28 files changed, 185 insertions, 286 deletions

diff --git a/arch/arm/mach-s3c2400/gpio.c b/arch/arm/mach-s3c2400/gpio.c
index 7a7ed4174c8c..81ebe2f09901 100644
--- a/arch/arm/mach-s3c2400/gpio.c
+++ b/arch/arm/mach-s3c2400/gpio.c
@@ -33,10 +33,10 @@
 
 int s3c2400_gpio_getirq(unsigned int pin)
 {
-        if (pin < S3C2410_GPE0 || pin > S3C2400_GPE7_EINT7)
+        if (pin < S3C2410_GPE(0) || pin > S3C2400_GPE7_EINT7)
                 return -1;  /* not valid interrupts */
 
-        return (pin - S3C2410_GPE0) + IRQ_EINT0;
+        return (pin - S3C2410_GPE(0)) + IRQ_EINT0;
 }
 
 EXPORT_SYMBOL(s3c2400_gpio_getirq);
diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
index 36a3132f39e7..bf7fbfe7e4d8 100644
--- a/arch/arm/mach-s3c2410/gpio.c
+++ b/arch/arm/mach-s3c2410/gpio.c
@@ -39,12 +39,12 @@ int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
         unsigned long flags;
         unsigned long val;
 
-        if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15)
+        if (pin < S3C2410_GPG(8) || pin > S3C2410_GPG(15))
                 return -1;
 
         config &= 0xff;
 
-        pin -= S3C2410_GPG8;
+        pin -= S3C2410_GPG(8);
         reg += pin & ~3;
 
         local_irq_save(flags);
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c
index 9bbea8a73ddc..5aabf117cbb0 100644
--- a/arch/arm/mach-s3c2410/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c
@@ -43,9 +43,9 @@ static void h1940bt_enable(int on)
                 h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
                 /* Reset the chip */
                 mdelay(10);
-                s3c2410_gpio_setpin(S3C2410_GPH1, 1);
+                s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
                 mdelay(10);
-                s3c2410_gpio_setpin(S3C2410_GPH1, 0);
+                s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
 
                 state = 1;
         }
@@ -54,9 +54,9 @@ static void h1940bt_enable(int on)
                 led_trigger_event(bt_led_trigger, 0);
 #endif
 
-                s3c2410_gpio_setpin(S3C2410_GPH1, 1);
+                s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
                 mdelay(10);
-                s3c2410_gpio_setpin(S3C2410_GPH1, 0);
+                s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
                 mdelay(10);
                 h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0);
 
@@ -89,14 +89,14 @@ static DEVICE_ATTR(enable, 0644,
 static int __init h1940bt_probe(struct platform_device *pdev)
 {
         /* Configures BT serial port GPIOs */
-        s3c2410_gpio_cfgpin(S3C2410_GPH0, S3C2410_GPH0_nCTS0);
-        s3c2410_gpio_pullup(S3C2410_GPH0, 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_pullup(S3C2410_GPH1, 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPH2, S3C2410_GPH2_TXD0);
-        s3c2410_gpio_pullup(S3C2410_GPH2, 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPH3, S3C2410_GPH3_RXD0);
-        s3c2410_gpio_pullup(S3C2410_GPH3, 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
+        s3c2410_gpio_pullup(S3C2410_GPH(0), 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_pullup(S3C2410_GPH(1), 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0);
+        s3c2410_gpio_pullup(S3C2410_GPH(2), 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
+        s3c2410_gpio_pullup(S3C2410_GPH(3), 1);
 
 #ifdef CONFIG_LEDS_H1940
         led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger);
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
index 6c9fbb99ef14..8fe192081d3a 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-core.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
@@ -24,7 +24,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
 {
         struct s3c_gpio_chip *chip;
 
-        if (pin > S3C2410_GPG10)
+        if (pin > S3C2410_GPG(10))
                 return NULL;
 
         chip = &s3c24xx_gpios[pin/32];
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
index b4f39558beda..801dff13858d 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
@@ -30,8 +30,8 @@
  * set the configuration of the given pin to the value passed.
  *
  * eg:
- *    s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);
- *    s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
+ *    s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
+ *    s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
 */
 
 extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
@@ -80,8 +80,8 @@ extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
  *
  * eg;
  *
- *   s3c2410_gpio_pullup(S3C2410_GPB0, 0);
- *   s3c2410_gpio_pullup(S3C2410_GPE8, 0);
+ *   s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
+ *   s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
 */
 
 extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
index 5213e453df1c..2edbb9c88ab3 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
@@ -68,5 +68,26 @@ enum s3c_gpio_number {
 #define S3C2410_GPG(_nr)        (S3C2410_GPIO_G_START + (_nr))
 #define S3C2410_GPH(_nr)        (S3C2410_GPIO_H_START + (_nr))
 
+/* compatibility until drivers can be modified */
+
+#define S3C2410_GPA0    S3C2410_GPA(0)
+#define S3C2410_GPA1    S3C2410_GPA(1)
+#define S3C2410_GPA3    S3C2410_GPA(3)
+#define S3C2410_GPA7    S3C2410_GPA(7)
+
+#define S3C2410_GPE0    S3C2410_GPE(0)
+#define S3C2410_GPE1    S3C2410_GPE(1)
+#define S3C2410_GPE2    S3C2410_GPE(2)
+#define S3C2410_GPE3    S3C2410_GPE(3)
+#define S3C2410_GPE4    S3C2410_GPE(4)
+#define S3C2410_GPE5    S3C2410_GPE(5)
+#define S3C2410_GPE6    S3C2410_GPE(6)
+#define S3C2410_GPE7    S3C2410_GPE(7)
+#define S3C2410_GPE8    S3C2410_GPE(8)
+#define S3C2410_GPE9    S3C2410_GPE(9)
+#define S3C2410_GPE10   S3C2410_GPE(10)
+
+#define S3C2410_GPH10   S3C2410_GPH(10)
+
 #endif /* __MACH_GPIONRS_H */
 
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index 90cefebd2937..b278d0c45ccf 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -69,81 +69,58 @@
 #define S3C2400_GPACON     S3C2410_GPIOREG(0x00)
 #define S3C2400_GPADAT     S3C2410_GPIOREG(0x04)
 
-#define S3C2410_GPA0         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
 #define S3C2410_GPA0_ADDR0   (1<<0)
 
-#define S3C2410_GPA1         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
 #define S3C2410_GPA1_ADDR16  (1<<1)
 
-#define S3C2410_GPA2         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
 #define S3C2410_GPA2_ADDR17  (1<<2)
 
-#define S3C2410_GPA3         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
 #define S3C2410_GPA3_ADDR18  (1<<3)
 
-#define S3C2410_GPA4         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
 #define S3C2410_GPA4_ADDR19  (1<<4)
 
-#define S3C2410_GPA5         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
 #define S3C2410_GPA5_ADDR20  (1<<5)
 
-#define S3C2410_GPA6         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
 #define S3C2410_GPA6_ADDR21  (1<<6)
 
-#define S3C2410_GPA7         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
 #define S3C2410_GPA7_ADDR22  (1<<7)
 
-#define S3C2410_GPA8         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
 #define S3C2410_GPA8_ADDR23  (1<<8)
 
-#define S3C2410_GPA9         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
 #define S3C2410_GPA9_ADDR24  (1<<9)
 
-#define S3C2410_GPA10        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
 #define S3C2410_GPA10_ADDR25 (1<<10)
 #define S3C2400_GPA10_SCKE   (1<<10)
 
-#define S3C2410_GPA11        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
 #define S3C2410_GPA11_ADDR26 (1<<11)
 #define S3C2400_GPA11_nCAS0  (1<<11)
 
-#define S3C2410_GPA12        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
 #define S3C2410_GPA12_nGCS1  (1<<12)
 #define S3C2400_GPA12_nCAS1  (1<<12)
 
-#define S3C2410_GPA13        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
 #define S3C2410_GPA13_nGCS2  (1<<13)
 #define S3C2400_GPA13_nGCS1  (1<<13)
 
-#define S3C2410_GPA14        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
 #define S3C2410_GPA14_nGCS3  (1<<14)
 #define S3C2400_GPA14_nGCS2  (1<<14)
 
-#define S3C2410_GPA15        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
 #define S3C2410_GPA15_nGCS4  (1<<15)
 #define S3C2400_GPA15_nGCS3  (1<<15)
 
-#define S3C2410_GPA16        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
 #define S3C2410_GPA16_nGCS5  (1<<16)
 #define S3C2400_GPA16_nGCS4  (1<<16)
 
-#define S3C2410_GPA17        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
 #define S3C2410_GPA17_CLE    (1<<17)
 #define S3C2400_GPA17_nGCS5  (1<<17)
 
-#define S3C2410_GPA18        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
 #define S3C2410_GPA18_ALE    (1<<18)
 
-#define S3C2410_GPA19        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
 #define S3C2410_GPA19_nFWE   (1<<19)
 
-#define S3C2410_GPA20        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
 #define S3C2410_GPA20_nFRE   (1<<20)
 
-#define S3C2410_GPA21        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
 #define S3C2410_GPA21_nRSTOUT (1<<21)
 
-#define S3C2410_GPA22        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
 #define S3C2410_GPA22_nFCE   (1<<22)
 
 /* 0x08 and 0x0c are reserved on S3C2410 */
@@ -171,85 +148,69 @@
 
 /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
 
-#define S3C2410_GPB0         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
 #define S3C2410_GPB0_TOUT0   (0x02 << 0)
 #define S3C2400_GPB0_DATA16  (0x02 << 0)
 
-#define S3C2410_GPB1         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
 #define S3C2410_GPB1_TOUT1   (0x02 << 2)
 #define S3C2400_GPB1_DATA17  (0x02 << 2)
 
-#define S3C2410_GPB2         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
 #define S3C2410_GPB2_TOUT2   (0x02 << 4)
 #define S3C2400_GPB2_DATA18  (0x02 << 4)
 #define S3C2400_GPB2_TCLK1   (0x03 << 4)
 
-#define S3C2410_GPB3         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
 #define S3C2410_GPB3_TOUT3   (0x02 << 6)
 #define S3C2400_GPB3_DATA19  (0x02 << 6)
 #define S3C2400_GPB3_TXD1    (0x03 << 6)
 
-#define S3C2410_GPB4         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
 #define S3C2410_GPB4_TCLK0   (0x02 << 8)
 #define S3C2400_GPB4_DATA20  (0x02 << 8)
 #define S3C2410_GPB4_MASK    (0x03 << 8)
 #define S3C2400_GPB4_RXD1    (0x03 << 8)
 #define S3C2400_GPB4_MASK    (0x03 << 8)
 
-#define S3C2410_GPB5         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
 #define S3C2410_GPB5_nXBACK  (0x02 << 10)
 #define S3C2443_GPB5_XBACK   (0x03 << 10)
 #define S3C2400_GPB5_DATA21  (0x02 << 10)
 #define S3C2400_GPB5_nCTS1   (0x03 << 10)
 
-#define S3C2410_GPB6         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
 #define S3C2410_GPB6_nXBREQ  (0x02 << 12)
 #define S3C2443_GPB6_XBREQ   (0x03 << 12)
 #define S3C2400_GPB6_DATA22  (0x02 << 12)
 #define S3C2400_GPB6_nRTS1   (0x03 << 12)
 
-#define S3C2410_GPB7         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
 #define S3C2410_GPB7_nXDACK1 (0x02 << 14)
 #define S3C2443_GPB7_XDACK1  (0x03 << 14)
 #define S3C2400_GPB7_DATA23  (0x02 << 14)
 
-#define S3C2410_GPB8         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
 #define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
 #define S3C2400_GPB8_DATA24  (0x02 << 16)
 
-#define S3C2410_GPB9         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
 #define S3C2410_GPB9_nXDACK0 (0x02 << 18)
 #define S3C2443_GPB9_XDACK0  (0x03 << 18)
 #define S3C2400_GPB9_DATA25  (0x02 << 18)
 #define S3C2400_GPB9_I2SSDI  (0x03 << 18)
 
-#define S3C2410_GPB10        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
 #define S3C2410_GPB10_nXDRE0 (0x02 << 20)
 #define S3C2443_GPB10_XDREQ0 (0x03 << 20)
 #define S3C2400_GPB10_DATA26 (0x02 << 20)
 #define S3C2400_GPB10_nSS    (0x03 << 20)
 
-#define S3C2400_GPB11        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11)
 #define S3C2400_GPB11_INP    (0x00 << 22)
 #define S3C2400_GPB11_OUTP   (0x01 << 22)
 #define S3C2400_GPB11_DATA27 (0x02 << 22)
 
-#define S3C2400_GPB12        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12)
 #define S3C2400_GPB12_INP    (0x00 << 24)
 #define S3C2400_GPB12_OUTP   (0x01 << 24)
 #define S3C2400_GPB12_DATA28 (0x02 << 24)
 
-#define S3C2400_GPB13        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13)
 #define S3C2400_GPB13_INP    (0x00 << 26)
 #define S3C2400_GPB13_OUTP   (0x01 << 26)
 #define S3C2400_GPB13_DATA29 (0x02 << 26)
 
-#define S3C2400_GPB14        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14)
 #define S3C2400_GPB14_INP    (0x00 << 28)
 #define S3C2400_GPB14_OUTP   (0x01 << 28)
 #define S3C2400_GPB14_DATA30 (0x02 << 28)
 
-#define S3C2400_GPB15        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15)
 #define S3C2400_GPB15_INP    (0x00 << 30)
 #define S3C2400_GPB15_OUTP   (0x01 << 30)
 #define S3C2400_GPB15_DATA31 (0x02 << 30)
@@ -270,67 +231,51 @@
 #define S3C2400_GPCDAT     S3C2410_GPIOREG(0x18)
 #define S3C2400_GPCUP      S3C2410_GPIOREG(0x1C)
 
-#define S3C2410_GPC0            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
 #define S3C2410_GPC0_LEND       (0x02 << 0)
 #define S3C2400_GPC0_VD0        (0x02 << 0)
 
-#define S3C2410_GPC1            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
 #define S3C2410_GPC1_VCLK       (0x02 << 2)
 #define S3C2400_GPC1_VD1        (0x02 << 2)
 
-#define S3C2410_GPC2            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
 #define S3C2410_GPC2_VLINE      (0x02 << 4)
 #define S3C2400_GPC2_VD2        (0x02 << 4)
 
-#define S3C2410_GPC3            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
 #define S3C2410_GPC3_VFRAME     (0x02 << 6)
 #define S3C2400_GPC3_VD3        (0x02 << 6)
 
-#define S3C2410_GPC4            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
 #define S3C2410_GPC4_VM         (0x02 << 8)
 #define S3C2400_GPC4_VD4        (0x02 << 8)
 
-#define S3C2410_GPC5            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
 #define S3C2410_GPC5_LCDVF0     (0x02 << 10)
 #define S3C2400_GPC5_VD5        (0x02 << 10)
 
-#define S3C2410_GPC6            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
 #define S3C2410_GPC6_LCDVF1     (0x02 << 12)
 #define S3C2400_GPC6_VD6        (0x02 << 12)
 
-#define S3C2410_GPC7            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
 #define S3C2410_GPC7_LCDVF2     (0x02 << 14)
 #define S3C2400_GPC7_VD7        (0x02 << 14)
 
-#define S3C2410_GPC8            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
 #define S3C2410_GPC8_VD0        (0x02 << 16)
 #define S3C2400_GPC8_VD8        (0x02 << 16)
 
-#define S3C2410_GPC9            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
 #define S3C2410_GPC9_VD1        (0x02 << 18)
 #define S3C2400_GPC9_VD9        (0x02 << 18)
 
-#define S3C2410_GPC10           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
 #define S3C2410_GPC10_VD2       (0x02 << 20)
 #define S3C2400_GPC10_VD10      (0x02 << 20)
 
-#define S3C2410_GPC11           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
 #define S3C2410_GPC11_VD3       (0x02 << 22)
 #define S3C2400_GPC11_VD11      (0x02 << 22)
 
-#define S3C2410_GPC12           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
 #define S3C2410_GPC12_VD4       (0x02 << 24)
 #define S3C2400_GPC12_VD12      (0x02 << 24)
 
-#define S3C2410_GPC13           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
 #define S3C2410_GPC13_VD5       (0x02 << 26)
 #define S3C2400_GPC13_VD13      (0x02 << 26)
 
-#define S3C2410_GPC14           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
 #define S3C2410_GPC14_VD6       (0x02 << 28)
 #define S3C2400_GPC14_VD14      (0x02 << 28)
 
-#define S3C2410_GPC15           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
 #define S3C2410_GPC15_VD7       (0x02 << 30)
 #define S3C2400_GPC15_VD15      (0x02 << 30)
 
@@ -355,67 +300,51 @@
 #define S3C2400_GPDDAT     S3C2410_GPIOREG(0x24)
 #define S3C2400_GPDUP      S3C2410_GPIOREG(0x28)
 
-#define S3C2410_GPD0            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
 #define S3C2410_GPD0_VD8        (0x02 << 0)
 #define S3C2400_GPD0_VFRAME     (0x02 << 0)
 #define S3C2442_GPD0_nSPICS1    (0x03 << 0)
 
-#define S3C2410_GPD1            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
 #define S3C2410_GPD1_VD9        (0x02 << 2)
 #define S3C2400_GPD1_VM         (0x02 << 2)
 #define S3C2442_GPD1_SPICLK1    (0x03 << 2)
 
-#define S3C2410_GPD2            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
 #define S3C2410_GPD2_VD10       (0x02 << 4)
 #define S3C2400_GPD2_VLINE      (0x02 << 4)
 
-#define S3C2410_GPD3            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
 #define S3C2410_GPD3_VD11       (0x02 << 6)
 #define S3C2400_GPD3_VCLK       (0x02 << 6)
 
-#define S3C2410_GPD4            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
 #define S3C2410_GPD4_VD12       (0x02 << 8)
 #define S3C2400_GPD4_LEND       (0x02 << 8)
 
-#define S3C2410_GPD5            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
 #define S3C2410_GPD5_VD13       (0x02 << 10)
 #define S3C2400_GPD5_TOUT0      (0x02 << 10)
 
-#define S3C2410_GPD6            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
 #define S3C2410_GPD6_VD14       (0x02 << 12)
 #define S3C2400_GPD6_TOUT1      (0x02 << 12)
 
-#define S3C2410_GPD7            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
 #define S3C2410_GPD7_VD15       (0x02 << 14)
 #define S3C2400_GPD7_TOUT2      (0x02 << 14)
 
-#define S3C2410_GPD8            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
 #define S3C2410_GPD8_VD16       (0x02 << 16)
 #define S3C2400_GPD8_TOUT3      (0x02 << 16)
 
-#define S3C2410_GPD9            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
 #define S3C2410_GPD9_VD17       (0x02 << 18)
 #define S3C2400_GPD9_TCLK0      (0x02 << 18)
 #define S3C2410_GPD9_MASK       (0x03 << 18)
 
-#define S3C2410_GPD10           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
 #define S3C2410_GPD10_VD18      (0x02 << 20)
 #define S3C2400_GPD10_nWAIT     (0x02 << 20)
 
-#define S3C2410_GPD11           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
 #define S3C2410_GPD11_VD19      (0x02 << 22)
 
-#define S3C2410_GPD12           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
 #define S3C2410_GPD12_VD20      (0x02 << 24)
 
-#define S3C2410_GPD13           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
 #define S3C2410_GPD13_VD21      (0x02 << 26)
 
-#define S3C2410_GPD14           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
 #define S3C2410_GPD14_VD22      (0x02 << 28)
 #define S3C2410_GPD14_nSS1      (0x03 << 28)
 
-#define S3C2410_GPD15           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
 #define S3C2410_GPD15_VD23      (0x02 << 30)
 #define S3C2410_GPD15_nSS0      (0x03 << 30)
 
@@ -441,26 +370,22 @@
 #define S3C2400_GPEDAT     S3C2410_GPIOREG(0x30)
 #define S3C2400_GPEUP      S3C2410_GPIOREG(0x34)
 
-#define S3C2410_GPE0           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
 #define S3C2410_GPE0_I2SLRCK   (0x02 << 0)
 #define S3C2443_GPE0_AC_nRESET (0x03 << 0)
 #define S3C2400_GPE0_EINT0     (0x02 << 0)
 #define S3C2410_GPE0_MASK      (0x03 << 0)
 
-#define S3C2410_GPE1           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
 #define S3C2410_GPE1_I2SSCLK   (0x02 << 2)
 #define S3C2443_GPE1_AC_SYNC   (0x03 << 2)
 #define S3C2400_GPE1_EINT1     (0x02 << 2)
 #define S3C2400_GPE1_nSS       (0x03 << 2)
 #define S3C2410_GPE1_MASK      (0x03 << 2)
 
-#define S3C2410_GPE2           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
 #define S3C2410_GPE2_CDCLK     (0x02 << 4)
 #define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
 #define S3C2400_GPE2_EINT2     (0x02 << 4)
 #define S3C2400_GPE2_I2SSDI    (0x03 << 4)
 
-#define S3C2410_GPE3           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
 #define S3C2410_GPE3_I2SSDI    (0x02 << 6)
 #define S3C2443_GPE3_AC_SDI    (0x03 << 6)
 #define S3C2400_GPE3_EINT3     (0x02 << 6)
@@ -468,7 +393,6 @@
 #define S3C2410_GPE3_nSS0      (0x03 << 6)
 #define S3C2410_GPE3_MASK      (0x03 << 6)
 
-#define S3C2410_GPE4           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
 #define S3C2410_GPE4_I2SSDO    (0x02 << 8)
 #define S3C2443_GPE4_AC_SDO    (0x03 << 8)
 #define S3C2400_GPE4_EINT4     (0x02 << 8)
@@ -476,59 +400,48 @@
 #define S3C2410_GPE4_I2SSDI    (0x03 << 8)
 #define S3C2410_GPE4_MASK      (0x03 << 8)
 
-#define S3C2410_GPE5           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
 #define S3C2410_GPE5_SDCLK     (0x02 << 10)
 #define S3C2443_GPE5_SD1_CLK   (0x02 << 10)
 #define S3C2400_GPE5_EINT5     (0x02 << 10)
 #define S3C2400_GPE5_TCLK1     (0x03 << 10)
 
-#define S3C2410_GPE6           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
 #define S3C2410_GPE6_SDCMD     (0x02 << 12)
 #define S3C2443_GPE6_SD1_CMD   (0x02 << 12)
 #define S3C2443_GPE6_AC_BITCLK (0x03 << 12)
 #define S3C2400_GPE6_EINT6     (0x02 << 12)
 
-#define S3C2410_GPE7           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
 #define S3C2410_GPE7_SDDAT0    (0x02 << 14)
 #define S3C2443_GPE5_SD1_DAT0  (0x02 << 14)
 #define S3C2443_GPE7_AC_SDI    (0x03 << 14)
 #define S3C2400_GPE7_EINT7     (0x02 << 14)
 
-#define S3C2410_GPE8           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
 #define S3C2410_GPE8_SDDAT1    (0x02 << 16)
 #define S3C2443_GPE8_SD1_DAT1  (0x02 << 16)
 #define S3C2443_GPE8_AC_SDO    (0x03 << 16)
 #define S3C2400_GPE8_nXDACK0   (0x02 << 16)
 
-#define S3C2410_GPE9           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
 #define S3C2410_GPE9_SDDAT2    (0x02 << 18)
 #define S3C2443_GPE9_SD1_DAT2  (0x02 << 18)
 #define S3C2443_GPE9_AC_SYNC   (0x03 << 18)
 #define S3C2400_GPE9_nXDACK1   (0x02 << 18)
 #define S3C2400_GPE9_nXBACK    (0x03 << 18)
 
-#define S3C2410_GPE10          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
 #define S3C2410_GPE10_SDDAT3   (0x02 << 20)
 #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
 #define S3C2443_GPE10_AC_nRESET (0x03 << 20)
 #define S3C2400_GPE10_nXDREQ0  (0x02 << 20)
 
-#define S3C2410_GPE11          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
 #define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
 #define S3C2400_GPE11_nXDREQ1  (0x02 << 22)
 #define S3C2400_GPE11_nXBREQ   (0x03 << 22)
 
-#define S3C2410_GPE12          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
 #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
 
-#define S3C2410_GPE13          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
 #define S3C2410_GPE13_SPICLK0  (0x02 << 26)
 
-#define S3C2410_GPE14          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
 #define S3C2410_GPE14_IICSCL   (0x02 << 28)
 #define S3C2410_GPE14_MASK     (0x03 << 28)
 
-#define S3C2410_GPE15          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
 #define S3C2410_GPE15_IICSDA   (0x02 << 30)
 #define S3C2410_GPE15_MASK     (0x03 << 30)
 
@@ -564,39 +477,31 @@
 #define S3C2400_GPFDAT     S3C2410_GPIOREG(0x3C)
 #define S3C2400_GPFUP      S3C2410_GPIOREG(0x40)
 
-#define S3C2410_GPF0        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
 #define S3C2410_GPF0_EINT0  (0x02 << 0)
 #define S3C2400_GPF0_RXD0   (0x02 << 0)
 
-#define S3C2410_GPF1        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
 #define S3C2410_GPF1_EINT1  (0x02 << 2)
 #define S3C2400_GPF1_RXD1   (0x02 << 2)
 #define S3C2400_GPF1_IICSDA (0x03 << 2)
 
-#define S3C2410_GPF2        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
 #define S3C2410_GPF2_EINT2  (0x02 << 4)
 #define S3C2400_GPF2_TXD0   (0x02 << 4)
 
-#define S3C2410_GPF3        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
 #define S3C2410_GPF3_EINT3  (0x02 << 6)
 #define S3C2400_GPF3_TXD1   (0x02 << 6)
 #define S3C2400_GPF3_IICSCL (0x03 << 6)
 
-#define S3C2410_GPF4        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
 #define S3C2410_GPF4_EINT4  (0x02 << 8)
 #define S3C2400_GPF4_nRTS0  (0x02 << 8)
 #define S3C2400_GPF4_nXBACK (0x03 << 8)
 
-#define S3C2410_GPF5        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
 #define S3C2410_GPF5_EINT5  (0x02 << 10)
 #define S3C2400_GPF5_nCTS0  (0x02 << 10)
 #define S3C2400_GPF5_nXBREQ (0x03 << 10)
 
-#define S3C2410_GPF6        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
 #define S3C2410_GPF6_EINT6  (0x02 << 12)
 #define S3C2400_GPF6_CLKOUT (0x02 << 12)
 
-#define S3C2410_GPF7        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
 #define S3C2410_GPF7_EINT7  (0x02 << 14)
 
 #define S3C2410_GPF_PUPDIS(x)  (1<<(x))
@@ -621,85 +526,69 @@
 #define S3C2400_GPGDAT     S3C2410_GPIOREG(0x48)
 #define S3C2400_GPGUP      S3C2410_GPIOREG(0x4C)
 
-#define S3C2410_GPG0          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
 #define S3C2410_GPG0_EINT8    (0x02 << 0)
 #define S3C2400_GPG0_I2SLRCK  (0x02 << 0)
 
-#define S3C2410_GPG1          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
 #define S3C2410_GPG1_EINT9    (0x02 << 2)
 #define S3C2400_GPG1_I2SSCLK  (0x02 << 2)
 
-#define S3C2410_GPG2          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
 #define S3C2410_GPG2_EINT10   (0x02 << 4)
 #define S3C2410_GPG2_nSS0     (0x03 << 4)
 #define S3C2400_GPG2_CDCLK    (0x02 << 4)
 
-#define S3C2410_GPG3          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
 #define S3C2410_GPG3_EINT11   (0x02 << 6)
 #define S3C2410_GPG3_nSS1     (0x03 << 6)
 #define S3C2400_GPG3_I2SSDO   (0x02 << 6)
 #define S3C2400_GPG3_I2SSDI   (0x03 << 6)
 
-#define S3C2410_GPG4          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
 #define S3C2410_GPG4_EINT12   (0x02 << 8)
 #define S3C2400_GPG4_MMCCLK   (0x02 << 8)
 #define S3C2400_GPG4_I2SSDI   (0x03 << 8)
 #define S3C2410_GPG4_LCDPWREN (0x03 << 8)
 #define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
 
-#define S3C2410_GPG5          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
 #define S3C2410_GPG5_EINT13   (0x02 << 10)
 #define S3C2400_GPG5_MMCCMD   (0x02 << 10)
 #define S3C2400_GPG5_IICSDA   (0x03 << 10)
 #define S3C2410_GPG5_SPIMISO1 (0x03 << 10)      /* not s3c2443 */
 
-#define S3C2410_GPG6          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
 #define S3C2410_GPG6_EINT14   (0x02 << 12)
 #define S3C2400_GPG6_MMCDAT   (0x02 << 12)
 #define S3C2400_GPG6_IICSCL   (0x03 << 12)
 #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
 
-#define S3C2410_GPG7          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
 #define S3C2410_GPG7_EINT15   (0x02 << 14)
 #define S3C2410_GPG7_SPICLK1  (0x03 << 14)
 #define S3C2400_GPG7_SPIMISO  (0x02 << 14)
 #define S3C2400_GPG7_IICSDA   (0x03 << 14)
 
-#define S3C2410_GPG8          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
 #define S3C2410_GPG8_EINT16   (0x02 << 16)
 #define S3C2400_GPG8_SPIMOSI  (0x02 << 16)
 #define S3C2400_GPG8_IICSCL   (0x03 << 16)
 
-#define S3C2410_GPG9          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
 #define S3C2410_GPG9_EINT17   (0x02 << 18)
 #define S3C2400_GPG9_SPICLK   (0x02 << 18)
 #define S3C2400_GPG9_MMCCLK   (0x03 << 18)
 
-#define S3C2410_GPG10         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
 #define S3C2410_GPG10_EINT18  (0x02 << 20)
 
-#define S3C2410_GPG11         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)
 #define S3C2410_GPG11_EINT19  (0x02 << 22)
 #define S3C2410_GPG11_TCLK1   (0x03 << 22)
 #define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
 
-#define S3C2410_GPG12         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
 #define S3C2410_GPG12_EINT20  (0x02 << 24)
 #define S3C2410_GPG12_XMON    (0x03 << 24)
 #define S3C2442_GPG12_nSPICS0 (0x03 << 24)
 #define S3C2443_GPG12_nINPACK (0x03 << 24)
 
-#define S3C2410_GPG13         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
 #define S3C2410_GPG13_EINT21  (0x02 << 26)
 #define S3C2410_GPG13_nXPON   (0x03 << 26)
 #define S3C2443_GPG13_CF_nREG (0x03 << 26)
 
-#define S3C2410_GPG14         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
 #define S3C2410_GPG14_EINT22  (0x02 << 28)
 #define S3C2410_GPG14_YMON    (0x03 << 28)
 #define S3C2443_GPG14_CF_RESET (0x03 << 28)
 
-#define S3C2410_GPG15         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
 #define S3C2410_GPG15_EINT23  (0x02 << 30)
 #define S3C2410_GPG15_nYPON   (0x03 << 30)
 #define S3C2443_GPG15_CF_PWR  (0x03 << 30)
@@ -718,40 +607,29 @@
 #define S3C2410_GPHDAT     S3C2410_GPIOREG(0x74)
 #define S3C2410_GPHUP      S3C2410_GPIOREG(0x78)
 
-#define S3C2410_GPH0        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
 #define S3C2410_GPH0_nCTS0  (0x02 << 0)
 
-#define S3C2410_GPH1        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
 #define S3C2410_GPH1_nRTS0  (0x02 << 2)
 
-#define S3C2410_GPH2        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
 #define S3C2410_GPH2_TXD0   (0x02 << 4)
 
-#define S3C2410_GPH3        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
 #define S3C2410_GPH3_RXD0   (0x02 << 6)
 
-#define S3C2410_GPH4        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
 #define S3C2410_GPH4_TXD1   (0x02 << 8)
 
-#define S3C2410_GPH5        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
 #define S3C2410_GPH5_RXD1   (0x02 << 10)
 
-#define S3C2410_GPH6        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
 #define S3C2410_GPH6_TXD2   (0x02 << 12)
 #define S3C2410_GPH6_nRTS1  (0x03 << 12)
 
-#define S3C2410_GPH7        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
 #define S3C2410_GPH7_RXD2   (0x02 << 14)
 #define S3C2410_GPH7_nCTS1  (0x03 << 14)
 
-#define S3C2410_GPH8        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
 #define S3C2410_GPH8_UCLK   (0x02 << 16)
 
-#define S3C2410_GPH9          S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
 #define S3C2410_GPH9_CLKOUT0  (0x02 << 18)
 #define S3C2442_GPH9_nSPICS0  (0x03 << 18)
 
-#define S3C2410_GPH10         S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
 #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
 
 /* The S3C2412 and S3C2413 move the GPJ register set to after
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 43f7536c5291..06a84adfb13f 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -225,8 +225,8 @@ static void amlm5900_init_pm(void)
         } else {
                 enable_irq_wake(IRQ_EINT9);
                 /* configure the suspend/resume status pin */
-                s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPIO_OUTPUT);
-                s3c2410_gpio_pullup(S3C2410_GPF2, 0);
+                s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
+                s3c2410_gpio_pullup(S3C2410_GPF(2), 0);
         }
 }
 static void __init amlm5900_init(void)
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 3410caefb869..496463768de7 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -213,15 +213,15 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
 static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
 {
         /* ensure that an nRESET is not generated on resume. */
-        s3c2410_gpio_setpin(S3C2410_GPA21, 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
 
         return 0;
 }
 
 static int bast_pm_resume(struct sys_device *sd)
 {
-        s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
         return 0;
 }
 
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 7a7c4da4c256..d9cd5ddecf4a 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -127,7 +127,7 @@ static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd)
 
 static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = {
         .udc_command            = h1940_udc_pullup,
-        .vbus_pin               = S3C2410_GPG5,
+        .vbus_pin               = S3C2410_GPG(5),
         .vbus_pin_inverted      = 1,
 };
 
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 83705036ca6b..0f6ed61af415 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -86,10 +86,10 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
 {
         switch (cmd) {
         case S3C2410_UDC_P_ENABLE :
-                s3c2410_gpio_setpin(S3C2410_GPB3, 1);
+                s3c2410_gpio_setpin(S3C2410_GPB(3), 1);
                 break;
         case S3C2410_UDC_P_DISABLE :
-                s3c2410_gpio_setpin(S3C2410_GPB3, 0);
+                s3c2410_gpio_setpin(S3C2410_GPB(3), 0);
                 break;
         case S3C2410_UDC_P_RESET :
                 break;
@@ -100,55 +100,55 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
 
 static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = {
         .udc_command            = n30_udc_pullup,
-        .vbus_pin               = S3C2410_GPG1,
+        .vbus_pin               = S3C2410_GPG(1),
         .vbus_pin_inverted      = 0,
 };
 
 static struct gpio_keys_button n30_buttons[] = {
         {
-                .gpio           = S3C2410_GPF0,
+                .gpio           = S3C2410_GPF(0),
                 .code           = KEY_POWER,
                 .desc           = "Power",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPG9,
+                .gpio           = S3C2410_GPG(9),
                 .code           = KEY_UP,
                 .desc           = "Thumbwheel Up",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPG8,
+                .gpio           = S3C2410_GPG(8),
                 .code           = KEY_DOWN,
                 .desc           = "Thumbwheel Down",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPG7,
+                .gpio           = S3C2410_GPG(7),
                 .code           = KEY_ENTER,
                 .desc           = "Thumbwheel Press",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPF7,
+                .gpio           = S3C2410_GPF(7),
                 .code           = KEY_HOMEPAGE,
                 .desc           = "Home",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPF6,
+                .gpio           = S3C2410_GPF(6),
                 .code           = KEY_CALENDAR,
                 .desc           = "Calendar",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPF5,
+                .gpio           = S3C2410_GPF(5),
                 .code           = KEY_ADDRESSBOOK,
                 .desc           = "Contacts",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPF4,
+                .gpio           = S3C2410_GPF(4),
                 .code           = KEY_MAIL,
                 .desc           = "Mail",
                 .active_low     = 0,
@@ -170,73 +170,73 @@ static struct platform_device n30_button_device = {
 
 static struct gpio_keys_button n35_buttons[] = {
         {
-                .gpio           = S3C2410_GPF0,
+                .gpio           = S3C2410_GPF(0),
                 .code           = KEY_POWER,
                 .desc           = "Power",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPG9,
+                .gpio           = S3C2410_GPG(9),
                 .code           = KEY_UP,
                 .desc           = "Joystick Up",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPG8,
+                .gpio           = S3C2410_GPG(8),
                 .code           = KEY_DOWN,
                 .desc           = "Joystick Down",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPG6,
+                .gpio           = S3C2410_GPG(6),
                 .code           = KEY_DOWN,
                 .desc           = "Joystick Left",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPG5,
+                .gpio           = S3C2410_GPG(5),
                 .code           = KEY_DOWN,
                 .desc           = "Joystick Right",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPG7,
+                .gpio           = S3C2410_GPG(7),
                 .code           = KEY_ENTER,
                 .desc           = "Joystick Press",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPF7,
+                .gpio           = S3C2410_GPF(7),
                 .code           = KEY_HOMEPAGE,
                 .desc           = "Home",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPF6,
+                .gpio           = S3C2410_GPF(6),
                 .code           = KEY_CALENDAR,
                 .desc           = "Calendar",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPF5,
+                .gpio           = S3C2410_GPF(5),
                 .code           = KEY_ADDRESSBOOK,
                 .desc           = "Contacts",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPF4,
+                .gpio           = S3C2410_GPF(4),
                 .code           = KEY_MAIL,
                 .desc           = "Mail",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPF3,
+                .gpio           = S3C2410_GPF(3),
                 .code           = SW_RADIO,
                 .desc           = "GPS Antenna",
                 .active_low     = 0,
         },
         {
-                .gpio           = S3C2410_GPG2,
+                .gpio           = S3C2410_GPG(2),
                 .code           = SW_HEADPHONE_INSERT,
                 .desc           = "Headphone",
                 .active_low     = 0,
@@ -260,7 +260,7 @@ static struct platform_device n35_button_device = {
 /* This is the bluetooth LED on the device. */
 static struct s3c24xx_led_platdata n30_blue_led_pdata = {
         .name           = "blue_led",
-        .gpio           = S3C2410_GPG6,
+        .gpio           = S3C2410_GPG(6),
         .def_trigger    = "",
 };
 
@@ -271,7 +271,7 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = {
 static struct s3c24xx_led_platdata n30_warning_led_pdata = {
         .name           = "warning_led",
         .flags          = S3C24XX_LEDF_ACTLOW,
-        .gpio           = S3C2410_GPD9,
+        .gpio           = S3C2410_GPD(9),
         .def_trigger    = "",
 };
 
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 7520aee3c9e1..2cc9849eb448 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -199,7 +199,7 @@ static struct platform_device qt2410_cs89x0 = {
 /* LED */
 
 static struct s3c24xx_led_platdata qt2410_pdata_led = {
-        .gpio           = S3C2410_GPB0,
+        .gpio           = S3C2410_GPB(0),
         .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
         .name           = "led",
         .def_trigger    = "timer",
@@ -219,18 +219,18 @@ static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
 {
         switch (cs) {
         case BITBANG_CS_ACTIVE:
-                s3c2410_gpio_setpin(S3C2410_GPB5, 0);
+                s3c2410_gpio_setpin(S3C2410_GPB(5), 0);
                 break;
         case BITBANG_CS_INACTIVE:
-                s3c2410_gpio_setpin(S3C2410_GPB5, 1);
+                s3c2410_gpio_setpin(S3C2410_GPB(5), 1);
                 break;
         }
 }
 
 static struct s3c2410_spigpio_info spi_gpio_cfg = {
-        .pin_clk        = S3C2410_GPG7,
-        .pin_mosi       = S3C2410_GPG6,
-        .pin_miso       = S3C2410_GPG5,
+        .pin_clk        = S3C2410_GPG(7),
+        .pin_mosi       = S3C2410_GPG(6),
+        .pin_miso       = S3C2410_GPG(5),
         .chip_select    = &spi_gpio_cs,
 };
 
@@ -347,13 +347,13 @@ static void __init qt2410_machine_init(void)
         }
         s3c24xx_fb_set_platdata(&qt2410_fb_info);
 
-        s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPB0, 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
 
         s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
         s3c_i2c0_set_platdata(NULL);
 
-        s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPB(5), S3C2410_GPIO_OUTPUT);
 
         platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
         s3c_pm_init();
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 0507a7ec18ce..1628cc773a2c 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -278,19 +278,19 @@ static struct platform_device vr1000_dm9k1 = {
 
 static struct s3c24xx_led_platdata vr1000_led1_pdata = {
         .name           = "led1",
-        .gpio           = S3C2410_GPB0,
+        .gpio           = S3C2410_GPB(0),
         .def_trigger    = "",
 };
 
 static struct s3c24xx_led_platdata vr1000_led2_pdata = {
         .name           = "led2",
-        .gpio           = S3C2410_GPB1,
+        .gpio           = S3C2410_GPB(1),
         .def_trigger    = "",
 };
 
 static struct s3c24xx_led_platdata vr1000_led3_pdata = {
         .name           = "led3",
-        .gpio           = S3C2410_GPB2,
+        .gpio           = S3C2410_GPB(2),
         .def_trigger    = "",
 };
 
@@ -356,8 +356,8 @@ static struct clk *vr1000_clocks[] __initdata = {
 
 static void vr1000_power_off(void)
 {
-        s3c2410_gpio_cfgpin(S3C2410_GPB9, S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPB9, 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPB(9), S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_setpin(S3C2410_GPB(9), 1);
 }
 
 static void __init vr1000_map_io(void)
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index 726cfc093886..143e08a599d4 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -77,7 +77,7 @@ static void s3c2410_pm_prepare(void)
         }
 
         if ( machine_is_aml_m5900() )
-                s3c2410_gpio_setpin(S3C2410_GPF2, 1);
+                s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
 
 }
 
@@ -92,7 +92,7 @@ static int s3c2410_pm_resume(struct sys_device *dev)
         __raw_writel(tmp, S3C2410_GSTATUS2);
 
         if ( machine_is_aml_m5900() )
-                s3c2410_gpio_setpin(S3C2410_GPF2, 0);
+                s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
 
         return 0;
 }
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c
index 506252b33fef..dd45eb4a6f0c 100644
--- a/arch/arm/mach-s3c2410/usb-simtec.c
+++ b/arch/arm/mach-s3c2410/usb-simtec.c
@@ -54,9 +54,9 @@ usb_simtec_powercontrol(int port, int to)
         power_state[port] = to;
 
         if (power_state[0] && power_state[1])
-                s3c2410_gpio_setpin(S3C2410_GPB4, 0);
+                s3c2410_gpio_setpin(S3C2410_GPB(4), 0);
         else
-                s3c2410_gpio_setpin(S3C2410_GPB4, 1);
+                s3c2410_gpio_setpin(S3C2410_GPB(4), 1);
 }
 
 static irqreturn_t
@@ -64,7 +64,7 @@ usb_simtec_ocirq(int irq, void *pw)
 {
         struct s3c2410_hcd_info *info = pw;
 
-        if (s3c2410_gpio_getpin(S3C2410_GPG10) == 0) {
+        if (s3c2410_gpio_getpin(S3C2410_GPG(10)) == 0) {
                 pr_debug("usb_simtec: over-current irq (oc detected)\n");
                 s3c2410_usb_report_oc(info, 3);
         } else {
@@ -110,7 +110,7 @@ int usb_simtec_init(void)
         printk("USB Power Control, (c) 2004 Simtec Electronics\n");
         s3c_device_usb.dev.platform_data = &usb_simtec_info;
 
-        s3c2410_gpio_cfgpin(S3C2410_GPB4, S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPB4, 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPB(4), S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_setpin(S3C2410_GPB(4), 1);
         return 0;
 }
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 56d12b56c9d9..8df506eac903 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -357,8 +357,8 @@ static void jive_lcm_reset(unsigned int set)
 {
         printk(KERN_DEBUG "%s(%d)\n", __func__, set);
 
-        s3c2410_gpio_setpin(S3C2410_GPG13, set);
-        s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_setpin(S3C2410_GPG(13), set);
+        s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
 }
 
 #undef LCD_UPPER_MARGIN
@@ -391,13 +391,13 @@ static struct ili9320_platdata jive_lcm_config = {
 
 static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
 {
-        s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1);
+        s3c2410_gpio_setpin(S3C2410_GPB(7), cs ? 0 : 1);
 }
 
 static struct s3c2410_spigpio_info jive_lcd_spi = {
         .bus_num        = 1,
-        .pin_clk        = S3C2410_GPG8,
-        .pin_mosi       = S3C2410_GPB8,
+        .pin_clk        = S3C2410_GPG(8),
+        .pin_mosi       = S3C2410_GPB(8),
         .num_chipselect = 1,
         .chip_select    = jive_lcd_spi_chipselect,
 };
@@ -413,13 +413,13 @@ static struct platform_device jive_device_lcdspi = {
 
 static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
 {
-        s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1);
+        s3c2410_gpio_setpin(S3C2410_GPH(10), cs ? 0 : 1);
 }
 
 static struct s3c2410_spigpio_info jive_wm8750_spi = {
         .bus_num        = 2,
-        .pin_clk        = S3C2410_GPB4,
-        .pin_mosi       = S3C2410_GPB9,
+        .pin_clk        = S3C2410_GPB(4),
+        .pin_mosi       = S3C2410_GPB(9),
         .num_chipselect = 1,
         .chip_select    = jive_wm8750_chipselect,
 };
@@ -480,7 +480,7 @@ static struct platform_device *jive_devices[] __initdata = {
 };
 
 static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
-        .vbus_pin       = S3C2410_GPG1,         /* detect is on GPG1 */
+        .vbus_pin       = S3C2410_GPG(1),               /* detect is on GPG1 */
 };
 
 /* Jive power management device */
@@ -530,8 +530,8 @@ static void jive_power_off(void)
 {
         printk(KERN_INFO "powering system down...\n");
 
-        s3c2410_gpio_setpin(S3C2410_GPC5, 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPC5, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
 }
 
 static void __init jive_machine_init(void)
@@ -635,22 +635,22 @@ static void __init jive_machine_init(void)
 
         /* initialise the spi */
 
-        s3c2410_gpio_setpin(S3C2410_GPG13, 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_setpin(S3C2410_GPG(13), 0);
+        s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
 
-        s3c2410_gpio_setpin(S3C2410_GPB7, 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_setpin(S3C2410_GPB(7), 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPB(7), S3C2410_GPIO_OUTPUT);
 
-        s3c2410_gpio_setpin(S3C2410_GPB6, 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
+        s3c2410_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
 
-        s3c2410_gpio_setpin(S3C2410_GPG8, 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
 
         /* initialise the WM8750 spi */
 
-        s3c2410_gpio_setpin(S3C2410_GPH10, 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_setpin(S3C2410_GPH(10), 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPH(10), S3C2410_GPIO_OUTPUT);
 
         /* Turn off suspend on both USB ports, and switch the
          * selectable USB port to USB device mode. */
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index 753aaedae551..9a5e43419722 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -85,10 +85,10 @@ static void smdk2413_udc_pullup(enum s3c2410_udc_cmd_e cmd)
         switch (cmd)
         {
                 case S3C2410_UDC_P_ENABLE :
-                        s3c2410_gpio_setpin(S3C2410_GPF2, 1);
+                        s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
                         break;
                 case S3C2410_UDC_P_DISABLE :
-                        s3c2410_gpio_setpin(S3C2410_GPF2, 0);
+                        s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
                         break;
                 case S3C2410_UDC_P_RESET :
                         break;
@@ -135,8 +135,8 @@ static void __init smdk2413_machine_init(void)
 {       /* Turn off suspend on both USB ports, and switch the
          * selectable USB port to USB device mode. */
 
-        s3c2410_gpio_setpin(S3C2410_GPF2, 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
+        s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
 
         s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
                               S3C2410_MISCCR_USBSUSPND0 |
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index d363b6f9000c..68f3870991bf 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -469,7 +469,7 @@ static void __init anubis_map_io(void)
                 anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
         } else {
                 /* ensure that the GPIO is setup */
-                s3c2410_gpio_setpin(S3C2410_GPA0, 1);
+                s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
         }
 }
 
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 315c42e31278..dfc7010935da 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -166,7 +166,7 @@ static struct platform_device at2440evb_device_eth = {
 };
 
 static struct s3c24xx_mci_pdata at2440evb_mci_pdata = {
-        .gpio_detect    = S3C2410_GPG10,
+        .gpio_detect    = S3C2410_GPG(10),
 };
 
 /* 7" LCD panel */
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 4b2088cb05e7..d43edede590e 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -121,16 +121,16 @@ static struct platform_device *nexcoder_devices[] __initdata = {
 static void __init nexcoder_sensorboard_init(void)
 {
         // Initialize SCCB bus
-        s3c2410_gpio_setpin(S3C2410_GPE14, 1); // IICSCL
-        s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPE15, 1); // IICSDA
-        s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL
+        s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA
+        s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
 
         // Power up the sensor board
-        s3c2410_gpio_setpin(S3C2410_GPF1, 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPF1, S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
-        s3c2410_gpio_setpin(S3C2410_GPF2, 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
+        s3c2410_gpio_setpin(S3C2410_GPF(1), 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
+        s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
+        s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
 }
 
 static void __init nexcoder_map_io(void)
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index ad0fdc4a794a..cba064b49a64 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -292,8 +292,8 @@ static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 
         /* ensure that an nRESET is not generated on resume. */
-        s3c2410_gpio_setpin(S3C2410_GPA21, 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
 
         return 0;
 }
@@ -305,7 +305,7 @@ static int osiris_pm_resume(struct sys_device *sd)
 
         __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
 
-        s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
 
         return 0;
 }
@@ -385,7 +385,7 @@ static void __init osiris_map_io(void)
                 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
         } else {
                 /* write-protect line to the NAND */
-                s3c2410_gpio_setpin(S3C2410_GPA0, 1);
+                s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
         }
 
         /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index fe658c48f724..aa119863c5ce 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -48,27 +48,27 @@
 /* LED devices */
 
 static struct s3c24xx_led_platdata smdk_pdata_led4 = {
-        .gpio           = S3C2410_GPF4,
+        .gpio           = S3C2410_GPF(4),
         .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
         .name           = "led4",
         .def_trigger    = "timer",
 };
 
 static struct s3c24xx_led_platdata smdk_pdata_led5 = {
-        .gpio           = S3C2410_GPF5,
+        .gpio           = S3C2410_GPF(5),
         .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
         .name           = "led5",
         .def_trigger    = "nand-disk",
 };
 
 static struct s3c24xx_led_platdata smdk_pdata_led6 = {
-        .gpio           = S3C2410_GPF6,
+        .gpio           = S3C2410_GPF(6),
         .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
         .name           = "led6",
 };
 
 static struct s3c24xx_led_platdata smdk_pdata_led7 = {
-        .gpio           = S3C2410_GPF7,
+        .gpio           = S3C2410_GPF(7),
         .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
         .name           = "led7",
 };
@@ -185,15 +185,15 @@ void __init smdk_machine_init(void)
 {
         /* Configure the LEDs (even if we have no LED support)*/
 
-        s3c2410_gpio_cfgpin(S3C2410_GPF4, S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_cfgpin(S3C2410_GPF5, S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_cfgpin(S3C2410_GPF6, S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_cfgpin(S3C2410_GPF7, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT);
 
-        s3c2410_gpio_setpin(S3C2410_GPF4, 1);
-        s3c2410_gpio_setpin(S3C2410_GPF5, 1);
-        s3c2410_gpio_setpin(S3C2410_GPF6, 1);
-        s3c2410_gpio_setpin(S3C2410_GPF7, 1);
+        s3c2410_gpio_setpin(S3C2410_GPF(4), 1);
+        s3c2410_gpio_setpin(S3C2410_GPF(5), 1);
+        s3c2410_gpio_setpin(S3C2410_GPF(6), 1);
+        s3c2410_gpio_setpin(S3C2410_GPF(7), 1);
 
         if (machine_is_smdk2443())
                 smdk_nand_info.twrph0 = 50;
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
index 65ebbaff7d50..ae0b9d6f3fb8 100644
--- a/arch/arm/plat-s3c24xx/gpio.c
+++ b/arch/arm/plat-s3c24xx/gpio.c
@@ -183,19 +183,19 @@ EXPORT_SYMBOL(s3c2410_modify_misccr);
 
 int s3c2410_gpio_getirq(unsigned int pin)
 {
-        if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15)
+        if (pin < S3C2410_GPF(0) || pin > S3C2410_GPG(15))
                 return -1;      /* not valid interrupts */
 
-        if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7)
+        if (pin < S3C2410_GPG(0) && pin > S3C2410_GPF(7))
                 return -1;      /* not valid pin */
 
-        if (pin < S3C2410_GPF4)
-                return (pin - S3C2410_GPF0) + IRQ_EINT0;
+        if (pin < S3C2410_GPF(4))
+                return (pin - S3C2410_GPF(0)) + IRQ_EINT0;
 
-        if (pin < S3C2410_GPG0)
-                return (pin - S3C2410_GPF4) + IRQ_EINT4;
+        if (pin < S3C2410_GPG(0))
+                return (pin - S3C2410_GPF(4)) + IRQ_EINT4;
 
-        return (pin - S3C2410_GPG0) + IRQ_EINT8;
+        return (pin - S3C2410_GPG(0)) + IRQ_EINT8;
 }
 
 EXPORT_SYMBOL(s3c2410_gpio_getirq);
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 60a9f7247205..a82adc3c98a5 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -82,7 +82,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
                 .base   = S3C2410_GPACON,
                 .pm     = __gpio_pm(&s3c_gpio_pm_1bit),
                 .chip   = {
-                        .base                   = S3C2410_GPA0,
+                        .base                   = S3C2410_GPA(0),
                         .owner                  = THIS_MODULE,
                         .label                  = "GPIOA",
                         .ngpio                  = 24,
@@ -94,7 +94,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
                 .base   = S3C2410_GPBCON,
                 .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                 .chip   = {
-                        .base                   = S3C2410_GPB0,
+                        .base                   = S3C2410_GPB(0),
                         .owner                  = THIS_MODULE,
                         .label                  = "GPIOB",
                         .ngpio                  = 16,
@@ -104,7 +104,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
                 .base   = S3C2410_GPCCON,
                 .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                 .chip   = {
-                        .base                   = S3C2410_GPC0,
+                        .base                   = S3C2410_GPC(0),
                         .owner                  = THIS_MODULE,
                         .label                  = "GPIOC",
                         .ngpio                  = 16,
@@ -114,7 +114,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
                 .base   = S3C2410_GPDCON,
                 .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                 .chip   = {
-                        .base                   = S3C2410_GPD0,
+                        .base                   = S3C2410_GPD(0),
                         .owner                  = THIS_MODULE,
                         .label                  = "GPIOD",
                         .ngpio                  = 16,
@@ -124,7 +124,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
                 .base   = S3C2410_GPECON,
                 .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                 .chip   = {
-                        .base                   = S3C2410_GPE0,
+                        .base                   = S3C2410_GPE(0),
                         .label                  = "GPIOE",
                         .owner                  = THIS_MODULE,
                         .ngpio                  = 16,
@@ -134,7 +134,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
                 .base   = S3C2410_GPFCON,
                 .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                 .chip   = {
-                        .base                   = S3C2410_GPF0,
+                        .base                   = S3C2410_GPF(0),
                         .owner                  = THIS_MODULE,
                         .label                  = "GPIOF",
                         .ngpio                  = 8,
@@ -145,7 +145,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
                 .base   = S3C2410_GPGCON,
                 .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                 .chip   = {
-                        .base                   = S3C2410_GPG0,
+                        .base                   = S3C2410_GPG(0),
                         .owner                  = THIS_MODULE,
                         .label                  = "GPIOG",
                         .ngpio                  = 10,
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 16aaf36b6e5a..56e5253ca02c 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -124,12 +124,12 @@ void s3c_pm_configure_extint(void)
          * and then configure it as an input if it is not
         */
 
-        for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
-                s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
+        for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) {
+                s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0));
         }
 
-        for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
-                s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
+        for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) {
+                s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8);
         }
 }
 
diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/plat-s3c24xx/setup-i2c.c
index e0d18530555e..71a6accf114e 100644
--- a/arch/arm/plat-s3c24xx/setup-i2c.c
+++ b/arch/arm/plat-s3c24xx/setup-i2c.c
@@ -21,6 +21,6 @@ struct platform_device;
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
-        s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
+        s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA);
+        s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL);
 }
diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
index 8b403cbb53d2..9edf7894eedd 100644
--- a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
+++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
@@ -22,16 +22,16 @@ void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
                                           int enable)
 {
         if (enable) {
-                s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0);
-                s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0);
-                s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0);
-                s3c2410_gpio_pullup(S3C2410_GPE11, 0);
-                s3c2410_gpio_pullup(S3C2410_GPE13, 0);
+                s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0);
+                s3c2410_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0);
+                s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0);
+                s3c2410_gpio_pullup(S3C2410_GPE(11), 0);
+                s3c2410_gpio_pullup(S3C2410_GPE(13), 0);
         } else {
-                s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPIO_INPUT);
-                s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPIO_INPUT);
-                s3c2410_gpio_pullup(S3C2410_GPE11, 1);
-                s3c2410_gpio_pullup(S3C2410_GPE12, 1);
-                s3c2410_gpio_pullup(S3C2410_GPE13, 1);
+                s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT);
+                s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT);
+                s3c2410_gpio_pullup(S3C2410_GPE(11), 1);
+                s3c2410_gpio_pullup(S3C2410_GPE(12), 1);
+                s3c2410_gpio_pullup(S3C2410_GPE(13), 1);
         }
 }
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
index 8fccd4e549f0..f34d0fc69ad8 100644
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
@@ -22,16 +22,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
                                        int enable)
 {
         if (enable) {
-                s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPG7_SPICLK1);
-                s3c2410_gpio_cfgpin(S3C2410_GPG6, S3C2410_GPG6_SPIMOSI1);
-                s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPG5_SPIMISO1);
-                s3c2410_gpio_pullup(S3C2410_GPG5, 0);
-                s3c2410_gpio_pullup(S3C2410_GPG6, 0);
+                s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1);
+                s3c2410_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1);
+                s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1);
+                s3c2410_gpio_pullup(S3C2410_GPG(5), 0);
+                s3c2410_gpio_pullup(S3C2410_GPG(6), 0);
         } else {
-                s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPIO_INPUT);
-                s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPIO_INPUT);
-                s3c2410_gpio_pullup(S3C2410_GPG5, 1);
-                s3c2410_gpio_pullup(S3C2410_GPG6, 1);
-                s3c2410_gpio_pullup(S3C2410_GPG7, 1);
+                s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT);
+                s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT);
+                s3c2410_gpio_pullup(S3C2410_GPG(5), 1);
+                s3c2410_gpio_pullup(S3C2410_GPG(6), 1);
+                s3c2410_gpio_pullup(S3C2410_GPG(7), 1);
         }
 }