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-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h22
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h130
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_sdramc.h23
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl.h2
-rw-r--r--arch/arm/mach-at91/pm.h49
-rw-r--r--arch/arm/mach-at91/pm_slowclock.S74
9 files changed, 258 insertions, 48 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index d8c1ededaa75..9c6af9737485 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -84,7 +84,7 @@
84 */ 84 */
85#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) 85#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
86#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) 86#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
87#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS) 87#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
88#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) 88#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
89#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) 89#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
90#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS) 90#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
index 1499b1cbffdd..976f4a6c3353 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
@@ -15,7 +15,7 @@
15#ifndef AT91CAP9_DDRSDR_H 15#ifndef AT91CAP9_DDRSDR_H
16#define AT91CAP9_DDRSDR_H 16#define AT91CAP9_DDRSDR_H
17 17
18#define AT91_DDRSDRC_MR (AT91_DDRSDRC + 0x00) /* Mode Register */ 18#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
19#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */ 19#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */
20#define AT91_DDRSDRC_MODE_NORMAL 0 20#define AT91_DDRSDRC_MODE_NORMAL 0
21#define AT91_DDRSDRC_MODE_NOP 1 21#define AT91_DDRSDRC_MODE_NOP 1
@@ -25,10 +25,10 @@
25#define AT91_DDRSDRC_MODE_EXT_LMR 5 25#define AT91_DDRSDRC_MODE_EXT_LMR 5
26#define AT91_DDRSDRC_MODE_DEEP 6 26#define AT91_DDRSDRC_MODE_DEEP 6
27 27
28#define AT91_DDRSDRC_RTR (AT91_DDRSDRC + 0x04) /* Refresh Timer Register */ 28#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
29#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ 29#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
30 30
31#define AT91_DDRSDRC_CR (AT91_DDRSDRC + 0x08) /* Configuration Register */ 31#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
32#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ 32#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
33#define AT91_DDRSDRC_NC_SDR8 (0 << 0) 33#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
34#define AT91_DDRSDRC_NC_SDR9 (1 << 0) 34#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
@@ -49,7 +49,7 @@
49#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */ 49#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
50#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ 50#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
51 51
52#define AT91_DDRSDRC_T0PR (AT91_DDRSDRC + 0x0C) /* Timing 0 Register */ 52#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
53#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ 53#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
54#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ 54#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
55#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ 55#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
@@ -59,13 +59,13 @@
59#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ 59#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
60#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ 60#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
61 61
62#define AT91_DDRSDRC_T1PR (AT91_DDRSDRC + 0x10) /* Timing 1 Register */ 62#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
63#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ 63#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
64#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ 64#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
65#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ 65#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
66#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ 66#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
67 67
68#define AT91_DDRSDRC_LPR (AT91_DDRSDRC + 0x18) /* Low Power Register */ 68#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */
69#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ 69#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
70#define AT91_DDRSDRC_LPCB_DISABLE 0 70#define AT91_DDRSDRC_LPCB_DISABLE 0
71#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 71#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
@@ -80,14 +80,14 @@
80#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) 80#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
81#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) 81#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
82 82
83#define AT91_DDRSDRC_MDR (AT91_DDRSDRC + 0x1C) /* Memory Device Register */ 83#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */
84#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ 84#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
85#define AT91_DDRSDRC_MD_SDR 0 85#define AT91_DDRSDRC_MD_SDR 0
86#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 86#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
87#define AT91_DDRSDRC_MD_DDR 2 87#define AT91_DDRSDRC_MD_DDR 2
88#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 88#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
89 89
90#define AT91_DDRSDRC_DLLR (AT91_DDRSDRC + 0x20) /* DLL Information Register */ 90#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */
91#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ 91#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
92#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ 92#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
93#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ 93#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
@@ -98,5 +98,11 @@
98#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ 98#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
99#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ 99#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
100 100
101/* Register access macros */
102#define at91_ramc_read(num, reg) \
103 at91_sys_read(AT91_DDRSDRC##num + reg)
104#define at91_ramc_write(num, reg, value) \
105 at91_sys_write(AT91_DDRSDRC##num + reg, value)
106
101 107
102#endif 108#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 43c396b9b4cb..4e79036d3b80 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -84,7 +84,7 @@
84 * System Peripherals (offset from AT91_BASE_SYS) 84 * System Peripherals (offset from AT91_BASE_SYS)
85 */ 85 */
86#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) 86#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
87#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) 87#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
88#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 88#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
89#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 89#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
90#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) 90#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 87de8be17484..2b5618518129 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -68,7 +68,7 @@
68/* 68/*
69 * System Peripherals (offset from AT91_BASE_SYS) 69 * System Peripherals (offset from AT91_BASE_SYS)
70 */ 70 */
71#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) 71#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
72#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 72#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
74#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) 74#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
new file mode 100644
index 000000000000..d27b15ba8ebf
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -0,0 +1,130 @@
1/*
2 * Header file for the Atmel DDR/SDR SDRAM Controller
3 *
4 * Copyright (C) 2010 Atmel Corporation
5 * Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#ifndef AT91SAM9_DDRSDR_H
13#define AT91SAM9_DDRSDR_H
14
15#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
16#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */
17#define AT91_DDRSDRC_MODE_NORMAL 0
18#define AT91_DDRSDRC_MODE_NOP 1
19#define AT91_DDRSDRC_MODE_PRECHARGE 2
20#define AT91_DDRSDRC_MODE_LMR 3
21#define AT91_DDRSDRC_MODE_REFRESH 4
22#define AT91_DDRSDRC_MODE_EXT_LMR 5
23#define AT91_DDRSDRC_MODE_DEEP 6
24
25#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
26#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
27
28#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
29#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
30#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
31#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
32#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
33#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
34#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
35#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
36#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
37#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
38#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
39#define AT91_DDRSDRC_NR_11 (0 << 2)
40#define AT91_DDRSDRC_NR_12 (1 << 2)
41#define AT91_DDRSDRC_NR_13 (2 << 2)
42#define AT91_DDRSDRC_NR_14 (3 << 2)
43#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
44#define AT91_DDRSDRC_CAS_2 (2 << 4)
45#define AT91_DDRSDRC_CAS_3 (3 << 4)
46#define AT91_DDRSDRC_CAS_25 (6 << 4)
47#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
48#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
49#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */
50#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */
51#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */
52#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */
53
54#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
55#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
56#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
57#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
58#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
59#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
60#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
61#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
62#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */
63#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
64
65#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
66#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
67#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
68#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
69#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
70
71#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */
72#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
73#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
74#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
75#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
76
77#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
78#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
79#define AT91_DDRSDRC_LPCB_DISABLE 0
80#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
81#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
82#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
83#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
84#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
85#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
86#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
87#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
88#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
89#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
90#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
91#define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */
92#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
93
94#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
95#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
96#define AT91_DDRSDRC_MD_SDR 0
97#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
98#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
99#define AT91_DDRSDRC_MD_DDR2 6
100#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
101#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
102#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
103
104#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
105#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
106#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
107#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
108#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
109
110#define AT91_DDRSDRC_HS 0x2C /* High Speed Register */
111#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
112
113#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
114
115#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */
116#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
117#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
118#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
119
120#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */
121#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
122#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
123
124/* Register access macros */
125#define at91_ramc_read(num, reg) \
126 at91_sys_read(AT91_DDRSDRC##num + reg)
127#define at91_ramc_write(num, reg, value) \
128 at91_sys_write(AT91_DDRSDRC##num + reg, value)
129
130#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index b7260389f7ca..100f5a592926 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -17,7 +17,7 @@
17#define AT91SAM9_SDRAMC_H 17#define AT91SAM9_SDRAMC_H
18 18
19/* SDRAM Controller (SDRAMC) registers */ 19/* SDRAM Controller (SDRAMC) registers */
20#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ 20#define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */
21#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ 21#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
22#define AT91_SDRAMC_MODE_NORMAL 0 22#define AT91_SDRAMC_MODE_NORMAL 0
23#define AT91_SDRAMC_MODE_NOP 1 23#define AT91_SDRAMC_MODE_NOP 1
@@ -27,10 +27,10 @@
27#define AT91_SDRAMC_MODE_EXT_LMR 5 27#define AT91_SDRAMC_MODE_EXT_LMR 5
28#define AT91_SDRAMC_MODE_DEEP 6 28#define AT91_SDRAMC_MODE_DEEP 6
29 29
30#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ 30#define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
31#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ 31#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
32 32
33#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ 33#define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */
34#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ 34#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
35#define AT91_SDRAMC_NC_8 (0 << 0) 35#define AT91_SDRAMC_NC_8 (0 << 0)
36#define AT91_SDRAMC_NC_9 (1 << 0) 36#define AT91_SDRAMC_NC_9 (1 << 0)
@@ -57,7 +57,7 @@
57#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ 57#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
58#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ 58#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
59 59
60#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ 60#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
61#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ 61#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
62#define AT91_SDRAMC_LPCB_DISABLE 0 62#define AT91_SDRAMC_LPCB_DISABLE 0
63#define AT91_SDRAMC_LPCB_SELF_REFRESH 1 63#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
@@ -71,16 +71,21 @@
71#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) 71#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
72#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) 72#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
73 73
74#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ 74#define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */
75#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ 75#define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */
76#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ 76#define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */
77#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ 77#define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */
78#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ 78#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
79 79
80#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ 80#define AT91_SDRAMC_MDR 0x24 /* SDRAM Memory Device Register */
81#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ 81#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
82#define AT91_SDRAMC_MD_SDRAM 0 82#define AT91_SDRAMC_MD_SDRAM 0
83#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 83#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
84 84
85/* Register access macros */
86#define at91_ramc_read(num, reg) \
87 at91_sys_read(AT91_SDRAMC##num + reg)
88#define at91_ramc_write(num, reg, value) \
89 at91_sys_write(AT91_SDRAMC##num + reg, value)
85 90
86#endif 91#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index fc2de6c09c86..87ba8517ad98 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -74,7 +74,7 @@
74 */ 74 */
75#define AT91_DMA (0xffffe600 - AT91_BASE_SYS) 75#define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
76#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) 76#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
77#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) 77#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
78#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 78#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
79#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 79#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
80#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) 80#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 08322c44df1a..8c87d0c1b8f8 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -30,14 +30,50 @@ static inline u32 sdram_selfrefresh_enable(void)
30{ 30{
31 u32 saved_lpr, lpr; 31 u32 saved_lpr, lpr;
32 32
33 saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR); 33 saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
34 34
35 lpr = saved_lpr & ~AT91_DDRSDRC_LPCB; 35 lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
36 at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH); 36 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
37 return saved_lpr; 37 return saved_lpr;
38} 38}
39 39
40#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr) 40#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
41
42#elif defined(CONFIG_ARCH_AT91SAM9G45)
43#include <mach/at91sam9_ddrsdr.h>
44
45/* We manage both DDRAM/SDRAM controllers, we need more than one value to
46 * remember.
47 */
48static u32 saved_lpr1;
49
50static inline u32 sdram_selfrefresh_enable(void)
51{
52 /* Those tow values allow us to delay self-refresh activation
53 * to the maximum. */
54 u32 lpr0, lpr1;
55 u32 saved_lpr0;
56
57 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
58 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
59 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
60
61 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
62 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
63 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
64
65 /* self-refresh mode now */
66 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
67 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
68
69 return saved_lpr0;
70}
71
72#define sdram_selfrefresh_disable(saved_lpr0) \
73 do { \
74 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
75 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
76 } while (0)
41 77
42#else 78#else
43#include <mach/at91sam9_sdramc.h> 79#include <mach/at91sam9_sdramc.h>
@@ -47,7 +83,6 @@ static inline u32 sdram_selfrefresh_enable(void)
47 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; 83 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
48 * handle those cases both here and in the Suspend-To-RAM support. 84 * handle those cases both here and in the Suspend-To-RAM support.
49 */ 85 */
50#define AT91_SDRAMC AT91_SDRAMC0
51#warning Assuming EB1 SDRAM controller is *NOT* used 86#warning Assuming EB1 SDRAM controller is *NOT* used
52#endif 87#endif
53 88
@@ -55,13 +90,13 @@ static inline u32 sdram_selfrefresh_enable(void)
55{ 90{
56 u32 saved_lpr, lpr; 91 u32 saved_lpr, lpr;
57 92
58 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR); 93 saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
59 94
60 lpr = saved_lpr & ~AT91_SDRAMC_LPCB; 95 lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
61 at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH); 96 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
62 return saved_lpr; 97 return saved_lpr;
63} 98}
64 99
65#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) 100#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
66 101
67#endif 102#endif
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 9c5b48e68a71..b6b00a1f6125 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -16,10 +16,12 @@
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17#include <mach/at91_pmc.h> 17#include <mach/at91_pmc.h>
18 18
19#ifdef CONFIG_ARCH_AT91RM9200 19#if defined(CONFIG_ARCH_AT91RM9200)
20#include <mach/at91rm9200_mc.h> 20#include <mach/at91rm9200_mc.h>
21#elif defined(CONFIG_ARCH_AT91CAP9) 21#elif defined(CONFIG_ARCH_AT91CAP9)
22#include <mach/at91cap9_ddrsdr.h> 22#include <mach/at91cap9_ddrsdr.h>
23#elif defined(CONFIG_ARCH_AT91SAM9G45)
24#include <mach/at91sam9_ddrsdr.h>
23#else 25#else
24#include <mach/at91sam9_sdramc.h> 26#include <mach/at91sam9_sdramc.h>
25#endif 27#endif
@@ -30,7 +32,6 @@
30 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; 32 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
31 * handle those cases both here and in the Suspend-To-RAM support. 33 * handle those cases both here and in the Suspend-To-RAM support.
32 */ 34 */
33#define AT91_SDRAMC AT91_SDRAMC0
34#warning Assuming EB1 SDRAM controller is *NOT* used 35#warning Assuming EB1 SDRAM controller is *NOT* used
35#endif 36#endif
36 37
@@ -113,12 +114,14 @@ ENTRY(at91_slow_clock)
113 /* 114 /*
114 * Register usage: 115 * Register usage:
115 * R1 = Base address of AT91_PMC 116 * R1 = Base address of AT91_PMC
116 * R2 = Base address of AT91_SDRAMC (or AT91_SYS on AT91RM9200) 117 * R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
117 * R3 = temporary register 118 * R3 = temporary register
118 * R4 = temporary register 119 * R4 = temporary register
120 * R5 = Base address of second RAM Controller or 0 if not present
119 */ 121 */
120 ldr r1, .at91_va_base_pmc 122 ldr r1, .at91_va_base_pmc
121 ldr r2, .at91_va_base_sdramc 123 ldr r2, .at91_va_base_sdramc
124 ldr r5, .at91_va_base_ramc1
122 125
123 /* Drain write buffer */ 126 /* Drain write buffer */
124 mcr p15, 0, r0, c7, c10, 4 127 mcr p15, 0, r0, c7, c10, 4
@@ -127,20 +130,33 @@ ENTRY(at91_slow_clock)
127 /* Put SDRAM in self-refresh mode */ 130 /* Put SDRAM in self-refresh mode */
128 mov r3, #1 131 mov r3, #1
129 str r3, [r2, #AT91_SDRAMC_SRR] 132 str r3, [r2, #AT91_SDRAMC_SRR]
130#elif defined(CONFIG_ARCH_AT91CAP9) 133#elif defined(CONFIG_ARCH_AT91CAP9) \
131 /* Enable SDRAM self-refresh mode */ 134 || defined(CONFIG_ARCH_AT91SAM9G45)
132 ldr r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
133 str r3, .saved_sam9_lpr
134 135
135 mov r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH 136 /* prepare for DDRAM self-refresh mode */
136 str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC] 137 ldr r3, [r2, #AT91_DDRSDRC_LPR]
138 str r3, .saved_sam9_lpr
139 bic r3, #AT91_DDRSDRC_LPCB
140 orr r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
141
142 /* figure out if we use the second ram controller */
143 cmp r5, #0
144 ldrne r4, [r5, #AT91_DDRSDRC_LPR]
145 strne r4, .saved_sam9_lpr1
146 bicne r4, #AT91_DDRSDRC_LPCB
147 orrne r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH
148
149 /* Enable DDRAM self-refresh mode */
150 str r3, [r2, #AT91_DDRSDRC_LPR]
151 strne r4, [r5, #AT91_DDRSDRC_LPR]
137#else 152#else
138 /* Enable SDRAM self-refresh mode */ 153 /* Enable SDRAM self-refresh mode */
139 ldr r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC] 154 ldr r3, [r2, #AT91_SDRAMC_LPR]
140 str r3, .saved_sam9_lpr 155 str r3, .saved_sam9_lpr
141 156
142 mov r3, #AT91_SDRAMC_LPCB_SELF_REFRESH 157 bic r3, #AT91_SDRAMC_LPCB
143 str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC] 158 orr r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
159 str r3, [r2, #AT91_SDRAMC_LPR]
144#endif 160#endif
145 161
146 /* Save Master clock setting */ 162 /* Save Master clock setting */
@@ -247,14 +263,21 @@ ENTRY(at91_slow_clock)
247 263
248#ifdef CONFIG_ARCH_AT91RM9200 264#ifdef CONFIG_ARCH_AT91RM9200
249 /* Do nothing - self-refresh is automatically disabled. */ 265 /* Do nothing - self-refresh is automatically disabled. */
250#elif defined(CONFIG_ARCH_AT91CAP9) 266#elif defined(CONFIG_ARCH_AT91CAP9) \
251 /* Restore LPR on AT91CAP9 */ 267 || defined(CONFIG_ARCH_AT91SAM9G45)
268 /* Restore LPR on AT91 with DDRAM */
252 ldr r3, .saved_sam9_lpr 269 ldr r3, .saved_sam9_lpr
253 str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC] 270 str r3, [r2, #AT91_DDRSDRC_LPR]
271
272 /* if we use the second ram controller */
273 cmp r5, #0
274 ldrne r4, .saved_sam9_lpr1
275 strne r4, [r5, #AT91_DDRSDRC_LPR]
276
254#else 277#else
255 /* Restore LPR on AT91SAM9 */ 278 /* Restore LPR on AT91 with SDRAM */
256 ldr r3, .saved_sam9_lpr 279 ldr r3, .saved_sam9_lpr
257 str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC] 280 str r3, [r2, #AT91_SDRAMC_LPR]
258#endif 281#endif
259 282
260 /* Restore registers, and return */ 283 /* Restore registers, and return */
@@ -273,18 +296,29 @@ ENTRY(at91_slow_clock)
273.saved_sam9_lpr: 296.saved_sam9_lpr:
274 .word 0 297 .word 0
275 298
299.saved_sam9_lpr1:
300 .word 0
301
276.at91_va_base_pmc: 302.at91_va_base_pmc:
277 .word AT91_VA_BASE_SYS + AT91_PMC 303 .word AT91_VA_BASE_SYS + AT91_PMC
278 304
279#ifdef CONFIG_ARCH_AT91RM9200 305#ifdef CONFIG_ARCH_AT91RM9200
280.at91_va_base_sdramc: 306.at91_va_base_sdramc:
281 .word AT91_VA_BASE_SYS 307 .word AT91_VA_BASE_SYS
282#elif defined(CONFIG_ARCH_AT91CAP9) 308#elif defined(CONFIG_ARCH_AT91CAP9) \
309 || defined(CONFIG_ARCH_AT91SAM9G45)
283.at91_va_base_sdramc: 310.at91_va_base_sdramc:
284 .word AT91_VA_BASE_SYS + AT91_DDRSDRC 311 .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
285#else 312#else
286.at91_va_base_sdramc: 313.at91_va_base_sdramc:
287 .word AT91_VA_BASE_SYS + AT91_SDRAMC 314 .word AT91_VA_BASE_SYS + AT91_SDRAMC0
315#endif
316
317.at91_va_base_ramc1:
318#if defined(CONFIG_ARCH_AT91SAM9G45)
319 .word AT91_VA_BASE_SYS + AT91_DDRSDRC1
320#else
321 .word 0
288#endif 322#endif
289 323
290ENTRY(at91_slow_clock_sz) 324ENTRY(at91_slow_clock_sz)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 22:55:30 -0500