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-rw-r--r--arch/arm/mach-omap1/Makefile6
-rw-r--r--arch/arm/mach-omap1/board-ams-delta.c1
-rw-r--r--arch/arm/mach-omap1/board-fsample.c22
-rw-r--r--arch/arm/mach-omap1/board-h2.c4
-rw-r--r--arch/arm/mach-omap1/board-h3.c22
-rw-r--r--arch/arm/mach-omap1/board-htcherald.c2
-rw-r--r--arch/arm/mach-omap1/board-innovator.c4
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c1
-rw-r--r--arch/arm/mach-omap1/board-osk.c6
-rw-r--r--arch/arm/mach-omap1/board-palmte.c1
-rw-r--r--arch/arm/mach-omap1/board-palmz71.c1
-rw-r--r--arch/arm/mach-omap1/board-perseus2.c22
-rw-r--r--arch/arm/mach-omap1/board-sx1.c1
-rw-r--r--arch/arm/mach-omap1/board-voiceblue.c1
-rw-r--r--arch/arm/mach-omap1/clock_data.c4
-rw-r--r--arch/arm/mach-omap1/gpio15xx.c99
-rw-r--r--arch/arm/mach-omap1/gpio16xx.c200
-rw-r--r--arch/arm/mach-omap1/gpio7xx.c262
-rw-r--r--arch/arm/mach-omap2/Makefile2
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c1
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c1
-rw-r--r--arch/arm/mach-omap2/board-3630sdp.c1
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c1
-rw-r--r--arch/arm/mach-omap2/board-am3517crane.c2
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c1
-rw-r--r--arch/arm/mach-omap2/board-apollon.c3
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c1
-rw-r--r--arch/arm/mach-omap2/board-cm-t3517.c1
-rw-r--r--arch/arm/mach-omap2/board-devkit8000.c1
-rw-r--r--arch/arm/mach-omap2/board-h4.c1
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c1
-rw-r--r--arch/arm/mach-omap2/board-igep0030.c1
-rw-r--r--arch/arm/mach-omap2/board-ldp.c3
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c1
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c1
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c1
-rw-r--r--arch/arm/mach-omap2/board-omap3logic.c1
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c1
-rw-r--r--arch/arm/mach-omap2/board-omap3stalker.c1
-rw-r--r--arch/arm/mach-omap2/board-omap3touchbook.c1
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c1
-rw-r--r--arch/arm/mach-omap2/board-overo.c1
-rw-r--r--arch/arm/mach-omap2/board-rx51.c1
-rw-r--r--arch/arm/mach-omap2/board-zoom.c1
-rw-r--r--arch/arm/mach-omap2/gpio.c104
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c230
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c280
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c361
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c341
-rw-r--r--arch/arm/plat-omap/gpio.c660
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h46
51 files changed, 2175 insertions, 538 deletions
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index de3cc130ab8e..0b1c07ffa2f1 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -49,6 +49,12 @@ ifeq ($(CONFIG_ARCH_OMAP15XX),y)
49obj-$(CONFIG_MACH_OMAP_INNOVATOR) += fpga.o 49obj-$(CONFIG_MACH_OMAP_INNOVATOR) += fpga.o
50endif 50endif
51 51
52# GPIO
53obj-$(CONFIG_ARCH_OMAP730) += gpio7xx.o
54obj-$(CONFIG_ARCH_OMAP850) += gpio7xx.o
55obj-$(CONFIG_ARCH_OMAP15XX) += gpio15xx.o
56obj-$(CONFIG_ARCH_OMAP16XX) += gpio16xx.o
57
52# LEDs support 58# LEDs support
53led-$(CONFIG_MACH_OMAP_H2) += leds-h2p2-debug.o 59led-$(CONFIG_MACH_OMAP_H2) += leds-h2p2-debug.o
54led-$(CONFIG_MACH_OMAP_H3) += leds-h2p2-debug.o 60led-$(CONFIG_MACH_OMAP_H3) += leds-h2p2-debug.o
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index dc82f3d028b5..e1439506eba9 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -141,7 +141,6 @@ static void __init ams_delta_init_irq(void)
141{ 141{
142 omap1_init_common_hw(); 142 omap1_init_common_hw();
143 omap_init_irq(); 143 omap_init_irq();
144 omap_gpio_init();
145} 144}
146 145
147static struct map_desc ams_delta_io_desc[] __initdata = { 146static struct map_desc ams_delta_io_desc[] __initdata = {
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 149fdd32e127..0c3f396328bd 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -120,6 +120,15 @@ static struct resource smc91x_resources[] = {
120 }, 120 },
121}; 121};
122 122
123static void __init fsample_init_smc91x(void)
124{
125 fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
126 mdelay(50);
127 fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
128 H2P2_DBG_FPGA_LAN_RESET);
129 mdelay(50);
130}
131
123static struct mtd_partition nor_partitions[] = { 132static struct mtd_partition nor_partitions[] = {
124 /* bootloader (U-Boot, etc) in first sector */ 133 /* bootloader (U-Boot, etc) in first sector */
125 { 134 {
@@ -285,6 +294,8 @@ static struct omap_board_config_kernel fsample_config[] = {
285 294
286static void __init omap_fsample_init(void) 295static void __init omap_fsample_init(void)
287{ 296{
297 fsample_init_smc91x();
298
288 if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0) 299 if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
289 BUG(); 300 BUG();
290 gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN); 301 gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
@@ -312,21 +323,10 @@ static void __init omap_fsample_init(void)
312 omap_register_i2c_bus(1, 100, NULL, 0); 323 omap_register_i2c_bus(1, 100, NULL, 0);
313} 324}
314 325
315static void __init fsample_init_smc91x(void)
316{
317 fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
318 mdelay(50);
319 fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
320 H2P2_DBG_FPGA_LAN_RESET);
321 mdelay(50);
322}
323
324static void __init omap_fsample_init_irq(void) 326static void __init omap_fsample_init_irq(void)
325{ 327{
326 omap1_init_common_hw(); 328 omap1_init_common_hw();
327 omap_init_irq(); 329 omap_init_irq();
328 omap_gpio_init();
329 fsample_init_smc91x();
330} 330}
331 331
332/* Only FPGA needs to be mapped here. All others are done with ioremap */ 332/* Only FPGA needs to be mapped here. All others are done with ioremap */
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 197adb49dc5a..082a73ca5564 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -374,8 +374,6 @@ static void __init h2_init_irq(void)
374{ 374{
375 omap1_init_common_hw(); 375 omap1_init_common_hw();
376 omap_init_irq(); 376 omap_init_irq();
377 omap_gpio_init();
378 h2_init_smc91x();
379} 377}
380 378
381static struct omap_usb_config h2_usb_config __initdata = { 379static struct omap_usb_config h2_usb_config __initdata = {
@@ -403,6 +401,8 @@ static struct omap_board_config_kernel h2_config[] __initdata = {
403 401
404static void __init h2_init(void) 402static void __init h2_init(void)
405{ 403{
404 h2_init_smc91x();
405
406 /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped 406 /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped
407 * to address 0 by a dip switch), NAND on CS2B. The NAND driver will 407 * to address 0 by a dip switch), NAND on CS2B. The NAND driver will
408 * notice whether a NAND chip is enabled at probe time. 408 * notice whether a NAND chip is enabled at probe time.
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 9126e3e37b4a..d2cff5022fe5 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -264,6 +264,15 @@ static struct platform_device smc91x_device = {
264 .resource = smc91x_resources, 264 .resource = smc91x_resources,
265}; 265};
266 266
267static void __init h3_init_smc91x(void)
268{
269 omap_cfg_reg(W15_1710_GPIO40);
270 if (gpio_request(40, "SMC91x irq") < 0) {
271 printk("Error requesting gpio 40 for smc91x irq\n");
272 return;
273 }
274}
275
267#define GPTIMER_BASE 0xFFFB1400 276#define GPTIMER_BASE 0xFFFB1400
268#define GPTIMER_REGS(x) (0xFFFB1400 + (x * 0x800)) 277#define GPTIMER_REGS(x) (0xFFFB1400 + (x * 0x800))
269#define GPTIMER_REGS_SIZE 0x46 278#define GPTIMER_REGS_SIZE 0x46
@@ -376,6 +385,8 @@ static struct i2c_board_info __initdata h3_i2c_board_info[] = {
376 385
377static void __init h3_init(void) 386static void __init h3_init(void)
378{ 387{
388 h3_init_smc91x();
389
379 /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped 390 /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped
380 * to address 0 by a dip switch), NAND on CS2B. The NAND driver will 391 * to address 0 by a dip switch), NAND on CS2B. The NAND driver will
381 * notice whether a NAND chip is enabled at probe time. 392 * notice whether a NAND chip is enabled at probe time.
@@ -422,21 +433,10 @@ static void __init h3_init(void)
422 h3_mmc_init(); 433 h3_mmc_init();
423} 434}
424 435
425static void __init h3_init_smc91x(void)
426{
427 omap_cfg_reg(W15_1710_GPIO40);
428 if (gpio_request(40, "SMC91x irq") < 0) {
429 printk("Error requesting gpio 40 for smc91x irq\n");
430 return;
431 }
432}
433
434static void __init h3_init_irq(void) 436static void __init h3_init_irq(void)
435{ 437{
436 omap1_init_common_hw(); 438 omap1_init_common_hw();
437 omap_init_irq(); 439 omap_init_irq();
438 omap_gpio_init();
439 h3_init_smc91x();
440} 440}
441 441
442static void __init h3_map_io(void) 442static void __init h3_map_io(void)
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 071af3e47789..faa344f734dc 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -577,8 +577,6 @@ static void __init htcherald_init(void)
577 printk(KERN_INFO "HTC Herald init.\n"); 577 printk(KERN_INFO "HTC Herald init.\n");
578 578
579 /* Do board initialization before we register all the devices */ 579 /* Do board initialization before we register all the devices */
580 omap_gpio_init();
581
582 omap_board_config = htcherald_config; 580 omap_board_config = htcherald_config;
583 omap_board_config_size = ARRAY_SIZE(htcherald_config); 581 omap_board_config_size = ARRAY_SIZE(htcherald_config);
584 platform_add_devices(devices, ARRAY_SIZE(devices)); 582 platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index dc2b86fd66c1..a051acdc526a 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -290,13 +290,11 @@ static void __init innovator_init_irq(void)
290{ 290{
291 omap1_init_common_hw(); 291 omap1_init_common_hw();
292 omap_init_irq(); 292 omap_init_irq();
293 omap_gpio_init();
294#ifdef CONFIG_ARCH_OMAP15XX 293#ifdef CONFIG_ARCH_OMAP15XX
295 if (cpu_is_omap1510()) { 294 if (cpu_is_omap1510()) {
296 omap1510_fpga_init_irq(); 295 omap1510_fpga_init_irq();
297 } 296 }
298#endif 297#endif
299 innovator_init_smc91x();
300} 298}
301 299
302#ifdef CONFIG_ARCH_OMAP15XX 300#ifdef CONFIG_ARCH_OMAP15XX
@@ -387,6 +385,8 @@ static struct omap_board_config_kernel innovator_config[] = {
387 385
388static void __init innovator_init(void) 386static void __init innovator_init(void)
389{ 387{
388 innovator_init_smc91x();
389
390#ifdef CONFIG_ARCH_OMAP15XX 390#ifdef CONFIG_ARCH_OMAP15XX
391 if (cpu_is_omap1510()) { 391 if (cpu_is_omap1510()) {
392 unsigned char reg; 392 unsigned char reg;
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index aa8375b2a0a3..605495bbc583 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -246,7 +246,6 @@ static void __init omap_nokia770_init(void)
246 platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices)); 246 platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
247 spi_register_board_info(nokia770_spi_board_info, 247 spi_register_board_info(nokia770_spi_board_info,
248 ARRAY_SIZE(nokia770_spi_board_info)); 248 ARRAY_SIZE(nokia770_spi_board_info));
249 omap_gpio_init();
250 omap_serial_init(); 249 omap_serial_init();
251 omap_register_i2c_bus(1, 100, NULL, 0); 250 omap_register_i2c_bus(1, 100, NULL, 0);
252 hwa742_dev_init(); 251 hwa742_dev_init();
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index e9dd79149a8e..d44e7172efc2 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -283,9 +283,6 @@ static void __init osk_init_irq(void)
283{ 283{
284 omap1_init_common_hw(); 284 omap1_init_common_hw();
285 omap_init_irq(); 285 omap_init_irq();
286 omap_gpio_init();
287 osk_init_smc91x();
288 osk_init_cf();
289} 286}
290 287
291static struct omap_usb_config osk_usb_config __initdata = { 288static struct omap_usb_config osk_usb_config __initdata = {
@@ -541,6 +538,9 @@ static void __init osk_init(void)
541{ 538{
542 u32 l; 539 u32 l;
543 540
541 osk_init_smc91x();
542 osk_init_cf();
543
544 /* Workaround for wrong CS3 (NOR flash) timing 544 /* Workaround for wrong CS3 (NOR flash) timing
545 * There are some U-Boot versions out there which configure 545 * There are some U-Boot versions out there which configure
546 * wrong CS3 memory timings. This mainly leads to CRC 546 * wrong CS3 memory timings. This mainly leads to CRC
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index f32738b1eb6b..994dc6f50729 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -63,7 +63,6 @@ static void __init omap_palmte_init_irq(void)
63{ 63{
64 omap1_init_common_hw(); 64 omap1_init_common_hw();
65 omap_init_irq(); 65 omap_init_irq();
66 omap_gpio_init();
67} 66}
68 67
69static const int palmte_keymap[] = { 68static const int palmte_keymap[] = {
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index d7a245cef9a4..2afac598baee 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -62,7 +62,6 @@ omap_palmz71_init_irq(void)
62{ 62{
63 omap1_init_common_hw(); 63 omap1_init_common_hw();
64 omap_init_irq(); 64 omap_init_irq();
65 omap_gpio_init();
66} 65}
67 66
68static int palmz71_keymap[] = { 67static int palmz71_keymap[] = {
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index a8d16a255c18..69fda218fb45 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -251,8 +251,19 @@ static struct omap_board_config_kernel perseus2_config[] __initdata = {
251 { OMAP_TAG_LCD, &perseus2_lcd_config }, 251 { OMAP_TAG_LCD, &perseus2_lcd_config },
252}; 252};
253 253
254static void __init perseus2_init_smc91x(void)
255{
256 fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
257 mdelay(50);
258 fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
259 H2P2_DBG_FPGA_LAN_RESET);
260 mdelay(50);
261}
262
254static void __init omap_perseus2_init(void) 263static void __init omap_perseus2_init(void)
255{ 264{
265 perseus2_init_smc91x();
266
256 if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0) 267 if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
257 BUG(); 268 BUG();
258 gpio_direction_input(P2_NAND_RB_GPIO_PIN); 269 gpio_direction_input(P2_NAND_RB_GPIO_PIN);
@@ -280,21 +291,10 @@ static void __init omap_perseus2_init(void)
280 omap_register_i2c_bus(1, 100, NULL, 0); 291 omap_register_i2c_bus(1, 100, NULL, 0);
281} 292}
282 293
283static void __init perseus2_init_smc91x(void)
284{
285 fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
286 mdelay(50);
287 fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
288 H2P2_DBG_FPGA_LAN_RESET);
289 mdelay(50);
290}
291
292static void __init omap_perseus2_init_irq(void) 294static void __init omap_perseus2_init_irq(void)
293{ 295{
294 omap1_init_common_hw(); 296 omap1_init_common_hw();
295 omap_init_irq(); 297 omap_init_irq();
296 omap_gpio_init();
297 perseus2_init_smc91x();
298} 298}
299/* Only FPGA needs to be mapped here. All others are done with ioremap */ 299/* Only FPGA needs to be mapped here. All others are done with ioremap */
300static struct map_desc omap_perseus2_io_desc[] __initdata = { 300static struct map_desc omap_perseus2_io_desc[] __initdata = {
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index d25f59e5a773..463862c67819 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -409,7 +409,6 @@ static void __init omap_sx1_init_irq(void)
409{ 409{
410 omap1_init_common_hw(); 410 omap1_init_common_hw();
411 omap_init_irq(); 411 omap_init_irq();
412 omap_gpio_init();
413} 412}
414/*----------------------------------------*/ 413/*----------------------------------------*/
415 414
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index b2838bfeab86..815a69ce821d 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -161,7 +161,6 @@ static void __init voiceblue_init_irq(void)
161{ 161{
162 omap1_init_common_hw(); 162 omap1_init_common_hw();
163 omap_init_irq(); 163 omap_init_irq();
164 omap_gpio_init();
165} 164}
166 165
167static void __init voiceblue_init(void) 166static void __init voiceblue_init(void)
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index af54114b8f08..423d21d8c190 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -143,7 +143,7 @@ static struct arm_idlect1_clk armper_ck = {
143 * activation. [ GPIO code for 1510 ] 143 * activation. [ GPIO code for 1510 ]
144 */ 144 */
145static struct clk arm_gpio_ck = { 145static struct clk arm_gpio_ck = {
146 .name = "arm_gpio_ck", 146 .name = "ick",
147 .ops = &clkops_generic, 147 .ops = &clkops_generic,
148 .parent = &ck_dpll1, 148 .parent = &ck_dpll1,
149 .flags = ENABLE_ON_INIT, 149 .flags = ENABLE_ON_INIT,
@@ -684,7 +684,7 @@ static struct omap_clk omap_clks[] = {
684 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), 684 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
685 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), 685 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
686 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), 686 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
687 CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), 687 CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310),
688 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), 688 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
689 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), 689 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
690 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), 690 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
new file mode 100644
index 000000000000..04c4b04cf54e
--- /dev/null
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -0,0 +1,99 @@
1/*
2 * OMAP15xx specific gpio init
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Author:
7 * Charulatha V <charu@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/gpio.h>
20
21#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
22#define OMAP1510_GPIO_BASE 0xFFFCE000
23
24/* gpio1 */
25static struct __initdata resource omap15xx_mpu_gpio_resources[] = {
26 {
27 .start = OMAP1_MPUIO_VBASE,
28 .end = OMAP1_MPUIO_VBASE + SZ_2K - 1,
29 .flags = IORESOURCE_MEM,
30 },
31 {
32 .start = INT_MPUIO,
33 .flags = IORESOURCE_IRQ,
34 },
35};
36
37static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
38 .virtual_irq_start = IH_MPUIO_BASE,
39 .bank_type = METHOD_MPUIO,
40 .bank_width = 16,
41 .bank_stride = 1,
42};
43
44static struct __initdata platform_device omap15xx_mpu_gpio = {
45 .name = "omap_gpio",
46 .id = 0,
47 .dev = {
48 .platform_data = &omap15xx_mpu_gpio_config,
49 },
50 .num_resources = ARRAY_SIZE(omap15xx_mpu_gpio_resources),
51 .resource = omap15xx_mpu_gpio_resources,
52};
53
54/* gpio2 */
55static struct __initdata resource omap15xx_gpio_resources[] = {
56 {
57 .start = OMAP1510_GPIO_BASE,
58 .end = OMAP1510_GPIO_BASE + SZ_2K - 1,
59 .flags = IORESOURCE_MEM,
60 },
61 {
62 .start = INT_GPIO_BANK1,
63 .flags = IORESOURCE_IRQ,
64 },
65};
66
67static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
68 .virtual_irq_start = IH_GPIO_BASE,
69 .bank_type = METHOD_GPIO_1510,
70 .bank_width = 16,
71};
72
73static struct __initdata platform_device omap15xx_gpio = {
74 .name = "omap_gpio",
75 .id = 1,
76 .dev = {
77 .platform_data = &omap15xx_gpio_config,
78 },
79 .num_resources = ARRAY_SIZE(omap15xx_gpio_resources),
80 .resource = omap15xx_gpio_resources,
81};
82
83/*
84 * omap15xx_gpio_init needs to be done before
85 * machine_init functions access gpio APIs.
86 * Hence omap15xx_gpio_init is a postcore_initcall.
87 */
88static int __init omap15xx_gpio_init(void)
89{
90 if (!cpu_is_omap15xx())
91 return -EINVAL;
92
93 platform_device_register(&omap15xx_mpu_gpio);
94 platform_device_register(&omap15xx_gpio);
95
96 gpio_bank_count = 2;
97 return 0;
98}
99postcore_initcall(omap15xx_gpio_init);
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
new file mode 100644
index 000000000000..5dd0d4c82b24
--- /dev/null
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -0,0 +1,200 @@
1/*
2 * OMAP16xx specific gpio init
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Author:
7 * Charulatha V <charu@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/gpio.h>
20
21#define OMAP1610_GPIO1_BASE 0xfffbe400
22#define OMAP1610_GPIO2_BASE 0xfffbec00
23#define OMAP1610_GPIO3_BASE 0xfffbb400
24#define OMAP1610_GPIO4_BASE 0xfffbbc00
25#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
26
27/* mpu gpio */
28static struct __initdata resource omap16xx_mpu_gpio_resources[] = {
29 {
30 .start = OMAP1_MPUIO_VBASE,
31 .end = OMAP1_MPUIO_VBASE + SZ_2K - 1,
32 .flags = IORESOURCE_MEM,
33 },
34 {
35 .start = INT_MPUIO,
36 .flags = IORESOURCE_IRQ,
37 },
38};
39
40static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
41 .virtual_irq_start = IH_MPUIO_BASE,
42 .bank_type = METHOD_MPUIO,
43 .bank_width = 16,
44 .bank_stride = 1,
45};
46
47static struct __initdata platform_device omap16xx_mpu_gpio = {
48 .name = "omap_gpio",
49 .id = 0,
50 .dev = {
51 .platform_data = &omap16xx_mpu_gpio_config,
52 },
53 .num_resources = ARRAY_SIZE(omap16xx_mpu_gpio_resources),
54 .resource = omap16xx_mpu_gpio_resources,
55};
56
57/* gpio1 */
58static struct __initdata resource omap16xx_gpio1_resources[] = {
59 {
60 .start = OMAP1610_GPIO1_BASE,
61 .end = OMAP1610_GPIO1_BASE + SZ_2K - 1,
62 .flags = IORESOURCE_MEM,
63 },
64 {
65 .start = INT_GPIO_BANK1,
66 .flags = IORESOURCE_IRQ,
67 },
68};
69
70static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
71 .virtual_irq_start = IH_GPIO_BASE,
72 .bank_type = METHOD_GPIO_1610,
73 .bank_width = 16,
74};
75
76static struct __initdata platform_device omap16xx_gpio1 = {
77 .name = "omap_gpio",
78 .id = 1,
79 .dev = {
80 .platform_data = &omap16xx_gpio1_config,
81 },
82 .num_resources = ARRAY_SIZE(omap16xx_gpio1_resources),
83 .resource = omap16xx_gpio1_resources,
84};
85
86/* gpio2 */
87static struct __initdata resource omap16xx_gpio2_resources[] = {
88 {
89 .start = OMAP1610_GPIO2_BASE,
90 .end = OMAP1610_GPIO2_BASE + SZ_2K - 1,
91 .flags = IORESOURCE_MEM,
92 },
93 {
94 .start = INT_1610_GPIO_BANK2,
95 .flags = IORESOURCE_IRQ,
96 },
97};
98
99static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = {
100 .virtual_irq_start = IH_GPIO_BASE + 16,
101 .bank_type = METHOD_GPIO_1610,
102 .bank_width = 16,
103};
104
105static struct __initdata platform_device omap16xx_gpio2 = {
106 .name = "omap_gpio",
107 .id = 2,
108 .dev = {
109 .platform_data = &omap16xx_gpio2_config,
110 },
111 .num_resources = ARRAY_SIZE(omap16xx_gpio2_resources),
112 .resource = omap16xx_gpio2_resources,
113};
114
115/* gpio3 */
116static struct __initdata resource omap16xx_gpio3_resources[] = {
117 {
118 .start = OMAP1610_GPIO3_BASE,
119 .end = OMAP1610_GPIO3_BASE + SZ_2K - 1,
120 .flags = IORESOURCE_MEM,
121 },
122 {
123 .start = INT_1610_GPIO_BANK3,
124 .flags = IORESOURCE_IRQ,
125 },
126};
127
128static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = {
129 .virtual_irq_start = IH_GPIO_BASE + 32,
130 .bank_type = METHOD_GPIO_1610,
131 .bank_width = 16,
132};
133
134static struct __initdata platform_device omap16xx_gpio3 = {
135 .name = "omap_gpio",
136 .id = 3,
137 .dev = {
138 .platform_data = &omap16xx_gpio3_config,
139 },
140 .num_resources = ARRAY_SIZE(omap16xx_gpio3_resources),
141 .resource = omap16xx_gpio3_resources,
142};
143
144/* gpio4 */
145static struct __initdata resource omap16xx_gpio4_resources[] = {
146 {
147 .start = OMAP1610_GPIO4_BASE,
148 .end = OMAP1610_GPIO4_BASE + SZ_2K - 1,
149 .flags = IORESOURCE_MEM,
150 },
151 {
152 .start = INT_1610_GPIO_BANK4,
153 .flags = IORESOURCE_IRQ,
154 },
155};
156
157static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = {
158 .virtual_irq_start = IH_GPIO_BASE + 48,
159 .bank_type = METHOD_GPIO_1610,
160 .bank_width = 16,
161};
162
163static struct __initdata platform_device omap16xx_gpio4 = {
164 .name = "omap_gpio",
165 .id = 4,
166 .dev = {
167 .platform_data = &omap16xx_gpio4_config,
168 },
169 .num_resources = ARRAY_SIZE(omap16xx_gpio4_resources),
170 .resource = omap16xx_gpio4_resources,
171};
172
173static struct __initdata platform_device * omap16xx_gpio_dev[] = {
174 &omap16xx_mpu_gpio,
175 &omap16xx_gpio1,
176 &omap16xx_gpio2,
177 &omap16xx_gpio3,
178 &omap16xx_gpio4,
179};
180
181/*
182 * omap16xx_gpio_init needs to be done before
183 * machine_init functions access gpio APIs.
184 * Hence omap16xx_gpio_init is a postcore_initcall.
185 */
186static int __init omap16xx_gpio_init(void)
187{
188 int i;
189
190 if (!cpu_is_omap16xx())
191 return -EINVAL;
192
193 for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
194 platform_device_register(omap16xx_gpio_dev[i]);
195
196 gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev);
197
198 return 0;
199}
200postcore_initcall(omap16xx_gpio_init);
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
new file mode 100644
index 000000000000..1204c8b871af
--- /dev/null
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -0,0 +1,262 @@
1/*
2 * OMAP7xx specific gpio init
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Author:
7 * Charulatha V <charu@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/gpio.h>
20
21#define OMAP7XX_GPIO1_BASE 0xfffbc000
22#define OMAP7XX_GPIO2_BASE 0xfffbc800
23#define OMAP7XX_GPIO3_BASE 0xfffbd000
24#define OMAP7XX_GPIO4_BASE 0xfffbd800
25#define OMAP7XX_GPIO5_BASE 0xfffbe000
26#define OMAP7XX_GPIO6_BASE 0xfffbe800
27#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
28
29/* mpu gpio */
30static struct __initdata resource omap7xx_mpu_gpio_resources[] = {
31 {
32 .start = OMAP1_MPUIO_VBASE,
33 .end = OMAP1_MPUIO_VBASE + SZ_2K - 1,
34 .flags = IORESOURCE_MEM,
35 },
36 {
37 .start = INT_7XX_MPUIO,
38 .flags = IORESOURCE_IRQ,
39 },
40};
41
42static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
43 .virtual_irq_start = IH_MPUIO_BASE,
44 .bank_type = METHOD_MPUIO,
45 .bank_width = 32,
46 .bank_stride = 2,
47};
48
49static struct __initdata platform_device omap7xx_mpu_gpio = {
50 .name = "omap_gpio",
51 .id = 0,
52 .dev = {
53 .platform_data = &omap7xx_mpu_gpio_config,
54 },
55 .num_resources = ARRAY_SIZE(omap7xx_mpu_gpio_resources),
56 .resource = omap7xx_mpu_gpio_resources,
57};
58
59/* gpio1 */
60static struct __initdata resource omap7xx_gpio1_resources[] = {
61 {
62 .start = OMAP7XX_GPIO1_BASE,
63 .end = OMAP7XX_GPIO1_BASE + SZ_2K - 1,
64 .flags = IORESOURCE_MEM,
65 },
66 {
67 .start = INT_7XX_GPIO_BANK1,
68 .flags = IORESOURCE_IRQ,
69 },
70};
71
72static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
73 .virtual_irq_start = IH_GPIO_BASE,
74 .bank_type = METHOD_GPIO_7XX,
75 .bank_width = 32,
76};
77
78static struct __initdata platform_device omap7xx_gpio1 = {
79 .name = "omap_gpio",
80 .id = 1,
81 .dev = {
82 .platform_data = &omap7xx_gpio1_config,
83 },
84 .num_resources = ARRAY_SIZE(omap7xx_gpio1_resources),
85 .resource = omap7xx_gpio1_resources,
86};
87
88/* gpio2 */
89static struct __initdata resource omap7xx_gpio2_resources[] = {
90 {
91 .start = OMAP7XX_GPIO2_BASE,
92 .end = OMAP7XX_GPIO2_BASE + SZ_2K - 1,
93 .flags = IORESOURCE_MEM,
94 },
95 {
96 .start = INT_7XX_GPIO_BANK2,
97 .flags = IORESOURCE_IRQ,
98 },
99};
100
101static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = {
102 .virtual_irq_start = IH_GPIO_BASE + 32,
103 .bank_type = METHOD_GPIO_7XX,
104 .bank_width = 32,
105};
106
107static struct __initdata platform_device omap7xx_gpio2 = {
108 .name = "omap_gpio",
109 .id = 2,
110 .dev = {
111 .platform_data = &omap7xx_gpio2_config,
112 },
113 .num_resources = ARRAY_SIZE(omap7xx_gpio2_resources),
114 .resource = omap7xx_gpio2_resources,
115};
116
117/* gpio3 */
118static struct __initdata resource omap7xx_gpio3_resources[] = {
119 {
120 .start = OMAP7XX_GPIO3_BASE,
121 .end = OMAP7XX_GPIO3_BASE + SZ_2K - 1,
122 .flags = IORESOURCE_MEM,
123 },
124 {
125 .start = INT_7XX_GPIO_BANK3,
126 .flags = IORESOURCE_IRQ,
127 },
128};
129
130static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = {
131 .virtual_irq_start = IH_GPIO_BASE + 64,
132 .bank_type = METHOD_GPIO_7XX,
133 .bank_width = 32,
134};
135
136static struct __initdata platform_device omap7xx_gpio3 = {
137 .name = "omap_gpio",
138 .id = 3,
139 .dev = {
140 .platform_data = &omap7xx_gpio3_config,
141 },
142 .num_resources = ARRAY_SIZE(omap7xx_gpio3_resources),
143 .resource = omap7xx_gpio3_resources,
144};
145
146/* gpio4 */
147static struct __initdata resource omap7xx_gpio4_resources[] = {
148 {
149 .start = OMAP7XX_GPIO4_BASE,
150 .end = OMAP7XX_GPIO4_BASE + SZ_2K - 1,
151 .flags = IORESOURCE_MEM,
152 },
153 {
154 .start = INT_7XX_GPIO_BANK4,
155 .flags = IORESOURCE_IRQ,
156 },
157};
158
159static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = {
160 .virtual_irq_start = IH_GPIO_BASE + 96,
161 .bank_type = METHOD_GPIO_7XX,
162 .bank_width = 32,
163};
164
165static struct __initdata platform_device omap7xx_gpio4 = {
166 .name = "omap_gpio",
167 .id = 4,
168 .dev = {
169 .platform_data = &omap7xx_gpio4_config,
170 },
171 .num_resources = ARRAY_SIZE(omap7xx_gpio4_resources),
172 .resource = omap7xx_gpio4_resources,
173};
174
175/* gpio5 */
176static struct __initdata resource omap7xx_gpio5_resources[] = {
177 {
178 .start = OMAP7XX_GPIO5_BASE,
179 .end = OMAP7XX_GPIO5_BASE + SZ_2K - 1,
180 .flags = IORESOURCE_MEM,
181 },
182 {
183 .start = INT_7XX_GPIO_BANK5,
184 .flags = IORESOURCE_IRQ,
185 },
186};
187
188static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = {
189 .virtual_irq_start = IH_GPIO_BASE + 128,
190 .bank_type = METHOD_GPIO_7XX,
191 .bank_width = 32,
192};
193
194static struct __initdata platform_device omap7xx_gpio5 = {
195 .name = "omap_gpio",
196 .id = 5,
197 .dev = {
198 .platform_data = &omap7xx_gpio5_config,
199 },
200 .num_resources = ARRAY_SIZE(omap7xx_gpio5_resources),
201 .resource = omap7xx_gpio5_resources,
202};
203
204/* gpio6 */
205static struct __initdata resource omap7xx_gpio6_resources[] = {
206 {
207 .start = OMAP7XX_GPIO6_BASE,
208 .end = OMAP7XX_GPIO6_BASE + SZ_2K - 1,
209 .flags = IORESOURCE_MEM,
210 },
211 {
212 .start = INT_7XX_GPIO_BANK6,
213 .flags = IORESOURCE_IRQ,
214 },
215};
216
217static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = {
218 .virtual_irq_start = IH_GPIO_BASE + 160,
219 .bank_type = METHOD_GPIO_7XX,
220 .bank_width = 32,
221};
222
223static struct __initdata platform_device omap7xx_gpio6 = {
224 .name = "omap_gpio",
225 .id = 6,
226 .dev = {
227 .platform_data = &omap7xx_gpio6_config,
228 },
229 .num_resources = ARRAY_SIZE(omap7xx_gpio6_resources),
230 .resource = omap7xx_gpio6_resources,
231};
232
233static struct __initdata platform_device * omap7xx_gpio_dev[] = {
234 &omap7xx_mpu_gpio,
235 &omap7xx_gpio1,
236 &omap7xx_gpio2,
237 &omap7xx_gpio3,
238 &omap7xx_gpio4,
239 &omap7xx_gpio5,
240 &omap7xx_gpio6,
241};
242
243/*
244 * omap7xx_gpio_init needs to be done before
245 * machine_init functions access gpio APIs.
246 * Hence omap7xx_gpio_init is a postcore_initcall.
247 */
248static int __init omap7xx_gpio_init(void)
249{
250 int i;
251
252 if (!cpu_is_omap7xx())
253 return -EINVAL;
254
255 for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++)
256 platform_device_register(omap7xx_gpio_dev[i]);
257
258 gpio_bank_count = ARRAY_SIZE(omap7xx_gpio_dev);
259
260 return 0;
261}
262postcore_initcall(omap7xx_gpio_init);
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ce7b1f017670..fbc87395a025 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
4 4
5# Common support 5# Common support
6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \ 6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
7 common.o 7 common.o gpio.o
8 8
9omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o 9omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o
10hwmod-common = omap_hwmod.o \ 10hwmod-common = omap_hwmod.o \
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index ee7ac993a277..c00f26aca0d6 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -145,7 +145,6 @@ static void __init omap_2430sdp_init_irq(void)
145 omap_board_config_size = ARRAY_SIZE(sdp2430_config); 145 omap_board_config_size = ARRAY_SIZE(sdp2430_config);
146 omap2_init_common_hw(NULL, NULL); 146 omap2_init_common_hw(NULL, NULL);
147 omap_init_irq(); 147 omap_init_irq();
148 omap_gpio_init();
149} 148}
150 149
151static struct twl4030_gpio_platform_data sdp2430_gpio_data = { 150static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index ad4cb262719e..869fb133c207 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -328,7 +328,6 @@ static void __init omap_3430sdp_init_irq(void)
328 omap3_pm_init_cpuidle(omap3_cpuidle_params_table); 328 omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
329 omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL); 329 omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
330 omap_init_irq(); 330 omap_init_irq();
331 omap_gpio_init();
332} 331}
333 332
334static int sdp3430_batt_table[] = { 333static int sdp3430_batt_table[] = {
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 4cd96d70b9c7..a8d35ba7781e 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -76,7 +76,6 @@ static void __init omap_sdp_init_irq(void)
76 omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params, 76 omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params,
77 h8mbx00u0mer0em_sdrc_params); 77 h8mbx00u0mer0em_sdrc_params);
78 omap_init_irq(); 78 omap_init_irq();
79 omap_gpio_init();
80} 79}
81 80
82#ifdef CONFIG_OMAP_MUX 81#ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 94d989bee8ad..8842ec5e51e3 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -223,7 +223,6 @@ static void __init omap_4430sdp_init_irq(void)
223 omap2_gp_clockevent_set_gptimer(1); 223 omap2_gp_clockevent_set_gptimer(1);
224#endif 224#endif
225 gic_init_irq(); 225 gic_init_irq();
226 omap_gpio_init();
227} 226}
228 227
229static struct omap_musb_board_data musb_board_data = { 228static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 13ead330e389..8ba404770e75 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -19,7 +19,6 @@
19 19
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/gpio.h>
23 22
24#include <mach/hardware.h> 23#include <mach/hardware.h>
25#include <asm/mach-types.h> 24#include <asm/mach-types.h>
@@ -50,7 +49,6 @@ static void __init am3517_crane_init_irq(void)
50 49
51 omap2_init_common_hw(NULL, NULL); 50 omap2_init_common_hw(NULL, NULL);
52 omap_init_irq(); 51 omap_init_irq();
53 omap_gpio_init();
54} 52}
55 53
56static void __init am3517_crane_init(void) 54static void __init am3517_crane_init(void)
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 63035d8231ef..86867138f1e4 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -392,7 +392,6 @@ static void __init am3517_evm_init_irq(void)
392 392
393 omap2_init_common_hw(NULL, NULL); 393 omap2_init_common_hw(NULL, NULL);
394 omap_init_irq(); 394 omap_init_irq();
395 omap_gpio_init();
396} 395}
397 396
398static struct omap_musb_board_data musb_board_data = { 397static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index b01d6e422d7a..4e91f453ea90 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -280,8 +280,6 @@ static void __init omap_apollon_init_irq(void)
280 omap_board_config_size = ARRAY_SIZE(apollon_config); 280 omap_board_config_size = ARRAY_SIZE(apollon_config);
281 omap2_init_common_hw(NULL, NULL); 281 omap2_init_common_hw(NULL, NULL);
282 omap_init_irq(); 282 omap_init_irq();
283 omap_gpio_init();
284 apollon_init_smc91x();
285} 283}
286 284
287static void __init apollon_led_init(void) 285static void __init apollon_led_init(void)
@@ -322,6 +320,7 @@ static void __init omap_apollon_init(void)
322 320
323 omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); 321 omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
324 322
323 apollon_init_smc91x();
325 apollon_led_init(); 324 apollon_led_init();
326 apollon_flash_init(); 325 apollon_flash_init();
327 apollon_usb_init(); 326 apollon_usb_init();
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 63f764e2af3f..78b67fb790bf 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -686,7 +686,6 @@ static void __init cm_t35_init_irq(void)
686 omap2_init_common_hw(mt46h32m32lf6_sdrc_params, 686 omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
687 mt46h32m32lf6_sdrc_params); 687 mt46h32m32lf6_sdrc_params);
688 omap_init_irq(); 688 omap_init_irq();
689 omap_gpio_init();
690} 689}
691 690
692static struct omap_board_mux board_mux[] __initdata = { 691static struct omap_board_mux board_mux[] __initdata = {
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 1dd303e9a267..7ee23dab84fe 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -250,7 +250,6 @@ static void __init cm_t3517_init_irq(void)
250 250
251 omap2_init_common_hw(NULL, NULL); 251 omap2_init_common_hw(NULL, NULL);
252 omap_init_irq(); 252 omap_init_irq();
253 omap_gpio_init();
254} 253}
255 254
256static struct omap_board_mux board_mux[] __initdata = { 255static struct omap_board_mux board_mux[] __initdata = {
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 53ac762518bd..a30a7fce8cbf 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -450,7 +450,6 @@ static void __init devkit8000_init_irq(void)
450#ifdef CONFIG_OMAP_32K_TIMER 450#ifdef CONFIG_OMAP_32K_TIMER
451 omap2_gp_clockevent_set_gptimer(12); 451 omap2_gp_clockevent_set_gptimer(12);
452#endif 452#endif
453 omap_gpio_init();
454} 453}
455 454
456static void __init devkit8000_ads7846_init(void) 455static void __init devkit8000_ads7846_init(void)
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 263da1da181c..9ec77a4a6b88 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -293,7 +293,6 @@ static void __init omap_h4_init_irq(void)
293 omap_board_config_size = ARRAY_SIZE(h4_config); 293 omap_board_config_size = ARRAY_SIZE(h4_config);
294 omap2_init_common_hw(NULL, NULL); 294 omap2_init_common_hw(NULL, NULL);
295 omap_init_irq(); 295 omap_init_irq();
296 omap_gpio_init();
297 h4_init_flash(); 296 h4_init_flash();
298} 297}
299 298
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 6f8f9b4533f9..59b95f2389dd 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -484,7 +484,6 @@ static void __init igep2_init_irq(void)
484{ 484{
485 omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); 485 omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params);
486 omap_init_irq(); 486 omap_init_irq();
487 omap_gpio_init();
488} 487}
489 488
490static struct twl4030_codec_audio_data igep2_audio_data = { 489static struct twl4030_codec_audio_data igep2_audio_data = {
diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c
index 8dc6ed3aa377..886f193a8415 100644
--- a/arch/arm/mach-omap2/board-igep0030.c
+++ b/arch/arm/mach-omap2/board-igep0030.c
@@ -291,7 +291,6 @@ static void __init igep3_init_irq(void)
291{ 291{
292 omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); 292 omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params);
293 omap_init_irq(); 293 omap_init_irq();
294 omap_gpio_init();
295} 294}
296 295
297static struct twl4030_platform_data igep3_twl4030_pdata = { 296static struct twl4030_platform_data igep3_twl4030_pdata = {
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 84b4ea67d156..7455b0aadf86 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -294,8 +294,6 @@ static void __init omap_ldp_init_irq(void)
294 omap_board_config_size = ARRAY_SIZE(ldp_config); 294 omap_board_config_size = ARRAY_SIZE(ldp_config);
295 omap2_init_common_hw(NULL, NULL); 295 omap2_init_common_hw(NULL, NULL);
296 omap_init_irq(); 296 omap_init_irq();
297 omap_gpio_init();
298 ldp_init_smsc911x();
299} 297}
300 298
301static struct twl4030_usb_data ldp_usb_data = { 299static struct twl4030_usb_data ldp_usb_data = {
@@ -424,6 +422,7 @@ static struct mtd_partition ldp_nand_partitions[] = {
424static void __init omap_ldp_init(void) 422static void __init omap_ldp_init(void)
425{ 423{
426 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 424 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
425 ldp_init_smsc911x();
427 omap_i2c_init(); 426 omap_i2c_init();
428 platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices)); 427 platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
429 ts_gpio = 54; 428 ts_gpio = 54;
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 0a4bc7715c38..d4ce96316e3b 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -633,7 +633,6 @@ static void __init n8x0_init_irq(void)
633{ 633{
634 omap2_init_common_hw(NULL, NULL); 634 omap2_init_common_hw(NULL, NULL);
635 omap_init_irq(); 635 omap_init_irq();
636 omap_gpio_init();
637} 636}
638 637
639#ifdef CONFIG_OMAP_MUX 638#ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index d42c8c936053..f1a8edefa42f 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -490,7 +490,6 @@ static void __init omap3_beagle_init_irq(void)
490#ifdef CONFIG_OMAP_32K_TIMER 490#ifdef CONFIG_OMAP_32K_TIMER
491 omap2_gp_clockevent_set_gptimer(12); 491 omap2_gp_clockevent_set_gptimer(12);
492#endif 492#endif
493 omap_gpio_init();
494} 493}
495 494
496static struct platform_device *omap3_beagle_devices[] __initdata = { 495static struct platform_device *omap3_beagle_devices[] __initdata = {
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 8f1e69a92056..21ffc5c587a1 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -625,7 +625,6 @@ static void __init omap3_evm_init_irq(void)
625 omap_board_config_size = ARRAY_SIZE(omap3_evm_config); 625 omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
626 omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL); 626 omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
627 omap_init_irq(); 627 omap_init_irq();
628 omap_gpio_init();
629} 628}
630 629
631static struct platform_device *omap3_evm_devices[] __initdata = { 630static struct platform_device *omap3_evm_devices[] __initdata = {
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index e2e9562f4de9..cfd618d3bda8 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -199,7 +199,6 @@ static void __init omap3logic_init_irq(void)
199{ 199{
200 omap2_init_common_hw(NULL, NULL); 200 omap2_init_common_hw(NULL, NULL);
201 omap_init_irq(); 201 omap_init_irq();
202 omap_gpio_init();
203} 202}
204 203
205#ifdef CONFIG_OMAP_MUX 204#ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 445b15843212..de8df58b8f1d 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -639,7 +639,6 @@ static void __init omap3pandora_init_irq(void)
639 omap2_init_common_hw(mt46h32m32lf6_sdrc_params, 639 omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
640 mt46h32m32lf6_sdrc_params); 640 mt46h32m32lf6_sdrc_params);
641 omap_init_irq(); 641 omap_init_irq();
642 omap_gpio_init();
643} 642}
644 643
645static void pandora_wl1251_set_power(bool enable) 644static void pandora_wl1251_set_power(bool enable)
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index ba65fe8a9e10..1af344b872bc 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -589,7 +589,6 @@ static void __init omap3_stalker_init_irq(void)
589#ifdef CONFIG_OMAP_32K_TIMER 589#ifdef CONFIG_OMAP_32K_TIMER
590 omap2_gp_clockevent_set_gptimer(12); 590 omap2_gp_clockevent_set_gptimer(12);
591#endif 591#endif
592 omap_gpio_init();
593} 592}
594 593
595static struct platform_device *omap3_stalker_devices[] __initdata = { 594static struct platform_device *omap3_stalker_devices[] __initdata = {
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 8d530a607f85..baa72c507d4c 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -426,7 +426,6 @@ static void __init omap3_touchbook_init_irq(void)
426#ifdef CONFIG_OMAP_32K_TIMER 426#ifdef CONFIG_OMAP_32K_TIMER
427 omap2_gp_clockevent_set_gptimer(12); 427 omap2_gp_clockevent_set_gptimer(12);
428#endif 428#endif
429 omap_gpio_init();
430} 429}
431 430
432static struct platform_device *omap3_touchbook_devices[] __initdata = { 431static struct platform_device *omap3_touchbook_devices[] __initdata = {
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 801f8146b00c..38f942beb121 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -79,7 +79,6 @@ static void __init omap4_panda_init_irq(void)
79{ 79{
80 omap2_init_common_hw(NULL, NULL); 80 omap2_init_common_hw(NULL, NULL);
81 gic_init_irq(); 81 gic_init_irq();
82 omap_gpio_init();
83} 82}
84 83
85static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { 84static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 133b5ead830d..b75bdcd47117 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -416,7 +416,6 @@ static void __init overo_init_irq(void)
416 omap2_init_common_hw(mt46h32m32lf6_sdrc_params, 416 omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
417 mt46h32m32lf6_sdrc_params); 417 mt46h32m32lf6_sdrc_params);
418 omap_init_irq(); 418 omap_init_irq();
419 omap_gpio_init();
420} 419}
421 420
422static struct platform_device *overo_devices[] __initdata = { 421static struct platform_device *overo_devices[] __initdata = {
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index f3b6e103b01c..6635142d7d07 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -108,7 +108,6 @@ static void __init rx51_init_irq(void)
108 sdrc_params = rx51_get_sdram_timings(); 108 sdrc_params = rx51_get_sdram_timings();
109 omap2_init_common_hw(sdrc_params, sdrc_params); 109 omap2_init_common_hw(sdrc_params, sdrc_params);
110 omap_init_irq(); 110 omap_init_irq();
111 omap_gpio_init();
112} 111}
113 112
114extern void __init rx51_peripherals_init(void); 113extern void __init rx51_peripherals_init(void);
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 27979fd527d3..0dff9deaa896 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -43,7 +43,6 @@ static void __init omap_zoom_init_irq(void)
43 h8mbx00u0mer0em_sdrc_params); 43 h8mbx00u0mer0em_sdrc_params);
44 44
45 omap_init_irq(); 45 omap_init_irq();
46 omap_gpio_init();
47} 46}
48 47
49#ifdef CONFIG_OMAP_MUX 48#ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
new file mode 100644
index 000000000000..413de18c1d2b
--- /dev/null
+++ b/arch/arm/mach-omap2/gpio.c
@@ -0,0 +1,104 @@
1/*
2 * OMAP2+ specific gpio initialization
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Author:
7 * Charulatha V <charu@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/gpio.h>
20#include <linux/err.h>
21#include <linux/slab.h>
22#include <linux/interrupt.h>
23
24#include <plat/omap_hwmod.h>
25#include <plat/omap_device.h>
26
27static struct omap_device_pm_latency omap_gpio_latency[] = {
28 [0] = {
29 .deactivate_func = omap_device_idle_hwmods,
30 .activate_func = omap_device_enable_hwmods,
31 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
32 },
33};
34
35static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
36{
37 struct omap_device *od;
38 struct omap_gpio_platform_data *pdata;
39 struct omap_gpio_dev_attr *dev_attr;
40 char *name = "omap_gpio";
41 int id;
42
43 /*
44 * extract the device id from name field available in the
45 * hwmod database and use the same for constructing ids for
46 * gpio devices.
47 * CAUTION: Make sure the name in the hwmod database does
48 * not change. If changed, make corresponding change here
49 * or make use of static variable mechanism to handle this.
50 */
51 sscanf(oh->name, "gpio%d", &id);
52
53 pdata = kzalloc(sizeof(struct omap_gpio_platform_data), GFP_KERNEL);
54 if (!pdata) {
55 pr_err("gpio%d: Memory allocation failed\n", id);
56 return -ENOMEM;
57 }
58
59 dev_attr = (struct omap_gpio_dev_attr *)oh->dev_attr;
60 pdata->bank_width = dev_attr->bank_width;
61 pdata->dbck_flag = dev_attr->dbck_flag;
62 pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
63
64 switch (oh->class->rev) {
65 case 0:
66 case 1:
67 pdata->bank_type = METHOD_GPIO_24XX;
68 break;
69 case 2:
70 pdata->bank_type = METHOD_GPIO_44XX;
71 break;
72 default:
73 WARN(1, "Invalid gpio bank_type\n");
74 kfree(pdata);
75 return -EINVAL;
76 }
77
78 od = omap_device_build(name, id - 1, oh, pdata,
79 sizeof(*pdata), omap_gpio_latency,
80 ARRAY_SIZE(omap_gpio_latency),
81 false);
82 kfree(pdata);
83
84 if (IS_ERR(od)) {
85 WARN(1, "Cant build omap_device for %s:%s.\n",
86 name, oh->name);
87 return PTR_ERR(od);
88 }
89
90 gpio_bank_count++;
91 return 0;
92}
93
94/*
95 * gpio_init needs to be done before
96 * machine_init functions access gpio APIs.
97 * Hence gpio_init is a postcore_initcall.
98 */
99static int __init omap2_gpio_init(void)
100{
101 return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init,
102 NULL);
103}
104postcore_initcall(omap2_gpio_init);
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a1a3dd6303b4..d95342599793 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -17,7 +17,7 @@
17#include <plat/dma.h> 17#include <plat/dma.h>
18#include <plat/serial.h> 18#include <plat/serial.h>
19#include <plat/i2c.h> 19#include <plat/i2c.h>
20#include <plat/omap24xx.h> 20#include <plat/gpio.h>
21 21
22#include "omap_hwmod_common_data.h" 22#include "omap_hwmod_common_data.h"
23 23
@@ -38,6 +38,10 @@ static struct omap_hwmod omap2420_iva_hwmod;
38static struct omap_hwmod omap2420_l3_main_hwmod; 38static struct omap_hwmod omap2420_l3_main_hwmod;
39static struct omap_hwmod omap2420_l4_core_hwmod; 39static struct omap_hwmod omap2420_l4_core_hwmod;
40static struct omap_hwmod omap2420_wd_timer2_hwmod; 40static struct omap_hwmod omap2420_wd_timer2_hwmod;
41static struct omap_hwmod omap2420_gpio1_hwmod;
42static struct omap_hwmod omap2420_gpio2_hwmod;
43static struct omap_hwmod omap2420_gpio3_hwmod;
44static struct omap_hwmod omap2420_gpio4_hwmod;
41 45
42/* L3 -> L4_CORE interface */ 46/* L3 -> L4_CORE interface */
43static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { 47static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
@@ -557,6 +561,224 @@ static struct omap_hwmod omap2420_i2c2_hwmod = {
557 .flags = HWMOD_16BIT_REG, 561 .flags = HWMOD_16BIT_REG,
558}; 562};
559 563
564/* l4_wkup -> gpio1 */
565static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
566 {
567 .pa_start = 0x48018000,
568 .pa_end = 0x480181ff,
569 .flags = ADDR_TYPE_RT
570 },
571};
572
573static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
574 .master = &omap2420_l4_wkup_hwmod,
575 .slave = &omap2420_gpio1_hwmod,
576 .clk = "gpios_ick",
577 .addr = omap2420_gpio1_addr_space,
578 .addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space),
579 .user = OCP_USER_MPU | OCP_USER_SDMA,
580};
581
582/* l4_wkup -> gpio2 */
583static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
584 {
585 .pa_start = 0x4801a000,
586 .pa_end = 0x4801a1ff,
587 .flags = ADDR_TYPE_RT
588 },
589};
590
591static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
592 .master = &omap2420_l4_wkup_hwmod,
593 .slave = &omap2420_gpio2_hwmod,
594 .clk = "gpios_ick",
595 .addr = omap2420_gpio2_addr_space,
596 .addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space),
597 .user = OCP_USER_MPU | OCP_USER_SDMA,
598};
599
600/* l4_wkup -> gpio3 */
601static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
602 {
603 .pa_start = 0x4801c000,
604 .pa_end = 0x4801c1ff,
605 .flags = ADDR_TYPE_RT
606 },
607};
608
609static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
610 .master = &omap2420_l4_wkup_hwmod,
611 .slave = &omap2420_gpio3_hwmod,
612 .clk = "gpios_ick",
613 .addr = omap2420_gpio3_addr_space,
614 .addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space),
615 .user = OCP_USER_MPU | OCP_USER_SDMA,
616};
617
618/* l4_wkup -> gpio4 */
619static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
620 {
621 .pa_start = 0x4801e000,
622 .pa_end = 0x4801e1ff,
623 .flags = ADDR_TYPE_RT
624 },
625};
626
627static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
628 .master = &omap2420_l4_wkup_hwmod,
629 .slave = &omap2420_gpio4_hwmod,
630 .clk = "gpios_ick",
631 .addr = omap2420_gpio4_addr_space,
632 .addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space),
633 .user = OCP_USER_MPU | OCP_USER_SDMA,
634};
635
636/* gpio dev_attr */
637static struct omap_gpio_dev_attr gpio_dev_attr = {
638 .bank_width = 32,
639 .dbck_flag = false,
640};
641
642static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
643 .rev_offs = 0x0000,
644 .sysc_offs = 0x0010,
645 .syss_offs = 0x0014,
646 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
647 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
648 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
649 .sysc_fields = &omap_hwmod_sysc_type1,
650};
651
652/*
653 * 'gpio' class
654 * general purpose io module
655 */
656static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
657 .name = "gpio",
658 .sysc = &omap242x_gpio_sysc,
659 .rev = 0,
660};
661
662/* gpio1 */
663static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
664 { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
665};
666
667static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
668 &omap2420_l4_wkup__gpio1,
669};
670
671static struct omap_hwmod omap2420_gpio1_hwmod = {
672 .name = "gpio1",
673 .mpu_irqs = omap242x_gpio1_irqs,
674 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs),
675 .main_clk = "gpios_fck",
676 .prcm = {
677 .omap2 = {
678 .prcm_reg_id = 1,
679 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
680 .module_offs = WKUP_MOD,
681 .idlest_reg_id = 1,
682 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
683 },
684 },
685 .slaves = omap2420_gpio1_slaves,
686 .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
687 .class = &omap242x_gpio_hwmod_class,
688 .dev_attr = &gpio_dev_attr,
689 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
690};
691
692/* gpio2 */
693static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
694 { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
695};
696
697static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
698 &omap2420_l4_wkup__gpio2,
699};
700
701static struct omap_hwmod omap2420_gpio2_hwmod = {
702 .name = "gpio2",
703 .mpu_irqs = omap242x_gpio2_irqs,
704 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs),
705 .main_clk = "gpios_fck",
706 .prcm = {
707 .omap2 = {
708 .prcm_reg_id = 1,
709 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
710 .module_offs = WKUP_MOD,
711 .idlest_reg_id = 1,
712 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
713 },
714 },
715 .slaves = omap2420_gpio2_slaves,
716 .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
717 .class = &omap242x_gpio_hwmod_class,
718 .dev_attr = &gpio_dev_attr,
719 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
720};
721
722/* gpio3 */
723static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
724 { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
725};
726
727static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
728 &omap2420_l4_wkup__gpio3,
729};
730
731static struct omap_hwmod omap2420_gpio3_hwmod = {
732 .name = "gpio3",
733 .mpu_irqs = omap242x_gpio3_irqs,
734 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs),
735 .main_clk = "gpios_fck",
736 .prcm = {
737 .omap2 = {
738 .prcm_reg_id = 1,
739 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
740 .module_offs = WKUP_MOD,
741 .idlest_reg_id = 1,
742 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
743 },
744 },
745 .slaves = omap2420_gpio3_slaves,
746 .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
747 .class = &omap242x_gpio_hwmod_class,
748 .dev_attr = &gpio_dev_attr,
749 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
750};
751
752/* gpio4 */
753static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
754 { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
755};
756
757static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
758 &omap2420_l4_wkup__gpio4,
759};
760
761static struct omap_hwmod omap2420_gpio4_hwmod = {
762 .name = "gpio4",
763 .mpu_irqs = omap242x_gpio4_irqs,
764 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs),
765 .main_clk = "gpios_fck",
766 .prcm = {
767 .omap2 = {
768 .prcm_reg_id = 1,
769 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
770 .module_offs = WKUP_MOD,
771 .idlest_reg_id = 1,
772 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
773 },
774 },
775 .slaves = omap2420_gpio4_slaves,
776 .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
777 .class = &omap242x_gpio_hwmod_class,
778 .dev_attr = &gpio_dev_attr,
779 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
780};
781
560static __initdata struct omap_hwmod *omap2420_hwmods[] = { 782static __initdata struct omap_hwmod *omap2420_hwmods[] = {
561 &omap2420_l3_main_hwmod, 783 &omap2420_l3_main_hwmod,
562 &omap2420_l4_core_hwmod, 784 &omap2420_l4_core_hwmod,
@@ -569,6 +791,12 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
569 &omap2420_uart3_hwmod, 791 &omap2420_uart3_hwmod,
570 &omap2420_i2c1_hwmod, 792 &omap2420_i2c1_hwmod,
571 &omap2420_i2c2_hwmod, 793 &omap2420_i2c2_hwmod,
794
795 /* gpio class */
796 &omap2420_gpio1_hwmod,
797 &omap2420_gpio2_hwmod,
798 &omap2420_gpio3_hwmod,
799 &omap2420_gpio4_hwmod,
572 NULL, 800 NULL,
573}; 801};
574 802
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 7cf0d3ab2a4a..f68409e9fd3e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -17,7 +17,7 @@
17#include <plat/dma.h> 17#include <plat/dma.h>
18#include <plat/serial.h> 18#include <plat/serial.h>
19#include <plat/i2c.h> 19#include <plat/i2c.h>
20#include <plat/omap24xx.h> 20#include <plat/gpio.h>
21 21
22#include "omap_hwmod_common_data.h" 22#include "omap_hwmod_common_data.h"
23 23
@@ -38,6 +38,11 @@ static struct omap_hwmod omap2430_iva_hwmod;
38static struct omap_hwmod omap2430_l3_main_hwmod; 38static struct omap_hwmod omap2430_l3_main_hwmod;
39static struct omap_hwmod omap2430_l4_core_hwmod; 39static struct omap_hwmod omap2430_l4_core_hwmod;
40static struct omap_hwmod omap2430_wd_timer2_hwmod; 40static struct omap_hwmod omap2430_wd_timer2_hwmod;
41static struct omap_hwmod omap2430_gpio1_hwmod;
42static struct omap_hwmod omap2430_gpio2_hwmod;
43static struct omap_hwmod omap2430_gpio3_hwmod;
44static struct omap_hwmod omap2430_gpio4_hwmod;
45static struct omap_hwmod omap2430_gpio5_hwmod;
41 46
42/* L3 -> L4_CORE interface */ 47/* L3 -> L4_CORE interface */
43static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { 48static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@@ -569,6 +574,272 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
569 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 574 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
570}; 575};
571 576
577/* l4_wkup -> gpio1 */
578static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
579 {
580 .pa_start = 0x4900C000,
581 .pa_end = 0x4900C1ff,
582 .flags = ADDR_TYPE_RT
583 },
584};
585
586static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
587 .master = &omap2430_l4_wkup_hwmod,
588 .slave = &omap2430_gpio1_hwmod,
589 .clk = "gpios_ick",
590 .addr = omap2430_gpio1_addr_space,
591 .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space),
592 .user = OCP_USER_MPU | OCP_USER_SDMA,
593};
594
595/* l4_wkup -> gpio2 */
596static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
597 {
598 .pa_start = 0x4900E000,
599 .pa_end = 0x4900E1ff,
600 .flags = ADDR_TYPE_RT
601 },
602};
603
604static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
605 .master = &omap2430_l4_wkup_hwmod,
606 .slave = &omap2430_gpio2_hwmod,
607 .clk = "gpios_ick",
608 .addr = omap2430_gpio2_addr_space,
609 .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space),
610 .user = OCP_USER_MPU | OCP_USER_SDMA,
611};
612
613/* l4_wkup -> gpio3 */
614static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
615 {
616 .pa_start = 0x49010000,
617 .pa_end = 0x490101ff,
618 .flags = ADDR_TYPE_RT
619 },
620};
621
622static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
623 .master = &omap2430_l4_wkup_hwmod,
624 .slave = &omap2430_gpio3_hwmod,
625 .clk = "gpios_ick",
626 .addr = omap2430_gpio3_addr_space,
627 .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space),
628 .user = OCP_USER_MPU | OCP_USER_SDMA,
629};
630
631/* l4_wkup -> gpio4 */
632static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
633 {
634 .pa_start = 0x49012000,
635 .pa_end = 0x490121ff,
636 .flags = ADDR_TYPE_RT
637 },
638};
639
640static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
641 .master = &omap2430_l4_wkup_hwmod,
642 .slave = &omap2430_gpio4_hwmod,
643 .clk = "gpios_ick",
644 .addr = omap2430_gpio4_addr_space,
645 .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space),
646 .user = OCP_USER_MPU | OCP_USER_SDMA,
647};
648
649/* l4_core -> gpio5 */
650static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
651 {
652 .pa_start = 0x480B6000,
653 .pa_end = 0x480B61ff,
654 .flags = ADDR_TYPE_RT
655 },
656};
657
658static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
659 .master = &omap2430_l4_core_hwmod,
660 .slave = &omap2430_gpio5_hwmod,
661 .clk = "gpio5_ick",
662 .addr = omap2430_gpio5_addr_space,
663 .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space),
664 .user = OCP_USER_MPU | OCP_USER_SDMA,
665};
666
667/* gpio dev_attr */
668static struct omap_gpio_dev_attr gpio_dev_attr = {
669 .bank_width = 32,
670 .dbck_flag = false,
671};
672
673static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
674 .rev_offs = 0x0000,
675 .sysc_offs = 0x0010,
676 .syss_offs = 0x0014,
677 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
678 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
679 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
680 .sysc_fields = &omap_hwmod_sysc_type1,
681};
682
683/*
684 * 'gpio' class
685 * general purpose io module
686 */
687static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
688 .name = "gpio",
689 .sysc = &omap243x_gpio_sysc,
690 .rev = 0,
691};
692
693/* gpio1 */
694static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
695 { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
696};
697
698static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
699 &omap2430_l4_wkup__gpio1,
700};
701
702static struct omap_hwmod omap2430_gpio1_hwmod = {
703 .name = "gpio1",
704 .mpu_irqs = omap243x_gpio1_irqs,
705 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs),
706 .main_clk = "gpios_fck",
707 .prcm = {
708 .omap2 = {
709 .prcm_reg_id = 1,
710 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
711 .module_offs = WKUP_MOD,
712 .idlest_reg_id = 1,
713 .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
714 },
715 },
716 .slaves = omap2430_gpio1_slaves,
717 .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
718 .class = &omap243x_gpio_hwmod_class,
719 .dev_attr = &gpio_dev_attr,
720 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
721};
722
723/* gpio2 */
724static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
725 { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
726};
727
728static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
729 &omap2430_l4_wkup__gpio2,
730};
731
732static struct omap_hwmod omap2430_gpio2_hwmod = {
733 .name = "gpio2",
734 .mpu_irqs = omap243x_gpio2_irqs,
735 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs),
736 .main_clk = "gpios_fck",
737 .prcm = {
738 .omap2 = {
739 .prcm_reg_id = 1,
740 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
741 .module_offs = WKUP_MOD,
742 .idlest_reg_id = 1,
743 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
744 },
745 },
746 .slaves = omap2430_gpio2_slaves,
747 .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
748 .class = &omap243x_gpio_hwmod_class,
749 .dev_attr = &gpio_dev_attr,
750 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
751};
752
753/* gpio3 */
754static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
755 { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
756};
757
758static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
759 &omap2430_l4_wkup__gpio3,
760};
761
762static struct omap_hwmod omap2430_gpio3_hwmod = {
763 .name = "gpio3",
764 .mpu_irqs = omap243x_gpio3_irqs,
765 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs),
766 .main_clk = "gpios_fck",
767 .prcm = {
768 .omap2 = {
769 .prcm_reg_id = 1,
770 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
771 .module_offs = WKUP_MOD,
772 .idlest_reg_id = 1,
773 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
774 },
775 },
776 .slaves = omap2430_gpio3_slaves,
777 .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
778 .class = &omap243x_gpio_hwmod_class,
779 .dev_attr = &gpio_dev_attr,
780 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
781};
782
783/* gpio4 */
784static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
785 { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
786};
787
788static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
789 &omap2430_l4_wkup__gpio4,
790};
791
792static struct omap_hwmod omap2430_gpio4_hwmod = {
793 .name = "gpio4",
794 .mpu_irqs = omap243x_gpio4_irqs,
795 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs),
796 .main_clk = "gpios_fck",
797 .prcm = {
798 .omap2 = {
799 .prcm_reg_id = 1,
800 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
801 .module_offs = WKUP_MOD,
802 .idlest_reg_id = 1,
803 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
804 },
805 },
806 .slaves = omap2430_gpio4_slaves,
807 .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
808 .class = &omap243x_gpio_hwmod_class,
809 .dev_attr = &gpio_dev_attr,
810 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
811};
812
813/* gpio5 */
814static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
815 { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
816};
817
818static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
819 &omap2430_l4_core__gpio5,
820};
821
822static struct omap_hwmod omap2430_gpio5_hwmod = {
823 .name = "gpio5",
824 .mpu_irqs = omap243x_gpio5_irqs,
825 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs),
826 .main_clk = "gpio5_fck",
827 .prcm = {
828 .omap2 = {
829 .prcm_reg_id = 2,
830 .module_bit = OMAP2430_EN_GPIO5_SHIFT,
831 .module_offs = CORE_MOD,
832 .idlest_reg_id = 2,
833 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
834 },
835 },
836 .slaves = omap2430_gpio5_slaves,
837 .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
838 .class = &omap243x_gpio_hwmod_class,
839 .dev_attr = &gpio_dev_attr,
840 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
841};
842
572static __initdata struct omap_hwmod *omap2430_hwmods[] = { 843static __initdata struct omap_hwmod *omap2430_hwmods[] = {
573 &omap2430_l3_main_hwmod, 844 &omap2430_l3_main_hwmod,
574 &omap2430_l4_core_hwmod, 845 &omap2430_l4_core_hwmod,
@@ -581,6 +852,13 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
581 &omap2430_uart3_hwmod, 852 &omap2430_uart3_hwmod,
582 &omap2430_i2c1_hwmod, 853 &omap2430_i2c1_hwmod,
583 &omap2430_i2c2_hwmod, 854 &omap2430_i2c2_hwmod,
855
856 /* gpio class */
857 &omap2430_gpio1_hwmod,
858 &omap2430_gpio2_hwmod,
859 &omap2430_gpio3_hwmod,
860 &omap2430_gpio4_hwmod,
861 &omap2430_gpio5_hwmod,
584 NULL, 862 NULL,
585}; 863};
586 864
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index a8bed843079c..2687be10d7aa 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -20,7 +20,7 @@
20#include <plat/serial.h> 20#include <plat/serial.h>
21#include <plat/l4_3xxx.h> 21#include <plat/l4_3xxx.h>
22#include <plat/i2c.h> 22#include <plat/i2c.h>
23#include <plat/omap34xx.h> 23#include <plat/gpio.h>
24 24
25#include "omap_hwmod_common_data.h" 25#include "omap_hwmod_common_data.h"
26 26
@@ -45,6 +45,12 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
45static struct omap_hwmod omap3xxx_i2c1_hwmod; 45static struct omap_hwmod omap3xxx_i2c1_hwmod;
46static struct omap_hwmod omap3xxx_i2c2_hwmod; 46static struct omap_hwmod omap3xxx_i2c2_hwmod;
47static struct omap_hwmod omap3xxx_i2c3_hwmod; 47static struct omap_hwmod omap3xxx_i2c3_hwmod;
48static struct omap_hwmod omap3xxx_gpio1_hwmod;
49static struct omap_hwmod omap3xxx_gpio2_hwmod;
50static struct omap_hwmod omap3xxx_gpio3_hwmod;
51static struct omap_hwmod omap3xxx_gpio4_hwmod;
52static struct omap_hwmod omap3xxx_gpio5_hwmod;
53static struct omap_hwmod omap3xxx_gpio6_hwmod;
48 54
49/* L3 -> L4_CORE interface */ 55/* L3 -> L4_CORE interface */
50static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { 56static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
@@ -739,6 +745,351 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
739 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 745 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
740}; 746};
741 747
748/* l4_wkup -> gpio1 */
749static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
750 {
751 .pa_start = 0x48310000,
752 .pa_end = 0x483101ff,
753 .flags = ADDR_TYPE_RT
754 },
755};
756
757static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
758 .master = &omap3xxx_l4_wkup_hwmod,
759 .slave = &omap3xxx_gpio1_hwmod,
760 .addr = omap3xxx_gpio1_addrs,
761 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
762 .user = OCP_USER_MPU | OCP_USER_SDMA,
763};
764
765/* l4_per -> gpio2 */
766static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
767 {
768 .pa_start = 0x49050000,
769 .pa_end = 0x490501ff,
770 .flags = ADDR_TYPE_RT
771 },
772};
773
774static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
775 .master = &omap3xxx_l4_per_hwmod,
776 .slave = &omap3xxx_gpio2_hwmod,
777 .addr = omap3xxx_gpio2_addrs,
778 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
779 .user = OCP_USER_MPU | OCP_USER_SDMA,
780};
781
782/* l4_per -> gpio3 */
783static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
784 {
785 .pa_start = 0x49052000,
786 .pa_end = 0x490521ff,
787 .flags = ADDR_TYPE_RT
788 },
789};
790
791static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
792 .master = &omap3xxx_l4_per_hwmod,
793 .slave = &omap3xxx_gpio3_hwmod,
794 .addr = omap3xxx_gpio3_addrs,
795 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
796 .user = OCP_USER_MPU | OCP_USER_SDMA,
797};
798
799/* l4_per -> gpio4 */
800static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
801 {
802 .pa_start = 0x49054000,
803 .pa_end = 0x490541ff,
804 .flags = ADDR_TYPE_RT
805 },
806};
807
808static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
809 .master = &omap3xxx_l4_per_hwmod,
810 .slave = &omap3xxx_gpio4_hwmod,
811 .addr = omap3xxx_gpio4_addrs,
812 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
813 .user = OCP_USER_MPU | OCP_USER_SDMA,
814};
815
816/* l4_per -> gpio5 */
817static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
818 {
819 .pa_start = 0x49056000,
820 .pa_end = 0x490561ff,
821 .flags = ADDR_TYPE_RT
822 },
823};
824
825static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
826 .master = &omap3xxx_l4_per_hwmod,
827 .slave = &omap3xxx_gpio5_hwmod,
828 .addr = omap3xxx_gpio5_addrs,
829 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
830 .user = OCP_USER_MPU | OCP_USER_SDMA,
831};
832
833/* l4_per -> gpio6 */
834static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
835 {
836 .pa_start = 0x49058000,
837 .pa_end = 0x490581ff,
838 .flags = ADDR_TYPE_RT
839 },
840};
841
842static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
843 .master = &omap3xxx_l4_per_hwmod,
844 .slave = &omap3xxx_gpio6_hwmod,
845 .addr = omap3xxx_gpio6_addrs,
846 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
847 .user = OCP_USER_MPU | OCP_USER_SDMA,
848};
849
850/*
851 * 'gpio' class
852 * general purpose io module
853 */
854
855static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
856 .rev_offs = 0x0000,
857 .sysc_offs = 0x0010,
858 .syss_offs = 0x0014,
859 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
860 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
861 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
862 .sysc_fields = &omap_hwmod_sysc_type1,
863};
864
865static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
866 .name = "gpio",
867 .sysc = &omap3xxx_gpio_sysc,
868 .rev = 1,
869};
870
871/* gpio_dev_attr*/
872static struct omap_gpio_dev_attr gpio_dev_attr = {
873 .bank_width = 32,
874 .dbck_flag = true,
875};
876
877/* gpio1 */
878static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
879 { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
880};
881
882static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
883 { .role = "dbclk", .clk = "gpio1_dbck", },
884};
885
886static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
887 &omap3xxx_l4_wkup__gpio1,
888};
889
890static struct omap_hwmod omap3xxx_gpio1_hwmod = {
891 .name = "gpio1",
892 .mpu_irqs = omap3xxx_gpio1_irqs,
893 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
894 .main_clk = "gpio1_ick",
895 .opt_clks = gpio1_opt_clks,
896 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
897 .prcm = {
898 .omap2 = {
899 .prcm_reg_id = 1,
900 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
901 .module_offs = WKUP_MOD,
902 .idlest_reg_id = 1,
903 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
904 },
905 },
906 .slaves = omap3xxx_gpio1_slaves,
907 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
908 .class = &omap3xxx_gpio_hwmod_class,
909 .dev_attr = &gpio_dev_attr,
910 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
911};
912
913/* gpio2 */
914static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
915 { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
916};
917
918static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
919 { .role = "dbclk", .clk = "gpio2_dbck", },
920};
921
922static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
923 &omap3xxx_l4_per__gpio2,
924};
925
926static struct omap_hwmod omap3xxx_gpio2_hwmod = {
927 .name = "gpio2",
928 .mpu_irqs = omap3xxx_gpio2_irqs,
929 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
930 .main_clk = "gpio2_ick",
931 .opt_clks = gpio2_opt_clks,
932 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
933 .prcm = {
934 .omap2 = {
935 .prcm_reg_id = 1,
936 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
937 .module_offs = OMAP3430_PER_MOD,
938 .idlest_reg_id = 1,
939 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
940 },
941 },
942 .slaves = omap3xxx_gpio2_slaves,
943 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
944 .class = &omap3xxx_gpio_hwmod_class,
945 .dev_attr = &gpio_dev_attr,
946 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
947};
948
949/* gpio3 */
950static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
951 { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
952};
953
954static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
955 { .role = "dbclk", .clk = "gpio3_dbck", },
956};
957
958static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
959 &omap3xxx_l4_per__gpio3,
960};
961
962static struct omap_hwmod omap3xxx_gpio3_hwmod = {
963 .name = "gpio3",
964 .mpu_irqs = omap3xxx_gpio3_irqs,
965 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
966 .main_clk = "gpio3_ick",
967 .opt_clks = gpio3_opt_clks,
968 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
969 .prcm = {
970 .omap2 = {
971 .prcm_reg_id = 1,
972 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
973 .module_offs = OMAP3430_PER_MOD,
974 .idlest_reg_id = 1,
975 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
976 },
977 },
978 .slaves = omap3xxx_gpio3_slaves,
979 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
980 .class = &omap3xxx_gpio_hwmod_class,
981 .dev_attr = &gpio_dev_attr,
982 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
983};
984
985/* gpio4 */
986static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
987 { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
988};
989
990static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
991 { .role = "dbclk", .clk = "gpio4_dbck", },
992};
993
994static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
995 &omap3xxx_l4_per__gpio4,
996};
997
998static struct omap_hwmod omap3xxx_gpio4_hwmod = {
999 .name = "gpio4",
1000 .mpu_irqs = omap3xxx_gpio4_irqs,
1001 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
1002 .main_clk = "gpio4_ick",
1003 .opt_clks = gpio4_opt_clks,
1004 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1005 .prcm = {
1006 .omap2 = {
1007 .prcm_reg_id = 1,
1008 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1009 .module_offs = OMAP3430_PER_MOD,
1010 .idlest_reg_id = 1,
1011 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1012 },
1013 },
1014 .slaves = omap3xxx_gpio4_slaves,
1015 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1016 .class = &omap3xxx_gpio_hwmod_class,
1017 .dev_attr = &gpio_dev_attr,
1018 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1019};
1020
1021/* gpio5 */
1022static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1023 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1024};
1025
1026static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1027 { .role = "dbclk", .clk = "gpio5_dbck", },
1028};
1029
1030static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
1031 &omap3xxx_l4_per__gpio5,
1032};
1033
1034static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1035 .name = "gpio5",
1036 .mpu_irqs = omap3xxx_gpio5_irqs,
1037 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
1038 .main_clk = "gpio5_ick",
1039 .opt_clks = gpio5_opt_clks,
1040 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1041 .prcm = {
1042 .omap2 = {
1043 .prcm_reg_id = 1,
1044 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1045 .module_offs = OMAP3430_PER_MOD,
1046 .idlest_reg_id = 1,
1047 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1048 },
1049 },
1050 .slaves = omap3xxx_gpio5_slaves,
1051 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
1052 .class = &omap3xxx_gpio_hwmod_class,
1053 .dev_attr = &gpio_dev_attr,
1054 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1055};
1056
1057/* gpio6 */
1058static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1059 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
1060};
1061
1062static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1063 { .role = "dbclk", .clk = "gpio6_dbck", },
1064};
1065
1066static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
1067 &omap3xxx_l4_per__gpio6,
1068};
1069
1070static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1071 .name = "gpio6",
1072 .mpu_irqs = omap3xxx_gpio6_irqs,
1073 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
1074 .main_clk = "gpio6_ick",
1075 .opt_clks = gpio6_opt_clks,
1076 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1077 .prcm = {
1078 .omap2 = {
1079 .prcm_reg_id = 1,
1080 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1081 .module_offs = OMAP3430_PER_MOD,
1082 .idlest_reg_id = 1,
1083 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1084 },
1085 },
1086 .slaves = omap3xxx_gpio6_slaves,
1087 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
1088 .class = &omap3xxx_gpio_hwmod_class,
1089 .dev_attr = &gpio_dev_attr,
1090 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1091};
1092
742static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { 1093static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
743 &omap3xxx_l3_main_hwmod, 1094 &omap3xxx_l3_main_hwmod,
744 &omap3xxx_l4_core_hwmod, 1095 &omap3xxx_l4_core_hwmod,
@@ -754,6 +1105,14 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
754 &omap3xxx_i2c1_hwmod, 1105 &omap3xxx_i2c1_hwmod,
755 &omap3xxx_i2c2_hwmod, 1106 &omap3xxx_i2c2_hwmod,
756 &omap3xxx_i2c3_hwmod, 1107 &omap3xxx_i2c3_hwmod,
1108
1109 /* gpio class */
1110 &omap3xxx_gpio1_hwmod,
1111 &omap3xxx_gpio2_hwmod,
1112 &omap3xxx_gpio3_hwmod,
1113 &omap3xxx_gpio4_hwmod,
1114 &omap3xxx_gpio5_hwmod,
1115 &omap3xxx_gpio6_hwmod,
757 NULL, 1116 NULL,
758}; 1117};
759 1118
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 0d5c6eb7e4c1..d258936410fb 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -22,6 +22,7 @@
22 22
23#include <plat/omap_hwmod.h> 23#include <plat/omap_hwmod.h>
24#include <plat/cpu.h> 24#include <plat/cpu.h>
25#include <plat/gpio.h>
25 26
26#include "omap_hwmod_common_data.h" 27#include "omap_hwmod_common_data.h"
27 28
@@ -1043,6 +1044,338 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
1043 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1044 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1044}; 1045};
1045 1046
1047/*
1048 * 'gpio' class
1049 * general purpose io module
1050 */
1051
1052static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1053 .rev_offs = 0x0000,
1054 .sysc_offs = 0x0010,
1055 .syss_offs = 0x0114,
1056 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1057 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1058 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1059 .sysc_fields = &omap_hwmod_sysc_type1,
1060};
1061
1062static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1063 .name = "gpio",
1064 .sysc = &omap44xx_gpio_sysc,
1065 .rev = 2,
1066};
1067
1068/* gpio dev_attr */
1069static struct omap_gpio_dev_attr gpio_dev_attr = {
1070 .bank_width = 32,
1071 .dbck_flag = true,
1072};
1073
1074/* gpio1 */
1075static struct omap_hwmod omap44xx_gpio1_hwmod;
1076static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1077 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1078};
1079
1080static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1081 {
1082 .pa_start = 0x4a310000,
1083 .pa_end = 0x4a3101ff,
1084 .flags = ADDR_TYPE_RT
1085 },
1086};
1087
1088/* l4_wkup -> gpio1 */
1089static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1090 .master = &omap44xx_l4_wkup_hwmod,
1091 .slave = &omap44xx_gpio1_hwmod,
1092 .addr = omap44xx_gpio1_addrs,
1093 .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
1094 .user = OCP_USER_MPU | OCP_USER_SDMA,
1095};
1096
1097/* gpio1 slave ports */
1098static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1099 &omap44xx_l4_wkup__gpio1,
1100};
1101
1102static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1103 { .role = "dbclk", .clk = "sys_32k_ck" },
1104};
1105
1106static struct omap_hwmod omap44xx_gpio1_hwmod = {
1107 .name = "gpio1",
1108 .class = &omap44xx_gpio_hwmod_class,
1109 .mpu_irqs = omap44xx_gpio1_irqs,
1110 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
1111 .main_clk = "gpio1_ick",
1112 .prcm = {
1113 .omap4 = {
1114 .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1115 },
1116 },
1117 .opt_clks = gpio1_opt_clks,
1118 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1119 .dev_attr = &gpio_dev_attr,
1120 .slaves = omap44xx_gpio1_slaves,
1121 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
1122 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1123};
1124
1125/* gpio2 */
1126static struct omap_hwmod omap44xx_gpio2_hwmod;
1127static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1128 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1129};
1130
1131static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1132 {
1133 .pa_start = 0x48055000,
1134 .pa_end = 0x480551ff,
1135 .flags = ADDR_TYPE_RT
1136 },
1137};
1138
1139/* l4_per -> gpio2 */
1140static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1141 .master = &omap44xx_l4_per_hwmod,
1142 .slave = &omap44xx_gpio2_hwmod,
1143 .addr = omap44xx_gpio2_addrs,
1144 .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
1145 .user = OCP_USER_MPU | OCP_USER_SDMA,
1146};
1147
1148/* gpio2 slave ports */
1149static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1150 &omap44xx_l4_per__gpio2,
1151};
1152
1153static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1154 { .role = "dbclk", .clk = "sys_32k_ck" },
1155};
1156
1157static struct omap_hwmod omap44xx_gpio2_hwmod = {
1158 .name = "gpio2",
1159 .class = &omap44xx_gpio_hwmod_class,
1160 .mpu_irqs = omap44xx_gpio2_irqs,
1161 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
1162 .main_clk = "gpio2_ick",
1163 .prcm = {
1164 .omap4 = {
1165 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1166 },
1167 },
1168 .opt_clks = gpio2_opt_clks,
1169 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1170 .dev_attr = &gpio_dev_attr,
1171 .slaves = omap44xx_gpio2_slaves,
1172 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
1173 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1174};
1175
1176/* gpio3 */
1177static struct omap_hwmod omap44xx_gpio3_hwmod;
1178static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1179 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1180};
1181
1182static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1183 {
1184 .pa_start = 0x48057000,
1185 .pa_end = 0x480571ff,
1186 .flags = ADDR_TYPE_RT
1187 },
1188};
1189
1190/* l4_per -> gpio3 */
1191static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1192 .master = &omap44xx_l4_per_hwmod,
1193 .slave = &omap44xx_gpio3_hwmod,
1194 .addr = omap44xx_gpio3_addrs,
1195 .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
1196 .user = OCP_USER_MPU | OCP_USER_SDMA,
1197};
1198
1199/* gpio3 slave ports */
1200static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1201 &omap44xx_l4_per__gpio3,
1202};
1203
1204static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1205 { .role = "dbclk", .clk = "sys_32k_ck" },
1206};
1207
1208static struct omap_hwmod omap44xx_gpio3_hwmod = {
1209 .name = "gpio3",
1210 .class = &omap44xx_gpio_hwmod_class,
1211 .mpu_irqs = omap44xx_gpio3_irqs,
1212 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
1213 .main_clk = "gpio3_ick",
1214 .prcm = {
1215 .omap4 = {
1216 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1217 },
1218 },
1219 .opt_clks = gpio3_opt_clks,
1220 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1221 .dev_attr = &gpio_dev_attr,
1222 .slaves = omap44xx_gpio3_slaves,
1223 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
1224 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1225};
1226
1227/* gpio4 */
1228static struct omap_hwmod omap44xx_gpio4_hwmod;
1229static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1230 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1231};
1232
1233static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1234 {
1235 .pa_start = 0x48059000,
1236 .pa_end = 0x480591ff,
1237 .flags = ADDR_TYPE_RT
1238 },
1239};
1240
1241/* l4_per -> gpio4 */
1242static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1243 .master = &omap44xx_l4_per_hwmod,
1244 .slave = &omap44xx_gpio4_hwmod,
1245 .addr = omap44xx_gpio4_addrs,
1246 .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
1247 .user = OCP_USER_MPU | OCP_USER_SDMA,
1248};
1249
1250/* gpio4 slave ports */
1251static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1252 &omap44xx_l4_per__gpio4,
1253};
1254
1255static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1256 { .role = "dbclk", .clk = "sys_32k_ck" },
1257};
1258
1259static struct omap_hwmod omap44xx_gpio4_hwmod = {
1260 .name = "gpio4",
1261 .class = &omap44xx_gpio_hwmod_class,
1262 .mpu_irqs = omap44xx_gpio4_irqs,
1263 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
1264 .main_clk = "gpio4_ick",
1265 .prcm = {
1266 .omap4 = {
1267 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1268 },
1269 },
1270 .opt_clks = gpio4_opt_clks,
1271 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1272 .dev_attr = &gpio_dev_attr,
1273 .slaves = omap44xx_gpio4_slaves,
1274 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
1275 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1276};
1277
1278/* gpio5 */
1279static struct omap_hwmod omap44xx_gpio5_hwmod;
1280static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1281 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1282};
1283
1284static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1285 {
1286 .pa_start = 0x4805b000,
1287 .pa_end = 0x4805b1ff,
1288 .flags = ADDR_TYPE_RT
1289 },
1290};
1291
1292/* l4_per -> gpio5 */
1293static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1294 .master = &omap44xx_l4_per_hwmod,
1295 .slave = &omap44xx_gpio5_hwmod,
1296 .addr = omap44xx_gpio5_addrs,
1297 .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
1298 .user = OCP_USER_MPU | OCP_USER_SDMA,
1299};
1300
1301/* gpio5 slave ports */
1302static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1303 &omap44xx_l4_per__gpio5,
1304};
1305
1306static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1307 { .role = "dbclk", .clk = "sys_32k_ck" },
1308};
1309
1310static struct omap_hwmod omap44xx_gpio5_hwmod = {
1311 .name = "gpio5",
1312 .class = &omap44xx_gpio_hwmod_class,
1313 .mpu_irqs = omap44xx_gpio5_irqs,
1314 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
1315 .main_clk = "gpio5_ick",
1316 .prcm = {
1317 .omap4 = {
1318 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1319 },
1320 },
1321 .opt_clks = gpio5_opt_clks,
1322 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1323 .dev_attr = &gpio_dev_attr,
1324 .slaves = omap44xx_gpio5_slaves,
1325 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
1326 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1327};
1328
1329/* gpio6 */
1330static struct omap_hwmod omap44xx_gpio6_hwmod;
1331static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1332 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1333};
1334
1335static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1336 {
1337 .pa_start = 0x4805d000,
1338 .pa_end = 0x4805d1ff,
1339 .flags = ADDR_TYPE_RT
1340 },
1341};
1342
1343/* l4_per -> gpio6 */
1344static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1345 .master = &omap44xx_l4_per_hwmod,
1346 .slave = &omap44xx_gpio6_hwmod,
1347 .addr = omap44xx_gpio6_addrs,
1348 .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
1349 .user = OCP_USER_MPU | OCP_USER_SDMA,
1350};
1351
1352/* gpio6 slave ports */
1353static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
1354 &omap44xx_l4_per__gpio6,
1355};
1356
1357static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1358 { .role = "dbclk", .clk = "sys_32k_ck" },
1359};
1360
1361static struct omap_hwmod omap44xx_gpio6_hwmod = {
1362 .name = "gpio6",
1363 .class = &omap44xx_gpio_hwmod_class,
1364 .mpu_irqs = omap44xx_gpio6_irqs,
1365 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
1366 .main_clk = "gpio6_ick",
1367 .prcm = {
1368 .omap4 = {
1369 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1370 },
1371 },
1372 .opt_clks = gpio6_opt_clks,
1373 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1374 .dev_attr = &gpio_dev_attr,
1375 .slaves = omap44xx_gpio6_slaves,
1376 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
1377 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1378};
1046static __initdata struct omap_hwmod *omap44xx_hwmods[] = { 1379static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
1047 /* dmm class */ 1380 /* dmm class */
1048 &omap44xx_dmm_hwmod, 1381 &omap44xx_dmm_hwmod,
@@ -1066,6 +1399,14 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
1066 /* mpu_bus class */ 1399 /* mpu_bus class */
1067 &omap44xx_mpu_private_hwmod, 1400 &omap44xx_mpu_private_hwmod,
1068 1401
1402 /* gpio class */
1403 &omap44xx_gpio1_hwmod,
1404 &omap44xx_gpio2_hwmod,
1405 &omap44xx_gpio3_hwmod,
1406 &omap44xx_gpio4_hwmod,
1407 &omap44xx_gpio5_hwmod,
1408 &omap44xx_gpio6_hwmod,
1409
1069 /* mpu class */ 1410 /* mpu class */
1070 &omap44xx_mpu_hwmod, 1411 &omap44xx_mpu_hwmod,
1071 /* wd_timer class */ 1412 /* wd_timer class */
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index e0e2fa725269..8d493b992e70 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -21,6 +21,8 @@
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/pm_runtime.h>
24 26
25#include <mach/hardware.h> 27#include <mach/hardware.h>
26#include <asm/irq.h> 28#include <asm/irq.h>
@@ -32,7 +34,6 @@
32/* 34/*
33 * OMAP1510 GPIO registers 35 * OMAP1510 GPIO registers
34 */ 36 */
35#define OMAP1510_GPIO_BASE 0xfffce000
36#define OMAP1510_GPIO_DATA_INPUT 0x00 37#define OMAP1510_GPIO_DATA_INPUT 0x00
37#define OMAP1510_GPIO_DATA_OUTPUT 0x04 38#define OMAP1510_GPIO_DATA_OUTPUT 0x04
38#define OMAP1510_GPIO_DIR_CONTROL 0x08 39#define OMAP1510_GPIO_DIR_CONTROL 0x08
@@ -46,10 +47,6 @@
46/* 47/*
47 * OMAP1610 specific GPIO registers 48 * OMAP1610 specific GPIO registers
48 */ 49 */
49#define OMAP1610_GPIO1_BASE 0xfffbe400
50#define OMAP1610_GPIO2_BASE 0xfffbec00
51#define OMAP1610_GPIO3_BASE 0xfffbb400
52#define OMAP1610_GPIO4_BASE 0xfffbbc00
53#define OMAP1610_GPIO_REVISION 0x0000 50#define OMAP1610_GPIO_REVISION 0x0000
54#define OMAP1610_GPIO_SYSCONFIG 0x0010 51#define OMAP1610_GPIO_SYSCONFIG 0x0010
55#define OMAP1610_GPIO_SYSSTATUS 0x0014 52#define OMAP1610_GPIO_SYSSTATUS 0x0014
@@ -71,12 +68,6 @@
71/* 68/*
72 * OMAP7XX specific GPIO registers 69 * OMAP7XX specific GPIO registers
73 */ 70 */
74#define OMAP7XX_GPIO1_BASE 0xfffbc000
75#define OMAP7XX_GPIO2_BASE 0xfffbc800
76#define OMAP7XX_GPIO3_BASE 0xfffbd000
77#define OMAP7XX_GPIO4_BASE 0xfffbd800
78#define OMAP7XX_GPIO5_BASE 0xfffbe000
79#define OMAP7XX_GPIO6_BASE 0xfffbe800
80#define OMAP7XX_GPIO_DATA_INPUT 0x00 71#define OMAP7XX_GPIO_DATA_INPUT 0x00
81#define OMAP7XX_GPIO_DATA_OUTPUT 0x04 72#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
82#define OMAP7XX_GPIO_DIR_CONTROL 0x08 73#define OMAP7XX_GPIO_DIR_CONTROL 0x08
@@ -84,25 +75,10 @@
84#define OMAP7XX_GPIO_INT_MASK 0x10 75#define OMAP7XX_GPIO_INT_MASK 0x10
85#define OMAP7XX_GPIO_INT_STATUS 0x14 76#define OMAP7XX_GPIO_INT_STATUS 0x14
86 77
87#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
88
89/* 78/*
90 * omap24xx specific GPIO registers 79 * omap2+ specific GPIO registers
91 */ 80 */
92#define OMAP242X_GPIO1_BASE 0x48018000
93#define OMAP242X_GPIO2_BASE 0x4801a000
94#define OMAP242X_GPIO3_BASE 0x4801c000
95#define OMAP242X_GPIO4_BASE 0x4801e000
96
97#define OMAP243X_GPIO1_BASE 0x4900C000
98#define OMAP243X_GPIO2_BASE 0x4900E000
99#define OMAP243X_GPIO3_BASE 0x49010000
100#define OMAP243X_GPIO4_BASE 0x49012000
101#define OMAP243X_GPIO5_BASE 0x480B6000
102
103#define OMAP24XX_GPIO_REVISION 0x0000 81#define OMAP24XX_GPIO_REVISION 0x0000
104#define OMAP24XX_GPIO_SYSCONFIG 0x0010
105#define OMAP24XX_GPIO_SYSSTATUS 0x0014
106#define OMAP24XX_GPIO_IRQSTATUS1 0x0018 82#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
107#define OMAP24XX_GPIO_IRQSTATUS2 0x0028 83#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
108#define OMAP24XX_GPIO_IRQENABLE2 0x002c 84#define OMAP24XX_GPIO_IRQENABLE2 0x002c
@@ -126,7 +102,6 @@
126#define OMAP24XX_GPIO_SETDATAOUT 0x0094 102#define OMAP24XX_GPIO_SETDATAOUT 0x0094
127 103
128#define OMAP4_GPIO_REVISION 0x0000 104#define OMAP4_GPIO_REVISION 0x0000
129#define OMAP4_GPIO_SYSCONFIG 0x0010
130#define OMAP4_GPIO_EOI 0x0020 105#define OMAP4_GPIO_EOI 0x0020
131#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024 106#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
132#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028 107#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
@@ -138,7 +113,6 @@
138#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 113#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
139#define OMAP4_GPIO_IRQWAKEN0 0x0044 114#define OMAP4_GPIO_IRQWAKEN0 0x0044
140#define OMAP4_GPIO_IRQWAKEN1 0x0048 115#define OMAP4_GPIO_IRQWAKEN1 0x0048
141#define OMAP4_GPIO_SYSSTATUS 0x0114
142#define OMAP4_GPIO_IRQENABLE1 0x011c 116#define OMAP4_GPIO_IRQENABLE1 0x011c
143#define OMAP4_GPIO_WAKE_EN 0x0120 117#define OMAP4_GPIO_WAKE_EN 0x0120
144#define OMAP4_GPIO_IRQSTATUS2 0x0128 118#define OMAP4_GPIO_IRQSTATUS2 0x0128
@@ -159,26 +133,6 @@
159#define OMAP4_GPIO_SETWKUENA 0x0184 133#define OMAP4_GPIO_SETWKUENA 0x0184
160#define OMAP4_GPIO_CLEARDATAOUT 0x0190 134#define OMAP4_GPIO_CLEARDATAOUT 0x0190
161#define OMAP4_GPIO_SETDATAOUT 0x0194 135#define OMAP4_GPIO_SETDATAOUT 0x0194
162/*
163 * omap34xx specific GPIO registers
164 */
165
166#define OMAP34XX_GPIO1_BASE 0x48310000
167#define OMAP34XX_GPIO2_BASE 0x49050000
168#define OMAP34XX_GPIO3_BASE 0x49052000
169#define OMAP34XX_GPIO4_BASE 0x49054000
170#define OMAP34XX_GPIO5_BASE 0x49056000
171#define OMAP34XX_GPIO6_BASE 0x49058000
172
173/*
174 * OMAP44XX specific GPIO registers
175 */
176#define OMAP44XX_GPIO1_BASE 0x4a310000
177#define OMAP44XX_GPIO2_BASE 0x48055000
178#define OMAP44XX_GPIO3_BASE 0x48057000
179#define OMAP44XX_GPIO4_BASE 0x48059000
180#define OMAP44XX_GPIO5_BASE 0x4805B000
181#define OMAP44XX_GPIO6_BASE 0x4805D000
182 136
183struct gpio_bank { 137struct gpio_bank {
184 unsigned long pbase; 138 unsigned long pbase;
@@ -190,14 +144,12 @@ struct gpio_bank {
190 u32 suspend_wakeup; 144 u32 suspend_wakeup;
191 u32 saved_wakeup; 145 u32 saved_wakeup;
192#endif 146#endif
193#ifdef CONFIG_ARCH_OMAP2PLUS
194 u32 non_wakeup_gpios; 147 u32 non_wakeup_gpios;
195 u32 enabled_non_wakeup_gpios; 148 u32 enabled_non_wakeup_gpios;
196 149
197 u32 saved_datain; 150 u32 saved_datain;
198 u32 saved_fallingdetect; 151 u32 saved_fallingdetect;
199 u32 saved_risingdetect; 152 u32 saved_risingdetect;
200#endif
201 u32 level_mask; 153 u32 level_mask;
202 u32 toggle_mask; 154 u32 toggle_mask;
203 spinlock_t lock; 155 spinlock_t lock;
@@ -205,104 +157,13 @@ struct gpio_bank {
205 struct clk *dbck; 157 struct clk *dbck;
206 u32 mod_usage; 158 u32 mod_usage;
207 u32 dbck_enable_mask; 159 u32 dbck_enable_mask;
160 struct device *dev;
161 bool dbck_flag;
162 int stride;
208}; 163};
209 164
210#define METHOD_MPUIO 0
211#define METHOD_GPIO_1510 1
212#define METHOD_GPIO_1610 2
213#define METHOD_GPIO_7XX 3
214#define METHOD_GPIO_24XX 5
215#define METHOD_GPIO_44XX 6
216
217#ifdef CONFIG_ARCH_OMAP16XX
218static struct gpio_bank gpio_bank_1610[5] = {
219 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
220 METHOD_MPUIO },
221 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
222 METHOD_GPIO_1610 },
223 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
224 METHOD_GPIO_1610 },
225 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
226 METHOD_GPIO_1610 },
227 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
228 METHOD_GPIO_1610 },
229};
230#endif
231
232#ifdef CONFIG_ARCH_OMAP15XX
233static struct gpio_bank gpio_bank_1510[2] = {
234 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
235 METHOD_MPUIO },
236 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
237 METHOD_GPIO_1510 }
238};
239#endif
240
241#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
242static struct gpio_bank gpio_bank_7xx[7] = {
243 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
244 METHOD_MPUIO },
245 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
246 METHOD_GPIO_7XX },
247 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
248 METHOD_GPIO_7XX },
249 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
250 METHOD_GPIO_7XX },
251 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
252 METHOD_GPIO_7XX },
253 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
254 METHOD_GPIO_7XX },
255 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
256 METHOD_GPIO_7XX },
257};
258#endif
259
260#ifdef CONFIG_ARCH_OMAP2
261
262static struct gpio_bank gpio_bank_242x[4] = {
263 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
264 METHOD_GPIO_24XX },
265 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
266 METHOD_GPIO_24XX },
267 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
268 METHOD_GPIO_24XX },
269 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
270 METHOD_GPIO_24XX },
271};
272
273static struct gpio_bank gpio_bank_243x[5] = {
274 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
275 METHOD_GPIO_24XX },
276 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
277 METHOD_GPIO_24XX },
278 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
279 METHOD_GPIO_24XX },
280 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
281 METHOD_GPIO_24XX },
282 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
283 METHOD_GPIO_24XX },
284};
285
286#endif
287
288#ifdef CONFIG_ARCH_OMAP3 165#ifdef CONFIG_ARCH_OMAP3
289static struct gpio_bank gpio_bank_34xx[6] = {
290 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
291 METHOD_GPIO_24XX },
292 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
293 METHOD_GPIO_24XX },
294 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
295 METHOD_GPIO_24XX },
296 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
297 METHOD_GPIO_24XX },
298 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
299 METHOD_GPIO_24XX },
300 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
301 METHOD_GPIO_24XX },
302};
303
304struct omap3_gpio_regs { 166struct omap3_gpio_regs {
305 u32 sysconfig;
306 u32 irqenable1; 167 u32 irqenable1;
307 u32 irqenable2; 168 u32 irqenable2;
308 u32 wake_en; 169 u32 wake_en;
@@ -318,26 +179,16 @@ struct omap3_gpio_regs {
318static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; 179static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
319#endif 180#endif
320 181
321#ifdef CONFIG_ARCH_OMAP4 182/*
322static struct gpio_bank gpio_bank_44xx[6] = { 183 * TODO: Cleanup gpio_bank usage as it is having information
323 { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE, 184 * related to all instances of the device
324 METHOD_GPIO_44XX }, 185 */
325 { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32, 186static struct gpio_bank *gpio_bank;
326 METHOD_GPIO_44XX },
327 { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
328 METHOD_GPIO_44XX },
329 { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
330 METHOD_GPIO_44XX },
331 { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
332 METHOD_GPIO_44XX },
333 { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
334 METHOD_GPIO_44XX },
335};
336 187
337#endif 188static int bank_width;
338 189
339static struct gpio_bank *gpio_bank; 190/* TODO: Analyze removing gpio_bank_count usage from driver code */
340static int gpio_bank_count; 191int gpio_bank_count;
341 192
342static inline struct gpio_bank *get_gpio_bank(int gpio) 193static inline struct gpio_bank *get_gpio_bank(int gpio)
343{ 194{
@@ -417,7 +268,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
417 switch (bank->method) { 268 switch (bank->method) {
418#ifdef CONFIG_ARCH_OMAP1 269#ifdef CONFIG_ARCH_OMAP1
419 case METHOD_MPUIO: 270 case METHOD_MPUIO:
420 reg += OMAP_MPUIO_IO_CNTL; 271 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
421 break; 272 break;
422#endif 273#endif
423#ifdef CONFIG_ARCH_OMAP15XX 274#ifdef CONFIG_ARCH_OMAP15XX
@@ -465,7 +316,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
465 switch (bank->method) { 316 switch (bank->method) {
466#ifdef CONFIG_ARCH_OMAP1 317#ifdef CONFIG_ARCH_OMAP1
467 case METHOD_MPUIO: 318 case METHOD_MPUIO:
468 reg += OMAP_MPUIO_OUTPUT; 319 reg += OMAP_MPUIO_OUTPUT / bank->stride;
469 l = __raw_readl(reg); 320 l = __raw_readl(reg);
470 if (enable) 321 if (enable)
471 l |= 1 << gpio; 322 l |= 1 << gpio;
@@ -537,7 +388,7 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
537 switch (bank->method) { 388 switch (bank->method) {
538#ifdef CONFIG_ARCH_OMAP1 389#ifdef CONFIG_ARCH_OMAP1
539 case METHOD_MPUIO: 390 case METHOD_MPUIO:
540 reg += OMAP_MPUIO_INPUT_LATCH; 391 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
541 break; 392 break;
542#endif 393#endif
543#ifdef CONFIG_ARCH_OMAP15XX 394#ifdef CONFIG_ARCH_OMAP15XX
@@ -583,7 +434,7 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
583 switch (bank->method) { 434 switch (bank->method) {
584#ifdef CONFIG_ARCH_OMAP1 435#ifdef CONFIG_ARCH_OMAP1
585 case METHOD_MPUIO: 436 case METHOD_MPUIO:
586 reg += OMAP_MPUIO_OUTPUT; 437 reg += OMAP_MPUIO_OUTPUT / bank->stride;
587 break; 438 break;
588#endif 439#endif
589#ifdef CONFIG_ARCH_OMAP15XX 440#ifdef CONFIG_ARCH_OMAP15XX
@@ -642,6 +493,9 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
642 u32 val; 493 u32 val;
643 u32 l; 494 u32 l;
644 495
496 if (!bank->dbck_flag)
497 return;
498
645 if (debounce < 32) 499 if (debounce < 32)
646 debounce = 0x01; 500 debounce = 0x01;
647 else if (debounce > 7936) 501 else if (debounce > 7936)
@@ -651,7 +505,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
651 505
652 l = 1 << get_gpio_index(gpio); 506 l = 1 << get_gpio_index(gpio);
653 507
654 if (cpu_is_omap44xx()) 508 if (bank->method == METHOD_GPIO_44XX)
655 reg += OMAP4_GPIO_DEBOUNCINGTIME; 509 reg += OMAP4_GPIO_DEBOUNCINGTIME;
656 else 510 else
657 reg += OMAP24XX_GPIO_DEBOUNCE_VAL; 511 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
@@ -659,7 +513,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
659 __raw_writel(debounce, reg); 513 __raw_writel(debounce, reg);
660 514
661 reg = bank->base; 515 reg = bank->base;
662 if (cpu_is_omap44xx()) 516 if (bank->method == METHOD_GPIO_44XX)
663 reg += OMAP4_GPIO_DEBOUNCENABLE; 517 reg += OMAP4_GPIO_DEBOUNCENABLE;
664 else 518 else
665 reg += OMAP24XX_GPIO_DEBOUNCE_EN; 519 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
@@ -668,12 +522,10 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
668 522
669 if (debounce) { 523 if (debounce) {
670 val |= l; 524 val |= l;
671 if (cpu_is_omap34xx() || cpu_is_omap44xx()) 525 clk_enable(bank->dbck);
672 clk_enable(bank->dbck);
673 } else { 526 } else {
674 val &= ~l; 527 val &= ~l;
675 if (cpu_is_omap34xx() || cpu_is_omap44xx()) 528 clk_disable(bank->dbck);
676 clk_disable(bank->dbck);
677 } 529 }
678 bank->dbck_enable_mask = val; 530 bank->dbck_enable_mask = val;
679 531
@@ -769,7 +621,7 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
769 621
770 switch (bank->method) { 622 switch (bank->method) {
771 case METHOD_MPUIO: 623 case METHOD_MPUIO:
772 reg += OMAP_MPUIO_GPIO_INT_EDGE; 624 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
773 break; 625 break;
774#ifdef CONFIG_ARCH_OMAP15XX 626#ifdef CONFIG_ARCH_OMAP15XX
775 case METHOD_GPIO_1510: 627 case METHOD_GPIO_1510:
@@ -803,7 +655,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
803 switch (bank->method) { 655 switch (bank->method) {
804#ifdef CONFIG_ARCH_OMAP1 656#ifdef CONFIG_ARCH_OMAP1
805 case METHOD_MPUIO: 657 case METHOD_MPUIO:
806 reg += OMAP_MPUIO_GPIO_INT_EDGE; 658 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
807 l = __raw_readl(reg); 659 l = __raw_readl(reg);
808 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 660 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
809 bank->toggle_mask |= 1 << gpio; 661 bank->toggle_mask |= 1 << gpio;
@@ -989,7 +841,7 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
989 switch (bank->method) { 841 switch (bank->method) {
990#ifdef CONFIG_ARCH_OMAP1 842#ifdef CONFIG_ARCH_OMAP1
991 case METHOD_MPUIO: 843 case METHOD_MPUIO:
992 reg += OMAP_MPUIO_GPIO_MASKIT; 844 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
993 mask = 0xffff; 845 mask = 0xffff;
994 inv = 1; 846 inv = 1;
995 break; 847 break;
@@ -1046,7 +898,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
1046 switch (bank->method) { 898 switch (bank->method) {
1047#ifdef CONFIG_ARCH_OMAP1 899#ifdef CONFIG_ARCH_OMAP1
1048 case METHOD_MPUIO: 900 case METHOD_MPUIO:
1049 reg += OMAP_MPUIO_GPIO_MASKIT; 901 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1050 l = __raw_readl(reg); 902 l = __raw_readl(reg);
1051 if (enable) 903 if (enable)
1052 l &= ~(gpio_mask); 904 l &= ~(gpio_mask);
@@ -1296,7 +1148,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1296 bank = get_irq_data(irq); 1148 bank = get_irq_data(irq);
1297#ifdef CONFIG_ARCH_OMAP1 1149#ifdef CONFIG_ARCH_OMAP1
1298 if (bank->method == METHOD_MPUIO) 1150 if (bank->method == METHOD_MPUIO)
1299 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; 1151 isr_reg = bank->base +
1152 OMAP_MPUIO_GPIO_INT / bank->stride;
1300#endif 1153#endif
1301#ifdef CONFIG_ARCH_OMAP15XX 1154#ifdef CONFIG_ARCH_OMAP15XX
1302 if (bank->method == METHOD_GPIO_1510) 1155 if (bank->method == METHOD_GPIO_1510)
@@ -1494,7 +1347,8 @@ static int omap_mpuio_suspend_noirq(struct device *dev)
1494{ 1347{
1495 struct platform_device *pdev = to_platform_device(dev); 1348 struct platform_device *pdev = to_platform_device(dev);
1496 struct gpio_bank *bank = platform_get_drvdata(pdev); 1349 struct gpio_bank *bank = platform_get_drvdata(pdev);
1497 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; 1350 void __iomem *mask_reg = bank->base +
1351 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1498 unsigned long flags; 1352 unsigned long flags;
1499 1353
1500 spin_lock_irqsave(&bank->lock, flags); 1354 spin_lock_irqsave(&bank->lock, flags);
@@ -1509,7 +1363,8 @@ static int omap_mpuio_resume_noirq(struct device *dev)
1509{ 1363{
1510 struct platform_device *pdev = to_platform_device(dev); 1364 struct platform_device *pdev = to_platform_device(dev);
1511 struct gpio_bank *bank = platform_get_drvdata(pdev); 1365 struct gpio_bank *bank = platform_get_drvdata(pdev);
1512 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; 1366 void __iomem *mask_reg = bank->base +
1367 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1513 unsigned long flags; 1368 unsigned long flags;
1514 1369
1515 spin_lock_irqsave(&bank->lock, flags); 1370 spin_lock_irqsave(&bank->lock, flags);
@@ -1545,7 +1400,8 @@ static struct platform_device omap_mpuio_device = {
1545 1400
1546static inline void mpuio_init(void) 1401static inline void mpuio_init(void)
1547{ 1402{
1548 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); 1403 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1404 platform_set_drvdata(&omap_mpuio_device, bank);
1549 1405
1550 if (platform_driver_register(&omap_mpuio_driver) == 0) 1406 if (platform_driver_register(&omap_mpuio_driver) == 0)
1551 (void) platform_device_register(&omap_mpuio_device); 1407 (void) platform_device_register(&omap_mpuio_device);
@@ -1588,7 +1444,7 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
1588 1444
1589 switch (bank->method) { 1445 switch (bank->method) {
1590 case METHOD_MPUIO: 1446 case METHOD_MPUIO:
1591 reg += OMAP_MPUIO_IO_CNTL; 1447 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1592 break; 1448 break;
1593 case METHOD_GPIO_1510: 1449 case METHOD_GPIO_1510:
1594 reg += OMAP1510_GPIO_DIR_CONTROL; 1450 reg += OMAP1510_GPIO_DIR_CONTROL;
@@ -1650,6 +1506,13 @@ static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1650 unsigned long flags; 1506 unsigned long flags;
1651 1507
1652 bank = container_of(chip, struct gpio_bank, chip); 1508 bank = container_of(chip, struct gpio_bank, chip);
1509
1510 if (!bank->dbck) {
1511 bank->dbck = clk_get(bank->dev, "dbclk");
1512 if (IS_ERR(bank->dbck))
1513 dev_err(bank->dev, "Could not get gpio dbck\n");
1514 }
1515
1653 spin_lock_irqsave(&bank->lock, flags); 1516 spin_lock_irqsave(&bank->lock, flags);
1654 _set_gpio_debounce(bank, offset, debounce); 1517 _set_gpio_debounce(bank, offset, debounce);
1655 spin_unlock_irqrestore(&bank->lock, flags); 1518 spin_unlock_irqrestore(&bank->lock, flags);
@@ -1678,34 +1541,16 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1678 1541
1679/*---------------------------------------------------------------------*/ 1542/*---------------------------------------------------------------------*/
1680 1543
1681static int initialized; 1544static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1682#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
1683static struct clk * gpio_ick;
1684#endif
1685
1686#if defined(CONFIG_ARCH_OMAP2)
1687static struct clk * gpio_fck;
1688#endif
1689
1690#if defined(CONFIG_ARCH_OMAP2430)
1691static struct clk * gpio5_ick;
1692static struct clk * gpio5_fck;
1693#endif
1694
1695#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1696static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1697#endif
1698
1699static void __init omap_gpio_show_rev(void)
1700{ 1545{
1701 u32 rev; 1546 u32 rev;
1702 1547
1703 if (cpu_is_omap16xx()) 1548 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1704 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); 1549 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1705 else if (cpu_is_omap24xx() || cpu_is_omap34xx()) 1550 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1706 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1551 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1707 else if (cpu_is_omap44xx()) 1552 else if (cpu_is_omap44xx())
1708 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION); 1553 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1709 else 1554 else
1710 return; 1555 return;
1711 1556
@@ -1718,250 +1563,190 @@ static void __init omap_gpio_show_rev(void)
1718 */ 1563 */
1719static struct lock_class_key gpio_lock_class; 1564static struct lock_class_key gpio_lock_class;
1720 1565
1721static int __init _omap_gpio_init(void) 1566static inline int init_gpio_info(struct platform_device *pdev)
1722{ 1567{
1723 int i; 1568 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1724 int gpio = 0; 1569 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1725 struct gpio_bank *bank; 1570 GFP_KERNEL);
1726 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ 1571 if (!gpio_bank) {
1727 char clk_name[11]; 1572 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1728 1573 return -ENOMEM;
1729 initialized = 1;
1730
1731#if defined(CONFIG_ARCH_OMAP1)
1732 if (cpu_is_omap15xx()) {
1733 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1734 if (IS_ERR(gpio_ick))
1735 printk("Could not get arm_gpio_ck\n");
1736 else
1737 clk_enable(gpio_ick);
1738 } 1574 }
1739#endif 1575 return 0;
1740#if defined(CONFIG_ARCH_OMAP2) 1576}
1741 if (cpu_class_is_omap2()) {
1742 gpio_ick = clk_get(NULL, "gpios_ick");
1743 if (IS_ERR(gpio_ick))
1744 printk("Could not get gpios_ick\n");
1745 else
1746 clk_enable(gpio_ick);
1747 gpio_fck = clk_get(NULL, "gpios_fck");
1748 if (IS_ERR(gpio_fck))
1749 printk("Could not get gpios_fck\n");
1750 else
1751 clk_enable(gpio_fck);
1752 1577
1753 /* 1578/* TODO: Cleanup cpu_is_* checks */
1754 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK 1579static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1755 */ 1580{
1756#if defined(CONFIG_ARCH_OMAP2430) 1581 if (cpu_class_is_omap2()) {
1757 if (cpu_is_omap2430()) { 1582 if (cpu_is_omap44xx()) {
1758 gpio5_ick = clk_get(NULL, "gpio5_ick"); 1583 __raw_writel(0xffffffff, bank->base +
1759 if (IS_ERR(gpio5_ick)) 1584 OMAP4_GPIO_IRQSTATUSCLR0);
1760 printk("Could not get gpio5_ick\n"); 1585 __raw_writel(0x00000000, bank->base +
1761 else 1586 OMAP4_GPIO_DEBOUNCENABLE);
1762 clk_enable(gpio5_ick); 1587 /* Initialize interface clk ungated, module enabled */
1763 gpio5_fck = clk_get(NULL, "gpio5_fck"); 1588 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1764 if (IS_ERR(gpio5_fck)) 1589 } else if (cpu_is_omap34xx()) {
1765 printk("Could not get gpio5_fck\n"); 1590 __raw_writel(0x00000000, bank->base +
1766 else 1591 OMAP24XX_GPIO_IRQENABLE1);
1767 clk_enable(gpio5_fck); 1592 __raw_writel(0xffffffff, bank->base +
1593 OMAP24XX_GPIO_IRQSTATUS1);
1594 __raw_writel(0x00000000, bank->base +
1595 OMAP24XX_GPIO_DEBOUNCE_EN);
1596
1597 /* Initialize interface clk ungated, module enabled */
1598 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1599 } else if (cpu_is_omap24xx()) {
1600 static const u32 non_wakeup_gpios[] = {
1601 0xe203ffc0, 0x08700040
1602 };
1603 if (id < ARRAY_SIZE(non_wakeup_gpios))
1604 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1768 } 1605 }
1769#endif 1606 } else if (cpu_class_is_omap1()) {
1770 } 1607 if (bank_is_mpuio(bank))
1771#endif 1608 __raw_writew(0xffff, bank->base +
1609 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1610 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1611 __raw_writew(0xffff, bank->base
1612 + OMAP1510_GPIO_INT_MASK);
1613 __raw_writew(0x0000, bank->base
1614 + OMAP1510_GPIO_INT_STATUS);
1615 }
1616 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1617 __raw_writew(0x0000, bank->base
1618 + OMAP1610_GPIO_IRQENABLE1);
1619 __raw_writew(0xffff, bank->base
1620 + OMAP1610_GPIO_IRQSTATUS1);
1621 __raw_writew(0x0014, bank->base
1622 + OMAP1610_GPIO_SYSCONFIG);
1772 1623
1773#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 1624 /*
1774 if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 1625 * Enable system clock for GPIO module.
1775 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { 1626 * The CAM_CLK_CTRL *is* really the right place.
1776 sprintf(clk_name, "gpio%d_ick", i + 1); 1627 */
1777 gpio_iclks[i] = clk_get(NULL, clk_name); 1628 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1778 if (IS_ERR(gpio_iclks[i])) 1629 ULPD_CAM_CLK_CTRL);
1779 printk(KERN_ERR "Could not get %s\n", clk_name); 1630 }
1780 else 1631 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1781 clk_enable(gpio_iclks[i]); 1632 __raw_writel(0xffffffff, bank->base
1633 + OMAP7XX_GPIO_INT_MASK);
1634 __raw_writel(0x00000000, bank->base
1635 + OMAP7XX_GPIO_INT_STATUS);
1782 } 1636 }
1783 } 1637 }
1784#endif 1638}
1785 1639
1640static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1641{
1642 int j;
1643 static int gpio;
1786 1644
1787#ifdef CONFIG_ARCH_OMAP15XX 1645 bank->mod_usage = 0;
1788 if (cpu_is_omap15xx()) { 1646 /*
1789 gpio_bank_count = 2; 1647 * REVISIT eventually switch from OMAP-specific gpio structs
1790 gpio_bank = gpio_bank_1510; 1648 * over to the generic ones
1791 bank_size = SZ_2K; 1649 */
1792 } 1650 bank->chip.request = omap_gpio_request;
1793#endif 1651 bank->chip.free = omap_gpio_free;
1794#if defined(CONFIG_ARCH_OMAP16XX) 1652 bank->chip.direction_input = gpio_input;
1795 if (cpu_is_omap16xx()) { 1653 bank->chip.get = gpio_get;
1796 gpio_bank_count = 5; 1654 bank->chip.direction_output = gpio_output;
1797 gpio_bank = gpio_bank_1610; 1655 bank->chip.set_debounce = gpio_debounce;
1798 bank_size = SZ_2K; 1656 bank->chip.set = gpio_set;
1799 } 1657 bank->chip.to_irq = gpio_2irq;
1800#endif 1658 if (bank_is_mpuio(bank)) {
1801#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 1659 bank->chip.label = "mpuio";
1802 if (cpu_is_omap7xx()) { 1660#ifdef CONFIG_ARCH_OMAP16XX
1803 gpio_bank_count = 7; 1661 bank->chip.dev = &omap_mpuio_device.dev;
1804 gpio_bank = gpio_bank_7xx;
1805 bank_size = SZ_2K;
1806 }
1807#endif
1808#ifdef CONFIG_ARCH_OMAP2
1809 if (cpu_is_omap242x()) {
1810 gpio_bank_count = 4;
1811 gpio_bank = gpio_bank_242x;
1812 }
1813 if (cpu_is_omap243x()) {
1814 gpio_bank_count = 5;
1815 gpio_bank = gpio_bank_243x;
1816 }
1817#endif 1662#endif
1818#ifdef CONFIG_ARCH_OMAP3 1663 bank->chip.base = OMAP_MPUIO(0);
1819 if (cpu_is_omap34xx()) { 1664 } else {
1820 gpio_bank_count = OMAP34XX_NR_GPIOS; 1665 bank->chip.label = "gpio";
1821 gpio_bank = gpio_bank_34xx; 1666 bank->chip.base = gpio;
1667 gpio += bank_width;
1822 } 1668 }
1823#endif 1669 bank->chip.ngpio = bank_width;
1824#ifdef CONFIG_ARCH_OMAP4 1670
1825 if (cpu_is_omap44xx()) { 1671 gpiochip_add(&bank->chip);
1826 gpio_bank_count = OMAP34XX_NR_GPIOS; 1672
1827 gpio_bank = gpio_bank_44xx; 1673 for (j = bank->virtual_irq_start;
1674 j < bank->virtual_irq_start + bank_width; j++) {
1675 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1676 set_irq_chip_data(j, bank);
1677 if (bank_is_mpuio(bank))
1678 set_irq_chip(j, &mpuio_irq_chip);
1679 else
1680 set_irq_chip(j, &gpio_irq_chip);
1681 set_irq_handler(j, handle_simple_irq);
1682 set_irq_flags(j, IRQF_VALID);
1828 } 1683 }
1829#endif 1684 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1830 for (i = 0; i < gpio_bank_count; i++) { 1685 set_irq_data(bank->irq, bank);
1831 int j, gpio_count = 16; 1686}
1832 1687
1833 bank = &gpio_bank[i]; 1688static int __devinit omap_gpio_probe(struct platform_device *pdev)
1834 spin_lock_init(&bank->lock); 1689{
1690 static int gpio_init_done;
1691 struct omap_gpio_platform_data *pdata;
1692 struct resource *res;
1693 int id;
1694 struct gpio_bank *bank;
1835 1695
1836 /* Static mapping, never released */ 1696 if (!pdev->dev.platform_data)
1837 bank->base = ioremap(bank->pbase, bank_size); 1697 return -EINVAL;
1838 if (!bank->base) {
1839 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1840 continue;
1841 }
1842 1698
1843 if (bank_is_mpuio(bank)) 1699 pdata = pdev->dev.platform_data;
1844 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1845 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1846 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1847 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1848 }
1849 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1850 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1851 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1852 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1853 }
1854 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1855 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1856 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
1857 1700
1858 gpio_count = 32; /* 7xx has 32-bit GPIOs */ 1701 if (!gpio_init_done) {
1859 } 1702 int ret;
1860 1703
1861#ifdef CONFIG_ARCH_OMAP2PLUS 1704 ret = init_gpio_info(pdev);
1862 if ((bank->method == METHOD_GPIO_24XX) || 1705 if (ret)
1863 (bank->method == METHOD_GPIO_44XX)) { 1706 return ret;
1864 static const u32 non_wakeup_gpios[] = { 1707 }
1865 0xe203ffc0, 0x08700040
1866 };
1867 1708
1868 if (cpu_is_omap44xx()) { 1709 id = pdev->id;
1869 __raw_writel(0xffffffff, bank->base + 1710 bank = &gpio_bank[id];
1870 OMAP4_GPIO_IRQSTATUSCLR0);
1871 __raw_writew(0x0015, bank->base +
1872 OMAP4_GPIO_SYSCONFIG);
1873 __raw_writel(0x00000000, bank->base +
1874 OMAP4_GPIO_DEBOUNCENABLE);
1875 /*
1876 * Initialize interface clock ungated,
1877 * module enabled
1878 */
1879 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1880 } else {
1881 __raw_writel(0x00000000, bank->base +
1882 OMAP24XX_GPIO_IRQENABLE1);
1883 __raw_writel(0xffffffff, bank->base +
1884 OMAP24XX_GPIO_IRQSTATUS1);
1885 __raw_writew(0x0015, bank->base +
1886 OMAP24XX_GPIO_SYSCONFIG);
1887 __raw_writel(0x00000000, bank->base +
1888 OMAP24XX_GPIO_DEBOUNCE_EN);
1889
1890 /*
1891 * Initialize interface clock ungated,
1892 * module enabled
1893 */
1894 __raw_writel(0, bank->base +
1895 OMAP24XX_GPIO_CTRL);
1896 }
1897 if (cpu_is_omap24xx() &&
1898 i < ARRAY_SIZE(non_wakeup_gpios))
1899 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1900 gpio_count = 32;
1901 }
1902#endif
1903 1711
1904 bank->mod_usage = 0; 1712 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1905 /* REVISIT eventually switch from OMAP-specific gpio structs 1713 if (unlikely(!res)) {
1906 * over to the generic ones 1714 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1907 */ 1715 return -ENODEV;
1908 bank->chip.request = omap_gpio_request; 1716 }
1909 bank->chip.free = omap_gpio_free;
1910 bank->chip.direction_input = gpio_input;
1911 bank->chip.get = gpio_get;
1912 bank->chip.direction_output = gpio_output;
1913 bank->chip.set_debounce = gpio_debounce;
1914 bank->chip.set = gpio_set;
1915 bank->chip.to_irq = gpio_2irq;
1916 if (bank_is_mpuio(bank)) {
1917 bank->chip.label = "mpuio";
1918#ifdef CONFIG_ARCH_OMAP16XX
1919 bank->chip.dev = &omap_mpuio_device.dev;
1920#endif
1921 bank->chip.base = OMAP_MPUIO(0);
1922 } else {
1923 bank->chip.label = "gpio";
1924 bank->chip.base = gpio;
1925 gpio += gpio_count;
1926 }
1927 bank->chip.ngpio = gpio_count;
1928 1717
1929 gpiochip_add(&bank->chip); 1718 bank->irq = res->start;
1719 bank->virtual_irq_start = pdata->virtual_irq_start;
1720 bank->method = pdata->bank_type;
1721 bank->dev = &pdev->dev;
1722 bank->dbck_flag = pdata->dbck_flag;
1723 bank->stride = pdata->bank_stride;
1724 bank_width = pdata->bank_width;
1930 1725
1931 for (j = bank->virtual_irq_start; 1726 spin_lock_init(&bank->lock);
1932 j < bank->virtual_irq_start + gpio_count; j++) { 1727
1933 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); 1728 /* Static mapping, never released */
1934 set_irq_chip_data(j, bank); 1729 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1935 if (bank_is_mpuio(bank)) 1730 if (unlikely(!res)) {
1936 set_irq_chip(j, &mpuio_irq_chip); 1731 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1937 else 1732 return -ENODEV;
1938 set_irq_chip(j, &gpio_irq_chip); 1733 }
1939 set_irq_handler(j, handle_simple_irq); 1734
1940 set_irq_flags(j, IRQF_VALID); 1735 bank->base = ioremap(res->start, resource_size(res));
1941 } 1736 if (!bank->base) {
1942 set_irq_chained_handler(bank->irq, gpio_irq_handler); 1737 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1943 set_irq_data(bank->irq, bank); 1738 return -ENOMEM;
1944
1945 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1946 sprintf(clk_name, "gpio%d_dbck", i + 1);
1947 bank->dbck = clk_get(NULL, clk_name);
1948 if (IS_ERR(bank->dbck))
1949 printk(KERN_ERR "Could not get %s\n", clk_name);
1950 }
1951 } 1739 }
1952 1740
1953 /* Enable system clock for GPIO module. 1741 pm_runtime_enable(bank->dev);
1954 * The CAM_CLK_CTRL *is* really the right place. */ 1742 pm_runtime_get_sync(bank->dev);
1955 if (cpu_is_omap16xx())
1956 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1957 1743
1958 /* Enable autoidle for the OCP interface */ 1744 omap_gpio_mod_init(bank, id);
1959 if (cpu_is_omap24xx()) 1745 omap_gpio_chip_init(bank);
1960 omap_writel(1 << 0, 0x48019010); 1746 omap_gpio_show_rev(bank);
1961 if (cpu_is_omap34xx())
1962 omap_writel(1 << 0, 0x48306814);
1963 1747
1964 omap_gpio_show_rev(); 1748 if (!gpio_init_done)
1749 gpio_init_done = 1;
1965 1750
1966 return 0; 1751 return 0;
1967} 1752}
@@ -2256,8 +2041,6 @@ void omap_gpio_save_context(void)
2256 /* saving banks from 2-6 only since GPIO1 is in WKUP */ 2041 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2257 for (i = 1; i < gpio_bank_count; i++) { 2042 for (i = 1; i < gpio_bank_count; i++) {
2258 struct gpio_bank *bank = &gpio_bank[i]; 2043 struct gpio_bank *bank = &gpio_bank[i];
2259 gpio_context[i].sysconfig =
2260 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2261 gpio_context[i].irqenable1 = 2044 gpio_context[i].irqenable1 =
2262 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); 2045 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2263 gpio_context[i].irqenable2 = 2046 gpio_context[i].irqenable2 =
@@ -2288,8 +2071,6 @@ void omap_gpio_restore_context(void)
2288 2071
2289 for (i = 1; i < gpio_bank_count; i++) { 2072 for (i = 1; i < gpio_bank_count; i++) {
2290 struct gpio_bank *bank = &gpio_bank[i]; 2073 struct gpio_bank *bank = &gpio_bank[i];
2291 __raw_writel(gpio_context[i].sysconfig,
2292 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2293 __raw_writel(gpio_context[i].irqenable1, 2074 __raw_writel(gpio_context[i].irqenable1,
2294 bank->base + OMAP24XX_GPIO_IRQENABLE1); 2075 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2295 __raw_writel(gpio_context[i].irqenable2, 2076 __raw_writel(gpio_context[i].irqenable2,
@@ -2314,25 +2095,28 @@ void omap_gpio_restore_context(void)
2314} 2095}
2315#endif 2096#endif
2316 2097
2098static struct platform_driver omap_gpio_driver = {
2099 .probe = omap_gpio_probe,
2100 .driver = {
2101 .name = "omap_gpio",
2102 },
2103};
2104
2317/* 2105/*
2318 * This may get called early from board specific init 2106 * gpio driver register needs to be done before
2319 * for boards that have interrupts routed via FPGA. 2107 * machine_init functions access gpio APIs.
2108 * Hence omap_gpio_drv_reg() is a postcore_initcall.
2320 */ 2109 */
2321int __init omap_gpio_init(void) 2110static int __init omap_gpio_drv_reg(void)
2322{ 2111{
2323 if (!initialized) 2112 return platform_driver_register(&omap_gpio_driver);
2324 return _omap_gpio_init();
2325 else
2326 return 0;
2327} 2113}
2114postcore_initcall(omap_gpio_drv_reg);
2328 2115
2329static int __init omap_gpio_sysinit(void) 2116static int __init omap_gpio_sysinit(void)
2330{ 2117{
2331 int ret = 0; 2118 int ret = 0;
2332 2119
2333 if (!initialized)
2334 ret = _omap_gpio_init();
2335
2336 mpuio_init(); 2120 mpuio_init();
2337 2121
2338#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) 2122#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index de1c604962eb..41ff2f8943f0 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -27,26 +27,15 @@
27#define __ASM_ARCH_OMAP_GPIO_H 27#define __ASM_ARCH_OMAP_GPIO_H
28 28
29#include <linux/io.h> 29#include <linux/io.h>
30#include <linux/platform_device.h>
30#include <mach/irqs.h> 31#include <mach/irqs.h>
31 32
32#define OMAP1_MPUIO_BASE 0xfffb5000 33#define OMAP1_MPUIO_BASE 0xfffb5000
33 34
34#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)) 35/*
35 36 * These are the omap15xx/16xx offsets. The omap7xx offset are
36#define OMAP_MPUIO_INPUT_LATCH 0x00 37 * OMAP_MPUIO_ / 2 offsets below.
37#define OMAP_MPUIO_OUTPUT 0x02 38 */
38#define OMAP_MPUIO_IO_CNTL 0x04
39#define OMAP_MPUIO_KBR_LATCH 0x08
40#define OMAP_MPUIO_KBC 0x0a
41#define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c
42#define OMAP_MPUIO_GPIO_INT_EDGE 0x0e
43#define OMAP_MPUIO_KBD_INT 0x10
44#define OMAP_MPUIO_GPIO_INT 0x12
45#define OMAP_MPUIO_KBD_MASKIT 0x14
46#define OMAP_MPUIO_GPIO_MASKIT 0x16
47#define OMAP_MPUIO_GPIO_DEBOUNCING 0x18
48#define OMAP_MPUIO_LATCH 0x1a
49#else
50#define OMAP_MPUIO_INPUT_LATCH 0x00 39#define OMAP_MPUIO_INPUT_LATCH 0x00
51#define OMAP_MPUIO_OUTPUT 0x04 40#define OMAP_MPUIO_OUTPUT 0x04
52#define OMAP_MPUIO_IO_CNTL 0x08 41#define OMAP_MPUIO_IO_CNTL 0x08
@@ -60,7 +49,6 @@
60#define OMAP_MPUIO_GPIO_MASKIT 0x2c 49#define OMAP_MPUIO_GPIO_MASKIT 0x2c
61#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30 50#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
62#define OMAP_MPUIO_LATCH 0x34 51#define OMAP_MPUIO_LATCH 0x34
63#endif
64 52
65#define OMAP34XX_NR_GPIOS 6 53#define OMAP34XX_NR_GPIOS 6
66 54
@@ -71,7 +59,29 @@
71 IH_MPUIO_BASE + ((nr) & 0x0f) : \ 59 IH_MPUIO_BASE + ((nr) & 0x0f) : \
72 IH_GPIO_BASE + (nr)) 60 IH_GPIO_BASE + (nr))
73 61
74extern int omap_gpio_init(void); /* Call from board init only */ 62#define METHOD_MPUIO 0
63#define METHOD_GPIO_1510 1
64#define METHOD_GPIO_1610 2
65#define METHOD_GPIO_7XX 3
66#define METHOD_GPIO_24XX 5
67#define METHOD_GPIO_44XX 6
68
69struct omap_gpio_dev_attr {
70 int bank_width; /* GPIO bank width */
71 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
72};
73
74struct omap_gpio_platform_data {
75 u16 virtual_irq_start;
76 int bank_type;
77 int bank_width; /* GPIO bank width */
78 int bank_stride; /* Only needed for omap1 MPUIO */
79 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
80};
81
82/* TODO: Analyze removing gpio_bank_count usage from driver code */
83extern int gpio_bank_count;
84
75extern void omap2_gpio_prepare_for_idle(int power_state); 85extern void omap2_gpio_prepare_for_idle(int power_state);
76extern void omap2_gpio_resume_after_idle(void); 86extern void omap2_gpio_resume_after_idle(void);
77extern void omap_set_gpio_debounce(int gpio, int enable); 87extern void omap_set_gpio_debounce(int gpio, int enable);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 22:09:14 -0500