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-rw-r--r--arch/arm/kernel/process.c15
-rw-r--r--arch/arm/kernel/traps.c8
-rw-r--r--arch/arm/lib/bitops.h33
-rw-r--r--arch/arm/lib/changebit.S11
-rw-r--r--arch/arm/lib/clearbit.S13
-rw-r--r--arch/arm/lib/setbit.S11
-rw-r--r--arch/arm/lib/testchangebit.S15
-rw-r--r--arch/arm/lib/testclearbit.S15
-rw-r--r--arch/arm/lib/testsetbit.S15
-rw-r--r--arch/arm/mach-footbridge/dc21285-timer.c4
-rw-r--r--arch/arm/mach-sa1100/h3600.c2
11 files changed, 61 insertions, 81 deletions
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index dbd8ca89b385..26eacd3e5def 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -168,12 +168,11 @@ void machine_restart(char * __unused)
168 168
169EXPORT_SYMBOL(machine_restart); 169EXPORT_SYMBOL(machine_restart);
170 170
171void show_regs(struct pt_regs * regs) 171void __show_regs(struct pt_regs *regs)
172{ 172{
173 unsigned long flags; 173 unsigned long flags = condition_codes(regs);
174
175 flags = condition_codes(regs);
176 174
175 printk("CPU: %d\n", smp_processor_id());
177 print_symbol("PC is at %s\n", instruction_pointer(regs)); 176 print_symbol("PC is at %s\n", instruction_pointer(regs));
178 print_symbol("LR is at %s\n", regs->ARM_lr); 177 print_symbol("LR is at %s\n", regs->ARM_lr);
179 printk("pc : [<%08lx>] lr : [<%08lx>] %s\n" 178 printk("pc : [<%08lx>] lr : [<%08lx>] %s\n"
@@ -213,6 +212,14 @@ void show_regs(struct pt_regs * regs)
213 } 212 }
214} 213}
215 214
215void show_regs(struct pt_regs * regs)
216{
217 printk("\n");
218 printk("Pid: %d, comm: %20s\n", current->pid, current->comm);
219 __show_regs(regs);
220 __backtrace();
221}
222
216void show_fpregs(struct user_fp *regs) 223void show_fpregs(struct user_fp *regs)
217{ 224{
218 int i; 225 int i;
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 93dc4646cd7f..6e31718f6008 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -31,9 +31,6 @@
31 31
32#include "ptrace.h" 32#include "ptrace.h"
33 33
34extern void c_backtrace (unsigned long fp, int pmode);
35extern void show_pte(struct mm_struct *mm, unsigned long addr);
36
37const char *processor_modes[]= 34const char *processor_modes[]=
38{ "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" , 35{ "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
39 "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26", 36 "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
@@ -216,8 +213,7 @@ NORET_TYPE void die(const char *str, struct pt_regs *regs, int err)
216 213
217 printk("Internal error: %s: %x [#%d]\n", str, err, ++die_counter); 214 printk("Internal error: %s: %x [#%d]\n", str, err, ++die_counter);
218 print_modules(); 215 print_modules();
219 printk("CPU: %d\n", smp_processor_id()); 216 __show_regs(regs);
220 show_regs(regs);
221 printk("Process %s (pid: %d, stack limit = 0x%p)\n", 217 printk("Process %s (pid: %d, stack limit = 0x%p)\n",
222 tsk->comm, tsk->pid, tsk->thread_info + 1); 218 tsk->comm, tsk->pid, tsk->thread_info + 1);
223 219
@@ -482,7 +478,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
482 current->pid, current->comm, no); 478 current->pid, current->comm, no);
483 dump_instr(regs); 479 dump_instr(regs);
484 if (user_mode(regs)) { 480 if (user_mode(regs)) {
485 show_regs(regs); 481 __show_regs(regs);
486 c_backtrace(regs->ARM_fp, processor_mode(regs)); 482 c_backtrace(regs->ARM_fp, processor_mode(regs));
487 } 483 }
488 } 484 }
diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h
new file mode 100644
index 000000000000..4a83ab6cd565
--- /dev/null
+++ b/arch/arm/lib/bitops.h
@@ -0,0 +1,33 @@
1 .macro bitop, instr
2 and r2, r0, #7
3 mov r3, #1
4 mov r3, r3, lsl r2
5 save_and_disable_irqs ip, r2
6 ldrb r2, [r1, r0, lsr #3]
7 \instr r2, r2, r3
8 strb r2, [r1, r0, lsr #3]
9 restore_irqs ip
10 mov pc, lr
11 .endm
12
13/**
14 * testop - implement a test_and_xxx_bit operation.
15 * @instr: operational instruction
16 * @store: store instruction
17 *
18 * Note: we can trivially conditionalise the store instruction
19 * to avoid dirting the data cache.
20 */
21 .macro testop, instr, store
22 add r1, r1, r0, lsr #3
23 and r3, r0, #7
24 mov r0, #1
25 save_and_disable_irqs ip, r2
26 ldrb r2, [r1]
27 tst r2, r0, lsl r3
28 \instr r2, r2, r0, lsl r3
29 \store r2, [r1]
30 restore_irqs ip
31 moveq r0, #0
32 mov pc, lr
33 .endm
diff --git a/arch/arm/lib/changebit.S b/arch/arm/lib/changebit.S
index 3af45cab70e1..389567c24090 100644
--- a/arch/arm/lib/changebit.S
+++ b/arch/arm/lib/changebit.S
@@ -9,6 +9,7 @@
9 */ 9 */
10#include <linux/linkage.h> 10#include <linux/linkage.h>
11#include <asm/assembler.h> 11#include <asm/assembler.h>
12#include "bitops.h"
12 .text 13 .text
13 14
14/* Purpose : Function to change a bit 15/* Purpose : Function to change a bit
@@ -17,12 +18,4 @@
17ENTRY(_change_bit_be) 18ENTRY(_change_bit_be)
18 eor r0, r0, #0x18 @ big endian byte ordering 19 eor r0, r0, #0x18 @ big endian byte ordering
19ENTRY(_change_bit_le) 20ENTRY(_change_bit_le)
20 and r2, r0, #7 21 bitop eor
21 mov r3, #1
22 mov r3, r3, lsl r2
23 save_and_disable_irqs ip, r2
24 ldrb r2, [r1, r0, lsr #3]
25 eor r2, r2, r3
26 strb r2, [r1, r0, lsr #3]
27 restore_irqs ip
28 RETINSTR(mov,pc,lr)
diff --git a/arch/arm/lib/clearbit.S b/arch/arm/lib/clearbit.S
index 069a2ce413f0..347516533025 100644
--- a/arch/arm/lib/clearbit.S
+++ b/arch/arm/lib/clearbit.S
@@ -9,6 +9,7 @@
9 */ 9 */
10#include <linux/linkage.h> 10#include <linux/linkage.h>
11#include <asm/assembler.h> 11#include <asm/assembler.h>
12#include "bitops.h"
12 .text 13 .text
13 14
14/* 15/*
@@ -18,14 +19,4 @@
18ENTRY(_clear_bit_be) 19ENTRY(_clear_bit_be)
19 eor r0, r0, #0x18 @ big endian byte ordering 20 eor r0, r0, #0x18 @ big endian byte ordering
20ENTRY(_clear_bit_le) 21ENTRY(_clear_bit_le)
21 and r2, r0, #7 22 bitop bic
22 mov r3, #1
23 mov r3, r3, lsl r2
24 save_and_disable_irqs ip, r2
25 ldrb r2, [r1, r0, lsr #3]
26 bic r2, r2, r3
27 strb r2, [r1, r0, lsr #3]
28 restore_irqs ip
29 RETINSTR(mov,pc,lr)
30
31
diff --git a/arch/arm/lib/setbit.S b/arch/arm/lib/setbit.S
index 8f337df5d99b..83bc23d5b037 100644
--- a/arch/arm/lib/setbit.S
+++ b/arch/arm/lib/setbit.S
@@ -9,6 +9,7 @@
9 */ 9 */
10#include <linux/linkage.h> 10#include <linux/linkage.h>
11#include <asm/assembler.h> 11#include <asm/assembler.h>
12#include "bitops.h"
12 .text 13 .text
13 14
14/* 15/*
@@ -18,12 +19,4 @@
18ENTRY(_set_bit_be) 19ENTRY(_set_bit_be)
19 eor r0, r0, #0x18 @ big endian byte ordering 20 eor r0, r0, #0x18 @ big endian byte ordering
20ENTRY(_set_bit_le) 21ENTRY(_set_bit_le)
21 and r2, r0, #7 22 bitop orr
22 mov r3, #1
23 mov r3, r3, lsl r2
24 save_and_disable_irqs ip, r2
25 ldrb r2, [r1, r0, lsr #3]
26 orr r2, r2, r3
27 strb r2, [r1, r0, lsr #3]
28 restore_irqs ip
29 RETINSTR(mov,pc,lr)
diff --git a/arch/arm/lib/testchangebit.S b/arch/arm/lib/testchangebit.S
index 4aba4676b984..b25dcd2be53e 100644
--- a/arch/arm/lib/testchangebit.S
+++ b/arch/arm/lib/testchangebit.S
@@ -9,21 +9,10 @@
9 */ 9 */
10#include <linux/linkage.h> 10#include <linux/linkage.h>
11#include <asm/assembler.h> 11#include <asm/assembler.h>
12#include "bitops.h"
12 .text 13 .text
13 14
14ENTRY(_test_and_change_bit_be) 15ENTRY(_test_and_change_bit_be)
15 eor r0, r0, #0x18 @ big endian byte ordering 16 eor r0, r0, #0x18 @ big endian byte ordering
16ENTRY(_test_and_change_bit_le) 17ENTRY(_test_and_change_bit_le)
17 add r1, r1, r0, lsr #3 18 testop eor, strb
18 and r3, r0, #7
19 mov r0, #1
20 save_and_disable_irqs ip, r2
21 ldrb r2, [r1]
22 tst r2, r0, lsl r3
23 eor r2, r2, r0, lsl r3
24 strb r2, [r1]
25 restore_irqs ip
26 moveq r0, #0
27 RETINSTR(mov,pc,lr)
28
29
diff --git a/arch/arm/lib/testclearbit.S b/arch/arm/lib/testclearbit.S
index e07c5bd24307..2dcc4b16b68e 100644
--- a/arch/arm/lib/testclearbit.S
+++ b/arch/arm/lib/testclearbit.S
@@ -9,21 +9,10 @@
9 */ 9 */
10#include <linux/linkage.h> 10#include <linux/linkage.h>
11#include <asm/assembler.h> 11#include <asm/assembler.h>
12#include "bitops.h"
12 .text 13 .text
13 14
14ENTRY(_test_and_clear_bit_be) 15ENTRY(_test_and_clear_bit_be)
15 eor r0, r0, #0x18 @ big endian byte ordering 16 eor r0, r0, #0x18 @ big endian byte ordering
16ENTRY(_test_and_clear_bit_le) 17ENTRY(_test_and_clear_bit_le)
17 add r1, r1, r0, lsr #3 @ Get byte offset 18 testop bicne, strneb
18 and r3, r0, #7 @ Get bit offset
19 mov r0, #1
20 save_and_disable_irqs ip, r2
21 ldrb r2, [r1]
22 tst r2, r0, lsl r3
23 bic r2, r2, r0, lsl r3
24 strb r2, [r1]
25 restore_irqs ip
26 moveq r0, #0
27 RETINSTR(mov,pc,lr)
28
29
diff --git a/arch/arm/lib/testsetbit.S b/arch/arm/lib/testsetbit.S
index a570fc74cddd..9011c969761a 100644
--- a/arch/arm/lib/testsetbit.S
+++ b/arch/arm/lib/testsetbit.S
@@ -9,21 +9,10 @@
9 */ 9 */
10#include <linux/linkage.h> 10#include <linux/linkage.h>
11#include <asm/assembler.h> 11#include <asm/assembler.h>
12#include "bitops.h"
12 .text 13 .text
13 14
14ENTRY(_test_and_set_bit_be) 15ENTRY(_test_and_set_bit_be)
15 eor r0, r0, #0x18 @ big endian byte ordering 16 eor r0, r0, #0x18 @ big endian byte ordering
16ENTRY(_test_and_set_bit_le) 17ENTRY(_test_and_set_bit_le)
17 add r1, r1, r0, lsr #3 @ Get byte offset 18 testop orreq, streqb
18 and r3, r0, #7 @ Get bit offset
19 mov r0, #1
20 save_and_disable_irqs ip, r2
21 ldrb r2, [r1]
22 tst r2, r0, lsl r3
23 orr r2, r2, r0, lsl r3
24 strb r2, [r1]
25 restore_irqs ip
26 moveq r0, #0
27 RETINSTR(mov,pc,lr)
28
29
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c
index 580e1d4bce08..da5b9b7623ca 100644
--- a/arch/arm/mach-footbridge/dc21285-timer.c
+++ b/arch/arm/mach-footbridge/dc21285-timer.c
@@ -51,8 +51,6 @@ static struct irqaction footbridge_timer_irq = {
51 */ 51 */
52static void __init footbridge_timer_init(void) 52static void __init footbridge_timer_init(void)
53{ 53{
54 isa_rtc_init();
55
56 timer1_latch = (mem_fclk_21285 + 8 * HZ) / (16 * HZ); 54 timer1_latch = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
57 55
58 *CSR_TIMER1_CLR = 0; 56 *CSR_TIMER1_CLR = 0;
@@ -60,6 +58,8 @@ static void __init footbridge_timer_init(void)
60 *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | TIMER_CNTL_DIV16; 58 *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | TIMER_CNTL_DIV16;
61 59
62 setup_irq(IRQ_TIMER1, &footbridge_timer_irq); 60 setup_irq(IRQ_TIMER1, &footbridge_timer_irq);
61
62 isa_rtc_init();
63} 63}
64 64
65struct sys_timer footbridge_timer = { 65struct sys_timer footbridge_timer = {
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index 9788d3aefa73..84c86543501a 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -130,7 +130,7 @@ static int h3600_irda_set_power(struct device *dev, unsigned int state)
130 return 0; 130 return 0;
131} 131}
132 132
133static void h3600_irda_set_speed(struct device *dev, int speed) 133static void h3600_irda_set_speed(struct device *dev, unsigned int speed)
134{ 134{
135 if (speed < 4000000) { 135 if (speed < 4000000) {
136 clr_h3600_egpio(IPAQ_EGPIO_IR_FSEL); 136 clr_h3600_egpio(IPAQ_EGPIO_IR_FSEL);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 18:00:51 -0500