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-rw-r--r--arch/arm/Kconfig14
-rw-r--r--arch/arm/boot/dts/tegra-harmony.dts12
-rw-r--r--arch/arm/boot/dts/tegra-seaboard.dts6
-rw-r--r--arch/arm/include/asm/futex.h34
-rw-r--r--arch/arm/include/asm/unistd.h4
-rw-r--r--arch/arm/kernel/smp_scu.c10
-rw-r--r--arch/arm/kernel/vmlinux.lds.S15
-rw-r--r--arch/arm/mach-dove/common.c2
-rw-r--r--arch/arm/mach-exynos4/clock.c6
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c2
-rw-r--r--arch/arm/mach-integrator/pci_v3.c2
-rw-r--r--arch/arm/mach-s3c2410/Kconfig6
-rw-r--r--arch/arm/mach-s3c2410/Makefile1
-rw-r--r--arch/arm/mach-s3c2410/dma.c14
-rw-r--r--arch/arm/mach-s3c2410/gpio.c72
-rw-r--r--arch/arm/mach-s3c2410/include/mach/map.h52
-rw-r--r--arch/arm/mach-s3c2412/Kconfig1
-rw-r--r--arch/arm/mach-s3c2412/Makefile1
-rw-r--r--arch/arm/mach-s3c2412/dma.c18
-rw-r--r--arch/arm/mach-s3c2412/gpio.c62
-rw-r--r--arch/arm/mach-s3c2440/Kconfig2
-rw-r--r--arch/arm/mach-s3c2440/dma.c17
-rw-r--r--arch/arm/mach-s3c2443/clock.c2
-rw-r--r--arch/arm/mach-s3c2443/dma.c27
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/map.h9
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410.c3
-rw-r--r--arch/arm/mach-s3c64xx/mach-mini6410.c8
-rw-r--r--arch/arm/mach-s3c64xx/mach-real6410.c8
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6410.c8
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6440.c8
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6450.c8
-rw-r--r--arch/arm/mach-s5pc100/mach-smdkc100.c8
-rw-r--r--arch/arm/mach-s5pv210/Kconfig6
-rw-r--r--arch/arm/mach-s5pv210/Makefile2
-rw-r--r--arch/arm/mach-s5pv210/clock.c6
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkv210.c8
-rw-r--r--arch/arm/mm/cache-v7.S20
-rw-r--r--arch/arm/mm/dma-mapping.c2
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/map.h100
-rw-r--r--arch/arm/plat-s5p/include/plat/pll.h1
-rw-r--r--arch/arm/plat-s5p/irq-gpioint.c9
-rw-r--r--arch/arm/plat-samsung/dev-hsmmc.c19
-rw-r--r--arch/arm/plat-samsung/dev-hsmmc1.c19
-rw-r--r--arch/arm/plat-samsung/dev-hsmmc2.c19
-rw-r--r--arch/arm/plat-samsung/dev-hsmmc3.c19
-rw-r--r--arch/arm/plat-samsung/dev-ts.c9
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-s3c24xx.h6
-rw-r--r--arch/arm/plat-samsung/include/plat/map-s3c.h84
-rw-r--r--arch/arm/plat-samsung/include/plat/map-s5p.h (renamed from arch/arm/plat-s5p/include/plat/map-s5p.h)6
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h7
-rw-r--r--arch/arm/plat-samsung/platformdata.c22
51 files changed, 283 insertions, 523 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3269576dbfa8..3146ed3f6eca 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1283,6 +1283,20 @@ config ARM_ERRATA_364296
1283 processor into full low interrupt latency mode. ARM11MPCore 1283 processor into full low interrupt latency mode. ARM11MPCore
1284 is not affected. 1284 is not affected.
1285 1285
1286config ARM_ERRATA_764369
1287 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1288 depends on CPU_V7 && SMP
1289 help
1290 This option enables the workaround for erratum 764369
1291 affecting Cortex-A9 MPCore with two or more processors (all
1292 current revisions). Under certain timing circumstances, a data
1293 cache line maintenance operation by MVA targeting an Inner
1294 Shareable memory region may fail to proceed up to either the
1295 Point of Coherency or to the Point of Unification of the
1296 system. This workaround adds a DSB instruction before the
1297 relevant cache maintenance functions and sets a specific bit
1298 in the diagnostic control register of the SCU.
1299
1286endmenu 1300endmenu
1287 1301
1288source "arch/arm/common/Kconfig" 1302source "arch/arm/common/Kconfig"
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 4c053340ce33..e5818668d091 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -57,14 +57,14 @@
57 }; 57 };
58 58
59 sdhci@c8000200 { 59 sdhci@c8000200 {
60 gpios = <&gpio 69 0>, /* cd, gpio PI5 */ 60 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
61 <&gpio 57 0>, /* wp, gpio PH1 */ 61 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
62 <&gpio 155 0>; /* power, gpio PT3 */ 62 power-gpios = <&gpio 155 0>; /* gpio PT3 */
63 }; 63 };
64 64
65 sdhci@c8000600 { 65 sdhci@c8000600 {
66 gpios = <&gpio 58 0>, /* cd, gpio PH2 */ 66 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
67 <&gpio 59 0>, /* wp, gpio PH3 */ 67 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
68 <&gpio 70 0>; /* power, gpio PI6 */ 68 power-gpios = <&gpio 70 0>; /* gpio PI6 */
69 }; 69 };
70}; 70};
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index 1940cae00748..64cedca6fc79 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -21,8 +21,8 @@
21 }; 21 };
22 22
23 sdhci@c8000400 { 23 sdhci@c8000400 {
24 gpios = <&gpio 69 0>, /* cd, gpio PI5 */ 24 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
25 <&gpio 57 0>, /* wp, gpio PH1 */ 25 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
26 <&gpio 70 0>; /* power, gpio PI6 */ 26 power-gpios = <&gpio 70 0>; /* gpio PI6 */
27 }; 27 };
28}; 28};
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 8c73900da9ed..253cc86318bf 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -25,17 +25,17 @@
25 25
26#ifdef CONFIG_SMP 26#ifdef CONFIG_SMP
27 27
28#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 28#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
29 smp_mb(); \ 29 smp_mb(); \
30 __asm__ __volatile__( \ 30 __asm__ __volatile__( \
31 "1: ldrex %1, [%2]\n" \ 31 "1: ldrex %1, [%3]\n" \
32 " " insn "\n" \ 32 " " insn "\n" \
33 "2: strex %1, %0, [%2]\n" \ 33 "2: strex %2, %0, [%3]\n" \
34 " teq %1, #0\n" \ 34 " teq %2, #0\n" \
35 " bne 1b\n" \ 35 " bne 1b\n" \
36 " mov %0, #0\n" \ 36 " mov %0, #0\n" \
37 __futex_atomic_ex_table("%4") \ 37 __futex_atomic_ex_table("%5") \
38 : "=&r" (ret), "=&r" (oldval) \ 38 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
39 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ 39 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
40 : "cc", "memory") 40 : "cc", "memory")
41 41
@@ -73,14 +73,14 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
73#include <linux/preempt.h> 73#include <linux/preempt.h>
74#include <asm/domain.h> 74#include <asm/domain.h>
75 75
76#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 76#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
77 __asm__ __volatile__( \ 77 __asm__ __volatile__( \
78 "1: " T(ldr) " %1, [%2]\n" \ 78 "1: " T(ldr) " %1, [%3]\n" \
79 " " insn "\n" \ 79 " " insn "\n" \
80 "2: " T(str) " %0, [%2]\n" \ 80 "2: " T(str) " %0, [%3]\n" \
81 " mov %0, #0\n" \ 81 " mov %0, #0\n" \
82 __futex_atomic_ex_table("%4") \ 82 __futex_atomic_ex_table("%5") \
83 : "=&r" (ret), "=&r" (oldval) \ 83 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
84 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ 84 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
85 : "cc", "memory") 85 : "cc", "memory")
86 86
@@ -117,7 +117,7 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
117 int cmp = (encoded_op >> 24) & 15; 117 int cmp = (encoded_op >> 24) & 15;
118 int oparg = (encoded_op << 8) >> 20; 118 int oparg = (encoded_op << 8) >> 20;
119 int cmparg = (encoded_op << 20) >> 20; 119 int cmparg = (encoded_op << 20) >> 20;
120 int oldval = 0, ret; 120 int oldval = 0, ret, tmp;
121 121
122 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) 122 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
123 oparg = 1 << oparg; 123 oparg = 1 << oparg;
@@ -129,19 +129,19 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
129 129
130 switch (op) { 130 switch (op) {
131 case FUTEX_OP_SET: 131 case FUTEX_OP_SET:
132 __futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg); 132 __futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg);
133 break; 133 break;
134 case FUTEX_OP_ADD: 134 case FUTEX_OP_ADD:
135 __futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg); 135 __futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
136 break; 136 break;
137 case FUTEX_OP_OR: 137 case FUTEX_OP_OR:
138 __futex_atomic_op("orr %0, %1, %3", ret, oldval, uaddr, oparg); 138 __futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
139 break; 139 break;
140 case FUTEX_OP_ANDN: 140 case FUTEX_OP_ANDN:
141 __futex_atomic_op("and %0, %1, %3", ret, oldval, uaddr, ~oparg); 141 __futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
142 break; 142 break;
143 case FUTEX_OP_XOR: 143 case FUTEX_OP_XOR:
144 __futex_atomic_op("eor %0, %1, %3", ret, oldval, uaddr, oparg); 144 __futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
145 break; 145 break;
146 default: 146 default:
147 ret = -ENOSYS; 147 ret = -ENOSYS;
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 2c04ed5efeb5..c60a2944f95b 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -478,8 +478,8 @@
478/* 478/*
479 * Unimplemented (or alternatively implemented) syscalls 479 * Unimplemented (or alternatively implemented) syscalls
480 */ 480 */
481#define __IGNORE_fadvise64_64 1 481#define __IGNORE_fadvise64_64
482#define __IGNORE_migrate_pages 1 482#define __IGNORE_migrate_pages
483 483
484#endif /* __KERNEL__ */ 484#endif /* __KERNEL__ */
485#endif /* __ASM_ARM_UNISTD_H */ 485#endif /* __ASM_ARM_UNISTD_H */
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 79ed5e7f204a..7fcddb75c877 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -13,6 +13,7 @@
13 13
14#include <asm/smp_scu.h> 14#include <asm/smp_scu.h>
15#include <asm/cacheflush.h> 15#include <asm/cacheflush.h>
16#include <asm/cputype.h>
16 17
17#define SCU_CTRL 0x00 18#define SCU_CTRL 0x00
18#define SCU_CONFIG 0x04 19#define SCU_CONFIG 0x04
@@ -37,6 +38,15 @@ void __init scu_enable(void __iomem *scu_base)
37{ 38{
38 u32 scu_ctrl; 39 u32 scu_ctrl;
39 40
41#ifdef CONFIG_ARM_ERRATA_764369
42 /* Cortex-A9 only */
43 if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
44 scu_ctrl = __raw_readl(scu_base + 0x30);
45 if (!(scu_ctrl & 1))
46 __raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
47 }
48#endif
49
40 scu_ctrl = __raw_readl(scu_base + SCU_CTRL); 50 scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
41 /* already enabled? */ 51 /* already enabled? */
42 if (scu_ctrl & 1) 52 if (scu_ctrl & 1)
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index bf977f8514f6..4e66f62b8d41 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -23,8 +23,10 @@
23 23
24#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK) 24#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
25#define ARM_EXIT_KEEP(x) x 25#define ARM_EXIT_KEEP(x) x
26#define ARM_EXIT_DISCARD(x)
26#else 27#else
27#define ARM_EXIT_KEEP(x) 28#define ARM_EXIT_KEEP(x)
29#define ARM_EXIT_DISCARD(x) x
28#endif 30#endif
29 31
30OUTPUT_ARCH(arm) 32OUTPUT_ARCH(arm)
@@ -39,6 +41,11 @@ jiffies = jiffies_64 + 4;
39SECTIONS 41SECTIONS
40{ 42{
41 /* 43 /*
44 * XXX: The linker does not define how output sections are
45 * assigned to input sections when there are multiple statements
46 * matching the same input section name. There is no documented
47 * order of matching.
48 *
42 * unwind exit sections must be discarded before the rest of the 49 * unwind exit sections must be discarded before the rest of the
43 * unwind sections get included. 50 * unwind sections get included.
44 */ 51 */
@@ -47,6 +54,9 @@ SECTIONS
47 *(.ARM.extab.exit.text) 54 *(.ARM.extab.exit.text)
48 ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text)) 55 ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
49 ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text)) 56 ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
57 ARM_EXIT_DISCARD(EXIT_TEXT)
58 ARM_EXIT_DISCARD(EXIT_DATA)
59 EXIT_CALL
50#ifndef CONFIG_HOTPLUG 60#ifndef CONFIG_HOTPLUG
51 *(.ARM.exidx.devexit.text) 61 *(.ARM.exidx.devexit.text)
52 *(.ARM.extab.devexit.text) 62 *(.ARM.extab.devexit.text)
@@ -58,6 +68,8 @@ SECTIONS
58#ifndef CONFIG_SMP_ON_UP 68#ifndef CONFIG_SMP_ON_UP
59 *(.alt.smp.init) 69 *(.alt.smp.init)
60#endif 70#endif
71 *(.discard)
72 *(.discard.*)
61 } 73 }
62 74
63#ifdef CONFIG_XIP_KERNEL 75#ifdef CONFIG_XIP_KERNEL
@@ -279,9 +291,6 @@ SECTIONS
279 291
280 STABS_DEBUG 292 STABS_DEBUG
281 .comment 0 : { *(.comment) } 293 .comment 0 : { *(.comment) }
282
283 /* Default discards */
284 DISCARDS
285} 294}
286 295
287/* 296/*
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 83dce859886d..a9e0dae86a26 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -158,7 +158,7 @@ void __init dove_spi0_init(void)
158 158
159void __init dove_spi1_init(void) 159void __init dove_spi1_init(void)
160{ 160{
161 orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk()); 161 orion_spi_1_init(DOVE_SPI1_PHYS_BASE, get_tclk());
162} 162}
163 163
164/***************************************************************************** 164/*****************************************************************************
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index f26aea3e1bbf..413c7cc81979 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -948,8 +948,7 @@ static struct clksrc_clk clksrcs[] = {
948 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 }, 948 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
949 }, { 949 }, {
950 .clk = { 950 .clk = {
951 .name = "sclk_cam", 951 .name = "sclk_cam0",
952 .devname = "exynos4-fimc.0",
953 .enable = exynos4_clksrc_mask_cam_ctrl, 952 .enable = exynos4_clksrc_mask_cam_ctrl,
954 .ctrlbit = (1 << 16), 953 .ctrlbit = (1 << 16),
955 }, 954 },
@@ -958,8 +957,7 @@ static struct clksrc_clk clksrcs[] = {
958 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 }, 957 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
959 }, { 958 }, {
960 .clk = { 959 .clk = {
961 .name = "sclk_cam", 960 .name = "sclk_cam1",
962 .devname = "exynos4-fimc.1",
963 .enable = exynos4_clksrc_mask_cam_ctrl, 961 .enable = exynos4_clksrc_mask_cam_ctrl,
964 .ctrlbit = (1 << 20), 962 .ctrlbit = (1 << 20),
965 }, 963 },
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index fcf0ae95651f..8cdc730dcb3a 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -32,6 +32,7 @@
32#include <linux/interrupt.h> 32#include <linux/interrupt.h>
33#include <linux/io.h> 33#include <linux/io.h>
34#include <linux/mtd/physmap.h> 34#include <linux/mtd/physmap.h>
35#include <video/vga.h>
35 36
36#include <mach/hardware.h> 37#include <mach/hardware.h>
37#include <mach/platform.h> 38#include <mach/platform.h>
@@ -154,6 +155,7 @@ static struct map_desc ap_io_desc[] __initdata = {
154static void __init ap_map_io(void) 155static void __init ap_map_io(void)
155{ 156{
156 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); 157 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
158 vga_base = PCI_MEMORY_VADDR;
157} 159}
158 160
159#define INTEGRATOR_SC_VALID_INT 0x003fffff 161#define INTEGRATOR_SC_VALID_INT 0x003fffff
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index dd56bfb351e3..11b86e5b71c2 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -27,7 +27,6 @@
27#include <linux/spinlock.h> 27#include <linux/spinlock.h>
28#include <linux/init.h> 28#include <linux/init.h>
29#include <linux/io.h> 29#include <linux/io.h>
30#include <video/vga.h>
31 30
32#include <mach/hardware.h> 31#include <mach/hardware.h>
33#include <mach/platform.h> 32#include <mach/platform.h>
@@ -505,7 +504,6 @@ void __init pci_v3_preinit(void)
505 504
506 pcibios_min_io = 0x6000; 505 pcibios_min_io = 0x6000;
507 pcibios_min_mem = 0x00100000; 506 pcibios_min_mem = 0x00100000;
508 vga_base = PCI_MEMORY_VADDR;
509 507
510 /* 508 /*
511 * Hook in our fault handler for PCI errors 509 * Hook in our fault handler for PCI errors
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 7245a55795dc..3700cf32af0f 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -8,7 +8,6 @@ config CPU_S3C2410
8 select CPU_ARM920T 8 select CPU_ARM920T
9 select S3C_GPIO_PULL_UP 9 select S3C_GPIO_PULL_UP
10 select S3C2410_CLOCK 10 select S3C2410_CLOCK
11 select S3C2410_GPIO
12 select CPU_LLSERIAL_S3C2410 11 select CPU_LLSERIAL_S3C2410
13 select S3C2410_PM if PM 12 select S3C2410_PM if PM
14 select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX 13 select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
@@ -28,11 +27,6 @@ config S3C2410_PM
28 help 27 help
29 Power Management code common to S3C2410 and better 28 Power Management code common to S3C2410 and better
30 29
31config S3C2410_GPIO
32 bool
33 help
34 GPIO code for S3C2410 and similar processors
35
36config SIMTEC_NOR 30config SIMTEC_NOR
37 bool 31 bool
38 help 32 help
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 81695353d8f4..782fd81144e9 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -13,7 +13,6 @@ obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
13obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o 13obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
14obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o 14obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
15obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o 15obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o
16obj-$(CONFIG_S3C2410_GPIO) += gpio.o
17obj-$(CONFIG_S3C2410_CPUFREQ) += cpu-freq.o 16obj-$(CONFIG_S3C2410_CPUFREQ) += cpu-freq.o
18obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o 17obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o
19 18
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 0d8e043804c2..dbe43df8cfec 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -47,38 +47,26 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
47 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID, 47 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
48 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID, 48 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
49 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID, 49 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
50 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
51 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
52 }, 50 },
53 [DMACH_SPI0] = { 51 [DMACH_SPI0] = {
54 .name = "spi0", 52 .name = "spi0",
55 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID, 53 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
56 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
57 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
58 }, 54 },
59 [DMACH_SPI1] = { 55 [DMACH_SPI1] = {
60 .name = "spi1", 56 .name = "spi1",
61 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID, 57 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
62 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
63 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
64 }, 58 },
65 [DMACH_UART0] = { 59 [DMACH_UART0] = {
66 .name = "uart0", 60 .name = "uart0",
67 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID, 61 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
68 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
69 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
70 }, 62 },
71 [DMACH_UART1] = { 63 [DMACH_UART1] = {
72 .name = "uart1", 64 .name = "uart1",
73 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID, 65 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
74 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
75 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
76 }, 66 },
77 [DMACH_UART2] = { 67 [DMACH_UART2] = {
78 .name = "uart2", 68 .name = "uart2",
79 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID, 69 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
80 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
81 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
82 }, 70 },
83 [DMACH_TIMER] = { 71 [DMACH_TIMER] = {
84 .name = "timer", 72 .name = "timer",
@@ -90,12 +78,10 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
90 .name = "i2s-sdi", 78 .name = "i2s-sdi",
91 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID, 79 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
92 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID, 80 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
93 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
94 }, 81 },
95 [DMACH_I2S_OUT] = { 82 [DMACH_I2S_OUT] = {
96 .name = "i2s-sdo", 83 .name = "i2s-sdo",
97 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID, 84 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
98 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
99 }, 85 },
100 [DMACH_USB_EP1] = { 86 [DMACH_USB_EP1] = {
101 .name = "usb-ep1", 87 .name = "usb-ep1",
diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
deleted file mode 100644
index 9664e011dae2..000000000000
--- a/arch/arm/mach-s3c2410/gpio.c
+++ /dev/null
@@ -1,72 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/gpio.c
2 *
3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 GPIO support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/interrupt.h>
27#include <linux/ioport.h>
28#include <linux/io.h>
29
30#include <mach/hardware.h>
31#include <mach/gpio-fns.h>
32#include <asm/irq.h>
33
34#include <mach/regs-gpio.h>
35
36int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
37 unsigned int config)
38{
39 void __iomem *reg = S3C24XX_EINFLT0;
40 unsigned long flags;
41 unsigned long val;
42
43 if (pin < S3C2410_GPG(8) || pin > S3C2410_GPG(15))
44 return -EINVAL;
45
46 config &= 0xff;
47
48 pin -= S3C2410_GPG(8);
49 reg += pin & ~3;
50
51 local_irq_save(flags);
52
53 /* update filter width and clock source */
54
55 val = __raw_readl(reg);
56 val &= ~(0xff << ((pin & 3) * 8));
57 val |= config << ((pin & 3) * 8);
58 __raw_writel(val, reg);
59
60 /* update filter enable */
61
62 val = __raw_readl(S3C24XX_EXTINT2);
63 val &= ~(1 << ((pin * 4) + 3));
64 val |= on << ((pin * 4) + 3);
65 __raw_writel(val, S3C24XX_EXTINT2);
66
67 local_irq_restore(flags);
68
69 return 0;
70}
71
72EXPORT_SYMBOL(s3c2410_gpio_irqfilter);
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index 425552d84b60..4cf495f813a7 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -14,9 +14,53 @@
14#define __ASM_ARCH_MAP_H 14#define __ASM_ARCH_MAP_H
15 15
16#include <plat/map-base.h> 16#include <plat/map-base.h>
17#include <plat/map.h>
18 17
19#define S3C2410_ADDR(x) S3C_ADDR(x) 18/*
19 * S3C2410 UART offset is 0x4000 but the other SoCs are 0x400.
20 * So need to define it, and here is to avoid redefinition warning.
21 */
22#define S3C_UART_OFFSET (0x4000)
23
24#include <plat/map-s3c.h>
25
26/*
27 * interrupt controller is the first thing we put in, to make
28 * the assembly code for the irq detection easier
29 */
30#define S3C2410_PA_IRQ (0x4A000000)
31#define S3C24XX_SZ_IRQ SZ_1M
32
33/* memory controller registers */
34#define S3C2410_PA_MEMCTRL (0x48000000)
35#define S3C24XX_SZ_MEMCTRL SZ_1M
36
37/* UARTs */
38#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
39
40/* Timers */
41#define S3C2410_PA_TIMER (0x51000000)
42#define S3C24XX_SZ_TIMER SZ_1M
43
44/* Clock and Power management */
45#define S3C24XX_SZ_CLKPWR SZ_1M
46
47/* USB Device port */
48#define S3C2410_PA_USBDEV (0x52000000)
49#define S3C24XX_SZ_USBDEV SZ_1M
50
51/* Watchdog */
52#define S3C2410_PA_WATCHDOG (0x53000000)
53#define S3C24XX_SZ_WATCHDOG SZ_1M
54
55/* Standard size definitions for peripheral blocks. */
56
57#define S3C24XX_SZ_UART SZ_1M
58#define S3C24XX_SZ_IIS SZ_1M
59#define S3C24XX_SZ_ADC SZ_1M
60#define S3C24XX_SZ_SPI SZ_1M
61#define S3C24XX_SZ_SDI SZ_1M
62#define S3C24XX_SZ_NAND SZ_1M
63#define S3C24XX_SZ_GPIO SZ_1M
20 64
21/* USB host controller */ 65/* USB host controller */
22#define S3C2410_PA_USBHOST (0x49000000) 66#define S3C2410_PA_USBHOST (0x49000000)
@@ -75,10 +119,8 @@
75 119
76/* S3C2412 memory and IO controls */ 120/* S3C2412 memory and IO controls */
77#define S3C2412_PA_SSMC (0x4F000000) 121#define S3C2412_PA_SSMC (0x4F000000)
78#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
79 122
80#define S3C2412_PA_EBI (0x48800000) 123#define S3C2412_PA_EBI (0x48800000)
81#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000)
82 124
83/* physical addresses of all the chip-select areas */ 125/* physical addresses of all the chip-select areas */
84 126
@@ -100,12 +142,10 @@
100#define S3C24XX_PA_DMA S3C2410_PA_DMA 142#define S3C24XX_PA_DMA S3C2410_PA_DMA
101#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR 143#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
102#define S3C24XX_PA_LCD S3C2410_PA_LCD 144#define S3C24XX_PA_LCD S3C2410_PA_LCD
103#define S3C24XX_PA_UART S3C2410_PA_UART
104#define S3C24XX_PA_TIMER S3C2410_PA_TIMER 145#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
105#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV 146#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
106#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG 147#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
107#define S3C24XX_PA_IIS S3C2410_PA_IIS 148#define S3C24XX_PA_IIS S3C2410_PA_IIS
108#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
109#define S3C24XX_PA_RTC S3C2410_PA_RTC 149#define S3C24XX_PA_RTC S3C2410_PA_RTC
110#define S3C24XX_PA_ADC S3C2410_PA_ADC 150#define S3C24XX_PA_ADC S3C2410_PA_ADC
111#define S3C24XX_PA_SPI S3C2410_PA_SPI 151#define S3C24XX_PA_SPI S3C2410_PA_SPI
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index c2cf4e569989..b8b9029e9f2d 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -9,7 +9,6 @@ config CPU_S3C2412
9 select CPU_LLSERIAL_S3C2440 9 select CPU_LLSERIAL_S3C2440
10 select S3C2412_PM if PM 10 select S3C2412_PM if PM
11 select S3C2412_DMA if S3C2410_DMA 11 select S3C2412_DMA if S3C2410_DMA
12 select S3C2410_GPIO
13 help 12 help
14 Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line 13 Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
15 14
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 6c48a91ea39e..7e4d95fa8a97 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -12,7 +12,6 @@ obj- :=
12obj-$(CONFIG_CPU_S3C2412) += s3c2412.o 12obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
13obj-$(CONFIG_CPU_S3C2412) += irq.o 13obj-$(CONFIG_CPU_S3C2412) += irq.o
14obj-$(CONFIG_CPU_S3C2412) += clock.o 14obj-$(CONFIG_CPU_S3C2412) += clock.o
15obj-$(CONFIG_CPU_S3C2412) += gpio.o
16obj-$(CONFIG_S3C2412_DMA) += dma.o 15obj-$(CONFIG_S3C2412_DMA) += dma.o
17obj-$(CONFIG_S3C2412_PM) += pm.o 16obj-$(CONFIG_S3C2412_PM) += pm.o
18obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep.o 17obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep.o
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 7abecfca0b7e..c61e3261615d 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -50,64 +50,46 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
50 .name = "sdi", 50 .name = "sdi",
51 .channels = MAP(S3C2412_DMAREQSEL_SDI), 51 .channels = MAP(S3C2412_DMAREQSEL_SDI),
52 .channels_rx = MAP(S3C2412_DMAREQSEL_SDI), 52 .channels_rx = MAP(S3C2412_DMAREQSEL_SDI),
53 .hw_addr.to = S3C2410_PA_SDI + S3C2410_SDIDATA,
54 .hw_addr.from = S3C2410_PA_SDI + S3C2410_SDIDATA,
55 }, 53 },
56 [DMACH_SPI0] = { 54 [DMACH_SPI0] = {
57 .name = "spi0", 55 .name = "spi0",
58 .channels = MAP(S3C2412_DMAREQSEL_SPI0TX), 56 .channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
59 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX), 57 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX),
60 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
61 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
62 }, 58 },
63 [DMACH_SPI1] = { 59 [DMACH_SPI1] = {
64 .name = "spi1", 60 .name = "spi1",
65 .channels = MAP(S3C2412_DMAREQSEL_SPI1TX), 61 .channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
66 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX), 62 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX),
67 .hw_addr.to = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT,
68 .hw_addr.from = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPRDAT,
69 }, 63 },
70 [DMACH_UART0] = { 64 [DMACH_UART0] = {
71 .name = "uart0", 65 .name = "uart0",
72 .channels = MAP(S3C2412_DMAREQSEL_UART0_0), 66 .channels = MAP(S3C2412_DMAREQSEL_UART0_0),
73 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0), 67 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0),
74 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
75 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
76 }, 68 },
77 [DMACH_UART1] = { 69 [DMACH_UART1] = {
78 .name = "uart1", 70 .name = "uart1",
79 .channels = MAP(S3C2412_DMAREQSEL_UART1_0), 71 .channels = MAP(S3C2412_DMAREQSEL_UART1_0),
80 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0), 72 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0),
81 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
82 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
83 }, 73 },
84 [DMACH_UART2] = { 74 [DMACH_UART2] = {
85 .name = "uart2", 75 .name = "uart2",
86 .channels = MAP(S3C2412_DMAREQSEL_UART2_0), 76 .channels = MAP(S3C2412_DMAREQSEL_UART2_0),
87 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0), 77 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0),
88 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
89 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
90 }, 78 },
91 [DMACH_UART0_SRC2] = { 79 [DMACH_UART0_SRC2] = {
92 .name = "uart0", 80 .name = "uart0",
93 .channels = MAP(S3C2412_DMAREQSEL_UART0_1), 81 .channels = MAP(S3C2412_DMAREQSEL_UART0_1),
94 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1), 82 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1),
95 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
96 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
97 }, 83 },
98 [DMACH_UART1_SRC2] = { 84 [DMACH_UART1_SRC2] = {
99 .name = "uart1", 85 .name = "uart1",
100 .channels = MAP(S3C2412_DMAREQSEL_UART1_1), 86 .channels = MAP(S3C2412_DMAREQSEL_UART1_1),
101 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1), 87 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1),
102 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
103 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
104 }, 88 },
105 [DMACH_UART2_SRC2] = { 89 [DMACH_UART2_SRC2] = {
106 .name = "uart2", 90 .name = "uart2",
107 .channels = MAP(S3C2412_DMAREQSEL_UART2_1), 91 .channels = MAP(S3C2412_DMAREQSEL_UART2_1),
108 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1), 92 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1),
109 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
110 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
111 }, 93 },
112 [DMACH_TIMER] = { 94 [DMACH_TIMER] = {
113 .name = "timer", 95 .name = "timer",
diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c
deleted file mode 100644
index 3404a876b33e..000000000000
--- a/arch/arm/mach-s3c2412/gpio.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/* linux/arch/arm/mach-s3c2412/gpio.c
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://armlinux.simtec.co.uk/.
7 *
8 * S3C2412/S3C2413 specific GPIO support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/module.h>
18#include <linux/interrupt.h>
19#include <linux/gpio.h>
20
21#include <asm/mach/arch.h>
22#include <asm/mach/map.h>
23
24#include <mach/regs-gpio.h>
25#include <mach/hardware.h>
26
27#include <plat/gpio-core.h>
28
29int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
30{
31 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
32 unsigned long offs = pin - chip->chip.base;
33 unsigned long flags;
34 unsigned long slpcon;
35
36 offs *= 2;
37
38 if (pin < S3C2410_GPB(0))
39 return -EINVAL;
40
41 if (pin >= S3C2410_GPF(0) &&
42 pin <= S3C2410_GPG(16))
43 return -EINVAL;
44
45 if (pin > S3C2410_GPH(16))
46 return -EINVAL;
47
48 local_irq_save(flags);
49
50 slpcon = __raw_readl(chip->base + 0x0C);
51
52 slpcon &= ~(3 << offs);
53 slpcon |= state << offs;
54
55 __raw_writel(slpcon, chip->base + 0x0C);
56
57 local_irq_restore(flags);
58
59 return 0;
60}
61
62EXPORT_SYMBOL(s3c2412_gpio_set_sleepcfg);
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index 50825a3f91cc..c461fb8e15c0 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -8,7 +8,6 @@ config CPU_S3C2440
8 select S3C_GPIO_PULL_UP 8 select S3C_GPIO_PULL_UP
9 select S3C2410_CLOCK 9 select S3C2410_CLOCK
10 select S3C2410_PM if PM 10 select S3C2410_PM if PM
11 select S3C2410_GPIO
12 select S3C2440_DMA if S3C2410_DMA 11 select S3C2440_DMA if S3C2410_DMA
13 select CPU_S3C244X 12 select CPU_S3C244X
14 select CPU_LLSERIAL_S3C2440 13 select CPU_LLSERIAL_S3C2440
@@ -20,7 +19,6 @@ config CPU_S3C2442
20 select CPU_ARM920T 19 select CPU_ARM920T
21 select S3C_GPIO_PULL_DOWN 20 select S3C_GPIO_PULL_DOWN
22 select S3C2410_CLOCK 21 select S3C2410_CLOCK
23 select S3C2410_GPIO
24 select S3C2410_PM if PM 22 select S3C2410_PM if PM
25 select CPU_S3C244X 23 select CPU_S3C244X
26 select CPU_LLSERIAL_S3C2440 24 select CPU_LLSERIAL_S3C2440
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index 3b0529f54e9c..0e73f8f9d132 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -48,38 +48,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
48 .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID, 48 .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
49 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID, 49 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
50 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID, 50 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
51 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
52 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
53 }, 51 },
54 [DMACH_SPI0] = { 52 [DMACH_SPI0] = {
55 .name = "spi0", 53 .name = "spi0",
56 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID, 54 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
57 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
58 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
59 }, 55 },
60 [DMACH_SPI1] = { 56 [DMACH_SPI1] = {
61 .name = "spi1", 57 .name = "spi1",
62 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID, 58 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
63 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
64 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
65 }, 59 },
66 [DMACH_UART0] = { 60 [DMACH_UART0] = {
67 .name = "uart0", 61 .name = "uart0",
68 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID, 62 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
69 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
70 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
71 }, 63 },
72 [DMACH_UART1] = { 64 [DMACH_UART1] = {
73 .name = "uart1", 65 .name = "uart1",
74 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID, 66 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
75 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
76 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
77 }, 67 },
78 [DMACH_UART2] = { 68 [DMACH_UART2] = {
79 .name = "uart2", 69 .name = "uart2",
80 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID, 70 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
81 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
82 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
83 }, 71 },
84 [DMACH_TIMER] = { 72 [DMACH_TIMER] = {
85 .name = "timer", 73 .name = "timer",
@@ -91,31 +79,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
91 .name = "i2s-sdi", 79 .name = "i2s-sdi",
92 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID, 80 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
93 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID, 81 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
94 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
95 }, 82 },
96 [DMACH_I2S_OUT] = { 83 [DMACH_I2S_OUT] = {
97 .name = "i2s-sdo", 84 .name = "i2s-sdo",
98 .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID, 85 .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
99 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID, 86 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
100 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
101 }, 87 },
102 [DMACH_PCM_IN] = { 88 [DMACH_PCM_IN] = {
103 .name = "pcm-in", 89 .name = "pcm-in",
104 .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID, 90 .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
105 .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID, 91 .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
106 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
107 }, 92 },
108 [DMACH_PCM_OUT] = { 93 [DMACH_PCM_OUT] = {
109 .name = "pcm-out", 94 .name = "pcm-out",
110 .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID, 95 .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
111 .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID, 96 .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
112 .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
113 }, 97 },
114 [DMACH_MIC_IN] = { 98 [DMACH_MIC_IN] = {
115 .name = "mic-in", 99 .name = "mic-in",
116 .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID, 100 .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
117 .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID, 101 .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
118 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
119 }, 102 },
120 [DMACH_USB_EP1] = { 103 [DMACH_USB_EP1] = {
121 .name = "usb-ep1", 104 .name = "usb-ep1",
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index a1a7176675b9..38058af48972 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -128,7 +128,7 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
128 unsigned long clkcon0; 128 unsigned long clkcon0;
129 129
130 clkcon0 = __raw_readl(S3C2443_CLKDIV0); 130 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
131 clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK; 131 clkcon0 &= ~S3C2443_CLKDIV0_ARMDIV_MASK;
132 clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT; 132 clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
133 __raw_writel(clkcon0, S3C2443_CLKDIV0); 133 __raw_writel(clkcon0, S3C2443_CLKDIV0);
134 } 134 }
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index 3f658685ec16..fe52151d2e84 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -54,68 +54,46 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
54 [DMACH_SDI] = { 54 [DMACH_SDI] = {
55 .name = "sdi", 55 .name = "sdi",
56 .channels = MAP(S3C2443_DMAREQSEL_SDI), 56 .channels = MAP(S3C2443_DMAREQSEL_SDI),
57 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
58 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
59 }, 57 },
60 [DMACH_SPI0] = { 58 [DMACH_SPI0] = {
61 .name = "spi0", 59 .name = "spi0",
62 .channels = MAP(S3C2443_DMAREQSEL_SPI0TX), 60 .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
63 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
64 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
65 }, 61 },
66 [DMACH_SPI1] = { 62 [DMACH_SPI1] = {
67 .name = "spi1", 63 .name = "spi1",
68 .channels = MAP(S3C2443_DMAREQSEL_SPI1TX), 64 .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
69 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
70 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
71 }, 65 },
72 [DMACH_UART0] = { 66 [DMACH_UART0] = {
73 .name = "uart0", 67 .name = "uart0",
74 .channels = MAP(S3C2443_DMAREQSEL_UART0_0), 68 .channels = MAP(S3C2443_DMAREQSEL_UART0_0),
75 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
76 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
77 }, 69 },
78 [DMACH_UART1] = { 70 [DMACH_UART1] = {
79 .name = "uart1", 71 .name = "uart1",
80 .channels = MAP(S3C2443_DMAREQSEL_UART1_0), 72 .channels = MAP(S3C2443_DMAREQSEL_UART1_0),
81 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
82 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
83 }, 73 },
84 [DMACH_UART2] = { 74 [DMACH_UART2] = {
85 .name = "uart2", 75 .name = "uart2",
86 .channels = MAP(S3C2443_DMAREQSEL_UART2_0), 76 .channels = MAP(S3C2443_DMAREQSEL_UART2_0),
87 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
88 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
89 }, 77 },
90 [DMACH_UART3] = { 78 [DMACH_UART3] = {
91 .name = "uart3", 79 .name = "uart3",
92 .channels = MAP(S3C2443_DMAREQSEL_UART3_0), 80 .channels = MAP(S3C2443_DMAREQSEL_UART3_0),
93 .hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
94 .hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
95 }, 81 },
96 [DMACH_UART0_SRC2] = { 82 [DMACH_UART0_SRC2] = {
97 .name = "uart0", 83 .name = "uart0",
98 .channels = MAP(S3C2443_DMAREQSEL_UART0_1), 84 .channels = MAP(S3C2443_DMAREQSEL_UART0_1),
99 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
100 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
101 }, 85 },
102 [DMACH_UART1_SRC2] = { 86 [DMACH_UART1_SRC2] = {
103 .name = "uart1", 87 .name = "uart1",
104 .channels = MAP(S3C2443_DMAREQSEL_UART1_1), 88 .channels = MAP(S3C2443_DMAREQSEL_UART1_1),
105 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
106 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
107 }, 89 },
108 [DMACH_UART2_SRC2] = { 90 [DMACH_UART2_SRC2] = {
109 .name = "uart2", 91 .name = "uart2",
110 .channels = MAP(S3C2443_DMAREQSEL_UART2_1), 92 .channels = MAP(S3C2443_DMAREQSEL_UART2_1),
111 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
112 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
113 }, 93 },
114 [DMACH_UART3_SRC2] = { 94 [DMACH_UART3_SRC2] = {
115 .name = "uart3", 95 .name = "uart3",
116 .channels = MAP(S3C2443_DMAREQSEL_UART3_1), 96 .channels = MAP(S3C2443_DMAREQSEL_UART3_1),
117 .hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
118 .hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
119 }, 97 },
120 [DMACH_TIMER] = { 98 [DMACH_TIMER] = {
121 .name = "timer", 99 .name = "timer",
@@ -124,27 +102,22 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
124 [DMACH_I2S_IN] = { 102 [DMACH_I2S_IN] = {
125 .name = "i2s-sdi", 103 .name = "i2s-sdi",
126 .channels = MAP(S3C2443_DMAREQSEL_I2SRX), 104 .channels = MAP(S3C2443_DMAREQSEL_I2SRX),
127 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
128 }, 105 },
129 [DMACH_I2S_OUT] = { 106 [DMACH_I2S_OUT] = {
130 .name = "i2s-sdo", 107 .name = "i2s-sdo",
131 .channels = MAP(S3C2443_DMAREQSEL_I2STX), 108 .channels = MAP(S3C2443_DMAREQSEL_I2STX),
132 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
133 }, 109 },
134 [DMACH_PCM_IN] = { 110 [DMACH_PCM_IN] = {
135 .name = "pcm-in", 111 .name = "pcm-in",
136 .channels = MAP(S3C2443_DMAREQSEL_PCMIN), 112 .channels = MAP(S3C2443_DMAREQSEL_PCMIN),
137 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
138 }, 113 },
139 [DMACH_PCM_OUT] = { 114 [DMACH_PCM_OUT] = {
140 .name = "pcm-out", 115 .name = "pcm-out",
141 .channels = MAP(S3C2443_DMAREQSEL_PCMOUT), 116 .channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
142 .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
143 }, 117 },
144 [DMACH_MIC_IN] = { 118 [DMACH_MIC_IN] = {
145 .name = "mic-in", 119 .name = "mic-in",
146 .channels = MAP(S3C2443_DMAREQSEL_MICIN), 120 .channels = MAP(S3C2443_DMAREQSEL_MICIN),
147 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
148 }, 121 },
149}; 122};
150 123
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index a1f13f02c841..23a1d71e4d53 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -16,6 +16,7 @@
16#define __ASM_ARCH_MAP_H __FILE__ 16#define __ASM_ARCH_MAP_H __FILE__
17 17
18#include <plat/map-base.h> 18#include <plat/map-base.h>
19#include <plat/map-s3c.h>
19 20
20/* 21/*
21 * Post-mux Chip Select Regions Xm0CSn_ 22 * Post-mux Chip Select Regions Xm0CSn_
@@ -83,7 +84,6 @@
83#define S3C64XX_PA_IIC1 (0x7F00F000) 84#define S3C64XX_PA_IIC1 (0x7F00F000)
84 85
85#define S3C64XX_PA_GPIO (0x7F008000) 86#define S3C64XX_PA_GPIO (0x7F008000)
86#define S3C64XX_VA_GPIO S3C_ADDR_CPU(0x00000000)
87#define S3C64XX_SZ_GPIO SZ_4K 87#define S3C64XX_SZ_GPIO SZ_4K
88 88
89#define S3C64XX_PA_SDRAM (0x50000000) 89#define S3C64XX_PA_SDRAM (0x50000000)
@@ -94,16 +94,10 @@
94#define S3C64XX_PA_VIC1 (0x71300000) 94#define S3C64XX_PA_VIC1 (0x71300000)
95 95
96#define S3C64XX_PA_MODEM (0x74108000) 96#define S3C64XX_PA_MODEM (0x74108000)
97#define S3C64XX_VA_MODEM S3C_ADDR_CPU(0x00100000)
98 97
99#define S3C64XX_PA_USBHOST (0x74300000) 98#define S3C64XX_PA_USBHOST (0x74300000)
100 99
101#define S3C64XX_PA_USB_HSPHY (0x7C100000) 100#define S3C64XX_PA_USB_HSPHY (0x7C100000)
102#define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000)
103
104/* place VICs close together */
105#define VA_VIC0 (S3C_VA_IRQ + 0x00)
106#define VA_VIC1 (S3C_VA_IRQ + 0x10000)
107 101
108/* compatibiltiy defines. */ 102/* compatibiltiy defines. */
109#define S3C_PA_TIMER S3C64XX_PA_TIMER 103#define S3C_PA_TIMER S3C64XX_PA_TIMER
@@ -119,7 +113,6 @@
119#define S3C_PA_FB S3C64XX_PA_FB 113#define S3C_PA_FB S3C64XX_PA_FB
120#define S3C_PA_USBHOST S3C64XX_PA_USBHOST 114#define S3C_PA_USBHOST S3C64XX_PA_USBHOST
121#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG 115#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
122#define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY
123#define S3C_PA_RTC S3C64XX_PA_RTC 116#define S3C_PA_RTC S3C64XX_PA_RTC
124#define S3C_PA_WDT S3C64XX_PA_WATCHDOG 117#define S3C_PA_WDT S3C64XX_PA_WATCHDOG
125 118
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index af0c2fe1ea37..f32ec68002ef 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -329,9 +329,6 @@ static struct platform_device *crag6410_devices[] __initdata = {
329 &s3c_device_fb, 329 &s3c_device_fb,
330 &s3c_device_ohci, 330 &s3c_device_ohci,
331 &s3c_device_usb_hsotg, 331 &s3c_device_usb_hsotg,
332 &s3c_device_adc,
333 &s3c_device_rtc,
334 &s3c_device_ts,
335 &s3c_device_timer[0], 332 &s3c_device_timer[0],
336 &s3c64xx_device_iis0, 333 &s3c64xx_device_iis0,
337 &s3c64xx_device_iis1, 334 &s3c64xx_device_iis1,
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 527f49bd1b57..8f34a3c10497 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -205,12 +205,6 @@ static struct platform_device mini6410_lcd_powerdev = {
205 .dev.platform_data = &mini6410_lcd_power_data, 205 .dev.platform_data = &mini6410_lcd_power_data,
206}; 206};
207 207
208static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
209 .delay = 10000,
210 .presc = 49,
211 .oversampling_shift = 2,
212};
213
214static struct platform_device *mini6410_devices[] __initdata = { 208static struct platform_device *mini6410_devices[] __initdata = {
215 &mini6410_device_eth, 209 &mini6410_device_eth,
216 &s3c_device_hsmmc0, 210 &s3c_device_hsmmc0,
@@ -319,7 +313,7 @@ static void __init mini6410_machine_init(void)
319 313
320 s3c_nand_set_platdata(&mini6410_nand_info); 314 s3c_nand_set_platdata(&mini6410_nand_info);
321 s3c_fb_set_platdata(&mini6410_lcd_pdata); 315 s3c_fb_set_platdata(&mini6410_lcd_pdata);
322 s3c24xx_ts_set_platdata(&s3c_ts_platform); 316 s3c24xx_ts_set_platdata(NULL);
323 317
324 /* configure nCS1 width to 16 bits */ 318 /* configure nCS1 width to 16 bits */
325 319
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 95b04b1729e3..1f5abfae4eac 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -198,12 +198,6 @@ static struct platform_device *real6410_devices[] __initdata = {
198 &s3c_device_ohci, 198 &s3c_device_ohci,
199}; 199};
200 200
201static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
202 .delay = 10000,
203 .presc = 49,
204 .oversampling_shift = 2,
205};
206
207static void __init real6410_map_io(void) 201static void __init real6410_map_io(void)
208{ 202{
209 u32 tmp; 203 u32 tmp;
@@ -300,7 +294,7 @@ static void __init real6410_machine_init(void)
300 294
301 s3c_fb_set_platdata(&real6410_lcd_pdata); 295 s3c_fb_set_platdata(&real6410_lcd_pdata);
302 s3c_nand_set_platdata(&real6410_nand_info); 296 s3c_nand_set_platdata(&real6410_nand_info);
303 s3c24xx_ts_set_platdata(&s3c_ts_platform); 297 s3c24xx_ts_set_platdata(NULL);
304 298
305 /* configure nCS1 width to 16 bits */ 299 /* configure nCS1 width to 16 bits */
306 300
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index a9f3183e0290..d831c97833ba 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -619,12 +619,6 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
619 { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */ 619 { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
620}; 620};
621 621
622static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
623 .delay = 10000,
624 .presc = 49,
625 .oversampling_shift = 2,
626};
627
628/* LCD Backlight data */ 622/* LCD Backlight data */
629static struct samsung_bl_gpio_info smdk6410_bl_gpio_info = { 623static struct samsung_bl_gpio_info smdk6410_bl_gpio_info = {
630 .no = S3C64XX_GPF(15), 624 .no = S3C64XX_GPF(15),
@@ -666,7 +660,7 @@ static void __init smdk6410_machine_init(void)
666 660
667 samsung_keypad_set_platdata(&smdk6410_keypad_data); 661 samsung_keypad_set_platdata(&smdk6410_keypad_data);
668 662
669 s3c24xx_ts_set_platdata(&s3c_ts_platform); 663 s3c24xx_ts_set_platdata(NULL);
670 664
671 /* configure nCS1 width to 16 bits */ 665 /* configure nCS1 width to 16 bits */
672 666
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 346f8dfa6f35..340f30f4a3da 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -129,12 +129,6 @@ static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = {
129 /* To be populated */ 129 /* To be populated */
130}; 130};
131 131
132static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
133 .delay = 10000,
134 .presc = 49,
135 .oversampling_shift = 2,
136};
137
138/* LCD Backlight data */ 132/* LCD Backlight data */
139static struct samsung_bl_gpio_info smdk6440_bl_gpio_info = { 133static struct samsung_bl_gpio_info smdk6440_bl_gpio_info = {
140 .no = S5P6440_GPF(15), 134 .no = S5P6440_GPF(15),
@@ -155,7 +149,7 @@ static void __init smdk6440_map_io(void)
155 149
156static void __init smdk6440_machine_init(void) 150static void __init smdk6440_machine_init(void)
157{ 151{
158 s3c24xx_ts_set_platdata(&s3c_ts_platform); 152 s3c24xx_ts_set_platdata(NULL);
159 153
160 s3c_i2c0_set_platdata(&s5p6440_i2c0_data); 154 s3c_i2c0_set_platdata(&s5p6440_i2c0_data);
161 s3c_i2c1_set_platdata(&s5p6440_i2c1_data); 155 s3c_i2c1_set_platdata(&s5p6440_i2c1_data);
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 33f2adf8f3fe..ee0da14665b6 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -148,12 +148,6 @@ static struct i2c_board_info smdk6450_i2c_devs1[] __initdata = {
148 { I2C_BOARD_INFO("24c128", 0x57), },/* Samsung S524AD0XD1 EEPROM */ 148 { I2C_BOARD_INFO("24c128", 0x57), },/* Samsung S524AD0XD1 EEPROM */
149}; 149};
150 150
151static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
152 .delay = 10000,
153 .presc = 49,
154 .oversampling_shift = 2,
155};
156
157/* LCD Backlight data */ 151/* LCD Backlight data */
158static struct samsung_bl_gpio_info smdk6450_bl_gpio_info = { 152static struct samsung_bl_gpio_info smdk6450_bl_gpio_info = {
159 .no = S5P6450_GPF(15), 153 .no = S5P6450_GPF(15),
@@ -174,7 +168,7 @@ static void __init smdk6450_map_io(void)
174 168
175static void __init smdk6450_machine_init(void) 169static void __init smdk6450_machine_init(void)
176{ 170{
177 s3c24xx_ts_set_platdata(&s3c_ts_platform); 171 s3c24xx_ts_set_platdata(NULL);
178 172
179 s3c_i2c0_set_platdata(&s5p6450_i2c0_data); 173 s3c_i2c0_set_platdata(&s5p6450_i2c0_data);
180 s3c_i2c1_set_platdata(&s5p6450_i2c1_data); 174 s3c_i2c1_set_platdata(&s5p6450_i2c1_data);
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 227d8908aab6..0b70762ebf1a 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -203,12 +203,6 @@ static struct platform_device *smdkc100_devices[] __initdata = {
203 &s5pc100_device_spdif, 203 &s5pc100_device_spdif,
204}; 204};
205 205
206static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
207 .delay = 10000,
208 .presc = 49,
209 .oversampling_shift = 2,
210};
211
212/* LCD Backlight data */ 206/* LCD Backlight data */
213static struct samsung_bl_gpio_info smdkc100_bl_gpio_info = { 207static struct samsung_bl_gpio_info smdkc100_bl_gpio_info = {
214 .no = S5PC100_GPD(0), 208 .no = S5PC100_GPD(0),
@@ -228,7 +222,7 @@ static void __init smdkc100_map_io(void)
228 222
229static void __init smdkc100_machine_init(void) 223static void __init smdkc100_machine_init(void)
230{ 224{
231 s3c24xx_ts_set_platdata(&s3c_ts_platform); 225 s3c24xx_ts_set_platdata(NULL);
232 226
233 /* I2C */ 227 /* I2C */
234 s3c_i2c0_set_platdata(NULL); 228 s3c_i2c0_set_platdata(NULL);
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 69dd87cd8e22..aaeb44a73716 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -14,7 +14,6 @@ config CPU_S5PV210
14 select S3C_PL330_DMA 14 select S3C_PL330_DMA
15 select S5P_EXT_INT 15 select S5P_EXT_INT
16 select S5P_HRT 16 select S5P_HRT
17 select S5PV210_PM if PM
18 help 17 help
19 Enable S5PV210 CPU support 18 Enable S5PV210 CPU support
20 19
@@ -169,9 +168,4 @@ config MACH_TORBRECK
169 168
170endmenu 169endmenu
171 170
172config S5PV210_PM
173 bool
174 help
175 Power Management code common to S5PV210
176
177endif 171endif
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 599a3c0e8f6c..ef7e4668d670 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -14,7 +14,7 @@ obj- :=
14 14
15obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o 15obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o
16obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o 16obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o
17obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o 17obj-$(CONFIG_PM) += pm.o sleep.o
18 18
19# machine support 19# machine support
20 20
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 52a8e607bcc2..f5f8fa89679c 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -815,8 +815,7 @@ static struct clksrc_clk clksrcs[] = {
815 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 }, 815 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
816 }, { 816 }, {
817 .clk = { 817 .clk = {
818 .name = "sclk_cam", 818 .name = "sclk_cam0",
819 .devname = "s5pv210-fimc.0",
820 .enable = s5pv210_clk_mask0_ctrl, 819 .enable = s5pv210_clk_mask0_ctrl,
821 .ctrlbit = (1 << 3), 820 .ctrlbit = (1 << 3),
822 }, 821 },
@@ -825,8 +824,7 @@ static struct clksrc_clk clksrcs[] = {
825 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 }, 824 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
826 }, { 825 }, {
827 .clk = { 826 .clk = {
828 .name = "sclk_cam", 827 .name = "sclk_cam1",
829 .devname = "s5pv210-fimc.1",
830 .enable = s5pv210_clk_mask0_ctrl, 828 .enable = s5pv210_clk_mask0_ctrl,
831 .ctrlbit = (1 << 4), 829 .ctrlbit = (1 << 4),
832 }, 830 },
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 5e011fc6720d..4b27bcaf676a 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -265,12 +265,6 @@ static struct i2c_board_info smdkv210_i2c_devs2[] __initdata = {
265 /* To Be Updated */ 265 /* To Be Updated */
266}; 266};
267 267
268static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
269 .delay = 10000,
270 .presc = 49,
271 .oversampling_shift = 2,
272};
273
274/* LCD Backlight data */ 268/* LCD Backlight data */
275static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = { 269static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = {
276 .no = S5PV210_GPD0(3), 270 .no = S5PV210_GPD0(3),
@@ -296,7 +290,7 @@ static void __init smdkv210_machine_init(void)
296 smdkv210_dm9000_init(); 290 smdkv210_dm9000_init();
297 291
298 samsung_keypad_set_platdata(&smdkv210_keypad_data); 292 samsung_keypad_set_platdata(&smdkv210_keypad_data);
299 s3c24xx_ts_set_platdata(&s3c_ts_platform); 293 s3c24xx_ts_set_platdata(NULL);
300 294
301 s3c_i2c0_set_platdata(NULL); 295 s3c_i2c0_set_platdata(NULL);
302 s3c_i2c1_set_platdata(NULL); 296 s3c_i2c1_set_platdata(NULL);
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 3b24bfa3b828..07c4bc8ea0a4 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -174,6 +174,10 @@ ENTRY(v7_coherent_user_range)
174 dcache_line_size r2, r3 174 dcache_line_size r2, r3
175 sub r3, r2, #1 175 sub r3, r2, #1
176 bic r12, r0, r3 176 bic r12, r0, r3
177#ifdef CONFIG_ARM_ERRATA_764369
178 ALT_SMP(W(dsb))
179 ALT_UP(W(nop))
180#endif
1771: 1811:
178 USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification 182 USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification
179 add r12, r12, r2 183 add r12, r12, r2
@@ -223,6 +227,10 @@ ENTRY(v7_flush_kern_dcache_area)
223 add r1, r0, r1 227 add r1, r0, r1
224 sub r3, r2, #1 228 sub r3, r2, #1
225 bic r0, r0, r3 229 bic r0, r0, r3
230#ifdef CONFIG_ARM_ERRATA_764369
231 ALT_SMP(W(dsb))
232 ALT_UP(W(nop))
233#endif
2261: 2341:
227 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 235 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
228 add r0, r0, r2 236 add r0, r0, r2
@@ -247,6 +255,10 @@ v7_dma_inv_range:
247 sub r3, r2, #1 255 sub r3, r2, #1
248 tst r0, r3 256 tst r0, r3
249 bic r0, r0, r3 257 bic r0, r0, r3
258#ifdef CONFIG_ARM_ERRATA_764369
259 ALT_SMP(W(dsb))
260 ALT_UP(W(nop))
261#endif
250 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 262 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
251 263
252 tst r1, r3 264 tst r1, r3
@@ -270,6 +282,10 @@ v7_dma_clean_range:
270 dcache_line_size r2, r3 282 dcache_line_size r2, r3
271 sub r3, r2, #1 283 sub r3, r2, #1
272 bic r0, r0, r3 284 bic r0, r0, r3
285#ifdef CONFIG_ARM_ERRATA_764369
286 ALT_SMP(W(dsb))
287 ALT_UP(W(nop))
288#endif
2731: 2891:
274 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line 290 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
275 add r0, r0, r2 291 add r0, r0, r2
@@ -288,6 +304,10 @@ ENTRY(v7_dma_flush_range)
288 dcache_line_size r2, r3 304 dcache_line_size r2, r3
289 sub r3, r2, #1 305 sub r3, r2, #1
290 bic r0, r0, r3 306 bic r0, r0, r3
307#ifdef CONFIG_ARM_ERRATA_764369
308 ALT_SMP(W(dsb))
309 ALT_UP(W(nop))
310#endif
2911: 3111:
292 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 312 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
293 add r0, r0, r2 313 add r0, r0, r2
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 0a0a1e7c20d2..c3ff82f92d9c 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -324,6 +324,8 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
324 324
325 if (addr) 325 if (addr)
326 *handle = pfn_to_dma(dev, page_to_pfn(page)); 326 *handle = pfn_to_dma(dev, page_to_pfn(page));
327 else
328 __dma_free_buffer(page, size);
327 329
328 return addr; 330 return addr;
329} 331}
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h
deleted file mode 100644
index bd534d32b993..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/map.h
+++ /dev/null
@@ -1,100 +0,0 @@
1/* linux/include/asm-arm/plat-s3c24xx/map.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_S3C24XX_MAP_H
14#define __ASM_PLAT_S3C24XX_MAP_H
15
16/* interrupt controller is the first thing we put in, to make
17 * the assembly code for the irq detection easier
18 */
19#define S3C24XX_VA_IRQ S3C_VA_IRQ
20#define S3C2410_PA_IRQ (0x4A000000)
21#define S3C24XX_SZ_IRQ SZ_1M
22
23/* memory controller registers */
24#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
25#define S3C2410_PA_MEMCTRL (0x48000000)
26#define S3C24XX_SZ_MEMCTRL SZ_1M
27
28/* UARTs */
29#define S3C24XX_VA_UART S3C_VA_UART
30#define S3C2410_PA_UART (0x50000000)
31#define S3C24XX_SZ_UART SZ_1M
32#define S3C_UART_OFFSET (0x4000)
33
34#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
35
36/* Timers */
37#define S3C24XX_VA_TIMER S3C_VA_TIMER
38#define S3C2410_PA_TIMER (0x51000000)
39#define S3C24XX_SZ_TIMER SZ_1M
40
41/* Clock and Power management */
42#define S3C24XX_VA_CLKPWR S3C_VA_SYS
43#define S3C24XX_SZ_CLKPWR SZ_1M
44
45/* USB Device port */
46#define S3C2410_PA_USBDEV (0x52000000)
47#define S3C24XX_SZ_USBDEV SZ_1M
48
49/* Watchdog */
50#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
51#define S3C2410_PA_WATCHDOG (0x53000000)
52#define S3C24XX_SZ_WATCHDOG SZ_1M
53
54/* Standard size definitions for peripheral blocks. */
55
56#define S3C24XX_SZ_IIS SZ_1M
57#define S3C24XX_SZ_ADC SZ_1M
58#define S3C24XX_SZ_SPI SZ_1M
59#define S3C24XX_SZ_SDI SZ_1M
60#define S3C24XX_SZ_NAND SZ_1M
61
62/* GPIO ports */
63
64/* the calculation for the VA of this must ensure that
65 * it is the same distance apart from the UART in the
66 * phsyical address space, as the initial mapping for the IO
67 * is done as a 1:1 mapping. This puts it (currently) at
68 * 0xFA800000, which is not in the way of any current mapping
69 * by the base system.
70*/
71
72#define S3C2410_PA_GPIO (0x56000000)
73#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
74#define S3C24XX_SZ_GPIO SZ_1M
75
76
77/* ISA style IO, for each machine to sort out mappings for, if it
78 * implements it. We reserve two 16M regions for ISA.
79 */
80
81#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
82#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
83
84/* deal with the registers that move under the 2412/2413 */
85
86#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
87#ifndef __ASSEMBLY__
88extern void __iomem *s3c24xx_va_gpio2;
89#endif
90#ifdef CONFIG_CPU_S3C2412_ONLY
91#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
92#else
93#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
94#endif
95#else
96#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
97#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
98#endif
99
100#endif /* __ASM_PLAT_S3C24XX_MAP_H */
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h
index 1bfd61a4c8de..3e21b9444cc5 100644
--- a/arch/arm/plat-s5p/include/plat/pll.h
+++ b/arch/arm/plat-s5p/include/plat/pll.h
@@ -123,7 +123,6 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
123 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; 123 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
124 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; 124 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
125 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; 125 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
126 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
127 126
128 if (pll_type == pll_4650c) 127 if (pll_type == pll_4650c)
129 kdiv = pll_con1 & PLL4650C_KDIV_MASK; 128 kdiv = pll_con1 & PLL4650C_KDIV_MASK;
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index f71078ef6bb5..f88216d23991 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -114,17 +114,18 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
114{ 114{
115 static int used_gpioint_groups = 0; 115 static int used_gpioint_groups = 0;
116 int group = chip->group; 116 int group = chip->group;
117 struct s5p_gpioint_bank *bank = NULL; 117 struct s5p_gpioint_bank *b, *bank = NULL;
118 struct irq_chip_generic *gc; 118 struct irq_chip_generic *gc;
119 struct irq_chip_type *ct; 119 struct irq_chip_type *ct;
120 120
121 if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT) 121 if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
122 return -ENOMEM; 122 return -ENOMEM;
123 123
124 list_for_each_entry(bank, &banks, list) { 124 list_for_each_entry(b, &banks, list) {
125 if (group >= bank->start && 125 if (group >= b->start && group < b->start + b->nr_groups) {
126 group < bank->start + bank->nr_groups) 126 bank = b;
127 break; 127 break;
128 }
128 } 129 }
129 if (!bank) 130 if (!bank)
130 return -EINVAL; 131 return -EINVAL;
diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c
index db7a65c7f127..06825c4276de 100644
--- a/arch/arm/plat-samsung/dev-hsmmc.c
+++ b/arch/arm/plat-samsung/dev-hsmmc.c
@@ -58,22 +58,5 @@ struct platform_device s3c_device_hsmmc0 = {
58 58
59void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd) 59void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
60{ 60{
61 struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata; 61 s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
62
63 set->cd_type = pd->cd_type;
64 set->ext_cd_init = pd->ext_cd_init;
65 set->ext_cd_cleanup = pd->ext_cd_cleanup;
66 set->ext_cd_gpio = pd->ext_cd_gpio;
67 set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
68
69 if (pd->max_width)
70 set->max_width = pd->max_width;
71 if (pd->cfg_gpio)
72 set->cfg_gpio = pd->cfg_gpio;
73 if (pd->cfg_card)
74 set->cfg_card = pd->cfg_card;
75 if (pd->host_caps)
76 set->host_caps |= pd->host_caps;
77 if (pd->clk_type)
78 set->clk_type = pd->clk_type;
79} 62}
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c
index 2497321f08d7..4524ef440010 100644
--- a/arch/arm/plat-samsung/dev-hsmmc1.c
+++ b/arch/arm/plat-samsung/dev-hsmmc1.c
@@ -58,22 +58,5 @@ struct platform_device s3c_device_hsmmc1 = {
58 58
59void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd) 59void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
60{ 60{
61 struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata; 61 s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
62
63 set->cd_type = pd->cd_type;
64 set->ext_cd_init = pd->ext_cd_init;
65 set->ext_cd_cleanup = pd->ext_cd_cleanup;
66 set->ext_cd_gpio = pd->ext_cd_gpio;
67 set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
68
69 if (pd->max_width)
70 set->max_width = pd->max_width;
71 if (pd->cfg_gpio)
72 set->cfg_gpio = pd->cfg_gpio;
73 if (pd->cfg_card)
74 set->cfg_card = pd->cfg_card;
75 if (pd->host_caps)
76 set->host_caps |= pd->host_caps;
77 if (pd->clk_type)
78 set->clk_type = pd->clk_type;
79} 62}
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c
index f60aedba417c..9cede9615e48 100644
--- a/arch/arm/plat-samsung/dev-hsmmc2.c
+++ b/arch/arm/plat-samsung/dev-hsmmc2.c
@@ -59,22 +59,5 @@ struct platform_device s3c_device_hsmmc2 = {
59 59
60void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd) 60void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
61{ 61{
62 struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata; 62 s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
63
64 set->cd_type = pd->cd_type;
65 set->ext_cd_init = pd->ext_cd_init;
66 set->ext_cd_cleanup = pd->ext_cd_cleanup;
67 set->ext_cd_gpio = pd->ext_cd_gpio;
68 set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
69
70 if (pd->max_width)
71 set->max_width = pd->max_width;
72 if (pd->cfg_gpio)
73 set->cfg_gpio = pd->cfg_gpio;
74 if (pd->cfg_card)
75 set->cfg_card = pd->cfg_card;
76 if (pd->host_caps)
77 set->host_caps |= pd->host_caps;
78 if (pd->clk_type)
79 set->clk_type = pd->clk_type;
80} 63}
diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c
index ede776f20e62..0358ef4a8f66 100644
--- a/arch/arm/plat-samsung/dev-hsmmc3.c
+++ b/arch/arm/plat-samsung/dev-hsmmc3.c
@@ -62,22 +62,5 @@ struct platform_device s3c_device_hsmmc3 = {
62 62
63void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd) 63void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
64{ 64{
65 struct s3c_sdhci_platdata *set = &s3c_hsmmc3_def_platdata; 65 s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
66
67 set->cd_type = pd->cd_type;
68 set->ext_cd_init = pd->ext_cd_init;
69 set->ext_cd_cleanup = pd->ext_cd_cleanup;
70 set->ext_cd_gpio = pd->ext_cd_gpio;
71 set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
72
73 if (pd->max_width)
74 set->max_width = pd->max_width;
75 if (pd->cfg_gpio)
76 set->cfg_gpio = pd->cfg_gpio;
77 if (pd->cfg_card)
78 set->cfg_card = pd->cfg_card;
79 if (pd->host_caps)
80 set->host_caps |= pd->host_caps;
81 if (pd->clk_type)
82 set->clk_type = pd->clk_type;
83} 66}
diff --git a/arch/arm/plat-samsung/dev-ts.c b/arch/arm/plat-samsung/dev-ts.c
index 82543f0248ac..5f3d46a9bd88 100644
--- a/arch/arm/plat-samsung/dev-ts.c
+++ b/arch/arm/plat-samsung/dev-ts.c
@@ -43,8 +43,17 @@ struct platform_device s3c_device_ts = {
43 .resource = s3c_ts_resource, 43 .resource = s3c_ts_resource,
44}; 44};
45 45
46static struct s3c2410_ts_mach_info default_ts_data __initdata = {
47 .delay = 10000,
48 .presc = 49,
49 .oversampling_shift = 2,
50};
51
46void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd) 52void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
47{ 53{
54 if (!pd)
55 pd = &default_ts_data;
56
48 s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info), 57 s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
49 &s3c_device_ts); 58 &s3c_device_ts);
50} 59}
diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
index 336d5ac02035..ab9bce637cbd 100644
--- a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
+++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
@@ -18,11 +18,6 @@ extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
18#define DMA_CH_VALID (1<<31) 18#define DMA_CH_VALID (1<<31)
19#define DMA_CH_NEVER (1<<30) 19#define DMA_CH_NEVER (1<<30)
20 20
21struct s3c24xx_dma_addr {
22 unsigned long from;
23 unsigned long to;
24};
25
26/* struct s3c24xx_dma_map 21/* struct s3c24xx_dma_map
27 * 22 *
28 * this holds the mapping information for the channel selected 23 * this holds the mapping information for the channel selected
@@ -31,7 +26,6 @@ struct s3c24xx_dma_addr {
31 26
32struct s3c24xx_dma_map { 27struct s3c24xx_dma_map {
33 const char *name; 28 const char *name;
34 struct s3c24xx_dma_addr hw_addr;
35 29
36 unsigned long channels[S3C_DMA_CHANNELS]; 30 unsigned long channels[S3C_DMA_CHANNELS];
37 unsigned long channels_rx[S3C_DMA_CHANNELS]; 31 unsigned long channels_rx[S3C_DMA_CHANNELS];
diff --git a/arch/arm/plat-samsung/include/plat/map-s3c.h b/arch/arm/plat-samsung/include/plat/map-s3c.h
new file mode 100644
index 000000000000..7d048759b772
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/map-s3c.h
@@ -0,0 +1,84 @@
1/* linux/arch/arm/plat-samsung/include/plat/map-s3c.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_MAP_S3C_H
14#define __ASM_PLAT_MAP_S3C_H __FILE__
15
16#define S3C24XX_VA_IRQ S3C_VA_IRQ
17#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
18#define S3C24XX_VA_UART S3C_VA_UART
19
20#define S3C24XX_VA_TIMER S3C_VA_TIMER
21#define S3C24XX_VA_CLKPWR S3C_VA_SYS
22#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
23
24#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
25#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000)
26
27#define S3C2410_PA_UART (0x50000000)
28#define S3C24XX_PA_UART S3C2410_PA_UART
29
30#ifndef S3C_UART_OFFSET
31#define S3C_UART_OFFSET (0x400)
32#endif
33
34/*
35 * GPIO ports
36 *
37 * the calculation for the VA of this must ensure that
38 * it is the same distance apart from the UART in the
39 * phsyical address space, as the initial mapping for the IO
40 * is done as a 1:1 mapping. This puts it (currently) at
41 * 0xFA800000, which is not in the way of any current mapping
42 * by the base system.
43*/
44
45#define S3C2410_PA_GPIO (0x56000000)
46#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
47
48#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
49#define S3C64XX_VA_GPIO S3C_ADDR_CPU(0x00000000)
50
51#define S3C64XX_VA_MODEM S3C_ADDR_CPU(0x00100000)
52#define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000)
53
54#define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY
55
56/*
57 * ISA style IO, for each machine to sort out mappings for,
58 * if it implements it. We reserve two 16M regions for ISA.
59 */
60
61#define S3C2410_ADDR(x) S3C_ADDR(x)
62
63#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
64#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
65
66/* deal with the registers that move under the 2412/2413 */
67
68#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
69#ifndef __ASSEMBLY__
70extern void __iomem *s3c24xx_va_gpio2;
71#endif
72#ifdef CONFIG_CPU_S3C2412_ONLY
73#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
74#else
75#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
76#endif
77#else
78#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
79#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
80#endif
81
82#include <plat/map-s5p.h>
83
84#endif /* __ASM_PLAT_MAP_S3C_H */
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index 36d3551173b2..c2d7bdae5891 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -1,4 +1,4 @@
1/* linux/arch/arm/plat-s5p/include/plat/map-s5p.h 1/* linux/arch/arm/plat-samsung/include/plat/map-s5p.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com/
@@ -40,8 +40,6 @@
40#define S5P_VA_GIC_CPU S3C_ADDR(0x02810000) 40#define S5P_VA_GIC_CPU S3C_ADDR(0x02810000)
41#define S5P_VA_GIC_DIST S3C_ADDR(0x02820000) 41#define S5P_VA_GIC_DIST S3C_ADDR(0x02820000)
42 42
43#define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000)
44
45#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000)) 43#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
46#define VA_VIC0 VA_VIC(0) 44#define VA_VIC0 VA_VIC(0)
47#define VA_VIC1 VA_VIC(1) 45#define VA_VIC1 VA_VIC(1)
@@ -58,4 +56,6 @@
58#define S3C_UART_OFFSET (0x400) 56#define S3C_UART_OFFSET (0x400)
59#endif 57#endif
60 58
59#include <plat/map-s3c.h>
60
61#endif /* __ASM_PLAT_MAP_S5P_H */ 61#endif /* __ASM_PLAT_MAP_S5P_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 058e09654fe8..4a6552066c7e 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -86,6 +86,13 @@ struct s3c_sdhci_platdata {
86 struct mmc_card *card); 86 struct mmc_card *card);
87}; 87};
88 88
89/* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data
90 * @pd: The default platform data for this device.
91 * @set: Pointer to the platform data to fill in.
92 */
93extern void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd,
94 struct s3c_sdhci_platdata *set);
95
89/** 96/**
90 * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device. 97 * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device.
91 * @pd: Platform data to register to device. 98 * @pd: Platform data to register to device.
diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/plat-samsung/platformdata.c
index 7cf2e1e3b20f..6de1a3825927 100644
--- a/arch/arm/plat-samsung/platformdata.c
+++ b/arch/arm/plat-samsung/platformdata.c
@@ -14,6 +14,7 @@
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15 15
16#include <plat/devs.h> 16#include <plat/devs.h>
17#include <plat/sdhci.h>
17 18
18void __init *s3c_set_platdata(void *pd, size_t pdsize, 19void __init *s3c_set_platdata(void *pd, size_t pdsize,
19 struct platform_device *pdev) 20 struct platform_device *pdev)
@@ -35,3 +36,24 @@ void __init *s3c_set_platdata(void *pd, size_t pdsize,
35 pdev->dev.platform_data = npd; 36 pdev->dev.platform_data = npd;
36 return npd; 37 return npd;
37} 38}
39
40void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd,
41 struct s3c_sdhci_platdata *set)
42{
43 set->cd_type = pd->cd_type;
44 set->ext_cd_init = pd->ext_cd_init;
45 set->ext_cd_cleanup = pd->ext_cd_cleanup;
46 set->ext_cd_gpio = pd->ext_cd_gpio;
47 set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
48
49 if (pd->max_width)
50 set->max_width = pd->max_width;
51 if (pd->cfg_gpio)
52 set->cfg_gpio = pd->cfg_gpio;
53 if (pd->cfg_card)
54 set->cfg_card = pd->cfg_card;
55 if (pd->host_caps)
56 set->host_caps |= pd->host_caps;
57 if (pd->clk_type)
58 set->clk_type = pd->clk_type;
59}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-24 04:58:47 -0500