284 files changed, 3191 insertions, 5127 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 87b63fde06d7..245058b3b0ef 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -175,13 +175,6 @@ config ARCH_HAS_ILOG2_U32
 config ARCH_HAS_ILOG2_U64
         bool
 
-config ARCH_HAS_CPUFREQ
-        bool
-        help
-          Internal node to signify that the ARCH has CPUFREQ support
-          and that the relevant menu configurations are displayed for
-          it.
-
 config ARCH_HAS_BANDGAP
         bool
 
@@ -318,7 +311,6 @@ config ARCH_MULTIPLATFORM
 
 config ARCH_INTEGRATOR
         bool "ARM Ltd. Integrator family"
-        select ARCH_HAS_CPUFREQ
         select ARM_AMBA
         select ARM_PATCH_PHYS_VIRT
         select AUTO_ZRELADDR
@@ -538,7 +530,6 @@ config ARCH_DOVE
 
 config ARCH_KIRKWOOD
         bool "Marvell Kirkwood"
-        select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
         select CPU_FEROCEON
         select GENERIC_CLOCKEVENTS
@@ -637,7 +628,6 @@ config ARCH_LPC32XX
 config ARCH_PXA
         bool "PXA2xx/PXA3xx-based"
         depends on MMU
-        select ARCH_HAS_CPUFREQ
         select ARCH_MTD_XIP
         select ARCH_REQUIRE_GPIOLIB
         select ARM_CPU_SUSPEND if PM
@@ -707,7 +697,6 @@ config ARCH_RPC
 
 config ARCH_SA1100
         bool "SA1100-based"
-        select ARCH_HAS_CPUFREQ
         select ARCH_MTD_XIP
         select ARCH_REQUIRE_GPIOLIB
         select ARCH_SPARSEMEM_ENABLE
@@ -725,7 +714,6 @@ config ARCH_SA1100
 
 config ARCH_S3C24XX
         bool "Samsung S3C24XX SoCs"
-        select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
         select ATAGS
         select CLKDEV_LOOKUP
@@ -746,7 +734,6 @@ config ARCH_S3C24XX
 
 config ARCH_S3C64XX
         bool "Samsung S3C64XX"
-        select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
         select ARM_AMBA
         select ARM_VIC
@@ -809,7 +796,6 @@ config ARCH_S5PC100
 
 config ARCH_S5PV210
         bool "Samsung S5PV210/S5PC110"
-        select ARCH_HAS_CPUFREQ
         select ARCH_HAS_HOLES_MEMORYMODEL
         select ARCH_SPARSEMEM_ENABLE
         select ATAGS
@@ -845,7 +831,6 @@ config ARCH_DAVINCI
 config ARCH_OMAP1
         bool "TI OMAP1"
         depends on MMU
-        select ARCH_HAS_CPUFREQ
         select ARCH_HAS_HOLES_MEMORYMODEL
         select ARCH_OMAP
         select ARCH_REQUIRE_GPIOLIB
@@ -1009,8 +994,6 @@ source "arch/arm/mach-rockchip/Kconfig"
 
 source "arch/arm/mach-sa1100/Kconfig"
 
-source "arch/arm/plat-samsung/Kconfig"
-
 source "arch/arm/mach-socfpga/Kconfig"
 
 source "arch/arm/mach-spear/Kconfig"
@@ -1028,6 +1011,7 @@ source "arch/arm/mach-s5pc100/Kconfig"
 source "arch/arm/mach-s5pv210/Kconfig"
 
 source "arch/arm/mach-exynos/Kconfig"
+source "arch/arm/plat-samsung/Kconfig"
 
 source "arch/arm/mach-shmobile/Kconfig"
 
@@ -2109,9 +2093,7 @@ endmenu
 
 menu "CPU Power Management"
 
-if ARCH_HAS_CPUFREQ
 source "drivers/cpufreq/Kconfig"
-endif
 
 source "drivers/cpuidle/Kconfig"
 
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5986ff63b901..eb280d3483eb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -327,7 +327,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
         r8a7778-bockw-reference.dtb \
         r8a7740-armadillo800eva-reference.dtb \
         r8a7779-marzen.dtb \
-        r8a7779-marzen-reference.dtb \
         r8a7791-koelsch.dtb \
         r8a7790-lager.dtb \
         sh73a0-kzm9g.dtb \
@@ -339,7 +338,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
         r7s72100-genmai.dtb \
         r8a7791-henninger.dtb \
         r8a7791-koelsch.dtb \
-        r8a7790-lager.dtb
+        r8a7790-lager.dtb \
+        r8a7779-marzen.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
         socfpga_cyclone5_socdk.dtb \
         socfpga_cyclone5_sockit.dtb \
@@ -357,7 +357,7 @@ dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
         stih415-b2020.dtb \
         stih416-b2000.dtb \
         stih416-b2020.dtb \
-        stih416-b2020-revE.dtb
+        stih416-b2020e.dtb
 dtb-$(CONFIG_MACH_SUN4I) += \
         sun4i-a10-a1000.dtb \
         sun4i-a10-cubieboard.dtb \
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
index 772fec2d26ce..1e2919d43d78 100644
--- a/arch/arm/boot/dts/armada-375-db.dts
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -91,6 +91,8 @@
                                 marvell,nand-keep-config;
                                 marvell,nand-enable-arbiter;
                                 nand-on-flash-bbt;
+                                nand-ecc-strength = <4>;
+                                nand-ecc-step-size = <512>;
 
                                 partition@0 {
                                         label = "U-Boot";
diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
index e69bc6759c39..4173a8ab34e7 100644
--- a/arch/arm/boot/dts/armada-380.dtsi
+++ b/arch/arm/boot/dts/armada-380.dtsi
@@ -16,7 +16,7 @@
 
 / {
         model = "Marvell Armada 380 family SoC";
-        compatible = "marvell,armada380", "marvell,armada38x";
+        compatible = "marvell,armada380";
 
         cpus {
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts
index ff9637dd8d0f..1af886f1e486 100644
--- a/arch/arm/boot/dts/armada-385-db.dts
+++ b/arch/arm/boot/dts/armada-385-db.dts
@@ -16,7 +16,7 @@
 
 / {
         model = "Marvell Armada 385 Development Board";
-        compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada38x";
+        compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada380";
 
         chosen {
                 bootargs = "console=ttyS0,115200 earlyprintk";
@@ -98,6 +98,8 @@
                                 marvell,nand-keep-config;
                                 marvell,nand-enable-arbiter;
                                 nand-on-flash-bbt;
+                                nand-ecc-strength = <4>;
+                                nand-ecc-step-size = <512>;
 
                                 partition@0 {
                                         label = "U-Boot";
diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-385-rd.dts
index 40893255a3f0..aaca2861dc87 100644
--- a/arch/arm/boot/dts/armada-385-rd.dts
+++ b/arch/arm/boot/dts/armada-385-rd.dts
@@ -17,7 +17,7 @@
 
 / {
         model = "Marvell Armada 385 Reference Design";
-        compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada38x";
+        compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380";
 
         chosen {
                 bootargs = "console=ttyS0,115200 earlyprintk";
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
index f011009bf4cf..6283d7912f71 100644
--- a/arch/arm/boot/dts/armada-385.dtsi
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -16,7 +16,7 @@
 
 / {
         model = "Marvell Armada 385 family SoC";
-        compatible = "marvell,armada385", "marvell,armada38x";
+        compatible = "marvell,armada385", "marvell,armada380";
 
         cpus {
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 3de364e81b52..689fa1a46728 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -20,7 +20,7 @@
 
 / {
         model = "Marvell Armada 38x family SoC";
-        compatible = "marvell,armada38x";
+        compatible = "marvell,armada380";
 
         aliases {
                 gpio0 = &gpio0;
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index e5c6a0492ca0..4e5a59ee1501 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -25,7 +25,7 @@
 
         memory {
                 device_type = "memory";
-                reg = <0 0x00000000 0 0xC0000000>; /* 3 GB */
+                reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */
         };
 
         soc {
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index b309c1c6e848..04927db1d6bf 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -568,24 +568,17 @@
                                 #size-cells = <0>;
                                 #interrupt-cells = <1>;
 
-                                slow_rc_osc: slow_rc_osc {
-                                        compatible = "fixed-clock";
+                                main_osc: main_osc {
+                                        compatible = "atmel,at91rm9200-clk-main-osc";
                                         #clock-cells = <0>;
-                                        clock-frequency = <32768>;
-                                        clock-accuracy = <50000000>;
-                                };
-
-                                clk32k: slck {
-                                        compatible = "atmel,at91sam9260-clk-slow";
-                                        #clock-cells = <0>;
-                                        clocks = <&slow_rc_osc &slow_xtal>;
+                                        interrupts-extended = <&pmc AT91_PMC_MOSCS>;
+                                        clocks = <&main_xtal>;
                                 };
 
                                 main: mainck {
                                         compatible = "atmel,at91rm9200-clk-main";
                                         #clock-cells = <0>;
-                                        interrupts-extended = <&pmc AT91_PMC_MOSCS>;
-                                        clocks = <&main_xtal>;
+                                        clocks = <&main_osc>;
                                 };
 
                                 plla: pllack {
@@ -615,7 +608,7 @@
                                         compatible = "atmel,at91rm9200-clk-master";
                                         #clock-cells = <0>;
                                         interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
-                                        clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+                                        clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
                                         atmel,clk-output-range = <0 94000000>;
                                         atmel,clk-divisors = <1 2 4 0>;
                                 };
@@ -632,7 +625,7 @@
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         interrupt-parent = <&pmc>;
-                                        clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+                                        clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
 
                                         prog0: prog0 {
                                                 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts
index c6683ea8b743..aa35a7aec9a8 100644
--- a/arch/arm/boot/dts/at91sam9261ek.dts
+++ b/arch/arm/boot/dts/at91sam9261ek.dts
@@ -20,6 +20,10 @@
                 reg = <0x20000000 0x4000000>;
         };
 
+        slow_xtal {
+                clock-frequency = <32768>;
+        };
+
         main_xtal {
                 clock-frequency = <18432000>;
         };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index d1b82e6635d5..287795985e32 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -132,8 +132,8 @@
                                                                       <595000000 650000000 3 0>,
                                                                       <545000000 600000000 0 1>,
                                                                       <495000000 555000000 1 1>,
-                                                                      <445000000 500000000 1 2>,
-                                                                      <400000000 450000000 1 3>;
+                                                                      <445000000 500000000 2 1>,
+                                                                      <400000000 450000000 3 1>;
                                 };
 
                                 plladiv: plladivck {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 1a57298636a5..d6133f497207 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -140,8 +140,8 @@
                                                                        595000000 650000000 3 0
                                                                        545000000 600000000 0 1
                                                                        495000000 555000000 1 1
-                                                                       445000000 500000000 1 2
-                                                                       400000000 450000000 1 3>;
+                                                                       445000000 500000000 2 1
+                                                                       400000000 450000000 3 1>;
                                 };
 
                                 plladiv: plladivck {
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index e37985fa10e2..00eeed3721b6 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -31,11 +31,13 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <0>;
+                        clock-frequency = <533000000>;
                 };
                 cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <1>;
+                        clock-frequency = <533000000>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index b8ece4be41ca..fbaf426d2daa 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -113,7 +113,7 @@
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
                 interrupt-controller;
-                reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+                reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
         };
 
         combiner: interrupt-controller@10440000 {
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 6bc3243a80d3..181d77fa2fa6 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -315,15 +315,15 @@
 &esdhc1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_esdhc1>;
-        fsl,cd-controller;
-        fsl,wp-controller;
+        cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+        wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
         status = "okay";
 };
 
 &esdhc2 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_esdhc2>;
-        cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+        cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
         wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
         status = "okay";
 };
@@ -468,8 +468,8 @@
                                 MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
                                 MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
                                 MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
-                                MX51_PAD_GPIO1_0__SD1_CD                0x20d5
-                                MX51_PAD_GPIO1_1__SD1_WP                0x20d5
+                                MX51_PAD_GPIO1_0__GPIO1_0               0x100
+                                MX51_PAD_GPIO1_1__GPIO1_1               0x100
                         >;
                 };
 
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
index 75e66c9c6144..31cfb7f2b02e 100644
--- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
+++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
@@ -107,7 +107,7 @@
 &esdhc1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_esdhc1 &pinctrl_esdhc1_cd>;
-        fsl,cd-controller;
+        cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
         status = "okay";
 };
 
@@ -206,7 +206,7 @@
 
                 pinctrl_esdhc1_cd: esdhc1_cd {
                         fsl,pins = <
-                                MX51_PAD_GPIO1_0__SD1_CD 0x20d5
+                                MX51_PAD_GPIO1_0__GPIO1_0 0xd5
                         >;
                 };
 
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index d5d146a8b149..c4956b0ffb35 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -21,27 +21,25 @@
                       <0xb0000000 0x20000000>;
         };
 
-        soc {
-                display1: display@di1 {
-                        compatible = "fsl,imx-parallel-display";
-                        interface-pix-fmt = "bgr666";
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_ipu_disp1>;
-
-                        display-timings {
-                                800x480p60 {
-                                        native-mode;
-                                        clock-frequency = <31500000>;
-                                        hactive = <800>;
-                                        vactive = <480>;
-                                        hfront-porch = <40>;
-                                        hback-porch = <88>;
-                                        hsync-len = <128>;
-                                        vback-porch = <33>;
-                                        vfront-porch = <9>;
-                                        vsync-len = <3>;
-                                        vsync-active = <1>;
-                                };
+        display1: display@di1 {
+                compatible = "fsl,imx-parallel-display";
+                interface-pix-fmt = "bgr666";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_ipu_disp1>;
+
+                display-timings {
+                        800x480p60 {
+                                native-mode;
+                                clock-frequency = <31500000>;
+                                hactive = <800>;
+                                vactive = <480>;
+                                hfront-porch = <40>;
+                                hback-porch = <88>;
+                                hsync-len = <128>;
+                                vback-porch = <33>;
+                                vfront-porch = <9>;
+                                vsync-len = <3>;
+                                vsync-active = <1>;
                         };
                 };
 
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
index 5373a5f2782b..c8e51dd41b8f 100644
--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -143,6 +143,14 @@
                         fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
                 };
 
+                pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
+                        /*
+                         * Similar to pinctrl_usbotg_2, but we want it
+                         * pulled down for a fixed host connection.
+                         */
+                        fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
+                };
+
                 pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
                         fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
                 };
@@ -178,6 +186,8 @@
 };
 
 &usbotg {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
         vbus-supply = <&reg_usbotg_vbus>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6q-gw51xx.dts b/arch/arm/boot/dts/imx6q-gw51xx.dts
index af4929aee075..0e1406e58eff 100644
--- a/arch/arm/boot/dts/imx6q-gw51xx.dts
+++ b/arch/arm/boot/dts/imx6q-gw51xx.dts
@@ -11,7 +11,7 @@
 
 /dts-v1/;
 #include "imx6q.dtsi"
-#include "imx6qdl-gw54xx.dtsi"
+#include "imx6qdl-gw51xx.dtsi"
 
 / {
         model = "Gateworks Ventana i.MX6 Quad GW51XX";
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index 25da82a03110..e8e781656b3f 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -12,6 +12,19 @@
                 pinctrl-0 = <&pinctrl_cubox_i_ir>;
         };
 
+        pwmleds {
+                compatible = "pwm-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_cubox_i_pwm1>;
+
+                front {
+                        active-low;
+                        label = "imx6:red:front";
+                        max-brightness = <248>;
+                        pwms = <&pwm1 0 50000>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
 
@@ -109,6 +122,10 @@
                         >;
                 };
 
+                pinctrl_cubox_i_pwm1: cubox-i-pwm1-front-led {
+                        fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0>;
+                };
+
                 pinctrl_cubox_i_spdif: cubox-i-spdif {
                         fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
                 };
@@ -117,6 +134,14 @@
                         fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>;
                 };
 
+                pinctrl_cubox_i_usbotg_id: cubox-i-usbotg-id {
+                        /*
+                         * The Cubox-i pulls this low, but as it's pointless
+                         * leaving it as a pull-up, even if it is just 10uA.
+                         */
+                        fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
+                };
+
                 pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus {
                         fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x4001b0b0>;
                 };
@@ -153,6 +178,8 @@
 };
 
 &usbotg {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_cubox_i_usbotg_id>;
         vbus-supply = <&reg_usbotg_vbus>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index 31665adcbf39..0db15af41cb1 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -161,7 +161,7 @@
         status = "okay";
 
         pmic: ltc3676@3c {
-                compatible = "ltc,ltc3676";
+                compatible = "lltc,ltc3676";
                 reg = <0x3c>;
 
                 regulators {
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 367af3ec9435..744c8a2d81f6 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -220,7 +220,7 @@
         };
 
         pmic: ltc3676@3c {
-                compatible = "ltc,ltc3676";
+                compatible = "lltc,ltc3676";
                 reg = <0x3c>;
 
                 regulators {
@@ -288,7 +288,7 @@
         codec: sgtl5000@0a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
-                clocks = <&clks 169>;
+                clocks = <&clks 201>;
                 VDDA-supply = <&reg_1p8v>;
                 VDDIO-supply = <&reg_3p3v>;
         };
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index c91b5a6c769b..adf150c1be90 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -234,7 +234,7 @@
         };
 
         pmic: ltc3676@3c {
-                compatible = "ltc,ltc3676";
+                compatible = "lltc,ltc3676";
                 reg = <0x3c>;
 
                 regulators {
diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
index d729d0b15f25..79eac6849d4c 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
@@ -10,14 +10,6 @@
                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
                         >;
                 };
-
-                pinctrl_microsom_usbotg: microsom-usbotg {
-                        /*
-                         * Similar to pinctrl_usbotg_2, but we want it
-                         * pulled down for a fixed host connection.
-                         */
-                        fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
-                };
         };
 };
 
@@ -26,8 +18,3 @@
         pinctrl-0 = <&pinctrl_microsom_uart1>;
         status = "okay";
 };
-
-&usbotg {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_microsom_usbotg>;
-};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 2d4e5285f3f3..57d4abe03a94 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -686,7 +686,7 @@
                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
                                 reg = <0x02188000 0x4000>;
                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX6SL_CLK_ENET_REF>,
+                                clocks = <&clks IMX6SL_CLK_ENET>,
                                          <&clks IMX6SL_CLK_ENET_REF>;
                                 clock-names = "ipg", "ahb";
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index c5a1fc75c7a3..b2d9834bf458 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -105,7 +105,6 @@
                 compatible = "ethernet-phy-id0141.0cb0",
                              "ethernet-phy-ieee802.3-c22";
                 reg = <0>;
-                phy-connection-type = "rgmii-id";
         };
 
         ethphy1: ethernet-phy@1 {
@@ -113,7 +112,6 @@
                 compatible = "ethernet-phy-id0141.0cb0",
                              "ethernet-phy-ieee802.3-c22";
                 reg = <1>;
-                phy-connection-type = "rgmii-id";
         };
 };
 
@@ -121,6 +119,7 @@
         status = "okay";
         ethernet0-port@0 {
                 phy-handle = <&ethphy0>;
+                phy-connection-type = "rgmii-id";
         };
 };
 
@@ -128,5 +127,6 @@
         status = "okay";
         ethernet1-port@0 {
                 phy-handle = <&ethphy1>;
+                phy-connection-type = "rgmii-id";
         };
 };
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index f50fbc8f3bd9..bdee22541189 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -144,6 +144,7 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <0>;
+                        clock-frequency = <400000000>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
deleted file mode 100644
index b27c6373ff4d..000000000000
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Reference Device Tree Source for the Marzen board
- *
- * Copyright (C) 2013 Renesas Solutions Corp.
- * Copyright (C) 2013 Simon Horman
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/dts-v1/;
-#include "r8a7779.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-        model = "marzen";
-        compatible = "renesas,marzen-reference", "renesas,r8a7779";
-
-        chosen {
-                bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on rw";
-        };
-
-        memory {
-                device_type = "memory";
-                reg = <0x60000000 0x40000000>;
-        };
-
-        fixedregulator3v3: fixedregulator@0 {
-                compatible = "regulator-fixed";
-                regulator-name = "fixed-3.3V";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                regulator-boot-on;
-                regulator-always-on;
-        };
-
-        lan0@18000000 {
-                compatible = "smsc,lan9220", "smsc,lan9115";
-                reg = <0x18000000 0x100>;
-                pinctrl-0 = <&lan0_pins>;
-                pinctrl-names = "default";
-
-                phy-mode = "mii";
-                interrupt-parent = <&irqpin0>;
-                interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
-                smsc,irq-push-pull;
-                reg-io-width = <4>;
-                vddvario-supply = <&fixedregulator3v3>;
-                vdd33a-supply = <&fixedregulator3v3>;
-        };
-
-        leds {
-                compatible = "gpio-leds";
-                led2 {
-                        gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
-                };
-                led3 {
-                        gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
-                };
-                led4 {
-                        gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
-                };
-        };
-};
-
-&irqpin0 {
-        status = "okay";
-};
-
-&pfc {
-        pinctrl-0 = <&scif2_pins &scif4_pins>;
-        pinctrl-names = "default";
-
-        lan0_pins: lan0 {
-                intc {
-                        renesas,groups = "intc_irq1_b";
-                        renesas,function = "intc";
-                };
-                lbsc {
-                        renesas,groups = "lbsc_ex_cs0";
-                        renesas,function = "lbsc";
-                };
-        };
-
-        scif2_pins: serial2 {
-                renesas,groups = "scif2_data_c";
-                renesas,function = "scif2";
-        };
-
-        scif4_pins: serial4 {
-                renesas,groups = "scif4_data";
-                renesas,function = "scif4";
-        };
-
-        sdhi0_pins: sd0 {
-                renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
-                renesas,function = "sdhi0";
-        };
-
-        hspi0_pins: hspi0 {
-                renesas,groups = "hspi0";
-                renesas,function = "hspi0";
-        };
-};
-
-&sdhi0 {
-        pinctrl-0 = <&sdhi0_pins>;
-        pinctrl-names = "default";
-
-        vmmc-supply = <&fixedregulator3v3>;
-        bus-width = <4>;
-        status = "okay";
-};
-
-&hspi0 {
-        pinctrl-0 = <&hspi0_pins>;
-        pinctrl-names = "default";
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index a7af2c2371f2..5745555df943 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -11,17 +11,131 @@
 
 /dts-v1/;
 #include "r8a7779.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         model = "marzen";
         compatible = "renesas,marzen", "renesas,r8a7779";
 
+        aliases {
+                serial2 = &scif2;
+                serial4 = &scif4;
+        };
+
         chosen {
-                bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on";
+                bootargs = "console=ttySC2,115200 ignore_loglevel root=/dev/nfs ip=on";
         };
 
         memory {
                 device_type = "memory";
                 reg = <0x60000000 0x40000000>;
         };
+
+        fixedregulator3v3: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        lan0@18000000 {
+                compatible = "smsc,lan9220", "smsc,lan9115";
+                reg = <0x18000000 0x100>;
+                pinctrl-0 = <&lan0_pins>;
+                pinctrl-names = "default";
+
+                phy-mode = "mii";
+                interrupt-parent = <&irqpin0>;
+                interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+                smsc,irq-push-pull;
+                reg-io-width = <4>;
+                vddvario-supply = <&fixedregulator3v3>;
+                vdd33a-supply = <&fixedregulator3v3>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led2 {
+                        gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+                };
+                led3 {
+                        gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+                };
+                led4 {
+                        gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+
+&irqpin0 {
+        status = "okay";
+};
+
+&extal_clk {
+        clock-frequency = <31250000>;
+};
+
+&pfc {
+        lan0_pins: lan0 {
+                intc {
+                        renesas,groups = "intc_irq1_b";
+                        renesas,function = "intc";
+                };
+                lbsc {
+                        renesas,groups = "lbsc_ex_cs0";
+                        renesas,function = "lbsc";
+                };
+        };
+
+        scif2_pins: serial2 {
+                renesas,groups = "scif2_data_c";
+                renesas,function = "scif2";
+        };
+
+        scif4_pins: serial4 {
+                renesas,groups = "scif4_data";
+                renesas,function = "scif4";
+        };
+
+        sdhi0_pins: sd0 {
+                renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
+                renesas,function = "sdhi0";
+        };
+
+        hspi0_pins: hspi0 {
+                renesas,groups = "hspi0";
+                renesas,function = "hspi0";
+        };
+};
+
+&scif2 {
+        pinctrl-0 = <&scif2_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+};
+
+&scif4 {
+        pinctrl-0 = <&scif4_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+};
+
+&sdhi0 {
+        pinctrl-0 = <&sdhi0_pins>;
+        pinctrl-names = "default";
+
+        vmmc-supply = <&fixedregulator3v3>;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&hspi0 {
+        pinctrl-0 = <&hspi0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
 };
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index b517c8e6b420..94e2fc836492 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -11,6 +11,7 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/clock/r8a7779-clock.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
@@ -25,21 +26,25 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <0>;
+                        clock-frequency = <1000000000>;
                 };
                 cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <1>;
+                        clock-frequency = <1000000000>;
                 };
                 cpu@2 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <2>;
+                        clock-frequency = <1000000000>;
                 };
                 cpu@3 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <3>;
+                        clock-frequency = <1000000000>;
                 };
         };
 
@@ -157,6 +162,7 @@
                 compatible = "renesas,i2c-r8a7779";
                 reg = <0xffc70000 0x1000>;
                 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
                 status = "disabled";
         };
 
@@ -166,6 +172,7 @@
                 compatible = "renesas,i2c-r8a7779";
                 reg = <0xffc71000 0x1000>;
                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
                 status = "disabled";
         };
 
@@ -175,6 +182,7 @@
                 compatible = "renesas,i2c-r8a7779";
                 reg = <0xffc72000 0x1000>;
                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
                 status = "disabled";
         };
 
@@ -184,6 +192,67 @@
                 compatible = "renesas,i2c-r8a7779";
                 reg = <0xffc73000 0x1000>;
                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
+                status = "disabled";
+        };
+
+        scif0: serial@ffe40000 {
+                compatible = "renesas,scif-r8a7779", "renesas,scif";
+                reg = <0xffe40000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cpg_clocks R8A7779_CLK_P>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scif1: serial@ffe41000 {
+                compatible = "renesas,scif-r8a7779", "renesas,scif";
+                reg = <0xffe41000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cpg_clocks R8A7779_CLK_P>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scif2: serial@ffe42000 {
+                compatible = "renesas,scif-r8a7779", "renesas,scif";
+                reg = <0xffe42000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cpg_clocks R8A7779_CLK_P>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scif3: serial@ffe43000 {
+                compatible = "renesas,scif-r8a7779", "renesas,scif";
+                reg = <0xffe43000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cpg_clocks R8A7779_CLK_P>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scif4: serial@ffe44000 {
+                compatible = "renesas,scif-r8a7779", "renesas,scif";
+                reg = <0xffe44000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cpg_clocks R8A7779_CLK_P>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+
+        scif5: serial@ffe45000 {
+                compatible = "renesas,scif-r8a7779", "renesas,scif";
+                reg = <0xffe45000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cpg_clocks R8A7779_CLK_P>;
+                clock-names = "sci_ick";
                 status = "disabled";
         };
 
@@ -201,12 +270,14 @@
                 compatible = "renesas,rcar-sata";
                 reg = <0xfc600000 0x2000>;
                 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7779_CLK_SATA>;
         };
 
         sdhi0: sd@ffe4c000 {
                 compatible = "renesas,sdhi-r8a7779";
                 reg = <0xffe4c000 0x100>;
                 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
@@ -216,6 +287,7 @@
                 compatible = "renesas,sdhi-r8a7779";
                 reg = <0xffe4d000 0x100>;
                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
@@ -225,6 +297,7 @@
                 compatible = "renesas,sdhi-r8a7779";
                 reg = <0xffe4e000 0x100>;
                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
@@ -234,6 +307,7 @@
                 compatible = "renesas,sdhi-r8a7779";
                 reg = <0xffe4f000 0x100>;
                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
@@ -245,6 +319,7 @@
                 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
                 status = "disabled";
         };
 
@@ -254,6 +329,7 @@
                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
                 status = "disabled";
         };
 
@@ -263,6 +339,150 @@
                 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
                 status = "disabled";
         };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /* External root clock */
+                extal_clk: extal_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        /* This value must be overriden by the board. */
+                        clock-frequency = <0>;
+                        clock-output-names = "extal";
+                };
+
+                /* Special CPG clocks */
+                cpg_clocks: clocks@ffc80000 {
+                        compatible = "renesas,r8a7779-cpg-clocks";
+                        reg = <0xffc80000 0x30>;
+                        clocks = <&extal_clk>;
+                        #clock-cells = <1>;
+                        clock-output-names = "plla", "z", "zs", "s",
+                                             "s1", "p", "b", "out";
+                };
+
+                /* Fixed factor clocks */
+                i_clk: i_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "i";
+                };
+                s3_clk: s3_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "s3";
+                };
+                s4_clk: s4_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+                        #clock-cells = <0>;
+                        clock-div = <16>;
+                        clock-mult = <1>;
+                        clock-output-names = "s4";
+                };
+                g_clk: g_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+                        #clock-cells = <0>;
+                        clock-div = <24>;
+                        clock-mult = <1>;
+                        clock-output-names = "g";
+                };
+
+                /* Gate clocks */
+                mstp0_clks: clocks@ffc80030 {
+                        compatible = "renesas,r8a7779-mstp-clocks",
+                                     "renesas,cpg-mstp-clocks";
+                        reg = <0xffc80030 4>;
+                        clocks = <&cpg_clocks R8A7779_CLK_S>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_S>,
+                                 <&cpg_clocks R8A7779_CLK_S>,
+                                 <&cpg_clocks R8A7779_CLK_S1>,
+                                 <&cpg_clocks R8A7779_CLK_S1>,
+                                 <&cpg_clocks R8A7779_CLK_S1>,
+                                 <&cpg_clocks R8A7779_CLK_S1>,
+                                 <&cpg_clocks R8A7779_CLK_S1>,
+                                 <&cpg_clocks R8A7779_CLK_S1>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7779_CLK_HSPI R8A7779_CLK_TMU2
+                                R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
+                                R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
+                                R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
+                                R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
+                                R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
+                                R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
+                                R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
+                        >;
+                        clock-output-names =
+                                "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
+                                "hscif0", "scif5", "scif4", "scif3", "scif2",
+                                "scif1", "scif0", "i2c3", "i2c2", "i2c1",
+                                "i2c0";
+                };
+                mstp1_clks: clocks@ffc80034 {
+                        compatible = "renesas,r8a7779-mstp-clocks",
+                                     "renesas,cpg-mstp-clocks";
+                        reg = <0xffc80034 4>, <0xffc80044 4>;
+                        clocks = <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_S>,
+                                 <&cpg_clocks R8A7779_CLK_S>,
+                                 <&cpg_clocks R8A7779_CLK_S>,
+                                 <&cpg_clocks R8A7779_CLK_S>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_P>,
+                                 <&cpg_clocks R8A7779_CLK_S>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7779_CLK_USB01 R8A7779_CLK_USB2
+                                R8A7779_CLK_DU R8A7779_CLK_VIN2
+                                R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
+                                R8A7779_CLK_ETHER R8A7779_CLK_SATA
+                                R8A7779_CLK_PCIE R8A7779_CLK_VIN3
+                        >;
+                        clock-output-names =
+                                "usb01", "usb2",
+                                "du", "vin2",
+                                "vin1", "vin0",
+                                "ether", "sata",
+                                "pcie", "vin3";
+                };
+                mstp3_clks: clocks@ffc8003c {
+                        compatible = "renesas,r8a7779-mstp-clocks",
+                                     "renesas,cpg-mstp-clocks";
+                        reg = <0xffc8003c 4>;
+                        clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
+                                 <&s4_clk>, <&s4_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
+                                R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
+                                R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
+                        >;
+                        clock-output-names =
+                                "sdhi3", "sdhi2", "sdhi1", "sdhi0",
+                                "mmc1", "mmc0";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index d6f254f302fe..a0f6f75fe3b5 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -169,8 +169,8 @@
 
                         pinctrl-names   = "default";
                         pinctrl-0       = <&pinctrl_mii0>;
-                        clock-names     = "stmmaceth";
-                        clocks          = <&clk_s_a1_ls CLK_GMAC0_PHY>;
+                        clock-names     = "stmmaceth", "sti-ethclk";
+                        clocks          = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
                 };
 
                 ethernet1: dwmac@fef08000 {
@@ -192,8 +192,8 @@
                         reset-names             = "stmmaceth";
                         pinctrl-names   = "default";
                         pinctrl-0       = <&pinctrl_mii1>;
-                        clock-names     = "stmmaceth";
-                        clocks          = <&clk_s_a0_ls CLK_ETH1_PHY>;
+                        clock-names     = "stmmaceth", "sti-ethclk";
+                        clocks          = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
                 };
 
                 rc: rc@fe518000 {
diff --git a/arch/arm/boot/dts/stih416-b2020-revE.dts b/arch/arm/boot/dts/stih416-b2020e.dts
index ba0fa2caaf18..ba0fa2caaf18 100644
--- a/arch/arm/boot/dts/stih416-b2020-revE.dts
+++ b/arch/arm/boot/dts/stih416-b2020e.dts
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 06473c5d9ea9..84758d76d064 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -175,8 +175,8 @@
                         reset-names             = "stmmaceth";
                         pinctrl-names   = "default";
                         pinctrl-0       = <&pinctrl_mii0>;
-                        clock-names     = "stmmaceth";
-                        clocks          = <&clk_s_a1_ls CLK_GMAC0_PHY>;
+                        clock-names     = "stmmaceth", "sti-ethclk";
+                        clocks          = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
                 };
 
                 ethernet1: dwmac@fef08000 {
@@ -197,8 +197,8 @@
                         reset-names     = "stmmaceth";
                         pinctrl-names   = "default";
                         pinctrl-0       = <&pinctrl_mii1>;
-                        clock-names     = "stmmaceth";
-                        clocks          = <&clk_s_a0_ls CLK_ETH1_PHY>;
+                        clock-names     = "stmmaceth", "sti-ethclk";
+                        clocks          = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
                 };
 
                 rc: rc@fe518000 {
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index e01e5a081def..36c771a2d765 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -19,6 +19,41 @@
                 reg = <0x0 0x08000000>;
         };
 
+        xtal24mhz: xtal24mhz@24M {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+        };
+
+        core-module@10000000 {
+                compatible = "arm,core-module-versatile", "syscon";
+                reg = <0x10000000 0x200>;
+
+                /* OSC1 on AB, OSC4 on PB */
+                osc1: cm_aux_osc@24M {
+                        #clock-cells = <0>;
+                        compatible = "arm,versatile-cm-auxosc";
+                        clocks = <&xtal24mhz>;
+                };
+
+                /* The timer clock is the 24 MHz oscillator divided to 1MHz */
+                timclk: timclk@1M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <24>;
+                        clock-mult = <1>;
+                        clocks = <&xtal24mhz>;
+                };
+
+                pclk: pclk@24M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <1>;
+                        clock-mult = <1>;
+                        clocks = <&xtal24mhz>;
+                };
+        };
+
         flash@34000000 {
                 compatible = "arm,versatile-flash";
                 reg = <0x34000000 0x4000000>;
@@ -59,6 +94,8 @@
                         interrupt-controller;
                         #interrupt-cells = <1>;
                         reg = <0x10140000 0x1000>;
+                        clear-mask = <0xffffffff>;
+                        valid-mask = <0xffffffff>;
                 };
 
                 sic: intc@10003000 {
@@ -68,69 +105,93 @@
                         reg = <0x10003000 0x1000>;
                         interrupt-parent = <&vic>;
                         interrupts = <31>; /* Cascaded to vic */
+                        clear-mask = <0xffffffff>;
+                        valid-mask = <0xffc203f8>;
                 };
 
                 dma@10130000 {
                         compatible = "arm,pl081", "arm,primecell";
                         reg = <0x10130000 0x1000>;
                         interrupts = <17>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 uart0: uart@101f1000 {
                         compatible = "arm,pl011", "arm,primecell";
                         reg = <0x101f1000 0x1000>;
                         interrupts = <12>;
+                        clocks = <&xtal24mhz>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
                 };
 
                 uart1: uart@101f2000 {
                         compatible = "arm,pl011", "arm,primecell";
                         reg = <0x101f2000 0x1000>;
                         interrupts = <13>;
+                        clocks = <&xtal24mhz>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
                 };
 
                 uart2: uart@101f3000 {
                         compatible = "arm,pl011", "arm,primecell";
                         reg = <0x101f3000 0x1000>;
                         interrupts = <14>;
+                        clocks = <&xtal24mhz>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
                 };
 
                 smc@10100000 {
                         compatible = "arm,primecell";
                         reg = <0x10100000 0x1000>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 mpmc@10110000 {
                         compatible = "arm,primecell";
                         reg = <0x10110000 0x1000>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 display@10120000 {
                         compatible = "arm,pl110", "arm,primecell";
                         reg = <0x10120000 0x1000>;
                         interrupts = <16>;
+                        clocks = <&osc1>, <&pclk>;
+                        clock-names = "clcd", "apb_pclk";
                 };
 
                 sctl@101e0000 {
                         compatible = "arm,primecell";
                         reg = <0x101e0000 0x1000>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 watchdog@101e1000 {
                         compatible = "arm,primecell";
                         reg = <0x101e1000 0x1000>;
                         interrupts = <0>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 timer@101e2000 {
                         compatible = "arm,sp804", "arm,primecell";
                         reg = <0x101e2000 0x1000>;
                         interrupts = <4>;
+                        clocks = <&timclk>, <&timclk>, <&pclk>;
+                        clock-names = "timer0", "timer1", "apb_pclk";
                 };
 
                 timer@101e3000 {
                         compatible = "arm,sp804", "arm,primecell";
                         reg = <0x101e3000 0x1000>;
                         interrupts = <5>;
+                        clocks = <&timclk>, <&timclk>, <&pclk>;
+                        clock-names = "timer0", "timer1", "apb_pclk";
                 };
 
                 gpio0: gpio@101e4000 {
@@ -141,6 +202,8 @@
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 gpio1: gpio@101e5000 {
@@ -151,24 +214,32 @@
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 rtc@101e8000 {
                         compatible = "arm,pl030", "arm,primecell";
                         reg = <0x101e8000 0x1000>;
                         interrupts = <10>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 sci@101f0000 {
                         compatible = "arm,primecell";
                         reg = <0x101f0000 0x1000>;
                         interrupts = <15>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 ssp@101f4000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x101f4000 0x1000>;
                         interrupts = <11>;
+                        clocks = <&xtal24mhz>, <&pclk>;
+                        clock-names = "SSPCLK", "apb_pclk";
                 };
 
                 fpga {
@@ -181,23 +252,31 @@
                                 compatible = "arm,primecell";
                                 reg = <0x4000 0x1000>;
                                 interrupts = <24>;
+                                clocks = <&pclk>;
+                                clock-names = "apb_pclk";
                         };
                         mmc@5000 {
-                                compatible = "arm,primecell";
+                                compatible = "arm,pl180", "arm,primecell";
                                 reg = < 0x5000 0x1000>;
                                 interrupts-extended = <&vic 22 &sic 2>;
+                                clocks = <&xtal24mhz>, <&pclk>;
+                                clock-names = "mclk", "apb_pclk";
                         };
                         kmi@6000 {
                                 compatible = "arm,pl050", "arm,primecell";
                                 reg = <0x6000 0x1000>;
                                 interrupt-parent = <&sic>;
                                 interrupts = <3>;
+                                clocks = <&xtal24mhz>, <&pclk>;
+                                clock-names = "KMIREFCLK", "apb_pclk";
                         };
                         kmi@7000 {
                                 compatible = "arm,pl050", "arm,primecell";
                                 reg = <0x7000 0x1000>;
                                 interrupt-parent = <&sic>;
                                 interrupts = <4>;
+                                clocks = <&xtal24mhz>, <&pclk>;
+                                clock-names = "KMIREFCLK", "apb_pclk";
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
index 65f657711323..d025048119d3 100644
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -13,6 +13,8 @@
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 gpio3: gpio@101e7000 {
@@ -23,6 +25,8 @@
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 fpga {
@@ -31,17 +35,23 @@
                                 reg = <0x9000 0x1000>;
                                 interrupt-parent = <&sic>;
                                 interrupts = <6>;
+                                clocks = <&xtal24mhz>, <&pclk>;
+                                clock-names = "uartclk", "apb_pclk";
                         };
                         sci@a000 {
                                 compatible = "arm,primecell";
                                 reg = <0xa000 0x1000>;
                                 interrupt-parent = <&sic>;
                                 interrupts = <5>;
+                                clocks = <&xtal24mhz>;
+                                clock-names = "apb_pclk";
                         };
                         mmc@b000 {
-                                compatible = "arm,primecell";
+                                compatible = "arm,pl180", "arm,primecell";
                                 reg = <0xb000 0x1000>;
                                 interrupts-extended = <&vic 23 &sic 2>;
+                                clocks = <&xtal24mhz>, <&pclk>;
+                                clock-names = "mclk", "apb_pclk";
                         };
                 };
         };
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c
index 6ef146edd0cd..a20fa80776d3 100644
--- a/arch/arm/common/scoop.c
+++ b/arch/arm/common/scoop.c
@@ -182,7 +182,6 @@ static int scoop_probe(struct platform_device *pdev)
         struct scoop_config *inf;
         struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         int ret;
-        int temp;
 
         if (!mem)
                 return -EINVAL;
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c
index fd6bff0c5b96..19211324772f 100644
--- a/arch/arm/common/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -233,13 +233,13 @@ static void __init sp804_of_init(struct device_node *np)
         if (IS_ERR(clk1))
                 clk1 = NULL;
 
-        /* Get the 2nd clock if the timer has 2 timer clocks */
+        /* Get the 2nd clock if the timer has 3 timer clocks */
         if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
                 clk2 = of_clk_get(np, 1);
                 if (IS_ERR(clk2)) {
                         pr_err("sp804: %s clock not found: %d\n", np->name,
                                 (int)PTR_ERR(clk2));
-                        goto err;
+                        clk2 = NULL;
                 }
         } else
                 clk2 = clk1;
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index bada59d93b67..63bde0efc041 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -1,6 +1,7 @@
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -35,10 +36,8 @@ CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y
 CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y
 CONFIG_MACH_MX27_3DS=y
 CONFIG_MACH_IMX27_VISSTRIM_M10=y
-CONFIG_MACH_IMX27LITE=y
 CONFIG_MACH_PCA100=y
 CONFIG_MACH_MXT_TD60=y
-CONFIG_MACH_IMX27IPCAM=y
 CONFIG_MACH_IMX27_DT=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
@@ -159,6 +158,8 @@ CONFIG_USB_CHIPIDEA=y
 CONFIG_USB_CHIPIDEA_UDC=y
 CONFIG_USB_CHIPIDEA_HOST=y
 CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ETH=m
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index ef8815327e5b..16cfec4385c8 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -1,5 +1,6 @@
 CONFIG_KERNEL_LZO=y
 CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=18
@@ -31,11 +32,12 @@ CONFIG_MACH_IMX35_DT=y
 CONFIG_MACH_PCM043=y
 CONFIG_MACH_MX35_3DS=y
 CONFIG_MACH_VPR200=y
-CONFIG_MACH_IMX51_DT=y
+CONFIG_SOC_IMX51=y
 CONFIG_SOC_IMX50=y
 CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_SOC_IMX6SL=y
+CONFIG_SOC_IMX6SX=y
 CONFIG_SOC_VF610=y
 CONFIG_PCI=y
 CONFIG_PCI_IMX6=y
@@ -67,6 +69,8 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_INET_LRO is not set
 CONFIG_IPV6=y
 CONFIG_NETFILTER=y
+CONFIG_CAN=y
+CONFIG_CAN_FLEXCAN=y
 CONFIG_CFG80211=y
 CONFIG_MAC80211=y
 CONFIG_RFKILL=y
@@ -160,6 +164,7 @@ CONFIG_SPI=y
 CONFIG_SPI_IMX=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_MC9S08DZ60=y
+CONFIG_GPIO_STMPE=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_IMX2_WDT=y
@@ -186,6 +191,7 @@ CONFIG_VIDEO_MX3=y
 CONFIG_V4L_MEM2MEM_DRIVERS=y
 CONFIG_VIDEO_CODA=y
 CONFIG_SOC_CAMERA_OV2640=y
+CONFIG_IMX_IPUV3_CORE=y
 CONFIG_DRM=y
 CONFIG_DRM_PANEL_SIMPLE=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
@@ -241,6 +247,7 @@ CONFIG_RTC_DRV_SNVS=y
 CONFIG_DMADEVICES=y
 CONFIG_IMX_SDMA=y
 CONFIG_MXS_DMA=y
+CONFIG_FSL_EDMA=y
 CONFIG_STAGING=y
 CONFIG_DRM_IMX=y
 CONFIG_DRM_IMX_FB_HELPER=y
@@ -287,6 +294,7 @@ CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_FS=y
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_SCHED_DEBUG is not set
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index e2d62048e198..9a1e7b0c3bea 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -27,7 +27,7 @@ CONFIG_ARCH_HIGHBANK=y
 CONFIG_ARCH_HI3xxx=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_ARCH_MXC=y
-CONFIG_MACH_IMX51_DT=y
+CONFIG_SOC_IMX51=y
 CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_SOC_IMX6SL=y
@@ -300,6 +300,7 @@ CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_OF_ARASAN=y
 CONFIG_MMC_SDHCI_ESDHC_IMX=y
 CONFIG_MMC_SDHCI_DOVE=y
@@ -352,6 +353,7 @@ CONFIG_MFD_NVEC=y
 CONFIG_KEYBOARD_NVEC=y
 CONFIG_SERIO_NVEC_PS2=y
 CONFIG_NVEC_POWER=y
+CONFIG_QCOM_GSBI=y
 CONFIG_COMMON_CLK_QCOM=y
 CONFIG_MSM_GCC_8660=y
 CONFIG_MSM_MMCC_8960=y
diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
index e11170e37442..b0bfefa23902 100644
--- a/arch/arm/configs/mvebu_v7_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -14,6 +14,7 @@ CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_375=y
 CONFIG_MACH_ARMADA_38X=y
 CONFIG_MACH_ARMADA_XP=y
+CONFIG_MACH_DOVE=y
 CONFIG_NEON=y
 # CONFIG_CACHE_L2X0 is not set
 # CONFIG_SWP_EMULATE is not set
@@ -52,6 +53,7 @@ CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_I2C=y
 CONFIG_SPI=y
 CONFIG_SPI_ORION=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index a9f992335eb2..c7906c2fd645 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -1,4 +1,5 @@
 CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_TASKSTATS=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 59066cf0271a..536a137863cb 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -32,6 +32,7 @@ CONFIG_SOC_OMAP5=y
 CONFIG_SOC_AM33XX=y
 CONFIG_SOC_AM43XX=y
 CONFIG_SOC_DRA7XX=y
+CONFIG_CACHE_L2X0=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_ARM_ERRATA_411920=y
 CONFIG_SMP=y
diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h
index eb577f4f5f70..39eb16b0066f 100644
--- a/arch/arm/include/asm/ftrace.h
+++ b/arch/arm/include/asm/ftrace.h
@@ -52,7 +52,7 @@ extern inline void *return_address(unsigned int level)
 
 #endif
 
-#define ftrace_return_addr(n) return_address(n)
+#define ftrace_return_address(n) return_address(n)
 
 #endif /* ifndef __ASSEMBLY__ */
 
diff --git a/arch/arm/include/asm/mcpm.h b/arch/arm/include/asm/mcpm.h
index d9702eb0b02b..94060adba174 100644
--- a/arch/arm/include/asm/mcpm.h
+++ b/arch/arm/include/asm/mcpm.h
@@ -208,8 +208,6 @@ struct sync_struct {
         struct mcpm_sync_struct clusters[MAX_NR_CLUSTERS];
 };
 
-extern unsigned long sync_phys; /* physical address of *mcpm_sync */
-
 void __mcpm_cpu_going_down(unsigned int cpu, unsigned int cluster);
 void __mcpm_cpu_down(unsigned int cpu, unsigned int cluster);
 void __mcpm_outbound_leave_critical(unsigned int cluster, int state);
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index f989d7c22dc5..e4e4208a9130 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -114,8 +114,14 @@ static inline struct thread_info *current_thread_info(void)
         ((unsigned long)(task_thread_info(tsk)->cpu_context.pc))
 #define thread_saved_sp(tsk)    \
         ((unsigned long)(task_thread_info(tsk)->cpu_context.sp))
+
+#ifndef CONFIG_THUMB2_KERNEL
 #define thread_saved_fp(tsk)    \
         ((unsigned long)(task_thread_info(tsk)->cpu_context.fp))
+#else
+#define thread_saved_fp(tsk)    \
+        ((unsigned long)(task_thread_info(tsk)->cpu_context.r7))
+#endif
 
 extern void crunch_task_disable(struct thread_info *);
 extern void crunch_task_copy(struct thread_info *, void *);
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 2037f7205987..1d37568c547a 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -1924,7 +1924,7 @@ static int krait_pmu_get_event_idx(struct pmu_hw_events *cpuc,
                                    struct perf_event *event)
 {
         int idx;
-        int bit;
+        int bit = -1;
         unsigned int prefix;
         unsigned int region;
         unsigned int code;
@@ -1953,7 +1953,7 @@ static int krait_pmu_get_event_idx(struct pmu_hw_events *cpuc,
         }
 
         idx = armv7pmu_get_event_idx(cpuc, event);
-        if (idx < 0 && krait_event)
+        if (idx < 0 && bit >= 0)
                 clear_bit(bit, cpuc->used_mask);
 
         return idx;
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 0dd3b79b15c3..0c27ed6f3f23 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -908,7 +908,7 @@ enum ptrace_syscall_dir {
         PTRACE_SYSCALL_EXIT,
 };
 
-static int tracehook_report_syscall(struct pt_regs *regs,
+static void tracehook_report_syscall(struct pt_regs *regs,
                                     enum ptrace_syscall_dir dir)
 {
         unsigned long ip;
@@ -926,7 +926,6 @@ static int tracehook_report_syscall(struct pt_regs *regs,
                 current_thread_info()->syscall = -1;
 
         regs->ARM_ip = ip;
-        return current_thread_info()->syscall;
 }
 
 asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
@@ -938,7 +937,9 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
                 return -1;
 
         if (test_thread_flag(TIF_SYSCALL_TRACE))
-                scno = tracehook_report_syscall(regs, PTRACE_SYSCALL_ENTER);
+                tracehook_report_syscall(regs, PTRACE_SYSCALL_ENTER);
+
+        scno = current_thread_info()->syscall;
 
         if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
                 trace_sys_enter(regs, scno);
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
index 5306de350133..312d43eb686a 100644
--- a/arch/arm/lib/delay.c
+++ b/arch/arm/lib/delay.c
@@ -19,6 +19,7 @@
  * Author: Will Deacon <will.deacon@arm.com>
  */
 
+#include <linux/clocksource.h>
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -36,6 +37,7 @@ struct arm_delay_ops arm_delay_ops = {
 
 static const struct delay_timer *delay_timer;
 static bool delay_calibrated;
+static u64 delay_res;
 
 int read_current_timer(unsigned long *timer_val)
 {
@@ -47,6 +49,11 @@ int read_current_timer(unsigned long *timer_val)
 }
 EXPORT_SYMBOL_GPL(read_current_timer);
 
+static inline u64 cyc_to_ns(u64 cyc, u32 mult, u32 shift)
+{
+        return (cyc * mult) >> shift;
+}
+
 static void __timer_delay(unsigned long cycles)
 {
         cycles_t start = get_cycles();
@@ -69,18 +76,24 @@ static void __timer_udelay(unsigned long usecs)
 
 void __init register_current_timer_delay(const struct delay_timer *timer)
 {
-        if (!delay_calibrated) {
-                pr_info("Switching to timer-based delay loop\n");
+        u32 new_mult, new_shift;
+        u64 res;
+
+        clocks_calc_mult_shift(&new_mult, &new_shift, timer->freq,
+                               NSEC_PER_SEC, 3600);
+        res = cyc_to_ns(1ULL, new_mult, new_shift);
+
+        if (!delay_calibrated && (!delay_res || (res < delay_res))) {
+                pr_info("Switching to timer-based delay loop, resolution %lluns\n", res);
                 delay_timer                     = timer;
                 lpj_fine                        = timer->freq / HZ;
+                delay_res                       = res;
 
                 /* cpufreq may scale loops_per_jiffy, so keep a private copy */
                 arm_delay_ops.ticks_per_jiffy   = lpj_fine;
                 arm_delay_ops.delay             = __timer_delay;
                 arm_delay_ops.const_udelay      = __timer_const_udelay;
                 arm_delay_ops.udelay            = __timer_udelay;
-
-                delay_calibrated                = true;
         } else {
                 pr_info("Ignoring duplicate/late registration of read_current_timer delay\n");
         }
@@ -91,3 +104,8 @@ unsigned long calibrate_delay_is_known(void)
         delay_calibrated = true;
         return lpj_fine;
 }
+
+void calibration_delay_done(void)
+{
+        delay_calibrated = true;
+}
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 9bc6db1c1348..41c839167e87 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -1,10 +1,9 @@
-config ARCH_BCM
+menuconfig ARCH_BCM
         bool "Broadcom SoC Support" if ARCH_MULTI_V6_V7
         help
           This enables support for Broadcom ARM based SoC chips
 
-menu "Broadcom SoC Selection"
-        depends on ARCH_BCM
+if ARCH_BCM
 
 config ARCH_BCM_MOBILE
         bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
@@ -88,4 +87,4 @@ config ARCH_BCM_5301X
           different SoC or with the older BCM47XX and BCM53XX based
           network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
 
-endmenu
+endif
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
index 101e0f356730..24f85be71671 100644
--- a/arch/arm/mach-berlin/Kconfig
+++ b/arch/arm/mach-berlin/Kconfig
@@ -1,4 +1,4 @@
-config ARCH_BERLIN
+menuconfig ARCH_BERLIN
         bool "Marvell Berlin SoCs" if ARCH_MULTI_V7
         select ARCH_REQUIRE_GPIOLIB
         select ARM_GIC
@@ -9,13 +9,13 @@ config ARCH_BERLIN
 
 if ARCH_BERLIN
 
-menu "Marvell Berlin SoC variants"
-
 config MACH_BERLIN_BG2
         bool "Marvell Armada 1500 (BG2)"
         select CACHE_L2X0
         select CPU_PJ4B
+        select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
+        select HAVE_SMP
         select PINCTRL_BERLIN_BG2
 
 config MACH_BERLIN_BG2CD
@@ -27,9 +27,8 @@ config MACH_BERLIN_BG2CD
 config MACH_BERLIN_BG2Q
         bool "Marvell Armada 1500 Pro (BG2-Q)"
         select CACHE_L2X0
+        select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
         select PINCTRL_BERLIN_BG2Q
 
-endmenu
-
 endif
diff --git a/arch/arm/mach-berlin/Makefile b/arch/arm/mach-berlin/Makefile
index ab69fe956f49..c0719ecd1890 100644
--- a/arch/arm/mach-berlin/Makefile
+++ b/arch/arm/mach-berlin/Makefile
@@ -1 +1,2 @@
-obj-y += berlin.o
+obj-y                   += berlin.o
+obj-$(CONFIG_SMP)       += headsmp.o platsmp.o
diff --git a/arch/arm/mach-berlin/headsmp.S b/arch/arm/mach-berlin/headsmp.S
new file mode 100644
index 000000000000..4a4c56a58ad3
--- /dev/null
+++ b/arch/arm/mach-berlin/headsmp.S
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2014 Marvell Technology Group Ltd.
+ *
+ * Antoine Ténart <antoine.tenart@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/assembler.h>
+
+ENTRY(berlin_secondary_startup)
+ ARM_BE8(setend be)
+        bl      v7_invalidate_l1
+        b       secondary_startup
+ENDPROC(berlin_secondary_startup)
+
+/*
+ * If the following instruction is set in the reset exception vector, CPUs
+ * will fetch the value of the software reset address vector when being
+ * reset.
+ */
+.global boot_inst
+boot_inst:
+        ldr     pc, [pc, #140]
+
+        .align
diff --git a/arch/arm/mach-berlin/platsmp.c b/arch/arm/mach-berlin/platsmp.c
new file mode 100644
index 000000000000..702e7982015a
--- /dev/null
+++ b/arch/arm/mach-berlin/platsmp.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2014 Marvell Technology Group Ltd.
+ *
+ * Antoine Ténart <antoine.tenart@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+
+#define CPU_RESET               0x00
+
+#define RESET_VECT              0x00
+#define SW_RESET_ADDR           0x94
+
+extern void berlin_secondary_startup(void);
+extern u32 boot_inst;
+
+static void __iomem *cpu_ctrl;
+
+static inline void berlin_perform_reset_cpu(unsigned int cpu)
+{
+        u32 val;
+
+        val = readl(cpu_ctrl + CPU_RESET);
+        val |= BIT(cpu_logical_map(cpu));
+        writel(val, cpu_ctrl + CPU_RESET);
+}
+
+static int berlin_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        if (!cpu_ctrl)
+                return -EFAULT;
+
+        /*
+         * Reset the CPU, making it to execute the instruction in the reset
+         * exception vector.
+         */
+        berlin_perform_reset_cpu(cpu);
+
+        return 0;
+}
+
+static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
+{
+        struct device_node *np;
+        void __iomem *scu_base;
+        void __iomem *vectors_base;
+
+        np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+        scu_base = of_iomap(np, 0);
+        of_node_put(np);
+        if (!scu_base)
+                return;
+
+        np = of_find_compatible_node(NULL, NULL, "marvell,berlin-cpu-ctrl");
+        cpu_ctrl = of_iomap(np, 0);
+        of_node_put(np);
+        if (!cpu_ctrl)
+                goto unmap_scu;
+
+        vectors_base = ioremap(CONFIG_VECTORS_BASE, SZ_32K);
+        if (!vectors_base)
+                goto unmap_scu;
+
+        scu_enable(scu_base);
+        flush_cache_all();
+
+        /*
+         * Write the first instruction the CPU will execute after being reset
+         * in the reset exception vector.
+         */
+        writel(boot_inst, vectors_base + RESET_VECT);
+
+        /*
+         * Write the secondary startup address into the SW reset address
+         * vector. This is used by boot_inst.
+         */
+        writel(virt_to_phys(berlin_secondary_startup), vectors_base + SW_RESET_ADDR);
+
+        iounmap(vectors_base);
+unmap_scu:
+        iounmap(scu_base);
+}
+
+static struct smp_operations berlin_smp_ops __initdata = {
+        .smp_prepare_cpus       = berlin_smp_prepare_cpus,
+        .smp_boot_secondary     = berlin_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(berlin_smp, "marvell,berlin-smp", &berlin_smp_ops);
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
index 66838f42037f..3c22a1990ecd 100644
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -1,12 +1,11 @@
-config ARCH_CNS3XXX
+menuconfig ARCH_CNS3XXX
         bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
         select ARM_GIC
         select PCI_DOMAINS if PCI
         help
           Support for Cavium Networks CNS3XXX platform.
 
-menu "CNS3XXX platform type"
-        depends on ARCH_CNS3XXX
+if ARCH_CNS3XXX
 
 config MACH_CNS3420VB
         bool "Support for CNS3420 Validation Board"
@@ -17,4 +16,4 @@ config MACH_CNS3420VB
           This is a platform with an on-board ARM11 MPCore and has support
           for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
 
-endmenu
+endif
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index db18ef866593..584e8d4e2892 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -39,7 +39,6 @@ config ARCH_DAVINCI_DA830
 config ARCH_DAVINCI_DA850
         bool "DA850/OMAP-L138/AM18x based system"
         select ARCH_DAVINCI_DA8XX
-        select ARCH_HAS_CPUFREQ
         select CP_INTC
 
 config ARCH_DAVINCI_DA8XX
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index d58995c9a95a..8f9b66c4ac78 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -7,10 +7,9 @@
 
 # Configuration options for the EXYNOS4
 
-config ARCH_EXYNOS
+menuconfig ARCH_EXYNOS
         bool "Samsung EXYNOS" if ARCH_MULTI_V7
         select ARCH_HAS_BANDGAP
-        select ARCH_HAS_CPUFREQ
         select ARCH_HAS_HOLES_MEMORYMODEL
         select ARCH_REQUIRE_GPIOLIB
         select ARM_AMBA
@@ -30,8 +29,6 @@ config ARCH_EXYNOS
 
 if ARCH_EXYNOS
 
-menu "SAMSUNG EXYNOS SoCs Support"
-
 config ARCH_EXYNOS3
         bool "SAMSUNG EXYNOS3"
         select ARM_CPU_SUSPEND if PM
@@ -118,8 +115,6 @@ config SOC_EXYNOS5800
         default y
         depends on SOC_EXYNOS5420
 
-endmenu
-
 config EXYNOS5420_MCPM
         bool "Exynos5420 Multi-Cluster PM support"
         depends on MCPM && SOC_EXYNOS5420
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 16617bdb37a9..1ee91763fa7c 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -118,6 +118,7 @@ extern void __iomem *sysram_ns_base_addr;
 extern void __iomem *sysram_base_addr;
 void exynos_init_io(void);
 void exynos_restart(enum reboot_mode mode, const char *cmd);
+void exynos_sysram_init(void);
 void exynos_cpuidle_init(void);
 void exynos_cpufreq_init(void);
 void exynos_init_late(void);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 90aab4d75d08..f38cf7c110cc 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -184,6 +184,28 @@ void __init exynos_cpufreq_init(void)
         platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
 }
 
+void __iomem *sysram_base_addr;
+void __iomem *sysram_ns_base_addr;
+
+void __init exynos_sysram_init(void)
+{
+        struct device_node *node;
+
+        for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
+                if (!of_device_is_available(node))
+                        continue;
+                sysram_base_addr = of_iomap(node, 0);
+                break;
+        }
+
+        for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") {
+                if (!of_device_is_available(node))
+                        continue;
+                sysram_ns_base_addr = of_iomap(node, 0);
+                break;
+        }
+}
+
 void __init exynos_init_late(void)
 {
         if (of_machine_is_compatible("samsung,exynos5440"))
@@ -198,7 +220,7 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
                                         int depth, void *data)
 {
         struct map_desc iodesc;
-        __be32 *reg;
+        const __be32 *reg;
         int len;
 
         if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
@@ -271,6 +293,13 @@ static void __init exynos_dt_machine_init(void)
                 }
         }
 
+        /*
+         * This is called from smp_prepare_cpus if we've built for SMP, but
+         * we still need to set it up for PM and firmware ops if not.
+         */
+        if (!IS_ENABLED(SMP))
+                exynos_sysram_init();
+
         exynos_cpuidle_init();
         exynos_cpufreq_init();
 
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 69fa48397394..8a134d019cb3 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -46,13 +46,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
                 if (cpu == 1)
                         exynos_cpu_power_down(cpu);
 
-                /*
-                 * here's the WFI
-                 */
-                asm(".word      0xe320f003\n"
-                    :
-                    :
-                    : "memory", "cc");
+                wfi();
 
                 if (pen_release == cpu_logical_map(cpu)) {
                         /*
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index 0498d0b887ef..ace0ed617476 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -25,7 +25,6 @@
 
 #define EXYNOS5420_CPUS_PER_CLUSTER     4
 #define EXYNOS5420_NR_CLUSTERS          2
-#define MCPM_BOOT_ADDR_OFFSET           0x1c
 
 /*
  * The common v7_exit_coherency_flush API could not be used because of the
@@ -343,11 +342,13 @@ static int __init exynos_mcpm_init(void)
         pr_info("Exynos MCPM support installed\n");
 
         /*
-         * Future entries into the kernel can now go
-         * through the cluster entry vectors.
+         * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
+         * as part of secondary_cpu_start().  Let's redirect it to the
+         * mcpm_entry_point().
          */
-        __raw_writel(virt_to_phys(mcpm_entry_point),
-                        ns_sram_base_addr + MCPM_BOOT_ADDR_OFFSET);
+        __raw_writel(0xe59f0000, ns_sram_base_addr);     /* ldr r0, [pc, #0] */
+        __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx  r0 */
+        __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
 
         iounmap(ns_sram_base_addr);
 
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index ec02422e8499..1c8d31e39520 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -32,28 +32,6 @@
 
 extern void exynos4_secondary_startup(void);
 
-void __iomem *sysram_base_addr;
-void __iomem *sysram_ns_base_addr;
-
-static void __init exynos_smp_prepare_sysram(void)
-{
-        struct device_node *node;
-
-        for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
-                if (!of_device_is_available(node))
-                        continue;
-                sysram_base_addr = of_iomap(node, 0);
-                break;
-        }
-
-        for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") {
-                if (!of_device_is_available(node))
-                        continue;
-                sysram_ns_base_addr = of_iomap(node, 0);
-                break;
-        }
-}
-
 static inline void __iomem *cpu_boot_reg_base(void)
 {
         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
@@ -234,11 +212,11 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 {
         int i;
 
+        exynos_sysram_init();
+
         if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
                 scu_enable(scu_base_addr());
 
-        exynos_smp_prepare_sysram();
-
         /*
          * Write the address of secondary startup into the
          * system-wide flags register. The boot monitor waits
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 87c0d34c7fba..202ca73e49c4 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -300,7 +300,7 @@ static int exynos_pm_suspend(void)
         tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
         __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 
-        if (!soc_is_exynos5250())
+        if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
                 exynos_cpu_save_register();
 
         return 0;
@@ -334,7 +334,7 @@ static void exynos_pm_resume(void)
         if (exynos_pm_central_resume())
                 goto early_wakeup;
 
-        if (!soc_is_exynos5250())
+        if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
                 exynos_cpu_restore_register();
 
         /* For release retention */
@@ -353,7 +353,7 @@ static void exynos_pm_resume(void)
 
         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 
-        if (!soc_is_exynos5250())
+        if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
                 scu_enable(S5P_VA_SCU);
 
 early_wakeup:
@@ -440,15 +440,18 @@ static int exynos_cpu_pm_notifier(struct notifier_block *self,
         case CPU_PM_ENTER:
                 if (cpu == 0) {
                         exynos_pm_central_suspend();
-                        exynos_cpu_save_register();
+                        if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
+                                exynos_cpu_save_register();
                 }
                 break;
 
         case CPU_PM_EXIT:
                 if (cpu == 0) {
-                        if (!soc_is_exynos5250())
+                        if (read_cpuid_part_number() ==
+                                        ARM_CPU_PART_CORTEX_A9) {
                                 scu_enable(S5P_VA_SCU);
-                        exynos_cpu_restore_register();
+                                exynos_cpu_restore_register();
+                        }
                         exynos_pm_central_resume();
                 }
                 break;
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 830b76e70250..a5960e2ac090 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -1,7 +1,6 @@
 config ARCH_HIGHBANK
         bool "Calxeda ECX-1000/2000 (Highbank/Midway)" if ARCH_MULTI_V7
         select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
-        select ARCH_HAS_CPUFREQ
         select ARCH_HAS_HOLES_MEMORYMODEL
         select ARCH_HAS_OPP
         select ARCH_SUPPORTS_BIG_ENDIAN
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 8d42eab76d53..2bc7b97861b4 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,6 +1,5 @@
-config ARCH_MXC
+menuconfig ARCH_MXC
         bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7
-        select ARCH_HAS_CPUFREQ
         select ARCH_HAS_OPP
         select ARCH_REQUIRE_GPIOLIB
         select ARM_CPU_SUSPEND if PM
@@ -13,8 +12,7 @@ config ARCH_MXC
         help
           Support for Freescale MXC/iMX-based family of processors
 
-menu "Freescale i.MX support"
-        depends on ARCH_MXC
+if ARCH_MXC
 
 config MXC_TZIC
         bool
@@ -67,18 +65,8 @@ config IMX_HAVE_IOMUX_V1
 config ARCH_MXC_IOMUX_V3
         bool
 
-config ARCH_MX1
-        bool
-
-config ARCH_MX25
-        bool
-
-config MACH_MX27
-        bool
-
 config SOC_IMX1
         bool
-        select ARCH_MX1
         select CPU_ARM920T
         select IMX_HAVE_IOMUX_V1
         select MXC_AVIC
@@ -91,7 +79,6 @@ config SOC_IMX21
 
 config SOC_IMX25
         bool
-        select ARCH_MX25
         select ARCH_MXC_IOMUX_V3
         select CPU_ARM926T
         select MXC_AVIC
@@ -99,11 +86,9 @@ config SOC_IMX25
 
 config SOC_IMX27
         bool
-        select ARCH_HAS_CPUFREQ
         select ARCH_HAS_OPP
         select CPU_ARM926T
         select IMX_HAVE_IOMUX_V1
-        select MACH_MX27
         select MXC_AVIC
         select PINCTRL_IMX27
 
@@ -122,19 +107,6 @@ config SOC_IMX35
         select PINCTRL_IMX35
         select SMP_ON_UP if SMP
 
-config SOC_IMX5
-        bool
-        select ARCH_HAS_CPUFREQ
-        select ARCH_HAS_OPP
-        select ARCH_MXC_IOMUX_V3
-        select MXC_TZIC
-
-config  SOC_IMX51
-        bool
-        select HAVE_IMX_SRC
-        select PINCTRL_IMX51
-        select SOC_IMX5
-
 if ARCH_MULTI_V4T
 
 comment "MX1 platforms:"
@@ -370,15 +342,6 @@ config MACH_IMX27_VISSTRIM_M10
           This includes specific configurations for the board and its
           peripherals.
 
-config MACH_IMX27LITE
-        bool "LogicPD MX27 LITEKIT platform"
-        select IMX_HAVE_PLATFORM_IMX_SSI
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select SOC_IMX27
-        help
-          Include support for MX27 LITEKIT platform. This includes specific
-          configurations for the board and its peripherals.
-
 config MACH_PCA100
         bool "Phytec phyCARD-s (pca100)"
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
@@ -410,15 +373,6 @@ config MACH_MXT_TD60
           Include support for i-MXT (aka td60) platform. This
           includes specific configurations for the module and its peripherals.
 
-config MACH_IMX27IPCAM
-        bool "IMX27 IPCAM platform"
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select SOC_IMX27
-        help
-          Include support for IMX27 IPCAM platform. This includes specific
-          configurations for the board and its peripherals.
-
 config MACH_IMX27_DT
         bool "Support i.MX27 platforms from device tree"
         select SOC_IMX27
@@ -704,24 +658,29 @@ if ARCH_MULTI_V7
 
 comment "Device tree only"
 
+config SOC_IMX5
+        bool
+        select ARCH_HAS_OPP
+        select HAVE_IMX_SRC
+        select MXC_TZIC
+
 config  SOC_IMX50
         bool "i.MX50 support"
-        select HAVE_IMX_SRC
         select PINCTRL_IMX50
         select SOC_IMX5
 
         help
           This enables support for Freescale i.MX50 processor.
 
-config MACH_IMX51_DT
+config SOC_IMX51
         bool "i.MX51 support"
-        select SOC_IMX51
+        select PINCTRL_IMX51
+        select SOC_IMX5
         help
           This enables support for Freescale i.MX51 processor
 
 config  SOC_IMX53
         bool "i.MX53 support"
-        select HAVE_IMX_SRC
         select PINCTRL_IMX53
         select SOC_IMX5
 
@@ -738,9 +697,7 @@ config SOC_IMX6
         select HAVE_IMX_MMDC
         select HAVE_IMX_SRC
         select MFD_SYSCON
-        select PL310_ERRATA_588369 if CACHE_PL310
-        select PL310_ERRATA_727915 if CACHE_PL310
-        select PL310_ERRATA_769419 if CACHE_PL310
+        select PL310_ERRATA_769419 if CACHE_L2X0
 
 config SOC_IMX6Q
         bool "i.MX6 Quad/DualLite support"
@@ -775,9 +732,7 @@ config SOC_VF610
         select ARM_GIC
         select PINCTRL_VF610
         select VF_PIT_TIMER
-        select PL310_ERRATA_588369 if CACHE_PL310
-        select PL310_ERRATA_727915 if CACHE_PL310
-        select PL310_ERRATA_769419 if CACHE_PL310
+        select PL310_ERRATA_769419 if CACHE_L2X0
 
         help
           This enable support for Freescale Vybrid VF610 processor.
@@ -786,4 +741,4 @@ endif
 
 source "arch/arm/mach-imx/devices/Kconfig"
 
-endmenu
+endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index bbe93bbfd003..ac88599ca080 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
 
 imx5-pm-$(CONFIG_PM) += pm-imx5.o
-obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y)
+obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y)
 
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
                             clk-pfd.o clk-busy.o clk.o \
@@ -31,6 +31,8 @@ ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
 obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
 obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
+# i.MX6SX reuses i.MX6Q cpuidle driver
+obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6q.o
 endif
 
 ifdef CONFIG_SND_IMX_SOC
@@ -38,9 +40,6 @@ obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
 endif
 
-# Support for CMOS sensor interface
-obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
-
 # i.MX1 based machines
 obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
 obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
@@ -60,13 +59,11 @@ obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
 obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
 obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
 obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
-obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
 obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
 obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
 obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
 obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
-obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
 obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o
 
 # i.MX31 based machines
@@ -109,8 +106,8 @@ obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
 endif
 obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
 
-obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
 obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
+obj-$(CONFIG_SOC_IMX51) += mach-imx51.o
 obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
 
 obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c
index 7f739be3de2c..37c307a8d896 100644
--- a/arch/arm/mach-imx/clk-imx1.c
+++ b/arch/arm/mach-imx/clk-imx1.c
@@ -15,100 +15,103 @@
  * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
  */
 
-#include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/clk.h>
-#include <linux/io.h>
 #include <linux/clkdev.h>
+#include <linux/clk-provider.h>
 #include <linux/err.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <dt-bindings/clock/imx1-clock.h>
 
 #include "clk.h"
 #include "common.h"
 #include "hardware.h"
 
-/* CCM register addresses */
-#define IO_ADDR_CCM(off)        (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
-
-#define CCM_CSCR        IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0      IO_ADDR_CCM(0x4)
-#define CCM_SPCTL0      IO_ADDR_CCM(0xc)
-#define CCM_PCDR        IO_ADDR_CCM(0x20)
-
-/* SCM register addresses */
-#define IO_ADDR_SCM(off)        (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
-
-#define SCM_GCCR        IO_ADDR_SCM(0xc)
-
 static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
 static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
                                        "prem", "fclk", };
 
-enum imx1_clks {
-        dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, mpll_gate,
-        spll, spll_gate, mcu, fclk, hclk, clk48m, per1, per2, per3, clko,
-        uart3_gate, ssi2_gate, brom_gate, dma_gate, csi_gate, mma_gate,
-        usbd_gate, clk_max
-};
+static struct clk *clk[IMX1_CLK_MAX];
+static struct clk_onecell_data clk_data;
 
-static struct clk *clk[clk_max];
+static void __iomem *ccm __initdata;
+#define CCM_CSCR        (ccm + 0x0000)
+#define CCM_MPCTL0      (ccm + 0x0004)
+#define CCM_SPCTL0      (ccm + 0x000c)
+#define CCM_PCDR        (ccm + 0x0020)
+#define SCM_GCCR        (ccm + 0x0810)
 
-int __init mx1_clocks_init(unsigned long fref)
+static void __init _mx1_clocks_init(unsigned long fref)
 {
-        int i;
+        clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+        clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref);
+        clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);
+        clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
+        clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
+        clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks));
+        clk[IMX1_CLK_MPLL] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
+        clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
+        clk[IMX1_CLK_SPLL] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
+        clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
+        clk[IMX1_CLK_MCU] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
+        clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
+        clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
+        clk[IMX1_CLK_CLK48M] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
+        clk[IMX1_CLK_PER1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
+        clk[IMX1_CLK_PER2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
+        clk[IMX1_CLK_PER3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
+        clk[IMX1_CLK_CLKO] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
+        clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
+        clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
+        clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
+        clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
+        clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
+        clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
+        clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
+
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
+}
 
-        clk[dummy] = imx_clk_fixed("dummy", 0);
-        clk[clk32] = imx_clk_fixed("clk32", fref);
-        clk[clk16m_ext] = imx_clk_fixed("clk16m_ext", 16000000);
-        clk[clk16m] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
-        clk[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
-        clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks,
-                        ARRAY_SIZE(prem_sel_clks));
-        clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
-        clk[mpll_gate] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
-        clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
-        clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
-        clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
-        clk[fclk] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
-        clk[hclk] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
-        clk[clk48m] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
-        clk[per1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
-        clk[per2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
-        clk[per3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
-        clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks,
-                        ARRAY_SIZE(clko_sel_clks));
-        clk[uart3_gate] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
-        clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
-        clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
-        clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
-        clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
-        clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
-        clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
+int __init mx1_clocks_init(unsigned long fref)
+{
+        ccm = MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR);
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("imx1 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+        _mx1_clocks_init(fref);
 
-        clk_register_clkdev(clk[dma_gate], "ahb", "imx1-dma");
-        clk_register_clkdev(clk[hclk], "ipg", "imx1-dma");
-        clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[per1], "per", "imx1-uart.0");
-        clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.0");
-        clk_register_clkdev(clk[per1], "per", "imx1-uart.1");
-        clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1");
-        clk_register_clkdev(clk[per1], "per", "imx1-uart.2");
-        clk_register_clkdev(clk[uart3_gate], "ipg", "imx1-uart.2");
-        clk_register_clkdev(clk[hclk], NULL, "imx1-i2c.0");
-        clk_register_clkdev(clk[per2], "per", "imx1-cspi.0");
-        clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0");
-        clk_register_clkdev(clk[per2], "per", "imx1-cspi.1");
-        clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1");
-        clk_register_clkdev(clk[per2], "per", "imx1-fb.0");
-        clk_register_clkdev(clk[dummy], "ipg", "imx1-fb.0");
-        clk_register_clkdev(clk[dummy], "ahb", "imx1-fb.0");
+        clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[IMX1_CLK_DMA_GATE], "ahb", "imx1-dma");
+        clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma");
+        clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.0");
+        clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.0");
+        clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.1");
+        clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.1");
+        clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.2");
+        clk_register_clkdev(clk[IMX1_CLK_UART3_GATE], "ipg", "imx1-uart.2");
+        clk_register_clkdev(clk[IMX1_CLK_HCLK], NULL, "imx1-i2c.0");
+        clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.0");
+        clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.0");
+        clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.1");
+        clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.1");
+        clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-fb.0");
+        clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0");
+        clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0");
 
         mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);
 
         return 0;
 }
+
+static void __init mx1_clocks_init_dt(struct device_node *np)
+{
+        ccm = of_iomap(np, 0);
+        BUG_ON(!ccm);
+
+        _mx1_clocks_init(32768);
+
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+CLK_OF_DECLARE(imx1_ccm, "fsl,imx1-ccm", mx1_clocks_init_dt);
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index bdc2e4630a08..4b4c75339aa6 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -7,178 +7,165 @@
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
  * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
  */
 
 #include <linux/clk.h>
-#include <linux/clkdev.h>
 #include <linux/clk-provider.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/err.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <dt-bindings/clock/imx21-clock.h>
 
 #include "clk.h"
 #include "common.h"
 #include "hardware.h"
 
-#define IO_ADDR_CCM(off)        (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
+static void __iomem *ccm __initdata;
 
 /* Register offsets */
-#define CCM_CSCR                IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0              IO_ADDR_CCM(0x4)
-#define CCM_MPCTL1              IO_ADDR_CCM(0x8)
-#define CCM_SPCTL0              IO_ADDR_CCM(0xc)
-#define CCM_SPCTL1              IO_ADDR_CCM(0x10)
-#define CCM_OSC26MCTL           IO_ADDR_CCM(0x14)
-#define CCM_PCDR0               IO_ADDR_CCM(0x18)
-#define CCM_PCDR1               IO_ADDR_CCM(0x1c)
-#define CCM_PCCR0               IO_ADDR_CCM(0x20)
-#define CCM_PCCR1               IO_ADDR_CCM(0x24)
-#define CCM_CCSR                IO_ADDR_CCM(0x28)
-#define CCM_PMCTL               IO_ADDR_CCM(0x2c)
-#define CCM_PMCOUNT             IO_ADDR_CCM(0x30)
-#define CCM_WKGDCTL             IO_ADDR_CCM(0x34)
-
-static const char *mpll_sel_clks[] = { "fpm", "ckih", };
-static const char *spll_sel_clks[] = { "fpm", "ckih", };
-
-enum imx21_clks {
-        ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
-        per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
-        uart4_ipg_gate, gpt1_ipg_gate, gpt2_ipg_gate, gpt3_ipg_gate,
-        pwm_ipg_gate, sdhc1_ipg_gate, sdhc2_ipg_gate, lcdc_ipg_gate,
-        lcdc_hclk_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate,
-        per4_gate, csi_hclk_gate, usb_div, usb_gate, usb_hclk_gate, ssi1_gate,
-        ssi2_gate, nfc_div, nfc_gate, dma_gate, dma_hclk_gate, brom_gate,
-        emma_gate, emma_hclk_gate, slcdc_gate, slcdc_hclk_gate, wdog_gate,
-        gpio_gate, i2c_gate, kpp_gate, owire_gate, rtc_gate, clk_max
-};
-
-static struct clk *clk[clk_max];
+#define CCM_CSCR        (ccm + 0x00)
+#define CCM_MPCTL0      (ccm + 0x04)
+#define CCM_SPCTL0      (ccm + 0x0c)
+#define CCM_PCDR0       (ccm + 0x18)
+#define CCM_PCDR1       (ccm + 0x1c)
+#define CCM_PCCR0       (ccm + 0x20)
+#define CCM_PCCR1       (ccm + 0x24)
+
+static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
+static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
+static const char *spll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
+static const char *ssi_sel_clks[] = { "spll_gate", "mpll_gate", };
+
+static struct clk *clk[IMX21_CLK_MAX];
+static struct clk_onecell_data clk_data;
+
+static void __init _mx21_clocks_init(unsigned long lref, unsigned long href)
+{
+        BUG_ON(!ccm);
+
+        clk[IMX21_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+        clk[IMX21_CLK_CKIL] = imx_obtain_fixed_clock("ckil", lref);
+        clk[IMX21_CLK_CKIH] = imx_obtain_fixed_clock("ckih", href);
+        clk[IMX21_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
+        clk[IMX21_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);
+
+        clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
+        clk[IMX21_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
+        clk[IMX21_CLK_FPM_GATE] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2);
+        clk[IMX21_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
+        clk[IMX21_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
+        clk[IMX21_CLK_IPG] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
+        clk[IMX21_CLK_HCLK] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
+        clk[IMX21_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
+        clk[IMX21_CLK_SPLL_SEL] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks));
+        clk[IMX21_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 19, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
+        clk[IMX21_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 20, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
+        clk[IMX21_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3);
+        clk[IMX21_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3);
+
+        clk[IMX21_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
+
+        clk[IMX21_CLK_SPLL] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
+
+        clk[IMX21_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4);
+        clk[IMX21_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
+        clk[IMX21_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
+
+        clk[IMX21_CLK_PER1] = imx_clk_divider("per1", "mpll_gate", CCM_PCDR1, 0, 6);
+        clk[IMX21_CLK_PER2] = imx_clk_divider("per2", "mpll_gate", CCM_PCDR1, 8, 6);
+        clk[IMX21_CLK_PER3] = imx_clk_divider("per3", "mpll_gate", CCM_PCDR1, 16, 6);
+        clk[IMX21_CLK_PER4] = imx_clk_divider("per4", "mpll_gate", CCM_PCDR1, 24, 6);
+
+        clk[IMX21_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
+        clk[IMX21_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
+        clk[IMX21_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
+        clk[IMX21_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
+        clk[IMX21_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
+        clk[IMX21_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
+        clk[IMX21_CLK_SSI1_GATE] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
+        clk[IMX21_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
+        clk[IMX21_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
+        clk[IMX21_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
+        clk[IMX21_CLK_GPIO_GATE] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
+        clk[IMX21_CLK_I2C_GATE] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
+        clk[IMX21_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
+        clk[IMX21_CLK_USB_GATE] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
+        clk[IMX21_CLK_EMMA_GATE] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
+        clk[IMX21_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16);
+        clk[IMX21_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17);
+        clk[IMX21_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
+        clk[IMX21_CLK_NFC_GATE] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
+        clk[IMX21_CLK_SLCDC_HCLK_GATE] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
+        clk[IMX21_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
+        clk[IMX21_CLK_BMI_GATE] = imx_clk_gate("bmi_gate", "hclk", CCM_PCCR0, 23);
+        clk[IMX21_CLK_USB_HCLK_GATE] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
+        clk[IMX21_CLK_SLCDC_GATE] = imx_clk_gate("slcdc_gate", "hclk", CCM_PCCR0, 25);
+        clk[IMX21_CLK_LCDC_HCLK_GATE] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
+        clk[IMX21_CLK_EMMA_HCLK_GATE] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
+        clk[IMX21_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
+        clk[IMX21_CLK_DMA_HCLK_GATE] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
+        clk[IMX21_CLK_CSI_HCLK_GATE] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
+
+        clk[IMX21_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
+        clk[IMX21_CLK_WDOG_GATE] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
+        clk[IMX21_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
+        clk[IMX21_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
+        clk[IMX21_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
+        clk[IMX21_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
+        clk[IMX21_CLK_RTC_GATE] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
+        clk[IMX21_CLK_KPP_GATE] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
+        clk[IMX21_CLK_OWIRE_GATE] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
+
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
+}
 
-/*
- * must be called very early to get information about the
- * available clock rate when the timer framework starts
- */
 int __init mx21_clocks_init(unsigned long lref, unsigned long href)
 {
-        int i;
-
-        clk[ckil] = imx_clk_fixed("ckil", lref);
-        clk[ckih] = imx_clk_fixed("ckih", href);
-        clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
-        clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
-                        ARRAY_SIZE(mpll_sel_clks));
-        clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
-                        ARRAY_SIZE(spll_sel_clks));
-        clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
-        clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
-        clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 29, 3);
-        clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
-        clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
-        clk[per1] = imx_clk_divider("per1", "mpll", CCM_PCDR1, 0, 6);
-        clk[per2] = imx_clk_divider("per2", "mpll", CCM_PCDR1, 8, 6);
-        clk[per3] = imx_clk_divider("per3", "mpll", CCM_PCDR1, 16, 6);
-        clk[per4] = imx_clk_divider("per4", "mpll", CCM_PCDR1, 24, 6);
-        clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
-        clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
-        clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
-        clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
-        clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
-        clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
-        clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
-        clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
-        clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
-        clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
-        clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
-        clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
-        clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
-        clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
-        clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
-        clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
-        clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
-        clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 26, 3);
-        clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
-        clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
-        clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
-        clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
-        clk[nfc_div] = imx_clk_divider("nfc_div", "ipg", CCM_PCDR0, 12, 4);
-        clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
-        clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
-        clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
-        clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
-        clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
-        clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
-        clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "ipg", CCM_PCCR0, 25);
-        clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
-        clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
-        clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
-        clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
-        clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
-        clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
-        clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
-
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX21 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
-
-        clk_register_clkdev(clk[per1], "per1", NULL);
-        clk_register_clkdev(clk[per2], "per2", NULL);
-        clk_register_clkdev(clk[per3], "per3", NULL);
-        clk_register_clkdev(clk[per4], "per4", NULL);
-        clk_register_clkdev(clk[per1], "per", "imx21-uart.0");
-        clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
-        clk_register_clkdev(clk[per1], "per", "imx21-uart.1");
-        clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
-        clk_register_clkdev(clk[per1], "per", "imx21-uart.2");
-        clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
-        clk_register_clkdev(clk[per1], "per", "imx21-uart.3");
-        clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
-        clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
-        clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
-        clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
-        clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
-        clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
-        clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
-        clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
-        clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1");
-        clk_register_clkdev(clk[per2], "per", "imx21-cspi.2");
-        clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2");
-        clk_register_clkdev(clk[per3], "per", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx21-fb.0");
-        clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");
-        clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");
-        clk_register_clkdev(clk[nfc_gate], NULL, "imx21-nand.0");
-        clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx21-dma");
-        clk_register_clkdev(clk[dma_gate], "ipg", "imx21-dma");
-        clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[i2c_gate], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[kpp_gate], NULL, "mxc-keypad");
-        clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
-        clk_register_clkdev(clk[brom_gate], "brom", NULL);
-        clk_register_clkdev(clk[emma_gate], "emma", NULL);
-        clk_register_clkdev(clk[slcdc_gate], "slcdc", NULL);
-        clk_register_clkdev(clk[gpio_gate], "gpio", NULL);
-        clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
-        clk_register_clkdev(clk[csi_hclk_gate], "csi", NULL);
-        clk_register_clkdev(clk[ssi1_gate], "ssi1", NULL);
-        clk_register_clkdev(clk[ssi2_gate], "ssi2", NULL);
-        clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
-        clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
+        ccm = ioremap(MX21_CCM_BASE_ADDR, SZ_2K);
+
+        _mx21_clocks_init(lref, href);
+
+        clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.0");
+        clk_register_clkdev(clk[IMX21_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
+        clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.1");
+        clk_register_clkdev(clk[IMX21_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
+        clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.2");
+        clk_register_clkdev(clk[IMX21_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
+        clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.3");
+        clk_register_clkdev(clk[IMX21_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
+        clk_register_clkdev(clk[IMX21_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.0");
+        clk_register_clkdev(clk[IMX21_CLK_CSPI1_IPG_GATE], "ipg", "imx21-cspi.0");
+        clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.1");
+        clk_register_clkdev(clk[IMX21_CLK_CSPI2_IPG_GATE], "ipg", "imx21-cspi.1");
+        clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.2");
+        clk_register_clkdev(clk[IMX21_CLK_CSPI3_IPG_GATE], "ipg", "imx21-cspi.2");
+        clk_register_clkdev(clk[IMX21_CLK_PER3], "per", "imx21-fb.0");
+        clk_register_clkdev(clk[IMX21_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");
+        clk_register_clkdev(clk[IMX21_CLK_LCDC_HCLK_GATE], "ahb", "imx21-fb.0");
+        clk_register_clkdev(clk[IMX21_CLK_USB_GATE], "per", "imx21-hcd.0");
+        clk_register_clkdev(clk[IMX21_CLK_USB_HCLK_GATE], "ahb", "imx21-hcd.0");
+        clk_register_clkdev(clk[IMX21_CLK_NFC_GATE], NULL, "imx21-nand.0");
+        clk_register_clkdev(clk[IMX21_CLK_DMA_HCLK_GATE], "ahb", "imx21-dma");
+        clk_register_clkdev(clk[IMX21_CLK_DMA_GATE], "ipg", "imx21-dma");
+        clk_register_clkdev(clk[IMX21_CLK_WDOG_GATE], NULL, "imx2-wdt.0");
+        clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0");
+        clk_register_clkdev(clk[IMX21_CLK_OWIRE_GATE], NULL, "mxc_w1.0");
 
         mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);
 
         return 0;
 }
+
+static void __init mx21_clocks_init_dt(struct device_node *np)
+{
+        ccm = of_iomap(np, 0);
+
+        _mx21_clocks_init(32768, 26000000);
+
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+CLK_OF_DECLARE(imx27_ccm, "fsl,imx21-ccm", mx21_clocks_init_dt);
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index ae578c096ad8..59c0c8558c6b 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -32,8 +32,6 @@
 #include "hardware.h"
 #include "mx25.h"
 
-#define CRM_BASE        MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
-
 #define CCM_MPCTL       0x00
 #define CCM_UPCTL       0x04
 #define CCM_CCTL        0x08
@@ -56,7 +54,7 @@
 #define CCM_LTR3        0x4c
 #define CCM_MCR         0x64
 
-#define ccm(x)  (CRM_BASE + (x))
+#define ccm(x)  (ccm_base + (x))
 
 static struct clk_onecell_data clk_data;
 
@@ -91,9 +89,10 @@ enum mx25_clks {
 
 static struct clk *clk[clk_max];
 
-static int __init __mx25_clocks_init(unsigned long osc_rate)
+static int __init __mx25_clocks_init(unsigned long osc_rate,
+                                     void __iomem *ccm_base)
 {
-        int i;
+        BUG_ON(!ccm_base);
 
         clk[dummy] = imx_clk_fixed("dummy", 0);
         clk[osc] = imx_clk_fixed("osc", osc_rate);
@@ -224,19 +223,13 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
         /* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */
         clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX25 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
         clk_prepare_enable(clk[emi_ahb]);
 
         /* Clock source for gpt must be derived from AHB */
         clk_set_parent(clk[per5_sel], clk[ahb]);
 
-        clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
-
         /*
          * Let's initially set up CLKO parent as ipg, since this configuration
          * is used on some imx25 board designs to clock the audio codec.
@@ -248,8 +241,14 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
 
 int __init mx25_clocks_init(void)
 {
-        __mx25_clocks_init(24000000);
+        void __iomem *ccm;
 
+        ccm = ioremap(MX25_CRM_BASE_ADDR, SZ_16K);
+
+        __mx25_clocks_init(24000000, ccm);
+
+        clk_register_clkdev(clk[gpt1_ipg], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
         /* i.mx25 has the i.mx21 type uart */
         clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
         clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
@@ -314,29 +313,27 @@ int __init mx25_clocks_init(void)
         return 0;
 }
 
-int __init mx25_clocks_init_dt(void)
+static void __init mx25_clocks_init_dt(struct device_node *np)
 {
-        struct device_node *np;
+        struct device_node *refnp;
         unsigned long osc_rate = 24000000;
+        void __iomem *ccm;
 
         /* retrieve the freqency of fixed clocks from device tree */
-        for_each_compatible_node(np, NULL, "fixed-clock") {
+        for_each_compatible_node(refnp, NULL, "fixed-clock") {
                 u32 rate;
-                if (of_property_read_u32(np, "clock-frequency", &rate))
+                if (of_property_read_u32(refnp, "clock-frequency", &rate))
                         continue;
 
-                if (of_device_is_compatible(np, "fsl,imx-osc"))
+                if (of_device_is_compatible(refnp, "fsl,imx-osc"))
                         osc_rate = rate;
         }
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
+        ccm = of_iomap(np, 0);
+        __mx25_clocks_init(osc_rate, ccm);
+
         clk_data.clks = clk;
         clk_data.clk_num = ARRAY_SIZE(clk);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-
-        __mx25_clocks_init(osc_rate);
-
-        mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt"));
-
-        return 0;
 }
+CLK_OF_DECLARE(imx25_ccm, "fsl,imx25-ccm", mx25_clocks_init_dt);
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 317a662626d6..ab6349ec23b9 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -1,61 +1,36 @@
 #include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/module.h>
+#include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 #include <linux/err.h>
-#include <linux/clk-provider.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
+#include <dt-bindings/clock/imx27-clock.h>
 
 #include "clk.h"
 #include "common.h"
 #include "hardware.h"
 
-#define IO_ADDR_CCM(off)        (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
+static void __iomem *ccm __initdata;
 
 /* Register offsets */
-#define CCM_CSCR                IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0              IO_ADDR_CCM(0x4)
-#define CCM_MPCTL1              IO_ADDR_CCM(0x8)
-#define CCM_SPCTL0              IO_ADDR_CCM(0xc)
-#define CCM_SPCTL1              IO_ADDR_CCM(0x10)
-#define CCM_OSC26MCTL           IO_ADDR_CCM(0x14)
-#define CCM_PCDR0               IO_ADDR_CCM(0x18)
-#define CCM_PCDR1               IO_ADDR_CCM(0x1c)
-#define CCM_PCCR0               IO_ADDR_CCM(0x20)
-#define CCM_PCCR1               IO_ADDR_CCM(0x24)
-#define CCM_CCSR                IO_ADDR_CCM(0x28)
-#define CCM_PMCTL               IO_ADDR_CCM(0x2c)
-#define CCM_PMCOUNT             IO_ADDR_CCM(0x30)
-#define CCM_WKGDCTL             IO_ADDR_CCM(0x34)
-
-#define CCM_CSCR_UPDATE_DIS     (1 << 31)
-#define CCM_CSCR_SSI2           (1 << 23)
-#define CCM_CSCR_SSI1           (1 << 22)
-#define CCM_CSCR_VPU            (1 << 21)
-#define CCM_CSCR_MSHC           (1 << 20)
-#define CCM_CSCR_SPLLRES        (1 << 19)
-#define CCM_CSCR_MPLLRES        (1 << 18)
-#define CCM_CSCR_SP             (1 << 17)
-#define CCM_CSCR_MCU            (1 << 16)
-#define CCM_CSCR_OSC26MDIV      (1 << 4)
-#define CCM_CSCR_OSC26M         (1 << 3)
-#define CCM_CSCR_FPM            (1 << 2)
-#define CCM_CSCR_SPEN           (1 << 1)
-#define CCM_CSCR_MPEN           (1 << 0)
-
-/* i.MX27 TO 2+ */
-#define CCM_CSCR_ARM_SRC        (1 << 15)
-
-#define CCM_SPCTL1_LF           (1 << 15)
-#define CCM_SPCTL1_BRMO         (1 << 6)
+#define CCM_CSCR                (ccm + 0x00)
+#define CCM_MPCTL0              (ccm + 0x04)
+#define CCM_MPCTL1              (ccm + 0x08)
+#define CCM_SPCTL0              (ccm + 0x0c)
+#define CCM_SPCTL1              (ccm + 0x10)
+#define CCM_PCDR0               (ccm + 0x18)
+#define CCM_PCDR1               (ccm + 0x1c)
+#define CCM_PCCR0               (ccm + 0x20)
+#define CCM_PCCR1               (ccm + 0x24)
+#define CCM_CCSR                (ccm + 0x28)
 
 static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
 static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
 static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", };
-static const char *mpll_osc_sel_clks[] = { "ckih", "ckih_div1p5", };
+static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
 static const char *clko_sel_clks[] = {
-        "ckil", "fpm", "ckih", "ckih",
-        "ckih", "mpll", "spll", "cpu_div",
+        "ckil", "fpm", "ckih_gate", "ckih_gate",
+        "ckih_gate", "mpll", "spll", "cpu_div",
         "ahb", "ipg", "per1_div", "per2_div",
         "per3_div", "per4_div", "ssi1_div", "ssi2_div",
         "nfc_div", "mshc_div", "vpu_div", "60m",
@@ -64,239 +39,220 @@ static const char *clko_sel_clks[] = {
 
 static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
 
-enum mx27_clks {
-        dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
-        per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel,
-        clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div,
-        clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate,
-        sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate,
-        rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate,
-        kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate,
-        gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate,
-        gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate,
-        emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate,
-        cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate,
-        vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate,
-        usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate,
-        vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
-        csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
-        uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
-        uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
-        mpll_sel, spll_gate, mshc_div, rtic_ipg_gate, mshc_ipg_gate,
-        rtic_ahb_gate, mshc_baud_gate, clk_max
-};
-
-static struct clk *clk[clk_max];
+static struct clk *clk[IMX27_CLK_MAX];
 static struct clk_onecell_data clk_data;
 
-int __init mx27_clocks_init(unsigned long fref)
+static void __init _mx27_clocks_init(unsigned long fref)
 {
-        int i;
-        struct device_node *np;
-
-        clk[dummy] = imx_clk_fixed("dummy", 0);
-        clk[ckih] = imx_clk_fixed("ckih", fref);
-        clk[ckil] = imx_clk_fixed("ckil", 32768);
-        clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
-        clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
+        BUG_ON(!ccm);
 
-        clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1,
-                        mpll_osc_sel_clks,
-                        ARRAY_SIZE(mpll_osc_sel_clks));
-        clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
-                        ARRAY_SIZE(mpll_sel_clks));
-        clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
-        clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
-        clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
-        clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
+        clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+        clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref);
+        clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768);
+        clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
+        clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);
+        clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
+        clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
+        clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
+        clk[IMX27_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
+        clk[IMX27_CLK_SPLL] = imx_clk_pllv1("spll", "ckih_gate", CCM_SPCTL0);
+        clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
+        clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
 
         if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
-                clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
-                clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
+                clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
+                clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
         } else {
-                clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
-                clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
+                clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
+                clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
         }
 
-        clk[mshc_div] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
-        clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
-        clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
-        clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
-        clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
-        clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
-        clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
-        clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
-        clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
-        clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
-        clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
+        clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
+        clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
+        clk[IMX27_CLK_PER1_DIV] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
+        clk[IMX27_CLK_PER2_DIV] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
+        clk[IMX27_CLK_PER3_DIV] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
+        clk[IMX27_CLK_PER4_DIV] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
+        clk[IMX27_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
+        clk[IMX27_CLK_VPU_DIV] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
+        clk[IMX27_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
+        clk[IMX27_CLK_CPU_SEL] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
+        clk[IMX27_CLK_CLKO_SEL] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
+
         if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
-                clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
+                clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
         else
-                clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
-        clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
-        clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
-        clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
-        clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
-        clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
-        clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
-        clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
-        clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
-        clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
-        clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
-        clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
-        clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
-        clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
-        clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
-        clk[rtic_ipg_gate] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
-        clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
-        clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
-        clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
-        clk[mshc_ipg_gate] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
-        clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
-        clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
-        clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
-        clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
-        clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
-        clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
-        clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
-        clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
-        clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
-        clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
-        clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
-        clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
-        clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
-        clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
-        clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
-        clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
-        clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
-        clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
-        clk[mshc_baud_gate] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
-        clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1,  3);
-        clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1,  4);
-        clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1,  5);
-        clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1,  6);
-        clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1,  7);
-        clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1,  8);
-        clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1,  9);
-        clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
-        clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
-        clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
-        clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
-        clk[rtic_ahb_gate] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
-        clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
-        clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
-        clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
-        clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
-        clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
-        clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
-        clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
-        clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
-        clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
-        clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
-        clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
-        clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
-        clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
-        clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
-        clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
-        clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
-        clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
+                clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX27 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+        clk[IMX27_CLK_CLKO_DIV] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
+        clk[IMX27_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
+        clk[IMX27_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
+        clk[IMX27_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
+        clk[IMX27_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
+        clk[IMX27_CLK_CLKO_EN] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
+        clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
+        clk[IMX27_CLK_SSI1_IPG_GATE] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
+        clk[IMX27_CLK_SLCDC_IPG_GATE] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
+        clk[IMX27_CLK_SDHC3_IPG_GATE] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
+        clk[IMX27_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
+        clk[IMX27_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
+        clk[IMX27_CLK_SCC_IPG_GATE] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
+        clk[IMX27_CLK_SAHARA_IPG_GATE] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
+        clk[IMX27_CLK_RTIC_IPG_GATE] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
+        clk[IMX27_CLK_RTC_IPG_GATE] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
+        clk[IMX27_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
+        clk[IMX27_CLK_OWIRE_IPG_GATE] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
+        clk[IMX27_CLK_MSHC_IPG_GATE] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
+        clk[IMX27_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
+        clk[IMX27_CLK_KPP_IPG_GATE] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
+        clk[IMX27_CLK_IIM_IPG_GATE] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
+        clk[IMX27_CLK_I2C2_IPG_GATE] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
+        clk[IMX27_CLK_I2C1_IPG_GATE] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
+        clk[IMX27_CLK_GPT6_IPG_GATE] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
+        clk[IMX27_CLK_GPT5_IPG_GATE] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
+        clk[IMX27_CLK_GPT4_IPG_GATE] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
+        clk[IMX27_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
+        clk[IMX27_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
+        clk[IMX27_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
+        clk[IMX27_CLK_GPIO_IPG_GATE] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
+        clk[IMX27_CLK_FEC_IPG_GATE] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
+        clk[IMX27_CLK_EMMA_IPG_GATE] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
+        clk[IMX27_CLK_DMA_IPG_GATE] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
+        clk[IMX27_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
+        clk[IMX27_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
+        clk[IMX27_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
+        clk[IMX27_CLK_MSHC_BAUD_GATE] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
+        clk[IMX27_CLK_NFC_BAUD_GATE] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1,  3);
+        clk[IMX27_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1,  4);
+        clk[IMX27_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1,  5);
+        clk[IMX27_CLK_VPU_BAUD_GATE] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1,  6);
+        clk[IMX27_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1,  7);
+        clk[IMX27_CLK_PER3_GATE] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1,  8);
+        clk[IMX27_CLK_PER2_GATE] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1,  9);
+        clk[IMX27_CLK_PER1_GATE] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
+        clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
+        clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
+        clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
+        clk[IMX27_CLK_RTIC_AHB_GATE] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
+        clk[IMX27_CLK_LCDC_AHB_GATE] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
+        clk[IMX27_CLK_VPU_AHB_GATE] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
+        clk[IMX27_CLK_FEC_AHB_GATE] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
+        clk[IMX27_CLK_EMMA_AHB_GATE] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
+        clk[IMX27_CLK_EMI_AHB_GATE] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
+        clk[IMX27_CLK_DMA_AHB_GATE] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
+        clk[IMX27_CLK_CSI_AHB_GATE] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
+        clk[IMX27_CLK_BROM_AHB_GATE] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
+        clk[IMX27_CLK_ATA_AHB_GATE] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
+        clk[IMX27_CLK_WDOG_IPG_GATE] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
+        clk[IMX27_CLK_USB_IPG_GATE] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
+        clk[IMX27_CLK_UART6_IPG_GATE] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
+        clk[IMX27_CLK_UART5_IPG_GATE] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
+        clk[IMX27_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
+        clk[IMX27_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
+        clk[IMX27_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
+        clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
-        if (np) {
-                clk_data.clks = clk;
-                clk_data.clk_num = ARRAY_SIZE(clk);
-                of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-        }
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
-        clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
-        clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1");
-        clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2");
-        clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3");
-        clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4");
-        clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5");
-        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5");
-        clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
-        clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
-        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
-        clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1");
-        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2");
-        clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2");
-        clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0");
-        clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0");
-        clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1");
-        clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1");
-        clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2");
-        clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2");
-        clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
-        clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
-        clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0");
-        clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0");
-        clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
-        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "imx-udc-mx27");
-        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "imx-udc-mx27");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
-        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0");
-        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
-        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1");
-        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1");
-        clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
-        clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2");
-        clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
-        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
-        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
-        clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0");
-        clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
-        clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
-        clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma");
-        clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma");
-        clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
-        clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0");
-        clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx21-i2c.1");
-        clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0");
-        clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad");
-        clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "imx27-camera.0");
-        clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0");
-        clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
-        clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
-        clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
+        clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0");
 
-        mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
-
-        clk_prepare_enable(clk[emi_ahb_gate]);
+        clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
 
         imx_print_silicon_rev("i.MX27", mx27_revision());
+}
+
+int __init mx27_clocks_init(unsigned long fref)
+{
+        ccm = ioremap(MX27_CCM_BASE_ADDR, SZ_4K);
+
+        _mx27_clocks_init(fref);
+
+        clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
+        clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0");
+        clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
+        clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1");
+        clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
+        clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2");
+        clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
+        clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3");
+        clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
+        clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4");
+        clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5");
+        clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5");
+        clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0");
+        clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0");
+        clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1");
+        clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1");
+        clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2");
+        clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2");
+        clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.0");
+        clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0");
+        clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.1");
+        clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1");
+        clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.2");
+        clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2");
+        clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0");
+        clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");
+        clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0");
+        clk_register_clkdev(clk[IMX27_CLK_CSI_AHB_GATE], "ahb", "imx27-camera.0");
+        clk_register_clkdev(clk[IMX27_CLK_PER4_GATE], "per", "imx27-camera.0");
+        clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "imx-udc-mx27");
+        clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27");
+        clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "imx-udc-mx27");
+        clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.0");
+        clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0");
+        clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.0");
+        clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.1");
+        clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1");
+        clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.1");
+        clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.2");
+        clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2");
+        clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.2");
+        clk_register_clkdev(clk[IMX27_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
+        clk_register_clkdev(clk[IMX27_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
+        clk_register_clkdev(clk[IMX27_CLK_NFC_BAUD_GATE], NULL, "imx27-nand.0");
+        clk_register_clkdev(clk[IMX27_CLK_VPU_BAUD_GATE], "per", "coda-imx27.0");
+        clk_register_clkdev(clk[IMX27_CLK_VPU_AHB_GATE], "ahb", "coda-imx27.0");
+        clk_register_clkdev(clk[IMX27_CLK_DMA_AHB_GATE], "ahb", "imx27-dma");
+        clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma");
+        clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0");
+        clk_register_clkdev(clk[IMX27_CLK_FEC_AHB_GATE], "ahb", "imx27-fec.0");
+        clk_register_clkdev(clk[IMX27_CLK_WDOG_IPG_GATE], NULL, "imx2-wdt.0");
+        clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0");
+        clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1");
+        clk_register_clkdev(clk[IMX27_CLK_OWIRE_IPG_GATE], NULL, "mxc_w1.0");
+        clk_register_clkdev(clk[IMX27_CLK_KPP_IPG_GATE], NULL, "imx-keypad");
+        clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "emma-ahb", "imx27-camera.0");
+        clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0");
+        clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0");
+        clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0");
+
+        mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
 
         return 0;
 }
 
-int __init mx27_clocks_init_dt(void)
+static void __init mx27_clocks_init_dt(struct device_node *np)
 {
-        struct device_node *np;
+        struct device_node *refnp;
         u32 fref = 26000000; /* default */
 
-        for_each_compatible_node(np, NULL, "fixed-clock") {
-                if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
+        for_each_compatible_node(refnp, NULL, "fixed-clock") {
+                if (!of_device_is_compatible(refnp, "fsl,imx-osc26m"))
                         continue;
 
-                if (!of_property_read_u32(np, "clock-frequency", &fref))
+                if (!of_property_read_u32(refnp, "clock-frequency", &fref))
                         break;
         }
 
-        return mx27_clocks_init(fref);
+        ccm = of_iomap(np, 0);
+
+        _mx27_clocks_init(fref);
+
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 }
+CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm", mx27_clocks_init_dt);
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index 4a9de0835eb1..286ef422cebc 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -51,7 +51,6 @@ static struct clk_onecell_data clk_data;
 int __init mx31_clocks_init(unsigned long fref)
 {
         void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
-        int i;
         struct device_node *np;
 
         clk[dummy] = imx_clk_fixed("dummy", 0);
@@ -114,10 +113,7 @@ int __init mx31_clocks_init(unsigned long fref)
         clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
         clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("imx31 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
         np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
 
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 71c86a2f856d..a0d2b57fd376 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -75,7 +75,6 @@ int __init mx35_clocks_init(void)
         u32 pdr0, consumer_sel, hsp_sel;
         struct arm_ahb_div *aad;
         unsigned char *hsp_div;
-        u32 i;
 
         pdr0 = __raw_readl(base + MXC_CCM_PDR0);
         consumer_sel = (pdr0 >> 16) & 0xf;
@@ -200,10 +199,7 @@ int __init mx35_clocks_init(void)
         clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3,  2);
         clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3,  4);
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX35 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
         clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
         clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 21d2b111c83d..72d65214223e 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -18,11 +18,54 @@
 #include <linux/of_irq.h>
 #include <dt-bindings/clock/imx5-clock.h>
 
-#include "crm-regs-imx5.h"
 #include "clk.h"
 #include "common.h"
 #include "hardware.h"
 
+#define MX51_DPLL1_BASE         0x83f80000
+#define MX51_DPLL2_BASE         0x83f84000
+#define MX51_DPLL3_BASE         0x83f88000
+
+#define MX53_DPLL1_BASE         0x63f80000
+#define MX53_DPLL2_BASE         0x63f84000
+#define MX53_DPLL3_BASE         0x63f88000
+#define MX53_DPLL4_BASE         0x63f8c000
+
+#define MXC_CCM_CCR             (ccm_base + 0x00)
+#define MXC_CCM_CCDR            (ccm_base + 0x04)
+#define MXC_CCM_CSR             (ccm_base + 0x08)
+#define MXC_CCM_CCSR            (ccm_base + 0x0c)
+#define MXC_CCM_CACRR           (ccm_base + 0x10)
+#define MXC_CCM_CBCDR           (ccm_base + 0x14)
+#define MXC_CCM_CBCMR           (ccm_base + 0x18)
+#define MXC_CCM_CSCMR1          (ccm_base + 0x1c)
+#define MXC_CCM_CSCMR2          (ccm_base + 0x20)
+#define MXC_CCM_CSCDR1          (ccm_base + 0x24)
+#define MXC_CCM_CS1CDR          (ccm_base + 0x28)
+#define MXC_CCM_CS2CDR          (ccm_base + 0x2c)
+#define MXC_CCM_CDCDR           (ccm_base + 0x30)
+#define MXC_CCM_CHSCDR          (ccm_base + 0x34)
+#define MXC_CCM_CSCDR2          (ccm_base + 0x38)
+#define MXC_CCM_CSCDR3          (ccm_base + 0x3c)
+#define MXC_CCM_CSCDR4          (ccm_base + 0x40)
+#define MXC_CCM_CWDR            (ccm_base + 0x44)
+#define MXC_CCM_CDHIPR          (ccm_base + 0x48)
+#define MXC_CCM_CDCR            (ccm_base + 0x4c)
+#define MXC_CCM_CTOR            (ccm_base + 0x50)
+#define MXC_CCM_CLPCR           (ccm_base + 0x54)
+#define MXC_CCM_CISR            (ccm_base + 0x58)
+#define MXC_CCM_CIMR            (ccm_base + 0x5c)
+#define MXC_CCM_CCOSR           (ccm_base + 0x60)
+#define MXC_CCM_CGPR            (ccm_base + 0x64)
+#define MXC_CCM_CCGR0           (ccm_base + 0x68)
+#define MXC_CCM_CCGR1           (ccm_base + 0x6c)
+#define MXC_CCM_CCGR2           (ccm_base + 0x70)
+#define MXC_CCM_CCGR3           (ccm_base + 0x74)
+#define MXC_CCM_CCGR4           (ccm_base + 0x78)
+#define MXC_CCM_CCGR5           (ccm_base + 0x7c)
+#define MXC_CCM_CCGR6           (ccm_base + 0x80)
+#define MXC_CCM_CCGR7           (ccm_base + 0x84)
+
 /* Low-power Audio Playback Mode clock */
 static const char *lp_apm_sel[] = { "osc", };
 
@@ -86,17 +129,15 @@ static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
 static struct clk *clk[IMX5_CLK_END];
 static struct clk_onecell_data clk_data;
 
-static void __init mx5_clocks_common_init(unsigned long rate_ckil,
-                unsigned long rate_osc, unsigned long rate_ckih1,
-                unsigned long rate_ckih2)
+static void __init mx5_clocks_common_init(void __iomem *ccm_base)
 {
-        int i;
+        imx5_pm_set_ccm_base(ccm_base);
 
         clk[IMX5_CLK_DUMMY]             = imx_clk_fixed("dummy", 0);
-        clk[IMX5_CLK_CKIL]              = imx_obtain_fixed_clock("ckil", rate_ckil);
-        clk[IMX5_CLK_OSC]               = imx_obtain_fixed_clock("osc", rate_osc);
-        clk[IMX5_CLK_CKIH1]             = imx_obtain_fixed_clock("ckih1", rate_ckih1);
-        clk[IMX5_CLK_CKIH2]             = imx_obtain_fixed_clock("ckih2", rate_ckih2);
+        clk[IMX5_CLK_CKIL]              = imx_obtain_fixed_clock("ckil", 0);
+        clk[IMX5_CLK_OSC]               = imx_obtain_fixed_clock("osc", 0);
+        clk[IMX5_CLK_CKIH1]             = imx_obtain_fixed_clock("ckih1", 0);
+        clk[IMX5_CLK_CKIH2]             = imx_obtain_fixed_clock("ckih2", 0);
 
         clk[IMX5_CLK_PERIPH_APM]        = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
                                                 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
@@ -244,58 +285,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk[IMX5_CLK_SAHARA_IPG_GATE]   = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
         clk[IMX5_CLK_SATA_REF]          = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX5 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
-
-        clk_register_clkdev(clk[IMX5_CLK_GPT_HF_GATE], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[IMX5_CLK_GPT_IPG_GATE], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0");
-        clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
-        clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1");
-        clk_register_clkdev(clk[IMX5_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
-        clk_register_clkdev(clk[IMX5_CLK_UART3_PER_GATE], "per", "imx21-uart.2");
-        clk_register_clkdev(clk[IMX5_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
-        clk_register_clkdev(clk[IMX5_CLK_UART4_PER_GATE], "per", "imx21-uart.3");
-        clk_register_clkdev(clk[IMX5_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
-        clk_register_clkdev(clk[IMX5_CLK_UART5_PER_GATE], "per", "imx21-uart.4");
-        clk_register_clkdev(clk[IMX5_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
-        clk_register_clkdev(clk[IMX5_CLK_ECSPI1_PER_GATE], "per", "imx51-ecspi.0");
-        clk_register_clkdev(clk[IMX5_CLK_ECSPI1_IPG_GATE], "ipg", "imx51-ecspi.0");
-        clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1");
-        clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1");
-        clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2");
-        clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0");
-        clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.0");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.0");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.1");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.1");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.1");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.2");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.2");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.2");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "imx-udc-mx51");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "imx-udc-mx51");
-        clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "imx-udc-mx51");
-        clk_register_clkdev(clk[IMX5_CLK_NFC_GATE], NULL, "imx51-nand");
-        clk_register_clkdev(clk[IMX5_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
-        clk_register_clkdev(clk[IMX5_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
-        clk_register_clkdev(clk[IMX5_CLK_SSI3_IPG_GATE], NULL, "imx-ssi.2");
-        clk_register_clkdev(clk[IMX5_CLK_SDMA_GATE], NULL, "imx35-sdma");
         clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
-        clk_register_clkdev(clk[IMX5_CLK_IIM_GATE], "iim", NULL);
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.1");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx-keypad");
-        clk_register_clkdev(clk[IMX5_CLK_IPU_DI1_GATE], "di1", "imx-tve.0");
         clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
-        clk_register_clkdev(clk[IMX5_CLK_EPIT1_IPG_GATE], "ipg", "imx-epit.0");
-        clk_register_clkdev(clk[IMX5_CLK_EPIT1_HF_GATE], "per", "imx-epit.0");
-        clk_register_clkdev(clk[IMX5_CLK_EPIT2_IPG_GATE], "ipg", "imx-epit.1");
-        clk_register_clkdev(clk[IMX5_CLK_EPIT2_HF_GATE], "per", "imx-epit.1");
 
         /* Set SDHC parents to be PLL2 */
         clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
@@ -322,12 +313,26 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 
 static void __init mx50_clocks_init(struct device_node *np)
 {
+        void __iomem *ccm_base;
+        void __iomem *pll_base;
         unsigned long r;
-        int i;
 
-        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
-        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
-        clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
+        pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", pll_base);
+
+        pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", pll_base);
+
+        pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", pll_base);
+
+        ccm_base = of_iomap(np, 0);
+        WARN_ON(!ccm_base);
+
+        mx5_clocks_common_init(ccm_base);
 
         clk[IMX5_CLK_LP_APM]            = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
                                                 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
@@ -349,17 +354,12 @@ static void __init mx50_clocks_init(struct device_node *np)
         clk[IMX5_CLK_CKO2_PODF]         = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
         clk[IMX5_CLK_CKO2]              = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX50 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
         clk_data.clks = clk;
         clk_data.clk_num = ARRAY_SIZE(clk);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        mx5_clocks_common_init(0, 0, 0, 0);
-
         /* set SDHC root clock to 200MHZ*/
         clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
         clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
@@ -370,21 +370,32 @@ static void __init mx50_clocks_init(struct device_node *np)
 
         r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
         clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
-
-        mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt"));
 }
 CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
 
-int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
-                        unsigned long rate_ckih1, unsigned long rate_ckih2)
+static void __init mx51_clocks_init(struct device_node *np)
 {
-        int i;
+        void __iomem *ccm_base;
+        void __iomem *pll_base;
         u32 val;
-        struct device_node *np;
 
-        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
-        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
-        clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
+        pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", pll_base);
+
+        pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", pll_base);
+
+        pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", pll_base);
+
+        ccm_base = of_iomap(np, 0);
+        WARN_ON(!ccm_base);
+
+        mx5_clocks_common_init(ccm_base);
+
         clk[IMX5_CLK_LP_APM]            = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
                                                 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
         clk[IMX5_CLK_IPU_DI0_SEL]       = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
@@ -417,35 +428,12 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                                                 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
         clk[IMX5_CLK_SPDIF1_GATE]       = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX51 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
         clk_data.clks = clk;
         clk_data.clk_num = ARRAY_SIZE(clk);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
-
-        clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
-        clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
-        clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0");
-        clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.0");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx51.0");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx51.1");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.1");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx51.1");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx51.2");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.2");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx51.2");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx51.3");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.3");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx51.3");
-
         /* set the usboh3 parent to pll2_sw */
         clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
 
@@ -453,9 +441,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
         clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
 
-        /* System timer */
-        mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
-
         clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
         imx_print_silicon_rev("i.MX51", mx51_revision());
         clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
@@ -474,25 +459,35 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         val = readl(MXC_CCM_CLPCR);
         val |= 1 << 23;
         writel(val, MXC_CCM_CLPCR);
-
-        return 0;
-}
-
-static void __init mx51_clocks_init_dt(struct device_node *np)
-{
-        mx51_clocks_init(0, 0, 0, 0);
 }
-CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt);
+CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
 
 static void __init mx53_clocks_init(struct device_node *np)
 {
-        int i;
+        void __iomem *ccm_base;
+        void __iomem *pll_base;
         unsigned long r;
 
-        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
-        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
-        clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
-        clk[IMX5_CLK_PLL4_SW]           = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
+        pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", pll_base);
+
+        pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", pll_base);
+
+        pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", pll_base);
+
+        pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);
+        WARN_ON(!pll_base);
+        clk[IMX5_CLK_PLL4_SW]           = imx_clk_pllv2("pll4_sw", "osc", pll_base);
+
+        ccm_base = of_iomap(np, 0);
+        WARN_ON(!ccm_base);
+
+        mx5_clocks_common_init(ccm_base);
 
         clk[IMX5_CLK_LP_APM]            = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
                                                 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
@@ -543,33 +538,12 @@ static void __init mx53_clocks_init(struct device_node *np)
         clk[IMX5_CLK_SPDIF_XTAL_SEL]    = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
                                                 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
 
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX53 clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
         clk_data.clks = clk;
         clk_data.clk_num = ARRAY_SIZE(clk);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        mx5_clocks_common_init(0, 0, 0, 0);
-
-        clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2");
-        clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0");
-        clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx53.0");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.0");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx53.0");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx53.1");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.1");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx53.1");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx53.2");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.2");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx53.2");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx53.3");
-        clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.3");
-        clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx53.3");
-
         /* set SDHC root clock to 200MHZ*/
         clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
         clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
@@ -583,7 +557,5 @@ static void __init mx53_clocks_init(struct device_node *np)
 
         r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
         clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
-
-        mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"));
 }
 CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 8e795dea02ec..6cceb7765c14 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -19,6 +19,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <dt-bindings/clock/imx6qdl-clock.h>
 
 #include "clk.h"
 #include "common.h"
@@ -70,51 +71,16 @@ static const char *cko_sels[] = { "cko1", "cko2", };
 static const char *lvds_sels[] = {
         "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
         "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
-        "pcie_ref", "sata_ref",
+        "pcie_ref_125m", "sata_ref_100m",
 };
 
-enum mx6q_clks {
-        dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
-        pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
-        pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
-        periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
-        esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
-        gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
-        ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
-        ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
-        ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
-        usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
-        emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
-        periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
-        asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
-        gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
-        ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
-        ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
-        ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
-        usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
-        emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
-        mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
-        can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
-        esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
-        hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
-        ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
-        mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
-        gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
-        ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
-        usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
-        pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
-        ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
-        sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
-        usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
-        spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div,
-        lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, esai_ahb, clk_max
-};
-
-static struct clk *clk[clk_max];
+static struct clk *clk[IMX6QDL_CLK_END];
 static struct clk_onecell_data clk_data;
 
-static enum mx6q_clks const clks_init_on[] __initconst = {
-        mmdc_ch0_axi, rom, arm,
+static unsigned int const clks_init_on[] __initconst = {
+        IMX6QDL_CLK_MMDC_CH0_AXI,
+        IMX6QDL_CLK_ROM,
+        IMX6QDL_CLK_ARM,
 };
 
 static struct clk_div_table clk_enet_ref_table[] = {
@@ -149,10 +115,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         int i;
         int ret;
 
-        clk[dummy] = imx_clk_fixed("dummy", 0);
-        clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
-        clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
-        clk[osc] = imx_obtain_fixed_clock("osc", 0);
+        clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+        clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
+        clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
+        clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
 
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
         base = of_iomap(np, 0);
@@ -166,14 +132,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
                 video_div_table[2].div = 1;
         };
 
-        /*                   type                               name         parent_name  base     div_mask */
-        clk[pll1_sys]      = imx_clk_pllv3(IMX_PLLV3_SYS,       "pll1_sys",     "osc", base,        0x7f);
-        clk[pll2_bus]      = imx_clk_pllv3(IMX_PLLV3_GENERIC,   "pll2_bus",     "osc", base + 0x30, 0x1);
-        clk[pll3_usb_otg]  = imx_clk_pllv3(IMX_PLLV3_USB,       "pll3_usb_otg", "osc", base + 0x10, 0x3);
-        clk[pll4_audio]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll4_audio",   "osc", base + 0x70, 0x7f);
-        clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll5_video",   "osc", base + 0xa0, 0x7f);
-        clk[pll6_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll6_enet",    "osc", base + 0xe0, 0x3);
-        clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x3);
+        /*                                             type             name         parent_name  base     div_mask */
+        clk[IMX6QDL_CLK_PLL1_SYS]      = imx_clk_pllv3(IMX_PLLV3_SYS,   "pll1_sys",     "osc", base,        0x7f);
+        clk[IMX6QDL_CLK_PLL2_BUS]      = imx_clk_pllv3(IMX_PLLV3_GENERIC,       "pll2_bus",     "osc", base + 0x30, 0x1);
+        clk[IMX6QDL_CLK_PLL3_USB_OTG]  = imx_clk_pllv3(IMX_PLLV3_USB,   "pll3_usb_otg", "osc", base + 0x10, 0x3);
+        clk[IMX6QDL_CLK_PLL4_AUDIO]    = imx_clk_pllv3(IMX_PLLV3_AV,    "pll4_audio",   "osc", base + 0x70, 0x7f);
+        clk[IMX6QDL_CLK_PLL5_VIDEO]    = imx_clk_pllv3(IMX_PLLV3_AV,    "pll5_video",   "osc", base + 0xa0, 0x7f);
+        clk[IMX6QDL_CLK_PLL6_ENET]     = imx_clk_pllv3(IMX_PLLV3_ENET,  "pll6_enet",    "osc", base + 0xe0, 0x3);
+        clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB,   "pll7_usb_host","osc", base + 0x20, 0x3);
 
         /*
          * Bit 20 is the reserved and read-only bit, we do this only for:
@@ -181,28 +147,28 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
          * - Keep refcount when do usbphy clk_enable/disable, in that case,
          * the clk framework may need to enable/disable usbphy's parent
          */
-        clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
-        clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
+        clk[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
+        clk[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
 
         /*
          * usbphy*_gate needs to be on after system boots up, and software
          * never needs to control it anymore.
          */
-        clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
-        clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
+        clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
+        clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
 
-        clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
-        clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
+        clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
+        clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
 
-        clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
-        clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
+        clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
+        clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
 
-        clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
+        clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
                         base + 0xe0, 0, 2, 0, clk_enet_ref_table,
                         &imx_ccm_lock);
 
-        clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
-        clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
+        clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
+        clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
 
         /*
          * lvds1_gate and lvds2_gate are pseudo-gates.  Both can be
@@ -210,29 +176,29 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
          * the "output_enable" bit as a gate, even though it's really just
          * enabling clock output.
          */
-        clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
-        clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
-
-        /*                                name              parent_name        reg       idx */
-        clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
-        clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
-        clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus",     base + 0x100, 2);
-        clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0,  0);
-        clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0,  1);
-        clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0,  2);
-        clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0,  3);
-
-        /*                                    name         parent_name     mult div */
-        clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
-        clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg",   1, 4);
-        clk[pll3_80m]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
-        clk[pll3_60m]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
-        clk[twd]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);
-
-        clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
-        clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
-        clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
-        clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
+        clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
+        clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
+
+        /*                                            name              parent_name        reg       idx */
+        clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
+        clk[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
+        clk[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus",     base + 0x100, 2);
+        clk[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0,  0);
+        clk[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0,  1);
+        clk[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0,  2);
+        clk[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0,  3);
+
+        /*                                                name         parent_name     mult div */
+        clk[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
+        clk[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg",   1, 4);
+        clk[IMX6QDL_CLK_PLL3_80M]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
+        clk[IMX6QDL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
+        clk[IMX6QDL_CLK_TWD]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);
+
+        clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
+        clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
+        clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
+        clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
 
         np = ccm_node;
         base = of_iomap(np, 0);
@@ -240,262 +206,254 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 
         imx6q_pm_set_ccm_base(base);
 
-        /*                                  name                reg       shift width parent_names     num_parents */
-        clk[step]             = imx_clk_mux("step",             base + 0xc,  8,  1, step_sels,         ARRAY_SIZE(step_sels));
-        clk[pll1_sw]          = imx_clk_mux("pll1_sw",          base + 0xc,  2,  1, pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));
-        clk[periph_pre]       = imx_clk_mux("periph_pre",       base + 0x18, 18, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
-        clk[periph2_pre]      = imx_clk_mux("periph2_pre",      base + 0x18, 21, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
-        clk[periph_clk2_sel]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 2, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
-        clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
-        clk[axi_sel]          = imx_clk_mux("axi_sel",          base + 0x14, 6,  2, axi_sels,          ARRAY_SIZE(axi_sels));
-        clk[esai_sel]         = imx_clk_mux("esai_sel",         base + 0x20, 19, 2, audio_sels,        ARRAY_SIZE(audio_sels));
-        clk[asrc_sel]         = imx_clk_mux("asrc_sel",         base + 0x30, 7,  2, audio_sels,        ARRAY_SIZE(audio_sels));
-        clk[spdif_sel]        = imx_clk_mux("spdif_sel",        base + 0x30, 20, 2, audio_sels,        ARRAY_SIZE(audio_sels));
-        clk[gpu2d_axi]        = imx_clk_mux("gpu2d_axi",        base + 0x18, 0,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
-        clk[gpu3d_axi]        = imx_clk_mux("gpu3d_axi",        base + 0x18, 1,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
-        clk[gpu2d_core_sel]   = imx_clk_mux("gpu2d_core_sel",   base + 0x18, 16, 2, gpu2d_core_sels,   ARRAY_SIZE(gpu2d_core_sels));
-        clk[gpu3d_core_sel]   = imx_clk_mux("gpu3d_core_sel",   base + 0x18, 4,  2, gpu3d_core_sels,   ARRAY_SIZE(gpu3d_core_sels));
-        clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8,  2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
-        clk[ipu1_sel]         = imx_clk_mux("ipu1_sel",         base + 0x3c, 9,  2, ipu_sels,          ARRAY_SIZE(ipu_sels));
-        clk[ipu2_sel]         = imx_clk_mux("ipu2_sel",         base + 0x3c, 14, 2, ipu_sels,          ARRAY_SIZE(ipu_sels));
-        clk[ldb_di0_sel]      = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9,  3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
-        clk[ldb_di1_sel]      = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
-        clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
-        clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
-        clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
-        clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
-        clk[ipu1_di0_sel]     = imx_clk_mux_flags("ipu1_di0_sel",     base + 0x34, 0,  3, ipu1_di0_sels,     ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
-        clk[ipu1_di1_sel]     = imx_clk_mux_flags("ipu1_di1_sel",     base + 0x34, 9,  3, ipu1_di1_sels,     ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
-        clk[ipu2_di0_sel]     = imx_clk_mux_flags("ipu2_di0_sel",     base + 0x38, 0,  3, ipu2_di0_sels,     ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
-        clk[ipu2_di1_sel]     = imx_clk_mux_flags("ipu2_di1_sel",     base + 0x38, 9,  3, ipu2_di1_sels,     ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
-        clk[hsi_tx_sel]       = imx_clk_mux("hsi_tx_sel",       base + 0x30, 28, 1, hsi_tx_sels,       ARRAY_SIZE(hsi_tx_sels));
-        clk[pcie_axi_sel]     = imx_clk_mux("pcie_axi_sel",     base + 0x18, 10, 1, pcie_axi_sels,     ARRAY_SIZE(pcie_axi_sels));
-        clk[ssi1_sel]         = imx_clk_fixup_mux("ssi1_sel",   base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels),          imx_cscmr1_fixup);
-        clk[ssi2_sel]         = imx_clk_fixup_mux("ssi2_sel",   base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels),          imx_cscmr1_fixup);
-        clk[ssi3_sel]         = imx_clk_fixup_mux("ssi3_sel",   base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels),          imx_cscmr1_fixup);
-        clk[usdhc1_sel]       = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),        imx_cscmr1_fixup);
-        clk[usdhc2_sel]       = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),        imx_cscmr1_fixup);
-        clk[usdhc3_sel]       = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),        imx_cscmr1_fixup);
-        clk[usdhc4_sel]       = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),        imx_cscmr1_fixup);
-        clk[enfc_sel]         = imx_clk_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels,         ARRAY_SIZE(enfc_sels));
-        clk[emi_sel]          = imx_clk_fixup_mux("emi_sel",      base + 0x1c, 27, 2, emi_sels,        ARRAY_SIZE(emi_sels),          imx_cscmr1_fixup);
-        clk[emi_slow_sel]     = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels,   ARRAY_SIZE(emi_slow_sels),     imx_cscmr1_fixup);
-        clk[vdo_axi_sel]      = imx_clk_mux("vdo_axi_sel",      base + 0x18, 11, 1, vdo_axi_sels,      ARRAY_SIZE(vdo_axi_sels));
-        clk[vpu_axi_sel]      = imx_clk_mux("vpu_axi_sel",      base + 0x18, 14, 2, vpu_axi_sels,      ARRAY_SIZE(vpu_axi_sels));
-        clk[cko1_sel]         = imx_clk_mux("cko1_sel",         base + 0x60, 0,  4, cko1_sels,         ARRAY_SIZE(cko1_sels));
-        clk[cko2_sel]         = imx_clk_mux("cko2_sel",         base + 0x60, 16, 5, cko2_sels,         ARRAY_SIZE(cko2_sels));
-        clk[cko]              = imx_clk_mux("cko",              base + 0x60, 8, 1,  cko_sels,          ARRAY_SIZE(cko_sels));
-
-        /*                              name         reg      shift width busy: reg, shift parent_names  num_parents */
-        clk[periph]  = imx_clk_busy_mux("periph",  base + 0x14, 25,  1,   base + 0x48, 5,  periph_sels,  ARRAY_SIZE(periph_sels));
-        clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26,  1,   base + 0x48, 3,  periph2_sels, ARRAY_SIZE(periph2_sels));
-
-        /*                                      name                parent_name          reg       shift width */
-        clk[periph_clk2]      = imx_clk_divider("periph_clk2",      "periph_clk2_sel",   base + 0x14, 27, 3);
-        clk[periph2_clk2]     = imx_clk_divider("periph2_clk2",     "periph2_clk2_sel",  base + 0x14, 0,  3);
-        clk[ipg]              = imx_clk_divider("ipg",              "ahb",               base + 0x14, 8,  2);
-        clk[ipg_per]          = imx_clk_fixup_divider("ipg_per",    "ipg",               base + 0x1c, 0,  6, imx_cscmr1_fixup);
-        clk[esai_pred]        = imx_clk_divider("esai_pred",        "esai_sel",          base + 0x28, 9,  3);
-        clk[esai_podf]        = imx_clk_divider("esai_podf",        "esai_pred",         base + 0x28, 25, 3);
-        clk[asrc_pred]        = imx_clk_divider("asrc_pred",        "asrc_sel",          base + 0x30, 12, 3);
-        clk[asrc_podf]        = imx_clk_divider("asrc_podf",        "asrc_pred",         base + 0x30, 9,  3);
-        clk[spdif_pred]       = imx_clk_divider("spdif_pred",       "spdif_sel",         base + 0x30, 25, 3);
-        clk[spdif_podf]       = imx_clk_divider("spdif_podf",       "spdif_pred",        base + 0x30, 22, 3);
-        clk[can_root]         = imx_clk_divider("can_root",         "pll3_60m",          base + 0x20, 2,  6);
-        clk[ecspi_root]       = imx_clk_divider("ecspi_root",       "pll3_60m",          base + 0x38, 19, 6);
-        clk[gpu2d_core_podf]  = imx_clk_divider("gpu2d_core_podf",  "gpu2d_core_sel",    base + 0x18, 23, 3);
-        clk[gpu3d_core_podf]  = imx_clk_divider("gpu3d_core_podf",  "gpu3d_core_sel",    base + 0x18, 26, 3);
-        clk[gpu3d_shader]     = imx_clk_divider("gpu3d_shader",     "gpu3d_shader_sel",  base + 0x18, 29, 3);
-        clk[ipu1_podf]        = imx_clk_divider("ipu1_podf",        "ipu1_sel",          base + 0x3c, 11, 3);
-        clk[ipu2_podf]        = imx_clk_divider("ipu2_podf",        "ipu2_sel",          base + 0x3c, 16, 3);
-        clk[ldb_di0_div_3_5]  = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
-        clk[ldb_di0_podf]     = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
-        clk[ldb_di1_div_3_5]  = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
-        clk[ldb_di1_podf]     = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
-        clk[ipu1_di0_pre]     = imx_clk_divider("ipu1_di0_pre",     "ipu1_di0_pre_sel",  base + 0x34, 3,  3);
-        clk[ipu1_di1_pre]     = imx_clk_divider("ipu1_di1_pre",     "ipu1_di1_pre_sel",  base + 0x34, 12, 3);
-        clk[ipu2_di0_pre]     = imx_clk_divider("ipu2_di0_pre",     "ipu2_di0_pre_sel",  base + 0x38, 3,  3);
-        clk[ipu2_di1_pre]     = imx_clk_divider("ipu2_di1_pre",     "ipu2_di1_pre_sel",  base + 0x38, 12, 3);
-        clk[hsi_tx_podf]      = imx_clk_divider("hsi_tx_podf",      "hsi_tx_sel",        base + 0x30, 29, 3);
-        clk[ssi1_pred]        = imx_clk_divider("ssi1_pred",        "ssi1_sel",          base + 0x28, 6,  3);
-        clk[ssi1_podf]        = imx_clk_divider("ssi1_podf",        "ssi1_pred",         base + 0x28, 0,  6);
-        clk[ssi2_pred]        = imx_clk_divider("ssi2_pred",        "ssi2_sel",          base + 0x2c, 6,  3);
-        clk[ssi2_podf]        = imx_clk_divider("ssi2_podf",        "ssi2_pred",         base + 0x2c, 0,  6);
-        clk[ssi3_pred]        = imx_clk_divider("ssi3_pred",        "ssi3_sel",          base + 0x28, 22, 3);
-        clk[ssi3_podf]        = imx_clk_divider("ssi3_podf",        "ssi3_pred",         base + 0x28, 16, 6);
-        clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m",          base + 0x24, 0,  6);
-        clk[usdhc1_podf]      = imx_clk_divider("usdhc1_podf",      "usdhc1_sel",        base + 0x24, 11, 3);
-        clk[usdhc2_podf]      = imx_clk_divider("usdhc2_podf",      "usdhc2_sel",        base + 0x24, 16, 3);
-        clk[usdhc3_podf]      = imx_clk_divider("usdhc3_podf",      "usdhc3_sel",        base + 0x24, 19, 3);
-        clk[usdhc4_podf]      = imx_clk_divider("usdhc4_podf",      "usdhc4_sel",        base + 0x24, 22, 3);
-        clk[enfc_pred]        = imx_clk_divider("enfc_pred",        "enfc_sel",          base + 0x2c, 18, 3);
-        clk[enfc_podf]        = imx_clk_divider("enfc_podf",        "enfc_pred",         base + 0x2c, 21, 6);
-        clk[emi_podf]         = imx_clk_fixup_divider("emi_podf",   "emi_sel",           base + 0x1c, 20, 3, imx_cscmr1_fixup);
-        clk[emi_slow_podf]    = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel",   base + 0x1c, 23, 3, imx_cscmr1_fixup);
-        clk[vpu_axi_podf]     = imx_clk_divider("vpu_axi_podf",     "vpu_axi_sel",       base + 0x24, 25, 3);
-        clk[cko1_podf]        = imx_clk_divider("cko1_podf",        "cko1_sel",          base + 0x60, 4,  3);
-        clk[cko2_podf]        = imx_clk_divider("cko2_podf",        "cko2_sel",          base + 0x60, 21, 3);
-
-        /*                                            name                 parent_name    reg        shift width busy: reg, shift */
-        clk[axi]               = imx_clk_busy_divider("axi",               "axi_sel",     base + 0x14, 16,  3,   base + 0x48, 0);
-        clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph",      base + 0x14, 19,  3,   base + 0x48, 4);
-        clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2",     base + 0x14, 3,   3,   base + 0x48, 2);
-        clk[arm]               = imx_clk_busy_divider("arm",               "pll1_sw",     base + 0x10, 0,   3,   base + 0x48, 16);
-        clk[ahb]               = imx_clk_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);
-
-        /*                                name             parent_name          reg         shift */
-        clk[apbh_dma]     = imx_clk_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);
-        clk[asrc]         = imx_clk_gate2("asrc",          "asrc_podf",         base + 0x68, 6);
-        clk[can1_ipg]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
-        clk[can1_serial]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
-        clk[can2_ipg]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
-        clk[can2_serial]  = imx_clk_gate2("can2_serial",   "can_root",          base + 0x68, 20);
-        clk[ecspi1]       = imx_clk_gate2("ecspi1",        "ecspi_root",        base + 0x6c, 0);
-        clk[ecspi2]       = imx_clk_gate2("ecspi2",        "ecspi_root",        base + 0x6c, 2);
-        clk[ecspi3]       = imx_clk_gate2("ecspi3",        "ecspi_root",        base + 0x6c, 4);
-        clk[ecspi4]       = imx_clk_gate2("ecspi4",        "ecspi_root",        base + 0x6c, 6);
+        /*                                              name                reg       shift width parent_names     num_parents */
+        clk[IMX6QDL_CLK_STEP]             = imx_clk_mux("step",             base + 0xc,  8,  1, step_sels,         ARRAY_SIZE(step_sels));
+        clk[IMX6QDL_CLK_PLL1_SW]          = imx_clk_mux("pll1_sw",          base + 0xc,  2,  1, pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));
+        clk[IMX6QDL_CLK_PERIPH_PRE]       = imx_clk_mux("periph_pre",       base + 0x18, 18, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
+        clk[IMX6QDL_CLK_PERIPH2_PRE]      = imx_clk_mux("periph2_pre",      base + 0x18, 21, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
+        clk[IMX6QDL_CLK_PERIPH_CLK2_SEL]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 2, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
+        clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
+        clk[IMX6QDL_CLK_AXI_SEL]          = imx_clk_mux("axi_sel",          base + 0x14, 6,  2, axi_sels,          ARRAY_SIZE(axi_sels));
+        clk[IMX6QDL_CLK_ESAI_SEL]         = imx_clk_mux("esai_sel",         base + 0x20, 19, 2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clk[IMX6QDL_CLK_ASRC_SEL]         = imx_clk_mux("asrc_sel",         base + 0x30, 7,  2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clk[IMX6QDL_CLK_SPDIF_SEL]        = imx_clk_mux("spdif_sel",        base + 0x30, 20, 2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clk[IMX6QDL_CLK_GPU2D_AXI]        = imx_clk_mux("gpu2d_axi",        base + 0x18, 0,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
+        clk[IMX6QDL_CLK_GPU3D_AXI]        = imx_clk_mux("gpu3d_axi",        base + 0x18, 1,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
+        clk[IMX6QDL_CLK_GPU2D_CORE_SEL]   = imx_clk_mux("gpu2d_core_sel",   base + 0x18, 16, 2, gpu2d_core_sels,   ARRAY_SIZE(gpu2d_core_sels));
+        clk[IMX6QDL_CLK_GPU3D_CORE_SEL]   = imx_clk_mux("gpu3d_core_sel",   base + 0x18, 4,  2, gpu3d_core_sels,   ARRAY_SIZE(gpu3d_core_sels));
+        clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8,  2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
+        clk[IMX6QDL_CLK_IPU1_SEL]         = imx_clk_mux("ipu1_sel",         base + 0x3c, 9,  2, ipu_sels,          ARRAY_SIZE(ipu_sels));
+        clk[IMX6QDL_CLK_IPU2_SEL]         = imx_clk_mux("ipu2_sel",         base + 0x3c, 14, 2, ipu_sels,          ARRAY_SIZE(ipu_sels));
+        clk[IMX6QDL_CLK_LDB_DI0_SEL]      = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9,  3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_LDB_DI1_SEL]      = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_IPU1_DI0_SEL]     = imx_clk_mux_flags("ipu1_di0_sel",     base + 0x34, 0,  3, ipu1_di0_sels,     ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_IPU1_DI1_SEL]     = imx_clk_mux_flags("ipu1_di1_sel",     base + 0x34, 9,  3, ipu1_di1_sels,     ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_IPU2_DI0_SEL]     = imx_clk_mux_flags("ipu2_di0_sel",     base + 0x38, 0,  3, ipu2_di0_sels,     ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_IPU2_DI1_SEL]     = imx_clk_mux_flags("ipu2_di1_sel",     base + 0x38, 9,  3, ipu2_di1_sels,     ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
+        clk[IMX6QDL_CLK_HSI_TX_SEL]       = imx_clk_mux("hsi_tx_sel",       base + 0x30, 28, 1, hsi_tx_sels,       ARRAY_SIZE(hsi_tx_sels));
+        clk[IMX6QDL_CLK_PCIE_AXI_SEL]     = imx_clk_mux("pcie_axi_sel",     base + 0x18, 10, 1, pcie_axi_sels,     ARRAY_SIZE(pcie_axi_sels));
+        clk[IMX6QDL_CLK_SSI1_SEL]         = imx_clk_fixup_mux("ssi1_sel",   base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_SSI2_SEL]         = imx_clk_fixup_mux("ssi2_sel",   base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_SSI3_SEL]         = imx_clk_fixup_mux("ssi3_sel",   base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_USDHC1_SEL]       = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_USDHC2_SEL]       = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_USDHC3_SEL]       = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_USDHC4_SEL]       = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_ENFC_SEL]         = imx_clk_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels,         ARRAY_SIZE(enfc_sels));
+        clk[IMX6QDL_CLK_EMI_SEL]          = imx_clk_fixup_mux("emi_sel",      base + 0x1c, 27, 2, emi_sels,        ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_EMI_SLOW_SEL]     = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels,   ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_VDO_AXI_SEL]      = imx_clk_mux("vdo_axi_sel",      base + 0x18, 11, 1, vdo_axi_sels,      ARRAY_SIZE(vdo_axi_sels));
+        clk[IMX6QDL_CLK_VPU_AXI_SEL]      = imx_clk_mux("vpu_axi_sel",      base + 0x18, 14, 2, vpu_axi_sels,      ARRAY_SIZE(vpu_axi_sels));
+        clk[IMX6QDL_CLK_CKO1_SEL]         = imx_clk_mux("cko1_sel",         base + 0x60, 0,  4, cko1_sels,         ARRAY_SIZE(cko1_sels));
+        clk[IMX6QDL_CLK_CKO2_SEL]         = imx_clk_mux("cko2_sel",         base + 0x60, 16, 5, cko2_sels,         ARRAY_SIZE(cko2_sels));
+        clk[IMX6QDL_CLK_CKO]              = imx_clk_mux("cko",              base + 0x60, 8, 1,  cko_sels,          ARRAY_SIZE(cko_sels));
+
+        /*                                          name         reg      shift width busy: reg, shift parent_names  num_parents */
+        clk[IMX6QDL_CLK_PERIPH]  = imx_clk_busy_mux("periph",  base + 0x14, 25,  1,   base + 0x48, 5,  periph_sels,  ARRAY_SIZE(periph_sels));
+        clk[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26,  1,   base + 0x48, 3,  periph2_sels, ARRAY_SIZE(periph2_sels));
+
+        /*                                                  name                parent_name          reg       shift width */
+        clk[IMX6QDL_CLK_PERIPH_CLK2]      = imx_clk_divider("periph_clk2",      "periph_clk2_sel",   base + 0x14, 27, 3);
+        clk[IMX6QDL_CLK_PERIPH2_CLK2]     = imx_clk_divider("periph2_clk2",     "periph2_clk2_sel",  base + 0x14, 0,  3);
+        clk[IMX6QDL_CLK_IPG]              = imx_clk_divider("ipg",              "ahb",               base + 0x14, 8,  2);
+        clk[IMX6QDL_CLK_IPG_PER]          = imx_clk_fixup_divider("ipg_per",    "ipg",               base + 0x1c, 0,  6, imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_ESAI_PRED]        = imx_clk_divider("esai_pred",        "esai_sel",          base + 0x28, 9,  3);
+        clk[IMX6QDL_CLK_ESAI_PODF]        = imx_clk_divider("esai_podf",        "esai_pred",         base + 0x28, 25, 3);
+        clk[IMX6QDL_CLK_ASRC_PRED]        = imx_clk_divider("asrc_pred",        "asrc_sel",          base + 0x30, 12, 3);
+        clk[IMX6QDL_CLK_ASRC_PODF]        = imx_clk_divider("asrc_podf",        "asrc_pred",         base + 0x30, 9,  3);
+        clk[IMX6QDL_CLK_SPDIF_PRED]       = imx_clk_divider("spdif_pred",       "spdif_sel",         base + 0x30, 25, 3);
+        clk[IMX6QDL_CLK_SPDIF_PODF]       = imx_clk_divider("spdif_podf",       "spdif_pred",        base + 0x30, 22, 3);
+        clk[IMX6QDL_CLK_CAN_ROOT]         = imx_clk_divider("can_root",         "pll3_60m",          base + 0x20, 2,  6);
+        clk[IMX6QDL_CLK_ECSPI_ROOT]       = imx_clk_divider("ecspi_root",       "pll3_60m",          base + 0x38, 19, 6);
+        clk[IMX6QDL_CLK_GPU2D_CORE_PODF]  = imx_clk_divider("gpu2d_core_podf",  "gpu2d_core_sel",    base + 0x18, 23, 3);
+        clk[IMX6QDL_CLK_GPU3D_CORE_PODF]  = imx_clk_divider("gpu3d_core_podf",  "gpu3d_core_sel",    base + 0x18, 26, 3);
+        clk[IMX6QDL_CLK_GPU3D_SHADER]     = imx_clk_divider("gpu3d_shader",     "gpu3d_shader_sel",  base + 0x18, 29, 3);
+        clk[IMX6QDL_CLK_IPU1_PODF]        = imx_clk_divider("ipu1_podf",        "ipu1_sel",          base + 0x3c, 11, 3);
+        clk[IMX6QDL_CLK_IPU2_PODF]        = imx_clk_divider("ipu2_podf",        "ipu2_sel",          base + 0x3c, 16, 3);
+        clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5]  = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
+        clk[IMX6QDL_CLK_LDB_DI0_PODF]     = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
+        clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5]  = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
+        clk[IMX6QDL_CLK_LDB_DI1_PODF]     = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
+        clk[IMX6QDL_CLK_IPU1_DI0_PRE]     = imx_clk_divider("ipu1_di0_pre",     "ipu1_di0_pre_sel",  base + 0x34, 3,  3);
+        clk[IMX6QDL_CLK_IPU1_DI1_PRE]     = imx_clk_divider("ipu1_di1_pre",     "ipu1_di1_pre_sel",  base + 0x34, 12, 3);
+        clk[IMX6QDL_CLK_IPU2_DI0_PRE]     = imx_clk_divider("ipu2_di0_pre",     "ipu2_di0_pre_sel",  base + 0x38, 3,  3);
+        clk[IMX6QDL_CLK_IPU2_DI1_PRE]     = imx_clk_divider("ipu2_di1_pre",     "ipu2_di1_pre_sel",  base + 0x38, 12, 3);
+        clk[IMX6QDL_CLK_HSI_TX_PODF]      = imx_clk_divider("hsi_tx_podf",      "hsi_tx_sel",        base + 0x30, 29, 3);
+        clk[IMX6QDL_CLK_SSI1_PRED]        = imx_clk_divider("ssi1_pred",        "ssi1_sel",          base + 0x28, 6,  3);
+        clk[IMX6QDL_CLK_SSI1_PODF]        = imx_clk_divider("ssi1_podf",        "ssi1_pred",         base + 0x28, 0,  6);
+        clk[IMX6QDL_CLK_SSI2_PRED]        = imx_clk_divider("ssi2_pred",        "ssi2_sel",          base + 0x2c, 6,  3);
+        clk[IMX6QDL_CLK_SSI2_PODF]        = imx_clk_divider("ssi2_podf",        "ssi2_pred",         base + 0x2c, 0,  6);
+        clk[IMX6QDL_CLK_SSI3_PRED]        = imx_clk_divider("ssi3_pred",        "ssi3_sel",          base + 0x28, 22, 3);
+        clk[IMX6QDL_CLK_SSI3_PODF]        = imx_clk_divider("ssi3_podf",        "ssi3_pred",         base + 0x28, 16, 6);
+        clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m",          base + 0x24, 0,  6);
+        clk[IMX6QDL_CLK_USDHC1_PODF]      = imx_clk_divider("usdhc1_podf",      "usdhc1_sel",        base + 0x24, 11, 3);
+        clk[IMX6QDL_CLK_USDHC2_PODF]      = imx_clk_divider("usdhc2_podf",      "usdhc2_sel",        base + 0x24, 16, 3);
+        clk[IMX6QDL_CLK_USDHC3_PODF]      = imx_clk_divider("usdhc3_podf",      "usdhc3_sel",        base + 0x24, 19, 3);
+        clk[IMX6QDL_CLK_USDHC4_PODF]      = imx_clk_divider("usdhc4_podf",      "usdhc4_sel",        base + 0x24, 22, 3);
+        clk[IMX6QDL_CLK_ENFC_PRED]        = imx_clk_divider("enfc_pred",        "enfc_sel",          base + 0x2c, 18, 3);
+        clk[IMX6QDL_CLK_ENFC_PODF]        = imx_clk_divider("enfc_podf",        "enfc_pred",         base + 0x2c, 21, 6);
+        clk[IMX6QDL_CLK_EMI_PODF]         = imx_clk_fixup_divider("emi_podf",   "emi_sel",           base + 0x1c, 20, 3, imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_EMI_SLOW_PODF]    = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel",   base + 0x1c, 23, 3, imx_cscmr1_fixup);
+        clk[IMX6QDL_CLK_VPU_AXI_PODF]     = imx_clk_divider("vpu_axi_podf",     "vpu_axi_sel",       base + 0x24, 25, 3);
+        clk[IMX6QDL_CLK_CKO1_PODF]        = imx_clk_divider("cko1_podf",        "cko1_sel",          base + 0x60, 4,  3);
+        clk[IMX6QDL_CLK_CKO2_PODF]        = imx_clk_divider("cko2_podf",        "cko2_sel",          base + 0x60, 21, 3);
+
+        /*                                                        name                 parent_name    reg        shift width busy: reg, shift */
+        clk[IMX6QDL_CLK_AXI]               = imx_clk_busy_divider("axi",               "axi_sel",     base + 0x14, 16,  3,   base + 0x48, 0);
+        clk[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph",      base + 0x14, 19,  3,   base + 0x48, 4);
+        clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2",     base + 0x14, 3,   3,   base + 0x48, 2);
+        clk[IMX6QDL_CLK_ARM]               = imx_clk_busy_divider("arm",               "pll1_sw",     base + 0x10, 0,   3,   base + 0x48, 16);
+        clk[IMX6QDL_CLK_AHB]               = imx_clk_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);
+
+        /*                                            name             parent_name          reg         shift */
+        clk[IMX6QDL_CLK_APBH_DMA]     = imx_clk_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);
+        clk[IMX6QDL_CLK_ASRC]         = imx_clk_gate2("asrc",          "asrc_podf",         base + 0x68, 6);
+        clk[IMX6QDL_CLK_CAN1_IPG]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
+        clk[IMX6QDL_CLK_CAN1_SERIAL]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
+        clk[IMX6QDL_CLK_CAN2_IPG]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
+        clk[IMX6QDL_CLK_CAN2_SERIAL]  = imx_clk_gate2("can2_serial",   "can_root",          base + 0x68, 20);
+        clk[IMX6QDL_CLK_ECSPI1]       = imx_clk_gate2("ecspi1",        "ecspi_root",        base + 0x6c, 0);
+        clk[IMX6QDL_CLK_ECSPI2]       = imx_clk_gate2("ecspi2",        "ecspi_root",        base + 0x6c, 2);
+        clk[IMX6QDL_CLK_ECSPI3]       = imx_clk_gate2("ecspi3",        "ecspi_root",        base + 0x6c, 4);
+        clk[IMX6QDL_CLK_ECSPI4]       = imx_clk_gate2("ecspi4",        "ecspi_root",        base + 0x6c, 6);
         if (cpu_is_imx6dl())
-                /* ecspi5 is replaced with i2c4 on imx6dl & imx6s */
-                clk[ecspi5] = imx_clk_gate2("i2c4",        "ipg_per",           base + 0x6c, 8);
+                clk[IMX6DL_CLK_I2C4]  = imx_clk_gate2("i2c4",          "ipg_per",           base + 0x6c, 8);
         else
-                clk[ecspi5] = imx_clk_gate2("ecspi5",      "ecspi_root",        base + 0x6c, 8);
-        clk[enet]         = imx_clk_gate2("enet",          "ipg",               base + 0x6c, 10);
-        clk[esai]         = imx_clk_gate2_shared("esai",   "esai_podf",         base + 0x6c, 16, &share_count_esai);
-        clk[esai_ahb]     = imx_clk_gate2_shared("esai_ahb", "ahb",             base + 0x6c, 16, &share_count_esai);
-        clk[gpt_ipg]      = imx_clk_gate2("gpt_ipg",       "ipg",               base + 0x6c, 20);
-        clk[gpt_ipg_per]  = imx_clk_gate2("gpt_ipg_per",   "ipg_per",           base + 0x6c, 22);
+                clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5",        "ecspi_root",        base + 0x6c, 8);
+        clk[IMX6QDL_CLK_ENET]         = imx_clk_gate2("enet",          "ipg",               base + 0x6c, 10);
+        clk[IMX6QDL_CLK_ESAI]         = imx_clk_gate2_shared("esai",   "esai_podf",         base + 0x6c, 16, &share_count_esai);
+        clk[IMX6QDL_CLK_ESAI_AHB]     = imx_clk_gate2_shared("esai_ahb", "ahb",             base + 0x6c, 16, &share_count_esai);
+        clk[IMX6QDL_CLK_GPT_IPG]      = imx_clk_gate2("gpt_ipg",       "ipg",               base + 0x6c, 20);
+        clk[IMX6QDL_CLK_GPT_IPG_PER]  = imx_clk_gate2("gpt_ipg_per",   "ipg_per",           base + 0x6c, 22);
         if (cpu_is_imx6dl())
                 /*
                  * The multiplexer and divider of imx6q clock gpu3d_shader get
                  * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
                  */
-                clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
+                clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
         else
-                clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
-        clk[gpu3d_core]   = imx_clk_gate2("gpu3d_core",    "gpu3d_core_podf",   base + 0x6c, 26);
-        clk[hdmi_iahb]    = imx_clk_gate2("hdmi_iahb",     "ahb",               base + 0x70, 0);
-        clk[hdmi_isfr]    = imx_clk_gate2("hdmi_isfr",     "pll3_pfd1_540m",    base + 0x70, 4);
-        clk[i2c1]         = imx_clk_gate2("i2c1",          "ipg_per",           base + 0x70, 6);
-        clk[i2c2]         = imx_clk_gate2("i2c2",          "ipg_per",           base + 0x70, 8);
-        clk[i2c3]         = imx_clk_gate2("i2c3",          "ipg_per",           base + 0x70, 10);
-        clk[iim]          = imx_clk_gate2("iim",           "ipg",               base + 0x70, 12);
-        clk[enfc]         = imx_clk_gate2("enfc",          "enfc_podf",         base + 0x70, 14);
-        clk[vdoa]         = imx_clk_gate2("vdoa",          "vdo_axi",           base + 0x70, 26);
-        clk[ipu1]         = imx_clk_gate2("ipu1",          "ipu1_podf",         base + 0x74, 0);
-        clk[ipu1_di0]     = imx_clk_gate2("ipu1_di0",      "ipu1_di0_sel",      base + 0x74, 2);
-        clk[ipu1_di1]     = imx_clk_gate2("ipu1_di1",      "ipu1_di1_sel",      base + 0x74, 4);
-        clk[ipu2]         = imx_clk_gate2("ipu2",          "ipu2_podf",         base + 0x74, 6);
-        clk[ipu2_di0]     = imx_clk_gate2("ipu2_di0",      "ipu2_di0_sel",      base + 0x74, 8);
-        clk[ldb_di0]      = imx_clk_gate2("ldb_di0",       "ldb_di0_podf",      base + 0x74, 12);
-        clk[ldb_di1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
-        clk[ipu2_di1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
-        clk[hsi_tx]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);
+                clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
+        clk[IMX6QDL_CLK_GPU3D_CORE]   = imx_clk_gate2("gpu3d_core",    "gpu3d_core_podf",   base + 0x6c, 26);
+        clk[IMX6QDL_CLK_HDMI_IAHB]    = imx_clk_gate2("hdmi_iahb",     "ahb",               base + 0x70, 0);
+        clk[IMX6QDL_CLK_HDMI_ISFR]    = imx_clk_gate2("hdmi_isfr",     "pll3_pfd1_540m",    base + 0x70, 4);
+        clk[IMX6QDL_CLK_I2C1]         = imx_clk_gate2("i2c1",          "ipg_per",           base + 0x70, 6);
+        clk[IMX6QDL_CLK_I2C2]         = imx_clk_gate2("i2c2",          "ipg_per",           base + 0x70, 8);
+        clk[IMX6QDL_CLK_I2C3]         = imx_clk_gate2("i2c3",          "ipg_per",           base + 0x70, 10);
+        clk[IMX6QDL_CLK_IIM]          = imx_clk_gate2("iim",           "ipg",               base + 0x70, 12);
+        clk[IMX6QDL_CLK_ENFC]         = imx_clk_gate2("enfc",          "enfc_podf",         base + 0x70, 14);
+        clk[IMX6QDL_CLK_VDOA]         = imx_clk_gate2("vdoa",          "vdo_axi",           base + 0x70, 26);
+        clk[IMX6QDL_CLK_IPU1]         = imx_clk_gate2("ipu1",          "ipu1_podf",         base + 0x74, 0);
+        clk[IMX6QDL_CLK_IPU1_DI0]     = imx_clk_gate2("ipu1_di0",      "ipu1_di0_sel",      base + 0x74, 2);
+        clk[IMX6QDL_CLK_IPU1_DI1]     = imx_clk_gate2("ipu1_di1",      "ipu1_di1_sel",      base + 0x74, 4);
+        clk[IMX6QDL_CLK_IPU2]         = imx_clk_gate2("ipu2",          "ipu2_podf",         base + 0x74, 6);
+        clk[IMX6QDL_CLK_IPU2_DI0]     = imx_clk_gate2("ipu2_di0",      "ipu2_di0_sel",      base + 0x74, 8);
+        clk[IMX6QDL_CLK_LDB_DI0]      = imx_clk_gate2("ldb_di0",       "ldb_di0_podf",      base + 0x74, 12);
+        clk[IMX6QDL_CLK_LDB_DI1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
+        clk[IMX6QDL_CLK_IPU2_DI1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
+        clk[IMX6QDL_CLK_HSI_TX]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);
         if (cpu_is_imx6dl())
                 /*
                  * The multiplexer and divider of the imx6q clock gpu2d get
                  * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
                  */
-                clk[mlb] = imx_clk_gate2("mlb",            "gpu2d_core_podf",   base + 0x74, 18);
+                clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb",            "gpu2d_core_podf",   base + 0x74, 18);
         else
-                clk[mlb] = imx_clk_gate2("mlb",            "axi",               base + 0x74, 18);
-        clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
-        clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
-        clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
-        clk[openvg_axi]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);
-        clk[pcie_axi]     = imx_clk_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
-        clk[per1_bch]     = imx_clk_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);
-        clk[pwm1]         = imx_clk_gate2("pwm1",          "ipg_per",           base + 0x78, 16);
-        clk[pwm2]         = imx_clk_gate2("pwm2",          "ipg_per",           base + 0x78, 18);
-        clk[pwm3]         = imx_clk_gate2("pwm3",          "ipg_per",           base + 0x78, 20);
-        clk[pwm4]         = imx_clk_gate2("pwm4",          "ipg_per",           base + 0x78, 22);
-        clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb",  "usdhc3",            base + 0x78, 24);
-        clk[gpmi_bch]     = imx_clk_gate2("gpmi_bch",      "usdhc4",            base + 0x78, 26);
-        clk[gpmi_io]      = imx_clk_gate2("gpmi_io",       "enfc",              base + 0x78, 28);
-        clk[gpmi_apb]     = imx_clk_gate2("gpmi_apb",      "usdhc3",            base + 0x78, 30);
-        clk[rom]          = imx_clk_gate2("rom",           "ahb",               base + 0x7c, 0);
-        clk[sata]         = imx_clk_gate2("sata",          "ipg",               base + 0x7c, 4);
-        clk[sdma]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
-        clk[spba]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
-        clk[spdif]        = imx_clk_gate2("spdif",         "spdif_podf",        base + 0x7c, 14);
-        clk[ssi1_ipg]     = imx_clk_gate2("ssi1_ipg",      "ipg",               base + 0x7c, 18);
-        clk[ssi2_ipg]     = imx_clk_gate2("ssi2_ipg",      "ipg",               base + 0x7c, 20);
-        clk[ssi3_ipg]     = imx_clk_gate2("ssi3_ipg",      "ipg",               base + 0x7c, 22);
-        clk[uart_ipg]     = imx_clk_gate2("uart_ipg",      "ipg",               base + 0x7c, 24);
-        clk[uart_serial]  = imx_clk_gate2("uart_serial",   "uart_serial_podf",  base + 0x7c, 26);
-        clk[usboh3]       = imx_clk_gate2("usboh3",        "ipg",               base + 0x80, 0);
-        clk[usdhc1]       = imx_clk_gate2("usdhc1",        "usdhc1_podf",       base + 0x80, 2);
-        clk[usdhc2]       = imx_clk_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
-        clk[usdhc3]       = imx_clk_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
-        clk[usdhc4]       = imx_clk_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
-        clk[eim_slow]     = imx_clk_gate2("eim_slow",      "emi_slow_podf",     base + 0x80, 10);
-        clk[vdo_axi]      = imx_clk_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
-        clk[vpu_axi]      = imx_clk_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
-        clk[cko1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
-        clk[cko2]         = imx_clk_gate("cko2",           "cko2_podf",         base + 0x60, 24);
-
-        for (i = 0; i < ARRAY_SIZE(clk); i++)
-                if (IS_ERR(clk[i]))
-                        pr_err("i.MX6q clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clk[i]));
+                clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb",            "axi",               base + 0x74, 18);
+        clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
+        clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
+        clk[IMX6QDL_CLK_OCRAM]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
+        clk[IMX6QDL_CLK_OPENVG_AXI]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);
+        clk[IMX6QDL_CLK_PCIE_AXI]     = imx_clk_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
+        clk[IMX6QDL_CLK_PER1_BCH]     = imx_clk_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);
+        clk[IMX6QDL_CLK_PWM1]         = imx_clk_gate2("pwm1",          "ipg_per",           base + 0x78, 16);
+        clk[IMX6QDL_CLK_PWM2]         = imx_clk_gate2("pwm2",          "ipg_per",           base + 0x78, 18);
+        clk[IMX6QDL_CLK_PWM3]         = imx_clk_gate2("pwm3",          "ipg_per",           base + 0x78, 20);
+        clk[IMX6QDL_CLK_PWM4]         = imx_clk_gate2("pwm4",          "ipg_per",           base + 0x78, 22);
+        clk[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb",  "usdhc3",            base + 0x78, 24);
+        clk[IMX6QDL_CLK_GPMI_BCH]     = imx_clk_gate2("gpmi_bch",      "usdhc4",            base + 0x78, 26);
+        clk[IMX6QDL_CLK_GPMI_IO]      = imx_clk_gate2("gpmi_io",       "enfc",              base + 0x78, 28);
+        clk[IMX6QDL_CLK_GPMI_APB]     = imx_clk_gate2("gpmi_apb",      "usdhc3",            base + 0x78, 30);
+        clk[IMX6QDL_CLK_ROM]          = imx_clk_gate2("rom",           "ahb",               base + 0x7c, 0);
+        clk[IMX6QDL_CLK_SATA]         = imx_clk_gate2("sata",          "ipg",               base + 0x7c, 4);
+        clk[IMX6QDL_CLK_SDMA]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
+        clk[IMX6QDL_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
+        clk[IMX6QDL_CLK_SPDIF]        = imx_clk_gate2("spdif",         "spdif_podf",        base + 0x7c, 14);
+        clk[IMX6QDL_CLK_SSI1_IPG]     = imx_clk_gate2("ssi1_ipg",      "ipg",               base + 0x7c, 18);
+        clk[IMX6QDL_CLK_SSI2_IPG]     = imx_clk_gate2("ssi2_ipg",      "ipg",               base + 0x7c, 20);
+        clk[IMX6QDL_CLK_SSI3_IPG]     = imx_clk_gate2("ssi3_ipg",      "ipg",               base + 0x7c, 22);
+        clk[IMX6QDL_CLK_UART_IPG]     = imx_clk_gate2("uart_ipg",      "ipg",               base + 0x7c, 24);
+        clk[IMX6QDL_CLK_UART_SERIAL]  = imx_clk_gate2("uart_serial",   "uart_serial_podf",  base + 0x7c, 26);
+        clk[IMX6QDL_CLK_USBOH3]       = imx_clk_gate2("usboh3",        "ipg",               base + 0x80, 0);
+        clk[IMX6QDL_CLK_USDHC1]       = imx_clk_gate2("usdhc1",        "usdhc1_podf",       base + 0x80, 2);
+        clk[IMX6QDL_CLK_USDHC2]       = imx_clk_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
+        clk[IMX6QDL_CLK_USDHC3]       = imx_clk_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
+        clk[IMX6QDL_CLK_USDHC4]       = imx_clk_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
+        clk[IMX6QDL_CLK_EIM_SLOW]     = imx_clk_gate2("eim_slow",      "emi_slow_podf",     base + 0x80, 10);
+        clk[IMX6QDL_CLK_VDO_AXI]      = imx_clk_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
+        clk[IMX6QDL_CLK_VPU_AXI]      = imx_clk_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
+        clk[IMX6QDL_CLK_CKO1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
+        clk[IMX6QDL_CLK_CKO2]         = imx_clk_gate("cko2",           "cko2_podf",         base + 0x60, 24);
+
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
         clk_data.clks = clk;
         clk_data.clk_num = ARRAY_SIZE(clk);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);
+        clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
 
         if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
             cpu_is_imx6dl()) {
-                clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
-                clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
+                clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+                clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
         }
 
-        clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
-        clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
-        clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
-        clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
-        clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
-        clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
-        clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
-        clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
+        clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+        clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+        clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+        clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+        clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
+        clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
+        clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
+        clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);
 
         /*
          * The gpmi needs 100MHz frequency in the EDO/Sync mode,
          * We can not get the 100MHz from the pll2_pfd0_352m.
          * So choose pll2_pfd2_396m as enfc_sel's parent.
          */
-        clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
+        clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
 
         for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
                 clk_prepare_enable(clk[clks_init_on[i]]);
 
         if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
-                clk_prepare_enable(clk[usbphy1_gate]);
-                clk_prepare_enable(clk[usbphy2_gate]);
+                clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
+                clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
         }
 
         /*
          * Let's initially set up CLKO with OSC24M, since this configuration
          * is widely used by imx6q board designs to clock audio codec.
          */
-        ret = clk_set_parent(clk[cko2_sel], clk[osc]);
+        ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
         if (!ret)
-                ret = clk_set_parent(clk[cko], clk[cko2]);
+                ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
         if (ret)
                 pr_warn("failed to set up CLKO: %d\n", ret);
 
         /* Audio-related clocks configuration */
-        clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
+        clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
 
         /* All existing boards with PCIe use LVDS1 */
         if (IS_ENABLED(CONFIG_PCI_IMX6))
-                clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
+                clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
 
         /* Set initial power mode */
         imx6q_set_lpm(WAIT_CLOCKED);
-
-        mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"));
 }
 CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 21cf06cebade..fef46faf692f 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -312,6 +312,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         clks[IMX6SL_CLK_ECSPI2]       = imx_clk_gate2("ecspi2",       "ecspi_root",        base + 0x6c, 2);
         clks[IMX6SL_CLK_ECSPI3]       = imx_clk_gate2("ecspi3",       "ecspi_root",        base + 0x6c, 4);
         clks[IMX6SL_CLK_ECSPI4]       = imx_clk_gate2("ecspi4",       "ecspi_root",        base + 0x6c, 6);
+        clks[IMX6SL_CLK_ENET]         = imx_clk_gate2("enet",         "ipg",               base + 0x6c, 10);
         clks[IMX6SL_CLK_EPIT1]        = imx_clk_gate2("epit1",        "perclk",            base + 0x6c, 12);
         clks[IMX6SL_CLK_EPIT2]        = imx_clk_gate2("epit2",        "perclk",            base + 0x6c, 14);
         clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16);
@@ -347,18 +348,12 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         clks[IMX6SL_CLK_USDHC3]       = imx_clk_gate2("usdhc3",       "usdhc3_podf",       base + 0x80, 6);
         clks[IMX6SL_CLK_USDHC4]       = imx_clk_gate2("usdhc4",       "usdhc4_podf",       base + 0x80, 8);
 
-        for (i = 0; i < ARRAY_SIZE(clks); i++)
-                if (IS_ERR(clks[i]))
-                        pr_err("i.MX6SL clk %d: register failed with %ld\n",
-                                i, PTR_ERR(clks[i]));
+        imx_check_clocks(clks, ARRAY_SIZE(clks));
 
         clk_data.clks = clks;
         clk_data.clk_num = ARRAY_SIZE(clks);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
-
         /* Ensure the AHB clk is at 132MHz. */
         ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
         if (ret)
@@ -382,8 +377,5 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 
         /* Set initial power mode */
         imx6q_set_lpm(WAIT_CLOCKED);
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
-        mxc_timer_init_dt(np);
 }
 CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index 72f8902235d1..ecde72bdfe88 100644
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -124,6 +124,9 @@ static struct clk_div_table video_div_table[] = {
 static u32 share_count_asrc;
 static u32 share_count_audio;
 static u32 share_count_esai;
+static u32 share_count_ssi1;
+static u32 share_count_ssi2;
+static u32 share_count_ssi3;
 
 static void __init imx6sx_clocks_init(struct device_node *ccm_node)
 {
@@ -409,12 +412,12 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
         clks[IMX6SX_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
         clks[IMX6SX_CLK_AUDIO]        = imx_clk_gate2_shared("audio",  "audio_podf",        base + 0x7c, 14, &share_count_audio);
         clks[IMX6SX_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",  "spdif_podf",        base + 0x7c, 14, &share_count_audio);
-        clks[IMX6SX_CLK_SSI1_IPG]     = imx_clk_gate2("ssi1_ipg",      "ipg",               base + 0x7c, 18);
-        clks[IMX6SX_CLK_SSI2_IPG]     = imx_clk_gate2("ssi2_ipg",      "ipg",               base + 0x7c, 20);
-        clks[IMX6SX_CLK_SSI3_IPG]     = imx_clk_gate2("ssi3_ipg",      "ipg",               base + 0x7c, 22);
-        clks[IMX6SX_CLK_SSI1]         = imx_clk_gate2("ssi1",          "ssi1_podf",         base + 0x7c, 18);
-        clks[IMX6SX_CLK_SSI2]         = imx_clk_gate2("ssi2",          "ssi2_podf",         base + 0x7c, 20);
-        clks[IMX6SX_CLK_SSI3]         = imx_clk_gate2("ssi3",          "ssi3_podf",         base + 0x7c, 22);
+        clks[IMX6SX_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
+        clks[IMX6SX_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
+        clks[IMX6SX_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
+        clks[IMX6SX_CLK_SSI1]         = imx_clk_gate2_shared("ssi1",          "ssi1_podf",  base + 0x7c, 18, &share_count_ssi1);
+        clks[IMX6SX_CLK_SSI2]         = imx_clk_gate2_shared("ssi2",          "ssi2_podf",  base + 0x7c, 20, &share_count_ssi2);
+        clks[IMX6SX_CLK_SSI3]         = imx_clk_gate2_shared("ssi3",          "ssi3_podf",  base + 0x7c, 22, &share_count_ssi3);
         clks[IMX6SX_CLK_UART_IPG]     = imx_clk_gate2("uart_ipg",      "ipg",               base + 0x7c, 24);
         clks[IMX6SX_CLK_UART_SERIAL]  = imx_clk_gate2("uart_serial",   "uart_podf",         base + 0x7c, 26);
         clks[IMX6SX_CLK_SAI1_IPG]     = imx_clk_gate2("sai1_ipg",      "ipg",               base + 0x7c, 28);
@@ -443,17 +446,12 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
         /* mask handshake of mmdc */
         writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
 
-        for (i = 0; i < ARRAY_SIZE(clks); i++)
-                if (IS_ERR(clks[i]))
-                        pr_err("i.MX6sx clk %d: register failed with %ld\n", i, PTR_ERR(clks[i]));
+        imx_check_clocks(clks, ARRAY_SIZE(clks));
 
         clk_data.clks = clks;
         clk_data.clk_num = ARRAY_SIZE(clks);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        clk_register_clkdev(clks[IMX6SX_CLK_GPT_BUS], "ipg", "imx-gpt.0");
-        clk_register_clkdev(clks[IMX6SX_CLK_GPT_SERIAL], "per", "imx-gpt.0");
-
         for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
                 clk_prepare_enable(clks[clks_init_on[i]]);
 
@@ -517,8 +515,5 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
 
         /* Set initial power mode */
         imx6q_set_lpm(WAIT_CLOCKED);
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-gpt");
-        mxc_timer_init_dt(np);
 }
 CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index 22dc3ee21fd4..f60d6d569ce3 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -295,14 +295,18 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
 
         clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1));
 
-        clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
-        clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
+        clk[VF610_CLK_FLEXCAN0_EN] = imx_clk_gate("flexcan0_en", "ipg_bus", CCM_CSCDR2, 11);
+        clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "flexcan0_en", CCM_CCGR0, CCM_CCGRx_CGn(0));
+        clk[VF610_CLK_FLEXCAN1_EN] = imx_clk_gate("flexcan1_en", "ipg_bus", CCM_CSCDR2, 12);
+        clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "flexcan1_en", CCM_CCGR9, CCM_CCGRx_CGn(4));
 
         clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4));
         clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5));
         clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1));
         clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2));
 
+        imx_check_clocks(clk, ARRAY_SIZE(clk));
+
         clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
         clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
         clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
index edc35df7bed4..df12b5307175 100644
--- a/arch/arm/mach-imx/clk.c
+++ b/arch/arm/mach-imx/clk.c
@@ -7,6 +7,16 @@
 
 DEFINE_SPINLOCK(imx_ccm_lock);
 
+void __init imx_check_clocks(struct clk *clks[], unsigned int count)
+{
+        unsigned i;
+
+        for (i = 0; i < count; i++)
+                if (IS_ERR(clks[i]))
+                        pr_err("i.MX clk %u: register failed with %ld\n",
+                               i, PTR_ERR(clks[i]));
+}
+
 static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
 {
         struct of_phandle_args phandle;
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index e29f6ebe9f39..d5ba76fee115 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -6,6 +6,8 @@
 
 extern spinlock_t imx_ccm_lock;
 
+void imx_check_clocks(struct clk *clks[], unsigned int count);
+
 extern void imx_cscmr1_fixup(u32 *val);
 
 struct clk *imx_clk_pllv1(const char *name, const char *parent,
@@ -95,6 +97,13 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent,
                         shift, 0, &imx_ccm_lock);
 }
 
+static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
+                void __iomem *reg, u8 shift)
+{
+        return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+                        shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
+}
+
 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
                 u8 shift, u8 width, const char **parents, int num_parents)
 {
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 9ab785ce13e8..22ba8973bcb9 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -19,6 +19,7 @@ struct pt_regs;
 struct clk;
 struct device_node;
 enum mxc_cpu_pwr_mode;
+struct of_device_id;
 
 void mx1_map_io(void);
 void mx21_map_io(void);
@@ -26,48 +27,34 @@ void mx25_map_io(void);
 void mx27_map_io(void);
 void mx31_map_io(void);
 void mx35_map_io(void);
-void mx51_map_io(void);
-void mx53_map_io(void);
 void imx1_init_early(void);
 void imx21_init_early(void);
 void imx25_init_early(void);
 void imx27_init_early(void);
 void imx31_init_early(void);
 void imx35_init_early(void);
-void imx51_init_early(void);
-void imx53_init_early(void);
 void mxc_init_irq(void __iomem *);
-void tzic_init_irq(void __iomem *);
+void tzic_init_irq(void);
 void mx1_init_irq(void);
 void mx21_init_irq(void);
 void mx25_init_irq(void);
 void mx27_init_irq(void);
 void mx31_init_irq(void);
 void mx35_init_irq(void);
-void mx51_init_irq(void);
-void mx53_init_irq(void);
 void imx1_soc_init(void);
 void imx21_soc_init(void);
 void imx25_soc_init(void);
 void imx27_soc_init(void);
 void imx31_soc_init(void);
 void imx35_soc_init(void);
-void imx51_soc_init(void);
-void imx51_init_late(void);
-void imx53_init_late(void);
 void epit_timer_init(void __iomem *base, int irq);
 void mxc_timer_init(void __iomem *, int);
-void mxc_timer_init_dt(struct device_node *);
 int mx1_clocks_init(unsigned long fref);
 int mx21_clocks_init(unsigned long lref, unsigned long fref);
 int mx25_clocks_init(void);
 int mx27_clocks_init(unsigned long fref);
 int mx31_clocks_init(unsigned long fref);
 int mx35_clocks_init(void);
-int mx51_clocks_init(unsigned long ckil, unsigned long osc,
-                        unsigned long ckih1, unsigned long ckih2);
-int mx25_clocks_init_dt(void);
-int mx27_clocks_init_dt(void);
 int mx31_clocks_init_dt(void);
 struct platform_device *mxc_register_gpio(char *name, int id,
         resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
@@ -75,8 +62,10 @@ void mxc_set_cpu_type(unsigned int type);
 void mxc_restart(enum reboot_mode, const char *);
 void mxc_arch_reset_init(void __iomem *);
 void mxc_arch_reset_init_dt(void);
+int mx51_revision(void);
 int mx53_revision(void);
 void imx_set_aips(void __iomem *);
+void imx_aips_allow_unprivileged_access(const char *compat);
 int mxc_device_init(void);
 void imx_set_soc_revision(unsigned int rev);
 unsigned int imx_get_soc_revision(void);
@@ -117,7 +106,7 @@ static inline void imx_scu_standby_enable(void) {}
 #endif
 void imx_src_init(void);
 void imx_gpc_init(void);
-void imx_gpc_pre_suspend(void);
+void imx_gpc_pre_suspend(bool arm_power_off);
 void imx_gpc_post_resume(void);
 void imx_gpc_mask_all(void);
 void imx_gpc_restore_all(void);
@@ -127,7 +116,7 @@ void imx_anatop_init(void);
 void imx_anatop_pre_suspend(void);
 void imx_anatop_post_resume(void);
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
-void imx6q_set_int_mem_clk_lpm(void);
+void imx6q_set_int_mem_clk_lpm(bool enable);
 void imx6sl_set_wait_clk(bool enter);
 
 void imx_cpu_die(unsigned int cpu);
@@ -144,12 +133,17 @@ static inline void imx6_suspend(void __iomem *ocram_vbase) {}
 void imx6q_pm_init(void);
 void imx6dl_pm_init(void);
 void imx6sl_pm_init(void);
+void imx6sx_pm_init(void);
 void imx6q_pm_set_ccm_base(void __iomem *base);
 
 #ifdef CONFIG_PM
-void imx5_pm_init(void);
+void imx51_pm_init(void);
+void imx53_pm_init(void);
+void imx5_pm_set_ccm_base(void __iomem *base);
 #else
-static inline void imx5_pm_init(void) {}
+static inline void imx51_pm_init(void) {}
+static inline void imx53_pm_init(void) {}
+static inline void imx5_pm_set_ccm_base(void __iomem *base) {}
 #endif
 
 #ifdef CONFIG_NEON
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index c1c99a72c6a1..3403bac94a31 100644
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -16,6 +16,8 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include "hardware.h"
 #include "common.h"
@@ -24,10 +26,26 @@ static int mx5_cpu_rev = -1;
 
 #define IIM_SREV 0x24
 
+static u32 imx5_read_srev_reg(const char *compat)
+{
+        void __iomem *iim_base;
+        struct device_node *np;
+        u32 srev;
+
+        np = of_find_compatible_node(NULL, NULL, compat);
+        iim_base = of_iomap(np, 0);
+        WARN_ON(!iim_base);
+
+        srev = readl(iim_base + IIM_SREV) & 0xff;
+
+        iounmap(iim_base);
+
+        return srev;
+}
+
 static int get_mx51_srev(void)
 {
-        void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
-        u32 rev = readl(iim_base + IIM_SREV) & 0xff;
+        u32 rev = imx5_read_srev_reg("fsl,imx51-iim");
 
         switch (rev) {
         case 0x0:
@@ -77,8 +95,7 @@ int __init mx51_neon_fixup(void)
 
 static int get_mx53_srev(void)
 {
-        void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
-        u32 rev = readl(iim_base + IIM_SREV) & 0xff;
+        u32 rev = imx5_read_srev_reg("fsl,imx53-iim");
 
         switch (rev) {
         case 0x0:
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index bbe8ff1f0412..df42c14ff749 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -2,6 +2,7 @@
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/slab.h>
 #include <linux/sys_soc.h>
 
@@ -60,6 +61,18 @@ void __init imx_set_aips(void __iomem *base)
         __raw_writel(reg, base + 0x50);
 }
 
+void __init imx_aips_allow_unprivileged_access(
+                const char *compat)
+{
+        void __iomem *aips_base_addr;
+        struct device_node *np;
+
+        for_each_compatible_node(np, NULL, compat) {
+                aips_base_addr = of_iomap(np, 0);
+                imx_set_aips(aips_base_addr);
+        }
+}
+
 struct device * __init imx_soc_device_init(void)
 {
         struct soc_device_attribute *soc_dev_attr;
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index 6bcae0479049..10844d3bb926 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -13,6 +13,7 @@
 
 #include "common.h"
 #include "cpuidle.h"
+#include "hardware.h"
 
 static atomic_t master = ATOMIC_INIT(0);
 static DEFINE_SPINLOCK(master_lock);
@@ -66,10 +67,11 @@ static struct cpuidle_driver imx6q_cpuidle_driver = {
 int __init imx6q_cpuidle_init(void)
 {
         /* Need to enable SCU standby for entering WAIT modes */
-        imx_scu_standby_enable();
+        if (!cpu_is_imx6sx())
+                imx_scu_standby_enable();
 
         /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
-        imx6q_set_int_mem_clk_lpm();
+        imx6q_set_int_mem_clk_lpm(true);
 
         return cpuidle_register(&imx6q_cpuidle_driver, NULL);
 }
diff --git a/arch/arm/mach-imx/crm-regs-imx5.h b/arch/arm/mach-imx/crm-regs-imx5.h
deleted file mode 100644
index 5e3f1f0f4cab..000000000000
--- a/arch/arm/mach-imx/crm-regs-imx5.h
+++ /dev/null
@@ -1,600 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-
-#define MX51_CCM_BASE           MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
-#define MX51_DPLL1_BASE         MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
-#define MX51_DPLL2_BASE         MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
-#define MX51_DPLL3_BASE         MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
-#define MX51_CORTEXA8_BASE      MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
-#define MX51_GPC_BASE           MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
-
-/*MX53*/
-#define MX53_CCM_BASE           MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
-#define MX53_DPLL1_BASE         MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
-#define MX53_DPLL2_BASE         MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
-#define MX53_DPLL3_BASE         MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
-#define MX53_DPLL4_BASE         MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR)
-
-/* PLL Register Offsets */
-#define MXC_PLL_DP_CTL                  0x00
-#define MXC_PLL_DP_CONFIG               0x04
-#define MXC_PLL_DP_OP                   0x08
-#define MXC_PLL_DP_MFD                  0x0C
-#define MXC_PLL_DP_MFN                  0x10
-#define MXC_PLL_DP_MFNMINUS             0x14
-#define MXC_PLL_DP_MFNPLUS              0x18
-#define MXC_PLL_DP_HFS_OP               0x1C
-#define MXC_PLL_DP_HFS_MFD              0x20
-#define MXC_PLL_DP_HFS_MFN              0x24
-#define MXC_PLL_DP_MFN_TOGC             0x28
-#define MXC_PLL_DP_DESTAT               0x2c
-
-/* PLL Register Bit definitions */
-#define MXC_PLL_DP_CTL_MUL_CTRL         0x2000
-#define MXC_PLL_DP_CTL_DPDCK0_2_EN      0x1000
-#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET  12
-#define MXC_PLL_DP_CTL_ADE              0x800
-#define MXC_PLL_DP_CTL_REF_CLK_DIV      0x400
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET       8
-#define MXC_PLL_DP_CTL_HFSM             0x80
-#define MXC_PLL_DP_CTL_PRE              0x40
-#define MXC_PLL_DP_CTL_UPEN             0x20
-#define MXC_PLL_DP_CTL_RST              0x10
-#define MXC_PLL_DP_CTL_RCP              0x8
-#define MXC_PLL_DP_CTL_PLM              0x4
-#define MXC_PLL_DP_CTL_BRM0             0x2
-#define MXC_PLL_DP_CTL_LRF              0x1
-
-#define MXC_PLL_DP_CONFIG_BIST          0x8
-#define MXC_PLL_DP_CONFIG_SJC_CE        0x4
-#define MXC_PLL_DP_CONFIG_AREN          0x2
-#define MXC_PLL_DP_CONFIG_LDREQ         0x1
-
-#define MXC_PLL_DP_OP_MFI_OFFSET        4
-#define MXC_PLL_DP_OP_MFI_MASK          (0xF << 4)
-#define MXC_PLL_DP_OP_PDF_OFFSET        0
-#define MXC_PLL_DP_OP_PDF_MASK          0xF
-
-#define MXC_PLL_DP_MFD_OFFSET           0
-#define MXC_PLL_DP_MFD_MASK             0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_OFFSET           0x0
-#define MXC_PLL_DP_MFN_MASK             0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_TOGC_TOG_DIS     (1 << 17)
-#define MXC_PLL_DP_MFN_TOGC_TOG_EN      (1 << 16)
-#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET  0x0
-#define MXC_PLL_DP_MFN_TOGC_CNT_MASK    0xFFFF
-
-#define MXC_PLL_DP_DESTAT_TOG_SEL       (1 << 31)
-#define MXC_PLL_DP_DESTAT_MFN           0x07FFFFFF
-
-/* Register addresses of CCM*/
-#define MXC_CCM_CCR             (MX51_CCM_BASE + 0x00)
-#define MXC_CCM_CCDR            (MX51_CCM_BASE + 0x04)
-#define MXC_CCM_CSR             (MX51_CCM_BASE + 0x08)
-#define MXC_CCM_CCSR            (MX51_CCM_BASE + 0x0C)
-#define MXC_CCM_CACRR           (MX51_CCM_BASE + 0x10)
-#define MXC_CCM_CBCDR           (MX51_CCM_BASE + 0x14)
-#define MXC_CCM_CBCMR           (MX51_CCM_BASE + 0x18)
-#define MXC_CCM_CSCMR1          (MX51_CCM_BASE + 0x1C)
-#define MXC_CCM_CSCMR2          (MX51_CCM_BASE + 0x20)
-#define MXC_CCM_CSCDR1          (MX51_CCM_BASE + 0x24)
-#define MXC_CCM_CS1CDR          (MX51_CCM_BASE + 0x28)
-#define MXC_CCM_CS2CDR          (MX51_CCM_BASE + 0x2C)
-#define MXC_CCM_CDCDR           (MX51_CCM_BASE + 0x30)
-#define MXC_CCM_CHSCDR          (MX51_CCM_BASE + 0x34)
-#define MXC_CCM_CSCDR2          (MX51_CCM_BASE + 0x38)
-#define MXC_CCM_CSCDR3          (MX51_CCM_BASE + 0x3C)
-#define MXC_CCM_CSCDR4          (MX51_CCM_BASE + 0x40)
-#define MXC_CCM_CWDR            (MX51_CCM_BASE + 0x44)
-#define MXC_CCM_CDHIPR          (MX51_CCM_BASE + 0x48)
-#define MXC_CCM_CDCR            (MX51_CCM_BASE + 0x4C)
-#define MXC_CCM_CTOR            (MX51_CCM_BASE + 0x50)
-#define MXC_CCM_CLPCR           (MX51_CCM_BASE + 0x54)
-#define MXC_CCM_CISR            (MX51_CCM_BASE + 0x58)
-#define MXC_CCM_CIMR            (MX51_CCM_BASE + 0x5C)
-#define MXC_CCM_CCOSR           (MX51_CCM_BASE + 0x60)
-#define MXC_CCM_CGPR            (MX51_CCM_BASE + 0x64)
-#define MXC_CCM_CCGR0           (MX51_CCM_BASE + 0x68)
-#define MXC_CCM_CCGR1           (MX51_CCM_BASE + 0x6C)
-#define MXC_CCM_CCGR2           (MX51_CCM_BASE + 0x70)
-#define MXC_CCM_CCGR3           (MX51_CCM_BASE + 0x74)
-#define MXC_CCM_CCGR4           (MX51_CCM_BASE + 0x78)
-#define MXC_CCM_CCGR5           (MX51_CCM_BASE + 0x7C)
-#define MXC_CCM_CCGR6           (MX51_CCM_BASE + 0x80)
-#define MXC_CCM_CCGR7           (MX51_CCM_BASE + 0x84)
-
-#define MXC_CCM_CMEOR           (MX51_CCM_BASE + 0x84)
-
-/* Define the bits in register CCR */
-#define MXC_CCM_CCR_COSC_EN             (1 << 12)
-#define MXC_CCM_CCR_FPM_MULT_MASK       (1 << 11)
-#define MXC_CCM_CCR_CAMP2_EN            (1 << 10)
-#define MXC_CCM_CCR_CAMP1_EN            (1 << 9)
-#define MXC_CCM_CCR_FPM_EN              (1 << 8)
-#define MXC_CCM_CCR_OSCNT_OFFSET        (0)
-#define MXC_CCM_CCR_OSCNT_MASK  (0xFF)
-
-/* Define the bits in register CCDR */
-#define MXC_CCM_CCDR_HSC_HS_MASK        (0x1 << 18)
-#define MXC_CCM_CCDR_IPU_HS_MASK        (0x1 << 17)
-#define MXC_CCM_CCDR_EMI_HS_MASK        (0x1 << 16)
-
-/* Define the bits in register CSR */
-#define MXC_CCM_CSR_COSR_READY  (1 << 5)
-#define MXC_CCM_CSR_LVS_VALUE   (1 << 4)
-#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
-#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
-#define MXC_CCM_CSR_FPM_READY   (1 << 1)
-#define MXC_CCM_CSR_REF_EN_B    (1 << 0)
-
-/* Define the bits in register CCSR */
-#define MXC_CCM_CCSR_LP_APM_SEL         (0x1 << 9)
-#define MXC_CCM_CCSR_STEP_SEL_OFFSET    (7)
-#define MXC_CCM_CCSR_STEP_SEL_MASK      (0x3 << 7)
-#define MXC_CCM_CCSR_STEP_SEL_LP_APM       0
-#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS  1 /* Only when JTAG connected? */
-#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
-#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
-#define MXC_CCM_CCSR_PLL2_PODF_OFFSET   (5)
-#define MXC_CCM_CCSR_PLL2_PODF_MASK     (0x3 << 5)
-#define MXC_CCM_CCSR_PLL3_PODF_OFFSET   (3)
-#define MXC_CCM_CCSR_PLL3_PODF_MASK     (0x3 << 3)
-#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL    (1 << 2) /* 0: pll1_main_clk,
-                                                    1: step_clk */
-#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL    (1 << 1)
-#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL    (1 << 0)
-
-/* Define the bits in register CACRR */
-#define MXC_CCM_CACRR_ARM_PODF_OFFSET   (0)
-#define MXC_CCM_CACRR_ARM_PODF_MASK     (0x7)
-
-/* Define the bits in register CBCDR */
-#define MXC_CCM_CBCDR_EMI_CLK_SEL               (0x1 << 26)
-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL            (0x1 << 25)
-#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET         (30)
-#define MXC_CCM_CBCDR_DDR_HF_SEL                (0x1 << 30)
-#define MXC_CCM_CBCDR_DDR_PODF_OFFSET           (27)
-#define MXC_CCM_CBCDR_DDR_PODF_MASK             (0x7 << 27)
-#define MXC_CCM_CBCDR_EMI_PODF_OFFSET           (22)
-#define MXC_CCM_CBCDR_EMI_PODF_MASK             (0x7 << 22)
-#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET         (19)
-#define MXC_CCM_CBCDR_AXI_B_PODF_MASK           (0x7 << 19)
-#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET         (16)
-#define MXC_CCM_CBCDR_AXI_A_PODF_MASK           (0x7 << 16)
-#define MXC_CCM_CBCDR_NFC_PODF_OFFSET           (13)
-#define MXC_CCM_CBCDR_NFC_PODF_MASK             (0x7 << 13)
-#define MXC_CCM_CBCDR_AHB_PODF_OFFSET           (10)
-#define MXC_CCM_CBCDR_AHB_PODF_MASK             (0x7 << 10)
-#define MXC_CCM_CBCDR_IPG_PODF_OFFSET           (8)
-#define MXC_CCM_CBCDR_IPG_PODF_MASK             (0x3 << 8)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET       (6)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK         (0x3 << 6)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET       (3)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK         (0x7 << 3)
-#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET        (0)
-#define MXC_CCM_CBCDR_PERCLK_PODF_MASK          (0x7)
-
-/* Define the bits in register CBCMR */
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET    (14)
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK      (0x3 << 14)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET     (12)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK       (0x3 << 12)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET        (10)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK          (0x3 << 10)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET    (8)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK      (0x3 << 8)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET    (6)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK      (0x3 << 6)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET        (4)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK          (0x3 << 4)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET      (14)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK        (0x3 << 14)
-#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL     (0x1 << 1)
-#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL        (0x1 << 0)
-
-/* Define the bits in register CSCMR1 */
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET          (30)
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK            (0x3 << 30)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET          (28)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK            (0x3 << 28)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET           (26)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL                  (0x1 << 26)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET              (24)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK                (0x3 << 24)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET            (22)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK              (0x3 << 22)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET      (20)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK        (0x3 << 20)
-#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL                   (0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL        (0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL                   (0x1 << 18)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET      (16)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK        (0x3 << 16)
-#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET       (16)
-#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK         (0x3 << 16)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET              (14)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK                (0x3 << 14)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET              (12)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK                (0x3 << 12)
-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL                     (0x1 << 11)
-#define MXC_CCM_CSCMR1_VPU_RCLK_SEL                     (0x1 << 10)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET           (8)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK             (0x3 << 8)
-#define MXC_CCM_CSCMR1_TVE_CLK_SEL                      (0x1 << 7)
-#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL                  (0x1 << 6)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET              (4)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK                (0x3 << 4)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET             (2)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK               (0x3 << 2)
-#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL             (0x1 << 1)
-#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL             (0x1)
-
-/* Define the bits in register CSCMR2 */
-#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n)             (26+n*3)
-#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n)               (0x7 << (26+n*3))
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET         (24)
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK           (0x3 << 24)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET         (22)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK           (0x3 << 22)
-#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET               (20)
-#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK                 (0x3 << 20)
-#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET              (18)
-#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK                (0x3 << 18)
-#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET              (16)
-#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK                (0x3 << 16)
-#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET             (14)
-#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK               (0x3 << 14)
-#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET              (12)
-#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK                (0x3 << 12)
-#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET               (10)
-#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK                 (0x3 << 10)
-#define MXC_CCM_CSCMR2_SLIMBUS_COM                      (0x1 << 9)
-#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET           (6)
-#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK             (0x7 << 6)
-#define MXC_CCM_CSCMR2_SPDIF1_COM                       (1 << 5)
-#define MXC_CCM_CSCMR2_SPDIF0_COM                       (1 << 4)
-#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET            (2)
-#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK              (0x3 << 2)
-#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET            (0)
-#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK              (0x3)
-
-/* Define the bits in register CSCDR1 */
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET     (22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK       (0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET     (19)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK       (0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET      (22)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK        (0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET      (19)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK        (0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET     (16)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK       (0x7 << 16)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET              (14)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK                (0x3 << 14)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET     (11)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK       (0x7 << 11)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET           (8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK             (0x7 << 8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET           (6)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK             (0x3 << 6)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET             (3)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK               (0x7 << 3)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET             (0)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK               (0x7)
-
-/* Define the bits in register CS1CDR and CS2CDR */
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET         (22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK           (0x7 << 22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET         (16)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK           (0x3F << 16)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET             (6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK               (0x7 << 6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET             (0)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK               (0x3F)
-
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET         (22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK           (0x7 << 22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET         (16)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK           (0x3F << 16)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET             (6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK               (0x7 << 6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET             (0)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK               (0x3F)
-
-/* Define the bits in register CDCDR */
-#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET               (28)
-#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK                 (0x7 << 28)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET            (25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK              (0x7 << 25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET            (19)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK              (0x3F << 19)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET            (16)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK              (0x7 << 16)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET            (9)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK              (0x3F << 9)
-#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET                (6)
-#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK                  (0x7 << 6)
-#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET               (3)
-#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK                 (0x7 << 3)
-#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET               (0)
-#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK                 (0x7)
-
-/* Define the bits in register CHSCCDR */
-#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET             (12)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK               (0x7 << 12)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET             (6)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK               (0x3F << 6)
-#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET            (3)
-#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK              (0x7 << 3)
-#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET            (0)
-#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK              (0x7)
-
-/* Define the bits in register CSCDR2 */
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET             (25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK               (0x7 << 25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET             (19)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK               (0x3F << 19)
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET              (16)
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK                (0x7 << 16)
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET              (9)
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK                (0x3F << 9)
-#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET          (6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK                (0x7 << 6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET              (0)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK                (0x3F)
-
-/* Define the bits in register CSCDR3 */
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET            (16)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK              (0x7 << 16)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET            (9)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK              (0x3F << 9)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET             (6)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK               (0x7 << 6)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET             (0)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK               (0x3F)
-
-/* Define the bits in register CSCDR4 */
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET        (16)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK          (0x7 << 16)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET        (9)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK          (0x3F << 9)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET        (6)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK          (0x7 << 6)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET        (0)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK          (0x3F)
-
-/* Define the bits in register CDHIPR */
-#define MXC_CCM_CDHIPR_ARM_PODF_BUSY                    (1 << 16)
-#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY              (1 << 8)
-#define MXC_CCM_CDHIPR_DDR_PODF_BUSY                    (1 << 7)
-#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY                 (1 << 6)
-#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY              (1 << 5)
-#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY        (1 << 4)
-#define MXC_CCM_CDHIPR_AHB_PODF_BUSY                    (1 << 3)
-#define MXC_CCM_CDHIPR_EMI_PODF_BUSY                    (1 << 2)
-#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY                  (1 << 1)
-#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY                  (1 << 0)
-
-/* Define the bits in register CDCR */
-#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER             (0x1 << 2)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET        (0)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK          (0x3)
-
-/* Define the bits in register CLPCR */
-#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS         (0x1 << 23)
-#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS         (0x1 << 22)
-#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS                (0x1 << 21)
-#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS                (0x1 << 25)
-#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS        (0x1 << 20)
-#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS         (0x1 << 19)
-#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS         (0x1 << 18)
-#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS        (0x1 << 17)
-#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS        (0x1 << 16)
-#define MXC_CCM_CLPCR_COSC_PWRDOWN              (0x1 << 11)
-#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET         (9)
-#define MXC_CCM_CLPCR_STBY_COUNT_MASK           (0x3 << 9)
-#define MXC_CCM_CLPCR_VSTBY                     (0x1 << 8)
-#define MXC_CCM_CLPCR_DIS_REF_OSC               (0x1 << 7)
-#define MXC_CCM_CLPCR_SBYOS                     (0x1 << 6)
-#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM        (0x1 << 5)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET       (3)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK         (0x3 << 3)
-#define MXC_CCM_CLPCR_LPM_OFFSET                (0)
-#define MXC_CCM_CLPCR_LPM_MASK                  (0x3)
-
-/* Define the bits in register CISR */
-#define MXC_CCM_CISR_ARM_PODF_LOADED                    (0x1 << 25)
-#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED        (0x1 << 21)
-#define MXC_CCM_CISR_AHB_PODF_LOADED                    (0x1 << 20)
-#define MXC_CCM_CISR_EMI_PODF_LOADED                    (0x1 << 19)
-#define MXC_CCM_CISR_AXI_B_PODF_LOADED                  (0x1 << 18)
-#define MXC_CCM_CISR_AXI_A_PODF_LOADED                  (0x1 << 17)
-#define MXC_CCM_CISR_DIVIDER_LOADED                     (0x1 << 16)
-#define MXC_CCM_CISR_COSC_READY                         (0x1 << 6)
-#define MXC_CCM_CISR_CKIH2_READY                        (0x1 << 5)
-#define MXC_CCM_CISR_CKIH_READY                         (0x1 << 4)
-#define MXC_CCM_CISR_FPM_READY                          (0x1 << 3)
-#define MXC_CCM_CISR_LRF_PLL3                           (0x1 << 2)
-#define MXC_CCM_CISR_LRF_PLL2                           (0x1 << 1)
-#define MXC_CCM_CISR_LRF_PLL1                           (0x1)
-
-/* Define the bits in register CIMR */
-#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED               (0x1 << 25)
-#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED   (0x1 << 21)
-#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED               (0x1 << 20)
-#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED             (0x1 << 19)
-#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED             (0x1 << 18)
-#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED             (0x1 << 17)
-#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED                (0x1 << 16)
-#define MXC_CCM_CIMR_MASK_COSC_READY                    (0x1 << 5)
-#define MXC_CCM_CIMR_MASK_CKIH_READY                    (0x1 << 4)
-#define MXC_CCM_CIMR_MASK_FPM_READY                     (0x1 << 3)
-#define MXC_CCM_CIMR_MASK_LRF_PLL3                      (0x1 << 2)
-#define MXC_CCM_CIMR_MASK_LRF_PLL2                      (0x1 << 1)
-#define MXC_CCM_CIMR_MASK_LRF_PLL1                      (0x1)
-
-/* Define the bits in register CCOSR */
-#define MXC_CCM_CCOSR_CKO2_EN_OFFSET                    (0x1 << 24)
-#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET                   (21)
-#define MXC_CCM_CCOSR_CKO2_DIV_MASK                     (0x7 << 21)
-#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET                   (16)
-#define MXC_CCM_CCOSR_CKO2_SEL_MASK                     (0x1F << 16)
-#define MXC_CCM_CCOSR_CKOL_EN                           (0x1 << 7)
-#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET                   (4)
-#define MXC_CCM_CCOSR_CKOL_DIV_MASK                     (0x7 << 4)
-#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET                   (0)
-#define MXC_CCM_CCOSR_CKOL_SEL_MASK                     (0xF)
-
-/* Define the bits in registers CGPR */
-#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE             (0x1 << 4)
-#define MXC_CCM_CGPR_FPM_SEL                            (0x1 << 3)
-#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET            (0)
-#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK              (0x7)
-
-/* Define the bits in registers CCGRx */
-#define MXC_CCM_CCGRx_CG_MASK                           0x3
-#define MXC_CCM_CCGRx_MOD_OFF                           0x0
-#define MXC_CCM_CCGRx_MOD_ON                            0x3
-#define MXC_CCM_CCGRx_MOD_IDLE                          0x1
-
-#define MXC_CCM_CCGRx_CG15_MASK                         (0x3 << 30)
-#define MXC_CCM_CCGRx_CG14_MASK                         (0x3 << 28)
-#define MXC_CCM_CCGRx_CG13_MASK                         (0x3 << 26)
-#define MXC_CCM_CCGRx_CG12_MASK                         (0x3 << 24)
-#define MXC_CCM_CCGRx_CG11_MASK                         (0x3 << 22)
-#define MXC_CCM_CCGRx_CG10_MASK                         (0x3 << 20)
-#define MXC_CCM_CCGRx_CG9_MASK                          (0x3 << 18)
-#define MXC_CCM_CCGRx_CG8_MASK                          (0x3 << 16)
-#define MXC_CCM_CCGRx_CG5_MASK                          (0x3 << 10)
-#define MXC_CCM_CCGRx_CG4_MASK                          (0x3 << 8)
-#define MXC_CCM_CCGRx_CG3_MASK                          (0x3 << 6)
-#define MXC_CCM_CCGRx_CG2_MASK                          (0x3 << 4)
-#define MXC_CCM_CCGRx_CG1_MASK                          (0x3 << 2)
-#define MXC_CCM_CCGRx_CG0_MASK                          (0x3 << 0)
-
-#define MXC_CCM_CCGRx_CG15_OFFSET                       30
-#define MXC_CCM_CCGRx_CG14_OFFSET                       28
-#define MXC_CCM_CCGRx_CG13_OFFSET                       26
-#define MXC_CCM_CCGRx_CG12_OFFSET                       24
-#define MXC_CCM_CCGRx_CG11_OFFSET                       22
-#define MXC_CCM_CCGRx_CG10_OFFSET                       20
-#define MXC_CCM_CCGRx_CG9_OFFSET                        18
-#define MXC_CCM_CCGRx_CG8_OFFSET                        16
-#define MXC_CCM_CCGRx_CG7_OFFSET                        14
-#define MXC_CCM_CCGRx_CG6_OFFSET                        12
-#define MXC_CCM_CCGRx_CG5_OFFSET                        10
-#define MXC_CCM_CCGRx_CG4_OFFSET                        8
-#define MXC_CCM_CCGRx_CG3_OFFSET                        6
-#define MXC_CCM_CCGRx_CG2_OFFSET                        4
-#define MXC_CCM_CCGRx_CG1_OFFSET                        2
-#define MXC_CCM_CCGRx_CG0_OFFSET                        0
-
-#define MXC_DPTC_LP_BASE        (MX51_GPC_BASE + 0x80)
-#define MXC_DPTC_GP_BASE        (MX51_GPC_BASE + 0x100)
-#define MXC_DVFS_CORE_BASE      (MX51_GPC_BASE + 0x180)
-#define MXC_DPTC_PER_BASE       (MX51_GPC_BASE + 0x1C0)
-#define MXC_PGC_IPU_BASE        (MX51_GPC_BASE + 0x220)
-#define MXC_PGC_VPU_BASE        (MX51_GPC_BASE + 0x240)
-#define MXC_PGC_GPU_BASE        (MX51_GPC_BASE + 0x260)
-#define MXC_SRPG_NEON_BASE      (MX51_GPC_BASE + 0x280)
-#define MXC_SRPG_ARM_BASE       (MX51_GPC_BASE + 0x2A0)
-#define MXC_SRPG_EMPGC0_BASE    (MX51_GPC_BASE + 0x2C0)
-#define MXC_SRPG_EMPGC1_BASE    (MX51_GPC_BASE + 0x2D0)
-#define MXC_SRPG_MEGAMIX_BASE   (MX51_GPC_BASE + 0x2E0)
-#define MXC_SRPG_EMI_BASE       (MX51_GPC_BASE + 0x300)
-
-/* CORTEXA8 platform */
-#define MXC_CORTEXA8_PLAT_PVID          (MX51_CORTEXA8_BASE + 0x0)
-#define MXC_CORTEXA8_PLAT_GPC           (MX51_CORTEXA8_BASE + 0x4)
-#define MXC_CORTEXA8_PLAT_PIC           (MX51_CORTEXA8_BASE + 0x8)
-#define MXC_CORTEXA8_PLAT_LPC           (MX51_CORTEXA8_BASE + 0xC)
-#define MXC_CORTEXA8_PLAT_NEON_LPC      (MX51_CORTEXA8_BASE + 0x10)
-#define MXC_CORTEXA8_PLAT_ICGC          (MX51_CORTEXA8_BASE + 0x14)
-#define MXC_CORTEXA8_PLAT_AMC           (MX51_CORTEXA8_BASE + 0x18)
-#define MXC_CORTEXA8_PLAT_NMC           (MX51_CORTEXA8_BASE + 0x20)
-#define MXC_CORTEXA8_PLAT_NMS           (MX51_CORTEXA8_BASE + 0x24)
-
-/* DVFS CORE */
-#define MXC_DVFSTHRS            (MXC_DVFS_CORE_BASE + 0x00)
-#define MXC_DVFSCOUN            (MXC_DVFS_CORE_BASE + 0x04)
-#define MXC_DVFSSIG1            (MXC_DVFS_CORE_BASE + 0x08)
-#define MXC_DVFSSIG0            (MXC_DVFS_CORE_BASE + 0x0C)
-#define MXC_DVFSGPC0            (MXC_DVFS_CORE_BASE + 0x10)
-#define MXC_DVFSGPC1            (MXC_DVFS_CORE_BASE + 0x14)
-#define MXC_DVFSGPBT            (MXC_DVFS_CORE_BASE + 0x18)
-#define MXC_DVFSEMAC            (MXC_DVFS_CORE_BASE + 0x1C)
-#define MXC_DVFSCNTR            (MXC_DVFS_CORE_BASE + 0x20)
-#define MXC_DVFSLTR0_0          (MXC_DVFS_CORE_BASE + 0x24)
-#define MXC_DVFSLTR0_1          (MXC_DVFS_CORE_BASE + 0x28)
-#define MXC_DVFSLTR1_0          (MXC_DVFS_CORE_BASE + 0x2C)
-#define MXC_DVFSLTR1_1          (MXC_DVFS_CORE_BASE + 0x30)
-#define MXC_DVFSPT0             (MXC_DVFS_CORE_BASE + 0x34)
-#define MXC_DVFSPT1             (MXC_DVFS_CORE_BASE + 0x38)
-#define MXC_DVFSPT2             (MXC_DVFS_CORE_BASE + 0x3C)
-#define MXC_DVFSPT3             (MXC_DVFS_CORE_BASE + 0x40)
-
-/* GPC */
-#define MXC_GPC_CNTR            (MX51_GPC_BASE + 0x0)
-#define MXC_GPC_PGR             (MX51_GPC_BASE + 0x4)
-#define MXC_GPC_VCR             (MX51_GPC_BASE + 0x8)
-#define MXC_GPC_ALL_PU          (MX51_GPC_BASE + 0xC)
-#define MXC_GPC_NEON            (MX51_GPC_BASE + 0x10)
-#define MXC_GPC_PGR_ARMPG_OFFSET        8
-#define MXC_GPC_PGR_ARMPG_MASK          (3 << 8)
-
-/* PGC */
-#define MXC_PGC_IPU_PGCR        (MXC_PGC_IPU_BASE + 0x0)
-#define MXC_PGC_IPU_PGSR        (MXC_PGC_IPU_BASE + 0xC)
-#define MXC_PGC_VPU_PGCR        (MXC_PGC_VPU_BASE + 0x0)
-#define MXC_PGC_VPU_PGSR        (MXC_PGC_VPU_BASE + 0xC)
-#define MXC_PGC_GPU_PGCR        (MXC_PGC_GPU_BASE + 0x0)
-#define MXC_PGC_GPU_PGSR        (MXC_PGC_GPU_BASE + 0xC)
-
-#define MXC_PGCR_PCR            1
-#define MXC_SRPGCR_PCR          1
-#define MXC_EMPGCR_PCR          1
-#define MXC_PGSR_PSR            1
-
-
-#define MXC_CORTEXA8_PLAT_LPC_DSM       (1 << 0)
-#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM   (1 << 1)
-
-/* SRPG */
-#define MXC_SRPG_NEON_SRPGCR    (MXC_SRPG_NEON_BASE + 0x0)
-#define MXC_SRPG_NEON_PUPSCR    (MXC_SRPG_NEON_BASE + 0x4)
-#define MXC_SRPG_NEON_PDNSCR    (MXC_SRPG_NEON_BASE + 0x8)
-
-#define MXC_SRPG_ARM_SRPGCR     (MXC_SRPG_ARM_BASE + 0x0)
-#define MXC_SRPG_ARM_PUPSCR     (MXC_SRPG_ARM_BASE + 0x4)
-#define MXC_SRPG_ARM_PDNSCR     (MXC_SRPG_ARM_BASE + 0x8)
-
-#define MXC_SRPG_EMPGC0_SRPGCR  (MXC_SRPG_EMPGC0_BASE + 0x0)
-#define MXC_SRPG_EMPGC0_PUPSCR  (MXC_SRPG_EMPGC0_BASE + 0x4)
-#define MXC_SRPG_EMPGC0_PDNSCR  (MXC_SRPG_EMPGC0_BASE + 0x8)
-
-#define MXC_SRPG_EMPGC1_SRPGCR  (MXC_SRPG_EMPGC1_BASE + 0x0)
-#define MXC_SRPG_EMPGC1_PUPSCR  (MXC_SRPG_EMPGC1_BASE + 0x4)
-#define MXC_SRPG_EMPGC1_PDNSCR  (MXC_SRPG_EMPGC1_BASE + 0x8)
-
-#define MXC_SRPG_MEGAMIX_SRPGCR         (MXC_SRPG_MEGAMIX_BASE + 0x0)
-#define MXC_SRPG_MEGAMIX_PUPSCR         (MXC_SRPG_MEGAMIX_BASE + 0x4)
-#define MXC_SRPG_MEGAMIX_PDNSCR         (MXC_SRPG_MEGAMIX_BASE + 0x8)
-
-#define MXC_SRPGC_EMI_SRPGCR    (MXC_SRPGC_EMI_BASE + 0x0)
-#define MXC_SRPGC_EMI_PUPSCR    (MXC_SRPGC_EMI_BASE + 0x4)
-#define MXC_SRPGC_EMI_PDNSCR    (MXC_SRPGC_EMI_BASE + 0x8)
-
-#endif                          /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/arch/arm/mach-imx/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h
deleted file mode 100644
index 26389f35a2b2..000000000000
--- a/arch/arm/mach-imx/devices-imx51.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "devices/devices-common.h"
-
-extern const struct imx_fec_data imx51_fec_data;
-#define imx51_add_fec(pdata)    \
-        imx_add_fec(&imx51_fec_data, pdata)
-
-extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data;
-#define imx51_add_fsl_usb2_udc(pdata)   \
-        imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata)
-
-extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
-#define imx51_add_imx_i2c(id, pdata)    \
-        imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
-#define imx51_add_hsi2c(pdata)  \
-        imx51_add_imx_i2c(2, pdata)
-
-extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
-#define imx51_add_imx_ssi(id, pdata)    \
-        imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
-
-extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
-#define imx51_add_imx_uart(id, pdata)   \
-        imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
-
-extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data;
-#define imx51_add_mxc_ehci_otg(pdata)   \
-        imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[];
-#define imx51_add_mxc_ehci_hs(id, pdata)        \
-        imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata)
-
-extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
-#define imx51_add_mxc_nand(pdata)       \
-        imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
-
-extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[];
-#define imx51_add_sdhci_esdhc_imx(id, pdata)    \
-        imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
-
-extern const struct imx_spi_imx_data imx51_cspi_data;
-#define imx51_add_cspi(pdata)   \
-        imx_add_spi_imx(&imx51_cspi_data, pdata)
-
-extern const struct imx_spi_imx_data imx51_ecspi_data[];
-#define imx51_add_ecspi(id, pdata)      \
-        imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
-
-extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
-#define imx51_add_imx2_wdt(id)  \
-        imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
-
-extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
-#define imx51_add_imx_keypad(pdata)     \
-        imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
-
-extern const struct imx_pata_imx_data imx51_pata_imx_data;
-#define imx51_add_pata_imx() \
-        imx_add_pata_imx(&imx51_pata_imx_data)
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 2d260a5a307c..1d2cc1805f3e 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -1,6 +1,6 @@
 config IMX_HAVE_PLATFORM_FEC
         bool
-        default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53
+        default y if SOC_IMX25 || SOC_IMX27 || SOC_IMX35
 
 config IMX_HAVE_PLATFORM_FLEXCAN
         bool
@@ -10,7 +10,6 @@ config IMX_HAVE_PLATFORM_FSL_USB2_UDC
 
 config IMX_HAVE_PLATFORM_GPIO_KEYS
         bool
-        default y if SOC_IMX51
 
 config IMX_HAVE_PLATFORM_IMX21_HCD
         bool
@@ -43,15 +42,9 @@ config IMX_HAVE_PLATFORM_IMX_SSI
 config IMX_HAVE_PLATFORM_IMX_UART
         bool
 
-config IMX_HAVE_PLATFORM_IMX_UDC
-        bool
-
 config IMX_HAVE_PLATFORM_IPU_CORE
         bool
 
-config IMX_HAVE_PLATFORM_MX1_CAMERA
-        bool
-
 config IMX_HAVE_PLATFORM_MX2_CAMERA
         bool
 
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
index 1cbc14cd80d1..8fdb12b4ca7e 100644
--- a/arch/arm/mach-imx/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -16,9 +16,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_PATA_IMX) += platform-pata_imx.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index 61352a80bb59..67f7fb13050d 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -176,22 +176,6 @@ struct platform_device *__init imx_add_imx_uart_1irq(
                 const struct imx_imx_uart_1irq_data *data,
                 const struct imxuart_platform_data *pdata);
 
-#include <linux/platform_data/usb-imx_udc.h>
-struct imx_imx_udc_data {
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq0;
-        resource_size_t irq1;
-        resource_size_t irq2;
-        resource_size_t irq3;
-        resource_size_t irq4;
-        resource_size_t irq5;
-        resource_size_t irq6;
-};
-struct platform_device *__init imx_add_imx_udc(
-                const struct imx_imx_udc_data *data,
-                const struct imxusb_platform_data *pdata);
-
 #include <linux/platform_data/video-mx3fb.h>
 #include <linux/platform_data/camera-mx3.h>
 struct imx_ipu_core_data {
@@ -208,16 +192,6 @@ struct platform_device *__init imx_add_mx3_sdc_fb(
                 const struct imx_ipu_core_data *data,
                 struct mx3fb_platform_data *pdata);
 
-#include <linux/platform_data/camera-mx1.h>
-struct imx_mx1_camera_data {
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_mx1_camera(
-                const struct imx_mx1_camera_data *data,
-                const struct mx1_camera_pdata *pdata);
-
 #include <linux/platform_data/camera-mx2.h>
 struct imx_mx2_camera_data {
         const char *devid;
diff --git a/arch/arm/mach-imx/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c
index 63eba08f87b1..d86f9250b4ee 100644
--- a/arch/arm/mach-imx/devices/platform-fec.c
+++ b/arch/arm/mach-imx/devices/platform-fec.c
@@ -35,18 +35,6 @@ const struct imx_fec_data imx35_fec_data __initconst =
         imx_fec_data_entry_single(MX35, "imx27-fec");
 #endif
 
-#ifdef CONFIG_SOC_IMX51
-/* i.mx51 has the i.mx27 type fec */
-const struct imx_fec_data imx51_fec_data __initconst =
-        imx_fec_data_entry_single(MX51, "imx27-fec");
-#endif
-
-#ifdef CONFIG_SOC_IMX53
-/* i.mx53 has the i.mx25 type fec */
-const struct imx_fec_data imx53_fec_data __initconst =
-        imx_fec_data_entry_single(MX53, "imx25-fec");
-#endif
-
 struct platform_device *__init imx_add_fec(
                 const struct imx_fec_data *data,
                 const struct fec_platform_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
index 3c06bd96e9cc..23b0061347cb 100644
--- a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
+++ b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
@@ -38,11 +38,6 @@ const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst =
         imx_fsl_usb2_udc_data_entry_single(MX35, "imx-udc-mx27");
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data __initconst =
-        imx_fsl_usb2_udc_data_entry_single(MX51, "imx-udc-mx51");
-#endif
-
 struct platform_device *__init imx_add_fsl_usb2_udc(
                 const struct imx_fsl_usb2_udc_data *data,
                 const struct fsl_usb2_platform_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c
index 57d342e85c2f..644ac2689882 100644
--- a/arch/arm/mach-imx/devices/platform-imx-i2c.c
+++ b/arch/arm/mach-imx/devices/platform-imx-i2c.c
@@ -70,32 +70,6 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
-#define imx51_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX51, "imx21-i2c", _id, _hwid, SZ_4K)
-        imx51_imx_i2c_data_entry(0, 1),
-        imx51_imx_i2c_data_entry(1, 2),
-        {
-                .devid = "imx21-i2c",
-                .id = 2,
-                .iobase = MX51_HSI2C_DMA_BASE_ADDR,
-                .iosize = SZ_16K,
-                .irq = MX51_INT_HS_I2C,
-        },
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst = {
-#define imx53_imx_i2c_data_entry(_id, _hwid)                            \
-        imx_imx_i2c_data_entry(MX53, "imx21-i2c", _id, _hwid, SZ_4K)
-        imx53_imx_i2c_data_entry(0, 1),
-        imx53_imx_i2c_data_entry(1, 2),
-        imx53_imx_i2c_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
 struct platform_device *__init imx_add_imx_i2c(
                 const struct imx_imx_i2c_data *data,
                 const struct imxi2c_platform_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-imx-keypad.c b/arch/arm/mach-imx/devices/platform-imx-keypad.c
index 8f22a4c98a4c..f42200b7aca9 100644
--- a/arch/arm/mach-imx/devices/platform-imx-keypad.c
+++ b/arch/arm/mach-imx/devices/platform-imx-keypad.c
@@ -41,16 +41,6 @@ const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst =
         imx_imx_keypad_data_entry_single(MX35, SZ_16);
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst =
-        imx_imx_keypad_data_entry_single(MX51, SZ_16);
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_imx_keypad_data imx53_imx_keypad_data __initconst =
-        imx_imx_keypad_data_entry_single(MX53, SZ_16);
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
 struct platform_device *__init imx_add_imx_keypad(
                 const struct imx_imx_keypad_data *data,
                 const struct matrix_keymap_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-imx-ssi.c b/arch/arm/mach-imx/devices/platform-imx-ssi.c
index bfcb8f3dfa8d..1c7c721ebff1 100644
--- a/arch/arm/mach-imx/devices/platform-imx-ssi.c
+++ b/arch/arm/mach-imx/devices/platform-imx-ssi.c
@@ -66,26 +66,6 @@ const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = {
-#define imx51_imx_ssi_data_entry(_id, _hwid)                            \
-        imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_16K)
-        imx51_imx_ssi_data_entry(0, 1),
-        imx51_imx_ssi_data_entry(1, 2),
-        imx51_imx_ssi_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_imx_ssi_data imx53_imx_ssi_data[] __initconst = {
-#define imx53_imx_ssi_data_entry(_id, _hwid)                            \
-        imx_imx_ssi_data_entry(MX53, _id, _hwid, SZ_16K)
-        imx53_imx_ssi_data_entry(0, 1),
-        imx53_imx_ssi_data_entry(1, 2),
-        imx53_imx_ssi_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
 struct platform_device *__init imx_add_imx_ssi(
                 const struct imx_imx_ssi_data *data,
                 const struct imx_ssi_platform_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c
index faac4aa6ca6d..8c01836bc1d4 100644
--- a/arch/arm/mach-imx/devices/platform-imx-uart.c
+++ b/arch/arm/mach-imx/devices/platform-imx-uart.c
@@ -94,28 +94,6 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
-#define imx51_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K)
-        imx51_imx_uart_data_entry(0, 1),
-        imx51_imx_uart_data_entry(1, 2),
-        imx51_imx_uart_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = {
-#define imx53_imx_uart_data_entry(_id, _hwid)                           \
-        imx_imx_uart_1irq_data_entry(MX53, _id, _hwid, SZ_4K)
-        imx53_imx_uart_data_entry(0, 1),
-        imx53_imx_uart_data_entry(1, 2),
-        imx53_imx_uart_data_entry(2, 3),
-        imx53_imx_uart_data_entry(3, 4),
-        imx53_imx_uart_data_entry(4, 5),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
 struct platform_device *__init imx_add_imx_uart_3irq(
                 const struct imx_imx_uart_3irq_data *data,
                 const struct imxuart_platform_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-imx2-wdt.c b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
index ec75d6413686..54f63bc25ca4 100644
--- a/arch/arm/mach-imx/devices/platform-imx2-wdt.c
+++ b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
@@ -45,24 +45,6 @@ const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst =
         imx_imx2_wdt_data_entry_single(MX35, 0, , SZ_16K);
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = {
-#define imx51_imx2_wdt_data_entry(_id, _hwid)                           \
-        imx_imx2_wdt_data_entry(MX51, _id, _hwid, SZ_16K)
-        imx51_imx2_wdt_data_entry(0, 1),
-        imx51_imx2_wdt_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst = {
-#define imx53_imx2_wdt_data_entry(_id, _hwid)                           \
-        imx_imx2_wdt_data_entry(MX53, _id, _hwid, SZ_16K)
-        imx53_imx2_wdt_data_entry(0, 1),
-        imx53_imx2_wdt_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
 struct platform_device *__init imx_add_imx2_wdt(
                 const struct imx_imx2_wdt_data *data)
 {
diff --git a/arch/arm/mach-imx/devices/platform-imx_udc.c b/arch/arm/mach-imx/devices/platform-imx_udc.c
deleted file mode 100644
index 5ced7e4e2c71..000000000000
--- a/arch/arm/mach-imx/devices/platform-imx_udc.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx_udc_data_entry_single(soc, _size)                       \
-        {                                                               \
-                .iobase = soc ## _USBD_BASE_ADDR,                       \
-                .iosize = _size,                                        \
-                .irq0 = soc ## _INT_USBD0,                              \
-                .irq1 = soc ## _INT_USBD1,                              \
-                .irq2 = soc ## _INT_USBD2,                              \
-                .irq3 = soc ## _INT_USBD3,                              \
-                .irq4 = soc ## _INT_USBD4,                              \
-                .irq5 = soc ## _INT_USBD5,                              \
-                .irq6 = soc ## _INT_USBD6,                              \
-        }
-
-#define imx_imx_udc_data_entry(soc, _size)                              \
-        [_id] = imx_imx_udc_data_entry_single(soc, _size)
-
-#ifdef CONFIG_SOC_IMX1
-const struct imx_imx_udc_data imx1_imx_udc_data __initconst =
-        imx_imx_udc_data_entry_single(MX1, SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX1 */
-
-struct platform_device *__init imx_add_imx_udc(
-                const struct imx_imx_udc_data *data,
-                const struct imxusb_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq0,
-                        .end = data->irq0,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq1,
-                        .end = data->irq1,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq2,
-                        .end = data->irq2,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq3,
-                        .end = data->irq3,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq4,
-                        .end = data->irq4,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq5,
-                        .end = data->irq5,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->irq6,
-                        .end = data->irq6,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device("imx_udc", 0,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-mx1-camera.c b/arch/arm/mach-imx/devices/platform-mx1-camera.c
deleted file mode 100644
index 2c6788131080..000000000000
--- a/arch/arm/mach-imx/devices/platform-mx1-camera.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mx1_camera_data_entry_single(soc, _size)                    \
-        {                                                               \
-                .iobase = soc ## _CSI ## _BASE_ADDR,                    \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_CSI,                                 \
-        }
-
-#ifdef CONFIG_SOC_IMX1
-const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst =
-        imx_mx1_camera_data_entry_single(MX1, 10);
-#endif /* ifdef CONFIG_SOC_IMX1 */
-
-struct platform_device *__init imx_add_mx1_camera(
-                const struct imx_mx1_camera_data *data,
-                const struct mx1_camera_pdata *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return imx_add_platform_device_dmamask("mx1-camera", 0,
-                        res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-mxc-ehci.c b/arch/arm/mach-imx/devices/platform-mxc-ehci.c
index 5d4bbbfde641..296353662ff0 100644
--- a/arch/arm/mach-imx/devices/platform-mxc-ehci.c
+++ b/arch/arm/mach-imx/devices/platform-mxc-ehci.c
@@ -50,15 +50,6 @@ const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst =
         imx_mxc_ehci_data_entry_single(MX35, 1, HS);
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data __initconst =
-        imx_mxc_ehci_data_entry_single(MX51, 0, OTG);
-const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[] __initconst = {
-        imx_mxc_ehci_data_entry_single(MX51, 1, HS1),
-        imx_mxc_ehci_data_entry_single(MX51, 2, HS2),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
 struct platform_device *__init imx_add_mxc_ehci(
                 const struct imx_mxc_ehci_data *data,
                 const struct mxc_usbh_platform_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-mxc_nand.c b/arch/arm/mach-imx/devices/platform-mxc_nand.c
index 7af1c53e42b5..fa618a34f462 100644
--- a/arch/arm/mach-imx/devices/platform-mxc_nand.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_nand.c
@@ -54,11 +54,6 @@ const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst =
         imx_mxc_nand_data_entry_single(MX35, "imx25-nand", SZ_8K);
 #endif
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst =
-        imx_mxc_nandv3_data_entry_single(MX51, "imx51-nand", SZ_16K);
-#endif
-
 struct platform_device *__init imx_add_mxc_nand(
                 const struct imx_mxc_nand_data *data,
                 const struct mxc_nand_platform_data *pdata)
diff --git a/arch/arm/mach-imx/devices/platform-mxc_rnga.c b/arch/arm/mach-imx/devices/platform-mxc_rnga.c
index c58404badb59..851fbc8af7a9 100644
--- a/arch/arm/mach-imx/devices/platform-mxc_rnga.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_rnga.c
@@ -48,9 +48,6 @@ static int __init imxXX_add_mxc_rnga(void)
 #endif /* if defined(CONFIG_SOC_IMX31) */
                 ret = ERR_PTR(-ENODEV);
 
-        if (IS_ERR(ret))
-                return PTR_ERR(ret);
-
-        return 0;
+        return PTR_ERR_OR_ZERO(ret);
 }
 arch_initcall(imxXX_add_mxc_rnga);
diff --git a/arch/arm/mach-imx/devices/platform-pata_imx.c b/arch/arm/mach-imx/devices/platform-pata_imx.c
index e4ec11c8ce55..1c7f895a69d2 100644
--- a/arch/arm/mach-imx/devices/platform-pata_imx.c
+++ b/arch/arm/mach-imx/devices/platform-pata_imx.c
@@ -28,16 +28,6 @@ const struct imx_pata_imx_data imx35_pata_imx_data __initconst =
         imx_pata_imx_data_entry_single(MX35, SZ_16K);
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_pata_imx_data imx51_pata_imx_data __initconst =
-        imx_pata_imx_data_entry_single(MX51, SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_pata_imx_data imx53_pata_imx_data __initconst =
-        imx_pata_imx_data_entry_single(MX53, SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
 struct platform_device *__init imx_add_pata_imx(
                 const struct imx_pata_imx_data *data)
 {
diff --git a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
index e66a4e316311..fb8d4a2ad48c 100644
--- a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
+++ b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
@@ -43,30 +43,6 @@ imx35_sdhci_esdhc_imx_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-const struct imx_sdhci_esdhc_imx_data
-imx51_sdhci_esdhc_imx_data[] __initconst = {
-#define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid)                    \
-        imx_sdhci_esdhc_imx_data_entry(MX51, "sdhci-esdhc-imx51", _id, _hwid)
-        imx51_sdhci_esdhc_imx_data_entry(0, 1),
-        imx51_sdhci_esdhc_imx_data_entry(1, 2),
-        imx51_sdhci_esdhc_imx_data_entry(2, 3),
-        imx51_sdhci_esdhc_imx_data_entry(3, 4),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_sdhci_esdhc_imx_data
-imx53_sdhci_esdhc_imx_data[] __initconst = {
-#define imx53_sdhci_esdhc_imx_data_entry(_id, _hwid)                    \
-        imx_sdhci_esdhc_imx_data_entry(MX53, "sdhci-esdhc-imx53", _id, _hwid)
-        imx53_sdhci_esdhc_imx_data_entry(0, 1),
-        imx53_sdhci_esdhc_imx_data_entry(1, 2),
-        imx53_sdhci_esdhc_imx_data_entry(2, 3),
-        imx53_sdhci_esdhc_imx_data_entry(3, 4),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
 static const struct esdhc_platform_data default_esdhc_pdata __initconst = {
         .wp_type = ESDHC_WP_NONE,
         .cd_type = ESDHC_CD_NONE,
diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c
index 8880bcb11e05..aca825d74c48 100644
--- a/arch/arm/mach-imx/devices/platform-spi_imx.c
+++ b/arch/arm/mach-imx/devices/platform-spi_imx.c
@@ -79,33 +79,6 @@ const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_SOC_IMX51
-/* i.mx51 has the i.mx35 type cspi */
-const struct imx_spi_imx_data imx51_cspi_data __initconst =
-        imx_spi_imx_data_entry_single(MX51, CSPI, "imx35-cspi", 2, , SZ_4K);
-
-const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
-#define imx51_ecspi_data_entry(_id, _hwid)                              \
-        imx_spi_imx_data_entry(MX51, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K)
-        imx51_ecspi_data_entry(0, 1),
-        imx51_ecspi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-#ifdef CONFIG_SOC_IMX53
-/* i.mx53 has the i.mx35 type cspi */
-const struct imx_spi_imx_data imx53_cspi_data __initconst =
-        imx_spi_imx_data_entry_single(MX53, CSPI, "imx35-cspi", 2, , SZ_4K);
-
-/* i.mx53 has the i.mx51 type ecspi */
-const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = {
-#define imx53_ecspi_data_entry(_id, _hwid)                              \
-        imx_spi_imx_data_entry(MX53, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K)
-        imx53_ecspi_data_entry(0, 1),
-        imx53_ecspi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX53 */
-
 struct platform_device *__init imx_add_spi_imx(
                 const struct imx_spi_imx_data *data,
                 const struct spi_imx_master *pdata)
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
index 134c190e3003..42a5a3d14c5f 100644
--- a/arch/arm/mach-imx/ehci-imx25.c
+++ b/arch/arm/mach-imx/ehci-imx25.c
@@ -17,6 +17,7 @@
 #include <linux/io.h>
 #include <linux/platform_data/usb-ehci-mxc.h>
 
+#include "ehci.h"
 #include "hardware.h"
 
 #define USBCTRL_OTGBASE_OFFSET  0x600
diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c
index 448d9115539d..c56974346c16 100644
--- a/arch/arm/mach-imx/ehci-imx27.c
+++ b/arch/arm/mach-imx/ehci-imx27.c
@@ -17,6 +17,7 @@
 #include <linux/io.h>
 #include <linux/platform_data/usb-ehci-mxc.h>
 
+#include "ehci.h"
 #include "hardware.h"
 
 #define USBCTRL_OTGBASE_OFFSET  0x600
diff --git a/arch/arm/mach-imx/ehci-imx31.c b/arch/arm/mach-imx/ehci-imx31.c
index 05de4e1e39d7..bede21d9b981 100644
--- a/arch/arm/mach-imx/ehci-imx31.c
+++ b/arch/arm/mach-imx/ehci-imx31.c
@@ -17,6 +17,7 @@
 #include <linux/io.h>
 #include <linux/platform_data/usb-ehci-mxc.h>
 
+#include "ehci.h"
 #include "hardware.h"
 
 #define USBCTRL_OTGBASE_OFFSET  0x600
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c
index 554e7cccff53..f424a543755c 100644
--- a/arch/arm/mach-imx/ehci-imx35.c
+++ b/arch/arm/mach-imx/ehci-imx35.c
@@ -17,6 +17,7 @@
 #include <linux/io.h>
 #include <linux/platform_data/usb-ehci-mxc.h>
 
+#include "ehci.h"
 #include "hardware.h"
 
 #define USBCTRL_OTGBASE_OFFSET  0x600
diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c
deleted file mode 100644
index e49710b10c68..000000000000
--- a/arch/arm/mach-imx/ehci-imx5.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * for more details.
- */
-
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/platform_data/usb-ehci-mxc.h>
-
-#include "hardware.h"
-
-#define MXC_OTG_OFFSET                  0
-#define MXC_H1_OFFSET                   0x200
-#define MXC_H2_OFFSET                   0x400
-
-/* USB_CTRL */
-#define MXC_OTG_UCTRL_OWIE_BIT          (1 << 27)       /* OTG wakeup intr enable */
-#define MXC_OTG_UCTRL_OPM_BIT           (1 << 24)       /* OTG power mask */
-#define MXC_H1_UCTRL_H1UIE_BIT          (1 << 12)       /* Host1 ULPI interrupt enable */
-#define MXC_H1_UCTRL_H1WIE_BIT          (1 << 11)       /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT           (1 <<  8)       /* HOST1 power mask */
-
-/* USB_PHY_CTRL_FUNC */
-#define MXC_OTG_PHYCTRL_OC_POL_BIT      (1 << 9)        /* OTG Polarity of Overcurrent */
-#define MXC_OTG_PHYCTRL_OC_DIS_BIT      (1 << 8)        /* OTG Disable Overcurrent Event */
-#define MXC_H1_OC_POL_BIT               (1 << 6)        /* UH1 Polarity of Overcurrent */
-#define MXC_H1_OC_DIS_BIT               (1 << 5)        /* UH1 Disable Overcurrent Event */
-#define MXC_OTG_PHYCTRL_PWR_POL_BIT     (1 << 3)        /* OTG Power Pin Polarity */
-
-/* USBH2CTRL */
-#define MXC_H2_UCTRL_H2UIE_BIT          (1 << 8)
-#define MXC_H2_UCTRL_H2WIE_BIT          (1 << 7)
-#define MXC_H2_UCTRL_H2PM_BIT           (1 << 4)
-
-#define MXC_USBCMD_OFFSET               0x140
-
-/* USBCMD */
-#define MXC_UCMD_ITC_NO_THRESHOLD_MASK  (~(0xff << 16)) /* Interrupt Threshold Control */
-
-int mx51_initialize_usb_hw(int port, unsigned int flags)
-{
-        unsigned int v;
-        void __iomem *usb_base;
-        void __iomem *usbotg_base;
-        void __iomem *usbother_base;
-        int ret = 0;
-
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base) {
-                printk(KERN_ERR "%s(): ioremap failed\n", __func__);
-                return -ENOMEM;
-        }
-
-        switch (port) {
-        case 0: /* OTG port */
-                usbotg_base = usb_base + MXC_OTG_OFFSET;
-                break;
-        case 1: /* Host 1 port */
-                usbotg_base = usb_base + MXC_H1_OFFSET;
-                break;
-        case 2: /* Host 2 port */
-                usbotg_base = usb_base + MXC_H2_OFFSET;
-                break;
-        default:
-                printk(KERN_ERR"%s no such port %d\n", __func__, port);
-                ret = -ENOENT;
-                goto error;
-        }
-        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-
-        switch (port) {
-        case 0: /*OTG port */
-                if (flags & MXC_EHCI_INTERNAL_PHY) {
-                        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-
-                        if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
-                                v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
-                        else
-                                v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
-                        if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
-                                /* OC/USBPWR is used */
-                                v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
-                        } else {
-                                /* OC/USBPWR is not used */
-                                v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
-                        }
-                        if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-                                v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
-                        else
-                                v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
-                        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-
-                        v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
-                        if (flags & MXC_EHCI_WAKEUP_ENABLED)
-                                v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
-                        else
-                                v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
-                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                                v &= ~MXC_OTG_UCTRL_OPM_BIT;
-                        else
-                                v |= MXC_OTG_UCTRL_OPM_BIT;
-                        __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
-                }
-                break;
-        case 1: /* Host 1 */
-                /*Host ULPI */
-                v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
-                if (flags & MXC_EHCI_WAKEUP_ENABLED) {
-                        /* HOST1 wakeup/ULPI intr enable */
-                        v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
-                } else {
-                        /* HOST1 wakeup/ULPI intr disable */
-                        v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
-                }
-
-                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                        v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/
-                else
-                        v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
-                __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
-
-                v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-                if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
-                        v |= MXC_H1_OC_POL_BIT;
-                else
-                        v &= ~MXC_H1_OC_POL_BIT;
-                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                        v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
-                else
-                        v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
-                __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-
-                v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
-                if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
-                        /* Interrupt Threshold Control:Immediate (no threshold) */
-                        v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
-                __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
-                break;
-        case 2: /* Host 2 ULPI */
-                v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
-                if (flags & MXC_EHCI_WAKEUP_ENABLED) {
-                        /* HOST1 wakeup/ULPI intr enable */
-                        v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
-                } else {
-                        /* HOST1 wakeup/ULPI intr disable */
-                        v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
-                }
-
-                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                        v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/
-                else
-                        v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
-                __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
-                break;
-        }
-
-error:
-        iounmap(usb_base);
-        return ret;
-}
-
diff --git a/arch/arm/mach-imx/ehci.h b/arch/arm/mach-imx/ehci.h
new file mode 100644
index 000000000000..0e060023db8b
--- /dev/null
+++ b/arch/arm/mach-imx/ehci.h
@@ -0,0 +1,43 @@
+#ifndef __MACH_IMX_EHCI_H
+#define __MACH_IMX_EHCI_H
+
+/* values for portsc field */
+#define MXC_EHCI_PHY_LOW_POWER_SUSPEND  (1 << 23)
+#define MXC_EHCI_FORCE_FS               (1 << 24)
+#define MXC_EHCI_UTMI_8BIT              (0 << 28)
+#define MXC_EHCI_UTMI_16BIT             (1 << 28)
+#define MXC_EHCI_SERIAL                 (1 << 29)
+#define MXC_EHCI_MODE_UTMI              (0 << 30)
+#define MXC_EHCI_MODE_PHILIPS           (1 << 30)
+#define MXC_EHCI_MODE_ULPI              (2 << 30)
+#define MXC_EHCI_MODE_SERIAL            (3 << 30)
+
+/* values for flags field */
+#define MXC_EHCI_INTERFACE_DIFF_UNI     (0 << 0)
+#define MXC_EHCI_INTERFACE_DIFF_BI      (1 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI   (2 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_BI    (3 << 0)
+#define MXC_EHCI_INTERFACE_MASK         (0xf)
+
+#define MXC_EHCI_POWER_PINS_ENABLED     (1 << 5)
+#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH    (1 << 6)
+#define MXC_EHCI_OC_PIN_ACTIVE_LOW      (1 << 7)
+#define MXC_EHCI_TTL_ENABLED            (1 << 8)
+
+#define MXC_EHCI_INTERNAL_PHY           (1 << 9)
+#define MXC_EHCI_IPPUE_DOWN             (1 << 10)
+#define MXC_EHCI_IPPUE_UP               (1 << 11)
+#define MXC_EHCI_WAKEUP_ENABLED         (1 << 12)
+#define MXC_EHCI_ITC_NO_THRESHOLD       (1 << 13)
+
+#define MXC_USBCTRL_OFFSET              0
+#define MXC_USB_PHY_CTR_FUNC_OFFSET     0x8
+#define MXC_USB_PHY_CTR_FUNC2_OFFSET    0xc
+#define MXC_USBH2CTRL_OFFSET            0x14
+
+int mx25_initialize_usb_hw(int port, unsigned int flags);
+int mx31_initialize_usb_hw(int port, unsigned int flags);
+int mx35_initialize_usb_hw(int port, unsigned int flags);
+int mx27_initialize_usb_hw(int port, unsigned int flags);
+
+#endif /* __MACH_IMX_EHCI_H */
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 586e0171a652..82ea74e68482 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -27,13 +27,14 @@ static void __iomem *gpc_base;
 static u32 gpc_wake_irqs[IMR_NUM];
 static u32 gpc_saved_imrs[IMR_NUM];
 
-void imx_gpc_pre_suspend(void)
+void imx_gpc_pre_suspend(bool arm_power_off)
 {
         void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
         int i;
 
         /* Tell GPC to power off ARM core when suspend */
-        writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
+        if (arm_power_off)
+                writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
 
         for (i = 0; i < IMR_NUM; i++) {
                 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index abf43bb47eca..66b2b564c463 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -105,8 +105,6 @@
 
 #include "mxc.h"
 
-#include "mx51.h"
-#include "mx53.h"
 #include "mx3x.h"
 #include "mx31.h"
 #include "mx35.h"
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index 42a65e067443..cf8032bae277 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -29,16 +29,10 @@ static const char * const imx25_dt_board_compat[] __initconst = {
         NULL
 };
 
-static void __init imx25_timer_init(void)
-{
-        mx25_clocks_init_dt();
-}
-
 DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
         .map_io         = mx25_map_io,
         .init_early     = imx25_init_early,
         .init_irq       = mx25_init_irq,
-        .init_time      = imx25_timer_init,
         .init_machine   = imx25_dt_init,
         .dt_compat      = imx25_dt_board_compat,
         .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 17bd4058133d..080e66c6a1d0 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -34,16 +34,10 @@ static const char * const imx27_dt_board_compat[] __initconst = {
         NULL
 };
 
-static void __init imx27_timer_init(void)
-{
-        mx27_clocks_init_dt();
-}
-
 DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
         .map_io         = mx27_map_io,
         .init_early     = imx27_init_early,
         .init_irq       = mx27_init_irq,
-        .init_time      = imx27_timer_init,
         .init_machine   = imx27_dt_init,
         .dt_compat      = imx27_dt_board_compat,
         .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index 581f4d6c9b8a..418dbc82adc4 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -25,7 +25,7 @@ static void __init imx31_dt_init(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const char *imx31_dt_board_compat[] __initconst = {
+static const char * const imx31_dt_board_compat[] __initconst = {
         "fsl,imx31",
         NULL
 };
diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c
index a62854c59240..584fbe105579 100644
--- a/arch/arm/mach-imx/imx35-dt.c
+++ b/arch/arm/mach-imx/imx35-dt.c
@@ -34,7 +34,7 @@ static void __init imx35_irq_init(void)
         mx35_init_irq();
 }
 
-static const char *imx35_dt_board_compat[] __initconst = {
+static const char * const imx35_dt_board_compat[] __initconst = {
         "fsl,imx35",
         NULL
 };
diff --git a/arch/arm/mach-imx/iomux-mx51.h b/arch/arm/mach-imx/iomux-mx51.h
deleted file mode 100644
index 75bbcc4aa2d2..000000000000
--- a/arch/arm/mach-imx/iomux-mx51.h
+++ /dev/null
@@ -1,827 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __MACH_IOMUX_MX51_H__
-#define __MACH_IOMUX_MX51_H__
-
-#include "iomux-v3.h"
-#define __NA_   0x000
-
-
-/* Pad control groupings */
-#define MX51_UART_PAD_CTRL      (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
-                                PAD_CTL_HYS | PAD_CTL_SRE_FAST)
-#define MX51_I2C_PAD_CTRL       (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
-                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
-                                PAD_CTL_HYS)
-#define MX51_ESDHC_PAD_CTRL     (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
-                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
-                                PAD_CTL_HYS)
-#define MX51_USBH1_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
-                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
-                                PAD_CTL_HYS | PAD_CTL_PUE)
-#define MX51_ECSPI_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_HYS | \
-                                PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
-#define MX51_SDHCI_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
-                                PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
-                                PAD_CTL_SRE_FAST | PAD_CTL_DVS)
-#define MX51_GPIO_PAD_CTRL      (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
-
-#define MX51_PAD_CTRL_2         (PAD_CTL_PKE | PAD_CTL_HYS)
-#define MX51_PAD_CTRL_3         (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_CTRL_4         (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
-#define MX51_PAD_CTRL_5         (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
-
-/*
- * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
- * See also iomux-v3.h
- */
-
-/* Raw pin modes without pad control */
-/*                                                        PAD    MUX ALT INPSE PATH PADCTRL */
-
-/* The same pins as above but with the default pad control values applied */
-#define MX51_PAD_EIM_D16__AUD4_RXFS             IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__AUD5_TXD              IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__EIM_D16               IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__GPIO2_0               IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__I2C1_SDA              IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D16__UART2_CTS             IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D16__USBH2_DATA0           IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__AUD5_RXD              IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__EIM_D17               IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__GPIO2_1               IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D17__UART2_RXD             IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D17__UART3_CTS             IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D17__USBH2_DATA1           IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__AUD5_TXC              IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__EIM_D18               IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__GPIO2_2               IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__UART2_TXD             IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D18__UART3_RTS             IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D18__USBH2_DATA2           IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__AUD4_RXC              IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__AUD5_TXFS             IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__EIM_D19               IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__GPIO2_3               IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__I2C1_SCL              IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D19__UART2_RTS             IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D19__USBH2_DATA3           IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__AUD4_TXD              IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__EIM_D20               IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__GPIO2_4               IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB        IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D20__USBH2_DATA4           IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__AUD4_RXD              IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__EIM_D21               IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__GPIO2_5               IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB        IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__USBH2_DATA5           IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__AUD4_TXC              IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__EIM_D22               IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__GPIO2_6               IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__USBH2_DATA6           IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__AUD4_TXFS             IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__EIM_D23               IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__GPIO2_7               IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__SPDIF_OUT1            IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__USBH2_DATA7           IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__AUD6_RXFS             IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__EIM_D24               IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__GPIO2_8               IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__I2C2_SDA              IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D24__UART3_CTS             IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D24__USBOTG_DATA0          IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__EIM_D25               IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__KEY_COL6              IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART2_CTS             IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D25__USBOTG_DATA1          IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D25__GPT_CMPOUT1           IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__EIM_D26               IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__KEY_COL7              IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART2_RTS             IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D26__USBOTG_DATA2          IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D26__GPT_CMPOUT2           IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__AUD6_RXC              IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__EIM_D27               IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__GPIO2_9               IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D27__I2C2_SCL              IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL)
-#define MX51_PAD_EIM_D27__USBOTG_DATA3          IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__AUD6_TXD              IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__EIM_D28               IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__KEY_ROW4              IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D28__USBOTG_DATA4          IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__AUD6_RXD              IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__EIM_D29               IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__KEY_ROW5              IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__USBOTG_DATA5          IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__AUD6_TXC              IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__EIM_D30               IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__KEY_ROW6              IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__USBOTG_DATA6          IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__AUD6_TXFS             IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__EIM_D31               IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__KEY_ROW7              IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__USBOTG_DATA7          IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__EIM_A16               IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__GPIO2_10              IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0         IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__EIM_A17               IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__GPIO2_11              IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1         IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__BOOT_LPB0             IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__EIM_A18               IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__GPIO2_12              IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__BOOT_LPB1             IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__EIM_A19               IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__GPIO2_13              IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__BOOT_UART_SRC0        IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__EIM_A20               IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__GPIO2_14              IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A21__BOOT_UART_SRC1        IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A21__EIM_A21               IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A21__GPIO2_15              IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A22__EIM_A22               IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A22__GPIO2_16              IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__BOOT_HPN_EN           IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__EIM_A23               IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__GPIO2_17              IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__EIM_A24               IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__GPIO2_18              IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__USBH2_CLK             IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__DISP1_PIN4            IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__EIM_A25               IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__GPIO2_19              IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__USBH2_DIR             IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__CSI1_DATA_EN          IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__DISP2_EXT_CLK         IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__EIM_A26               IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__GPIO2_20              IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__USBH2_STP             IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__CSI2_DATA_EN          IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__DISP1_PIN1            IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__EIM_A27               IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__GPIO2_21              IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__USBH2_NXT             IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB0__EIM_EB0               IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB1__EIM_EB1               IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__AUD5_RXFS             IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__CSI1_D2               IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__EIM_EB2               IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__FEC_MDIO              (IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, 0) | \
-                MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
-                PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS))
-#define MX51_PAD_EIM_EB2__GPIO2_22              IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__GPT_CMPOUT1           IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__AUD5_RXC              IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__CSI1_D3               IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__EIM_EB3               IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__FEC_RDATA1            IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__GPIO2_23              IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__GPT_CMPOUT2           IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_OE__EIM_OE                 IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_OE__GPIO2_24               IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS0__EIM_CS0               IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS0__GPIO2_25              IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS1__EIM_CS1               IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS1__GPIO2_26              IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__AUD5_TXD              IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__CSI1_D4               IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__EIM_CS2               IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__FEC_RDATA2            IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__GPIO2_27              IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__USBOTG_STP            IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__AUD5_RXD              IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__CSI1_D5               IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__EIM_CS3               IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__FEC_RDATA3            IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__GPIO2_28              IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__USBOTG_NXT            IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__AUD5_TXC              IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__CSI1_D6               IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__EIM_CS4               IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__FEC_RX_ER             IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_EIM_CS4__GPIO2_29              IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__USBOTG_CLK            IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__AUD5_TXFS             IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__CSI1_D7               IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK         IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__EIM_CS5               IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__FEC_CRS               IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_EIM_CS5__GPIO2_30              IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__USBOTG_DIR            IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DTACK__EIM_DTACK           IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DTACK__GPIO2_31            IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_LBA__EIM_LBA               IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_LBA__GPIO3_1               IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_CRE__EIM_CRE               IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CRE__GPIO3_2               IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__DRAM_CS1             IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__CCM_CLKO             IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__GPIO3_3            IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__NANDF_WE_B         IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__PATA_DIOW          IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__SD3_DATA0          IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__GPIO3_4            IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__NANDF_RE_B         IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__PATA_DIOR          IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__SD3_DATA1          IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__GPIO3_5             IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__NANDF_ALE           IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN      IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__GPIO3_6             IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__NANDF_CLE           IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__PATA_RESET_B        IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__GPIO3_7            IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__NANDF_WP_B         IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__PATA_DMACK         IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__SD3_DATA2          IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__ECSPI2_SS1          IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__GPIO3_8             IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__NANDF_RB0           IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__PATA_DMARQ          IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__SD3_DATA3           IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__CSPI_MOSI           IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__ECSPI2_RDY          IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__GPIO3_9             IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__NANDF_RB1           IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__PATA_IORDY          IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__GPT_CMPOUT2         IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__SD4_CMD             IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__DISP2_WAIT          IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__FEC_COL             IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_NANDF_RB2__GPIO3_10            IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__NANDF_RB2           IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__GPT_CMPOUT3         IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__USBH3_H3_DP         IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__USBH3_NXT           IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__DISP1_WAIT          IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__ECSPI2_MISO         IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__FEC_RX_CLK          IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2)
-#define MX51_PAD_NANDF_RB3__GPIO3_11            IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__NANDF_RB3           IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__USBH3_CLK           IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__USBH3_H3_DM         IOMUX_PAD(0x504, 0x128, 0x17, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_NAND__GPIO_NAND           IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_NAND__PATA_INTRQ          IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS0__GPIO3_16            IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS0__NANDF_CS0           IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS1__GPIO3_17            IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS1__NANDF_CS1           IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__CSPI_SCLK           IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__FEC_TX_ER           IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS2__GPIO3_18            IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__NANDF_CS2           IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__PATA_CS_0           IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__SD4_CLK             IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_NANDF_CS2__USBH3_H1_DP         IOMUX_PAD(0x520, 0x138, 0x17, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__FEC_MDC             IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS3__GPIO3_19            IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__NANDF_CS3           IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__PATA_CS_1           IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__SD4_DAT0            IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__USBH3_H1_DM         IOMUX_PAD(0x524, 0x13c, 0x17, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__FEC_TDATA1          IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS4__GPIO3_20            IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__NANDF_CS4           IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__PATA_DA_0           IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__SD4_DAT1            IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__USBH3_STP           IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__FEC_TDATA2          IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS5__GPIO3_21            IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__NANDF_CS5           IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__PATA_DA_1           IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__SD4_DAT2            IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__USBH3_DIR           IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__CSPI_SS3            IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__FEC_TDATA3          IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS6__GPIO3_22            IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__NANDF_CS6           IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__PATA_DA_2           IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__SD4_DAT3            IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__FEC_TX_EN           IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS7__GPIO3_23            IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__NANDF_CS7           IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__SD3_CLK             IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0      IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4)
-#define MX51_PAD_NANDF_RDY_INT__GPIO3_24        IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT   IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__SD3_CMD         IOMUX_PAD(0x538, 0x150, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__ECSPI2_MOSI         IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__GPIO3_25            IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__NANDF_D15           IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__PATA_DATA15         IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__SD3_DAT7            IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__ECSPI2_SS3          IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__GPIO3_26            IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__NANDF_D14           IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__PATA_DATA14         IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__SD3_DAT6            IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__ECSPI2_SS2          IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__GPIO3_27            IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__NANDF_D13           IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__PATA_DATA13         IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__SD3_DAT5            IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__ECSPI2_SS1          IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__GPIO3_28            IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__NANDF_D12           IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__PATA_DATA12         IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__SD3_DAT4            IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__FEC_RX_DV           IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__GPIO3_29            IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__NANDF_D11           IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__PATA_DATA11         IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__SD3_DATA3           IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__GPIO3_30            IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__NANDF_D10           IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__PATA_DATA10         IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__SD3_DATA2           IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__FEC_RDATA0           IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4)
-#define MX51_PAD_NANDF_D9__GPIO3_31             IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__NANDF_D9             IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__PATA_DATA9           IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__SD3_DATA1            IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__FEC_TDATA0           IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_D8__GPIO4_0              IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__NANDF_D8             IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__PATA_DATA8           IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__SD3_DATA0            IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__GPIO4_1              IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__NANDF_D7             IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__PATA_DATA7           IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__USBH3_DATA0          IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__GPIO4_2              IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__NANDF_D6             IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__PATA_DATA6           IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__SD4_LCTL             IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__USBH3_DATA1          IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__GPIO4_3              IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__NANDF_D5             IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__PATA_DATA5           IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__SD4_WP               IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__USBH3_DATA2          IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__GPIO4_4              IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__NANDF_D4             IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__PATA_DATA4           IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__SD4_CD               IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__USBH3_DATA3          IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__GPIO4_5              IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__NANDF_D3             IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__PATA_DATA3           IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__SD4_DAT4             IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__USBH3_DATA4          IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__GPIO4_6              IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__NANDF_D2             IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__PATA_DATA2           IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__SD4_DAT5             IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__USBH3_DATA5          IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__GPIO4_7              IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__NANDF_D1             IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__PATA_DATA1           IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__SD4_DAT6             IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__USBH3_DATA6          IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__GPIO4_8              IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__NANDF_D0             IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__PATA_DATA0           IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__SD4_DAT7             IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__USBH3_DATA7          IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D8__CSI1_D8               IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D8__GPIO3_12              IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_D9__CSI1_D9               IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D9__GPIO3_13              IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_D10__CSI1_D10             IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D11__CSI1_D11             IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D12__CSI1_D12             IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D13__CSI1_D13             IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D14__CSI1_D14             IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D15__CSI1_D15             IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D16__CSI1_D16             IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D17__CSI1_D17             IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D18__CSI1_D18             IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D19__CSI1_D19             IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__GPIO3_14           IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__GPIO3_15           IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D12__CSI2_D12             IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D12__GPIO4_9              IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_D13__CSI2_D13             IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D13__GPIO4_10             IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_D14__CSI2_D14             IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D15__CSI2_D15             IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D16__CSI2_D16             IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D17__CSI2_D17             IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D18__CSI2_D18             IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D18__GPIO4_11             IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_D19__CSI2_D19             IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D19__GPIO4_12             IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC         IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_VSYNC__GPIO4_13           IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC         IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_HSYNC__GPIO4_14           IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK       IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PIXCLK__GPIO4_15          IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_I2C1_CLK__GPIO4_16             IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_I2C1_CLK__I2C1_CLK             IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_I2C1_DAT__GPIO4_17             IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_I2C1_DAT__I2C1_DAT             IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD          IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_TXD__GPIO4_18          IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD          IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__GPIO4_19          IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__UART3_RXD         IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_CK__AUD3_TXC           IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_CK__GPIO4_20           IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS          IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__GPIO4_21           IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__UART3_TXD          IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__GPIO4_22           IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__I2C1_SDA           IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__AUD4_RXD           IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO        IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__GPIO4_23           IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__AUD4_TXC            IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0          IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__GPIO4_24            IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__AUD4_TXD            IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1          IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__GPIO4_25            IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__AUD4_TXFS           IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY          IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__GPIO4_26            IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__GPIO4_27           IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__I2C1_SCL           IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_UART1_RXD__GPIO4_28            IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_RXD__UART1_RXD           IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART1_TXD__GPIO4_29            IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_TXD__PWM2_PWMO           IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART1_TXD__UART1_TXD           IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART1_RTS__GPIO4_30            IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_RTS__UART1_RTS           IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__GPIO4_31            IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__UART1_CTS           IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__FIRI_TXD            IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__GPIO1_20            IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__UART2_RXD           IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__FIRI_RXD            IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__GPIO1_21            IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__UART2_TXD           IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__CSI1_D0             IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__GPIO1_22            IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__UART1_DTR           IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__UART3_RXD           IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__CSI1_D1             IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__GPIO1_23            IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__UART1_DSR           IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__UART3_TXD           IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__GPIO1_24           IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__OWIRE_LINE         IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__SPDIF_OUT          IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW0__KEY_ROW0             IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW1__KEY_ROW1             IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW2__KEY_ROW2             IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW3__KEY_ROW3             IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__KEY_COL0             IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__PLL1_BYP             IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__KEY_COL1             IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__PLL2_BYP             IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__KEY_COL2             IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__PLL3_BYP             IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL3__KEY_COL3             IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__I2C2_SCL             IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__KEY_COL4             IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__SPDIF_OUT1           IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__UART1_RI             IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__UART3_RTS            IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__I2C2_SDA             IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__KEY_COL5             IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__UART1_DCD            IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__UART3_CTS            IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__CSPI_SCLK           IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__GPIO1_25            IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__I2C2_SCL            IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__USBH1_CLK           IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__CSPI_MOSI           IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__GPIO1_26            IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__I2C2_SDA            IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__USBH1_DIR           IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__CSPI_RDY            IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__GPIO1_27            IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__UART3_RXD           IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__USBH1_STP           IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__CSPI_MISO           IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__GPIO1_28            IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__UART3_TXD           IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__USBH1_NXT           IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__GPIO1_11          IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__UART2_CTS         IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__GPIO1_12          IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__UART2_RXD         IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__GPIO1_13          IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__UART2_TXD         IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__GPIO1_14          IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__UART2_RTS         IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__CSPI_SS0          IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__GPIO1_15          IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__CSPI_SS1          IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__GPIO1_16          IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__CSPI_SS3          IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__GPIO1_17          IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3        IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3        IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__GPIO1_18          IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__DI1_PIN11           IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__ECSPI1_SS2          IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__GPIO3_0             IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN12__DI1_PIN12           IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN12__GPIO3_1             IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN13__DI1_PIN13           IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN13__GPIO3_2             IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_D0_CS__DI1_D0_CS           IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D0_CS__GPIO3_3             IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__DI1_D1_CS           IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__DISP1_PIN14         IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__DISP1_PIN5          IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__GPIO3_4             IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1     IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5        IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6     IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6        IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17    IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7     IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7        IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK   IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16     IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8      IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__GPIO3_8         IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC       IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG    IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__BOOT_SRC0          IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__BOOT_SRC1          IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE   IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2    IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL      IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0     IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1     IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH    IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0   IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1   IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0  IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP2_PIN11       IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP2_PIN5        IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1  IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP2_PIN12       IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP2_PIN6        IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0    IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP2_PIN13       IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP2_PIN7        IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1    IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP2_PIN14       IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP2_PIN8        IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0    IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS       IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP2_DAT16       IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1    IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS       IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP2_DAT17       IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS      IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN3__DI1_PIN3             IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK     IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN2__DI1_PIN2             IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN15__DI1_PIN15           IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DISP1_SER_CLK          IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DISP2_WAIT             IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__CSI1_DATA_EN           IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__DISP1_SER_DIO          IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__FEC_TX_ER              IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN         IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__DI2_PIN4             IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__FEC_CRS              IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__DI2_PIN2             IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__FEC_MDC              IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DI2_PIN3__DI2_PIN3             IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__FEC_MDIO             IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1       IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DI2_PIN15              IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DISP1_SER_DIN          IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DISP2_PIN1             IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__FEC_RDATA2             IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__FEC_RDATA3         IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__KEY_COL6           IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__UART3_RXD          IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__USBH3_CLK          IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__FEC_RX_ER          IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__KEY_COL7           IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__UART3_TXD          IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__USBH3_DIR          IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__DISP2_DAT6         IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__FEC_TDATA1         IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT6__GPIO1_19           IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__KEY_ROW4           IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__USBH3_STP          IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__DISP2_DAT7         IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__FEC_TDATA2         IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT7__GPIO1_29           IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__KEY_ROW5           IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__USBH3_NXT          IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__DISP2_DAT8         IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__FEC_TDATA3         IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT8__GPIO1_30           IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__KEY_ROW6           IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__USBH3_DATA0        IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__AUD6_RXC           IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__DISP2_DAT9         IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__FEC_TX_EN          IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT9__GPIO1_31           IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__USBH3_DATA1        IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS      IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__FEC_COL           IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__KEY_ROW7          IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__USBH3_DATA2       IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__AUD6_TXD          IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK        IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__GPIO1_10          IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__USBH3_DATA3       IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__AUD6_RXD          IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__FEC_RX_DV         IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__USBH3_DATA4       IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__AUD6_TXC          IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK        IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4)
-#define MX51_PAD_DISP2_DAT13__USBH3_DATA5       IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__AUD6_TXFS         IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__FEC_RDATA0        IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4)
-#define MX51_PAD_DISP2_DAT14__USBH3_DATA6       IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__AUD6_RXFS         IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS      IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__FEC_TDATA0        IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT15__USBH3_DATA7       IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__AUD5_RXFS             IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__CSPI_MOSI             IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__AUD5_RXC              IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__CSPI_SCLK             IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_SD1_DATA0__AUD5_TXD            IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__CSPI_MISO           IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_EIM_DA0__EIM_DA0               IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA1__EIM_DA1               IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA2__EIM_DA2               IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA3__EIM_DA3               IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__AUD5_RXD            IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_EIM_DA4__EIM_DA4               IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA5__EIM_DA5               IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA6__EIM_DA6               IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA7__EIM_DA7               IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__AUD5_TXC            IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_EIM_DA10__EIM_DA10             IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA11__EIM_DA11             IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA8__EIM_DA8               IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA9__EIM_DA9               IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__AUD5_TXFS           IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__CSPI_SS1            IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__CSPI_SS2              IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__GPIO1_0               IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__SD1_CD                IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__CSPI_MISO             IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__GPIO1_1               IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__SD1_WP                IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_EIM_DA12__EIM_DA12             IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA13__EIM_DA13             IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA14__EIM_DA14             IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA15__EIM_DA15             IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__CSPI_MOSI             IOMUX_PAD(0x7bc, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__I2C1_SCL              IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__CSPI_SCLK             IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__I2C1_SDA              IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK               IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_SD2_DATA0__CSPI_MISO           IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD1_DAT4            IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD1_DAT5            IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__USBH3_H2_DP         IOMUX_PAD(0x7c8, 0x3c0, 0x12, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD1_DAT6            IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__USBH3_H2_DM         IOMUX_PAD(0x7cc, 0x3c4, 0x12, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__CSPI_SS2            IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD1_DAT7            IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__CCM_OUT_2             IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__GPIO1_2               IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__I2C2_SCL              IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__PLL1_BYP              IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__PWM1_PWMO             IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__GPIO1_3               IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__I2C2_SDA              IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__CCM_CLKO2             IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__GPT_CLKIN             IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__PLL2_BYP              IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__PWM2_PWMO             IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ     IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B   IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK         IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__EIM_RDY               IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__GPIO1_4               IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B          IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__GPT_CAPIN1            IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__CSI2_MCLK             IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__DISP2_PIN16           IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__GPIO1_5               IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B          IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__CCM_CLKO              IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__DISP2_PIN17           IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__GPIO1_6               IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__REF_EN_B              IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__GPT_CAPIN2            IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__CCM_OUT_0             IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__GPIO1_7               IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__SD2_WP                IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__SPDIF_OUT1            IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__CSI2_DATA_EN          IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__GPIO1_8               IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__SD2_CD                IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__USBH3_PWR             IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__CCM_CLKO2             IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__CCM_OUT_1             IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__DISP2_D1_CS           IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__DISP2_SER_CS          IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__GPIO1_9               IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__SD2_LCTL              IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__USBH3_OC              IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__CCM_CLKO              IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL)
-
-#endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index 39406b7e3228..a7e9bd26a552 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -50,6 +50,7 @@
 #include "common.h"
 #include "devices-imx31.h"
 #include "crmregs-imx3.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 75b7b6aa2720..e6d4b9929571 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -36,6 +36,7 @@
 
 #include "common.h"
 #include "devices-imx27.h"
+#include "ehci.h"
 #include "eukrea-baseboards.h"
 #include "hardware.h"
 #include "iomux-mx27.h"
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 1ffa27169045..62a6e02f4763 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -39,6 +39,7 @@
 
 #include "common.h"
 #include "devices-imx35.h"
+#include "ehci.h"
 #include "eukrea-baseboards.h"
 #include "hardware.h"
 #include "iomux-mx35.h"
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index e978dda1434c..b2ee6e009fe4 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -35,6 +35,7 @@
 
 #include "common.h"
 #include "devices-imx25.h"
+#include "ehci.h"
 #include "eukrea-baseboards.h"
 #include "hardware.h"
 #include "iomux-mx25.h"
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index b61bd8ed5568..ede2bdbb5dd5 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -43,6 +43,7 @@
 
 #include "common.h"
 #include "devices-imx27.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx27.h"
 
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
deleted file mode 100644
index bb3ca0429680..000000000000
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "hardware.h"
-#include "common.h"
-#include "devices-imx27.h"
-#include "iomux-mx27.h"
-
-static const int mx27ipcam_pins[] __initconst = {
-        /* UART1 */
-        PE12_PF_UART1_TXD,
-        PE13_PF_UART1_RXD,
-        /* FEC */
-        PD0_AIN_FEC_TXD0,
-        PD1_AIN_FEC_TXD1,
-        PD2_AIN_FEC_TXD2,
-        PD3_AIN_FEC_TXD3,
-        PD4_AOUT_FEC_RX_ER,
-        PD5_AOUT_FEC_RXD1,
-        PD6_AOUT_FEC_RXD2,
-        PD7_AOUT_FEC_RXD3,
-        PD8_AF_FEC_MDIO,
-        PD9_AIN_FEC_MDC,
-        PD10_AOUT_FEC_CRS,
-        PD11_AOUT_FEC_TX_CLK,
-        PD12_AOUT_FEC_RXD0,
-        PD13_AOUT_FEC_RX_DV,
-        PD14_AOUT_FEC_RX_CLK,
-        PD15_AOUT_FEC_COL,
-        PD16_AIN_FEC_TX_ER,
-        PF23_AIN_FEC_TX_EN,
-};
-
-static void __init mx27ipcam_init(void)
-{
-        imx27_soc_init();
-
-        mxc_gpio_setup_multiple_pins(mx27ipcam_pins, ARRAY_SIZE(mx27ipcam_pins),
-                "mx27ipcam");
-
-        imx27_add_imx_uart0(NULL);
-        imx27_add_fec(NULL);
-        imx27_add_imx2_wdt();
-}
-
-static void __init mx27ipcam_timer_init(void)
-{
-        mx27_clocks_init(25000000);
-}
-
-MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
-        /* maintainer: Freescale Semiconductor, Inc. */
-        .atag_offset = 0x100,
-        .map_io = mx27_map_io,
-        .init_early = imx27_init_early,
-        .init_irq = mx27_init_irq,
-        .init_time      = mx27ipcam_timer_init,
-        .init_machine = mx27ipcam_init,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
deleted file mode 100644
index 9992089d3ad1..000000000000
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- * Copyright 2009 Daniel Schaeffer (daniel.schaeffer@timesys.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices-imx27.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
-
-static const int mx27lite_pins[] __initconst = {
-        /* UART1 */
-        PE12_PF_UART1_TXD,
-        PE13_PF_UART1_RXD,
-        PE14_PF_UART1_CTS,
-        PE15_PF_UART1_RTS,
-        /* FEC */
-        PD0_AIN_FEC_TXD0,
-        PD1_AIN_FEC_TXD1,
-        PD2_AIN_FEC_TXD2,
-        PD3_AIN_FEC_TXD3,
-        PD4_AOUT_FEC_RX_ER,
-        PD5_AOUT_FEC_RXD1,
-        PD6_AOUT_FEC_RXD2,
-        PD7_AOUT_FEC_RXD3,
-        PD8_AF_FEC_MDIO,
-        PD9_AIN_FEC_MDC,
-        PD10_AOUT_FEC_CRS,
-        PD11_AOUT_FEC_TX_CLK,
-        PD12_AOUT_FEC_RXD0,
-        PD13_AOUT_FEC_RX_DV,
-        PD14_AOUT_FEC_RX_CLK,
-        PD15_AOUT_FEC_COL,
-        PD16_AIN_FEC_TX_ER,
-        PF23_AIN_FEC_TX_EN,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static void __init mx27lite_init(void)
-{
-        imx27_soc_init();
-
-        mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
-                "imx27lite");
-        imx27_add_imx_uart0(&uart_pdata);
-        imx27_add_fec(NULL);
-}
-
-static void __init mx27lite_timer_init(void)
-{
-        mx27_clocks_init(26000000);
-}
-
-MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
-        .atag_offset = 0x100,
-        .map_io = mx27_map_io,
-        .init_early = imx27_init_early,
-        .init_irq = mx27_init_irq,
-        .init_time      = mx27lite_timer_init,
-        .init_machine = mx27lite_init,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c
index b899c0b59afd..b1e56a94a382 100644
--- a/arch/arm/mach-imx/mach-imx50.c
+++ b/arch/arm/mach-imx/mach-imx50.c
@@ -23,14 +23,13 @@ static void __init imx50_dt_init(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const char *imx50_dt_board_compat[] __initconst = {
+static const char * const imx50_dt_board_compat[] __initconst = {
         "fsl,imx50",
         NULL
 };
 
 DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
-        .map_io         = mx53_map_io,
-        .init_irq       = mx53_init_irq,
+        .init_irq       = tzic_init_irq,
         .init_machine   = imx50_dt_init,
         .dt_compat      = imx50_dt_board_compat,
         .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/mach-imx51.c
index b8cd968faa52..c77deb3f0893 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/mach-imx51.c
@@ -10,6 +10,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
@@ -17,27 +18,63 @@
 #include <asm/mach/time.h>
 
 #include "common.h"
-#include "mx51.h"
+#include "hardware.h"
+
+static void __init imx51_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX51);
+}
+
+/*
+ * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
+ * the Freescale marketing division. However this did not remove the
+ * hardware from the chip which still needs to be configured for proper
+ * IPU support.
+ */
+#define MX51_MIPI_HSC_BASE 0x83fdc000
+static void __init imx51_ipu_mipi_setup(void)
+{
+        void __iomem *hsc_addr;
+
+        hsc_addr = ioremap(MX51_MIPI_HSC_BASE, SZ_16K);
+        WARN_ON(!hsc_addr);
+
+        /* setup MIPI module to legacy mode */
+        __raw_writel(0xf00, hsc_addr);
+
+        /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
+        __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
+                hsc_addr + 0x800);
+
+        iounmap(hsc_addr);
+}
 
 static void __init imx51_dt_init(void)
 {
         struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
 
         mxc_arch_reset_init_dt();
+        imx51_ipu_mipi_setup();
+        imx_src_init();
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
         platform_device_register_full(&devinfo);
 }
 
-static const char *imx51_dt_board_compat[] __initconst = {
+static void __init imx51_init_late(void)
+{
+        mx51_neon_fixup();
+        imx51_pm_init();
+}
+
+static const char * const imx51_dt_board_compat[] __initconst = {
         "fsl,imx51",
         NULL
 };
 
 DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
-        .map_io         = mx51_map_io,
         .init_early     = imx51_init_early,
-        .init_irq       = mx51_init_irq,
+        .init_irq       = tzic_init_irq,
         .init_machine   = imx51_dt_init,
         .init_late      = imx51_init_late,
         .dt_compat      = imx51_dt_board_compat,
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 2bad387956c0..03dd6ea13acc 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -22,24 +22,35 @@
 
 #include "common.h"
 #include "hardware.h"
-#include "mx53.h"
+
+static void __init imx53_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX53);
+}
 
 static void __init imx53_dt_init(void)
 {
         mxc_arch_reset_init_dt();
+        imx_src_init();
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+
+        imx_aips_allow_unprivileged_access("fsl,imx53-aipstz");
+}
+
+static void __init imx53_init_late(void)
+{
+        imx53_pm_init();
 }
 
-static const char *imx53_dt_board_compat[] __initconst = {
+static const char * const imx53_dt_board_compat[] __initconst = {
         "fsl,imx53",
         NULL
 };
 
 DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
-        .map_io         = mx53_map_io,
         .init_early     = imx53_init_early,
-        .init_irq       = mx53_init_irq,
+        .init_irq       = tzic_init_irq,
         .init_machine   = imx53_dt_init,
         .init_late      = imx53_init_late,
         .dt_compat      = imx53_dt_board_compat,
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index e60456d85c9d..d51c6e99a2e9 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -320,7 +320,7 @@ static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev)
         val >>= OCOTP_CFG3_SPEED_SHIFT;
         val &= 0x3;
 
-        if (val != OCOTP_CFG3_SPEED_1P2GHZ)
+        if ((val != OCOTP_CFG3_SPEED_1P2GHZ) && cpu_is_imx6q())
                 if (dev_pm_opp_disable(cpu_dev, 1200000000))
                         pr_warn("failed to disable 1.2 GHz OPP\n");
         if (val < OCOTP_CFG3_SPEED_996MHZ)
@@ -396,7 +396,7 @@ static void __init imx6q_init_irq(void)
         irqchip_init();
 }
 
-static const char *imx6q_dt_compat[] __initconst = {
+static const char * const imx6q_dt_compat[] __initconst = {
         "fsl,imx6dl",
         "fsl,imx6q",
         NULL,
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index ad323385115c..ed263a21d928 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -70,7 +70,7 @@ static void __init imx6sl_init_irq(void)
         irqchip_init();
 }
 
-static const char *imx6sl_dt_compat[] __initconst = {
+static const char * const imx6sl_dt_compat[] __initconst = {
         "fsl,imx6sl",
         NULL,
 };
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index 02fccf6033ac..673a734165ba 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -12,6 +12,7 @@
 #include <asm/mach/map.h>
 
 #include "common.h"
+#include "cpuidle.h"
 
 static void __init imx6sx_init_machine(void)
 {
@@ -26,6 +27,7 @@ static void __init imx6sx_init_machine(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
 
         imx_anatop_init();
+        imx6sx_pm_init();
 }
 
 static void __init imx6sx_init_irq(void)
@@ -37,7 +39,12 @@ static void __init imx6sx_init_irq(void)
         irqchip_init();
 }
 
-static const char *imx6sx_dt_compat[] __initconst = {
+static void __init imx6sx_init_late(void)
+{
+        imx6q_cpuidle_init();
+}
+
+static const char * const imx6sx_dt_compat[] __initconst = {
         "fsl,imx6sx",
         NULL,
 };
@@ -47,5 +54,6 @@ DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)")
         .init_irq       = imx6sx_init_irq,
         .init_machine   = imx6sx_init_machine,
         .dt_compat      = imx6sx_dt_compat,
+        .init_late      = imx6sx_init_late,
         .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index ea1fa199c148..0d01e367b062 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -39,6 +39,7 @@
 
 #include "common.h"
 #include "devices-imx25.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx25.h"
 #include "mx25.h"
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 435a5428a678..9ef4640f3660 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -40,6 +40,7 @@
 #include "3ds_debugboard.h"
 #include "common.h"
 #include "devices-imx27.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx27.h"
 #include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 4217871a9653..453f41a2c5a9 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -40,6 +40,7 @@
 #include "3ds_debugboard.h"
 #include "common.h"
 #include "devices-imx31.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index eee042fa2768..e9549a3c0223 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -45,6 +45,7 @@
 #include "board-mx31lilly.h"
 #include "common.h"
 #include "devices-imx31.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index fa15d0b6118d..57eac6f45fab 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -42,6 +42,7 @@
 #include "board-mx31lite.h"
 #include "common.h"
 #include "devices-imx31.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 08730f238449..bb6f8a52a6b8 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -47,6 +47,7 @@
 #include "board-mx31moboard.h"
 #include "common.h"
 #include "devices-imx31.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "ulpi.h"
@@ -434,10 +435,8 @@ static int __init moboard_usbh2_init(void)
                 return -ENODEV;
 
         pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-        if (IS_ERR(pdev))
-                return PTR_ERR(pdev);
 
-        return 0;
+        return PTR_ERR_OR_ZERO(pdev);
 }
 
 static const struct gpio_led mx31moboard_leds[] __initconst = {
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 4e8b184d773b..72cd77d21f63 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -50,6 +50,7 @@
 #include "3ds_debugboard.h"
 #include "common.h"
 #include "devices-imx35.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx35.h"
 
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 12212378c672..2d1c50bd8bdf 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -36,6 +36,7 @@
 
 #include "common.h"
 #include "devices-imx27.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx27.h"
 #include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 81b8affb9448..8eb1570f7851 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -45,6 +45,7 @@
 
 #include "common.h"
 #include "devices-imx31.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "pcm037.h"
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 6c56fb5553c7..ee862ad6b6fc 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -36,6 +36,7 @@
 #include "board-pcm038.h"
 #include "common.h"
 #include "devices-imx27.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx27.h"
 #include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index c62b5d261345..b623bcaca76c 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -35,6 +35,7 @@
 
 #include "common.h"
 #include "devices-imx35.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx35.h"
 #include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
index c44602758120..ee7e57b752a7 100644
--- a/arch/arm/mach-imx/mach-vf610.c
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -20,7 +20,7 @@ static void __init vf610_init_machine(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const char *vf610_dt_compat[] __initconst = {
+static const char * const vf610_dt_compat[] __initconst = {
         "fsl,vf610",
         NULL,
 };
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 872b3c6ba408..97836e94451c 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -34,6 +34,7 @@
 
 #include "common.h"
 #include "devices-imx35.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx35.h"
 
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
deleted file mode 100644
index 4c112021aa4e..000000000000
--- a/arch/arm/mach-imx/mm-imx5.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License.  You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- *
- * Create static mapping between physical to virtual memory.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/of_address.h>
-
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices/devices-common.h"
-#include "hardware.h"
-#include "iomux-v3.h"
-
-/*
- * Define the MX51 memory map.
- */
-static struct map_desc mx51_io_desc[] __initdata = {
-        imx_map_entry(MX51, TZIC, MT_DEVICE),
-        imx_map_entry(MX51, IRAM, MT_DEVICE),
-        imx_map_entry(MX51, AIPS1, MT_DEVICE),
-        imx_map_entry(MX51, SPBA0, MT_DEVICE),
-        imx_map_entry(MX51, AIPS2, MT_DEVICE),
-};
-
-/*
- * Define the MX53 memory map.
- */
-static struct map_desc mx53_io_desc[] __initdata = {
-        imx_map_entry(MX53, TZIC, MT_DEVICE),
-        imx_map_entry(MX53, AIPS1, MT_DEVICE),
-        imx_map_entry(MX53, SPBA0, MT_DEVICE),
-        imx_map_entry(MX53, AIPS2, MT_DEVICE),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx51_map_io(void)
-{
-        iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
-}
-
-void __init mx53_map_io(void)
-{
-        iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
-}
-
-/*
- * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
- * the Freescale marketing division. However this did not remove the
- * hardware from the chip which still needs to be configured for proper
- * IPU support.
- */
-static void __init imx51_ipu_mipi_setup(void)
-{
-        void __iomem *hsc_addr;
-        hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR);
-
-        /* setup MIPI module to legacy mode */
-        __raw_writel(0xf00, hsc_addr);
-
-        /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
-        __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
-                hsc_addr + 0x800);
-}
-
-void __init imx51_init_early(void)
-{
-        imx51_ipu_mipi_setup();
-        mxc_set_cpu_type(MXC_CPU_MX51);
-        mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
-        imx_src_init();
-}
-
-void __init imx53_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX53);
-        imx_src_init();
-}
-
-void __init mx51_init_irq(void)
-{
-        tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
-}
-
-void __init mx53_init_irq(void)
-{
-        struct device_node *np;
-        void __iomem *base;
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx53-tzic");
-        base = of_iomap(np, 0);
-        WARN_ON(!base);
-
-        tzic_init_irq(base);
-}
-
-static struct sdma_platform_data imx51_sdma_pdata __initdata = {
-        .fw_name = "sdma-imx51.bin",
-};
-
-static const struct resource imx51_audmux_res[] __initconst = {
-        DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
-};
-
-void __init imx51_soc_init(void)
-{
-        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
-        mxc_device_init();
-
-        /* i.mx51 has the i.mx35 type gpio */
-        mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
-        mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
-        mxc_register_gpio("imx35-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
-        mxc_register_gpio("imx35-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
-
-        pinctrl_provide_dummies();
-
-        /* i.mx51 has the i.mx35 type sdma */
-        imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
-
-        /* Setup AIPS registers */
-        imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
-        imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
-
-        /* i.mx51 has the i.mx31 type audmux */
-        platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
-                                        ARRAY_SIZE(imx51_audmux_res));
-}
-
-void __init imx51_init_late(void)
-{
-        mx51_neon_fixup();
-        imx5_pm_init();
-}
-
-void __init imx53_init_late(void)
-{
-        imx5_pm_init();
-}
diff --git a/arch/arm/mach-imx/mx1-camera-fiq-ksym.c b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
deleted file mode 100644
index fb38436ca67f..000000000000
--- a/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Exported ksyms of ARCH_MX1
- *
- * Copyright (C) 2008, Darius Augulis <augulis.darius@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/module.h>
-
-#include <linux/platform_data/camera-mx1.h>
-
-/* IMX camera FIQ handler */
-EXPORT_SYMBOL(mx1_camera_sof_fiq_start);
-EXPORT_SYMBOL(mx1_camera_sof_fiq_end);
diff --git a/arch/arm/mach-imx/mx1-camera-fiq.S b/arch/arm/mach-imx/mx1-camera-fiq.S
deleted file mode 100644
index 9c69aa65bf17..000000000000
--- a/arch/arm/mach-imx/mx1-camera-fiq.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- *  Copyright (C) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- *
- *  Based on linux/arch/arm/lib/floppydma.S
- *      Copyright (C) 1995, 1996 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-                .text
-                .global mx1_camera_sof_fiq_end
-                .global mx1_camera_sof_fiq_start
-mx1_camera_sof_fiq_start:
-                @ enable dma
-                ldr     r12, [r9]
-                orr     r12, r12, #0x00000001
-                str     r12, [r9]
-                @ unmask DMA interrupt
-                ldr     r12, [r8]
-                bic     r12, r12, r13
-                str     r12, [r8]
-                @ disable SOF interrupt
-                ldr     r12, [r10]
-                bic     r12, r12, #0x00010000
-                str     r12, [r10]
-                @ clear SOF flag
-                mov     r12, #0x00010000
-                str     r12, [r11]
-                @ return from FIQ
-                subs    pc, lr, #4
-mx1_camera_sof_fiq_end:
diff --git a/arch/arm/mach-imx/mx31moboard-devboard.c b/arch/arm/mach-imx/mx31moboard-devboard.c
index 52d5b1574721..1e91a0918e83 100644
--- a/arch/arm/mach-imx/mx31moboard-devboard.c
+++ b/arch/arm/mach-imx/mx31moboard-devboard.c
@@ -24,6 +24,7 @@
 
 #include "common.h"
 #include "devices-imx31.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "ulpi.h"
@@ -213,10 +214,8 @@ static int __init devboard_usbh1_init(void)
         usbh1_pdata.otg = phy;
 
         pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
-        if (IS_ERR(pdev))
-                return PTR_ERR(pdev);
 
-        return 0;
+        return PTR_ERR_OR_ZERO(pdev);
 }
 
 
diff --git a/arch/arm/mach-imx/mx31moboard-marxbot.c b/arch/arm/mach-imx/mx31moboard-marxbot.c
index a4f43e90f3c1..2e895a82a6eb 100644
--- a/arch/arm/mach-imx/mx31moboard-marxbot.c
+++ b/arch/arm/mach-imx/mx31moboard-marxbot.c
@@ -28,6 +28,7 @@
 
 #include "common.h"
 #include "devices-imx31.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "ulpi.h"
@@ -327,10 +328,8 @@ static int __init marxbot_usbh1_init(void)
         usbh1_pdata.otg = phy;
 
         pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
-        if (IS_ERR(pdev))
-                return PTR_ERR(pdev);
 
-        return 0;
+        return PTR_ERR_OR_ZERO(pdev);
 }
 
 static const struct fsl_usb2_platform_data usb_pdata __initconst = {
diff --git a/arch/arm/mach-imx/mx31moboard-smartbot.c b/arch/arm/mach-imx/mx31moboard-smartbot.c
index 04ae45dbfaa7..89fc35a64448 100644
--- a/arch/arm/mach-imx/mx31moboard-smartbot.c
+++ b/arch/arm/mach-imx/mx31moboard-smartbot.c
@@ -28,6 +28,7 @@
 #include "board-mx31moboard.h"
 #include "common.h"
 #include "devices-imx31.h"
+#include "ehci.h"
 #include "hardware.h"
 #include "iomux-mx3.h"
 #include "ulpi.h"
@@ -141,10 +142,8 @@ static int __init smartbot_otg_host_init(void)
                 return -ENODEV;
 
         pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata);
-        if (IS_ERR(pdev))
-                return PTR_ERR(pdev);
 
-        return 0;
+        return PTR_ERR_OR_ZERO(pdev);
 }
 #else
 static inline int smartbot_otg_host_init(void) { return 0; }
diff --git a/arch/arm/mach-imx/mx51.h b/arch/arm/mach-imx/mx51.h
deleted file mode 100644
index af844f76261a..000000000000
--- a/arch/arm/mach-imx/mx51.h
+++ /dev/null
@@ -1,346 +0,0 @@
-#ifndef __MACH_MX51_H__
-#define __MACH_MX51_H__
-
-/*
- * IROM
- */
-#define MX51_IROM_BASE_ADDR             0x0
-#define MX51_IROM_SIZE                  SZ_64K
-
-/*
- * IRAM
- */
-#define MX51_IRAM_BASE_ADDR             0x1ffe0000      /* internal ram */
-#define MX51_IRAM_PARTITIONS            16
-#define MX51_IRAM_SIZE          (MX51_IRAM_PARTITIONS * SZ_8K)  /* 128KB */
-
-#define MX51_GPU_BASE_ADDR              0x20000000
-#define MX51_GPU_CTRL_BASE_ADDR         0x30000000
-#define MX51_IPU_CTRL_BASE_ADDR         0x40000000
-
-/*
- * SPBA global module enabled #0
- */
-#define MX51_SPBA0_BASE_ADDR            0x70000000
-#define MX51_SPBA0_SIZE                 SZ_1M
-
-#define MX51_ESDHC1_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x04000)
-#define MX51_ESDHC2_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x08000)
-#define MX51_UART3_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x0c000)
-#define MX51_ECSPI1_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x10000)
-#define MX51_SSI2_BASE_ADDR             (MX51_SPBA0_BASE_ADDR + 0x14000)
-#define MX51_ESDHC3_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x20000)
-#define MX51_ESDHC4_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x24000)
-#define MX51_SPDIF_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x28000)
-#define MX51_ATA_DMA_BASE_ADDR          (MX51_SPBA0_BASE_ADDR + 0x30000)
-#define MX51_SLIM_DMA_BASE_ADDR         (MX51_SPBA0_BASE_ADDR + 0x34000)
-#define MX51_HSI2C_DMA_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x38000)
-#define MX51_SPBA_CTRL_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x3c000)
-
-/*
- * AIPS 1
- */
-#define MX51_AIPS1_BASE_ADDR            0x73f00000
-#define MX51_AIPS1_SIZE                 SZ_1M
-
-#define MX51_USB_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x80000)
-#define MX51_USB_OTG_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0000)
-#define MX51_USB_HS1_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0200)
-#define MX51_USB_HS2_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0400)
-#define MX51_GPIO1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x84000)
-#define MX51_GPIO2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x88000)
-#define MX51_GPIO3_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x8c000)
-#define MX51_GPIO4_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x90000)
-#define MX51_KPP_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x94000)
-#define MX51_WDOG1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x98000)
-#define MX51_WDOG2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x9c000)
-#define MX51_GPT1_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xa0000)
-#define MX51_SRTC_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xa4000)
-#define MX51_IOMUXC_BASE_ADDR           (MX51_AIPS1_BASE_ADDR + 0xa8000)
-#define MX51_EPIT1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xac000)
-#define MX51_EPIT2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xb0000)
-#define MX51_PWM1_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xb4000)
-#define MX51_PWM2_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xb8000)
-#define MX51_UART1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xbc000)
-#define MX51_UART2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xc0000)
-#define MX51_SRC_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0xd0000)
-#define MX51_CCM_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0xd4000)
-#define MX51_GPC_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0xd8000)
-
-/*
- * AIPS 2
- */
-#define MX51_AIPS2_BASE_ADDR            0x83f00000
-#define MX51_AIPS2_SIZE                 SZ_1M
-
-#define MX51_PLL1_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0x80000)
-#define MX51_PLL2_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0x84000)
-#define MX51_PLL3_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0x88000)
-#define MX51_AHBMAX_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0x94000)
-#define MX51_IIM_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0x98000)
-#define MX51_CSU_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0x9c000)
-#define MX51_ARM_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xa0000)
-#define MX51_OWIRE_BASE_ADDR            (MX51_AIPS2_BASE_ADDR + 0xa4000)
-#define MX51_FIRI_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xa8000)
-#define MX51_ECSPI2_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xac000)
-#define MX51_SDMA_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xb0000)
-#define MX51_SCC_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xb4000)
-#define MX51_ROMCP_BASE_ADDR            (MX51_AIPS2_BASE_ADDR + 0xb8000)
-#define MX51_RTIC_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xbc000)
-#define MX51_CSPI_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xc0000)
-#define MX51_I2C2_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xc4000)
-#define MX51_I2C1_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xc8000)
-#define MX51_SSI1_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xcc000)
-#define MX51_AUDMUX_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xd0000)
-#define MX51_M4IF_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xd8000)
-#define MX51_ESDCTL_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xd9000)
-#define MX51_WEIM_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xda000)
-#define MX51_NFC_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xdb000)
-#define MX51_EMI_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xdbf00)
-#define MX51_MIPI_HSC_BASE_ADDR         (MX51_AIPS2_BASE_ADDR + 0xdc000)
-#define MX51_ATA_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xe0000)
-#define MX51_SIM_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xe4000)
-#define MX51_SSI3_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xe8000)
-#define MX51_FEC_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xec000)
-#define MX51_TVE_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xf0000)
-#define MX51_VPU_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xf4000)
-#define MX51_SAHARA_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xf8000)
-
-#define MX51_CSD0_BASE_ADDR             0x90000000
-#define MX51_CSD1_BASE_ADDR             0xa0000000
-#define MX51_CS0_BASE_ADDR              0xb0000000
-#define MX51_CS1_BASE_ADDR              0xb8000000
-#define MX51_CS2_BASE_ADDR              0xc0000000
-#define MX51_CS3_BASE_ADDR              0xc8000000
-#define MX51_CS4_BASE_ADDR              0xcc000000
-#define MX51_CS5_BASE_ADDR              0xce000000
-
-/*
- * NFC
- */
-#define MX51_NFC_AXI_BASE_ADDR          0xcfff0000      /* NAND flash AXI */
-#define MX51_NFC_AXI_SIZE               SZ_64K
-
-#define MX51_GPU2D_BASE_ADDR            0xd0000000
-#define MX51_TZIC_BASE_ADDR             0xe0000000
-#define MX51_TZIC_SIZE                  SZ_16K
-
-#define MX51_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX51_IO_ADDRESS(x)              IOMEM(MX51_IO_P2V(x))
-
-/*
- * defines for SPBA modules
- */
-#define MX51_SPBA_SDHC1 0x04
-#define MX51_SPBA_SDHC2 0x08
-#define MX51_SPBA_UART3 0x0c
-#define MX51_SPBA_CSPI1 0x10
-#define MX51_SPBA_SSI2  0x14
-#define MX51_SPBA_SDHC3 0x20
-#define MX51_SPBA_SDHC4 0x24
-#define MX51_SPBA_SPDIF 0x28
-#define MX51_SPBA_ATA   0x30
-#define MX51_SPBA_SLIM  0x34
-#define MX51_SPBA_HSI2C 0x38
-#define MX51_SPBA_CTRL  0x3c
-
-/*
- * Defines for modules using static and dynamic DMA channels
- */
-#define MX51_MXC_DMA_CHANNEL_IRAM       30
-#define MX51_MXC_DMA_CHANNEL_SPDIF_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART1_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART1_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART2_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART2_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART3_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART3_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_MMC1       MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_MMC2       MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_SSI1_RX    MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_SSI1_TX    MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_SSI2_RX    MXC_DMA_DYNAMIC_CHANNEL
-#ifdef CONFIG_SDMA_IRAM
-#define MX51_MXC_DMA_CHANNEL_SSI2_TX    (MX51_MXC_DMA_CHANNEL_IRAM + 1)
-#else                           /*CONFIG_SDMA_IRAM */
-#define MX51_MXC_DMA_CHANNEL_SSI2_TX    MXC_DMA_DYNAMIC_CHANNEL
-#endif                          /*CONFIG_SDMA_IRAM */
-#define MX51_MXC_DMA_CHANNEL_CSPI1_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI1_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI2_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI2_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI3_RX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI3_TX   MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_ATA_RX     MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_ATA_TX     MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_MEMORY     MXC_DMA_DYNAMIC_CHANNEL
-
-#define MX51_IS_MEM_DEVICE_NONSHARED(x)         0
-
-/*
- * DMA request assignments
- */
-#define MX51_DMA_REQ_VPU                0
-#define MX51_DMA_REQ_GPC                1
-#define MX51_DMA_REQ_ATA_RX             2
-#define MX51_DMA_REQ_ATA_TX             3
-#define MX51_DMA_REQ_ATA_TX_END         4
-#define MX51_DMA_REQ_SLIM_B             5
-#define MX51_DMA_REQ_CSPI1_RX           6
-#define MX51_DMA_REQ_CSPI1_TX           7
-#define MX51_DMA_REQ_CSPI2_RX           8
-#define MX51_DMA_REQ_CSPI2_TX           9
-#define MX51_DMA_REQ_HS_I2C_TX          10
-#define MX51_DMA_REQ_HS_I2C_RX          11
-#define MX51_DMA_REQ_FIRI_RX            12
-#define MX51_DMA_REQ_FIRI_TX            13
-#define MX51_DMA_REQ_EXTREQ1            14
-#define MX51_DMA_REQ_GPU                15
-#define MX51_DMA_REQ_UART2_RX           16
-#define MX51_DMA_REQ_UART2_TX           17
-#define MX51_DMA_REQ_UART1_RX           18
-#define MX51_DMA_REQ_UART1_TX           19
-#define MX51_DMA_REQ_SDHC1              20
-#define MX51_DMA_REQ_SDHC2              21
-#define MX51_DMA_REQ_SSI2_RX1           22
-#define MX51_DMA_REQ_SSI2_TX1           23
-#define MX51_DMA_REQ_SSI2_RX0           24
-#define MX51_DMA_REQ_SSI2_TX0           25
-#define MX51_DMA_REQ_SSI1_RX1           26
-#define MX51_DMA_REQ_SSI1_TX1           27
-#define MX51_DMA_REQ_SSI1_RX0           28
-#define MX51_DMA_REQ_SSI1_TX0           29
-#define MX51_DMA_REQ_EMI_RD             30
-#define MX51_DMA_REQ_CTI2_0             31
-#define MX51_DMA_REQ_EMI_WR             32
-#define MX51_DMA_REQ_CTI2_1             33
-#define MX51_DMA_REQ_EPIT2              34
-#define MX51_DMA_REQ_SSI3_RX1           35
-#define MX51_DMA_REQ_IPU                36
-#define MX51_DMA_REQ_SSI3_TX1           37
-#define MX51_DMA_REQ_CSPI_RX            38
-#define MX51_DMA_REQ_CSPI_TX            39
-#define MX51_DMA_REQ_SDHC3              40
-#define MX51_DMA_REQ_SDHC4              41
-#define MX51_DMA_REQ_SLIM_B_TX          42
-#define MX51_DMA_REQ_UART3_RX           43
-#define MX51_DMA_REQ_UART3_TX           44
-#define MX51_DMA_REQ_SPDIF              45
-#define MX51_DMA_REQ_SSI3_RX0           46
-#define MX51_DMA_REQ_SSI3_TX0           47
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX51_INT_BASE                   (NR_IRQS_LEGACY + 0)
-#define MX51_INT_RESV0                  (NR_IRQS_LEGACY + 0)
-#define MX51_INT_ESDHC1                 (NR_IRQS_LEGACY + 1)
-#define MX51_INT_ESDHC2                 (NR_IRQS_LEGACY + 2)
-#define MX51_INT_ESDHC3                 (NR_IRQS_LEGACY + 3)
-#define MX51_INT_ESDHC4                 (NR_IRQS_LEGACY + 4)
-#define MX51_INT_RESV5                  (NR_IRQS_LEGACY + 5)
-#define MX51_INT_SDMA                   (NR_IRQS_LEGACY + 6)
-#define MX51_INT_IOMUX                  (NR_IRQS_LEGACY + 7)
-#define MX51_INT_NFC                    (NR_IRQS_LEGACY + 8)
-#define MX51_INT_VPU                    (NR_IRQS_LEGACY + 9)
-#define MX51_INT_IPU_ERR                (NR_IRQS_LEGACY + 10)
-#define MX51_INT_IPU_SYN                (NR_IRQS_LEGACY + 11)
-#define MX51_INT_GPU                    (NR_IRQS_LEGACY + 12)
-#define MX51_INT_RESV13                 (NR_IRQS_LEGACY + 13)
-#define MX51_INT_USB_HS1                (NR_IRQS_LEGACY + 14)
-#define MX51_INT_EMI                    (NR_IRQS_LEGACY + 15)
-#define MX51_INT_USB_HS2                (NR_IRQS_LEGACY + 16)
-#define MX51_INT_USB_HS3                (NR_IRQS_LEGACY + 17)
-#define MX51_INT_USB_OTG                (NR_IRQS_LEGACY + 18)
-#define MX51_INT_SAHARA_H0              (NR_IRQS_LEGACY + 19)
-#define MX51_INT_SAHARA_H1              (NR_IRQS_LEGACY + 20)
-#define MX51_INT_SCC_SMN                (NR_IRQS_LEGACY + 21)
-#define MX51_INT_SCC_STZ                (NR_IRQS_LEGACY + 22)
-#define MX51_INT_SCC_SCM                (NR_IRQS_LEGACY + 23)
-#define MX51_INT_SRTC_NTZ               (NR_IRQS_LEGACY + 24)
-#define MX51_INT_SRTC_TZ                (NR_IRQS_LEGACY + 25)
-#define MX51_INT_RTIC                   (NR_IRQS_LEGACY + 26)
-#define MX51_INT_CSU                    (NR_IRQS_LEGACY + 27)
-#define MX51_INT_SLIM_B                 (NR_IRQS_LEGACY + 28)
-#define MX51_INT_SSI1                   (NR_IRQS_LEGACY + 29)
-#define MX51_INT_SSI2                   (NR_IRQS_LEGACY + 30)
-#define MX51_INT_UART1                  (NR_IRQS_LEGACY + 31)
-#define MX51_INT_UART2                  (NR_IRQS_LEGACY + 32)
-#define MX51_INT_UART3                  (NR_IRQS_LEGACY + 33)
-#define MX51_INT_RESV34                 (NR_IRQS_LEGACY + 34)
-#define MX51_INT_RESV35                 (NR_IRQS_LEGACY + 35)
-#define MX51_INT_ECSPI1                 (NR_IRQS_LEGACY + 36)
-#define MX51_INT_ECSPI2                 (NR_IRQS_LEGACY + 37)
-#define MX51_INT_CSPI                   (NR_IRQS_LEGACY + 38)
-#define MX51_INT_GPT                    (NR_IRQS_LEGACY + 39)
-#define MX51_INT_EPIT1                  (NR_IRQS_LEGACY + 40)
-#define MX51_INT_EPIT2                  (NR_IRQS_LEGACY + 41)
-#define MX51_INT_GPIO1_INT7             (NR_IRQS_LEGACY + 42)
-#define MX51_INT_GPIO1_INT6             (NR_IRQS_LEGACY + 43)
-#define MX51_INT_GPIO1_INT5             (NR_IRQS_LEGACY + 44)
-#define MX51_INT_GPIO1_INT4             (NR_IRQS_LEGACY + 45)
-#define MX51_INT_GPIO1_INT3             (NR_IRQS_LEGACY + 46)
-#define MX51_INT_GPIO1_INT2             (NR_IRQS_LEGACY + 47)
-#define MX51_INT_GPIO1_INT1             (NR_IRQS_LEGACY + 48)
-#define MX51_INT_GPIO1_INT0             (NR_IRQS_LEGACY + 49)
-#define MX51_INT_GPIO1_LOW              (NR_IRQS_LEGACY + 50)
-#define MX51_INT_GPIO1_HIGH             (NR_IRQS_LEGACY + 51)
-#define MX51_INT_GPIO2_LOW              (NR_IRQS_LEGACY + 52)
-#define MX51_INT_GPIO2_HIGH             (NR_IRQS_LEGACY + 53)
-#define MX51_INT_GPIO3_LOW              (NR_IRQS_LEGACY + 54)
-#define MX51_INT_GPIO3_HIGH             (NR_IRQS_LEGACY + 55)
-#define MX51_INT_GPIO4_LOW              (NR_IRQS_LEGACY + 56)
-#define MX51_INT_GPIO4_HIGH             (NR_IRQS_LEGACY + 57)
-#define MX51_INT_WDOG1                  (NR_IRQS_LEGACY + 58)
-#define MX51_INT_WDOG2                  (NR_IRQS_LEGACY + 59)
-#define MX51_INT_KPP                    (NR_IRQS_LEGACY + 60)
-#define MX51_INT_PWM1                   (NR_IRQS_LEGACY + 61)
-#define MX51_INT_I2C1                   (NR_IRQS_LEGACY + 62)
-#define MX51_INT_I2C2                   (NR_IRQS_LEGACY + 63)
-#define MX51_INT_HS_I2C                 (NR_IRQS_LEGACY + 64)
-#define MX51_INT_RESV65                 (NR_IRQS_LEGACY + 65)
-#define MX51_INT_RESV66                 (NR_IRQS_LEGACY + 66)
-#define MX51_INT_SIM_IPB                (NR_IRQS_LEGACY + 67)
-#define MX51_INT_SIM_DAT                (NR_IRQS_LEGACY + 68)
-#define MX51_INT_IIM                    (NR_IRQS_LEGACY + 69)
-#define MX51_INT_ATA                    (NR_IRQS_LEGACY + 70)
-#define MX51_INT_CCM1                   (NR_IRQS_LEGACY + 71)
-#define MX51_INT_CCM2                   (NR_IRQS_LEGACY + 72)
-#define MX51_INT_GPC1                   (NR_IRQS_LEGACY + 73)
-#define MX51_INT_GPC2                   (NR_IRQS_LEGACY + 74)
-#define MX51_INT_SRC                    (NR_IRQS_LEGACY + 75)
-#define MX51_INT_NM                     (NR_IRQS_LEGACY + 76)
-#define MX51_INT_PMU                    (NR_IRQS_LEGACY + 77)
-#define MX51_INT_CTI_IRQ                (NR_IRQS_LEGACY + 78)
-#define MX51_INT_CTI1_TG0               (NR_IRQS_LEGACY + 79)
-#define MX51_INT_CTI1_TG1               (NR_IRQS_LEGACY + 80)
-#define MX51_INT_MCG_ERR                (NR_IRQS_LEGACY + 81)
-#define MX51_INT_MCG_TMR                (NR_IRQS_LEGACY + 82)
-#define MX51_INT_MCG_FUNC               (NR_IRQS_LEGACY + 83)
-#define MX51_INT_GPU2_IRQ               (NR_IRQS_LEGACY + 84)
-#define MX51_INT_GPU2_BUSY              (NR_IRQS_LEGACY + 85)
-#define MX51_INT_RESV86                 (NR_IRQS_LEGACY + 86)
-#define MX51_INT_FEC                    (NR_IRQS_LEGACY + 87)
-#define MX51_INT_OWIRE                  (NR_IRQS_LEGACY + 88)
-#define MX51_INT_CTI1_TG2               (NR_IRQS_LEGACY + 89)
-#define MX51_INT_SJC                    (NR_IRQS_LEGACY + 90)
-#define MX51_INT_SPDIF                  (NR_IRQS_LEGACY + 91)
-#define MX51_INT_TVE                    (NR_IRQS_LEGACY + 92)
-#define MX51_INT_FIRI                   (NR_IRQS_LEGACY + 93)
-#define MX51_INT_PWM2                   (NR_IRQS_LEGACY + 94)
-#define MX51_INT_SLIM_EXP               (NR_IRQS_LEGACY + 95)
-#define MX51_INT_SSI3                   (NR_IRQS_LEGACY + 96)
-#define MX51_INT_EMI_BOOT               (NR_IRQS_LEGACY + 97)
-#define MX51_INT_CTI1_TG3               (NR_IRQS_LEGACY + 98)
-#define MX51_INT_SMC_RX                 (NR_IRQS_LEGACY + 99)
-#define MX51_INT_VPU_IDLE               (NR_IRQS_LEGACY + 100)
-#define MX51_INT_EMI_NFC                (NR_IRQS_LEGACY + 101)
-#define MX51_INT_GPU_IDLE               (NR_IRQS_LEGACY + 102)
-
-#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-extern int mx51_revision(void);
-extern void mx51_display_revision(void);
-#endif
-
-#endif  /* ifndef __MACH_MX51_H__ */
diff --git a/arch/arm/mach-imx/mx53.h b/arch/arm/mach-imx/mx53.h
deleted file mode 100644
index f829d1c22501..000000000000
--- a/arch/arm/mach-imx/mx53.h
+++ /dev/null
@@ -1,342 +0,0 @@
-#ifndef __MACH_MX53_H__
-#define __MACH_MX53_H__
-
-/*
- * IROM
- */
-#define MX53_IROM_BASE_ADDR             0x0
-#define MX53_IROM_SIZE                  SZ_64K
-
-/* TZIC */
-#define MX53_TZIC_BASE_ADDR             0x0FFFC000
-#define MX53_TZIC_SIZE                  SZ_16K
-
-/*
- * AHCI SATA
- */
-#define MX53_SATA_BASE_ADDR             0x10000000
-
-/*
- * NFC
- */
-#define MX53_NFC_AXI_BASE_ADDR  0xF7FF0000      /* NAND flash AXI */
-#define MX53_NFC_AXI_SIZE               SZ_64K
-
-/*
- * IRAM
- */
-#define MX53_IRAM_BASE_ADDR     0xF8000000      /* internal ram */
-#define MX53_IRAM_PARTITIONS    16
-#define MX53_IRAM_SIZE          (MX53_IRAM_PARTITIONS * SZ_8K)  /* 128KB */
-
-/*
- * Graphics Memory of GPU
- */
-#define MX53_IPU_CTRL_BASE_ADDR 0x18000000
-#define MX53_GPU2D_BASE_ADDR            0x20000000
-#define MX53_GPU_BASE_ADDR              0x30000000
-#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000
-
-#define MX53_DEBUG_BASE_ADDR            0x40000000
-#define MX53_DEBUG_SIZE         SZ_1M
-#define MX53_ETB_BASE_ADDR              (MX53_DEBUG_BASE_ADDR + 0x00001000)
-#define MX53_ETM_BASE_ADDR              (MX53_DEBUG_BASE_ADDR + 0x00002000)
-#define MX53_TPIU_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00003000)
-#define MX53_CTI0_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00004000)
-#define MX53_CTI1_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00005000)
-#define MX53_CTI2_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00006000)
-#define MX53_CTI3_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00007000)
-#define MX53_CORTEX_DBG_BASE_ADDR       (MX53_DEBUG_BASE_ADDR + 0x00008000)
-
-/*
- * SPBA global module enabled #0
- */
-#define MX53_SPBA0_BASE_ADDR            0x50000000
-#define MX53_SPBA0_SIZE         SZ_1M
-
-#define MX53_ESDHC1_BASE_ADDR   (MX53_SPBA0_BASE_ADDR + 0x00004000)
-#define MX53_ESDHC2_BASE_ADDR   (MX53_SPBA0_BASE_ADDR + 0x00008000)
-#define MX53_UART3_BASE_ADDR            (MX53_SPBA0_BASE_ADDR + 0x0000C000)
-#define MX53_ECSPI1_BASE_ADDR           (MX53_SPBA0_BASE_ADDR + 0x00010000)
-#define MX53_SSI2_BASE_ADDR             (MX53_SPBA0_BASE_ADDR + 0x00014000)
-#define MX53_ESDHC3_BASE_ADDR   (MX53_SPBA0_BASE_ADDR + 0x00020000)
-#define MX53_ESDHC4_BASE_ADDR   (MX53_SPBA0_BASE_ADDR + 0x00024000)
-#define MX53_SPDIF_BASE_ADDR            (MX53_SPBA0_BASE_ADDR + 0x00028000)
-#define MX53_ASRC_BASE_ADDR             (MX53_SPBA0_BASE_ADDR + 0x0002C000)
-#define MX53_ATA_DMA_BASE_ADDR  (MX53_SPBA0_BASE_ADDR + 0x00030000)
-#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000)
-#define MX53_HSI2C_DMA_BASE_ADDR        (MX53_SPBA0_BASE_ADDR + 0x00038000)
-#define MX53_SPBA_CTRL_BASE_ADDR        (MX53_SPBA0_BASE_ADDR + 0x0003C000)
-
-/*
- * AIPS 1
- */
-#define MX53_AIPS1_BASE_ADDR    0x53F00000
-#define MX53_AIPS1_SIZE         SZ_1M
-
-#define MX53_OTG_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x00080000)
-#define MX53_GPIO1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00084000)
-#define MX53_GPIO2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00088000)
-#define MX53_GPIO3_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x0008C000)
-#define MX53_GPIO4_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00090000)
-#define MX53_KPP_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x00094000)
-#define MX53_WDOG1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00098000)
-#define MX53_WDOG2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x0009C000)
-#define MX53_GPT1_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000A0000)
-#define MX53_SRTC_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000A4000)
-#define MX53_IOMUXC_BASE_ADDR   (MX53_AIPS1_BASE_ADDR + 0x000A8000)
-#define MX53_EPIT1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000AC000)
-#define MX53_EPIT2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000B0000)
-#define MX53_PWM1_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000B4000)
-#define MX53_PWM2_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000B8000)
-#define MX53_UART1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000BC000)
-#define MX53_UART2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000C0000)
-#define MX53_SRC_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x000D0000)
-#define MX53_CCM_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x000D4000)
-#define MX53_GPC_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x000D8000)
-#define MX53_GPIO5_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000DC000)
-#define MX53_GPIO6_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000E0000)
-#define MX53_GPIO7_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000E4000)
-#define MX53_ATA_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x000E8000)
-#define MX53_I2C3_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000EC000)
-#define MX53_UART4_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000F0000)
-
-/*
- * AIPS 2
- */
-#define MX53_AIPS2_BASE_ADDR            0x63F00000
-#define MX53_AIPS2_SIZE                 SZ_1M
-
-#define MX53_PLL1_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x00080000)
-#define MX53_PLL2_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x00084000)
-#define MX53_PLL3_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x00088000)
-#define MX53_PLL4_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x0008C000)
-#define MX53_UART5_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x00090000)
-#define MX53_AHBMAX_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x00094000)
-#define MX53_IIM_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x00098000)
-#define MX53_CSU_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x0009C000)
-#define MX53_ARM_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000A0000)
-#define MX53_OWIRE_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x000A4000)
-#define MX53_FIRI_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000A8000)
-#define MX53_ECSPI2_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000AC000)
-#define MX53_SDMA_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000B0000)
-#define MX53_SCC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000B4000)
-#define MX53_ROMCP_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x000B8000)
-#define MX53_RTIC_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000BC000)
-#define MX53_CSPI_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000C0000)
-#define MX53_I2C2_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000C4000)
-#define MX53_I2C1_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000C8000)
-#define MX53_SSI1_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000CC000)
-#define MX53_AUDMUX_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000D0000)
-#define MX53_RTC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000D4000)
-#define MX53_M4IF_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000D8000)
-#define MX53_ESDCTL_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000D9000)
-#define MX53_WEIM_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000DA000)
-#define MX53_NFC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000DB000)
-#define MX53_EMI_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000DBF00)
-#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000)
-#define MX53_MLB_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000E4000)
-#define MX53_SSI3_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000E8000)
-#define MX53_FEC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000EC000)
-#define MX53_TVE_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000F0000)
-#define MX53_VPU_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000F4000)
-#define MX53_SAHARA_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000F8000)
-#define MX53_PTP_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000FC000)
-
-/*
- * Memory regions and CS
- */
-#define MX53_CSD0_BASE_ADDR             0x70000000
-#define MX53_CSD1_BASE_ADDR             0xB0000000
-#define MX53_CS0_BASE_ADDR              0xF0000000
-#define MX53_CS1_32MB_BASE_ADDR 0xF2000000
-#define MX53_CS1_64MB_BASE_ADDR         0xF4000000
-#define MX53_CS2_64MB_BASE_ADDR         0xF4000000
-#define MX53_CS2_96MB_BASE_ADDR         0xF6000000
-#define MX53_CS3_BASE_ADDR              0xF6000000
-
-#define MX53_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX53_IO_ADDRESS(x)              IOMEM(MX53_IO_P2V(x))
-
-/*
- * defines for SPBA modules
- */
-#define MX53_SPBA_SDHC1 0x04
-#define MX53_SPBA_SDHC2 0x08
-#define MX53_SPBA_UART3 0x0C
-#define MX53_SPBA_CSPI1 0x10
-#define MX53_SPBA_SSI2          0x14
-#define MX53_SPBA_SDHC3 0x20
-#define MX53_SPBA_SDHC4 0x24
-#define MX53_SPBA_SPDIF 0x28
-#define MX53_SPBA_ATA           0x30
-#define MX53_SPBA_SLIM          0x34
-#define MX53_SPBA_HSI2C 0x38
-#define MX53_SPBA_CTRL          0x3C
-
-/*
- * DMA request assignments
- */
-#define MX53_DMA_REQ_SSI3_TX0           47
-#define MX53_DMA_REQ_SSI3_RX0           46
-#define MX53_DMA_REQ_SSI3_TX1           45
-#define MX53_DMA_REQ_SSI3_RX1           44
-#define MX53_DMA_REQ_UART3_TX   43
-#define MX53_DMA_REQ_UART3_RX   42
-#define MX53_DMA_REQ_ESAI_TX            41
-#define MX53_DMA_REQ_ESAI_RX            40
-#define MX53_DMA_REQ_CSPI_TX            39
-#define MX53_DMA_REQ_CSPI_RX            38
-#define MX53_DMA_REQ_ASRC_DMA6  37
-#define MX53_DMA_REQ_ASRC_DMA5  36
-#define MX53_DMA_REQ_ASRC_DMA4  35
-#define MX53_DMA_REQ_ASRC_DMA3  34
-#define MX53_DMA_REQ_ASRC_DMA2  33
-#define MX53_DMA_REQ_ASRC_DMA1  32
-#define MX53_DMA_REQ_EMI_WR             31
-#define MX53_DMA_REQ_EMI_RD             30
-#define MX53_DMA_REQ_SSI1_TX0           29
-#define MX53_DMA_REQ_SSI1_RX0           28
-#define MX53_DMA_REQ_SSI1_TX1           27
-#define MX53_DMA_REQ_SSI1_RX1           26
-#define MX53_DMA_REQ_SSI2_TX0           25
-#define MX53_DMA_REQ_SSI2_RX0           24
-#define MX53_DMA_REQ_SSI2_TX1           23
-#define MX53_DMA_REQ_SSI2_RX1           22
-#define MX53_DMA_REQ_I2C2_SDHC2 21
-#define MX53_DMA_REQ_I2C1_SDHC1 20
-#define MX53_DMA_REQ_UART1_TX   19
-#define MX53_DMA_REQ_UART1_RX   18
-#define MX53_DMA_REQ_UART5_TX   17
-#define MX53_DMA_REQ_UART5_RX   16
-#define MX53_DMA_REQ_SPDIF_TX           15
-#define MX53_DMA_REQ_SPDIF_RX           14
-#define MX53_DMA_REQ_UART2_FIRI_TX      13
-#define MX53_DMA_REQ_UART2_FIRI_RX      12
-#define MX53_DMA_REQ_SDHC4              11
-#define MX53_DMA_REQ_I2C3_SDHC3 10
-#define MX53_DMA_REQ_CSPI2_TX           9
-#define MX53_DMA_REQ_CSPI2_RX           8
-#define MX53_DMA_REQ_CSPI1_TX           7
-#define MX53_DMA_REQ_CSPI1_RX           6
-#define MX53_DMA_REQ_IPU                5
-#define MX53_DMA_REQ_ATA_TX_END 4
-#define MX53_DMA_REQ_ATA_UART4_TX       3
-#define MX53_DMA_REQ_ATA_UART4_RX       2
-#define MX53_DMA_REQ_GPC                1
-#define MX53_DMA_REQ_VPU                0
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX53_INT_RESV0          (NR_IRQS_LEGACY + 0)
-#define MX53_INT_ESDHC1         (NR_IRQS_LEGACY + 1)
-#define MX53_INT_ESDHC2         (NR_IRQS_LEGACY + 2)
-#define MX53_INT_ESDHC3         (NR_IRQS_LEGACY + 3)
-#define MX53_INT_ESDHC4         (NR_IRQS_LEGACY + 4)
-#define MX53_INT_DAP            (NR_IRQS_LEGACY + 5)
-#define MX53_INT_SDMA           (NR_IRQS_LEGACY + 6)
-#define MX53_INT_IOMUX          (NR_IRQS_LEGACY + 7)
-#define MX53_INT_NFC            (NR_IRQS_LEGACY + 8)
-#define MX53_INT_VPU            (NR_IRQS_LEGACY + 9)
-#define MX53_INT_IPU_ERR        (NR_IRQS_LEGACY + 10)
-#define MX53_INT_IPU_SYN        (NR_IRQS_LEGACY + 11)
-#define MX53_INT_GPU            (NR_IRQS_LEGACY + 12)
-#define MX53_INT_UART4          (NR_IRQS_LEGACY + 13)
-#define MX53_INT_USB_H1         (NR_IRQS_LEGACY + 14)
-#define MX53_INT_EMI            (NR_IRQS_LEGACY + 15)
-#define MX53_INT_USB_H2         (NR_IRQS_LEGACY + 16)
-#define MX53_INT_USB_H3         (NR_IRQS_LEGACY + 17)
-#define MX53_INT_USB_OTG        (NR_IRQS_LEGACY + 18)
-#define MX53_INT_SAHARA_H0      (NR_IRQS_LEGACY + 19)
-#define MX53_INT_SAHARA_H1      (NR_IRQS_LEGACY + 20)
-#define MX53_INT_SCC_SMN        (NR_IRQS_LEGACY + 21)
-#define MX53_INT_SCC_STZ        (NR_IRQS_LEGACY + 22)
-#define MX53_INT_SCC_SCM        (NR_IRQS_LEGACY + 23)
-#define MX53_INT_SRTC_NTZ       (NR_IRQS_LEGACY + 24)
-#define MX53_INT_SRTC_TZ        (NR_IRQS_LEGACY + 25)
-#define MX53_INT_RTIC           (NR_IRQS_LEGACY + 26)
-#define MX53_INT_CSU            (NR_IRQS_LEGACY + 27)
-#define MX53_INT_SATA           (NR_IRQS_LEGACY + 28)
-#define MX53_INT_SSI1           (NR_IRQS_LEGACY + 29)
-#define MX53_INT_SSI2           (NR_IRQS_LEGACY + 30)
-#define MX53_INT_UART1          (NR_IRQS_LEGACY + 31)
-#define MX53_INT_UART2          (NR_IRQS_LEGACY + 32)
-#define MX53_INT_UART3          (NR_IRQS_LEGACY + 33)
-#define MX53_INT_RTC            (NR_IRQS_LEGACY + 34)
-#define MX53_INT_PTP            (NR_IRQS_LEGACY + 35)
-#define MX53_INT_ECSPI1         (NR_IRQS_LEGACY + 36)
-#define MX53_INT_ECSPI2         (NR_IRQS_LEGACY + 37)
-#define MX53_INT_CSPI           (NR_IRQS_LEGACY + 38)
-#define MX53_INT_GPT            (NR_IRQS_LEGACY + 39)
-#define MX53_INT_EPIT1          (NR_IRQS_LEGACY + 40)
-#define MX53_INT_EPIT2          (NR_IRQS_LEGACY + 41)
-#define MX53_INT_GPIO1_INT7     (NR_IRQS_LEGACY + 42)
-#define MX53_INT_GPIO1_INT6     (NR_IRQS_LEGACY + 43)
-#define MX53_INT_GPIO1_INT5     (NR_IRQS_LEGACY + 44)
-#define MX53_INT_GPIO1_INT4     (NR_IRQS_LEGACY + 45)
-#define MX53_INT_GPIO1_INT3     (NR_IRQS_LEGACY + 46)
-#define MX53_INT_GPIO1_INT2     (NR_IRQS_LEGACY + 47)
-#define MX53_INT_GPIO1_INT1     (NR_IRQS_LEGACY + 48)
-#define MX53_INT_GPIO1_INT0     (NR_IRQS_LEGACY + 49)
-#define MX53_INT_GPIO1_LOW      (NR_IRQS_LEGACY + 50)
-#define MX53_INT_GPIO1_HIGH     (NR_IRQS_LEGACY + 51)
-#define MX53_INT_GPIO2_LOW      (NR_IRQS_LEGACY + 52)
-#define MX53_INT_GPIO2_HIGH     (NR_IRQS_LEGACY + 53)
-#define MX53_INT_GPIO3_LOW      (NR_IRQS_LEGACY + 54)
-#define MX53_INT_GPIO3_HIGH     (NR_IRQS_LEGACY + 55)
-#define MX53_INT_GPIO4_LOW      (NR_IRQS_LEGACY + 56)
-#define MX53_INT_GPIO4_HIGH     (NR_IRQS_LEGACY + 57)
-#define MX53_INT_WDOG1          (NR_IRQS_LEGACY + 58)
-#define MX53_INT_WDOG2          (NR_IRQS_LEGACY + 59)
-#define MX53_INT_KPP            (NR_IRQS_LEGACY + 60)
-#define MX53_INT_PWM1           (NR_IRQS_LEGACY + 61)
-#define MX53_INT_I2C1           (NR_IRQS_LEGACY + 62)
-#define MX53_INT_I2C2           (NR_IRQS_LEGACY + 63)
-#define MX53_INT_I2C3           (NR_IRQS_LEGACY + 64)
-#define MX53_INT_MLB            (NR_IRQS_LEGACY + 65)
-#define MX53_INT_ASRC           (NR_IRQS_LEGACY + 66)
-#define MX53_INT_SPDIF          (NR_IRQS_LEGACY + 67)
-#define MX53_INT_SIM_DAT        (NR_IRQS_LEGACY + 68)
-#define MX53_INT_IIM            (NR_IRQS_LEGACY + 69)
-#define MX53_INT_ATA            (NR_IRQS_LEGACY + 70)
-#define MX53_INT_CCM1           (NR_IRQS_LEGACY + 71)
-#define MX53_INT_CCM2           (NR_IRQS_LEGACY + 72)
-#define MX53_INT_GPC1           (NR_IRQS_LEGACY + 73)
-#define MX53_INT_GPC2           (NR_IRQS_LEGACY + 74)
-#define MX53_INT_SRC            (NR_IRQS_LEGACY + 75)
-#define MX53_INT_NM             (NR_IRQS_LEGACY + 76)
-#define MX53_INT_PMU            (NR_IRQS_LEGACY + 77)
-#define MX53_INT_CTI_IRQ        (NR_IRQS_LEGACY + 78)
-#define MX53_INT_CTI1_TG0       (NR_IRQS_LEGACY + 79)
-#define MX53_INT_CTI1_TG1       (NR_IRQS_LEGACY + 80)
-#define MX53_INT_ESAI           (NR_IRQS_LEGACY + 81)
-#define MX53_INT_CAN1           (NR_IRQS_LEGACY + 82)
-#define MX53_INT_CAN2           (NR_IRQS_LEGACY + 83)
-#define MX53_INT_GPU2_IRQ       (NR_IRQS_LEGACY + 84)
-#define MX53_INT_GPU2_BUSY      (NR_IRQS_LEGACY + 85)
-#define MX53_INT_UART5          (NR_IRQS_LEGACY + 86)
-#define MX53_INT_FEC            (NR_IRQS_LEGACY + 87)
-#define MX53_INT_OWIRE          (NR_IRQS_LEGACY + 88)
-#define MX53_INT_CTI1_TG2       (NR_IRQS_LEGACY + 89)
-#define MX53_INT_SJC            (NR_IRQS_LEGACY + 90)
-#define MX53_INT_TVE            (NR_IRQS_LEGACY + 92)
-#define MX53_INT_FIRI           (NR_IRQS_LEGACY + 93)
-#define MX53_INT_PWM2           (NR_IRQS_LEGACY + 94)
-#define MX53_INT_SLIM_EXP       (NR_IRQS_LEGACY + 95)
-#define MX53_INT_SSI3           (NR_IRQS_LEGACY + 96)
-#define MX53_INT_EMI_BOOT       (NR_IRQS_LEGACY + 97)
-#define MX53_INT_CTI1_TG3       (NR_IRQS_LEGACY + 98)
-#define MX53_INT_SMC_RX         (NR_IRQS_LEGACY + 99)
-#define MX53_INT_VPU_IDLE       (NR_IRQS_LEGACY + 100)
-#define MX53_INT_EMI_NFC        (NR_IRQS_LEGACY + 101)
-#define MX53_INT_GPU_IDLE       (NR_IRQS_LEGACY + 102)
-#define MX53_INT_GPIO5_LOW      (NR_IRQS_LEGACY + 103)
-#define MX53_INT_GPIO5_HIGH     (NR_IRQS_LEGACY + 104)
-#define MX53_INT_GPIO6_LOW      (NR_IRQS_LEGACY + 105)
-#define MX53_INT_GPIO6_HIGH     (NR_IRQS_LEGACY + 106)
-#define MX53_INT_GPIO7_LOW      (NR_IRQS_LEGACY + 107)
-#define MX53_INT_GPIO7_HIGH     (NR_IRQS_LEGACY + 108)
-
-#endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index 75d6a37e1ae4..a39b69ef4301 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -154,10 +154,17 @@ extern unsigned int __mxc_cpu_type;
 #endif
 
 #ifndef __ASSEMBLY__
+#ifdef CONFIG_SOC_IMX6SL
 static inline bool cpu_is_imx6sl(void)
 {
         return __mxc_cpu_type == MXC_CPU_IMX6SL;
 }
+#else
+static inline bool cpu_is_imx6sl(void)
+{
+        return false;
+}
+#endif
 
 static inline bool cpu_is_imx6dl(void)
 {
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index 58aeaf5baaf6..f1f80ab73e69 100644
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -19,9 +19,26 @@
 
 #include "common.h"
 #include "cpuidle.h"
-#include "crm-regs-imx5.h"
 #include "hardware.h"
 
+#define MXC_CCM_CLPCR                   0x54
+#define MXC_CCM_CLPCR_LPM_OFFSET        0
+#define MXC_CCM_CLPCR_LPM_MASK          0x3
+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
+#define MXC_CCM_CLPCR_VSTBY             (0x1 << 8)
+#define MXC_CCM_CLPCR_SBYOS             (0x1 << 6)
+
+#define MXC_CORTEXA8_PLAT_LPC           0xc
+#define MXC_CORTEXA8_PLAT_LPC_DSM       (1 << 0)
+#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM   (1 << 1)
+
+#define MXC_SRPG_NEON_SRPGCR            0x280
+#define MXC_SRPG_ARM_SRPGCR             0x2a0
+#define MXC_SRPG_EMPGC0_SRPGCR          0x2c0
+#define MXC_SRPG_EMPGC1_SRPGCR          0x2d0
+
+#define MXC_SRPGCR_PCR                  1
+
 /*
  * The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit.
  * This is also the lowest power state possible without affecting
@@ -32,6 +49,30 @@
  */
 #define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF
 
+struct imx5_pm_data {
+        phys_addr_t cortex_addr;
+        phys_addr_t gpc_addr;
+};
+
+static const struct imx5_pm_data imx51_pm_data __initconst = {
+        .cortex_addr = 0x83fa0000,
+        .gpc_addr = 0x73fd8000,
+};
+
+static const struct imx5_pm_data imx53_pm_data __initconst = {
+        .cortex_addr = 0x63fa0000,
+        .gpc_addr = 0x53fd8000,
+};
+
+static void __iomem *ccm_base;
+static void __iomem *cortex_base;
+static void __iomem *gpc_base;
+
+void __init imx5_pm_set_ccm_base(void __iomem *base)
+{
+        ccm_base = base;
+}
+
 /*
  * set cpu low power mode before WFI instruction. This function is called
  * mx5 because it can be used for mx51, and mx53.
@@ -43,12 +84,16 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
         int stop_mode = 0;
 
         /* always allow platform to issue a deep sleep mode request */
-        plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &
+        plat_lpc = __raw_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) &
             ~(MXC_CORTEXA8_PLAT_LPC_DSM);
-        ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
-        arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
-        empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);
-        empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);
+        ccm_clpcr = __raw_readl(ccm_base + MXC_CCM_CLPCR) &
+                    ~(MXC_CCM_CLPCR_LPM_MASK);
+        arm_srpgcr = __raw_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) &
+                     ~(MXC_SRPGCR_PCR);
+        empgc0 = __raw_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) &
+                 ~(MXC_SRPGCR_PCR);
+        empgc1 = __raw_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) &
+                 ~(MXC_SRPGCR_PCR);
 
         switch (mode) {
         case WAIT_CLOCKED:
@@ -82,17 +127,17 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
                 return;
         }
 
-        __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
-        __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
-        __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
-        __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
+        __raw_writel(plat_lpc, cortex_base + MXC_CORTEXA8_PLAT_LPC);
+        __raw_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR);
+        __raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR);
+        __raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR);
 
         if (stop_mode) {
                 empgc0 |= MXC_SRPGCR_PCR;
                 empgc1 |= MXC_SRPGCR_PCR;
 
-                __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR);
-                __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);
+                __raw_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
+                __raw_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
         }
 }
 
@@ -114,8 +159,8 @@ static int mx5_suspend_enter(suspend_state_t state)
                 flush_cache_all();
 
                 /*clear the EMPGC0/1 bits */
-                __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
-                __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
+                __raw_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
+                __raw_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
         }
         cpu_do_idle();
 
@@ -149,7 +194,7 @@ static void imx5_pm_idle(void)
         imx5_cpu_do_idle();
 }
 
-static int __init imx5_pm_common_init(void)
+static int __init imx5_pm_common_init(const struct imx5_pm_data *data)
 {
         int ret;
         struct clk *gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
@@ -163,15 +208,28 @@ static int __init imx5_pm_common_init(void)
 
         arm_pm_idle = imx5_pm_idle;
 
+        cortex_base = ioremap(data->cortex_addr, SZ_16K);
+        gpc_base = ioremap(data->gpc_addr, SZ_16K);
+        WARN_ON(!ccm_base || !cortex_base || !gpc_base);
+
         /* Set the registers to the default cpu idle state. */
         mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);
 
-        return imx5_cpuidle_init();
+        ret = imx5_cpuidle_init();
+        if (ret)
+                pr_warn("%s: cpuidle init failed %d\n", __func__, ret);
+
+        suspend_set_ops(&mx5_suspend_ops);
+
+        return 0;
+}
+
+void __init imx51_pm_init(void)
+{
+        imx5_pm_common_init(&imx51_pm_data);
 }
 
-void __init imx5_pm_init(void)
+void __init imx53_pm_init(void)
 {
-        int ret = imx5_pm_common_init();
-        if (!ret)
-                suspend_set_ops(&mx5_suspend_ops);
+        imx5_pm_common_init(&imx53_pm_data);
 }
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 9392a8f4ef24..5c3af8f993d0 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -129,6 +129,14 @@ static const u32 imx6sl_mmdc_io_offset[] __initconst = {
         0x330, 0x334, 0x320,        /* SDCKE0, SDCKE1, RESET */
 };
 
+static const u32 imx6sx_mmdc_io_offset[] __initconst = {
+        0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
+        0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
+        0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
+        0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
+        0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
+};
+
 static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
         .cpu_type = MXC_CPU_IMX6Q,
         .mmdc_compat = "fsl,imx6q-mmdc",
@@ -159,6 +167,16 @@ static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
         .mmdc_io_offset = imx6sl_mmdc_io_offset,
 };
 
+static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
+        .cpu_type = MXC_CPU_IMX6SX,
+        .mmdc_compat = "fsl,imx6sx-mmdc",
+        .src_compat = "fsl,imx6sx-src",
+        .iomuxc_compat = "fsl,imx6sx-iomuxc",
+        .gpc_compat = "fsl,imx6sx-gpc",
+        .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
+        .mmdc_io_offset = imx6sx_mmdc_io_offset,
+};
+
 /*
  * This structure is for passing necessary data for low level ocram
  * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
@@ -181,11 +199,13 @@ struct imx6_cpu_pm_info {
         u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
 } __aligned(8);
 
-void imx6q_set_int_mem_clk_lpm(void)
+void imx6q_set_int_mem_clk_lpm(bool enable)
 {
         u32 val = readl_relaxed(ccm_base + CGPR);
 
-        val |= BM_CGPR_INT_MEM_CLK_LPM;
+        val &= ~BM_CGPR_INT_MEM_CLK_LPM;
+        if (enable)
+                val |= BM_CGPR_INT_MEM_CLK_LPM;
         writel_relaxed(val, ccm_base + CGPR);
 }
 
@@ -254,6 +274,14 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
                 break;
         case STOP_POWER_ON:
                 val |= 0x2 << BP_CLPCR_LPM;
+                val &= ~BM_CLPCR_VSTBY;
+                val &= ~BM_CLPCR_SBYOS;
+                if (cpu_is_imx6sl())
+                        val |= BM_CLPCR_BYPASS_PMIC_READY;
+                if (cpu_is_imx6sl() || cpu_is_imx6sx())
+                        val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
+                else
+                        val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
                 break;
         case WAIT_UNCLOCKED_POWER_OFF:
                 val |= 0x1 << BP_CLPCR_LPM;
@@ -265,12 +293,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
                 val |= 0x3 << BP_CLPCR_STBY_COUNT;
                 val |= BM_CLPCR_VSTBY;
                 val |= BM_CLPCR_SBYOS;
-                if (cpu_is_imx6sl()) {
+                if (cpu_is_imx6sl())
                         val |= BM_CLPCR_BYPASS_PMIC_READY;
+                if (cpu_is_imx6sl() || cpu_is_imx6sx())
                         val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
-                } else {
+                else
                         val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
-                }
                 break;
         default:
                 return -EINVAL;
@@ -314,8 +342,22 @@ static int imx6q_suspend_finish(unsigned long val)
 static int imx6q_pm_enter(suspend_state_t state)
 {
         switch (state) {
+        case PM_SUSPEND_STANDBY:
+                imx6q_set_lpm(STOP_POWER_ON);
+                imx6q_set_int_mem_clk_lpm(true);
+                imx_gpc_pre_suspend(false);
+                if (cpu_is_imx6sl())
+                        imx6sl_set_wait_clk(true);
+                /* Zzz ... */
+                cpu_do_idle();
+                if (cpu_is_imx6sl())
+                        imx6sl_set_wait_clk(false);
+                imx_gpc_post_resume();
+                imx6q_set_lpm(WAIT_CLOCKED);
+                break;
         case PM_SUSPEND_MEM:
                 imx6q_set_lpm(STOP_POWER_OFF);
+                imx6q_set_int_mem_clk_lpm(false);
                 imx6q_enable_wb(true);
                 /*
                  * For suspend into ocram, asm code already take care of
@@ -323,7 +365,7 @@ static int imx6q_pm_enter(suspend_state_t state)
                  */
                 if (!imx6_suspend_in_ocram_fn)
                         imx6q_enable_rbc(true);
-                imx_gpc_pre_suspend();
+                imx_gpc_pre_suspend(true);
                 imx_anatop_pre_suspend();
                 imx_set_cpu_jump(0, v7_cpu_resume);
                 /* Zzz ... */
@@ -334,6 +376,7 @@ static int imx6q_pm_enter(suspend_state_t state)
                 imx_gpc_post_resume();
                 imx6q_enable_rbc(false);
                 imx6q_enable_wb(false);
+                imx6q_set_int_mem_clk_lpm(true);
                 imx6q_set_lpm(WAIT_CLOCKED);
                 break;
         default:
@@ -343,9 +386,14 @@ static int imx6q_pm_enter(suspend_state_t state)
         return 0;
 }
 
+static int imx6q_pm_valid(suspend_state_t state)
+{
+        return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
+}
+
 static const struct platform_suspend_ops imx6q_pm_ops = {
         .enter = imx6q_pm_enter,
-        .valid = suspend_valid_only_mem,
+        .valid = imx6q_pm_valid,
 };
 
 void __init imx6q_pm_set_ccm_base(void __iomem *base)
@@ -549,3 +597,8 @@ void __init imx6sl_pm_init(void)
 {
         imx6_pm_common_init(&imx6sl_pm_data);
 }
+
+void __init imx6sx_pm_init(void)
+{
+        imx6_pm_common_init(&imx6sx_pm_data);
+}
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 3b0733edb68c..d14c33fd6b03 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -42,7 +42,10 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
 {
         unsigned int wcr_enable;
 
-        if (wdog_clk)
+        if (!wdog_base)
+                goto reset_fallback;
+
+        if (!IS_ERR(wdog_clk))
                 clk_enable(wdog_clk);
 
         if (cpu_is_mx1())
@@ -70,6 +73,7 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
         /* delay to allow the serial port to show the message */
         mdelay(50);
 
+reset_fallback:
         /* we'll take a jump through zero as a poor second */
         soft_restart(0);
 }
@@ -79,13 +83,10 @@ void __init mxc_arch_reset_init(void __iomem *base)
         wdog_base = base;
 
         wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
-        if (IS_ERR(wdog_clk)) {
+        if (IS_ERR(wdog_clk))
                 pr_warn("%s: failed to get wdog clock\n", __func__);
-                wdog_clk = NULL;
-                return;
-        }
-
-        clk_prepare(wdog_clk);
+        else
+                clk_prepare(wdog_clk);
 }
 
 void __init mxc_arch_reset_init_dt(void)
@@ -97,13 +98,10 @@ void __init mxc_arch_reset_init_dt(void)
         WARN_ON(!wdog_base);
 
         wdog_clk = of_clk_get(np, 0);
-        if (IS_ERR(wdog_clk)) {
+        if (IS_ERR(wdog_clk))
                 pr_warn("%s: failed to get wdog clock\n", __func__);
-                wdog_clk = NULL;
-                return;
-        }
-
-        clk_prepare(wdog_clk);
+        else
+                clk_prepare(wdog_clk);
 }
 
 #ifdef CONFIG_CACHE_L2X0
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index bed081e58262..bf92e5a351c0 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -290,25 +290,20 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
         return 0;
 }
 
-void __init mxc_timer_init(void __iomem *base, int irq)
+static void __init _mxc_timer_init(int irq,
+                                   struct clk *clk_per, struct clk *clk_ipg)
 {
         uint32_t tctl_val;
-        struct clk *timer_clk;
-        struct clk *timer_ipg_clk;
 
-        timer_clk = clk_get_sys("imx-gpt.0", "per");
-        if (IS_ERR(timer_clk)) {
+        if (IS_ERR(clk_per)) {
                 pr_err("i.MX timer: unable to get clk\n");
                 return;
         }
 
-        timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
-        if (!IS_ERR(timer_ipg_clk))
-                clk_prepare_enable(timer_ipg_clk);
-
-        clk_prepare_enable(timer_clk);
+        if (!IS_ERR(clk_ipg))
+                clk_prepare_enable(clk_ipg);
 
-        timer_base = base;
+        clk_prepare_enable(clk_per);
 
         /*
          * Initialise to a known state (all timers off, and timing reset)
@@ -325,21 +320,45 @@ void __init mxc_timer_init(void __iomem *base, int irq)
         __raw_writel(tctl_val, timer_base + MXC_TCTL);
 
         /* init and register the timer to the framework */
-        mxc_clocksource_init(timer_clk);
-        mxc_clockevent_init(timer_clk);
+        mxc_clocksource_init(clk_per);
+        mxc_clockevent_init(clk_per);
 
         /* Make irqs happen */
         setup_irq(irq, &mxc_timer_irq);
 }
 
-void __init mxc_timer_init_dt(struct device_node *np)
+void __init mxc_timer_init(void __iomem *base, int irq)
 {
-        void __iomem *base;
+        struct clk *clk_per = clk_get_sys("imx-gpt.0", "per");
+        struct clk *clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
+
+        timer_base = base;
+
+        _mxc_timer_init(irq, clk_per, clk_ipg);
+}
+
+static void __init mxc_timer_init_dt(struct device_node *np)
+{
+        struct clk *clk_per, *clk_ipg;
         int irq;
 
-        base = of_iomap(np, 0);
-        WARN_ON(!base);
+        if (timer_base)
+                return;
+
+        timer_base = of_iomap(np, 0);
+        WARN_ON(!timer_base);
         irq = irq_of_parse_and_map(np, 0);
 
-        mxc_timer_init(base, irq);
+        clk_per = of_clk_get_by_name(np, "per");
+        clk_ipg = of_clk_get_by_name(np, "ipg");
+
+        _mxc_timer_init(irq, clk_per, clk_ipg);
 }
+CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx25_timer, "fsl,imx25-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx50_timer, "fsl,imx50-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx51_timer, "fsl,imx51-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx53_timer, "fsl,imx53-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx6q_timer, "fsl,imx6q-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx6sl_timer, "fsl,imx6sl-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx6sx_timer, "fsl,imx6sx-gpt", mxc_timer_init_dt);
diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c
index 7828af4b2022..1d4f384ca773 100644
--- a/arch/arm/mach-imx/tzic.c
+++ b/arch/arm/mach-imx/tzic.c
@@ -17,6 +17,7 @@
 #include <linux/io.h>
 #include <linux/irqdomain.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <asm/mach/irq.h>
 #include <asm/exception.h>
@@ -153,13 +154,16 @@ static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
  * interrupts. It registers the interrupt enable and disable functions
  * to the kernel for each interrupt source.
  */
-void __init tzic_init_irq(void __iomem *irqbase)
+void __init tzic_init_irq(void)
 {
         struct device_node *np;
         int irq_base;
         int i;
 
-        tzic_base = irqbase;
+        np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
+        tzic_base = of_iomap(np, 0);
+        WARN_ON(!tzic_base);
+
         /* put the TZIC into the reset value with
          * all interrupts disabled
          */
@@ -181,7 +185,6 @@ void __init tzic_init_irq(void __iomem *irqbase)
         irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
         WARN_ON(irq_base < 0);
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
         domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
                                        &irq_domain_simple_ops, NULL);
         WARN_ON(!domain);
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index ba43321001d8..64f8e2564a37 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -28,7 +28,7 @@ config ARCH_CINTEGRATOR
         bool
 
 config INTEGRATOR_IMPD1
-        tristate "Include support for Integrator/IM-PD1"
+        bool "Include support for Integrator/IM-PD1"
         depends on ARCH_INTEGRATOR_AP
         select ARCH_REQUIRE_GPIOLIB
         select ARM_VIC
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index 0e870ea818c4..3ce880729cff 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -308,7 +308,12 @@ static struct impd1_device impd1_devs[] = {
  */
 #define IMPD1_VALID_IRQS 0x00000bffU
 
-static int __init impd1_probe(struct lm_device *dev)
+/*
+ * As this module is bool, it is OK to have this as __init_refok() - no
+ * probe calls will be done after the initial system bootup, as devices
+ * are discovered as part of the machine startup.
+ */
+static int __init_refok impd1_probe(struct lm_device *dev)
 {
         struct impd1_module *impd1;
         int irq_base;
@@ -397,6 +402,11 @@ static void impd1_remove(struct lm_device *dev)
 static struct lm_driver impd1_driver = {
         .drv = {
                 .name   = "impd1",
+                /*
+                 * As we're dropping the probe() function, suppress driver
+                 * binding from sysfs.
+                 */
+                .suppress_bind_attrs = true,
         },
         .probe          = impd1_probe,
         .remove         = impd1_remove,
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index dd0cc677d596..8ca290b479b1 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -31,7 +31,7 @@
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
-#include <linux/irqchip/versatile-fpga.h>
+#include <linux/irqchip.h>
 #include <linux/mtd/physmap.h>
 #include <linux/clk.h>
 #include <linux/platform_data/clk-integrator.h>
@@ -439,15 +439,10 @@ static void __init ap_of_timer_init(void)
         integrator_clockevent_init(rate, base, irq);
 }
 
-static const struct of_device_id fpga_irq_of_match[] __initconst = {
-        { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
-        { /* Sentinel */ }
-};
-
 static void __init ap_init_irq_of(void)
 {
         cm_init();
-        of_irq_init(fpga_irq_of_match);
+        irqchip_init();
 }
 
 /* For the Device Tree, add in the UART callbacks as AUXDATA */
@@ -480,25 +475,18 @@ static const struct of_device_id ebi_match[] = {
 static void __init ap_init_of(void)
 {
         unsigned long sc_dec;
-        struct device_node *root;
         struct device_node *syscon;
         struct device_node *ebi;
         struct device *parent;
         struct soc_device *soc_dev;
         struct soc_device_attribute *soc_dev_attr;
         u32 ap_sc_id;
-        int err;
         int i;
 
-        /* Here we create an SoC device for the root node */
-        root = of_find_node_by_path("/");
-        if (!root)
-                return;
-
-        syscon = of_find_matching_node(root, ap_syscon_match);
+        syscon = of_find_matching_node(NULL, ap_syscon_match);
         if (!syscon)
                 return;
-        ebi = of_find_matching_node(root, ebi_match);
+        ebi = of_find_matching_node(NULL, ebi_match);
         if (!ebi)
                 return;
 
@@ -509,19 +497,17 @@ static void __init ap_init_of(void)
         if (!ebi_base)
                 return;
 
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        ap_auxdata_lookup, NULL);
+
         ap_sc_id = readl(ap_syscon_base);
 
         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
         if (!soc_dev_attr)
                 return;
 
-        err = of_property_read_string(root, "compatible",
-                                      &soc_dev_attr->soc_id);
-        if (err)
-                return;
-        err = of_property_read_string(root, "model", &soc_dev_attr->machine);
-        if (err)
-                return;
+        soc_dev_attr->soc_id = "XVC";
+        soc_dev_attr->machine = "Integrator/AP";
         soc_dev_attr->family = "Integrator";
         soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
                                            'A' + (ap_sc_id & 0x0f));
@@ -536,9 +522,6 @@ static void __init ap_init_of(void)
         parent = soc_device_to_device(soc_dev);
         integrator_init_sysfs(parent, ap_sc_id);
 
-        of_platform_populate(root, of_default_bus_match_table,
-                        ap_auxdata_lookup, parent);
-
         sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
         for (i = 0; i < 4; i++) {
                 struct lm_device *lmdev;
@@ -570,7 +553,6 @@ DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
         .map_io         = ap_map_io,
         .init_early     = ap_init_early,
         .init_irq       = ap_init_irq_of,
-        .handle_irq     = fpga_handle_irq,
         .init_time      = ap_of_timer_init,
         .init_machine   = ap_init_of,
         .restart        = integrator_restart,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index a938242b0c95..5236ebee249c 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -20,7 +20,7 @@
 #include <linux/amba/clcd.h>
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
-#include <linux/irqchip/versatile-fpga.h>
+#include <linux/irqchip.h>
 #include <linux/gfp.h>
 #include <linux/mtd/physmap.h>
 #include <linux/of_irq.h>
@@ -235,15 +235,10 @@ static void __init intcp_init_early(void)
         sched_clock_register(intcp_read_sched_clock, 32, 24000000);
 }
 
-static const struct of_device_id fpga_irq_of_match[] __initconst = {
-        { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
-        { /* Sentinel */ }
-};
-
 static void __init intcp_init_irq_of(void)
 {
         cm_init();
-        of_irq_init(fpga_irq_of_match);
+        irqchip_init();
 }
 
 /*
@@ -279,20 +274,13 @@ static const struct of_device_id intcp_syscon_match[] = {
 
 static void __init intcp_init_of(void)
 {
-        struct device_node *root;
         struct device_node *cpcon;
         struct device *parent;
         struct soc_device *soc_dev;
         struct soc_device_attribute *soc_dev_attr;
         u32 intcp_sc_id;
-        int err;
-
-        /* Here we create an SoC device for the root node */
-        root = of_find_node_by_path("/");
-        if (!root)
-                return;
 
-        cpcon = of_find_matching_node(root, intcp_syscon_match);
+        cpcon = of_find_matching_node(NULL, intcp_syscon_match);
         if (!cpcon)
                 return;
 
@@ -300,19 +288,17 @@ static void __init intcp_init_of(void)
         if (!intcp_con_base)
                 return;
 
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             intcp_auxdata_lookup, NULL);
+
         intcp_sc_id = readl(intcp_con_base);
 
         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
         if (!soc_dev_attr)
                 return;
 
-        err = of_property_read_string(root, "compatible",
-                                      &soc_dev_attr->soc_id);
-        if (err)
-                return;
-        err = of_property_read_string(root, "model", &soc_dev_attr->machine);
-        if (err)
-                return;
+        soc_dev_attr->soc_id = "XCV";
+        soc_dev_attr->machine = "Integrator/CP";
         soc_dev_attr->family = "Integrator";
         soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
                                            'A' + (intcp_sc_id & 0x0f));
@@ -326,8 +312,6 @@ static void __init intcp_init_of(void)
 
         parent = soc_device_to_device(soc_dev);
         integrator_init_sysfs(parent, intcp_sc_id);
-        of_platform_populate(root, of_default_bus_match_table,
-                        intcp_auxdata_lookup, parent);
 }
 
 static const char * intcp_dt_board_compat[] = {
@@ -340,7 +324,6 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
         .map_io         = intcp_map_io,
         .init_early     = intcp_init_early,
         .init_irq       = intcp_init_irq_of,
-        .handle_irq     = fpga_handle_irq,
         .init_machine   = intcp_init_of,
         .restart        = integrator_restart,
         .dt_compat      = intcp_dt_board_compat,
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index f50bc936cb84..98a156afaa94 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -1,6 +1,7 @@
 config ARCH_KEYSTONE
         bool "Texas Instruments Keystone Devices"
         depends on ARCH_MULTI_V7
+        depends on ARM_PATCH_PHYS_VIRT
         select ARM_GIC
         select HAVE_ARM_ARCH_TIMER
         select CLKSRC_MMIO
diff --git a/arch/arm/mach-moxart/Kconfig b/arch/arm/mach-moxart/Kconfig
index 82a4ba8578a2..f49328c39bef 100644
--- a/arch/arm/mach-moxart/Kconfig
+++ b/arch/arm/mach-moxart/Kconfig
@@ -1,4 +1,4 @@
-config ARCH_MOXART
+menuconfig ARCH_MOXART
         bool "MOXA ART SoC" if ARCH_MULTI_V4
         select CPU_FA526
         select ARM_DMA_MEM_BUFFERABLE
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 6090b9eb00c8..955d4a3afabd 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,4 +1,4 @@
-config ARCH_MVEBU
+menuconfig ARCH_MVEBU
         bool "Marvell Engineering Business Unit (MVEBU) SoCs" if (ARCH_MULTI_V7 || ARCH_MULTI_V5)
         select ARCH_SUPPORTS_BIG_ENDIAN
         select CLKSRC_MMIO
@@ -10,15 +10,15 @@ config ARCH_MVEBU
         select ZONE_DMA if ARM_LPAE
         select ARCH_REQUIRE_GPIOLIB
         select PCI_QUIRKS if PCI
+        select OF_ADDRESS_PCI
 
 if ARCH_MVEBU
 
-menu "Marvell EBU SoC variants"
-
 config MACH_MVEBU_V7
         bool
         select ARMADA_370_XP_TIMER
         select CACHE_L2X0
+        select ARM_CPU_SUSPEND
 
 config MACH_ARMADA_370
         bool "Marvell Armada 370 boards" if ARCH_MULTI_V7
@@ -84,7 +84,6 @@ config MACH_DOVE
 
 config MACH_KIRKWOOD
         bool "Marvell Kirkwood boards" if ARCH_MULTI_V5
-        select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
         select CPU_FEROCEON
         select KIRKWOOD_CLK
@@ -97,6 +96,11 @@ config MACH_KIRKWOOD
           Say 'Y' here if you want your kernel to support boards based
           on the Marvell Kirkwood device tree.
 
-endmenu
+config MACH_NETXBIG
+        bool "LaCie 2Big and 5Big Network v2"
+        depends on MACH_KIRKWOOD
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie 2Big and 5Big Network v2
 
 endif
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 2ecb828e4a8b..90bcd5327312 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -9,8 +9,8 @@ obj-y				 += system-controller.o mvebu-soc-id.o
 ifeq ($(CONFIG_MACH_MVEBU_V7),y)
 obj-y                            += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o
 obj-$(CONFIG_SMP)                += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o
-obj-$(CONFIG_HOTPLUG_CPU)        += hotplug.o
 endif
 
 obj-$(CONFIG_MACH_DOVE)          += dove.o
 obj-$(CONFIG_MACH_KIRKWOOD)      += kirkwood.o kirkwood-pm.o
+obj-$(CONFIG_MACH_NETXBIG)       += netxbig.o
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index c3465f5b1250..52c1603a4f92 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -24,4 +24,7 @@ void armada_xp_secondary_startup(void);
 extern struct smp_operations armada_xp_smp_ops;
 #endif
 
+int armada_370_xp_pmsu_idle_enter(unsigned long deepidle);
+void armada_370_xp_pmsu_idle_exit(void);
+
 #endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index 8bb742fdf5ca..a04675e2ec99 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -118,8 +118,16 @@ static void __init thermal_quirk(void)
 {
         struct device_node *np;
         u32 dev, rev;
+        int res;
 
-        if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > ARMADA_375_Z1_REV)
+        /*
+         * The early SoC Z1 revision needs a quirk to be applied in order
+         * for the thermal controller to work properly. This quirk breaks
+         * the thermal support if applied on a SoC that doesn't need it,
+         * so we enforce the SoC revision to be known.
+         */
+        res = mvebu_get_soc_id(&dev, &rev);
+        if (res < 0 || (res == 0 && rev > ARMADA_375_Z1_REV))
                 return;
 
         for_each_compatible_node(np, NULL, "marvell,armada375-thermal") {
@@ -153,7 +161,8 @@ static void __init thermal_quirk(void)
 
                 /*
                  * The thermal controller needs some quirk too, so let's change
-                 * the compatible string to reflect this.
+                 * the compatible string to reflect this and allow the driver
+                 * the take the necessary action.
                  */
                 prop = kzalloc(sizeof(*prop), GFP_KERNEL);
                 prop->name = kstrdup("compatible", GFP_KERNEL);
diff --git a/arch/arm/mach-mvebu/board.h b/arch/arm/mach-mvebu/board.h
index 9c7bb4386f8b..98e32cc2ef3d 100644
--- a/arch/arm/mach-mvebu/board.h
+++ b/arch/arm/mach-mvebu/board.h
@@ -13,4 +13,9 @@
 #ifndef __ARCH_MVEBU_BOARD_H
 #define __ARCH_MVEBU_BOARD_H
 
+#ifdef CONFIG_MACH_NETXBIG
+void netxbig_init(void);
+#else
+static inline void netxbig_init(void) {};
+#endif
 #endif
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index b67fb7a10d8b..a97778e28bf6 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -21,7 +21,6 @@ void mvebu_restart(enum reboot_mode mode, const char *cmd);
 int mvebu_cpu_reset_deassert(int cpu);
 void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr);
 void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr);
-
-void armada_xp_cpu_die(unsigned int cpu);
+int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev);
 
 #endif
diff --git a/arch/arm/mach-mvebu/cpu-reset.c b/arch/arm/mach-mvebu/cpu-reset.c
index 4a8f9eebebea..60fb53787004 100644
--- a/arch/arm/mach-mvebu/cpu-reset.c
+++ b/arch/arm/mach-mvebu/cpu-reset.c
@@ -67,7 +67,7 @@ static int mvebu_cpu_reset_map(struct device_node *np, int res_idx)
         return 0;
 }
 
-int __init mvebu_cpu_reset_init(void)
+static int __init mvebu_cpu_reset_init(void)
 {
         struct device_node *np;
         int res_idx;
diff --git a/arch/arm/mach-mvebu/hotplug.c b/arch/arm/mach-mvebu/hotplug.c
deleted file mode 100644
index d95e91047168..000000000000
--- a/arch/arm/mach-mvebu/hotplug.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Symmetric Multi Processing (SMP) support for Armada XP
- *
- * Copyright (C) 2012 Marvell
- *
- * Lior Amsalem <alior@marvell.com>
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-#include <asm/proc-fns.h>
-#include "common.h"
-
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void __ref armada_xp_cpu_die(unsigned int cpu)
-{
-        cpu_do_idle();
-
-        /* We should never return from idle */
-        panic("mvebu: cpu %d unexpectedly exit from shutdown\n", cpu);
-}
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index 46f105913c84..6b5310828eb2 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -180,6 +180,9 @@ static void __init kirkwood_dt_init(void)
         kirkwood_pm_init();
         kirkwood_dt_eth_fixup();
 
+        if (of_machine_is_compatible("lacie,netxbig"))
+                netxbig_init();
+
         of_platform_populate(NULL, of_default_bus_match_table, auxdata, NULL);
 }
 
diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c
index d0f35b4d4a23..a99434bcee84 100644
--- a/arch/arm/mach-mvebu/mvebu-soc-id.c
+++ b/arch/arm/mach-mvebu/mvebu-soc-id.c
@@ -25,6 +25,7 @@
 #include <linux/of_address.h>
 #include <linux/slab.h>
 #include <linux/sys_soc.h>
+#include "common.h"
 #include "mvebu-soc-id.h"
 
 #define PCIE_DEV_ID_OFF         0x0
@@ -51,10 +52,10 @@ int mvebu_get_soc_id(u32 *dev, u32 *rev)
                 *rev = soc_rev;
                 return 0;
         } else
-                return -1;
+                return -ENODEV;
 }
 
-static int __init mvebu_soc_id_init(void)
+static int __init get_soc_id_by_pci(void)
 {
         struct device_node *np;
         int ret = 0;
@@ -129,6 +130,22 @@ clk_err:
 
         return ret;
 }
+
+static int __init mvebu_soc_id_init(void)
+{
+
+        /*
+         * First try to get the ID and the revision by the system
+         * register and use PCI registers only if it is not possible
+         */
+        if (!mvebu_system_controller_get_soc_id(&soc_dev_id, &soc_rev)) {
+                is_id_valid = true;
+                pr_info("MVEBU SoC ID=0x%X, Rev=0x%X\n", soc_dev_id, soc_rev);
+                return 0;
+        }
+
+        return get_soc_id_by_pci();
+}
 early_initcall(mvebu_soc_id_init);
 
 static int __init mvebu_soc_device(void)
diff --git a/arch/arm/mach-mvebu/netxbig.c b/arch/arm/mach-mvebu/netxbig.c
new file mode 100644
index 000000000000..94b11b6585a4
--- /dev/null
+++ b/arch/arm/mach-mvebu/netxbig.c
@@ -0,0 +1,191 @@
+/*
+ * arch/arm/mach-mvbu/board-netxbig.c
+ *
+ * LaCie 2Big and 5Big Network v2 board setup
+ *
+ * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/leds-kirkwood-netxbig.h>
+#include "common.h"
+
+/*****************************************************************************
+ * GPIO extension LEDs
+ ****************************************************************************/
+
+/*
+ * The LEDs are controlled by a CPLD and can be configured through a GPIO
+ * extension bus:
+ *
+ * - address register : bit [0-2] -> GPIO [47-49]
+ * - data register    : bit [0-2] -> GPIO [44-46]
+ * - enable register  : GPIO 29
+ */
+
+static int netxbig_v2_gpio_ext_addr[] = { 47, 48, 49 };
+static int netxbig_v2_gpio_ext_data[] = { 44, 45, 46 };
+
+static struct netxbig_gpio_ext netxbig_v2_gpio_ext = {
+        .addr           = netxbig_v2_gpio_ext_addr,
+        .num_addr       = ARRAY_SIZE(netxbig_v2_gpio_ext_addr),
+        .data           = netxbig_v2_gpio_ext_data,
+        .num_data       = ARRAY_SIZE(netxbig_v2_gpio_ext_data),
+        .enable         = 29,
+};
+
+/*
+ * Address register selection:
+ *
+ * addr | register
+ * ----------------------------
+ *   0  | front LED
+ *   1  | front LED brightness
+ *   2  | SATA LED brightness
+ *   3  | SATA0 LED
+ *   4  | SATA1 LED
+ *   5  | SATA2 LED
+ *   6  | SATA3 LED
+ *   7  | SATA4 LED
+ *
+ * Data register configuration:
+ *
+ * data | LED brightness
+ * -------------------------------------------------
+ *   0  | min (off)
+ *   -  | -
+ *   7  | max
+ *
+ * data | front LED mode
+ * -------------------------------------------------
+ *   0  | fix off
+ *   1  | fix blue on
+ *   2  | fix red on
+ *   3  | blink blue on=1 sec and blue off=1 sec
+ *   4  | blink red on=1 sec and red off=1 sec
+ *   5  | blink blue on=2.5 sec and red on=0.5 sec
+ *   6  | blink blue on=1 sec and red on=1 sec
+ *   7  | blink blue on=0.5 sec and blue off=2.5 sec
+ *
+ * data | SATA LED mode
+ * -------------------------------------------------
+ *   0  | fix off
+ *   1  | SATA activity blink
+ *   2  | fix red on
+ *   3  | blink blue on=1 sec and blue off=1 sec
+ *   4  | blink red on=1 sec and red off=1 sec
+ *   5  | blink blue on=2.5 sec and red on=0.5 sec
+ *   6  | blink blue on=1 sec and red on=1 sec
+ *   7  | fix blue on
+ */
+
+static int netxbig_v2_red_mled[NETXBIG_LED_MODE_NUM] = {
+        [NETXBIG_LED_OFF]       = 0,
+        [NETXBIG_LED_ON]        = 2,
+        [NETXBIG_LED_SATA]      = NETXBIG_LED_INVALID_MODE,
+        [NETXBIG_LED_TIMER1]    = 4,
+        [NETXBIG_LED_TIMER2]    = NETXBIG_LED_INVALID_MODE,
+};
+
+static int netxbig_v2_blue_pwr_mled[NETXBIG_LED_MODE_NUM] = {
+        [NETXBIG_LED_OFF]       = 0,
+        [NETXBIG_LED_ON]        = 1,
+        [NETXBIG_LED_SATA]      = NETXBIG_LED_INVALID_MODE,
+        [NETXBIG_LED_TIMER1]    = 3,
+        [NETXBIG_LED_TIMER2]    = 7,
+};
+
+static int netxbig_v2_blue_sata_mled[NETXBIG_LED_MODE_NUM] = {
+        [NETXBIG_LED_OFF]       = 0,
+        [NETXBIG_LED_ON]        = 7,
+        [NETXBIG_LED_SATA]      = 1,
+        [NETXBIG_LED_TIMER1]    = 3,
+        [NETXBIG_LED_TIMER2]    = NETXBIG_LED_INVALID_MODE,
+};
+
+static struct netxbig_led_timer netxbig_v2_led_timer[] = {
+        [0] = {
+                .delay_on       = 500,
+                .delay_off      = 500,
+                .mode           = NETXBIG_LED_TIMER1,
+        },
+        [1] = {
+                .delay_on       = 500,
+                .delay_off      = 1000,
+                .mode           = NETXBIG_LED_TIMER2,
+        },
+};
+
+#define NETXBIG_LED(_name, maddr, mval, baddr)                  \
+        { .name         = _name,                                \
+          .mode_addr    = maddr,                                \
+          .mode_val     = mval,                                 \
+          .bright_addr  = baddr }
+
+static struct netxbig_led net2big_v2_leds_ctrl[] = {
+        NETXBIG_LED("net2big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled,  1),
+        NETXBIG_LED("net2big-v2:red:power",  0, netxbig_v2_red_mled,       1),
+        NETXBIG_LED("net2big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net2big-v2:red:sata0",  3, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net2big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net2big-v2:red:sata1",  4, netxbig_v2_red_mled,       2),
+};
+
+static struct netxbig_led_platform_data net2big_v2_leds_data = {
+        .gpio_ext       = &netxbig_v2_gpio_ext,
+        .timer          = netxbig_v2_led_timer,
+        .num_timer      = ARRAY_SIZE(netxbig_v2_led_timer),
+        .leds           = net2big_v2_leds_ctrl,
+        .num_leds       = ARRAY_SIZE(net2big_v2_leds_ctrl),
+};
+
+static struct netxbig_led net5big_v2_leds_ctrl[] = {
+        NETXBIG_LED("net5big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled,  1),
+        NETXBIG_LED("net5big-v2:red:power",  0, netxbig_v2_red_mled,       1),
+        NETXBIG_LED("net5big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata0",  3, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata1",  4, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata2", 5, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata2",  5, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata3", 6, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata3",  6, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata4", 7, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata4",  7, netxbig_v2_red_mled,       2),
+};
+
+static struct netxbig_led_platform_data net5big_v2_leds_data = {
+        .gpio_ext       = &netxbig_v2_gpio_ext,
+        .timer          = netxbig_v2_led_timer,
+        .num_timer      = ARRAY_SIZE(netxbig_v2_led_timer),
+        .leds           = net5big_v2_leds_ctrl,
+        .num_leds       = ARRAY_SIZE(net5big_v2_leds_ctrl),
+};
+
+static struct platform_device netxbig_v2_leds = {
+        .name           = "leds-netxbig",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &net2big_v2_leds_data,
+        },
+};
+
+void __init netxbig_init(void)
+{
+
+        if (of_machine_is_compatible("lacie,net5big_v2"))
+                netxbig_v2_leds.dev.platform_data = &net5big_v2_leds_data;
+        platform_device_register(&netxbig_v2_leds);
+}
diff --git a/arch/arm/mach-mvebu/platsmp-a9.c b/arch/arm/mach-mvebu/platsmp-a9.c
index 96c2c59e34b6..43aaf3fa75ee 100644
--- a/arch/arm/mach-mvebu/platsmp-a9.c
+++ b/arch/arm/mach-mvebu/platsmp-a9.c
@@ -33,7 +33,7 @@
 extern unsigned char armada_375_smp_cpu1_enable_code_end;
 extern unsigned char armada_375_smp_cpu1_enable_code_start;
 
-void armada_375_smp_cpu1_enable_wa(void)
+static void armada_375_smp_cpu1_enable_wa(void)
 {
         void __iomem *sram_virt_base;
 
@@ -91,9 +91,6 @@ static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
 
 static struct smp_operations mvebu_cortex_a9_smp_ops __initdata = {
         .smp_boot_secondary     = mvebu_cortex_a9_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
-        .cpu_die                = armada_xp_cpu_die,
-#endif
 };
 
 CPU_METHOD_OF_DECLARE(mvebu_armada_375_smp, "marvell,armada-375-smp",
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index 88b976b31719..b6fa9f0c98b8 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -78,6 +78,17 @@ static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
         hw_cpu = cpu_logical_map(cpu);
         mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup);
+
+        /*
+         * This is needed to wake up CPUs in the offline state after
+         * using CPU hotplug.
+         */
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+        /*
+         * This is needed to take secondary CPUs out of reset on the
+         * initial boot.
+         */
         ret = mvebu_cpu_reset_deassert(hw_cpu);
         if (ret) {
                 pr_warn("unable to boot CPU: %d\n", ret);
@@ -87,6 +98,19 @@ static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
         return 0;
 }
 
+/*
+ * When a CPU is brought back online, either through CPU hotplug, or
+ * because of the boot of a kexec'ed kernel, the PMSU configuration
+ * for this CPU might be in the deep idle state, preventing this CPU
+ * from receiving interrupts. Here, we therefore take out the current
+ * CPU from this state, which was entered by armada_xp_cpu_die()
+ * below.
+ */
+static void armada_xp_secondary_init(unsigned int cpu)
+{
+        armada_370_xp_pmsu_idle_exit();
+}
+
 static void __init armada_xp_smp_init_cpus(void)
 {
         unsigned int ncores = num_possible_cpus();
@@ -122,12 +146,36 @@ static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
                 panic("The address for the BootROM is incorrect");
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+static void armada_xp_cpu_die(unsigned int cpu)
+{
+        /*
+         * CPU hotplug is implemented by putting offline CPUs into the
+         * deep idle sleep state.
+         */
+        armada_370_xp_pmsu_idle_enter(true);
+}
+
+/*
+ * We need a dummy function, so that platform_can_cpu_hotplug() knows
+ * we support CPU hotplug. However, the function does not need to do
+ * anything, because CPUs going offline can enter the deep idle state
+ * by themselves, without any help from a still alive CPU.
+ */
+static int armada_xp_cpu_kill(unsigned int cpu)
+{
+        return 1;
+}
+#endif
+
 struct smp_operations armada_xp_smp_ops __initdata = {
         .smp_init_cpus          = armada_xp_smp_init_cpus,
         .smp_prepare_cpus       = armada_xp_smp_prepare_cpus,
         .smp_boot_secondary     = armada_xp_boot_secondary,
+        .smp_secondary_init     = armada_xp_secondary_init,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_die                = armada_xp_cpu_die,
+        .cpu_kill               = armada_xp_cpu_kill,
 #endif
 };
 
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 53a55c8520bf..9c819d65b337 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -148,13 +148,13 @@ static void armada_370_xp_cpu_resume(void)
 }
 
 /* No locking is needed because we only access per-CPU registers */
-void armada_370_xp_pmsu_idle_prepare(bool deepidle)
+int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
 {
         unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
         u32 reg;
 
         if (pmsu_mp_base == NULL)
-                return;
+                return -EINVAL;
 
         /*
          * Adjust the PMSU configuration to wait for WFI signal, enable
@@ -183,11 +183,6 @@ void armada_370_xp_pmsu_idle_prepare(bool deepidle)
         reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
         reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
         writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
-}
-
-static noinline int do_armada_370_xp_cpu_suspend(unsigned long deepidle)
-{
-        armada_370_xp_pmsu_idle_prepare(deepidle);
 
         v7_exit_coherency_flush(all);
 
@@ -220,11 +215,11 @@ static noinline int do_armada_370_xp_cpu_suspend(unsigned long deepidle)
 
 static int armada_370_xp_cpu_suspend(unsigned long deepidle)
 {
-        return cpu_suspend(deepidle, do_armada_370_xp_cpu_suspend);
+        return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter);
 }
 
 /* No locking is needed because we only access per-CPU registers */
-static noinline void armada_370_xp_pmsu_idle_restore(void)
+void armada_370_xp_pmsu_idle_exit(void)
 {
         unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
         u32 reg;
@@ -253,7 +248,7 @@ static int armada_370_xp_cpu_pm_notify(struct notifier_block *self,
                 unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
                 mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume);
         } else if (action == CPU_PM_EXIT) {
-                armada_370_xp_pmsu_idle_restore();
+                armada_370_xp_pmsu_idle_exit();
         }
 
         return NOTIFY_OK;
@@ -263,7 +258,7 @@ static struct notifier_block armada_370_xp_cpu_pm_notifier = {
         .notifier_call = armada_370_xp_cpu_pm_notify,
 };
 
-int __init armada_370_xp_cpu_pm_init(void)
+static int __init armada_370_xp_cpu_pm_init(void)
 {
         struct device_node *np;
 
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index 0c5524ac75b7..b2b4e3d6558c 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -39,6 +39,9 @@ struct mvebu_system_controller {
         u32 system_soft_reset;
 
         u32 resume_boot_addr;
+
+        u32 dev_id;
+        u32 rev_id;
 };
 static struct mvebu_system_controller *mvebu_sc;
 
@@ -47,6 +50,8 @@ static const struct mvebu_system_controller armada_370_xp_system_controller = {
         .system_soft_reset_offset = 0x64,
         .rstoutn_mask_reset_out_en = 0x1,
         .system_soft_reset = 0x1,
+        .dev_id = 0x38,
+        .rev_id = 0x3c,
 };
 
 static const struct mvebu_system_controller armada_375_system_controller = {
@@ -55,6 +60,8 @@ static const struct mvebu_system_controller armada_375_system_controller = {
         .rstoutn_mask_reset_out_en = 0x1,
         .system_soft_reset = 0x1,
         .resume_boot_addr = 0xd4,
+        .dev_id = 0x38,
+        .rev_id = 0x3c,
 };
 
 static const struct mvebu_system_controller orion_system_controller = {
@@ -101,6 +108,18 @@ void mvebu_restart(enum reboot_mode mode, const char *cmd)
                 ;
 }
 
+int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev)
+{
+        if (of_machine_is_compatible("marvell,armada380") &&
+                system_controller_base) {
+                *dev = readl(system_controller_base + mvebu_sc->dev_id) >> 16;
+                *rev = (readl(system_controller_base + mvebu_sc->rev_id) >> 8)
+                        & 0xF;
+                return 0;
+        } else
+                return -ENODEV;
+}
+
 #ifdef CONFIG_SMP
 void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr)
 {
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 486d301f43fd..3c61096c8627 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -1,4 +1,4 @@
-config ARCH_NOMADIK
+menuconfig ARCH_NOMADIK
         bool "ST-Ericsson Nomadik"
         depends on ARCH_MULTI_V5
         select ARCH_REQUIRE_GPIOLIB
@@ -15,7 +15,6 @@ config ARCH_NOMADIK
           Support for the Nomadik platform by ST-Ericsson
 
 if ARCH_NOMADIK
-menu "Nomadik boards"
 
 config MACH_NOMADIK_8815NHK
         bool "ST 8815 Nomadik Hardware Kit (evaluation board)"
@@ -24,7 +23,6 @@ config MACH_NOMADIK_8815NHK
         select I2C_ALGOBIT
         select I2C_NOMADIK
 
-endmenu
 endif
 
 config NOMADIK_8815
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 0ba482638ebf..1c1ed737f7ab 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -1,3 +1,6 @@
+menu "TI OMAP/AM/DM/DRA Family"
+        depends on ARCH_MULTI_V6 || ARCH_MULTI_V7
+
 config ARCH_OMAP
         bool
 
@@ -28,12 +31,11 @@ config ARCH_OMAP4
         select ARM_CPU_SUSPEND if PM
         select ARM_ERRATA_720789
         select ARM_GIC
-        select CACHE_L2X0
         select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
         select OMAP_INTERCONNECT
-        select PL310_ERRATA_588369
-        select PL310_ERRATA_727915
+        select PL310_ERRATA_588369 if CACHE_L2X0
+        select PL310_ERRATA_727915 if CACHE_L2X0
         select PM_OPP if PM
         select PM_RUNTIME if CPU_IDLE
         select ARM_ERRATA_754322
@@ -80,7 +82,6 @@ config SOC_DRA7XX
 config ARCH_OMAP2PLUS
         bool
         select ARCH_HAS_BANDGAP
-        select ARCH_HAS_CPUFREQ
         select ARCH_HAS_HOLES_MEMORYMODEL
         select ARCH_OMAP
         select ARCH_REQUIRE_GPIOLIB
@@ -343,3 +344,5 @@ config OMAP4_ERRATA_I688
 endmenu
 
 endif
+
+endmenu
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index ff029737c8f0..a373d508799a 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -91,7 +91,14 @@ extern void omap3_sync32k_timer_init(void);
 extern void omap3_secure_sync32k_timer_init(void);
 extern void omap3_gptimer_timer_init(void);
 extern void omap4_local_timer_init(void);
+#ifdef CONFIG_CACHE_L2X0
 int omap_l2_cache_init(void);
+#else
+static inline int omap_l2_cache_init(void)
+{
+        return 0;
+}
+#endif
 extern void omap5_realtime_timer_init(void);
 
 void omap2420_init_early(void);
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
index e4e505f52ba0..042f693ef423 100644
--- a/arch/arm/mach-prima2/Kconfig
+++ b/arch/arm/mach-prima2/Kconfig
@@ -1,4 +1,4 @@
-config ARCH_SIRF
+menuconfig ARCH_SIRF
         bool "CSR SiRF" if ARCH_MULTI_V7
         select ARCH_HAS_RESET_CONTROLLER
         select ARCH_REQUIRE_GPIOLIB
@@ -11,7 +11,7 @@ config ARCH_SIRF
 
 if ARCH_SIRF
 
-menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
+comment "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
 
 config ARCH_ATLAS6
         bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
@@ -37,8 +37,6 @@ config ARCH_MARCO
         help
           Support for CSR SiRFSoC ARM Cortex A9 Platform
 
-endmenu
-
 config SIRF_IRQ
         bool
 
diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig
index fd2b99dceb89..ee5697ba05bc 100644
--- a/arch/arm/mach-qcom/Kconfig
+++ b/arch/arm/mach-qcom/Kconfig
@@ -1,4 +1,4 @@
-config ARCH_QCOM
+menuconfig ARCH_QCOM
         bool "Qualcomm Support" if ARCH_MULTI_V7
         select ARCH_REQUIRE_GPIOLIB
         select ARM_GIC
@@ -11,8 +11,6 @@ config ARCH_QCOM
 
 if ARCH_QCOM
 
-menu "Qualcomm SoC Selection"
-
 config ARCH_MSM8X60
         bool "Enable support for MSM8X60"
         select CLKSRC_QCOM
@@ -25,8 +23,6 @@ config ARCH_MSM8974
         bool "Enable support for MSM8974"
         select HAVE_ARM_ARCH_TIMER
 
-endmenu
-
 config QCOM_SCM
         bool
 
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 04284de7aca5..ad5316ae524e 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -117,7 +117,7 @@ config S3C24XX_SETUP_TS
           Compile in platform device definition for Samsung TouchScreen.
 
 config S3C24XX_DMA
-        bool "S3C2410 DMA support"
+        bool "S3C2410 DMA support (deprecated)"
         select S3C_DMA
         help
           S3C2410 DMA support. This is needed for drivers like sound which
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 3136d86b0d6e..26ca2427e53d 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -18,9 +18,9 @@ config CPU_S3C6410
           Enable S3C6410 CPU support
 
 config S3C64XX_PL080
-        bool "S3C64XX DMA using generic PL08x driver"
+        def_bool DMADEVICES
+        select ARM_AMBA
         select AMBA_PL08X
-        select SAMSUNG_DMADEV
 
 config S3C64XX_SETUP_SDHCI
         bool
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index bb2111b3751e..26003e23796d 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -9,16 +9,18 @@ if ARCH_S5P64X0
 
 config CPU_S5P6440
         bool
+        select ARM_AMBA
+        select PL330_DMA if DMADEVICES
         select S5P_SLEEP if PM
-        select SAMSUNG_DMADEV
         select SAMSUNG_WAKEMASK if PM
         help
           Enable S5P6440 CPU support
 
 config CPU_S5P6450
         bool
+        select ARM_AMBA
+        select PL330_DMA if DMADEVICES
         select S5P_SLEEP if PM
-        select SAMSUNG_DMADEV
         select SAMSUNG_WAKEMASK if PM
         help
           Enable S5P6450 CPU support
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 15170be97a74..c5e3a969b063 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -9,8 +9,9 @@ if ARCH_S5PC100
 
 config CPU_S5PC100
         bool
+        select ARM_AMBA
+        select PL330_DMA if DMADEVICES
         select S5P_EXT_INT
-        select SAMSUNG_DMADEV
         help
           Enable S5PC100 CPU support
 
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 8c3abe521757..f60f2862856d 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -11,10 +11,11 @@ if ARCH_S5PV210
 
 config CPU_S5PV210
         bool
+        select ARM_AMBA
+        select PL330_DMA if DMADEVICES
         select S5P_EXT_INT
         select S5P_PM if PM
         select S5P_SLEEP if PM
-        select SAMSUNG_DMADEV
         help
           Enable S5PV210 CPU support
 
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index f9874ba60cc8..108939f8d053 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -329,6 +329,11 @@ static struct mtd_partition collie_partitions[] = {
                 .name           = "rootfs",
                 .offset         = MTDPART_OFS_APPEND,
                 .size           = 0x00e20000,
+        }, {
+                .name           = "bootblock",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 0x00020000,
+                .mask_flags     = MTD_WRITEABLE
         }
 };
 
@@ -356,7 +361,7 @@ static void collie_flash_exit(void)
 }
 
 static struct flash_platform_data collie_flash_data = {
-        .map_name       = "jedec_probe",
+        .map_name       = "cfi_probe",
         .init           = collie_flash_init,
         .set_vpp        = collie_set_vpp,
         .exit           = collie_flash_exit,
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index dbd954e61aa7..4508643cca32 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -1,7 +1,7 @@
 config ARCH_SHMOBILE
         bool
 
-config ARCH_SHMOBILE_MULTI
+menuconfig ARCH_SHMOBILE_MULTI
         bool "Renesas ARM SoCs" if ARCH_MULTI_V7
         depends on MMU
         select ARCH_SHMOBILE
@@ -12,10 +12,11 @@ config ARCH_SHMOBILE_MULTI
         select NO_IOPORT_MAP
         select PINCTRL
         select ARCH_REQUIRE_GPIOLIB
+        select ARCH_HAS_OPP
 
 if ARCH_SHMOBILE_MULTI
 
-comment "Renesas ARM SoCs System Type"
+#comment "Renesas ARM SoCs System Type"
 
 config ARCH_EMEV2
         bool "Emma Mobile EV2"
@@ -25,6 +26,11 @@ config ARCH_R7S72100
         bool "RZ/A1H (R7S72100)"
         select SYS_SUPPORTS_SH_MTU2
 
+config ARCH_R8A7779
+        bool "R-Car H1 (R8A77790)"
+        select RENESAS_INTC_IRQPIN
+        select SYS_SUPPORTS_SH_TMU
+
 config ARCH_R8A7790
         bool "R-Car H2 (R8A77900)"
         select RENESAS_IRQC
@@ -51,6 +57,11 @@ config MACH_LAGER
         depends on ARCH_R8A7790
         select MICREL_PHY if SH_ETH
 
+config MACH_MARZEN
+        bool "MARZEN board"
+        depends on ARCH_R8A7779
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
+
 comment "Renesas ARM SoCs System Configuration"
 endif
 
@@ -85,7 +96,6 @@ config ARCH_R8A73A4
         select CPU_V7
         select SH_CLK_CPG
         select RENESAS_IRQC
-        select ARCH_HAS_CPUFREQ
         select ARCH_HAS_OPP
         select SYS_SUPPORTS_SH_CMT
         select SYS_SUPPORTS_SH_TMU
@@ -235,19 +245,6 @@ config MACH_MARZEN
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
         select USE_OF
 
-config MACH_MARZEN_REFERENCE
-        bool "MARZEN board - Reference Device Tree Implementation"
-        depends on ARCH_R8A7779
-        select ARCH_REQUIRE_GPIOLIB
-        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-        select USE_OF
-        ---help---
-           Use reference implementation of Marzen board support
-           which makes use of device tree at the expense
-           of not supporting a number of devices.
-
-           This is intended to aid developers
-
 config MACH_LAGER
         bool "Lager board"
         depends on ARCH_R8A7790
@@ -264,7 +261,6 @@ config MACH_KOELSCH
 config MACH_KZM9G
         bool "KZM-A9-GT board"
         depends on ARCH_SH73A0
-        select ARCH_HAS_CPUFREQ
         select ARCH_HAS_OPP
         select ARCH_REQUIRE_GPIOLIB
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 38d5fe825e93..fe3878a1a69a 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -34,31 +34,39 @@ obj-$(CONFIG_ARCH_R8A7791)	+= clock-r8a7791.o
 obj-$(CONFIG_ARCH_R7S72100)     += clock-r7s72100.o
 endif
 
+# CPU reset vector handling objects
+cpu-y                           := platsmp.o headsmp.o
+cpu-$(CONFIG_ARCH_R8A7790)      += platsmp-apmu.o
+cpu-$(CONFIG_ARCH_R8A7791)      += platsmp-apmu.o
+
 # SMP objects
-smp-y                           := platsmp.o headsmp.o
+smp-y                           := $(cpu-y)
 smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o headsmp-scu.o platsmp-scu.o
 smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o headsmp-scu.o platsmp-scu.o
-smp-$(CONFIG_ARCH_R8A7790)      += smp-r8a7790.o platsmp-apmu.o
-smp-$(CONFIG_ARCH_R8A7791)      += smp-r8a7791.o platsmp-apmu.o
+smp-$(CONFIG_ARCH_R8A7790)      += smp-r8a7790.o
+smp-$(CONFIG_ARCH_R8A7791)      += smp-r8a7791.o
 smp-$(CONFIG_ARCH_EMEV2)        += smp-emev2.o headsmp-scu.o platsmp-scu.o
 
-# IRQ objects
-obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
-
 # PM objects
 obj-$(CONFIG_SUSPEND)           += suspend.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
+obj-$(CONFIG_CPU_FREQ)          += cpufreq.o
 obj-$(CONFIG_ARCH_SH7372)       += pm-sh7372.o sleep-sh7372.o pm-rmobile.o
 obj-$(CONFIG_ARCH_SH73A0)       += pm-sh73a0.o
 obj-$(CONFIG_ARCH_R8A7740)      += pm-r8a7740.o pm-rmobile.o
 obj-$(CONFIG_ARCH_R8A7779)      += pm-r8a7779.o pm-rcar.o
-obj-$(CONFIG_ARCH_R8A7790)      += pm-r8a7790.o pm-rcar.o
+obj-$(CONFIG_ARCH_R8A7790)      += pm-r8a7790.o pm-rcar.o $(cpu-y)
+obj-$(CONFIG_ARCH_R8A7791)      += pm-r8a7791.o pm-rcar.o $(cpu-y)
+
+# IRQ objects
+obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
 
 # Board objects
 ifdef CONFIG_ARCH_SHMOBILE_MULTI
 obj-$(CONFIG_MACH_GENMAI)       += board-genmai-reference.o
 obj-$(CONFIG_MACH_KOELSCH)      += board-koelsch-reference.o
 obj-$(CONFIG_MACH_LAGER)        += board-lager-reference.o
+obj-$(CONFIG_MACH_MARZEN)       += board-marzen-reference.o
 else
 obj-$(CONFIG_MACH_APE6EVM)      += board-ape6evm.o
 obj-$(CONFIG_MACH_APE6EVM_REFERENCE)    += board-ape6evm-reference.o
@@ -67,7 +75,6 @@ obj-$(CONFIG_MACH_BOCKW)	+= board-bockw.o
 obj-$(CONFIG_MACH_BOCKW_REFERENCE)      += board-bockw-reference.o
 obj-$(CONFIG_MACH_GENMAI)       += board-genmai.o
 obj-$(CONFIG_MACH_MARZEN)       += board-marzen.o
-obj-$(CONFIG_MACH_MARZEN_REFERENCE)     += board-marzen-reference.o
 obj-$(CONFIG_MACH_LAGER)        += board-lager.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA)      += board-armadillo800eva.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE)    += board-armadillo800eva-reference.o
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 918fccffa1b6..ebf97d4bcfd8 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -13,7 +13,6 @@ loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
 loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
 loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
 loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
-loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000
 
 __ZRELADDR      := $(sort $(loadaddr-y))
    zreladdr-y   += $(__ZRELADDR)
diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c
index 3276afcf3cc9..2f7723e5fe91 100644
--- a/arch/arm/mach-shmobile/board-ape6evm-reference.c
+++ b/arch/arm/mach-shmobile/board-ape6evm-reference.c
@@ -24,11 +24,13 @@
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
 #include <linux/sh_clk.h>
-#include <mach/common.h>
-#include <mach/r8a73a4.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "r8a73a4.h"
+
 static void __init ape6evm_add_standard_devices(void)
 {
 
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index fe071a9130b7..485567876d39 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -33,12 +33,14 @@
 #include <linux/regulator/machine.h>
 #include <linux/sh_clk.h>
 #include <linux/smsc911x.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/r8a73a4.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "r8a73a4.h"
+
 /* LEDS */
 static struct gpio_led ape6evm_leds[] = {
         {
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
index f660fbb96e0b..208576667b22 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
@@ -24,11 +24,13 @@
 #include <linux/kernel.h>
 #include <linux/gpio.h>
 #include <linux/io.h>
-#include <mach/common.h>
-#include <mach/r8a7740.h>
+
 #include <asm/mach/arch.h>
 #include <asm/hardware/cache-l2x0.h>
 
+#include "common.h"
+#include "r8a7740.h"
+
 /*
  * CON1         Camera Module
  * CON2         Extension Bus
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 30fcac73a540..32339cf6ee7b 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -45,9 +45,7 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/i2c-gpio.h>
 #include <linux/reboot.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/r8a7740.h>
+
 #include <media/mt9t112.h>
 #include <media/sh_mobile_ceu.h>
 #include <media/soc_camera.h>
@@ -62,6 +60,10 @@
 #include <sound/sh_fsi.h>
 #include <sound/simple_card.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "pm-rmobile.h"
+#include "r8a7740.h"
 #include "sh-gpio.h"
 
 /*
diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c
index 027373f8de82..ba840cd333b9 100644
--- a/arch/arm/mach-shmobile/board-bockw-reference.c
+++ b/arch/arm/mach-shmobile/board-bockw-reference.c
@@ -19,10 +19,12 @@
  */
 
 #include <linux/of_platform.h>
-#include <mach/common.h>
-#include <mach/r8a7778.h>
+
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "r8a7778.h"
+
 /*
  *      see board-bock.c for checking detail of dip-switch
  */
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index f444be2f241e..b4e4789017bc 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -34,14 +34,16 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/usb/renesas_usbhs.h>
+
 #include <media/soc_camera.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/r8a7778.h>
 #include <asm/mach/arch.h>
 #include <sound/rcar_snd.h>
 #include <sound/simple_card.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "r8a7778.h"
+
 #define FPGA    0x18200000
 #define IRQ0MR  0x30
 #define COMCTLR 0x101c
diff --git a/arch/arm/mach-shmobile/board-genmai-reference.c b/arch/arm/mach-shmobile/board-genmai-reference.c
index 2ff6ad6e608e..e5448f7b868a 100644
--- a/arch/arm/mach-shmobile/board-genmai-reference.c
+++ b/arch/arm/mach-shmobile/board-genmai-reference.c
@@ -20,12 +20,14 @@
 
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/r7s72100.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "clock.h"
+#include "common.h"
+#include "r7s72100.h"
+
 /*
  * This is a really crude hack to provide clkdev support to platform
  * devices until they get moved to DT.
@@ -47,7 +49,7 @@ static const char * const genmai_boards_compat_dt[] __initconst = {
 };
 
 DT_MACHINE_START(GENMAI_DT, "genmai")
-        .init_early     = r7s72100_init_early,
+        .init_early     = shmobile_init_delay,
         .init_machine   = genmai_add_standard_devices,
         .dt_compat      = genmai_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-genmai.c b/arch/arm/mach-shmobile/board-genmai.c
index c94201ee8596..e2a3ba4871c3 100644
--- a/arch/arm/mach-shmobile/board-genmai.c
+++ b/arch/arm/mach-shmobile/board-genmai.c
@@ -25,12 +25,14 @@
 #include <linux/sh_eth.h>
 #include <linux/spi/rspi.h>
 #include <linux/spi/spi.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/r7s72100.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "r7s72100.h"
+
 /* Ether */
 static const struct sh_eth_plat_data ether_pdata __initconst = {
         .phy                    = 0x00, /* PD60610 */
@@ -154,7 +156,7 @@ static const char * const genmai_boards_compat_dt[] __initconst = {
 };
 
 DT_MACHINE_START(GENMAI_DT, "genmai")
-        .init_early     = r7s72100_init_early,
+        .init_early     = shmobile_init_delay,
         .init_machine   = genmai_add_standard_devices,
         .dt_compat      = genmai_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c
index d322a162b4b0..0b1fb2345aa1 100644
--- a/arch/arm/mach-shmobile/board-koelsch-reference.c
+++ b/arch/arm/mach-shmobile/board-koelsch-reference.c
@@ -23,13 +23,15 @@
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/rcar-du.h>
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/rcar-gen2.h>
-#include <mach/r8a7791.h>
+
 #include <asm/mach/arch.h>
 
+#include "clock.h"
+#include "common.h"
+#include "irqs.h"
+#include "r8a7791.h"
+#include "rcar-gen2.h"
+
 /* DU */
 static struct rcar_du_encoder_data koelsch_du_encoders[] = {
         {
diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
index c6c68892caa3..e698b90ae761 100644
--- a/arch/arm/mach-shmobile/board-koelsch.c
+++ b/arch/arm/mach-shmobile/board-koelsch.c
@@ -45,13 +45,15 @@
 #include <linux/spi/flash.h>
 #include <linux/spi/rspi.h>
 #include <linux/spi/spi.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/r8a7791.h>
-#include <mach/rcar-gen2.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "r8a7791.h"
+#include "rcar-gen2.h"
+
 /* DU */
 static struct rcar_du_encoder_data koelsch_du_encoders[] = {
         {
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index a735a1d80c28..5d2621f202d1 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -25,12 +25,14 @@
 #include <linux/irq.h>
 #include <linux/input.h>
 #include <linux/of_platform.h>
-#include <mach/sh73a0.h>
-#include <mach/common.h>
+
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "sh73a0.h"
+
 static void __init kzm_init(void)
 {
         sh73a0_add_standard_devices_dt();
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index f94ec8ca42c1..1320e9d063b1 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -41,16 +41,18 @@
 #include <linux/usb/r8a66597.h>
 #include <linux/usb/renesas_usbhs.h>
 #include <linux/videodev2.h>
+
 #include <sound/sh_fsi.h>
 #include <sound/simple_card.h>
-#include <mach/irqs.h>
-#include <mach/sh73a0.h>
-#include <mach/common.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <video/sh_mobile_lcdc.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "sh73a0.h"
+
 /*
  * external GPIO
  */
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
index 749832e3f33c..8dcff51a8f45 100644
--- a/arch/arm/mach-shmobile/board-lager-reference.c
+++ b/arch/arm/mach-shmobile/board-lager-reference.c
@@ -22,13 +22,15 @@
 #include <linux/init.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/rcar-du.h>
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/rcar-gen2.h>
-#include <mach/r8a7790.h>
+
 #include <asm/mach/arch.h>
 
+#include "clock.h"
+#include "common.h"
+#include "irqs.h"
+#include "r8a7790.h"
+#include "rcar-gen2.h"
+
 /* DU */
 static struct rcar_du_encoder_data lager_du_encoders[] = {
         {
@@ -129,7 +131,7 @@ static const char *lager_boards_compat_dt[] __initdata = {
 
 DT_MACHINE_START(LAGER_DT, "lager")
         .smp            = smp_ops(r8a7790_smp_ops),
-        .init_early     = r8a7790_init_early,
+        .init_early     = shmobile_init_delay,
         .init_time      = rcar_gen2_timer_init,
         .init_machine   = lager_add_standard_devices,
         .init_late      = shmobile_init_late,
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index f8b1e05463cc..bfd9e4846fc9 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -31,6 +31,8 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/mtd.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_data/camera-rcar.h>
 #include <linux/platform_data/gpio-rcar.h>
@@ -43,22 +45,23 @@
 #include <linux/regulator/gpio-regulator.h>
 #include <linux/regulator/machine.h>
 #include <linux/sh_eth.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/rspi.h>
+#include <linux/spi/spi.h>
 #include <linux/usb/phy.h>
 #include <linux/usb/renesas_usbhs.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/r8a7790.h>
+
 #include <media/soc_camera.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/mtd.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/rspi.h>
-#include <linux/spi/spi.h>
 #include <sound/rcar_snd.h>
 #include <sound/simple_card.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "r8a7790.h"
+#include "rcar-gen2.h"
+
 /*
  * SSI-AK4643
  *
@@ -886,7 +889,7 @@ static const char * const lager_boards_compat_dt[] __initconst = {
 
 DT_MACHINE_START(LAGER_DT, "lager")
         .smp            = smp_ops(r8a7790_smp_ops),
-        .init_early     = r8a7790_init_early,
+        .init_early     = shmobile_init_delay,
         .init_time      = rcar_gen2_timer_init,
         .init_machine   = lager_init,
         .init_late      = shmobile_init_late,
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 0ff4d8e45cf7..304b76f3bf4a 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -47,10 +47,11 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
-#include <linux/sh_intc.h>
+#include <linux/sh_clk.h>
 #include <linux/tca6416_keypad.h>
 #include <linux/usb/renesas_usbhs.h>
 #include <linux/dma-mapping.h>
+
 #include <video/sh_mobile_hdmi.h>
 #include <video/sh_mobile_lcdc.h>
 #include <media/sh_mobile_ceu.h>
@@ -58,15 +59,14 @@
 #include <media/soc_camera_platform.h>
 #include <sound/sh_fsi.h>
 #include <sound/simple_card.h>
-
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/sh7372.h>
-
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "pm-rmobile.h"
 #include "sh-gpio.h"
+#include "sh7372.h"
 
 /*
  * Address      Interface               BusWidth        note
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 2773936bf7dc..21b3e1ca2261 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,19 +19,42 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#include <mach/r8a7779.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
+#include <linux/clk/shmobile.h>
+#include <linux/clocksource.h>
+#include <linux/of_platform.h>
+
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 
+#include "clock.h"
+#include "common.h"
+#include "irqs.h"
+#include "r8a7779.h"
+
+static void __init marzen_init_timer(void)
+{
+        r8a7779_clocks_init(r8a7779_read_mode_pins());
+        clocksource_of_init();
+}
+
+/*
+ * This is a really crude hack to provide clkdev support to platform
+ * devices until they get moved to DT.
+ */
+static const struct clk_name clk_names[] __initconst = {
+        { "tmu0", "fck", "sh-tmu.0" },
+};
+
 static void __init marzen_init(void)
 {
+        shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
         r8a7779_add_standard_devices_dt();
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
         r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
 }
 
 static const char *marzen_boards_compat_dt[] __initdata = {
+        "renesas,marzen",
         "renesas,marzen-reference",
         NULL,
 };
@@ -39,7 +62,8 @@ static const char *marzen_boards_compat_dt[] __initdata = {
 DT_MACHINE_START(MARZEN, "marzen")
         .smp            = smp_ops(r8a7779_smp_ops),
         .map_io         = r8a7779_map_io,
-        .init_early     = r8a7779_init_delay,
+        .init_early     = shmobile_init_delay,
+        .init_time      = marzen_init_timer,
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = r8a7779_init_irq_dt,
         .init_machine   = marzen_init,
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index d832a4477b4b..25a1037e289d 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -41,14 +41,16 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
+
 #include <media/soc_camera.h>
-#include <mach/r8a7779.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/traps.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "r8a7779.h"
+
 /* Fixed 3.3V regulator to be used by SDHI0 */
 static struct regulator_consumer_supply fixed3v3_power_consumers[] = {
         REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
index df187484de5d..3eb2ec401e0c 100644
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ b/arch/arm/mach-shmobile/clock-r7s72100.c
@@ -19,8 +19,9 @@
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
-#include <mach/common.h>
-#include <mach/r7s72100.h>
+
+#include "common.h"
+#include "r7s72100.h"
 
 /* Frequency Control Registers */
 #define FRQCR           0xfcfe0010
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index b5bc22c6a858..49d139748aa6 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -22,8 +22,8 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
-#include <mach/common.h>
+#include "common.h"
+#include "clock.h"
 
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x270
@@ -574,11 +574,17 @@ static struct clk_lookup lookups[] = {
 
         /* MSTP */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
+        CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
+        CLKDEV_DEV_ID("e6c50000.serial", &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
+        CLKDEV_DEV_ID("e6c20000.serial", &mstp_clks[MSTP206]),
         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
+        CLKDEV_DEV_ID("e6c30000.serial", &mstp_clks[MSTP207]),
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
+        CLKDEV_DEV_ID("e6ce0000.serial", &mstp_clks[MSTP216]),
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
+        CLKDEV_DEV_ID("e6cf0000.serial", &mstp_clks[MSTP217]),
         CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
         CLKDEV_DEV_ID("e6700020.dma-controller", &mstp_clks[MSTP218]),
         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 50931e3c97c7..a60c324df64e 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -22,9 +22,10 @@
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/r8a7740.h>
+
+#include "clock.h"
+#include "common.h"
+#include "r8a7740.h"
 
 /*
  *        |  MDx  |  XTAL1/EXTAL1   |  System   | EXTALR |
@@ -555,27 +556,27 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_ceu.1",        &mstp_clks[MSTP128]),
 
         CLKDEV_DEV_ID("sh-sci.4",               &mstp_clks[MSTP200]),
-        CLKDEV_DEV_ID("e6c80000.sci",           &mstp_clks[MSTP200]),
+        CLKDEV_DEV_ID("e6c80000.serial",        &mstp_clks[MSTP200]),
         CLKDEV_DEV_ID("sh-sci.3",               &mstp_clks[MSTP201]),
-        CLKDEV_DEV_ID("e6c70000.sci",           &mstp_clks[MSTP201]),
+        CLKDEV_DEV_ID("e6c70000.serial",        &mstp_clks[MSTP201]),
         CLKDEV_DEV_ID("sh-sci.2",               &mstp_clks[MSTP202]),
-        CLKDEV_DEV_ID("e6c60000.sci",           &mstp_clks[MSTP202]),
+        CLKDEV_DEV_ID("e6c60000.serial",        &mstp_clks[MSTP202]),
         CLKDEV_DEV_ID("sh-sci.1",               &mstp_clks[MSTP203]),
-        CLKDEV_DEV_ID("e6c50000.sci",           &mstp_clks[MSTP203]),
+        CLKDEV_DEV_ID("e6c50000.serial",        &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.0",               &mstp_clks[MSTP204]),
-        CLKDEV_DEV_ID("e6c40000.sci",           &mstp_clks[MSTP204]),
+        CLKDEV_DEV_ID("e6c40000.serial",        &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.8",               &mstp_clks[MSTP206]),
-        CLKDEV_DEV_ID("e6c30000.sci",           &mstp_clks[MSTP206]),
+        CLKDEV_DEV_ID("e6c30000.serial",        &mstp_clks[MSTP206]),
         CLKDEV_DEV_ID("sh-sci.5",               &mstp_clks[MSTP207]),
-        CLKDEV_DEV_ID("e6cb0000.sci",           &mstp_clks[MSTP207]),
+        CLKDEV_DEV_ID("e6cb0000.serial",        &mstp_clks[MSTP207]),
         CLKDEV_DEV_ID("sh-dma-engine.3",        &mstp_clks[MSTP214]),
         CLKDEV_DEV_ID("sh-dma-engine.2",        &mstp_clks[MSTP216]),
         CLKDEV_DEV_ID("sh-dma-engine.1",        &mstp_clks[MSTP217]),
         CLKDEV_DEV_ID("sh-dma-engine.0",        &mstp_clks[MSTP218]),
         CLKDEV_DEV_ID("sh-sci.7",               &mstp_clks[MSTP222]),
-        CLKDEV_DEV_ID("e6cd0000.sci",           &mstp_clks[MSTP222]),
+        CLKDEV_DEV_ID("e6cd0000.serial",        &mstp_clks[MSTP222]),
         CLKDEV_DEV_ID("sh-sci.6",               &mstp_clks[MSTP230]),
-        CLKDEV_DEV_ID("e6cc0000.sci",           &mstp_clks[MSTP230]),
+        CLKDEV_DEV_ID("e6cc0000.serial",        &mstp_clks[MSTP230]),
 
         CLKDEV_DEV_ID("sh_fsi2",                &mstp_clks[MSTP328]),
         CLKDEV_DEV_ID("fe1f0000.sound",         &mstp_clks[MSTP328]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index 13f8f3ab8840..95579073cfce 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -39,8 +39,8 @@
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
-#include <mach/common.h>
+#include "clock.h"
+#include "common.h"
 
 #define MSTPCR0         IOMEM(0xffc80030)
 #define MSTPCR1         IOMEM(0xffc80034)
@@ -202,11 +202,17 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
         CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
+        CLKDEV_DEV_ID("ffe40000.serial", &mstp_clks[MSTP026]), /* SCIF0 */
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
+        CLKDEV_DEV_ID("ffe41000.serial", &mstp_clks[MSTP025]), /* SCIF1 */
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
+        CLKDEV_DEV_ID("ffe42000.serial", &mstp_clks[MSTP024]), /* SCIF2 */
         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
+        CLKDEV_DEV_ID("ffe43000.serial", &mstp_clks[MSTP023]), /* SCIF3 */
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
+        CLKDEV_DEV_ID("ffe44000.serial", &mstp_clks[MSTP022]), /* SCIF4 */
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
+        CLKDEV_DEV_ID("ffe45000.serial", &mstp_clks[MSTP021]), /* SCIF5 */
         CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
         CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
         CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index a13298bd37a8..c51f9db3f66f 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -23,8 +23,11 @@
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
-#include <mach/common.h>
+#include <linux/sh_timer.h>
+
+#include "clock.h"
+#include "common.h"
+#include "r8a7779.h"
 
 /*
  *              MD1 = 1                 MD1 = 0
@@ -52,9 +55,6 @@
 #define MSTPCR3         IOMEM(0xffc8003c)
 #define MSTPSR1         IOMEM(0xffc80044)
 
-#define MODEMR          0xffcc0020
-
-
 /* ioremap() through clock mapping mandatory to avoid
  * collision with ARM coherent DMA virtual memory range.
  */
@@ -207,14 +207,9 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a7779_clock_init(void)
 {
-        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
-        u32 mode;
+        u32 mode = r8a7779_read_mode_pins();
         int k, ret = 0;
 
-        BUG_ON(!modemr);
-        mode = ioread32(modemr);
-        iounmap(modemr);
-
         if (mode & MD(1)) {
                 plla_clk.rate = 1500000000;
 
@@ -268,3 +263,13 @@ void __init r8a7779_clock_init(void)
         else
                 panic("failed to setup r8a7779 clocks\n");
 }
+
+/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
+void __init __weak r8a7779_register_twd(void) { }
+
+void __init r8a7779_earlytimer_init(void)
+{
+        r8a7779_clock_init();
+        r8a7779_register_twd();
+        shmobile_earlytimer_init();
+}
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 296a057109e4..17435c1aa2fe 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -22,9 +22,11 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/r8a7790.h>
+
+#include "clock.h"
+#include "common.h"
+#include "r8a7790.h"
+#include "rcar-gen2.h"
 
 /*
  *   MD         EXTAL           PLL0    PLL1    PLL3
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index e2fdfcc14436..10e193d707f5 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -23,9 +23,9 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/rcar-gen2.h>
+#include "clock.h"
+#include "common.h"
+#include "rcar-gen2.h"
 
 /*
  *   MD         EXTAL           PLL0    PLL1    PLL3
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index d16d9ca7f79e..7071676145c4 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -21,8 +21,8 @@
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
-#include <mach/common.h>
+#include "clock.h"
+#include "common.h"
 
 /* SH7372 registers */
 #define FRQCRA          IOMEM(0xe6150000)
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 0d9cd1fe0212..9433a4e2c88e 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -22,8 +22,8 @@
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
 #include <asm/processor.h>
-#include <mach/clock.h>
-#include <mach/common.h>
+#include "clock.h"
+#include "common.h"
 
 #define FRQCRA          IOMEM(0xe6150000)
 #define FRQCRB          IOMEM(0xe6150004)
@@ -638,16 +638,25 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("e6820000.i2c", &mstp_clks[MSTP116]), /* I2C0 */
         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
+        CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP219]), /* SCIFA7 */
         CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* SY-DMAC */
         CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* MP-DMAC */
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
+        CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), /* SCIFA5 */
         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
+        CLKDEV_DEV_ID("0xe6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
+        CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), /* SCIFA0 */
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
+        CLKDEV_DEV_ID("e6c50000.serial", &mstp_clks[MSTP203]), /* SCIFA1 */
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
+        CLKDEV_DEV_ID("e6c60000.serial", &mstp_clks[MSTP202]), /* SCIFA2 */
         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
+        CLKDEV_DEV_ID("e6c70000.serial", &mstp_clks[MSTP201]), /* SCIFA3 */
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
+        CLKDEV_DEV_ID("e6c80000.serial", &mstp_clks[MSTP200]), /* SCIFA4 */
         CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
+        CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP331]), /* SCIFA6 */
         CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
         CLKDEV_DEV_ID("ec230000.sound", &mstp_clks[MSTP328]), /* FSI */
         CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
index e7232a0373b9..806f94038cc4 100644
--- a/arch/arm/mach-shmobile/clock.c
+++ b/arch/arm/mach-shmobile/clock.c
@@ -25,7 +25,7 @@
 #ifdef CONFIG_COMMON_CLK
 #include <linux/clk.h>
 #include <linux/clkdev.h>
-#include <mach/clock.h>
+#include "clock.h"
 
 void __init shmobile_clk_workaround(const struct clk_name *clks,
                                     int nr_clks, bool enable)
@@ -49,8 +49,8 @@ void __init shmobile_clk_workaround(const struct clk_name *clks,
 #else /* CONFIG_COMMON_CLK */
 #include <linux/sh_clk.h>
 #include <linux/export.h>
-#include <mach/clock.h>
-#include <mach/common.h>
+#include "clock.h"
+#include "common.h"
 
 unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk)
 {
diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/clock.h
index 31b6417463e6..31b6417463e6 100644
--- a/arch/arm/mach-shmobile/include/mach/clock.h
+++ b/arch/arm/mach-shmobile/clock.h
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/common.h
index f7a360edcc35..98056081f0da 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -35,8 +35,10 @@ extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
 
 #ifdef CONFIG_SUSPEND
 int shmobile_suspend_init(void);
+void shmobile_smp_apmu_suspend_init(void);
 #else
 static inline int shmobile_suspend_init(void) { return 0; }
+static inline void shmobile_smp_apmu_suspend_init(void) { }
 #endif
 
 #ifdef CONFIG_CPU_IDLE
@@ -45,12 +47,19 @@ int shmobile_cpuidle_init(void);
 static inline int shmobile_cpuidle_init(void) { return 0; }
 #endif
 
+#ifdef CONFIG_CPU_FREQ
+int shmobile_cpufreq_init(void);
+#else
+static inline int shmobile_cpufreq_init(void) { return 0; }
+#endif
+
 extern void __iomem *shmobile_scu_base;
 
 static inline void __init shmobile_init_late(void)
 {
         shmobile_suspend_init();
         shmobile_cpuidle_init();
+        shmobile_cpufreq_init();
 }
 
 #endif /* __ARCH_MACH_COMMON_H */
diff --git a/arch/arm/mach-shmobile/console.c b/arch/arm/mach-shmobile/console.c
index 9411a5bf4fd6..f2e79f2376e1 100644
--- a/arch/arm/mach-shmobile/console.c
+++ b/arch/arm/mach-shmobile/console.c
@@ -19,8 +19,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <mach/common.h>
 #include <asm/mach/map.h>
+#include "common.h"
 
 void __init shmobile_setup_console(void)
 {
diff --git a/arch/arm/mach-shmobile/cpufreq.c b/arch/arm/mach-shmobile/cpufreq.c
new file mode 100644
index 000000000000..8a24b2be46ae
--- /dev/null
+++ b/arch/arm/mach-shmobile/cpufreq.c
@@ -0,0 +1,17 @@
+/*
+ * CPUFreq support code for SH-Mobile ARM
+ *
+ *  Copyright (C) 2014 Gaku Inami
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/platform_device.h>
+
+int __init shmobile_cpufreq_init(void)
+{
+        platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0);
+        return 0;
+}
diff --git a/arch/arm/mach-shmobile/include/mach/dma-register.h b/arch/arm/mach-shmobile/dma-register.h
index 97c40bd9b94f..97c40bd9b94f 100644
--- a/arch/arm/mach-shmobile/include/mach/dma-register.h
+++ b/arch/arm/mach-shmobile/dma-register.h
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index e5be5c88644b..faf82144a262 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -10,14 +10,17 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <linux/linkage.h>
 #include <linux/init.h>
+#include <linux/linkage.h>
+#include <linux/threads.h>
 #include <asm/memory.h>
 
+#ifdef CONFIG_SMP
 ENTRY(shmobile_invalidate_start)
         bl      v7_invalidate_l1
         b       secondary_startup
 ENDPROC(shmobile_invalidate_start)
+#endif
 
 /*
  * Reset vector for secondary CPUs.
@@ -68,7 +71,7 @@ shmobile_smp_boot_find_mpidr:
 
 shmobile_smp_boot_next:
         add     r1, r1, #1
-        cmp     r1, #CONFIG_NR_CPUS
+        cmp     r1, #NR_CPUS
         blo     shmobile_smp_boot_find_mpidr
 
         b       shmobile_smp_sleep
@@ -85,10 +88,10 @@ ENDPROC(shmobile_smp_sleep)
 
         .globl  shmobile_smp_mpidr
 shmobile_smp_mpidr:
-1:      .space  CONFIG_NR_CPUS * 4
+1:      .space  NR_CPUS * 4
         .globl  shmobile_smp_fn
 shmobile_smp_fn:
-2:      .space  CONFIG_NR_CPUS * 4
+2:      .space  NR_CPUS * 4
         .globl  shmobile_smp_arg
 shmobile_smp_arg:
-3:      .space  CONFIG_NR_CPUS * 4
+3:      .space  NR_CPUS * 4
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index d241bfd6926d..5aee83f079e2 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -1,24 +1,10 @@
 #ifndef __ASM_MACH_IRQS_H
 #define __ASM_MACH_IRQS_H
 
-#include <linux/sh_intc.h>
-
-/* GIC */
-#define gic_spi(nr)             ((nr) + 32)
-#define gic_iid(nr)             (nr) /* ICCIAR / interrupt ID */
-
-/* INTCS */
-#define INTCS_VECT_BASE         0x3400
-#define INTCS_VECT(n, vect)     INTC_VECT((n), INTCS_VECT_BASE + (vect))
-#define intcs_evt2irq(evt)      evt2irq(INTCS_VECT_BASE + (evt))
+/* Stuck here until drivers/pinctl/sh-pfc gets rid of legacy code */
 
 /* External IRQ pins */
 #define IRQPIN_BASE             2000
 #define irq_pin(nr)             ((nr) + IRQPIN_BASE)
 
-/* GPIO IRQ */
-#define _GPIO_IRQ_BASE          2500
-#define GPIO_IRQ_BASE(x)        (_GPIO_IRQ_BASE + (32 * x))
-#define GPIO_IRQ(x, y)          (_GPIO_IRQ_BASE + (32 * x) + y)
-
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index a91caad7db7c..e2af00b1bd9d 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -22,11 +22,10 @@
 #include <linux/module.h>
 #include <linux/irq.h>
 #include <linux/io.h>
-#include <linux/sh_intc.h>
-#include <mach/intc.h>
-#include <mach/irqs.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include "intc.h"
+#include "irqs.h"
 
 enum {
         UNUSED_INTCA = 0,
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 19a26f4579b3..44457a94897b 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -22,15 +22,16 @@
 #include <linux/module.h>
 #include <linux/irq.h>
 #include <linux/io.h>
-#include <linux/sh_intc.h>
 #include <linux/irqchip.h>
 #include <linux/irqchip/arm-gic.h>
-#include <mach/intc.h>
-#include <mach/irqs.h>
-#include <mach/sh73a0.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "intc.h"
+#include "irqs.h"
+#include "sh73a0.h"
+
 enum {
         UNUSED = 0,
 
diff --git a/arch/arm/mach-shmobile/include/mach/intc.h b/arch/arm/mach-shmobile/intc.h
index a5603c76cfe0..a5603c76cfe0 100644
--- a/arch/arm/mach-shmobile/include/mach/intc.h
+++ b/arch/arm/mach-shmobile/intc.h
diff --git a/arch/arm/mach-shmobile/irqs.h b/arch/arm/mach-shmobile/irqs.h
new file mode 100644
index 000000000000..4ff2d2aa94f0
--- /dev/null
+++ b/arch/arm/mach-shmobile/irqs.h
@@ -0,0 +1,21 @@
+#ifndef __SHMOBILE_IRQS_H
+#define __SHMOBILE_IRQS_H
+
+#include <linux/sh_intc.h>
+#include <mach/irqs.h>
+
+/* GIC */
+#define gic_spi(nr)             ((nr) + 32)
+#define gic_iid(nr)             (nr) /* ICCIAR / interrupt ID */
+
+/* INTCS */
+#define INTCS_VECT_BASE         0x3400
+#define INTCS_VECT(n, vect)     INTC_VECT((n), INTCS_VECT_BASE + (vect))
+#define intcs_evt2irq(evt)      evt2irq(INTCS_VECT_BASE + (evt))
+
+/* GPIO IRQ */
+#define _GPIO_IRQ_BASE          2500
+#define GPIO_IRQ_BASE(x)        (_GPIO_IRQ_BASE + (32 * x))
+#define GPIO_IRQ(x, y)          (_GPIO_IRQ_BASE + (32 * x) + y)
+
+#endif /* __SHMOBILE_IRQS_H */
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index 8cb641c00fdb..2c06810d3a70 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -7,27 +7,32 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/cpu_pm.h>
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/ioport.h>
 #include <linux/of_address.h>
 #include <linux/smp.h>
+#include <linux/suspend.h>
+#include <linux/threads.h>
 #include <asm/cacheflush.h>
 #include <asm/cp15.h>
+#include <asm/proc-fns.h>
 #include <asm/smp_plat.h>
-#include <mach/common.h>
+#include <asm/suspend.h>
+#include "common.h"
 
 static struct {
         void __iomem *iomem;
         int bit;
-} apmu_cpus[CONFIG_NR_CPUS];
+} apmu_cpus[NR_CPUS];
 
 #define WUPCR_OFFS 0x10
 #define PSTR_OFFS 0x40
 #define CPUNCR_OFFS(n) (0x100 + (0x10 * (n)))
 
-static int apmu_power_on(void __iomem *p, int bit)
+static int __maybe_unused apmu_power_on(void __iomem *p, int bit)
 {
         /* request power on */
         writel_relaxed(BIT(bit), p + WUPCR_OFFS);
@@ -46,7 +51,7 @@ static int apmu_power_off(void __iomem *p, int bit)
         return 0;
 }
 
-static int apmu_power_off_poll(void __iomem *p, int bit)
+static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit)
 {
         int k;
 
@@ -69,7 +74,7 @@ static int apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu))
 
 static void apmu_init_cpu(struct resource *res, int cpu, int bit)
 {
-        if (apmu_cpus[cpu].iomem)
+        if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem)
                 return;
 
         apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res));
@@ -133,6 +138,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus)
         apmu_parse_cfg(apmu_init_cpu);
 }
 
+#ifdef CONFIG_SMP
 int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         /* For this particular CPU register boot vector */
@@ -140,8 +146,9 @@ int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
         return apmu_wrap(cpu, apmu_power_on);
 }
+#endif
 
-#ifdef CONFIG_HOTPLUG_CPU
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_SUSPEND)
 /* nicked from arch/arm/mach-exynos/hotplug.c */
 static inline void cpu_enter_lowpower_a15(void)
 {
@@ -172,16 +179,40 @@ static inline void cpu_enter_lowpower_a15(void)
         dsb();
 }
 
-void shmobile_smp_apmu_cpu_die(unsigned int cpu)
+void shmobile_smp_apmu_cpu_shutdown(unsigned int cpu)
 {
-        /* For this particular CPU deregister boot vector */
-        shmobile_smp_hook(cpu, 0, 0);
 
         /* Select next sleep mode using the APMU */
         apmu_wrap(cpu, apmu_power_off);
 
         /* Do ARM specific CPU shutdown */
         cpu_enter_lowpower_a15();
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+        unsigned int v;
+
+        asm volatile("mrc    p15, 0, %0, c1, c0, 0\n"
+                     "       orr     %0, %0, %1\n"
+                     "       mcr     p15, 0, %0, c1, c0, 0\n"
+                     "       mrc     p15, 0, %0, c1, c0, 1\n"
+                     "       orr     %0, %0, %2\n"
+                     "       mcr     p15, 0, %0, c1, c0, 1\n"
+                     : "=&r" (v)
+                     : "Ir" (CR_C), "Ir" (0x40)
+                     : "cc");
+}
+#endif
+
+#if defined(CONFIG_HOTPLUG_CPU)
+void shmobile_smp_apmu_cpu_die(unsigned int cpu)
+{
+        /* For this particular CPU deregister boot vector */
+        shmobile_smp_hook(cpu, 0, 0);
+
+        /* Shutdown CPU core */
+        shmobile_smp_apmu_cpu_shutdown(cpu);
 
         /* jump to shared mach-shmobile sleep / reset code */
         shmobile_smp_sleep();
@@ -192,3 +223,25 @@ int shmobile_smp_apmu_cpu_kill(unsigned int cpu)
         return apmu_wrap(cpu, apmu_power_off_poll);
 }
 #endif
+
+#if defined(CONFIG_SUSPEND)
+static int shmobile_smp_apmu_do_suspend(unsigned long cpu)
+{
+        shmobile_smp_hook(cpu, virt_to_phys(cpu_resume), 0);
+        shmobile_smp_apmu_cpu_shutdown(cpu);
+        cpu_do_idle(); /* WFI selects Core Standby */
+        return 1;
+}
+
+static int shmobile_smp_apmu_enter_suspend(suspend_state_t state)
+{
+        cpu_suspend(smp_processor_id(), shmobile_smp_apmu_do_suspend);
+        cpu_leave_lowpower();
+        return 0;
+}
+
+void __init shmobile_smp_apmu_suspend_init(void)
+{
+        shmobile_suspend_ops.enter = shmobile_smp_apmu_enter_suspend;
+}
+#endif
diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c
index 673ad6e80869..64663110ab6c 100644
--- a/arch/arm/mach-shmobile/platsmp-scu.c
+++ b/arch/arm/mach-shmobile/platsmp-scu.c
@@ -15,7 +15,7 @@
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
-#include <mach/common.h>
+#include "common.h"
 
 static int shmobile_smp_scu_notifier_call(struct notifier_block *nfb,
                                           unsigned long action, void *hcpu)
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index 9ebc246b8d7d..3923e09e966d 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -13,7 +13,7 @@
 #include <linux/init.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
-#include <mach/common.h>
+#include "common.h"
 
 extern unsigned long shmobile_smp_fn[];
 extern unsigned long shmobile_smp_arg[];
diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c
index 40b87aa1d448..a0d44d537fa0 100644
--- a/arch/arm/mach-shmobile/pm-r8a7740.c
+++ b/arch/arm/mach-shmobile/pm-r8a7740.c
@@ -10,8 +10,8 @@
  */
 #include <linux/console.h>
 #include <linux/suspend.h>
-#include <mach/pm-rmobile.h>
-#include <mach/common.h>
+#include "common.h"
+#include "pm-rmobile.h"
 
 #ifdef CONFIG_PM
 static int r8a7740_pd_a4s_suspend(void)
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c
index d6fe189b2df6..69f70b7f7fb2 100644
--- a/arch/arm/mach-shmobile/pm-r8a7779.c
+++ b/arch/arm/mach-shmobile/pm-r8a7779.c
@@ -13,20 +13,33 @@
 #include <linux/suspend.h>
 #include <linux/err.h>
 #include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/console.h>
+
 #include <asm/io.h>
-#include <mach/common.h>
-#include <mach/pm-rcar.h>
-#include <mach/r8a7779.h>
+
+#include "common.h"
+#include "pm-rcar.h"
+#include "r8a7779.h"
 
 /* SYSC */
 #define SYSCIER 0x0c
 #define SYSCIMR 0x10
 
+struct r8a7779_pm_domain {
+        struct generic_pm_domain genpd;
+        struct rcar_sysc_ch ch;
+};
+
+static inline struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d)
+{
+        return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
+}
+
 #if defined(CONFIG_PM) || defined(CONFIG_SMP)
 
 static void __init r8a7779_sysc_init(void)
diff --git a/arch/arm/mach-shmobile/pm-r8a7790.c b/arch/arm/mach-shmobile/pm-r8a7790.c
index fc82839e2c2a..80e8d95e54d3 100644
--- a/arch/arm/mach-shmobile/pm-r8a7790.c
+++ b/arch/arm/mach-shmobile/pm-r8a7790.c
@@ -11,9 +11,21 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/smp.h>
 #include <asm/io.h>
-#include <mach/pm-rcar.h>
-#include <mach/r8a7790.h>
+#include "common.h"
+#include "pm-rcar.h"
+#include "r8a7790.h"
+
+/* RST */
+#define RST             0xe6160000
+#define CA15BAR         0x0020
+#define CA7BAR          0x0030
+#define CA15RESCNT      0x0040
+#define CA7RESCNT       0x0044
+
+/* On-chip RAM */
+#define MERAM          0xe8080000
 
 /* SYSC */
 #define SYSCIER 0x0c
@@ -38,8 +50,33 @@ static inline void r8a7790_sysc_init(void) {}
 
 void __init r8a7790_pm_init(void)
 {
+        void __iomem *p;
+        u32 bar;
         static int once;
 
-        if (!once++)
-                r8a7790_sysc_init();
+        if (once++)
+                return;
+
+        /* MERAM for jump stub, because BAR requires 256KB aligned address */
+        p = ioremap_nocache(MERAM, shmobile_boot_size);
+        memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
+        iounmap(p);
+
+        /* setup reset vectors */
+        p = ioremap_nocache(RST, 0x63);
+        bar = (MERAM >> 8) & 0xfffffc00;
+        writel_relaxed(bar, p + CA15BAR);
+        writel_relaxed(bar, p + CA7BAR);
+        writel_relaxed(bar | 0x10, p + CA15BAR);
+        writel_relaxed(bar | 0x10, p + CA7BAR);
+
+        /* de-assert reset for all CPUs */
+        writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000,
+                       p + CA15RESCNT);
+        writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | 0x5a5a0000,
+                       p + CA7RESCNT);
+        iounmap(p);
+
+        r8a7790_sysc_init();
+        shmobile_smp_apmu_suspend_init();
 }
diff --git a/arch/arm/mach-shmobile/pm-r8a7791.c b/arch/arm/mach-shmobile/pm-r8a7791.c
new file mode 100644
index 000000000000..25f107bb3657
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-r8a7791.c
@@ -0,0 +1,73 @@
+/*
+ * r8a7791 Power management support
+ *
+ * Copyright (C) 2014  Renesas Electronics Corporation
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/smp.h>
+#include <asm/io.h>
+#include "common.h"
+#include "pm-rcar.h"
+#include "r8a7791.h"
+
+#define RST             0xe6160000
+#define CA15BAR         0x0020
+#define CA15RESCNT      0x0040
+#define RAM             0xe6300000
+
+/* SYSC */
+#define SYSCIER 0x0c
+#define SYSCIMR 0x10
+
+#if defined(CONFIG_SMP)
+
+static void __init r8a7791_sysc_init(void)
+{
+        void __iomem *base = rcar_sysc_init(0xe6180000);
+
+        /* enable all interrupt sources, but do not use interrupt handler */
+        iowrite32(0x0131000e, base + SYSCIER);
+        iowrite32(0, base + SYSCIMR);
+}
+
+#else /* CONFIG_SMP */
+
+static inline void r8a7791_sysc_init(void) {}
+
+#endif /* CONFIG_SMP */
+
+void __init r8a7791_pm_init(void)
+{
+        void __iomem *p;
+        u32 bar;
+        static int once;
+
+        if (once++)
+                return;
+
+        /* RAM for jump stub, because BAR requires 256KB aligned address */
+        p = ioremap_nocache(RAM, shmobile_boot_size);
+        memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
+        iounmap(p);
+
+        /* setup reset vectors */
+        p = ioremap_nocache(RST, 0x63);
+        bar = (RAM >> 8) & 0xfffffc00;
+        writel_relaxed(bar, p + CA15BAR);
+        writel_relaxed(bar | 0x10, p + CA15BAR);
+
+        /* enable clocks to all CPUs */
+        writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000,
+                       p + CA15RESCNT);
+        iounmap(p);
+
+        r8a7791_sysc_init();
+        shmobile_smp_apmu_suspend_init();
+}
diff --git a/arch/arm/mach-shmobile/pm-rcar.c b/arch/arm/mach-shmobile/pm-rcar.c
index 1f465a12d1b1..34b8a5674f85 100644
--- a/arch/arm/mach-shmobile/pm-rcar.c
+++ b/arch/arm/mach-shmobile/pm-rcar.c
@@ -13,7 +13,7 @@
 #include <linux/mm.h>
 #include <linux/spinlock.h>
 #include <asm/io.h>
-#include <mach/pm-rcar.h>
+#include "pm-rcar.h"
 
 /* SYSC */
 #define SYSCSR 0x00
diff --git a/arch/arm/mach-shmobile/include/mach/pm-rcar.h b/arch/arm/mach-shmobile/pm-rcar.h
index ef3a1ef628f1..ef3a1ef628f1 100644
--- a/arch/arm/mach-shmobile/include/mach/pm-rcar.h
+++ b/arch/arm/mach-shmobile/pm-rcar.h
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index f710235aff2f..ebdd16e94a84 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -17,7 +17,7 @@
 #include <linux/pm.h>
 #include <linux/pm_clock.h>
 #include <asm/io.h>
-#include <mach/pm-rmobile.h>
+#include "pm-rmobile.h"
 
 /* SYSC */
 #define SPDCR           IOMEM(0xe6180008)
diff --git a/arch/arm/mach-shmobile/include/mach/pm-rmobile.h b/arch/arm/mach-shmobile/pm-rmobile.h
index 690553a06887..690553a06887 100644
--- a/arch/arm/mach-shmobile/include/mach/pm-rmobile.h
+++ b/arch/arm/mach-shmobile/pm-rmobile.h
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index 0de75fd394b9..7e5c2676c489 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -21,13 +21,15 @@
 #include <linux/irq.h>
 #include <linux/bitrev.h>
 #include <linux/console.h>
+
 #include <asm/cpuidle.h>
 #include <asm/io.h>
 #include <asm/tlbflush.h>
 #include <asm/suspend.h>
-#include <mach/common.h>
-#include <mach/sh7372.h>
-#include <mach/pm-rmobile.h>
+
+#include "common.h"
+#include "pm-rmobile.h"
+#include "sh7372.h"
 
 /* DBG */
 #define DBGREG1 IOMEM(0xe6100020)
diff --git a/arch/arm/mach-shmobile/pm-sh73a0.c b/arch/arm/mach-shmobile/pm-sh73a0.c
index 99086e98fbbc..a7e466817965 100644
--- a/arch/arm/mach-shmobile/pm-sh73a0.c
+++ b/arch/arm/mach-shmobile/pm-sh73a0.c
@@ -9,7 +9,7 @@
  */
 
 #include <linux/suspend.h>
-#include <mach/common.h>
+#include "common.h"
 
 #ifdef CONFIG_SUSPEND
 static int sh73a0_enter_suspend(suspend_state_t suspend_state)
diff --git a/arch/arm/mach-shmobile/include/mach/r7s72100.h b/arch/arm/mach-shmobile/r7s72100.h
index 5f34b20ecd4a..efb723c88dd0 100644
--- a/arch/arm/mach-shmobile/include/mach/r7s72100.h
+++ b/arch/arm/mach-shmobile/r7s72100.h
@@ -3,6 +3,5 @@
 
 void r7s72100_add_dt_devices(void);
 void r7s72100_clock_init(void);
-void r7s72100_init_early(void);
 
 #endif /* __ASM_R7S72100_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/r8a73a4.h
index ce8bdd1d8a8a..ce8bdd1d8a8a 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/r8a73a4.h
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/r8a7740.h
index 5e3c9ec06303..1d1a5fd78b6b 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/r8a7740.h
@@ -19,8 +19,6 @@
 #ifndef __ASM_R8A7740_H__
 #define __ASM_R8A7740_H__
 
-#include <mach/pm-rmobile.h>
-
 /*
  * MD_CKx pin
  */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/r8a7778.h
index f4076a50e970..f4076a50e970 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/r8a7778.h
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/r8a7779.h
index 88eeceaf1088..5415c719dc19 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/r8a7779.h
@@ -2,8 +2,6 @@
 #define __ASM_R8A7779_H__
 
 #include <linux/sh_clk.h>
-#include <linux/pm_domain.h>
-#include <mach/pm-rcar.h>
 
 /* HPB-DMA slave IDs */
 enum {
@@ -12,17 +10,6 @@ enum {
         HPBDMA_SLAVE_SDHI0_RX,
 };
 
-struct r8a7779_pm_domain {
-        struct generic_pm_domain genpd;
-        struct rcar_sysc_ch ch;
-};
-
-static inline struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d)
-{
-        return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
-}
-
-extern void r8a7779_init_delay(void);
 extern void r8a7779_init_irq_extpin(int irlm);
 extern void r8a7779_init_irq_extpin_dt(int irlm);
 extern void r8a7779_init_irq_dt(void);
@@ -32,6 +19,7 @@ extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
 extern void r8a7779_add_standard_devices_dt(void);
 extern void r8a7779_init_late(void);
+extern u32 r8a7779_read_mode_pins(void);
 extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/r8a7790.h
index 0b95babe84ba..459827f1369b 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-shmobile/r8a7790.h
@@ -1,8 +1,6 @@
 #ifndef __ASM_R8A7790_H__
 #define __ASM_R8A7790_H__
 
-#include <mach/rcar-gen2.h>
-
 /* DMA slave IDs */
 enum {
         RCAR_DMA_SLAVE_INVALID,
@@ -33,7 +31,6 @@ void r8a7790_add_dt_devices(void);
 void r8a7790_clock_init(void);
 void r8a7790_pinmux_init(void);
 void r8a7790_pm_init(void);
-void r8a7790_init_early(void);
 extern struct smp_operations r8a7790_smp_ops;
 
 #endif /* __ASM_R8A7790_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7791.h b/arch/arm/mach-shmobile/r8a7791.h
index 664274cc4b64..86eae7bceb6f 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7791.h
+++ b/arch/arm/mach-shmobile/r8a7791.h
@@ -5,6 +5,7 @@ void r8a7791_add_standard_devices(void);
 void r8a7791_add_dt_devices(void);
 void r8a7791_clock_init(void);
 void r8a7791_pinmux_init(void);
+void r8a7791_pm_init(void);
 extern struct smp_operations r8a7791_smp_ops;
 
 #endif /* __ASM_R8A7791_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/rcar-gen2.h b/arch/arm/mach-shmobile/rcar-gen2.h
index 43f606eb2d82..ce53cb5f53a1 100644
--- a/arch/arm/mach-shmobile/include/mach/rcar-gen2.h
+++ b/arch/arm/mach-shmobile/rcar-gen2.h
@@ -4,5 +4,6 @@
 void rcar_gen2_timer_init(void);
 #define MD(nr) BIT(nr)
 u32 rcar_gen2_read_mode_pins(void);
+void rcar_gen2_reserve(void);
 
 #endif /* __ASM_RCAR_GEN2_H__ */
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index d953ff6e78a2..b06a9e8f59a5 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -16,14 +16,13 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
-#include <linux/clk-provider.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/of_platform.h>
-#include <mach/common.h>
+#include <linux/mm.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include "common.h"
 
 static struct map_desc emev2_io_desc[] __initdata = {
 #ifdef CONFIG_SMP
@@ -42,17 +41,6 @@ static void __init emev2_map_io(void)
         iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc));
 }
 
-static void __init emev2_init_delay(void)
-{
-        shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
-}
-
-static void __init emev2_add_standard_devices_dt(void)
-{
-        of_clk_init(NULL);
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
 static const char *emev2_boards_compat_dt[] __initconst = {
         "renesas,emev2",
         NULL,
@@ -63,8 +51,7 @@ extern struct smp_operations emev2_smp_ops;
 DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
         .smp            = smp_ops(emev2_smp_ops),
         .map_io         = emev2_map_io,
-        .init_early     = emev2_init_delay,
-        .init_machine   = emev2_add_standard_devices_dt,
+        .init_early     = shmobile_init_delay,
         .init_late      = shmobile_init_late,
         .dt_compat      = emev2_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c
index 412e179429cd..4a98b232d316 100644
--- a/arch/arm/mach-shmobile/setup-r7s72100.c
+++ b/arch/arm/mach-shmobile/setup-r7s72100.c
@@ -22,11 +22,13 @@
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/sh_timer.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/r7s72100.h>
+
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "r7s72100.h"
+
 static struct resource mtu2_resources[] __initdata = {
         DEFINE_RES_MEM(0xfcff0000, 0x400),
         DEFINE_RES_IRQ_NAMED(gic_iid(139), "tgi0a"),
@@ -43,11 +45,6 @@ void __init r7s72100_add_dt_devices(void)
         r7s72100_register_mtu2();
 }
 
-void __init r7s72100_init_early(void)
-{
-        shmobile_setup_delay(400, 1, 3); /* Cortex-A9 @ 400MHz */
-}
-
 #ifdef CONFIG_USE_OF
 static const char *r7s72100_boards_compat_dt[] __initdata = {
         "renesas,r7s72100",
@@ -55,7 +52,7 @@ static const char *r7s72100_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)")
-        .init_early     = r7s72100_init_early,
+        .init_early     = shmobile_init_delay,
         .dt_compat      = r7s72100_boards_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index 9333770cfac2..f470b3cc0b7b 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -24,12 +24,14 @@
 #include <linux/serial_sci.h>
 #include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
-#include <mach/common.h>
-#include <mach/dma-register.h>
-#include <mach/irqs.h>
-#include <mach/r8a73a4.h>
+
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "dma-register.h"
+#include "irqs.h"
+#include "r8a73a4.h"
+
 static const struct resource pfc_resources[] = {
         DEFINE_RES_MEM(0xe6050000, 0x9000),
 };
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 35dec233301e..348af358a239 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -31,16 +31,18 @@
 #include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
 #include <linux/platform_data/sh_ipmmu.h>
-#include <mach/dma-register.h>
-#include <mach/r8a7740.h>
-#include <mach/pm-rmobile.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
+#include "common.h"
+#include "dma-register.h"
+#include "irqs.h"
+#include "pm-rmobile.h"
+#include "r8a7740.h"
+
 static struct map_desc r8a7740_io_desc[] __initdata = {
          /*
           * for CPGA/INTC/PFC
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index d311ef903b39..2ccc0128b469 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -37,12 +37,14 @@
 #include <linux/usb/ehci_pdriver.h>
 #include <linux/usb/ohci_pdriver.h>
 #include <linux/dma-mapping.h>
-#include <mach/irqs.h>
-#include <mach/r8a7778.h>
-#include <mach/common.h>
+
 #include <asm/mach/arch.h>
 #include <asm/hardware/cache-l2x0.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "r8a7778.h"
+
 /* SCIF */
 #define R8A7778_SCIF(index, baseaddr, irq)                      \
 static struct plat_sci_port scif##index##_platform_data = {     \
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index aba4ed652d54..8dbc407f4c8d 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -40,15 +40,17 @@
 #include <linux/usb/ehci_pdriver.h>
 #include <linux/usb/ohci_pdriver.h>
 #include <linux/pm_runtime.h>
-#include <mach/irqs.h>
-#include <mach/r8a7779.h>
-#include <mach/common.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <asm/hardware/cache-l2x0.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "r8a7779.h"
+
 static struct map_desc r8a7779_io_desc[] __initdata = {
         /* 2M entity map for 0xf0000000 (MPCORE) */
         {
@@ -640,16 +642,16 @@ static void __init r8a7779_register_hpb_dmae(void)
 }
 
 static struct platform_device *r8a7779_devices_dt[] __initdata = {
+        &tmu0_device,
+};
+
+static struct platform_device *r8a7779_standard_devices[] __initdata = {
         &scif0_device,
         &scif1_device,
         &scif2_device,
         &scif3_device,
         &scif4_device,
         &scif5_device,
-        &tmu0_device,
-};
-
-static struct platform_device *r8a7779_standard_devices[] __initdata = {
         &i2c0_device,
         &i2c1_device,
         &i2c2_device,
@@ -674,16 +676,6 @@ void __init r8a7779_add_standard_devices(void)
         r8a7779_register_hpb_dmae();
 }
 
-/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
-void __init __weak r8a7779_register_twd(void) { }
-
-void __init r8a7779_earlytimer_init(void)
-{
-        r8a7779_clock_init();
-        r8a7779_register_twd();
-        shmobile_earlytimer_init();
-}
-
 void __init r8a7779_add_early_devices(void)
 {
         early_platform_add_devices(r8a7779_devices_dt,
@@ -747,19 +739,28 @@ void __init r8a7779_init_irq_dt(void)
         __raw_writel(0x003fee3f, INT2SMSKCR4);
 }
 
-void __init r8a7779_init_delay(void)
+void __init r8a7779_add_standard_devices_dt(void)
 {
-        shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
+        platform_add_devices(r8a7779_devices_dt,
+                             ARRAY_SIZE(r8a7779_devices_dt));
 }
 
-void __init r8a7779_add_standard_devices_dt(void)
+#define MODEMR          0xffcc0020
+
+u32 __init r8a7779_read_mode_pins(void)
 {
-        /* clocks are setup late during boot in the case of DT */
-        r8a7779_clock_init();
+        static u32 mode;
+        static bool mode_valid;
+
+        if (!mode_valid) {
+                void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+                BUG_ON(!modemr);
+                mode = ioread32(modemr);
+                iounmap(modemr);
+                mode_valid = true;
+        }
 
-        platform_add_devices(r8a7779_devices_dt,
-                             ARRAY_SIZE(r8a7779_devices_dt));
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        return mode;
 }
 
 static const char *r8a7779_compat_dt[] __initdata = {
@@ -769,7 +770,7 @@ static const char *r8a7779_compat_dt[] __initdata = {
 
 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
         .map_io         = r8a7779_map_io,
-        .init_early     = r8a7779_init_delay,
+        .init_early     = shmobile_init_delay,
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = r8a7779_init_irq_dt,
         .init_machine   = r8a7779_add_standard_devices_dt,
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 6bd08b127fa4..c37d82d38617 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -26,12 +26,15 @@
 #include <linux/serial_sci.h>
 #include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
-#include <mach/common.h>
-#include <mach/dma-register.h>
-#include <mach/irqs.h>
-#include <mach/r8a7790.h>
+
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "dma-register.h"
+#include "irqs.h"
+#include "r8a7790.h"
+#include "rcar-gen2.h"
+
 /* Audio-DMAC */
 #define AUDIO_DMAC_SLAVE(_id, _addr, t, r)                      \
 {                                                               \
@@ -307,13 +310,6 @@ void __init r8a7790_add_standard_devices(void)
         r8a7790_register_audio_dmac(1);
 }
 
-void __init r8a7790_init_early(void)
-{
-#ifndef CONFIG_ARM_ARCH_TIMER
-        shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
-#endif
-}
-
 #ifdef CONFIG_USE_OF
 
 static const char * const r8a7790_boards_compat_dt[] __initconst = {
@@ -323,8 +319,10 @@ static const char * const r8a7790_boards_compat_dt[] __initconst = {
 
 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
         .smp            = smp_ops(r8a7790_smp_ops),
-        .init_early     = r8a7790_init_early,
+        .init_early     = shmobile_init_delay,
         .init_time      = rcar_gen2_timer_init,
+        .init_late      = shmobile_init_late,
+        .reserve        = rcar_gen2_reserve,
         .dt_compat      = r8a7790_boards_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c
index 04a96ddb3224..8823324ac5a9 100644
--- a/arch/arm/mach-shmobile/setup-r8a7791.c
+++ b/arch/arm/mach-shmobile/setup-r8a7791.c
@@ -26,12 +26,14 @@
 #include <linux/platform_data/irq-renesas-irqc.h>
 #include <linux/serial_sci.h>
 #include <linux/sh_timer.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/r8a7791.h>
-#include <mach/rcar-gen2.h>
+
 #include <asm/mach/arch.h>
 
+#include "common.h"
+#include "irqs.h"
+#include "r8a7791.h"
+#include "rcar-gen2.h"
+
 static const struct resource pfc_resources[] __initconst = {
         DEFINE_RES_MEM(0xe6060000, 0x250),
 };
@@ -217,6 +219,8 @@ DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
         .smp            = smp_ops(r8a7791_smp_ops),
         .init_early     = shmobile_init_delay,
         .init_time      = rcar_gen2_timer_init,
+        .init_late      = shmobile_init_late,
+        .reserve        = rcar_gen2_reserve,
         .dt_compat      = r8a7791_boards_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 542c5a47173f..42d5b4308923 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -20,11 +20,14 @@
 
 #include <linux/clk/shmobile.h>
 #include <linux/clocksource.h>
+#include <linux/device.h>
+#include <linux/dma-contiguous.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
-#include <mach/common.h>
-#include <mach/rcar-gen2.h>
+#include <linux/of_fdt.h>
 #include <asm/mach/arch.h>
+#include "common.h"
+#include "rcar-gen2.h"
 
 #define MODEMR 0xe6160060
 
@@ -110,3 +113,72 @@ void __init rcar_gen2_timer_init(void)
 #endif
         clocksource_of_init();
 }
+
+struct memory_reserve_config {
+        u64 reserved;
+        u64 base, size;
+};
+
+static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname,
+                                     int depth, void *data)
+{
+        const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
+        const __be32 *reg, *endp;
+        int l;
+        struct memory_reserve_config *mrc = data;
+        u64 lpae_start = 1ULL << 32;
+
+        /* We are scanning "memory" nodes only */
+        if (type == NULL || strcmp(type, "memory"))
+                return 0;
+
+        reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
+        if (reg == NULL)
+                reg = of_get_flat_dt_prop(node, "reg", &l);
+        if (reg == NULL)
+                return 0;
+
+        endp = reg + (l / sizeof(__be32));
+        while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
+                u64 base, size;
+
+                base = dt_mem_next_cell(dt_root_addr_cells, &reg);
+                size = dt_mem_next_cell(dt_root_size_cells, &reg);
+
+                if (base >= lpae_start)
+                        continue;
+
+                if ((base + size) >= lpae_start)
+                        size = lpae_start - base;
+
+                if (size < mrc->reserved)
+                        continue;
+
+                if (base < mrc->base)
+                        continue;
+
+                /* keep the area at top near the 32-bit legacy limit */
+                mrc->base = base + size - mrc->reserved;
+                mrc->size = mrc->reserved;
+        }
+
+        return 0;
+}
+
+struct cma *rcar_gen2_dma_contiguous;
+
+void __init rcar_gen2_reserve(void)
+{
+        struct memory_reserve_config mrc;
+
+        /* reserve 256 MiB at the top of the physical legacy 32-bit space */
+        memset(&mrc, 0, sizeof(mrc));
+        mrc.reserved = SZ_256M;
+
+        of_scan_flat_dt(rcar_gen2_scan_mem, &mrc);
+#ifdef CONFIG_DMA_CMA
+        if (mrc.size)
+                dma_contiguous_reserve_area(mrc.size, mrc.base, 0,
+                                            &rcar_gen2_dma_contiguous, true);
+#endif
+}
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 2a8b9f2a2f54..9cdfcdfd38fc 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -29,20 +29,22 @@
 #include <linux/io.h>
 #include <linux/serial_sci.h>
 #include <linux/sh_dma.h>
-#include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <linux/pm_domain.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_data/sh_ipmmu.h>
-#include <mach/dma-register.h>
-#include <mach/irqs.h>
-#include <mach/sh7372.h>
-#include <mach/common.h>
+
 #include <asm/mach/map.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
+#include "common.h"
+#include "dma-register.h"
+#include "irqs.h"
+#include "pm-rmobile.h"
+#include "sh7372.h"
+
 static struct map_desc sh7372_io_desc[] __initdata = {
         /* create a 1:1 entity map for 0xe6xxxxxx
          * used by CPGA, INTC and PFC.
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index ad00724a2269..224882151667 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -29,19 +29,20 @@
 #include <linux/io.h>
 #include <linux/serial_sci.h>
 #include <linux/sh_dma.h>
-#include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <linux/platform_data/sh_ipmmu.h>
 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
-#include <mach/dma-register.h>
-#include <mach/irqs.h>
-#include <mach/sh73a0.h>
-#include <mach/common.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
+#include "common.h"
+#include "dma-register.h"
+#include "irqs.h"
+#include "sh73a0.h"
+
 static struct map_desc sh73a0_io_desc[] __initdata = {
         /* create a 1:1 entity map for 0xe6xxxxxx
          * used by CPGA, INTC and PFC.
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/sh7372.h
index 854a9f0ca040..4ad960d5075b 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/sh7372.h
@@ -11,10 +11,6 @@
 #ifndef __ASM_SH7372_H__
 #define __ASM_SH7372_H__
 
-#include <linux/sh_clk.h>
-#include <linux/pm_domain.h>
-#include <mach/pm-rmobile.h>
-
 /* DMA slave IDs */
 enum {
         SHDMA_SLAVE_INVALID,
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/sh73a0.h
index 359b582dc270..359b582dc270 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/sh73a0.h
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 2dfd748da7f3..6ff1df1df9a7 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -23,9 +23,9 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
-#include <mach/common.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
+#include "common.h"
 
 #define EMEV2_SCU_BASE 0x1e000000
 #define EMEV2_SMU_BASE 0xe0110000
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index e7a3201473d0..3100e355c3fd 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -23,14 +23,16 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
-#include <mach/common.h>
-#include <mach/pm-rcar.h>
-#include <mach/r8a7779.h>
+
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
 
+#include "common.h"
+#include "pm-rcar.h"
+#include "r8a7779.h"
+
 #define AVECR IOMEM(0xfe700040)
 #define R8A7779_SCU_BASE 0xf0000000
 
diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c
index 591052799e8f..2311694636e1 100644
--- a/arch/arm/mach-shmobile/smp-r8a7790.c
+++ b/arch/arm/mach-shmobile/smp-r8a7790.c
@@ -17,17 +17,12 @@
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+
 #include <asm/smp_plat.h>
-#include <mach/common.h>
-#include <mach/pm-rcar.h>
-#include <mach/r8a7790.h>
 
-#define RST             0xe6160000
-#define CA15BAR         0x0020
-#define CA7BAR          0x0030
-#define CA15RESCNT      0x0040
-#define CA7RESCNT       0x0044
-#define MERAM           0xe8080000
+#include "common.h"
+#include "pm-rcar.h"
+#include "r8a7790.h"
 
 static struct rcar_sysc_ch r8a7790_ca15_scu = {
         .chan_offs = 0x180, /* PWRSR5 .. PWRER5 */
@@ -41,32 +36,9 @@ static struct rcar_sysc_ch r8a7790_ca7_scu = {
 
 static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus)
 {
-        void __iomem *p;
-        u32 bar;
-
         /* let APMU code install data related to shmobile_boot_vector */
         shmobile_smp_apmu_prepare_cpus(max_cpus);
 
-        /* MERAM for jump stub, because BAR requires 256KB aligned address */
-        p = ioremap_nocache(MERAM, shmobile_boot_size);
-        memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
-        iounmap(p);
-
-        /* setup reset vectors */
-        p = ioremap_nocache(RST, 0x63);
-        bar = (MERAM >> 8) & 0xfffffc00;
-        writel_relaxed(bar, p + CA15BAR);
-        writel_relaxed(bar, p + CA7BAR);
-        writel_relaxed(bar | 0x10, p + CA15BAR);
-        writel_relaxed(bar | 0x10, p + CA7BAR);
-
-        /* enable clocks to all CPUs */
-        writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000,
-                       p + CA15RESCNT);
-        writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | 0x5a5a0000,
-                       p + CA7RESCNT);
-        iounmap(p);
-
         /* turn on power to SCU */
         r8a7790_pm_init();
         rcar_sysc_power_up(&r8a7790_ca15_scu);
diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c
index ec979529f30f..f743386166fb 100644
--- a/arch/arm/mach-shmobile/smp-r8a7791.c
+++ b/arch/arm/mach-shmobile/smp-r8a7791.c
@@ -17,39 +17,19 @@
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+
 #include <asm/smp_plat.h>
-#include <mach/common.h>
-#include <mach/r8a7791.h>
-#include <mach/rcar-gen2.h>
 
-#define RST             0xe6160000
-#define CA15BAR         0x0020
-#define CA15RESCNT      0x0040
-#define RAM             0xe6300000
+#include "common.h"
+#include "r8a7791.h"
+#include "rcar-gen2.h"
 
 static void __init r8a7791_smp_prepare_cpus(unsigned int max_cpus)
 {
-        void __iomem *p;
-        u32 bar;
-
         /* let APMU code install data related to shmobile_boot_vector */
         shmobile_smp_apmu_prepare_cpus(max_cpus);
 
-        /* RAM for jump stub, because BAR requires 256KB aligned address */
-        p = ioremap_nocache(RAM, shmobile_boot_size);
-        memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
-        iounmap(p);
-
-        /* setup reset vectors */
-        p = ioremap_nocache(RST, 0x63);
-        bar = (RAM >> 8) & 0xfffffc00;
-        writel_relaxed(bar, p + CA15BAR);
-        writel_relaxed(bar | 0x10, p + CA15BAR);
-
-        /* enable clocks to all CPUs */
-        writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000,
-                       p + CA15RESCNT);
-        iounmap(p);
+        r8a7791_pm_init();
 }
 
 static int r8a7791_smp_boot_secondary(unsigned int cpu,
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 13ba36a6831f..22d8f87b23e9 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -22,11 +22,13 @@
 #include <linux/smp.h>
 #include <linux/io.h>
 #include <linux/delay.h>
-#include <mach/common.h>
-#include <mach/sh73a0.h>
+
 #include <asm/smp_plat.h>
 #include <asm/smp_twd.h>
 
+#include "common.h"
+#include "sh73a0.h"
+
 #define WUPCR           IOMEM(0xe6151010)
 #define SRESCR          IOMEM(0xe6151018)
 #define PSTR            IOMEM(0xe6151040)
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index 68bc0b82226d..942efdc82a62 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -59,29 +59,37 @@ void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz,
 
 void __init shmobile_init_delay(void)
 {
-        struct device_node *np, *parent;
-        u32 max_freq, freq;
-
-        max_freq = 0;
-
-        parent = of_find_node_by_path("/cpus");
-        if (parent) {
-                for_each_child_of_node(parent, np) {
-                        if (!of_property_read_u32(np, "clock-frequency", &freq))
-                                max_freq = max(max_freq, freq);
-                }
-                of_node_put(parent);
-        }
+        struct device_node *np, *cpus;
+        bool is_a8_a9 = false;
+        bool is_a15 = false;
+        u32 max_freq = 0;
+
+        cpus = of_find_node_by_path("/cpus");
+        if (!cpus)
+                return;
+
+        for_each_child_of_node(cpus, np) {
+                u32 freq;
+
+                if (!of_property_read_u32(np, "clock-frequency", &freq))
+                        max_freq = max(max_freq, freq);
 
-        if (max_freq) {
-                if (of_find_compatible_node(NULL, NULL, "arm,cortex-a8"))
-                        shmobile_setup_delay_hz(max_freq, 1, 3);
-                else if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
-                        shmobile_setup_delay_hz(max_freq, 1, 3);
-                else if (of_find_compatible_node(NULL, NULL, "arm,cortex-a15"))
-                        if (!IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
-                                shmobile_setup_delay_hz(max_freq, 2, 4);
+                if (of_device_is_compatible(np, "arm,cortex-a8") ||
+                    of_device_is_compatible(np, "arm,cortex-a9"))
+                        is_a8_a9 = true;
+                else if (of_device_is_compatible(np, "arm,cortex-a15"))
+                        is_a15 = true;
         }
+
+        of_node_put(cpus);
+
+        if (!max_freq)
+                return;
+
+        if (is_a8_a9)
+                shmobile_setup_delay_hz(max_freq, 1, 3);
+        else if (is_a15 && !IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
+                shmobile_setup_delay_hz(max_freq, 2, 4);
 }
 
 static void __init shmobile_late_time_init(void)
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index 0786249b2832..90df2022276a 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -14,7 +14,6 @@ if PLAT_SPEAR
 config ARCH_SPEAR13XX
         bool "ST SPEAr13xx"
         depends on ARCH_MULTI_V7 || PLAT_SPEAR_SINGLE
-        select ARCH_HAS_CPUFREQ
         select ARM_GIC
         select GPIO_SPEAR_SPICS
         select HAVE_ARM_SCU if SMP
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index abf9ee9bbc3f..878e9ec97d0f 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -1,5 +1,5 @@
 menuconfig ARCH_STI
-        bool "STMicroelectronics Consumer Electronics SOCs with Device Trees" if ARCH_MULTI_V7
+        bool "STMicroelectronics Consumer Electronics SOCs" if ARCH_MULTI_V7
         select ARM_GIC
         select ARM_GLOBAL_TIMER
         select PINCTRL
@@ -11,8 +11,8 @@ menuconfig ARCH_STI
         select ARM_ERRATA_754322
         select ARM_ERRATA_764369 if SMP
         select ARM_ERRATA_775420
-        select PL310_ERRATA_753970 if CACHE_PL310
-        select PL310_ERRATA_769419 if CACHE_PL310
+        select PL310_ERRATA_753970 if CACHE_L2X0
+        select PL310_ERRATA_769419 if CACHE_L2X0
         help
           Include support for STiH41x SOCs like STiH415/416 using the device tree
           for discovery
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index e16999e5b735..095399618ca5 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -1,6 +1,5 @@
-config ARCH_TEGRA
+menuconfig ARCH_TEGRA
         bool "NVIDIA Tegra" if ARCH_MULTI_V7
-        select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
         select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
         select ARM_GIC
@@ -16,8 +15,7 @@ config ARCH_TEGRA
         help
           This enables support for NVIDIA Tegra based systems.
 
-menu "NVIDIA Tegra options"
-        depends on ARCH_TEGRA
+if ARCH_TEGRA
 
 config ARCH_TEGRA_2x_SOC
         bool "Enable support for Tegra20 family"
@@ -69,4 +67,4 @@ config TEGRA_AHB
           which controls AHB bus master arbitration and some
           performance parameters(priority, prefech size).
 
-endmenu
+endif
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index e3a96d7302e9..bc51a71394af 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -1,4 +1,4 @@
-config ARCH_U300
+menuconfig ARCH_U300
         bool "ST-Ericsson U300 Series" if ARCH_MULTI_V5
         depends on MMU
         select ARCH_REQUIRE_GPIOLIB
@@ -16,8 +16,6 @@ config ARCH_U300
 
 if ARCH_U300
 
-menu "ST-Ericsson AB U300/U335 Platform"
-
 config MACH_U300
         depends on ARCH_U300
         bool "U300"
@@ -43,6 +41,4 @@ config MACH_U300_SPIDUMMY
                 you don't need it. Selecting this will activate the
                 SPI framework and ARM PL022 support.
 
-endmenu
-
 endif
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index b41a42da1505..699e8601dbf0 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -1,9 +1,8 @@
-config ARCH_U8500
+menuconfig ARCH_U8500
         bool "ST-Ericsson U8500 Series" if ARCH_MULTI_V7
         depends on MMU
         select AB8500_CORE
         select ABX500_CORE
-        select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
         select ARM_AMBA
         select ARM_ERRATA_754322
@@ -16,7 +15,7 @@ config ARCH_U8500
         select PINCTRL
         select PINCTRL_ABX500
         select PINCTRL_NOMADIK
-        select PL310_ERRATA_753970 if CACHE_PL310
+        select PL310_ERRATA_753970 if CACHE_L2X0
         help
           Support for ST-Ericsson's Ux500 architecture
 
@@ -34,8 +33,6 @@ config UX500_SOC_DB8500
         select REGULATOR
         select REGULATOR_DB8500_PRCMU
 
-menu "Ux500 target platform (boards)"
-
 config MACH_MOP500
         bool "U8500 Development platform, MOP500 versions"
         select I2C
@@ -68,8 +65,6 @@ config UX500_AUTO_PLATFORM
           a working kernel. If everything else is disabled, this
           automatically enables MACH_MOP500.
 
-endmenu
-
 config UX500_DEBUG_UART
         int "Ux500 UART to use for low-level debug"
         default 2
diff --git a/arch/arm/mach-versatile/versatile_dt.c b/arch/arm/mach-versatile/versatile_dt.c
index 3621b000a0f6..9f9bc61ca64b 100644
--- a/arch/arm/mach-versatile/versatile_dt.c
+++ b/arch/arm/mach-versatile/versatile_dt.c
@@ -44,7 +44,6 @@ static const char *versatile_dt_match[] __initconst = {
 DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)")
         .map_io         = versatile_map_io,
         .init_early     = versatile_init_early,
-        .init_irq       = versatile_init_irq,
         .init_machine   = versatile_dt_init,
         .dt_compat      = versatile_dt_match,
         .restart        = versatile_restart,
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 90249cfc37b3..d8b9330f896a 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -1,4 +1,4 @@
-config ARCH_VEXPRESS
+menuconfig ARCH_VEXPRESS
         bool "ARM Ltd. Versatile Express family" if ARCH_MULTI_V7
         select ARCH_REQUIRE_GPIOLIB
         select ARCH_SUPPORTS_BIG_ENDIAN
@@ -37,14 +37,13 @@ config ARCH_VEXPRESS
           platforms. The traditional (ATAGs) boot method is not usable on
           these boards with this option.
 
-menu "Versatile Express platform type"
-        depends on ARCH_VEXPRESS
+if ARCH_VEXPRESS
 
 config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
         bool "Enable A5 and A9 only errata work-arounds"
         default y
         select ARM_ERRATA_720789
-        select PL310_ERRATA_753970 if CACHE_PL310
+        select PL310_ERRATA_753970 if CACHE_L2X0
         help
           Provides common dependencies for Versatile Express platforms
           based on Cortex-A5 and Cortex-A9 processors. In order to
@@ -65,7 +64,6 @@ config ARCH_VEXPRESS_DCSCB
 
 config ARCH_VEXPRESS_SPC
         bool "Versatile Express Serial Power Controller (SPC)"
-        select ARCH_HAS_CPUFREQ
         select ARCH_HAS_OPP
         select PM_OPP
         help
@@ -83,4 +81,4 @@ config ARCH_VEXPRESS_TC2_PM
           Support for CPU and cluster power management on Versatile Express
           with a TC2 (A15x2 A7x3) big.LITTLE core tile.
 
-endmenu
+endif
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
index 08f56a41cb55..aaaa24fe4d71 100644
--- a/arch/arm/mach-vt8500/Kconfig
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -1,6 +1,5 @@
 config ARCH_VT8500
         bool
-        select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
         select VT8500_TIMER
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 573e0db1d0f0..0c164f81e72d 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -1,6 +1,5 @@
 config ARCH_ZYNQ
         bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7
-        select ARCH_HAS_CPUFREQ
         select ARCH_HAS_OPP
         select ARCH_SUPPORTS_BIG_ENDIAN
         select ARM_AMBA
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index eda0dd0ab97b..c348eaee7ee2 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -889,9 +889,10 @@ config CACHE_L2X0
         help
           This option enables the L2x0 PrimeCell.
 
+if CACHE_L2X0
+
 config CACHE_PL310
         bool
-        depends on CACHE_L2X0
         default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
         help
           This option enables optimisations for the PL310 cache
@@ -899,7 +900,6 @@ config CACHE_PL310
 
 config PL310_ERRATA_588369
         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
-        depends on CACHE_L2X0
         help
            The PL310 L2 cache controller implements three types of Clean &
            Invalidate maintenance operations: by Physical Address
@@ -912,7 +912,6 @@ config PL310_ERRATA_588369
 
 config PL310_ERRATA_727915
         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
-        depends on CACHE_L2X0
         help
           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
           operation (offset 0x7FC). This operation runs in background so that
@@ -923,7 +922,6 @@ config PL310_ERRATA_727915
 
 config PL310_ERRATA_753970
         bool "PL310 errata: cache sync operation may be faulty"
-        depends on CACHE_PL310
         help
           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
 
@@ -938,7 +936,6 @@ config PL310_ERRATA_753970
 
 config PL310_ERRATA_769419
         bool "PL310 errata: no automatic Store Buffer drain"
-        depends on CACHE_L2X0
         help
           On revisions of the PL310 prior to r3p2, the Store Buffer does
           not automatically drain. This can cause normal, non-cacheable
@@ -948,6 +945,8 @@ config PL310_ERRATA_769419
           on systems with an outer cache, the store buffer is drained
           explicitly.
 
+endif
+
 config CACHE_TAUROS2
         bool "Enable the Tauros2 L2 cache controller"
         depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index efc5cabf70e0..076172b69422 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1069,6 +1069,33 @@ static const struct l2c_init_data of_l2c310_data __initconst = {
 };
 
 /*
+ * This is a variant of the of_l2c310_data with .sync set to
+ * NULL. Outer sync operations are not needed when the system is I/O
+ * coherent, and potentially harmful in certain situations (PCIe/PL310
+ * deadlock on Armada 375/38x due to hardware I/O coherency). The
+ * other operations are kept because they are infrequent (therefore do
+ * not cause the deadlock in practice) and needed for secondary CPU
+ * boot and other power management activities.
+ */
+static const struct l2c_init_data of_l2c310_coherent_data __initconst = {
+        .type = "L2C-310 Coherent",
+        .way_size_0 = SZ_8K,
+        .num_lock = 8,
+        .of_parse = l2c310_of_parse,
+        .enable = l2c310_enable,
+        .fixup = l2c310_fixup,
+        .save  = l2c310_save,
+        .outer_cache = {
+                .inv_range   = l2c210_inv_range,
+                .clean_range = l2c210_clean_range,
+                .flush_range = l2c210_flush_range,
+                .flush_all   = l2c210_flush_all,
+                .disable     = l2c310_disable,
+                .resume      = l2c310_resume,
+        },
+};
+
+/*
  * Note that the end addresses passed to Linux primitives are
  * noninclusive, while the hardware cache range operations use
  * inclusive start and end addresses.
@@ -1487,6 +1514,10 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 
         data = of_match_node(l2x0_ids, np)->data;
 
+        if (of_device_is_compatible(np, "arm,pl310-cache") &&
+            of_property_read_bool(np, "arm,io-coherent"))
+                data = &of_l2c310_coherent_data;
+
         old_aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
         if (old_aux != ((old_aux & aux_mask) | aux_val)) {
                 pr_warn("L2C: platform modifies aux control register: 0x%08x -> 0x%08x\n",
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index da1874f9f8cf..a014dfacd5ca 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -300,6 +300,7 @@ void __init sanity_check_meminfo(void)
         sanity_check_meminfo_mpu();
         end = memblock_end_of_DRAM();
         high_memory = __va(end - 1) + 1;
+        memblock_set_current_limit(end);
 }
 
 /*
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 97448c3acf38..ba0d58e1a2a2 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -502,6 +502,7 @@ __\name\()_proc_info:
         .long   \cpu_val
         .long   \cpu_mask
         .long   PMD_TYPE_SECT | \
+                PMD_SECT_CACHEABLE | \
                 PMD_BIT4 | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 243dfcb2ca0e..301b892d97d9 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -35,27 +35,15 @@ config SAMSUNG_PM
           Base platform power management code for samsung code
 
 if PLAT_SAMSUNG
+menu "Samsung Common options"
 
 # boot configurations
 
 comment "Boot options"
 
-config S3C_BOOT_ERROR_RESET
-        bool "S3C Reboot on decompression error"
-        help
-          Say y here to use the watchdog to reset the system if the
-          kernel decompressor detects an error during decompression.
-
-config S3C_BOOT_UART_FORCE_FIFO
-       bool "Force UART FIFO on during boot process"
-       default y
-       help
-         Say Y here to force the UART FIFOs on during the kernel
-         uncompressor
-
-
 config S3C_LOWLEVEL_UART_PORT
         int "S3C UART to use for low-level messages"
+        depends on ARCH_S3C64XX
         default 0
         help
           Choice of which UART port to use for the low-level messages,
@@ -407,17 +395,16 @@ config SAMSUNG_PM_GPIO
           Include legacy GPIO power management code for platforms not using
           pinctrl-samsung driver.
 
-endif
-
 config SAMSUNG_DMADEV
-        bool
-        select ARM_AMBA
+        bool "Use legacy Samsung DMA abstraction"
+        depends on CPU_S5PV210 || CPU_S5PC100 || ARCH_S5P64X0 || ARCH_S3C64XX
         select DMADEVICES
-        select PL330_DMA if (ARCH_EXYNOS5 || ARCH_EXYNOS4 || CPU_S5PV210 || CPU_S5PC100 || \
-                                        CPU_S5P6450 || CPU_S5P6440)
+        default y
         help
           Use DMA device engine for PL330 DMAC.
 
+endif
+
 config S5P_DEV_MFC
         bool
         help
@@ -503,4 +490,5 @@ config DEBUG_S3C_UART
         default "2" if DEBUG_S3C_UART2
         default "3" if DEBUG_S3C_UART3
 
+endmenu
 endif