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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/boot/dts/spear300-evb.dts38
-rw-r--r--arch/arm/boot/dts/spear300.dtsi5
-rw-r--r--arch/arm/boot/dts/spear310-evb.dts61
-rw-r--r--arch/arm/boot/dts/spear310.dtsi5
-rw-r--r--arch/arm/boot/dts/spear320-evb.dts61
-rw-r--r--arch/arm/boot/dts/spear320.dtsi7
-rw-r--r--arch/arm/configs/imx_v4_v5_defconfig1
-rw-r--r--arch/arm/configs/u8500_defconfig9
-rw-r--r--arch/arm/mach-at91/at91rm9200_devices.c1
-rw-r--r--arch/arm/mach-at91/at91rm9200_time.c2
-rw-r--r--arch/arm/mach-at91/board-rm9200ek.c2
-rw-r--r--arch/arm/mach-at91/board-sam9261ek.c5
-rw-r--r--arch/arm/mach-at91/clock.c1
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pmc.h2
-rw-r--r--arch/arm/mach-at91/setup.c2
-rw-r--r--arch/arm/mach-bcmring/core.c4
-rw-r--r--arch/arm/mach-imx/imx27-dt.c6
-rw-r--r--arch/arm/mach-imx/mm-imx5.c2
-rw-r--r--arch/arm/mach-omap1/mux.c1
-rw-r--r--arch/arm/mach-omap1/timer.c4
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c12
-rw-r--r--arch/arm/mach-omap2/board-generic.c2
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c13
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c17
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c9
-rw-r--r--arch/arm/mach-omap2/serial.c124
-rw-r--r--arch/arm/mach-omap2/twl-common.c37
-rw-r--r--arch/arm/mach-omap2/twl-common.h10
-rw-r--r--arch/arm/mach-spear3xx/Kconfig3
-rw-r--r--arch/arm/mach-spear3xx/Makefile2
-rw-r--r--arch/arm/mach-spear3xx/clock.c892
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h147
-rw-r--r--arch/arm/mach-spear3xx/include/mach/misc_regs.h2
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear.h13
-rw-r--r--arch/arm/mach-spear3xx/spear300.c390
-rw-r--r--arch/arm/mach-spear3xx/spear310.c162
-rw-r--r--arch/arm/mach-spear3xx/spear320.c415
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c427
-rw-r--r--arch/arm/mach-spear6xx/Makefile2
-rw-r--r--arch/arm/mach-spear6xx/clock.c789
-rw-r--r--arch/arm/mach-spear6xx/include/mach/misc_regs.h2
-rw-r--r--arch/arm/mach-spear6xx/spear6xx.c5
-rw-r--r--arch/arm/mach-ux500/Kconfig1
-rw-r--r--arch/arm/mach-ux500/platsmp.c2
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h4
-rw-r--r--arch/arm/plat-omap/sram.c12
-rw-r--r--arch/arm/plat-spear/Kconfig1
-rw-r--r--arch/arm/plat-spear/Makefile4
-rw-r--r--arch/arm/plat-spear/clock.c1005
-rw-r--r--arch/arm/plat-spear/include/plat/clock.h249
-rw-r--r--arch/arm/plat-spear/include/plat/padmux.h92
-rw-r--r--arch/arm/plat-spear/padmux.c164
-rw-r--r--arch/arm/plat-spear/time.c8
57 files changed, 340 insertions, 4900 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cf006d40342c..ce030c242644 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -980,6 +980,7 @@ config PLAT_SPEAR
980 select ARM_AMBA 980 select ARM_AMBA
981 select ARCH_REQUIRE_GPIOLIB 981 select ARCH_REQUIRE_GPIOLIB
982 select CLKDEV_LOOKUP 982 select CLKDEV_LOOKUP
983 select COMMON_CLK
983 select CLKSRC_MMIO 984 select CLKSRC_MMIO
984 select GENERIC_CLOCKEVENTS 985 select GENERIC_CLOCKEVENTS
985 select HAVE_CLK 986 select HAVE_CLK
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
index bf491a332145..fc82b1a26458 100644
--- a/arch/arm/boot/dts/spear300-evb.dts
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -25,6 +25,44 @@
25 }; 25 };
26 26
27 ahb { 27 ahb {
28 pinmux@99000000 {
29 st,pinmux-mode = <2>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 ssp0 {
39 st,pins = "ssp0_grp";
40 st,function = "ssp0";
41 };
42 mii0 {
43 st,pins = "mii0_grp";
44 st,function = "mii0";
45 };
46 uart0 {
47 st,pins = "uart0_grp";
48 st,function = "uart0";
49 };
50 clcd {
51 st,pins = "clcd_pfmode_grp";
52 st,function = "clcd";
53 };
54 sdhci {
55 st,pins = "sdhci_4bit_grp";
56 st,function = "sdhci";
57 };
58 gpio1 {
59 st,pins = "gpio1_4_to_7_grp",
60 "gpio1_0_to_3_grp";
61 st,function = "gpio1";
62 };
63 };
64 };
65
28 clcd@60000000 { 66 clcd@60000000 {
29 status = "okay"; 67 status = "okay";
30 }; 68 };
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
index f9fcbf4f477b..01c5e358fdb2 100644
--- a/arch/arm/boot/dts/spear300.dtsi
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -21,6 +21,11 @@
21 ranges = <0x60000000 0x60000000 0x50000000 21 ranges = <0x60000000 0x60000000 0x50000000
22 0xd0000000 0xd0000000 0x30000000>; 22 0xd0000000 0xd0000000 0x30000000>;
23 23
24 pinmux@99000000 {
25 compatible = "st,spear300-pinmux";
26 reg = <0x99000000 0x1000>;
27 };
28
24 clcd@60000000 { 29 clcd@60000000 {
25 compatible = "arm,clcd-pl110", "arm,primecell"; 30 compatible = "arm,clcd-pl110", "arm,primecell";
26 reg = <0x60000000 0x1000>; 31 reg = <0x60000000 0x1000>;
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
index f7ecb0c1c6e8..dc5e2d445a93 100644
--- a/arch/arm/boot/dts/spear310-evb.dts
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -25,6 +25,67 @@
25 }; 25 };
26 26
27 ahb { 27 ahb {
28 pinmux@b4000000 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&state_default>;
31
32 state_default: pinmux {
33 gpio0 {
34 st,pins = "gpio0_pin0_grp",
35 "gpio0_pin1_grp",
36 "gpio0_pin2_grp",
37 "gpio0_pin3_grp",
38 "gpio0_pin4_grp",
39 "gpio0_pin5_grp";
40 st,function = "gpio0";
41 };
42 i2c0 {
43 st,pins = "i2c0_grp";
44 st,function = "i2c0";
45 };
46 mii0 {
47 st,pins = "mii0_grp";
48 st,function = "mii0";
49 };
50 ssp0 {
51 st,pins = "ssp0_grp";
52 st,function = "ssp0";
53 };
54 uart0 {
55 st,pins = "uart0_grp";
56 st,function = "uart0";
57 };
58 emi {
59 st,pins = "emi_cs_0_to_5_grp";
60 st,function = "emi";
61 };
62 fsmc {
63 st,pins = "fsmc_grp";
64 st,function = "fsmc";
65 };
66 uart1 {
67 st,pins = "uart1_grp";
68 st,function = "uart1";
69 };
70 uart2 {
71 st,pins = "uart2_grp";
72 st,function = "uart2";
73 };
74 uart3 {
75 st,pins = "uart3_grp";
76 st,function = "uart3";
77 };
78 uart4 {
79 st,pins = "uart4_grp";
80 st,function = "uart4";
81 };
82 uart5 {
83 st,pins = "uart5_grp";
84 st,function = "uart5";
85 };
86 };
87 };
88
28 dma@fc400000 { 89 dma@fc400000 {
29 status = "okay"; 90 status = "okay";
30 }; 91 };
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
index dc7fa14da846..e47081c494d9 100644
--- a/arch/arm/boot/dts/spear310.dtsi
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -22,6 +22,11 @@
22 0xb0000000 0xb0000000 0x10000000 22 0xb0000000 0xb0000000 0x10000000
23 0xd0000000 0xd0000000 0x30000000>; 23 0xd0000000 0xd0000000 0x30000000>;
24 24
25 pinmux@b4000000 {
26 compatible = "st,spear310-pinmux";
27 reg = <0xb4000000 0x1000>;
28 };
29
25 fsmc: flash@44000000 { 30 fsmc: flash@44000000 {
26 compatible = "st,spear600-fsmc-nand"; 31 compatible = "st,spear600-fsmc-nand";
27 #address-cells = <1>; 32 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index 8fb59d805be3..6308fa3bec1e 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -25,6 +25,67 @@
25 }; 25 };
26 26
27 ahb { 27 ahb {
28 pinmux@b3000000 {
29 st,pinmux-mode = <3>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 mii0 {
39 st,pins = "mii0_grp";
40 st,function = "mii0";
41 };
42 ssp0 {
43 st,pins = "ssp0_grp";
44 st,function = "ssp0";
45 };
46 uart0 {
47 st,pins = "uart0_grp";
48 st,function = "uart0";
49 };
50 sdhci {
51 st,pins = "sdhci_cd_51_grp";
52 st,function = "sdhci";
53 };
54 i2s {
55 st,pins = "i2s_grp";
56 st,function = "i2s";
57 };
58 uart1 {
59 st,pins = "uart1_grp";
60 st,function = "uart1";
61 };
62 uart2 {
63 st,pins = "uart2_grp";
64 st,function = "uart2";
65 };
66 can0 {
67 st,pins = "can0_grp";
68 st,function = "can0";
69 };
70 can1 {
71 st,pins = "can1_grp";
72 st,function = "can1";
73 };
74 mii2 {
75 st,pins = "mii2_grp";
76 st,function = "mii2";
77 };
78 pwm0_1 {
79 st,pins = "pwm0_1_pin_14_15_grp";
80 st,function = "pwm0_1";
81 };
82 pwm2 {
83 st,pins = "pwm2_pin_13_grp";
84 st,function = "pwm2";
85 };
86 };
87 };
88
28 clcd@90000000 { 89 clcd@90000000 {
29 status = "okay"; 90 status = "okay";
30 }; 91 };
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index 9a0267a5a0b7..5372ca399b1f 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -18,9 +18,14 @@
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 compatible = "simple-bus"; 20 compatible = "simple-bus";
21 ranges = <0x40000000 0x40000000 0x70000000 21 ranges = <0x40000000 0x40000000 0x80000000
22 0xd0000000 0xd0000000 0x30000000>; 22 0xd0000000 0xd0000000 0x30000000>;
23 23
24 pinmux@b3000000 {
25 compatible = "st,spear320-pinmux";
26 reg = <0xb3000000 0x1000>;
27 };
28
24 clcd@90000000 { 29 clcd@90000000 {
25 compatible = "arm,clcd-pl110", "arm,primecell"; 30 compatible = "arm,clcd-pl110", "arm,primecell";
26 reg = <0x90000000 0x1000>; 31 reg = <0x90000000 0x1000>;
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index b5ac644e12af..6b31cb60daab 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -112,6 +112,7 @@ CONFIG_WATCHDOG=y
112CONFIG_IMX2_WDT=y 112CONFIG_IMX2_WDT=y
113CONFIG_MFD_MC13XXX=y 113CONFIG_MFD_MC13XXX=y
114CONFIG_REGULATOR=y 114CONFIG_REGULATOR=y
115CONFIG_REGULATOR_FIXED_VOLTAGE=y
115CONFIG_REGULATOR_MC13783=y 116CONFIG_REGULATOR_MC13783=y
116CONFIG_REGULATOR_MC13892=y 117CONFIG_REGULATOR_MC13892=y
117CONFIG_FB=y 118CONFIG_FB=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 889d73ac1ae1..7e84f453e8a6 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -8,8 +8,6 @@ CONFIG_MODULE_UNLOAD=y
8# CONFIG_LBDAF is not set 8# CONFIG_LBDAF is not set
9# CONFIG_BLK_DEV_BSG is not set 9# CONFIG_BLK_DEV_BSG is not set
10CONFIG_ARCH_U8500=y 10CONFIG_ARCH_U8500=y
11CONFIG_UX500_SOC_DB5500=y
12CONFIG_UX500_SOC_DB8500=y
13CONFIG_MACH_HREFV60=y 11CONFIG_MACH_HREFV60=y
14CONFIG_MACH_SNOWBALL=y 12CONFIG_MACH_SNOWBALL=y
15CONFIG_MACH_U5500=y 13CONFIG_MACH_U5500=y
@@ -39,7 +37,6 @@ CONFIG_CAIF=y
39CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 37CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
40CONFIG_BLK_DEV_RAM=y 38CONFIG_BLK_DEV_RAM=y
41CONFIG_BLK_DEV_RAM_SIZE=65536 39CONFIG_BLK_DEV_RAM_SIZE=65536
42CONFIG_MISC_DEVICES=y
43CONFIG_AB8500_PWM=y 40CONFIG_AB8500_PWM=y
44CONFIG_SENSORS_BH1780=y 41CONFIG_SENSORS_BH1780=y
45CONFIG_NETDEVICES=y 42CONFIG_NETDEVICES=y
@@ -65,16 +62,18 @@ CONFIG_SERIAL_AMBA_PL011=y
65CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 62CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
66CONFIG_HW_RANDOM=y 63CONFIG_HW_RANDOM=y
67CONFIG_HW_RANDOM_NOMADIK=y 64CONFIG_HW_RANDOM_NOMADIK=y
68CONFIG_I2C=y
69CONFIG_I2C_NOMADIK=y
70CONFIG_SPI=y 65CONFIG_SPI=y
71CONFIG_SPI_PL022=y 66CONFIG_SPI_PL022=y
72CONFIG_GPIO_STMPE=y 67CONFIG_GPIO_STMPE=y
73CONFIG_GPIO_TC3589X=y 68CONFIG_GPIO_TC3589X=y
69CONFIG_POWER_SUPPLY=y
70CONFIG_AB8500_BM=y
71CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL=y
74CONFIG_MFD_STMPE=y 72CONFIG_MFD_STMPE=y
75CONFIG_MFD_TC3589X=y 73CONFIG_MFD_TC3589X=y
76CONFIG_AB5500_CORE=y 74CONFIG_AB5500_CORE=y
77CONFIG_AB8500_CORE=y 75CONFIG_AB8500_CORE=y
76CONFIG_REGULATOR=y
78CONFIG_REGULATOR_AB8500=y 77CONFIG_REGULATOR_AB8500=y
79# CONFIG_HID_SUPPORT is not set 78# CONFIG_HID_SUPPORT is not set
80CONFIG_USB_GADGET=y 79CONFIG_USB_GADGET=y
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 99ce5c955e39..05774e5b1cba 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -1173,7 +1173,6 @@ void __init at91_add_device_serial(void)
1173 printk(KERN_INFO "AT91: No default serial console defined.\n"); 1173 printk(KERN_INFO "AT91: No default serial console defined.\n");
1174} 1174}
1175#else 1175#else
1176void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
1177void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} 1176void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1178void __init at91_set_serial_console(unsigned portnr) {} 1177void __init at91_set_serial_console(unsigned portnr) {}
1179void __init at91_add_device_serial(void) {} 1178void __init at91_add_device_serial(void) {}
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index dd7f782b0b91..104ca40d8d18 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -23,6 +23,7 @@
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/irq.h> 24#include <linux/irq.h>
25#include <linux/clockchips.h> 25#include <linux/clockchips.h>
26#include <linux/export.h>
26 27
27#include <asm/mach/time.h> 28#include <asm/mach/time.h>
28 29
@@ -176,6 +177,7 @@ static struct clock_event_device clkevt = {
176}; 177};
177 178
178void __iomem *at91_st_base; 179void __iomem *at91_st_base;
180EXPORT_SYMBOL_GPL(at91_st_base);
179 181
180void __init at91rm9200_ioremap_st(u32 addr) 182void __init at91rm9200_ioremap_st(u32 addr)
181{ 183{
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 11cbaa8946fe..b2e4fe21f346 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -117,7 +117,7 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = {
117}; 117};
118 118
119#define EK_FLASH_BASE AT91_CHIPSELECT_0 119#define EK_FLASH_BASE AT91_CHIPSELECT_0
120#define EK_FLASH_SIZE SZ_2M 120#define EK_FLASH_SIZE SZ_8M
121 121
122static struct physmap_flash_data ek_flash_data = { 122static struct physmap_flash_data ek_flash_data = {
123 .width = 2, 123 .width = 2,
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index c3f994462864..065fed342424 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -85,8 +85,6 @@ static struct resource dm9000_resource[] = {
85 .flags = IORESOURCE_MEM 85 .flags = IORESOURCE_MEM
86 }, 86 },
87 [2] = { 87 [2] = {
88 .start = AT91_PIN_PC11,
89 .end = AT91_PIN_PC11,
90 .flags = IORESOURCE_IRQ 88 .flags = IORESOURCE_IRQ
91 | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE, 89 | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE,
92 } 90 }
@@ -130,6 +128,8 @@ static struct sam9_smc_config __initdata dm9000_smc_config = {
130 128
131static void __init ek_add_device_dm9000(void) 129static void __init ek_add_device_dm9000(void)
132{ 130{
131 struct resource *r = &dm9000_resource[2];
132
133 /* Configure chip-select 2 (DM9000) */ 133 /* Configure chip-select 2 (DM9000) */
134 sam9_smc_configure(0, 2, &dm9000_smc_config); 134 sam9_smc_configure(0, 2, &dm9000_smc_config);
135 135
@@ -139,6 +139,7 @@ static void __init ek_add_device_dm9000(void)
139 /* Configure Interrupt pin as input, no pull-up */ 139 /* Configure Interrupt pin as input, no pull-up */
140 at91_set_gpio_input(AT91_PIN_PC11, 0); 140 at91_set_gpio_input(AT91_PIN_PC11, 0);
141 141
142 r->start = r->end = gpio_to_irq(AT91_PIN_PC11);
142 platform_device_register(&dm9000_device); 143 platform_device_register(&dm9000_device);
143} 144}
144#else 145#else
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index a0f4d7424cdc..6b692824c988 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -35,6 +35,7 @@
35#include "generic.h" 35#include "generic.h"
36 36
37void __iomem *at91_pmc_base; 37void __iomem *at91_pmc_base;
38EXPORT_SYMBOL_GPL(at91_pmc_base);
38 39
39/* 40/*
40 * There's a lot more which can be done with clocks, including cpufreq 41 * There's a lot more which can be done with clocks, including cpufreq
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 36604782a78f..ea2c57a86ca6 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -25,7 +25,7 @@ extern void __iomem *at91_pmc_base;
25#define at91_pmc_write(field, value) \ 25#define at91_pmc_write(field, value) \
26 __raw_writel(value, at91_pmc_base + field) 26 __raw_writel(value, at91_pmc_base + field)
27#else 27#else
28.extern at91_aic_base 28.extern at91_pmc_base
29#endif 29#endif
30 30
31#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ 31#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 97cc04dc8073..f44a2e7272e3 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -54,6 +54,7 @@ void __init at91_init_interrupts(unsigned int *priority)
54} 54}
55 55
56void __iomem *at91_ramc_base[2]; 56void __iomem *at91_ramc_base[2];
57EXPORT_SYMBOL_GPL(at91_ramc_base);
57 58
58void __init at91_ioremap_ramc(int id, u32 addr, u32 size) 59void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
59{ 60{
@@ -292,6 +293,7 @@ void __init at91_ioremap_rstc(u32 base_addr)
292} 293}
293 294
294void __iomem *at91_matrix_base; 295void __iomem *at91_matrix_base;
296EXPORT_SYMBOL_GPL(at91_matrix_base);
295 297
296void __init at91_ioremap_matrix(u32 base_addr) 298void __init at91_ioremap_matrix(u32 base_addr)
297{ 299{
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index 22e4e0a28ad1..adbfb1994582 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -52,8 +52,8 @@
52#include <mach/csp/chipcHw_inline.h> 52#include <mach/csp/chipcHw_inline.h>
53#include <mach/csp/tmrHw_reg.h> 53#include <mach/csp/tmrHw_reg.h>
54 54
55static AMBA_APB_DEVICE(uartA, "uarta", MM_ADDR_IO_UARTA, { IRQ_UARTA }, NULL); 55static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
56static AMBA_APB_DEVICE(uartB, "uartb", MM_ADDR_IO_UARTB, { IRQ_UARTB }, NULL); 56static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
57 57
58static struct clk pll1_clk = { 58static struct clk pll1_clk = {
59 .name = "PLL1", 59 .name = "PLL1",
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 861ceb8232d6..ed38d03c61f2 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -35,7 +35,7 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
35static int __init imx27_avic_add_irq_domain(struct device_node *np, 35static int __init imx27_avic_add_irq_domain(struct device_node *np,
36 struct device_node *interrupt_parent) 36 struct device_node *interrupt_parent)
37{ 37{
38 irq_domain_add_simple(np, 0); 38 irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL);
39 return 0; 39 return 0;
40} 40}
41 41
@@ -44,7 +44,9 @@ static int __init imx27_gpio_add_irq_domain(struct device_node *np,
44{ 44{
45 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; 45 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
46 46
47 irq_domain_add_simple(np, gpio_irq_base); 47 gpio_irq_base -= 32;
48 irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
49 NULL);
48 50
49 return 0; 51 return 0;
50} 52}
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 05250aed61fb..e10f3914fcfe 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -35,7 +35,7 @@ static void imx5_idle(void)
35 } 35 }
36 clk_enable(gpc_dvfs_clk); 36 clk_enable(gpc_dvfs_clk);
37 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); 37 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
38 if (tzic_enable_wake() != 0) 38 if (!tzic_enable_wake())
39 cpu_do_idle(); 39 cpu_do_idle();
40 clk_disable(gpc_dvfs_clk); 40 clk_disable(gpc_dvfs_clk);
41} 41}
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 087dba0df47e..e9cc52d4cb28 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -27,6 +27,7 @@
27#include <linux/io.h> 27#include <linux/io.h>
28#include <linux/spinlock.h> 28#include <linux/spinlock.h>
29 29
30#include <mach/hardware.h>
30 31
31#include <plat/mux.h> 32#include <plat/mux.h>
32 33
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index 6e90665a7c47..fb202af01d0d 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -47,9 +47,9 @@ static int omap1_dm_timer_set_src(struct platform_device *pdev,
47 int n = (pdev->id - 1) << 1; 47 int n = (pdev->id - 1) << 1;
48 u32 l; 48 u32 l;
49 49
50 l = __raw_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); 50 l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
51 l |= source << n; 51 l |= source << n;
52 __raw_writel(l, MOD_CONF_CTRL_1); 52 omap_writel(l, MOD_CONF_CTRL_1);
53 53
54 return 0; 54 return 0;
55} 55}
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index a39fc4bbd2b8..130ab00c09a2 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -20,6 +20,7 @@
20#include <linux/usb/otg.h> 20#include <linux/usb/otg.h>
21#include <linux/spi/spi.h> 21#include <linux/spi/spi.h>
22#include <linux/i2c/twl.h> 22#include <linux/i2c/twl.h>
23#include <linux/mfd/twl6040.h>
23#include <linux/gpio_keys.h> 24#include <linux/gpio_keys.h>
24#include <linux/regulator/machine.h> 25#include <linux/regulator/machine.h>
25#include <linux/regulator/fixed.h> 26#include <linux/regulator/fixed.h>
@@ -560,7 +561,7 @@ static struct regulator_init_data sdp4430_vusim = {
560 }, 561 },
561}; 562};
562 563
563static struct twl4030_codec_data twl6040_codec = { 564static struct twl6040_codec_data twl6040_codec = {
564 /* single-step ramp for headset and handsfree */ 565 /* single-step ramp for headset and handsfree */
565 .hs_left_step = 0x0f, 566 .hs_left_step = 0x0f,
566 .hs_right_step = 0x0f, 567 .hs_right_step = 0x0f,
@@ -568,7 +569,7 @@ static struct twl4030_codec_data twl6040_codec = {
568 .hf_right_step = 0x1d, 569 .hf_right_step = 0x1d,
569}; 570};
570 571
571static struct twl4030_vibra_data twl6040_vibra = { 572static struct twl6040_vibra_data twl6040_vibra = {
572 .vibldrv_res = 8, 573 .vibldrv_res = 8,
573 .vibrdrv_res = 3, 574 .vibrdrv_res = 3,
574 .viblmotor_res = 10, 575 .viblmotor_res = 10,
@@ -577,16 +578,14 @@ static struct twl4030_vibra_data twl6040_vibra = {
577 .vddvibr_uV = 0, /* fixed volt supply - VBAT */ 578 .vddvibr_uV = 0, /* fixed volt supply - VBAT */
578}; 579};
579 580
580static struct twl4030_audio_data twl6040_audio = { 581static struct twl6040_platform_data twl6040_data = {
581 .codec = &twl6040_codec, 582 .codec = &twl6040_codec,
582 .vibra = &twl6040_vibra, 583 .vibra = &twl6040_vibra,
583 .audpwron_gpio = 127, 584 .audpwron_gpio = 127,
584 .naudint_irq = OMAP44XX_IRQ_SYS_2N,
585 .irq_base = TWL6040_CODEC_IRQ_BASE, 585 .irq_base = TWL6040_CODEC_IRQ_BASE,
586}; 586};
587 587
588static struct twl4030_platform_data sdp4430_twldata = { 588static struct twl4030_platform_data sdp4430_twldata = {
589 .audio = &twl6040_audio,
590 /* Regulators */ 589 /* Regulators */
591 .vusim = &sdp4430_vusim, 590 .vusim = &sdp4430_vusim,
592 .vaux1 = &sdp4430_vaux1, 591 .vaux1 = &sdp4430_vaux1,
@@ -617,7 +616,8 @@ static int __init omap4_i2c_init(void)
617 TWL_COMMON_REGULATOR_VCXIO | 616 TWL_COMMON_REGULATOR_VCXIO |
618 TWL_COMMON_REGULATOR_VUSB | 617 TWL_COMMON_REGULATOR_VUSB |
619 TWL_COMMON_REGULATOR_CLK32KG); 618 TWL_COMMON_REGULATOR_CLK32KG);
620 omap4_pmic_init("twl6030", &sdp4430_twldata); 619 omap4_pmic_init("twl6030", &sdp4430_twldata,
620 &twl6040_data, OMAP44XX_IRQ_SYS_2N);
621 omap_register_i2c_bus(2, 400, NULL, 0); 621 omap_register_i2c_bus(2, 400, NULL, 0);
622 omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, 622 omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
623 ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); 623 ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 74e1687b5170..098d183a0086 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -137,7 +137,7 @@ static struct twl4030_platform_data sdp4430_twldata = {
137 137
138static void __init omap4_i2c_init(void) 138static void __init omap4_i2c_init(void)
139{ 139{
140 omap4_pmic_init("twl6030", &sdp4430_twldata); 140 omap4_pmic_init("twl6030", &sdp4430_twldata, NULL, 0);
141} 141}
142 142
143static void __init omap4_init(void) 143static void __init omap4_init(void)
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index d8c0e89f0126..1b782ba53433 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -25,6 +25,7 @@
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <linux/usb/otg.h> 26#include <linux/usb/otg.h>
27#include <linux/i2c/twl.h> 27#include <linux/i2c/twl.h>
28#include <linux/mfd/twl6040.h>
28#include <linux/regulator/machine.h> 29#include <linux/regulator/machine.h>
29#include <linux/regulator/fixed.h> 30#include <linux/regulator/fixed.h>
30#include <linux/wl12xx.h> 31#include <linux/wl12xx.h>
@@ -284,7 +285,7 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
284 return 0; 285 return 0;
285} 286}
286 287
287static struct twl4030_codec_data twl6040_codec = { 288static struct twl6040_codec_data twl6040_codec = {
288 /* single-step ramp for headset and handsfree */ 289 /* single-step ramp for headset and handsfree */
289 .hs_left_step = 0x0f, 290 .hs_left_step = 0x0f,
290 .hs_right_step = 0x0f, 291 .hs_right_step = 0x0f,
@@ -292,17 +293,14 @@ static struct twl4030_codec_data twl6040_codec = {
292 .hf_right_step = 0x1d, 293 .hf_right_step = 0x1d,
293}; 294};
294 295
295static struct twl4030_audio_data twl6040_audio = { 296static struct twl6040_platform_data twl6040_data = {
296 .codec = &twl6040_codec, 297 .codec = &twl6040_codec,
297 .audpwron_gpio = 127, 298 .audpwron_gpio = 127,
298 .naudint_irq = OMAP44XX_IRQ_SYS_2N,
299 .irq_base = TWL6040_CODEC_IRQ_BASE, 299 .irq_base = TWL6040_CODEC_IRQ_BASE,
300}; 300};
301 301
302/* Panda board uses the common PMIC configuration */ 302/* Panda board uses the common PMIC configuration */
303static struct twl4030_platform_data omap4_panda_twldata = { 303static struct twl4030_platform_data omap4_panda_twldata;
304 .audio = &twl6040_audio,
305};
306 304
307/* 305/*
308 * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM 306 * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
@@ -326,7 +324,8 @@ static int __init omap4_panda_i2c_init(void)
326 TWL_COMMON_REGULATOR_VCXIO | 324 TWL_COMMON_REGULATOR_VCXIO |
327 TWL_COMMON_REGULATOR_VUSB | 325 TWL_COMMON_REGULATOR_VUSB |
328 TWL_COMMON_REGULATOR_CLK32KG); 326 TWL_COMMON_REGULATOR_CLK32KG);
329 omap4_pmic_init("twl6030", &omap4_panda_twldata); 327 omap4_pmic_init("twl6030", &omap4_panda_twldata,
328 &twl6040_data, OMAP44XX_IRQ_SYS_2N);
330 omap_register_i2c_bus(2, 400, NULL, 0); 329 omap_register_i2c_bus(2, 400, NULL, 0);
331 /* 330 /*
332 * Bus 3 is attached to the DVI port where devices like the pico DLP 331 * Bus 3 is attached to the DVI port where devices like the pico DLP
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 2c27fdb61e66..7144ae651d3d 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1422,6 +1422,9 @@ static int _ocp_softreset(struct omap_hwmod *oh)
1422 goto dis_opt_clks; 1422 goto dis_opt_clks;
1423 _write_sysconfig(v, oh); 1423 _write_sysconfig(v, oh);
1424 1424
1425 if (oh->class->sysc->srst_udelay)
1426 udelay(oh->class->sysc->srst_udelay);
1427
1425 if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) 1428 if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
1426 omap_test_timeout((omap_hwmod_read(oh, 1429 omap_test_timeout((omap_hwmod_read(oh,
1427 oh->class->sysc->syss_offs) 1430 oh->class->sysc->syss_offs)
@@ -1903,10 +1906,20 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
1903 */ 1906 */
1904int omap_hwmod_softreset(struct omap_hwmod *oh) 1907int omap_hwmod_softreset(struct omap_hwmod *oh)
1905{ 1908{
1906 if (!oh) 1909 u32 v;
1910 int ret;
1911
1912 if (!oh || !(oh->_sysc_cache))
1907 return -EINVAL; 1913 return -EINVAL;
1908 1914
1909 return _ocp_softreset(oh); 1915 v = oh->_sysc_cache;
1916 ret = _set_softreset(oh, &v);
1917 if (ret)
1918 goto error;
1919 _write_sysconfig(v, oh);
1920
1921error:
1922 return ret;
1910} 1923}
1911 1924
1912/** 1925/**
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a5409ce3f323..a6bde34e443a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -1000,7 +1000,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
1000 .flags = OMAP_FIREWALL_L4, 1000 .flags = OMAP_FIREWALL_L4,
1001 } 1001 }
1002 }, 1002 },
1003 .flags = OCPIF_SWSUP_IDLE,
1004 .user = OCP_USER_MPU | OCP_USER_SDMA, 1003 .user = OCP_USER_MPU | OCP_USER_SDMA,
1005}; 1004};
1006 1005
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index c4f56cb60d7d..04a3885f4475 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -1049,7 +1049,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1049 .slave = &omap2430_dss_venc_hwmod, 1049 .slave = &omap2430_dss_venc_hwmod,
1050 .clk = "dss_ick", 1050 .clk = "dss_ick",
1051 .addr = omap2_dss_venc_addrs, 1051 .addr = omap2_dss_venc_addrs,
1052 .flags = OCPIF_SWSUP_IDLE,
1053 .user = OCP_USER_MPU | OCP_USER_SDMA, 1052 .user = OCP_USER_MPU | OCP_USER_SDMA,
1054}; 1053};
1055 1054
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 34b9766d1d23..db86ce90c69f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1676,7 +1676,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1676 .flags = OMAP_FIREWALL_L4, 1676 .flags = OMAP_FIREWALL_L4,
1677 } 1677 }
1678 }, 1678 },
1679 .flags = OCPIF_SWSUP_IDLE,
1680 .user = OCP_USER_MPU | OCP_USER_SDMA, 1679 .user = OCP_USER_MPU | OCP_USER_SDMA,
1681}; 1680};
1682 1681
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index cc9bd106a854..6abc75753e42 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2594,6 +2594,15 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
2594static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { 2594static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2595 .rev_offs = 0x0000, 2595 .rev_offs = 0x0000,
2596 .sysc_offs = 0x0010, 2596 .sysc_offs = 0x0010,
2597 /*
2598 * ISS needs 100 OCP clk cycles delay after a softreset before
2599 * accessing sysconfig again.
2600 * The lowest frequency at the moment for L3 bus is 100 MHz, so
2601 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
2602 *
2603 * TODO: Indicate errata when available.
2604 */
2605 .srst_udelay = 2,
2597 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | 2606 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2598 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 2607 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2599 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 2608 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 0cdd359a128e..9fc2f44188cb 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -108,8 +108,14 @@ static void omap_uart_set_noidle(struct platform_device *pdev)
108static void omap_uart_set_smartidle(struct platform_device *pdev) 108static void omap_uart_set_smartidle(struct platform_device *pdev)
109{ 109{
110 struct omap_device *od = to_omap_device(pdev); 110 struct omap_device *od = to_omap_device(pdev);
111 u8 idlemode;
111 112
112 omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_SMART); 113 if (od->hwmods[0]->class->sysc->idlemodes & SIDLE_SMART_WKUP)
114 idlemode = HWMOD_IDLEMODE_SMART_WKUP;
115 else
116 idlemode = HWMOD_IDLEMODE_SMART;
117
118 omap_hwmod_set_slave_idlemode(od->hwmods[0], idlemode);
113} 119}
114 120
115#else 121#else
@@ -120,124 +126,8 @@ static void omap_uart_set_smartidle(struct platform_device *pdev) {}
120#endif /* CONFIG_PM */ 126#endif /* CONFIG_PM */
121 127
122#ifdef CONFIG_OMAP_MUX 128#ifdef CONFIG_OMAP_MUX
123static struct omap_device_pad default_uart1_pads[] __initdata = {
124 {
125 .name = "uart1_cts.uart1_cts",
126 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
127 },
128 {
129 .name = "uart1_rts.uart1_rts",
130 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
131 },
132 {
133 .name = "uart1_tx.uart1_tx",
134 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
135 },
136 {
137 .name = "uart1_rx.uart1_rx",
138 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
139 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
140 .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
141 },
142};
143
144static struct omap_device_pad default_uart2_pads[] __initdata = {
145 {
146 .name = "uart2_cts.uart2_cts",
147 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
148 },
149 {
150 .name = "uart2_rts.uart2_rts",
151 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
152 },
153 {
154 .name = "uart2_tx.uart2_tx",
155 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
156 },
157 {
158 .name = "uart2_rx.uart2_rx",
159 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
160 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
161 .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
162 },
163};
164
165static struct omap_device_pad default_uart3_pads[] __initdata = {
166 {
167 .name = "uart3_cts_rctx.uart3_cts_rctx",
168 .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
169 },
170 {
171 .name = "uart3_rts_sd.uart3_rts_sd",
172 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
173 },
174 {
175 .name = "uart3_tx_irtx.uart3_tx_irtx",
176 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
177 },
178 {
179 .name = "uart3_rx_irrx.uart3_rx_irrx",
180 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
181 .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
182 .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
183 },
184};
185
186static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
187 {
188 .name = "gpmc_wait2.uart4_tx",
189 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
190 },
191 {
192 .name = "gpmc_wait3.uart4_rx",
193 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
194 .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
195 .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
196 },
197};
198
199static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
200 {
201 .name = "uart4_tx.uart4_tx",
202 .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
203 },
204 {
205 .name = "uart4_rx.uart4_rx",
206 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
207 .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
208 .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
209 },
210};
211
212static void omap_serial_fill_default_pads(struct omap_board_data *bdata) 129static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
213{ 130{
214 switch (bdata->id) {
215 case 0:
216 bdata->pads = default_uart1_pads;
217 bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
218 break;
219 case 1:
220 bdata->pads = default_uart2_pads;
221 bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
222 break;
223 case 2:
224 bdata->pads = default_uart3_pads;
225 bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
226 break;
227 case 3:
228 if (cpu_is_omap44xx()) {
229 bdata->pads = default_omap4_uart4_pads;
230 bdata->pads_cnt =
231 ARRAY_SIZE(default_omap4_uart4_pads);
232 } else if (cpu_is_omap3630()) {
233 bdata->pads = default_omap36xx_uart4_pads;
234 bdata->pads_cnt =
235 ARRAY_SIZE(default_omap36xx_uart4_pads);
236 }
237 break;
238 default:
239 break;
240 }
241} 131}
242#else 132#else
243static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {} 133static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 4b57757bf9d1..7a7b89304c48 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -37,6 +37,16 @@ static struct i2c_board_info __initdata pmic_i2c_board_info = {
37 .flags = I2C_CLIENT_WAKE, 37 .flags = I2C_CLIENT_WAKE,
38}; 38};
39 39
40static struct i2c_board_info __initdata omap4_i2c1_board_info[] = {
41 {
42 .addr = 0x48,
43 .flags = I2C_CLIENT_WAKE,
44 },
45 {
46 I2C_BOARD_INFO("twl6040", 0x4b),
47 },
48};
49
40void __init omap_pmic_init(int bus, u32 clkrate, 50void __init omap_pmic_init(int bus, u32 clkrate,
41 const char *pmic_type, int pmic_irq, 51 const char *pmic_type, int pmic_irq,
42 struct twl4030_platform_data *pmic_data) 52 struct twl4030_platform_data *pmic_data)
@@ -49,14 +59,31 @@ void __init omap_pmic_init(int bus, u32 clkrate,
49 omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1); 59 omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
50} 60}
51 61
62void __init omap4_pmic_init(const char *pmic_type,
63 struct twl4030_platform_data *pmic_data,
64 struct twl6040_platform_data *twl6040_data, int twl6040_irq)
65{
66 /* PMIC part*/
67 strncpy(omap4_i2c1_board_info[0].type, pmic_type,
68 sizeof(omap4_i2c1_board_info[0].type));
69 omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N;
70 omap4_i2c1_board_info[0].platform_data = pmic_data;
71
72 /* TWL6040 audio IC part */
73 omap4_i2c1_board_info[1].irq = twl6040_irq;
74 omap4_i2c1_board_info[1].platform_data = twl6040_data;
75
76 omap_register_i2c_bus(1, 400, omap4_i2c1_board_info, 2);
77
78}
79
52void __init omap_pmic_late_init(void) 80void __init omap_pmic_late_init(void)
53{ 81{
54 /* Init the OMAP TWL parameters (if PMIC has been registerd) */ 82 /* Init the OMAP TWL parameters (if PMIC has been registerd) */
55 if (!pmic_i2c_board_info.irq) 83 if (pmic_i2c_board_info.irq)
56 return; 84 omap3_twl_init();
57 85 if (omap4_i2c1_board_info[0].irq)
58 omap3_twl_init(); 86 omap4_twl_init();
59 omap4_twl_init();
60} 87}
61 88
62#if defined(CONFIG_ARCH_OMAP3) 89#if defined(CONFIG_ARCH_OMAP3)
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
index 275dde8cb27a..09627483a57f 100644
--- a/arch/arm/mach-omap2/twl-common.h
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -29,6 +29,7 @@
29 29
30 30
31struct twl4030_platform_data; 31struct twl4030_platform_data;
32struct twl6040_platform_data;
32 33
33void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq, 34void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
34 struct twl4030_platform_data *pmic_data); 35 struct twl4030_platform_data *pmic_data);
@@ -46,12 +47,9 @@ static inline void omap3_pmic_init(const char *pmic_type,
46 omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data); 47 omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
47} 48}
48 49
49static inline void omap4_pmic_init(const char *pmic_type, 50void omap4_pmic_init(const char *pmic_type,
50 struct twl4030_platform_data *pmic_data) 51 struct twl4030_platform_data *pmic_data,
51{ 52 struct twl6040_platform_data *audio_data, int twl6040_irq);
52 /* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
53 omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
54}
55 53
56void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, 54void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
57 u32 pdata_flags, u32 regulators_flags); 55 u32 pdata_flags, u32 regulators_flags);
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index d9fe11cb6f16..8bd37291fa4f 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -7,16 +7,19 @@ if ARCH_SPEAR3XX
7menu "SPEAr3xx Implementations" 7menu "SPEAr3xx Implementations"
8config MACH_SPEAR300 8config MACH_SPEAR300
9 bool "SPEAr300 Machine support with Device Tree" 9 bool "SPEAr300 Machine support with Device Tree"
10 select PINCTRL_SPEAR300
10 help 11 help
11 Supports ST SPEAr300 machine configured via the device-tree 12 Supports ST SPEAr300 machine configured via the device-tree
12 13
13config MACH_SPEAR310 14config MACH_SPEAR310
14 bool "SPEAr310 Machine support with Device Tree" 15 bool "SPEAr310 Machine support with Device Tree"
16 select PINCTRL_SPEAR310
15 help 17 help
16 Supports ST SPEAr310 machine configured via the device-tree 18 Supports ST SPEAr310 machine configured via the device-tree
17 19
18config MACH_SPEAR320 20config MACH_SPEAR320
19 bool "SPEAr320 Machine support with Device Tree" 21 bool "SPEAr320 Machine support with Device Tree"
22 select PINCTRL_SPEAR320
20 help 23 help
21 Supports ST SPEAr320 machine configured via the device-tree 24 Supports ST SPEAr320 machine configured via the device-tree
22endmenu 25endmenu
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index 17b5d83cf2d5..8d12faa178fd 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# common files 5# common files
6obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o clock.o 6obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o
7 7
8# spear300 specific files 8# spear300 specific files
9obj-$(CONFIG_MACH_SPEAR300) += spear300.o 9obj-$(CONFIG_MACH_SPEAR300) += spear300.o
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
deleted file mode 100644
index cd6c11099083..000000000000
--- a/arch/arm/mach-spear3xx/clock.c
+++ /dev/null
@@ -1,892 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/clock.c
3 *
4 * SPEAr3xx machines clock framework source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/clkdev.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/of_platform.h>
19#include <asm/mach-types.h>
20#include <plat/clock.h>
21#include <mach/misc_regs.h>
22#include <mach/spear.h>
23
24#define PLL1_CTR (MISC_BASE + 0x008)
25#define PLL1_FRQ (MISC_BASE + 0x00C)
26#define PLL1_MOD (MISC_BASE + 0x010)
27#define PLL2_CTR (MISC_BASE + 0x014)
28/* PLL_CTR register masks */
29#define PLL_ENABLE 2
30#define PLL_MODE_SHIFT 4
31#define PLL_MODE_MASK 0x3
32#define PLL_MODE_NORMAL 0
33#define PLL_MODE_FRACTION 1
34#define PLL_MODE_DITH_DSB 2
35#define PLL_MODE_DITH_SSB 3
36
37#define PLL2_FRQ (MISC_BASE + 0x018)
38/* PLL FRQ register masks */
39#define PLL_DIV_N_SHIFT 0
40#define PLL_DIV_N_MASK 0xFF
41#define PLL_DIV_P_SHIFT 8
42#define PLL_DIV_P_MASK 0x7
43#define PLL_NORM_FDBK_M_SHIFT 24
44#define PLL_NORM_FDBK_M_MASK 0xFF
45#define PLL_DITH_FDBK_M_SHIFT 16
46#define PLL_DITH_FDBK_M_MASK 0xFFFF
47
48#define PLL2_MOD (MISC_BASE + 0x01C)
49#define PLL_CLK_CFG (MISC_BASE + 0x020)
50#define CORE_CLK_CFG (MISC_BASE + 0x024)
51/* CORE CLK CFG register masks */
52#define PLL_HCLK_RATIO_SHIFT 10
53#define PLL_HCLK_RATIO_MASK 0x3
54#define HCLK_PCLK_RATIO_SHIFT 8
55#define HCLK_PCLK_RATIO_MASK 0x3
56
57#define PERIP_CLK_CFG (MISC_BASE + 0x028)
58/* PERIP_CLK_CFG register masks */
59#define UART_CLK_SHIFT 4
60#define UART_CLK_MASK 0x1
61#define FIRDA_CLK_SHIFT 5
62#define FIRDA_CLK_MASK 0x3
63#define GPT0_CLK_SHIFT 8
64#define GPT1_CLK_SHIFT 11
65#define GPT2_CLK_SHIFT 12
66#define GPT_CLK_MASK 0x1
67#define AUX_CLK_PLL3_VAL 0
68#define AUX_CLK_PLL1_VAL 1
69
70#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
71/* PERIP1_CLK_ENB register masks */
72#define UART_CLK_ENB 3
73#define SSP_CLK_ENB 5
74#define I2C_CLK_ENB 7
75#define JPEG_CLK_ENB 8
76#define FIRDA_CLK_ENB 10
77#define GPT1_CLK_ENB 11
78#define GPT2_CLK_ENB 12
79#define ADC_CLK_ENB 15
80#define RTC_CLK_ENB 17
81#define GPIO_CLK_ENB 18
82#define DMA_CLK_ENB 19
83#define SMI_CLK_ENB 21
84#define GMAC_CLK_ENB 23
85#define USBD_CLK_ENB 24
86#define USBH_CLK_ENB 25
87#define C3_CLK_ENB 31
88
89#define RAS_CLK_ENB (MISC_BASE + 0x034)
90
91#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
92#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
93#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
94/* gpt synthesizer register masks */
95#define GPT_MSCALE_SHIFT 0
96#define GPT_MSCALE_MASK 0xFFF
97#define GPT_NSCALE_SHIFT 12
98#define GPT_NSCALE_MASK 0xF
99
100#define AMEM_CLK_CFG (MISC_BASE + 0x050)
101#define EXPI_CLK_CFG (MISC_BASE + 0x054)
102#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
103#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
104#define UART_CLK_SYNT (MISC_BASE + 0x064)
105#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
106#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
107#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
108#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
109#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
110/* aux clk synthesiser register masks for irda to ras4 */
111#define AUX_SYNT_ENB 31
112#define AUX_EQ_SEL_SHIFT 30
113#define AUX_EQ_SEL_MASK 1
114#define AUX_EQ1_SEL 0
115#define AUX_EQ2_SEL 1
116#define AUX_XSCALE_SHIFT 16
117#define AUX_XSCALE_MASK 0xFFF
118#define AUX_YSCALE_SHIFT 0
119#define AUX_YSCALE_MASK 0xFFF
120
121/* root clks */
122/* 32 KHz oscillator clock */
123static struct clk osc_32k_clk = {
124 .flags = ALWAYS_ENABLED,
125 .rate = 32000,
126};
127
128/* 24 MHz oscillator clock */
129static struct clk osc_24m_clk = {
130 .flags = ALWAYS_ENABLED,
131 .rate = 24000000,
132};
133
134/* clock derived from 32 KHz osc clk */
135/* rtc clock */
136static struct clk rtc_clk = {
137 .pclk = &osc_32k_clk,
138 .en_reg = PERIP1_CLK_ENB,
139 .en_reg_bit = RTC_CLK_ENB,
140 .recalc = &follow_parent,
141};
142
143/* clock derived from 24 MHz osc clk */
144/* pll masks structure */
145static struct pll_clk_masks pll1_masks = {
146 .mode_mask = PLL_MODE_MASK,
147 .mode_shift = PLL_MODE_SHIFT,
148 .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
149 .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
150 .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
151 .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
152 .div_p_mask = PLL_DIV_P_MASK,
153 .div_p_shift = PLL_DIV_P_SHIFT,
154 .div_n_mask = PLL_DIV_N_MASK,
155 .div_n_shift = PLL_DIV_N_SHIFT,
156};
157
158/* pll1 configuration structure */
159static struct pll_clk_config pll1_config = {
160 .mode_reg = PLL1_CTR,
161 .cfg_reg = PLL1_FRQ,
162 .masks = &pll1_masks,
163};
164
165/* pll rate configuration table, in ascending order of rates */
166struct pll_rate_tbl pll_rtbl[] = {
167 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
168 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
169};
170
171/* PLL1 clock */
172static struct clk pll1_clk = {
173 .flags = ENABLED_ON_INIT,
174 .pclk = &osc_24m_clk,
175 .en_reg = PLL1_CTR,
176 .en_reg_bit = PLL_ENABLE,
177 .calc_rate = &pll_calc_rate,
178 .recalc = &pll_clk_recalc,
179 .set_rate = &pll_clk_set_rate,
180 .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
181 .private_data = &pll1_config,
182};
183
184/* PLL3 48 MHz clock */
185static struct clk pll3_48m_clk = {
186 .flags = ALWAYS_ENABLED,
187 .pclk = &osc_24m_clk,
188 .rate = 48000000,
189};
190
191/* watch dog timer clock */
192static struct clk wdt_clk = {
193 .flags = ALWAYS_ENABLED,
194 .pclk = &osc_24m_clk,
195 .recalc = &follow_parent,
196};
197
198/* clock derived from pll1 clk */
199/* cpu clock */
200static struct clk cpu_clk = {
201 .flags = ALWAYS_ENABLED,
202 .pclk = &pll1_clk,
203 .recalc = &follow_parent,
204};
205
206/* ahb masks structure */
207static struct bus_clk_masks ahb_masks = {
208 .mask = PLL_HCLK_RATIO_MASK,
209 .shift = PLL_HCLK_RATIO_SHIFT,
210};
211
212/* ahb configuration structure */
213static struct bus_clk_config ahb_config = {
214 .reg = CORE_CLK_CFG,
215 .masks = &ahb_masks,
216};
217
218/* ahb rate configuration table, in ascending order of rates */
219struct bus_rate_tbl bus_rtbl[] = {
220 {.div = 3}, /* == parent divided by 4 */
221 {.div = 2}, /* == parent divided by 3 */
222 {.div = 1}, /* == parent divided by 2 */
223 {.div = 0}, /* == parent divided by 1 */
224};
225
226/* ahb clock */
227static struct clk ahb_clk = {
228 .flags = ALWAYS_ENABLED,
229 .pclk = &pll1_clk,
230 .calc_rate = &bus_calc_rate,
231 .recalc = &bus_clk_recalc,
232 .set_rate = &bus_clk_set_rate,
233 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
234 .private_data = &ahb_config,
235};
236
237/* auxiliary synthesizers masks */
238static struct aux_clk_masks aux_masks = {
239 .eq_sel_mask = AUX_EQ_SEL_MASK,
240 .eq_sel_shift = AUX_EQ_SEL_SHIFT,
241 .eq1_mask = AUX_EQ1_SEL,
242 .eq2_mask = AUX_EQ2_SEL,
243 .xscale_sel_mask = AUX_XSCALE_MASK,
244 .xscale_sel_shift = AUX_XSCALE_SHIFT,
245 .yscale_sel_mask = AUX_YSCALE_MASK,
246 .yscale_sel_shift = AUX_YSCALE_SHIFT,
247};
248
249/* uart synth configurations */
250static struct aux_clk_config uart_synth_config = {
251 .synth_reg = UART_CLK_SYNT,
252 .masks = &aux_masks,
253};
254
255/* aux rate configuration table, in ascending order of rates */
256struct aux_rate_tbl aux_rtbl[] = {
257 /* For PLL1 = 332 MHz */
258 {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
259 {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
260 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
261};
262
263/* uart synth clock */
264static struct clk uart_synth_clk = {
265 .en_reg = UART_CLK_SYNT,
266 .en_reg_bit = AUX_SYNT_ENB,
267 .pclk = &pll1_clk,
268 .calc_rate = &aux_calc_rate,
269 .recalc = &aux_clk_recalc,
270 .set_rate = &aux_clk_set_rate,
271 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
272 .private_data = &uart_synth_config,
273};
274
275/* uart parents */
276static struct pclk_info uart_pclk_info[] = {
277 {
278 .pclk = &uart_synth_clk,
279 .pclk_val = AUX_CLK_PLL1_VAL,
280 }, {
281 .pclk = &pll3_48m_clk,
282 .pclk_val = AUX_CLK_PLL3_VAL,
283 },
284};
285
286/* uart parent select structure */
287static struct pclk_sel uart_pclk_sel = {
288 .pclk_info = uart_pclk_info,
289 .pclk_count = ARRAY_SIZE(uart_pclk_info),
290 .pclk_sel_reg = PERIP_CLK_CFG,
291 .pclk_sel_mask = UART_CLK_MASK,
292};
293
294/* uart clock */
295static struct clk uart_clk = {
296 .en_reg = PERIP1_CLK_ENB,
297 .en_reg_bit = UART_CLK_ENB,
298 .pclk_sel = &uart_pclk_sel,
299 .pclk_sel_shift = UART_CLK_SHIFT,
300 .recalc = &follow_parent,
301};
302
303/* firda configurations */
304static struct aux_clk_config firda_synth_config = {
305 .synth_reg = FIRDA_CLK_SYNT,
306 .masks = &aux_masks,
307};
308
309/* firda synth clock */
310static struct clk firda_synth_clk = {
311 .en_reg = FIRDA_CLK_SYNT,
312 .en_reg_bit = AUX_SYNT_ENB,
313 .pclk = &pll1_clk,
314 .calc_rate = &aux_calc_rate,
315 .recalc = &aux_clk_recalc,
316 .set_rate = &aux_clk_set_rate,
317 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
318 .private_data = &firda_synth_config,
319};
320
321/* firda parents */
322static struct pclk_info firda_pclk_info[] = {
323 {
324 .pclk = &firda_synth_clk,
325 .pclk_val = AUX_CLK_PLL1_VAL,
326 }, {
327 .pclk = &pll3_48m_clk,
328 .pclk_val = AUX_CLK_PLL3_VAL,
329 },
330};
331
332/* firda parent select structure */
333static struct pclk_sel firda_pclk_sel = {
334 .pclk_info = firda_pclk_info,
335 .pclk_count = ARRAY_SIZE(firda_pclk_info),
336 .pclk_sel_reg = PERIP_CLK_CFG,
337 .pclk_sel_mask = FIRDA_CLK_MASK,
338};
339
340/* firda clock */
341static struct clk firda_clk = {
342 .en_reg = PERIP1_CLK_ENB,
343 .en_reg_bit = FIRDA_CLK_ENB,
344 .pclk_sel = &firda_pclk_sel,
345 .pclk_sel_shift = FIRDA_CLK_SHIFT,
346 .recalc = &follow_parent,
347};
348
349/* gpt synthesizer masks */
350static struct gpt_clk_masks gpt_masks = {
351 .mscale_sel_mask = GPT_MSCALE_MASK,
352 .mscale_sel_shift = GPT_MSCALE_SHIFT,
353 .nscale_sel_mask = GPT_NSCALE_MASK,
354 .nscale_sel_shift = GPT_NSCALE_SHIFT,
355};
356
357/* gpt rate configuration table, in ascending order of rates */
358struct gpt_rate_tbl gpt_rtbl[] = {
359 /* For pll1 = 332 MHz */
360 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
361 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
362 {.mscale = 1, .nscale = 0}, /* 83 MHz */
363};
364
365/* gpt0 synth clk config*/
366static struct gpt_clk_config gpt0_synth_config = {
367 .synth_reg = PRSC1_CLK_CFG,
368 .masks = &gpt_masks,
369};
370
371/* gpt synth clock */
372static struct clk gpt0_synth_clk = {
373 .flags = ALWAYS_ENABLED,
374 .pclk = &pll1_clk,
375 .calc_rate = &gpt_calc_rate,
376 .recalc = &gpt_clk_recalc,
377 .set_rate = &gpt_clk_set_rate,
378 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
379 .private_data = &gpt0_synth_config,
380};
381
382/* gpt parents */
383static struct pclk_info gpt0_pclk_info[] = {
384 {
385 .pclk = &gpt0_synth_clk,
386 .pclk_val = AUX_CLK_PLL1_VAL,
387 }, {
388 .pclk = &pll3_48m_clk,
389 .pclk_val = AUX_CLK_PLL3_VAL,
390 },
391};
392
393/* gpt parent select structure */
394static struct pclk_sel gpt0_pclk_sel = {
395 .pclk_info = gpt0_pclk_info,
396 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
397 .pclk_sel_reg = PERIP_CLK_CFG,
398 .pclk_sel_mask = GPT_CLK_MASK,
399};
400
401/* gpt0 timer clock */
402static struct clk gpt0_clk = {
403 .flags = ALWAYS_ENABLED,
404 .pclk_sel = &gpt0_pclk_sel,
405 .pclk_sel_shift = GPT0_CLK_SHIFT,
406 .recalc = &follow_parent,
407};
408
409/* gpt1 synth clk configurations */
410static struct gpt_clk_config gpt1_synth_config = {
411 .synth_reg = PRSC2_CLK_CFG,
412 .masks = &gpt_masks,
413};
414
415/* gpt1 synth clock */
416static struct clk gpt1_synth_clk = {
417 .flags = ALWAYS_ENABLED,
418 .pclk = &pll1_clk,
419 .calc_rate = &gpt_calc_rate,
420 .recalc = &gpt_clk_recalc,
421 .set_rate = &gpt_clk_set_rate,
422 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
423 .private_data = &gpt1_synth_config,
424};
425
426static struct pclk_info gpt1_pclk_info[] = {
427 {
428 .pclk = &gpt1_synth_clk,
429 .pclk_val = AUX_CLK_PLL1_VAL,
430 }, {
431 .pclk = &pll3_48m_clk,
432 .pclk_val = AUX_CLK_PLL3_VAL,
433 },
434};
435
436/* gpt parent select structure */
437static struct pclk_sel gpt1_pclk_sel = {
438 .pclk_info = gpt1_pclk_info,
439 .pclk_count = ARRAY_SIZE(gpt1_pclk_info),
440 .pclk_sel_reg = PERIP_CLK_CFG,
441 .pclk_sel_mask = GPT_CLK_MASK,
442};
443
444/* gpt1 timer clock */
445static struct clk gpt1_clk = {
446 .en_reg = PERIP1_CLK_ENB,
447 .en_reg_bit = GPT1_CLK_ENB,
448 .pclk_sel = &gpt1_pclk_sel,
449 .pclk_sel_shift = GPT1_CLK_SHIFT,
450 .recalc = &follow_parent,
451};
452
453/* gpt2 synth clk configurations */
454static struct gpt_clk_config gpt2_synth_config = {
455 .synth_reg = PRSC3_CLK_CFG,
456 .masks = &gpt_masks,
457};
458
459/* gpt1 synth clock */
460static struct clk gpt2_synth_clk = {
461 .flags = ALWAYS_ENABLED,
462 .pclk = &pll1_clk,
463 .calc_rate = &gpt_calc_rate,
464 .recalc = &gpt_clk_recalc,
465 .set_rate = &gpt_clk_set_rate,
466 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
467 .private_data = &gpt2_synth_config,
468};
469
470static struct pclk_info gpt2_pclk_info[] = {
471 {
472 .pclk = &gpt2_synth_clk,
473 .pclk_val = AUX_CLK_PLL1_VAL,
474 }, {
475 .pclk = &pll3_48m_clk,
476 .pclk_val = AUX_CLK_PLL3_VAL,
477 },
478};
479
480/* gpt parent select structure */
481static struct pclk_sel gpt2_pclk_sel = {
482 .pclk_info = gpt2_pclk_info,
483 .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
484 .pclk_sel_reg = PERIP_CLK_CFG,
485 .pclk_sel_mask = GPT_CLK_MASK,
486};
487
488/* gpt2 timer clock */
489static struct clk gpt2_clk = {
490 .en_reg = PERIP1_CLK_ENB,
491 .en_reg_bit = GPT2_CLK_ENB,
492 .pclk_sel = &gpt2_pclk_sel,
493 .pclk_sel_shift = GPT2_CLK_SHIFT,
494 .recalc = &follow_parent,
495};
496
497/* clock derived from pll3 clk */
498/* usbh clock */
499static struct clk usbh_clk = {
500 .pclk = &pll3_48m_clk,
501 .en_reg = PERIP1_CLK_ENB,
502 .en_reg_bit = USBH_CLK_ENB,
503 .recalc = &follow_parent,
504};
505
506/* usbd clock */
507static struct clk usbd_clk = {
508 .pclk = &pll3_48m_clk,
509 .en_reg = PERIP1_CLK_ENB,
510 .en_reg_bit = USBD_CLK_ENB,
511 .recalc = &follow_parent,
512};
513
514/* clock derived from usbh clk */
515/* usbh0 clock */
516static struct clk usbh0_clk = {
517 .flags = ALWAYS_ENABLED,
518 .pclk = &usbh_clk,
519 .recalc = &follow_parent,
520};
521
522/* usbh1 clock */
523static struct clk usbh1_clk = {
524 .flags = ALWAYS_ENABLED,
525 .pclk = &usbh_clk,
526 .recalc = &follow_parent,
527};
528
529/* clock derived from ahb clk */
530/* apb masks structure */
531static struct bus_clk_masks apb_masks = {
532 .mask = HCLK_PCLK_RATIO_MASK,
533 .shift = HCLK_PCLK_RATIO_SHIFT,
534};
535
536/* apb configuration structure */
537static struct bus_clk_config apb_config = {
538 .reg = CORE_CLK_CFG,
539 .masks = &apb_masks,
540};
541
542/* apb clock */
543static struct clk apb_clk = {
544 .flags = ALWAYS_ENABLED,
545 .pclk = &ahb_clk,
546 .calc_rate = &bus_calc_rate,
547 .recalc = &bus_clk_recalc,
548 .set_rate = &bus_clk_set_rate,
549 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
550 .private_data = &apb_config,
551};
552
553/* i2c clock */
554static struct clk i2c_clk = {
555 .pclk = &ahb_clk,
556 .en_reg = PERIP1_CLK_ENB,
557 .en_reg_bit = I2C_CLK_ENB,
558 .recalc = &follow_parent,
559};
560
561/* dma clock */
562static struct clk dma_clk = {
563 .pclk = &ahb_clk,
564 .en_reg = PERIP1_CLK_ENB,
565 .en_reg_bit = DMA_CLK_ENB,
566 .recalc = &follow_parent,
567};
568
569/* jpeg clock */
570static struct clk jpeg_clk = {
571 .pclk = &ahb_clk,
572 .en_reg = PERIP1_CLK_ENB,
573 .en_reg_bit = JPEG_CLK_ENB,
574 .recalc = &follow_parent,
575};
576
577/* gmac clock */
578static struct clk gmac_clk = {
579 .pclk = &ahb_clk,
580 .en_reg = PERIP1_CLK_ENB,
581 .en_reg_bit = GMAC_CLK_ENB,
582 .recalc = &follow_parent,
583};
584
585/* smi clock */
586static struct clk smi_clk = {
587 .pclk = &ahb_clk,
588 .en_reg = PERIP1_CLK_ENB,
589 .en_reg_bit = SMI_CLK_ENB,
590 .recalc = &follow_parent,
591};
592
593/* c3 clock */
594static struct clk c3_clk = {
595 .pclk = &ahb_clk,
596 .en_reg = PERIP1_CLK_ENB,
597 .en_reg_bit = C3_CLK_ENB,
598 .recalc = &follow_parent,
599};
600
601/* clock derived from apb clk */
602/* adc clock */
603static struct clk adc_clk = {
604 .pclk = &apb_clk,
605 .en_reg = PERIP1_CLK_ENB,
606 .en_reg_bit = ADC_CLK_ENB,
607 .recalc = &follow_parent,
608};
609
610#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
611/* emi clock */
612static struct clk emi_clk = {
613 .flags = ALWAYS_ENABLED,
614 .pclk = &ahb_clk,
615 .recalc = &follow_parent,
616};
617#endif
618
619/* ssp clock */
620static struct clk ssp0_clk = {
621 .pclk = &apb_clk,
622 .en_reg = PERIP1_CLK_ENB,
623 .en_reg_bit = SSP_CLK_ENB,
624 .recalc = &follow_parent,
625};
626
627/* gpio clock */
628static struct clk gpio_clk = {
629 .pclk = &apb_clk,
630 .en_reg = PERIP1_CLK_ENB,
631 .en_reg_bit = GPIO_CLK_ENB,
632 .recalc = &follow_parent,
633};
634
635static struct clk dummy_apb_pclk;
636
637#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
638 defined(CONFIG_MACH_SPEAR320)
639/* fsmc clock */
640static struct clk fsmc_clk = {
641 .flags = ALWAYS_ENABLED,
642 .pclk = &ahb_clk,
643 .recalc = &follow_parent,
644};
645#endif
646
647/* common clocks to spear310 and spear320 */
648#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
649/* uart1 clock */
650static struct clk uart1_clk = {
651 .flags = ALWAYS_ENABLED,
652 .pclk = &apb_clk,
653 .recalc = &follow_parent,
654};
655
656/* uart2 clock */
657static struct clk uart2_clk = {
658 .flags = ALWAYS_ENABLED,
659 .pclk = &apb_clk,
660 .recalc = &follow_parent,
661};
662#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
663
664/* common clocks to spear300 and spear320 */
665#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
666/* clcd clock */
667static struct clk clcd_clk = {
668 .flags = ALWAYS_ENABLED,
669 .pclk = &pll3_48m_clk,
670 .recalc = &follow_parent,
671};
672
673/* sdhci clock */
674static struct clk sdhci_clk = {
675 .flags = ALWAYS_ENABLED,
676 .pclk = &ahb_clk,
677 .recalc = &follow_parent,
678};
679#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
680
681/* spear300 machine specific clock structures */
682#ifdef CONFIG_MACH_SPEAR300
683/* gpio1 clock */
684static struct clk gpio1_clk = {
685 .flags = ALWAYS_ENABLED,
686 .pclk = &apb_clk,
687 .recalc = &follow_parent,
688};
689
690/* keyboard clock */
691static struct clk kbd_clk = {
692 .flags = ALWAYS_ENABLED,
693 .pclk = &apb_clk,
694 .recalc = &follow_parent,
695};
696
697#endif
698
699/* spear310 machine specific clock structures */
700#ifdef CONFIG_MACH_SPEAR310
701/* uart3 clock */
702static struct clk uart3_clk = {
703 .flags = ALWAYS_ENABLED,
704 .pclk = &apb_clk,
705 .recalc = &follow_parent,
706};
707
708/* uart4 clock */
709static struct clk uart4_clk = {
710 .flags = ALWAYS_ENABLED,
711 .pclk = &apb_clk,
712 .recalc = &follow_parent,
713};
714
715/* uart5 clock */
716static struct clk uart5_clk = {
717 .flags = ALWAYS_ENABLED,
718 .pclk = &apb_clk,
719 .recalc = &follow_parent,
720};
721#endif
722
723/* spear320 machine specific clock structures */
724#ifdef CONFIG_MACH_SPEAR320
725/* can0 clock */
726static struct clk can0_clk = {
727 .flags = ALWAYS_ENABLED,
728 .pclk = &apb_clk,
729 .recalc = &follow_parent,
730};
731
732/* can1 clock */
733static struct clk can1_clk = {
734 .flags = ALWAYS_ENABLED,
735 .pclk = &apb_clk,
736 .recalc = &follow_parent,
737};
738
739/* i2c1 clock */
740static struct clk i2c1_clk = {
741 .flags = ALWAYS_ENABLED,
742 .pclk = &ahb_clk,
743 .recalc = &follow_parent,
744};
745
746/* ssp1 clock */
747static struct clk ssp1_clk = {
748 .flags = ALWAYS_ENABLED,
749 .pclk = &apb_clk,
750 .recalc = &follow_parent,
751};
752
753/* ssp2 clock */
754static struct clk ssp2_clk = {
755 .flags = ALWAYS_ENABLED,
756 .pclk = &apb_clk,
757 .recalc = &follow_parent,
758};
759
760/* pwm clock */
761static struct clk pwm_clk = {
762 .flags = ALWAYS_ENABLED,
763 .pclk = &apb_clk,
764 .recalc = &follow_parent,
765};
766#endif
767
768/* array of all spear 3xx clock lookups */
769static struct clk_lookup spear_clk_lookups[] = {
770 CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
771 /* root clks */
772 CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
773 CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk),
774 /* clock derived from 32 KHz osc clk */
775 CLKDEV_INIT("fc900000.rtc", NULL, &rtc_clk),
776 /* clock derived from 24 MHz osc clk */
777 CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
778 CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
779 CLKDEV_INIT("fc880000.wdt", NULL, &wdt_clk),
780 /* clock derived from pll1 clk */
781 CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
782 CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
783 CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
784 CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
785 CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
786 CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk),
787 CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
788 CLKDEV_INIT("d0000000.serial", NULL, &uart_clk),
789 CLKDEV_INIT("firda", NULL, &firda_clk),
790 CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
791 CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
792 CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
793 /* clock derived from pll3 clk */
794 CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
795 CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk),
796 /* clock derived from usbh clk */
797 CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
798 CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
799 /* clock derived from ahb clk */
800 CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
801 CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk),
802 CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
803 CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
804 CLKDEV_INIT("e0800000.eth", NULL, &gmac_clk),
805 CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
806 CLKDEV_INIT("c3", NULL, &c3_clk),
807 /* clock derived from apb clk */
808 CLKDEV_INIT("adc", NULL, &adc_clk),
809 CLKDEV_INIT("d0100000.spi", NULL, &ssp0_clk),
810 CLKDEV_INIT("fc980000.gpio", NULL, &gpio_clk),
811};
812
813/* array of all spear 300 clock lookups */
814#ifdef CONFIG_MACH_SPEAR300
815static struct clk_lookup spear300_clk_lookups[] = {
816 CLKDEV_INIT("60000000.clcd", NULL, &clcd_clk),
817 CLKDEV_INIT("94000000.flash", NULL, &fsmc_clk),
818 CLKDEV_INIT("a9000000.gpio", NULL, &gpio1_clk),
819 CLKDEV_INIT("a0000000.kbd", NULL, &kbd_clk),
820 CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
821};
822
823void __init spear300_clk_init(void)
824{
825 int i;
826
827 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
828 clk_register(&spear_clk_lookups[i]);
829
830 for (i = 0; i < ARRAY_SIZE(spear300_clk_lookups); i++)
831 clk_register(&spear300_clk_lookups[i]);
832
833 clk_init();
834}
835#endif
836
837/* array of all spear 310 clock lookups */
838#ifdef CONFIG_MACH_SPEAR310
839static struct clk_lookup spear310_clk_lookups[] = {
840 CLKDEV_INIT("44000000.flash", NULL, &fsmc_clk),
841 CLKDEV_INIT(NULL, "emi", &emi_clk),
842 CLKDEV_INIT("b2000000.serial", NULL, &uart1_clk),
843 CLKDEV_INIT("b2080000.serial", NULL, &uart2_clk),
844 CLKDEV_INIT("b2100000.serial", NULL, &uart3_clk),
845 CLKDEV_INIT("b2180000.serial", NULL, &uart4_clk),
846 CLKDEV_INIT("b2200000.serial", NULL, &uart5_clk),
847};
848
849void __init spear310_clk_init(void)
850{
851 int i;
852
853 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
854 clk_register(&spear_clk_lookups[i]);
855
856 for (i = 0; i < ARRAY_SIZE(spear310_clk_lookups); i++)
857 clk_register(&spear310_clk_lookups[i]);
858
859 clk_init();
860}
861#endif
862
863/* array of all spear 320 clock lookups */
864#ifdef CONFIG_MACH_SPEAR320
865static struct clk_lookup spear320_clk_lookups[] = {
866 CLKDEV_INIT("90000000.clcd", NULL, &clcd_clk),
867 CLKDEV_INIT("4c000000.flash", NULL, &fsmc_clk),
868 CLKDEV_INIT("a7000000.i2c", NULL, &i2c1_clk),
869 CLKDEV_INIT(NULL, "emi", &emi_clk),
870 CLKDEV_INIT("pwm", NULL, &pwm_clk),
871 CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
872 CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk),
873 CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk),
874 CLKDEV_INIT("a5000000.spi", NULL, &ssp1_clk),
875 CLKDEV_INIT("a6000000.spi", NULL, &ssp2_clk),
876 CLKDEV_INIT("a3000000.serial", NULL, &uart1_clk),
877 CLKDEV_INIT("a4000000.serial", NULL, &uart2_clk),
878};
879
880void __init spear320_clk_init(void)
881{
882 int i;
883
884 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
885 clk_register(&spear_clk_lookups[i]);
886
887 for (i = 0; i < ARRAY_SIZE(spear320_clk_lookups); i++)
888 clk_register(&spear320_clk_lookups[i]);
889
890 clk_init();
891}
892#endif
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index efb69357429a..4a95b9453c2a 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -20,7 +20,6 @@
20#include <linux/amba/bus.h> 20#include <linux/amba/bus.h>
21#include <asm/mach/time.h> 21#include <asm/mach/time.h>
22#include <asm/mach/map.h> 22#include <asm/mach/map.h>
23#include <plat/padmux.h>
24 23
25/* Add spear3xx family device structure declarations here */ 24/* Add spear3xx family device structure declarations here */
26extern struct sys_timer spear3xx_timer; 25extern struct sys_timer spear3xx_timer;
@@ -29,154 +28,10 @@ extern struct pl08x_platform_data pl080_plat_data;
29 28
30/* Add spear3xx family function declarations here */ 29/* Add spear3xx family function declarations here */
31void __init spear_setup_of_timer(void); 30void __init spear_setup_of_timer(void);
31void __init spear3xx_clk_init(void);
32void __init spear3xx_map_io(void); 32void __init spear3xx_map_io(void);
33void __init spear3xx_dt_init_irq(void); 33void __init spear3xx_dt_init_irq(void);
34 34
35void spear_restart(char, const char *); 35void spear_restart(char, const char *);
36 36
37/* pad mux declarations */
38#define PMX_FIRDA_MASK (1 << 14)
39#define PMX_I2C_MASK (1 << 13)
40#define PMX_SSP_CS_MASK (1 << 12)
41#define PMX_SSP_MASK (1 << 11)
42#define PMX_MII_MASK (1 << 10)
43#define PMX_GPIO_PIN0_MASK (1 << 9)
44#define PMX_GPIO_PIN1_MASK (1 << 8)
45#define PMX_GPIO_PIN2_MASK (1 << 7)
46#define PMX_GPIO_PIN3_MASK (1 << 6)
47#define PMX_GPIO_PIN4_MASK (1 << 5)
48#define PMX_GPIO_PIN5_MASK (1 << 4)
49#define PMX_UART0_MODEM_MASK (1 << 3)
50#define PMX_UART0_MASK (1 << 2)
51#define PMX_TIMER_3_4_MASK (1 << 1)
52#define PMX_TIMER_1_2_MASK (1 << 0)
53
54/* pad mux devices */
55extern struct pmx_dev spear3xx_pmx_firda;
56extern struct pmx_dev spear3xx_pmx_i2c;
57extern struct pmx_dev spear3xx_pmx_ssp_cs;
58extern struct pmx_dev spear3xx_pmx_ssp;
59extern struct pmx_dev spear3xx_pmx_mii;
60extern struct pmx_dev spear3xx_pmx_gpio_pin0;
61extern struct pmx_dev spear3xx_pmx_gpio_pin1;
62extern struct pmx_dev spear3xx_pmx_gpio_pin2;
63extern struct pmx_dev spear3xx_pmx_gpio_pin3;
64extern struct pmx_dev spear3xx_pmx_gpio_pin4;
65extern struct pmx_dev spear3xx_pmx_gpio_pin5;
66extern struct pmx_dev spear3xx_pmx_uart0_modem;
67extern struct pmx_dev spear3xx_pmx_uart0;
68extern struct pmx_dev spear3xx_pmx_timer_3_4;
69extern struct pmx_dev spear3xx_pmx_timer_1_2;
70
71#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
72/* padmux plgpio devices */
73extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
74extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
75extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
76extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
77extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
78extern struct pmx_dev spear3xx_pmx_plgpio_28;
79extern struct pmx_dev spear3xx_pmx_plgpio_29;
80extern struct pmx_dev spear3xx_pmx_plgpio_30;
81extern struct pmx_dev spear3xx_pmx_plgpio_31;
82extern struct pmx_dev spear3xx_pmx_plgpio_32;
83extern struct pmx_dev spear3xx_pmx_plgpio_33;
84extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
85extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
86extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
87extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
88#endif
89
90/* spear300 declarations */
91#ifdef CONFIG_MACH_SPEAR300
92/* pad mux modes */
93extern struct pmx_mode spear300_nand_mode;
94extern struct pmx_mode spear300_nor_mode;
95extern struct pmx_mode spear300_photo_frame_mode;
96extern struct pmx_mode spear300_lend_ip_phone_mode;
97extern struct pmx_mode spear300_hend_ip_phone_mode;
98extern struct pmx_mode spear300_lend_wifi_phone_mode;
99extern struct pmx_mode spear300_hend_wifi_phone_mode;
100extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
101extern struct pmx_mode spear300_ata_pabx_i2s_mode;
102extern struct pmx_mode spear300_caml_lcdw_mode;
103extern struct pmx_mode spear300_camu_lcd_mode;
104extern struct pmx_mode spear300_camu_wlcd_mode;
105extern struct pmx_mode spear300_caml_lcd_mode;
106
107/* pad mux devices */
108extern struct pmx_dev spear300_pmx_fsmc_2_chips;
109extern struct pmx_dev spear300_pmx_fsmc_4_chips;
110extern struct pmx_dev spear300_pmx_keyboard;
111extern struct pmx_dev spear300_pmx_clcd;
112extern struct pmx_dev spear300_pmx_telecom_gpio;
113extern struct pmx_dev spear300_pmx_telecom_tdm;
114extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
115extern struct pmx_dev spear300_pmx_telecom_camera;
116extern struct pmx_dev spear300_pmx_telecom_dac;
117extern struct pmx_dev spear300_pmx_telecom_i2s;
118extern struct pmx_dev spear300_pmx_telecom_boot_pins;
119extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
120extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
121extern struct pmx_dev spear300_pmx_gpio1;
122
123/* Add spear300 machine declarations here */
124void __init spear300_clk_init(void);
125
126#endif /* CONFIG_MACH_SPEAR300 */
127
128/* spear310 declarations */
129#ifdef CONFIG_MACH_SPEAR310
130/* pad mux devices */
131extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
132extern struct pmx_dev spear310_pmx_emi_cs_2_3;
133extern struct pmx_dev spear310_pmx_uart1;
134extern struct pmx_dev spear310_pmx_uart2;
135extern struct pmx_dev spear310_pmx_uart3_4_5;
136extern struct pmx_dev spear310_pmx_fsmc;
137extern struct pmx_dev spear310_pmx_rs485_0_1;
138extern struct pmx_dev spear310_pmx_tdm0;
139
140/* Add spear310 machine declarations here */
141void __init spear310_clk_init(void);
142
143#endif /* CONFIG_MACH_SPEAR310 */
144
145/* spear320 declarations */
146#ifdef CONFIG_MACH_SPEAR320
147/* pad mux modes */
148extern struct pmx_mode spear320_auto_net_smii_mode;
149extern struct pmx_mode spear320_auto_net_mii_mode;
150extern struct pmx_mode spear320_auto_exp_mode;
151extern struct pmx_mode spear320_small_printers_mode;
152
153/* pad mux devices */
154extern struct pmx_dev spear320_pmx_clcd;
155extern struct pmx_dev spear320_pmx_emi;
156extern struct pmx_dev spear320_pmx_fsmc;
157extern struct pmx_dev spear320_pmx_spp;
158extern struct pmx_dev spear320_pmx_sdhci;
159extern struct pmx_dev spear320_pmx_i2s;
160extern struct pmx_dev spear320_pmx_uart1;
161extern struct pmx_dev spear320_pmx_uart1_modem;
162extern struct pmx_dev spear320_pmx_uart2;
163extern struct pmx_dev spear320_pmx_touchscreen;
164extern struct pmx_dev spear320_pmx_can;
165extern struct pmx_dev spear320_pmx_sdhci_led;
166extern struct pmx_dev spear320_pmx_pwm0;
167extern struct pmx_dev spear320_pmx_pwm1;
168extern struct pmx_dev spear320_pmx_pwm2;
169extern struct pmx_dev spear320_pmx_pwm3;
170extern struct pmx_dev spear320_pmx_ssp1;
171extern struct pmx_dev spear320_pmx_ssp2;
172extern struct pmx_dev spear320_pmx_mii1;
173extern struct pmx_dev spear320_pmx_smii0;
174extern struct pmx_dev spear320_pmx_smii1;
175extern struct pmx_dev spear320_pmx_i2c1;
176
177/* Add spear320 machine declarations here */
178void __init spear320_clk_init(void);
179
180#endif /* CONFIG_MACH_SPEAR320 */
181
182#endif /* __MACH_GENERIC_H */ 37#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index e0ab72e61507..18e2ac576f25 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -14,6 +14,8 @@
14#ifndef __MACH_MISC_REGS_H 14#ifndef __MACH_MISC_REGS_H
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/spear.h>
18
17#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) 19#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
18#define DMA_CHN_CFG (MISC_BASE + 0x0A0) 20#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
19 21
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 04da906b0d4c..51eb953148a9 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -44,4 +44,17 @@
44#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE 44#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE
45#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE 45#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
46 46
47/* SPEAr320 Macros */
48#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
49#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000)
50#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
51#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
52 #define SPEAR320_UARTX_PCLK_MASK 0x1
53 #define SPEAR320_UART2_PCLK_SHIFT 8
54 #define SPEAR320_UART3_PCLK_SHIFT 9
55 #define SPEAR320_UART4_PCLK_SHIFT 10
56 #define SPEAR320_UART5_PCLK_SHIFT 11
57 #define SPEAR320_UART6_PCLK_SHIFT 12
58 #define SPEAR320_RS485_PCLK_SHIFT 13
59
47#endif /* __MACH_SPEAR3XX_H */ 60#endif /* __MACH_SPEAR3XX_H */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index febcdd8d4e92..f74a05bdb829 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -60,357 +60,6 @@
60/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ 60/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
61#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 61#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
62 62
63/* pad multiplexing support */
64/* muxing registers */
65#define PAD_MUX_CONFIG_REG 0x00
66#define MODE_CONFIG_REG 0x04
67
68/* modes */
69#define NAND_MODE (1 << 0)
70#define NOR_MODE (1 << 1)
71#define PHOTO_FRAME_MODE (1 << 2)
72#define LEND_IP_PHONE_MODE (1 << 3)
73#define HEND_IP_PHONE_MODE (1 << 4)
74#define LEND_WIFI_PHONE_MODE (1 << 5)
75#define HEND_WIFI_PHONE_MODE (1 << 6)
76#define ATA_PABX_WI2S_MODE (1 << 7)
77#define ATA_PABX_I2S_MODE (1 << 8)
78#define CAML_LCDW_MODE (1 << 9)
79#define CAMU_LCD_MODE (1 << 10)
80#define CAMU_WLCD_MODE (1 << 11)
81#define CAML_LCD_MODE (1 << 12)
82#define ALL_MODES 0x1FFF
83
84struct pmx_mode spear300_nand_mode = {
85 .id = NAND_MODE,
86 .name = "nand mode",
87 .mask = 0x00,
88};
89
90struct pmx_mode spear300_nor_mode = {
91 .id = NOR_MODE,
92 .name = "nor mode",
93 .mask = 0x01,
94};
95
96struct pmx_mode spear300_photo_frame_mode = {
97 .id = PHOTO_FRAME_MODE,
98 .name = "photo frame mode",
99 .mask = 0x02,
100};
101
102struct pmx_mode spear300_lend_ip_phone_mode = {
103 .id = LEND_IP_PHONE_MODE,
104 .name = "lend ip phone mode",
105 .mask = 0x03,
106};
107
108struct pmx_mode spear300_hend_ip_phone_mode = {
109 .id = HEND_IP_PHONE_MODE,
110 .name = "hend ip phone mode",
111 .mask = 0x04,
112};
113
114struct pmx_mode spear300_lend_wifi_phone_mode = {
115 .id = LEND_WIFI_PHONE_MODE,
116 .name = "lend wifi phone mode",
117 .mask = 0x05,
118};
119
120struct pmx_mode spear300_hend_wifi_phone_mode = {
121 .id = HEND_WIFI_PHONE_MODE,
122 .name = "hend wifi phone mode",
123 .mask = 0x06,
124};
125
126struct pmx_mode spear300_ata_pabx_wi2s_mode = {
127 .id = ATA_PABX_WI2S_MODE,
128 .name = "ata pabx wi2s mode",
129 .mask = 0x07,
130};
131
132struct pmx_mode spear300_ata_pabx_i2s_mode = {
133 .id = ATA_PABX_I2S_MODE,
134 .name = "ata pabx i2s mode",
135 .mask = 0x08,
136};
137
138struct pmx_mode spear300_caml_lcdw_mode = {
139 .id = CAML_LCDW_MODE,
140 .name = "caml lcdw mode",
141 .mask = 0x0C,
142};
143
144struct pmx_mode spear300_camu_lcd_mode = {
145 .id = CAMU_LCD_MODE,
146 .name = "camu lcd mode",
147 .mask = 0x0D,
148};
149
150struct pmx_mode spear300_camu_wlcd_mode = {
151 .id = CAMU_WLCD_MODE,
152 .name = "camu wlcd mode",
153 .mask = 0x0E,
154};
155
156struct pmx_mode spear300_caml_lcd_mode = {
157 .id = CAML_LCD_MODE,
158 .name = "caml lcd mode",
159 .mask = 0x0F,
160};
161
162/* devices */
163static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
164 {
165 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
166 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
167 .mask = PMX_FIRDA_MASK,
168 },
169};
170
171struct pmx_dev spear300_pmx_fsmc_2_chips = {
172 .name = "fsmc_2_chips",
173 .modes = pmx_fsmc_2_chips_modes,
174 .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
175 .enb_on_reset = 1,
176};
177
178static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
179 {
180 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
181 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
182 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
183 },
184};
185
186struct pmx_dev spear300_pmx_fsmc_4_chips = {
187 .name = "fsmc_4_chips",
188 .modes = pmx_fsmc_4_chips_modes,
189 .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
190 .enb_on_reset = 1,
191};
192
193static struct pmx_dev_mode pmx_keyboard_modes[] = {
194 {
195 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
196 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
197 CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
198 CAML_LCD_MODE,
199 .mask = 0x0,
200 },
201};
202
203struct pmx_dev spear300_pmx_keyboard = {
204 .name = "keyboard",
205 .modes = pmx_keyboard_modes,
206 .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
207 .enb_on_reset = 1,
208};
209
210static struct pmx_dev_mode pmx_clcd_modes[] = {
211 {
212 .ids = PHOTO_FRAME_MODE,
213 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
214 }, {
215 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
216 CAMU_LCD_MODE | CAML_LCD_MODE,
217 .mask = PMX_TIMER_3_4_MASK,
218 },
219};
220
221struct pmx_dev spear300_pmx_clcd = {
222 .name = "clcd",
223 .modes = pmx_clcd_modes,
224 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
225 .enb_on_reset = 1,
226};
227
228static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
229 {
230 .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
231 .mask = PMX_MII_MASK,
232 }, {
233 .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
234 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
235 }, {
236 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
237 .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
238 }, {
239 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
240 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
241 }, {
242 .ids = ATA_PABX_WI2S_MODE,
243 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
244 | PMX_UART0_MODEM_MASK,
245 },
246};
247
248struct pmx_dev spear300_pmx_telecom_gpio = {
249 .name = "telecom_gpio",
250 .modes = pmx_telecom_gpio_modes,
251 .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
252 .enb_on_reset = 1,
253};
254
255static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
256 {
257 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
258 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
259 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
260 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
261 | CAMU_WLCD_MODE | CAML_LCD_MODE,
262 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
263 },
264};
265
266struct pmx_dev spear300_pmx_telecom_tdm = {
267 .name = "telecom_tdm",
268 .modes = pmx_telecom_tdm_modes,
269 .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
270 .enb_on_reset = 1,
271};
272
273static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
274 {
275 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
276 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
277 | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
278 CAML_LCDW_MODE | CAML_LCD_MODE,
279 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
280 },
281};
282
283struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
284 .name = "telecom_spi_cs_i2c_clk",
285 .modes = pmx_telecom_spi_cs_i2c_clk_modes,
286 .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
287 .enb_on_reset = 1,
288};
289
290static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
291 {
292 .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
293 .mask = PMX_MII_MASK,
294 }, {
295 .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
296 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
297 },
298};
299
300struct pmx_dev spear300_pmx_telecom_camera = {
301 .name = "telecom_camera",
302 .modes = pmx_telecom_camera_modes,
303 .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
304 .enb_on_reset = 1,
305};
306
307static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
308 {
309 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
310 | CAMU_WLCD_MODE | CAML_LCD_MODE,
311 .mask = PMX_TIMER_1_2_MASK,
312 },
313};
314
315struct pmx_dev spear300_pmx_telecom_dac = {
316 .name = "telecom_dac",
317 .modes = pmx_telecom_dac_modes,
318 .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
319 .enb_on_reset = 1,
320};
321
322static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
323 {
324 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
325 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
326 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
327 | CAMU_WLCD_MODE | CAML_LCD_MODE,
328 .mask = PMX_UART0_MODEM_MASK,
329 },
330};
331
332struct pmx_dev spear300_pmx_telecom_i2s = {
333 .name = "telecom_i2s",
334 .modes = pmx_telecom_i2s_modes,
335 .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
336 .enb_on_reset = 1,
337};
338
339static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
340 {
341 .ids = NAND_MODE | NOR_MODE,
342 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
343 PMX_TIMER_3_4_MASK,
344 },
345};
346
347struct pmx_dev spear300_pmx_telecom_boot_pins = {
348 .name = "telecom_boot_pins",
349 .modes = pmx_telecom_boot_pins_modes,
350 .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
351 .enb_on_reset = 1,
352};
353
354static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
355 {
356 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
357 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
358 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
359 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
360 ATA_PABX_I2S_MODE,
361 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
362 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
363 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
364 },
365};
366
367struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
368 .name = "telecom_sdhci_4bit",
369 .modes = pmx_telecom_sdhci_4bit_modes,
370 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
371 .enb_on_reset = 1,
372};
373
374static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
375 {
376 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
377 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
378 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
379 CAMU_WLCD_MODE | CAML_LCD_MODE,
380 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
381 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
382 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
383 },
384};
385
386struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
387 .name = "telecom_sdhci_8bit",
388 .modes = pmx_telecom_sdhci_8bit_modes,
389 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
390 .enb_on_reset = 1,
391};
392
393static struct pmx_dev_mode pmx_gpio1_modes[] = {
394 {
395 .ids = PHOTO_FRAME_MODE,
396 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
397 PMX_TIMER_3_4_MASK,
398 },
399};
400
401struct pmx_dev spear300_pmx_gpio1 = {
402 .name = "arm gpio1",
403 .modes = pmx_gpio1_modes,
404 .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
405 .enb_on_reset = 1,
406};
407
408/* pmx driver structure */
409static struct pmx_driver pmx_driver = {
410 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
411 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
412};
413
414/* spear3xx shared irq */ 63/* spear3xx shared irq */
415static struct shirq_dev_config shirq_ras1_config[] = { 64static struct shirq_dev_config shirq_ras1_config[] = {
416 { 65 {
@@ -464,22 +113,6 @@ static struct spear_shirq shirq_ras1 = {
464 }, 113 },
465}; 114};
466 115
467/* padmux devices to enable */
468static struct pmx_dev *spear300_evb_pmx_devs[] = {
469 /* spear3xx specific devices */
470 &spear3xx_pmx_i2c,
471 &spear3xx_pmx_ssp_cs,
472 &spear3xx_pmx_ssp,
473 &spear3xx_pmx_mii,
474 &spear3xx_pmx_uart0,
475
476 /* spear300 specific devices */
477 &spear300_pmx_fsmc_2_chips,
478 &spear300_pmx_clcd,
479 &spear300_pmx_telecom_sdhci_4bit,
480 &spear300_pmx_gpio1,
481};
482
483/* DMAC platform data's slave info */ 116/* DMAC platform data's slave info */
484struct pl08x_channel_data spear300_dma_info[] = { 117struct pl08x_channel_data spear300_dma_info[] = {
485 { 118 {
@@ -678,7 +311,7 @@ static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
678 311
679static void __init spear300_dt_init(void) 312static void __init spear300_dt_init(void)
680{ 313{
681 int ret = -EINVAL; 314 int ret;
682 315
683 pl080_plat_data.slave_channels = spear300_dma_info; 316 pl080_plat_data.slave_channels = spear300_dma_info;
684 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info); 317 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
@@ -693,26 +326,6 @@ static void __init spear300_dt_init(void)
693 if (ret) 326 if (ret)
694 pr_err("Error registering Shared IRQ\n"); 327 pr_err("Error registering Shared IRQ\n");
695 } 328 }
696
697 if (of_machine_is_compatible("st,spear300-evb")) {
698 /* pmx initialization */
699 pmx_driver.mode = &spear300_photo_frame_mode;
700 pmx_driver.devs = spear300_evb_pmx_devs;
701 pmx_driver.devs_count = ARRAY_SIZE(spear300_evb_pmx_devs);
702
703 pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
704 if (pmx_driver.base) {
705 ret = pmx_register(&pmx_driver);
706 if (ret)
707 pr_err("padmux: registration failed. err no: %d\n",
708 ret);
709 /* Free Mapping, device selection already done */
710 iounmap(pmx_driver.base);
711 }
712
713 if (ret)
714 pr_err("Initialization Failed");
715 }
716} 329}
717 330
718static const char * const spear300_dt_board_compat[] = { 331static const char * const spear300_dt_board_compat[] = {
@@ -724,7 +337,6 @@ static const char * const spear300_dt_board_compat[] = {
724static void __init spear300_map_io(void) 337static void __init spear300_map_io(void)
725{ 338{
726 spear3xx_map_io(); 339 spear3xx_map_io();
727 spear300_clk_init();
728} 340}
729 341
730DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree") 342DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index b26e41566b50..84dfb0900747 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -82,128 +82,6 @@
82#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17) 82#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
83 83
84 84
85/* pad multiplexing support */
86/* muxing registers */
87#define PAD_MUX_CONFIG_REG 0x08
88
89/* devices */
90static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
91 {
92 .ids = 0x00,
93 .mask = PMX_TIMER_3_4_MASK,
94 },
95};
96
97struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
98 .name = "emi_cs_0_1_4_5",
99 .modes = pmx_emi_cs_0_1_4_5_modes,
100 .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
101 .enb_on_reset = 1,
102};
103
104static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
105 {
106 .ids = 0x00,
107 .mask = PMX_TIMER_1_2_MASK,
108 },
109};
110
111struct pmx_dev spear310_pmx_emi_cs_2_3 = {
112 .name = "emi_cs_2_3",
113 .modes = pmx_emi_cs_2_3_modes,
114 .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
115 .enb_on_reset = 1,
116};
117
118static struct pmx_dev_mode pmx_uart1_modes[] = {
119 {
120 .ids = 0x00,
121 .mask = PMX_FIRDA_MASK,
122 },
123};
124
125struct pmx_dev spear310_pmx_uart1 = {
126 .name = "uart1",
127 .modes = pmx_uart1_modes,
128 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
129 .enb_on_reset = 1,
130};
131
132static struct pmx_dev_mode pmx_uart2_modes[] = {
133 {
134 .ids = 0x00,
135 .mask = PMX_TIMER_1_2_MASK,
136 },
137};
138
139struct pmx_dev spear310_pmx_uart2 = {
140 .name = "uart2",
141 .modes = pmx_uart2_modes,
142 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
143 .enb_on_reset = 1,
144};
145
146static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
147 {
148 .ids = 0x00,
149 .mask = PMX_UART0_MODEM_MASK,
150 },
151};
152
153struct pmx_dev spear310_pmx_uart3_4_5 = {
154 .name = "uart3_4_5",
155 .modes = pmx_uart3_4_5_modes,
156 .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
157 .enb_on_reset = 1,
158};
159
160static struct pmx_dev_mode pmx_fsmc_modes[] = {
161 {
162 .ids = 0x00,
163 .mask = PMX_SSP_CS_MASK,
164 },
165};
166
167struct pmx_dev spear310_pmx_fsmc = {
168 .name = "fsmc",
169 .modes = pmx_fsmc_modes,
170 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
171 .enb_on_reset = 1,
172};
173
174static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
175 {
176 .ids = 0x00,
177 .mask = PMX_MII_MASK,
178 },
179};
180
181struct pmx_dev spear310_pmx_rs485_0_1 = {
182 .name = "rs485_0_1",
183 .modes = pmx_rs485_0_1_modes,
184 .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
185 .enb_on_reset = 1,
186};
187
188static struct pmx_dev_mode pmx_tdm0_modes[] = {
189 {
190 .ids = 0x00,
191 .mask = PMX_MII_MASK,
192 },
193};
194
195struct pmx_dev spear310_pmx_tdm0 = {
196 .name = "tdm0",
197 .modes = pmx_tdm0_modes,
198 .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
199 .enb_on_reset = 1,
200};
201
202/* pmx driver structure */
203static struct pmx_driver pmx_driver = {
204 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
205};
206
207/* spear3xx shared irq */ 85/* spear3xx shared irq */
208static struct shirq_dev_config shirq_ras1_config[] = { 86static struct shirq_dev_config shirq_ras1_config[] = {
209 { 87 {
@@ -320,30 +198,6 @@ static struct spear_shirq shirq_intrcomm_ras = {
320 }, 198 },
321}; 199};
322 200
323/* padmux devices to enable */
324static struct pmx_dev *spear310_evb_pmx_devs[] = {
325 /* spear3xx specific devices */
326 &spear3xx_pmx_i2c,
327 &spear3xx_pmx_ssp,
328 &spear3xx_pmx_gpio_pin0,
329 &spear3xx_pmx_gpio_pin1,
330 &spear3xx_pmx_gpio_pin2,
331 &spear3xx_pmx_gpio_pin3,
332 &spear3xx_pmx_gpio_pin4,
333 &spear3xx_pmx_gpio_pin5,
334 &spear3xx_pmx_uart0,
335
336 /* spear310 specific devices */
337 &spear310_pmx_emi_cs_0_1_4_5,
338 &spear310_pmx_emi_cs_2_3,
339 &spear310_pmx_uart1,
340 &spear310_pmx_uart2,
341 &spear310_pmx_uart3_4_5,
342 &spear310_pmx_fsmc,
343 &spear310_pmx_rs485_0_1,
344 &spear310_pmx_tdm0,
345};
346
347/* DMAC platform data's slave info */ 201/* DMAC platform data's slave info */
348struct pl08x_channel_data spear310_dma_info[] = { 202struct pl08x_channel_data spear310_dma_info[] = {
349 { 203 {
@@ -578,7 +432,7 @@ static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
578static void __init spear310_dt_init(void) 432static void __init spear310_dt_init(void)
579{ 433{
580 void __iomem *base; 434 void __iomem *base;
581 int ret = 0; 435 int ret;
582 436
583 pl080_plat_data.slave_channels = spear310_dma_info; 437 pl080_plat_data.slave_channels = spear310_dma_info;
584 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info); 438 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
@@ -613,19 +467,6 @@ static void __init spear310_dt_init(void)
613 if (ret) 467 if (ret)
614 pr_err("Error registering Shared IRQ 4\n"); 468 pr_err("Error registering Shared IRQ 4\n");
615 } 469 }
616
617 if (of_machine_is_compatible("st,spear310-evb")) {
618 /* pmx initialization */
619 pmx_driver.base = base;
620 pmx_driver.mode = NULL;
621 pmx_driver.devs = spear310_evb_pmx_devs;
622 pmx_driver.devs_count = ARRAY_SIZE(spear310_evb_pmx_devs);
623
624 ret = pmx_register(&pmx_driver);
625 if (ret)
626 pr_err("padmux: registration failed. err no: %d\n",
627 ret);
628 }
629} 470}
630 471
631static const char * const spear310_dt_board_compat[] = { 472static const char * const spear310_dt_board_compat[] = {
@@ -637,7 +478,6 @@ static const char * const spear310_dt_board_compat[] = {
637static void __init spear310_map_io(void) 478static void __init spear310_map_io(void)
638{ 479{
639 spear3xx_map_io(); 480 spear3xx_map_io();
640 spear310_clk_init();
641} 481}
642 482
643DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") 483DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 2f5979b0c169..a88fa841d29d 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -27,7 +27,6 @@
27#define SPEAR320_UART2_BASE UL(0xA4000000) 27#define SPEAR320_UART2_BASE UL(0xA4000000)
28#define SPEAR320_SSP0_BASE UL(0xA5000000) 28#define SPEAR320_SSP0_BASE UL(0xA5000000)
29#define SPEAR320_SSP1_BASE UL(0xA6000000) 29#define SPEAR320_SSP1_BASE UL(0xA6000000)
30#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
31 30
32/* Interrupt registers offsets and masks */ 31/* Interrupt registers offsets and masks */
33#define SPEAR320_INT_STS_MASK_REG 0x04 32#define SPEAR320_INT_STS_MASK_REG 0x04
@@ -83,373 +82,6 @@
83#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15) 82#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
84#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16) 83#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
85 84
86/* pad multiplexing support */
87/* muxing registers */
88#define PAD_MUX_CONFIG_REG 0x0C
89#define MODE_CONFIG_REG 0x10
90
91/* modes */
92#define AUTO_NET_SMII_MODE (1 << 0)
93#define AUTO_NET_MII_MODE (1 << 1)
94#define AUTO_EXP_MODE (1 << 2)
95#define SMALL_PRINTERS_MODE (1 << 3)
96#define ALL_MODES 0xF
97
98struct pmx_mode spear320_auto_net_smii_mode = {
99 .id = AUTO_NET_SMII_MODE,
100 .name = "Automation Networking SMII Mode",
101 .mask = 0x00,
102};
103
104struct pmx_mode spear320_auto_net_mii_mode = {
105 .id = AUTO_NET_MII_MODE,
106 .name = "Automation Networking MII Mode",
107 .mask = 0x01,
108};
109
110struct pmx_mode spear320_auto_exp_mode = {
111 .id = AUTO_EXP_MODE,
112 .name = "Automation Expanded Mode",
113 .mask = 0x02,
114};
115
116struct pmx_mode spear320_small_printers_mode = {
117 .id = SMALL_PRINTERS_MODE,
118 .name = "Small Printers Mode",
119 .mask = 0x03,
120};
121
122/* devices */
123static struct pmx_dev_mode pmx_clcd_modes[] = {
124 {
125 .ids = AUTO_NET_SMII_MODE,
126 .mask = 0x0,
127 },
128};
129
130struct pmx_dev spear320_pmx_clcd = {
131 .name = "clcd",
132 .modes = pmx_clcd_modes,
133 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
134 .enb_on_reset = 1,
135};
136
137static struct pmx_dev_mode pmx_emi_modes[] = {
138 {
139 .ids = AUTO_EXP_MODE,
140 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
141 },
142};
143
144struct pmx_dev spear320_pmx_emi = {
145 .name = "emi",
146 .modes = pmx_emi_modes,
147 .mode_count = ARRAY_SIZE(pmx_emi_modes),
148 .enb_on_reset = 1,
149};
150
151static struct pmx_dev_mode pmx_fsmc_modes[] = {
152 {
153 .ids = ALL_MODES,
154 .mask = 0x0,
155 },
156};
157
158struct pmx_dev spear320_pmx_fsmc = {
159 .name = "fsmc",
160 .modes = pmx_fsmc_modes,
161 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
162 .enb_on_reset = 1,
163};
164
165static struct pmx_dev_mode pmx_spp_modes[] = {
166 {
167 .ids = SMALL_PRINTERS_MODE,
168 .mask = 0x0,
169 },
170};
171
172struct pmx_dev spear320_pmx_spp = {
173 .name = "spp",
174 .modes = pmx_spp_modes,
175 .mode_count = ARRAY_SIZE(pmx_spp_modes),
176 .enb_on_reset = 1,
177};
178
179static struct pmx_dev_mode pmx_sdhci_modes[] = {
180 {
181 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
182 SMALL_PRINTERS_MODE,
183 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
184 },
185};
186
187struct pmx_dev spear320_pmx_sdhci = {
188 .name = "sdhci",
189 .modes = pmx_sdhci_modes,
190 .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
191 .enb_on_reset = 1,
192};
193
194static struct pmx_dev_mode pmx_i2s_modes[] = {
195 {
196 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
197 .mask = PMX_UART0_MODEM_MASK,
198 },
199};
200
201struct pmx_dev spear320_pmx_i2s = {
202 .name = "i2s",
203 .modes = pmx_i2s_modes,
204 .mode_count = ARRAY_SIZE(pmx_i2s_modes),
205 .enb_on_reset = 1,
206};
207
208static struct pmx_dev_mode pmx_uart1_modes[] = {
209 {
210 .ids = ALL_MODES,
211 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
212 },
213};
214
215struct pmx_dev spear320_pmx_uart1 = {
216 .name = "uart1",
217 .modes = pmx_uart1_modes,
218 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
219 .enb_on_reset = 1,
220};
221
222static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
223 {
224 .ids = AUTO_EXP_MODE,
225 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
226 PMX_SSP_CS_MASK,
227 }, {
228 .ids = SMALL_PRINTERS_MODE,
229 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
230 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
231 },
232};
233
234struct pmx_dev spear320_pmx_uart1_modem = {
235 .name = "uart1_modem",
236 .modes = pmx_uart1_modem_modes,
237 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
238 .enb_on_reset = 1,
239};
240
241static struct pmx_dev_mode pmx_uart2_modes[] = {
242 {
243 .ids = ALL_MODES,
244 .mask = PMX_FIRDA_MASK,
245 },
246};
247
248struct pmx_dev spear320_pmx_uart2 = {
249 .name = "uart2",
250 .modes = pmx_uart2_modes,
251 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
252 .enb_on_reset = 1,
253};
254
255static struct pmx_dev_mode pmx_touchscreen_modes[] = {
256 {
257 .ids = AUTO_NET_SMII_MODE,
258 .mask = PMX_SSP_CS_MASK,
259 },
260};
261
262struct pmx_dev spear320_pmx_touchscreen = {
263 .name = "touchscreen",
264 .modes = pmx_touchscreen_modes,
265 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
266 .enb_on_reset = 1,
267};
268
269static struct pmx_dev_mode pmx_can_modes[] = {
270 {
271 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
272 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
273 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
274 },
275};
276
277struct pmx_dev spear320_pmx_can = {
278 .name = "can",
279 .modes = pmx_can_modes,
280 .mode_count = ARRAY_SIZE(pmx_can_modes),
281 .enb_on_reset = 1,
282};
283
284static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
285 {
286 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
287 .mask = PMX_SSP_CS_MASK,
288 },
289};
290
291struct pmx_dev spear320_pmx_sdhci_led = {
292 .name = "sdhci_led",
293 .modes = pmx_sdhci_led_modes,
294 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
295 .enb_on_reset = 1,
296};
297
298static struct pmx_dev_mode pmx_pwm0_modes[] = {
299 {
300 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
301 .mask = PMX_UART0_MODEM_MASK,
302 }, {
303 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
304 .mask = PMX_MII_MASK,
305 },
306};
307
308struct pmx_dev spear320_pmx_pwm0 = {
309 .name = "pwm0",
310 .modes = pmx_pwm0_modes,
311 .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
312 .enb_on_reset = 1,
313};
314
315static struct pmx_dev_mode pmx_pwm1_modes[] = {
316 {
317 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
318 .mask = PMX_UART0_MODEM_MASK,
319 }, {
320 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
321 .mask = PMX_MII_MASK,
322 },
323};
324
325struct pmx_dev spear320_pmx_pwm1 = {
326 .name = "pwm1",
327 .modes = pmx_pwm1_modes,
328 .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
329 .enb_on_reset = 1,
330};
331
332static struct pmx_dev_mode pmx_pwm2_modes[] = {
333 {
334 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
335 .mask = PMX_SSP_CS_MASK,
336 }, {
337 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
338 .mask = PMX_MII_MASK,
339 },
340};
341
342struct pmx_dev spear320_pmx_pwm2 = {
343 .name = "pwm2",
344 .modes = pmx_pwm2_modes,
345 .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
346 .enb_on_reset = 1,
347};
348
349static struct pmx_dev_mode pmx_pwm3_modes[] = {
350 {
351 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
352 .mask = PMX_MII_MASK,
353 },
354};
355
356struct pmx_dev spear320_pmx_pwm3 = {
357 .name = "pwm3",
358 .modes = pmx_pwm3_modes,
359 .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
360 .enb_on_reset = 1,
361};
362
363static struct pmx_dev_mode pmx_ssp1_modes[] = {
364 {
365 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
366 .mask = PMX_MII_MASK,
367 },
368};
369
370struct pmx_dev spear320_pmx_ssp1 = {
371 .name = "ssp1",
372 .modes = pmx_ssp1_modes,
373 .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
374 .enb_on_reset = 1,
375};
376
377static struct pmx_dev_mode pmx_ssp2_modes[] = {
378 {
379 .ids = AUTO_NET_SMII_MODE,
380 .mask = PMX_MII_MASK,
381 },
382};
383
384struct pmx_dev spear320_pmx_ssp2 = {
385 .name = "ssp2",
386 .modes = pmx_ssp2_modes,
387 .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
388 .enb_on_reset = 1,
389};
390
391static struct pmx_dev_mode pmx_mii1_modes[] = {
392 {
393 .ids = AUTO_NET_MII_MODE,
394 .mask = 0x0,
395 },
396};
397
398struct pmx_dev spear320_pmx_mii1 = {
399 .name = "mii1",
400 .modes = pmx_mii1_modes,
401 .mode_count = ARRAY_SIZE(pmx_mii1_modes),
402 .enb_on_reset = 1,
403};
404
405static struct pmx_dev_mode pmx_smii0_modes[] = {
406 {
407 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
408 .mask = PMX_MII_MASK,
409 },
410};
411
412struct pmx_dev spear320_pmx_smii0 = {
413 .name = "smii0",
414 .modes = pmx_smii0_modes,
415 .mode_count = ARRAY_SIZE(pmx_smii0_modes),
416 .enb_on_reset = 1,
417};
418
419static struct pmx_dev_mode pmx_smii1_modes[] = {
420 {
421 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
422 .mask = PMX_MII_MASK,
423 },
424};
425
426struct pmx_dev spear320_pmx_smii1 = {
427 .name = "smii1",
428 .modes = pmx_smii1_modes,
429 .mode_count = ARRAY_SIZE(pmx_smii1_modes),
430 .enb_on_reset = 1,
431};
432
433static struct pmx_dev_mode pmx_i2c1_modes[] = {
434 {
435 .ids = AUTO_EXP_MODE,
436 .mask = 0x0,
437 },
438};
439
440struct pmx_dev spear320_pmx_i2c1 = {
441 .name = "i2c1",
442 .modes = pmx_i2c1_modes,
443 .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
444 .enb_on_reset = 1,
445};
446
447/* pmx driver structure */
448static struct pmx_driver pmx_driver = {
449 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
450 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
451};
452
453/* spear3xx shared irq */ 85/* spear3xx shared irq */
454static struct shirq_dev_config shirq_ras1_config[] = { 86static struct shirq_dev_config shirq_ras1_config[] = {
455 { 87 {
@@ -574,27 +206,6 @@ static struct spear_shirq shirq_intrcomm_ras = {
574 }, 206 },
575}; 207};
576 208
577/* padmux devices to enable */
578static struct pmx_dev *spear320_evb_pmx_devs[] = {
579 /* spear3xx specific devices */
580 &spear3xx_pmx_i2c,
581 &spear3xx_pmx_ssp,
582 &spear3xx_pmx_mii,
583 &spear3xx_pmx_uart0,
584
585 /* spear320 specific devices */
586 &spear320_pmx_fsmc,
587 &spear320_pmx_sdhci,
588 &spear320_pmx_i2s,
589 &spear320_pmx_uart1,
590 &spear320_pmx_uart2,
591 &spear320_pmx_can,
592 &spear320_pmx_pwm0,
593 &spear320_pmx_pwm1,
594 &spear320_pmx_pwm2,
595 &spear320_pmx_mii1,
596};
597
598/* DMAC platform data's slave info */ 209/* DMAC platform data's slave info */
599struct pl08x_channel_data spear320_dma_info[] = { 210struct pl08x_channel_data spear320_dma_info[] = {
600 { 211 {
@@ -832,7 +443,7 @@ static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
832static void __init spear320_dt_init(void) 443static void __init spear320_dt_init(void)
833{ 444{
834 void __iomem *base; 445 void __iomem *base;
835 int ret = 0; 446 int ret;
836 447
837 pl080_plat_data.slave_channels = spear320_dma_info; 448 pl080_plat_data.slave_channels = spear320_dma_info;
838 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); 449 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
@@ -861,19 +472,6 @@ static void __init spear320_dt_init(void)
861 if (ret) 472 if (ret)
862 pr_err("Error registering Shared IRQ 4\n"); 473 pr_err("Error registering Shared IRQ 4\n");
863 } 474 }
864
865 if (of_machine_is_compatible("st,spear320-evb")) {
866 /* pmx initialization */
867 pmx_driver.base = base;
868 pmx_driver.mode = &spear320_auto_net_mii_mode;
869 pmx_driver.devs = spear320_evb_pmx_devs;
870 pmx_driver.devs_count = ARRAY_SIZE(spear320_evb_pmx_devs);
871
872 ret = pmx_register(&pmx_driver);
873 if (ret)
874 pr_err("padmux: registration failed. err no: %d\n",
875 ret);
876 }
877} 475}
878 476
879static const char * const spear320_dt_board_compat[] = { 477static const char * const spear320_dt_board_compat[] = {
@@ -882,10 +480,19 @@ static const char * const spear320_dt_board_compat[] = {
882 NULL, 480 NULL,
883}; 481};
884 482
483struct map_desc spear320_io_desc[] __initdata = {
484 {
485 .virtual = VA_SPEAR320_SOC_CONFIG_BASE,
486 .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
487 .length = SZ_16M,
488 .type = MT_DEVICE
489 },
490};
491
885static void __init spear320_map_io(void) 492static void __init spear320_map_io(void)
886{ 493{
494 iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
887 spear3xx_map_io(); 495 spear3xx_map_io();
888 spear320_clk_init();
889} 496}
890 497
891DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") 498DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 25c6c67d5b07..f22419ed74a8 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -23,431 +23,6 @@
23#include <mach/generic.h> 23#include <mach/generic.h>
24#include <mach/spear.h> 24#include <mach/spear.h>
25 25
26/* pad multiplexing support */
27/* devices */
28static struct pmx_dev_mode pmx_firda_modes[] = {
29 {
30 .ids = 0xffffffff,
31 .mask = PMX_FIRDA_MASK,
32 },
33};
34
35struct pmx_dev spear3xx_pmx_firda = {
36 .name = "firda",
37 .modes = pmx_firda_modes,
38 .mode_count = ARRAY_SIZE(pmx_firda_modes),
39 .enb_on_reset = 0,
40};
41
42static struct pmx_dev_mode pmx_i2c_modes[] = {
43 {
44 .ids = 0xffffffff,
45 .mask = PMX_I2C_MASK,
46 },
47};
48
49struct pmx_dev spear3xx_pmx_i2c = {
50 .name = "i2c",
51 .modes = pmx_i2c_modes,
52 .mode_count = ARRAY_SIZE(pmx_i2c_modes),
53 .enb_on_reset = 0,
54};
55
56static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
57 {
58 .ids = 0xffffffff,
59 .mask = PMX_SSP_CS_MASK,
60 },
61};
62
63struct pmx_dev spear3xx_pmx_ssp_cs = {
64 .name = "ssp_chip_selects",
65 .modes = pmx_ssp_cs_modes,
66 .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
67 .enb_on_reset = 0,
68};
69
70static struct pmx_dev_mode pmx_ssp_modes[] = {
71 {
72 .ids = 0xffffffff,
73 .mask = PMX_SSP_MASK,
74 },
75};
76
77struct pmx_dev spear3xx_pmx_ssp = {
78 .name = "ssp",
79 .modes = pmx_ssp_modes,
80 .mode_count = ARRAY_SIZE(pmx_ssp_modes),
81 .enb_on_reset = 0,
82};
83
84static struct pmx_dev_mode pmx_mii_modes[] = {
85 {
86 .ids = 0xffffffff,
87 .mask = PMX_MII_MASK,
88 },
89};
90
91struct pmx_dev spear3xx_pmx_mii = {
92 .name = "mii",
93 .modes = pmx_mii_modes,
94 .mode_count = ARRAY_SIZE(pmx_mii_modes),
95 .enb_on_reset = 0,
96};
97
98static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
99 {
100 .ids = 0xffffffff,
101 .mask = PMX_GPIO_PIN0_MASK,
102 },
103};
104
105struct pmx_dev spear3xx_pmx_gpio_pin0 = {
106 .name = "gpio_pin0",
107 .modes = pmx_gpio_pin0_modes,
108 .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
109 .enb_on_reset = 0,
110};
111
112static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
113 {
114 .ids = 0xffffffff,
115 .mask = PMX_GPIO_PIN1_MASK,
116 },
117};
118
119struct pmx_dev spear3xx_pmx_gpio_pin1 = {
120 .name = "gpio_pin1",
121 .modes = pmx_gpio_pin1_modes,
122 .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
123 .enb_on_reset = 0,
124};
125
126static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
127 {
128 .ids = 0xffffffff,
129 .mask = PMX_GPIO_PIN2_MASK,
130 },
131};
132
133struct pmx_dev spear3xx_pmx_gpio_pin2 = {
134 .name = "gpio_pin2",
135 .modes = pmx_gpio_pin2_modes,
136 .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
137 .enb_on_reset = 0,
138};
139
140static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
141 {
142 .ids = 0xffffffff,
143 .mask = PMX_GPIO_PIN3_MASK,
144 },
145};
146
147struct pmx_dev spear3xx_pmx_gpio_pin3 = {
148 .name = "gpio_pin3",
149 .modes = pmx_gpio_pin3_modes,
150 .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
151 .enb_on_reset = 0,
152};
153
154static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
155 {
156 .ids = 0xffffffff,
157 .mask = PMX_GPIO_PIN4_MASK,
158 },
159};
160
161struct pmx_dev spear3xx_pmx_gpio_pin4 = {
162 .name = "gpio_pin4",
163 .modes = pmx_gpio_pin4_modes,
164 .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
165 .enb_on_reset = 0,
166};
167
168static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
169 {
170 .ids = 0xffffffff,
171 .mask = PMX_GPIO_PIN5_MASK,
172 },
173};
174
175struct pmx_dev spear3xx_pmx_gpio_pin5 = {
176 .name = "gpio_pin5",
177 .modes = pmx_gpio_pin5_modes,
178 .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
179 .enb_on_reset = 0,
180};
181
182static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
183 {
184 .ids = 0xffffffff,
185 .mask = PMX_UART0_MODEM_MASK,
186 },
187};
188
189struct pmx_dev spear3xx_pmx_uart0_modem = {
190 .name = "uart0_modem",
191 .modes = pmx_uart0_modem_modes,
192 .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
193 .enb_on_reset = 0,
194};
195
196static struct pmx_dev_mode pmx_uart0_modes[] = {
197 {
198 .ids = 0xffffffff,
199 .mask = PMX_UART0_MASK,
200 },
201};
202
203struct pmx_dev spear3xx_pmx_uart0 = {
204 .name = "uart0",
205 .modes = pmx_uart0_modes,
206 .mode_count = ARRAY_SIZE(pmx_uart0_modes),
207 .enb_on_reset = 0,
208};
209
210static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
211 {
212 .ids = 0xffffffff,
213 .mask = PMX_TIMER_3_4_MASK,
214 },
215};
216
217struct pmx_dev spear3xx_pmx_timer_3_4 = {
218 .name = "timer_3_4",
219 .modes = pmx_timer_3_4_modes,
220 .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
221 .enb_on_reset = 0,
222};
223
224static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
225 {
226 .ids = 0xffffffff,
227 .mask = PMX_TIMER_1_2_MASK,
228 },
229};
230
231struct pmx_dev spear3xx_pmx_timer_1_2 = {
232 .name = "timer_1_2",
233 .modes = pmx_timer_1_2_modes,
234 .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
235 .enb_on_reset = 0,
236};
237
238#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
239/* plgpios devices */
240static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
241 {
242 .ids = 0x00,
243 .mask = PMX_FIRDA_MASK,
244 },
245};
246
247struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
248 .name = "plgpio 0 and 1",
249 .modes = pmx_plgpio_0_1_modes,
250 .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
251 .enb_on_reset = 1,
252};
253
254static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
255 {
256 .ids = 0x00,
257 .mask = PMX_UART0_MASK,
258 },
259};
260
261struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
262 .name = "plgpio 2 and 3",
263 .modes = pmx_plgpio_2_3_modes,
264 .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
265 .enb_on_reset = 1,
266};
267
268static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
269 {
270 .ids = 0x00,
271 .mask = PMX_I2C_MASK,
272 },
273};
274
275struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
276 .name = "plgpio 4 and 5",
277 .modes = pmx_plgpio_4_5_modes,
278 .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
279 .enb_on_reset = 1,
280};
281
282static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
283 {
284 .ids = 0x00,
285 .mask = PMX_SSP_MASK,
286 },
287};
288
289struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
290 .name = "plgpio 6 to 9",
291 .modes = pmx_plgpio_6_9_modes,
292 .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
293 .enb_on_reset = 1,
294};
295
296static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
297 {
298 .ids = 0x00,
299 .mask = PMX_MII_MASK,
300 },
301};
302
303struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
304 .name = "plgpio 10 to 27",
305 .modes = pmx_plgpio_10_27_modes,
306 .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
307 .enb_on_reset = 1,
308};
309
310static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
311 {
312 .ids = 0x00,
313 .mask = PMX_GPIO_PIN0_MASK,
314 },
315};
316
317struct pmx_dev spear3xx_pmx_plgpio_28 = {
318 .name = "plgpio 28",
319 .modes = pmx_plgpio_28_modes,
320 .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
321 .enb_on_reset = 1,
322};
323
324static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
325 {
326 .ids = 0x00,
327 .mask = PMX_GPIO_PIN1_MASK,
328 },
329};
330
331struct pmx_dev spear3xx_pmx_plgpio_29 = {
332 .name = "plgpio 29",
333 .modes = pmx_plgpio_29_modes,
334 .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
335 .enb_on_reset = 1,
336};
337
338static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
339 {
340 .ids = 0x00,
341 .mask = PMX_GPIO_PIN2_MASK,
342 },
343};
344
345struct pmx_dev spear3xx_pmx_plgpio_30 = {
346 .name = "plgpio 30",
347 .modes = pmx_plgpio_30_modes,
348 .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
349 .enb_on_reset = 1,
350};
351
352static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
353 {
354 .ids = 0x00,
355 .mask = PMX_GPIO_PIN3_MASK,
356 },
357};
358
359struct pmx_dev spear3xx_pmx_plgpio_31 = {
360 .name = "plgpio 31",
361 .modes = pmx_plgpio_31_modes,
362 .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
363 .enb_on_reset = 1,
364};
365
366static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
367 {
368 .ids = 0x00,
369 .mask = PMX_GPIO_PIN4_MASK,
370 },
371};
372
373struct pmx_dev spear3xx_pmx_plgpio_32 = {
374 .name = "plgpio 32",
375 .modes = pmx_plgpio_32_modes,
376 .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
377 .enb_on_reset = 1,
378};
379
380static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
381 {
382 .ids = 0x00,
383 .mask = PMX_GPIO_PIN5_MASK,
384 },
385};
386
387struct pmx_dev spear3xx_pmx_plgpio_33 = {
388 .name = "plgpio 33",
389 .modes = pmx_plgpio_33_modes,
390 .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
391 .enb_on_reset = 1,
392};
393
394static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
395 {
396 .ids = 0x00,
397 .mask = PMX_SSP_CS_MASK,
398 },
399};
400
401struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
402 .name = "plgpio 34 to 36",
403 .modes = pmx_plgpio_34_36_modes,
404 .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
405 .enb_on_reset = 1,
406};
407
408static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
409 {
410 .ids = 0x00,
411 .mask = PMX_UART0_MODEM_MASK,
412 },
413};
414
415struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
416 .name = "plgpio 37 to 42",
417 .modes = pmx_plgpio_37_42_modes,
418 .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
419 .enb_on_reset = 1,
420};
421
422static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
423 {
424 .ids = 0x00,
425 .mask = PMX_TIMER_1_2_MASK,
426 },
427};
428
429struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
430 .name = "plgpio 43, 44, 47 and 48",
431 .modes = pmx_plgpio_43_44_47_48_modes,
432 .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
433 .enb_on_reset = 1,
434};
435
436static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
437 {
438 .ids = 0x00,
439 .mask = PMX_TIMER_3_4_MASK,
440 },
441};
442
443struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
444 .name = "plgpio 45, 46, 49 and 50",
445 .modes = pmx_plgpio_45_46_49_50_modes,
446 .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
447 .enb_on_reset = 1,
448};
449#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
450
451/* ssp device registration */ 26/* ssp device registration */
452struct pl022_ssp_controller pl022_plat_data = { 27struct pl022_ssp_controller pl022_plat_data = {
453 .bus_id = 0, 28 .bus_id = 0,
@@ -515,6 +90,8 @@ static void __init spear3xx_timer_init(void)
515 char pclk_name[] = "pll3_48m_clk"; 90 char pclk_name[] = "pll3_48m_clk";
516 struct clk *gpt_clk, *pclk; 91 struct clk *gpt_clk, *pclk;
517 92
93 spear3xx_clk_init();
94
518 /* get the system timer clock */ 95 /* get the system timer clock */
519 gpt_clk = clk_get_sys("gpt0", NULL); 96 gpt_clk = clk_get_sys("gpt0", NULL);
520 if (IS_ERR(gpt_clk)) { 97 if (IS_ERR(gpt_clk)) {
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
index 76e5750552fc..898831d93f37 100644
--- a/arch/arm/mach-spear6xx/Makefile
+++ b/arch/arm/mach-spear6xx/Makefile
@@ -3,4 +3,4 @@
3# 3#
4 4
5# common files 5# common files
6obj-y += clock.o spear6xx.o 6obj-y += spear6xx.o
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
deleted file mode 100644
index bef77d43db87..000000000000
--- a/arch/arm/mach-spear6xx/clock.c
+++ /dev/null
@@ -1,789 +0,0 @@
1/*
2 * arch/arm/mach-spear6xx/clock.c
3 *
4 * SPEAr6xx machines clock framework source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <plat/clock.h>
18#include <mach/misc_regs.h>
19#include <mach/spear.h>
20
21#define PLL1_CTR (MISC_BASE + 0x008)
22#define PLL1_FRQ (MISC_BASE + 0x00C)
23#define PLL1_MOD (MISC_BASE + 0x010)
24#define PLL2_CTR (MISC_BASE + 0x014)
25/* PLL_CTR register masks */
26#define PLL_ENABLE 2
27#define PLL_MODE_SHIFT 4
28#define PLL_MODE_MASK 0x3
29#define PLL_MODE_NORMAL 0
30#define PLL_MODE_FRACTION 1
31#define PLL_MODE_DITH_DSB 2
32#define PLL_MODE_DITH_SSB 3
33
34#define PLL2_FRQ (MISC_BASE + 0x018)
35/* PLL FRQ register masks */
36#define PLL_DIV_N_SHIFT 0
37#define PLL_DIV_N_MASK 0xFF
38#define PLL_DIV_P_SHIFT 8
39#define PLL_DIV_P_MASK 0x7
40#define PLL_NORM_FDBK_M_SHIFT 24
41#define PLL_NORM_FDBK_M_MASK 0xFF
42#define PLL_DITH_FDBK_M_SHIFT 16
43#define PLL_DITH_FDBK_M_MASK 0xFFFF
44
45#define PLL2_MOD (MISC_BASE + 0x01C)
46#define PLL_CLK_CFG (MISC_BASE + 0x020)
47#define CORE_CLK_CFG (MISC_BASE + 0x024)
48/* CORE CLK CFG register masks */
49#define PLL_HCLK_RATIO_SHIFT 10
50#define PLL_HCLK_RATIO_MASK 0x3
51#define HCLK_PCLK_RATIO_SHIFT 8
52#define HCLK_PCLK_RATIO_MASK 0x3
53
54#define PERIP_CLK_CFG (MISC_BASE + 0x028)
55/* PERIP_CLK_CFG register masks */
56#define CLCD_CLK_SHIFT 2
57#define CLCD_CLK_MASK 0x3
58#define UART_CLK_SHIFT 4
59#define UART_CLK_MASK 0x1
60#define FIRDA_CLK_SHIFT 5
61#define FIRDA_CLK_MASK 0x3
62#define GPT0_CLK_SHIFT 8
63#define GPT1_CLK_SHIFT 10
64#define GPT2_CLK_SHIFT 11
65#define GPT3_CLK_SHIFT 12
66#define GPT_CLK_MASK 0x1
67#define AUX_CLK_PLL3_VAL 0
68#define AUX_CLK_PLL1_VAL 1
69
70#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
71/* PERIP1_CLK_ENB register masks */
72#define UART0_CLK_ENB 3
73#define UART1_CLK_ENB 4
74#define SSP0_CLK_ENB 5
75#define SSP1_CLK_ENB 6
76#define I2C_CLK_ENB 7
77#define JPEG_CLK_ENB 8
78#define FSMC_CLK_ENB 9
79#define FIRDA_CLK_ENB 10
80#define GPT2_CLK_ENB 11
81#define GPT3_CLK_ENB 12
82#define GPIO2_CLK_ENB 13
83#define SSP2_CLK_ENB 14
84#define ADC_CLK_ENB 15
85#define GPT1_CLK_ENB 11
86#define RTC_CLK_ENB 17
87#define GPIO1_CLK_ENB 18
88#define DMA_CLK_ENB 19
89#define SMI_CLK_ENB 21
90#define CLCD_CLK_ENB 22
91#define GMAC_CLK_ENB 23
92#define USBD_CLK_ENB 24
93#define USBH0_CLK_ENB 25
94#define USBH1_CLK_ENB 26
95
96#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
97#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
98#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
99/* gpt synthesizer register masks */
100#define GPT_MSCALE_SHIFT 0
101#define GPT_MSCALE_MASK 0xFFF
102#define GPT_NSCALE_SHIFT 12
103#define GPT_NSCALE_MASK 0xF
104
105#define AMEM_CLK_CFG (MISC_BASE + 0x050)
106#define EXPI_CLK_CFG (MISC_BASE + 0x054)
107#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
108#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
109#define UART_CLK_SYNT (MISC_BASE + 0x064)
110#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
111#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
112#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
113#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
114#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
115/* aux clk synthesiser register masks for irda to ras4 */
116#define AUX_SYNT_ENB 31
117#define AUX_EQ_SEL_SHIFT 30
118#define AUX_EQ_SEL_MASK 1
119#define AUX_EQ1_SEL 0
120#define AUX_EQ2_SEL 1
121#define AUX_XSCALE_SHIFT 16
122#define AUX_XSCALE_MASK 0xFFF
123#define AUX_YSCALE_SHIFT 0
124#define AUX_YSCALE_MASK 0xFFF
125
126/* root clks */
127/* 32 KHz oscillator clock */
128static struct clk osc_32k_clk = {
129 .flags = ALWAYS_ENABLED,
130 .rate = 32000,
131};
132
133/* 30 MHz oscillator clock */
134static struct clk osc_30m_clk = {
135 .flags = ALWAYS_ENABLED,
136 .rate = 30000000,
137};
138
139/* clock derived from 32 KHz osc clk */
140/* rtc clock */
141static struct clk rtc_clk = {
142 .pclk = &osc_32k_clk,
143 .en_reg = PERIP1_CLK_ENB,
144 .en_reg_bit = RTC_CLK_ENB,
145 .recalc = &follow_parent,
146};
147
148/* clock derived from 30 MHz osc clk */
149/* pll masks structure */
150static struct pll_clk_masks pll1_masks = {
151 .mode_mask = PLL_MODE_MASK,
152 .mode_shift = PLL_MODE_SHIFT,
153 .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
154 .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
155 .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
156 .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
157 .div_p_mask = PLL_DIV_P_MASK,
158 .div_p_shift = PLL_DIV_P_SHIFT,
159 .div_n_mask = PLL_DIV_N_MASK,
160 .div_n_shift = PLL_DIV_N_SHIFT,
161};
162
163/* pll1 configuration structure */
164static struct pll_clk_config pll1_config = {
165 .mode_reg = PLL1_CTR,
166 .cfg_reg = PLL1_FRQ,
167 .masks = &pll1_masks,
168};
169
170/* pll rate configuration table, in ascending order of rates */
171struct pll_rate_tbl pll_rtbl[] = {
172 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
173 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
174};
175
176/* PLL1 clock */
177static struct clk pll1_clk = {
178 .flags = ENABLED_ON_INIT,
179 .pclk = &osc_30m_clk,
180 .en_reg = PLL1_CTR,
181 .en_reg_bit = PLL_ENABLE,
182 .calc_rate = &pll_calc_rate,
183 .recalc = &pll_clk_recalc,
184 .set_rate = &pll_clk_set_rate,
185 .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
186 .private_data = &pll1_config,
187};
188
189/* PLL3 48 MHz clock */
190static struct clk pll3_48m_clk = {
191 .flags = ALWAYS_ENABLED,
192 .pclk = &osc_30m_clk,
193 .rate = 48000000,
194};
195
196/* watch dog timer clock */
197static struct clk wdt_clk = {
198 .flags = ALWAYS_ENABLED,
199 .pclk = &osc_30m_clk,
200 .recalc = &follow_parent,
201};
202
203/* clock derived from pll1 clk */
204/* cpu clock */
205static struct clk cpu_clk = {
206 .flags = ALWAYS_ENABLED,
207 .pclk = &pll1_clk,
208 .recalc = &follow_parent,
209};
210
211/* ahb masks structure */
212static struct bus_clk_masks ahb_masks = {
213 .mask = PLL_HCLK_RATIO_MASK,
214 .shift = PLL_HCLK_RATIO_SHIFT,
215};
216
217/* ahb configuration structure */
218static struct bus_clk_config ahb_config = {
219 .reg = CORE_CLK_CFG,
220 .masks = &ahb_masks,
221};
222
223/* ahb rate configuration table, in ascending order of rates */
224struct bus_rate_tbl bus_rtbl[] = {
225 {.div = 3}, /* == parent divided by 4 */
226 {.div = 2}, /* == parent divided by 3 */
227 {.div = 1}, /* == parent divided by 2 */
228 {.div = 0}, /* == parent divided by 1 */
229};
230
231/* ahb clock */
232static struct clk ahb_clk = {
233 .flags = ALWAYS_ENABLED,
234 .pclk = &pll1_clk,
235 .calc_rate = &bus_calc_rate,
236 .recalc = &bus_clk_recalc,
237 .set_rate = &bus_clk_set_rate,
238 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
239 .private_data = &ahb_config,
240};
241
242/* auxiliary synthesizers masks */
243static struct aux_clk_masks aux_masks = {
244 .eq_sel_mask = AUX_EQ_SEL_MASK,
245 .eq_sel_shift = AUX_EQ_SEL_SHIFT,
246 .eq1_mask = AUX_EQ1_SEL,
247 .eq2_mask = AUX_EQ2_SEL,
248 .xscale_sel_mask = AUX_XSCALE_MASK,
249 .xscale_sel_shift = AUX_XSCALE_SHIFT,
250 .yscale_sel_mask = AUX_YSCALE_MASK,
251 .yscale_sel_shift = AUX_YSCALE_SHIFT,
252};
253
254/* uart configurations */
255static struct aux_clk_config uart_synth_config = {
256 .synth_reg = UART_CLK_SYNT,
257 .masks = &aux_masks,
258};
259
260/* aux rate configuration table, in ascending order of rates */
261struct aux_rate_tbl aux_rtbl[] = {
262 /* For PLL1 = 332 MHz */
263 {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
264 {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
265 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
266};
267
268/* uart synth clock */
269static struct clk uart_synth_clk = {
270 .en_reg = UART_CLK_SYNT,
271 .en_reg_bit = AUX_SYNT_ENB,
272 .pclk = &pll1_clk,
273 .calc_rate = &aux_calc_rate,
274 .recalc = &aux_clk_recalc,
275 .set_rate = &aux_clk_set_rate,
276 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
277 .private_data = &uart_synth_config,
278};
279
280/* uart parents */
281static struct pclk_info uart_pclk_info[] = {
282 {
283 .pclk = &uart_synth_clk,
284 .pclk_val = AUX_CLK_PLL1_VAL,
285 }, {
286 .pclk = &pll3_48m_clk,
287 .pclk_val = AUX_CLK_PLL3_VAL,
288 },
289};
290
291/* uart parent select structure */
292static struct pclk_sel uart_pclk_sel = {
293 .pclk_info = uart_pclk_info,
294 .pclk_count = ARRAY_SIZE(uart_pclk_info),
295 .pclk_sel_reg = PERIP_CLK_CFG,
296 .pclk_sel_mask = UART_CLK_MASK,
297};
298
299/* uart0 clock */
300static struct clk uart0_clk = {
301 .en_reg = PERIP1_CLK_ENB,
302 .en_reg_bit = UART0_CLK_ENB,
303 .pclk_sel = &uart_pclk_sel,
304 .pclk_sel_shift = UART_CLK_SHIFT,
305 .recalc = &follow_parent,
306};
307
308/* uart1 clock */
309static struct clk uart1_clk = {
310 .en_reg = PERIP1_CLK_ENB,
311 .en_reg_bit = UART1_CLK_ENB,
312 .pclk_sel = &uart_pclk_sel,
313 .pclk_sel_shift = UART_CLK_SHIFT,
314 .recalc = &follow_parent,
315};
316
317/* firda configurations */
318static struct aux_clk_config firda_synth_config = {
319 .synth_reg = FIRDA_CLK_SYNT,
320 .masks = &aux_masks,
321};
322
323/* firda synth clock */
324static struct clk firda_synth_clk = {
325 .en_reg = FIRDA_CLK_SYNT,
326 .en_reg_bit = AUX_SYNT_ENB,
327 .pclk = &pll1_clk,
328 .calc_rate = &aux_calc_rate,
329 .recalc = &aux_clk_recalc,
330 .set_rate = &aux_clk_set_rate,
331 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
332 .private_data = &firda_synth_config,
333};
334
335/* firda parents */
336static struct pclk_info firda_pclk_info[] = {
337 {
338 .pclk = &firda_synth_clk,
339 .pclk_val = AUX_CLK_PLL1_VAL,
340 }, {
341 .pclk = &pll3_48m_clk,
342 .pclk_val = AUX_CLK_PLL3_VAL,
343 },
344};
345
346/* firda parent select structure */
347static struct pclk_sel firda_pclk_sel = {
348 .pclk_info = firda_pclk_info,
349 .pclk_count = ARRAY_SIZE(firda_pclk_info),
350 .pclk_sel_reg = PERIP_CLK_CFG,
351 .pclk_sel_mask = FIRDA_CLK_MASK,
352};
353
354/* firda clock */
355static struct clk firda_clk = {
356 .en_reg = PERIP1_CLK_ENB,
357 .en_reg_bit = FIRDA_CLK_ENB,
358 .pclk_sel = &firda_pclk_sel,
359 .pclk_sel_shift = FIRDA_CLK_SHIFT,
360 .recalc = &follow_parent,
361};
362
363/* clcd configurations */
364static struct aux_clk_config clcd_synth_config = {
365 .synth_reg = CLCD_CLK_SYNT,
366 .masks = &aux_masks,
367};
368
369/* firda synth clock */
370static struct clk clcd_synth_clk = {
371 .en_reg = CLCD_CLK_SYNT,
372 .en_reg_bit = AUX_SYNT_ENB,
373 .pclk = &pll1_clk,
374 .calc_rate = &aux_calc_rate,
375 .recalc = &aux_clk_recalc,
376 .set_rate = &aux_clk_set_rate,
377 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
378 .private_data = &clcd_synth_config,
379};
380
381/* clcd parents */
382static struct pclk_info clcd_pclk_info[] = {
383 {
384 .pclk = &clcd_synth_clk,
385 .pclk_val = AUX_CLK_PLL1_VAL,
386 }, {
387 .pclk = &pll3_48m_clk,
388 .pclk_val = AUX_CLK_PLL3_VAL,
389 },
390};
391
392/* clcd parent select structure */
393static struct pclk_sel clcd_pclk_sel = {
394 .pclk_info = clcd_pclk_info,
395 .pclk_count = ARRAY_SIZE(clcd_pclk_info),
396 .pclk_sel_reg = PERIP_CLK_CFG,
397 .pclk_sel_mask = CLCD_CLK_MASK,
398};
399
400/* clcd clock */
401static struct clk clcd_clk = {
402 .en_reg = PERIP1_CLK_ENB,
403 .en_reg_bit = CLCD_CLK_ENB,
404 .pclk_sel = &clcd_pclk_sel,
405 .pclk_sel_shift = CLCD_CLK_SHIFT,
406 .recalc = &follow_parent,
407};
408
409/* gpt synthesizer masks */
410static struct gpt_clk_masks gpt_masks = {
411 .mscale_sel_mask = GPT_MSCALE_MASK,
412 .mscale_sel_shift = GPT_MSCALE_SHIFT,
413 .nscale_sel_mask = GPT_NSCALE_MASK,
414 .nscale_sel_shift = GPT_NSCALE_SHIFT,
415};
416
417/* gpt rate configuration table, in ascending order of rates */
418struct gpt_rate_tbl gpt_rtbl[] = {
419 /* For pll1 = 332 MHz */
420 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
421 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
422 {.mscale = 1, .nscale = 0}, /* 83 MHz */
423};
424
425/* gpt0 synth clk config*/
426static struct gpt_clk_config gpt0_synth_config = {
427 .synth_reg = PRSC1_CLK_CFG,
428 .masks = &gpt_masks,
429};
430
431/* gpt synth clock */
432static struct clk gpt0_synth_clk = {
433 .flags = ALWAYS_ENABLED,
434 .pclk = &pll1_clk,
435 .calc_rate = &gpt_calc_rate,
436 .recalc = &gpt_clk_recalc,
437 .set_rate = &gpt_clk_set_rate,
438 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
439 .private_data = &gpt0_synth_config,
440};
441
442/* gpt parents */
443static struct pclk_info gpt0_pclk_info[] = {
444 {
445 .pclk = &gpt0_synth_clk,
446 .pclk_val = AUX_CLK_PLL1_VAL,
447 }, {
448 .pclk = &pll3_48m_clk,
449 .pclk_val = AUX_CLK_PLL3_VAL,
450 },
451};
452
453/* gpt parent select structure */
454static struct pclk_sel gpt0_pclk_sel = {
455 .pclk_info = gpt0_pclk_info,
456 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
457 .pclk_sel_reg = PERIP_CLK_CFG,
458 .pclk_sel_mask = GPT_CLK_MASK,
459};
460
461/* gpt0 ARM1 subsystem timer clock */
462static struct clk gpt0_clk = {
463 .flags = ALWAYS_ENABLED,
464 .pclk_sel = &gpt0_pclk_sel,
465 .pclk_sel_shift = GPT0_CLK_SHIFT,
466 .recalc = &follow_parent,
467};
468
469
470/* Note: gpt0 and gpt1 share same parent clocks */
471/* gpt parent select structure */
472static struct pclk_sel gpt1_pclk_sel = {
473 .pclk_info = gpt0_pclk_info,
474 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
475 .pclk_sel_reg = PERIP_CLK_CFG,
476 .pclk_sel_mask = GPT_CLK_MASK,
477};
478
479/* gpt1 timer clock */
480static struct clk gpt1_clk = {
481 .flags = ALWAYS_ENABLED,
482 .pclk_sel = &gpt1_pclk_sel,
483 .pclk_sel_shift = GPT1_CLK_SHIFT,
484 .recalc = &follow_parent,
485};
486
487/* gpt2 synth clk config*/
488static struct gpt_clk_config gpt2_synth_config = {
489 .synth_reg = PRSC2_CLK_CFG,
490 .masks = &gpt_masks,
491};
492
493/* gpt synth clock */
494static struct clk gpt2_synth_clk = {
495 .flags = ALWAYS_ENABLED,
496 .pclk = &pll1_clk,
497 .calc_rate = &gpt_calc_rate,
498 .recalc = &gpt_clk_recalc,
499 .set_rate = &gpt_clk_set_rate,
500 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
501 .private_data = &gpt2_synth_config,
502};
503
504/* gpt parents */
505static struct pclk_info gpt2_pclk_info[] = {
506 {
507 .pclk = &gpt2_synth_clk,
508 .pclk_val = AUX_CLK_PLL1_VAL,
509 }, {
510 .pclk = &pll3_48m_clk,
511 .pclk_val = AUX_CLK_PLL3_VAL,
512 },
513};
514
515/* gpt parent select structure */
516static struct pclk_sel gpt2_pclk_sel = {
517 .pclk_info = gpt2_pclk_info,
518 .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
519 .pclk_sel_reg = PERIP_CLK_CFG,
520 .pclk_sel_mask = GPT_CLK_MASK,
521};
522
523/* gpt2 timer clock */
524static struct clk gpt2_clk = {
525 .flags = ALWAYS_ENABLED,
526 .pclk_sel = &gpt2_pclk_sel,
527 .pclk_sel_shift = GPT2_CLK_SHIFT,
528 .recalc = &follow_parent,
529};
530
531/* gpt3 synth clk config*/
532static struct gpt_clk_config gpt3_synth_config = {
533 .synth_reg = PRSC3_CLK_CFG,
534 .masks = &gpt_masks,
535};
536
537/* gpt synth clock */
538static struct clk gpt3_synth_clk = {
539 .flags = ALWAYS_ENABLED,
540 .pclk = &pll1_clk,
541 .calc_rate = &gpt_calc_rate,
542 .recalc = &gpt_clk_recalc,
543 .set_rate = &gpt_clk_set_rate,
544 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
545 .private_data = &gpt3_synth_config,
546};
547
548/* gpt parents */
549static struct pclk_info gpt3_pclk_info[] = {
550 {
551 .pclk = &gpt3_synth_clk,
552 .pclk_val = AUX_CLK_PLL1_VAL,
553 }, {
554 .pclk = &pll3_48m_clk,
555 .pclk_val = AUX_CLK_PLL3_VAL,
556 },
557};
558
559/* gpt parent select structure */
560static struct pclk_sel gpt3_pclk_sel = {
561 .pclk_info = gpt3_pclk_info,
562 .pclk_count = ARRAY_SIZE(gpt3_pclk_info),
563 .pclk_sel_reg = PERIP_CLK_CFG,
564 .pclk_sel_mask = GPT_CLK_MASK,
565};
566
567/* gpt3 timer clock */
568static struct clk gpt3_clk = {
569 .flags = ALWAYS_ENABLED,
570 .pclk_sel = &gpt3_pclk_sel,
571 .pclk_sel_shift = GPT3_CLK_SHIFT,
572 .recalc = &follow_parent,
573};
574
575/* clock derived from pll3 clk */
576/* usbh0 clock */
577static struct clk usbh0_clk = {
578 .pclk = &pll3_48m_clk,
579 .en_reg = PERIP1_CLK_ENB,
580 .en_reg_bit = USBH0_CLK_ENB,
581 .recalc = &follow_parent,
582};
583
584/* usbh1 clock */
585static struct clk usbh1_clk = {
586 .pclk = &pll3_48m_clk,
587 .en_reg = PERIP1_CLK_ENB,
588 .en_reg_bit = USBH1_CLK_ENB,
589 .recalc = &follow_parent,
590};
591
592/* usbd clock */
593static struct clk usbd_clk = {
594 .pclk = &pll3_48m_clk,
595 .en_reg = PERIP1_CLK_ENB,
596 .en_reg_bit = USBD_CLK_ENB,
597 .recalc = &follow_parent,
598};
599
600/* clock derived from ahb clk */
601/* apb masks structure */
602static struct bus_clk_masks apb_masks = {
603 .mask = HCLK_PCLK_RATIO_MASK,
604 .shift = HCLK_PCLK_RATIO_SHIFT,
605};
606
607/* apb configuration structure */
608static struct bus_clk_config apb_config = {
609 .reg = CORE_CLK_CFG,
610 .masks = &apb_masks,
611};
612
613/* apb clock */
614static struct clk apb_clk = {
615 .flags = ALWAYS_ENABLED,
616 .pclk = &ahb_clk,
617 .calc_rate = &bus_calc_rate,
618 .recalc = &bus_clk_recalc,
619 .set_rate = &bus_clk_set_rate,
620 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
621 .private_data = &apb_config,
622};
623
624/* i2c clock */
625static struct clk i2c_clk = {
626 .pclk = &ahb_clk,
627 .en_reg = PERIP1_CLK_ENB,
628 .en_reg_bit = I2C_CLK_ENB,
629 .recalc = &follow_parent,
630};
631
632/* dma clock */
633static struct clk dma_clk = {
634 .pclk = &ahb_clk,
635 .en_reg = PERIP1_CLK_ENB,
636 .en_reg_bit = DMA_CLK_ENB,
637 .recalc = &follow_parent,
638};
639
640/* jpeg clock */
641static struct clk jpeg_clk = {
642 .pclk = &ahb_clk,
643 .en_reg = PERIP1_CLK_ENB,
644 .en_reg_bit = JPEG_CLK_ENB,
645 .recalc = &follow_parent,
646};
647
648/* gmac clock */
649static struct clk gmac_clk = {
650 .pclk = &ahb_clk,
651 .en_reg = PERIP1_CLK_ENB,
652 .en_reg_bit = GMAC_CLK_ENB,
653 .recalc = &follow_parent,
654};
655
656/* smi clock */
657static struct clk smi_clk = {
658 .pclk = &ahb_clk,
659 .en_reg = PERIP1_CLK_ENB,
660 .en_reg_bit = SMI_CLK_ENB,
661 .recalc = &follow_parent,
662};
663
664/* fsmc clock */
665static struct clk fsmc_clk = {
666 .pclk = &ahb_clk,
667 .en_reg = PERIP1_CLK_ENB,
668 .en_reg_bit = FSMC_CLK_ENB,
669 .recalc = &follow_parent,
670};
671
672/* clock derived from apb clk */
673/* adc clock */
674static struct clk adc_clk = {
675 .pclk = &apb_clk,
676 .en_reg = PERIP1_CLK_ENB,
677 .en_reg_bit = ADC_CLK_ENB,
678 .recalc = &follow_parent,
679};
680
681/* ssp0 clock */
682static struct clk ssp0_clk = {
683 .pclk = &apb_clk,
684 .en_reg = PERIP1_CLK_ENB,
685 .en_reg_bit = SSP0_CLK_ENB,
686 .recalc = &follow_parent,
687};
688
689/* ssp1 clock */
690static struct clk ssp1_clk = {
691 .pclk = &apb_clk,
692 .en_reg = PERIP1_CLK_ENB,
693 .en_reg_bit = SSP1_CLK_ENB,
694 .recalc = &follow_parent,
695};
696
697/* ssp2 clock */
698static struct clk ssp2_clk = {
699 .pclk = &apb_clk,
700 .en_reg = PERIP1_CLK_ENB,
701 .en_reg_bit = SSP2_CLK_ENB,
702 .recalc = &follow_parent,
703};
704
705/* gpio0 ARM subsystem clock */
706static struct clk gpio0_clk = {
707 .flags = ALWAYS_ENABLED,
708 .pclk = &apb_clk,
709 .recalc = &follow_parent,
710};
711
712/* gpio1 clock */
713static struct clk gpio1_clk = {
714 .pclk = &apb_clk,
715 .en_reg = PERIP1_CLK_ENB,
716 .en_reg_bit = GPIO1_CLK_ENB,
717 .recalc = &follow_parent,
718};
719
720/* gpio2 clock */
721static struct clk gpio2_clk = {
722 .pclk = &apb_clk,
723 .en_reg = PERIP1_CLK_ENB,
724 .en_reg_bit = GPIO2_CLK_ENB,
725 .recalc = &follow_parent,
726};
727
728static struct clk dummy_apb_pclk;
729
730/* array of all spear 6xx clock lookups */
731static struct clk_lookup spear_clk_lookups[] = {
732 CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
733 /* root clks */
734 CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
735 CLKDEV_INIT(NULL, "osc_30m_clk", &osc_30m_clk),
736 /* clock derived from 32 KHz os clk */
737 CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
738 /* clock derived from 30 MHz os clk */
739 CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
740 CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
741 CLKDEV_INIT("wdt", NULL, &wdt_clk),
742 /* clock derived from pll1 clk */
743 CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
744 CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
745 CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
746 CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
747 CLKDEV_INIT(NULL, "clcd_synth_clk", &clcd_synth_clk),
748 CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
749 CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
750 CLKDEV_INIT(NULL, "gpt3_synth_clk", &gpt3_synth_clk),
751 CLKDEV_INIT("d0000000.serial", NULL, &uart0_clk),
752 CLKDEV_INIT("d0080000.serial", NULL, &uart1_clk),
753 CLKDEV_INIT("firda", NULL, &firda_clk),
754 CLKDEV_INIT("clcd", NULL, &clcd_clk),
755 CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
756 CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
757 CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
758 CLKDEV_INIT("gpt3", NULL, &gpt3_clk),
759 /* clock derived from pll3 clk */
760 CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
761 CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
762 CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
763 /* clock derived from ahb clk */
764 CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
765 CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk),
766 CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
767 CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
768 CLKDEV_INIT("gmac", NULL, &gmac_clk),
769 CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
770 CLKDEV_INIT("d1800000.flash", NULL, &fsmc_clk),
771 /* clock derived from apb clk */
772 CLKDEV_INIT("adc", NULL, &adc_clk),
773 CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
774 CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
775 CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
776 CLKDEV_INIT("f0100000.gpio", NULL, &gpio0_clk),
777 CLKDEV_INIT("fc980000.gpio", NULL, &gpio1_clk),
778 CLKDEV_INIT("d8100000.gpio", NULL, &gpio2_clk),
779};
780
781void __init spear6xx_clk_init(void)
782{
783 int i;
784
785 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
786 clk_register(&spear_clk_lookups[i]);
787
788 clk_init();
789}
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
index 2b9aaa6cdd11..179e45774b3a 100644
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -14,6 +14,8 @@
14#ifndef __MACH_MISC_REGS_H 14#ifndef __MACH_MISC_REGS_H
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/spear.h>
18
17#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE) 19#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
18#define DMA_CHN_CFG (MISC_BASE + 0x0A0) 20#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
19 21
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 7ae4d5be6cb5..2e2e3596583e 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -419,9 +419,6 @@ struct map_desc spear6xx_io_desc[] __initdata = {
419void __init spear6xx_map_io(void) 419void __init spear6xx_map_io(void)
420{ 420{
421 iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); 421 iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
422
423 /* This will initialize clock framework */
424 spear6xx_clk_init();
425} 422}
426 423
427static void __init spear6xx_timer_init(void) 424static void __init spear6xx_timer_init(void)
@@ -429,6 +426,8 @@ static void __init spear6xx_timer_init(void)
429 char pclk_name[] = "pll3_48m_clk"; 426 char pclk_name[] = "pll3_48m_clk";
430 struct clk *gpt_clk, *pclk; 427 struct clk *gpt_clk, *pclk;
431 428
429 spear6xx_clk_init();
430
432 /* get the system timer clock */ 431 /* get the system timer clock */
433 gpt_clk = clk_get_sys("gpt0", NULL); 432 gpt_clk = clk_get_sys("gpt0", NULL);
434 if (IS_ERR(gpt_clk)) { 433 if (IS_ERR(gpt_clk)) {
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 880d02ec89d4..ef7099eea0f2 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -17,6 +17,7 @@ config UX500_SOC_DB5500
17config UX500_SOC_DB8500 17config UX500_SOC_DB8500
18 bool 18 bool
19 select MFD_DB8500_PRCMU 19 select MFD_DB8500_PRCMU
20 select REGULATOR
20 select REGULATOR_DB8500_PRCMU 21 select REGULATOR_DB8500_PRCMU
21 select CPU_FREQ_TABLE if CPU_FREQ 22 select CPU_FREQ_TABLE if CPU_FREQ
22 23
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index d2058ef8345f..eff5842f6232 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -99,7 +99,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
99 */ 99 */
100 write_pen_release(cpu_logical_map(cpu)); 100 write_pen_release(cpu_logical_map(cpu));
101 101
102 gic_raise_softirq(cpumask_of(cpu), 1); 102 smp_send_reschedule(cpu);
103 103
104 timeout = jiffies + (1 * HZ); 104 timeout = jiffies + (1 * HZ);
105 while (time_before(jiffies, timeout)) { 105 while (time_before(jiffies, timeout)) {
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 8070145ccb98..3f26db4ee8e6 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -305,6 +305,7 @@ struct omap_hwmod_sysc_fields {
305 * @rev_offs: IP block revision register offset (from module base addr) 305 * @rev_offs: IP block revision register offset (from module base addr)
306 * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) 306 * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
307 * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) 307 * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
308 * @srst_udelay: Delay needed after doing a softreset in usecs
308 * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART} 309 * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
309 * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported 310 * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
310 * @clockact: the default value of the module CLOCKACTIVITY bits 311 * @clockact: the default value of the module CLOCKACTIVITY bits
@@ -330,9 +331,10 @@ struct omap_hwmod_class_sysconfig {
330 u16 sysc_offs; 331 u16 sysc_offs;
331 u16 syss_offs; 332 u16 syss_offs;
332 u16 sysc_flags; 333 u16 sysc_flags;
334 struct omap_hwmod_sysc_fields *sysc_fields;
335 u8 srst_udelay;
333 u8 idlemodes; 336 u8 idlemodes;
334 u8 clockact; 337 u8 clockact;
335 struct omap_hwmod_sysc_fields *sysc_fields;
336}; 338};
337 339
338/** 340/**
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index eec98afa0f83..f9a8c5341ee9 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -348,7 +348,6 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
348 sdrc_actim_ctrl_b_1, sdrc_mr_1); 348 sdrc_actim_ctrl_b_1, sdrc_mr_1);
349} 349}
350 350
351#ifdef CONFIG_PM
352void omap3_sram_restore_context(void) 351void omap3_sram_restore_context(void)
353{ 352{
354 omap_sram_ceil = omap_sram_base + omap_sram_size; 353 omap_sram_ceil = omap_sram_base + omap_sram_size;
@@ -358,17 +357,18 @@ void omap3_sram_restore_context(void)
358 omap3_sram_configure_core_dpll_sz); 357 omap3_sram_configure_core_dpll_sz);
359 omap_push_sram_idle(); 358 omap_push_sram_idle();
360} 359}
361#endif /* CONFIG_PM */
362
363#endif /* CONFIG_ARCH_OMAP3 */
364 360
365static inline int omap34xx_sram_init(void) 361static inline int omap34xx_sram_init(void)
366{ 362{
367#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
368 omap3_sram_restore_context(); 363 omap3_sram_restore_context();
369#endif
370 return 0; 364 return 0;
371} 365}
366#else
367static inline int omap34xx_sram_init(void)
368{
369 return 0;
370}
371#endif /* CONFIG_ARCH_OMAP3 */
372 372
373static inline int am33xx_sram_init(void) 373static inline int am33xx_sram_init(void)
374{ 374{
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 6c066fcb2979..387655b5ce05 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -13,6 +13,7 @@ config ARCH_SPEAR3XX
13 select ARM_VIC 13 select ARM_VIC
14 select CPU_ARM926T 14 select CPU_ARM926T
15 select USE_OF 15 select USE_OF
16 select PINCTRL
16 help 17 help
17 Supports for ARM's SPEAR3XX family 18 Supports for ARM's SPEAR3XX family
18 19
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 4af6258d0fee..38f1235f4632 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,6 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := clock.o restart.o time.o pl080.o 6obj-y := restart.o time.o pl080.o
7 7
8obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o 8obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
deleted file mode 100644
index 67dd00381ea6..000000000000
--- a/arch/arm/plat-spear/clock.c
+++ /dev/null
@@ -1,1005 +0,0 @@
1/*
2 * arch/arm/plat-spear/clock.c
3 *
4 * Clock framework for SPEAr platform
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/bug.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/module.h>
21#include <linux/spinlock.h>
22#include <plat/clock.h>
23
24static DEFINE_SPINLOCK(clocks_lock);
25static LIST_HEAD(root_clks);
26#ifdef CONFIG_DEBUG_FS
27static LIST_HEAD(clocks);
28#endif
29
30static void propagate_rate(struct clk *, int on_init);
31#ifdef CONFIG_DEBUG_FS
32static int clk_debugfs_reparent(struct clk *);
33#endif
34
35static int generic_clk_enable(struct clk *clk)
36{
37 unsigned int val;
38
39 if (!clk->en_reg)
40 return -EFAULT;
41
42 val = readl(clk->en_reg);
43 if (unlikely(clk->flags & RESET_TO_ENABLE))
44 val &= ~(1 << clk->en_reg_bit);
45 else
46 val |= 1 << clk->en_reg_bit;
47
48 writel(val, clk->en_reg);
49
50 return 0;
51}
52
53static void generic_clk_disable(struct clk *clk)
54{
55 unsigned int val;
56
57 if (!clk->en_reg)
58 return;
59
60 val = readl(clk->en_reg);
61 if (unlikely(clk->flags & RESET_TO_ENABLE))
62 val |= 1 << clk->en_reg_bit;
63 else
64 val &= ~(1 << clk->en_reg_bit);
65
66 writel(val, clk->en_reg);
67}
68
69/* generic clk ops */
70static struct clkops generic_clkops = {
71 .enable = generic_clk_enable,
72 .disable = generic_clk_disable,
73};
74
75/* returns current programmed clocks clock info structure */
76static struct pclk_info *pclk_info_get(struct clk *clk)
77{
78 unsigned int val, i;
79 struct pclk_info *info = NULL;
80
81 val = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift)
82 & clk->pclk_sel->pclk_sel_mask;
83
84 for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
85 if (clk->pclk_sel->pclk_info[i].pclk_val == val)
86 info = &clk->pclk_sel->pclk_info[i];
87 }
88
89 return info;
90}
91
92/*
93 * Set Update pclk, and pclk_info of clk and add clock sibling node to current
94 * parents children list
95 */
96static void clk_reparent(struct clk *clk, struct pclk_info *pclk_info)
97{
98 unsigned long flags;
99
100 spin_lock_irqsave(&clocks_lock, flags);
101 list_del(&clk->sibling);
102 list_add(&clk->sibling, &pclk_info->pclk->children);
103
104 clk->pclk = pclk_info->pclk;
105 spin_unlock_irqrestore(&clocks_lock, flags);
106
107#ifdef CONFIG_DEBUG_FS
108 clk_debugfs_reparent(clk);
109#endif
110}
111
112static void do_clk_disable(struct clk *clk)
113{
114 if (!clk)
115 return;
116
117 if (!clk->usage_count) {
118 WARN_ON(1);
119 return;
120 }
121
122 clk->usage_count--;
123
124 if (clk->usage_count == 0) {
125 /*
126 * Surely, there are no active childrens or direct users
127 * of this clock
128 */
129 if (clk->pclk)
130 do_clk_disable(clk->pclk);
131
132 if (clk->ops && clk->ops->disable)
133 clk->ops->disable(clk);
134 }
135}
136
137static int do_clk_enable(struct clk *clk)
138{
139 int ret = 0;
140
141 if (!clk)
142 return -EFAULT;
143
144 if (clk->usage_count == 0) {
145 if (clk->pclk) {
146 ret = do_clk_enable(clk->pclk);
147 if (ret)
148 goto err;
149 }
150 if (clk->ops && clk->ops->enable) {
151 ret = clk->ops->enable(clk);
152 if (ret) {
153 if (clk->pclk)
154 do_clk_disable(clk->pclk);
155 goto err;
156 }
157 }
158 /*
159 * Since the clock is going to be used for the first
160 * time please reclac
161 */
162 if (clk->recalc) {
163 ret = clk->recalc(clk);
164 if (ret)
165 goto err;
166 }
167 }
168 clk->usage_count++;
169err:
170 return ret;
171}
172
173/*
174 * clk_enable - inform the system when the clock source should be running.
175 * @clk: clock source
176 *
177 * If the clock can not be enabled/disabled, this should return success.
178 *
179 * Returns success (0) or negative errno.
180 */
181int clk_enable(struct clk *clk)
182{
183 unsigned long flags;
184 int ret = 0;
185
186 spin_lock_irqsave(&clocks_lock, flags);
187 ret = do_clk_enable(clk);
188 spin_unlock_irqrestore(&clocks_lock, flags);
189 return ret;
190}
191EXPORT_SYMBOL(clk_enable);
192
193/*
194 * clk_disable - inform the system when the clock source is no longer required.
195 * @clk: clock source
196 *
197 * Inform the system that a clock source is no longer required by
198 * a driver and may be shut down.
199 *
200 * Implementation detail: if the clock source is shared between
201 * multiple drivers, clk_enable() calls must be balanced by the
202 * same number of clk_disable() calls for the clock source to be
203 * disabled.
204 */
205void clk_disable(struct clk *clk)
206{
207 unsigned long flags;
208
209 spin_lock_irqsave(&clocks_lock, flags);
210 do_clk_disable(clk);
211 spin_unlock_irqrestore(&clocks_lock, flags);
212}
213EXPORT_SYMBOL(clk_disable);
214
215/**
216 * clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
217 * This is only valid once the clock source has been enabled.
218 * @clk: clock source
219 */
220unsigned long clk_get_rate(struct clk *clk)
221{
222 unsigned long flags, rate;
223
224 spin_lock_irqsave(&clocks_lock, flags);
225 rate = clk->rate;
226 spin_unlock_irqrestore(&clocks_lock, flags);
227
228 return rate;
229}
230EXPORT_SYMBOL(clk_get_rate);
231
232/**
233 * clk_set_parent - set the parent clock source for this clock
234 * @clk: clock source
235 * @parent: parent clock source
236 *
237 * Returns success (0) or negative errno.
238 */
239int clk_set_parent(struct clk *clk, struct clk *parent)
240{
241 int i, found = 0, val = 0;
242 unsigned long flags;
243
244 if (!clk || !parent)
245 return -EFAULT;
246 if (clk->pclk == parent)
247 return 0;
248 if (!clk->pclk_sel)
249 return -EPERM;
250
251 /* check if requested parent is in clk parent list */
252 for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
253 if (clk->pclk_sel->pclk_info[i].pclk == parent) {
254 found = 1;
255 break;
256 }
257 }
258
259 if (!found)
260 return -EINVAL;
261
262 spin_lock_irqsave(&clocks_lock, flags);
263 /* reflect parent change in hardware */
264 val = readl(clk->pclk_sel->pclk_sel_reg);
265 val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift);
266 val |= clk->pclk_sel->pclk_info[i].pclk_val << clk->pclk_sel_shift;
267 writel(val, clk->pclk_sel->pclk_sel_reg);
268 spin_unlock_irqrestore(&clocks_lock, flags);
269
270 /* reflect parent change in software */
271 clk_reparent(clk, &clk->pclk_sel->pclk_info[i]);
272
273 propagate_rate(clk, 0);
274 return 0;
275}
276EXPORT_SYMBOL(clk_set_parent);
277
278/**
279 * clk_set_rate - set the clock rate for a clock source
280 * @clk: clock source
281 * @rate: desired clock rate in Hz
282 *
283 * Returns success (0) or negative errno.
284 */
285int clk_set_rate(struct clk *clk, unsigned long rate)
286{
287 unsigned long flags;
288 int ret = -EINVAL;
289
290 if (!clk || !rate)
291 return -EFAULT;
292
293 if (clk->set_rate) {
294 spin_lock_irqsave(&clocks_lock, flags);
295 ret = clk->set_rate(clk, rate);
296 if (!ret)
297 /* if successful -> propagate */
298 propagate_rate(clk, 0);
299 spin_unlock_irqrestore(&clocks_lock, flags);
300 } else if (clk->pclk) {
301 u32 mult = clk->div_factor ? clk->div_factor : 1;
302 ret = clk_set_rate(clk->pclk, mult * rate);
303 }
304
305 return ret;
306}
307EXPORT_SYMBOL(clk_set_rate);
308
309/* registers clock in platform clock framework */
310void clk_register(struct clk_lookup *cl)
311{
312 struct clk *clk;
313 unsigned long flags;
314
315 if (!cl || !cl->clk)
316 return;
317 clk = cl->clk;
318
319 spin_lock_irqsave(&clocks_lock, flags);
320
321 INIT_LIST_HEAD(&clk->children);
322 if (clk->flags & ALWAYS_ENABLED)
323 clk->ops = NULL;
324 else if (!clk->ops)
325 clk->ops = &generic_clkops;
326
327 /* root clock don't have any parents */
328 if (!clk->pclk && !clk->pclk_sel) {
329 list_add(&clk->sibling, &root_clks);
330 } else if (clk->pclk && !clk->pclk_sel) {
331 /* add clocks with only one parent to parent's children list */
332 list_add(&clk->sibling, &clk->pclk->children);
333 } else {
334 /* clocks with more than one parent */
335 struct pclk_info *pclk_info;
336
337 pclk_info = pclk_info_get(clk);
338 if (!pclk_info) {
339 pr_err("CLKDEV: invalid pclk info of clk with"
340 " %s dev_id and %s con_id\n",
341 cl->dev_id, cl->con_id);
342 } else {
343 clk->pclk = pclk_info->pclk;
344 list_add(&clk->sibling, &pclk_info->pclk->children);
345 }
346 }
347
348 spin_unlock_irqrestore(&clocks_lock, flags);
349
350 /* debugfs specific */
351#ifdef CONFIG_DEBUG_FS
352 list_add(&clk->node, &clocks);
353 clk->cl = cl;
354#endif
355
356 /* add clock to arm clockdev framework */
357 clkdev_add(cl);
358}
359
360/**
361 * propagate_rate - recalculate and propagate all clocks to children
362 * @pclk: parent clock required to be propogated
363 * @on_init: flag for enabling clocks which are ENABLED_ON_INIT.
364 *
365 * Recalculates all children clocks
366 */
367void propagate_rate(struct clk *pclk, int on_init)
368{
369 struct clk *clk, *_temp;
370 int ret = 0;
371
372 list_for_each_entry_safe(clk, _temp, &pclk->children, sibling) {
373 if (clk->recalc) {
374 ret = clk->recalc(clk);
375 /*
376 * recalc will return error if clk out is not programmed
377 * In this case configure default rate.
378 */
379 if (ret && clk->set_rate)
380 clk->set_rate(clk, 0);
381 }
382 propagate_rate(clk, on_init);
383
384 if (!on_init)
385 continue;
386
387 /* Enable clks enabled on init, in software view */
388 if (clk->flags & ENABLED_ON_INIT)
389 do_clk_enable(clk);
390 }
391}
392
393/**
394 * round_rate_index - return closest programmable rate index in rate_config tbl
395 * @clk: ptr to clock structure
396 * @drate: desired rate
397 * @rate: final rate will be returned in this variable only.
398 *
399 * Finds index in rate_config for highest clk rate which is less than
400 * requested rate. If there is no clk rate lesser than requested rate then
401 * -EINVAL is returned. This routine assumes that rate_config is written
402 * in incrementing order of clk rates.
403 * If drate passed is zero then default rate is programmed.
404 */
405static int
406round_rate_index(struct clk *clk, unsigned long drate, unsigned long *rate)
407{
408 unsigned long tmp = 0, prev_rate = 0;
409 int index;
410
411 if (!clk->calc_rate)
412 return -EFAULT;
413
414 if (!drate)
415 return -EINVAL;
416
417 /*
418 * This loops ends on two conditions:
419 * - as soon as clk is found with rate greater than requested rate.
420 * - if all clks in rate_config are smaller than requested rate.
421 */
422 for (index = 0; index < clk->rate_config.count; index++) {
423 prev_rate = tmp;
424 tmp = clk->calc_rate(clk, index);
425 if (drate < tmp) {
426 index--;
427 break;
428 }
429 }
430 /* return if can't find suitable clock */
431 if (index < 0) {
432 index = -EINVAL;
433 *rate = 0;
434 } else if (index == clk->rate_config.count) {
435 /* program with highest clk rate possible */
436 index = clk->rate_config.count - 1;
437 *rate = tmp;
438 } else
439 *rate = prev_rate;
440
441 return index;
442}
443
444/**
445 * clk_round_rate - adjust a rate to the exact rate a clock can provide
446 * @clk: clock source
447 * @rate: desired clock rate in Hz
448 *
449 * Returns rounded clock rate in Hz, or negative errno.
450 */
451long clk_round_rate(struct clk *clk, unsigned long drate)
452{
453 long rate = 0;
454 int index;
455
456 /*
457 * propagate call to parent who supports calc_rate. Similar approach is
458 * used in clk_set_rate.
459 */
460 if (!clk->calc_rate) {
461 u32 mult;
462 if (!clk->pclk)
463 return clk->rate;
464
465 mult = clk->div_factor ? clk->div_factor : 1;
466 return clk_round_rate(clk->pclk, mult * drate) / mult;
467 }
468
469 index = round_rate_index(clk, drate, &rate);
470 if (index >= 0)
471 return rate;
472 else
473 return index;
474}
475EXPORT_SYMBOL(clk_round_rate);
476
477/*All below functions are called with lock held */
478
479/*
480 * Calculates pll clk rate for specific value of mode, m, n and p
481 *
482 * In normal mode
483 * rate = (2 * M[15:8] * Fin)/(N * 2^P)
484 *
485 * In Dithered mode
486 * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
487 */
488unsigned long pll_calc_rate(struct clk *clk, int index)
489{
490 unsigned long rate = clk->pclk->rate;
491 struct pll_rate_tbl *tbls = clk->rate_config.tbls;
492 unsigned int mode;
493
494 mode = tbls[index].mode ? 256 : 1;
495 return (((2 * rate / 10000) * tbls[index].m) /
496 (mode * tbls[index].n * (1 << tbls[index].p))) * 10000;
497}
498
499/*
500 * calculates current programmed rate of pll1
501 *
502 * In normal mode
503 * rate = (2 * M[15:8] * Fin)/(N * 2^P)
504 *
505 * In Dithered mode
506 * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
507 */
508int pll_clk_recalc(struct clk *clk)
509{
510 struct pll_clk_config *config = clk->private_data;
511 unsigned int num = 2, den = 0, val, mode = 0;
512
513 mode = (readl(config->mode_reg) >> config->masks->mode_shift) &
514 config->masks->mode_mask;
515
516 val = readl(config->cfg_reg);
517 /* calculate denominator */
518 den = (val >> config->masks->div_p_shift) & config->masks->div_p_mask;
519 den = 1 << den;
520 den *= (val >> config->masks->div_n_shift) & config->masks->div_n_mask;
521
522 /* calculate numerator & denominator */
523 if (!mode) {
524 /* Normal mode */
525 num *= (val >> config->masks->norm_fdbk_m_shift) &
526 config->masks->norm_fdbk_m_mask;
527 } else {
528 /* Dithered mode */
529 num *= (val >> config->masks->dith_fdbk_m_shift) &
530 config->masks->dith_fdbk_m_mask;
531 den *= 256;
532 }
533
534 if (!den)
535 return -EINVAL;
536
537 clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
538 return 0;
539}
540
541/*
542 * Configures new clock rate of pll
543 */
544int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate)
545{
546 struct pll_rate_tbl *tbls = clk->rate_config.tbls;
547 struct pll_clk_config *config = clk->private_data;
548 unsigned long val, rate;
549 int i;
550
551 i = round_rate_index(clk, desired_rate, &rate);
552 if (i < 0)
553 return i;
554
555 val = readl(config->mode_reg) &
556 ~(config->masks->mode_mask << config->masks->mode_shift);
557 val |= (tbls[i].mode & config->masks->mode_mask) <<
558 config->masks->mode_shift;
559 writel(val, config->mode_reg);
560
561 val = readl(config->cfg_reg) &
562 ~(config->masks->div_p_mask << config->masks->div_p_shift);
563 val |= (tbls[i].p & config->masks->div_p_mask) <<
564 config->masks->div_p_shift;
565 val &= ~(config->masks->div_n_mask << config->masks->div_n_shift);
566 val |= (tbls[i].n & config->masks->div_n_mask) <<
567 config->masks->div_n_shift;
568 val &= ~(config->masks->dith_fdbk_m_mask <<
569 config->masks->dith_fdbk_m_shift);
570 if (tbls[i].mode)
571 val |= (tbls[i].m & config->masks->dith_fdbk_m_mask) <<
572 config->masks->dith_fdbk_m_shift;
573 else
574 val |= (tbls[i].m & config->masks->norm_fdbk_m_mask) <<
575 config->masks->norm_fdbk_m_shift;
576
577 writel(val, config->cfg_reg);
578
579 clk->rate = rate;
580
581 return 0;
582}
583
584/*
585 * Calculates ahb, apb clk rate for specific value of div
586 */
587unsigned long bus_calc_rate(struct clk *clk, int index)
588{
589 unsigned long rate = clk->pclk->rate;
590 struct bus_rate_tbl *tbls = clk->rate_config.tbls;
591
592 return rate / (tbls[index].div + 1);
593}
594
595/* calculates current programmed rate of ahb or apb bus */
596int bus_clk_recalc(struct clk *clk)
597{
598 struct bus_clk_config *config = clk->private_data;
599 unsigned int div;
600
601 div = ((readl(config->reg) >> config->masks->shift) &
602 config->masks->mask) + 1;
603
604 if (!div)
605 return -EINVAL;
606
607 clk->rate = (unsigned long)clk->pclk->rate / div;
608 return 0;
609}
610
611/* Configures new clock rate of AHB OR APB bus */
612int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate)
613{
614 struct bus_rate_tbl *tbls = clk->rate_config.tbls;
615 struct bus_clk_config *config = clk->private_data;
616 unsigned long val, rate;
617 int i;
618
619 i = round_rate_index(clk, desired_rate, &rate);
620 if (i < 0)
621 return i;
622
623 val = readl(config->reg) &
624 ~(config->masks->mask << config->masks->shift);
625 val |= (tbls[i].div & config->masks->mask) << config->masks->shift;
626 writel(val, config->reg);
627
628 clk->rate = rate;
629
630 return 0;
631}
632
633/*
634 * gives rate for different values of eq, x and y
635 *
636 * Fout from synthesizer can be given from two equations:
637 * Fout1 = (Fin * X/Y)/2 EQ1
638 * Fout2 = Fin * X/Y EQ2
639 */
640unsigned long aux_calc_rate(struct clk *clk, int index)
641{
642 unsigned long rate = clk->pclk->rate;
643 struct aux_rate_tbl *tbls = clk->rate_config.tbls;
644 u8 eq = tbls[index].eq ? 1 : 2;
645
646 return (((rate/10000) * tbls[index].xscale) /
647 (tbls[index].yscale * eq)) * 10000;
648}
649
650/*
651 * calculates current programmed rate of auxiliary synthesizers
652 * used by: UART, FIRDA
653 *
654 * Fout from synthesizer can be given from two equations:
655 * Fout1 = (Fin * X/Y)/2
656 * Fout2 = Fin * X/Y
657 *
658 * Selection of eqn 1 or 2 is programmed in register
659 */
660int aux_clk_recalc(struct clk *clk)
661{
662 struct aux_clk_config *config = clk->private_data;
663 unsigned int num = 1, den = 1, val, eqn;
664
665 val = readl(config->synth_reg);
666
667 eqn = (val >> config->masks->eq_sel_shift) &
668 config->masks->eq_sel_mask;
669 if (eqn == config->masks->eq1_mask)
670 den *= 2;
671
672 /* calculate numerator */
673 num = (val >> config->masks->xscale_sel_shift) &
674 config->masks->xscale_sel_mask;
675
676 /* calculate denominator */
677 den *= (val >> config->masks->yscale_sel_shift) &
678 config->masks->yscale_sel_mask;
679
680 if (!den)
681 return -EINVAL;
682
683 clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
684 return 0;
685}
686
687/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
688int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate)
689{
690 struct aux_rate_tbl *tbls = clk->rate_config.tbls;
691 struct aux_clk_config *config = clk->private_data;
692 unsigned long val, rate;
693 int i;
694
695 i = round_rate_index(clk, desired_rate, &rate);
696 if (i < 0)
697 return i;
698
699 val = readl(config->synth_reg) &
700 ~(config->masks->eq_sel_mask << config->masks->eq_sel_shift);
701 val |= (tbls[i].eq & config->masks->eq_sel_mask) <<
702 config->masks->eq_sel_shift;
703 val &= ~(config->masks->xscale_sel_mask <<
704 config->masks->xscale_sel_shift);
705 val |= (tbls[i].xscale & config->masks->xscale_sel_mask) <<
706 config->masks->xscale_sel_shift;
707 val &= ~(config->masks->yscale_sel_mask <<
708 config->masks->yscale_sel_shift);
709 val |= (tbls[i].yscale & config->masks->yscale_sel_mask) <<
710 config->masks->yscale_sel_shift;
711 writel(val, config->synth_reg);
712
713 clk->rate = rate;
714
715 return 0;
716}
717
718/*
719 * Calculates gpt clk rate for different values of mscale and nscale
720 *
721 * Fout= Fin/((2 ^ (N+1)) * (M+1))
722 */
723unsigned long gpt_calc_rate(struct clk *clk, int index)
724{
725 unsigned long rate = clk->pclk->rate;
726 struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
727
728 return rate / ((1 << (tbls[index].nscale + 1)) *
729 (tbls[index].mscale + 1));
730}
731
732/*
733 * calculates current programmed rate of gpt synthesizers
734 * Fout from synthesizer can be given from below equations:
735 * Fout= Fin/((2 ^ (N+1)) * (M+1))
736 */
737int gpt_clk_recalc(struct clk *clk)
738{
739 struct gpt_clk_config *config = clk->private_data;
740 unsigned int div = 1, val;
741
742 val = readl(config->synth_reg);
743 div += (val >> config->masks->mscale_sel_shift) &
744 config->masks->mscale_sel_mask;
745 div *= 1 << (((val >> config->masks->nscale_sel_shift) &
746 config->masks->nscale_sel_mask) + 1);
747
748 if (!div)
749 return -EINVAL;
750
751 clk->rate = (unsigned long)clk->pclk->rate / div;
752 return 0;
753}
754
755/* Configures new clock rate of gptiliary synthesizers used by: UART, FIRDA*/
756int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate)
757{
758 struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
759 struct gpt_clk_config *config = clk->private_data;
760 unsigned long val, rate;
761 int i;
762
763 i = round_rate_index(clk, desired_rate, &rate);
764 if (i < 0)
765 return i;
766
767 val = readl(config->synth_reg) & ~(config->masks->mscale_sel_mask <<
768 config->masks->mscale_sel_shift);
769 val |= (tbls[i].mscale & config->masks->mscale_sel_mask) <<
770 config->masks->mscale_sel_shift;
771 val &= ~(config->masks->nscale_sel_mask <<
772 config->masks->nscale_sel_shift);
773 val |= (tbls[i].nscale & config->masks->nscale_sel_mask) <<
774 config->masks->nscale_sel_shift;
775 writel(val, config->synth_reg);
776
777 clk->rate = rate;
778
779 return 0;
780}
781
782/*
783 * Calculates clcd clk rate for different values of div
784 *
785 * Fout from synthesizer can be given from below equation:
786 * Fout= Fin/2*div (division factor)
787 * div is 17 bits:-
788 * 0-13 (fractional part)
789 * 14-16 (integer part)
790 * To calculate Fout we left shift val by 14 bits and divide Fin by
791 * complete div (including fractional part) and then right shift the
792 * result by 14 places.
793 */
794unsigned long clcd_calc_rate(struct clk *clk, int index)
795{
796 unsigned long rate = clk->pclk->rate;
797 struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
798
799 rate /= 1000;
800 rate <<= 12;
801 rate /= (2 * tbls[index].div);
802 rate >>= 12;
803 rate *= 1000;
804
805 return rate;
806}
807
808/*
809 * calculates current programmed rate of clcd synthesizer
810 * Fout from synthesizer can be given from below equation:
811 * Fout= Fin/2*div (division factor)
812 * div is 17 bits:-
813 * 0-13 (fractional part)
814 * 14-16 (integer part)
815 * To calculate Fout we left shift val by 14 bits and divide Fin by
816 * complete div (including fractional part) and then right shift the
817 * result by 14 places.
818 */
819int clcd_clk_recalc(struct clk *clk)
820{
821 struct clcd_clk_config *config = clk->private_data;
822 unsigned int div = 1;
823 unsigned long prate;
824 unsigned int val;
825
826 val = readl(config->synth_reg);
827 div = (val >> config->masks->div_factor_shift) &
828 config->masks->div_factor_mask;
829
830 if (!div)
831 return -EINVAL;
832
833 prate = clk->pclk->rate / 1000; /* first level division, make it KHz */
834
835 clk->rate = (((unsigned long)prate << 12) / (2 * div)) >> 12;
836 clk->rate *= 1000;
837 return 0;
838}
839
840/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
841int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate)
842{
843 struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
844 struct clcd_clk_config *config = clk->private_data;
845 unsigned long val, rate;
846 int i;
847
848 i = round_rate_index(clk, desired_rate, &rate);
849 if (i < 0)
850 return i;
851
852 val = readl(config->synth_reg) & ~(config->masks->div_factor_mask <<
853 config->masks->div_factor_shift);
854 val |= (tbls[i].div & config->masks->div_factor_mask) <<
855 config->masks->div_factor_shift;
856 writel(val, config->synth_reg);
857
858 clk->rate = rate;
859
860 return 0;
861}
862
863/*
864 * Used for clocks that always have value as the parent clock divided by a
865 * fixed divisor
866 */
867int follow_parent(struct clk *clk)
868{
869 unsigned int div_factor = (clk->div_factor < 1) ? 1 : clk->div_factor;
870
871 clk->rate = clk->pclk->rate/div_factor;
872 return 0;
873}
874
875/**
876 * recalc_root_clocks - recalculate and propagate all root clocks
877 *
878 * Recalculates all root clocks (clocks with no parent), which if the
879 * clock's .recalc is set correctly, should also propagate their rates.
880 */
881void recalc_root_clocks(void)
882{
883 struct clk *pclk;
884 unsigned long flags;
885 int ret = 0;
886
887 spin_lock_irqsave(&clocks_lock, flags);
888 list_for_each_entry(pclk, &root_clks, sibling) {
889 if (pclk->recalc) {
890 ret = pclk->recalc(pclk);
891 /*
892 * recalc will return error if clk out is not programmed
893 * In this case configure default clock.
894 */
895 if (ret && pclk->set_rate)
896 pclk->set_rate(pclk, 0);
897 }
898 propagate_rate(pclk, 1);
899 /* Enable clks enabled on init, in software view */
900 if (pclk->flags & ENABLED_ON_INIT)
901 do_clk_enable(pclk);
902 }
903 spin_unlock_irqrestore(&clocks_lock, flags);
904}
905
906void __init clk_init(void)
907{
908 recalc_root_clocks();
909}
910
911#ifdef CONFIG_DEBUG_FS
912/*
913 * debugfs support to trace clock tree hierarchy and attributes
914 */
915static struct dentry *clk_debugfs_root;
916static int clk_debugfs_register_one(struct clk *c)
917{
918 int err;
919 struct dentry *d;
920 struct clk *pa = c->pclk;
921 char s[255];
922 char *p = s;
923
924 if (c) {
925 if (c->cl->con_id)
926 p += sprintf(p, "%s", c->cl->con_id);
927 if (c->cl->dev_id)
928 p += sprintf(p, "%s", c->cl->dev_id);
929 }
930 d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
931 if (!d)
932 return -ENOMEM;
933 c->dent = d;
934
935 d = debugfs_create_u32("usage_count", S_IRUGO, c->dent,
936 (u32 *)&c->usage_count);
937 if (!d) {
938 err = -ENOMEM;
939 goto err_out;
940 }
941 d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
942 if (!d) {
943 err = -ENOMEM;
944 goto err_out;
945 }
946 d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
947 if (!d) {
948 err = -ENOMEM;
949 goto err_out;
950 }
951 return 0;
952
953err_out:
954 debugfs_remove_recursive(c->dent);
955 return err;
956}
957
958static int clk_debugfs_register(struct clk *c)
959{
960 int err;
961 struct clk *pa = c->pclk;
962
963 if (pa && !pa->dent) {
964 err = clk_debugfs_register(pa);
965 if (err)
966 return err;
967 }
968
969 if (!c->dent) {
970 err = clk_debugfs_register_one(c);
971 if (err)
972 return err;
973 }
974 return 0;
975}
976
977static int __init clk_debugfs_init(void)
978{
979 struct clk *c;
980 struct dentry *d;
981 int err;
982
983 d = debugfs_create_dir("clock", NULL);
984 if (!d)
985 return -ENOMEM;
986 clk_debugfs_root = d;
987
988 list_for_each_entry(c, &clocks, node) {
989 err = clk_debugfs_register(c);
990 if (err)
991 goto err_out;
992 }
993 return 0;
994err_out:
995 debugfs_remove_recursive(clk_debugfs_root);
996 return err;
997}
998late_initcall(clk_debugfs_init);
999
1000static int clk_debugfs_reparent(struct clk *c)
1001{
1002 debugfs_remove(c->dent);
1003 return clk_debugfs_register_one(c);
1004}
1005#endif /* CONFIG_DEBUG_FS */
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
deleted file mode 100644
index 0062bafef12d..000000000000
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ /dev/null
@@ -1,249 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/clock.h
3 *
4 * Clock framework definitions for SPEAr platform
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_CLOCK_H
15#define __PLAT_CLOCK_H
16
17#include <linux/list.h>
18#include <linux/clkdev.h>
19#include <linux/types.h>
20
21/* clk structure flags */
22#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */
23#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */
24#define ENABLED_ON_INIT (1 << 2) /* clocks enabled at init */
25
26/**
27 * struct clkops - clock operations
28 * @enable: pointer to clock enable function
29 * @disable: pointer to clock disable function
30 */
31struct clkops {
32 int (*enable) (struct clk *);
33 void (*disable) (struct clk *);
34};
35
36/**
37 * struct pclk_info - parents info
38 * @pclk: pointer to parent clk
39 * @pclk_val: value to be written for selecting this parent
40 */
41struct pclk_info {
42 struct clk *pclk;
43 u8 pclk_val;
44};
45
46/**
47 * struct pclk_sel - parents selection configuration
48 * @pclk_info: pointer to array of parent clock info
49 * @pclk_count: number of parents
50 * @pclk_sel_reg: register for selecting a parent
51 * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also)
52 */
53struct pclk_sel {
54 struct pclk_info *pclk_info;
55 u8 pclk_count;
56 void __iomem *pclk_sel_reg;
57 unsigned int pclk_sel_mask;
58};
59
60/**
61 * struct rate_config - clk rate configurations
62 * @tbls: array of device specific clk rate tables, in ascending order of rates
63 * @count: size of tbls array
64 * @default_index: default setting when originally disabled
65 */
66struct rate_config {
67 void *tbls;
68 u8 count;
69 u8 default_index;
70};
71
72/**
73 * struct clk - clock structure
74 * @usage_count: num of users who enabled this clock
75 * @flags: flags for clock properties
76 * @rate: programmed clock rate in Hz
77 * @en_reg: clk enable/disable reg
78 * @en_reg_bit: clk enable/disable bit
79 * @ops: clk enable/disable ops - generic_clkops selected if NULL
80 * @recalc: pointer to clock rate recalculate function
81 * @set_rate: pointer to clock set rate function
82 * @calc_rate: pointer to clock get rate function for index
83 * @rate_config: rate configuration information, used by set_rate
84 * @div_factor: division factor to parent clock.
85 * @pclk: current parent clk
86 * @pclk_sel: pointer to parent selection structure
87 * @pclk_sel_shift: register shift for selecting parent of this clock
88 * @children: list for childrens or this clock
89 * @sibling: node for list of clocks having same parents
90 * @private_data: clock specific private data
91 * @node: list to maintain clocks linearly
92 * @cl: clocklook up associated with this clock
93 * @dent: object for debugfs
94 */
95struct clk {
96 unsigned int usage_count;
97 unsigned int flags;
98 unsigned long rate;
99 void __iomem *en_reg;
100 u8 en_reg_bit;
101 const struct clkops *ops;
102 int (*recalc) (struct clk *);
103 int (*set_rate) (struct clk *, unsigned long rate);
104 unsigned long (*calc_rate)(struct clk *, int index);
105 struct rate_config rate_config;
106 unsigned int div_factor;
107
108 struct clk *pclk;
109 struct pclk_sel *pclk_sel;
110 unsigned int pclk_sel_shift;
111
112 struct list_head children;
113 struct list_head sibling;
114 void *private_data;
115#ifdef CONFIG_DEBUG_FS
116 struct list_head node;
117 struct clk_lookup *cl;
118 struct dentry *dent;
119#endif
120};
121
122/* pll configuration structure */
123struct pll_clk_masks {
124 u32 mode_mask;
125 u32 mode_shift;
126
127 u32 norm_fdbk_m_mask;
128 u32 norm_fdbk_m_shift;
129 u32 dith_fdbk_m_mask;
130 u32 dith_fdbk_m_shift;
131 u32 div_p_mask;
132 u32 div_p_shift;
133 u32 div_n_mask;
134 u32 div_n_shift;
135};
136
137struct pll_clk_config {
138 void __iomem *mode_reg;
139 void __iomem *cfg_reg;
140 struct pll_clk_masks *masks;
141};
142
143/* pll clk rate config structure */
144struct pll_rate_tbl {
145 u8 mode;
146 u16 m;
147 u8 n;
148 u8 p;
149};
150
151/* ahb and apb bus configuration structure */
152struct bus_clk_masks {
153 u32 mask;
154 u32 shift;
155};
156
157struct bus_clk_config {
158 void __iomem *reg;
159 struct bus_clk_masks *masks;
160};
161
162/* ahb and apb clk bus rate config structure */
163struct bus_rate_tbl {
164 u8 div;
165};
166
167/* Aux clk configuration structure: applicable to UART and FIRDA */
168struct aux_clk_masks {
169 u32 eq_sel_mask;
170 u32 eq_sel_shift;
171 u32 eq1_mask;
172 u32 eq2_mask;
173 u32 xscale_sel_mask;
174 u32 xscale_sel_shift;
175 u32 yscale_sel_mask;
176 u32 yscale_sel_shift;
177};
178
179struct aux_clk_config {
180 void __iomem *synth_reg;
181 struct aux_clk_masks *masks;
182};
183
184/* aux clk rate config structure */
185struct aux_rate_tbl {
186 u16 xscale;
187 u16 yscale;
188 u8 eq;
189};
190
191/* GPT clk configuration structure */
192struct gpt_clk_masks {
193 u32 mscale_sel_mask;
194 u32 mscale_sel_shift;
195 u32 nscale_sel_mask;
196 u32 nscale_sel_shift;
197};
198
199struct gpt_clk_config {
200 void __iomem *synth_reg;
201 struct gpt_clk_masks *masks;
202};
203
204/* gpt clk rate config structure */
205struct gpt_rate_tbl {
206 u16 mscale;
207 u16 nscale;
208};
209
210/* clcd clk configuration structure */
211struct clcd_synth_masks {
212 u32 div_factor_mask;
213 u32 div_factor_shift;
214};
215
216struct clcd_clk_config {
217 void __iomem *synth_reg;
218 struct clcd_synth_masks *masks;
219};
220
221/* clcd clk rate config structure */
222struct clcd_rate_tbl {
223 u16 div;
224};
225
226/* platform specific clock functions */
227void __init clk_init(void);
228void clk_register(struct clk_lookup *cl);
229void recalc_root_clocks(void);
230
231/* clock recalc & set rate functions */
232int follow_parent(struct clk *clk);
233unsigned long pll_calc_rate(struct clk *clk, int index);
234int pll_clk_recalc(struct clk *clk);
235int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate);
236unsigned long bus_calc_rate(struct clk *clk, int index);
237int bus_clk_recalc(struct clk *clk);
238int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate);
239unsigned long gpt_calc_rate(struct clk *clk, int index);
240int gpt_clk_recalc(struct clk *clk);
241int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate);
242unsigned long aux_calc_rate(struct clk *clk, int index);
243int aux_clk_recalc(struct clk *clk);
244int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate);
245unsigned long clcd_calc_rate(struct clk *clk, int index);
246int clcd_clk_recalc(struct clk *clk);
247int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate);
248
249#endif /* __PLAT_CLOCK_H */
diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
deleted file mode 100644
index 877f3adcf610..000000000000
--- a/arch/arm/plat-spear/include/plat/padmux.h
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/padmux.h
3 *
4 * SPEAr platform specific gpio pads muxing file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_PADMUX_H
15#define __PLAT_PADMUX_H
16
17#include <linux/types.h>
18
19/*
20 * struct pmx_reg: configuration structure for mode reg and mux reg
21 *
22 * offset: offset of mode reg
23 * mask: mask of mode reg
24 */
25struct pmx_reg {
26 u32 offset;
27 u32 mask;
28};
29
30/*
31 * struct pmx_dev_mode: configuration structure every group of modes of a device
32 *
33 * ids: all modes for this configuration
34 * mask: mask for supported mode
35 */
36struct pmx_dev_mode {
37 u32 ids;
38 u32 mask;
39};
40
41/*
42 * struct pmx_mode: mode definition structure
43 *
44 * name: mode name
45 * mask: mode mask
46 */
47struct pmx_mode {
48 char *name;
49 u32 id;
50 u32 mask;
51};
52
53/*
54 * struct pmx_dev: device definition structure
55 *
56 * name: device name
57 * modes: device configuration array for different modes supported
58 * mode_count: size of modes array
59 * is_active: is peripheral active/enabled
60 * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
61 */
62struct pmx_dev {
63 char *name;
64 struct pmx_dev_mode *modes;
65 u8 mode_count;
66 bool is_active;
67 bool enb_on_reset;
68};
69
70/*
71 * struct pmx_driver: driver definition structure
72 *
73 * mode: mode to be set
74 * devs: array of pointer to pmx devices
75 * devs_count: ARRAY_SIZE of devs
76 * base: base address of soc config registers
77 * mode_reg: structure of mode config register
78 * mux_reg: structure of device mux config register
79 */
80struct pmx_driver {
81 struct pmx_mode *mode;
82 struct pmx_dev **devs;
83 u8 devs_count;
84 u32 *base;
85 struct pmx_reg mode_reg;
86 struct pmx_reg mux_reg;
87};
88
89/* pmx functions */
90int pmx_register(struct pmx_driver *driver);
91
92#endif /* __PLAT_PADMUX_H */
diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
deleted file mode 100644
index 555eec6dc1cb..000000000000
--- a/arch/arm/plat-spear/padmux.c
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/padmux.c
3 *
4 * SPEAr platform specific gpio pads muxing source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <plat/padmux.h>
18
19/*
20 * struct pmx: pmx definition structure
21 *
22 * base: base address of configuration registers
23 * mode_reg: mode configurations
24 * mux_reg: muxing configurations
25 * active_mode: pointer to current active mode
26 */
27struct pmx {
28 u32 base;
29 struct pmx_reg mode_reg;
30 struct pmx_reg mux_reg;
31 struct pmx_mode *active_mode;
32};
33
34static struct pmx *pmx;
35
36/**
37 * pmx_mode_set - Enables an multiplexing mode
38 * @mode - pointer to pmx mode
39 *
40 * It will set mode of operation in hardware.
41 * Returns -ve on Err otherwise 0
42 */
43static int pmx_mode_set(struct pmx_mode *mode)
44{
45 u32 val;
46
47 if (!mode->name)
48 return -EFAULT;
49
50 pmx->active_mode = mode;
51
52 val = readl(pmx->base + pmx->mode_reg.offset);
53 val &= ~pmx->mode_reg.mask;
54 val |= mode->mask & pmx->mode_reg.mask;
55 writel(val, pmx->base + pmx->mode_reg.offset);
56
57 return 0;
58}
59
60/**
61 * pmx_devs_enable - Enables list of devices
62 * @devs - pointer to pmx device array
63 * @count - number of devices to enable
64 *
65 * It will enable pads for all required peripherals once and only once.
66 * If peripheral is not supported by current mode then request is rejected.
67 * Conflicts between peripherals are not handled and peripherals will be
68 * enabled in the order they are present in pmx_dev array.
69 * In case of conflicts last peripheral enabled will be present.
70 * Returns -ve on Err otherwise 0
71 */
72static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
73{
74 u32 val, i, mask;
75
76 if (!count)
77 return -EINVAL;
78
79 val = readl(pmx->base + pmx->mux_reg.offset);
80 for (i = 0; i < count; i++) {
81 u8 j = 0;
82
83 if (!devs[i]->name || !devs[i]->modes) {
84 printk(KERN_ERR "padmux: dev name or modes is null\n");
85 continue;
86 }
87 /* check if peripheral exists in active mode */
88 if (pmx->active_mode) {
89 bool found = false;
90 for (j = 0; j < devs[i]->mode_count; j++) {
91 if (devs[i]->modes[j].ids &
92 pmx->active_mode->id) {
93 found = true;
94 break;
95 }
96 }
97 if (found == false) {
98 printk(KERN_ERR "%s device not available in %s"\
99 "mode\n", devs[i]->name,
100 pmx->active_mode->name);
101 continue;
102 }
103 }
104
105 /* enable peripheral */
106 mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
107 if (devs[i]->enb_on_reset)
108 val &= ~mask;
109 else
110 val |= mask;
111
112 devs[i]->is_active = true;
113 }
114 writel(val, pmx->base + pmx->mux_reg.offset);
115 kfree(pmx);
116
117 /* this will ensure that multiplexing can't be changed now */
118 pmx = (struct pmx *)-1;
119
120 return 0;
121}
122
123/**
124 * pmx_register - registers a platform requesting pad mux feature
125 * @driver - pointer to driver structure containing driver specific parameters
126 *
127 * Also this must be called only once. This will allocate memory for pmx
128 * structure, will call pmx_mode_set, will call pmx_devs_enable.
129 * Returns -ve on Err otherwise 0
130 */
131int pmx_register(struct pmx_driver *driver)
132{
133 int ret = 0;
134
135 if (pmx)
136 return -EPERM;
137 if (!driver->base || !driver->devs)
138 return -EFAULT;
139
140 pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
141 if (!pmx)
142 return -ENOMEM;
143
144 pmx->base = (u32)driver->base;
145 pmx->mode_reg.offset = driver->mode_reg.offset;
146 pmx->mode_reg.mask = driver->mode_reg.mask;
147 pmx->mux_reg.offset = driver->mux_reg.offset;
148 pmx->mux_reg.mask = driver->mux_reg.mask;
149
150 /* choose mode to enable */
151 if (driver->mode) {
152 ret = pmx_mode_set(driver->mode);
153 if (ret)
154 goto pmx_fail;
155 }
156 ret = pmx_devs_enable(driver->devs, driver->devs_count);
157 if (ret)
158 goto pmx_fail;
159
160 return 0;
161
162pmx_fail:
163 return ret;
164}
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index 9a378987bbb1..03321af5de9f 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -233,10 +233,10 @@ void __init spear_setup_of_timer(void)
233 goto err_iomap; 233 goto err_iomap;
234 } 234 }
235 235
236 ret = clk_enable(gpt_clk); 236 ret = clk_prepare_enable(gpt_clk);
237 if (ret < 0) { 237 if (ret < 0) {
238 pr_err("%s:couldn't enable gpt clock\n", __func__); 238 pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
239 goto err_clk; 239 goto err_prepare_enable_clk;
240 } 240 }
241 241
242 spear_clockevent_init(irq); 242 spear_clockevent_init(irq);
@@ -244,7 +244,7 @@ void __init spear_setup_of_timer(void)
244 244
245 return; 245 return;
246 246
247err_clk: 247err_prepare_enable_clk:
248 clk_put(gpt_clk); 248 clk_put(gpt_clk);
249err_iomap: 249err_iomap:
250 iounmap(gpt_base); 250 iounmap(gpt_base);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 10:07:58 -0500