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-rw-r--r--arch/arm/Kconfig61
-rw-r--r--arch/arm/configs/davinci_all_defconfig1784
-rw-r--r--arch/arm/configs/kirkwood_defconfig92
-rw-r--r--arch/arm/configs/mv78xx0_defconfig429
-rw-r--r--arch/arm/configs/mx31moboard_defconfig790
-rw-r--r--arch/arm/configs/mx3_defconfig2
-rw-r--r--arch/arm/configs/orion5x_defconfig363
-rw-r--r--arch/arm/configs/viper_defconfig1
-rw-r--r--arch/arm/include/asm/elf.h16
-rw-r--r--arch/arm/kernel/module.c15
-rw-r--r--arch/arm/mach-davinci/Kconfig47
-rw-r--r--arch/arm/mach-davinci/Makefile9
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c (renamed from arch/arm/mach-davinci/board-evm.c)318
-rw-r--r--arch/arm/mach-davinci/clock.c385
-rw-r--r--arch/arm/mach-davinci/clock.h87
-rw-r--r--arch/arm/mach-davinci/devices.c7
-rw-r--r--arch/arm/mach-davinci/dm644x.c461
-rw-r--r--arch/arm/mach-davinci/dma.c1135
-rw-r--r--arch/arm/mach-davinci/gpio.c82
-rw-r--r--arch/arm/mach-davinci/id.c35
-rw-r--r--arch/arm/mach-davinci/include/mach/board-dm6446evm.h20
-rw-r--r--arch/arm/mach-davinci/include/mach/clkdev.h13
-rw-r--r--arch/arm/mach-davinci/include/mach/clock.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h6
-rw-r--r--arch/arm/mach-davinci/include/mach/cputype.h49
-rw-r--r--arch/arm/mach-davinci/include/mach/dm644x.h37
-rw-r--r--arch/arm/mach-davinci/include/mach/edma.h228
-rw-r--r--arch/arm/mach-davinci/include/mach/gpio.h27
-rw-r--r--arch/arm/mach-davinci/include/mach/hardware.h51
-rw-r--r--arch/arm/mach-davinci/include/mach/io.h20
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h103
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h220
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h53
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h21
-rw-r--r--arch/arm/mach-davinci/io.c23
-rw-r--r--arch/arm/mach-davinci/irq.c156
-rw-r--r--arch/arm/mach-davinci/mux.c100
-rw-r--r--arch/arm/mach-davinci/mux.h51
-rw-r--r--arch/arm/mach-davinci/psc.c98
-rw-r--r--arch/arm/mach-davinci/serial.c95
-rw-r--r--arch/arm/mach-davinci/time.c103
-rw-r--r--arch/arm/mach-davinci/usb.c2
-rw-r--r--arch/arm/mach-omap1/board-h2-mmc.c14
-rw-r--r--arch/arm/mach-omap1/board-h3-mmc.c6
-rw-r--r--arch/arm/mach-omap1/board-h3.c101
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c6
-rw-r--r--arch/arm/mach-omap1/mcbsp.c4
-rw-r--r--arch/arm/mach-omap2/board-h4.c95
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c4
-rw-r--r--arch/arm/mach-omap2/board-rx51.c1
-rw-r--r--arch/arm/mach-omap2/clock24xx.c19
-rw-r--r--arch/arm/mach-omap2/clock24xx.h10
-rw-r--r--arch/arm/mach-omap2/clock34xx.h7
-rw-r--r--arch/arm/mach-omap2/devices.c33
-rw-r--r--arch/arm/mach-omap2/irq.c4
-rw-r--r--arch/arm/mach-omap2/timer-gp.c48
-rw-r--r--arch/arm/mach-omap2/usb-tusb6010.c2
-rw-r--r--arch/arm/mach-pxa/Kconfig4
-rw-r--r--arch/arm/mach-pxa/corgi.c10
-rw-r--r--arch/arm/mach-pxa/littleton.c9
-rw-r--r--arch/arm/mach-pxa/spitz.c10
-rw-r--r--arch/arm/mach-pxa/zylonite_pxa300.c5
-rw-r--r--arch/arm/mach-pxa/zylonite_pxa320.c1
-rw-r--r--arch/arm/mach-s3c2412/pm.c3
-rw-r--r--arch/arm/mach-s3c6400/include/mach/map.h2
-rw-r--r--arch/arm/mach-sa1100/lart.c1
-rw-r--r--arch/arm/mm/cache-v6.S33
-rw-r--r--arch/arm/mm/flush.c23
-rw-r--r--arch/arm/mm/proc-v6.S3
-rw-r--r--arch/arm/mm/proc-v7.S22
-rw-r--r--arch/arm/mm/tlb-v6.S3
-rw-r--r--arch/arm/mm/tlb-v7.S3
-rw-r--r--arch/arm/plat-mxc/dma-mx1-mx2.c17
-rw-r--r--arch/arm/plat-mxc/gpio.c2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx27ads.h2
-rw-r--r--arch/arm/plat-omap/clock.c7
-rw-r--r--arch/arm/plat-omap/dma.c13
-rw-r--r--arch/arm/plat-omap/dmtimer.c28
-rw-r--r--arch/arm/plat-omap/gpio.c20
-rw-r--r--arch/arm/plat-omap/include/mach/dmtimer.h2
-rw-r--r--arch/arm/plat-omap/include/mach/eac.h100
-rw-r--r--arch/arm/plat-omap/include/mach/gpioexpander.h35
-rw-r--r--arch/arm/plat-omap/include/mach/irda.h4
-rw-r--r--arch/arm/plat-omap/include/mach/mmc.h1
-rw-r--r--arch/arm/plat-omap/include/mach/timer-gp.h17
-rw-r--r--arch/arm/plat-pxa/gpio.c23
86 files changed, 6366 insertions, 1987 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e02b893fb909..e60ec54df334 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -454,6 +454,7 @@ config ARCH_MXC
454 select ARCH_MTD_XIP 454 select ARCH_MTD_XIP
455 select GENERIC_GPIO 455 select GENERIC_GPIO
456 select ARCH_REQUIRE_GPIOLIB 456 select ARCH_REQUIRE_GPIOLIB
457 select HAVE_CLK
457 help 458 help
458 Support for Freescale MXC/iMX-based family of processors 459 Support for Freescale MXC/iMX-based family of processors
459 460
@@ -486,8 +487,6 @@ config ARCH_PXA
486 select HAVE_CLK 487 select HAVE_CLK
487 select COMMON_CLKDEV 488 select COMMON_CLKDEV
488 select ARCH_REQUIRE_GPIOLIB 489 select ARCH_REQUIRE_GPIOLIB
489 select HAVE_CLK
490 select COMMON_CLKDEV
491 select GENERIC_TIME 490 select GENERIC_TIME
492 select GENERIC_CLOCKEVENTS 491 select GENERIC_CLOCKEVENTS
493 select TICK_ONESHOT 492 select TICK_ONESHOT
@@ -585,6 +584,8 @@ config ARCH_DAVINCI
585 select ARCH_REQUIRE_GPIOLIB 584 select ARCH_REQUIRE_GPIOLIB
586 select HAVE_CLK 585 select HAVE_CLK
587 select ZONE_DMA 586 select ZONE_DMA
587 select HAVE_IDE
588 select COMMON_CLKDEV
588 help 589 help
589 Support for TI's DaVinci platform. 590 Support for TI's DaVinci platform.
590 591
@@ -740,6 +741,56 @@ if !MMU
740source "arch/arm/Kconfig-nommu" 741source "arch/arm/Kconfig-nommu"
741endif 742endif
742 743
744config ARM_ERRATA_411920
745 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
746 depends on CPU_V6 && !SMP
747 help
748 Invalidation of the Instruction Cache operation can
749 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
750 It does not affect the MPCore. This option enables the ARM Ltd.
751 recommended workaround.
752
753config ARM_ERRATA_430973
754 bool "ARM errata: Stale prediction on replaced interworking branch"
755 depends on CPU_V7
756 help
757 This option enables the workaround for the 430973 Cortex-A8
758 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
759 interworking branch is replaced with another code sequence at the
760 same virtual address, whether due to self-modifying code or virtual
761 to physical address re-mapping, Cortex-A8 does not recover from the
762 stale interworking branch prediction. This results in Cortex-A8
763 executing the new code sequence in the incorrect ARM or Thumb state.
764 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
765 and also flushes the branch target cache at every context switch.
766 Note that setting specific bits in the ACTLR register may not be
767 available in non-secure mode.
768
769config ARM_ERRATA_458693
770 bool "ARM errata: Processor deadlock when a false hazard is created"
771 depends on CPU_V7
772 help
773 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
774 erratum. For very specific sequences of memory operations, it is
775 possible for a hazard condition intended for a cache line to instead
776 be incorrectly associated with a different cache line. This false
777 hazard might then cause a processor deadlock. The workaround enables
778 the L1 caching of the NEON accesses and disables the PLD instruction
779 in the ACTLR register. Note that setting specific bits in the ACTLR
780 register may not be available in non-secure mode.
781
782config ARM_ERRATA_460075
783 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
784 depends on CPU_V7
785 help
786 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
787 erratum. Any asynchronous access to the L2 cache may encounter a
788 situation in which recent store transactions to the L2 cache are lost
789 and overwritten with stale memory contents from external memory. The
790 workaround disables the write-allocate mode for the L2 cache via the
791 ACTLR register. Note that setting specific bits in the ACTLR register
792 may not be available in non-secure mode.
793
743endmenu 794endmenu
744 795
745source "arch/arm/common/Kconfig" 796source "arch/arm/common/Kconfig"
@@ -1171,12 +1222,6 @@ config CPU_FREQ_IMX
1171 1222
1172 If in doubt, say N. 1223 If in doubt, say N.
1173 1224
1174config CPU_FREQ_PXA
1175 bool
1176 depends on CPU_FREQ && ARCH_PXA && PXA25x
1177 default y
1178 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1179
1180endif 1225endif
1181 1226
1182source "drivers/cpuidle/Kconfig" 1227source "drivers/cpuidle/Kconfig"
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
new file mode 100644
index 000000000000..eb2738b5be5f
--- /dev/null
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -0,0 +1,1784 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.30-rc2
4# Wed Apr 15 08:16:53 2009
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
16CONFIG_LOCKDEP_SUPPORT=y
17CONFIG_TRACE_IRQFLAGS_SUPPORT=y
18CONFIG_HARDIRQS_SW_RESEND=y
19CONFIG_GENERIC_IRQ_PROBE=y
20CONFIG_RWSEM_GENERIC_SPINLOCK=y
21# CONFIG_ARCH_HAS_ILOG2_U32 is not set
22# CONFIG_ARCH_HAS_ILOG2_U64 is not set
23CONFIG_GENERIC_HWEIGHT=y
24CONFIG_GENERIC_CALIBRATE_DELAY=y
25CONFIG_ZONE_DMA=y
26CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
27CONFIG_VECTORS_BASE=0xffff0000
28CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
29
30#
31# General setup
32#
33CONFIG_EXPERIMENTAL=y
34CONFIG_BROKEN_ON_SMP=y
35CONFIG_LOCK_KERNEL=y
36CONFIG_INIT_ENV_ARG_LIMIT=32
37CONFIG_LOCALVERSION=""
38CONFIG_LOCALVERSION_AUTO=y
39# CONFIG_SWAP is not set
40CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y
42CONFIG_POSIX_MQUEUE=y
43CONFIG_POSIX_MQUEUE_SYSCTL=y
44# CONFIG_BSD_PROCESS_ACCT is not set
45# CONFIG_TASKSTATS is not set
46# CONFIG_AUDIT is not set
47
48#
49# RCU Subsystem
50#
51CONFIG_CLASSIC_RCU=y
52# CONFIG_TREE_RCU is not set
53# CONFIG_PREEMPT_RCU is not set
54# CONFIG_TREE_RCU_TRACE is not set
55# CONFIG_PREEMPT_RCU_TRACE is not set
56CONFIG_IKCONFIG=y
57CONFIG_IKCONFIG_PROC=y
58CONFIG_LOG_BUF_SHIFT=14
59CONFIG_GROUP_SCHED=y
60CONFIG_FAIR_GROUP_SCHED=y
61# CONFIG_RT_GROUP_SCHED is not set
62CONFIG_USER_SCHED=y
63# CONFIG_CGROUP_SCHED is not set
64# CONFIG_CGROUPS is not set
65CONFIG_SYSFS_DEPRECATED=y
66CONFIG_SYSFS_DEPRECATED_V2=y
67# CONFIG_RELAY is not set
68# CONFIG_NAMESPACES is not set
69CONFIG_BLK_DEV_INITRD=y
70CONFIG_INITRAMFS_SOURCE=""
71CONFIG_RD_GZIP=y
72# CONFIG_RD_BZIP2 is not set
73# CONFIG_RD_LZMA is not set
74CONFIG_CC_OPTIMIZE_FOR_SIZE=y
75CONFIG_SYSCTL=y
76CONFIG_ANON_INODES=y
77CONFIG_EMBEDDED=y
78CONFIG_UID16=y
79CONFIG_SYSCTL_SYSCALL=y
80CONFIG_KALLSYMS=y
81# CONFIG_KALLSYMS_ALL is not set
82# CONFIG_KALLSYMS_EXTRA_PASS is not set
83# CONFIG_STRIP_ASM_SYMS is not set
84CONFIG_HOTPLUG=y
85CONFIG_PRINTK=y
86CONFIG_BUG=y
87CONFIG_ELF_CORE=y
88CONFIG_BASE_FULL=y
89CONFIG_FUTEX=y
90CONFIG_EPOLL=y
91CONFIG_SIGNALFD=y
92CONFIG_TIMERFD=y
93CONFIG_EVENTFD=y
94CONFIG_SHMEM=y
95CONFIG_AIO=y
96CONFIG_VM_EVENT_COUNTERS=y
97CONFIG_SLUB_DEBUG=y
98CONFIG_COMPAT_BRK=y
99# CONFIG_SLAB is not set
100CONFIG_SLUB=y
101# CONFIG_SLOB is not set
102# CONFIG_PROFILING is not set
103# CONFIG_MARKERS is not set
104CONFIG_HAVE_OPROFILE=y
105# CONFIG_KPROBES is not set
106CONFIG_HAVE_KPROBES=y
107CONFIG_HAVE_KRETPROBES=y
108CONFIG_HAVE_CLK=y
109# CONFIG_SLOW_WORK is not set
110CONFIG_HAVE_GENERIC_DMA_COHERENT=y
111CONFIG_SLABINFO=y
112CONFIG_RT_MUTEXES=y
113CONFIG_BASE_SMALL=0
114CONFIG_MODULES=y
115# CONFIG_MODULE_FORCE_LOAD is not set
116CONFIG_MODULE_UNLOAD=y
117CONFIG_MODULE_FORCE_UNLOAD=y
118CONFIG_MODVERSIONS=y
119# CONFIG_MODULE_SRCVERSION_ALL is not set
120CONFIG_BLOCK=y
121# CONFIG_LBD is not set
122# CONFIG_BLK_DEV_BSG is not set
123# CONFIG_BLK_DEV_INTEGRITY is not set
124
125#
126# IO Schedulers
127#
128CONFIG_IOSCHED_NOOP=y
129CONFIG_IOSCHED_AS=y
130# CONFIG_IOSCHED_DEADLINE is not set
131# CONFIG_IOSCHED_CFQ is not set
132CONFIG_DEFAULT_AS=y
133# CONFIG_DEFAULT_DEADLINE is not set
134# CONFIG_DEFAULT_CFQ is not set
135# CONFIG_DEFAULT_NOOP is not set
136CONFIG_DEFAULT_IOSCHED="anticipatory"
137# CONFIG_FREEZER is not set
138
139#
140# System Type
141#
142# CONFIG_ARCH_AAEC2000 is not set
143# CONFIG_ARCH_INTEGRATOR is not set
144# CONFIG_ARCH_REALVIEW is not set
145# CONFIG_ARCH_VERSATILE is not set
146# CONFIG_ARCH_AT91 is not set
147# CONFIG_ARCH_CLPS711X is not set
148# CONFIG_ARCH_EBSA110 is not set
149# CONFIG_ARCH_EP93XX is not set
150# CONFIG_ARCH_GEMINI is not set
151# CONFIG_ARCH_FOOTBRIDGE is not set
152# CONFIG_ARCH_NETX is not set
153# CONFIG_ARCH_H720X is not set
154# CONFIG_ARCH_IMX is not set
155# CONFIG_ARCH_IOP13XX is not set
156# CONFIG_ARCH_IOP32X is not set
157# CONFIG_ARCH_IOP33X is not set
158# CONFIG_ARCH_IXP23XX is not set
159# CONFIG_ARCH_IXP2000 is not set
160# CONFIG_ARCH_IXP4XX is not set
161# CONFIG_ARCH_L7200 is not set
162# CONFIG_ARCH_KIRKWOOD is not set
163# CONFIG_ARCH_KS8695 is not set
164# CONFIG_ARCH_NS9XXX is not set
165# CONFIG_ARCH_LOKI is not set
166# CONFIG_ARCH_MV78XX0 is not set
167# CONFIG_ARCH_MXC is not set
168# CONFIG_ARCH_ORION5X is not set
169# CONFIG_ARCH_PNX4008 is not set
170# CONFIG_ARCH_PXA is not set
171# CONFIG_ARCH_MMP is not set
172# CONFIG_ARCH_RPC is not set
173# CONFIG_ARCH_SA1100 is not set
174# CONFIG_ARCH_S3C2410 is not set
175# CONFIG_ARCH_S3C64XX is not set
176# CONFIG_ARCH_SHARK is not set
177# CONFIG_ARCH_LH7A40X is not set
178CONFIG_ARCH_DAVINCI=y
179# CONFIG_ARCH_OMAP is not set
180# CONFIG_ARCH_MSM is not set
181# CONFIG_ARCH_W90X900 is not set
182
183#
184# TI DaVinci Implementations
185#
186
187#
188# DaVinci Core Type
189#
190CONFIG_ARCH_DAVINCI_DM644x=y
191
192#
193# DaVinci Board Type
194#
195CONFIG_MACH_DAVINCI_EVM=y
196CONFIG_DAVINCI_MUX=y
197CONFIG_DAVINCI_MUX_DEBUG=y
198CONFIG_DAVINCI_MUX_WARNINGS=y
199CONFIG_DAVINCI_RESET_CLOCKS=y
200
201#
202# Processor Type
203#
204CONFIG_CPU_32=y
205CONFIG_CPU_ARM926T=y
206CONFIG_CPU_32v5=y
207CONFIG_CPU_ABRT_EV5TJ=y
208CONFIG_CPU_PABRT_NOIFAR=y
209CONFIG_CPU_CACHE_VIVT=y
210CONFIG_CPU_COPY_V4WB=y
211CONFIG_CPU_TLB_V4WBI=y
212CONFIG_CPU_CP15=y
213CONFIG_CPU_CP15_MMU=y
214
215#
216# Processor Features
217#
218CONFIG_ARM_THUMB=y
219# CONFIG_CPU_ICACHE_DISABLE is not set
220# CONFIG_CPU_DCACHE_DISABLE is not set
221# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
222# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
223# CONFIG_OUTER_CACHE is not set
224CONFIG_COMMON_CLKDEV=y
225
226#
227# Bus support
228#
229# CONFIG_PCI_SYSCALL is not set
230# CONFIG_ARCH_SUPPORTS_MSI is not set
231# CONFIG_PCCARD is not set
232
233#
234# Kernel Features
235#
236CONFIG_TICK_ONESHOT=y
237CONFIG_NO_HZ=y
238CONFIG_HIGH_RES_TIMERS=y
239CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
240CONFIG_VMSPLIT_3G=y
241# CONFIG_VMSPLIT_2G is not set
242# CONFIG_VMSPLIT_1G is not set
243CONFIG_PAGE_OFFSET=0xC0000000
244CONFIG_PREEMPT=y
245CONFIG_HZ=100
246CONFIG_AEABI=y
247# CONFIG_OABI_COMPAT is not set
248CONFIG_ARCH_FLATMEM_HAS_HOLES=y
249# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
250# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
251# CONFIG_HIGHMEM is not set
252CONFIG_SELECT_MEMORY_MODEL=y
253CONFIG_FLATMEM_MANUAL=y
254# CONFIG_DISCONTIGMEM_MANUAL is not set
255# CONFIG_SPARSEMEM_MANUAL is not set
256CONFIG_FLATMEM=y
257CONFIG_FLAT_NODE_MEM_MAP=y
258CONFIG_PAGEFLAGS_EXTENDED=y
259CONFIG_SPLIT_PTLOCK_CPUS=4096
260# CONFIG_PHYS_ADDR_T_64BIT is not set
261CONFIG_ZONE_DMA_FLAG=1
262CONFIG_BOUNCE=y
263CONFIG_VIRT_TO_BUS=y
264CONFIG_UNEVICTABLE_LRU=y
265CONFIG_HAVE_MLOCK=y
266CONFIG_HAVE_MLOCKED_PAGE_BIT=y
267CONFIG_LEDS=y
268# CONFIG_LEDS_CPU is not set
269CONFIG_ALIGNMENT_TRAP=y
270
271#
272# Boot options
273#
274CONFIG_ZBOOT_ROM_TEXT=0x0
275CONFIG_ZBOOT_ROM_BSS=0x0
276CONFIG_CMDLINE=""
277# CONFIG_XIP_KERNEL is not set
278# CONFIG_KEXEC is not set
279
280#
281# CPU Power Management
282#
283# CONFIG_CPU_IDLE is not set
284
285#
286# Floating point emulation
287#
288
289#
290# At least one emulation must be selected
291#
292# CONFIG_VFP is not set
293
294#
295# Userspace binary formats
296#
297CONFIG_BINFMT_ELF=y
298# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
299CONFIG_HAVE_AOUT=y
300# CONFIG_BINFMT_AOUT is not set
301# CONFIG_BINFMT_MISC is not set
302
303#
304# Power management options
305#
306# CONFIG_PM is not set
307CONFIG_ARCH_SUSPEND_POSSIBLE=y
308CONFIG_NET=y
309
310#
311# Networking options
312#
313CONFIG_PACKET=y
314# CONFIG_PACKET_MMAP is not set
315CONFIG_UNIX=y
316CONFIG_XFRM=y
317# CONFIG_XFRM_USER is not set
318# CONFIG_XFRM_SUB_POLICY is not set
319# CONFIG_XFRM_MIGRATE is not set
320# CONFIG_XFRM_STATISTICS is not set
321# CONFIG_NET_KEY is not set
322CONFIG_INET=y
323# CONFIG_IP_MULTICAST is not set
324# CONFIG_IP_ADVANCED_ROUTER is not set
325CONFIG_IP_FIB_HASH=y
326CONFIG_IP_PNP=y
327CONFIG_IP_PNP_DHCP=y
328# CONFIG_IP_PNP_BOOTP is not set
329# CONFIG_IP_PNP_RARP is not set
330# CONFIG_NET_IPIP is not set
331# CONFIG_NET_IPGRE is not set
332# CONFIG_ARPD is not set
333# CONFIG_SYN_COOKIES is not set
334# CONFIG_INET_AH is not set
335# CONFIG_INET_ESP is not set
336# CONFIG_INET_IPCOMP is not set
337# CONFIG_INET_XFRM_TUNNEL is not set
338CONFIG_INET_TUNNEL=m
339CONFIG_INET_XFRM_MODE_TRANSPORT=y
340CONFIG_INET_XFRM_MODE_TUNNEL=y
341CONFIG_INET_XFRM_MODE_BEET=y
342# CONFIG_INET_LRO is not set
343CONFIG_INET_DIAG=y
344CONFIG_INET_TCP_DIAG=y
345# CONFIG_TCP_CONG_ADVANCED is not set
346CONFIG_TCP_CONG_CUBIC=y
347CONFIG_DEFAULT_TCP_CONG="cubic"
348# CONFIG_TCP_MD5SIG is not set
349CONFIG_IPV6=m
350# CONFIG_IPV6_PRIVACY is not set
351# CONFIG_IPV6_ROUTER_PREF is not set
352# CONFIG_IPV6_OPTIMISTIC_DAD is not set
353# CONFIG_INET6_AH is not set
354# CONFIG_INET6_ESP is not set
355# CONFIG_INET6_IPCOMP is not set
356# CONFIG_IPV6_MIP6 is not set
357# CONFIG_INET6_XFRM_TUNNEL is not set
358# CONFIG_INET6_TUNNEL is not set
359CONFIG_INET6_XFRM_MODE_TRANSPORT=m
360CONFIG_INET6_XFRM_MODE_TUNNEL=m
361CONFIG_INET6_XFRM_MODE_BEET=m
362# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
363CONFIG_IPV6_SIT=m
364CONFIG_IPV6_NDISC_NODETYPE=y
365# CONFIG_IPV6_TUNNEL is not set
366# CONFIG_IPV6_MULTIPLE_TABLES is not set
367# CONFIG_IPV6_MROUTE is not set
368# CONFIG_NETWORK_SECMARK is not set
369CONFIG_NETFILTER=y
370# CONFIG_NETFILTER_DEBUG is not set
371CONFIG_NETFILTER_ADVANCED=y
372
373#
374# Core Netfilter Configuration
375#
376# CONFIG_NETFILTER_NETLINK_QUEUE is not set
377# CONFIG_NETFILTER_NETLINK_LOG is not set
378# CONFIG_NF_CONNTRACK is not set
379# CONFIG_NETFILTER_XTABLES is not set
380# CONFIG_IP_VS is not set
381
382#
383# IP: Netfilter Configuration
384#
385# CONFIG_NF_DEFRAG_IPV4 is not set
386# CONFIG_IP_NF_QUEUE is not set
387# CONFIG_IP_NF_IPTABLES is not set
388# CONFIG_IP_NF_ARPTABLES is not set
389
390#
391# IPv6: Netfilter Configuration
392#
393# CONFIG_IP6_NF_QUEUE is not set
394# CONFIG_IP6_NF_IPTABLES is not set
395# CONFIG_IP_DCCP is not set
396# CONFIG_IP_SCTP is not set
397# CONFIG_TIPC is not set
398# CONFIG_ATM is not set
399# CONFIG_BRIDGE is not set
400# CONFIG_NET_DSA is not set
401# CONFIG_VLAN_8021Q is not set
402# CONFIG_DECNET is not set
403# CONFIG_LLC2 is not set
404# CONFIG_IPX is not set
405# CONFIG_ATALK is not set
406# CONFIG_X25 is not set
407# CONFIG_LAPB is not set
408# CONFIG_ECONET is not set
409# CONFIG_WAN_ROUTER is not set
410# CONFIG_PHONET is not set
411# CONFIG_NET_SCHED is not set
412# CONFIG_DCB is not set
413
414#
415# Network testing
416#
417# CONFIG_NET_PKTGEN is not set
418# CONFIG_HAMRADIO is not set
419# CONFIG_CAN is not set
420# CONFIG_IRDA is not set
421# CONFIG_BT is not set
422# CONFIG_AF_RXRPC is not set
423# CONFIG_WIRELESS is not set
424# CONFIG_WIMAX is not set
425# CONFIG_RFKILL is not set
426# CONFIG_NET_9P is not set
427
428#
429# Device Drivers
430#
431
432#
433# Generic Driver Options
434#
435CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
436CONFIG_STANDALONE=y
437CONFIG_PREVENT_FIRMWARE_BUILD=y
438# CONFIG_FW_LOADER is not set
439# CONFIG_DEBUG_DRIVER is not set
440# CONFIG_DEBUG_DEVRES is not set
441# CONFIG_SYS_HYPERVISOR is not set
442# CONFIG_CONNECTOR is not set
443CONFIG_MTD=m
444# CONFIG_MTD_DEBUG is not set
445# CONFIG_MTD_CONCAT is not set
446CONFIG_MTD_PARTITIONS=y
447# CONFIG_MTD_TESTS is not set
448# CONFIG_MTD_REDBOOT_PARTS is not set
449# CONFIG_MTD_AFS_PARTS is not set
450# CONFIG_MTD_AR7_PARTS is not set
451
452#
453# User Modules And Translation Layers
454#
455CONFIG_MTD_CHAR=m
456CONFIG_MTD_BLKDEVS=m
457CONFIG_MTD_BLOCK=m
458# CONFIG_MTD_BLOCK_RO is not set
459# CONFIG_FTL is not set
460# CONFIG_NFTL is not set
461# CONFIG_INFTL is not set
462# CONFIG_RFD_FTL is not set
463# CONFIG_SSFDC is not set
464# CONFIG_MTD_OOPS is not set
465
466#
467# RAM/ROM/Flash chip drivers
468#
469CONFIG_MTD_CFI=m
470# CONFIG_MTD_JEDECPROBE is not set
471CONFIG_MTD_GEN_PROBE=m
472# CONFIG_MTD_CFI_ADV_OPTIONS is not set
473CONFIG_MTD_MAP_BANK_WIDTH_1=y
474CONFIG_MTD_MAP_BANK_WIDTH_2=y
475CONFIG_MTD_MAP_BANK_WIDTH_4=y
476# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
477# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
478# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
479CONFIG_MTD_CFI_I1=y
480CONFIG_MTD_CFI_I2=y
481# CONFIG_MTD_CFI_I4 is not set
482# CONFIG_MTD_CFI_I8 is not set
483# CONFIG_MTD_CFI_INTELEXT is not set
484CONFIG_MTD_CFI_AMDSTD=m
485# CONFIG_MTD_CFI_STAA is not set
486CONFIG_MTD_CFI_UTIL=m
487# CONFIG_MTD_RAM is not set
488# CONFIG_MTD_ROM is not set
489# CONFIG_MTD_ABSENT is not set
490
491#
492# Mapping drivers for chip access
493#
494# CONFIG_MTD_COMPLEX_MAPPINGS is not set
495CONFIG_MTD_PHYSMAP=m
496# CONFIG_MTD_PHYSMAP_COMPAT is not set
497# CONFIG_MTD_ARM_INTEGRATOR is not set
498# CONFIG_MTD_PLATRAM is not set
499
500#
501# Self-contained MTD device drivers
502#
503# CONFIG_MTD_SLRAM is not set
504# CONFIG_MTD_PHRAM is not set
505# CONFIG_MTD_MTDRAM is not set
506# CONFIG_MTD_BLOCK2MTD is not set
507
508#
509# Disk-On-Chip Device Drivers
510#
511# CONFIG_MTD_DOC2000 is not set
512# CONFIG_MTD_DOC2001 is not set
513# CONFIG_MTD_DOC2001PLUS is not set
514CONFIG_MTD_NAND=m
515# CONFIG_MTD_NAND_VERIFY_WRITE is not set
516# CONFIG_MTD_NAND_ECC_SMC is not set
517# CONFIG_MTD_NAND_MUSEUM_IDS is not set
518# CONFIG_MTD_NAND_GPIO is not set
519CONFIG_MTD_NAND_IDS=m
520# CONFIG_MTD_NAND_DISKONCHIP is not set
521# CONFIG_MTD_NAND_NANDSIM is not set
522# CONFIG_MTD_NAND_PLATFORM is not set
523# CONFIG_MTD_ALAUDA is not set
524CONFIG_MTD_NAND_DAVINCI=m
525# CONFIG_MTD_ONENAND is not set
526
527#
528# LPDDR flash memory drivers
529#
530# CONFIG_MTD_LPDDR is not set
531
532#
533# UBI - Unsorted block images
534#
535# CONFIG_MTD_UBI is not set
536# CONFIG_PARPORT is not set
537CONFIG_BLK_DEV=y
538# CONFIG_BLK_DEV_COW_COMMON is not set
539CONFIG_BLK_DEV_LOOP=m
540# CONFIG_BLK_DEV_CRYPTOLOOP is not set
541# CONFIG_BLK_DEV_NBD is not set
542# CONFIG_BLK_DEV_UB is not set
543CONFIG_BLK_DEV_RAM=y
544CONFIG_BLK_DEV_RAM_COUNT=1
545CONFIG_BLK_DEV_RAM_SIZE=32768
546# CONFIG_BLK_DEV_XIP is not set
547# CONFIG_CDROM_PKTCDVD is not set
548# CONFIG_ATA_OVER_ETH is not set
549CONFIG_MISC_DEVICES=y
550# CONFIG_ICS932S401 is not set
551# CONFIG_ENCLOSURE_SERVICES is not set
552# CONFIG_ISL29003 is not set
553# CONFIG_C2PORT is not set
554
555#
556# EEPROM support
557#
558CONFIG_EEPROM_AT24=y
559# CONFIG_EEPROM_LEGACY is not set
560# CONFIG_EEPROM_93CX6 is not set
561CONFIG_HAVE_IDE=y
562CONFIG_IDE=m
563
564#
565# Please see Documentation/ide/ide.txt for help/info on IDE drives
566#
567CONFIG_IDE_XFER_MODE=y
568CONFIG_IDE_TIMINGS=y
569# CONFIG_BLK_DEV_IDE_SATA is not set
570CONFIG_IDE_GD=m
571CONFIG_IDE_GD_ATA=y
572# CONFIG_IDE_GD_ATAPI is not set
573# CONFIG_BLK_DEV_IDECD is not set
574# CONFIG_BLK_DEV_IDETAPE is not set
575# CONFIG_IDE_TASK_IOCTL is not set
576CONFIG_IDE_PROC_FS=y
577
578#
579# IDE chipset support/bugfixes
580#
581# CONFIG_BLK_DEV_PLATFORM is not set
582CONFIG_BLK_DEV_IDEDMA_SFF=y
583CONFIG_BLK_DEV_PALMCHIP_BK3710=m
584CONFIG_BLK_DEV_IDEDMA=y
585
586#
587# SCSI device support
588#
589# CONFIG_RAID_ATTRS is not set
590CONFIG_SCSI=m
591CONFIG_SCSI_DMA=y
592# CONFIG_SCSI_TGT is not set
593# CONFIG_SCSI_NETLINK is not set
594CONFIG_SCSI_PROC_FS=y
595
596#
597# SCSI support type (disk, tape, CD-ROM)
598#
599CONFIG_BLK_DEV_SD=m
600# CONFIG_CHR_DEV_ST is not set
601# CONFIG_CHR_DEV_OSST is not set
602# CONFIG_BLK_DEV_SR is not set
603# CONFIG_CHR_DEV_SG is not set
604# CONFIG_CHR_DEV_SCH is not set
605
606#
607# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
608#
609# CONFIG_SCSI_MULTI_LUN is not set
610# CONFIG_SCSI_CONSTANTS is not set
611# CONFIG_SCSI_LOGGING is not set
612# CONFIG_SCSI_SCAN_ASYNC is not set
613CONFIG_SCSI_WAIT_SCAN=m
614
615#
616# SCSI Transports
617#
618# CONFIG_SCSI_SPI_ATTRS is not set
619# CONFIG_SCSI_FC_ATTRS is not set
620# CONFIG_SCSI_ISCSI_ATTRS is not set
621# CONFIG_SCSI_SAS_LIBSAS is not set
622# CONFIG_SCSI_SRP_ATTRS is not set
623CONFIG_SCSI_LOWLEVEL=y
624# CONFIG_ISCSI_TCP is not set
625# CONFIG_LIBFC is not set
626# CONFIG_LIBFCOE is not set
627# CONFIG_SCSI_DEBUG is not set
628# CONFIG_SCSI_DH is not set
629# CONFIG_SCSI_OSD_INITIATOR is not set
630# CONFIG_ATA is not set
631# CONFIG_MD is not set
632CONFIG_NETDEVICES=y
633CONFIG_COMPAT_NET_DEV_OPS=y
634# CONFIG_DUMMY is not set
635# CONFIG_BONDING is not set
636# CONFIG_MACVLAN is not set
637# CONFIG_EQUALIZER is not set
638CONFIG_TUN=m
639# CONFIG_VETH is not set
640CONFIG_PHYLIB=y
641
642#
643# MII PHY device drivers
644#
645# CONFIG_MARVELL_PHY is not set
646# CONFIG_DAVICOM_PHY is not set
647# CONFIG_QSEMI_PHY is not set
648CONFIG_LXT_PHY=y
649# CONFIG_CICADA_PHY is not set
650# CONFIG_VITESSE_PHY is not set
651# CONFIG_SMSC_PHY is not set
652# CONFIG_BROADCOM_PHY is not set
653# CONFIG_ICPLUS_PHY is not set
654# CONFIG_REALTEK_PHY is not set
655# CONFIG_NATIONAL_PHY is not set
656# CONFIG_STE10XP is not set
657CONFIG_LSI_ET1011C_PHY=y
658# CONFIG_FIXED_PHY is not set
659# CONFIG_MDIO_BITBANG is not set
660CONFIG_NET_ETHERNET=y
661CONFIG_MII=y
662# CONFIG_AX88796 is not set
663# CONFIG_SMC91X is not set
664# CONFIG_DM9000 is not set
665# CONFIG_ETHOC is not set
666# CONFIG_SMC911X is not set
667# CONFIG_SMSC911X is not set
668# CONFIG_DNET is not set
669# CONFIG_IBM_NEW_EMAC_ZMII is not set
670# CONFIG_IBM_NEW_EMAC_RGMII is not set
671# CONFIG_IBM_NEW_EMAC_TAH is not set
672# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
673# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
674# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
675# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
676# CONFIG_B44 is not set
677# CONFIG_NETDEV_1000 is not set
678# CONFIG_NETDEV_10000 is not set
679
680#
681# Wireless LAN
682#
683# CONFIG_WLAN_PRE80211 is not set
684# CONFIG_WLAN_80211 is not set
685
686#
687# Enable WiMAX (Networking options) to see the WiMAX drivers
688#
689
690#
691# USB Network Adapters
692#
693# CONFIG_USB_CATC is not set
694# CONFIG_USB_KAWETH is not set
695# CONFIG_USB_PEGASUS is not set
696# CONFIG_USB_RTL8150 is not set
697# CONFIG_USB_USBNET is not set
698# CONFIG_WAN is not set
699CONFIG_PPP=m
700# CONFIG_PPP_MULTILINK is not set
701# CONFIG_PPP_FILTER is not set
702CONFIG_PPP_ASYNC=m
703CONFIG_PPP_SYNC_TTY=m
704CONFIG_PPP_DEFLATE=m
705# CONFIG_PPP_BSDCOMP is not set
706# CONFIG_PPP_MPPE is not set
707# CONFIG_PPPOE is not set
708# CONFIG_PPPOL2TP is not set
709# CONFIG_SLIP is not set
710CONFIG_SLHC=m
711CONFIG_NETCONSOLE=y
712# CONFIG_NETCONSOLE_DYNAMIC is not set
713CONFIG_NETPOLL=y
714CONFIG_NETPOLL_TRAP=y
715CONFIG_NET_POLL_CONTROLLER=y
716# CONFIG_ISDN is not set
717
718#
719# Input device support
720#
721CONFIG_INPUT=y
722# CONFIG_INPUT_FF_MEMLESS is not set
723# CONFIG_INPUT_POLLDEV is not set
724
725#
726# Userland interfaces
727#
728CONFIG_INPUT_MOUSEDEV=m
729CONFIG_INPUT_MOUSEDEV_PSAUX=y
730CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
731CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
732# CONFIG_INPUT_JOYDEV is not set
733CONFIG_INPUT_EVDEV=m
734CONFIG_INPUT_EVBUG=m
735
736#
737# Input Device Drivers
738#
739CONFIG_INPUT_KEYBOARD=y
740CONFIG_KEYBOARD_ATKBD=m
741# CONFIG_KEYBOARD_SUNKBD is not set
742# CONFIG_KEYBOARD_LKKBD is not set
743CONFIG_KEYBOARD_XTKBD=m
744# CONFIG_KEYBOARD_NEWTON is not set
745# CONFIG_KEYBOARD_STOWAWAY is not set
746CONFIG_KEYBOARD_GPIO=y
747# CONFIG_INPUT_MOUSE is not set
748# CONFIG_INPUT_JOYSTICK is not set
749# CONFIG_INPUT_TABLET is not set
750CONFIG_INPUT_TOUCHSCREEN=y
751# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
752# CONFIG_TOUCHSCREEN_AD7879 is not set
753# CONFIG_TOUCHSCREEN_FUJITSU is not set
754# CONFIG_TOUCHSCREEN_GUNZE is not set
755# CONFIG_TOUCHSCREEN_ELO is not set
756# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
757# CONFIG_TOUCHSCREEN_MTOUCH is not set
758# CONFIG_TOUCHSCREEN_INEXIO is not set
759# CONFIG_TOUCHSCREEN_MK712 is not set
760# CONFIG_TOUCHSCREEN_PENMOUNT is not set
761# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
762# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
763# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
764# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
765# CONFIG_TOUCHSCREEN_TSC2007 is not set
766# CONFIG_INPUT_MISC is not set
767
768#
769# Hardware I/O ports
770#
771CONFIG_SERIO=y
772CONFIG_SERIO_SERPORT=y
773CONFIG_SERIO_LIBPS2=y
774# CONFIG_SERIO_RAW is not set
775# CONFIG_GAMEPORT is not set
776
777#
778# Character devices
779#
780CONFIG_VT=y
781CONFIG_CONSOLE_TRANSLATIONS=y
782# CONFIG_VT_CONSOLE is not set
783CONFIG_HW_CONSOLE=y
784# CONFIG_VT_HW_CONSOLE_BINDING is not set
785CONFIG_DEVKMEM=y
786# CONFIG_SERIAL_NONSTANDARD is not set
787
788#
789# Serial drivers
790#
791CONFIG_SERIAL_8250=y
792CONFIG_SERIAL_8250_CONSOLE=y
793CONFIG_SERIAL_8250_NR_UARTS=3
794CONFIG_SERIAL_8250_RUNTIME_UARTS=3
795# CONFIG_SERIAL_8250_EXTENDED is not set
796
797#
798# Non-8250 serial port support
799#
800CONFIG_SERIAL_CORE=y
801CONFIG_SERIAL_CORE_CONSOLE=y
802CONFIG_UNIX98_PTYS=y
803# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
804CONFIG_LEGACY_PTYS=y
805CONFIG_LEGACY_PTY_COUNT=256
806# CONFIG_IPMI_HANDLER is not set
807CONFIG_HW_RANDOM=m
808# CONFIG_HW_RANDOM_TIMERIOMEM is not set
809# CONFIG_R3964 is not set
810# CONFIG_RAW_DRIVER is not set
811# CONFIG_TCG_TPM is not set
812CONFIG_I2C=y
813CONFIG_I2C_BOARDINFO=y
814CONFIG_I2C_CHARDEV=y
815CONFIG_I2C_HELPER_AUTO=y
816
817#
818# I2C Hardware Bus support
819#
820
821#
822# I2C system bus drivers (mostly embedded / system-on-chip)
823#
824CONFIG_I2C_DAVINCI=y
825# CONFIG_I2C_GPIO is not set
826# CONFIG_I2C_OCORES is not set
827# CONFIG_I2C_SIMTEC is not set
828
829#
830# External I2C/SMBus adapter drivers
831#
832# CONFIG_I2C_PARPORT_LIGHT is not set
833# CONFIG_I2C_TAOS_EVM is not set
834# CONFIG_I2C_TINY_USB is not set
835
836#
837# Other I2C/SMBus bus drivers
838#
839# CONFIG_I2C_PCA_PLATFORM is not set
840# CONFIG_I2C_STUB is not set
841
842#
843# Miscellaneous I2C Chip support
844#
845# CONFIG_DS1682 is not set
846# CONFIG_SENSORS_PCA9539 is not set
847# CONFIG_SENSORS_MAX6875 is not set
848# CONFIG_SENSORS_TSL2550 is not set
849# CONFIG_I2C_DEBUG_CORE is not set
850# CONFIG_I2C_DEBUG_ALGO is not set
851# CONFIG_I2C_DEBUG_BUS is not set
852# CONFIG_I2C_DEBUG_CHIP is not set
853# CONFIG_SPI is not set
854CONFIG_ARCH_REQUIRE_GPIOLIB=y
855CONFIG_GPIOLIB=y
856# CONFIG_DEBUG_GPIO is not set
857# CONFIG_GPIO_SYSFS is not set
858
859#
860# Memory mapped GPIO expanders:
861#
862
863#
864# I2C GPIO expanders:
865#
866# CONFIG_GPIO_MAX732X is not set
867# CONFIG_GPIO_PCA953X is not set
868CONFIG_GPIO_PCF857X=m
869
870#
871# PCI GPIO expanders:
872#
873
874#
875# SPI GPIO expanders:
876#
877# CONFIG_W1 is not set
878# CONFIG_POWER_SUPPLY is not set
879CONFIG_HWMON=y
880# CONFIG_HWMON_VID is not set
881# CONFIG_SENSORS_AD7414 is not set
882# CONFIG_SENSORS_AD7418 is not set
883# CONFIG_SENSORS_ADM1021 is not set
884# CONFIG_SENSORS_ADM1025 is not set
885# CONFIG_SENSORS_ADM1026 is not set
886# CONFIG_SENSORS_ADM1029 is not set
887# CONFIG_SENSORS_ADM1031 is not set
888# CONFIG_SENSORS_ADM9240 is not set
889# CONFIG_SENSORS_ADT7462 is not set
890# CONFIG_SENSORS_ADT7470 is not set
891# CONFIG_SENSORS_ADT7473 is not set
892# CONFIG_SENSORS_ADT7475 is not set
893# CONFIG_SENSORS_ATXP1 is not set
894# CONFIG_SENSORS_DS1621 is not set
895# CONFIG_SENSORS_F71805F is not set
896# CONFIG_SENSORS_F71882FG is not set
897# CONFIG_SENSORS_F75375S is not set
898# CONFIG_SENSORS_G760A is not set
899# CONFIG_SENSORS_GL518SM is not set
900# CONFIG_SENSORS_GL520SM is not set
901# CONFIG_SENSORS_IT87 is not set
902# CONFIG_SENSORS_LM63 is not set
903# CONFIG_SENSORS_LM75 is not set
904# CONFIG_SENSORS_LM77 is not set
905# CONFIG_SENSORS_LM78 is not set
906# CONFIG_SENSORS_LM80 is not set
907# CONFIG_SENSORS_LM83 is not set
908# CONFIG_SENSORS_LM85 is not set
909# CONFIG_SENSORS_LM87 is not set
910# CONFIG_SENSORS_LM90 is not set
911# CONFIG_SENSORS_LM92 is not set
912# CONFIG_SENSORS_LM93 is not set
913# CONFIG_SENSORS_LTC4215 is not set
914# CONFIG_SENSORS_LTC4245 is not set
915# CONFIG_SENSORS_LM95241 is not set
916# CONFIG_SENSORS_MAX1619 is not set
917# CONFIG_SENSORS_MAX6650 is not set
918# CONFIG_SENSORS_PC87360 is not set
919# CONFIG_SENSORS_PC87427 is not set
920# CONFIG_SENSORS_PCF8591 is not set
921# CONFIG_SENSORS_SHT15 is not set
922# CONFIG_SENSORS_DME1737 is not set
923# CONFIG_SENSORS_SMSC47M1 is not set
924# CONFIG_SENSORS_SMSC47M192 is not set
925# CONFIG_SENSORS_SMSC47B397 is not set
926# CONFIG_SENSORS_ADS7828 is not set
927# CONFIG_SENSORS_THMC50 is not set
928# CONFIG_SENSORS_VT1211 is not set
929# CONFIG_SENSORS_W83781D is not set
930# CONFIG_SENSORS_W83791D is not set
931# CONFIG_SENSORS_W83792D is not set
932# CONFIG_SENSORS_W83793 is not set
933# CONFIG_SENSORS_W83L785TS is not set
934# CONFIG_SENSORS_W83L786NG is not set
935# CONFIG_SENSORS_W83627HF is not set
936# CONFIG_SENSORS_W83627EHF is not set
937# CONFIG_HWMON_DEBUG_CHIP is not set
938# CONFIG_THERMAL is not set
939# CONFIG_THERMAL_HWMON is not set
940CONFIG_WATCHDOG=y
941# CONFIG_WATCHDOG_NOWAYOUT is not set
942
943#
944# Watchdog Device Drivers
945#
946# CONFIG_SOFT_WATCHDOG is not set
947CONFIG_DAVINCI_WATCHDOG=m
948
949#
950# USB-based Watchdog Cards
951#
952# CONFIG_USBPCWATCHDOG is not set
953CONFIG_SSB_POSSIBLE=y
954
955#
956# Sonics Silicon Backplane
957#
958# CONFIG_SSB is not set
959
960#
961# Multifunction device drivers
962#
963# CONFIG_MFD_CORE is not set
964# CONFIG_MFD_SM501 is not set
965# CONFIG_MFD_ASIC3 is not set
966# CONFIG_HTC_EGPIO is not set
967# CONFIG_HTC_PASIC3 is not set
968# CONFIG_TPS65010 is not set
969# CONFIG_TWL4030_CORE is not set
970# CONFIG_MFD_TMIO is not set
971# CONFIG_MFD_T7L66XB is not set
972# CONFIG_MFD_TC6387XB is not set
973# CONFIG_MFD_TC6393XB is not set
974# CONFIG_PMIC_DA903X is not set
975# CONFIG_MFD_WM8400 is not set
976# CONFIG_MFD_WM8350_I2C is not set
977# CONFIG_MFD_PCF50633 is not set
978
979#
980# Multimedia devices
981#
982
983#
984# Multimedia core support
985#
986CONFIG_VIDEO_DEV=y
987CONFIG_VIDEO_V4L2_COMMON=y
988CONFIG_VIDEO_ALLOW_V4L1=y
989CONFIG_VIDEO_V4L1_COMPAT=y
990# CONFIG_DVB_CORE is not set
991CONFIG_VIDEO_MEDIA=y
992
993#
994# Multimedia drivers
995#
996# CONFIG_MEDIA_ATTACH is not set
997CONFIG_MEDIA_TUNER=y
998# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
999CONFIG_MEDIA_TUNER_SIMPLE=y
1000CONFIG_MEDIA_TUNER_TDA8290=y
1001CONFIG_MEDIA_TUNER_TDA9887=y
1002CONFIG_MEDIA_TUNER_TEA5761=y
1003CONFIG_MEDIA_TUNER_TEA5767=y
1004CONFIG_MEDIA_TUNER_MT20XX=y
1005CONFIG_MEDIA_TUNER_XC2028=y
1006CONFIG_MEDIA_TUNER_XC5000=y
1007CONFIG_MEDIA_TUNER_MC44S803=y
1008CONFIG_VIDEO_V4L2=y
1009CONFIG_VIDEO_V4L1=y
1010CONFIG_VIDEO_CAPTURE_DRIVERS=y
1011# CONFIG_VIDEO_ADV_DEBUG is not set
1012# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
1013CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
1014# CONFIG_VIDEO_VIVI is not set
1015# CONFIG_VIDEO_CPIA is not set
1016# CONFIG_VIDEO_CPIA2 is not set
1017# CONFIG_VIDEO_SAA5246A is not set
1018# CONFIG_VIDEO_SAA5249 is not set
1019# CONFIG_SOC_CAMERA is not set
1020# CONFIG_V4L_USB_DRIVERS is not set
1021# CONFIG_RADIO_ADAPTERS is not set
1022CONFIG_DAB=y
1023# CONFIG_USB_DABUSB is not set
1024
1025#
1026# Graphics support
1027#
1028# CONFIG_VGASTATE is not set
1029CONFIG_VIDEO_OUTPUT_CONTROL=m
1030CONFIG_FB=y
1031CONFIG_FIRMWARE_EDID=y
1032# CONFIG_FB_DDC is not set
1033# CONFIG_FB_BOOT_VESA_SUPPORT is not set
1034# CONFIG_FB_CFB_FILLRECT is not set
1035# CONFIG_FB_CFB_COPYAREA is not set
1036# CONFIG_FB_CFB_IMAGEBLIT is not set
1037# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
1038# CONFIG_FB_SYS_FILLRECT is not set
1039# CONFIG_FB_SYS_COPYAREA is not set
1040# CONFIG_FB_SYS_IMAGEBLIT is not set
1041# CONFIG_FB_FOREIGN_ENDIAN is not set
1042# CONFIG_FB_SYS_FOPS is not set
1043# CONFIG_FB_SVGALIB is not set
1044# CONFIG_FB_MACMODES is not set
1045# CONFIG_FB_BACKLIGHT is not set
1046# CONFIG_FB_MODE_HELPERS is not set
1047# CONFIG_FB_TILEBLITTING is not set
1048
1049#
1050# Frame buffer hardware drivers
1051#
1052# CONFIG_FB_S1D13XXX is not set
1053# CONFIG_FB_VIRTUAL is not set
1054# CONFIG_FB_METRONOME is not set
1055# CONFIG_FB_MB862XX is not set
1056# CONFIG_FB_BROADSHEET is not set
1057# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1058
1059#
1060# Display device support
1061#
1062# CONFIG_DISPLAY_SUPPORT is not set
1063
1064#
1065# Console display driver support
1066#
1067# CONFIG_VGA_CONSOLE is not set
1068CONFIG_DUMMY_CONSOLE=y
1069CONFIG_FRAMEBUFFER_CONSOLE=y
1070# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
1071# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
1072# CONFIG_FONTS is not set
1073CONFIG_FONT_8x8=y
1074CONFIG_FONT_8x16=y
1075CONFIG_LOGO=y
1076CONFIG_LOGO_LINUX_MONO=y
1077CONFIG_LOGO_LINUX_VGA16=y
1078CONFIG_LOGO_LINUX_CLUT224=y
1079CONFIG_SOUND=m
1080# CONFIG_SOUND_OSS_CORE is not set
1081CONFIG_SND=m
1082CONFIG_SND_TIMER=m
1083CONFIG_SND_PCM=m
1084CONFIG_SND_JACK=y
1085# CONFIG_SND_SEQUENCER is not set
1086# CONFIG_SND_MIXER_OSS is not set
1087# CONFIG_SND_PCM_OSS is not set
1088# CONFIG_SND_HRTIMER is not set
1089# CONFIG_SND_DYNAMIC_MINORS is not set
1090CONFIG_SND_SUPPORT_OLD_API=y
1091CONFIG_SND_VERBOSE_PROCFS=y
1092# CONFIG_SND_VERBOSE_PRINTK is not set
1093# CONFIG_SND_DEBUG is not set
1094CONFIG_SND_DRIVERS=y
1095# CONFIG_SND_DUMMY is not set
1096# CONFIG_SND_MTPAV is not set
1097# CONFIG_SND_SERIAL_U16550 is not set
1098# CONFIG_SND_MPU401 is not set
1099CONFIG_SND_ARM=y
1100CONFIG_SND_USB=y
1101# CONFIG_SND_USB_AUDIO is not set
1102# CONFIG_SND_USB_CAIAQ is not set
1103CONFIG_SND_SOC=m
1104# CONFIG_SND_DAVINCI_SOC is not set
1105CONFIG_SND_SOC_I2C_AND_SPI=m
1106# CONFIG_SND_SOC_ALL_CODECS is not set
1107# CONFIG_SOUND_PRIME is not set
1108CONFIG_HID_SUPPORT=y
1109CONFIG_HID=m
1110# CONFIG_HID_DEBUG is not set
1111# CONFIG_HIDRAW is not set
1112
1113#
1114# USB Input Devices
1115#
1116CONFIG_USB_HID=m
1117# CONFIG_HID_PID is not set
1118# CONFIG_USB_HIDDEV is not set
1119
1120#
1121# USB HID Boot Protocol drivers
1122#
1123# CONFIG_USB_KBD is not set
1124# CONFIG_USB_MOUSE is not set
1125
1126#
1127# Special HID drivers
1128#
1129CONFIG_HID_A4TECH=m
1130CONFIG_HID_APPLE=m
1131CONFIG_HID_BELKIN=m
1132CONFIG_HID_CHERRY=m
1133CONFIG_HID_CHICONY=m
1134CONFIG_HID_CYPRESS=m
1135# CONFIG_DRAGONRISE_FF is not set
1136CONFIG_HID_EZKEY=m
1137# CONFIG_HID_KYE is not set
1138CONFIG_HID_GYRATION=m
1139# CONFIG_HID_KENSINGTON is not set
1140CONFIG_HID_LOGITECH=m
1141# CONFIG_LOGITECH_FF is not set
1142# CONFIG_LOGIRUMBLEPAD2_FF is not set
1143CONFIG_HID_MICROSOFT=m
1144CONFIG_HID_MONTEREY=m
1145# CONFIG_HID_NTRIG is not set
1146CONFIG_HID_PANTHERLORD=m
1147# CONFIG_PANTHERLORD_FF is not set
1148CONFIG_HID_PETALYNX=m
1149CONFIG_HID_SAMSUNG=m
1150CONFIG_HID_SONY=m
1151CONFIG_HID_SUNPLUS=m
1152# CONFIG_GREENASIA_FF is not set
1153# CONFIG_HID_TOPSEED is not set
1154# CONFIG_THRUSTMASTER_FF is not set
1155# CONFIG_ZEROPLUS_FF is not set
1156CONFIG_USB_SUPPORT=y
1157CONFIG_USB_ARCH_HAS_HCD=y
1158# CONFIG_USB_ARCH_HAS_OHCI is not set
1159# CONFIG_USB_ARCH_HAS_EHCI is not set
1160CONFIG_USB=m
1161# CONFIG_USB_DEBUG is not set
1162# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
1163
1164#
1165# Miscellaneous USB options
1166#
1167CONFIG_USB_DEVICEFS=y
1168CONFIG_USB_DEVICE_CLASS=y
1169# CONFIG_USB_DYNAMIC_MINORS is not set
1170# CONFIG_USB_OTG is not set
1171# CONFIG_USB_OTG_WHITELIST is not set
1172# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1173CONFIG_USB_MON=m
1174# CONFIG_USB_WUSB is not set
1175# CONFIG_USB_WUSB_CBAF is not set
1176
1177#
1178# USB Host Controller Drivers
1179#
1180# CONFIG_USB_C67X00_HCD is not set
1181# CONFIG_USB_OXU210HP_HCD is not set
1182# CONFIG_USB_ISP116X_HCD is not set
1183# CONFIG_USB_ISP1760_HCD is not set
1184# CONFIG_USB_SL811_HCD is not set
1185# CONFIG_USB_R8A66597_HCD is not set
1186# CONFIG_USB_HWA_HCD is not set
1187CONFIG_USB_MUSB_HDRC=m
1188CONFIG_USB_MUSB_SOC=y
1189
1190#
1191# DaVinci 35x and 644x USB support
1192#
1193# CONFIG_USB_MUSB_HOST is not set
1194CONFIG_USB_MUSB_PERIPHERAL=y
1195# CONFIG_USB_MUSB_OTG is not set
1196CONFIG_USB_GADGET_MUSB_HDRC=y
1197CONFIG_MUSB_PIO_ONLY=y
1198# CONFIG_USB_MUSB_DEBUG is not set
1199
1200#
1201# USB Device Class drivers
1202#
1203# CONFIG_USB_ACM is not set
1204# CONFIG_USB_PRINTER is not set
1205# CONFIG_USB_WDM is not set
1206# CONFIG_USB_TMC is not set
1207
1208#
1209# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1210#
1211
1212#
1213# also be needed; see USB_STORAGE Help for more info
1214#
1215CONFIG_USB_STORAGE=m
1216# CONFIG_USB_STORAGE_DEBUG is not set
1217# CONFIG_USB_STORAGE_DATAFAB is not set
1218# CONFIG_USB_STORAGE_FREECOM is not set
1219# CONFIG_USB_STORAGE_ISD200 is not set
1220# CONFIG_USB_STORAGE_USBAT is not set
1221# CONFIG_USB_STORAGE_SDDR09 is not set
1222# CONFIG_USB_STORAGE_SDDR55 is not set
1223# CONFIG_USB_STORAGE_JUMPSHOT is not set
1224# CONFIG_USB_STORAGE_ALAUDA is not set
1225# CONFIG_USB_STORAGE_ONETOUCH is not set
1226# CONFIG_USB_STORAGE_KARMA is not set
1227# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1228# CONFIG_USB_LIBUSUAL is not set
1229
1230#
1231# USB Imaging devices
1232#
1233# CONFIG_USB_MDC800 is not set
1234# CONFIG_USB_MICROTEK is not set
1235
1236#
1237# USB port drivers
1238#
1239# CONFIG_USB_SERIAL is not set
1240
1241#
1242# USB Miscellaneous drivers
1243#
1244# CONFIG_USB_EMI62 is not set
1245# CONFIG_USB_EMI26 is not set
1246# CONFIG_USB_ADUTUX is not set
1247# CONFIG_USB_SEVSEG is not set
1248# CONFIG_USB_RIO500 is not set
1249# CONFIG_USB_LEGOTOWER is not set
1250# CONFIG_USB_LCD is not set
1251# CONFIG_USB_BERRY_CHARGE is not set
1252# CONFIG_USB_LED is not set
1253# CONFIG_USB_CYPRESS_CY7C63 is not set
1254# CONFIG_USB_CYTHERM is not set
1255# CONFIG_USB_IDMOUSE is not set
1256# CONFIG_USB_FTDI_ELAN is not set
1257# CONFIG_USB_APPLEDISPLAY is not set
1258# CONFIG_USB_LD is not set
1259# CONFIG_USB_TRANCEVIBRATOR is not set
1260# CONFIG_USB_IOWARRIOR is not set
1261CONFIG_USB_TEST=m
1262# CONFIG_USB_ISIGHTFW is not set
1263# CONFIG_USB_VST is not set
1264CONFIG_USB_GADGET=m
1265# CONFIG_USB_GADGET_DEBUG is not set
1266CONFIG_USB_GADGET_DEBUG_FILES=y
1267CONFIG_USB_GADGET_DEBUG_FS=y
1268CONFIG_USB_GADGET_VBUS_DRAW=2
1269CONFIG_USB_GADGET_SELECTED=y
1270# CONFIG_USB_GADGET_AT91 is not set
1271# CONFIG_USB_GADGET_ATMEL_USBA is not set
1272# CONFIG_USB_GADGET_FSL_USB2 is not set
1273# CONFIG_USB_GADGET_LH7A40X is not set
1274# CONFIG_USB_GADGET_OMAP is not set
1275# CONFIG_USB_GADGET_PXA25X is not set
1276# CONFIG_USB_GADGET_PXA27X is not set
1277# CONFIG_USB_GADGET_S3C2410 is not set
1278# CONFIG_USB_GADGET_IMX is not set
1279# CONFIG_USB_GADGET_M66592 is not set
1280# CONFIG_USB_GADGET_AMD5536UDC is not set
1281# CONFIG_USB_GADGET_FSL_QE is not set
1282# CONFIG_USB_GADGET_CI13XXX is not set
1283# CONFIG_USB_GADGET_NET2280 is not set
1284# CONFIG_USB_GADGET_GOKU is not set
1285# CONFIG_USB_GADGET_DUMMY_HCD is not set
1286CONFIG_USB_GADGET_DUALSPEED=y
1287CONFIG_USB_ZERO=m
1288CONFIG_USB_ETH=m
1289CONFIG_USB_ETH_RNDIS=y
1290CONFIG_USB_GADGETFS=m
1291CONFIG_USB_FILE_STORAGE=m
1292# CONFIG_USB_FILE_STORAGE_TEST is not set
1293CONFIG_USB_G_SERIAL=m
1294# CONFIG_USB_MIDI_GADGET is not set
1295CONFIG_USB_G_PRINTER=m
1296CONFIG_USB_CDC_COMPOSITE=m
1297
1298#
1299# OTG and related infrastructure
1300#
1301CONFIG_USB_OTG_UTILS=y
1302# CONFIG_USB_GPIO_VBUS is not set
1303# CONFIG_NOP_USB_XCEIV is not set
1304CONFIG_MMC=m
1305# CONFIG_MMC_DEBUG is not set
1306# CONFIG_MMC_UNSAFE_RESUME is not set
1307
1308#
1309# MMC/SD/SDIO Card Drivers
1310#
1311CONFIG_MMC_BLOCK=m
1312# CONFIG_MMC_BLOCK_BOUNCE is not set
1313# CONFIG_SDIO_UART is not set
1314# CONFIG_MMC_TEST is not set
1315
1316#
1317# MMC/SD/SDIO Host Controller Drivers
1318#
1319# CONFIG_MMC_SDHCI is not set
1320# CONFIG_MEMSTICK is not set
1321# CONFIG_ACCESSIBILITY is not set
1322CONFIG_NEW_LEDS=y
1323CONFIG_LEDS_CLASS=m
1324
1325#
1326# LED drivers
1327#
1328# CONFIG_LEDS_PCA9532 is not set
1329CONFIG_LEDS_GPIO=m
1330CONFIG_LEDS_GPIO_PLATFORM=y
1331# CONFIG_LEDS_LP5521 is not set
1332# CONFIG_LEDS_PCA955X is not set
1333# CONFIG_LEDS_BD2802 is not set
1334
1335#
1336# LED Triggers
1337#
1338CONFIG_LEDS_TRIGGERS=y
1339CONFIG_LEDS_TRIGGER_TIMER=m
1340# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
1341CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1342# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
1343# CONFIG_LEDS_TRIGGER_GPIO is not set
1344# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
1345
1346#
1347# iptables trigger is under Netfilter config (LED target)
1348#
1349CONFIG_RTC_LIB=y
1350CONFIG_RTC_CLASS=m
1351
1352#
1353# RTC interfaces
1354#
1355CONFIG_RTC_INTF_SYSFS=y
1356CONFIG_RTC_INTF_PROC=y
1357CONFIG_RTC_INTF_DEV=y
1358# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1359# CONFIG_RTC_DRV_TEST is not set
1360
1361#
1362# I2C RTC drivers
1363#
1364# CONFIG_RTC_DRV_DS1307 is not set
1365# CONFIG_RTC_DRV_DS1374 is not set
1366# CONFIG_RTC_DRV_DS1672 is not set
1367# CONFIG_RTC_DRV_MAX6900 is not set
1368# CONFIG_RTC_DRV_RS5C372 is not set
1369# CONFIG_RTC_DRV_ISL1208 is not set
1370# CONFIG_RTC_DRV_X1205 is not set
1371# CONFIG_RTC_DRV_PCF8563 is not set
1372# CONFIG_RTC_DRV_PCF8583 is not set
1373# CONFIG_RTC_DRV_M41T80 is not set
1374# CONFIG_RTC_DRV_S35390A is not set
1375# CONFIG_RTC_DRV_FM3130 is not set
1376# CONFIG_RTC_DRV_RX8581 is not set
1377
1378#
1379# SPI RTC drivers
1380#
1381
1382#
1383# Platform RTC drivers
1384#
1385# CONFIG_RTC_DRV_CMOS is not set
1386# CONFIG_RTC_DRV_DS1286 is not set
1387# CONFIG_RTC_DRV_DS1511 is not set
1388# CONFIG_RTC_DRV_DS1553 is not set
1389# CONFIG_RTC_DRV_DS1742 is not set
1390# CONFIG_RTC_DRV_STK17TA8 is not set
1391# CONFIG_RTC_DRV_M48T86 is not set
1392# CONFIG_RTC_DRV_M48T35 is not set
1393# CONFIG_RTC_DRV_M48T59 is not set
1394# CONFIG_RTC_DRV_BQ4802 is not set
1395# CONFIG_RTC_DRV_V3020 is not set
1396
1397#
1398# on-CPU RTC drivers
1399#
1400# CONFIG_DMADEVICES is not set
1401# CONFIG_AUXDISPLAY is not set
1402# CONFIG_REGULATOR is not set
1403# CONFIG_UIO is not set
1404# CONFIG_STAGING is not set
1405
1406#
1407# File systems
1408#
1409CONFIG_EXT2_FS=y
1410# CONFIG_EXT2_FS_XATTR is not set
1411# CONFIG_EXT2_FS_XIP is not set
1412CONFIG_EXT3_FS=y
1413# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1414CONFIG_EXT3_FS_XATTR=y
1415# CONFIG_EXT3_FS_POSIX_ACL is not set
1416# CONFIG_EXT3_FS_SECURITY is not set
1417# CONFIG_EXT4_FS is not set
1418CONFIG_JBD=y
1419# CONFIG_JBD_DEBUG is not set
1420CONFIG_FS_MBCACHE=y
1421# CONFIG_REISERFS_FS is not set
1422# CONFIG_JFS_FS is not set
1423# CONFIG_FS_POSIX_ACL is not set
1424CONFIG_FILE_LOCKING=y
1425CONFIG_XFS_FS=m
1426# CONFIG_XFS_QUOTA is not set
1427# CONFIG_XFS_POSIX_ACL is not set
1428# CONFIG_XFS_RT is not set
1429# CONFIG_XFS_DEBUG is not set
1430# CONFIG_OCFS2_FS is not set
1431# CONFIG_BTRFS_FS is not set
1432CONFIG_DNOTIFY=y
1433CONFIG_INOTIFY=y
1434CONFIG_INOTIFY_USER=y
1435# CONFIG_QUOTA is not set
1436# CONFIG_AUTOFS_FS is not set
1437CONFIG_AUTOFS4_FS=m
1438# CONFIG_FUSE_FS is not set
1439
1440#
1441# Caches
1442#
1443# CONFIG_FSCACHE is not set
1444
1445#
1446# CD-ROM/DVD Filesystems
1447#
1448# CONFIG_ISO9660_FS is not set
1449# CONFIG_UDF_FS is not set
1450
1451#
1452# DOS/FAT/NT Filesystems
1453#
1454CONFIG_FAT_FS=y
1455CONFIG_MSDOS_FS=y
1456CONFIG_VFAT_FS=y
1457CONFIG_FAT_DEFAULT_CODEPAGE=437
1458CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1459# CONFIG_NTFS_FS is not set
1460
1461#
1462# Pseudo filesystems
1463#
1464CONFIG_PROC_FS=y
1465CONFIG_PROC_SYSCTL=y
1466CONFIG_PROC_PAGE_MONITOR=y
1467CONFIG_SYSFS=y
1468CONFIG_TMPFS=y
1469# CONFIG_TMPFS_POSIX_ACL is not set
1470# CONFIG_HUGETLB_PAGE is not set
1471# CONFIG_CONFIGFS_FS is not set
1472CONFIG_MISC_FILESYSTEMS=y
1473# CONFIG_ADFS_FS is not set
1474# CONFIG_AFFS_FS is not set
1475# CONFIG_HFS_FS is not set
1476# CONFIG_HFSPLUS_FS is not set
1477# CONFIG_BEFS_FS is not set
1478# CONFIG_BFS_FS is not set
1479# CONFIG_EFS_FS is not set
1480CONFIG_JFFS2_FS=m
1481CONFIG_JFFS2_FS_DEBUG=0
1482CONFIG_JFFS2_FS_WRITEBUFFER=y
1483# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1484# CONFIG_JFFS2_SUMMARY is not set
1485# CONFIG_JFFS2_FS_XATTR is not set
1486# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1487CONFIG_JFFS2_ZLIB=y
1488# CONFIG_JFFS2_LZO is not set
1489CONFIG_JFFS2_RTIME=y
1490# CONFIG_JFFS2_RUBIN is not set
1491CONFIG_CRAMFS=y
1492# CONFIG_SQUASHFS is not set
1493# CONFIG_VXFS_FS is not set
1494CONFIG_MINIX_FS=m
1495# CONFIG_OMFS_FS is not set
1496# CONFIG_HPFS_FS is not set
1497# CONFIG_QNX4FS_FS is not set
1498# CONFIG_ROMFS_FS is not set
1499# CONFIG_SYSV_FS is not set
1500# CONFIG_UFS_FS is not set
1501# CONFIG_NILFS2_FS is not set
1502CONFIG_NETWORK_FILESYSTEMS=y
1503CONFIG_NFS_FS=y
1504CONFIG_NFS_V3=y
1505# CONFIG_NFS_V3_ACL is not set
1506# CONFIG_NFS_V4 is not set
1507CONFIG_ROOT_NFS=y
1508CONFIG_NFSD=m
1509CONFIG_NFSD_V3=y
1510# CONFIG_NFSD_V3_ACL is not set
1511# CONFIG_NFSD_V4 is not set
1512CONFIG_LOCKD=y
1513CONFIG_LOCKD_V4=y
1514CONFIG_EXPORTFS=m
1515CONFIG_NFS_COMMON=y
1516CONFIG_SUNRPC=y
1517# CONFIG_RPCSEC_GSS_KRB5 is not set
1518# CONFIG_RPCSEC_GSS_SPKM3 is not set
1519CONFIG_SMB_FS=m
1520# CONFIG_SMB_NLS_DEFAULT is not set
1521# CONFIG_CIFS is not set
1522# CONFIG_NCP_FS is not set
1523# CONFIG_CODA_FS is not set
1524# CONFIG_AFS_FS is not set
1525
1526#
1527# Partition Types
1528#
1529CONFIG_PARTITION_ADVANCED=y
1530# CONFIG_ACORN_PARTITION is not set
1531# CONFIG_OSF_PARTITION is not set
1532# CONFIG_AMIGA_PARTITION is not set
1533# CONFIG_ATARI_PARTITION is not set
1534# CONFIG_MAC_PARTITION is not set
1535CONFIG_MSDOS_PARTITION=y
1536# CONFIG_BSD_DISKLABEL is not set
1537# CONFIG_MINIX_SUBPARTITION is not set
1538# CONFIG_SOLARIS_X86_PARTITION is not set
1539# CONFIG_UNIXWARE_DISKLABEL is not set
1540# CONFIG_LDM_PARTITION is not set
1541# CONFIG_SGI_PARTITION is not set
1542# CONFIG_ULTRIX_PARTITION is not set
1543# CONFIG_SUN_PARTITION is not set
1544# CONFIG_KARMA_PARTITION is not set
1545# CONFIG_EFI_PARTITION is not set
1546# CONFIG_SYSV68_PARTITION is not set
1547CONFIG_NLS=y
1548CONFIG_NLS_DEFAULT="iso8859-1"
1549CONFIG_NLS_CODEPAGE_437=y
1550# CONFIG_NLS_CODEPAGE_737 is not set
1551# CONFIG_NLS_CODEPAGE_775 is not set
1552# CONFIG_NLS_CODEPAGE_850 is not set
1553# CONFIG_NLS_CODEPAGE_852 is not set
1554# CONFIG_NLS_CODEPAGE_855 is not set
1555# CONFIG_NLS_CODEPAGE_857 is not set
1556# CONFIG_NLS_CODEPAGE_860 is not set
1557# CONFIG_NLS_CODEPAGE_861 is not set
1558# CONFIG_NLS_CODEPAGE_862 is not set
1559# CONFIG_NLS_CODEPAGE_863 is not set
1560# CONFIG_NLS_CODEPAGE_864 is not set
1561# CONFIG_NLS_CODEPAGE_865 is not set
1562# CONFIG_NLS_CODEPAGE_866 is not set
1563# CONFIG_NLS_CODEPAGE_869 is not set
1564# CONFIG_NLS_CODEPAGE_936 is not set
1565# CONFIG_NLS_CODEPAGE_950 is not set
1566# CONFIG_NLS_CODEPAGE_932 is not set
1567# CONFIG_NLS_CODEPAGE_949 is not set
1568# CONFIG_NLS_CODEPAGE_874 is not set
1569# CONFIG_NLS_ISO8859_8 is not set
1570# CONFIG_NLS_CODEPAGE_1250 is not set
1571# CONFIG_NLS_CODEPAGE_1251 is not set
1572CONFIG_NLS_ASCII=m
1573CONFIG_NLS_ISO8859_1=y
1574# CONFIG_NLS_ISO8859_2 is not set
1575# CONFIG_NLS_ISO8859_3 is not set
1576# CONFIG_NLS_ISO8859_4 is not set
1577# CONFIG_NLS_ISO8859_5 is not set
1578# CONFIG_NLS_ISO8859_6 is not set
1579# CONFIG_NLS_ISO8859_7 is not set
1580# CONFIG_NLS_ISO8859_9 is not set
1581# CONFIG_NLS_ISO8859_13 is not set
1582# CONFIG_NLS_ISO8859_14 is not set
1583# CONFIG_NLS_ISO8859_15 is not set
1584# CONFIG_NLS_KOI8_R is not set
1585# CONFIG_NLS_KOI8_U is not set
1586CONFIG_NLS_UTF8=m
1587# CONFIG_DLM is not set
1588
1589#
1590# Kernel hacking
1591#
1592# CONFIG_PRINTK_TIME is not set
1593CONFIG_ENABLE_WARN_DEPRECATED=y
1594CONFIG_ENABLE_MUST_CHECK=y
1595CONFIG_FRAME_WARN=1024
1596# CONFIG_MAGIC_SYSRQ is not set
1597# CONFIG_UNUSED_SYMBOLS is not set
1598CONFIG_DEBUG_FS=y
1599# CONFIG_HEADERS_CHECK is not set
1600CONFIG_DEBUG_KERNEL=y
1601# CONFIG_DEBUG_SHIRQ is not set
1602CONFIG_DETECT_SOFTLOCKUP=y
1603# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1604CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1605CONFIG_DETECT_HUNG_TASK=y
1606# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1607CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1608CONFIG_SCHED_DEBUG=y
1609# CONFIG_SCHEDSTATS is not set
1610CONFIG_TIMER_STATS=y
1611# CONFIG_DEBUG_OBJECTS is not set
1612# CONFIG_SLUB_DEBUG_ON is not set
1613# CONFIG_SLUB_STATS is not set
1614CONFIG_DEBUG_PREEMPT=y
1615CONFIG_DEBUG_RT_MUTEXES=y
1616CONFIG_DEBUG_PI_LIST=y
1617# CONFIG_RT_MUTEX_TESTER is not set
1618# CONFIG_DEBUG_SPINLOCK is not set
1619CONFIG_DEBUG_MUTEXES=y
1620# CONFIG_DEBUG_LOCK_ALLOC is not set
1621# CONFIG_PROVE_LOCKING is not set
1622# CONFIG_LOCK_STAT is not set
1623# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1624# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1625# CONFIG_DEBUG_KOBJECT is not set
1626CONFIG_DEBUG_BUGVERBOSE=y
1627# CONFIG_DEBUG_INFO is not set
1628# CONFIG_DEBUG_VM is not set
1629# CONFIG_DEBUG_WRITECOUNT is not set
1630# CONFIG_DEBUG_MEMORY_INIT is not set
1631# CONFIG_DEBUG_LIST is not set
1632# CONFIG_DEBUG_SG is not set
1633# CONFIG_DEBUG_NOTIFIERS is not set
1634# CONFIG_BOOT_PRINTK_DELAY is not set
1635# CONFIG_RCU_TORTURE_TEST is not set
1636# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1637# CONFIG_BACKTRACE_SELF_TEST is not set
1638# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1639# CONFIG_FAULT_INJECTION is not set
1640# CONFIG_LATENCYTOP is not set
1641# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1642# CONFIG_PAGE_POISONING is not set
1643CONFIG_HAVE_FUNCTION_TRACER=y
1644CONFIG_TRACING_SUPPORT=y
1645
1646#
1647# Tracers
1648#
1649# CONFIG_FUNCTION_TRACER is not set
1650# CONFIG_IRQSOFF_TRACER is not set
1651# CONFIG_PREEMPT_TRACER is not set
1652# CONFIG_SCHED_TRACER is not set
1653# CONFIG_CONTEXT_SWITCH_TRACER is not set
1654# CONFIG_EVENT_TRACER is not set
1655# CONFIG_BOOT_TRACER is not set
1656# CONFIG_TRACE_BRANCH_PROFILING is not set
1657# CONFIG_STACK_TRACER is not set
1658# CONFIG_KMEMTRACE is not set
1659# CONFIG_WORKQUEUE_TRACER is not set
1660# CONFIG_BLK_DEV_IO_TRACE is not set
1661# CONFIG_DYNAMIC_DEBUG is not set
1662# CONFIG_SAMPLES is not set
1663CONFIG_HAVE_ARCH_KGDB=y
1664# CONFIG_KGDB is not set
1665CONFIG_ARM_UNWIND=y
1666CONFIG_DEBUG_USER=y
1667CONFIG_DEBUG_ERRORS=y
1668# CONFIG_DEBUG_STACK_USAGE is not set
1669# CONFIG_DEBUG_LL is not set
1670
1671#
1672# Security options
1673#
1674# CONFIG_KEYS is not set
1675# CONFIG_SECURITY is not set
1676# CONFIG_SECURITYFS is not set
1677# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1678CONFIG_CRYPTO=y
1679
1680#
1681# Crypto core or helper
1682#
1683# CONFIG_CRYPTO_FIPS is not set
1684# CONFIG_CRYPTO_MANAGER is not set
1685# CONFIG_CRYPTO_MANAGER2 is not set
1686# CONFIG_CRYPTO_GF128MUL is not set
1687# CONFIG_CRYPTO_NULL is not set
1688# CONFIG_CRYPTO_CRYPTD is not set
1689# CONFIG_CRYPTO_AUTHENC is not set
1690# CONFIG_CRYPTO_TEST is not set
1691
1692#
1693# Authenticated Encryption with Associated Data
1694#
1695# CONFIG_CRYPTO_CCM is not set
1696# CONFIG_CRYPTO_GCM is not set
1697# CONFIG_CRYPTO_SEQIV is not set
1698
1699#
1700# Block modes
1701#
1702# CONFIG_CRYPTO_CBC is not set
1703# CONFIG_CRYPTO_CTR is not set
1704# CONFIG_CRYPTO_CTS is not set
1705# CONFIG_CRYPTO_ECB is not set
1706# CONFIG_CRYPTO_LRW is not set
1707# CONFIG_CRYPTO_PCBC is not set
1708# CONFIG_CRYPTO_XTS is not set
1709
1710#
1711# Hash modes
1712#
1713# CONFIG_CRYPTO_HMAC is not set
1714# CONFIG_CRYPTO_XCBC is not set
1715
1716#
1717# Digest
1718#
1719# CONFIG_CRYPTO_CRC32C is not set
1720# CONFIG_CRYPTO_MD4 is not set
1721# CONFIG_CRYPTO_MD5 is not set
1722# CONFIG_CRYPTO_MICHAEL_MIC is not set
1723# CONFIG_CRYPTO_RMD128 is not set
1724# CONFIG_CRYPTO_RMD160 is not set
1725# CONFIG_CRYPTO_RMD256 is not set
1726# CONFIG_CRYPTO_RMD320 is not set
1727# CONFIG_CRYPTO_SHA1 is not set
1728# CONFIG_CRYPTO_SHA256 is not set
1729# CONFIG_CRYPTO_SHA512 is not set
1730# CONFIG_CRYPTO_TGR192 is not set
1731# CONFIG_CRYPTO_WP512 is not set
1732
1733#
1734# Ciphers
1735#
1736# CONFIG_CRYPTO_AES is not set
1737# CONFIG_CRYPTO_ANUBIS is not set
1738# CONFIG_CRYPTO_ARC4 is not set
1739# CONFIG_CRYPTO_BLOWFISH is not set
1740# CONFIG_CRYPTO_CAMELLIA is not set
1741# CONFIG_CRYPTO_CAST5 is not set
1742# CONFIG_CRYPTO_CAST6 is not set
1743# CONFIG_CRYPTO_DES is not set
1744# CONFIG_CRYPTO_FCRYPT is not set
1745# CONFIG_CRYPTO_KHAZAD is not set
1746# CONFIG_CRYPTO_SALSA20 is not set
1747# CONFIG_CRYPTO_SEED is not set
1748# CONFIG_CRYPTO_SERPENT is not set
1749# CONFIG_CRYPTO_TEA is not set
1750# CONFIG_CRYPTO_TWOFISH is not set
1751
1752#
1753# Compression
1754#
1755# CONFIG_CRYPTO_DEFLATE is not set
1756# CONFIG_CRYPTO_ZLIB is not set
1757# CONFIG_CRYPTO_LZO is not set
1758
1759#
1760# Random Number Generation
1761#
1762# CONFIG_CRYPTO_ANSI_CPRNG is not set
1763# CONFIG_CRYPTO_HW is not set
1764# CONFIG_BINARY_PRINTF is not set
1765
1766#
1767# Library routines
1768#
1769CONFIG_BITREVERSE=y
1770CONFIG_GENERIC_FIND_LAST_BIT=y
1771CONFIG_CRC_CCITT=m
1772# CONFIG_CRC16 is not set
1773CONFIG_CRC_T10DIF=m
1774# CONFIG_CRC_ITU_T is not set
1775CONFIG_CRC32=y
1776# CONFIG_CRC7 is not set
1777# CONFIG_LIBCRC32C is not set
1778CONFIG_ZLIB_INFLATE=y
1779CONFIG_ZLIB_DEFLATE=m
1780CONFIG_DECOMPRESS_GZIP=y
1781CONFIG_HAS_IOMEM=y
1782CONFIG_HAS_IOPORT=y
1783CONFIG_HAS_DMA=y
1784CONFIG_NLATTR=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index c367ae44012e..dcf8153a947d 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29-rc5 3# Linux kernel version: 2.6.30-rc4
4# Tue Mar 3 21:45:57 2009 4# Mon May 4 11:58:57 2009
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -66,20 +66,20 @@ CONFIG_NAMESPACES=y
66# CONFIG_BLK_DEV_INITRD is not set 66# CONFIG_BLK_DEV_INITRD is not set
67CONFIG_CC_OPTIMIZE_FOR_SIZE=y 67CONFIG_CC_OPTIMIZE_FOR_SIZE=y
68CONFIG_SYSCTL=y 68CONFIG_SYSCTL=y
69CONFIG_ANON_INODES=y
69# CONFIG_EMBEDDED is not set 70# CONFIG_EMBEDDED is not set
70CONFIG_UID16=y 71CONFIG_UID16=y
71CONFIG_SYSCTL_SYSCALL=y 72CONFIG_SYSCTL_SYSCALL=y
72CONFIG_KALLSYMS=y 73CONFIG_KALLSYMS=y
73# CONFIG_KALLSYMS_ALL is not set 74# CONFIG_KALLSYMS_ALL is not set
74# CONFIG_KALLSYMS_EXTRA_PASS is not set 75# CONFIG_KALLSYMS_EXTRA_PASS is not set
76# CONFIG_STRIP_ASM_SYMS is not set
75CONFIG_HOTPLUG=y 77CONFIG_HOTPLUG=y
76CONFIG_PRINTK=y 78CONFIG_PRINTK=y
77CONFIG_BUG=y 79CONFIG_BUG=y
78CONFIG_ELF_CORE=y 80CONFIG_ELF_CORE=y
79CONFIG_COMPAT_BRK=y
80CONFIG_BASE_FULL=y 81CONFIG_BASE_FULL=y
81CONFIG_FUTEX=y 82CONFIG_FUTEX=y
82CONFIG_ANON_INODES=y
83CONFIG_EPOLL=y 83CONFIG_EPOLL=y
84CONFIG_SIGNALFD=y 84CONFIG_SIGNALFD=y
85CONFIG_TIMERFD=y 85CONFIG_TIMERFD=y
@@ -89,6 +89,7 @@ CONFIG_AIO=y
89CONFIG_VM_EVENT_COUNTERS=y 89CONFIG_VM_EVENT_COUNTERS=y
90CONFIG_PCI_QUIRKS=y 90CONFIG_PCI_QUIRKS=y
91CONFIG_SLUB_DEBUG=y 91CONFIG_SLUB_DEBUG=y
92CONFIG_COMPAT_BRK=y
92# CONFIG_SLAB is not set 93# CONFIG_SLAB is not set
93CONFIG_SLUB=y 94CONFIG_SLUB=y
94# CONFIG_SLOB is not set 95# CONFIG_SLOB is not set
@@ -101,6 +102,7 @@ CONFIG_KPROBES=y
101CONFIG_KRETPROBES=y 102CONFIG_KRETPROBES=y
102CONFIG_HAVE_KPROBES=y 103CONFIG_HAVE_KPROBES=y
103CONFIG_HAVE_KRETPROBES=y 104CONFIG_HAVE_KRETPROBES=y
105# CONFIG_SLOW_WORK is not set
104CONFIG_HAVE_GENERIC_DMA_COHERENT=y 106CONFIG_HAVE_GENERIC_DMA_COHERENT=y
105CONFIG_SLABINFO=y 107CONFIG_SLABINFO=y
106CONFIG_RT_MUTEXES=y 108CONFIG_RT_MUTEXES=y
@@ -113,7 +115,6 @@ CONFIG_MODULE_UNLOAD=y
113# CONFIG_MODULE_SRCVERSION_ALL is not set 115# CONFIG_MODULE_SRCVERSION_ALL is not set
114CONFIG_BLOCK=y 116CONFIG_BLOCK=y
115# CONFIG_LBD is not set 117# CONFIG_LBD is not set
116# CONFIG_BLK_DEV_IO_TRACE is not set
117# CONFIG_BLK_DEV_BSG is not set 118# CONFIG_BLK_DEV_BSG is not set
118# CONFIG_BLK_DEV_INTEGRITY is not set 119# CONFIG_BLK_DEV_INTEGRITY is not set
119 120
@@ -142,6 +143,7 @@ CONFIG_DEFAULT_IOSCHED="cfq"
142# CONFIG_ARCH_CLPS711X is not set 143# CONFIG_ARCH_CLPS711X is not set
143# CONFIG_ARCH_EBSA110 is not set 144# CONFIG_ARCH_EBSA110 is not set
144# CONFIG_ARCH_EP93XX is not set 145# CONFIG_ARCH_EP93XX is not set
146# CONFIG_ARCH_GEMINI is not set
145# CONFIG_ARCH_FOOTBRIDGE is not set 147# CONFIG_ARCH_FOOTBRIDGE is not set
146# CONFIG_ARCH_NETX is not set 148# CONFIG_ARCH_NETX is not set
147# CONFIG_ARCH_H720X is not set 149# CONFIG_ARCH_H720X is not set
@@ -162,6 +164,7 @@ CONFIG_ARCH_KIRKWOOD=y
162# CONFIG_ARCH_ORION5X is not set 164# CONFIG_ARCH_ORION5X is not set
163# CONFIG_ARCH_PNX4008 is not set 165# CONFIG_ARCH_PNX4008 is not set
164# CONFIG_ARCH_PXA is not set 166# CONFIG_ARCH_PXA is not set
167# CONFIG_ARCH_MMP is not set
165# CONFIG_ARCH_RPC is not set 168# CONFIG_ARCH_RPC is not set
166# CONFIG_ARCH_SA1100 is not set 169# CONFIG_ARCH_SA1100 is not set
167# CONFIG_ARCH_S3C2410 is not set 170# CONFIG_ARCH_S3C2410 is not set
@@ -217,6 +220,7 @@ CONFIG_PCI_SYSCALL=y
217CONFIG_PCI_LEGACY=y 220CONFIG_PCI_LEGACY=y
218# CONFIG_PCI_DEBUG is not set 221# CONFIG_PCI_DEBUG is not set
219# CONFIG_PCI_STUB is not set 222# CONFIG_PCI_STUB is not set
223# CONFIG_PCI_IOV is not set
220# CONFIG_PCCARD is not set 224# CONFIG_PCCARD is not set
221 225
222# 226#
@@ -237,6 +241,7 @@ CONFIG_AEABI=y
237CONFIG_ARCH_FLATMEM_HAS_HOLES=y 241CONFIG_ARCH_FLATMEM_HAS_HOLES=y
238# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set 242# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
239# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set 243# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
244# CONFIG_HIGHMEM is not set
240CONFIG_SELECT_MEMORY_MODEL=y 245CONFIG_SELECT_MEMORY_MODEL=y
241CONFIG_FLATMEM_MANUAL=y 246CONFIG_FLATMEM_MANUAL=y
242# CONFIG_DISCONTIGMEM_MANUAL is not set 247# CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -249,6 +254,8 @@ CONFIG_SPLIT_PTLOCK_CPUS=4096
249CONFIG_ZONE_DMA_FLAG=0 254CONFIG_ZONE_DMA_FLAG=0
250CONFIG_VIRT_TO_BUS=y 255CONFIG_VIRT_TO_BUS=y
251CONFIG_UNEVICTABLE_LRU=y 256CONFIG_UNEVICTABLE_LRU=y
257CONFIG_HAVE_MLOCK=y
258CONFIG_HAVE_MLOCKED_PAGE_BIT=y
252CONFIG_ALIGNMENT_TRAP=y 259CONFIG_ALIGNMENT_TRAP=y
253 260
254# 261#
@@ -293,7 +300,6 @@ CONFIG_NET=y
293# 300#
294# Networking options 301# Networking options
295# 302#
296CONFIG_COMPAT_NET_DEV_OPS=y
297CONFIG_PACKET=y 303CONFIG_PACKET=y
298CONFIG_PACKET_MMAP=y 304CONFIG_PACKET_MMAP=y
299CONFIG_UNIX=y 305CONFIG_UNIX=y
@@ -324,7 +330,7 @@ CONFIG_IP_PNP_BOOTP=y
324CONFIG_INET_XFRM_MODE_TRANSPORT=y 330CONFIG_INET_XFRM_MODE_TRANSPORT=y
325CONFIG_INET_XFRM_MODE_TUNNEL=y 331CONFIG_INET_XFRM_MODE_TUNNEL=y
326CONFIG_INET_XFRM_MODE_BEET=y 332CONFIG_INET_XFRM_MODE_BEET=y
327# CONFIG_INET_LRO is not set 333CONFIG_INET_LRO=y
328CONFIG_INET_DIAG=y 334CONFIG_INET_DIAG=y
329CONFIG_INET_TCP_DIAG=y 335CONFIG_INET_TCP_DIAG=y
330# CONFIG_TCP_CONG_ADVANCED is not set 336# CONFIG_TCP_CONG_ADVANCED is not set
@@ -357,6 +363,7 @@ CONFIG_NET_DSA_MV88E6123_61_65=y
357# CONFIG_LAPB is not set 363# CONFIG_LAPB is not set
358# CONFIG_ECONET is not set 364# CONFIG_ECONET is not set
359# CONFIG_WAN_ROUTER is not set 365# CONFIG_WAN_ROUTER is not set
366# CONFIG_PHONET is not set
360# CONFIG_NET_SCHED is not set 367# CONFIG_NET_SCHED is not set
361# CONFIG_DCB is not set 368# CONFIG_DCB is not set
362 369
@@ -365,20 +372,20 @@ CONFIG_NET_DSA_MV88E6123_61_65=y
365# 372#
366CONFIG_NET_PKTGEN=m 373CONFIG_NET_PKTGEN=m
367# CONFIG_NET_TCPPROBE is not set 374# CONFIG_NET_TCPPROBE is not set
375# CONFIG_NET_DROP_MONITOR is not set
368# CONFIG_HAMRADIO is not set 376# CONFIG_HAMRADIO is not set
369# CONFIG_CAN is not set 377# CONFIG_CAN is not set
370# CONFIG_IRDA is not set 378# CONFIG_IRDA is not set
371# CONFIG_BT is not set 379# CONFIG_BT is not set
372# CONFIG_AF_RXRPC is not set 380# CONFIG_AF_RXRPC is not set
373# CONFIG_PHONET is not set
374CONFIG_WIRELESS=y 381CONFIG_WIRELESS=y
375CONFIG_CFG80211=y 382CONFIG_CFG80211=y
376# CONFIG_CFG80211_REG_DEBUG is not set 383# CONFIG_CFG80211_REG_DEBUG is not set
377# CONFIG_NL80211 is not set
378CONFIG_WIRELESS_OLD_REGULATORY=y 384CONFIG_WIRELESS_OLD_REGULATORY=y
379CONFIG_WIRELESS_EXT=y 385CONFIG_WIRELESS_EXT=y
380CONFIG_WIRELESS_EXT_SYSFS=y 386CONFIG_WIRELESS_EXT_SYSFS=y
381CONFIG_LIB80211=y 387CONFIG_LIB80211=y
388# CONFIG_LIB80211_DEBUG is not set
382CONFIG_MAC80211=y 389CONFIG_MAC80211=y
383 390
384# 391#
@@ -513,7 +520,6 @@ CONFIG_MTD_NAND_ORION=y
513# LPDDR flash memory drivers 520# LPDDR flash memory drivers
514# 521#
515# CONFIG_MTD_LPDDR is not set 522# CONFIG_MTD_LPDDR is not set
516# CONFIG_MTD_QINFO_PROBE is not set
517 523
518# 524#
519# UBI - Unsorted block images 525# UBI - Unsorted block images
@@ -592,8 +598,10 @@ CONFIG_SCSI_LOWLEVEL=y
592# CONFIG_MEGARAID_NEWGEN is not set 598# CONFIG_MEGARAID_NEWGEN is not set
593# CONFIG_MEGARAID_LEGACY is not set 599# CONFIG_MEGARAID_LEGACY is not set
594# CONFIG_MEGARAID_SAS is not set 600# CONFIG_MEGARAID_SAS is not set
601# CONFIG_SCSI_MPT2SAS is not set
595# CONFIG_SCSI_HPTIOP is not set 602# CONFIG_SCSI_HPTIOP is not set
596# CONFIG_LIBFC is not set 603# CONFIG_LIBFC is not set
604# CONFIG_LIBFCOE is not set
597# CONFIG_FCOE is not set 605# CONFIG_FCOE is not set
598# CONFIG_SCSI_DMX3191D is not set 606# CONFIG_SCSI_DMX3191D is not set
599# CONFIG_SCSI_FUTURE_DOMAIN is not set 607# CONFIG_SCSI_FUTURE_DOMAIN is not set
@@ -614,6 +622,7 @@ CONFIG_SCSI_LOWLEVEL=y
614# CONFIG_SCSI_DEBUG is not set 622# CONFIG_SCSI_DEBUG is not set
615# CONFIG_SCSI_SRP is not set 623# CONFIG_SCSI_SRP is not set
616# CONFIG_SCSI_DH is not set 624# CONFIG_SCSI_DH is not set
625# CONFIG_SCSI_OSD_INITIATOR is not set
617CONFIG_ATA=y 626CONFIG_ATA=y
618# CONFIG_ATA_NONSTANDARD is not set 627# CONFIG_ATA_NONSTANDARD is not set
619CONFIG_SATA_PMP=y 628CONFIG_SATA_PMP=y
@@ -687,6 +696,7 @@ CONFIG_SATA_MV=y
687# CONFIG_IEEE1394 is not set 696# CONFIG_IEEE1394 is not set
688# CONFIG_I2O is not set 697# CONFIG_I2O is not set
689CONFIG_NETDEVICES=y 698CONFIG_NETDEVICES=y
699CONFIG_COMPAT_NET_DEV_OPS=y
690# CONFIG_DUMMY is not set 700# CONFIG_DUMMY is not set
691# CONFIG_BONDING is not set 701# CONFIG_BONDING is not set
692# CONFIG_MACVLAN is not set 702# CONFIG_MACVLAN is not set
@@ -724,8 +734,10 @@ CONFIG_MII=y
724# CONFIG_SMC91X is not set 734# CONFIG_SMC91X is not set
725# CONFIG_DM9000 is not set 735# CONFIG_DM9000 is not set
726# CONFIG_ENC28J60 is not set 736# CONFIG_ENC28J60 is not set
737# CONFIG_ETHOC is not set
727# CONFIG_SMC911X is not set 738# CONFIG_SMC911X is not set
728# CONFIG_SMSC911X is not set 739# CONFIG_SMSC911X is not set
740# CONFIG_DNET is not set
729# CONFIG_NET_TULIP is not set 741# CONFIG_NET_TULIP is not set
730# CONFIG_HP100 is not set 742# CONFIG_HP100 is not set
731# CONFIG_IBM_NEW_EMAC_ZMII is not set 743# CONFIG_IBM_NEW_EMAC_ZMII is not set
@@ -763,6 +775,7 @@ CONFIG_NETDEV_1000=y
763# CONFIG_E1000E is not set 775# CONFIG_E1000E is not set
764# CONFIG_IP1000 is not set 776# CONFIG_IP1000 is not set
765# CONFIG_IGB is not set 777# CONFIG_IGB is not set
778# CONFIG_IGBVF is not set
766# CONFIG_NS83820 is not set 779# CONFIG_NS83820 is not set
767# CONFIG_HAMACHI is not set 780# CONFIG_HAMACHI is not set
768# CONFIG_YELLOWFIN is not set 781# CONFIG_YELLOWFIN is not set
@@ -777,6 +790,7 @@ CONFIG_MV643XX_ETH=y
777# CONFIG_QLA3XXX is not set 790# CONFIG_QLA3XXX is not set
778# CONFIG_ATL1 is not set 791# CONFIG_ATL1 is not set
779# CONFIG_ATL1E is not set 792# CONFIG_ATL1E is not set
793# CONFIG_ATL1C is not set
780# CONFIG_JME is not set 794# CONFIG_JME is not set
781# CONFIG_NETDEV_10000 is not set 795# CONFIG_NETDEV_10000 is not set
782# CONFIG_TR is not set 796# CONFIG_TR is not set
@@ -789,10 +803,11 @@ CONFIG_WLAN_80211=y
789CONFIG_LIBERTAS=y 803CONFIG_LIBERTAS=y
790# CONFIG_LIBERTAS_USB is not set 804# CONFIG_LIBERTAS_USB is not set
791CONFIG_LIBERTAS_SDIO=y 805CONFIG_LIBERTAS_SDIO=y
806# CONFIG_LIBERTAS_SPI is not set
792# CONFIG_LIBERTAS_DEBUG is not set 807# CONFIG_LIBERTAS_DEBUG is not set
793# CONFIG_LIBERTAS_THINFIRM is not set 808# CONFIG_LIBERTAS_THINFIRM is not set
794# CONFIG_HERMES is not set
795# CONFIG_ATMEL is not set 809# CONFIG_ATMEL is not set
810# CONFIG_AT76C50X_USB is not set
796# CONFIG_PRISM54 is not set 811# CONFIG_PRISM54 is not set
797# CONFIG_USB_ZD1201 is not set 812# CONFIG_USB_ZD1201 is not set
798# CONFIG_USB_NET_RNDIS_WLAN is not set 813# CONFIG_USB_NET_RNDIS_WLAN is not set
@@ -800,20 +815,20 @@ CONFIG_LIBERTAS_SDIO=y
800# CONFIG_RTL8187 is not set 815# CONFIG_RTL8187 is not set
801# CONFIG_ADM8211 is not set 816# CONFIG_ADM8211 is not set
802# CONFIG_MAC80211_HWSIM is not set 817# CONFIG_MAC80211_HWSIM is not set
818# CONFIG_MWL8K is not set
803# CONFIG_P54_COMMON is not set 819# CONFIG_P54_COMMON is not set
804# CONFIG_ATH5K is not set 820# CONFIG_ATH5K is not set
805# CONFIG_ATH9K is not set 821# CONFIG_ATH9K is not set
822# CONFIG_AR9170_USB is not set
806# CONFIG_IPW2100 is not set 823# CONFIG_IPW2100 is not set
807# CONFIG_IPW2200 is not set 824# CONFIG_IPW2200 is not set
808# CONFIG_IWLCORE is not set 825# CONFIG_IWLWIFI is not set
809# CONFIG_IWLWIFI_LEDS is not set
810# CONFIG_IWLAGN is not set
811# CONFIG_IWL3945 is not set
812# CONFIG_HOSTAP is not set 826# CONFIG_HOSTAP is not set
813# CONFIG_B43 is not set 827# CONFIG_B43 is not set
814# CONFIG_B43LEGACY is not set 828# CONFIG_B43LEGACY is not set
815# CONFIG_ZD1211RW is not set 829# CONFIG_ZD1211RW is not set
816# CONFIG_RT2X00 is not set 830# CONFIG_RT2X00 is not set
831# CONFIG_HERMES is not set
817 832
818# 833#
819# Enable WiMAX (Networking options) to see the WiMAX drivers 834# Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -908,6 +923,7 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=2
908# 923#
909# Non-8250 serial port support 924# Non-8250 serial port support
910# 925#
926# CONFIG_SERIAL_MAX3100 is not set
911CONFIG_SERIAL_CORE=y 927CONFIG_SERIAL_CORE=y
912CONFIG_SERIAL_CORE_CONSOLE=y 928CONFIG_SERIAL_CORE_CONSOLE=y
913# CONFIG_SERIAL_JSM is not set 929# CONFIG_SERIAL_JSM is not set
@@ -982,7 +998,6 @@ CONFIG_I2C_MV64XXX=y
982# CONFIG_SENSORS_PCF8574 is not set 998# CONFIG_SENSORS_PCF8574 is not set
983# CONFIG_PCF8575 is not set 999# CONFIG_PCF8575 is not set
984# CONFIG_SENSORS_PCA9539 is not set 1000# CONFIG_SENSORS_PCA9539 is not set
985# CONFIG_SENSORS_PCF8591 is not set
986# CONFIG_SENSORS_MAX6875 is not set 1001# CONFIG_SENSORS_MAX6875 is not set
987# CONFIG_SENSORS_TSL2550 is not set 1002# CONFIG_SENSORS_TSL2550 is not set
988# CONFIG_I2C_DEBUG_CORE is not set 1003# CONFIG_I2C_DEBUG_CORE is not set
@@ -1082,15 +1097,17 @@ CONFIG_USB_HID=y
1082# 1097#
1083# Special HID drivers 1098# Special HID drivers
1084# 1099#
1085CONFIG_HID_COMPAT=y
1086CONFIG_HID_A4TECH=y 1100CONFIG_HID_A4TECH=y
1087CONFIG_HID_APPLE=y 1101CONFIG_HID_APPLE=y
1088CONFIG_HID_BELKIN=y 1102CONFIG_HID_BELKIN=y
1089CONFIG_HID_CHERRY=y 1103CONFIG_HID_CHERRY=y
1090CONFIG_HID_CHICONY=y 1104CONFIG_HID_CHICONY=y
1091CONFIG_HID_CYPRESS=y 1105CONFIG_HID_CYPRESS=y
1106# CONFIG_DRAGONRISE_FF is not set
1092CONFIG_HID_EZKEY=y 1107CONFIG_HID_EZKEY=y
1108CONFIG_HID_KYE=y
1093CONFIG_HID_GYRATION=y 1109CONFIG_HID_GYRATION=y
1110CONFIG_HID_KENSINGTON=y
1094CONFIG_HID_LOGITECH=y 1111CONFIG_HID_LOGITECH=y
1095# CONFIG_LOGITECH_FF is not set 1112# CONFIG_LOGITECH_FF is not set
1096# CONFIG_LOGIRUMBLEPAD2_FF is not set 1113# CONFIG_LOGIRUMBLEPAD2_FF is not set
@@ -1152,11 +1169,11 @@ CONFIG_USB_PRINTER=m
1152# CONFIG_USB_TMC is not set 1169# CONFIG_USB_TMC is not set
1153 1170
1154# 1171#
1155# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; 1172# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1156# 1173#
1157 1174
1158# 1175#
1159# see USB_STORAGE Help for more information 1176# also be needed; see USB_STORAGE Help for more info
1160# 1177#
1161CONFIG_USB_STORAGE=y 1178CONFIG_USB_STORAGE=y
1162# CONFIG_USB_STORAGE_DEBUG is not set 1179# CONFIG_USB_STORAGE_DEBUG is not set
@@ -1198,7 +1215,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1198# CONFIG_USB_LED is not set 1215# CONFIG_USB_LED is not set
1199# CONFIG_USB_CYPRESS_CY7C63 is not set 1216# CONFIG_USB_CYPRESS_CY7C63 is not set
1200# CONFIG_USB_CYTHERM is not set 1217# CONFIG_USB_CYTHERM is not set
1201# CONFIG_USB_PHIDGET is not set
1202# CONFIG_USB_IDMOUSE is not set 1218# CONFIG_USB_IDMOUSE is not set
1203# CONFIG_USB_FTDI_ELAN is not set 1219# CONFIG_USB_FTDI_ELAN is not set
1204# CONFIG_USB_APPLEDISPLAY is not set 1220# CONFIG_USB_APPLEDISPLAY is not set
@@ -1215,6 +1231,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1215# OTG and related infrastructure 1231# OTG and related infrastructure
1216# 1232#
1217# CONFIG_USB_GPIO_VBUS is not set 1233# CONFIG_USB_GPIO_VBUS is not set
1234# CONFIG_NOP_USB_XCEIV is not set
1218# CONFIG_UWB is not set 1235# CONFIG_UWB is not set
1219CONFIG_MMC=y 1236CONFIG_MMC=y
1220# CONFIG_MMC_DEBUG is not set 1237# CONFIG_MMC_DEBUG is not set
@@ -1245,7 +1262,11 @@ CONFIG_LEDS_CLASS=y
1245# 1262#
1246# CONFIG_LEDS_PCA9532 is not set 1263# CONFIG_LEDS_PCA9532 is not set
1247CONFIG_LEDS_GPIO=y 1264CONFIG_LEDS_GPIO=y
1265CONFIG_LEDS_GPIO_PLATFORM=y
1266# CONFIG_LEDS_LP5521 is not set
1248# CONFIG_LEDS_PCA955X is not set 1267# CONFIG_LEDS_PCA955X is not set
1268# CONFIG_LEDS_DAC124S085 is not set
1269# CONFIG_LEDS_BD2802 is not set
1249 1270
1250# 1271#
1251# LED Triggers 1272# LED Triggers
@@ -1255,6 +1276,10 @@ CONFIG_LEDS_TRIGGER_TIMER=y
1255CONFIG_LEDS_TRIGGER_HEARTBEAT=y 1276CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1256# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set 1277# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
1257CONFIG_LEDS_TRIGGER_DEFAULT_ON=y 1278CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
1279
1280#
1281# iptables trigger is under Netfilter config (LED target)
1282#
1258CONFIG_RTC_LIB=y 1283CONFIG_RTC_LIB=y
1259CONFIG_RTC_CLASS=y 1284CONFIG_RTC_CLASS=y
1260CONFIG_RTC_HCTOSYS=y 1285CONFIG_RTC_HCTOSYS=y
@@ -1329,7 +1354,9 @@ CONFIG_DMA_ENGINE=y
1329# DMA Clients 1354# DMA Clients
1330# 1355#
1331# CONFIG_NET_DMA is not set 1356# CONFIG_NET_DMA is not set
1357# CONFIG_ASYNC_TX_DMA is not set
1332# CONFIG_DMATEST is not set 1358# CONFIG_DMATEST is not set
1359# CONFIG_AUXDISPLAY is not set
1333# CONFIG_REGULATOR is not set 1360# CONFIG_REGULATOR is not set
1334# CONFIG_UIO is not set 1361# CONFIG_UIO is not set
1335# CONFIG_STAGING is not set 1362# CONFIG_STAGING is not set
@@ -1341,6 +1368,7 @@ CONFIG_EXT2_FS=y
1341# CONFIG_EXT2_FS_XATTR is not set 1368# CONFIG_EXT2_FS_XATTR is not set
1342# CONFIG_EXT2_FS_XIP is not set 1369# CONFIG_EXT2_FS_XIP is not set
1343CONFIG_EXT3_FS=y 1370CONFIG_EXT3_FS=y
1371# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1344# CONFIG_EXT3_FS_XATTR is not set 1372# CONFIG_EXT3_FS_XATTR is not set
1345# CONFIG_EXT4_FS is not set 1373# CONFIG_EXT4_FS is not set
1346CONFIG_JBD=y 1374CONFIG_JBD=y
@@ -1361,6 +1389,11 @@ CONFIG_INOTIFY_USER=y
1361# CONFIG_FUSE_FS is not set 1389# CONFIG_FUSE_FS is not set
1362 1390
1363# 1391#
1392# Caches
1393#
1394# CONFIG_FSCACHE is not set
1395
1396#
1364# CD-ROM/DVD Filesystems 1397# CD-ROM/DVD Filesystems
1365# 1398#
1366CONFIG_ISO9660_FS=m 1399CONFIG_ISO9660_FS=m
@@ -1419,6 +1452,7 @@ CONFIG_CRAMFS=y
1419# CONFIG_ROMFS_FS is not set 1452# CONFIG_ROMFS_FS is not set
1420# CONFIG_SYSV_FS is not set 1453# CONFIG_SYSV_FS is not set
1421# CONFIG_UFS_FS is not set 1454# CONFIG_UFS_FS is not set
1455# CONFIG_NILFS2_FS is not set
1422CONFIG_NETWORK_FILESYSTEMS=y 1456CONFIG_NETWORK_FILESYSTEMS=y
1423CONFIG_NFS_FS=y 1457CONFIG_NFS_FS=y
1424CONFIG_NFS_V3=y 1458CONFIG_NFS_V3=y
@@ -1430,7 +1464,6 @@ CONFIG_LOCKD=y
1430CONFIG_LOCKD_V4=y 1464CONFIG_LOCKD_V4=y
1431CONFIG_NFS_COMMON=y 1465CONFIG_NFS_COMMON=y
1432CONFIG_SUNRPC=y 1466CONFIG_SUNRPC=y
1433# CONFIG_SUNRPC_REGISTER_V4 is not set
1434# CONFIG_RPCSEC_GSS_KRB5 is not set 1467# CONFIG_RPCSEC_GSS_KRB5 is not set
1435# CONFIG_RPCSEC_GSS_SPKM3 is not set 1468# CONFIG_RPCSEC_GSS_SPKM3 is not set
1436# CONFIG_SMB_FS is not set 1469# CONFIG_SMB_FS is not set
@@ -1502,6 +1535,9 @@ CONFIG_DEBUG_KERNEL=y
1502CONFIG_DETECT_SOFTLOCKUP=y 1535CONFIG_DETECT_SOFTLOCKUP=y
1503# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set 1536# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1504CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 1537CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1538CONFIG_DETECT_HUNG_TASK=y
1539# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1540CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1505# CONFIG_SCHED_DEBUG is not set 1541# CONFIG_SCHED_DEBUG is not set
1506# CONFIG_SCHEDSTATS is not set 1542# CONFIG_SCHEDSTATS is not set
1507# CONFIG_TIMER_STATS is not set 1543# CONFIG_TIMER_STATS is not set
@@ -1538,10 +1574,12 @@ CONFIG_DEBUG_MEMORY_INIT=y
1538# CONFIG_FAULT_INJECTION is not set 1574# CONFIG_FAULT_INJECTION is not set
1539# CONFIG_LATENCYTOP is not set 1575# CONFIG_LATENCYTOP is not set
1540CONFIG_SYSCTL_SYSCALL_CHECK=y 1576CONFIG_SYSCTL_SYSCALL_CHECK=y
1577# CONFIG_PAGE_POISONING is not set
1541CONFIG_NOP_TRACER=y 1578CONFIG_NOP_TRACER=y
1542CONFIG_HAVE_FUNCTION_TRACER=y 1579CONFIG_HAVE_FUNCTION_TRACER=y
1543CONFIG_RING_BUFFER=y 1580CONFIG_RING_BUFFER=y
1544CONFIG_TRACING=y 1581CONFIG_TRACING=y
1582CONFIG_TRACING_SUPPORT=y
1545 1583
1546# 1584#
1547# Tracers 1585# Tracers
@@ -1551,11 +1589,15 @@ CONFIG_TRACING=y
1551# CONFIG_PREEMPT_TRACER is not set 1589# CONFIG_PREEMPT_TRACER is not set
1552# CONFIG_SCHED_TRACER is not set 1590# CONFIG_SCHED_TRACER is not set
1553# CONFIG_CONTEXT_SWITCH_TRACER is not set 1591# CONFIG_CONTEXT_SWITCH_TRACER is not set
1592# CONFIG_EVENT_TRACER is not set
1554# CONFIG_BOOT_TRACER is not set 1593# CONFIG_BOOT_TRACER is not set
1555# CONFIG_TRACE_BRANCH_PROFILING is not set 1594# CONFIG_TRACE_BRANCH_PROFILING is not set
1556# CONFIG_STACK_TRACER is not set 1595# CONFIG_STACK_TRACER is not set
1596# CONFIG_KMEMTRACE is not set
1597# CONFIG_WORKQUEUE_TRACER is not set
1598# CONFIG_BLK_DEV_IO_TRACE is not set
1557# CONFIG_FTRACE_STARTUP_TEST is not set 1599# CONFIG_FTRACE_STARTUP_TEST is not set
1558# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 1600# CONFIG_DYNAMIC_DEBUG is not set
1559# CONFIG_SAMPLES is not set 1601# CONFIG_SAMPLES is not set
1560CONFIG_HAVE_ARCH_KGDB=y 1602CONFIG_HAVE_ARCH_KGDB=y
1561# CONFIG_KGDB is not set 1603# CONFIG_KGDB is not set
@@ -1587,10 +1629,12 @@ CONFIG_CRYPTO_BLKCIPHER2=y
1587CONFIG_CRYPTO_HASH=y 1629CONFIG_CRYPTO_HASH=y
1588CONFIG_CRYPTO_HASH2=y 1630CONFIG_CRYPTO_HASH2=y
1589CONFIG_CRYPTO_RNG2=y 1631CONFIG_CRYPTO_RNG2=y
1632CONFIG_CRYPTO_PCOMP=y
1590CONFIG_CRYPTO_MANAGER=y 1633CONFIG_CRYPTO_MANAGER=y
1591CONFIG_CRYPTO_MANAGER2=y 1634CONFIG_CRYPTO_MANAGER2=y
1592# CONFIG_CRYPTO_GF128MUL is not set 1635# CONFIG_CRYPTO_GF128MUL is not set
1593# CONFIG_CRYPTO_NULL is not set 1636# CONFIG_CRYPTO_NULL is not set
1637CONFIG_CRYPTO_WORKQUEUE=y
1594# CONFIG_CRYPTO_CRYPTD is not set 1638# CONFIG_CRYPTO_CRYPTD is not set
1595# CONFIG_CRYPTO_AUTHENC is not set 1639# CONFIG_CRYPTO_AUTHENC is not set
1596# CONFIG_CRYPTO_TEST is not set 1640# CONFIG_CRYPTO_TEST is not set
@@ -1659,6 +1703,7 @@ CONFIG_CRYPTO_ARC4=y
1659# Compression 1703# Compression
1660# 1704#
1661# CONFIG_CRYPTO_DEFLATE is not set 1705# CONFIG_CRYPTO_DEFLATE is not set
1706# CONFIG_CRYPTO_ZLIB is not set
1662# CONFIG_CRYPTO_LZO is not set 1707# CONFIG_CRYPTO_LZO is not set
1663 1708
1664# 1709#
@@ -1667,6 +1712,7 @@ CONFIG_CRYPTO_ARC4=y
1667# CONFIG_CRYPTO_ANSI_CPRNG is not set 1712# CONFIG_CRYPTO_ANSI_CPRNG is not set
1668CONFIG_CRYPTO_HW=y 1713CONFIG_CRYPTO_HW=y
1669# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1714# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1715CONFIG_BINARY_PRINTF=y
1670 1716
1671# 1717#
1672# Library routines 1718# Library routines
@@ -1682,7 +1728,7 @@ CONFIG_CRC32=y
1682CONFIG_LIBCRC32C=y 1728CONFIG_LIBCRC32C=y
1683CONFIG_ZLIB_INFLATE=y 1729CONFIG_ZLIB_INFLATE=y
1684CONFIG_ZLIB_DEFLATE=y 1730CONFIG_ZLIB_DEFLATE=y
1685CONFIG_PLIST=y
1686CONFIG_HAS_IOMEM=y 1731CONFIG_HAS_IOMEM=y
1687CONFIG_HAS_IOPORT=y 1732CONFIG_HAS_IOPORT=y
1688CONFIG_HAS_DMA=y 1733CONFIG_HAS_DMA=y
1734CONFIG_NLATTR=y
diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig
index b0698722e0cb..398274b0771a 100644
--- a/arch/arm/configs/mv78xx0_defconfig
+++ b/arch/arm/configs/mv78xx0_defconfig
@@ -1,11 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5 3# Linux kernel version: 2.6.30-rc4
4# Fri Jun 13 02:57:32 2008 4# Mon May 4 14:22:12 2009
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8# CONFIG_GENERIC_GPIO is not set 8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y 9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y 10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y 11CONFIG_MMU=y
@@ -22,8 +22,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
22# CONFIG_ARCH_HAS_ILOG2_U64 is not set 22# CONFIG_ARCH_HAS_ILOG2_U64 is not set
23CONFIG_GENERIC_HWEIGHT=y 23CONFIG_GENERIC_HWEIGHT=y
24CONFIG_GENERIC_CALIBRATE_DELAY=y 24CONFIG_GENERIC_CALIBRATE_DELAY=y
25CONFIG_ARCH_SUPPORTS_AOUT=y 25CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
26CONFIG_ZONE_DMA=y
27CONFIG_VECTORS_BASE=0xffff0000 26CONFIG_VECTORS_BASE=0xffff0000
28CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
29 28
@@ -43,10 +42,19 @@ CONFIG_SYSVIPC_SYSCTL=y
43# CONFIG_BSD_PROCESS_ACCT is not set 42# CONFIG_BSD_PROCESS_ACCT is not set
44# CONFIG_TASKSTATS is not set 43# CONFIG_TASKSTATS is not set
45# CONFIG_AUDIT is not set 44# CONFIG_AUDIT is not set
45
46#
47# RCU Subsystem
48#
49CONFIG_CLASSIC_RCU=y
50# CONFIG_TREE_RCU is not set
51# CONFIG_PREEMPT_RCU is not set
52# CONFIG_TREE_RCU_TRACE is not set
53# CONFIG_PREEMPT_RCU_TRACE is not set
46# CONFIG_IKCONFIG is not set 54# CONFIG_IKCONFIG is not set
47CONFIG_LOG_BUF_SHIFT=14 55CONFIG_LOG_BUF_SHIFT=14
48# CONFIG_CGROUPS is not set
49# CONFIG_GROUP_SCHED is not set 56# CONFIG_GROUP_SCHED is not set
57# CONFIG_CGROUPS is not set
50CONFIG_SYSFS_DEPRECATED=y 58CONFIG_SYSFS_DEPRECATED=y
51CONFIG_SYSFS_DEPRECATED_V2=y 59CONFIG_SYSFS_DEPRECATED_V2=y
52# CONFIG_RELAY is not set 60# CONFIG_RELAY is not set
@@ -54,32 +62,35 @@ CONFIG_SYSFS_DEPRECATED_V2=y
54# CONFIG_BLK_DEV_INITRD is not set 62# CONFIG_BLK_DEV_INITRD is not set
55CONFIG_CC_OPTIMIZE_FOR_SIZE=y 63CONFIG_CC_OPTIMIZE_FOR_SIZE=y
56CONFIG_SYSCTL=y 64CONFIG_SYSCTL=y
65CONFIG_ANON_INODES=y
57CONFIG_EMBEDDED=y 66CONFIG_EMBEDDED=y
58CONFIG_UID16=y 67CONFIG_UID16=y
59CONFIG_SYSCTL_SYSCALL=y 68CONFIG_SYSCTL_SYSCALL=y
60CONFIG_SYSCTL_SYSCALL_CHECK=y
61CONFIG_KALLSYMS=y 69CONFIG_KALLSYMS=y
62CONFIG_KALLSYMS_ALL=y 70CONFIG_KALLSYMS_ALL=y
63# CONFIG_KALLSYMS_EXTRA_PASS is not set 71# CONFIG_KALLSYMS_EXTRA_PASS is not set
72# CONFIG_STRIP_ASM_SYMS is not set
64CONFIG_HOTPLUG=y 73CONFIG_HOTPLUG=y
65CONFIG_PRINTK=y 74CONFIG_PRINTK=y
66CONFIG_BUG=y 75CONFIG_BUG=y
67CONFIG_ELF_CORE=y 76CONFIG_ELF_CORE=y
68CONFIG_COMPAT_BRK=y
69CONFIG_BASE_FULL=y 77CONFIG_BASE_FULL=y
70CONFIG_FUTEX=y 78CONFIG_FUTEX=y
71CONFIG_ANON_INODES=y
72CONFIG_EPOLL=y 79CONFIG_EPOLL=y
73CONFIG_SIGNALFD=y 80CONFIG_SIGNALFD=y
74CONFIG_TIMERFD=y 81CONFIG_TIMERFD=y
75CONFIG_EVENTFD=y 82CONFIG_EVENTFD=y
76CONFIG_SHMEM=y 83CONFIG_SHMEM=y
84CONFIG_AIO=y
77CONFIG_VM_EVENT_COUNTERS=y 85CONFIG_VM_EVENT_COUNTERS=y
86CONFIG_PCI_QUIRKS=y
78# CONFIG_SLUB_DEBUG is not set 87# CONFIG_SLUB_DEBUG is not set
88CONFIG_COMPAT_BRK=y
79# CONFIG_SLAB is not set 89# CONFIG_SLAB is not set
80CONFIG_SLUB=y 90CONFIG_SLUB=y
81# CONFIG_SLOB is not set 91# CONFIG_SLOB is not set
82CONFIG_PROFILING=y 92CONFIG_PROFILING=y
93CONFIG_TRACEPOINTS=y
83# CONFIG_MARKERS is not set 94# CONFIG_MARKERS is not set
84CONFIG_OPROFILE=y 95CONFIG_OPROFILE=y
85CONFIG_HAVE_OPROFILE=y 96CONFIG_HAVE_OPROFILE=y
@@ -87,10 +98,9 @@ CONFIG_KPROBES=y
87CONFIG_KRETPROBES=y 98CONFIG_KRETPROBES=y
88CONFIG_HAVE_KPROBES=y 99CONFIG_HAVE_KPROBES=y
89CONFIG_HAVE_KRETPROBES=y 100CONFIG_HAVE_KRETPROBES=y
90# CONFIG_HAVE_DMA_ATTRS is not set 101# CONFIG_SLOW_WORK is not set
91CONFIG_PROC_PAGE_MONITOR=y 102CONFIG_HAVE_GENERIC_DMA_COHERENT=y
92CONFIG_RT_MUTEXES=y 103CONFIG_RT_MUTEXES=y
93# CONFIG_TINY_SHMEM is not set
94CONFIG_BASE_SMALL=0 104CONFIG_BASE_SMALL=0
95CONFIG_MODULES=y 105CONFIG_MODULES=y
96# CONFIG_MODULE_FORCE_LOAD is not set 106# CONFIG_MODULE_FORCE_LOAD is not set
@@ -98,12 +108,10 @@ CONFIG_MODULE_UNLOAD=y
98# CONFIG_MODULE_FORCE_UNLOAD is not set 108# CONFIG_MODULE_FORCE_UNLOAD is not set
99# CONFIG_MODVERSIONS is not set 109# CONFIG_MODVERSIONS is not set
100# CONFIG_MODULE_SRCVERSION_ALL is not set 110# CONFIG_MODULE_SRCVERSION_ALL is not set
101# CONFIG_KMOD is not set
102CONFIG_BLOCK=y 111CONFIG_BLOCK=y
103# CONFIG_LBD is not set 112# CONFIG_LBD is not set
104# CONFIG_BLK_DEV_IO_TRACE is not set
105# CONFIG_LSF is not set
106# CONFIG_BLK_DEV_BSG is not set 113# CONFIG_BLK_DEV_BSG is not set
114# CONFIG_BLK_DEV_INTEGRITY is not set
107 115
108# 116#
109# IO Schedulers 117# IO Schedulers
@@ -117,7 +125,7 @@ CONFIG_IOSCHED_CFQ=y
117CONFIG_DEFAULT_CFQ=y 125CONFIG_DEFAULT_CFQ=y
118# CONFIG_DEFAULT_NOOP is not set 126# CONFIG_DEFAULT_NOOP is not set
119CONFIG_DEFAULT_IOSCHED="cfq" 127CONFIG_DEFAULT_IOSCHED="cfq"
120CONFIG_CLASSIC_RCU=y 128# CONFIG_FREEZER is not set
121 129
122# 130#
123# System Type 131# System Type
@@ -127,11 +135,10 @@ CONFIG_CLASSIC_RCU=y
127# CONFIG_ARCH_REALVIEW is not set 135# CONFIG_ARCH_REALVIEW is not set
128# CONFIG_ARCH_VERSATILE is not set 136# CONFIG_ARCH_VERSATILE is not set
129# CONFIG_ARCH_AT91 is not set 137# CONFIG_ARCH_AT91 is not set
130# CONFIG_ARCH_CLPS7500 is not set
131# CONFIG_ARCH_CLPS711X is not set 138# CONFIG_ARCH_CLPS711X is not set
132# CONFIG_ARCH_CO285 is not set
133# CONFIG_ARCH_EBSA110 is not set 139# CONFIG_ARCH_EBSA110 is not set
134# CONFIG_ARCH_EP93XX is not set 140# CONFIG_ARCH_EP93XX is not set
141# CONFIG_ARCH_GEMINI is not set
135# CONFIG_ARCH_FOOTBRIDGE is not set 142# CONFIG_ARCH_FOOTBRIDGE is not set
136# CONFIG_ARCH_NETX is not set 143# CONFIG_ARCH_NETX is not set
137# CONFIG_ARCH_H720X is not set 144# CONFIG_ARCH_H720X is not set
@@ -152,28 +159,23 @@ CONFIG_ARCH_MV78XX0=y
152# CONFIG_ARCH_ORION5X is not set 159# CONFIG_ARCH_ORION5X is not set
153# CONFIG_ARCH_PNX4008 is not set 160# CONFIG_ARCH_PNX4008 is not set
154# CONFIG_ARCH_PXA is not set 161# CONFIG_ARCH_PXA is not set
162# CONFIG_ARCH_MMP is not set
155# CONFIG_ARCH_RPC is not set 163# CONFIG_ARCH_RPC is not set
156# CONFIG_ARCH_SA1100 is not set 164# CONFIG_ARCH_SA1100 is not set
157# CONFIG_ARCH_S3C2410 is not set 165# CONFIG_ARCH_S3C2410 is not set
166# CONFIG_ARCH_S3C64XX is not set
158# CONFIG_ARCH_SHARK is not set 167# CONFIG_ARCH_SHARK is not set
159# CONFIG_ARCH_LH7A40X is not set 168# CONFIG_ARCH_LH7A40X is not set
160# CONFIG_ARCH_DAVINCI is not set 169# CONFIG_ARCH_DAVINCI is not set
161# CONFIG_ARCH_OMAP is not set 170# CONFIG_ARCH_OMAP is not set
162# CONFIG_ARCH_MSM7X00A is not set 171# CONFIG_ARCH_MSM is not set
172# CONFIG_ARCH_W90X900 is not set
163 173
164# 174#
165# Marvell MV78xx0 Implementations 175# Marvell MV78xx0 Implementations
166# 176#
167CONFIG_MACH_DB78X00_BP=y 177CONFIG_MACH_DB78X00_BP=y
168CONFIG_MACH_RD78X00_MASA=y 178CONFIG_MACH_RD78X00_MASA=y
169
170#
171# Boot options
172#
173
174#
175# Power management
176#
177CONFIG_PLAT_ORION=y 179CONFIG_PLAT_ORION=y
178 180
179# 181#
@@ -199,6 +201,7 @@ CONFIG_ARM_THUMB=y
199# CONFIG_CPU_DCACHE_DISABLE is not set 201# CONFIG_CPU_DCACHE_DISABLE is not set
200CONFIG_OUTER_CACHE=y 202CONFIG_OUTER_CACHE=y
201CONFIG_CACHE_FEROCEON_L2=y 203CONFIG_CACHE_FEROCEON_L2=y
204# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set
202 205
203# 206#
204# Bus support 207# Bus support
@@ -208,6 +211,8 @@ CONFIG_PCI_SYSCALL=y
208# CONFIG_ARCH_SUPPORTS_MSI is not set 211# CONFIG_ARCH_SUPPORTS_MSI is not set
209CONFIG_PCI_LEGACY=y 212CONFIG_PCI_LEGACY=y
210# CONFIG_PCI_DEBUG is not set 213# CONFIG_PCI_DEBUG is not set
214# CONFIG_PCI_STUB is not set
215# CONFIG_PCI_IOV is not set
211# CONFIG_PCCARD is not set 216# CONFIG_PCCARD is not set
212 217
213# 218#
@@ -217,25 +222,33 @@ CONFIG_TICK_ONESHOT=y
217CONFIG_NO_HZ=y 222CONFIG_NO_HZ=y
218CONFIG_HIGH_RES_TIMERS=y 223CONFIG_HIGH_RES_TIMERS=y
219CONFIG_GENERIC_CLOCKEVENTS_BUILD=y 224CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
225CONFIG_VMSPLIT_3G=y
226# CONFIG_VMSPLIT_2G is not set
227# CONFIG_VMSPLIT_1G is not set
228CONFIG_PAGE_OFFSET=0xC0000000
220CONFIG_PREEMPT=y 229CONFIG_PREEMPT=y
221CONFIG_HZ=100 230CONFIG_HZ=100
222CONFIG_AEABI=y 231CONFIG_AEABI=y
223CONFIG_OABI_COMPAT=y 232CONFIG_OABI_COMPAT=y
224# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 233CONFIG_ARCH_FLATMEM_HAS_HOLES=y
234# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
235# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
236CONFIG_HIGHMEM=y
225CONFIG_SELECT_MEMORY_MODEL=y 237CONFIG_SELECT_MEMORY_MODEL=y
226CONFIG_FLATMEM_MANUAL=y 238CONFIG_FLATMEM_MANUAL=y
227# CONFIG_DISCONTIGMEM_MANUAL is not set 239# CONFIG_DISCONTIGMEM_MANUAL is not set
228# CONFIG_SPARSEMEM_MANUAL is not set 240# CONFIG_SPARSEMEM_MANUAL is not set
229CONFIG_FLATMEM=y 241CONFIG_FLATMEM=y
230CONFIG_FLAT_NODE_MEM_MAP=y 242CONFIG_FLAT_NODE_MEM_MAP=y
231# CONFIG_SPARSEMEM_STATIC is not set
232# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
233CONFIG_PAGEFLAGS_EXTENDED=y 243CONFIG_PAGEFLAGS_EXTENDED=y
234CONFIG_SPLIT_PTLOCK_CPUS=4096 244CONFIG_SPLIT_PTLOCK_CPUS=4096
235# CONFIG_RESOURCES_64BIT is not set 245# CONFIG_PHYS_ADDR_T_64BIT is not set
236CONFIG_ZONE_DMA_FLAG=1 246CONFIG_ZONE_DMA_FLAG=0
237CONFIG_BOUNCE=y 247CONFIG_BOUNCE=y
238CONFIG_VIRT_TO_BUS=y 248CONFIG_VIRT_TO_BUS=y
249CONFIG_UNEVICTABLE_LRU=y
250CONFIG_HAVE_MLOCK=y
251CONFIG_HAVE_MLOCKED_PAGE_BIT=y
239CONFIG_ALIGNMENT_TRAP=y 252CONFIG_ALIGNMENT_TRAP=y
240 253
241# 254#
@@ -248,6 +261,11 @@ CONFIG_CMDLINE=""
248# CONFIG_KEXEC is not set 261# CONFIG_KEXEC is not set
249 262
250# 263#
264# CPU Power Management
265#
266# CONFIG_CPU_IDLE is not set
267
268#
251# Floating point emulation 269# Floating point emulation
252# 270#
253 271
@@ -263,6 +281,8 @@ CONFIG_VFP=y
263# Userspace binary formats 281# Userspace binary formats
264# 282#
265CONFIG_BINFMT_ELF=y 283CONFIG_BINFMT_ELF=y
284# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
285CONFIG_HAVE_AOUT=y
266# CONFIG_BINFMT_AOUT is not set 286# CONFIG_BINFMT_AOUT is not set
267# CONFIG_BINFMT_MISC is not set 287# CONFIG_BINFMT_MISC is not set
268 288
@@ -271,10 +291,6 @@ CONFIG_BINFMT_ELF=y
271# 291#
272# CONFIG_PM is not set 292# CONFIG_PM is not set
273CONFIG_ARCH_SUSPEND_POSSIBLE=y 293CONFIG_ARCH_SUSPEND_POSSIBLE=y
274
275#
276# Networking
277#
278CONFIG_NET=y 294CONFIG_NET=y
279 295
280# 296#
@@ -310,7 +326,7 @@ CONFIG_IP_PNP_BOOTP=y
310CONFIG_INET_XFRM_MODE_TRANSPORT=y 326CONFIG_INET_XFRM_MODE_TRANSPORT=y
311CONFIG_INET_XFRM_MODE_TUNNEL=y 327CONFIG_INET_XFRM_MODE_TUNNEL=y
312CONFIG_INET_XFRM_MODE_BEET=y 328CONFIG_INET_XFRM_MODE_BEET=y
313# CONFIG_INET_LRO is not set 329CONFIG_INET_LRO=y
314CONFIG_INET_DIAG=y 330CONFIG_INET_DIAG=y
315CONFIG_INET_TCP_DIAG=y 331CONFIG_INET_TCP_DIAG=y
316# CONFIG_TCP_CONG_ADVANCED is not set 332# CONFIG_TCP_CONG_ADVANCED is not set
@@ -325,6 +341,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
325# CONFIG_TIPC is not set 341# CONFIG_TIPC is not set
326# CONFIG_ATM is not set 342# CONFIG_ATM is not set
327# CONFIG_BRIDGE is not set 343# CONFIG_BRIDGE is not set
344# CONFIG_NET_DSA is not set
328# CONFIG_VLAN_8021Q is not set 345# CONFIG_VLAN_8021Q is not set
329# CONFIG_DECNET is not set 346# CONFIG_DECNET is not set
330# CONFIG_LLC2 is not set 347# CONFIG_LLC2 is not set
@@ -334,26 +351,23 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
334# CONFIG_LAPB is not set 351# CONFIG_LAPB is not set
335# CONFIG_ECONET is not set 352# CONFIG_ECONET is not set
336# CONFIG_WAN_ROUTER is not set 353# CONFIG_WAN_ROUTER is not set
354# CONFIG_PHONET is not set
337# CONFIG_NET_SCHED is not set 355# CONFIG_NET_SCHED is not set
356# CONFIG_DCB is not set
338 357
339# 358#
340# Network testing 359# Network testing
341# 360#
342CONFIG_NET_PKTGEN=m 361CONFIG_NET_PKTGEN=m
343# CONFIG_NET_TCPPROBE is not set 362# CONFIG_NET_TCPPROBE is not set
363# CONFIG_NET_DROP_MONITOR is not set
344# CONFIG_HAMRADIO is not set 364# CONFIG_HAMRADIO is not set
345# CONFIG_CAN is not set 365# CONFIG_CAN is not set
346# CONFIG_IRDA is not set 366# CONFIG_IRDA is not set
347# CONFIG_BT is not set 367# CONFIG_BT is not set
348# CONFIG_AF_RXRPC is not set 368# CONFIG_AF_RXRPC is not set
349 369# CONFIG_WIRELESS is not set
350# 370# CONFIG_WIMAX is not set
351# Wireless
352#
353# CONFIG_CFG80211 is not set
354CONFIG_WIRELESS_EXT=y
355# CONFIG_MAC80211 is not set
356# CONFIG_IEEE80211 is not set
357# CONFIG_RFKILL is not set 371# CONFIG_RFKILL is not set
358# CONFIG_NET_9P is not set 372# CONFIG_NET_9P is not set
359 373
@@ -368,6 +382,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
368CONFIG_STANDALONE=y 382CONFIG_STANDALONE=y
369CONFIG_PREVENT_FIRMWARE_BUILD=y 383CONFIG_PREVENT_FIRMWARE_BUILD=y
370CONFIG_FW_LOADER=y 384CONFIG_FW_LOADER=y
385# CONFIG_FIRMWARE_IN_KERNEL is not set
386CONFIG_EXTRA_FIRMWARE=""
371# CONFIG_DEBUG_DRIVER is not set 387# CONFIG_DEBUG_DRIVER is not set
372# CONFIG_DEBUG_DEVRES is not set 388# CONFIG_DEBUG_DEVRES is not set
373# CONFIG_SYS_HYPERVISOR is not set 389# CONFIG_SYS_HYPERVISOR is not set
@@ -376,6 +392,7 @@ CONFIG_MTD=y
376# CONFIG_MTD_DEBUG is not set 392# CONFIG_MTD_DEBUG is not set
377# CONFIG_MTD_CONCAT is not set 393# CONFIG_MTD_CONCAT is not set
378CONFIG_MTD_PARTITIONS=y 394CONFIG_MTD_PARTITIONS=y
395# CONFIG_MTD_TESTS is not set
379# CONFIG_MTD_REDBOOT_PARTS is not set 396# CONFIG_MTD_REDBOOT_PARTS is not set
380CONFIG_MTD_CMDLINE_PARTS=y 397CONFIG_MTD_CMDLINE_PARTS=y
381# CONFIG_MTD_AFS_PARTS is not set 398# CONFIG_MTD_AFS_PARTS is not set
@@ -429,9 +446,7 @@ CONFIG_MTD_CFI_UTIL=y
429# 446#
430# CONFIG_MTD_COMPLEX_MAPPINGS is not set 447# CONFIG_MTD_COMPLEX_MAPPINGS is not set
431CONFIG_MTD_PHYSMAP=y 448CONFIG_MTD_PHYSMAP=y
432CONFIG_MTD_PHYSMAP_START=0x0 449# CONFIG_MTD_PHYSMAP_COMPAT is not set
433CONFIG_MTD_PHYSMAP_LEN=0x0
434CONFIG_MTD_PHYSMAP_BANKWIDTH=0
435# CONFIG_MTD_ARM_INTEGRATOR is not set 450# CONFIG_MTD_ARM_INTEGRATOR is not set
436# CONFIG_MTD_IMPA7 is not set 451# CONFIG_MTD_IMPA7 is not set
437# CONFIG_MTD_INTEL_VR_NOR is not set 452# CONFIG_MTD_INTEL_VR_NOR is not set
@@ -456,6 +471,7 @@ CONFIG_MTD_NAND=y
456CONFIG_MTD_NAND_VERIFY_WRITE=y 471CONFIG_MTD_NAND_VERIFY_WRITE=y
457# CONFIG_MTD_NAND_ECC_SMC is not set 472# CONFIG_MTD_NAND_ECC_SMC is not set
458# CONFIG_MTD_NAND_MUSEUM_IDS is not set 473# CONFIG_MTD_NAND_MUSEUM_IDS is not set
474# CONFIG_MTD_NAND_GPIO is not set
459CONFIG_MTD_NAND_IDS=y 475CONFIG_MTD_NAND_IDS=y
460# CONFIG_MTD_NAND_DISKONCHIP is not set 476# CONFIG_MTD_NAND_DISKONCHIP is not set
461# CONFIG_MTD_NAND_CAFE is not set 477# CONFIG_MTD_NAND_CAFE is not set
@@ -466,6 +482,11 @@ CONFIG_MTD_NAND_ORION=y
466# CONFIG_MTD_ONENAND is not set 482# CONFIG_MTD_ONENAND is not set
467 483
468# 484#
485# LPDDR flash memory drivers
486#
487# CONFIG_MTD_LPDDR is not set
488
489#
469# UBI - Unsorted block images 490# UBI - Unsorted block images
470# 491#
471# CONFIG_MTD_UBI is not set 492# CONFIG_MTD_UBI is not set
@@ -486,10 +507,20 @@ CONFIG_BLK_DEV_LOOP=y
486# CONFIG_ATA_OVER_ETH is not set 507# CONFIG_ATA_OVER_ETH is not set
487CONFIG_MISC_DEVICES=y 508CONFIG_MISC_DEVICES=y
488# CONFIG_PHANTOM is not set 509# CONFIG_PHANTOM is not set
489# CONFIG_EEPROM_93CX6 is not set
490# CONFIG_SGI_IOC4 is not set 510# CONFIG_SGI_IOC4 is not set
491# CONFIG_TIFM_CORE is not set 511# CONFIG_TIFM_CORE is not set
512# CONFIG_ICS932S401 is not set
492# CONFIG_ENCLOSURE_SERVICES is not set 513# CONFIG_ENCLOSURE_SERVICES is not set
514# CONFIG_HP_ILO is not set
515# CONFIG_ISL29003 is not set
516# CONFIG_C2PORT is not set
517
518#
519# EEPROM support
520#
521# CONFIG_EEPROM_AT24 is not set
522# CONFIG_EEPROM_LEGACY is not set
523# CONFIG_EEPROM_93CX6 is not set
493CONFIG_HAVE_IDE=y 524CONFIG_HAVE_IDE=y
494# CONFIG_IDE is not set 525# CONFIG_IDE is not set
495 526
@@ -547,7 +578,11 @@ CONFIG_SCSI_LOWLEVEL=y
547# CONFIG_MEGARAID_NEWGEN is not set 578# CONFIG_MEGARAID_NEWGEN is not set
548# CONFIG_MEGARAID_LEGACY is not set 579# CONFIG_MEGARAID_LEGACY is not set
549# CONFIG_MEGARAID_SAS is not set 580# CONFIG_MEGARAID_SAS is not set
581# CONFIG_SCSI_MPT2SAS is not set
550# CONFIG_SCSI_HPTIOP is not set 582# CONFIG_SCSI_HPTIOP is not set
583# CONFIG_LIBFC is not set
584# CONFIG_LIBFCOE is not set
585# CONFIG_FCOE is not set
551# CONFIG_SCSI_DMX3191D is not set 586# CONFIG_SCSI_DMX3191D is not set
552# CONFIG_SCSI_FUTURE_DOMAIN is not set 587# CONFIG_SCSI_FUTURE_DOMAIN is not set
553# CONFIG_SCSI_IPS is not set 588# CONFIG_SCSI_IPS is not set
@@ -566,6 +601,8 @@ CONFIG_SCSI_LOWLEVEL=y
566# CONFIG_SCSI_NSP32 is not set 601# CONFIG_SCSI_NSP32 is not set
567# CONFIG_SCSI_DEBUG is not set 602# CONFIG_SCSI_DEBUG is not set
568# CONFIG_SCSI_SRP is not set 603# CONFIG_SCSI_SRP is not set
604# CONFIG_SCSI_DH is not set
605# CONFIG_SCSI_OSD_INITIATOR is not set
569CONFIG_ATA=y 606CONFIG_ATA=y
570# CONFIG_ATA_NONSTANDARD is not set 607# CONFIG_ATA_NONSTANDARD is not set
571CONFIG_SATA_PMP=y 608CONFIG_SATA_PMP=y
@@ -632,11 +669,15 @@ CONFIG_SATA_MV=y
632# 669#
633# IEEE 1394 (FireWire) support 670# IEEE 1394 (FireWire) support
634# 671#
672
673#
674# Enable only one of the two stacks, unless you know what you are doing
675#
635# CONFIG_FIREWIRE is not set 676# CONFIG_FIREWIRE is not set
636# CONFIG_IEEE1394 is not set 677# CONFIG_IEEE1394 is not set
637# CONFIG_I2O is not set 678# CONFIG_I2O is not set
638CONFIG_NETDEVICES=y 679CONFIG_NETDEVICES=y
639# CONFIG_NETDEVICES_MULTIQUEUE is not set 680CONFIG_COMPAT_NET_DEV_OPS=y
640# CONFIG_DUMMY is not set 681# CONFIG_DUMMY is not set
641# CONFIG_BONDING is not set 682# CONFIG_BONDING is not set
642# CONFIG_MACVLAN is not set 683# CONFIG_MACVLAN is not set
@@ -644,7 +685,26 @@ CONFIG_NETDEVICES=y
644# CONFIG_TUN is not set 685# CONFIG_TUN is not set
645# CONFIG_VETH is not set 686# CONFIG_VETH is not set
646# CONFIG_ARCNET is not set 687# CONFIG_ARCNET is not set
647# CONFIG_PHYLIB is not set 688CONFIG_PHYLIB=y
689
690#
691# MII PHY device drivers
692#
693CONFIG_MARVELL_PHY=y
694# CONFIG_DAVICOM_PHY is not set
695# CONFIG_QSEMI_PHY is not set
696# CONFIG_LXT_PHY is not set
697# CONFIG_CICADA_PHY is not set
698# CONFIG_VITESSE_PHY is not set
699# CONFIG_SMSC_PHY is not set
700# CONFIG_BROADCOM_PHY is not set
701# CONFIG_ICPLUS_PHY is not set
702# CONFIG_REALTEK_PHY is not set
703# CONFIG_NATIONAL_PHY is not set
704# CONFIG_STE10XP is not set
705# CONFIG_LSI_ET1011C_PHY is not set
706# CONFIG_FIXED_PHY is not set
707# CONFIG_MDIO_BITBANG is not set
648CONFIG_NET_ETHERNET=y 708CONFIG_NET_ETHERNET=y
649CONFIG_MII=y 709CONFIG_MII=y
650# CONFIG_AX88796 is not set 710# CONFIG_AX88796 is not set
@@ -654,19 +714,25 @@ CONFIG_MII=y
654# CONFIG_NET_VENDOR_3COM is not set 714# CONFIG_NET_VENDOR_3COM is not set
655# CONFIG_SMC91X is not set 715# CONFIG_SMC91X is not set
656# CONFIG_DM9000 is not set 716# CONFIG_DM9000 is not set
717# CONFIG_ETHOC is not set
718# CONFIG_SMC911X is not set
719# CONFIG_SMSC911X is not set
720# CONFIG_DNET is not set
657# CONFIG_NET_TULIP is not set 721# CONFIG_NET_TULIP is not set
658# CONFIG_HP100 is not set 722# CONFIG_HP100 is not set
659# CONFIG_IBM_NEW_EMAC_ZMII is not set 723# CONFIG_IBM_NEW_EMAC_ZMII is not set
660# CONFIG_IBM_NEW_EMAC_RGMII is not set 724# CONFIG_IBM_NEW_EMAC_RGMII is not set
661# CONFIG_IBM_NEW_EMAC_TAH is not set 725# CONFIG_IBM_NEW_EMAC_TAH is not set
662# CONFIG_IBM_NEW_EMAC_EMAC4 is not set 726# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
727# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
728# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
729# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
663CONFIG_NET_PCI=y 730CONFIG_NET_PCI=y
664# CONFIG_PCNET32 is not set 731# CONFIG_PCNET32 is not set
665# CONFIG_AMD8111_ETH is not set 732# CONFIG_AMD8111_ETH is not set
666# CONFIG_ADAPTEC_STARFIRE is not set 733# CONFIG_ADAPTEC_STARFIRE is not set
667# CONFIG_B44 is not set 734# CONFIG_B44 is not set
668# CONFIG_FORCEDETH is not set 735# CONFIG_FORCEDETH is not set
669# CONFIG_EEPRO100 is not set
670# CONFIG_E100 is not set 736# CONFIG_E100 is not set
671# CONFIG_FEALNX is not set 737# CONFIG_FEALNX is not set
672# CONFIG_NATSEMI is not set 738# CONFIG_NATSEMI is not set
@@ -676,18 +742,20 @@ CONFIG_NET_PCI=y
676# CONFIG_R6040 is not set 742# CONFIG_R6040 is not set
677# CONFIG_SIS900 is not set 743# CONFIG_SIS900 is not set
678# CONFIG_EPIC100 is not set 744# CONFIG_EPIC100 is not set
745# CONFIG_SMSC9420 is not set
679# CONFIG_SUNDANCE is not set 746# CONFIG_SUNDANCE is not set
680# CONFIG_TLAN is not set 747# CONFIG_TLAN is not set
681# CONFIG_VIA_RHINE is not set 748# CONFIG_VIA_RHINE is not set
682# CONFIG_SC92031 is not set 749# CONFIG_SC92031 is not set
750# CONFIG_ATL2 is not set
683CONFIG_NETDEV_1000=y 751CONFIG_NETDEV_1000=y
684# CONFIG_ACENIC is not set 752# CONFIG_ACENIC is not set
685# CONFIG_DL2K is not set 753# CONFIG_DL2K is not set
686# CONFIG_E1000 is not set 754# CONFIG_E1000 is not set
687# CONFIG_E1000E is not set 755# CONFIG_E1000E is not set
688# CONFIG_E1000E_ENABLED is not set
689# CONFIG_IP1000 is not set 756# CONFIG_IP1000 is not set
690# CONFIG_IGB is not set 757# CONFIG_IGB is not set
758# CONFIG_IGBVF is not set
691# CONFIG_NS83820 is not set 759# CONFIG_NS83820 is not set
692# CONFIG_HAMACHI is not set 760# CONFIG_HAMACHI is not set
693# CONFIG_YELLOWFIN is not set 761# CONFIG_YELLOWFIN is not set
@@ -701,6 +769,9 @@ CONFIG_NETDEV_1000=y
701CONFIG_MV643XX_ETH=y 769CONFIG_MV643XX_ETH=y
702# CONFIG_QLA3XXX is not set 770# CONFIG_QLA3XXX is not set
703# CONFIG_ATL1 is not set 771# CONFIG_ATL1 is not set
772# CONFIG_ATL1E is not set
773# CONFIG_ATL1C is not set
774# CONFIG_JME is not set
704# CONFIG_NETDEV_10000 is not set 775# CONFIG_NETDEV_10000 is not set
705# CONFIG_TR is not set 776# CONFIG_TR is not set
706 777
@@ -709,7 +780,10 @@ CONFIG_MV643XX_ETH=y
709# 780#
710# CONFIG_WLAN_PRE80211 is not set 781# CONFIG_WLAN_PRE80211 is not set
711# CONFIG_WLAN_80211 is not set 782# CONFIG_WLAN_80211 is not set
712# CONFIG_IWLWIFI_LEDS is not set 783
784#
785# Enable WiMAX (Networking options) to see the WiMAX drivers
786#
713 787
714# 788#
715# USB Network Adapters 789# USB Network Adapters
@@ -786,11 +860,11 @@ CONFIG_SERIAL_CORE=y
786CONFIG_SERIAL_CORE_CONSOLE=y 860CONFIG_SERIAL_CORE_CONSOLE=y
787# CONFIG_SERIAL_JSM is not set 861# CONFIG_SERIAL_JSM is not set
788CONFIG_UNIX98_PTYS=y 862CONFIG_UNIX98_PTYS=y
863# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
789CONFIG_LEGACY_PTYS=y 864CONFIG_LEGACY_PTYS=y
790CONFIG_LEGACY_PTY_COUNT=16 865CONFIG_LEGACY_PTY_COUNT=16
791# CONFIG_IPMI_HANDLER is not set 866# CONFIG_IPMI_HANDLER is not set
792# CONFIG_HW_RANDOM is not set 867# CONFIG_HW_RANDOM is not set
793# CONFIG_NVRAM is not set
794# CONFIG_R3964 is not set 868# CONFIG_R3964 is not set
795# CONFIG_APPLICOM is not set 869# CONFIG_APPLICOM is not set
796# CONFIG_RAW_DRIVER is not set 870# CONFIG_RAW_DRIVER is not set
@@ -799,44 +873,63 @@ CONFIG_DEVPORT=y
799CONFIG_I2C=y 873CONFIG_I2C=y
800CONFIG_I2C_BOARDINFO=y 874CONFIG_I2C_BOARDINFO=y
801CONFIG_I2C_CHARDEV=y 875CONFIG_I2C_CHARDEV=y
876CONFIG_I2C_HELPER_AUTO=y
802 877
803# 878#
804# I2C Hardware Bus support 879# I2C Hardware Bus support
805# 880#
881
882#
883# PC SMBus host controller drivers
884#
806# CONFIG_I2C_ALI1535 is not set 885# CONFIG_I2C_ALI1535 is not set
807# CONFIG_I2C_ALI1563 is not set 886# CONFIG_I2C_ALI1563 is not set
808# CONFIG_I2C_ALI15X3 is not set 887# CONFIG_I2C_ALI15X3 is not set
809# CONFIG_I2C_AMD756 is not set 888# CONFIG_I2C_AMD756 is not set
810# CONFIG_I2C_AMD8111 is not set 889# CONFIG_I2C_AMD8111 is not set
811# CONFIG_I2C_I801 is not set 890# CONFIG_I2C_I801 is not set
812# CONFIG_I2C_I810 is not set 891# CONFIG_I2C_ISCH is not set
813# CONFIG_I2C_PIIX4 is not set 892# CONFIG_I2C_PIIX4 is not set
814# CONFIG_I2C_NFORCE2 is not set 893# CONFIG_I2C_NFORCE2 is not set
815# CONFIG_I2C_OCORES is not set
816# CONFIG_I2C_PARPORT_LIGHT is not set
817# CONFIG_I2C_PROSAVAGE is not set
818# CONFIG_I2C_SAVAGE4 is not set
819# CONFIG_I2C_SIMTEC is not set
820# CONFIG_I2C_SIS5595 is not set 894# CONFIG_I2C_SIS5595 is not set
821# CONFIG_I2C_SIS630 is not set 895# CONFIG_I2C_SIS630 is not set
822# CONFIG_I2C_SIS96X is not set 896# CONFIG_I2C_SIS96X is not set
823# CONFIG_I2C_TAOS_EVM is not set
824# CONFIG_I2C_STUB is not set
825# CONFIG_I2C_TINY_USB is not set
826# CONFIG_I2C_VIA is not set 897# CONFIG_I2C_VIA is not set
827# CONFIG_I2C_VIAPRO is not set 898# CONFIG_I2C_VIAPRO is not set
899
900#
901# I2C system bus drivers (mostly embedded / system-on-chip)
902#
903# CONFIG_I2C_GPIO is not set
904CONFIG_I2C_MV64XXX=y
905# CONFIG_I2C_OCORES is not set
906# CONFIG_I2C_SIMTEC is not set
907
908#
909# External I2C/SMBus adapter drivers
910#
911# CONFIG_I2C_PARPORT_LIGHT is not set
912# CONFIG_I2C_TAOS_EVM is not set
913# CONFIG_I2C_TINY_USB is not set
914
915#
916# Graphics adapter I2C/DDC channel drivers
917#
828# CONFIG_I2C_VOODOO3 is not set 918# CONFIG_I2C_VOODOO3 is not set
919
920#
921# Other I2C/SMBus bus drivers
922#
829# CONFIG_I2C_PCA_PLATFORM is not set 923# CONFIG_I2C_PCA_PLATFORM is not set
830CONFIG_I2C_MV64XXX=y 924# CONFIG_I2C_STUB is not set
831 925
832# 926#
833# Miscellaneous I2C Chip support 927# Miscellaneous I2C Chip support
834# 928#
835# CONFIG_DS1682 is not set 929# CONFIG_DS1682 is not set
836# CONFIG_EEPROM_LEGACY is not set
837# CONFIG_SENSORS_PCF8574 is not set 930# CONFIG_SENSORS_PCF8574 is not set
838# CONFIG_PCF8575 is not set 931# CONFIG_PCF8575 is not set
839# CONFIG_SENSORS_PCF8591 is not set 932# CONFIG_SENSORS_PCA9539 is not set
840# CONFIG_SENSORS_MAX6875 is not set 933# CONFIG_SENSORS_MAX6875 is not set
841# CONFIG_SENSORS_TSL2550 is not set 934# CONFIG_SENSORS_TSL2550 is not set
842# CONFIG_I2C_DEBUG_CORE is not set 935# CONFIG_I2C_DEBUG_CORE is not set
@@ -848,6 +941,7 @@ CONFIG_I2C_MV64XXX=y
848# CONFIG_POWER_SUPPLY is not set 941# CONFIG_POWER_SUPPLY is not set
849CONFIG_HWMON=y 942CONFIG_HWMON=y
850# CONFIG_HWMON_VID is not set 943# CONFIG_HWMON_VID is not set
944# CONFIG_SENSORS_AD7414 is not set
851# CONFIG_SENSORS_AD7418 is not set 945# CONFIG_SENSORS_AD7418 is not set
852# CONFIG_SENSORS_ADM1021 is not set 946# CONFIG_SENSORS_ADM1021 is not set
853# CONFIG_SENSORS_ADM1025 is not set 947# CONFIG_SENSORS_ADM1025 is not set
@@ -855,14 +949,17 @@ CONFIG_HWMON=y
855# CONFIG_SENSORS_ADM1029 is not set 949# CONFIG_SENSORS_ADM1029 is not set
856# CONFIG_SENSORS_ADM1031 is not set 950# CONFIG_SENSORS_ADM1031 is not set
857# CONFIG_SENSORS_ADM9240 is not set 951# CONFIG_SENSORS_ADM9240 is not set
952# CONFIG_SENSORS_ADT7462 is not set
858# CONFIG_SENSORS_ADT7470 is not set 953# CONFIG_SENSORS_ADT7470 is not set
859# CONFIG_SENSORS_ADT7473 is not set 954# CONFIG_SENSORS_ADT7473 is not set
955# CONFIG_SENSORS_ADT7475 is not set
860# CONFIG_SENSORS_ATXP1 is not set 956# CONFIG_SENSORS_ATXP1 is not set
861# CONFIG_SENSORS_DS1621 is not set 957# CONFIG_SENSORS_DS1621 is not set
862# CONFIG_SENSORS_I5K_AMB is not set 958# CONFIG_SENSORS_I5K_AMB is not set
863# CONFIG_SENSORS_F71805F is not set 959# CONFIG_SENSORS_F71805F is not set
864# CONFIG_SENSORS_F71882FG is not set 960# CONFIG_SENSORS_F71882FG is not set
865# CONFIG_SENSORS_F75375S is not set 961# CONFIG_SENSORS_F75375S is not set
962# CONFIG_SENSORS_G760A is not set
866# CONFIG_SENSORS_GL518SM is not set 963# CONFIG_SENSORS_GL518SM is not set
867# CONFIG_SENSORS_GL520SM is not set 964# CONFIG_SENSORS_GL520SM is not set
868# CONFIG_SENSORS_IT87 is not set 965# CONFIG_SENSORS_IT87 is not set
@@ -877,10 +974,15 @@ CONFIG_HWMON=y
877# CONFIG_SENSORS_LM90 is not set 974# CONFIG_SENSORS_LM90 is not set
878# CONFIG_SENSORS_LM92 is not set 975# CONFIG_SENSORS_LM92 is not set
879# CONFIG_SENSORS_LM93 is not set 976# CONFIG_SENSORS_LM93 is not set
977# CONFIG_SENSORS_LTC4215 is not set
978# CONFIG_SENSORS_LTC4245 is not set
979# CONFIG_SENSORS_LM95241 is not set
880# CONFIG_SENSORS_MAX1619 is not set 980# CONFIG_SENSORS_MAX1619 is not set
881# CONFIG_SENSORS_MAX6650 is not set 981# CONFIG_SENSORS_MAX6650 is not set
882# CONFIG_SENSORS_PC87360 is not set 982# CONFIG_SENSORS_PC87360 is not set
883# CONFIG_SENSORS_PC87427 is not set 983# CONFIG_SENSORS_PC87427 is not set
984# CONFIG_SENSORS_PCF8591 is not set
985# CONFIG_SENSORS_SHT15 is not set
884# CONFIG_SENSORS_SIS5595 is not set 986# CONFIG_SENSORS_SIS5595 is not set
885# CONFIG_SENSORS_DME1737 is not set 987# CONFIG_SENSORS_DME1737 is not set
886# CONFIG_SENSORS_SMSC47M1 is not set 988# CONFIG_SENSORS_SMSC47M1 is not set
@@ -900,20 +1002,28 @@ CONFIG_HWMON=y
900# CONFIG_SENSORS_W83627HF is not set 1002# CONFIG_SENSORS_W83627HF is not set
901# CONFIG_SENSORS_W83627EHF is not set 1003# CONFIG_SENSORS_W83627EHF is not set
902# CONFIG_HWMON_DEBUG_CHIP is not set 1004# CONFIG_HWMON_DEBUG_CHIP is not set
1005# CONFIG_THERMAL is not set
1006# CONFIG_THERMAL_HWMON is not set
903# CONFIG_WATCHDOG is not set 1007# CONFIG_WATCHDOG is not set
1008CONFIG_SSB_POSSIBLE=y
904 1009
905# 1010#
906# Sonics Silicon Backplane 1011# Sonics Silicon Backplane
907# 1012#
908CONFIG_SSB_POSSIBLE=y
909# CONFIG_SSB is not set 1013# CONFIG_SSB is not set
910 1014
911# 1015#
912# Multifunction device drivers 1016# Multifunction device drivers
913# 1017#
1018# CONFIG_MFD_CORE is not set
914# CONFIG_MFD_SM501 is not set 1019# CONFIG_MFD_SM501 is not set
915# CONFIG_MFD_ASIC3 is not set
916# CONFIG_HTC_PASIC3 is not set 1020# CONFIG_HTC_PASIC3 is not set
1021# CONFIG_TWL4030_CORE is not set
1022# CONFIG_MFD_TMIO is not set
1023# CONFIG_PMIC_DA903X is not set
1024# CONFIG_MFD_WM8400 is not set
1025# CONFIG_MFD_WM8350_I2C is not set
1026# CONFIG_MFD_PCF50633 is not set
917 1027
918# 1028#
919# Multimedia devices 1029# Multimedia devices
@@ -944,10 +1054,6 @@ CONFIG_SSB_POSSIBLE=y
944# Display device support 1054# Display device support
945# 1055#
946# CONFIG_DISPLAY_SUPPORT is not set 1056# CONFIG_DISPLAY_SUPPORT is not set
947
948#
949# Sound
950#
951# CONFIG_SOUND is not set 1057# CONFIG_SOUND is not set
952CONFIG_HID_SUPPORT=y 1058CONFIG_HID_SUPPORT=y
953CONFIG_HID=y 1059CONFIG_HID=y
@@ -958,9 +1064,36 @@ CONFIG_HID=y
958# USB Input Devices 1064# USB Input Devices
959# 1065#
960CONFIG_USB_HID=y 1066CONFIG_USB_HID=y
961# CONFIG_USB_HIDINPUT_POWERBOOK is not set 1067# CONFIG_HID_PID is not set
962# CONFIG_HID_FF is not set
963# CONFIG_USB_HIDDEV is not set 1068# CONFIG_USB_HIDDEV is not set
1069
1070#
1071# Special HID drivers
1072#
1073# CONFIG_HID_A4TECH is not set
1074# CONFIG_HID_APPLE is not set
1075# CONFIG_HID_BELKIN is not set
1076# CONFIG_HID_CHERRY is not set
1077# CONFIG_HID_CHICONY is not set
1078# CONFIG_HID_CYPRESS is not set
1079# CONFIG_DRAGONRISE_FF is not set
1080# CONFIG_HID_EZKEY is not set
1081# CONFIG_HID_KYE is not set
1082# CONFIG_HID_GYRATION is not set
1083# CONFIG_HID_KENSINGTON is not set
1084# CONFIG_HID_LOGITECH is not set
1085# CONFIG_HID_MICROSOFT is not set
1086# CONFIG_HID_MONTEREY is not set
1087# CONFIG_HID_NTRIG is not set
1088# CONFIG_HID_PANTHERLORD is not set
1089# CONFIG_HID_PETALYNX is not set
1090# CONFIG_HID_SAMSUNG is not set
1091# CONFIG_HID_SONY is not set
1092# CONFIG_HID_SUNPLUS is not set
1093# CONFIG_GREENASIA_FF is not set
1094# CONFIG_HID_TOPSEED is not set
1095# CONFIG_THRUSTMASTER_FF is not set
1096# CONFIG_ZEROPLUS_FF is not set
964CONFIG_USB_SUPPORT=y 1097CONFIG_USB_SUPPORT=y
965CONFIG_USB_ARCH_HAS_HCD=y 1098CONFIG_USB_ARCH_HAS_HCD=y
966CONFIG_USB_ARCH_HAS_OHCI=y 1099CONFIG_USB_ARCH_HAS_OHCI=y
@@ -978,6 +1111,9 @@ CONFIG_USB_DEVICE_CLASS=y
978# CONFIG_USB_OTG is not set 1111# CONFIG_USB_OTG is not set
979# CONFIG_USB_OTG_WHITELIST is not set 1112# CONFIG_USB_OTG_WHITELIST is not set
980# CONFIG_USB_OTG_BLACKLIST_HUB is not set 1113# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1114# CONFIG_USB_MON is not set
1115# CONFIG_USB_WUSB is not set
1116# CONFIG_USB_WUSB_CBAF is not set
981 1117
982# 1118#
983# USB Host Controller Drivers 1119# USB Host Controller Drivers
@@ -986,12 +1122,15 @@ CONFIG_USB_DEVICE_CLASS=y
986CONFIG_USB_EHCI_HCD=y 1122CONFIG_USB_EHCI_HCD=y
987CONFIG_USB_EHCI_ROOT_HUB_TT=y 1123CONFIG_USB_EHCI_ROOT_HUB_TT=y
988CONFIG_USB_EHCI_TT_NEWSCHED=y 1124CONFIG_USB_EHCI_TT_NEWSCHED=y
1125# CONFIG_USB_OXU210HP_HCD is not set
989# CONFIG_USB_ISP116X_HCD is not set 1126# CONFIG_USB_ISP116X_HCD is not set
990# CONFIG_USB_ISP1760_HCD is not set 1127# CONFIG_USB_ISP1760_HCD is not set
991# CONFIG_USB_OHCI_HCD is not set 1128# CONFIG_USB_OHCI_HCD is not set
992# CONFIG_USB_UHCI_HCD is not set 1129# CONFIG_USB_UHCI_HCD is not set
993# CONFIG_USB_SL811_HCD is not set 1130# CONFIG_USB_SL811_HCD is not set
994# CONFIG_USB_R8A66597_HCD is not set 1131# CONFIG_USB_R8A66597_HCD is not set
1132# CONFIG_USB_WHCI_HCD is not set
1133# CONFIG_USB_HWA_HCD is not set
995 1134
996# 1135#
997# USB Device Class drivers 1136# USB Device Class drivers
@@ -999,20 +1138,20 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y
999# CONFIG_USB_ACM is not set 1138# CONFIG_USB_ACM is not set
1000CONFIG_USB_PRINTER=y 1139CONFIG_USB_PRINTER=y
1001# CONFIG_USB_WDM is not set 1140# CONFIG_USB_WDM is not set
1141# CONFIG_USB_TMC is not set
1002 1142
1003# 1143#
1004# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1144# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1005# 1145#
1006 1146
1007# 1147#
1008# may also be needed; see USB_STORAGE Help for more information 1148# also be needed; see USB_STORAGE Help for more info
1009# 1149#
1010CONFIG_USB_STORAGE=y 1150CONFIG_USB_STORAGE=y
1011# CONFIG_USB_STORAGE_DEBUG is not set 1151# CONFIG_USB_STORAGE_DEBUG is not set
1012CONFIG_USB_STORAGE_DATAFAB=y 1152CONFIG_USB_STORAGE_DATAFAB=y
1013CONFIG_USB_STORAGE_FREECOM=y 1153CONFIG_USB_STORAGE_FREECOM=y
1014# CONFIG_USB_STORAGE_ISD200 is not set 1154# CONFIG_USB_STORAGE_ISD200 is not set
1015CONFIG_USB_STORAGE_DPCM=y
1016# CONFIG_USB_STORAGE_USBAT is not set 1155# CONFIG_USB_STORAGE_USBAT is not set
1017CONFIG_USB_STORAGE_SDDR09=y 1156CONFIG_USB_STORAGE_SDDR09=y
1018CONFIG_USB_STORAGE_SDDR55=y 1157CONFIG_USB_STORAGE_SDDR55=y
@@ -1028,7 +1167,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1028# 1167#
1029# CONFIG_USB_MDC800 is not set 1168# CONFIG_USB_MDC800 is not set
1030# CONFIG_USB_MICROTEK is not set 1169# CONFIG_USB_MICROTEK is not set
1031# CONFIG_USB_MON is not set
1032 1170
1033# 1171#
1034# USB port drivers 1172# USB port drivers
@@ -1041,7 +1179,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1041# CONFIG_USB_EMI62 is not set 1179# CONFIG_USB_EMI62 is not set
1042# CONFIG_USB_EMI26 is not set 1180# CONFIG_USB_EMI26 is not set
1043# CONFIG_USB_ADUTUX is not set 1181# CONFIG_USB_ADUTUX is not set
1044# CONFIG_USB_AUERSWALD is not set 1182# CONFIG_USB_SEVSEG is not set
1045# CONFIG_USB_RIO500 is not set 1183# CONFIG_USB_RIO500 is not set
1046# CONFIG_USB_LEGOTOWER is not set 1184# CONFIG_USB_LEGOTOWER is not set
1047# CONFIG_USB_LCD is not set 1185# CONFIG_USB_LCD is not set
@@ -1049,7 +1187,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1049# CONFIG_USB_LED is not set 1187# CONFIG_USB_LED is not set
1050# CONFIG_USB_CYPRESS_CY7C63 is not set 1188# CONFIG_USB_CYPRESS_CY7C63 is not set
1051# CONFIG_USB_CYTHERM is not set 1189# CONFIG_USB_CYTHERM is not set
1052# CONFIG_USB_PHIDGET is not set
1053# CONFIG_USB_IDMOUSE is not set 1190# CONFIG_USB_IDMOUSE is not set
1054# CONFIG_USB_FTDI_ELAN is not set 1191# CONFIG_USB_FTDI_ELAN is not set
1055# CONFIG_USB_APPLEDISPLAY is not set 1192# CONFIG_USB_APPLEDISPLAY is not set
@@ -1059,14 +1196,29 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1059# CONFIG_USB_IOWARRIOR is not set 1196# CONFIG_USB_IOWARRIOR is not set
1060# CONFIG_USB_TEST is not set 1197# CONFIG_USB_TEST is not set
1061# CONFIG_USB_ISIGHTFW is not set 1198# CONFIG_USB_ISIGHTFW is not set
1199# CONFIG_USB_VST is not set
1062# CONFIG_USB_GADGET is not set 1200# CONFIG_USB_GADGET is not set
1201
1202#
1203# OTG and related infrastructure
1204#
1205# CONFIG_USB_GPIO_VBUS is not set
1206# CONFIG_NOP_USB_XCEIV is not set
1207# CONFIG_UWB is not set
1063# CONFIG_MMC is not set 1208# CONFIG_MMC is not set
1209# CONFIG_MEMSTICK is not set
1210# CONFIG_ACCESSIBILITY is not set
1064CONFIG_NEW_LEDS=y 1211CONFIG_NEW_LEDS=y
1065CONFIG_LEDS_CLASS=y 1212CONFIG_LEDS_CLASS=y
1066 1213
1067# 1214#
1068# LED drivers 1215# LED drivers
1069# 1216#
1217# CONFIG_LEDS_PCA9532 is not set
1218# CONFIG_LEDS_GPIO is not set
1219# CONFIG_LEDS_LP5521 is not set
1220# CONFIG_LEDS_PCA955X is not set
1221# CONFIG_LEDS_BD2802 is not set
1070 1222
1071# 1223#
1072# LED Triggers 1224# LED Triggers
@@ -1074,7 +1226,12 @@ CONFIG_LEDS_CLASS=y
1074CONFIG_LEDS_TRIGGERS=y 1226CONFIG_LEDS_TRIGGERS=y
1075CONFIG_LEDS_TRIGGER_TIMER=y 1227CONFIG_LEDS_TRIGGER_TIMER=y
1076CONFIG_LEDS_TRIGGER_HEARTBEAT=y 1228CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1229# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
1077# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set 1230# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
1231
1232#
1233# iptables trigger is under Netfilter config (LED target)
1234#
1078CONFIG_RTC_LIB=y 1235CONFIG_RTC_LIB=y
1079CONFIG_RTC_CLASS=y 1236CONFIG_RTC_CLASS=y
1080CONFIG_RTC_HCTOSYS=y 1237CONFIG_RTC_HCTOSYS=y
@@ -1105,6 +1262,8 @@ CONFIG_RTC_DRV_RS5C372=y
1105CONFIG_RTC_DRV_M41T80=y 1262CONFIG_RTC_DRV_M41T80=y
1106# CONFIG_RTC_DRV_M41T80_WDT is not set 1263# CONFIG_RTC_DRV_M41T80_WDT is not set
1107# CONFIG_RTC_DRV_S35390A is not set 1264# CONFIG_RTC_DRV_S35390A is not set
1265# CONFIG_RTC_DRV_FM3130 is not set
1266# CONFIG_RTC_DRV_RX8581 is not set
1108 1267
1109# 1268#
1110# SPI RTC drivers 1269# SPI RTC drivers
@@ -1114,18 +1273,25 @@ CONFIG_RTC_DRV_M41T80=y
1114# Platform RTC drivers 1273# Platform RTC drivers
1115# 1274#
1116# CONFIG_RTC_DRV_CMOS is not set 1275# CONFIG_RTC_DRV_CMOS is not set
1276# CONFIG_RTC_DRV_DS1286 is not set
1117# CONFIG_RTC_DRV_DS1511 is not set 1277# CONFIG_RTC_DRV_DS1511 is not set
1118# CONFIG_RTC_DRV_DS1553 is not set 1278# CONFIG_RTC_DRV_DS1553 is not set
1119# CONFIG_RTC_DRV_DS1742 is not set 1279# CONFIG_RTC_DRV_DS1742 is not set
1120# CONFIG_RTC_DRV_STK17TA8 is not set 1280# CONFIG_RTC_DRV_STK17TA8 is not set
1121# CONFIG_RTC_DRV_M48T86 is not set 1281# CONFIG_RTC_DRV_M48T86 is not set
1282# CONFIG_RTC_DRV_M48T35 is not set
1122# CONFIG_RTC_DRV_M48T59 is not set 1283# CONFIG_RTC_DRV_M48T59 is not set
1284# CONFIG_RTC_DRV_BQ4802 is not set
1123# CONFIG_RTC_DRV_V3020 is not set 1285# CONFIG_RTC_DRV_V3020 is not set
1124 1286
1125# 1287#
1126# on-CPU RTC drivers 1288# on-CPU RTC drivers
1127# 1289#
1290# CONFIG_DMADEVICES is not set
1291# CONFIG_AUXDISPLAY is not set
1292# CONFIG_REGULATOR is not set
1128# CONFIG_UIO is not set 1293# CONFIG_UIO is not set
1294# CONFIG_STAGING is not set
1129 1295
1130# 1296#
1131# File systems 1297# File systems
@@ -1134,14 +1300,25 @@ CONFIG_EXT2_FS=y
1134# CONFIG_EXT2_FS_XATTR is not set 1300# CONFIG_EXT2_FS_XATTR is not set
1135# CONFIG_EXT2_FS_XIP is not set 1301# CONFIG_EXT2_FS_XIP is not set
1136CONFIG_EXT3_FS=y 1302CONFIG_EXT3_FS=y
1303# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1137# CONFIG_EXT3_FS_XATTR is not set 1304# CONFIG_EXT3_FS_XATTR is not set
1138# CONFIG_EXT4DEV_FS is not set 1305CONFIG_EXT4_FS=m
1306# CONFIG_EXT4DEV_COMPAT is not set
1307CONFIG_EXT4_FS_XATTR=y
1308# CONFIG_EXT4_FS_POSIX_ACL is not set
1309# CONFIG_EXT4_FS_SECURITY is not set
1139CONFIG_JBD=y 1310CONFIG_JBD=y
1311# CONFIG_JBD_DEBUG is not set
1312CONFIG_JBD2=m
1313# CONFIG_JBD2_DEBUG is not set
1314CONFIG_FS_MBCACHE=m
1140# CONFIG_REISERFS_FS is not set 1315# CONFIG_REISERFS_FS is not set
1141# CONFIG_JFS_FS is not set 1316# CONFIG_JFS_FS is not set
1142# CONFIG_FS_POSIX_ACL is not set 1317# CONFIG_FS_POSIX_ACL is not set
1318CONFIG_FILE_LOCKING=y
1143# CONFIG_XFS_FS is not set 1319# CONFIG_XFS_FS is not set
1144# CONFIG_OCFS2_FS is not set 1320# CONFIG_OCFS2_FS is not set
1321# CONFIG_BTRFS_FS is not set
1145CONFIG_DNOTIFY=y 1322CONFIG_DNOTIFY=y
1146CONFIG_INOTIFY=y 1323CONFIG_INOTIFY=y
1147CONFIG_INOTIFY_USER=y 1324CONFIG_INOTIFY_USER=y
@@ -1151,6 +1328,11 @@ CONFIG_INOTIFY_USER=y
1151# CONFIG_FUSE_FS is not set 1328# CONFIG_FUSE_FS is not set
1152 1329
1153# 1330#
1331# Caches
1332#
1333# CONFIG_FSCACHE is not set
1334
1335#
1154# CD-ROM/DVD Filesystems 1336# CD-ROM/DVD Filesystems
1155# 1337#
1156CONFIG_ISO9660_FS=m 1338CONFIG_ISO9660_FS=m
@@ -1174,15 +1356,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1174# 1356#
1175CONFIG_PROC_FS=y 1357CONFIG_PROC_FS=y
1176CONFIG_PROC_SYSCTL=y 1358CONFIG_PROC_SYSCTL=y
1359CONFIG_PROC_PAGE_MONITOR=y
1177CONFIG_SYSFS=y 1360CONFIG_SYSFS=y
1178CONFIG_TMPFS=y 1361CONFIG_TMPFS=y
1179# CONFIG_TMPFS_POSIX_ACL is not set 1362# CONFIG_TMPFS_POSIX_ACL is not set
1180# CONFIG_HUGETLB_PAGE is not set 1363# CONFIG_HUGETLB_PAGE is not set
1181# CONFIG_CONFIGFS_FS is not set 1364# CONFIG_CONFIGFS_FS is not set
1182 1365CONFIG_MISC_FILESYSTEMS=y
1183#
1184# Miscellaneous filesystems
1185#
1186# CONFIG_ADFS_FS is not set 1366# CONFIG_ADFS_FS is not set
1187# CONFIG_AFFS_FS is not set 1367# CONFIG_AFFS_FS is not set
1188# CONFIG_HFS_FS is not set 1368# CONFIG_HFS_FS is not set
@@ -1202,25 +1382,27 @@ CONFIG_JFFS2_ZLIB=y
1202CONFIG_JFFS2_RTIME=y 1382CONFIG_JFFS2_RTIME=y
1203# CONFIG_JFFS2_RUBIN is not set 1383# CONFIG_JFFS2_RUBIN is not set
1204CONFIG_CRAMFS=y 1384CONFIG_CRAMFS=y
1385# CONFIG_SQUASHFS is not set
1205# CONFIG_VXFS_FS is not set 1386# CONFIG_VXFS_FS is not set
1206# CONFIG_MINIX_FS is not set 1387# CONFIG_MINIX_FS is not set
1388# CONFIG_OMFS_FS is not set
1207# CONFIG_HPFS_FS is not set 1389# CONFIG_HPFS_FS is not set
1208# CONFIG_QNX4FS_FS is not set 1390# CONFIG_QNX4FS_FS is not set
1209# CONFIG_ROMFS_FS is not set 1391# CONFIG_ROMFS_FS is not set
1210# CONFIG_SYSV_FS is not set 1392# CONFIG_SYSV_FS is not set
1211# CONFIG_UFS_FS is not set 1393# CONFIG_UFS_FS is not set
1394# CONFIG_NILFS2_FS is not set
1212CONFIG_NETWORK_FILESYSTEMS=y 1395CONFIG_NETWORK_FILESYSTEMS=y
1213CONFIG_NFS_FS=y 1396CONFIG_NFS_FS=y
1214CONFIG_NFS_V3=y 1397CONFIG_NFS_V3=y
1215# CONFIG_NFS_V3_ACL is not set 1398# CONFIG_NFS_V3_ACL is not set
1216# CONFIG_NFS_V4 is not set 1399# CONFIG_NFS_V4 is not set
1217# CONFIG_NFSD is not set
1218CONFIG_ROOT_NFS=y 1400CONFIG_ROOT_NFS=y
1401# CONFIG_NFSD is not set
1219CONFIG_LOCKD=y 1402CONFIG_LOCKD=y
1220CONFIG_LOCKD_V4=y 1403CONFIG_LOCKD_V4=y
1221CONFIG_NFS_COMMON=y 1404CONFIG_NFS_COMMON=y
1222CONFIG_SUNRPC=y 1405CONFIG_SUNRPC=y
1223# CONFIG_SUNRPC_BIND34 is not set
1224# CONFIG_RPCSEC_GSS_KRB5 is not set 1406# CONFIG_RPCSEC_GSS_KRB5 is not set
1225# CONFIG_RPCSEC_GSS_SPKM3 is not set 1407# CONFIG_RPCSEC_GSS_SPKM3 is not set
1226# CONFIG_SMB_FS is not set 1408# CONFIG_SMB_FS is not set
@@ -1301,11 +1483,16 @@ CONFIG_ENABLE_MUST_CHECK=y
1301CONFIG_FRAME_WARN=1024 1483CONFIG_FRAME_WARN=1024
1302CONFIG_MAGIC_SYSRQ=y 1484CONFIG_MAGIC_SYSRQ=y
1303# CONFIG_UNUSED_SYMBOLS is not set 1485# CONFIG_UNUSED_SYMBOLS is not set
1304# CONFIG_DEBUG_FS is not set 1486CONFIG_DEBUG_FS=y
1305# CONFIG_HEADERS_CHECK is not set 1487# CONFIG_HEADERS_CHECK is not set
1306CONFIG_DEBUG_KERNEL=y 1488CONFIG_DEBUG_KERNEL=y
1307# CONFIG_DEBUG_SHIRQ is not set 1489# CONFIG_DEBUG_SHIRQ is not set
1308CONFIG_DETECT_SOFTLOCKUP=y 1490CONFIG_DETECT_SOFTLOCKUP=y
1491# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1492CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1493CONFIG_DETECT_HUNG_TASK=y
1494# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1495CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1309CONFIG_SCHED_DEBUG=y 1496CONFIG_SCHED_DEBUG=y
1310CONFIG_SCHEDSTATS=y 1497CONFIG_SCHEDSTATS=y
1311# CONFIG_TIMER_STATS is not set 1498# CONFIG_TIMER_STATS is not set
@@ -1320,22 +1507,55 @@ CONFIG_DEBUG_PREEMPT=y
1320# CONFIG_LOCK_STAT is not set 1507# CONFIG_LOCK_STAT is not set
1321# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1508# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1322# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1509# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1510CONFIG_STACKTRACE=y
1323# CONFIG_DEBUG_KOBJECT is not set 1511# CONFIG_DEBUG_KOBJECT is not set
1512# CONFIG_DEBUG_HIGHMEM is not set
1324# CONFIG_DEBUG_BUGVERBOSE is not set 1513# CONFIG_DEBUG_BUGVERBOSE is not set
1325CONFIG_DEBUG_INFO=y 1514CONFIG_DEBUG_INFO=y
1326# CONFIG_DEBUG_VM is not set 1515# CONFIG_DEBUG_VM is not set
1327# CONFIG_DEBUG_WRITECOUNT is not set 1516# CONFIG_DEBUG_WRITECOUNT is not set
1517# CONFIG_DEBUG_MEMORY_INIT is not set
1328# CONFIG_DEBUG_LIST is not set 1518# CONFIG_DEBUG_LIST is not set
1329# CONFIG_DEBUG_SG is not set 1519# CONFIG_DEBUG_SG is not set
1330CONFIG_FRAME_POINTER=y 1520# CONFIG_DEBUG_NOTIFIERS is not set
1331# CONFIG_BOOT_PRINTK_DELAY is not set 1521# CONFIG_BOOT_PRINTK_DELAY is not set
1332# CONFIG_RCU_TORTURE_TEST is not set 1522# CONFIG_RCU_TORTURE_TEST is not set
1523# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1333# CONFIG_KPROBES_SANITY_TEST is not set 1524# CONFIG_KPROBES_SANITY_TEST is not set
1334# CONFIG_BACKTRACE_SELF_TEST is not set 1525# CONFIG_BACKTRACE_SELF_TEST is not set
1526# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1335# CONFIG_LKDTM is not set 1527# CONFIG_LKDTM is not set
1336# CONFIG_FAULT_INJECTION is not set 1528# CONFIG_FAULT_INJECTION is not set
1337# CONFIG_LATENCYTOP is not set 1529# CONFIG_LATENCYTOP is not set
1530CONFIG_SYSCTL_SYSCALL_CHECK=y
1531# CONFIG_PAGE_POISONING is not set
1532CONFIG_NOP_TRACER=y
1533CONFIG_HAVE_FUNCTION_TRACER=y
1534CONFIG_RING_BUFFER=y
1535CONFIG_TRACING=y
1536CONFIG_TRACING_SUPPORT=y
1537
1538#
1539# Tracers
1540#
1541# CONFIG_FUNCTION_TRACER is not set
1542# CONFIG_IRQSOFF_TRACER is not set
1543# CONFIG_PREEMPT_TRACER is not set
1544# CONFIG_SCHED_TRACER is not set
1545# CONFIG_CONTEXT_SWITCH_TRACER is not set
1546# CONFIG_EVENT_TRACER is not set
1547# CONFIG_BOOT_TRACER is not set
1548# CONFIG_TRACE_BRANCH_PROFILING is not set
1549# CONFIG_STACK_TRACER is not set
1550# CONFIG_KMEMTRACE is not set
1551# CONFIG_WORKQUEUE_TRACER is not set
1552# CONFIG_BLK_DEV_IO_TRACE is not set
1553# CONFIG_FTRACE_STARTUP_TEST is not set
1554# CONFIG_DYNAMIC_DEBUG is not set
1338# CONFIG_SAMPLES is not set 1555# CONFIG_SAMPLES is not set
1556CONFIG_HAVE_ARCH_KGDB=y
1557# CONFIG_KGDB is not set
1558CONFIG_ARM_UNWIND=y
1339CONFIG_DEBUG_USER=y 1559CONFIG_DEBUG_USER=y
1340CONFIG_DEBUG_ERRORS=y 1560CONFIG_DEBUG_ERRORS=y
1341# CONFIG_DEBUG_STACK_USAGE is not set 1561# CONFIG_DEBUG_STACK_USAGE is not set
@@ -1347,17 +1567,27 @@ CONFIG_DEBUG_LL=y
1347# 1567#
1348# CONFIG_KEYS is not set 1568# CONFIG_KEYS is not set
1349# CONFIG_SECURITY is not set 1569# CONFIG_SECURITY is not set
1570# CONFIG_SECURITYFS is not set
1350# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1571# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1351CONFIG_CRYPTO=y 1572CONFIG_CRYPTO=y
1352 1573
1353# 1574#
1354# Crypto core or helper 1575# Crypto core or helper
1355# 1576#
1577# CONFIG_CRYPTO_FIPS is not set
1356CONFIG_CRYPTO_ALGAPI=m 1578CONFIG_CRYPTO_ALGAPI=m
1579CONFIG_CRYPTO_ALGAPI2=m
1580CONFIG_CRYPTO_AEAD2=m
1357CONFIG_CRYPTO_BLKCIPHER=m 1581CONFIG_CRYPTO_BLKCIPHER=m
1582CONFIG_CRYPTO_BLKCIPHER2=m
1583CONFIG_CRYPTO_HASH2=m
1584CONFIG_CRYPTO_RNG2=m
1585CONFIG_CRYPTO_PCOMP=m
1358CONFIG_CRYPTO_MANAGER=m 1586CONFIG_CRYPTO_MANAGER=m
1587CONFIG_CRYPTO_MANAGER2=m
1359# CONFIG_CRYPTO_GF128MUL is not set 1588# CONFIG_CRYPTO_GF128MUL is not set
1360# CONFIG_CRYPTO_NULL is not set 1589# CONFIG_CRYPTO_NULL is not set
1590CONFIG_CRYPTO_WORKQUEUE=m
1361# CONFIG_CRYPTO_CRYPTD is not set 1591# CONFIG_CRYPTO_CRYPTD is not set
1362# CONFIG_CRYPTO_AUTHENC is not set 1592# CONFIG_CRYPTO_AUTHENC is not set
1363# CONFIG_CRYPTO_TEST is not set 1593# CONFIG_CRYPTO_TEST is not set
@@ -1393,6 +1623,10 @@ CONFIG_CRYPTO_PCBC=m
1393# CONFIG_CRYPTO_MD4 is not set 1623# CONFIG_CRYPTO_MD4 is not set
1394# CONFIG_CRYPTO_MD5 is not set 1624# CONFIG_CRYPTO_MD5 is not set
1395# CONFIG_CRYPTO_MICHAEL_MIC is not set 1625# CONFIG_CRYPTO_MICHAEL_MIC is not set
1626# CONFIG_CRYPTO_RMD128 is not set
1627# CONFIG_CRYPTO_RMD160 is not set
1628# CONFIG_CRYPTO_RMD256 is not set
1629# CONFIG_CRYPTO_RMD320 is not set
1396# CONFIG_CRYPTO_SHA1 is not set 1630# CONFIG_CRYPTO_SHA1 is not set
1397# CONFIG_CRYPTO_SHA256 is not set 1631# CONFIG_CRYPTO_SHA256 is not set
1398# CONFIG_CRYPTO_SHA512 is not set 1632# CONFIG_CRYPTO_SHA512 is not set
@@ -1422,25 +1656,32 @@ CONFIG_CRYPTO_PCBC=m
1422# Compression 1656# Compression
1423# 1657#
1424# CONFIG_CRYPTO_DEFLATE is not set 1658# CONFIG_CRYPTO_DEFLATE is not set
1659# CONFIG_CRYPTO_ZLIB is not set
1425# CONFIG_CRYPTO_LZO is not set 1660# CONFIG_CRYPTO_LZO is not set
1661
1662#
1663# Random Number Generation
1664#
1665# CONFIG_CRYPTO_ANSI_CPRNG is not set
1426CONFIG_CRYPTO_HW=y 1666CONFIG_CRYPTO_HW=y
1427# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1667# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1668CONFIG_BINARY_PRINTF=y
1428 1669
1429# 1670#
1430# Library routines 1671# Library routines
1431# 1672#
1432CONFIG_BITREVERSE=y 1673CONFIG_BITREVERSE=y
1433# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1674CONFIG_GENERIC_FIND_LAST_BIT=y
1434# CONFIG_GENERIC_FIND_NEXT_BIT is not set
1435# CONFIG_CRC_CCITT is not set 1675# CONFIG_CRC_CCITT is not set
1436# CONFIG_CRC16 is not set 1676CONFIG_CRC16=m
1677# CONFIG_CRC_T10DIF is not set
1437CONFIG_CRC_ITU_T=m 1678CONFIG_CRC_ITU_T=m
1438CONFIG_CRC32=y 1679CONFIG_CRC32=y
1439# CONFIG_CRC7 is not set 1680# CONFIG_CRC7 is not set
1440# CONFIG_LIBCRC32C is not set 1681# CONFIG_LIBCRC32C is not set
1441CONFIG_ZLIB_INFLATE=y 1682CONFIG_ZLIB_INFLATE=y
1442CONFIG_ZLIB_DEFLATE=y 1683CONFIG_ZLIB_DEFLATE=y
1443CONFIG_PLIST=y
1444CONFIG_HAS_IOMEM=y 1684CONFIG_HAS_IOMEM=y
1445CONFIG_HAS_IOPORT=y 1685CONFIG_HAS_IOPORT=y
1446CONFIG_HAS_DMA=y 1686CONFIG_HAS_DMA=y
1687CONFIG_NLATTR=y
diff --git a/arch/arm/configs/mx31moboard_defconfig b/arch/arm/configs/mx31moboard_defconfig
deleted file mode 100644
index e90f86d6deef..000000000000
--- a/arch/arm/configs/mx31moboard_defconfig
+++ /dev/null
@@ -1,790 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.27-rc5
4# Fri Oct 24 11:41:22 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
16CONFIG_LOCKDEP_SUPPORT=y
17CONFIG_TRACE_IRQFLAGS_SUPPORT=y
18CONFIG_HARDIRQS_SW_RESEND=y
19CONFIG_GENERIC_IRQ_PROBE=y
20CONFIG_RWSEM_GENERIC_SPINLOCK=y
21# CONFIG_ARCH_HAS_ILOG2_U32 is not set
22# CONFIG_ARCH_HAS_ILOG2_U64 is not set
23CONFIG_GENERIC_HWEIGHT=y
24CONFIG_GENERIC_CALIBRATE_DELAY=y
25CONFIG_ARCH_SUPPORTS_AOUT=y
26CONFIG_ZONE_DMA=y
27CONFIG_ARCH_MTD_XIP=y
28CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
29CONFIG_VECTORS_BASE=0xffff0000
30CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
31
32#
33# General setup
34#
35CONFIG_EXPERIMENTAL=y
36CONFIG_BROKEN_ON_SMP=y
37CONFIG_LOCK_KERNEL=y
38CONFIG_INIT_ENV_ARG_LIMIT=32
39CONFIG_LOCALVERSION=""
40CONFIG_LOCALVERSION_AUTO=y
41CONFIG_SWAP=y
42CONFIG_SYSVIPC=y
43CONFIG_SYSVIPC_SYSCTL=y
44# CONFIG_POSIX_MQUEUE is not set
45# CONFIG_BSD_PROCESS_ACCT is not set
46# CONFIG_TASKSTATS is not set
47# CONFIG_AUDIT is not set
48CONFIG_IKCONFIG=y
49CONFIG_IKCONFIG_PROC=y
50CONFIG_LOG_BUF_SHIFT=14
51# CONFIG_CGROUPS is not set
52CONFIG_GROUP_SCHED=y
53CONFIG_FAIR_GROUP_SCHED=y
54# CONFIG_RT_GROUP_SCHED is not set
55CONFIG_USER_SCHED=y
56# CONFIG_CGROUP_SCHED is not set
57CONFIG_SYSFS_DEPRECATED=y
58CONFIG_SYSFS_DEPRECATED_V2=y
59# CONFIG_RELAY is not set
60# CONFIG_NAMESPACES is not set
61# CONFIG_BLK_DEV_INITRD is not set
62CONFIG_CC_OPTIMIZE_FOR_SIZE=y
63CONFIG_SYSCTL=y
64CONFIG_EMBEDDED=y
65CONFIG_UID16=y
66CONFIG_SYSCTL_SYSCALL=y
67CONFIG_KALLSYMS=y
68# CONFIG_KALLSYMS_EXTRA_PASS is not set
69CONFIG_HOTPLUG=y
70CONFIG_PRINTK=y
71CONFIG_BUG=y
72CONFIG_ELF_CORE=y
73CONFIG_COMPAT_BRK=y
74CONFIG_BASE_FULL=y
75CONFIG_FUTEX=y
76CONFIG_ANON_INODES=y
77CONFIG_EPOLL=y
78CONFIG_SIGNALFD=y
79CONFIG_TIMERFD=y
80CONFIG_EVENTFD=y
81CONFIG_SHMEM=y
82CONFIG_VM_EVENT_COUNTERS=y
83CONFIG_SLAB=y
84# CONFIG_SLUB is not set
85# CONFIG_SLOB is not set
86# CONFIG_PROFILING is not set
87# CONFIG_MARKERS is not set
88CONFIG_HAVE_OPROFILE=y
89# CONFIG_KPROBES is not set
90# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
91# CONFIG_HAVE_IOREMAP_PROT is not set
92CONFIG_HAVE_KPROBES=y
93CONFIG_HAVE_KRETPROBES=y
94# CONFIG_HAVE_ARCH_TRACEHOOK is not set
95# CONFIG_HAVE_DMA_ATTRS is not set
96# CONFIG_USE_GENERIC_SMP_HELPERS is not set
97# CONFIG_HAVE_CLK is not set
98CONFIG_PROC_PAGE_MONITOR=y
99CONFIG_HAVE_GENERIC_DMA_COHERENT=y
100CONFIG_SLABINFO=y
101CONFIG_RT_MUTEXES=y
102# CONFIG_TINY_SHMEM is not set
103CONFIG_BASE_SMALL=0
104CONFIG_MODULES=y
105# CONFIG_MODULE_FORCE_LOAD is not set
106CONFIG_MODULE_UNLOAD=y
107CONFIG_MODULE_FORCE_UNLOAD=y
108CONFIG_MODVERSIONS=y
109# CONFIG_MODULE_SRCVERSION_ALL is not set
110CONFIG_KMOD=y
111CONFIG_BLOCK=y
112# CONFIG_LBD is not set
113# CONFIG_BLK_DEV_IO_TRACE is not set
114# CONFIG_LSF is not set
115# CONFIG_BLK_DEV_BSG is not set
116# CONFIG_BLK_DEV_INTEGRITY is not set
117
118#
119# IO Schedulers
120#
121CONFIG_IOSCHED_NOOP=y
122CONFIG_IOSCHED_AS=y
123CONFIG_IOSCHED_DEADLINE=y
124CONFIG_IOSCHED_CFQ=y
125# CONFIG_DEFAULT_AS is not set
126# CONFIG_DEFAULT_DEADLINE is not set
127CONFIG_DEFAULT_CFQ=y
128# CONFIG_DEFAULT_NOOP is not set
129CONFIG_DEFAULT_IOSCHED="cfq"
130CONFIG_CLASSIC_RCU=y
131
132#
133# System Type
134#
135# CONFIG_ARCH_AAEC2000 is not set
136# CONFIG_ARCH_INTEGRATOR is not set
137# CONFIG_ARCH_REALVIEW is not set
138# CONFIG_ARCH_VERSATILE is not set
139# CONFIG_ARCH_AT91 is not set
140# CONFIG_ARCH_CLPS7500 is not set
141# CONFIG_ARCH_CLPS711X is not set
142# CONFIG_ARCH_EBSA110 is not set
143# CONFIG_ARCH_EP93XX is not set
144# CONFIG_ARCH_FOOTBRIDGE is not set
145# CONFIG_ARCH_NETX is not set
146# CONFIG_ARCH_H720X is not set
147# CONFIG_ARCH_IMX is not set
148# CONFIG_ARCH_IOP13XX is not set
149# CONFIG_ARCH_IOP32X is not set
150# CONFIG_ARCH_IOP33X is not set
151# CONFIG_ARCH_IXP23XX is not set
152# CONFIG_ARCH_IXP2000 is not set
153# CONFIG_ARCH_IXP4XX is not set
154# CONFIG_ARCH_L7200 is not set
155# CONFIG_ARCH_KIRKWOOD is not set
156# CONFIG_ARCH_KS8695 is not set
157# CONFIG_ARCH_NS9XXX is not set
158# CONFIG_ARCH_LOKI is not set
159# CONFIG_ARCH_MV78XX0 is not set
160CONFIG_ARCH_MXC=y
161# CONFIG_ARCH_ORION5X is not set
162# CONFIG_ARCH_PNX4008 is not set
163# CONFIG_ARCH_PXA is not set
164# CONFIG_ARCH_RPC is not set
165# CONFIG_ARCH_SA1100 is not set
166# CONFIG_ARCH_S3C2410 is not set
167# CONFIG_ARCH_SHARK is not set
168# CONFIG_ARCH_LH7A40X is not set
169# CONFIG_ARCH_DAVINCI is not set
170# CONFIG_ARCH_OMAP is not set
171# CONFIG_ARCH_MSM7X00A is not set
172
173#
174# Boot options
175#
176
177#
178# Power management
179#
180
181#
182# Freescale MXC Implementations
183#
184# CONFIG_ARCH_MX2 is not set
185CONFIG_ARCH_MX3=y
186
187#
188# MX3 Options
189#
190# CONFIG_MACH_MX31ADS is not set
191# CONFIG_MACH_PCM037 is not set
192# CONFIG_MACH_MX31LITE is not set
193CONFIG_MACH_MX31MOBOARD=y
194# CONFIG_MXC_IRQ_PRIOR is not set
195
196#
197# Processor Type
198#
199CONFIG_CPU_32=y
200CONFIG_CPU_V6=y
201# CONFIG_CPU_32v6K is not set
202CONFIG_CPU_32v6=y
203CONFIG_CPU_ABRT_EV6=y
204CONFIG_CPU_PABRT_NOIFAR=y
205CONFIG_CPU_CACHE_V6=y
206CONFIG_CPU_CACHE_VIPT=y
207CONFIG_CPU_COPY_V6=y
208CONFIG_CPU_TLB_V6=y
209CONFIG_CPU_HAS_ASID=y
210CONFIG_CPU_CP15=y
211CONFIG_CPU_CP15_MMU=y
212
213#
214# Processor Features
215#
216CONFIG_ARM_THUMB=y
217# CONFIG_CPU_ICACHE_DISABLE is not set
218# CONFIG_CPU_DCACHE_DISABLE is not set
219# CONFIG_CPU_BPREDICT_DISABLE is not set
220# CONFIG_OUTER_CACHE is not set
221
222#
223# Bus support
224#
225# CONFIG_PCI_SYSCALL is not set
226# CONFIG_ARCH_SUPPORTS_MSI is not set
227# CONFIG_PCCARD is not set
228
229#
230# Kernel Features
231#
232CONFIG_TICK_ONESHOT=y
233CONFIG_NO_HZ=y
234CONFIG_HIGH_RES_TIMERS=y
235CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
236CONFIG_PREEMPT=y
237CONFIG_HZ=100
238CONFIG_AEABI=y
239# CONFIG_OABI_COMPAT is not set
240CONFIG_ARCH_FLATMEM_HAS_HOLES=y
241# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
242CONFIG_SELECT_MEMORY_MODEL=y
243CONFIG_FLATMEM_MANUAL=y
244# CONFIG_DISCONTIGMEM_MANUAL is not set
245# CONFIG_SPARSEMEM_MANUAL is not set
246CONFIG_FLATMEM=y
247CONFIG_FLAT_NODE_MEM_MAP=y
248# CONFIG_SPARSEMEM_STATIC is not set
249# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
250CONFIG_PAGEFLAGS_EXTENDED=y
251CONFIG_SPLIT_PTLOCK_CPUS=4
252# CONFIG_RESOURCES_64BIT is not set
253CONFIG_ZONE_DMA_FLAG=1
254CONFIG_BOUNCE=y
255CONFIG_VIRT_TO_BUS=y
256CONFIG_ALIGNMENT_TRAP=y
257
258#
259# Boot options
260#
261CONFIG_ZBOOT_ROM_TEXT=0x0
262CONFIG_ZBOOT_ROM_BSS=0x0
263CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
264# CONFIG_XIP_KERNEL is not set
265# CONFIG_KEXEC is not set
266
267#
268# Floating point emulation
269#
270
271#
272# At least one emulation must be selected
273#
274CONFIG_VFP=y
275
276#
277# Userspace binary formats
278#
279CONFIG_BINFMT_ELF=y
280# CONFIG_BINFMT_AOUT is not set
281# CONFIG_BINFMT_MISC is not set
282
283#
284# Power management options
285#
286# CONFIG_PM is not set
287CONFIG_ARCH_SUSPEND_POSSIBLE=y
288CONFIG_NET=y
289
290#
291# Networking options
292#
293CONFIG_PACKET=y
294# CONFIG_PACKET_MMAP is not set
295CONFIG_UNIX=y
296# CONFIG_NET_KEY is not set
297CONFIG_INET=y
298# CONFIG_IP_MULTICAST is not set
299# CONFIG_IP_ADVANCED_ROUTER is not set
300CONFIG_IP_FIB_HASH=y
301CONFIG_IP_PNP=y
302CONFIG_IP_PNP_DHCP=y
303# CONFIG_IP_PNP_BOOTP is not set
304# CONFIG_IP_PNP_RARP is not set
305# CONFIG_NET_IPIP is not set
306# CONFIG_NET_IPGRE is not set
307# CONFIG_ARPD is not set
308# CONFIG_SYN_COOKIES is not set
309# CONFIG_INET_AH is not set
310# CONFIG_INET_ESP is not set
311# CONFIG_INET_IPCOMP is not set
312# CONFIG_INET_XFRM_TUNNEL is not set
313# CONFIG_INET_TUNNEL is not set
314# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
315# CONFIG_INET_XFRM_MODE_TUNNEL is not set
316# CONFIG_INET_XFRM_MODE_BEET is not set
317# CONFIG_INET_LRO is not set
318# CONFIG_INET_DIAG is not set
319# CONFIG_TCP_CONG_ADVANCED is not set
320CONFIG_TCP_CONG_CUBIC=y
321CONFIG_DEFAULT_TCP_CONG="cubic"
322# CONFIG_TCP_MD5SIG is not set
323# CONFIG_IPV6 is not set
324# CONFIG_NETWORK_SECMARK is not set
325# CONFIG_NETFILTER is not set
326# CONFIG_IP_DCCP is not set
327# CONFIG_IP_SCTP is not set
328# CONFIG_TIPC is not set
329# CONFIG_ATM is not set
330# CONFIG_BRIDGE is not set
331# CONFIG_VLAN_8021Q is not set
332# CONFIG_DECNET is not set
333# CONFIG_LLC2 is not set
334# CONFIG_IPX is not set
335# CONFIG_ATALK is not set
336# CONFIG_X25 is not set
337# CONFIG_LAPB is not set
338# CONFIG_ECONET is not set
339# CONFIG_WAN_ROUTER is not set
340# CONFIG_NET_SCHED is not set
341
342#
343# Network testing
344#
345# CONFIG_NET_PKTGEN is not set
346# CONFIG_HAMRADIO is not set
347# CONFIG_CAN is not set
348# CONFIG_IRDA is not set
349# CONFIG_BT is not set
350# CONFIG_AF_RXRPC is not set
351
352#
353# Wireless
354#
355# CONFIG_CFG80211 is not set
356# CONFIG_WIRELESS_EXT is not set
357# CONFIG_MAC80211 is not set
358# CONFIG_IEEE80211 is not set
359# CONFIG_RFKILL is not set
360# CONFIG_NET_9P is not set
361
362#
363# Device Drivers
364#
365
366#
367# Generic Driver Options
368#
369CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
370CONFIG_STANDALONE=y
371CONFIG_PREVENT_FIRMWARE_BUILD=y
372CONFIG_FW_LOADER=m
373CONFIG_FIRMWARE_IN_KERNEL=y
374CONFIG_EXTRA_FIRMWARE=""
375# CONFIG_SYS_HYPERVISOR is not set
376# CONFIG_CONNECTOR is not set
377CONFIG_MTD=y
378# CONFIG_MTD_DEBUG is not set
379# CONFIG_MTD_CONCAT is not set
380CONFIG_MTD_PARTITIONS=y
381CONFIG_MTD_REDBOOT_PARTS=y
382CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
383# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
384CONFIG_MTD_REDBOOT_PARTS_READONLY=y
385# CONFIG_MTD_CMDLINE_PARTS is not set
386# CONFIG_MTD_AFS_PARTS is not set
387# CONFIG_MTD_AR7_PARTS is not set
388
389#
390# User Modules And Translation Layers
391#
392CONFIG_MTD_CHAR=y
393CONFIG_MTD_BLKDEVS=y
394CONFIG_MTD_BLOCK=y
395# CONFIG_FTL is not set
396# CONFIG_NFTL is not set
397# CONFIG_INFTL is not set
398# CONFIG_RFD_FTL is not set
399# CONFIG_SSFDC is not set
400# CONFIG_MTD_OOPS is not set
401
402#
403# RAM/ROM/Flash chip drivers
404#
405CONFIG_MTD_CFI=y
406# CONFIG_MTD_JEDECPROBE is not set
407CONFIG_MTD_GEN_PROBE=y
408CONFIG_MTD_CFI_ADV_OPTIONS=y
409CONFIG_MTD_CFI_NOSWAP=y
410# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
411# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
412CONFIG_MTD_CFI_GEOMETRY=y
413# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
414CONFIG_MTD_MAP_BANK_WIDTH_2=y
415# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
416# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
417# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
418# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
419CONFIG_MTD_CFI_I1=y
420# CONFIG_MTD_CFI_I2 is not set
421# CONFIG_MTD_CFI_I4 is not set
422# CONFIG_MTD_CFI_I8 is not set
423# CONFIG_MTD_OTP is not set
424# CONFIG_MTD_CFI_INTELEXT is not set
425CONFIG_MTD_CFI_AMDSTD=y
426# CONFIG_MTD_CFI_STAA is not set
427CONFIG_MTD_CFI_UTIL=y
428# CONFIG_MTD_RAM is not set
429# CONFIG_MTD_ROM is not set
430# CONFIG_MTD_ABSENT is not set
431# CONFIG_MTD_XIP is not set
432
433#
434# Mapping drivers for chip access
435#
436# CONFIG_MTD_COMPLEX_MAPPINGS is not set
437CONFIG_MTD_PHYSMAP=y
438CONFIG_MTD_PHYSMAP_START=0x0
439CONFIG_MTD_PHYSMAP_LEN=0x0
440CONFIG_MTD_PHYSMAP_BANKWIDTH=2
441# CONFIG_MTD_ARM_INTEGRATOR is not set
442# CONFIG_MTD_PLATRAM is not set
443
444#
445# Self-contained MTD device drivers
446#
447# CONFIG_MTD_SLRAM is not set
448# CONFIG_MTD_PHRAM is not set
449# CONFIG_MTD_MTDRAM is not set
450# CONFIG_MTD_BLOCK2MTD is not set
451
452#
453# Disk-On-Chip Device Drivers
454#
455# CONFIG_MTD_DOC2000 is not set
456# CONFIG_MTD_DOC2001 is not set
457# CONFIG_MTD_DOC2001PLUS is not set
458# CONFIG_MTD_NAND is not set
459# CONFIG_MTD_ONENAND is not set
460
461#
462# UBI - Unsorted block images
463#
464# CONFIG_MTD_UBI is not set
465# CONFIG_PARPORT is not set
466# CONFIG_BLK_DEV is not set
467# CONFIG_MISC_DEVICES is not set
468CONFIG_HAVE_IDE=y
469# CONFIG_IDE is not set
470
471#
472# SCSI device support
473#
474# CONFIG_RAID_ATTRS is not set
475# CONFIG_SCSI is not set
476# CONFIG_SCSI_DMA is not set
477# CONFIG_SCSI_NETLINK is not set
478# CONFIG_ATA is not set
479# CONFIG_MD is not set
480CONFIG_NETDEVICES=y
481# CONFIG_DUMMY is not set
482# CONFIG_BONDING is not set
483# CONFIG_MACVLAN is not set
484# CONFIG_EQUALIZER is not set
485# CONFIG_TUN is not set
486# CONFIG_VETH is not set
487# CONFIG_PHYLIB is not set
488CONFIG_NET_ETHERNET=y
489CONFIG_MII=y
490# CONFIG_AX88796 is not set
491CONFIG_SMC91X=y
492# CONFIG_DM9000 is not set
493# CONFIG_IBM_NEW_EMAC_ZMII is not set
494# CONFIG_IBM_NEW_EMAC_RGMII is not set
495# CONFIG_IBM_NEW_EMAC_TAH is not set
496# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
497# CONFIG_B44 is not set
498# CONFIG_NETDEV_1000 is not set
499# CONFIG_NETDEV_10000 is not set
500
501#
502# Wireless LAN
503#
504# CONFIG_WLAN_PRE80211 is not set
505# CONFIG_WLAN_80211 is not set
506# CONFIG_IWLWIFI_LEDS is not set
507# CONFIG_WAN is not set
508# CONFIG_PPP is not set
509# CONFIG_SLIP is not set
510# CONFIG_NETCONSOLE is not set
511# CONFIG_NETPOLL is not set
512# CONFIG_NET_POLL_CONTROLLER is not set
513# CONFIG_ISDN is not set
514
515#
516# Input device support
517#
518# CONFIG_INPUT is not set
519
520#
521# Hardware I/O ports
522#
523# CONFIG_SERIO is not set
524# CONFIG_GAMEPORT is not set
525
526#
527# Character devices
528#
529# CONFIG_VT is not set
530CONFIG_DEVKMEM=y
531# CONFIG_SERIAL_NONSTANDARD is not set
532
533#
534# Serial drivers
535#
536# CONFIG_SERIAL_8250 is not set
537
538#
539# Non-8250 serial port support
540#
541CONFIG_SERIAL_IMX=y
542CONFIG_SERIAL_IMX_CONSOLE=y
543CONFIG_SERIAL_CORE=y
544CONFIG_SERIAL_CORE_CONSOLE=y
545CONFIG_UNIX98_PTYS=y
546# CONFIG_LEGACY_PTYS is not set
547# CONFIG_IPMI_HANDLER is not set
548# CONFIG_HW_RANDOM is not set
549# CONFIG_NVRAM is not set
550# CONFIG_R3964 is not set
551# CONFIG_RAW_DRIVER is not set
552# CONFIG_TCG_TPM is not set
553# CONFIG_I2C is not set
554# CONFIG_SPI is not set
555CONFIG_ARCH_REQUIRE_GPIOLIB=y
556CONFIG_GPIOLIB=y
557# CONFIG_GPIO_SYSFS is not set
558
559#
560# I2C GPIO expanders:
561#
562
563#
564# PCI GPIO expanders:
565#
566
567#
568# SPI GPIO expanders:
569#
570# CONFIG_W1 is not set
571# CONFIG_POWER_SUPPLY is not set
572# CONFIG_HWMON is not set
573# CONFIG_WATCHDOG is not set
574
575#
576# Sonics Silicon Backplane
577#
578CONFIG_SSB_POSSIBLE=y
579# CONFIG_SSB is not set
580
581#
582# Multifunction device drivers
583#
584# CONFIG_MFD_CORE is not set
585# CONFIG_MFD_SM501 is not set
586# CONFIG_HTC_EGPIO is not set
587# CONFIG_HTC_PASIC3 is not set
588# CONFIG_MFD_TMIO is not set
589# CONFIG_MFD_T7L66XB is not set
590# CONFIG_MFD_TC6387XB is not set
591# CONFIG_MFD_TC6393XB is not set
592
593#
594# Multimedia devices
595#
596
597#
598# Multimedia core support
599#
600# CONFIG_VIDEO_DEV is not set
601# CONFIG_DVB_CORE is not set
602# CONFIG_VIDEO_MEDIA is not set
603
604#
605# Multimedia drivers
606#
607# CONFIG_DAB is not set
608
609#
610# Graphics support
611#
612# CONFIG_VGASTATE is not set
613# CONFIG_VIDEO_OUTPUT_CONTROL is not set
614# CONFIG_FB is not set
615# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
616
617#
618# Display device support
619#
620# CONFIG_DISPLAY_SUPPORT is not set
621# CONFIG_SOUND is not set
622# CONFIG_USB_SUPPORT is not set
623# CONFIG_MMC is not set
624# CONFIG_NEW_LEDS is not set
625CONFIG_RTC_LIB=y
626# CONFIG_RTC_CLASS is not set
627# CONFIG_DMADEVICES is not set
628
629#
630# Voltage and Current regulators
631#
632# CONFIG_REGULATOR is not set
633# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
634# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
635# CONFIG_REGULATOR_BQ24022 is not set
636# CONFIG_UIO is not set
637
638#
639# File systems
640#
641# CONFIG_EXT2_FS is not set
642# CONFIG_EXT3_FS is not set
643# CONFIG_EXT4DEV_FS is not set
644# CONFIG_REISERFS_FS is not set
645# CONFIG_JFS_FS is not set
646# CONFIG_FS_POSIX_ACL is not set
647# CONFIG_XFS_FS is not set
648# CONFIG_OCFS2_FS is not set
649# CONFIG_DNOTIFY is not set
650CONFIG_INOTIFY=y
651CONFIG_INOTIFY_USER=y
652# CONFIG_QUOTA is not set
653# CONFIG_AUTOFS_FS is not set
654# CONFIG_AUTOFS4_FS is not set
655# CONFIG_FUSE_FS is not set
656
657#
658# CD-ROM/DVD Filesystems
659#
660# CONFIG_ISO9660_FS is not set
661# CONFIG_UDF_FS is not set
662
663#
664# DOS/FAT/NT Filesystems
665#
666# CONFIG_MSDOS_FS is not set
667# CONFIG_VFAT_FS is not set
668# CONFIG_NTFS_FS is not set
669
670#
671# Pseudo filesystems
672#
673CONFIG_PROC_FS=y
674CONFIG_PROC_SYSCTL=y
675CONFIG_SYSFS=y
676CONFIG_TMPFS=y
677# CONFIG_TMPFS_POSIX_ACL is not set
678# CONFIG_HUGETLB_PAGE is not set
679# CONFIG_CONFIGFS_FS is not set
680
681#
682# Miscellaneous filesystems
683#
684# CONFIG_ADFS_FS is not set
685# CONFIG_AFFS_FS is not set
686# CONFIG_HFS_FS is not set
687# CONFIG_HFSPLUS_FS is not set
688# CONFIG_BEFS_FS is not set
689# CONFIG_BFS_FS is not set
690# CONFIG_EFS_FS is not set
691CONFIG_JFFS2_FS=y
692CONFIG_JFFS2_FS_DEBUG=0
693CONFIG_JFFS2_FS_WRITEBUFFER=y
694# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
695# CONFIG_JFFS2_SUMMARY is not set
696# CONFIG_JFFS2_FS_XATTR is not set
697# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
698CONFIG_JFFS2_ZLIB=y
699# CONFIG_JFFS2_LZO is not set
700CONFIG_JFFS2_RTIME=y
701# CONFIG_JFFS2_RUBIN is not set
702# CONFIG_CRAMFS is not set
703# CONFIG_VXFS_FS is not set
704# CONFIG_MINIX_FS is not set
705# CONFIG_OMFS_FS is not set
706# CONFIG_HPFS_FS is not set
707# CONFIG_QNX4FS_FS is not set
708# CONFIG_ROMFS_FS is not set
709# CONFIG_SYSV_FS is not set
710# CONFIG_UFS_FS is not set
711CONFIG_NETWORK_FILESYSTEMS=y
712CONFIG_NFS_FS=y
713# CONFIG_NFS_V3 is not set
714# CONFIG_NFS_V4 is not set
715CONFIG_ROOT_NFS=y
716# CONFIG_NFSD is not set
717CONFIG_LOCKD=y
718CONFIG_NFS_COMMON=y
719CONFIG_SUNRPC=y
720# CONFIG_RPCSEC_GSS_KRB5 is not set
721# CONFIG_RPCSEC_GSS_SPKM3 is not set
722# CONFIG_SMB_FS is not set
723# CONFIG_CIFS is not set
724# CONFIG_NCP_FS is not set
725# CONFIG_CODA_FS is not set
726# CONFIG_AFS_FS is not set
727
728#
729# Partition Types
730#
731# CONFIG_PARTITION_ADVANCED is not set
732CONFIG_MSDOS_PARTITION=y
733# CONFIG_NLS is not set
734# CONFIG_DLM is not set
735
736#
737# Kernel hacking
738#
739# CONFIG_PRINTK_TIME is not set
740# CONFIG_ENABLE_WARN_DEPRECATED is not set
741# CONFIG_ENABLE_MUST_CHECK is not set
742CONFIG_FRAME_WARN=1024
743# CONFIG_MAGIC_SYSRQ is not set
744# CONFIG_UNUSED_SYMBOLS is not set
745# CONFIG_DEBUG_FS is not set
746# CONFIG_HEADERS_CHECK is not set
747# CONFIG_DEBUG_KERNEL is not set
748# CONFIG_DEBUG_BUGVERBOSE is not set
749# CONFIG_DEBUG_MEMORY_INIT is not set
750CONFIG_FRAME_POINTER=y
751# CONFIG_LATENCYTOP is not set
752CONFIG_SYSCTL_SYSCALL_CHECK=y
753CONFIG_HAVE_FTRACE=y
754CONFIG_HAVE_DYNAMIC_FTRACE=y
755# CONFIG_FTRACE is not set
756# CONFIG_IRQSOFF_TRACER is not set
757# CONFIG_PREEMPT_TRACER is not set
758# CONFIG_SCHED_TRACER is not set
759# CONFIG_CONTEXT_SWITCH_TRACER is not set
760# CONFIG_SAMPLES is not set
761CONFIG_HAVE_ARCH_KGDB=y
762# CONFIG_DEBUG_USER is not set
763
764#
765# Security options
766#
767# CONFIG_KEYS is not set
768# CONFIG_SECURITY is not set
769# CONFIG_SECURITY_FILE_CAPABILITIES is not set
770# CONFIG_CRYPTO is not set
771
772#
773# Library routines
774#
775CONFIG_BITREVERSE=y
776# CONFIG_GENERIC_FIND_FIRST_BIT is not set
777# CONFIG_GENERIC_FIND_NEXT_BIT is not set
778# CONFIG_CRC_CCITT is not set
779# CONFIG_CRC16 is not set
780# CONFIG_CRC_T10DIF is not set
781# CONFIG_CRC_ITU_T is not set
782CONFIG_CRC32=y
783# CONFIG_CRC7 is not set
784# CONFIG_LIBCRC32C is not set
785CONFIG_ZLIB_INFLATE=y
786CONFIG_ZLIB_DEFLATE=y
787CONFIG_PLIST=y
788CONFIG_HAS_IOMEM=y
789CONFIG_HAS_IOPORT=y
790CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig
index 72a8201a5370..20ada526f6de 100644
--- a/arch/arm/configs/mx3_defconfig
+++ b/arch/arm/configs/mx3_defconfig
@@ -197,7 +197,7 @@ CONFIG_MXC_PWM=y
197# 197#
198CONFIG_CPU_32=y 198CONFIG_CPU_32=y
199CONFIG_CPU_V6=y 199CONFIG_CPU_V6=y
200CONFIG_CPU_32v6K=y 200# CONFIG_CPU_32v6K is not set
201CONFIG_CPU_32v6=y 201CONFIG_CPU_32v6=y
202CONFIG_CPU_ABRT_EV6=y 202CONFIG_CPU_ABRT_EV6=y
203CONFIG_CPU_PABRT_NOIFAR=y 203CONFIG_CPU_PABRT_NOIFAR=y
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
index 020e6a8a9e5c..5b98f7645119 100644
--- a/arch/arm/configs/orion5x_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.27-rc4 3# Linux kernel version: 2.6.30-rc4
4# Fri Aug 22 12:38:51 2008 4# Mon May 4 14:07:25 2009
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -22,8 +22,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
22# CONFIG_ARCH_HAS_ILOG2_U64 is not set 22# CONFIG_ARCH_HAS_ILOG2_U64 is not set
23CONFIG_GENERIC_HWEIGHT=y 23CONFIG_GENERIC_HWEIGHT=y
24CONFIG_GENERIC_CALIBRATE_DELAY=y 24CONFIG_GENERIC_CALIBRATE_DELAY=y
25CONFIG_ARCH_SUPPORTS_AOUT=y
26CONFIG_ZONE_DMA=y
27CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 25CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
28CONFIG_VECTORS_BASE=0xffff0000 26CONFIG_VECTORS_BASE=0xffff0000
29CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -44,10 +42,19 @@ CONFIG_SYSVIPC_SYSCTL=y
44# CONFIG_BSD_PROCESS_ACCT is not set 42# CONFIG_BSD_PROCESS_ACCT is not set
45# CONFIG_TASKSTATS is not set 43# CONFIG_TASKSTATS is not set
46# CONFIG_AUDIT is not set 44# CONFIG_AUDIT is not set
45
46#
47# RCU Subsystem
48#
49CONFIG_CLASSIC_RCU=y
50# CONFIG_TREE_RCU is not set
51# CONFIG_PREEMPT_RCU is not set
52# CONFIG_TREE_RCU_TRACE is not set
53# CONFIG_PREEMPT_RCU_TRACE is not set
47# CONFIG_IKCONFIG is not set 54# CONFIG_IKCONFIG is not set
48CONFIG_LOG_BUF_SHIFT=14 55CONFIG_LOG_BUF_SHIFT=14
49# CONFIG_CGROUPS is not set
50# CONFIG_GROUP_SCHED is not set 56# CONFIG_GROUP_SCHED is not set
57# CONFIG_CGROUPS is not set
51CONFIG_SYSFS_DEPRECATED=y 58CONFIG_SYSFS_DEPRECATED=y
52CONFIG_SYSFS_DEPRECATED_V2=y 59CONFIG_SYSFS_DEPRECATED_V2=y
53# CONFIG_RELAY is not set 60# CONFIG_RELAY is not set
@@ -55,48 +62,45 @@ CONFIG_SYSFS_DEPRECATED_V2=y
55# CONFIG_BLK_DEV_INITRD is not set 62# CONFIG_BLK_DEV_INITRD is not set
56CONFIG_CC_OPTIMIZE_FOR_SIZE=y 63CONFIG_CC_OPTIMIZE_FOR_SIZE=y
57CONFIG_SYSCTL=y 64CONFIG_SYSCTL=y
65CONFIG_ANON_INODES=y
58CONFIG_EMBEDDED=y 66CONFIG_EMBEDDED=y
59CONFIG_UID16=y 67CONFIG_UID16=y
60CONFIG_SYSCTL_SYSCALL=y 68CONFIG_SYSCTL_SYSCALL=y
61CONFIG_KALLSYMS=y 69CONFIG_KALLSYMS=y
62CONFIG_KALLSYMS_ALL=y 70CONFIG_KALLSYMS_ALL=y
63# CONFIG_KALLSYMS_EXTRA_PASS is not set 71# CONFIG_KALLSYMS_EXTRA_PASS is not set
72# CONFIG_STRIP_ASM_SYMS is not set
64CONFIG_HOTPLUG=y 73CONFIG_HOTPLUG=y
65CONFIG_PRINTK=y 74CONFIG_PRINTK=y
66CONFIG_BUG=y 75CONFIG_BUG=y
67CONFIG_ELF_CORE=y 76CONFIG_ELF_CORE=y
68CONFIG_COMPAT_BRK=y
69CONFIG_BASE_FULL=y 77CONFIG_BASE_FULL=y
70CONFIG_FUTEX=y 78CONFIG_FUTEX=y
71CONFIG_ANON_INODES=y
72CONFIG_EPOLL=y 79CONFIG_EPOLL=y
73CONFIG_SIGNALFD=y 80CONFIG_SIGNALFD=y
74CONFIG_TIMERFD=y 81CONFIG_TIMERFD=y
75CONFIG_EVENTFD=y 82CONFIG_EVENTFD=y
76CONFIG_SHMEM=y 83CONFIG_SHMEM=y
84CONFIG_AIO=y
77CONFIG_VM_EVENT_COUNTERS=y 85CONFIG_VM_EVENT_COUNTERS=y
86CONFIG_PCI_QUIRKS=y
78# CONFIG_SLUB_DEBUG is not set 87# CONFIG_SLUB_DEBUG is not set
88CONFIG_COMPAT_BRK=y
79# CONFIG_SLAB is not set 89# CONFIG_SLAB is not set
80CONFIG_SLUB=y 90CONFIG_SLUB=y
81# CONFIG_SLOB is not set 91# CONFIG_SLOB is not set
82CONFIG_PROFILING=y 92CONFIG_PROFILING=y
93CONFIG_TRACEPOINTS=y
83# CONFIG_MARKERS is not set 94# CONFIG_MARKERS is not set
84CONFIG_OPROFILE=y 95CONFIG_OPROFILE=y
85CONFIG_HAVE_OPROFILE=y 96CONFIG_HAVE_OPROFILE=y
86CONFIG_KPROBES=y 97CONFIG_KPROBES=y
87# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
88CONFIG_KRETPROBES=y 98CONFIG_KRETPROBES=y
89# CONFIG_HAVE_IOREMAP_PROT is not set
90CONFIG_HAVE_KPROBES=y 99CONFIG_HAVE_KPROBES=y
91CONFIG_HAVE_KRETPROBES=y 100CONFIG_HAVE_KRETPROBES=y
92# CONFIG_HAVE_ARCH_TRACEHOOK is not set 101# CONFIG_SLOW_WORK is not set
93# CONFIG_HAVE_DMA_ATTRS is not set
94# CONFIG_USE_GENERIC_SMP_HELPERS is not set
95# CONFIG_HAVE_CLK is not set
96CONFIG_PROC_PAGE_MONITOR=y
97CONFIG_HAVE_GENERIC_DMA_COHERENT=y 102CONFIG_HAVE_GENERIC_DMA_COHERENT=y
98CONFIG_RT_MUTEXES=y 103CONFIG_RT_MUTEXES=y
99# CONFIG_TINY_SHMEM is not set
100CONFIG_BASE_SMALL=0 104CONFIG_BASE_SMALL=0
101CONFIG_MODULES=y 105CONFIG_MODULES=y
102# CONFIG_MODULE_FORCE_LOAD is not set 106# CONFIG_MODULE_FORCE_LOAD is not set
@@ -104,11 +108,8 @@ CONFIG_MODULE_UNLOAD=y
104# CONFIG_MODULE_FORCE_UNLOAD is not set 108# CONFIG_MODULE_FORCE_UNLOAD is not set
105# CONFIG_MODVERSIONS is not set 109# CONFIG_MODVERSIONS is not set
106# CONFIG_MODULE_SRCVERSION_ALL is not set 110# CONFIG_MODULE_SRCVERSION_ALL is not set
107CONFIG_KMOD=y
108CONFIG_BLOCK=y 111CONFIG_BLOCK=y
109# CONFIG_LBD is not set 112# CONFIG_LBD is not set
110# CONFIG_BLK_DEV_IO_TRACE is not set
111# CONFIG_LSF is not set
112# CONFIG_BLK_DEV_BSG is not set 113# CONFIG_BLK_DEV_BSG is not set
113# CONFIG_BLK_DEV_INTEGRITY is not set 114# CONFIG_BLK_DEV_INTEGRITY is not set
114 115
@@ -124,7 +125,7 @@ CONFIG_IOSCHED_CFQ=y
124CONFIG_DEFAULT_CFQ=y 125CONFIG_DEFAULT_CFQ=y
125# CONFIG_DEFAULT_NOOP is not set 126# CONFIG_DEFAULT_NOOP is not set
126CONFIG_DEFAULT_IOSCHED="cfq" 127CONFIG_DEFAULT_IOSCHED="cfq"
127CONFIG_CLASSIC_RCU=y 128# CONFIG_FREEZER is not set
128 129
129# 130#
130# System Type 131# System Type
@@ -134,10 +135,10 @@ CONFIG_CLASSIC_RCU=y
134# CONFIG_ARCH_REALVIEW is not set 135# CONFIG_ARCH_REALVIEW is not set
135# CONFIG_ARCH_VERSATILE is not set 136# CONFIG_ARCH_VERSATILE is not set
136# CONFIG_ARCH_AT91 is not set 137# CONFIG_ARCH_AT91 is not set
137# CONFIG_ARCH_CLPS7500 is not set
138# CONFIG_ARCH_CLPS711X is not set 138# CONFIG_ARCH_CLPS711X is not set
139# CONFIG_ARCH_EBSA110 is not set 139# CONFIG_ARCH_EBSA110 is not set
140# CONFIG_ARCH_EP93XX is not set 140# CONFIG_ARCH_EP93XX is not set
141# CONFIG_ARCH_GEMINI is not set
141# CONFIG_ARCH_FOOTBRIDGE is not set 142# CONFIG_ARCH_FOOTBRIDGE is not set
142# CONFIG_ARCH_NETX is not set 143# CONFIG_ARCH_NETX is not set
143# CONFIG_ARCH_H720X is not set 144# CONFIG_ARCH_H720X is not set
@@ -158,14 +159,17 @@ CONFIG_CLASSIC_RCU=y
158CONFIG_ARCH_ORION5X=y 159CONFIG_ARCH_ORION5X=y
159# CONFIG_ARCH_PNX4008 is not set 160# CONFIG_ARCH_PNX4008 is not set
160# CONFIG_ARCH_PXA is not set 161# CONFIG_ARCH_PXA is not set
162# CONFIG_ARCH_MMP is not set
161# CONFIG_ARCH_RPC is not set 163# CONFIG_ARCH_RPC is not set
162# CONFIG_ARCH_SA1100 is not set 164# CONFIG_ARCH_SA1100 is not set
163# CONFIG_ARCH_S3C2410 is not set 165# CONFIG_ARCH_S3C2410 is not set
166# CONFIG_ARCH_S3C64XX is not set
164# CONFIG_ARCH_SHARK is not set 167# CONFIG_ARCH_SHARK is not set
165# CONFIG_ARCH_LH7A40X is not set 168# CONFIG_ARCH_LH7A40X is not set
166# CONFIG_ARCH_DAVINCI is not set 169# CONFIG_ARCH_DAVINCI is not set
167# CONFIG_ARCH_OMAP is not set 170# CONFIG_ARCH_OMAP is not set
168# CONFIG_ARCH_MSM7X00A is not set 171# CONFIG_ARCH_MSM is not set
172# CONFIG_ARCH_W90X900 is not set
169 173
170# 174#
171# Orion Implementations 175# Orion Implementations
@@ -175,6 +179,7 @@ CONFIG_MACH_RD88F5182=y
175CONFIG_MACH_KUROBOX_PRO=y 179CONFIG_MACH_KUROBOX_PRO=y
176CONFIG_MACH_DNS323=y 180CONFIG_MACH_DNS323=y
177CONFIG_MACH_TS209=y 181CONFIG_MACH_TS209=y
182CONFIG_MACH_TERASTATION_PRO2=y
178CONFIG_MACH_LINKSTATION_PRO=y 183CONFIG_MACH_LINKSTATION_PRO=y
179CONFIG_MACH_LINKSTATION_MINI=y 184CONFIG_MACH_LINKSTATION_MINI=y
180CONFIG_MACH_TS409=y 185CONFIG_MACH_TS409=y
@@ -187,14 +192,6 @@ CONFIG_MACH_WNR854T=y
187CONFIG_MACH_RD88F5181L_GE=y 192CONFIG_MACH_RD88F5181L_GE=y
188CONFIG_MACH_RD88F5181L_FXO=y 193CONFIG_MACH_RD88F5181L_FXO=y
189CONFIG_MACH_RD88F6183AP_GE=y 194CONFIG_MACH_RD88F6183AP_GE=y
190
191#
192# Boot options
193#
194
195#
196# Power management
197#
198CONFIG_PLAT_ORION=y 195CONFIG_PLAT_ORION=y
199 196
200# 197#
@@ -228,6 +225,8 @@ CONFIG_PCI_SYSCALL=y
228# CONFIG_ARCH_SUPPORTS_MSI is not set 225# CONFIG_ARCH_SUPPORTS_MSI is not set
229CONFIG_PCI_LEGACY=y 226CONFIG_PCI_LEGACY=y
230# CONFIG_PCI_DEBUG is not set 227# CONFIG_PCI_DEBUG is not set
228# CONFIG_PCI_STUB is not set
229# CONFIG_PCI_IOV is not set
231# CONFIG_PCCARD is not set 230# CONFIG_PCCARD is not set
232 231
233# 232#
@@ -237,25 +236,32 @@ CONFIG_TICK_ONESHOT=y
237CONFIG_NO_HZ=y 236CONFIG_NO_HZ=y
238CONFIG_HIGH_RES_TIMERS=y 237CONFIG_HIGH_RES_TIMERS=y
239CONFIG_GENERIC_CLOCKEVENTS_BUILD=y 238CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
239CONFIG_VMSPLIT_3G=y
240# CONFIG_VMSPLIT_2G is not set
241# CONFIG_VMSPLIT_1G is not set
242CONFIG_PAGE_OFFSET=0xC0000000
240CONFIG_PREEMPT=y 243CONFIG_PREEMPT=y
241CONFIG_HZ=100 244CONFIG_HZ=100
242CONFIG_AEABI=y 245CONFIG_AEABI=y
243CONFIG_OABI_COMPAT=y 246CONFIG_OABI_COMPAT=y
244# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 247CONFIG_ARCH_FLATMEM_HAS_HOLES=y
248# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
249# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
250# CONFIG_HIGHMEM is not set
245CONFIG_SELECT_MEMORY_MODEL=y 251CONFIG_SELECT_MEMORY_MODEL=y
246CONFIG_FLATMEM_MANUAL=y 252CONFIG_FLATMEM_MANUAL=y
247# CONFIG_DISCONTIGMEM_MANUAL is not set 253# CONFIG_DISCONTIGMEM_MANUAL is not set
248# CONFIG_SPARSEMEM_MANUAL is not set 254# CONFIG_SPARSEMEM_MANUAL is not set
249CONFIG_FLATMEM=y 255CONFIG_FLATMEM=y
250CONFIG_FLAT_NODE_MEM_MAP=y 256CONFIG_FLAT_NODE_MEM_MAP=y
251# CONFIG_SPARSEMEM_STATIC is not set
252# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
253CONFIG_PAGEFLAGS_EXTENDED=y 257CONFIG_PAGEFLAGS_EXTENDED=y
254CONFIG_SPLIT_PTLOCK_CPUS=4096 258CONFIG_SPLIT_PTLOCK_CPUS=4096
255# CONFIG_RESOURCES_64BIT is not set 259# CONFIG_PHYS_ADDR_T_64BIT is not set
256CONFIG_ZONE_DMA_FLAG=1 260CONFIG_ZONE_DMA_FLAG=0
257CONFIG_BOUNCE=y
258CONFIG_VIRT_TO_BUS=y 261CONFIG_VIRT_TO_BUS=y
262CONFIG_UNEVICTABLE_LRU=y
263CONFIG_HAVE_MLOCK=y
264CONFIG_HAVE_MLOCKED_PAGE_BIT=y
259CONFIG_LEDS=y 265CONFIG_LEDS=y
260CONFIG_LEDS_CPU=y 266CONFIG_LEDS_CPU=y
261CONFIG_ALIGNMENT_TRAP=y 267CONFIG_ALIGNMENT_TRAP=y
@@ -270,6 +276,11 @@ CONFIG_CMDLINE=""
270# CONFIG_KEXEC is not set 276# CONFIG_KEXEC is not set
271 277
272# 278#
279# CPU Power Management
280#
281# CONFIG_CPU_IDLE is not set
282
283#
273# Floating point emulation 284# Floating point emulation
274# 285#
275 286
@@ -285,13 +296,18 @@ CONFIG_VFP=y
285# Userspace binary formats 296# Userspace binary formats
286# 297#
287CONFIG_BINFMT_ELF=y 298CONFIG_BINFMT_ELF=y
299# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
300CONFIG_HAVE_AOUT=y
288# CONFIG_BINFMT_AOUT is not set 301# CONFIG_BINFMT_AOUT is not set
289# CONFIG_BINFMT_MISC is not set 302# CONFIG_BINFMT_MISC is not set
290 303
291# 304#
292# Power management options 305# Power management options
293# 306#
294# CONFIG_PM is not set 307CONFIG_PM=y
308# CONFIG_PM_DEBUG is not set
309# CONFIG_SUSPEND is not set
310# CONFIG_APM_EMULATION is not set
295CONFIG_ARCH_SUSPEND_POSSIBLE=y 311CONFIG_ARCH_SUSPEND_POSSIBLE=y
296CONFIG_NET=y 312CONFIG_NET=y
297 313
@@ -328,7 +344,7 @@ CONFIG_IP_PNP_BOOTP=y
328CONFIG_INET_XFRM_MODE_TRANSPORT=y 344CONFIG_INET_XFRM_MODE_TRANSPORT=y
329CONFIG_INET_XFRM_MODE_TUNNEL=y 345CONFIG_INET_XFRM_MODE_TUNNEL=y
330CONFIG_INET_XFRM_MODE_BEET=y 346CONFIG_INET_XFRM_MODE_BEET=y
331# CONFIG_INET_LRO is not set 347CONFIG_INET_LRO=y
332CONFIG_INET_DIAG=y 348CONFIG_INET_DIAG=y
333CONFIG_INET_TCP_DIAG=y 349CONFIG_INET_TCP_DIAG=y
334# CONFIG_TCP_CONG_ADVANCED is not set 350# CONFIG_TCP_CONG_ADVANCED is not set
@@ -343,6 +359,15 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
343# CONFIG_TIPC is not set 359# CONFIG_TIPC is not set
344# CONFIG_ATM is not set 360# CONFIG_ATM is not set
345# CONFIG_BRIDGE is not set 361# CONFIG_BRIDGE is not set
362CONFIG_NET_DSA=y
363CONFIG_NET_DSA_TAG_DSA=y
364CONFIG_NET_DSA_TAG_EDSA=y
365# CONFIG_NET_DSA_TAG_TRAILER is not set
366CONFIG_NET_DSA_MV88E6XXX=y
367# CONFIG_NET_DSA_MV88E6060 is not set
368CONFIG_NET_DSA_MV88E6XXX_NEED_PPU=y
369CONFIG_NET_DSA_MV88E6131=y
370CONFIG_NET_DSA_MV88E6123_61_65=y
346# CONFIG_VLAN_8021Q is not set 371# CONFIG_VLAN_8021Q is not set
347# CONFIG_DECNET is not set 372# CONFIG_DECNET is not set
348# CONFIG_LLC2 is not set 373# CONFIG_LLC2 is not set
@@ -352,27 +377,29 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
352# CONFIG_LAPB is not set 377# CONFIG_LAPB is not set
353# CONFIG_ECONET is not set 378# CONFIG_ECONET is not set
354# CONFIG_WAN_ROUTER is not set 379# CONFIG_WAN_ROUTER is not set
380# CONFIG_PHONET is not set
355# CONFIG_NET_SCHED is not set 381# CONFIG_NET_SCHED is not set
382# CONFIG_DCB is not set
356 383
357# 384#
358# Network testing 385# Network testing
359# 386#
360CONFIG_NET_PKTGEN=m 387CONFIG_NET_PKTGEN=m
361# CONFIG_NET_TCPPROBE is not set 388# CONFIG_NET_TCPPROBE is not set
389# CONFIG_NET_DROP_MONITOR is not set
362# CONFIG_HAMRADIO is not set 390# CONFIG_HAMRADIO is not set
363# CONFIG_CAN is not set 391# CONFIG_CAN is not set
364# CONFIG_IRDA is not set 392# CONFIG_IRDA is not set
365# CONFIG_BT is not set 393# CONFIG_BT is not set
366# CONFIG_AF_RXRPC is not set 394# CONFIG_AF_RXRPC is not set
367 395CONFIG_WIRELESS=y
368#
369# Wireless
370#
371# CONFIG_CFG80211 is not set 396# CONFIG_CFG80211 is not set
397# CONFIG_WIRELESS_OLD_REGULATORY is not set
372CONFIG_WIRELESS_EXT=y 398CONFIG_WIRELESS_EXT=y
373CONFIG_WIRELESS_EXT_SYSFS=y 399CONFIG_WIRELESS_EXT_SYSFS=y
400# CONFIG_LIB80211 is not set
374# CONFIG_MAC80211 is not set 401# CONFIG_MAC80211 is not set
375# CONFIG_IEEE80211 is not set 402# CONFIG_WIMAX is not set
376# CONFIG_RFKILL is not set 403# CONFIG_RFKILL is not set
377# CONFIG_NET_9P is not set 404# CONFIG_NET_9P is not set
378 405
@@ -397,6 +424,7 @@ CONFIG_MTD=y
397# CONFIG_MTD_DEBUG is not set 424# CONFIG_MTD_DEBUG is not set
398# CONFIG_MTD_CONCAT is not set 425# CONFIG_MTD_CONCAT is not set
399CONFIG_MTD_PARTITIONS=y 426CONFIG_MTD_PARTITIONS=y
427# CONFIG_MTD_TESTS is not set
400# CONFIG_MTD_REDBOOT_PARTS is not set 428# CONFIG_MTD_REDBOOT_PARTS is not set
401CONFIG_MTD_CMDLINE_PARTS=y 429CONFIG_MTD_CMDLINE_PARTS=y
402# CONFIG_MTD_AFS_PARTS is not set 430# CONFIG_MTD_AFS_PARTS is not set
@@ -450,9 +478,7 @@ CONFIG_MTD_CFI_UTIL=y
450# 478#
451# CONFIG_MTD_COMPLEX_MAPPINGS is not set 479# CONFIG_MTD_COMPLEX_MAPPINGS is not set
452CONFIG_MTD_PHYSMAP=y 480CONFIG_MTD_PHYSMAP=y
453CONFIG_MTD_PHYSMAP_START=0x0 481# CONFIG_MTD_PHYSMAP_COMPAT is not set
454CONFIG_MTD_PHYSMAP_LEN=0x0
455CONFIG_MTD_PHYSMAP_BANKWIDTH=0
456# CONFIG_MTD_ARM_INTEGRATOR is not set 482# CONFIG_MTD_ARM_INTEGRATOR is not set
457# CONFIG_MTD_IMPA7 is not set 483# CONFIG_MTD_IMPA7 is not set
458# CONFIG_MTD_INTEL_VR_NOR is not set 484# CONFIG_MTD_INTEL_VR_NOR is not set
@@ -477,6 +503,7 @@ CONFIG_MTD_NAND=y
477CONFIG_MTD_NAND_VERIFY_WRITE=y 503CONFIG_MTD_NAND_VERIFY_WRITE=y
478# CONFIG_MTD_NAND_ECC_SMC is not set 504# CONFIG_MTD_NAND_ECC_SMC is not set
479# CONFIG_MTD_NAND_MUSEUM_IDS is not set 505# CONFIG_MTD_NAND_MUSEUM_IDS is not set
506# CONFIG_MTD_NAND_GPIO is not set
480CONFIG_MTD_NAND_IDS=y 507CONFIG_MTD_NAND_IDS=y
481# CONFIG_MTD_NAND_DISKONCHIP is not set 508# CONFIG_MTD_NAND_DISKONCHIP is not set
482# CONFIG_MTD_NAND_CAFE is not set 509# CONFIG_MTD_NAND_CAFE is not set
@@ -487,6 +514,11 @@ CONFIG_MTD_NAND_ORION=y
487# CONFIG_MTD_ONENAND is not set 514# CONFIG_MTD_ONENAND is not set
488 515
489# 516#
517# LPDDR flash memory drivers
518#
519# CONFIG_MTD_LPDDR is not set
520
521#
490# UBI - Unsorted block images 522# UBI - Unsorted block images
491# 523#
492# CONFIG_MTD_UBI is not set 524# CONFIG_MTD_UBI is not set
@@ -507,11 +539,20 @@ CONFIG_BLK_DEV_LOOP=y
507# CONFIG_ATA_OVER_ETH is not set 539# CONFIG_ATA_OVER_ETH is not set
508CONFIG_MISC_DEVICES=y 540CONFIG_MISC_DEVICES=y
509# CONFIG_PHANTOM is not set 541# CONFIG_PHANTOM is not set
510# CONFIG_EEPROM_93CX6 is not set
511# CONFIG_SGI_IOC4 is not set 542# CONFIG_SGI_IOC4 is not set
512# CONFIG_TIFM_CORE is not set 543# CONFIG_TIFM_CORE is not set
544# CONFIG_ICS932S401 is not set
513# CONFIG_ENCLOSURE_SERVICES is not set 545# CONFIG_ENCLOSURE_SERVICES is not set
514# CONFIG_HP_ILO is not set 546# CONFIG_HP_ILO is not set
547# CONFIG_ISL29003 is not set
548# CONFIG_C2PORT is not set
549
550#
551# EEPROM support
552#
553# CONFIG_EEPROM_AT24 is not set
554# CONFIG_EEPROM_LEGACY is not set
555# CONFIG_EEPROM_93CX6 is not set
515CONFIG_HAVE_IDE=y 556CONFIG_HAVE_IDE=y
516# CONFIG_IDE is not set 557# CONFIG_IDE is not set
517 558
@@ -569,7 +610,11 @@ CONFIG_SCSI_LOWLEVEL=y
569# CONFIG_MEGARAID_NEWGEN is not set 610# CONFIG_MEGARAID_NEWGEN is not set
570# CONFIG_MEGARAID_LEGACY is not set 611# CONFIG_MEGARAID_LEGACY is not set
571# CONFIG_MEGARAID_SAS is not set 612# CONFIG_MEGARAID_SAS is not set
613# CONFIG_SCSI_MPT2SAS is not set
572# CONFIG_SCSI_HPTIOP is not set 614# CONFIG_SCSI_HPTIOP is not set
615# CONFIG_LIBFC is not set
616# CONFIG_LIBFCOE is not set
617# CONFIG_FCOE is not set
573# CONFIG_SCSI_DMX3191D is not set 618# CONFIG_SCSI_DMX3191D is not set
574# CONFIG_SCSI_FUTURE_DOMAIN is not set 619# CONFIG_SCSI_FUTURE_DOMAIN is not set
575# CONFIG_SCSI_IPS is not set 620# CONFIG_SCSI_IPS is not set
@@ -589,6 +634,7 @@ CONFIG_SCSI_LOWLEVEL=y
589# CONFIG_SCSI_DEBUG is not set 634# CONFIG_SCSI_DEBUG is not set
590# CONFIG_SCSI_SRP is not set 635# CONFIG_SCSI_SRP is not set
591# CONFIG_SCSI_DH is not set 636# CONFIG_SCSI_DH is not set
637# CONFIG_SCSI_OSD_INITIATOR is not set
592CONFIG_ATA=y 638CONFIG_ATA=y
593# CONFIG_ATA_NONSTANDARD is not set 639# CONFIG_ATA_NONSTANDARD is not set
594CONFIG_SATA_PMP=y 640CONFIG_SATA_PMP=y
@@ -663,6 +709,7 @@ CONFIG_SATA_MV=y
663# CONFIG_IEEE1394 is not set 709# CONFIG_IEEE1394 is not set
664# CONFIG_I2O is not set 710# CONFIG_I2O is not set
665CONFIG_NETDEVICES=y 711CONFIG_NETDEVICES=y
712CONFIG_COMPAT_NET_DEV_OPS=y
666# CONFIG_DUMMY is not set 713# CONFIG_DUMMY is not set
667# CONFIG_BONDING is not set 714# CONFIG_BONDING is not set
668# CONFIG_MACVLAN is not set 715# CONFIG_MACVLAN is not set
@@ -670,7 +717,26 @@ CONFIG_NETDEVICES=y
670# CONFIG_TUN is not set 717# CONFIG_TUN is not set
671# CONFIG_VETH is not set 718# CONFIG_VETH is not set
672# CONFIG_ARCNET is not set 719# CONFIG_ARCNET is not set
673# CONFIG_PHYLIB is not set 720CONFIG_PHYLIB=y
721
722#
723# MII PHY device drivers
724#
725CONFIG_MARVELL_PHY=y
726# CONFIG_DAVICOM_PHY is not set
727# CONFIG_QSEMI_PHY is not set
728# CONFIG_LXT_PHY is not set
729# CONFIG_CICADA_PHY is not set
730# CONFIG_VITESSE_PHY is not set
731# CONFIG_SMSC_PHY is not set
732# CONFIG_BROADCOM_PHY is not set
733# CONFIG_ICPLUS_PHY is not set
734# CONFIG_REALTEK_PHY is not set
735# CONFIG_NATIONAL_PHY is not set
736# CONFIG_STE10XP is not set
737# CONFIG_LSI_ET1011C_PHY is not set
738# CONFIG_FIXED_PHY is not set
739# CONFIG_MDIO_BITBANG is not set
674CONFIG_NET_ETHERNET=y 740CONFIG_NET_ETHERNET=y
675CONFIG_MII=y 741CONFIG_MII=y
676# CONFIG_AX88796 is not set 742# CONFIG_AX88796 is not set
@@ -680,19 +746,25 @@ CONFIG_MII=y
680# CONFIG_NET_VENDOR_3COM is not set 746# CONFIG_NET_VENDOR_3COM is not set
681# CONFIG_SMC91X is not set 747# CONFIG_SMC91X is not set
682# CONFIG_DM9000 is not set 748# CONFIG_DM9000 is not set
749# CONFIG_ETHOC is not set
750# CONFIG_SMC911X is not set
751# CONFIG_SMSC911X is not set
752# CONFIG_DNET is not set
683# CONFIG_NET_TULIP is not set 753# CONFIG_NET_TULIP is not set
684# CONFIG_HP100 is not set 754# CONFIG_HP100 is not set
685# CONFIG_IBM_NEW_EMAC_ZMII is not set 755# CONFIG_IBM_NEW_EMAC_ZMII is not set
686# CONFIG_IBM_NEW_EMAC_RGMII is not set 756# CONFIG_IBM_NEW_EMAC_RGMII is not set
687# CONFIG_IBM_NEW_EMAC_TAH is not set 757# CONFIG_IBM_NEW_EMAC_TAH is not set
688# CONFIG_IBM_NEW_EMAC_EMAC4 is not set 758# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
759# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
760# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
761# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
689CONFIG_NET_PCI=y 762CONFIG_NET_PCI=y
690# CONFIG_PCNET32 is not set 763# CONFIG_PCNET32 is not set
691# CONFIG_AMD8111_ETH is not set 764# CONFIG_AMD8111_ETH is not set
692# CONFIG_ADAPTEC_STARFIRE is not set 765# CONFIG_ADAPTEC_STARFIRE is not set
693# CONFIG_B44 is not set 766# CONFIG_B44 is not set
694# CONFIG_FORCEDETH is not set 767# CONFIG_FORCEDETH is not set
695# CONFIG_EEPRO100 is not set
696# CONFIG_E100 is not set 768# CONFIG_E100 is not set
697# CONFIG_FEALNX is not set 769# CONFIG_FEALNX is not set
698# CONFIG_NATSEMI is not set 770# CONFIG_NATSEMI is not set
@@ -702,10 +774,12 @@ CONFIG_NET_PCI=y
702# CONFIG_R6040 is not set 774# CONFIG_R6040 is not set
703# CONFIG_SIS900 is not set 775# CONFIG_SIS900 is not set
704# CONFIG_EPIC100 is not set 776# CONFIG_EPIC100 is not set
777# CONFIG_SMSC9420 is not set
705# CONFIG_SUNDANCE is not set 778# CONFIG_SUNDANCE is not set
706# CONFIG_TLAN is not set 779# CONFIG_TLAN is not set
707# CONFIG_VIA_RHINE is not set 780# CONFIG_VIA_RHINE is not set
708# CONFIG_SC92031 is not set 781# CONFIG_SC92031 is not set
782# CONFIG_ATL2 is not set
709CONFIG_NETDEV_1000=y 783CONFIG_NETDEV_1000=y
710# CONFIG_ACENIC is not set 784# CONFIG_ACENIC is not set
711# CONFIG_DL2K is not set 785# CONFIG_DL2K is not set
@@ -713,6 +787,7 @@ CONFIG_NETDEV_1000=y
713# CONFIG_E1000E is not set 787# CONFIG_E1000E is not set
714# CONFIG_IP1000 is not set 788# CONFIG_IP1000 is not set
715# CONFIG_IGB is not set 789# CONFIG_IGB is not set
790# CONFIG_IGBVF is not set
716# CONFIG_NS83820 is not set 791# CONFIG_NS83820 is not set
717# CONFIG_HAMACHI is not set 792# CONFIG_HAMACHI is not set
718# CONFIG_YELLOWFIN is not set 793# CONFIG_YELLOWFIN is not set
@@ -727,6 +802,8 @@ CONFIG_MV643XX_ETH=y
727# CONFIG_QLA3XXX is not set 802# CONFIG_QLA3XXX is not set
728# CONFIG_ATL1 is not set 803# CONFIG_ATL1 is not set
729# CONFIG_ATL1E is not set 804# CONFIG_ATL1E is not set
805# CONFIG_ATL1C is not set
806# CONFIG_JME is not set
730# CONFIG_NETDEV_10000 is not set 807# CONFIG_NETDEV_10000 is not set
731# CONFIG_TR is not set 808# CONFIG_TR is not set
732 809
@@ -735,7 +812,10 @@ CONFIG_MV643XX_ETH=y
735# 812#
736# CONFIG_WLAN_PRE80211 is not set 813# CONFIG_WLAN_PRE80211 is not set
737# CONFIG_WLAN_80211 is not set 814# CONFIG_WLAN_80211 is not set
738# CONFIG_IWLWIFI_LEDS is not set 815
816#
817# Enable WiMAX (Networking options) to see the WiMAX drivers
818#
739 819
740# 820#
741# USB Network Adapters 821# USB Network Adapters
@@ -819,11 +899,11 @@ CONFIG_SERIAL_CORE=y
819CONFIG_SERIAL_CORE_CONSOLE=y 899CONFIG_SERIAL_CORE_CONSOLE=y
820# CONFIG_SERIAL_JSM is not set 900# CONFIG_SERIAL_JSM is not set
821CONFIG_UNIX98_PTYS=y 901CONFIG_UNIX98_PTYS=y
902# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
822CONFIG_LEGACY_PTYS=y 903CONFIG_LEGACY_PTYS=y
823CONFIG_LEGACY_PTY_COUNT=16 904CONFIG_LEGACY_PTY_COUNT=16
824# CONFIG_IPMI_HANDLER is not set 905# CONFIG_IPMI_HANDLER is not set
825# CONFIG_HW_RANDOM is not set 906# CONFIG_HW_RANDOM is not set
826# CONFIG_NVRAM is not set
827# CONFIG_R3964 is not set 907# CONFIG_R3964 is not set
828# CONFIG_APPLICOM is not set 908# CONFIG_APPLICOM is not set
829# CONFIG_RAW_DRIVER is not set 909# CONFIG_RAW_DRIVER is not set
@@ -886,12 +966,9 @@ CONFIG_I2C_MV64XXX=y
886# Miscellaneous I2C Chip support 966# Miscellaneous I2C Chip support
887# 967#
888# CONFIG_DS1682 is not set 968# CONFIG_DS1682 is not set
889# CONFIG_EEPROM_AT24 is not set
890# CONFIG_EEPROM_LEGACY is not set
891# CONFIG_SENSORS_PCF8574 is not set 969# CONFIG_SENSORS_PCF8574 is not set
892# CONFIG_PCF8575 is not set 970# CONFIG_PCF8575 is not set
893# CONFIG_SENSORS_PCA9539 is not set 971# CONFIG_SENSORS_PCA9539 is not set
894# CONFIG_SENSORS_PCF8591 is not set
895# CONFIG_SENSORS_MAX6875 is not set 972# CONFIG_SENSORS_MAX6875 is not set
896# CONFIG_SENSORS_TSL2550 is not set 973# CONFIG_SENSORS_TSL2550 is not set
897# CONFIG_I2C_DEBUG_CORE is not set 974# CONFIG_I2C_DEBUG_CORE is not set
@@ -911,14 +988,17 @@ CONFIG_HWMON=y
911# CONFIG_SENSORS_ADM1029 is not set 988# CONFIG_SENSORS_ADM1029 is not set
912# CONFIG_SENSORS_ADM1031 is not set 989# CONFIG_SENSORS_ADM1031 is not set
913# CONFIG_SENSORS_ADM9240 is not set 990# CONFIG_SENSORS_ADM9240 is not set
991# CONFIG_SENSORS_ADT7462 is not set
914# CONFIG_SENSORS_ADT7470 is not set 992# CONFIG_SENSORS_ADT7470 is not set
915# CONFIG_SENSORS_ADT7473 is not set 993# CONFIG_SENSORS_ADT7473 is not set
994# CONFIG_SENSORS_ADT7475 is not set
916# CONFIG_SENSORS_ATXP1 is not set 995# CONFIG_SENSORS_ATXP1 is not set
917# CONFIG_SENSORS_DS1621 is not set 996# CONFIG_SENSORS_DS1621 is not set
918# CONFIG_SENSORS_I5K_AMB is not set 997# CONFIG_SENSORS_I5K_AMB is not set
919# CONFIG_SENSORS_F71805F is not set 998# CONFIG_SENSORS_F71805F is not set
920# CONFIG_SENSORS_F71882FG is not set 999# CONFIG_SENSORS_F71882FG is not set
921# CONFIG_SENSORS_F75375S is not set 1000# CONFIG_SENSORS_F75375S is not set
1001# CONFIG_SENSORS_G760A is not set
922# CONFIG_SENSORS_GL518SM is not set 1002# CONFIG_SENSORS_GL518SM is not set
923# CONFIG_SENSORS_GL520SM is not set 1003# CONFIG_SENSORS_GL520SM is not set
924# CONFIG_SENSORS_IT87 is not set 1004# CONFIG_SENSORS_IT87 is not set
@@ -933,10 +1013,15 @@ CONFIG_SENSORS_LM75=y
933# CONFIG_SENSORS_LM90 is not set 1013# CONFIG_SENSORS_LM90 is not set
934# CONFIG_SENSORS_LM92 is not set 1014# CONFIG_SENSORS_LM92 is not set
935# CONFIG_SENSORS_LM93 is not set 1015# CONFIG_SENSORS_LM93 is not set
1016# CONFIG_SENSORS_LTC4215 is not set
1017# CONFIG_SENSORS_LTC4245 is not set
1018# CONFIG_SENSORS_LM95241 is not set
936# CONFIG_SENSORS_MAX1619 is not set 1019# CONFIG_SENSORS_MAX1619 is not set
937# CONFIG_SENSORS_MAX6650 is not set 1020# CONFIG_SENSORS_MAX6650 is not set
938# CONFIG_SENSORS_PC87360 is not set 1021# CONFIG_SENSORS_PC87360 is not set
939# CONFIG_SENSORS_PC87427 is not set 1022# CONFIG_SENSORS_PC87427 is not set
1023# CONFIG_SENSORS_PCF8591 is not set
1024# CONFIG_SENSORS_SHT15 is not set
940# CONFIG_SENSORS_SIS5595 is not set 1025# CONFIG_SENSORS_SIS5595 is not set
941# CONFIG_SENSORS_DME1737 is not set 1026# CONFIG_SENSORS_DME1737 is not set
942# CONFIG_SENSORS_SMSC47M1 is not set 1027# CONFIG_SENSORS_SMSC47M1 is not set
@@ -956,12 +1041,14 @@ CONFIG_SENSORS_LM75=y
956# CONFIG_SENSORS_W83627HF is not set 1041# CONFIG_SENSORS_W83627HF is not set
957# CONFIG_SENSORS_W83627EHF is not set 1042# CONFIG_SENSORS_W83627EHF is not set
958# CONFIG_HWMON_DEBUG_CHIP is not set 1043# CONFIG_HWMON_DEBUG_CHIP is not set
1044# CONFIG_THERMAL is not set
1045# CONFIG_THERMAL_HWMON is not set
959# CONFIG_WATCHDOG is not set 1046# CONFIG_WATCHDOG is not set
1047CONFIG_SSB_POSSIBLE=y
960 1048
961# 1049#
962# Sonics Silicon Backplane 1050# Sonics Silicon Backplane
963# 1051#
964CONFIG_SSB_POSSIBLE=y
965# CONFIG_SSB is not set 1052# CONFIG_SSB is not set
966 1053
967# 1054#
@@ -970,9 +1057,12 @@ CONFIG_SSB_POSSIBLE=y
970# CONFIG_MFD_CORE is not set 1057# CONFIG_MFD_CORE is not set
971# CONFIG_MFD_SM501 is not set 1058# CONFIG_MFD_SM501 is not set
972# CONFIG_HTC_PASIC3 is not set 1059# CONFIG_HTC_PASIC3 is not set
1060# CONFIG_TWL4030_CORE is not set
973# CONFIG_MFD_TMIO is not set 1061# CONFIG_MFD_TMIO is not set
974# CONFIG_MFD_T7L66XB is not set 1062# CONFIG_PMIC_DA903X is not set
975# CONFIG_MFD_TC6387XB is not set 1063# CONFIG_MFD_WM8400 is not set
1064# CONFIG_MFD_WM8350_I2C is not set
1065# CONFIG_MFD_PCF50633 is not set
976 1066
977# 1067#
978# Multimedia devices 1068# Multimedia devices
@@ -1013,9 +1103,36 @@ CONFIG_HID=y
1013# USB Input Devices 1103# USB Input Devices
1014# 1104#
1015CONFIG_USB_HID=y 1105CONFIG_USB_HID=y
1016# CONFIG_USB_HIDINPUT_POWERBOOK is not set 1106# CONFIG_HID_PID is not set
1017# CONFIG_HID_FF is not set
1018# CONFIG_USB_HIDDEV is not set 1107# CONFIG_USB_HIDDEV is not set
1108
1109#
1110# Special HID drivers
1111#
1112# CONFIG_HID_A4TECH is not set
1113# CONFIG_HID_APPLE is not set
1114# CONFIG_HID_BELKIN is not set
1115# CONFIG_HID_CHERRY is not set
1116# CONFIG_HID_CHICONY is not set
1117# CONFIG_HID_CYPRESS is not set
1118# CONFIG_DRAGONRISE_FF is not set
1119# CONFIG_HID_EZKEY is not set
1120# CONFIG_HID_KYE is not set
1121# CONFIG_HID_GYRATION is not set
1122# CONFIG_HID_KENSINGTON is not set
1123# CONFIG_HID_LOGITECH is not set
1124# CONFIG_HID_MICROSOFT is not set
1125# CONFIG_HID_MONTEREY is not set
1126# CONFIG_HID_NTRIG is not set
1127# CONFIG_HID_PANTHERLORD is not set
1128# CONFIG_HID_PETALYNX is not set
1129# CONFIG_HID_SAMSUNG is not set
1130# CONFIG_HID_SONY is not set
1131# CONFIG_HID_SUNPLUS is not set
1132# CONFIG_GREENASIA_FF is not set
1133# CONFIG_HID_TOPSEED is not set
1134# CONFIG_THRUSTMASTER_FF is not set
1135# CONFIG_ZEROPLUS_FF is not set
1019CONFIG_USB_SUPPORT=y 1136CONFIG_USB_SUPPORT=y
1020CONFIG_USB_ARCH_HAS_HCD=y 1137CONFIG_USB_ARCH_HAS_HCD=y
1021CONFIG_USB_ARCH_HAS_OHCI=y 1138CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1030,10 +1147,13 @@ CONFIG_USB=y
1030CONFIG_USB_DEVICEFS=y 1147CONFIG_USB_DEVICEFS=y
1031CONFIG_USB_DEVICE_CLASS=y 1148CONFIG_USB_DEVICE_CLASS=y
1032# CONFIG_USB_DYNAMIC_MINORS is not set 1149# CONFIG_USB_DYNAMIC_MINORS is not set
1150# CONFIG_USB_SUSPEND is not set
1033# CONFIG_USB_OTG is not set 1151# CONFIG_USB_OTG is not set
1034# CONFIG_USB_OTG_WHITELIST is not set 1152# CONFIG_USB_OTG_WHITELIST is not set
1035# CONFIG_USB_OTG_BLACKLIST_HUB is not set 1153# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1036# CONFIG_USB_MON is not set 1154# CONFIG_USB_MON is not set
1155# CONFIG_USB_WUSB is not set
1156# CONFIG_USB_WUSB_CBAF is not set
1037 1157
1038# 1158#
1039# USB Host Controller Drivers 1159# USB Host Controller Drivers
@@ -1042,12 +1162,15 @@ CONFIG_USB_DEVICE_CLASS=y
1042CONFIG_USB_EHCI_HCD=y 1162CONFIG_USB_EHCI_HCD=y
1043CONFIG_USB_EHCI_ROOT_HUB_TT=y 1163CONFIG_USB_EHCI_ROOT_HUB_TT=y
1044CONFIG_USB_EHCI_TT_NEWSCHED=y 1164CONFIG_USB_EHCI_TT_NEWSCHED=y
1165# CONFIG_USB_OXU210HP_HCD is not set
1045# CONFIG_USB_ISP116X_HCD is not set 1166# CONFIG_USB_ISP116X_HCD is not set
1046# CONFIG_USB_ISP1760_HCD is not set 1167# CONFIG_USB_ISP1760_HCD is not set
1047# CONFIG_USB_OHCI_HCD is not set 1168# CONFIG_USB_OHCI_HCD is not set
1048# CONFIG_USB_UHCI_HCD is not set 1169# CONFIG_USB_UHCI_HCD is not set
1049# CONFIG_USB_SL811_HCD is not set 1170# CONFIG_USB_SL811_HCD is not set
1050# CONFIG_USB_R8A66597_HCD is not set 1171# CONFIG_USB_R8A66597_HCD is not set
1172# CONFIG_USB_WHCI_HCD is not set
1173# CONFIG_USB_HWA_HCD is not set
1051 1174
1052# 1175#
1053# USB Device Class drivers 1176# USB Device Class drivers
@@ -1055,20 +1178,20 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y
1055# CONFIG_USB_ACM is not set 1178# CONFIG_USB_ACM is not set
1056CONFIG_USB_PRINTER=y 1179CONFIG_USB_PRINTER=y
1057# CONFIG_USB_WDM is not set 1180# CONFIG_USB_WDM is not set
1181# CONFIG_USB_TMC is not set
1058 1182
1059# 1183#
1060# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1184# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1061# 1185#
1062 1186
1063# 1187#
1064# may also be needed; see USB_STORAGE Help for more information 1188# also be needed; see USB_STORAGE Help for more info
1065# 1189#
1066CONFIG_USB_STORAGE=y 1190CONFIG_USB_STORAGE=y
1067# CONFIG_USB_STORAGE_DEBUG is not set 1191# CONFIG_USB_STORAGE_DEBUG is not set
1068CONFIG_USB_STORAGE_DATAFAB=y 1192CONFIG_USB_STORAGE_DATAFAB=y
1069CONFIG_USB_STORAGE_FREECOM=y 1193CONFIG_USB_STORAGE_FREECOM=y
1070# CONFIG_USB_STORAGE_ISD200 is not set 1194# CONFIG_USB_STORAGE_ISD200 is not set
1071CONFIG_USB_STORAGE_DPCM=y
1072# CONFIG_USB_STORAGE_USBAT is not set 1195# CONFIG_USB_STORAGE_USBAT is not set
1073CONFIG_USB_STORAGE_SDDR09=y 1196CONFIG_USB_STORAGE_SDDR09=y
1074CONFIG_USB_STORAGE_SDDR55=y 1197CONFIG_USB_STORAGE_SDDR55=y
@@ -1076,7 +1199,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1076# CONFIG_USB_STORAGE_ALAUDA is not set 1199# CONFIG_USB_STORAGE_ALAUDA is not set
1077# CONFIG_USB_STORAGE_ONETOUCH is not set 1200# CONFIG_USB_STORAGE_ONETOUCH is not set
1078# CONFIG_USB_STORAGE_KARMA is not set 1201# CONFIG_USB_STORAGE_KARMA is not set
1079# CONFIG_USB_STORAGE_SIERRA is not set
1080# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 1202# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1081# CONFIG_USB_LIBUSUAL is not set 1203# CONFIG_USB_LIBUSUAL is not set
1082 1204
@@ -1097,6 +1219,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1097# CONFIG_USB_EMI62 is not set 1219# CONFIG_USB_EMI62 is not set
1098# CONFIG_USB_EMI26 is not set 1220# CONFIG_USB_EMI26 is not set
1099# CONFIG_USB_ADUTUX is not set 1221# CONFIG_USB_ADUTUX is not set
1222# CONFIG_USB_SEVSEG is not set
1100# CONFIG_USB_RIO500 is not set 1223# CONFIG_USB_RIO500 is not set
1101# CONFIG_USB_LEGOTOWER is not set 1224# CONFIG_USB_LEGOTOWER is not set
1102# CONFIG_USB_LCD is not set 1225# CONFIG_USB_LCD is not set
@@ -1104,7 +1227,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1104# CONFIG_USB_LED is not set 1227# CONFIG_USB_LED is not set
1105# CONFIG_USB_CYPRESS_CY7C63 is not set 1228# CONFIG_USB_CYPRESS_CY7C63 is not set
1106# CONFIG_USB_CYTHERM is not set 1229# CONFIG_USB_CYTHERM is not set
1107# CONFIG_USB_PHIDGET is not set
1108# CONFIG_USB_IDMOUSE is not set 1230# CONFIG_USB_IDMOUSE is not set
1109# CONFIG_USB_FTDI_ELAN is not set 1231# CONFIG_USB_FTDI_ELAN is not set
1110# CONFIG_USB_APPLEDISPLAY is not set 1232# CONFIG_USB_APPLEDISPLAY is not set
@@ -1114,8 +1236,18 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1114# CONFIG_USB_IOWARRIOR is not set 1236# CONFIG_USB_IOWARRIOR is not set
1115# CONFIG_USB_TEST is not set 1237# CONFIG_USB_TEST is not set
1116# CONFIG_USB_ISIGHTFW is not set 1238# CONFIG_USB_ISIGHTFW is not set
1239# CONFIG_USB_VST is not set
1117# CONFIG_USB_GADGET is not set 1240# CONFIG_USB_GADGET is not set
1241
1242#
1243# OTG and related infrastructure
1244#
1245# CONFIG_USB_GPIO_VBUS is not set
1246# CONFIG_NOP_USB_XCEIV is not set
1247# CONFIG_UWB is not set
1118# CONFIG_MMC is not set 1248# CONFIG_MMC is not set
1249# CONFIG_MEMSTICK is not set
1250# CONFIG_ACCESSIBILITY is not set
1119CONFIG_NEW_LEDS=y 1251CONFIG_NEW_LEDS=y
1120CONFIG_LEDS_CLASS=y 1252CONFIG_LEDS_CLASS=y
1121 1253
@@ -1124,7 +1256,10 @@ CONFIG_LEDS_CLASS=y
1124# 1256#
1125# CONFIG_LEDS_PCA9532 is not set 1257# CONFIG_LEDS_PCA9532 is not set
1126CONFIG_LEDS_GPIO=y 1258CONFIG_LEDS_GPIO=y
1259CONFIG_LEDS_GPIO_PLATFORM=y
1260# CONFIG_LEDS_LP5521 is not set
1127# CONFIG_LEDS_PCA955X is not set 1261# CONFIG_LEDS_PCA955X is not set
1262# CONFIG_LEDS_BD2802 is not set
1128 1263
1129# 1264#
1130# LED Triggers 1265# LED Triggers
@@ -1132,7 +1267,12 @@ CONFIG_LEDS_GPIO=y
1132CONFIG_LEDS_TRIGGERS=y 1267CONFIG_LEDS_TRIGGERS=y
1133CONFIG_LEDS_TRIGGER_TIMER=y 1268CONFIG_LEDS_TRIGGER_TIMER=y
1134CONFIG_LEDS_TRIGGER_HEARTBEAT=y 1269CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1270# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
1135CONFIG_LEDS_TRIGGER_DEFAULT_ON=y 1271CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
1272
1273#
1274# iptables trigger is under Netfilter config (LED target)
1275#
1136CONFIG_RTC_LIB=y 1276CONFIG_RTC_LIB=y
1137CONFIG_RTC_CLASS=y 1277CONFIG_RTC_CLASS=y
1138CONFIG_RTC_HCTOSYS=y 1278CONFIG_RTC_HCTOSYS=y
@@ -1164,6 +1304,7 @@ CONFIG_RTC_DRV_M41T80=y
1164# CONFIG_RTC_DRV_M41T80_WDT is not set 1304# CONFIG_RTC_DRV_M41T80_WDT is not set
1165CONFIG_RTC_DRV_S35390A=y 1305CONFIG_RTC_DRV_S35390A=y
1166# CONFIG_RTC_DRV_FM3130 is not set 1306# CONFIG_RTC_DRV_FM3130 is not set
1307# CONFIG_RTC_DRV_RX8581 is not set
1167 1308
1168# 1309#
1169# SPI RTC drivers 1310# SPI RTC drivers
@@ -1173,12 +1314,15 @@ CONFIG_RTC_DRV_S35390A=y
1173# Platform RTC drivers 1314# Platform RTC drivers
1174# 1315#
1175# CONFIG_RTC_DRV_CMOS is not set 1316# CONFIG_RTC_DRV_CMOS is not set
1317# CONFIG_RTC_DRV_DS1286 is not set
1176# CONFIG_RTC_DRV_DS1511 is not set 1318# CONFIG_RTC_DRV_DS1511 is not set
1177# CONFIG_RTC_DRV_DS1553 is not set 1319# CONFIG_RTC_DRV_DS1553 is not set
1178# CONFIG_RTC_DRV_DS1742 is not set 1320# CONFIG_RTC_DRV_DS1742 is not set
1179# CONFIG_RTC_DRV_STK17TA8 is not set 1321# CONFIG_RTC_DRV_STK17TA8 is not set
1180CONFIG_RTC_DRV_M48T86=y 1322CONFIG_RTC_DRV_M48T86=y
1323# CONFIG_RTC_DRV_M48T35 is not set
1181# CONFIG_RTC_DRV_M48T59 is not set 1324# CONFIG_RTC_DRV_M48T59 is not set
1325# CONFIG_RTC_DRV_BQ4802 is not set
1182# CONFIG_RTC_DRV_V3020 is not set 1326# CONFIG_RTC_DRV_V3020 is not set
1183 1327
1184# 1328#
@@ -1196,16 +1340,12 @@ CONFIG_DMA_ENGINE=y
1196# DMA Clients 1340# DMA Clients
1197# 1341#
1198# CONFIG_NET_DMA is not set 1342# CONFIG_NET_DMA is not set
1343# CONFIG_ASYNC_TX_DMA is not set
1199# CONFIG_DMATEST is not set 1344# CONFIG_DMATEST is not set
1200 1345# CONFIG_AUXDISPLAY is not set
1201#
1202# Voltage and Current regulators
1203#
1204# CONFIG_REGULATOR is not set 1346# CONFIG_REGULATOR is not set
1205# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
1206# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
1207# CONFIG_REGULATOR_BQ24022 is not set
1208# CONFIG_UIO is not set 1347# CONFIG_UIO is not set
1348# CONFIG_STAGING is not set
1209 1349
1210# 1350#
1211# File systems 1351# File systems
@@ -1214,14 +1354,25 @@ CONFIG_EXT2_FS=y
1214# CONFIG_EXT2_FS_XATTR is not set 1354# CONFIG_EXT2_FS_XATTR is not set
1215# CONFIG_EXT2_FS_XIP is not set 1355# CONFIG_EXT2_FS_XIP is not set
1216CONFIG_EXT3_FS=y 1356CONFIG_EXT3_FS=y
1357# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1217# CONFIG_EXT3_FS_XATTR is not set 1358# CONFIG_EXT3_FS_XATTR is not set
1218# CONFIG_EXT4DEV_FS is not set 1359CONFIG_EXT4_FS=m
1360# CONFIG_EXT4DEV_COMPAT is not set
1361CONFIG_EXT4_FS_XATTR=y
1362# CONFIG_EXT4_FS_POSIX_ACL is not set
1363# CONFIG_EXT4_FS_SECURITY is not set
1219CONFIG_JBD=y 1364CONFIG_JBD=y
1365# CONFIG_JBD_DEBUG is not set
1366CONFIG_JBD2=m
1367# CONFIG_JBD2_DEBUG is not set
1368CONFIG_FS_MBCACHE=m
1220# CONFIG_REISERFS_FS is not set 1369# CONFIG_REISERFS_FS is not set
1221# CONFIG_JFS_FS is not set 1370# CONFIG_JFS_FS is not set
1222# CONFIG_FS_POSIX_ACL is not set 1371# CONFIG_FS_POSIX_ACL is not set
1372CONFIG_FILE_LOCKING=y
1223# CONFIG_XFS_FS is not set 1373# CONFIG_XFS_FS is not set
1224# CONFIG_OCFS2_FS is not set 1374# CONFIG_OCFS2_FS is not set
1375# CONFIG_BTRFS_FS is not set
1225CONFIG_DNOTIFY=y 1376CONFIG_DNOTIFY=y
1226CONFIG_INOTIFY=y 1377CONFIG_INOTIFY=y
1227CONFIG_INOTIFY_USER=y 1378CONFIG_INOTIFY_USER=y
@@ -1231,6 +1382,11 @@ CONFIG_INOTIFY_USER=y
1231# CONFIG_FUSE_FS is not set 1382# CONFIG_FUSE_FS is not set
1232 1383
1233# 1384#
1385# Caches
1386#
1387# CONFIG_FSCACHE is not set
1388
1389#
1234# CD-ROM/DVD Filesystems 1390# CD-ROM/DVD Filesystems
1235# 1391#
1236CONFIG_ISO9660_FS=m 1392CONFIG_ISO9660_FS=m
@@ -1254,15 +1410,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1254# 1410#
1255CONFIG_PROC_FS=y 1411CONFIG_PROC_FS=y
1256CONFIG_PROC_SYSCTL=y 1412CONFIG_PROC_SYSCTL=y
1413CONFIG_PROC_PAGE_MONITOR=y
1257CONFIG_SYSFS=y 1414CONFIG_SYSFS=y
1258CONFIG_TMPFS=y 1415CONFIG_TMPFS=y
1259# CONFIG_TMPFS_POSIX_ACL is not set 1416# CONFIG_TMPFS_POSIX_ACL is not set
1260# CONFIG_HUGETLB_PAGE is not set 1417# CONFIG_HUGETLB_PAGE is not set
1261# CONFIG_CONFIGFS_FS is not set 1418# CONFIG_CONFIGFS_FS is not set
1262 1419CONFIG_MISC_FILESYSTEMS=y
1263#
1264# Miscellaneous filesystems
1265#
1266# CONFIG_ADFS_FS is not set 1420# CONFIG_ADFS_FS is not set
1267# CONFIG_AFFS_FS is not set 1421# CONFIG_AFFS_FS is not set
1268# CONFIG_HFS_FS is not set 1422# CONFIG_HFS_FS is not set
@@ -1282,6 +1436,7 @@ CONFIG_JFFS2_ZLIB=y
1282CONFIG_JFFS2_RTIME=y 1436CONFIG_JFFS2_RTIME=y
1283# CONFIG_JFFS2_RUBIN is not set 1437# CONFIG_JFFS2_RUBIN is not set
1284CONFIG_CRAMFS=y 1438CONFIG_CRAMFS=y
1439# CONFIG_SQUASHFS is not set
1285# CONFIG_VXFS_FS is not set 1440# CONFIG_VXFS_FS is not set
1286# CONFIG_MINIX_FS is not set 1441# CONFIG_MINIX_FS is not set
1287# CONFIG_OMFS_FS is not set 1442# CONFIG_OMFS_FS is not set
@@ -1290,6 +1445,7 @@ CONFIG_CRAMFS=y
1290# CONFIG_ROMFS_FS is not set 1445# CONFIG_ROMFS_FS is not set
1291# CONFIG_SYSV_FS is not set 1446# CONFIG_SYSV_FS is not set
1292# CONFIG_UFS_FS is not set 1447# CONFIG_UFS_FS is not set
1448# CONFIG_NILFS2_FS is not set
1293CONFIG_NETWORK_FILESYSTEMS=y 1449CONFIG_NETWORK_FILESYSTEMS=y
1294CONFIG_NFS_FS=y 1450CONFIG_NFS_FS=y
1295CONFIG_NFS_V3=y 1451CONFIG_NFS_V3=y
@@ -1381,13 +1537,16 @@ CONFIG_ENABLE_MUST_CHECK=y
1381CONFIG_FRAME_WARN=1024 1537CONFIG_FRAME_WARN=1024
1382CONFIG_MAGIC_SYSRQ=y 1538CONFIG_MAGIC_SYSRQ=y
1383# CONFIG_UNUSED_SYMBOLS is not set 1539# CONFIG_UNUSED_SYMBOLS is not set
1384# CONFIG_DEBUG_FS is not set 1540CONFIG_DEBUG_FS=y
1385# CONFIG_HEADERS_CHECK is not set 1541# CONFIG_HEADERS_CHECK is not set
1386CONFIG_DEBUG_KERNEL=y 1542CONFIG_DEBUG_KERNEL=y
1387# CONFIG_DEBUG_SHIRQ is not set 1543# CONFIG_DEBUG_SHIRQ is not set
1388CONFIG_DETECT_SOFTLOCKUP=y 1544CONFIG_DETECT_SOFTLOCKUP=y
1389# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set 1545# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1390CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 1546CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1547CONFIG_DETECT_HUNG_TASK=y
1548# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1549CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1391CONFIG_SCHED_DEBUG=y 1550CONFIG_SCHED_DEBUG=y
1392CONFIG_SCHEDSTATS=y 1551CONFIG_SCHEDSTATS=y
1393# CONFIG_TIMER_STATS is not set 1552# CONFIG_TIMER_STATS is not set
@@ -1411,25 +1570,46 @@ CONFIG_DEBUG_INFO=y
1411# CONFIG_DEBUG_MEMORY_INIT is not set 1570# CONFIG_DEBUG_MEMORY_INIT is not set
1412# CONFIG_DEBUG_LIST is not set 1571# CONFIG_DEBUG_LIST is not set
1413# CONFIG_DEBUG_SG is not set 1572# CONFIG_DEBUG_SG is not set
1573# CONFIG_DEBUG_NOTIFIERS is not set
1414CONFIG_FRAME_POINTER=y 1574CONFIG_FRAME_POINTER=y
1415# CONFIG_BOOT_PRINTK_DELAY is not set 1575# CONFIG_BOOT_PRINTK_DELAY is not set
1416# CONFIG_RCU_TORTURE_TEST is not set 1576# CONFIG_RCU_TORTURE_TEST is not set
1577# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1417# CONFIG_KPROBES_SANITY_TEST is not set 1578# CONFIG_KPROBES_SANITY_TEST is not set
1418# CONFIG_BACKTRACE_SELF_TEST is not set 1579# CONFIG_BACKTRACE_SELF_TEST is not set
1580# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1419# CONFIG_LKDTM is not set 1581# CONFIG_LKDTM is not set
1420# CONFIG_FAULT_INJECTION is not set 1582# CONFIG_FAULT_INJECTION is not set
1421CONFIG_LATENCYTOP=y 1583CONFIG_LATENCYTOP=y
1422CONFIG_SYSCTL_SYSCALL_CHECK=y 1584CONFIG_SYSCTL_SYSCALL_CHECK=y
1423CONFIG_HAVE_FTRACE=y 1585# CONFIG_PAGE_POISONING is not set
1424CONFIG_HAVE_DYNAMIC_FTRACE=y 1586CONFIG_NOP_TRACER=y
1425# CONFIG_FTRACE is not set 1587CONFIG_HAVE_FUNCTION_TRACER=y
1588CONFIG_RING_BUFFER=y
1589CONFIG_TRACING=y
1590CONFIG_TRACING_SUPPORT=y
1591
1592#
1593# Tracers
1594#
1595# CONFIG_FUNCTION_TRACER is not set
1426# CONFIG_IRQSOFF_TRACER is not set 1596# CONFIG_IRQSOFF_TRACER is not set
1427# CONFIG_PREEMPT_TRACER is not set 1597# CONFIG_PREEMPT_TRACER is not set
1428# CONFIG_SCHED_TRACER is not set 1598# CONFIG_SCHED_TRACER is not set
1429# CONFIG_CONTEXT_SWITCH_TRACER is not set 1599# CONFIG_CONTEXT_SWITCH_TRACER is not set
1600# CONFIG_EVENT_TRACER is not set
1601# CONFIG_BOOT_TRACER is not set
1602# CONFIG_TRACE_BRANCH_PROFILING is not set
1603# CONFIG_STACK_TRACER is not set
1604# CONFIG_KMEMTRACE is not set
1605# CONFIG_WORKQUEUE_TRACER is not set
1606# CONFIG_BLK_DEV_IO_TRACE is not set
1607# CONFIG_FTRACE_STARTUP_TEST is not set
1608# CONFIG_DYNAMIC_DEBUG is not set
1430# CONFIG_SAMPLES is not set 1609# CONFIG_SAMPLES is not set
1431CONFIG_HAVE_ARCH_KGDB=y 1610CONFIG_HAVE_ARCH_KGDB=y
1432# CONFIG_KGDB is not set 1611# CONFIG_KGDB is not set
1612CONFIG_ARM_UNWIND=y
1433CONFIG_DEBUG_USER=y 1613CONFIG_DEBUG_USER=y
1434CONFIG_DEBUG_ERRORS=y 1614CONFIG_DEBUG_ERRORS=y
1435# CONFIG_DEBUG_STACK_USAGE is not set 1615# CONFIG_DEBUG_STACK_USAGE is not set
@@ -1441,18 +1621,27 @@ CONFIG_DEBUG_LL=y
1441# 1621#
1442# CONFIG_KEYS is not set 1622# CONFIG_KEYS is not set
1443# CONFIG_SECURITY is not set 1623# CONFIG_SECURITY is not set
1624# CONFIG_SECURITYFS is not set
1444# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1625# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1445CONFIG_ASYNC_CORE=y
1446CONFIG_CRYPTO=y 1626CONFIG_CRYPTO=y
1447 1627
1448# 1628#
1449# Crypto core or helper 1629# Crypto core or helper
1450# 1630#
1631# CONFIG_CRYPTO_FIPS is not set
1451CONFIG_CRYPTO_ALGAPI=m 1632CONFIG_CRYPTO_ALGAPI=m
1633CONFIG_CRYPTO_ALGAPI2=m
1634CONFIG_CRYPTO_AEAD2=m
1452CONFIG_CRYPTO_BLKCIPHER=m 1635CONFIG_CRYPTO_BLKCIPHER=m
1636CONFIG_CRYPTO_BLKCIPHER2=m
1637CONFIG_CRYPTO_HASH2=m
1638CONFIG_CRYPTO_RNG2=m
1639CONFIG_CRYPTO_PCOMP=m
1453CONFIG_CRYPTO_MANAGER=m 1640CONFIG_CRYPTO_MANAGER=m
1641CONFIG_CRYPTO_MANAGER2=m
1454# CONFIG_CRYPTO_GF128MUL is not set 1642# CONFIG_CRYPTO_GF128MUL is not set
1455# CONFIG_CRYPTO_NULL is not set 1643# CONFIG_CRYPTO_NULL is not set
1644CONFIG_CRYPTO_WORKQUEUE=m
1456# CONFIG_CRYPTO_CRYPTD is not set 1645# CONFIG_CRYPTO_CRYPTD is not set
1457# CONFIG_CRYPTO_AUTHENC is not set 1646# CONFIG_CRYPTO_AUTHENC is not set
1458# CONFIG_CRYPTO_TEST is not set 1647# CONFIG_CRYPTO_TEST is not set
@@ -1521,18 +1710,24 @@ CONFIG_CRYPTO_PCBC=m
1521# Compression 1710# Compression
1522# 1711#
1523# CONFIG_CRYPTO_DEFLATE is not set 1712# CONFIG_CRYPTO_DEFLATE is not set
1713# CONFIG_CRYPTO_ZLIB is not set
1524# CONFIG_CRYPTO_LZO is not set 1714# CONFIG_CRYPTO_LZO is not set
1715
1716#
1717# Random Number Generation
1718#
1719# CONFIG_CRYPTO_ANSI_CPRNG is not set
1525CONFIG_CRYPTO_HW=y 1720CONFIG_CRYPTO_HW=y
1526# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1721# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1722CONFIG_BINARY_PRINTF=y
1527 1723
1528# 1724#
1529# Library routines 1725# Library routines
1530# 1726#
1531CONFIG_BITREVERSE=y 1727CONFIG_BITREVERSE=y
1532# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1728CONFIG_GENERIC_FIND_LAST_BIT=y
1533# CONFIG_GENERIC_FIND_NEXT_BIT is not set
1534# CONFIG_CRC_CCITT is not set 1729# CONFIG_CRC_CCITT is not set
1535# CONFIG_CRC16 is not set 1730CONFIG_CRC16=m
1536CONFIG_CRC_T10DIF=y 1731CONFIG_CRC_T10DIF=y
1537CONFIG_CRC_ITU_T=m 1732CONFIG_CRC_ITU_T=m
1538CONFIG_CRC32=y 1733CONFIG_CRC32=y
@@ -1540,7 +1735,7 @@ CONFIG_CRC32=y
1540# CONFIG_LIBCRC32C is not set 1735# CONFIG_LIBCRC32C is not set
1541CONFIG_ZLIB_INFLATE=y 1736CONFIG_ZLIB_INFLATE=y
1542CONFIG_ZLIB_DEFLATE=y 1737CONFIG_ZLIB_DEFLATE=y
1543CONFIG_PLIST=y
1544CONFIG_HAS_IOMEM=y 1738CONFIG_HAS_IOMEM=y
1545CONFIG_HAS_IOPORT=y 1739CONFIG_HAS_IOPORT=y
1546CONFIG_HAS_DMA=y 1740CONFIG_HAS_DMA=y
1741CONFIG_NLATTR=y
diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig
index 30f463d2fa8a..6ab5dd5868de 100644
--- a/arch/arm/configs/viper_defconfig
+++ b/arch/arm/configs/viper_defconfig
@@ -298,7 +298,6 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=m
298CONFIG_CPU_FREQ_GOV_USERSPACE=m 298CONFIG_CPU_FREQ_GOV_USERSPACE=m
299CONFIG_CPU_FREQ_GOV_ONDEMAND=m 299CONFIG_CPU_FREQ_GOV_ONDEMAND=m
300CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m 300CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
301CONFIG_CPU_FREQ_PXA=y
302 301
303# 302#
304# Floating point emulation 303# Floating point emulation
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index d7da19bcf928..c207504de84d 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -45,13 +45,15 @@ typedef struct user_fp elf_fpregset_t;
45#define EF_ARM_HASENTRY 0x00000002 /* All */ 45#define EF_ARM_HASENTRY 0x00000002 /* All */
46#define EF_ARM_RELEXEC 0x00000001 /* All */ 46#define EF_ARM_RELEXEC 0x00000001 /* All */
47 47
48#define R_ARM_NONE 0 48#define R_ARM_NONE 0
49#define R_ARM_PC24 1 49#define R_ARM_PC24 1
50#define R_ARM_ABS32 2 50#define R_ARM_ABS32 2
51#define R_ARM_CALL 28 51#define R_ARM_CALL 28
52#define R_ARM_JUMP24 29 52#define R_ARM_JUMP24 29
53#define R_ARM_V4BX 40 53#define R_ARM_V4BX 40
54#define R_ARM_PREL31 42 54#define R_ARM_PREL31 42
55#define R_ARM_MOVW_ABS_NC 43
56#define R_ARM_MOVT_ABS 44
55 57
56/* 58/*
57 * These are used to set parameters in the core dumps. 59 * These are used to set parameters in the core dumps.
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index d1731e39b496..bac03c81489d 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -169,6 +169,21 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
169 *(u32 *)loc = offset & 0x7fffffff; 169 *(u32 *)loc = offset & 0x7fffffff;
170 break; 170 break;
171 171
172 case R_ARM_MOVW_ABS_NC:
173 case R_ARM_MOVT_ABS:
174 offset = *(u32 *)loc;
175 offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff);
176 offset = (offset ^ 0x8000) - 0x8000;
177
178 offset += sym->st_value;
179 if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS)
180 offset >>= 16;
181
182 *(u32 *)loc &= 0xfff0f000;
183 *(u32 *)loc |= ((offset & 0xf000) << 4) |
184 (offset & 0x0fff);
185 break;
186
172 default: 187 default:
173 printk(KERN_ERR "%s: unknown relocation: %u\n", 188 printk(KERN_ERR "%s: unknown relocation: %u\n",
174 module->name, ELF32_R_TYPE(rel->r_info)); 189 module->name, ELF32_R_TYPE(rel->r_info));
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index bac988e7a4c3..a9c78bc72b84 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -4,19 +4,56 @@ menu "TI DaVinci Implementations"
4 4
5comment "DaVinci Core Type" 5comment "DaVinci Core Type"
6 6
7config ARCH_DAVINCI644x 7config ARCH_DAVINCI_DM644x
8 default y
9 bool "DaVinci 644x based system" 8 bool "DaVinci 644x based system"
10 9
11comment "DaVinci Board Type" 10comment "DaVinci Board Type"
12 11
13config MACH_DAVINCI_EVM 12config MACH_DAVINCI_EVM
14 bool "TI DaVinci EVM" 13 bool "TI DM644x EVM"
15 default y 14 default y
16 depends on ARCH_DAVINCI644x 15 depends on ARCH_DAVINCI_DM644x
17 help 16 help
18 Configure this option to specify the whether the board used 17 Configure this option to specify the whether the board used
19 for development is a DaVinci EVM 18 for development is a DM644x EVM
19
20
21config DAVINCI_MUX
22 bool "DAVINCI multiplexing support"
23 depends on ARCH_DAVINCI
24 default y
25 help
26 Pin multiplexing support for DAVINCI boards. If your bootloader
27 sets the multiplexing correctly, say N. Otherwise, or if unsure,
28 say Y.
29
30config DAVINCI_MUX_DEBUG
31 bool "Multiplexing debug output"
32 depends on DAVINCI_MUX
33 help
34 Makes the multiplexing functions print out a lot of debug info.
35 This is useful if you want to find out the correct values of the
36 multiplexing registers.
37
38config DAVINCI_MUX_WARNINGS
39 bool "Warn about pins the bootloader didn't set up"
40 depends on DAVINCI_MUX
41 help
42 Choose Y here to warn whenever driver initialization logic needs
43 to change the pin multiplexing setup. When there are no warnings
44 printed, it's safe to deselect DAVINCI_MUX for your product.
45
46config DAVINCI_RESET_CLOCKS
47 bool "Reset unused clocks during boot"
48 depends on ARCH_DAVINCI
49 help
50 Say Y if you want to reset unused clocks during boot.
51 This option saves power, but assumes all drivers are
52 using the clock framework. Broken drivers that do not
53 yet use clock framework may not work with this option.
54 If you are booting from another operating system, you
55 probably do not want this option enabled until your
56 device drivers work properly.
20 57
21endmenu 58endmenu
22 59
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 4dc458597f40..1674661942f3 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,7 +5,12 @@
5 5
6# Common objects 6# Common objects
7obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \ 7obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \
8 gpio.o mux.o devices.o usb.o 8 gpio.o devices.o dma.o usb.o
9
10obj-$(CONFIG_DAVINCI_MUX) += mux.o
11
12# Chip specific
13obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o
9 14
10# Board specific 15# Board specific
11obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o 16obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o
diff --git a/arch/arm/mach-davinci/board-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 0b97a528902b..b2e7f9c63bc5 100644
--- a/arch/arm/mach-davinci/board-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -15,15 +15,20 @@
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <linux/leds.h> 17#include <linux/leds.h>
18#include <linux/memory.h>
19#include <linux/etherdevice.h>
18 20
19#include <linux/i2c.h> 21#include <linux/i2c.h>
20#include <linux/i2c/pcf857x.h> 22#include <linux/i2c/pcf857x.h>
21#include <linux/i2c/at24.h> 23#include <linux/i2c/at24.h>
22 24
23#include <linux/mtd/mtd.h> 25#include <linux/mtd/mtd.h>
26#include <linux/mtd/nand.h>
24#include <linux/mtd/partitions.h> 27#include <linux/mtd/partitions.h>
25#include <linux/mtd/physmap.h> 28#include <linux/mtd/physmap.h>
26#include <linux/io.h> 29#include <linux/io.h>
30#include <linux/phy.h>
31#include <linux/clk.h>
27 32
28#include <asm/setup.h> 33#include <asm/setup.h>
29#include <asm/mach-types.h> 34#include <asm/mach-types.h>
@@ -32,25 +37,34 @@
32#include <asm/mach/map.h> 37#include <asm/mach/map.h>
33#include <asm/mach/flash.h> 38#include <asm/mach/flash.h>
34 39
35#include <mach/hardware.h> 40#include <mach/dm644x.h>
36#include <mach/common.h> 41#include <mach/common.h>
37#include <mach/i2c.h> 42#include <mach/i2c.h>
43#include <mach/serial.h>
44#include <mach/mux.h>
45#include <mach/psc.h>
46#include <mach/nand.h>
38 47
39/* other misc. init functions */ 48#define DM644X_EVM_PHY_MASK (0x2)
40void __init davinci_psc_init(void); 49#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
41void __init davinci_irq_init(void);
42void __init davinci_map_common_io(void);
43void __init davinci_init_common_hw(void);
44 50
45#if defined(CONFIG_MTD_PHYSMAP) || \ 51#define DAVINCI_CFC_ATA_BASE 0x01C66000
46 defined(CONFIG_MTD_PHYSMAP_MODULE) 52
53#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
54#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
55#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
56#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
57#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
58
59#define LXT971_PHY_ID (0x001378e2)
60#define LXT971_PHY_MASK (0xfffffff0)
47 61
48static struct mtd_partition davinci_evm_norflash_partitions[] = { 62static struct mtd_partition davinci_evm_norflash_partitions[] = {
49 /* bootloader (U-Boot, etc) in first 4 sectors */ 63 /* bootloader (UBL, U-Boot, etc) in first 5 sectors */
50 { 64 {
51 .name = "bootloader", 65 .name = "bootloader",
52 .offset = 0, 66 .offset = 0,
53 .size = 4 * SZ_64K, 67 .size = 5 * SZ_64K,
54 .mask_flags = MTD_WRITEABLE, /* force read-only */ 68 .mask_flags = MTD_WRITEABLE, /* force read-only */
55 }, 69 },
56 /* bootloader params in the next 1 sectors */ 70 /* bootloader params in the next 1 sectors */
@@ -100,10 +114,89 @@ static struct platform_device davinci_evm_norflash_device = {
100 .resource = &davinci_evm_norflash_resource, 114 .resource = &davinci_evm_norflash_resource,
101}; 115};
102 116
103#endif 117/* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
118 * It may used instead of the (default) NOR chip to boot, using TI's
119 * tools to install the secondary boot loader (UBL) and U-Boot.
120 */
121struct mtd_partition davinci_evm_nandflash_partition[] = {
122 /* Bootloader layout depends on whose u-boot is installed, but we
123 * can hide all the details.
124 * - block 0 for u-boot environment ... in mainline u-boot
125 * - block 1 for UBL (plus up to four backup copies in blocks 2..5)
126 * - blocks 6...? for u-boot
127 * - blocks 16..23 for u-boot environment ... in TI's u-boot
128 */
129 {
130 .name = "bootloader",
131 .offset = 0,
132 .size = SZ_256K + SZ_128K,
133 .mask_flags = MTD_WRITEABLE, /* force read-only */
134 },
135 /* Kernel */
136 {
137 .name = "kernel",
138 .offset = MTDPART_OFS_APPEND,
139 .size = SZ_4M,
140 .mask_flags = 0,
141 },
142 /* File system (older GIT kernels started this on the 5MB mark) */
143 {
144 .name = "filesystem",
145 .offset = MTDPART_OFS_APPEND,
146 .size = MTDPART_SIZ_FULL,
147 .mask_flags = 0,
148 }
149 /* A few blocks at end hold a flash BBT ... created by TI's CCS
150 * using flashwriter_nand.out, but ignored by TI's versions of
151 * Linux and u-boot. We boot faster by using them.
152 */
153};
104 154
105#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ 155static struct davinci_nand_pdata davinci_evm_nandflash_data = {
106 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) 156 .parts = davinci_evm_nandflash_partition,
157 .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
158 .ecc_mode = NAND_ECC_HW,
159 .options = NAND_USE_FLASH_BBT,
160};
161
162static struct resource davinci_evm_nandflash_resource[] = {
163 {
164 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
165 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
166 .flags = IORESOURCE_MEM,
167 }, {
168 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
169 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
170 .flags = IORESOURCE_MEM,
171 },
172};
173
174static struct platform_device davinci_evm_nandflash_device = {
175 .name = "davinci_nand",
176 .id = 0,
177 .dev = {
178 .platform_data = &davinci_evm_nandflash_data,
179 },
180 .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
181 .resource = davinci_evm_nandflash_resource,
182};
183
184static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
185
186static struct platform_device davinci_fb_device = {
187 .name = "davincifb",
188 .id = -1,
189 .dev = {
190 .dma_mask = &davinci_fb_dma_mask,
191 .coherent_dma_mask = DMA_BIT_MASK(32),
192 },
193 .num_resources = 0,
194};
195
196static struct platform_device rtc_dev = {
197 .name = "rtc_davinci_evm",
198 .id = -1,
199};
107 200
108static struct resource ide_resources[] = { 201static struct resource ide_resources[] = {
109 { 202 {
@@ -131,8 +224,6 @@ static struct platform_device ide_dev = {
131 }, 224 },
132}; 225};
133 226
134#endif
135
136/*----------------------------------------------------------------------*/ 227/*----------------------------------------------------------------------*/
137 228
138/* 229/*
@@ -311,7 +402,9 @@ evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
311 gpio_request(gpio + 7, "nCF_SEL"); 402 gpio_request(gpio + 7, "nCF_SEL");
312 gpio_direction_output(gpio + 7, 1); 403 gpio_direction_output(gpio + 7, 1);
313 404
314 /* irlml6401 sustains over 3A, switches 5V in under 8 msec */ 405 /* irlml6401 switches over 1A, in under 8 msec;
406 * now it can be managed by nDRV_VBUS ...
407 */
315 setup_usb(500, 8); 408 setup_usb(500, 8);
316 409
317 return 0; 410 return 0;
@@ -343,14 +436,120 @@ static struct pcf857x_platform_data pcf_data_u35 = {
343 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL) 436 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
344 * - ... newer boards may have more 437 * - ... newer boards may have more
345 */ 438 */
439static struct memory_accessor *at24_mem_acc;
440
441static void at24_setup(struct memory_accessor *mem_acc, void *context)
442{
443 DECLARE_MAC_BUF(mac_str);
444 char mac_addr[6];
445
446 at24_mem_acc = mem_acc;
447
448 /* Read MAC addr from EEPROM */
449 if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x7f00, 6) == 6) {
450 printk(KERN_INFO "Read MAC addr from EEPROM: %s\n",
451 print_mac(mac_str, mac_addr));
452 }
453}
454
346static struct at24_platform_data eeprom_info = { 455static struct at24_platform_data eeprom_info = {
347 .byte_len = (256*1024) / 8, 456 .byte_len = (256*1024) / 8,
348 .page_size = 64, 457 .page_size = 64,
349 .flags = AT24_FLAG_ADDR16, 458 .flags = AT24_FLAG_ADDR16,
459 .setup = at24_setup,
350}; 460};
351 461
462int dm6446evm_eeprom_read(void *buf, off_t off, size_t count)
463{
464 if (at24_mem_acc)
465 return at24_mem_acc->read(at24_mem_acc, buf, off, count);
466 return -ENODEV;
467}
468EXPORT_SYMBOL(dm6446evm_eeprom_read);
469
470int dm6446evm_eeprom_write(void *buf, off_t off, size_t count)
471{
472 if (at24_mem_acc)
473 return at24_mem_acc->write(at24_mem_acc, buf, off, count);
474 return -ENODEV;
475}
476EXPORT_SYMBOL(dm6446evm_eeprom_write);
477
478/*
479 * MSP430 supports RTC, card detection, input from IR remote, and
480 * a bit more. It triggers interrupts on GPIO(7) from pressing
481 * buttons on the IR remote, and for card detect switches.
482 */
483static struct i2c_client *dm6446evm_msp;
484
485static int dm6446evm_msp_probe(struct i2c_client *client,
486 const struct i2c_device_id *id)
487{
488 dm6446evm_msp = client;
489 return 0;
490}
491
492static int dm6446evm_msp_remove(struct i2c_client *client)
493{
494 dm6446evm_msp = NULL;
495 return 0;
496}
497
498static const struct i2c_device_id dm6446evm_msp_ids[] = {
499 { "dm6446evm_msp", 0, },
500 { /* end of list */ },
501};
502
503static struct i2c_driver dm6446evm_msp_driver = {
504 .driver.name = "dm6446evm_msp",
505 .id_table = dm6446evm_msp_ids,
506 .probe = dm6446evm_msp_probe,
507 .remove = dm6446evm_msp_remove,
508};
509
510static int dm6444evm_msp430_get_pins(void)
511{
512 static const char txbuf[2] = { 2, 4, };
513 char buf[4];
514 struct i2c_msg msg[2] = {
515 {
516 .addr = dm6446evm_msp->addr,
517 .flags = 0,
518 .len = 2,
519 .buf = (void __force *)txbuf,
520 },
521 {
522 .addr = dm6446evm_msp->addr,
523 .flags = I2C_M_RD,
524 .len = 4,
525 .buf = buf,
526 },
527 };
528 int status;
529
530 if (!dm6446evm_msp)
531 return -ENXIO;
532
533 /* Command 4 == get input state, returns port 2 and port3 data
534 * S Addr W [A] len=2 [A] cmd=4 [A]
535 * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
536 */
537 status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
538 if (status < 0)
539 return status;
540
541 dev_dbg(&dm6446evm_msp->dev,
542 "PINS: %02x %02x %02x %02x\n",
543 buf[0], buf[1], buf[2], buf[3]);
544
545 return (buf[3] << 8) | buf[2];
546}
547
352static struct i2c_board_info __initdata i2c_info[] = { 548static struct i2c_board_info __initdata i2c_info[] = {
353 { 549 {
550 I2C_BOARD_INFO("dm6446evm_msp", 0x23),
551 },
552 {
354 I2C_BOARD_INFO("pcf8574", 0x38), 553 I2C_BOARD_INFO("pcf8574", 0x38),
355 .platform_data = &pcf_data_u2, 554 .platform_data = &pcf_data_u2,
356 }, 555 },
@@ -368,7 +567,6 @@ static struct i2c_board_info __initdata i2c_info[] = {
368 }, 567 },
369 /* ALSO: 568 /* ALSO:
370 * - tvl320aic33 audio codec (0x1b) 569 * - tvl320aic33 audio codec (0x1b)
371 * - msp430 microcontroller (0x23)
372 * - tvp5146 video decoder (0x5d) 570 * - tvp5146 video decoder (0x5d)
373 */ 571 */
374}; 572};
@@ -384,51 +582,109 @@ static struct davinci_i2c_platform_data i2c_pdata = {
384static void __init evm_init_i2c(void) 582static void __init evm_init_i2c(void)
385{ 583{
386 davinci_init_i2c(&i2c_pdata); 584 davinci_init_i2c(&i2c_pdata);
585 i2c_add_driver(&dm6446evm_msp_driver);
387 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); 586 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
388} 587}
389 588
390static struct platform_device *davinci_evm_devices[] __initdata = { 589static struct platform_device *davinci_evm_devices[] __initdata = {
391#if defined(CONFIG_MTD_PHYSMAP) || \ 590 &davinci_fb_device,
392 defined(CONFIG_MTD_PHYSMAP_MODULE) 591 &rtc_dev,
393 &davinci_evm_norflash_device, 592};
394#endif 593
395#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ 594static struct davinci_uart_config uart_config __initdata = {
396 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) 595 .enabled_uarts = (1 << 0),
397 &ide_dev,
398#endif
399}; 596};
400 597
401static void __init 598static void __init
402davinci_evm_map_io(void) 599davinci_evm_map_io(void)
403{ 600{
404 davinci_map_common_io(); 601 davinci_map_common_io();
602 dm644x_init();
405} 603}
406 604
407static __init void davinci_evm_init(void) 605static int davinci_phy_fixup(struct phy_device *phydev)
408{ 606{
409 davinci_psc_init(); 607 unsigned int control;
608 /* CRITICAL: Fix for increasing PHY signal drive strength for
609 * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
610 * signal strength was low causing TX to fail randomly. The
611 * fix is to Set bit 11 (Increased MII drive strength) of PHY
612 * register 26 (Digital Config register) on this phy. */
613 control = phy_read(phydev, 26);
614 phy_write(phydev, 26, (control | 0x800));
615 return 0;
616}
410 617
411#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ 618#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
412 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) 619 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
620#define HAS_ATA 1
621#else
622#define HAS_ATA 0
623#endif
624
413#if defined(CONFIG_MTD_PHYSMAP) || \ 625#if defined(CONFIG_MTD_PHYSMAP) || \
414 defined(CONFIG_MTD_PHYSMAP_MODULE) 626 defined(CONFIG_MTD_PHYSMAP_MODULE)
415 printk(KERN_WARNING "WARNING: both IDE and NOR flash are enabled, " 627#define HAS_NOR 1
416 "but share pins.\n\t Disable IDE for NOR support.\n"); 628#else
629#define HAS_NOR 0
417#endif 630#endif
631
632#if defined(CONFIG_MTD_NAND_DAVINCI) || \
633 defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
634#define HAS_NAND 1
635#else
636#define HAS_NAND 0
418#endif 637#endif
419 638
639static __init void davinci_evm_init(void)
640{
641 struct clk *aemif_clk;
642
643 aemif_clk = clk_get(NULL, "aemif");
644 clk_enable(aemif_clk);
645
646 if (HAS_ATA) {
647 if (HAS_NAND || HAS_NOR)
648 pr_warning("WARNING: both IDE and Flash are "
649 "enabled, but they share AEMIF pins.\n"
650 "\tDisable IDE for NAND/NOR support.\n");
651 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
652 davinci_cfg_reg(DM644X_ATAEN);
653 davinci_cfg_reg(DM644X_HDIREN);
654 platform_device_register(&ide_dev);
655 } else if (HAS_NAND || HAS_NOR) {
656 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
657 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
658
659 /* only one device will be jumpered and detected */
660 if (HAS_NAND) {
661 platform_device_register(&davinci_evm_nandflash_device);
662 evm_leds[7].default_trigger = "nand-disk";
663 if (HAS_NOR)
664 pr_warning("WARNING: both NAND and NOR flash "
665 "are enabled; disable one of them.\n");
666 } else if (HAS_NOR)
667 platform_device_register(&davinci_evm_norflash_device);
668 }
669
420 platform_add_devices(davinci_evm_devices, 670 platform_add_devices(davinci_evm_devices,
421 ARRAY_SIZE(davinci_evm_devices)); 671 ARRAY_SIZE(davinci_evm_devices));
422 evm_init_i2c(); 672 evm_init_i2c();
673
674 davinci_serial_init(&uart_config);
675
676 /* Register the fixup for PHY on DaVinci */
677 phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
678 davinci_phy_fixup);
679
423} 680}
424 681
425static __init void davinci_evm_irq_init(void) 682static __init void davinci_evm_irq_init(void)
426{ 683{
427 davinci_init_common_hw();
428 davinci_irq_init(); 684 davinci_irq_init();
429} 685}
430 686
431MACHINE_START(DAVINCI_EVM, "DaVinci EVM") 687MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
432 /* Maintainer: MontaVista Software <source@mvista.com> */ 688 /* Maintainer: MontaVista Software <source@mvista.com> */
433 .phys_io = IO_PHYS, 689 .phys_io = IO_PHYS,
434 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 690 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index abb92b7eca0c..f0baaa15a57e 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -1,7 +1,8 @@
1/* 1/*
2 * TI DaVinci clock config file 2 * Clock and PLL control for DaVinci devices
3 * 3 *
4 * Copyright (C) 2006 Texas Instruments. 4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
@@ -13,6 +14,7 @@
13#include <linux/kernel.h> 14#include <linux/kernel.h>
14#include <linux/init.h> 15#include <linux/init.h>
15#include <linux/errno.h> 16#include <linux/errno.h>
17#include <linux/clk.h>
16#include <linux/err.h> 18#include <linux/err.h>
17#include <linux/mutex.h> 19#include <linux/mutex.h>
18#include <linux/platform_device.h> 20#include <linux/platform_device.h>
@@ -21,98 +23,50 @@
21#include <mach/hardware.h> 23#include <mach/hardware.h>
22 24
23#include <mach/psc.h> 25#include <mach/psc.h>
26#include <mach/cputype.h>
24#include "clock.h" 27#include "clock.h"
25 28
26/* PLL/Reset register offsets */
27#define PLLM 0x110
28
29static LIST_HEAD(clocks); 29static LIST_HEAD(clocks);
30static DEFINE_MUTEX(clocks_mutex); 30static DEFINE_MUTEX(clocks_mutex);
31static DEFINE_SPINLOCK(clockfw_lock); 31static DEFINE_SPINLOCK(clockfw_lock);
32 32
33static unsigned int commonrate; 33static unsigned psc_domain(struct clk *clk)
34static unsigned int armrate;
35static unsigned int fixedrate = 27000000; /* 27 MHZ */
36
37extern void davinci_psc_config(unsigned int domain, unsigned int id, char enable);
38
39/*
40 * Returns a clock. Note that we first try to use device id on the bus
41 * and clock name. If this fails, we try to use clock name only.
42 */
43struct clk *clk_get(struct device *dev, const char *id)
44{ 34{
45 struct clk *p, *clk = ERR_PTR(-ENOENT); 35 return (clk->flags & PSC_DSP)
46 int idno; 36 ? DAVINCI_GPSC_DSPDOMAIN
47 37 : DAVINCI_GPSC_ARMDOMAIN;
48 if (dev == NULL || dev->bus != &platform_bus_type)
49 idno = -1;
50 else
51 idno = to_platform_device(dev)->id;
52
53 mutex_lock(&clocks_mutex);
54
55 list_for_each_entry(p, &clocks, node) {
56 if (p->id == idno &&
57 strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
58 clk = p;
59 goto found;
60 }
61 }
62
63 list_for_each_entry(p, &clocks, node) {
64 if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
65 clk = p;
66 break;
67 }
68 }
69
70found:
71 mutex_unlock(&clocks_mutex);
72
73 return clk;
74} 38}
75EXPORT_SYMBOL(clk_get);
76 39
77void clk_put(struct clk *clk) 40static void __clk_enable(struct clk *clk)
78{ 41{
79 if (clk && !IS_ERR(clk)) 42 if (clk->parent)
80 module_put(clk->owner); 43 __clk_enable(clk->parent);
81} 44 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
82EXPORT_SYMBOL(clk_put); 45 davinci_psc_config(psc_domain(clk), clk->lpsc, 1);
83
84static int __clk_enable(struct clk *clk)
85{
86 if (clk->flags & ALWAYS_ENABLED)
87 return 0;
88
89 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 1);
90 return 0;
91} 46}
92 47
93static void __clk_disable(struct clk *clk) 48static void __clk_disable(struct clk *clk)
94{ 49{
95 if (clk->usecount) 50 if (WARN_ON(clk->usecount == 0))
96 return; 51 return;
97 52 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
98 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 0); 53 davinci_psc_config(psc_domain(clk), clk->lpsc, 0);
54 if (clk->parent)
55 __clk_disable(clk->parent);
99} 56}
100 57
101int clk_enable(struct clk *clk) 58int clk_enable(struct clk *clk)
102{ 59{
103 unsigned long flags; 60 unsigned long flags;
104 int ret = 0;
105 61
106 if (clk == NULL || IS_ERR(clk)) 62 if (clk == NULL || IS_ERR(clk))
107 return -EINVAL; 63 return -EINVAL;
108 64
109 if (clk->usecount++ == 0) { 65 spin_lock_irqsave(&clockfw_lock, flags);
110 spin_lock_irqsave(&clockfw_lock, flags); 66 __clk_enable(clk);
111 ret = __clk_enable(clk); 67 spin_unlock_irqrestore(&clockfw_lock, flags);
112 spin_unlock_irqrestore(&clockfw_lock, flags);
113 }
114 68
115 return ret; 69 return 0;
116} 70}
117EXPORT_SYMBOL(clk_enable); 71EXPORT_SYMBOL(clk_enable);
118 72
@@ -123,11 +77,9 @@ void clk_disable(struct clk *clk)
123 if (clk == NULL || IS_ERR(clk)) 77 if (clk == NULL || IS_ERR(clk))
124 return; 78 return;
125 79
126 if (clk->usecount > 0 && !(--clk->usecount)) { 80 spin_lock_irqsave(&clockfw_lock, flags);
127 spin_lock_irqsave(&clockfw_lock, flags); 81 __clk_disable(clk);
128 __clk_disable(clk); 82 spin_unlock_irqrestore(&clockfw_lock, flags);
129 spin_unlock_irqrestore(&clockfw_lock, flags);
130 }
131} 83}
132EXPORT_SYMBOL(clk_disable); 84EXPORT_SYMBOL(clk_disable);
133 85
@@ -136,7 +88,7 @@ unsigned long clk_get_rate(struct clk *clk)
136 if (clk == NULL || IS_ERR(clk)) 88 if (clk == NULL || IS_ERR(clk))
137 return -EINVAL; 89 return -EINVAL;
138 90
139 return *(clk->rate); 91 return clk->rate;
140} 92}
141EXPORT_SYMBOL(clk_get_rate); 93EXPORT_SYMBOL(clk_get_rate);
142 94
@@ -145,7 +97,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
145 if (clk == NULL || IS_ERR(clk)) 97 if (clk == NULL || IS_ERR(clk))
146 return -EINVAL; 98 return -EINVAL;
147 99
148 return *(clk->rate); 100 return clk->rate;
149} 101}
150EXPORT_SYMBOL(clk_round_rate); 102EXPORT_SYMBOL(clk_round_rate);
151 103
@@ -164,10 +116,23 @@ int clk_register(struct clk *clk)
164 if (clk == NULL || IS_ERR(clk)) 116 if (clk == NULL || IS_ERR(clk))
165 return -EINVAL; 117 return -EINVAL;
166 118
119 if (WARN(clk->parent && !clk->parent->rate,
120 "CLK: %s parent %s has no rate!\n",
121 clk->name, clk->parent->name))
122 return -EINVAL;
123
167 mutex_lock(&clocks_mutex); 124 mutex_lock(&clocks_mutex);
168 list_add(&clk->node, &clocks); 125 list_add_tail(&clk->node, &clocks);
169 mutex_unlock(&clocks_mutex); 126 mutex_unlock(&clocks_mutex);
170 127
128 /* If rate is already set, use it */
129 if (clk->rate)
130 return 0;
131
132 /* Otherwise, default to parent rate */
133 if (clk->parent)
134 clk->rate = clk->parent->rate;
135
171 return 0; 136 return 0;
172} 137}
173EXPORT_SYMBOL(clk_register); 138EXPORT_SYMBOL(clk_register);
@@ -183,84 +148,150 @@ void clk_unregister(struct clk *clk)
183} 148}
184EXPORT_SYMBOL(clk_unregister); 149EXPORT_SYMBOL(clk_unregister);
185 150
186static struct clk davinci_clks[] = { 151#ifdef CONFIG_DAVINCI_RESET_CLOCKS
187 { 152/*
188 .name = "ARMCLK", 153 * Disable any unused clocks left on by the bootloader
189 .rate = &armrate, 154 */
190 .lpsc = -1, 155static int __init clk_disable_unused(void)
191 .flags = ALWAYS_ENABLED, 156{
192 }, 157 struct clk *ck;
193 { 158
194 .name = "UART", 159 spin_lock_irq(&clockfw_lock);
195 .rate = &fixedrate, 160 list_for_each_entry(ck, &clocks, node) {
196 .lpsc = DAVINCI_LPSC_UART0, 161 if (ck->usecount > 0)
197 }, 162 continue;
198 { 163 if (!(ck->flags & CLK_PSC))
199 .name = "EMACCLK", 164 continue;
200 .rate = &commonrate, 165
201 .lpsc = DAVINCI_LPSC_EMAC_WRAPPER, 166 /* ignore if in Disabled or SwRstDisable states */
202 }, 167 if (!davinci_psc_is_clk_active(ck->lpsc))
203 { 168 continue;
204 .name = "I2CCLK", 169
205 .rate = &fixedrate, 170 pr_info("Clocks: disable unused %s\n", ck->name);
206 .lpsc = DAVINCI_LPSC_I2C, 171 davinci_psc_config(psc_domain(ck), ck->lpsc, 0);
207 },
208 {
209 .name = "IDECLK",
210 .rate = &commonrate,
211 .lpsc = DAVINCI_LPSC_ATA,
212 },
213 {
214 .name = "McBSPCLK",
215 .rate = &commonrate,
216 .lpsc = DAVINCI_LPSC_McBSP,
217 },
218 {
219 .name = "MMCSDCLK",
220 .rate = &commonrate,
221 .lpsc = DAVINCI_LPSC_MMC_SD,
222 },
223 {
224 .name = "SPICLK",
225 .rate = &commonrate,
226 .lpsc = DAVINCI_LPSC_SPI,
227 },
228 {
229 .name = "gpio",
230 .rate = &commonrate,
231 .lpsc = DAVINCI_LPSC_GPIO,
232 },
233 {
234 .name = "usb",
235 .rate = &commonrate,
236 .lpsc = DAVINCI_LPSC_USB,
237 },
238 {
239 .name = "AEMIFCLK",
240 .rate = &commonrate,
241 .lpsc = DAVINCI_LPSC_AEMIF,
242 .usecount = 1,
243 } 172 }
244}; 173 spin_unlock_irq(&clockfw_lock);
174
175 return 0;
176}
177late_initcall(clk_disable_unused);
178#endif
245 179
246int __init davinci_clk_init(void) 180static void clk_sysclk_recalc(struct clk *clk)
247{ 181{
248 struct clk *clkp; 182 u32 v, plldiv;
249 int count = 0; 183 struct pll_data *pll;
250 u32 pll_mult; 184
251 185 /* If this is the PLL base clock, no more calculations needed */
252 pll_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM); 186 if (clk->pll_data)
253 commonrate = ((pll_mult + 1) * 27000000) / 6; 187 return;
254 armrate = ((pll_mult + 1) * 27000000) / 2; 188
255 189 if (WARN_ON(!clk->parent))
256 for (clkp = davinci_clks; count < ARRAY_SIZE(davinci_clks); 190 return;
257 count++, clkp++) { 191
258 clk_register(clkp); 192 clk->rate = clk->parent->rate;
259 193
260 /* Turn on clocks that have been enabled in the 194 /* Otherwise, the parent must be a PLL */
261 * table above */ 195 if (WARN_ON(!clk->parent->pll_data))
262 if (clkp->usecount) 196 return;
263 clk_enable(clkp); 197
198 pll = clk->parent->pll_data;
199
200 /* If pre-PLL, source clock is before the multiplier and divider(s) */
201 if (clk->flags & PRE_PLL)
202 clk->rate = pll->input_rate;
203
204 if (!clk->div_reg)
205 return;
206
207 v = __raw_readl(pll->base + clk->div_reg);
208 if (v & PLLDIV_EN) {
209 plldiv = (v & PLLDIV_RATIO_MASK) + 1;
210 if (plldiv)
211 clk->rate /= plldiv;
212 }
213}
214
215static void __init clk_pll_init(struct clk *clk)
216{
217 u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
218 u8 bypass;
219 struct pll_data *pll = clk->pll_data;
220
221 pll->base = IO_ADDRESS(pll->phys_base);
222 ctrl = __raw_readl(pll->base + PLLCTL);
223 clk->rate = pll->input_rate = clk->parent->rate;
224
225 if (ctrl & PLLCTL_PLLEN) {
226 bypass = 0;
227 mult = __raw_readl(pll->base + PLLM);
228 mult = (mult & PLLM_PLLM_MASK) + 1;
229 } else
230 bypass = 1;
231
232 if (pll->flags & PLL_HAS_PREDIV) {
233 prediv = __raw_readl(pll->base + PREDIV);
234 if (prediv & PLLDIV_EN)
235 prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
236 else
237 prediv = 1;
238 }
239
240 /* pre-divider is fixed, but (some?) chips won't report that */
241 if (cpu_is_davinci_dm355() && pll->num == 1)
242 prediv = 8;
243
244 if (pll->flags & PLL_HAS_POSTDIV) {
245 postdiv = __raw_readl(pll->base + POSTDIV);
246 if (postdiv & PLLDIV_EN)
247 postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
248 else
249 postdiv = 1;
250 }
251
252 if (!bypass) {
253 clk->rate /= prediv;
254 clk->rate *= mult;
255 clk->rate /= postdiv;
256 }
257
258 pr_debug("PLL%d: input = %lu MHz [ ",
259 pll->num, clk->parent->rate / 1000000);
260 if (bypass)
261 pr_debug("bypass ");
262 if (prediv > 1)
263 pr_debug("/ %d ", prediv);
264 if (mult > 1)
265 pr_debug("* %d ", mult);
266 if (postdiv > 1)
267 pr_debug("/ %d ", postdiv);
268 pr_debug("] --> %lu MHz output.\n", clk->rate / 1000000);
269}
270
271int __init davinci_clk_init(struct davinci_clk *clocks)
272 {
273 struct davinci_clk *c;
274 struct clk *clk;
275
276 for (c = clocks; c->lk.clk; c++) {
277 clk = c->lk.clk;
278
279 if (clk->pll_data)
280 clk_pll_init(clk);
281
282 /* Calculate rates for PLL-derived clocks */
283 else if (clk->flags & CLK_PLL)
284 clk_sysclk_recalc(clk);
285
286 if (clk->lpsc)
287 clk->flags |= CLK_PSC;
288
289 clkdev_add(&c->lk);
290 clk_register(clk);
291
292 /* Turn on clocks that Linux doesn't otherwise manage */
293 if (clk->flags & ALWAYS_ENABLED)
294 clk_enable(clk);
264 } 295 }
265 296
266 return 0; 297 return 0;
@@ -285,12 +316,52 @@ static void davinci_ck_stop(struct seq_file *m, void *v)
285{ 316{
286} 317}
287 318
288static int davinci_ck_show(struct seq_file *m, void *v) 319#define CLKNAME_MAX 10 /* longest clock name */
320#define NEST_DELTA 2
321#define NEST_MAX 4
322
323static void
324dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
289{ 325{
290 struct clk *cp; 326 char *state;
327 char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
328 struct clk *clk;
329 unsigned i;
330
331 if (parent->flags & CLK_PLL)
332 state = "pll";
333 else if (parent->flags & CLK_PSC)
334 state = "psc";
335 else
336 state = "";
337
338 /* <nest spaces> name <pad to end> */
339 memset(buf, ' ', sizeof(buf) - 1);
340 buf[sizeof(buf) - 1] = 0;
341 i = strlen(parent->name);
342 memcpy(buf + nest, parent->name,
343 min(i, (unsigned)(sizeof(buf) - 1 - nest)));
344
345 seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
346 buf, parent->usecount, state, clk_get_rate(parent));
347 /* REVISIT show device associations too */
348
349 /* cost is now small, but not linear... */
350 list_for_each_entry(clk, &clocks, node) {
351 if (clk->parent == parent)
352 dump_clock(s, nest + NEST_DELTA, clk);
353 }
354}
291 355
292 list_for_each_entry(cp, &clocks, node) 356static int davinci_ck_show(struct seq_file *m, void *v)
293 seq_printf(m,"%s %d %d\n", cp->name, *(cp->rate), cp->usecount); 357{
358 /* Show clock tree; we know the main oscillator is first.
359 * We trust nonzero usecounts equate to PSC enables...
360 */
361 mutex_lock(&clocks_mutex);
362 if (!list_empty(&clocks))
363 dump_clock(m, 0, list_first_entry(&clocks, struct clk, node));
364 mutex_unlock(&clocks_mutex);
294 365
295 return 0; 366 return 0;
296} 367}
@@ -321,4 +392,4 @@ static int __init davinci_ck_proc_init(void)
321 392
322} 393}
323__initcall(davinci_ck_proc_init); 394__initcall(davinci_ck_proc_init);
324#endif /* CONFIG_DEBUG_PROC_FS */ 395#endif /* CONFIG_DEBUG_PROC_FS */
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index ed47079a52e4..35736ec202f8 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -1,7 +1,8 @@
1/* 1/*
2 * TI DaVinci clock definitions 2 * TI DaVinci clock definitions
3 * 3 *
4 * Copyright (C) 2006 Texas Instruments. 4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -11,23 +12,85 @@
11#ifndef __ARCH_ARM_DAVINCI_CLOCK_H 12#ifndef __ARCH_ARM_DAVINCI_CLOCK_H
12#define __ARCH_ARM_DAVINCI_CLOCK_H 13#define __ARCH_ARM_DAVINCI_CLOCK_H
13 14
15#include <linux/list.h>
16#include <asm/clkdev.h>
17
18#define DAVINCI_PLL1_BASE 0x01c40800
19#define DAVINCI_PLL2_BASE 0x01c40c00
20#define MAX_PLL 2
21
22/* PLL/Reset register offsets */
23#define PLLCTL 0x100
24#define PLLCTL_PLLEN BIT(0)
25#define PLLCTL_CLKMODE BIT(8)
26
27#define PLLM 0x110
28#define PLLM_PLLM_MASK 0xff
29
30#define PREDIV 0x114
31#define PLLDIV1 0x118
32#define PLLDIV2 0x11c
33#define PLLDIV3 0x120
34#define POSTDIV 0x128
35#define BPDIV 0x12c
36#define PLLCMD 0x138
37#define PLLSTAT 0x13c
38#define PLLALNCTL 0x140
39#define PLLDCHANGE 0x144
40#define PLLCKEN 0x148
41#define PLLCKSTAT 0x14c
42#define PLLSYSTAT 0x150
43#define PLLDIV4 0x160
44#define PLLDIV5 0x164
45#define PLLDIV6 0x168
46#define PLLDIV7 0x16c
47#define PLLDIV8 0x170
48#define PLLDIV9 0x174
49#define PLLDIV_EN BIT(15)
50#define PLLDIV_RATIO_MASK 0x1f
51
52struct pll_data {
53 u32 phys_base;
54 void __iomem *base;
55 u32 num;
56 u32 flags;
57 u32 input_rate;
58};
59#define PLL_HAS_PREDIV 0x01
60#define PLL_HAS_POSTDIV 0x02
61
14struct clk { 62struct clk {
15 struct list_head node; 63 struct list_head node;
16 struct module *owner; 64 struct module *owner;
17 const char *name; 65 const char *name;
18 unsigned int *rate; 66 unsigned long rate;
19 int id; 67 u8 usecount;
20 __s8 usecount; 68 u8 flags;
21 __u8 flags; 69 u8 lpsc;
22 __u8 lpsc; 70 struct clk *parent;
71 struct pll_data *pll_data;
72 u32 div_reg;
23}; 73};
24 74
25/* Clock flags */ 75/* Clock flags */
26#define RATE_CKCTL 1 76#define ALWAYS_ENABLED BIT(1)
27#define RATE_FIXED 2 77#define CLK_PSC BIT(2)
28#define RATE_PROPAGATES 4 78#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
29#define VIRTUAL_CLOCK 8 79#define CLK_PLL BIT(4) /* PLL-derived clock */
30#define ALWAYS_ENABLED 16 80#define PRE_PLL BIT(5) /* source is before PLL mult/div */
31#define ENABLE_REG_32BIT 32 81
82struct davinci_clk {
83 struct clk_lookup lk;
84};
85
86#define CLK(dev, con, ck) \
87 { \
88 .lk = { \
89 .dev_id = dev, \
90 .con_id = con, \
91 .clk = ck, \
92 }, \
93 }
32 94
95int davinci_clk_init(struct davinci_clk *clocks);
33#endif 96#endif
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 808633f9f03c..a31370b93dd2 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -21,6 +21,10 @@
21#include <mach/hardware.h> 21#include <mach/hardware.h>
22#include <mach/i2c.h> 22#include <mach/i2c.h>
23#include <mach/irqs.h> 23#include <mach/irqs.h>
24#include <mach/cputype.h>
25#include <mach/mux.h>
26
27#define DAVINCI_I2C_BASE 0x01C21000
24 28
25static struct resource i2c_resources[] = { 29static struct resource i2c_resources[] = {
26 { 30 {
@@ -43,6 +47,9 @@ static struct platform_device davinci_i2c_device = {
43 47
44void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata) 48void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
45{ 49{
50 if (cpu_is_davinci_dm644x())
51 davinci_cfg_reg(DM644X_I2C);
52
46 davinci_i2c_device.dev.platform_data = pdata; 53 davinci_i2c_device.dev.platform_data = pdata;
47 (void) platform_device_register(&davinci_i2c_device); 54 (void) platform_device_register(&davinci_i2c_device);
48} 55}
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
new file mode 100644
index 000000000000..d428ef192eac
--- /dev/null
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -0,0 +1,461 @@
1/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h>
14#include <linux/platform_device.h>
15
16#include <mach/dm644x.h>
17#include <mach/clock.h>
18#include <mach/cputype.h>
19#include <mach/edma.h>
20#include <mach/irqs.h>
21#include <mach/psc.h>
22#include <mach/mux.h>
23
24#include "clock.h"
25#include "mux.h"
26
27/*
28 * Device specific clocks
29 */
30#define DM644X_REF_FREQ 27000000
31
32static struct pll_data pll1_data = {
33 .num = 1,
34 .phys_base = DAVINCI_PLL1_BASE,
35};
36
37static struct pll_data pll2_data = {
38 .num = 2,
39 .phys_base = DAVINCI_PLL2_BASE,
40};
41
42static struct clk ref_clk = {
43 .name = "ref_clk",
44 .rate = DM644X_REF_FREQ,
45};
46
47static struct clk pll1_clk = {
48 .name = "pll1",
49 .parent = &ref_clk,
50 .pll_data = &pll1_data,
51 .flags = CLK_PLL,
52};
53
54static struct clk pll1_sysclk1 = {
55 .name = "pll1_sysclk1",
56 .parent = &pll1_clk,
57 .flags = CLK_PLL,
58 .div_reg = PLLDIV1,
59};
60
61static struct clk pll1_sysclk2 = {
62 .name = "pll1_sysclk2",
63 .parent = &pll1_clk,
64 .flags = CLK_PLL,
65 .div_reg = PLLDIV2,
66};
67
68static struct clk pll1_sysclk3 = {
69 .name = "pll1_sysclk3",
70 .parent = &pll1_clk,
71 .flags = CLK_PLL,
72 .div_reg = PLLDIV3,
73};
74
75static struct clk pll1_sysclk5 = {
76 .name = "pll1_sysclk5",
77 .parent = &pll1_clk,
78 .flags = CLK_PLL,
79 .div_reg = PLLDIV5,
80};
81
82static struct clk pll1_aux_clk = {
83 .name = "pll1_aux_clk",
84 .parent = &pll1_clk,
85 .flags = CLK_PLL | PRE_PLL,
86};
87
88static struct clk pll1_sysclkbp = {
89 .name = "pll1_sysclkbp",
90 .parent = &pll1_clk,
91 .flags = CLK_PLL | PRE_PLL,
92 .div_reg = BPDIV
93};
94
95static struct clk pll2_clk = {
96 .name = "pll2",
97 .parent = &ref_clk,
98 .pll_data = &pll2_data,
99 .flags = CLK_PLL,
100};
101
102static struct clk pll2_sysclk1 = {
103 .name = "pll2_sysclk1",
104 .parent = &pll2_clk,
105 .flags = CLK_PLL,
106 .div_reg = PLLDIV1,
107};
108
109static struct clk pll2_sysclk2 = {
110 .name = "pll2_sysclk2",
111 .parent = &pll2_clk,
112 .flags = CLK_PLL,
113 .div_reg = PLLDIV2,
114};
115
116static struct clk pll2_sysclkbp = {
117 .name = "pll2_sysclkbp",
118 .parent = &pll2_clk,
119 .flags = CLK_PLL | PRE_PLL,
120 .div_reg = BPDIV
121};
122
123static struct clk dsp_clk = {
124 .name = "dsp",
125 .parent = &pll1_sysclk1,
126 .lpsc = DAVINCI_LPSC_GEM,
127 .flags = PSC_DSP,
128 .usecount = 1, /* REVISIT how to disable? */
129};
130
131static struct clk arm_clk = {
132 .name = "arm",
133 .parent = &pll1_sysclk2,
134 .lpsc = DAVINCI_LPSC_ARM,
135 .flags = ALWAYS_ENABLED,
136};
137
138static struct clk vicp_clk = {
139 .name = "vicp",
140 .parent = &pll1_sysclk2,
141 .lpsc = DAVINCI_LPSC_IMCOP,
142 .flags = PSC_DSP,
143 .usecount = 1, /* REVISIT how to disable? */
144};
145
146static struct clk vpss_master_clk = {
147 .name = "vpss_master",
148 .parent = &pll1_sysclk3,
149 .lpsc = DAVINCI_LPSC_VPSSMSTR,
150 .flags = CLK_PSC,
151};
152
153static struct clk vpss_slave_clk = {
154 .name = "vpss_slave",
155 .parent = &pll1_sysclk3,
156 .lpsc = DAVINCI_LPSC_VPSSSLV,
157};
158
159static struct clk uart0_clk = {
160 .name = "uart0",
161 .parent = &pll1_aux_clk,
162 .lpsc = DAVINCI_LPSC_UART0,
163};
164
165static struct clk uart1_clk = {
166 .name = "uart1",
167 .parent = &pll1_aux_clk,
168 .lpsc = DAVINCI_LPSC_UART1,
169};
170
171static struct clk uart2_clk = {
172 .name = "uart2",
173 .parent = &pll1_aux_clk,
174 .lpsc = DAVINCI_LPSC_UART2,
175};
176
177static struct clk emac_clk = {
178 .name = "emac",
179 .parent = &pll1_sysclk5,
180 .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
181};
182
183static struct clk i2c_clk = {
184 .name = "i2c",
185 .parent = &pll1_aux_clk,
186 .lpsc = DAVINCI_LPSC_I2C,
187};
188
189static struct clk ide_clk = {
190 .name = "ide",
191 .parent = &pll1_sysclk5,
192 .lpsc = DAVINCI_LPSC_ATA,
193};
194
195static struct clk asp_clk = {
196 .name = "asp0",
197 .parent = &pll1_sysclk5,
198 .lpsc = DAVINCI_LPSC_McBSP,
199};
200
201static struct clk mmcsd_clk = {
202 .name = "mmcsd",
203 .parent = &pll1_sysclk5,
204 .lpsc = DAVINCI_LPSC_MMC_SD,
205};
206
207static struct clk spi_clk = {
208 .name = "spi",
209 .parent = &pll1_sysclk5,
210 .lpsc = DAVINCI_LPSC_SPI,
211};
212
213static struct clk gpio_clk = {
214 .name = "gpio",
215 .parent = &pll1_sysclk5,
216 .lpsc = DAVINCI_LPSC_GPIO,
217};
218
219static struct clk usb_clk = {
220 .name = "usb",
221 .parent = &pll1_sysclk5,
222 .lpsc = DAVINCI_LPSC_USB,
223};
224
225static struct clk vlynq_clk = {
226 .name = "vlynq",
227 .parent = &pll1_sysclk5,
228 .lpsc = DAVINCI_LPSC_VLYNQ,
229};
230
231static struct clk aemif_clk = {
232 .name = "aemif",
233 .parent = &pll1_sysclk5,
234 .lpsc = DAVINCI_LPSC_AEMIF,
235};
236
237static struct clk pwm0_clk = {
238 .name = "pwm0",
239 .parent = &pll1_aux_clk,
240 .lpsc = DAVINCI_LPSC_PWM0,
241};
242
243static struct clk pwm1_clk = {
244 .name = "pwm1",
245 .parent = &pll1_aux_clk,
246 .lpsc = DAVINCI_LPSC_PWM1,
247};
248
249static struct clk pwm2_clk = {
250 .name = "pwm2",
251 .parent = &pll1_aux_clk,
252 .lpsc = DAVINCI_LPSC_PWM2,
253};
254
255static struct clk timer0_clk = {
256 .name = "timer0",
257 .parent = &pll1_aux_clk,
258 .lpsc = DAVINCI_LPSC_TIMER0,
259};
260
261static struct clk timer1_clk = {
262 .name = "timer1",
263 .parent = &pll1_aux_clk,
264 .lpsc = DAVINCI_LPSC_TIMER1,
265};
266
267static struct clk timer2_clk = {
268 .name = "timer2",
269 .parent = &pll1_aux_clk,
270 .lpsc = DAVINCI_LPSC_TIMER2,
271 .usecount = 1, /* REVISIT: why cant' this be disabled? */
272};
273
274struct davinci_clk dm644x_clks[] = {
275 CLK(NULL, "ref", &ref_clk),
276 CLK(NULL, "pll1", &pll1_clk),
277 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
278 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
279 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
280 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
281 CLK(NULL, "pll1_aux", &pll1_aux_clk),
282 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
283 CLK(NULL, "pll2", &pll2_clk),
284 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
285 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
286 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
287 CLK(NULL, "dsp", &dsp_clk),
288 CLK(NULL, "arm", &arm_clk),
289 CLK(NULL, "vicp", &vicp_clk),
290 CLK(NULL, "vpss_master", &vpss_master_clk),
291 CLK(NULL, "vpss_slave", &vpss_slave_clk),
292 CLK(NULL, "arm", &arm_clk),
293 CLK(NULL, "uart0", &uart0_clk),
294 CLK(NULL, "uart1", &uart1_clk),
295 CLK(NULL, "uart2", &uart2_clk),
296 CLK("davinci_emac.1", NULL, &emac_clk),
297 CLK("i2c_davinci.1", NULL, &i2c_clk),
298 CLK("palm_bk3710", NULL, &ide_clk),
299 CLK("soc-audio.0", NULL, &asp_clk),
300 CLK("davinci_mmc.0", NULL, &mmcsd_clk),
301 CLK(NULL, "spi", &spi_clk),
302 CLK(NULL, "gpio", &gpio_clk),
303 CLK(NULL, "usb", &usb_clk),
304 CLK(NULL, "vlynq", &vlynq_clk),
305 CLK(NULL, "aemif", &aemif_clk),
306 CLK(NULL, "pwm0", &pwm0_clk),
307 CLK(NULL, "pwm1", &pwm1_clk),
308 CLK(NULL, "pwm2", &pwm2_clk),
309 CLK(NULL, "timer0", &timer0_clk),
310 CLK(NULL, "timer1", &timer1_clk),
311 CLK("watchdog", NULL, &timer2_clk),
312 CLK(NULL, NULL, NULL),
313};
314
315#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
316
317static struct resource dm644x_emac_resources[] = {
318 {
319 .start = DM644X_EMAC_BASE,
320 .end = DM644X_EMAC_BASE + 0x47ff,
321 .flags = IORESOURCE_MEM,
322 },
323 {
324 .start = IRQ_EMACINT,
325 .end = IRQ_EMACINT,
326 .flags = IORESOURCE_IRQ,
327 },
328};
329
330static struct platform_device dm644x_emac_device = {
331 .name = "davinci_emac",
332 .id = 1,
333 .num_resources = ARRAY_SIZE(dm644x_emac_resources),
334 .resource = dm644x_emac_resources,
335};
336
337#endif
338
339/*
340 * Device specific mux setup
341 *
342 * soc description mux mode mode mux dbg
343 * reg offset mask mode
344 */
345static const struct mux_config dm644x_pins[] = {
346MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
347MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
348MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
349
350MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
351
352MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
353
354MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
355
356MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
357
358MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
359
360MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
361MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
362
363MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
364
365MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
366
367MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
368
369MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
370MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
371MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
372
373MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
374
375MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
376
377MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
378MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
379MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
380MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
381
382MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
383
384MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
385MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
386};
387
388
389/*----------------------------------------------------------------------*/
390
391static const s8 dma_chan_dm644x_no_event[] = {
392 0, 1, 12, 13, 14,
393 15, 25, 30, 31, 45,
394 46, 47, 55, 56, 57,
395 58, 59, 60, 61, 62,
396 63,
397 -1
398};
399
400static struct edma_soc_info dm644x_edma_info = {
401 .n_channel = 64,
402 .n_region = 4,
403 .n_slot = 128,
404 .n_tc = 2,
405 .noevent = dma_chan_dm644x_no_event,
406};
407
408static struct resource edma_resources[] = {
409 {
410 .name = "edma_cc",
411 .start = 0x01c00000,
412 .end = 0x01c00000 + SZ_64K - 1,
413 .flags = IORESOURCE_MEM,
414 },
415 {
416 .name = "edma_tc0",
417 .start = 0x01c10000,
418 .end = 0x01c10000 + SZ_1K - 1,
419 .flags = IORESOURCE_MEM,
420 },
421 {
422 .name = "edma_tc1",
423 .start = 0x01c10400,
424 .end = 0x01c10400 + SZ_1K - 1,
425 .flags = IORESOURCE_MEM,
426 },
427 {
428 .start = IRQ_CCINT0,
429 .flags = IORESOURCE_IRQ,
430 },
431 {
432 .start = IRQ_CCERRINT,
433 .flags = IORESOURCE_IRQ,
434 },
435 /* not using TC*_ERR */
436};
437
438static struct platform_device dm644x_edma_device = {
439 .name = "edma",
440 .id = -1,
441 .dev.platform_data = &dm644x_edma_info,
442 .num_resources = ARRAY_SIZE(edma_resources),
443 .resource = edma_resources,
444};
445
446/*----------------------------------------------------------------------*/
447void __init dm644x_init(void)
448{
449 davinci_clk_init(dm644x_clks);
450 davinci_mux_register(dm644x_pins, ARRAY_SIZE(dm644x_pins));
451}
452
453static int __init dm644x_init_devices(void)
454{
455 if (!cpu_is_davinci_dm644x())
456 return 0;
457
458 platform_device_register(&dm644x_edma_device);
459 return 0;
460}
461postcore_initcall(dm644x_init_devices);
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
new file mode 100644
index 000000000000..15e9eb158bb7
--- /dev/null
+++ b/arch/arm/mach-davinci/dma.c
@@ -0,0 +1,1135 @@
1/*
2 * EDMA3 support for DaVinci
3 *
4 * Copyright (C) 2006-2009 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20#include <linux/kernel.h>
21#include <linux/sched.h>
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/platform_device.h>
26#include <linux/spinlock.h>
27#include <linux/compiler.h>
28#include <linux/io.h>
29
30#include <mach/cputype.h>
31#include <mach/memory.h>
32#include <mach/hardware.h>
33#include <mach/irqs.h>
34#include <mach/edma.h>
35#include <mach/mux.h>
36
37
38/* Offsets matching "struct edmacc_param" */
39#define PARM_OPT 0x00
40#define PARM_SRC 0x04
41#define PARM_A_B_CNT 0x08
42#define PARM_DST 0x0c
43#define PARM_SRC_DST_BIDX 0x10
44#define PARM_LINK_BCNTRLD 0x14
45#define PARM_SRC_DST_CIDX 0x18
46#define PARM_CCNT 0x1c
47
48#define PARM_SIZE 0x20
49
50/* Offsets for EDMA CC global channel registers and their shadows */
51#define SH_ER 0x00 /* 64 bits */
52#define SH_ECR 0x08 /* 64 bits */
53#define SH_ESR 0x10 /* 64 bits */
54#define SH_CER 0x18 /* 64 bits */
55#define SH_EER 0x20 /* 64 bits */
56#define SH_EECR 0x28 /* 64 bits */
57#define SH_EESR 0x30 /* 64 bits */
58#define SH_SER 0x38 /* 64 bits */
59#define SH_SECR 0x40 /* 64 bits */
60#define SH_IER 0x50 /* 64 bits */
61#define SH_IECR 0x58 /* 64 bits */
62#define SH_IESR 0x60 /* 64 bits */
63#define SH_IPR 0x68 /* 64 bits */
64#define SH_ICR 0x70 /* 64 bits */
65#define SH_IEVAL 0x78
66#define SH_QER 0x80
67#define SH_QEER 0x84
68#define SH_QEECR 0x88
69#define SH_QEESR 0x8c
70#define SH_QSER 0x90
71#define SH_QSECR 0x94
72#define SH_SIZE 0x200
73
74/* Offsets for EDMA CC global registers */
75#define EDMA_REV 0x0000
76#define EDMA_CCCFG 0x0004
77#define EDMA_QCHMAP 0x0200 /* 8 registers */
78#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
79#define EDMA_QDMAQNUM 0x0260
80#define EDMA_QUETCMAP 0x0280
81#define EDMA_QUEPRI 0x0284
82#define EDMA_EMR 0x0300 /* 64 bits */
83#define EDMA_EMCR 0x0308 /* 64 bits */
84#define EDMA_QEMR 0x0310
85#define EDMA_QEMCR 0x0314
86#define EDMA_CCERR 0x0318
87#define EDMA_CCERRCLR 0x031c
88#define EDMA_EEVAL 0x0320
89#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
90#define EDMA_QRAE 0x0380 /* 4 registers */
91#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
92#define EDMA_QSTAT 0x0600 /* 2 registers */
93#define EDMA_QWMTHRA 0x0620
94#define EDMA_QWMTHRB 0x0624
95#define EDMA_CCSTAT 0x0640
96
97#define EDMA_M 0x1000 /* global channel registers */
98#define EDMA_ECR 0x1008
99#define EDMA_ECRH 0x100C
100#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
101#define EDMA_PARM 0x4000 /* 128 param entries */
102
103#define DAVINCI_DMA_3PCC_BASE 0x01C00000
104
105#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
106
107#define EDMA_MAX_DMACH 64
108#define EDMA_MAX_PARAMENTRY 512
109#define EDMA_MAX_EVQUE 2 /* FIXME too small */
110
111
112/*****************************************************************************/
113
114static void __iomem *edmacc_regs_base;
115
116static inline unsigned int edma_read(int offset)
117{
118 return (unsigned int)__raw_readl(edmacc_regs_base + offset);
119}
120
121static inline void edma_write(int offset, int val)
122{
123 __raw_writel(val, edmacc_regs_base + offset);
124}
125static inline void edma_modify(int offset, unsigned and, unsigned or)
126{
127 unsigned val = edma_read(offset);
128 val &= and;
129 val |= or;
130 edma_write(offset, val);
131}
132static inline void edma_and(int offset, unsigned and)
133{
134 unsigned val = edma_read(offset);
135 val &= and;
136 edma_write(offset, val);
137}
138static inline void edma_or(int offset, unsigned or)
139{
140 unsigned val = edma_read(offset);
141 val |= or;
142 edma_write(offset, val);
143}
144static inline unsigned int edma_read_array(int offset, int i)
145{
146 return edma_read(offset + (i << 2));
147}
148static inline void edma_write_array(int offset, int i, unsigned val)
149{
150 edma_write(offset + (i << 2), val);
151}
152static inline void edma_modify_array(int offset, int i,
153 unsigned and, unsigned or)
154{
155 edma_modify(offset + (i << 2), and, or);
156}
157static inline void edma_or_array(int offset, int i, unsigned or)
158{
159 edma_or(offset + (i << 2), or);
160}
161static inline void edma_or_array2(int offset, int i, int j, unsigned or)
162{
163 edma_or(offset + ((i*2 + j) << 2), or);
164}
165static inline void edma_write_array2(int offset, int i, int j, unsigned val)
166{
167 edma_write(offset + ((i*2 + j) << 2), val);
168}
169static inline unsigned int edma_shadow0_read(int offset)
170{
171 return edma_read(EDMA_SHADOW0 + offset);
172}
173static inline unsigned int edma_shadow0_read_array(int offset, int i)
174{
175 return edma_read(EDMA_SHADOW0 + offset + (i << 2));
176}
177static inline void edma_shadow0_write(int offset, unsigned val)
178{
179 edma_write(EDMA_SHADOW0 + offset, val);
180}
181static inline void edma_shadow0_write_array(int offset, int i, unsigned val)
182{
183 edma_write(EDMA_SHADOW0 + offset + (i << 2), val);
184}
185static inline unsigned int edma_parm_read(int offset, int param_no)
186{
187 return edma_read(EDMA_PARM + offset + (param_no << 5));
188}
189static inline void edma_parm_write(int offset, int param_no, unsigned val)
190{
191 edma_write(EDMA_PARM + offset + (param_no << 5), val);
192}
193static inline void edma_parm_modify(int offset, int param_no,
194 unsigned and, unsigned or)
195{
196 edma_modify(EDMA_PARM + offset + (param_no << 5), and, or);
197}
198static inline void edma_parm_and(int offset, int param_no, unsigned and)
199{
200 edma_and(EDMA_PARM + offset + (param_no << 5), and);
201}
202static inline void edma_parm_or(int offset, int param_no, unsigned or)
203{
204 edma_or(EDMA_PARM + offset + (param_no << 5), or);
205}
206
207/*****************************************************************************/
208
209/* actual number of DMA channels and slots on this silicon */
210static unsigned num_channels;
211static unsigned num_slots;
212
213static struct dma_interrupt_data {
214 void (*callback)(unsigned channel, unsigned short ch_status,
215 void *data);
216 void *data;
217} intr_data[EDMA_MAX_DMACH];
218
219/* The edma_inuse bit for each PaRAM slot is clear unless the
220 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
221 */
222static DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
223
224/* The edma_noevent bit for each channel is clear unless
225 * it doesn't trigger DMA events on this platform. It uses a
226 * bit of SOC-specific initialization code.
227 */
228static DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH);
229
230/* dummy param set used to (re)initialize parameter RAM slots */
231static const struct edmacc_param dummy_paramset = {
232 .link_bcntrld = 0xffff,
233 .ccnt = 1,
234};
235
236static const int __initconst
237queue_tc_mapping[EDMA_MAX_EVQUE + 1][2] = {
238/* {event queue no, TC no} */
239 {0, 0},
240 {1, 1},
241 {-1, -1}
242};
243
244static const int __initconst
245queue_priority_mapping[EDMA_MAX_EVQUE + 1][2] = {
246 /* {event queue no, Priority} */
247 {0, 3},
248 {1, 7},
249 {-1, -1}
250};
251
252/*****************************************************************************/
253
254static void map_dmach_queue(unsigned ch_no, enum dma_event_q queue_no)
255{
256 int bit = (ch_no & 0x7) * 4;
257
258 /* default to low priority queue */
259 if (queue_no == EVENTQ_DEFAULT)
260 queue_no = EVENTQ_1;
261
262 queue_no &= 7;
263 edma_modify_array(EDMA_DMAQNUM, (ch_no >> 3),
264 ~(0x7 << bit), queue_no << bit);
265}
266
267static void __init map_queue_tc(int queue_no, int tc_no)
268{
269 int bit = queue_no * 4;
270 edma_modify(EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
271}
272
273static void __init assign_priority_to_queue(int queue_no, int priority)
274{
275 int bit = queue_no * 4;
276 edma_modify(EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
277}
278
279static inline void
280setup_dma_interrupt(unsigned lch,
281 void (*callback)(unsigned channel, u16 ch_status, void *data),
282 void *data)
283{
284 if (!callback) {
285 edma_shadow0_write_array(SH_IECR, lch >> 5,
286 (1 << (lch & 0x1f)));
287 }
288
289 intr_data[lch].callback = callback;
290 intr_data[lch].data = data;
291
292 if (callback) {
293 edma_shadow0_write_array(SH_ICR, lch >> 5,
294 (1 << (lch & 0x1f)));
295 edma_shadow0_write_array(SH_IESR, lch >> 5,
296 (1 << (lch & 0x1f)));
297 }
298}
299
300/******************************************************************************
301 *
302 * DMA interrupt handler
303 *
304 *****************************************************************************/
305static irqreturn_t dma_irq_handler(int irq, void *data)
306{
307 int i;
308 unsigned int cnt = 0;
309
310 dev_dbg(data, "dma_irq_handler\n");
311
312 if ((edma_shadow0_read_array(SH_IPR, 0) == 0)
313 && (edma_shadow0_read_array(SH_IPR, 1) == 0))
314 return IRQ_NONE;
315
316 while (1) {
317 int j;
318 if (edma_shadow0_read_array(SH_IPR, 0))
319 j = 0;
320 else if (edma_shadow0_read_array(SH_IPR, 1))
321 j = 1;
322 else
323 break;
324 dev_dbg(data, "IPR%d %08x\n", j,
325 edma_shadow0_read_array(SH_IPR, j));
326 for (i = 0; i < 32; i++) {
327 int k = (j << 5) + i;
328 if (edma_shadow0_read_array(SH_IPR, j) & (1 << i)) {
329 /* Clear the corresponding IPR bits */
330 edma_shadow0_write_array(SH_ICR, j, (1 << i));
331 if (intr_data[k].callback) {
332 intr_data[k].callback(k, DMA_COMPLETE,
333 intr_data[k].data);
334 }
335 }
336 }
337 cnt++;
338 if (cnt > 10)
339 break;
340 }
341 edma_shadow0_write(SH_IEVAL, 1);
342 return IRQ_HANDLED;
343}
344
345/******************************************************************************
346 *
347 * DMA error interrupt handler
348 *
349 *****************************************************************************/
350static irqreturn_t dma_ccerr_handler(int irq, void *data)
351{
352 int i;
353 unsigned int cnt = 0;
354
355 dev_dbg(data, "dma_ccerr_handler\n");
356
357 if ((edma_read_array(EDMA_EMR, 0) == 0) &&
358 (edma_read_array(EDMA_EMR, 1) == 0) &&
359 (edma_read(EDMA_QEMR) == 0) && (edma_read(EDMA_CCERR) == 0))
360 return IRQ_NONE;
361
362 while (1) {
363 int j = -1;
364 if (edma_read_array(EDMA_EMR, 0))
365 j = 0;
366 else if (edma_read_array(EDMA_EMR, 1))
367 j = 1;
368 if (j >= 0) {
369 dev_dbg(data, "EMR%d %08x\n", j,
370 edma_read_array(EDMA_EMR, j));
371 for (i = 0; i < 32; i++) {
372 int k = (j << 5) + i;
373 if (edma_read_array(EDMA_EMR, j) & (1 << i)) {
374 /* Clear the corresponding EMR bits */
375 edma_write_array(EDMA_EMCR, j, 1 << i);
376 /* Clear any SER */
377 edma_shadow0_write_array(SH_SECR, j,
378 (1 << i));
379 if (intr_data[k].callback) {
380 intr_data[k].callback(k,
381 DMA_CC_ERROR,
382 intr_data
383 [k].data);
384 }
385 }
386 }
387 } else if (edma_read(EDMA_QEMR)) {
388 dev_dbg(data, "QEMR %02x\n",
389 edma_read(EDMA_QEMR));
390 for (i = 0; i < 8; i++) {
391 if (edma_read(EDMA_QEMR) & (1 << i)) {
392 /* Clear the corresponding IPR bits */
393 edma_write(EDMA_QEMCR, 1 << i);
394 edma_shadow0_write(SH_QSECR, (1 << i));
395
396 /* NOTE: not reported!! */
397 }
398 }
399 } else if (edma_read(EDMA_CCERR)) {
400 dev_dbg(data, "CCERR %08x\n",
401 edma_read(EDMA_CCERR));
402 /* FIXME: CCERR.BIT(16) ignored! much better
403 * to just write CCERRCLR with CCERR value...
404 */
405 for (i = 0; i < 8; i++) {
406 if (edma_read(EDMA_CCERR) & (1 << i)) {
407 /* Clear the corresponding IPR bits */
408 edma_write(EDMA_CCERRCLR, 1 << i);
409
410 /* NOTE: not reported!! */
411 }
412 }
413 }
414 if ((edma_read_array(EDMA_EMR, 0) == 0)
415 && (edma_read_array(EDMA_EMR, 1) == 0)
416 && (edma_read(EDMA_QEMR) == 0)
417 && (edma_read(EDMA_CCERR) == 0)) {
418 break;
419 }
420 cnt++;
421 if (cnt > 10)
422 break;
423 }
424 edma_write(EDMA_EEVAL, 1);
425 return IRQ_HANDLED;
426}
427
428/******************************************************************************
429 *
430 * Transfer controller error interrupt handlers
431 *
432 *****************************************************************************/
433
434#define tc_errs_handled false /* disabled as long as they're NOPs */
435
436static irqreturn_t dma_tc0err_handler(int irq, void *data)
437{
438 dev_dbg(data, "dma_tc0err_handler\n");
439 return IRQ_HANDLED;
440}
441
442static irqreturn_t dma_tc1err_handler(int irq, void *data)
443{
444 dev_dbg(data, "dma_tc1err_handler\n");
445 return IRQ_HANDLED;
446}
447
448/*-----------------------------------------------------------------------*/
449
450/* Resource alloc/free: dma channels, parameter RAM slots */
451
452/**
453 * edma_alloc_channel - allocate DMA channel and paired parameter RAM
454 * @channel: specific channel to allocate; negative for "any unmapped channel"
455 * @callback: optional; to be issued on DMA completion or errors
456 * @data: passed to callback
457 * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
458 * Controller (TC) executes requests using this channel. Use
459 * EVENTQ_DEFAULT unless you really need a high priority queue.
460 *
461 * This allocates a DMA channel and its associated parameter RAM slot.
462 * The parameter RAM is initialized to hold a dummy transfer.
463 *
464 * Normal use is to pass a specific channel number as @channel, to make
465 * use of hardware events mapped to that channel. When the channel will
466 * be used only for software triggering or event chaining, channels not
467 * mapped to hardware events (or mapped to unused events) are preferable.
468 *
469 * DMA transfers start from a channel using edma_start(), or by
470 * chaining. When the transfer described in that channel's parameter RAM
471 * slot completes, that slot's data may be reloaded through a link.
472 *
473 * DMA errors are only reported to the @callback associated with the
474 * channel driving that transfer, but transfer completion callbacks can
475 * be sent to another channel under control of the TCC field in
476 * the option word of the transfer's parameter RAM set. Drivers must not
477 * use DMA transfer completion callbacks for channels they did not allocate.
478 * (The same applies to TCC codes used in transfer chaining.)
479 *
480 * Returns the number of the channel, else negative errno.
481 */
482int edma_alloc_channel(int channel,
483 void (*callback)(unsigned channel, u16 ch_status, void *data),
484 void *data,
485 enum dma_event_q eventq_no)
486{
487 if (channel < 0) {
488 channel = 0;
489 for (;;) {
490 channel = find_next_bit(edma_noevent,
491 num_channels, channel);
492 if (channel == num_channels)
493 return -ENOMEM;
494 if (!test_and_set_bit(channel, edma_inuse))
495 break;
496 channel++;
497 }
498 } else if (channel >= num_channels) {
499 return -EINVAL;
500 } else if (test_and_set_bit(channel, edma_inuse)) {
501 return -EBUSY;
502 }
503
504 /* ensure access through shadow region 0 */
505 edma_or_array2(EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f));
506
507 /* ensure no events are pending */
508 edma_stop(channel);
509 memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel),
510 &dummy_paramset, PARM_SIZE);
511
512 if (callback)
513 setup_dma_interrupt(channel, callback, data);
514
515 map_dmach_queue(channel, eventq_no);
516
517 return channel;
518}
519EXPORT_SYMBOL(edma_alloc_channel);
520
521
522/**
523 * edma_free_channel - deallocate DMA channel
524 * @channel: dma channel returned from edma_alloc_channel()
525 *
526 * This deallocates the DMA channel and associated parameter RAM slot
527 * allocated by edma_alloc_channel().
528 *
529 * Callers are responsible for ensuring the channel is inactive, and
530 * will not be reactivated by linking, chaining, or software calls to
531 * edma_start().
532 */
533void edma_free_channel(unsigned channel)
534{
535 if (channel >= num_channels)
536 return;
537
538 setup_dma_interrupt(channel, NULL, NULL);
539 /* REVISIT should probably take out of shadow region 0 */
540
541 memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel),
542 &dummy_paramset, PARM_SIZE);
543 clear_bit(channel, edma_inuse);
544}
545EXPORT_SYMBOL(edma_free_channel);
546
547/**
548 * edma_alloc_slot - allocate DMA parameter RAM
549 * @slot: specific slot to allocate; negative for "any unused slot"
550 *
551 * This allocates a parameter RAM slot, initializing it to hold a
552 * dummy transfer. Slots allocated using this routine have not been
553 * mapped to a hardware DMA channel, and will normally be used by
554 * linking to them from a slot associated with a DMA channel.
555 *
556 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
557 * slots may be allocated on behalf of DSP firmware.
558 *
559 * Returns the number of the slot, else negative errno.
560 */
561int edma_alloc_slot(int slot)
562{
563 if (slot < 0) {
564 slot = num_channels;
565 for (;;) {
566 slot = find_next_zero_bit(edma_inuse,
567 num_slots, slot);
568 if (slot == num_slots)
569 return -ENOMEM;
570 if (!test_and_set_bit(slot, edma_inuse))
571 break;
572 }
573 } else if (slot < num_channels || slot >= num_slots) {
574 return -EINVAL;
575 } else if (test_and_set_bit(slot, edma_inuse)) {
576 return -EBUSY;
577 }
578
579 memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot),
580 &dummy_paramset, PARM_SIZE);
581
582 return slot;
583}
584EXPORT_SYMBOL(edma_alloc_slot);
585
586/**
587 * edma_free_slot - deallocate DMA parameter RAM
588 * @slot: parameter RAM slot returned from edma_alloc_slot()
589 *
590 * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
591 * Callers are responsible for ensuring the slot is inactive, and will
592 * not be activated.
593 */
594void edma_free_slot(unsigned slot)
595{
596 if (slot < num_channels || slot >= num_slots)
597 return;
598
599 memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot),
600 &dummy_paramset, PARM_SIZE);
601 clear_bit(slot, edma_inuse);
602}
603EXPORT_SYMBOL(edma_free_slot);
604
605/*-----------------------------------------------------------------------*/
606
607/* Parameter RAM operations (i) -- read/write partial slots */
608
609/**
610 * edma_set_src - set initial DMA source address in parameter RAM slot
611 * @slot: parameter RAM slot being configured
612 * @src_port: physical address of source (memory, controller FIFO, etc)
613 * @addressMode: INCR, except in very rare cases
614 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
615 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
616 *
617 * Note that the source address is modified during the DMA transfer
618 * according to edma_set_src_index().
619 */
620void edma_set_src(unsigned slot, dma_addr_t src_port,
621 enum address_mode mode, enum fifo_width width)
622{
623 if (slot < num_slots) {
624 unsigned int i = edma_parm_read(PARM_OPT, slot);
625
626 if (mode) {
627 /* set SAM and program FWID */
628 i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
629 } else {
630 /* clear SAM */
631 i &= ~SAM;
632 }
633 edma_parm_write(PARM_OPT, slot, i);
634
635 /* set the source port address
636 in source register of param structure */
637 edma_parm_write(PARM_SRC, slot, src_port);
638 }
639}
640EXPORT_SYMBOL(edma_set_src);
641
642/**
643 * edma_set_dest - set initial DMA destination address in parameter RAM slot
644 * @slot: parameter RAM slot being configured
645 * @dest_port: physical address of destination (memory, controller FIFO, etc)
646 * @addressMode: INCR, except in very rare cases
647 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
648 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
649 *
650 * Note that the destination address is modified during the DMA transfer
651 * according to edma_set_dest_index().
652 */
653void edma_set_dest(unsigned slot, dma_addr_t dest_port,
654 enum address_mode mode, enum fifo_width width)
655{
656 if (slot < num_slots) {
657 unsigned int i = edma_parm_read(PARM_OPT, slot);
658
659 if (mode) {
660 /* set DAM and program FWID */
661 i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
662 } else {
663 /* clear DAM */
664 i &= ~DAM;
665 }
666 edma_parm_write(PARM_OPT, slot, i);
667 /* set the destination port address
668 in dest register of param structure */
669 edma_parm_write(PARM_DST, slot, dest_port);
670 }
671}
672EXPORT_SYMBOL(edma_set_dest);
673
674/**
675 * edma_get_position - returns the current transfer points
676 * @slot: parameter RAM slot being examined
677 * @src: pointer to source port position
678 * @dst: pointer to destination port position
679 *
680 * Returns current source and destination addresses for a particular
681 * parameter RAM slot. Its channel should not be active when this is called.
682 */
683void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
684{
685 struct edmacc_param temp;
686
687 edma_read_slot(slot, &temp);
688 if (src != NULL)
689 *src = temp.src;
690 if (dst != NULL)
691 *dst = temp.dst;
692}
693EXPORT_SYMBOL(edma_get_position);
694
695/**
696 * edma_set_src_index - configure DMA source address indexing
697 * @slot: parameter RAM slot being configured
698 * @src_bidx: byte offset between source arrays in a frame
699 * @src_cidx: byte offset between source frames in a block
700 *
701 * Offsets are specified to support either contiguous or discontiguous
702 * memory transfers, or repeated access to a hardware register, as needed.
703 * When accessing hardware registers, both offsets are normally zero.
704 */
705void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
706{
707 if (slot < num_slots) {
708 edma_parm_modify(PARM_SRC_DST_BIDX, slot,
709 0xffff0000, src_bidx);
710 edma_parm_modify(PARM_SRC_DST_CIDX, slot,
711 0xffff0000, src_cidx);
712 }
713}
714EXPORT_SYMBOL(edma_set_src_index);
715
716/**
717 * edma_set_dest_index - configure DMA destination address indexing
718 * @slot: parameter RAM slot being configured
719 * @dest_bidx: byte offset between destination arrays in a frame
720 * @dest_cidx: byte offset between destination frames in a block
721 *
722 * Offsets are specified to support either contiguous or discontiguous
723 * memory transfers, or repeated access to a hardware register, as needed.
724 * When accessing hardware registers, both offsets are normally zero.
725 */
726void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
727{
728 if (slot < num_slots) {
729 edma_parm_modify(PARM_SRC_DST_BIDX, slot,
730 0x0000ffff, dest_bidx << 16);
731 edma_parm_modify(PARM_SRC_DST_CIDX, slot,
732 0x0000ffff, dest_cidx << 16);
733 }
734}
735EXPORT_SYMBOL(edma_set_dest_index);
736
737/**
738 * edma_set_transfer_params - configure DMA transfer parameters
739 * @slot: parameter RAM slot being configured
740 * @acnt: how many bytes per array (at least one)
741 * @bcnt: how many arrays per frame (at least one)
742 * @ccnt: how many frames per block (at least one)
743 * @bcnt_rld: used only for A-Synchronized transfers; this specifies
744 * the value to reload into bcnt when it decrements to zero
745 * @sync_mode: ASYNC or ABSYNC
746 *
747 * See the EDMA3 documentation to understand how to configure and link
748 * transfers using the fields in PaRAM slots. If you are not doing it
749 * all at once with edma_write_slot(), you will use this routine
750 * plus two calls each for source and destination, setting the initial
751 * address and saying how to index that address.
752 *
753 * An example of an A-Synchronized transfer is a serial link using a
754 * single word shift register. In that case, @acnt would be equal to
755 * that word size; the serial controller issues a DMA synchronization
756 * event to transfer each word, and memory access by the DMA transfer
757 * controller will be word-at-a-time.
758 *
759 * An example of an AB-Synchronized transfer is a device using a FIFO.
760 * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
761 * The controller with the FIFO issues DMA synchronization events when
762 * the FIFO threshold is reached, and the DMA transfer controller will
763 * transfer one frame to (or from) the FIFO. It will probably use
764 * efficient burst modes to access memory.
765 */
766void edma_set_transfer_params(unsigned slot,
767 u16 acnt, u16 bcnt, u16 ccnt,
768 u16 bcnt_rld, enum sync_dimension sync_mode)
769{
770 if (slot < num_slots) {
771 edma_parm_modify(PARM_LINK_BCNTRLD, slot,
772 0x0000ffff, bcnt_rld << 16);
773 if (sync_mode == ASYNC)
774 edma_parm_and(PARM_OPT, slot, ~SYNCDIM);
775 else
776 edma_parm_or(PARM_OPT, slot, SYNCDIM);
777 /* Set the acount, bcount, ccount registers */
778 edma_parm_write(PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
779 edma_parm_write(PARM_CCNT, slot, ccnt);
780 }
781}
782EXPORT_SYMBOL(edma_set_transfer_params);
783
784/**
785 * edma_link - link one parameter RAM slot to another
786 * @from: parameter RAM slot originating the link
787 * @to: parameter RAM slot which is the link target
788 *
789 * The originating slot should not be part of any active DMA transfer.
790 */
791void edma_link(unsigned from, unsigned to)
792{
793 if (from >= num_slots)
794 return;
795 if (to >= num_slots)
796 return;
797 edma_parm_modify(PARM_LINK_BCNTRLD, from, 0xffff0000, PARM_OFFSET(to));
798}
799EXPORT_SYMBOL(edma_link);
800
801/**
802 * edma_unlink - cut link from one parameter RAM slot
803 * @from: parameter RAM slot originating the link
804 *
805 * The originating slot should not be part of any active DMA transfer.
806 * Its link is set to 0xffff.
807 */
808void edma_unlink(unsigned from)
809{
810 if (from >= num_slots)
811 return;
812 edma_parm_or(PARM_LINK_BCNTRLD, from, 0xffff);
813}
814EXPORT_SYMBOL(edma_unlink);
815
816/*-----------------------------------------------------------------------*/
817
818/* Parameter RAM operations (ii) -- read/write whole parameter sets */
819
820/**
821 * edma_write_slot - write parameter RAM data for slot
822 * @slot: number of parameter RAM slot being modified
823 * @param: data to be written into parameter RAM slot
824 *
825 * Use this to assign all parameters of a transfer at once. This
826 * allows more efficient setup of transfers than issuing multiple
827 * calls to set up those parameters in small pieces, and provides
828 * complete control over all transfer options.
829 */
830void edma_write_slot(unsigned slot, const struct edmacc_param *param)
831{
832 if (slot >= num_slots)
833 return;
834 memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), param, PARM_SIZE);
835}
836EXPORT_SYMBOL(edma_write_slot);
837
838/**
839 * edma_read_slot - read parameter RAM data from slot
840 * @slot: number of parameter RAM slot being copied
841 * @param: where to store copy of parameter RAM data
842 *
843 * Use this to read data from a parameter RAM slot, perhaps to
844 * save them as a template for later reuse.
845 */
846void edma_read_slot(unsigned slot, struct edmacc_param *param)
847{
848 if (slot >= num_slots)
849 return;
850 memcpy_fromio(param, edmacc_regs_base + PARM_OFFSET(slot), PARM_SIZE);
851}
852EXPORT_SYMBOL(edma_read_slot);
853
854/*-----------------------------------------------------------------------*/
855
856/* Various EDMA channel control operations */
857
858/**
859 * edma_pause - pause dma on a channel
860 * @channel: on which edma_start() has been called
861 *
862 * This temporarily disables EDMA hardware events on the specified channel,
863 * preventing them from triggering new transfers on its behalf
864 */
865void edma_pause(unsigned channel)
866{
867 if (channel < num_channels) {
868 unsigned int mask = (1 << (channel & 0x1f));
869
870 edma_shadow0_write_array(SH_EECR, channel >> 5, mask);
871 }
872}
873EXPORT_SYMBOL(edma_pause);
874
875/**
876 * edma_resume - resumes dma on a paused channel
877 * @channel: on which edma_pause() has been called
878 *
879 * This re-enables EDMA hardware events on the specified channel.
880 */
881void edma_resume(unsigned channel)
882{
883 if (channel < num_channels) {
884 unsigned int mask = (1 << (channel & 0x1f));
885
886 edma_shadow0_write_array(SH_EESR, channel >> 5, mask);
887 }
888}
889EXPORT_SYMBOL(edma_resume);
890
891/**
892 * edma_start - start dma on a channel
893 * @channel: channel being activated
894 *
895 * Channels with event associations will be triggered by their hardware
896 * events, and channels without such associations will be triggered by
897 * software. (At this writing there is no interface for using software
898 * triggers except with channels that don't support hardware triggers.)
899 *
900 * Returns zero on success, else negative errno.
901 */
902int edma_start(unsigned channel)
903{
904 if (channel < num_channels) {
905 int j = channel >> 5;
906 unsigned int mask = (1 << (channel & 0x1f));
907
908 /* EDMA channels without event association */
909 if (test_bit(channel, edma_noevent)) {
910 pr_debug("EDMA: ESR%d %08x\n", j,
911 edma_shadow0_read_array(SH_ESR, j));
912 edma_shadow0_write_array(SH_ESR, j, mask);
913 return 0;
914 }
915
916 /* EDMA channel with event association */
917 pr_debug("EDMA: ER%d %08x\n", j,
918 edma_shadow0_read_array(SH_ER, j));
919 /* Clear any pending error */
920 edma_write_array(EDMA_EMCR, j, mask);
921 /* Clear any SER */
922 edma_shadow0_write_array(SH_SECR, j, mask);
923 edma_shadow0_write_array(SH_EESR, j, mask);
924 pr_debug("EDMA: EER%d %08x\n", j,
925 edma_shadow0_read_array(SH_EER, j));
926 return 0;
927 }
928
929 return -EINVAL;
930}
931EXPORT_SYMBOL(edma_start);
932
933/**
934 * edma_stop - stops dma on the channel passed
935 * @channel: channel being deactivated
936 *
937 * When @lch is a channel, any active transfer is paused and
938 * all pending hardware events are cleared. The current transfer
939 * may not be resumed, and the channel's Parameter RAM should be
940 * reinitialized before being reused.
941 */
942void edma_stop(unsigned channel)
943{
944 if (channel < num_channels) {
945 int j = channel >> 5;
946 unsigned int mask = (1 << (channel & 0x1f));
947
948 edma_shadow0_write_array(SH_EECR, j, mask);
949 edma_shadow0_write_array(SH_ECR, j, mask);
950 edma_shadow0_write_array(SH_SECR, j, mask);
951 edma_write_array(EDMA_EMCR, j, mask);
952
953 pr_debug("EDMA: EER%d %08x\n", j,
954 edma_shadow0_read_array(SH_EER, j));
955
956 /* REVISIT: consider guarding against inappropriate event
957 * chaining by overwriting with dummy_paramset.
958 */
959 }
960}
961EXPORT_SYMBOL(edma_stop);
962
963/******************************************************************************
964 *
965 * It cleans ParamEntry qand bring back EDMA to initial state if media has
966 * been removed before EDMA has finished.It is usedful for removable media.
967 * Arguments:
968 * ch_no - channel no
969 *
970 * Return: zero on success, or corresponding error no on failure
971 *
972 * FIXME this should not be needed ... edma_stop() should suffice.
973 *
974 *****************************************************************************/
975
976void edma_clean_channel(unsigned channel)
977{
978 if (channel < num_channels) {
979 int j = (channel >> 5);
980 unsigned int mask = 1 << (channel & 0x1f);
981
982 pr_debug("EDMA: EMR%d %08x\n", j,
983 edma_read_array(EDMA_EMR, j));
984 edma_shadow0_write_array(SH_ECR, j, mask);
985 /* Clear the corresponding EMR bits */
986 edma_write_array(EDMA_EMCR, j, mask);
987 /* Clear any SER */
988 edma_shadow0_write_array(SH_SECR, j, mask);
989 edma_write(EDMA_CCERRCLR, (1 << 16) | 0x3);
990 }
991}
992EXPORT_SYMBOL(edma_clean_channel);
993
994/*
995 * edma_clear_event - clear an outstanding event on the DMA channel
996 * Arguments:
997 * channel - channel number
998 */
999void edma_clear_event(unsigned channel)
1000{
1001 if (channel >= num_channels)
1002 return;
1003 if (channel < 32)
1004 edma_write(EDMA_ECR, 1 << channel);
1005 else
1006 edma_write(EDMA_ECRH, 1 << (channel - 32));
1007}
1008EXPORT_SYMBOL(edma_clear_event);
1009
1010/*-----------------------------------------------------------------------*/
1011
1012static int __init edma_probe(struct platform_device *pdev)
1013{
1014 struct edma_soc_info *info = pdev->dev.platform_data;
1015 int i;
1016 int status;
1017 const s8 *noevent;
1018 int irq = 0, err_irq = 0;
1019 struct resource *r;
1020 resource_size_t len;
1021
1022 if (!info)
1023 return -ENODEV;
1024
1025 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma_cc");
1026 if (!r)
1027 return -ENODEV;
1028
1029 len = r->end - r->start + 1;
1030
1031 r = request_mem_region(r->start, len, r->name);
1032 if (!r)
1033 return -EBUSY;
1034
1035 edmacc_regs_base = ioremap(r->start, len);
1036 if (!edmacc_regs_base) {
1037 status = -EBUSY;
1038 goto fail1;
1039 }
1040
1041 num_channels = min_t(unsigned, info->n_channel, EDMA_MAX_DMACH);
1042 num_slots = min_t(unsigned, info->n_slot, EDMA_MAX_PARAMENTRY);
1043
1044 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base);
1045
1046 for (i = 0; i < num_slots; i++)
1047 memcpy_toio(edmacc_regs_base + PARM_OFFSET(i),
1048 &dummy_paramset, PARM_SIZE);
1049
1050 noevent = info->noevent;
1051 if (noevent) {
1052 while (*noevent != -1)
1053 set_bit(*noevent++, edma_noevent);
1054 }
1055
1056 irq = platform_get_irq(pdev, 0);
1057 status = request_irq(irq, dma_irq_handler, 0, "edma", &pdev->dev);
1058 if (status < 0) {
1059 dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1060 irq, status);
1061 goto fail;
1062 }
1063
1064 err_irq = platform_get_irq(pdev, 1);
1065 status = request_irq(err_irq, dma_ccerr_handler, 0,
1066 "edma_error", &pdev->dev);
1067 if (status < 0) {
1068 dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1069 err_irq, status);
1070 goto fail;
1071 }
1072
1073 if (tc_errs_handled) {
1074 status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0,
1075 "edma_tc0", &pdev->dev);
1076 if (status < 0) {
1077 dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1078 IRQ_TCERRINT0, status);
1079 return status;
1080 }
1081 status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0,
1082 "edma_tc1", &pdev->dev);
1083 if (status < 0) {
1084 dev_dbg(&pdev->dev, "request_irq %d --> %d\n",
1085 IRQ_TCERRINT, status);
1086 return status;
1087 }
1088 }
1089
1090 /* Everything lives on transfer controller 1 until otherwise specified.
1091 * This way, long transfers on the low priority queue
1092 * started by the codec engine will not cause audio defects.
1093 */
1094 for (i = 0; i < num_channels; i++)
1095 map_dmach_queue(i, EVENTQ_1);
1096
1097 /* Event queue to TC mapping */
1098 for (i = 0; queue_tc_mapping[i][0] != -1; i++)
1099 map_queue_tc(queue_tc_mapping[i][0], queue_tc_mapping[i][1]);
1100
1101 /* Event queue priority mapping */
1102 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1103 assign_priority_to_queue(queue_priority_mapping[i][0],
1104 queue_priority_mapping[i][1]);
1105
1106 for (i = 0; i < info->n_region; i++) {
1107 edma_write_array2(EDMA_DRAE, i, 0, 0x0);
1108 edma_write_array2(EDMA_DRAE, i, 1, 0x0);
1109 edma_write_array(EDMA_QRAE, i, 0x0);
1110 }
1111
1112 return 0;
1113
1114fail:
1115 if (err_irq)
1116 free_irq(err_irq, NULL);
1117 if (irq)
1118 free_irq(irq, NULL);
1119 iounmap(edmacc_regs_base);
1120fail1:
1121 release_mem_region(r->start, len);
1122 return status;
1123}
1124
1125
1126static struct platform_driver edma_driver = {
1127 .driver.name = "edma",
1128};
1129
1130static int __init edma_init(void)
1131{
1132 return platform_driver_probe(&edma_driver, edma_probe);
1133}
1134arch_initcall(edma_init);
1135
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index b49e9d092aab..1aba41c6351e 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -20,6 +20,7 @@
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/bitops.h> 21#include <linux/bitops.h>
22 22
23#include <mach/cputype.h>
23#include <mach/irqs.h> 24#include <mach/irqs.h>
24#include <mach/hardware.h> 25#include <mach/hardware.h>
25#include <mach/gpio.h> 26#include <mach/gpio.h>
@@ -36,9 +37,10 @@ struct davinci_gpio {
36 37
37static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; 38static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
38 39
40static unsigned __initdata ngpio;
39 41
40/* create a non-inlined version */ 42/* create a non-inlined version */
41static struct gpio_controller *__iomem __init gpio2controller(unsigned gpio) 43static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
42{ 44{
43 return __gpio_to_controller(gpio); 45 return __gpio_to_controller(gpio);
44} 46}
@@ -114,9 +116,30 @@ static int __init davinci_gpio_setup(void)
114{ 116{
115 int i, base; 117 int i, base;
116 118
117 for (i = 0, base = 0; 119 /* The gpio banks conceptually expose a segmented bitmap,
118 i < ARRAY_SIZE(chips); 120 * and "ngpio" is one more than the largest zero-based
119 i++, base += 32) { 121 * bit index that's valid.
122 */
123 if (cpu_is_davinci_dm355()) { /* or dm335() */
124 ngpio = 104;
125 } else if (cpu_is_davinci_dm644x()) { /* or dm337() */
126 ngpio = 71;
127 } else if (cpu_is_davinci_dm646x()) {
128 /* NOTE: each bank has several "reserved" bits,
129 * unusable as GPIOs. Only 33 of the GPIO numbers
130 * are usable, and we're not rejecting the others.
131 */
132 ngpio = 43;
133 } else {
134 /* if cpu_is_davinci_dm643x() ngpio = 111 */
135 pr_err("GPIO setup: how many GPIOs?\n");
136 return -EINVAL;
137 }
138
139 if (WARN_ON(DAVINCI_N_GPIO < ngpio))
140 ngpio = DAVINCI_N_GPIO;
141
142 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
120 chips[i].chip.label = "DaVinci"; 143 chips[i].chip.label = "DaVinci";
121 144
122 chips[i].chip.direction_input = davinci_direction_in; 145 chips[i].chip.direction_input = davinci_direction_in;
@@ -125,7 +148,7 @@ static int __init davinci_gpio_setup(void)
125 chips[i].chip.set = davinci_gpio_set; 148 chips[i].chip.set = davinci_gpio_set;
126 149
127 chips[i].chip.base = base; 150 chips[i].chip.base = base;
128 chips[i].chip.ngpio = DAVINCI_N_GPIO - base; 151 chips[i].chip.ngpio = ngpio - base;
129 if (chips[i].chip.ngpio > 32) 152 if (chips[i].chip.ngpio > 32)
130 chips[i].chip.ngpio = 32; 153 chips[i].chip.ngpio = 32;
131 154
@@ -143,11 +166,11 @@ pure_initcall(davinci_gpio_setup);
143 * We expect irqs will normally be set up as input pins, but they can also be 166 * We expect irqs will normally be set up as input pins, but they can also be
144 * used as output pins ... which is convenient for testing. 167 * used as output pins ... which is convenient for testing.
145 * 168 *
146 * NOTE: GPIO0..GPIO7 also have direct INTC hookups, which work in addition 169 * NOTE: The first few GPIOs also have direct INTC hookups in addition
147 * to their GPIOBNK0 irq (but with a bit less overhead). But we don't have 170 * to their GPIOBNK0 irq, with a bit less overhead but less flexibility
148 * a good way to hook those up ... 171 * on triggering (e.g. no edge options). We don't try to use those.
149 * 172 *
150 * All those INTC hookups (GPIO0..GPIO7 plus five IRQ banks) can also 173 * All those INTC hookups (direct, plus several IRQ banks) can also
151 * serve as EDMA event triggers. 174 * serve as EDMA event triggers.
152 */ 175 */
153 176
@@ -235,29 +258,42 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
235} 258}
236 259
237/* 260/*
238 * NOTE: for suspend/resume, probably best to make a sysdev (and class) 261 * NOTE: for suspend/resume, probably best to make a platform_device with
239 * with its suspend/resume calls hooking into the results of the set_wake() 262 * suspend_late/resume_resume calls hooking into results of the set_wake()
240 * calls ... so if no gpios are wakeup events the clock can be disabled, 263 * calls ... so if no gpios are wakeup events the clock can be disabled,
241 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 264 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
242 * can be set appropriately for GPIOV33 pins. 265 * (dm6446) can be set appropriately for GPIOV33 pins.
243 */ 266 */
244 267
245static int __init davinci_gpio_irq_setup(void) 268static int __init davinci_gpio_irq_setup(void)
246{ 269{
247 unsigned gpio, irq, bank; 270 unsigned gpio, irq, bank;
271 unsigned bank_irq;
248 struct clk *clk; 272 struct clk *clk;
273 u32 binten = 0;
274
275 if (cpu_is_davinci_dm355()) { /* or dm335() */
276 bank_irq = IRQ_DM355_GPIOBNK0;
277 } else if (cpu_is_davinci_dm644x()) {
278 bank_irq = IRQ_GPIOBNK0;
279 } else if (cpu_is_davinci_dm646x()) {
280 bank_irq = IRQ_DM646X_GPIOBNK0;
281 } else {
282 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
283 return -EINVAL;
284 }
249 285
250 clk = clk_get(NULL, "gpio"); 286 clk = clk_get(NULL, "gpio");
251 if (IS_ERR(clk)) { 287 if (IS_ERR(clk)) {
252 printk(KERN_ERR "Error %ld getting gpio clock?\n", 288 printk(KERN_ERR "Error %ld getting gpio clock?\n",
253 PTR_ERR(clk)); 289 PTR_ERR(clk));
254 return 0; 290 return PTR_ERR(clk);
255 } 291 }
256
257 clk_enable(clk); 292 clk_enable(clk);
258 293
259 for (gpio = 0, irq = gpio_to_irq(0), bank = IRQ_GPIOBNK0; 294 for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
260 gpio < DAVINCI_N_GPIO; bank++) { 295 gpio < ngpio;
296 bank++, bank_irq++) {
261 struct gpio_controller *__iomem g = gpio2controller(gpio); 297 struct gpio_controller *__iomem g = gpio2controller(gpio);
262 unsigned i; 298 unsigned i;
263 299
@@ -265,28 +301,28 @@ static int __init davinci_gpio_irq_setup(void)
265 __raw_writel(~0, &g->clr_rising); 301 __raw_writel(~0, &g->clr_rising);
266 302
267 /* set up all irqs in this bank */ 303 /* set up all irqs in this bank */
268 set_irq_chained_handler(bank, gpio_irq_handler); 304 set_irq_chained_handler(bank_irq, gpio_irq_handler);
269 set_irq_chip_data(bank, g); 305 set_irq_chip_data(bank_irq, g);
270 set_irq_data(bank, (void *)irq); 306 set_irq_data(bank_irq, (void *)irq);
271 307
272 for (i = 0; i < 16 && gpio < DAVINCI_N_GPIO; 308 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
273 i++, irq++, gpio++) {
274 set_irq_chip(irq, &gpio_irqchip); 309 set_irq_chip(irq, &gpio_irqchip);
275 set_irq_chip_data(irq, g); 310 set_irq_chip_data(irq, g);
276 set_irq_handler(irq, handle_simple_irq); 311 set_irq_handler(irq, handle_simple_irq);
277 set_irq_flags(irq, IRQF_VALID); 312 set_irq_flags(irq, IRQF_VALID);
278 } 313 }
314
315 binten |= BIT(bank);
279 } 316 }
280 317
281 /* BINTEN -- per-bank interrupt enable. genirq would also let these 318 /* BINTEN -- per-bank interrupt enable. genirq would also let these
282 * bits be set/cleared dynamically. 319 * bits be set/cleared dynamically.
283 */ 320 */
284 __raw_writel(0x1f, (void *__iomem) 321 __raw_writel(binten, (void *__iomem)
285 IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08)); 322 IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08));
286 323
287 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); 324 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
288 325
289 return 0; 326 return 0;
290} 327}
291
292arch_initcall(davinci_gpio_irq_setup); 328arch_initcall(davinci_gpio_irq_setup);
diff --git a/arch/arm/mach-davinci/id.c b/arch/arm/mach-davinci/id.c
index bf067d604918..018b994cd794 100644
--- a/arch/arm/mach-davinci/id.c
+++ b/arch/arm/mach-davinci/id.c
@@ -15,7 +15,9 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/io.h> 16#include <linux/io.h>
17 17
18#define JTAG_ID_BASE 0x01c40028 18#define JTAG_ID_BASE IO_ADDRESS(0x01c40028)
19
20static unsigned int davinci_revision;
19 21
20struct davinci_id { 22struct davinci_id {
21 u8 variant; /* JTAG ID bits 31:28 */ 23 u8 variant; /* JTAG ID bits 31:28 */
@@ -33,6 +35,20 @@ static struct davinci_id davinci_ids[] __initdata = {
33 .manufacturer = 0x017, 35 .manufacturer = 0x017,
34 .type = 0x64460000, 36 .type = 0x64460000,
35 }, 37 },
38 {
39 /* DM646X */
40 .part_no = 0xb770,
41 .variant = 0x0,
42 .manufacturer = 0x017,
43 .type = 0x64670000,
44 },
45 {
46 /* DM355 */
47 .part_no = 0xb73b,
48 .variant = 0x0,
49 .manufacturer = 0x00f,
50 .type = 0x03550000,
51 },
36}; 52};
37 53
38/* 54/*
@@ -42,7 +58,7 @@ static u16 __init davinci_get_part_no(void)
42{ 58{
43 u32 dev_id, part_no; 59 u32 dev_id, part_no;
44 60
45 dev_id = davinci_readl(JTAG_ID_BASE); 61 dev_id = __raw_readl(JTAG_ID_BASE);
46 62
47 part_no = ((dev_id >> 12) & 0xffff); 63 part_no = ((dev_id >> 12) & 0xffff);
48 64
@@ -56,13 +72,19 @@ static u8 __init davinci_get_variant(void)
56{ 72{
57 u32 variant; 73 u32 variant;
58 74
59 variant = davinci_readl(JTAG_ID_BASE); 75 variant = __raw_readl(JTAG_ID_BASE);
60 76
61 variant = (variant >> 28) & 0xf; 77 variant = (variant >> 28) & 0xf;
62 78
63 return variant; 79 return variant;
64} 80}
65 81
82unsigned int davinci_rev(void)
83{
84 return davinci_revision >> 16;
85}
86EXPORT_SYMBOL(davinci_rev);
87
66void __init davinci_check_revision(void) 88void __init davinci_check_revision(void)
67{ 89{
68 int i; 90 int i;
@@ -75,7 +97,7 @@ void __init davinci_check_revision(void)
75 /* First check only the major version in a safe way */ 97 /* First check only the major version in a safe way */
76 for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { 98 for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) {
77 if (part_no == (davinci_ids[i].part_no)) { 99 if (part_no == (davinci_ids[i].part_no)) {
78 system_rev = davinci_ids[i].type; 100 davinci_revision = davinci_ids[i].type;
79 break; 101 break;
80 } 102 }
81 } 103 }
@@ -84,10 +106,11 @@ void __init davinci_check_revision(void)
84 for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { 106 for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) {
85 if (part_no == davinci_ids[i].part_no && 107 if (part_no == davinci_ids[i].part_no &&
86 variant == davinci_ids[i].variant) { 108 variant == davinci_ids[i].variant) {
87 system_rev = davinci_ids[i].type; 109 davinci_revision = davinci_ids[i].type;
88 break; 110 break;
89 } 111 }
90 } 112 }
91 113
92 printk("DaVinci DM%04x variant 0x%x\n", system_rev >> 16, variant); 114 printk(KERN_INFO "DaVinci DM%04x variant 0x%x\n",
115 davinci_rev(), variant);
93} 116}
diff --git a/arch/arm/mach-davinci/include/mach/board-dm6446evm.h b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h
new file mode 100644
index 000000000000..3216f21c1238
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h
@@ -0,0 +1,20 @@
1/*
2 * DaVinci DM6446 EVM board specific headers
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or ifndef.
10 */
11
12#ifndef _MACH_DAVINCI_DM6446EVM_H
13#define _MACH_DAVINCI_DM6446EVM_H
14
15#include <linux/types.h>
16
17int dm6446evm_eeprom_read(char *buf, off_t off, size_t count);
18int dm6446evm_eeprom_write(char *buf, off_t off, size_t count);
19
20#endif
diff --git a/arch/arm/mach-davinci/include/mach/clkdev.h b/arch/arm/mach-davinci/include/mach/clkdev.h
new file mode 100644
index 000000000000..730c49d1ebd8
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/clkdev.h
@@ -0,0 +1,13 @@
1#ifndef __MACH_CLKDEV_H
2#define __MACH_CLKDEV_H
3
4static inline int __clk_get(struct clk *clk)
5{
6 return 1;
7}
8
9static inline void __clk_put(struct clk *clk)
10{
11}
12
13#endif
diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h
index 38bdd49bc181..a3b040219876 100644
--- a/arch/arm/mach-davinci/include/mach/clock.h
+++ b/arch/arm/mach-davinci/include/mach/clock.h
@@ -17,6 +17,5 @@ struct clk;
17 17
18extern int clk_register(struct clk *clk); 18extern int clk_register(struct clk *clk);
19extern void clk_unregister(struct clk *clk); 19extern void clk_unregister(struct clk *clk);
20extern int davinci_clk_init(void);
21 20
22#endif 21#endif
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 4b522e5c70ec..191770976250 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -16,6 +16,12 @@ struct sys_timer;
16 16
17extern struct sys_timer davinci_timer; 17extern struct sys_timer davinci_timer;
18 18
19extern void davinci_irq_init(void);
20extern void davinci_map_common_io(void);
21
22/* parameters describe VBUS sourcing for host mode */
23extern void setup_usb(unsigned mA, unsigned potpgt_msec);
24
19/* parameters describe VBUS sourcing for host mode */ 25/* parameters describe VBUS sourcing for host mode */
20extern void setup_usb(unsigned mA, unsigned potpgt_msec); 26extern void setup_usb(unsigned mA, unsigned potpgt_msec);
21 27
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
new file mode 100644
index 000000000000..27cfb1b3a662
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -0,0 +1,49 @@
1/*
2 * DaVinci CPU type detection
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * Defines the cpu_is_*() macros for runtime detection of DaVinci
7 * device type. In addtion, if support for a given device is not
8 * compiled in to the kernel, the macros return 0 so that
9 * resulting code can be optimized out.
10 *
11 * 2009 (c) Deep Root Systems, LLC. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16#ifndef _ASM_ARCH_CPU_H
17#define _ASM_ARCH_CPU_H
18
19extern unsigned int davinci_rev(void);
20
21#define IS_DAVINCI_CPU(type, id) \
22static inline int is_davinci_dm ##type(void) \
23{ \
24 return (davinci_rev() == (id)) ? 1 : 0; \
25}
26
27IS_DAVINCI_CPU(644x, 0x6446)
28IS_DAVINCI_CPU(646x, 0x6467)
29IS_DAVINCI_CPU(355, 0x355)
30
31#ifdef CONFIG_ARCH_DAVINCI_DM644x
32#define cpu_is_davinci_dm644x() is_davinci_dm644x()
33#else
34#define cpu_is_davinci_dm644x() 0
35#endif
36
37#ifdef CONFIG_ARCH_DAVINCI_DM646x
38#define cpu_is_davinci_dm646x() is_davinci_dm646x()
39#else
40#define cpu_is_davinci_dm646x() 0
41#endif
42
43#ifdef CONFIG_ARCH_DAVINCI_DM355
44#define cpu_is_davinci_dm355() is_davinci_dm355()
45#else
46#define cpu_is_davinci_dm355() 0
47#endif
48
49#endif
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
new file mode 100644
index 000000000000..3dcb9f4e58b4
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -0,0 +1,37 @@
1/*
2 * This file contains the processor specific definitions
3 * of the TI DM644x.
4 *
5 * Copyright (C) 2008 Texas Instruments.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22#ifndef __ASM_ARCH_DM644X_H
23#define __ASM_ARCH_DM644X_H
24
25#include <linux/platform_device.h>
26#include <mach/hardware.h>
27
28#define DM644X_EMAC_BASE (0x01C80000)
29#define DM644X_EMAC_CNTRL_OFFSET (0x0000)
30#define DM644X_EMAC_CNTRL_MOD_OFFSET (0x1000)
31#define DM644X_EMAC_CNTRL_RAM_OFFSET (0x2000)
32#define DM644X_EMAC_MDIO_OFFSET (0x4000)
33#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000)
34
35void __init dm644x_init(void);
36
37#endif /* __ASM_ARCH_DM644X_H */
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
new file mode 100644
index 000000000000..f6fc5396dafc
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -0,0 +1,228 @@
1/*
2 * TI DAVINCI dma definitions
3 *
4 * Copyright (C) 2006-2009 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 */
27
28/*
29 * This EDMA3 programming framework exposes two basic kinds of resource:
30 *
31 * Channel Triggers transfers, usually from a hardware event but
32 * also manually or by "chaining" from DMA completions.
33 * Each channel is coupled to a Parameter RAM (PaRAM) slot.
34 *
35 * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
36 * "set"), source and destination addresses, a link to a
37 * next PaRAM slot (if any), options for the transfer, and
38 * instructions for updating those addresses. There are
39 * more than twice as many slots as event channels.
40 *
41 * Each PaRAM set describes a sequence of transfers, either for one large
42 * buffer or for several discontiguous smaller buffers. An EDMA transfer
43 * is driven only from a channel, which performs the transfers specified
44 * in its PaRAM slot until there are no more transfers. When that last
45 * transfer completes, the "link" field may be used to reload the channel's
46 * PaRAM slot with a new transfer descriptor.
47 *
48 * The EDMA Channel Controller (CC) maps requests from channels into physical
49 * Transfer Controller (TC) requests when the channel triggers (by hardware
50 * or software events, or by chaining). The two physical DMA channels provided
51 * by the TCs are thus shared by many logical channels.
52 *
53 * DaVinci hardware also has a "QDMA" mechanism which is not currently
54 * supported through this interface. (DSP firmware uses it though.)
55 */
56
57#ifndef EDMA_H_
58#define EDMA_H_
59
60/* PaRAM slots are laid out like this */
61struct edmacc_param {
62 unsigned int opt;
63 unsigned int src;
64 unsigned int a_b_cnt;
65 unsigned int dst;
66 unsigned int src_dst_bidx;
67 unsigned int link_bcntrld;
68 unsigned int src_dst_cidx;
69 unsigned int ccnt;
70};
71
72#define CCINT0_INTERRUPT 16
73#define CCERRINT_INTERRUPT 17
74#define TCERRINT0_INTERRUPT 18
75#define TCERRINT1_INTERRUPT 19
76
77/* fields in edmacc_param.opt */
78#define SAM BIT(0)
79#define DAM BIT(1)
80#define SYNCDIM BIT(2)
81#define STATIC BIT(3)
82#define EDMA_FWID (0x07 << 8)
83#define TCCMODE BIT(11)
84#define EDMA_TCC(t) ((t) << 12)
85#define TCINTEN BIT(20)
86#define ITCINTEN BIT(21)
87#define TCCHEN BIT(22)
88#define ITCCHEN BIT(23)
89
90#define TRWORD (0x7<<2)
91#define PAENTRY (0x1ff<<5)
92
93/* Drivers should avoid using these symbolic names for dm644x
94 * channels, and use platform_device IORESOURCE_DMA resources
95 * instead. (Other DaVinci chips have different peripherals
96 * and thus have different DMA channel mappings.)
97 */
98#define DAVINCI_DMA_MCBSP_TX 2
99#define DAVINCI_DMA_MCBSP_RX 3
100#define DAVINCI_DMA_VPSS_HIST 4
101#define DAVINCI_DMA_VPSS_H3A 5
102#define DAVINCI_DMA_VPSS_PRVU 6
103#define DAVINCI_DMA_VPSS_RSZ 7
104#define DAVINCI_DMA_IMCOP_IMXINT 8
105#define DAVINCI_DMA_IMCOP_VLCDINT 9
106#define DAVINCI_DMA_IMCO_PASQINT 10
107#define DAVINCI_DMA_IMCOP_DSQINT 11
108#define DAVINCI_DMA_SPI_SPIX 16
109#define DAVINCI_DMA_SPI_SPIR 17
110#define DAVINCI_DMA_UART0_URXEVT0 18
111#define DAVINCI_DMA_UART0_UTXEVT0 19
112#define DAVINCI_DMA_UART1_URXEVT1 20
113#define DAVINCI_DMA_UART1_UTXEVT1 21
114#define DAVINCI_DMA_UART2_URXEVT2 22
115#define DAVINCI_DMA_UART2_UTXEVT2 23
116#define DAVINCI_DMA_MEMSTK_MSEVT 24
117#define DAVINCI_DMA_MMCRXEVT 26
118#define DAVINCI_DMA_MMCTXEVT 27
119#define DAVINCI_DMA_I2C_ICREVT 28
120#define DAVINCI_DMA_I2C_ICXEVT 29
121#define DAVINCI_DMA_GPIO_GPINT0 32
122#define DAVINCI_DMA_GPIO_GPINT1 33
123#define DAVINCI_DMA_GPIO_GPINT2 34
124#define DAVINCI_DMA_GPIO_GPINT3 35
125#define DAVINCI_DMA_GPIO_GPINT4 36
126#define DAVINCI_DMA_GPIO_GPINT5 37
127#define DAVINCI_DMA_GPIO_GPINT6 38
128#define DAVINCI_DMA_GPIO_GPINT7 39
129#define DAVINCI_DMA_GPIO_GPBNKINT0 40
130#define DAVINCI_DMA_GPIO_GPBNKINT1 41
131#define DAVINCI_DMA_GPIO_GPBNKINT2 42
132#define DAVINCI_DMA_GPIO_GPBNKINT3 43
133#define DAVINCI_DMA_GPIO_GPBNKINT4 44
134#define DAVINCI_DMA_TIMER0_TINT0 48
135#define DAVINCI_DMA_TIMER1_TINT1 49
136#define DAVINCI_DMA_TIMER2_TINT2 50
137#define DAVINCI_DMA_TIMER3_TINT3 51
138#define DAVINCI_DMA_PWM0 52
139#define DAVINCI_DMA_PWM1 53
140#define DAVINCI_DMA_PWM2 54
141
142/*ch_status paramater of callback function possible values*/
143#define DMA_COMPLETE 1
144#define DMA_CC_ERROR 2
145#define DMA_TC1_ERROR 3
146#define DMA_TC2_ERROR 4
147
148enum address_mode {
149 INCR = 0,
150 FIFO = 1
151};
152
153enum fifo_width {
154 W8BIT = 0,
155 W16BIT = 1,
156 W32BIT = 2,
157 W64BIT = 3,
158 W128BIT = 4,
159 W256BIT = 5
160};
161
162enum dma_event_q {
163 EVENTQ_0 = 0,
164 EVENTQ_1 = 1,
165 EVENTQ_DEFAULT = -1
166};
167
168enum sync_dimension {
169 ASYNC = 0,
170 ABSYNC = 1
171};
172
173#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
174#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
175
176/* alloc/free DMA channels and their dedicated parameter RAM slots */
177int edma_alloc_channel(int channel,
178 void (*callback)(unsigned channel, u16 ch_status, void *data),
179 void *data, enum dma_event_q);
180void edma_free_channel(unsigned channel);
181
182/* alloc/free parameter RAM slots */
183int edma_alloc_slot(int slot);
184void edma_free_slot(unsigned slot);
185
186/* calls that operate on part of a parameter RAM slot */
187void edma_set_src(unsigned slot, dma_addr_t src_port,
188 enum address_mode mode, enum fifo_width);
189void edma_set_dest(unsigned slot, dma_addr_t dest_port,
190 enum address_mode mode, enum fifo_width);
191void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
192void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
193void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
194void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
195 u16 bcnt_rld, enum sync_dimension sync_mode);
196void edma_link(unsigned from, unsigned to);
197void edma_unlink(unsigned from);
198
199/* calls that operate on an entire parameter RAM slot */
200void edma_write_slot(unsigned slot, const struct edmacc_param *params);
201void edma_read_slot(unsigned slot, struct edmacc_param *params);
202
203/* channel control operations */
204int edma_start(unsigned channel);
205void edma_stop(unsigned channel);
206void edma_clean_channel(unsigned channel);
207void edma_clear_event(unsigned channel);
208void edma_pause(unsigned channel);
209void edma_resume(unsigned channel);
210
211/* UNRELATED TO DMA */
212int davinci_alloc_iram(unsigned size);
213void davinci_free_iram(unsigned addr, unsigned size);
214
215/* platform_data for EDMA driver */
216struct edma_soc_info {
217
218 /* how many dma resources of each type */
219 unsigned n_channel;
220 unsigned n_region;
221 unsigned n_slot;
222 unsigned n_tc;
223
224 /* list of channels with no even trigger; terminated by "-1" */
225 const s8 *noevent;
226};
227
228#endif
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index b456f079f43f..efe3281364e6 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -15,9 +15,11 @@
15 15
16#include <linux/io.h> 16#include <linux/io.h>
17#include <asm-generic/gpio.h> 17#include <asm-generic/gpio.h>
18#include <mach/hardware.h> 18
19#include <mach/irqs.h> 19#include <mach/irqs.h>
20 20
21#define DAVINCI_GPIO_BASE 0x01C67000
22
21/* 23/*
22 * basic gpio routines 24 * basic gpio routines
23 * 25 *
@@ -26,23 +28,18 @@
26 * go through boot loaders. 28 * go through boot loaders.
27 * 29 *
28 * the gpio clock will be turned on when gpios are used, and you may also 30 * the gpio clock will be turned on when gpios are used, and you may also
29 * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are 31 * need to pay attention to PINMUX registers to be sure those pins are
30 * used as gpios, not with other peripherals. 32 * used as gpios, not with other peripherals.
31 * 33 *
32 * On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, 34 * On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation,
33 * and maybe for later updates, code should write GPIO(N) or: 35 * and maybe for later updates, code may write GPIO(N). These may be
34 * - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53) 36 * all 1.8V signals, all 3.3V ones, or a mix of the two. A given chip
35 * - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70) 37 * may not support all the GPIOs in that range.
36 *
37 * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc
38 * for now, that's != GPIO(N)
39 * 38 *
40 * GPIOs can also be on external chips, numbered after the ones built-in 39 * GPIOs can also be on external chips, numbered after the ones built-in
41 * to the DaVinci chip. For now, they won't be usable as IRQ sources. 40 * to the DaVinci chip. For now, they won't be usable as IRQ sources.
42 */ 41 */
43#define GPIO(X) (X) /* 0 <= X <= 70 */ 42#define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */
44#define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */
45#define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */
46 43
47struct gpio_controller { 44struct gpio_controller {
48 u32 dir; 45 u32 dir;
@@ -71,12 +68,14 @@ __gpio_to_controller(unsigned gpio)
71{ 68{
72 void *__iomem ptr; 69 void *__iomem ptr;
73 70
74 if (gpio < 32) 71 if (gpio < 32 * 1)
75 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10); 72 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
76 else if (gpio < 64) 73 else if (gpio < 32 * 2)
77 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38); 74 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
78 else if (gpio < DAVINCI_N_GPIO) 75 else if (gpio < 32 * 3)
79 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60); 76 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
77 else if (gpio < 32 * 4)
78 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x88);
80 else 79 else
81 ptr = NULL; 80 ptr = NULL;
82 return ptr; 81 return ptr;
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index a2e8969afaca..48c77934d519 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -1,9 +1,9 @@
1/* 1/*
2 * Common hardware definitions 2 * Hardware definitions common to all DaVinci family processors
3 * 3 *
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 * 5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under 6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program 7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express 8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 9 * or implied.
@@ -12,41 +12,16 @@
12#define __ASM_ARCH_HARDWARE_H 12#define __ASM_ARCH_HARDWARE_H
13 13
14/* 14/*
15 * Base register addresses 15 * Before you add anything to ths file:
16 *
17 * This header is for defines common to ALL DaVinci family chips.
18 * Anything that is chip specific should go in <chipname>.h,
19 * and the chip/board init code should then explicitly include
20 * <chipname>.h
16 */ 21 */
17#define DAVINCI_DMA_3PCC_BASE (0x01C00000) 22#define DAVINCI_SYSTEM_MODULE_BASE 0x01C40000
18#define DAVINCI_DMA_3PTC0_BASE (0x01C10000) 23
19#define DAVINCI_DMA_3PTC1_BASE (0x01C10400) 24/* System control register offsets */
20#define DAVINCI_I2C_BASE (0x01C21000) 25#define DM64XX_VDD3P3V_PWDN 0x48
21#define DAVINCI_PWM0_BASE (0x01C22000)
22#define DAVINCI_PWM1_BASE (0x01C22400)
23#define DAVINCI_PWM2_BASE (0x01C22800)
24#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000)
25#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800)
26#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00)
27#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000)
28#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000)
29#define DAVINCI_IEEE1394_BASE (0x01C60000)
30#define DAVINCI_USB_OTG_BASE (0x01C64000)
31#define DAVINCI_CFC_ATA_BASE (0x01C66000)
32#define DAVINCI_SPI_BASE (0x01C66800)
33#define DAVINCI_GPIO_BASE (0x01C67000)
34#define DAVINCI_UHPI_BASE (0x01C67800)
35#define DAVINCI_VPSS_REGS_BASE (0x01C70000)
36#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000)
37#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000)
38#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000)
39#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000)
40#define DAVINCI_IMCOP_BASE (0x01CC0000)
41#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000)
42#define DAVINCI_VLYNQ_BASE (0x01E01000)
43#define DAVINCI_MCBSP_BASE (0x01E02000)
44#define DAVINCI_MMC_SD_BASE (0x01E10000)
45#define DAVINCI_MS_BASE (0x01E20000)
46#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
47#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
48#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
49#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
50#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000)
51 26
52#endif /* __ASM_ARCH_HARDWARE_H */ 27#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index a48795fd2417..2479785405af 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -40,22 +40,12 @@
40#else 40#else
41#define IOMEM(x) ((void __force __iomem *)(x)) 41#define IOMEM(x) ((void __force __iomem *)(x))
42 42
43/* 43#define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t)
44 * Functions to access the DaVinci IO region 44#define __arch_iounmap(v) davinci_iounmap(v)
45 *
46 * NOTE: - Use davinci_read/write[bwl] for physical register addresses
47 * - Use __raw_read/write[bwl]() for virtual register addresses
48 * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
49 * - DO NOT use hardcoded virtual addresses to allow changing the
50 * IO address space again if needed
51 */
52#define davinci_readb(a) __raw_readb(IO_ADDRESS(a))
53#define davinci_readw(a) __raw_readw(IO_ADDRESS(a))
54#define davinci_readl(a) __raw_readl(IO_ADDRESS(a))
55 45
56#define davinci_writeb(v, a) __raw_writeb(v, IO_ADDRESS(a)) 46void __iomem *davinci_ioremap(unsigned long phys, size_t size,
57#define davinci_writew(v, a) __raw_writew(v, IO_ADDRESS(a)) 47 unsigned int type);
58#define davinci_writel(v, a) __raw_writel(v, IO_ADDRESS(a)) 48void davinci_iounmap(volatile void __iomem *addr);
59 49
60#endif /* __ASSEMBLER__ */ 50#endif /* __ASSEMBLER__ */
61#endif /* __ASM_ARCH_IO_H */ 51#endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index f4c5ca6da9f4..18066074c995 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -96,10 +96,111 @@
96#define IRQ_EMUINT 63 96#define IRQ_EMUINT 63
97 97
98#define DAVINCI_N_AINTC_IRQ 64 98#define DAVINCI_N_AINTC_IRQ 64
99#define DAVINCI_N_GPIO 71 99#define DAVINCI_N_GPIO 104
100 100
101#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) 101#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO)
102 102
103#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 103#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
104 104
105/* DaVinci DM6467-specific Interrupts */
106#define IRQ_DM646X_VP_VERTINT0 0
107#define IRQ_DM646X_VP_VERTINT1 1
108#define IRQ_DM646X_VP_VERTINT2 2
109#define IRQ_DM646X_VP_VERTINT3 3
110#define IRQ_DM646X_VP_ERRINT 4
111#define IRQ_DM646X_RESERVED_1 5
112#define IRQ_DM646X_RESERVED_2 6
113#define IRQ_DM646X_WDINT 7
114#define IRQ_DM646X_CRGENINT0 8
115#define IRQ_DM646X_CRGENINT1 9
116#define IRQ_DM646X_TSIFINT0 10
117#define IRQ_DM646X_TSIFINT1 11
118#define IRQ_DM646X_VDCEINT 12
119#define IRQ_DM646X_USBINT 13
120#define IRQ_DM646X_USBDMAINT 14
121#define IRQ_DM646X_PCIINT 15
122#define IRQ_DM646X_TCERRINT2 20
123#define IRQ_DM646X_TCERRINT3 21
124#define IRQ_DM646X_IDE 22
125#define IRQ_DM646X_HPIINT 23
126#define IRQ_DM646X_EMACRXTHINT 24
127#define IRQ_DM646X_EMACRXINT 25
128#define IRQ_DM646X_EMACTXINT 26
129#define IRQ_DM646X_EMACMISCINT 27
130#define IRQ_DM646X_MCASP0TXINT 28
131#define IRQ_DM646X_MCASP0RXINT 29
132#define IRQ_DM646X_RESERVED_3 31
133#define IRQ_DM646X_MCASP1TXINT 32
134#define IRQ_DM646X_VLQINT 38
135#define IRQ_DM646X_UARTINT2 42
136#define IRQ_DM646X_SPINT0 43
137#define IRQ_DM646X_SPINT1 44
138#define IRQ_DM646X_DSP2ARMINT 45
139#define IRQ_DM646X_RESERVED_4 46
140#define IRQ_DM646X_PSCINT 47
141#define IRQ_DM646X_GPIO0 48
142#define IRQ_DM646X_GPIO1 49
143#define IRQ_DM646X_GPIO2 50
144#define IRQ_DM646X_GPIO3 51
145#define IRQ_DM646X_GPIO4 52
146#define IRQ_DM646X_GPIO5 53
147#define IRQ_DM646X_GPIO6 54
148#define IRQ_DM646X_GPIO7 55
149#define IRQ_DM646X_GPIOBNK0 56
150#define IRQ_DM646X_GPIOBNK1 57
151#define IRQ_DM646X_GPIOBNK2 58
152#define IRQ_DM646X_DDRINT 59
153#define IRQ_DM646X_AEMIFINT 60
154
155/* DaVinci DM355-specific Interrupts */
156#define IRQ_DM355_CCDC_VDINT0 0
157#define IRQ_DM355_CCDC_VDINT1 1
158#define IRQ_DM355_CCDC_VDINT2 2
159#define IRQ_DM355_IPIPE_HST 3
160#define IRQ_DM355_H3AINT 4
161#define IRQ_DM355_IPIPE_SDR 5
162#define IRQ_DM355_IPIPEIFINT 6
163#define IRQ_DM355_OSDINT 7
164#define IRQ_DM355_VENCINT 8
165#define IRQ_DM355_IMCOPINT 11
166#define IRQ_DM355_RTOINT 13
167#define IRQ_DM355_TINT4 13
168#define IRQ_DM355_TINT2_TINT12 13
169#define IRQ_DM355_UARTINT2 14
170#define IRQ_DM355_TINT5 14
171#define IRQ_DM355_TINT2_TINT34 14
172#define IRQ_DM355_TINT6 15
173#define IRQ_DM355_TINT3_TINT12 15
174#define IRQ_DM355_SPINT1_0 17
175#define IRQ_DM355_SPINT1_1 18
176#define IRQ_DM355_SPINT2_0 19
177#define IRQ_DM355_SPINT2_1 21
178#define IRQ_DM355_TINT7 22
179#define IRQ_DM355_TINT3_TINT34 22
180#define IRQ_DM355_SDIOINT0 23
181#define IRQ_DM355_MMCINT0 26
182#define IRQ_DM355_MSINT 26
183#define IRQ_DM355_MMCINT1 27
184#define IRQ_DM355_PWMINT3 28
185#define IRQ_DM355_SDIOINT1 31
186#define IRQ_DM355_SPINT0_0 42
187#define IRQ_DM355_SPINT0_1 43
188#define IRQ_DM355_GPIO0 44
189#define IRQ_DM355_GPIO1 45
190#define IRQ_DM355_GPIO2 46
191#define IRQ_DM355_GPIO3 47
192#define IRQ_DM355_GPIO4 48
193#define IRQ_DM355_GPIO5 49
194#define IRQ_DM355_GPIO6 50
195#define IRQ_DM355_GPIO7 51
196#define IRQ_DM355_GPIO8 52
197#define IRQ_DM355_GPIO9 53
198#define IRQ_DM355_GPIOBNK0 54
199#define IRQ_DM355_GPIOBNK1 55
200#define IRQ_DM355_GPIOBNK2 56
201#define IRQ_DM355_GPIOBNK3 57
202#define IRQ_DM355_GPIOBNK4 58
203#define IRQ_DM355_GPIOBNK5 59
204#define IRQ_DM355_GPIOBNK6 60
205
105#endif /* __ASM_ARCH_IRQS_H */ 206#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index c24b6782804d..bae22cb3e27b 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -1,55 +1,183 @@
1/* 1/*
2 * DaVinci pin multiplexing defines 2 * Table of the DAVINCI register configurations for the PINMUX combinations
3 * 3 *
4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> 4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
5 * 5 *
6 * Based on linux/include/asm-arm/arch-omap/mux.h:
7 * Copyright (C) 2003 - 2005 Nokia Corporation
8 *
9 * Written by Tony Lindgren
10 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under 11 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program 12 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express 13 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 14 * or implied.
15 *
16 * Copyright (C) 2008 Texas Instruments.
10 */ 17 */
11#ifndef __ASM_ARCH_MUX_H 18
12#define __ASM_ARCH_MUX_H 19#ifndef __INC_MACH_MUX_H
13 20#define __INC_MACH_MUX_H
14#define DAVINCI_MUX_AEAW0 0 21
15#define DAVINCI_MUX_AEAW1 1 22/* System module registers */
16#define DAVINCI_MUX_AEAW2 2 23#define PINMUX0 0x00
17#define DAVINCI_MUX_AEAW3 3 24#define PINMUX1 0x04
18#define DAVINCI_MUX_AEAW4 4 25/* dm355 only */
19#define DAVINCI_MUX_AECS4 10 26#define PINMUX2 0x08
20#define DAVINCI_MUX_AECS5 11 27#define PINMUX3 0x0c
21#define DAVINCI_MUX_VLYNQWD0 12 28#define PINMUX4 0x10
22#define DAVINCI_MUX_VLYNQWD1 13 29#define INTMUX 0x18
23#define DAVINCI_MUX_VLSCREN 14 30#define EVTMUX 0x1c
24#define DAVINCI_MUX_VLYNQEN 15 31
25#define DAVINCI_MUX_HDIREN 16 32struct mux_config {
26#define DAVINCI_MUX_ATAEN 17 33 const char *name;
27#define DAVINCI_MUX_RGB666 22 34 const char *mux_reg_name;
28#define DAVINCI_MUX_RGB888 23 35 const unsigned char mux_reg;
29#define DAVINCI_MUX_LOEEN 24 36 const unsigned char mask_offset;
30#define DAVINCI_MUX_LFLDEN 25 37 const unsigned char mask;
31#define DAVINCI_MUX_CWEN 26 38 const unsigned char mode;
32#define DAVINCI_MUX_CFLDEN 27 39 bool debug;
33#define DAVINCI_MUX_HPIEN 29 40};
34#define DAVINCI_MUX_1394EN 30 41
35#define DAVINCI_MUX_EMACEN 31 42enum davinci_dm644x_index {
36 43 /* ATA and HDDIR functions */
37#define DAVINCI_MUX_LEVEL2 32 44 DM644X_HDIREN,
38#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0) 45 DM644X_ATAEN,
39#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1) 46 DM644X_ATAEN_DISABLE,
40#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2) 47
41#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3) 48 /* HPI functions */
42#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4) 49 DM644X_HPIEN_DISABLE,
43#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5) 50
44#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6) 51 /* AEAW functions */
45#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7) 52 DM644X_AEAW,
46#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8) 53
47#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9) 54 /* Memory Stick */
48#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10) 55 DM644X_MSTK,
49#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16) 56
50#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17) 57 /* I2C */
51#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18) 58 DM644X_I2C,
52 59
53extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable); 60 /* ASP function */
54 61 DM644X_MCBSP,
55#endif /* __ASM_ARCH_MUX_H */ 62
63 /* UART1 */
64 DM644X_UART1,
65
66 /* UART2 */
67 DM644X_UART2,
68
69 /* PWM0 */
70 DM644X_PWM0,
71
72 /* PWM1 */
73 DM644X_PWM1,
74
75 /* PWM2 */
76 DM644X_PWM2,
77
78 /* VLYNQ function */
79 DM644X_VLYNQEN,
80 DM644X_VLSCREN,
81 DM644X_VLYNQWD,
82
83 /* EMAC and MDIO function */
84 DM644X_EMACEN,
85
86 /* GPIO3V[0:16] pins */
87 DM644X_GPIO3V,
88
89 /* GPIO pins */
90 DM644X_GPIO0,
91 DM644X_GPIO3,
92 DM644X_GPIO43_44,
93 DM644X_GPIO46_47,
94
95 /* VPBE */
96 DM644X_RGB666,
97
98 /* LCD */
99 DM644X_LOEEN,
100 DM644X_LFLDEN,
101};
102
103enum davinci_dm646x_index {
104 /* ATA function */
105 DM646X_ATAEN,
106
107 /* AUDIO Clock */
108 DM646X_AUDCK1,
109 DM646X_AUDCK0,
110
111 /* CRGEN Control */
112 DM646X_CRGMUX,
113
114 /* VPIF Control */
115 DM646X_STSOMUX_DISABLE,
116 DM646X_STSIMUX_DISABLE,
117 DM646X_PTSOMUX_DISABLE,
118 DM646X_PTSIMUX_DISABLE,
119
120 /* TSIF Control */
121 DM646X_STSOMUX,
122 DM646X_STSIMUX,
123 DM646X_PTSOMUX_PARALLEL,
124 DM646X_PTSIMUX_PARALLEL,
125 DM646X_PTSOMUX_SERIAL,
126 DM646X_PTSIMUX_SERIAL,
127};
128
129enum davinci_dm355_index {
130 /* MMC/SD 0 */
131 DM355_MMCSD0,
132
133 /* MMC/SD 1 */
134 DM355_SD1_CLK,
135 DM355_SD1_CMD,
136 DM355_SD1_DATA3,
137 DM355_SD1_DATA2,
138 DM355_SD1_DATA1,
139 DM355_SD1_DATA0,
140
141 /* I2C */
142 DM355_I2C_SDA,
143 DM355_I2C_SCL,
144
145 /* ASP0 function */
146 DM355_MCBSP0_BDX,
147 DM355_MCBSP0_X,
148 DM355_MCBSP0_BFSX,
149 DM355_MCBSP0_BDR,
150 DM355_MCBSP0_R,
151 DM355_MCBSP0_BFSR,
152
153 /* SPI0 */
154 DM355_SPI0_SDI,
155 DM355_SPI0_SDENA0,
156 DM355_SPI0_SDENA1,
157
158 /* IRQ muxing */
159 DM355_INT_EDMA_CC,
160 DM355_INT_EDMA_TC0_ERR,
161 DM355_INT_EDMA_TC1_ERR,
162
163 /* EDMA event muxing */
164 DM355_EVT8_ASP1_TX,
165 DM355_EVT9_ASP1_RX,
166 DM355_EVT26_MMC0_RX,
167};
168
169#ifdef CONFIG_DAVINCI_MUX
170/* setup pin muxing */
171extern void davinci_mux_init(void);
172extern int davinci_mux_register(const struct mux_config *pins,
173 unsigned long size);
174extern int davinci_cfg_reg(unsigned long reg_cfg);
175#else
176/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
177static inline void davinci_mux_init(void) {}
178static inline int davinci_mux_register(const struct mux_config *pins,
179 unsigned long size) { return 0; }
180static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
181#endif
182
183#endif /* __INC_MACH_MUX_H */
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 4977aa071e1e..55a90d419fac 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -38,8 +38,6 @@
38#define DAVINCI_LPSC_TPTC1 4 38#define DAVINCI_LPSC_TPTC1 4
39#define DAVINCI_LPSC_EMAC 5 39#define DAVINCI_LPSC_EMAC 5
40#define DAVINCI_LPSC_EMAC_WRAPPER 6 40#define DAVINCI_LPSC_EMAC_WRAPPER 6
41#define DAVINCI_LPSC_MDIO 7
42#define DAVINCI_LPSC_IEEE1394 8
43#define DAVINCI_LPSC_USB 9 41#define DAVINCI_LPSC_USB 9
44#define DAVINCI_LPSC_ATA 10 42#define DAVINCI_LPSC_ATA 10
45#define DAVINCI_LPSC_VLYNQ 11 43#define DAVINCI_LPSC_VLYNQ 11
@@ -47,7 +45,6 @@
47#define DAVINCI_LPSC_DDR_EMIF 13 45#define DAVINCI_LPSC_DDR_EMIF 13
48#define DAVINCI_LPSC_AEMIF 14 46#define DAVINCI_LPSC_AEMIF 14
49#define DAVINCI_LPSC_MMC_SD 15 47#define DAVINCI_LPSC_MMC_SD 15
50#define DAVINCI_LPSC_MEMSTICK 16
51#define DAVINCI_LPSC_McBSP 17 48#define DAVINCI_LPSC_McBSP 17
52#define DAVINCI_LPSC_I2C 18 49#define DAVINCI_LPSC_I2C 18
53#define DAVINCI_LPSC_UART0 19 50#define DAVINCI_LPSC_UART0 19
@@ -73,4 +70,54 @@
73#define DAVINCI_LPSC_GEM 39 70#define DAVINCI_LPSC_GEM 39
74#define DAVINCI_LPSC_IMCOP 40 71#define DAVINCI_LPSC_IMCOP 40
75 72
73#define DM355_LPSC_TIMER3 5
74#define DM355_LPSC_SPI1 6
75#define DM355_LPSC_MMC_SD1 7
76#define DM355_LPSC_McBSP1 8
77#define DM355_LPSC_PWM3 10
78#define DM355_LPSC_SPI2 11
79#define DM355_LPSC_RTO 12
80#define DM355_LPSC_VPSS_DAC 41
81
82/*
83 * LPSC Assignments
84 */
85#define DM646X_LPSC_ARM 0
86#define DM646X_LPSC_C64X_CPU 1
87#define DM646X_LPSC_HDVICP0 2
88#define DM646X_LPSC_HDVICP1 3
89#define DM646X_LPSC_TPCC 4
90#define DM646X_LPSC_TPTC0 5
91#define DM646X_LPSC_TPTC1 6
92#define DM646X_LPSC_TPTC2 7
93#define DM646X_LPSC_TPTC3 8
94#define DM646X_LPSC_PCI 13
95#define DM646X_LPSC_EMAC 14
96#define DM646X_LPSC_VDCE 15
97#define DM646X_LPSC_VPSSMSTR 16
98#define DM646X_LPSC_VPSSSLV 17
99#define DM646X_LPSC_TSIF0 18
100#define DM646X_LPSC_TSIF1 19
101#define DM646X_LPSC_DDR_EMIF 20
102#define DM646X_LPSC_AEMIF 21
103#define DM646X_LPSC_McASP0 22
104#define DM646X_LPSC_McASP1 23
105#define DM646X_LPSC_CRGEN0 24
106#define DM646X_LPSC_CRGEN1 25
107#define DM646X_LPSC_UART0 26
108#define DM646X_LPSC_UART1 27
109#define DM646X_LPSC_UART2 28
110#define DM646X_LPSC_PWM0 29
111#define DM646X_LPSC_PWM1 30
112#define DM646X_LPSC_I2C 31
113#define DM646X_LPSC_SPI 32
114#define DM646X_LPSC_GPIO 33
115#define DM646X_LPSC_TIMER0 34
116#define DM646X_LPSC_TIMER1 35
117#define DM646X_LPSC_ARM_INTC 45
118
119extern int davinci_psc_is_clk_active(unsigned int id);
120extern void davinci_psc_config(unsigned int domain, unsigned int id,
121 char enable);
122
76#endif /* __ASM_ARCH_PSC_H */ 123#endif /* __ASM_ARCH_PSC_H */
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index fb8cb229bfd2..632847d74a1c 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -13,8 +13,23 @@
13 13
14#include <mach/io.h> 14#include <mach/io.h>
15 15
16#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) 16#define DAVINCI_MAX_NR_UARTS 3
17#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) 17#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
18#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) 18#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
19#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
20
21#define DM355_UART2_BASE (IO_PHYS + 0x206000)
22
23/* DaVinci UART register offsets */
24#define UART_DAVINCI_PWREMU 0x0c
25#define UART_DM646X_SCR 0x10
26#define UART_DM646X_SCR_TX_WATERMARK 0x08
27
28struct davinci_uart_config {
29 /* Bit field of UARTs present; bit 0 --> UART1 */
30 unsigned int enabled_uarts;
31};
32
33extern void davinci_serial_init(struct davinci_uart_config *);
19 34
20#endif /* __ASM_ARCH_SERIAL_H */ 35#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
index 299515f70b8b..a548abb513e2 100644
--- a/arch/arm/mach-davinci/io.c
+++ b/arch/arm/mach-davinci/io.c
@@ -51,7 +51,26 @@ void __init davinci_map_common_io(void)
51 davinci_check_revision(); 51 davinci_check_revision();
52} 52}
53 53
54void __init davinci_init_common_hw(void) 54#define BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
55#define XLATE(p, pst, vst) ((void __iomem *)((p) - (pst) + (vst)))
56
57/*
58 * Intercept ioremap() requests for addresses in our fixed mapping regions.
59 */
60void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
61{
62 if (BETWEEN(p, IO_PHYS, IO_SIZE))
63 return XLATE(p, IO_PHYS, IO_VIRT);
64
65 return __arm_ioremap(p, size, type);
66}
67EXPORT_SYMBOL(davinci_ioremap);
68
69void davinci_iounmap(volatile void __iomem *addr)
55{ 70{
56 davinci_clk_init(); 71 unsigned long virt = (unsigned long)addr;
72
73 if (virt >= VMALLOC_START && virt < VMALLOC_END)
74 __iounmap(addr);
57} 75}
76EXPORT_SYMBOL(davinci_iounmap);
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index 38021af8359a..5a324c90e291 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -25,6 +25,7 @@
25#include <linux/io.h> 25#include <linux/io.h>
26 26
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/cputype.h>
28#include <asm/mach/irq.h> 29#include <asm/mach/irq.h>
29 30
30#define IRQ_BIT(irq) ((irq) & 0x1f) 31#define IRQ_BIT(irq) ((irq) & 0x1f)
@@ -40,14 +41,18 @@
40#define IRQ_INTPRI0_REG_OFFSET 0x0030 41#define IRQ_INTPRI0_REG_OFFSET 0x0030
41#define IRQ_INTPRI7_REG_OFFSET 0x004C 42#define IRQ_INTPRI7_REG_OFFSET 0x004C
42 43
44const u8 *davinci_def_priorities;
45
46#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
47
43static inline unsigned int davinci_irq_readl(int offset) 48static inline unsigned int davinci_irq_readl(int offset)
44{ 49{
45 return davinci_readl(DAVINCI_ARM_INTC_BASE + offset); 50 return __raw_readl(INTC_BASE + offset);
46} 51}
47 52
48static inline void davinci_irq_writel(unsigned long value, int offset) 53static inline void davinci_irq_writel(unsigned long value, int offset)
49{ 54{
50 davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset); 55 __raw_writel(value, INTC_BASE + offset);
51} 56}
52 57
53/* Disable interrupt */ 58/* Disable interrupt */
@@ -108,9 +113,8 @@ static struct irq_chip davinci_irq_chip_0 = {
108 .unmask = davinci_unmask_irq, 113 .unmask = davinci_unmask_irq,
109}; 114};
110 115
111
112/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ 116/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
113static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = { 117static const u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
114 [IRQ_VDINT0] = 2, 118 [IRQ_VDINT0] = 2,
115 [IRQ_VDINT1] = 6, 119 [IRQ_VDINT1] = 6,
116 [IRQ_VDINT2] = 6, 120 [IRQ_VDINT2] = 6,
@@ -177,11 +181,149 @@ static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
177 [IRQ_EMUINT] = 7, 181 [IRQ_EMUINT] = 7,
178}; 182};
179 183
184static const u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
185 [IRQ_DM646X_VP_VERTINT0] = 7,
186 [IRQ_DM646X_VP_VERTINT1] = 7,
187 [IRQ_DM646X_VP_VERTINT2] = 7,
188 [IRQ_DM646X_VP_VERTINT3] = 7,
189 [IRQ_DM646X_VP_ERRINT] = 7,
190 [IRQ_DM646X_RESERVED_1] = 7,
191 [IRQ_DM646X_RESERVED_2] = 7,
192 [IRQ_DM646X_WDINT] = 7,
193 [IRQ_DM646X_CRGENINT0] = 7,
194 [IRQ_DM646X_CRGENINT1] = 7,
195 [IRQ_DM646X_TSIFINT0] = 7,
196 [IRQ_DM646X_TSIFINT1] = 7,
197 [IRQ_DM646X_VDCEINT] = 7,
198 [IRQ_DM646X_USBINT] = 7,
199 [IRQ_DM646X_USBDMAINT] = 7,
200 [IRQ_DM646X_PCIINT] = 7,
201 [IRQ_CCINT0] = 7, /* dma */
202 [IRQ_CCERRINT] = 7, /* dma */
203 [IRQ_TCERRINT0] = 7, /* dma */
204 [IRQ_TCERRINT] = 7, /* dma */
205 [IRQ_DM646X_TCERRINT2] = 7,
206 [IRQ_DM646X_TCERRINT3] = 7,
207 [IRQ_DM646X_IDE] = 7,
208 [IRQ_DM646X_HPIINT] = 7,
209 [IRQ_DM646X_EMACRXTHINT] = 7,
210 [IRQ_DM646X_EMACRXINT] = 7,
211 [IRQ_DM646X_EMACTXINT] = 7,
212 [IRQ_DM646X_EMACMISCINT] = 7,
213 [IRQ_DM646X_MCASP0TXINT] = 7,
214 [IRQ_DM646X_MCASP0RXINT] = 7,
215 [IRQ_AEMIFINT] = 7,
216 [IRQ_DM646X_RESERVED_3] = 7,
217 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
218 [IRQ_TINT0_TINT34] = 7, /* clocksource */
219 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
220 [IRQ_TINT1_TINT34] = 7, /* system tick */
221 [IRQ_PWMINT0] = 7,
222 [IRQ_PWMINT1] = 7,
223 [IRQ_DM646X_VLQINT] = 7,
224 [IRQ_I2C] = 7,
225 [IRQ_UARTINT0] = 7,
226 [IRQ_UARTINT1] = 7,
227 [IRQ_DM646X_UARTINT2] = 7,
228 [IRQ_DM646X_SPINT0] = 7,
229 [IRQ_DM646X_SPINT1] = 7,
230 [IRQ_DM646X_DSP2ARMINT] = 7,
231 [IRQ_DM646X_RESERVED_4] = 7,
232 [IRQ_DM646X_PSCINT] = 7,
233 [IRQ_DM646X_GPIO0] = 7,
234 [IRQ_DM646X_GPIO1] = 7,
235 [IRQ_DM646X_GPIO2] = 7,
236 [IRQ_DM646X_GPIO3] = 7,
237 [IRQ_DM646X_GPIO4] = 7,
238 [IRQ_DM646X_GPIO5] = 7,
239 [IRQ_DM646X_GPIO6] = 7,
240 [IRQ_DM646X_GPIO7] = 7,
241 [IRQ_DM646X_GPIOBNK0] = 7,
242 [IRQ_DM646X_GPIOBNK1] = 7,
243 [IRQ_DM646X_GPIOBNK2] = 7,
244 [IRQ_DM646X_DDRINT] = 7,
245 [IRQ_DM646X_AEMIFINT] = 7,
246 [IRQ_COMMTX] = 7,
247 [IRQ_COMMRX] = 7,
248 [IRQ_EMUINT] = 7,
249};
250
251static const u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
252 [IRQ_DM355_CCDC_VDINT0] = 2,
253 [IRQ_DM355_CCDC_VDINT1] = 6,
254 [IRQ_DM355_CCDC_VDINT2] = 6,
255 [IRQ_DM355_IPIPE_HST] = 6,
256 [IRQ_DM355_H3AINT] = 6,
257 [IRQ_DM355_IPIPE_SDR] = 6,
258 [IRQ_DM355_IPIPEIFINT] = 6,
259 [IRQ_DM355_OSDINT] = 7,
260 [IRQ_DM355_VENCINT] = 6,
261 [IRQ_ASQINT] = 6,
262 [IRQ_IMXINT] = 6,
263 [IRQ_USBINT] = 4,
264 [IRQ_DM355_RTOINT] = 4,
265 [IRQ_DM355_UARTINT2] = 7,
266 [IRQ_DM355_TINT6] = 7,
267 [IRQ_CCINT0] = 5, /* dma */
268 [IRQ_CCERRINT] = 5, /* dma */
269 [IRQ_TCERRINT0] = 5, /* dma */
270 [IRQ_TCERRINT] = 5, /* dma */
271 [IRQ_DM355_SPINT2_1] = 7,
272 [IRQ_DM355_TINT7] = 4,
273 [IRQ_DM355_SDIOINT0] = 7,
274 [IRQ_MBXINT] = 7,
275 [IRQ_MBRINT] = 7,
276 [IRQ_MMCINT] = 7,
277 [IRQ_DM355_MMCINT1] = 7,
278 [IRQ_DM355_PWMINT3] = 7,
279 [IRQ_DDRINT] = 7,
280 [IRQ_AEMIFINT] = 7,
281 [IRQ_DM355_SDIOINT1] = 4,
282 [IRQ_TINT0_TINT12] = 2, /* clockevent */
283 [IRQ_TINT0_TINT34] = 2, /* clocksource */
284 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
285 [IRQ_TINT1_TINT34] = 7, /* system tick */
286 [IRQ_PWMINT0] = 7,
287 [IRQ_PWMINT1] = 7,
288 [IRQ_PWMINT2] = 7,
289 [IRQ_I2C] = 3,
290 [IRQ_UARTINT0] = 3,
291 [IRQ_UARTINT1] = 3,
292 [IRQ_DM355_SPINT0_0] = 3,
293 [IRQ_DM355_SPINT0_1] = 3,
294 [IRQ_DM355_GPIO0] = 3,
295 [IRQ_DM355_GPIO1] = 7,
296 [IRQ_DM355_GPIO2] = 4,
297 [IRQ_DM355_GPIO3] = 4,
298 [IRQ_DM355_GPIO4] = 7,
299 [IRQ_DM355_GPIO5] = 7,
300 [IRQ_DM355_GPIO6] = 7,
301 [IRQ_DM355_GPIO7] = 7,
302 [IRQ_DM355_GPIO8] = 7,
303 [IRQ_DM355_GPIO9] = 7,
304 [IRQ_DM355_GPIOBNK0] = 7,
305 [IRQ_DM355_GPIOBNK1] = 7,
306 [IRQ_DM355_GPIOBNK2] = 7,
307 [IRQ_DM355_GPIOBNK3] = 7,
308 [IRQ_DM355_GPIOBNK4] = 7,
309 [IRQ_DM355_GPIOBNK5] = 7,
310 [IRQ_DM355_GPIOBNK6] = 7,
311 [IRQ_COMMTX] = 7,
312 [IRQ_COMMRX] = 7,
313 [IRQ_EMUINT] = 7,
314};
315
180/* ARM Interrupt Controller Initialization */ 316/* ARM Interrupt Controller Initialization */
181void __init davinci_irq_init(void) 317void __init davinci_irq_init(void)
182{ 318{
183 unsigned i; 319 unsigned i;
184 const u8 *priority = default_priorities; 320
321 if (cpu_is_davinci_dm644x())
322 davinci_def_priorities = dm644x_default_priorities;
323 else if (cpu_is_davinci_dm646x())
324 davinci_def_priorities = dm646x_default_priorities;
325 else if (cpu_is_davinci_dm355())
326 davinci_def_priorities = dm355_default_priorities;
185 327
186 /* Clear all interrupt requests */ 328 /* Clear all interrupt requests */
187 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); 329 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
@@ -209,8 +351,8 @@ void __init davinci_irq_init(void)
209 unsigned j; 351 unsigned j;
210 u32 pri; 352 u32 pri;
211 353
212 for (j = 0, pri = 0; j < 32; j += 4, priority++) 354 for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
213 pri |= (*priority & 0x07) << j; 355 pri |= (*davinci_def_priorities & 0x07) << j;
214 davinci_irq_writel(pri, i); 356 davinci_irq_writel(pri, i);
215 } 357 }
216 358
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index 8ff9d8aca60b..bbba0b247a44 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -1,41 +1,103 @@
1/* 1/*
2 * DaVinci pin multiplexing configurations 2 * Utility to set the DAVINCI MUX register from a table in mux.h
3 * 3 *
4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> 4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
5 * 5 *
6 * Based on linux/arch/arm/plat-omap/mux.c:
7 * Copyright (C) 2003 - 2005 Nokia Corporation
8 *
9 * Written by Tony Lindgren
10 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under 11 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program 12 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express 13 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 14 * or implied.
15 *
16 * Copyright (C) 2008 Texas Instruments.
10 */ 17 */
11#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/module.h>
12#include <linux/spinlock.h> 20#include <linux/spinlock.h>
13 21
14#include <mach/hardware.h> 22#include <mach/hardware.h>
15
16#include <mach/mux.h> 23#include <mach/mux.h>
17 24
18/* System control register offsets */ 25static const struct mux_config *mux_table;
19#define PINMUX0 0x00 26static unsigned long pin_table_sz;
20#define PINMUX1 0x04 27
28int __init davinci_mux_register(const struct mux_config *pins,
29 unsigned long size)
30{
31 mux_table = pins;
32 pin_table_sz = size;
21 33
22static DEFINE_SPINLOCK(mux_lock); 34 return 0;
35}
23 36
24void davinci_mux_peripheral(unsigned int mux, unsigned int enable) 37/*
38 * Sets the DAVINCI MUX register based on the table
39 */
40int __init_or_module davinci_cfg_reg(const unsigned long index)
25{ 41{
26 u32 pinmux, muxreg = PINMUX0; 42 static DEFINE_SPINLOCK(mux_spin_lock);
43 void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
44 unsigned long flags;
45 const struct mux_config *cfg;
46 unsigned int reg_orig = 0, reg = 0;
47 unsigned int mask, warn = 0;
48
49 if (!mux_table)
50 BUG();
51
52 if (index >= pin_table_sz) {
53 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
54 index, pin_table_sz);
55 dump_stack();
56 return -ENODEV;
57 }
58
59 cfg = &mux_table[index];
60
61 if (cfg->name == NULL) {
62 printk(KERN_ERR "No entry for the specified index\n");
63 return -ENODEV;
64 }
65
66 /* Update the mux register in question */
67 if (cfg->mask) {
68 unsigned tmp1, tmp2;
69
70 spin_lock_irqsave(&mux_spin_lock, flags);
71 reg_orig = __raw_readl(base + cfg->mux_reg);
72
73 mask = (cfg->mask << cfg->mask_offset);
74 tmp1 = reg_orig & mask;
75 reg = reg_orig & ~mask;
76
77 tmp2 = (cfg->mode << cfg->mask_offset);
78 reg |= tmp2;
79
80 if (tmp1 != tmp2)
81 warn = 1;
82
83 __raw_writel(reg, base + cfg->mux_reg);
84 spin_unlock_irqrestore(&mux_spin_lock, flags);
85 }
86
87 if (warn) {
88#ifdef CONFIG_DAVINCI_MUX_WARNINGS
89 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
90#endif
91 }
27 92
28 if (mux >= DAVINCI_MUX_LEVEL2) { 93#ifdef CONFIG_DAVINCI_MUX_DEBUG
29 muxreg = PINMUX1; 94 if (cfg->debug || warn) {
30 mux -= DAVINCI_MUX_LEVEL2; 95 printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name);
96 printk(KERN_WARNING " %s (0x%08x) = 0x%08x -> 0x%08x\n",
97 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
31 } 98 }
99#endif
32 100
33 spin_lock(&mux_lock); 101 return 0;
34 pinmux = davinci_readl(DAVINCI_SYSTEM_MODULE_BASE + muxreg);
35 if (enable)
36 pinmux |= (1 << mux);
37 else
38 pinmux &= ~(1 << mux);
39 davinci_writel(pinmux, DAVINCI_SYSTEM_MODULE_BASE + muxreg);
40 spin_unlock(&mux_lock);
41} 102}
103EXPORT_SYMBOL(davinci_cfg_reg);
diff --git a/arch/arm/mach-davinci/mux.h b/arch/arm/mach-davinci/mux.h
new file mode 100644
index 000000000000..adc869413371
--- /dev/null
+++ b/arch/arm/mach-davinci/mux.h
@@ -0,0 +1,51 @@
1/*
2 * Pin-multiplex helper macros for TI DaVinci family devices
3 *
4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Copyright (C) 2008 Texas Instruments.
12 */
13#ifndef _MACH_DAVINCI_MUX_H_
14#define _MACH_DAVINCI_MUX_H_
15
16#include <mach/mux.h>
17
18#define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\
19[soc##_##desc] = { \
20 .name = #desc, \
21 .debug = dbg, \
22 .mux_reg_name = "PINMUX"#muxreg, \
23 .mux_reg = PINMUX##muxreg, \
24 .mask_offset = mode_offset, \
25 .mask = mode_mask, \
26 .mode = mux_mode, \
27 },
28
29#define INT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \
30[soc##_##desc] = { \
31 .name = #desc, \
32 .debug = dbg, \
33 .mux_reg_name = "INTMUX", \
34 .mux_reg = INTMUX, \
35 .mask_offset = mode_offset, \
36 .mask = mode_mask, \
37 .mode = mux_mode, \
38 },
39
40#define EVT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \
41[soc##_##desc] = { \
42 .name = #desc, \
43 .debug = dbg, \
44 .mux_reg_name = "EVTMUX", \
45 .mux_reg = EVTMUX, \
46 .mask_offset = mode_offset, \
47 .mask = mode_mask, \
48 .mode = mux_mode, \
49 },
50
51#endif /* _MACH_DAVINCI_MUX_H */
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 58754f066d5b..84171abf5f7b 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -23,10 +23,13 @@
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/io.h> 24#include <linux/io.h>
25 25
26#include <mach/cputype.h>
26#include <mach/hardware.h> 27#include <mach/hardware.h>
27#include <mach/psc.h> 28#include <mach/psc.h>
28#include <mach/mux.h> 29#include <mach/mux.h>
29 30
31#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
32
30/* PSC register offsets */ 33/* PSC register offsets */
31#define EPCPR 0x070 34#define EPCPR 0x070
32#define PTCMD 0x120 35#define PTCMD 0x120
@@ -36,102 +39,61 @@
36#define MDSTAT 0x800 39#define MDSTAT 0x800
37#define MDCTL 0xA00 40#define MDCTL 0xA00
38 41
39/* System control register offsets */ 42#define MDSTAT_STATE_MASK 0x1f
40#define VDD3P3V_PWDN 0x48
41 43
42static void davinci_psc_mux(unsigned int id) 44/* Return nonzero iff the domain's clock is active */
45int __init davinci_psc_is_clk_active(unsigned int id)
43{ 46{
44 switch (id) { 47 void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
45 case DAVINCI_LPSC_ATA: 48 u32 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
46 davinci_mux_peripheral(DAVINCI_MUX_HDIREN, 1); 49
47 davinci_mux_peripheral(DAVINCI_MUX_ATAEN, 1); 50 /* if clocked, state can be "Enable" or "SyncReset" */
48 break; 51 return mdstat & BIT(12);
49 case DAVINCI_LPSC_MMC_SD:
50 /* VDD power manupulations are done in U-Boot for CPMAC
51 * so applies to MMC as well
52 */
53 /*Set up the pull regiter for MMC */
54 davinci_writel(0, DAVINCI_SYSTEM_MODULE_BASE + VDD3P3V_PWDN);
55 davinci_mux_peripheral(DAVINCI_MUX_MSTK, 0);
56 break;
57 case DAVINCI_LPSC_I2C:
58 davinci_mux_peripheral(DAVINCI_MUX_I2C, 1);
59 break;
60 case DAVINCI_LPSC_McBSP:
61 davinci_mux_peripheral(DAVINCI_MUX_ASP, 1);
62 break;
63 default:
64 break;
65 }
66} 52}
67 53
68/* Enable or disable a PSC domain */ 54/* Enable or disable a PSC domain */
69void davinci_psc_config(unsigned int domain, unsigned int id, char enable) 55void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
70{ 56{
71 u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask; 57 u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
58 void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
59 u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */
72 60
73 mdctl = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id); 61 mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
74 if (enable) 62 mdctl &= ~MDSTAT_STATE_MASK;
75 mdctl |= 0x00000003; /* Enable Module */ 63 mdctl |= next_state;
76 else 64 __raw_writel(mdctl, psc_base + MDCTL + 4 * id);
77 mdctl &= 0xFFFFFFF2; /* Disable Module */
78 davinci_writel(mdctl, DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
79 65
80 pdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDSTAT); 66 pdstat = __raw_readl(psc_base + PDSTAT);
81 if ((pdstat & 0x00000001) == 0) { 67 if ((pdstat & 0x00000001) == 0) {
82 pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); 68 pdctl1 = __raw_readl(psc_base + PDCTL1);
83 pdctl1 |= 0x1; 69 pdctl1 |= 0x1;
84 davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); 70 __raw_writel(pdctl1, psc_base + PDCTL1);
85 71
86 ptcmd = 1 << domain; 72 ptcmd = 1 << domain;
87 davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD); 73 __raw_writel(ptcmd, psc_base + PTCMD);
88 74
89 do { 75 do {
90 epcpr = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + 76 epcpr = __raw_readl(psc_base + EPCPR);
91 EPCPR);
92 } while ((((epcpr >> domain) & 1) == 0)); 77 } while ((((epcpr >> domain) & 1) == 0));
93 78
94 pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); 79 pdctl1 = __raw_readl(psc_base + PDCTL1);
95 pdctl1 |= 0x100; 80 pdctl1 |= 0x100;
96 davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); 81 __raw_writel(pdctl1, psc_base + PDCTL1);
97 82
98 do { 83 do {
99 ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + 84 ptstat = __raw_readl(psc_base +
100 PTSTAT); 85 PTSTAT);
101 } while (!(((ptstat >> domain) & 1) == 0)); 86 } while (!(((ptstat >> domain) & 1) == 0));
102 } else { 87 } else {
103 ptcmd = 1 << domain; 88 ptcmd = 1 << domain;
104 davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD); 89 __raw_writel(ptcmd, psc_base + PTCMD);
105 90
106 do { 91 do {
107 ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + 92 ptstat = __raw_readl(psc_base + PTSTAT);
108 PTSTAT);
109 } while (!(((ptstat >> domain) & 1) == 0)); 93 } while (!(((ptstat >> domain) & 1) == 0));
110 } 94 }
111 95
112 if (enable)
113 mdstat_mask = 0x3;
114 else
115 mdstat_mask = 0x2;
116
117 do { 96 do {
118 mdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + 97 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
119 MDSTAT + 4 * id); 98 } while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
120 } while (!((mdstat & 0x0000001F) == mdstat_mask));
121
122 if (enable)
123 davinci_psc_mux(id);
124}
125
126void __init davinci_psc_init(void)
127{
128 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSMSTR, 1);
129 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSSLV, 1);
130 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPCC, 1);
131 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC0, 1);
132 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC1, 1);
133 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_GPIO, 1);
134
135 /* Turn on WatchDog timer LPSC. Needed for RESET to work */
136 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TIMER2, 1);
137} 99}
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 3010f9971255..695075796522 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -32,32 +32,47 @@
32#include <mach/hardware.h> 32#include <mach/hardware.h>
33#include <mach/serial.h> 33#include <mach/serial.h>
34#include <mach/irqs.h> 34#include <mach/irqs.h>
35#include <mach/cputype.h>
36#include "clock.h"
35 37
36#define UART_DAVINCI_PWREMU 0x0c 38static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
37 39 int offset)
38static inline unsigned int davinci_serial_in(struct plat_serial8250_port *up,
39 int offset)
40{ 40{
41 offset <<= up->regshift; 41 offset <<= up->regshift;
42 return (unsigned int)__raw_readb(up->membase + offset); 42 return (unsigned int)__raw_readl(IO_ADDRESS(up->mapbase) + offset);
43} 43}
44 44
45static inline void davinci_serial_outp(struct plat_serial8250_port *p, 45static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
46 int offset, int value) 46 int value)
47{ 47{
48 offset <<= p->regshift; 48 offset <<= p->regshift;
49 __raw_writeb(value, p->membase + offset); 49 __raw_writel(value, IO_ADDRESS(p->mapbase) + offset);
50} 50}
51 51
52static struct plat_serial8250_port serial_platform_data[] = { 52static struct plat_serial8250_port serial_platform_data[] = {
53 { 53 {
54 .membase = (char *)IO_ADDRESS(DAVINCI_UART0_BASE), 54 .mapbase = DAVINCI_UART0_BASE,
55 .mapbase = (unsigned long)DAVINCI_UART0_BASE,
56 .irq = IRQ_UARTINT0, 55 .irq = IRQ_UARTINT0,
57 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 56 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
57 UPF_IOREMAP,
58 .iotype = UPIO_MEM,
59 .regshift = 2,
60 },
61 {
62 .mapbase = DAVINCI_UART1_BASE,
63 .irq = IRQ_UARTINT1,
64 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
65 UPF_IOREMAP,
66 .iotype = UPIO_MEM,
67 .regshift = 2,
68 },
69 {
70 .mapbase = DAVINCI_UART2_BASE,
71 .irq = IRQ_UARTINT2,
72 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
73 UPF_IOREMAP,
58 .iotype = UPIO_MEM, 74 .iotype = UPIO_MEM,
59 .regshift = 2, 75 .regshift = 2,
60 .uartclk = 27000000,
61 }, 76 },
62 { 77 {
63 .flags = 0 78 .flags = 0
@@ -74,22 +89,68 @@ static struct platform_device serial_device = {
74 89
75static void __init davinci_serial_reset(struct plat_serial8250_port *p) 90static void __init davinci_serial_reset(struct plat_serial8250_port *p)
76{ 91{
77 /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */
78 unsigned int pwremu = 0; 92 unsigned int pwremu = 0;
79 93
80 davinci_serial_outp(p, UART_IER, 0); /* disable all interrupts */ 94 serial_write_reg(p, UART_IER, 0); /* disable all interrupts */
81 95
82 davinci_serial_outp(p, UART_DAVINCI_PWREMU, pwremu); 96 /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */
97 serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
83 mdelay(10); 98 mdelay(10);
84 99
85 pwremu |= (0x3 << 13); 100 pwremu |= (0x3 << 13);
86 pwremu |= 0x1; 101 pwremu |= 0x1;
87 davinci_serial_outp(p, UART_DAVINCI_PWREMU, pwremu); 102 serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
103
104 if (cpu_is_davinci_dm646x())
105 serial_write_reg(p, UART_DM646X_SCR,
106 UART_DM646X_SCR_TX_WATERMARK);
107}
108
109void __init davinci_serial_init(struct davinci_uart_config *info)
110{
111 int i;
112 char name[16];
113 struct clk *uart_clk;
114 struct device *dev = &serial_device.dev;
115
116 /*
117 * Make sure the serial ports are muxed on at this point.
118 * You have to mux them off in device drivers later on
119 * if not needed.
120 */
121 for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++) {
122 struct plat_serial8250_port *p = serial_platform_data + i;
123
124 if (!(info->enabled_uarts & (1 << i))) {
125 p->flags = 0;
126 continue;
127 }
128
129 if (cpu_is_davinci_dm646x())
130 p->iotype = UPIO_MEM32;
131
132 if (cpu_is_davinci_dm355()) {
133 if (i == 2) {
134 p->mapbase = (unsigned long)DM355_UART2_BASE;
135 p->irq = IRQ_DM355_UARTINT2;
136 }
137 }
138
139 sprintf(name, "uart%d", i);
140 uart_clk = clk_get(dev, name);
141 if (IS_ERR(uart_clk))
142 printk(KERN_ERR "%s:%d: failed to get UART%d clock\n",
143 __func__, __LINE__, i);
144 else {
145 clk_enable(uart_clk);
146 p->uartclk = clk_get_rate(uart_clk);
147 davinci_serial_reset(p);
148 }
149 }
88} 150}
89 151
90static int __init davinci_init(void) 152static int __init davinci_init(void)
91{ 153{
92 davinci_serial_reset(&serial_platform_data[0]);
93 return platform_device_register(&serial_device); 154 return platform_device_register(&serial_device);
94} 155}
95 156
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 6c227d4ba998..494e01bff5c3 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -16,6 +16,9 @@
16#include <linux/clockchips.h> 16#include <linux/clockchips.h>
17#include <linux/spinlock.h> 17#include <linux/spinlock.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/device.h>
19 22
20#include <mach/hardware.h> 23#include <mach/hardware.h>
21#include <asm/system.h> 24#include <asm/system.h>
@@ -24,8 +27,11 @@
24#include <asm/mach/time.h> 27#include <asm/mach/time.h>
25#include <asm/errno.h> 28#include <asm/errno.h>
26#include <mach/io.h> 29#include <mach/io.h>
30#include <mach/cputype.h>
31#include "clock.h"
27 32
28static struct clock_event_device clockevent_davinci; 33static struct clock_event_device clockevent_davinci;
34static unsigned int davinci_clock_tick_rate;
29 35
30#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400) 36#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
31#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800) 37#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
@@ -99,9 +105,9 @@ struct timer_s {
99 unsigned int id; 105 unsigned int id;
100 unsigned long period; 106 unsigned long period;
101 unsigned long opts; 107 unsigned long opts;
102 unsigned long reg_base; 108 void __iomem *base;
103 unsigned long tim_reg; 109 unsigned long tim_off;
104 unsigned long prd_reg; 110 unsigned long prd_off;
105 unsigned long enamode_shift; 111 unsigned long enamode_shift;
106 struct irqaction irqaction; 112 struct irqaction irqaction;
107}; 113};
@@ -114,15 +120,15 @@ static struct timer_s timers[];
114 120
115static int timer32_config(struct timer_s *t) 121static int timer32_config(struct timer_s *t)
116{ 122{
117 u32 tcr = davinci_readl(t->reg_base + TCR); 123 u32 tcr = __raw_readl(t->base + TCR);
118 124
119 /* disable timer */ 125 /* disable timer */
120 tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift); 126 tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
121 davinci_writel(tcr, t->reg_base + TCR); 127 __raw_writel(tcr, t->base + TCR);
122 128
123 /* reset counter to zero, set new period */ 129 /* reset counter to zero, set new period */
124 davinci_writel(0, t->tim_reg); 130 __raw_writel(0, t->base + t->tim_off);
125 davinci_writel(t->period, t->prd_reg); 131 __raw_writel(t->period, t->base + t->prd_off);
126 132
127 /* Set enable mode */ 133 /* Set enable mode */
128 if (t->opts & TIMER_OPTS_ONESHOT) { 134 if (t->opts & TIMER_OPTS_ONESHOT) {
@@ -131,13 +137,13 @@ static int timer32_config(struct timer_s *t)
131 tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift; 137 tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
132 } 138 }
133 139
134 davinci_writel(tcr, t->reg_base + TCR); 140 __raw_writel(tcr, t->base + TCR);
135 return 0; 141 return 0;
136} 142}
137 143
138static inline u32 timer32_read(struct timer_s *t) 144static inline u32 timer32_read(struct timer_s *t)
139{ 145{
140 return davinci_readl(t->tim_reg); 146 return __raw_readl(t->base + t->tim_off);
141} 147}
142 148
143static irqreturn_t timer_interrupt(int irq, void *dev_id) 149static irqreturn_t timer_interrupt(int irq, void *dev_id)
@@ -176,51 +182,54 @@ static struct timer_s timers[] = {
176 182
177static void __init timer_init(void) 183static void __init timer_init(void)
178{ 184{
179 u32 bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE}; 185 u32 phys_bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE};
180 int i; 186 int i;
181 187
182 /* Global init of each 64-bit timer as a whole */ 188 /* Global init of each 64-bit timer as a whole */
183 for(i=0; i<2; i++) { 189 for(i=0; i<2; i++) {
184 u32 tgcr, base = bases[i]; 190 u32 tgcr;
191 void __iomem *base = IO_ADDRESS(phys_bases[i]);
185 192
186 /* Disabled, Internal clock source */ 193 /* Disabled, Internal clock source */
187 davinci_writel(0, base + TCR); 194 __raw_writel(0, base + TCR);
188 195
189 /* reset both timers, no pre-scaler for timer34 */ 196 /* reset both timers, no pre-scaler for timer34 */
190 tgcr = 0; 197 tgcr = 0;
191 davinci_writel(tgcr, base + TGCR); 198 __raw_writel(tgcr, base + TGCR);
192 199
193 /* Set both timers to unchained 32-bit */ 200 /* Set both timers to unchained 32-bit */
194 tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT; 201 tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
195 davinci_writel(tgcr, base + TGCR); 202 __raw_writel(tgcr, base + TGCR);
196 203
197 /* Unreset timers */ 204 /* Unreset timers */
198 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | 205 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
199 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); 206 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
200 davinci_writel(tgcr, base + TGCR); 207 __raw_writel(tgcr, base + TGCR);
201 208
202 /* Init both counters to zero */ 209 /* Init both counters to zero */
203 davinci_writel(0, base + TIM12); 210 __raw_writel(0, base + TIM12);
204 davinci_writel(0, base + TIM34); 211 __raw_writel(0, base + TIM34);
205 } 212 }
206 213
207 /* Init of each timer as a 32-bit timer */ 214 /* Init of each timer as a 32-bit timer */
208 for (i=0; i< ARRAY_SIZE(timers); i++) { 215 for (i=0; i< ARRAY_SIZE(timers); i++) {
209 struct timer_s *t = &timers[i]; 216 struct timer_s *t = &timers[i];
217 u32 phys_base;
210 218
211 if (t->name) { 219 if (t->name) {
212 t->id = i; 220 t->id = i;
213 t->reg_base = (IS_TIMER1(t->id) ? 221 phys_base = (IS_TIMER1(t->id) ?
214 DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE); 222 DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE);
223 t->base = IO_ADDRESS(phys_base);
215 224
216 if (IS_TIMER_BOT(t->id)) { 225 if (IS_TIMER_BOT(t->id)) {
217 t->enamode_shift = 6; 226 t->enamode_shift = 6;
218 t->tim_reg = t->reg_base + TIM12; 227 t->tim_off = TIM12;
219 t->prd_reg = t->reg_base + PRD12; 228 t->prd_off = PRD12;
220 } else { 229 } else {
221 t->enamode_shift = 22; 230 t->enamode_shift = 22;
222 t->tim_reg = t->reg_base + TIM34; 231 t->tim_off = TIM34;
223 t->prd_reg = t->reg_base + PRD34; 232 t->prd_off = PRD34;
224 } 233 }
225 234
226 /* Register interrupt */ 235 /* Register interrupt */
@@ -274,7 +283,7 @@ static void davinci_set_mode(enum clock_event_mode mode,
274 283
275 switch (mode) { 284 switch (mode) {
276 case CLOCK_EVT_MODE_PERIODIC: 285 case CLOCK_EVT_MODE_PERIODIC:
277 t->period = CLOCK_TICK_RATE / (HZ); 286 t->period = davinci_clock_tick_rate / (HZ);
278 t->opts = TIMER_OPTS_PERIODIC; 287 t->opts = TIMER_OPTS_PERIODIC;
279 timer32_config(t); 288 timer32_config(t);
280 break; 289 break;
@@ -301,21 +310,29 @@ static struct clock_event_device clockevent_davinci = {
301 310
302static void __init davinci_timer_init(void) 311static void __init davinci_timer_init(void)
303{ 312{
313 struct clk *timer_clk;
314
304 static char err[] __initdata = KERN_ERR 315 static char err[] __initdata = KERN_ERR
305 "%s: can't register clocksource!\n"; 316 "%s: can't register clocksource!\n";
306 317
307 /* init timer hw */ 318 /* init timer hw */
308 timer_init(); 319 timer_init();
309 320
321 timer_clk = clk_get(NULL, "timer0");
322 BUG_ON(IS_ERR(timer_clk));
323 clk_enable(timer_clk);
324
325 davinci_clock_tick_rate = clk_get_rate(timer_clk);
326
310 /* setup clocksource */ 327 /* setup clocksource */
311 clocksource_davinci.mult = 328 clocksource_davinci.mult =
312 clocksource_khz2mult(CLOCK_TICK_RATE/1000, 329 clocksource_khz2mult(davinci_clock_tick_rate/1000,
313 clocksource_davinci.shift); 330 clocksource_davinci.shift);
314 if (clocksource_register(&clocksource_davinci)) 331 if (clocksource_register(&clocksource_davinci))
315 printk(err, clocksource_davinci.name); 332 printk(err, clocksource_davinci.name);
316 333
317 /* setup clockevent */ 334 /* setup clockevent */
318 clockevent_davinci.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, 335 clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC,
319 clockevent_davinci.shift); 336 clockevent_davinci.shift);
320 clockevent_davinci.max_delta_ns = 337 clockevent_davinci.max_delta_ns =
321 clockevent_delta2ns(0xfffffffe, &clockevent_davinci); 338 clockevent_delta2ns(0xfffffffe, &clockevent_davinci);
@@ -333,42 +350,52 @@ struct sys_timer davinci_timer = {
333 350
334/* reset board using watchdog timer */ 351/* reset board using watchdog timer */
335void davinci_watchdog_reset(void) { 352void davinci_watchdog_reset(void) {
336 u32 tgcr, wdtcr, base = DAVINCI_WDOG_BASE; 353 u32 tgcr, wdtcr;
354 void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE);
355 struct device dev;
356 struct clk *wd_clk;
357 char *name = "watchdog";
358
359 dev_set_name(&dev, name);
360 wd_clk = clk_get(&dev, NULL);
361 if (WARN_ON(IS_ERR(wd_clk)))
362 return;
363 clk_enable(wd_clk);
337 364
338 /* disable, internal clock source */ 365 /* disable, internal clock source */
339 davinci_writel(0, base + TCR); 366 __raw_writel(0, base + TCR);
340 367
341 /* reset timer, set mode to 64-bit watchdog, and unreset */ 368 /* reset timer, set mode to 64-bit watchdog, and unreset */
342 tgcr = 0; 369 tgcr = 0;
343 davinci_writel(tgcr, base + TCR); 370 __raw_writel(tgcr, base + TCR);
344 tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT; 371 tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
345 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | 372 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
346 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); 373 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
347 davinci_writel(tgcr, base + TCR); 374 __raw_writel(tgcr, base + TCR);
348 375
349 /* clear counter and period regs */ 376 /* clear counter and period regs */
350 davinci_writel(0, base + TIM12); 377 __raw_writel(0, base + TIM12);
351 davinci_writel(0, base + TIM34); 378 __raw_writel(0, base + TIM34);
352 davinci_writel(0, base + PRD12); 379 __raw_writel(0, base + PRD12);
353 davinci_writel(0, base + PRD34); 380 __raw_writel(0, base + PRD34);
354 381
355 /* enable */ 382 /* enable */
356 wdtcr = davinci_readl(base + WDTCR); 383 wdtcr = __raw_readl(base + WDTCR);
357 wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT; 384 wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT;
358 davinci_writel(wdtcr, base + WDTCR); 385 __raw_writel(wdtcr, base + WDTCR);
359 386
360 /* put watchdog in pre-active state */ 387 /* put watchdog in pre-active state */
361 wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | 388 wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
362 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); 389 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
363 davinci_writel(wdtcr, base + WDTCR); 390 __raw_writel(wdtcr, base + WDTCR);
364 391
365 /* put watchdog in active state */ 392 /* put watchdog in active state */
366 wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) | 393 wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
367 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); 394 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
368 davinci_writel(wdtcr, base + WDTCR); 395 __raw_writel(wdtcr, base + WDTCR);
369 396
370 /* write an invalid value to the WDKEY field to trigger 397 /* write an invalid value to the WDKEY field to trigger
371 * a watchdog reset */ 398 * a watchdog reset */
372 wdtcr = 0x00004000; 399 wdtcr = 0x00004000;
373 davinci_writel(wdtcr, base + WDTCR); 400 __raw_writel(wdtcr, base + WDTCR);
374} 401}
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index 2429b79f6da2..abedb6337182 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -14,6 +14,8 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/irqs.h> 15#include <mach/irqs.h>
16 16
17#define DAVINCI_USB_OTG_BASE 0x01C64000
18
17#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) 19#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
18static struct musb_hdrc_eps_bits musb_eps[] = { 20static struct musb_hdrc_eps_bits musb_eps[] = {
19 { "ep1_tx", 8, }, 21 { "ep1_tx", 8, },
diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c
index 44d4a966bed9..46098f546824 100644
--- a/arch/arm/mach-omap1/board-h2-mmc.c
+++ b/arch/arm/mach-omap1/board-h2-mmc.c
@@ -26,19 +26,13 @@
26static int mmc_set_power(struct device *dev, int slot, int power_on, 26static int mmc_set_power(struct device *dev, int slot, int power_on,
27 int vdd) 27 int vdd)
28{ 28{
29 if (power_on) 29 gpio_set_value(H2_TPS_GPIO_MMC_PWR_EN, power_on);
30 gpio_direction_output(H2_TPS_GPIO_MMC_PWR_EN, 1);
31 else
32 gpio_direction_output(H2_TPS_GPIO_MMC_PWR_EN, 0);
33
34 return 0; 30 return 0;
35} 31}
36 32
37static int mmc_late_init(struct device *dev) 33static int mmc_late_init(struct device *dev)
38{ 34{
39 int ret; 35 int ret = gpio_request(H2_TPS_GPIO_MMC_PWR_EN, "MMC power");
40
41 ret = gpio_request(H2_TPS_GPIO_MMC_PWR_EN, "MMC power");
42 if (ret < 0) 36 if (ret < 0)
43 return ret; 37 return ret;
44 38
@@ -47,7 +41,7 @@ static int mmc_late_init(struct device *dev)
47 return ret; 41 return ret;
48} 42}
49 43
50static void mmc_shutdown(struct device *dev) 44static void mmc_cleanup(struct device *dev)
51{ 45{
52 gpio_free(H2_TPS_GPIO_MMC_PWR_EN); 46 gpio_free(H2_TPS_GPIO_MMC_PWR_EN);
53} 47}
@@ -60,7 +54,7 @@ static void mmc_shutdown(struct device *dev)
60static struct omap_mmc_platform_data mmc1_data = { 54static struct omap_mmc_platform_data mmc1_data = {
61 .nr_slots = 1, 55 .nr_slots = 1,
62 .init = mmc_late_init, 56 .init = mmc_late_init,
63 .shutdown = mmc_shutdown, 57 .cleanup = mmc_cleanup,
64 .dma_mask = 0xffffffff, 58 .dma_mask = 0xffffffff,
65 .slots[0] = { 59 .slots[0] = {
66 .set_power = mmc_set_power, 60 .set_power = mmc_set_power,
diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c
index 0d8a3c195e2e..5e8877ce35e0 100644
--- a/arch/arm/mach-omap1/board-h3-mmc.c
+++ b/arch/arm/mach-omap1/board-h3-mmc.c
@@ -26,11 +26,7 @@
26static int mmc_set_power(struct device *dev, int slot, int power_on, 26static int mmc_set_power(struct device *dev, int slot, int power_on,
27 int vdd) 27 int vdd)
28{ 28{
29 if (power_on) 29 gpio_set_value(H3_TPS_GPIO_MMC_PWR_EN, power_on);
30 gpio_direction_output(H3_TPS_GPIO_MMC_PWR_EN, 1);
31 else
32 gpio_direction_output(H3_TPS_GPIO_MMC_PWR_EN, 0);
33
34 return 0; 30 return 0;
35} 31}
36 32
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 4695965114c4..f597968733b4 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -39,12 +39,10 @@
39#include <asm/mach/flash.h> 39#include <asm/mach/flash.h>
40#include <asm/mach/map.h> 40#include <asm/mach/map.h>
41 41
42#include <mach/gpioexpander.h>
43#include <mach/irqs.h> 42#include <mach/irqs.h>
44#include <mach/mux.h> 43#include <mach/mux.h>
45#include <mach/tc.h> 44#include <mach/tc.h>
46#include <mach/nand.h> 45#include <mach/nand.h>
47#include <mach/irda.h>
48#include <mach/usb.h> 46#include <mach/usb.h>
49#include <mach/keypad.h> 47#include <mach/keypad.h>
50#include <mach/dma.h> 48#include <mach/dma.h>
@@ -276,104 +274,6 @@ static struct platform_device h3_kp_device = {
276 .resource = h3_kp_resources, 274 .resource = h3_kp_resources,
277}; 275};
278 276
279
280/* Select between the IrDA and aGPS module
281 */
282static int h3_select_irda(struct device *dev, int state)
283{
284 unsigned char expa;
285 int err = 0;
286
287 if ((err = read_gpio_expa(&expa, 0x26))) {
288 printk(KERN_ERR "Error reading from I/O EXPANDER \n");
289 return err;
290 }
291
292 /* 'P6' enable/disable IRDA_TX and IRDA_RX */
293 if (state & IR_SEL) { /* IrDA */
294 if ((err = write_gpio_expa(expa | 0x40, 0x26))) {
295 printk(KERN_ERR "Error writing to I/O EXPANDER \n");
296 return err;
297 }
298 } else {
299 if ((err = write_gpio_expa(expa & ~0x40, 0x26))) {
300 printk(KERN_ERR "Error writing to I/O EXPANDER \n");
301 return err;
302 }
303 }
304 return err;
305}
306
307static void set_trans_mode(struct work_struct *work)
308{
309 struct omap_irda_config *irda_config =
310 container_of(work, struct omap_irda_config, gpio_expa.work);
311 int mode = irda_config->mode;
312 unsigned char expa;
313 int err = 0;
314
315 if ((err = read_gpio_expa(&expa, 0x27)) != 0) {
316 printk(KERN_ERR "Error reading from I/O expander\n");
317 }
318
319 expa &= ~0x03;
320
321 if (mode & IR_SIRMODE) {
322 expa |= 0x01;
323 } else { /* MIR/FIR */
324 expa |= 0x03;
325 }
326
327 if ((err = write_gpio_expa(expa, 0x27)) != 0) {
328 printk(KERN_ERR "Error writing to I/O expander\n");
329 }
330}
331
332static int h3_transceiver_mode(struct device *dev, int mode)
333{
334 struct omap_irda_config *irda_config = dev->platform_data;
335
336 irda_config->mode = mode;
337 cancel_delayed_work(&irda_config->gpio_expa);
338 PREPARE_DELAYED_WORK(&irda_config->gpio_expa, set_trans_mode);
339 schedule_delayed_work(&irda_config->gpio_expa, 0);
340
341 return 0;
342}
343
344static struct omap_irda_config h3_irda_data = {
345 .transceiver_cap = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE,
346 .transceiver_mode = h3_transceiver_mode,
347 .select_irda = h3_select_irda,
348 .rx_channel = OMAP_DMA_UART3_RX,
349 .tx_channel = OMAP_DMA_UART3_TX,
350 .dest_start = UART3_THR,
351 .src_start = UART3_RHR,
352 .tx_trigger = 0,
353 .rx_trigger = 0,
354};
355
356static struct resource h3_irda_resources[] = {
357 [0] = {
358 .start = INT_UART3,
359 .end = INT_UART3,
360 .flags = IORESOURCE_IRQ,
361 },
362};
363
364static u64 irda_dmamask = 0xffffffff;
365
366static struct platform_device h3_irda_device = {
367 .name = "omapirda",
368 .id = 0,
369 .dev = {
370 .platform_data = &h3_irda_data,
371 .dma_mask = &irda_dmamask,
372 },
373 .num_resources = ARRAY_SIZE(h3_irda_resources),
374 .resource = h3_irda_resources,
375};
376
377static struct platform_device h3_lcd_device = { 277static struct platform_device h3_lcd_device = {
378 .name = "lcd_h3", 278 .name = "lcd_h3",
379 .id = -1, 279 .id = -1,
@@ -395,7 +295,6 @@ static struct platform_device *devices[] __initdata = {
395 &nand_device, 295 &nand_device,
396 &smc91x_device, 296 &smc91x_device,
397 &intlat_device, 297 &intlat_device,
398 &h3_irda_device,
399 &h3_kp_device, 298 &h3_kp_device,
400 &h3_lcd_device, 299 &h3_lcd_device,
401}; 300};
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 7bc7a3cb9c51..d1ed1365319e 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -181,11 +181,7 @@ static struct omap_usb_config nokia770_usb_config __initdata = {
181static int nokia770_mmc_set_power(struct device *dev, int slot, int power_on, 181static int nokia770_mmc_set_power(struct device *dev, int slot, int power_on,
182 int vdd) 182 int vdd)
183{ 183{
184 if (power_on) 184 gpio_set_value(NOKIA770_GPIO_MMC_POWER, power_on);
185 gpio_set_value(NOKIA770_GPIO_MMC_POWER, 1);
186 else
187 gpio_set_value(NOKIA770_GPIO_MMC_POWER, 0);
188
189 return 0; 185 return 0;
190} 186}
191 187
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index d040c3f1027f..a2d7814896be 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -40,8 +40,8 @@ static void omap1_mcbsp_request(unsigned int id)
40 */ 40 */
41 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) { 41 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
42 if (dsp_use++ == 0) { 42 if (dsp_use++ == 0) {
43 api_clk = clk_get(NULL, "api_clk"); 43 api_clk = clk_get(NULL, "api_ck");
44 dsp_clk = clk_get(NULL, "dsp_clk"); 44 dsp_clk = clk_get(NULL, "dsp_ck");
45 if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) { 45 if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) {
46 clk_enable(api_clk); 46 clk_enable(api_clk);
47 clk_enable(dsp_clk); 47 clk_enable(dsp_clk);
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index a0267a9ab466..e7d017cdc438 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -33,10 +33,8 @@
33 33
34#include <mach/control.h> 34#include <mach/control.h>
35#include <mach/gpio.h> 35#include <mach/gpio.h>
36#include <mach/gpioexpander.h>
37#include <mach/mux.h> 36#include <mach/mux.h>
38#include <mach/usb.h> 37#include <mach/usb.h>
39#include <mach/irda.h>
40#include <mach/board.h> 38#include <mach/board.h>
41#include <mach/common.h> 39#include <mach/common.h>
42#include <mach/keypad.h> 40#include <mach/keypad.h>
@@ -138,98 +136,6 @@ static struct platform_device h4_flash_device = {
138 .resource = &h4_flash_resource, 136 .resource = &h4_flash_resource,
139}; 137};
140 138
141/* Select between the IrDA and aGPS module
142 */
143static int h4_select_irda(struct device *dev, int state)
144{
145 unsigned char expa;
146 int err = 0;
147
148 if ((err = read_gpio_expa(&expa, 0x21))) {
149 printk(KERN_ERR "Error reading from I/O expander\n");
150 return err;
151 }
152
153 /* 'P6' enable/disable IRDA_TX and IRDA_RX */
154 if (state & IR_SEL) { /* IrDa */
155 if ((err = write_gpio_expa(expa | 0x01, 0x21))) {
156 printk(KERN_ERR "Error writing to I/O expander\n");
157 return err;
158 }
159 } else {
160 if ((err = write_gpio_expa(expa & ~0x01, 0x21))) {
161 printk(KERN_ERR "Error writing to I/O expander\n");
162 return err;
163 }
164 }
165 return err;
166}
167
168static void set_trans_mode(struct work_struct *work)
169{
170 struct omap_irda_config *irda_config =
171 container_of(work, struct omap_irda_config, gpio_expa.work);
172 int mode = irda_config->mode;
173 unsigned char expa;
174 int err = 0;
175
176 if ((err = read_gpio_expa(&expa, 0x20)) != 0) {
177 printk(KERN_ERR "Error reading from I/O expander\n");
178 }
179
180 expa &= ~0x01;
181
182 if (!(mode & IR_SIRMODE)) { /* MIR/FIR */
183 expa |= 0x01;
184 }
185
186 if ((err = write_gpio_expa(expa, 0x20)) != 0) {
187 printk(KERN_ERR "Error writing to I/O expander\n");
188 }
189}
190
191static int h4_transceiver_mode(struct device *dev, int mode)
192{
193 struct omap_irda_config *irda_config = dev->platform_data;
194
195 irda_config->mode = mode;
196 cancel_delayed_work(&irda_config->gpio_expa);
197 PREPARE_DELAYED_WORK(&irda_config->gpio_expa, set_trans_mode);
198 schedule_delayed_work(&irda_config->gpio_expa, 0);
199
200 return 0;
201}
202
203static struct omap_irda_config h4_irda_data = {
204 .transceiver_cap = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE,
205 .transceiver_mode = h4_transceiver_mode,
206 .select_irda = h4_select_irda,
207 .rx_channel = OMAP24XX_DMA_UART3_RX,
208 .tx_channel = OMAP24XX_DMA_UART3_TX,
209 .dest_start = OMAP_UART3_BASE,
210 .src_start = OMAP_UART3_BASE,
211 .tx_trigger = OMAP24XX_DMA_UART3_TX,
212 .rx_trigger = OMAP24XX_DMA_UART3_RX,
213};
214
215static struct resource h4_irda_resources[] = {
216 [0] = {
217 .start = INT_24XX_UART3_IRQ,
218 .end = INT_24XX_UART3_IRQ,
219 .flags = IORESOURCE_IRQ,
220 },
221};
222
223static struct platform_device h4_irda_device = {
224 .name = "omapirda",
225 .id = -1,
226 .dev = {
227 .platform_data = &h4_irda_data,
228 },
229 .num_resources = 1,
230 .resource = h4_irda_resources,
231};
232
233static struct omap_kp_platform_data h4_kp_data = { 139static struct omap_kp_platform_data h4_kp_data = {
234 .rows = 6, 140 .rows = 6,
235 .cols = 7, 141 .cols = 7,
@@ -255,7 +161,6 @@ static struct platform_device h4_lcd_device = {
255 161
256static struct platform_device *h4_devices[] __initdata = { 162static struct platform_device *h4_devices[] __initdata = {
257 &h4_flash_device, 163 &h4_flash_device,
258 &h4_irda_device,
259 &h4_kp_device, 164 &h4_kp_device,
260 &h4_lcd_device, 165 &h4_lcd_device,
261}; 166};
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 744740ae1b9c..3a7a29d1f9a7 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -42,6 +42,7 @@
42#include <mach/nand.h> 42#include <mach/nand.h>
43#include <mach/mux.h> 43#include <mach/mux.h>
44#include <mach/usb.h> 44#include <mach/usb.h>
45#include <mach/timer-gp.h>
45 46
46#include "mmc-twl4030.h" 47#include "mmc-twl4030.h"
47 48
@@ -186,6 +187,9 @@ static void __init omap3_beagle_init_irq(void)
186{ 187{
187 omap2_init_common_hw(NULL); 188 omap2_init_common_hw(NULL);
188 omap_init_irq(); 189 omap_init_irq();
190#ifdef CONFIG_OMAP_32K_TIMER
191 omap2_gp_clockevent_set_gptimer(12);
192#endif
189 omap_gpio_init(); 193 omap_gpio_init();
190} 194}
191 195
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 3a0daac6c839..374ff63c3eb2 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -15,7 +15,6 @@
15#include <linux/err.h> 15#include <linux/err.h>
16#include <linux/clk.h> 16#include <linux/clk.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/delay.h>
19#include <linux/gpio.h> 18#include <linux/gpio.h>
20 19
21#include <mach/hardware.h> 20#include <mach/hardware.h>
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 1e839c5a28c5..efc59c49341b 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -60,12 +60,13 @@ struct omap_clk {
60 }, \ 60 }, \
61 } 61 }
62 62
63#define CK_243X (1 << 0) 63#define CK_243X RATE_IN_243X
64#define CK_242X (1 << 1) 64#define CK_242X RATE_IN_242X
65 65
66static struct omap_clk omap24xx_clks[] = { 66static struct omap_clk omap24xx_clks[] = {
67 /* external root sources */ 67 /* external root sources */
68 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X), 68 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X),
69 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),
69 CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X), 70 CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X),
70 CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X), 71 CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X),
71 CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X), 72 CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X),
@@ -711,7 +712,7 @@ int __init omap2_clk_init(void)
711{ 712{
712 struct prcm_config *prcm; 713 struct prcm_config *prcm;
713 struct omap_clk *c; 714 struct omap_clk *c;
714 u32 clkrate, cpu_mask; 715 u32 clkrate;
715 716
716 if (cpu_is_omap242x()) 717 if (cpu_is_omap242x())
717 cpu_mask = RATE_IN_242X; 718 cpu_mask = RATE_IN_242X;
@@ -720,21 +721,15 @@ int __init omap2_clk_init(void)
720 721
721 clk_init(&omap2_clk_functions); 722 clk_init(&omap2_clk_functions);
722 723
724 for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
725 clk_init_one(c->lk.clk);
726
723 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); 727 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
724 propagate_rate(&osc_ck); 728 propagate_rate(&osc_ck);
725 sys_ck.rate = omap2_sys_clk_recalc(&sys_ck); 729 sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
726 propagate_rate(&sys_ck); 730 propagate_rate(&sys_ck);
727 731
728 for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) 732 for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
729 clk_init_one(c->lk.clk);
730
731 cpu_mask = 0;
732 if (cpu_is_omap2420())
733 cpu_mask |= CK_242X;
734 if (cpu_is_omap2430())
735 cpu_mask |= CK_243X;
736
737 for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
738 if (c->cpu & cpu_mask) { 733 if (c->cpu & cpu_mask) {
739 clkdev_add(&c->lk); 734 clkdev_add(&c->lk);
740 clk_register(c->lk.clk); 735 clk_register(c->lk.clk);
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 33c3e5b14323..88c5acb40fcf 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -625,6 +625,14 @@ static struct clk func_32k_ck = {
625 .clkdm_name = "wkup_clkdm", 625 .clkdm_name = "wkup_clkdm",
626}; 626};
627 627
628static struct clk secure_32k_ck = {
629 .name = "secure_32k_ck",
630 .ops = &clkops_null,
631 .rate = 32768,
632 .flags = RATE_FIXED,
633 .clkdm_name = "wkup_clkdm",
634};
635
628/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ 636/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
629static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ 637static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
630 .name = "osc_ck", 638 .name = "osc_ck",
@@ -1790,7 +1798,7 @@ static struct clk gpt12_ick = {
1790static struct clk gpt12_fck = { 1798static struct clk gpt12_fck = {
1791 .name = "gpt12_fck", 1799 .name = "gpt12_fck",
1792 .ops = &clkops_omap2_dflt_wait, 1800 .ops = &clkops_omap2_dflt_wait,
1793 .parent = &func_32k_ck, 1801 .parent = &secure_32k_ck,
1794 .clkdm_name = "core_l4_clkdm", 1802 .clkdm_name = "core_l4_clkdm",
1795 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1803 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1796 .enable_bit = OMAP24XX_EN_GPT12_SHIFT, 1804 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 70ec10deb654..6763b8f73028 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -2052,7 +2052,7 @@ static struct clk dss_ick = {
2052 2052
2053static struct clk cam_mclk = { 2053static struct clk cam_mclk = {
2054 .name = "cam_mclk", 2054 .name = "cam_mclk",
2055 .ops = &clkops_omap2_dflt_wait, 2055 .ops = &clkops_omap2_dflt,
2056 .parent = &dpll4_m5x2_ck, 2056 .parent = &dpll4_m5x2_ck,
2057 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), 2057 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2058 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2058 .enable_bit = OMAP3430_EN_CAM_SHIFT,
@@ -2063,7 +2063,7 @@ static struct clk cam_mclk = {
2063static struct clk cam_ick = { 2063static struct clk cam_ick = {
2064 /* Handles both L3 and L4 clocks */ 2064 /* Handles both L3 and L4 clocks */
2065 .name = "cam_ick", 2065 .name = "cam_ick",
2066 .ops = &clkops_omap2_dflt_wait, 2066 .ops = &clkops_omap2_dflt,
2067 .parent = &l4_ick, 2067 .parent = &l4_ick,
2068 .init = &omap2_init_clk_clkdm, 2068 .init = &omap2_init_clk_clkdm,
2069 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), 2069 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
@@ -2074,7 +2074,7 @@ static struct clk cam_ick = {
2074 2074
2075static struct clk csi2_96m_fck = { 2075static struct clk csi2_96m_fck = {
2076 .name = "csi2_96m_fck", 2076 .name = "csi2_96m_fck",
2077 .ops = &clkops_omap2_dflt_wait, 2077 .ops = &clkops_omap2_dflt,
2078 .parent = &core_96m_fck, 2078 .parent = &core_96m_fck,
2079 .init = &omap2_init_clk_clkdm, 2079 .init = &omap2_init_clk_clkdm,
2080 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), 2080 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
@@ -2901,7 +2901,6 @@ static struct clk sr_l4_ick = {
2901 2901
2902/* SECURE_32K_FCK clocks */ 2902/* SECURE_32K_FCK clocks */
2903 2903
2904/* XXX This clock no longer exists in 3430 TRM rev F */
2905static struct clk gpt12_fck = { 2904static struct clk gpt12_fck = {
2906 .name = "gpt12_fck", 2905 .name = "gpt12_fck",
2907 .ops = &clkops_null, 2906 .ops = &clkops_null,
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index d6b4b2f8722f..496983ade97e 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -25,7 +25,6 @@
25#include <mach/board.h> 25#include <mach/board.h>
26#include <mach/mux.h> 26#include <mach/mux.h>
27#include <mach/gpio.h> 27#include <mach/gpio.h>
28#include <mach/eac.h>
29#include <mach/mmc.h> 28#include <mach/mmc.h>
30 29
31#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) 30#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
@@ -366,38 +365,6 @@ static void omap_init_mcspi(void)
366static inline void omap_init_mcspi(void) {} 365static inline void omap_init_mcspi(void) {}
367#endif 366#endif
368 367
369#ifdef CONFIG_SND_OMAP24XX_EAC
370
371#define OMAP2_EAC_BASE 0x48090000
372
373static struct resource omap2_eac_resources[] = {
374 {
375 .start = OMAP2_EAC_BASE,
376 .end = OMAP2_EAC_BASE + 0x109,
377 .flags = IORESOURCE_MEM,
378 },
379};
380
381static struct platform_device omap2_eac_device = {
382 .name = "omap24xx-eac",
383 .id = -1,
384 .num_resources = ARRAY_SIZE(omap2_eac_resources),
385 .resource = omap2_eac_resources,
386 .dev = {
387 .platform_data = NULL,
388 },
389};
390
391void omap_init_eac(struct eac_platform_data *pdata)
392{
393 omap2_eac_device.dev.platform_data = pdata;
394 platform_device_register(&omap2_eac_device);
395}
396
397#else
398void omap_init_eac(struct eac_platform_data *pdata) {}
399#endif
400
401#ifdef CONFIG_OMAP_SHA1_MD5 368#ifdef CONFIG_OMAP_SHA1_MD5
402static struct resource sha1_md5_resources[] = { 369static struct resource sha1_md5_resources[] = {
403 { 370 {
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 9ba20d985dda..998c5c45587e 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -73,9 +73,9 @@ static int omap_check_spurious(unsigned int irq)
73 u32 sir, spurious; 73 u32 sir, spurious;
74 74
75 sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR); 75 sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR);
76 spurious = sir >> 6; 76 spurious = sir >> 7;
77 77
78 if (spurious > 1) { 78 if (spurious) {
79 printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush " 79 printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush "
80 "posted write for irq %i\n", 80 "posted write for irq %i\n",
81 irq, sir, previous_irq); 81 irq, sir, previous_irq);
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 1cb2c0909c2b..f36aba12090e 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -3,6 +3,8 @@
3 * 3 *
4 * OMAP2 GP timer support. 4 * OMAP2 GP timer support.
5 * 5 *
6 * Copyright (C) 2009 Nokia Corporation
7 *
6 * Update to use new clocksource/clockevent layers 8 * Update to use new clocksource/clockevent layers
7 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
8 * Copyright (C) 2007 MontaVista Software, Inc. 10 * Copyright (C) 2007 MontaVista Software, Inc.
@@ -36,8 +38,13 @@
36#include <asm/mach/time.h> 38#include <asm/mach/time.h>
37#include <mach/dmtimer.h> 39#include <mach/dmtimer.h>
38 40
41/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
42#define MAX_GPTIMER_ID 12
43
39static struct omap_dm_timer *gptimer; 44static struct omap_dm_timer *gptimer;
40static struct clock_event_device clockevent_gpt; 45static struct clock_event_device clockevent_gpt;
46static u8 __initdata gptimer_id = 1;
47static u8 __initdata inited;
41 48
42static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) 49static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
43{ 50{
@@ -95,20 +102,53 @@ static struct clock_event_device clockevent_gpt = {
95 .set_mode = omap2_gp_timer_set_mode, 102 .set_mode = omap2_gp_timer_set_mode,
96}; 103};
97 104
105/**
106 * omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents
107 * @id: GPTIMER to use (1..MAX_GPTIMER_ID)
108 *
109 * Define the GPTIMER that the system should use for the tick timer.
110 * Meant to be called from board-*.c files in the event that GPTIMER1, the
111 * default, is unsuitable. Returns -EINVAL on error or 0 on success.
112 */
113int __init omap2_gp_clockevent_set_gptimer(u8 id)
114{
115 if (id < 1 || id > MAX_GPTIMER_ID)
116 return -EINVAL;
117
118 BUG_ON(inited);
119
120 gptimer_id = id;
121
122 return 0;
123}
124
98static void __init omap2_gp_clockevent_init(void) 125static void __init omap2_gp_clockevent_init(void)
99{ 126{
100 u32 tick_rate; 127 u32 tick_rate;
128 int src;
129
130 inited = 1;
101 131
102 gptimer = omap_dm_timer_request_specific(1); 132 gptimer = omap_dm_timer_request_specific(gptimer_id);
103 BUG_ON(gptimer == NULL); 133 BUG_ON(gptimer == NULL);
104 134
105#if defined(CONFIG_OMAP_32K_TIMER) 135#if defined(CONFIG_OMAP_32K_TIMER)
106 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ); 136 src = OMAP_TIMER_SRC_32_KHZ;
107#else 137#else
108 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK); 138 src = OMAP_TIMER_SRC_SYS_CLK;
139 WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the "
140 "secure 32KiHz clock source\n");
109#endif 141#endif
142
143 if (gptimer_id != 12)
144 WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)),
145 "timer-gp: omap_dm_timer_set_source() failed\n");
146
110 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); 147 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
111 148
149 pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
150 gptimer_id, tick_rate);
151
112 omap2_gp_timer_irq.dev_id = (void *)gptimer; 152 omap2_gp_timer_irq.dev_id = (void *)gptimer;
113 setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); 153 setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
114 omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); 154 omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
@@ -125,6 +165,8 @@ static void __init omap2_gp_clockevent_init(void)
125 clockevents_register_device(&clockevent_gpt); 165 clockevents_register_device(&clockevent_gpt);
126} 166}
127 167
168/* Clocksource code */
169
128#ifdef CONFIG_OMAP_32K_TIMER 170#ifdef CONFIG_OMAP_32K_TIMER
129/* 171/*
130 * When 32k-timer is enabled, don't use GPTimer for clocksource 172 * When 32k-timer is enabled, don't use GPTimer for clocksource
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 15e509013def..8df55f40f4c0 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -187,7 +187,7 @@ int tusb6010_platform_retime(unsigned is_refclk)
187 unsigned sysclk_ps; 187 unsigned sysclk_ps;
188 int status; 188 int status;
189 189
190 if (!refclk_psec) 190 if (!refclk_psec || sysclk_ps == 0)
191 return -ENODEV; 191 return -ENODEV;
192 192
193 sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60; 193 sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60;
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 3e66d9099eab..17d3fbd368a3 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -289,12 +289,12 @@ config MACH_LITTLETON
289config MACH_TAVOREVB 289config MACH_TAVOREVB
290 bool "PXA930 Evaluation Board (aka TavorEVB)" 290 bool "PXA930 Evaluation Board (aka TavorEVB)"
291 select PXA3xx 291 select PXA3xx
292 select PXA930 292 select CPU_PXA930
293 293
294config MACH_SAAR 294config MACH_SAAR
295 bool "PXA930 Handheld Platform (aka SAAR)" 295 bool "PXA930 Handheld Platform (aka SAAR)"
296 select PXA3xx 296 select PXA3xx
297 select PXA930 297 select CPU_PXA930
298 298
299config MACH_ARMCORE 299config MACH_ARMCORE
300 bool "CompuLab CM-X255/CM-X270 modules" 300 bool "CompuLab CM-X255/CM-X270 modules"
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index cdf21dd135b4..930e364ccde9 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -427,12 +427,22 @@ static struct pxa2xx_spi_master corgi_spi_info = {
427 .num_chipselect = 3, 427 .num_chipselect = 3,
428}; 428};
429 429
430static void corgi_wait_for_hsync(void)
431{
432 while (gpio_get_value(CORGI_GPIO_HSYNC))
433 cpu_relax();
434
435 while (!gpio_get_value(CORGI_GPIO_HSYNC))
436 cpu_relax();
437}
438
430static struct ads7846_platform_data corgi_ads7846_info = { 439static struct ads7846_platform_data corgi_ads7846_info = {
431 .model = 7846, 440 .model = 7846,
432 .vref_delay_usecs = 100, 441 .vref_delay_usecs = 100,
433 .x_plate_ohms = 419, 442 .x_plate_ohms = 419,
434 .y_plate_ohms = 486, 443 .y_plate_ohms = 486,
435 .gpio_pendown = CORGI_GPIO_TP_INT, 444 .gpio_pendown = CORGI_GPIO_TP_INT,
445 .wait_for_sync = corgi_wait_for_hsync,
436}; 446};
437 447
438static void corgi_ads7846_cs(u32 command) 448static void corgi_ads7846_cs(u32 command)
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index e13f6a81c223..c872b9feb4d4 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -334,6 +334,11 @@ static struct led_info littleton_da9034_leds[] = {
334 }, 334 },
335}; 335};
336 336
337static struct da9034_touch_pdata littleton_da9034_touch = {
338 .x_inverted = 1,
339 .interval_ms = 20,
340};
341
337static struct da903x_subdev_info littleton_da9034_subdevs[] = { 342static struct da903x_subdev_info littleton_da9034_subdevs[] = {
338 { 343 {
339 .name = "da903x-led", 344 .name = "da903x-led",
@@ -350,6 +355,10 @@ static struct da903x_subdev_info littleton_da9034_subdevs[] = {
350 }, { 355 }, {
351 .name = "da903x-backlight", 356 .name = "da903x-backlight",
352 .id = DA9034_ID_WLED, 357 .id = DA9034_ID_WLED,
358 }, {
359 .name = "da9034-touch",
360 .id = DA9034_ID_TOUCH,
361 .platform_data = &littleton_da9034_touch,
353 }, 362 },
354}; 363};
355 364
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 8c61ddac119e..c18e34acafcb 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -299,12 +299,22 @@ static struct pxa2xx_spi_master spitz_spi_info = {
299 .num_chipselect = 3, 299 .num_chipselect = 3,
300}; 300};
301 301
302static void spitz_wait_for_hsync(void)
303{
304 while (gpio_get_value(SPITZ_GPIO_HSYNC))
305 cpu_relax();
306
307 while (!gpio_get_value(SPITZ_GPIO_HSYNC))
308 cpu_relax();
309}
310
302static struct ads7846_platform_data spitz_ads7846_info = { 311static struct ads7846_platform_data spitz_ads7846_info = {
303 .model = 7846, 312 .model = 7846,
304 .vref_delay_usecs = 100, 313 .vref_delay_usecs = 100,
305 .x_plate_ohms = 419, 314 .x_plate_ohms = 419,
306 .y_plate_ohms = 486, 315 .y_plate_ohms = 486,
307 .gpio_pendown = SPITZ_GPIO_TP_INT, 316 .gpio_pendown = SPITZ_GPIO_TP_INT,
317 .wait_for_sync = spitz_wait_for_hsync,
308}; 318};
309 319
310static void spitz_ads7846_cs(u32 command) 320static void spitz_ads7846_cs(u32 command)
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index c1f73205d078..c256c57642c0 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -72,6 +72,7 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
72 GPIO25_AC97_SDATA_IN_0, 72 GPIO25_AC97_SDATA_IN_0,
73 GPIO27_AC97_SDATA_OUT, 73 GPIO27_AC97_SDATA_OUT,
74 GPIO28_AC97_SYNC, 74 GPIO28_AC97_SYNC,
75 GPIO17_GPIO, /* SDATA_IN_1 but unused - configure to GPIO */
75 76
76 /* SSP3 */ 77 /* SSP3 */
77 GPIO91_SSP3_SCLK, 78 GPIO91_SSP3_SCLK,
@@ -126,6 +127,10 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
126 /* Standard I2C */ 127 /* Standard I2C */
127 GPIO21_I2C_SCL, 128 GPIO21_I2C_SCL,
128 GPIO22_I2C_SDA, 129 GPIO22_I2C_SDA,
130
131 /* GPIO */
132 GPIO18_GPIO, /* GPIO Expander #0 INT_N */
133 GPIO19_GPIO, /* GPIO Expander #1 INT_N */
129}; 134};
130 135
131static mfp_cfg_t pxa300_mfp_cfg[] __initdata = { 136static mfp_cfg_t pxa300_mfp_cfg[] __initdata = {
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
index 4e1c488c6906..cc5a22833605 100644
--- a/arch/arm/mach-pxa/zylonite_pxa320.c
+++ b/arch/arm/mach-pxa/zylonite_pxa320.c
@@ -68,6 +68,7 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
68 GPIO38_AC97_SYNC, 68 GPIO38_AC97_SYNC,
69 GPIO39_AC97_BITCLK, 69 GPIO39_AC97_BITCLK,
70 GPIO40_AC97_nACRESET, 70 GPIO40_AC97_nACRESET,
71 GPIO36_GPIO, /* SDATA_IN_1 but unused - configure to GPIO */
71 72
72 /* SSP3 */ 73 /* SSP3 */
73 GPIO89_SSP3_SCLK, 74 GPIO89_SSP3_SCLK,
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
index c9cfe40e21f6..a7417c479ffe 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -21,6 +21,7 @@
21#include <linux/io.h> 21#include <linux/io.h>
22 22
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24#include <asm/cacheflush.h>
24#include <asm/irq.h> 25#include <asm/irq.h>
25 26
26#include <mach/regs-power.h> 27#include <mach/regs-power.h>
@@ -39,6 +40,8 @@ static void s3c2412_cpu_suspend(void)
39{ 40{
40 unsigned long tmp; 41 unsigned long tmp;
41 42
43 flush_cache_all();
44
42 /* set our standby method to sleep */ 45 /* set our standby method to sleep */
43 46
44 tmp = __raw_readl(S3C2412_PWRCFG); 47 tmp = __raw_readl(S3C2412_PWRCFG);
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h
index baf1c0f1ea5a..8199972ed5bd 100644
--- a/arch/arm/mach-s3c6400/include/mach/map.h
+++ b/arch/arm/mach-s3c6400/include/mach/map.h
@@ -40,6 +40,8 @@
40 40
41#define S3C64XX_PA_FB (0x77100000) 41#define S3C64XX_PA_FB (0x77100000)
42#define S3C64XX_PA_SYSCON (0x7E00F000) 42#define S3C64XX_PA_SYSCON (0x7E00F000)
43#define S3C64XX_PA_IIS0 (0x7F002000)
44#define S3C64XX_PA_IIS1 (0x7F003000)
43#define S3C64XX_PA_TIMER (0x7F006000) 45#define S3C64XX_PA_TIMER (0x7F006000)
44#define S3C64XX_PA_IIC0 (0x7F004000) 46#define S3C64XX_PA_IIC0 (0x7F004000)
45#define S3C64XX_PA_IIC1 (0x7F00F000) 47#define S3C64XX_PA_IIC1 (0x7F00F000)
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index 0cd52692d2f7..1f940df0e5af 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -9,6 +9,7 @@
9#include <mach/hardware.h> 9#include <mach/hardware.h>
10#include <asm/setup.h> 10#include <asm/setup.h>
11#include <asm/mach-types.h> 11#include <asm/mach-types.h>
12#include <asm/page.h>
12 13
13#include <asm/mach/arch.h> 14#include <asm/mach/arch.h>
14#include <asm/mach/map.h> 15#include <asm/mach/map.h>
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 2c6c2a7c05a0..8f5c13f4c936 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -20,6 +20,31 @@
20#define D_CACHE_LINE_SIZE 32 20#define D_CACHE_LINE_SIZE 32
21#define BTB_FLUSH_SIZE 8 21#define BTB_FLUSH_SIZE 8
22 22
23#ifdef CONFIG_ARM_ERRATA_411920
24/*
25 * Invalidate the entire I cache (this code is a workaround for the ARM1136
26 * erratum 411920 - Invalidate Instruction Cache operation can fail. This
27 * erratum is present in 1136, 1156 and 1176. It does not affect the MPCore.
28 *
29 * Registers:
30 * r0 - set to 0
31 * r1 - corrupted
32 */
33ENTRY(v6_icache_inval_all)
34 mov r0, #0
35 mrs r1, cpsr
36 cpsid ifa @ disable interrupts
37 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
38 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
39 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
40 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
41 msr cpsr_cx, r1 @ restore interrupts
42 .rept 11 @ ARM Ltd recommends at least
43 nop @ 11 NOPs
44 .endr
45 mov pc, lr
46#endif
47
23/* 48/*
24 * v6_flush_cache_all() 49 * v6_flush_cache_all()
25 * 50 *
@@ -31,8 +56,12 @@ ENTRY(v6_flush_kern_cache_all)
31 mov r0, #0 56 mov r0, #0
32#ifdef HARVARD_CACHE 57#ifdef HARVARD_CACHE
33 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 58 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
59#ifndef CONFIG_ARM_ERRATA_411920
34 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 60 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
35#else 61#else
62 b v6_icache_inval_all
63#endif
64#else
36 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 65 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
37#endif 66#endif
38 mov pc, lr 67 mov pc, lr
@@ -103,8 +132,12 @@ ENTRY(v6_coherent_user_range)
103 mov r0, #0 132 mov r0, #0
104#ifdef HARVARD_CACHE 133#ifdef HARVARD_CACHE
105 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 134 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
135#ifndef CONFIG_ARM_ERRATA_411920
106 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 136 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
107#else 137#else
138 b v6_icache_inval_all
139#endif
140#else
108 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 141 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
109#endif 142#endif
110 mov pc, lr 143 mov pc, lr
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 4e283481cee1..c07222eb5ce0 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -18,6 +18,10 @@
18 18
19#include "mm.h" 19#include "mm.h"
20 20
21#ifdef CONFIG_ARM_ERRATA_411920
22extern void v6_icache_inval_all(void);
23#endif
24
21#ifdef CONFIG_CPU_CACHE_VIPT 25#ifdef CONFIG_CPU_CACHE_VIPT
22 26
23#define ALIAS_FLUSH_START 0xffff4000 27#define ALIAS_FLUSH_START 0xffff4000
@@ -32,10 +36,15 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
32 36
33 asm( "mcrr p15, 0, %1, %0, c14\n" 37 asm( "mcrr p15, 0, %1, %0, c14\n"
34 " mcr p15, 0, %2, c7, c10, 4\n" 38 " mcr p15, 0, %2, c7, c10, 4\n"
39#ifndef CONFIG_ARM_ERRATA_411920
35 " mcr p15, 0, %2, c7, c5, 0\n" 40 " mcr p15, 0, %2, c7, c5, 0\n"
41#endif
36 : 42 :
37 : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero) 43 : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
38 : "cc"); 44 : "cc");
45#ifdef CONFIG_ARM_ERRATA_411920
46 v6_icache_inval_all();
47#endif
39} 48}
40 49
41void flush_cache_mm(struct mm_struct *mm) 50void flush_cache_mm(struct mm_struct *mm)
@@ -48,11 +57,16 @@ void flush_cache_mm(struct mm_struct *mm)
48 57
49 if (cache_is_vipt_aliasing()) { 58 if (cache_is_vipt_aliasing()) {
50 asm( "mcr p15, 0, %0, c7, c14, 0\n" 59 asm( "mcr p15, 0, %0, c7, c14, 0\n"
60 " mcr p15, 0, %0, c7, c10, 4\n"
61#ifndef CONFIG_ARM_ERRATA_411920
51 " mcr p15, 0, %0, c7, c5, 0\n" 62 " mcr p15, 0, %0, c7, c5, 0\n"
52 " mcr p15, 0, %0, c7, c10, 4" 63#endif
53 : 64 :
54 : "r" (0) 65 : "r" (0)
55 : "cc"); 66 : "cc");
67#ifdef CONFIG_ARM_ERRATA_411920
68 v6_icache_inval_all();
69#endif
56 } 70 }
57} 71}
58 72
@@ -67,11 +81,16 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned
67 81
68 if (cache_is_vipt_aliasing()) { 82 if (cache_is_vipt_aliasing()) {
69 asm( "mcr p15, 0, %0, c7, c14, 0\n" 83 asm( "mcr p15, 0, %0, c7, c14, 0\n"
84 " mcr p15, 0, %0, c7, c10, 4\n"
85#ifndef CONFIG_ARM_ERRATA_411920
70 " mcr p15, 0, %0, c7, c5, 0\n" 86 " mcr p15, 0, %0, c7, c5, 0\n"
71 " mcr p15, 0, %0, c7, c10, 4" 87#endif
72 : 88 :
73 : "r" (0) 89 : "r" (0)
74 : "cc"); 90 : "cc");
91#ifdef CONFIG_ARM_ERRATA_411920
92 v6_icache_inval_all();
93#endif
75 } 94 }
76} 95}
77 96
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index f0cc599facb7..087e239704df 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -10,6 +10,7 @@
10 * 10 *
11 * This is the "shell" of the ARMv6 processor support. 11 * This is the "shell" of the ARMv6 processor support.
12 */ 12 */
13#include <linux/init.h>
13#include <linux/linkage.h> 14#include <linux/linkage.h>
14#include <asm/assembler.h> 15#include <asm/assembler.h>
15#include <asm/asm-offsets.h> 16#include <asm/asm-offsets.h>
@@ -132,7 +133,7 @@ cpu_v6_name:
132 .asciz "ARMv6-compatible processor" 133 .asciz "ARMv6-compatible processor"
133 .align 134 .align
134 135
135 .section ".text.init", #alloc, #execinstr 136 __INIT
136 137
137/* 138/*
138 * __v6_setup 139 * __v6_setup
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index d1ebec42521d..3397f1e64d76 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -9,6 +9,7 @@
9 * 9 *
10 * This is the "shell" of the ARMv7 processor support. 10 * This is the "shell" of the ARMv7 processor support.
11 */ 11 */
12#include <linux/init.h>
12#include <linux/linkage.h> 13#include <linux/linkage.h>
13#include <asm/assembler.h> 14#include <asm/assembler.h>
14#include <asm/asm-offsets.h> 15#include <asm/asm-offsets.h>
@@ -95,6 +96,9 @@ ENTRY(cpu_v7_switch_mm)
95 mov r2, #0 96 mov r2, #0
96 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 97 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
97 orr r0, r0, #TTB_FLAGS 98 orr r0, r0, #TTB_FLAGS
99#ifdef CONFIG_ARM_ERRATA_430973
100 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
101#endif
98 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID 102 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
99 isb 103 isb
1001: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 1041: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
@@ -153,7 +157,7 @@ cpu_v7_name:
153 .ascii "ARMv7 Processor" 157 .ascii "ARMv7 Processor"
154 .align 158 .align
155 159
156 .section ".text.init", #alloc, #execinstr 160 __INIT
157 161
158/* 162/*
159 * __v7_setup 163 * __v7_setup
@@ -180,6 +184,22 @@ __v7_setup:
180 stmia r12, {r0-r5, r7, r9, r11, lr} 184 stmia r12, {r0-r5, r7, r9, r11, lr}
181 bl v7_flush_dcache_all 185 bl v7_flush_dcache_all
182 ldmia r12, {r0-r5, r7, r9, r11, lr} 186 ldmia r12, {r0-r5, r7, r9, r11, lr}
187#ifdef CONFIG_ARM_ERRATA_430973
188 mrc p15, 0, r10, c1, c0, 1 @ read aux control register
189 orr r10, r10, #(1 << 6) @ set IBE to 1
190 mcr p15, 0, r10, c1, c0, 1 @ write aux control register
191#endif
192#ifdef CONFIG_ARM_ERRATA_458693
193 mrc p15, 0, r10, c1, c0, 1 @ read aux control register
194 orr r10, r10, #(1 << 5) @ set L1NEON to 1
195 orr r10, r10, #(1 << 9) @ set PLDNOP to 1
196 mcr p15, 0, r10, c1, c0, 1 @ write aux control register
197#endif
198#ifdef CONFIG_ARM_ERRATA_460075
199 mrc p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
200 orr r10, r10, #(1 << 22) @ set the Write Allocate disable bit
201 mcr p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
202#endif
183 mov r10, #0 203 mov r10, #0
184#ifdef HARVARD_CACHE 204#ifdef HARVARD_CACHE
185 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 205 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S
index 20f84bbaa9bb..73d7d89b04c4 100644
--- a/arch/arm/mm/tlb-v6.S
+++ b/arch/arm/mm/tlb-v6.S
@@ -10,6 +10,7 @@
10 * ARM architecture version 6 TLB handling functions. 10 * ARM architecture version 6 TLB handling functions.
11 * These assume a split I/D TLB. 11 * These assume a split I/D TLB.
12 */ 12 */
13#include <linux/init.h>
13#include <linux/linkage.h> 14#include <linux/linkage.h>
14#include <asm/asm-offsets.h> 15#include <asm/asm-offsets.h>
15#include <asm/page.h> 16#include <asm/page.h>
@@ -87,7 +88,7 @@ ENTRY(v6wbi_flush_kern_tlb_range)
87 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush 88 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush
88 mov pc, lr 89 mov pc, lr
89 90
90 .section ".text.init", #alloc, #execinstr 91 __INIT
91 92
92 .type v6wbi_tlb_fns, #object 93 .type v6wbi_tlb_fns, #object
93ENTRY(v6wbi_tlb_fns) 94ENTRY(v6wbi_tlb_fns)
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index 24ba5109f2e7..b637e7380ab7 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -11,6 +11,7 @@
11 * ARM architecture version 6 TLB handling functions. 11 * ARM architecture version 6 TLB handling functions.
12 * These assume a split I/D TLB. 12 * These assume a split I/D TLB.
13 */ 13 */
14#include <linux/init.h>
14#include <linux/linkage.h> 15#include <linux/linkage.h>
15#include <asm/asm-offsets.h> 16#include <asm/asm-offsets.h>
16#include <asm/page.h> 17#include <asm/page.h>
@@ -80,7 +81,7 @@ ENTRY(v7wbi_flush_kern_tlb_range)
80 mov pc, lr 81 mov pc, lr
81ENDPROC(v7wbi_flush_kern_tlb_range) 82ENDPROC(v7wbi_flush_kern_tlb_range)
82 83
83 .section ".text.init", #alloc, #execinstr 84 __INIT
84 85
85 .type v7wbi_tlb_fns, #object 86 .type v7wbi_tlb_fns, #object
86ENTRY(v7wbi_tlb_fns) 87ENTRY(v7wbi_tlb_fns)
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
index e364a5ed10f1..77646436c00e 100644
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ b/arch/arm/plat-mxc/dma-mx1-mx2.c
@@ -693,12 +693,15 @@ int imx_dma_request(int channel, const char *name)
693 local_irq_restore(flags); 693 local_irq_restore(flags);
694 return -EBUSY; 694 return -EBUSY;
695 } 695 }
696 memset(imxdma, 0, sizeof(imxdma));
697 imxdma->name = name;
698 local_irq_restore(flags); /* request_irq() can block */
696 699
697#ifdef CONFIG_ARCH_MX2 700#ifdef CONFIG_ARCH_MX2
698 ret = request_irq(MXC_INT_DMACH0 + channel, dma_irq_handler, 0, "DMA", 701 ret = request_irq(MXC_INT_DMACH0 + channel, dma_irq_handler, 0, "DMA",
699 NULL); 702 NULL);
700 if (ret) { 703 if (ret) {
701 local_irq_restore(flags); 704 imxdma->name = NULL;
702 printk(KERN_CRIT "Can't register IRQ %d for DMA channel %d\n", 705 printk(KERN_CRIT "Can't register IRQ %d for DMA channel %d\n",
703 MXC_INT_DMACH0 + channel, channel); 706 MXC_INT_DMACH0 + channel, channel);
704 return ret; 707 return ret;
@@ -708,13 +711,6 @@ int imx_dma_request(int channel, const char *name)
708 imxdma->watchdog.data = channel; 711 imxdma->watchdog.data = channel;
709#endif 712#endif
710 713
711 imxdma->name = name;
712 imxdma->irq_handler = NULL;
713 imxdma->err_handler = NULL;
714 imxdma->data = NULL;
715 imxdma->sg = NULL;
716
717 local_irq_restore(flags);
718 return ret; 714 return ret;
719} 715}
720EXPORT_SYMBOL(imx_dma_request); 716EXPORT_SYMBOL(imx_dma_request);
@@ -737,10 +733,7 @@ void imx_dma_free(int channel)
737 733
738 local_irq_save(flags); 734 local_irq_save(flags);
739 /* Disable interrupts */ 735 /* Disable interrupts */
740 __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) | (1 << channel), 736 imx_dma_disable(channel);
741 DMA_BASE + DMA_DIMR);
742 __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) & ~CCR_CEN,
743 DMA_BASE + DMA_CCR(channel));
744 imxdma->name = NULL; 737 imxdma->name = NULL;
745 738
746#ifdef CONFIG_ARCH_MX2 739#ifdef CONFIG_ARCH_MX2
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index c6483bad8a26..89e95798cc3b 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -124,7 +124,7 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
124 124
125 irq_stat = __raw_readl(port->base + GPIO_ISR) & 125 irq_stat = __raw_readl(port->base + GPIO_ISR) &
126 __raw_readl(port->base + GPIO_IMR); 126 __raw_readl(port->base + GPIO_IMR);
127 BUG_ON(!irq_stat); 127
128 mxc_gpio_irq_handler(port, irq_stat); 128 mxc_gpio_irq_handler(port, irq_stat);
129} 129}
130#endif 130#endif
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
index 1cac9d1135cd..d42f4e6116f8 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
@@ -47,7 +47,7 @@
47/* 47/*
48 * Base address of PBC controller, CS4 48 * Base address of PBC controller, CS4
49 */ 49 */
50#define PBC_BASE_ADDRESS 0xEB000000 50#define PBC_BASE_ADDRESS 0xf4300000
51#define PBC_REG_ADDR(offset) (void __force __iomem *) \ 51#define PBC_REG_ADDR(offset) (void __force __iomem *) \
52 (PBC_BASE_ADDRESS + (offset)) 52 (PBC_BASE_ADDRESS + (offset))
53 53
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 2e0614552ac8..29efc279287a 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -239,6 +239,13 @@ void recalculate_root_clocks(void)
239 } 239 }
240} 240}
241 241
242/**
243 * clk_init_one - initialize any fields in the struct clk before clk init
244 * @clk: struct clk * to initialize
245 *
246 * Initialize any struct clk fields needed before normal clk initialization
247 * can run. No return value.
248 */
242void clk_init_one(struct clk *clk) 249void clk_init_one(struct clk *clk)
243{ 250{
244 INIT_LIST_HEAD(&clk->children); 251 INIT_LIST_HEAD(&clk->children);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 21cc0142b97a..7fc8c045ad5d 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -760,19 +760,12 @@ void omap_free_dma(int lch)
760{ 760{
761 unsigned long flags; 761 unsigned long flags;
762 762
763 spin_lock_irqsave(&dma_chan_lock, flags);
764 if (dma_chan[lch].dev_id == -1) { 763 if (dma_chan[lch].dev_id == -1) {
765 pr_err("omap_dma: trying to free unallocated DMA channel %d\n", 764 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
766 lch); 765 lch);
767 spin_unlock_irqrestore(&dma_chan_lock, flags);
768 return; 766 return;
769 } 767 }
770 768
771 dma_chan[lch].dev_id = -1;
772 dma_chan[lch].next_lch = -1;
773 dma_chan[lch].callback = NULL;
774 spin_unlock_irqrestore(&dma_chan_lock, flags);
775
776 if (cpu_class_is_omap1()) { 769 if (cpu_class_is_omap1()) {
777 /* Disable all DMA interrupts for the channel. */ 770 /* Disable all DMA interrupts for the channel. */
778 dma_write(0, CICR(lch)); 771 dma_write(0, CICR(lch));
@@ -798,6 +791,12 @@ void omap_free_dma(int lch)
798 dma_write(0, CCR(lch)); 791 dma_write(0, CCR(lch));
799 omap_clear_dma(lch); 792 omap_clear_dma(lch);
800 } 793 }
794
795 spin_lock_irqsave(&dma_chan_lock, flags);
796 dma_chan[lch].dev_id = -1;
797 dma_chan[lch].next_lch = -1;
798 dma_chan[lch].callback = NULL;
799 spin_unlock_irqrestore(&dma_chan_lock, flags);
801} 800}
802EXPORT_SYMBOL(omap_free_dma); 801EXPORT_SYMBOL(omap_free_dma);
803 802
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index bfd47570cc91..55bb99631292 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -238,7 +238,7 @@ static struct omap_dm_timer omap3_dm_timers[] = {
238 { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 }, 238 { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 },
239 { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 }, 239 { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
240 { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 }, 240 { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
241 { .phys_base = 0x48304000, .irq = INT_24XX_GPTIMER12 }, 241 { .phys_base = 0x48304000, .irq = INT_34XX_GPT12_IRQ },
242}; 242};
243 243
244static const char *omap3_dm_source_names[] __initdata = { 244static const char *omap3_dm_source_names[] __initdata = {
@@ -321,11 +321,9 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
321 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */ 321 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
322 322
323 /* 323 /*
324 * Enable wake-up only for GPT1 on OMAP2 CPUs. 324 * Enable wake-up on OMAP2 CPUs.
325 * FIXME: All timers should have wake-up enabled and clear
326 * PRCM status.
327 */ 325 */
328 if (cpu_class_is_omap2() && (timer == &dm_timers[0])) 326 if (cpu_class_is_omap2())
329 l |= 1 << 2; 327 l |= 1 << 2;
330 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l); 328 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
331 329
@@ -511,7 +509,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
511 509
512#ifdef CONFIG_ARCH_OMAP1 510#ifdef CONFIG_ARCH_OMAP1
513 511
514void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) 512int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
515{ 513{
516 int n = (timer - dm_timers) << 1; 514 int n = (timer - dm_timers) << 1;
517 u32 l; 515 u32 l;
@@ -519,23 +517,31 @@ void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
519 l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); 517 l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
520 l |= source << n; 518 l |= source << n;
521 omap_writel(l, MOD_CONF_CTRL_1); 519 omap_writel(l, MOD_CONF_CTRL_1);
520
521 return 0;
522} 522}
523EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); 523EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
524 524
525#else 525#else
526 526
527void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) 527int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
528{ 528{
529 int ret = -EINVAL;
530
529 if (source < 0 || source >= 3) 531 if (source < 0 || source >= 3)
530 return; 532 return -EINVAL;
531 533
532 clk_disable(timer->fclk); 534 clk_disable(timer->fclk);
533 clk_set_parent(timer->fclk, dm_source_clocks[source]); 535 ret = clk_set_parent(timer->fclk, dm_source_clocks[source]);
534 clk_enable(timer->fclk); 536 clk_enable(timer->fclk);
535 537
536 /* When the functional clock disappears, too quick writes seem to 538 /*
537 * cause an abort. */ 539 * When the functional clock disappears, too quick writes seem
540 * to cause an abort. XXX Is this still necessary?
541 */
538 __delay(150000); 542 __delay(150000);
543
544 return ret;
539} 545}
540EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); 546EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
541 547
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index d3fa41e3d8c5..17d7afe42b83 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -758,8 +758,12 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
758 758
759 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 759 /* Workaround for clearing DSP GPIO interrupts to allow retention */
760#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 760#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
761 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
761 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 762 if (cpu_is_omap24xx() || cpu_is_omap34xx())
762 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2); 763 __raw_writel(gpio_mask, reg);
764
765 /* Flush posted write for the irq status to avoid spurious interrupts */
766 __raw_readl(reg);
763#endif 767#endif
764} 768}
765 769
@@ -921,13 +925,10 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
921 case METHOD_MPUIO: 925 case METHOD_MPUIO:
922 case METHOD_GPIO_1610: 926 case METHOD_GPIO_1610:
923 spin_lock_irqsave(&bank->lock, flags); 927 spin_lock_irqsave(&bank->lock, flags);
924 if (enable) { 928 if (enable)
925 bank->suspend_wakeup |= (1 << gpio); 929 bank->suspend_wakeup |= (1 << gpio);
926 enable_irq_wake(bank->irq); 930 else
927 } else {
928 disable_irq_wake(bank->irq);
929 bank->suspend_wakeup &= ~(1 << gpio); 931 bank->suspend_wakeup &= ~(1 << gpio);
930 }
931 spin_unlock_irqrestore(&bank->lock, flags); 932 spin_unlock_irqrestore(&bank->lock, flags);
932 return 0; 933 return 0;
933#endif 934#endif
@@ -940,13 +941,10 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
940 return -EINVAL; 941 return -EINVAL;
941 } 942 }
942 spin_lock_irqsave(&bank->lock, flags); 943 spin_lock_irqsave(&bank->lock, flags);
943 if (enable) { 944 if (enable)
944 bank->suspend_wakeup |= (1 << gpio); 945 bank->suspend_wakeup |= (1 << gpio);
945 enable_irq_wake(bank->irq); 946 else
946 } else {
947 disable_irq_wake(bank->irq);
948 bank->suspend_wakeup &= ~(1 << gpio); 947 bank->suspend_wakeup &= ~(1 << gpio);
949 }
950 spin_unlock_irqrestore(&bank->lock, flags); 948 spin_unlock_irqrestore(&bank->lock, flags);
951 return 0; 949 return 0;
952#endif 950#endif
diff --git a/arch/arm/plat-omap/include/mach/dmtimer.h b/arch/arm/plat-omap/include/mach/dmtimer.h
index 6dc703138210..20f1054c0a80 100644
--- a/arch/arm/plat-omap/include/mach/dmtimer.h
+++ b/arch/arm/plat-omap/include/mach/dmtimer.h
@@ -64,7 +64,7 @@ void omap_dm_timer_trigger(struct omap_dm_timer *timer);
64void omap_dm_timer_start(struct omap_dm_timer *timer); 64void omap_dm_timer_start(struct omap_dm_timer *timer);
65void omap_dm_timer_stop(struct omap_dm_timer *timer); 65void omap_dm_timer_stop(struct omap_dm_timer *timer);
66 66
67void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source); 67int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
68void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value); 68void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
69void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value); 69void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
70void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match); 70void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
diff --git a/arch/arm/plat-omap/include/mach/eac.h b/arch/arm/plat-omap/include/mach/eac.h
deleted file mode 100644
index 9e62cf030270..000000000000
--- a/arch/arm/plat-omap/include/mach/eac.h
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach2/eac.h
3 *
4 * Defines for Enhanced Audio Controller
5 *
6 * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
7 *
8 * Copyright (C) 2006 Nokia Corporation
9 * Copyright (C) 2004 Texas Instruments, Inc.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 */
26
27#ifndef __ASM_ARM_ARCH_OMAP2_EAC_H
28#define __ASM_ARM_ARCH_OMAP2_EAC_H
29
30#include <mach/io.h>
31#include <mach/hardware.h>
32#include <asm/irq.h>
33
34#include <sound/core.h>
35
36/* master codec clock source */
37#define EAC_MCLK_EXT_MASK 0x100
38enum eac_mclk_src {
39 EAC_MCLK_INT_11290000, /* internal 96 MHz / 8.5 = 11.29 Mhz */
40 EAC_MCLK_EXT_11289600 = EAC_MCLK_EXT_MASK,
41 EAC_MCLK_EXT_12288000,
42 EAC_MCLK_EXT_2x11289600,
43 EAC_MCLK_EXT_2x12288000,
44};
45
46/* codec port interface mode */
47enum eac_codec_mode {
48 EAC_CODEC_PCM,
49 EAC_CODEC_AC97,
50 EAC_CODEC_I2S_MASTER, /* codec port, I.e. EAC is the master */
51 EAC_CODEC_I2S_SLAVE,
52};
53
54/* configuration structure for I2S mode */
55struct eac_i2s_conf {
56 /* if enabled, then first data slot (left channel) is signaled as
57 * positive level of frame sync EAC.AC_FS */
58 unsigned polarity_changed_mode:1;
59 /* if enabled, then serial data starts one clock cycle after the
60 * of EAC.AC_FS for first audio slot */
61 unsigned sync_delay_enable:1;
62};
63
64/* configuration structure for EAC codec port */
65struct eac_codec {
66 enum eac_mclk_src mclk_src;
67
68 enum eac_codec_mode codec_mode;
69 union {
70 struct eac_i2s_conf i2s;
71 } codec_conf;
72
73 int default_rate; /* audio sampling rate */
74
75 int (* set_power)(void *private_data, int dac, int adc);
76 int (* register_controls)(void *private_data,
77 struct snd_card *card);
78 const char *short_name;
79
80 void *private_data;
81};
82
83/* structure for passing platform dependent data to the EAC driver */
84struct eac_platform_data {
85 int (* init)(struct device *eac_dev);
86 void (* cleanup)(struct device *eac_dev);
87 /* these callbacks are used to configure & control external MCLK
88 * source. NULL if not used */
89 int (* enable_ext_clocks)(struct device *eac_dev);
90 void (* disable_ext_clocks)(struct device *eac_dev);
91};
92
93extern void omap_init_eac(struct eac_platform_data *pdata);
94
95extern int eac_register_codec(struct device *eac_dev, struct eac_codec *codec);
96extern void eac_unregister_codec(struct device *eac_dev);
97
98extern int eac_set_mode(struct device *eac_dev, int play, int rec);
99
100#endif /* __ASM_ARM_ARCH_OMAP2_EAC_H */
diff --git a/arch/arm/plat-omap/include/mach/gpioexpander.h b/arch/arm/plat-omap/include/mach/gpioexpander.h
deleted file mode 100644
index 90444a0d6b1a..000000000000
--- a/arch/arm/plat-omap/include/mach/gpioexpander.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/gpioexpander.h
3 *
4 *
5 * Copyright (C) 2004 Texas Instruments, Inc.
6 *
7 * This package is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
12 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
13 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 */
15
16#ifndef __ASM_ARCH_OMAP_GPIOEXPANDER_H
17#define __ASM_ARCH_OMAP_GPIOEXPANDER_H
18
19/* Function Prototypes for GPIO Expander functions */
20
21#ifdef CONFIG_GPIOEXPANDER_OMAP
22int read_gpio_expa(u8 *, int);
23int write_gpio_expa(u8 , int);
24#else
25static inline int read_gpio_expa(u8 *val, int addr)
26{
27 return 0;
28}
29static inline int write_gpio_expa(u8 val, int addr)
30{
31 return 0;
32}
33#endif
34
35#endif /* __ASM_ARCH_OMAP_GPIOEXPANDER_H */
diff --git a/arch/arm/plat-omap/include/mach/irda.h b/arch/arm/plat-omap/include/mach/irda.h
index 8372a00d8e0b..40f60339d1c6 100644
--- a/arch/arm/plat-omap/include/mach/irda.h
+++ b/arch/arm/plat-omap/include/mach/irda.h
@@ -21,10 +21,6 @@ struct omap_irda_config {
21 int transceiver_cap; 21 int transceiver_cap;
22 int (*transceiver_mode)(struct device *dev, int mode); 22 int (*transceiver_mode)(struct device *dev, int mode);
23 int (*select_irda)(struct device *dev, int state); 23 int (*select_irda)(struct device *dev, int state);
24 /* Very specific to the needs of some platforms (h3,h4)
25 * having calls which can sleep in irda_set_speed.
26 */
27 struct delayed_work gpio_expa;
28 int rx_channel; 24 int rx_channel;
29 int tx_channel; 25 int tx_channel;
30 unsigned long dest_start; 26 unsigned long dest_start;
diff --git a/arch/arm/plat-omap/include/mach/mmc.h b/arch/arm/plat-omap/include/mach/mmc.h
index 4435bd434e17..81d5b36534b3 100644
--- a/arch/arm/plat-omap/include/mach/mmc.h
+++ b/arch/arm/plat-omap/include/mach/mmc.h
@@ -79,7 +79,6 @@ struct omap_mmc_platform_data {
79 79
80 /* use the internal clock */ 80 /* use the internal clock */
81 unsigned internal_clock:1; 81 unsigned internal_clock:1;
82 s16 power_pin;
83 82
84 int switch_pin; /* gpio (card detect) */ 83 int switch_pin; /* gpio (card detect) */
85 int gpio_wp; /* gpio (write protect) */ 84 int gpio_wp; /* gpio (write protect) */
diff --git a/arch/arm/plat-omap/include/mach/timer-gp.h b/arch/arm/plat-omap/include/mach/timer-gp.h
new file mode 100644
index 000000000000..c88d346b59d9
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/timer-gp.h
@@ -0,0 +1,17 @@
1/*
2 * OMAP2/3 GPTIMER support.headers
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
12#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
13
14int __init omap2_gp_clockevent_set_gptimer(u8 id);
15
16#endif
17
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c
index af819bf21b63..abc79d44acaa 100644
--- a/arch/arm/plat-pxa/gpio.c
+++ b/arch/arm/plat-pxa/gpio.c
@@ -121,6 +121,8 @@ static int __init pxa_init_gpio_chip(int gpio_end)
121 return -ENOMEM; 121 return -ENOMEM;
122 } 122 }
123 123
124 memset(chips, 0, nbanks * sizeof(struct pxa_gpio_chip));
125
124 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { 126 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
125 struct gpio_chip *c = &chips[i].chip; 127 struct gpio_chip *c = &chips[i].chip;
126 128
@@ -143,6 +145,21 @@ static int __init pxa_init_gpio_chip(int gpio_end)
143 return 0; 145 return 0;
144} 146}
145 147
148/* Update only those GRERx and GFERx edge detection register bits if those
149 * bits are set in c->irq_mask
150 */
151static inline void update_edge_detect(struct pxa_gpio_chip *c)
152{
153 uint32_t grer, gfer;
154
155 grer = __raw_readl(c->regbase + GRER_OFFSET) & ~c->irq_mask;
156 gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~c->irq_mask;
157 grer |= c->irq_edge_rise & c->irq_mask;
158 gfer |= c->irq_edge_fall & c->irq_mask;
159 __raw_writel(grer, c->regbase + GRER_OFFSET);
160 __raw_writel(gfer, c->regbase + GFER_OFFSET);
161}
162
146static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) 163static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
147{ 164{
148 struct pxa_gpio_chip *c; 165 struct pxa_gpio_chip *c;
@@ -181,8 +198,7 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
181 else 198 else
182 c->irq_edge_fall &= ~mask; 199 c->irq_edge_fall &= ~mask;
183 200
184 __raw_writel(c->irq_edge_rise & c->irq_mask, c->regbase + GRER_OFFSET); 201 update_edge_detect(c);
185 __raw_writel(c->irq_edge_fall & c->irq_mask, c->regbase + GFER_OFFSET);
186 202
187 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio, 203 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
188 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), 204 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
@@ -244,8 +260,7 @@ static void pxa_unmask_muxed_gpio(unsigned int irq)
244 struct pxa_gpio_chip *c = gpio_to_chip(gpio); 260 struct pxa_gpio_chip *c = gpio_to_chip(gpio);
245 261
246 c->irq_mask |= GPIO_bit(gpio); 262 c->irq_mask |= GPIO_bit(gpio);
247 __raw_writel(c->irq_edge_rise & c->irq_mask, c->regbase + GRER_OFFSET); 263 update_edge_detect(c);
248 __raw_writel(c->irq_edge_fall & c->irq_mask, c->regbase + GFER_OFFSET);
249} 264}
250 265
251static struct irq_chip pxa_muxed_gpio_chip = { 266static struct irq_chip pxa_muxed_gpio_chip = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 07:18:00 -0500