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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-s3c64xx/clock.c2
-rw-r--r--arch/arm/mach-s3c64xx/dev-audio.c60
-rw-r--r--arch/arm/mach-s5p6442/dev-audio.c44
-rw-r--r--arch/arm/mach-s5p6442/include/mach/map.h3
-rw-r--r--arch/arm/mach-s5p6442/mach-smdk6442.c10
-rw-r--r--arch/arm/mach-s5p6442/setup-i2c0.c5
-rw-r--r--arch/arm/mach-s5p64x0/Makefile4
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c8
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c20
-rw-r--r--arch/arm/mach-s5p64x0/dev-audio.c144
-rw-r--r--arch/arm/mach-s5p64x0/gpiolib.c (renamed from arch/arm/mach-s5p64x0/gpio.c)221
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/map.h5
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-gpio.h57
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6440.c1
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6450.c1
-rw-r--r--arch/arm/mach-s5pc100/dev-audio.c54
-rw-r--r--arch/arm/mach-s5pc100/include/mach/map.h2
-rw-r--r--arch/arm/mach-s5pv210/Kconfig2
-rw-r--r--arch/arm/mach-s5pv210/clock.c16
-rw-r--r--arch/arm/mach-s5pv210/cpu.c5
-rw-r--r--arch/arm/mach-s5pv210/dev-audio.c56
-rw-r--r--arch/arm/mach-s5pv210/include/mach/irqs.h3
-rw-r--r--arch/arm/mach-s5pv210/include/mach/map.h6
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-clock.h5
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkc110.c1
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkv210.c139
-rw-r--r--arch/arm/mach-s5pv310/Kconfig16
-rw-r--r--arch/arm/mach-s5pv310/Makefile6
-rw-r--r--arch/arm/mach-s5pv310/clock.c58
-rw-r--r--arch/arm/mach-s5pv310/cpu.c21
-rw-r--r--arch/arm/mach-s5pv310/cpufreq.c580
-rw-r--r--arch/arm/mach-s5pv310/dev-audio.c364
-rw-r--r--arch/arm/mach-s5pv310/dev-pd.c139
-rw-r--r--arch/arm/mach-s5pv310/dma.c168
-rw-r--r--arch/arm/mach-s5pv310/include/mach/dma.h26
-rw-r--r--arch/arm/mach-s5pv310/include/mach/irqs.h19
-rw-r--r--arch/arm/mach-s5pv310/include/mach/map.h31
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-clock.h80
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-mem.h23
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-pmu.h30
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-srom.h50
-rw-r--r--arch/arm/mach-s5pv310/irq-combiner.c6
-rw-r--r--arch/arm/mach-s5pv310/mach-smdkc210.c51
-rw-r--r--arch/arm/mach-s5pv310/mach-smdkv310.c51
-rw-r--r--arch/arm/mach-s5pv310/mach-universal_c210.c80
-rw-r--r--arch/arm/plat-s5p/Kconfig10
-rw-r--r--arch/arm/plat-s5p/Makefile2
-rw-r--r--arch/arm/plat-s5p/cpu.c5
-rw-r--r--arch/arm/plat-s5p/dev-csis0.c34
-rw-r--r--arch/arm/plat-s5p/dev-csis1.c34
-rw-r--r--arch/arm/plat-s5p/include/plat/csis.h28
-rw-r--r--arch/arm/plat-s5p/include/plat/map-s5p.h1
-rw-r--r--arch/arm/plat-s5p/include/plat/regs-srom.h54
-rw-r--r--arch/arm/plat-samsung/gpiolib.c7
-rw-r--r--arch/arm/plat-samsung/include/plat/audio.h24
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h15
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-core.h2
58 files changed, 2608 insertions, 282 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d56d21c0573b..5ecaec63a47b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -738,6 +738,7 @@ config ARCH_S5PV310
738 select ARCH_SPARSEMEM_ENABLE 738 select ARCH_SPARSEMEM_ENABLE
739 select GENERIC_GPIO 739 select GENERIC_GPIO
740 select HAVE_CLK 740 select HAVE_CLK
741 select ARCH_HAS_CPUFREQ
741 select GENERIC_CLOCKEVENTS 742 select GENERIC_CLOCKEVENTS
742 select HAVE_S3C_RTC if RTC_CLASS 743 select HAVE_S3C_RTC if RTC_CLASS
743 select HAVE_S3C2410_I2C if I2C 744 select HAVE_S3C2410_I2C if I2C
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 7e03f0ae2fc8..1c98d2ff2ed6 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -695,7 +695,7 @@ static struct clksrc_clk clksrcs[] = {
695 }, { 695 }, {
696 .clk = { 696 .clk = {
697 .name = "audio-bus", 697 .name = "audio-bus",
698 .id = -1, /* There's only one IISv4 port */ 698 .id = 2,
699 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2, 699 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
700 .enable = s3c64xx_sclk_ctrl, 700 .enable = s3c64xx_sclk_ctrl,
701 }, 701 },
diff --git a/arch/arm/mach-s3c64xx/dev-audio.c b/arch/arm/mach-s3c64xx/dev-audio.c
index 76426a32c013..7618627b98f5 100644
--- a/arch/arm/mach-s3c64xx/dev-audio.c
+++ b/arch/arm/mach-s3c64xx/dev-audio.c
@@ -22,7 +22,12 @@
22#include <plat/audio.h> 22#include <plat/audio.h>
23#include <plat/gpio-cfg.h> 23#include <plat/gpio-cfg.h>
24 24
25static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev) 25static const char *rclksrc[] = {
26 [0] = "iis",
27 [1] = "audio-bus",
28};
29
30static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev)
26{ 31{
27 unsigned int base; 32 unsigned int base;
28 33
@@ -33,6 +38,12 @@ static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
33 case 1: 38 case 1:
34 base = S3C64XX_GPE(0); 39 base = S3C64XX_GPE(0);
35 break; 40 break;
41 case 2:
42 s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5));
43 s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5));
44 s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5));
45 s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(5));
46 return 0;
36 default: 47 default:
37 printk(KERN_DEBUG "Invalid I2S Controller number: %d\n", 48 printk(KERN_DEBUG "Invalid I2S Controller number: %d\n",
38 pdev->id); 49 pdev->id);
@@ -44,16 +55,6 @@ static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
44 return 0; 55 return 0;
45} 56}
46 57
47static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev)
48{
49 s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5));
50 s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5));
51 s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5));
52 s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(5));
53
54 return 0;
55}
56
57static struct resource s3c64xx_iis0_resource[] = { 58static struct resource s3c64xx_iis0_resource[] = {
58 [0] = { 59 [0] = {
59 .start = S3C64XX_PA_IIS0, 60 .start = S3C64XX_PA_IIS0,
@@ -72,17 +73,22 @@ static struct resource s3c64xx_iis0_resource[] = {
72 }, 73 },
73}; 74};
74 75
75static struct s3c_audio_pdata s3c_i2s0_pdata = { 76static struct s3c_audio_pdata i2sv3_pdata = {
76 .cfg_gpio = s3c64xx_i2sv3_cfg_gpio, 77 .cfg_gpio = s3c64xx_i2s_cfg_gpio,
78 .type = {
79 .i2s = {
80 .src_clk = rclksrc,
81 },
82 },
77}; 83};
78 84
79struct platform_device s3c64xx_device_iis0 = { 85struct platform_device s3c64xx_device_iis0 = {
80 .name = "s3c64xx-iis", 86 .name = "samsung-i2s",
81 .id = 0, 87 .id = 0,
82 .num_resources = ARRAY_SIZE(s3c64xx_iis0_resource), 88 .num_resources = ARRAY_SIZE(s3c64xx_iis0_resource),
83 .resource = s3c64xx_iis0_resource, 89 .resource = s3c64xx_iis0_resource,
84 .dev = { 90 .dev = {
85 .platform_data = &s3c_i2s0_pdata, 91 .platform_data = &i2sv3_pdata,
86 }, 92 },
87}; 93};
88EXPORT_SYMBOL(s3c64xx_device_iis0); 94EXPORT_SYMBOL(s3c64xx_device_iis0);
@@ -105,17 +111,13 @@ static struct resource s3c64xx_iis1_resource[] = {
105 }, 111 },
106}; 112};
107 113
108static struct s3c_audio_pdata s3c_i2s1_pdata = {
109 .cfg_gpio = s3c64xx_i2sv3_cfg_gpio,
110};
111
112struct platform_device s3c64xx_device_iis1 = { 114struct platform_device s3c64xx_device_iis1 = {
113 .name = "s3c64xx-iis", 115 .name = "samsung-i2s",
114 .id = 1, 116 .id = 1,
115 .num_resources = ARRAY_SIZE(s3c64xx_iis1_resource), 117 .num_resources = ARRAY_SIZE(s3c64xx_iis1_resource),
116 .resource = s3c64xx_iis1_resource, 118 .resource = s3c64xx_iis1_resource,
117 .dev = { 119 .dev = {
118 .platform_data = &s3c_i2s1_pdata, 120 .platform_data = &i2sv3_pdata,
119 }, 121 },
120}; 122};
121EXPORT_SYMBOL(s3c64xx_device_iis1); 123EXPORT_SYMBOL(s3c64xx_device_iis1);
@@ -138,17 +140,23 @@ static struct resource s3c64xx_iisv4_resource[] = {
138 }, 140 },
139}; 141};
140 142
141static struct s3c_audio_pdata s3c_i2sv4_pdata = { 143static struct s3c_audio_pdata i2sv4_pdata = {
142 .cfg_gpio = s3c64xx_i2sv4_cfg_gpio, 144 .cfg_gpio = s3c64xx_i2s_cfg_gpio,
145 .type = {
146 .i2s = {
147 .quirks = QUIRK_PRI_6CHAN,
148 .src_clk = rclksrc,
149 },
150 },
143}; 151};
144 152
145struct platform_device s3c64xx_device_iisv4 = { 153struct platform_device s3c64xx_device_iisv4 = {
146 .name = "s3c64xx-iis-v4", 154 .name = "samsung-i2s",
147 .id = -1, 155 .id = 2,
148 .num_resources = ARRAY_SIZE(s3c64xx_iisv4_resource), 156 .num_resources = ARRAY_SIZE(s3c64xx_iisv4_resource),
149 .resource = s3c64xx_iisv4_resource, 157 .resource = s3c64xx_iisv4_resource,
150 .dev = { 158 .dev = {
151 .platform_data = &s3c_i2sv4_pdata, 159 .platform_data = &i2sv4_pdata,
152 }, 160 },
153}; 161};
154EXPORT_SYMBOL(s3c64xx_device_iisv4); 162EXPORT_SYMBOL(s3c64xx_device_iisv4);
diff --git a/arch/arm/mach-s5p6442/dev-audio.c b/arch/arm/mach-s5p6442/dev-audio.c
index 3462197ff352..8719dc41fe32 100644
--- a/arch/arm/mach-s5p6442/dev-audio.c
+++ b/arch/arm/mach-s5p6442/dev-audio.c
@@ -29,7 +29,7 @@ static int s5p6442_cfg_i2s(struct platform_device *pdev)
29 base = S5P6442_GPC1(0); 29 base = S5P6442_GPC1(0);
30 break; 30 break;
31 31
32 case -1: 32 case 0:
33 base = S5P6442_GPC0(0); 33 base = S5P6442_GPC0(0);
34 break; 34 break;
35 35
@@ -42,8 +42,19 @@ static int s5p6442_cfg_i2s(struct platform_device *pdev)
42 return 0; 42 return 0;
43} 43}
44 44
45static struct s3c_audio_pdata s3c_i2s_pdata = { 45static const char *rclksrc_v35[] = {
46 [0] = "busclk",
47 [1] = "i2sclk",
48};
49
50static struct s3c_audio_pdata i2sv35_pdata = {
46 .cfg_gpio = s5p6442_cfg_i2s, 51 .cfg_gpio = s5p6442_cfg_i2s,
52 .type = {
53 .i2s = {
54 .quirks = QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR,
55 .src_clk = rclksrc_v35,
56 },
57 },
47}; 58};
48 59
49static struct resource s5p6442_iis0_resource[] = { 60static struct resource s5p6442_iis0_resource[] = {
@@ -62,15 +73,34 @@ static struct resource s5p6442_iis0_resource[] = {
62 .end = DMACH_I2S0_RX, 73 .end = DMACH_I2S0_RX,
63 .flags = IORESOURCE_DMA, 74 .flags = IORESOURCE_DMA,
64 }, 75 },
76 [3] = {
77 .start = DMACH_I2S0S_TX,
78 .end = DMACH_I2S0S_TX,
79 .flags = IORESOURCE_DMA,
80 },
65}; 81};
66 82
67struct platform_device s5p6442_device_iis0 = { 83struct platform_device s5p6442_device_iis0 = {
68 .name = "s3c64xx-iis-v4", 84 .name = "samsung-i2s",
69 .id = -1, 85 .id = 0,
70 .num_resources = ARRAY_SIZE(s5p6442_iis0_resource), 86 .num_resources = ARRAY_SIZE(s5p6442_iis0_resource),
71 .resource = s5p6442_iis0_resource, 87 .resource = s5p6442_iis0_resource,
72 .dev = { 88 .dev = {
73 .platform_data = &s3c_i2s_pdata, 89 .platform_data = &i2sv35_pdata,
90 },
91};
92
93static const char *rclksrc_v3[] = {
94 [0] = "iis",
95 [1] = "sclk_audio",
96};
97
98static struct s3c_audio_pdata i2sv3_pdata = {
99 .cfg_gpio = s5p6442_cfg_i2s,
100 .type = {
101 .i2s = {
102 .src_clk = rclksrc_v3,
103 },
74 }, 104 },
75}; 105};
76 106
@@ -93,12 +123,12 @@ static struct resource s5p6442_iis1_resource[] = {
93}; 123};
94 124
95struct platform_device s5p6442_device_iis1 = { 125struct platform_device s5p6442_device_iis1 = {
96 .name = "s3c64xx-iis", 126 .name = "samsung-i2s",
97 .id = 1, 127 .id = 1,
98 .num_resources = ARRAY_SIZE(s5p6442_iis1_resource), 128 .num_resources = ARRAY_SIZE(s5p6442_iis1_resource),
99 .resource = s5p6442_iis1_resource, 129 .resource = s5p6442_iis1_resource,
100 .dev = { 130 .dev = {
101 .platform_data = &s3c_i2s_pdata, 131 .platform_data = &i2sv3_pdata,
102 }, 132 },
103}; 133};
104 134
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h
index 31fb2e68d527..203dd5a18bd5 100644
--- a/arch/arm/mach-s5p6442/include/mach/map.h
+++ b/arch/arm/mach-s5p6442/include/mach/map.h
@@ -28,6 +28,9 @@
28#define S5P6442_PA_VIC1 (0xE4100000) 28#define S5P6442_PA_VIC1 (0xE4100000)
29#define S5P6442_PA_VIC2 (0xE4200000) 29#define S5P6442_PA_VIC2 (0xE4200000)
30 30
31#define S5P6442_PA_SROMC (0xE7000000)
32#define S5P_PA_SROMC S5P6442_PA_SROMC
33
31#define S5P6442_PA_MDMA 0xE8000000 34#define S5P6442_PA_MDMA 0xE8000000
32#define S5P6442_PA_PDMA 0xE9000000 35#define S5P6442_PA_PDMA 0xE9000000
33 36
diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c
index 819fd80d00af..e69f137b0a39 100644
--- a/arch/arm/mach-s5p6442/mach-smdk6442.c
+++ b/arch/arm/mach-s5p6442/mach-smdk6442.c
@@ -12,6 +12,7 @@
12#include <linux/types.h> 12#include <linux/types.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/serial_core.h> 14#include <linux/serial_core.h>
15#include <linux/i2c.h>
15 16
16#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
17#include <asm/mach/map.h> 18#include <asm/mach/map.h>
@@ -25,6 +26,7 @@
25#include <plat/s5p6442.h> 26#include <plat/s5p6442.h>
26#include <plat/devs.h> 27#include <plat/devs.h>
27#include <plat/cpu.h> 28#include <plat/cpu.h>
29#include <plat/iic.h>
28 30
29/* Following are default values for UCON, ULCON and UFCON UART registers */ 31/* Following are default values for UCON, ULCON and UFCON UART registers */
30#define SMDK6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 32#define SMDK6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -65,10 +67,15 @@ static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = {
65}; 67};
66 68
67static struct platform_device *smdk6442_devices[] __initdata = { 69static struct platform_device *smdk6442_devices[] __initdata = {
70 &s3c_device_i2c0,
68 &s5p6442_device_iis0, 71 &s5p6442_device_iis0,
69 &s3c_device_wdt, 72 &s3c_device_wdt,
70}; 73};
71 74
75static struct i2c_board_info smdk6442_i2c_devs0[] __initdata = {
76 { I2C_BOARD_INFO("wm8580", 0x1b), },
77};
78
72static void __init smdk6442_map_io(void) 79static void __init smdk6442_map_io(void)
73{ 80{
74 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 81 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -78,6 +85,9 @@ static void __init smdk6442_map_io(void)
78 85
79static void __init smdk6442_machine_init(void) 86static void __init smdk6442_machine_init(void)
80{ 87{
88 s3c_i2c0_set_platdata(NULL);
89 i2c_register_board_info(0, smdk6442_i2c_devs0,
90 ARRAY_SIZE(smdk6442_i2c_devs0));
81 platform_add_devices(smdk6442_devices, ARRAY_SIZE(smdk6442_devices)); 91 platform_add_devices(smdk6442_devices, ARRAY_SIZE(smdk6442_devices));
82} 92}
83 93
diff --git a/arch/arm/mach-s5p6442/setup-i2c0.c b/arch/arm/mach-s5p6442/setup-i2c0.c
index 662695dd7761..aad85656b0cc 100644
--- a/arch/arm/mach-s5p6442/setup-i2c0.c
+++ b/arch/arm/mach-s5p6442/setup-i2c0.c
@@ -14,12 +14,15 @@
14 14
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/types.h> 16#include <linux/types.h>
17#include <linux/gpio.h>
17 18
18struct platform_device; /* don't need the contents */ 19struct platform_device; /* don't need the contents */
19 20
21#include <plat/gpio-cfg.h>
20#include <plat/iic.h> 22#include <plat/iic.h>
21 23
22void s3c_i2c0_cfg_gpio(struct platform_device *dev) 24void s3c_i2c0_cfg_gpio(struct platform_device *dev)
23{ 25{
24 /* Will be populated later */ 26 s3c_gpio_cfgall_range(S5P6442_GPD1(0), 2,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
25} 28}
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index 2655829e6bf8..ae6bf6feba89 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -12,9 +12,9 @@ obj- :=
12 12
13# Core support for S5P64X0 system 13# Core support for S5P64X0 system
14 14
15obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o 15obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o
16obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o 16obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o
17obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o gpio.o 17obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o
18obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o 18obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
19 19
20# machine support 20# machine support
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index e4883dc1c8d7..40137c6f0488 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -261,7 +261,7 @@ static struct clk init_clocks_disable[] = {
261 .enable = s5p64x0_pclk_ctrl, 261 .enable = s5p64x0_pclk_ctrl,
262 .ctrlbit = (1 << 25), 262 .ctrlbit = (1 << 25),
263 }, { 263 }, {
264 .name = "i2s_v40", 264 .name = "iis",
265 .id = 0, 265 .id = 0,
266 .parent = &clk_pclk_low.clk, 266 .parent = &clk_pclk_low.clk,
267 .enable = s5p64x0_pclk_ctrl, 267 .enable = s5p64x0_pclk_ctrl,
@@ -419,7 +419,7 @@ static struct clksrc_sources clkset_audio = {
419static struct clksrc_clk clksrcs[] = { 419static struct clksrc_clk clksrcs[] = {
420 { 420 {
421 .clk = { 421 .clk = {
422 .name = "mmc_bus", 422 .name = "sclk_mmc",
423 .id = 0, 423 .id = 0,
424 .ctrlbit = (1 << 24), 424 .ctrlbit = (1 << 24),
425 .enable = s5p64x0_sclk_ctrl, 425 .enable = s5p64x0_sclk_ctrl,
@@ -429,7 +429,7 @@ static struct clksrc_clk clksrcs[] = {
429 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 }, 429 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
430 }, { 430 }, {
431 .clk = { 431 .clk = {
432 .name = "mmc_bus", 432 .name = "sclk_mmc",
433 .id = 1, 433 .id = 1,
434 .ctrlbit = (1 << 25), 434 .ctrlbit = (1 << 25),
435 .enable = s5p64x0_sclk_ctrl, 435 .enable = s5p64x0_sclk_ctrl,
@@ -439,7 +439,7 @@ static struct clksrc_clk clksrcs[] = {
439 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 }, 439 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
440 }, { 440 }, {
441 .clk = { 441 .clk = {
442 .name = "mmc_bus", 442 .name = "sclk_mmc",
443 .id = 2, 443 .id = 2,
444 .ctrlbit = (1 << 26), 444 .ctrlbit = (1 << 26),
445 .enable = s5p64x0_sclk_ctrl, 445 .enable = s5p64x0_sclk_ctrl,
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 7dbf3c968f53..3f5ac93c455e 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -231,6 +231,12 @@ static struct clk init_clocks_disable[] = {
231 .enable = s5p64x0_pclk_ctrl, 231 .enable = s5p64x0_pclk_ctrl,
232 .ctrlbit = (1 << 5), 232 .ctrlbit = (1 << 5),
233 }, { 233 }, {
234 .name = "rtc",
235 .id = -1,
236 .parent = &clk_pclk_low.clk,
237 .enable = s5p64x0_pclk_ctrl,
238 .ctrlbit = (1 << 6),
239 }, {
234 .name = "adc", 240 .name = "adc",
235 .id = -1, 241 .id = -1,
236 .parent = &clk_pclk_low.clk, 242 .parent = &clk_pclk_low.clk,
@@ -256,11 +262,23 @@ static struct clk init_clocks_disable[] = {
256 .ctrlbit = (1 << 22), 262 .ctrlbit = (1 << 22),
257 }, { 263 }, {
258 .name = "iis", 264 .name = "iis",
259 .id = -1, 265 .id = 0,
260 .parent = &clk_pclk_low.clk, 266 .parent = &clk_pclk_low.clk,
261 .enable = s5p64x0_pclk_ctrl, 267 .enable = s5p64x0_pclk_ctrl,
262 .ctrlbit = (1 << 26), 268 .ctrlbit = (1 << 26),
263 }, { 269 }, {
270 .name = "iis",
271 .id = 1,
272 .parent = &clk_pclk_low.clk,
273 .enable = s5p64x0_pclk_ctrl,
274 .ctrlbit = (1 << 15),
275 }, {
276 .name = "iis",
277 .id = 2,
278 .parent = &clk_pclk_low.clk,
279 .enable = s5p64x0_pclk_ctrl,
280 .ctrlbit = (1 << 16),
281 }, {
264 .name = "i2c", 282 .name = "i2c",
265 .id = 1, 283 .id = 1,
266 .parent = &clk_pclk_low.clk, 284 .parent = &clk_pclk_low.clk,
diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c
index 396bacc0a39a..35f1f226dabb 100644
--- a/arch/arm/mach-s5p64x0/dev-audio.c
+++ b/arch/arm/mach-s5p64x0/dev-audio.c
@@ -19,15 +19,19 @@
19#include <mach/dma.h> 19#include <mach/dma.h>
20#include <mach/irqs.h> 20#include <mach/irqs.h>
21 21
22static const char *rclksrc[] = {
23 [0] = "iis",
24 [1] = "sclk_audio2",
25};
26
22static int s5p6440_cfg_i2s(struct platform_device *pdev) 27static int s5p6440_cfg_i2s(struct platform_device *pdev)
23{ 28{
24 /* configure GPIO for i2s port */
25 switch (pdev->id) { 29 switch (pdev->id) {
26 case -1: 30 case 0:
27 s3c_gpio_cfgpin_range(S5P6440_GPR(4), 5, S3C_GPIO_SFN(5)); 31 s3c_gpio_cfgpin_range(S5P6440_GPC(4), 2, S3C_GPIO_SFN(5));
28 s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(5)); 32 s3c_gpio_cfgpin(S5P6440_GPC(7), S3C_GPIO_SFN(5));
33 s3c_gpio_cfgpin_range(S5P6440_GPH(6), 4, S3C_GPIO_SFN(5));
29 break; 34 break;
30
31 default: 35 default:
32 printk(KERN_ERR "Invalid Device %d\n", pdev->id); 36 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
33 return -EINVAL; 37 return -EINVAL;
@@ -36,17 +40,58 @@ static int s5p6440_cfg_i2s(struct platform_device *pdev)
36 return 0; 40 return 0;
37} 41}
38 42
43static struct s3c_audio_pdata s5p6440_i2s_pdata = {
44 .cfg_gpio = s5p6440_cfg_i2s,
45 .type = {
46 .i2s = {
47 .quirks = QUIRK_PRI_6CHAN,
48 .src_clk = rclksrc,
49 },
50 },
51};
52
53static struct resource s5p64x0_i2s0_resource[] = {
54 [0] = {
55 .start = S5P64X0_PA_I2S,
56 .end = S5P64X0_PA_I2S + 0x100 - 1,
57 .flags = IORESOURCE_MEM,
58 },
59 [1] = {
60 .start = DMACH_I2S0_TX,
61 .end = DMACH_I2S0_TX,
62 .flags = IORESOURCE_DMA,
63 },
64 [2] = {
65 .start = DMACH_I2S0_RX,
66 .end = DMACH_I2S0_RX,
67 .flags = IORESOURCE_DMA,
68 },
69};
70
71struct platform_device s5p6440_device_iis = {
72 .name = "samsung-i2s",
73 .id = 0,
74 .num_resources = ARRAY_SIZE(s5p64x0_i2s0_resource),
75 .resource = s5p64x0_i2s0_resource,
76 .dev = {
77 .platform_data = &s5p6440_i2s_pdata,
78 },
79};
80
39static int s5p6450_cfg_i2s(struct platform_device *pdev) 81static int s5p6450_cfg_i2s(struct platform_device *pdev)
40{ 82{
41 /* configure GPIO for i2s port */
42 switch (pdev->id) { 83 switch (pdev->id) {
43 case -1: 84 case 0:
44 s3c_gpio_cfgpin(S5P6450_GPB(4), S3C_GPIO_SFN(5));
45 s3c_gpio_cfgpin_range(S5P6450_GPR(4), 5, S3C_GPIO_SFN(5)); 85 s3c_gpio_cfgpin_range(S5P6450_GPR(4), 5, S3C_GPIO_SFN(5));
46 s3c_gpio_cfgpin_range(S5P6450_GPR(13), 2, S3C_GPIO_SFN(5)); 86 s3c_gpio_cfgpin_range(S5P6450_GPR(13), 2, S3C_GPIO_SFN(5));
47
48 break; 87 break;
49 88 case 1:
89 s3c_gpio_cfgpin(S5P6440_GPB(4), S3C_GPIO_SFN(5));
90 s3c_gpio_cfgpin_range(S5P6450_GPC(0), 4, S3C_GPIO_SFN(5));
91 break;
92 case 2:
93 s3c_gpio_cfgpin_range(S5P6450_GPK(0), 5, S3C_GPIO_SFN(5));
94 break;
50 default: 95 default:
51 printk(KERN_ERR "Invalid Device %d\n", pdev->id); 96 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
52 return -EINVAL; 97 return -EINVAL;
@@ -55,47 +100,86 @@ static int s5p6450_cfg_i2s(struct platform_device *pdev)
55 return 0; 100 return 0;
56} 101}
57 102
58static struct s3c_audio_pdata s5p6440_i2s_pdata = { 103static struct s3c_audio_pdata s5p6450_i2s0_pdata = {
59 .cfg_gpio = s5p6440_cfg_i2s, 104 .cfg_gpio = s5p6450_cfg_i2s,
105 .type = {
106 .i2s = {
107 .quirks = QUIRK_PRI_6CHAN,
108 .src_clk = rclksrc,
109 },
110 },
111};
112
113struct platform_device s5p6450_device_iis0 = {
114 .name = "samsung-i2s",
115 .id = 0,
116 .num_resources = ARRAY_SIZE(s5p64x0_i2s0_resource),
117 .resource = s5p64x0_i2s0_resource,
118 .dev = {
119 .platform_data = &s5p6450_i2s0_pdata,
120 },
60}; 121};
61 122
62static struct s3c_audio_pdata s5p6450_i2s_pdata = { 123static struct s3c_audio_pdata s5p6450_i2s_pdata = {
63 .cfg_gpio = s5p6450_cfg_i2s, 124 .cfg_gpio = s5p6450_cfg_i2s,
125 .type = {
126 .i2s = {
127 .src_clk = rclksrc,
128 },
129 },
64}; 130};
65 131
66static struct resource s5p64x0_iis0_resource[] = { 132static struct resource s5p6450_i2s1_resource[] = {
67 [0] = { 133 [0] = {
68 .start = S5P64X0_PA_I2S, 134 .start = S5P6450_PA_I2S1,
69 .end = S5P64X0_PA_I2S + 0x100 - 1, 135 .end = S5P6450_PA_I2S1 + 0x100 - 1,
70 .flags = IORESOURCE_MEM, 136 .flags = IORESOURCE_MEM,
71 }, 137 },
72 [1] = { 138 [1] = {
73 .start = DMACH_I2S0_TX, 139 .start = DMACH_I2S1_TX,
74 .end = DMACH_I2S0_TX, 140 .end = DMACH_I2S1_TX,
75 .flags = IORESOURCE_DMA, 141 .flags = IORESOURCE_DMA,
76 }, 142 },
77 [2] = { 143 [2] = {
78 .start = DMACH_I2S0_RX, 144 .start = DMACH_I2S1_RX,
79 .end = DMACH_I2S0_RX, 145 .end = DMACH_I2S1_RX,
80 .flags = IORESOURCE_DMA, 146 .flags = IORESOURCE_DMA,
81 }, 147 },
82}; 148};
83 149
84struct platform_device s5p6440_device_iis = { 150struct platform_device s5p6450_device_iis1 = {
85 .name = "s3c64xx-iis-v4", 151 .name = "samsung-i2s",
86 .id = -1, 152 .id = 1,
87 .num_resources = ARRAY_SIZE(s5p64x0_iis0_resource), 153 .num_resources = ARRAY_SIZE(s5p6450_i2s1_resource),
88 .resource = s5p64x0_iis0_resource, 154 .resource = s5p6450_i2s1_resource,
89 .dev = { 155 .dev = {
90 .platform_data = &s5p6440_i2s_pdata, 156 .platform_data = &s5p6450_i2s_pdata,
91 }, 157 },
92}; 158};
93 159
94struct platform_device s5p6450_device_iis0 = { 160static struct resource s5p6450_i2s2_resource[] = {
95 .name = "s3c64xx-iis-v4", 161 [0] = {
96 .id = -1, 162 .start = S5P6450_PA_I2S2,
97 .num_resources = ARRAY_SIZE(s5p64x0_iis0_resource), 163 .end = S5P6450_PA_I2S2 + 0x100 - 1,
98 .resource = s5p64x0_iis0_resource, 164 .flags = IORESOURCE_MEM,
165 },
166 [1] = {
167 .start = DMACH_I2S2_TX,
168 .end = DMACH_I2S2_TX,
169 .flags = IORESOURCE_DMA,
170 },
171 [2] = {
172 .start = DMACH_I2S2_RX,
173 .end = DMACH_I2S2_RX,
174 .flags = IORESOURCE_DMA,
175 },
176};
177
178struct platform_device s5p6450_device_iis2 = {
179 .name = "samsung-i2s",
180 .id = 2,
181 .num_resources = ARRAY_SIZE(s5p6450_i2s2_resource),
182 .resource = s5p6450_i2s2_resource,
99 .dev = { 183 .dev = {
100 .platform_data = &s5p6450_i2s_pdata, 184 .platform_data = &s5p6450_i2s_pdata,
101 }, 185 },
diff --git a/arch/arm/mach-s5p64x0/gpio.c b/arch/arm/mach-s5p64x0/gpiolib.c
index 39159dd5a29a..e7fb3b004e77 100644
--- a/arch/arm/mach-s5p64x0/gpio.c
+++ b/arch/arm/mach-s5p64x0/gpiolib.c
@@ -1,4 +1,4 @@
1/* linux/arch/arm/mach-s5p64x0/gpio.c 1/* linux/arch/arm/mach-s5p64x0/gpiolib.c
2 * 2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
@@ -17,13 +17,12 @@
17 17
18#include <mach/map.h> 18#include <mach/map.h>
19#include <mach/regs-gpio.h> 19#include <mach/regs-gpio.h>
20#include <mach/regs-clock.h>
20 21
21#include <plat/gpio-core.h> 22#include <plat/gpio-core.h>
22#include <plat/gpio-cfg.h> 23#include <plat/gpio-cfg.h>
23#include <plat/gpio-cfg-helpers.h> 24#include <plat/gpio-cfg-helpers.h>
24 25
25/* To be implemented S5P6450 GPIO */
26
27/* 26/*
28 * S5P6440 GPIO bank summary: 27 * S5P6440 GPIO bank summary:
29 * 28 *
@@ -40,6 +39,25 @@
40 * P 8 2Bit Yes 8 39 * P 8 2Bit Yes 8
41 * R 15 4Bit[2] Yes 8 40 * R 15 4Bit[2] Yes 8
42 * 41 *
42 * S5P6450 GPIO bank summary:
43 *
44 * Bank GPIOs Style SlpCon ExtInt Group
45 * A 6 4Bit Yes 1
46 * B 7 4Bit Yes 1
47 * C 8 4Bit Yes 2
48 * D 8 4Bit Yes None
49 * F 2 2Bit Yes None
50 * G 14 4Bit[2] Yes 5
51 * H 10 4Bit[2] Yes 6
52 * I 16 2Bit Yes None
53 * J 12 2Bit Yes None
54 * K 5 4Bit Yes None
55 * N 16 2Bit No IRQ_EINT
56 * P 11 2Bit Yes 8
57 * Q 14 2Bit Yes None
58 * R 15 4Bit[2] Yes None
59 * S 8 2Bit Yes None
60 *
43 * [1] BANKF pins 14,15 do not form part of the external interrupt sources 61 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
44 * [2] BANK has two control registers, GPxCON0 and GPxCON1 62 * [2] BANK has two control registers, GPxCON0 and GPxCON1
45 */ 63 */
@@ -190,7 +208,7 @@ static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
190 208
191static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { 209static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
192 { 210 {
193 .base = S5P6440_GPA_BASE, 211 .base = S5P64X0_GPA_BASE,
194 .config = &s5p64x0_gpio_cfgs[1], 212 .config = &s5p64x0_gpio_cfgs[1],
195 .chip = { 213 .chip = {
196 .base = S5P6440_GPA(0), 214 .base = S5P6440_GPA(0),
@@ -198,7 +216,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
198 .label = "GPA", 216 .label = "GPA",
199 }, 217 },
200 }, { 218 }, {
201 .base = S5P6440_GPB_BASE, 219 .base = S5P64X0_GPB_BASE,
202 .config = &s5p64x0_gpio_cfgs[1], 220 .config = &s5p64x0_gpio_cfgs[1],
203 .chip = { 221 .chip = {
204 .base = S5P6440_GPB(0), 222 .base = S5P6440_GPB(0),
@@ -206,7 +224,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
206 .label = "GPB", 224 .label = "GPB",
207 }, 225 },
208 }, { 226 }, {
209 .base = S5P6440_GPC_BASE, 227 .base = S5P64X0_GPC_BASE,
210 .config = &s5p64x0_gpio_cfgs[1], 228 .config = &s5p64x0_gpio_cfgs[1],
211 .chip = { 229 .chip = {
212 .base = S5P6440_GPC(0), 230 .base = S5P6440_GPC(0),
@@ -214,7 +232,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
214 .label = "GPC", 232 .label = "GPC",
215 }, 233 },
216 }, { 234 }, {
217 .base = S5P6440_GPG_BASE, 235 .base = S5P64X0_GPG_BASE,
218 .config = &s5p64x0_gpio_cfgs[1], 236 .config = &s5p64x0_gpio_cfgs[1],
219 .chip = { 237 .chip = {
220 .base = S5P6440_GPG(0), 238 .base = S5P6440_GPG(0),
@@ -226,7 +244,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
226 244
227static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = { 245static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
228 { 246 {
229 .base = S5P6440_GPH_BASE + 0x4, 247 .base = S5P64X0_GPH_BASE + 0x4,
230 .config = &s5p64x0_gpio_cfgs[1], 248 .config = &s5p64x0_gpio_cfgs[1],
231 .chip = { 249 .chip = {
232 .base = S5P6440_GPH(0), 250 .base = S5P6440_GPH(0),
@@ -238,7 +256,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
238 256
239static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = { 257static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
240 { 258 {
241 .base = S5P6440_GPR_BASE + 0x4, 259 .base = S5P64X0_GPR_BASE + 0x4,
242 .config = &s5p64x0_gpio_cfgs[2], 260 .config = &s5p64x0_gpio_cfgs[2],
243 .chip = { 261 .chip = {
244 .base = S5P6440_GPR(0), 262 .base = S5P6440_GPR(0),
@@ -250,7 +268,7 @@ static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
250 268
251static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { 269static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
252 { 270 {
253 .base = S5P6440_GPF_BASE, 271 .base = S5P64X0_GPF_BASE,
254 .config = &s5p64x0_gpio_cfgs[5], 272 .config = &s5p64x0_gpio_cfgs[5],
255 .chip = { 273 .chip = {
256 .base = S5P6440_GPF(0), 274 .base = S5P6440_GPF(0),
@@ -258,7 +276,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
258 .label = "GPF", 276 .label = "GPF",
259 }, 277 },
260 }, { 278 }, {
261 .base = S5P6440_GPI_BASE, 279 .base = S5P64X0_GPI_BASE,
262 .config = &s5p64x0_gpio_cfgs[3], 280 .config = &s5p64x0_gpio_cfgs[3],
263 .chip = { 281 .chip = {
264 .base = S5P6440_GPI(0), 282 .base = S5P6440_GPI(0),
@@ -266,7 +284,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
266 .label = "GPI", 284 .label = "GPI",
267 }, 285 },
268 }, { 286 }, {
269 .base = S5P6440_GPJ_BASE, 287 .base = S5P64X0_GPJ_BASE,
270 .config = &s5p64x0_gpio_cfgs[3], 288 .config = &s5p64x0_gpio_cfgs[3],
271 .chip = { 289 .chip = {
272 .base = S5P6440_GPJ(0), 290 .base = S5P6440_GPJ(0),
@@ -274,7 +292,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
274 .label = "GPJ", 292 .label = "GPJ",
275 }, 293 },
276 }, { 294 }, {
277 .base = S5P6440_GPN_BASE, 295 .base = S5P64X0_GPN_BASE,
278 .config = &s5p64x0_gpio_cfgs[4], 296 .config = &s5p64x0_gpio_cfgs[4],
279 .chip = { 297 .chip = {
280 .base = S5P6440_GPN(0), 298 .base = S5P6440_GPN(0),
@@ -282,7 +300,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
282 .label = "GPN", 300 .label = "GPN",
283 }, 301 },
284 }, { 302 }, {
285 .base = S5P6440_GPP_BASE, 303 .base = S5P64X0_GPP_BASE,
286 .config = &s5p64x0_gpio_cfgs[5], 304 .config = &s5p64x0_gpio_cfgs[5],
287 .chip = { 305 .chip = {
288 .base = S5P6440_GPP(0), 306 .base = S5P6440_GPP(0),
@@ -292,6 +310,142 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
292 }, 310 },
293}; 311};
294 312
313static struct s3c_gpio_chip s5p6450_gpio_4bit[] = {
314 {
315 .base = S5P64X0_GPA_BASE,
316 .config = &s5p64x0_gpio_cfgs[1],
317 .chip = {
318 .base = S5P6450_GPA(0),
319 .ngpio = S5P6450_GPIO_A_NR,
320 .label = "GPA",
321 },
322 }, {
323 .base = S5P64X0_GPB_BASE,
324 .config = &s5p64x0_gpio_cfgs[1],
325 .chip = {
326 .base = S5P6450_GPB(0),
327 .ngpio = S5P6450_GPIO_B_NR,
328 .label = "GPB",
329 },
330 }, {
331 .base = S5P64X0_GPC_BASE,
332 .config = &s5p64x0_gpio_cfgs[1],
333 .chip = {
334 .base = S5P6450_GPC(0),
335 .ngpio = S5P6450_GPIO_C_NR,
336 .label = "GPC",
337 },
338 }, {
339 .base = S5P6450_GPD_BASE,
340 .config = &s5p64x0_gpio_cfgs[1],
341 .chip = {
342 .base = S5P6450_GPD(0),
343 .ngpio = S5P6450_GPIO_D_NR,
344 .label = "GPD",
345 },
346 }, {
347 .base = S5P6450_GPK_BASE,
348 .config = &s5p64x0_gpio_cfgs[1],
349 .chip = {
350 .base = S5P6450_GPK(0),
351 .ngpio = S5P6450_GPIO_K_NR,
352 .label = "GPK",
353 },
354 },
355};
356
357static struct s3c_gpio_chip s5p6450_gpio_4bit2[] = {
358 {
359 .base = S5P64X0_GPG_BASE + 0x4,
360 .config = &s5p64x0_gpio_cfgs[1],
361 .chip = {
362 .base = S5P6450_GPG(0),
363 .ngpio = S5P6450_GPIO_G_NR,
364 .label = "GPG",
365 },
366 }, {
367 .base = S5P64X0_GPH_BASE + 0x4,
368 .config = &s5p64x0_gpio_cfgs[1],
369 .chip = {
370 .base = S5P6450_GPH(0),
371 .ngpio = S5P6450_GPIO_H_NR,
372 .label = "GPH",
373 },
374 },
375};
376
377static struct s3c_gpio_chip s5p6450_gpio_rbank_4bit2[] = {
378 {
379 .base = S5P64X0_GPR_BASE + 0x4,
380 .config = &s5p64x0_gpio_cfgs[2],
381 .chip = {
382 .base = S5P6450_GPR(0),
383 .ngpio = S5P6450_GPIO_R_NR,
384 .label = "GPR",
385 },
386 },
387};
388
389static struct s3c_gpio_chip s5p6450_gpio_2bit[] = {
390 {
391 .base = S5P64X0_GPF_BASE,
392 .config = &s5p64x0_gpio_cfgs[5],
393 .chip = {
394 .base = S5P6450_GPF(0),
395 .ngpio = S5P6450_GPIO_F_NR,
396 .label = "GPF",
397 },
398 }, {
399 .base = S5P64X0_GPI_BASE,
400 .config = &s5p64x0_gpio_cfgs[3],
401 .chip = {
402 .base = S5P6450_GPI(0),
403 .ngpio = S5P6450_GPIO_I_NR,
404 .label = "GPI",
405 },
406 }, {
407 .base = S5P64X0_GPJ_BASE,
408 .config = &s5p64x0_gpio_cfgs[3],
409 .chip = {
410 .base = S5P6450_GPJ(0),
411 .ngpio = S5P6450_GPIO_J_NR,
412 .label = "GPJ",
413 },
414 }, {
415 .base = S5P64X0_GPN_BASE,
416 .config = &s5p64x0_gpio_cfgs[4],
417 .chip = {
418 .base = S5P6450_GPN(0),
419 .ngpio = S5P6450_GPIO_N_NR,
420 .label = "GPN",
421 },
422 }, {
423 .base = S5P64X0_GPP_BASE,
424 .config = &s5p64x0_gpio_cfgs[5],
425 .chip = {
426 .base = S5P6450_GPP(0),
427 .ngpio = S5P6450_GPIO_P_NR,
428 .label = "GPP",
429 },
430 }, {
431 .base = S5P6450_GPQ_BASE,
432 .config = &s5p64x0_gpio_cfgs[4],
433 .chip = {
434 .base = S5P6450_GPQ(0),
435 .ngpio = S5P6450_GPIO_Q_NR,
436 .label = "GPQ",
437 },
438 }, {
439 .base = S5P6450_GPS_BASE,
440 .config = &s5p64x0_gpio_cfgs[5],
441 .chip = {
442 .base = S5P6450_GPS(0),
443 .ngpio = S5P6450_GPIO_S_NR,
444 .label = "GPS",
445 },
446 },
447};
448
295void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips) 449void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
296{ 450{
297 for (; nr_chips > 0; nr_chips--, chipcfg++) { 451 for (; nr_chips > 0; nr_chips--, chipcfg++) {
@@ -317,26 +471,41 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
317 } 471 }
318} 472}
319 473
320static int __init s5p6440_gpiolib_init(void) 474static int __init s5p64x0_gpiolib_init(void)
321{ 475{
322 struct s3c_gpio_chip *chips = s5p6440_gpio_2bit; 476 unsigned int chipid;
323 int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit); 477
478 chipid = __raw_readl(S5P64X0_SYS_ID);
324 479
325 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs, 480 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
326 ARRAY_SIZE(s5p64x0_gpio_cfgs)); 481 ARRAY_SIZE(s5p64x0_gpio_cfgs));
327 482
328 for (; nr_chips > 0; nr_chips--, chips++) 483 if ((chipid & 0xff000) == 0x50000) {
329 s3c_gpiolib_add(chips); 484 samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
485 ARRAY_SIZE(s5p6450_gpio_2bit));
486
487 samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit,
488 ARRAY_SIZE(s5p6450_gpio_4bit));
330 489
331 samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit, 490 samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2,
332 ARRAY_SIZE(s5p6440_gpio_4bit)); 491 ARRAY_SIZE(s5p6450_gpio_4bit2));
333 492
334 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2, 493 s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2,
335 ARRAY_SIZE(s5p6440_gpio_4bit2)); 494 ARRAY_SIZE(s5p6450_gpio_rbank_4bit2));
495 } else {
496 samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit,
497 ARRAY_SIZE(s5p6440_gpio_2bit));
336 498
337 s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2, 499 samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
338 ARRAY_SIZE(s5p6440_gpio_rbank_4bit2)); 500 ARRAY_SIZE(s5p6440_gpio_4bit));
501
502 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
503 ARRAY_SIZE(s5p6440_gpio_4bit2));
504
505 s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
506 ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
507 }
339 508
340 return 0; 509 return 0;
341} 510}
342arch_initcall(s5p6440_gpiolib_init); 511core_initcall(s5p64x0_gpiolib_init);
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index 31e534156e06..a9365e5ba614 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -29,6 +29,9 @@
29#define S5P64X0_PA_VIC0 (0xE4000000) 29#define S5P64X0_PA_VIC0 (0xE4000000)
30#define S5P64X0_PA_VIC1 (0xE4100000) 30#define S5P64X0_PA_VIC1 (0xE4100000)
31 31
32#define S5P64X0_PA_SROMC (0xE7000000)
33#define S5P_PA_SROMC S5P64X0_PA_SROMC
34
32#define S5P64X0_PA_PDMA (0xE9000000) 35#define S5P64X0_PA_PDMA (0xE9000000)
33 36
34#define S5P64X0_PA_TIMER (0xEA000000) 37#define S5P64X0_PA_TIMER (0xEA000000)
@@ -63,6 +66,8 @@
63#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) 66#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
64 67
65#define S5P64X0_PA_I2S (0xF2000000) 68#define S5P64X0_PA_I2S (0xF2000000)
69#define S5P6450_PA_I2S1 0xF2800000
70#define S5P6450_PA_I2S2 0xF2900000
66 71
67#define S5P64X0_PA_PCM (0xF2100000) 72#define S5P64X0_PA_PCM (0xF2100000)
68 73
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 85f448e20a8b..0953ef6b1c77 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -15,48 +15,23 @@
15 15
16#include <mach/map.h> 16#include <mach/map.h>
17 17
18/* Will be implemented S5P6442 GPIOlib */
19
20/* Base addresses for each of the banks */ 18/* Base addresses for each of the banks */
21 19
22#define S5P6440_GPA_BASE (S5P_VA_GPIO + 0x0000) 20#define S5P64X0_GPA_BASE (S5P_VA_GPIO + 0x0000)
23#define S5P6440_GPB_BASE (S5P_VA_GPIO + 0x0020) 21#define S5P64X0_GPB_BASE (S5P_VA_GPIO + 0x0020)
24#define S5P6440_GPC_BASE (S5P_VA_GPIO + 0x0040) 22#define S5P64X0_GPC_BASE (S5P_VA_GPIO + 0x0040)
25#define S5P6440_GPF_BASE (S5P_VA_GPIO + 0x00A0) 23#define S5P64X0_GPF_BASE (S5P_VA_GPIO + 0x00A0)
26#define S5P6440_GPG_BASE (S5P_VA_GPIO + 0x00C0) 24#define S5P64X0_GPG_BASE (S5P_VA_GPIO + 0x00C0)
27#define S5P6440_GPH_BASE (S5P_VA_GPIO + 0x00E0) 25#define S5P64X0_GPH_BASE (S5P_VA_GPIO + 0x00E0)
28#define S5P6440_GPI_BASE (S5P_VA_GPIO + 0x0100) 26#define S5P64X0_GPI_BASE (S5P_VA_GPIO + 0x0100)
29#define S5P6440_GPJ_BASE (S5P_VA_GPIO + 0x0120) 27#define S5P64X0_GPJ_BASE (S5P_VA_GPIO + 0x0120)
30#define S5P6440_GPN_BASE (S5P_VA_GPIO + 0x0830) 28#define S5P64X0_GPN_BASE (S5P_VA_GPIO + 0x0830)
31#define S5P6440_GPP_BASE (S5P_VA_GPIO + 0x0160) 29#define S5P64X0_GPP_BASE (S5P_VA_GPIO + 0x0160)
32#define S5P6440_GPR_BASE (S5P_VA_GPIO + 0x0290) 30#define S5P64X0_GPR_BASE (S5P_VA_GPIO + 0x0290)
33 31
34#define S5P6440_EINT0CON0 (S5P_VA_GPIO + 0x900) 32#define S5P6450_GPD_BASE (S5P_VA_GPIO + 0x0060)
35#define S5P6440_EINT0FLTCON0 (S5P_VA_GPIO + 0x910) 33#define S5P6450_GPK_BASE (S5P_VA_GPIO + 0x0140)
36#define S5P6440_EINT0FLTCON1 (S5P_VA_GPIO + 0x914) 34#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
37#define S5P6440_EINT0MASK (S5P_VA_GPIO + 0x920) 35#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
38#define S5P6440_EINT0PEND (S5P_VA_GPIO + 0x924)
39
40/* for LCD */
41
42#define S5P6440_SPCON_LCD_SEL_RGB (1 << 0)
43#define S5P6440_SPCON_LCD_SEL_MASK (3 << 0)
44
45/*
46 * These set of macros are not really useful for the
47 * GPF/GPI/GPJ/GPN/GPP, useful for others set of GPIO's (4 bit)
48 */
49
50#define S5P6440_GPIO_CONMASK(__gpio) (0xf << ((__gpio) * 4))
51#define S5P6440_GPIO_INPUT(__gpio) (0x0 << ((__gpio) * 4))
52#define S5P6440_GPIO_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
53
54/*
55 * Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit)
56 */
57
58#define S5P6440_GPIO2_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
59#define S5P6440_GPIO2_INPUT(__gpio) (0x0 << ((__gpio) * 2))
60#define S5P6440_GPIO2_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
61 36
62#endif /* __ASM_ARCH_REGS_GPIO_H */ 37#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 87c3f03c618c..e9802755daeb 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -117,6 +117,7 @@ static struct s3c2410_platform_i2c s5p6440_i2c1_data __initdata = {
117 117
118static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = { 118static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = {
119 { I2C_BOARD_INFO("24c08", 0x50), }, 119 { I2C_BOARD_INFO("24c08", 0x50), },
120 { I2C_BOARD_INFO("wm8580", 0x1b), },
120}; 121};
121 122
122static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = { 123static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = {
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index d609f5af2b98..b78f56292780 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -135,6 +135,7 @@ static struct s3c2410_platform_i2c s5p6450_i2c1_data __initdata = {
135}; 135};
136 136
137static struct i2c_board_info smdk6450_i2c_devs0[] __initdata = { 137static struct i2c_board_info smdk6450_i2c_devs0[] __initdata = {
138 { I2C_BOARD_INFO("wm8580", 0x1b), },
138 { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung KS24C080C EEPROM */ 139 { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung KS24C080C EEPROM */
139}; 140};
140 141
diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c
index 564e195ec493..10ab275ebd63 100644
--- a/arch/arm/mach-s5pc100/dev-audio.c
+++ b/arch/arm/mach-s5pc100/dev-audio.c
@@ -23,17 +23,14 @@ static int s5pc100_cfg_i2s(struct platform_device *pdev)
23{ 23{
24 /* configure GPIO for i2s port */ 24 /* configure GPIO for i2s port */
25 switch (pdev->id) { 25 switch (pdev->id) {
26 case 0: /* Dedicated pins */
27 break;
26 case 1: 28 case 1:
27 s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(2)); 29 s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(2));
28 break; 30 break;
29
30 case 2: 31 case 2:
31 s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(4)); 32 s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(4));
32 break; 33 break;
33
34 case -1: /* Dedicated pins */
35 break;
36
37 default: 34 default:
38 printk(KERN_ERR "Invalid Device %d\n", pdev->id); 35 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
39 return -EINVAL; 36 return -EINVAL;
@@ -42,8 +39,20 @@ static int s5pc100_cfg_i2s(struct platform_device *pdev)
42 return 0; 39 return 0;
43} 40}
44 41
45static struct s3c_audio_pdata s3c_i2s_pdata = { 42static const char *rclksrc_v5[] = {
43 [0] = "iis",
44 [1] = "i2sclkd2",
45};
46
47static struct s3c_audio_pdata i2sv5_pdata = {
46 .cfg_gpio = s5pc100_cfg_i2s, 48 .cfg_gpio = s5pc100_cfg_i2s,
49 .type = {
50 .i2s = {
51 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
52 | QUIRK_NEED_RSTCLR,
53 .src_clk = rclksrc_v5,
54 },
55 },
47}; 56};
48 57
49static struct resource s5pc100_iis0_resource[] = { 58static struct resource s5pc100_iis0_resource[] = {
@@ -62,15 +71,34 @@ static struct resource s5pc100_iis0_resource[] = {
62 .end = DMACH_I2S0_RX, 71 .end = DMACH_I2S0_RX,
63 .flags = IORESOURCE_DMA, 72 .flags = IORESOURCE_DMA,
64 }, 73 },
74 [3] = {
75 .start = DMACH_I2S0S_TX,
76 .end = DMACH_I2S0S_TX,
77 .flags = IORESOURCE_DMA,
78 },
65}; 79};
66 80
67struct platform_device s5pc100_device_iis0 = { 81struct platform_device s5pc100_device_iis0 = {
68 .name = "s3c64xx-iis-v4", 82 .name = "samsung-i2s",
69 .id = -1, 83 .id = 0,
70 .num_resources = ARRAY_SIZE(s5pc100_iis0_resource), 84 .num_resources = ARRAY_SIZE(s5pc100_iis0_resource),
71 .resource = s5pc100_iis0_resource, 85 .resource = s5pc100_iis0_resource,
72 .dev = { 86 .dev = {
73 .platform_data = &s3c_i2s_pdata, 87 .platform_data = &i2sv5_pdata,
88 },
89};
90
91static const char *rclksrc_v3[] = {
92 [0] = "iis",
93 [1] = "sclk_audio",
94};
95
96static struct s3c_audio_pdata i2sv3_pdata = {
97 .cfg_gpio = s5pc100_cfg_i2s,
98 .type = {
99 .i2s = {
100 .src_clk = rclksrc_v3,
101 },
74 }, 102 },
75}; 103};
76 104
@@ -93,12 +121,12 @@ static struct resource s5pc100_iis1_resource[] = {
93}; 121};
94 122
95struct platform_device s5pc100_device_iis1 = { 123struct platform_device s5pc100_device_iis1 = {
96 .name = "s3c64xx-iis", 124 .name = "samsung-i2s",
97 .id = 1, 125 .id = 1,
98 .num_resources = ARRAY_SIZE(s5pc100_iis1_resource), 126 .num_resources = ARRAY_SIZE(s5pc100_iis1_resource),
99 .resource = s5pc100_iis1_resource, 127 .resource = s5pc100_iis1_resource,
100 .dev = { 128 .dev = {
101 .platform_data = &s3c_i2s_pdata, 129 .platform_data = &i2sv3_pdata,
102 }, 130 },
103}; 131};
104 132
@@ -121,12 +149,12 @@ static struct resource s5pc100_iis2_resource[] = {
121}; 149};
122 150
123struct platform_device s5pc100_device_iis2 = { 151struct platform_device s5pc100_device_iis2 = {
124 .name = "s3c64xx-iis", 152 .name = "samsung-i2s",
125 .id = 2, 153 .id = 2,
126 .num_resources = ARRAY_SIZE(s5pc100_iis2_resource), 154 .num_resources = ARRAY_SIZE(s5pc100_iis2_resource),
127 .resource = s5pc100_iis2_resource, 155 .resource = s5pc100_iis2_resource,
128 .dev = { 156 .dev = {
129 .platform_data = &s3c_i2s_pdata, 157 .platform_data = &i2sv3_pdata,
130 }, 158 },
131}; 159};
132 160
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 32e9cab5c864..328467b346aa 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -55,6 +55,8 @@
55#define S5PC100_VA_VIC_OFFSET 0x10000 55#define S5PC100_VA_VIC_OFFSET 0x10000
56#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) 56#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
57 57
58#define S5PC100_PA_SROMC (0xE7000000)
59#define S5P_PA_SROMC S5PC100_PA_SROMC
58 60
59#define S5PC100_PA_ONENAND (0xE7100000) 61#define S5PC100_PA_ONENAND (0xE7100000)
60 62
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 862f239a0fdb..53aabef1e9ce 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -118,6 +118,7 @@ menu "S5PV210 Machines"
118config MACH_SMDKV210 118config MACH_SMDKV210
119 bool "SMDKV210" 119 bool "SMDKV210"
120 select CPU_S5PV210 120 select CPU_S5PV210
121 select S3C_DEV_FB
121 select S3C_DEV_HSMMC 122 select S3C_DEV_HSMMC
122 select S3C_DEV_HSMMC1 123 select S3C_DEV_HSMMC1
123 select S3C_DEV_HSMMC2 124 select S3C_DEV_HSMMC2
@@ -130,6 +131,7 @@ config MACH_SMDKV210
130 select SAMSUNG_DEV_IDE 131 select SAMSUNG_DEV_IDE
131 select SAMSUNG_DEV_KEYPAD 132 select SAMSUNG_DEV_KEYPAD
132 select SAMSUNG_DEV_TS 133 select SAMSUNG_DEV_TS
134 select S5PV210_SETUP_FB_24BPP
133 select S5PV210_SETUP_I2C1 135 select S5PV210_SETUP_I2C1
134 select S5PV210_SETUP_I2C2 136 select S5PV210_SETUP_I2C2
135 select S5PV210_SETUP_IDE 137 select S5PV210_SETUP_IDE
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 019c3a69b0e4..dab6ef3b6ca9 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -467,20 +467,20 @@ static struct clk init_clocks_disable[] = {
467 .enable = s5pv210_clk_ip3_ctrl, 467 .enable = s5pv210_clk_ip3_ctrl,
468 .ctrlbit = (1<<21), 468 .ctrlbit = (1<<21),
469 }, { 469 }, {
470 .name = "i2s_v50", 470 .name = "iis",
471 .id = 0, 471 .id = 0,
472 .parent = &clk_p, 472 .parent = &clk_p,
473 .enable = s5pv210_clk_ip3_ctrl, 473 .enable = s5pv210_clk_ip3_ctrl,
474 .ctrlbit = (1<<4), 474 .ctrlbit = (1<<4),
475 }, { 475 }, {
476 .name = "i2s_v32", 476 .name = "iis",
477 .id = 0, 477 .id = 1,
478 .parent = &clk_p, 478 .parent = &clk_p,
479 .enable = s5pv210_clk_ip3_ctrl, 479 .enable = s5pv210_clk_ip3_ctrl,
480 .ctrlbit = (1 << 5), 480 .ctrlbit = (1 << 5),
481 }, { 481 }, {
482 .name = "i2s_v32", 482 .name = "iis",
483 .id = 1, 483 .id = 2,
484 .parent = &clk_p, 484 .parent = &clk_p,
485 .enable = s5pv210_clk_ip3_ctrl, 485 .enable = s5pv210_clk_ip3_ctrl,
486 .ctrlbit = (1 << 6), 486 .ctrlbit = (1 << 6),
@@ -525,6 +525,12 @@ static struct clk init_clocks[] = {
525 .parent = &clk_pclk_psys.clk, 525 .parent = &clk_pclk_psys.clk,
526 .enable = s5pv210_clk_ip3_ctrl, 526 .enable = s5pv210_clk_ip3_ctrl,
527 .ctrlbit = (1 << 20), 527 .ctrlbit = (1 << 20),
528 }, {
529 .name = "sromc",
530 .id = -1,
531 .parent = &clk_hclk_psys.clk,
532 .enable = s5pv210_clk_ip1_ctrl,
533 .ctrlbit = (1 << 26),
528 }, 534 },
529}; 535};
530 536
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 8eb480e201b0..61e6c24b90ac 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -81,11 +81,6 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
81 .length = SZ_512K, 81 .length = SZ_512K,
82 .type = MT_DEVICE, 82 .type = MT_DEVICE,
83 }, { 83 }, {
84 .virtual = (unsigned long)S5P_VA_SROMC,
85 .pfn = __phys_to_pfn(S5PV210_PA_SROMC),
86 .length = SZ_4K,
87 .type = MT_DEVICE,
88 }, {
89 .virtual = (unsigned long)S5P_VA_DMC0, 84 .virtual = (unsigned long)S5P_VA_DMC0,
90 .pfn = __phys_to_pfn(S5PV210_PA_DMC0), 85 .pfn = __phys_to_pfn(S5PV210_PA_DMC0),
91 .length = SZ_4K, 86 .length = SZ_4K,
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c
index 1303fcb12b51..ddd2704b3467 100644
--- a/arch/arm/mach-s5pv210/dev-audio.c
+++ b/arch/arm/mach-s5pv210/dev-audio.c
@@ -19,22 +19,24 @@
19#include <mach/dma.h> 19#include <mach/dma.h>
20#include <mach/irqs.h> 20#include <mach/irqs.h>
21 21
22static const char *rclksrc[] = {
23 [0] = "busclk",
24 [1] = "i2sclk",
25};
26
22static int s5pv210_cfg_i2s(struct platform_device *pdev) 27static int s5pv210_cfg_i2s(struct platform_device *pdev)
23{ 28{
24 /* configure GPIO for i2s port */ 29 /* configure GPIO for i2s port */
25 switch (pdev->id) { 30 switch (pdev->id) {
31 case 0:
32 s3c_gpio_cfgpin_range(S5PV210_GPI(0), 7, S3C_GPIO_SFN(2));
33 break;
26 case 1: 34 case 1:
27 s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(2)); 35 s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(2));
28 break; 36 break;
29
30 case 2: 37 case 2:
31 s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(4)); 38 s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(4));
32 break; 39 break;
33
34 case -1:
35 s3c_gpio_cfgpin_range(S5PV210_GPI(0), 7, S3C_GPIO_SFN(2));
36 break;
37
38 default: 40 default:
39 printk(KERN_ERR "Invalid Device %d\n", pdev->id); 41 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
40 return -EINVAL; 42 return -EINVAL;
@@ -43,8 +45,15 @@ static int s5pv210_cfg_i2s(struct platform_device *pdev)
43 return 0; 45 return 0;
44} 46}
45 47
46static struct s3c_audio_pdata s3c_i2s_pdata = { 48static struct s3c_audio_pdata i2sv5_pdata = {
47 .cfg_gpio = s5pv210_cfg_i2s, 49 .cfg_gpio = s5pv210_cfg_i2s,
50 .type = {
51 .i2s = {
52 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
53 | QUIRK_NEED_RSTCLR,
54 .src_clk = rclksrc,
55 },
56 },
48}; 57};
49 58
50static struct resource s5pv210_iis0_resource[] = { 59static struct resource s5pv210_iis0_resource[] = {
@@ -63,15 +72,34 @@ static struct resource s5pv210_iis0_resource[] = {
63 .end = DMACH_I2S0_RX, 72 .end = DMACH_I2S0_RX,
64 .flags = IORESOURCE_DMA, 73 .flags = IORESOURCE_DMA,
65 }, 74 },
75 [3] = {
76 .start = DMACH_I2S0S_TX,
77 .end = DMACH_I2S0S_TX,
78 .flags = IORESOURCE_DMA,
79 },
66}; 80};
67 81
68struct platform_device s5pv210_device_iis0 = { 82struct platform_device s5pv210_device_iis0 = {
69 .name = "s3c64xx-iis-v4", 83 .name = "samsung-i2s",
70 .id = -1, 84 .id = 0,
71 .num_resources = ARRAY_SIZE(s5pv210_iis0_resource), 85 .num_resources = ARRAY_SIZE(s5pv210_iis0_resource),
72 .resource = s5pv210_iis0_resource, 86 .resource = s5pv210_iis0_resource,
73 .dev = { 87 .dev = {
74 .platform_data = &s3c_i2s_pdata, 88 .platform_data = &i2sv5_pdata,
89 },
90};
91
92static const char *rclksrc_v3[] = {
93 [0] = "iis",
94 [1] = "audio-bus",
95};
96
97static struct s3c_audio_pdata i2sv3_pdata = {
98 .cfg_gpio = s5pv210_cfg_i2s,
99 .type = {
100 .i2s = {
101 .src_clk = rclksrc_v3,
102 },
75 }, 103 },
76}; 104};
77 105
@@ -94,12 +122,12 @@ static struct resource s5pv210_iis1_resource[] = {
94}; 122};
95 123
96struct platform_device s5pv210_device_iis1 = { 124struct platform_device s5pv210_device_iis1 = {
97 .name = "s3c64xx-iis", 125 .name = "samsung-i2s",
98 .id = 1, 126 .id = 1,
99 .num_resources = ARRAY_SIZE(s5pv210_iis1_resource), 127 .num_resources = ARRAY_SIZE(s5pv210_iis1_resource),
100 .resource = s5pv210_iis1_resource, 128 .resource = s5pv210_iis1_resource,
101 .dev = { 129 .dev = {
102 .platform_data = &s3c_i2s_pdata, 130 .platform_data = &i2sv3_pdata,
103 }, 131 },
104}; 132};
105 133
@@ -122,12 +150,12 @@ static struct resource s5pv210_iis2_resource[] = {
122}; 150};
123 151
124struct platform_device s5pv210_device_iis2 = { 152struct platform_device s5pv210_device_iis2 = {
125 .name = "s3c64xx-iis", 153 .name = "samsung-i2s",
126 .id = 2, 154 .id = 2,
127 .num_resources = ARRAY_SIZE(s5pv210_iis2_resource), 155 .num_resources = ARRAY_SIZE(s5pv210_iis2_resource),
128 .resource = s5pv210_iis2_resource, 156 .resource = s5pv210_iis2_resource,
129 .dev = { 157 .dev = {
130 .platform_data = &s3c_i2s_pdata, 158 .platform_data = &i2sv3_pdata,
131 }, 159 },
132}; 160};
133 161
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index 119b95fdc3ce..26710b35ef87 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -65,7 +65,7 @@
65#define IRQ_HSMMC0 S5P_IRQ_VIC1(26) 65#define IRQ_HSMMC0 S5P_IRQ_VIC1(26)
66#define IRQ_HSMMC1 S5P_IRQ_VIC1(27) 66#define IRQ_HSMMC1 S5P_IRQ_VIC1(27)
67#define IRQ_HSMMC2 S5P_IRQ_VIC1(28) 67#define IRQ_HSMMC2 S5P_IRQ_VIC1(28)
68#define IRQ_MIPICSI S5P_IRQ_VIC1(29) 68#define IRQ_MIPI_CSIS S5P_IRQ_VIC1(29)
69#define IRQ_MIPIDSI S5P_IRQ_VIC1(30) 69#define IRQ_MIPIDSI S5P_IRQ_VIC1(30)
70#define IRQ_ONENAND_AUDI S5P_IRQ_VIC1(31) 70#define IRQ_ONENAND_AUDI S5P_IRQ_VIC1(31)
71 71
@@ -132,5 +132,6 @@
132#define IRQ_LCD_FIFO IRQ_LCD0 132#define IRQ_LCD_FIFO IRQ_LCD0
133#define IRQ_LCD_VSYNC IRQ_LCD1 133#define IRQ_LCD_VSYNC IRQ_LCD1
134#define IRQ_LCD_SYSTEM IRQ_LCD2 134#define IRQ_LCD_SYSTEM IRQ_LCD2
135#define IRQ_MIPI_CSIS0 IRQ_MIPI_CSIS
135 136
136#endif /* ASM_ARCH_IRQS_H */ 137#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 861d7fe11fc9..3611492ad681 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -16,6 +16,8 @@
16#include <plat/map-base.h> 16#include <plat/map-base.h>
17#include <plat/map-s5p.h> 17#include <plat/map-s5p.h>
18 18
19#define S5PV210_PA_SROM_BANK5 (0xA8000000)
20
19#define S5PC110_PA_ONENAND (0xB0000000) 21#define S5PC110_PA_ONENAND (0xB0000000)
20#define S5P_PA_ONENAND S5PC110_PA_ONENAND 22#define S5P_PA_ONENAND S5PC110_PA_ONENAND
21 23
@@ -60,6 +62,7 @@
60#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 62#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
61 63
62#define S5PV210_PA_SROMC (0xE8000000) 64#define S5PV210_PA_SROMC (0xE8000000)
65#define S5P_PA_SROMC S5PV210_PA_SROMC
63 66
64#define S5PV210_PA_CFCON (0xE8200000) 67#define S5PV210_PA_CFCON (0xE8200000)
65 68
@@ -107,6 +110,8 @@
107#define S5PV210_PA_DMC0 (0xF0000000) 110#define S5PV210_PA_DMC0 (0xF0000000)
108#define S5PV210_PA_DMC1 (0xF1400000) 111#define S5PV210_PA_DMC1 (0xF1400000)
109 112
113#define S5PV210_PA_MIPI_CSIS 0xFA600000
114
110/* compatibiltiy defines. */ 115/* compatibiltiy defines. */
111#define S3C_PA_UART S5PV210_PA_UART 116#define S3C_PA_UART S5PV210_PA_UART
112#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0) 117#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
@@ -123,6 +128,7 @@
123#define S5P_PA_FIMC0 S5PV210_PA_FIMC0 128#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
124#define S5P_PA_FIMC1 S5PV210_PA_FIMC1 129#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
125#define S5P_PA_FIMC2 S5PV210_PA_FIMC2 130#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
131#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
126 132
127#define SAMSUNG_PA_ADC S5PV210_PA_ADC 133#define SAMSUNG_PA_ADC S5PV210_PA_ADC
128#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON 134#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index ebaabe021af9..4c45b74def5f 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -161,7 +161,7 @@
161#define S5P_MDNIE_SEL S5P_CLKREG(0x7008) 161#define S5P_MDNIE_SEL S5P_CLKREG(0x7008)
162#define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) 162#define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200)
163#define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) 163#define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204)
164#define S5P_MIPI_CONTROL S5P_CLKREG(0xE814) 164#define S5P_MIPI_DPHY_CONTROL S5P_CLKREG(0xE814)
165 165
166#define S5P_IDLE_CFG_TL_MASK (3 << 30) 166#define S5P_IDLE_CFG_TL_MASK (3 << 30)
167#define S5P_IDLE_CFG_TM_MASK (3 << 28) 167#define S5P_IDLE_CFG_TM_MASK (3 << 28)
@@ -195,9 +195,6 @@
195#define S5P_OTHERS_RET_UART (1 << 28) 195#define S5P_OTHERS_RET_UART (1 << 28)
196#define S5P_OTHERS_USB_SIG_MASK (1 << 16) 196#define S5P_OTHERS_USB_SIG_MASK (1 << 16)
197 197
198/* MIPI */
199#define S5P_MIPI_DPHY_EN (3)
200
201/* S5P_DAC_CONTROL */ 198/* S5P_DAC_CONTROL */
202#define S5P_DAC_ENABLE (1) 199#define S5P_DAC_ENABLE (1)
203#define S5P_DAC_DISABLE (0) 200#define S5P_DAC_DISABLE (0)
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 5dd1681c069e..bb20a14da100 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -94,6 +94,7 @@ static struct platform_device *smdkc110_devices[] __initdata = {
94 94
95static struct i2c_board_info smdkc110_i2c_devs0[] __initdata = { 95static struct i2c_board_info smdkc110_i2c_devs0[] __initdata = {
96 { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */ 96 { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */
97 { I2C_BOARD_INFO("wm8580", 0x1b), },
97}; 98};
98 99
99static struct i2c_board_info smdkc110_i2c_devs1[] __initdata = { 100static struct i2c_board_info smdkc110_i2c_devs1[] __initdata = {
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 1fbc45b2a432..88e45223c8af 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -14,16 +14,25 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/serial_core.h> 15#include <linux/serial_core.h>
16#include <linux/sysdev.h> 16#include <linux/sysdev.h>
17#include <linux/dm9000.h>
18#include <linux/fb.h>
19#include <linux/gpio.h>
20#include <linux/delay.h>
17 21
18#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
19#include <asm/mach/map.h> 23#include <asm/mach/map.h>
20#include <asm/setup.h> 24#include <asm/setup.h>
21#include <asm/mach-types.h> 25#include <asm/mach-types.h>
22 26
27#include <video/platform_lcd.h>
28
23#include <mach/map.h> 29#include <mach/map.h>
24#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
31#include <mach/regs-fb.h>
25 32
26#include <plat/regs-serial.h> 33#include <plat/regs-serial.h>
34#include <plat/regs-srom.h>
35#include <plat/gpio-cfg.h>
27#include <plat/s5pv210.h> 36#include <plat/s5pv210.h>
28#include <plat/devs.h> 37#include <plat/devs.h>
29#include <plat/cpu.h> 38#include <plat/cpu.h>
@@ -33,6 +42,7 @@
33#include <plat/iic.h> 42#include <plat/iic.h>
34#include <plat/keypad.h> 43#include <plat/keypad.h>
35#include <plat/pm.h> 44#include <plat/pm.h>
45#include <plat/fb.h>
36 46
37/* Following are default values for UCON, ULCON and UFCON UART registers */ 47/* Following are default values for UCON, ULCON and UFCON UART registers */
38#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 48#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -102,12 +112,106 @@ static struct samsung_keypad_platdata smdkv210_keypad_data __initdata = {
102 .cols = 8, 112 .cols = 8,
103}; 113};
104 114
115static struct resource smdkv210_dm9000_resources[] = {
116 [0] = {
117 .start = S5PV210_PA_SROM_BANK5,
118 .end = S5PV210_PA_SROM_BANK5,
119 .flags = IORESOURCE_MEM,
120 },
121 [1] = {
122 .start = S5PV210_PA_SROM_BANK5 + 2,
123 .end = S5PV210_PA_SROM_BANK5 + 2,
124 .flags = IORESOURCE_MEM,
125 },
126 [2] = {
127 .start = IRQ_EINT(9),
128 .end = IRQ_EINT(9),
129 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
130 },
131};
132
133static struct dm9000_plat_data smdkv210_dm9000_platdata = {
134 .flags = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM,
135 .dev_addr = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 },
136};
137
138struct platform_device smdkv210_dm9000 = {
139 .name = "dm9000",
140 .id = -1,
141 .num_resources = ARRAY_SIZE(smdkv210_dm9000_resources),
142 .resource = smdkv210_dm9000_resources,
143 .dev = {
144 .platform_data = &smdkv210_dm9000_platdata,
145 },
146};
147
148static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd,
149 unsigned int power)
150{
151 if (power) {
152#if !defined(CONFIG_BACKLIGHT_PWM)
153 gpio_request(S5PV210_GPD0(3), "GPD0");
154 gpio_direction_output(S5PV210_GPD0(3), 1);
155 gpio_free(S5PV210_GPD0(3));
156#endif
157
158 /* fire nRESET on power up */
159 gpio_request(S5PV210_GPH0(6), "GPH0");
160
161 gpio_direction_output(S5PV210_GPH0(6), 1);
162
163 gpio_set_value(S5PV210_GPH0(6), 0);
164 mdelay(10);
165
166 gpio_set_value(S5PV210_GPH0(6), 1);
167 mdelay(10);
168
169 gpio_free(S5PV210_GPH0(6));
170 } else {
171#if !defined(CONFIG_BACKLIGHT_PWM)
172 gpio_request(S5PV210_GPD0(3), "GPD0");
173 gpio_direction_output(S5PV210_GPD0(3), 0);
174 gpio_free(S5PV210_GPD0(3));
175#endif
176 }
177}
178
179static struct plat_lcd_data smdkv210_lcd_lte480wv_data = {
180 .set_power = smdkv210_lte480wv_set_power,
181};
182
183static struct platform_device smdkv210_lcd_lte480wv = {
184 .name = "platform-lcd",
185 .dev.parent = &s3c_device_fb.dev,
186 .dev.platform_data = &smdkv210_lcd_lte480wv_data,
187};
188
189static struct s3c_fb_pd_win smdkv210_fb_win0 = {
190 .win_mode = {
191 .left_margin = 13,
192 .right_margin = 8,
193 .upper_margin = 7,
194 .lower_margin = 5,
195 .hsync_len = 3,
196 .vsync_len = 1,
197 .xres = 800,
198 .yres = 480,
199 },
200 .max_bpp = 32,
201 .default_bpp = 24,
202};
203
204static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
205 .win[0] = &smdkv210_fb_win0,
206 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
207 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
208 .setup_gpio = s5pv210_fb_gpio_setup_24bpp,
209};
210
105static struct platform_device *smdkv210_devices[] __initdata = { 211static struct platform_device *smdkv210_devices[] __initdata = {
106 &s5pv210_device_iis0,
107 &s5pv210_device_ac97,
108 &s5pv210_device_spdif,
109 &s3c_device_adc, 212 &s3c_device_adc,
110 &s3c_device_cfcon, 213 &s3c_device_cfcon,
214 &s3c_device_fb,
111 &s3c_device_hsmmc0, 215 &s3c_device_hsmmc0,
112 &s3c_device_hsmmc1, 216 &s3c_device_hsmmc1,
113 &s3c_device_hsmmc2, 217 &s3c_device_hsmmc2,
@@ -115,14 +219,37 @@ static struct platform_device *smdkv210_devices[] __initdata = {
115 &s3c_device_i2c0, 219 &s3c_device_i2c0,
116 &s3c_device_i2c1, 220 &s3c_device_i2c1,
117 &s3c_device_i2c2, 221 &s3c_device_i2c2,
118 &samsung_device_keypad,
119 &s3c_device_rtc, 222 &s3c_device_rtc,
120 &s3c_device_ts, 223 &s3c_device_ts,
121 &s3c_device_wdt, 224 &s3c_device_wdt,
225 &s5pv210_device_ac97,
226 &s5pv210_device_iis0,
227 &s5pv210_device_spdif,
228 &samsung_device_keypad,
229 &smdkv210_dm9000,
230 &smdkv210_lcd_lte480wv,
122}; 231};
123 232
233static void __init smdkv210_dm9000_init(void)
234{
235 unsigned int tmp;
236
237 gpio_request(S5PV210_MP01(5), "nCS5");
238 s3c_gpio_cfgpin(S5PV210_MP01(5), S3C_GPIO_SFN(2));
239 gpio_free(S5PV210_MP01(5));
240
241 tmp = (5 << S5P_SROM_BCX__TACC__SHIFT);
242 __raw_writel(tmp, S5P_SROM_BC5);
243
244 tmp = __raw_readl(S5P_SROM_BW);
245 tmp &= (S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS5__SHIFT);
246 tmp |= (1 << S5P_SROM_BW__NCS5__SHIFT);
247 __raw_writel(tmp, S5P_SROM_BW);
248}
249
124static struct i2c_board_info smdkv210_i2c_devs0[] __initdata = { 250static struct i2c_board_info smdkv210_i2c_devs0[] __initdata = {
125 { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */ 251 { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */
252 { I2C_BOARD_INFO("wm8580", 0x1b), },
126}; 253};
127 254
128static struct i2c_board_info smdkv210_i2c_devs1[] __initdata = { 255static struct i2c_board_info smdkv210_i2c_devs1[] __initdata = {
@@ -150,6 +277,8 @@ static void __init smdkv210_machine_init(void)
150{ 277{
151 s3c_pm_init(); 278 s3c_pm_init();
152 279
280 smdkv210_dm9000_init();
281
153 samsung_keypad_set_platdata(&smdkv210_keypad_data); 282 samsung_keypad_set_platdata(&smdkv210_keypad_data);
154 s3c24xx_ts_set_platdata(&s3c_ts_platform); 283 s3c24xx_ts_set_platdata(&s3c_ts_platform);
155 284
@@ -165,6 +294,8 @@ static void __init smdkv210_machine_init(void)
165 294
166 s3c_ide_set_platdata(&smdkv210_ide_pdata); 295 s3c_ide_set_platdata(&smdkv210_ide_pdata);
167 296
297 s3c_fb_set_platdata(&smdkv210_lcd0_pdata);
298
168 platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices)); 299 platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
169} 300}
170 301
diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig
index 1150b360f38c..b7aa3cd2198a 100644
--- a/arch/arm/mach-s5pv310/Kconfig
+++ b/arch/arm/mach-s5pv310/Kconfig
@@ -11,9 +11,15 @@ if ARCH_S5PV310
11 11
12config CPU_S5PV310 12config CPU_S5PV310
13 bool 13 bool
14 select S3C_PL330_DMA
14 help 15 help
15 Enable S5PV310 CPU support 16 Enable S5PV310 CPU support
16 17
18config S5PV310_DEV_PD
19 bool
20 help
21 Compile in platform device definitions for Power Domain
22
17config S5PV310_SETUP_I2C1 23config S5PV310_SETUP_I2C1
18 bool 24 bool
19 help 25 help
@@ -69,10 +75,13 @@ config MACH_SMDKC210
69 select CPU_S5PV310 75 select CPU_S5PV310
70 select S3C_DEV_RTC 76 select S3C_DEV_RTC
71 select S3C_DEV_WDT 77 select S3C_DEV_WDT
78 select S3C_DEV_I2C1
72 select S3C_DEV_HSMMC 79 select S3C_DEV_HSMMC
73 select S3C_DEV_HSMMC1 80 select S3C_DEV_HSMMC1
74 select S3C_DEV_HSMMC2 81 select S3C_DEV_HSMMC2
75 select S3C_DEV_HSMMC3 82 select S3C_DEV_HSMMC3
83 select S5PV310_DEV_PD
84 select S5PV310_SETUP_I2C1
76 select S5PV310_SETUP_SDHCI 85 select S5PV310_SETUP_SDHCI
77 help 86 help
78 Machine support for Samsung SMDKC210 87 Machine support for Samsung SMDKC210
@@ -82,6 +91,10 @@ config MACH_UNIVERSAL_C210
82 bool "Mobile UNIVERSAL_C210 Board" 91 bool "Mobile UNIVERSAL_C210 Board"
83 select CPU_S5PV310 92 select CPU_S5PV310
84 select S5P_DEV_ONENAND 93 select S5P_DEV_ONENAND
94 select S3C_DEV_HSMMC
95 select S3C_DEV_HSMMC2
96 select S3C_DEV_HSMMC3
97 select S5PV310_SETUP_SDHCI
85 select S3C_DEV_I2C1 98 select S3C_DEV_I2C1
86 select S5PV310_SETUP_I2C1 99 select S5PV310_SETUP_I2C1
87 help 100 help
@@ -97,10 +110,13 @@ config MACH_SMDKV310
97 select CPU_S5PV310 110 select CPU_S5PV310
98 select S3C_DEV_RTC 111 select S3C_DEV_RTC
99 select S3C_DEV_WDT 112 select S3C_DEV_WDT
113 select S3C_DEV_I2C1
100 select S3C_DEV_HSMMC 114 select S3C_DEV_HSMMC
101 select S3C_DEV_HSMMC1 115 select S3C_DEV_HSMMC1
102 select S3C_DEV_HSMMC2 116 select S3C_DEV_HSMMC2
103 select S3C_DEV_HSMMC3 117 select S3C_DEV_HSMMC3
118 select S5PV310_DEV_PD
119 select S5PV310_SETUP_I2C1
104 select S5PV310_SETUP_SDHCI 120 select S5PV310_SETUP_SDHCI
105 help 121 help
106 Machine support for Samsung SMDKV310 122 Machine support for Samsung SMDKV310
diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
index 84afc64e7c01..651f1933e228 100644
--- a/arch/arm/mach-s5pv310/Makefile
+++ b/arch/arm/mach-s5pv310/Makefile
@@ -13,7 +13,8 @@ obj- :=
13# Core support for S5PV310 system 13# Core support for S5PV310 system
14 14
15obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o 15obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o
16obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o irq-eint.o 16obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o irq-eint.o dma.o
17obj-$(CONFIG_CPU_FREQ) += cpufreq.o
17 18
18obj-$(CONFIG_SMP) += platsmp.o headsmp.o 19obj-$(CONFIG_SMP) += platsmp.o headsmp.o
19obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o 20obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
@@ -27,6 +28,9 @@ obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
27 28
28# device support 29# device support
29 30
31obj-y += dev-audio.o
32obj-$(CONFIG_S5PV310_DEV_PD) += dev-pd.o
33
30obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o 34obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o
31obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o 35obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o
32obj-$(CONFIG_S5PV310_SETUP_I2C3) += setup-i2c3.o 36obj-$(CONFIG_S5PV310_SETUP_I2C3) += setup-i2c3.o
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 58c9d33f36fe..753fa4465876 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -244,7 +244,7 @@ static struct clksrc_clk clk_mout_corebus = {
244 .id = -1, 244 .id = -1,
245 }, 245 },
246 .sources = &clkset_mout_corebus, 246 .sources = &clkset_mout_corebus,
247 .reg_src = { .reg = S5P_CLKSRC_CORE, .shift = 4, .size = 1 }, 247 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
248}; 248};
249 249
250static struct clksrc_clk clk_sclk_dmc = { 250static struct clksrc_clk clk_sclk_dmc = {
@@ -253,7 +253,7 @@ static struct clksrc_clk clk_sclk_dmc = {
253 .id = -1, 253 .id = -1,
254 .parent = &clk_mout_corebus.clk, 254 .parent = &clk_mout_corebus.clk,
255 }, 255 },
256 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 }, 256 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
257}; 257};
258 258
259static struct clksrc_clk clk_aclk_cored = { 259static struct clksrc_clk clk_aclk_cored = {
@@ -262,7 +262,7 @@ static struct clksrc_clk clk_aclk_cored = {
262 .id = -1, 262 .id = -1,
263 .parent = &clk_sclk_dmc.clk, 263 .parent = &clk_sclk_dmc.clk,
264 }, 264 },
265 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 }, 265 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
266}; 266};
267 267
268static struct clksrc_clk clk_aclk_corep = { 268static struct clksrc_clk clk_aclk_corep = {
@@ -271,7 +271,7 @@ static struct clksrc_clk clk_aclk_corep = {
271 .id = -1, 271 .id = -1,
272 .parent = &clk_aclk_cored.clk, 272 .parent = &clk_aclk_cored.clk,
273 }, 273 },
274 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 }, 274 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
275}; 275};
276 276
277static struct clksrc_clk clk_aclk_acp = { 277static struct clksrc_clk clk_aclk_acp = {
@@ -280,7 +280,7 @@ static struct clksrc_clk clk_aclk_acp = {
280 .id = -1, 280 .id = -1,
281 .parent = &clk_mout_corebus.clk, 281 .parent = &clk_mout_corebus.clk,
282 }, 282 },
283 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 }, 283 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
284}; 284};
285 285
286static struct clksrc_clk clk_pclk_acp = { 286static struct clksrc_clk clk_pclk_acp = {
@@ -289,7 +289,7 @@ static struct clksrc_clk clk_pclk_acp = {
289 .id = -1, 289 .id = -1,
290 .parent = &clk_aclk_acp.clk, 290 .parent = &clk_aclk_acp.clk,
291 }, 291 },
292 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 }, 292 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
293}; 293};
294 294
295/* Core list of CMU_TOP side */ 295/* Core list of CMU_TOP side */
@@ -467,6 +467,16 @@ static struct clk init_clocks_disable[] = {
467 .enable = s5pv310_clk_ip_fsys_ctrl, 467 .enable = s5pv310_clk_ip_fsys_ctrl,
468 .ctrlbit = (1 << 10), 468 .ctrlbit = (1 << 10),
469 }, { 469 }, {
470 .name = "pdma",
471 .id = 0,
472 .enable = s5pv310_clk_ip_fsys_ctrl,
473 .ctrlbit = (1 << 0),
474 }, {
475 .name = "pdma",
476 .id = 1,
477 .enable = s5pv310_clk_ip_fsys_ctrl,
478 .ctrlbit = (1 << 1),
479 }, {
470 .name = "adc", 480 .name = "adc",
471 .id = -1, 481 .id = -1,
472 .enable = s5pv310_clk_ip_peril_ctrl, 482 .enable = s5pv310_clk_ip_peril_ctrl,
@@ -507,6 +517,26 @@ static struct clk init_clocks_disable[] = {
507 .enable = s5pv310_clk_ip_peril_ctrl, 517 .enable = s5pv310_clk_ip_peril_ctrl,
508 .ctrlbit = (1 << 18), 518 .ctrlbit = (1 << 18),
509 }, { 519 }, {
520 .name = "iis",
521 .id = 0,
522 .enable = s5pv310_clk_ip_peril_ctrl,
523 .ctrlbit = (1 << 19),
524 }, {
525 .name = "iis",
526 .id = 1,
527 .enable = s5pv310_clk_ip_peril_ctrl,
528 .ctrlbit = (1 << 20),
529 }, {
530 .name = "iis",
531 .id = 2,
532 .enable = s5pv310_clk_ip_peril_ctrl,
533 .ctrlbit = (1 << 21),
534 }, {
535 .name = "ac97",
536 .id = -1,
537 .enable = s5pv310_clk_ip_peril_ctrl,
538 .ctrlbit = (1 << 27),
539 }, {
510 .name = "fimg2d", 540 .name = "fimg2d",
511 .id = -1, 541 .id = -1,
512 .enable = s5pv310_clk_ip_image_ctrl, 542 .enable = s5pv310_clk_ip_image_ctrl,
@@ -990,6 +1020,17 @@ static struct clksrc_clk *sysclks[] = {
990 &clk_dout_mmc4, 1020 &clk_dout_mmc4,
991}; 1021};
992 1022
1023static int xtal_rate;
1024
1025static unsigned long s5pv310_fout_apll_get_rate(struct clk *clk)
1026{
1027 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
1028}
1029
1030static struct clk_ops s5pv310_fout_apll_ops = {
1031 .get_rate = s5pv310_fout_apll_get_rate,
1032};
1033
993void __init_or_cpufreq s5pv310_setup_clocks(void) 1034void __init_or_cpufreq s5pv310_setup_clocks(void)
994{ 1035{
995 struct clk *xtal_clk; 1036 struct clk *xtal_clk;
@@ -1013,6 +1054,9 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
1013 BUG_ON(IS_ERR(xtal_clk)); 1054 BUG_ON(IS_ERR(xtal_clk));
1014 1055
1015 xtal = clk_get_rate(xtal_clk); 1056 xtal = clk_get_rate(xtal_clk);
1057
1058 xtal_rate = xtal;
1059
1016 clk_put(xtal_clk); 1060 clk_put(xtal_clk);
1017 1061
1018 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); 1062 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
@@ -1026,7 +1070,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
1026 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), 1070 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1027 __raw_readl(S5P_VPLL_CON1), pll_4650); 1071 __raw_readl(S5P_VPLL_CON1), pll_4650);
1028 1072
1029 clk_fout_apll.rate = apll; 1073 clk_fout_apll.ops = &s5pv310_fout_apll_ops;
1030 clk_fout_mpll.rate = mpll; 1074 clk_fout_mpll.rate = mpll;
1031 clk_fout_epll.rate = epll; 1075 clk_fout_epll.rate = epll;
1032 clk_fout_vpll.rate = vpll; 1076 clk_fout_vpll.rate = vpll;
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index 82ce4aa6d61a..72092db104c5 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -43,6 +43,11 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
43 .length = SZ_128K, 43 .length = SZ_128K,
44 .type = MT_DEVICE, 44 .type = MT_DEVICE,
45 }, { 45 }, {
46 .virtual = (unsigned long)S5P_VA_PMU,
47 .pfn = __phys_to_pfn(S5PV310_PA_PMU),
48 .length = SZ_64K,
49 .type = MT_DEVICE,
50 }, {
46 .virtual = (unsigned long)S5P_VA_COMBINER_BASE, 51 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
47 .pfn = __phys_to_pfn(S5PV310_PA_COMBINER), 52 .pfn = __phys_to_pfn(S5PV310_PA_COMBINER),
48 .length = SZ_4K, 53 .length = SZ_4K,
@@ -73,6 +78,11 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
73 .length = SZ_256, 78 .length = SZ_256,
74 .type = MT_DEVICE, 79 .type = MT_DEVICE,
75 }, { 80 }, {
81 .virtual = (unsigned long)S5P_VA_DMC0,
82 .pfn = __phys_to_pfn(S5PV310_PA_DMC0),
83 .length = SZ_4K,
84 .type = MT_DEVICE,
85 }, {
76 .virtual = (unsigned long)S3C_VA_UART, 86 .virtual = (unsigned long)S3C_VA_UART,
77 .pfn = __phys_to_pfn(S3C_PA_UART), 87 .pfn = __phys_to_pfn(S3C_PA_UART),
78 .length = SZ_512K, 88 .length = SZ_512K,
@@ -127,6 +137,15 @@ void __init s5pv310_init_irq(void)
127 gic_cpu_init(0, S5P_VA_GIC_CPU); 137 gic_cpu_init(0, S5P_VA_GIC_CPU);
128 138
129 for (irq = 0; irq < MAX_COMBINER_NR; irq++) { 139 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
140
141 /*
142 * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
143 * connected to the interrupt combiner. These irqs
144 * should be initialized to support cascade interrupt.
145 */
146 if ((irq >= 40) && !(irq == 51) && !(irq == 53))
147 continue;
148
130 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), 149 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
131 COMBINER_IRQ(irq, 0)); 150 COMBINER_IRQ(irq, 0));
132 combiner_cascade_irq(irq, IRQ_SPI(irq)); 151 combiner_cascade_irq(irq, IRQ_SPI(irq));
@@ -168,7 +187,7 @@ static int __init s5pv310_l2x0_cache_init(void)
168 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, 187 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
169 S5P_VA_L2CC + L2X0_POWER_CTRL); 188 S5P_VA_L2CC + L2X0_POWER_CTRL);
170 189
171 l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff); 190 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
172 191
173 return 0; 192 return 0;
174} 193}
diff --git a/arch/arm/mach-s5pv310/cpufreq.c b/arch/arm/mach-s5pv310/cpufreq.c
new file mode 100644
index 000000000000..b04cbc731128
--- /dev/null
+++ b/arch/arm/mach-s5pv310/cpufreq.c
@@ -0,0 +1,580 @@
1/* linux/arch/arm/mach-s5pv310/cpufreq.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - CPU frequency scaling support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/slab.h>
19#include <linux/regulator/consumer.h>
20#include <linux/cpufreq.h>
21
22#include <mach/map.h>
23#include <mach/regs-clock.h>
24#include <mach/regs-mem.h>
25
26#include <plat/clock.h>
27#include <plat/pm.h>
28
29static struct clk *cpu_clk;
30static struct clk *moutcore;
31static struct clk *mout_mpll;
32static struct clk *mout_apll;
33
34#ifdef CONFIG_REGULATOR
35static struct regulator *arm_regulator;
36static struct regulator *int_regulator;
37#endif
38
39static struct cpufreq_freqs freqs;
40static unsigned int memtype;
41
42enum s5pv310_memory_type {
43 DDR2 = 4,
44 LPDDR2,
45 DDR3,
46};
47
48enum cpufreq_level_index {
49 L0, L1, L2, L3, CPUFREQ_LEVEL_END,
50};
51
52static struct cpufreq_frequency_table s5pv310_freq_table[] = {
53 {L0, 1000*1000},
54 {L1, 800*1000},
55 {L2, 400*1000},
56 {L3, 100*1000},
57 {0, CPUFREQ_TABLE_END},
58};
59
60static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
61 /*
62 * Clock divider value for following
63 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
64 * DIVATB, DIVPCLK_DBG, DIVAPLL }
65 */
66
67 /* ARM L0: 1000MHz */
68 { 0, 3, 7, 3, 3, 0, 1 },
69
70 /* ARM L1: 800MHz */
71 { 0, 3, 7, 3, 3, 0, 1 },
72
73 /* ARM L2: 400MHz */
74 { 0, 1, 3, 1, 3, 0, 1 },
75
76 /* ARM L3: 100MHz */
77 { 0, 0, 1, 0, 3, 1, 1 },
78};
79
80static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
81 /*
82 * Clock divider value for following
83 * { DIVCOPY, DIVHPM }
84 */
85
86 /* ARM L0: 1000MHz */
87 { 3, 0 },
88
89 /* ARM L1: 800MHz */
90 { 3, 0 },
91
92 /* ARM L2: 400MHz */
93 { 3, 0 },
94
95 /* ARM L3: 100MHz */
96 { 3, 0 },
97};
98
99static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
100 /*
101 * Clock divider value for following
102 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
103 * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
104 */
105
106 /* DMC L0: 400MHz */
107 { 3, 1, 1, 1, 1, 1, 3, 1 },
108
109 /* DMC L1: 400MHz */
110 { 3, 1, 1, 1, 1, 1, 3, 1 },
111
112 /* DMC L2: 266.7MHz */
113 { 7, 1, 1, 2, 1, 1, 3, 1 },
114
115 /* DMC L3: 200MHz */
116 { 7, 1, 1, 3, 1, 1, 3, 1 },
117};
118
119static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
120 /*
121 * Clock divider value for following
122 * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
123 */
124
125 /* ACLK200 L0: 200MHz */
126 { 3, 7, 4, 5, 1 },
127
128 /* ACLK200 L1: 200MHz */
129 { 3, 7, 4, 5, 1 },
130
131 /* ACLK200 L2: 160MHz */
132 { 4, 7, 5, 7, 1 },
133
134 /* ACLK200 L3: 133.3MHz */
135 { 5, 7, 7, 7, 1 },
136};
137
138static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
139 /*
140 * Clock divider value for following
141 * { DIVGDL/R, DIVGPL/R }
142 */
143
144 /* ACLK_GDL/R L0: 200MHz */
145 { 3, 1 },
146
147 /* ACLK_GDL/R L1: 200MHz */
148 { 3, 1 },
149
150 /* ACLK_GDL/R L2: 160MHz */
151 { 4, 1 },
152
153 /* ACLK_GDL/R L3: 133.3MHz */
154 { 5, 1 },
155};
156
157struct cpufreq_voltage_table {
158 unsigned int index; /* any */
159 unsigned int arm_volt; /* uV */
160 unsigned int int_volt;
161};
162
163static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
164 {
165 .index = L0,
166 .arm_volt = 1200000,
167 .int_volt = 1100000,
168 }, {
169 .index = L1,
170 .arm_volt = 1100000,
171 .int_volt = 1100000,
172 }, {
173 .index = L2,
174 .arm_volt = 1000000,
175 .int_volt = 1000000,
176 }, {
177 .index = L3,
178 .arm_volt = 900000,
179 .int_volt = 1000000,
180 },
181};
182
183static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
184 /* APLL FOUT L0: 1000MHz */
185 ((250 << 16) | (6 << 8) | 1),
186
187 /* APLL FOUT L1: 800MHz */
188 ((200 << 16) | (6 << 8) | 1),
189
190 /* APLL FOUT L2 : 400MHz */
191 ((200 << 16) | (6 << 8) | 2),
192
193 /* APLL FOUT L3: 100MHz */
194 ((200 << 16) | (6 << 8) | 4),
195};
196
197int s5pv310_verify_speed(struct cpufreq_policy *policy)
198{
199 return cpufreq_frequency_table_verify(policy, s5pv310_freq_table);
200}
201
202unsigned int s5pv310_getspeed(unsigned int cpu)
203{
204 return clk_get_rate(cpu_clk) / 1000;
205}
206
207void s5pv310_set_clkdiv(unsigned int div_index)
208{
209 unsigned int tmp;
210
211 /* Change Divider - CPU0 */
212
213 tmp = __raw_readl(S5P_CLKDIV_CPU);
214
215 tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
216 S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
217 S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
218 S5P_CLKDIV_CPU0_APLL_MASK);
219
220 tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
221 (clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
222 (clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
223 (clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
224 (clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
225 (clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
226 (clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
227
228 __raw_writel(tmp, S5P_CLKDIV_CPU);
229
230 do {
231 tmp = __raw_readl(S5P_CLKDIV_STATCPU);
232 } while (tmp & 0x1111111);
233
234 /* Change Divider - CPU1 */
235
236 tmp = __raw_readl(S5P_CLKDIV_CPU1);
237
238 tmp &= ~((0x7 << 4) | 0x7);
239
240 tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
241 (clkdiv_cpu1[div_index][1] << 0));
242
243 __raw_writel(tmp, S5P_CLKDIV_CPU1);
244
245 do {
246 tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
247 } while (tmp & 0x11);
248
249 /* Change Divider - DMC0 */
250
251 tmp = __raw_readl(S5P_CLKDIV_DMC0);
252
253 tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
254 S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
255 S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
256 S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
257
258 tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) |
259 (clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
260 (clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) |
261 (clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) |
262 (clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) |
263 (clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) |
264 (clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) |
265 (clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT));
266
267 __raw_writel(tmp, S5P_CLKDIV_DMC0);
268
269 do {
270 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
271 } while (tmp & 0x11111111);
272
273 /* Change Divider - TOP */
274
275 tmp = __raw_readl(S5P_CLKDIV_TOP);
276
277 tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
278 S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
279 S5P_CLKDIV_TOP_ONENAND_MASK);
280
281 tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) |
282 (clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) |
283 (clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) |
284 (clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) |
285 (clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT));
286
287 __raw_writel(tmp, S5P_CLKDIV_TOP);
288
289 do {
290 tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
291 } while (tmp & 0x11111);
292
293 /* Change Divider - LEFTBUS */
294
295 tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
296
297 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
298
299 tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
300 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
301
302 __raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
303
304 do {
305 tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
306 } while (tmp & 0x11);
307
308 /* Change Divider - RIGHTBUS */
309
310 tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
311
312 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
313
314 tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
315 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
316
317 __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
318
319 do {
320 tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
321 } while (tmp & 0x11);
322}
323
324static void s5pv310_set_apll(unsigned int index)
325{
326 unsigned int tmp;
327
328 /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
329 clk_set_parent(moutcore, mout_mpll);
330
331 do {
332 tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
333 >> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
334 tmp &= 0x7;
335 } while (tmp != 0x2);
336
337 /* 2. Set APLL Lock time */
338 __raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
339
340 /* 3. Change PLL PMS values */
341 tmp = __raw_readl(S5P_APLL_CON0);
342 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
343 tmp |= s5pv310_apll_pms_table[index];
344 __raw_writel(tmp, S5P_APLL_CON0);
345
346 /* 4. wait_lock_time */
347 do {
348 tmp = __raw_readl(S5P_APLL_CON0);
349 } while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
350
351 /* 5. MUX_CORE_SEL = APLL */
352 clk_set_parent(moutcore, mout_apll);
353
354 do {
355 tmp = __raw_readl(S5P_CLKMUX_STATCPU);
356 tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
357 } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
358}
359
360static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index)
361{
362 unsigned int tmp;
363
364 if (old_index > new_index) {
365 /* The frequency changing to L0 needs to change apll */
366 if (freqs.new == s5pv310_freq_table[L0].frequency) {
367 /* 1. Change the system clock divider values */
368 s5pv310_set_clkdiv(new_index);
369
370 /* 2. Change the apll m,p,s value */
371 s5pv310_set_apll(new_index);
372 } else {
373 /* 1. Change the system clock divider values */
374 s5pv310_set_clkdiv(new_index);
375
376 /* 2. Change just s value in apll m,p,s value */
377 tmp = __raw_readl(S5P_APLL_CON0);
378 tmp &= ~(0x7 << 0);
379 tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
380 __raw_writel(tmp, S5P_APLL_CON0);
381 }
382 }
383
384 else if (old_index < new_index) {
385 /* The frequency changing from L0 needs to change apll */
386 if (freqs.old == s5pv310_freq_table[L0].frequency) {
387 /* 1. Change the apll m,p,s value */
388 s5pv310_set_apll(new_index);
389
390 /* 2. Change the system clock divider values */
391 s5pv310_set_clkdiv(new_index);
392 } else {
393 /* 1. Change just s value in apll m,p,s value */
394 tmp = __raw_readl(S5P_APLL_CON0);
395 tmp &= ~(0x7 << 0);
396 tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
397 __raw_writel(tmp, S5P_APLL_CON0);
398
399 /* 2. Change the system clock divider values */
400 s5pv310_set_clkdiv(new_index);
401 }
402 }
403}
404
405static int s5pv310_target(struct cpufreq_policy *policy,
406 unsigned int target_freq,
407 unsigned int relation)
408{
409 unsigned int index, old_index;
410 unsigned int arm_volt, int_volt;
411
412 freqs.old = s5pv310_getspeed(policy->cpu);
413
414 if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
415 freqs.old, relation, &old_index))
416 return -EINVAL;
417
418 if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
419 target_freq, relation, &index))
420 return -EINVAL;
421
422 freqs.new = s5pv310_freq_table[index].frequency;
423 freqs.cpu = policy->cpu;
424
425 if (freqs.new == freqs.old)
426 return 0;
427
428 /* get the voltage value */
429 arm_volt = s5pv310_volt_table[index].arm_volt;
430 int_volt = s5pv310_volt_table[index].int_volt;
431
432 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
433
434 /* control regulator */
435 if (freqs.new > freqs.old) {
436 /* Voltage up */
437#ifdef CONFIG_REGULATOR
438 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
439 regulator_set_voltage(int_regulator, int_volt, int_volt);
440#endif
441 }
442
443 /* Clock Configuration Procedure */
444 s5pv310_set_frequency(old_index, index);
445
446 /* control regulator */
447 if (freqs.new < freqs.old) {
448 /* Voltage down */
449#ifdef CONFIG_REGULATOR
450 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
451 regulator_set_voltage(int_regulator, int_volt, int_volt);
452#endif
453 }
454
455 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
456
457 return 0;
458}
459
460#ifdef CONFIG_PM
461static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy,
462 pm_message_t pmsg)
463{
464 return 0;
465}
466
467static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy)
468{
469 return 0;
470}
471#endif
472
473static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy)
474{
475 policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu);
476
477 cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu);
478
479 /* set the transition latency value */
480 policy->cpuinfo.transition_latency = 100000;
481
482 /*
483 * S5PV310 multi-core processors has 2 cores
484 * that the frequency cannot be set independently.
485 * Each cpu is bound to the same speed.
486 * So the affected cpu is all of the cpus.
487 */
488 cpumask_setall(policy->cpus);
489
490 return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table);
491}
492
493static struct cpufreq_driver s5pv310_driver = {
494 .flags = CPUFREQ_STICKY,
495 .verify = s5pv310_verify_speed,
496 .target = s5pv310_target,
497 .get = s5pv310_getspeed,
498 .init = s5pv310_cpufreq_cpu_init,
499 .name = "s5pv310_cpufreq",
500#ifdef CONFIG_PM
501 .suspend = s5pv310_cpufreq_suspend,
502 .resume = s5pv310_cpufreq_resume,
503#endif
504};
505
506static int __init s5pv310_cpufreq_init(void)
507{
508 cpu_clk = clk_get(NULL, "armclk");
509 if (IS_ERR(cpu_clk))
510 return PTR_ERR(cpu_clk);
511
512 moutcore = clk_get(NULL, "moutcore");
513 if (IS_ERR(moutcore))
514 goto out;
515
516 mout_mpll = clk_get(NULL, "mout_mpll");
517 if (IS_ERR(mout_mpll))
518 goto out;
519
520 mout_apll = clk_get(NULL, "mout_apll");
521 if (IS_ERR(mout_apll))
522 goto out;
523
524#ifdef CONFIG_REGULATOR
525 arm_regulator = regulator_get(NULL, "vdd_arm");
526 if (IS_ERR(arm_regulator)) {
527 printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
528 goto out;
529 }
530
531 int_regulator = regulator_get(NULL, "vdd_int");
532 if (IS_ERR(int_regulator)) {
533 printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
534 goto out;
535 }
536#endif
537
538 /*
539 * Check DRAM type.
540 * Because DVFS level is different according to DRAM type.
541 */
542 memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET);
543 memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT);
544 memtype &= S5P_DMC0_MEMTYPE_MASK;
545
546 if ((memtype < DDR2) && (memtype > DDR3)) {
547 printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype);
548 goto out;
549 } else {
550 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
551 }
552
553 return cpufreq_register_driver(&s5pv310_driver);
554
555out:
556 if (!IS_ERR(cpu_clk))
557 clk_put(cpu_clk);
558
559 if (!IS_ERR(moutcore))
560 clk_put(moutcore);
561
562 if (!IS_ERR(mout_mpll))
563 clk_put(mout_mpll);
564
565 if (!IS_ERR(mout_apll))
566 clk_put(mout_apll);
567
568#ifdef CONFIG_REGULATOR
569 if (!IS_ERR(arm_regulator))
570 regulator_put(arm_regulator);
571
572 if (!IS_ERR(int_regulator))
573 regulator_put(int_regulator);
574#endif
575
576 printk(KERN_ERR "%s: failed initialization\n", __func__);
577
578 return -EINVAL;
579}
580late_initcall(s5pv310_cpufreq_init);
diff --git a/arch/arm/mach-s5pv310/dev-audio.c b/arch/arm/mach-s5pv310/dev-audio.c
new file mode 100644
index 000000000000..a1964242f0fa
--- /dev/null
+++ b/arch/arm/mach-s5pv310/dev-audio.c
@@ -0,0 +1,364 @@
1/* linux/arch/arm/mach-s5pv310/dev-audio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <plat/gpio-cfg.h>
16#include <plat/audio.h>
17
18#include <mach/map.h>
19#include <mach/dma.h>
20#include <mach/irqs.h>
21
22static const char *rclksrc[] = {
23 [0] = "busclk",
24 [1] = "i2sclk",
25};
26
27static int s5pv310_cfg_i2s(struct platform_device *pdev)
28{
29 /* configure GPIO for i2s port */
30 switch (pdev->id) {
31 case 0:
32 s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 7, S3C_GPIO_SFN(2));
33 break;
34 case 1:
35 s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(2));
36 break;
37 case 2:
38 s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(4));
39 break;
40 default:
41 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
42 return -EINVAL;
43 }
44
45 return 0;
46}
47
48static struct s3c_audio_pdata i2sv5_pdata = {
49 .cfg_gpio = s5pv310_cfg_i2s,
50 .type = {
51 .i2s = {
52 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
53 | QUIRK_NEED_RSTCLR,
54 .src_clk = rclksrc,
55 },
56 },
57};
58
59static struct resource s5pv310_i2s0_resource[] = {
60 [0] = {
61 .start = S5PV310_PA_I2S0,
62 .end = S5PV310_PA_I2S0 + 0x100 - 1,
63 .flags = IORESOURCE_MEM,
64 },
65 [1] = {
66 .start = DMACH_I2S0_TX,
67 .end = DMACH_I2S0_TX,
68 .flags = IORESOURCE_DMA,
69 },
70 [2] = {
71 .start = DMACH_I2S0_RX,
72 .end = DMACH_I2S0_RX,
73 .flags = IORESOURCE_DMA,
74 },
75 [3] = {
76 .start = DMACH_I2S0S_TX,
77 .end = DMACH_I2S0S_TX,
78 .flags = IORESOURCE_DMA,
79 },
80};
81
82struct platform_device s5pv310_device_i2s0 = {
83 .name = "samsung-i2s",
84 .id = 0,
85 .num_resources = ARRAY_SIZE(s5pv310_i2s0_resource),
86 .resource = s5pv310_i2s0_resource,
87 .dev = {
88 .platform_data = &i2sv5_pdata,
89 },
90};
91
92static const char *rclksrc_v3[] = {
93 [0] = "sclk_i2s",
94 [1] = "no_such_clock",
95};
96
97static struct s3c_audio_pdata i2sv3_pdata = {
98 .cfg_gpio = s5pv310_cfg_i2s,
99 .type = {
100 .i2s = {
101 .quirks = QUIRK_NO_MUXPSR,
102 .src_clk = rclksrc_v3,
103 },
104 },
105};
106
107static struct resource s5pv310_i2s1_resource[] = {
108 [0] = {
109 .start = S5PV310_PA_I2S1,
110 .end = S5PV310_PA_I2S1 + 0x100 - 1,
111 .flags = IORESOURCE_MEM,
112 },
113 [1] = {
114 .start = DMACH_I2S1_TX,
115 .end = DMACH_I2S1_TX,
116 .flags = IORESOURCE_DMA,
117 },
118 [2] = {
119 .start = DMACH_I2S1_RX,
120 .end = DMACH_I2S1_RX,
121 .flags = IORESOURCE_DMA,
122 },
123};
124
125struct platform_device s5pv310_device_i2s1 = {
126 .name = "samsung-i2s",
127 .id = 1,
128 .num_resources = ARRAY_SIZE(s5pv310_i2s1_resource),
129 .resource = s5pv310_i2s1_resource,
130 .dev = {
131 .platform_data = &i2sv3_pdata,
132 },
133};
134
135static struct resource s5pv310_i2s2_resource[] = {
136 [0] = {
137 .start = S5PV310_PA_I2S2,
138 .end = S5PV310_PA_I2S2 + 0x100 - 1,
139 .flags = IORESOURCE_MEM,
140 },
141 [1] = {
142 .start = DMACH_I2S2_TX,
143 .end = DMACH_I2S2_TX,
144 .flags = IORESOURCE_DMA,
145 },
146 [2] = {
147 .start = DMACH_I2S2_RX,
148 .end = DMACH_I2S2_RX,
149 .flags = IORESOURCE_DMA,
150 },
151};
152
153struct platform_device s5pv310_device_i2s2 = {
154 .name = "samsung-i2s",
155 .id = 2,
156 .num_resources = ARRAY_SIZE(s5pv310_i2s2_resource),
157 .resource = s5pv310_i2s2_resource,
158 .dev = {
159 .platform_data = &i2sv3_pdata,
160 },
161};
162
163/* PCM Controller platform_devices */
164
165static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev)
166{
167 switch (pdev->id) {
168 case 0:
169 s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 5, S3C_GPIO_SFN(3));
170 break;
171 case 1:
172 s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(3));
173 break;
174 case 2:
175 s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(3));
176 break;
177 default:
178 printk(KERN_DEBUG "Invalid PCM Controller number!");
179 return -EINVAL;
180 }
181
182 return 0;
183}
184
185static struct s3c_audio_pdata s3c_pcm_pdata = {
186 .cfg_gpio = s5pv310_pcm_cfg_gpio,
187};
188
189static struct resource s5pv310_pcm0_resource[] = {
190 [0] = {
191 .start = S5PV310_PA_PCM0,
192 .end = S5PV310_PA_PCM0 + 0x100 - 1,
193 .flags = IORESOURCE_MEM,
194 },
195 [1] = {
196 .start = DMACH_PCM0_TX,
197 .end = DMACH_PCM0_TX,
198 .flags = IORESOURCE_DMA,
199 },
200 [2] = {
201 .start = DMACH_PCM0_RX,
202 .end = DMACH_PCM0_RX,
203 .flags = IORESOURCE_DMA,
204 },
205};
206
207struct platform_device s5pv310_device_pcm0 = {
208 .name = "samsung-pcm",
209 .id = 0,
210 .num_resources = ARRAY_SIZE(s5pv310_pcm0_resource),
211 .resource = s5pv310_pcm0_resource,
212 .dev = {
213 .platform_data = &s3c_pcm_pdata,
214 },
215};
216
217static struct resource s5pv310_pcm1_resource[] = {
218 [0] = {
219 .start = S5PV310_PA_PCM1,
220 .end = S5PV310_PA_PCM1 + 0x100 - 1,
221 .flags = IORESOURCE_MEM,
222 },
223 [1] = {
224 .start = DMACH_PCM1_TX,
225 .end = DMACH_PCM1_TX,
226 .flags = IORESOURCE_DMA,
227 },
228 [2] = {
229 .start = DMACH_PCM1_RX,
230 .end = DMACH_PCM1_RX,
231 .flags = IORESOURCE_DMA,
232 },
233};
234
235struct platform_device s5pv310_device_pcm1 = {
236 .name = "samsung-pcm",
237 .id = 1,
238 .num_resources = ARRAY_SIZE(s5pv310_pcm1_resource),
239 .resource = s5pv310_pcm1_resource,
240 .dev = {
241 .platform_data = &s3c_pcm_pdata,
242 },
243};
244
245static struct resource s5pv310_pcm2_resource[] = {
246 [0] = {
247 .start = S5PV310_PA_PCM2,
248 .end = S5PV310_PA_PCM2 + 0x100 - 1,
249 .flags = IORESOURCE_MEM,
250 },
251 [1] = {
252 .start = DMACH_PCM2_TX,
253 .end = DMACH_PCM2_TX,
254 .flags = IORESOURCE_DMA,
255 },
256 [2] = {
257 .start = DMACH_PCM2_RX,
258 .end = DMACH_PCM2_RX,
259 .flags = IORESOURCE_DMA,
260 },
261};
262
263struct platform_device s5pv310_device_pcm2 = {
264 .name = "samsung-pcm",
265 .id = 2,
266 .num_resources = ARRAY_SIZE(s5pv310_pcm2_resource),
267 .resource = s5pv310_pcm2_resource,
268 .dev = {
269 .platform_data = &s3c_pcm_pdata,
270 },
271};
272
273/* AC97 Controller platform devices */
274
275static int s5pv310_ac97_cfg_gpio(struct platform_device *pdev)
276{
277 return s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(4));
278}
279
280static struct resource s5pv310_ac97_resource[] = {
281 [0] = {
282 .start = S5PV310_PA_AC97,
283 .end = S5PV310_PA_AC97 + 0x100 - 1,
284 .flags = IORESOURCE_MEM,
285 },
286 [1] = {
287 .start = DMACH_AC97_PCMOUT,
288 .end = DMACH_AC97_PCMOUT,
289 .flags = IORESOURCE_DMA,
290 },
291 [2] = {
292 .start = DMACH_AC97_PCMIN,
293 .end = DMACH_AC97_PCMIN,
294 .flags = IORESOURCE_DMA,
295 },
296 [3] = {
297 .start = DMACH_AC97_MICIN,
298 .end = DMACH_AC97_MICIN,
299 .flags = IORESOURCE_DMA,
300 },
301 [4] = {
302 .start = IRQ_AC97,
303 .end = IRQ_AC97,
304 .flags = IORESOURCE_IRQ,
305 },
306};
307
308static struct s3c_audio_pdata s3c_ac97_pdata = {
309 .cfg_gpio = s5pv310_ac97_cfg_gpio,
310};
311
312static u64 s5pv310_ac97_dmamask = DMA_BIT_MASK(32);
313
314struct platform_device s5pv310_device_ac97 = {
315 .name = "samsung-ac97",
316 .id = -1,
317 .num_resources = ARRAY_SIZE(s5pv310_ac97_resource),
318 .resource = s5pv310_ac97_resource,
319 .dev = {
320 .platform_data = &s3c_ac97_pdata,
321 .dma_mask = &s5pv310_ac97_dmamask,
322 .coherent_dma_mask = DMA_BIT_MASK(32),
323 },
324};
325
326/* S/PDIF Controller platform_device */
327
328static int s5pv310_spdif_cfg_gpio(struct platform_device *pdev)
329{
330 s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 2, S3C_GPIO_SFN(3));
331
332 return 0;
333}
334
335static struct resource s5pv310_spdif_resource[] = {
336 [0] = {
337 .start = S5PV310_PA_SPDIF,
338 .end = S5PV310_PA_SPDIF + 0x100 - 1,
339 .flags = IORESOURCE_MEM,
340 },
341 [1] = {
342 .start = DMACH_SPDIF,
343 .end = DMACH_SPDIF,
344 .flags = IORESOURCE_DMA,
345 },
346};
347
348static struct s3c_audio_pdata samsung_spdif_pdata = {
349 .cfg_gpio = s5pv310_spdif_cfg_gpio,
350};
351
352static u64 s5pv310_spdif_dmamask = DMA_BIT_MASK(32);
353
354struct platform_device s5pv310_device_spdif = {
355 .name = "samsung-spdif",
356 .id = -1,
357 .num_resources = ARRAY_SIZE(s5pv310_spdif_resource),
358 .resource = s5pv310_spdif_resource,
359 .dev = {
360 .platform_data = &samsung_spdif_pdata,
361 .dma_mask = &s5pv310_spdif_dmamask,
362 .coherent_dma_mask = DMA_BIT_MASK(32),
363 },
364};
diff --git a/arch/arm/mach-s5pv310/dev-pd.c b/arch/arm/mach-s5pv310/dev-pd.c
new file mode 100644
index 000000000000..58a50c2d0b67
--- /dev/null
+++ b/arch/arm/mach-s5pv310/dev-pd.c
@@ -0,0 +1,139 @@
1/* linux/arch/arm/mach-s5pv310/dev-pd.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - Power Domain support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17
18#include <mach/regs-pmu.h>
19
20#include <plat/pd.h>
21
22static int s5pv310_pd_enable(struct device *dev)
23{
24 struct samsung_pd_info *pdata = dev->platform_data;
25 u32 timeout;
26
27 __raw_writel(S5P_INT_LOCAL_PWR_EN, pdata->base);
28
29 /* Wait max 1ms */
30 timeout = 10;
31 while ((__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN)
32 != S5P_INT_LOCAL_PWR_EN) {
33 if (timeout == 0) {
34 printk(KERN_ERR "Power domain %s enable failed.\n",
35 dev_name(dev));
36 return -ETIMEDOUT;
37 }
38 timeout--;
39 udelay(100);
40 }
41
42 return 0;
43}
44
45static int s5pv310_pd_disable(struct device *dev)
46{
47 struct samsung_pd_info *pdata = dev->platform_data;
48 u32 timeout;
49
50 __raw_writel(0, pdata->base);
51
52 /* Wait max 1ms */
53 timeout = 10;
54 while (__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) {
55 if (timeout == 0) {
56 printk(KERN_ERR "Power domain %s disable failed.\n",
57 dev_name(dev));
58 return -ETIMEDOUT;
59 }
60 timeout--;
61 udelay(100);
62 }
63
64 return 0;
65}
66
67struct platform_device s5pv310_device_pd[] = {
68 {
69 .name = "samsung-pd",
70 .id = 0,
71 .dev = {
72 .platform_data = &(struct samsung_pd_info) {
73 .enable = s5pv310_pd_enable,
74 .disable = s5pv310_pd_disable,
75 .base = S5P_PMU_MFC_CONF,
76 },
77 },
78 }, {
79 .name = "samsung-pd",
80 .id = 1,
81 .dev = {
82 .platform_data = &(struct samsung_pd_info) {
83 .enable = s5pv310_pd_enable,
84 .disable = s5pv310_pd_disable,
85 .base = S5P_PMU_G3D_CONF,
86 },
87 },
88 }, {
89 .name = "samsung-pd",
90 .id = 2,
91 .dev = {
92 .platform_data = &(struct samsung_pd_info) {
93 .enable = s5pv310_pd_enable,
94 .disable = s5pv310_pd_disable,
95 .base = S5P_PMU_LCD0_CONF,
96 },
97 },
98 }, {
99 .name = "samsung-pd",
100 .id = 3,
101 .dev = {
102 .platform_data = &(struct samsung_pd_info) {
103 .enable = s5pv310_pd_enable,
104 .disable = s5pv310_pd_disable,
105 .base = S5P_PMU_LCD1_CONF,
106 },
107 },
108 }, {
109 .name = "samsung-pd",
110 .id = 4,
111 .dev = {
112 .platform_data = &(struct samsung_pd_info) {
113 .enable = s5pv310_pd_enable,
114 .disable = s5pv310_pd_disable,
115 .base = S5P_PMU_TV_CONF,
116 },
117 },
118 }, {
119 .name = "samsung-pd",
120 .id = 5,
121 .dev = {
122 .platform_data = &(struct samsung_pd_info) {
123 .enable = s5pv310_pd_enable,
124 .disable = s5pv310_pd_disable,
125 .base = S5P_PMU_CAM_CONF,
126 },
127 },
128 }, {
129 .name = "samsung-pd",
130 .id = 6,
131 .dev = {
132 .platform_data = &(struct samsung_pd_info) {
133 .enable = s5pv310_pd_enable,
134 .disable = s5pv310_pd_disable,
135 .base = S5P_PMU_GPS_CONF,
136 },
137 },
138 },
139};
diff --git a/arch/arm/mach-s5pv310/dma.c b/arch/arm/mach-s5pv310/dma.c
new file mode 100644
index 000000000000..20066c7c9e56
--- /dev/null
+++ b/arch/arm/mach-s5pv310/dma.c
@@ -0,0 +1,168 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h>
22
23#include <plat/devs.h>
24#include <plat/irqs.h>
25
26#include <mach/map.h>
27#include <mach/irqs.h>
28
29#include <plat/s3c-pl330-pdata.h>
30
31static u64 dma_dmamask = DMA_BIT_MASK(32);
32
33static struct resource s5pv310_pdma0_resource[] = {
34 [0] = {
35 .start = S5PV310_PA_PDMA0,
36 .end = S5PV310_PA_PDMA0 + SZ_4K,
37 .flags = IORESOURCE_MEM,
38 },
39 [1] = {
40 .start = IRQ_PDMA0,
41 .end = IRQ_PDMA0,
42 .flags = IORESOURCE_IRQ,
43 },
44};
45
46static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
47 .peri = {
48 [0] = DMACH_PCM0_RX,
49 [1] = DMACH_PCM0_TX,
50 [2] = DMACH_PCM2_RX,
51 [3] = DMACH_PCM2_TX,
52 [4] = DMACH_MSM_REQ0,
53 [5] = DMACH_MSM_REQ2,
54 [6] = DMACH_SPI0_RX,
55 [7] = DMACH_SPI0_TX,
56 [8] = DMACH_SPI2_RX,
57 [9] = DMACH_SPI2_TX,
58 [10] = DMACH_I2S0S_TX,
59 [11] = DMACH_I2S0_RX,
60 [12] = DMACH_I2S0_TX,
61 [13] = DMACH_I2S2_RX,
62 [14] = DMACH_I2S2_TX,
63 [15] = DMACH_UART0_RX,
64 [16] = DMACH_UART0_TX,
65 [17] = DMACH_UART2_RX,
66 [18] = DMACH_UART2_TX,
67 [19] = DMACH_UART4_RX,
68 [20] = DMACH_UART4_TX,
69 [21] = DMACH_SLIMBUS0_RX,
70 [22] = DMACH_SLIMBUS0_TX,
71 [23] = DMACH_SLIMBUS2_RX,
72 [24] = DMACH_SLIMBUS2_TX,
73 [25] = DMACH_SLIMBUS4_RX,
74 [26] = DMACH_SLIMBUS4_TX,
75 [27] = DMACH_AC97_MICIN,
76 [28] = DMACH_AC97_PCMIN,
77 [29] = DMACH_AC97_PCMOUT,
78 [30] = DMACH_MAX,
79 [31] = DMACH_MAX,
80 },
81};
82
83static struct platform_device s5pv310_device_pdma0 = {
84 .name = "s3c-pl330",
85 .id = 0,
86 .num_resources = ARRAY_SIZE(s5pv310_pdma0_resource),
87 .resource = s5pv310_pdma0_resource,
88 .dev = {
89 .dma_mask = &dma_dmamask,
90 .coherent_dma_mask = DMA_BIT_MASK(32),
91 .platform_data = &s5pv310_pdma0_pdata,
92 },
93};
94
95static struct resource s5pv310_pdma1_resource[] = {
96 [0] = {
97 .start = S5PV310_PA_PDMA1,
98 .end = S5PV310_PA_PDMA1 + SZ_4K,
99 .flags = IORESOURCE_MEM,
100 },
101 [1] = {
102 .start = IRQ_PDMA1,
103 .end = IRQ_PDMA1,
104 .flags = IORESOURCE_IRQ,
105 },
106};
107
108static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
109 .peri = {
110 [0] = DMACH_PCM0_RX,
111 [1] = DMACH_PCM0_TX,
112 [2] = DMACH_PCM1_RX,
113 [3] = DMACH_PCM1_TX,
114 [4] = DMACH_MSM_REQ1,
115 [5] = DMACH_MSM_REQ3,
116 [6] = DMACH_SPI1_RX,
117 [7] = DMACH_SPI1_TX,
118 [8] = DMACH_I2S0S_TX,
119 [9] = DMACH_I2S0_RX,
120 [10] = DMACH_I2S0_TX,
121 [11] = DMACH_I2S1_RX,
122 [12] = DMACH_I2S1_TX,
123 [13] = DMACH_UART0_RX,
124 [14] = DMACH_UART0_TX,
125 [15] = DMACH_UART1_RX,
126 [16] = DMACH_UART1_TX,
127 [17] = DMACH_UART3_RX,
128 [18] = DMACH_UART3_TX,
129 [19] = DMACH_SLIMBUS1_RX,
130 [20] = DMACH_SLIMBUS1_TX,
131 [21] = DMACH_SLIMBUS3_RX,
132 [22] = DMACH_SLIMBUS3_TX,
133 [23] = DMACH_SLIMBUS5_RX,
134 [24] = DMACH_SLIMBUS5_TX,
135 [25] = DMACH_SLIMBUS0AUX_RX,
136 [26] = DMACH_SLIMBUS0AUX_TX,
137 [27] = DMACH_SPDIF,
138 [28] = DMACH_MAX,
139 [29] = DMACH_MAX,
140 [30] = DMACH_MAX,
141 [31] = DMACH_MAX,
142 },
143};
144
145static struct platform_device s5pv310_device_pdma1 = {
146 .name = "s3c-pl330",
147 .id = 1,
148 .num_resources = ARRAY_SIZE(s5pv310_pdma1_resource),
149 .resource = s5pv310_pdma1_resource,
150 .dev = {
151 .dma_mask = &dma_dmamask,
152 .coherent_dma_mask = DMA_BIT_MASK(32),
153 .platform_data = &s5pv310_pdma1_pdata,
154 },
155};
156
157static struct platform_device *s5pv310_dmacs[] __initdata = {
158 &s5pv310_device_pdma0,
159 &s5pv310_device_pdma1,
160};
161
162static int __init s5pv310_dma_init(void)
163{
164 platform_add_devices(s5pv310_dmacs, ARRAY_SIZE(s5pv310_dmacs));
165
166 return 0;
167}
168arch_initcall(s5pv310_dma_init);
diff --git a/arch/arm/mach-s5pv310/include/mach/dma.h b/arch/arm/mach-s5pv310/include/mach/dma.h
new file mode 100644
index 000000000000..81209eb1409b
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/dma.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common S3C DMA API driver for PL330 */
24#include <plat/s3c-dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h
index 99e7dad8a85a..1dd130a34782 100644
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv310/include/mach/irqs.h
@@ -25,6 +25,8 @@
25 25
26#define IRQ_SPI(x) S5P_IRQ(x+32) 26#define IRQ_SPI(x) S5P_IRQ(x+32)
27 27
28#define IRQ_MCT1 IRQ_SPI(35)
29
28#define IRQ_EINT0 IRQ_SPI(40) 30#define IRQ_EINT0 IRQ_SPI(40)
29#define IRQ_EINT1 IRQ_SPI(41) 31#define IRQ_EINT1 IRQ_SPI(41)
30#define IRQ_EINT2 IRQ_SPI(42) 32#define IRQ_EINT2 IRQ_SPI(42)
@@ -36,9 +38,8 @@
36#define IRQ_JPEG IRQ_SPI(48) 38#define IRQ_JPEG IRQ_SPI(48)
37#define IRQ_2D IRQ_SPI(49) 39#define IRQ_2D IRQ_SPI(49)
38#define IRQ_PCIE IRQ_SPI(50) 40#define IRQ_PCIE IRQ_SPI(50)
39#define IRQ_SYSTEM_TIMER IRQ_SPI(51) 41#define IRQ_MCT0 IRQ_SPI(51)
40#define IRQ_MFC IRQ_SPI(52) 42#define IRQ_MFC IRQ_SPI(52)
41#define IRQ_WDT IRQ_SPI(53)
42#define IRQ_AUDIO_SS IRQ_SPI(54) 43#define IRQ_AUDIO_SS IRQ_SPI(54)
43#define IRQ_AC97 IRQ_SPI(55) 44#define IRQ_AC97 IRQ_SPI(55)
44#define IRQ_SPDIF IRQ_SPI(56) 45#define IRQ_SPDIF IRQ_SPI(56)
@@ -54,6 +55,9 @@
54#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64)) 55#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64))
55#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) 56#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
56 57
58#define IRQ_PDMA0 COMBINER_IRQ(21, 0)
59#define IRQ_PDMA1 COMBINER_IRQ(21, 1)
60
57#define IRQ_TIMER0_VIC COMBINER_IRQ(22, 0) 61#define IRQ_TIMER0_VIC COMBINER_IRQ(22, 0)
58#define IRQ_TIMER1_VIC COMBINER_IRQ(22, 1) 62#define IRQ_TIMER1_VIC COMBINER_IRQ(22, 1)
59#define IRQ_TIMER2_VIC COMBINER_IRQ(22, 2) 63#define IRQ_TIMER2_VIC COMBINER_IRQ(22, 2)
@@ -83,8 +87,13 @@
83#define IRQ_HSMMC2 COMBINER_IRQ(29, 2) 87#define IRQ_HSMMC2 COMBINER_IRQ(29, 2)
84#define IRQ_HSMMC3 COMBINER_IRQ(29, 3) 88#define IRQ_HSMMC3 COMBINER_IRQ(29, 3)
85 89
90#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0)
91#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1)
92
86#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0) 93#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
87 94
95#define IRQ_MCT_L1 COMBINER_IRQ(35, 3)
96
88#define IRQ_EINT4 COMBINER_IRQ(37, 0) 97#define IRQ_EINT4 COMBINER_IRQ(37, 0)
89#define IRQ_EINT5 COMBINER_IRQ(37, 1) 98#define IRQ_EINT5 COMBINER_IRQ(37, 1)
90#define IRQ_EINT6 COMBINER_IRQ(37, 2) 99#define IRQ_EINT6 COMBINER_IRQ(37, 2)
@@ -101,7 +110,11 @@
101 110
102#define IRQ_EINT16_31 COMBINER_IRQ(39, 0) 111#define IRQ_EINT16_31 COMBINER_IRQ(39, 0)
103 112
104#define MAX_COMBINER_NR 40 113#define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
114
115#define IRQ_WDT COMBINER_IRQ(53, 0)
116
117#define MAX_COMBINER_NR 54
105 118
106#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) 119#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
107 120
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index 7acf4e77e92e..33bcff2a9568 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -39,11 +39,15 @@
39#define S5PV310_PA_SYSCON (0x10010000) 39#define S5PV310_PA_SYSCON (0x10010000)
40#define S5P_PA_SYSCON S5PV310_PA_SYSCON 40#define S5P_PA_SYSCON S5PV310_PA_SYSCON
41 41
42#define S5PV310_PA_PMU (0x10020000)
43
42#define S5PV310_PA_CMU (0x10030000) 44#define S5PV310_PA_CMU (0x10030000)
43 45
44#define S5PV310_PA_WATCHDOG (0x10060000) 46#define S5PV310_PA_WATCHDOG (0x10060000)
45#define S5PV310_PA_RTC (0x10070000) 47#define S5PV310_PA_RTC (0x10070000)
46 48
49#define S5PV310_PA_DMC0 (0x10400000)
50
47#define S5PV310_PA_COMBINER (0x10448000) 51#define S5PV310_PA_COMBINER (0x10448000)
48 52
49#define S5PV310_PA_COREPERI (0x10500000) 53#define S5PV310_PA_COREPERI (0x10500000)
@@ -52,13 +56,38 @@
52#define S5PV310_PA_GIC_DIST (0x10501000) 56#define S5PV310_PA_GIC_DIST (0x10501000)
53#define S5PV310_PA_L2CC (0x10502000) 57#define S5PV310_PA_L2CC (0x10502000)
54 58
59/* DMA */
60#define S5PV310_PA_MDMA 0x10810000
61#define S5PV310_PA_PDMA0 0x12680000
62#define S5PV310_PA_PDMA1 0x12690000
63
55#define S5PV310_PA_GPIO1 (0x11400000) 64#define S5PV310_PA_GPIO1 (0x11400000)
56#define S5PV310_PA_GPIO2 (0x11000000) 65#define S5PV310_PA_GPIO2 (0x11000000)
57#define S5PV310_PA_GPIO3 (0x03860000) 66#define S5PV310_PA_GPIO3 (0x03860000)
58 67
68#define S5PV310_PA_MIPI_CSIS0 0x11880000
69#define S5PV310_PA_MIPI_CSIS1 0x11890000
70
59#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) 71#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
60 72
61#define S5PV310_PA_SROMC (0x12570000) 73#define S5PV310_PA_SROMC (0x12570000)
74#define S5P_PA_SROMC S5PV310_PA_SROMC
75
76/* S/PDIF */
77#define S5PV310_PA_SPDIF 0xE1100000
78
79/* I2S */
80#define S5PV310_PA_I2S0 0x03830000
81#define S5PV310_PA_I2S1 0xE3100000
82#define S5PV310_PA_I2S2 0xE2A00000
83
84/* PCM */
85#define S5PV310_PA_PCM0 0x03840000
86#define S5PV310_PA_PCM1 0x13980000
87#define S5PV310_PA_PCM2 0x13990000
88
89/* AC97 */
90#define S5PV310_PA_AC97 0x139A0000
62 91
63#define S5PV310_PA_UART (0x13800000) 92#define S5PV310_PA_UART (0x13800000)
64 93
@@ -95,5 +124,7 @@
95#define S3C_PA_IIC7 S5PV310_PA_IIC(7) 124#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
96#define S3C_PA_RTC S5PV310_PA_RTC 125#define S3C_PA_RTC S5PV310_PA_RTC
97#define S3C_PA_WDT S5PV310_PA_WATCHDOG 126#define S3C_PA_WDT S5PV310_PA_WATCHDOG
127#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0
128#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1
98 129
99#endif /* __ASM_ARCH_MAP_H */ 130#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
index f1028cad9788..b5c4ada1cff5 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
@@ -19,6 +19,12 @@
19 19
20#define S5P_INFORM0 S5P_CLKREG(0x800) 20#define S5P_INFORM0 S5P_CLKREG(0x800)
21 21
22#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500)
23#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600)
24
25#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500)
26#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
27
22#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) 28#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
23#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) 29#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
24#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) 30#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
@@ -58,6 +64,8 @@
58#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) 64#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
59#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) 65#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
60 66
67#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
68
61#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920) 69#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
62#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930) 70#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
63#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) 71#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
@@ -66,8 +74,9 @@
66#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) 74#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
67#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960) 75#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
68 76
69#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200) 77#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200)
70#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500) 78#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500)
79#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600)
71 80
72#define S5P_APLL_LOCK S5P_CLKREG(0x14000) 81#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
73#define S5P_MPLL_LOCK S5P_CLKREG(0x14004) 82#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
@@ -80,10 +89,77 @@
80#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) 89#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
81 90
82#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500) 91#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
92#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504)
83#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600) 93#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
94#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604)
84 95
85#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) 96#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
86 97
98/* APLL_LOCK */
99#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */
100
101/* APLL_CON0 */
102#define S5P_APLLCON0_ENABLE_SHIFT (31)
103#define S5P_APLLCON0_LOCKED_SHIFT (29)
104#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
105#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
106
107/* CLK_SRC_CPU */
108#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
109#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
110
111/* CLKDIV_CPU0 */
112#define S5P_CLKDIV_CPU0_CORE_SHIFT (0)
113#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
114#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4)
115#define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
116#define S5P_CLKDIV_CPU0_COREM1_SHIFT (8)
117#define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
118#define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12)
119#define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
120#define S5P_CLKDIV_CPU0_ATB_SHIFT (16)
121#define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
122#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
123#define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
124#define S5P_CLKDIV_CPU0_APLL_SHIFT (24)
125#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
126
127/* CLKDIV_DMC0 */
128#define S5P_CLKDIV_DMC0_ACP_SHIFT (0)
129#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
130#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
131#define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
132#define S5P_CLKDIV_DMC0_DPHY_SHIFT (8)
133#define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
134#define S5P_CLKDIV_DMC0_DMC_SHIFT (12)
135#define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
136#define S5P_CLKDIV_DMC0_DMCD_SHIFT (16)
137#define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
138#define S5P_CLKDIV_DMC0_DMCP_SHIFT (20)
139#define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
140#define S5P_CLKDIV_DMC0_COPY2_SHIFT (24)
141#define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
142#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28)
143#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
144
145/* CLKDIV_TOP */
146#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0)
147#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
148#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4)
149#define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
150#define S5P_CLKDIV_TOP_ACLK160_SHIFT (8)
151#define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
152#define S5P_CLKDIV_TOP_ACLK133_SHIFT (12)
153#define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
154#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16)
155#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
156
157/* CLKDIV_LEFTBUS / CLKDIV_RIGHTBUS*/
158#define S5P_CLKDIV_BUS_GDLR_SHIFT (0)
159#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
160#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
161#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
162
87/* Compatibility defines */ 163/* Compatibility defines */
88 164
89#define S5P_EPLL_CON S5P_EPLL_CON0 165#define S5P_EPLL_CON S5P_EPLL_CON0
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-mem.h b/arch/arm/mach-s5pv310/include/mach/regs-mem.h
new file mode 100644
index 000000000000..834227140eaa
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/regs-mem.h
@@ -0,0 +1,23 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-mem.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - SROMC and DMC register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_MEM_H
14#define __ASM_ARCH_REGS_MEM_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_DMC0_MEMCON_OFFSET 0x04
19
20#define S5P_DMC0_MEMTYPE_SHIFT 8
21#define S5P_DMC0_MEMTYPE_MASK 0xF
22
23#endif /* __ASM_ARCH_REGS_MEM_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h b/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
new file mode 100644
index 000000000000..fb333d0f6073
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
@@ -0,0 +1,30 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - Power management unit definition
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_PMU_H
14#define __ASM_ARCH_REGS_PMU_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
19
20#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
21#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
22#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
23#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
24#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
25#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
26#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
27
28#define S5P_INT_LOCAL_PWR_EN 0x7
29
30#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-srom.h b/arch/arm/mach-s5pv310/include/mach/regs-srom.h
deleted file mode 100644
index 1898b3e10550..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-srom.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-srom.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - SROMC register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_SROM_H
14#define __ASM_ARCH_REGS_SROM_H __FILE__
15
16#include <mach/map.h>
17
18#define S5PV310_SROMREG(x) (S5P_VA_SROMC + (x))
19
20#define S5PV310_SROM_BW S5PV310_SROMREG(0x0)
21#define S5PV310_SROM_BC0 S5PV310_SROMREG(0x4)
22#define S5PV310_SROM_BC1 S5PV310_SROMREG(0x8)
23#define S5PV310_SROM_BC2 S5PV310_SROMREG(0xc)
24#define S5PV310_SROM_BC3 S5PV310_SROMREG(0x10)
25
26/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
27
28#define S5PV310_SROM_BW__DATAWIDTH__SHIFT 0
29#define S5PV310_SROM_BW__ADDRMODE__SHIFT 1
30#define S5PV310_SROM_BW__WAITENABLE__SHIFT 2
31#define S5PV310_SROM_BW__BYTEENABLE__SHIFT 3
32
33#define S5PV310_SROM_BW__CS_MASK 0xf
34
35#define S5PV310_SROM_BW__NCS0__SHIFT 0
36#define S5PV310_SROM_BW__NCS1__SHIFT 4
37#define S5PV310_SROM_BW__NCS2__SHIFT 8
38#define S5PV310_SROM_BW__NCS3__SHIFT 12
39
40/* applies to same to BCS0 - BCS3 */
41
42#define S5PV310_SROM_BCX__PMC__SHIFT 0
43#define S5PV310_SROM_BCX__TACP__SHIFT 4
44#define S5PV310_SROM_BCX__TCAH__SHIFT 8
45#define S5PV310_SROM_BCX__TCOH__SHIFT 12
46#define S5PV310_SROM_BCX__TACC__SHIFT 16
47#define S5PV310_SROM_BCX__TCOS__SHIFT 24
48#define S5PV310_SROM_BCX__TACS__SHIFT 28
49
50#endif /* __ASM_ARCH_REGS_SROM_H */
diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-s5pv310/irq-combiner.c
index 9cdd1e4d4a40..1ea4a9e83bbe 100644
--- a/arch/arm/mach-s5pv310/irq-combiner.c
+++ b/arch/arm/mach-s5pv310/irq-combiner.c
@@ -24,6 +24,7 @@ static DEFINE_SPINLOCK(irq_controller_lock);
24 24
25struct combiner_chip_data { 25struct combiner_chip_data {
26 unsigned int irq_offset; 26 unsigned int irq_offset;
27 unsigned int irq_mask;
27 void __iomem *base; 28 void __iomem *base;
28}; 29};
29 30
@@ -64,6 +65,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
64 spin_lock(&irq_controller_lock); 65 spin_lock(&irq_controller_lock);
65 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); 66 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
66 spin_unlock(&irq_controller_lock); 67 spin_unlock(&irq_controller_lock);
68 status &= chip_data->irq_mask;
67 69
68 if (status == 0) 70 if (status == 0)
69 goto out; 71 goto out;
@@ -106,10 +108,12 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
106 108
107 combiner_data[combiner_nr].base = base; 109 combiner_data[combiner_nr].base = base;
108 combiner_data[combiner_nr].irq_offset = irq_start; 110 combiner_data[combiner_nr].irq_offset = irq_start;
111 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
109 112
110 /* Disable all interrupts */ 113 /* Disable all interrupts */
111 114
112 __raw_writel(0xffffffff, base + COMBINER_ENABLE_CLEAR); 115 __raw_writel(combiner_data[combiner_nr].irq_mask,
116 base + COMBINER_ENABLE_CLEAR);
113 117
114 /* Setup the Linux IRQ subsystem */ 118 /* Setup the Linux IRQ subsystem */
115 119
diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c
index 2b8d4fc52d7c..9262966cd269 100644
--- a/arch/arm/mach-s5pv310/mach-smdkc210.c
+++ b/arch/arm/mach-s5pv310/mach-smdkc210.c
@@ -14,18 +14,21 @@
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/smsc911x.h> 15#include <linux/smsc911x.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/i2c.h>
17 18
18#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
19#include <asm/mach-types.h> 20#include <asm/mach-types.h>
20 21
21#include <plat/regs-serial.h> 22#include <plat/regs-serial.h>
23#include <plat/regs-srom.h>
22#include <plat/s5pv310.h> 24#include <plat/s5pv310.h>
23#include <plat/cpu.h> 25#include <plat/cpu.h>
24#include <plat/devs.h> 26#include <plat/devs.h>
25#include <plat/sdhci.h> 27#include <plat/sdhci.h>
28#include <plat/iic.h>
29#include <plat/pd.h>
26 30
27#include <mach/map.h> 31#include <mach/map.h>
28#include <mach/regs-srom.h>
29 32
30/* Following are default values for UCON, ULCON and UFCON UART registers */ 33/* Following are default values for UCON, ULCON and UFCON UART registers */
31#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 34#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -139,13 +142,27 @@ static struct platform_device smdkc210_smsc911x = {
139 }, 142 },
140}; 143};
141 144
145static struct i2c_board_info i2c_devs1[] __initdata = {
146 {I2C_BOARD_INFO("wm8994", 0x1a),},
147};
148
142static struct platform_device *smdkc210_devices[] __initdata = { 149static struct platform_device *smdkc210_devices[] __initdata = {
143 &s3c_device_hsmmc0, 150 &s3c_device_hsmmc0,
144 &s3c_device_hsmmc1, 151 &s3c_device_hsmmc1,
145 &s3c_device_hsmmc2, 152 &s3c_device_hsmmc2,
146 &s3c_device_hsmmc3, 153 &s3c_device_hsmmc3,
154 &s3c_device_i2c1,
147 &s3c_device_rtc, 155 &s3c_device_rtc,
148 &s3c_device_wdt, 156 &s3c_device_wdt,
157 &s5pv310_device_ac97,
158 &s5pv310_device_i2s0,
159 &s5pv310_device_pd[PD_MFC],
160 &s5pv310_device_pd[PD_G3D],
161 &s5pv310_device_pd[PD_LCD0],
162 &s5pv310_device_pd[PD_LCD1],
163 &s5pv310_device_pd[PD_CAM],
164 &s5pv310_device_pd[PD_TV],
165 &s5pv310_device_pd[PD_GPS],
149 &smdkc210_smsc911x, 166 &smdkc210_smsc911x,
150}; 167};
151 168
@@ -154,23 +171,22 @@ static void __init smdkc210_smsc911x_init(void)
154 u32 cs1; 171 u32 cs1;
155 172
156 /* configure nCS1 width to 16 bits */ 173 /* configure nCS1 width to 16 bits */
157 cs1 = __raw_readl(S5PV310_SROM_BW) & 174 cs1 = __raw_readl(S5P_SROM_BW) &
158 ~(S5PV310_SROM_BW__CS_MASK << 175 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
159 S5PV310_SROM_BW__NCS1__SHIFT); 176 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
160 cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) | 177 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
161 (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) | 178 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
162 (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) << 179 S5P_SROM_BW__NCS1__SHIFT;
163 S5PV310_SROM_BW__NCS1__SHIFT; 180 __raw_writel(cs1, S5P_SROM_BW);
164 __raw_writel(cs1, S5PV310_SROM_BW);
165 181
166 /* set timing for nCS1 suitable for ethernet chip */ 182 /* set timing for nCS1 suitable for ethernet chip */
167 __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) | 183 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
168 (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) | 184 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
169 (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) | 185 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
170 (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) | 186 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
171 (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) | 187 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
172 (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) | 188 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
173 (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1); 189 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
174} 190}
175 191
176static void __init smdkc210_map_io(void) 192static void __init smdkc210_map_io(void)
@@ -182,6 +198,9 @@ static void __init smdkc210_map_io(void)
182 198
183static void __init smdkc210_machine_init(void) 199static void __init smdkc210_machine_init(void)
184{ 200{
201 s3c_i2c1_set_platdata(NULL);
202 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
203
185 smdkc210_smsc911x_init(); 204 smdkc210_smsc911x_init();
186 205
187 s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata); 206 s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c
index 35826d66632c..3eb029ca2073 100644
--- a/arch/arm/mach-s5pv310/mach-smdkv310.c
+++ b/arch/arm/mach-s5pv310/mach-smdkv310.c
@@ -14,18 +14,21 @@
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/smsc911x.h> 15#include <linux/smsc911x.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/i2c.h>
17 18
18#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
19#include <asm/mach-types.h> 20#include <asm/mach-types.h>
20 21
21#include <plat/regs-serial.h> 22#include <plat/regs-serial.h>
23#include <plat/regs-srom.h>
22#include <plat/s5pv310.h> 24#include <plat/s5pv310.h>
23#include <plat/cpu.h> 25#include <plat/cpu.h>
24#include <plat/devs.h> 26#include <plat/devs.h>
25#include <plat/sdhci.h> 27#include <plat/sdhci.h>
28#include <plat/iic.h>
29#include <plat/pd.h>
26 30
27#include <mach/map.h> 31#include <mach/map.h>
28#include <mach/regs-srom.h>
29 32
30/* Following are default values for UCON, ULCON and UFCON UART registers */ 33/* Following are default values for UCON, ULCON and UFCON UART registers */
31#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 34#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -139,13 +142,27 @@ static struct platform_device smdkv310_smsc911x = {
139 }, 142 },
140}; 143};
141 144
145static struct i2c_board_info i2c_devs1[] __initdata = {
146 {I2C_BOARD_INFO("wm8994", 0x1a),},
147};
148
142static struct platform_device *smdkv310_devices[] __initdata = { 149static struct platform_device *smdkv310_devices[] __initdata = {
143 &s3c_device_hsmmc0, 150 &s3c_device_hsmmc0,
144 &s3c_device_hsmmc1, 151 &s3c_device_hsmmc1,
145 &s3c_device_hsmmc2, 152 &s3c_device_hsmmc2,
146 &s3c_device_hsmmc3, 153 &s3c_device_hsmmc3,
154 &s3c_device_i2c1,
147 &s3c_device_rtc, 155 &s3c_device_rtc,
148 &s3c_device_wdt, 156 &s3c_device_wdt,
157 &s5pv310_device_ac97,
158 &s5pv310_device_i2s0,
159 &s5pv310_device_pd[PD_MFC],
160 &s5pv310_device_pd[PD_G3D],
161 &s5pv310_device_pd[PD_LCD0],
162 &s5pv310_device_pd[PD_LCD1],
163 &s5pv310_device_pd[PD_CAM],
164 &s5pv310_device_pd[PD_TV],
165 &s5pv310_device_pd[PD_GPS],
149 &smdkv310_smsc911x, 166 &smdkv310_smsc911x,
150}; 167};
151 168
@@ -154,23 +171,22 @@ static void __init smdkv310_smsc911x_init(void)
154 u32 cs1; 171 u32 cs1;
155 172
156 /* configure nCS1 width to 16 bits */ 173 /* configure nCS1 width to 16 bits */
157 cs1 = __raw_readl(S5PV310_SROM_BW) & 174 cs1 = __raw_readl(S5P_SROM_BW) &
158 ~(S5PV310_SROM_BW__CS_MASK << 175 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
159 S5PV310_SROM_BW__NCS1__SHIFT); 176 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
160 cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) | 177 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
161 (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) | 178 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
162 (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) << 179 S5P_SROM_BW__NCS1__SHIFT;
163 S5PV310_SROM_BW__NCS1__SHIFT; 180 __raw_writel(cs1, S5P_SROM_BW);
164 __raw_writel(cs1, S5PV310_SROM_BW);
165 181
166 /* set timing for nCS1 suitable for ethernet chip */ 182 /* set timing for nCS1 suitable for ethernet chip */
167 __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) | 183 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
168 (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) | 184 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
169 (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) | 185 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
170 (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) | 186 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
171 (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) | 187 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
172 (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) | 188 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
173 (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1); 189 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
174} 190}
175 191
176static void __init smdkv310_map_io(void) 192static void __init smdkv310_map_io(void)
@@ -182,6 +198,9 @@ static void __init smdkv310_map_io(void)
182 198
183static void __init smdkv310_machine_init(void) 199static void __init smdkv310_machine_init(void)
184{ 200{
201 s3c_i2c1_set_platdata(NULL);
202 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
203
185 smdkv310_smsc911x_init(); 204 smdkv310_smsc911x_init();
186 205
187 s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata); 206 s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c
index 16d8fc00cafd..36bc3cf825e3 100644
--- a/arch/arm/mach-s5pv310/mach-universal_c210.c
+++ b/arch/arm/mach-s5pv310/mach-universal_c210.c
@@ -13,6 +13,9 @@
13#include <linux/i2c.h> 13#include <linux/i2c.h>
14#include <linux/gpio_keys.h> 14#include <linux/gpio_keys.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/regulator/machine.h>
17#include <linux/regulator/fixed.h>
18#include <linux/mmc/host.h>
16 19
17#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
18#include <asm/mach-types.h> 21#include <asm/mach-types.h>
@@ -21,6 +24,7 @@
21#include <plat/s5pv310.h> 24#include <plat/s5pv310.h>
22#include <plat/cpu.h> 25#include <plat/cpu.h>
23#include <plat/devs.h> 26#include <plat/devs.h>
27#include <plat/sdhci.h>
24 28
25#include <mach/map.h> 29#include <mach/map.h>
26 30
@@ -116,6 +120,73 @@ static struct platform_device universal_gpio_keys = {
116 }, 120 },
117}; 121};
118 122
123/* eMMC */
124static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
125 .max_width = 8,
126 .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
127 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
128 MMC_CAP_DISABLE),
129 .cd_type = S3C_SDHCI_CD_PERMANENT,
130 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
131};
132
133static struct regulator_consumer_supply mmc0_supplies[] = {
134 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
135};
136
137static struct regulator_init_data mmc0_fixed_voltage_init_data = {
138 .constraints = {
139 .name = "VMEM_VDD_2.8V",
140 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
141 },
142 .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
143 .consumer_supplies = mmc0_supplies,
144};
145
146static struct fixed_voltage_config mmc0_fixed_voltage_config = {
147 .supply_name = "MASSMEMORY_EN",
148 .microvolts = 2800000,
149 .gpio = S5PV310_GPE1(3),
150 .enable_high = true,
151 .init_data = &mmc0_fixed_voltage_init_data,
152};
153
154static struct platform_device mmc0_fixed_voltage = {
155 .name = "reg-fixed-voltage",
156 .id = 0,
157 .dev = {
158 .platform_data = &mmc0_fixed_voltage_config,
159 },
160};
161
162/* SD */
163static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
164 .max_width = 4,
165 .host_caps = MMC_CAP_4_BIT_DATA |
166 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
167 MMC_CAP_DISABLE,
168 .ext_cd_gpio = S5PV310_GPX3(4), /* XEINT_28 */
169 .ext_cd_gpio_invert = 1,
170 .cd_type = S3C_SDHCI_CD_GPIO,
171 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
172};
173
174/* WiFi */
175static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
176 .max_width = 4,
177 .host_caps = MMC_CAP_4_BIT_DATA |
178 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
179 MMC_CAP_DISABLE,
180 .cd_type = S3C_SDHCI_CD_EXTERNAL,
181};
182
183static void __init universal_sdhci_init(void)
184{
185 s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
186 s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
187 s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
188}
189
119/* I2C0 */ 190/* I2C0 */
120static struct i2c_board_info i2c0_devs[] __initdata = { 191static struct i2c_board_info i2c0_devs[] __initdata = {
121 /* Camera, To be updated */ 192 /* Camera, To be updated */
@@ -127,6 +198,13 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
127}; 198};
128 199
129static struct platform_device *universal_devices[] __initdata = { 200static struct platform_device *universal_devices[] __initdata = {
201 /* Samsung Platform Devices */
202 &mmc0_fixed_voltage,
203 &s3c_device_hsmmc0,
204 &s3c_device_hsmmc2,
205 &s3c_device_hsmmc3,
206
207 /* Universal Devices */
130 &universal_gpio_keys, 208 &universal_gpio_keys,
131 &s5p_device_onenand, 209 &s5p_device_onenand,
132}; 210};
@@ -140,6 +218,8 @@ static void __init universal_map_io(void)
140 218
141static void __init universal_machine_init(void) 219static void __init universal_machine_init(void)
142{ 220{
221 universal_sdhci_init();
222
143 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); 223 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
144 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); 224 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
145 225
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 65dbfa8e0a86..6a161f317a79 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -56,3 +56,13 @@ config S5P_DEV_ONENAND
56 bool 56 bool
57 help 57 help
58 Compile in platform device definition for OneNAND controller 58 Compile in platform device definition for OneNAND controller
59
60config S5P_DEV_CSIS0
61 bool
62 help
63 Compile in platform device definitions for MIPI-CSIS channel 0
64
65config S5P_DEV_CSIS1
66 bool
67 help
68 Compile in platform device definitions for MIPI-CSIS channel 1
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index de65238a7aef..2b7317378103 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -28,3 +28,5 @@ obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o
28obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o 28obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o
29obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o 29obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o
30obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o 30obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o
31obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o
32obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index 74f7f5a5446c..047d31c1bbd8 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -108,6 +108,11 @@ static struct map_desc s5p_iodesc[] __initdata = {
108 .pfn = __phys_to_pfn(S3C_PA_WDT), 108 .pfn = __phys_to_pfn(S3C_PA_WDT),
109 .length = SZ_4K, 109 .length = SZ_4K,
110 .type = MT_DEVICE, 110 .type = MT_DEVICE,
111 }, {
112 .virtual = (unsigned long)S5P_VA_SROMC,
113 .pfn = __phys_to_pfn(S5P_PA_SROMC),
114 .length = SZ_4K,
115 .type = MT_DEVICE,
111 }, 116 },
112}; 117};
113 118
diff --git a/arch/arm/plat-s5p/dev-csis0.c b/arch/arm/plat-s5p/dev-csis0.c
new file mode 100644
index 000000000000..dfab1c85f54f
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-csis0.c
@@ -0,0 +1,34 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics
3 *
4 * S5P series device definition for MIPI-CSIS channel 0
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/interrupt.h>
13#include <linux/platform_device.h>
14#include <mach/map.h>
15
16static struct resource s5p_mipi_csis0_resource[] = {
17 [0] = {
18 .start = S5P_PA_MIPI_CSIS0,
19 .end = S5P_PA_MIPI_CSIS0 + SZ_4K - 1,
20 .flags = IORESOURCE_MEM,
21 },
22 [1] = {
23 .start = IRQ_MIPI_CSIS0,
24 .end = IRQ_MIPI_CSIS0,
25 .flags = IORESOURCE_IRQ,
26 }
27};
28
29struct platform_device s5p_device_mipi_csis0 = {
30 .name = "s5p-mipi-csis",
31 .id = 0,
32 .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
33 .resource = s5p_mipi_csis0_resource,
34};
diff --git a/arch/arm/plat-s5p/dev-csis1.c b/arch/arm/plat-s5p/dev-csis1.c
new file mode 100644
index 000000000000..e3053f27fbbf
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-csis1.c
@@ -0,0 +1,34 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics
3 *
4 * S5P series device definition for MIPI-CSIS channel 1
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/interrupt.h>
13#include <linux/platform_device.h>
14#include <mach/map.h>
15
16static struct resource s5p_mipi_csis1_resource[] = {
17 [0] = {
18 .start = S5P_PA_MIPI_CSIS1,
19 .end = S5P_PA_MIPI_CSIS1 + SZ_4K - 1,
20 .flags = IORESOURCE_MEM,
21 },
22 [1] = {
23 .start = IRQ_MIPI_CSIS1,
24 .end = IRQ_MIPI_CSIS1,
25 .flags = IORESOURCE_IRQ,
26 },
27};
28
29struct platform_device s5p_device_mipi_csis1 = {
30 .name = "s5p-mipi-csis",
31 .id = 1,
32 .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
33 .resource = s5p_mipi_csis1_resource,
34};
diff --git a/arch/arm/plat-s5p/include/plat/csis.h b/arch/arm/plat-s5p/include/plat/csis.h
new file mode 100644
index 000000000000..51e308c7981d
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/csis.h
@@ -0,0 +1,28 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics
3 *
4 * S5P series MIPI CSI slave device support
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef PLAT_S5P_CSIS_H_
12#define PLAT_S5P_CSIS_H_ __FILE__
13
14/**
15 * struct s5p_platform_mipi_csis - platform data for MIPI-CSIS
16 * @clk_rate: bus clock frequency
17 * @lanes: number of data lanes used
18 * @alignment: data alignment in bits
19 * @hs_settle: HS-RX settle time
20 */
21struct s5p_platform_mipi_csis {
22 unsigned long clk_rate;
23 u8 lanes;
24 u8 alignment;
25 u8 hs_settle;
26};
27
28#endif /* PLAT_S5P_CSIS_H_ */
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h
index fef353d44513..d973d39666a3 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-s5p/include/plat/map-s5p.h
@@ -15,6 +15,7 @@
15 15
16#define S5P_VA_CHIPID S3C_ADDR(0x02000000) 16#define S5P_VA_CHIPID S3C_ADDR(0x02000000)
17#define S5P_VA_CMU S3C_ADDR(0x02100000) 17#define S5P_VA_CMU S3C_ADDR(0x02100000)
18#define S5P_VA_PMU S3C_ADDR(0x02180000)
18#define S5P_VA_GPIO S3C_ADDR(0x02200000) 19#define S5P_VA_GPIO S3C_ADDR(0x02200000)
19#define S5P_VA_GPIO1 S5P_VA_GPIO 20#define S5P_VA_GPIO1 S5P_VA_GPIO
20#define S5P_VA_GPIO2 S3C_ADDR(0x02240000) 21#define S5P_VA_GPIO2 S3C_ADDR(0x02240000)
diff --git a/arch/arm/plat-s5p/include/plat/regs-srom.h b/arch/arm/plat-s5p/include/plat/regs-srom.h
new file mode 100644
index 000000000000..f121ab5e76cb
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/regs-srom.h
@@ -0,0 +1,54 @@
1/* linux/arch/arm/plat-s5p/include/plat/regs-srom.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P SROMC register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_S5P_REGS_SROM_H
14#define __ASM_PLAT_S5P_REGS_SROM_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_SROMREG(x) (S5P_VA_SROMC + (x))
19
20#define S5P_SROM_BW S5P_SROMREG(0x0)
21#define S5P_SROM_BC0 S5P_SROMREG(0x4)
22#define S5P_SROM_BC1 S5P_SROMREG(0x8)
23#define S5P_SROM_BC2 S5P_SROMREG(0xc)
24#define S5P_SROM_BC3 S5P_SROMREG(0x10)
25#define S5P_SROM_BC4 S5P_SROMREG(0x14)
26#define S5P_SROM_BC5 S5P_SROMREG(0x18)
27
28/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
29
30#define S5P_SROM_BW__DATAWIDTH__SHIFT 0
31#define S5P_SROM_BW__ADDRMODE__SHIFT 1
32#define S5P_SROM_BW__WAITENABLE__SHIFT 2
33#define S5P_SROM_BW__BYTEENABLE__SHIFT 3
34
35#define S5P_SROM_BW__CS_MASK 0xf
36
37#define S5P_SROM_BW__NCS0__SHIFT 0
38#define S5P_SROM_BW__NCS1__SHIFT 4
39#define S5P_SROM_BW__NCS2__SHIFT 8
40#define S5P_SROM_BW__NCS3__SHIFT 12
41#define S5P_SROM_BW__NCS4__SHIFT 16
42#define S5P_SROM_BW__NCS5__SHIFT 20
43
44/* applies to same to BCS0 - BCS3 */
45
46#define S5P_SROM_BCX__PMC__SHIFT 0
47#define S5P_SROM_BCX__TACP__SHIFT 4
48#define S5P_SROM_BCX__TCAH__SHIFT 8
49#define S5P_SROM_BCX__TCOH__SHIFT 12
50#define S5P_SROM_BCX__TACC__SHIFT 16
51#define S5P_SROM_BCX__TCOS__SHIFT 24
52#define S5P_SROM_BCX__TACS__SHIFT 28
53
54#endif /* __ASM_PLAT_S5P_REGS_SROM_H */
diff --git a/arch/arm/plat-samsung/gpiolib.c b/arch/arm/plat-samsung/gpiolib.c
index c354089254fc..ea37c0461788 100644
--- a/arch/arm/plat-samsung/gpiolib.c
+++ b/arch/arm/plat-samsung/gpiolib.c
@@ -197,3 +197,10 @@ void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
197 s3c_gpiolib_add(chip); 197 s3c_gpiolib_add(chip);
198 } 198 }
199} 199}
200
201void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
202 int nr_chips)
203{
204 for (; nr_chips > 0; nr_chips--, chip++)
205 s3c_gpiolib_add(chip);
206}
diff --git a/arch/arm/plat-samsung/include/plat/audio.h b/arch/arm/plat-samsung/include/plat/audio.h
index 7712ff6336f4..a0826ed2f9fe 100644
--- a/arch/arm/plat-samsung/include/plat/audio.h
+++ b/arch/arm/plat-samsung/include/plat/audio.h
@@ -25,10 +25,34 @@ extern void s3c64xx_ac97_setup_gpio(int);
25#define S5PC100_SPDIF_GPG3 1 25#define S5PC100_SPDIF_GPG3 1
26extern void s5pc100_spdif_setup_gpio(int); 26extern void s5pc100_spdif_setup_gpio(int);
27 27
28struct samsung_i2s {
29/* If the Primary DAI has 5.1 Channels */
30#define QUIRK_PRI_6CHAN (1 << 0)
31/* If the I2S block has a Stereo Overlay Channel */
32#define QUIRK_SEC_DAI (1 << 1)
33/*
34 * If the I2S block has no internal prescalar or MUX (I2SMOD[10] bit)
35 * The Machine driver must provide suitably set clock to the I2S block.
36 */
37#define QUIRK_NO_MUXPSR (1 << 2)
38#define QUIRK_NEED_RSTCLR (1 << 3)
39 /* Quirks of the I2S controller */
40 u32 quirks;
41
42 /*
43 * Array of clock names that can be used to generate I2S signals.
44 * Also corresponds to clocks of I2SMOD[10]
45 */
46 const char **src_clk;
47};
48
28/** 49/**
29 * struct s3c_audio_pdata - common platform data for audio device drivers 50 * struct s3c_audio_pdata - common platform data for audio device drivers
30 * @cfg_gpio: Callback function to setup mux'ed pins in I2S/PCM/AC97 mode 51 * @cfg_gpio: Callback function to setup mux'ed pins in I2S/PCM/AC97 mode
31 */ 52 */
32struct s3c_audio_pdata { 53struct s3c_audio_pdata {
33 int (*cfg_gpio)(struct platform_device *); 54 int (*cfg_gpio)(struct platform_device *);
55 union {
56 struct samsung_i2s i2s;
57 } type;
34}; 58};
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 2d82a6cb1444..165fa8496c9e 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -96,6 +96,16 @@ extern struct platform_device s5pv210_device_iis1;
96extern struct platform_device s5pv210_device_iis2; 96extern struct platform_device s5pv210_device_iis2;
97extern struct platform_device s5pv210_device_spdif; 97extern struct platform_device s5pv210_device_spdif;
98 98
99extern struct platform_device s5pv310_device_ac97;
100extern struct platform_device s5pv310_device_pcm0;
101extern struct platform_device s5pv310_device_pcm1;
102extern struct platform_device s5pv310_device_pcm2;
103extern struct platform_device s5pv310_device_i2s0;
104extern struct platform_device s5pv310_device_i2s1;
105extern struct platform_device s5pv310_device_i2s2;
106extern struct platform_device s5pv310_device_spdif;
107extern struct platform_device s5pv310_device_pd[];
108
99extern struct platform_device s5p6442_device_pcm0; 109extern struct platform_device s5p6442_device_pcm0;
100extern struct platform_device s5p6442_device_pcm1; 110extern struct platform_device s5p6442_device_pcm1;
101extern struct platform_device s5p6442_device_iis0; 111extern struct platform_device s5p6442_device_iis0;
@@ -106,6 +116,8 @@ extern struct platform_device s5p6440_device_pcm;
106extern struct platform_device s5p6440_device_iis; 116extern struct platform_device s5p6440_device_iis;
107 117
108extern struct platform_device s5p6450_device_iis0; 118extern struct platform_device s5p6450_device_iis0;
119extern struct platform_device s5p6450_device_iis1;
120extern struct platform_device s5p6450_device_iis2;
109extern struct platform_device s5p6450_device_pcm0; 121extern struct platform_device s5p6450_device_pcm0;
110 122
111extern struct platform_device s5pc100_device_ac97; 123extern struct platform_device s5pc100_device_ac97;
@@ -122,6 +134,9 @@ extern struct platform_device s5p_device_fimc0;
122extern struct platform_device s5p_device_fimc1; 134extern struct platform_device s5p_device_fimc1;
123extern struct platform_device s5p_device_fimc2; 135extern struct platform_device s5p_device_fimc2;
124 136
137extern struct platform_device s5p_device_mipi_csis0;
138extern struct platform_device s5p_device_mipi_csis1;
139
125/* s3c2440 specific devices */ 140/* s3c2440 specific devices */
126 141
127#ifdef CONFIG_CPU_S3C2440 142#ifdef CONFIG_CPU_S3C2440
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index 13a22b8861ef..dac35d0a711d 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -118,6 +118,8 @@ extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
118 int nr_chips); 118 int nr_chips);
119extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, 119extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
120 int nr_chips); 120 int nr_chips);
121extern void samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
122 int nr_chips);
121 123
122extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip); 124extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
123extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip); 125extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 20:04:46 -0500