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-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/boot/compressed/head.S10
-rw-r--r--arch/arm/boot/compressed/misc.c12
-rw-r--r--arch/arm/common/gic.c15
-rw-r--r--arch/arm/common/it8152.c4
-rw-r--r--arch/arm/common/locomo.c17
-rw-r--r--arch/arm/common/sa1111.c24
-rw-r--r--arch/arm/common/vic.c6
-rw-r--r--arch/arm/include/asm/hw_irq.h8
-rw-r--r--arch/arm/include/asm/mach/udc_pxa2xx.h2
-rw-r--r--arch/arm/kernel/bios32.c25
-rw-r--r--arch/arm/kernel/debug.S19
-rw-r--r--arch/arm/kernel/ecard.c6
-rw-r--r--arch/arm/kernel/etm.c4
-rw-r--r--arch/arm/kernel/irq.c70
-rw-r--r--arch/arm/kernel/kprobes-decode.c10
-rw-r--r--arch/arm/kernel/perf_event.c33
-rw-r--r--arch/arm/kernel/perf_event_v6.c2
-rw-r--r--arch/arm/kernel/perf_event_v7.c26
-rw-r--r--arch/arm/kernel/perf_event_xscale.c4
-rw-r--r--arch/arm/kernel/sleep.S14
-rw-r--r--arch/arm/mach-at91/at91cap9_devices.c6
-rw-r--r--arch/arm/mach-at91/gpio.c43
-rw-r--r--arch/arm/mach-at91/include/mach/at572d940hf.h2
-rw-r--r--arch/arm/mach-at91/irq.c3
-rw-r--r--arch/arm/mach-bcmring/irq.c10
-rw-r--r--arch/arm/mach-clps711x/irq.c8
-rw-r--r--arch/arm/mach-davinci/cp_intc.c4
-rw-r--r--arch/arm/mach-davinci/gpio.c49
-rw-r--r--arch/arm/mach-davinci/irq.c6
-rw-r--r--arch/arm/mach-dove/include/mach/dove.h2
-rw-r--r--arch/arm/mach-dove/irq.c20
-rw-r--r--arch/arm/mach-dove/mpp.c3
-rw-r--r--arch/arm/mach-ebsa110/core.c4
-rw-r--r--arch/arm/mach-ep93xx/gpio.c52
-rw-r--r--arch/arm/mach-exynos4/irq-combiner.c13
-rw-r--r--arch/arm/mach-exynos4/irq-eint.c15
-rw-r--r--arch/arm/mach-footbridge/common.c3
-rw-r--r--arch/arm/mach-footbridge/dc21285-timer.c2
-rw-r--r--arch/arm/mach-footbridge/isa-irq.c10
-rw-r--r--arch/arm/mach-gemini/gpio.c14
-rw-r--r--arch/arm/mach-gemini/irq.c6
-rw-r--r--arch/arm/mach-h720x/common.c22
-rw-r--r--arch/arm/mach-h720x/cpu-h7202.c17
-rw-r--r--arch/arm/mach-imx/Kconfig1
-rw-r--r--arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c8
-rw-r--r--arch/arm/mach-iop13xx/irq.c10
-rw-r--r--arch/arm/mach-iop13xx/msi.c6
-rw-r--r--arch/arm/mach-iop32x/irq.c3
-rw-r--r--arch/arm/mach-iop33x/irq.c5
-rw-r--r--arch/arm/mach-ixp2000/core.c20
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x00.c6
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x01.c6
-rw-r--r--arch/arm/mach-ixp23xx/core.c14
-rw-r--r--arch/arm/mach-ixp23xx/ixdp2351.c12
-rw-r--r--arch/arm/mach-ixp23xx/roadrunner.c4
-rw-r--r--arch/arm/mach-ixp4xx/avila-pci.c8
-rw-r--r--arch/arm/mach-ixp4xx/common.c4
-rw-r--r--arch/arm/mach-ixp4xx/coyote-pci.c4
-rw-r--r--arch/arm/mach-ixp4xx/dsmg600-pci.c12
-rw-r--r--arch/arm/mach-ixp4xx/fsg-pci.c6
-rw-r--r--arch/arm/mach-ixp4xx/gateway7001-pci.c4
-rw-r--r--arch/arm/mach-ixp4xx/goramo_mlr.c12
-rw-r--r--arch/arm/mach-ixp4xx/gtwx5715-pci.c4
-rw-r--r--arch/arm/mach-ixp4xx/ixdp425-pci.c8
-rw-r--r--arch/arm/mach-ixp4xx/ixdpg425-pci.c4
-rw-r--r--arch/arm/mach-ixp4xx/nas100d-pci.c10
-rw-r--r--arch/arm/mach-ixp4xx/nslu2-pci.c6
-rw-r--r--arch/arm/mach-ixp4xx/vulcan-pci.c4
-rw-r--r--arch/arm/mach-ixp4xx/wg302v2-pci.c4
-rw-r--r--arch/arm/mach-kirkwood/irq.c15
-rw-r--r--arch/arm/mach-kirkwood/sheevaplug-setup.c7
-rw-r--r--arch/arm/mach-ks8695/gpio.c2
-rw-r--r--arch/arm/mach-ks8695/irq.c18
-rw-r--r--arch/arm/mach-lpc32xx/irq.c10
-rw-r--r--arch/arm/mach-mmp/irq-mmp2.c18
-rw-r--r--arch/arm/mach-mmp/irq-pxa168.c3
-rw-r--r--arch/arm/mach-msm/board-msm8960.c2
-rw-r--r--arch/arm/mach-msm/board-msm8x60.c2
-rw-r--r--arch/arm/mach-msm/board-trout-gpio.c10
-rw-r--r--arch/arm/mach-msm/board-trout-mmc.c2
-rw-r--r--arch/arm/mach-msm/gpio-v2.c49
-rw-r--r--arch/arm/mach-msm/gpio.c18
-rw-r--r--arch/arm/mach-msm/irq-vic.c7
-rw-r--r--arch/arm/mach-msm/irq.c7
-rw-r--r--arch/arm/mach-msm/sirc.c11
-rw-r--r--arch/arm/mach-mv78xx0/irq.c8
-rw-r--r--arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c14
-rw-r--r--arch/arm/mach-mx3/mach-mx31ads.c7
-rw-r--r--arch/arm/mach-mx3/mach-pcm043.c12
-rw-r--r--arch/arm/mach-mx5/Kconfig1
-rw-r--r--arch/arm/mach-mx5/Makefile2
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c5
-rw-r--r--arch/arm/mach-mx5/board-mx53_evk.c9
-rw-r--r--arch/arm/mach-mx5/board-mx53_loco.c25
-rw-r--r--arch/arm/mach-mx5/clock-mx51-mx53.c9
-rw-r--r--arch/arm/mach-mx5/cpu.c59
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c2
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c4
-rw-r--r--arch/arm/mach-mx5/mx51_efika.c1
-rw-r--r--arch/arm/mach-mx5/system.c84
-rw-r--r--arch/arm/mach-mxs/Kconfig2
-rw-r--r--arch/arm/mach-mxs/clock-mx23.c15
-rw-r--r--arch/arm/mach-mxs/clock-mx28.c18
-rw-r--r--arch/arm/mach-mxs/devices-mx23.h4
-rw-r--r--arch/arm/mach-mxs/devices-mx28.h4
-rw-r--r--arch/arm/mach-mxs/devices/Kconfig3
-rw-r--r--arch/arm/mach-mxs/devices/Makefile1
-rw-r--r--arch/arm/mach-mxs/devices/platform-mxs-mmc.c73
-rw-r--r--arch/arm/mach-mxs/gpio.c10
-rw-r--r--arch/arm/mach-mxs/icoll.c3
-rw-r--r--arch/arm/mach-mxs/include/mach/devices-common.h13
-rw-r--r--arch/arm/mach-mxs/mach-mx23evk.c44
-rw-r--r--arch/arm/mach-mxs/mach-mx28evk.c89
-rw-r--r--arch/arm/mach-mxs/module-tx28.c41
-rw-r--r--arch/arm/mach-mxs/module-tx28.h1
-rw-r--r--arch/arm/mach-netx/generic.c6
-rw-r--r--arch/arm/mach-ns9xxx/board-a9m9750dev.c8
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/board.h2
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/module.h5
-rw-r--r--arch/arm/mach-ns9xxx/irq.c3
-rw-r--r--arch/arm/mach-nuc93x/irq.c4
-rw-r--r--arch/arm/mach-omap1/board-osk.c6
-rw-r--r--arch/arm/mach-omap1/board-palmz71.c8
-rw-r--r--arch/arm/mach-omap1/board-voiceblue.c8
-rw-r--r--arch/arm/mach-omap1/fpga.c10
-rw-r--r--arch/arm/mach-omap1/irq.c4
-rw-r--r--arch/arm/mach-omap2/gpmc.c2
-rw-r--r--arch/arm/mach-omap2/irq.c3
-rw-r--r--arch/arm/mach-orion5x/db88f5281-setup.c4
-rw-r--r--arch/arm/mach-orion5x/irq.c8
-rw-r--r--arch/arm/mach-orion5x/rd88f5182-setup.c4
-rw-r--r--arch/arm/mach-orion5x/terastation_pro2-setup.c2
-rw-r--r--arch/arm/mach-orion5x/ts209-setup.c4
-rw-r--r--arch/arm/mach-orion5x/ts78xx-setup.c18
-rw-r--r--arch/arm/mach-pnx4008/irq.c10
-rw-r--r--arch/arm/mach-pxa/am200epd.c8
-rw-r--r--arch/arm/mach-pxa/am300epd.c13
-rw-r--r--arch/arm/mach-pxa/balloon3.c10
-rw-r--r--arch/arm/mach-pxa/cm-x2xx-pci.c5
-rw-r--r--arch/arm/mach-pxa/cm-x2xx.c2
-rw-r--r--arch/arm/mach-pxa/cm-x300.c4
-rw-r--r--arch/arm/mach-pxa/colibri-pxa270-income.c2
-rw-r--r--arch/arm/mach-pxa/colibri-pxa3xx.c2
-rw-r--r--arch/arm/mach-pxa/corgi.c1
-rw-r--r--arch/arm/mach-pxa/devices.c9
-rw-r--r--arch/arm/mach-pxa/em-x270.c2
-rw-r--r--arch/arm/mach-pxa/eseries.c36
-rw-r--r--arch/arm/mach-pxa/ezx.c12
-rw-r--r--arch/arm/mach-pxa/gumstix.c13
-rw-r--r--arch/arm/mach-pxa/idp.c2
-rw-r--r--arch/arm/mach-pxa/include/mach/palmz72.h5
-rw-r--r--arch/arm/mach-pxa/include/mach/pxafb.h4
-rw-r--r--arch/arm/mach-pxa/include/mach/z2.h3
-rw-r--r--arch/arm/mach-pxa/irq.c12
-rw-r--r--arch/arm/mach-pxa/littleton.c2
-rw-r--r--arch/arm/mach-pxa/lpd270.c10
-rw-r--r--arch/arm/mach-pxa/lubbock.c10
-rw-r--r--arch/arm/mach-pxa/magician.c2
-rw-r--r--arch/arm/mach-pxa/mainstone.c10
-rw-r--r--arch/arm/mach-pxa/mioa701.c2
-rw-r--r--arch/arm/mach-pxa/palm27x.c5
-rw-r--r--arch/arm/mach-pxa/palmtc.c2
-rw-r--r--arch/arm/mach-pxa/palmte2.c33
-rw-r--r--arch/arm/mach-pxa/palmz72.c127
-rw-r--r--arch/arm/mach-pxa/pcm990-baseboard.c10
-rw-r--r--arch/arm/mach-pxa/poodle.c3
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c4
-rw-r--r--arch/arm/mach-pxa/raumfeld.c2
-rw-r--r--arch/arm/mach-pxa/saar.c2
-rw-r--r--arch/arm/mach-pxa/spitz.c2
-rw-r--r--arch/arm/mach-pxa/tavorevb.c2
-rw-r--r--arch/arm/mach-pxa/time.c5
-rw-r--r--arch/arm/mach-pxa/tosa.c13
-rw-r--r--arch/arm/mach-pxa/trizeps4.c4
-rw-r--r--arch/arm/mach-pxa/viper.c10
-rw-r--r--arch/arm/mach-pxa/vpac270.c2
-rw-r--r--arch/arm/mach-pxa/z2.c77
-rw-r--r--arch/arm/mach-pxa/zeus.c21
-rw-r--r--arch/arm/mach-pxa/zylonite.c4
-rw-r--r--arch/arm/mach-realview/realview_eb.c2
-rw-r--r--arch/arm/mach-rpc/irq.c14
-rw-r--r--arch/arm/mach-s3c2410/bast-irq.c6
-rw-r--r--arch/arm/mach-s3c2412/irq.c12
-rw-r--r--arch/arm/mach-s3c2416/irq.c8
-rw-r--r--arch/arm/mach-s3c2440/irq.c10
-rw-r--r--arch/arm/mach-s3c2440/s3c244x-irq.c14
-rw-r--r--arch/arm/mach-s3c2443/irq.c8
-rw-r--r--arch/arm/mach-s3c64xx/irq-eint.c13
-rw-r--r--arch/arm/mach-sa1100/cerf.c2
-rw-r--r--arch/arm/mach-sa1100/irq.c16
-rw-r--r--arch/arm/mach-sa1100/neponset.c8
-rw-r--r--arch/arm/mach-sa1100/pleb.c2
-rw-r--r--arch/arm/mach-shark/irq.c3
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c10
-rw-r--r--arch/arm/mach-shmobile/board-g4evm.c6
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c14
-rw-r--r--arch/arm/mach-shmobile/intc-sh7367.c6
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c6
-rw-r--r--arch/arm/mach-shmobile/intc-sh7377.c6
-rw-r--r--arch/arm/mach-tcc8k/irq.c6
-rw-r--r--arch/arm/mach-tegra/gpio.c39
-rw-r--r--arch/arm/mach-tegra/irq.c5
-rw-r--r--arch/arm/mach-ux500/modem-irq-db5500.c3
-rw-r--r--arch/arm/mach-vt8500/irq.c14
-rw-r--r--arch/arm/mach-w90x900/irq.c4
-rw-r--r--arch/arm/plat-mxc/3ds_debugboard.c14
-rw-r--r--arch/arm/plat-mxc/avic.c4
-rw-r--r--arch/arm/plat-mxc/devices/platform-fec.c2
-rw-r--r--arch/arm/plat-mxc/devices/platform-imxdi_rtc.c2
-rw-r--r--arch/arm/plat-mxc/gpio.c24
-rw-r--r--arch/arm/plat-mxc/include/mach/audmux.h10
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx2x.h12
-rw-r--r--arch/arm/plat-mxc/include/mach/mx50.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx51.h1
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h23
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h6
-rw-r--r--arch/arm/plat-mxc/irq-common.c4
-rw-r--r--arch/arm/plat-mxc/time.c25
-rw-r--r--arch/arm/plat-mxc/tzic.c4
-rw-r--r--arch/arm/plat-nomadik/gpio.c57
-rw-r--r--arch/arm/plat-omap/gpio.c31
-rw-r--r--arch/arm/plat-orion/gpio.c31
-rw-r--r--arch/arm/plat-orion/irq.c8
-rw-r--r--arch/arm/plat-pxa/gpio.c6
-rw-r--r--arch/arm/plat-s3c24xx/irq.c43
-rw-r--r--arch/arm/plat-s5p/irq-eint.c7
-rw-r--r--arch/arm/plat-s5p/irq-gpioint.c22
-rw-r--r--arch/arm/plat-samsung/irq-uart.c10
-rw-r--r--arch/arm/plat-samsung/irq-vic-timer.c11
-rw-r--r--arch/arm/plat-samsung/wakeup-mask.c8
-rw-r--r--arch/arm/plat-spear/shirq.c12
-rw-r--r--arch/arm/plat-stmp3xxx/irq.c3
-rw-r--r--arch/arm/plat-stmp3xxx/pinmux.c13
-rw-r--r--arch/arm/plat-versatile/fpga-irq.c12
235 files changed, 1689 insertions, 1141 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index efe06e004714..5b9f78b570e8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -28,6 +28,7 @@ config ARM
28 select HAVE_C_RECORDMCOUNT 28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS 29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ 30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
31 help 32 help
32 The ARM series is a line of low-power-consumption RISC chip designs 33 The ARM series is a line of low-power-consumption RISC chip designs
33 licensed by ARM Ltd and targeted at embedded applications and 34 licensed by ARM Ltd and targeted at embedded applications and
@@ -365,6 +366,7 @@ config ARCH_MXC
365 select GENERIC_CLOCKEVENTS 366 select GENERIC_CLOCKEVENTS
366 select ARCH_REQUIRE_GPIOLIB 367 select ARCH_REQUIRE_GPIOLIB
367 select CLKDEV_LOOKUP 368 select CLKDEV_LOOKUP
369 select HAVE_SCHED_CLOCK
368 help 370 help
369 Support for Freescale MXC/iMX-based family of processors 371 Support for Freescale MXC/iMX-based family of processors
370 372
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 84ac4d656310..adf583cd0c35 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -21,20 +21,12 @@
21 21
22#if defined(CONFIG_DEBUG_ICEDCC) 22#if defined(CONFIG_DEBUG_ICEDCC)
23 23
24#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) 24#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
25 .macro loadsp, rb, tmp 25 .macro loadsp, rb, tmp
26 .endm 26 .endm
27 .macro writeb, ch, rb 27 .macro writeb, ch, rb
28 mcr p14, 0, \ch, c0, c5, 0 28 mcr p14, 0, \ch, c0, c5, 0
29 .endm 29 .endm
30#elif defined(CONFIG_CPU_V7)
31 .macro loadsp, rb, tmp
32 .endm
33 .macro writeb, ch, rb
34wait: mrc p14, 0, pc, c0, c1, 0
35 bcs wait
36 mcr p14, 0, \ch, c0, c5, 0
37 .endm
38#elif defined(CONFIG_CPU_XSCALE) 30#elif defined(CONFIG_CPU_XSCALE)
39 .macro loadsp, rb, tmp 31 .macro loadsp, rb, tmp
40 .endm 32 .endm
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 4657e877bf8f..2df38263124c 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -36,7 +36,7 @@ extern void error(char *x);
36 36
37#ifdef CONFIG_DEBUG_ICEDCC 37#ifdef CONFIG_DEBUG_ICEDCC
38 38
39#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) 39#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
40 40
41static void icedcc_putc(int ch) 41static void icedcc_putc(int ch)
42{ 42{
@@ -52,16 +52,6 @@ static void icedcc_putc(int ch)
52 asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); 52 asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch));
53} 53}
54 54
55#elif defined(CONFIG_CPU_V7)
56
57static void icedcc_putc(int ch)
58{
59 asm(
60 "wait: mrc p14, 0, pc, c0, c1, 0 \n\
61 bcs wait \n\
62 mcr p14, 0, %0, c0, c5, 0 "
63 : : "r" (ch));
64}
65 55
66#elif defined(CONFIG_CPU_XSCALE) 56#elif defined(CONFIG_CPU_XSCALE)
67 57
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index cb6b041c39d2..f70ec7dadebb 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -213,8 +213,8 @@ static int gic_set_wake(struct irq_data *d, unsigned int on)
213 213
214static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) 214static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
215{ 215{
216 struct gic_chip_data *chip_data = get_irq_data(irq); 216 struct gic_chip_data *chip_data = irq_get_handler_data(irq);
217 struct irq_chip *chip = get_irq_chip(irq); 217 struct irq_chip *chip = irq_get_chip(irq);
218 unsigned int cascade_irq, gic_irq; 218 unsigned int cascade_irq, gic_irq;
219 unsigned long status; 219 unsigned long status;
220 220
@@ -257,9 +257,9 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
257{ 257{
258 if (gic_nr >= MAX_GIC_NR) 258 if (gic_nr >= MAX_GIC_NR)
259 BUG(); 259 BUG();
260 if (set_irq_data(irq, &gic_data[gic_nr]) != 0) 260 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
261 BUG(); 261 BUG();
262 set_irq_chained_handler(irq, gic_handle_cascade_irq); 262 irq_set_chained_handler(irq, gic_handle_cascade_irq);
263} 263}
264 264
265static void __init gic_dist_init(struct gic_chip_data *gic, 265static void __init gic_dist_init(struct gic_chip_data *gic,
@@ -319,9 +319,8 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
319 * Setup the Linux IRQ subsystem. 319 * Setup the Linux IRQ subsystem.
320 */ 320 */
321 for (i = irq_start; i < irq_limit; i++) { 321 for (i = irq_start; i < irq_limit; i++) {
322 set_irq_chip(i, &gic_chip); 322 irq_set_chip_and_handler(i, &gic_chip, handle_level_irq);
323 set_irq_chip_data(i, gic); 323 irq_set_chip_data(i, gic);
324 set_irq_handler(i, handle_level_irq);
325 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 324 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
326 } 325 }
327 326
@@ -382,7 +381,7 @@ void __cpuinit gic_enable_ppi(unsigned int irq)
382 unsigned long flags; 381 unsigned long flags;
383 382
384 local_irq_save(flags); 383 local_irq_save(flags);
385 irq_to_desc(irq)->status |= IRQ_NOPROBE; 384 irq_set_status_flags(irq, IRQ_NOPROBE);
386 gic_unmask_irq(irq_get_irq_data(irq)); 385 gic_unmask_irq(irq_get_irq_data(irq));
387 local_irq_restore(flags); 386 local_irq_restore(flags);
388} 387}
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index fcddd48fe9da..7a21927c52e1 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -88,8 +88,8 @@ void it8152_init_irq(void)
88 __raw_writel((0), IT8152_INTC_LDCNIRR); 88 __raw_writel((0), IT8152_INTC_LDCNIRR);
89 89
90 for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { 90 for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
91 set_irq_chip(irq, &it8152_irq_chip); 91 irq_set_chip_and_handler(irq, &it8152_irq_chip,
92 set_irq_handler(irq, handle_level_irq); 92 handle_level_irq);
93 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 93 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
94 } 94 }
95} 95}
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index a026a6bf4892..b55c3625d7ee 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -140,7 +140,7 @@ static struct locomo_dev_info locomo_devices[] = {
140 140
141static void locomo_handler(unsigned int irq, struct irq_desc *desc) 141static void locomo_handler(unsigned int irq, struct irq_desc *desc)
142{ 142{
143 struct locomo *lchip = get_irq_chip_data(irq); 143 struct locomo *lchip = irq_get_chip_data(irq);
144 int req, i; 144 int req, i;
145 145
146 /* Acknowledge the parent IRQ */ 146 /* Acknowledge the parent IRQ */
@@ -197,15 +197,14 @@ static void locomo_setup_irq(struct locomo *lchip)
197 /* 197 /*
198 * Install handler for IRQ_LOCOMO_HW. 198 * Install handler for IRQ_LOCOMO_HW.
199 */ 199 */
200 set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING); 200 irq_set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING);
201 set_irq_chip_data(lchip->irq, lchip); 201 irq_set_chip_data(lchip->irq, lchip);
202 set_irq_chained_handler(lchip->irq, locomo_handler); 202 irq_set_chained_handler(lchip->irq, locomo_handler);
203 203
204 /* Install handlers for IRQ_LOCOMO_* */ 204 /* Install handlers for IRQ_LOCOMO_* */
205 for ( ; irq <= lchip->irq_base + 3; irq++) { 205 for ( ; irq <= lchip->irq_base + 3; irq++) {
206 set_irq_chip(irq, &locomo_chip); 206 irq_set_chip_and_handler(irq, &locomo_chip, handle_level_irq);
207 set_irq_chip_data(irq, lchip); 207 irq_set_chip_data(irq, lchip);
208 set_irq_handler(irq, handle_level_irq);
209 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 208 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
210 } 209 }
211} 210}
@@ -476,8 +475,8 @@ static void __locomo_remove(struct locomo *lchip)
476 device_for_each_child(lchip->dev, NULL, locomo_remove_child); 475 device_for_each_child(lchip->dev, NULL, locomo_remove_child);
477 476
478 if (lchip->irq != NO_IRQ) { 477 if (lchip->irq != NO_IRQ) {
479 set_irq_chained_handler(lchip->irq, NULL); 478 irq_set_chained_handler(lchip->irq, NULL);
480 set_irq_data(lchip->irq, NULL); 479 irq_set_handler_data(lchip->irq, NULL);
481 } 480 }
482 481
483 iounmap(lchip->base); 482 iounmap(lchip->base);
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index eb9796b0dab2..a12b33c0dc42 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -202,7 +202,7 @@ static void
202sa1111_irq_handler(unsigned int irq, struct irq_desc *desc) 202sa1111_irq_handler(unsigned int irq, struct irq_desc *desc)
203{ 203{
204 unsigned int stat0, stat1, i; 204 unsigned int stat0, stat1, i;
205 struct sa1111 *sachip = get_irq_data(irq); 205 struct sa1111 *sachip = irq_get_handler_data(irq);
206 void __iomem *mapbase = sachip->base + SA1111_INTC; 206 void __iomem *mapbase = sachip->base + SA1111_INTC;
207 207
208 stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0); 208 stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0);
@@ -472,25 +472,25 @@ static void sa1111_setup_irq(struct sa1111 *sachip)
472 sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1); 472 sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1);
473 473
474 for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { 474 for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) {
475 set_irq_chip(irq, &sa1111_low_chip); 475 irq_set_chip_and_handler(irq, &sa1111_low_chip,
476 set_irq_chip_data(irq, sachip); 476 handle_edge_irq);
477 set_irq_handler(irq, handle_edge_irq); 477 irq_set_chip_data(irq, sachip);
478 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 478 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
479 } 479 }
480 480
481 for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) { 481 for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) {
482 set_irq_chip(irq, &sa1111_high_chip); 482 irq_set_chip_and_handler(irq, &sa1111_high_chip,
483 set_irq_chip_data(irq, sachip); 483 handle_edge_irq);
484 set_irq_handler(irq, handle_edge_irq); 484 irq_set_chip_data(irq, sachip);
485 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 485 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
486 } 486 }
487 487
488 /* 488 /*
489 * Register SA1111 interrupt 489 * Register SA1111 interrupt
490 */ 490 */
491 set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); 491 irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
492 set_irq_data(sachip->irq, sachip); 492 irq_set_handler_data(sachip->irq, sachip);
493 set_irq_chained_handler(sachip->irq, sa1111_irq_handler); 493 irq_set_chained_handler(sachip->irq, sa1111_irq_handler);
494} 494}
495 495
496/* 496/*
@@ -815,8 +815,8 @@ static void __sa1111_remove(struct sa1111 *sachip)
815 clk_disable(sachip->clk); 815 clk_disable(sachip->clk);
816 816
817 if (sachip->irq != NO_IRQ) { 817 if (sachip->irq != NO_IRQ) {
818 set_irq_chained_handler(sachip->irq, NULL); 818 irq_set_chained_handler(sachip->irq, NULL);
819 set_irq_data(sachip->irq, NULL); 819 irq_set_handler_data(sachip->irq, NULL);
820 820
821 release_mem_region(sachip->phys + SA1111_INTC, 512); 821 release_mem_region(sachip->phys + SA1111_INTC, 512);
822 } 822 }
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index ae5fe7292e0d..113085a77123 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -305,9 +305,9 @@ static void __init vic_set_irq_sources(void __iomem *base,
305 if (vic_sources & (1 << i)) { 305 if (vic_sources & (1 << i)) {
306 unsigned int irq = irq_start + i; 306 unsigned int irq = irq_start + i;
307 307
308 set_irq_chip(irq, &vic_chip); 308 irq_set_chip_and_handler(irq, &vic_chip,
309 set_irq_chip_data(irq, base); 309 handle_level_irq);
310 set_irq_handler(irq, handle_level_irq); 310 irq_set_chip_data(irq, base);
311 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 311 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
312 } 312 }
313 } 313 }
diff --git a/arch/arm/include/asm/hw_irq.h b/arch/arm/include/asm/hw_irq.h
index 5586b7c8ef6f..a71b417b1856 100644
--- a/arch/arm/include/asm/hw_irq.h
+++ b/arch/arm/include/asm/hw_irq.h
@@ -10,14 +10,6 @@ static inline void ack_bad_irq(int irq)
10 irq_err_count++; 10 irq_err_count++;
11} 11}
12 12
13/*
14 * Obsolete inline function for calling irq descriptor handlers.
15 */
16static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc)
17{
18 desc->handle_irq(irq, desc);
19}
20
21void set_irq_flags(unsigned int irq, unsigned int flags); 13void set_irq_flags(unsigned int irq, unsigned int flags);
22 14
23#define IRQF_VALID (1 << 0) 15#define IRQF_VALID (1 << 0)
diff --git a/arch/arm/include/asm/mach/udc_pxa2xx.h b/arch/arm/include/asm/mach/udc_pxa2xx.h
index 833306ee9e7f..ea297ac70bc6 100644
--- a/arch/arm/include/asm/mach/udc_pxa2xx.h
+++ b/arch/arm/include/asm/mach/udc_pxa2xx.h
@@ -20,8 +20,6 @@ struct pxa2xx_udc_mach_info {
20 * VBUS IRQ and omit the methods above. Store the GPIO number 20 * VBUS IRQ and omit the methods above. Store the GPIO number
21 * here. Note that sometimes the signals go through inverters... 21 * here. Note that sometimes the signals go through inverters...
22 */ 22 */
23 bool gpio_vbus_inverted;
24 int gpio_vbus; /* high == vbus present */
25 bool gpio_pullup_inverted; 23 bool gpio_pullup_inverted;
26 int gpio_pullup; /* high == pullup activated */ 24 int gpio_pullup; /* high == pullup activated */
27}; 25};
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index d86fcd44b220..e4ee050aad7d 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -159,31 +159,6 @@ static void __devinit pci_fixup_dec21285(struct pci_dev *dev)
159DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285); 159DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
160 160
161/* 161/*
162 * Same as above. The PrPMC800 carrier board for the PrPMC1100
163 * card maps the host-bridge @ 00:01:00 for some reason and it
164 * ends up getting scanned. Note that we only want to do this
165 * fixup when we find the IXP4xx on a PrPMC system, which is why
166 * we check the machine type. We could be running on a board
167 * with an IXP4xx target device and we don't want to kill the
168 * resources in that case.
169 */
170static void __devinit pci_fixup_prpmc1100(struct pci_dev *dev)
171{
172 int i;
173
174 if (machine_is_prpmc1100()) {
175 dev->class &= 0xff;
176 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
177 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
178 dev->resource[i].start = 0;
179 dev->resource[i].end = 0;
180 dev->resource[i].flags = 0;
181 }
182 }
183}
184DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP4XX, pci_fixup_prpmc1100);
185
186/*
187 * PCI IDE controllers use non-standard I/O port decoding, respect it. 162 * PCI IDE controllers use non-standard I/O port decoding, respect it.
188 */ 163 */
189static void __devinit pci_fixup_ide_bases(struct pci_dev *dev) 164static void __devinit pci_fixup_ide_bases(struct pci_dev *dev)
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index d2d983be096d..bcd66e00bdbe 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -25,7 +25,7 @@
25 .macro addruart, rp, rv 25 .macro addruart, rp, rv
26 .endm 26 .endm
27 27
28#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) 28#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
29 29
30 .macro senduart, rd, rx 30 .macro senduart, rd, rx
31 mcr p14, 0, \rd, c0, c5, 0 31 mcr p14, 0, \rd, c0, c5, 0
@@ -49,23 +49,6 @@
491002: 491002:
50 .endm 50 .endm
51 51
52#elif defined(CONFIG_CPU_V7)
53
54 .macro senduart, rd, rx
55 mcr p14, 0, \rd, c0, c5, 0
56 .endm
57
58 .macro busyuart, rd, rx
59busy: mrc p14, 0, pc, c0, c1, 0
60 bcs busy
61 .endm
62
63 .macro waituart, rd, rx
64wait: mrc p14, 0, pc, c0, c1, 0
65 bcs wait
66
67 .endm
68
69#elif defined(CONFIG_CPU_XSCALE) 52#elif defined(CONFIG_CPU_XSCALE)
70 53
71 .macro senduart, rd, rx 54 .macro senduart, rd, rx
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index 2ad62df37730..d16500110ee9 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -1043,8 +1043,8 @@ ecard_probe(int slot, card_type_t type)
1043 */ 1043 */
1044 if (slot < 8) { 1044 if (slot < 8) {
1045 ec->irq = 32 + slot; 1045 ec->irq = 32 + slot;
1046 set_irq_chip(ec->irq, &ecard_chip); 1046 irq_set_chip_and_handler(ec->irq, &ecard_chip,
1047 set_irq_handler(ec->irq, handle_level_irq); 1047 handle_level_irq);
1048 set_irq_flags(ec->irq, IRQF_VALID); 1048 set_irq_flags(ec->irq, IRQF_VALID);
1049 } 1049 }
1050 1050
@@ -1103,7 +1103,7 @@ static int __init ecard_init(void)
1103 1103
1104 irqhw = ecard_probeirqhw(); 1104 irqhw = ecard_probeirqhw();
1105 1105
1106 set_irq_chained_handler(IRQ_EXPANSIONCARD, 1106 irq_set_chained_handler(IRQ_EXPANSIONCARD,
1107 irqhw ? ecard_irqexp_handler : ecard_irq_handler); 1107 irqhw ? ecard_irqexp_handler : ecard_irq_handler);
1108 1108
1109 ecard_proc_init(); 1109 ecard_proc_init();
diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c
index 052b509e2d5f..1bec8b5f22f0 100644
--- a/arch/arm/kernel/etm.c
+++ b/arch/arm/kernel/etm.c
@@ -338,7 +338,7 @@ static struct miscdevice etb_miscdev = {
338 .fops = &etb_fops, 338 .fops = &etb_fops,
339}; 339};
340 340
341static int __init etb_probe(struct amba_device *dev, const struct amba_id *id) 341static int __devinit etb_probe(struct amba_device *dev, const struct amba_id *id)
342{ 342{
343 struct tracectx *t = &tracer; 343 struct tracectx *t = &tracer;
344 int ret = 0; 344 int ret = 0;
@@ -530,7 +530,7 @@ static ssize_t trace_mode_store(struct kobject *kobj,
530static struct kobj_attribute trace_mode_attr = 530static struct kobj_attribute trace_mode_attr =
531 __ATTR(trace_mode, 0644, trace_mode_show, trace_mode_store); 531 __ATTR(trace_mode, 0644, trace_mode_show, trace_mode_store);
532 532
533static int __init etm_probe(struct amba_device *dev, const struct amba_id *id) 533static int __devinit etm_probe(struct amba_device *dev, const struct amba_id *id)
534{ 534{
535 struct tracectx *t = &tracer; 535 struct tracectx *t = &tracer;
536 int ret = 0; 536 int ret = 0;
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 3535d3793e65..83bbad03fcc6 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -51,63 +51,18 @@
51 51
52unsigned long irq_err_count; 52unsigned long irq_err_count;
53 53
54int show_interrupts(struct seq_file *p, void *v) 54int arch_show_interrupts(struct seq_file *p, int prec)
55{ 55{
56 int i = *(loff_t *) v, cpu;
57 struct irq_desc *desc;
58 struct irqaction * action;
59 unsigned long flags;
60 int prec, n;
61
62 for (prec = 3, n = 1000; prec < 10 && n <= nr_irqs; prec++)
63 n *= 10;
64
65#ifdef CONFIG_SMP
66 if (prec < 4)
67 prec = 4;
68#endif
69
70 if (i == 0) {
71 char cpuname[12];
72
73 seq_printf(p, "%*s ", prec, "");
74 for_each_present_cpu(cpu) {
75 sprintf(cpuname, "CPU%d", cpu);
76 seq_printf(p, " %10s", cpuname);
77 }
78 seq_putc(p, '\n');
79 }
80
81 if (i < nr_irqs) {
82 desc = irq_to_desc(i);
83 raw_spin_lock_irqsave(&desc->lock, flags);
84 action = desc->action;
85 if (!action)
86 goto unlock;
87
88 seq_printf(p, "%*d: ", prec, i);
89 for_each_present_cpu(cpu)
90 seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
91 seq_printf(p, " %10s", desc->irq_data.chip->name ? : "-");
92 seq_printf(p, " %s", action->name);
93 for (action = action->next; action; action = action->next)
94 seq_printf(p, ", %s", action->name);
95
96 seq_putc(p, '\n');
97unlock:
98 raw_spin_unlock_irqrestore(&desc->lock, flags);
99 } else if (i == nr_irqs) {
100#ifdef CONFIG_FIQ 56#ifdef CONFIG_FIQ
101 show_fiq_list(p, prec); 57 show_fiq_list(p, prec);
102#endif 58#endif
103#ifdef CONFIG_SMP 59#ifdef CONFIG_SMP
104 show_ipi_list(p, prec); 60 show_ipi_list(p, prec);
105#endif 61#endif
106#ifdef CONFIG_LOCAL_TIMERS 62#ifdef CONFIG_LOCAL_TIMERS
107 show_local_irqs(p, prec); 63 show_local_irqs(p, prec);
108#endif 64#endif
109 seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); 65 seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
110 }
111 return 0; 66 return 0;
112} 67}
113 68
@@ -144,24 +99,21 @@ asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
144 99
145void set_irq_flags(unsigned int irq, unsigned int iflags) 100void set_irq_flags(unsigned int irq, unsigned int iflags)
146{ 101{
147 struct irq_desc *desc; 102 unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
148 unsigned long flags;
149 103
150 if (irq >= nr_irqs) { 104 if (irq >= nr_irqs) {
151 printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq); 105 printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq);
152 return; 106 return;
153 } 107 }
154 108
155 desc = irq_to_desc(irq);
156 raw_spin_lock_irqsave(&desc->lock, flags);
157 desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
158 if (iflags & IRQF_VALID) 109 if (iflags & IRQF_VALID)
159 desc->status &= ~IRQ_NOREQUEST; 110 clr |= IRQ_NOREQUEST;
160 if (iflags & IRQF_PROBE) 111 if (iflags & IRQF_PROBE)
161 desc->status &= ~IRQ_NOPROBE; 112 clr |= IRQ_NOPROBE;
162 if (!(iflags & IRQF_NOAUTOEN)) 113 if (!(iflags & IRQF_NOAUTOEN))
163 desc->status &= ~IRQ_NOAUTOEN; 114 clr |= IRQ_NOAUTOEN;
164 raw_spin_unlock_irqrestore(&desc->lock, flags); 115 /* Order is clear bits in "clr" then set bits in "set" */
116 irq_modify_status(irq, clr, set & ~clr);
165} 117}
166 118
167void __init init_IRQ(void) 119void __init init_IRQ(void)
diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c
index 8f6ed43861f1..23891317dc4b 100644
--- a/arch/arm/kernel/kprobes-decode.c
+++ b/arch/arm/kernel/kprobes-decode.c
@@ -594,7 +594,8 @@ static void __kprobes emulate_ldr(struct kprobe *p, struct pt_regs *regs)
594 long cpsr = regs->ARM_cpsr; 594 long cpsr = regs->ARM_cpsr;
595 595
596 fnr.dr = insnslot_llret_3arg_rflags(rnv, 0, rmv, cpsr, i_fn); 596 fnr.dr = insnslot_llret_3arg_rflags(rnv, 0, rmv, cpsr, i_fn);
597 regs->uregs[rn] = fnr.r0; /* Save Rn in case of writeback. */ 597 if (rn != 15)
598 regs->uregs[rn] = fnr.r0; /* Save Rn in case of writeback. */
598 rdv = fnr.r1; 599 rdv = fnr.r1;
599 600
600 if (rd == 15) { 601 if (rd == 15) {
@@ -622,10 +623,11 @@ static void __kprobes emulate_str(struct kprobe *p, struct pt_regs *regs)
622 long rdv = (rd == 15) ? iaddr + str_pc_offset : regs->uregs[rd]; 623 long rdv = (rd == 15) ? iaddr + str_pc_offset : regs->uregs[rd];
623 long rnv = (rn == 15) ? iaddr + 8 : regs->uregs[rn]; 624 long rnv = (rn == 15) ? iaddr + 8 : regs->uregs[rn];
624 long rmv = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */ 625 long rmv = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */
626 long rnv_wb;
625 627
626 /* Save Rn in case of writeback. */ 628 rnv_wb = insnslot_3arg_rflags(rnv, rdv, rmv, regs->ARM_cpsr, i_fn);
627 regs->uregs[rn] = 629 if (rn != 15)
628 insnslot_3arg_rflags(rnv, rdv, rmv, regs->ARM_cpsr, i_fn); 630 regs->uregs[rn] = rnv_wb; /* Save Rn in case of writeback. */
629} 631}
630 632
631static void __kprobes emulate_mrrc(struct kprobe *p, struct pt_regs *regs) 633static void __kprobes emulate_mrrc(struct kprobe *p, struct pt_regs *regs)
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 22e194eb8536..69cfee0fe00f 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -79,6 +79,7 @@ struct arm_pmu {
79 void (*write_counter)(int idx, u32 val); 79 void (*write_counter)(int idx, u32 val);
80 void (*start)(void); 80 void (*start)(void);
81 void (*stop)(void); 81 void (*stop)(void);
82 void (*reset)(void *);
82 const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] 83 const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
83 [PERF_COUNT_HW_CACHE_OP_MAX] 84 [PERF_COUNT_HW_CACHE_OP_MAX]
84 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 85 [PERF_COUNT_HW_CACHE_RESULT_MAX];
@@ -204,11 +205,9 @@ armpmu_event_set_period(struct perf_event *event,
204static u64 205static u64
205armpmu_event_update(struct perf_event *event, 206armpmu_event_update(struct perf_event *event,
206 struct hw_perf_event *hwc, 207 struct hw_perf_event *hwc,
207 int idx) 208 int idx, int overflow)
208{ 209{
209 int shift = 64 - 32; 210 u64 delta, prev_raw_count, new_raw_count;
210 s64 prev_raw_count, new_raw_count;
211 u64 delta;
212 211
213again: 212again:
214 prev_raw_count = local64_read(&hwc->prev_count); 213 prev_raw_count = local64_read(&hwc->prev_count);
@@ -218,8 +217,13 @@ again:
218 new_raw_count) != prev_raw_count) 217 new_raw_count) != prev_raw_count)
219 goto again; 218 goto again;
220 219
221 delta = (new_raw_count << shift) - (prev_raw_count << shift); 220 new_raw_count &= armpmu->max_period;
222 delta >>= shift; 221 prev_raw_count &= armpmu->max_period;
222
223 if (overflow)
224 delta = armpmu->max_period - prev_raw_count + new_raw_count;
225 else
226 delta = new_raw_count - prev_raw_count;
223 227
224 local64_add(delta, &event->count); 228 local64_add(delta, &event->count);
225 local64_sub(delta, &hwc->period_left); 229 local64_sub(delta, &hwc->period_left);
@@ -236,7 +240,7 @@ armpmu_read(struct perf_event *event)
236 if (hwc->idx < 0) 240 if (hwc->idx < 0)
237 return; 241 return;
238 242
239 armpmu_event_update(event, hwc, hwc->idx); 243 armpmu_event_update(event, hwc, hwc->idx, 0);
240} 244}
241 245
242static void 246static void
@@ -254,7 +258,7 @@ armpmu_stop(struct perf_event *event, int flags)
254 if (!(hwc->state & PERF_HES_STOPPED)) { 258 if (!(hwc->state & PERF_HES_STOPPED)) {
255 armpmu->disable(hwc, hwc->idx); 259 armpmu->disable(hwc, hwc->idx);
256 barrier(); /* why? */ 260 barrier(); /* why? */
257 armpmu_event_update(event, hwc, hwc->idx); 261 armpmu_event_update(event, hwc, hwc->idx, 0);
258 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 262 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
259 } 263 }
260} 264}
@@ -624,6 +628,19 @@ static struct pmu pmu = {
624#include "perf_event_v6.c" 628#include "perf_event_v6.c"
625#include "perf_event_v7.c" 629#include "perf_event_v7.c"
626 630
631/*
632 * Ensure the PMU has sane values out of reset.
633 * This requires SMP to be available, so exists as a separate initcall.
634 */
635static int __init
636armpmu_reset(void)
637{
638 if (armpmu && armpmu->reset)
639 return on_each_cpu(armpmu->reset, NULL, 1);
640 return 0;
641}
642arch_initcall(armpmu_reset);
643
627static int __init 644static int __init
628init_hw_perf_events(void) 645init_hw_perf_events(void)
629{ 646{
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index 6fc2d228db55..f1e8dd94afe8 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -474,7 +474,7 @@ armv6pmu_handle_irq(int irq_num,
474 continue; 474 continue;
475 475
476 hwc = &event->hw; 476 hwc = &event->hw;
477 armpmu_event_update(event, hwc, idx); 477 armpmu_event_update(event, hwc, idx, 1);
478 data.period = event->hw.last_period; 478 data.period = event->hw.last_period;
479 if (!armpmu_event_set_period(event, hwc, idx)) 479 if (!armpmu_event_set_period(event, hwc, idx))
480 continue; 480 continue;
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 2e1402556fa0..4960686afb58 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -466,6 +466,7 @@ static inline unsigned long armv7_pmnc_read(void)
466static inline void armv7_pmnc_write(unsigned long val) 466static inline void armv7_pmnc_write(unsigned long val)
467{ 467{
468 val &= ARMV7_PMNC_MASK; 468 val &= ARMV7_PMNC_MASK;
469 isb();
469 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); 470 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
470} 471}
471 472
@@ -502,6 +503,7 @@ static inline int armv7_pmnc_select_counter(unsigned int idx)
502 503
503 val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK; 504 val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK;
504 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val)); 505 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
506 isb();
505 507
506 return idx; 508 return idx;
507} 509}
@@ -780,7 +782,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
780 continue; 782 continue;
781 783
782 hwc = &event->hw; 784 hwc = &event->hw;
783 armpmu_event_update(event, hwc, idx); 785 armpmu_event_update(event, hwc, idx, 1);
784 data.period = event->hw.last_period; 786 data.period = event->hw.last_period;
785 if (!armpmu_event_set_period(event, hwc, idx)) 787 if (!armpmu_event_set_period(event, hwc, idx))
786 continue; 788 continue;
@@ -847,6 +849,18 @@ static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc,
847 } 849 }
848} 850}
849 851
852static void armv7pmu_reset(void *info)
853{
854 u32 idx, nb_cnt = armpmu->num_events;
855
856 /* The counter and interrupt enable registers are unknown at reset. */
857 for (idx = 1; idx < nb_cnt; ++idx)
858 armv7pmu_disable_event(NULL, idx);
859
860 /* Initialize & Reset PMNC: C and P bits */
861 armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
862}
863
850static struct arm_pmu armv7pmu = { 864static struct arm_pmu armv7pmu = {
851 .handle_irq = armv7pmu_handle_irq, 865 .handle_irq = armv7pmu_handle_irq,
852 .enable = armv7pmu_enable_event, 866 .enable = armv7pmu_enable_event,
@@ -856,17 +870,15 @@ static struct arm_pmu armv7pmu = {
856 .get_event_idx = armv7pmu_get_event_idx, 870 .get_event_idx = armv7pmu_get_event_idx,
857 .start = armv7pmu_start, 871 .start = armv7pmu_start,
858 .stop = armv7pmu_stop, 872 .stop = armv7pmu_stop,
873 .reset = armv7pmu_reset,
859 .raw_event_mask = 0xFF, 874 .raw_event_mask = 0xFF,
860 .max_period = (1LLU << 32) - 1, 875 .max_period = (1LLU << 32) - 1,
861}; 876};
862 877
863static u32 __init armv7_reset_read_pmnc(void) 878static u32 __init armv7_read_num_pmnc_events(void)
864{ 879{
865 u32 nb_cnt; 880 u32 nb_cnt;
866 881
867 /* Initialize & Reset PMNC: C and P bits */
868 armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
869
870 /* Read the nb of CNTx counters supported from PMNC */ 882 /* Read the nb of CNTx counters supported from PMNC */
871 nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK; 883 nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK;
872 884
@@ -880,7 +892,7 @@ static const struct arm_pmu *__init armv7_a8_pmu_init(void)
880 armv7pmu.name = "ARMv7 Cortex-A8"; 892 armv7pmu.name = "ARMv7 Cortex-A8";
881 armv7pmu.cache_map = &armv7_a8_perf_cache_map; 893 armv7pmu.cache_map = &armv7_a8_perf_cache_map;
882 armv7pmu.event_map = &armv7_a8_perf_map; 894 armv7pmu.event_map = &armv7_a8_perf_map;
883 armv7pmu.num_events = armv7_reset_read_pmnc(); 895 armv7pmu.num_events = armv7_read_num_pmnc_events();
884 return &armv7pmu; 896 return &armv7pmu;
885} 897}
886 898
@@ -890,7 +902,7 @@ static const struct arm_pmu *__init armv7_a9_pmu_init(void)
890 armv7pmu.name = "ARMv7 Cortex-A9"; 902 armv7pmu.name = "ARMv7 Cortex-A9";
891 armv7pmu.cache_map = &armv7_a9_perf_cache_map; 903 armv7pmu.cache_map = &armv7_a9_perf_cache_map;
892 armv7pmu.event_map = &armv7_a9_perf_map; 904 armv7pmu.event_map = &armv7_a9_perf_map;
893 armv7pmu.num_events = armv7_reset_read_pmnc(); 905 armv7pmu.num_events = armv7_read_num_pmnc_events();
894 return &armv7pmu; 906 return &armv7pmu;
895} 907}
896#else 908#else
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index 28cd3b025bc3..39affbe4fdb2 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -246,7 +246,7 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
246 continue; 246 continue;
247 247
248 hwc = &event->hw; 248 hwc = &event->hw;
249 armpmu_event_update(event, hwc, idx); 249 armpmu_event_update(event, hwc, idx, 1);
250 data.period = event->hw.last_period; 250 data.period = event->hw.last_period;
251 if (!armpmu_event_set_period(event, hwc, idx)) 251 if (!armpmu_event_set_period(event, hwc, idx))
252 continue; 252 continue;
@@ -578,7 +578,7 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
578 continue; 578 continue;
579 579
580 hwc = &event->hw; 580 hwc = &event->hw;
581 armpmu_event_update(event, hwc, idx); 581 armpmu_event_update(event, hwc, idx, 1);
582 data.period = event->hw.last_period; 582 data.period = event->hw.last_period;
583 if (!armpmu_event_set_period(event, hwc, idx)) 583 if (!armpmu_event_set_period(event, hwc, idx))
584 continue; 584 continue;
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index bfad698a02e7..6398ead9d1c0 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -119,11 +119,19 @@ ENTRY(cpu_resume)
119#else 119#else
120 ldr r0, sleep_save_sp @ stack phys addr 120 ldr r0, sleep_save_sp @ stack phys addr
121#endif 121#endif
122 msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off 122 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off
123#ifdef MULTI_CPU 123#ifdef MULTI_CPU
124 ldmia r0!, {r1, sp, lr, pc} @ load v:p, stack, return fn, resume fn 124 @ load v:p, stack, return fn, resume fn
125 ARM( ldmia r0!, {r1, sp, lr, pc} )
126THUMB( ldmia r0!, {r1, r2, r3, r4} )
127THUMB( mov sp, r2 )
128THUMB( mov lr, r3 )
129THUMB( bx r4 )
125#else 130#else
126 ldmia r0!, {r1, sp, lr} @ load v:p, stack, return fn 131 @ load v:p, stack, return fn
132 ARM( ldmia r0!, {r1, sp, lr} )
133THUMB( ldmia r0!, {r1, r2, lr} )
134THUMB( mov sp, r2 )
127 b cpu_do_resume 135 b cpu_do_resume
128#endif 136#endif
129ENDPROC(cpu_resume) 137ENDPROC(cpu_resume)
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
index d1f775e86353..9ffbf3a2dfea 100644
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -72,7 +72,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
72 return; 72 return;
73 73
74 if (cpu_is_at91cap9_revB()) 74 if (cpu_is_at91cap9_revB())
75 set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); 75 irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
76 76
77 /* Enable VBus control for UHP ports */ 77 /* Enable VBus control for UHP ports */
78 for (i = 0; i < data->ports; i++) { 78 for (i = 0; i < data->ports; i++) {
@@ -157,7 +157,7 @@ static struct platform_device at91_usba_udc_device = {
157void __init at91_add_device_usba(struct usba_platform_data *data) 157void __init at91_add_device_usba(struct usba_platform_data *data)
158{ 158{
159 if (cpu_is_at91cap9_revB()) { 159 if (cpu_is_at91cap9_revB()) {
160 set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); 160 irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
161 at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS | 161 at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
162 AT91_MATRIX_UDPHS_BYPASS_LOCK); 162 AT91_MATRIX_UDPHS_BYPASS_LOCK);
163 } 163 }
@@ -861,7 +861,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
861 return; 861 return;
862 862
863 if (cpu_is_at91cap9_revB()) 863 if (cpu_is_at91cap9_revB())
864 set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); 864 irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
865 865
866 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ 866 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
867 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ 867 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index af818a21587c..4615528205c8 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -287,7 +287,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
287 else 287 else
288 wakeups[bank] &= ~mask; 288 wakeups[bank] &= ~mask;
289 289
290 set_irq_wake(gpio_chip[bank].bank->id, state); 290 irq_set_irq_wake(gpio_chip[bank].bank->id, state);
291 291
292 return 0; 292 return 0;
293} 293}
@@ -375,6 +375,7 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
375 375
376static struct irq_chip gpio_irqchip = { 376static struct irq_chip gpio_irqchip = {
377 .name = "GPIO", 377 .name = "GPIO",
378 .irq_disable = gpio_irq_mask,
378 .irq_mask = gpio_irq_mask, 379 .irq_mask = gpio_irq_mask,
379 .irq_unmask = gpio_irq_unmask, 380 .irq_unmask = gpio_irq_unmask,
380 .irq_set_type = gpio_irq_type, 381 .irq_set_type = gpio_irq_type,
@@ -384,16 +385,14 @@ static struct irq_chip gpio_irqchip = {
384static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 385static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
385{ 386{
386 unsigned pin; 387 unsigned pin;
387 struct irq_desc *gpio; 388 struct irq_data *idata = irq_desc_get_irq_data(desc);
388 struct at91_gpio_chip *at91_gpio; 389 struct irq_chip *chip = irq_data_get_irq_chip(idata);
389 void __iomem *pio; 390 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
391 void __iomem *pio = at91_gpio->regbase;
390 u32 isr; 392 u32 isr;
391 393
392 at91_gpio = get_irq_chip_data(irq);
393 pio = at91_gpio->regbase;
394
395 /* temporarily mask (level sensitive) parent IRQ */ 394 /* temporarily mask (level sensitive) parent IRQ */
396 desc->irq_data.chip->irq_ack(&desc->irq_data); 395 chip->irq_ack(idata);
397 for (;;) { 396 for (;;) {
398 /* Reading ISR acks pending (edge triggered) GPIO interrupts. 397 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
399 * When there none are pending, we're finished unless we need 398 * When there none are pending, we're finished unless we need
@@ -409,27 +408,15 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
409 } 408 }
410 409
411 pin = at91_gpio->chip.base; 410 pin = at91_gpio->chip.base;
412 gpio = &irq_desc[pin];
413 411
414 while (isr) { 412 while (isr) {
415 if (isr & 1) { 413 if (isr & 1)
416 if (unlikely(gpio->depth)) { 414 generic_handle_irq(pin);
417 /*
418 * The core ARM interrupt handler lazily disables IRQs so
419 * another IRQ must be generated before it actually gets
420 * here to be disabled on the GPIO controller.
421 */
422 gpio_irq_mask(irq_get_irq_data(pin));
423 }
424 else
425 generic_handle_irq(pin);
426 }
427 pin++; 415 pin++;
428 gpio++;
429 isr >>= 1; 416 isr >>= 1;
430 } 417 }
431 } 418 }
432 desc->irq_data.chip->irq_unmask(&desc->irq_data); 419 chip->irq_unmask(idata);
433 /* now it may re-trigger */ 420 /* now it may re-trigger */
434} 421}
435 422
@@ -518,14 +505,14 @@ void __init at91_gpio_irq_setup(void)
518 __raw_writel(~0, this->regbase + PIO_IDR); 505 __raw_writel(~0, this->regbase + PIO_IDR);
519 506
520 for (i = 0, pin = this->chip.base; i < 32; i++, pin++) { 507 for (i = 0, pin = this->chip.base; i < 32; i++, pin++) {
521 lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class); 508 irq_set_lockdep_class(pin, &gpio_lock_class);
522 509
523 /* 510 /*
524 * Can use the "simple" and not "edge" handler since it's 511 * Can use the "simple" and not "edge" handler since it's
525 * shorter, and the AIC handles interrupts sanely. 512 * shorter, and the AIC handles interrupts sanely.
526 */ 513 */
527 set_irq_chip(pin, &gpio_irqchip); 514 irq_set_chip_and_handler(pin, &gpio_irqchip,
528 set_irq_handler(pin, handle_simple_irq); 515 handle_simple_irq);
529 set_irq_flags(pin, IRQF_VALID); 516 set_irq_flags(pin, IRQF_VALID);
530 } 517 }
531 518
@@ -536,8 +523,8 @@ void __init at91_gpio_irq_setup(void)
536 if (prev && prev->next == this) 523 if (prev && prev->next == this)
537 continue; 524 continue;
538 525
539 set_irq_chip_data(id, this); 526 irq_set_chip_data(id, this);
540 set_irq_chained_handler(id, gpio_irq_handler); 527 irq_set_chained_handler(id, gpio_irq_handler);
541 } 528 }
542 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); 529 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
543} 530}
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h
index 2d9b0af9c4d5..be510cfc56be 100644
--- a/arch/arm/mach-at91/include/mach/at572d940hf.h
+++ b/arch/arm/mach-at91/include/mach/at572d940hf.h
@@ -89,7 +89,7 @@
89/* 89/*
90 * System Peripherals (offset from AT91_BASE_SYS) 90 * System Peripherals (offset from AT91_BASE_SYS)
91 */ 91 */
92#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) 92#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
93#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 93#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
94#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 94#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
95#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) 95#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index b56d6b3a4087..9665265ec757 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -143,8 +143,7 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
143 /* Active Low interrupt, with the specified priority */ 143 /* Active Low interrupt, with the specified priority */
144 at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); 144 at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
145 145
146 set_irq_chip(i, &at91_aic_chip); 146 irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
147 set_irq_handler(i, handle_level_irq);
148 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 147 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
149 148
150 /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ 149 /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
index 84dcda0d1d9a..c48feaf4e8e9 100644
--- a/arch/arm/mach-bcmring/irq.c
+++ b/arch/arm/mach-bcmring/irq.c
@@ -93,11 +93,11 @@ static void vic_init(void __iomem *base, struct irq_chip *chip,
93 unsigned int i; 93 unsigned int i;
94 for (i = 0; i < 32; i++) { 94 for (i = 0; i < 32; i++) {
95 unsigned int irq = irq_start + i; 95 unsigned int irq = irq_start + i;
96 set_irq_chip(irq, chip); 96 irq_set_chip(irq, chip);
97 set_irq_chip_data(irq, base); 97 irq_set_chip_data(irq, base);
98 98
99 if (vic_sources & (1 << i)) { 99 if (vic_sources & (1 << i)) {
100 set_irq_handler(irq, handle_level_irq); 100 irq_set_handler(irq, handle_level_irq);
101 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 101 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
102 } 102 }
103 } 103 }
@@ -119,9 +119,9 @@ void __init bcmring_init_irq(void)
119 119
120 /* special cases */ 120 /* special cases */
121 if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) { 121 if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
122 set_irq_handler(IRQ_GPIO0, handle_simple_irq); 122 irq_set_handler(IRQ_GPIO0, handle_simple_irq);
123 } 123 }
124 if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) { 124 if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
125 set_irq_handler(IRQ_GPIO1, handle_simple_irq); 125 irq_set_handler(IRQ_GPIO1, handle_simple_irq);
126 } 126 }
127} 127}
diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c
index 86da7a1b2bbe..c2eceee645e3 100644
--- a/arch/arm/mach-clps711x/irq.c
+++ b/arch/arm/mach-clps711x/irq.c
@@ -112,13 +112,13 @@ void __init clps711x_init_irq(void)
112 112
113 for (i = 0; i < NR_IRQS; i++) { 113 for (i = 0; i < NR_IRQS; i++) {
114 if (INT1_IRQS & (1 << i)) { 114 if (INT1_IRQS & (1 << i)) {
115 set_irq_handler(i, handle_level_irq); 115 irq_set_chip_and_handler(i, &int1_chip,
116 set_irq_chip(i, &int1_chip); 116 handle_level_irq);
117 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 117 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
118 } 118 }
119 if (INT2_IRQS & (1 << i)) { 119 if (INT2_IRQS & (1 << i)) {
120 set_irq_handler(i, handle_level_irq); 120 irq_set_chip_and_handler(i, &int2_chip,
121 set_irq_chip(i, &int2_chip); 121 handle_level_irq);
122 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 122 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
123 } 123 }
124 } 124 }
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index 9abc80a86a22..f83152d643c5 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -167,9 +167,9 @@ void __init cp_intc_init(void)
167 167
168 /* Set up genirq dispatching for cp_intc */ 168 /* Set up genirq dispatching for cp_intc */
169 for (i = 0; i < num_irq; i++) { 169 for (i = 0; i < num_irq; i++) {
170 set_irq_chip(i, &cp_intc_irq_chip); 170 irq_set_chip(i, &cp_intc_irq_chip);
171 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 171 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
172 set_irq_handler(i, handle_edge_irq); 172 irq_set_handler(i, handle_edge_irq);
173 } 173 }
174 174
175 /* Enable global interrupt */ 175 /* Enable global interrupt */
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 20d66e5e4663..a0b838894ac9 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -62,7 +62,7 @@ static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
62{ 62{
63 struct davinci_gpio_regs __iomem *g; 63 struct davinci_gpio_regs __iomem *g;
64 64
65 g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq); 65 g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
66 66
67 return g; 67 return g;
68} 68}
@@ -208,7 +208,7 @@ pure_initcall(davinci_gpio_setup);
208static void gpio_irq_disable(struct irq_data *d) 208static void gpio_irq_disable(struct irq_data *d)
209{ 209{
210 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); 210 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
211 u32 mask = (u32) irq_data_get_irq_data(d); 211 u32 mask = (u32) irq_data_get_irq_handler_data(d);
212 212
213 __raw_writel(mask, &g->clr_falling); 213 __raw_writel(mask, &g->clr_falling);
214 __raw_writel(mask, &g->clr_rising); 214 __raw_writel(mask, &g->clr_rising);
@@ -217,8 +217,8 @@ static void gpio_irq_disable(struct irq_data *d)
217static void gpio_irq_enable(struct irq_data *d) 217static void gpio_irq_enable(struct irq_data *d)
218{ 218{
219 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); 219 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
220 u32 mask = (u32) irq_data_get_irq_data(d); 220 u32 mask = (u32) irq_data_get_irq_handler_data(d);
221 unsigned status = irq_desc[d->irq].status; 221 unsigned status = irqd_get_trigger_type(d);
222 222
223 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; 223 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
224 if (!status) 224 if (!status)
@@ -233,21 +233,11 @@ static void gpio_irq_enable(struct irq_data *d)
233static int gpio_irq_type(struct irq_data *d, unsigned trigger) 233static int gpio_irq_type(struct irq_data *d, unsigned trigger)
234{ 234{
235 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); 235 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
236 u32 mask = (u32) irq_data_get_irq_data(d); 236 u32 mask = (u32) irq_data_get_irq_handler_data(d);
237 237
238 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 238 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
239 return -EINVAL; 239 return -EINVAL;
240 240
241 irq_desc[d->irq].status &= ~IRQ_TYPE_SENSE_MASK;
242 irq_desc[d->irq].status |= trigger;
243
244 /* don't enable the IRQ if it's currently disabled */
245 if (irq_desc[d->irq].depth == 0) {
246 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
247 ? &g->set_falling : &g->clr_falling);
248 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
249 ? &g->set_rising : &g->clr_rising);
250 }
251 return 0; 241 return 0;
252} 242}
253 243
@@ -256,6 +246,7 @@ static struct irq_chip gpio_irqchip = {
256 .irq_enable = gpio_irq_enable, 246 .irq_enable = gpio_irq_enable,
257 .irq_disable = gpio_irq_disable, 247 .irq_disable = gpio_irq_disable,
258 .irq_set_type = gpio_irq_type, 248 .irq_set_type = gpio_irq_type,
249 .flags = IRQCHIP_SET_TYPE_MASKED,
259}; 250};
260 251
261static void 252static void
@@ -285,7 +276,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
285 status >>= 16; 276 status >>= 16;
286 277
287 /* now demux them to the right lowlevel handler */ 278 /* now demux them to the right lowlevel handler */
288 n = (int)get_irq_data(irq); 279 n = (int)irq_get_handler_data(irq);
289 while (status) { 280 while (status) {
290 res = ffs(status); 281 res = ffs(status);
291 n += res; 282 n += res;
@@ -323,7 +314,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
323static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger) 314static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
324{ 315{
325 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); 316 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
326 u32 mask = (u32) irq_data_get_irq_data(d); 317 u32 mask = (u32) irq_data_get_irq_handler_data(d);
327 318
328 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 319 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
329 return -EINVAL; 320 return -EINVAL;
@@ -395,7 +386,7 @@ static int __init davinci_gpio_irq_setup(void)
395 386
396 /* AINTC handles mask/unmask; GPIO handles triggering */ 387 /* AINTC handles mask/unmask; GPIO handles triggering */
397 irq = bank_irq; 388 irq = bank_irq;
398 gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq)); 389 gpio_irqchip_unbanked = *irq_get_chip(irq);
399 gpio_irqchip_unbanked.name = "GPIO-AINTC"; 390 gpio_irqchip_unbanked.name = "GPIO-AINTC";
400 gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked; 391 gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
401 392
@@ -406,10 +397,10 @@ static int __init davinci_gpio_irq_setup(void)
406 397
407 /* set the direct IRQs up to use that irqchip */ 398 /* set the direct IRQs up to use that irqchip */
408 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { 399 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
409 set_irq_chip(irq, &gpio_irqchip_unbanked); 400 irq_set_chip(irq, &gpio_irqchip_unbanked);
410 set_irq_data(irq, (void *) __gpio_mask(gpio)); 401 irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
411 set_irq_chip_data(irq, (__force void *) g); 402 irq_set_chip_data(irq, (__force void *)g);
412 irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH; 403 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
413 } 404 }
414 405
415 goto done; 406 goto done;
@@ -430,15 +421,15 @@ static int __init davinci_gpio_irq_setup(void)
430 __raw_writel(~0, &g->clr_rising); 421 __raw_writel(~0, &g->clr_rising);
431 422
432 /* set up all irqs in this bank */ 423 /* set up all irqs in this bank */
433 set_irq_chained_handler(bank_irq, gpio_irq_handler); 424 irq_set_chained_handler(bank_irq, gpio_irq_handler);
434 set_irq_chip_data(bank_irq, (__force void *) g); 425 irq_set_chip_data(bank_irq, (__force void *)g);
435 set_irq_data(bank_irq, (void *) irq); 426 irq_set_handler_data(bank_irq, (void *)irq);
436 427
437 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { 428 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
438 set_irq_chip(irq, &gpio_irqchip); 429 irq_set_chip(irq, &gpio_irqchip);
439 set_irq_chip_data(irq, (__force void *) g); 430 irq_set_chip_data(irq, (__force void *)g);
440 set_irq_data(irq, (void *) __gpio_mask(gpio)); 431 irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
441 set_irq_handler(irq, handle_simple_irq); 432 irq_set_handler(irq, handle_simple_irq);
442 set_irq_flags(irq, IRQF_VALID); 433 set_irq_flags(irq, IRQF_VALID);
443 } 434 }
444 435
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index 5e05c9b64e1f..e6269a6e0014 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -154,11 +154,11 @@ void __init davinci_irq_init(void)
154 154
155 /* set up genirq dispatch for ARM INTC */ 155 /* set up genirq dispatch for ARM INTC */
156 for (i = 0; i < davinci_soc_info.intc_irq_num; i++) { 156 for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
157 set_irq_chip(i, &davinci_irq_chip_0); 157 irq_set_chip(i, &davinci_irq_chip_0);
158 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 158 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
159 if (i != IRQ_TINT1_TINT34) 159 if (i != IRQ_TINT1_TINT34)
160 set_irq_handler(i, handle_edge_irq); 160 irq_set_handler(i, handle_edge_irq);
161 else 161 else
162 set_irq_handler(i, handle_level_irq); 162 irq_set_handler(i, handle_level_irq);
163 } 163 }
164} 164}
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index e5fcdd3f5bf5..b20ec9af7882 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -136,7 +136,7 @@
136#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) 136#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
137#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) 137#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
138#define DOVE_NAND_GPIO_EN (1 << 0) 138#define DOVE_NAND_GPIO_EN (1 << 0)
139#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40) 139#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
140#define DOVE_SPI_GPIO_SEL (1 << 5) 140#define DOVE_SPI_GPIO_SEL (1 << 5)
141#define DOVE_UART1_GPIO_SEL (1 << 4) 141#define DOVE_UART1_GPIO_SEL (1 << 4)
142#define DOVE_AU1_GPIO_SEL (1 << 3) 142#define DOVE_AU1_GPIO_SEL (1 << 3)
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 101707fa2e2c..f07fd16e0c9b 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -86,8 +86,7 @@ static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
86 if (!(cause & (1 << irq))) 86 if (!(cause & (1 << irq)))
87 continue; 87 continue;
88 irq = pmu_to_irq(irq); 88 irq = pmu_to_irq(irq);
89 desc = irq_desc + irq; 89 generic_handle_irq(irq);
90 desc_handle_irq(irq, desc);
91 } 90 }
92} 91}
93 92
@@ -103,14 +102,14 @@ void __init dove_init_irq(void)
103 */ 102 */
104 orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, 103 orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
105 IRQ_DOVE_GPIO_START); 104 IRQ_DOVE_GPIO_START);
106 set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); 105 irq_set_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
107 set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); 106 irq_set_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
108 set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); 107 irq_set_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
109 set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); 108 irq_set_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
110 109
111 orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, 110 orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
112 IRQ_DOVE_GPIO_START + 32); 111 IRQ_DOVE_GPIO_START + 32);
113 set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); 112 irq_set_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
114 113
115 orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0, 114 orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
116 IRQ_DOVE_GPIO_START + 64); 115 IRQ_DOVE_GPIO_START + 64);
@@ -122,10 +121,9 @@ void __init dove_init_irq(void)
122 writel(0, PMU_INTERRUPT_CAUSE); 121 writel(0, PMU_INTERRUPT_CAUSE);
123 122
124 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { 123 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
125 set_irq_chip(i, &pmu_irq_chip); 124 irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
126 set_irq_handler(i, handle_level_irq); 125 irq_set_status_flags(i, IRQ_LEVEL);
127 irq_desc[i].status |= IRQ_LEVEL;
128 set_irq_flags(i, IRQF_VALID); 126 set_irq_flags(i, IRQF_VALID);
129 } 127 }
130 set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); 128 irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
131} 129}
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index 71db2bdf2f28..c66c76346904 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -147,9 +147,6 @@ void __init dove_mpp_conf(unsigned int *mpp_list)
147 u32 pmu_sig_ctrl[PMU_SIG_REGS]; 147 u32 pmu_sig_ctrl[PMU_SIG_REGS];
148 int i; 148 int i;
149 149
150 /* Initialize gpiolib. */
151 orion_gpio_init();
152
153 for (i = 0; i < MPP_NR_REGS; i++) 150 for (i = 0; i < MPP_NR_REGS; i++)
154 mpp_ctrl[i] = readl(MPP_CTRL(i)); 151 mpp_ctrl[i] = readl(MPP_CTRL(i));
155 152
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 7df083f37fa7..087bc771ac23 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -66,8 +66,8 @@ static void __init ebsa110_init_irq(void)
66 local_irq_restore(flags); 66 local_irq_restore(flags);
67 67
68 for (irq = 0; irq < NR_IRQS; irq++) { 68 for (irq = 0; irq < NR_IRQS; irq++) {
69 set_irq_chip(irq, &ebsa110_irq_chip); 69 irq_set_chip_and_handler(irq, &ebsa110_irq_chip,
70 set_irq_handler(irq, handle_level_irq); 70 handle_level_irq);
71 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 71 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
72 } 72 }
73} 73}
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index 34e071d79761..180b8a9d0d21 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -117,7 +117,7 @@ static void ep93xx_gpio_irq_ack(struct irq_data *d)
117 int port = line >> 3; 117 int port = line >> 3;
118 int port_mask = 1 << (line & 7); 118 int port_mask = 1 << (line & 7);
119 119
120 if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 120 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
121 gpio_int_type2[port] ^= port_mask; /* switch edge direction */ 121 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
122 ep93xx_gpio_update_int_params(port); 122 ep93xx_gpio_update_int_params(port);
123 } 123 }
@@ -131,7 +131,7 @@ static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
131 int port = line >> 3; 131 int port = line >> 3;
132 int port_mask = 1 << (line & 7); 132 int port_mask = 1 << (line & 7);
133 133
134 if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 134 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
135 gpio_int_type2[port] ^= port_mask; /* switch edge direction */ 135 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
136 136
137 gpio_int_unmasked[port] &= ~port_mask; 137 gpio_int_unmasked[port] &= ~port_mask;
@@ -165,10 +165,10 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d)
165 */ 165 */
166static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) 166static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
167{ 167{
168 struct irq_desc *desc = irq_desc + d->irq;
169 const int gpio = irq_to_gpio(d->irq); 168 const int gpio = irq_to_gpio(d->irq);
170 const int port = gpio >> 3; 169 const int port = gpio >> 3;
171 const int port_mask = 1 << (gpio & 7); 170 const int port_mask = 1 << (gpio & 7);
171 irq_flow_handler_t handler;
172 172
173 gpio_direction_input(gpio); 173 gpio_direction_input(gpio);
174 174
@@ -176,22 +176,22 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
176 case IRQ_TYPE_EDGE_RISING: 176 case IRQ_TYPE_EDGE_RISING:
177 gpio_int_type1[port] |= port_mask; 177 gpio_int_type1[port] |= port_mask;
178 gpio_int_type2[port] |= port_mask; 178 gpio_int_type2[port] |= port_mask;
179 desc->handle_irq = handle_edge_irq; 179 handler = handle_edge_irq;
180 break; 180 break;
181 case IRQ_TYPE_EDGE_FALLING: 181 case IRQ_TYPE_EDGE_FALLING:
182 gpio_int_type1[port] |= port_mask; 182 gpio_int_type1[port] |= port_mask;
183 gpio_int_type2[port] &= ~port_mask; 183 gpio_int_type2[port] &= ~port_mask;
184 desc->handle_irq = handle_edge_irq; 184 handler = handle_edge_irq;
185 break; 185 break;
186 case IRQ_TYPE_LEVEL_HIGH: 186 case IRQ_TYPE_LEVEL_HIGH:
187 gpio_int_type1[port] &= ~port_mask; 187 gpio_int_type1[port] &= ~port_mask;
188 gpio_int_type2[port] |= port_mask; 188 gpio_int_type2[port] |= port_mask;
189 desc->handle_irq = handle_level_irq; 189 handler = handle_level_irq;
190 break; 190 break;
191 case IRQ_TYPE_LEVEL_LOW: 191 case IRQ_TYPE_LEVEL_LOW:
192 gpio_int_type1[port] &= ~port_mask; 192 gpio_int_type1[port] &= ~port_mask;
193 gpio_int_type2[port] &= ~port_mask; 193 gpio_int_type2[port] &= ~port_mask;
194 desc->handle_irq = handle_level_irq; 194 handler = handle_level_irq;
195 break; 195 break;
196 case IRQ_TYPE_EDGE_BOTH: 196 case IRQ_TYPE_EDGE_BOTH:
197 gpio_int_type1[port] |= port_mask; 197 gpio_int_type1[port] |= port_mask;
@@ -200,17 +200,16 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
200 gpio_int_type2[port] &= ~port_mask; /* falling */ 200 gpio_int_type2[port] &= ~port_mask; /* falling */
201 else 201 else
202 gpio_int_type2[port] |= port_mask; /* rising */ 202 gpio_int_type2[port] |= port_mask; /* rising */
203 desc->handle_irq = handle_edge_irq; 203 handler = handle_edge_irq;
204 break; 204 break;
205 default: 205 default:
206 pr_err("failed to set irq type %d for gpio %d\n", type, gpio); 206 pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
207 return -EINVAL; 207 return -EINVAL;
208 } 208 }
209 209
210 gpio_int_enabled[port] |= port_mask; 210 __irq_set_handler_locked(d->irq, handler);
211 211
212 desc->status &= ~IRQ_TYPE_SENSE_MASK; 212 gpio_int_enabled[port] |= port_mask;
213 desc->status |= type & IRQ_TYPE_SENSE_MASK;
214 213
215 ep93xx_gpio_update_int_params(port); 214 ep93xx_gpio_update_int_params(port);
216 215
@@ -232,20 +231,29 @@ void __init ep93xx_gpio_init_irq(void)
232 231
233 for (gpio_irq = gpio_to_irq(0); 232 for (gpio_irq = gpio_to_irq(0);
234 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { 233 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
235 set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip); 234 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
236 set_irq_handler(gpio_irq, handle_level_irq); 235 handle_level_irq);
237 set_irq_flags(gpio_irq, IRQF_VALID); 236 set_irq_flags(gpio_irq, IRQF_VALID);
238 } 237 }
239 238
240 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler); 239 irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
241 set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler); 240 ep93xx_gpio_ab_irq_handler);
242 set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler); 241 irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
243 set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler); 242 ep93xx_gpio_f_irq_handler);
244 set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler); 243 irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
245 set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler); 244 ep93xx_gpio_f_irq_handler);
246 set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler); 245 irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
247 set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler); 246 ep93xx_gpio_f_irq_handler);
248 set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler); 247 irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
248 ep93xx_gpio_f_irq_handler);
249 irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
250 ep93xx_gpio_f_irq_handler);
251 irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
252 ep93xx_gpio_f_irq_handler);
253 irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
254 ep93xx_gpio_f_irq_handler);
255 irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
256 ep93xx_gpio_f_irq_handler);
249} 257}
250 258
251 259
diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c
index 31618d91ce15..f488b66d6806 100644
--- a/arch/arm/mach-exynos4/irq-combiner.c
+++ b/arch/arm/mach-exynos4/irq-combiner.c
@@ -54,8 +54,8 @@ static void combiner_unmask_irq(struct irq_data *data)
54 54
55static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) 55static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
56{ 56{
57 struct combiner_chip_data *chip_data = get_irq_data(irq); 57 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
58 struct irq_chip *chip = get_irq_chip(irq); 58 struct irq_chip *chip = irq_get_chip(irq);
59 unsigned int cascade_irq, combiner_irq; 59 unsigned int cascade_irq, combiner_irq;
60 unsigned long status; 60 unsigned long status;
61 61
@@ -93,9 +93,9 @@ void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
93{ 93{
94 if (combiner_nr >= MAX_COMBINER_NR) 94 if (combiner_nr >= MAX_COMBINER_NR)
95 BUG(); 95 BUG();
96 if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0) 96 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
97 BUG(); 97 BUG();
98 set_irq_chained_handler(irq, combiner_handle_cascade_irq); 98 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
99} 99}
100 100
101void __init combiner_init(unsigned int combiner_nr, void __iomem *base, 101void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
@@ -119,9 +119,8 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
119 119
120 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset 120 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
121 + MAX_IRQ_IN_COMBINER; i++) { 121 + MAX_IRQ_IN_COMBINER; i++) {
122 set_irq_chip(i, &combiner_chip); 122 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
123 set_irq_chip_data(i, &combiner_data[combiner_nr]); 123 irq_set_chip_data(i, &combiner_data[combiner_nr]);
124 set_irq_handler(i, handle_level_irq);
125 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 124 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
126 } 125 }
127} 126}
diff --git a/arch/arm/mach-exynos4/irq-eint.c b/arch/arm/mach-exynos4/irq-eint.c
index 4f7ad4a796e4..9d87d2ac7f68 100644
--- a/arch/arm/mach-exynos4/irq-eint.c
+++ b/arch/arm/mach-exynos4/irq-eint.c
@@ -190,8 +190,8 @@ static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
190 190
191static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) 191static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
192{ 192{
193 u32 *irq_data = get_irq_data(irq); 193 u32 *irq_data = irq_get_handler_data(irq);
194 struct irq_chip *chip = get_irq_chip(irq); 194 struct irq_chip *chip = irq_get_chip(irq);
195 195
196 chip->irq_mask(&desc->irq_data); 196 chip->irq_mask(&desc->irq_data);
197 197
@@ -208,18 +208,19 @@ int __init exynos4_init_irq_eint(void)
208 int irq; 208 int irq;
209 209
210 for (irq = 0 ; irq <= 31 ; irq++) { 210 for (irq = 0 ; irq <= 31 ; irq++) {
211 set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint); 211 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
212 set_irq_handler(IRQ_EINT(irq), handle_level_irq); 212 handle_level_irq);
213 set_irq_flags(IRQ_EINT(irq), IRQF_VALID); 213 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
214 } 214 }
215 215
216 set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); 216 irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
217 217
218 for (irq = 0 ; irq <= 15 ; irq++) { 218 for (irq = 0 ; irq <= 15 ; irq++) {
219 eint0_15_data[irq] = IRQ_EINT(irq); 219 eint0_15_data[irq] = IRQ_EINT(irq);
220 220
221 set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]); 221 irq_set_handler_data(exynos4_get_irq_nr(irq),
222 set_irq_chained_handler(exynos4_get_irq_nr(irq), 222 &eint0_15_data[irq]);
223 irq_set_chained_handler(exynos4_get_irq_nr(irq),
223 exynos4_irq_eint0_15); 224 exynos4_irq_eint0_15);
224 } 225 }
225 226
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 84c5f258f2d8..38a44f9b9da2 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -102,8 +102,7 @@ static void __init __fb_init_irq(void)
102 *CSR_FIQ_DISABLE = -1; 102 *CSR_FIQ_DISABLE = -1;
103 103
104 for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { 104 for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
105 set_irq_chip(irq, &fb_chip); 105 irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq);
106 set_irq_handler(irq, handle_level_irq);
107 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 106 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
108 } 107 }
109} 108}
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c
index a921fe92b858..5f1f9867fc70 100644
--- a/arch/arm/mach-footbridge/dc21285-timer.c
+++ b/arch/arm/mach-footbridge/dc21285-timer.c
@@ -30,7 +30,7 @@ static int cksrc_dc21285_enable(struct clocksource *cs)
30 return 0; 30 return 0;
31} 31}
32 32
33static int cksrc_dc21285_disable(struct clocksource *cs) 33static void cksrc_dc21285_disable(struct clocksource *cs)
34{ 34{
35 *CSR_TIMER2_CNTL = 0; 35 *CSR_TIMER2_CNTL = 0;
36} 36}
diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c
index de7a5cb5dbe1..c3a0abbc9049 100644
--- a/arch/arm/mach-footbridge/isa-irq.c
+++ b/arch/arm/mach-footbridge/isa-irq.c
@@ -151,14 +151,14 @@ void __init isa_init_irq(unsigned int host_irq)
151 151
152 if (host_irq != (unsigned int)-1) { 152 if (host_irq != (unsigned int)-1) {
153 for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) { 153 for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
154 set_irq_chip(irq, &isa_lo_chip); 154 irq_set_chip_and_handler(irq, &isa_lo_chip,
155 set_irq_handler(irq, handle_level_irq); 155 handle_level_irq);
156 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 156 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
157 } 157 }
158 158
159 for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) { 159 for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
160 set_irq_chip(irq, &isa_hi_chip); 160 irq_set_chip_and_handler(irq, &isa_hi_chip,
161 set_irq_handler(irq, handle_level_irq); 161 handle_level_irq);
162 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 162 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
163 } 163 }
164 164
@@ -166,7 +166,7 @@ void __init isa_init_irq(unsigned int host_irq)
166 request_resource(&ioport_resource, &pic2_resource); 166 request_resource(&ioport_resource, &pic2_resource);
167 setup_irq(IRQ_ISA_CASCADE, &irq_cascade); 167 setup_irq(IRQ_ISA_CASCADE, &irq_cascade);
168 168
169 set_irq_chained_handler(host_irq, isa_irq_handler); 169 irq_set_chained_handler(host_irq, isa_irq_handler);
170 170
171 /* 171 /*
172 * On the NetWinder, don't automatically 172 * On the NetWinder, don't automatically
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c
index fa3d333f21e1..fdc7ef1391d3 100644
--- a/arch/arm/mach-gemini/gpio.c
+++ b/arch/arm/mach-gemini/gpio.c
@@ -127,8 +127,8 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
127 127
128static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 128static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
129{ 129{
130 unsigned int port = (unsigned int)irq_desc_get_handler_data(desc);
130 unsigned int gpio_irq_no, irq_stat; 131 unsigned int gpio_irq_no, irq_stat;
131 unsigned int port = (unsigned int)get_irq_data(irq);
132 132
133 irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT); 133 irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT);
134 134
@@ -138,9 +138,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
138 if ((irq_stat & 1) == 0) 138 if ((irq_stat & 1) == 0)
139 continue; 139 continue;
140 140
141 BUG_ON(!(irq_desc[gpio_irq_no].handle_irq)); 141 generic_handle_irq(gpio_irq_no);
142 irq_desc[gpio_irq_no].handle_irq(gpio_irq_no,
143 &irq_desc[gpio_irq_no]);
144 } 142 }
145} 143}
146 144
@@ -219,13 +217,13 @@ void __init gemini_gpio_init(void)
219 217
220 for (j = GPIO_IRQ_BASE + i * 32; 218 for (j = GPIO_IRQ_BASE + i * 32;
221 j < GPIO_IRQ_BASE + (i + 1) * 32; j++) { 219 j < GPIO_IRQ_BASE + (i + 1) * 32; j++) {
222 set_irq_chip(j, &gpio_irq_chip); 220 irq_set_chip_and_handler(j, &gpio_irq_chip,
223 set_irq_handler(j, handle_edge_irq); 221 handle_edge_irq);
224 set_irq_flags(j, IRQF_VALID); 222 set_irq_flags(j, IRQF_VALID);
225 } 223 }
226 224
227 set_irq_chained_handler(IRQ_GPIO(i), gpio_irq_handler); 225 irq_set_chained_handler(IRQ_GPIO(i), gpio_irq_handler);
228 set_irq_data(IRQ_GPIO(i), (void *)i); 226 irq_set_handler_data(IRQ_GPIO(i), (void *)i);
229 } 227 }
230 228
231 BUG_ON(gpiochip_add(&gemini_gpio_chip)); 229 BUG_ON(gpiochip_add(&gemini_gpio_chip));
diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c
index 96bc227dd849..9485a8fdf851 100644
--- a/arch/arm/mach-gemini/irq.c
+++ b/arch/arm/mach-gemini/irq.c
@@ -81,13 +81,13 @@ void __init gemini_init_irq(void)
81 request_resource(&iomem_resource, &irq_resource); 81 request_resource(&iomem_resource, &irq_resource);
82 82
83 for (i = 0; i < NR_IRQS; i++) { 83 for (i = 0; i < NR_IRQS; i++) {
84 set_irq_chip(i, &gemini_irq_chip); 84 irq_set_chip(i, &gemini_irq_chip);
85 if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) { 85 if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) {
86 set_irq_handler(i, handle_edge_irq); 86 irq_set_handler(i, handle_edge_irq);
87 mode |= 1 << i; 87 mode |= 1 << i;
88 level |= 1 << i; 88 level |= 1 << i;
89 } else { 89 } else {
90 set_irq_handler(i, handle_level_irq); 90 irq_set_handler(i, handle_level_irq);
91 } 91 }
92 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 92 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
93 } 93 }
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index 1f28c90932c7..51d4e44ab973 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -199,29 +199,29 @@ void __init h720x_init_irq (void)
199 199
200 /* Initialize global IRQ's, fast path */ 200 /* Initialize global IRQ's, fast path */
201 for (irq = 0; irq < NR_GLBL_IRQS; irq++) { 201 for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
202 set_irq_chip(irq, &h720x_global_chip); 202 irq_set_chip_and_handler(irq, &h720x_global_chip,
203 set_irq_handler(irq, handle_level_irq); 203 handle_level_irq);
204 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 204 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
205 } 205 }
206 206
207 /* Initialize multiplexed IRQ's, slow path */ 207 /* Initialize multiplexed IRQ's, slow path */
208 for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { 208 for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
209 set_irq_chip(irq, &h720x_gpio_chip); 209 irq_set_chip_and_handler(irq, &h720x_gpio_chip,
210 set_irq_handler(irq, handle_edge_irq); 210 handle_edge_irq);
211 set_irq_flags(irq, IRQF_VALID ); 211 set_irq_flags(irq, IRQF_VALID );
212 } 212 }
213 set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); 213 irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
214 set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); 214 irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
215 set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); 215 irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
216 set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); 216 irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
217 217
218#ifdef CONFIG_CPU_H7202 218#ifdef CONFIG_CPU_H7202
219 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { 219 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
220 set_irq_chip(irq, &h720x_gpio_chip); 220 irq_set_chip_and_handler(irq, &h720x_gpio_chip,
221 set_irq_handler(irq, handle_edge_irq); 221 handle_edge_irq);
222 set_irq_flags(irq, IRQF_VALID ); 222 set_irq_flags(irq, IRQF_VALID );
223 } 223 }
224 set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); 224 irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
225#endif 225#endif
226 226
227 /* Enable multiplexed irq's */ 227 /* Enable multiplexed irq's */
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
index ac3f91442376..c37d570b852d 100644
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ b/arch/arm/mach-h720x/cpu-h7202.c
@@ -141,13 +141,18 @@ h7202_timer_interrupt(int irq, void *dev_id)
141/* 141/*
142 * mask multiplexed timer IRQs 142 * mask multiplexed timer IRQs
143 */ 143 */
144static void inline mask_timerx_irq(struct irq_data *d) 144static void inline __mask_timerx_irq(unsigned int irq)
145{ 145{
146 unsigned int bit; 146 unsigned int bit;
147 bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1)); 147 bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
148 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit; 148 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
149} 149}
150 150
151static void inline mask_timerx_irq(struct irq_data *d)
152{
153 __mask_timerx_irq(d->irq);
154}
155
151/* 156/*
152 * unmask multiplexed timer IRQs 157 * unmask multiplexed timer IRQs
153 */ 158 */
@@ -196,12 +201,12 @@ void __init h7202_init_irq (void)
196 201
197 for (irq = IRQ_TIMER1; 202 for (irq = IRQ_TIMER1;
198 irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) { 203 irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
199 mask_timerx_irq(irq); 204 __mask_timerx_irq(irq);
200 set_irq_chip(irq, &h7202_timerx_chip); 205 irq_set_chip_and_handler(irq, &h7202_timerx_chip,
201 set_irq_handler(irq, handle_edge_irq); 206 handle_edge_irq);
202 set_irq_flags(irq, IRQF_VALID ); 207 set_irq_flags(irq, IRQF_VALID );
203 } 208 }
204 set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); 209 irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
205 210
206 h720x_init_irq(); 211 h720x_init_irq();
207} 212}
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 5eec099e0c72..56b930a13443 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -255,6 +255,7 @@ config MACH_IMX27_VISSTRIM_M10
255 bool "Vista Silicon i.MX27 Visstrim_m10" 255 bool "Vista Silicon i.MX27 Visstrim_m10"
256 select SOC_IMX27 256 select SOC_IMX27
257 select IMX_HAVE_PLATFORM_IMX_I2C 257 select IMX_HAVE_PLATFORM_IMX_I2C
258 select IMX_HAVE_PLATFORM_IMX_SSI
258 select IMX_HAVE_PLATFORM_IMX_UART 259 select IMX_HAVE_PLATFORM_IMX_UART
259 select IMX_HAVE_PLATFORM_MXC_MMC 260 select IMX_HAVE_PLATFORM_MXC_MMC
260 select IMX_HAVE_PLATFORM_MXC_EHCI 261 select IMX_HAVE_PLATFORM_MXC_EHCI
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index cb705c28de02..6269053505f7 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -34,6 +34,7 @@
34#include <mach/mx25.h> 34#include <mach/mx25.h>
35#include <mach/imx-uart.h> 35#include <mach/imx-uart.h>
36#include <mach/audmux.h> 36#include <mach/audmux.h>
37#include <mach/esdhc.h>
37 38
38#include "devices-imx25.h" 39#include "devices-imx25.h"
39 40
@@ -242,6 +243,11 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
242 .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, 243 .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
243}; 244};
244 245
246static struct esdhc_platform_data sd1_pdata = {
247 .cd_gpio = GPIO_SD1CD,
248 .wp_gpio = -EINVAL,
249};
250
245/* 251/*
246 * system init for baseboard usage. Will be called by cpuimx25 init. 252 * system init for baseboard usage. Will be called by cpuimx25 init.
247 * 253 *
@@ -275,7 +281,7 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
275 imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); 281 imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
276 282
277 imx25_add_flexcan1(NULL); 283 imx25_add_flexcan1(NULL);
278 imx25_add_sdhci_esdhc_imx(0, NULL); 284 imx25_add_sdhci_esdhc_imx(0, &sd1_pdata);
279 285
280 gpio_request(GPIO_LED1, "LED1"); 286 gpio_request(GPIO_LED1, "LED1");
281 gpio_direction_output(GPIO_LED1, 1); 287 gpio_direction_output(GPIO_LED1, 1);
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
index a233470dd10c..bc739701c301 100644
--- a/arch/arm/mach-iop13xx/irq.c
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -224,15 +224,15 @@ void __init iop13xx_init_irq(void)
224 224
225 for(i = 0; i <= IRQ_IOP13XX_HPI; i++) { 225 for(i = 0; i <= IRQ_IOP13XX_HPI; i++) {
226 if (i < 32) 226 if (i < 32)
227 set_irq_chip(i, &iop13xx_irqchip1); 227 irq_set_chip(i, &iop13xx_irqchip1);
228 else if (i < 64) 228 else if (i < 64)
229 set_irq_chip(i, &iop13xx_irqchip2); 229 irq_set_chip(i, &iop13xx_irqchip2);
230 else if (i < 96) 230 else if (i < 96)
231 set_irq_chip(i, &iop13xx_irqchip3); 231 irq_set_chip(i, &iop13xx_irqchip3);
232 else 232 else
233 set_irq_chip(i, &iop13xx_irqchip4); 233 irq_set_chip(i, &iop13xx_irqchip4);
234 234
235 set_irq_handler(i, handle_level_irq); 235 irq_set_handler(i, handle_level_irq);
236 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 236 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
237 } 237 }
238 238
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c
index c9c02e3698bc..560d5b2dec22 100644
--- a/arch/arm/mach-iop13xx/msi.c
+++ b/arch/arm/mach-iop13xx/msi.c
@@ -118,7 +118,7 @@ static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc)
118 118
119void __init iop13xx_msi_init(void) 119void __init iop13xx_msi_init(void)
120{ 120{
121 set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); 121 irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
122} 122}
123 123
124/* 124/*
@@ -178,7 +178,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
178 if (irq < 0) 178 if (irq < 0)
179 return irq; 179 return irq;
180 180
181 set_irq_msi(irq, desc); 181 irq_set_msi_desc(irq, desc);
182 182
183 msg.address_hi = 0x0; 183 msg.address_hi = 0x0;
184 msg.address_lo = IOP13XX_MU_MIMR_PCI; 184 msg.address_lo = IOP13XX_MU_MIMR_PCI;
@@ -187,7 +187,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
187 msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); 187 msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f);
188 188
189 write_msi_msg(irq, &msg); 189 write_msi_msg(irq, &msg);
190 set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); 190 irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
191 191
192 return 0; 192 return 0;
193} 193}
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index d3426a120599..d7ee2789d890 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -68,8 +68,7 @@ void __init iop32x_init_irq(void)
68 *IOP3XX_PCIIRSR = 0x0f; 68 *IOP3XX_PCIIRSR = 0x0f;
69 69
70 for (i = 0; i < NR_IRQS; i++) { 70 for (i = 0; i < NR_IRQS; i++) {
71 set_irq_chip(i, &ext_chip); 71 irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);
72 set_irq_handler(i, handle_level_irq);
73 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 72 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
74 } 73 }
75} 74}
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index 0ff2f74363a5..f7f5d3e451c7 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -110,8 +110,9 @@ void __init iop33x_init_irq(void)
110 *IOP3XX_PCIIRSR = 0x0f; 110 *IOP3XX_PCIIRSR = 0x0f;
111 111
112 for (i = 0; i < NR_IRQS; i++) { 112 for (i = 0; i < NR_IRQS; i++) {
113 set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2); 113 irq_set_chip_and_handler(i,
114 set_irq_handler(i, handle_level_irq); 114 (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2,
115 handle_level_irq);
115 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 116 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
116 } 117 }
117} 118}
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 5fc4e064b650..4068166c8993 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -476,8 +476,8 @@ void __init ixp2000_init_irq(void)
476 */ 476 */
477 for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { 477 for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
478 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { 478 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
479 set_irq_chip(irq, &ixp2000_irq_chip); 479 irq_set_chip_and_handler(irq, &ixp2000_irq_chip,
480 set_irq_handler(irq, handle_level_irq); 480 handle_level_irq);
481 set_irq_flags(irq, IRQF_VALID); 481 set_irq_flags(irq, IRQF_VALID);
482 } else set_irq_flags(irq, 0); 482 } else set_irq_flags(irq, 0);
483 } 483 }
@@ -485,21 +485,21 @@ void __init ixp2000_init_irq(void)
485 for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) { 485 for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
486 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & 486 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
487 IXP2000_VALID_ERR_IRQ_MASK) { 487 IXP2000_VALID_ERR_IRQ_MASK) {
488 set_irq_chip(irq, &ixp2000_err_irq_chip); 488 irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip,
489 set_irq_handler(irq, handle_level_irq); 489 handle_level_irq);
490 set_irq_flags(irq, IRQF_VALID); 490 set_irq_flags(irq, IRQF_VALID);
491 } 491 }
492 else 492 else
493 set_irq_flags(irq, 0); 493 set_irq_flags(irq, 0);
494 } 494 }
495 set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); 495 irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
496 496
497 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { 497 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
498 set_irq_chip(irq, &ixp2000_GPIO_irq_chip); 498 irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip,
499 set_irq_handler(irq, handle_level_irq); 499 handle_level_irq);
500 set_irq_flags(irq, IRQF_VALID); 500 set_irq_flags(irq, IRQF_VALID);
501 } 501 }
502 set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); 502 irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
503 503
504 /* 504 /*
505 * Enable PCI irqs. The actual PCI[AB] decoding is done in 505 * Enable PCI irqs. The actual PCI[AB] decoding is done in
@@ -508,8 +508,8 @@ void __init ixp2000_init_irq(void)
508 */ 508 */
509 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); 509 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
510 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { 510 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
511 set_irq_chip(irq, &ixp2000_pci_irq_chip); 511 irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip,
512 set_irq_handler(irq, handle_level_irq); 512 handle_level_irq);
513 set_irq_flags(irq, IRQF_VALID); 513 set_irq_flags(irq, IRQF_VALID);
514 } 514 }
515} 515}
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index 7d90d3f13ee8..235638f800e5 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -158,13 +158,13 @@ void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigne
158 *board_irq_mask = 0xffffffff; 158 *board_irq_mask = 0xffffffff;
159 159
160 for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { 160 for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
161 set_irq_chip(irq, &ixdp2x00_cpld_irq_chip); 161 irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip,
162 set_irq_handler(irq, handle_level_irq); 162 handle_level_irq);
163 set_irq_flags(irq, IRQF_VALID); 163 set_irq_flags(irq, IRQF_VALID);
164 } 164 }
165 165
166 /* Hook into PCI interrupt */ 166 /* Hook into PCI interrupt */
167 set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler); 167 irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler);
168} 168}
169 169
170/************************************************************************* 170/*************************************************************************
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 34b1b2af37c8..84835b209557 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -115,8 +115,8 @@ void __init ixdp2x01_init_irq(void)
115 115
116 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { 116 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
117 if (irq & valid_irq_mask) { 117 if (irq & valid_irq_mask) {
118 set_irq_chip(irq, &ixdp2x01_irq_chip); 118 irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip,
119 set_irq_handler(irq, handle_level_irq); 119 handle_level_irq);
120 set_irq_flags(irq, IRQF_VALID); 120 set_irq_flags(irq, IRQF_VALID);
121 } else { 121 } else {
122 set_irq_flags(irq, 0); 122 set_irq_flags(irq, 0);
@@ -124,7 +124,7 @@ void __init ixdp2x01_init_irq(void)
124 } 124 }
125 125
126 /* Hook into PCI interrupts */ 126 /* Hook into PCI interrupts */
127 set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler); 127 irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
128} 128}
129 129
130 130
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index 9c8a33903216..a1bee33d183e 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -289,12 +289,12 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
289{ 289{
290 switch (type) { 290 switch (type) {
291 case IXP23XX_IRQ_LEVEL: 291 case IXP23XX_IRQ_LEVEL:
292 set_irq_chip(irq, &ixp23xx_irq_level_chip); 292 irq_set_chip_and_handler(irq, &ixp23xx_irq_level_chip,
293 set_irq_handler(irq, handle_level_irq); 293 handle_level_irq);
294 break; 294 break;
295 case IXP23XX_IRQ_EDGE: 295 case IXP23XX_IRQ_EDGE:
296 set_irq_chip(irq, &ixp23xx_irq_edge_chip); 296 irq_set_chip_and_handler(irq, &ixp23xx_irq_edge_chip,
297 set_irq_handler(irq, handle_edge_irq); 297 handle_edge_irq);
298 break; 298 break;
299 } 299 }
300 set_irq_flags(irq, IRQF_VALID); 300 set_irq_flags(irq, IRQF_VALID);
@@ -324,12 +324,12 @@ void __init ixp23xx_init_irq(void)
324 } 324 }
325 325
326 for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) { 326 for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
327 set_irq_chip(irq, &ixp23xx_pci_irq_chip); 327 irq_set_chip_and_handler(irq, &ixp23xx_pci_irq_chip,
328 set_irq_handler(irq, handle_level_irq); 328 handle_level_irq);
329 set_irq_flags(irq, IRQF_VALID); 329 set_irq_flags(irq, IRQF_VALID);
330 } 330 }
331 331
332 set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler); 332 irq_set_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
333} 333}
334 334
335 335
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index 181116aa6591..8dcba17c81e7 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -136,8 +136,8 @@ void __init ixdp2351_init_irq(void)
136 irq++) { 136 irq++) {
137 if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) { 137 if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
138 set_irq_flags(irq, IRQF_VALID); 138 set_irq_flags(irq, IRQF_VALID);
139 set_irq_handler(irq, handle_level_irq); 139 irq_set_chip_and_handler(irq, &ixdp2351_inta_chip,
140 set_irq_chip(irq, &ixdp2351_inta_chip); 140 handle_level_irq);
141 } 141 }
142 } 142 }
143 143
@@ -147,13 +147,13 @@ void __init ixdp2351_init_irq(void)
147 irq++) { 147 irq++) {
148 if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) { 148 if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
149 set_irq_flags(irq, IRQF_VALID); 149 set_irq_flags(irq, IRQF_VALID);
150 set_irq_handler(irq, handle_level_irq); 150 irq_set_chip_and_handler(irq, &ixdp2351_intb_chip,
151 set_irq_chip(irq, &ixdp2351_intb_chip); 151 handle_level_irq);
152 } 152 }
153 } 153 }
154 154
155 set_irq_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler); 155 irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler);
156 set_irq_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler); 156 irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler);
157} 157}
158 158
159/* 159/*
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
index 76c61ba73218..8fe0c6273262 100644
--- a/arch/arm/mach-ixp23xx/roadrunner.c
+++ b/arch/arm/mach-ixp23xx/roadrunner.c
@@ -110,8 +110,8 @@ static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
110 110
111static void __init roadrunner_pci_preinit(void) 111static void __init roadrunner_pci_preinit(void)
112{ 112{
113 set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW); 113 irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
114 set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW); 114 irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
115 115
116 ixp23xx_pci_preinit(); 116 ixp23xx_pci_preinit();
117} 117}
diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c
index 845e1b500548..162043ff29ff 100644
--- a/arch/arm/mach-ixp4xx/avila-pci.c
+++ b/arch/arm/mach-ixp4xx/avila-pci.c
@@ -39,10 +39,10 @@
39 39
40void __init avila_pci_preinit(void) 40void __init avila_pci_preinit(void)
41{ 41{
42 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); 42 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
43 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); 43 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
44 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); 44 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
45 set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); 45 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
46 ixp4xx_pci_preinit(); 46 ixp4xx_pci_preinit();
47} 47}
48 48
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 9fd894271d5d..ed19bc314318 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -252,8 +252,8 @@ void __init ixp4xx_init_irq(void)
252 252
253 /* Default to all level triggered */ 253 /* Default to all level triggered */
254 for(i = 0; i < NR_IRQS; i++) { 254 for(i = 0; i < NR_IRQS; i++) {
255 set_irq_chip(i, &ixp4xx_irq_chip); 255 irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
256 set_irq_handler(i, handle_level_irq); 256 handle_level_irq);
257 set_irq_flags(i, IRQF_VALID); 257 set_irq_flags(i, IRQF_VALID);
258 } 258 }
259} 259}
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c
index b978ea8bd6f0..37fda7d6e83d 100644
--- a/arch/arm/mach-ixp4xx/coyote-pci.c
+++ b/arch/arm/mach-ixp4xx/coyote-pci.c
@@ -32,8 +32,8 @@
32 32
33void __init coyote_pci_preinit(void) 33void __init coyote_pci_preinit(void)
34{ 34{
35 set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); 35 irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
36 set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); 36 irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
37 ixp4xx_pci_preinit(); 37 ixp4xx_pci_preinit();
38} 38}
39 39
diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c
index fa70fed462ba..c7612010b3fc 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-pci.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c
@@ -35,12 +35,12 @@
35 35
36void __init dsmg600_pci_preinit(void) 36void __init dsmg600_pci_preinit(void)
37{ 37{
38 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); 38 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
39 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); 39 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
40 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); 40 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
41 set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); 41 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
42 set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); 42 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
43 set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); 43 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
44 ixp4xx_pci_preinit(); 44 ixp4xx_pci_preinit();
45} 45}
46 46
diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c
index 5a810c930624..44ccde9d4879 100644
--- a/arch/arm/mach-ixp4xx/fsg-pci.c
+++ b/arch/arm/mach-ixp4xx/fsg-pci.c
@@ -32,9 +32,9 @@
32 32
33void __init fsg_pci_preinit(void) 33void __init fsg_pci_preinit(void)
34{ 34{
35 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); 35 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
36 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); 36 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
37 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); 37 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
38 ixp4xx_pci_preinit(); 38 ixp4xx_pci_preinit();
39} 39}
40 40
diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c
index 7e93a0975c4d..fc1124168874 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-pci.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c
@@ -29,8 +29,8 @@
29 29
30void __init gateway7001_pci_preinit(void) 30void __init gateway7001_pci_preinit(void)
31{ 31{
32 set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); 32 irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
33 set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); 33 irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
34 34
35 ixp4xx_pci_preinit(); 35 ixp4xx_pci_preinit();
36} 36}
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index d0e4861ac03d..3e8c0e33b59c 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -420,8 +420,8 @@ static void __init gmlr_init(void)
420 gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); 420 gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT);
421 gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); 421 gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN);
422 gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); 422 gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN);
423 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); 423 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
424 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); 424 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
425 425
426 set_control(CONTROL_HSS0_DTR_N, 1); 426 set_control(CONTROL_HSS0_DTR_N, 1);
427 set_control(CONTROL_HSS1_DTR_N, 1); 427 set_control(CONTROL_HSS1_DTR_N, 1);
@@ -441,10 +441,10 @@ static void __init gmlr_init(void)
441#ifdef CONFIG_PCI 441#ifdef CONFIG_PCI
442static void __init gmlr_pci_preinit(void) 442static void __init gmlr_pci_preinit(void)
443{ 443{
444 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); 444 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
445 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); 445 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
446 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); 446 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
447 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); 447 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
448 ixp4xx_pci_preinit(); 448 ixp4xx_pci_preinit();
449} 449}
450 450
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
index 25d2c333c204..38cc0725dbd8 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
@@ -43,8 +43,8 @@
43 */ 43 */
44void __init gtwx5715_pci_preinit(void) 44void __init gtwx5715_pci_preinit(void)
45{ 45{
46 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); 46 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
47 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); 47 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
48 ixp4xx_pci_preinit(); 48 ixp4xx_pci_preinit();
49} 49}
50 50
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c
index 1ba165a6edac..58f400417eaf 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
@@ -36,10 +36,10 @@
36 36
37void __init ixdp425_pci_preinit(void) 37void __init ixdp425_pci_preinit(void)
38{ 38{
39 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); 39 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
40 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); 40 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
41 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); 41 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
42 set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); 42 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
43 ixp4xx_pci_preinit(); 43 ixp4xx_pci_preinit();
44} 44}
45 45
diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
index 4ed7ac614920..e64f6d041488 100644
--- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
@@ -25,8 +25,8 @@
25 25
26void __init ixdpg425_pci_preinit(void) 26void __init ixdpg425_pci_preinit(void)
27{ 27{
28 set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); 28 irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
29 set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); 29 irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
30 30
31 ixp4xx_pci_preinit(); 31 ixp4xx_pci_preinit();
32} 32}
diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c
index d0cea34cf61e..428d1202b799 100644
--- a/arch/arm/mach-ixp4xx/nas100d-pci.c
+++ b/arch/arm/mach-ixp4xx/nas100d-pci.c
@@ -33,11 +33,11 @@
33 33
34void __init nas100d_pci_preinit(void) 34void __init nas100d_pci_preinit(void)
35{ 35{
36 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); 36 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
37 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); 37 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
38 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); 38 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
39 set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); 39 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
40 set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); 40 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
41 ixp4xx_pci_preinit(); 41 ixp4xx_pci_preinit();
42} 42}
43 43
diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c
index 1eb5a90470bc..2e85f76b950d 100644
--- a/arch/arm/mach-ixp4xx/nslu2-pci.c
+++ b/arch/arm/mach-ixp4xx/nslu2-pci.c
@@ -32,9 +32,9 @@
32 32
33void __init nslu2_pci_preinit(void) 33void __init nslu2_pci_preinit(void)
34{ 34{
35 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); 35 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
36 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); 36 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
37 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); 37 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
38 ixp4xx_pci_preinit(); 38 ixp4xx_pci_preinit();
39} 39}
40 40
diff --git a/arch/arm/mach-ixp4xx/vulcan-pci.c b/arch/arm/mach-ixp4xx/vulcan-pci.c
index f3111c6840ef..03bdec5140a7 100644
--- a/arch/arm/mach-ixp4xx/vulcan-pci.c
+++ b/arch/arm/mach-ixp4xx/vulcan-pci.c
@@ -38,8 +38,8 @@ void __init vulcan_pci_preinit(void)
38 pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n", 38 pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
39 (int)(pci_cardbus_mem_size >> 20)); 39 (int)(pci_cardbus_mem_size >> 20));
40#endif 40#endif
41 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); 41 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
42 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); 42 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
43 ixp4xx_pci_preinit(); 43 ixp4xx_pci_preinit();
44} 44}
45 45
diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c
index 9b59ed03b151..17f3cf59a31b 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-pci.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c
@@ -29,8 +29,8 @@
29 29
30void __init wg302v2_pci_preinit(void) 30void __init wg302v2_pci_preinit(void)
31{ 31{
32 set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); 32 irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
33 set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); 33 irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
34 34
35 ixp4xx_pci_preinit(); 35 ixp4xx_pci_preinit();
36} 36}
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index cbdb5863d13b..05d193a25b25 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -35,14 +35,15 @@ void __init kirkwood_init_irq(void)
35 */ 35 */
36 orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0, 36 orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0,
37 IRQ_KIRKWOOD_GPIO_START); 37 IRQ_KIRKWOOD_GPIO_START);
38 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); 38 irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
39 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); 39 irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
40 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); 40 irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
41 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); 41 irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
42 42
43 orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0, 43 orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0,
44 IRQ_KIRKWOOD_GPIO_START + 32); 44 IRQ_KIRKWOOD_GPIO_START + 32);
45 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); 45 irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
46 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); 46 irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
47 set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler); 47 irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23,
48 gpio_irq_handler);
48} 49}
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index 0a95063f6d32..17de0bf53c08 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -58,6 +58,12 @@ static struct mvsdio_platform_data sheeva_esata_mvsdio_data = {
58 58
59static struct gpio_led sheevaplug_led_pins[] = { 59static struct gpio_led sheevaplug_led_pins[] = {
60 { 60 {
61 .name = "plug:red:misc",
62 .default_trigger = "none",
63 .gpio = 46,
64 .active_low = 1,
65 },
66 {
61 .name = "plug:green:health", 67 .name = "plug:green:health",
62 .default_trigger = "default-on", 68 .default_trigger = "default-on",
63 .gpio = 49, 69 .gpio = 49,
@@ -80,6 +86,7 @@ static struct platform_device sheevaplug_leds = {
80 86
81static unsigned int sheevaplug_mpp_config[] __initdata = { 87static unsigned int sheevaplug_mpp_config[] __initdata = {
82 MPP29_GPIO, /* USB Power Enable */ 88 MPP29_GPIO, /* USB Power Enable */
89 MPP46_GPIO, /* LED Red */
83 MPP49_GPIO, /* LED */ 90 MPP49_GPIO, /* LED */
84 0 91 0
85}; 92};
diff --git a/arch/arm/mach-ks8695/gpio.c b/arch/arm/mach-ks8695/gpio.c
index 55fbf7111a5b..31e456508a6f 100644
--- a/arch/arm/mach-ks8695/gpio.c
+++ b/arch/arm/mach-ks8695/gpio.c
@@ -80,7 +80,7 @@ int ks8695_gpio_interrupt(unsigned int pin, unsigned int type)
80 local_irq_restore(flags); 80 local_irq_restore(flags);
81 81
82 /* Set IRQ triggering type */ 82 /* Set IRQ triggering type */
83 set_irq_type(gpio_irq[pin], type); 83 irq_set_irq_type(gpio_irq[pin], type);
84 84
85 /* enable interrupt mode */ 85 /* enable interrupt mode */
86 ks8695_gpio_mode(pin, 0); 86 ks8695_gpio_mode(pin, 0);
diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c
index 7998ccaa6333..a78092dcd6fb 100644
--- a/arch/arm/mach-ks8695/irq.c
+++ b/arch/arm/mach-ks8695/irq.c
@@ -115,12 +115,12 @@ static int ks8695_irq_set_type(struct irq_data *d, unsigned int type)
115 } 115 }
116 116
117 if (level_triggered) { 117 if (level_triggered) {
118 set_irq_chip(d->irq, &ks8695_irq_level_chip); 118 irq_set_chip_and_handler(d->irq, &ks8695_irq_level_chip,
119 set_irq_handler(d->irq, handle_level_irq); 119 handle_level_irq);
120 } 120 }
121 else { 121 else {
122 set_irq_chip(d->irq, &ks8695_irq_edge_chip); 122 irq_set_chip_and_handler(d->irq, &ks8695_irq_edge_chip,
123 set_irq_handler(d->irq, handle_edge_irq); 123 handle_edge_irq);
124 } 124 }
125 125
126 __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC); 126 __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC);
@@ -158,16 +158,18 @@ void __init ks8695_init_irq(void)
158 case KS8695_IRQ_UART_RX: 158 case KS8695_IRQ_UART_RX:
159 case KS8695_IRQ_COMM_TX: 159 case KS8695_IRQ_COMM_TX:
160 case KS8695_IRQ_COMM_RX: 160 case KS8695_IRQ_COMM_RX:
161 set_irq_chip(irq, &ks8695_irq_level_chip); 161 irq_set_chip_and_handler(irq,
162 set_irq_handler(irq, handle_level_irq); 162 &ks8695_irq_level_chip,
163 handle_level_irq);
163 break; 164 break;
164 165
165 /* Edge-triggered interrupts */ 166 /* Edge-triggered interrupts */
166 default: 167 default:
167 /* clear pending bit */ 168 /* clear pending bit */
168 ks8695_irq_ack(irq_get_irq_data(irq)); 169 ks8695_irq_ack(irq_get_irq_data(irq));
169 set_irq_chip(irq, &ks8695_irq_edge_chip); 170 irq_set_chip_and_handler(irq,
170 set_irq_handler(irq, handle_edge_irq); 171 &ks8695_irq_edge_chip,
172 handle_edge_irq);
171 } 173 }
172 174
173 set_irq_flags(irq, IRQF_VALID); 175 set_irq_flags(irq, IRQF_VALID);
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index 316ecbf6c586..4eae566dfdc7 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -290,7 +290,7 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
290 } 290 }
291 291
292 /* Ok to use the level handler for all types */ 292 /* Ok to use the level handler for all types */
293 set_irq_handler(d->irq, handle_level_irq); 293 irq_set_handler(d->irq, handle_level_irq);
294 294
295 return 0; 295 return 0;
296} 296}
@@ -390,8 +390,8 @@ void __init lpc32xx_init_irq(void)
390 390
391 /* Configure supported IRQ's */ 391 /* Configure supported IRQ's */
392 for (i = 0; i < NR_IRQS; i++) { 392 for (i = 0; i < NR_IRQS; i++) {
393 set_irq_chip(i, &lpc32xx_irq_chip); 393 irq_set_chip_and_handler(i, &lpc32xx_irq_chip,
394 set_irq_handler(i, handle_level_irq); 394 handle_level_irq);
395 set_irq_flags(i, IRQF_VALID); 395 set_irq_flags(i, IRQF_VALID);
396 } 396 }
397 397
@@ -406,8 +406,8 @@ void __init lpc32xx_init_irq(void)
406 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); 406 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
407 407
408 /* MIC SUBIRQx interrupts will route handling to the chain handlers */ 408 /* MIC SUBIRQx interrupts will route handling to the chain handlers */
409 set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); 409 irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
410 set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); 410 irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
411 411
412 /* Initially disable all wake events */ 412 /* Initially disable all wake events */
413 __raw_writel(0, LPC32XX_CLKPWR_P01_ER); 413 __raw_writel(0, LPC32XX_CLKPWR_P01_ER);
diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c
index fa037038e7b8..d21c5441a3d0 100644
--- a/arch/arm/mach-mmp/irq-mmp2.c
+++ b/arch/arm/mach-mmp/irq-mmp2.c
@@ -110,9 +110,9 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num)
110 if (chip->irq_ack) 110 if (chip->irq_ack)
111 chip->irq_ack(d); 111 chip->irq_ack(d);
112 112
113 set_irq_chip(irq, chip); 113 irq_set_chip(irq, chip);
114 set_irq_flags(irq, IRQF_VALID); 114 set_irq_flags(irq, IRQF_VALID);
115 set_irq_handler(irq, handle_level_irq); 115 irq_set_handler(irq, handle_level_irq);
116 } 116 }
117} 117}
118 118
@@ -122,7 +122,7 @@ void __init mmp2_init_icu(void)
122 122
123 for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { 123 for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
124 icu_mask_irq(irq_get_irq_data(irq)); 124 icu_mask_irq(irq_get_irq_data(irq));
125 set_irq_chip(irq, &icu_irq_chip); 125 irq_set_chip(irq, &icu_irq_chip);
126 set_irq_flags(irq, IRQF_VALID); 126 set_irq_flags(irq, IRQF_VALID);
127 127
128 switch (irq) { 128 switch (irq) {
@@ -133,7 +133,7 @@ void __init mmp2_init_icu(void)
133 case IRQ_MMP2_SSP_MUX: 133 case IRQ_MMP2_SSP_MUX:
134 break; 134 break;
135 default: 135 default:
136 set_irq_handler(irq, handle_level_irq); 136 irq_set_handler(irq, handle_level_irq);
137 break; 137 break;
138 } 138 }
139 } 139 }
@@ -149,9 +149,9 @@ void __init mmp2_init_icu(void)
149 init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15); 149 init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
150 init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2); 150 init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
151 151
152 set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); 152 irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
153 set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); 153 irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
154 set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); 154 irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
155 set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); 155 irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
156 set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); 156 irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
157} 157}
diff --git a/arch/arm/mach-mmp/irq-pxa168.c b/arch/arm/mach-mmp/irq-pxa168.c
index f86b450cb93c..89706a0d08f1 100644
--- a/arch/arm/mach-mmp/irq-pxa168.c
+++ b/arch/arm/mach-mmp/irq-pxa168.c
@@ -48,8 +48,7 @@ void __init icu_init_irq(void)
48 48
49 for (irq = 0; irq < 64; irq++) { 49 for (irq = 0; irq < 64; irq++) {
50 icu_mask_irq(irq_get_irq_data(irq)); 50 icu_mask_irq(irq_get_irq_data(irq));
51 set_irq_chip(irq, &icu_irq_chip); 51 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
52 set_irq_handler(irq, handle_level_irq);
53 set_irq_flags(irq, IRQF_VALID); 52 set_irq_flags(irq, IRQF_VALID);
54 } 53 }
55} 54}
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index 1993721d472e..35c7ceeb3f29 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -53,7 +53,7 @@ static void __init msm8960_init_irq(void)
53 */ 53 */
54 for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { 54 for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
55 if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) 55 if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
56 set_irq_handler(i, handle_percpu_irq); 56 irq_set_handler(i, handle_percpu_irq);
57 } 57 }
58} 58}
59 59
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index b3c55f138fce..1163b6fd05d2 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -56,7 +56,7 @@ static void __init msm8x60_init_irq(void)
56 */ 56 */
57 for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { 57 for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
58 if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) 58 if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
59 set_irq_handler(i, handle_percpu_irq); 59 irq_set_handler(i, handle_percpu_irq);
60 } 60 }
61} 61}
62 62
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
index 31117a4499c4..87e1d01edecc 100644
--- a/arch/arm/mach-msm/board-trout-gpio.c
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -214,17 +214,17 @@ int __init trout_init_gpio(void)
214{ 214{
215 int i; 215 int i;
216 for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) { 216 for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) {
217 set_irq_chip(i, &trout_gpio_irq_chip); 217 irq_set_chip_and_handler(i, &trout_gpio_irq_chip,
218 set_irq_handler(i, handle_edge_irq); 218 handle_edge_irq);
219 set_irq_flags(i, IRQF_VALID); 219 set_irq_flags(i, IRQF_VALID);
220 } 220 }
221 221
222 for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++) 222 for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
223 gpiochip_add(&msm_gpio_banks[i].chip); 223 gpiochip_add(&msm_gpio_banks[i].chip);
224 224
225 set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH); 225 irq_set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
226 set_irq_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler); 226 irq_set_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler);
227 set_irq_wake(MSM_GPIO_TO_INT(17), 1); 227 irq_set_irq_wake(MSM_GPIO_TO_INT(17), 1);
228 228
229 return 0; 229 return 0;
230} 230}
diff --git a/arch/arm/mach-msm/board-trout-mmc.c b/arch/arm/mach-msm/board-trout-mmc.c
index 44be8464657b..f7a9724788b0 100644
--- a/arch/arm/mach-msm/board-trout-mmc.c
+++ b/arch/arm/mach-msm/board-trout-mmc.c
@@ -174,7 +174,7 @@ int __init trout_init_mmc(unsigned int sys_rev)
174 if (IS_ERR(vreg_sdslot)) 174 if (IS_ERR(vreg_sdslot))
175 return PTR_ERR(vreg_sdslot); 175 return PTR_ERR(vreg_sdslot);
176 176
177 set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1); 177 irq_set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1);
178 178
179 if (!opt_disable_sdcard) 179 if (!opt_disable_sdcard)
180 msm_add_sdcc(2, &trout_sdslot_data, 180 msm_add_sdcc(2, &trout_sdslot_data,
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c
index 0de19ec74e34..56a964e52ad3 100644
--- a/arch/arm/mach-msm/gpio-v2.c
+++ b/arch/arm/mach-msm/gpio-v2.c
@@ -230,18 +230,18 @@ static void msm_gpio_update_dual_edge_pos(unsigned gpio)
230 val, val2); 230 val, val2);
231} 231}
232 232
233static void msm_gpio_irq_ack(unsigned int irq) 233static void msm_gpio_irq_ack(struct irq_data *d)
234{ 234{
235 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); 235 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
236 236
237 writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio)); 237 writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio));
238 if (test_bit(gpio, msm_gpio.dual_edge_irqs)) 238 if (test_bit(gpio, msm_gpio.dual_edge_irqs))
239 msm_gpio_update_dual_edge_pos(gpio); 239 msm_gpio_update_dual_edge_pos(gpio);
240} 240}
241 241
242static void msm_gpio_irq_mask(unsigned int irq) 242static void msm_gpio_irq_mask(struct irq_data *d)
243{ 243{
244 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); 244 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
245 unsigned long irq_flags; 245 unsigned long irq_flags;
246 246
247 spin_lock_irqsave(&tlmm_lock, irq_flags); 247 spin_lock_irqsave(&tlmm_lock, irq_flags);
@@ -251,9 +251,9 @@ static void msm_gpio_irq_mask(unsigned int irq)
251 spin_unlock_irqrestore(&tlmm_lock, irq_flags); 251 spin_unlock_irqrestore(&tlmm_lock, irq_flags);
252} 252}
253 253
254static void msm_gpio_irq_unmask(unsigned int irq) 254static void msm_gpio_irq_unmask(struct irq_data *d)
255{ 255{
256 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); 256 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
257 unsigned long irq_flags; 257 unsigned long irq_flags;
258 258
259 spin_lock_irqsave(&tlmm_lock, irq_flags); 259 spin_lock_irqsave(&tlmm_lock, irq_flags);
@@ -263,9 +263,9 @@ static void msm_gpio_irq_unmask(unsigned int irq)
263 spin_unlock_irqrestore(&tlmm_lock, irq_flags); 263 spin_unlock_irqrestore(&tlmm_lock, irq_flags);
264} 264}
265 265
266static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) 266static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
267{ 267{
268 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); 268 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
269 unsigned long irq_flags; 269 unsigned long irq_flags;
270 uint32_t bits; 270 uint32_t bits;
271 271
@@ -275,14 +275,14 @@ static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
275 275
276 if (flow_type & IRQ_TYPE_EDGE_BOTH) { 276 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
277 bits |= BIT(INTR_DECT_CTL); 277 bits |= BIT(INTR_DECT_CTL);
278 irq_desc[irq].handle_irq = handle_edge_irq; 278 __irq_set_handler_locked(d->irq, handle_edge_irq);
279 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 279 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
280 __set_bit(gpio, msm_gpio.dual_edge_irqs); 280 __set_bit(gpio, msm_gpio.dual_edge_irqs);
281 else 281 else
282 __clear_bit(gpio, msm_gpio.dual_edge_irqs); 282 __clear_bit(gpio, msm_gpio.dual_edge_irqs);
283 } else { 283 } else {
284 bits &= ~BIT(INTR_DECT_CTL); 284 bits &= ~BIT(INTR_DECT_CTL);
285 irq_desc[irq].handle_irq = handle_level_irq; 285 __irq_set_handler_locked(d->irq, handle_level_irq);
286 __clear_bit(gpio, msm_gpio.dual_edge_irqs); 286 __clear_bit(gpio, msm_gpio.dual_edge_irqs);
287 } 287 }
288 288
@@ -309,6 +309,7 @@ static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
309 */ 309 */
310static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) 310static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
311{ 311{
312 struct irq_data *data = irq_desc_get_irq_data(desc);
312 unsigned long i; 313 unsigned long i;
313 314
314 for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS); 315 for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
@@ -318,21 +319,21 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
318 generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip, 319 generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
319 i)); 320 i));
320 } 321 }
321 desc->chip->ack(irq); 322 data->chip->irq_ack(data);
322} 323}
323 324
324static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) 325static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
325{ 326{
326 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); 327 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
327 328
328 if (on) { 329 if (on) {
329 if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) 330 if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
330 set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); 331 irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
331 set_bit(gpio, msm_gpio.wake_irqs); 332 set_bit(gpio, msm_gpio.wake_irqs);
332 } else { 333 } else {
333 clear_bit(gpio, msm_gpio.wake_irqs); 334 clear_bit(gpio, msm_gpio.wake_irqs);
334 if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) 335 if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
335 set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); 336 irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
336 } 337 }
337 338
338 return 0; 339 return 0;
@@ -340,11 +341,11 @@ static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
340 341
341static struct irq_chip msm_gpio_irq_chip = { 342static struct irq_chip msm_gpio_irq_chip = {
342 .name = "msmgpio", 343 .name = "msmgpio",
343 .mask = msm_gpio_irq_mask, 344 .irq_mask = msm_gpio_irq_mask,
344 .unmask = msm_gpio_irq_unmask, 345 .irq_unmask = msm_gpio_irq_unmask,
345 .ack = msm_gpio_irq_ack, 346 .irq_ack = msm_gpio_irq_ack,
346 .set_type = msm_gpio_irq_set_type, 347 .irq_set_type = msm_gpio_irq_set_type,
347 .set_wake = msm_gpio_irq_set_wake, 348 .irq_set_wake = msm_gpio_irq_set_wake,
348}; 349};
349 350
350static int __devinit msm_gpio_probe(struct platform_device *dev) 351static int __devinit msm_gpio_probe(struct platform_device *dev)
@@ -361,12 +362,12 @@ static int __devinit msm_gpio_probe(struct platform_device *dev)
361 362
362 for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { 363 for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
363 irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); 364 irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
364 set_irq_chip(irq, &msm_gpio_irq_chip); 365 irq_set_chip_and_handler(irq, &msm_gpio_irq_chip,
365 set_irq_handler(irq, handle_level_irq); 366 handle_level_irq);
366 set_irq_flags(irq, IRQF_VALID); 367 set_irq_flags(irq, IRQF_VALID);
367 } 368 }
368 369
369 set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ, 370 irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
370 msm_summary_irq_handler); 371 msm_summary_irq_handler);
371 return 0; 372 return 0;
372} 373}
@@ -378,7 +379,7 @@ static int __devexit msm_gpio_remove(struct platform_device *dev)
378 if (ret < 0) 379 if (ret < 0)
379 return ret; 380 return ret;
380 381
381 set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); 382 irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
382 383
383 return 0; 384 return 0;
384} 385}
diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c
index 176af9dcb8ee..5ea273b00da8 100644
--- a/arch/arm/mach-msm/gpio.c
+++ b/arch/arm/mach-msm/gpio.c
@@ -293,10 +293,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
293 val = readl(msm_chip->regs.int_edge); 293 val = readl(msm_chip->regs.int_edge);
294 if (flow_type & IRQ_TYPE_EDGE_BOTH) { 294 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
295 writel(val | mask, msm_chip->regs.int_edge); 295 writel(val | mask, msm_chip->regs.int_edge);
296 irq_desc[d->irq].handle_irq = handle_edge_irq; 296 __irq_set_handler_locked(d->irq, handle_edge_irq);
297 } else { 297 } else {
298 writel(val & ~mask, msm_chip->regs.int_edge); 298 writel(val & ~mask, msm_chip->regs.int_edge);
299 irq_desc[d->irq].handle_irq = handle_level_irq; 299 __irq_set_handler_locked(d->irq, handle_level_irq);
300 } 300 }
301 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 301 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
302 msm_chip->both_edge_detect |= mask; 302 msm_chip->both_edge_detect |= mask;
@@ -354,9 +354,9 @@ static int __init msm_init_gpio(void)
354 msm_gpio_chips[j].chip.base + 354 msm_gpio_chips[j].chip.base +
355 msm_gpio_chips[j].chip.ngpio) 355 msm_gpio_chips[j].chip.ngpio)
356 j++; 356 j++;
357 set_irq_chip_data(i, &msm_gpio_chips[j]); 357 irq_set_chip_data(i, &msm_gpio_chips[j]);
358 set_irq_chip(i, &msm_gpio_irq_chip); 358 irq_set_chip_and_handler(i, &msm_gpio_irq_chip,
359 set_irq_handler(i, handle_edge_irq); 359 handle_edge_irq);
360 set_irq_flags(i, IRQF_VALID); 360 set_irq_flags(i, IRQF_VALID);
361 } 361 }
362 362
@@ -366,10 +366,10 @@ static int __init msm_init_gpio(void)
366 gpiochip_add(&msm_gpio_chips[i].chip); 366 gpiochip_add(&msm_gpio_chips[i].chip);
367 } 367 }
368 368
369 set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); 369 irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
370 set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); 370 irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
371 set_irq_wake(INT_GPIO_GROUP1, 1); 371 irq_set_irq_wake(INT_GPIO_GROUP1, 1);
372 set_irq_wake(INT_GPIO_GROUP2, 2); 372 irq_set_irq_wake(INT_GPIO_GROUP2, 2);
373 return 0; 373 return 0;
374} 374}
375 375
diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c
index 68c28bbdc969..1b54f807c2d0 100644
--- a/arch/arm/mach-msm/irq-vic.c
+++ b/arch/arm/mach-msm/irq-vic.c
@@ -313,11 +313,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
313 type = msm_irq_shadow_reg[index].int_type; 313 type = msm_irq_shadow_reg[index].int_type;
314 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { 314 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
315 type |= b; 315 type |= b;
316 irq_desc[d->irq].handle_irq = handle_edge_irq; 316 __irq_set_handler_locked(d->irq, handle_edge_irq);
317 } 317 }
318 if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { 318 if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
319 type &= ~b; 319 type &= ~b;
320 irq_desc[d->irq].handle_irq = handle_level_irq; 320 __irq_set_handler_locked(d->irq, handle_level_irq);
321 } 321 }
322 writel(type, treg); 322 writel(type, treg);
323 msm_irq_shadow_reg[index].int_type = type; 323 msm_irq_shadow_reg[index].int_type = type;
@@ -357,8 +357,7 @@ void __init msm_init_irq(void)
357 writel(3, VIC_INT_MASTEREN); 357 writel(3, VIC_INT_MASTEREN);
358 358
359 for (n = 0; n < NR_MSM_IRQS; n++) { 359 for (n = 0; n < NR_MSM_IRQS; n++) {
360 set_irq_chip(n, &msm_irq_chip); 360 irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
361 set_irq_handler(n, handle_level_irq);
362 set_irq_flags(n, IRQF_VALID); 361 set_irq_flags(n, IRQF_VALID);
363 } 362 }
364} 363}
diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c
index 0b27d899f40e..ea514be390c6 100644
--- a/arch/arm/mach-msm/irq.c
+++ b/arch/arm/mach-msm/irq.c
@@ -100,11 +100,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
100 100
101 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { 101 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
102 writel(readl(treg) | b, treg); 102 writel(readl(treg) | b, treg);
103 irq_desc[d->irq].handle_irq = handle_edge_irq; 103 __irq_set_handler_locked(d->irq, handle_edge_irq);
104 } 104 }
105 if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { 105 if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
106 writel(readl(treg) & (~b), treg); 106 writel(readl(treg) & (~b), treg);
107 irq_desc[d->irq].handle_irq = handle_level_irq; 107 __irq_set_handler_locked(d->irq, handle_level_irq);
108 } 108 }
109 return 0; 109 return 0;
110} 110}
@@ -145,8 +145,7 @@ void __init msm_init_irq(void)
145 writel(1, VIC_INT_MASTEREN); 145 writel(1, VIC_INT_MASTEREN);
146 146
147 for (n = 0; n < NR_MSM_IRQS; n++) { 147 for (n = 0; n < NR_MSM_IRQS; n++) {
148 set_irq_chip(n, &msm_irq_chip); 148 irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
149 set_irq_handler(n, handle_level_irq);
150 set_irq_flags(n, IRQF_VALID); 149 set_irq_flags(n, IRQF_VALID);
151 } 150 }
152} 151}
diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c
index 11b54c7aeb09..689e78c95f38 100644
--- a/arch/arm/mach-msm/sirc.c
+++ b/arch/arm/mach-msm/sirc.c
@@ -105,10 +105,10 @@ static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type)
105 val = readl(sirc_regs.int_type); 105 val = readl(sirc_regs.int_type);
106 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { 106 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
107 val |= mask; 107 val |= mask;
108 irq_desc[d->irq].handle_irq = handle_edge_irq; 108 __irq_set_handler_locked(d->irq, handle_edge_irq);
109 } else { 109 } else {
110 val &= ~mask; 110 val &= ~mask;
111 irq_desc[d->irq].handle_irq = handle_level_irq; 111 __irq_set_handler_locked(d->irq, handle_level_irq);
112 } 112 }
113 113
114 writel(val, sirc_regs.int_type); 114 writel(val, sirc_regs.int_type);
@@ -158,15 +158,14 @@ void __init msm_init_sirc(void)
158 wake_enable = 0; 158 wake_enable = 0;
159 159
160 for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) { 160 for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
161 set_irq_chip(i, &sirc_irq_chip); 161 irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq);
162 set_irq_handler(i, handle_edge_irq);
163 set_irq_flags(i, IRQF_VALID); 162 set_irq_flags(i, IRQF_VALID);
164 } 163 }
165 164
166 for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) { 165 for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) {
167 set_irq_chained_handler(sirc_reg_table[i].cascade_irq, 166 irq_set_chained_handler(sirc_reg_table[i].cascade_irq,
168 sirc_irq_handler); 167 sirc_irq_handler);
169 set_irq_wake(sirc_reg_table[i].cascade_irq, 1); 168 irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
170 } 169 }
171 return; 170 return;
172} 171}
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index 08da497c39c2..3e24431bb5ea 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -38,8 +38,8 @@ void __init mv78xx0_init_irq(void)
38 orion_gpio_init(0, 32, GPIO_VIRT_BASE, 38 orion_gpio_init(0, 32, GPIO_VIRT_BASE,
39 mv78xx0_core_index() ? 0x18 : 0, 39 mv78xx0_core_index() ? 0x18 : 0,
40 IRQ_MV78XX0_GPIO_START); 40 IRQ_MV78XX0_GPIO_START);
41 set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); 41 irq_set_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
42 set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); 42 irq_set_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
43 set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); 43 irq_set_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
44 set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); 44 irq_set_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler);
45} 45}
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
index 80761474c0f8..2e288b38b4ad 100644
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -43,6 +43,7 @@
43#include <mach/ipu.h> 43#include <mach/ipu.h>
44#include <mach/mx3fb.h> 44#include <mach/mx3fb.h>
45#include <mach/audmux.h> 45#include <mach/audmux.h>
46#include <mach/esdhc.h>
46 47
47#include "devices-imx35.h" 48#include "devices-imx35.h"
48#include "devices.h" 49#include "devices.h"
@@ -163,11 +164,14 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
163 MX35_PAD_SD1_DATA1__ESDHC1_DAT1, 164 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
164 MX35_PAD_SD1_DATA2__ESDHC1_DAT2, 165 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
165 MX35_PAD_SD1_DATA3__ESDHC1_DAT3, 166 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
167 /* SD1 CD */
168 MX35_PAD_LD18__GPIO3_24,
166}; 169};
167 170
168#define GPIO_LED1 IMX_GPIO_NR(3, 29) 171#define GPIO_LED1 IMX_GPIO_NR(3, 29)
169#define GPIO_SWITCH1 IMX_GPIO_NR(3, 25) 172#define GPIO_SWITCH1 IMX_GPIO_NR(3, 25)
170#define GPIO_LCDPWR (4) 173#define GPIO_LCDPWR IMX_GPIO_NR(1, 4)
174#define GPIO_SD1CD IMX_GPIO_NR(3, 24)
171 175
172static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, 176static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
173 unsigned int power) 177 unsigned int power)
@@ -254,6 +258,11 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
254 .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, 258 .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
255}; 259};
256 260
261static struct esdhc_platform_data sd1_pdata = {
262 .cd_gpio = GPIO_SD1CD,
263 .wp_gpio = -EINVAL,
264};
265
257/* 266/*
258 * system init for baseboard usage. Will be called by cpuimx35 init. 267 * system init for baseboard usage. Will be called by cpuimx35 init.
259 * 268 *
@@ -289,7 +298,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
289 imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); 298 imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
290 299
291 imx35_add_flexcan1(NULL); 300 imx35_add_flexcan1(NULL);
292 imx35_add_sdhci_esdhc_imx(0, NULL); 301 imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
293 302
294 gpio_request(GPIO_LED1, "LED1"); 303 gpio_request(GPIO_LED1, "LED1");
295 gpio_direction_output(GPIO_LED1, 1); 304 gpio_direction_output(GPIO_LED1, 1);
@@ -301,7 +310,6 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
301 310
302 gpio_request(GPIO_LCDPWR, "LCDPWR"); 311 gpio_request(GPIO_LCDPWR, "LCDPWR");
303 gpio_direction_output(GPIO_LCDPWR, 1); 312 gpio_direction_output(GPIO_LCDPWR, 1);
304 gpio_free(GPIO_LCDPWR);
305 313
306 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, 314 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
307 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); 315 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index 4e4b780c481d..3d095d69bc68 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -199,12 +199,11 @@ static void __init mx31ads_init_expio(void)
199 __raw_writew(0xFFFF, PBC_INTSTATUS_REG); 199 __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
200 for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); 200 for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
201 i++) { 201 i++) {
202 set_irq_chip(i, &expio_irq_chip); 202 irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
203 set_irq_handler(i, handle_level_irq);
204 set_irq_flags(i, IRQF_VALID); 203 set_irq_flags(i, IRQF_VALID);
205 } 204 }
206 set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH); 205 irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
207 set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); 206 irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
208} 207}
209 208
210#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 209#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index b3ecfb22d241..036ba1a4704b 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -40,6 +40,7 @@
40#include <mach/mx3fb.h> 40#include <mach/mx3fb.h>
41#include <mach/ulpi.h> 41#include <mach/ulpi.h>
42#include <mach/audmux.h> 42#include <mach/audmux.h>
43#include <mach/esdhc.h>
43 44
44#include "devices-imx35.h" 45#include "devices-imx35.h"
45#include "devices.h" 46#include "devices.h"
@@ -217,11 +218,15 @@ static iomux_v3_cfg_t pcm043_pads[] = {
217 MX35_PAD_SD1_DATA1__ESDHC1_DAT1, 218 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
218 MX35_PAD_SD1_DATA2__ESDHC1_DAT2, 219 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
219 MX35_PAD_SD1_DATA3__ESDHC1_DAT3, 220 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
221 MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */
222 MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */
220}; 223};
221 224
222#define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31) 225#define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31)
223#define AC97_GPIO_TXD IMX_GPIO_NR(2, 28) 226#define AC97_GPIO_TXD IMX_GPIO_NR(2, 28)
224#define AC97_GPIO_RESET IMX_GPIO_NR(2, 0) 227#define AC97_GPIO_RESET IMX_GPIO_NR(2, 0)
228#define SD1_GPIO_WP IMX_GPIO_NR(2, 23)
229#define SD1_GPIO_CD IMX_GPIO_NR(2, 24)
225 230
226static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) 231static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
227{ 232{
@@ -346,6 +351,11 @@ static int __init pcm043_otg_mode(char *options)
346} 351}
347__setup("otg_mode=", pcm043_otg_mode); 352__setup("otg_mode=", pcm043_otg_mode);
348 353
354static struct esdhc_platform_data sd1_pdata = {
355 .wp_gpio = SD1_GPIO_WP,
356 .cd_gpio = SD1_GPIO_CD,
357};
358
349/* 359/*
350 * Board specific initialization. 360 * Board specific initialization.
351 */ 361 */
@@ -395,7 +405,7 @@ static void __init pcm043_init(void)
395 imx35_add_fsl_usb2_udc(&otg_device_pdata); 405 imx35_add_fsl_usb2_udc(&otg_device_pdata);
396 406
397 imx35_add_flexcan1(NULL); 407 imx35_add_flexcan1(NULL);
398 imx35_add_sdhci_esdhc_imx(0, NULL); 408 imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
399} 409}
400 410
401static void __init pcm043_timer_init(void) 411static void __init pcm043_timer_init(void)
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 83ee08847d4d..159340da9191 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -165,6 +165,7 @@ config MACH_MX53_LOCO
165 select IMX_HAVE_PLATFORM_IMX_I2C 165 select IMX_HAVE_PLATFORM_IMX_I2C
166 select IMX_HAVE_PLATFORM_IMX_UART 166 select IMX_HAVE_PLATFORM_IMX_UART
167 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 167 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
168 select IMX_HAVE_PLATFORM_GPIO_KEYS
168 help 169 help
169 Include support for MX53 LOCO platform. This includes specific 170 Include support for MX53 LOCO platform. This includes specific
170 configurations for the board and its peripherals. 171 configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 4f63048be3ca..0b9338cec516 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Object file lists. 5# Object file lists.
6obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o 6obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o system.o
7obj-$(CONFIG_SOC_IMX50) += mm-mx50.o 7obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
8 8
9obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o 9obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index b2ecd194e76d..bea4e4135f9d 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -228,13 +228,12 @@ static inline void babbage_fec_reset(void)
228 int ret; 228 int ret;
229 229
230 /* reset FEC PHY */ 230 /* reset FEC PHY */
231 ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset"); 231 ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
232 GPIOF_OUT_INIT_LOW, "fec-phy-reset");
232 if (ret) { 233 if (ret) {
233 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); 234 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
234 return; 235 return;
235 } 236 }
236 gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0);
237 gpio_set_value(BABBAGE_FEC_PHY_RESET, 0);
238 msleep(1); 237 msleep(1);
239 gpio_set_value(BABBAGE_FEC_PHY_RESET, 1); 238 gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
240} 239}
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index 7b5735c5ea59..2af3f43f74db 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -34,7 +34,7 @@
34#include <mach/imx-uart.h> 34#include <mach/imx-uart.h>
35#include <mach/iomux-mx53.h> 35#include <mach/iomux-mx53.h>
36 36
37#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) 37#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6)
38#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) 38#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30)
39#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) 39#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
40 40
@@ -82,15 +82,14 @@ static inline void mx53_evk_fec_reset(void)
82 int ret; 82 int ret;
83 83
84 /* reset FEC PHY */ 84 /* reset FEC PHY */
85 ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset"); 85 ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW,
86 "fec-phy-reset");
86 if (ret) { 87 if (ret) {
87 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); 88 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
88 return; 89 return;
89 } 90 }
90 gpio_direction_output(SMD_FEC_PHY_RST, 0);
91 gpio_set_value(SMD_FEC_PHY_RST, 0);
92 msleep(1); 91 msleep(1);
93 gpio_set_value(SMD_FEC_PHY_RST, 1); 92 gpio_set_value(MX53_EVK_FEC_PHY_RST, 1);
94} 93}
95 94
96static struct fec_platform_data mx53_evk_fec_pdata = { 95static struct fec_platform_data mx53_evk_fec_pdata = {
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 0a18f8d23eb0..10a1bea10548 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -36,6 +36,9 @@
36#include "crm_regs.h" 36#include "crm_regs.h"
37#include "devices-imx53.h" 37#include "devices-imx53.h"
38 38
39#define MX53_LOCO_POWER IMX_GPIO_NR(1, 8)
40#define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14)
41#define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15)
39#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) 42#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
40 43
41static iomux_v3_cfg_t mx53_loco_pads[] = { 44static iomux_v3_cfg_t mx53_loco_pads[] = {
@@ -180,6 +183,27 @@ static iomux_v3_cfg_t mx53_loco_pads[] = {
180 MX53_PAD_GPIO_8__GPIO1_8, 183 MX53_PAD_GPIO_8__GPIO1_8,
181}; 184};
182 185
186#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
187{ \
188 .gpio = gpio_num, \
189 .type = EV_KEY, \
190 .code = ev_code, \
191 .active_low = act_low, \
192 .desc = "btn " descr, \
193 .wakeup = wake, \
194}
195
196static const struct gpio_keys_button loco_buttons[] __initconst = {
197 GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0),
198 GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
199 GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
200};
201
202static const struct gpio_keys_platform_data loco_button_data __initconst = {
203 .buttons = loco_buttons,
204 .nbuttons = ARRAY_SIZE(loco_buttons),
205};
206
183static inline void mx53_loco_fec_reset(void) 207static inline void mx53_loco_fec_reset(void)
184{ 208{
185 int ret; 209 int ret;
@@ -215,6 +239,7 @@ static void __init mx53_loco_board_init(void)
215 imx53_add_imx_i2c(1, &mx53_loco_i2c_data); 239 imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
216 imx53_add_sdhci_esdhc_imx(0, NULL); 240 imx53_add_sdhci_esdhc_imx(0, NULL);
217 imx53_add_sdhci_esdhc_imx(2, NULL); 241 imx53_add_sdhci_esdhc_imx(2, NULL);
242 imx_add_gpio_keys(&loco_button_data);
218} 243}
219 244
220static void __init mx53_loco_timer_init(void) 245static void __init mx53_loco_timer_init(void)
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 652ace413825..fdbc05ed5513 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -865,6 +865,13 @@ static struct clk aips_tz2_clk = {
865 .disable = _clk_ccgr_disable_inwait, 865 .disable = _clk_ccgr_disable_inwait,
866}; 866};
867 867
868static struct clk gpc_dvfs_clk = {
869 .enable_reg = MXC_CCM_CCGR5,
870 .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
871 .enable = _clk_ccgr_enable,
872 .disable = _clk_ccgr_disable,
873};
874
868static struct clk gpt_32k_clk = { 875static struct clk gpt_32k_clk = {
869 .id = 0, 876 .id = 0,
870 .parent = &ckil_clk, 877 .parent = &ckil_clk,
@@ -1448,6 +1455,7 @@ static struct clk_lookup mx51_lookups[] = {
1448 _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk) 1455 _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk)
1449 _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) 1456 _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)
1450 _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) 1457 _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)
1458 _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk)
1451}; 1459};
1452 1460
1453static struct clk_lookup mx53_lookups[] = { 1461static struct clk_lookup mx53_lookups[] = {
@@ -1511,6 +1519,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
1511 clk_enable(&iim_clk); 1519 clk_enable(&iim_clk);
1512 mx51_revision(); 1520 mx51_revision();
1513 clk_disable(&iim_clk); 1521 clk_disable(&iim_clk);
1522 mx51_display_revision();
1514 1523
1515 /* move usb_phy_clk to 24MHz */ 1524 /* move usb_phy_clk to 24MHz */
1516 clk_set_parent(&usb_phy1_clk, &osc_clk); 1525 clk_set_parent(&usb_phy1_clk, &osc_clk);
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index df46b5e60857..472bdfab2e55 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -21,6 +21,7 @@
21static int cpu_silicon_rev = -1; 21static int cpu_silicon_rev = -1;
22 22
23#define IIM_SREV 0x24 23#define IIM_SREV 0x24
24#define MX50_HW_ADADIG_DIGPROG 0xB0
24 25
25static int get_mx51_srev(void) 26static int get_mx51_srev(void)
26{ 27{
@@ -51,6 +52,26 @@ int mx51_revision(void)
51} 52}
52EXPORT_SYMBOL(mx51_revision); 53EXPORT_SYMBOL(mx51_revision);
53 54
55void mx51_display_revision(void)
56{
57 int rev;
58 char *srev;
59 rev = mx51_revision();
60
61 switch (rev) {
62 case IMX_CHIP_REVISION_2_0:
63 srev = IMX_CHIP_REVISION_2_0_STRING;
64 break;
65 case IMX_CHIP_REVISION_3_0:
66 srev = IMX_CHIP_REVISION_3_0_STRING;
67 break;
68 default:
69 srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
70 }
71 printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev);
72}
73EXPORT_SYMBOL(mx51_display_revision);
74
54#ifdef CONFIG_NEON 75#ifdef CONFIG_NEON
55 76
56/* 77/*
@@ -107,6 +128,44 @@ int mx53_revision(void)
107} 128}
108EXPORT_SYMBOL(mx53_revision); 129EXPORT_SYMBOL(mx53_revision);
109 130
131static int get_mx50_srev(void)
132{
133 void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
134 u32 rev;
135
136 if (!anatop) {
137 cpu_silicon_rev = -EINVAL;
138 return 0;
139 }
140
141 rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
142 rev &= 0xff;
143
144 iounmap(anatop);
145 if (rev == 0x0)
146 return IMX_CHIP_REVISION_1_0;
147 else if (rev == 0x1)
148 return IMX_CHIP_REVISION_1_1;
149 return 0;
150}
151
152/*
153 * Returns:
154 * the silicon revision of the cpu
155 * -EINVAL - not a mx50
156 */
157int mx50_revision(void)
158{
159 if (!cpu_is_mx50())
160 return -EINVAL;
161
162 if (cpu_silicon_rev == -1)
163 cpu_silicon_rev = get_mx50_srev();
164
165 return cpu_silicon_rev;
166}
167EXPORT_SYMBOL(mx50_revision);
168
110static int __init post_cpu_init(void) 169static int __init post_cpu_init(void)
111{ 170{
112 unsigned int reg; 171 unsigned int reg;
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index e83ffadb65f8..4a8550529b04 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -212,7 +212,7 @@ void __init eukrea_mbimx51_baseboard_init(void)
212 212
213 gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq"); 213 gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
214 gpio_direction_input(MBIMX51_TSC2007_GPIO); 214 gpio_direction_input(MBIMX51_TSC2007_GPIO);
215 set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); 215 irq_set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
216 i2c_register_board_info(1, mbimx51_i2c_devices, 216 i2c_register_board_info(1, mbimx51_i2c_devices,
217 ARRAY_SIZE(mbimx51_i2c_devices)); 217 ARRAY_SIZE(mbimx51_i2c_devices));
218 218
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
index c372a4373691..e6c1119c20ae 100644
--- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
@@ -67,6 +67,10 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
67 MX51_PAD_SD1_DATA1__SD1_DATA1, 67 MX51_PAD_SD1_DATA1__SD1_DATA1,
68 MX51_PAD_SD1_DATA2__SD1_DATA2, 68 MX51_PAD_SD1_DATA2__SD1_DATA2,
69 MX51_PAD_SD1_DATA3__SD1_DATA3, 69 MX51_PAD_SD1_DATA3__SD1_DATA3,
70 /* SD1 CD */
71 _MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
72 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
73 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
70}; 74};
71 75
72#define GPIO_LED1 IMX_GPIO_NR(3, 30) 76#define GPIO_LED1 IMX_GPIO_NR(3, 30)
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
index 868af8f435fa..d0c7075937cf 100644
--- a/arch/arm/mach-mx5/mx51_efika.c
+++ b/arch/arm/mach-mx5/mx51_efika.c
@@ -42,7 +42,6 @@
42#include <asm/mach-types.h> 42#include <asm/mach-types.h>
43#include <asm/mach/arch.h> 43#include <asm/mach/arch.h>
44#include <asm/mach/time.h> 44#include <asm/mach/time.h>
45#include <asm/mach-types.h>
46 45
47#include "devices-imx51.h" 46#include "devices-imx51.h"
48#include "devices.h" 47#include "devices.h"
diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c
new file mode 100644
index 000000000000..76ae8dc33e00
--- /dev/null
+++ b/arch/arm/mach-mx5/system.c
@@ -0,0 +1,84 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13#include <linux/platform_device.h>
14#include <linux/io.h>
15#include <mach/hardware.h>
16#include "crm_regs.h"
17
18/* set cpu low power mode before WFI instruction. This function is called
19 * mx5 because it can be used for mx50, mx51, and mx53.*/
20void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
21{
22 u32 plat_lpc, arm_srpgcr, ccm_clpcr;
23 u32 empgc0, empgc1;
24 int stop_mode = 0;
25
26 /* always allow platform to issue a deep sleep mode request */
27 plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &
28 ~(MXC_CORTEXA8_PLAT_LPC_DSM);
29 ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
30 arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
31 empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);
32 empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);
33
34 switch (mode) {
35 case WAIT_CLOCKED:
36 break;
37 case WAIT_UNCLOCKED:
38 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
39 break;
40 case WAIT_UNCLOCKED_POWER_OFF:
41 case STOP_POWER_OFF:
42 plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM
43 | MXC_CORTEXA8_PLAT_LPC_DBG_DSM;
44 if (mode == WAIT_UNCLOCKED_POWER_OFF) {
45 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
46 ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY;
47 ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS;
48 stop_mode = 0;
49 } else {
50 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
51 ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET;
52 ccm_clpcr |= MXC_CCM_CLPCR_VSTBY;
53 ccm_clpcr |= MXC_CCM_CLPCR_SBYOS;
54 stop_mode = 1;
55 }
56 arm_srpgcr |= MXC_SRPGCR_PCR;
57
58 if (tzic_enable_wake(1) != 0)
59 return;
60 break;
61 case STOP_POWER_ON:
62 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
63 break;
64 default:
65 printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode);
66 return;
67 }
68
69 __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
70 __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
71 __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
72
73 /* Enable NEON SRPG for all but MX50TO1.0. */
74 if (mx50_revision() != IMX_CHIP_REVISION_1_0)
75 __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
76
77 if (stop_mode) {
78 empgc0 |= MXC_SRPGCR_PCR;
79 empgc1 |= MXC_SRPGCR_PCR;
80
81 __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR);
82 __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);
83 }
84}
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 4f6f174af6c8..4522fbb235d5 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -22,6 +22,7 @@ config MACH_MX23EVK
22 select SOC_IMX23 22 select SOC_IMX23
23 select MXS_HAVE_AMBA_DUART 23 select MXS_HAVE_AMBA_DUART
24 select MXS_HAVE_PLATFORM_AUART 24 select MXS_HAVE_PLATFORM_AUART
25 select MXS_HAVE_PLATFORM_MXS_MMC
25 select MXS_HAVE_PLATFORM_MXSFB 26 select MXS_HAVE_PLATFORM_MXSFB
26 default y 27 default y
27 help 28 help
@@ -35,6 +36,7 @@ config MACH_MX28EVK
35 select MXS_HAVE_PLATFORM_AUART 36 select MXS_HAVE_PLATFORM_AUART
36 select MXS_HAVE_PLATFORM_FEC 37 select MXS_HAVE_PLATFORM_FEC
37 select MXS_HAVE_PLATFORM_FLEXCAN 38 select MXS_HAVE_PLATFORM_FLEXCAN
39 select MXS_HAVE_PLATFORM_MXS_MMC
38 select MXS_HAVE_PLATFORM_MXSFB 40 select MXS_HAVE_PLATFORM_MXSFB
39 select MXS_OCOTP 41 select MXS_OCOTP
40 default y 42 default y
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index d133c7f30940..c3577ea789ac 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -521,6 +521,15 @@ static int clk_misc_init(void)
521 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, 521 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
522 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET); 522 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
523 523
524 /*
525 * 480 MHz seems too high to be ssp clock source directly,
526 * so set frac to get a 288 MHz ref_io.
527 */
528 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
529 reg &= ~BM_CLKCTRL_FRAC_IOFRAC;
530 reg |= 30 << BP_CLKCTRL_FRAC_IOFRAC;
531 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
532
524 return 0; 533 return 0;
525} 534}
526 535
@@ -528,6 +537,12 @@ int __init mx23_clocks_init(void)
528{ 537{
529 clk_misc_init(); 538 clk_misc_init();
530 539
540 /*
541 * source ssp clock from ref_io than ref_xtal,
542 * as ref_xtal only provides 24 MHz as maximum.
543 */
544 clk_set_parent(&ssp_clk, &ref_io_clk);
545
531 clk_enable(&cpu_clk); 546 clk_enable(&cpu_clk);
532 clk_enable(&hbus_clk); 547 clk_enable(&hbus_clk);
533 clk_enable(&xbus_clk); 548 clk_enable(&xbus_clk);
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 5e489a2b2023..1ad97fed1e94 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -618,6 +618,8 @@ static struct clk_lookup lookups[] = {
618 _REGISTER_CLOCK("pll2", NULL, pll2_clk) 618 _REGISTER_CLOCK("pll2", NULL, pll2_clk)
619 _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk) 619 _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
620 _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk) 620 _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
621 _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk)
622 _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk)
621 _REGISTER_CLOCK("flexcan.0", NULL, can0_clk) 623 _REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
622 _REGISTER_CLOCK("flexcan.1", NULL, can1_clk) 624 _REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
623 _REGISTER_CLOCK(NULL, "usb0", usb0_clk) 625 _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
@@ -737,6 +739,15 @@ static int clk_misc_init(void)
737 reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; 739 reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
738 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); 740 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
739 741
742 /*
743 * 480 MHz seems too high to be ssp clock source directly,
744 * so set frac0 to get a 288 MHz ref_io0.
745 */
746 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
747 reg &= ~BM_CLKCTRL_FRAC0_IO0FRAC;
748 reg |= 30 << BP_CLKCTRL_FRAC0_IO0FRAC;
749 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
750
740 return 0; 751 return 0;
741} 752}
742 753
@@ -744,6 +755,13 @@ int __init mx28_clocks_init(void)
744{ 755{
745 clk_misc_init(); 756 clk_misc_init();
746 757
758 /*
759 * source ssp clock from ref_io0 than ref_xtal,
760 * as ref_xtal only provides 24 MHz as maximum.
761 */
762 clk_set_parent(&ssp0_clk, &ref_io0_clk);
763 clk_set_parent(&ssp1_clk, &ref_io0_clk);
764
747 clk_enable(&cpu_clk); 765 clk_enable(&cpu_clk);
748 clk_enable(&hbus_clk); 766 clk_enable(&hbus_clk);
749 clk_enable(&xbus_clk); 767 clk_enable(&xbus_clk);
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index c7e14f4e3669..c6f345febd39 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -21,6 +21,10 @@ extern const struct mxs_auart_data mx23_auart_data[] __initconst;
21#define mx23_add_auart0() mx23_add_auart(0) 21#define mx23_add_auart0() mx23_add_auart(0)
22#define mx23_add_auart1() mx23_add_auart(1) 22#define mx23_add_auart1() mx23_add_auart(1)
23 23
24extern const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst;
25#define mx23_add_mxs_mmc(id, pdata) \
26 mxs_add_mxs_mmc(&mx23_mxs_mmc_data[id], pdata)
27
24#define mx23_add_mxs_pwm(id) mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id) 28#define mx23_add_mxs_pwm(id) mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id)
25 29
26struct platform_device *__init mx23_add_mxsfb( 30struct platform_device *__init mx23_add_mxsfb(
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 9d08555c4cf0..c473eddce8cf 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -37,6 +37,10 @@ extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst;
37extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst; 37extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
38#define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id]) 38#define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id])
39 39
40extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst;
41#define mx28_add_mxs_mmc(id, pdata) \
42 mxs_add_mxs_mmc(&mx28_mxs_mmc_data[id], pdata)
43
40#define mx28_add_mxs_pwm(id) mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id) 44#define mx28_add_mxs_pwm(id) mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id)
41 45
42struct platform_device *__init mx28_add_mxsfb( 46struct platform_device *__init mx28_add_mxsfb(
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index 1451ad060d82..acf9eea124c0 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -15,6 +15,9 @@ config MXS_HAVE_PLATFORM_FLEXCAN
15config MXS_HAVE_PLATFORM_MXS_I2C 15config MXS_HAVE_PLATFORM_MXS_I2C
16 bool 16 bool
17 17
18config MXS_HAVE_PLATFORM_MXS_MMC
19 bool
20
18config MXS_HAVE_PLATFORM_MXS_PWM 21config MXS_HAVE_PLATFORM_MXS_PWM
19 bool 22 bool
20 23
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
index 0d9bea30b0a2..324f2824d38d 100644
--- a/arch/arm/mach-mxs/devices/Makefile
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -4,5 +4,6 @@ obj-y += platform-dma.o
4obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o 4obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
5obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o 5obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
6obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o 6obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
7obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o
7obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o 8obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
8obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o 9obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
new file mode 100644
index 000000000000..382dacbeca21
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
@@ -0,0 +1,73 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License version 2 as published by the
9 * Free Software Foundation.
10 */
11
12#include <linux/compiler.h>
13#include <linux/err.h>
14#include <linux/init.h>
15
16#include <mach/mx23.h>
17#include <mach/mx28.h>
18#include <mach/devices-common.h>
19
20#define mxs_mxs_mmc_data_entry_single(soc, _id, hwid) \
21 { \
22 .id = _id, \
23 .iobase = soc ## _SSP ## hwid ## _BASE_ADDR, \
24 .dma = soc ## _DMA_SSP ## hwid, \
25 .irq_err = soc ## _INT_SSP ## hwid ## _ERROR, \
26 .irq_dma = soc ## _INT_SSP ## hwid ## _DMA, \
27 }
28
29#define mxs_mxs_mmc_data_entry(soc, _id, hwid) \
30 [_id] = mxs_mxs_mmc_data_entry_single(soc, _id, hwid)
31
32
33#ifdef CONFIG_SOC_IMX23
34const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst = {
35 mxs_mxs_mmc_data_entry(MX23, 0, 1),
36 mxs_mxs_mmc_data_entry(MX23, 1, 2),
37};
38#endif
39
40#ifdef CONFIG_SOC_IMX28
41const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst = {
42 mxs_mxs_mmc_data_entry(MX28, 0, 0),
43 mxs_mxs_mmc_data_entry(MX28, 1, 1),
44};
45#endif
46
47struct platform_device *__init mxs_add_mxs_mmc(
48 const struct mxs_mxs_mmc_data *data,
49 const struct mxs_mmc_platform_data *pdata)
50{
51 struct resource res[] = {
52 {
53 .start = data->iobase,
54 .end = data->iobase + SZ_8K - 1,
55 .flags = IORESOURCE_MEM,
56 }, {
57 .start = data->dma,
58 .end = data->dma,
59 .flags = IORESOURCE_DMA,
60 }, {
61 .start = data->irq_err,
62 .end = data->irq_err,
63 .flags = IORESOURCE_IRQ,
64 }, {
65 .start = data->irq_dma,
66 .end = data->irq_dma,
67 .flags = IORESOURCE_IRQ,
68 },
69 };
70
71 return mxs_add_platform_device("mxs-mmc", data->id,
72 res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
73}
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c
index 56fa2ed15222..2c950fef71a8 100644
--- a/arch/arm/mach-mxs/gpio.c
+++ b/arch/arm/mach-mxs/gpio.c
@@ -136,7 +136,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
136static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) 136static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
137{ 137{
138 u32 irq_stat; 138 u32 irq_stat;
139 struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq); 139 struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq);
140 u32 gpio_irq_no_base = port->virtual_irq_start; 140 u32 gpio_irq_no_base = port->virtual_irq_start;
141 141
142 desc->irq_data.chip->irq_ack(&desc->irq_data); 142 desc->irq_data.chip->irq_ack(&desc->irq_data);
@@ -265,14 +265,14 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
265 265
266 for (j = port[i].virtual_irq_start; 266 for (j = port[i].virtual_irq_start;
267 j < port[i].virtual_irq_start + 32; j++) { 267 j < port[i].virtual_irq_start + 32; j++) {
268 set_irq_chip(j, &gpio_irq_chip); 268 irq_set_chip_and_handler(j, &gpio_irq_chip,
269 set_irq_handler(j, handle_level_irq); 269 handle_level_irq);
270 set_irq_flags(j, IRQF_VALID); 270 set_irq_flags(j, IRQF_VALID);
271 } 271 }
272 272
273 /* setup one handler for each entry */ 273 /* setup one handler for each entry */
274 set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler); 274 irq_set_chained_handler(port[i].irq, mxs_gpio_irq_handler);
275 set_irq_data(port[i].irq, &port[i]); 275 irq_set_handler_data(port[i].irq, &port[i]);
276 276
277 /* register gpio chip */ 277 /* register gpio chip */
278 port[i].chip.direction_input = mxs_gpio_direction_input; 278 port[i].chip.direction_input = mxs_gpio_direction_input;
diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c
index 0f4c120fc169..23ca9d083b2c 100644
--- a/arch/arm/mach-mxs/icoll.c
+++ b/arch/arm/mach-mxs/icoll.c
@@ -74,8 +74,7 @@ void __init icoll_init_irq(void)
74 mxs_reset_block(icoll_base + HW_ICOLL_CTRL); 74 mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
75 75
76 for (i = 0; i < MXS_INTERNAL_IRQS; i++) { 76 for (i = 0; i < MXS_INTERNAL_IRQS; i++) {
77 set_irq_chip(i, &mxs_icoll_chip); 77 irq_set_chip_and_handler(i, &mxs_icoll_chip, handle_level_irq);
78 set_irq_handler(i, handle_level_irq);
79 set_irq_flags(i, IRQF_VALID); 78 set_irq_flags(i, IRQF_VALID);
80 } 79 }
81} 80}
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index 71f24484b044..c5137f14c364 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -73,6 +73,19 @@ struct mxs_i2c_data {
73}; 73};
74struct platform_device * __init mxs_add_mxs_i2c(const struct mxs_i2c_data *data); 74struct platform_device * __init mxs_add_mxs_i2c(const struct mxs_i2c_data *data);
75 75
76/* mmc */
77#include <mach/mmc.h>
78struct mxs_mxs_mmc_data {
79 int id;
80 resource_size_t iobase;
81 resource_size_t dma;
82 resource_size_t irq_err;
83 resource_size_t irq_dma;
84};
85struct platform_device *__init mxs_add_mxs_mmc(
86 const struct mxs_mxs_mmc_data *data,
87 const struct mxs_mmc_platform_data *pdata);
88
76/* pwm */ 89/* pwm */
77struct platform_device *__init mxs_add_mxs_pwm( 90struct platform_device *__init mxs_add_mxs_pwm(
78 resource_size_t iobase, int id); 91 resource_size_t iobase, int id);
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index a66994f0518f..214e5b641bbc 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -28,6 +28,8 @@
28 28
29#define MX23EVK_LCD_ENABLE MXS_GPIO_NR(1, 18) 29#define MX23EVK_LCD_ENABLE MXS_GPIO_NR(1, 18)
30#define MX23EVK_BL_ENABLE MXS_GPIO_NR(1, 28) 30#define MX23EVK_BL_ENABLE MXS_GPIO_NR(1, 28)
31#define MX23EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30)
32#define MX23EVK_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29)
31 33
32static const iomux_cfg_t mx23evk_pads[] __initconst = { 34static const iomux_cfg_t mx23evk_pads[] __initconst = {
33 /* duart */ 35 /* duart */
@@ -73,6 +75,36 @@ static const iomux_cfg_t mx23evk_pads[] __initconst = {
73 MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL, 75 MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL,
74 /* backlight control */ 76 /* backlight control */
75 MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL, 77 MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL,
78
79 /* mmc */
80 MX23_PAD_SSP1_DATA0__SSP1_DATA0 |
81 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
82 MX23_PAD_SSP1_DATA1__SSP1_DATA1 |
83 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
84 MX23_PAD_SSP1_DATA2__SSP1_DATA2 |
85 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
86 MX23_PAD_SSP1_DATA3__SSP1_DATA3 |
87 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
88 MX23_PAD_GPMI_D08__SSP1_DATA4 |
89 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
90 MX23_PAD_GPMI_D09__SSP1_DATA5 |
91 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
92 MX23_PAD_GPMI_D10__SSP1_DATA6 |
93 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
94 MX23_PAD_GPMI_D11__SSP1_DATA7 |
95 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
96 MX23_PAD_SSP1_CMD__SSP1_CMD |
97 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
98 MX23_PAD_SSP1_DETECT__SSP1_DETECT |
99 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
100 MX23_PAD_SSP1_SCK__SSP1_SCK |
101 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
102 /* write protect */
103 MX23_PAD_PWM4__GPIO_1_30 |
104 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
105 /* slot power enable */
106 MX23_PAD_PWM3__GPIO_1_29 |
107 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
76}; 108};
77 109
78/* mxsfb (lcdif) */ 110/* mxsfb (lcdif) */
@@ -101,6 +133,11 @@ static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = {
101 .ld_intf_width = STMLCDIF_24BIT, 133 .ld_intf_width = STMLCDIF_24BIT,
102}; 134};
103 135
136static struct mxs_mmc_platform_data mx23evk_mmc_pdata __initdata = {
137 .wp_gpio = MX23EVK_MMC0_WRITE_PROTECT,
138 .flags = SLOTF_8_BIT_CAPABLE,
139};
140
104static void __init mx23evk_init(void) 141static void __init mx23evk_init(void)
105{ 142{
106 int ret; 143 int ret;
@@ -110,6 +147,13 @@ static void __init mx23evk_init(void)
110 mx23_add_duart(); 147 mx23_add_duart();
111 mx23_add_auart0(); 148 mx23_add_auart0();
112 149
150 /* power on mmc slot by writing 0 to the gpio */
151 ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_DIR_OUT,
152 "mmc0-slot-power");
153 if (ret)
154 pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret);
155 mx23_add_mxs_mmc(0, &mx23evk_mmc_pdata);
156
113 ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable"); 157 ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
114 if (ret) 158 if (ret)
115 pr_warn("failed to request gpio lcd-enable: %d\n", ret); 159 pr_warn("failed to request gpio lcd-enable: %d\n", ret);
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index 08002d02267a..bb329b9a2608 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -34,6 +34,11 @@
34#define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30) 34#define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30)
35#define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) 35#define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
36 36
37#define MX28EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(2, 12)
38#define MX28EVK_MMC1_WRITE_PROTECT MXS_GPIO_NR(0, 28)
39#define MX28EVK_MMC0_SLOT_POWER MXS_GPIO_NR(3, 28)
40#define MX28EVK_MMC1_SLOT_POWER MXS_GPIO_NR(3, 29)
41
37static const iomux_cfg_t mx28evk_pads[] __initconst = { 42static const iomux_cfg_t mx28evk_pads[] __initconst = {
38 /* duart */ 43 /* duart */
39 MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, 44 MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
@@ -115,6 +120,65 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = {
115 MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL, 120 MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
116 /* backlight control */ 121 /* backlight control */
117 MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL, 122 MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL,
123 /* mmc0 */
124 MX28_PAD_SSP0_DATA0__SSP0_D0 |
125 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
126 MX28_PAD_SSP0_DATA1__SSP0_D1 |
127 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
128 MX28_PAD_SSP0_DATA2__SSP0_D2 |
129 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
130 MX28_PAD_SSP0_DATA3__SSP0_D3 |
131 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
132 MX28_PAD_SSP0_DATA4__SSP0_D4 |
133 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
134 MX28_PAD_SSP0_DATA5__SSP0_D5 |
135 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
136 MX28_PAD_SSP0_DATA6__SSP0_D6 |
137 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
138 MX28_PAD_SSP0_DATA7__SSP0_D7 |
139 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
140 MX28_PAD_SSP0_CMD__SSP0_CMD |
141 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
142 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
143 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
144 MX28_PAD_SSP0_SCK__SSP0_SCK |
145 (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
146 /* write protect */
147 MX28_PAD_SSP1_SCK__GPIO_2_12 |
148 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
149 /* slot power enable */
150 MX28_PAD_PWM3__GPIO_3_28 |
151 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
152
153 /* mmc1 */
154 MX28_PAD_GPMI_D00__SSP1_D0 |
155 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
156 MX28_PAD_GPMI_D01__SSP1_D1 |
157 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
158 MX28_PAD_GPMI_D02__SSP1_D2 |
159 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
160 MX28_PAD_GPMI_D03__SSP1_D3 |
161 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
162 MX28_PAD_GPMI_D04__SSP1_D4 |
163 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
164 MX28_PAD_GPMI_D05__SSP1_D5 |
165 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
166 MX28_PAD_GPMI_D06__SSP1_D6 |
167 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
168 MX28_PAD_GPMI_D07__SSP1_D7 |
169 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
170 MX28_PAD_GPMI_RDY1__SSP1_CMD |
171 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
172 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
173 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
174 MX28_PAD_GPMI_WRN__SSP1_SCK |
175 (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
176 /* write protect */
177 MX28_PAD_GPMI_RESETN__GPIO_0_28 |
178 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
179 /* slot power enable */
180 MX28_PAD_PWM4__GPIO_3_29 |
181 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
118}; 182};
119 183
120/* fec */ 184/* fec */
@@ -258,6 +322,18 @@ static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = {
258 .ld_intf_width = STMLCDIF_24BIT, 322 .ld_intf_width = STMLCDIF_24BIT,
259}; 323};
260 324
325static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = {
326 {
327 /* mmc0 */
328 .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT,
329 .flags = SLOTF_8_BIT_CAPABLE,
330 }, {
331 /* mmc1 */
332 .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT,
333 .flags = SLOTF_8_BIT_CAPABLE,
334 },
335};
336
261static void __init mx28evk_init(void) 337static void __init mx28evk_init(void)
262{ 338{
263 int ret; 339 int ret;
@@ -297,6 +373,19 @@ static void __init mx28evk_init(void)
297 gpio_set_value(MX28EVK_BL_ENABLE, 1); 373 gpio_set_value(MX28EVK_BL_ENABLE, 1);
298 374
299 mx28_add_mxsfb(&mx28evk_mxsfb_pdata); 375 mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
376
377 /* power on mmc slot by writing 0 to the gpio */
378 ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_DIR_OUT,
379 "mmc0-slot-power");
380 if (ret)
381 pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret);
382 mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]);
383
384 ret = gpio_request_one(MX28EVK_MMC1_SLOT_POWER, GPIOF_DIR_OUT,
385 "mmc1-slot-power");
386 if (ret)
387 pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret);
388 mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
300} 389}
301 390
302static void __init mx28evk_timer_init(void) 391static void __init mx28evk_timer_init(void)
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c
index fa0b154da67b..0fcff47009cf 100644
--- a/arch/arm/mach-mxs/module-tx28.c
+++ b/arch/arm/mach-mxs/module-tx28.c
@@ -45,7 +45,7 @@ static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = {
45}; 45};
46 46
47#define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3) 47#define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3)
48static const iomux_cfg_t tx28_fec_pads[] __initconst = { 48static const iomux_cfg_t tx28_fec0_pads[] __initconst = {
49 MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE, 49 MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE,
50 MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE, 50 MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE,
51 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE, 51 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE,
@@ -57,7 +57,20 @@ static const iomux_cfg_t tx28_fec_pads[] __initconst = {
57 MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE, 57 MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE,
58}; 58};
59 59
60static const struct fec_platform_data tx28_fec_data __initconst = { 60static const iomux_cfg_t tx28_fec1_pads[] __initconst = {
61 MX28_PAD_ENET0_RXD2__ENET1_RXD0,
62 MX28_PAD_ENET0_RXD3__ENET1_RXD1,
63 MX28_PAD_ENET0_TXD2__ENET1_TXD0,
64 MX28_PAD_ENET0_TXD3__ENET1_TXD1,
65 MX28_PAD_ENET0_COL__ENET1_TX_EN,
66 MX28_PAD_ENET0_CRS__ENET1_RX_EN,
67};
68
69static struct fec_platform_data tx28_fec0_data = {
70 .phy = PHY_INTERFACE_MODE_RMII,
71};
72
73static struct fec_platform_data tx28_fec1_data = {
61 .phy = PHY_INTERFACE_MODE_RMII, 74 .phy = PHY_INTERFACE_MODE_RMII,
62}; 75};
63 76
@@ -108,15 +121,15 @@ int __init tx28_add_fec0(void)
108 pr_debug("%s: Deasserting FEC PHY RESET\n", __func__); 121 pr_debug("%s: Deasserting FEC PHY RESET\n", __func__);
109 gpio_set_value(TX28_FEC_PHY_RESET, 1); 122 gpio_set_value(TX28_FEC_PHY_RESET, 1);
110 123
111 ret = mxs_iomux_setup_multiple_pads(tx28_fec_pads, 124 ret = mxs_iomux_setup_multiple_pads(tx28_fec0_pads,
112 ARRAY_SIZE(tx28_fec_pads)); 125 ARRAY_SIZE(tx28_fec0_pads));
113 if (ret) { 126 if (ret) {
114 pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", 127 pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n",
115 __func__, ret); 128 __func__, ret);
116 goto free_gpios; 129 goto free_gpios;
117 } 130 }
118 pr_debug("%s: Registering FEC device\n", __func__); 131 pr_debug("%s: Registering FEC0 device\n", __func__);
119 mx28_add_fec(0, &tx28_fec_data); 132 mx28_add_fec(0, &tx28_fec0_data);
120 return 0; 133 return 0;
121 134
122free_gpios: 135free_gpios:
@@ -129,3 +142,19 @@ free_gpios:
129 142
130 return ret; 143 return ret;
131} 144}
145
146int __init tx28_add_fec1(void)
147{
148 int ret;
149
150 ret = mxs_iomux_setup_multiple_pads(tx28_fec1_pads,
151 ARRAY_SIZE(tx28_fec1_pads));
152 if (ret) {
153 pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n",
154 __func__, ret);
155 return ret;
156 }
157 pr_debug("%s: Registering FEC1 device\n", __func__);
158 mx28_add_fec(1, &tx28_fec1_data);
159 return 0;
160}
diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h
index df9e1b6e81bf..8ed425457d30 100644
--- a/arch/arm/mach-mxs/module-tx28.h
+++ b/arch/arm/mach-mxs/module-tx28.h
@@ -7,3 +7,4 @@
7 * Free Software Foundation. 7 * Free Software Foundation.
8 */ 8 */
9int __init tx28_add_fec0(void); 9int __init tx28_add_fec0(void);
10int __init tx28_add_fec1(void);
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 29ffa750fbe6..00023b5cf12b 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -171,13 +171,13 @@ void __init netx_init_irq(void)
171 vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0); 171 vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
172 172
173 for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { 173 for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
174 set_irq_chip(irq, &netx_hif_chip); 174 irq_set_chip_and_handler(irq, &netx_hif_chip,
175 set_irq_handler(irq, handle_level_irq); 175 handle_level_irq);
176 set_irq_flags(irq, IRQF_VALID); 176 set_irq_flags(irq, IRQF_VALID);
177 } 177 }
178 178
179 writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN); 179 writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN);
180 set_irq_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler); 180 irq_set_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler);
181} 181}
182 182
183static int __init netx_init(void) 183static int __init netx_init(void)
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
index 0c0d5248c368..e27687d53504 100644
--- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c
+++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
@@ -107,8 +107,8 @@ void __init board_a9m9750dev_init_irq(void)
107 __func__); 107 __func__);
108 108
109 for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { 109 for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
110 set_irq_chip(i, &a9m9750dev_fpga_chip); 110 irq_set_chip_and_handler(i, &a9m9750dev_fpga_chip,
111 set_irq_handler(i, handle_level_irq); 111 handle_level_irq);
112 set_irq_flags(i, IRQF_VALID); 112 set_irq_flags(i, IRQF_VALID);
113 } 113 }
114 114
@@ -118,8 +118,8 @@ void __init board_a9m9750dev_init_irq(void)
118 REGSET(eic, SYS_EIC, LVEDG, LEVEL); 118 REGSET(eic, SYS_EIC, LVEDG, LEVEL);
119 __raw_writel(eic, SYS_EIC(2)); 119 __raw_writel(eic, SYS_EIC(2));
120 120
121 set_irq_chained_handler(IRQ_NS9XXX_EXT2, 121 irq_set_chained_handler(IRQ_NS9XXX_EXT2,
122 a9m9750dev_fpga_demux_handler); 122 a9m9750dev_fpga_demux_handler);
123} 123}
124 124
125void __init board_a9m9750dev_init_machine(void) 125void __init board_a9m9750dev_init_machine(void)
diff --git a/arch/arm/mach-ns9xxx/include/mach/board.h b/arch/arm/mach-ns9xxx/include/mach/board.h
index f7e9196eb9ab..19ca6de46a45 100644
--- a/arch/arm/mach-ns9xxx/include/mach/board.h
+++ b/arch/arm/mach-ns9xxx/include/mach/board.h
@@ -14,12 +14,10 @@
14#include <asm/mach-types.h> 14#include <asm/mach-types.h>
15 15
16#define board_is_a9m9750dev() (0 \ 16#define board_is_a9m9750dev() (0 \
17 || machine_is_cc9p9360dev() \
18 || machine_is_cc9p9750dev() \ 17 || machine_is_cc9p9750dev() \
19 ) 18 )
20 19
21#define board_is_a9mvali() (0 \ 20#define board_is_a9mvali() (0 \
22 || machine_is_cc9p9360val() \
23 || machine_is_cc9p9750val() \ 21 || machine_is_cc9p9750val() \
24 ) 22 )
25 23
diff --git a/arch/arm/mach-ns9xxx/include/mach/module.h b/arch/arm/mach-ns9xxx/include/mach/module.h
index f851a6b7da6c..628e9752589b 100644
--- a/arch/arm/mach-ns9xxx/include/mach/module.h
+++ b/arch/arm/mach-ns9xxx/include/mach/module.h
@@ -18,7 +18,6 @@
18 ) 18 )
19 19
20#define module_is_cc9c() (0 \ 20#define module_is_cc9c() (0 \
21 || machine_is_cc9c() \
22 ) 21 )
23 22
24#define module_is_cc9p9210() (0 \ 23#define module_is_cc9p9210() (0 \
@@ -32,21 +31,17 @@
32 ) 31 )
33 32
34#define module_is_cc9p9360() (0 \ 33#define module_is_cc9p9360() (0 \
35 || machine_is_a9m9360() \
36 || machine_is_cc9p9360dev() \ 34 || machine_is_cc9p9360dev() \
37 || machine_is_cc9p9360js() \ 35 || machine_is_cc9p9360js() \
38 || machine_is_cc9p9360val() \
39 ) 36 )
40 37
41#define module_is_cc9p9750() (0 \ 38#define module_is_cc9p9750() (0 \
42 || machine_is_a9m9750() \ 39 || machine_is_a9m9750() \
43 || machine_is_cc9p9750dev() \
44 || machine_is_cc9p9750js() \ 40 || machine_is_cc9p9750js() \
45 || machine_is_cc9p9750val() \ 41 || machine_is_cc9p9750val() \
46 ) 42 )
47 43
48#define module_is_ccw9c() (0 \ 44#define module_is_ccw9c() (0 \
49 || machine_is_ccw9c() \
50 ) 45 )
51 46
52#define module_is_inc20otter() (0 \ 47#define module_is_inc20otter() (0 \
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c
index bf0fd48cbd80..37ab0a2b83ad 100644
--- a/arch/arm/mach-ns9xxx/irq.c
+++ b/arch/arm/mach-ns9xxx/irq.c
@@ -67,8 +67,7 @@ void __init ns9xxx_init_irq(void)
67 __raw_writel(prio2irq(i), SYS_IVA(i)); 67 __raw_writel(prio2irq(i), SYS_IVA(i));
68 68
69 for (i = 0; i <= 31; ++i) { 69 for (i = 0; i <= 31; ++i) {
70 set_irq_chip(i, &ns9xxx_chip); 70 irq_set_chip_and_handler(i, &ns9xxx_chip, handle_fasteoi_irq);
71 set_irq_handler(i, handle_fasteoi_irq);
72 set_irq_flags(i, IRQF_VALID); 71 set_irq_flags(i, IRQF_VALID);
73 irq_set_status_flags(i, IRQ_LEVEL); 72 irq_set_status_flags(i, IRQ_LEVEL);
74 } 73 }
diff --git a/arch/arm/mach-nuc93x/irq.c b/arch/arm/mach-nuc93x/irq.c
index 1f8a05a22834..aa279f23e342 100644
--- a/arch/arm/mach-nuc93x/irq.c
+++ b/arch/arm/mach-nuc93x/irq.c
@@ -59,8 +59,8 @@ void __init nuc93x_init_irq(void)
59 __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); 59 __raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
60 60
61 for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) { 61 for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) {
62 set_irq_chip(irqno, &nuc93x_irq_chip); 62 irq_set_chip_and_handler(irqno, &nuc93x_irq_chip,
63 set_irq_handler(irqno, handle_level_irq); 63 handle_level_irq);
64 set_irq_flags(irqno, IRQF_VALID); 64 set_irq_flags(irqno, IRQF_VALID);
65 } 65 }
66} 66}
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 7c5e2112c776..e68dfde1918e 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -276,7 +276,7 @@ static void __init osk_init_cf(void)
276 return; 276 return;
277 } 277 }
278 /* the CF I/O IRQ is really active-low */ 278 /* the CF I/O IRQ is really active-low */
279 set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING); 279 irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING);
280} 280}
281 281
282static void __init osk_init_irq(void) 282static void __init osk_init_irq(void)
@@ -482,7 +482,7 @@ static void __init osk_mistral_init(void)
482 omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ 482 omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */
483 gpio_request(4, "ts_int"); 483 gpio_request(4, "ts_int");
484 gpio_direction_input(4); 484 gpio_direction_input(4);
485 set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING); 485 irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING);
486 486
487 spi_register_board_info(mistral_boardinfo, 487 spi_register_board_info(mistral_boardinfo,
488 ARRAY_SIZE(mistral_boardinfo)); 488 ARRAY_SIZE(mistral_boardinfo));
@@ -500,7 +500,7 @@ static void __init osk_mistral_init(void)
500 int irq = gpio_to_irq(OMAP_MPUIO(2)); 500 int irq = gpio_to_irq(OMAP_MPUIO(2));
501 501
502 gpio_direction_input(OMAP_MPUIO(2)); 502 gpio_direction_input(OMAP_MPUIO(2));
503 set_irq_type(irq, IRQ_TYPE_EDGE_RISING); 503 irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
504#ifdef CONFIG_PM 504#ifdef CONFIG_PM
505 /* share the IRQ in case someone wants to use the 505 /* share the IRQ in case someone wants to use the
506 * button for more than wakeup from system sleep. 506 * button for more than wakeup from system sleep.
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index d7bbbe721a75..45f01d2c3a7a 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -256,12 +256,12 @@ palmz71_powercable(int irq, void *dev_id)
256{ 256{
257 if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) { 257 if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) {
258 printk(KERN_INFO "PM: Power cable connected\n"); 258 printk(KERN_INFO "PM: Power cable connected\n");
259 set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), 259 irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
260 IRQ_TYPE_EDGE_FALLING); 260 IRQ_TYPE_EDGE_FALLING);
261 } else { 261 } else {
262 printk(KERN_INFO "PM: Power cable disconnected\n"); 262 printk(KERN_INFO "PM: Power cable disconnected\n");
263 set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), 263 irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
264 IRQ_TYPE_EDGE_RISING); 264 IRQ_TYPE_EDGE_RISING);
265 } 265 }
266 return IRQ_HANDLED; 266 return IRQ_HANDLED;
267} 267}
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index bdc0ac8dc21f..65d24204937a 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -279,10 +279,10 @@ static void __init voiceblue_init(void)
279 gpio_request(13, "16C554 irq"); 279 gpio_request(13, "16C554 irq");
280 gpio_request(14, "16C554 irq"); 280 gpio_request(14, "16C554 irq");
281 gpio_request(15, "16C554 irq"); 281 gpio_request(15, "16C554 irq");
282 set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); 282 irq_set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING);
283 set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); 283 irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
284 set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); 284 irq_set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
285 set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); 285 irq_set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
286 286
287 platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); 287 platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
288 omap_board_config = voiceblue_config; 288 omap_board_config = voiceblue_config;
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 0ace7998aaa5..cddbf8b089ce 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -156,17 +156,17 @@ void omap1510_fpga_init_irq(void)
156 * The touchscreen interrupt is level-sensitive, so 156 * The touchscreen interrupt is level-sensitive, so
157 * we'll use the regular mask_ack routine for it. 157 * we'll use the regular mask_ack routine for it.
158 */ 158 */
159 set_irq_chip(i, &omap_fpga_irq_ack); 159 irq_set_chip(i, &omap_fpga_irq_ack);
160 } 160 }
161 else { 161 else {
162 /* 162 /*
163 * All FPGA interrupts except the touchscreen are 163 * All FPGA interrupts except the touchscreen are
164 * edge-sensitive, so we won't mask them. 164 * edge-sensitive, so we won't mask them.
165 */ 165 */
166 set_irq_chip(i, &omap_fpga_irq); 166 irq_set_chip(i, &omap_fpga_irq);
167 } 167 }
168 168
169 set_irq_handler(i, handle_edge_irq); 169 irq_set_handler(i, handle_edge_irq);
170 set_irq_flags(i, IRQF_VALID); 170 set_irq_flags(i, IRQF_VALID);
171 } 171 }
172 172
@@ -183,6 +183,6 @@ void omap1510_fpga_init_irq(void)
183 return; 183 return;
184 } 184 }
185 gpio_direction_input(13); 185 gpio_direction_input(13);
186 set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); 186 irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
187 set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); 187 irq_set_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
188} 188}
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 731dd33bff51..5d3da7a63af3 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -230,8 +230,8 @@ void __init omap_init_irq(void)
230 irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); 230 irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
231 omap_irq_set_cfg(j, 0, 0, irq_trigger); 231 omap_irq_set_cfg(j, 0, 0, irq_trigger);
232 232
233 set_irq_chip(j, &omap_irq_chip); 233 irq_set_chip_and_handler(j, &omap_irq_chip,
234 set_irq_handler(j, handle_level_irq); 234 handle_level_irq);
235 set_irq_flags(j, IRQF_VALID); 235 set_irq_flags(j, IRQF_VALID);
236 } 236 }
237 } 237 }
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 493505c3b2f5..130034bf01d5 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -743,7 +743,7 @@ static int __init gpmc_init(void)
743 /* initalize the irq_chained */ 743 /* initalize the irq_chained */
744 irq = OMAP_GPMC_IRQ_BASE; 744 irq = OMAP_GPMC_IRQ_BASE;
745 for (cs = 0; cs < GPMC_CS_NUM; cs++) { 745 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
746 set_irq_chip_and_handler(irq, &dummy_irq_chip, 746 irq_set_chip_and_handler(irq, &dummy_irq_chip,
747 handle_simple_irq); 747 handle_simple_irq);
748 set_irq_flags(irq, IRQF_VALID); 748 set_irq_flags(irq, IRQF_VALID);
749 irq++; 749 irq++;
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index bc524b94fd59..237e4530abf2 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -223,8 +223,7 @@ void __init omap_init_irq(void)
223 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); 223 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
224 224
225 for (i = 0; i < nr_of_irqs; i++) { 225 for (i = 0; i < nr_of_irqs; i++) {
226 set_irq_chip(i, &omap_irq_chip); 226 irq_set_chip_and_handler(i, &omap_irq_chip, handle_level_irq);
227 set_irq_handler(i, handle_level_irq);
228 set_irq_flags(i, IRQF_VALID); 227 set_irq_flags(i, IRQF_VALID);
229 } 228 }
230} 229}
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index c10a11715376..b7d4591214e0 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -213,7 +213,7 @@ void __init db88f5281_pci_preinit(void)
213 pin = DB88F5281_PCI_SLOT0_IRQ_PIN; 213 pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
214 if (gpio_request(pin, "PCI Int1") == 0) { 214 if (gpio_request(pin, "PCI Int1") == 0) {
215 if (gpio_direction_input(pin) == 0) { 215 if (gpio_direction_input(pin) == 0) {
216 set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); 216 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
217 } else { 217 } else {
218 printk(KERN_ERR "db88f5281_pci_preinit faield to " 218 printk(KERN_ERR "db88f5281_pci_preinit faield to "
219 "set_irq_type pin %d\n", pin); 219 "set_irq_type pin %d\n", pin);
@@ -226,7 +226,7 @@ void __init db88f5281_pci_preinit(void)
226 pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; 226 pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
227 if (gpio_request(pin, "PCI Int2") == 0) { 227 if (gpio_request(pin, "PCI Int2") == 0) {
228 if (gpio_direction_input(pin) == 0) { 228 if (gpio_direction_input(pin) == 0) {
229 set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); 229 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
230 } else { 230 } else {
231 printk(KERN_ERR "db88f5281_pci_preinit faield " 231 printk(KERN_ERR "db88f5281_pci_preinit faield "
232 "to set_irq_type pin %d\n", pin); 232 "to set_irq_type pin %d\n", pin);
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index ed85891f8699..43cf8bc9767b 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -34,8 +34,8 @@ void __init orion5x_init_irq(void)
34 * Initialize gpiolib for GPIOs 0-31. 34 * Initialize gpiolib for GPIOs 0-31.
35 */ 35 */
36 orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START); 36 orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START);
37 set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); 37 irq_set_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
38 set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); 38 irq_set_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
39 set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); 39 irq_set_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
40 set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler); 40 irq_set_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler);
41} 41}
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 67ec6959b267..4fc46772a087 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -148,7 +148,7 @@ void __init rd88f5182_pci_preinit(void)
148 pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; 148 pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
149 if (gpio_request(pin, "PCI IntA") == 0) { 149 if (gpio_request(pin, "PCI IntA") == 0) {
150 if (gpio_direction_input(pin) == 0) { 150 if (gpio_direction_input(pin) == 0) {
151 set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); 151 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
152 } else { 152 } else {
153 printk(KERN_ERR "rd88f5182_pci_preinit faield to " 153 printk(KERN_ERR "rd88f5182_pci_preinit faield to "
154 "set_irq_type pin %d\n", pin); 154 "set_irq_type pin %d\n", pin);
@@ -161,7 +161,7 @@ void __init rd88f5182_pci_preinit(void)
161 pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; 161 pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
162 if (gpio_request(pin, "PCI IntB") == 0) { 162 if (gpio_request(pin, "PCI IntB") == 0) {
163 if (gpio_direction_input(pin) == 0) { 163 if (gpio_direction_input(pin) == 0) {
164 set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); 164 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
165 } else { 165 } else {
166 printk(KERN_ERR "rd88f5182_pci_preinit faield to " 166 printk(KERN_ERR "rd88f5182_pci_preinit faield to "
167 "set_irq_type pin %d\n", pin); 167 "set_irq_type pin %d\n", pin);
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 5653ee6c71d8..616004143912 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -88,7 +88,7 @@ void __init tsp2_pci_preinit(void)
88 pin = TSP2_PCI_SLOT0_IRQ_PIN; 88 pin = TSP2_PCI_SLOT0_IRQ_PIN;
89 if (gpio_request(pin, "PCI Int1") == 0) { 89 if (gpio_request(pin, "PCI Int1") == 0) {
90 if (gpio_direction_input(pin) == 0) { 90 if (gpio_direction_input(pin) == 0) {
91 set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); 91 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
92 } else { 92 } else {
93 printk(KERN_ERR "tsp2_pci_preinit failed " 93 printk(KERN_ERR "tsp2_pci_preinit failed "
94 "to set_irq_type pin %d\n", pin); 94 "to set_irq_type pin %d\n", pin);
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 8bbd27ea6735..f0f43e13ac87 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -117,7 +117,7 @@ void __init qnap_ts209_pci_preinit(void)
117 pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; 117 pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN;
118 if (gpio_request(pin, "PCI Int1") == 0) { 118 if (gpio_request(pin, "PCI Int1") == 0) {
119 if (gpio_direction_input(pin) == 0) { 119 if (gpio_direction_input(pin) == 0) {
120 set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); 120 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
121 } else { 121 } else {
122 printk(KERN_ERR "qnap_ts209_pci_preinit failed to " 122 printk(KERN_ERR "qnap_ts209_pci_preinit failed to "
123 "set_irq_type pin %d\n", pin); 123 "set_irq_type pin %d\n", pin);
@@ -131,7 +131,7 @@ void __init qnap_ts209_pci_preinit(void)
131 pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; 131 pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN;
132 if (gpio_request(pin, "PCI Int2") == 0) { 132 if (gpio_request(pin, "PCI Int2") == 0) {
133 if (gpio_direction_input(pin) == 0) { 133 if (gpio_direction_input(pin) == 0) {
134 set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); 134 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
135 } else { 135 } else {
136 printk(KERN_ERR "qnap_ts209_pci_preinit failed " 136 printk(KERN_ERR "qnap_ts209_pci_preinit failed "
137 "to set_irq_type pin %d\n", pin); 137 "to set_irq_type pin %d\n", pin);
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index 8554707d20a9..edb1dd2d1611 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -402,7 +402,7 @@ static void ts78xx_fpga_supports(void)
402 /* enable devices if magic matches */ 402 /* enable devices if magic matches */
403 switch ((ts78xx_fpga.id >> 8) & 0xffffff) { 403 switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
404 case TS7800_FPGA_MAGIC: 404 case TS7800_FPGA_MAGIC:
405 printk(KERN_WARNING "TS-7800 FPGA: unrecognized revision 0x%.2x\n", 405 pr_warning("TS-7800 FPGA: unrecognized revision 0x%.2x\n",
406 ts78xx_fpga.id & 0xff); 406 ts78xx_fpga.id & 0xff);
407 ts78xx_fpga.supports.ts_rtc.present = 1; 407 ts78xx_fpga.supports.ts_rtc.present = 1;
408 ts78xx_fpga.supports.ts_nand.present = 1; 408 ts78xx_fpga.supports.ts_nand.present = 1;
@@ -423,7 +423,7 @@ static int ts78xx_fpga_load_devices(void)
423 if (ts78xx_fpga.supports.ts_rtc.present == 1) { 423 if (ts78xx_fpga.supports.ts_rtc.present == 1) {
424 tmp = ts78xx_ts_rtc_load(); 424 tmp = ts78xx_ts_rtc_load();
425 if (tmp) { 425 if (tmp) {
426 printk(KERN_INFO "TS-78xx: RTC not registered\n"); 426 pr_info("TS-78xx: RTC not registered\n");
427 ts78xx_fpga.supports.ts_rtc.present = 0; 427 ts78xx_fpga.supports.ts_rtc.present = 0;
428 } 428 }
429 ret |= tmp; 429 ret |= tmp;
@@ -431,7 +431,7 @@ static int ts78xx_fpga_load_devices(void)
431 if (ts78xx_fpga.supports.ts_nand.present == 1) { 431 if (ts78xx_fpga.supports.ts_nand.present == 1) {
432 tmp = ts78xx_ts_nand_load(); 432 tmp = ts78xx_ts_nand_load();
433 if (tmp) { 433 if (tmp) {
434 printk(KERN_INFO "TS-78xx: NAND not registered\n"); 434 pr_info("TS-78xx: NAND not registered\n");
435 ts78xx_fpga.supports.ts_nand.present = 0; 435 ts78xx_fpga.supports.ts_nand.present = 0;
436 } 436 }
437 ret |= tmp; 437 ret |= tmp;
@@ -439,7 +439,7 @@ static int ts78xx_fpga_load_devices(void)
439 if (ts78xx_fpga.supports.ts_rng.present == 1) { 439 if (ts78xx_fpga.supports.ts_rng.present == 1) {
440 tmp = ts78xx_ts_rng_load(); 440 tmp = ts78xx_ts_rng_load();
441 if (tmp) { 441 if (tmp) {
442 printk(KERN_INFO "TS-78xx: RNG not registered\n"); 442 pr_info("TS-78xx: RNG not registered\n");
443 ts78xx_fpga.supports.ts_rng.present = 0; 443 ts78xx_fpga.supports.ts_rng.present = 0;
444 } 444 }
445 ret |= tmp; 445 ret |= tmp;
@@ -466,7 +466,7 @@ static int ts78xx_fpga_load(void)
466{ 466{
467 ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE); 467 ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
468 468
469 printk(KERN_INFO "TS-78xx FPGA: magic=0x%.6x, rev=0x%.2x\n", 469 pr_info("TS-78xx FPGA: magic=0x%.6x, rev=0x%.2x\n",
470 (ts78xx_fpga.id >> 8) & 0xffffff, 470 (ts78xx_fpga.id >> 8) & 0xffffff,
471 ts78xx_fpga.id & 0xff); 471 ts78xx_fpga.id & 0xff);
472 472
@@ -494,7 +494,7 @@ static int ts78xx_fpga_unload(void)
494 * UrJTAG SVN since r1381 can be used to reprogram the FPGA 494 * UrJTAG SVN since r1381 can be used to reprogram the FPGA
495 */ 495 */
496 if (ts78xx_fpga.id != fpga_id) { 496 if (ts78xx_fpga.id != fpga_id) {
497 printk(KERN_ERR "TS-78xx FPGA: magic/rev mismatch\n" 497 pr_err("TS-78xx FPGA: magic/rev mismatch\n"
498 "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n", 498 "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n",
499 (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff, 499 (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff,
500 (fpga_id >> 8) & 0xffffff, fpga_id & 0xff); 500 (fpga_id >> 8) & 0xffffff, fpga_id & 0xff);
@@ -525,7 +525,7 @@ static ssize_t ts78xx_fpga_store(struct kobject *kobj,
525 int value, ret; 525 int value, ret;
526 526
527 if (ts78xx_fpga.state < 0) { 527 if (ts78xx_fpga.state < 0) {
528 printk(KERN_ERR "TS-78xx FPGA: borked, you must powercycle asap\n"); 528 pr_err("TS-78xx FPGA: borked, you must powercycle asap\n");
529 return -EBUSY; 529 return -EBUSY;
530 } 530 }
531 531
@@ -534,7 +534,7 @@ static ssize_t ts78xx_fpga_store(struct kobject *kobj,
534 else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0) 534 else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0)
535 value = 0; 535 value = 0;
536 else { 536 else {
537 printk(KERN_ERR "ts78xx_fpga_store: Invalid value\n"); 537 pr_err("ts78xx_fpga_store: Invalid value\n");
538 return -EINVAL; 538 return -EINVAL;
539 } 539 }
540 540
@@ -616,7 +616,7 @@ static void __init ts78xx_init(void)
616 ret = ts78xx_fpga_load(); 616 ret = ts78xx_fpga_load();
617 ret = sysfs_create_file(power_kobj, &ts78xx_fpga_attr.attr); 617 ret = sysfs_create_file(power_kobj, &ts78xx_fpga_attr.attr);
618 if (ret) 618 if (ret)
619 printk(KERN_ERR "sysfs_create_file failed: %d\n", ret); 619 pr_err("sysfs_create_file failed: %d\n", ret);
620} 620}
621 621
622MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC") 622MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
index c69c180aec76..7608c7a288cf 100644
--- a/arch/arm/mach-pnx4008/irq.c
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -58,22 +58,22 @@ static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type)
58 case IRQ_TYPE_EDGE_RISING: 58 case IRQ_TYPE_EDGE_RISING:
59 __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ 59 __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
60 __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */ 60 __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */
61 set_irq_handler(d->irq, handle_edge_irq); 61 irq_set_handler(d->irq, handle_edge_irq);
62 break; 62 break;
63 case IRQ_TYPE_EDGE_FALLING: 63 case IRQ_TYPE_EDGE_FALLING:
64 __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ 64 __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
65 __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */ 65 __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */
66 set_irq_handler(d->irq, handle_edge_irq); 66 irq_set_handler(d->irq, handle_edge_irq);
67 break; 67 break;
68 case IRQ_TYPE_LEVEL_LOW: 68 case IRQ_TYPE_LEVEL_LOW:
69 __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ 69 __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
70 __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */ 70 __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */
71 set_irq_handler(d->irq, handle_level_irq); 71 irq_set_handler(d->irq, handle_level_irq);
72 break; 72 break;
73 case IRQ_TYPE_LEVEL_HIGH: 73 case IRQ_TYPE_LEVEL_HIGH:
74 __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ 74 __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
75 __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */ 75 __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */
76 set_irq_handler(d->irq, handle_level_irq); 76 irq_set_handler(d->irq, handle_level_irq);
77 break; 77 break;
78 78
79 /* IRQ_TYPE_EDGE_BOTH is not supported */ 79 /* IRQ_TYPE_EDGE_BOTH is not supported */
@@ -98,7 +98,7 @@ void __init pnx4008_init_irq(void)
98 /* configure IRQ's */ 98 /* configure IRQ's */
99 for (i = 0; i < NR_IRQS; i++) { 99 for (i = 0; i < NR_IRQS; i++) {
100 set_irq_flags(i, IRQF_VALID); 100 set_irq_flags(i, IRQF_VALID);
101 set_irq_chip(i, &pnx4008_irq_chip); 101 irq_set_chip(i, &pnx4008_irq_chip);
102 pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]); 102 pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]);
103 } 103 }
104 104
diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c
index 3499fada73ae..4cb069fd9af2 100644
--- a/arch/arm/mach-pxa/am200epd.c
+++ b/arch/arm/mach-pxa/am200epd.c
@@ -128,8 +128,8 @@ static int am200_init_gpio_regs(struct metronomefb_par *par)
128 return 0; 128 return 0;
129 129
130err_req_gpio: 130err_req_gpio:
131 while (i > 0) 131 while (--i >= 0)
132 gpio_free(gpios[i--]); 132 gpio_free(gpios[i]);
133 133
134 return err; 134 return err;
135} 135}
@@ -194,7 +194,7 @@ static struct notifier_block am200_fb_notif = {
194}; 194};
195 195
196/* this gets called as part of our init. these steps must be done now so 196/* this gets called as part of our init. these steps must be done now so
197 * that we can use set_pxa_fb_info */ 197 * that we can use pxa_set_fb_info */
198static void __init am200_presetup_fb(void) 198static void __init am200_presetup_fb(void)
199{ 199{
200 int fw; 200 int fw;
@@ -249,7 +249,7 @@ static void __init am200_presetup_fb(void)
249 /* we divide since we told the LCD controller we're 16bpp */ 249 /* we divide since we told the LCD controller we're 16bpp */
250 am200_fb_info.modes->xres /= 2; 250 am200_fb_info.modes->xres /= 2;
251 251
252 set_pxa_fb_info(&am200_fb_info); 252 pxa_set_fb_info(NULL, &am200_fb_info);
253 253
254} 254}
255 255
diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c
index 993d75e66390..fa8bad235d9f 100644
--- a/arch/arm/mach-pxa/am300epd.c
+++ b/arch/arm/mach-pxa/am300epd.c
@@ -125,10 +125,7 @@ static int am300_init_gpio_regs(struct broadsheetfb_par *par)
125 if (err) { 125 if (err) {
126 dev_err(&am300_device->dev, "failed requesting " 126 dev_err(&am300_device->dev, "failed requesting "
127 "gpio %d, err=%d\n", i, err); 127 "gpio %d, err=%d\n", i, err);
128 while (i >= DB0_GPIO_PIN) 128 goto err_req_gpio2;
129 gpio_free(i--);
130 i = ARRAY_SIZE(gpios) - 1;
131 goto err_req_gpio;
132 } 129 }
133 } 130 }
134 131
@@ -159,9 +156,13 @@ static int am300_init_gpio_regs(struct broadsheetfb_par *par)
159 156
160 return 0; 157 return 0;
161 158
159err_req_gpio2:
160 while (--i >= DB0_GPIO_PIN)
161 gpio_free(i);
162 i = ARRAY_SIZE(gpios);
162err_req_gpio: 163err_req_gpio:
163 while (i > 0) 164 while (--i >= 0)
164 gpio_free(gpios[i--]); 165 gpio_free(gpios[i]);
165 166
166 return err; 167 return err;
167} 168}
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index d2af73321dae..bfbecec6d05f 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -263,7 +263,7 @@ static void __init balloon3_lcd_init(void)
263 } 263 }
264 264
265 balloon3_lcd_screen.pxafb_backlight_power = balloon3_backlight_power; 265 balloon3_lcd_screen.pxafb_backlight_power = balloon3_backlight_power;
266 set_pxa_fb_info(&balloon3_lcd_screen); 266 pxa_set_fb_info(NULL, &balloon3_lcd_screen);
267 return; 267 return;
268 268
269err2: 269err2:
@@ -527,13 +527,13 @@ static void __init balloon3_init_irq(void)
527 pxa27x_init_irq(); 527 pxa27x_init_irq();
528 /* setup extra Balloon3 irqs */ 528 /* setup extra Balloon3 irqs */
529 for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) { 529 for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) {
530 set_irq_chip(irq, &balloon3_irq_chip); 530 irq_set_chip_and_handler(irq, &balloon3_irq_chip,
531 set_irq_handler(irq, handle_level_irq); 531 handle_level_irq);
532 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 532 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
533 } 533 }
534 534
535 set_irq_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler); 535 irq_set_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler);
536 set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING); 536 irq_set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING);
537 537
538 pr_debug("%s: chained handler installed - irq %d automatically " 538 pr_debug("%s: chained handler installed - irq %d automatically "
539 "enabled\n", __func__, BALLOON3_AUX_NIRQ); 539 "enabled\n", __func__, BALLOON3_AUX_NIRQ);
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c
index a2380cd76f80..8b1a30959fae 100644
--- a/arch/arm/mach-pxa/cm-x2xx-pci.c
+++ b/arch/arm/mach-pxa/cm-x2xx-pci.c
@@ -70,9 +70,10 @@ void __cmx2xx_pci_init_irq(int irq_gpio)
70 70
71 cmx2xx_it8152_irq_gpio = irq_gpio; 71 cmx2xx_it8152_irq_gpio = irq_gpio;
72 72
73 set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING); 73 irq_set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
74 74
75 set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx2xx_it8152_irq_demux); 75 irq_set_chained_handler(gpio_to_irq(irq_gpio),
76 cmx2xx_it8152_irq_demux);
76} 77}
77 78
78#ifdef CONFIG_PM 79#ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index b734d8468168..8225e2e58c6e 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -379,7 +379,7 @@ __setup("monitor=", cmx2xx_set_display);
379 379
380static void __init cmx2xx_init_display(void) 380static void __init cmx2xx_init_display(void)
381{ 381{
382 set_pxa_fb_info(cmx2xx_display); 382 pxa_set_fb_info(NULL, cmx2xx_display);
383} 383}
384#else 384#else
385static inline void cmx2xx_init_display(void) {} 385static inline void cmx2xx_init_display(void) {}
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index bfca7ed2fea3..b2248e76ec8b 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -296,7 +296,7 @@ static struct pxafb_mach_info cm_x300_lcd = {
296 296
297static void __init cm_x300_init_lcd(void) 297static void __init cm_x300_init_lcd(void)
298{ 298{
299 set_pxa_fb_info(&cm_x300_lcd); 299 pxa_set_fb_info(NULL, &cm_x300_lcd);
300} 300}
301#else 301#else
302static inline void cm_x300_init_lcd(void) {} 302static inline void cm_x300_init_lcd(void) {}
@@ -765,7 +765,7 @@ static void __init cm_x300_init_da9030(void)
765{ 765{
766 pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info); 766 pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info);
767 i2c_register_board_info(1, &cm_x300_pmic_info, 1); 767 i2c_register_board_info(1, &cm_x300_pmic_info, 1);
768 set_irq_wake(IRQ_WAKEUP0, 1); 768 irq_set_irq_wake(IRQ_WAKEUP0, 1);
769} 769}
770 770
771static void __init cm_x300_init_wi2wi(void) 771static void __init cm_x300_init_wi2wi(void)
diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c
index ee797397dc5b..44c1b77ece67 100644
--- a/arch/arm/mach-pxa/colibri-pxa270-income.c
+++ b/arch/arm/mach-pxa/colibri-pxa270-income.c
@@ -175,7 +175,7 @@ static struct pxafb_mach_info income_lcd_screen = {
175 175
176static void __init income_lcd_init(void) 176static void __init income_lcd_init(void)
177{ 177{
178 set_pxa_fb_info(&income_lcd_screen); 178 pxa_set_fb_info(NULL, &income_lcd_screen);
179} 179}
180#else 180#else
181static inline void income_lcd_init(void) {} 181static inline void income_lcd_init(void) {}
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c
index 96b2d9fbfef0..3f9be419959d 100644
--- a/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -105,7 +105,7 @@ void __init colibri_pxa3xx_init_lcd(int bl_pin)
105 lcd_bl_pin = bl_pin; 105 lcd_bl_pin = bl_pin;
106 gpio_request(bl_pin, "lcd backlight"); 106 gpio_request(bl_pin, "lcd backlight");
107 gpio_direction_output(bl_pin, 0); 107 gpio_direction_output(bl_pin, 0);
108 set_pxa_fb_info(&sharp_lq43_info); 108 pxa_set_fb_info(NULL, &sharp_lq43_info);
109} 109}
110#endif 110#endif
111 111
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index d4e705caefea..3a5507e31919 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -462,7 +462,6 @@ static struct pxaficp_platform_data corgi_ficp_platform_data = {
462 * USB Device Controller 462 * USB Device Controller
463 */ 463 */
464static struct pxa2xx_udc_mach_info udc_info __initdata = { 464static struct pxa2xx_udc_mach_info udc_info __initdata = {
465 .gpio_vbus = -1,
466 /* no connect GPIO; corgi can't tell connection status */ 465 /* no connect GPIO; corgi can't tell connection status */
467 .gpio_pullup = CORGI_GPIO_USB_PULLUP, 466 .gpio_pullup = CORGI_GPIO_USB_PULLUP,
468}; 467};
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index c4bf08b3eb61..2e0425404de5 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -90,7 +90,6 @@ void __init pxa_set_mci_info(struct pxamci_platform_data *info)
90 90
91static struct pxa2xx_udc_mach_info pxa_udc_info = { 91static struct pxa2xx_udc_mach_info pxa_udc_info = {
92 .gpio_pullup = -1, 92 .gpio_pullup = -1,
93 .gpio_vbus = -1,
94}; 93};
95 94
96void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info) 95void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
@@ -188,16 +187,12 @@ struct platform_device pxa_device_fb = {
188 .resource = pxafb_resources, 187 .resource = pxafb_resources,
189}; 188};
190 189
191void __init set_pxa_fb_info(struct pxafb_mach_info *info) 190void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
192{ 191{
192 pxa_device_fb.dev.parent = parent;
193 pxa_register_device(&pxa_device_fb, info); 193 pxa_register_device(&pxa_device_fb, info);
194} 194}
195 195
196void __init set_pxa_fb_parent(struct device *parent_dev)
197{
198 pxa_device_fb.dev.parent = parent_dev;
199}
200
201static struct resource pxa_resource_ffuart[] = { 196static struct resource pxa_resource_ffuart[] = {
202 { 197 {
203 .start = 0x40100000, 198 .start = 0x40100000,
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index b411d7cbf5a1..f8a6e9d79a3a 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -689,7 +689,7 @@ static struct pxafb_mach_info em_x270_lcd = {
689 689
690static void __init em_x270_init_lcd(void) 690static void __init em_x270_init_lcd(void)
691{ 691{
692 set_pxa_fb_info(&em_x270_lcd); 692 pxa_set_fb_info(NULL, &em_x270_lcd);
693} 693}
694#else 694#else
695static inline void em_x270_init_lcd(void) {} 695static inline void em_x270_init_lcd(void) {}
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index edca0a043293..2e3970fdde0b 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -20,6 +20,7 @@
20#include <linux/mfd/t7l66xb.h> 20#include <linux/mfd/t7l66xb.h>
21#include <linux/mtd/nand.h> 21#include <linux/mtd/nand.h>
22#include <linux/mtd/partitions.h> 22#include <linux/mtd/partitions.h>
23#include <linux/usb/gpio_vbus.h>
23 24
24#include <video/w100fb.h> 25#include <video/w100fb.h>
25 26
@@ -51,12 +52,20 @@ void __init eseries_fixup(struct machine_desc *desc,
51 mi->bank[0].size = (64*1024*1024); 52 mi->bank[0].size = (64*1024*1024);
52} 53}
53 54
54struct pxa2xx_udc_mach_info e7xx_udc_mach_info = { 55struct gpio_vbus_mach_info e7xx_udc_info = {
55 .gpio_vbus = GPIO_E7XX_USB_DISC, 56 .gpio_vbus = GPIO_E7XX_USB_DISC,
56 .gpio_pullup = GPIO_E7XX_USB_PULLUP, 57 .gpio_pullup = GPIO_E7XX_USB_PULLUP,
57 .gpio_pullup_inverted = 1 58 .gpio_pullup_inverted = 1
58}; 59};
59 60
61static struct platform_device e7xx_gpio_vbus = {
62 .name = "gpio-vbus",
63 .id = -1,
64 .dev = {
65 .platform_data = &e7xx_udc_info,
66 },
67};
68
60struct pxaficp_platform_data e7xx_ficp_platform_data = { 69struct pxaficp_platform_data e7xx_ficp_platform_data = {
61 .gpio_pwdown = GPIO_E7XX_IR_OFF, 70 .gpio_pwdown = GPIO_E7XX_IR_OFF,
62 .transceiver_cap = IR_SIRMODE | IR_OFF, 71 .transceiver_cap = IR_SIRMODE | IR_OFF,
@@ -165,6 +174,7 @@ static struct platform_device e330_tc6387xb_device = {
165 174
166static struct platform_device *e330_devices[] __initdata = { 175static struct platform_device *e330_devices[] __initdata = {
167 &e330_tc6387xb_device, 176 &e330_tc6387xb_device,
177 &e7xx_gpio_vbus,
168}; 178};
169 179
170static void __init e330_init(void) 180static void __init e330_init(void)
@@ -175,7 +185,6 @@ static void __init e330_init(void)
175 eseries_register_clks(); 185 eseries_register_clks();
176 eseries_get_tmio_gpios(); 186 eseries_get_tmio_gpios();
177 platform_add_devices(ARRAY_AND_SIZE(e330_devices)); 187 platform_add_devices(ARRAY_AND_SIZE(e330_devices));
178 pxa_set_udc_info(&e7xx_udc_mach_info);
179} 188}
180 189
181MACHINE_START(E330, "Toshiba e330") 190MACHINE_START(E330, "Toshiba e330")
@@ -214,6 +223,7 @@ static struct platform_device e350_t7l66xb_device = {
214 223
215static struct platform_device *e350_devices[] __initdata = { 224static struct platform_device *e350_devices[] __initdata = {
216 &e350_t7l66xb_device, 225 &e350_t7l66xb_device,
226 &e7xx_gpio_vbus,
217}; 227};
218 228
219static void __init e350_init(void) 229static void __init e350_init(void)
@@ -224,7 +234,6 @@ static void __init e350_init(void)
224 eseries_register_clks(); 234 eseries_register_clks();
225 eseries_get_tmio_gpios(); 235 eseries_get_tmio_gpios();
226 platform_add_devices(ARRAY_AND_SIZE(e350_devices)); 236 platform_add_devices(ARRAY_AND_SIZE(e350_devices));
227 pxa_set_udc_info(&e7xx_udc_mach_info);
228} 237}
229 238
230MACHINE_START(E350, "Toshiba e350") 239MACHINE_START(E350, "Toshiba e350")
@@ -333,6 +342,7 @@ static struct platform_device e400_t7l66xb_device = {
333 342
334static struct platform_device *e400_devices[] __initdata = { 343static struct platform_device *e400_devices[] __initdata = {
335 &e400_t7l66xb_device, 344 &e400_t7l66xb_device,
345 &e7xx_gpio_vbus,
336}; 346};
337 347
338static void __init e400_init(void) 348static void __init e400_init(void)
@@ -344,9 +354,8 @@ static void __init e400_init(void)
344 /* Fixme - e400 may have a switched clock */ 354 /* Fixme - e400 may have a switched clock */
345 eseries_register_clks(); 355 eseries_register_clks();
346 eseries_get_tmio_gpios(); 356 eseries_get_tmio_gpios();
347 set_pxa_fb_info(&e400_pxafb_mach_info); 357 pxa_set_fb_info(NULL, &e400_pxafb_mach_info);
348 platform_add_devices(ARRAY_AND_SIZE(e400_devices)); 358 platform_add_devices(ARRAY_AND_SIZE(e400_devices));
349 pxa_set_udc_info(&e7xx_udc_mach_info);
350} 359}
351 360
352MACHINE_START(E400, "Toshiba e400") 361MACHINE_START(E400, "Toshiba e400")
@@ -519,6 +528,7 @@ static struct platform_device e740_t7l66xb_device = {
519static struct platform_device *e740_devices[] __initdata = { 528static struct platform_device *e740_devices[] __initdata = {
520 &e740_fb_device, 529 &e740_fb_device,
521 &e740_t7l66xb_device, 530 &e740_t7l66xb_device,
531 &e7xx_gpio_vbus,
522}; 532};
523 533
524static void __init e740_init(void) 534static void __init e740_init(void)
@@ -532,7 +542,6 @@ static void __init e740_init(void)
532 "UDCCLK", &pxa25x_device_udc.dev), 542 "UDCCLK", &pxa25x_device_udc.dev),
533 eseries_get_tmio_gpios(); 543 eseries_get_tmio_gpios();
534 platform_add_devices(ARRAY_AND_SIZE(e740_devices)); 544 platform_add_devices(ARRAY_AND_SIZE(e740_devices));
535 pxa_set_udc_info(&e7xx_udc_mach_info);
536 pxa_set_ac97_info(NULL); 545 pxa_set_ac97_info(NULL);
537 pxa_set_ficp_info(&e7xx_ficp_platform_data); 546 pxa_set_ficp_info(&e7xx_ficp_platform_data);
538} 547}
@@ -711,6 +720,7 @@ static struct platform_device e750_tc6393xb_device = {
711static struct platform_device *e750_devices[] __initdata = { 720static struct platform_device *e750_devices[] __initdata = {
712 &e750_fb_device, 721 &e750_fb_device,
713 &e750_tc6393xb_device, 722 &e750_tc6393xb_device,
723 &e7xx_gpio_vbus,
714}; 724};
715 725
716static void __init e750_init(void) 726static void __init e750_init(void)
@@ -723,7 +733,6 @@ static void __init e750_init(void)
723 "GPIO11_CLK", NULL), 733 "GPIO11_CLK", NULL),
724 eseries_get_tmio_gpios(); 734 eseries_get_tmio_gpios();
725 platform_add_devices(ARRAY_AND_SIZE(e750_devices)); 735 platform_add_devices(ARRAY_AND_SIZE(e750_devices));
726 pxa_set_udc_info(&e7xx_udc_mach_info);
727 pxa_set_ac97_info(NULL); 736 pxa_set_ac97_info(NULL);
728 pxa_set_ficp_info(&e7xx_ficp_platform_data); 737 pxa_set_ficp_info(&e7xx_ficp_platform_data);
729} 738}
@@ -873,12 +882,21 @@ static struct platform_device e800_fb_device = {
873 882
874/* --------------------------- UDC definitions --------------------------- */ 883/* --------------------------- UDC definitions --------------------------- */
875 884
876static struct pxa2xx_udc_mach_info e800_udc_mach_info = { 885static struct gpio_vbus_mach_info e800_udc_info = {
877 .gpio_vbus = GPIO_E800_USB_DISC, 886 .gpio_vbus = GPIO_E800_USB_DISC,
878 .gpio_pullup = GPIO_E800_USB_PULLUP, 887 .gpio_pullup = GPIO_E800_USB_PULLUP,
879 .gpio_pullup_inverted = 1 888 .gpio_pullup_inverted = 1
880}; 889};
881 890
891static struct platform_device e800_gpio_vbus = {
892 .name = "gpio-vbus",
893 .id = -1,
894 .dev = {
895 .platform_data = &e800_udc_info,
896 },
897};
898
899
882/* ----------------- e800 tc6393xb parameters ------------------ */ 900/* ----------------- e800 tc6393xb parameters ------------------ */
883 901
884static struct tc6393xb_platform_data e800_tc6393xb_info = { 902static struct tc6393xb_platform_data e800_tc6393xb_info = {
@@ -907,6 +925,7 @@ static struct platform_device e800_tc6393xb_device = {
907static struct platform_device *e800_devices[] __initdata = { 925static struct platform_device *e800_devices[] __initdata = {
908 &e800_fb_device, 926 &e800_fb_device,
909 &e800_tc6393xb_device, 927 &e800_tc6393xb_device,
928 &e800_gpio_vbus,
910}; 929};
911 930
912static void __init e800_init(void) 931static void __init e800_init(void)
@@ -919,7 +938,6 @@ static void __init e800_init(void)
919 "GPIO11_CLK", NULL), 938 "GPIO11_CLK", NULL),
920 eseries_get_tmio_gpios(); 939 eseries_get_tmio_gpios();
921 platform_add_devices(ARRAY_AND_SIZE(e800_devices)); 940 platform_add_devices(ARRAY_AND_SIZE(e800_devices));
922 pxa_set_udc_info(&e800_udc_mach_info);
923 pxa_set_ac97_info(NULL); 941 pxa_set_ac97_info(NULL);
924} 942}
925 943
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 93f05e024313..d88aed8fbe15 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -783,7 +783,7 @@ static void __init a780_init(void)
783 783
784 pxa_set_i2c_info(NULL); 784 pxa_set_i2c_info(NULL);
785 785
786 set_pxa_fb_info(&ezx_fb_info_1); 786 pxa_set_fb_info(NULL, &ezx_fb_info_1);
787 787
788 pxa_set_keypad_info(&a780_keypad_platform_data); 788 pxa_set_keypad_info(&a780_keypad_platform_data);
789 789
@@ -853,7 +853,7 @@ static void __init e680_init(void)
853 pxa_set_i2c_info(NULL); 853 pxa_set_i2c_info(NULL);
854 i2c_register_board_info(0, ARRAY_AND_SIZE(e680_i2c_board_info)); 854 i2c_register_board_info(0, ARRAY_AND_SIZE(e680_i2c_board_info));
855 855
856 set_pxa_fb_info(&ezx_fb_info_1); 856 pxa_set_fb_info(NULL, &ezx_fb_info_1);
857 857
858 pxa_set_keypad_info(&e680_keypad_platform_data); 858 pxa_set_keypad_info(&e680_keypad_platform_data);
859 859
@@ -918,7 +918,7 @@ static void __init a1200_init(void)
918 pxa_set_i2c_info(NULL); 918 pxa_set_i2c_info(NULL);
919 i2c_register_board_info(0, ARRAY_AND_SIZE(a1200_i2c_board_info)); 919 i2c_register_board_info(0, ARRAY_AND_SIZE(a1200_i2c_board_info));
920 920
921 set_pxa_fb_info(&ezx_fb_info_2); 921 pxa_set_fb_info(NULL, &ezx_fb_info_2);
922 922
923 pxa_set_keypad_info(&a1200_keypad_platform_data); 923 pxa_set_keypad_info(&a1200_keypad_platform_data);
924 924
@@ -1103,7 +1103,7 @@ static void __init a910_init(void)
1103 pxa_set_i2c_info(NULL); 1103 pxa_set_i2c_info(NULL);
1104 i2c_register_board_info(0, ARRAY_AND_SIZE(a910_i2c_board_info)); 1104 i2c_register_board_info(0, ARRAY_AND_SIZE(a910_i2c_board_info));
1105 1105
1106 set_pxa_fb_info(&ezx_fb_info_2); 1106 pxa_set_fb_info(NULL, &ezx_fb_info_2);
1107 1107
1108 pxa_set_keypad_info(&a910_keypad_platform_data); 1108 pxa_set_keypad_info(&a910_keypad_platform_data);
1109 1109
@@ -1173,7 +1173,7 @@ static void __init e6_init(void)
1173 pxa_set_i2c_info(NULL); 1173 pxa_set_i2c_info(NULL);
1174 i2c_register_board_info(0, ARRAY_AND_SIZE(e6_i2c_board_info)); 1174 i2c_register_board_info(0, ARRAY_AND_SIZE(e6_i2c_board_info));
1175 1175
1176 set_pxa_fb_info(&ezx_fb_info_2); 1176 pxa_set_fb_info(NULL, &ezx_fb_info_2);
1177 1177
1178 pxa_set_keypad_info(&e6_keypad_platform_data); 1178 pxa_set_keypad_info(&e6_keypad_platform_data);
1179 1179
@@ -1212,7 +1212,7 @@ static void __init e2_init(void)
1212 pxa_set_i2c_info(NULL); 1212 pxa_set_i2c_info(NULL);
1213 i2c_register_board_info(0, ARRAY_AND_SIZE(e2_i2c_board_info)); 1213 i2c_register_board_info(0, ARRAY_AND_SIZE(e2_i2c_board_info));
1214 1214
1215 set_pxa_fb_info(&ezx_fb_info_2); 1215 pxa_set_fb_info(NULL, &ezx_fb_info_2);
1216 1216
1217 pxa_set_keypad_info(&e2_keypad_platform_data); 1217 pxa_set_keypad_info(&e2_keypad_platform_data);
1218 1218
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index 6fd319ea5284..d65e4bde9b91 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -26,6 +26,7 @@
26#include <linux/gpio.h> 26#include <linux/gpio.h>
27#include <linux/err.h> 27#include <linux/err.h>
28#include <linux/clk.h> 28#include <linux/clk.h>
29#include <linux/usb/gpio_vbus.h>
29 30
30#include <asm/setup.h> 31#include <asm/setup.h>
31#include <asm/memory.h> 32#include <asm/memory.h>
@@ -106,14 +107,22 @@ static void __init gumstix_mmc_init(void)
106#endif 107#endif
107 108
108#ifdef CONFIG_USB_GADGET_PXA25X 109#ifdef CONFIG_USB_GADGET_PXA25X
109static struct pxa2xx_udc_mach_info gumstix_udc_info __initdata = { 110static struct gpio_vbus_mach_info gumstix_udc_info = {
110 .gpio_vbus = GPIO_GUMSTIX_USB_GPIOn, 111 .gpio_vbus = GPIO_GUMSTIX_USB_GPIOn,
111 .gpio_pullup = GPIO_GUMSTIX_USB_GPIOx, 112 .gpio_pullup = GPIO_GUMSTIX_USB_GPIOx,
112}; 113};
113 114
115static struct platform_device gumstix_gpio_vbus = {
116 .name = "gpio-vbus",
117 .id = -1,
118 .dev = {
119 .platform_data = &gumstix_udc_info,
120 },
121};
122
114static void __init gumstix_udc_init(void) 123static void __init gumstix_udc_init(void)
115{ 124{
116 pxa_set_udc_info(&gumstix_udc_info); 125 platform_device_register(&gumstix_gpio_vbus);
117} 126}
118#else 127#else
119static void gumstix_udc_init(void) 128static void gumstix_udc_init(void)
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index dd40e4a9291c..f7fb64f11a7d 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -167,7 +167,7 @@ static void __init idp_init(void)
167 167
168 platform_device_register(&smc91x_device); 168 platform_device_register(&smc91x_device);
169 //platform_device_register(&mst_audio_device); 169 //platform_device_register(&mst_audio_device);
170 set_pxa_fb_info(&sharp_lm8v31); 170 pxa_set_fb_info(NULL, &sharp_lm8v31);
171 pxa_set_mci_info(&idp_mci_platform_data); 171 pxa_set_mci_info(&idp_mci_platform_data);
172} 172}
173 173
diff --git a/arch/arm/mach-pxa/include/mach/palmz72.h b/arch/arm/mach-pxa/include/mach/palmz72.h
index 2bbcf70dd935..0d4700a79612 100644
--- a/arch/arm/mach-pxa/include/mach/palmz72.h
+++ b/arch/arm/mach-pxa/include/mach/palmz72.h
@@ -44,6 +44,11 @@
44#define GPIO_NR_PALMZ72_BT_POWER 17 44#define GPIO_NR_PALMZ72_BT_POWER 17
45#define GPIO_NR_PALMZ72_BT_RESET 83 45#define GPIO_NR_PALMZ72_BT_RESET 83
46 46
47/* Camera */
48#define GPIO_NR_PALMZ72_CAM_PWDN 56
49#define GPIO_NR_PALMZ72_CAM_RESET 57
50#define GPIO_NR_PALMZ72_CAM_POWER 91
51
47/** Initial values **/ 52/** Initial values **/
48 53
49/* Battery */ 54/* Battery */
diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h
index 160ec83f51a6..01a45ac48114 100644
--- a/arch/arm/mach-pxa/include/mach/pxafb.h
+++ b/arch/arm/mach-pxa/include/mach/pxafb.h
@@ -154,8 +154,8 @@ struct pxafb_mach_info {
154 void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *); 154 void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
155 void (*smart_update)(struct fb_info *); 155 void (*smart_update)(struct fb_info *);
156}; 156};
157void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info); 157
158void set_pxa_fb_parent(struct device *parent_dev); 158void pxa_set_fb_info(struct device *, struct pxafb_mach_info *);
159unsigned long pxafb_get_hsync_time(struct device *dev); 159unsigned long pxafb_get_hsync_time(struct device *dev);
160 160
161extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int); 161extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
diff --git a/arch/arm/mach-pxa/include/mach/z2.h b/arch/arm/mach-pxa/include/mach/z2.h
index 8835c16bc82f..7b0f71ef3167 100644
--- a/arch/arm/mach-pxa/include/mach/z2.h
+++ b/arch/arm/mach-pxa/include/mach/z2.h
@@ -25,8 +25,7 @@
25#define GPIO98_ZIPITZ2_LID_BUTTON 98 25#define GPIO98_ZIPITZ2_LID_BUTTON 98
26 26
27/* Libertas GSPI8686 WiFi */ 27/* Libertas GSPI8686 WiFi */
28#define GPIO14_ZIPITZ2_WIFI_RESET 14 28#define GPIO14_ZIPITZ2_WIFI_POWER 14
29#define GPIO15_ZIPITZ2_WIFI_POWER 15
30#define GPIO24_ZIPITZ2_WIFI_CS 24 29#define GPIO24_ZIPITZ2_WIFI_CS 24
31#define GPIO36_ZIPITZ2_WIFI_IRQ 36 30#define GPIO36_ZIPITZ2_WIFI_IRQ 36
32 31
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 2693e3c3776f..6251e3f5c62c 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -137,9 +137,9 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn)
137 GEDR0 = 0x3; 137 GEDR0 = 0x3;
138 138
139 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 139 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
140 set_irq_chip(irq, &pxa_low_gpio_chip); 140 irq_set_chip_and_handler(irq, &pxa_low_gpio_chip,
141 set_irq_chip_data(irq, irq_base(0)); 141 handle_edge_irq);
142 set_irq_handler(irq, handle_edge_irq); 142 irq_set_chip_data(irq, irq_base(0));
143 set_irq_flags(irq, IRQF_VALID); 143 set_irq_flags(irq, IRQF_VALID);
144 } 144 }
145 145
@@ -165,9 +165,9 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn)
165 __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); 165 __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
166 166
167 irq = PXA_IRQ(i); 167 irq = PXA_IRQ(i);
168 set_irq_chip(irq, &pxa_internal_irq_chip); 168 irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
169 set_irq_chip_data(irq, base); 169 handle_level_irq);
170 set_irq_handler(irq, handle_level_irq); 170 irq_set_chip_data(irq, base);
171 set_irq_flags(irq, IRQF_VALID); 171 set_irq_flags(irq, IRQF_VALID);
172 } 172 }
173 } 173 }
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 87c1ed9ccd2f..e5e326d2cdc9 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -185,7 +185,7 @@ static struct pxafb_mach_info littleton_lcd_info = {
185 185
186static void littleton_init_lcd(void) 186static void littleton_init_lcd(void)
187{ 187{
188 set_pxa_fb_info(&littleton_lcd_info); 188 pxa_set_fb_info(NULL, &littleton_lcd_info);
189} 189}
190#else 190#else
191static inline void littleton_init_lcd(void) {}; 191static inline void littleton_init_lcd(void) {};
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index c9a3e775c2de..f5de541725b1 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -149,12 +149,12 @@ static void __init lpd270_init_irq(void)
149 149
150 /* setup extra LogicPD PXA270 irqs */ 150 /* setup extra LogicPD PXA270 irqs */
151 for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { 151 for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
152 set_irq_chip(irq, &lpd270_irq_chip); 152 irq_set_chip_and_handler(irq, &lpd270_irq_chip,
153 set_irq_handler(irq, handle_level_irq); 153 handle_level_irq);
154 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 154 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
155 } 155 }
156 set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); 156 irq_set_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
157 set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); 157 irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
158} 158}
159 159
160 160
@@ -480,7 +480,7 @@ static void __init lpd270_init(void)
480 pxa_set_ac97_info(NULL); 480 pxa_set_ac97_info(NULL);
481 481
482 if (lpd270_lcd_to_use != NULL) 482 if (lpd270_lcd_to_use != NULL)
483 set_pxa_fb_info(lpd270_lcd_to_use); 483 pxa_set_fb_info(NULL, lpd270_lcd_to_use);
484 484
485 pxa_set_ohci_info(&lpd270_ohci_platform_data); 485 pxa_set_ohci_info(&lpd270_ohci_platform_data);
486} 486}
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index dca20de306bb..3ede978c83d9 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -165,13 +165,13 @@ static void __init lubbock_init_irq(void)
165 165
166 /* setup extra lubbock irqs */ 166 /* setup extra lubbock irqs */
167 for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) { 167 for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
168 set_irq_chip(irq, &lubbock_irq_chip); 168 irq_set_chip_and_handler(irq, &lubbock_irq_chip,
169 set_irq_handler(irq, handle_level_irq); 169 handle_level_irq);
170 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 170 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
171 } 171 }
172 172
173 set_irq_chained_handler(IRQ_GPIO(0), lubbock_irq_handler); 173 irq_set_chained_handler(IRQ_GPIO(0), lubbock_irq_handler);
174 set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); 174 irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
175} 175}
176 176
177#ifdef CONFIG_PM 177#ifdef CONFIG_PM
@@ -521,7 +521,7 @@ static void __init lubbock_init(void)
521 521
522 clk_add_alias("SA1111_CLK", NULL, "GPIO11_CLK", NULL); 522 clk_add_alias("SA1111_CLK", NULL, "GPIO11_CLK", NULL);
523 pxa_set_udc_info(&udc_info); 523 pxa_set_udc_info(&udc_info);
524 set_pxa_fb_info(&sharp_lm8v31); 524 pxa_set_fb_info(NULL, &sharp_lm8v31);
525 pxa_set_mci_info(&lubbock_mci_platform_data); 525 pxa_set_mci_info(&lubbock_mci_platform_data);
526 pxa_set_ficp_info(&lubbock_ficp_platform_data); 526 pxa_set_ficp_info(&lubbock_ficp_platform_data);
527 pxa_set_ac97_info(NULL); 527 pxa_set_ac97_info(NULL);
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 5535991c4a3c..a72993dde2b3 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -757,7 +757,7 @@ static void __init magician_init(void)
757 gpio_direction_output(GPIO104_MAGICIAN_LCD_POWER_1, 0); 757 gpio_direction_output(GPIO104_MAGICIAN_LCD_POWER_1, 0);
758 gpio_direction_output(GPIO105_MAGICIAN_LCD_POWER_2, 0); 758 gpio_direction_output(GPIO105_MAGICIAN_LCD_POWER_2, 0);
759 gpio_direction_output(GPIO106_MAGICIAN_LCD_POWER_3, 0); 759 gpio_direction_output(GPIO106_MAGICIAN_LCD_POWER_3, 0);
760 set_pxa_fb_info(lcd_select ? &samsung_info : &toppoly_info); 760 pxa_set_fb_info(NULL, lcd_select ? &samsung_info : &toppoly_info);
761 } else 761 } else
762 pr_err("LCD detection: CPLD mapping failed\n"); 762 pr_err("LCD detection: CPLD mapping failed\n");
763} 763}
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index f9542220595a..95163baca29e 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -166,8 +166,8 @@ static void __init mainstone_init_irq(void)
166 166
167 /* setup extra Mainstone irqs */ 167 /* setup extra Mainstone irqs */
168 for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { 168 for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
169 set_irq_chip(irq, &mainstone_irq_chip); 169 irq_set_chip_and_handler(irq, &mainstone_irq_chip,
170 set_irq_handler(irq, handle_level_irq); 170 handle_level_irq);
171 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) 171 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
172 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); 172 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
173 else 173 else
@@ -179,8 +179,8 @@ static void __init mainstone_init_irq(void)
179 MST_INTMSKENA = 0; 179 MST_INTMSKENA = 0;
180 MST_INTSETCLR = 0; 180 MST_INTSETCLR = 0;
181 181
182 set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); 182 irq_set_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
183 set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); 183 irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
184} 184}
185 185
186#ifdef CONFIG_PM 186#ifdef CONFIG_PM
@@ -592,7 +592,7 @@ static void __init mainstone_init(void)
592 else 592 else
593 mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode; 593 mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode;
594 594
595 set_pxa_fb_info(&mainstone_pxafb_info); 595 pxa_set_fb_info(NULL, &mainstone_pxafb_info);
596 mainstone_backlight_register(); 596 mainstone_backlight_register();
597 597
598 pxa_set_mci_info(&mainstone_mci_platform_data); 598 pxa_set_mci_info(&mainstone_mci_platform_data);
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 78d98a8607ec..dd13bb63259b 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -795,7 +795,7 @@ static void __init mioa701_machine_init(void)
795 pxa_set_stuart_info(NULL); 795 pxa_set_stuart_info(NULL);
796 mio_gpio_request(ARRAY_AND_SIZE(global_gpios)); 796 mio_gpio_request(ARRAY_AND_SIZE(global_gpios));
797 bootstrap_init(); 797 bootstrap_init();
798 set_pxa_fb_info(&mioa701_pxafb_info); 798 pxa_set_fb_info(NULL, &mioa701_pxafb_info);
799 pxa_set_mci_info(&mioa701_mci_info); 799 pxa_set_mci_info(&mioa701_mci_info);
800 pxa_set_keypad_info(&mioa701_keypad_info); 800 pxa_set_keypad_info(&mioa701_keypad_info);
801 pxa_set_udc_info(&mioa701_udc_info); 801 pxa_set_udc_info(&mioa701_udc_info);
diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c
index 72adb3ae2b43..325c245c0a0d 100644
--- a/arch/arm/mach-pxa/palm27x.c
+++ b/arch/arm/mach-pxa/palm27x.c
@@ -1,8 +1,7 @@
1/* 1/*
2 * Common code for Palm LD, T5, TX, Z72 2 * Common code for Palm LD, T5, TX, Z72
3 * 3 *
4 * Copyright (C) 2010 4 * Copyright (C) 2010-2011 Marek Vasut <marek.vasut@gmail.com>
5 * Marek Vasut <marek.vasut@gmail.com>
6 * 5 *
7 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -158,7 +157,7 @@ void __init palm27x_lcd_init(int power, struct pxafb_mode_info *mode)
158 palm27x_lcd_screen.pxafb_lcd_power = palm27x_lcd_ctl; 157 palm27x_lcd_screen.pxafb_lcd_power = palm27x_lcd_ctl;
159 } 158 }
160 159
161 set_pxa_fb_info(&palm27x_lcd_screen); 160 pxa_set_fb_info(NULL, &palm27x_lcd_screen);
162} 161}
163#endif 162#endif
164 163
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index a09a2374697b..fb06bd047272 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -507,7 +507,7 @@ static struct pxafb_mach_info palmtc_lcd_screen = {
507 507
508static void __init palmtc_lcd_init(void) 508static void __init palmtc_lcd_init(void)
509{ 509{
510 set_pxa_fb_info(&palmtc_lcd_screen); 510 pxa_set_fb_info(NULL, &palmtc_lcd_screen);
511} 511}
512#else 512#else
513static inline void palmtc_lcd_init(void) {} 513static inline void palmtc_lcd_init(void) {}
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index 3f25014a136c..726f5b98dcd3 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -136,30 +136,14 @@ static struct platform_device palmte2_pxa_keys = {
136/****************************************************************************** 136/******************************************************************************
137 * Backlight 137 * Backlight
138 ******************************************************************************/ 138 ******************************************************************************/
139static struct gpio palmte_bl_gpios[] = {
140 { GPIO_NR_PALMTE2_BL_POWER, GPIOF_INIT_LOW, "Backlight power" },
141 { GPIO_NR_PALMTE2_LCD_POWER, GPIOF_INIT_LOW, "LCD power" },
142};
143
139static int palmte2_backlight_init(struct device *dev) 144static int palmte2_backlight_init(struct device *dev)
140{ 145{
141 int ret; 146 return gpio_request_array(ARRAY_AND_SIZE(palmte_bl_gpios));
142
143 ret = gpio_request(GPIO_NR_PALMTE2_BL_POWER, "BL POWER");
144 if (ret)
145 goto err;
146 ret = gpio_direction_output(GPIO_NR_PALMTE2_BL_POWER, 0);
147 if (ret)
148 goto err2;
149 ret = gpio_request(GPIO_NR_PALMTE2_LCD_POWER, "LCD POWER");
150 if (ret)
151 goto err2;
152 ret = gpio_direction_output(GPIO_NR_PALMTE2_LCD_POWER, 0);
153 if (ret)
154 goto err3;
155
156 return 0;
157err3:
158 gpio_free(GPIO_NR_PALMTE2_LCD_POWER);
159err2:
160 gpio_free(GPIO_NR_PALMTE2_BL_POWER);
161err:
162 return ret;
163} 147}
164 148
165static int palmte2_backlight_notify(struct device *dev, int brightness) 149static int palmte2_backlight_notify(struct device *dev, int brightness)
@@ -171,8 +155,7 @@ static int palmte2_backlight_notify(struct device *dev, int brightness)
171 155
172static void palmte2_backlight_exit(struct device *dev) 156static void palmte2_backlight_exit(struct device *dev)
173{ 157{
174 gpio_free(GPIO_NR_PALMTE2_BL_POWER); 158 gpio_free_array(ARRAY_AND_SIZE(palmte_bl_gpios));
175 gpio_free(GPIO_NR_PALMTE2_LCD_POWER);
176} 159}
177 160
178static struct platform_pwm_backlight_data palmte2_backlight_data = { 161static struct platform_pwm_backlight_data palmte2_backlight_data = {
@@ -363,7 +346,7 @@ static void __init palmte2_init(void)
363 pxa_set_btuart_info(NULL); 346 pxa_set_btuart_info(NULL);
364 pxa_set_stuart_info(NULL); 347 pxa_set_stuart_info(NULL);
365 348
366 set_pxa_fb_info(&palmte2_lcd_screen); 349 pxa_set_fb_info(NULL, &palmte2_lcd_screen);
367 pxa_set_mci_info(&palmte2_mci_platform_data); 350 pxa_set_mci_info(&palmte2_mci_platform_data);
368 palmte2_udc_init(); 351 palmte2_udc_init();
369 pxa_set_ac97_info(&palmte2_ac97_pdata); 352 pxa_set_ac97_info(&palmte2_ac97_pdata);
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 3010193b081e..3b8a4f37dbbe 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -30,6 +30,7 @@
30#include <linux/wm97xx.h> 30#include <linux/wm97xx.h>
31#include <linux/power_supply.h> 31#include <linux/power_supply.h>
32#include <linux/usb/gpio_vbus.h> 32#include <linux/usb/gpio_vbus.h>
33#include <linux/i2c-gpio.h>
33 34
34#include <asm/mach-types.h> 35#include <asm/mach-types.h>
35#include <asm/mach/arch.h> 36#include <asm/mach/arch.h>
@@ -47,6 +48,9 @@
47#include <mach/palm27x.h> 48#include <mach/palm27x.h>
48 49
49#include <mach/pm.h> 50#include <mach/pm.h>
51#include <mach/camera.h>
52
53#include <media/soc_camera.h>
50 54
51#include "generic.h" 55#include "generic.h"
52#include "devices.h" 56#include "devices.h"
@@ -103,6 +107,28 @@ static unsigned long palmz72_pin_config[] __initdata = {
103 GPIO22_GPIO, /* LCD border color */ 107 GPIO22_GPIO, /* LCD border color */
104 GPIO96_GPIO, /* lcd power */ 108 GPIO96_GPIO, /* lcd power */
105 109
110 /* PXA Camera */
111 GPIO81_CIF_DD_0,
112 GPIO48_CIF_DD_5,
113 GPIO50_CIF_DD_3,
114 GPIO51_CIF_DD_2,
115 GPIO52_CIF_DD_4,
116 GPIO53_CIF_MCLK,
117 GPIO54_CIF_PCLK,
118 GPIO55_CIF_DD_1,
119 GPIO84_CIF_FV,
120 GPIO85_CIF_LV,
121 GPIO93_CIF_DD_6,
122 GPIO108_CIF_DD_7,
123
124 GPIO56_GPIO, /* OV9640 Powerdown */
125 GPIO57_GPIO, /* OV9640 Reset */
126 GPIO91_GPIO, /* OV9640 Power */
127
128 /* I2C */
129 GPIO117_GPIO, /* I2C_SCL */
130 GPIO118_GPIO, /* I2C_SDA */
131
106 /* Misc. */ 132 /* Misc. */
107 GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* power detect */ 133 GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* power detect */
108 GPIO88_GPIO, /* green led */ 134 GPIO88_GPIO, /* green led */
@@ -254,6 +280,106 @@ device_initcall(palmz72_pm_init);
254#endif 280#endif
255 281
256/****************************************************************************** 282/******************************************************************************
283 * SoC Camera
284 ******************************************************************************/
285#if defined(CONFIG_SOC_CAMERA_OV9640) || \
286 defined(CONFIG_SOC_CAMERA_OV9640_MODULE)
287static struct pxacamera_platform_data palmz72_pxacamera_platform_data = {
288 .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
289 PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN,
290 .mclk_10khz = 2600,
291};
292
293/* Board I2C devices. */
294static struct i2c_board_info palmz72_i2c_device[] = {
295 {
296 I2C_BOARD_INFO("ov9640", 0x30),
297 }
298};
299
300static int palmz72_camera_power(struct device *dev, int power)
301{
302 gpio_set_value(GPIO_NR_PALMZ72_CAM_PWDN, !power);
303 mdelay(50);
304 return 0;
305}
306
307static int palmz72_camera_reset(struct device *dev)
308{
309 gpio_set_value(GPIO_NR_PALMZ72_CAM_RESET, 1);
310 mdelay(50);
311 gpio_set_value(GPIO_NR_PALMZ72_CAM_RESET, 0);
312 mdelay(50);
313 return 0;
314}
315
316static struct soc_camera_link palmz72_iclink = {
317 .bus_id = 0, /* Match id in pxa27x_device_camera in device.c */
318 .board_info = &palmz72_i2c_device[0],
319 .i2c_adapter_id = 0,
320 .module_name = "ov96xx",
321 .power = &palmz72_camera_power,
322 .reset = &palmz72_camera_reset,
323 .flags = SOCAM_DATAWIDTH_8,
324};
325
326static struct i2c_gpio_platform_data palmz72_i2c_bus_data = {
327 .sda_pin = 118,
328 .scl_pin = 117,
329 .udelay = 10,
330 .timeout = 100,
331};
332
333static struct platform_device palmz72_i2c_bus_device = {
334 .name = "i2c-gpio",
335 .id = 0, /* we use this as a replacement for i2c-pxa */
336 .dev = {
337 .platform_data = &palmz72_i2c_bus_data,
338 }
339};
340
341static struct platform_device palmz72_camera = {
342 .name = "soc-camera-pdrv",
343 .id = -1,
344 .dev = {
345 .platform_data = &palmz72_iclink,
346 },
347};
348
349/* Here we request the camera GPIOs and configure them. We power up the camera
350 * module, deassert the reset pin, but put it into powerdown (low to no power
351 * consumption) mode. This allows us to later bring the module up fast. */
352static struct gpio palmz72_camera_gpios[] = {
353 { GPIO_NR_PALMZ72_CAM_POWER, GPIOF_INIT_HIGH,"Camera DVDD" },
354 { GPIO_NR_PALMZ72_CAM_RESET, GPIOF_INIT_LOW, "Camera RESET" },
355 { GPIO_NR_PALMZ72_CAM_PWDN, GPIOF_INIT_LOW, "Camera PWDN" },
356};
357
358static inline void __init palmz72_cam_gpio_init(void)
359{
360 int ret;
361
362 ret = gpio_request_array(ARRAY_AND_SIZE(palmz72_camera_gpios));
363 if (!ret)
364 gpio_free_array(ARRAY_AND_SIZE(palmz72_camera_gpios));
365 else
366 printk(KERN_ERR "Camera GPIO init failed!\n");
367
368 return;
369}
370
371static void __init palmz72_camera_init(void)
372{
373 palmz72_cam_gpio_init();
374 pxa_set_camera_info(&palmz72_pxacamera_platform_data);
375 platform_device_register(&palmz72_i2c_bus_device);
376 platform_device_register(&palmz72_camera);
377}
378#else
379static inline void palmz72_camera_init(void) {}
380#endif
381
382/******************************************************************************
257 * Machine init 383 * Machine init
258 ******************************************************************************/ 384 ******************************************************************************/
259static void __init palmz72_init(void) 385static void __init palmz72_init(void)
@@ -276,6 +402,7 @@ static void __init palmz72_init(void)
276 palm27x_pmic_init(); 402 palm27x_pmic_init();
277 palmz72_kpc_init(); 403 palmz72_kpc_init();
278 palmz72_leds_init(); 404 palmz72_leds_init();
405 palmz72_camera_init();
279} 406}
280 407
281MACHINE_START(PALMZ72, "Palm Zire72") 408MACHINE_START(PALMZ72, "Palm Zire72")
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 9dbf3ccd4150..6d5b7e062124 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -281,16 +281,16 @@ static void __init pcm990_init_irq(void)
281 281
282 /* setup extra PCM990 irqs */ 282 /* setup extra PCM990 irqs */
283 for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) { 283 for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) {
284 set_irq_chip(irq, &pcm990_irq_chip); 284 irq_set_chip_and_handler(irq, &pcm990_irq_chip,
285 set_irq_handler(irq, handle_level_irq); 285 handle_level_irq);
286 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 286 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
287 } 287 }
288 288
289 PCM990_INTMSKENA = 0x00; /* disable all Interrupts */ 289 PCM990_INTMSKENA = 0x00; /* disable all Interrupts */
290 PCM990_INTSETCLR = 0xFF; 290 PCM990_INTSETCLR = 0xFF;
291 291
292 set_irq_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler); 292 irq_set_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
293 set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE); 293 irq_set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
294} 294}
295 295
296static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int, 296static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
@@ -515,7 +515,7 @@ void __init pcm990_baseboard_init(void)
515 pcm990_init_irq(); 515 pcm990_init_irq();
516 516
517#ifndef CONFIG_PCM990_DISPLAY_NONE 517#ifndef CONFIG_PCM990_DISPLAY_NONE
518 set_pxa_fb_info(&pcm990_fbinfo); 518 pxa_set_fb_info(NULL, &pcm990_fbinfo);
519#endif 519#endif
520 platform_device_register(&pcm990_backlight_device); 520 platform_device_register(&pcm990_backlight_device);
521 521
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 35353af345d5..16d14fd79b4b 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -445,8 +445,7 @@ static void __init poodle_init(void)
445 if (ret) 445 if (ret)
446 pr_warning("poodle: Unable to register LoCoMo device\n"); 446 pr_warning("poodle: Unable to register LoCoMo device\n");
447 447
448 set_pxa_fb_parent(&poodle_locomo_device.dev); 448 pxa_set_fb_info(&poodle_locomo_device.dev, &poodle_fb_info);
449 set_pxa_fb_info(&poodle_fb_info);
450 pxa_set_udc_info(&udc_info); 449 pxa_set_udc_info(&udc_info);
451 pxa_set_mci_info(&poodle_mci_platform_data); 450 pxa_set_mci_info(&poodle_mci_platform_data);
452 pxa_set_ficp_info(&poodle_ficp_platform_data); 451 pxa_set_ficp_info(&poodle_ficp_platform_data);
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index f374247b8466..8dd107391157 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -362,8 +362,8 @@ static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
362 int irq; 362 int irq;
363 363
364 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { 364 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
365 set_irq_chip(irq, &pxa_ext_wakeup_chip); 365 irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
366 set_irq_handler(irq, handle_edge_irq); 366 handle_edge_irq);
367 set_irq_flags(irq, IRQF_VALID); 367 set_irq_flags(irq, IRQF_VALID);
368 } 368 }
369 369
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index 47094188e029..cd1861351f75 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -597,7 +597,7 @@ static void __init raumfeld_lcd_init(void)
597{ 597{
598 int ret; 598 int ret;
599 599
600 set_pxa_fb_info(&raumfeld_sharp_lcd_info); 600 pxa_set_fb_info(NULL, &raumfeld_sharp_lcd_info);
601 601
602 /* Earlier devices had the backlight regulator controlled 602 /* Earlier devices had the backlight regulator controlled
603 * via PWM, later versions use another controller for that */ 603 * via PWM, later versions use another controller for that */
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index eb83c89428ef..fee97a935122 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -473,7 +473,7 @@ static struct pxafb_mach_info saar_lcd_info = {
473 473
474static void __init saar_init_lcd(void) 474static void __init saar_init_lcd(void)
475{ 475{
476 set_pxa_fb_info(&saar_lcd_info); 476 pxa_set_fb_info(NULL, &saar_lcd_info);
477} 477}
478#else 478#else
479static inline void saar_init_lcd(void) {} 479static inline void saar_init_lcd(void) {}
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 38e2c0912b9a..01c576963e94 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -724,7 +724,7 @@ static struct pxafb_mach_info spitz_pxafb_info = {
724 724
725static void __init spitz_lcd_init(void) 725static void __init spitz_lcd_init(void)
726{ 726{
727 set_pxa_fb_info(&spitz_pxafb_info); 727 pxa_set_fb_info(NULL, &spitz_pxafb_info);
728} 728}
729#else 729#else
730static inline void spitz_lcd_init(void) {} 730static inline void spitz_lcd_init(void) {}
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index 9cecf8366db8..53d4a472b699 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -466,7 +466,7 @@ static void __init tavorevb_init_lcd(void)
466{ 466{
467 platform_device_register(&tavorevb_backlight_devices[0]); 467 platform_device_register(&tavorevb_backlight_devices[0]);
468 platform_device_register(&tavorevb_backlight_devices[1]); 468 platform_device_register(&tavorevb_backlight_devices[1]);
469 set_pxa_fb_info(&tavorevb_lcd_info); 469 pxa_set_fb_info(NULL, &tavorevb_lcd_info);
470} 470}
471#else 471#else
472static inline void tavorevb_init_lcd(void) {} 472static inline void tavorevb_init_lcd(void) {}
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index e7f64d9b4f2d..428da3ff33a5 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -100,7 +100,6 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
100static struct clock_event_device ckevt_pxa_osmr0 = { 100static struct clock_event_device ckevt_pxa_osmr0 = {
101 .name = "osmr0", 101 .name = "osmr0",
102 .features = CLOCK_EVT_FEAT_ONESHOT, 102 .features = CLOCK_EVT_FEAT_ONESHOT,
103 .shift = 32,
104 .rating = 200, 103 .rating = 200,
105 .set_next_event = pxa_osmr0_set_next_event, 104 .set_next_event = pxa_osmr0_set_next_event,
106 .set_mode = pxa_osmr0_set_mode, 105 .set_mode = pxa_osmr0_set_mode,
@@ -135,8 +134,8 @@ static void __init pxa_timer_init(void)
135 134
136 init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate); 135 init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate);
137 136
138 ckevt_pxa_osmr0.mult = 137 clocksource_calc_mult_shift(&cksrc_pxa_oscr0, clock_tick_rate, 4);
139 div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); 138 clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4);
140 ckevt_pxa_osmr0.max_delta_ns = 139 ckevt_pxa_osmr0.max_delta_ns =
141 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); 140 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
142 ckevt_pxa_osmr0.min_delta_ns = 141 ckevt_pxa_osmr0.min_delta_ns =
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 5ad3807af334..5fa145778e7d 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -35,6 +35,7 @@
35#include <linux/spi/pxa2xx_spi.h> 35#include <linux/spi/pxa2xx_spi.h>
36#include <linux/input/matrix_keypad.h> 36#include <linux/input/matrix_keypad.h>
37#include <linux/i2c/pxa-i2c.h> 37#include <linux/i2c/pxa-i2c.h>
38#include <linux/usb/gpio_vbus.h>
38 39
39#include <asm/setup.h> 40#include <asm/setup.h>
40#include <asm/mach-types.h> 41#include <asm/mach-types.h>
@@ -240,12 +241,20 @@ static struct scoop_pcmcia_config tosa_pcmcia_config = {
240/* 241/*
241 * USB Device Controller 242 * USB Device Controller
242 */ 243 */
243static struct pxa2xx_udc_mach_info udc_info __initdata = { 244static struct gpio_vbus_mach_info tosa_udc_info = {
244 .gpio_pullup = TOSA_GPIO_USB_PULLUP, 245 .gpio_pullup = TOSA_GPIO_USB_PULLUP,
245 .gpio_vbus = TOSA_GPIO_USB_IN, 246 .gpio_vbus = TOSA_GPIO_USB_IN,
246 .gpio_vbus_inverted = 1, 247 .gpio_vbus_inverted = 1,
247}; 248};
248 249
250static struct platform_device tosa_gpio_vbus = {
251 .name = "gpio-vbus",
252 .id = -1,
253 .dev = {
254 .platform_data = &tosa_udc_info,
255 },
256};
257
249/* 258/*
250 * MMC/SD Device 259 * MMC/SD Device
251 */ 260 */
@@ -891,6 +900,7 @@ static struct platform_device *devices[] __initdata = {
891 &tosa_bt_device, 900 &tosa_bt_device,
892 &sharpsl_rom_device, 901 &sharpsl_rom_device,
893 &wm9712_device, 902 &wm9712_device,
903 &tosa_gpio_vbus,
894}; 904};
895 905
896static void tosa_poweroff(void) 906static void tosa_poweroff(void)
@@ -937,7 +947,6 @@ static void __init tosa_init(void)
937 dummy = gpiochip_reserve(TOSA_TC6393XB_GPIO_BASE, 16); 947 dummy = gpiochip_reserve(TOSA_TC6393XB_GPIO_BASE, 16);
938 948
939 pxa_set_mci_info(&tosa_mci_platform_data); 949 pxa_set_mci_info(&tosa_mci_platform_data);
940 pxa_set_udc_info(&udc_info);
941 pxa_set_ficp_info(&tosa_ficp_platform_data); 950 pxa_set_ficp_info(&tosa_ficp_platform_data);
942 pxa_set_i2c_info(NULL); 951 pxa_set_i2c_info(NULL);
943 pxa_set_ac97_info(NULL); 952 pxa_set_ac97_info(NULL);
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 857bb2e63486..b9cfbebdfe9c 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -516,9 +516,9 @@ static void __init trizeps4_init(void)
516 pxa_set_stuart_info(NULL); 516 pxa_set_stuart_info(NULL);
517 517
518 if (0) /* dont know how to determine LCD */ 518 if (0) /* dont know how to determine LCD */
519 set_pxa_fb_info(&sharp_lcd); 519 pxa_set_fb_info(NULL, &sharp_lcd);
520 else 520 else
521 set_pxa_fb_info(&toshiba_lcd); 521 pxa_set_fb_info(NULL, &toshiba_lcd);
522 522
523 pxa_set_mci_info(&trizeps4_mci_platform_data); 523 pxa_set_mci_info(&trizeps4_mci_platform_data);
524#ifndef STATUS_LEDS_ON_STUART_PINS 524#ifndef STATUS_LEDS_ON_STUART_PINS
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 12279214c875..b523f119e0f0 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -310,14 +310,14 @@ static void __init viper_init_irq(void)
310 /* setup ISA IRQs */ 310 /* setup ISA IRQs */
311 for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) { 311 for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) {
312 isa_irq = viper_bit_to_irq(level); 312 isa_irq = viper_bit_to_irq(level);
313 set_irq_chip(isa_irq, &viper_irq_chip); 313 irq_set_chip_and_handler(isa_irq, &viper_irq_chip,
314 set_irq_handler(isa_irq, handle_edge_irq); 314 handle_edge_irq);
315 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); 315 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
316 } 316 }
317 317
318 set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), 318 irq_set_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO),
319 viper_irq_handler); 319 viper_irq_handler);
320 set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH); 320 irq_set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH);
321} 321}
322 322
323/* Flat Panel */ 323/* Flat Panel */
@@ -932,7 +932,7 @@ static void __init viper_init(void)
932 /* Wake-up serial console */ 932 /* Wake-up serial console */
933 viper_init_serial_gpio(); 933 viper_init_serial_gpio();
934 934
935 set_pxa_fb_info(&fb_info); 935 pxa_set_fb_info(NULL, &fb_info);
936 936
937 /* v1 hardware cannot use the datacs line */ 937 /* v1 hardware cannot use the datacs line */
938 version = viper_hw_version(); 938 version = viper_hw_version();
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index e709fd459268..f71d377c8640 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -572,7 +572,7 @@ static void __init vpac270_lcd_init(void)
572 } 572 }
573 573
574 vpac270_lcd_screen.pxafb_lcd_power = vpac270_lcd_power; 574 vpac270_lcd_screen.pxafb_lcd_power = vpac270_lcd_power;
575 set_pxa_fb_info(&vpac270_lcd_screen); 575 pxa_set_fb_info(NULL, &vpac270_lcd_screen);
576 return; 576 return;
577 577
578err2: 578err2:
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index aaf883754ef4..fbe9e02e2f9f 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -91,13 +91,13 @@ static unsigned long z2_pin_config[] = {
91 GPIO47_STUART_TXD, 91 GPIO47_STUART_TXD,
92 92
93 /* Keypad */ 93 /* Keypad */
94 GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, 94 GPIO100_KP_MKIN_0,
95 GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, 95 GPIO101_KP_MKIN_1,
96 GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, 96 GPIO102_KP_MKIN_2,
97 GPIO34_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, 97 GPIO34_KP_MKIN_3,
98 GPIO38_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, 98 GPIO38_KP_MKIN_4,
99 GPIO16_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH, 99 GPIO16_KP_MKIN_5,
100 GPIO17_KP_MKIN_6 | WAKEUP_ON_LEVEL_HIGH, 100 GPIO17_KP_MKIN_6,
101 GPIO103_KP_MKOUT_0, 101 GPIO103_KP_MKOUT_0,
102 GPIO104_KP_MKOUT_1, 102 GPIO104_KP_MKOUT_1,
103 GPIO105_KP_MKOUT_2, 103 GPIO105_KP_MKOUT_2,
@@ -138,8 +138,7 @@ static unsigned long z2_pin_config[] = {
138 GPIO1_GPIO, /* Power button */ 138 GPIO1_GPIO, /* Power button */
139 GPIO37_GPIO, /* Headphone detect */ 139 GPIO37_GPIO, /* Headphone detect */
140 GPIO98_GPIO, /* Lid switch */ 140 GPIO98_GPIO, /* Lid switch */
141 GPIO14_GPIO, /* WiFi Reset */ 141 GPIO14_GPIO, /* WiFi Power */
142 GPIO15_GPIO, /* WiFi Power */
143 GPIO24_GPIO, /* WiFi CS */ 142 GPIO24_GPIO, /* WiFi CS */
144 GPIO36_GPIO, /* WiFi IRQ */ 143 GPIO36_GPIO, /* WiFi IRQ */
145 GPIO88_GPIO, /* LCD CS */ 144 GPIO88_GPIO, /* LCD CS */
@@ -204,7 +203,7 @@ static struct platform_pwm_backlight_data z2_backlight_data[] = {
204 /* Keypad Backlight */ 203 /* Keypad Backlight */
205 .pwm_id = 1, 204 .pwm_id = 1,
206 .max_brightness = 1023, 205 .max_brightness = 1023,
207 .dft_brightness = 512, 206 .dft_brightness = 0,
208 .pwm_period_ns = 1260320, 207 .pwm_period_ns = 1260320,
209 }, 208 },
210 [1] = { 209 [1] = {
@@ -271,7 +270,7 @@ static struct pxafb_mach_info z2_lcd_screen = {
271 270
272static void __init z2_lcd_init(void) 271static void __init z2_lcd_init(void)
273{ 272{
274 set_pxa_fb_info(&z2_lcd_screen); 273 pxa_set_fb_info(NULL, &z2_lcd_screen);
275} 274}
276#else 275#else
277static inline void z2_lcd_init(void) {} 276static inline void z2_lcd_init(void) {}
@@ -309,12 +308,12 @@ struct gpio_led z2_gpio_leds[] = {
309 .active_low = 1, 308 .active_low = 1,
310}, { 309}, {
311 .name = "z2:green:charged", 310 .name = "z2:green:charged",
312 .default_trigger = "none", 311 .default_trigger = "mmc0",
313 .gpio = GPIO85_ZIPITZ2_LED_CHARGED, 312 .gpio = GPIO85_ZIPITZ2_LED_CHARGED,
314 .active_low = 1, 313 .active_low = 1,
315}, { 314}, {
316 .name = "z2:amber:charging", 315 .name = "z2:amber:charging",
317 .default_trigger = "none", 316 .default_trigger = "Z2-charging-or-full",
318 .gpio = GPIO83_ZIPITZ2_LED_CHARGING, 317 .gpio = GPIO83_ZIPITZ2_LED_CHARGING,
319 .active_low = 1, 318 .active_low = 1,
320}, 319},
@@ -427,8 +426,22 @@ static inline void z2_mkp_init(void) {}
427 ******************************************************************************/ 426 ******************************************************************************/
428#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) 427#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
429static struct gpio_keys_button z2_pxa_buttons[] = { 428static struct gpio_keys_button z2_pxa_buttons[] = {
430 {KEY_POWER, GPIO1_ZIPITZ2_POWER_BUTTON, 0, "Power Button" }, 429 {
431 {KEY_CLOSE, GPIO98_ZIPITZ2_LID_BUTTON, 0, "Lid Button" }, 430 .code = KEY_POWER,
431 .gpio = GPIO1_ZIPITZ2_POWER_BUTTON,
432 .active_low = 0,
433 .desc = "Power Button",
434 .wakeup = 1,
435 .type = EV_KEY,
436 },
437 {
438 .code = SW_LID,
439 .gpio = GPIO98_ZIPITZ2_LID_BUTTON,
440 .active_low = 1,
441 .desc = "Lid Switch",
442 .wakeup = 0,
443 .type = EV_SW,
444 },
432}; 445};
433 446
434static struct gpio_keys_platform_data z2_pxa_keys_data = { 447static struct gpio_keys_platform_data z2_pxa_keys_data = {
@@ -461,9 +474,9 @@ static struct z2_battery_info batt_chip_info = {
461 .batt_I2C_addr = 0x55, 474 .batt_I2C_addr = 0x55,
462 .batt_I2C_reg = 2, 475 .batt_I2C_reg = 2,
463 .charge_gpio = GPIO0_ZIPITZ2_AC_DETECT, 476 .charge_gpio = GPIO0_ZIPITZ2_AC_DETECT,
464 .min_voltage = 2400000, 477 .min_voltage = 3475000,
465 .max_voltage = 3700000, 478 .max_voltage = 4190000,
466 .batt_div = 69, 479 .batt_div = 59,
467 .batt_mult = 1000000, 480 .batt_mult = 1000000,
468 .batt_tech = POWER_SUPPLY_TECHNOLOGY_LION, 481 .batt_tech = POWER_SUPPLY_TECHNOLOGY_LION,
469 .batt_name = "Z2", 482 .batt_name = "Z2",
@@ -497,26 +510,16 @@ static int z2_lbs_spi_setup(struct spi_device *spi)
497{ 510{
498 int ret = 0; 511 int ret = 0;
499 512
500 ret = gpio_request(GPIO15_ZIPITZ2_WIFI_POWER, "WiFi Power"); 513 ret = gpio_request(GPIO14_ZIPITZ2_WIFI_POWER, "WiFi Power");
501 if (ret) 514 if (ret)
502 goto err; 515 goto err;
503 516
504 ret = gpio_direction_output(GPIO15_ZIPITZ2_WIFI_POWER, 1); 517 ret = gpio_direction_output(GPIO14_ZIPITZ2_WIFI_POWER, 1);
505 if (ret) 518 if (ret)
506 goto err2; 519 goto err2;
507 520
508 ret = gpio_request(GPIO14_ZIPITZ2_WIFI_RESET, "WiFi Reset"); 521 /* Wait until card is powered on */
509 if (ret)
510 goto err2;
511
512 ret = gpio_direction_output(GPIO14_ZIPITZ2_WIFI_RESET, 0);
513 if (ret)
514 goto err3;
515
516 /* Reset the card */
517 mdelay(180); 522 mdelay(180);
518 gpio_set_value(GPIO14_ZIPITZ2_WIFI_RESET, 1);
519 mdelay(20);
520 523
521 spi->bits_per_word = 16; 524 spi->bits_per_word = 16;
522 spi->mode = SPI_MODE_2, 525 spi->mode = SPI_MODE_2,
@@ -525,22 +528,18 @@ static int z2_lbs_spi_setup(struct spi_device *spi)
525 528
526 return 0; 529 return 0;
527 530
528err3:
529 gpio_free(GPIO14_ZIPITZ2_WIFI_RESET);
530err2: 531err2:
531 gpio_free(GPIO15_ZIPITZ2_WIFI_POWER); 532 gpio_free(GPIO14_ZIPITZ2_WIFI_POWER);
532err: 533err:
533 return ret; 534 return ret;
534}; 535};
535 536
536static int z2_lbs_spi_teardown(struct spi_device *spi) 537static int z2_lbs_spi_teardown(struct spi_device *spi)
537{ 538{
538 gpio_set_value(GPIO14_ZIPITZ2_WIFI_RESET, 0); 539 gpio_set_value(GPIO14_ZIPITZ2_WIFI_POWER, 0);
539 gpio_set_value(GPIO15_ZIPITZ2_WIFI_POWER, 0); 540 gpio_free(GPIO14_ZIPITZ2_WIFI_POWER);
540 gpio_free(GPIO14_ZIPITZ2_WIFI_RESET);
541 gpio_free(GPIO15_ZIPITZ2_WIFI_POWER);
542 return 0;
543 541
542 return 0;
544}; 543};
545 544
546static struct pxa2xx_spi_chip z2_lbs_chip_info = { 545static struct pxa2xx_spi_chip z2_lbs_chip_info = {
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 730f51e57c17..00363c7ac182 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -136,22 +136,23 @@ static void __init zeus_init_irq(void)
136 136
137 /* Peripheral IRQs. It would be nice to move those inside driver 137 /* Peripheral IRQs. It would be nice to move those inside driver
138 configuration, but it is not supported at the moment. */ 138 configuration, but it is not supported at the moment. */
139 set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING); 139 irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
140 set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING); 140 irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
141 set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING); 141 irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
142 set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), IRQ_TYPE_EDGE_FALLING); 142 irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
143 set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING); 143 IRQ_TYPE_EDGE_FALLING);
144 irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
144 145
145 /* Setup ISA IRQs */ 146 /* Setup ISA IRQs */
146 for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) { 147 for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
147 isa_irq = zeus_bit_to_irq(level); 148 isa_irq = zeus_bit_to_irq(level);
148 set_irq_chip(isa_irq, &zeus_irq_chip); 149 irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
149 set_irq_handler(isa_irq, handle_edge_irq); 150 handle_edge_irq);
150 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); 151 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
151 } 152 }
152 153
153 set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); 154 irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
154 set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler); 155 irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
155} 156}
156 157
157 158
@@ -846,7 +847,7 @@ static void __init zeus_init(void)
846 if (zeus_setup_fb_gpios()) 847 if (zeus_setup_fb_gpios())
847 pr_err("Failed to setup fb gpios\n"); 848 pr_err("Failed to setup fb gpios\n");
848 else 849 else
849 set_pxa_fb_info(&zeus_fb_info); 850 pxa_set_fb_info(NULL, &zeus_fb_info);
850 851
851 pxa_set_mci_info(&zeus_mci_platform_data); 852 pxa_set_mci_info(&zeus_mci_platform_data);
852 pxa_set_udc_info(&zeus_udc_info); 853 pxa_set_udc_info(&zeus_udc_info);
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index a4c784aab764..5821185f77ab 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -208,7 +208,7 @@ static void __init zylonite_init_lcd(void)
208 platform_device_register(&zylonite_backlight_device); 208 platform_device_register(&zylonite_backlight_device);
209 209
210 if (lcd_id & 0x20) { 210 if (lcd_id & 0x20) {
211 set_pxa_fb_info(&zylonite_sharp_lcd_info); 211 pxa_set_fb_info(NULL, &zylonite_sharp_lcd_info);
212 return; 212 return;
213 } 213 }
214 214
@@ -220,7 +220,7 @@ static void __init zylonite_init_lcd(void)
220 else 220 else
221 zylonite_toshiba_lcd_info.modes = &toshiba_ltm04c380k_mode; 221 zylonite_toshiba_lcd_info.modes = &toshiba_ltm04c380k_mode;
222 222
223 set_pxa_fb_info(&zylonite_toshiba_lcd_info); 223 pxa_set_fb_info(NULL, &zylonite_toshiba_lcd_info);
224} 224}
225#else 225#else
226static inline void zylonite_init_lcd(void) {} 226static inline void zylonite_init_lcd(void) {}
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 2ecc1d94284e..10e75faba4c9 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -348,7 +348,7 @@ static void __init gic_init_irq(void)
348 348
349#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB 349#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
350 /* board GIC, secondary */ 350 /* board GIC, secondary */
351 gic_init(1, 64, __io_address(REALVIEW_EB_GIC_DIST_BASE), 351 gic_init(1, 96, __io_address(REALVIEW_EB_GIC_DIST_BASE),
352 __io_address(REALVIEW_EB_GIC_CPU_BASE)); 352 __io_address(REALVIEW_EB_GIC_CPU_BASE));
353 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); 353 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
354#endif 354#endif
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index d29cd9b737fc..2e1b5309fbab 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -133,25 +133,25 @@ void __init rpc_init_irq(void)
133 133
134 switch (irq) { 134 switch (irq) {
135 case 0 ... 7: 135 case 0 ... 7:
136 set_irq_chip(irq, &iomd_a_chip); 136 irq_set_chip_and_handler(irq, &iomd_a_chip,
137 set_irq_handler(irq, handle_level_irq); 137 handle_level_irq);
138 set_irq_flags(irq, flags); 138 set_irq_flags(irq, flags);
139 break; 139 break;
140 140
141 case 8 ... 15: 141 case 8 ... 15:
142 set_irq_chip(irq, &iomd_b_chip); 142 irq_set_chip_and_handler(irq, &iomd_b_chip,
143 set_irq_handler(irq, handle_level_irq); 143 handle_level_irq);
144 set_irq_flags(irq, flags); 144 set_irq_flags(irq, flags);
145 break; 145 break;
146 146
147 case 16 ... 21: 147 case 16 ... 21:
148 set_irq_chip(irq, &iomd_dma_chip); 148 irq_set_chip_and_handler(irq, &iomd_dma_chip,
149 set_irq_handler(irq, handle_level_irq); 149 handle_level_irq);
150 set_irq_flags(irq, flags); 150 set_irq_flags(irq, flags);
151 break; 151 break;
152 152
153 case 64 ... 71: 153 case 64 ... 71:
154 set_irq_chip(irq, &iomd_fiq_chip); 154 irq_set_chip(irq, &iomd_fiq_chip);
155 set_irq_flags(irq, IRQF_VALID); 155 set_irq_flags(irq, IRQF_VALID);
156 break; 156 break;
157 } 157 }
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 606cb6b1cc47..bc53d2d16d1a 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -147,15 +147,15 @@ static __init int bast_irq_init(void)
147 147
148 __raw_writeb(0x0, BAST_VA_PC104_IRQMASK); 148 __raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
149 149
150 set_irq_chained_handler(IRQ_ISA, bast_irq_pc104_demux); 150 irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux);
151 151
152 /* register our IRQs */ 152 /* register our IRQs */
153 153
154 for (i = 0; i < 4; i++) { 154 for (i = 0; i < 4; i++) {
155 unsigned int irqno = bast_pc104_irqs[i]; 155 unsigned int irqno = bast_pc104_irqs[i];
156 156
157 set_irq_chip(irqno, &bast_pc104_chip); 157 irq_set_chip_and_handler(irqno, &bast_pc104_chip,
158 set_irq_handler(irqno, handle_level_irq); 158 handle_level_irq);
159 set_irq_flags(irqno, IRQF_VALID); 159 set_irq_flags(irqno, IRQF_VALID);
160 } 160 }
161 } 161 }
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
index eddb52ba5b65..f3355d2ec634 100644
--- a/arch/arm/mach-s3c2412/irq.c
+++ b/arch/arm/mach-s3c2412/irq.c
@@ -175,18 +175,18 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
175 unsigned int irqno; 175 unsigned int irqno;
176 176
177 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { 177 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
178 set_irq_chip(irqno, &s3c2412_irq_eint0t4); 178 irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
179 set_irq_handler(irqno, handle_edge_irq); 179 handle_edge_irq);
180 set_irq_flags(irqno, IRQF_VALID); 180 set_irq_flags(irqno, IRQF_VALID);
181 } 181 }
182 182
183 /* add demux support for CF/SDI */ 183 /* add demux support for CF/SDI */
184 184
185 set_irq_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); 185 irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
186 186
187 for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) { 187 for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
188 set_irq_chip(irqno, &s3c2412_irq_cfsdi); 188 irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
189 set_irq_handler(irqno, handle_level_irq); 189 handle_level_irq);
190 set_irq_flags(irqno, IRQF_VALID); 190 set_irq_flags(irqno, IRQF_VALID);
191 } 191 }
192 192
@@ -195,7 +195,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
195 s3c2412_irq_rtc_chip = s3c_irq_chip; 195 s3c2412_irq_rtc_chip = s3c_irq_chip;
196 s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake; 196 s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
197 197
198 set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip); 198 irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
199 199
200 return 0; 200 return 0;
201} 201}
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c
index 680fe386aca5..77b38f2381c1 100644
--- a/arch/arm/mach-s3c2416/irq.c
+++ b/arch/arm/mach-s3c2416/irq.c
@@ -202,13 +202,11 @@ static int __init s3c2416_add_sub(unsigned int base,
202{ 202{
203 unsigned int irqno; 203 unsigned int irqno;
204 204
205 set_irq_chip(base, &s3c_irq_level_chip); 205 irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
206 set_irq_handler(base, handle_level_irq); 206 irq_set_chained_handler(base, demux);
207 set_irq_chained_handler(base, demux);
208 207
209 for (irqno = start; irqno <= end; irqno++) { 208 for (irqno = start; irqno <= end; irqno++) {
210 set_irq_chip(irqno, chip); 209 irq_set_chip_and_handler(irqno, chip, handle_level_irq);
211 set_irq_handler(irqno, handle_level_irq);
212 set_irq_flags(irqno, IRQF_VALID); 210 set_irq_flags(irqno, IRQF_VALID);
213 } 211 }
214 212
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
index acad4428bef0..eb1cc0f0705e 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -100,13 +100,13 @@ static int s3c2440_irq_add(struct sys_device *sysdev)
100 100
101 /* add new chained handler for wdt, ac7 */ 101 /* add new chained handler for wdt, ac7 */
102 102
103 set_irq_chip(IRQ_WDT, &s3c_irq_level_chip); 103 irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip,
104 set_irq_handler(IRQ_WDT, handle_level_irq); 104 handle_level_irq);
105 set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); 105 irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
106 106
107 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { 107 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
108 set_irq_chip(irqno, &s3c_irq_wdtac97); 108 irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97,
109 set_irq_handler(irqno, handle_level_irq); 109 handle_level_irq);
110 set_irq_flags(irqno, IRQF_VALID); 110 set_irq_flags(irqno, IRQF_VALID);
111 } 111 }
112 112
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c
index 83daf4ece764..de07c2feaa32 100644
--- a/arch/arm/mach-s3c2440/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2440/s3c244x-irq.c
@@ -95,19 +95,19 @@ static int s3c244x_irq_add(struct sys_device *sysdev)
95{ 95{
96 unsigned int irqno; 96 unsigned int irqno;
97 97
98 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip); 98 irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip,
99 set_irq_handler(IRQ_NFCON, handle_level_irq); 99 handle_level_irq);
100 set_irq_flags(IRQ_NFCON, IRQF_VALID); 100 set_irq_flags(IRQ_NFCON, IRQF_VALID);
101 101
102 /* add chained handler for camera */ 102 /* add chained handler for camera */
103 103
104 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip); 104 irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip,
105 set_irq_handler(IRQ_CAM, handle_level_irq); 105 handle_level_irq);
106 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam); 106 irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
107 107
108 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { 108 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
109 set_irq_chip(irqno, &s3c_irq_cam); 109 irq_set_chip_and_handler(irqno, &s3c_irq_cam,
110 set_irq_handler(irqno, handle_level_irq); 110 handle_level_irq);
111 set_irq_flags(irqno, IRQF_VALID); 111 set_irq_flags(irqno, IRQF_VALID);
112 } 112 }
113 113
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c
index c7820f9c1352..83ecb1173fb1 100644
--- a/arch/arm/mach-s3c2443/irq.c
+++ b/arch/arm/mach-s3c2443/irq.c
@@ -230,13 +230,11 @@ static int __init s3c2443_add_sub(unsigned int base,
230{ 230{
231 unsigned int irqno; 231 unsigned int irqno;
232 232
233 set_irq_chip(base, &s3c_irq_level_chip); 233 irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
234 set_irq_handler(base, handle_level_irq); 234 irq_set_chained_handler(base, demux);
235 set_irq_chained_handler(base, demux);
236 235
237 for (irqno = start; irqno <= end; irqno++) { 236 for (irqno = start; irqno <= end; irqno++) {
238 set_irq_chip(irqno, chip); 237 irq_set_chip_and_handler(irqno, chip, handle_level_irq);
239 set_irq_handler(irqno, handle_level_irq);
240 set_irq_flags(irqno, IRQF_VALID); 238 set_irq_flags(irqno, IRQF_VALID);
241 } 239 }
242 240
diff --git a/arch/arm/mach-s3c64xx/irq-eint.c b/arch/arm/mach-s3c64xx/irq-eint.c
index 2ead8189da74..4d203be1f4c3 100644
--- a/arch/arm/mach-s3c64xx/irq-eint.c
+++ b/arch/arm/mach-s3c64xx/irq-eint.c
@@ -197,16 +197,15 @@ static int __init s3c64xx_init_irq_eint(void)
197 int irq; 197 int irq;
198 198
199 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { 199 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
200 set_irq_chip(irq, &s3c_irq_eint); 200 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
201 set_irq_chip_data(irq, (void *)eint_irq_to_bit(irq)); 201 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
202 set_irq_handler(irq, handle_level_irq);
203 set_irq_flags(irq, IRQF_VALID); 202 set_irq_flags(irq, IRQF_VALID);
204 } 203 }
205 204
206 set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); 205 irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
207 set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); 206 irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
208 set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); 207 irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
209 set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); 208 irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
210 209
211 return 0; 210 return 0;
212} 211}
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index 98d780608c7e..7f3da4b11ec9 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -96,7 +96,7 @@ static struct resource cerf_flash_resource = {
96static void __init cerf_init_irq(void) 96static void __init cerf_init_irq(void)
97{ 97{
98 sa1100_init_irq(); 98 sa1100_init_irq();
99 set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING); 99 irq_set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING);
100} 100}
101 101
102static struct map_desc cerf_io_desc[] __initdata = { 102static struct map_desc cerf_io_desc[] __initdata = {
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 3d85dfad9c1f..423ddb3d65e9 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -323,28 +323,28 @@ void __init sa1100_init_irq(void)
323 ICCR = 1; 323 ICCR = 1;
324 324
325 for (irq = 0; irq <= 10; irq++) { 325 for (irq = 0; irq <= 10; irq++) {
326 set_irq_chip(irq, &sa1100_low_gpio_chip); 326 irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
327 set_irq_handler(irq, handle_edge_irq); 327 handle_edge_irq);
328 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 328 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
329 } 329 }
330 330
331 for (irq = 12; irq <= 31; irq++) { 331 for (irq = 12; irq <= 31; irq++) {
332 set_irq_chip(irq, &sa1100_normal_chip); 332 irq_set_chip_and_handler(irq, &sa1100_normal_chip,
333 set_irq_handler(irq, handle_level_irq); 333 handle_level_irq);
334 set_irq_flags(irq, IRQF_VALID); 334 set_irq_flags(irq, IRQF_VALID);
335 } 335 }
336 336
337 for (irq = 32; irq <= 48; irq++) { 337 for (irq = 32; irq <= 48; irq++) {
338 set_irq_chip(irq, &sa1100_high_gpio_chip); 338 irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
339 set_irq_handler(irq, handle_edge_irq); 339 handle_edge_irq);
340 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 340 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
341 } 341 }
342 342
343 /* 343 /*
344 * Install handler for GPIO 11-27 edge detect interrupts 344 * Install handler for GPIO 11-27 edge detect interrupts
345 */ 345 */
346 set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip); 346 irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
347 set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); 347 irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
348 348
349 sa1100_init_gpio(); 349 sa1100_init_gpio();
350} 350}
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index 4aad01f73660..b4fa53a1427e 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -145,8 +145,8 @@ static int __devinit neponset_probe(struct platform_device *dev)
145 /* 145 /*
146 * Install handler for GPIO25. 146 * Install handler for GPIO25.
147 */ 147 */
148 set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING); 148 irq_set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING);
149 set_irq_chained_handler(IRQ_GPIO25, neponset_irq_handler); 149 irq_set_chained_handler(IRQ_GPIO25, neponset_irq_handler);
150 150
151 /* 151 /*
152 * We would set IRQ_GPIO25 to be a wake-up IRQ, but 152 * We would set IRQ_GPIO25 to be a wake-up IRQ, but
@@ -161,9 +161,9 @@ static int __devinit neponset_probe(struct platform_device *dev)
161 * Setup other Neponset IRQs. SA1111 will be done by the 161 * Setup other Neponset IRQs. SA1111 will be done by the
162 * generic SA1111 code. 162 * generic SA1111 code.
163 */ 163 */
164 set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq); 164 irq_set_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq);
165 set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE); 165 set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE);
166 set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq); 166 irq_set_handler(IRQ_NEPONSET_USAR, handle_simple_irq);
167 set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE); 167 set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE);
168 168
169 /* 169 /*
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c
index 42b80400c100..65161f2bea29 100644
--- a/arch/arm/mach-sa1100/pleb.c
+++ b/arch/arm/mach-sa1100/pleb.c
@@ -142,7 +142,7 @@ static void __init pleb_map_io(void)
142 142
143 GPDR &= ~GPIO_ETH0_IRQ; 143 GPDR &= ~GPIO_ETH0_IRQ;
144 144
145 set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING); 145 irq_set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING);
146} 146}
147 147
148MACHINE_START(PLEB, "PLEB") 148MACHINE_START(PLEB, "PLEB")
diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c
index 831fc66dfa4d..5dce13e429f3 100644
--- a/arch/arm/mach-shark/irq.c
+++ b/arch/arm/mach-shark/irq.c
@@ -80,8 +80,7 @@ void __init shark_init_irq(void)
80 int irq; 80 int irq;
81 81
82 for (irq = 0; irq < NR_IRQS; irq++) { 82 for (irq = 0; irq < NR_IRQS; irq++) {
83 set_irq_chip(irq, &fb_chip); 83 irq_set_chip_and_handler(irq, &fb_chip, handle_edge_irq);
84 set_irq_handler(irq, handle_edge_irq);
85 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 84 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
86 } 85 }
87 86
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index a94f29da5d30..783b66fa95fb 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -24,9 +24,9 @@
24#include <linux/irq.h> 24#include <linux/irq.h>
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/delay.h> 26#include <linux/delay.h>
27#include <linux/mfd/sh_mobile_sdhi.h>
28#include <linux/mfd/tmio.h> 27#include <linux/mfd/tmio.h>
29#include <linux/mmc/host.h> 28#include <linux/mmc/host.h>
29#include <linux/mmc/sh_mobile_sdhi.h>
30#include <linux/mtd/mtd.h> 30#include <linux/mtd/mtd.h>
31#include <linux/mtd/partitions.h> 31#include <linux/mtd/partitions.h>
32#include <linux/mtd/physmap.h> 32#include <linux/mtd/physmap.h>
@@ -312,7 +312,7 @@ static struct resource sdhi0_resources[] = {
312 [0] = { 312 [0] = {
313 .name = "SDHI0", 313 .name = "SDHI0",
314 .start = 0xe6850000, 314 .start = 0xe6850000,
315 .end = 0xe68501ff, 315 .end = 0xe68500ff,
316 .flags = IORESOURCE_MEM, 316 .flags = IORESOURCE_MEM,
317 }, 317 },
318 [1] = { 318 [1] = {
@@ -345,7 +345,7 @@ static struct resource sdhi1_resources[] = {
345 [0] = { 345 [0] = {
346 .name = "SDHI1", 346 .name = "SDHI1",
347 .start = 0xe6860000, 347 .start = 0xe6860000,
348 .end = 0xe68601ff, 348 .end = 0xe68600ff,
349 .flags = IORESOURCE_MEM, 349 .flags = IORESOURCE_MEM,
350 }, 350 },
351 [1] = { 351 [1] = {
@@ -1255,7 +1255,7 @@ static void __init ap4evb_init(void)
1255 gpio_request(GPIO_FN_KEYIN4, NULL); 1255 gpio_request(GPIO_FN_KEYIN4, NULL);
1256 1256
1257 /* enable TouchScreen */ 1257 /* enable TouchScreen */
1258 set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); 1258 irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
1259 1259
1260 tsc_device.irq = IRQ28; 1260 tsc_device.irq = IRQ28;
1261 i2c_register_board_info(1, &tsc_device, 1); 1261 i2c_register_board_info(1, &tsc_device, 1);
@@ -1311,7 +1311,7 @@ static void __init ap4evb_init(void)
1311 lcdc_info.ch[0].lcd_size_cfg.height = 91; 1311 lcdc_info.ch[0].lcd_size_cfg.height = 91;
1312 1312
1313 /* enable TouchScreen */ 1313 /* enable TouchScreen */
1314 set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); 1314 irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
1315 1315
1316 tsc_device.irq = IRQ7; 1316 tsc_device.irq = IRQ7;
1317 i2c_register_board_info(0, &tsc_device, 1); 1317 i2c_register_board_info(0, &tsc_device, 1);
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index dee3e9231fb9..c87a7b7c5832 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -31,7 +31,7 @@
31#include <linux/input.h> 31#include <linux/input.h>
32#include <linux/input/sh_keysc.h> 32#include <linux/input/sh_keysc.h>
33#include <linux/mmc/host.h> 33#include <linux/mmc/host.h>
34#include <linux/mfd/sh_mobile_sdhi.h> 34#include <linux/mmc/sh_mobile_sdhi.h>
35#include <linux/gpio.h> 35#include <linux/gpio.h>
36#include <mach/sh7377.h> 36#include <mach/sh7377.h>
37#include <mach/common.h> 37#include <mach/common.h>
@@ -205,7 +205,7 @@ static struct resource sdhi0_resources[] = {
205 [0] = { 205 [0] = {
206 .name = "SDHI0", 206 .name = "SDHI0",
207 .start = 0xe6d50000, 207 .start = 0xe6d50000,
208 .end = 0xe6d501ff, 208 .end = 0xe6d50nff,
209 .flags = IORESOURCE_MEM, 209 .flags = IORESOURCE_MEM,
210 }, 210 },
211 [1] = { 211 [1] = {
@@ -232,7 +232,7 @@ static struct resource sdhi1_resources[] = {
232 [0] = { 232 [0] = {
233 .name = "SDHI1", 233 .name = "SDHI1",
234 .start = 0xe6d60000, 234 .start = 0xe6d60000,
235 .end = 0xe6d601ff, 235 .end = 0xe6d600ff,
236 .flags = IORESOURCE_MEM, 236 .flags = IORESOURCE_MEM,
237 }, 237 },
238 [1] = { 238 [1] = {
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 49bc07482179..8184d4d4f234 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -32,10 +32,10 @@
32#include <linux/io.h> 32#include <linux/io.h>
33#include <linux/i2c.h> 33#include <linux/i2c.h>
34#include <linux/leds.h> 34#include <linux/leds.h>
35#include <linux/mfd/sh_mobile_sdhi.h>
36#include <linux/mfd/tmio.h> 35#include <linux/mfd/tmio.h>
37#include <linux/mmc/host.h> 36#include <linux/mmc/host.h>
38#include <linux/mmc/sh_mmcif.h> 37#include <linux/mmc/sh_mmcif.h>
38#include <linux/mmc/sh_mobile_sdhi.h>
39#include <linux/mtd/mtd.h> 39#include <linux/mtd/mtd.h>
40#include <linux/mtd/partitions.h> 40#include <linux/mtd/partitions.h>
41#include <linux/mtd/physmap.h> 41#include <linux/mtd/physmap.h>
@@ -690,7 +690,7 @@ static struct resource sdhi0_resources[] = {
690 [0] = { 690 [0] = {
691 .name = "SDHI0", 691 .name = "SDHI0",
692 .start = 0xe6850000, 692 .start = 0xe6850000,
693 .end = 0xe68501ff, 693 .end = 0xe68500ff,
694 .flags = IORESOURCE_MEM, 694 .flags = IORESOURCE_MEM,
695 }, 695 },
696 [1] = { 696 [1] = {
@@ -725,7 +725,7 @@ static struct resource sdhi1_resources[] = {
725 [0] = { 725 [0] = {
726 .name = "SDHI1", 726 .name = "SDHI1",
727 .start = 0xe6860000, 727 .start = 0xe6860000,
728 .end = 0xe68601ff, 728 .end = 0xe68600ff,
729 .flags = IORESOURCE_MEM, 729 .flags = IORESOURCE_MEM,
730 }, 730 },
731 [1] = { 731 [1] = {
@@ -768,7 +768,7 @@ static struct resource sdhi2_resources[] = {
768 [0] = { 768 [0] = {
769 .name = "SDHI2", 769 .name = "SDHI2",
770 .start = 0xe6870000, 770 .start = 0xe6870000,
771 .end = 0xe68701ff, 771 .end = 0xe68700ff,
772 .flags = IORESOURCE_MEM, 772 .flags = IORESOURCE_MEM,
773 }, 773 },
774 [1] = { 774 [1] = {
@@ -1124,15 +1124,15 @@ static void __init mackerel_init(void)
1124 1124
1125 /* enable Keypad */ 1125 /* enable Keypad */
1126 gpio_request(GPIO_FN_IRQ9_42, NULL); 1126 gpio_request(GPIO_FN_IRQ9_42, NULL);
1127 set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); 1127 irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
1128 1128
1129 /* enable Touchscreen */ 1129 /* enable Touchscreen */
1130 gpio_request(GPIO_FN_IRQ7_40, NULL); 1130 gpio_request(GPIO_FN_IRQ7_40, NULL);
1131 set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); 1131 irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
1132 1132
1133 /* enable Accelerometer */ 1133 /* enable Accelerometer */
1134 gpio_request(GPIO_FN_IRQ21, NULL); 1134 gpio_request(GPIO_FN_IRQ21, NULL);
1135 set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); 1135 irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
1136 1136
1137 /* enable SDHI0 */ 1137 /* enable SDHI0 */
1138 gpio_request(GPIO_FN_SDHICD0, NULL); 1138 gpio_request(GPIO_FN_SDHICD0, NULL);
diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c
index 2fe9704d5ea1..cc442d198cdc 100644
--- a/arch/arm/mach-shmobile/intc-sh7367.c
+++ b/arch/arm/mach-shmobile/intc-sh7367.c
@@ -421,7 +421,7 @@ static struct intc_desc intcs_desc __initdata = {
421 421
422static void intcs_demux(unsigned int irq, struct irq_desc *desc) 422static void intcs_demux(unsigned int irq, struct irq_desc *desc)
423{ 423{
424 void __iomem *reg = (void *)get_irq_data(irq); 424 void __iomem *reg = (void *)irq_get_handler_data(irq);
425 unsigned int evtcodeas = ioread32(reg); 425 unsigned int evtcodeas = ioread32(reg);
426 426
427 generic_handle_irq(intcs_evt2irq(evtcodeas)); 427 generic_handle_irq(intcs_evt2irq(evtcodeas));
@@ -435,6 +435,6 @@ void __init sh7367_init_irq(void)
435 register_intc_controller(&intcs_desc); 435 register_intc_controller(&intcs_desc);
436 436
437 /* demux using INTEVTSA */ 437 /* demux using INTEVTSA */
438 set_irq_data(evt2irq(0xf80), (void *)intevtsa); 438 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
439 set_irq_chained_handler(evt2irq(0xf80), intcs_demux); 439 irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
440} 440}
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index ca5f9d17b39a..7a4960f9c1e3 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -601,7 +601,7 @@ static struct intc_desc intcs_desc __initdata = {
601 601
602static void intcs_demux(unsigned int irq, struct irq_desc *desc) 602static void intcs_demux(unsigned int irq, struct irq_desc *desc)
603{ 603{
604 void __iomem *reg = (void *)get_irq_data(irq); 604 void __iomem *reg = (void *)irq_get_handler_data(irq);
605 unsigned int evtcodeas = ioread32(reg); 605 unsigned int evtcodeas = ioread32(reg);
606 606
607 generic_handle_irq(intcs_evt2irq(evtcodeas)); 607 generic_handle_irq(intcs_evt2irq(evtcodeas));
@@ -615,6 +615,6 @@ void __init sh7372_init_irq(void)
615 register_intc_controller(&intcs_desc); 615 register_intc_controller(&intcs_desc);
616 616
617 /* demux using INTEVTSA */ 617 /* demux using INTEVTSA */
618 set_irq_data(evt2irq(0xf80), (void *)intevtsa); 618 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
619 set_irq_chained_handler(evt2irq(0xf80), intcs_demux); 619 irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
620} 620}
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c
index dd568382cc9f..fe45154ce660 100644
--- a/arch/arm/mach-shmobile/intc-sh7377.c
+++ b/arch/arm/mach-shmobile/intc-sh7377.c
@@ -626,7 +626,7 @@ static struct intc_desc intcs_desc __initdata = {
626 626
627static void intcs_demux(unsigned int irq, struct irq_desc *desc) 627static void intcs_demux(unsigned int irq, struct irq_desc *desc)
628{ 628{
629 void __iomem *reg = (void *)get_irq_data(irq); 629 void __iomem *reg = (void *)irq_get_handler_data(irq);
630 unsigned int evtcodeas = ioread32(reg); 630 unsigned int evtcodeas = ioread32(reg);
631 631
632 generic_handle_irq(intcs_evt2irq(evtcodeas)); 632 generic_handle_irq(intcs_evt2irq(evtcodeas));
@@ -641,6 +641,6 @@ void __init sh7377_init_irq(void)
641 register_intc_controller(&intcs_desc); 641 register_intc_controller(&intcs_desc);
642 642
643 /* demux using INTEVTSA */ 643 /* demux using INTEVTSA */
644 set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa); 644 irq_set_handler_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
645 set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux); 645 irq_set_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
646} 646}
diff --git a/arch/arm/mach-tcc8k/irq.c b/arch/arm/mach-tcc8k/irq.c
index aa9231f4fc6e..209fa5c65d4c 100644
--- a/arch/arm/mach-tcc8k/irq.c
+++ b/arch/arm/mach-tcc8k/irq.c
@@ -102,10 +102,10 @@ void __init tcc8k_init_irq(void)
102 102
103 for (irqno = 0; irqno < NR_IRQS; irqno++) { 103 for (irqno = 0; irqno < NR_IRQS; irqno++) {
104 if (irqno < 32) 104 if (irqno < 32)
105 set_irq_chip(irqno, &tcc8000_irq_chip0); 105 irq_set_chip(irqno, &tcc8000_irq_chip0);
106 else 106 else
107 set_irq_chip(irqno, &tcc8000_irq_chip1); 107 irq_set_chip(irqno, &tcc8000_irq_chip1);
108 set_irq_handler(irqno, handle_level_irq); 108 irq_set_handler(irqno, handle_level_irq);
109 set_irq_flags(irqno, IRQF_VALID); 109 set_irq_flags(irqno, IRQF_VALID);
110 } 110 }
111} 111}
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
index 12090a2cf3e0..76a3f654220f 100644
--- a/arch/arm/mach-tegra/gpio.c
+++ b/arch/arm/mach-tegra/gpio.c
@@ -208,9 +208,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
208 spin_unlock_irqrestore(&bank->lvl_lock[port], flags); 208 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
209 209
210 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 210 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
211 __set_irq_handler_unlocked(d->irq, handle_level_irq); 211 __irq_set_handler_locked(d->irq, handle_level_irq);
212 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 212 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
213 __set_irq_handler_unlocked(d->irq, handle_edge_irq); 213 __irq_set_handler_locked(d->irq, handle_edge_irq);
214 214
215 return 0; 215 return 0;
216} 216}
@@ -224,7 +224,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
224 224
225 desc->irq_data.chip->irq_ack(&desc->irq_data); 225 desc->irq_data.chip->irq_ack(&desc->irq_data);
226 226
227 bank = get_irq_data(irq); 227 bank = irq_get_handler_data(irq);
228 228
229 for (port = 0; port < 4; port++) { 229 for (port = 0; port < 4; port++) {
230 int gpio = tegra_gpio_compose(bank->bank, port, 0); 230 int gpio = tegra_gpio_compose(bank->bank, port, 0);
@@ -275,13 +275,6 @@ void tegra_gpio_resume(void)
275 } 275 }
276 276
277 local_irq_restore(flags); 277 local_irq_restore(flags);
278
279 for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
280 struct irq_desc *desc = irq_to_desc(i);
281 if (!desc || (desc->status & IRQ_WAKEUP))
282 continue;
283 enable_irq(i);
284 }
285} 278}
286 279
287void tegra_gpio_suspend(void) 280void tegra_gpio_suspend(void)
@@ -289,18 +282,6 @@ void tegra_gpio_suspend(void)
289 unsigned long flags; 282 unsigned long flags;
290 int b, p, i; 283 int b, p, i;
291 284
292 for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
293 struct irq_desc *desc = irq_to_desc(i);
294 if (!desc)
295 continue;
296 if (desc->status & IRQ_WAKEUP) {
297 int gpio = i - INT_GPIO_BASE;
298 pr_debug("gpio %d.%d is wakeup\n", gpio/8, gpio&7);
299 continue;
300 }
301 disable_irq(i);
302 }
303
304 local_irq_save(flags); 285 local_irq_save(flags);
305 for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) { 286 for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
306 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; 287 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
@@ -320,7 +301,7 @@ void tegra_gpio_suspend(void)
320static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) 301static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
321{ 302{
322 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 303 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
323 return set_irq_wake(bank->irq, enable); 304 return irq_set_irq_wake(bank->irq, enable);
324} 305}
325#endif 306#endif
326 307
@@ -359,18 +340,18 @@ static int __init tegra_gpio_init(void)
359 for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { 340 for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
360 bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))]; 341 bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))];
361 342
362 lockdep_set_class(&irq_desc[i].lock, &gpio_lock_class); 343 irq_set_lockdep_class(i, &gpio_lock_class);
363 set_irq_chip_data(i, bank); 344 irq_set_chip_data(i, bank);
364 set_irq_chip(i, &tegra_gpio_irq_chip); 345 irq_set_chip_and_handler(i, &tegra_gpio_irq_chip,
365 set_irq_handler(i, handle_simple_irq); 346 handle_simple_irq);
366 set_irq_flags(i, IRQF_VALID); 347 set_irq_flags(i, IRQF_VALID);
367 } 348 }
368 349
369 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) { 350 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
370 bank = &tegra_gpio_banks[i]; 351 bank = &tegra_gpio_banks[i];
371 352
372 set_irq_chained_handler(bank->irq, tegra_gpio_irq_handler); 353 irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
373 set_irq_data(bank->irq, bank); 354 irq_set_handler_data(bank->irq, bank);
374 355
375 for (j = 0; j < 4; j++) 356 for (j = 0; j < 4; j++)
376 spin_lock_init(&bank->lvl_lock[j]); 357 spin_lock_init(&bank->lvl_lock[j]);
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index dfbc219ea492..4330d8995b27 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -144,7 +144,7 @@ void __init tegra_init_irq(void)
144 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 144 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
145 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); 145 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
146 146
147 gic = get_irq_chip(29); 147 gic = irq_get_chip(29);
148 tegra_gic_unmask_irq = gic->irq_unmask; 148 tegra_gic_unmask_irq = gic->irq_unmask;
149 tegra_gic_mask_irq = gic->irq_mask; 149 tegra_gic_mask_irq = gic->irq_mask;
150 tegra_gic_ack_irq = gic->irq_ack; 150 tegra_gic_ack_irq = gic->irq_ack;
@@ -154,8 +154,7 @@ void __init tegra_init_irq(void)
154 154
155 for (i = 0; i < INT_MAIN_NR; i++) { 155 for (i = 0; i < INT_MAIN_NR; i++) {
156 irq = INT_PRI_BASE + i; 156 irq = INT_PRI_BASE + i;
157 set_irq_chip(irq, &tegra_irq); 157 irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq);
158 set_irq_handler(irq, handle_level_irq);
159 set_irq_flags(irq, IRQF_VALID); 158 set_irq_flags(irq, IRQF_VALID);
160 } 159 }
161} 160}
diff --git a/arch/arm/mach-ux500/modem-irq-db5500.c b/arch/arm/mach-ux500/modem-irq-db5500.c
index e1296a7447c8..6b86416c94c9 100644
--- a/arch/arm/mach-ux500/modem-irq-db5500.c
+++ b/arch/arm/mach-ux500/modem-irq-db5500.c
@@ -90,8 +90,7 @@ static irqreturn_t modem_cpu_irq_handler(int irq, void *data)
90 90
91static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip) 91static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip)
92{ 92{
93 set_irq_chip(irq, modem_irq_chip); 93 irq_set_chip_and_handler(irq, modem_irq_chip, handle_simple_irq);
94 set_irq_handler(irq, handle_simple_irq);
95 set_irq_flags(irq, IRQF_VALID); 94 set_irq_flags(irq, IRQF_VALID);
96 95
97 pr_debug("modem_irq: Created virtual IRQ %d\n", irq); 96 pr_debug("modem_irq: Created virtual IRQ %d\n", irq);
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c
index 5f4ddde4f02a..245140c0df10 100644
--- a/arch/arm/mach-vt8500/irq.c
+++ b/arch/arm/mach-vt8500/irq.c
@@ -97,15 +97,15 @@ static int vt8500_irq_set_type(unsigned int irq, unsigned int flow_type)
97 return -EINVAL; 97 return -EINVAL;
98 case IRQF_TRIGGER_HIGH: 98 case IRQF_TRIGGER_HIGH:
99 dctr |= VT8500_TRIGGER_HIGH; 99 dctr |= VT8500_TRIGGER_HIGH;
100 irq_desc[orig_irq].handle_irq = handle_level_irq; 100 __irq_set_handler_locked(orig_irq, handle_level_irq);
101 break; 101 break;
102 case IRQF_TRIGGER_FALLING: 102 case IRQF_TRIGGER_FALLING:
103 dctr |= VT8500_TRIGGER_FALLING; 103 dctr |= VT8500_TRIGGER_FALLING;
104 irq_desc[orig_irq].handle_irq = handle_edge_irq; 104 __irq_set_handler_locked(orig_irq, handle_edge_irq);
105 break; 105 break;
106 case IRQF_TRIGGER_RISING: 106 case IRQF_TRIGGER_RISING:
107 dctr |= VT8500_TRIGGER_RISING; 107 dctr |= VT8500_TRIGGER_RISING;
108 irq_desc[orig_irq].handle_irq = handle_edge_irq; 108 __irq_set_handler_locked(orig_irq, handle_edge_irq);
109 break; 109 break;
110 } 110 }
111 writeb(dctr, base + VT8500_IC_DCTR + irq); 111 writeb(dctr, base + VT8500_IC_DCTR + irq);
@@ -136,8 +136,8 @@ void __init vt8500_init_irq(void)
136 /* Disable all interrupts and route them to IRQ */ 136 /* Disable all interrupts and route them to IRQ */
137 writeb(0x00, ic_regbase + VT8500_IC_DCTR + i); 137 writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
138 138
139 set_irq_chip(i, &vt8500_irq_chip); 139 irq_set_chip_and_handler(i, &vt8500_irq_chip,
140 set_irq_handler(i, handle_level_irq); 140 handle_level_irq);
141 set_irq_flags(i, IRQF_VALID); 141 set_irq_flags(i, IRQF_VALID);
142 } 142 }
143 } else { 143 } else {
@@ -167,8 +167,8 @@ void __init wm8505_init_irq(void)
167 writeb(0x00, sic_regbase + VT8500_IC_DCTR 167 writeb(0x00, sic_regbase + VT8500_IC_DCTR
168 + i - 64); 168 + i - 64);
169 169
170 set_irq_chip(i, &vt8500_irq_chip); 170 irq_set_chip_and_handler(i, &vt8500_irq_chip,
171 set_irq_handler(i, handle_level_irq); 171 handle_level_irq);
172 set_irq_flags(i, IRQF_VALID); 172 set_irq_flags(i, IRQF_VALID);
173 } 173 }
174 } else { 174 } else {
diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c
index 9c350103dcda..7bf143c443f1 100644
--- a/arch/arm/mach-w90x900/irq.c
+++ b/arch/arm/mach-w90x900/irq.c
@@ -207,8 +207,8 @@ void __init nuc900_init_irq(void)
207 __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); 207 __raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
208 208
209 for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) { 209 for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) {
210 set_irq_chip(irqno, &nuc900_irq_chip); 210 irq_set_chip_and_handler(irqno, &nuc900_irq_chip,
211 set_irq_handler(irqno, handle_level_irq); 211 handle_level_irq);
212 set_irq_flags(irqno, IRQF_VALID); 212 set_irq_flags(irqno, IRQF_VALID);
213 } 213 }
214} 214}
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
index c856fa397606..f0ba0726306c 100644
--- a/arch/arm/plat-mxc/3ds_debugboard.c
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -100,14 +100,9 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
100 100
101 expio_irq = MXC_BOARD_IRQ_START; 101 expio_irq = MXC_BOARD_IRQ_START;
102 for (; int_valid != 0; int_valid >>= 1, expio_irq++) { 102 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
103 struct irq_desc *d;
104 if ((int_valid & 1) == 0) 103 if ((int_valid & 1) == 0)
105 continue; 104 continue;
106 d = irq_desc + expio_irq; 105 generic_handle_irq(expio_irq);
107 if (unlikely(!(d->handle_irq)))
108 pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
109 else
110 d->handle_irq(expio_irq, d);
111 } 106 }
112 107
113 desc->irq_data.chip->irq_ack(&desc->irq_data); 108 desc->irq_data.chip->irq_ack(&desc->irq_data);
@@ -186,12 +181,11 @@ int __init mxc_expio_init(u32 base, u32 p_irq)
186 __raw_writew(0x1F, brd_io + INTR_MASK_REG); 181 __raw_writew(0x1F, brd_io + INTR_MASK_REG);
187 for (i = MXC_EXP_IO_BASE; 182 for (i = MXC_EXP_IO_BASE;
188 i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { 183 i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
189 set_irq_chip(i, &expio_irq_chip); 184 irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
190 set_irq_handler(i, handle_level_irq);
191 set_irq_flags(i, IRQF_VALID); 185 set_irq_flags(i, IRQF_VALID);
192 } 186 }
193 set_irq_type(p_irq, IRQF_TRIGGER_LOW); 187 irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW);
194 set_irq_chained_handler(p_irq, mxc_expio_irq_handler); 188 irq_set_chained_handler(p_irq, mxc_expio_irq_handler);
195 189
196 /* Register Lan device on the debugboard */ 190 /* Register Lan device on the debugboard */
197 smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); 191 smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index deb284bc7c4b..09e2bd0fcdca 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -139,8 +139,8 @@ void __init mxc_init_irq(void __iomem *irqbase)
139 __raw_writel(0, avic_base + AVIC_INTTYPEH); 139 __raw_writel(0, avic_base + AVIC_INTTYPEH);
140 __raw_writel(0, avic_base + AVIC_INTTYPEL); 140 __raw_writel(0, avic_base + AVIC_INTTYPEL);
141 for (i = 0; i < MXC_INTERNAL_IRQS; i++) { 141 for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
142 set_irq_chip(i, &mxc_avic_chip.base); 142 irq_set_chip_and_handler(i, &mxc_avic_chip.base,
143 set_irq_handler(i, handle_level_irq); 143 handle_level_irq);
144 set_irq_flags(i, IRQF_VALID); 144 set_irq_flags(i, IRQF_VALID);
145 } 145 }
146 146
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c
index 6561c9df5f0d..ccc789e21daa 100644
--- a/arch/arm/plat-mxc/devices/platform-fec.c
+++ b/arch/arm/plat-mxc/devices/platform-fec.c
@@ -53,7 +53,7 @@ struct platform_device *__init imx_add_fec(
53 struct resource res[] = { 53 struct resource res[] = {
54 { 54 {
55 .start = data->iobase, 55 .start = data->iobase,
56 .end = data->iobase + SZ_4K, 56 .end = data->iobase + SZ_4K - 1,
57 .flags = IORESOURCE_MEM, 57 .flags = IORESOURCE_MEM,
58 }, { 58 }, {
59 .start = data->irq, 59 .start = data->irq,
diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c
index 10653cc8d1fa..805336fdc252 100644
--- a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c
+++ b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c
@@ -27,7 +27,7 @@ struct platform_device *__init imx_add_imxdi_rtc(
27 struct resource res[] = { 27 struct resource res[] = {
28 { 28 {
29 .start = data->iobase, 29 .start = data->iobase,
30 .end = data->iobase + SZ_16K, 30 .end = data->iobase + SZ_16K - 1,
31 .flags = IORESOURCE_MEM, 31 .flags = IORESOURCE_MEM,
32 }, { 32 }, {
33 .start = data->irq, 33 .start = data->irq,
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 57d59855f9ec..7a107246fd98 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
175static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) 175static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
176{ 176{
177 u32 irq_stat; 177 u32 irq_stat;
178 struct mxc_gpio_port *port = get_irq_data(irq); 178 struct mxc_gpio_port *port = irq_get_handler_data(irq);
179 179
180 irq_stat = __raw_readl(port->base + GPIO_ISR) & 180 irq_stat = __raw_readl(port->base + GPIO_ISR) &
181 __raw_readl(port->base + GPIO_IMR); 181 __raw_readl(port->base + GPIO_IMR);
@@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
188{ 188{
189 int i; 189 int i;
190 u32 irq_msk, irq_stat; 190 u32 irq_msk, irq_stat;
191 struct mxc_gpio_port *port = get_irq_data(irq); 191 struct mxc_gpio_port *port = irq_get_handler_data(irq);
192 192
193 /* walk through all interrupt status registers */ 193 /* walk through all interrupt status registers */
194 for (i = 0; i < gpio_table_size; i++) { 194 for (i = 0; i < gpio_table_size; i++) {
@@ -311,8 +311,8 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
311 __raw_writel(~0, port[i].base + GPIO_ISR); 311 __raw_writel(~0, port[i].base + GPIO_ISR);
312 for (j = port[i].virtual_irq_start; 312 for (j = port[i].virtual_irq_start;
313 j < port[i].virtual_irq_start + 32; j++) { 313 j < port[i].virtual_irq_start + 32; j++) {
314 set_irq_chip(j, &gpio_irq_chip); 314 irq_set_chip_and_handler(j, &gpio_irq_chip,
315 set_irq_handler(j, handle_level_irq); 315 handle_level_irq);
316 set_irq_flags(j, IRQF_VALID); 316 set_irq_flags(j, IRQF_VALID);
317 } 317 }
318 318
@@ -331,21 +331,23 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
331 331
332 if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) { 332 if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
333 /* setup one handler for each entry */ 333 /* setup one handler for each entry */
334 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); 334 irq_set_chained_handler(port[i].irq,
335 set_irq_data(port[i].irq, &port[i]); 335 mx3_gpio_irq_handler);
336 irq_set_handler_data(port[i].irq, &port[i]);
336 if (port[i].irq_high) { 337 if (port[i].irq_high) {
337 /* setup handler for GPIO 16 to 31 */ 338 /* setup handler for GPIO 16 to 31 */
338 set_irq_chained_handler(port[i].irq_high, 339 irq_set_chained_handler(port[i].irq_high,
339 mx3_gpio_irq_handler); 340 mx3_gpio_irq_handler);
340 set_irq_data(port[i].irq_high, &port[i]); 341 irq_set_handler_data(port[i].irq_high,
342 &port[i]);
341 } 343 }
342 } 344 }
343 } 345 }
344 346
345 if (cpu_is_mx2()) { 347 if (cpu_is_mx2()) {
346 /* setup one handler for all GPIO interrupts */ 348 /* setup one handler for all GPIO interrupts */
347 set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler); 349 irq_set_chained_handler(port[0].irq, mx2_gpio_irq_handler);
348 set_irq_data(port[0].irq, port); 350 irq_set_handler_data(port[0].irq, port);
349 } 351 }
350 352
351 return 0; 353 return 0;
diff --git a/arch/arm/plat-mxc/include/mach/audmux.h b/arch/arm/plat-mxc/include/mach/audmux.h
index 5cd6466964af..6fda788ed0e9 100644
--- a/arch/arm/plat-mxc/include/mach/audmux.h
+++ b/arch/arm/plat-mxc/include/mach/audmux.h
@@ -15,6 +15,14 @@
15#define MX31_AUDMUX_PORT5_SSI_PINS_5 4 15#define MX31_AUDMUX_PORT5_SSI_PINS_5 4
16#define MX31_AUDMUX_PORT6_SSI_PINS_6 5 16#define MX31_AUDMUX_PORT6_SSI_PINS_6 5
17 17
18#define MX51_AUDMUX_PORT1_SSI0 0
19#define MX51_AUDMUX_PORT2_SSI1 1
20#define MX51_AUDMUX_PORT3 2
21#define MX51_AUDMUX_PORT4 3
22#define MX51_AUDMUX_PORT5 4
23#define MX51_AUDMUX_PORT6 5
24#define MX51_AUDMUX_PORT7 6
25
18/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */ 26/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */
19#define MXC_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff) 27#define MXC_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff)
20#define MXC_AUDMUX_V1_PCR_INMEN (1 << 8) 28#define MXC_AUDMUX_V1_PCR_INMEN (1 << 8)
@@ -28,7 +36,7 @@
28#define MXC_AUDMUX_V1_PCR_TCLKDIR (1 << 30) 36#define MXC_AUDMUX_V1_PCR_TCLKDIR (1 << 30)
29#define MXC_AUDMUX_V1_PCR_TFSDIR (1 << 31) 37#define MXC_AUDMUX_V1_PCR_TFSDIR (1 << 31)
30 38
31/* Register definitions for the i.MX25/31/35 Digital Audio Multiplexer */ 39/* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */
32#define MXC_AUDMUX_V2_PTCR_TFSDIR (1 << 31) 40#define MXC_AUDMUX_V2_PTCR_TFSDIR (1 << 31)
33#define MXC_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27) 41#define MXC_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27)
34#define MXC_AUDMUX_V2_PTCR_TCLKDIR (1 << 26) 42#define MXC_AUDMUX_V2_PTCR_TCLKDIR (1 << 26)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
index c4f116d214f2..7a9b20abda09 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
@@ -90,12 +90,12 @@
90#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) 90#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31)
91#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) 91#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
92#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) 92#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
93#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19) 93#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
94#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20) 94#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
95#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21) 95#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
96#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22) 96#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
97#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23) 97#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 23)
98#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24) 98#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
99#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) 99#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
100#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) 100#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
101#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) 101#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h
index aaec2a6e7b3a..5f2da75a47f4 100644
--- a/arch/arm/plat-mxc/include/mach/mx50.h
+++ b/arch/arm/plat-mxc/include/mach/mx50.h
@@ -282,4 +282,8 @@
282#define MX50_INT_APBHDMA_CHAN6 116 282#define MX50_INT_APBHDMA_CHAN6 116
283#define MX50_INT_APBHDMA_CHAN7 117 283#define MX50_INT_APBHDMA_CHAN7 117
284 284
285#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
286extern int mx50_revision(void);
287#endif
288
285#endif /* ifndef __MACH_MX50_H__ */ 289#endif /* ifndef __MACH_MX50_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 1eb339e6c857..dede19a766ff 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -347,6 +347,7 @@
347 347
348#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 348#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
349extern int mx51_revision(void); 349extern int mx51_revision(void);
350extern void mx51_display_revision(void);
350#endif 351#endif
351 352
352/* tape-out 1 defines */ 353/* tape-out 1 defines */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 7e072637eefa..1aea818d9d31 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -51,6 +51,20 @@
51#define IMX_CHIP_REVISION_3_3 0x33 51#define IMX_CHIP_REVISION_3_3 0x33
52#define IMX_CHIP_REVISION_UNKNOWN 0xff 52#define IMX_CHIP_REVISION_UNKNOWN 0xff
53 53
54#define IMX_CHIP_REVISION_1_0_STRING "1.0"
55#define IMX_CHIP_REVISION_1_1_STRING "1.1"
56#define IMX_CHIP_REVISION_1_2_STRING "1.2"
57#define IMX_CHIP_REVISION_1_3_STRING "1.3"
58#define IMX_CHIP_REVISION_2_0_STRING "2.0"
59#define IMX_CHIP_REVISION_2_1_STRING "2.1"
60#define IMX_CHIP_REVISION_2_2_STRING "2.2"
61#define IMX_CHIP_REVISION_2_3_STRING "2.3"
62#define IMX_CHIP_REVISION_3_0_STRING "3.0"
63#define IMX_CHIP_REVISION_3_1_STRING "3.1"
64#define IMX_CHIP_REVISION_3_2_STRING "3.2"
65#define IMX_CHIP_REVISION_3_3_STRING "3.3"
66#define IMX_CHIP_REVISION_UNKNOWN_STRING "unknown"
67
54#ifndef __ASSEMBLY__ 68#ifndef __ASSEMBLY__
55extern unsigned int __mxc_cpu_type; 69extern unsigned int __mxc_cpu_type;
56#endif 70#endif
@@ -181,6 +195,15 @@ struct cpu_op {
181 u32 cpu_rate; 195 u32 cpu_rate;
182}; 196};
183 197
198int tzic_enable_wake(int is_idle);
199enum mxc_cpu_pwr_mode {
200 WAIT_CLOCKED, /* wfi only */
201 WAIT_UNCLOCKED, /* WAIT */
202 WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
203 STOP_POWER_ON, /* just STOP */
204 STOP_POWER_OFF, /* STOP + SRPG */
205};
206
184extern struct cpu_op *(*get_cpu_op)(int *op); 207extern struct cpu_op *(*get_cpu_op)(int *op);
185#endif 208#endif
186 209
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 95be51bfe9a9..0417da9f710d 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -20,6 +20,8 @@
20#include <mach/hardware.h> 20#include <mach/hardware.h>
21#include <mach/common.h> 21#include <mach/common.h>
22 22
23extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
24
23static inline void arch_idle(void) 25static inline void arch_idle(void)
24{ 26{
25#ifdef CONFIG_ARCH_MXC91231 27#ifdef CONFIG_ARCH_MXC91231
@@ -54,7 +56,9 @@ static inline void arch_idle(void)
54 "orr %0, %0, #0x00000004\n" 56 "orr %0, %0, #0x00000004\n"
55 "mcr p15, 0, %0, c1, c0, 0\n" 57 "mcr p15, 0, %0, c1, c0, 0\n"
56 : "=r" (reg)); 58 : "=r" (reg));
57 } else 59 } else if (cpu_is_mx51())
60 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
61 else
58 cpu_do_idle(); 62 cpu_do_idle();
59} 63}
60 64
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c
index 0c799ac27730..e1c6eff7258a 100644
--- a/arch/arm/plat-mxc/irq-common.c
+++ b/arch/arm/plat-mxc/irq-common.c
@@ -29,7 +29,7 @@ int imx_irq_set_priority(unsigned char irq, unsigned char prio)
29 29
30 ret = -ENOSYS; 30 ret = -ENOSYS;
31 31
32 base = get_irq_chip(irq); 32 base = irq_get_chip(irq);
33 if (base) { 33 if (base) {
34 chip = container_of(base, struct mxc_irq_chip, base); 34 chip = container_of(base, struct mxc_irq_chip, base);
35 if (chip->set_priority) 35 if (chip->set_priority)
@@ -48,7 +48,7 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
48 48
49 ret = -ENOSYS; 49 ret = -ENOSYS;
50 50
51 base = get_irq_chip(irq); 51 base = irq_get_chip(irq);
52 if (base) { 52 if (base) {
53 chip = container_of(base, struct mxc_irq_chip, base); 53 chip = container_of(base, struct mxc_irq_chip, base);
54 if (chip->set_irq_fiq) 54 if (chip->set_irq_fiq)
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 9f0c2610595e..2237ff8b434f 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -27,6 +27,7 @@
27#include <linux/clk.h> 27#include <linux/clk.h>
28 28
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30#include <asm/sched_clock.h>
30#include <asm/mach/time.h> 31#include <asm/mach/time.h>
31#include <mach/common.h> 32#include <mach/common.h>
32 33
@@ -105,6 +106,11 @@ static void gpt_irq_acknowledge(void)
105 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); 106 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
106} 107}
107 108
109static cycle_t dummy_get_cycles(struct clocksource *cs)
110{
111 return 0;
112}
113
108static cycle_t mx1_2_get_cycles(struct clocksource *cs) 114static cycle_t mx1_2_get_cycles(struct clocksource *cs)
109{ 115{
110 return __raw_readl(timer_base + MX1_2_TCN); 116 return __raw_readl(timer_base + MX1_2_TCN);
@@ -118,18 +124,35 @@ static cycle_t v2_get_cycles(struct clocksource *cs)
118static struct clocksource clocksource_mxc = { 124static struct clocksource clocksource_mxc = {
119 .name = "mxc_timer1", 125 .name = "mxc_timer1",
120 .rating = 200, 126 .rating = 200,
121 .read = mx1_2_get_cycles, 127 .read = dummy_get_cycles,
122 .mask = CLOCKSOURCE_MASK(32), 128 .mask = CLOCKSOURCE_MASK(32),
123 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 129 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
124}; 130};
125 131
132static DEFINE_CLOCK_DATA(cd);
133unsigned long long notrace sched_clock(void)
134{
135 cycle_t cyc = clocksource_mxc.read(&clocksource_mxc);
136
137 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
138}
139
140static void notrace mxc_update_sched_clock(void)
141{
142 cycle_t cyc = clocksource_mxc.read(&clocksource_mxc);
143 update_sched_clock(&cd, cyc, (u32)~0);
144}
145
126static int __init mxc_clocksource_init(struct clk *timer_clk) 146static int __init mxc_clocksource_init(struct clk *timer_clk)
127{ 147{
128 unsigned int c = clk_get_rate(timer_clk); 148 unsigned int c = clk_get_rate(timer_clk);
129 149
130 if (timer_is_v2()) 150 if (timer_is_v2())
131 clocksource_mxc.read = v2_get_cycles; 151 clocksource_mxc.read = v2_get_cycles;
152 else
153 clocksource_mxc.read = mx1_2_get_cycles;
132 154
155 init_sched_clock(&cd, mxc_update_sched_clock, 32, c);
133 clocksource_register_hz(&clocksource_mxc, c); 156 clocksource_register_hz(&clocksource_mxc, c);
134 157
135 return 0; 158 return 0;
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index bc3a6be8a27f..57f9395f87ce 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -167,8 +167,8 @@ void __init tzic_init_irq(void __iomem *irqbase)
167 /* all IRQ no FIQ Warning :: No selection */ 167 /* all IRQ no FIQ Warning :: No selection */
168 168
169 for (i = 0; i < MXC_INTERNAL_IRQS; i++) { 169 for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
170 set_irq_chip(i, &mxc_tzic_chip.base); 170 irq_set_chip_and_handler(i, &mxc_tzic_chip.base,
171 set_irq_handler(i, handle_level_irq); 171 handle_level_irq);
172 set_irq_flags(i, IRQF_VALID); 172 set_irq_flags(i, IRQF_VALID);
173 } 173 }
174 174
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 80643bc38e10..f49748eca1a3 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -54,6 +54,7 @@ struct nmk_gpio_chip {
54 u32 rwimsc; 54 u32 rwimsc;
55 u32 fwimsc; 55 u32 fwimsc;
56 u32 slpm; 56 u32 slpm;
57 u32 enabled;
57}; 58};
58 59
59static struct nmk_gpio_chip * 60static struct nmk_gpio_chip *
@@ -318,7 +319,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
318 struct nmk_gpio_chip *nmk_chip; 319 struct nmk_gpio_chip *nmk_chip;
319 int pin = PIN_NUM(cfgs[i]); 320 int pin = PIN_NUM(cfgs[i]);
320 321
321 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); 322 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
322 if (!nmk_chip) { 323 if (!nmk_chip) {
323 ret = -EINVAL; 324 ret = -EINVAL;
324 break; 325 break;
@@ -397,7 +398,7 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
397 struct nmk_gpio_chip *nmk_chip; 398 struct nmk_gpio_chip *nmk_chip;
398 unsigned long flags; 399 unsigned long flags;
399 400
400 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); 401 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
401 if (!nmk_chip) 402 if (!nmk_chip)
402 return -EINVAL; 403 return -EINVAL;
403 404
@@ -430,7 +431,7 @@ int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
430 struct nmk_gpio_chip *nmk_chip; 431 struct nmk_gpio_chip *nmk_chip;
431 unsigned long flags; 432 unsigned long flags;
432 433
433 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); 434 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
434 if (!nmk_chip) 435 if (!nmk_chip)
435 return -EINVAL; 436 return -EINVAL;
436 437
@@ -456,7 +457,7 @@ int nmk_gpio_set_mode(int gpio, int gpio_mode)
456 struct nmk_gpio_chip *nmk_chip; 457 struct nmk_gpio_chip *nmk_chip;
457 unsigned long flags; 458 unsigned long flags;
458 459
459 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); 460 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
460 if (!nmk_chip) 461 if (!nmk_chip)
461 return -EINVAL; 462 return -EINVAL;
462 463
@@ -473,7 +474,7 @@ int nmk_gpio_get_mode(int gpio)
473 struct nmk_gpio_chip *nmk_chip; 474 struct nmk_gpio_chip *nmk_chip;
474 u32 afunc, bfunc, bit; 475 u32 afunc, bfunc, bit;
475 476
476 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); 477 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
477 if (!nmk_chip) 478 if (!nmk_chip)
478 return -EINVAL; 479 return -EINVAL;
479 480
@@ -541,13 +542,6 @@ static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
541static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, 542static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
542 int gpio, bool on) 543 int gpio, bool on)
543{ 544{
544#ifdef CONFIG_ARCH_U8500
545 if (cpu_is_u8500v2()) {
546 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base,
547 on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
548 : NMK_GPIO_SLPM_WAKEUP_DISABLE);
549 }
550#endif
551 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); 545 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
552} 546}
553 547
@@ -564,6 +558,11 @@ static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
564 if (!nmk_chip) 558 if (!nmk_chip)
565 return -EINVAL; 559 return -EINVAL;
566 560
561 if (enable)
562 nmk_chip->enabled |= bitmask;
563 else
564 nmk_chip->enabled &= ~bitmask;
565
567 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 566 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
568 spin_lock(&nmk_chip->lock); 567 spin_lock(&nmk_chip->lock);
569 568
@@ -590,8 +589,6 @@ static void nmk_gpio_irq_unmask(struct irq_data *d)
590 589
591static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 590static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
592{ 591{
593 struct irq_desc *desc = irq_to_desc(d->irq);
594 bool enabled = !(desc->status & IRQ_DISABLED);
595 struct nmk_gpio_chip *nmk_chip; 592 struct nmk_gpio_chip *nmk_chip;
596 unsigned long flags; 593 unsigned long flags;
597 u32 bitmask; 594 u32 bitmask;
@@ -606,7 +603,7 @@ static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
606 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 603 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
607 spin_lock(&nmk_chip->lock); 604 spin_lock(&nmk_chip->lock);
608 605
609 if (!enabled) 606 if (!(nmk_chip->enabled & bitmask))
610 __nmk_gpio_set_wake(nmk_chip, gpio, on); 607 __nmk_gpio_set_wake(nmk_chip, gpio, on);
611 608
612 if (on) 609 if (on)
@@ -622,9 +619,7 @@ static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
622 619
623static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) 620static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
624{ 621{
625 struct irq_desc *desc = irq_to_desc(d->irq); 622 bool enabled, wake = irqd_is_wakeup_set(d);
626 bool enabled = !(desc->status & IRQ_DISABLED);
627 bool wake = desc->wake_depth;
628 int gpio; 623 int gpio;
629 struct nmk_gpio_chip *nmk_chip; 624 struct nmk_gpio_chip *nmk_chip;
630 unsigned long flags; 625 unsigned long flags;
@@ -641,6 +636,8 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
641 if (type & IRQ_TYPE_LEVEL_LOW) 636 if (type & IRQ_TYPE_LEVEL_LOW)
642 return -EINVAL; 637 return -EINVAL;
643 638
639 enabled = nmk_chip->enabled & bitmask;
640
644 spin_lock_irqsave(&nmk_chip->lock, flags); 641 spin_lock_irqsave(&nmk_chip->lock, flags);
645 642
646 if (enabled) 643 if (enabled)
@@ -681,7 +678,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
681 u32 status) 678 u32 status)
682{ 679{
683 struct nmk_gpio_chip *nmk_chip; 680 struct nmk_gpio_chip *nmk_chip;
684 struct irq_chip *host_chip = get_irq_chip(irq); 681 struct irq_chip *host_chip = irq_get_chip(irq);
685 unsigned int first_irq; 682 unsigned int first_irq;
686 683
687 if (host_chip->irq_mask_ack) 684 if (host_chip->irq_mask_ack)
@@ -692,7 +689,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
692 host_chip->irq_ack(&desc->irq_data); 689 host_chip->irq_ack(&desc->irq_data);
693 } 690 }
694 691
695 nmk_chip = get_irq_data(irq); 692 nmk_chip = irq_get_handler_data(irq);
696 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); 693 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
697 while (status) { 694 while (status) {
698 int bit = __ffs(status); 695 int bit = __ffs(status);
@@ -706,7 +703,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
706 703
707static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 704static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
708{ 705{
709 struct nmk_gpio_chip *nmk_chip = get_irq_data(irq); 706 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
710 u32 status = readl(nmk_chip->addr + NMK_GPIO_IS); 707 u32 status = readl(nmk_chip->addr + NMK_GPIO_IS);
711 708
712 __nmk_gpio_irq_handler(irq, desc, status); 709 __nmk_gpio_irq_handler(irq, desc, status);
@@ -715,7 +712,7 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
715static void nmk_gpio_secondary_irq_handler(unsigned int irq, 712static void nmk_gpio_secondary_irq_handler(unsigned int irq,
716 struct irq_desc *desc) 713 struct irq_desc *desc)
717{ 714{
718 struct nmk_gpio_chip *nmk_chip = get_irq_data(irq); 715 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
719 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); 716 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
720 717
721 __nmk_gpio_irq_handler(irq, desc, status); 718 __nmk_gpio_irq_handler(irq, desc, status);
@@ -728,20 +725,20 @@ static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
728 725
729 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); 726 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
730 for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { 727 for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
731 set_irq_chip(i, &nmk_gpio_irq_chip); 728 irq_set_chip_and_handler(i, &nmk_gpio_irq_chip,
732 set_irq_handler(i, handle_edge_irq); 729 handle_edge_irq);
733 set_irq_flags(i, IRQF_VALID); 730 set_irq_flags(i, IRQF_VALID);
734 set_irq_chip_data(i, nmk_chip); 731 irq_set_chip_data(i, nmk_chip);
735 set_irq_type(i, IRQ_TYPE_EDGE_FALLING); 732 irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
736 } 733 }
737 734
738 set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); 735 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
739 set_irq_data(nmk_chip->parent_irq, nmk_chip); 736 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
740 737
741 if (nmk_chip->secondary_parent_irq >= 0) { 738 if (nmk_chip->secondary_parent_irq >= 0) {
742 set_irq_chained_handler(nmk_chip->secondary_parent_irq, 739 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
743 nmk_gpio_secondary_irq_handler); 740 nmk_gpio_secondary_irq_handler);
744 set_irq_data(nmk_chip->secondary_parent_irq, nmk_chip); 741 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
745 } 742 }
746 743
747 return 0; 744 return 0;
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 971d18636942..d2adcdda23cf 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -755,18 +755,12 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
755 bank = irq_data_get_irq_chip_data(d); 755 bank = irq_data_get_irq_chip_data(d);
756 spin_lock_irqsave(&bank->lock, flags); 756 spin_lock_irqsave(&bank->lock, flags);
757 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); 757 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
758 if (retval == 0) {
759 struct irq_desc *desc = irq_to_desc(d->irq);
760
761 desc->status &= ~IRQ_TYPE_SENSE_MASK;
762 desc->status |= type;
763 }
764 spin_unlock_irqrestore(&bank->lock, flags); 758 spin_unlock_irqrestore(&bank->lock, flags);
765 759
766 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 760 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
767 __set_irq_handler_unlocked(d->irq, handle_level_irq); 761 __irq_set_handler_locked(d->irq, handle_level_irq);
768 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 762 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
769 __set_irq_handler_unlocked(d->irq, handle_edge_irq); 763 __irq_set_handler_locked(d->irq, handle_edge_irq);
770 764
771 return retval; 765 return retval;
772} 766}
@@ -1146,7 +1140,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1146 1140
1147 desc->irq_data.chip->irq_ack(&desc->irq_data); 1141 desc->irq_data.chip->irq_ack(&desc->irq_data);
1148 1142
1149 bank = get_irq_data(irq); 1143 bank = irq_get_handler_data(irq);
1150#ifdef CONFIG_ARCH_OMAP1 1144#ifdef CONFIG_ARCH_OMAP1
1151 if (bank->method == METHOD_MPUIO) 1145 if (bank->method == METHOD_MPUIO)
1152 isr_reg = bank->base + 1146 isr_reg = bank->base +
@@ -1270,8 +1264,7 @@ static void gpio_unmask_irq(struct irq_data *d)
1270 unsigned int gpio = d->irq - IH_GPIO_BASE; 1264 unsigned int gpio = d->irq - IH_GPIO_BASE;
1271 struct gpio_bank *bank = irq_data_get_irq_chip_data(d); 1265 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1272 unsigned int irq_mask = 1 << get_gpio_index(gpio); 1266 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1273 struct irq_desc *desc = irq_to_desc(d->irq); 1267 u32 trigger = irqd_get_trigger_type(d);
1274 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1275 1268
1276 if (trigger) 1269 if (trigger)
1277 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); 1270 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
@@ -1672,19 +1665,17 @@ static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1672 1665
1673 for (j = bank->virtual_irq_start; 1666 for (j = bank->virtual_irq_start;
1674 j < bank->virtual_irq_start + bank_width; j++) { 1667 j < bank->virtual_irq_start + bank_width; j++) {
1675 struct irq_desc *d = irq_to_desc(j); 1668 irq_set_lockdep_class(j, &gpio_lock_class);
1676 1669 irq_set_chip_data(j, bank);
1677 lockdep_set_class(&d->lock, &gpio_lock_class);
1678 set_irq_chip_data(j, bank);
1679 if (bank_is_mpuio(bank)) 1670 if (bank_is_mpuio(bank))
1680 set_irq_chip(j, &mpuio_irq_chip); 1671 irq_set_chip(j, &mpuio_irq_chip);
1681 else 1672 else
1682 set_irq_chip(j, &gpio_irq_chip); 1673 irq_set_chip(j, &gpio_irq_chip);
1683 set_irq_handler(j, handle_simple_irq); 1674 irq_set_handler(j, handle_simple_irq);
1684 set_irq_flags(j, IRQF_VALID); 1675 set_irq_flags(j, IRQF_VALID);
1685 } 1676 }
1686 set_irq_chained_handler(bank->irq, gpio_irq_handler); 1677 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1687 set_irq_data(bank->irq, bank); 1678 irq_set_handler_data(bank->irq, bank);
1688} 1679}
1689 1680
1690static int __devinit omap_gpio_probe(struct platform_device *pdev) 1681static int __devinit omap_gpio_probe(struct platform_device *pdev)
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 078894bc3b9a..a431a138f402 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -324,9 +324,8 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
324static void gpio_irq_ack(struct irq_data *d) 324static void gpio_irq_ack(struct irq_data *d)
325{ 325{
326 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); 326 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
327 int type; 327 int type = irqd_get_trigger_type(d);
328 328
329 type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
330 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { 329 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
331 int pin = d->irq - ochip->secondary_irq_base; 330 int pin = d->irq - ochip->secondary_irq_base;
332 331
@@ -337,11 +336,10 @@ static void gpio_irq_ack(struct irq_data *d)
337static void gpio_irq_mask(struct irq_data *d) 336static void gpio_irq_mask(struct irq_data *d)
338{ 337{
339 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); 338 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
340 int type; 339 int type = irqd_get_trigger_type(d);
341 void __iomem *reg; 340 void __iomem *reg;
342 int pin; 341 int pin;
343 342
344 type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
345 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) 343 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
346 reg = GPIO_EDGE_MASK(ochip); 344 reg = GPIO_EDGE_MASK(ochip);
347 else 345 else
@@ -355,11 +353,10 @@ static void gpio_irq_mask(struct irq_data *d)
355static void gpio_irq_unmask(struct irq_data *d) 353static void gpio_irq_unmask(struct irq_data *d)
356{ 354{
357 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); 355 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
358 int type; 356 int type = irqd_get_trigger_type(d);
359 void __iomem *reg; 357 void __iomem *reg;
360 int pin; 358 int pin;
361 359
362 type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
363 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) 360 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
364 reg = GPIO_EDGE_MASK(ochip); 361 reg = GPIO_EDGE_MASK(ochip);
365 else 362 else
@@ -389,9 +386,9 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
389 * Set edge/level type. 386 * Set edge/level type.
390 */ 387 */
391 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { 388 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
392 set_irq_handler(d->irq, handle_edge_irq); 389 __irq_set_handler_locked(d->irq, handle_edge_irq);
393 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 390 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
394 set_irq_handler(d->irq, handle_level_irq); 391 __irq_set_handler_locked(d->irq, handle_level_irq);
395 } else { 392 } else {
396 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", 393 printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
397 d->irq, type); 394 d->irq, type);
@@ -477,10 +474,10 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
477 for (i = 0; i < ngpio; i++) { 474 for (i = 0; i < ngpio; i++) {
478 unsigned int irq = secondary_irq_base + i; 475 unsigned int irq = secondary_irq_base + i;
479 476
480 set_irq_chip(irq, &orion_gpio_irq_chip); 477 irq_set_chip_and_handler(irq, &orion_gpio_irq_chip,
481 set_irq_handler(irq, handle_level_irq); 478 handle_level_irq);
482 set_irq_chip_data(irq, ochip); 479 irq_set_chip_data(irq, ochip);
483 irq_desc[irq].status |= IRQ_LEVEL; 480 irq_set_status_flags(irq, IRQ_LEVEL);
484 set_irq_flags(irq, IRQF_VALID); 481 set_irq_flags(irq, IRQF_VALID);
485 } 482 }
486} 483}
@@ -488,7 +485,7 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
488void orion_gpio_irq_handler(int pinoff) 485void orion_gpio_irq_handler(int pinoff)
489{ 486{
490 struct orion_gpio_chip *ochip; 487 struct orion_gpio_chip *ochip;
491 u32 cause; 488 u32 cause, type;
492 int i; 489 int i;
493 490
494 ochip = orion_gpio_chip_find(pinoff); 491 ochip = orion_gpio_chip_find(pinoff);
@@ -500,15 +497,14 @@ void orion_gpio_irq_handler(int pinoff)
500 497
501 for (i = 0; i < ochip->chip.ngpio; i++) { 498 for (i = 0; i < ochip->chip.ngpio; i++) {
502 int irq; 499 int irq;
503 struct irq_desc *desc;
504 500
505 irq = ochip->secondary_irq_base + i; 501 irq = ochip->secondary_irq_base + i;
506 502
507 if (!(cause & (1 << i))) 503 if (!(cause & (1 << i)))
508 continue; 504 continue;
509 505
510 desc = irq_desc + irq; 506 type = irqd_get_trigger_type(irq_get_irq_data(irq));
511 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 507 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
512 /* Swap polarity (race with GPIO line) */ 508 /* Swap polarity (race with GPIO line) */
513 u32 polarity; 509 u32 polarity;
514 510
@@ -516,7 +512,6 @@ void orion_gpio_irq_handler(int pinoff)
516 polarity ^= 1 << i; 512 polarity ^= 1 << i;
517 writel(polarity, GPIO_IN_POL(ochip)); 513 writel(polarity, GPIO_IN_POL(ochip));
518 } 514 }
519 515 generic_handle_irq(irq);
520 desc_handle_irq(irq, desc);
521 } 516 }
522} 517}
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index 7d0c7eb59f09..d8d638e09f8f 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -56,10 +56,10 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
56 for (i = 0; i < 32; i++) { 56 for (i = 0; i < 32; i++) {
57 unsigned int irq = irq_start + i; 57 unsigned int irq = irq_start + i;
58 58
59 set_irq_chip(irq, &orion_irq_chip); 59 irq_set_chip_and_handler(irq, &orion_irq_chip,
60 set_irq_chip_data(irq, maskaddr); 60 handle_level_irq);
61 set_irq_handler(irq, handle_level_irq); 61 irq_set_chip_data(irq, maskaddr);
62 irq_desc[irq].status |= IRQ_LEVEL; 62 irq_set_status_flags(irq, IRQ_LEVEL);
63 set_irq_flags(irq, IRQF_VALID); 63 set_irq_flags(irq, IRQF_VALID);
64 } 64 }
65} 65}
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c
index e7de6ae2a1e8..dce088f45678 100644
--- a/arch/arm/plat-pxa/gpio.c
+++ b/arch/arm/plat-pxa/gpio.c
@@ -284,13 +284,13 @@ void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
284 } 284 }
285 285
286 for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) { 286 for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
287 set_irq_chip(irq, &pxa_muxed_gpio_chip); 287 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
288 set_irq_handler(irq, handle_edge_irq); 288 handle_edge_irq);
289 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 289 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
290 } 290 }
291 291
292 /* Install handler for GPIO>=2 edge detect interrupts */ 292 /* Install handler for GPIO>=2 edge detect interrupts */
293 set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler); 293 irq_set_chained_handler(mux_irq, pxa_gpio_demux_handler);
294 pxa_muxed_gpio_chip.irq_set_wake = fn; 294 pxa_muxed_gpio_chip.irq_set_wake = fn;
295} 295}
296 296
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index 4434cb56bd9a..9aee7e1668b1 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -592,8 +592,8 @@ void __init s3c24xx_init_irq(void)
592 case IRQ_UART1: 592 case IRQ_UART1:
593 case IRQ_UART2: 593 case IRQ_UART2:
594 case IRQ_ADCPARENT: 594 case IRQ_ADCPARENT:
595 set_irq_chip(irqno, &s3c_irq_level_chip); 595 irq_set_chip_and_handler(irqno, &s3c_irq_level_chip,
596 set_irq_handler(irqno, handle_level_irq); 596 handle_level_irq);
597 break; 597 break;
598 598
599 case IRQ_RESERVED6: 599 case IRQ_RESERVED6:
@@ -603,35 +603,35 @@ void __init s3c24xx_init_irq(void)
603 603
604 default: 604 default:
605 //irqdbf("registering irq %d (s3c irq)\n", irqno); 605 //irqdbf("registering irq %d (s3c irq)\n", irqno);
606 set_irq_chip(irqno, &s3c_irq_chip); 606 irq_set_chip_and_handler(irqno, &s3c_irq_chip,
607 set_irq_handler(irqno, handle_edge_irq); 607 handle_edge_irq);
608 set_irq_flags(irqno, IRQF_VALID); 608 set_irq_flags(irqno, IRQF_VALID);
609 } 609 }
610 } 610 }
611 611
612 /* setup the cascade irq handlers */ 612 /* setup the cascade irq handlers */
613 613
614 set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7); 614 irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
615 set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8); 615 irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
616 616
617 set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0); 617 irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
618 set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1); 618 irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
619 set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2); 619 irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
620 set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc); 620 irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
621 621
622 /* external interrupts */ 622 /* external interrupts */
623 623
624 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { 624 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
625 irqdbf("registering irq %d (ext int)\n", irqno); 625 irqdbf("registering irq %d (ext int)\n", irqno);
626 set_irq_chip(irqno, &s3c_irq_eint0t4); 626 irq_set_chip_and_handler(irqno, &s3c_irq_eint0t4,
627 set_irq_handler(irqno, handle_edge_irq); 627 handle_edge_irq);
628 set_irq_flags(irqno, IRQF_VALID); 628 set_irq_flags(irqno, IRQF_VALID);
629 } 629 }
630 630
631 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { 631 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
632 irqdbf("registering irq %d (extended s3c irq)\n", irqno); 632 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
633 set_irq_chip(irqno, &s3c_irqext_chip); 633 irq_set_chip_and_handler(irqno, &s3c_irqext_chip,
634 set_irq_handler(irqno, handle_edge_irq); 634 handle_edge_irq);
635 set_irq_flags(irqno, IRQF_VALID); 635 set_irq_flags(irqno, IRQF_VALID);
636 } 636 }
637 637
@@ -641,29 +641,28 @@ void __init s3c24xx_init_irq(void)
641 641
642 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { 642 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
643 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); 643 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
644 set_irq_chip(irqno, &s3c_irq_uart0); 644 irq_set_chip_and_handler(irqno, &s3c_irq_uart0,
645 set_irq_handler(irqno, handle_level_irq); 645 handle_level_irq);
646 set_irq_flags(irqno, IRQF_VALID); 646 set_irq_flags(irqno, IRQF_VALID);
647 } 647 }
648 648
649 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { 649 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
650 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); 650 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
651 set_irq_chip(irqno, &s3c_irq_uart1); 651 irq_set_chip_and_handler(irqno, &s3c_irq_uart1,
652 set_irq_handler(irqno, handle_level_irq); 652 handle_level_irq);
653 set_irq_flags(irqno, IRQF_VALID); 653 set_irq_flags(irqno, IRQF_VALID);
654 } 654 }
655 655
656 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { 656 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
657 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); 657 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
658 set_irq_chip(irqno, &s3c_irq_uart2); 658 irq_set_chip_and_handler(irqno, &s3c_irq_uart2,
659 set_irq_handler(irqno, handle_level_irq); 659 handle_level_irq);
660 set_irq_flags(irqno, IRQF_VALID); 660 set_irq_flags(irqno, IRQF_VALID);
661 } 661 }
662 662
663 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { 663 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
664 irqdbf("registering irq %d (s3c adc irq)\n", irqno); 664 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
665 set_irq_chip(irqno, &s3c_irq_adc); 665 irq_set_chip_and_handler(irqno, &s3c_irq_adc, handle_edge_irq);
666 set_irq_handler(irqno, handle_edge_irq);
667 set_irq_flags(irqno, IRQF_VALID); 666 set_irq_flags(irqno, IRQF_VALID);
668 } 667 }
669 668
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c
index 225aa25405db..b5bb774985b0 100644
--- a/arch/arm/plat-s5p/irq-eint.c
+++ b/arch/arm/plat-s5p/irq-eint.c
@@ -205,15 +205,14 @@ int __init s5p_init_irq_eint(void)
205 int irq; 205 int irq;
206 206
207 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) 207 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
208 set_irq_chip(irq, &s5p_irq_vic_eint); 208 irq_set_chip(irq, &s5p_irq_vic_eint);
209 209
210 for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { 210 for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
211 set_irq_chip(irq, &s5p_irq_eint); 211 irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq);
212 set_irq_handler(irq, handle_level_irq);
213 set_irq_flags(irq, IRQF_VALID); 212 set_irq_flags(irq, IRQF_VALID);
214 } 213 }
215 214
216 set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31); 215 irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
217 return 0; 216 return 0;
218} 217}
219 218
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index cd87d3256e03..46dd078147d8 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -43,13 +43,13 @@ LIST_HEAD(banks);
43 43
44static int s5p_gpioint_get_offset(struct irq_data *data) 44static int s5p_gpioint_get_offset(struct irq_data *data)
45{ 45{
46 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); 46 struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
47 return data->irq - chip->irq_base; 47 return data->irq - chip->irq_base;
48} 48}
49 49
50static void s5p_gpioint_ack(struct irq_data *data) 50static void s5p_gpioint_ack(struct irq_data *data)
51{ 51{
52 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); 52 struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
53 int group, offset, pend_offset; 53 int group, offset, pend_offset;
54 unsigned int value; 54 unsigned int value;
55 55
@@ -64,7 +64,7 @@ static void s5p_gpioint_ack(struct irq_data *data)
64 64
65static void s5p_gpioint_mask(struct irq_data *data) 65static void s5p_gpioint_mask(struct irq_data *data)
66{ 66{
67 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); 67 struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
68 int group, offset, mask_offset; 68 int group, offset, mask_offset;
69 unsigned int value; 69 unsigned int value;
70 70
@@ -79,7 +79,7 @@ static void s5p_gpioint_mask(struct irq_data *data)
79 79
80static void s5p_gpioint_unmask(struct irq_data *data) 80static void s5p_gpioint_unmask(struct irq_data *data)
81{ 81{
82 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); 82 struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
83 int group, offset, mask_offset; 83 int group, offset, mask_offset;
84 unsigned int value; 84 unsigned int value;
85 85
@@ -100,7 +100,7 @@ static void s5p_gpioint_mask_ack(struct irq_data *data)
100 100
101static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type) 101static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
102{ 102{
103 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); 103 struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
104 int group, offset, con_offset; 104 int group, offset, con_offset;
105 unsigned int value; 105 unsigned int value;
106 106
@@ -149,7 +149,7 @@ static struct irq_chip s5p_gpioint = {
149 149
150static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) 150static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
151{ 151{
152 struct s5p_gpioint_bank *bank = get_irq_data(irq); 152 struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
153 int group, pend_offset, mask_offset; 153 int group, pend_offset, mask_offset;
154 unsigned int pend, mask; 154 unsigned int pend, mask;
155 155
@@ -200,8 +200,8 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
200 if (!bank->chips) 200 if (!bank->chips)
201 return -ENOMEM; 201 return -ENOMEM;
202 202
203 set_irq_chained_handler(bank->irq, s5p_gpioint_handler); 203 irq_set_chained_handler(bank->irq, s5p_gpioint_handler);
204 set_irq_data(bank->irq, bank); 204 irq_set_handler_data(bank->irq, bank);
205 bank->handler = s5p_gpioint_handler; 205 bank->handler = s5p_gpioint_handler;
206 printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n", 206 printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
207 bank->irq); 207 bank->irq);
@@ -219,9 +219,9 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
219 bank->chips[group - bank->start] = chip; 219 bank->chips[group - bank->start] = chip;
220 for (i = 0; i < chip->chip.ngpio; i++) { 220 for (i = 0; i < chip->chip.ngpio; i++) {
221 irq = chip->irq_base + i; 221 irq = chip->irq_base + i;
222 set_irq_chip(irq, &s5p_gpioint); 222 irq_set_chip(irq, &s5p_gpioint);
223 set_irq_data(irq, chip); 223 irq_set_handler_data(irq, chip);
224 set_irq_handler(irq, handle_level_irq); 224 irq_set_handler(irq, handle_level_irq);
225 set_irq_flags(irq, IRQF_VALID); 225 set_irq_flags(irq, IRQF_VALID);
226 } 226 }
227 return 0; 227 return 0;
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
index 4e770355ccbc..4d4e571af553 100644
--- a/arch/arm/plat-samsung/irq-uart.c
+++ b/arch/arm/plat-samsung/irq-uart.c
@@ -107,7 +107,6 @@ static struct irq_chip s3c_irq_uart = {
107 107
108static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) 108static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
109{ 109{
110 struct irq_desc *desc = irq_to_desc(uirq->parent_irq);
111 void __iomem *reg_base = uirq->regs; 110 void __iomem *reg_base = uirq->regs;
112 unsigned int irq; 111 unsigned int irq;
113 int offs; 112 int offs;
@@ -118,14 +117,13 @@ static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
118 for (offs = 0; offs < 3; offs++) { 117 for (offs = 0; offs < 3; offs++) {
119 irq = uirq->base_irq + offs; 118 irq = uirq->base_irq + offs;
120 119
121 set_irq_chip(irq, &s3c_irq_uart); 120 irq_set_chip_and_handler(irq, &s3c_irq_uart, handle_level_irq);
122 set_irq_chip_data(irq, uirq); 121 irq_set_chip_data(irq, uirq);
123 set_irq_handler(irq, handle_level_irq);
124 set_irq_flags(irq, IRQF_VALID); 122 set_irq_flags(irq, IRQF_VALID);
125 } 123 }
126 124
127 desc->irq_data.handler_data = uirq; 125 irq_set_handler_data(uirq->parent_irq, uirq);
128 set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); 126 irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
129} 127}
130 128
131/** 129/**
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index dd8692ae5c4c..d6ad66ab9290 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -77,14 +77,11 @@ static struct irq_chip s3c_irq_timer = {
77void __init s3c_init_vic_timer_irq(unsigned int parent_irq, 77void __init s3c_init_vic_timer_irq(unsigned int parent_irq,
78 unsigned int timer_irq) 78 unsigned int timer_irq)
79{ 79{
80 struct irq_desc *desc = irq_to_desc(parent_irq);
81 80
82 set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer); 81 irq_set_chained_handler(parent_irq, s3c_irq_demux_vic_timer);
82 irq_set_handler_data(parent_irq, (void *)timer_irq);
83 83
84 set_irq_chip(timer_irq, &s3c_irq_timer); 84 irq_set_chip_and_handler(timer_irq, &s3c_irq_timer, handle_level_irq);
85 set_irq_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0))); 85 irq_set_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0)));
86 set_irq_handler(timer_irq, handle_level_irq);
87 set_irq_flags(timer_irq, IRQF_VALID); 86 set_irq_flags(timer_irq, IRQF_VALID);
88
89 desc->irq_data.handler_data = (void *)timer_irq;
90} 87}
diff --git a/arch/arm/plat-samsung/wakeup-mask.c b/arch/arm/plat-samsung/wakeup-mask.c
index 2e09b6ad84ca..dc814037297b 100644
--- a/arch/arm/plat-samsung/wakeup-mask.c
+++ b/arch/arm/plat-samsung/wakeup-mask.c
@@ -22,7 +22,7 @@
22void samsung_sync_wakemask(void __iomem *reg, 22void samsung_sync_wakemask(void __iomem *reg,
23 struct samsung_wakeup_mask *mask, int nr_mask) 23 struct samsung_wakeup_mask *mask, int nr_mask)
24{ 24{
25 struct irq_desc *desc; 25 struct irq_data *data;
26 u32 val; 26 u32 val;
27 27
28 val = __raw_readl(reg); 28 val = __raw_readl(reg);
@@ -33,10 +33,10 @@ void samsung_sync_wakemask(void __iomem *reg,
33 continue; 33 continue;
34 } 34 }
35 35
36 desc = irq_to_desc(mask->irq); 36 data = irq_get_irq_data(mask->irq);
37 37
38 /* bit of a liberty to read this directly from irq_desc. */ 38 /* bit of a liberty to read this directly from irq_data. */
39 if (desc->wake_depth > 0) 39 if (irqd_is_wakeup_set(data))
40 val &= ~mask->bit; 40 val &= ~mask->bit;
41 else 41 else
42 val |= mask->bit; 42 val |= mask->bit;
diff --git a/arch/arm/plat-spear/shirq.c b/arch/arm/plat-spear/shirq.c
index 78189035e7f1..961fb7261243 100644
--- a/arch/arm/plat-spear/shirq.c
+++ b/arch/arm/plat-spear/shirq.c
@@ -68,7 +68,7 @@ static struct irq_chip shirq_chip = {
68static void shirq_handler(unsigned irq, struct irq_desc *desc) 68static void shirq_handler(unsigned irq, struct irq_desc *desc)
69{ 69{
70 u32 i, val, mask; 70 u32 i, val, mask;
71 struct spear_shirq *shirq = get_irq_data(irq); 71 struct spear_shirq *shirq = irq_get_handler_data(irq);
72 72
73 desc->irq_data.chip->irq_ack(&desc->irq_data); 73 desc->irq_data.chip->irq_ack(&desc->irq_data);
74 while ((val = readl(shirq->regs.base + shirq->regs.status_reg) & 74 while ((val = readl(shirq->regs.base + shirq->regs.status_reg) &
@@ -105,14 +105,14 @@ int spear_shirq_register(struct spear_shirq *shirq)
105 if (!shirq->dev_count) 105 if (!shirq->dev_count)
106 return -EINVAL; 106 return -EINVAL;
107 107
108 set_irq_chained_handler(shirq->irq, shirq_handler); 108 irq_set_chained_handler(shirq->irq, shirq_handler);
109 for (i = 0; i < shirq->dev_count; i++) { 109 for (i = 0; i < shirq->dev_count; i++) {
110 set_irq_chip(shirq->dev_config[i].virq, &shirq_chip); 110 irq_set_chip_and_handler(shirq->dev_config[i].virq,
111 set_irq_handler(shirq->dev_config[i].virq, handle_simple_irq); 111 &shirq_chip, handle_simple_irq);
112 set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID); 112 set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID);
113 set_irq_chip_data(shirq->dev_config[i].virq, shirq); 113 irq_set_chip_data(shirq->dev_config[i].virq, shirq);
114 } 114 }
115 115
116 set_irq_data(shirq->irq, shirq); 116 irq_set_handler_data(shirq->irq, shirq);
117 return 0; 117 return 0;
118} 118}
diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c
index aaa168683d4e..6fdf9acf82ed 100644
--- a/arch/arm/plat-stmp3xxx/irq.c
+++ b/arch/arm/plat-stmp3xxx/irq.c
@@ -35,8 +35,7 @@ void __init stmp3xxx_init_irq(struct irq_chip *chip)
35 /* Disable all interrupts initially */ 35 /* Disable all interrupts initially */
36 for (i = 0; i < NR_REAL_IRQS; i++) { 36 for (i = 0; i < NR_REAL_IRQS; i++) {
37 chip->irq_mask(irq_get_irq_data(i)); 37 chip->irq_mask(irq_get_irq_data(i));
38 set_irq_chip(i, chip); 38 irq_set_chip_and_handler(i, chip, handle_level_irq);
39 set_irq_handler(i, handle_level_irq);
40 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 39 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
41 } 40 }
42 41
diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c
index 66d5bac3ace2..3def03b3217d 100644
--- a/arch/arm/plat-stmp3xxx/pinmux.c
+++ b/arch/arm/plat-stmp3xxx/pinmux.c
@@ -489,14 +489,13 @@ static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset)
489 489
490static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc) 490static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc)
491{ 491{
492 struct stmp3xxx_pinmux_bank *pm = get_irq_data(irq); 492 struct stmp3xxx_pinmux_bank *pm = irq_get_handler_data(irq);
493 int gpio_irq = pm->virq; 493 int gpio_irq = pm->virq;
494 u32 stat = __raw_readl(pm->irqstat); 494 u32 stat = __raw_readl(pm->irqstat);
495 495
496 while (stat) { 496 while (stat) {
497 if (stat & 1) 497 if (stat & 1)
498 irq_desc[gpio_irq].handle_irq(gpio_irq, 498 generic_handle_irq(gpio_irq);
499 &irq_desc[gpio_irq]);
500 gpio_irq++; 499 gpio_irq++;
501 stat >>= 1; 500 stat >>= 1;
502 } 501 }
@@ -534,15 +533,15 @@ int __init stmp3xxx_pinmux_init(int virtual_irq_start)
534 533
535 for (virq = pm->virq; virq < pm->virq; virq++) { 534 for (virq = pm->virq; virq < pm->virq; virq++) {
536 gpio_irq_chip.irq_mask(irq_get_irq_data(virq)); 535 gpio_irq_chip.irq_mask(irq_get_irq_data(virq));
537 set_irq_chip(virq, &gpio_irq_chip); 536 irq_set_chip_and_handler(virq, &gpio_irq_chip,
538 set_irq_handler(virq, handle_level_irq); 537 handle_level_irq);
539 set_irq_flags(virq, IRQF_VALID); 538 set_irq_flags(virq, IRQF_VALID);
540 } 539 }
541 r = gpiochip_add(&pm->chip); 540 r = gpiochip_add(&pm->chip);
542 if (r < 0) 541 if (r < 0)
543 break; 542 break;
544 set_irq_chained_handler(pm->irq, stmp3xxx_gpio_irq); 543 irq_set_chained_handler(pm->irq, stmp3xxx_gpio_irq);
545 set_irq_data(pm->irq, pm); 544 irq_set_handler_data(pm->irq, pm);
546 } 545 }
547 return r; 546 return r;
548} 547}
diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c
index 31d945d37e4f..f0cc8e19b094 100644
--- a/arch/arm/plat-versatile/fpga-irq.c
+++ b/arch/arm/plat-versatile/fpga-irq.c
@@ -30,7 +30,7 @@ static void fpga_irq_unmask(struct irq_data *d)
30 30
31static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc) 31static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc)
32{ 32{
33 struct fpga_irq_data *f = get_irq_desc_data(desc); 33 struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
34 u32 status = readl(f->base + IRQ_STATUS); 34 u32 status = readl(f->base + IRQ_STATUS);
35 35
36 if (status == 0) { 36 if (status == 0) {
@@ -55,17 +55,17 @@ void __init fpga_irq_init(int parent_irq, u32 valid, struct fpga_irq_data *f)
55 f->chip.irq_unmask = fpga_irq_unmask; 55 f->chip.irq_unmask = fpga_irq_unmask;
56 56
57 if (parent_irq != -1) { 57 if (parent_irq != -1) {
58 set_irq_data(parent_irq, f); 58 irq_set_handler_data(parent_irq, f);
59 set_irq_chained_handler(parent_irq, fpga_irq_handle); 59 irq_set_chained_handler(parent_irq, fpga_irq_handle);
60 } 60 }
61 61
62 for (i = 0; i < 32; i++) { 62 for (i = 0; i < 32; i++) {
63 if (valid & (1 << i)) { 63 if (valid & (1 << i)) {
64 unsigned int irq = f->irq_start + i; 64 unsigned int irq = f->irq_start + i;
65 65
66 set_irq_chip_data(irq, f); 66 irq_set_chip_data(irq, f);
67 set_irq_chip(irq, &f->chip); 67 irq_set_chip_and_handler(irq, &f->chip,
68 set_irq_handler(irq, handle_level_irq); 68 handle_level_irq);
69 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 69 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
70 } 70 }
71 } 71 }