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-rw-r--r--arch/arm/mach-omap2/cm.h5
-rw-r--r--arch/arm/mach-omap2/pm24xx.c21
-rw-r--r--arch/arm/mach-omap2/pm34xx.c30
-rw-r--r--arch/arm/mach-omap2/powerdomain.c2
-rw-r--r--arch/arm/mach-omap2/prcm-common.h146
-rw-r--r--arch/arm/mach-omap2/prcm.c4
-rw-r--r--arch/arm/mach-omap2/prm.h18
7 files changed, 114 insertions, 112 deletions
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 94728b1ee3c4..b6ab183212df 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -134,10 +134,11 @@ static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
134 134
135/* CM_ICLKEN_GFX */ 135/* CM_ICLKEN_GFX */
136#define OMAP_EN_GFX_SHIFT 0 136#define OMAP_EN_GFX_SHIFT 0
137#define OMAP_EN_GFX (1 << 0) 137#define OMAP_EN_GFX_MASK (1 << 0)
138 138
139/* CM_IDLEST_GFX */ 139/* CM_IDLEST_GFX */
140#define OMAP_ST_GFX (1 << 0) 140#define OMAP_ST_GFX_MASK (1 << 0)
141
141 142
142/* CM_IDLEST indicator */ 143/* CM_IDLEST indicator */
143#define OMAP24XX_CM_IDLEST_VAL 0 144#define OMAP24XX_CM_IDLEST_VAL 0
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index b8c9e900a679..e321281ab6e1 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -70,8 +70,8 @@ static int omap2_fclks_active(void)
70 f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); 70 f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
71 71
72 /* Ignore UART clocks. These are handled by UART core (serial.c) */ 72 /* Ignore UART clocks. These are handled by UART core (serial.c) */
73 f1 &= ~(OMAP24XX_EN_UART1 | OMAP24XX_EN_UART2); 73 f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
74 f2 &= ~OMAP24XX_EN_UART3; 74 f2 &= ~OMAP24XX_EN_UART3_MASK;
75 75
76 if (f1 | f2) 76 if (f1 | f2)
77 return 1; 77 return 1;
@@ -181,13 +181,13 @@ static int omap2_allow_mpu_retention(void)
181 181
182 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ 182 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
183 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 183 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
184 if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 | 184 if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
185 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 | 185 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
186 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1_MASK)) 186 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
187 return 0; 187 return 0;
188 /* Check for UART3. */ 188 /* Check for UART3. */
189 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); 189 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
190 if (l & OMAP24XX_EN_UART3) 190 if (l & OMAP24XX_EN_UART3_MASK)
191 return 0; 191 return 0;
192 if (sti_console_enabled) 192 if (sti_console_enabled)
193 return 0; 193 return 0;
@@ -215,12 +215,12 @@ static void omap2_enter_mpu_retention(void)
215 215
216 /* Try to enter MPU retention */ 216 /* Try to enter MPU retention */
217 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | 217 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
218 OMAP_LOGICRETSTATE, 218 OMAP_LOGICRETSTATE_MASK,
219 MPU_MOD, OMAP2_PM_PWSTCTRL); 219 MPU_MOD, OMAP2_PM_PWSTCTRL);
220 } else { 220 } else {
221 /* Block MPU retention */ 221 /* Block MPU retention */
222 222
223 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, 223 prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
224 OMAP2_PM_PWSTCTRL); 224 OMAP2_PM_PWSTCTRL);
225 only_idle = 1; 225 only_idle = 1;
226 } 226 }
@@ -288,7 +288,8 @@ static int omap2_pm_suspend(void)
288 u32 wken_wkup, mir1; 288 u32 wken_wkup, mir1;
289 289
290 wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN); 290 wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
291 prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN); 291 wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
292 prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
292 293
293 /* Mask GPT1 */ 294 /* Mask GPT1 */
294 mir1 = omap_readl(0x480fe0a4); 295 mir1 = omap_readl(0x480fe0a4);
@@ -469,7 +470,7 @@ static void __init prcm_setup_regs(void)
469 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); 470 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
470 471
471 /* Enable wake-up events */ 472 /* Enable wake-up events */
472 prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1, 473 prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
473 WKUP_MOD, PM_WKEN); 474 WKUP_MOD, PM_WKEN);
474} 475}
475 476
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index dd09d80ea3eb..b2c299d9f428 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -867,7 +867,7 @@ static void __init prcm_setup_regs(void)
867 CM_AUTOIDLE); 867 CM_AUTOIDLE);
868 } 868 }
869 869
870 omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG); 870 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
871 871
872 /* 872 /*
873 * Set all plls to autoidle. This is needed until autoidle is 873 * Set all plls to autoidle. This is needed until autoidle is
@@ -897,12 +897,12 @@ static void __init prcm_setup_regs(void)
897 OMAP3_PRM_CLKSRC_CTRL_OFFSET); 897 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
898 898
899 /* setup wakup source */ 899 /* setup wakup source */
900 prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1 | 900 prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
901 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, 901 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
902 WKUP_MOD, PM_WKEN); 902 WKUP_MOD, PM_WKEN);
903 /* No need to write EN_IO, that is always enabled */ 903 /* No need to write EN_IO, that is always enabled */
904 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | 904 prm_write_mod_reg(OMAP3430_EN_GPIO1_MASK | OMAP3430_EN_GPT1_MASK |
905 OMAP3430_EN_GPT12, 905 OMAP3430_EN_GPT12_MASK,
906 WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 906 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
907 /* For some reason IO doesn't generate wakeup event even if 907 /* For some reason IO doesn't generate wakeup event even if
908 * it is selected to mpu wakeup goup */ 908 * it is selected to mpu wakeup goup */
@@ -914,18 +914,18 @@ static void __init prcm_setup_regs(void)
914 OMAP3430_DSS_MOD, PM_WKEN); 914 OMAP3430_DSS_MOD, PM_WKEN);
915 915
916 /* Enable wakeups in PER */ 916 /* Enable wakeups in PER */
917 prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | 917 prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
918 OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | 918 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
919 OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 | 919 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
920 OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | 920 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
921 OMAP3430_EN_MCBSP4, 921 OMAP3430_EN_MCBSP4_MASK,
922 OMAP3430_PER_MOD, PM_WKEN); 922 OMAP3430_PER_MOD, PM_WKEN);
923 /* and allow them to wake up MPU */ 923 /* and allow them to wake up MPU */
924 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK | OMAP3430_EN_GPIO3 | 924 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
925 OMAP3430_GRPSEL_GPIO4_MASK | OMAP3430_EN_GPIO5 | 925 OMAP3430_GRPSEL_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
926 OMAP3430_GRPSEL_GPIO6_MASK | OMAP3430_EN_UART3 | 926 OMAP3430_GRPSEL_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
927 OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | 927 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
928 OMAP3430_EN_MCBSP4, 928 OMAP3430_EN_MCBSP4_MASK,
929 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 929 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
930 930
931 /* Don't attach IVA interrupts */ 931 /* Don't attach IVA interrupts */
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 637fdfe7acd4..4a91d38d7b1a 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -1004,7 +1004,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
1004 1004
1005 /* XXX Is this udelay() value meaningful? */ 1005 /* XXX Is this udelay() value meaningful? */
1006 while ((prm_read_mod_reg(pwrdm->prcm_offs, pwrstst_reg_offs) & 1006 while ((prm_read_mod_reg(pwrdm->prcm_offs, pwrstst_reg_offs) &
1007 OMAP_INTRANSITION) && 1007 OMAP_INTRANSITION_MASK) &&
1008 (c++ < PWRDM_TRANSITION_BAILOUT)) 1008 (c++ < PWRDM_TRANSITION_BAILOUT))
1009 udelay(1); 1009 udelay(1);
1010 1010
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 90f603d434c6..ed2379f38db8 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -132,63 +132,63 @@
132 132
133/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 133/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
134#define OMAP2420_EN_MMC_SHIFT 26 134#define OMAP2420_EN_MMC_SHIFT 26
135#define OMAP2420_EN_MMC (1 << 26) 135#define OMAP2420_EN_MMC_MASK (1 << 26)
136#define OMAP24XX_EN_UART2_SHIFT 22 136#define OMAP24XX_EN_UART2_SHIFT 22
137#define OMAP24XX_EN_UART2 (1 << 22) 137#define OMAP24XX_EN_UART2_MASK (1 << 22)
138#define OMAP24XX_EN_UART1_SHIFT 21 138#define OMAP24XX_EN_UART1_SHIFT 21
139#define OMAP24XX_EN_UART1 (1 << 21) 139#define OMAP24XX_EN_UART1_MASK (1 << 21)
140#define OMAP24XX_EN_MCSPI2_SHIFT 18 140#define OMAP24XX_EN_MCSPI2_SHIFT 18
141#define OMAP24XX_EN_MCSPI2 (1 << 18) 141#define OMAP24XX_EN_MCSPI2_MASK (1 << 18)
142#define OMAP24XX_EN_MCSPI1_SHIFT 17 142#define OMAP24XX_EN_MCSPI1_SHIFT 17
143#define OMAP24XX_EN_MCSPI1 (1 << 17) 143#define OMAP24XX_EN_MCSPI1_MASK (1 << 17)
144#define OMAP24XX_EN_MCBSP2_SHIFT 16 144#define OMAP24XX_EN_MCBSP2_SHIFT 16
145#define OMAP24XX_EN_MCBSP2 (1 << 16) 145#define OMAP24XX_EN_MCBSP2_MASK (1 << 16)
146#define OMAP24XX_EN_MCBSP1_SHIFT 15 146#define OMAP24XX_EN_MCBSP1_SHIFT 15
147#define OMAP24XX_EN_MCBSP1 (1 << 15) 147#define OMAP24XX_EN_MCBSP1_MASK (1 << 15)
148#define OMAP24XX_EN_GPT12_SHIFT 14 148#define OMAP24XX_EN_GPT12_SHIFT 14
149#define OMAP24XX_EN_GPT12 (1 << 14) 149#define OMAP24XX_EN_GPT12_MASK (1 << 14)
150#define OMAP24XX_EN_GPT11_SHIFT 13 150#define OMAP24XX_EN_GPT11_SHIFT 13
151#define OMAP24XX_EN_GPT11 (1 << 13) 151#define OMAP24XX_EN_GPT11_MASK (1 << 13)
152#define OMAP24XX_EN_GPT10_SHIFT 12 152#define OMAP24XX_EN_GPT10_SHIFT 12
153#define OMAP24XX_EN_GPT10 (1 << 12) 153#define OMAP24XX_EN_GPT10_MASK (1 << 12)
154#define OMAP24XX_EN_GPT9_SHIFT 11 154#define OMAP24XX_EN_GPT9_SHIFT 11
155#define OMAP24XX_EN_GPT9 (1 << 11) 155#define OMAP24XX_EN_GPT9_MASK (1 << 11)
156#define OMAP24XX_EN_GPT8_SHIFT 10 156#define OMAP24XX_EN_GPT8_SHIFT 10
157#define OMAP24XX_EN_GPT8 (1 << 10) 157#define OMAP24XX_EN_GPT8_MASK (1 << 10)
158#define OMAP24XX_EN_GPT7_SHIFT 9 158#define OMAP24XX_EN_GPT7_SHIFT 9
159#define OMAP24XX_EN_GPT7 (1 << 9) 159#define OMAP24XX_EN_GPT7_MASK (1 << 9)
160#define OMAP24XX_EN_GPT6_SHIFT 8 160#define OMAP24XX_EN_GPT6_SHIFT 8
161#define OMAP24XX_EN_GPT6 (1 << 8) 161#define OMAP24XX_EN_GPT6_MASK (1 << 8)
162#define OMAP24XX_EN_GPT5_SHIFT 7 162#define OMAP24XX_EN_GPT5_SHIFT 7
163#define OMAP24XX_EN_GPT5 (1 << 7) 163#define OMAP24XX_EN_GPT5_MASK (1 << 7)
164#define OMAP24XX_EN_GPT4_SHIFT 6 164#define OMAP24XX_EN_GPT4_SHIFT 6
165#define OMAP24XX_EN_GPT4 (1 << 6) 165#define OMAP24XX_EN_GPT4_MASK (1 << 6)
166#define OMAP24XX_EN_GPT3_SHIFT 5 166#define OMAP24XX_EN_GPT3_SHIFT 5
167#define OMAP24XX_EN_GPT3 (1 << 5) 167#define OMAP24XX_EN_GPT3_MASK (1 << 5)
168#define OMAP24XX_EN_GPT2_SHIFT 4 168#define OMAP24XX_EN_GPT2_SHIFT 4
169#define OMAP24XX_EN_GPT2 (1 << 4) 169#define OMAP24XX_EN_GPT2_MASK (1 << 4)
170#define OMAP2420_EN_VLYNQ_SHIFT 3 170#define OMAP2420_EN_VLYNQ_SHIFT 3
171#define OMAP2420_EN_VLYNQ (1 << 3) 171#define OMAP2420_EN_VLYNQ_MASK (1 << 3)
172 172
173/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ 173/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
174#define OMAP2430_EN_GPIO5_SHIFT 10 174#define OMAP2430_EN_GPIO5_SHIFT 10
175#define OMAP2430_EN_GPIO5 (1 << 10) 175#define OMAP2430_EN_GPIO5_MASK (1 << 10)
176#define OMAP2430_EN_MCSPI3_SHIFT 9 176#define OMAP2430_EN_MCSPI3_SHIFT 9
177#define OMAP2430_EN_MCSPI3 (1 << 9) 177#define OMAP2430_EN_MCSPI3_MASK (1 << 9)
178#define OMAP2430_EN_MMCHS2_SHIFT 8 178#define OMAP2430_EN_MMCHS2_SHIFT 8
179#define OMAP2430_EN_MMCHS2 (1 << 8) 179#define OMAP2430_EN_MMCHS2_MASK (1 << 8)
180#define OMAP2430_EN_MMCHS1_SHIFT 7 180#define OMAP2430_EN_MMCHS1_SHIFT 7
181#define OMAP2430_EN_MMCHS1 (1 << 7) 181#define OMAP2430_EN_MMCHS1_MASK (1 << 7)
182#define OMAP24XX_EN_UART3_SHIFT 2 182#define OMAP24XX_EN_UART3_SHIFT 2
183#define OMAP24XX_EN_UART3 (1 << 2) 183#define OMAP24XX_EN_UART3_MASK (1 << 2)
184#define OMAP24XX_EN_USB_SHIFT 0 184#define OMAP24XX_EN_USB_SHIFT 0
185#define OMAP24XX_EN_USB (1 << 0) 185#define OMAP24XX_EN_USB_MASK (1 << 0)
186 186
187/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ 187/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
188#define OMAP2430_EN_MDM_INTC_SHIFT 11 188#define OMAP2430_EN_MDM_INTC_SHIFT 11
189#define OMAP2430_EN_MDM_INTC (1 << 11) 189#define OMAP2430_EN_MDM_INTC_MASK (1 << 11)
190#define OMAP2430_EN_USBHS_SHIFT 6 190#define OMAP2430_EN_USBHS_SHIFT 6
191#define OMAP2430_EN_USBHS (1 << 6) 191#define OMAP2430_EN_USBHS_MASK (1 << 6)
192 192
193/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ 193/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
194#define OMAP2420_ST_MMC_SHIFT 26 194#define OMAP2420_ST_MMC_SHIFT 26
@@ -246,9 +246,9 @@
246 246
247/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 247/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
248#define OMAP24XX_EN_GPIOS_SHIFT 2 248#define OMAP24XX_EN_GPIOS_SHIFT 2
249#define OMAP24XX_EN_GPIOS (1 << 2) 249#define OMAP24XX_EN_GPIOS_MASK (1 << 2)
250#define OMAP24XX_EN_GPT1_SHIFT 0 250#define OMAP24XX_EN_GPT1_SHIFT 0
251#define OMAP24XX_EN_GPT1 (1 << 0) 251#define OMAP24XX_EN_GPT1_MASK (1 << 0)
252 252
253/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ 253/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
254#define OMAP24XX_ST_GPIOS_SHIFT (1 << 2) 254#define OMAP24XX_ST_GPIOS_SHIFT (1 << 2)
@@ -267,47 +267,47 @@
267#define OMAP3430_REV_MASK (0xff << 0) 267#define OMAP3430_REV_MASK (0xff << 0)
268 268
269/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */ 269/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
270#define OMAP3430_AUTOIDLE (1 << 0) 270#define OMAP3430_AUTOIDLE_MASK (1 << 0)
271 271
272/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 272/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
273#define OMAP3430_EN_MMC2 (1 << 25) 273#define OMAP3430_EN_MMC2_MASK (1 << 25)
274#define OMAP3430_EN_MMC2_SHIFT 25 274#define OMAP3430_EN_MMC2_SHIFT 25
275#define OMAP3430_EN_MMC1 (1 << 24) 275#define OMAP3430_EN_MMC1_MASK (1 << 24)
276#define OMAP3430_EN_MMC1_SHIFT 24 276#define OMAP3430_EN_MMC1_SHIFT 24
277#define OMAP3430_EN_MCSPI4 (1 << 21) 277#define OMAP3430_EN_MCSPI4_MASK (1 << 21)
278#define OMAP3430_EN_MCSPI4_SHIFT 21 278#define OMAP3430_EN_MCSPI4_SHIFT 21
279#define OMAP3430_EN_MCSPI3 (1 << 20) 279#define OMAP3430_EN_MCSPI3_MASK (1 << 20)
280#define OMAP3430_EN_MCSPI3_SHIFT 20 280#define OMAP3430_EN_MCSPI3_SHIFT 20
281#define OMAP3430_EN_MCSPI2 (1 << 19) 281#define OMAP3430_EN_MCSPI2_MASK (1 << 19)
282#define OMAP3430_EN_MCSPI2_SHIFT 19 282#define OMAP3430_EN_MCSPI2_SHIFT 19
283#define OMAP3430_EN_MCSPI1 (1 << 18) 283#define OMAP3430_EN_MCSPI1_MASK (1 << 18)
284#define OMAP3430_EN_MCSPI1_SHIFT 18 284#define OMAP3430_EN_MCSPI1_SHIFT 18
285#define OMAP3430_EN_I2C3 (1 << 17) 285#define OMAP3430_EN_I2C3_MASK (1 << 17)
286#define OMAP3430_EN_I2C3_SHIFT 17 286#define OMAP3430_EN_I2C3_SHIFT 17
287#define OMAP3430_EN_I2C2 (1 << 16) 287#define OMAP3430_EN_I2C2_MASK (1 << 16)
288#define OMAP3430_EN_I2C2_SHIFT 16 288#define OMAP3430_EN_I2C2_SHIFT 16
289#define OMAP3430_EN_I2C1 (1 << 15) 289#define OMAP3430_EN_I2C1_MASK (1 << 15)
290#define OMAP3430_EN_I2C1_SHIFT 15 290#define OMAP3430_EN_I2C1_SHIFT 15
291#define OMAP3430_EN_UART2 (1 << 14) 291#define OMAP3430_EN_UART2_MASK (1 << 14)
292#define OMAP3430_EN_UART2_SHIFT 14 292#define OMAP3430_EN_UART2_SHIFT 14
293#define OMAP3430_EN_UART1 (1 << 13) 293#define OMAP3430_EN_UART1_MASK (1 << 13)
294#define OMAP3430_EN_UART1_SHIFT 13 294#define OMAP3430_EN_UART1_SHIFT 13
295#define OMAP3430_EN_GPT11 (1 << 12) 295#define OMAP3430_EN_GPT11_MASK (1 << 12)
296#define OMAP3430_EN_GPT11_SHIFT 12 296#define OMAP3430_EN_GPT11_SHIFT 12
297#define OMAP3430_EN_GPT10 (1 << 11) 297#define OMAP3430_EN_GPT10_MASK (1 << 11)
298#define OMAP3430_EN_GPT10_SHIFT 11 298#define OMAP3430_EN_GPT10_SHIFT 11
299#define OMAP3430_EN_MCBSP5 (1 << 10) 299#define OMAP3430_EN_MCBSP5_MASK (1 << 10)
300#define OMAP3430_EN_MCBSP5_SHIFT 10 300#define OMAP3430_EN_MCBSP5_SHIFT 10
301#define OMAP3430_EN_MCBSP1 (1 << 9) 301#define OMAP3430_EN_MCBSP1_MASK (1 << 9)
302#define OMAP3430_EN_MCBSP1_SHIFT 9 302#define OMAP3430_EN_MCBSP1_SHIFT 9
303#define OMAP3430_EN_FSHOSTUSB (1 << 5) 303#define OMAP3430_EN_FSHOSTUSB_MASK (1 << 5)
304#define OMAP3430_EN_FSHOSTUSB_SHIFT 5 304#define OMAP3430_EN_FSHOSTUSB_SHIFT 5
305#define OMAP3430_EN_D2D (1 << 3) 305#define OMAP3430_EN_D2D_MASK (1 << 3)
306#define OMAP3430_EN_D2D_SHIFT 3 306#define OMAP3430_EN_D2D_SHIFT 3
307 307
308/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 308/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
309#define OMAP3430_EN_HSOTGUSB (1 << 4) 309#define OMAP3430_EN_HSOTGUSB_MASK (1 << 4)
310#define OMAP3430_EN_HSOTGUSB_SHIFT 4 310#define OMAP3430_EN_HSOTGUSB_SHIFT 4
311 311
312/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ 312/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
313#define OMAP3430_ST_MMC2_SHIFT 25 313#define OMAP3430_ST_MMC2_SHIFT 25
@@ -352,21 +352,21 @@
352#define OMAP3430_ST_D2D_MASK (1 << 3) 352#define OMAP3430_ST_D2D_MASK (1 << 3)
353 353
354/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 354/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
355#define OMAP3430_EN_GPIO1 (1 << 3) 355#define OMAP3430_EN_GPIO1_MASK (1 << 3)
356#define OMAP3430_EN_GPIO1_SHIFT 3 356#define OMAP3430_EN_GPIO1_SHIFT 3
357#define OMAP3430_EN_GPT12 (1 << 1) 357#define OMAP3430_EN_GPT12_MASK (1 << 1)
358#define OMAP3430_EN_GPT12_SHIFT 1 358#define OMAP3430_EN_GPT12_SHIFT 1
359#define OMAP3430_EN_GPT1 (1 << 0) 359#define OMAP3430_EN_GPT1_MASK (1 << 0)
360#define OMAP3430_EN_GPT1_SHIFT 0 360#define OMAP3430_EN_GPT1_SHIFT 0
361 361
362/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */ 362/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
363#define OMAP3430_EN_SR2 (1 << 7) 363#define OMAP3430_EN_SR2_MASK (1 << 7)
364#define OMAP3430_EN_SR2_SHIFT 7 364#define OMAP3430_EN_SR2_SHIFT 7
365#define OMAP3430_EN_SR1 (1 << 6) 365#define OMAP3430_EN_SR1_MASK (1 << 6)
366#define OMAP3430_EN_SR1_SHIFT 6 366#define OMAP3430_EN_SR1_SHIFT 6
367 367
368/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 368/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
369#define OMAP3430_EN_GPT12 (1 << 1) 369#define OMAP3430_EN_GPT12_MASK (1 << 1)
370#define OMAP3430_EN_GPT12_SHIFT 1 370#define OMAP3430_EN_GPT12_SHIFT 1
371 371
372/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ 372/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
@@ -386,47 +386,47 @@
386 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX, 386 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
387 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits 387 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
388 */ 388 */
389#define OMAP3430_EN_MPU (1 << 1) 389#define OMAP3430_EN_MPU_MASK (1 << 1)
390#define OMAP3430_EN_MPU_SHIFT 1 390#define OMAP3430_EN_MPU_SHIFT 1
391 391
392/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ 392/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
393#define OMAP3430_EN_GPIO6 (1 << 17) 393#define OMAP3430_EN_GPIO6_MASK (1 << 17)
394#define OMAP3430_EN_GPIO6_SHIFT 17 394#define OMAP3430_EN_GPIO6_SHIFT 17
395#define OMAP3430_EN_GPIO5 (1 << 16) 395#define OMAP3430_EN_GPIO5_MASK (1 << 16)
396#define OMAP3430_EN_GPIO5_SHIFT 16 396#define OMAP3430_EN_GPIO5_SHIFT 16
397#define OMAP3430_EN_GPIO4 (1 << 15) 397#define OMAP3430_EN_GPIO4_MASK (1 << 15)
398#define OMAP3430_EN_GPIO4_SHIFT 15 398#define OMAP3430_EN_GPIO4_SHIFT 15
399#define OMAP3430_EN_GPIO3 (1 << 14) 399#define OMAP3430_EN_GPIO3_MASK (1 << 14)
400#define OMAP3430_EN_GPIO3_SHIFT 14 400#define OMAP3430_EN_GPIO3_SHIFT 14
401#define OMAP3430_EN_GPIO2 (1 << 13) 401#define OMAP3430_EN_GPIO2_MASK (1 << 13)
402#define OMAP3430_EN_GPIO2_SHIFT 13 402#define OMAP3430_EN_GPIO2_SHIFT 13
403#define OMAP3430_EN_UART3 (1 << 11) 403#define OMAP3430_EN_UART3_MASK (1 << 11)
404#define OMAP3430_EN_UART3_SHIFT 11 404#define OMAP3430_EN_UART3_SHIFT 11
405#define OMAP3430_EN_GPT9 (1 << 10) 405#define OMAP3430_EN_GPT9_MASK (1 << 10)
406#define OMAP3430_EN_GPT9_SHIFT 10 406#define OMAP3430_EN_GPT9_SHIFT 10
407#define OMAP3430_EN_GPT8 (1 << 9) 407#define OMAP3430_EN_GPT8_MASK (1 << 9)
408#define OMAP3430_EN_GPT8_SHIFT 9 408#define OMAP3430_EN_GPT8_SHIFT 9
409#define OMAP3430_EN_GPT7 (1 << 8) 409#define OMAP3430_EN_GPT7_MASK (1 << 8)
410#define OMAP3430_EN_GPT7_SHIFT 8 410#define OMAP3430_EN_GPT7_SHIFT 8
411#define OMAP3430_EN_GPT6 (1 << 7) 411#define OMAP3430_EN_GPT6_MASK (1 << 7)
412#define OMAP3430_EN_GPT6_SHIFT 7 412#define OMAP3430_EN_GPT6_SHIFT 7
413#define OMAP3430_EN_GPT5 (1 << 6) 413#define OMAP3430_EN_GPT5_MASK (1 << 6)
414#define OMAP3430_EN_GPT5_SHIFT 6 414#define OMAP3430_EN_GPT5_SHIFT 6
415#define OMAP3430_EN_GPT4 (1 << 5) 415#define OMAP3430_EN_GPT4_MASK (1 << 5)
416#define OMAP3430_EN_GPT4_SHIFT 5 416#define OMAP3430_EN_GPT4_SHIFT 5
417#define OMAP3430_EN_GPT3 (1 << 4) 417#define OMAP3430_EN_GPT3_MASK (1 << 4)
418#define OMAP3430_EN_GPT3_SHIFT 4 418#define OMAP3430_EN_GPT3_SHIFT 4
419#define OMAP3430_EN_GPT2 (1 << 3) 419#define OMAP3430_EN_GPT2_MASK (1 << 3)
420#define OMAP3430_EN_GPT2_SHIFT 3 420#define OMAP3430_EN_GPT2_SHIFT 3
421 421
422/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */ 422/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
423/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits 423/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
424 * be ST_* bits instead? */ 424 * be ST_* bits instead? */
425#define OMAP3430_EN_MCBSP4 (1 << 2) 425#define OMAP3430_EN_MCBSP4_MASK (1 << 2)
426#define OMAP3430_EN_MCBSP4_SHIFT 2 426#define OMAP3430_EN_MCBSP4_SHIFT 2
427#define OMAP3430_EN_MCBSP3 (1 << 1) 427#define OMAP3430_EN_MCBSP3_MASK (1 << 1)
428#define OMAP3430_EN_MCBSP3_SHIFT 1 428#define OMAP3430_EN_MCBSP3_SHIFT 1
429#define OMAP3430_EN_MCBSP2 (1 << 0) 429#define OMAP3430_EN_MCBSP2_MASK (1 << 0)
430#define OMAP3430_EN_MCBSP2_SHIFT 0 430#define OMAP3430_EN_MCBSP2_SHIFT 0
431 431
432/* CM_IDLEST_PER, PM_WKST_PER shared bits */ 432/* CM_IDLEST_PER, PM_WKST_PER shared bits */
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 07a60f1204ca..c20137497c92 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -158,10 +158,10 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
158 WARN_ON(1); 158 WARN_ON(1);
159 159
160 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 160 if (cpu_is_omap24xx() || cpu_is_omap34xx())
161 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, 161 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
162 OMAP2_RM_RSTCTRL); 162 OMAP2_RM_RSTCTRL);
163 if (cpu_is_omap44xx()) 163 if (cpu_is_omap44xx())
164 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, 164 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
165 OMAP4_RM_RSTCTRL); 165 OMAP4_RM_RSTCTRL);
166} 166}
167 167
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 5fba2aa8932c..7bffb6e39d79 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -284,7 +284,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
284#define OMAP_OFFLOADMODE_MASK (0x3 << 3) 284#define OMAP_OFFLOADMODE_MASK (0x3 << 3)
285#define OMAP_ONLOADMODE_SHIFT 1 285#define OMAP_ONLOADMODE_SHIFT 1
286#define OMAP_ONLOADMODE_MASK (0x3 << 1) 286#define OMAP_ONLOADMODE_MASK (0x3 << 1)
287#define OMAP_ENABLE (1 << 0) 287#define OMAP_ENABLE_MASK (1 << 0)
288 288
289/* PRM_RSTTIME */ 289/* PRM_RSTTIME */
290/* Named RM_RSTTIME_WKUP on the 24xx */ 290/* Named RM_RSTTIME_WKUP on the 24xx */
@@ -296,8 +296,8 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
296/* PRM_RSTCTRL */ 296/* PRM_RSTCTRL */
297/* Named RM_RSTCTRL_WKUP on the 24xx */ 297/* Named RM_RSTCTRL_WKUP on the 24xx */
298/* 2420 calls RST_DPLL3 'RST_DPLL' */ 298/* 2420 calls RST_DPLL3 'RST_DPLL' */
299#define OMAP_RST_DPLL3 (1 << 2) 299#define OMAP_RST_DPLL3_MASK (1 << 2)
300#define OMAP_RST_GS (1 << 1) 300#define OMAP_RST_GS_MASK (1 << 1)
301 301
302 302
303/* 303/*
@@ -316,7 +316,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
316 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, 316 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
317 * PM_PWSTST_NEON 317 * PM_PWSTST_NEON
318 */ 318 */
319#define OMAP_INTRANSITION (1 << 20) 319#define OMAP_INTRANSITION_MASK (1 << 20)
320 320
321 321
322/* 322/*
@@ -338,7 +338,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
338 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS, 338 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
339 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON 339 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
340 */ 340 */
341#define OMAP_COREDOMAINWKUP_RST (1 << 3) 341#define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3)
342 342
343/* 343/*
344 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP 344 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
@@ -347,7 +347,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
347 * 347 *
348 * 3430: RM_RSTST_CORE, RM_RSTST_EMU 348 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
349 */ 349 */
350#define OMAP_DOMAINWKUP_RST (1 << 2) 350#define OMAP_DOMAINWKUP_RST_MASK (1 << 2)
351 351
352/* 352/*
353 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP 353 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
@@ -357,8 +357,8 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
357 * 357 *
358 * 3430: RM_RSTST_CORE, RM_RSTST_EMU 358 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
359 */ 359 */
360#define OMAP_GLOBALWARM_RST (1 << 1) 360#define OMAP_GLOBALWARM_RST_MASK (1 << 1)
361#define OMAP_GLOBALCOLD_RST (1 << 0) 361#define OMAP_GLOBALCOLD_RST_MASK (1 << 0)
362 362
363/* 363/*
364 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP 364 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
@@ -382,7 +382,7 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
382 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, 382 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
383 * PM_PWSTCTRL_NEON 383 * PM_PWSTCTRL_NEON
384 */ 384 */
385#define OMAP_LOGICRETSTATE (1 << 2) 385#define OMAP_LOGICRETSTATE_MASK (1 << 2)
386 386
387/* 387/*
388 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, 388 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 21:54:02 -0500