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-rw-r--r--arch/arm/plat-s3c64xx/Kconfig1
-rw-r--r--arch/arm/plat-s3c64xx/irq.c117
-rw-r--r--arch/arm/plat-samsung/Kconfig5
-rw-r--r--arch/arm/plat-samsung/Makefile1
-rw-r--r--arch/arm/plat-samsung/include/plat/irq-uart.h20
-rw-r--r--arch/arm/plat-samsung/irq-uart.c143
6 files changed, 173 insertions, 114 deletions
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig
index 02d716fb157a..0fba1f956b8a 100644
--- a/arch/arm/plat-s3c64xx/Kconfig
+++ b/arch/arm/plat-s3c64xx/Kconfig
@@ -15,6 +15,7 @@ config PLAT_S3C64XX
15 select ARCH_REQUIRE_GPIOLIB 15 select ARCH_REQUIRE_GPIOLIB
16 select SAMSUNG_CLKSRC 16 select SAMSUNG_CLKSRC
17 select SAMSUNG_IRQ_VIC_TIMER 17 select SAMSUNG_IRQ_VIC_TIMER
18 select SAMSUNG_IRQ_UART
18 select S3C_GPIO_TRACK 19 select S3C_GPIO_TRACK
19 select S3C_GPIO_PULL_UPDOWN 20 select S3C_GPIO_PULL_UPDOWN
20 select S3C_GPIO_CFG_S3C24XX 21 select S3C_GPIO_CFG_S3C24XX
diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/plat-s3c64xx/irq.c
index 8b69bca05876..b98451e8ee24 100644
--- a/arch/arm/plat-s3c64xx/irq.c
+++ b/arch/arm/plat-s3c64xx/irq.c
@@ -22,19 +22,10 @@
22 22
23#include <mach/map.h> 23#include <mach/map.h>
24#include <plat/irq-vic-timer.h> 24#include <plat/irq-vic-timer.h>
25#include <plat/regs-serial.h> 25#include <plat/irq-uart.h>
26#include <plat/cpu.h> 26#include <plat/cpu.h>
27 27
28struct uart_irq { 28static struct s3c_uart_irq uart_irqs[] = {
29 void __iomem *regs;
30 unsigned int base_irq;
31 unsigned int parent_irq;
32};
33
34/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
35 * are consecutive when looking up the interrupt in the demux routines.
36 */
37static struct uart_irq uart_irqs[] = {
38 [0] = { 29 [0] = {
39 .regs = S3C_VA_UART0, 30 .regs = S3C_VA_UART0,
40 .base_irq = IRQ_S3CUART_BASE0, 31 .base_irq = IRQ_S3CUART_BASE0,
@@ -57,110 +48,9 @@ static struct uart_irq uart_irqs[] = {
57 }, 48 },
58}; 49};
59 50
60static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
61{
62 struct uart_irq *uirq = get_irq_chip_data(irq);
63 return uirq->regs;
64}
65
66static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
67{
68 return irq & 3;
69}
70
71/* UART interrupt registers, not worth adding to seperate include header */
72
73static void s3c_irq_uart_mask(unsigned int irq)
74{
75 void __iomem *regs = s3c_irq_uart_base(irq);
76 unsigned int bit = s3c_irq_uart_bit(irq);
77 u32 reg;
78
79 reg = __raw_readl(regs + S3C64XX_UINTM);
80 reg |= (1 << bit);
81 __raw_writel(reg, regs + S3C64XX_UINTM);
82}
83
84static void s3c_irq_uart_maskack(unsigned int irq)
85{
86 void __iomem *regs = s3c_irq_uart_base(irq);
87 unsigned int bit = s3c_irq_uart_bit(irq);
88 u32 reg;
89
90 reg = __raw_readl(regs + S3C64XX_UINTM);
91 reg |= (1 << bit);
92 __raw_writel(reg, regs + S3C64XX_UINTM);
93 __raw_writel(1 << bit, regs + S3C64XX_UINTP);
94}
95
96static void s3c_irq_uart_unmask(unsigned int irq)
97{
98 void __iomem *regs = s3c_irq_uart_base(irq);
99 unsigned int bit = s3c_irq_uart_bit(irq);
100 u32 reg;
101
102 reg = __raw_readl(regs + S3C64XX_UINTM);
103 reg &= ~(1 << bit);
104 __raw_writel(reg, regs + S3C64XX_UINTM);
105}
106
107static void s3c_irq_uart_ack(unsigned int irq)
108{
109 void __iomem *regs = s3c_irq_uart_base(irq);
110 unsigned int bit = s3c_irq_uart_bit(irq);
111
112 __raw_writel(1 << bit, regs + S3C64XX_UINTP);
113}
114
115static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
116{
117 struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0];
118 u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
119 int base = uirq->base_irq;
120
121 if (pend & (1 << 0))
122 generic_handle_irq(base);
123 if (pend & (1 << 1))
124 generic_handle_irq(base + 1);
125 if (pend & (1 << 2))
126 generic_handle_irq(base + 2);
127 if (pend & (1 << 3))
128 generic_handle_irq(base + 3);
129}
130
131static struct irq_chip s3c_irq_uart = {
132 .name = "s3c-uart",
133 .mask = s3c_irq_uart_mask,
134 .unmask = s3c_irq_uart_unmask,
135 .mask_ack = s3c_irq_uart_maskack,
136 .ack = s3c_irq_uart_ack,
137};
138
139static void __init s3c64xx_uart_irq(struct uart_irq *uirq)
140{
141 void __iomem *reg_base = uirq->regs;
142 unsigned int irq;
143 int offs;
144
145 /* mask all interrupts at the start. */
146 __raw_writel(0xf, reg_base + S3C64XX_UINTM);
147
148 for (offs = 0; offs < 3; offs++) {
149 irq = uirq->base_irq + offs;
150
151 set_irq_chip(irq, &s3c_irq_uart);
152 set_irq_chip_data(irq, uirq);
153 set_irq_handler(irq, handle_level_irq);
154 set_irq_flags(irq, IRQF_VALID);
155 }
156
157 set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
158}
159 51
160void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) 52void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
161{ 53{
162 int uart;
163
164 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); 54 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
165 55
166 /* initialise the pair of VICs */ 56 /* initialise the pair of VICs */
@@ -175,6 +65,5 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
175 s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); 65 s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
176 s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); 66 s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
177 67
178 for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) 68 s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
179 s3c64xx_uart_irq(&uart_irqs[uart]);
180} 69}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index cedecd87d899..900b463fc197 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -26,6 +26,11 @@ config SAMSUNG_IRQ_VIC_TIMER
26 help 26 help
27 Internal configuration to build the VIC timer interrupt code. 27 Internal configuration to build the VIC timer interrupt code.
28 28
29config SAMSUNG_IRQ_UART
30 bool
31 help
32 Internal configuration to build the IRQ UART demux code.
33
29# options for gpio configuration support 34# options for gpio configuration support
30 35
31config S3C_GPIO_CFG_S3C24XX 36config S3C_GPIO_CFG_S3C24XX
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index aa048c7337dd..aeb7e12d1f63 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -17,6 +17,7 @@ obj-y += gpio-config.o
17 17
18obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o 18obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
19 19
20obj-$(CONFIG_SAMSUNG_IRQ_UART) += irq-uart.o
20obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o 21obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o
21 22
22# devices 23# devices
diff --git a/arch/arm/plat-samsung/include/plat/irq-uart.h b/arch/arm/plat-samsung/include/plat/irq-uart.h
new file mode 100644
index 000000000000..a9331e49bea3
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/irq-uart.h
@@ -0,0 +1,20 @@
1/* arch/arm/plat-samsung/include/plat/irq-uart.h
2 *
3 * Copyright (c) 2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for Samsung SoC UART IRQ demux for S3C64XX and later
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct s3c_uart_irq {
14 void __iomem *regs;
15 unsigned int base_irq;
16 unsigned int parent_irq;
17};
18
19extern void s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs);
20
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
new file mode 100644
index 000000000000..4f8c102674ae
--- /dev/null
+++ b/arch/arm/plat-samsung/irq-uart.c
@@ -0,0 +1,143 @@
1/* arch/arm/plat-samsung/irq-uart.c
2 * originally part of arch/arm/plat-s3c64xx/irq.c
3 *
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * Samsung- UART Interrupt handling
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/serial_core.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21
22#include <mach/map.h>
23#include <plat/irq-uart.h>
24#include <plat/regs-serial.h>
25#include <plat/cpu.h>
26
27/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
28 * are consecutive when looking up the interrupt in the demux routines.
29 */
30
31static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
32{
33 struct s3c_uart_irq *uirq = get_irq_chip_data(irq);
34 return uirq->regs;
35}
36
37static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
38{
39 return irq & 3;
40}
41
42static void s3c_irq_uart_mask(unsigned int irq)
43{
44 void __iomem *regs = s3c_irq_uart_base(irq);
45 unsigned int bit = s3c_irq_uart_bit(irq);
46 u32 reg;
47
48 reg = __raw_readl(regs + S3C64XX_UINTM);
49 reg |= (1 << bit);
50 __raw_writel(reg, regs + S3C64XX_UINTM);
51}
52
53static void s3c_irq_uart_maskack(unsigned int irq)
54{
55 void __iomem *regs = s3c_irq_uart_base(irq);
56 unsigned int bit = s3c_irq_uart_bit(irq);
57 u32 reg;
58
59 reg = __raw_readl(regs + S3C64XX_UINTM);
60 reg |= (1 << bit);
61 __raw_writel(reg, regs + S3C64XX_UINTM);
62 __raw_writel(1 << bit, regs + S3C64XX_UINTP);
63}
64
65static void s3c_irq_uart_unmask(unsigned int irq)
66{
67 void __iomem *regs = s3c_irq_uart_base(irq);
68 unsigned int bit = s3c_irq_uart_bit(irq);
69 u32 reg;
70
71 reg = __raw_readl(regs + S3C64XX_UINTM);
72 reg &= ~(1 << bit);
73 __raw_writel(reg, regs + S3C64XX_UINTM);
74}
75
76static void s3c_irq_uart_ack(unsigned int irq)
77{
78 void __iomem *regs = s3c_irq_uart_base(irq);
79 unsigned int bit = s3c_irq_uart_bit(irq);
80
81 __raw_writel(1 << bit, regs + S3C64XX_UINTP);
82}
83
84static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
85{
86 struct s3c_uart_irq *uirq = desc->handler_data;
87 u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
88 int base = uirq->base_irq;
89
90 if (pend & (1 << 0))
91 generic_handle_irq(base);
92 if (pend & (1 << 1))
93 generic_handle_irq(base + 1);
94 if (pend & (1 << 2))
95 generic_handle_irq(base + 2);
96 if (pend & (1 << 3))
97 generic_handle_irq(base + 3);
98}
99
100static struct irq_chip s3c_irq_uart = {
101 .name = "s3c-uart",
102 .mask = s3c_irq_uart_mask,
103 .unmask = s3c_irq_uart_unmask,
104 .mask_ack = s3c_irq_uart_maskack,
105 .ack = s3c_irq_uart_ack,
106};
107
108static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
109{
110 struct irq_desc *desc = irq_to_desc(uirq->parent_irq);
111 void __iomem *reg_base = uirq->regs;
112 unsigned int irq;
113 int offs;
114
115 /* mask all interrupts at the start. */
116 __raw_writel(0xf, reg_base + S3C64XX_UINTM);
117
118 for (offs = 0; offs < 3; offs++) {
119 irq = uirq->base_irq + offs;
120
121 set_irq_chip(irq, &s3c_irq_uart);
122 set_irq_chip_data(irq, uirq);
123 set_irq_handler(irq, handle_level_irq);
124 set_irq_flags(irq, IRQF_VALID);
125 }
126
127 desc->handler_data = uirq;
128 set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
129}
130
131/**
132 * s3c_init_uart_irqs() - initialise UART IRQs and the necessary demuxing
133 * @irq: The interrupt data for registering
134 * @nr_irqs: The number of interrupt descriptions in @irq.
135 *
136 * Register the UART interrupts specified by @irq including the demuxing
137 * routines. This supports the S3C6400 and newer style of devices.
138 */
139void __init s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs)
140{
141 for (; nr_irqs > 0; nr_irqs--, irq++)
142 s3c_init_uart_irq(irq);
143}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 08:56:55 -0500