176 files changed, 7343 insertions, 1266 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8e6672acb9c9..b0c3c0d89e05 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -18,6 +18,8 @@ config ARM
        select HAVE_KRETPROBES if (HAVE_KPROBES)
        select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
        select HAVE_GENERIC_DMA_COHERENT
+        select HAVE_KERNEL_GZIP
+        select HAVE_KERNEL_LZO
        help
          The ARM series is a line of low-power-consumption RISC chip designs
          licensed by ARM Ltd and targeted at embedded applications and
@@ -697,6 +699,7 @@ config ARCH_DAVINCI
        select HAVE_IDE
        select COMMON_CLKDEV
        select GENERIC_ALLOCATOR
+        select ARCH_HAS_HOLES_MEMORYMODEL
        help
          Support for TI's DaVinci platform.
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index ce39dc540085..2d4d88ba73bf 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -63,8 +63,12 @@ endif
 SEDFLAGS        = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/
-targets       := vmlinux vmlinux.lds piggy.gz piggy.o font.o font.c \
+suffix_$(CONFIG_KERNEL_GZIP) = gzip
-                 head.o misc.o $(OBJS)
+suffix_$(CONFIG_KERNEL_LZO)  = lzo
+targets       := vmlinux vmlinux.lds \
+                 piggy.$(suffix_y) piggy.$(suffix_y).o \
+                 font.o font.c head.o misc.o $(OBJS)
 ifeq ($(CONFIG_FUNCTION_TRACER),y)
 ORIG_CFLAGS := $(KBUILD_CFLAGS)
@@ -87,22 +91,34 @@ endif
 ifneq ($(PARAMS_PHYS),)
 LDFLAGS_vmlinux += --defsym params_phys=$(PARAMS_PHYS)
 endif
-LDFLAGS_vmlinux += -p --no-undefined -X \
+# ?
-        $(shell $(CC) $(KBUILD_CFLAGS) --print-libgcc-file-name) -T
+LDFLAGS_vmlinux += -p
+# Report unresolved symbol references
+LDFLAGS_vmlinux += --no-undefined
+# Delete all temporary local symbols
+LDFLAGS_vmlinux += -X
+# Next argument is a linker script
+LDFLAGS_vmlinux += -T
+# For __aeabi_uidivmod
+lib1funcs = $(obj)/lib1funcs.o
+$(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE
+        $(call cmd,shipped)
 # Don't allow any static data in misc.o, which
 # would otherwise mess up our GOT table
 CFLAGS_misc.o := -Dstatic=
-$(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.o \
+$(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \
-                $(addprefix $(obj)/, $(OBJS)) FORCE
+                $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE
        $(call if_changed,ld)
        @:
-$(obj)/piggy.gz: $(obj)/../Image FORCE
+$(obj)/piggy.$(suffix_y): $(obj)/../Image FORCE
-        $(call if_changed,gzip)
+        $(call if_changed,$(suffix_y))
-$(obj)/piggy.o:  $(obj)/piggy.gz FORCE
+$(obj)/piggy.$(suffix_y).o:  $(obj)/piggy.$(suffix_y) FORCE
 CFLAGS_font.o := -Dstatic=
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 17153b54613b..7e0fe4d42c7b 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -18,10 +18,15 @@
 unsigned int __machine_arch_type;
+#define _LINUX_STRING_H_
 #include <linux/compiler.h>     /* for inline */
 #include <linux/types.h>        /* for size_t */
 #include <linux/stddef.h>       /* for NULL */
 #include <asm/string.h>
+#include <linux/linkage.h>
+#include <asm/unaligned.h>
 #ifdef STANDALONE_DEBUG
 #define putstr printf
@@ -188,34 +193,8 @@ static inline __ptr_t memcpy(__ptr_t __dest, __const __ptr_t __src,
 /*
 * gzip delarations
 */
-#define OF(args)  args
 #define STATIC static
-typedef unsigned char  uch;
-typedef unsigned short ush;
-typedef unsigned long  ulg;
-#define WSIZE 0x8000            /* Window size must be at least 32k, */
-                                /* and a power of two */
-static uch *inbuf;              /* input buffer */
-static uch window[WSIZE];       /* Sliding window buffer */
-static unsigned insize;         /* valid bytes in inbuf */
-static unsigned inptr;          /* index of next byte to be processed in inbuf */
-static unsigned outcnt;         /* bytes in output buffer */
-/* gzip flag byte */
-#define ASCII_FLAG   0x01 /* bit 0 set: file probably ascii text */
-#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
-#define EXTRA_FIELD  0x04 /* bit 2 set: extra field present */
-#define ORIG_NAME    0x08 /* bit 3 set: original file name present */
-#define COMMENT      0x10 /* bit 4 set: file comment present */
-#define ENCRYPTED    0x20 /* bit 5 set: file is encrypted */
-#define RESERVED     0xC0 /* bit 6,7:   reserved */
-#define get_byte()  (inptr < insize ? inbuf[inptr++] : fill_inbuf())
 /* Diagnostic functions */
 #ifdef DEBUG
 #  define Assert(cond,msg) {if(!(cond)) error(msg);}
@@ -233,24 +212,20 @@ static unsigned outcnt;		/* bytes in output buffer */
 #  define Tracecv(c,x)
 #endif
-static int  fill_inbuf(void);
-static void flush_window(void);
 static void error(char *m);
 extern char input_data[];
 extern char input_data_end[];
-static uch *output_data;
+static unsigned char *output_data;
-static ulg output_ptr;
+static unsigned long output_ptr;
-static ulg bytes_out;
 static void error(char *m);
 static void putstr(const char *);
-extern int end;
+static unsigned long free_mem_ptr;
-static ulg free_mem_ptr;
+static unsigned long free_mem_end_ptr;
-static ulg free_mem_end_ptr;
 #ifdef STANDALONE_DEBUG
 #define NO_INFLATE_MALLOC
@@ -258,46 +233,13 @@ static ulg free_mem_end_ptr;
 #define ARCH_HAS_DECOMP_WDOG
-#include "../../../../lib/inflate.c"
+#ifdef CONFIG_KERNEL_GZIP
+#include "../../../../lib/decompress_inflate.c"
-/* ===========================================================================
+#endif
- * Fill the input buffer. This is called only when the buffer is empty
- * and at least one byte is really needed.
- */
-int fill_inbuf(void)
-{
-        if (insize != 0)
-                error("ran out of input data");
-        inbuf = input_data;
-        insize = &input_data_end[0] - &input_data[0];
-        inptr = 1;
-        return inbuf[0];
-}
-/* ===========================================================================
+#ifdef CONFIG_KERNEL_LZO
- * Write the output window window[0..outcnt-1] and update crc and bytes_out.
+#include "../../../../lib/decompress_unlzo.c"
- * (Used for the decompressed data only.)
+#endif
- */
-void flush_window(void)
-{
-        ulg c = crc;
-        unsigned n;
-        uch *in, *out, ch;
-        in = window;
-        out = &output_data[output_ptr];
-        for (n = 0; n < outcnt; n++) {
-                ch = *out++ = *in++;
-                c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
-        }
-        crc = c;
-        bytes_out += (ulg)outcnt;
-        output_ptr += (ulg)outcnt;
-        outcnt = 0;
-        putstr(".");
-}
 #ifndef arch_error
 #define arch_error(x)
@@ -314,22 +256,33 @@ static void error(char *x)
        while(1);       /* Halt */
 }
+asmlinkage void __div0(void)
+{
+        error("Attempting division by 0!");
+}
 #ifndef STANDALONE_DEBUG
-ulg
+unsigned long
-decompress_kernel(ulg output_start, ulg free_mem_ptr_p, ulg free_mem_ptr_end_p,
+decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
-                  int arch_id)
+                unsigned long free_mem_ptr_end_p,
+                int arch_id)
 {
-        output_data             = (uch *)output_start;  /* Points to kernel start */
+        unsigned char *tmp;
+        output_data             = (unsigned char *)output_start;
        free_mem_ptr            = free_mem_ptr_p;
        free_mem_end_ptr        = free_mem_ptr_end_p;
        __machine_arch_type     = arch_id;
        arch_decomp_setup();
-        makecrc();
+        tmp = (unsigned char *) (((unsigned long)input_data_end) - 4);
+        output_ptr = get_unaligned_le32(tmp);
        putstr("Uncompressing Linux...");
-        gunzip();
+        decompress(input_data, input_data_end - input_data,
+                        NULL, NULL, output_data, NULL, error);
        putstr(" done, booting the kernel.\n");
        return output_ptr;
 }
@@ -341,11 +294,10 @@ int main()
 {
        output_data = output_buffer;
-        makecrc();
        putstr("Uncompressing Linux...");
-        gunzip();
+        decompress(input_data, input_data_end - input_data,
+                        NULL, NULL, output_data, NULL, error);
        putstr("done.\n");
        return 0;
 }
 #endif
-        
diff --git a/arch/arm/boot/compressed/piggy.gzip.S b/arch/arm/boot/compressed/piggy.gzip.S
new file mode 100644
index 000000000000..a68adf91a165
--- /dev/null
+++ b/arch/arm/boot/compressed/piggy.gzip.S
@@ -0,0 +1,6 @@
+        .section .piggydata,#alloc
+        .globl  input_data
+input_data:
+        .incbin "arch/arm/boot/compressed/piggy.gzip"
+        .globl  input_data_end
+input_data_end:
diff --git a/arch/arm/boot/compressed/piggy.S b/arch/arm/boot/compressed/piggy.lzo.S
index 54c951800ebd..a425ad95959a 100644
--- a/arch/arm/boot/compressed/piggy.S
+++ b/arch/arm/boot/compressed/piggy.lzo.S
@@ -1,6 +1,6 @@
        .section .piggydata,#alloc
        .globl  input_data
 input_data:
-        .incbin "arch/arm/boot/compressed/piggy.gz"
+        .incbin "arch/arm/boot/compressed/piggy.lzo"
        .globl  input_data_end
 input_data_end:
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index cc32c1e54a59..cc0a932bbea9 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -277,7 +277,7 @@ static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size,
                 * We don't need to sync the DMA buffer since
                 * it was allocated via the coherent allocators.
                 */
-                dma_cache_maint(ptr, size, dir);
+                __dma_single_cpu_to_dev(ptr, size, dir);
        }
        return dma_addr;
@@ -315,6 +315,8 @@ static inline void unmap_single(struct device *dev, dma_addr_t dma_addr,
                        __cpuc_flush_dcache_area(ptr, size);
                }
                free_safe_buffer(dev->archdata.dmabounce, buf);
+        } else {
+                __dma_single_dev_to_cpu(dma_to_virt(dev, dma_addr), size, dir);
        }
 }
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index f232941de8ab..1cf999ade4bc 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -18,6 +18,7 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/io.h>
@@ -28,48 +29,6 @@
 #include <asm/mach/irq.h>
 #include <asm/hardware/vic.h>
-static void vic_ack_irq(unsigned int irq)
-{
-        void __iomem *base = get_irq_chip_data(irq);
-        irq &= 31;
-        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
-        /* moreover, clear the soft-triggered, in case it was the reason */
-        writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
-}
-static void vic_mask_irq(unsigned int irq)
-{
-        void __iomem *base = get_irq_chip_data(irq);
-        irq &= 31;
-        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
-}
-static void vic_unmask_irq(unsigned int irq)
-{
-        void __iomem *base = get_irq_chip_data(irq);
-        irq &= 31;
-        writel(1 << irq, base + VIC_INT_ENABLE);
-}
-/**
- * vic_init2 - common initialisation code
- * @base: Base of the VIC.
- *
- * Common initialisation code for registeration
- * and resume.
-*/
-static void vic_init2(void __iomem *base)
-{
-        int i;
-        for (i = 0; i < 16; i++) {
-                void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
-                writel(VIC_VECT_CNTL_ENABLE | i, reg);
-        }
-        writel(32, base + VIC_PL190_DEF_VECT_ADDR);
-}
 #if defined(CONFIG_PM)
 /**
 * struct vic_device - VIC PM device
@@ -99,13 +58,34 @@ struct vic_device {
 /* we cannot allocate memory when VICs are initially registered */
 static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
+static int vic_id;
 static inline struct vic_device *to_vic(struct sys_device *sys)
 {
        return container_of(sys, struct vic_device, sysdev);
 }
+#endif /* CONFIG_PM */
-static int vic_id;
+/**
+ * vic_init2 - common initialisation code
+ * @base: Base of the VIC.
+ *
+ * Common initialisation code for registeration
+ * and resume.
+*/
+static void vic_init2(void __iomem *base)
+{
+        int i;
+        for (i = 0; i < 16; i++) {
+                void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
+                writel(VIC_VECT_CNTL_ENABLE | i, reg);
+        }
+        writel(32, base + VIC_PL190_DEF_VECT_ADDR);
+}
+#if defined(CONFIG_PM)
 static int vic_class_resume(struct sys_device *dev)
 {
        struct vic_device *vic = to_vic(dev);
@@ -159,31 +139,6 @@ struct sysdev_class vic_class = {
 };
 /**
- * vic_pm_register - Register a VIC for later power management control
- * @base: The base address of the VIC.
- * @irq: The base IRQ for the VIC.
- * @resume_sources: bitmask of interrupts allowed for resume sources.
- *
- * Register the VIC with the system device tree so that it can be notified
- * of suspend and resume requests and ensure that the correct actions are
- * taken to re-instate the settings on resume.
- */
-static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
-{
-        struct vic_device *v;
-        if (vic_id >= ARRAY_SIZE(vic_devices))
-                printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
-        else {
-                v = &vic_devices[vic_id];
-                v->base = base;
-                v->resume_sources = resume_sources;
-                v->irq = irq;
-                vic_id++;
-        }
-}
-/**
 * vic_pm_init - initicall to register VIC pm
 *
 * This is called via late_initcall() to register
@@ -219,9 +174,60 @@ static int __init vic_pm_init(void)
        return 0;
 }
 late_initcall(vic_pm_init);
+/**
+ * vic_pm_register - Register a VIC for later power management control
+ * @base: The base address of the VIC.
+ * @irq: The base IRQ for the VIC.
+ * @resume_sources: bitmask of interrupts allowed for resume sources.
+ *
+ * Register the VIC with the system device tree so that it can be notified
+ * of suspend and resume requests and ensure that the correct actions are
+ * taken to re-instate the settings on resume.
+ */
+static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
+{
+        struct vic_device *v;
+        if (vic_id >= ARRAY_SIZE(vic_devices))
+                printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
+        else {
+                v = &vic_devices[vic_id];
+                v->base = base;
+                v->resume_sources = resume_sources;
+                v->irq = irq;
+                vic_id++;
+        }
+}
+#else
+static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
+#endif /* CONFIG_PM */
+static void vic_ack_irq(unsigned int irq)
+{
+        void __iomem *base = get_irq_chip_data(irq);
+        irq &= 31;
+        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
+        /* moreover, clear the soft-triggered, in case it was the reason */
+        writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
+}
+static void vic_mask_irq(unsigned int irq)
+{
+        void __iomem *base = get_irq_chip_data(irq);
+        irq &= 31;
+        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
+}
+static void vic_unmask_irq(unsigned int irq)
+{
+        void __iomem *base = get_irq_chip_data(irq);
+        irq &= 31;
+        writel(1 << irq, base + VIC_INT_ENABLE);
+}
+#if defined(CONFIG_PM)
 static struct vic_device *vic_from_irq(unsigned int irq)
 {
        struct vic_device *v = vic_devices;
@@ -255,10 +261,7 @@ static int vic_set_wake(unsigned int irq, unsigned int on)
        return 0;
 }
 #else
-static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
 #define vic_set_wake NULL
 #endif /* CONFIG_PM */
@@ -270,9 +273,62 @@ static struct irq_chip vic_chip = {
        .set_wake = vic_set_wake,
 };
-/* The PL190 cell from ARM has been modified by ST, so handle both here */
+/*
-static void vik_init_st(void __iomem *base, unsigned int irq_start,
+ * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
-                         u32 vic_sources);
+ * The original cell has 32 interrupts, while the modified one has 64,
+ * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
+ * the probe function is called twice, with base set to offset 000
+ *  and 020 within the page. We call this "second block".
+ */
+static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
+                                u32 vic_sources)
+{
+        unsigned int i;
+        int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
+        /* Disable all interrupts initially. */
+        writel(0, base + VIC_INT_SELECT);
+        writel(0, base + VIC_INT_ENABLE);
+        writel(~0, base + VIC_INT_ENABLE_CLEAR);
+        writel(0, base + VIC_IRQ_STATUS);
+        writel(0, base + VIC_ITCR);
+        writel(~0, base + VIC_INT_SOFT_CLEAR);
+        /*
+         * Make sure we clear all existing interrupts. The vector registers
+         * in this cell are after the second block of general registers,
+         * so we can address them using standard offsets, but only from
+         * the second base address, which is 0x20 in the page
+         */
+        if (vic_2nd_block) {
+                writel(0, base + VIC_PL190_VECT_ADDR);
+                for (i = 0; i < 19; i++) {
+                        unsigned int value;
+                        value = readl(base + VIC_PL190_VECT_ADDR);
+                        writel(value, base + VIC_PL190_VECT_ADDR);
+                }
+                /* ST has 16 vectors as well, but we don't enable them by now */
+                for (i = 0; i < 16; i++) {
+                        void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
+                        writel(0, reg);
+                }
+                writel(32, base + VIC_PL190_DEF_VECT_ADDR);
+        }
+        for (i = 0; i < 32; i++) {
+                if (vic_sources & (1 << i)) {
+                        unsigned int irq = irq_start + i;
+                        set_irq_chip(irq, &vic_chip);
+                        set_irq_chip_data(irq, base);
+                        set_irq_handler(irq, handle_level_irq);
+                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+                }
+        }
+}
 /**
 * vic_init - initialise a vectored interrupt controller
@@ -299,7 +355,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
        switch(vendor) {
        case AMBA_VENDOR_ST:
-                vik_init_st(base, irq_start, vic_sources);
+                vic_init_st(base, irq_start, vic_sources);
                return;
        default:
                printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
@@ -343,60 +399,3 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
        vic_pm_register(base, irq_start, resume_sources);
 }
-/*
- * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
- * The original cell has 32 interrupts, while the modified one has 64,
- * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
- * the probe function is called twice, with base set to offset 000
- *  and 020 within the page. We call this "second block".
- */
-static void __init vik_init_st(void __iomem *base, unsigned int irq_start,
-                                u32 vic_sources)
-{
-        unsigned int i;
-        int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
-        /* Disable all interrupts initially. */
-        writel(0, base + VIC_INT_SELECT);
-        writel(0, base + VIC_INT_ENABLE);
-        writel(~0, base + VIC_INT_ENABLE_CLEAR);
-        writel(0, base + VIC_IRQ_STATUS);
-        writel(0, base + VIC_ITCR);
-        writel(~0, base + VIC_INT_SOFT_CLEAR);
-        /*
-         * Make sure we clear all existing interrupts. The vector registers
-         * in this cell are after the second block of general registers,
-         * so we can address them using standard offsets, but only from
-         * the second base address, which is 0x20 in the page
-         */
-        if (vic_2nd_block) {
-                writel(0, base + VIC_PL190_VECT_ADDR);
-                for (i = 0; i < 19; i++) {
-                        unsigned int value;
-                        value = readl(base + VIC_PL190_VECT_ADDR);
-                        writel(value, base + VIC_PL190_VECT_ADDR);
-                }
-                /* ST has 16 vectors as well, but we don't enable them by now */
-                for (i = 0; i < 16; i++) {
-                        void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
-                        writel(0, reg);
-                }
-                writel(32, base + VIC_PL190_DEF_VECT_ADDR);
-        }
-        for (i = 0; i < 32; i++) {
-                if (vic_sources & (1 << i)) {
-                        unsigned int irq = irq_start + i;
-                        set_irq_chip(irq, &vic_chip);
-                        set_irq_chip_data(irq, base);
-                        set_irq_handler(irq, handle_level_irq);
-                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-                }
-        }
-}
diff --git a/arch/arm/configs/at572d940hfek_defconfig b/arch/arm/configs/at572d940hfek_defconfig
new file mode 100644
index 000000000000..76d724b8041a
--- /dev/null
+++ b/arch/arm/configs/at572d940hfek_defconfig
@@ -0,0 +1,1640 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28-rc7
+# Fri Dec  5 10:58:47 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-AT572D940HF"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+# CONFIG_TASK_DELAY_ACCT is not set
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_NS is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_DEVICE is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+# CONFIG_USER_SCHED is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_MARKERS=y
+CONFIG_OPROFILE=m
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+CONFIG_BLK_DEV_IO_TRACE=y
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_FREEZER is not set
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+#
+# Boot options
+#
+#
+# Power management
+#
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91SAM9G20 is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_ARCH_AT572D940HF=y
+CONFIG_AT91_PMC_UNIT=y
+#
+# AT572D940HF Board Type
+#
+CONFIG_MACH_AT572D940HFEB=y
+#
+# AT91 Board Options
+#
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
+# CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16 is not set
+CONFIG_NUM_SERIAL=3
+#
+# AT91 Feature Selections
+#
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+CONFIG_RESOURCES_64BIT=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="mem=48M console=ttyS0 initrd=0x21100000,3145728 root=/dev/ram0 rw ip=172.16.1.181"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+CONFIG_FPE_NWFPE_XP=y
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+#
+# Networking options
+#
+CONFIG_PACKET=m
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+CONFIG_NET_TCPPROBE=m
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=m
+CONFIG_CAN_DEBUG_DEVICES=y
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+CONFIG_MTD=m
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=1
+CONFIG_MTD_CONCAT=m
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK=m
+CONFIG_MTD_BLOCK_RO=m
+CONFIG_FTL=m
+CONFIG_NFTL=m
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=m
+CONFIG_RFD_FTL=m
+CONFIG_SSFDC=m
+CONFIG_MTD_OOPS=m
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=m
+CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_GEN_PROBE=m
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_CFI_STAA=m
+CONFIG_MTD_CFI_UTIL=m
+CONFIG_MTD_RAM=m
+CONFIG_MTD_ROM=m
+CONFIG_MTD_ABSENT=m
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PHYSMAP_START=0x8000000
+CONFIG_MTD_PHYSMAP_LEN=0x4000000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+CONFIG_MTD_PLATRAM=m
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=m
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+# CONFIG_MTD_DATAFLASH_OTP is not set
+CONFIG_MTD_M25P80=m
+CONFIG_M25PXX_USE_FAST_READ=y
+CONFIG_MTD_SLRAM=m
+CONFIG_MTD_PHRAM=m
+CONFIG_MTD_MTDRAM=m
+CONFIG_MTDRAM_TOTAL_SIZE=4096
+CONFIG_MTDRAM_ERASE_SIZE=128
+CONFIG_MTD_BLOCK2MTD=m
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=m
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=m
+CONFIG_MTD_NAND_DISKONCHIP=m
+# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
+# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set
+# CONFIG_MTD_NAND_ATMEL is not set
+CONFIG_MTD_NAND_NANDSIM=m
+CONFIG_MTD_NAND_PLATFORM=m
+CONFIG_MTD_ALAUDA=m
+# CONFIG_MTD_ONENAND is not set
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=m
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+CONFIG_MTD_UBI_GLUEBI=y
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ICS932S401 is not set
+CONFIG_ATMEL_SSC=m
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+CONFIG_CHR_DEV_SCH=m
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+CONFIG_BONDING=m
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+CONFIG_TUN=m
+CONFIG_VETH=m
+CONFIG_PHYLIB=y
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=m
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+#
+# Wireless LAN
+#
+CONFIG_WLAN_PRE80211=y
+CONFIG_STRIP=m
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_DEBUG is not set
+CONFIG_USB_ZD1201=m
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+# CONFIG_USB_NET_SMSC95XX is not set
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+# CONFIG_USB_NET_ZAURUS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=m
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=m
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_EVBUG=m
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_SUNKBD=m
+CONFIG_KEYBOARD_LKKBD=m
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEYBOARD_NEWTON=m
+CONFIG_KEYBOARD_STOWAWAY=m
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_SERIAL=m
+CONFIG_MOUSE_APPLETOUCH=m
+# CONFIG_MOUSE_BCM5974 is not set
+CONFIG_MOUSE_VSXXXAA=m
+CONFIG_MOUSE_GPIO=m
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=m
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=m
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_RAW=m
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_N_HDLC=m
+# CONFIG_RISCOM8 is not set
+CONFIG_SPECIALIX=m
+CONFIG_RIO=m
+# CONFIG_RIO_OLDPCI is not set
+CONFIG_STALDRV=y
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_IPMI_HANDLER=m
+# CONFIG_IPMI_PANIC_EVENT is not set
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_SI=m
+CONFIG_IPMI_WATCHDOG=m
+CONFIG_IPMI_POWEROFF=m
+CONFIG_HW_RANDOM=y
+CONFIG_NVRAM=m
+CONFIG_R3964=m
+CONFIG_RAW_DRIVER=m
+CONFIG_MAX_RAW_DEVS=256
+CONFIG_TCG_TPM=m
+CONFIG_TCG_NSC=m
+CONFIG_TCG_ATMEL=m
+CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
+#
+# I2C Hardware Bus support
+#
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+#
+# Miscellaneous I2C Chip support
+#
+CONFIG_DS1682=m
+# CONFIG_AT24 is not set
+CONFIG_SENSORS_EEPROM=m
+CONFIG_SENSORS_PCF8574=m
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+CONFIG_SENSORS_PCF8591=m
+CONFIG_SENSORS_MAX6875=m
+CONFIG_SENSORS_TSL2550=m
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+CONFIG_SPI_BITBANG=m
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_AT25=m
+CONFIG_SPI_SPIDEV=m
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+#
+# Multimedia devices
+#
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+# CONFIG_SND_PCM_OSS_PLUGINS is not set
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_SUPPORT_OLD_API=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_DUMMY=m
+CONFIG_SND_VIRMIDI=m
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+# CONFIG_SND_AT73C213 is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+#
+# USB HID Boot Protocol drivers
+#
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=m
+CONFIG_HID_APPLE=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_BRIGHT=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_DELL=m
+CONFIG_HID_EZKEY=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_LOGITECH=m
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_PANTHERLORD=m
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_HID_SUNPLUS=m
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_ISD200=y
+CONFIG_USB_STORAGE_DPCM=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_STORAGE_ALAUDA=y
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+CONFIG_USB_STORAGE_KARMA=y
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP2101 is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+CONFIG_USB_SERIAL_PL2303=m
+# CONFIG_USB_SERIAL_OTI6858 is not set
+CONFIG_USB_SERIAL_SPCP8X5=m
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+CONFIG_USB_SERIAL_DEBUG=m
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+CONFIG_USB_ADUTUX=m
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_TEST=m
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=m
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=m
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_MIDI_GADGET=m
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=m
+# CONFIG_MMC_TEST is not set
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_AT91=y
+CONFIG_MMC_SPI=m
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=m
+# CONFIG_LEDS_PCA955X is not set
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+# CONFIG_RTC_DRV_TEST is not set
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=m
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+CONFIG_RTC_DRV_DS1305=y
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_AT91SAM9 is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_JBD_DEBUG=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+CONFIG_REISERFS_CHECK=y
+CONFIG_REISERFS_PROC_INFO=y
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+CONFIG_GENERIC_ACL=y
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=m
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+# CONFIG_JFFS2_CMODE_PRIORITY is not set
+# CONFIG_JFFS2_CMODE_SIZE is not set
+CONFIG_JFFS2_CMODE_FAVOURLZO=y
+# CONFIG_UBIFS_FS is not set
+CONFIG_CRAMFS=m
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+CONFIG_SUNRPC_GSS=m
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+CONFIG_CIFS_WEAK_PW_HASH=y
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_LDM_PARTITION=y
+CONFIG_LDM_DEBUG=y
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+#
+# Tracers
+#
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=m
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_REED_SOLOMON=m
+CONFIG_REED_SOLOMON_DEC16=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index 610ac3c47b0f..9155196e623b 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.32-rc5
+# Linux kernel version: 2.6.33-rc2
-# Sat Oct 17 23:32:24 2009
+# Wed Jan  6 00:01:36 2010
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -46,6 +46,7 @@ CONFIG_SYSVIPC_SYSCTL=y
 #
 CONFIG_TREE_RCU=y
 # CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
 # CONFIG_RCU_TRACE is not set
 CONFIG_RCU_FANOUT=32
 # CONFIG_RCU_FANOUT_EXACT is not set
@@ -119,14 +120,41 @@ CONFIG_BLOCK=y
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
 CONFIG_IOSCHED_DEADLINE=y
 # CONFIG_IOSCHED_CFQ is not set
-# CONFIG_DEFAULT_AS is not set
 CONFIG_DEFAULT_DEADLINE=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
 # CONFIG_FREEZER is not set
 #
@@ -155,6 +183,7 @@ CONFIG_MMU=y
 # CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_DOVE is not set
 # CONFIG_ARCH_KIRKWOOD is not set
 # CONFIG_ARCH_LOKI is not set
 # CONFIG_ARCH_MV78XX0 is not set
@@ -177,6 +206,7 @@ CONFIG_ARCH_U300=y
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
 # CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_U8500 is not set
 #
 # ST-Ericsson AB U300/U330/U335/U365 Platform
@@ -265,12 +295,10 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
+CONFIG_SPLIT_PTLOCK_CPUS=999999
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
 # CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_ALIGNMENT_TRAP=y
@@ -499,14 +527,21 @@ CONFIG_MTD_NAND_IDS=y
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
 CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
 # CONFIG_ICS932S401 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
 # CONFIG_ISL29003 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
 # CONFIG_C2PORT is not set
 #
@@ -517,6 +552,7 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_LEGACY is not set
 # CONFIG_EEPROM_MAX6875 is not set
 # CONFIG_EEPROM_93CX6 is not set
+# CONFIG_IWMC3200TOP is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
@@ -539,6 +575,7 @@ CONFIG_HAVE_IDE=y
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
 # CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 #
 # Userland interfaces
@@ -645,7 +682,6 @@ CONFIG_I2C_STU300=y
 #
 # Miscellaneous I2C Chip support
 #
-# CONFIG_DS1682 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
@@ -661,6 +697,8 @@ CONFIG_SPI_MASTER=y
 # CONFIG_SPI_BITBANG is not set
 # CONFIG_SPI_GPIO is not set
 CONFIG_SPI_PL022=y
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
 #
 # SPI Protocol Masters
@@ -708,6 +746,7 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_T7L66XB is not set
 # CONFIG_MFD_TC6387XB is not set
 # CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM831X is not set
 # CONFIG_MFD_WM8350_I2C is not set
@@ -716,6 +755,8 @@ CONFIG_SSB_POSSIBLE=y
 CONFIG_AB3100_CORE=y
 CONFIG_AB3100_OTP=y
 # CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_88PM8607 is not set
+# CONFIG_AB4500_CORE is not set
 CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_DEBUG is not set
 # CONFIG_REGULATOR_FIXED_VOLTAGE is not set
@@ -723,6 +764,7 @@ CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
 # CONFIG_REGULATOR_BQ24022 is not set
 # CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
 # CONFIG_REGULATOR_LP3971 is not set
 CONFIG_REGULATOR_AB3100=y
 # CONFIG_REGULATOR_TPS65023 is not set
@@ -840,7 +882,9 @@ CONFIG_LEDS_CLASS=y
 # CONFIG_LEDS_LP3944 is not set
 # CONFIG_LEDS_PCA955X is not set
 # CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_REGULATOR is not set
 # CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
 #
 # LED Triggers
@@ -882,6 +926,7 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
 # CONFIG_RTC_DRV_RX8581 is not set
@@ -911,7 +956,9 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_M48T86 is not set
 # CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
 # CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 CONFIG_RTC_DRV_AB3100=y
@@ -926,6 +973,15 @@ CONFIG_DMADEVICES=y
 #
 # DMA Devices
 #
+CONFIG_COH901318=y
+CONFIG_DMA_ENGINE=y
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
@@ -1018,7 +1074,7 @@ CONFIG_MISC_FILESYSTEMS=y
 CONFIG_MSDOS_PARTITION=y
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
+CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_CODEPAGE_737 is not set
 # CONFIG_NLS_CODEPAGE_775 is not set
 # CONFIG_NLS_CODEPAGE_850 is not set
@@ -1135,6 +1191,7 @@ CONFIG_ARM_UNWIND=y
 # CONFIG_DEBUG_ERRORS is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_DEBUG_LL is not set
+# CONFIG_OC_ETM is not set
 #
 # Security options
@@ -1142,7 +1199,11 @@ CONFIG_ARM_UNWIND=y
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
 # CONFIG_CRYPTO is not set
 # CONFIG_BINARY_PRINTF is not set
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 730aefcfbee3..be8b4d79cf41 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -182,21 +182,6 @@
 *      DMA Cache Coherency
 *      ===================
 *
- *      dma_inv_range(start, end)
- *
- *              Invalidate (discard) the specified virtual address range.
- *              May not write back any entries.  If 'start' or 'end'
- *              are not cache line aligned, those lines must be written
- *              back.
- *              - start  - virtual start address
- *              - end    - virtual end address
- *
- *      dma_clean_range(start, end)
- *
- *              Clean (write back) the specified virtual address range.
- *              - start  - virtual start address
- *              - end    - virtual end address
- *
 *      dma_flush_range(start, end)
 *
 *              Clean and invalidate the specified virtual address range.
@@ -213,8 +198,9 @@ struct cpu_cache_fns {
        void (*coherent_user_range)(unsigned long, unsigned long);
        void (*flush_kern_dcache_area)(void *, size_t);
-        void (*dma_inv_range)(const void *, const void *);
+        void (*dma_map_area)(const void *, size_t, int);
-        void (*dma_clean_range)(const void *, const void *);
+        void (*dma_unmap_area)(const void *, size_t, int);
        void (*dma_flush_range)(const void *, const void *);
 };
@@ -244,8 +230,8 @@ extern struct cpu_cache_fns cpu_cache;
 * is visible to DMA, or data written by DMA to system memory is
 * visible to the CPU.
 */
-#define dmac_inv_range                  cpu_cache.dma_inv_range
+#define dmac_map_area                   cpu_cache.dma_map_area
-#define dmac_clean_range                cpu_cache.dma_clean_range
+#define dmac_unmap_area         cpu_cache.dma_unmap_area
 #define dmac_flush_range                cpu_cache.dma_flush_range
 #else
@@ -270,12 +256,12 @@ extern void __cpuc_flush_dcache_area(void *, size_t);
 * is visible to DMA, or data written by DMA to system memory is
 * visible to the CPU.
 */
-#define dmac_inv_range                  __glue(_CACHE,_dma_inv_range)
+#define dmac_map_area                   __glue(_CACHE,_dma_map_area)
-#define dmac_clean_range                __glue(_CACHE,_dma_clean_range)
+#define dmac_unmap_area         __glue(_CACHE,_dma_unmap_area)
 #define dmac_flush_range                __glue(_CACHE,_dma_flush_range)
-extern void dmac_inv_range(const void *, const void *);
+extern void dmac_map_area(const void *, size_t, int);
-extern void dmac_clean_range(const void *, const void *);
+extern void dmac_unmap_area(const void *, size_t, int);
 extern void dmac_flush_range(const void *, const void *);
 #endif
@@ -316,12 +302,8 @@ static inline void outer_flush_range(unsigned long start, unsigned long end)
 * processes address space.  Really, we want to allow our "user
 * space" model to handle this.
 */
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+extern void copy_to_user_page(struct vm_area_struct *, struct page *,
-        do {                                                    \
+        unsigned long, void *, const void *, unsigned long);
-                memcpy(dst, src, len);                          \
-                flush_ptrace_access(vma, page, vaddr, dst, len, 1);\
-        } while (0)
 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
        do {                                                    \
                memcpy(dst, src, len);                          \
@@ -355,17 +337,6 @@ vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
        }
 }
-static inline void
-vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
-                         unsigned long uaddr, void *kaddr,
-                         unsigned long len, int write)
-{
-        if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
-                unsigned long addr = (unsigned long)kaddr;
-                __cpuc_coherent_kern_range(addr, addr + len);
-        }
-}
 #ifndef CONFIG_CPU_CACHE_VIPT
 #define flush_cache_mm(mm) \
                vivt_flush_cache_mm(mm)
@@ -373,15 +344,10 @@ vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
                vivt_flush_cache_range(vma,start,end)
 #define flush_cache_page(vma,addr,pfn) \
                vivt_flush_cache_page(vma,addr,pfn)
-#define flush_ptrace_access(vma,page,ua,ka,len,write) \
-                vivt_flush_ptrace_access(vma,page,ua,ka,len,write)
 #else
 extern void flush_cache_mm(struct mm_struct *mm);
 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
-extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
-                                unsigned long uaddr, void *kaddr,
-                                unsigned long len, int write);
 #endif
 #define flush_cache_dup_mm(mm) flush_cache_mm(mm)
diff --git a/arch/arm/include/asm/cpu.h b/arch/arm/include/asm/cpu.h
index 634b2d7c612a..793968173bef 100644
--- a/arch/arm/include/asm/cpu.h
+++ b/arch/arm/include/asm/cpu.h
@@ -11,6 +11,7 @@
 #define __ASM_ARM_CPU_H
 #include <linux/percpu.h>
+#include <linux/cpu.h>
 struct cpuinfo_arm {
        struct cpu      cpu;
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index a96300bf83fd..256ee1c9f51a 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -57,18 +57,58 @@ static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
 #endif
 /*
- * DMA-consistent mapping functions.  These allocate/free a region of
+ * The DMA API is built upon the notion of "buffer ownership".  A buffer
- * uncached, unwrite-buffered mapped memory space for use with DMA
+ * is either exclusively owned by the CPU (and therefore may be accessed
- * devices.  This is the "generic" version.  The PCI specific version
+ * by it) or exclusively owned by the DMA device.  These helper functions
- * is in pci.h
+ * represent the transitions between these two ownership states.
 *
- * Note: Drivers should NOT use this function directly, as it will break
+ * Note, however, that on later ARMs, this notion does not work due to
- * platforms with CONFIG_DMABOUNCE.
+ * speculative prefetches.  We model our approach on the assumption that
- * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
+ * the CPU does do speculative prefetches, which means we clean caches
+ * before transfers and delay cache invalidation until transfer completion.
+ *
+ * Private support functions: these are not part of the API and are
+ * liable to change.  Drivers must not use these.
 */
-extern void dma_cache_maint(const void *kaddr, size_t size, int rw);
+static inline void __dma_single_cpu_to_dev(const void *kaddr, size_t size,
-extern void dma_cache_maint_page(struct page *page, unsigned long offset,
+        enum dma_data_direction dir)
-                                 size_t size, int rw);
+{
+        extern void ___dma_single_cpu_to_dev(const void *, size_t,
+                enum dma_data_direction);
+        if (!arch_is_coherent())
+                ___dma_single_cpu_to_dev(kaddr, size, dir);
+}
+static inline void __dma_single_dev_to_cpu(const void *kaddr, size_t size,
+        enum dma_data_direction dir)
+{
+        extern void ___dma_single_dev_to_cpu(const void *, size_t,
+                enum dma_data_direction);
+        if (!arch_is_coherent())
+                ___dma_single_dev_to_cpu(kaddr, size, dir);
+}
+static inline void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
+        size_t size, enum dma_data_direction dir)
+{
+        extern void ___dma_page_cpu_to_dev(struct page *, unsigned long,
+                size_t, enum dma_data_direction);
+        if (!arch_is_coherent())
+                ___dma_page_cpu_to_dev(page, off, size, dir);
+}
+static inline void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
+        size_t size, enum dma_data_direction dir)
+{
+        extern void ___dma_page_dev_to_cpu(struct page *, unsigned long,
+                size_t, enum dma_data_direction);
+        if (!arch_is_coherent())
+                ___dma_page_dev_to_cpu(page, off, size, dir);
+}
 /*
 * Return whether the given device DMA address mask can be supported
@@ -304,8 +344,7 @@ static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
 {
        BUG_ON(!valid_dma_direction(dir));
-        if (!arch_is_coherent())
+        __dma_single_cpu_to_dev(cpu_addr, size, dir);
-                dma_cache_maint(cpu_addr, size, dir);
        return virt_to_dma(dev, cpu_addr);
 }
@@ -329,8 +368,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
 {
        BUG_ON(!valid_dma_direction(dir));
-        if (!arch_is_coherent())
+        __dma_page_cpu_to_dev(page, offset, size, dir);
-                dma_cache_maint_page(page, offset, size, dir);
        return page_to_dma(dev, page) + offset;
 }
@@ -352,7 +390,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
 static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
                size_t size, enum dma_data_direction dir)
 {
-        /* nothing to do */
+        __dma_single_dev_to_cpu(dma_to_virt(dev, handle), size, dir);
 }
 /**
@@ -372,7 +410,8 @@ static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
 static inline void dma_unmap_page(struct device *dev, dma_addr_t handle,
                size_t size, enum dma_data_direction dir)
 {
-        /* nothing to do */
+        __dma_page_dev_to_cpu(dma_to_page(dev, handle), handle & ~PAGE_MASK,
+                size, dir);
 }
 #endif /* CONFIG_DMABOUNCE */
@@ -400,7 +439,10 @@ static inline void dma_sync_single_range_for_cpu(struct device *dev,
 {
        BUG_ON(!valid_dma_direction(dir));
-        dmabounce_sync_for_cpu(dev, handle, offset, size, dir);
+        if (!dmabounce_sync_for_cpu(dev, handle, offset, size, dir))
+                return;
+        __dma_single_dev_to_cpu(dma_to_virt(dev, handle) + offset, size, dir);
 }
 static inline void dma_sync_single_range_for_device(struct device *dev,
@@ -412,8 +454,7 @@ static inline void dma_sync_single_range_for_device(struct device *dev,
        if (!dmabounce_sync_for_device(dev, handle, offset, size, dir))
                return;
-        if (!arch_is_coherent())
+        __dma_single_cpu_to_dev(dma_to_virt(dev, handle) + offset, size, dir);
-                dma_cache_maint(dma_to_virt(dev, handle) + offset, size, dir);
 }
 static inline void dma_sync_single_for_cpu(struct device *dev,
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 7edf3536df24..ca51143f97f1 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -138,12 +138,12 @@ extern int  get_dma_residue(unsigned int chan);
 #define NO_DMA  255
 #endif
+#endif /* CONFIG_ISA_DMA_API */
 #ifdef CONFIG_PCI
 extern int isa_dma_bridge_buggy;
 #else
 #define isa_dma_bridge_buggy    (0)
 #endif
-#endif /* CONFIG_ISA_DMA_API */
 #endif /* __ASM_ARM_DMA_H */
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index 3a32af4cce30..a485ac3c8696 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -117,11 +117,12 @@
 #endif
 struct page;
+struct vm_area_struct;
 struct cpu_user_fns {
        void (*cpu_clear_user_highpage)(struct page *page, unsigned long vaddr);
        void (*cpu_copy_user_highpage)(struct page *to, struct page *from,
-                        unsigned long vaddr);
+                        unsigned long vaddr, struct vm_area_struct *vma);
 };
 #ifdef MULTI_USER
@@ -137,7 +138,7 @@ extern struct cpu_user_fns cpu_user;
 extern void __cpu_clear_user_highpage(struct page *page, unsigned long vaddr);
 extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
-                        unsigned long vaddr);
+                        unsigned long vaddr, struct vm_area_struct *vma);
 #endif
 #define clear_user_highpage(page,vaddr)         \
@@ -145,7 +146,7 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
 #define __HAVE_ARCH_COPY_USER_HIGHPAGE
 #define copy_user_highpage(to,from,vaddr,vma)   \
-        __cpu_copy_user_highpage(to, from, vaddr)
+        __cpu_copy_user_highpage(to, from, vaddr, vma)
 #define clear_page(page)        memset((void *)(page), 0, PAGE_SIZE)
 extern void copy_page(void *to, const void *from);
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index bbecccda76d0..eec6e897ceb2 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -97,9 +97,15 @@
 * stack during a system call.  Note that sizeof(struct pt_regs)
 * has to be a multiple of 8.
 */
+#ifndef __KERNEL__
 struct pt_regs {
        long uregs[18];
 };
+#else /* __KERNEL__ */
+struct pt_regs {
+        unsigned long uregs[18];
+};
+#endif /* __KERNEL__ */
 #define ARM_cpsr        uregs[16]
 #define ARM_pc          uregs[15]
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 59303e200845..e6215305544a 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -13,4 +13,9 @@ static inline int tlb_ops_need_broadcast(void)
        return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
 }
+static inline int cache_ops_need_broadcast(void)
+{
+        return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
+}
 #endif
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index c2f1605de359..e085e2c545eb 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -529,7 +529,8 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 * cache entries for the kernels virtual memory range are written
 * back to the page.
 */
-extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte);
+extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
+        pte_t *ptep);
 #endif
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 4e506d09e5f9..cf9cdaa2d4d4 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -391,6 +391,7 @@
 #define __NR_pwritev                    (__NR_SYSCALL_BASE+362)
 #define __NR_rt_tgsigqueueinfo          (__NR_SYSCALL_BASE+363)
 #define __NR_perf_event_open            (__NR_SYSCALL_BASE+364)
+#define __NR_recvmmsg                   (__NR_SYSCALL_BASE+365)
 /*
 * The following SWIs are ARM private.
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 4a881258bb17..883511522fca 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -12,6 +12,7 @@
 */
 #include <linux/sched.h>
 #include <linux/mm.h>
+#include <linux/dma-mapping.h>
 #include <asm/mach/arch.h>
 #include <asm/thread_info.h>
 #include <asm/memory.h>
@@ -112,5 +113,9 @@ int main(void)
 #ifdef MULTI_PABORT
  DEFINE(PROCESSOR_PABT_FUNC,   offsetof(struct processor, _prefetch_abort));
 #endif
+  BLANK();
+  DEFINE(DMA_BIDIRECTIONAL,     DMA_BIDIRECTIONAL);
+  DEFINE(DMA_TO_DEVICE,         DMA_TO_DEVICE);
+  DEFINE(DMA_FROM_DEVICE,       DMA_FROM_DEVICE);
  return 0; 
 }
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index d2903e3bc861..6c5cf369183b 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -957,9 +957,7 @@ kuser_cmpxchg_fixup:
 #else
-#ifdef CONFIG_SMP
+        smp_dmb
-        mcr     p15, 0, r0, c7, c10, 5  @ dmb
-#endif
 1:      ldrex   r3, [r2]
        subs    r3, r3, r0
        strexeq r3, r1, [r2]
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 67304138a2ca..ba2adefa53f7 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -212,7 +212,8 @@ void __show_regs(struct pt_regs *regs)
        char buf[64];
        printk("CPU: %d    %s  (%s %.*s)\n",
-                smp_processor_id(), print_tainted(), init_utsname()->release,
+                raw_smp_processor_id(), print_tainted(),
+                init_utsname()->release,
                (int)strcspn(init_utsname()->version, " "),
                init_utsname()->version);
        print_symbol("PC is at %s\n", instruction_pointer(regs));
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 0b2ee953f164..2db43a5ddd9b 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -89,6 +89,12 @@ config ARCH_AT91CAP9
        select GENERIC_CLOCKEVENTS
        select HAVE_FB_ATMEL
+config ARCH_AT572D940HF
+        bool "AT572D940HF"
+        select CPU_ARM926T
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
 config ARCH_AT91X40
        bool "AT91x40"
@@ -390,6 +396,23 @@ endif
 # ----------------------------------------------------------
+if ARCH_AT572D940HF
+comment "AT572D940HF Board Type"
+config MACH_AT572D940HFEB
+        bool "AT572D940HF-EK"
+        depends on ARCH_AT572D940HF
+        select HAVE_AT91_DATAFLASH_CARD
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
+        help
+          Select this if you are using Atmel's AT572D940HF-EK evaluation kit.
+          <http://www.atmel.com/products/diopsis/default.asp>
+endif
+# ----------------------------------------------------------
 if ARCH_AT91X40
 comment "AT91X40 Board Type"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 709fbad4a3ee..027dd570dcc3 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_AT91SAM9RL)	+= at91sam9rl.o at91sam926x_time.o at91sam9rl_devi
 obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o  sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91CAP9)     += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT572D940HF)  += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91X40)      += at91x40.o at91x40_time.o
 # AT91RM9200 board-specific support
@@ -69,6 +70,9 @@ obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
 # AT91CAP9 board-specific support
 obj-$(CONFIG_MACH_AT91CAP9ADK)  += board-cap9adk.o
+# AT572D940HF board-specific support
+obj-$(CONFIG_MACH_AT572D940HFEB) += board-at572d940hf_ek.o
 # AT91X40 board-specific support
 obj-$(CONFIG_MACH_AT91EB01)     += board-eb01.o
diff --git a/arch/arm/mach-at91/at572d940hf.c b/arch/arm/mach-at91/at572d940hf.c
new file mode 100644
index 000000000000..a6b9c68c003a
--- /dev/null
+++ b/arch/arm/mach-at91/at572d940hf.c
@@ -0,0 +1,377 @@
+/*
+ * arch/arm/mach-at91/at572d940hf.c
+ *
+ * Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2008 Atmel
+ *
+ * Copyright (C) 2005 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include <linux/module.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/at572d940hf.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91_rstc.h>
+#include "generic.h"
+#include "clock.h"
+static struct map_desc at572d940hf_io_desc[] __initdata = {
+        {
+                .virtual        = AT91_VA_BASE_SYS,
+                .pfn            = __phys_to_pfn(AT91_BASE_SYS),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_IO_VIRT_BASE - AT572D940HF_SRAM_SIZE,
+                .pfn            = __phys_to_pfn(AT572D940HF_SRAM_BASE),
+                .length         = AT572D940HF_SRAM_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+/*
+ * The peripheral clocks.
+ */
+static struct clk pioA_clk = {
+        .name           = "pioA_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_PIOA,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioB_clk = {
+        .name           = "pioB_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_PIOB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioC_clk = {
+        .name           = "pioC_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_PIOC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk macb_clk = {
+        .name           = "macb_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_EMAC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+        .name           = "usart0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_US0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart1_clk = {
+        .name           = "usart1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_US1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart2_clk = {
+        .name           = "usart2_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_US2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc_clk = {
+        .name           = "mci_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_MCI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udc_clk = {
+        .name           = "udc_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_UDP,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi0_clk = {
+        .name           = "twi0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_TWI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+        .name           = "spi0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SPI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+        .name           = "spi1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SPI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc0_clk = {
+        .name           = "ssc0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SSC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc1_clk = {
+        .name           = "ssc1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SSC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc2_clk = {
+        .name           = "ssc2_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SSC2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc0_clk = {
+        .name           = "tc0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_TC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc1_clk = {
+        .name           = "tc1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_TC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc2_clk = {
+        .name           = "tc2_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_TC2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ohci_clk = {
+        .name           = "ohci_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_UHP,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc3_clk = {
+        .name           = "ssc3_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SSC3,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi1_clk = {
+        .name           = "twi1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_TWI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk can0_clk = {
+        .name           = "can0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_CAN0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk can1_clk = {
+        .name           = "can1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_CAN1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mAgicV_clk = {
+        .name           = "mAgicV_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_MSIRQ0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk *periph_clocks[] __initdata = {
+        &pioA_clk,
+        &pioB_clk,
+        &pioC_clk,
+        &macb_clk,
+        &usart0_clk,
+        &usart1_clk,
+        &usart2_clk,
+        &mmc_clk,
+        &udc_clk,
+        &twi0_clk,
+        &spi0_clk,
+        &spi1_clk,
+        &ssc0_clk,
+        &ssc1_clk,
+        &ssc2_clk,
+        &tc0_clk,
+        &tc1_clk,
+        &tc2_clk,
+        &ohci_clk,
+        &ssc3_clk,
+        &twi1_clk,
+        &can0_clk,
+        &can1_clk,
+        &mAgicV_clk,
+        /* irq0 .. irq2 */
+};
+/*
+ * The five programmable clocks.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+        .name           = "pck0",
+        .pmc_mask       = AT91_PMC_PCK0,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 0,
+};
+static struct clk pck1 = {
+        .name           = "pck1",
+        .pmc_mask       = AT91_PMC_PCK1,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 1,
+};
+static struct clk pck2 = {
+        .name           = "pck2",
+        .pmc_mask       = AT91_PMC_PCK2,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 2,
+};
+static struct clk pck3 = {
+        .name           = "pck3",
+        .pmc_mask       = AT91_PMC_PCK3,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 3,
+};
+static struct clk mAgicV_mem_clk = {
+        .name           = "mAgicV_mem_clk",
+        .pmc_mask       = AT91_PMC_PCK4,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 4,
+};
+/* HClocks */
+static struct clk hck0 = {
+        .name           = "hck0",
+        .pmc_mask       = AT91_PMC_HCK0,
+        .type           = CLK_TYPE_SYSTEM,
+        .id             = 0,
+};
+static struct clk hck1 = {
+        .name           = "hck1",
+        .pmc_mask       = AT91_PMC_HCK1,
+        .type           = CLK_TYPE_SYSTEM,
+        .id             = 1,
+};
+static void __init at572d940hf_register_clocks(void)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+                clk_register(periph_clocks[i]);
+        clk_register(&pck0);
+        clk_register(&pck1);
+        clk_register(&pck2);
+        clk_register(&pck3);
+        clk_register(&mAgicV_mem_clk);
+        clk_register(&hck0);
+        clk_register(&hck1);
+}
+/* --------------------------------------------------------------------
+ *  GPIO
+ * -------------------------------------------------------------------- */
+static struct at91_gpio_bank at572d940hf_gpio[] = {
+        {
+                .id             = AT572D940HF_ID_PIOA,
+                .offset         = AT91_PIOA,
+                .clock          = &pioA_clk,
+        }, {
+                .id             = AT572D940HF_ID_PIOB,
+                .offset         = AT91_PIOB,
+                .clock          = &pioB_clk,
+        }, {
+                .id             = AT572D940HF_ID_PIOC,
+                .offset         = AT91_PIOC,
+                .clock          = &pioC_clk,
+        }
+};
+static void at572d940hf_reset(void)
+{
+        at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
+}
+/* --------------------------------------------------------------------
+ *  AT572D940HF processor initialization
+ * -------------------------------------------------------------------- */
+void __init at572d940hf_initialize(unsigned long main_clock)
+{
+        /* Map peripherals */
+        iotable_init(at572d940hf_io_desc, ARRAY_SIZE(at572d940hf_io_desc));
+        at91_arch_reset = at572d940hf_reset;
+        at91_extern_irq = (1 << AT572D940HF_ID_IRQ0) | (1 << AT572D940HF_ID_IRQ1)
+                        | (1 << AT572D940HF_ID_IRQ2);
+        /* Init clock subsystem */
+        at91_clock_init(main_clock);
+        /* Register the processor-specific clocks */
+        at572d940hf_register_clocks();
+        /* Register GPIO subsystem */
+        at91_gpio_init(at572d940hf_gpio, 3);
+}
+/* --------------------------------------------------------------------
+ *  Interrupt initialization
+ * -------------------------------------------------------------------- */
+/*
+ * The default interrupt priority levels (0 = lowest, 7 = highest).
+ */
+static unsigned int at572d940hf_default_irq_priority[NR_AIC_IRQS] __initdata = {
+        7,      /* Advanced Interrupt Controller */
+        7,      /* System Peripherals */
+        0,      /* Parallel IO Controller A */
+        0,      /* Parallel IO Controller B */
+        0,      /* Parallel IO Controller C */
+        3,      /* Ethernet */
+        6,      /* USART 0 */
+        6,      /* USART 1 */
+        6,      /* USART 2 */
+        0,      /* Multimedia Card Interface */
+        4,      /* USB Device Port */
+        0,      /* Two-Wire Interface 0 */
+        6,      /* Serial Peripheral Interface 0 */
+        6,      /* Serial Peripheral Interface 1 */
+        5,      /* Serial Synchronous Controller 0 */
+        5,      /* Serial Synchronous Controller 1 */
+        5,      /* Serial Synchronous Controller 2 */
+        0,      /* Timer Counter 0 */
+        0,      /* Timer Counter 1 */
+        0,      /* Timer Counter 2 */
+        3,      /* USB Host port */
+        3,      /* Serial Synchronous Controller 3 */
+        0,      /* Two-Wire Interface 1 */
+        0,      /* CAN Controller 0 */
+        0,      /* CAN Controller 1 */
+        0,      /* mAgicV HALT line */
+        0,      /* mAgicV SIRQ0 line */
+        0,      /* mAgicV exception line */
+        0,      /* mAgicV end of DMA line */
+        0,      /* Advanced Interrupt Controller */
+        0,      /* Advanced Interrupt Controller */
+        0,      /* Advanced Interrupt Controller */
+};
+void __init at572d940hf_init_interrupts(unsigned int priority[NR_AIC_IRQS])
+{
+        if (!priority)
+                priority = at572d940hf_default_irq_priority;
+        /* Initialize the AIC interrupt controller */
+        at91_aic_init(priority);
+        /* Enable GPIO interrupts */
+        at91_gpio_irq_setup();
+}
diff --git a/arch/arm/mach-at91/at572d940hf_devices.c b/arch/arm/mach-at91/at572d940hf_devices.c
new file mode 100644
index 000000000000..0fc20a240782
--- /dev/null
+++ b/arch/arm/mach-at91/at572d940hf_devices.c
@@ -0,0 +1,970 @@
+/*
+ * arch/arm/mach-at91/at572d940hf_devices.c
+ *
+ * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
+ * Copyright (C) 2005 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at572d940hf.h>
+#include <mach/at572d940hf_matrix.h>
+#include <mach/at91sam9_smc.h>
+#include "generic.h"
+#include "sam9_smc.h"
+/* --------------------------------------------------------------------
+ *  USB Host
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static u64 ohci_dmamask = DMA_BIT_MASK(32);
+static struct at91_usbh_data usbh_data;
+static struct resource usbh_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_UHP_BASE,
+                .end    = AT572D940HF_UHP_BASE + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_UHP,
+                .end    = AT572D940HF_ID_UHP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at572d940hf_usbh_device = {
+        .name           = "at91_ohci",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &ohci_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &usbh_data,
+        },
+        .resource       = usbh_resources,
+        .num_resources  = ARRAY_SIZE(usbh_resources),
+};
+void __init at91_add_device_usbh(struct at91_usbh_data *data)
+{
+        if (!data)
+                return;
+        usbh_data = *data;
+        platform_device_register(&at572d940hf_usbh_device);
+}
+#else
+void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
+#endif
+/* --------------------------------------------------------------------
+ *  USB Device (Gadget)
+ * -------------------------------------------------------------------- */
+#ifdef CONFIG_USB_GADGET_AT91
+static struct at91_udc_data udc_data;
+static struct resource udc_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_UDP,
+                .end    = AT572D940HF_BASE_UDP + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_UDP,
+                .end    = AT572D940HF_ID_UDP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at572d940hf_udc_device = {
+        .name           = "at91_udc",
+        .id             = -1,
+        .dev            = {
+                                .platform_data          = &udc_data,
+        },
+        .resource       = udc_resources,
+        .num_resources  = ARRAY_SIZE(udc_resources),
+};
+void __init at91_add_device_udc(struct at91_udc_data *data)
+{
+        if (!data)
+                return;
+        if (data->vbus_pin) {
+                at91_set_gpio_input(data->vbus_pin, 0);
+                at91_set_deglitch(data->vbus_pin, 1);
+        }
+        /* Pullup pin is handled internally */
+        udc_data = *data;
+        platform_device_register(&at572d940hf_udc_device);
+}
+#else
+void __init at91_add_device_udc(struct at91_udc_data *data) {}
+#endif
+/* --------------------------------------------------------------------
+ *  Ethernet
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
+static u64 eth_dmamask = DMA_BIT_MASK(32);
+static struct at91_eth_data eth_data;
+static struct resource eth_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_EMAC,
+                .end    = AT572D940HF_BASE_EMAC + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_EMAC,
+                .end    = AT572D940HF_ID_EMAC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at572d940hf_eth_device = {
+        .name           = "macb",
+        .id             = -1,
+        .dev            = {
+                        .dma_mask               = &eth_dmamask,
+                        .coherent_dma_mask      = DMA_BIT_MASK(32),
+                        .platform_data          = &eth_data,
+        },
+        .resource       = eth_resources,
+        .num_resources  = ARRAY_SIZE(eth_resources),
+};
+void __init at91_add_device_eth(struct at91_eth_data *data)
+{
+        if (!data)
+                return;
+        if (data->phy_irq_pin) {
+                at91_set_gpio_input(data->phy_irq_pin, 0);
+                at91_set_deglitch(data->phy_irq_pin, 1);
+        }
+        /* Only RMII is supported */
+        data->is_rmii = 1;
+        /* Pins used for RMII */
+        at91_set_A_periph(AT91_PIN_PA16, 0);    /* ETXCK_EREFCK */
+        at91_set_A_periph(AT91_PIN_PA17, 0);    /* ERXDV */
+        at91_set_A_periph(AT91_PIN_PA18, 0);    /* ERX0 */
+        at91_set_A_periph(AT91_PIN_PA19, 0);    /* ERX1 */
+        at91_set_A_periph(AT91_PIN_PA20, 0);    /* ERXER */
+        at91_set_A_periph(AT91_PIN_PA23, 0);    /* ETXEN */
+        at91_set_A_periph(AT91_PIN_PA21, 0);    /* ETX0 */
+        at91_set_A_periph(AT91_PIN_PA22, 0);    /* ETX1 */
+        at91_set_A_periph(AT91_PIN_PA13, 0);    /* EMDIO */
+        at91_set_A_periph(AT91_PIN_PA14, 0);    /* EMDC */
+        eth_data = *data;
+        platform_device_register(&at572d940hf_eth_device);
+}
+#else
+void __init at91_add_device_eth(struct at91_eth_data *data) {}
+#endif
+/* --------------------------------------------------------------------
+ *  MMC / SD
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
+static u64 mmc_dmamask = DMA_BIT_MASK(32);
+static struct at91_mmc_data mmc_data;
+static struct resource mmc_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_MCI,
+                .end    = AT572D940HF_BASE_MCI + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_MCI,
+                .end    = AT572D940HF_ID_MCI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at572d940hf_mmc_device = {
+        .name           = "at91_mci",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &mmc_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &mmc_data,
+        },
+        .resource       = mmc_resources,
+        .num_resources  = ARRAY_SIZE(mmc_resources),
+};
+void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
+{
+        if (!data)
+                return;
+        /* input/irq */
+        if (data->det_pin) {
+                at91_set_gpio_input(data->det_pin, 1);
+                at91_set_deglitch(data->det_pin, 1);
+        }
+        if (data->wp_pin)
+                at91_set_gpio_input(data->wp_pin, 1);
+        if (data->vcc_pin)
+                at91_set_gpio_output(data->vcc_pin, 0);
+        /* CLK */
+        at91_set_A_periph(AT91_PIN_PC22, 0);
+        /* CMD */
+        at91_set_A_periph(AT91_PIN_PC23, 1);
+        /* DAT0, maybe DAT1..DAT3 */
+        at91_set_A_periph(AT91_PIN_PC24, 1);
+        if (data->wire4) {
+                at91_set_A_periph(AT91_PIN_PC25, 1);
+                at91_set_A_periph(AT91_PIN_PC26, 1);
+                at91_set_A_periph(AT91_PIN_PC27, 1);
+        }
+        mmc_data = *data;
+        platform_device_register(&at572d940hf_mmc_device);
+}
+#else
+void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
+#endif
+/* --------------------------------------------------------------------
+ *  NAND / SmartMedia
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
+static struct atmel_nand_data nand_data;
+#define NAND_BASE       AT91_CHIPSELECT_3
+static struct resource nand_resources[] = {
+        {
+                .start  = NAND_BASE,
+                .end    = NAND_BASE + SZ_256M - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device at572d940hf_nand_device = {
+        .name           = "atmel_nand",
+        .id             = -1,
+        .dev            = {
+                                .platform_data  = &nand_data,
+        },
+        .resource       = nand_resources,
+        .num_resources  = ARRAY_SIZE(nand_resources),
+};
+void __init at91_add_device_nand(struct atmel_nand_data *data)
+{
+        unsigned long csa;
+        if (!data)
+                return;
+        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+        /* enable pin */
+        if (data->enable_pin)
+                at91_set_gpio_output(data->enable_pin, 1);
+        /* ready/busy pin */
+        if (data->rdy_pin)
+                at91_set_gpio_input(data->rdy_pin, 1);
+        /* card detect pin */
+        if (data->det_pin)
+                at91_set_gpio_input(data->det_pin, 1);
+        at91_set_A_periph(AT91_PIN_PB28, 0);            /* A[22] */
+        at91_set_B_periph(AT91_PIN_PA28, 0);            /* NANDOE */
+        at91_set_B_periph(AT91_PIN_PA29, 0);            /* NANDWE */
+        nand_data = *data;
+        platform_device_register(&at572d940hf_nand_device);
+}
+#else
+void __init at91_add_device_nand(struct atmel_nand_data *data) {}
+#endif
+/* --------------------------------------------------------------------
+ *  TWI (i2c)
+ * -------------------------------------------------------------------- */
+/*
+ * Prefer the GPIO code since the TWI controller isn't robust
+ * (gets overruns and underruns under load) and can only issue
+ * repeated STARTs in one scenario (the driver doesn't yet handle them).
+ */
+#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+static struct i2c_gpio_platform_data pdata = {
+        .sda_pin                = AT91_PIN_PC7,
+        .sda_is_open_drain      = 1,
+        .scl_pin                = AT91_PIN_PC8,
+        .scl_is_open_drain      = 1,
+        .udelay                 = 2,            /* ~100 kHz */
+};
+static struct platform_device at572d940hf_twi_device {
+        .name                   = "i2c-gpio",
+        .id                     = -1,
+        .dev.platform_data      = &pdata,
+};
+void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
+{
+        at91_set_GPIO_periph(AT91_PIN_PC7, 1);          /* TWD (SDA) */
+        at91_set_multi_drive(AT91_PIN_PC7, 1);
+        at91_set_GPIO_periph(AT91_PIN_PA8, 1);          /* TWCK (SCL) */
+        at91_set_multi_drive(AT91_PIN_PC8, 1);
+        i2c_register_board_info(0, devices, nr_devices);
+        platform_device_register(&at572d940hf_twi_device);
+}
+#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
+static struct resource twi0_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_TWI0,
+                .end    = AT572D940HF_BASE_TWI0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_TWI0,
+                .end    = AT572D940HF_ID_TWI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at572d940hf_twi0_device = {
+        .name           = "at91_i2c",
+        .id             = 0,
+        .resource       = twi0_resources,
+        .num_resources  = ARRAY_SIZE(twi0_resources),
+};
+static struct resource twi1_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_TWI1,
+                .end    = AT572D940HF_BASE_TWI1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_TWI1,
+                .end    = AT572D940HF_ID_TWI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at572d940hf_twi1_device = {
+        .name           = "at91_i2c",
+        .id             = 1,
+        .resource       = twi1_resources,
+        .num_resources  = ARRAY_SIZE(twi1_resources),
+};
+void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
+{
+        /* pins used for TWI0 interface */
+        at91_set_A_periph(AT91_PIN_PC7, 0);             /* TWD */
+        at91_set_multi_drive(AT91_PIN_PC7, 1);
+        at91_set_A_periph(AT91_PIN_PC8, 0);             /* TWCK */
+        at91_set_multi_drive(AT91_PIN_PC8, 1);
+        /* pins used for TWI1 interface */
+        at91_set_A_periph(AT91_PIN_PC20, 0);            /* TWD */
+        at91_set_multi_drive(AT91_PIN_PC20, 1);
+        at91_set_A_periph(AT91_PIN_PC21, 0);            /* TWCK */
+        at91_set_multi_drive(AT91_PIN_PC21, 1);
+        i2c_register_board_info(0, devices, nr_devices);
+        platform_device_register(&at572d940hf_twi0_device);
+        platform_device_register(&at572d940hf_twi1_device);
+}
+#else
+void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
+#endif
+/* --------------------------------------------------------------------
+ *  SPI
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+static struct resource spi0_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_SPI0,
+                .end    = AT572D940HF_BASE_SPI0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_SPI0,
+                .end    = AT572D940HF_ID_SPI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at572d940hf_spi0_device = {
+        .name           = "atmel_spi",
+        .id             = 0,
+        .dev            = {
+                                .dma_mask               = &spi_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = spi0_resources,
+        .num_resources  = ARRAY_SIZE(spi0_resources),
+};
+static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
+static struct resource spi1_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_SPI1,
+                .end    = AT572D940HF_BASE_SPI1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_SPI1,
+                .end    = AT572D940HF_ID_SPI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at572d940hf_spi1_device = {
+        .name           = "atmel_spi",
+        .id             = 1,
+        .dev            = {
+                                .dma_mask               = &spi_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = spi1_resources,
+        .num_resources  = ARRAY_SIZE(spi1_resources),
+};
+static const unsigned spi1_standard_cs[4] = { AT91_PIN_PC3, AT91_PIN_PC4, AT91_PIN_PC5, AT91_PIN_PC6 };
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
+{
+        int i;
+        unsigned long cs_pin;
+        short enable_spi0 = 0;
+        short enable_spi1 = 0;
+        /* Choose SPI chip-selects */
+        for (i = 0; i < nr_devices; i++) {
+                if (devices[i].controller_data)
+                        cs_pin = (unsigned long) devices[i].controller_data;
+                else if (devices[i].bus_num == 0)
+                        cs_pin = spi0_standard_cs[devices[i].chip_select];
+                else
+                        cs_pin = spi1_standard_cs[devices[i].chip_select];
+                if (devices[i].bus_num == 0)
+                        enable_spi0 = 1;
+                else
+                        enable_spi1 = 1;
+                /* enable chip-select pin */
+                at91_set_gpio_output(cs_pin, 1);
+                /* pass chip-select pin to driver */
+                devices[i].controller_data = (void *) cs_pin;
+        }
+        spi_register_board_info(devices, nr_devices);
+        /* Configure SPI bus(es) */
+        if (enable_spi0) {
+                at91_set_A_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
+                at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
+                at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
+                at91_clock_associate("spi0_clk", &at572d940hf_spi0_device.dev, "spi_clk");
+                platform_device_register(&at572d940hf_spi0_device);
+        }
+        if (enable_spi1) {
+                at91_set_A_periph(AT91_PIN_PC0, 0);     /* SPI1_MISO */
+                at91_set_A_periph(AT91_PIN_PC1, 0);     /* SPI1_MOSI */
+                at91_set_A_periph(AT91_PIN_PC2, 0);     /* SPI1_SPCK */
+                at91_clock_associate("spi1_clk", &at572d940hf_spi1_device.dev, "spi_clk");
+                platform_device_register(&at572d940hf_spi1_device);
+        }
+}
+#else
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
+#endif
+/* --------------------------------------------------------------------
+ *  Timer/Counter blocks
+ * -------------------------------------------------------------------- */
+#ifdef CONFIG_ATMEL_TCLIB
+static struct resource tcb_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_TCB,
+                .end    = AT572D940HF_BASE_TCB + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_TC0,
+                .end    = AT572D940HF_ID_TC0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AT572D940HF_ID_TC1,
+                .end    = AT572D940HF_ID_TC1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = AT572D940HF_ID_TC2,
+                .end    = AT572D940HF_ID_TC2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at572d940hf_tcb_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb_resources,
+        .num_resources  = ARRAY_SIZE(tcb_resources),
+};
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has a separate clock and irq for each TC channel */
+        at91_clock_associate("tc0_clk", &at572d940hf_tcb_device.dev, "t0_clk");
+        at91_clock_associate("tc1_clk", &at572d940hf_tcb_device.dev, "t1_clk");
+        at91_clock_associate("tc2_clk", &at572d940hf_tcb_device.dev, "t2_clk");
+        platform_device_register(&at572d940hf_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+/* --------------------------------------------------------------------
+ *  RTT
+ * -------------------------------------------------------------------- */
+static struct resource rtt_resources[] = {
+        {
+                .start  = AT91_BASE_SYS + AT91_RTT,
+                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device at572d940hf_rtt_device = {
+        .name           = "at91_rtt",
+        .id             = 0,
+        .resource       = rtt_resources,
+        .num_resources  = ARRAY_SIZE(rtt_resources),
+};
+static void __init at91_add_device_rtt(void)
+{
+        platform_device_register(&at572d940hf_rtt_device);
+}
+/* --------------------------------------------------------------------
+ *  Watchdog
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
+static struct platform_device at572d940hf_wdt_device = {
+        .name           = "at91_wdt",
+        .id             = -1,
+        .num_resources  = 0,
+};
+static void __init at91_add_device_watchdog(void)
+{
+        platform_device_register(&at572d940hf_wdt_device);
+}
+#else
+static void __init at91_add_device_watchdog(void) {}
+#endif
+/* --------------------------------------------------------------------
+ *  UART
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_SERIAL_ATMEL)
+static struct resource dbgu_resources[] = {
+        [0] = {
+                .start  = AT91_VA_BASE_SYS + AT91_DBGU,
+                .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_ID_SYS,
+                .end    = AT91_ID_SYS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct atmel_uart_data dbgu_data = {
+        .use_dma_tx     = 0,
+        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
+        .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
+};
+static u64 dbgu_dmamask = DMA_BIT_MASK(32);
+static struct platform_device at572d940hf_dbgu_device = {
+        .name           = "atmel_usart",
+        .id             = 0,
+        .dev            = {
+                                .dma_mask               = &dbgu_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &dbgu_data,
+        },
+        .resource       = dbgu_resources,
+        .num_resources  = ARRAY_SIZE(dbgu_resources),
+};
+static inline void configure_dbgu_pins(void)
+{
+        at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
+        at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
+}
+static struct resource uart0_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_US0,
+                .end    = AT572D940HF_BASE_US0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_US0,
+                .end    = AT572D940HF_ID_US0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct atmel_uart_data uart0_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+static u64 uart0_dmamask = DMA_BIT_MASK(32);
+static struct platform_device at572d940hf_uart0_device = {
+        .name           = "atmel_usart",
+        .id             = 1,
+        .dev            = {
+                                .dma_mask               = &uart0_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart0_data,
+        },
+        .resource       = uart0_resources,
+        .num_resources  = ARRAY_SIZE(uart0_resources),
+};
+static inline void configure_usart0_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PA8, 1);             /* TXD0 */
+        at91_set_A_periph(AT91_PIN_PA7, 0);             /* RXD0 */
+        if (pins & ATMEL_UART_RTS)
+                at91_set_A_periph(AT91_PIN_PA10, 0);    /* RTS0 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_A_periph(AT91_PIN_PA9, 0);     /* CTS0 */
+}
+static struct resource uart1_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_US1,
+                .end    = AT572D940HF_BASE_US1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_US1,
+                .end    = AT572D940HF_ID_US1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct atmel_uart_data uart1_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+static u64 uart1_dmamask = DMA_BIT_MASK(32);
+static struct platform_device at572d940hf_uart1_device = {
+        .name           = "atmel_usart",
+        .id             = 2,
+        .dev            = {
+                                .dma_mask               = &uart1_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart1_data,
+        },
+        .resource       = uart1_resources,
+        .num_resources  = ARRAY_SIZE(uart1_resources),
+};
+static inline void configure_usart1_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PC10, 1);            /* TXD1 */
+        at91_set_A_periph(AT91_PIN_PC9 , 0);            /* RXD1 */
+        if (pins & ATMEL_UART_RTS)
+                at91_set_A_periph(AT91_PIN_PC12, 0);    /* RTS1 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_A_periph(AT91_PIN_PC11, 0);    /* CTS1 */
+}
+static struct resource uart2_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_US2,
+                .end    = AT572D940HF_BASE_US2 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_US2,
+                .end    = AT572D940HF_ID_US2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct atmel_uart_data uart2_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+static u64 uart2_dmamask = DMA_BIT_MASK(32);
+static struct platform_device at572d940hf_uart2_device = {
+        .name           = "atmel_usart",
+        .id             = 3,
+        .dev            = {
+                                .dma_mask               = &uart2_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart2_data,
+        },
+        .resource       = uart2_resources,
+        .num_resources  = ARRAY_SIZE(uart2_resources),
+};
+static inline void configure_usart2_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PC15, 1);            /* TXD2 */
+        at91_set_A_periph(AT91_PIN_PC14, 0);            /* RXD2 */
+        if (pins & ATMEL_UART_RTS)
+                at91_set_A_periph(AT91_PIN_PC17, 0);    /* RTS2 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_A_periph(AT91_PIN_PC16, 0);    /* CTS2 */
+}
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
+struct platform_device *atmel_default_console_device;   /* the serial console device */
+void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
+{
+        struct platform_device *pdev;
+        switch (id) {
+                case 0:         /* DBGU */
+                        pdev = &at572d940hf_dbgu_device;
+                        configure_dbgu_pins();
+                        at91_clock_associate("mck", &pdev->dev, "usart");
+                        break;
+                case AT572D940HF_ID_US0:
+                        pdev = &at572d940hf_uart0_device;
+                        configure_usart0_pins(pins);
+                        at91_clock_associate("usart0_clk", &pdev->dev, "usart");
+                        break;
+                case AT572D940HF_ID_US1:
+                        pdev = &at572d940hf_uart1_device;
+                        configure_usart1_pins(pins);
+                        at91_clock_associate("usart1_clk", &pdev->dev, "usart");
+                        break;
+                case AT572D940HF_ID_US2:
+                        pdev = &at572d940hf_uart2_device;
+                        configure_usart2_pins(pins);
+                        at91_clock_associate("usart2_clk", &pdev->dev, "usart");
+                        break;
+                default:
+                        return;
+        }
+        pdev->id = portnr;              /* update to mapped ID */
+        if (portnr < ATMEL_MAX_UART)
+                at91_uarts[portnr] = pdev;
+}
+void __init at91_set_serial_console(unsigned portnr)
+{
+        if (portnr < ATMEL_MAX_UART)
+                atmel_default_console_device = at91_uarts[portnr];
+}
+void __init at91_add_device_serial(void)
+{
+        int i;
+        for (i = 0; i < ATMEL_MAX_UART; i++) {
+                if (at91_uarts[i])
+                        platform_device_register(at91_uarts[i]);
+        }
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
+}
+#else
+void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
+void __init at91_set_serial_console(unsigned portnr) {}
+void __init at91_add_device_serial(void) {}
+#endif
+/* --------------------------------------------------------------------
+ *  mAgic
+ * -------------------------------------------------------------------- */
+#ifdef CONFIG_MAGICV
+static struct resource mAgic_resources[] = {
+        {
+                .start = AT91_MAGIC_PM_BASE,
+                .end   = AT91_MAGIC_PM_BASE + AT91_MAGIC_PM_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = AT91_MAGIC_DM_I_BASE,
+                .end   = AT91_MAGIC_DM_I_BASE + AT91_MAGIC_DM_I_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = AT91_MAGIC_DM_F_BASE,
+                .end   = AT91_MAGIC_DM_F_BASE + AT91_MAGIC_DM_F_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = AT91_MAGIC_DM_DB_BASE,
+                .end   = AT91_MAGIC_DM_DB_BASE + AT91_MAGIC_DM_DB_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = AT91_MAGIC_REGS_BASE,
+                .end   = AT91_MAGIC_REGS_BASE + AT91_MAGIC_REGS_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = AT91_MAGIC_EXTPAGE_BASE,
+                .end   = AT91_MAGIC_EXTPAGE_BASE + AT91_MAGIC_EXTPAGE_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start  = AT572D940HF_ID_MSIRQ0,
+                .end    = AT572D940HF_ID_MSIRQ0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = AT572D940HF_ID_MHALT,
+                .end    = AT572D940HF_ID_MHALT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = AT572D940HF_ID_MEXC,
+                .end    = AT572D940HF_ID_MEXC,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = AT572D940HF_ID_MEDMA,
+                .end    = AT572D940HF_ID_MEDMA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device mAgic_device = {
+        .name           = "mAgic",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(mAgic_resources),
+        .resource       = mAgic_resources,
+};
+void __init at91_add_device_mAgic(void)
+{
+        platform_device_register(&mAgic_device);
+}
+#else
+void __init at91_add_device_mAgic(void) {}
+#endif
+/* -------------------------------------------------------------------- */
+/*
+ * These devices are always present and don't need any board-specific
+ * setup.
+ */
+static int __init at91_add_standard_devices(void)
+{
+        at91_add_device_rtt();
+        at91_add_device_watchdog();
+        at91_add_device_tc();
+        return 0;
+}
+arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/board-at572d940hf_ek.c b/arch/arm/mach-at91/board-at572d940hf_ek.c
new file mode 100644
index 000000000000..5daff277f53e
--- /dev/null
+++ b/arch/arm/mach-at91/board-at572d940hf_ek.c
@@ -0,0 +1,328 @@
+/*
+ * linux/arch/arm/mach-at91/board-at572d940hf_ek.c
+ *
+ * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2005 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ds1305.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <mach/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9_smc.h>
+#include "sam9_smc.h"
+#include "generic.h"
+static void __init eb_map_io(void)
+{
+        /* Initialize processor: 12.500 MHz crystal */
+        at572d940hf_initialize(12000000);
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1. (Rx & Tx only) */
+        at91_register_uart(AT572D940HF_ID_US0, 1, 0);
+        /* USART1 on ttyS2. (Rx & Tx only) */
+        at91_register_uart(AT572D940HF_ID_US1, 2, 0);
+        /* USART2 on ttyS3. (Tx & Rx only */
+        at91_register_uart(AT572D940HF_ID_US2, 3, 0);
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+static void __init eb_init_irq(void)
+{
+        at572d940hf_init_interrupts(NULL);
+}
+/*
+ * USB Host Port
+ */
+static struct at91_usbh_data __initdata eb_usbh_data = {
+        .ports          = 2,
+};
+/*
+ * USB Device Port
+ */
+static struct at91_udc_data __initdata eb_udc_data = {
+        .vbus_pin       = 0,            /* no VBUS detection,UDC always on */
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+/*
+ * MCI (SD/MMC)
+ */
+static struct at91_mmc_data __initdata eb_mmc_data = {
+        .wire4          = 1,
+/*      .det_pin        = ... not connected */
+/*      .wp_pin         = ... not connected */
+/*      .vcc_pin        = ... not connected */
+};
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata eb_eth_data = {
+        .phy_irq_pin    = AT91_PIN_PB25,
+        .is_rmii        = 1,
+};
+/*
+ * NOR flash
+ */
+static struct mtd_partition eb_nor_partitions[] = {
+        {
+                .name           = "Raw Environment",
+                .offset         = 0,
+                .size           = SZ_4M,
+                .mask_flags     = 0,
+        },
+        {
+                .name           = "OS FS",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 3 * SZ_1M,
+                .mask_flags     = 0,
+        },
+        {
+                .name           = "APP FS",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+                .mask_flags     = 0,
+        },
+};
+static void nor_flash_set_vpp(struct map_info* mi, int i) {
+};
+static struct physmap_flash_data nor_flash_data = {
+        .width          = 4,
+        .parts          = eb_nor_partitions,
+        .nr_parts       = ARRAY_SIZE(eb_nor_partitions),
+        .set_vpp        = nor_flash_set_vpp,
+};
+static struct resource nor_flash_resources[] = {
+        {
+                .start  = AT91_CHIPSELECT_0,
+                .end    = AT91_CHIPSELECT_0 + SZ_16M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device nor_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                                .platform_data = &nor_flash_data,
+                        },
+        .resource       = nor_flash_resources,
+        .num_resources  = ARRAY_SIZE(nor_flash_resources),
+};
+static struct sam9_smc_config __initdata eb_nor_smc_config = {
+        .ncs_read_setup         = 1,
+        .nrd_setup              = 1,
+        .ncs_write_setup        = 1,
+        .nwe_setup              = 1,
+        .ncs_read_pulse         = 7,
+        .nrd_pulse              = 7,
+        .ncs_write_pulse        = 7,
+        .nwe_pulse              = 7,
+        .read_cycle             = 9,
+        .write_cycle            = 9,
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_32,
+        .tdf_cycles             = 1,
+};
+static void __init eb_add_device_nor(void)
+{
+        /* configure chip-select 0 (NOR) */
+        sam9_smc_configure(0, &eb_nor_smc_config);
+        platform_device_register(&nor_flash);
+}
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata eb_nand_partition[] = {
+        {
+                .name   = "Partition 1",
+                .offset = 0,
+                .size   = SZ_16M,
+        },
+        {
+                .name   = "Partition 2",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = MTDPART_SIZ_FULL,
+        }
+};
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(eb_nand_partition);
+        return eb_nand_partition;
+}
+static struct atmel_nand_data __initdata eb_nand_data = {
+        .ale            = 22,
+        .cle            = 21,
+/*      .det_pin        = ... not connected */
+/*      .rdy_pin        = AT91_PIN_PC16, */
+        .enable_pin     = AT91_PIN_PA15,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+static struct sam9_smc_config __initdata eb_nand_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 0,
+        .ncs_write_setup        = 1,
+        .nwe_setup              = 1,
+        .ncs_read_pulse         = 3,
+        .nrd_pulse              = 3,
+        .ncs_write_pulse        = 3,
+        .nwe_pulse              = 3,
+        .read_cycle             = 5,
+        .write_cycle            = 5,
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
+        .tdf_cycles             = 12,
+};
+static void __init eb_add_device_nand(void)
+{
+        /* setup bus-width (8 or 16) */
+        if (eb_nand_data.bus_width_16)
+                eb_nand_smc_config.mode |= AT91_SMC_DBW_16;
+        else
+                eb_nand_smc_config.mode |= AT91_SMC_DBW_8;
+        /* configure chip-select 3 (NAND) */
+        sam9_smc_configure(3, &eb_nand_smc_config);
+        at91_add_device_nand(&eb_nand_data);
+}
+/*
+ * SPI devices
+ */
+static struct resource rtc_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_ID_IRQ1,
+                .end    = AT572D940HF_ID_IRQ1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct ds1305_platform_data ds1306_data = {
+        .is_ds1306      = true,
+        .en_1hz         = false,
+};
+static struct spi_board_info eb_spi_devices[] = {
+        {       /* RTC Dallas DS1306 */
+                .modalias       = "rtc-ds1305",
+                .chip_select    = 3,
+                .mode           = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA,
+                .max_speed_hz   = 500000,
+                .bus_num        = 0,
+                .irq            = AT572D940HF_ID_IRQ1,
+                .platform_data  = (void *) &ds1306_data,
+        },
+#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
+        {       /* Dataflash card */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#endif
+};
+static void __init eb_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&eb_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&eb_udc_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+        /* NOR */
+        eb_add_device_nor();
+        /* NAND */
+        eb_add_device_nand();
+        /* SPI */
+        at91_add_device_spi(eb_spi_devices, ARRAY_SIZE(eb_spi_devices));
+        /* MMC */
+        at91_add_device_mmc(0, &eb_mmc_data);
+        /* Ethernet */
+        at91_add_device_eth(&eb_eth_data);
+        /* mAgic */
+        at91_add_device_mAgic();
+}
+MACHINE_START(AT572D940HFEB, "Atmel AT91D940HF-EB")
+        /* Maintainer: Atmel <costa.antonior@gmail.com> */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = eb_map_io,
+        .init_irq       = eb_init_irq,
+        .init_machine   = eb_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index c042dcf4725f..7f7da439341f 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -29,6 +29,7 @@
 #include <mach/cpu.h>
 #include "clock.h"
+#include "generic.h"
 /*
@@ -628,7 +629,7 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
                at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
                   cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
-                   cpu_is_at91sam9g10()) {
+                   cpu_is_at91sam9g10() || cpu_is_at572d940hf()) {
                uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                udpck.pmc_mask = AT91SAM926x_PMC_UDP;
        } else if (cpu_is_at91cap9()) {
@@ -711,12 +712,13 @@ int __init at91_clock_init(unsigned long main_clock)
        /*
         * USB HS clock init
         */
-        if (cpu_has_utmi())
+        if (cpu_has_utmi()) {
                /*
                 * multiplier is hard-wired to 40
                 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
                 */
                utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
+        }
        /*
         * USB FS clock init
@@ -746,7 +748,7 @@ int __init at91_clock_init(unsigned long main_clock)
                mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
                        freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
        } else {
-                mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
+                mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));              /* mdiv */
        }
        /* Register the PMC's standard clocks */
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h
index 1ba3b95ff359..6cf4b78e175d 100644
--- a/arch/arm/mach-at91/clock.h
+++ b/arch/arm/mach-at91/clock.h
@@ -22,7 +22,7 @@ struct clk {
        struct clk      *parent;
        u32             pmc_mask;
        void            (*mode)(struct clk *, int);
-        unsigned        id:2;           /* PCK0..3, or 32k/main/a/b */
+        unsigned        id:3;           /* PCK0..4, or 32k/main/a/b */
        unsigned        type;           /* clock type */
        u16             users;
 };
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 88e413b38480..65c3dc5ba0d0 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -17,6 +17,7 @@ extern void __init at91sam9rl_initialize(unsigned long main_clock);
 extern void __init at91sam9g45_initialize(unsigned long main_clock);
 extern void __init at91x40_initialize(unsigned long main_clock);
 extern void __init at91cap9_initialize(unsigned long main_clock);
+extern void __init at572d940hf_initialize(unsigned long main_clock);
 /* Interrupts */
 extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
@@ -27,6 +28,7 @@ extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
 extern void __init at91sam9g45_init_interrupts(unsigned int priority[]);
 extern void __init at91x40_init_interrupts(unsigned int priority[]);
 extern void __init at91cap9_init_interrupts(unsigned int priority[]);
+extern void __init at572d940hf_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[]);
 /* Timer */
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h
new file mode 100644
index 000000000000..2d9b0af9c4d5
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at572d940hf.h
@@ -0,0 +1,123 @@
+/*
+ * include/mach/at572d940hf.h
+ *
+ * Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2008 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#ifndef AT572D940HF_H
+#define AT572D940HF_H
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripherals */
+#define AT572D940HF_ID_PIOA     2       /* Parallel IO Controller A */
+#define AT572D940HF_ID_PIOB     3       /* Parallel IO Controller B */
+#define AT572D940HF_ID_PIOC     4       /* Parallel IO Controller C */
+#define AT572D940HF_ID_EMAC     5       /* MACB ethernet controller */
+#define AT572D940HF_ID_US0      6       /* USART 0 */
+#define AT572D940HF_ID_US1      7       /* USART 1 */
+#define AT572D940HF_ID_US2      8       /* USART 2 */
+#define AT572D940HF_ID_MCI      9       /* Multimedia Card Interface */
+#define AT572D940HF_ID_UDP      10      /* USB Device Port */
+#define AT572D940HF_ID_TWI0     11      /* Two-Wire Interface 0 */
+#define AT572D940HF_ID_SPI0     12      /* Serial Peripheral Interface 0 */
+#define AT572D940HF_ID_SPI1     13      /* Serial Peripheral Interface 1 */
+#define AT572D940HF_ID_SSC0     14      /* Serial Synchronous Controller 0 */
+#define AT572D940HF_ID_SSC1     15      /* Serial Synchronous Controller 1 */
+#define AT572D940HF_ID_SSC2     16      /* Serial Synchronous Controller 2 */
+#define AT572D940HF_ID_TC0      17      /* Timer Counter 0 */
+#define AT572D940HF_ID_TC1      18      /* Timer Counter 1 */
+#define AT572D940HF_ID_TC2      19      /* Timer Counter 2 */
+#define AT572D940HF_ID_UHP      20      /* USB Host port */
+#define AT572D940HF_ID_SSC3     21      /* Serial Synchronous Controller 3 */
+#define AT572D940HF_ID_TWI1     22      /* Two-Wire Interface 1 */
+#define AT572D940HF_ID_CAN0     23      /* CAN Controller 0 */
+#define AT572D940HF_ID_CAN1     24      /* CAN Controller 1 */
+#define AT572D940HF_ID_MHALT    25      /* mAgicV HALT line */
+#define AT572D940HF_ID_MSIRQ0   26      /* mAgicV SIRQ0 line */
+#define AT572D940HF_ID_MEXC     27      /* mAgicV exception line */
+#define AT572D940HF_ID_MEDMA    28      /* mAgicV end of DMA line */
+#define AT572D940HF_ID_IRQ0     29      /* External Interrupt Source (IRQ0) */
+#define AT572D940HF_ID_IRQ1     30      /* External Interrupt Source (IRQ1) */
+#define AT572D940HF_ID_IRQ2     31      /* External Interrupt Source (IRQ2) */
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT572D940HF_BASE_TCB    0xfffa0000
+#define AT572D940HF_BASE_TC0    0xfffa0000
+#define AT572D940HF_BASE_TC1    0xfffa0040
+#define AT572D940HF_BASE_TC2    0xfffa0080
+#define AT572D940HF_BASE_UDP    0xfffa4000
+#define AT572D940HF_BASE_MCI    0xfffa8000
+#define AT572D940HF_BASE_TWI0   0xfffac000
+#define AT572D940HF_BASE_US0    0xfffb0000
+#define AT572D940HF_BASE_US1    0xfffb4000
+#define AT572D940HF_BASE_US2    0xfffb8000
+#define AT572D940HF_BASE_SSC0   0xfffbc000
+#define AT572D940HF_BASE_SSC1   0xfffc0000
+#define AT572D940HF_BASE_SSC2   0xfffc4000
+#define AT572D940HF_BASE_SPI0   0xfffc8000
+#define AT572D940HF_BASE_SPI1   0xfffcc000
+#define AT572D940HF_BASE_SSC3   0xfffd0000
+#define AT572D940HF_BASE_TWI1   0xfffd4000
+#define AT572D940HF_BASE_EMAC   0xfffd8000
+#define AT572D940HF_BASE_CAN0   0xfffdc000
+#define AT572D940HF_BASE_CAN1   0xfffe0000
+#define AT91_BASE_SYS           0xffffea00
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_USART0     AT572D940HF_ID_US0
+#define AT91_USART1     AT572D940HF_ID_US1
+#define AT91_USART2     AT572D940HF_ID_US2
+/*
+ * Internal Memory.
+ */
+#define AT572D940HF_SRAM_BASE   0x00300000      /* Internal SRAM base address */
+#define AT572D940HF_SRAM_SIZE   (48 * SZ_1K)    /* Internal SRAM size (48Kb) */
+#define AT572D940HF_ROM_BASE    0x00400000      /* Internal ROM base address */
+#define AT572D940HF_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
+#define AT572D940HF_UHP_BASE    0x00500000      /* USB Host controller */
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h b/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
new file mode 100644
index 000000000000..b6751df09488
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
@@ -0,0 +1,123 @@
+/*
+ * include/mach//at572d940hf_matrix.h
+ *
+ * Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2008 Atmel
+ *
+ * Copyright (C) 2005 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef AT572D940HF_MATRIX_H
+#define AT572D940HF_MATRIX_H
+#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
+#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (0x7  << 18)    /* Fixed Index of Default Master */
+#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
+#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
+#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
+#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
+#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
+#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
+#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
+#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
+#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91_MATRIX_SFR0        (AT91_MATRIX + 0x110)   /* Special Function Register 0 */
+#define AT91_MATRIX_SFR1        (AT91_MATRIX + 0x114)   /* Special Function Register 1 */
+#define AT91_MATRIX_SFR2        (AT91_MATRIX + 0x118)   /* Special Function Register 2 */
+#define AT91_MATRIX_SFR3        (AT91_MATRIX + 0x11C)   /* Special Function Register 3 */
+#define AT91_MATRIX_SFR4        (AT91_MATRIX + 0x120)   /* Special Function Register 4 */
+#define AT91_MATRIX_SFR5        (AT91_MATRIX + 0x124)   /* Special Function Register 5 */
+#define AT91_MATRIX_SFR6        (AT91_MATRIX + 0x128)   /* Special Function Register 6 */
+#define AT91_MATRIX_SFR7        (AT91_MATRIX + 0x12C)   /* Special Function Register 7 */
+#define AT91_MATRIX_SFR8        (AT91_MATRIX + 0x130)   /* Special Function Register 8 */
+#define AT91_MATRIX_SFR9        (AT91_MATRIX + 0x134)   /* Special Function Register 9 */
+#define AT91_MATRIX_SFR10       (AT91_MATRIX + 0x138)   /* Special Function Register 10 */
+#define AT91_MATRIX_SFR11       (AT91_MATRIX + 0x13C)   /* Special Function Register 11 */
+#define AT91_MATRIX_SFR12       (AT91_MATRIX + 0x140)   /* Special Function Register 12 */
+#define AT91_MATRIX_SFR13       (AT91_MATRIX + 0x144)   /* Special Function Register 13 */
+#define AT91_MATRIX_SFR14       (AT91_MATRIX + 0x148)   /* Special Function Register 14 */
+#define AT91_MATRIX_SFR15       (AT91_MATRIX + 0x14C)   /* Special Function Register 15 */
+/*
+ * The following registers / bits are not defined in the Datasheet (Revision A)
+ */
+#define AT91_MATRIX_TCR         (AT91_MATRIX + 0x100)   /* TCM Configuration Register */
+#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
+#define                 AT91_MATRIX_ITCM_0              (0 << 0)
+#define                 AT91_MATRIX_ITCM_16             (5 << 0)
+#define                 AT91_MATRIX_ITCM_32             (6 << 0)
+#define                 AT91_MATRIX_ITCM_64             (7 << 0)
+#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
+#define                 AT91_MATRIX_DTCM_0              (0 << 4)
+#define                 AT91_MATRIX_DTCM_16             (5 << 4)
+#define                 AT91_MATRIX_DTCM_32             (6 << 4)
+#define                 AT91_MATRIX_DTCM_64             (7 << 4)
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x11C)   /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
+#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
+#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
+#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
+#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
+#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
+#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
+#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 64589eaaaee8..e46f93e34aab 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -32,6 +32,7 @@
 #define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
 #define         AT91_PMC_PCK2           (1 << 10)               /* Programmable Clock 2 */
 #define         AT91_PMC_PCK3           (1 << 11)               /* Programmable Clock 3 */
+#define         AT91_PMC_PCK4           (1 << 12)               /* Programmable Clock 4 [AT572D940HF only] */
 #define         AT91_PMC_HCK0           (1 << 16)               /* AHB Clock (USB host) [AT91SAM9261 only] */
 #define         AT91_PMC_HCK1           (1 << 17)               /* AHB Clock (LCD) [AT91SAM9261 only] */
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index bb6f6a7ba5e0..ceaec6c16eb2 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -87,7 +87,7 @@ struct at91_eth_data {
 extern void __init at91_add_device_eth(struct at91_eth_data *data);
 #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
-        || defined(CONFIG_ARCH_AT91SAM9G45)
+        || defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT572D940HF)
 #define eth_platform_data       at91_eth_data
 #endif
@@ -205,6 +205,9 @@ extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
 extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
 extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
+ /* AT572D940HF DSP */
+extern void __init at91_add_device_mAgic(void);
 /* FIXME: this needs a better location, but gets stuff building again */
 extern int at91_suspend_entering_slow_clock(void);
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index c22df30ed5e5..5a0650101d45 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -33,6 +33,8 @@
 #define ARCH_ID_AT91SAM9XE256   0x329a93a0
 #define ARCH_ID_AT91SAM9XE512   0x329aa3a0
+#define ARCH_ID_AT572D940HF     0x0e0303e0
 #define ARCH_ID_AT91M40800      0x14080044
 #define ARCH_ID_AT91R40807      0x44080746
 #define ARCH_ID_AT91M40807      0x14080745
@@ -141,6 +143,12 @@ static inline unsigned long at91cap9_rev_identify(void)
 #define cpu_is_at91cap9_revC()  (0)
 #endif
+#ifdef CONFIG_ARCH_AT572D940HF
+#define cpu_is_at572d940hf() (at91_cpu_identify() == ARCH_ID_AT572D940HF)
+#else
+#define cpu_is_at572d940hf() (0)
+#endif
 /*
 * Since this is ARM, we will never run on any AVR32 CPU. But these
 * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index a0df8b022df2..3d64a75e3ed5 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -32,6 +32,8 @@
 #include <mach/at91cap9.h>
 #elif defined(CONFIG_ARCH_AT91X40)
 #include <mach/at91x40.h>
+#elif defined(CONFIG_ARCH_AT572D940HF)
+#include <mach/at572d940hf.h>
 #else
 #error "Unsupported AT91 processor"
 #endif
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index 31ac2d97f14c..05a6e8af80c4 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -82,6 +82,11 @@
 #define AT91X40_MASTER_CLOCK    40000000
 #define CLOCK_TICK_RATE         (AT91X40_MASTER_CLOCK)
+#elif defined(CONFIG_ARCH_AT572D940HF)
+#define AT572D940HF_MASTER_CLOCK        80000000
+#define CLOCK_TICK_RATE         (AT572D940HF_MASTER_CLOCK/16)
 #endif
 #endif
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index a9b650dcc172..077ecf4fecda 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -236,6 +236,7 @@ static struct vpfe_subdev_info vpfe_sub_devs[] = {
 static struct vpfe_config vpfe_cfg = {
        .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
+        .i2c_adapter_id = 1,
        .sub_devs = vpfe_sub_devs,
        .card_name = "DM355 EVM",
        .ccdc = "DM355 CCDC",
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 289fe1b7d25a..b476395d2cd4 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -192,7 +192,11 @@ static struct davinci_i2c_platform_data i2c_pdata = {
        .bus_delay      = 0     /* usec */,
 };
-#ifdef CONFIG_KEYBOARD_DAVINCI
+static int dm365evm_keyscan_enable(struct device *dev)
+{
+        return davinci_cfg_reg(DM365_KEYSCAN);
+}
 static unsigned short dm365evm_keymap[] = {
        KEY_KP2,
        KEY_LEFT,
@@ -214,6 +218,7 @@ static unsigned short dm365evm_keymap[] = {
 };
 static struct davinci_ks_platform_data dm365evm_ks_data = {
+        .device_enable  = dm365evm_keyscan_enable,
        .keymap         = dm365evm_keymap,
        .keymapsize     = ARRAY_SIZE(dm365evm_keymap),
        .rep            = 1,
@@ -222,7 +227,6 @@ static struct davinci_ks_platform_data dm365evm_ks_data = {
        .interval       = 0x2,
        .matrix_type    = DAVINCI_KEYSCAN_MATRIX_4X4,
 };
-#endif
 static int cpld_mmc_get_cd(int module)
 {
@@ -511,10 +515,7 @@ static __init void dm365_evm_init(void)
        dm365_init_asp(&dm365_evm_snd_data);
        dm365_init_rtc();
-#ifdef CONFIG_KEYBOARD_DAVINCI
        dm365_init_ks(&dm365evm_ks_data);
-#endif
 }
 static __init void dm365_evm_irq_init(void)
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index fd0398bc6db3..e9612cf727b7 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -247,6 +247,7 @@ static struct vpfe_subdev_info vpfe_sub_devs[] = {
 static struct vpfe_config vpfe_cfg = {
        .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
+        .i2c_adapter_id = 1,
        .sub_devs = vpfe_sub_devs,
        .card_name = "DM6446 EVM",
        .ccdc = "DM6446 CCDC",
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index 52b287cf3a42..37311d1830eb 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -81,12 +81,23 @@ static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type)
        return 0;
 }
+/*
+ * Faking this allows us to to work with suspend functions of
+ * generic drivers which call {enable|disable}_irq_wake for
+ * wake up interrupt sources (eg RTC on DA850).
+ */
+static int cp_intc_set_wake(unsigned int irq, unsigned int on)
+{
+        return 0;
+}
 static struct irq_chip cp_intc_irq_chip = {
        .name           = "cp_intc",
        .ack            = cp_intc_ack_irq,
        .mask           = cp_intc_mask_irq,
        .unmask         = cp_intc_unmask_irq,
        .set_type       = cp_intc_set_irq_type,
+        .set_wake       = cp_intc_set_wake,
 };
 void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index dd2d32c4ce86..a5105f03fd86 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -481,11 +481,18 @@ static struct platform_device da8xx_rtc_device = {
 int da8xx_register_rtc(void)
 {
+        int ret;
        /* Unlock the rtc's registers */
        __raw_writel(0x83e70b13, IO_ADDRESS(DA8XX_RTC_BASE + 0x6c));
        __raw_writel(0x95a4f1e0, IO_ADDRESS(DA8XX_RTC_BASE + 0x70));
-        return platform_device_register(&da8xx_rtc_device);
+        ret = platform_device_register(&da8xx_rtc_device);
+        if (!ret)
+                /* Atleast on DA850, RTC is a wakeup source */
+                device_init_wakeup(&da8xx_rtc_device.dev, true);
+        return ret;
 }
 static struct resource da8xx_cpuidle_resources[] = {
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 2ec619ec1657..f53735cb922e 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -993,7 +993,6 @@ void __init dm365_init_asp(struct snd_platform_data *pdata)
 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
 {
-        davinci_cfg_reg(DM365_KEYSCAN);
        dm365_ks_device.dev.platform_data = pdata;
        platform_device_register(&dm365_ks_device);
 }
diff --git a/arch/arm/mach-davinci/include/mach/keyscan.h b/arch/arm/mach-davinci/include/mach/keyscan.h
index b4e21a2976d1..7a560e05bda8 100644
--- a/arch/arm/mach-davinci/include/mach/keyscan.h
+++ b/arch/arm/mach-davinci/include/mach/keyscan.h
@@ -29,6 +29,7 @@ enum davinci_matrix_types {
 };
 struct davinci_ks_platform_data {
+        int             (*device_enable)(struct device *dev);
        unsigned short  *keymap;
        u32             keymapsize;
        u8              rep:1;
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index 9167c3d2a5ed..3a08b18f6433 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -161,6 +161,20 @@ config MACH_MICRO9S
          Say 'Y' here if you want your kernel to support the
          Contec Micro9-Slim board.
+config MACH_SIM_ONE
+        bool "Support Simplemachines Sim.One board"
+        depends on EP93XX_SDCE0_PHYS_OFFSET
+        help
+          Say 'Y' here if you want your kernel to support the
+          Simplemachines Sim.One board.
+config MACH_SNAPPER_CL15
+        bool "Support Bluewater Systems Snapper CL15 Module"
+        depends on EP93XX_SDCE0_PHYS_OFFSET
+        help
+          Say 'Y' here if you want your kernel to support the Bluewater
+          Systems Snapper CL15 Module.
 config MACH_TS72XX
        bool "Support Technologic Systems TS-72xx SBC"
        depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index eae6199a9891..33ee2c863d18 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -10,4 +10,6 @@ obj-$(CONFIG_MACH_ADSSPHERE)	+= adssphere.o
 obj-$(CONFIG_MACH_EDB93XX)      += edb93xx.o
 obj-$(CONFIG_MACH_GESBC9312)    += gesbc9312.o
 obj-$(CONFIG_MACH_MICRO9)       += micro9.o
+obj-$(CONFIG_MACH_SIM_ONE)      += simone.o
+obj-$(CONFIG_MACH_SNAPPER_CL15) += snappercl15.o
 obj-$(CONFIG_MACH_TS72XX)       += ts72xx.o
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 1d0f9d8aff2e..49fa9f8fef4a 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -10,6 +10,8 @@
 * your option) any later version.
 */
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/err.h>
@@ -447,30 +449,34 @@ static int __init ep93xx_clock_init(void)
        u32 value;
        int i;
-        value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
+        /* Determine the bootloader configured pll1 rate */
-        if (!(value & 0x00800000)) {                    /* PLL1 bypassed?  */
+        value = __raw_readl(EP93XX_SYSCON_CLKSET1);
+        if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
                clk_pll1.rate = clk_xtali.rate;
-        } else {
+        else
                clk_pll1.rate = calc_pll_rate(value);
-        }
+        /* Initialize the pll1 derived clocks */
        clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
        clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
        clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
        ep93xx_dma_clock_init();
-        value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
+        /* Determine the bootloader configured pll2 rate */
-        if (!(value & 0x00080000)) {                    /* PLL2 bypassed?  */
+        value = __raw_readl(EP93XX_SYSCON_CLKSET2);
+        if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
                clk_pll2.rate = clk_xtali.rate;
-        } else if (value & 0x00040000) {                /* PLL2 enabled?  */
+        else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
                clk_pll2.rate = calc_pll_rate(value);
-        } else {
+        else
                clk_pll2.rate = 0;
-        }
+        /* Initialize the pll2 derived clocks */
        clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
-        printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
+        pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
                clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
-        printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
+        pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
                clk_f.rate / 1000000, clk_h.rate / 1000000,
                clk_p.rate / 1000000);
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 1f0d66561bbe..90fb591cbffa 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -14,12 +14,15 @@
 * your option) any later version.
 */
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/dma-mapping.h>
 #include <linux/timex.h>
+#include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
@@ -35,7 +38,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/mach/irq.h>
 #include <asm/hardware/vic.h>
@@ -82,13 +84,40 @@ void __init ep93xx_map_io(void)
 * to use this timer for something else.  We also use timer 4 for keeping
 * track of lost jiffies.
 */
-static unsigned int last_jiffy_time;
+#define EP93XX_TIMER_REG(x)             (EP93XX_TIMER_BASE + (x))
+#define EP93XX_TIMER1_LOAD              EP93XX_TIMER_REG(0x00)
+#define EP93XX_TIMER1_VALUE             EP93XX_TIMER_REG(0x04)
+#define EP93XX_TIMER1_CONTROL           EP93XX_TIMER_REG(0x08)
+#define EP93XX_TIMER123_CONTROL_ENABLE  (1 << 7)
+#define EP93XX_TIMER123_CONTROL_MODE    (1 << 6)
+#define EP93XX_TIMER123_CONTROL_CLKSEL  (1 << 3)
+#define EP93XX_TIMER1_CLEAR             EP93XX_TIMER_REG(0x0c)
+#define EP93XX_TIMER2_LOAD              EP93XX_TIMER_REG(0x20)
+#define EP93XX_TIMER2_VALUE             EP93XX_TIMER_REG(0x24)
+#define EP93XX_TIMER2_CONTROL           EP93XX_TIMER_REG(0x28)
+#define EP93XX_TIMER2_CLEAR             EP93XX_TIMER_REG(0x2c)
+#define EP93XX_TIMER4_VALUE_LOW         EP93XX_TIMER_REG(0x60)
+#define EP93XX_TIMER4_VALUE_HIGH        EP93XX_TIMER_REG(0x64)
+#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
+#define EP93XX_TIMER3_LOAD              EP93XX_TIMER_REG(0x80)
+#define EP93XX_TIMER3_VALUE             EP93XX_TIMER_REG(0x84)
+#define EP93XX_TIMER3_CONTROL           EP93XX_TIMER_REG(0x88)
+#define EP93XX_TIMER3_CLEAR             EP93XX_TIMER_REG(0x8c)
+#define EP93XX_TIMER123_CLOCK           508469
+#define EP93XX_TIMER4_CLOCK             983040
+#define TIMER1_RELOAD                   ((EP93XX_TIMER123_CLOCK / HZ) - 1)
 #define TIMER4_TICKS_PER_JIFFY          DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
+static unsigned int last_jiffy_time;
 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
 {
+        /* Writing any value clears the timer interrupt */
        __raw_writel(1, EP93XX_TIMER1_CLEAR);
+        /* Recover lost jiffies */
        while ((signed long)
                (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
                                                >= TIMER4_TICKS_PER_JIFFY) {
@@ -107,13 +136,18 @@ static struct irqaction ep93xx_timer_irq = {
 static void __init ep93xx_timer_init(void)
 {
+        u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
+                    EP93XX_TIMER123_CONTROL_CLKSEL;
        /* Enable periodic HZ timer.  */
-        __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
+        __raw_writel(tmode, EP93XX_TIMER1_CONTROL);
-        __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
+        __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
-        __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
+        __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
+                        EP93XX_TIMER1_CONTROL);
        /* Enable lost jiffy timer.  */
-        __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
+        __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
+                        EP93XX_TIMER4_VALUE_HIGH);
        setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
 }
@@ -135,237 +169,16 @@ struct sys_timer ep93xx_timer = {
 /*************************************************************************
- * GPIO handling for EP93xx
- *************************************************************************/
-static unsigned char gpio_int_unmasked[3];
-static unsigned char gpio_int_enabled[3];
-static unsigned char gpio_int_type1[3];
-static unsigned char gpio_int_type2[3];
-static unsigned char gpio_int_debounce[3];
-/* Port ordering is: A B F */
-static const u8 int_type1_register_offset[3]    = { 0x90, 0xac, 0x4c };
-static const u8 int_type2_register_offset[3]    = { 0x94, 0xb0, 0x50 };
-static const u8 eoi_register_offset[3]          = { 0x98, 0xb4, 0x54 };
-static const u8 int_en_register_offset[3]       = { 0x9c, 0xb8, 0x58 };
-static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
-void ep93xx_gpio_update_int_params(unsigned port)
-{
-        BUG_ON(port > 2);
-        __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
-        __raw_writeb(gpio_int_type2[port],
-                EP93XX_GPIO_REG(int_type2_register_offset[port]));
-        __raw_writeb(gpio_int_type1[port],
-                EP93XX_GPIO_REG(int_type1_register_offset[port]));
-        __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
-                EP93XX_GPIO_REG(int_en_register_offset[port]));
-}
-void ep93xx_gpio_int_mask(unsigned line)
-{
-        gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
-}
-void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
-{
-        int line = irq_to_gpio(irq);
-        int port = line >> 3;
-        int port_mask = 1 << (line & 7);
-        if (enable)
-                gpio_int_debounce[port] |= port_mask;
-        else
-                gpio_int_debounce[port] &= ~port_mask;
-        __raw_writeb(gpio_int_debounce[port],
-                EP93XX_GPIO_REG(int_debounce_register_offset[port]));
-}
-EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
-/*************************************************************************
 * EP93xx IRQ handling
 *************************************************************************/
-static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
+extern void ep93xx_gpio_init_irq(void);
-{
-        unsigned char status;
-        int i;
-        status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
-        for (i = 0; i < 8; i++) {
-                if (status & (1 << i)) {
-                        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
-                        generic_handle_irq(gpio_irq);
-                }
-        }
-        status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
-        for (i = 0; i < 8; i++) {
-                if (status & (1 << i)) {
-                        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
-                        generic_handle_irq(gpio_irq);
-                }
-        }
-}
-static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        /*
-         * map discontiguous hw irq range to continous sw irq range:
-         *
-         *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
-         */
-        int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
-        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
-        generic_handle_irq(gpio_irq);
-}
-static void ep93xx_gpio_irq_ack(unsigned int irq)
-{
-        int line = irq_to_gpio(irq);
-        int port = line >> 3;
-        int port_mask = 1 << (line & 7);
-        if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
-                gpio_int_type2[port] ^= port_mask; /* switch edge direction */
-                ep93xx_gpio_update_int_params(port);
-        }
-        __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
-}
-static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
-{
-        int line = irq_to_gpio(irq);
-        int port = line >> 3;
-        int port_mask = 1 << (line & 7);
-        if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
-                gpio_int_type2[port] ^= port_mask; /* switch edge direction */
-        gpio_int_unmasked[port] &= ~port_mask;
-        ep93xx_gpio_update_int_params(port);
-        __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
-}
-static void ep93xx_gpio_irq_mask(unsigned int irq)
-{
-        int line = irq_to_gpio(irq);
-        int port = line >> 3;
-        gpio_int_unmasked[port] &= ~(1 << (line & 7));
-        ep93xx_gpio_update_int_params(port);
-}
-static void ep93xx_gpio_irq_unmask(unsigned int irq)
-{
-        int line = irq_to_gpio(irq);
-        int port = line >> 3;
-        gpio_int_unmasked[port] |= 1 << (line & 7);
-        ep93xx_gpio_update_int_params(port);
-}
-/*
- * gpio_int_type1 controls whether the interrupt is level (0) or
- * edge (1) triggered, while gpio_int_type2 controls whether it
- * triggers on low/falling (0) or high/rising (1).
- */
-static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
-{
-        struct irq_desc *desc = irq_desc + irq;
-        const int gpio = irq_to_gpio(irq);
-        const int port = gpio >> 3;
-        const int port_mask = 1 << (gpio & 7);
-        gpio_direction_input(gpio);
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                gpio_int_type1[port] |= port_mask;
-                gpio_int_type2[port] |= port_mask;
-                desc->handle_irq = handle_edge_irq;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                gpio_int_type1[port] |= port_mask;
-                gpio_int_type2[port] &= ~port_mask;
-                desc->handle_irq = handle_edge_irq;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                gpio_int_type1[port] &= ~port_mask;
-                gpio_int_type2[port] |= port_mask;
-                desc->handle_irq = handle_level_irq;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                gpio_int_type1[port] &= ~port_mask;
-                gpio_int_type2[port] &= ~port_mask;
-                desc->handle_irq = handle_level_irq;
-                break;
-        case IRQ_TYPE_EDGE_BOTH:
-                gpio_int_type1[port] |= port_mask;
-                /* set initial polarity based on current input level */
-                if (gpio_get_value(gpio))
-                        gpio_int_type2[port] &= ~port_mask; /* falling */
-                else
-                        gpio_int_type2[port] |= port_mask; /* rising */
-                desc->handle_irq = handle_edge_irq;
-                break;
-        default:
-                pr_err("ep93xx: failed to set irq type %d for gpio %d\n",
-                       type, gpio);
-                return -EINVAL;
-        }
-        gpio_int_enabled[port] |= port_mask;
-        desc->status &= ~IRQ_TYPE_SENSE_MASK;
-        desc->status |= type & IRQ_TYPE_SENSE_MASK;
-        ep93xx_gpio_update_int_params(port);
-        return 0;
-}
-static struct irq_chip ep93xx_gpio_irq_chip = {
-        .name           = "GPIO",
-        .ack            = ep93xx_gpio_irq_ack,
-        .mask_ack       = ep93xx_gpio_irq_mask_ack,
-        .mask           = ep93xx_gpio_irq_mask,
-        .unmask         = ep93xx_gpio_irq_unmask,
-        .set_type       = ep93xx_gpio_irq_type,
-};
 void __init ep93xx_init_irq(void)
 {
-        int gpio_irq;
        vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
        vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
-        for (gpio_irq = gpio_to_irq(0);
+        ep93xx_gpio_init_irq();
-             gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
-                set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
-                set_irq_handler(gpio_irq, handle_level_irq);
-                set_irq_flags(gpio_irq, IRQF_VALID);
-        }
-        set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
 }
@@ -572,9 +385,9 @@ void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
         * CMOS driver.
         */
        if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT)
-                pr_warning("ep93xx: sda != EEDAT, open drain has no effect\n");
+                pr_warning("sda != EEDAT, open drain has no effect\n");
        if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK)
-                pr_warning("ep93xx: scl != EECLK, open drain has no effect\n");
+                pr_warning("scl != EECLK, open drain has no effect\n");
        __raw_writel((data->sda_is_open_drain << 1) |
                     (data->scl_is_open_drain << 0),
diff --git a/arch/arm/mach-ep93xx/dma-m2p.c b/arch/arm/mach-ep93xx/dma-m2p.c
index dbcac9c40a28..8904ca4e2e24 100644
--- a/arch/arm/mach-ep93xx/dma-m2p.c
+++ b/arch/arm/mach-ep93xx/dma-m2p.c
@@ -28,6 +28,8 @@
 * with this implementation.
 */
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/err.h>
@@ -173,7 +175,7 @@ static irqreturn_t m2p_irq(int irq, void *dev_id)
        switch (m2p_channel_state(ch)) {
        case STATE_IDLE:
-                pr_crit("m2p_irq: dma interrupt without a dma buffer\n");
+                pr_crit("dma interrupt without a dma buffer\n");
                BUG();
                break;
@@ -197,7 +199,7 @@ static irqreturn_t m2p_irq(int irq, void *dev_id)
                break;
        case STATE_NEXT:
-                pr_crit("m2p_irq: dma interrupt while next\n");
+                pr_crit("dma interrupt while next\n");
                BUG();
                break;
        }
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index a4a7be308000..d22d67ac8b99 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -118,12 +118,33 @@ static void __init edb93xx_register_i2c(void)
        }
 }
+/*************************************************************************
+ * EDB93xx pwm
+ *************************************************************************/
+static void __init edb93xx_register_pwm(void)
+{
+        if (machine_is_edb9301() ||
+            machine_is_edb9302() || machine_is_edb9302a()) {
+                /* EP9301 and EP9302 only have pwm.1 (EGPIO14) */
+                ep93xx_register_pwm(0, 1);
+        } else if (machine_is_edb9307() || machine_is_edb9307a()) {
+                /* EP9307 only has pwm.0 (PWMOUT) */
+                ep93xx_register_pwm(1, 0);
+        } else {
+                /* EP9312 and EP9315 have both */
+                ep93xx_register_pwm(1, 1);
+        }
+}
 static void __init edb93xx_init_machine(void)
 {
        ep93xx_init_devices();
        edb93xx_register_flash();
        ep93xx_register_eth(&edb93xx_eth_data, 1);
        edb93xx_register_i2c();
+        edb93xx_register_pwm();
 }
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index 1ea8871e03a9..cc377ae8c428 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -13,6 +13,8 @@
 *  published by the Free Software Foundation.
 */
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/seq_file.h>
@@ -22,6 +24,235 @@
 #include <mach/hardware.h>
+/*************************************************************************
+ * GPIO handling for EP93xx
+ *************************************************************************/
+static unsigned char gpio_int_unmasked[3];
+static unsigned char gpio_int_enabled[3];
+static unsigned char gpio_int_type1[3];
+static unsigned char gpio_int_type2[3];
+static unsigned char gpio_int_debounce[3];
+/* Port ordering is: A B F */
+static const u8 int_type1_register_offset[3]    = { 0x90, 0xac, 0x4c };
+static const u8 int_type2_register_offset[3]    = { 0x94, 0xb0, 0x50 };
+static const u8 eoi_register_offset[3]          = { 0x98, 0xb4, 0x54 };
+static const u8 int_en_register_offset[3]       = { 0x9c, 0xb8, 0x58 };
+static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
+void ep93xx_gpio_update_int_params(unsigned port)
+{
+        BUG_ON(port > 2);
+        __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
+        __raw_writeb(gpio_int_type2[port],
+                EP93XX_GPIO_REG(int_type2_register_offset[port]));
+        __raw_writeb(gpio_int_type1[port],
+                EP93XX_GPIO_REG(int_type1_register_offset[port]));
+        __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
+                EP93XX_GPIO_REG(int_en_register_offset[port]));
+}
+void ep93xx_gpio_int_mask(unsigned line)
+{
+        gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
+}
+void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
+{
+        int line = irq_to_gpio(irq);
+        int port = line >> 3;
+        int port_mask = 1 << (line & 7);
+        if (enable)
+                gpio_int_debounce[port] |= port_mask;
+        else
+                gpio_int_debounce[port] &= ~port_mask;
+        __raw_writeb(gpio_int_debounce[port],
+                EP93XX_GPIO_REG(int_debounce_register_offset[port]));
+}
+EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
+static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned char status;
+        int i;
+        status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
+        for (i = 0; i < 8; i++) {
+                if (status & (1 << i)) {
+                        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
+                        generic_handle_irq(gpio_irq);
+                }
+        }
+        status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
+        for (i = 0; i < 8; i++) {
+                if (status & (1 << i)) {
+                        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
+                        generic_handle_irq(gpio_irq);
+                }
+        }
+}
+static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        /*
+         * map discontiguous hw irq range to continous sw irq range:
+         *
+         *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
+         */
+        int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
+        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
+        generic_handle_irq(gpio_irq);
+}
+static void ep93xx_gpio_irq_ack(unsigned int irq)
+{
+        int line = irq_to_gpio(irq);
+        int port = line >> 3;
+        int port_mask = 1 << (line & 7);
+        if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
+                gpio_int_type2[port] ^= port_mask; /* switch edge direction */
+                ep93xx_gpio_update_int_params(port);
+        }
+        __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
+}
+static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
+{
+        int line = irq_to_gpio(irq);
+        int port = line >> 3;
+        int port_mask = 1 << (line & 7);
+        if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
+                gpio_int_type2[port] ^= port_mask; /* switch edge direction */
+        gpio_int_unmasked[port] &= ~port_mask;
+        ep93xx_gpio_update_int_params(port);
+        __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
+}
+static void ep93xx_gpio_irq_mask(unsigned int irq)
+{
+        int line = irq_to_gpio(irq);
+        int port = line >> 3;
+        gpio_int_unmasked[port] &= ~(1 << (line & 7));
+        ep93xx_gpio_update_int_params(port);
+}
+static void ep93xx_gpio_irq_unmask(unsigned int irq)
+{
+        int line = irq_to_gpio(irq);
+        int port = line >> 3;
+        gpio_int_unmasked[port] |= 1 << (line & 7);
+        ep93xx_gpio_update_int_params(port);
+}
+/*
+ * gpio_int_type1 controls whether the interrupt is level (0) or
+ * edge (1) triggered, while gpio_int_type2 controls whether it
+ * triggers on low/falling (0) or high/rising (1).
+ */
+static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
+{
+        struct irq_desc *desc = irq_desc + irq;
+        const int gpio = irq_to_gpio(irq);
+        const int port = gpio >> 3;
+        const int port_mask = 1 << (gpio & 7);
+        gpio_direction_input(gpio);
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                gpio_int_type1[port] |= port_mask;
+                gpio_int_type2[port] |= port_mask;
+                desc->handle_irq = handle_edge_irq;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                gpio_int_type1[port] |= port_mask;
+                gpio_int_type2[port] &= ~port_mask;
+                desc->handle_irq = handle_edge_irq;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                gpio_int_type1[port] &= ~port_mask;
+                gpio_int_type2[port] |= port_mask;
+                desc->handle_irq = handle_level_irq;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                gpio_int_type1[port] &= ~port_mask;
+                gpio_int_type2[port] &= ~port_mask;
+                desc->handle_irq = handle_level_irq;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                gpio_int_type1[port] |= port_mask;
+                /* set initial polarity based on current input level */
+                if (gpio_get_value(gpio))
+                        gpio_int_type2[port] &= ~port_mask; /* falling */
+                else
+                        gpio_int_type2[port] |= port_mask; /* rising */
+                desc->handle_irq = handle_edge_irq;
+                break;
+        default:
+                pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
+                return -EINVAL;
+        }
+        gpio_int_enabled[port] |= port_mask;
+        desc->status &= ~IRQ_TYPE_SENSE_MASK;
+        desc->status |= type & IRQ_TYPE_SENSE_MASK;
+        ep93xx_gpio_update_int_params(port);
+        return 0;
+}
+static struct irq_chip ep93xx_gpio_irq_chip = {
+        .name           = "GPIO",
+        .ack            = ep93xx_gpio_irq_ack,
+        .mask_ack       = ep93xx_gpio_irq_mask_ack,
+        .mask           = ep93xx_gpio_irq_mask,
+        .unmask         = ep93xx_gpio_irq_unmask,
+        .set_type       = ep93xx_gpio_irq_type,
+};
+void __init ep93xx_gpio_init_irq(void)
+{
+        int gpio_irq;
+        for (gpio_irq = gpio_to_irq(0);
+             gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
+                set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
+                set_irq_handler(gpio_irq, handle_level_irq);
+                set_irq_flags(gpio_irq, IRQF_VALID);
+        }
+        set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
+}
+/*************************************************************************
+ * gpiolib interface for EP93xx on-chip GPIOs
+ *************************************************************************/
 struct ep93xx_gpio_chip {
        struct gpio_chip        chip;
@@ -31,10 +262,6 @@ struct ep93xx_gpio_chip {
 #define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
-/* From core.c */
-extern void ep93xx_gpio_int_mask(unsigned line);
-extern void ep93xx_gpio_update_int_params(unsigned port);
 static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index d55194a4c093..93e2ecc79ceb 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -92,21 +92,6 @@
 /* APB peripherals */
 #define EP93XX_TIMER_BASE               EP93XX_APB_IOMEM(0x00010000)
-#define EP93XX_TIMER_REG(x)             (EP93XX_TIMER_BASE + (x))
-#define EP93XX_TIMER1_LOAD              EP93XX_TIMER_REG(0x00)
-#define EP93XX_TIMER1_VALUE             EP93XX_TIMER_REG(0x04)
-#define EP93XX_TIMER1_CONTROL           EP93XX_TIMER_REG(0x08)
-#define EP93XX_TIMER1_CLEAR             EP93XX_TIMER_REG(0x0c)
-#define EP93XX_TIMER2_LOAD              EP93XX_TIMER_REG(0x20)
-#define EP93XX_TIMER2_VALUE             EP93XX_TIMER_REG(0x24)
-#define EP93XX_TIMER2_CONTROL           EP93XX_TIMER_REG(0x28)
-#define EP93XX_TIMER2_CLEAR             EP93XX_TIMER_REG(0x2c)
-#define EP93XX_TIMER4_VALUE_LOW         EP93XX_TIMER_REG(0x60)
-#define EP93XX_TIMER4_VALUE_HIGH        EP93XX_TIMER_REG(0x64)
-#define EP93XX_TIMER3_LOAD              EP93XX_TIMER_REG(0x80)
-#define EP93XX_TIMER3_VALUE             EP93XX_TIMER_REG(0x84)
-#define EP93XX_TIMER3_CONTROL           EP93XX_TIMER_REG(0x88)
-#define EP93XX_TIMER3_CLEAR             EP93XX_TIMER_REG(0x8c)
 #define EP93XX_I2S_BASE                 EP93XX_APB_IOMEM(0x00020000)
@@ -167,8 +152,11 @@
 #define EP93XX_SYSCON_PWRCNT_DMA_M2P1   (1<<16)
 #define EP93XX_SYSCON_HALT              EP93XX_SYSCON_REG(0x08)
 #define EP93XX_SYSCON_STANDBY           EP93XX_SYSCON_REG(0x0c)
-#define EP93XX_SYSCON_CLOCK_SET1        EP93XX_SYSCON_REG(0x20)
+#define EP93XX_SYSCON_CLKSET1           EP93XX_SYSCON_REG(0x20)
-#define EP93XX_SYSCON_CLOCK_SET2        EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET1_NBYP1     (1<<23)
+#define EP93XX_SYSCON_CLKSET2           EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET2_NBYP2     (1<<19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN   (1<<18)
 #define EP93XX_SYSCON_DEVCFG            EP93XX_SYSCON_REG(0x80)
 #define EP93XX_SYSCON_DEVCFG_SWRST      (1<<31)
 #define EP93XX_SYSCON_DEVCFG_D1ONG      (1<<30)
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
new file mode 100644
index 000000000000..cd93990f1b99
--- /dev/null
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -0,0 +1,97 @@
+/*
+ * arch/arm/mach-ep93xx/simone.c
+ * Simplemachines Sim.One support.
+ *
+ * Copyright (C) 2010 Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * Based on the 2.6.24.7 support:
+ *   Copyright (C) 2009 Simplemachines
+ *   MMC support by Peter Ivanov <ivanovp@gmail.com>, 2007
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <mach/hardware.h>
+#include <mach/fb.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+static struct physmap_flash_data simone_flash_data = {
+        .width          = 2,
+};
+static struct resource simone_flash_resource = {
+        .start          = EP93XX_CS6_PHYS_BASE,
+        .end            = EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
+        .flags          = IORESOURCE_MEM,
+};
+static struct platform_device simone_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = &simone_flash_resource,
+        .dev = {
+                .platform_data  = &simone_flash_data,
+        },
+};
+static struct ep93xx_eth_data simone_eth_data = {
+        .phy_id         = 1,
+};
+static struct ep93xxfb_mach_info simone_fb_info = {
+        .num_modes      = EP93XXFB_USE_MODEDB,
+        .bpp            = 16,
+        .flags          = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING,
+};
+static struct i2c_gpio_platform_data simone_i2c_gpio_data = {
+        .sda_pin                = EP93XX_GPIO_LINE_EEDAT,
+        .sda_is_open_drain      = 0,
+        .scl_pin                = EP93XX_GPIO_LINE_EECLK,
+        .scl_is_open_drain      = 0,
+        .udelay                 = 0,
+        .timeout                = 0,
+};
+static struct i2c_board_info __initdata simone_i2c_board_info[] = {
+        {
+                I2C_BOARD_INFO("ds1337", 0x68),
+        },
+};
+static void __init simone_init_machine(void)
+{
+        ep93xx_init_devices();
+        platform_device_register(&simone_flash);
+        ep93xx_register_eth(&simone_eth_data, 1);
+        ep93xx_register_fb(&simone_fb_info);
+        ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info,
+                            ARRAY_SIZE(simone_i2c_board_info));
+}
+MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
+/* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = simone_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
new file mode 100644
index 000000000000..51134b0382ca
--- /dev/null
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -0,0 +1,172 @@
+/*
+ * arch/arm/mach-ep93xx/snappercl15.c
+ * Bluewater Systems Snapper CL15 system module
+ *
+ * Copyright (C) 2009 Bluewater Systems Ltd
+ * Author: Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * NAND code adapted from driver by:
+ *   Andre Renaud <andre@bluewatersys.com>
+ *   James R. McKaskill
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ */
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/fb.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand.h>
+#include <mach/hardware.h>
+#include <mach/fb.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#define SNAPPERCL15_NAND_BASE   (EP93XX_CS7_PHYS_BASE + SZ_16M)
+#define SNAPPERCL15_NAND_WPN    (1 << 8)  /* Write protect (active low) */
+#define SNAPPERCL15_NAND_ALE    (1 << 9)  /* Address latch */
+#define SNAPPERCL15_NAND_CLE    (1 << 10) /* Command latch */
+#define SNAPPERCL15_NAND_CEN    (1 << 11) /* Chip enable (active low) */
+#define SNAPPERCL15_NAND_RDY    (1 << 14) /* Device ready */
+#define NAND_CTRL_ADDR(chip)    (chip->IO_ADDR_W + 0x40)
+static void snappercl15_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+                                      unsigned int ctrl)
+{
+        struct nand_chip *chip = mtd->priv;
+        static u16 nand_state = SNAPPERCL15_NAND_WPN;
+        u16 set;
+        if (ctrl & NAND_CTRL_CHANGE) {
+                set = SNAPPERCL15_NAND_CEN | SNAPPERCL15_NAND_WPN;
+                if (ctrl & NAND_NCE)
+                        set &= ~SNAPPERCL15_NAND_CEN;
+                if (ctrl & NAND_CLE)
+                        set |= SNAPPERCL15_NAND_CLE;
+                if (ctrl & NAND_ALE)
+                        set |= SNAPPERCL15_NAND_ALE;
+                nand_state &= ~(SNAPPERCL15_NAND_CEN |
+                                SNAPPERCL15_NAND_CLE |
+                                SNAPPERCL15_NAND_ALE);
+                nand_state |= set;
+                __raw_writew(nand_state, NAND_CTRL_ADDR(chip));
+        }
+        if (cmd != NAND_CMD_NONE)
+                __raw_writew((cmd & 0xff) | nand_state, chip->IO_ADDR_W);
+}
+static int snappercl15_nand_dev_ready(struct mtd_info *mtd)
+{
+        struct nand_chip *chip = mtd->priv;
+        return !!(__raw_readw(NAND_CTRL_ADDR(chip)) & SNAPPERCL15_NAND_RDY);
+}
+static const char *snappercl15_nand_part_probes[] = {"cmdlinepart", NULL};
+static struct mtd_partition snappercl15_nand_parts[] = {
+        {
+                .name           = "Kernel",
+                .offset         = 0,
+                .size           = SZ_2M,
+        },
+        {
+                .name           = "Filesystem",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+static struct platform_nand_data snappercl15_nand_data = {
+        .chip = {
+                .nr_chips               = 1,
+                .part_probe_types       = snappercl15_nand_part_probes,
+                .partitions             = snappercl15_nand_parts,
+                .nr_partitions          = ARRAY_SIZE(snappercl15_nand_parts),
+                .options                = NAND_NO_AUTOINCR,
+                .chip_delay             = 25,
+        },
+        .ctrl = {
+                .dev_ready              = snappercl15_nand_dev_ready,
+                .cmd_ctrl               = snappercl15_nand_cmd_ctrl,
+        },
+};
+static struct resource snappercl15_nand_resource[] = {
+        {
+                .start          = SNAPPERCL15_NAND_BASE,
+                .end            = SNAPPERCL15_NAND_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+static struct platform_device snappercl15_nand_device = {
+        .name                   = "gen_nand",
+        .id                     = -1,
+        .dev.platform_data      = &snappercl15_nand_data,
+        .resource               = snappercl15_nand_resource,
+        .num_resources          = ARRAY_SIZE(snappercl15_nand_resource),
+};
+static struct ep93xx_eth_data snappercl15_eth_data = {
+        .phy_id                 = 1,
+};
+static struct i2c_gpio_platform_data snappercl15_i2c_gpio_data = {
+        .sda_pin                = EP93XX_GPIO_LINE_EEDAT,
+        .sda_is_open_drain      = 0,
+        .scl_pin                = EP93XX_GPIO_LINE_EECLK,
+        .scl_is_open_drain      = 0,
+        .udelay                 = 0,
+        .timeout                = 0,
+};
+static struct i2c_board_info __initdata snappercl15_i2c_data[] = {
+        {
+                /* Audio codec */
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        },
+};
+static struct ep93xxfb_mach_info snappercl15_fb_info = {
+        .num_modes              = EP93XXFB_USE_MODEDB,
+        .bpp                    = 16,
+};
+static void __init snappercl15_init_machine(void)
+{
+        ep93xx_init_devices();
+        ep93xx_register_eth(&snappercl15_eth_data, 1);
+        ep93xx_register_i2c(&snappercl15_i2c_gpio_data, snappercl15_i2c_data,
+                            ARRAY_SIZE(snappercl15_i2c_data));
+        ep93xx_register_fb(&snappercl15_fb_info);
+        platform_device_register(&snappercl15_nand_device);
+}
+MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
+        /* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = snappercl15_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 3bbf40f6d964..71728d36d501 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -427,6 +427,17 @@ static void __init ixp4xx_clocksource_init(void)
 }
 /*
+ * sched_clock()
+ */
+unsigned long long sched_clock(void)
+{
+        cycle_t cyc = ixp4xx_get_cycles(NULL);
+        struct clocksource *cs = &clocksource_ixp4xx;
+        return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
+}
+/*
 * clockevents
 */
 static int ixp4xx_set_next_event(unsigned long evt,
diff --git a/arch/arm/mach-lh7a40x/clocks.c b/arch/arm/mach-lh7a40x/clocks.c
index fcaf876f19b6..0651f96653f9 100644
--- a/arch/arm/mach-lh7a40x/clocks.c
+++ b/arch/arm/mach-lh7a40x/clocks.c
@@ -10,6 +10,8 @@
 #include <mach/hardware.h>
 #include <mach/clocks.h>
 #include <linux/err.h>
+#include <linux/device.h>
+#include <linux/string.h>
 struct module;
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 8f49b2b12608..b22dec4abf78 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -24,8 +24,6 @@
 #include "common.h"
-#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
 static unsigned long ttc_dkb_pin_config[] __initdata = {
        /* UART2 */
        GPIO47_UART2_RXD,
diff --git a/arch/arm/mach-mx2/mxt_td60.c b/arch/arm/mach-mx2/mxt_td60.c
index 03dbbdc98955..8bcc1a5b8829 100644
--- a/arch/arm/mach-mx2/mxt_td60.c
+++ b/arch/arm/mach-mx2/mxt_td60.c
@@ -58,21 +58,6 @@ static unsigned int mxt_td60_pins[] __initdata = {
        PE9_PF_UART3_RXD,
        PE10_PF_UART3_CTS,
        PE11_PF_UART3_RTS,
-        /* UART3 */
-        PB26_AF_UART4_RTS,
-        PB28_AF_UART4_TXD,
-        PB29_AF_UART4_CTS,
-        PB31_AF_UART4_RXD,
-        /* UART4 */
-        PB18_AF_UART5_TXD,
-        PB19_AF_UART5_RXD,
-        PB20_AF_UART5_CTS,
-        PB21_AF_UART5_RTS,
-        /* UART5 */
-        PB10_AF_UART6_TXD,
-        PB12_AF_UART6_CTS,
-        PB11_AF_UART6_RXD,
-        PB13_AF_UART6_RTS,
        /* FEC */
        PD0_AIN_FEC_TXD0,
        PD1_AIN_FEC_TXD1,
@@ -261,12 +246,6 @@ static struct imxuart_platform_data uart_pdata[] = {
                .flags = IMXUART_HAVE_RTSCTS,
        }, {
                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
        },
 };
@@ -278,9 +257,6 @@ static void __init mxt_td60_board_init(void)
        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
        mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
        mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
-        mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
-        mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
-        mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
        mxc_register_device(&mxc_nand_device, &mxt_td60_nand_board_info);
        i2c_register_board_info(0, mxt_td60_i2c_devices,
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index ef26951a5275..6e838b857712 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -173,6 +173,7 @@ DEFINE_CLOCK(pwm4_clk,	 0, CCM_CGCR2,  2, get_rate_ipg, NULL);
 DEFINE_CLOCK(kpp_clk,    0, CCM_CGCR1, 28, get_rate_ipg, NULL);
 DEFINE_CLOCK(tsc_clk,    0, CCM_CGCR2, 13, get_rate_ipg, NULL);
 DEFINE_CLOCK(i2c_clk,    0, CCM_CGCR0,  6, get_rate_i2c, NULL);
+DEFINE_CLOCK(fec_clk,    0, CCM_CGCR0, 23, get_rate_ipg, NULL);
 #define _REGISTER_CLOCK(d, n, c)        \
        {                               \
@@ -204,6 +205,7 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
        _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
+        _REGISTER_CLOCK("fec.0", NULL, fec_clk)
 };
 int __init mx25_clocks_init(unsigned long fref)
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 63511de3a559..9fdeea1c083b 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -419,3 +419,22 @@ int __init mxc_register_gpios(void)
        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
 }
+static struct resource mx25_fec_resources[] = {
+        {
+                .start  = MX25_FEC_BASE_ADDR,
+                .end    = MX25_FEC_BASE_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = MX25_INT_FEC,
+                .end    = MX25_INT_FEC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mx25_fec_device = {
+        .name   = "fec",
+        .id     = 0,
+        .num_resources  = ARRAY_SIZE(mx25_fec_resources),
+        .resource       = mx25_fec_resources,
+};
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index fe6bf88ad1dd..fe5420fcd11f 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -17,3 +17,4 @@ extern struct platform_device mxc_keypad_device;
 extern struct platform_device mxc_i2c_device0;
 extern struct platform_device mxc_i2c_device1;
 extern struct platform_device mxc_i2c_device2;
+extern struct platform_device mx25_fec_device;
diff --git a/arch/arm/mach-mx25/mx25pdk.c b/arch/arm/mach-mx25/mx25pdk.c
index d23ae571c03f..921bc99ea231 100644
--- a/arch/arm/mach-mx25/mx25pdk.c
+++ b/arch/arm/mach-mx25/mx25pdk.c
@@ -18,10 +18,11 @@
 #include <linux/types.h>
 #include <linux/init.h>
+#include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
-#include <linux/smsc911x.h>
+#include <linux/fec.h>
 #include <linux/platform_device.h>
 #include <mach/hardware.h>
@@ -35,16 +36,57 @@
 #include <mach/mx25.h>
 #include <mach/mxc_nand.h>
 #include "devices.h"
-#include <mach/iomux-v3.h>
+#include <mach/iomux.h>
 static struct imxuart_platform_data uart_pdata = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
+static struct pad_desc mx25pdk_pads[] = {
+        MX25_PAD_FEC_MDC__FEC_MDC,
+        MX25_PAD_FEC_MDIO__FEC_MDIO,
+        MX25_PAD_FEC_TDATA0__FEC_TDATA0,
+        MX25_PAD_FEC_TDATA1__FEC_TDATA1,
+        MX25_PAD_FEC_TX_EN__FEC_TX_EN,
+        MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+        MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+        MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+        MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+        MX25_PAD_A17__GPIO_2_3, /* FEC_EN, GPIO 35 */
+        MX25_PAD_D12__GPIO_4_8, /* FEC_RESET_B, GPIO 104 */
+};
+static struct fec_platform_data mx25_fec_pdata = {
+        .phy    = PHY_INTERFACE_MODE_RMII,
+};
+#define FEC_ENABLE_GPIO         35
+#define FEC_RESET_B_GPIO        104
+static void __init mx25pdk_fec_reset(void)
+{
+        gpio_request(FEC_ENABLE_GPIO, "FEC PHY enable");
+        gpio_request(FEC_RESET_B_GPIO, "FEC PHY reset");
+        gpio_direction_output(FEC_ENABLE_GPIO, 0);  /* drop PHY power */
+        gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */
+        udelay(2);
+        /* turn on PHY power and lift reset */
+        gpio_set_value(FEC_ENABLE_GPIO, 1);
+        gpio_set_value(FEC_RESET_B_GPIO, 1);
+}
 static void __init mx25pdk_init(void)
 {
+        mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
+                        ARRAY_SIZE(mx25pdk_pads));
        mxc_register_device(&mxc_uart_device0, &uart_pdata);
        mxc_register_device(&mxc_usbh2, NULL);
+        mx25pdk_fec_reset();
+        mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
 }
 static void __init mx25pdk_timer_init(void)
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index ea8ed109a7c2..28294416b0af 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -49,6 +49,7 @@ config MACH_PCM037_EET
 config MACH_MX31LITE
        bool "Support MX31 LITEKIT (LogicPD)"
        select ARCH_MX31
+        select MXC_ULPI if USB_ULPI
        help
          Include support for MX31 LITEKIT platform. This includes specific
          configurations for the board and its peripherals.
@@ -63,7 +64,7 @@ config MACH_MX31_3DS
 config MACH_MX31MOBOARD
        bool "Support mx31moboard platforms (EPFL Mobots group)"
        select ARCH_MX31
-        select MXC_ULPI
+        select MXC_ULPI if USB_ULPI
        help
          Include support for mx31moboard platform. This includes specific
          configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index bedf5b8d976a..6858a4f9806c 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -65,6 +65,11 @@ static struct map_desc mxc_io_desc[] __initdata = {
                .pfn            = __phys_to_pfn(AIPS2_BASE_ADDR),
                .length         = AIPS2_SIZE,
                .type           = MT_DEVICE_NONSHARED
+        }, {
+                .virtual = SPBA0_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
+                .length = SPBA0_SIZE,
+                .type = MT_DEVICE_NONSHARED
        },
 };
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
index 0497c152be18..3e7bafa2ddbb 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -494,11 +494,6 @@ static void mxc_init_i2c(void)
 */
 static struct map_desc mx31ads_io_desc[] __initdata = {
        {
-                .virtual        = SPBA0_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(SPBA0_BASE_ADDR),
-                .length         = SPBA0_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        }, {
                .virtual        = CS4_BASE_ADDR_VIRT,
                .pfn            = __phys_to_pfn(CS4_BASE_ADDR),
                .length         = CS4_SIZE / 2,
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
index def6b6736594..789b20d1730f 100644
--- a/arch/arm/mach-mx3/mx31lite.c
+++ b/arch/arm/mach-mx3/mx31lite.c
@@ -135,6 +135,7 @@ static struct spi_board_info mc13783_spi_dev __initdata = {
 * USB
 */
+#if defined(CONFIG_USB_ULPI)
 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
@@ -180,6 +181,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
+#endif
 /*
 * NOR flash
@@ -212,11 +214,6 @@ static struct platform_device physmap_flash_device = {
 */
 static struct map_desc mx31lite_io_desc[] __initdata = {
        {
-                .virtual = SPBA0_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
-                .length = SPBA0_SIZE,
-                .type = MT_DEVICE_NONSHARED
-        }, {
                .virtual = CS4_BASE_ADDR_VIRT,
                .pfn = __phys_to_pfn(CS4_BASE_ADDR),
                .length = CS4_SIZE,
@@ -261,11 +258,13 @@ static void __init mxc_board_init(void)
        mxc_register_device(&mxc_spi_device1, &spi1_pdata);
        spi_register_board_info(&mc13783_spi_dev, 1);
+#if defined(CONFIG_USB_ULPI)
        /* USB */
        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
                                USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+#endif
        /* SMSC9117 IRQ pin */
        ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 8fc624f141cb..438428eaf769 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -179,7 +179,7 @@ static int __init devboard_usbh1_init(void)
        usbh1_pdata.otg = otg;
-        return mxc_register_device(&mx31_usbh1, &usbh1_pdata);
+        return mxc_register_device(&mxc_usbh1, &usbh1_pdata);
 }
 /*
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 85184a35e674..1f44b9ccbb0f 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -294,7 +294,7 @@ static int __init marxbot_usbh1_init(void)
        usbh1_pdata.otg = otg;
-        return mxc_register_device(&mx31_usbh1, &usbh1_pdata);
+        return mxc_register_device(&mxc_usbh1, &usbh1_pdata);
 }
 /*
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c
index b70529145936..cfd605d078ec 100644
--- a/arch/arm/mach-mx3/mx31moboard.c
+++ b/arch/arm/mach-mx3/mx31moboard.c
@@ -346,6 +346,8 @@ static struct fsl_usb2_platform_data usb_pdata = {
        .phy_mode       = FSL_USB2_PHY_ULPI,
 };
+#if defined(CONFIG_USB_ULPI)
 #define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6)
 static int moboard_usbh2_hw_init(struct platform_device *pdev)
@@ -392,8 +394,11 @@ static int __init moboard_usbh2_init(void)
        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
                        USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
-        return mxc_register_device(&mx31_usbh2, &usbh2_pdata);
+        return mxc_register_device(&mxc_usbh2, &usbh2_pdata);
 }
+#else
+static inline int moboard_usbh2_init(void) { return 0; }
+#endif
 static struct gpio_led mx31moboard_leds[] = {
diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mx31pdk.c
index 0f7a2f06bc2d..18715f1aa7eb 100644
--- a/arch/arm/mach-mx3/mx31pdk.c
+++ b/arch/arm/mach-mx3/mx31pdk.c
@@ -211,11 +211,6 @@ static int __init mx31pdk_init_expio(void)
 */
 static struct map_desc mx31pdk_io_desc[] __initdata = {
        {
-                .virtual = SPBA0_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
-                .length = SPBA0_SIZE,
-                .type = MT_DEVICE_NONSHARED,
-        }, {
                .virtual = CS5_BASE_ADDR_VIRT,
                .pfn = __phys_to_pfn(CS5_BASE_ADDR),
                .length = CS5_SIZE,
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c
index 6cbaabedf386..5be396917c99 100644
--- a/arch/arm/mach-mx3/pcm037.c
+++ b/arch/arm/mach-mx3/pcm037.c
@@ -322,16 +322,25 @@ static int pcm037_camera_power(struct device *dev, int on)
        return 0;
 }
-static struct i2c_board_info pcm037_i2c_2_devices[] = {
+static struct i2c_board_info pcm037_i2c_camera[] = {
        {
                I2C_BOARD_INFO("mt9t031", 0x5d),
+        }, {
+                I2C_BOARD_INFO("mt9v022", 0x48),
        },
 };
-static struct soc_camera_link iclink = {
+static struct soc_camera_link iclink_mt9v022 = {
+        .bus_id         = 0,            /* Must match with the camera ID */
+        .board_info     = &pcm037_i2c_camera[1],
+        .i2c_adapter_id = 2,
+        .module_name    = "mt9v022",
+};
+static struct soc_camera_link iclink_mt9t031 = {
        .bus_id         = 0,            /* Must match with the camera ID */
        .power          = pcm037_camera_power,
-        .board_info     = &pcm037_i2c_2_devices[0],
+        .board_info     = &pcm037_i2c_camera[0],
        .i2c_adapter_id = 2,
        .module_name    = "mt9t031",
 };
@@ -345,11 +354,19 @@ static struct i2c_board_info pcm037_i2c_devices[] = {
        }
 };
-static struct platform_device pcm037_camera = {
+static struct platform_device pcm037_mt9t031 = {
        .name   = "soc-camera-pdrv",
        .id     = 0,
        .dev    = {
-                .platform_data = &iclink,
+                .platform_data = &iclink_mt9t031,
+        },
+};
+static struct platform_device pcm037_mt9v022 = {
+        .name   = "soc-camera-pdrv",
+        .id     = 1,
+        .dev    = {
+                .platform_data = &iclink_mt9v022,
        },
 };
@@ -449,7 +466,8 @@ static int __init pcm037_camera_alloc_dma(const size_t buf_size)
 static struct platform_device *devices[] __initdata = {
        &pcm037_flash,
        &pcm037_sram_device,
-        &pcm037_camera,
+        &pcm037_mt9t031,
+        &pcm037_mt9v022,
 };
 static struct ipu_platform_data mx3_ipu_data = {
@@ -599,7 +617,7 @@ static void __init mxc_board_init(void)
        if (!ret)
                gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
        else
-                iclink.power = NULL;
+                iclink_mt9t031.power = NULL;
        if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
                mxc_register_device(&mx3_camera, &camera_pdata);
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index ab995a9c606c..65e7b5b85d83 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -599,7 +599,7 @@ static struct clk i2c_ick = {
 static struct omap_clk omap_clks[] = {
        /* non-ULPD clocks */
        CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310 | CK_7XX),
-        CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310 | CK_7XX),
        /* CK_GEN1 clocks */
        CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
        CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
@@ -627,7 +627,7 @@ static struct omap_clk omap_clks[] = {
        CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
        CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
        CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
-        CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310 | CK_7XX),
        CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
        CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
        CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
@@ -658,6 +658,10 @@ static struct omap_clk omap_clks[] = {
        CLK("i2c_omap.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310 | CK_7XX),
        CLK("i2c_omap.1", "ick",        &i2c_ick,       CK_16XX),
        CLK("i2c_omap.1", "ick",        &dummy_ck,      CK_1510 | CK_310 | CK_7XX),
+        CLK("omap1_spi100k.1", "fck",   &dummy_ck,      CK_7XX),
+        CLK("omap1_spi100k.1", "ick",   &dummy_ck,      CK_7XX),
+        CLK("omap1_spi100k.2", "fck",   &dummy_ck,      CK_7XX),
+        CLK("omap1_spi100k.2", "ick",   &dummy_ck,      CK_7XX),
        CLK("omap_uwire", "fck",        &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
        CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
        CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
@@ -674,7 +678,7 @@ static struct omap_clk omap_clks[] = {
 * init
 */
-static struct clk_functions omap1_clk_functions __initdata = {
+static struct clk_functions omap1_clk_functions = {
        .clk_enable             = omap1_clk_enable,
        .clk_disable            = omap1_clk_disable,
        .clk_round_rate         = omap1_clk_round_rate,
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 23ded2d49600..a2d07aa75c9e 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/spi/spi.h>
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
@@ -23,6 +24,7 @@
 #include <plat/mux.h>
 #include <mach/gpio.h>
 #include <plat/mmc.h>
+#include <plat/omap7xx.h>
 /*-------------------------------------------------------------------------*/
@@ -196,6 +198,38 @@ void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
 /*-------------------------------------------------------------------------*/
+/* OMAP7xx SPI support */
+#if defined(CONFIG_SPI_OMAP_100K) || defined(CONFIG_SPI_OMAP_100K_MODULE)
+struct platform_device omap_spi1 = {
+        .name           = "omap1_spi100k",
+        .id             = 1,
+};
+struct platform_device omap_spi2 = {
+        .name           = "omap1_spi100k",
+        .id             = 2,
+};
+static void omap_init_spi100k(void)
+{
+        omap_spi1.dev.platform_data = ioremap(OMAP7XX_SPI1_BASE, 0x7ff);
+        if (omap_spi1.dev.platform_data)
+                platform_device_register(&omap_spi1);
+        omap_spi2.dev.platform_data = ioremap(OMAP7XX_SPI2_BASE, 0x7ff);
+        if (omap_spi2.dev.platform_data)
+                platform_device_register(&omap_spi2);
+}
+#else
+static inline void omap_init_spi100k(void)
+{
+}
+#endif
+/*-------------------------------------------------------------------------*/
 #if defined(CONFIG_OMAP_STI)
 #define OMAP1_STI_BASE          0xfffea000
@@ -263,6 +297,7 @@ static int __init omap1_init_devices(void)
        omap_init_mbox();
        omap_init_rtc();
+        omap_init_spi100k();
        omap_init_sti();
        return 0;
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 07212cc621ae..84341377232d 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -62,6 +62,14 @@ MUX_CFG_7XX("MMC_7XX_DAT0",        2,   17,    0,   16,   1, 0)
 /* I2C interface */
 MUX_CFG_7XX("I2C_7XX_SCL",         5,    1,    0,    0,   1, 0)
 MUX_CFG_7XX("I2C_7XX_SDA",         5,    5,    0,    0,   1, 0)
+/* SPI pins */
+MUX_CFG_7XX("SPI_7XX_1",           6,    5,    4,    4,   1, 0)
+MUX_CFG_7XX("SPI_7XX_2",           6,    9,    4,    8,   1, 0)
+MUX_CFG_7XX("SPI_7XX_3",           6,   13,    4,   12,   1, 0)
+MUX_CFG_7XX("SPI_7XX_4",           6,   17,    4,   16,   1, 0)
+MUX_CFG_7XX("SPI_7XX_5",           8,   25,    0,   24,   0, 0)
+MUX_CFG_7XX("SPI_7XX_6",           9,    5,    0,    4,   0, 0)
 };
 #define OMAP7XX_PINS_SZ         ARRAY_SIZE(omap7xx_pins)
 #else
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 10eafa70a909..606bf04f51b6 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -80,6 +80,7 @@ config MACH_OVERO
 config MACH_OMAP3EVM
        bool "OMAP 3530 EVM board"
        depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 config MACH_OMAP3517EVM
        bool "OMAP3517/ AM3517 EVM board"
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 8dd277c36661..1e3dfb652acc 100755
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -63,21 +63,21 @@ static int board_keymap[] = {
        KEY(5, 1, KEY_H),
        KEY(5, 2, KEY_J),
        KEY(5, 3, KEY_F3),
+        KEY(5, 4, KEY_UNKNOWN),
        KEY(5, 5, KEY_VOLUMEDOWN),
        KEY(5, 6, KEY_M),
-        KEY(5, 7, KEY_ENTER),
+        KEY(5, 7, KEY_RIGHT),
        KEY(6, 0, KEY_Q),
        KEY(6, 1, KEY_A),
        KEY(6, 2, KEY_N),
        KEY(6, 3, KEY_BACKSPACE),
        KEY(6, 6, KEY_P),
-        KEY(6, 7, KEY_SELECT),
+        KEY(6, 7, KEY_UP),
        KEY(7, 0, KEY_PROG1),   /*MACRO 1 <User defined> */
        KEY(7, 1, KEY_PROG2),   /*MACRO 2 <User defined> */
        KEY(7, 2, KEY_PROG3),   /*MACRO 3 <User defined> */
        KEY(7, 3, KEY_PROG4),   /*MACRO 4 <User defined> */
-        KEY(7, 5, KEY_RIGHT),
+        KEY(7, 6, KEY_SELECT),
-        KEY(7, 6, KEY_UP),
        KEY(7, 7, KEY_DOWN)
 };
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index d0e3fb7f9298..5420356eb407 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -449,40 +449,78 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 #ifdef CONFIG_CPU_FREQ
 /*
 * Walk PRCM rate table and fillout cpufreq freq_table
+ * XXX This should be replaced by an OPP layer in the near future
 */
-static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
+static struct cpufreq_frequency_table *freq_table;
 void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
 {
-        struct prcm_config *prcm;
+        const struct prcm_config *prcm;
+        long sys_ck_rate;
        int i = 0;
+        int tbl_sz = 0;
+        sys_ck_rate = clk_get_rate(sclk);
        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
                if (!(prcm->flags & cpu_mask))
                        continue;
-                if (prcm->xtal_speed != sys_ck.rate)
+                if (prcm->xtal_speed != sys_ck_rate)
                        continue;
                /* don't put bypass rates in table */
                if (prcm->dpll_speed == prcm->xtal_speed)
                        continue;
-                freq_table[i].index = i;
+                tbl_sz++;
-                freq_table[i].frequency = prcm->mpu_speed / 1000;
-                i++;
        }
-        if (i == 0) {
+        /*
-                printk(KERN_WARNING "%s: failed to initialize frequency "
+         * XXX Ensure that we're doing what CPUFreq expects for this error
-                       "table\n", __func__);
+         * case and the following one
+         */
+        if (tbl_sz == 0) {
+                pr_warning("%s: no matching entries in rate_table\n",
+                           __func__);
+                return;
+        }
+        /* Include the CPUFREQ_TABLE_END terminator entry */
+        tbl_sz++;
+        freq_table = kzalloc(sizeof(struct cpufreq_frequency_table) * tbl_sz,
+                             GFP_ATOMIC);
+        if (!freq_table) {
+                pr_err("%s: could not kzalloc frequency table\n", __func__);
                return;
        }
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck_rate)
+                        continue;
+                /* don't put bypass rates in table */
+                if (prcm->dpll_speed == prcm->xtal_speed)
+                        continue;
+                freq_table[i].index = i;
+                freq_table[i].frequency = prcm->mpu_speed / 1000;
+                i++;
+        }
        freq_table[i].index = i;
        freq_table[i].frequency = CPUFREQ_TABLE_END;
        *table = &freq_table[0];
 }
+void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+        kfree(freq_table);
+}
 #endif
 struct clk_functions omap2_clk_functions = {
@@ -494,6 +532,7 @@ struct clk_functions omap2_clk_functions = {
        .clk_disable_unused     = omap2_clk_disable_unused,
 #ifdef  CONFIG_CPU_FREQ
        .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
+        .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table,
 #endif
 };
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index ded32364f32b..d4217b93e10b 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -34,7 +34,6 @@
 #include <asm/div64.h>
 #include <asm/clkdev.h>
-#include <plat/sdrc.h>
 #include "clock.h"
 #include "clock34xx.h"
 #include "sdrc.h"
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c
index 8bdcc9cc7f9a..c6031d74d6f6 100644
--- a/arch/arm/mach-omap2/clock34xx_data.c
+++ b/arch/arm/mach-omap2/clock34xx_data.c
@@ -776,6 +776,8 @@ static struct clk dpll4_m5_ck = {
        .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
        .clksel         = div16_dpll4_clksel,
        .clkdm_name     = "dpll4_clkdm",
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate,
        .recalc         = &omap2_clksel_recalc,
 };
@@ -1500,6 +1502,7 @@ static struct clk uart2_fck = {
        .parent         = &core_48m_fck,
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
        .recalc         = &followparent_recalc,
 };
@@ -1509,6 +1512,7 @@ static struct clk uart1_fck = {
        .parent         = &core_48m_fck,
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
        .recalc         = &followparent_recalc,
 };
@@ -2745,7 +2749,7 @@ static struct clk mcbsp4_ick = {
 };
 static const struct clksel mcbsp_234_clksel[] = {
-        { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+        { .parent = &per_96m_fck,  .rates = common_mcbsp_96m_rates },
        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
        { .parent = NULL }
 };
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 1a45ed1e8ba1..dd285f001467 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -559,7 +559,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
         * downstream clocks for debugging purposes?
         */
-        if (!clkdm || !clk)
+        if (!clkdm || !clk || !clkdm->clktrctrl_mask)
                return -EINVAL;
        if (atomic_inc_return(&clkdm->usecount) > 1)
@@ -610,7 +610,7 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
         * downstream clocks for debugging purposes?
         */
-        if (!clkdm || !clk)
+        if (!clkdm || !clk || !clkdm->clktrctrl_mask)
                return -EINVAL;
 #ifdef DEBUG
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index a8749e8017b9..5a7996402c53 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -33,7 +33,6 @@
 #include <plat/sdrc.h>
 #include <plat/gpmc.h>
 #include <plat/serial.h>
-#include <plat/mux.h>
 #include <plat/vram.h>
 #include "clock.h"
@@ -73,21 +72,21 @@ static struct map_desc omap24xx_io_desc[] __initdata = {
 #ifdef CONFIG_ARCH_OMAP2420
 static struct map_desc omap242x_io_desc[] __initdata = {
        {
-                .virtual        = DSP_MEM_24XX_VIRT,
+                .virtual        = DSP_MEM_2420_VIRT,
-                .pfn            = __phys_to_pfn(DSP_MEM_24XX_PHYS),
+                .pfn            = __phys_to_pfn(DSP_MEM_2420_PHYS),
-                .length         = DSP_MEM_24XX_SIZE,
+                .length         = DSP_MEM_2420_SIZE,
                .type           = MT_DEVICE
        },
        {
-                .virtual        = DSP_IPI_24XX_VIRT,
+                .virtual        = DSP_IPI_2420_VIRT,
-                .pfn            = __phys_to_pfn(DSP_IPI_24XX_PHYS),
+                .pfn            = __phys_to_pfn(DSP_IPI_2420_PHYS),
-                .length         = DSP_IPI_24XX_SIZE,
+                .length         = DSP_IPI_2420_SIZE,
                .type           = MT_DEVICE
        },
        {
-                .virtual        = DSP_MMU_24XX_VIRT,
+                .virtual        = DSP_MMU_2420_VIRT,
-                .pfn            = __phys_to_pfn(DSP_MMU_24XX_PHYS),
+                .pfn            = __phys_to_pfn(DSP_MMU_2420_PHYS),
-                .length         = DSP_MMU_24XX_SIZE,
+                .length         = DSP_MMU_2420_SIZE,
                .type           = MT_DEVICE
        },
 };
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index e071b3fd1878..459ef23ab8a8 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -994,8 +994,10 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
        }
 #ifdef CONFIG_OMAP_MUX
-        omap_mux_package_fixup(package_subset, superset);
+        if (package_subset)
-        omap_mux_package_init_balls(package_balls, superset);
+                omap_mux_package_fixup(package_subset, superset);
+        if (package_balls)
+                omap_mux_package_init_balls(package_balls, superset);
        omap_mux_set_cmdline_signals();
        omap_mux_set_board_signals(board_mux);
 #endif
diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c
index 126a9396b3a8..e6dda694fd5c 100644
--- a/arch/arm/mach-omap2/opp2420_data.c
+++ b/arch/arm/mach-omap2/opp2420_data.c
@@ -9,45 +9,47 @@
 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
 * These configurations are characterized by voltage and speed for clocks.
 * The device is only validated for certain combinations. One way to express
- * these combinations is via the 'ratio's' which the clocks operate with
+ * these combinations is via the 'ratios' which the clocks operate with
 * respect to each other. These ratio sets are for a given voltage/DPLL
- * setting. All configurations can be described by a DPLL setting and a ratio
+ * setting. All configurations can be described by a DPLL setting and a ratio.
- * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
- *
- * 2430 differs from 2420 in that there are no more phase synchronizers used.
- * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
- * 2430 (iva2.1, NOdsp, mdm)
 *
 * XXX Missing voltage data.
+ * XXX Missing 19.2MHz sys_clk rate sets (needed for N800/N810)
 *
 * THe format described in this file is deprecated.  Once a reasonable
 * OPP API exists, the data in this file should be converted to use it.
 *
 * This is technically part of the OMAP2xxx clock code.
+ *
+ * Considerable work is still needed to fully support dynamic frequency
+ * changes on OMAP2xxx-series chips.  Readers interested in such a
+ * project are encouraged to review the Maemo Diablo RX-34 and RX-44
+ * kernel source at:
+ *     http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
 */
 #include "opp2xxx.h"
 #include "sdrc.h"
 #include "clock.h"
-/*-------------------------------------------------------------------------
+/*
- * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+ * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 *
- * Filling in table based on H4 boards and 2430-SDPs variants available.
+ * Filling in table based on H4 boards available.  There are quite a
- * There are quite a few more rates combinations which could be defined.
+ * few more rate combinations which could be defined.
 *
- * When multiple values are defined the start up will try and choose the
+ * When multiple values are defined the start up will try and choose
- * fastest one. If a 'fast' value is defined, then automatically, the /2
+ * the fastest one. If a 'fast' value is defined, then automatically,
- * one should be included as it can be used.    Generally having more that
+ * the /2 one should be included as it can be used.  Generally having
- * one fast set does not make sense, as static timings need to be changed
+ * more than one fast set does not make sense, as static timings need
- * to change the set.    The exception is the bypass setting which is
+ * to be changed to change the set.  The exception is the bypass
- * availble for low power bypass.
+ * setting which is available for low power bypass.
 *
 * Note: This table needs to be sorted, fastest to slowest.
- *-------------------------------------------------------------------------*/
+ **/
 const struct prcm_config omap2420_rate_table[] = {
        /* PRCM I - FAST */
        {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c
index edb81672c844..1b9596ae201e 100644
--- a/arch/arm/mach-omap2/opp2430_data.c
+++ b/arch/arm/mach-omap2/opp2430_data.c
@@ -1,5 +1,5 @@
 /*
- * opp2420_data.c - old-style "OPP" table for OMAP2420
+ * opp2430_data.c - old-style "OPP" table for OMAP2430
 *
 * Copyright (C) 2005-2009 Texas Instruments, Inc.
 * Copyright (C) 2004-2009 Nokia Corporation
@@ -9,16 +9,16 @@
 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
 * These configurations are characterized by voltage and speed for clocks.
 * The device is only validated for certain combinations. One way to express
- * these combinations is via the 'ratio's' which the clocks operate with
+ * these combinations is via the 'ratios' which the clocks operate with
 * respect to each other. These ratio sets are for a given voltage/DPLL
- * setting. All configurations can be described by a DPLL setting and a ratio
+ * setting. All configurations can be described by a DPLL setting and a ratio.
- * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
 *
 * 2430 differs from 2420 in that there are no more phase synchronizers used.
 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
 * 2430 (iva2.1, NOdsp, mdm)
 *
 * XXX Missing voltage data.
+ * XXX Missing 19.2MHz sys_clk rate sets.
 *
 * THe format described in this file is deprecated.  Once a reasonable
 * OPP API exists, the data in this file should be converted to use it.
@@ -30,24 +30,24 @@
 #include "sdrc.h"
 #include "clock.h"
-/*-------------------------------------------------------------------------
+/*
- * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+ * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 *
- * Filling in table based on H4 boards and 2430-SDPs variants available.
+ * Filling in table based on 2430-SDPs variants available.  There are
- * There are quite a few more rates combinations which could be defined.
+ * quite a few more rate combinations which could be defined.
 *
- * When multiple values are defined the start up will try and choose the
+ * When multiple values are defined the start up will try and choose
- * fastest one. If a 'fast' value is defined, then automatically, the /2
+ * the fastest one. If a 'fast' value is defined, then automatically,
- * one should be included as it can be used.    Generally having more that
+ * the /2 one should be included as it can be used.  Generally having
- * one fast set does not make sense, as static timings need to be changed
+ * more than one fast set does not make sense, as static timings need
- * to change the set.    The exception is the bypass setting which is
+ * to be changed to change the set.  The exception is the bypass
- * availble for low power bypass.
+ * setting which is available for low power bypass.
 *
 * Note: This table needs to be sorted, fastest to slowest.
- *-------------------------------------------------------------------------*/
+ */
 const struct prcm_config omap2430_rate_table[] = {
        /* PRCM #4 - ratio2 (ES2.1) - FAST */
        {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 81ed252a0f8a..c6cc809afb79 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -124,8 +124,8 @@ static void omap3_core_save_context(void)
        control_padconf_off |= START_PADCONF_SAVE;
        omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
        /* wait for the save to complete */
-        while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
+        while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
-                        & PADCONF_SAVE_DONE)
+                        & PADCONF_SAVE_DONE))
                ;
        /* Save the Interrupt controller context */
        omap_intc_save_context();
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 19805a7de06c..8c964bec8159 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -125,6 +125,13 @@ static struct plat_serial8250_port serial_platform_data3[] = {
        }
 };
 #endif
+static inline unsigned int __serial_read_reg(struct uart_port *up,
+                                           int offset)
+{
+        offset <<= up->regshift;
+        return (unsigned int)__raw_readb(up->membase + offset);
+}
 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
                                           int offset)
 {
@@ -583,11 +590,12 @@ static unsigned int serial_in_override(struct uart_port *up, int offset)
 {
        if (UART_RX == offset) {
                unsigned int lsr;
-                lsr = serial_read_reg(omap_uart[up->line].p, UART_LSR);
+                lsr = __serial_read_reg(up, UART_LSR);
                if (!(lsr & UART_LSR_DR))
                        return -EPERM;
        }
-        return serial_read_reg(omap_uart[up->line].p, offset);
+        return __serial_read_reg(up, offset);
 }
 void __init omap_serial_early_init(void)
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 8a0837ea0294..dee92182749b 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -37,6 +37,8 @@ config MACH_ZYLONITE320
 config MACH_LITTLETON
        bool "PXA3xx Form Factor Platform (aka Littleton)"
        select PXA3xx
+        select CPU_PXA300
+        select CPU_PXA310
        select PXA_SSP
 config MACH_TAVOREVB
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 50f1297bf5ac..e741bf1bfb2d 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -250,20 +250,17 @@
 #define cpu_is_pxa930()                                 \
        ({                                              \
-                unsigned int id = read_cpuid(CPUID_ID); \
+                __cpu_is_pxa930(read_cpuid_id());       \
-                __cpu_is_pxa930(id);                    \
         })
 #define cpu_is_pxa935()                                 \
        ({                                              \
-                unsigned int id = read_cpuid(CPUID_ID); \
+                __cpu_is_pxa935(read_cpuid_id());       \
-                __cpu_is_pxa935(id);                    \
         })
 #define cpu_is_pxa950()                                 \
        ({                                              \
-                unsigned int id = read_cpuid(CPUID_ID); \
+                __cpu_is_pxa950(read_cpuid_id());       \
-                __cpu_is_pxa950(id);                    \
         })
diff --git a/arch/arm/mach-pxa/include/mach/zylonite.h b/arch/arm/mach-pxa/include/mach/zylonite.h
index bf6785adccf4..9edf645368d6 100644
--- a/arch/arm/mach-pxa/include/mach/zylonite.h
+++ b/arch/arm/mach-pxa/include/mach/zylonite.h
@@ -8,13 +8,6 @@
 /* the following variables are processor specific and initialized
 * by the corresponding zylonite_pxa3xx_init()
 */
-struct platform_mmc_slot {
-        int gpio_cd;
-        int gpio_wp;
-};
-extern struct platform_mmc_slot zylonite_mmc_slot[];
 extern int gpio_eth_irq;
 extern int gpio_debug_led1;
 extern int gpio_debug_led2;
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index f28c1715b910..fa527b258d61 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -110,6 +110,12 @@ static mfp_cfg_t littleton_mfp_cfg[] __initdata = {
        GPIO7_MMC1_CLK,
        GPIO8_MMC1_CMD,
        GPIO15_GPIO, /* card detect */
+        /* UART3 */
+        GPIO107_UART3_CTS,
+        GPIO108_UART3_RTS,
+        GPIO109_UART3_TXD,
+        GPIO110_UART3_RXD,
 };
 static struct resource smc91x_resources[] = {
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 8a38d604dc77..189f330719a2 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -381,7 +381,7 @@ err:
        return ret;
 }
-static int magician_backlight_notify(int brightness)
+static int magician_backlight_notify(struct device *dev, int brightness)
 {
        gpio_set_value(EGPIO_MAGICIAN_BL_POWER, brightness);
        if (brightness >= 200) {
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 59140217890a..e100af78b166 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -270,7 +270,7 @@ err:
        return ret;
 }
-static int palmld_backlight_notify(int brightness)
+static int palmld_backlight_notify(struct device *dev, int brightness)
 {
        gpio_set_value(GPIO_NR_PALMLD_BL_POWER, brightness);
        gpio_set_value(GPIO_NR_PALMLD_LCD_POWER, brightness);
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 7f89ca20f13a..8fe3ec27568f 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -209,7 +209,7 @@ err:
        return ret;
 }
-static int palmt5_backlight_notify(int brightness)
+static int palmt5_backlight_notify(struct device *dev, int brightness)
 {
        gpio_set_value(GPIO_NR_PALMT5_BL_POWER, brightness);
        gpio_set_value(GPIO_NR_PALMT5_LCD_POWER, brightness);
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index 308417592007..b992f07ece21 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -185,7 +185,7 @@ err:
        return ret;
 }
-static int palmtc_backlight_notify(int brightness)
+static int palmtc_backlight_notify(struct device *dev, int brightness)
 {
        /* backlight is on when GPIO16 AF0 is high */
        gpio_set_value(GPIO_NR_PALMTC_BL_POWER, brightness);
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index 265d62bae7de..dc728d6ab94e 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -181,7 +181,7 @@ err:
        return ret;
 }
-static int palmte2_backlight_notify(int brightness)
+static int palmte2_backlight_notify(struct device *dev, int brightness)
 {
        gpio_set_value(GPIO_NR_PALMTE2_BL_POWER, brightness);
        gpio_set_value(GPIO_NR_PALMTE2_LCD_POWER, brightness);
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index 606eb7e8a17e..b433bb496711 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -375,7 +375,7 @@ err:
        return ret;
 }
-static int treo_backlight_notify(int brightness)
+static int treo_backlight_notify(struct device *dev, int brightness)
 {
        gpio_set_value(GPIO_NR_TREO_BL_POWER, brightness);
        return TREO_MAX_INTENSITY - brightness;
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 7bf18c2f002f..b37a025c0b7b 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -269,7 +269,7 @@ err:
        return ret;
 }
-static int palmtx_backlight_notify(int brightness)
+static int palmtx_backlight_notify(struct device *dev, int brightness)
 {
        gpio_set_value(GPIO_NR_PALMTX_BL_POWER, brightness);
        gpio_set_value(GPIO_NR_PALMTX_LCD_POWER, brightness);
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index d787ac7cfdd8..1c5d68a94511 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -196,7 +196,7 @@ err:
        return ret;
 }
-static int palmz72_backlight_notify(int brightness)
+static int palmz72_backlight_notify(struct device *dev, int brightness)
 {
        gpio_set_value(GPIO_NR_PALMZ72_BL_POWER, brightness);
        gpio_set_value(GPIO_NR_PALMZ72_LCD_POWER, brightness);
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index e5eeb3a62d01..c2b938a4d5c9 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -293,7 +293,7 @@ static struct pxamci_platform_data poodle_mci_platform_data = {
        .init                   = poodle_mci_init,
        .setpower               = poodle_mci_setpower,
        .exit                   = poodle_mci_exit,
-        .gpio_card_detect       = POODLE_IRQ_GPIO_nSD_DETECT,
+        .gpio_card_detect       = POODLE_GPIO_nSD_DETECT,
        .gpio_card_ro           = POODLE_GPIO_nSD_WP,
        .gpio_power             = -1,
 };
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 4b50f144fa48..28352c0b8c34 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -389,13 +389,13 @@ static struct gpio_keys_button spitz_gpio_keys[] = {
                .type   = EV_SW,
                .code   = 0,
                .gpio   = SPITZ_GPIO_SWA,
-                .desc   = "Display Down",
+                .desc   = "Display Down",
        },
        {
                .type   = EV_SW,
                .code   = 1,
                .gpio   = SPITZ_GPIO_SWB,
-                .desc   = "Lid Closed",
+                .desc   = "Lid Closed",
        },
 };
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 5352b4e5a7dd..89f258c9e126 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -379,7 +379,7 @@ err_request_bckl:
        return ret;
 }
-static int viper_backlight_notify(int brightness)
+static int viper_backlight_notify(struct device *dev, int brightness)
 {
        gpio_set_value(VIPER_LCD_EN_GPIO, !!brightness);
        gpio_set_value(VIPER_BCKLIGHT_EN_GPIO, !!brightness);
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 5b986a8bd9e6..75f2a37f945d 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -25,6 +25,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pca953x.h>
+#include <linux/apm-emulation.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -626,8 +627,27 @@ static void zeus_power_off(void)
        pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP);
 }
-int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
+#ifdef CONFIG_APM_EMULATION
-                      unsigned ngpio, void *context)
+static void zeus_get_power_status(struct apm_power_info *info)
+{
+        /* Power supply is always present */
+        info->ac_line_status    = APM_AC_ONLINE;
+        info->battery_status    = APM_BATTERY_STATUS_NOT_PRESENT;
+        info->battery_flag      = APM_BATTERY_FLAG_NOT_PRESENT;
+}
+static inline void zeus_setup_apm(void)
+{
+        apm_get_power_status = zeus_get_power_status;
+}
+#else
+static inline void zeus_setup_apm(void)
+{
+}
+#endif
+static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
+                             unsigned ngpio, void *context)
 {
        int i;
        u8 pcb_info = 0;
@@ -726,9 +746,18 @@ static mfp_cfg_t zeus_pin_config[] __initdata = {
        GPIO99_GPIO,            /* CF RDY */
 };
+/*
+ * DM9k MSCx settings:  SRAM, 16 bits
+ *                      17 cycles delay first access
+ *                       5 cycles delay next access
+ *                      13 cycles recovery time
+ *                      faster device
+ */
+#define DM9K_MSC_VALUE          0xe4c9
 static void __init zeus_init(void)
 {
-        u16 dm9000_msc = 0xe279;
+        u16 dm9000_msc = DM9K_MSC_VALUE;
        system_rev = __raw_readw(ZEUS_CPLD_VERSION);
        pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
@@ -738,6 +767,7 @@ static void __init zeus_init(void)
        MSC1 = (MSC1 & 0xffff0000) | dm9000_msc;
        pm_power_off = zeus_power_off;
+        zeus_setup_apm();
        pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index b66e9e2d06e7..2b4043c04d0c 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -36,9 +36,6 @@
 #include "devices.h"
 #include "generic.h"
-#define MAX_SLOTS       3
-struct platform_mmc_slot zylonite_mmc_slot[MAX_SLOTS];
 int gpio_eth_irq;
 int gpio_debug_led1;
 int gpio_debug_led2;
@@ -220,84 +217,28 @@ static inline void zylonite_init_lcd(void) {}
 #endif
 #if defined(CONFIG_MMC)
-static int zylonite_mci_ro(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        return gpio_get_value(zylonite_mmc_slot[pdev->id].gpio_wp);
-}
-static int zylonite_mci_init(struct device *dev,
-                             irq_handler_t zylonite_detect_int,
-                             void *data)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        int err, cd_irq, gpio_cd, gpio_wp;
-        cd_irq = gpio_to_irq(zylonite_mmc_slot[pdev->id].gpio_cd);
-        gpio_cd = zylonite_mmc_slot[pdev->id].gpio_cd;
-        gpio_wp = zylonite_mmc_slot[pdev->id].gpio_wp;
-        /*
-         * setup GPIO for Zylonite MMC controller
-         */
-        err = gpio_request(gpio_cd, "mmc card detect");
-        if (err)
-                goto err_request_cd;
-        gpio_direction_input(gpio_cd);
-        err = gpio_request(gpio_wp, "mmc write protect");
-        if (err)
-                goto err_request_wp;
-        gpio_direction_input(gpio_wp);
-        err = request_irq(cd_irq, zylonite_detect_int,
-                          IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
-                          "MMC card detect", data);
-        if (err) {
-                printk(KERN_ERR "%s: MMC/SD/SDIO: "
-                                "can't request card detect IRQ\n", __func__);
-                goto err_request_irq;
-        }
-        return 0;
-err_request_irq:
-        gpio_free(gpio_wp);
-err_request_wp:
-        gpio_free(gpio_cd);
-err_request_cd:
-        return err;
-}
-static void zylonite_mci_exit(struct device *dev, void *data)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        int cd_irq, gpio_cd, gpio_wp;
-        cd_irq = gpio_to_irq(zylonite_mmc_slot[pdev->id].gpio_cd);
-        gpio_cd = zylonite_mmc_slot[pdev->id].gpio_cd;
-        gpio_wp = zylonite_mmc_slot[pdev->id].gpio_wp;
-        free_irq(cd_irq, data);
-        gpio_free(gpio_cd);
-        gpio_free(gpio_wp);
-}
 static struct pxamci_platform_data zylonite_mci_platform_data = {
        .detect_delay   = 20,
        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
-        .init           = zylonite_mci_init,
+        .gpio_card_detect = EXT_GPIO(0),
-        .exit           = zylonite_mci_exit,
+        .gpio_card_ro   = EXT_GPIO(2),
-        .get_ro         = zylonite_mci_ro,
-        .gpio_card_detect = -1,
-        .gpio_card_ro   = -1,
        .gpio_power     = -1,
 };
 static struct pxamci_platform_data zylonite_mci2_platform_data = {
        .detect_delay   = 20,
        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
+        .gpio_card_detect = EXT_GPIO(1),
+        .gpio_card_ro   = EXT_GPIO(3),
+        .gpio_power     = -1,
+};
+static struct pxamci_platform_data zylonite_mci3_platform_data = {
+        .detect_delay   = 20,
+        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
+        .gpio_card_detect = EXT_GPIO(30),
+        .gpio_card_ro   = EXT_GPIO(31),
+        .gpio_power     = -1,
 };
 static void __init zylonite_init_mmc(void)
@@ -305,7 +246,7 @@ static void __init zylonite_init_mmc(void)
        pxa_set_mci_info(&zylonite_mci_platform_data);
        pxa3xx_set_mci2_info(&zylonite_mci2_platform_data);
        if (cpu_is_pxa310())
-                pxa3xx_set_mci3_info(&zylonite_mci_platform_data);
+                pxa3xx_set_mci3_info(&zylonite_mci3_platform_data);
 }
 #else
 static inline void zylonite_init_mmc(void) {}
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index 84095440a878..3aa73b3e33f2 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -129,8 +129,8 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
        GPIO22_I2C_SDA,
        /* GPIO */
-        GPIO18_GPIO,    /* GPIO Expander #0 INT_N */
+        GPIO18_GPIO | MFP_PULL_HIGH,    /* GPIO Expander #0 INT_N */
-        GPIO19_GPIO,    /* GPIO Expander #1 INT_N */
+        GPIO19_GPIO | MFP_PULL_HIGH,    /* GPIO Expander #1 INT_N */
 };
 static mfp_cfg_t pxa300_mfp_cfg[] __initdata = {
@@ -258,10 +258,6 @@ void __init zylonite_pxa300_init(void)
                /* detect LCD panel */
                zylonite_detect_lcd_panel();
-                /* MMC card detect & write protect for controller 0 */
-                zylonite_mmc_slot[0].gpio_cd  = EXT_GPIO(0);
-                zylonite_mmc_slot[0].gpio_wp  = EXT_GPIO(2);
                /* WM9713 IRQ */
                wm9713_irq = mfp_to_gpio(MFP_PIN_GPIO26);
@@ -276,10 +272,6 @@ void __init zylonite_pxa300_init(void)
        if (cpu_is_pxa310()) {
                pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa310_mfp_cfg));
                gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO102);
-                /* MMC card detect & write protect for controller 2 */
-                zylonite_mmc_slot[2].gpio_cd = EXT_GPIO(30);
-                zylonite_mmc_slot[2].gpio_wp = EXT_GPIO(31);
        }
        /* GPIOs for Debug LEDs */
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
index 60d08f23f5e4..9942bac4cf7d 100644
--- a/arch/arm/mach-pxa/zylonite_pxa320.c
+++ b/arch/arm/mach-pxa/zylonite_pxa320.c
@@ -209,10 +209,6 @@ void __init zylonite_pxa320_init(void)
                gpio_debug_led1 = mfp_to_gpio(MFP_PIN_GPIO1_2);
                gpio_debug_led2 = mfp_to_gpio(MFP_PIN_GPIO4_2);
-                /* MMC card detect & write protect for controller 0 */
-                zylonite_mmc_slot[0].gpio_cd  = mfp_to_gpio(MFP_PIN_GPIO1);
-                zylonite_mmc_slot[0].gpio_wp  = mfp_to_gpio(MFP_PIN_GPIO5);
                /* WM9713 IRQ */
                wm9713_irq = mfp_to_gpio(MFP_PIN_GPIO15);
        }
diff --git a/arch/arm/mach-realview/include/mach/board-pb1176.h b/arch/arm/mach-realview/include/mach/board-pb1176.h
index 34b80b7d40b8..2f5ccb298858 100644
--- a/arch/arm/mach-realview/include/mach/board-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/board-pb1176.h
@@ -74,8 +74,8 @@
 #define REALVIEW_PB1176_L220_BASE               0x10110000 /* L220 registers */
 /*
- * Control register SYS_RESETCTL is set to 1 to force a soft reset
+ * Control register SYS_RESETCTL Bit 8 is set to 1 to force a soft reset
 */
-#define REALVIEW_PB1176_SYS_LOCKVAL_RSTCTL    0x0100
+#define REALVIEW_PB1176_SYS_SOFT_RESET    0x0100
 #endif  /* __ASM_ARCH_BOARD_PB1176_H */
diff --git a/arch/arm/mach-realview/include/mach/platform.h b/arch/arm/mach-realview/include/mach/platform.h
index 4f46bf71e752..86c0c4435a46 100644
--- a/arch/arm/mach-realview/include/mach/platform.h
+++ b/arch/arm/mach-realview/include/mach/platform.h
@@ -140,7 +140,7 @@
 *     SYS_CLD, SYS_BOOTCS
 */
 #define REALVIEW_SYS_LOCK_LOCKED    (1 << 16)
-#define REALVIEW_SYS_LOCKVAL_MASK       0xA05F         /* Enable write access */
+#define REALVIEW_SYS_LOCK_VAL   0xA05F         /* Enable write access */
 /*
 * REALVIEW_SYS_FLASH
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 917f8ca3abff..7d857d300558 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -381,6 +381,20 @@ static struct sys_timer realview_eb_timer = {
        .init           = realview_eb_timer_init,
 };
+static void realview_eb_reset(char mode)
+{
+        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
+        void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
+        /*
+         * To reset, we hit the on-board reset register
+         * in the system FPGA
+         */
+        __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
+        if (core_tile_eb11mp())
+                __raw_writel(0x0008, reset_ctrl);
+}
 static void __init realview_eb_init(void)
 {
        int i;
@@ -408,6 +422,7 @@ static void __init realview_eb_init(void)
 #ifdef CONFIG_LEDS
        leds_event = realview_leds_event;
 #endif
+        realview_reset = realview_eb_reset;
 }
 MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 7fb726d5f8b9..44392e51dd50 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -292,12 +292,10 @@ static struct sys_timer realview_pb1176_timer = {
 static void realview_pb1176_reset(char mode)
 {
-        void __iomem *hdr_ctrl = __io_address(REALVIEW_SYS_BASE) +
+        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
-                REALVIEW_SYS_RESETCTL_OFFSET;
+        void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
-        void __iomem *rst_hdr_ctrl = __io_address(REALVIEW_SYS_BASE) +
+        __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
-                REALVIEW_SYS_LOCK_OFFSET;
+        __raw_writel(REALVIEW_PB1176_SYS_SOFT_RESET, reset_ctrl);
-        __raw_writel(REALVIEW_SYS_LOCKVAL_MASK, rst_hdr_ctrl);
-        __raw_writel(REALVIEW_PB1176_SYS_LOCKVAL_RSTCTL, hdr_ctrl);
 }
 static void realview_pb1176_fixup(struct machine_desc *mdesc,
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 9bbbfc05f225..3e02731af959 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -301,17 +301,16 @@ static struct sys_timer realview_pb11mp_timer = {
 static void realview_pb11mp_reset(char mode)
 {
-        void __iomem *hdr_ctrl = __io_address(REALVIEW_SYS_BASE) +
+        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
-                REALVIEW_SYS_RESETCTL_OFFSET;
+        void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
-        unsigned int val;
        /*
         * To reset, we hit the on-board reset register
         * in the system FPGA
         */
-        val = __raw_readl(hdr_ctrl);
+        __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
-        val |= REALVIEW_PB11MP_SYS_CTRL_RESET_CONFIGCLR;
+        __raw_writel(0x0000, reset_ctrl);
-        __raw_writel(val, hdr_ctrl);
+        __raw_writel(0x0004, reset_ctrl);
 }
 static void __init realview_pb11mp_init(void)
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index fe861e96c566..fe4e25c4201a 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -272,6 +272,20 @@ static struct sys_timer realview_pba8_timer = {
        .init           = realview_pba8_timer_init,
 };
+static void realview_pba8_reset(char mode)
+{
+        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
+        void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
+        /*
+         * To reset, we hit the on-board reset register
+         * in the system FPGA
+         */
+        __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
+        __raw_writel(0x0000, reset_ctrl);
+        __raw_writel(0x0004, reset_ctrl);
+}
 static void __init realview_pba8_init(void)
 {
        int i;
@@ -291,6 +305,7 @@ static void __init realview_pba8_init(void)
 #ifdef CONFIG_LEDS
        leds_event = realview_leds_event;
 #endif
+        realview_reset = realview_pba8_reset;
 }
 MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index ec39488e2b42..a21a4b395f73 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -324,6 +324,20 @@ static void realview_pbx_fixup(struct machine_desc *mdesc, struct tag *tags,
 #endif
 }
+static void realview_pbx_reset(char mode)
+{
+        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
+        void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
+        /*
+         * To reset, we hit the on-board reset register
+         * in the system FPGA
+         */
+        __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
+        __raw_writel(0x0000, reset_ctrl);
+        __raw_writel(0x0004, reset_ctrl);
+}
 static void __init realview_pbx_init(void)
 {
        int i;
@@ -358,6 +372,7 @@ static void __init realview_pbx_init(void)
 #ifdef CONFIG_LEDS
        leds_event = realview_leds_event;
 #endif
+        realview_reset = realview_pbx_reset;
 }
 MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index 547d4fc99131..2068e9096a43 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -288,7 +288,7 @@ static struct s3c2410_platform_nand mini2440_nand_info __initdata = {
 /* DM9000AEP 10/100 ethernet controller */
-static struct resource mini2440_dm9k_resource[] __initdata = {
+static struct resource mini2440_dm9k_resource[] = {
        [0] = {
                .start = MACH_MINI2440_DM9K_BASE,
                .end   = MACH_MINI2440_DM9K_BASE + 3,
@@ -310,11 +310,11 @@ static struct resource mini2440_dm9k_resource[] __initdata = {
 * The DM9000 has no eeprom, and it's MAC address is set by
 * the bootloader before starting the kernel.
 */
-static struct dm9000_plat_data mini2440_dm9k_pdata __initdata = {
+static struct dm9000_plat_data mini2440_dm9k_pdata = {
        .flags          = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
 };
-static struct platform_device mini2440_device_eth __initdata = {
+static struct platform_device mini2440_device_eth = {
        .name           = "dm9000",
        .id             = -1,
        .num_resources  = ARRAY_SIZE(mini2440_dm9k_resource),
@@ -341,7 +341,7 @@ static struct platform_device mini2440_device_eth __initdata = {
 *      |  |  +----+  +----+
 *        .....
 */
-static struct gpio_keys_button mini2440_buttons[] __initdata = {
+static struct gpio_keys_button mini2440_buttons[] = {
        {
                .gpio           = S3C2410_GPG(0),               /* K1 */
                .code           = KEY_F1,
@@ -384,12 +384,12 @@ static struct gpio_keys_button mini2440_buttons[] __initdata = {
 #endif
 };
-static struct gpio_keys_platform_data mini2440_button_data __initdata = {
+static struct gpio_keys_platform_data mini2440_button_data = {
        .buttons        = mini2440_buttons,
        .nbuttons       = ARRAY_SIZE(mini2440_buttons),
 };
-static struct platform_device mini2440_button_device __initdata = {
+static struct platform_device mini2440_button_device = {
        .name           = "gpio-keys",
        .id             = -1,
        .dev            = {
@@ -399,41 +399,41 @@ static struct platform_device mini2440_button_device __initdata = {
 /* LEDS */
-static struct s3c24xx_led_platdata mini2440_led1_pdata __initdata = {
+static struct s3c24xx_led_platdata mini2440_led1_pdata = {
        .name           = "led1",
        .gpio           = S3C2410_GPB(5),
        .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
        .def_trigger    = "heartbeat",
 };
-static struct s3c24xx_led_platdata mini2440_led2_pdata __initdata = {
+static struct s3c24xx_led_platdata mini2440_led2_pdata = {
        .name           = "led2",
        .gpio           = S3C2410_GPB(6),
        .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
        .def_trigger    = "nand-disk",
 };
-static struct s3c24xx_led_platdata mini2440_led3_pdata __initdata = {
+static struct s3c24xx_led_platdata mini2440_led3_pdata = {
        .name           = "led3",
        .gpio           = S3C2410_GPB(7),
        .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
        .def_trigger    = "mmc0",
 };
-static struct s3c24xx_led_platdata mini2440_led4_pdata __initdata = {
+static struct s3c24xx_led_platdata mini2440_led4_pdata = {
        .name           = "led4",
        .gpio           = S3C2410_GPB(8),
        .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
        .def_trigger    = "",
 };
-static struct s3c24xx_led_platdata mini2440_led_backlight_pdata __initdata = {
+static struct s3c24xx_led_platdata mini2440_led_backlight_pdata = {
        .name           = "backlight",
        .gpio           = S3C2410_GPG(4),
        .def_trigger    = "backlight",
 };
-static struct platform_device mini2440_led1 __initdata = {
+static struct platform_device mini2440_led1 = {
        .name           = "s3c24xx_led",
        .id             = 1,
        .dev            = {
@@ -441,7 +441,7 @@ static struct platform_device mini2440_led1 __initdata = {
        },
 };
-static struct platform_device mini2440_led2 __initdata = {
+static struct platform_device mini2440_led2 = {
        .name           = "s3c24xx_led",
        .id             = 2,
        .dev            = {
@@ -449,7 +449,7 @@ static struct platform_device mini2440_led2 __initdata = {
        },
 };
-static struct platform_device mini2440_led3 __initdata = {
+static struct platform_device mini2440_led3 = {
        .name           = "s3c24xx_led",
        .id             = 3,
        .dev            = {
@@ -457,7 +457,7 @@ static struct platform_device mini2440_led3 __initdata = {
        },
 };
-static struct platform_device mini2440_led4 __initdata = {
+static struct platform_device mini2440_led4 = {
        .name           = "s3c24xx_led",
        .id             = 4,
        .dev            = {
@@ -465,7 +465,7 @@ static struct platform_device mini2440_led4 __initdata = {
        },
 };
-static struct platform_device mini2440_led_backlight __initdata = {
+static struct platform_device mini2440_led_backlight = {
        .name           = "s3c24xx_led",
        .id             = 5,
        .dev            = {
@@ -475,14 +475,14 @@ static struct platform_device mini2440_led_backlight __initdata = {
 /* AUDIO */
-static struct s3c24xx_uda134x_platform_data mini2440_audio_pins __initdata = {
+static struct s3c24xx_uda134x_platform_data mini2440_audio_pins = {
        .l3_clk = S3C2410_GPB(4),
        .l3_mode = S3C2410_GPB(2),
        .l3_data = S3C2410_GPB(3),
        .model = UDA134X_UDA1341
 };
-static struct platform_device mini2440_audio __initdata = {
+static struct platform_device mini2440_audio = {
        .name           = "s3c24xx_uda134x",
        .id             = 0,
        .dev            = {
diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
index 480d297c1de2..8969fe73b83f 100644
--- a/arch/arm/mach-s3c6410/mach-smdk6410.c
+++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
@@ -211,6 +211,7 @@ static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
        .supply_name = "B_PWR_5V",
        .microvolts = 5000000,
        .init_data = &smdk6410_b_pwr_5v_data,
+        .gpio = -EINVAL,
 };
 static struct platform_device smdk6410_b_pwr_5v = {
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
index 111f7ea32b38..36ffd6a8b34c 100644
--- a/arch/arm/mach-u300/clock.c
+++ b/arch/arm/mach-u300/clock.c
@@ -610,34 +610,34 @@ EXPORT_SYMBOL(clk_get_rate);
 static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate)
 {
-        if (rate >= 18900000)
+        if (rate <= 18900000)
                return 18900000;
-        if (rate >= 20800000)
+        if (rate <= 20800000)
                return 20800000;
-        if (rate >= 23100000)
+        if (rate <= 23100000)
                return 23100000;
-        if (rate >= 26000000)
+        if (rate <= 26000000)
                return 26000000;
-        if (rate >= 29700000)
+        if (rate <= 29700000)
                return 29700000;
-        if (rate >= 34700000)
+        if (rate <= 34700000)
                return 34700000;
-        if (rate >= 41600000)
+        if (rate <= 41600000)
                return 41600000;
-        if (rate >= 52000000)
+        if (rate <= 52000000)
                return 52000000;
        return -EINVAL;
 }
 static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
 {
-        if (rate >= 13000000)
+        if (rate <= 13000000)
                return 13000000;
-        if (rate >= 52000000)
+        if (rate <= 52000000)
                return 52000000;
-        if (rate >= 104000000)
+        if (rate <= 104000000)
                return 104000000;
-        if (rate >= 208000000)
+        if (rate <= 208000000)
                return 208000000;
        return -EINVAL;
 }
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 653e25be3dd8..01b50313914c 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -3,7 +3,7 @@
 * arch/arm/mach-u300/core.c
 *
 *
- * Copyright (C) 2007-2009 ST-Ericsson AB
+ * Copyright (C) 2007-2010 ST-Ericsson AB
 * License terms: GNU General Public License (GPL) version 2
 * Core platform support, IRQ handling and device definitions.
 * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -19,6 +19,7 @@
 #include <linux/amba/bus.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <mach/coh901318.h>
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -29,6 +30,7 @@
 #include <mach/hardware.h>
 #include <mach/syscon.h>
+#include <mach/dma_channels.h>
 #include "clock.h"
 #include "mmc.h"
@@ -372,8 +374,1019 @@ static struct resource ave_resources[] = {
        },
 };
+static struct resource dma_resource[] = {
+        {
+                .start = U300_DMAC_BASE,
+                .end = U300_DMAC_BASE + PAGE_SIZE - 1,
+                .flags =  IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_U300_DMA,
+                .end = IRQ_U300_DMA,
+                .flags =  IORESOURCE_IRQ,
+        }
+};
+#ifdef CONFIG_MACH_U300_BS335
+/* points out all dma slave channels.
+ * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
+ * Select all channels from A to B, end of list is marked with -1,-1
+ */
+static int dma_slave_channels[] = {
+        U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
+        U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
+/* points out all dma memcpy channels. */
+static int dma_memcpy_channels[] = {
+        U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
+#else /* CONFIG_MACH_U300_BS335 */
+static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
+static int dma_memcpy_channels[] = {
+        U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
+#endif
+/** register dma for memory access
+ *
+ * active  1 means dma intends to access memory
+ *         0 means dma wont access memory
+ */
+static void coh901318_access_memory_state(struct device *dev, bool active)
+{
+}
+#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
+                        COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
+                        COH901318_CX_CFG_LCR_DISABLE | \
+                        COH901318_CX_CFG_TC_IRQ_ENABLE | \
+                        COH901318_CX_CFG_BE_IRQ_ENABLE)
+#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
+                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
+                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
+                        COH901318_CX_CTRL_TCP_DISABLE | \
+                        COH901318_CX_CTRL_TC_IRQ_DISABLE | \
+                        COH901318_CX_CTRL_HSP_DISABLE | \
+                        COH901318_CX_CTRL_HSS_DISABLE | \
+                        COH901318_CX_CTRL_DDMA_LEGACY | \
+                        COH901318_CX_CTRL_PRDD_SOURCE)
+#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
+                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
+                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
+                        COH901318_CX_CTRL_TCP_DISABLE | \
+                        COH901318_CX_CTRL_TC_IRQ_DISABLE | \
+                        COH901318_CX_CTRL_HSP_DISABLE | \
+                        COH901318_CX_CTRL_HSS_DISABLE | \
+                        COH901318_CX_CTRL_DDMA_LEGACY | \
+                        COH901318_CX_CTRL_PRDD_SOURCE)
+#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
+                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
+                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
+                        COH901318_CX_CTRL_TCP_DISABLE | \
+                        COH901318_CX_CTRL_TC_IRQ_ENABLE | \
+                        COH901318_CX_CTRL_HSP_DISABLE | \
+                        COH901318_CX_CTRL_HSS_DISABLE | \
+                        COH901318_CX_CTRL_DDMA_LEGACY | \
+                        COH901318_CX_CTRL_PRDD_SOURCE)
+const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
+        {
+                .number = U300_DMA_MSL_TX_0,
+                .name = "MSL TX 0",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
+        },
+        {
+                .number = U300_DMA_MSL_TX_1,
+                .name = "MSL TX 1",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+        },
+        {
+                .number = U300_DMA_MSL_TX_2,
+                .name = "MSL TX 2",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .desc_nbr_max = 10,
+        },
+        {
+                .number = U300_DMA_MSL_TX_3,
+                .name = "MSL TX 3",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+        },
+        {
+                .number = U300_DMA_MSL_TX_4,
+                .name = "MSL TX 4",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+        },
+        {
+                .number = U300_DMA_MSL_TX_5,
+                .name = "MSL TX 5",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
+        },
+        {
+                .number = U300_DMA_MSL_TX_6,
+                .name = "MSL TX 6",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
+        },
+        {
+                .number = U300_DMA_MSL_RX_0,
+                .name = "MSL RX 0",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
+        },
+        {
+                .number = U300_DMA_MSL_RX_1,
+                .name = "MSL RX 1",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_MSL_RX_2,
+                .name = "MSL RX 2",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_MSL_RX_3,
+                .name = "MSL RX 3",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_MSL_RX_4,
+                .name = "MSL RX 4",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_MSL_RX_5,
+                .name = "MSL RX 5",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_MSL_RX_6,
+                .name = "MSL RX 6",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
+        },
+        {
+                .number = U300_DMA_MMCSD_RX_TX,
+                .name = "MMCSD RX TX",
+                .priority_high = 0,
+                .dev_addr =  U300_MMCSD_BASE + 0x080,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+        },
+        {
+                .number = U300_DMA_MSPRO_TX,
+                .name = "MSPRO TX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_MSPRO_RX,
+                .name = "MSPRO RX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_UART0_TX,
+                .name = "UART0 TX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_UART0_RX,
+                .name = "UART0 RX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_APEX_TX,
+                .name = "APEX TX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_APEX_RX,
+                .name = "APEX RX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_PCM_I2S0_TX,
+                .name = "PCM I2S0 TX",
+                .priority_high = 1,
+                .dev_addr = U300_PCM_I2S0_BASE + 0x14,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+        },
+        {
+                .number = U300_DMA_PCM_I2S0_RX,
+                .name = "PCM I2S0 RX",
+                .priority_high = 1,
+                .dev_addr = U300_PCM_I2S0_BASE + 0x10,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_PCM_I2S1_TX,
+                .name = "PCM I2S1 TX",
+                .priority_high = 1,
+                .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+        },
+        {
+                .number = U300_DMA_PCM_I2S1_RX,
+                .name = "PCM I2S1 RX",
+                .priority_high = 1,
+                .dev_addr = U300_PCM_I2S1_BASE + 0x10,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_XGAM_CDI,
+                .name = "XGAM CDI",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_XGAM_PDI,
+                .name = "XGAM PDI",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_SPI_TX,
+                .name = "SPI TX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_SPI_RX,
+                .name = "SPI RX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_0,
+                .name = "GENERAL 00",
+                .priority_high = 0,
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_1,
+                .name = "GENERAL 01",
+                .priority_high = 0,
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_2,
+                .name = "GENERAL 02",
+                .priority_high = 0,
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_3,
+                .name = "GENERAL 03",
+                .priority_high = 0,
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_4,
+                .name = "GENERAL 04",
+                .priority_high = 0,
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_5,
+                .name = "GENERAL 05",
+                .priority_high = 0,
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_6,
+                .name = "GENERAL 06",
+                .priority_high = 0,
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_7,
+                .name = "GENERAL 07",
+                .priority_high = 0,
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_8,
+                .name = "GENERAL 08",
+                .priority_high = 0,
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+#ifdef CONFIG_MACH_U300_BS335
+        {
+                .number = U300_DMA_UART1_TX,
+                .name = "UART1 TX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_UART1_RX,
+                .name = "UART1 RX",
+                .priority_high = 0,
+        }
+#else
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_9,
+                .name = "GENERAL 09",
+                .priority_high = 0,
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_10,
+                .name = "GENERAL 10",
+                .priority_high = 0,
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        }
+#endif
+};
+static struct coh901318_platform coh901318_platform = {
+        .chans_slave = dma_slave_channels,
+        .chans_memcpy = dma_memcpy_channels,
+        .access_memory_state = coh901318_access_memory_state,
+        .chan_conf = chan_config,
+        .max_channels = U300_DMA_CHANNELS,
+};
 static struct platform_device wdog_device = {
-        .name = "wdog",
+        .name = "coh901327_wdog",
        .id = -1,
        .num_resources = ARRAY_SIZE(wdog_resources),
        .resource = wdog_resources,
@@ -428,11 +1441,23 @@ static struct platform_device ave_device = {
        .resource = ave_resources,
 };
+static struct platform_device dma_device = {
+        .name           = "coh901318",
+        .id             = -1,
+        .resource       = dma_resource,
+        .num_resources  = ARRAY_SIZE(dma_resource),
+        .dev = {
+                .platform_data = &coh901318_platform,
+                .coherent_dma_mask = ~0,
+        },
+};
 /*
 * Notice that AMBA devices are initialized before platform devices.
 *
 */
 static struct platform_device *platform_devs[] __initdata = {
+        &dma_device,
        &i2c0_device,
        &i2c1_device,
        &keypad_device,
diff --git a/arch/arm/mach-u300/gpio.c b/arch/arm/mach-u300/gpio.c
index 0b35826b7d1d..5f61fd45a0c8 100644
--- a/arch/arm/mach-u300/gpio.c
+++ b/arch/arm/mach-u300/gpio.c
@@ -546,7 +546,7 @@ static void gpio_set_initial_values(void)
        for (i = 0; i < U300_GPIO_MAX; i++) {
                val = 0;
                for (j = 0; j < 8; j++)
-                        val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP)) << j;
+                        val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP) << j);
                local_irq_save(flags);
                writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING);
                local_irq_restore(flags);
diff --git a/arch/arm/mach-u300/include/mach/dma_channels.h b/arch/arm/mach-u300/include/mach/dma_channels.h
new file mode 100644
index 000000000000..b239149ba0d0
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/dma_channels.h
@@ -0,0 +1,69 @@
+/*
+ *
+ * arch/arm/mach-u300/include/mach/dma_channels.h
+ *
+ *
+ * Copyright (C) 2007-2009 ST-Ericsson
+ * License terms: GNU General Public License (GPL) version 2
+ * Map file for the U300 dma driver.
+ * Author: Per Friden <per.friden@stericsson.com>
+ */
+#ifndef DMA_CHANNELS_H
+#define DMA_CHANNELS_H
+#define U300_DMA_MSL_TX_0             0
+#define U300_DMA_MSL_TX_1             1
+#define U300_DMA_MSL_TX_2             2
+#define U300_DMA_MSL_TX_3             3
+#define U300_DMA_MSL_TX_4             4
+#define U300_DMA_MSL_TX_5             5
+#define U300_DMA_MSL_TX_6             6
+#define U300_DMA_MSL_RX_0             7
+#define U300_DMA_MSL_RX_1             8
+#define U300_DMA_MSL_RX_2             9
+#define U300_DMA_MSL_RX_3             10
+#define U300_DMA_MSL_RX_4             11
+#define U300_DMA_MSL_RX_5             12
+#define U300_DMA_MSL_RX_6             13
+#define U300_DMA_MMCSD_RX_TX          14
+#define U300_DMA_MSPRO_TX             15
+#define U300_DMA_MSPRO_RX             16
+#define U300_DMA_UART0_TX             17
+#define U300_DMA_UART0_RX             18
+#define U300_DMA_APEX_TX              19
+#define U300_DMA_APEX_RX              20
+#define U300_DMA_PCM_I2S0_TX          21
+#define U300_DMA_PCM_I2S0_RX          22
+#define U300_DMA_PCM_I2S1_TX          23
+#define U300_DMA_PCM_I2S1_RX          24
+#define U300_DMA_XGAM_CDI             25
+#define U300_DMA_XGAM_PDI             26
+#define U300_DMA_SPI_TX               27
+#define U300_DMA_SPI_RX               28
+#define U300_DMA_GENERAL_PURPOSE_0    29
+#define U300_DMA_GENERAL_PURPOSE_1    30
+#define U300_DMA_GENERAL_PURPOSE_2    31
+#define U300_DMA_GENERAL_PURPOSE_3    32
+#define U300_DMA_GENERAL_PURPOSE_4    33
+#define U300_DMA_GENERAL_PURPOSE_5    34
+#define U300_DMA_GENERAL_PURPOSE_6    35
+#define U300_DMA_GENERAL_PURPOSE_7    36
+#define U300_DMA_GENERAL_PURPOSE_8    37
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_DMA_UART1_TX             38
+#define U300_DMA_UART1_RX             39
+#else
+#define U300_DMA_GENERAL_PURPOSE_9    38
+#define U300_DMA_GENERAL_PURPOSE_10   39
+#endif
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_DMA_DEVICE_CHANNELS      32
+#else
+#define U300_DMA_DEVICE_CHANNELS      30
+#endif
+#define U300_DMA_CHANNELS             40
+#endif /* DMA_CHANNELS_H */
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index aa5afbcc90f9..803aec1d6728 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -22,6 +22,7 @@
 #include <asm/mach/arch.h>
 #include <plat/mtu.h>
+#include <plat/i2c.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
@@ -108,11 +109,96 @@ static struct amba_device pl022_device = {
        .periphid = SSP_PER_ID,
 };
+static struct amba_device pl031_device = {
+        .dev = {
+                .init_name = "pl031",
+        },
+        .res = {
+                .start = U8500_RTC_BASE,
+                .end = U8500_RTC_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = {IRQ_RTC_RTT, NO_IRQ},
+};
+#define U8500_I2C_RESOURCES(id, size)           \
+static struct resource u8500_i2c_resources_##id[] = {   \
+        [0] = {                                 \
+                .start  = U8500_I2C##id##_BASE, \
+                .end    = U8500_I2C##id##_BASE + size - 1, \
+                .flags  = IORESOURCE_MEM,       \
+        },                                      \
+        [1] = {                                 \
+                .start  = IRQ_I2C##id,          \
+                .end    = IRQ_I2C##id,          \
+                .flags  = IORESOURCE_IRQ        \
+        }                                       \
+}
+U8500_I2C_RESOURCES(0, SZ_4K);
+U8500_I2C_RESOURCES(1, SZ_4K);
+U8500_I2C_RESOURCES(2, SZ_4K);
+U8500_I2C_RESOURCES(3, SZ_4K);
+#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
+static struct nmk_i2c_controller u8500_i2c_##id = { \
+        /*                              \
+         * slave data setup time, which is      \
+         * 250 ns,100ns,10ns which is 14,6,2    \
+         * respectively for a 48 Mhz    \
+         * i2c clock                    \
+         */                             \
+        .slsu           = _slsu,        \
+        /* Tx FIFO threshold */         \
+        .tft            = _tft,         \
+        /* Rx FIFO threshold */         \
+        .rft            = _rft,         \
+        /* std. mode operation */       \
+        .clk_freq       = clk,          \
+        .sm             = _sm,          \
+}
+/*
+ * The board uses 4 i2c controllers, initialize all of
+ * them with slave data setup time of 250 ns,
+ * Tx & Rx FIFO threshold values as 1 and standard
+ * mode of operation
+ */
+U8500_I2C_CONTROLLER(0, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
+U8500_I2C_CONTROLLER(1, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
+U8500_I2C_CONTROLLER(2, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
+U8500_I2C_CONTROLLER(3, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
+#define U8500_I2C_PDEVICE(cid)          \
+static struct platform_device i2c_controller##cid = { \
+        .name = "nmk-i2c",              \
+        .id      = cid,                 \
+        .num_resources = 2,             \
+        .resource = u8500_i2c_resources_##cid,  \
+        .dev = {                        \
+                .platform_data = &u8500_i2c_##cid \
+        }                               \
+}
+U8500_I2C_PDEVICE(0);
+U8500_I2C_PDEVICE(1);
+U8500_I2C_PDEVICE(2);
+U8500_I2C_PDEVICE(3);
 static struct amba_device *amba_devs[] __initdata = {
        &uart0_device,
        &uart1_device,
        &uart2_device,
        &pl022_device,
+        &pl031_device,
+};
+/* add any platform devices here - TODO */
+static struct platform_device *platform_devs[] __initdata = {
+        &i2c_controller0,
+        &i2c_controller1,
+        &i2c_controller2,
+        &i2c_controller3,
 };
 static void __init u8500_timer_init(void)
@@ -139,6 +225,8 @@ static void __init u8500_init_machine(void)
        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
                amba_device_register(amba_devs[i], &iomem_resource);
+        platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
        spi_register_board_info(u8500_spi_devices,
                        ARRAY_SIZE(u8500_spi_devices));
diff --git a/arch/arm/mach-ux500/cpu-u8500.c b/arch/arm/mach-ux500/cpu-u8500.c
index 5f05e5850f71..397bc1f9ed94 100644
--- a/arch/arm/mach-ux500/cpu-u8500.c
+++ b/arch/arm/mach-ux500/cpu-u8500.c
@@ -33,6 +33,7 @@ static struct platform_device *platform_devs[] __initdata = {
 /* minimum static i/o mapping required to boot U8500 platforms */
 static struct map_desc u8500_io_desc[] __initdata = {
+        __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
        __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K),
        __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
        __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
index 8f21b6a95dce..8de225e02235 100644
--- a/arch/arm/mach-ux500/include/mach/debug-macro.S
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -8,12 +8,13 @@
 * published by the Free Software Foundation.
 *
 */
+#include <mach/hardware.h>
        .macro  addruart,rx
        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                 @MMU enabled?
+        tst     \rx, #1                                 @ MMU enabled?
-        moveq   \rx, #0x80000000        @MMU off, Physical address
+        ldreq   \rx, =U8500_UART2_BASE                  @ no, physical address
-        movne   \rx, #0xF0000000        @MMU on, Virtual address
+        ldrne   \rx, =IO_ADDRESS(U8500_UART2_BASE)      @ yes, virtual address
-        orr     \rx, \rx, #0x7000
        .endm
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-w90x900/include/mach/system.h b/arch/arm/mach-w90x900/include/mach/system.h
index 940640066857..ce228bdc66dd 100644
--- a/arch/arm/mach-w90x900/include/mach/system.h
+++ b/arch/arm/mach-w90x900/include/mach/system.h
@@ -15,7 +15,15 @@
 *
 */
+#include <linux/io.h>
 #include <asm/proc-fns.h>
+#include <mach/map.h>
+#include <mach/regs-timer.h>
+#define WTCR    (TMR_BA + 0x1C)
+#define WTCLK   (1 << 10)
+#define WTE     (1 << 7)
+#define WTRE    (1 << 1)
 static void arch_idle(void)
 {
@@ -23,6 +31,11 @@ static void arch_idle(void)
 static void arch_reset(char mode, const char *cmd)
 {
-        cpu_reset(0);
+        if (mode == 's') {
+                /* Jump into ROM at address 0 */
+                cpu_reset(0);
+        } else {
+                __raw_writel(WTE | WTRE | WTCLK, WTCR);
+        }
 }
diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c
index 4128af870b41..b80f769bc135 100644
--- a/arch/arm/mach-w90x900/time.c
+++ b/arch/arm/mach-w90x900/time.c
@@ -42,7 +42,10 @@
 #define TICKS_PER_SEC   100
 #define PRESCALE        0x63 /* Divider = prescale + 1 */
-unsigned int timer0_load;
+#define TDR_SHIFT       24
+#define TDR_MASK        ((1 << TDR_SHIFT) - 1)
+static unsigned int timer0_load;
 static void nuc900_clockevent_setmode(enum clock_event_mode mode,
                struct clock_event_device *clk)
@@ -88,7 +91,7 @@ static int nuc900_clockevent_setnextevent(unsigned long evt,
 static struct clock_event_device nuc900_clockevent_device = {
        .name           = "nuc900-timer0",
        .shift          = 32,
-        .features       = CLOCK_EVT_MODE_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
        .set_mode       = nuc900_clockevent_setmode,
        .set_next_event = nuc900_clockevent_setnextevent,
        .rating         = 300,
@@ -112,8 +115,23 @@ static struct irqaction nuc900_timer0_irq = {
        .handler        = nuc900_timer0_interrupt,
 };
-static void __init nuc900_clockevents_init(unsigned int rate)
+static void __init nuc900_clockevents_init(void)
 {
+        unsigned int rate;
+        struct clk *clk = clk_get(NULL, "timer0");
+        BUG_ON(IS_ERR(clk));
+        __raw_writel(0x00, REG_TCSR0);
+        clk_enable(clk);
+        rate = clk_get_rate(clk) / (PRESCALE + 1);
+        timer0_load = (rate / TICKS_PER_SEC);
+        __raw_writel(RESETINT, REG_TISR);
+        setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
        nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC,
                                        nuc900_clockevent_device.shift);
        nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff,
@@ -127,26 +145,35 @@ static void __init nuc900_clockevents_init(unsigned int rate)
 static cycle_t nuc900_get_cycles(struct clocksource *cs)
 {
-        return ~__raw_readl(REG_TDR1);
+        return (~__raw_readl(REG_TDR1)) & TDR_MASK;
 }
 static struct clocksource clocksource_nuc900 = {
        .name   = "nuc900-timer1",
        .rating = 200,
        .read   = nuc900_get_cycles,
-        .mask   = CLOCKSOURCE_MASK(32),
+        .mask   = CLOCKSOURCE_MASK(TDR_SHIFT),
-        .shift  = 20,
+        .shift  = 10,
        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
-static void __init nuc900_clocksource_init(unsigned int rate)
+static void __init nuc900_clocksource_init(void)
 {
        unsigned int val;
+        unsigned int rate;
+        struct clk *clk = clk_get(NULL, "timer1");
+        BUG_ON(IS_ERR(clk));
+        __raw_writel(0x00, REG_TCSR1);
+        clk_enable(clk);
+        rate = clk_get_rate(clk) / (PRESCALE + 1);
        __raw_writel(0xffffffff, REG_TICR1);
        val = __raw_readl(REG_TCSR1);
-        val |= (COUNTEN | PERIOD);
+        val |= (COUNTEN | PERIOD | PRESCALE);
        __raw_writel(val, REG_TCSR1);
        clocksource_nuc900.mult =
@@ -156,25 +183,8 @@ static void __init nuc900_clocksource_init(unsigned int rate)
 static void __init nuc900_timer_init(void)
 {
-        struct clk *ck_ext = clk_get(NULL, "ext");
+        nuc900_clocksource_init();
-        unsigned int    rate;
+        nuc900_clockevents_init();
-        BUG_ON(IS_ERR(ck_ext));
-        rate = clk_get_rate(ck_ext);
-        clk_put(ck_ext);
-        rate = rate / (PRESCALE + 0x01);
-         /* set a known state */
-        __raw_writel(0x00, REG_TCSR0);
-        __raw_writel(0x00, REG_TCSR1);
-        __raw_writel(RESETINT, REG_TISR);
-        timer0_load = (rate / TICKS_PER_SEC);
-        setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
-        nuc900_clocksource_init(rate);
-        nuc900_clockevents_init(rate);
 }
 struct sys_timer nuc900_timer = {
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 827e238e5d4a..e8d34a80851c 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -27,6 +27,9 @@ obj-$(CONFIG_CPU_ABRT_EV5TJ)	+= abort-ev5tj.o
 obj-$(CONFIG_CPU_ABRT_EV6)      += abort-ev6.o
 obj-$(CONFIG_CPU_ABRT_EV7)      += abort-ev7.o
+AFLAGS_abort-ev6.o      :=-Wa,-march=armv6k
+AFLAGS_abort-ev7.o      :=-Wa,-march=armv7-a
 obj-$(CONFIG_CPU_PABRT_LEGACY)  += pabort-legacy.o
 obj-$(CONFIG_CPU_PABRT_V6)      += pabort-v6.o
 obj-$(CONFIG_CPU_PABRT_V7)      += pabort-v7.o
@@ -39,6 +42,9 @@ obj-$(CONFIG_CPU_CACHE_V6)	+= cache-v6.o
 obj-$(CONFIG_CPU_CACHE_V7)      += cache-v7.o
 obj-$(CONFIG_CPU_CACHE_FA)      += cache-fa.o
+AFLAGS_cache-v6.o       :=-Wa,-march=armv6
+AFLAGS_cache-v7.o       :=-Wa,-march=armv7-a
 obj-$(CONFIG_CPU_COPY_V3)       += copypage-v3.o
 obj-$(CONFIG_CPU_COPY_V4WT)     += copypage-v4wt.o
 obj-$(CONFIG_CPU_COPY_V4WB)     += copypage-v4wb.o
@@ -58,6 +64,9 @@ obj-$(CONFIG_CPU_TLB_V6)	+= tlb-v6.o
 obj-$(CONFIG_CPU_TLB_V7)        += tlb-v7.o
 obj-$(CONFIG_CPU_TLB_FA)        += tlb-fa.o
+AFLAGS_tlb-v6.o         :=-Wa,-march=armv6
+AFLAGS_tlb-v7.o         :=-Wa,-march=armv7-a
 obj-$(CONFIG_CPU_ARM610)        += proc-arm6_7.o
 obj-$(CONFIG_CPU_ARM710)        += proc-arm6_7.o
 obj-$(CONFIG_CPU_ARM7TDMI)      += proc-arm7tdmi.o
@@ -84,6 +93,9 @@ obj-$(CONFIG_CPU_FEROCEON)	+= proc-feroceon.o
 obj-$(CONFIG_CPU_V6)            += proc-v6.o
 obj-$(CONFIG_CPU_V7)            += proc-v7.o
+AFLAGS_proc-v6.o        :=-Wa,-march=armv6
+AFLAGS_proc-v7.o        :=-Wa,-march=armv7-a
 obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
 obj-$(CONFIG_CACHE_XSC3L2)      += cache-xsc3l2.o
diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S
index a89444a3c016..7148e53e6078 100644
--- a/arch/arm/mm/cache-fa.S
+++ b/arch/arm/mm/cache-fa.S
@@ -157,7 +157,7 @@ ENTRY(fa_flush_kern_dcache_area)
 *      - start  - virtual start address
 *      - end    - virtual end address
 */
-ENTRY(fa_dma_inv_range)
+fa_dma_inv_range:
        tst     r0, #CACHE_DLINESIZE - 1
        bic     r0, r0, #CACHE_DLINESIZE - 1
        mcrne   p15, 0, r0, c7, c14, 1          @ clean & invalidate D entry
@@ -180,7 +180,7 @@ ENTRY(fa_dma_inv_range)
 *      - start  - virtual start address
 *      - end    - virtual end address
 */
-ENTRY(fa_dma_clean_range)
+fa_dma_clean_range:
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        add     r0, r0, #CACHE_DLINESIZE
@@ -205,6 +205,30 @@ ENTRY(fa_dma_flush_range)
        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
        mov     pc, lr
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(fa_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     fa_dma_clean_range
+        bcs     fa_dma_inv_range
+        b       fa_dma_flush_range
+ENDPROC(fa_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(fa_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(fa_dma_unmap_area)
        __INITDATA
        .type   fa_cache_fns, #object
@@ -215,7 +239,7 @@ ENTRY(fa_cache_fns)
        .long   fa_coherent_kern_range
        .long   fa_coherent_user_range
        .long   fa_flush_kern_dcache_area
-        .long   fa_dma_inv_range
+        .long   fa_dma_map_area
-        .long   fa_dma_clean_range
+        .long   fa_dma_unmap_area
        .long   fa_dma_flush_range
        .size   fa_cache_fns, . - fa_cache_fns
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index 2a482731ea36..c2ff3c599fee 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -84,20 +84,6 @@ ENTRY(v3_flush_kern_dcache_area)
        /* FALLTHROUGH */
 /*
- *      dma_inv_range(start, end)
- *
- *      Invalidate (discard) the specified virtual address range.
- *      May not write back any entries.  If 'start' or 'end'
- *      are not cache line aligned, those lines must be written
- *      back.
- *
- *      - start  - virtual start address
- *      - end    - virtual end address
- */
-ENTRY(v3_dma_inv_range)
-        /* FALLTHROUGH */
-/*
 *      dma_flush_range(start, end)
 *
 *      Clean and invalidate the specified virtual address range.
@@ -108,18 +94,29 @@ ENTRY(v3_dma_inv_range)
 ENTRY(v3_dma_flush_range)
        mov     r0, #0
        mcr     p15, 0, r0, c7, c0, 0           @ flush ID cache
+        mov     pc, lr
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v3_dma_unmap_area)
+        teq     r2, #DMA_TO_DEVICE
+        bne     v3_dma_flush_range
        /* FALLTHROUGH */
 /*
- *      dma_clean_range(start, end)
+ *      dma_map_area(start, size, dir)
- *
+ *      - start - kernel virtual start address
- *      Clean (write back) the specified virtual address range.
+ *      - size  - size of region
- *
+ *      - dir   - DMA direction
- *      - start  - virtual start address
- *      - end    - virtual end address
 */
-ENTRY(v3_dma_clean_range)
+ENTRY(v3_dma_map_area)
        mov     pc, lr
+ENDPROC(v3_dma_unmap_area)
+ENDPROC(v3_dma_map_area)
        __INITDATA
@@ -131,7 +128,7 @@ ENTRY(v3_cache_fns)
        .long   v3_coherent_kern_range
        .long   v3_coherent_user_range
        .long   v3_flush_kern_dcache_area
-        .long   v3_dma_inv_range
+        .long   v3_dma_map_area
-        .long   v3_dma_clean_range
+        .long   v3_dma_unmap_area
        .long   v3_dma_flush_range
        .size   v3_cache_fns, . - v3_cache_fns
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index 5c7da3e372e9..4810f7e3e813 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -94,20 +94,6 @@ ENTRY(v4_flush_kern_dcache_area)
        /* FALLTHROUGH */
 /*
- *      dma_inv_range(start, end)
- *
- *      Invalidate (discard) the specified virtual address range.
- *      May not write back any entries.  If 'start' or 'end'
- *      are not cache line aligned, those lines must be written
- *      back.
- *
- *      - start  - virtual start address
- *      - end    - virtual end address
- */
-ENTRY(v4_dma_inv_range)
-        /* FALLTHROUGH */
-/*
 *      dma_flush_range(start, end)
 *
 *      Clean and invalidate the specified virtual address range.
@@ -120,18 +106,29 @@ ENTRY(v4_dma_flush_range)
        mov     r0, #0
        mcr     p15, 0, r0, c7, c7, 0           @ flush ID cache
 #endif
+        mov     pc, lr
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v4_dma_unmap_area)
+        teq     r2, #DMA_TO_DEVICE
+        bne     v4_dma_flush_range
        /* FALLTHROUGH */
 /*
- *      dma_clean_range(start, end)
+ *      dma_map_area(start, size, dir)
- *
+ *      - start - kernel virtual start address
- *      Clean (write back) the specified virtual address range.
+ *      - size  - size of region
- *
+ *      - dir   - DMA direction
- *      - start  - virtual start address
- *      - end    - virtual end address
 */
-ENTRY(v4_dma_clean_range)
+ENTRY(v4_dma_map_area)
        mov     pc, lr
+ENDPROC(v4_dma_unmap_area)
+ENDPROC(v4_dma_map_area)
        __INITDATA
@@ -143,7 +140,7 @@ ENTRY(v4_cache_fns)
        .long   v4_coherent_kern_range
        .long   v4_coherent_user_range
        .long   v4_flush_kern_dcache_area
-        .long   v4_dma_inv_range
+        .long   v4_dma_map_area
-        .long   v4_dma_clean_range
+        .long   v4_dma_unmap_area
        .long   v4_dma_flush_range
        .size   v4_cache_fns, . - v4_cache_fns
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index 3dbedf1ec0e7..df8368afa102 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -173,7 +173,7 @@ ENTRY(v4wb_coherent_user_range)
 *      - start  - virtual start address
 *      - end    - virtual end address
 */
-ENTRY(v4wb_dma_inv_range)
+v4wb_dma_inv_range:
        tst     r0, #CACHE_DLINESIZE - 1
        bic     r0, r0, #CACHE_DLINESIZE - 1
        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -194,7 +194,7 @@ ENTRY(v4wb_dma_inv_range)
 *      - start  - virtual start address
 *      - end    - virtual end address
 */
-ENTRY(v4wb_dma_clean_range)
+v4wb_dma_clean_range:
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        add     r0, r0, #CACHE_DLINESIZE
@@ -216,6 +216,30 @@ ENTRY(v4wb_dma_clean_range)
        .globl  v4wb_dma_flush_range
        .set    v4wb_dma_flush_range, v4wb_coherent_kern_range
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v4wb_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     v4wb_dma_clean_range
+        bcs     v4wb_dma_inv_range
+        b       v4wb_dma_flush_range
+ENDPROC(v4wb_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v4wb_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(v4wb_dma_unmap_area)
        __INITDATA
        .type   v4wb_cache_fns, #object
@@ -226,7 +250,7 @@ ENTRY(v4wb_cache_fns)
        .long   v4wb_coherent_kern_range
        .long   v4wb_coherent_user_range
        .long   v4wb_flush_kern_dcache_area
-        .long   v4wb_dma_inv_range
+        .long   v4wb_dma_map_area
-        .long   v4wb_dma_clean_range
+        .long   v4wb_dma_unmap_area
        .long   v4wb_dma_flush_range
        .size   v4wb_cache_fns, . - v4wb_cache_fns
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index b3b7410270b4..45c70312f43b 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -142,23 +142,12 @@ ENTRY(v4wt_flush_kern_dcache_area)
 *      - start  - virtual start address
 *      - end    - virtual end address
 */
-ENTRY(v4wt_dma_inv_range)
+v4wt_dma_inv_range:
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
        add     r0, r0, #CACHE_DLINESIZE
        cmp     r0, r1
        blo     1b
-        /* FALLTHROUGH */
-/*
- *      dma_clean_range(start, end)
- *
- *      Clean the specified virtual address range.
- *
- *      - start  - virtual start address
- *      - end    - virtual end address
- */
-ENTRY(v4wt_dma_clean_range)
        mov     pc, lr
 /*
@@ -172,6 +161,29 @@ ENTRY(v4wt_dma_clean_range)
        .globl  v4wt_dma_flush_range
        .equ    v4wt_dma_flush_range, v4wt_dma_inv_range
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v4wt_dma_unmap_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_TO_DEVICE
+        bne     v4wt_dma_inv_range
+        /* FALLTHROUGH */
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v4wt_dma_map_area)
+        mov     pc, lr
+ENDPROC(v4wt_dma_unmap_area)
+ENDPROC(v4wt_dma_map_area)
        __INITDATA
        .type   v4wt_cache_fns, #object
@@ -182,7 +194,7 @@ ENTRY(v4wt_cache_fns)
        .long   v4wt_coherent_kern_range
        .long   v4wt_coherent_user_range
        .long   v4wt_flush_kern_dcache_area
-        .long   v4wt_dma_inv_range
+        .long   v4wt_dma_map_area
-        .long   v4wt_dma_clean_range
+        .long   v4wt_dma_unmap_area
        .long   v4wt_dma_flush_range
        .size   v4wt_cache_fns, . - v4wt_cache_fns
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 4ba0a24ce6f5..9d89c67a1cc3 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -195,7 +195,7 @@ ENTRY(v6_flush_kern_dcache_area)
 *      - start   - virtual start address of region
 *      - end     - virtual end address of region
 */
-ENTRY(v6_dma_inv_range)
+v6_dma_inv_range:
        tst     r0, #D_CACHE_LINE_SIZE - 1
        bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 #ifdef HARVARD_CACHE
@@ -228,7 +228,7 @@ ENTRY(v6_dma_inv_range)
 *      - start   - virtual start address of region
 *      - end     - virtual end address of region
 */
-ENTRY(v6_dma_clean_range)
+v6_dma_clean_range:
        bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
 #ifdef HARVARD_CACHE
@@ -263,6 +263,32 @@ ENTRY(v6_dma_flush_range)
        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
        mov     pc, lr
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v6_dma_map_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_FROM_DEVICE
+        beq     v6_dma_inv_range
+        b       v6_dma_clean_range
+ENDPROC(v6_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v6_dma_unmap_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_TO_DEVICE
+        bne     v6_dma_inv_range
+        mov     pc, lr
+ENDPROC(v6_dma_unmap_area)
        __INITDATA
        .type   v6_cache_fns, #object
@@ -273,7 +299,7 @@ ENTRY(v6_cache_fns)
        .long   v6_coherent_kern_range
        .long   v6_coherent_user_range
        .long   v6_flush_kern_dcache_area
-        .long   v6_dma_inv_range
+        .long   v6_dma_map_area
-        .long   v6_dma_clean_range
+        .long   v6_dma_unmap_area
        .long   v6_dma_flush_range
        .size   v6_cache_fns, . - v6_cache_fns
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 9073db849fb4..bcd64f265870 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -216,7 +216,7 @@ ENDPROC(v7_flush_kern_dcache_area)
 *      - start   - virtual start address of region
 *      - end     - virtual end address of region
 */
-ENTRY(v7_dma_inv_range)
+v7_dma_inv_range:
        dcache_line_size r2, r3
        sub     r3, r2, #1
        tst     r0, r3
@@ -240,7 +240,7 @@ ENDPROC(v7_dma_inv_range)
 *      - start   - virtual start address of region
 *      - end     - virtual end address of region
 */
-ENTRY(v7_dma_clean_range)
+v7_dma_clean_range:
        dcache_line_size r2, r3
        sub     r3, r2, #1
        bic     r0, r0, r3
@@ -271,6 +271,32 @@ ENTRY(v7_dma_flush_range)
        mov     pc, lr
 ENDPROC(v7_dma_flush_range)
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v7_dma_map_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_FROM_DEVICE
+        beq     v7_dma_inv_range
+        b       v7_dma_clean_range
+ENDPROC(v7_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v7_dma_unmap_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_TO_DEVICE
+        bne     v7_dma_inv_range
+        mov     pc, lr
+ENDPROC(v7_dma_unmap_area)
        __INITDATA
        .type   v7_cache_fns, #object
@@ -281,7 +307,7 @@ ENTRY(v7_cache_fns)
        .long   v7_coherent_kern_range
        .long   v7_coherent_user_range
        .long   v7_flush_kern_dcache_area
-        .long   v7_dma_inv_range
+        .long   v7_dma_map_area
-        .long   v7_dma_clean_range
+        .long   v7_dma_unmap_area
        .long   v7_dma_flush_range
        .size   v7_cache_fns, . - v7_cache_fns
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c
index 5d180cb0bd94..c3154928bccd 100644
--- a/arch/arm/mm/cache-xsc3l2.c
+++ b/arch/arm/mm/cache-xsc3l2.c
@@ -221,15 +221,14 @@ static int __init xsc3_l2_init(void)
        if (!cpu_is_xsc3() || !xsc3_l2_present())
                return 0;
-        if (!(get_cr() & CR_L2)) {
+        if (get_cr() & CR_L2) {
                pr_info("XScale3 L2 cache enabled.\n");
-                adjust_cr(CR_L2, CR_L2);
                xsc3_l2_inv_all();
-        }
-        outer_cache.inv_range = xsc3_l2_inv_range;
+                outer_cache.inv_range = xsc3_l2_inv_range;
-        outer_cache.clean_range = xsc3_l2_clean_range;
+                outer_cache.clean_range = xsc3_l2_clean_range;
-        outer_cache.flush_range = xsc3_l2_flush_range;
+                outer_cache.flush_range = xsc3_l2_flush_range;
+        }
        return 0;
 }
diff --git a/arch/arm/mm/copypage-feroceon.c b/arch/arm/mm/copypage-feroceon.c
index 70997d5bee2d..5eb4fd93893d 100644
--- a/arch/arm/mm/copypage-feroceon.c
+++ b/arch/arm/mm/copypage-feroceon.c
@@ -68,12 +68,13 @@ feroceon_copy_user_page(void *kto, const void *kfrom)
 }
 void feroceon_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
        void *kto, *kfrom;
        kto = kmap_atomic(to, KM_USER0);
        kfrom = kmap_atomic(from, KM_USER1);
+        flush_cache_page(vma, vaddr, page_to_pfn(from));
        feroceon_copy_user_page(kto, kfrom);
        kunmap_atomic(kfrom, KM_USER1);
        kunmap_atomic(kto, KM_USER0);
diff --git a/arch/arm/mm/copypage-v3.c b/arch/arm/mm/copypage-v3.c
index de9c06854ad7..f72303e1d804 100644
--- a/arch/arm/mm/copypage-v3.c
+++ b/arch/arm/mm/copypage-v3.c
@@ -38,7 +38,7 @@ v3_copy_user_page(void *kto, const void *kfrom)
 }
 void v3_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
        void *kto, *kfrom;
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index 7370a7142b04..598c51ad5071 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -69,7 +69,7 @@ mc_copy_user_page(void *from, void *to)
 }
 void v4_mc_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
        void *kto = kmap_atomic(to, KM_USER1);
diff --git a/arch/arm/mm/copypage-v4wb.c b/arch/arm/mm/copypage-v4wb.c
index 9ab098414227..7c2eb55cd4a9 100644
--- a/arch/arm/mm/copypage-v4wb.c
+++ b/arch/arm/mm/copypage-v4wb.c
@@ -48,12 +48,13 @@ v4wb_copy_user_page(void *kto, const void *kfrom)
 }
 void v4wb_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
        void *kto, *kfrom;
        kto = kmap_atomic(to, KM_USER0);
        kfrom = kmap_atomic(from, KM_USER1);
+        flush_cache_page(vma, vaddr, page_to_pfn(from));
        v4wb_copy_user_page(kto, kfrom);
        kunmap_atomic(kfrom, KM_USER1);
        kunmap_atomic(kto, KM_USER0);
diff --git a/arch/arm/mm/copypage-v4wt.c b/arch/arm/mm/copypage-v4wt.c
index 300efafd6643..172e6a55458e 100644
--- a/arch/arm/mm/copypage-v4wt.c
+++ b/arch/arm/mm/copypage-v4wt.c
@@ -44,7 +44,7 @@ v4wt_copy_user_page(void *kto, const void *kfrom)
 }
 void v4wt_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
        void *kto, *kfrom;
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 0fa1319273de..8bca4dea6dfa 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -34,7 +34,7 @@ static DEFINE_SPINLOCK(v6_lock);
 * attack the kernel's existing mapping of these pages.
 */
 static void v6_copy_user_highpage_nonaliasing(struct page *to,
-        struct page *from, unsigned long vaddr)
+        struct page *from, unsigned long vaddr, struct vm_area_struct *vma)
 {
        void *kto, *kfrom;
@@ -81,7 +81,7 @@ static void discard_old_kernel_data(void *kto)
 * Copy the page, taking account of the cache colour.
 */
 static void v6_copy_user_highpage_aliasing(struct page *to,
-        struct page *from, unsigned long vaddr)
+        struct page *from, unsigned long vaddr, struct vm_area_struct *vma)
 {
        unsigned int offset = CACHE_COLOUR(vaddr);
        unsigned long kfrom, kto;
diff --git a/arch/arm/mm/copypage-xsc3.c b/arch/arm/mm/copypage-xsc3.c
index bc4525f5ab23..747ad4140fc7 100644
--- a/arch/arm/mm/copypage-xsc3.c
+++ b/arch/arm/mm/copypage-xsc3.c
@@ -71,12 +71,13 @@ xsc3_mc_copy_user_page(void *kto, const void *kfrom)
 }
 void xsc3_mc_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
        void *kto, *kfrom;
        kto = kmap_atomic(to, KM_USER0);
        kfrom = kmap_atomic(from, KM_USER1);
+        flush_cache_page(vma, vaddr, page_to_pfn(from));
        xsc3_mc_copy_user_page(kto, kfrom);
        kunmap_atomic(kfrom, KM_USER1);
        kunmap_atomic(kto, KM_USER0);
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 76824d3e966a..9920c0ae2096 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -91,7 +91,7 @@ mc_copy_user_page(void *from, void *to)
 }
 void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
        void *kto = kmap_atomic(to, KM_USER1);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 26325cb5d368..64daef2173bd 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -404,78 +404,44 @@ EXPORT_SYMBOL(dma_free_coherent);
 * platforms with CONFIG_DMABOUNCE.
 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
 */
-void dma_cache_maint(const void *start, size_t size, int direction)
+void ___dma_single_cpu_to_dev(const void *kaddr, size_t size,
+        enum dma_data_direction dir)
 {
-        void (*inner_op)(const void *, const void *);
+        unsigned long paddr;
-        void (*outer_op)(unsigned long, unsigned long);
+        BUG_ON(!virt_addr_valid(kaddr) || !virt_addr_valid(kaddr + size - 1));
-        BUG_ON(!virt_addr_valid(start) || !virt_addr_valid(start + size - 1));
+        dmac_map_area(kaddr, size, dir);
-        switch (direction) {
-        case DMA_FROM_DEVICE:           /* invalidate only */
-                inner_op = dmac_inv_range;
-                outer_op = outer_inv_range;
-                break;
-        case DMA_TO_DEVICE:             /* writeback only */
-                inner_op = dmac_clean_range;
-                outer_op = outer_clean_range;
-                break;
-        case DMA_BIDIRECTIONAL:         /* writeback and invalidate */
-                inner_op = dmac_flush_range;
-                outer_op = outer_flush_range;
-                break;
-        default:
-                BUG();
-        }
-        inner_op(start, start + size);
+        paddr = __pa(kaddr);
-        outer_op(__pa(start), __pa(start) + size);
+        if (dir == DMA_FROM_DEVICE) {
+                outer_inv_range(paddr, paddr + size);
+        } else {
+                outer_clean_range(paddr, paddr + size);
+        }
+        /* FIXME: non-speculating: flush on bidirectional mappings? */
 }
-EXPORT_SYMBOL(dma_cache_maint);
+EXPORT_SYMBOL(___dma_single_cpu_to_dev);
-static void dma_cache_maint_contiguous(struct page *page, unsigned long offset,
+void ___dma_single_dev_to_cpu(const void *kaddr, size_t size,
-                                       size_t size, int direction)
+        enum dma_data_direction dir)
 {
-        void *vaddr;
+        BUG_ON(!virt_addr_valid(kaddr) || !virt_addr_valid(kaddr + size - 1));
-        unsigned long paddr;
-        void (*inner_op)(const void *, const void *);
-        void (*outer_op)(unsigned long, unsigned long);
-        switch (direction) {
-        case DMA_FROM_DEVICE:           /* invalidate only */
-                inner_op = dmac_inv_range;
-                outer_op = outer_inv_range;
-                break;
-        case DMA_TO_DEVICE:             /* writeback only */
-                inner_op = dmac_clean_range;
-                outer_op = outer_clean_range;
-                break;
-        case DMA_BIDIRECTIONAL:         /* writeback and invalidate */
-                inner_op = dmac_flush_range;
-                outer_op = outer_flush_range;
-                break;
-        default:
-                BUG();
-        }
-        if (!PageHighMem(page)) {
+        /* FIXME: non-speculating: not required */
-                vaddr = page_address(page) + offset;
+        /* don't bother invalidating if DMA to device */
-                inner_op(vaddr, vaddr + size);
+        if (dir != DMA_TO_DEVICE) {
-        } else {
+                unsigned long paddr = __pa(kaddr);
-                vaddr = kmap_high_get(page);
+                outer_inv_range(paddr, paddr + size);
-                if (vaddr) {
-                        vaddr += offset;
-                        inner_op(vaddr, vaddr + size);
-                        kunmap_high(page);
-                }
        }
-        paddr = page_to_phys(page) + offset;
+        dmac_unmap_area(kaddr, size, dir);
-        outer_op(paddr, paddr + size);
 }
+EXPORT_SYMBOL(___dma_single_dev_to_cpu);
-void dma_cache_maint_page(struct page *page, unsigned long offset,
+static void dma_cache_maint_page(struct page *page, unsigned long offset,
-                          size_t size, int dir)
+        size_t size, enum dma_data_direction dir,
+        void (*op)(const void *, size_t, int))
 {
        /*
         * A single sg entry may refer to multiple physically contiguous
@@ -486,20 +452,62 @@ void dma_cache_maint_page(struct page *page, unsigned long offset,
        size_t left = size;
        do {
                size_t len = left;
-                if (PageHighMem(page) && len + offset > PAGE_SIZE) {
+                void *vaddr;
-                        if (offset >= PAGE_SIZE) {
-                                page += offset / PAGE_SIZE;
+                if (PageHighMem(page)) {
-                                offset %= PAGE_SIZE;
+                        if (len + offset > PAGE_SIZE) {
+                                if (offset >= PAGE_SIZE) {
+                                        page += offset / PAGE_SIZE;
+                                        offset %= PAGE_SIZE;
+                                }
+                                len = PAGE_SIZE - offset;
                        }
-                        len = PAGE_SIZE - offset;
+                        vaddr = kmap_high_get(page);
+                        if (vaddr) {
+                                vaddr += offset;
+                                op(vaddr, len, dir);
+                                kunmap_high(page);
+                        }
+                } else {
+                        vaddr = page_address(page) + offset;
+                        op(vaddr, len, dir);
                }
-                dma_cache_maint_contiguous(page, offset, len, dir);
                offset = 0;
                page++;
                left -= len;
        } while (left);
 }
-EXPORT_SYMBOL(dma_cache_maint_page);
+void ___dma_page_cpu_to_dev(struct page *page, unsigned long off,
+        size_t size, enum dma_data_direction dir)
+{
+        unsigned long paddr;
+        dma_cache_maint_page(page, off, size, dir, dmac_map_area);
+        paddr = page_to_phys(page) + off;
+        if (dir == DMA_FROM_DEVICE) {
+                outer_inv_range(paddr, paddr + size);
+        } else {
+                outer_clean_range(paddr, paddr + size);
+        }
+        /* FIXME: non-speculating: flush on bidirectional mappings? */
+}
+EXPORT_SYMBOL(___dma_page_cpu_to_dev);
+void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
+        size_t size, enum dma_data_direction dir)
+{
+        unsigned long paddr = page_to_phys(page) + off;
+        /* FIXME: non-speculating: not required */
+        /* don't bother invalidating if DMA to device */
+        if (dir != DMA_TO_DEVICE)
+                outer_inv_range(paddr, paddr + size);
+        dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
+}
+EXPORT_SYMBOL(___dma_page_dev_to_cpu);
 /**
 * dma_map_sg - map a set of SG buffers for streaming mode DMA
@@ -573,8 +581,12 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
        int i;
        for_each_sg(sg, s, nents, i) {
-                dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0,
+                if (!dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0,
-                                        sg_dma_len(s), dir);
+                                            sg_dma_len(s), dir))
+                        continue;
+                __dma_page_dev_to_cpu(sg_page(s), s->offset,
+                                      s->length, dir);
        }
 }
 EXPORT_SYMBOL(dma_sync_sg_for_cpu);
@@ -597,9 +609,8 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
                                        sg_dma_len(s), dir))
                        continue;
-                if (!arch_is_coherent())
+                __dma_page_cpu_to_dev(sg_page(s), s->offset,
-                        dma_cache_maint_page(sg_page(s), s->offset,
+                                      s->length, dir);
-                                             s->length, dir);
        }
 }
 EXPORT_SYMBOL(dma_sync_sg_for_device);
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 56ee15321b00..c9b97e9836a2 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -36,28 +36,12 @@ static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
 * Therefore those configurations which might call adjust_pte (those
 * without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock.
 */
-static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
+static int do_adjust_pte(struct vm_area_struct *vma, unsigned long address,
+        unsigned long pfn, pte_t *ptep)
 {
-        pgd_t *pgd;
+        pte_t entry = *ptep;
-        pmd_t *pmd;
-        pte_t *pte, entry;
        int ret;
-        pgd = pgd_offset(vma->vm_mm, address);
-        if (pgd_none(*pgd))
-                goto no_pgd;
-        if (pgd_bad(*pgd))
-                goto bad_pgd;
-        pmd = pmd_offset(pgd, address);
-        if (pmd_none(*pmd))
-                goto no_pmd;
-        if (pmd_bad(*pmd))
-                goto bad_pmd;
-        pte = pte_offset_map(pmd, address);
-        entry = *pte;
        /*
         * If this page is present, it's actually being shared.
         */
@@ -68,33 +52,55 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
         * fault (ie, is old), we can safely ignore any issues.
         */
        if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
-                unsigned long pfn = pte_pfn(entry);
                flush_cache_page(vma, address, pfn);
                outer_flush_range((pfn << PAGE_SHIFT),
                                  (pfn << PAGE_SHIFT) + PAGE_SIZE);
                pte_val(entry) &= ~L_PTE_MT_MASK;
                pte_val(entry) |= shared_pte_mask;
-                set_pte_at(vma->vm_mm, address, pte, entry);
+                set_pte_at(vma->vm_mm, address, ptep, entry);
                flush_tlb_page(vma, address);
        }
-        pte_unmap(pte);
        return ret;
+}
+static int adjust_pte(struct vm_area_struct *vma, unsigned long address,
+        unsigned long pfn)
+{
+        spinlock_t *ptl;
+        pgd_t *pgd;
+        pmd_t *pmd;
+        pte_t *pte;
+        int ret;
+        pgd = pgd_offset(vma->vm_mm, address);
+        if (pgd_none_or_clear_bad(pgd))
+                return 0;
+        pmd = pmd_offset(pgd, address);
+        if (pmd_none_or_clear_bad(pmd))
+                return 0;
-bad_pgd:
+        /*
-        pgd_ERROR(*pgd);
+         * This is called while another page table is mapped, so we
-        pgd_clear(pgd);
+         * must use the nested version.  This also means we need to
-no_pgd:
+         * open-code the spin-locking.
-        return 0;
+         */
+        ptl = pte_lockptr(vma->vm_mm, pmd);
-bad_pmd:
+        pte = pte_offset_map_nested(pmd, address);
-        pmd_ERROR(*pmd);
+        spin_lock(ptl);
-        pmd_clear(pmd);
-no_pmd:
+        ret = do_adjust_pte(vma, address, pfn, pte);
-        return 0;
+        spin_unlock(ptl);
+        pte_unmap_nested(pte);
+        return ret;
 }
 static void
-make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
+make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
+        unsigned long addr, pte_t *ptep, unsigned long pfn)
 {
        struct mm_struct *mm = vma->vm_mm;
        struct vm_area_struct *mpnt;
@@ -122,11 +128,11 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigne
                if (!(mpnt->vm_flags & VM_MAYSHARE))
                        continue;
                offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
-                aliases += adjust_pte(mpnt, mpnt->vm_start + offset);
+                aliases += adjust_pte(mpnt, mpnt->vm_start + offset, pfn);
        }
        flush_dcache_mmap_unlock(mapping);
        if (aliases)
-                adjust_pte(vma, addr);
+                do_adjust_pte(vma, addr, pfn, ptep);
        else
                flush_cache_page(vma, addr, pfn);
 }
@@ -144,9 +150,10 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigne
 *
 * Note that the pte lock will be held.
 */
-void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
+        pte_t *ptep)
 {
-        unsigned long pfn = pte_pfn(pte);
+        unsigned long pfn = pte_pfn(*ptep);
        struct address_space *mapping;
        struct page *page;
@@ -168,7 +175,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
 #endif
        if (mapping) {
                if (cache_is_vivt())
-                        make_coherent(mapping, vma, addr, pfn);
+                        make_coherent(mapping, vma, addr, ptep, pfn);
                else if (vma->vm_flags & VM_EXEC)
                        __flush_icache_all();
        }
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 6f3a4b7a3b82..e34f095e2090 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -13,6 +13,7 @@
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
+#include <asm/smp_plat.h>
 #include <asm/system.h>
 #include <asm/tlbflush.h>
@@ -87,13 +88,26 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
        if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged())
                __flush_icache_all();
 }
+#else
+#define flush_pfn_alias(pfn,vaddr)      do { } while (0)
+#endif
+#ifdef CONFIG_SMP
+static void flush_ptrace_access_other(void *args)
+{
+        __flush_icache_all();
+}
+#endif
+static
 void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
-                         unsigned long uaddr, void *kaddr,
+                         unsigned long uaddr, void *kaddr, unsigned long len)
-                         unsigned long len, int write)
 {
        if (cache_is_vivt()) {
-                vivt_flush_ptrace_access(vma, page, uaddr, kaddr, len, write);
+                if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
+                        unsigned long addr = (unsigned long)kaddr;
+                        __cpuc_coherent_kern_range(addr, addr + len);
+                }
                return;
        }
@@ -104,16 +118,37 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
        }
        /* VIPT non-aliasing cache */
-        if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)) &&
+        if (vma->vm_flags & VM_EXEC) {
-            vma->vm_flags & VM_EXEC) {
                unsigned long addr = (unsigned long)kaddr;
-                /* only flushing the kernel mapping on non-aliasing VIPT */
                __cpuc_coherent_kern_range(addr, addr + len);
+#ifdef CONFIG_SMP
+                if (cache_ops_need_broadcast())
+                        smp_call_function(flush_ptrace_access_other,
+                                          NULL, 1);
+#endif
        }
 }
-#else
-#define flush_pfn_alias(pfn,vaddr)      do { } while (0)
+/*
+ * Copy user data from/to a page which is mapped into a different
+ * processes address space.  Really, we want to allow our "user
+ * space" model to handle this.
+ *
+ * Note that this code needs to run on the current CPU.
+ */
+void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
+                       unsigned long uaddr, void *dst, const void *src,
+                       unsigned long len)
+{
+#ifdef CONFIG_SMP
+        preempt_disable();
 #endif
+        memcpy(dst, src, len);
+        flush_ptrace_access(vma, page, uaddr, dst, len);
+#ifdef CONFIG_SMP
+        preempt_enable();
+#endif
+}
 void __flush_dcache_page(struct address_space *mapping, struct page *page)
 {
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 52c40d155672..a04ffbbbe253 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -616,7 +616,7 @@ void __init mem_init(void)
                "%dK data, %dK init, %luK highmem)\n",
                nr_free_pages() << (PAGE_SHIFT-10), codesize >> 10,
                datasize >> 10, initsize >> 10,
-                (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
+                totalhigh_pages << (PAGE_SHIFT-10));
        if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
                extern int sysctl_overcommit_memory;
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 8012e24282b2..72507c630ceb 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -265,7 +265,7 @@ ENTRY(arm1020_flush_kern_dcache_area)
 *
 * (same as v4wb)
 */
-ENTRY(arm1020_dma_inv_range)
+arm1020_dma_inv_range:
        mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
        tst     r0, #CACHE_DLINESIZE - 1
@@ -295,7 +295,7 @@ ENTRY(arm1020_dma_inv_range)
 *
 * (same as v4wb)
 */
-ENTRY(arm1020_dma_clean_range)
+arm1020_dma_clean_range:
        mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
        bic     r0, r0, #CACHE_DLINESIZE - 1
@@ -330,6 +330,30 @@ ENTRY(arm1020_dma_flush_range)
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
        mov     pc, lr
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1020_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm1020_dma_clean_range
+        bcs     arm1020_dma_inv_range
+        b       arm1020_dma_flush_range
+ENDPROC(arm1020_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1020_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm1020_dma_unmap_area)
 ENTRY(arm1020_cache_fns)
        .long   arm1020_flush_kern_cache_all
        .long   arm1020_flush_user_cache_all
@@ -337,8 +361,8 @@ ENTRY(arm1020_cache_fns)
        .long   arm1020_coherent_kern_range
        .long   arm1020_coherent_user_range
        .long   arm1020_flush_kern_dcache_area
-        .long   arm1020_dma_inv_range
+        .long   arm1020_dma_map_area
-        .long   arm1020_dma_clean_range
+        .long   arm1020_dma_unmap_area
        .long   arm1020_dma_flush_range
        .align  5
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 41fe25d234f5..d27829805609 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -258,7 +258,7 @@ ENTRY(arm1020e_flush_kern_dcache_area)
 *
 * (same as v4wb)
 */
-ENTRY(arm1020e_dma_inv_range)
+arm1020e_dma_inv_range:
        mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
        tst     r0, #CACHE_DLINESIZE - 1
@@ -284,7 +284,7 @@ ENTRY(arm1020e_dma_inv_range)
 *
 * (same as v4wb)
 */
-ENTRY(arm1020e_dma_clean_range)
+arm1020e_dma_clean_range:
        mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
        bic     r0, r0, #CACHE_DLINESIZE - 1
@@ -316,6 +316,30 @@ ENTRY(arm1020e_dma_flush_range)
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
        mov     pc, lr
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1020e_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm1020e_dma_clean_range
+        bcs     arm1020e_dma_inv_range
+        b       arm1020e_dma_flush_range
+ENDPROC(arm1020e_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1020e_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm1020e_dma_unmap_area)
 ENTRY(arm1020e_cache_fns)
        .long   arm1020e_flush_kern_cache_all
        .long   arm1020e_flush_user_cache_all
@@ -323,8 +347,8 @@ ENTRY(arm1020e_cache_fns)
        .long   arm1020e_coherent_kern_range
        .long   arm1020e_coherent_user_range
        .long   arm1020e_flush_kern_dcache_area
-        .long   arm1020e_dma_inv_range
+        .long   arm1020e_dma_map_area
-        .long   arm1020e_dma_clean_range
+        .long   arm1020e_dma_unmap_area
        .long   arm1020e_dma_flush_range
        .align  5
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 20a5b1b31a70..ce13e4a827de 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -247,7 +247,7 @@ ENTRY(arm1022_flush_kern_dcache_area)
 *
 * (same as v4wb)
 */
-ENTRY(arm1022_dma_inv_range)
+arm1022_dma_inv_range:
        mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
        tst     r0, #CACHE_DLINESIZE - 1
@@ -273,7 +273,7 @@ ENTRY(arm1022_dma_inv_range)
 *
 * (same as v4wb)
 */
-ENTRY(arm1022_dma_clean_range)
+arm1022_dma_clean_range:
        mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
        bic     r0, r0, #CACHE_DLINESIZE - 1
@@ -305,6 +305,30 @@ ENTRY(arm1022_dma_flush_range)
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
        mov     pc, lr
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1022_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm1022_dma_clean_range
+        bcs     arm1022_dma_inv_range
+        b       arm1022_dma_flush_range
+ENDPROC(arm1022_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1022_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm1022_dma_unmap_area)
 ENTRY(arm1022_cache_fns)
        .long   arm1022_flush_kern_cache_all
        .long   arm1022_flush_user_cache_all
@@ -312,8 +336,8 @@ ENTRY(arm1022_cache_fns)
        .long   arm1022_coherent_kern_range
        .long   arm1022_coherent_user_range
        .long   arm1022_flush_kern_dcache_area
-        .long   arm1022_dma_inv_range
+        .long   arm1022_dma_map_area
-        .long   arm1022_dma_clean_range
+        .long   arm1022_dma_unmap_area
        .long   arm1022_dma_flush_range
        .align  5
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 96aedb10fcc4..636672a29c6d 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -241,7 +241,7 @@ ENTRY(arm1026_flush_kern_dcache_area)
 *
 * (same as v4wb)
 */
-ENTRY(arm1026_dma_inv_range)
+arm1026_dma_inv_range:
        mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
        tst     r0, #CACHE_DLINESIZE - 1
@@ -267,7 +267,7 @@ ENTRY(arm1026_dma_inv_range)
 *
 * (same as v4wb)
 */
-ENTRY(arm1026_dma_clean_range)
+arm1026_dma_clean_range:
        mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
        bic     r0, r0, #CACHE_DLINESIZE - 1
@@ -299,6 +299,30 @@ ENTRY(arm1026_dma_flush_range)
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
        mov     pc, lr
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1026_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm1026_dma_clean_range
+        bcs     arm1026_dma_inv_range
+        b       arm1026_dma_flush_range
+ENDPROC(arm1026_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1026_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm1026_dma_unmap_area)
 ENTRY(arm1026_cache_fns)
        .long   arm1026_flush_kern_cache_all
        .long   arm1026_flush_user_cache_all
@@ -306,8 +330,8 @@ ENTRY(arm1026_cache_fns)
        .long   arm1026_coherent_kern_range
        .long   arm1026_coherent_user_range
        .long   arm1026_flush_kern_dcache_area
-        .long   arm1026_dma_inv_range
+        .long   arm1026_dma_map_area
-        .long   arm1026_dma_clean_range
+        .long   arm1026_dma_unmap_area
        .long   arm1026_dma_flush_range
        .align  5
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 471669e2d7cb..8be81992645d 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -239,7 +239,7 @@ ENTRY(arm920_flush_kern_dcache_area)
 *
 * (same as v4wb)
 */
-ENTRY(arm920_dma_inv_range)
+arm920_dma_inv_range:
        tst     r0, #CACHE_DLINESIZE - 1
        bic     r0, r0, #CACHE_DLINESIZE - 1
        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -262,7 +262,7 @@ ENTRY(arm920_dma_inv_range)
 *
 * (same as v4wb)
 */
-ENTRY(arm920_dma_clean_range)
+arm920_dma_clean_range:
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        add     r0, r0, #CACHE_DLINESIZE
@@ -288,6 +288,30 @@ ENTRY(arm920_dma_flush_range)
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm920_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm920_dma_clean_range
+        bcs     arm920_dma_inv_range
+        b       arm920_dma_flush_range
+ENDPROC(arm920_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm920_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm920_dma_unmap_area)
 ENTRY(arm920_cache_fns)
        .long   arm920_flush_kern_cache_all
        .long   arm920_flush_user_cache_all
@@ -295,8 +319,8 @@ ENTRY(arm920_cache_fns)
        .long   arm920_coherent_kern_range
        .long   arm920_coherent_user_range
        .long   arm920_flush_kern_dcache_area
-        .long   arm920_dma_inv_range
+        .long   arm920_dma_map_area
-        .long   arm920_dma_clean_range
+        .long   arm920_dma_unmap_area
        .long   arm920_dma_flush_range
 #endif
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index ee111b00fa41..c0ff8e4b1074 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -241,7 +241,7 @@ ENTRY(arm922_flush_kern_dcache_area)
 *
 * (same as v4wb)
 */
-ENTRY(arm922_dma_inv_range)
+arm922_dma_inv_range:
        tst     r0, #CACHE_DLINESIZE - 1
        bic     r0, r0, #CACHE_DLINESIZE - 1
        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -264,7 +264,7 @@ ENTRY(arm922_dma_inv_range)
 *
 * (same as v4wb)
 */
-ENTRY(arm922_dma_clean_range)
+arm922_dma_clean_range:
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        add     r0, r0, #CACHE_DLINESIZE
@@ -290,6 +290,30 @@ ENTRY(arm922_dma_flush_range)
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm922_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm922_dma_clean_range
+        bcs     arm922_dma_inv_range
+        b       arm922_dma_flush_range
+ENDPROC(arm922_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm922_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm922_dma_unmap_area)
 ENTRY(arm922_cache_fns)
        .long   arm922_flush_kern_cache_all
        .long   arm922_flush_user_cache_all
@@ -297,8 +321,8 @@ ENTRY(arm922_cache_fns)
        .long   arm922_coherent_kern_range
        .long   arm922_coherent_user_range
        .long   arm922_flush_kern_dcache_area
-        .long   arm922_dma_inv_range
+        .long   arm922_dma_map_area
-        .long   arm922_dma_clean_range
+        .long   arm922_dma_unmap_area
        .long   arm922_dma_flush_range
 #endif
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 8deb5bde58e4..3c6cffe400f6 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -283,7 +283,7 @@ ENTRY(arm925_flush_kern_dcache_area)
 *
 * (same as v4wb)
 */
-ENTRY(arm925_dma_inv_range)
+arm925_dma_inv_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
        tst     r0, #CACHE_DLINESIZE - 1
        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -308,7 +308,7 @@ ENTRY(arm925_dma_inv_range)
 *
 * (same as v4wb)
 */
-ENTRY(arm925_dma_clean_range)
+arm925_dma_clean_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -341,6 +341,30 @@ ENTRY(arm925_dma_flush_range)
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm925_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm925_dma_clean_range
+        bcs     arm925_dma_inv_range
+        b       arm925_dma_flush_range
+ENDPROC(arm925_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm925_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm925_dma_unmap_area)
 ENTRY(arm925_cache_fns)
        .long   arm925_flush_kern_cache_all
        .long   arm925_flush_user_cache_all
@@ -348,8 +372,8 @@ ENTRY(arm925_cache_fns)
        .long   arm925_coherent_kern_range
        .long   arm925_coherent_user_range
        .long   arm925_flush_kern_dcache_area
-        .long   arm925_dma_inv_range
+        .long   arm925_dma_map_area
-        .long   arm925_dma_clean_range
+        .long   arm925_dma_unmap_area
        .long   arm925_dma_flush_range
 ENTRY(cpu_arm925_dcache_clean_area)
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 64db6e275a44..75b707c9cce1 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -246,7 +246,7 @@ ENTRY(arm926_flush_kern_dcache_area)
 *
 * (same as v4wb)
 */
-ENTRY(arm926_dma_inv_range)
+arm926_dma_inv_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
        tst     r0, #CACHE_DLINESIZE - 1
        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -271,7 +271,7 @@ ENTRY(arm926_dma_inv_range)
 *
 * (same as v4wb)
 */
-ENTRY(arm926_dma_clean_range)
+arm926_dma_clean_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -304,6 +304,30 @@ ENTRY(arm926_dma_flush_range)
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm926_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm926_dma_clean_range
+        bcs     arm926_dma_inv_range
+        b       arm926_dma_flush_range
+ENDPROC(arm926_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm926_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm926_dma_unmap_area)
 ENTRY(arm926_cache_fns)
        .long   arm926_flush_kern_cache_all
        .long   arm926_flush_user_cache_all
@@ -311,8 +335,8 @@ ENTRY(arm926_cache_fns)
        .long   arm926_coherent_kern_range
        .long   arm926_coherent_user_range
        .long   arm926_flush_kern_dcache_area
-        .long   arm926_dma_inv_range
+        .long   arm926_dma_map_area
-        .long   arm926_dma_clean_range
+        .long   arm926_dma_unmap_area
        .long   arm926_dma_flush_range
 ENTRY(cpu_arm926_dcache_clean_area)
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 8196b9f401fb..1af1657819eb 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -171,7 +171,7 @@ ENTRY(arm940_flush_kern_dcache_area)
 *      - start - virtual start address
 *      - end   - virtual end address
 */
-ENTRY(arm940_dma_inv_range)
+arm940_dma_inv_range:
        mov     ip, #0
        mov     r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
 1:      orr     r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
@@ -192,7 +192,7 @@ ENTRY(arm940_dma_inv_range)
 *      - start - virtual start address
 *      - end   - virtual end address
 */
-ENTRY(arm940_dma_clean_range)
+arm940_dma_clean_range:
 ENTRY(cpu_arm940_dcache_clean_area)
        mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -233,6 +233,30 @@ ENTRY(arm940_dma_flush_range)
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
        mov     pc, lr
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm940_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm940_dma_clean_range
+        bcs     arm940_dma_inv_range
+        b       arm940_dma_flush_range
+ENDPROC(arm940_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm940_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm940_dma_unmap_area)
 ENTRY(arm940_cache_fns)
        .long   arm940_flush_kern_cache_all
        .long   arm940_flush_user_cache_all
@@ -240,8 +264,8 @@ ENTRY(arm940_cache_fns)
        .long   arm940_coherent_kern_range
        .long   arm940_coherent_user_range
        .long   arm940_flush_kern_dcache_area
-        .long   arm940_dma_inv_range
+        .long   arm940_dma_map_area
-        .long   arm940_dma_clean_range
+        .long   arm940_dma_unmap_area
        .long   arm940_dma_flush_range
        __INIT
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 9a951239c86c..1664b6aaff79 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -215,7 +215,7 @@ ENTRY(arm946_flush_kern_dcache_area)
 *      - end   - virtual end address
 * (same as arm926)
 */
-ENTRY(arm946_dma_inv_range)
+arm946_dma_inv_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
        tst     r0, #CACHE_DLINESIZE - 1
        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -240,7 +240,7 @@ ENTRY(arm946_dma_inv_range)
 *
 * (same as arm926)
 */
-ENTRY(arm946_dma_clean_range)
+arm946_dma_clean_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -275,6 +275,30 @@ ENTRY(arm946_dma_flush_range)
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm946_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm946_dma_clean_range
+        bcs     arm946_dma_inv_range
+        b       arm946_dma_flush_range
+ENDPROC(arm946_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm946_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm946_dma_unmap_area)
 ENTRY(arm946_cache_fns)
        .long   arm946_flush_kern_cache_all
        .long   arm946_flush_user_cache_all
@@ -282,8 +306,8 @@ ENTRY(arm946_cache_fns)
        .long   arm946_coherent_kern_range
        .long   arm946_coherent_user_range
        .long   arm946_flush_kern_dcache_area
-        .long   arm946_dma_inv_range
+        .long   arm946_dma_map_area
-        .long   arm946_dma_clean_range
+        .long   arm946_dma_unmap_area
        .long   arm946_dma_flush_range
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index dbc39383e66a..53e632343849 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -274,7 +274,7 @@ ENTRY(feroceon_range_flush_kern_dcache_area)
 * (same as v4wb)
 */
        .align  5
-ENTRY(feroceon_dma_inv_range)
+feroceon_dma_inv_range:
        tst     r0, #CACHE_DLINESIZE - 1
        bic     r0, r0, #CACHE_DLINESIZE - 1
        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -288,7 +288,7 @@ ENTRY(feroceon_dma_inv_range)
        mov     pc, lr
        .align  5
-ENTRY(feroceon_range_dma_inv_range)
+feroceon_range_dma_inv_range:
        mrs     r2, cpsr
        tst     r0, #CACHE_DLINESIZE - 1
        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -314,7 +314,7 @@ ENTRY(feroceon_range_dma_inv_range)
 * (same as v4wb)
 */
        .align  5
-ENTRY(feroceon_dma_clean_range)
+feroceon_dma_clean_range:
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        add     r0, r0, #CACHE_DLINESIZE
@@ -324,7 +324,7 @@ ENTRY(feroceon_dma_clean_range)
        mov     pc, lr
        .align  5
-ENTRY(feroceon_range_dma_clean_range)
+feroceon_range_dma_clean_range:
        mrs     r2, cpsr
        cmp     r1, r0
        subne   r1, r1, #1                      @ top address is inclusive
@@ -367,6 +367,44 @@ ENTRY(feroceon_range_dma_flush_range)
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(feroceon_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     feroceon_dma_clean_range
+        bcs     feroceon_dma_inv_range
+        b       feroceon_dma_flush_range
+ENDPROC(feroceon_dma_map_area)
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(feroceon_range_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     feroceon_range_dma_clean_range
+        bcs     feroceon_range_dma_inv_range
+        b       feroceon_range_dma_flush_range
+ENDPROC(feroceon_range_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(feroceon_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(feroceon_dma_unmap_area)
 ENTRY(feroceon_cache_fns)
        .long   feroceon_flush_kern_cache_all
        .long   feroceon_flush_user_cache_all
@@ -374,8 +412,8 @@ ENTRY(feroceon_cache_fns)
        .long   feroceon_coherent_kern_range
        .long   feroceon_coherent_user_range
        .long   feroceon_flush_kern_dcache_area
-        .long   feroceon_dma_inv_range
+        .long   feroceon_dma_map_area
-        .long   feroceon_dma_clean_range
+        .long   feroceon_dma_unmap_area
        .long   feroceon_dma_flush_range
 ENTRY(feroceon_range_cache_fns)
@@ -385,8 +423,8 @@ ENTRY(feroceon_range_cache_fns)
        .long   feroceon_coherent_kern_range
        .long   feroceon_coherent_user_range
        .long   feroceon_range_flush_kern_dcache_area
-        .long   feroceon_range_dma_inv_range
+        .long   feroceon_range_dma_map_area
-        .long   feroceon_range_dma_clean_range
+        .long   feroceon_dma_unmap_area
        .long   feroceon_range_dma_flush_range
        .align  5
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index 9674d36cc97d..caa31154e7db 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -218,7 +218,7 @@ ENTRY(mohawk_flush_kern_dcache_area)
 *
 * (same as v4wb)
 */
-ENTRY(mohawk_dma_inv_range)
+mohawk_dma_inv_range:
        tst     r0, #CACHE_DLINESIZE - 1
        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
        tst     r1, #CACHE_DLINESIZE - 1
@@ -241,7 +241,7 @@ ENTRY(mohawk_dma_inv_range)
 *
 * (same as v4wb)
 */
-ENTRY(mohawk_dma_clean_range)
+mohawk_dma_clean_range:
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        add     r0, r0, #CACHE_DLINESIZE
@@ -268,6 +268,30 @@ ENTRY(mohawk_dma_flush_range)
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(mohawk_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     mohawk_dma_clean_range
+        bcs     mohawk_dma_inv_range
+        b       mohawk_dma_flush_range
+ENDPROC(mohawk_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(mohawk_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(mohawk_dma_unmap_area)
 ENTRY(mohawk_cache_fns)
        .long   mohawk_flush_kern_cache_all
        .long   mohawk_flush_user_cache_all
@@ -275,8 +299,8 @@ ENTRY(mohawk_cache_fns)
        .long   mohawk_coherent_kern_range
        .long   mohawk_coherent_user_range
        .long   mohawk_flush_kern_dcache_area
-        .long   mohawk_dma_inv_range
+        .long   mohawk_dma_map_area
-        .long   mohawk_dma_clean_range
+        .long   mohawk_dma_unmap_area
        .long   mohawk_dma_flush_range
 ENTRY(cpu_mohawk_dcache_clean_area)
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 96456f548798..e5797f1c1db7 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -257,7 +257,7 @@ ENTRY(xsc3_flush_kern_dcache_area)
 *      - start  - virtual start address
 *      - end    - virtual end address
 */
-ENTRY(xsc3_dma_inv_range)
+xsc3_dma_inv_range:
        tst     r0, #CACHELINESIZE - 1
        bic     r0, r0, #CACHELINESIZE - 1
        mcrne   p15, 0, r0, c7, c10, 1          @ clean L1 D line
@@ -278,7 +278,7 @@ ENTRY(xsc3_dma_inv_range)
 *      - start  - virtual start address
 *      - end    - virtual end address
 */
-ENTRY(xsc3_dma_clean_range)
+xsc3_dma_clean_range:
        bic     r0, r0, #CACHELINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean L1 D line
        add     r0, r0, #CACHELINESIZE
@@ -304,6 +304,30 @@ ENTRY(xsc3_dma_flush_range)
        mcr     p15, 0, r0, c7, c10, 4          @ data write barrier
        mov     pc, lr
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(xsc3_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     xsc3_dma_clean_range
+        bcs     xsc3_dma_inv_range
+        b       xsc3_dma_flush_range
+ENDPROC(xsc3_dma_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(xsc3_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(xsc3_dma_unmap_area)
 ENTRY(xsc3_cache_fns)
        .long   xsc3_flush_kern_cache_all
        .long   xsc3_flush_user_cache_all
@@ -311,8 +335,8 @@ ENTRY(xsc3_cache_fns)
        .long   xsc3_coherent_kern_range
        .long   xsc3_coherent_user_range
        .long   xsc3_flush_kern_dcache_area
-        .long   xsc3_dma_inv_range
+        .long   xsc3_dma_map_area
-        .long   xsc3_dma_clean_range
+        .long   xsc3_dma_unmap_area
        .long   xsc3_dma_flush_range
 ENTRY(cpu_xsc3_dcache_clean_area)
@@ -407,6 +431,13 @@ __xsc3_setup:
        adr     r5, xsc3_crval
        ldmia   r5, {r5, r6}
+#ifdef CONFIG_CACHE_XSC3L2
+        mrc     p15, 1, r0, c0, c0, 1           @ get L2 present information
+        ands    r0, r0, #0xf8
+        orrne   r6, r6, #(1 << 26)              @ enable L2 if present
+#endif
        mrc     p15, 0, r0, c1, c0, 0           @ get control register
        bic     r0, r0, r5                      @ ..V. ..R. .... ..A.
        orr     r0, r0, r6                      @ ..VI Z..S .... .C.M (mmu)
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 93df47265f2d..63037e2162f2 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -315,7 +315,7 @@ ENTRY(xscale_flush_kern_dcache_area)
 *      - start  - virtual start address
 *      - end    - virtual end address
 */
-ENTRY(xscale_dma_inv_range)
+xscale_dma_inv_range:
        tst     r0, #CACHELINESIZE - 1
        bic     r0, r0, #CACHELINESIZE - 1
        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -336,7 +336,7 @@ ENTRY(xscale_dma_inv_range)
 *      - start  - virtual start address
 *      - end    - virtual end address
 */
-ENTRY(xscale_dma_clean_range)
+xscale_dma_clean_range:
        bic     r0, r0, #CACHELINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        add     r0, r0, #CACHELINESIZE
@@ -363,6 +363,43 @@ ENTRY(xscale_dma_flush_range)
        mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
        mov     pc, lr
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(xscale_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     xscale_dma_clean_range
+        bcs     xscale_dma_inv_range
+        b       xscale_dma_flush_range
+ENDPROC(xscale_dma_map_area)
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(xscale_dma_a0_map_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_TO_DEVICE
+        beq     xscale_dma_clean_range
+        b       xscale_dma_flush_range
+ENDPROC(xscsale_dma_a0_map_area)
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(xscale_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(xscale_dma_unmap_area)
 ENTRY(xscale_cache_fns)
        .long   xscale_flush_kern_cache_all
        .long   xscale_flush_user_cache_all
@@ -370,8 +407,8 @@ ENTRY(xscale_cache_fns)
        .long   xscale_coherent_kern_range
        .long   xscale_coherent_user_range
        .long   xscale_flush_kern_dcache_area
-        .long   xscale_dma_inv_range
+        .long   xscale_dma_map_area
-        .long   xscale_dma_clean_range
+        .long   xscale_dma_unmap_area
        .long   xscale_dma_flush_range
 /*
@@ -394,8 +431,8 @@ ENTRY(xscale_80200_A0_A1_cache_fns)
        .long   xscale_coherent_kern_range
        .long   xscale_coherent_user_range
        .long   xscale_flush_kern_dcache_area
-        .long   xscale_dma_flush_range
+        .long   xscale_dma_a0_map_area
-        .long   xscale_dma_clean_range
+        .long   xscale_dma_unmap_area
        .long   xscale_dma_flush_range
 ENTRY(cpu_xscale_dcache_clean_area)
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index a26a605b73bd..0cb1848bd876 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -40,7 +40,6 @@ ENTRY(v7wbi_flush_user_tlb_range)
        asid    r3, r3                          @ mask ASID
        orr     r0, r3, r0, lsl #PAGE_SHIFT     @ Create initial MVA
        mov     r1, r1, lsl #PAGE_SHIFT
-        vma_vm_flags r2, r2                     @ get vma->vm_flags
 1:
 #ifdef CONFIG_SMP
        mcr     p15, 0, r0, c8, c3, 1           @ TLB invalidate U MVA (shareable) 
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index 810c47f56e77..9af494f0ab3d 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -58,19 +58,19 @@
 #define MX25_PAD_A18__A18               IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_A18__GPIO_2_4          IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A18__FEC_COL           IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTL)
+#define MX25_PAD_A18__FEC_COL           IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL)
 #define MX25_PAD_A19__A19               IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A19__FEC_RX_ER         IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTL)
+#define MX25_PAD_A19__FEC_RX_ER         IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL)
 #define MX25_PAD_A19__GPIO_2_5          IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_A20__A20               IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_A20__GPIO_2_6          IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A20__FEC_RDATA2        IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTL)
+#define MX25_PAD_A20__FEC_RDATA2        IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL)
 #define MX25_PAD_A21__A21               IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_A21__GPIO_2_7          IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A21__FEC_RDATA3        IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTL)
+#define MX25_PAD_A21__FEC_RDATA3        IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL)
 #define MX25_PAD_A22__A22               IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_A22__GPIO_2_8          IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL)
@@ -80,11 +80,11 @@
 #define MX25_PAD_A24__A24               IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_A24__GPIO_2_10         IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A24__FEC_RX_CLK        IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTL)
+#define MX25_PAD_A24__FEC_RX_CLK        IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL)
 #define MX25_PAD_A25__A25               IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_A25__GPIO_2_11         IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_A25__FEC_CRS           IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTL)
+#define MX25_PAD_A25__FEC_CRS           IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL)
 #define MX25_PAD_EB0__EB0               IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_EB0__AUD4_TXD          IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL)
@@ -112,7 +112,7 @@
 #define MX25_PAD_CS5__UART5_RTS         IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
 #define MX25_PAD_CS5__GPIO_3_21         IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_NF_CE0__NF_CE0         IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_NF_CE0__NF_CE0         IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_NF_CE0__GPIO_3_22      IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_ECB__ECB               IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL)
@@ -229,28 +229,28 @@
 #define MX25_PAD_LD7__GPIO_1_21         IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_LD8__LD8               IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD8__FEC_TX_ERR        IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_LD8__FEC_TX_ERR        IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_LD9__LD9               IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD9__FEC_COL           IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTL)
+#define MX25_PAD_LD9__FEC_COL           IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL)
 #define MX25_PAD_LD10__LD10             IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD10__FEC_RX_ER        IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTL)
+#define MX25_PAD_LD10__FEC_RX_ER        IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL)
 #define MX25_PAD_LD11__LD11             IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD11__FEC_RDATA2       IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTL)
+#define MX25_PAD_LD11__FEC_RDATA2       IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL)
 #define MX25_PAD_LD12__LD12             IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD12__FEC_RDATA3       IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTL)
+#define MX25_PAD_LD12__FEC_RDATA3       IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL)
 #define MX25_PAD_LD13__LD13             IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD13__FEC_TDATA2       IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_LD13__FEC_TDATA2       IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_LD14__LD14             IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD14__FEC_TDATA3       IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_LD14__FEC_TDATA3       IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_LD15__LD15             IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_LD15__FEC_RX_CLK       IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTL)
+#define MX25_PAD_LD15__FEC_RX_CLK       IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL)
 #define MX25_PAD_HSYNC__HSYNC           IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_HSYNC__GPIO_1_22       IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL)
@@ -265,7 +265,7 @@
 #define MX25_PAD_OE_ACD__GPIO_1_25      IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CONTRAST__CONTRAST     IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_CONTRAST__FEC_CRS      IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTL)
+#define MX25_PAD_CONTRAST__FEC_CRS      IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL)
 #define MX25_PAD_PWM__PWM               IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_PWM__GPIO_1_26         IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL)
@@ -354,19 +354,19 @@
 #define MX25_PAD_UART2_TXD__GPIO_4_27   IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_UART2_RTS__UART2_RTS   IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_RTS__FEC_COL     IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTL)
+#define MX25_PAD_UART2_RTS__FEC_COL     IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL)
 #define MX25_PAD_UART2_RTS__GPIO_4_28   IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_UART2_CTS__FEC_RX_ER   IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTL)
+#define MX25_PAD_UART2_CTS__FEC_RX_ER   IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL)
 #define MX25_PAD_UART2_CTS__UART2_CTS   IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_UART2_CTS__GPIO_4_29   IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_CMD__SD1_CMD       IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_CMD__FEC_RDATA2    IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTL)
+#define MX25_PAD_SD1_CMD__FEC_RDATA2    IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL)
 #define MX25_PAD_SD1_CMD__GPIO_2_23     IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_CLK__SD1_CLK       IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_CLK__FEC_RDATA3    IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTL)
+#define MX25_PAD_SD1_CLK__FEC_RDATA3    IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL)
 #define MX25_PAD_SD1_CLK__GPIO_2_24     IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA0__SD1_DATA0   IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
@@ -377,11 +377,11 @@
 #define MX25_PAD_SD1_DATA1__GPIO_2_26   IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA2__SD1_DATA2   IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA2__FEC_RX_CLK  IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTL)
+#define MX25_PAD_SD1_DATA2__FEC_RX_CLK  IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA2__GPIO_2_27   IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA3__SD1_DATA3   IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
-#define MX25_PAD_SD1_DATA3__FEC_CRS     IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTL)
+#define MX25_PAD_SD1_DATA3__FEC_CRS     IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA3__GPIO_2_28   IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_KPP_ROW0__KPP_ROW0     IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE)
@@ -410,7 +410,7 @@
 #define MX25_PAD_KPP_COL3__KPP_COL3     IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
 #define MX25_PAD_KPP_COL3__GPIO_3_4     IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_MDC__FEC_MDC       IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_FEC_MDC__FEC_MDC       IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_FEC_MDC__AUD4_TXD      IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL)
 #define MX25_PAD_FEC_MDC__GPIO_3_5      IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL)
@@ -418,23 +418,23 @@
 #define MX25_PAD_FEC_MDIO__AUD4_RXD     IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL)
 #define MX25_PAD_FEC_MDIO__GPIO_3_6     IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_FEC_TDATA0__GPIO_3_7   IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_FEC_TDATA1__AUD4_TXFS  IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL)
 #define MX25_PAD_FEC_TDATA1__GPIO_3_8   IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_TX_EN__FEC_TX_EN   IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_FEC_TX_EN__FEC_TX_EN   IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_FEC_TX_EN__GPIO_3_9    IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
+#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
 #define MX25_PAD_FEC_RDATA0__GPIO_3_10  IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
+#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
 #define MX25_PAD_FEC_RDATA1__GPIO_3_11  IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_FEC_RX_DV__FEC_RX_DV   IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
+#define MX25_PAD_FEC_RX_DV__FEC_RX_DV   IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
 #define MX25_PAD_FEC_RX_DV__CAN2_RX     IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP)
 #define MX25_PAD_FEC_RX_DV__GPIO_3_12   IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 91e738144804..854e2dc58481 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -41,4 +41,8 @@
 #define UART1_BASE_ADDR                 0x43f90000
 #define UART2_BASE_ADDR                 0x43f94000
+#define MX25_FEC_BASE_ADDR              0x50038000
+#define MX25_INT_FEC    57
 #endif /* __MACH_MX25_H__ */
diff --git a/arch/arm/plat-nomadik/include/plat/i2c.h b/arch/arm/plat-nomadik/include/plat/i2c.h
new file mode 100644
index 000000000000..1621db67a53d
--- /dev/null
+++ b/arch/arm/plat-nomadik/include/plat/i2c.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+#ifndef __PLAT_I2C_H
+#define __PLAT_I2C_H
+enum i2c_freq_mode {
+        I2C_FREQ_MODE_STANDARD,         /* up to 100 Kb/s */
+        I2C_FREQ_MODE_FAST,             /* up to 400 Kb/s */
+        I2C_FREQ_MODE_FAST_PLUS,        /* up to 1 Mb/s */
+        I2C_FREQ_MODE_HIGH_SPEED        /* up to 3.4 Mb/s */
+};
+/**
+ * struct nmk_i2c_controller - client specific controller configuration
+ * @clk_freq:   clock frequency for the operation mode
+ * @slsu:       Slave data setup time in ns.
+ *              The needed setup time for three modes of operation
+ *              are 250ns, 100ns and 10ns respectively thus leading
+ *              to the values of 14, 6, 2 for a 48 MHz i2c clk
+ * @tft:        Tx FIFO Threshold in bytes
+ * @rft:        Rx FIFO Threshold in bytes
+ * @sm:         speed mode
+ */
+struct nmk_i2c_controller {
+        unsigned long   clk_freq;
+        unsigned short  slsu;
+        unsigned char   tft;
+        unsigned char   rft;
+        enum i2c_freq_mode      sm;
+};
+#endif  /* __PLAT_I2C_H */
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 89cafc937249..d9f8c844c385 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -36,10 +36,6 @@ static struct clk_functions *arch_clock;
 * Standard clock functions defined in include/linux/clk.h
 *-------------------------------------------------------------------------*/
-/* This functions is moved to arch/arm/common/clkdev.c. For OMAP4 since
- * clock framework is not up , it is defined here to avoid rework in
- * every driver. Also dummy prcm reset function is added */
 int clk_enable(struct clk *clk)
 {
        unsigned long flags;
@@ -305,7 +301,6 @@ void clk_enable_init_clocks(void)
                        clk_enable(clkp);
        }
 }
-EXPORT_SYMBOL(clk_enable_init_clocks);
 /*
 * Low level helpers
@@ -334,7 +329,16 @@ void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
                arch_clock->clk_init_cpufreq_table(table);
        spin_unlock_irqrestore(&clockfw_lock, flags);
 }
-EXPORT_SYMBOL(clk_init_cpufreq_table);
+void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&clockfw_lock, flags);
+        if (arch_clock->clk_exit_cpufreq_table)
+                arch_clock->clk_exit_cpufreq_table(table);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+}
 #endif
 /*-------------------------------------------------------------------------*/
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index f8ddbdd8b076..6d3d33360056 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -134,6 +134,7 @@ static int __init omap_cpu_init(struct cpufreq_policy *policy)
 static int omap_cpu_exit(struct cpufreq_policy *policy)
 {
+        clk_exit_cpufreq_table(&freq_table);
        clk_put(mpu_clk);
        return 0;
 }
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 04846811d0aa..d17620c50c28 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -192,6 +192,7 @@ struct gpio_bank {
        u32 saved_risingdetect;
 #endif
        u32 level_mask;
+        u32 toggle_mask;
        spinlock_t lock;
        struct gpio_chip chip;
        struct clk *dbck;
@@ -749,6 +750,44 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
 }
 #endif
+/*
+ * This only applies to chips that can't do both rising and falling edge
+ * detection at once.  For all other chips, this function is a noop.
+ */
+static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
+{
+        void __iomem *reg = bank->base;
+        u32 l = 0;
+        switch (bank->method) {
+#ifdef CONFIG_ARCH_OMAP1
+        case METHOD_MPUIO:
+                reg += OMAP_MPUIO_GPIO_INT_EDGE;
+                break;
+#endif
+#ifdef CONFIG_ARCH_OMAP15XX
+        case METHOD_GPIO_1510:
+                reg += OMAP1510_GPIO_INT_CONTROL;
+                break;
+#endif
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_INT_CONTROL;
+                break;
+#endif
+        default:
+                return;
+        }
+        l = __raw_readl(reg);
+        if ((l >> gpio) & 1)
+                l &= ~(1 << gpio);
+        else
+                l |= 1 << gpio;
+        __raw_writel(l, reg);
+}
 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
 {
        void __iomem *reg = bank->base;
@@ -759,6 +798,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
        case METHOD_MPUIO:
                reg += OMAP_MPUIO_GPIO_INT_EDGE;
                l = __raw_readl(reg);
+                if (trigger & IRQ_TYPE_EDGE_BOTH)
+                        bank->toggle_mask |= 1 << gpio;
                if (trigger & IRQ_TYPE_EDGE_RISING)
                        l |= 1 << gpio;
                else if (trigger & IRQ_TYPE_EDGE_FALLING)
@@ -771,6 +812,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
        case METHOD_GPIO_1510:
                reg += OMAP1510_GPIO_INT_CONTROL;
                l = __raw_readl(reg);
+                if (trigger & IRQ_TYPE_EDGE_BOTH)
+                        bank->toggle_mask |= 1 << gpio;
                if (trigger & IRQ_TYPE_EDGE_RISING)
                        l |= 1 << gpio;
                else if (trigger & IRQ_TYPE_EDGE_FALLING)
@@ -803,6 +846,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
        case METHOD_GPIO_7XX:
                reg += OMAP7XX_GPIO_INT_CONTROL;
                l = __raw_readl(reg);
+                if (trigger & IRQ_TYPE_EDGE_BOTH)
+                        bank->toggle_mask |= 1 << gpio;
                if (trigger & IRQ_TYPE_EDGE_RISING)
                        l |= 1 << gpio;
                else if (trigger & IRQ_TYPE_EDGE_FALLING)
@@ -1072,7 +1117,7 @@ static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int ena
 */
 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
 {
-        unsigned long flags;
+        unsigned long uninitialized_var(flags);
        switch (bank->method) {
 #ifdef CONFIG_ARCH_OMAP16XX
@@ -1217,7 +1262,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
        void __iomem *isr_reg = NULL;
        u32 isr;
-        unsigned int gpio_irq;
+        unsigned int gpio_irq, gpio_index;
        struct gpio_bank *bank;
        u32 retrigger = 0;
        int unmasked = 0;
@@ -1284,9 +1329,23 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                gpio_irq = bank->virtual_irq_start;
                for (; isr != 0; isr >>= 1, gpio_irq++) {
+                        gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
                        if (!(isr & 1))
                                continue;
+#ifdef CONFIG_ARCH_OMAP1
+                        /*
+                         * Some chips can't respond to both rising and falling
+                         * at the same time.  If this irq was requested with
+                         * both flags, we need to flip the ICR data for the IRQ
+                         * to respond to the IRQ for the opposite direction.
+                         * This will be indicated in the bank toggle_mask.
+                         */
+                        if (bank->toggle_mask & (1 << gpio_index))
+                                _toggle_gpio_edge_triggering(bank, gpio_index);
+#endif
                        generic_handle_irq(gpio_irq);
                }
        }
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 376ce18216ff..5cd622039da0 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -99,7 +99,6 @@ struct fb_info;
 struct omap_backlight_config {
        int default_intensity;
        int (*set_power)(struct device *dev, int state);
-        int (*check_fb)(struct fb_info *fb);
 };
 struct omap_fbmem_config {
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 309b6d1dccdb..94fe2a0ce40a 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -119,6 +119,7 @@ struct clk_functions {
        void            (*clk_disable_unused)(struct clk *clk);
 #ifdef CONFIG_CPU_FREQ
        void            (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
+        void            (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
 #endif
 };
@@ -135,6 +136,7 @@ extern unsigned long followparent_recalc(struct clk *clk);
 extern void clk_enable_init_clocks(void);
 #ifdef CONFIG_CPU_FREQ
 extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
+extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 #endif
 extern const struct clkops clkops_null;
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index 2ae884378638..a745d62fad0d 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -147,7 +147,7 @@
 #define OMAP343X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
 #define OMAP343X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
 #define OMAP343X_CONTROL_DEBOBS(i)      (OMAP2_CONTROL_GENERAL + 0x01B0 \
-                                        + ((i) >> 1) * 4 + (!(i) & 1) * 2)
+                                        + ((i) >> 1) * 4 + (!((i) & 1)) * 2)
 #define OMAP343X_CONTROL_PROG_IO0       (OMAP2_CONTROL_GENERAL + 0x01D4)
 #define OMAP343X_CONTROL_PROG_IO1       (OMAP2_CONTROL_GENERAL + 0x01D8)
 #define OMAP343X_CONTROL_DSS_DPLL_SPREADING     (OMAP2_CONTROL_GENERAL + 0x01E0)
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index 7e5319f907d1..a3e7b471bcba 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -122,16 +122,21 @@
 #define OMAP243X_SMS_VIRT       (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP243X_SMS_SIZE       SZ_1M
-/* DSP */
+/* 2420 IVA */
-#define DSP_MEM_24XX_PHYS       OMAP2420_DSP_MEM_BASE   /* 0x58000000 */
+#define DSP_MEM_2420_PHYS       OMAP2420_DSP_MEM_BASE
-#define DSP_MEM_24XX_VIRT       0xe0000000
+                                                /* 0x58000000 --> 0xfc100000 */
-#define DSP_MEM_24XX_SIZE       0x28000
+#define DSP_MEM_2420_VIRT       0xfc100000
-#define DSP_IPI_24XX_PHYS       OMAP2420_DSP_IPI_BASE   /* 0x59000000 */
+#define DSP_MEM_2420_SIZE       0x28000
-#define DSP_IPI_24XX_VIRT       0xe1000000
+#define DSP_IPI_2420_PHYS       OMAP2420_DSP_IPI_BASE
-#define DSP_IPI_24XX_SIZE       SZ_4K
+                                                /* 0x59000000 --> 0xfc128000 */
-#define DSP_MMU_24XX_PHYS       OMAP2420_DSP_MMU_BASE   /* 0x5a000000 */
+#define DSP_IPI_2420_VIRT       0xfc128000
-#define DSP_MMU_24XX_VIRT       0xe2000000
+#define DSP_IPI_2420_SIZE       SZ_4K
-#define DSP_MMU_24XX_SIZE       SZ_4K
+#define DSP_MMU_2420_PHYS       OMAP2420_DSP_MMU_BASE
+                                                /* 0x5a000000 --> 0xfc129000 */
+#define DSP_MMU_2420_VIRT       0xfc129000
+#define DSP_MMU_2420_SIZE       SZ_4K
+/* 2430 IVA2.1 - currently unmapped */
 /*
 * ----------------------------------------------------------------------------
@@ -182,16 +187,7 @@
 #define OMAP343X_SDRC_VIRT      (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
 #define OMAP343X_SDRC_SIZE      SZ_1M
-/* DSP */
+/* 3430 IVA - currently unmapped */
-#define DSP_MEM_34XX_PHYS       OMAP34XX_DSP_MEM_BASE   /* 0x58000000 */
-#define DSP_MEM_34XX_VIRT       0xe0000000
-#define DSP_MEM_34XX_SIZE       0x28000
-#define DSP_IPI_34XX_PHYS       OMAP34XX_DSP_IPI_BASE   /* 0x59000000 */
-#define DSP_IPI_34XX_VIRT       0xe1000000
-#define DSP_IPI_34XX_SIZE       SZ_4K
-#define DSP_MMU_34XX_PHYS       OMAP34XX_DSP_MMU_BASE   /* 0x5a000000 */
-#define DSP_MMU_34XX_VIRT       0xe2000000
-#define DSP_MMU_34XX_SIZE       SZ_4K
 /*
 * ----------------------------------------------------------------------------
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h
index 8f069cc80350..692c90e89ac3 100644
--- a/arch/arm/plat-omap/include/plat/mux.h
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -183,6 +183,14 @@ enum omap7xx_index {
        /* I2C */
        I2C_7XX_SCL,
        I2C_7XX_SDA,
+        /* SPI */
+        SPI_7XX_1,
+        SPI_7XX_2,
+        SPI_7XX_3,
+        SPI_7XX_4,
+        SPI_7XX_5,
+        SPI_7XX_6,
 };
 enum omap1xxx_index {
diff --git a/arch/arm/plat-omap/include/plat/omap7xx.h b/arch/arm/plat-omap/include/plat/omap7xx.h
index 53f52414b0e9..48e4757e1e30 100644
--- a/arch/arm/plat-omap/include/plat/omap7xx.h
+++ b/arch/arm/plat-omap/include/plat/omap7xx.h
@@ -46,6 +46,9 @@
 #define OMAP7XX_DSPREG_SIZE     SZ_128K
 #define OMAP7XX_DSPREG_START    0xE1000000
+#define OMAP7XX_SPI1_BASE       0xfffc0800
+#define OMAP7XX_SPI2_BASE       0xfffc1000
 /*
 * ----------------------------------------------------------------------------
 * OMAP7XX specific configuration registers
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index 11f5d7961c73..0cfd54f519c4 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -66,12 +66,12 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
                        return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT);
        }
        if (cpu_is_omap2420()) {
-                if (BETWEEN(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_SIZE))
+                if (BETWEEN(p, DSP_MEM_2420_PHYS, DSP_MEM_2420_SIZE))
-                        return XLATE(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_VIRT);
+                        return XLATE(p, DSP_MEM_2420_PHYS, DSP_MEM_2420_VIRT);
-                if (BETWEEN(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE))
+                if (BETWEEN(p, DSP_IPI_2420_PHYS, DSP_IPI_2420_SIZE))
-                        return XLATE(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE);
+                        return XLATE(p, DSP_IPI_2420_PHYS, DSP_IPI_2420_SIZE);
-                if (BETWEEN(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_SIZE))
+                if (BETWEEN(p, DSP_MMU_2420_PHYS, DSP_MMU_2420_SIZE))
-                        return XLATE(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_VIRT);
+                        return XLATE(p, DSP_MMU_2420_PHYS, DSP_MMU_2420_VIRT);
        }
        if (cpu_is_omap2430()) {
                if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE))
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index c0ff1e39d893..463d6386aff2 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -827,7 +827,7 @@ EXPORT_SYMBOL_GPL(iommu_get);
 **/
 void iommu_put(struct iommu *obj)
 {
-        if (!obj && IS_ERR(obj))
+        if (!obj || IS_ERR(obj))
                return;
        mutex_lock(&obj->iommu_lock);
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 2cc1cc328bac..f75767278fc3 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -436,7 +436,7 @@ int omap_mcbsp_request(unsigned int id)
                        dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
                                        "for McBSP%d\n", mcbsp->tx_irq,
                                        mcbsp->id);
-                        return err;
+                        goto error;
                }
                init_completion(&mcbsp->rx_irq_completion);
@@ -446,12 +446,26 @@ int omap_mcbsp_request(unsigned int id)
                        dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
                                        "for McBSP%d\n", mcbsp->rx_irq,
                                        mcbsp->id);
-                        free_irq(mcbsp->tx_irq, (void *)mcbsp);
+                        goto tx_irq;
-                        return err;
                }
        }
        return 0;
+tx_irq:
+        free_irq(mcbsp->tx_irq, (void *)mcbsp);
+error:
+        if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
+                        mcbsp->pdata->ops->free(id);
+        /* Do procedure specific to omap34xx arch, if applicable */
+        omap34xx_mcbsp_free(mcbsp);
+        clk_disable(mcbsp->fclk);
+        clk_disable(mcbsp->iclk);
+        mcbsp->free = 1;
+        return err;
 }
 EXPORT_SYMBOL(omap_mcbsp_request);
diff --git a/arch/arm/plat-pxa/pwm.c b/arch/arm/plat-pxa/pwm.c
index a9eabdcfa163..51dc5c8106c0 100644
--- a/arch/arm/plat-pxa/pwm.c
+++ b/arch/arm/plat-pxa/pwm.c
@@ -204,14 +204,14 @@ static int __devinit pwm_probe(struct platform_device *pdev)
                goto err_free_clk;
        }
-        r = request_mem_region(r->start, r->end - r->start + 1, pdev->name);
+        r = request_mem_region(r->start, resource_size(r), pdev->name);
        if (r == NULL) {
                dev_err(&pdev->dev, "failed to request memory resource\n");
                ret = -EBUSY;
                goto err_free_clk;
        }
-        pwm->mmio_base = ioremap(r->start, r->end - r->start + 1);
+        pwm->mmio_base = ioremap(r->start, resource_size(r));
        if (pwm->mmio_base == NULL) {
                dev_err(&pdev->dev, "failed to ioremap() registers\n");
                ret = -ENODEV;
@@ -241,7 +241,7 @@ static int __devinit pwm_probe(struct platform_device *pdev)
        return 0;
 err_free_mem:
-        release_mem_region(r->start, r->end - r->start + 1);
+        release_mem_region(r->start, resource_size(r));
 err_free_clk:
        clk_put(pwm->clk);
 err_free:
@@ -271,7 +271,7 @@ static int __devexit pwm_remove(struct platform_device *pdev)
        iounmap(pwm->mmio_base);
        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        release_mem_region(r->start, r->end - r->start + 1);
+        release_mem_region(r->start, resource_size(r));
        clk_put(pwm->clk);
        kfree(pwm);
diff --git a/arch/arm/plat-s3c/dev-nand.c b/arch/arm/plat-s3c/dev-nand.c
index 84808ccda70e..a52fb6cf618f 100644
--- a/arch/arm/plat-s3c/dev-nand.c
+++ b/arch/arm/plat-s3c/dev-nand.c
@@ -58,8 +58,8 @@ static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
                        return -ENOMEM;
        }
        
-        size = sizeof(int) * set->nr_chips;
+        if (set->nr_map && set->nr_chips) {
-        if (size) {
+                size = sizeof(int) * set->nr_chips;
                ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
                set->nr_map = ptr;
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 6ffa21eb1b91..ffd56deb9e81 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -46,6 +46,7 @@ static struct clk clk_ext_xtal_mux = {
 #define clk_fin_epll clk_ext_xtal_mux
 #define clk_fout_mpll   clk_mpll
+#define clk_fout_epll   clk_epll
 struct clk_sources {
        unsigned int    nr_sources;
@@ -88,11 +89,6 @@ static struct clksrc_clk clk_mout_apll = {
        .sources        = &clk_src_apll,
 };
-static struct clk clk_fout_epll = {
-        .name           = "fout_epll",
-        .id             = -1,
-};
 static struct clk *clk_src_epll_list[] = {
        [0] = &clk_fin_epll,
        [1] = &clk_fout_epll,
@@ -715,7 +711,6 @@ static struct clk *clks[] __initdata = {
        &clk_iis_cd1,
        &clk_pcm_cd,
        &clk_mout_epll.clk,
-        &clk_fout_epll,
        &clk_mout_mpll.clk,
        &clk_dout_mpll,
        &clk_mmc0.clk,
@@ -760,7 +755,4 @@ void __init s3c6400_register_clocks(unsigned armclk_divlimit)
                               clkp->name, ret);
                }
        }
-        clk_mpll.parent = &clk_mout_mpll.clk;
-        clk_epll.parent = &clk_mout_epll.clk;
 }