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-rw-r--r--arch/arm/common/dmabounce.c2
-rw-r--r--arch/arm/common/gic.c2
-rw-r--r--arch/arm/common/sharpsl_param.c2
-rw-r--r--arch/arm/common/sharpsl_pm.c10
-rw-r--r--arch/arm/kernel/sys_arm.c2
-rw-r--r--arch/arm/lib/bitops.h2
-rw-r--r--arch/arm/mach-at91/board-carmeva.c8
-rw-r--r--arch/arm/mach-h720x/cpu-h7202.c4
-rw-r--r--arch/arm/mach-imx/cpufreq.c2
-rw-r--r--arch/arm/mach-imx/dma.c8
-rw-r--r--arch/arm/mach-iop13xx/pci.c2
-rw-r--r--arch/arm/mach-ixp2000/enp2611.c2
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x00.c4
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x01.c6
-rw-r--r--arch/arm/mach-ixp2000/pci.c2
-rw-r--r--arch/arm/mach-ixp23xx/core.c2
-rw-r--r--arch/arm/mach-ixp4xx/gtwx5715-setup.c2
-rw-r--r--arch/arm/mach-lh7a40x/lcd-panel.h6
-rw-r--r--arch/arm/mach-ns9xxx/time.c2
-rw-r--r--arch/arm/mach-omap1/board-osk.c2
-rw-r--r--arch/arm/mach-omap1/board-palmte.c2
-rw-r--r--arch/arm/mach-omap1/pm.c2
-rw-r--r--arch/arm/mach-omap2/clock.c2
-rw-r--r--arch/arm/mach-omap2/clock.h4
-rw-r--r--arch/arm/mach-pxa/corgi_lcd.c10
-rw-r--r--arch/arm/mach-pxa/corgi_ssp.c2
-rw-r--r--arch/arm/mach-realview/localtimer.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-osiris.c2
-rw-r--r--arch/arm/mach-sa1100/time.c2
-rw-r--r--arch/arm/mm/alignment.c2
-rw-r--r--arch/arm/mm/ioremap.c2
-rw-r--r--arch/arm/mm/mmu.c2
-rw-r--r--arch/arm/plat-iop/pci.c2
-rw-r--r--arch/arm/plat-omap/common.c2
-rw-r--r--arch/arm/plat-omap/dma.c2
-rw-r--r--arch/arm/plat-omap/sram.c6
-rw-r--r--arch/arm/plat-omap/usb.c2
-rw-r--r--arch/arm/plat-s3c24xx/dma.c2
-rw-r--r--arch/arm/plat-s3c24xx/pm.c2
39 files changed, 62 insertions, 62 deletions
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index 6fbe7722aa44..b36b1e8a105d 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -6,7 +6,7 @@
6 * copy data to/from buffers located outside the DMA region. This 6 * copy data to/from buffers located outside the DMA region. This
7 * only works for systems in which DMA memory is at the bottom of 7 * only works for systems in which DMA memory is at the bottom of
8 * RAM, the remainder of memory is at the top and the DMA memory 8 * RAM, the remainder of memory is at the top and the DMA memory
9 * can be marked as ZONE_DMA. Anything beyond that such as discontigous 9 * can be marked as ZONE_DMA. Anything beyond that such as discontiguous
10 * DMA windows will require custom implementations that reserve memory 10 * DMA windows will require custom implementations that reserve memory
11 * areas at early bootup. 11 * areas at early bootup.
12 * 12 *
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 2ae0bd1c907d..0c89bd35e06f 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -72,7 +72,7 @@ static inline unsigned int gic_irq(unsigned int irq)
72 * unmask it, in the same way we need to unmask an interrupt when 72 * unmask it, in the same way we need to unmask an interrupt when
73 * we first enable it. 73 * we first enable it.
74 * 74 *
75 * The GIC has a seperate notion of "end of interrupt" to re-enable 75 * The GIC has a separate notion of "end of interrupt" to re-enable
76 * an interrupt after handling, in order to support hardware 76 * an interrupt after handling, in order to support hardware
77 * prioritisation. 77 * prioritisation.
78 * 78 *
diff --git a/arch/arm/common/sharpsl_param.c b/arch/arm/common/sharpsl_param.c
index c94864c5b1af..aad4d94ba8f5 100644
--- a/arch/arm/common/sharpsl_param.c
+++ b/arch/arm/common/sharpsl_param.c
@@ -20,7 +20,7 @@
20 * typically including LCD parameters are loaded by the bootloader at the 20 * typically including LCD parameters are loaded by the bootloader at the
21 * address PARAM_BASE. As the kernel will overwrite them, we need to store 21 * address PARAM_BASE. As the kernel will overwrite them, we need to store
22 * them early in the boot process, then pass them to the appropriate drivers. 22 * them early in the boot process, then pass them to the appropriate drivers.
23 * Not all devices use all paramaters but the format is common to all. 23 * Not all devices use all parameters but the format is common to all.
24 */ 24 */
25#ifdef CONFIG_ARCH_SA1100 25#ifdef CONFIG_ARCH_SA1100
26#define PARAM_BASE 0xe8ffc000 26#define PARAM_BASE 0xe8ffc000
diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c
index c8e78d96e592..3bf3a927ae22 100644
--- a/arch/arm/common/sharpsl_pm.c
+++ b/arch/arm/common/sharpsl_pm.c
@@ -291,7 +291,7 @@ static void sharpsl_chrg_full_timer(unsigned long data)
291} 291}
292 292
293/* Charging Finished Interrupt (Not present on Corgi) */ 293/* Charging Finished Interrupt (Not present on Corgi) */
294/* Can trigger at the same time as an AC staus change so 294/* Can trigger at the same time as an AC status change so
295 delay until after that has been processed */ 295 delay until after that has been processed */
296irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id) 296irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id)
297{ 297{
@@ -635,7 +635,7 @@ static int sharpsl_fatal_check(void)
635 635
636static int sharpsl_off_charge_error(void) 636static int sharpsl_off_charge_error(void)
637{ 637{
638 dev_err(sharpsl_pm.dev, "Offline Charger: Error occured.\n"); 638 dev_err(sharpsl_pm.dev, "Offline Charger: Error occurred.\n");
639 sharpsl_pm.machinfo->charge(0); 639 sharpsl_pm.machinfo->charge(0);
640 sharpsl_pm_led(SHARPSL_LED_ERROR); 640 sharpsl_pm_led(SHARPSL_LED_ERROR);
641 sharpsl_pm.charge_mode = CHRG_ERROR; 641 sharpsl_pm.charge_mode = CHRG_ERROR;
@@ -691,14 +691,14 @@ static int sharpsl_off_charge_battery(void)
691 691
692 time = RCNR; 692 time = RCNR;
693 while(1) { 693 while(1) {
694 /* Check if any wakeup event had occured */ 694 /* Check if any wakeup event had occurred */
695 if (sharpsl_pm.machinfo->charger_wakeup() != 0) 695 if (sharpsl_pm.machinfo->charger_wakeup() != 0)
696 return 0; 696 return 0;
697 /* Check for timeout */ 697 /* Check for timeout */
698 if ((RCNR - time) > SHARPSL_WAIT_CO_TIME) 698 if ((RCNR - time) > SHARPSL_WAIT_CO_TIME)
699 return 1; 699 return 1;
700 if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) { 700 if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) {
701 dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occured. Retrying to check\n"); 701 dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occurred. Retrying to check\n");
702 sharpsl_pm.full_count++; 702 sharpsl_pm.full_count++;
703 sharpsl_pm.machinfo->charge(0); 703 sharpsl_pm.machinfo->charge(0);
704 mdelay(SHARPSL_CHARGE_WAIT_TIME); 704 mdelay(SHARPSL_CHARGE_WAIT_TIME);
@@ -714,7 +714,7 @@ static int sharpsl_off_charge_battery(void)
714 714
715 time = RCNR; 715 time = RCNR;
716 while(1) { 716 while(1) {
717 /* Check if any wakeup event had occured */ 717 /* Check if any wakeup event had occurred */
718 if (sharpsl_pm.machinfo->charger_wakeup() != 0) 718 if (sharpsl_pm.machinfo->charger_wakeup() != 0)
719 return 0; 719 return 0;
720 /* Check for timeout */ 720 /* Check for timeout */
diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index 3d4fcbc16276..1ca2d5174fcb 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -320,7 +320,7 @@ int kernel_execve(const char *filename, char *const argv[], char *const envp[])
320EXPORT_SYMBOL(kernel_execve); 320EXPORT_SYMBOL(kernel_execve);
321 321
322/* 322/*
323 * Since loff_t is a 64 bit type we avoid a lot of ABI hastle 323 * Since loff_t is a 64 bit type we avoid a lot of ABI hassle
324 * with a different argument ordering. 324 * with a different argument ordering.
325 */ 325 */
326asmlinkage long sys_arm_fadvise64_64(int fd, int advice, 326asmlinkage long sys_arm_fadvise64_64(int fd, int advice,
diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h
index 542251021744..2e787d40d599 100644
--- a/arch/arm/lib/bitops.h
+++ b/arch/arm/lib/bitops.h
@@ -47,7 +47,7 @@
47 * @store: store instruction 47 * @store: store instruction
48 * 48 *
49 * Note: we can trivially conditionalise the store instruction 49 * Note: we can trivially conditionalise the store instruction
50 * to avoid dirting the data cache. 50 * to avoid dirtying the data cache.
51 */ 51 */
52 .macro testop, instr, store 52 .macro testop, instr, store
53 add r1, r1, r0, lsr #3 53 add r1, r1, r0, lsr #3
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index b4518619063a..76ec856cd4f9 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -79,7 +79,7 @@ static struct at91_udc_data __initdata carmeva_udc_data = {
79 .pullup_pin = AT91_PIN_PD9, 79 .pullup_pin = AT91_PIN_PD9,
80}; 80};
81 81
82/* FIXME: user dependend */ 82/* FIXME: user dependant */
83// static struct at91_cf_data __initdata carmeva_cf_data = { 83// static struct at91_cf_data __initdata carmeva_cf_data = {
84// .det_pin = AT91_PIN_PB0, 84// .det_pin = AT91_PIN_PB0,
85// .rst_pin = AT91_PIN_PC5, 85// .rst_pin = AT91_PIN_PC5,
@@ -100,17 +100,17 @@ static struct spi_board_info carmeva_spi_devices[] = {
100 .chip_select = 0, 100 .chip_select = 0,
101 .max_speed_hz = 10 * 1000 * 1000, 101 .max_speed_hz = 10 * 1000 * 1000,
102 }, 102 },
103 { /* User accessable spi - cs1 (250KHz) */ 103 { /* User accessible spi - cs1 (250KHz) */
104 .modalias = "spi-cs1", 104 .modalias = "spi-cs1",
105 .chip_select = 1, 105 .chip_select = 1,
106 .max_speed_hz = 250 * 1000, 106 .max_speed_hz = 250 * 1000,
107 }, 107 },
108 { /* User accessable spi - cs2 (1MHz) */ 108 { /* User accessible spi - cs2 (1MHz) */
109 .modalias = "spi-cs2", 109 .modalias = "spi-cs2",
110 .chip_select = 2, 110 .chip_select = 2,
111 .max_speed_hz = 1 * 1000 * 1000, 111 .max_speed_hz = 1 * 1000 * 1000,
112 }, 112 },
113 { /* User accessable spi - cs3 (10MHz) */ 113 { /* User accessible spi - cs3 (10MHz) */
114 .modalias = "spi-cs3", 114 .modalias = "spi-cs3",
115 .chip_select = 3, 115 .chip_select = 3,
116 .max_speed_hz = 10 * 1000 * 1000, 116 .max_speed_hz = 10 * 1000 * 1000,
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
index 82e420d6fd19..0a1a25fb8ba8 100644
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ b/arch/arm/mach-h720x/cpu-h7202.c
@@ -143,7 +143,7 @@ h7202_timer_interrupt(int irq, void *dev_id)
143} 143}
144 144
145/* 145/*
146 * mask multiplexed timer irq's 146 * mask multiplexed timer IRQs
147 */ 147 */
148static void inline mask_timerx_irq (u32 irq) 148static void inline mask_timerx_irq (u32 irq)
149{ 149{
@@ -153,7 +153,7 @@ static void inline mask_timerx_irq (u32 irq)
153} 153}
154 154
155/* 155/*
156 * unmask multiplexed timer irq's 156 * unmask multiplexed timer IRQs
157 */ 157 */
158static void inline unmask_timerx_irq (u32 irq) 158static void inline unmask_timerx_irq (u32 irq)
159{ 159{
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
index 7e70e0b0b989..467d899fbe75 100644
--- a/arch/arm/mach-imx/cpufreq.c
+++ b/arch/arm/mach-imx/cpufreq.c
@@ -245,7 +245,7 @@ static int imx_set_target(struct cpufreq_policy *policy,
245 if(mpctl0) { 245 if(mpctl0) {
246 CSCR |= CSCR_MPLL_RESTART; 246 CSCR |= CSCR_MPLL_RESTART;
247 247
248 /* Wait until MPLL is stablized */ 248 /* Wait until MPLL is stabilized */
249 while( CSCR & CSCR_MPLL_RESTART ); 249 while( CSCR & CSCR_MPLL_RESTART );
250 250
251 imx_set_async_mode(); 251 imx_set_async_mode();
diff --git a/arch/arm/mach-imx/dma.c b/arch/arm/mach-imx/dma.c
index 6d50d85a618c..bc6fb02d213b 100644
--- a/arch/arm/mach-imx/dma.c
+++ b/arch/arm/mach-imx/dma.c
@@ -131,7 +131,7 @@ imx_dma_setup_sg_base(imx_dmach_t dma_ch,
131 * The function setups DMA channel source and destination addresses for transfer 131 * The function setups DMA channel source and destination addresses for transfer
132 * specified by provided parameters. The scatter-gather emulation is disabled, 132 * specified by provided parameters. The scatter-gather emulation is disabled,
133 * because linear data block 133 * because linear data block
134 * form the physical address range is transfered. 134 * form the physical address range is transferred.
135 * Return value: if incorrect parameters are provided -%EINVAL. 135 * Return value: if incorrect parameters are provided -%EINVAL.
136 * Zero indicates success. 136 * Zero indicates success.
137 */ 137 */
@@ -192,7 +192,7 @@ imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
192 * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory 192 * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
193 * or %DMA_MODE_WRITE from memory to the device 193 * or %DMA_MODE_WRITE from memory to the device
194 * 194 *
195 * The function setups DMA channel state and registers to be ready for transfer 195 * The function sets up DMA channel state and registers to be ready for transfer
196 * specified by provided parameters. The scatter-gather emulation is set up 196 * specified by provided parameters. The scatter-gather emulation is set up
197 * according to the parameters. 197 * according to the parameters.
198 * 198 *
@@ -212,7 +212,7 @@ imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
212 * 212 *
213 * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x 213 * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
214 * 214 *
215 * Be carefull there and do not mistakenly mix source and target device 215 * Be careful here and do not mistakenly mix source and target device
216 * port sizes constants, they are really different: 216 * port sizes constants, they are really different:
217 * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32, 217 * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
218 * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32 218 * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
@@ -495,7 +495,7 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id)
495 /* 495 /*
496 * The cleaning of @sg field would be questionable 496 * The cleaning of @sg field would be questionable
497 * there, because its value can help to compute 497 * there, because its value can help to compute
498 * remaining/transfered bytes count in the handler 498 * remaining/transferred bytes count in the handler
499 */ 499 */
500 /*imx_dma_channels[i].sg = NULL;*/ 500 /*imx_dma_channels[i].sg = NULL;*/
501 501
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 69e8953832fd..306f82ee57f0 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -989,7 +989,7 @@ void __init iop13xx_pci_init(void)
989 "imprecise external abort"); 989 "imprecise external abort");
990} 990}
991 991
992/* intialize the pci memory space. handle any combination of 992/* initialize the pci memory space. handle any combination of
993 * atue and atux enabled/disabled 993 * atue and atux enabled/disabled
994 */ 994 */
995int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) 995int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index 500e997ba7a4..9c49435d42c3 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -198,7 +198,7 @@ subsys_initcall(enp2611_pci_init);
198 198
199 199
200/************************************************************************* 200/*************************************************************************
201 * ENP-2611 Machine Intialization 201 * ENP-2611 Machine Initialization
202 *************************************************************************/ 202 *************************************************************************/
203static struct flash_platform_data enp2611_flash_platform_data = { 203static struct flash_platform_data enp2611_flash_platform_data = {
204 .map_name = "cfi_probe", 204 .map_name = "cfi_probe",
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index 52b368b34346..011065b967b4 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -195,7 +195,7 @@ void __init ixdp2x00_map_io(void)
195 * instances of the kernel. So far so good. Peers on the PCI bus running 195 * instances of the kernel. So far so good. Peers on the PCI bus running
196 * Linux is a common design in telecom systems. The problem is that instead 196 * Linux is a common design in telecom systems. The problem is that instead
197 * of all the devices being controlled by a single host, different 197 * of all the devices being controlled by a single host, different
198 * devices are controlles by different NPUs on the same bus, leading to 198 * devices are controlled by different NPUs on the same bus, leading to
199 * multiple hosts on the bus. The exact bus layout looks like: 199 * multiple hosts on the bus. The exact bus layout looks like:
200 * 200 *
201 * Bus 0 201 * Bus 0
@@ -211,7 +211,7 @@ void __init ixdp2x00_map_io(void)
211 * | | | | | 211 * | | | | |
212 * ... Dev PMC Media Eth0 Eth1 ... 212 * ... Dev PMC Media Eth0 Eth1 ...
213 * 213 *
214 * The master controlls all but Eth1, which is controlled by the 214 * The master controls all but Eth1, which is controlled by the
215 * slave. What this means is that the both the master and the slave 215 * slave. What this means is that the both the master and the slave
216 * have to scan the bus, but only one of them can enumerate the bus. 216 * have to scan the bus, but only one of them can enumerate the bus.
217 * In addition, after the bus is scanned, each kernel must remove 217 * In addition, after the bus is scanned, each kernel must remove
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 3084a5fa751c..d3d730d2fc2b 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -276,7 +276,7 @@ static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
276 /* Device is located after first MB bridge */ 276 /* Device is located after first MB bridge */
277 case 0x0008: 277 case 0x0008:
278 if (tmp_bus == dev->bus) { 278 if (tmp_bus == dev->bus) {
279 /* Device is located directy after first MB bridge */ 279 /* Device is located directly after first MB bridge */
280 switch (devpin) { 280 switch (devpin) {
281 case DEVPIN(1, 1): /* Onboard 82546 ch 0 */ 281 case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
282 if (machine_is_ixdp2401()) 282 if (machine_is_ixdp2401())
@@ -299,7 +299,7 @@ static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
299 break; 299 break;
300 case 0x0010: 300 case 0x0010:
301 if (tmp_bus == dev->bus) { 301 if (tmp_bus == dev->bus) {
302 /* Device is located directy after second MB bridge */ 302 /* Device is located directly after second MB bridge */
303 /* Secondary bus of second bridge */ 303 /* Secondary bus of second bridge */
304 switch (devpin) { 304 switch (devpin) {
305 case DEVPIN(0, 1): /* DB#0 */ 305 case DEVPIN(0, 1): /* DB#0 */
@@ -348,7 +348,7 @@ int __init ixdp2x01_pci_init(void)
348subsys_initcall(ixdp2x01_pci_init); 348subsys_initcall(ixdp2x01_pci_init);
349 349
350/************************************************************************* 350/*************************************************************************
351 * IXDP2x01 Machine Intialization 351 * IXDP2x01 Machine Initialization
352 *************************************************************************/ 352 *************************************************************************/
353static struct flash_platform_data ixdp2x01_flash_platform_data = { 353static struct flash_platform_data ixdp2x01_flash_platform_data = {
354 .map_name = "cfi_probe", 354 .map_name = "cfi_probe",
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index 5a09a90c08fb..03f4cf7f9dec 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -102,7 +102,7 @@ int ixp2000_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where,
102} 102}
103 103
104/* 104/*
105 * We don't do error checks by callling clear_master_aborts() b/c the 105 * We don't do error checks by calling clear_master_aborts() b/c the
106 * assumption is that the caller did a read first to make sure a device 106 * assumption is that the caller did a read first to make sure a device
107 * exists. 107 * exists.
108 */ 108 */
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index b644bbab7d0a..16356ffc86ae 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -389,7 +389,7 @@ struct sys_timer ixp23xx_timer = {
389 389
390 390
391/************************************************************************* 391/*************************************************************************
392 * IXP23xx Platform Initializaion 392 * IXP23xx Platform Initialization
393 *************************************************************************/ 393 *************************************************************************/
394static struct resource ixp23xx_uart_resources[] = { 394static struct resource ixp23xx_uart_resources[] = {
395 { 395 {
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index 30f1300e0e21..dc6725bda3c4 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/mach-ixp4xx/gtwx5715-setup.c 2 * arch/arm/mach-ixp4xx/gtwx5715-setup.c
3 * 3 *
4 * Gemtek GTWX5715 (Linksys WRV54G) board settup 4 * Gemtek GTWX5715 (Linksys WRV54G) board setup
5 * 5 *
6 * Copyright (C) 2004 George T. Joseph 6 * Copyright (C) 2004 George T. Joseph
7 * Derived from Coyote 7 * Derived from Coyote
diff --git a/arch/arm/mach-lh7a40x/lcd-panel.h b/arch/arm/mach-lh7a40x/lcd-panel.h
index 4fb2efc4950f..df6e38ed425b 100644
--- a/arch/arm/mach-lh7a40x/lcd-panel.h
+++ b/arch/arm/mach-lh7a40x/lcd-panel.h
@@ -126,7 +126,7 @@ static struct clcd_panel_extra lcd_panel_extra = {
126 126
127 */ 127 */
128 128
129/* The full horozontal cycle (Th) is clock/360/400/450. */ 129/* The full horizontal cycle (Th) is clock/360/400/450. */
130/* The full vertical cycle (Tv) is line/251/262/280. */ 130/* The full vertical cycle (Tv) is line/251/262/280. */
131 131
132#define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */ 132#define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */
@@ -162,7 +162,7 @@ static struct clcd_panel lcd_panel = {
162 /* Logic Product Development LCD 6.4" VGA -10 */ 162 /* Logic Product Development LCD 6.4" VGA -10 */
163 /* Sharp PN LQ64D343 */ 163 /* Sharp PN LQ64D343 */
164 164
165/* The full horozontal cycle (Th) is clock/750/800/900. */ 165/* The full horizontal cycle (Th) is clock/750/800/900. */
166/* The full vertical cycle (Tv) is line/515/525/560. */ 166/* The full vertical cycle (Tv) is line/515/525/560. */
167 167
168#define PIX_CLOCK_TARGET (28330000) 168#define PIX_CLOCK_TARGET (28330000)
@@ -243,7 +243,7 @@ static struct clcd_panel lcd_panel = {
243 * (fdisk, e2fsck). And, at that speed the display may have a visible 243 * (fdisk, e2fsck). And, at that speed the display may have a visible
244 * flicker. */ 244 * flicker. */
245 245
246/* The full horozontal cycle (Th) is clock/832/1056/1395. */ 246/* The full horizontal cycle (Th) is clock/832/1056/1395. */
247 247
248#define PIX_CLOCK_TARGET (20000000) 248#define PIX_CLOCK_TARGET (20000000)
249#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) 249#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
diff --git a/arch/arm/mach-ns9xxx/time.c b/arch/arm/mach-ns9xxx/time.c
index dd257084441c..b97d0c54a388 100644
--- a/arch/arm/mach-ns9xxx/time.c
+++ b/arch/arm/mach-ns9xxx/time.c
@@ -35,7 +35,7 @@ static unsigned long ns9xxx_timer_gettimeoffset(void)
35{ 35{
36 /* return the microseconds which have passed since the last interrupt 36 /* return the microseconds which have passed since the last interrupt
37 * was _serviced_. That is, if an interrupt is pending or the counter 37 * was _serviced_. That is, if an interrupt is pending or the counter
38 * reloads, return one periode more. */ 38 * reloads, return one period more. */
39 39
40 u32 counter1 = SYS_TR(0); 40 u32 counter1 = SYS_TR(0);
41 int pending = SYS_ISR & (1 << IRQ_TIMER0); 41 int pending = SYS_ISR & (1 << IRQ_TIMER0);
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 7d0cf7af88ce..e7130293a03f 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -385,7 +385,7 @@ static void __init osk_init(void)
385 /* Workaround for wrong CS3 (NOR flash) timing 385 /* Workaround for wrong CS3 (NOR flash) timing
386 * There are some U-Boot versions out there which configure 386 * There are some U-Boot versions out there which configure
387 * wrong CS3 memory timings. This mainly leads to CRC 387 * wrong CS3 memory timings. This mainly leads to CRC
388 * or similiar errors if you use NOR flash (e.g. with JFFS2) 388 * or similar errors if you use NOR flash (e.g. with JFFS2)
389 */ 389 */
390 if (EMIFS_CCS(3) != EMIFS_CS3_VAL) 390 if (EMIFS_CCS(3) != EMIFS_CS3_VAL)
391 EMIFS_CCS(3) = EMIFS_CS3_VAL; 391 EMIFS_CCS(3) = EMIFS_CS3_VAL;
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 4bc8a62909b9..015824185629 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -7,7 +7,7 @@
7 * 7 *
8 * Original version : Laurent Gonzalez 8 * Original version : Laurent Gonzalez
9 * 9 *
10 * Maintainters : http://palmtelinux.sf.net 10 * Maintainers : http://palmtelinux.sf.net
11 * palmtelinux-developpers@lists.sf.net 11 * palmtelinux-developpers@lists.sf.net
12 * 12 *
13 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 8caee68aa090..5bb348e2e315 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -438,7 +438,7 @@ void omap_pm_suspend(void)
438 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG); 438 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
439 439
440 /* 440 /*
441 * Reenable interrupts 441 * Re-enable interrupts
442 */ 442 */
443 443
444 local_irq_enable(); 444 local_irq_enable();
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 5170481afeab..588adb5ab47f 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -443,7 +443,7 @@ static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
443 443
444/* 444/*
445 * Check the DLL lock state, and return tue if running in unlock mode. 445 * Check the DLL lock state, and return tue if running in unlock mode.
446 * This is needed to compenste for the shifted DLL value in unlock mode. 446 * This is needed to compensate for the shifted DLL value in unlock mode.
447 */ 447 */
448static u32 omap2_dll_force_needed(void) 448static u32 omap2_dll_force_needed(void)
449{ 449{
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 162978fd5359..4f791866b910 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -338,7 +338,7 @@ struct prcm_config {
338/* 338/*
339 * These represent optimal values for common parts, it won't work for all. 339 * These represent optimal values for common parts, it won't work for all.
340 * As long as you scale down, most parameters are still work, they just 340 * As long as you scale down, most parameters are still work, they just
341 * become sub-optimal. The RFR value goes in the oppisite direction. If you 341 * become sub-optimal. The RFR value goes in the opposite direction. If you
342 * don't adjust it down as your clock period increases the refresh interval 342 * don't adjust it down as your clock period increases the refresh interval
343 * will not be met. Setting all parameters for complete worst case may work, 343 * will not be met. Setting all parameters for complete worst case may work,
344 * but may cut memory performance by 2x. Due to errata the DLLs need to be 344 * but may cut memory performance by 2x. Due to errata the DLLs need to be
@@ -384,7 +384,7 @@ struct prcm_config {
384 * Filling in table based on H4 boards and 2430-SDPs variants available. 384 * Filling in table based on H4 boards and 2430-SDPs variants available.
385 * There are quite a few more rates combinations which could be defined. 385 * There are quite a few more rates combinations which could be defined.
386 * 386 *
387 * When multiple values are defiend the start up will try and choose the 387 * When multiple values are defined the start up will try and choose the
388 * fastest one. If a 'fast' value is defined, then automatically, the /2 388 * fastest one. If a 'fast' value is defined, then automatically, the /2
389 * one should be included as it can be used. Generally having more that 389 * one should be included as it can be used. Generally having more that
390 * one fast set does not make sense, as static timings need to be changed 390 * one fast set does not make sense, as static timings need to be changed
diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c
index a72476c24621..365b9435f748 100644
--- a/arch/arm/mach-pxa/corgi_lcd.c
+++ b/arch/arm/mach-pxa/corgi_lcd.c
@@ -40,7 +40,7 @@
40#define PICTRL_ADRS 0x06 40#define PICTRL_ADRS 0x06
41#define POLCTRL_ADRS 0x07 41#define POLCTRL_ADRS 0x07
42 42
43/* Resgister Bit Definitions */ 43/* Register Bit Definitions */
44#define RESCTL_QVGA 0x01 44#define RESCTL_QVGA 0x01
45#define RESCTL_VGA 0x00 45#define RESCTL_VGA 0x00
46 46
@@ -55,11 +55,11 @@
55#define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */ 55#define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */
56#define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */ 56#define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */
57#define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */ 57#define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */
58#define POWER0_COM_ON 0x08 /* COM Powewr Supply ON */ 58#define POWER0_COM_ON 0x08 /* COM Power Supply ON */
59#define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */ 59#define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */
60 60
61#define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */ 61#define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */
62#define POWER0_COM_OFF 0x00 /* COM Powewr Supply OFF */ 62#define POWER0_COM_OFF 0x00 /* COM Power Supply OFF */
63#define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */ 63#define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */
64 64
65#define PICTRL_INIT_STATE 0x01 65#define PICTRL_INIT_STATE 0x01
@@ -145,7 +145,7 @@ static void lcdtg_set_common_voltage(u8 base_data, u8 data)
145 lcdtg_i2c_send_stop(base_data); 145 lcdtg_i2c_send_stop(base_data);
146} 146}
147 147
148/* Set Phase Adjuct */ 148/* Set Phase Adjust */
149static void lcdtg_set_phadadj(int mode) 149static void lcdtg_set_phadadj(int mode)
150{ 150{
151 int adj; 151 int adj;
@@ -226,7 +226,7 @@ static void lcdtg_hw_init(int mode)
226 /* Signals output enable */ 226 /* Signals output enable */
227 corgi_ssp_lcdtg_send(PICTRL_ADRS, 0); 227 corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
228 228
229 /* Set Phase Adjuct */ 229 /* Set Phase Adjust */
230 lcdtg_set_phadadj(mode); 230 lcdtg_set_phadadj(mode);
231 231
232 /* Initialize for Input Signals from ATI */ 232 /* Initialize for Input Signals from ATI */
diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c
index ff6b4ee037f5..40dea3d5142b 100644
--- a/arch/arm/mach-pxa/corgi_ssp.c
+++ b/arch/arm/mach-pxa/corgi_ssp.c
@@ -32,7 +32,7 @@ static struct corgissp_machinfo *ssp_machinfo;
32 * There are three devices connected to the SSP interface: 32 * There are three devices connected to the SSP interface:
33 * 1. A touchscreen controller (TI ADS7846 compatible) 33 * 1. A touchscreen controller (TI ADS7846 compatible)
34 * 2. An LCD contoller (with some Backlight functionality) 34 * 2. An LCD contoller (with some Backlight functionality)
35 * 3. A battery moinitoring IC (Maxim MAX1111) 35 * 3. A battery monitoring IC (Maxim MAX1111)
36 * 36 *
37 * Each device uses a different speed/mode of communication. 37 * Each device uses a different speed/mode of communication.
38 * 38 *
diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c
index caf6b8bb6c95..c7bdf04ab094 100644
--- a/arch/arm/mach-realview/localtimer.c
+++ b/arch/arm/mach-realview/localtimer.c
@@ -30,7 +30,7 @@ static unsigned long mpcore_timer_rate;
30/* 30/*
31 * local_timer_ack: checks for a local timer interrupt. 31 * local_timer_ack: checks for a local timer interrupt.
32 * 32 *
33 * If a local timer interrupt has occured, acknowledge and return 1. 33 * If a local timer interrupt has occurred, acknowledge and return 1.
34 * Otherwise, return 0. 34 * Otherwise, return 0.
35 */ 35 */
36int local_timer_ack(void) 36int local_timer_ack(void)
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 324f5a237921..4d6c7a574c1a 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -45,7 +45,7 @@
45#include <asm/plat-s3c24xx/devs.h> 45#include <asm/plat-s3c24xx/devs.h>
46#include <asm/plat-s3c24xx/cpu.h> 46#include <asm/plat-s3c24xx/cpu.h>
47 47
48/* onboard perihpheral map */ 48/* onboard perihperal map */
49 49
50static struct map_desc osiris_iodesc[] __initdata = { 50static struct map_desc osiris_iodesc[] __initdata = {
51 /* ISA IO areas (may be over-written later) */ 51 /* ISA IO areas (may be over-written later) */
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 416e277054c2..29cb0c1604ab 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -25,7 +25,7 @@ static unsigned long __init sa1100_get_rtc_time(void)
25{ 25{
26 /* 26 /*
27 * According to the manual we should be able to let RTTR be zero 27 * According to the manual we should be able to let RTTR be zero
28 * and then a default diviser for a 32.768KHz clock is used. 28 * and then a default divisor for a 32.768KHz clock is used.
29 * Apparently this doesn't work, at least for my SA1110 rev 5. 29 * Apparently this doesn't work, at least for my SA1110 rev 5.
30 * If the clock divider is uninitialized then reset it to the 30 * If the clock divider is uninitialized then reset it to the
31 * default value to get the 1Hz clock. 31 * default value to get the 1Hz clock.
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 19ca333240ec..36440c899583 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 1995 Linus Torvalds 4 * Copyright (C) 1995 Linus Torvalds
5 * Modifications for ARM processor (c) 1995-2001 Russell King 5 * Modifications for ARM processor (c) 1995-2001 Russell King
6 * Thumb aligment fault fixups (c) 2004 MontaVista Software, Inc. 6 * Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
7 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation. 7 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
8 * Copyright (C) 1996, Cygnus Software Technologies Ltd. 8 * Copyright (C) 1996, Cygnus Software Technologies Ltd.
9 * 9 *
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index d6167ad4e011..f3ade18862aa 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -346,7 +346,7 @@ void __iounmap(volatile void __iomem *addr)
346#ifndef CONFIG_SMP 346#ifndef CONFIG_SMP
347 /* 347 /*
348 * If this is a section based mapping we need to handle it 348 * If this is a section based mapping we need to handle it
349 * specially as the VM subysystem does not know how to handle 349 * specially as the VM subsystem does not know how to handle
350 * such a beast. We need the lock here b/c we need to clear 350 * such a beast. We need the lock here b/c we need to clear
351 * all the mappings before the area can be reclaimed 351 * all the mappings before the area can be reclaimed
352 * by someone else. 352 * by someone else.
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 2ba1530d1ce1..02e050ae59f6 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -92,7 +92,7 @@ static struct cachepolicy cache_policies[] __initdata = {
92}; 92};
93 93
94/* 94/*
95 * These are useful for identifing cache coherency 95 * These are useful for identifying cache coherency
96 * problems by allowing the cache or the cache and 96 * problems by allowing the cache or the cache and
97 * writebuffer to be turned off. (Note: the write 97 * writebuffer to be turned off. (Note: the write
98 * buffer should not be on and the cache off). 98 * buffer should not be on and the cache off).
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index d3605934f1c7..c200c2810066 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -85,7 +85,7 @@ static int iop3xx_pci_status(void)
85 85
86/* 86/*
87 * Simply write the address register and read the configuration 87 * Simply write the address register and read the configuration
88 * data. Note that the 4 nop's ensure that we are able to handle 88 * data. Note that the 4 nops ensure that we are able to handle
89 * a delayed abort (in theory.) 89 * a delayed abort (in theory.)
90 */ 90 */
91static u32 iop3xx_read(unsigned long addr) 91static u32 iop3xx_read(unsigned long addr)
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index dd8708ad0a71..7987aa6e95f8 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -73,7 +73,7 @@ static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
73 } 73 }
74 if (info != NULL) { 74 if (info != NULL) {
75 /* Check the length as a lame attempt to check for 75 /* Check the length as a lame attempt to check for
76 * binary inconsistancy. */ 76 * binary inconsistency. */
77 if (len != NO_LENGTH_CHECK) { 77 if (len != NO_LENGTH_CHECK) {
78 /* Word-align len */ 78 /* Word-align len */
79 if (len & 0x03) 79 if (len & 0x03)
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 55a4d3be16b6..88d5b6d9f950 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1172,7 +1172,7 @@ static void set_b1_regs(void)
1172 break; 1172 break;
1173 default: 1173 default:
1174 BUG(); 1174 BUG();
1175 return; /* Supress warning about uninitialized vars */ 1175 return; /* Suppress warning about uninitialized vars */
1176 } 1176 }
1177 1177
1178 if (omap_dma_in_1510_mode()) { 1178 if (omap_dma_in_1510_mode()) {
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index bc46f33aede3..1f23f0459e5f 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -59,8 +59,8 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
59 59
60/* 60/*
61 * Depending on the target RAMFS firewall setup, the public usable amount of 61 * Depending on the target RAMFS firewall setup, the public usable amount of
62 * SRAM varies. The default accessable size for all device types is 2k. A GP 62 * SRAM varies. The default accessible size for all device types is 2k. A GP
63 * device allows ARM11 but not other initators for full size. This 63 * device allows ARM11 but not other initiators for full size. This
64 * functionality seems ok until some nice security API happens. 64 * functionality seems ok until some nice security API happens.
65 */ 65 */
66static int is_sram_locked(void) 66static int is_sram_locked(void)
@@ -71,7 +71,7 @@ static int is_sram_locked(void)
71 type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK; 71 type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK;
72 72
73 if (type == GP_DEVICE) { 73 if (type == GP_DEVICE) {
74 /* RAMFW: R/W access to all initators for all qualifier sets */ 74 /* RAMFW: R/W access to all initiators for all qualifier sets */
75 if (cpu_is_omap242x()) { 75 if (cpu_is_omap242x()) {
76 __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */ 76 __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */
77 __raw_writel(0xCFDE, VA_READPERM0); /* all i-read */ 77 __raw_writel(0xCFDE, VA_READPERM0); /* all i-read */
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index 25489aafb113..a5aedf964b88 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -177,7 +177,7 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
177 177
178 /* NOTE: SPEED and SUSP aren't configured here. OTG hosts 178 /* NOTE: SPEED and SUSP aren't configured here. OTG hosts
179 * may be able to use I2C requests to set those bits along 179 * may be able to use I2C requests to set those bits along
180 * with VBUS switching and overcurrent detction. 180 * with VBUS switching and overcurrent detection.
181 */ 181 */
182 182
183 if (cpu_class_is_omap1() && nwires != 6) 183 if (cpu_class_is_omap1() && nwires != 6)
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 6f03c9370979..08d80f2f51f2 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -1153,7 +1153,7 @@ EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1153 * 1153 *
1154 * hwcfg: the value for xxxSTCn register, 1154 * hwcfg: the value for xxxSTCn register,
1155 * bit 0: 0=increment pointer, 1=leave pointer 1155 * bit 0: 0=increment pointer, 1=leave pointer
1156 * bit 1: 0=soucre is AHB, 1=soucre is APB 1156 * bit 1: 0=source is AHB, 1=source is APB
1157 * 1157 *
1158 * devaddr: physical address of the source 1158 * devaddr: physical address of the source
1159*/ 1159*/
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index c6b03f8ab260..5692eccdf4d1 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -555,7 +555,7 @@ static int s3c2410_pm_enter(suspend_state_t state)
555 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); 555 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
556 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); 556 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
557 557
558 /* call cpu specific preperation */ 558 /* call cpu specific preparation */
559 559
560 pm_cpu_prep(); 560 pm_cpu_prep();
561 561