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-rw-r--r--arch/arm/Kconfig4
-rw-r--r--arch/arm/Kconfig.debug7
-rw-r--r--arch/arm/include/asm/fiq.h23
-rw-r--r--arch/arm/include/asm/page.h2
-rw-r--r--arch/arm/include/asm/smp.h7
-rw-r--r--arch/arm/include/asm/tlb.h53
-rw-r--r--arch/arm/include/asm/unistd.h1
-rw-r--r--arch/arm/kernel/Makefile2
-rw-r--r--arch/arm/kernel/calls.S1
-rw-r--r--arch/arm/kernel/fiq.c45
-rw-r--r--arch/arm/kernel/fiqasm.S49
-rw-r--r--arch/arm/kernel/head.S7
-rw-r--r--arch/arm/kernel/smp.c1
-rw-r--r--arch/arm/lib/lib1funcs.S25
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h78
-rw-r--r--arch/arm/mach-netx/fb.c1
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c4
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c11
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c4
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c4
-rw-r--r--arch/arm/mach-omap2/board-devkit8000.c4
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c4
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c4
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c4
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3stalker.c4
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c4
-rw-r--r--arch/arm/mach-omap2/board-overo.c4
-rw-r--r--arch/arm/mach-omap2/board-rx51-video.c2
-rw-r--r--arch/arm/mach-omap2/board-zoom-display.c2
-rw-r--r--arch/arm/mach-omap2/display.c77
-rw-r--r--arch/arm/mach-omap2/include/mach/board-zoom.h2
-rw-r--r--arch/arm/mach-shmobile/Makefile5
-rw-r--r--arch/arm/mach-shmobile/board-ag5evm.c118
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c30
-rw-r--r--arch/arm/mach-shmobile/board-g4evm.c2
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c272
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c21
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c19
-rw-r--r--arch/arm/mach-shmobile/cpuidle.c92
-rw-r--r--arch/arm/mach-shmobile/headsmp.S2
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h7
-rw-r--r--arch/arm/mach-shmobile/include/mach/head-ap4evb.txt3
-rw-r--r--arch/arm/mach-shmobile/include/mach/head-mackerel.txt3
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7372.h1
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh73a0.h30
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c46
-rw-r--r--arch/arm/mach-shmobile/pm-sh7372.c108
-rw-r--r--arch/arm/mach-shmobile/setup-sh7367.c223
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c217
-rw-r--r--arch/arm/mach-shmobile/setup-sh7377.c239
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c244
-rw-r--r--arch/arm/mach-shmobile/sleep-sh7372.S260
-rw-r--r--arch/arm/mach-shmobile/smp-sh73a0.c9
-rw-r--r--arch/arm/mach-shmobile/suspend.c47
-rw-r--r--arch/arm/mach-tegra/include/mach/sdhci.h1
-rw-r--r--arch/arm/mach-ux500/Kconfig3
-rw-r--r--arch/arm/mach-ux500/Makefile4
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c16
-rw-r--r--arch/arm/mach-ux500/cpu-db5500.c2
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c7
-rw-r--r--arch/arm/mach-ux500/cpu.c7
-rw-r--r--arch/arm/mach-ux500/cpufreq.c211
-rw-r--r--arch/arm/mach-ux500/devices-common.h10
-rw-r--r--arch/arm/mach-ux500/devices-db5500.h28
-rw-r--r--arch/arm/mach-ux500/devices-db8500.h34
-rw-r--r--arch/arm/mach-ux500/include/mach/db5500-regs.h20
-rw-r--r--arch/arm/mach-ux500/include/mach/db8500-regs.h37
-rw-r--r--arch/arm/mach-ux500/include/mach/hardware.h4
-rw-r--r--arch/arm/mach-ux500/include/mach/id.h20
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-board-mop500.h5
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-board-u5500.h21
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-db5500.h27
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-db8500.h54
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs.h46
-rw-r--r--arch/arm/mach-ux500/include/mach/prcmu-defs.h30
-rw-r--r--arch/arm/mach-ux500/include/mach/prcmu-regs.h96
-rw-r--r--arch/arm/mach-ux500/include/mach/prcmu.h28
-rw-r--r--arch/arm/mach-ux500/prcmu.c394
-rw-r--r--arch/arm/mm/cache-v6.S1
-rw-r--r--arch/arm/mm/cache-v7.S2
-rw-r--r--arch/arm/mm/context.c17
-rw-r--r--arch/arm/mm/init.c6
-rw-r--r--arch/arm/mm/mm.h7
-rw-r--r--arch/arm/mm/mmu.c11
-rw-r--r--arch/arm/mm/proc-v6.S4
-rw-r--r--arch/arm/mm/proc-v7.S14
-rw-r--r--arch/arm/plat-omap/include/plat/display.h591
-rw-r--r--arch/arm/plat-omap/include/plat/nokia-dsi-panel.h31
-rw-r--r--arch/arm/plat-omap/include/plat/panel-generic-dpi.h37
90 files changed, 2519 insertions, 1747 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f59758dd86cf..9adc278a22ab 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1389,7 +1389,6 @@ config NR_CPUS
1389config HOTPLUG_CPU 1389config HOTPLUG_CPU
1390 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" 1390 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1391 depends on SMP && HOTPLUG && EXPERIMENTAL 1391 depends on SMP && HOTPLUG && EXPERIMENTAL
1392 depends on !ARCH_MSM
1393 help 1392 help
1394 Say Y here to experiment with turning CPUs off and on. CPUs 1393 Say Y here to experiment with turning CPUs off and on. CPUs
1395 can be controlled through /sys/devices/system/cpu. 1394 can be controlled through /sys/devices/system/cpu.
@@ -1506,6 +1505,9 @@ config ARCH_SPARSEMEM_DEFAULT
1506config ARCH_SELECT_MEMORY_MODEL 1505config ARCH_SELECT_MEMORY_MODEL
1507 def_bool ARCH_SPARSEMEM_ENABLE 1506 def_bool ARCH_SPARSEMEM_ENABLE
1508 1507
1508config HAVE_ARCH_PFN_VALID
1509 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1510
1509config HIGHMEM 1511config HIGHMEM
1510 bool "High Memory Support" 1512 bool "High Memory Support"
1511 depends on MMU 1513 depends on MMU
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 03d01d783e3b..81cbe40c159c 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -63,13 +63,6 @@ config DEBUG_USER
63 8 - SIGSEGV faults 63 8 - SIGSEGV faults
64 16 - SIGBUS faults 64 16 - SIGBUS faults
65 65
66config DEBUG_STACK_USAGE
67 bool "Enable stack utilization instrumentation"
68 depends on DEBUG_KERNEL
69 help
70 Enables the display of the minimum amount of free stack which each
71 task has ever had available in the sysrq-T output.
72
73# These options are only for real kernel hackers who want to get their hands dirty. 66# These options are only for real kernel hackers who want to get their hands dirty.
74config DEBUG_LL 67config DEBUG_LL
75 bool "Kernel low-level debugging functions" 68 bool "Kernel low-level debugging functions"
diff --git a/arch/arm/include/asm/fiq.h b/arch/arm/include/asm/fiq.h
index 2242ce22ec6c..d493d0b742a1 100644
--- a/arch/arm/include/asm/fiq.h
+++ b/arch/arm/include/asm/fiq.h
@@ -4,6 +4,13 @@
4 * Support for FIQ on ARM architectures. 4 * Support for FIQ on ARM architectures.
5 * Written by Philip Blundell <philb@gnu.org>, 1998 5 * Written by Philip Blundell <philb@gnu.org>, 1998
6 * Re-written by Russell King 6 * Re-written by Russell King
7 *
8 * NOTE: The FIQ mode registers are not magically preserved across
9 * suspend/resume.
10 *
11 * Drivers which require these registers to be preserved across power
12 * management operations must implement appropriate suspend/resume handlers to
13 * save and restore them.
7 */ 14 */
8 15
9#ifndef __ASM_FIQ_H 16#ifndef __ASM_FIQ_H
@@ -29,9 +36,21 @@ struct fiq_handler {
29extern int claim_fiq(struct fiq_handler *f); 36extern int claim_fiq(struct fiq_handler *f);
30extern void release_fiq(struct fiq_handler *f); 37extern void release_fiq(struct fiq_handler *f);
31extern void set_fiq_handler(void *start, unsigned int length); 38extern void set_fiq_handler(void *start, unsigned int length);
32extern void set_fiq_regs(struct pt_regs *regs);
33extern void get_fiq_regs(struct pt_regs *regs);
34extern void enable_fiq(int fiq); 39extern void enable_fiq(int fiq);
35extern void disable_fiq(int fiq); 40extern void disable_fiq(int fiq);
36 41
42/* helpers defined in fiqasm.S: */
43extern void __set_fiq_regs(unsigned long const *regs);
44extern void __get_fiq_regs(unsigned long *regs);
45
46static inline void set_fiq_regs(struct pt_regs const *regs)
47{
48 __set_fiq_regs(&regs->ARM_r8);
49}
50
51static inline void get_fiq_regs(struct pt_regs *regs)
52{
53 __get_fiq_regs(&regs->ARM_r8);
54}
55
37#endif 56#endif
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index f51a69595f6e..ac75d0848889 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -197,7 +197,7 @@ typedef unsigned long pgprot_t;
197 197
198typedef struct page *pgtable_t; 198typedef struct page *pgtable_t;
199 199
200#ifndef CONFIG_SPARSEMEM 200#ifdef CONFIG_HAVE_ARCH_PFN_VALID
201extern int pfn_valid(unsigned long); 201extern int pfn_valid(unsigned long);
202#endif 202#endif
203 203
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index a87664f54f93..e42d96a45d3e 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -20,12 +20,6 @@
20 20
21#define raw_smp_processor_id() (current_thread_info()->cpu) 21#define raw_smp_processor_id() (current_thread_info()->cpu)
22 22
23/*
24 * at the moment, there's not a big penalty for changing CPUs
25 * (the >big< penalty is running SMP in the first place)
26 */
27#define PROC_CHANGE_PENALTY 15
28
29struct seq_file; 23struct seq_file;
30 24
31/* 25/*
@@ -76,6 +70,7 @@ extern void platform_smp_prepare_cpus(unsigned int);
76 */ 70 */
77struct secondary_data { 71struct secondary_data {
78 unsigned long pgdir; 72 unsigned long pgdir;
73 unsigned long swapper_pg_dir;
79 void *stack; 74 void *stack;
80}; 75};
81extern struct secondary_data secondary_data; 76extern struct secondary_data secondary_data;
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index 82dfe5d0c41e..265f908c4a6e 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -41,12 +41,12 @@
41 */ 41 */
42#if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7) 42#if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7)
43#define tlb_fast_mode(tlb) 0 43#define tlb_fast_mode(tlb) 0
44#define FREE_PTE_NR 500
45#else 44#else
46#define tlb_fast_mode(tlb) 1 45#define tlb_fast_mode(tlb) 1
47#define FREE_PTE_NR 0
48#endif 46#endif
49 47
48#define MMU_GATHER_BUNDLE 8
49
50/* 50/*
51 * TLB handling. This allows us to remove pages from the page 51 * TLB handling. This allows us to remove pages from the page
52 * tables, and efficiently handle the TLB issues. 52 * tables, and efficiently handle the TLB issues.
@@ -58,7 +58,9 @@ struct mmu_gather {
58 unsigned long range_start; 58 unsigned long range_start;
59 unsigned long range_end; 59 unsigned long range_end;
60 unsigned int nr; 60 unsigned int nr;
61 struct page *pages[FREE_PTE_NR]; 61 unsigned int max;
62 struct page **pages;
63 struct page *local[MMU_GATHER_BUNDLE];
62}; 64};
63 65
64DECLARE_PER_CPU(struct mmu_gather, mmu_gathers); 66DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
@@ -97,26 +99,37 @@ static inline void tlb_add_flush(struct mmu_gather *tlb, unsigned long addr)
97 } 99 }
98} 100}
99 101
102static inline void __tlb_alloc_page(struct mmu_gather *tlb)
103{
104 unsigned long addr = __get_free_pages(GFP_NOWAIT | __GFP_NOWARN, 0);
105
106 if (addr) {
107 tlb->pages = (void *)addr;
108 tlb->max = PAGE_SIZE / sizeof(struct page *);
109 }
110}
111
100static inline void tlb_flush_mmu(struct mmu_gather *tlb) 112static inline void tlb_flush_mmu(struct mmu_gather *tlb)
101{ 113{
102 tlb_flush(tlb); 114 tlb_flush(tlb);
103 if (!tlb_fast_mode(tlb)) { 115 if (!tlb_fast_mode(tlb)) {
104 free_pages_and_swap_cache(tlb->pages, tlb->nr); 116 free_pages_and_swap_cache(tlb->pages, tlb->nr);
105 tlb->nr = 0; 117 tlb->nr = 0;
118 if (tlb->pages == tlb->local)
119 __tlb_alloc_page(tlb);
106 } 120 }
107} 121}
108 122
109static inline struct mmu_gather * 123static inline void
110tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush) 124tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int fullmm)
111{ 125{
112 struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
113
114 tlb->mm = mm; 126 tlb->mm = mm;
115 tlb->fullmm = full_mm_flush; 127 tlb->fullmm = fullmm;
116 tlb->vma = NULL; 128 tlb->vma = NULL;
129 tlb->max = ARRAY_SIZE(tlb->local);
130 tlb->pages = tlb->local;
117 tlb->nr = 0; 131 tlb->nr = 0;
118 132 __tlb_alloc_page(tlb);
119 return tlb;
120} 133}
121 134
122static inline void 135static inline void
@@ -127,7 +140,8 @@ tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
127 /* keep the page table cache within bounds */ 140 /* keep the page table cache within bounds */
128 check_pgt_cache(); 141 check_pgt_cache();
129 142
130 put_cpu_var(mmu_gathers); 143 if (tlb->pages != tlb->local)
144 free_pages((unsigned long)tlb->pages, 0);
131} 145}
132 146
133/* 147/*
@@ -162,15 +176,22 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
162 tlb_flush(tlb); 176 tlb_flush(tlb);
163} 177}
164 178
165static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page) 179static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
166{ 180{
167 if (tlb_fast_mode(tlb)) { 181 if (tlb_fast_mode(tlb)) {
168 free_page_and_swap_cache(page); 182 free_page_and_swap_cache(page);
169 } else { 183 return 1; /* avoid calling tlb_flush_mmu */
170 tlb->pages[tlb->nr++] = page;
171 if (tlb->nr >= FREE_PTE_NR)
172 tlb_flush_mmu(tlb);
173 } 184 }
185
186 tlb->pages[tlb->nr++] = page;
187 VM_BUG_ON(tlb->nr > tlb->max);
188 return tlb->max - tlb->nr;
189}
190
191static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
192{
193 if (!__tlb_remove_page(tlb, page))
194 tlb_flush_mmu(tlb);
174} 195}
175 196
176static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, 197static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 87dbe3e21970..3de689aa6f68 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -400,6 +400,7 @@
400#define __NR_open_by_handle_at (__NR_SYSCALL_BASE+371) 400#define __NR_open_by_handle_at (__NR_SYSCALL_BASE+371)
401#define __NR_clock_adjtime (__NR_SYSCALL_BASE+372) 401#define __NR_clock_adjtime (__NR_SYSCALL_BASE+372)
402#define __NR_syncfs (__NR_SYSCALL_BASE+373) 402#define __NR_syncfs (__NR_SYSCALL_BASE+373)
403#define __NR_sendmmsg (__NR_SYSCALL_BASE+374)
403 404
404/* 405/*
405 * The following SWIs are ARM private. 406 * The following SWIs are ARM private.
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 908c78cb1d1c..a5b31af5c2b8 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -24,7 +24,7 @@ obj-$(CONFIG_OC_ETM) += etm.o
24 24
25obj-$(CONFIG_ISA_DMA_API) += dma.o 25obj-$(CONFIG_ISA_DMA_API) += dma.o
26obj-$(CONFIG_ARCH_ACORN) += ecard.o 26obj-$(CONFIG_ARCH_ACORN) += ecard.o
27obj-$(CONFIG_FIQ) += fiq.o 27obj-$(CONFIG_FIQ) += fiq.o fiqasm.o
28obj-$(CONFIG_MODULES) += armksyms.o module.o 28obj-$(CONFIG_MODULES) += armksyms.o module.o
29obj-$(CONFIG_ARTHUR) += arthur.o 29obj-$(CONFIG_ARTHUR) += arthur.o
30obj-$(CONFIG_ISA_DMA) += dma-isa.o 30obj-$(CONFIG_ISA_DMA) += dma-isa.o
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 7fbf28c35bb2..24cdac3ce2e3 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -383,6 +383,7 @@
383 CALL(sys_open_by_handle_at) 383 CALL(sys_open_by_handle_at)
384 CALL(sys_clock_adjtime) 384 CALL(sys_clock_adjtime)
385 CALL(sys_syncfs) 385 CALL(sys_syncfs)
386 CALL(sys_sendmmsg)
386#ifndef syscalls_counted 387#ifndef syscalls_counted
387.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls 388.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
388#define syscalls_counted 389#define syscalls_counted
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index e72dc34eea1c..4c164ece5891 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -89,47 +89,6 @@ void set_fiq_handler(void *start, unsigned int length)
89 flush_icache_range(0x1c, 0x1c + length); 89 flush_icache_range(0x1c, 0x1c + length);
90} 90}
91 91
92/*
93 * Taking an interrupt in FIQ mode is death, so both these functions
94 * disable irqs for the duration. Note - these functions are almost
95 * entirely coded in assembly.
96 */
97void __naked set_fiq_regs(struct pt_regs *regs)
98{
99 register unsigned long tmp;
100 asm volatile (
101 "mov ip, sp\n\
102 stmfd sp!, {fp, ip, lr, pc}\n\
103 sub fp, ip, #4\n\
104 mrs %0, cpsr\n\
105 msr cpsr_c, %2 @ select FIQ mode\n\
106 mov r0, r0\n\
107 ldmia %1, {r8 - r14}\n\
108 msr cpsr_c, %0 @ return to SVC mode\n\
109 mov r0, r0\n\
110 ldmfd sp, {fp, sp, pc}"
111 : "=&r" (tmp)
112 : "r" (&regs->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | FIQ_MODE));
113}
114
115void __naked get_fiq_regs(struct pt_regs *regs)
116{
117 register unsigned long tmp;
118 asm volatile (
119 "mov ip, sp\n\
120 stmfd sp!, {fp, ip, lr, pc}\n\
121 sub fp, ip, #4\n\
122 mrs %0, cpsr\n\
123 msr cpsr_c, %2 @ select FIQ mode\n\
124 mov r0, r0\n\
125 stmia %1, {r8 - r14}\n\
126 msr cpsr_c, %0 @ return to SVC mode\n\
127 mov r0, r0\n\
128 ldmfd sp, {fp, sp, pc}"
129 : "=&r" (tmp)
130 : "r" (&regs->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | FIQ_MODE));
131}
132
133int claim_fiq(struct fiq_handler *f) 92int claim_fiq(struct fiq_handler *f)
134{ 93{
135 int ret = 0; 94 int ret = 0;
@@ -174,8 +133,8 @@ void disable_fiq(int fiq)
174} 133}
175 134
176EXPORT_SYMBOL(set_fiq_handler); 135EXPORT_SYMBOL(set_fiq_handler);
177EXPORT_SYMBOL(set_fiq_regs); 136EXPORT_SYMBOL(__set_fiq_regs); /* defined in fiqasm.S */
178EXPORT_SYMBOL(get_fiq_regs); 137EXPORT_SYMBOL(__get_fiq_regs); /* defined in fiqasm.S */
179EXPORT_SYMBOL(claim_fiq); 138EXPORT_SYMBOL(claim_fiq);
180EXPORT_SYMBOL(release_fiq); 139EXPORT_SYMBOL(release_fiq);
181EXPORT_SYMBOL(enable_fiq); 140EXPORT_SYMBOL(enable_fiq);
diff --git a/arch/arm/kernel/fiqasm.S b/arch/arm/kernel/fiqasm.S
new file mode 100644
index 000000000000..207f9d652010
--- /dev/null
+++ b/arch/arm/kernel/fiqasm.S
@@ -0,0 +1,49 @@
1/*
2 * linux/arch/arm/kernel/fiqasm.S
3 *
4 * Derived from code originally in linux/arch/arm/kernel/fiq.c:
5 *
6 * Copyright (C) 1998 Russell King
7 * Copyright (C) 1998, 1999 Phil Blundell
8 * Copyright (C) 2011, Linaro Limited
9 *
10 * FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
11 *
12 * FIQ support re-written by Russell King to be more generic
13 *
14 * v7/Thumb-2 compatibility modifications by Linaro Limited, 2011.
15 */
16
17#include <linux/linkage.h>
18#include <asm/assembler.h>
19
20/*
21 * Taking an interrupt in FIQ mode is death, so both these functions
22 * disable irqs for the duration.
23 */
24
25ENTRY(__set_fiq_regs)
26 mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
27 mrs r1, cpsr
28 msr cpsr_c, r2 @ select FIQ mode
29 mov r0, r0 @ avoid hazard prior to ARMv4
30 ldmia r0!, {r8 - r12}
31 ldr sp, [r0], #4
32 ldr lr, [r0]
33 msr cpsr_c, r1 @ return to SVC mode
34 mov r0, r0 @ avoid hazard prior to ARMv4
35 mov pc, lr
36ENDPROC(__set_fiq_regs)
37
38ENTRY(__get_fiq_regs)
39 mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
40 mrs r1, cpsr
41 msr cpsr_c, r2 @ select FIQ mode
42 mov r0, r0 @ avoid hazard prior to ARMv4
43 stmia r0!, {r8 - r12}
44 str sp, [r0], #4
45 str lr, [r0]
46 msr cpsr_c, r1 @ return to SVC mode
47 mov r0, r0 @ avoid hazard prior to ARMv4
48 mov pc, lr
49ENDPROC(__get_fiq_regs)
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index a5e5c5b9b48e..278c1b0ebb2e 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -113,6 +113,7 @@ ENTRY(stext)
113 ldr r13, =__mmap_switched @ address to jump to after 113 ldr r13, =__mmap_switched @ address to jump to after
114 @ mmu has been enabled 114 @ mmu has been enabled
115 adr lr, BSYM(1f) @ return (PIC) address 115 adr lr, BSYM(1f) @ return (PIC) address
116 mov r8, r4 @ set TTBR1 to swapper_pg_dir
116 ARM( add pc, r10, #PROCINFO_INITFUNC ) 117 ARM( add pc, r10, #PROCINFO_INITFUNC )
117 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 118 THUMB( add r12, r10, #PROCINFO_INITFUNC )
118 THUMB( mov pc, r12 ) 119 THUMB( mov pc, r12 )
@@ -302,8 +303,10 @@ ENTRY(secondary_startup)
302 */ 303 */
303 adr r4, __secondary_data 304 adr r4, __secondary_data
304 ldmia r4, {r5, r7, r12} @ address to jump to after 305 ldmia r4, {r5, r7, r12} @ address to jump to after
305 sub r4, r4, r5 @ mmu has been enabled 306 sub lr, r4, r5 @ mmu has been enabled
306 ldr r4, [r7, r4] @ get secondary_data.pgdir 307 ldr r4, [r7, lr] @ get secondary_data.pgdir
308 add r7, r7, #4
309 ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir
307 adr lr, BSYM(__enable_mmu) @ return address 310 adr lr, BSYM(__enable_mmu) @ return address
308 mov r13, r12 @ __secondary_switched address 311 mov r13, r12 @ __secondary_switched address
309 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor 312 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index d439a8f4c078..344e52b16c8c 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -105,6 +105,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
105 */ 105 */
106 secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; 106 secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
107 secondary_data.pgdir = virt_to_phys(pgd); 107 secondary_data.pgdir = virt_to_phys(pgd);
108 secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir);
108 __cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data)); 109 __cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
109 outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1)); 110 outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
110 111
diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
index 6dc06487f3c3..c562f649734c 100644
--- a/arch/arm/lib/lib1funcs.S
+++ b/arch/arm/lib/lib1funcs.S
@@ -35,7 +35,7 @@ Boston, MA 02111-1307, USA. */
35 35
36#include <linux/linkage.h> 36#include <linux/linkage.h>
37#include <asm/assembler.h> 37#include <asm/assembler.h>
38 38#include <asm/unwind.h>
39 39
40.macro ARM_DIV_BODY dividend, divisor, result, curbit 40.macro ARM_DIV_BODY dividend, divisor, result, curbit
41 41
@@ -207,6 +207,7 @@ Boston, MA 02111-1307, USA. */
207 207
208ENTRY(__udivsi3) 208ENTRY(__udivsi3)
209ENTRY(__aeabi_uidiv) 209ENTRY(__aeabi_uidiv)
210UNWIND(.fnstart)
210 211
211 subs r2, r1, #1 212 subs r2, r1, #1
212 moveq pc, lr 213 moveq pc, lr
@@ -230,10 +231,12 @@ ENTRY(__aeabi_uidiv)
230 mov r0, r0, lsr r2 231 mov r0, r0, lsr r2
231 mov pc, lr 232 mov pc, lr
232 233
234UNWIND(.fnend)
233ENDPROC(__udivsi3) 235ENDPROC(__udivsi3)
234ENDPROC(__aeabi_uidiv) 236ENDPROC(__aeabi_uidiv)
235 237
236ENTRY(__umodsi3) 238ENTRY(__umodsi3)
239UNWIND(.fnstart)
237 240
238 subs r2, r1, #1 @ compare divisor with 1 241 subs r2, r1, #1 @ compare divisor with 1
239 bcc Ldiv0 242 bcc Ldiv0
@@ -247,10 +250,12 @@ ENTRY(__umodsi3)
247 250
248 mov pc, lr 251 mov pc, lr
249 252
253UNWIND(.fnend)
250ENDPROC(__umodsi3) 254ENDPROC(__umodsi3)
251 255
252ENTRY(__divsi3) 256ENTRY(__divsi3)
253ENTRY(__aeabi_idiv) 257ENTRY(__aeabi_idiv)
258UNWIND(.fnstart)
254 259
255 cmp r1, #0 260 cmp r1, #0
256 eor ip, r0, r1 @ save the sign of the result. 261 eor ip, r0, r1 @ save the sign of the result.
@@ -287,10 +292,12 @@ ENTRY(__aeabi_idiv)
287 rsbmi r0, r0, #0 292 rsbmi r0, r0, #0
288 mov pc, lr 293 mov pc, lr
289 294
295UNWIND(.fnend)
290ENDPROC(__divsi3) 296ENDPROC(__divsi3)
291ENDPROC(__aeabi_idiv) 297ENDPROC(__aeabi_idiv)
292 298
293ENTRY(__modsi3) 299ENTRY(__modsi3)
300UNWIND(.fnstart)
294 301
295 cmp r1, #0 302 cmp r1, #0
296 beq Ldiv0 303 beq Ldiv0
@@ -310,11 +317,14 @@ ENTRY(__modsi3)
310 rsbmi r0, r0, #0 317 rsbmi r0, r0, #0
311 mov pc, lr 318 mov pc, lr
312 319
320UNWIND(.fnend)
313ENDPROC(__modsi3) 321ENDPROC(__modsi3)
314 322
315#ifdef CONFIG_AEABI 323#ifdef CONFIG_AEABI
316 324
317ENTRY(__aeabi_uidivmod) 325ENTRY(__aeabi_uidivmod)
326UNWIND(.fnstart)
327UNWIND(.save {r0, r1, ip, lr} )
318 328
319 stmfd sp!, {r0, r1, ip, lr} 329 stmfd sp!, {r0, r1, ip, lr}
320 bl __aeabi_uidiv 330 bl __aeabi_uidiv
@@ -323,10 +333,12 @@ ENTRY(__aeabi_uidivmod)
323 sub r1, r1, r3 333 sub r1, r1, r3
324 mov pc, lr 334 mov pc, lr
325 335
336UNWIND(.fnend)
326ENDPROC(__aeabi_uidivmod) 337ENDPROC(__aeabi_uidivmod)
327 338
328ENTRY(__aeabi_idivmod) 339ENTRY(__aeabi_idivmod)
329 340UNWIND(.fnstart)
341UNWIND(.save {r0, r1, ip, lr} )
330 stmfd sp!, {r0, r1, ip, lr} 342 stmfd sp!, {r0, r1, ip, lr}
331 bl __aeabi_idiv 343 bl __aeabi_idiv
332 ldmfd sp!, {r1, r2, ip, lr} 344 ldmfd sp!, {r1, r2, ip, lr}
@@ -334,15 +346,18 @@ ENTRY(__aeabi_idivmod)
334 sub r1, r1, r3 346 sub r1, r1, r3
335 mov pc, lr 347 mov pc, lr
336 348
349UNWIND(.fnend)
337ENDPROC(__aeabi_idivmod) 350ENDPROC(__aeabi_idivmod)
338 351
339#endif 352#endif
340 353
341Ldiv0: 354Ldiv0:
342 355UNWIND(.fnstart)
356UNWIND(.pad #4)
357UNWIND(.save {lr})
343 str lr, [sp, #-8]! 358 str lr, [sp, #-8]!
344 bl __div0 359 bl __div0
345 mov r0, #0 @ About as wrong as it could be. 360 mov r0, #0 @ About as wrong as it could be.
346 ldr pc, [sp], #8 361 ldr pc, [sp], #8
347 362UNWIND(.fnend)
348 363ENDPROC(Ldiv0)
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
new file mode 100644
index 000000000000..292d55ed2113
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
@@ -0,0 +1,78 @@
1/*
2 * PTP 1588 clock using the IXP46X
3 *
4 * Copyright (C) 2010 OMICRON electronics GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#ifndef _IXP46X_TS_H_
22#define _IXP46X_TS_H_
23
24#define DEFAULT_ADDEND 0xF0000029
25#define TICKS_NS_SHIFT 4
26
27struct ixp46x_channel_ctl {
28 u32 ch_control; /* 0x40 Time Synchronization Channel Control */
29 u32 ch_event; /* 0x44 Time Synchronization Channel Event */
30 u32 tx_snap_lo; /* 0x48 Transmit Snapshot Low Register */
31 u32 tx_snap_hi; /* 0x4C Transmit Snapshot High Register */
32 u32 rx_snap_lo; /* 0x50 Receive Snapshot Low Register */
33 u32 rx_snap_hi; /* 0x54 Receive Snapshot High Register */
34 u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
35 u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
36};
37
38struct ixp46x_ts_regs {
39 u32 control; /* 0x00 Time Sync Control Register */
40 u32 event; /* 0x04 Time Sync Event Register */
41 u32 addend; /* 0x08 Time Sync Addend Register */
42 u32 accum; /* 0x0C Time Sync Accumulator Register */
43 u32 test; /* 0x10 Time Sync Test Register */
44 u32 unused; /* 0x14 */
45 u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */
46 u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */
47 u32 systime_lo; /* 0x20 SystemTime_Low Register */
48 u32 systime_hi; /* 0x24 SystemTime_High Register */
49 u32 trgt_lo; /* 0x28 TargetTime_Low Register */
50 u32 trgt_hi; /* 0x2C TargetTime_High Register */
51 u32 asms_lo; /* 0x30 Auxiliary Slave Mode Snapshot Low */
52 u32 asms_hi; /* 0x34 Auxiliary Slave Mode Snapshot High */
53 u32 amms_lo; /* 0x38 Auxiliary Master Mode Snapshot Low */
54 u32 amms_hi; /* 0x3C Auxiliary Master Mode Snapshot High */
55
56 struct ixp46x_channel_ctl channel[3];
57};
58
59/* 0x00 Time Sync Control Register Bits */
60#define TSCR_AMM (1<<3)
61#define TSCR_ASM (1<<2)
62#define TSCR_TTM (1<<1)
63#define TSCR_RST (1<<0)
64
65/* 0x04 Time Sync Event Register Bits */
66#define TSER_SNM (1<<3)
67#define TSER_SNS (1<<2)
68#define TTIPEND (1<<1)
69
70/* 0x40 Time Synchronization Channel Control Register Bits */
71#define MASTER_MODE (1<<0)
72#define TIMESTAMP_ALL (1<<1)
73
74/* 0x44 Time Synchronization Channel Event Register Bits */
75#define TX_SNAPSHOT_LOCKED (1<<0)
76#define RX_SNAPSHOT_LOCKED (1<<1)
77
78#endif
diff --git a/arch/arm/mach-netx/fb.c b/arch/arm/mach-netx/fb.c
index 5b84bcd30271..b9913234bbf6 100644
--- a/arch/arm/mach-netx/fb.c
+++ b/arch/arm/mach-netx/fb.c
@@ -103,7 +103,6 @@ static struct amba_device fb_device = {
103 .flags = IORESOURCE_MEM, 103 .flags = IORESOURCE_MEM,
104 }, 104 },
105 .irq = { NETX_IRQ_LCD, NO_IRQ }, 105 .irq = { NETX_IRQ_LCD, NO_IRQ },
106 .periphid = 0x10112400,
107}; 106};
108 107
109int netx_fb_init(struct clcd_board *board, struct clcd_panel *panel) 108int netx_fb_init(struct clcd_board *board, struct clcd_panel *panel)
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 9afd087cc29c..23244cd0a5b6 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -37,8 +37,8 @@
37#include <plat/common.h> 37#include <plat/common.h>
38#include <plat/dma.h> 38#include <plat/dma.h>
39#include <plat/gpmc.h> 39#include <plat/gpmc.h>
40#include <plat/display.h> 40#include <video/omapdss.h>
41#include <plat/panel-generic-dpi.h> 41#include <video/omap-panel-generic-dpi.h>
42 42
43#include <plat/gpmc-smc91x.h> 43#include <plat/gpmc-smc91x.h>
44 44
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 56702c5e577f..93edd7fcf451 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -36,7 +36,7 @@
36#include <plat/usb.h> 36#include <plat/usb.h>
37#include <plat/mmc.h> 37#include <plat/mmc.h>
38#include <plat/omap4-keypad.h> 38#include <plat/omap4-keypad.h>
39#include <plat/display.h> 39#include <video/omapdss.h>
40 40
41#include "mux.h" 41#include "mux.h"
42#include "hsmmc.h" 42#include "hsmmc.h"
@@ -680,6 +680,15 @@ static struct omap_dss_device sdp4430_hdmi_device = {
680 .name = "hdmi", 680 .name = "hdmi",
681 .driver_name = "hdmi_panel", 681 .driver_name = "hdmi_panel",
682 .type = OMAP_DISPLAY_TYPE_HDMI, 682 .type = OMAP_DISPLAY_TYPE_HDMI,
683 .clocks = {
684 .dispc = {
685 .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
686 },
687 .hdmi = {
688 .regn = 15,
689 .regm2 = 1,
690 },
691 },
683 .platform_enable = sdp4430_panel_enable_hdmi, 692 .platform_enable = sdp4430_panel_enable_hdmi,
684 .platform_disable = sdp4430_panel_disable_hdmi, 693 .platform_disable = sdp4430_panel_disable_hdmi,
685 .channel = OMAP_DSS_CHANNEL_DIGIT, 694 .channel = OMAP_DSS_CHANNEL_DIGIT,
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index ce7d5e6e4150..ff8c59be36e5 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -34,8 +34,8 @@
34#include <plat/board.h> 34#include <plat/board.h>
35#include <plat/common.h> 35#include <plat/common.h>
36#include <plat/usb.h> 36#include <plat/usb.h>
37#include <plat/display.h> 37#include <video/omapdss.h>
38#include <plat/panel-generic-dpi.h> 38#include <video/omap-panel-generic-dpi.h>
39 39
40#include "mux.h" 40#include "mux.h"
41#include "control.h" 41#include "control.h"
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 02a12b41c0ff..9340f6a06f4a 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -45,8 +45,8 @@
45#include <plat/nand.h> 45#include <plat/nand.h>
46#include <plat/gpmc.h> 46#include <plat/gpmc.h>
47#include <plat/usb.h> 47#include <plat/usb.h>
48#include <plat/display.h> 48#include <video/omapdss.h>
49#include <plat/panel-generic-dpi.h> 49#include <video/omap-panel-generic-dpi.h>
50#include <plat/mcspi.h> 50#include <plat/mcspi.h>
51 51
52#include <mach/hardware.h> 52#include <mach/hardware.h>
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 65f9fde2c567..1d1b56a29fb1 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -45,8 +45,8 @@
45#include <plat/gpmc.h> 45#include <plat/gpmc.h>
46#include <plat/nand.h> 46#include <plat/nand.h>
47#include <plat/usb.h> 47#include <plat/usb.h>
48#include <plat/display.h> 48#include <video/omapdss.h>
49#include <plat/panel-generic-dpi.h> 49#include <video/omap-panel-generic-dpi.h>
50 50
51#include <plat/mcspi.h> 51#include <plat/mcspi.h>
52#include <linux/input/matrix_keypad.h> 52#include <linux/input/matrix_keypad.h>
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 34cf982b9679..3da64d361651 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -31,8 +31,8 @@
31#include <plat/common.h> 31#include <plat/common.h>
32#include <plat/gpmc.h> 32#include <plat/gpmc.h>
33#include <plat/usb.h> 33#include <plat/usb.h>
34#include <plat/display.h> 34#include <video/omapdss.h>
35#include <plat/panel-generic-dpi.h> 35#include <video/omap-panel-generic-dpi.h>
36#include <plat/onenand.h> 36#include <plat/onenand.h>
37 37
38#include "mux.h" 38#include "mux.h"
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 33007fd4a083..97750d483a70 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -41,8 +41,8 @@
41 41
42#include <plat/board.h> 42#include <plat/board.h>
43#include <plat/common.h> 43#include <plat/common.h>
44#include <plat/display.h> 44#include <video/omapdss.h>
45#include <plat/panel-generic-dpi.h> 45#include <video/omap-panel-generic-dpi.h>
46#include <plat/gpmc.h> 46#include <plat/gpmc.h>
47#include <plat/nand.h> 47#include <plat/nand.h>
48#include <plat/usb.h> 48#include <plat/usb.h>
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 5a1a916e5cc8..7f94cccdb076 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -44,8 +44,8 @@
44#include <plat/usb.h> 44#include <plat/usb.h>
45#include <plat/common.h> 45#include <plat/common.h>
46#include <plat/mcspi.h> 46#include <plat/mcspi.h>
47#include <plat/display.h> 47#include <video/omapdss.h>
48#include <plat/panel-generic-dpi.h> 48#include <video/omap-panel-generic-dpi.h>
49 49
50#include "mux.h" 50#include "mux.h"
51#include "sdram-micron-mt46h32m32lf-6.h" 51#include "sdram-micron-mt46h32m32lf-6.h"
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 07dba888f450..1db15492d82b 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -46,7 +46,7 @@
46#include <mach/hardware.h> 46#include <mach/hardware.h>
47#include <plat/mcspi.h> 47#include <plat/mcspi.h>
48#include <plat/usb.h> 48#include <plat/usb.h>
49#include <plat/display.h> 49#include <video/omapdss.h>
50#include <plat/nand.h> 50#include <plat/nand.h>
51 51
52#include "mux.h" 52#include "mux.h"
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index a6e0b9161c99..a72c90a08c8a 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -39,8 +39,8 @@
39#include <plat/gpmc.h> 39#include <plat/gpmc.h>
40#include <plat/nand.h> 40#include <plat/nand.h>
41#include <plat/usb.h> 41#include <plat/usb.h>
42#include <plat/display.h> 42#include <video/omapdss.h>
43#include <plat/panel-generic-dpi.h> 43#include <video/omap-panel-generic-dpi.h>
44 44
45#include <plat/mcspi.h> 45#include <plat/mcspi.h>
46#include <linux/input/matrix_keypad.h> 46#include <linux/input/matrix_keypad.h>
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index f3a7b1011914..e4973ac77cbc 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -34,13 +34,13 @@
34#include <asm/mach-types.h> 34#include <asm/mach-types.h>
35#include <asm/mach/arch.h> 35#include <asm/mach/arch.h>
36#include <asm/mach/map.h> 36#include <asm/mach/map.h>
37#include <plat/display.h> 37#include <video/omapdss.h>
38 38
39#include <plat/board.h> 39#include <plat/board.h>
40#include <plat/common.h> 40#include <plat/common.h>
41#include <plat/usb.h> 41#include <plat/usb.h>
42#include <plat/mmc.h> 42#include <plat/mmc.h>
43#include <plat/panel-generic-dpi.h> 43#include <video/omap-panel-generic-dpi.h>
44#include "timer-gp.h" 44#include "timer-gp.h"
45 45
46#include "hsmmc.h" 46#include "hsmmc.h"
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 59ca33326b8c..9d192ff3b9ac 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -43,8 +43,8 @@
43 43
44#include <plat/board.h> 44#include <plat/board.h>
45#include <plat/common.h> 45#include <plat/common.h>
46#include <plat/display.h> 46#include <video/omapdss.h>
47#include <plat/panel-generic-dpi.h> 47#include <video/omap-panel-generic-dpi.h>
48#include <mach/gpio.h> 48#include <mach/gpio.h>
49#include <plat/gpmc.h> 49#include <plat/gpmc.h>
50#include <mach/hardware.h> 50#include <mach/hardware.h>
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index 89a66db8b77d..2df10b6a5940 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -15,7 +15,7 @@
15#include <linux/spi/spi.h> 15#include <linux/spi/spi.h>
16#include <linux/mm.h> 16#include <linux/mm.h>
17#include <asm/mach-types.h> 17#include <asm/mach-types.h>
18#include <plat/display.h> 18#include <video/omapdss.h>
19#include <plat/vram.h> 19#include <plat/vram.h>
20#include <plat/mcspi.h> 20#include <plat/mcspi.h>
21 21
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index 37b84c2b850f..60e8645db59d 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -15,7 +15,7 @@
15#include <linux/i2c/twl.h> 15#include <linux/i2c/twl.h>
16#include <linux/spi/spi.h> 16#include <linux/spi/spi.h>
17#include <plat/mcspi.h> 17#include <plat/mcspi.h>
18#include <plat/display.h> 18#include <video/omapdss.h>
19 19
20#define LCD_PANEL_RESET_GPIO_PROD 96 20#define LCD_PANEL_RESET_GPIO_PROD 96
21#define LCD_PANEL_RESET_GPIO_PILOT 55 21#define LCD_PANEL_RESET_GPIO_PILOT 55
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 256d23fb79ab..543fcb8b518c 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -22,7 +22,7 @@
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/err.h> 23#include <linux/err.h>
24 24
25#include <plat/display.h> 25#include <video/omapdss.h>
26#include <plat/omap_hwmod.h> 26#include <plat/omap_hwmod.h>
27#include <plat/omap_device.h> 27#include <plat/omap_device.h>
28 28
@@ -56,37 +56,58 @@ static bool opt_clock_available(const char *clk_role)
56 return false; 56 return false;
57} 57}
58 58
59struct omap_dss_hwmod_data {
60 const char *oh_name;
61 const char *dev_name;
62 const int id;
63};
64
65static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
66 { "dss_core", "omapdss_dss", -1 },
67 { "dss_dispc", "omapdss_dispc", -1 },
68 { "dss_rfbi", "omapdss_rfbi", -1 },
69 { "dss_venc", "omapdss_venc", -1 },
70};
71
72static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
73 { "dss_core", "omapdss_dss", -1 },
74 { "dss_dispc", "omapdss_dispc", -1 },
75 { "dss_rfbi", "omapdss_rfbi", -1 },
76 { "dss_venc", "omapdss_venc", -1 },
77 { "dss_dsi1", "omapdss_dsi1", -1 },
78};
79
80static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
81 { "dss_core", "omapdss_dss", -1 },
82 { "dss_dispc", "omapdss_dispc", -1 },
83 { "dss_rfbi", "omapdss_rfbi", -1 },
84 { "dss_venc", "omapdss_venc", -1 },
85 { "dss_dsi1", "omapdss_dsi1", -1 },
86 { "dss_dsi2", "omapdss_dsi2", -1 },
87 { "dss_hdmi", "omapdss_hdmi", -1 },
88};
89
59int __init omap_display_init(struct omap_dss_board_info *board_data) 90int __init omap_display_init(struct omap_dss_board_info *board_data)
60{ 91{
61 int r = 0; 92 int r = 0;
62 struct omap_hwmod *oh; 93 struct omap_hwmod *oh;
63 struct omap_device *od; 94 struct omap_device *od;
64 int i; 95 int i, oh_count;
65 struct omap_display_platform_data pdata; 96 struct omap_display_platform_data pdata;
66 97 const struct omap_dss_hwmod_data *curr_dss_hwmod;
67 /*
68 * omap: valid DSS hwmod names
69 * omap2,3,4: dss_core, dss_dispc, dss_rfbi, dss_venc
70 * omap3,4: dss_dsi1
71 * omap4: dss_dsi2, dss_hdmi
72 */
73 char *oh_name[] = { "dss_core", "dss_dispc", "dss_rfbi", "dss_venc",
74 "dss_dsi1", "dss_dsi2", "dss_hdmi" };
75 char *dev_name[] = { "omapdss_dss", "omapdss_dispc", "omapdss_rfbi",
76 "omapdss_venc", "omapdss_dsi1", "omapdss_dsi2",
77 "omapdss_hdmi" };
78 int oh_count;
79 98
80 memset(&pdata, 0, sizeof(pdata)); 99 memset(&pdata, 0, sizeof(pdata));
81 100
82 if (cpu_is_omap24xx()) 101 if (cpu_is_omap24xx()) {
83 oh_count = ARRAY_SIZE(oh_name) - 3; 102 curr_dss_hwmod = omap2_dss_hwmod_data;
84 /* last 3 hwmod dev in oh_name are not available for omap2 */ 103 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
85 else if (cpu_is_omap44xx()) 104 } else if (cpu_is_omap34xx()) {
86 oh_count = ARRAY_SIZE(oh_name); 105 curr_dss_hwmod = omap3_dss_hwmod_data;
87 else 106 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
88 oh_count = ARRAY_SIZE(oh_name) - 2; 107 } else {
89 /* last 2 hwmod dev in oh_name are not available for omap3 */ 108 curr_dss_hwmod = omap4_dss_hwmod_data;
109 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
110 }
90 111
91 /* opt_clks are always associated with dss hwmod */ 112 /* opt_clks are always associated with dss hwmod */
92 oh_core = omap_hwmod_lookup("dss_core"); 113 oh_core = omap_hwmod_lookup("dss_core");
@@ -100,19 +121,21 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
100 pdata.opt_clock_available = opt_clock_available; 121 pdata.opt_clock_available = opt_clock_available;
101 122
102 for (i = 0; i < oh_count; i++) { 123 for (i = 0; i < oh_count; i++) {
103 oh = omap_hwmod_lookup(oh_name[i]); 124 oh = omap_hwmod_lookup(curr_dss_hwmod[i].oh_name);
104 if (!oh) { 125 if (!oh) {
105 pr_err("Could not look up %s\n", oh_name[i]); 126 pr_err("Could not look up %s\n",
127 curr_dss_hwmod[i].oh_name);
106 return -ENODEV; 128 return -ENODEV;
107 } 129 }
108 130
109 od = omap_device_build(dev_name[i], -1, oh, &pdata, 131 od = omap_device_build(curr_dss_hwmod[i].dev_name,
132 curr_dss_hwmod[i].id, oh, &pdata,
110 sizeof(struct omap_display_platform_data), 133 sizeof(struct omap_display_platform_data),
111 omap_dss_latency, 134 omap_dss_latency,
112 ARRAY_SIZE(omap_dss_latency), 0); 135 ARRAY_SIZE(omap_dss_latency), 0);
113 136
114 if (WARN((IS_ERR(od)), "Could not build omap_device for %s\n", 137 if (WARN((IS_ERR(od)), "Could not build omap_device for %s\n",
115 oh_name[i])) 138 curr_dss_hwmod[i].oh_name))
116 return -ENODEV; 139 return -ENODEV;
117 } 140 }
118 omap_display_device.dev.platform_data = board_data; 141 omap_display_device.dev.platform_data = board_data;
diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h
index d20bd9c1a106..775fdc3b000b 100644
--- a/arch/arm/mach-omap2/include/mach/board-zoom.h
+++ b/arch/arm/mach-omap2/include/mach/board-zoom.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Defines for zoom boards 2 * Defines for zoom boards
3 */ 3 */
4#include <plat/display.h> 4#include <video/omapdss.h>
5 5
6#define ZOOM_NAND_CS 0 6#define ZOOM_NAND_CS 0
7 7
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index e2507f66f9d5..612b27000c3e 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -30,6 +30,11 @@ obj-$(CONFIG_ARCH_SH7377) += entry-intc.o
30obj-$(CONFIG_ARCH_SH7372) += entry-intc.o 30obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
31obj-$(CONFIG_ARCH_SH73A0) += entry-gic.o 31obj-$(CONFIG_ARCH_SH73A0) += entry-gic.o
32 32
33# PM objects
34obj-$(CONFIG_SUSPEND) += suspend.o
35obj-$(CONFIG_CPU_IDLE) += cpuidle.o
36obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o
37
33# Board objects 38# Board objects
34obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o 39obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o
35obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o 40obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 3e6f0aab460b..c95258c274c1 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -34,6 +34,8 @@
34#include <linux/input/sh_keysc.h> 34#include <linux/input/sh_keysc.h>
35#include <linux/mmc/host.h> 35#include <linux/mmc/host.h>
36#include <linux/mmc/sh_mmcif.h> 36#include <linux/mmc/sh_mmcif.h>
37#include <linux/mmc/sh_mobile_sdhi.h>
38#include <linux/mfd/tmio.h>
37#include <linux/sh_clk.h> 39#include <linux/sh_clk.h>
38#include <video/sh_mobile_lcdc.h> 40#include <video/sh_mobile_lcdc.h>
39#include <video/sh_mipi_dsi.h> 41#include <video/sh_mipi_dsi.h>
@@ -156,10 +158,19 @@ static struct resource sh_mmcif_resources[] = {
156 }, 158 },
157}; 159};
158 160
161static struct sh_mmcif_dma sh_mmcif_dma = {
162 .chan_priv_rx = {
163 .slave_id = SHDMA_SLAVE_MMCIF_RX,
164 },
165 .chan_priv_tx = {
166 .slave_id = SHDMA_SLAVE_MMCIF_TX,
167 },
168};
159static struct sh_mmcif_plat_data sh_mmcif_platdata = { 169static struct sh_mmcif_plat_data sh_mmcif_platdata = {
160 .sup_pclk = 0, 170 .sup_pclk = 0,
161 .ocr = MMC_VDD_165_195, 171 .ocr = MMC_VDD_165_195,
162 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, 172 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
173 .dma = &sh_mmcif_dma,
163}; 174};
164 175
165static struct platform_device mmc_device = { 176static struct platform_device mmc_device = {
@@ -296,11 +307,13 @@ static struct platform_device lcdc0_device = {
296/* MIPI-DSI */ 307/* MIPI-DSI */
297static struct resource mipidsi0_resources[] = { 308static struct resource mipidsi0_resources[] = {
298 [0] = { 309 [0] = {
310 .name = "DSI0",
299 .start = 0xfeab0000, 311 .start = 0xfeab0000,
300 .end = 0xfeab3fff, 312 .end = 0xfeab3fff,
301 .flags = IORESOURCE_MEM, 313 .flags = IORESOURCE_MEM,
302 }, 314 },
303 [1] = { 315 [1] = {
316 .name = "DSI0",
304 .start = 0xfeab4000, 317 .start = 0xfeab4000,
305 .end = 0xfeab7fff, 318 .end = 0xfeab7fff,
306 .flags = IORESOURCE_MEM, 319 .flags = IORESOURCE_MEM,
@@ -325,6 +338,89 @@ static struct platform_device mipidsi0_device = {
325 }, 338 },
326}; 339};
327 340
341static struct sh_mobile_sdhi_info sdhi0_info = {
342 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
343 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
344 .tmio_caps = MMC_CAP_SD_HIGHSPEED,
345 .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
346};
347
348static struct resource sdhi0_resources[] = {
349 [0] = {
350 .name = "SDHI0",
351 .start = 0xee100000,
352 .end = 0xee1000ff,
353 .flags = IORESOURCE_MEM,
354 },
355 [1] = {
356 .start = gic_spi(83),
357 .flags = IORESOURCE_IRQ,
358 },
359 [2] = {
360 .start = gic_spi(84),
361 .flags = IORESOURCE_IRQ,
362 },
363 [3] = {
364 .start = gic_spi(85),
365 .flags = IORESOURCE_IRQ,
366 },
367};
368
369static struct platform_device sdhi0_device = {
370 .name = "sh_mobile_sdhi",
371 .id = 0,
372 .num_resources = ARRAY_SIZE(sdhi0_resources),
373 .resource = sdhi0_resources,
374 .dev = {
375 .platform_data = &sdhi0_info,
376 },
377};
378
379void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
380{
381 gpio_set_value(GPIO_PORT114, state);
382}
383
384static struct sh_mobile_sdhi_info sh_sdhi1_platdata = {
385 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
386 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
387 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
388 .tmio_caps = MMC_CAP_NONREMOVABLE,
389 .tmio_ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
390 .set_pwr = ag5evm_sdhi1_set_pwr,
391};
392
393static struct resource sdhi1_resources[] = {
394 [0] = {
395 .name = "SDHI1",
396 .start = 0xee120000,
397 .end = 0xee1200ff,
398 .flags = IORESOURCE_MEM,
399 },
400 [1] = {
401 .start = gic_spi(87),
402 .flags = IORESOURCE_IRQ,
403 },
404 [2] = {
405 .start = gic_spi(88),
406 .flags = IORESOURCE_IRQ,
407 },
408 [3] = {
409 .start = gic_spi(89),
410 .flags = IORESOURCE_IRQ,
411 },
412};
413
414static struct platform_device sdhi1_device = {
415 .name = "sh_mobile_sdhi",
416 .id = 1,
417 .dev = {
418 .platform_data = &sh_sdhi1_platdata,
419 },
420 .num_resources = ARRAY_SIZE(sdhi1_resources),
421 .resource = sdhi1_resources,
422};
423
328static struct platform_device *ag5evm_devices[] __initdata = { 424static struct platform_device *ag5evm_devices[] __initdata = {
329 &eth_device, 425 &eth_device,
330 &keysc_device, 426 &keysc_device,
@@ -333,6 +429,8 @@ static struct platform_device *ag5evm_devices[] __initdata = {
333 &irda_device, 429 &irda_device,
334 &lcdc0_device, 430 &lcdc0_device,
335 &mipidsi0_device, 431 &mipidsi0_device,
432 &sdhi0_device,
433 &sdhi1_device,
336}; 434};
337 435
338static struct map_desc ag5evm_io_desc[] __initdata = { 436static struct map_desc ag5evm_io_desc[] __initdata = {
@@ -454,6 +552,26 @@ static void __init ag5evm_init(void)
454 /* MIPI-DSI clock setup */ 552 /* MIPI-DSI clock setup */
455 __raw_writel(0x2a809010, DSI0PHYCR); 553 __raw_writel(0x2a809010, DSI0PHYCR);
456 554
555 /* enable SDHI0 on CN15 [SD I/F] */
556 gpio_request(GPIO_FN_SDHICD0, NULL);
557 gpio_request(GPIO_FN_SDHIWP0, NULL);
558 gpio_request(GPIO_FN_SDHICMD0, NULL);
559 gpio_request(GPIO_FN_SDHICLK0, NULL);
560 gpio_request(GPIO_FN_SDHID0_3, NULL);
561 gpio_request(GPIO_FN_SDHID0_2, NULL);
562 gpio_request(GPIO_FN_SDHID0_1, NULL);
563 gpio_request(GPIO_FN_SDHID0_0, NULL);
564
565 /* enable SDHI1 on CN4 [WLAN I/F] */
566 gpio_request(GPIO_FN_SDHICLK1, NULL);
567 gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
568 gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
569 gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
570 gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
571 gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
572 gpio_request(GPIO_PORT114, "sdhi1_power");
573 gpio_direction_output(GPIO_PORT114, 0);
574
457#ifdef CONFIG_CACHE_L2X0 575#ifdef CONFIG_CACHE_L2X0
458 /* Shared attribute override enable, 64K*8way */ 576 /* Shared attribute override enable, 64K*8way */
459 l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff); 577 l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff);
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 1e35fa976d64..08acb6ec8139 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -316,8 +316,16 @@ static struct resource sdhi0_resources[] = {
316 .flags = IORESOURCE_MEM, 316 .flags = IORESOURCE_MEM,
317 }, 317 },
318 [1] = { 318 [1] = {
319 .start = evt2irq(0x0e00) /* SDHI0 */, 319 .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
320 .flags = IORESOURCE_IRQ, 320 .flags = IORESOURCE_IRQ,
321 },
322 [2] = {
323 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
324 .flags = IORESOURCE_IRQ,
325 },
326 [3] = {
327 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
328 .flags = IORESOURCE_IRQ,
321 }, 329 },
322}; 330};
323 331
@@ -349,8 +357,16 @@ static struct resource sdhi1_resources[] = {
349 .flags = IORESOURCE_MEM, 357 .flags = IORESOURCE_MEM,
350 }, 358 },
351 [1] = { 359 [1] = {
352 .start = evt2irq(0x0e80), 360 .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
353 .flags = IORESOURCE_IRQ, 361 .flags = IORESOURCE_IRQ,
362 },
363 [2] = {
364 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
365 .flags = IORESOURCE_IRQ,
366 },
367 [3] = {
368 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
369 .flags = IORESOURCE_IRQ,
354 }, 370 },
355}; 371};
356 372
@@ -980,11 +996,6 @@ static void __init hdmi_init_pm_clock(void)
980 goto out; 996 goto out;
981 } 997 }
982 998
983 ret = clk_enable(&sh7372_pllc2_clk);
984 if (ret < 0) {
985 pr_err("Cannot enable pllc2 clock\n");
986 goto out;
987 }
988 pr_debug("PLLC2 set frequency %lu\n", rate); 999 pr_debug("PLLC2 set frequency %lu\n", rate);
989 1000
990 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); 1001 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
@@ -1343,6 +1354,7 @@ static void __init ap4evb_init(void)
1343 1354
1344 hdmi_init_pm_clock(); 1355 hdmi_init_pm_clock();
1345 fsi_init_pm_clock(); 1356 fsi_init_pm_clock();
1357 sh7372_pm_init();
1346} 1358}
1347 1359
1348static void __init ap4evb_timer_init(void) 1360static void __init ap4evb_timer_init(void)
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index c87a7b7c5832..8e3c5559f27f 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -205,7 +205,7 @@ static struct resource sdhi0_resources[] = {
205 [0] = { 205 [0] = {
206 .name = "SDHI0", 206 .name = "SDHI0",
207 .start = 0xe6d50000, 207 .start = 0xe6d50000,
208 .end = 0xe6d50nff, 208 .end = 0xe6d500ff,
209 .flags = IORESOURCE_MEM, 209 .flags = IORESOURCE_MEM,
210 }, 210 },
211 [1] = { 211 [1] = {
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 7da2ca24229d..448ddbe43335 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -43,6 +43,7 @@
43#include <linux/sh_intc.h> 43#include <linux/sh_intc.h>
44#include <linux/tca6416_keypad.h> 44#include <linux/tca6416_keypad.h>
45#include <linux/usb/r8a66597.h> 45#include <linux/usb/r8a66597.h>
46#include <linux/usb/renesas_usbhs.h>
46 47
47#include <video/sh_mobile_hdmi.h> 48#include <video/sh_mobile_hdmi.h>
48#include <video/sh_mobile_lcdc.h> 49#include <video/sh_mobile_lcdc.h>
@@ -143,7 +144,30 @@
143 * open | external VBUS | Function 144 * open | external VBUS | Function
144 * 145 *
145 * *1 146 * *1
146 * CN31 is used as Host in Linux. 147 * CN31 is used as
148 * CONFIG_USB_R8A66597_HCD Host
149 * CONFIG_USB_RENESAS_USBHS Function
150 *
151 * CAUTION
152 *
153 * renesas_usbhs driver can use external interrupt mode
154 * (which come from USB-PHY) or autonomy mode (it use own interrupt)
155 * for detecting connection/disconnection when Function.
156 * USB will be power OFF while it has been disconnecting
157 * if external interrupt mode, and it is always power ON if autonomy mode,
158 *
159 * mackerel can not use external interrupt (IRQ7-PORT167) mode on "USB0",
160 * because Touchscreen is using IRQ7-PORT40.
161 * It is impossible to use IRQ7 demux on this board.
162 *
163 * We can use external interrupt mode USB-Function on "USB1".
164 * USB1 can become Host by r8a66597, and become Function by renesas_usbhs.
165 * But don't select both drivers in same time.
166 * These uses same IRQ number for request_irq(), and aren't supporting
167 * IRQF_SHARD / IORESOURCE_IRQ_SHAREABLE.
168 *
169 * Actually these are old/new version of USB driver.
170 * This mean its register will be broken if it supports SHARD IRQ,
147 */ 171 */
148 172
149/* 173/*
@@ -185,6 +209,7 @@
185 * FIXME !! 209 * FIXME !!
186 * 210 *
187 * gpio_no_direction 211 * gpio_no_direction
212 * gpio_pull_down
188 * are quick_hack. 213 * are quick_hack.
189 * 214 *
190 * current gpio frame work doesn't have 215 * current gpio frame work doesn't have
@@ -196,6 +221,16 @@ static void __init gpio_no_direction(u32 addr)
196 __raw_writeb(0x00, addr); 221 __raw_writeb(0x00, addr);
197} 222}
198 223
224static void __init gpio_pull_down(u32 addr)
225{
226 u8 data = __raw_readb(addr);
227
228 data &= 0x0F;
229 data |= 0xA0;
230
231 __raw_writeb(data, addr);
232}
233
199/* MTD */ 234/* MTD */
200static struct mtd_partition nor_flash_partitions[] = { 235static struct mtd_partition nor_flash_partitions[] = {
201 { 236 {
@@ -458,12 +493,6 @@ static void __init hdmi_init_pm_clock(void)
458 goto out; 493 goto out;
459 } 494 }
460 495
461 ret = clk_enable(&sh7372_pllc2_clk);
462 if (ret < 0) {
463 pr_err("Cannot enable pllc2 clock\n");
464 goto out;
465 }
466
467 pr_debug("PLLC2 set frequency %lu\n", rate); 496 pr_debug("PLLC2 set frequency %lu\n", rate);
468 497
469 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); 498 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
@@ -515,6 +544,157 @@ static struct platform_device usb1_host_device = {
515 .resource = usb1_host_resources, 544 .resource = usb1_host_resources,
516}; 545};
517 546
547/* USB1 (Function) */
548#define USB_PHY_MODE (1 << 4)
549#define USB_PHY_INT_EN ((1 << 3) | (1 << 2))
550#define USB_PHY_ON (1 << 1)
551#define USB_PHY_OFF (1 << 0)
552#define USB_PHY_INT_CLR (USB_PHY_ON | USB_PHY_OFF)
553
554struct usbhs_private {
555 unsigned int irq;
556 unsigned int usbphyaddr;
557 unsigned int usbcrcaddr;
558 struct renesas_usbhs_platform_info info;
559};
560
561#define usbhs_get_priv(pdev) \
562 container_of(renesas_usbhs_get_info(pdev), \
563 struct usbhs_private, info)
564
565#define usbhs_is_connected(priv) \
566 (!((1 << 7) & __raw_readw(priv->usbcrcaddr)))
567
568static int usbhs1_get_id(struct platform_device *pdev)
569{
570 return USBHS_GADGET;
571}
572
573static int usbhs1_get_vbus(struct platform_device *pdev)
574{
575 return usbhs_is_connected(usbhs_get_priv(pdev));
576}
577
578static irqreturn_t usbhs1_interrupt(int irq, void *data)
579{
580 struct platform_device *pdev = data;
581 struct usbhs_private *priv = usbhs_get_priv(pdev);
582
583 dev_dbg(&pdev->dev, "%s\n", __func__);
584
585 renesas_usbhs_call_notify_hotplug(pdev);
586
587 /* clear status */
588 __raw_writew(__raw_readw(priv->usbphyaddr) | USB_PHY_INT_CLR,
589 priv->usbphyaddr);
590
591 return IRQ_HANDLED;
592}
593
594static int usbhs1_hardware_init(struct platform_device *pdev)
595{
596 struct usbhs_private *priv = usbhs_get_priv(pdev);
597 int ret;
598
599 irq_set_irq_type(priv->irq, IRQ_TYPE_LEVEL_HIGH);
600
601 /* clear interrupt status */
602 __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr);
603
604 ret = request_irq(priv->irq, usbhs1_interrupt, 0,
605 dev_name(&pdev->dev), pdev);
606 if (ret) {
607 dev_err(&pdev->dev, "request_irq err\n");
608 return ret;
609 }
610
611 /* enable USB phy interrupt */
612 __raw_writew(USB_PHY_MODE | USB_PHY_INT_EN, priv->usbphyaddr);
613
614 return 0;
615}
616
617static void usbhs1_hardware_exit(struct platform_device *pdev)
618{
619 struct usbhs_private *priv = usbhs_get_priv(pdev);
620
621 /* clear interrupt status */
622 __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr);
623
624 free_irq(priv->irq, pdev);
625}
626
627static void usbhs1_phy_reset(struct platform_device *pdev)
628{
629 struct usbhs_private *priv = usbhs_get_priv(pdev);
630
631 /* init phy */
632 __raw_writew(0x8a0a, priv->usbcrcaddr);
633}
634
635static u32 usbhs1_pipe_cfg[] = {
636 USB_ENDPOINT_XFER_CONTROL,
637 USB_ENDPOINT_XFER_ISOC,
638 USB_ENDPOINT_XFER_ISOC,
639 USB_ENDPOINT_XFER_BULK,
640 USB_ENDPOINT_XFER_BULK,
641 USB_ENDPOINT_XFER_BULK,
642 USB_ENDPOINT_XFER_INT,
643 USB_ENDPOINT_XFER_INT,
644 USB_ENDPOINT_XFER_INT,
645 USB_ENDPOINT_XFER_BULK,
646 USB_ENDPOINT_XFER_BULK,
647 USB_ENDPOINT_XFER_BULK,
648 USB_ENDPOINT_XFER_BULK,
649 USB_ENDPOINT_XFER_BULK,
650 USB_ENDPOINT_XFER_BULK,
651 USB_ENDPOINT_XFER_BULK,
652};
653
654static struct usbhs_private usbhs1_private = {
655 .irq = evt2irq(0x0300), /* IRQ8 */
656 .usbphyaddr = 0xE60581E2, /* USBPHY1INTAP */
657 .usbcrcaddr = 0xE6058130, /* USBCR4 */
658 .info = {
659 .platform_callback = {
660 .hardware_init = usbhs1_hardware_init,
661 .hardware_exit = usbhs1_hardware_exit,
662 .phy_reset = usbhs1_phy_reset,
663 .get_id = usbhs1_get_id,
664 .get_vbus = usbhs1_get_vbus,
665 },
666 .driver_param = {
667 .buswait_bwait = 4,
668 .pipe_type = usbhs1_pipe_cfg,
669 .pipe_size = ARRAY_SIZE(usbhs1_pipe_cfg),
670 },
671 },
672};
673
674static struct resource usbhs1_resources[] = {
675 [0] = {
676 .name = "USBHS",
677 .start = 0xE68B0000,
678 .end = 0xE68B00E6 - 1,
679 .flags = IORESOURCE_MEM,
680 },
681 [1] = {
682 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
683 .flags = IORESOURCE_IRQ,
684 },
685};
686
687static struct platform_device usbhs1_device = {
688 .name = "renesas_usbhs",
689 .id = 1,
690 .dev = {
691 .platform_data = &usbhs1_private.info,
692 },
693 .num_resources = ARRAY_SIZE(usbhs1_resources),
694 .resource = usbhs1_resources,
695};
696
697
518/* LED */ 698/* LED */
519static struct gpio_led mackerel_leds[] = { 699static struct gpio_led mackerel_leds[] = {
520 { 700 {
@@ -690,7 +870,15 @@ static struct resource sdhi0_resources[] = {
690 .flags = IORESOURCE_MEM, 870 .flags = IORESOURCE_MEM,
691 }, 871 },
692 [1] = { 872 [1] = {
693 .start = evt2irq(0x0e00) /* SDHI0 */, 873 .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
874 .flags = IORESOURCE_IRQ,
875 },
876 [2] = {
877 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
878 .flags = IORESOURCE_IRQ,
879 },
880 [3] = {
881 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
694 .flags = IORESOURCE_IRQ, 882 .flags = IORESOURCE_IRQ,
695 }, 883 },
696}; 884};
@@ -705,7 +893,7 @@ static struct platform_device sdhi0_device = {
705 }, 893 },
706}; 894};
707 895
708#if !defined(CONFIG_MMC_SH_MMCIF) 896#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
709/* SDHI1 */ 897/* SDHI1 */
710static struct sh_mobile_sdhi_info sdhi1_info = { 898static struct sh_mobile_sdhi_info sdhi1_info = {
711 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, 899 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
@@ -725,7 +913,15 @@ static struct resource sdhi1_resources[] = {
725 .flags = IORESOURCE_MEM, 913 .flags = IORESOURCE_MEM,
726 }, 914 },
727 [1] = { 915 [1] = {
728 .start = evt2irq(0x0e80), 916 .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
917 .flags = IORESOURCE_IRQ,
918 },
919 [2] = {
920 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
921 .flags = IORESOURCE_IRQ,
922 },
923 [3] = {
924 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
729 .flags = IORESOURCE_IRQ, 925 .flags = IORESOURCE_IRQ,
730 }, 926 },
731}; 927};
@@ -768,7 +964,15 @@ static struct resource sdhi2_resources[] = {
768 .flags = IORESOURCE_MEM, 964 .flags = IORESOURCE_MEM,
769 }, 965 },
770 [1] = { 966 [1] = {
771 .start = evt2irq(0x1200), 967 .start = evt2irq(0x1200), /* SDHI2_SDHI2I0 */
968 .flags = IORESOURCE_IRQ,
969 },
970 [2] = {
971 .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */
972 .flags = IORESOURCE_IRQ,
973 },
974 [3] = {
975 .start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */
772 .flags = IORESOURCE_IRQ, 976 .flags = IORESOURCE_IRQ,
773 }, 977 },
774}; 978};
@@ -803,6 +1007,15 @@ static struct resource sh_mmcif_resources[] = {
803 }, 1007 },
804}; 1008};
805 1009
1010static struct sh_mmcif_dma sh_mmcif_dma = {
1011 .chan_priv_rx = {
1012 .slave_id = SHDMA_SLAVE_MMCIF_RX,
1013 },
1014 .chan_priv_tx = {
1015 .slave_id = SHDMA_SLAVE_MMCIF_TX,
1016 },
1017};
1018
806static struct sh_mmcif_plat_data sh_mmcif_plat = { 1019static struct sh_mmcif_plat_data sh_mmcif_plat = {
807 .sup_pclk = 0, 1020 .sup_pclk = 0,
808 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, 1021 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
@@ -810,6 +1023,7 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
810 MMC_CAP_8_BIT_DATA | 1023 MMC_CAP_8_BIT_DATA |
811 MMC_CAP_NEEDS_POLL, 1024 MMC_CAP_NEEDS_POLL,
812 .get_cd = slot_cn7_get_cd, 1025 .get_cd = slot_cn7_get_cd,
1026 .dma = &sh_mmcif_dma,
813}; 1027};
814 1028
815static struct platform_device sh_mmcif_device = { 1029static struct platform_device sh_mmcif_device = {
@@ -858,37 +1072,23 @@ static struct soc_camera_link camera_link = {
858 .priv = &camera_info, 1072 .priv = &camera_info,
859}; 1073};
860 1074
861static void dummy_release(struct device *dev) 1075static struct platform_device *camera_device;
1076
1077static void mackerel_camera_release(struct device *dev)
862{ 1078{
1079 soc_camera_platform_release(&camera_device);
863} 1080}
864 1081
865static struct platform_device camera_device = {
866 .name = "soc_camera_platform",
867 .dev = {
868 .platform_data = &camera_info,
869 .release = dummy_release,
870 },
871};
872
873static int mackerel_camera_add(struct soc_camera_link *icl, 1082static int mackerel_camera_add(struct soc_camera_link *icl,
874 struct device *dev) 1083 struct device *dev)
875{ 1084{
876 if (icl != &camera_link) 1085 return soc_camera_platform_add(icl, dev, &camera_device, &camera_link,
877 return -ENODEV; 1086 mackerel_camera_release, 0);
878
879 camera_info.dev = dev;
880
881 return platform_device_register(&camera_device);
882} 1087}
883 1088
884static void mackerel_camera_del(struct soc_camera_link *icl) 1089static void mackerel_camera_del(struct soc_camera_link *icl)
885{ 1090{
886 if (icl != &camera_link) 1091 soc_camera_platform_del(icl, camera_device, &camera_link);
887 return;
888
889 platform_device_unregister(&camera_device);
890 memset(&camera_device.dev.kobj, 0,
891 sizeof(camera_device.dev.kobj));
892} 1092}
893 1093
894static struct sh_mobile_ceu_info sh_mobile_ceu_info = { 1094static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
@@ -935,12 +1135,13 @@ static struct platform_device *mackerel_devices[] __initdata = {
935 &smc911x_device, 1135 &smc911x_device,
936 &lcdc_device, 1136 &lcdc_device,
937 &usb1_host_device, 1137 &usb1_host_device,
1138 &usbhs1_device,
938 &leds_device, 1139 &leds_device,
939 &fsi_device, 1140 &fsi_device,
940 &fsi_ak4643_device, 1141 &fsi_ak4643_device,
941 &fsi_hdmi_device, 1142 &fsi_hdmi_device,
942 &sdhi0_device, 1143 &sdhi0_device,
943#if !defined(CONFIG_MMC_SH_MMCIF) 1144#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
944 &sdhi1_device, 1145 &sdhi1_device,
945#endif 1146#endif
946 &sdhi2_device, 1147 &sdhi2_device,
@@ -1030,6 +1231,7 @@ static void __init mackerel_map_io(void)
1030 1231
1031#define GPIO_PORT9CR 0xE6051009 1232#define GPIO_PORT9CR 0xE6051009
1032#define GPIO_PORT10CR 0xE605100A 1233#define GPIO_PORT10CR 0xE605100A
1234#define GPIO_PORT168CR 0xE60520A8
1033#define SRCR4 0xe61580bc 1235#define SRCR4 0xe61580bc
1034#define USCCR1 0xE6058144 1236#define USCCR1 0xE6058144
1035static void __init mackerel_init(void) 1237static void __init mackerel_init(void)
@@ -1088,6 +1290,7 @@ static void __init mackerel_init(void)
1088 gpio_request(GPIO_FN_OVCN_1_114, NULL); 1290 gpio_request(GPIO_FN_OVCN_1_114, NULL);
1089 gpio_request(GPIO_FN_EXTLP_1, NULL); 1291 gpio_request(GPIO_FN_EXTLP_1, NULL);
1090 gpio_request(GPIO_FN_OVCN2_1, NULL); 1292 gpio_request(GPIO_FN_OVCN2_1, NULL);
1293 gpio_pull_down(GPIO_PORT168CR);
1091 1294
1092 /* setup USB phy */ 1295 /* setup USB phy */
1093 __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */ 1296 __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */
@@ -1140,7 +1343,7 @@ static void __init mackerel_init(void)
1140 gpio_request(GPIO_FN_SDHID0_1, NULL); 1343 gpio_request(GPIO_FN_SDHID0_1, NULL);
1141 gpio_request(GPIO_FN_SDHID0_0, NULL); 1344 gpio_request(GPIO_FN_SDHID0_0, NULL);
1142 1345
1143#if !defined(CONFIG_MMC_SH_MMCIF) 1346#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
1144 /* enable SDHI1 */ 1347 /* enable SDHI1 */
1145 gpio_request(GPIO_FN_SDHICMD1, NULL); 1348 gpio_request(GPIO_FN_SDHICMD1, NULL);
1146 gpio_request(GPIO_FN_SDHICLK1, NULL); 1349 gpio_request(GPIO_FN_SDHICLK1, NULL);
@@ -1216,6 +1419,7 @@ static void __init mackerel_init(void)
1216 platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices)); 1419 platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
1217 1420
1218 hdmi_init_pm_clock(); 1421 hdmi_init_pm_clock();
1422 sh7372_pm_init();
1219} 1423}
1220 1424
1221static void __init mackerel_timer_init(void) 1425static void __init mackerel_timer_init(void)
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index e9731b5a73ed..d17eb66f4ac2 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -44,6 +44,11 @@
44#define DSI1PCKCR 0xe6150098 44#define DSI1PCKCR 0xe6150098
45#define PLLC01CR 0xe6150028 45#define PLLC01CR 0xe6150028
46#define PLLC2CR 0xe615002c 46#define PLLC2CR 0xe615002c
47#define RMSTPCR0 0xe6150110
48#define RMSTPCR1 0xe6150114
49#define RMSTPCR2 0xe6150118
50#define RMSTPCR3 0xe615011c
51#define RMSTPCR4 0xe6150120
47#define SMSTPCR0 0xe6150130 52#define SMSTPCR0 0xe6150130
48#define SMSTPCR1 0xe6150134 53#define SMSTPCR1 0xe6150134
49#define SMSTPCR2 0xe6150138 54#define SMSTPCR2 0xe6150138
@@ -421,9 +426,6 @@ static unsigned long fsidiv_recalc(struct clk *clk)
421 426
422 value = __raw_readl(clk->mapping->base); 427 value = __raw_readl(clk->mapping->base);
423 428
424 if ((value & 0x3) != 0x3)
425 return 0;
426
427 value >>= 16; 429 value >>= 16;
428 if (value < 2) 430 if (value < 2)
429 return 0; 431 return 0;
@@ -504,7 +506,7 @@ static struct clk *late_main_clks[] = {
504enum { MSTP001, 506enum { MSTP001,
505 MSTP131, MSTP130, 507 MSTP131, MSTP130,
506 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, 508 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
507 MSTP118, MSTP117, MSTP116, 509 MSTP118, MSTP117, MSTP116, MSTP113,
508 MSTP106, MSTP101, MSTP100, 510 MSTP106, MSTP101, MSTP100,
509 MSTP223, 511 MSTP223,
510 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, 512 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
@@ -527,6 +529,7 @@ static struct clk mstp_clks[MSTP_NR] = {
527 [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */ 529 [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
528 [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */ 530 [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
529 [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */ 531 [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
532 [MSTP113] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 13, 0), /* MERAM */
530 [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */ 533 [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
531 [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */ 534 [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
532 [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ 535 [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
@@ -617,6 +620,7 @@ static struct clk_lookup lookups[] = {
617 CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */ 620 CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
618 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */ 621 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
619 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */ 622 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
623 CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[MSTP113]), /* MERAM */
620 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */ 624 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
621 CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */ 625 CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
622 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */ 626 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
@@ -634,6 +638,7 @@ static struct clk_lookup lookups[] = {
634 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */ 638 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
635 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */ 639 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
636 CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */ 640 CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */
641 CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP322]), /* USB0 */
637 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ 642 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
638 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ 643 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
639 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */ 644 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
@@ -644,6 +649,7 @@ static struct clk_lookup lookups[] = {
644 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */ 649 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
645 CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */ 650 CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
646 CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */ 651 CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
652 CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
647 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ 653 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
648 654
649 CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]), 655 CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
@@ -655,6 +661,13 @@ void __init sh7372_clock_init(void)
655{ 661{
656 int k, ret = 0; 662 int k, ret = 0;
657 663
664 /* make sure MSTP bits on the RT/SH4AL-DSP side are off */
665 __raw_writel(0xe4ef8087, RMSTPCR0);
666 __raw_writel(0xffffffff, RMSTPCR1);
667 __raw_writel(0x37c7f7ff, RMSTPCR2);
668 __raw_writel(0xffffffff, RMSTPCR3);
669 __raw_writel(0xffe0fffd, RMSTPCR4);
670
658 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 671 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
659 ret = clk_register(main_clks[k]); 672 ret = clk_register(main_clks[k]);
660 673
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 7e58904c1c8c..bcacb1e8cf85 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -266,7 +266,8 @@ enum { MSTP001,
266 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100, 266 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
267 MSTP219, 267 MSTP219,
268 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, 268 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
269 MSTP331, MSTP329, MSTP325, MSTP323, MSTP312, 269 MSTP331, MSTP329, MSTP325, MSTP323, MSTP318,
270 MSTP314, MSTP313, MSTP312, MSTP311,
270 MSTP411, MSTP410, MSTP403, 271 MSTP411, MSTP410, MSTP403,
271 MSTP_NR }; 272 MSTP_NR };
272 273
@@ -295,7 +296,11 @@ static struct clk mstp_clks[MSTP_NR] = {
295 [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ 296 [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
296 [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */ 297 [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
297 [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */ 298 [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
299 [MSTP318] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* SY-DMAC */
300 [MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */
301 [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */
298 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */ 302 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
303 [MSTP311] = MSTP(&div6_clks[DIV6_SDHI2], SMSTPCR3, 11, 0), /* SDHI2 */
299 [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */ 304 [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
300 [MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */ 305 [MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
301 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */ 306 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
@@ -313,6 +318,9 @@ static struct clk_lookup lookups[] = {
313 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), 318 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
314 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]), 319 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
315 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]), 320 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
321 CLKDEV_CON_ID("sdhi0_clk", &div6_clks[DIV6_SDHI0]),
322 CLKDEV_CON_ID("sdhi1_clk", &div6_clks[DIV6_SDHI1]),
323 CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]),
316 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]), 324 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
317 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), 325 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
318 CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), 326 CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
@@ -341,7 +349,11 @@ static struct clk_lookup lookups[] = {
341 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ 349 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
342 CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */ 350 CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
343 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ 351 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
352 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP318]), /* SY-DMAC */
353 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
354 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
344 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ 355 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
356 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
345 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */ 357 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
346 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */ 358 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
347 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ 359 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
@@ -351,6 +363,11 @@ void __init sh73a0_clock_init(void)
351{ 363{
352 int k, ret = 0; 364 int k, ret = 0;
353 365
366 /* Set SDHI clocks to a known state */
367 __raw_writel(0x108, SD0CKCR);
368 __raw_writel(0x108, SD1CKCR);
369 __raw_writel(0x108, SD2CKCR);
370
354 /* detect main clock parent */ 371 /* detect main clock parent */
355 switch ((__raw_readl(CKSCR) >> 24) & 0x03) { 372 switch ((__raw_readl(CKSCR) >> 24) & 0x03) {
356 case 0: 373 case 0:
diff --git a/arch/arm/mach-shmobile/cpuidle.c b/arch/arm/mach-shmobile/cpuidle.c
new file mode 100644
index 000000000000..2e44f11f592e
--- /dev/null
+++ b/arch/arm/mach-shmobile/cpuidle.c
@@ -0,0 +1,92 @@
1/*
2 * CPUIdle support code for SH-Mobile ARM
3 *
4 * Copyright (C) 2011 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/pm.h>
12#include <linux/cpuidle.h>
13#include <linux/suspend.h>
14#include <linux/module.h>
15#include <linux/err.h>
16#include <asm/system.h>
17#include <asm/io.h>
18
19static void shmobile_enter_wfi(void)
20{
21 cpu_do_idle();
22}
23
24void (*shmobile_cpuidle_modes[CPUIDLE_STATE_MAX])(void) = {
25 shmobile_enter_wfi, /* regular sleep mode */
26};
27
28static int shmobile_cpuidle_enter(struct cpuidle_device *dev,
29 struct cpuidle_state *state)
30{
31 ktime_t before, after;
32 int requested_state = state - &dev->states[0];
33
34 dev->last_state = &dev->states[requested_state];
35 before = ktime_get();
36
37 local_irq_disable();
38 local_fiq_disable();
39
40 shmobile_cpuidle_modes[requested_state]();
41
42 local_irq_enable();
43 local_fiq_enable();
44
45 after = ktime_get();
46 return ktime_to_ns(ktime_sub(after, before)) >> 10;
47}
48
49static struct cpuidle_device shmobile_cpuidle_dev;
50static struct cpuidle_driver shmobile_cpuidle_driver = {
51 .name = "shmobile_cpuidle",
52 .owner = THIS_MODULE,
53};
54
55void (*shmobile_cpuidle_setup)(struct cpuidle_device *dev);
56
57static int shmobile_cpuidle_init(void)
58{
59 struct cpuidle_device *dev = &shmobile_cpuidle_dev;
60 struct cpuidle_state *state;
61 int i;
62
63 cpuidle_register_driver(&shmobile_cpuidle_driver);
64
65 for (i = 0; i < CPUIDLE_STATE_MAX; i++) {
66 dev->states[i].name[0] = '\0';
67 dev->states[i].desc[0] = '\0';
68 dev->states[i].enter = shmobile_cpuidle_enter;
69 }
70
71 i = CPUIDLE_DRIVER_STATE_START;
72
73 state = &dev->states[i++];
74 snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
75 strncpy(state->desc, "WFI", CPUIDLE_DESC_LEN);
76 state->exit_latency = 1;
77 state->target_residency = 1 * 2;
78 state->power_usage = 3;
79 state->flags = 0;
80 state->flags |= CPUIDLE_FLAG_TIME_VALID;
81
82 dev->safe_state = state;
83 dev->state_count = i;
84
85 if (shmobile_cpuidle_setup)
86 shmobile_cpuidle_setup(dev);
87
88 cpuidle_register_device(dev);
89
90 return 0;
91}
92late_initcall(shmobile_cpuidle_init);
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index d4cec6b4c7d9..26079d933d91 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -24,4 +24,4 @@
24 .align 12 24 .align 12
25ENTRY(shmobile_secondary_vector) 25ENTRY(shmobile_secondary_vector)
26 ldr pc, 1f 26 ldr pc, 1f
271: .long secondary_startup - PAGE_OFFSET + PHYS_OFFSET 271: .long secondary_startup - PAGE_OFFSET + PLAT_PHYS_OFFSET
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 013ac0ee8256..06aecb31d9c7 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -8,6 +8,10 @@ struct clk;
8extern int clk_init(void); 8extern int clk_init(void);
9extern void shmobile_handle_irq_intc(struct pt_regs *); 9extern void shmobile_handle_irq_intc(struct pt_regs *);
10extern void shmobile_handle_irq_gic(struct pt_regs *); 10extern void shmobile_handle_irq_gic(struct pt_regs *);
11extern struct platform_suspend_ops shmobile_suspend_ops;
12struct cpuidle_device;
13extern void (*shmobile_cpuidle_modes[])(void);
14extern void (*shmobile_cpuidle_setup)(struct cpuidle_device *dev);
11 15
12extern void sh7367_init_irq(void); 16extern void sh7367_init_irq(void);
13extern void sh7367_add_early_devices(void); 17extern void sh7367_add_early_devices(void);
@@ -30,6 +34,9 @@ extern void sh7372_add_early_devices(void);
30extern void sh7372_add_standard_devices(void); 34extern void sh7372_add_standard_devices(void);
31extern void sh7372_clock_init(void); 35extern void sh7372_clock_init(void);
32extern void sh7372_pinmux_init(void); 36extern void sh7372_pinmux_init(void);
37extern void sh7372_pm_init(void);
38extern void sh7372_cpu_suspend(void);
39extern void sh7372_cpu_resume(void);
33extern struct clk sh7372_extal1_clk; 40extern struct clk sh7372_extal1_clk;
34extern struct clk sh7372_extal2_clk; 41extern struct clk sh7372_extal2_clk;
35 42
diff --git a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
index 3029aba38688..9f134dfeffdc 100644
--- a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
+++ b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
@@ -87,8 +87,7 @@ WAIT 1, 0xFE40009C
87ED 0xFE400354, 0x01AD8002 87ED 0xFE400354, 0x01AD8002
88 88
89LIST "SCIF0 - Serial port for earlyprintk" 89LIST "SCIF0 - Serial port for earlyprintk"
90EB 0xE6053098, 0x11
91EB 0xE6053098, 0xe1 90EB 0xE6053098, 0xe1
92EW 0xE6C40000, 0x0000 91EW 0xE6C40000, 0x0000
93EB 0xE6C40004, 0x19 92EB 0xE6C40004, 0x19
94EW 0xE6C40008, 0x3000 93EW 0xE6C40008, 0x0030
diff --git a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
index 3029aba38688..9f134dfeffdc 100644
--- a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
+++ b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
@@ -87,8 +87,7 @@ WAIT 1, 0xFE40009C
87ED 0xFE400354, 0x01AD8002 87ED 0xFE400354, 0x01AD8002
88 88
89LIST "SCIF0 - Serial port for earlyprintk" 89LIST "SCIF0 - Serial port for earlyprintk"
90EB 0xE6053098, 0x11
91EB 0xE6053098, 0xe1 90EB 0xE6053098, 0xe1
92EW 0xE6C40000, 0x0000 91EW 0xE6C40000, 0x0000
93EB 0xE6C40004, 0x19 92EB 0xE6C40004, 0x19
94EW 0xE6C40008, 0x3000 93EW 0xE6C40008, 0x0030
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index 5736efcca60c..df20d7670172 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -435,6 +435,7 @@ enum {
435 435
436/* DMA slave IDs */ 436/* DMA slave IDs */
437enum { 437enum {
438 SHDMA_SLAVE_INVALID,
438 SHDMA_SLAVE_SCIF0_TX, 439 SHDMA_SLAVE_SCIF0_TX,
439 SHDMA_SLAVE_SCIF0_RX, 440 SHDMA_SLAVE_SCIF0_RX,
440 SHDMA_SLAVE_SCIF1_TX, 441 SHDMA_SLAVE_SCIF1_TX,
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index ceb2cdc92bf9..216c3d695ef1 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -463,5 +463,35 @@ enum {
463 GPIO_FN_FSIAIBT_PU, 463 GPIO_FN_FSIAIBT_PU,
464 GPIO_FN_FSIAISLD_PU, 464 GPIO_FN_FSIAISLD_PU,
465}; 465};
466/* DMA slave IDs */
467enum {
468 SHDMA_SLAVE_INVALID,
469 SHDMA_SLAVE_SCIF0_TX,
470 SHDMA_SLAVE_SCIF0_RX,
471 SHDMA_SLAVE_SCIF1_TX,
472 SHDMA_SLAVE_SCIF1_RX,
473 SHDMA_SLAVE_SCIF2_TX,
474 SHDMA_SLAVE_SCIF2_RX,
475 SHDMA_SLAVE_SCIF3_TX,
476 SHDMA_SLAVE_SCIF3_RX,
477 SHDMA_SLAVE_SCIF4_TX,
478 SHDMA_SLAVE_SCIF4_RX,
479 SHDMA_SLAVE_SCIF5_TX,
480 SHDMA_SLAVE_SCIF5_RX,
481 SHDMA_SLAVE_SCIF6_TX,
482 SHDMA_SLAVE_SCIF6_RX,
483 SHDMA_SLAVE_SCIF7_TX,
484 SHDMA_SLAVE_SCIF7_RX,
485 SHDMA_SLAVE_SCIF8_TX,
486 SHDMA_SLAVE_SCIF8_RX,
487 SHDMA_SLAVE_SDHI0_TX,
488 SHDMA_SLAVE_SDHI0_RX,
489 SHDMA_SLAVE_SDHI1_TX,
490 SHDMA_SLAVE_SDHI1_RX,
491 SHDMA_SLAVE_SDHI2_TX,
492 SHDMA_SLAVE_SDHI2_RX,
493 SHDMA_SLAVE_MMCIF_TX,
494 SHDMA_SLAVE_MMCIF_RX,
495};
466 496
467#endif /* __ASM_SH73A0_H__ */ 497#endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 7a4960f9c1e3..3b28743c77eb 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -27,8 +27,6 @@
27 27
28enum { 28enum {
29 UNUSED_INTCA = 0, 29 UNUSED_INTCA = 0,
30 ENABLED,
31 DISABLED,
32 30
33 /* interrupt sources INTCA */ 31 /* interrupt sources INTCA */
34 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, 32 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
@@ -49,14 +47,14 @@ enum {
49 MSIOF2, MSIOF1, 47 MSIOF2, MSIOF1,
50 SCIFA4, SCIFA5, SCIFB, 48 SCIFA4, SCIFA5, SCIFB,
51 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 49 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
52 SDHI0, 50 SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3,
53 SDHI1, 51 SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2,
54 IRREM, 52 IRREM,
55 IRDA, 53 IRDA,
56 TPU0, 54 TPU0,
57 TTI20, 55 TTI20,
58 DDM, 56 DDM,
59 SDHI2, 57 SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3,
60 RWDT0, 58 RWDT0,
61 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3, 59 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
62 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR, 60 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
@@ -84,7 +82,7 @@ enum {
84 82
85 /* interrupt groups INTCA */ 83 /* interrupt groups INTCA */
86 DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT, 84 DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
87 AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1 85 AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2
88}; 86};
89 87
90static struct intc_vect intca_vectors[] __initdata = { 88static struct intc_vect intca_vectors[] __initdata = {
@@ -125,17 +123,17 @@ static struct intc_vect intca_vectors[] __initdata = {
125 INTC_VECT(SCIFB, 0x0d60), 123 INTC_VECT(SCIFB, 0x0d60),
126 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), 124 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
127 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), 125 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
128 INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20), 126 INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20),
129 INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60), 127 INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60),
130 INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0), 128 INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0),
131 INTC_VECT(SDHI1, 0x0ec0), 129 INTC_VECT(SDHI1_SDHI1I2, 0x0ec0),
132 INTC_VECT(IRREM, 0x0f60), 130 INTC_VECT(IRREM, 0x0f60),
133 INTC_VECT(IRDA, 0x0480), 131 INTC_VECT(IRDA, 0x0480),
134 INTC_VECT(TPU0, 0x04a0), 132 INTC_VECT(TPU0, 0x04a0),
135 INTC_VECT(TTI20, 0x1100), 133 INTC_VECT(TTI20, 0x1100),
136 INTC_VECT(DDM, 0x1140), 134 INTC_VECT(DDM, 0x1140),
137 INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220), 135 INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220),
138 INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260), 136 INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260),
139 INTC_VECT(RWDT0, 0x1280), 137 INTC_VECT(RWDT0, 0x1280),
140 INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020), 138 INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
141 INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060), 139 INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
@@ -195,6 +193,12 @@ static struct intc_group intca_groups[] __initdata = {
195 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, 193 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
196 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 194 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
197 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), 195 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
196 INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
197 SDHI0_SDHI0I2, SDHI0_SDHI0I3),
198 INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
199 SDHI1_SDHI1I2),
200 INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1,
201 SDHI2_SDHI2I2, SDHI2_SDHI2I3),
198 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), 202 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
199}; 203};
200 204
@@ -230,10 +234,10 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
230 { SCIFB, SCIFA5, SCIFA4, MSIOF1, 234 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
231 0, 0, MSIOF2, 0 } }, 235 0, 0, MSIOF2, 0 } },
232 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ 236 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
233 { DISABLED, ENABLED, ENABLED, ENABLED, 237 { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0,
234 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 238 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
235 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ 239 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
236 { 0, ENABLED, ENABLED, ENABLED, 240 { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0,
237 TTI20, USBHSDMAC0_USHDMI, 0, 0 } }, 241 TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
238 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ 242 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
239 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, 243 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
@@ -248,7 +252,7 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
248 { 0, 0, TPU0, 0, 252 { 0, 0, TPU0, 0,
249 0, 0, 0, 0 } }, 253 0, 0, 0, 0 } },
250 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ 254 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
251 { DISABLED, DISABLED, ENABLED, ENABLED, 255 { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0,
252 0, CMT3, 0, RWDT0 } }, 256 0, CMT3, 0, RWDT0 } },
253 { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */ 257 { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
254 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0, 258 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
@@ -354,14 +358,10 @@ static struct intc_mask_reg intca_ack_registers[] __initdata = {
354 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, 358 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
355}; 359};
356 360
357static struct intc_desc intca_desc __initdata = { 361static DECLARE_INTC_DESC_ACK(intca_desc, "sh7372-intca",
358 .name = "sh7372-intca", 362 intca_vectors, intca_groups,
359 .force_enable = ENABLED, 363 intca_mask_registers, intca_prio_registers,
360 .force_disable = DISABLED, 364 intca_sense_registers, intca_ack_registers);
361 .hw = INTC_HW_DESC(intca_vectors, intca_groups,
362 intca_mask_registers, intca_prio_registers,
363 intca_sense_registers, intca_ack_registers),
364};
365 365
366enum { 366enum {
367 UNUSED_INTCS = 0, 367 UNUSED_INTCS = 0,
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
new file mode 100644
index 000000000000..8e4aadf14c9f
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -0,0 +1,108 @@
1/*
2 * sh7372 Power management support
3 *
4 * Copyright (C) 2011 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/pm.h>
12#include <linux/suspend.h>
13#include <linux/cpuidle.h>
14#include <linux/module.h>
15#include <linux/list.h>
16#include <linux/err.h>
17#include <linux/slab.h>
18#include <asm/system.h>
19#include <asm/io.h>
20#include <asm/tlbflush.h>
21#include <mach/common.h>
22
23#define SMFRAM 0xe6a70000
24#define SYSTBCR 0xe6150024
25#define SBAR 0xe6180020
26#define APARMBAREA 0xe6f10020
27
28static void sh7372_enter_core_standby(void)
29{
30 void __iomem *smfram = (void __iomem *)SMFRAM;
31
32 __raw_writel(0, APARMBAREA); /* translate 4k */
33 __raw_writel(__pa(sh7372_cpu_resume), SBAR); /* set reset vector */
34 __raw_writel(0x10, SYSTBCR); /* enable core standby */
35
36 __raw_writel(0, smfram + 0x3c); /* clear page table address */
37
38 sh7372_cpu_suspend();
39 cpu_init();
40
41 /* if page table address is non-NULL then we have been powered down */
42 if (__raw_readl(smfram + 0x3c)) {
43 __raw_writel(__raw_readl(smfram + 0x40),
44 __va(__raw_readl(smfram + 0x3c)));
45
46 flush_tlb_all();
47 set_cr(__raw_readl(smfram + 0x38));
48 }
49
50 __raw_writel(0, SYSTBCR); /* disable core standby */
51 __raw_writel(0, SBAR); /* disable reset vector translation */
52}
53
54#ifdef CONFIG_CPU_IDLE
55static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
56{
57 struct cpuidle_state *state;
58 int i = dev->state_count;
59
60 state = &dev->states[i];
61 snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
62 strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
63 state->exit_latency = 10;
64 state->target_residency = 20 + 10;
65 state->power_usage = 1; /* perhaps not */
66 state->flags = 0;
67 state->flags |= CPUIDLE_FLAG_TIME_VALID;
68 shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
69
70 dev->state_count = i + 1;
71}
72
73static void sh7372_cpuidle_init(void)
74{
75 shmobile_cpuidle_setup = sh7372_cpuidle_setup;
76}
77#else
78static void sh7372_cpuidle_init(void) {}
79#endif
80
81#ifdef CONFIG_SUSPEND
82static int sh7372_enter_suspend(suspend_state_t suspend_state)
83{
84 sh7372_enter_core_standby();
85 return 0;
86}
87
88static void sh7372_suspend_init(void)
89{
90 shmobile_suspend_ops.enter = sh7372_enter_suspend;
91}
92#else
93static void sh7372_suspend_init(void) {}
94#endif
95
96#define DBGREG1 0xe6100020
97#define DBGREG9 0xe6100040
98
99void __init sh7372_pm_init(void)
100{
101 /* enable DBG hardware block to kick SYSC */
102 __raw_writel(0x0000a500, DBGREG9);
103 __raw_writel(0x0000a501, DBGREG9);
104 __raw_writel(0x00000000, DBGREG1);
105
106 sh7372_suspend_init();
107 sh7372_cpuidle_init();
108}
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
index ce28141662da..2c10190dbb55 100644
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ b/arch/arm/mach-shmobile/setup-sh7367.c
@@ -22,6 +22,7 @@
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/uio_driver.h>
25#include <linux/delay.h> 26#include <linux/delay.h>
26#include <linux/input.h> 27#include <linux/input.h>
27#include <linux/io.h> 28#include <linux/io.h>
@@ -195,6 +196,214 @@ static struct platform_device cmt10_device = {
195 .num_resources = ARRAY_SIZE(cmt10_resources), 196 .num_resources = ARRAY_SIZE(cmt10_resources),
196}; 197};
197 198
199/* VPU */
200static struct uio_info vpu_platform_data = {
201 .name = "VPU5",
202 .version = "0",
203 .irq = intcs_evt2irq(0x980),
204};
205
206static struct resource vpu_resources[] = {
207 [0] = {
208 .name = "VPU",
209 .start = 0xfe900000,
210 .end = 0xfe902807,
211 .flags = IORESOURCE_MEM,
212 },
213};
214
215static struct platform_device vpu_device = {
216 .name = "uio_pdrv_genirq",
217 .id = 0,
218 .dev = {
219 .platform_data = &vpu_platform_data,
220 },
221 .resource = vpu_resources,
222 .num_resources = ARRAY_SIZE(vpu_resources),
223};
224
225/* VEU0 */
226static struct uio_info veu0_platform_data = {
227 .name = "VEU0",
228 .version = "0",
229 .irq = intcs_evt2irq(0x700),
230};
231
232static struct resource veu0_resources[] = {
233 [0] = {
234 .name = "VEU0",
235 .start = 0xfe920000,
236 .end = 0xfe9200b7,
237 .flags = IORESOURCE_MEM,
238 },
239};
240
241static struct platform_device veu0_device = {
242 .name = "uio_pdrv_genirq",
243 .id = 1,
244 .dev = {
245 .platform_data = &veu0_platform_data,
246 },
247 .resource = veu0_resources,
248 .num_resources = ARRAY_SIZE(veu0_resources),
249};
250
251/* VEU1 */
252static struct uio_info veu1_platform_data = {
253 .name = "VEU1",
254 .version = "0",
255 .irq = intcs_evt2irq(0x720),
256};
257
258static struct resource veu1_resources[] = {
259 [0] = {
260 .name = "VEU1",
261 .start = 0xfe924000,
262 .end = 0xfe9240b7,
263 .flags = IORESOURCE_MEM,
264 },
265};
266
267static struct platform_device veu1_device = {
268 .name = "uio_pdrv_genirq",
269 .id = 2,
270 .dev = {
271 .platform_data = &veu1_platform_data,
272 },
273 .resource = veu1_resources,
274 .num_resources = ARRAY_SIZE(veu1_resources),
275};
276
277/* VEU2 */
278static struct uio_info veu2_platform_data = {
279 .name = "VEU2",
280 .version = "0",
281 .irq = intcs_evt2irq(0x740),
282};
283
284static struct resource veu2_resources[] = {
285 [0] = {
286 .name = "VEU2",
287 .start = 0xfe928000,
288 .end = 0xfe9280b7,
289 .flags = IORESOURCE_MEM,
290 },
291};
292
293static struct platform_device veu2_device = {
294 .name = "uio_pdrv_genirq",
295 .id = 3,
296 .dev = {
297 .platform_data = &veu2_platform_data,
298 },
299 .resource = veu2_resources,
300 .num_resources = ARRAY_SIZE(veu2_resources),
301};
302
303/* VEU3 */
304static struct uio_info veu3_platform_data = {
305 .name = "VEU3",
306 .version = "0",
307 .irq = intcs_evt2irq(0x760),
308};
309
310static struct resource veu3_resources[] = {
311 [0] = {
312 .name = "VEU3",
313 .start = 0xfe92c000,
314 .end = 0xfe92c0b7,
315 .flags = IORESOURCE_MEM,
316 },
317};
318
319static struct platform_device veu3_device = {
320 .name = "uio_pdrv_genirq",
321 .id = 4,
322 .dev = {
323 .platform_data = &veu3_platform_data,
324 },
325 .resource = veu3_resources,
326 .num_resources = ARRAY_SIZE(veu3_resources),
327};
328
329/* VEU2H */
330static struct uio_info veu2h_platform_data = {
331 .name = "VEU2H",
332 .version = "0",
333 .irq = intcs_evt2irq(0x520),
334};
335
336static struct resource veu2h_resources[] = {
337 [0] = {
338 .name = "VEU2H",
339 .start = 0xfe93c000,
340 .end = 0xfe93c27b,
341 .flags = IORESOURCE_MEM,
342 },
343};
344
345static struct platform_device veu2h_device = {
346 .name = "uio_pdrv_genirq",
347 .id = 5,
348 .dev = {
349 .platform_data = &veu2h_platform_data,
350 },
351 .resource = veu2h_resources,
352 .num_resources = ARRAY_SIZE(veu2h_resources),
353};
354
355/* JPU */
356static struct uio_info jpu_platform_data = {
357 .name = "JPU",
358 .version = "0",
359 .irq = intcs_evt2irq(0x560),
360};
361
362static struct resource jpu_resources[] = {
363 [0] = {
364 .name = "JPU",
365 .start = 0xfe980000,
366 .end = 0xfe9902d3,
367 .flags = IORESOURCE_MEM,
368 },
369};
370
371static struct platform_device jpu_device = {
372 .name = "uio_pdrv_genirq",
373 .id = 6,
374 .dev = {
375 .platform_data = &jpu_platform_data,
376 },
377 .resource = jpu_resources,
378 .num_resources = ARRAY_SIZE(jpu_resources),
379};
380
381/* SPU1 */
382static struct uio_info spu1_platform_data = {
383 .name = "SPU1",
384 .version = "0",
385 .irq = evt2irq(0xfc0),
386};
387
388static struct resource spu1_resources[] = {
389 [0] = {
390 .name = "SPU1",
391 .start = 0xfe300000,
392 .end = 0xfe3fffff,
393 .flags = IORESOURCE_MEM,
394 },
395};
396
397static struct platform_device spu1_device = {
398 .name = "uio_pdrv_genirq",
399 .id = 7,
400 .dev = {
401 .platform_data = &spu1_platform_data,
402 },
403 .resource = spu1_resources,
404 .num_resources = ARRAY_SIZE(spu1_resources),
405};
406
198static struct platform_device *sh7367_early_devices[] __initdata = { 407static struct platform_device *sh7367_early_devices[] __initdata = {
199 &scif0_device, 408 &scif0_device,
200 &scif1_device, 409 &scif1_device,
@@ -206,10 +415,24 @@ static struct platform_device *sh7367_early_devices[] __initdata = {
206 &cmt10_device, 415 &cmt10_device,
207}; 416};
208 417
418static struct platform_device *sh7367_devices[] __initdata = {
419 &vpu_device,
420 &veu0_device,
421 &veu1_device,
422 &veu2_device,
423 &veu3_device,
424 &veu2h_device,
425 &jpu_device,
426 &spu1_device,
427};
428
209void __init sh7367_add_standard_devices(void) 429void __init sh7367_add_standard_devices(void)
210{ 430{
211 platform_add_devices(sh7367_early_devices, 431 platform_add_devices(sh7367_early_devices,
212 ARRAY_SIZE(sh7367_early_devices)); 432 ARRAY_SIZE(sh7367_early_devices));
433
434 platform_add_devices(sh7367_devices,
435 ARRAY_SIZE(sh7367_devices));
213} 436}
214 437
215#define SYMSTPCR2 0xe6158048 438#define SYMSTPCR2 0xe6158048
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index ff0494f3d00c..cd807eea69e2 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -22,6 +22,7 @@
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/uio_driver.h>
25#include <linux/delay.h> 26#include <linux/delay.h>
26#include <linux/input.h> 27#include <linux/input.h>
27#include <linux/io.h> 28#include <linux/io.h>
@@ -601,6 +602,214 @@ static struct platform_device dma2_device = {
601 }, 602 },
602}; 603};
603 604
605/* VPU */
606static struct uio_info vpu_platform_data = {
607 .name = "VPU5HG",
608 .version = "0",
609 .irq = intcs_evt2irq(0x980),
610};
611
612static struct resource vpu_resources[] = {
613 [0] = {
614 .name = "VPU",
615 .start = 0xfe900000,
616 .end = 0xfe900157,
617 .flags = IORESOURCE_MEM,
618 },
619};
620
621static struct platform_device vpu_device = {
622 .name = "uio_pdrv_genirq",
623 .id = 0,
624 .dev = {
625 .platform_data = &vpu_platform_data,
626 },
627 .resource = vpu_resources,
628 .num_resources = ARRAY_SIZE(vpu_resources),
629};
630
631/* VEU0 */
632static struct uio_info veu0_platform_data = {
633 .name = "VEU0",
634 .version = "0",
635 .irq = intcs_evt2irq(0x700),
636};
637
638static struct resource veu0_resources[] = {
639 [0] = {
640 .name = "VEU0",
641 .start = 0xfe920000,
642 .end = 0xfe9200cb,
643 .flags = IORESOURCE_MEM,
644 },
645};
646
647static struct platform_device veu0_device = {
648 .name = "uio_pdrv_genirq",
649 .id = 1,
650 .dev = {
651 .platform_data = &veu0_platform_data,
652 },
653 .resource = veu0_resources,
654 .num_resources = ARRAY_SIZE(veu0_resources),
655};
656
657/* VEU1 */
658static struct uio_info veu1_platform_data = {
659 .name = "VEU1",
660 .version = "0",
661 .irq = intcs_evt2irq(0x720),
662};
663
664static struct resource veu1_resources[] = {
665 [0] = {
666 .name = "VEU1",
667 .start = 0xfe924000,
668 .end = 0xfe9240cb,
669 .flags = IORESOURCE_MEM,
670 },
671};
672
673static struct platform_device veu1_device = {
674 .name = "uio_pdrv_genirq",
675 .id = 2,
676 .dev = {
677 .platform_data = &veu1_platform_data,
678 },
679 .resource = veu1_resources,
680 .num_resources = ARRAY_SIZE(veu1_resources),
681};
682
683/* VEU2 */
684static struct uio_info veu2_platform_data = {
685 .name = "VEU2",
686 .version = "0",
687 .irq = intcs_evt2irq(0x740),
688};
689
690static struct resource veu2_resources[] = {
691 [0] = {
692 .name = "VEU2",
693 .start = 0xfe928000,
694 .end = 0xfe928307,
695 .flags = IORESOURCE_MEM,
696 },
697};
698
699static struct platform_device veu2_device = {
700 .name = "uio_pdrv_genirq",
701 .id = 3,
702 .dev = {
703 .platform_data = &veu2_platform_data,
704 },
705 .resource = veu2_resources,
706 .num_resources = ARRAY_SIZE(veu2_resources),
707};
708
709/* VEU3 */
710static struct uio_info veu3_platform_data = {
711 .name = "VEU3",
712 .version = "0",
713 .irq = intcs_evt2irq(0x760),
714};
715
716static struct resource veu3_resources[] = {
717 [0] = {
718 .name = "VEU3",
719 .start = 0xfe92c000,
720 .end = 0xfe92c307,
721 .flags = IORESOURCE_MEM,
722 },
723};
724
725static struct platform_device veu3_device = {
726 .name = "uio_pdrv_genirq",
727 .id = 4,
728 .dev = {
729 .platform_data = &veu3_platform_data,
730 },
731 .resource = veu3_resources,
732 .num_resources = ARRAY_SIZE(veu3_resources),
733};
734
735/* JPU */
736static struct uio_info jpu_platform_data = {
737 .name = "JPU",
738 .version = "0",
739 .irq = intcs_evt2irq(0x560),
740};
741
742static struct resource jpu_resources[] = {
743 [0] = {
744 .name = "JPU",
745 .start = 0xfe980000,
746 .end = 0xfe9902d3,
747 .flags = IORESOURCE_MEM,
748 },
749};
750
751static struct platform_device jpu_device = {
752 .name = "uio_pdrv_genirq",
753 .id = 5,
754 .dev = {
755 .platform_data = &jpu_platform_data,
756 },
757 .resource = jpu_resources,
758 .num_resources = ARRAY_SIZE(jpu_resources),
759};
760
761/* SPU2DSP0 */
762static struct uio_info spu0_platform_data = {
763 .name = "SPU2DSP0",
764 .version = "0",
765 .irq = evt2irq(0x1800),
766};
767
768static struct resource spu0_resources[] = {
769 [0] = {
770 .name = "SPU2DSP0",
771 .start = 0xfe200000,
772 .end = 0xfe2fffff,
773 .flags = IORESOURCE_MEM,
774 },
775};
776
777static struct platform_device spu0_device = {
778 .name = "uio_pdrv_genirq",
779 .id = 6,
780 .dev = {
781 .platform_data = &spu0_platform_data,
782 },
783 .resource = spu0_resources,
784 .num_resources = ARRAY_SIZE(spu0_resources),
785};
786
787/* SPU2DSP1 */
788static struct uio_info spu1_platform_data = {
789 .name = "SPU2DSP1",
790 .version = "0",
791 .irq = evt2irq(0x1820),
792};
793
794static struct resource spu1_resources[] = {
795 [0] = {
796 .name = "SPU2DSP1",
797 .start = 0xfe300000,
798 .end = 0xfe3fffff,
799 .flags = IORESOURCE_MEM,
800 },
801};
802
803static struct platform_device spu1_device = {
804 .name = "uio_pdrv_genirq",
805 .id = 7,
806 .dev = {
807 .platform_data = &spu1_platform_data,
808 },
809 .resource = spu1_resources,
810 .num_resources = ARRAY_SIZE(spu1_resources),
811};
812
604static struct platform_device *sh7372_early_devices[] __initdata = { 813static struct platform_device *sh7372_early_devices[] __initdata = {
605 &scif0_device, 814 &scif0_device,
606 &scif1_device, 815 &scif1_device,
@@ -620,6 +829,14 @@ static struct platform_device *sh7372_late_devices[] __initdata = {
620 &dma0_device, 829 &dma0_device,
621 &dma1_device, 830 &dma1_device,
622 &dma2_device, 831 &dma2_device,
832 &vpu_device,
833 &veu0_device,
834 &veu1_device,
835 &veu2_device,
836 &veu3_device,
837 &jpu_device,
838 &spu0_device,
839 &spu1_device,
623}; 840};
624 841
625void __init sh7372_add_standard_devices(void) 842void __init sh7372_add_standard_devices(void)
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
index 8099b0b8a934..bb405b8e459b 100644
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -22,6 +22,7 @@
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/uio_driver.h>
25#include <linux/delay.h> 26#include <linux/delay.h>
26#include <linux/input.h> 27#include <linux/input.h>
27#include <linux/io.h> 28#include <linux/io.h>
@@ -38,7 +39,7 @@ static struct plat_sci_port scif0_platform_data = {
38 .flags = UPF_BOOT_AUTOCONF, 39 .flags = UPF_BOOT_AUTOCONF,
39 .scscr = SCSCR_RE | SCSCR_TE, 40 .scscr = SCSCR_RE | SCSCR_TE,
40 .scbrr_algo_id = SCBRR_ALGO_4, 41 .scbrr_algo_id = SCBRR_ALGO_4,
41 .type = PORT_SCIF, 42 .type = PORT_SCIFA,
42 .irqs = { evt2irq(0xc00), evt2irq(0xc00), 43 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
43 evt2irq(0xc00), evt2irq(0xc00) }, 44 evt2irq(0xc00), evt2irq(0xc00) },
44}; 45};
@@ -57,7 +58,7 @@ static struct plat_sci_port scif1_platform_data = {
57 .flags = UPF_BOOT_AUTOCONF, 58 .flags = UPF_BOOT_AUTOCONF,
58 .scscr = SCSCR_RE | SCSCR_TE, 59 .scscr = SCSCR_RE | SCSCR_TE,
59 .scbrr_algo_id = SCBRR_ALGO_4, 60 .scbrr_algo_id = SCBRR_ALGO_4,
60 .type = PORT_SCIF, 61 .type = PORT_SCIFA,
61 .irqs = { evt2irq(0xc20), evt2irq(0xc20), 62 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
62 evt2irq(0xc20), evt2irq(0xc20) }, 63 evt2irq(0xc20), evt2irq(0xc20) },
63}; 64};
@@ -76,7 +77,7 @@ static struct plat_sci_port scif2_platform_data = {
76 .flags = UPF_BOOT_AUTOCONF, 77 .flags = UPF_BOOT_AUTOCONF,
77 .scscr = SCSCR_RE | SCSCR_TE, 78 .scscr = SCSCR_RE | SCSCR_TE,
78 .scbrr_algo_id = SCBRR_ALGO_4, 79 .scbrr_algo_id = SCBRR_ALGO_4,
79 .type = PORT_SCIF, 80 .type = PORT_SCIFA,
80 .irqs = { evt2irq(0xc40), evt2irq(0xc40), 81 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
81 evt2irq(0xc40), evt2irq(0xc40) }, 82 evt2irq(0xc40), evt2irq(0xc40) },
82}; 83};
@@ -95,7 +96,7 @@ static struct plat_sci_port scif3_platform_data = {
95 .flags = UPF_BOOT_AUTOCONF, 96 .flags = UPF_BOOT_AUTOCONF,
96 .scscr = SCSCR_RE | SCSCR_TE, 97 .scscr = SCSCR_RE | SCSCR_TE,
97 .scbrr_algo_id = SCBRR_ALGO_4, 98 .scbrr_algo_id = SCBRR_ALGO_4,
98 .type = PORT_SCIF, 99 .type = PORT_SCIFA,
99 .irqs = { evt2irq(0xc60), evt2irq(0xc60), 100 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
100 evt2irq(0xc60), evt2irq(0xc60) }, 101 evt2irq(0xc60), evt2irq(0xc60) },
101}; 102};
@@ -114,7 +115,7 @@ static struct plat_sci_port scif4_platform_data = {
114 .flags = UPF_BOOT_AUTOCONF, 115 .flags = UPF_BOOT_AUTOCONF,
115 .scscr = SCSCR_RE | SCSCR_TE, 116 .scscr = SCSCR_RE | SCSCR_TE,
116 .scbrr_algo_id = SCBRR_ALGO_4, 117 .scbrr_algo_id = SCBRR_ALGO_4,
117 .type = PORT_SCIF, 118 .type = PORT_SCIFA,
118 .irqs = { evt2irq(0xd20), evt2irq(0xd20), 119 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
119 evt2irq(0xd20), evt2irq(0xd20) }, 120 evt2irq(0xd20), evt2irq(0xd20) },
120}; 121};
@@ -133,7 +134,7 @@ static struct plat_sci_port scif5_platform_data = {
133 .flags = UPF_BOOT_AUTOCONF, 134 .flags = UPF_BOOT_AUTOCONF,
134 .scscr = SCSCR_RE | SCSCR_TE, 135 .scscr = SCSCR_RE | SCSCR_TE,
135 .scbrr_algo_id = SCBRR_ALGO_4, 136 .scbrr_algo_id = SCBRR_ALGO_4,
136 .type = PORT_SCIF, 137 .type = PORT_SCIFA,
137 .irqs = { evt2irq(0xd40), evt2irq(0xd40), 138 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
138 evt2irq(0xd40), evt2irq(0xd40) }, 139 evt2irq(0xd40), evt2irq(0xd40) },
139}; 140};
@@ -152,7 +153,7 @@ static struct plat_sci_port scif6_platform_data = {
152 .flags = UPF_BOOT_AUTOCONF, 153 .flags = UPF_BOOT_AUTOCONF,
153 .scscr = SCSCR_RE | SCSCR_TE, 154 .scscr = SCSCR_RE | SCSCR_TE,
154 .scbrr_algo_id = SCBRR_ALGO_4, 155 .scbrr_algo_id = SCBRR_ALGO_4,
155 .type = PORT_SCIF, 156 .type = PORT_SCIFA,
156 .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80), 157 .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
157 intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) }, 158 intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
158}; 159};
@@ -171,7 +172,7 @@ static struct plat_sci_port scif7_platform_data = {
171 .flags = UPF_BOOT_AUTOCONF, 172 .flags = UPF_BOOT_AUTOCONF,
172 .scscr = SCSCR_RE | SCSCR_TE, 173 .scscr = SCSCR_RE | SCSCR_TE,
173 .scbrr_algo_id = SCBRR_ALGO_4, 174 .scbrr_algo_id = SCBRR_ALGO_4,
174 .type = PORT_SCIF, 175 .type = PORT_SCIFB,
175 .irqs = { evt2irq(0xd60), evt2irq(0xd60), 176 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
176 evt2irq(0xd60), evt2irq(0xd60) }, 177 evt2irq(0xd60), evt2irq(0xd60) },
177}; 178};
@@ -215,6 +216,214 @@ static struct platform_device cmt10_device = {
215 .num_resources = ARRAY_SIZE(cmt10_resources), 216 .num_resources = ARRAY_SIZE(cmt10_resources),
216}; 217};
217 218
219/* VPU */
220static struct uio_info vpu_platform_data = {
221 .name = "VPU5HG",
222 .version = "0",
223 .irq = intcs_evt2irq(0x980),
224};
225
226static struct resource vpu_resources[] = {
227 [0] = {
228 .name = "VPU",
229 .start = 0xfe900000,
230 .end = 0xfe900157,
231 .flags = IORESOURCE_MEM,
232 },
233};
234
235static struct platform_device vpu_device = {
236 .name = "uio_pdrv_genirq",
237 .id = 0,
238 .dev = {
239 .platform_data = &vpu_platform_data,
240 },
241 .resource = vpu_resources,
242 .num_resources = ARRAY_SIZE(vpu_resources),
243};
244
245/* VEU0 */
246static struct uio_info veu0_platform_data = {
247 .name = "VEU0",
248 .version = "0",
249 .irq = intcs_evt2irq(0x700),
250};
251
252static struct resource veu0_resources[] = {
253 [0] = {
254 .name = "VEU0",
255 .start = 0xfe920000,
256 .end = 0xfe9200cb,
257 .flags = IORESOURCE_MEM,
258 },
259};
260
261static struct platform_device veu0_device = {
262 .name = "uio_pdrv_genirq",
263 .id = 1,
264 .dev = {
265 .platform_data = &veu0_platform_data,
266 },
267 .resource = veu0_resources,
268 .num_resources = ARRAY_SIZE(veu0_resources),
269};
270
271/* VEU1 */
272static struct uio_info veu1_platform_data = {
273 .name = "VEU1",
274 .version = "0",
275 .irq = intcs_evt2irq(0x720),
276};
277
278static struct resource veu1_resources[] = {
279 [0] = {
280 .name = "VEU1",
281 .start = 0xfe924000,
282 .end = 0xfe9240cb,
283 .flags = IORESOURCE_MEM,
284 },
285};
286
287static struct platform_device veu1_device = {
288 .name = "uio_pdrv_genirq",
289 .id = 2,
290 .dev = {
291 .platform_data = &veu1_platform_data,
292 },
293 .resource = veu1_resources,
294 .num_resources = ARRAY_SIZE(veu1_resources),
295};
296
297/* VEU2 */
298static struct uio_info veu2_platform_data = {
299 .name = "VEU2",
300 .version = "0",
301 .irq = intcs_evt2irq(0x740),
302};
303
304static struct resource veu2_resources[] = {
305 [0] = {
306 .name = "VEU2",
307 .start = 0xfe928000,
308 .end = 0xfe928307,
309 .flags = IORESOURCE_MEM,
310 },
311};
312
313static struct platform_device veu2_device = {
314 .name = "uio_pdrv_genirq",
315 .id = 3,
316 .dev = {
317 .platform_data = &veu2_platform_data,
318 },
319 .resource = veu2_resources,
320 .num_resources = ARRAY_SIZE(veu2_resources),
321};
322
323/* VEU3 */
324static struct uio_info veu3_platform_data = {
325 .name = "VEU3",
326 .version = "0",
327 .irq = intcs_evt2irq(0x760),
328};
329
330static struct resource veu3_resources[] = {
331 [0] = {
332 .name = "VEU3",
333 .start = 0xfe92c000,
334 .end = 0xfe92c307,
335 .flags = IORESOURCE_MEM,
336 },
337};
338
339static struct platform_device veu3_device = {
340 .name = "uio_pdrv_genirq",
341 .id = 4,
342 .dev = {
343 .platform_data = &veu3_platform_data,
344 },
345 .resource = veu3_resources,
346 .num_resources = ARRAY_SIZE(veu3_resources),
347};
348
349/* JPU */
350static struct uio_info jpu_platform_data = {
351 .name = "JPU",
352 .version = "0",
353 .irq = intcs_evt2irq(0x560),
354};
355
356static struct resource jpu_resources[] = {
357 [0] = {
358 .name = "JPU",
359 .start = 0xfe980000,
360 .end = 0xfe9902d3,
361 .flags = IORESOURCE_MEM,
362 },
363};
364
365static struct platform_device jpu_device = {
366 .name = "uio_pdrv_genirq",
367 .id = 5,
368 .dev = {
369 .platform_data = &jpu_platform_data,
370 },
371 .resource = jpu_resources,
372 .num_resources = ARRAY_SIZE(jpu_resources),
373};
374
375/* SPU2DSP0 */
376static struct uio_info spu0_platform_data = {
377 .name = "SPU2DSP0",
378 .version = "0",
379 .irq = evt2irq(0x1800),
380};
381
382static struct resource spu0_resources[] = {
383 [0] = {
384 .name = "SPU2DSP0",
385 .start = 0xfe200000,
386 .end = 0xfe2fffff,
387 .flags = IORESOURCE_MEM,
388 },
389};
390
391static struct platform_device spu0_device = {
392 .name = "uio_pdrv_genirq",
393 .id = 6,
394 .dev = {
395 .platform_data = &spu0_platform_data,
396 },
397 .resource = spu0_resources,
398 .num_resources = ARRAY_SIZE(spu0_resources),
399};
400
401/* SPU2DSP1 */
402static struct uio_info spu1_platform_data = {
403 .name = "SPU2DSP1",
404 .version = "0",
405 .irq = evt2irq(0x1820),
406};
407
408static struct resource spu1_resources[] = {
409 [0] = {
410 .name = "SPU2DSP1",
411 .start = 0xfe300000,
412 .end = 0xfe3fffff,
413 .flags = IORESOURCE_MEM,
414 },
415};
416
417static struct platform_device spu1_device = {
418 .name = "uio_pdrv_genirq",
419 .id = 7,
420 .dev = {
421 .platform_data = &spu1_platform_data,
422 },
423 .resource = spu1_resources,
424 .num_resources = ARRAY_SIZE(spu1_resources),
425};
426
218static struct platform_device *sh7377_early_devices[] __initdata = { 427static struct platform_device *sh7377_early_devices[] __initdata = {
219 &scif0_device, 428 &scif0_device,
220 &scif1_device, 429 &scif1_device,
@@ -227,10 +436,24 @@ static struct platform_device *sh7377_early_devices[] __initdata = {
227 &cmt10_device, 436 &cmt10_device,
228}; 437};
229 438
439static struct platform_device *sh7377_devices[] __initdata = {
440 &vpu_device,
441 &veu0_device,
442 &veu1_device,
443 &veu2_device,
444 &veu3_device,
445 &jpu_device,
446 &spu0_device,
447 &spu1_device,
448};
449
230void __init sh7377_add_standard_devices(void) 450void __init sh7377_add_standard_devices(void)
231{ 451{
232 platform_add_devices(sh7377_early_devices, 452 platform_add_devices(sh7377_early_devices,
233 ARRAY_SIZE(sh7377_early_devices)); 453 ARRAY_SIZE(sh7377_early_devices));
454
455 platform_add_devices(sh7377_devices,
456 ARRAY_SIZE(sh7377_devices));
234} 457}
235 458
236#define SMSTPCR3 0xe615013c 459#define SMSTPCR3 0xe615013c
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 685c40a2f5e6..e46821c0a62e 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -27,9 +27,11 @@
27#include <linux/input.h> 27#include <linux/input.h>
28#include <linux/io.h> 28#include <linux/io.h>
29#include <linux/serial_sci.h> 29#include <linux/serial_sci.h>
30#include <linux/sh_dma.h>
30#include <linux/sh_intc.h> 31#include <linux/sh_intc.h>
31#include <linux/sh_timer.h> 32#include <linux/sh_timer.h>
32#include <mach/hardware.h> 33#include <mach/hardware.h>
34#include <mach/sh73a0.h>
33#include <asm/mach-types.h> 35#include <asm/mach-types.h>
34#include <asm/mach/arch.h> 36#include <asm/mach/arch.h>
35 37
@@ -392,6 +394,242 @@ static struct platform_device i2c4_device = {
392 .num_resources = ARRAY_SIZE(i2c4_resources), 394 .num_resources = ARRAY_SIZE(i2c4_resources),
393}; 395};
394 396
397/* Transmit sizes and respective CHCR register values */
398enum {
399 XMIT_SZ_8BIT = 0,
400 XMIT_SZ_16BIT = 1,
401 XMIT_SZ_32BIT = 2,
402 XMIT_SZ_64BIT = 7,
403 XMIT_SZ_128BIT = 3,
404 XMIT_SZ_256BIT = 4,
405 XMIT_SZ_512BIT = 5,
406};
407
408/* log2(size / 8) - used to calculate number of transfers */
409#define TS_SHIFT { \
410 [XMIT_SZ_8BIT] = 0, \
411 [XMIT_SZ_16BIT] = 1, \
412 [XMIT_SZ_32BIT] = 2, \
413 [XMIT_SZ_64BIT] = 3, \
414 [XMIT_SZ_128BIT] = 4, \
415 [XMIT_SZ_256BIT] = 5, \
416 [XMIT_SZ_512BIT] = 6, \
417}
418
419#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | (((i) & 0xc) << (20 - 2)))
420#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
421#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
422
423static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
424 {
425 .slave_id = SHDMA_SLAVE_SCIF0_TX,
426 .addr = 0xe6c40020,
427 .chcr = CHCR_TX(XMIT_SZ_8BIT),
428 .mid_rid = 0x21,
429 }, {
430 .slave_id = SHDMA_SLAVE_SCIF0_RX,
431 .addr = 0xe6c40024,
432 .chcr = CHCR_RX(XMIT_SZ_8BIT),
433 .mid_rid = 0x22,
434 }, {
435 .slave_id = SHDMA_SLAVE_SCIF1_TX,
436 .addr = 0xe6c50020,
437 .chcr = CHCR_TX(XMIT_SZ_8BIT),
438 .mid_rid = 0x25,
439 }, {
440 .slave_id = SHDMA_SLAVE_SCIF1_RX,
441 .addr = 0xe6c50024,
442 .chcr = CHCR_RX(XMIT_SZ_8BIT),
443 .mid_rid = 0x26,
444 }, {
445 .slave_id = SHDMA_SLAVE_SCIF2_TX,
446 .addr = 0xe6c60020,
447 .chcr = CHCR_TX(XMIT_SZ_8BIT),
448 .mid_rid = 0x29,
449 }, {
450 .slave_id = SHDMA_SLAVE_SCIF2_RX,
451 .addr = 0xe6c60024,
452 .chcr = CHCR_RX(XMIT_SZ_8BIT),
453 .mid_rid = 0x2a,
454 }, {
455 .slave_id = SHDMA_SLAVE_SCIF3_TX,
456 .addr = 0xe6c70020,
457 .chcr = CHCR_TX(XMIT_SZ_8BIT),
458 .mid_rid = 0x2d,
459 }, {
460 .slave_id = SHDMA_SLAVE_SCIF3_RX,
461 .addr = 0xe6c70024,
462 .chcr = CHCR_RX(XMIT_SZ_8BIT),
463 .mid_rid = 0x2e,
464 }, {
465 .slave_id = SHDMA_SLAVE_SCIF4_TX,
466 .addr = 0xe6c80020,
467 .chcr = CHCR_TX(XMIT_SZ_8BIT),
468 .mid_rid = 0x39,
469 }, {
470 .slave_id = SHDMA_SLAVE_SCIF4_RX,
471 .addr = 0xe6c80024,
472 .chcr = CHCR_RX(XMIT_SZ_8BIT),
473 .mid_rid = 0x3a,
474 }, {
475 .slave_id = SHDMA_SLAVE_SCIF5_TX,
476 .addr = 0xe6cb0020,
477 .chcr = CHCR_TX(XMIT_SZ_8BIT),
478 .mid_rid = 0x35,
479 }, {
480 .slave_id = SHDMA_SLAVE_SCIF5_RX,
481 .addr = 0xe6cb0024,
482 .chcr = CHCR_RX(XMIT_SZ_8BIT),
483 .mid_rid = 0x36,
484 }, {
485 .slave_id = SHDMA_SLAVE_SCIF6_TX,
486 .addr = 0xe6cc0020,
487 .chcr = CHCR_TX(XMIT_SZ_8BIT),
488 .mid_rid = 0x1d,
489 }, {
490 .slave_id = SHDMA_SLAVE_SCIF6_RX,
491 .addr = 0xe6cc0024,
492 .chcr = CHCR_RX(XMIT_SZ_8BIT),
493 .mid_rid = 0x1e,
494 }, {
495 .slave_id = SHDMA_SLAVE_SCIF7_TX,
496 .addr = 0xe6cd0020,
497 .chcr = CHCR_TX(XMIT_SZ_8BIT),
498 .mid_rid = 0x19,
499 }, {
500 .slave_id = SHDMA_SLAVE_SCIF7_RX,
501 .addr = 0xe6cd0024,
502 .chcr = CHCR_RX(XMIT_SZ_8BIT),
503 .mid_rid = 0x1a,
504 }, {
505 .slave_id = SHDMA_SLAVE_SCIF8_TX,
506 .addr = 0xe6c30040,
507 .chcr = CHCR_TX(XMIT_SZ_8BIT),
508 .mid_rid = 0x3d,
509 }, {
510 .slave_id = SHDMA_SLAVE_SCIF8_RX,
511 .addr = 0xe6c30060,
512 .chcr = CHCR_RX(XMIT_SZ_8BIT),
513 .mid_rid = 0x3e,
514 }, {
515 .slave_id = SHDMA_SLAVE_SDHI0_TX,
516 .addr = 0xee100030,
517 .chcr = CHCR_TX(XMIT_SZ_16BIT),
518 .mid_rid = 0xc1,
519 }, {
520 .slave_id = SHDMA_SLAVE_SDHI0_RX,
521 .addr = 0xee100030,
522 .chcr = CHCR_RX(XMIT_SZ_16BIT),
523 .mid_rid = 0xc2,
524 }, {
525 .slave_id = SHDMA_SLAVE_SDHI1_TX,
526 .addr = 0xee120030,
527 .chcr = CHCR_TX(XMIT_SZ_16BIT),
528 .mid_rid = 0xc9,
529 }, {
530 .slave_id = SHDMA_SLAVE_SDHI1_RX,
531 .addr = 0xee120030,
532 .chcr = CHCR_RX(XMIT_SZ_16BIT),
533 .mid_rid = 0xca,
534 }, {
535 .slave_id = SHDMA_SLAVE_SDHI2_TX,
536 .addr = 0xee140030,
537 .chcr = CHCR_TX(XMIT_SZ_16BIT),
538 .mid_rid = 0xcd,
539 }, {
540 .slave_id = SHDMA_SLAVE_SDHI2_RX,
541 .addr = 0xee140030,
542 .chcr = CHCR_RX(XMIT_SZ_16BIT),
543 .mid_rid = 0xce,
544 }, {
545 .slave_id = SHDMA_SLAVE_MMCIF_TX,
546 .addr = 0xe6bd0034,
547 .chcr = CHCR_TX(XMIT_SZ_32BIT),
548 .mid_rid = 0xd1,
549 }, {
550 .slave_id = SHDMA_SLAVE_MMCIF_RX,
551 .addr = 0xe6bd0034,
552 .chcr = CHCR_RX(XMIT_SZ_32BIT),
553 .mid_rid = 0xd2,
554 },
555};
556
557#define DMAE_CHANNEL(_offset) \
558 { \
559 .offset = _offset - 0x20, \
560 .dmars = _offset - 0x20 + 0x40, \
561 }
562
563static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
564 DMAE_CHANNEL(0x8000),
565 DMAE_CHANNEL(0x8080),
566 DMAE_CHANNEL(0x8100),
567 DMAE_CHANNEL(0x8180),
568 DMAE_CHANNEL(0x8200),
569 DMAE_CHANNEL(0x8280),
570 DMAE_CHANNEL(0x8300),
571 DMAE_CHANNEL(0x8380),
572 DMAE_CHANNEL(0x8400),
573 DMAE_CHANNEL(0x8480),
574 DMAE_CHANNEL(0x8500),
575 DMAE_CHANNEL(0x8580),
576 DMAE_CHANNEL(0x8600),
577 DMAE_CHANNEL(0x8680),
578 DMAE_CHANNEL(0x8700),
579 DMAE_CHANNEL(0x8780),
580 DMAE_CHANNEL(0x8800),
581 DMAE_CHANNEL(0x8880),
582 DMAE_CHANNEL(0x8900),
583 DMAE_CHANNEL(0x8980),
584};
585
586static const unsigned int ts_shift[] = TS_SHIFT;
587
588static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
589 .slave = sh73a0_dmae_slaves,
590 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
591 .channel = sh73a0_dmae_channels,
592 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
593 .ts_low_shift = 3,
594 .ts_low_mask = 0x18,
595 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
596 .ts_high_mask = 0x00300000,
597 .ts_shift = ts_shift,
598 .ts_shift_num = ARRAY_SIZE(ts_shift),
599 .dmaor_init = DMAOR_DME,
600};
601
602static struct resource sh73a0_dmae_resources[] = {
603 {
604 /* Registers including DMAOR and channels including DMARSx */
605 .start = 0xfe000020,
606 .end = 0xfe008a00 - 1,
607 .flags = IORESOURCE_MEM,
608 },
609 {
610 /* DMA error IRQ */
611 .start = gic_spi(129),
612 .end = gic_spi(129),
613 .flags = IORESOURCE_IRQ,
614 },
615 {
616 /* IRQ for channels 0-19 */
617 .start = gic_spi(109),
618 .end = gic_spi(128),
619 .flags = IORESOURCE_IRQ,
620 },
621};
622
623static struct platform_device dma0_device = {
624 .name = "sh-dma-engine",
625 .id = 0,
626 .resource = sh73a0_dmae_resources,
627 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
628 .dev = {
629 .platform_data = &sh73a0_dmae_platform_data,
630 },
631};
632
395static struct platform_device *sh73a0_early_devices[] __initdata = { 633static struct platform_device *sh73a0_early_devices[] __initdata = {
396 &scif0_device, 634 &scif0_device,
397 &scif1_device, 635 &scif1_device,
@@ -413,10 +651,16 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
413 &i2c2_device, 651 &i2c2_device,
414 &i2c3_device, 652 &i2c3_device,
415 &i2c4_device, 653 &i2c4_device,
654 &dma0_device,
416}; 655};
417 656
657#define SRCR2 0xe61580b0
658
418void __init sh73a0_add_standard_devices(void) 659void __init sh73a0_add_standard_devices(void)
419{ 660{
661 /* Clear software reset bit on SY-DMAC module */
662 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
663
420 platform_add_devices(sh73a0_early_devices, 664 platform_add_devices(sh73a0_early_devices,
421 ARRAY_SIZE(sh73a0_early_devices)); 665 ARRAY_SIZE(sh73a0_early_devices));
422 platform_add_devices(sh73a0_late_devices, 666 platform_add_devices(sh73a0_late_devices,
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
new file mode 100644
index 000000000000..d37d3ca4d18f
--- /dev/null
+++ b/arch/arm/mach-shmobile/sleep-sh7372.S
@@ -0,0 +1,260 @@
1/*
2 * sh7372 lowlevel sleep code for "Core Standby Mode"
3 *
4 * Copyright (C) 2011 Magnus Damm
5 *
6 * In "Core Standby Mode" the ARM core is off, but L2 cache is still on
7 *
8 * Based on mach-omap2/sleep34xx.S
9 *
10 * (C) Copyright 2007 Texas Instruments
11 * Karthik Dasu <karthik-dp@ti.com>
12 *
13 * (C) Copyright 2004 Texas Instruments, <www.ti.com>
14 * Richard Woodruff <r-woodruff2@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 */
31
32#include <linux/linkage.h>
33#include <asm/assembler.h>
34
35#define SMFRAM 0xe6a70000
36
37 .align
38kernel_flush:
39 .word v7_flush_dcache_all
40
41 .align 3
42ENTRY(sh7372_cpu_suspend)
43 stmfd sp!, {r0-r12, lr} @ save registers on stack
44
45 ldr r8, =SMFRAM
46
47 mov r4, sp @ Store sp
48 mrs r5, spsr @ Store spsr
49 mov r6, lr @ Store lr
50 stmia r8!, {r4-r6}
51
52 mrc p15, 0, r4, c1, c0, 2 @ Coprocessor access control register
53 mrc p15, 0, r5, c2, c0, 0 @ TTBR0
54 mrc p15, 0, r6, c2, c0, 1 @ TTBR1
55 mrc p15, 0, r7, c2, c0, 2 @ TTBCR
56 stmia r8!, {r4-r7}
57
58 mrc p15, 0, r4, c3, c0, 0 @ Domain access Control Register
59 mrc p15, 0, r5, c10, c2, 0 @ PRRR
60 mrc p15, 0, r6, c10, c2, 1 @ NMRR
61 stmia r8!,{r4-r6}
62
63 mrc p15, 0, r4, c13, c0, 1 @ Context ID
64 mrc p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
65 mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
66 mrs r7, cpsr @ Store current cpsr
67 stmia r8!, {r4-r7}
68
69 mrc p15, 0, r4, c1, c0, 0 @ save control register
70 stmia r8!, {r4}
71
72 /*
73 * jump out to kernel flush routine
74 * - reuse that code is better
75 * - it executes in a cached space so is faster than refetch per-block
76 * - should be faster and will change with kernel
77 * - 'might' have to copy address, load and jump to it
78 * Flush all data from the L1 data cache before disabling
79 * SCTLR.C bit.
80 */
81 ldr r1, kernel_flush
82 mov lr, pc
83 bx r1
84
85 /*
86 * Clear the SCTLR.C bit to prevent further data cache
87 * allocation. Clearing SCTLR.C would make all the data accesses
88 * strongly ordered and would not hit the cache.
89 */
90 mrc p15, 0, r0, c1, c0, 0
91 bic r0, r0, #(1 << 2) @ Disable the C bit
92 mcr p15, 0, r0, c1, c0, 0
93 isb
94
95 /*
96 * Invalidate L1 data cache. Even though only invalidate is
97 * necessary exported flush API is used here. Doing clean
98 * on already clean cache would be almost NOP.
99 */
100 ldr r1, kernel_flush
101 blx r1
102 /*
103 * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
104 * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
105 * This sequence switches back to ARM. Note that .align may insert a
106 * nop: bx pc needs to be word-aligned in order to work.
107 */
108 THUMB( .thumb )
109 THUMB( .align )
110 THUMB( bx pc )
111 THUMB( nop )
112 .arm
113
114 /* Data memory barrier and Data sync barrier */
115 dsb
116 dmb
117
118/*
119 * ===================================
120 * == WFI instruction => Enter idle ==
121 * ===================================
122 */
123 wfi @ wait for interrupt
124
125/*
126 * ===================================
127 * == Resume path for non-OFF modes ==
128 * ===================================
129 */
130 mrc p15, 0, r0, c1, c0, 0
131 tst r0, #(1 << 2) @ Check C bit enabled?
132 orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared
133 mcreq p15, 0, r0, c1, c0, 0
134 isb
135
136/*
137 * ===================================
138 * == Exit point from non-OFF modes ==
139 * ===================================
140 */
141 ldmfd sp!, {r0-r12, pc} @ restore regs and return
142
143 .pool
144
145 .align 12
146 .text
147 .global sh7372_cpu_resume
148sh7372_cpu_resume:
149
150 mov r1, #0
151 /*
152 * Invalidate all instruction caches to PoU
153 * and flush branch target cache
154 */
155 mcr p15, 0, r1, c7, c5, 0
156
157 ldr r3, =SMFRAM
158
159 ldmia r3!, {r4-r6}
160 mov sp, r4 @ Restore sp
161 msr spsr_cxsf, r5 @ Restore spsr
162 mov lr, r6 @ Restore lr
163
164 ldmia r3!, {r4-r7}
165 mcr p15, 0, r4, c1, c0, 2 @ Coprocessor access Control Register
166 mcr p15, 0, r5, c2, c0, 0 @ TTBR0
167 mcr p15, 0, r6, c2, c0, 1 @ TTBR1
168 mcr p15, 0, r7, c2, c0, 2 @ TTBCR
169
170 ldmia r3!,{r4-r6}
171 mcr p15, 0, r4, c3, c0, 0 @ Domain access Control Register
172 mcr p15, 0, r5, c10, c2, 0 @ PRRR
173 mcr p15, 0, r6, c10, c2, 1 @ NMRR
174
175 ldmia r3!,{r4-r7}
176 mcr p15, 0, r4, c13, c0, 1 @ Context ID
177 mcr p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
178 mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
179 msr cpsr, r7 @ store cpsr
180
181 /* Starting to enable MMU here */
182 mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
183 /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
184 and r7, #0x7
185 cmp r7, #0x0
186 beq usettbr0
187ttbr_error:
188 /*
189 * More work needs to be done to support N[0:2] value other than 0
190 * So looping here so that the error can be detected
191 */
192 b ttbr_error
193
194 .align
195cache_pred_disable_mask:
196 .word 0xFFFFE7FB
197ttbrbit_mask:
198 .word 0xFFFFC000
199table_index_mask:
200 .word 0xFFF00000
201table_entry:
202 .word 0x00000C02
203usettbr0:
204
205 mrc p15, 0, r2, c2, c0, 0
206 ldr r5, ttbrbit_mask
207 and r2, r5
208 mov r4, pc
209 ldr r5, table_index_mask
210 and r4, r5 @ r4 = 31 to 20 bits of pc
211 /* Extract the value to be written to table entry */
212 ldr r6, table_entry
213 /* r6 has the value to be written to table entry */
214 add r6, r6, r4
215 /* Getting the address of table entry to modify */
216 lsr r4, #18
217 /* r2 has the location which needs to be modified */
218 add r2, r4
219 ldr r4, [r2]
220 str r6, [r2] /* modify the table entry */
221
222 mov r7, r6
223 mov r5, r2
224 mov r6, r4
225 /* r5 = original page table address */
226 /* r6 = original page table data */
227
228 mov r0, #0
229 mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer
230 mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
231 mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
232 mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
233
234 /*
235 * Restore control register. This enables the MMU.
236 * The caches and prediction are not enabled here, they
237 * will be enabled after restoring the MMU table entry.
238 */
239 ldmia r3!, {r4}
240 stmia r3!, {r5} /* save original page table address */
241 stmia r3!, {r6} /* save original page table data */
242 stmia r3!, {r7} /* save modified page table data */
243
244 ldr r2, cache_pred_disable_mask
245 and r4, r2
246 mcr p15, 0, r4, c1, c0, 0
247 dsb
248 isb
249
250 ldr r0, =restoremmu_on
251 bx r0
252
253/*
254 * ==============================
255 * == Exit point from OFF mode ==
256 * ==============================
257 */
258restoremmu_on:
259
260 ldmfd sp!, {r0-r12, pc} @ restore regs and return
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index a156d2108df1..3ffdbc92ba82 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -59,6 +59,11 @@ unsigned int __init sh73a0_get_core_count(void)
59{ 59{
60 void __iomem *scu_base = scu_base_addr(); 60 void __iomem *scu_base = scu_base_addr();
61 61
62#ifdef CONFIG_HAVE_ARM_TWD
63 /* twd_base needs to be initialized before percpu_timer_setup() */
64 twd_base = (void __iomem *)0xf0000600;
65#endif
66
62 return scu_get_core_count(scu_base); 67 return scu_get_core_count(scu_base);
63} 68}
64 69
@@ -82,10 +87,6 @@ int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
82 87
83void __init sh73a0_smp_prepare_cpus(void) 88void __init sh73a0_smp_prepare_cpus(void)
84{ 89{
85#ifdef CONFIG_HAVE_ARM_TWD
86 twd_base = (void __iomem *)0xf0000600;
87#endif
88
89 scu_enable(scu_base_addr()); 90 scu_enable(scu_base_addr());
90 91
91 /* Map the reset vector (in headsmp.S) */ 92 /* Map the reset vector (in headsmp.S) */
diff --git a/arch/arm/mach-shmobile/suspend.c b/arch/arm/mach-shmobile/suspend.c
new file mode 100644
index 000000000000..c1febe13f709
--- /dev/null
+++ b/arch/arm/mach-shmobile/suspend.c
@@ -0,0 +1,47 @@
1/*
2 * Suspend-to-RAM support code for SH-Mobile ARM
3 *
4 * Copyright (C) 2011 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/pm.h>
12#include <linux/suspend.h>
13#include <linux/module.h>
14#include <linux/err.h>
15#include <asm/system.h>
16#include <asm/io.h>
17
18static int shmobile_suspend_default_enter(suspend_state_t suspend_state)
19{
20 cpu_do_idle();
21 return 0;
22}
23
24static int shmobile_suspend_begin(suspend_state_t state)
25{
26 disable_hlt();
27 return 0;
28}
29
30static void shmobile_suspend_end(void)
31{
32 enable_hlt();
33}
34
35struct platform_suspend_ops shmobile_suspend_ops = {
36 .begin = shmobile_suspend_begin,
37 .end = shmobile_suspend_end,
38 .enter = shmobile_suspend_default_enter,
39 .valid = suspend_valid_only_mem,
40};
41
42static int __init shmobile_suspend_init(void)
43{
44 suspend_set_ops(&shmobile_suspend_ops);
45 return 0;
46}
47late_initcall(shmobile_suspend_init);
diff --git a/arch/arm/mach-tegra/include/mach/sdhci.h b/arch/arm/mach-tegra/include/mach/sdhci.h
index 3ad086e859c3..4231bc7b8652 100644
--- a/arch/arm/mach-tegra/include/mach/sdhci.h
+++ b/arch/arm/mach-tegra/include/mach/sdhci.h
@@ -24,6 +24,7 @@ struct tegra_sdhci_platform_data {
24 int wp_gpio; 24 int wp_gpio;
25 int power_gpio; 25 int power_gpio;
26 int is_8bit; 26 int is_8bit;
27 int pm_flags;
27}; 28};
28 29
29#endif 30#endif
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 58626013aa32..54429d015954 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -12,9 +12,12 @@ menu "Ux500 SoC"
12 12
13config UX500_SOC_DB5500 13config UX500_SOC_DB5500
14 bool "DB5500" 14 bool "DB5500"
15 select MFD_DB5500_PRCMU
15 16
16config UX500_SOC_DB8500 17config UX500_SOC_DB8500
17 bool "DB8500" 18 bool "DB8500"
19 select MFD_DB8500_PRCMU
20 select REGULATOR_DB8500_PRCMU
18 21
19endmenu 22endmenu
20 23
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index b549a8fb4231..1694916e6822 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -5,7 +5,7 @@
5obj-y := clock.o cpu.o devices.o devices-common.o \ 5obj-y := clock.o cpu.o devices.o devices-common.o \
6 id.o usb.o 6 id.o usb.o
7obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o 7obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o
8obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o 8obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o
9obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \ 9obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \
10 board-mop500-regulators.o \ 10 board-mop500-regulators.o \
11 board-mop500-uib.o board-mop500-stuib.o \ 11 board-mop500-uib.o board-mop500-stuib.o \
@@ -17,4 +17,4 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
17obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o 17obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
18obj-$(CONFIG_U5500_MODEM_IRQ) += modem-irq-db5500.o 18obj-$(CONFIG_U5500_MODEM_IRQ) += modem-irq-db5500.o
19obj-$(CONFIG_U5500_MBOX) += mbox-db5500.o 19obj-$(CONFIG_U5500_MBOX) += mbox-db5500.o
20obj-$(CONFIG_CPU_FREQ) += cpufreq.o 20
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index bf0b02414e5b..7c6cb4fa47a9 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -99,8 +99,11 @@ static void sdi0_configure(void)
99 gpio_direction_output(sdi0_vsel, 0); 99 gpio_direction_output(sdi0_vsel, 0);
100 gpio_direction_output(sdi0_en, 1); 100 gpio_direction_output(sdi0_en, 1);
101 101
102 /* Add the device */ 102 /* Add the device, force v2 to subrevision 1 */
103 db8500_add_sdi0(&mop500_sdi0_data); 103 if (cpu_is_u8500v2())
104 db8500_add_sdi0(&mop500_sdi0_data, 0x10480180);
105 else
106 db8500_add_sdi0(&mop500_sdi0_data, 0);
104} 107}
105 108
106void mop500_sdi_tc35892_init(void) 109void mop500_sdi_tc35892_init(void)
@@ -188,13 +191,18 @@ static struct mmci_platform_data mop500_sdi4_data = {
188 191
189void __init mop500_sdi_init(void) 192void __init mop500_sdi_init(void)
190{ 193{
194 u32 periphid = 0;
195
196 /* v2 has a new version of this block that need to be forced */
197 if (cpu_is_u8500v2())
198 periphid = 0x10480180;
191 /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */ 199 /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
192 if (!cpu_is_u8500v10()) 200 if (!cpu_is_u8500v10())
193 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED; 201 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
194 db8500_add_sdi2(&mop500_sdi2_data); 202 db8500_add_sdi2(&mop500_sdi2_data, periphid);
195 203
196 /* On-board eMMC */ 204 /* On-board eMMC */
197 db8500_add_sdi4(&mop500_sdi4_data); 205 db8500_add_sdi4(&mop500_sdi4_data, periphid);
198 206
199 if (machine_is_hrefv60()) { 207 if (machine_is_hrefv60()) {
200 mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; 208 mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index c9dc2eff3cb2..c01bc19e3c5e 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -188,6 +188,8 @@ void __init u5500_map_io(void)
188 ux500_map_io(); 188 ux500_map_io();
189 189
190 iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc)); 190 iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc));
191
192 _PRCMU_BASE = __io_address(U5500_PRCMU_BASE);
191} 193}
192 194
193static int usb_db5500_rx_dma_cfg[] = { 195static int usb_db5500_rx_dma_cfg[] = {
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 516126cb357d..c3c417656bd9 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -87,6 +87,8 @@ void __init u8500_map_io(void)
87 iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc)); 87 iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc));
88 else if (cpu_is_u8500v2()) 88 else if (cpu_is_u8500v2())
89 iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc)); 89 iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
90
91 _PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
90} 92}
91 93
92static struct resource db8500_pmu_resources[] = { 94static struct resource db8500_pmu_resources[] = {
@@ -129,9 +131,14 @@ static struct platform_device db8500_pmu_device = {
129 .dev.platform_data = &db8500_pmu_platdata, 131 .dev.platform_data = &db8500_pmu_platdata,
130}; 132};
131 133
134static struct platform_device db8500_prcmu_device = {
135 .name = "db8500-prcmu",
136};
137
132static struct platform_device *platform_devs[] __initdata = { 138static struct platform_device *platform_devs[] __initdata = {
133 &u8500_dma40_device, 139 &u8500_dma40_device,
134 &db8500_pmu_device, 140 &db8500_pmu_device,
141 &db8500_prcmu_device,
135}; 142};
136 143
137static resource_size_t __initdata db8500_gpio_base[] = { 144static resource_size_t __initdata db8500_gpio_base[] = {
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 5a43107c6232..1da23bb87c16 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -8,6 +8,8 @@
8#include <linux/platform_device.h> 8#include <linux/platform_device.h>
9#include <linux/io.h> 9#include <linux/io.h>
10#include <linux/clk.h> 10#include <linux/clk.h>
11#include <linux/mfd/db8500-prcmu.h>
12#include <linux/mfd/db5500-prcmu.h>
11 13
12#include <asm/cacheflush.h> 14#include <asm/cacheflush.h>
13#include <asm/hardware/cache-l2x0.h> 15#include <asm/hardware/cache-l2x0.h>
@@ -19,10 +21,11 @@
19#include <mach/hardware.h> 21#include <mach/hardware.h>
20#include <mach/setup.h> 22#include <mach/setup.h>
21#include <mach/devices.h> 23#include <mach/devices.h>
22#include <mach/prcmu.h>
23 24
24#include "clock.h" 25#include "clock.h"
25 26
27void __iomem *_PRCMU_BASE;
28
26#ifdef CONFIG_CACHE_L2X0 29#ifdef CONFIG_CACHE_L2X0
27static void __iomem *l2x0_base; 30static void __iomem *l2x0_base;
28#endif 31#endif
@@ -47,6 +50,8 @@ void __init ux500_init_irq(void)
47 * Init clocks here so that they are available for system timer 50 * Init clocks here so that they are available for system timer
48 * initialization. 51 * initialization.
49 */ 52 */
53 if (cpu_is_u5500())
54 db5500_prcmu_early_init();
50 if (cpu_is_u8500()) 55 if (cpu_is_u8500())
51 prcmu_early_init(); 56 prcmu_early_init();
52 clk_init(); 57 clk_init();
diff --git a/arch/arm/mach-ux500/cpufreq.c b/arch/arm/mach-ux500/cpufreq.c
deleted file mode 100644
index 5c5b747f134d..000000000000
--- a/arch/arm/mach-ux500/cpufreq.c
+++ /dev/null
@@ -1,211 +0,0 @@
1/*
2 * CPU frequency scaling for u8500
3 * Inspired by linux/arch/arm/mach-davinci/cpufreq.c
4 *
5 * Copyright (C) STMicroelectronics 2009
6 * Copyright (C) ST-Ericsson SA 2010
7 *
8 * License Terms: GNU General Public License v2
9 *
10 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
11 * Author: Martin Persson <martin.persson@stericsson.com>
12 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
13 *
14 */
15
16#include <linux/platform_device.h>
17#include <linux/kernel.h>
18#include <linux/cpufreq.h>
19#include <linux/delay.h>
20
21#include <mach/hardware.h>
22#include <mach/prcmu.h>
23#include <mach/prcmu-defs.h>
24
25#define DRIVER_NAME "cpufreq-u8500"
26#define CPUFREQ_NAME "u8500"
27
28static struct device *dev;
29
30static struct cpufreq_frequency_table freq_table[] = {
31 [0] = {
32 .index = 0,
33 .frequency = 200000,
34 },
35 [1] = {
36 .index = 1,
37 .frequency = 300000,
38 },
39 [2] = {
40 .index = 2,
41 .frequency = 600000,
42 },
43 [3] = {
44 /* Used for CPU_OPP_MAX, if available */
45 .index = 3,
46 .frequency = CPUFREQ_TABLE_END,
47 },
48 [4] = {
49 .index = 4,
50 .frequency = CPUFREQ_TABLE_END,
51 },
52};
53
54static enum prcmu_cpu_opp index2opp[] = {
55 CPU_OPP_EXT_CLK,
56 CPU_OPP_50,
57 CPU_OPP_100,
58 CPU_OPP_MAX
59};
60
61static int u8500_cpufreq_verify_speed(struct cpufreq_policy *policy)
62{
63 return cpufreq_frequency_table_verify(policy, freq_table);
64}
65
66static int u8500_cpufreq_target(struct cpufreq_policy *policy,
67 unsigned int target_freq,
68 unsigned int relation)
69{
70 struct cpufreq_freqs freqs;
71 unsigned int index;
72 int ret = 0;
73
74 /*
75 * Ensure desired rate is within allowed range. Some govenors
76 * (ondemand) will just pass target_freq=0 to get the minimum.
77 */
78 if (target_freq < policy->cpuinfo.min_freq)
79 target_freq = policy->cpuinfo.min_freq;
80 if (target_freq > policy->cpuinfo.max_freq)
81 target_freq = policy->cpuinfo.max_freq;
82
83 ret = cpufreq_frequency_table_target(policy, freq_table,
84 target_freq, relation, &index);
85 if (ret < 0) {
86 dev_err(dev, "Could not look up next frequency\n");
87 return ret;
88 }
89
90 freqs.old = policy->cur;
91 freqs.new = freq_table[index].frequency;
92 freqs.cpu = policy->cpu;
93
94 if (freqs.old == freqs.new) {
95 dev_dbg(dev, "Current and target frequencies are equal\n");
96 return 0;
97 }
98
99 dev_dbg(dev, "transition: %u --> %u\n", freqs.old, freqs.new);
100 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
101
102 ret = prcmu_set_cpu_opp(index2opp[index]);
103 if (ret < 0) {
104 dev_err(dev, "Failed to set OPP level\n");
105 return ret;
106 }
107
108 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
109
110 return ret;
111}
112
113static unsigned int u8500_cpufreq_getspeed(unsigned int cpu)
114{
115 int i;
116
117 for (i = 0; prcmu_get_cpu_opp() != index2opp[i]; i++)
118 ;
119 return freq_table[i].frequency;
120}
121
122static int __cpuinit u8500_cpu_init(struct cpufreq_policy *policy)
123{
124 int res;
125
126 BUILD_BUG_ON(ARRAY_SIZE(index2opp) + 1 != ARRAY_SIZE(freq_table));
127
128 if (cpu_is_u8500v2()) {
129 freq_table[1].frequency = 400000;
130 freq_table[2].frequency = 800000;
131 if (prcmu_has_arm_maxopp())
132 freq_table[3].frequency = 1000000;
133 }
134
135 /* get policy fields based on the table */
136 res = cpufreq_frequency_table_cpuinfo(policy, freq_table);
137 if (!res)
138 cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
139 else {
140 dev_err(dev, "u8500-cpufreq : Failed to read policy table\n");
141 return res;
142 }
143
144 policy->min = policy->cpuinfo.min_freq;
145 policy->max = policy->cpuinfo.max_freq;
146 policy->cur = u8500_cpufreq_getspeed(policy->cpu);
147 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
148
149 /*
150 * FIXME : Need to take time measurement across the target()
151 * function with no/some/all drivers in the notification
152 * list.
153 */
154 policy->cpuinfo.transition_latency = 200 * 1000; /* in ns */
155
156 /* policy sharing between dual CPUs */
157 cpumask_copy(policy->cpus, &cpu_present_map);
158
159 policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
160
161 return res;
162}
163
164static struct freq_attr *u8500_cpufreq_attr[] = {
165 &cpufreq_freq_attr_scaling_available_freqs,
166 NULL,
167};
168static int u8500_cpu_exit(struct cpufreq_policy *policy)
169{
170 cpufreq_frequency_table_put_attr(policy->cpu);
171 return 0;
172}
173
174static struct cpufreq_driver u8500_driver = {
175 .owner = THIS_MODULE,
176 .flags = CPUFREQ_STICKY,
177 .verify = u8500_cpufreq_verify_speed,
178 .target = u8500_cpufreq_target,
179 .get = u8500_cpufreq_getspeed,
180 .init = u8500_cpu_init,
181 .exit = u8500_cpu_exit,
182 .name = CPUFREQ_NAME,
183 .attr = u8500_cpufreq_attr,
184};
185
186static int __init u8500_cpufreq_probe(struct platform_device *pdev)
187{
188 dev = &pdev->dev;
189 return cpufreq_register_driver(&u8500_driver);
190}
191
192static int __exit u8500_cpufreq_remove(struct platform_device *pdev)
193{
194 return cpufreq_unregister_driver(&u8500_driver);
195}
196
197static struct platform_driver u8500_cpufreq_driver = {
198 .driver = {
199 .name = DRIVER_NAME,
200 .owner = THIS_MODULE,
201 },
202 .remove = __exit_p(u8500_cpufreq_remove),
203};
204
205static int __init u8500_cpufreq_init(void)
206{
207 return platform_driver_probe(&u8500_cpufreq_driver,
208 &u8500_cpufreq_probe);
209}
210
211device_initcall(u8500_cpufreq_init);
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index c719b5a1d913..7825705033bf 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -28,18 +28,20 @@ dbx500_add_msp_spi(const char *name, resource_size_t base, int irq,
28 28
29static inline struct amba_device * 29static inline struct amba_device *
30dbx500_add_spi(const char *name, resource_size_t base, int irq, 30dbx500_add_spi(const char *name, resource_size_t base, int irq,
31 struct spi_master_cntlr *pdata) 31 struct spi_master_cntlr *pdata,
32 u32 periphid)
32{ 33{
33 return dbx500_add_amba_device(name, base, irq, pdata, 0); 34 return dbx500_add_amba_device(name, base, irq, pdata, periphid);
34} 35}
35 36
36struct mmci_platform_data; 37struct mmci_platform_data;
37 38
38static inline struct amba_device * 39static inline struct amba_device *
39dbx500_add_sdi(const char *name, resource_size_t base, int irq, 40dbx500_add_sdi(const char *name, resource_size_t base, int irq,
40 struct mmci_platform_data *pdata) 41 struct mmci_platform_data *pdata,
42 u32 periphid)
41{ 43{
42 return dbx500_add_amba_device(name, base, irq, pdata, 0); 44 return dbx500_add_amba_device(name, base, irq, pdata, periphid);
43} 45}
44 46
45struct amba_pl011_data; 47struct amba_pl011_data;
diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h
index 94627f7783b0..0c4bccd02b90 100644
--- a/arch/arm/mach-ux500/devices-db5500.h
+++ b/arch/arm/mach-ux500/devices-db5500.h
@@ -38,24 +38,34 @@
38 ux500_add_usb(U5500_USBOTG_BASE, IRQ_DB5500_USBOTG, rx_cfg, tx_cfg) 38 ux500_add_usb(U5500_USBOTG_BASE, IRQ_DB5500_USBOTG, rx_cfg, tx_cfg)
39 39
40#define db5500_add_sdi0(pdata) \ 40#define db5500_add_sdi0(pdata) \
41 dbx500_add_sdi("sdi0", U5500_SDI0_BASE, IRQ_DB5500_SDMMC0, pdata) 41 dbx500_add_sdi("sdi0", U5500_SDI0_BASE, IRQ_DB5500_SDMMC0, pdata, \
42 0x10480180)
42#define db5500_add_sdi1(pdata) \ 43#define db5500_add_sdi1(pdata) \
43 dbx500_add_sdi("sdi1", U5500_SDI1_BASE, IRQ_DB5500_SDMMC1, pdata) 44 dbx500_add_sdi("sdi1", U5500_SDI1_BASE, IRQ_DB5500_SDMMC1, pdata, \
45 0x10480180)
44#define db5500_add_sdi2(pdata) \ 46#define db5500_add_sdi2(pdata) \
45 dbx500_add_sdi("sdi2", U5500_SDI2_BASE, IRQ_DB5500_SDMMC2, pdata) 47 dbx500_add_sdi("sdi2", U5500_SDI2_BASE, IRQ_DB5500_SDMMC2, pdata \
48 0x10480180)
46#define db5500_add_sdi3(pdata) \ 49#define db5500_add_sdi3(pdata) \
47 dbx500_add_sdi("sdi3", U5500_SDI3_BASE, IRQ_DB5500_SDMMC3, pdata) 50 dbx500_add_sdi("sdi3", U5500_SDI3_BASE, IRQ_DB5500_SDMMC3, pdata \
51 0x10480180)
48#define db5500_add_sdi4(pdata) \ 52#define db5500_add_sdi4(pdata) \
49 dbx500_add_sdi("sdi4", U5500_SDI4_BASE, IRQ_DB5500_SDMMC4, pdata) 53 dbx500_add_sdi("sdi4", U5500_SDI4_BASE, IRQ_DB5500_SDMMC4, pdata \
54 0x10480180)
50 55
56/* This one has a bad peripheral ID in the U5500 silicon */
51#define db5500_add_spi0(pdata) \ 57#define db5500_add_spi0(pdata) \
52 dbx500_add_spi("spi0", U5500_SPI0_BASE, IRQ_DB5500_SPI0, pdata) 58 dbx500_add_spi("spi0", U5500_SPI0_BASE, IRQ_DB5500_SPI0, pdata, \
59 0x10080023)
53#define db5500_add_spi1(pdata) \ 60#define db5500_add_spi1(pdata) \
54 dbx500_add_spi("spi1", U5500_SPI1_BASE, IRQ_DB5500_SPI1, pdata) 61 dbx500_add_spi("spi1", U5500_SPI1_BASE, IRQ_DB5500_SPI1, pdata, \
62 0x10080023)
55#define db5500_add_spi2(pdata) \ 63#define db5500_add_spi2(pdata) \
56 dbx500_add_spi("spi2", U5500_SPI2_BASE, IRQ_DB5500_SPI2, pdata) 64 dbx500_add_spi("spi2", U5500_SPI2_BASE, IRQ_DB5500_SPI2, pdata \
65 0x10080023)
57#define db5500_add_spi3(pdata) \ 66#define db5500_add_spi3(pdata) \
58 dbx500_add_spi("spi3", U5500_SPI3_BASE, IRQ_DB5500_SPI3, pdata) 67 dbx500_add_spi("spi3", U5500_SPI3_BASE, IRQ_DB5500_SPI3, pdata \
68 0x10080023)
59 69
60#define db5500_add_uart0(plat) \ 70#define db5500_add_uart0(plat) \
61 dbx500_add_uart("uart0", U5500_UART0_BASE, IRQ_DB5500_UART0, plat) 71 dbx500_add_uart("uart0", U5500_UART0_BASE, IRQ_DB5500_UART0, plat)
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index 9cc6f8f5d3e6..cbd4a9ae8109 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -25,7 +25,7 @@ static inline struct amba_device *
25db8500_add_ssp(const char *name, resource_size_t base, int irq, 25db8500_add_ssp(const char *name, resource_size_t base, int irq,
26 struct pl022_ssp_controller *pdata) 26 struct pl022_ssp_controller *pdata)
27{ 27{
28 return dbx500_add_amba_device(name, base, irq, pdata, SSP_PER_ID); 28 return dbx500_add_amba_device(name, base, irq, pdata, 0);
29} 29}
30 30
31 31
@@ -64,18 +64,18 @@ db8500_add_ssp(const char *name, resource_size_t base, int irq,
64#define db8500_add_usb(rx_cfg, tx_cfg) \ 64#define db8500_add_usb(rx_cfg, tx_cfg) \
65 ux500_add_usb(U8500_USBOTG_BASE, IRQ_DB8500_USBOTG, rx_cfg, tx_cfg) 65 ux500_add_usb(U8500_USBOTG_BASE, IRQ_DB8500_USBOTG, rx_cfg, tx_cfg)
66 66
67#define db8500_add_sdi0(pdata) \ 67#define db8500_add_sdi0(pdata, pid) \
68 dbx500_add_sdi("sdi0", U8500_SDI0_BASE, IRQ_DB8500_SDMMC0, pdata) 68 dbx500_add_sdi("sdi0", U8500_SDI0_BASE, IRQ_DB8500_SDMMC0, pdata, pid)
69#define db8500_add_sdi1(pdata) \ 69#define db8500_add_sdi1(pdata, pid) \
70 dbx500_add_sdi("sdi1", U8500_SDI1_BASE, IRQ_DB8500_SDMMC1, pdata) 70 dbx500_add_sdi("sdi1", U8500_SDI1_BASE, IRQ_DB8500_SDMMC1, pdata, pid)
71#define db8500_add_sdi2(pdata) \ 71#define db8500_add_sdi2(pdata, pid) \
72 dbx500_add_sdi("sdi2", U8500_SDI2_BASE, IRQ_DB8500_SDMMC2, pdata) 72 dbx500_add_sdi("sdi2", U8500_SDI2_BASE, IRQ_DB8500_SDMMC2, pdata, pid)
73#define db8500_add_sdi3(pdata) \ 73#define db8500_add_sdi3(pdata, pid) \
74 dbx500_add_sdi("sdi3", U8500_SDI3_BASE, IRQ_DB8500_SDMMC3, pdata) 74 dbx500_add_sdi("sdi3", U8500_SDI3_BASE, IRQ_DB8500_SDMMC3, pdata, pid)
75#define db8500_add_sdi4(pdata) \ 75#define db8500_add_sdi4(pdata, pid) \
76 dbx500_add_sdi("sdi4", U8500_SDI4_BASE, IRQ_DB8500_SDMMC4, pdata) 76 dbx500_add_sdi("sdi4", U8500_SDI4_BASE, IRQ_DB8500_SDMMC4, pdata, pid)
77#define db8500_add_sdi5(pdata) \ 77#define db8500_add_sdi5(pdata, pid) \
78 dbx500_add_sdi("sdi5", U8500_SDI5_BASE, IRQ_DB8500_SDMMC5, pdata) 78 dbx500_add_sdi("sdi5", U8500_SDI5_BASE, IRQ_DB8500_SDMMC5, pdata, pid)
79 79
80#define db8500_add_ssp0(pdata) \ 80#define db8500_add_ssp0(pdata) \
81 db8500_add_ssp("ssp0", U8500_SSP0_BASE, IRQ_DB8500_SSP0, pdata) 81 db8500_add_ssp("ssp0", U8500_SSP0_BASE, IRQ_DB8500_SSP0, pdata)
@@ -83,13 +83,13 @@ db8500_add_ssp(const char *name, resource_size_t base, int irq,
83 db8500_add_ssp("ssp1", U8500_SSP1_BASE, IRQ_DB8500_SSP1, pdata) 83 db8500_add_ssp("ssp1", U8500_SSP1_BASE, IRQ_DB8500_SSP1, pdata)
84 84
85#define db8500_add_spi0(pdata) \ 85#define db8500_add_spi0(pdata) \
86 dbx500_add_spi("spi0", U8500_SPI0_BASE, IRQ_DB8500_SPI0, pdata) 86 dbx500_add_spi("spi0", U8500_SPI0_BASE, IRQ_DB8500_SPI0, pdata, 0)
87#define db8500_add_spi1(pdata) \ 87#define db8500_add_spi1(pdata) \
88 dbx500_add_spi("spi1", U8500_SPI1_BASE, IRQ_DB8500_SPI1, pdata) 88 dbx500_add_spi("spi1", U8500_SPI1_BASE, IRQ_DB8500_SPI1, pdata, 0)
89#define db8500_add_spi2(pdata) \ 89#define db8500_add_spi2(pdata) \
90 dbx500_add_spi("spi2", U8500_SPI2_BASE, IRQ_DB8500_SPI2, pdata) 90 dbx500_add_spi("spi2", U8500_SPI2_BASE, IRQ_DB8500_SPI2, pdata, 0)
91#define db8500_add_spi3(pdata) \ 91#define db8500_add_spi3(pdata) \
92 dbx500_add_spi("spi3", U8500_SPI3_BASE, IRQ_DB8500_SPI3, pdata) 92 dbx500_add_spi("spi3", U8500_SPI3_BASE, IRQ_DB8500_SPI3, pdata, 0)
93 93
94#define db8500_add_uart0(pdata) \ 94#define db8500_add_uart0(pdata) \
95 dbx500_add_uart("uart0", U8500_UART0_BASE, IRQ_DB8500_UART0, pdata) 95 dbx500_add_uart("uart0", U8500_UART0_BASE, IRQ_DB8500_UART0, pdata)
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
index bd88c1e74060..6ad983294103 100644
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -17,6 +17,8 @@
17#define U5500_GIC_DIST_BASE 0xA0411000 17#define U5500_GIC_DIST_BASE 0xA0411000
18#define U5500_GIC_CPU_BASE 0xA0410100 18#define U5500_GIC_CPU_BASE 0xA0410100
19#define U5500_DMA_BASE 0x90030000 19#define U5500_DMA_BASE 0x90030000
20#define U5500_STM_BASE 0x90020000
21#define U5500_STM_REG_BASE (U5500_STM_BASE + 0xF000)
20#define U5500_MCDE_BASE 0xA0400000 22#define U5500_MCDE_BASE 0xA0400000
21#define U5500_MODEM_BASE 0xB0000000 23#define U5500_MODEM_BASE 0xB0000000
22#define U5500_L2CC_BASE 0xA0412000 24#define U5500_L2CC_BASE 0xA0412000
@@ -29,7 +31,9 @@
29#define U5500_NAND0_BASE 0x60000000 31#define U5500_NAND0_BASE 0x60000000
30#define U5500_NAND1_BASE 0x70000000 32#define U5500_NAND1_BASE 0x70000000
31#define U5500_TWD_BASE 0xa0410600 33#define U5500_TWD_BASE 0xa0410600
34#define U5500_ICN_BASE 0xA0040000
32#define U5500_B2R2_BASE 0xa0200000 35#define U5500_B2R2_BASE 0xa0200000
36#define U5500_BOOT_ROM_BASE 0x90000000
33 37
34#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000) 38#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000)
35#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000) 39#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000)
@@ -60,6 +64,7 @@
60#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) 64#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000)
61#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) 65#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000)
62#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) 66#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000)
67#define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000)
63 68
64#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000) 69#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000)
65#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000) 70#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000)
@@ -83,7 +88,7 @@
83#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000) 88#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000)
84#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000) 89#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000)
85#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000) 90#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000)
86#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5000) 91#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5100)
87#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000) 92#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000)
88#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000) 93#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000)
89#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000) 94#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000)
@@ -114,8 +119,19 @@
114#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20) 119#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20)
115#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F) 120#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F)
116 121
117#define U5500_ESRAM_BASE 0x40000000 122#define U5500_ACCCON_BASE_SEC (0xBFFF0000)
123#define U5500_ACCCON_BASE (0xBFFF1000)
124#define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020)
125#define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC)
126
127#define U5500_ESRAM_BASE 0x40000000
118#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000 128#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000
119#define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET) 129#define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET)
120 130
131#define U5500_MCDE_SIZE 0x1000
132#define U5500_DSI_LINK_SIZE 0x1000
133#define U5500_DSI_LINK_COUNT 0x2
134#define U5500_DSI_LINK1_BASE (U5500_MCDE_BASE + U5500_MCDE_SIZE)
135#define U5500_DSI_LINK2_BASE (U5500_DSI_LINK1_BASE + U5500_DSI_LINK_SIZE)
136
121#endif 137#endif
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 16647b255378..049997109cf9 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -15,8 +15,13 @@
15#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE) 15#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)
16#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE) 16#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)
17#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE) 17#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)
18/* Use bank 4 for DMA LCPA */ 18/*
19#define U8500_DMA_LCPA_BASE U8500_ESRAM_BANK4 19 * on V1 DMA uses 4KB for logical parameters position is right after the 64KB
20 * reserved for security
21 */
22#define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
23
24#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)
20#define U8500_DMA_LCPA_BASE_ED (U8500_ESRAM_BANK4 + 0x4000) 25#define U8500_DMA_LCPA_BASE_ED (U8500_ESRAM_BANK4 + 0x4000)
21 26
22#define U8500_PER3_BASE 0x80000000 27#define U8500_PER3_BASE 0x80000000
@@ -27,9 +32,12 @@
27#define U8500_B2R2_BASE 0x80130000 32#define U8500_B2R2_BASE 0x80130000
28#define U8500_HSEM_BASE 0x80140000 33#define U8500_HSEM_BASE 0x80140000
29#define U8500_PER4_BASE 0x80150000 34#define U8500_PER4_BASE 0x80150000
35#define U8500_TPIU_BASE 0x80190000
30#define U8500_ICN_BASE 0x81000000 36#define U8500_ICN_BASE 0x81000000
31 37
32#define U8500_BOOT_ROM_BASE 0x90000000 38#define U8500_BOOT_ROM_BASE 0x90000000
39/* ASIC ID is at 0xbf4 offset within this region */
40#define U8500_ASIC_ID_BASE 0x9001D000
33 41
34#define U8500_PER6_BASE 0xa03c0000 42#define U8500_PER6_BASE 0xa03c0000
35#define U8500_PER5_BASE 0xa03e0000 43#define U8500_PER5_BASE 0xa03e0000
@@ -70,13 +78,15 @@
70 78
71/* per6 base addresses */ 79/* per6 base addresses */
72#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) 80#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
73#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000) 81#define U8500_HASH0_BASE (U8500_PER6_BASE + 0x1000)
74#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000) 82#define U8500_HASH1_BASE (U8500_PER6_BASE + 0x2000)
83#define U8500_PKA_BASE (U8500_PER6_BASE + 0x4000)
84#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x5100)
75#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */ 85#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */
76#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */ 86#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */
77#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */ 87#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */
78#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000) 88#define U8500_CRYP0_BASE (U8500_PER6_BASE + 0xa000)
79#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000) 89#define U8500_CRYP1_BASE (U8500_PER6_BASE + 0xb000)
80#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) 90#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
81 91
82/* per5 base addresses */ 92/* per5 base addresses */
@@ -93,7 +103,8 @@
93#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) 103#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
94#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) 104#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
95#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000) 105#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000)
96#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) 106#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
107#define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000)
97 108
98/* per3 base addresses */ 109/* per3 base addresses */
99#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) 110#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
@@ -124,6 +135,7 @@
124#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000) 135#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
125#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000) 136#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
126#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000) 137#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
138#define U8500_MSP3_BASE (U8500_PER1_BASE + 0x5000)
127#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000) 139#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
128#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000) 140#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
129#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000) 141#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
@@ -143,4 +155,15 @@
143#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80) 155#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80)
144#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE 156#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE
145 157
158#define U8500_MCDE_SIZE 0x1000
159#define U8500_DSI_LINK_SIZE 0x1000
160#define U8500_DSI_LINK1_BASE (U8500_MCDE_BASE + U8500_MCDE_SIZE)
161#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
162#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
163#define U8500_DSI_LINK_COUNT 0x3
164
165/* Modem and APE physical addresses */
166#define U8500_MODEM_BASE 0xe000000
167#define U8500_APE_BASE 0x6000000
168
146#endif 169#endif
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index bf63f2631ba0..470ac52663d6 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -29,12 +29,10 @@
29#include <mach/db8500-regs.h> 29#include <mach/db8500-regs.h>
30#include <mach/db5500-regs.h> 30#include <mach/db5500-regs.h>
31 31
32/* ST-Ericsson modified pl022 id */
33#define SSP_PER_ID 0x01080022
34
35#ifndef __ASSEMBLY__ 32#ifndef __ASSEMBLY__
36 33
37#include <mach/id.h> 34#include <mach/id.h>
35extern void __iomem *_PRCMU_BASE;
38 36
39#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) 37#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
40 38
diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h
index f1288d10b6ab..02b541a37ee5 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/include/mach/id.h
@@ -75,6 +75,26 @@ static inline bool __attribute_const__ cpu_is_u8500v2(void)
75 return cpu_is_u8500() && ((dbx500_revision() & 0xf0) == 0xB0); 75 return cpu_is_u8500() && ((dbx500_revision() & 0xf0) == 0xB0);
76} 76}
77 77
78static inline bool cpu_is_u8500v20(void)
79{
80 return cpu_is_u8500() && (dbx500_revision() == 0xB0);
81}
82
83static inline bool cpu_is_u8500v21(void)
84{
85 return cpu_is_u8500() && (dbx500_revision() == 0xB1);
86}
87
88static inline bool cpu_is_u8500v20_or_later(void)
89{
90 return cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11();
91}
92
93static inline bool ux500_is_svp(void)
94{
95 return false;
96}
97
78#define ux500_unknown_soc() BUG() 98#define ux500_unknown_soc() BUG()
79 99
80#endif 100#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
index 97ef55f84934..47969909836c 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -50,6 +50,11 @@
50 50
51#define MOP500_IRQ_END MOP500_NR_IRQS 51#define MOP500_IRQ_END MOP500_NR_IRQS
52 52
53/*
54 * We may have several boards, but only one will run at a
55 * time, so the one with most IRQs will bump this ahead,
56 * but the IRQ_BOARD_START remains the same for either board.
57 */
53#if MOP500_IRQ_END > IRQ_BOARD_END 58#if MOP500_IRQ_END > IRQ_BOARD_END
54#undef IRQ_BOARD_END 59#undef IRQ_BOARD_END
55#define IRQ_BOARD_END MOP500_IRQ_END 60#define IRQ_BOARD_END MOP500_IRQ_END
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
new file mode 100644
index 000000000000..29d972c7717b
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
@@ -0,0 +1,21 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __MACH_IRQS_BOARD_U5500_H
8#define __MACH_IRQS_BOARD_U5500_H
9
10#define AB5500_NR_IRQS 5
11#define IRQ_AB5500_BASE IRQ_BOARD_START
12#define IRQ_AB5500_END (IRQ_AB5500_BASE + AB5500_NR_IRQS)
13
14#define U5500_IRQ_END IRQ_AB5500_END
15
16#if IRQ_BOARD_END < U5500_IRQ_END
17#undef IRQ_BOARD_END
18#define IRQ_BOARD_END U5500_IRQ_END
19#endif
20
21#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
index bfa123dbec3b..77239776a6f2 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-db5500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
@@ -83,4 +83,31 @@
83#define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125) 83#define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125)
84#define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126) 84#define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126)
85 85
86#ifdef CONFIG_UX500_SOC_DB5500
87
88/*
89 * After the GPIO ones we reserve a range of IRQ:s in which virtual
90 * IRQ:s representing modem IRQ:s can be allocated
91 */
92#define IRQ_MODEM_EVENTS_BASE IRQ_SOC_START
93#define IRQ_MODEM_EVENTS_NBR 72
94#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
95
96/* List of virtual IRQ:s that are allocated from the range above */
97#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43)
98#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45)
99#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41)
100
101/*
102 * We may have several SoCs, but only one will run at a
103 * time, so the one with most IRQs will bump this ahead,
104 * but the IRQ_SOC_START remains the same for either SoC.
105 */
106#if IRQ_SOC_END < IRQ_MODEM_EVENTS_END
107#undef IRQ_SOC_END
108#define IRQ_SOC_END IRQ_MODEM_EVENTS_END
109#endif
110
111#endif /* CONFIG_UX500_SOC_DB5500 */
112
86#endif 113#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
index 8b5d9f0a1633..68bc14974608 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-db8500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
@@ -93,4 +93,58 @@
93#define IRQ_DB8500_GPIO7 (IRQ_SHPI_START + 126) 93#define IRQ_DB8500_GPIO7 (IRQ_SHPI_START + 126)
94#define IRQ_DB8500_GPIO8 (IRQ_SHPI_START + 127) 94#define IRQ_DB8500_GPIO8 (IRQ_SHPI_START + 127)
95 95
96#define IRQ_CA_WAKE_REQ_ED (IRQ_SHPI_START + 71)
97#define IRQ_AC_READ_NOTIFICATION_0_ED (IRQ_SHPI_START + 66)
98#define IRQ_AC_READ_NOTIFICATION_1_ED (IRQ_SHPI_START + 64)
99#define IRQ_CA_MSG_PEND_NOTIFICATION_0_ED (IRQ_SHPI_START + 67)
100#define IRQ_CA_MSG_PEND_NOTIFICATION_1_ED (IRQ_SHPI_START + 65)
101
102#define IRQ_CA_WAKE_REQ_V1 (IRQ_SHPI_START + 83)
103#define IRQ_AC_READ_NOTIFICATION_0_V1 (IRQ_SHPI_START + 78)
104#define IRQ_AC_READ_NOTIFICATION_1_V1 (IRQ_SHPI_START + 76)
105#define IRQ_CA_MSG_PEND_NOTIFICATION_0_V1 (IRQ_SHPI_START + 79)
106#define IRQ_CA_MSG_PEND_NOTIFICATION_1_V1 (IRQ_SHPI_START + 77)
107
108#ifdef CONFIG_UX500_SOC_DB8500
109
110/* Virtual interrupts corresponding to the PRCMU wakeups. */
111#define IRQ_PRCMU_BASE IRQ_SOC_START
112#define NUM_PRCMU_WAKEUPS (IRQ_PRCMU_END - IRQ_PRCMU_BASE)
113
114#define IRQ_PRCMU_RTC (IRQ_PRCMU_BASE)
115#define IRQ_PRCMU_RTT0 (IRQ_PRCMU_BASE + 1)
116#define IRQ_PRCMU_RTT1 (IRQ_PRCMU_BASE + 2)
117#define IRQ_PRCMU_HSI0 (IRQ_PRCMU_BASE + 3)
118#define IRQ_PRCMU_HSI1 (IRQ_PRCMU_BASE + 4)
119#define IRQ_PRCMU_CA_WAKE (IRQ_PRCMU_BASE + 5)
120#define IRQ_PRCMU_USB (IRQ_PRCMU_BASE + 6)
121#define IRQ_PRCMU_ABB (IRQ_PRCMU_BASE + 7)
122#define IRQ_PRCMU_ABB_FIFO (IRQ_PRCMU_BASE + 8)
123#define IRQ_PRCMU_ARM (IRQ_PRCMU_BASE + 9)
124#define IRQ_PRCMU_MODEM_SW_RESET_REQ (IRQ_PRCMU_BASE + 10)
125#define IRQ_PRCMU_GPIO0 (IRQ_PRCMU_BASE + 11)
126#define IRQ_PRCMU_GPIO1 (IRQ_PRCMU_BASE + 12)
127#define IRQ_PRCMU_GPIO2 (IRQ_PRCMU_BASE + 13)
128#define IRQ_PRCMU_GPIO3 (IRQ_PRCMU_BASE + 14)
129#define IRQ_PRCMU_GPIO4 (IRQ_PRCMU_BASE + 15)
130#define IRQ_PRCMU_GPIO5 (IRQ_PRCMU_BASE + 16)
131#define IRQ_PRCMU_GPIO6 (IRQ_PRCMU_BASE + 17)
132#define IRQ_PRCMU_GPIO7 (IRQ_PRCMU_BASE + 18)
133#define IRQ_PRCMU_GPIO8 (IRQ_PRCMU_BASE + 19)
134#define IRQ_PRCMU_CA_SLEEP (IRQ_PRCMU_BASE + 20)
135#define IRQ_PRCMU_HOTMON_LOW (IRQ_PRCMU_BASE + 21)
136#define IRQ_PRCMU_HOTMON_HIGH (IRQ_PRCMU_BASE + 22)
137#define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23)
138
139/*
140 * We may have several SoCs, but only one will run at a
141 * time, so the one with most IRQs will bump this ahead,
142 * but the IRQ_SOC_START remains the same for either SoC.
143 */
144#if IRQ_SOC_END < IRQ_PRCMU_END
145#undef IRQ_SOC_END
146#define IRQ_SOC_END IRQ_PRCMU_END
147#endif
148
149#endif /* CONFIG_UX500_SOC_DB8500 */
96#endif 150#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index ba1294c13c4d..9db68d264c5f 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -10,49 +10,47 @@
10#ifndef ASM_ARCH_IRQS_H 10#ifndef ASM_ARCH_IRQS_H
11#define ASM_ARCH_IRQS_H 11#define ASM_ARCH_IRQS_H
12 12
13#include <mach/irqs-db5500.h> 13#include <mach/hardware.h>
14#include <mach/irqs-db8500.h>
15 14
16#define IRQ_LOCALTIMER 29 15#define IRQ_LOCALTIMER 29
17#define IRQ_LOCALWDOG 30 16#define IRQ_LOCALWDOG 30
18 17
19/* Shared Peripheral Interrupt (SHPI) */ 18/* Shared Peripheral Interrupt (SHPI) */
20#define IRQ_SHPI_START 32 19#define IRQ_SHPI_START 32
21 20
22/* Interrupt numbers generic for shared peripheral */ 21/*
22 * MTU0 preserved for now until plat-nomadik is taught not to use it. Don't
23 * add any other IRQs here, use the irqs-dbx500.h files.
24 */
23#define IRQ_MTU0 (IRQ_SHPI_START + 4) 25#define IRQ_MTU0 (IRQ_SHPI_START + 4)
24 26
25/* There are 128 shared peripheral interrupts assigned to 27#define DBX500_NR_INTERNAL_IRQS 160
26 * INTID[160:32]. The first 32 interrupts are reserved.
27 */
28#define DBX500_NR_INTERNAL_IRQS 161
29 28
30/* After chip-specific IRQ numbers we have the GPIO ones */ 29/* After chip-specific IRQ numbers we have the GPIO ones */
31#define NOMADIK_NR_GPIO 288 30#define NOMADIK_NR_GPIO 288
32#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + DBX500_NR_INTERNAL_IRQS) 31#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + DBX500_NR_INTERNAL_IRQS)
33#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - DBX500_NR_INTERNAL_IRQS) 32#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - DBX500_NR_INTERNAL_IRQS)
34#define IRQ_BOARD_START NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) 33#define IRQ_GPIO_END NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
34
35#define IRQ_SOC_START IRQ_GPIO_END
36/* This will be overridden by SoC-specific irq headers */
37#define IRQ_SOC_END IRQ_SOC_START
35 38
39#include <mach/irqs-db5500.h>
40#include <mach/irqs-db8500.h>
41
42#define IRQ_BOARD_START IRQ_SOC_END
36/* This will be overridden by board-specific irq headers */ 43/* This will be overridden by board-specific irq headers */
37#define IRQ_BOARD_END IRQ_BOARD_START 44#define IRQ_BOARD_END IRQ_BOARD_START
38 45
39#ifdef CONFIG_MACH_U8500 46#ifdef CONFIG_MACH_U8500
40#include <mach/irqs-board-mop500.h> 47#include <mach/irqs-board-mop500.h>
41#endif 48#endif
42 49
43/* 50#ifdef CONFIG_MACH_U5500
44 * After the board specific IRQ:s we reserve a range of IRQ:s in which virtual 51#include <mach/irqs-board-u5500.h>
45 * IRQ:s representing modem IRQ:s can be allocated 52#endif
46 */
47#define IRQ_MODEM_EVENTS_BASE (IRQ_BOARD_END + 1)
48#define IRQ_MODEM_EVENTS_NBR 72
49#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
50
51/* List of virtual IRQ:s that are allocated from the range above */
52#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43)
53#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45)
54#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41)
55 53
56#define NR_IRQS IRQ_MODEM_EVENTS_END 54#define NR_IRQS IRQ_BOARD_END
57 55
58#endif /* ASM_ARCH_IRQS_H */ 56#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-defs.h b/arch/arm/mach-ux500/include/mach/prcmu-defs.h
deleted file mode 100644
index 848ba64b561f..000000000000
--- a/arch/arm/mach-ux500/include/mach/prcmu-defs.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
6 * Author: Martin Persson <martin.persson@stericsson.com>
7 *
8 * License Terms: GNU General Public License v2
9 *
10 * PRCM Unit definitions
11 */
12
13#ifndef __MACH_PRCMU_DEFS_H
14#define __MACH_PRCMU_DEFS_H
15
16enum prcmu_cpu_opp {
17 CPU_OPP_INIT = 0x00,
18 CPU_OPP_NO_CHANGE = 0x01,
19 CPU_OPP_100 = 0x02,
20 CPU_OPP_50 = 0x03,
21 CPU_OPP_MAX = 0x04,
22 CPU_OPP_EXT_CLK = 0x07
23};
24enum prcmu_ape_opp {
25 APE_OPP_NO_CHANGE = 0x00,
26 APE_OPP_100 = 0x02,
27 APE_OPP_50 = 0x03,
28};
29
30#endif /* __MACH_PRCMU_DEFS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
deleted file mode 100644
index 455467e88791..000000000000
--- a/arch/arm/mach-ux500/include/mach/prcmu-regs.h
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
6 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
7 *
8 * License Terms: GNU General Public License v2
9 *
10 * PRCM Unit registers
11 */
12
13#ifndef __MACH_PRCMU_REGS_H
14#define __MACH_PRCMU_REGS_H
15
16#include <mach/hardware.h>
17
18#define _PRCMU_BASE IO_ADDRESS(U8500_PRCMU_BASE)
19
20#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118)
21#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114)
22#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98)
23#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0)
24#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4)
25#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0)
26#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c)
27#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308)
28
29/* ARM WFI Standby signal register */
30#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130)
31#define PRCMU_IOCR (_PRCMU_BASE + 0x310)
32
33/* CPU mailbox registers */
34#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc)
35#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100)
36#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104)
37
38/* Dual A9 core interrupt management unit registers */
39#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328)
40#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c)
41#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c)
42#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120)
43#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124)
44#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128)
45#define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C)
46#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260)
47#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264)
48#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268)
49#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C)
50
51#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334)
52#define ARM_WAKEUP_MODEM 0x1
53
54#define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C)
55#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494)
56#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174)
57
58#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148)
59#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150)
60#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158)
61#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160)
62#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168)
63#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484)
64#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488)
65#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018)
66
67/* System reset register */
68#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228)
69
70/* Level shifter and clamp control registers */
71#define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420)
72#define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424)
73
74/* PRCMU clock/PLL/reset registers */
75#define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500)
76#define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504)
77#define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044)
78#define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064)
79#define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058)
80#define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07c)
81#define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530)
82#define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C)
83#define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4)
84#define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8)
85
86/* ePOD and memory power signal control registers */
87#define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410)
88#define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304)
89
90/* Debug power control unit registers */
91#define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254)
92
93/* Miscellaneous unit registers */
94#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324)
95
96#endif /* __MACH_PRCMU_REGS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h
deleted file mode 100644
index c49e456162ef..000000000000
--- a/arch/arm/mach-ux500/include/mach/prcmu.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
6 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
7 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
8 *
9 * License Terms: GNU General Public License v2
10 *
11 * PRCM Unit f/w API
12 */
13#ifndef __MACH_PRCMU_H
14#define __MACH_PRCMU_H
15#include <mach/prcmu-defs.h>
16
17void __init prcmu_early_init(void);
18int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
19int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
20int prcmu_set_ape_opp(enum prcmu_ape_opp opp);
21int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp);
22int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp,
23 enum prcmu_cpu_opp cpu_opp);
24int prcmu_get_ape_opp(void);
25int prcmu_get_cpu_opp(void);
26bool prcmu_has_arm_maxopp(void);
27
28#endif /* __MACH_PRCMU_H */
diff --git a/arch/arm/mach-ux500/prcmu.c b/arch/arm/mach-ux500/prcmu.c
deleted file mode 100644
index c522d26ef348..000000000000
--- a/arch/arm/mach-ux500/prcmu.c
+++ /dev/null
@@ -1,394 +0,0 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * License Terms: GNU General Public License v2
6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
8 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
9 *
10 * U8500 PRCM Unit interface driver
11 *
12 */
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/errno.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/mutex.h>
19#include <linux/completion.h>
20#include <linux/jiffies.h>
21#include <linux/bitops.h>
22#include <linux/interrupt.h>
23
24#include <mach/hardware.h>
25#include <mach/prcmu-regs.h>
26#include <mach/prcmu-defs.h>
27
28/* Global var to runtime determine TCDM base for v2 or v1 */
29static __iomem void *tcdm_base;
30
31#define _MBOX_HEADER (tcdm_base + 0xFE8)
32#define MBOX_HEADER_REQ_MB0 (_MBOX_HEADER + 0x0)
33
34#define REQ_MB1 (tcdm_base + 0xFD0)
35#define REQ_MB5 (tcdm_base + 0xE44)
36
37#define REQ_MB1_ARMOPP (REQ_MB1 + 0x0)
38#define REQ_MB1_APEOPP (REQ_MB1 + 0x1)
39#define REQ_MB1_BOOSTOPP (REQ_MB1 + 0x2)
40
41#define ACK_MB1 (tcdm_base + 0xE04)
42#define ACK_MB5 (tcdm_base + 0xDF4)
43
44#define ACK_MB1_CURR_ARMOPP (ACK_MB1 + 0x0)
45#define ACK_MB1_CURR_APEOPP (ACK_MB1 + 0x1)
46
47#define REQ_MB5_I2C_SLAVE_OP (REQ_MB5)
48#define REQ_MB5_I2C_HW_BITS (REQ_MB5 + 1)
49#define REQ_MB5_I2C_REG (REQ_MB5 + 2)
50#define REQ_MB5_I2C_VAL (REQ_MB5 + 3)
51
52#define ACK_MB5_I2C_STATUS (ACK_MB5 + 1)
53#define ACK_MB5_I2C_VAL (ACK_MB5 + 3)
54
55#define PRCM_AVS_VARM_MAX_OPP (tcdm_base + 0x2E4)
56#define PRCM_AVS_ISMODEENABLE 7
57#define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
58
59#define I2C_WRITE(slave) \
60 (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
61#define I2C_READ(slave) \
62 (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0) | BIT(0))
63#define I2C_STOP_EN BIT(3)
64
65enum mb1_h {
66 MB1H_ARM_OPP = 1,
67 MB1H_APE_OPP,
68 MB1H_ARM_APE_OPP,
69};
70
71static struct {
72 struct mutex lock;
73 struct completion work;
74 struct {
75 u8 arm_opp;
76 u8 ape_opp;
77 u8 arm_status;
78 u8 ape_status;
79 } ack;
80} mb1_transfer;
81
82enum ack_mb5_status {
83 I2C_WR_OK = 0x01,
84 I2C_RD_OK = 0x02,
85};
86
87#define MBOX_BIT BIT
88#define NUM_MBOX 8
89
90static struct {
91 struct mutex lock;
92 struct completion work;
93 bool failed;
94 struct {
95 u8 status;
96 u8 value;
97 } ack;
98} mb5_transfer;
99
100/**
101 * prcmu_abb_read() - Read register value(s) from the ABB.
102 * @slave: The I2C slave address.
103 * @reg: The (start) register address.
104 * @value: The read out value(s).
105 * @size: The number of registers to read.
106 *
107 * Reads register value(s) from the ABB.
108 * @size has to be 1 for the current firmware version.
109 */
110int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
111{
112 int r;
113
114 if (size != 1)
115 return -EINVAL;
116
117 r = mutex_lock_interruptible(&mb5_transfer.lock);
118 if (r)
119 return r;
120
121 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
122 cpu_relax();
123
124 writeb(I2C_READ(slave), REQ_MB5_I2C_SLAVE_OP);
125 writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
126 writeb(reg, REQ_MB5_I2C_REG);
127
128 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
129 if (!wait_for_completion_timeout(&mb5_transfer.work,
130 msecs_to_jiffies(500))) {
131 pr_err("prcmu: prcmu_abb_read timed out.\n");
132 r = -EIO;
133 goto unlock_and_return;
134 }
135 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
136 if (!r)
137 *value = mb5_transfer.ack.value;
138
139unlock_and_return:
140 mutex_unlock(&mb5_transfer.lock);
141 return r;
142}
143EXPORT_SYMBOL(prcmu_abb_read);
144
145/**
146 * prcmu_abb_write() - Write register value(s) to the ABB.
147 * @slave: The I2C slave address.
148 * @reg: The (start) register address.
149 * @value: The value(s) to write.
150 * @size: The number of registers to write.
151 *
152 * Reads register value(s) from the ABB.
153 * @size has to be 1 for the current firmware version.
154 */
155int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
156{
157 int r;
158
159 if (size != 1)
160 return -EINVAL;
161
162 r = mutex_lock_interruptible(&mb5_transfer.lock);
163 if (r)
164 return r;
165
166
167 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
168 cpu_relax();
169
170 writeb(I2C_WRITE(slave), REQ_MB5_I2C_SLAVE_OP);
171 writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
172 writeb(reg, REQ_MB5_I2C_REG);
173 writeb(*value, REQ_MB5_I2C_VAL);
174
175 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
176 if (!wait_for_completion_timeout(&mb5_transfer.work,
177 msecs_to_jiffies(500))) {
178 pr_err("prcmu: prcmu_abb_write timed out.\n");
179 r = -EIO;
180 goto unlock_and_return;
181 }
182 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
183
184unlock_and_return:
185 mutex_unlock(&mb5_transfer.lock);
186 return r;
187}
188EXPORT_SYMBOL(prcmu_abb_write);
189
190static int set_ape_cpu_opps(u8 header, enum prcmu_ape_opp ape_opp,
191 enum prcmu_cpu_opp cpu_opp)
192{
193 bool do_ape;
194 bool do_arm;
195 int err = 0;
196
197 do_ape = ((header == MB1H_APE_OPP) || (header == MB1H_ARM_APE_OPP));
198 do_arm = ((header == MB1H_ARM_OPP) || (header == MB1H_ARM_APE_OPP));
199
200 mutex_lock(&mb1_transfer.lock);
201
202 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
203 cpu_relax();
204
205 writeb(0, MBOX_HEADER_REQ_MB0);
206 writeb(cpu_opp, REQ_MB1_ARMOPP);
207 writeb(ape_opp, REQ_MB1_APEOPP);
208 writeb(0, REQ_MB1_BOOSTOPP);
209 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
210 wait_for_completion(&mb1_transfer.work);
211 if ((do_ape) && (mb1_transfer.ack.ape_status != 0))
212 err = -EIO;
213 if ((do_arm) && (mb1_transfer.ack.arm_status != 0))
214 err = -EIO;
215
216 mutex_unlock(&mb1_transfer.lock);
217
218 return err;
219}
220
221/**
222 * prcmu_set_ape_opp() - Set the OPP of the APE.
223 * @opp: The OPP to set.
224 *
225 * This function sets the OPP of the APE.
226 */
227int prcmu_set_ape_opp(enum prcmu_ape_opp opp)
228{
229 return set_ape_cpu_opps(MB1H_APE_OPP, opp, APE_OPP_NO_CHANGE);
230}
231EXPORT_SYMBOL(prcmu_set_ape_opp);
232
233/**
234 * prcmu_set_cpu_opp() - Set the OPP of the CPU.
235 * @opp: The OPP to set.
236 *
237 * This function sets the OPP of the CPU.
238 */
239int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp)
240{
241 return set_ape_cpu_opps(MB1H_ARM_OPP, CPU_OPP_NO_CHANGE, opp);
242}
243EXPORT_SYMBOL(prcmu_set_cpu_opp);
244
245/**
246 * prcmu_set_ape_cpu_opps() - Set the OPPs of the APE and the CPU.
247 * @ape_opp: The APE OPP to set.
248 * @cpu_opp: The CPU OPP to set.
249 *
250 * This function sets the OPPs of the APE and the CPU.
251 */
252int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp,
253 enum prcmu_cpu_opp cpu_opp)
254{
255 return set_ape_cpu_opps(MB1H_ARM_APE_OPP, ape_opp, cpu_opp);
256}
257EXPORT_SYMBOL(prcmu_set_ape_cpu_opps);
258
259/**
260 * prcmu_get_ape_opp() - Get the OPP of the APE.
261 *
262 * This function gets the OPP of the APE.
263 */
264enum prcmu_ape_opp prcmu_get_ape_opp(void)
265{
266 return readb(ACK_MB1_CURR_APEOPP);
267}
268EXPORT_SYMBOL(prcmu_get_ape_opp);
269
270/**
271 * prcmu_get_cpu_opp() - Get the OPP of the CPU.
272 *
273 * This function gets the OPP of the CPU. The OPP is specified in %%.
274 * PRCMU_OPP_EXT is a special OPP value, not specified in %%.
275 */
276int prcmu_get_cpu_opp(void)
277{
278 return readb(ACK_MB1_CURR_ARMOPP);
279}
280EXPORT_SYMBOL(prcmu_get_cpu_opp);
281
282bool prcmu_has_arm_maxopp(void)
283{
284 return (readb(PRCM_AVS_VARM_MAX_OPP) & PRCM_AVS_ISMODEENABLE_MASK)
285 == PRCM_AVS_ISMODEENABLE_MASK;
286}
287
288static void read_mailbox_0(void)
289{
290 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);
291}
292
293static void read_mailbox_1(void)
294{
295 mb1_transfer.ack.arm_opp = readb(ACK_MB1_CURR_ARMOPP);
296 mb1_transfer.ack.ape_opp = readb(ACK_MB1_CURR_APEOPP);
297 complete(&mb1_transfer.work);
298 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);
299}
300
301static void read_mailbox_2(void)
302{
303 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR);
304}
305
306static void read_mailbox_3(void)
307{
308 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR);
309}
310
311static void read_mailbox_4(void)
312{
313 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR);
314}
315
316static void read_mailbox_5(void)
317{
318 mb5_transfer.ack.status = readb(ACK_MB5_I2C_STATUS);
319 mb5_transfer.ack.value = readb(ACK_MB5_I2C_VAL);
320 complete(&mb5_transfer.work);
321 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR);
322}
323
324static void read_mailbox_6(void)
325{
326 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR);
327}
328
329static void read_mailbox_7(void)
330{
331 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR);
332}
333
334static void (* const read_mailbox[NUM_MBOX])(void) = {
335 read_mailbox_0,
336 read_mailbox_1,
337 read_mailbox_2,
338 read_mailbox_3,
339 read_mailbox_4,
340 read_mailbox_5,
341 read_mailbox_6,
342 read_mailbox_7
343};
344
345static irqreturn_t prcmu_irq_handler(int irq, void *data)
346{
347 u32 bits;
348 u8 n;
349
350 bits = (readl(PRCM_ARM_IT1_VAL) & (MBOX_BIT(NUM_MBOX) - 1));
351 if (unlikely(!bits))
352 return IRQ_NONE;
353
354 for (n = 0; bits; n++) {
355 if (bits & MBOX_BIT(n)) {
356 bits -= MBOX_BIT(n);
357 read_mailbox[n]();
358 }
359 }
360 return IRQ_HANDLED;
361}
362
363void __init prcmu_early_init(void)
364{
365 if (cpu_is_u8500v11() || cpu_is_u8500ed()) {
366 tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE_V1);
367 } else if (cpu_is_u8500v2()) {
368 tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
369 } else {
370 pr_err("prcmu: Unsupported chip version\n");
371 BUG();
372 }
373}
374
375static int __init prcmu_init(void)
376{
377 if (cpu_is_u8500ed()) {
378 pr_err("prcmu: Unsupported chip version\n");
379 return 0;
380 }
381
382 mutex_init(&mb1_transfer.lock);
383 init_completion(&mb1_transfer.work);
384 mutex_init(&mb5_transfer.lock);
385 init_completion(&mb5_transfer.work);
386
387 /* Clean up the mailbox interrupts after pre-kernel code. */
388 writel((MBOX_BIT(NUM_MBOX) - 1), PRCM_ARM_IT1_CLEAR);
389
390 return request_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler, 0,
391 "prcmu", NULL);
392}
393
394arch_initcall(prcmu_init);
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index c96fa1b3f49f..73b4a8b66a57 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -176,6 +176,7 @@ ENDPROC(v6_coherent_kern_range)
176 */ 176 */
177ENTRY(v6_flush_kern_dcache_area) 177ENTRY(v6_flush_kern_dcache_area)
178 add r1, r0, r1 178 add r1, r0, r1
179 bic r0, r0, #D_CACHE_LINE_SIZE - 1
1791: 1801:
180#ifdef HARVARD_CACHE 181#ifdef HARVARD_CACHE
181 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 182 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index dc18d81ef8ce..d32f02b61866 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -221,6 +221,8 @@ ENDPROC(v7_coherent_user_range)
221ENTRY(v7_flush_kern_dcache_area) 221ENTRY(v7_flush_kern_dcache_area)
222 dcache_line_size r2, r3 222 dcache_line_size r2, r3
223 add r1, r0, r1 223 add r1, r0, r1
224 sub r3, r2, #1
225 bic r0, r0, r3
2241: 2261:
225 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 227 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
226 add r0, r0, r2 228 add r0, r0, r2
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index b0ee9ba3cfab..8bfae964b133 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -24,9 +24,7 @@ DEFINE_PER_CPU(struct mm_struct *, current_mm);
24 24
25/* 25/*
26 * We fork()ed a process, and we need a new context for the child 26 * We fork()ed a process, and we need a new context for the child
27 * to run in. We reserve version 0 for initial tasks so we will 27 * to run in.
28 * always allocate an ASID. The ASID 0 is reserved for the TTBR
29 * register changing sequence.
30 */ 28 */
31void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) 29void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
32{ 30{
@@ -36,8 +34,11 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
36 34
37static void flush_context(void) 35static void flush_context(void)
38{ 36{
39 /* set the reserved ASID before flushing the TLB */ 37 u32 ttb;
40 asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (0)); 38 /* Copy TTBR1 into TTBR0 */
39 asm volatile("mrc p15, 0, %0, c2, c0, 1\n"
40 "mcr p15, 0, %0, c2, c0, 0"
41 : "=r" (ttb));
41 isb(); 42 isb();
42 local_flush_tlb_all(); 43 local_flush_tlb_all();
43 if (icache_is_vivt_asid_tagged()) { 44 if (icache_is_vivt_asid_tagged()) {
@@ -93,7 +94,7 @@ static void reset_context(void *info)
93 return; 94 return;
94 95
95 smp_rmb(); 96 smp_rmb();
96 asid = cpu_last_asid + cpu + 1; 97 asid = cpu_last_asid + cpu;
97 98
98 flush_context(); 99 flush_context();
99 set_mm_context(mm, asid); 100 set_mm_context(mm, asid);
@@ -143,13 +144,13 @@ void __new_context(struct mm_struct *mm)
143 * to start a new version and flush the TLB. 144 * to start a new version and flush the TLB.
144 */ 145 */
145 if (unlikely((asid & ~ASID_MASK) == 0)) { 146 if (unlikely((asid & ~ASID_MASK) == 0)) {
146 asid = cpu_last_asid + smp_processor_id() + 1; 147 asid = cpu_last_asid + smp_processor_id();
147 flush_context(); 148 flush_context();
148#ifdef CONFIG_SMP 149#ifdef CONFIG_SMP
149 smp_wmb(); 150 smp_wmb();
150 smp_call_function(reset_context, NULL, 1); 151 smp_call_function(reset_context, NULL, 1);
151#endif 152#endif
152 cpu_last_asid += NR_CPUS; 153 cpu_last_asid += NR_CPUS - 1;
153 } 154 }
154 155
155 set_mm_context(mm, asid); 156 set_mm_context(mm, asid);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 751767279b3e..2c2cce9cd8c8 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -95,7 +95,7 @@ void show_mem(unsigned int filter)
95 struct meminfo * mi = &meminfo; 95 struct meminfo * mi = &meminfo;
96 96
97 printk("Mem-info:\n"); 97 printk("Mem-info:\n");
98 show_free_areas(); 98 show_free_areas(filter);
99 99
100 for_each_bank (i, mi) { 100 for_each_bank (i, mi) {
101 struct membank *bank = &mi->bank[i]; 101 struct membank *bank = &mi->bank[i];
@@ -283,13 +283,15 @@ static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
283 free_area_init_node(0, zone_size, min, zhole_size); 283 free_area_init_node(0, zone_size, min, zhole_size);
284} 284}
285 285
286#ifndef CONFIG_SPARSEMEM 286#ifdef CONFIG_HAVE_ARCH_PFN_VALID
287int pfn_valid(unsigned long pfn) 287int pfn_valid(unsigned long pfn)
288{ 288{
289 return memblock_is_memory(pfn << PAGE_SHIFT); 289 return memblock_is_memory(pfn << PAGE_SHIFT);
290} 290}
291EXPORT_SYMBOL(pfn_valid); 291EXPORT_SYMBOL(pfn_valid);
292#endif
292 293
294#ifndef CONFIG_SPARSEMEM
293static void arm_memory_present(void) 295static void arm_memory_present(void)
294{ 296{
295} 297}
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index d2384106af9c..5b3d7d543659 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -5,14 +5,9 @@ extern pmd_t *top_pmd;
5 5
6#define TOP_PTE(x) pte_offset_kernel(top_pmd, x) 6#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)
7 7
8static inline pmd_t *pmd_off(pgd_t *pgd, unsigned long virt)
9{
10 return pmd_offset(pud_offset(pgd, virt), virt);
11}
12
13static inline pmd_t *pmd_off_k(unsigned long virt) 8static inline pmd_t *pmd_off_k(unsigned long virt)
14{ 9{
15 return pmd_off(pgd_offset_k(virt), virt); 10 return pmd_offset(pud_offset(pgd_offset_k(virt), virt), virt);
16} 11}
17 12
18struct mem_type { 13struct mem_type {
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6cf76b3b68d1..9d9e736c2b4f 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -31,8 +31,6 @@
31 31
32#include "mm.h" 32#include "mm.h"
33 33
34DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
35
36/* 34/*
37 * empty_zero_page is a special page that is used for 35 * empty_zero_page is a special page that is used for
38 * zero-initialized data and COW. 36 * zero-initialized data and COW.
@@ -765,15 +763,12 @@ static void __init sanity_check_meminfo(void)
765{ 763{
766 int i, j, highmem = 0; 764 int i, j, highmem = 0;
767 765
768 lowmem_limit = __pa(vmalloc_min - 1) + 1;
769 memblock_set_current_limit(lowmem_limit);
770
771 for (i = 0, j = 0; i < meminfo.nr_banks; i++) { 766 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
772 struct membank *bank = &meminfo.bank[j]; 767 struct membank *bank = &meminfo.bank[j];
773 *bank = meminfo.bank[i]; 768 *bank = meminfo.bank[i];
774 769
775#ifdef CONFIG_HIGHMEM 770#ifdef CONFIG_HIGHMEM
776 if (__va(bank->start) > vmalloc_min || 771 if (__va(bank->start) >= vmalloc_min ||
777 __va(bank->start) < (void *)PAGE_OFFSET) 772 __va(bank->start) < (void *)PAGE_OFFSET)
778 highmem = 1; 773 highmem = 1;
779 774
@@ -831,6 +826,9 @@ static void __init sanity_check_meminfo(void)
831 bank->size = newsize; 826 bank->size = newsize;
832 } 827 }
833#endif 828#endif
829 if (!bank->highmem && bank->start + bank->size > lowmem_limit)
830 lowmem_limit = bank->start + bank->size;
831
834 j++; 832 j++;
835 } 833 }
836#ifdef CONFIG_HIGHMEM 834#ifdef CONFIG_HIGHMEM
@@ -854,6 +852,7 @@ static void __init sanity_check_meminfo(void)
854 } 852 }
855#endif 853#endif
856 meminfo.nr_banks = j; 854 meminfo.nr_banks = j;
855 memblock_set_current_limit(lowmem_limit);
857} 856}
858 857
859static inline void prepare_page_table(void) 858static inline void prepare_page_table(void)
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index ab17cc0d3fa7..1d2b8451bf25 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -213,7 +213,9 @@ __v6_setup:
213 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 213 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
214 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 214 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
215 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 215 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
216 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 216 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
217 ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
218 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
217#endif /* CONFIG_MMU */ 219#endif /* CONFIG_MMU */
218 adr r5, v6_crval 220 adr r5, v6_crval
219 ldmia r5, {r5, r6} 221 ldmia r5, {r5, r6}
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index babfba09c89f..b3b566ec83d3 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -108,18 +108,16 @@ ENTRY(cpu_v7_switch_mm)
108#ifdef CONFIG_ARM_ERRATA_430973 108#ifdef CONFIG_ARM_ERRATA_430973
109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
110#endif 110#endif
111#ifdef CONFIG_ARM_ERRATA_754322 111 mrc p15, 0, r2, c2, c0, 1 @ load TTB 1
112 dsb 112 mcr p15, 0, r2, c2, c0, 0 @ into TTB 0
113#endif
114 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
115 isb
1161: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
117 isb 113 isb
118#ifdef CONFIG_ARM_ERRATA_754322 114#ifdef CONFIG_ARM_ERRATA_754322
119 dsb 115 dsb
120#endif 116#endif
121 mcr p15, 0, r1, c13, c0, 1 @ set context ID 117 mcr p15, 0, r1, c13, c0, 1 @ set context ID
122 isb 118 isb
119 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
120 isb
123#endif 121#endif
124 mov pc, lr 122 mov pc, lr
125ENDPROC(cpu_v7_switch_mm) 123ENDPROC(cpu_v7_switch_mm)
@@ -368,7 +366,9 @@ __v7_setup:
368 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 366 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
369 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 367 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
370 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 368 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
371 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 369 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
370 ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
371 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
372 ldr r5, =PRRR @ PRRR 372 ldr r5, =PRRR @ PRRR
373 ldr r6, =NMRR @ NMRR 373 ldr r6, =NMRR @ NMRR
374 mcr p15, 0, r5, c10, c2, 0 @ write PRRR 374 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
deleted file mode 100644
index 5e04ddc18fa8..000000000000
--- a/arch/arm/plat-omap/include/plat/display.h
+++ /dev/null
@@ -1,591 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/display.h
3 *
4 * Copyright (C) 2008 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef __ASM_ARCH_OMAP_DISPLAY_H
21#define __ASM_ARCH_OMAP_DISPLAY_H
22
23#include <linux/list.h>
24#include <linux/kobject.h>
25#include <linux/device.h>
26#include <linux/platform_device.h>
27#include <asm/atomic.h>
28
29#define DISPC_IRQ_FRAMEDONE (1 << 0)
30#define DISPC_IRQ_VSYNC (1 << 1)
31#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
32#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
33#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
34#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
35#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
36#define DISPC_IRQ_GFX_END_WIN (1 << 7)
37#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
38#define DISPC_IRQ_OCP_ERR (1 << 9)
39#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
40#define DISPC_IRQ_VID1_END_WIN (1 << 11)
41#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
42#define DISPC_IRQ_VID2_END_WIN (1 << 13)
43#define DISPC_IRQ_SYNC_LOST (1 << 14)
44#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
45#define DISPC_IRQ_WAKEUP (1 << 16)
46#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
47#define DISPC_IRQ_VSYNC2 (1 << 18)
48#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
49#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
50
51struct omap_dss_device;
52struct omap_overlay_manager;
53
54enum omap_display_type {
55 OMAP_DISPLAY_TYPE_NONE = 0,
56 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
57 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
58 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
59 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
60 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
61 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
62};
63
64enum omap_plane {
65 OMAP_DSS_GFX = 0,
66 OMAP_DSS_VIDEO1 = 1,
67 OMAP_DSS_VIDEO2 = 2
68};
69
70enum omap_channel {
71 OMAP_DSS_CHANNEL_LCD = 0,
72 OMAP_DSS_CHANNEL_DIGIT = 1,
73 OMAP_DSS_CHANNEL_LCD2 = 2,
74};
75
76enum omap_color_mode {
77 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
78 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
79 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
80 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
81 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
82 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
83 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
84 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
85 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
86 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
87 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
88 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
89 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
90 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
91};
92
93enum omap_lcd_display_type {
94 OMAP_DSS_LCD_DISPLAY_STN,
95 OMAP_DSS_LCD_DISPLAY_TFT,
96};
97
98enum omap_dss_load_mode {
99 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
100 OMAP_DSS_LOAD_CLUT_ONLY = 1,
101 OMAP_DSS_LOAD_FRAME_ONLY = 2,
102 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
103};
104
105enum omap_dss_trans_key_type {
106 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
107 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
108};
109
110enum omap_rfbi_te_mode {
111 OMAP_DSS_RFBI_TE_MODE_1 = 1,
112 OMAP_DSS_RFBI_TE_MODE_2 = 2,
113};
114
115enum omap_panel_config {
116 OMAP_DSS_LCD_IVS = 1<<0,
117 OMAP_DSS_LCD_IHS = 1<<1,
118 OMAP_DSS_LCD_IPC = 1<<2,
119 OMAP_DSS_LCD_IEO = 1<<3,
120 OMAP_DSS_LCD_RF = 1<<4,
121 OMAP_DSS_LCD_ONOFF = 1<<5,
122
123 OMAP_DSS_LCD_TFT = 1<<20,
124};
125
126enum omap_dss_venc_type {
127 OMAP_DSS_VENC_TYPE_COMPOSITE,
128 OMAP_DSS_VENC_TYPE_SVIDEO,
129};
130
131enum omap_display_caps {
132 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
133 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
134};
135
136enum omap_dss_update_mode {
137 OMAP_DSS_UPDATE_DISABLED = 0,
138 OMAP_DSS_UPDATE_AUTO,
139 OMAP_DSS_UPDATE_MANUAL,
140};
141
142enum omap_dss_display_state {
143 OMAP_DSS_DISPLAY_DISABLED = 0,
144 OMAP_DSS_DISPLAY_ACTIVE,
145 OMAP_DSS_DISPLAY_SUSPENDED,
146};
147
148/* XXX perhaps this should be removed */
149enum omap_dss_overlay_managers {
150 OMAP_DSS_OVL_MGR_LCD,
151 OMAP_DSS_OVL_MGR_TV,
152 OMAP_DSS_OVL_MGR_LCD2,
153};
154
155enum omap_dss_rotation_type {
156 OMAP_DSS_ROT_DMA = 0,
157 OMAP_DSS_ROT_VRFB = 1,
158};
159
160/* clockwise rotation angle */
161enum omap_dss_rotation_angle {
162 OMAP_DSS_ROT_0 = 0,
163 OMAP_DSS_ROT_90 = 1,
164 OMAP_DSS_ROT_180 = 2,
165 OMAP_DSS_ROT_270 = 3,
166};
167
168enum omap_overlay_caps {
169 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
170 OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
171};
172
173enum omap_overlay_manager_caps {
174 OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
175};
176
177/* RFBI */
178
179struct rfbi_timings {
180 int cs_on_time;
181 int cs_off_time;
182 int we_on_time;
183 int we_off_time;
184 int re_on_time;
185 int re_off_time;
186 int we_cycle_time;
187 int re_cycle_time;
188 int cs_pulse_width;
189 int access_time;
190
191 int clk_div;
192
193 u32 tim[5]; /* set by rfbi_convert_timings() */
194
195 int converted;
196};
197
198void omap_rfbi_write_command(const void *buf, u32 len);
199void omap_rfbi_read_data(void *buf, u32 len);
200void omap_rfbi_write_data(const void *buf, u32 len);
201void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
202 u16 x, u16 y,
203 u16 w, u16 h);
204int omap_rfbi_enable_te(bool enable, unsigned line);
205int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
206 unsigned hs_pulse_time, unsigned vs_pulse_time,
207 int hs_pol_inv, int vs_pol_inv, int extif_div);
208
209/* DSI */
210void dsi_bus_lock(void);
211void dsi_bus_unlock(void);
212int dsi_vc_dcs_write(int channel, u8 *data, int len);
213int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd);
214int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param);
215int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
216int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
217int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data);
218int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2);
219int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
220int dsi_vc_send_null(int channel);
221int dsi_vc_send_bta_sync(int channel);
222
223/* Board specific data */
224struct omap_dss_board_info {
225 int (*get_last_off_on_transaction_id)(struct device *dev);
226 int num_devices;
227 struct omap_dss_device **devices;
228 struct omap_dss_device *default_device;
229};
230
231#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
232/* Init with the board info */
233extern int omap_display_init(struct omap_dss_board_info *board_data);
234#else
235static inline int omap_display_init(struct omap_dss_board_info *board_data)
236{
237 return 0;
238}
239#endif
240
241struct omap_display_platform_data {
242 struct omap_dss_board_info *board_data;
243 /* TODO: Additional members to be added when PM is considered */
244
245 bool (*opt_clock_available)(const char *clk_role);
246};
247
248struct omap_video_timings {
249 /* Unit: pixels */
250 u16 x_res;
251 /* Unit: pixels */
252 u16 y_res;
253 /* Unit: KHz */
254 u32 pixel_clock;
255 /* Unit: pixel clocks */
256 u16 hsw; /* Horizontal synchronization pulse width */
257 /* Unit: pixel clocks */
258 u16 hfp; /* Horizontal front porch */
259 /* Unit: pixel clocks */
260 u16 hbp; /* Horizontal back porch */
261 /* Unit: line clocks */
262 u16 vsw; /* Vertical synchronization pulse width */
263 /* Unit: line clocks */
264 u16 vfp; /* Vertical front porch */
265 /* Unit: line clocks */
266 u16 vbp; /* Vertical back porch */
267};
268
269#ifdef CONFIG_OMAP2_DSS_VENC
270/* Hardcoded timings for tv modes. Venc only uses these to
271 * identify the mode, and does not actually use the configs
272 * itself. However, the configs should be something that
273 * a normal monitor can also show */
274extern const struct omap_video_timings omap_dss_pal_timings;
275extern const struct omap_video_timings omap_dss_ntsc_timings;
276#endif
277
278struct omap_overlay_info {
279 bool enabled;
280
281 u32 paddr;
282 void __iomem *vaddr;
283 u16 screen_width;
284 u16 width;
285 u16 height;
286 enum omap_color_mode color_mode;
287 u8 rotation;
288 enum omap_dss_rotation_type rotation_type;
289 bool mirror;
290
291 u16 pos_x;
292 u16 pos_y;
293 u16 out_width; /* if 0, out_width == width */
294 u16 out_height; /* if 0, out_height == height */
295 u8 global_alpha;
296 u8 pre_mult_alpha;
297};
298
299struct omap_overlay {
300 struct kobject kobj;
301 struct list_head list;
302
303 /* static fields */
304 const char *name;
305 int id;
306 enum omap_color_mode supported_modes;
307 enum omap_overlay_caps caps;
308
309 /* dynamic fields */
310 struct omap_overlay_manager *manager;
311 struct omap_overlay_info info;
312
313 /* if true, info has been changed, but not applied() yet */
314 bool info_dirty;
315
316 int (*set_manager)(struct omap_overlay *ovl,
317 struct omap_overlay_manager *mgr);
318 int (*unset_manager)(struct omap_overlay *ovl);
319
320 int (*set_overlay_info)(struct omap_overlay *ovl,
321 struct omap_overlay_info *info);
322 void (*get_overlay_info)(struct omap_overlay *ovl,
323 struct omap_overlay_info *info);
324
325 int (*wait_for_go)(struct omap_overlay *ovl);
326};
327
328struct omap_overlay_manager_info {
329 u32 default_color;
330
331 enum omap_dss_trans_key_type trans_key_type;
332 u32 trans_key;
333 bool trans_enabled;
334
335 bool alpha_enabled;
336};
337
338struct omap_overlay_manager {
339 struct kobject kobj;
340 struct list_head list;
341
342 /* static fields */
343 const char *name;
344 int id;
345 enum omap_overlay_manager_caps caps;
346 int num_overlays;
347 struct omap_overlay **overlays;
348 enum omap_display_type supported_displays;
349
350 /* dynamic fields */
351 struct omap_dss_device *device;
352 struct omap_overlay_manager_info info;
353
354 bool device_changed;
355 /* if true, info has been changed but not applied() yet */
356 bool info_dirty;
357
358 int (*set_device)(struct omap_overlay_manager *mgr,
359 struct omap_dss_device *dssdev);
360 int (*unset_device)(struct omap_overlay_manager *mgr);
361
362 int (*set_manager_info)(struct omap_overlay_manager *mgr,
363 struct omap_overlay_manager_info *info);
364 void (*get_manager_info)(struct omap_overlay_manager *mgr,
365 struct omap_overlay_manager_info *info);
366
367 int (*apply)(struct omap_overlay_manager *mgr);
368 int (*wait_for_go)(struct omap_overlay_manager *mgr);
369 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
370
371 int (*enable)(struct omap_overlay_manager *mgr);
372 int (*disable)(struct omap_overlay_manager *mgr);
373};
374
375struct omap_dss_device {
376 struct device dev;
377
378 enum omap_display_type type;
379
380 enum omap_channel channel;
381
382 union {
383 struct {
384 u8 data_lines;
385 } dpi;
386
387 struct {
388 u8 channel;
389 u8 data_lines;
390 } rfbi;
391
392 struct {
393 u8 datapairs;
394 } sdi;
395
396 struct {
397 u8 clk_lane;
398 u8 clk_pol;
399 u8 data1_lane;
400 u8 data1_pol;
401 u8 data2_lane;
402 u8 data2_pol;
403
404 struct {
405 u16 regn;
406 u16 regm;
407 u16 regm_dispc;
408 u16 regm_dsi;
409
410 u16 lp_clk_div;
411
412 u16 lck_div;
413 u16 pck_div;
414 } div;
415
416 bool ext_te;
417 u8 ext_te_gpio;
418 } dsi;
419
420 struct {
421 enum omap_dss_venc_type type;
422 bool invert_polarity;
423 } venc;
424 } phy;
425
426 struct {
427 struct omap_video_timings timings;
428
429 int acbi; /* ac-bias pin transitions per interrupt */
430 /* Unit: line clocks */
431 int acb; /* ac-bias pin frequency */
432
433 enum omap_panel_config config;
434 } panel;
435
436 struct {
437 u8 pixel_size;
438 struct rfbi_timings rfbi_timings;
439 } ctrl;
440
441 int reset_gpio;
442
443 int max_backlight_level;
444
445 const char *name;
446
447 /* used to match device to driver */
448 const char *driver_name;
449
450 void *data;
451
452 struct omap_dss_driver *driver;
453
454 /* helper variable for driver suspend/resume */
455 bool activate_after_resume;
456
457 enum omap_display_caps caps;
458
459 struct omap_overlay_manager *manager;
460
461 enum omap_dss_display_state state;
462
463 /* platform specific */
464 int (*platform_enable)(struct omap_dss_device *dssdev);
465 void (*platform_disable)(struct omap_dss_device *dssdev);
466 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
467 int (*get_backlight)(struct omap_dss_device *dssdev);
468};
469
470struct omap_dss_driver {
471 struct device_driver driver;
472
473 int (*probe)(struct omap_dss_device *);
474 void (*remove)(struct omap_dss_device *);
475
476 int (*enable)(struct omap_dss_device *display);
477 void (*disable)(struct omap_dss_device *display);
478 int (*suspend)(struct omap_dss_device *display);
479 int (*resume)(struct omap_dss_device *display);
480 int (*run_test)(struct omap_dss_device *display, int test);
481
482 int (*set_update_mode)(struct omap_dss_device *dssdev,
483 enum omap_dss_update_mode);
484 enum omap_dss_update_mode (*get_update_mode)(
485 struct omap_dss_device *dssdev);
486
487 int (*update)(struct omap_dss_device *dssdev,
488 u16 x, u16 y, u16 w, u16 h);
489 int (*sync)(struct omap_dss_device *dssdev);
490
491 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
492 int (*get_te)(struct omap_dss_device *dssdev);
493
494 u8 (*get_rotate)(struct omap_dss_device *dssdev);
495 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
496
497 bool (*get_mirror)(struct omap_dss_device *dssdev);
498 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
499
500 int (*memory_read)(struct omap_dss_device *dssdev,
501 void *buf, size_t size,
502 u16 x, u16 y, u16 w, u16 h);
503
504 void (*get_resolution)(struct omap_dss_device *dssdev,
505 u16 *xres, u16 *yres);
506 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
507
508 int (*check_timings)(struct omap_dss_device *dssdev,
509 struct omap_video_timings *timings);
510 void (*set_timings)(struct omap_dss_device *dssdev,
511 struct omap_video_timings *timings);
512 void (*get_timings)(struct omap_dss_device *dssdev,
513 struct omap_video_timings *timings);
514
515 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
516 u32 (*get_wss)(struct omap_dss_device *dssdev);
517};
518
519int omap_dss_register_driver(struct omap_dss_driver *);
520void omap_dss_unregister_driver(struct omap_dss_driver *);
521
522int omap_dss_register_device(struct omap_dss_device *);
523void omap_dss_unregister_device(struct omap_dss_device *);
524
525void omap_dss_get_device(struct omap_dss_device *dssdev);
526void omap_dss_put_device(struct omap_dss_device *dssdev);
527#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
528struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
529struct omap_dss_device *omap_dss_find_device(void *data,
530 int (*match)(struct omap_dss_device *dssdev, void *data));
531
532int omap_dss_start_device(struct omap_dss_device *dssdev);
533void omap_dss_stop_device(struct omap_dss_device *dssdev);
534
535int omap_dss_get_num_overlay_managers(void);
536struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
537
538int omap_dss_get_num_overlays(void);
539struct omap_overlay *omap_dss_get_overlay(int num);
540
541void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
542 u16 *xres, u16 *yres);
543int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
544
545typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
546int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
547int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
548
549int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
550int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
551 unsigned long timeout);
552
553#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
554#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
555
556void omapdss_dsi_vc_enable_hs(int channel, bool enable);
557int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
558
559int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
560 u16 *x, u16 *y, u16 *w, u16 *h,
561 bool enlarge_update_area);
562int omap_dsi_update(struct omap_dss_device *dssdev,
563 int channel,
564 u16 x, u16 y, u16 w, u16 h,
565 void (*callback)(int, void *), void *data);
566int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
567int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
568void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
569
570int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
571void omapdss_dsi_display_disable(struct omap_dss_device *dssdev);
572
573int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
574void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
575void dpi_set_timings(struct omap_dss_device *dssdev,
576 struct omap_video_timings *timings);
577int dpi_check_timings(struct omap_dss_device *dssdev,
578 struct omap_video_timings *timings);
579
580int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
581void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
582
583int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
584void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
585int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
586 u16 *x, u16 *y, u16 *w, u16 *h);
587int omap_rfbi_update(struct omap_dss_device *dssdev,
588 u16 x, u16 y, u16 w, u16 h,
589 void (*callback)(void *), void *data);
590
591#endif
diff --git a/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h b/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h
deleted file mode 100644
index 01ab6572ccbb..000000000000
--- a/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h
+++ /dev/null
@@ -1,31 +0,0 @@
1#ifndef __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H
2#define __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H
3
4#include "display.h"
5
6/**
7 * struct nokia_dsi_panel_data - Nokia DSI panel driver configuration
8 * @name: panel name
9 * @use_ext_te: use external TE
10 * @ext_te_gpio: external TE GPIO
11 * @use_esd_check: perform ESD checks
12 * @max_backlight_level: maximum backlight level
13 * @set_backlight: pointer to backlight set function
14 * @get_backlight: pointer to backlight get function
15 */
16struct nokia_dsi_panel_data {
17 const char *name;
18
19 int reset_gpio;
20
21 bool use_ext_te;
22 int ext_te_gpio;
23
24 bool use_esd_check;
25
26 int max_backlight_level;
27 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
28 int (*get_backlight)(struct omap_dss_device *dssdev);
29};
30
31#endif /* __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H */
diff --git a/arch/arm/plat-omap/include/plat/panel-generic-dpi.h b/arch/arm/plat-omap/include/plat/panel-generic-dpi.h
deleted file mode 100644
index 790619734bcd..000000000000
--- a/arch/arm/plat-omap/include/plat/panel-generic-dpi.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * Header for generic DPI panel driver
3 *
4 * Copyright (C) 2010 Canonical Ltd.
5 * Author: Bryan Wu <bryan.wu@canonical.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef __ARCH_ARM_PLAT_OMAP_PANEL_GENERIC_DPI_H
21#define __ARCH_ARM_PLAT_OMAP_PANEL_GENERIC_DPI_H
22
23#include "display.h"
24
25/**
26 * struct panel_generic_dpi_data - panel driver configuration data
27 * @name: panel name
28 * @platform_enable: platform specific panel enable function
29 * @platform_disable: platform specific panel disable function
30 */
31struct panel_generic_dpi_data {
32 const char *name;
33 int (*platform_enable)(struct omap_dss_device *dssdev);
34 void (*platform_disable)(struct omap_dss_device *dssdev);
35};
36
37#endif /* __ARCH_ARM_PLAT_OMAP_PANEL_GENERIC_DPI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-12 20:55:10 -0400