78 files changed, 5434 insertions, 229 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 29475101a7b3..aef63c8e3d2d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1241,7 +1241,7 @@ endmenu
 menu "CPU Power Management"
-if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA)
+if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA || ARCH_S3C64XX)
 source "drivers/cpufreq/Kconfig"
@@ -1272,6 +1272,10 @@ config CPU_FREQ_PXA
        default y
        select CPU_FREQ_DEFAULT_GOV_USERSPACE
+config CPU_FREQ_S3C64XX
+        bool "CPUfreq support for Samsung S3C64XX CPUs"
+        depends on CPU_FREQ && CPU_S3C6410
 endif
 source "drivers/cpuidle/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index a71fd941ade7..a89e4734b8f0 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -99,14 +99,6 @@ config DEBUG_CLPS711X_UART2
          output to the second serial port on these devices.  Saying N will
          cause the debug messages to appear on the first serial port.
-config DEBUG_S3C_PORT
-        depends on DEBUG_LL && PLAT_S3C
-        bool "Kernel low-level debugging messages via S3C UART"
-        help
-          Say Y here if you want debug print routines to go to one of the
-          S3C internal UARTs. The chosen UART must have been configured
-          before it is used.
 config DEBUG_S3C_UART
        depends on PLAT_S3C
        int "S3C UART to use for low-level debug"
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 01d49be3b2ca..4515728c5345 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -674,6 +674,15 @@ proc_types:
                b       __armv4_mmu_cache_off
                b       __armv5tej_mmu_cache_flush
+#ifdef CONFIG_CPU_FEROCEON_OLD_ID
+                /* this conflicts with the standard ARMv5TE entry */
+                .long   0x41009260              @ Old Feroceon
+                .long   0xff00fff0
+                b       __armv4_mmu_cache_on
+                b       __armv4_mmu_cache_off
+                b       __armv5tej_mmu_cache_flush
+#endif
                .word   0x66015261              @ FA526
                .word   0xff01fff1
                b       __fa526_cache_on
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 664c7b8b1ba8..337741f734ac 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -117,7 +117,7 @@ static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
        u32 val;
        spin_lock(&irq_controller_lock);
-        irq_desc[irq].cpu = cpu;
+        irq_desc[irq].node = cpu;
        val = readl(reg) & ~(0xff << shift);
        val |= 1 << (cpu + shift);
        writel(val, reg);
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index 887c6eb3a18a..6ed89836e908 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -229,14 +229,18 @@ static int vic_set_wake(unsigned int irq, unsigned int on)
 {
        struct vic_device *v = vic_from_irq(irq);
        unsigned int off = irq & 31;
+        u32 bit = 1 << off;
        if (!v)
                return -EINVAL;
+        if (!(bit & v->resume_sources))
+                return -EINVAL;
        if (on)
-                v->resume_irqs |= 1 << off;
+                v->resume_irqs |= bit;
        else
-                v->resume_irqs &= ~(1 << off);
+                v->resume_irqs &= ~bit;
        return 0;
 }
diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
new file mode 100644
index 000000000000..e49ed40f3be7
--- /dev/null
+++ b/arch/arm/configs/mini2440_defconfig
@@ -0,0 +1,2097 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.30-rc6
+# Wed May 20 12:29:51 2009
+#
+CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+CONFIG_NO_IOPORT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLK_DEV_INTEGRITY=y
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_FREEZER=y
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+CONFIG_ARCH_S3C2410=y
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+CONFIG_PLAT_S3C24XX=y
+CONFIG_S3C2410_CLOCK=y
+CONFIG_CPU_S3C244X=y
+CONFIG_S3C24XX_PWM=y
+CONFIG_S3C24XX_GPIO_EXTRA=0
+CONFIG_S3C2410_DMA=y
+# CONFIG_S3C2410_DMA_DEBUG is not set
+CONFIG_S3C24XX_ADC=y
+CONFIG_PLAT_S3C=y
+CONFIG_CPU_LLSERIAL_S3C2440_ONLY=y
+CONFIG_CPU_LLSERIAL_S3C2440=y
+#
+# Boot options
+#
+# CONFIG_S3C_BOOT_WATCHDOG is not set
+# CONFIG_S3C_BOOT_ERROR_RESET is not set
+CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
+#
+# Power management
+#
+# CONFIG_S3C2410_PM_DEBUG is not set
+# CONFIG_S3C2410_PM_CHECK is not set
+CONFIG_S3C_LOWLEVEL_UART_PORT=0
+CONFIG_S3C_GPIO_SPACE=0
+#
+# S3C2400 Machines
+#
+CONFIG_S3C2410_PM=y
+CONFIG_S3C2410_GPIO=y
+#
+# S3C2410 Machines
+#
+# CONFIG_ARCH_SMDK2410 is not set
+# CONFIG_ARCH_H1940 is not set
+# CONFIG_MACH_N30 is not set
+# CONFIG_ARCH_BAST is not set
+# CONFIG_MACH_OTOM is not set
+# CONFIG_MACH_AML_M5900 is not set
+# CONFIG_MACH_TCT_HAMMER is not set
+# CONFIG_MACH_VR1000 is not set
+# CONFIG_MACH_QT2410 is not set
+#
+# S3C2412 Machines
+#
+# CONFIG_MACH_JIVE is not set
+# CONFIG_MACH_SMDK2413 is not set
+# CONFIG_MACH_SMDK2412 is not set
+# CONFIG_MACH_VSTMS is not set
+CONFIG_CPU_S3C2440=y
+CONFIG_S3C2440_DMA=y
+#
+# S3C2440 Machines
+#
+# CONFIG_MACH_ANUBIS is not set
+# CONFIG_MACH_OSIRIS is not set
+# CONFIG_MACH_RX3715 is not set
+# CONFIG_ARCH_S3C2440 is not set
+# CONFIG_MACH_NEXCODER_2440 is not set
+# CONFIG_MACH_AT2440EVB is not set
+CONFIG_MACH_MINI2440=y
+#
+# S3C2442 Machines
+#
+#
+# S3C2443 Machines
+#
+# CONFIG_MACH_SMDK2443 is not set
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=200
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_ALIGNMENT_TRAP=y
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+#
+# CPU Power Management
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=m
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=m
+CONFIG_GARP=m
+CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIBTSDIO=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIVHCI=m
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=m
+CONFIG_CFG80211_REG_DEBUG=y
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+CONFIG_LIB80211_CRYPT_WEP=m
+CONFIG_LIB80211_CRYPT_CCMP=m
+CONFIG_LIB80211_CRYPT_TKIP=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=m
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_MINSTREL=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel"
+CONFIG_MAC80211_MESH=y
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_FTL=y
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=y
+CONFIG_RFD_FTL=y
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+CONFIG_MTD_ROM=y
+# CONFIG_MTD_ABSENT is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_PLATRAM is not set
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_S3C2410=y
+# CONFIG_MTD_NAND_S3C2410_DEBUG is not set
+# CONFIG_MTD_NAND_S3C2410_HWECC is not set
+# CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+#
+# LPDDR flash memory drivers
+#
+CONFIG_MTD_LPDDR=y
+CONFIG_MTD_QINFO_PROBE=y
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+CONFIG_DM9000=y
+CONFIG_DM9000_DEBUGLEVEL=4
+# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=m
+# CONFIG_LIBERTAS_USB is not set
+CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_SPI is not set
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_AT76C50X_USB is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_AR9170_USB is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+CONFIG_ZD1211RW=m
+CONFIG_ZD1211RW_DEBUG=y
+# CONFIG_RT2X00 is not set
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=m
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_RAW=y
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_UARTS=3
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_S3C2440=y
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=128
+CONFIG_IPMI_HANDLER=m
+# CONFIG_IPMI_PANIC_EVENT is not set
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_SI=m
+CONFIG_IPMI_WATCHDOG=m
+CONFIG_IPMI_POWEROFF=m
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+#
+# I2C Hardware Bus support
+#
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_S3C2410=y
+CONFIG_I2C_SIMTEC=y
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+CONFIG_SENSORS_TSL2550=m
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_S3C24XX=y
+# CONFIG_SPI_S3C24XX_GPIO is not set
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+#
+# Memory mapped GPIO expanders:
+#
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+#
+# PCI GPIO expanders:
+#
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IBMAEM is not set
+# CONFIG_SENSORS_IBMPEX is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+CONFIG_SENSORS_LM75=y
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_THERMAL=m
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_S3C2410_WATCHDOG=y
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+#
+# Multimedia devices
+#
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+CONFIG_DVB_CORE=m
+CONFIG_VIDEO_MEDIA=m
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L1=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_VIDEO_AU0828 is not set
+CONFIG_SOC_CAMERA=m
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+# CONFIG_SOC_CAMERA_MT9M111 is not set
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+CONFIG_SOC_CAMERA_PLATFORM=m
+# CONFIG_SOC_CAMERA_OV772X is not set
+# CONFIG_VIDEO_SH_MOBILE_CEU is not set
+CONFIG_V4L_USB_DRIVERS=y
+# CONFIG_USB_VIDEO_CLASS is not set
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+CONFIG_USB_GSPCA_ZC3XX=m
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_VICAM is not set
+# CONFIG_USB_IBMCAM is not set
+# CONFIG_USB_KONICAWC is not set
+# CONFIG_USB_QUICKCAM_MESSENGER is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_VIDEO_OVCAMCHIP is not set
+# CONFIG_USB_OV511 is not set
+# CONFIG_USB_SE401 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STV680 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_PWC_INPUT_EVDEV is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_SI470X is not set
+# CONFIG_USB_MR800 is not set
+# CONFIG_RADIO_TEA5764 is not set
+# CONFIG_DVB_DYNAMIC_MINORS is not set
+CONFIG_DVB_CAPTURE_DRIVERS=y
+# CONFIG_TTPCI_EEPROM is not set
+#
+# Supported USB Adapters
+#
+# CONFIG_DVB_USB is not set
+# CONFIG_DVB_SIANO_SMS1XXX is not set
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+# CONFIG_DVB_B2C2_FLEXCOP is not set
+#
+# Supported DVB Frontends
+#
+# CONFIG_DVB_FE_CUSTOMISE is not set
+# CONFIG_DAB is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_S3C2410=y
+# CONFIG_FB_S3C2410_DEBUG is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+#
+# Display hardware drivers
+#
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+CONFIG_FONT_MINI_4x6=y
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_JACK=y
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_SOC=y
+CONFIG_SND_S3C24XX_SOC=y
+CONFIG_SND_S3C24XX_SOC_I2S=y
+# CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650 is not set
+CONFIG_SND_S3C24XX_SOC_S3C24XX_UDA134X=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_L3=y
+CONFIG_SND_SOC_UDA134X=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_HID_PID=y
+CONFIG_USB_HIDDEV=y
+#
+# Special HID drivers
+#
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+# CONFIG_DRAGONRISE_FF is not set
+CONFIG_HID_EZKEY=y
+CONFIG_HID_KYE=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_NTRIG=y
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+# CONFIG_GREENASIA_FF is not set
+CONFIG_HID_TOPSEED=y
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+# CONFIG_USB_PRINTER is not set
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=m
+# CONFIG_USB_STORAGE_FREECOM is not set
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_ALAUDA=m
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+# CONFIG_USB_EZUSB is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+CONFIG_USB_SERIAL_CP210X=m
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+CONFIG_USB_SERIAL_FTDI_SIO=m
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+CONFIG_USB_SERIAL_SPCP8X5=m
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+CONFIG_USB_GADGET_S3C2410=y
+CONFIG_USB_S3C2410=y
+# CONFIG_USB_S3C2410_DEBUG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_CDC_COMPOSITE=m
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SPI=y
+CONFIG_MMC_S3C=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+#
+# LED drivers
+#
+CONFIG_LEDS_S3C24XX=y
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_PWM is not set
+# CONFIG_LEDS_BD2802 is not set
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+# CONFIG_RTC_DRV_TEST is not set
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_S3C=y
+CONFIG_DMADEVICES=y
+#
+# DMA Devices
+#
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+CONFIG_EXT2_FS=m
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_ROMFS_BACKED_BY_BLOCK is not set
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+CONFIG_ROMFS_BACKED_BY_BOTH=y
+CONFIG_ROMFS_ON_BLOCK=y
+CONFIG_ROMFS_ON_MTD=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_LDM_PARTITION=y
+# CONFIG_LDM_DEBUG is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+CONFIG_DEBUG_S3C_UART=0
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_SECURITY_FILE_CAPABILITIES=y
+CONFIG_CRYPTO=y
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_FIPS=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_SEQIV=m
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_ZLIB=m
+CONFIG_CRYPTO_LZO=m
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
index 2d58b8fe59be..b49810461e41 100644
--- a/arch/arm/configs/s3c2410_defconfig
+++ b/arch/arm/configs/s3c2410_defconfig
@@ -260,6 +260,7 @@ CONFIG_MACH_NEXCODER_2440=y
 CONFIG_SMDK2440_CPU2440=y
 CONFIG_MACH_AT2440EVB=y
 CONFIG_CPU_S3C2442=y
+CONFIG_MACH_MINI2440=y
 #
 # S3C2442 Machines
@@ -2298,7 +2299,6 @@ CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
-CONFIG_DEBUG_S3C_PORT=y
 CONFIG_DEBUG_S3C_UART=0
 #
diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig
index 2e8fa50e9a09..32860609e057 100644
--- a/arch/arm/configs/s3c6400_defconfig
+++ b/arch/arm/configs/s3c6400_defconfig
@@ -816,7 +816,6 @@ CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
-CONFIG_DEBUG_S3C_PORT=y
 CONFIG_DEBUG_S3C_UART=0
 #
diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig
index 07dfb98df4f0..9d32faef05f6 100644
--- a/arch/arm/configs/tct_hammer_defconfig
+++ b/arch/arm/configs/tct_hammer_defconfig
@@ -857,7 +857,6 @@ CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
-# CONFIG_DEBUG_S3C_PORT is not set
 CONFIG_DEBUG_S3C_UART=0
 #
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index be962c1349c4..9c746af1bf6e 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -12,7 +12,7 @@
 /* PAGE_SHIFT determines the page size */
 #define PAGE_SHIFT              12
-#define PAGE_SIZE               (1UL << PAGE_SHIFT)
+#define PAGE_SIZE               (_AC(1,UL) << PAGE_SHIFT)
 #define PAGE_MASK               (~(PAGE_SIZE-1))
 #ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 94cc58ef61ae..0e97b8cb77d5 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -389,6 +389,8 @@
 #define __NR_inotify_init1              (__NR_SYSCALL_BASE+360)
 #define __NR_preadv                     (__NR_SYSCALL_BASE+361)
 #define __NR_pwritev                    (__NR_SYSCALL_BASE+362)
+#define __NR_rt_tgsigqueueinfo          (__NR_SYSCALL_BASE+363)
+#define __NR_perf_counter_open          (__NR_SYSCALL_BASE+364)
 /*
 * The following SWIs are ARM private.
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 1680e9e9c831..f776e72a4cb8 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -372,6 +372,8 @@
 /* 360 */       CALL(sys_inotify_init1)
                CALL(sys_preadv)
                CALL(sys_pwritev)
+                CALL(sys_rt_tgsigqueueinfo)
+                CALL(sys_perf_counter_open)
 #ifndef syscalls_counted
 .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
 #define syscalls_counted
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 6874c7dca75a..b7c3490eaa24 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -98,17 +98,6 @@ unlock:
        return 0;
 }
-/* Handle bad interrupts */
-static struct irq_desc bad_irq_desc = {
-        .handle_irq = handle_bad_irq,
-        .lock = __SPIN_LOCK_UNLOCKED(bad_irq_desc.lock),
-};
-#ifdef CONFIG_CPUMASK_OFFSTACK
-/* We are not allocating bad_irq_desc.affinity or .pending_mask */
-#error "ARM architecture does not support CONFIG_CPUMASK_OFFSTACK."
-#endif
 /*
 * do_IRQ handles all hardware IRQ's.  Decoded IRQs should not
 * come via this function.  Instead, they should provide their
@@ -124,10 +113,13 @@ asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
         * Some hardware gives randomly wrong interrupts.  Rather
         * than crashing, do something sensible.
         */
-        if (irq >= NR_IRQS)
+        if (unlikely(irq >= NR_IRQS)) {
-                handle_bad_irq(irq, &bad_irq_desc);
+                if (printk_ratelimit())
-        else
+                        printk(KERN_WARNING "Bad IRQ%u\n", irq);
+                ack_bad_irq(irq);
+        } else {
                generic_handle_irq(irq);
+        }
        /* AT91 specific workaround */
        irq_finish(irq);
@@ -165,10 +157,6 @@ void __init init_IRQ(void)
        for (irq = 0; irq < NR_IRQS; irq++)
                irq_desc[irq].status |= IRQ_NOREQUEST | IRQ_NOPROBE;
-#ifdef CONFIG_SMP
-        cpumask_setall(bad_irq_desc.affinity);
-        bad_irq_desc.cpu = smp_processor_id();
-#endif
        init_arch_irq();
 }
@@ -176,7 +164,7 @@ void __init init_IRQ(void)
 static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
 {
-        pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->cpu, cpu);
+        pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->node, cpu);
        spin_lock_irq(&desc->lock);
        desc->chip->set_affinity(irq, cpumask_of(cpu));
@@ -195,7 +183,7 @@ void migrate_irqs(void)
        for (i = 0; i < NR_IRQS; i++) {
                struct irq_desc *desc = irq_desc + i;
-                if (desc->cpu == cpu) {
+                if (desc->node == cpu) {
                        unsigned int newcpu = cpumask_any_and(desc->affinity,
                                                              cpu_online_mask);
                        if (newcpu >= nr_cpu_ids) {
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 1585423699ee..39196dff478c 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -114,9 +114,6 @@ void arm_machine_restart(char mode, const char *cmd)
 /*
 * Function pointers to optional machine specific functions
 */
-void (*pm_idle)(void);
-EXPORT_SYMBOL(pm_idle);
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
@@ -130,20 +127,19 @@ EXPORT_SYMBOL_GPL(arm_pm_restart);
 */
 static void default_idle(void)
 {
-        if (hlt_counter)
+        if (!need_resched())
-                cpu_relax();
+                arch_idle();
-        else {
+        local_irq_enable();
-                local_irq_disable();
-                if (!need_resched())
-                        arch_idle();
-                local_irq_enable();
-        }
 }
+void (*pm_idle)(void) = default_idle;
+EXPORT_SYMBOL(pm_idle);
 /*
- * The idle thread.  We try to conserve power, while trying to keep
+ * The idle thread, has rather strange semantics for calling pm_idle,
- * overall latency low.  The architecture specific idle is passed
+ * but this is what x86 does and we need to do the same, so that
- * a value to indicate the level of "idleness" of the system.
+ * things like cpuidle get called in the same way.  The only difference
+ * is that we always respect 'hlt_counter' to prevent low power idle.
 */
 void cpu_idle(void)
 {
@@ -151,21 +147,31 @@ void cpu_idle(void)
        /* endless idle loop with no priority at all */
        while (1) {
-                void (*idle)(void) = pm_idle;
+                tick_nohz_stop_sched_tick(1);
+                leds_event(led_idle_start);
+                while (!need_resched()) {
 #ifdef CONFIG_HOTPLUG_CPU
-                if (cpu_is_offline(smp_processor_id())) {
+                        if (cpu_is_offline(smp_processor_id()))
-                        leds_event(led_idle_start);
+                                cpu_die();
-                        cpu_die();
-                }
 #endif
-                if (!idle)
+                        local_irq_disable();
-                        idle = default_idle;
+                        if (hlt_counter) {
-                leds_event(led_idle_start);
+                                local_irq_enable();
-                tick_nohz_stop_sched_tick(1);
+                                cpu_relax();
-                while (!need_resched())
+                        } else {
-                        idle();
+                                stop_critical_timings();
+                                pm_idle();
+                                start_critical_timings();
+                                /*
+                                 * This will eventually be removed - pm_idle
+                                 * functions should always return with IRQs
+                                 * enabled.
+                                 */
+                                WARN_ON(irqs_disabled());
+                                local_irq_enable();
+                        }
+                }
                leds_event(led_idle_end);
                tick_nohz_restart_sched_tick();
                preempt_enable_no_resched();
@@ -352,6 +358,23 @@ asm(	".section .text\n"
 "       .size   kernel_thread_helper, . - kernel_thread_helper\n"
 "       .previous");
+#ifdef CONFIG_ARM_UNWIND
+extern void kernel_thread_exit(long code);
+asm(    ".section .text\n"
+"       .align\n"
+"       .type   kernel_thread_exit, #function\n"
+"kernel_thread_exit:\n"
+"       .fnstart\n"
+"       .cantunwind\n"
+"       bl      do_exit\n"
+"       nop\n"
+"       .fnend\n"
+"       .size   kernel_thread_exit, . - kernel_thread_exit\n"
+"       .previous");
+#else
+#define kernel_thread_exit      do_exit
+#endif
 /*
 * Create a kernel thread.
 */
@@ -363,7 +386,7 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
        regs.ARM_r1 = (unsigned long)arg;
        regs.ARM_r2 = (unsigned long)fn;
-        regs.ARM_r3 = (unsigned long)do_exit;
+        regs.ARM_r3 = (unsigned long)kernel_thread_exit;
        regs.ARM_pc = (unsigned long)kernel_thread_helper;
        regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE;
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index 1dedc2c7ff49..dd56e11f339a 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -212,7 +212,8 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
                        ctrl->vrs[14] = *vsp++;
                ctrl->vrs[SP] = (unsigned long)vsp;
        } else if (insn == 0xb0) {
-                ctrl->vrs[PC] = ctrl->vrs[LR];
+                if (ctrl->vrs[PC] == 0)
+                        ctrl->vrs[PC] = ctrl->vrs[LR];
                /* no further processing */
                ctrl->entries = 0;
        } else if (insn == 0xb1) {
@@ -309,18 +310,20 @@ int unwind_frame(struct stackframe *frame)
        }
        while (ctrl.entries > 0) {
-                int urc;
+                int urc = unwind_exec_insn(&ctrl);
-                if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high)
-                        return -URC_FAILURE;
-                urc = unwind_exec_insn(&ctrl);
                if (urc < 0)
                        return urc;
+                if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high)
+                        return -URC_FAILURE;
        }
        if (ctrl.vrs[PC] == 0)
                ctrl.vrs[PC] = ctrl.vrs[LR];
+        /* check for infinite loop */
+        if (frame->pc == ctrl.vrs[PC])
+                return -URC_FAILURE;
        frame->fp = ctrl.vrs[FP];
        frame->sp = ctrl.vrs[SP];
        frame->lr = ctrl.vrs[LR];
@@ -332,7 +335,6 @@ int unwind_frame(struct stackframe *frame)
 void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk)
 {
        struct stackframe frame;
-        unsigned long high, low;
        register unsigned long current_sp asm ("sp");
        pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
@@ -362,9 +364,6 @@ void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk)
                frame.pc = thread_saved_pc(tsk);
        }
-        low = frame.sp & ~(THREAD_SIZE - 1);
-        high = low + THREAD_SIZE;
        while (1) {
                int urc;
                unsigned long where = frame.pc;
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index e256c57b8981..5cc4812c9763 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -6,6 +6,7 @@
 #include <asm-generic/vmlinux.lds.h>
 #include <asm/thread_info.h>
 #include <asm/memory.h>
+#include <asm/page.h>
        
 OUTPUT_ARCH(arm)
 ENTRY(stext)
@@ -63,7 +64,7 @@ SECTIONS
                        usr/built-in.o(.init.ramfs)
                __initramfs_end = .;
 #endif
-                . = ALIGN(4096);
+                . = ALIGN(PAGE_SIZE);
                __per_cpu_load = .;
                __per_cpu_start = .;
                        *(.data.percpu.page_aligned)
@@ -73,7 +74,7 @@ SECTIONS
 #ifndef CONFIG_XIP_KERNEL
                __init_begin = _stext;
                INIT_DATA
-                . = ALIGN(4096);
+                . = ALIGN(PAGE_SIZE);
                __init_end = .;
 #endif
        }
@@ -85,6 +86,14 @@ SECTIONS
                *(.discard)
                *(.ARM.exidx.exit.text)
                *(.ARM.extab.exit.text)
+#ifndef CONFIG_HOTPLUG_CPU
+                *(.ARM.exidx.cpuexit.text)
+                *(.ARM.extab.cpuexit.text)
+#endif
+#ifndef CONFIG_HOTPLUG
+                *(.ARM.exidx.devexit.text)
+                *(.ARM.extab.devexit.text)
+#endif
 #ifndef CONFIG_MMU
                *(.fixup)
                *(__ex_table)
@@ -111,7 +120,7 @@ SECTIONS
                *(.got)                 /* Global offset table          */
        }
-        RODATA
+        RO_DATA(PAGE_SIZE)
        _etext = .;                     /* End of text and rodata section */
@@ -151,17 +160,17 @@ SECTIONS
                *(.data.init_task)
 #ifdef CONFIG_XIP_KERNEL
-                . = ALIGN(4096);
+                . = ALIGN(PAGE_SIZE);
                __init_begin = .;
                INIT_DATA
-                . = ALIGN(4096);
+                . = ALIGN(PAGE_SIZE);
                __init_end = .;
 #endif
-                . = ALIGN(4096);
+                . = ALIGN(PAGE_SIZE);
                __nosave_begin = .;
                *(.data.nosave)
-                . = ALIGN(4096);
+                . = ALIGN(PAGE_SIZE);
                __nosave_end = .;
                /*
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index cc270beadd5d..a55398ed1211 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -24,6 +24,8 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/at73c213.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
 #include <linux/clk.h>
 #include <mach/hardware.h>
@@ -218,6 +220,56 @@ static struct gpio_led ek_leds[] = {
        }
 };
+/*
+ * GPIO Buttons
+ */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button ek_buttons[] = {
+        {
+                .gpio           = AT91_PIN_PA30,
+                .code           = BTN_3,
+                .desc           = "Button 3",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+        {
+                .gpio           = AT91_PIN_PA31,
+                .code           = BTN_4,
+                .desc           = "Button 4",
+                .active_low     = 1,
+                .wakeup         = 1,
+        }
+};
+static struct gpio_keys_platform_data ek_button_data = {
+        .buttons        = ek_buttons,
+        .nbuttons       = ARRAY_SIZE(ek_buttons),
+};
+static struct platform_device ek_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ek_button_data,
+        }
+};
+static void __init ek_add_device_buttons(void)
+{
+        at91_set_gpio_input(AT91_PIN_PA30, 1);  /* btn3 */
+        at91_set_deglitch(AT91_PIN_PA30, 1);
+        at91_set_gpio_input(AT91_PIN_PA31, 1);  /* btn4 */
+        at91_set_deglitch(AT91_PIN_PA31, 1);
+        platform_device_register(&ek_button_device);
+}
+#else
+static void __init ek_add_device_buttons(void) {}
+#endif
 static struct i2c_board_info __initdata ek_i2c_devices[] = {
        {
                I2C_BOARD_INFO("24c512", 0x50),
@@ -245,6 +297,8 @@ static void __init ek_board_init(void)
        at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
        /* LEDs */
        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        /* Push Buttons */
+        ek_add_device_buttons();
        /* PCK0 provides MCLK to the WM8731 */
        at91_set_B_periph(AT91_PIN_PC1, 0);
        /* SSC (for WM8731) */
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index 35e12a49d1a6..f6b5672cabd6 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -186,19 +186,21 @@ static struct fb_monspecs at91fb_default_monspecs = {
 static void at91_lcdc_power_control(int on)
 {
        if (on)
-                at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
+                at91_set_gpio_value(AT91_PIN_PC1, 0);   /* power up */
        else
-                at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
+                at91_set_gpio_value(AT91_PIN_PC1, 1);   /* power down */
 }
 /* Driver datas */
 static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
+        .lcdcon_is_backlight            = true,
        .default_bpp                    = 16,
        .default_dmacon                 = ATMEL_LCDC_DMAEN,
        .default_lcdcon2                = AT91SAM9RL_DEFAULT_LCDCON2,
        .default_monspecs               = &at91fb_default_monspecs,
        .atmel_lcdfb_power_control      = at91_lcdc_power_control,
        .guard_time                     = 1,
+        .lcd_wiring_mode                = ATMEL_LCDC_WIRING_RGB,
 };
 #else
diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h
index aa482841270b..b520c4b5678a 100644
--- a/arch/arm/mach-davinci/include/mach/nand.h
+++ b/arch/arm/mach-davinci/include/mach/nand.h
@@ -68,10 +68,14 @@ struct davinci_nand_pdata {		/* platform_data */
        /* none  == NAND_ECC_NONE (strongly *not* advised!!)
         * soft  == NAND_ECC_SOFT
-         * 1-bit == NAND_ECC_HW
+         * else  == NAND_ECC_HW, according to ecc_bits
-         * 4-bit == NAND_ECC_HW_SYNDROME (not on all chips)
+         *
+         * All DaVinci-family chips support 1-bit hardware ECC.
+         * Newer ones also support 4-bit ECC, but are awkward
+         * using it with large page chips.
         */
        nand_ecc_modes_t        ecc_mode;
+        u8                      ecc_bits;
        /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */
        unsigned                options;
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index e70fc7c66bbb..ed2a48a9ce74 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -36,7 +36,6 @@
 #include <mach/hwa742.h>
 #include <mach/lcd_mipid.h>
 #include <mach/mmc.h>
-#include <mach/usb.h>
 #include <mach/clock.h>
 #define ADS7846_PENDOWN_GPIO    15
@@ -205,9 +204,11 @@ static int nokia770_mmc_get_cover_state(struct device *dev, int slot)
 static struct omap_mmc_platform_data nokia770_mmc2_data = {
        .nr_slots                       = 1,
        .dma_mask                       = 0xffffffff,
+        .max_freq                       = 12000000,
        .slots[0]       = {
                .set_power              = nokia770_mmc_set_power,
                .get_cover_state        = nokia770_mmc_get_cover_state,
+                .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
                .name                   = "mmcblk",
        },
 };
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
index 0af4d6c85b47..6810b4aeb02c 100644
--- a/arch/arm/mach-omap1/mailbox.c
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -203,5 +203,5 @@ module_exit(omap1_mbox_exit);
 MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("omap mailbox: omap1 architecture specific functions");
-MODULE_AUTHOR("Hiroshi DOYU" <Hiroshi.DOYU@nokia.com>);
+MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
 MODULE_ALIAS("platform:omap1-mailbox");
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index da93b86234ed..9a0bf6744a05 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -362,6 +362,7 @@ static struct omap_onenand_platform_data board_onenand_data = {
        .gpio_irq       = 65,
        .parts          = onenand_partitions,
        .nr_parts       = ARRAY_SIZE(onenand_partitions),
+        .flags          = ONENAND_SYNC_READWRITE,
 };
 static void __init board_onenand_init(void)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ba528f85749c..b0665f161c03 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -302,7 +302,7 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
                udelay(1);
        }
-        if (i < MAX_CLOCK_ENABLE_WAIT)
+        if (i <= MAX_CLOCK_ENABLE_WAIT)
                pr_debug("Clock %s stable after %d loops\n", name, i);
        else
                printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 9e43fe5209d3..045da923e75b 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -286,6 +286,20 @@ static struct omap_clk omap34xx_clks[] = {
 #define MIN_SDRC_DLL_LOCK_FREQ          83000000
+#define CYCLES_PER_MHZ                  1000000
+/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
+#define SDRC_MPURATE_SCALE              8
+/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
+#define SDRC_MPURATE_BASE_SHIFT         9
+/*
+ * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
+ * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
+ */
+#define SDRC_MPURATE_LOOPS              96
 /**
 * omap3_dpll_recalc - recalculate DPLL rate
 * @clk: DPLL struct clk
@@ -709,7 +723,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 {
        u32 new_div = 0;
        u32 unlock_dll = 0;
-        unsigned long validrate, sdrcrate;
+        u32 c;
+        unsigned long validrate, sdrcrate, mpurate;
        struct omap_sdrc_params *sp;
        if (!clk || !rate)
@@ -718,18 +733,15 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
        if (clk != &dpll3_m2_ck)
                return -EINVAL;
-        if (rate == clk->rate)
-                return 0;
        validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
        if (validrate != rate)
                return -EINVAL;
        sdrcrate = sdrc_ick.rate;
        if (rate > clk->rate)
-                sdrcrate <<= ((rate / clk->rate) - 1);
+                sdrcrate <<= ((rate / clk->rate) >> 1);
        else
-                sdrcrate >>= ((clk->rate / rate) - 1);
+                sdrcrate >>= ((clk->rate / rate) >> 1);
        sp = omap2_sdrc_get_params(sdrcrate);
        if (!sp)
@@ -740,17 +752,25 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
                unlock_dll = 1;
        }
+        /*
+         * XXX This only needs to be done when the CPU frequency changes
+         */
+        mpurate = arm_fck.rate / CYCLES_PER_MHZ;
+        c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
+        c += 1;  /* for safety */
+        c *= SDRC_MPURATE_LOOPS;
+        c >>= SDRC_MPURATE_SCALE;
+        if (c == 0)
+                c = 1;
        pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
                 validrate);
        pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
                 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
-        /* REVISIT: SRAM code doesn't support other M2 divisors yet */
-        WARN_ON(new_div != 1 && new_div != 2);
-        /* REVISIT: Add SDRC_MR changing to this code also */
        omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
-                                  sp->actim_ctrlb, new_div, unlock_dll);
+                                  sp->actim_ctrlb, new_div, unlock_dll, c,
+                                  sp->mr, rate > clk->rate);
        return 0;
 }
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 2fd22f9c5f0e..54fec53a48e7 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -31,6 +31,8 @@ static struct platform_device gpmc_onenand_device = {
 static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
 {
        struct gpmc_timings t;
+        u32 reg;
+        int err;
        const int t_cer = 15;
        const int t_avdp = 12;
@@ -43,6 +45,11 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
        const int t_wpl = 40;
        const int t_wph = 30;
+        /* Ensure sync read and sync write are disabled */
+        reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
+        reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
+        writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
        memset(&t, 0, sizeof(t));
        t.sync_clk = 0;
        t.cs_on = 0;
@@ -74,7 +81,16 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
                          GPMC_CONFIG1_DEVICESIZE_16 |
                          GPMC_CONFIG1_MUXADDDATA);
-        return gpmc_cs_set_timings(cs, &t);
+        err = gpmc_cs_set_timings(cs, &t);
+        if (err)
+                return err;
+        /* Ensure sync read and sync write are disabled */
+        reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
+        reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
+        writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
+        return 0;
 }
 static void set_onenand_cfg(void __iomem *onenand_base, int latency,
@@ -124,7 +140,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
        } else if (cfg->flags & ONENAND_SYNC_READWRITE) {
                sync_read = 1;
                sync_write = 1;
-        }
+        } else
+                return omap2_onenand_set_async_mode(cs, onenand_base);
        if (!freq) {
                /* Very first call freq is not known */
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 458990e20c60..a98201cc265c 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -48,6 +48,28 @@ int omap_chip_is(struct omap_chip_id oci)
 }
 EXPORT_SYMBOL(omap_chip_is);
+int omap_type(void)
+{
+        u32 val = 0;
+        if (cpu_is_omap24xx())
+                val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
+        else if (cpu_is_omap34xx())
+                val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
+        else {
+                pr_err("Cannot detect omap type!\n");
+                goto out;
+        }
+        val &= OMAP2_DEVICETYPE_MASK;
+        val >>= 8;
+out:
+        return val;
+}
+EXPORT_SYMBOL(omap_type);
 /*----------------------------------------------------------------------------*/
 #define OMAP_TAP_IDCODE         0x0204
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 32afd9448216..3a86b0f66031 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -21,6 +21,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/clk.h>
 #include <asm/tlb.h>
@@ -241,6 +242,40 @@ void __init omap2_map_common_io(void)
        omapfb_reserve_sdram();
 }
+/*
+ * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
+ *
+ * Sets the CORE DPLL3 M2 divider to the same value that it's at
+ * currently.  This has the effect of setting the SDRC SDRAM AC timing
+ * registers to the values currently defined by the kernel.  Currently
+ * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
+ * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
+ * or passes along the return value of clk_set_rate().
+ */
+static int __init _omap2_init_reprogram_sdrc(void)
+{
+        struct clk *dpll3_m2_ck;
+        int v = -EINVAL;
+        long rate;
+        if (!cpu_is_omap34xx())
+                return 0;
+        dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
+        if (!dpll3_m2_ck)
+                return -EINVAL;
+        rate = clk_get_rate(dpll3_m2_ck);
+        pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
+        v = clk_set_rate(dpll3_m2_ck, rate);
+        if (v)
+                pr_err("dpll3_m2_clk rate change failed: %d\n", v);
+        clk_put(dpll3_m2_ck);
+        return v;
+}
 void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
 {
        omap2_mux_init();
@@ -249,6 +284,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
        clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
        omap2_clk_init();
        omap2_sdrc_init(sp);
+        _omap2_init_reprogram_sdrc();
 #endif
        gpmc_init();
 }
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index fd5b8a5925cc..6f71f3730c97 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -282,12 +282,12 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
                return -ENOMEM;
        /* DSP or IVA2 IRQ */
-        mbox_dsp_info.irq = platform_get_irq(pdev, 0);
+        ret = platform_get_irq(pdev, 0);
-        if (mbox_dsp_info.irq < 0) {
+        if (ret < 0) {
                dev_err(&pdev->dev, "invalid irq resource\n");
-                ret = -ENODEV;
                goto err_dsp;
        }
+        mbox_dsp_info.irq = ret;
        ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
        if (ret)
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c
index 9756a878fd90..1541fd4c8d0f 100644
--- a/arch/arm/mach-omap2/mmc-twl4030.c
+++ b/arch/arm/mach-omap2/mmc-twl4030.c
@@ -263,8 +263,19 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
 static int twl_mmc23_set_power(struct device *dev, int slot, int power_on, int vdd)
 {
        int ret = 0;
-        struct twl_mmc_controller *c = &hsmmc[1];
+        struct twl_mmc_controller *c = NULL;
        struct omap_mmc_platform_data *mmc = dev->platform_data;
+        int i;
+        for (i = 1; i < ARRAY_SIZE(hsmmc); i++) {
+                if (mmc == hsmmc[i].mmc) {
+                        c = &hsmmc[i];
+                        break;
+                }
+        }
+        if (c == NULL)
+                return -ENODEV;
        /* If we don't see a Vcc regulator, assume it's a fixed
         * voltage always-on regulator.
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 73e2971b1757..983f1cb676be 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -1099,7 +1099,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
               (c++ < PWRDM_TRANSITION_BAILOUT))
                udelay(1);
-        if (c >= PWRDM_TRANSITION_BAILOUT) {
+        if (c > PWRDM_TRANSITION_BAILOUT) {
                printk(KERN_ERR "powerdomain: waited too long for "
                       "powerdomain %s to complete transition\n", pwrdm->name);
                return -EAGAIN;
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index c080c82521e1..f41f8d96ddba 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -3,13 +3,12 @@
 *
 * Omap3 specific functions that need to be run in internal SRAM
 *
- * (C) Copyright 2007
+ * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
- * Texas Instruments Inc.
+ * Copyright (C) 2008 Nokia Corporation
- * Rajendra Nayak <rnayak@ti.com>
 *
- * (C) Copyright 2004
+ * Rajendra Nayak <rnayak@ti.com>
- * Texas Instruments, <www.ti.com>
 * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
@@ -37,61 +36,112 @@
        .text
+/* r4 parameters */
+#define SDRC_NO_UNLOCK_DLL              0x0
+#define SDRC_UNLOCK_DLL                 0x1
+/* SDRC_DLLA_CTRL bit settings */
+#define FIXEDDELAY_SHIFT                24
+#define FIXEDDELAY_MASK                 (0xff << FIXEDDELAY_SHIFT)
+#define DLLIDLE_MASK                    0x4
+/*
+ * SDRC_DLLA_CTRL default values: TI hardware team indicates that
+ * FIXEDDELAY should be initialized to 0xf.  This apparently was
+ * empirically determined during process testing, so no derivation
+ * was provided.
+ */
+#define FIXEDDELAY_DEFAULT              (0x0f << FIXEDDELAY_SHIFT)
+/* SDRC_DLLA_STATUS bit settings */
+#define LOCKSTATUS_MASK                 0x4
+/* SDRC_POWER bit settings */
+#define SRFRONIDLEREQ_MASK              0x40
+#define PWDENA_MASK                     0x4
+/* CM_IDLEST1_CORE bit settings */
+#define ST_SDRC_MASK                    0x2
+/* CM_ICLKEN1_CORE bit settings */
+#define EN_SDRC_MASK                    0x2
+/* CM_CLKSEL1_PLL bit settings */
+#define CORE_DPLL_CLKOUT_DIV_SHIFT      0x1b
 /*
- * Change frequency of core dpll
+ * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
- * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
+ * r0 = new SDRC_RFR_CTRL register contents
- * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
+ * r1 = new SDRC_ACTIM_CTRLA register contents
+ * r2 = new SDRC_ACTIM_CTRLB register contents
+ * r3 = new M2 divider setting (only 1 and 2 supported right now)
+ * r4 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
 *      SDRC rates < 83MHz
+ * r5 = number of MPU cycles to wait for SDRC to stabilize after
+ *      reprogramming the SDRC when switching to a slower MPU speed
+ * r6 = new SDRC_MR_0 register value
+ * r7 = increasing SDRC rate? (1 = yes, 0 = no)
+ *
 */
 ENTRY(omap3_sram_configure_core_dpll)
        stmfd   sp!, {r1-r12, lr}       @ store regs to stack
        ldr     r4, [sp, #52]           @ pull extra args off the stack
+        ldr     r5, [sp, #56]           @ load extra args from the stack
+        ldr     r6, [sp, #60]           @ load extra args from the stack
+        ldr     r7, [sp, #64]           @ load extra args from the stack
        dsb                             @ flush buffered writes to interconnect
-        cmp     r3, #0x2
+        cmp     r7, #1                  @ if increasing SDRC clk rate,
-        blne    configure_sdrc
+        bleq    configure_sdrc          @ program the SDRC regs early (for RFR)
-        cmp     r4, #0x1
+        cmp     r4, #SDRC_UNLOCK_DLL    @ set the intended DLL state
        bleq    unlock_dll
        blne    lock_dll
-        bl      sdram_in_selfrefresh    @ put the SDRAM in self refresh
+        bl      sdram_in_selfrefresh    @ put SDRAM in self refresh, idle SDRC
-        bl      configure_core_dpll
+        bl      configure_core_dpll     @ change the DPLL3 M2 divider
-        bl      enable_sdrc
+        bl      enable_sdrc             @ take SDRC out of idle
-        cmp     r4, #0x1
+        cmp     r4, #SDRC_UNLOCK_DLL    @ wait for DLL status to change
        bleq    wait_dll_unlock
        blne    wait_dll_lock
-        cmp     r3, #0x1
+        cmp     r7, #1                  @ if increasing SDRC clk rate,
-        blne    configure_sdrc
+        beq     return_to_sdram         @ return to SDRAM code, otherwise,
+        bl      configure_sdrc          @ reprogram SDRC regs now
+        mov     r12, r5
+        bl      wait_clk_stable         @ wait for SDRC to stabilize
+return_to_sdram:
        isb                             @ prevent speculative exec past here
        mov     r0, #0                  @ return value
        ldmfd   sp!, {r1-r12, pc}       @ restore regs and return
 unlock_dll:
        ldr     r11, omap3_sdrc_dlla_ctrl
        ldr     r12, [r11]
-        orr     r12, r12, #0x4
+        and     r12, r12, #FIXEDDELAY_MASK
+        orr     r12, r12, #FIXEDDELAY_DEFAULT
+        orr     r12, r12, #DLLIDLE_MASK
        str     r12, [r11]              @ (no OCP barrier needed)
        bx      lr
 lock_dll:
        ldr     r11, omap3_sdrc_dlla_ctrl
        ldr     r12, [r11]
-        bic     r12, r12, #0x4
+        bic     r12, r12, #DLLIDLE_MASK
        str     r12, [r11]              @ (no OCP barrier needed)
        bx      lr
 sdram_in_selfrefresh:
        ldr     r11, omap3_sdrc_power   @ read the SDRC_POWER register
        ldr     r12, [r11]              @ read the contents of SDRC_POWER
        mov     r9, r12                 @ keep a copy of SDRC_POWER bits
-        orr     r12, r12, #0x40         @ enable self refresh on idle req
+        orr     r12, r12, #SRFRONIDLEREQ_MASK   @ enable self refresh on idle
-        bic     r12, r12, #0x4          @ clear PWDENA
+        bic     r12, r12, #PWDENA_MASK  @ clear PWDENA
        str     r12, [r11]              @ write back to SDRC_POWER register
        ldr     r12, [r11]              @ posted-write barrier for SDRC
+idle_sdrc:
        ldr     r11, omap3_cm_iclken1_core      @ read the CM_ICLKEN1_CORE reg
        ldr     r12, [r11]
-        bic     r12, r12, #0x2          @ disable iclk bit for SDRC
+        bic     r12, r12, #EN_SDRC_MASK         @ disable iclk bit for SDRC
        str     r12, [r11]
 wait_sdrc_idle:
        ldr     r11, omap3_cm_idlest1_core
        ldr     r12, [r11]
-        and     r12, r12, #0x2          @ check for SDRC idle
+        and     r12, r12, #ST_SDRC_MASK         @ check for SDRC idle
-        cmp     r12, #2
+        cmp     r12, #ST_SDRC_MASK
        bne     wait_sdrc_idle
        bx      lr
 configure_core_dpll:
@@ -99,36 +149,23 @@ configure_core_dpll:
        ldr     r12, [r11]
        ldr     r10, core_m2_mask_val   @ modify m2 for core dpll
        and     r12, r12, r10
-        orr     r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
+        orr     r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
        str     r12, [r11]
        ldr     r12, [r11]              @ posted-write barrier for CM
-        mov     r12, #0x800             @ wait for the clock to stabilise
-        cmp     r3, #2
-        bne     wait_clk_stable
        bx      lr
 wait_clk_stable:
        subs    r12, r12, #1
        bne     wait_clk_stable
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
        bx      lr
 enable_sdrc:
        ldr     r11, omap3_cm_iclken1_core
        ldr     r12, [r11]
-        orr     r12, r12, #0x2          @ enable iclk bit for SDRC
+        orr     r12, r12, #EN_SDRC_MASK         @ enable iclk bit for SDRC
        str     r12, [r11]
 wait_sdrc_idle1:
        ldr     r11, omap3_cm_idlest1_core
        ldr     r12, [r11]
-        and     r12, r12, #0x2
+        and     r12, r12, #ST_SDRC_MASK
        cmp     r12, #0
        bne     wait_sdrc_idle1
 restore_sdrc_power_val:
@@ -138,14 +175,14 @@ restore_sdrc_power_val:
 wait_dll_lock:
        ldr     r11, omap3_sdrc_dlla_status
        ldr     r12, [r11]
-        and     r12, r12, #0x4
+        and     r12, r12, #LOCKSTATUS_MASK
-        cmp     r12, #0x4
+        cmp     r12, #LOCKSTATUS_MASK
        bne     wait_dll_lock
        bx      lr
 wait_dll_unlock:
        ldr     r11, omap3_sdrc_dlla_status
        ldr     r12, [r11]
-        and     r12, r12, #0x4
+        and     r12, r12, #LOCKSTATUS_MASK
        cmp     r12, #0x0
        bne     wait_dll_unlock
        bx      lr
@@ -156,7 +193,9 @@ configure_sdrc:
        str     r1, [r11]
        ldr     r11, omap3_sdrc_actim_ctrlb
        str     r2, [r11]
-        ldr     r2, [r11]               @ posted-write barrier for SDRC
+        ldr     r11, omap3_sdrc_mr_0
+        str     r6, [r11]
+        ldr     r6, [r11]               @ posted-write barrier for SDRC
        bx      lr
 omap3_sdrc_power:
@@ -173,6 +212,8 @@ omap3_sdrc_actim_ctrla:
        .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
 omap3_sdrc_actim_ctrlb:
        .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
+omap3_sdrc_mr_0:
+        .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
 omap3_sdrc_dlla_status:
        .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 omap3_sdrc_dlla_ctrl:
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 6f3f77d031d0..d78731edebb6 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -200,6 +200,6 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
 int __init orion5x_setup_sram_win(void)
 {
-        return setup_cpu_win(win_alloc_count, ORION5X_SRAM_PHYS_BASE,
+        return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE,
                        ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1);
 }
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index eafcc49009ea..f87fa1253803 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -562,7 +562,7 @@ static struct platform_device orion5x_crypto_device = {
        .resource       = orion5x_crypto_res,
 };
-int __init orion5x_crypto_init(void)
+static int __init orion5x_crypto_init(void)
 {
        int ret;
@@ -697,6 +697,14 @@ void __init orion5x_init(void)
        }
        /*
+         * The 5082/5181l/5182/6082/6082l/6183 have crypto
+         * while 5180n/5181/5281 don't have crypto.
+         */
+        if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
+            dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
+                orion5x_crypto_init();
+        /*
         * Register watchdog driver
         */
        orion5x_wdt_init();
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index de483e83edd7..8f004503c96d 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -38,7 +38,6 @@ void orion5x_spi_init(void);
 void orion5x_uart0_init(void);
 void orion5x_uart1_init(void);
 void orion5x_xor_init(void);
-int orion5x_crypto_init(void);
 /*
 * PCIe/PCI functions.
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index f4533f8ff4e8..89c992b8f75b 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -401,6 +401,16 @@ config MACH_PALMZ72
          Say Y here if you intend to run this kernel on Palm Zire 72
          handheld computer.
+config MACH_TREO680
+        bool "Palm Treo 680"
+        default y
+        depends on ARCH_PXA_PALM
+        select PXA27x
+        select IWMMXT
+        help
+          Say Y here if you intend to run this kernel on Palm Treo 680
+          smartphone.
 config MACH_PALMLD
        bool "Palm LifeDrive"
        default y
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index d18ffef44b8c..d4c6122a342f 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -62,6 +62,7 @@ obj-$(CONFIG_MACH_PALMT5)	+= palmt5.o
 obj-$(CONFIG_MACH_PALMTX)       += palmtx.o
 obj-$(CONFIG_MACH_PALMLD)       += palmld.o
 obj-$(CONFIG_MACH_PALMZ72)      += palmz72.o
+obj-$(CONFIG_MACH_TREO680)      += treo680.o
 obj-$(CONFIG_ARCH_VIPER)        += viper.o
 ifeq ($(CONFIG_MACH_ZYLONITE),y)
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 962dda2e154a..5363e1aea3fb 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -23,6 +23,7 @@
 #include <linux/pm.h>
 #include <linux/gpio.h>
 #include <linux/backlight.h>
+#include <linux/i2c.h>
 #include <linux/io.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
@@ -600,6 +601,10 @@ static struct platform_device *devices[] __initdata = {
        &sharpsl_rom_device,
 };
+static struct i2c_board_info __initdata corgi_i2c_devices[] = {
+        { I2C_BOARD_INFO("wm8731", 0x1b) },
+};
 static void corgi_poweroff(void)
 {
        if (!machine_is_corgi())
@@ -634,6 +639,7 @@ static void __init corgi_init(void)
        pxa_set_mci_info(&corgi_mci_platform_data);
        pxa_set_ficp_info(&corgi_ficp_platform_data);
        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(corgi_i2c_devices));
        platform_scoop_config = &corgi_pcmcia_config;
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 243e0802b5f4..63b10d9bb1d3 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -30,6 +30,7 @@
 #include <linux/apm-emulation.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pca953x.h>
+#include <linux/regulator/userspace-consumer.h>
 #include <media/soc_camera.h>
@@ -735,6 +736,7 @@ static struct pxa2xx_spi_chip em_x270_libertas_chip = {
        .rx_threshold   = 1,
        .tx_threshold   = 1,
        .timeout        = 1000,
+        .gpio_cs        = 14,
 };
 static unsigned long em_x270_libertas_pin_config[] = {
@@ -803,7 +805,6 @@ static int em_x270_libertas_teardown(struct spi_device *spi)
 struct libertas_spi_platform_data em_x270_libertas_pdata = {
        .use_dummy_writes       = 1,
-        .gpio_cs                = 14,
        .setup                  = em_x270_libertas_setup,
        .teardown               = em_x270_libertas_teardown,
 };
@@ -838,10 +839,14 @@ static void __init em_x270_init_spi(void)
 static inline void em_x270_init_spi(void) {}
 #endif
-#if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE)
+#if defined(CONFIG_SND_PXA2XX_LIB_AC97)
+static pxa2xx_audio_ops_t em_x270_ac97_info = {
+        .reset_gpio = 113,
+};
 static void __init em_x270_init_ac97(void)
 {
-        pxa_set_ac97_info(NULL);
+        pxa_set_ac97_info(&em_x270_ac97_info);
 }
 #else
 static inline void em_x270_init_ac97(void) {}
@@ -1038,6 +1043,52 @@ static void  __init em_x270_init_camera(void)
 static inline void em_x270_init_camera(void) {}
 #endif
+static struct regulator_bulk_data em_x270_gps_consumer_supply = {
+        .supply         = "vcc gps",
+};
+static struct regulator_userspace_consumer_data em_x270_gps_consumer_data = {
+        .name           = "vcc gps",
+        .num_supplies   = 1,
+        .supplies       = &em_x270_gps_consumer_supply,
+};
+static struct platform_device em_x270_gps_userspace_consumer = {
+        .name           = "reg-userspace-consumer",
+        .id             = 0,
+        .dev            = {
+                .platform_data = &em_x270_gps_consumer_data,
+        },
+};
+static struct regulator_bulk_data em_x270_gprs_consumer_supply = {
+        .supply         = "vcc gprs",
+};
+static struct regulator_userspace_consumer_data em_x270_gprs_consumer_data = {
+        .name           = "vcc gprs",
+        .num_supplies   = 1,
+        .supplies       = &em_x270_gprs_consumer_supply
+};
+static struct platform_device em_x270_gprs_userspace_consumer = {
+        .name           = "reg-userspace-consumer",
+        .id             = 1,
+        .dev            = {
+                .platform_data = &em_x270_gprs_consumer_data,
+        }
+};
+static struct platform_device *em_x270_userspace_consumers[] = {
+        &em_x270_gps_userspace_consumer,
+        &em_x270_gprs_userspace_consumer,
+};
+static void __init em_x270_userspace_consumers_init(void)
+{
+        platform_add_devices(ARRAY_AND_SIZE(em_x270_userspace_consumers));
+}
 /* DA9030 related initializations */
 #define REGULATOR_CONSUMER(_name, _dev, _supply)                               \
        static struct regulator_consumer_supply _name##_consumers[] = { \
@@ -1047,11 +1098,11 @@ static inline void em_x270_init_camera(void) {}
                },                                                      \
        }
-REGULATOR_CONSUMER(ldo3, NULL, "vcc gps");
+REGULATOR_CONSUMER(ldo3, &em_x270_gps_userspace_consumer.dev, "vcc gps");
 REGULATOR_CONSUMER(ldo5, NULL, "vcc cam");
 REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio");
 REGULATOR_CONSUMER(ldo12, NULL, "vcc usb");
-REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs");
+REGULATOR_CONSUMER(ldo19, &em_x270_gprs_userspace_consumer.dev, "vcc gprs");
 #define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask)               \
        static struct regulator_init_data _ldo##_data = {               \
@@ -1062,6 +1113,7 @@ REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs");
                                .enabled = 0,                           \
                        },                                              \
                        .valid_ops_mask = _ops_mask,                    \
+                        .apply_uV = 1,                                  \
                },                                                      \
                .num_consumer_supplies = ARRAY_SIZE(_ldo##_consumers),  \
                .consumer_supplies = _ldo##_consumers,                  \
@@ -1240,6 +1292,7 @@ static void __init em_x270_init(void)
        em_x270_init_spi();
        em_x270_init_i2c();
        em_x270_init_camera();
+        em_x270_userspace_consumers_init();
 }
 MACHINE_START(EM_X270, "Compulab EM-X270")
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 7fff467e84fc..81359d574f88 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -30,6 +30,7 @@
 #include <linux/pwm_backlight.h>
 #include <linux/regulator/bq24022.h>
 #include <linux/regulator/machine.h>
+#include <linux/regulator/max1586.h>
 #include <linux/spi/ads7846.h>
 #include <linux/spi/spi.h>
 #include <linux/usb/gpio_vbus.h>
@@ -775,6 +776,45 @@ static struct platform_device strataflash = {
 };
 /*
+ * Maxim MAX1587A on PI2C
+ */
+static struct regulator_consumer_supply max1587a_consumer = {
+        .supply = "vcc_core",
+};
+static struct regulator_init_data max1587a_v3_info = {
+        .constraints = {
+                .name = "vcc_core range",
+                .min_uV =  900000,
+                .max_uV = 1705000,
+                .always_on = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies = 1,
+        .consumer_supplies     = &max1587a_consumer,
+};
+static struct max1586_subdev_data max1587a_subdev = {
+        .name = "vcc_core",
+        .id   = MAX1586_V3,
+        .platform_data = &max1587a_v3_info,
+};
+static struct max1586_platform_data max1587a_info = {
+        .num_subdevs = 1,
+        .subdevs     = &max1587a_subdev,
+        .v3_gain     = MAX1586_GAIN_R24_3k32, /* 730..1550 mV */
+};
+static struct i2c_board_info __initdata pi2c_board_info[] = {
+        {
+                I2C_BOARD_INFO("max1586", 0x14),
+                .platform_data = &max1587a_info,
+        },
+};
+/*
 * PCMCIA
 */
@@ -828,6 +868,7 @@ static void __init hx4700_init(void)
        pxa_set_ficp_info(&ficp_info);
        pxa27x_set_i2c_power_info(NULL);
        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(1, ARRAY_AND_SIZE(pi2c_board_info));
        pxa2xx_set_spi_info(2, &pxa_ssp2_master_info);
        spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info));
diff --git a/arch/arm/mach-pxa/include/mach/palmz72.h b/arch/arm/mach-pxa/include/mach/palmz72.h
index 5032307ebf7d..2806ef69ba5a 100644
--- a/arch/arm/mach-pxa/include/mach/palmz72.h
+++ b/arch/arm/mach-pxa/include/mach/palmz72.h
@@ -21,7 +21,7 @@
 /* SD/MMC */
 #define GPIO_NR_PALMZ72_SD_DETECT_N             14
 #define GPIO_NR_PALMZ72_SD_POWER_N              98
-#define GPIO_NR_PALMZ72_SD_RO 115
+#define GPIO_NR_PALMZ72_SD_RO                   115
 /* Touchscreen */
 #define GPIO_NR_PALMZ72_WM9712_IRQ              27
@@ -31,8 +31,7 @@
 /* USB */
 #define GPIO_NR_PALMZ72_USB_DETECT_N            15
-#define GPIO_NR_PALMZ72_USB_POWER               95
+#define GPIO_NR_PALMZ72_USB_PULLUP              95
-#define GPIO_NR_PALMZ72_USB_PULLUP              12
 /* LCD/Backlight */
 #define GPIO_NR_PALMZ72_BL_POWER                20
diff --git a/arch/arm/mach-pxa/include/mach/treo680.h b/arch/arm/mach-pxa/include/mach/treo680.h
new file mode 100644
index 000000000000..af443b24d99a
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/treo680.h
@@ -0,0 +1,49 @@
+/*
+ * GPIOs and interrupts for Palm Treo 680 smartphone
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef _INCLUDE_TREO680_H_
+#define _INCLUDE_TREO680_H_
+/* GPIOs */
+#define GPIO_NR_TREO680_POWER_DETECT    0
+#define GPIO_NR_TREO680_AMP_EN          27
+#define GPIO_NR_TREO680_KEYB_BL         24
+#define GPIO_NR_TREO680_VIBRATE_EN      44
+#define GPIO_NR_TREO680_GREEN_LED       20
+#define GPIO_NR_TREO680_RED_LED         79
+#define GPIO_NR_TREO680_SD_DETECT_N     113
+#define GPIO_NR_TREO680_SD_READONLY     33
+#define GPIO_NR_TREO680_EP_DETECT_N     116
+#define GPIO_NR_TREO680_SD_POWER        42
+#define GPIO_NR_TREO680_USB_DETECT      1
+#define GPIO_NR_TREO680_USB_PULLUP      114
+#define GPIO_NR_TREO680_GSM_POWER       40
+#define GPIO_NR_TREO680_GSM_RESET       87
+#define GPIO_NR_TREO680_GSM_WAKE        57
+#define GPIO_NR_TREO680_GSM_HOST_WAKE   14
+#define GPIO_NR_TREO680_GSM_TRIGGER     10
+#define GPIO_NR_TREO680_BT_EN           43
+#define GPIO_NR_TREO680_IR_EN           115
+#define GPIO_NR_TREO680_IR_TXD          47
+#define GPIO_NR_TREO680_BL_POWER        38
+#define GPIO_NR_TREO680_LCD_POWER       25
+/* Various addresses  */
+#define TREO680_PHYS_RAM_START  0xa0000000
+#define TREO680_PHYS_IO_START   0x40000000
+#define TREO680_STR_BASE        0xa2000000
+/* BACKLIGHT */
+#define TREO680_MAX_INTENSITY           254
+#define TREO680_DEFAULT_INTENSITY       160
+#define TREO680_LIMIT_MASK              0x7F
+#define TREO680_PRESCALER               63
+#define TREO680_PERIOD_NS               3500
+#endif
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 4dc8c2ec40a9..2d28132c725b 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -37,6 +37,7 @@
 #include <linux/wm97xx_batt.h>
 #include <linux/mtd/physmap.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/regulator/max1586.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -717,6 +718,38 @@ static struct wm97xx_batt_info mioa701_battery_data = {
 };
 /*
+ * Voltage regulation
+ */
+static struct regulator_consumer_supply max1586_consumers[] = {
+        {
+                .supply = "vcc_core",
+        }
+};
+static struct regulator_init_data max1586_v3_info = {
+        .constraints = {
+                .name = "vcc_core range",
+                .min_uV = 1000000,
+                .max_uV = 1705000,
+                .always_on = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(max1586_consumers),
+        .consumer_supplies = max1586_consumers,
+};
+static struct max1586_subdev_data max1586_subdevs[] = {
+        { .name = "vcc_core", .id = MAX1586_V3,
+          .platform_data = &max1586_v3_info },
+};
+static struct max1586_platform_data max1586_info = {
+        .subdevs = max1586_subdevs,
+        .num_subdevs = ARRAY_SIZE(max1586_subdevs),
+        .v3_gain = MAX1586_GAIN_NO_R24, /* 700..1475 mV */
+};
+/*
 * Camera interface
 */
 struct pxacamera_platform_data mioa701_pxacamera_platform_data = {
@@ -725,6 +758,13 @@ struct pxacamera_platform_data mioa701_pxacamera_platform_data = {
        .mclk_10khz = 5000,
 };
+static struct i2c_board_info __initdata mioa701_pi2c_devices[] = {
+        {
+                I2C_BOARD_INFO("max1586", 0x14),
+                .platform_data = &max1586_info,
+        },
+};
 static struct soc_camera_link iclink = {
        .bus_id = 0, /* Must match id in pxa27x_device_camera in device.c */
 };
@@ -825,7 +865,9 @@ static void __init mioa701_machine_init(void)
        platform_add_devices(devices, ARRAY_SIZE(devices));
        gsm_init();
+        i2c_register_board_info(1, ARRAY_AND_SIZE(mioa701_pi2c_devices));
        pxa_set_i2c_info(&i2c_pdata);
+        pxa27x_set_i2c_power_info(NULL);
        pxa_set_camera_info(&mioa701_pxacamera_platform_data);
        i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices));
 }
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index b88eb4dd2c84..c3645aa3fa3d 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -27,7 +27,9 @@
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
 #include <linux/gpio.h>
+#include <linux/wm97xx_batt.h>
 #include <linux/power_supply.h>
+#include <linux/usb/gpio_vbus.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -41,6 +43,8 @@
 #include <mach/irda.h>
 #include <mach/pxa27x_keypad.h>
 #include <mach/udc.h>
+#include <mach/palmasoc.h>
 #include <mach/pm.h>
 #include "generic.h"
@@ -66,6 +70,8 @@ static unsigned long palmz72_pin_config[] __initdata = {
        GPIO29_AC97_SDATA_IN_0,
        GPIO30_AC97_SDATA_OUT,
        GPIO31_AC97_SYNC,
+        GPIO89_AC97_SYSCLK,
+        GPIO113_AC97_nRESET,
        /* IrDA */
        GPIO49_GPIO,    /* ir disable */
@@ -77,8 +83,7 @@ static unsigned long palmz72_pin_config[] __initdata = {
        /* USB */
        GPIO15_GPIO,    /* usb detect */
-        GPIO12_GPIO,    /* usb pullup */
+        GPIO95_GPIO,    /* usb pullup */
-        GPIO95_GPIO,    /* usb power */
        /* Matrix keypad */
        GPIO100_KP_MKIN_0       | WAKEUP_ON_LEVEL_HIGH,
@@ -355,6 +360,22 @@ static struct platform_device palmz72_leds = {
 };
 /******************************************************************************
+ * UDC
+ ******************************************************************************/
+static struct gpio_vbus_mach_info palmz72_udc_info = {
+        .gpio_vbus              = GPIO_NR_PALMZ72_USB_DETECT_N,
+        .gpio_pullup            = GPIO_NR_PALMZ72_USB_PULLUP,
+};
+static struct platform_device palmz72_gpio_vbus = {
+        .name   = "gpio-vbus",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &palmz72_udc_info,
+        },
+};
+/******************************************************************************
 * Power supply
 ******************************************************************************/
 static int power_supply_init(struct device *dev)
@@ -422,6 +443,31 @@ static struct platform_device power_supply = {
 };
 /******************************************************************************
+ * WM97xx battery
+ ******************************************************************************/
+static struct wm97xx_batt_info wm97xx_batt_pdata = {
+        .batt_aux       = WM97XX_AUX_ID3,
+        .temp_aux       = WM97XX_AUX_ID2,
+        .charge_gpio    = -1,
+        .max_voltage    = PALMZ72_BAT_MAX_VOLTAGE,
+        .min_voltage    = PALMZ72_BAT_MIN_VOLTAGE,
+        .batt_mult      = 1000,
+        .batt_div       = 414,
+        .temp_mult      = 1,
+        .temp_div       = 1,
+        .batt_tech      = POWER_SUPPLY_TECHNOLOGY_LIPO,
+        .batt_name      = "main-batt",
+};
+/******************************************************************************
+ * aSoC audio
+ ******************************************************************************/
+static struct platform_device palmz72_asoc = {
+        .name = "palm27x-asoc",
+        .id   = -1,
+};
+/******************************************************************************
 * Framebuffer
 ******************************************************************************/
 static struct pxafb_mode_info palmz72_lcd_modes[] = {
@@ -527,17 +573,32 @@ device_initcall(palmz72_pm_init);
 static struct platform_device *devices[] __initdata = {
        &palmz72_backlight,
        &palmz72_leds,
+        &palmz72_asoc,
        &power_supply,
+        &palmz72_gpio_vbus,
 };
+/* setup udc GPIOs initial state */
+static void __init palmz72_udc_init(void)
+{
+        if (!gpio_request(GPIO_NR_PALMZ72_USB_PULLUP, "USB Pullup")) {
+                gpio_direction_output(GPIO_NR_PALMZ72_USB_PULLUP, 0);
+                gpio_free(GPIO_NR_PALMZ72_USB_PULLUP);
+        }
+}
 static void __init palmz72_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config));
        set_pxa_fb_info(&palmz72_lcd_screen);
        pxa_set_mci_info(&palmz72_mci_platform_data);
+        palmz72_udc_init();
        pxa_set_ac97_info(NULL);
        pxa_set_ficp_info(&palmz72_ficp_platform_data);
        pxa_set_keypad_info(&palmz72_keypad_platform_data);
+        wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index ac431ed10399..9352d4a34837 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -22,6 +22,7 @@
 #include <linux/delay.h>
 #include <linux/mtd/physmap.h>
 #include <linux/gpio.h>
+#include <linux/i2c.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/mtd/sharpsl.h>
@@ -486,6 +487,10 @@ static struct platform_device *devices[] __initdata = {
        &sharpsl_rom_device,
 };
+static struct i2c_board_info __initdata poodle_i2c_devices[] = {
+        { I2C_BOARD_INFO("wm8731", 0x1b) },
+};
 static void poodle_poweroff(void)
 {
        arm_machine_restart('h', NULL);
@@ -519,6 +524,7 @@ static void __init poodle_init(void)
        pxa_set_mci_info(&poodle_mci_platform_data);
        pxa_set_ficp_info(&poodle_ficp_platform_data);
        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(poodle_i2c_devices));
        poodle_init_spi();
 }
diff --git a/arch/arm/mach-pxa/treo680.c b/arch/arm/mach-pxa/treo680.c
new file mode 100644
index 000000000000..a06f19edebb3
--- /dev/null
+++ b/arch/arm/mach-pxa/treo680.c
@@ -0,0 +1,612 @@
+/*
+ * Hardware definitions for Palm Treo 680
+ *
+ * Author:     Tomas Cech <sleep_walker@suse.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * (find more info at www.hackndev.com)
+ *
+ */
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/pda_power.h>
+#include <linux/pwm_backlight.h>
+#include <linux/gpio.h>
+#include <linux/wm97xx_batt.h>
+#include <linux/power_supply.h>
+#include <linux/sysdev.h>
+#include <linux/w1-gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/pxa27x.h>
+#include <mach/pxa27x-udc.h>
+#include <mach/audio.h>
+#include <mach/treo680.h>
+#include <mach/mmc.h>
+#include <mach/pxafb.h>
+#include <mach/irda.h>
+#include <mach/pxa27x_keypad.h>
+#include <mach/udc.h>
+#include <mach/ohci.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/palmasoc.h>
+#include <mach/camera.h>
+#include <sound/pxa2xx-lib.h>
+#include "generic.h"
+#include "devices.h"
+/******************************************************************************
+ * Pin configuration
+ ******************************************************************************/
+static unsigned long treo680_pin_config[] __initdata = {
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+        GPIO33_GPIO,                            /* SD read only */
+        GPIO113_GPIO,                           /* SD detect */
+        /* AC97 */
+        GPIO28_AC97_BITCLK,
+        GPIO29_AC97_SDATA_IN_0,
+        GPIO30_AC97_SDATA_OUT,
+        GPIO31_AC97_SYNC,
+        GPIO89_AC97_SYSCLK,
+        GPIO95_AC97_nRESET,
+        /* IrDA */
+        GPIO46_FICP_RXD,
+        GPIO47_FICP_TXD,
+        /* PWM */
+        GPIO16_PWM0_OUT,
+        /* USB */
+        GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,       /* usb detect */
+        /* MATRIX KEYPAD */
+        GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
+        GPIO101_KP_MKIN_1,
+        GPIO102_KP_MKIN_2,
+        GPIO97_KP_MKIN_3,
+        GPIO98_KP_MKIN_4,
+        GPIO99_KP_MKIN_5,
+        GPIO91_KP_MKIN_6,
+        GPIO13_KP_MKIN_7,
+        GPIO103_KP_MKOUT_0 | MFP_LPM_DRIVE_HIGH,
+        GPIO104_KP_MKOUT_1,
+        GPIO105_KP_MKOUT_2,
+        GPIO106_KP_MKOUT_3,
+        GPIO107_KP_MKOUT_4,
+        GPIO108_KP_MKOUT_5,
+        GPIO96_KP_MKOUT_6,
+        GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH,        /* Hotsync button */
+        /* LCD */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+        /* Quick Capture Interface */
+        GPIO84_CIF_FV,
+        GPIO85_CIF_LV,
+        GPIO53_CIF_MCLK,
+        GPIO54_CIF_PCLK,
+        GPIO81_CIF_DD_0,
+        GPIO55_CIF_DD_1,
+        GPIO51_CIF_DD_2,
+        GPIO50_CIF_DD_3,
+        GPIO52_CIF_DD_4,
+        GPIO48_CIF_DD_5,
+        GPIO17_CIF_DD_6,
+        GPIO12_CIF_DD_7,
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+        /* GSM */
+        GPIO14_GPIO | WAKEUP_ON_EDGE_BOTH,      /* GSM host wake up */
+        GPIO34_FFUART_RXD,
+        GPIO35_FFUART_CTS,
+        GPIO39_FFUART_TXD,
+        GPIO41_FFUART_RTS,
+        /* MISC. */
+        GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH,       /* external power detect */
+        GPIO15_GPIO | WAKEUP_ON_EDGE_BOTH,      /* silent switch */
+        GPIO116_GPIO,                           /* headphone detect */
+        GPIO11_GPIO | WAKEUP_ON_EDGE_BOTH,      /* bluetooth host wake up */
+};
+/******************************************************************************
+ * SD/MMC card controller
+ ******************************************************************************/
+static int treo680_mci_init(struct device *dev,
+                irq_handler_t treo680_detect_int, void *data)
+{
+        int err = 0;
+        /* Setup an interrupt for detecting card insert/remove events */
+        err = gpio_request(GPIO_NR_TREO680_SD_DETECT_N, "SD IRQ");
+        if (err)
+                goto err;
+        err = gpio_direction_input(GPIO_NR_TREO680_SD_DETECT_N);
+        if (err)
+                goto err2;
+        err = request_irq(gpio_to_irq(GPIO_NR_TREO680_SD_DETECT_N),
+                        treo680_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM |
+                        IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
+                        "SD/MMC card detect", data);
+        if (err) {
+                dev_err(dev, "%s: cannot request SD/MMC card detect IRQ\n",
+                             __func__);
+                goto err2;
+        }
+        err = gpio_request(GPIO_NR_TREO680_SD_POWER, "SD_POWER");
+        if (err)
+                goto err3;
+        err = gpio_direction_output(GPIO_NR_TREO680_SD_POWER, 1);
+        if (err)
+                goto err4;
+        err = gpio_request(GPIO_NR_TREO680_SD_READONLY, "SD_READONLY");
+        if (err)
+                goto err4;
+        err = gpio_direction_input(GPIO_NR_TREO680_SD_READONLY);
+        if (err)
+                goto err5;
+        return 0;
+err5:
+        gpio_free(GPIO_NR_TREO680_SD_READONLY);
+err4:
+        gpio_free(GPIO_NR_TREO680_SD_POWER);
+err3:
+        free_irq(gpio_to_irq(GPIO_NR_TREO680_SD_DETECT_N), data);
+err2:
+        gpio_free(GPIO_NR_TREO680_SD_DETECT_N);
+err:
+        return err;
+}
+static void treo680_mci_exit(struct device *dev, void *data)
+{
+        gpio_free(GPIO_NR_TREO680_SD_READONLY);
+        gpio_free(GPIO_NR_TREO680_SD_POWER);
+        free_irq(gpio_to_irq(GPIO_NR_TREO680_SD_DETECT_N), data);
+        gpio_free(GPIO_NR_TREO680_SD_DETECT_N);
+}
+static void treo680_mci_power(struct device *dev, unsigned int vdd)
+{
+        struct pxamci_platform_data *p_d = dev->platform_data;
+        gpio_set_value(GPIO_NR_TREO680_SD_POWER, p_d->ocr_mask & (1 << vdd));
+}
+static int treo680_mci_get_ro(struct device *dev)
+{
+        return gpio_get_value(GPIO_NR_TREO680_SD_READONLY);
+}
+static struct pxamci_platform_data treo680_mci_platform_data = {
+        .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34,
+        .setpower       = treo680_mci_power,
+        .get_ro         = treo680_mci_get_ro,
+        .init           = treo680_mci_init,
+        .exit           = treo680_mci_exit,
+};
+/******************************************************************************
+ * GPIO keyboard
+ ******************************************************************************/
+static unsigned int treo680_matrix_keys[] = {
+        KEY(0, 0, KEY_F8),              /* Red/Off/Power */
+        KEY(0, 1, KEY_LEFT),
+        KEY(0, 2, KEY_LEFTCTRL),        /* Alternate */
+        KEY(0, 3, KEY_L),
+        KEY(0, 4, KEY_A),
+        KEY(0, 5, KEY_Q),
+        KEY(0, 6, KEY_P),
+        KEY(1, 0, KEY_RIGHTCTRL),       /* Menu */
+        KEY(1, 1, KEY_RIGHT),
+        KEY(1, 2, KEY_LEFTSHIFT),       /* Left shift */
+        KEY(1, 3, KEY_Z),
+        KEY(1, 4, KEY_S),
+        KEY(1, 5, KEY_W),
+        KEY(2, 0, KEY_F1),              /* Phone */
+        KEY(2, 1, KEY_UP),
+        KEY(2, 2, KEY_0),
+        KEY(2, 3, KEY_X),
+        KEY(2, 4, KEY_D),
+        KEY(2, 5, KEY_E),
+        KEY(3, 0, KEY_F10),             /* Calendar */
+        KEY(3, 1, KEY_DOWN),
+        KEY(3, 2, KEY_SPACE),
+        KEY(3, 3, KEY_C),
+        KEY(3, 4, KEY_F),
+        KEY(3, 5, KEY_R),
+        KEY(4, 0, KEY_F12),             /* Mail */
+        KEY(4, 1, KEY_KPENTER),
+        KEY(4, 2, KEY_RIGHTALT),        /* Alt */
+        KEY(4, 3, KEY_V),
+        KEY(4, 4, KEY_G),
+        KEY(4, 5, KEY_T),
+        KEY(5, 0, KEY_F9),              /* Home */
+        KEY(5, 1, KEY_PAGEUP),          /* Side up */
+        KEY(5, 2, KEY_DOT),
+        KEY(5, 3, KEY_B),
+        KEY(5, 4, KEY_H),
+        KEY(5, 5, KEY_Y),
+        KEY(6, 0, KEY_TAB),             /* Side Activate */
+        KEY(6, 1, KEY_PAGEDOWN),        /* Side down */
+        KEY(6, 2, KEY_ENTER),
+        KEY(6, 3, KEY_N),
+        KEY(6, 4, KEY_J),
+        KEY(6, 5, KEY_U),
+        KEY(7, 0, KEY_F6),              /* Green/Call */
+        KEY(7, 1, KEY_O),
+        KEY(7, 2, KEY_BACKSPACE),
+        KEY(7, 3, KEY_M),
+        KEY(7, 4, KEY_K),
+        KEY(7, 5, KEY_I),
+};
+static struct pxa27x_keypad_platform_data treo680_keypad_platform_data = {
+        .matrix_key_rows        = 8,
+        .matrix_key_cols        = 7,
+        .matrix_key_map         = treo680_matrix_keys,
+        .matrix_key_map_size    = ARRAY_SIZE(treo680_matrix_keys),
+        .direct_key_map         = { KEY_CONNECT },
+        .direct_key_num         = 1,
+        .debounce_interval      = 30,
+};
+/******************************************************************************
+ * aSoC audio
+ ******************************************************************************/
+static pxa2xx_audio_ops_t treo680_ac97_pdata = {
+        .reset_gpio     = 95,
+};
+/******************************************************************************
+ * Backlight
+ ******************************************************************************/
+static int treo680_backlight_init(struct device *dev)
+{
+        int ret;
+        ret = gpio_request(GPIO_NR_TREO680_BL_POWER, "BL POWER");
+        if (ret)
+                goto err;
+        ret = gpio_direction_output(GPIO_NR_TREO680_BL_POWER, 0);
+        if (ret)
+                goto err2;
+        ret = gpio_request(GPIO_NR_TREO680_LCD_POWER, "LCD POWER");
+        if (ret)
+                goto err2;
+        ret = gpio_direction_output(GPIO_NR_TREO680_LCD_POWER, 0);
+        if (ret)
+                goto err3;
+        return 0;
+err3:
+        gpio_free(GPIO_NR_TREO680_LCD_POWER);
+err2:
+        gpio_free(GPIO_NR_TREO680_BL_POWER);
+err:
+        return ret;
+}
+static int treo680_backlight_notify(int brightness)
+{
+        gpio_set_value(GPIO_NR_TREO680_BL_POWER, brightness);
+        return TREO680_MAX_INTENSITY - brightness;
+};
+static void treo680_backlight_exit(struct device *dev)
+{
+        gpio_free(GPIO_NR_TREO680_BL_POWER);
+        gpio_free(GPIO_NR_TREO680_LCD_POWER);
+}
+static struct platform_pwm_backlight_data treo680_backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = TREO680_MAX_INTENSITY,
+        .dft_brightness = TREO680_DEFAULT_INTENSITY,
+        .pwm_period_ns  = TREO680_PERIOD_NS,
+        .init           = treo680_backlight_init,
+        .notify         = treo680_backlight_notify,
+        .exit           = treo680_backlight_exit,
+};
+static struct platform_device treo680_backlight = {
+        .name   = "pwm-backlight",
+        .dev    = {
+                .parent         = &pxa27x_device_pwm0.dev,
+                .platform_data  = &treo680_backlight_data,
+        },
+};
+/******************************************************************************
+ * IrDA
+ ******************************************************************************/
+static void treo680_transceiver_mode(struct device *dev, int mode)
+{
+        gpio_set_value(GPIO_NR_TREO680_IR_EN, mode & IR_OFF);
+        pxa2xx_transceiver_mode(dev, mode);
+}
+static int treo680_irda_startup(struct device *dev)
+{
+        int err;
+        err = gpio_request(GPIO_NR_TREO680_IR_EN, "Ir port disable");
+        if (err)
+                goto err1;
+        err = gpio_direction_output(GPIO_NR_TREO680_IR_EN, 1);
+        if (err)
+                goto err2;
+        return 0;
+err2:
+        dev_err(dev, "treo680_irda: cannot change IR gpio direction\n");
+        gpio_free(GPIO_NR_TREO680_IR_EN);
+err1:
+        dev_err(dev, "treo680_irda: cannot allocate IR gpio\n");
+        return err;
+}
+static void treo680_irda_shutdown(struct device *dev)
+{
+        gpio_free(GPIO_NR_TREO680_AMP_EN);
+}
+static struct pxaficp_platform_data treo680_ficp_info = {
+        .transceiver_cap  = IR_FIRMODE | IR_SIRMODE | IR_OFF,
+        .startup          = treo680_irda_startup,
+        .shutdown         = treo680_irda_shutdown,
+        .transceiver_mode = treo680_transceiver_mode,
+};
+/******************************************************************************
+ * UDC
+ ******************************************************************************/
+static struct pxa2xx_udc_mach_info treo680_udc_info __initdata = {
+        .gpio_vbus              = GPIO_NR_TREO680_USB_DETECT,
+        .gpio_vbus_inverted     = 1,
+        .gpio_pullup            = GPIO_NR_TREO680_USB_PULLUP,
+};
+/******************************************************************************
+ * USB host
+ ******************************************************************************/
+static struct pxaohci_platform_data treo680_ohci_info = {
+        .port_mode    = PMM_PERPORT_MODE,
+        .flags        = ENABLE_PORT1 | ENABLE_PORT3,
+        .power_budget = 0,
+};
+/******************************************************************************
+ * Power supply
+ ******************************************************************************/
+static int power_supply_init(struct device *dev)
+{
+        int ret;
+        ret = gpio_request(GPIO_NR_TREO680_POWER_DETECT, "CABLE_STATE_AC");
+        if (ret)
+                goto err1;
+        ret = gpio_direction_input(GPIO_NR_TREO680_POWER_DETECT);
+        if (ret)
+                goto err2;
+        return 0;
+err2:
+        gpio_free(GPIO_NR_TREO680_POWER_DETECT);
+err1:
+        return ret;
+}
+static int treo680_is_ac_online(void)
+{
+        return gpio_get_value(GPIO_NR_TREO680_POWER_DETECT);
+}
+static void power_supply_exit(struct device *dev)
+{
+        gpio_free(GPIO_NR_TREO680_POWER_DETECT);
+}
+static char *treo680_supplicants[] = {
+        "main-battery",
+};
+static struct pda_power_pdata power_supply_info = {
+        .init            = power_supply_init,
+        .is_ac_online    = treo680_is_ac_online,
+        .exit            = power_supply_exit,
+        .supplied_to     = treo680_supplicants,
+        .num_supplicants = ARRAY_SIZE(treo680_supplicants),
+};
+static struct platform_device power_supply = {
+        .name = "pda-power",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &power_supply_info,
+        },
+};
+/******************************************************************************
+ * Vibra and LEDs
+ ******************************************************************************/
+static struct gpio_led gpio_leds[] = {
+        {
+                .name                   = "treo680:vibra:vibra",
+                .default_trigger        = "none",
+                .gpio                   = GPIO_NR_TREO680_VIBRATE_EN,
+        },
+        {
+                .name                   = "treo680:green:led",
+                .default_trigger        = "mmc0",
+                .gpio                   = GPIO_NR_TREO680_GREEN_LED,
+        },
+        {
+                .name                   = "treo680:keybbl:keybbl",
+                .default_trigger        = "none",
+                .gpio                   = GPIO_NR_TREO680_KEYB_BL,
+        },
+};
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+static struct platform_device treo680_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_led_info,
+        }
+};
+/******************************************************************************
+ * Framebuffer
+ ******************************************************************************/
+/* TODO: add support for 324x324 */
+static struct pxafb_mode_info treo680_lcd_modes[] = {
+{
+        .pixclock               = 86538,
+        .xres                   = 320,
+        .yres                   = 320,
+        .bpp                    = 16,
+        .left_margin            = 20,
+        .right_margin           = 8,
+        .upper_margin           = 8,
+        .lower_margin           = 5,
+        .hsync_len              = 4,
+        .vsync_len              = 1,
+},
+};
+static struct pxafb_mach_info treo680_lcd_screen = {
+        .modes          = treo680_lcd_modes,
+        .num_modes      = ARRAY_SIZE(treo680_lcd_modes),
+        .lcd_conn       = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
+};
+/******************************************************************************
+ * Power management - standby
+ ******************************************************************************/
+static void __init treo680_pm_init(void)
+{
+        static u32 resume[] = {
+                0xe3a00101,     /* mov  r0,     #0x40000000 */
+                0xe380060f,     /* orr  r0, r0, #0x00f00000 */
+                0xe590f008,     /* ldr  pc, [r0, #0x08] */
+        };
+        /* this is where the bootloader jumps */
+        memcpy(phys_to_virt(TREO680_STR_BASE), resume, sizeof(resume));
+}
+/******************************************************************************
+ * Machine init
+ ******************************************************************************/
+static struct platform_device *devices[] __initdata = {
+        &treo680_backlight,
+        &treo680_leds,
+        &power_supply,
+};
+/* setup udc GPIOs initial state */
+static void __init treo680_udc_init(void)
+{
+        if (!gpio_request(GPIO_NR_TREO680_USB_PULLUP, "UDC Vbus")) {
+                gpio_direction_output(GPIO_NR_TREO680_USB_PULLUP, 1);
+                gpio_free(GPIO_NR_TREO680_USB_PULLUP);
+        }
+}
+static void __init treo680_init(void)
+{
+        treo680_pm_init();
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config));
+        pxa_set_keypad_info(&treo680_keypad_platform_data);
+        set_pxa_fb_info(&treo680_lcd_screen);
+        pxa_set_mci_info(&treo680_mci_platform_data);
+        treo680_udc_init();
+        pxa_set_udc_info(&treo680_udc_info);
+        pxa_set_ac97_info(&treo680_ac97_pdata);
+        pxa_set_ficp_info(&treo680_ficp_info);
+        pxa_set_ohci_info(&treo680_ohci_info);
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+MACHINE_START(TREO680, "Palm Treo 680")
+        .phys_io        = TREO680_PHYS_IO_START,
+        .io_pg_offst    = io_p2v(0x40000000),
+        .boot_params    = 0xa0000100,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa27x_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = treo680_init,
+MACHINE_END
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 1fe294d0bf9d..ede2a57240a3 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -27,6 +27,7 @@
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
+#include <asm/smp_twd.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c
index 6cd9377ddb82..50e25fc5f8ab 100644
--- a/arch/arm/mach-s3c2410/usb-simtec.c
+++ b/arch/arm/mach-s3c2410/usb-simtec.c
@@ -22,7 +22,6 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/device.h>
-#include <linux/gpio.h>
 #include <linux/io.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index 5df73cbf2b40..8cfeaec37306 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -84,5 +84,15 @@ config MACH_AT2440EVB
        help
          Say Y here if you are using the AT2440EVB development board
+config MACH_MINI2440
+        bool "MINI2440 development board"
+        select CPU_S3C2440
+        select EEPROM_AT24
+        select LEDS_TRIGGER_BACKLIGHT
+        select SND_S3C24XX_SOC_S3C24XX_UDA134X
+        help
+          Say Y here to select support for the MINI2440. Is a 10cm x 10cm board
+          available via various sources. It can come with a 3.5" or 7" touch LCD.
 endmenu
diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile
index 0b4440e79b90..bfadcf684a2a 100644
--- a/arch/arm/mach-s3c2440/Makefile
+++ b/arch/arm/mach-s3c2440/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_MACH_RX3715)	+= mach-rx3715.o
 obj-$(CONFIG_ARCH_S3C2440)      += mach-smdk2440.o
 obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
 obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
+obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
new file mode 100644
index 000000000000..ec71a6965786
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -0,0 +1,702 @@
+/* linux/arch/arm/mach-s3c2440/mach-mini2440.c
+ *
+ * Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com>
+ *      Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk>
+ *      and modifications by SBZ <sbz@spgui.org> and
+ *      Weibing <http://weibing.blogbus.com> and
+ *      Michel Pollet <buserror@gmail.com>
+ *
+ * For product information, visit http://code.google.com/p/mini2440/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/serial_core.h>
+#include <linux/dm9000.h>
+#include <linux/i2c/at24.h>
+#include <linux/platform_device.h>
+#include <linux/gpio_keys.h>
+#include <linux/i2c.h>
+#include <linux/mmc/host.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include <mach/fb.h>
+#include <asm/mach-types.h>
+#include <plat/regs-serial.h>
+#include <mach/regs-gpio.h>
+#include <mach/leds-gpio.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-lcd.h>
+#include <mach/irqs.h>
+#include <plat/nand.h>
+#include <plat/iic.h>
+#include <plat/mci.h>
+#include <plat/udc.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <sound/s3c24xx_uda134x.h>
+#define MACH_MINI2440_DM9K_BASE (S3C2410_CS4 + 0x300)
+static struct map_desc mini2440_iodesc[] __initdata = {
+        /* nothing to declare, move along */
+};
+#define UCON S3C2410_UCON_DEFAULT
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+static struct s3c2410_uartcfg mini2440_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+};
+/* USB device UDC support */
+static void mini2440_udc_pullup(enum s3c2410_udc_cmd_e cmd)
+{
+        pr_debug("udc: pullup(%d)\n", cmd);
+        switch (cmd) {
+                case S3C2410_UDC_P_ENABLE :
+                        s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
+                        break;
+                case S3C2410_UDC_P_DISABLE :
+                        s3c2410_gpio_setpin(S3C2410_GPC(5), 0);
+                        break;
+                case S3C2410_UDC_P_RESET :
+                        break;
+                default:
+                        break;
+        }
+}
+static struct s3c2410_udc_mach_info mini2440_udc_cfg __initdata = {
+        .udc_command            = mini2440_udc_pullup,
+};
+/* LCD timing and setup */
+/*
+ * This macro simplifies the table bellow
+ */
+#define _LCD_DECLARE(_clock,_xres,margin_left,margin_right,hsync, \
+                        _yres,margin_top,margin_bottom,vsync, refresh) \
+        .width = _xres, \
+        .xres = _xres, \
+        .height = _yres, \
+        .yres = _yres, \
+        .left_margin    = margin_left,  \
+        .right_margin   = margin_right, \
+        .upper_margin   = margin_top,   \
+        .lower_margin   = margin_bottom,        \
+        .hsync_len      = hsync,        \
+        .vsync_len      = vsync,        \
+        .pixclock       = ((_clock*100000000000LL) /    \
+                           ((refresh) * \
+                           (hsync + margin_left + _xres + margin_right) * \
+                           (vsync + margin_top + _yres + margin_bottom))), \
+        .bpp            = 16,\
+        .type           = (S3C2410_LCDCON1_TFT16BPP |\
+                           S3C2410_LCDCON1_TFT)
+struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = {
+        [0] = { /* mini2440 + 3.5" TFT + touchscreen */
+                _LCD_DECLARE(
+                        7,                      /* The 3.5 is quite fast */
+                        240, 21, 38, 6,         /* x timing */
+                        320, 4, 4, 2,           /* y timing */
+                        60),                    /* refresh rate */
+                .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
+                                   S3C2410_LCDCON5_INVVLINE |
+                                   S3C2410_LCDCON5_INVVFRAME |
+                                   S3C2410_LCDCON5_INVVDEN |
+                                   S3C2410_LCDCON5_PWREN),
+        },
+        [1] = { /* mini2440 + 7" TFT + touchscreen */
+                _LCD_DECLARE(
+                        10,                     /* the 7" runs slower */
+                        800, 40, 40, 48,        /* x timing */
+                        480, 29, 3, 3,          /* y timing */
+                        50),                    /* refresh rate */
+                .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
+                                   S3C2410_LCDCON5_INVVLINE |
+                                   S3C2410_LCDCON5_INVVFRAME |
+                                   S3C2410_LCDCON5_PWREN),
+        },
+        /* The VGA shield can outout at several resolutions. All share 
+         * the same timings, however, anything smaller than 1024x768
+         * will only be displayed in the top left corner of a 1024x768
+         * XGA output unless you add optional dip switches to the shield.
+         * Therefore timings for other resolutions have been ommited here.
+         */
+        [2] = {
+                _LCD_DECLARE(
+                        10,
+                        1024, 1, 2, 2,          /* y timing */
+                        768, 200, 16, 16,       /* x timing */
+                        24),    /* refresh rate, maximum stable,
+                                 tested with the FPGA shield */
+                .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
+                                   S3C2410_LCDCON5_HWSWP),
+        },
+};
+/* todo - put into gpio header */
+#define S3C2410_GPCCON_MASK(x)  (3 << ((x) * 2))
+#define S3C2410_GPDCON_MASK(x)  (3 << ((x) * 2))
+struct s3c2410fb_mach_info mini2440_fb_info __initdata = {
+        .displays        = &mini2440_lcd_cfg[0], /* not constant! see init */
+        .num_displays    = 1,
+        .default_display = 0,
+        /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
+         * and disable the pull down resistors on pins we are using for LCD
+         * data. */
+        .gpcup          = (0xf << 1) | (0x3f << 10),
+        .gpccon         = (S3C2410_GPC1_VCLK   | S3C2410_GPC2_VLINE |
+                           S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
+                           S3C2410_GPC10_VD2   | S3C2410_GPC11_VD3 |
+                           S3C2410_GPC12_VD4   | S3C2410_GPC13_VD5 |
+                           S3C2410_GPC14_VD6   | S3C2410_GPC15_VD7),
+        .gpccon_mask    = (S3C2410_GPCCON_MASK(1)  | S3C2410_GPCCON_MASK(2)  |
+                           S3C2410_GPCCON_MASK(3)  | S3C2410_GPCCON_MASK(4)  |
+                           S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
+                           S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
+                           S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
+        .gpdup          = (0x3f << 2) | (0x3f << 10),
+        .gpdcon         = (S3C2410_GPD2_VD10  | S3C2410_GPD3_VD11 |
+                           S3C2410_GPD4_VD12  | S3C2410_GPD5_VD13 |
+                           S3C2410_GPD6_VD14  | S3C2410_GPD7_VD15 |
+                           S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
+                           S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
+                           S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
+        .gpdcon_mask    = (S3C2410_GPDCON_MASK(2)  | S3C2410_GPDCON_MASK(3) |
+                           S3C2410_GPDCON_MASK(4)  | S3C2410_GPDCON_MASK(5) |
+                           S3C2410_GPDCON_MASK(6)  | S3C2410_GPDCON_MASK(7) |
+                           S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
+                           S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
+                           S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
+};
+/* MMC/SD  */
+static struct s3c24xx_mci_pdata mini2440_mmc_cfg __initdata = {
+   .gpio_detect   = S3C2410_GPG(8),
+   .gpio_wprotect = S3C2410_GPH(8),
+   .set_power     = NULL,
+   .ocr_avail     = MMC_VDD_32_33|MMC_VDD_33_34,
+};
+/* NAND Flash on MINI2440 board */
+static struct mtd_partition mini2440_default_nand_part[] __initdata = {
+        [0] = {
+                .name   = "u-boot",
+                .size   = SZ_256K,
+                .offset = 0,
+        },
+        [1] = {
+                .name   = "u-boot-env",
+                .size   = SZ_128K,
+                .offset = SZ_256K,
+        },
+        [2] = {
+                .name   = "kernel",
+                /* 5 megabytes, for a kernel with no modules
+                 * or a uImage with a ramdisk attached */
+                .size   = 0x00500000,
+                .offset = SZ_256K + SZ_128K,
+        },
+        [3] = {
+                .name   = "root",
+                .offset = SZ_256K + SZ_128K + 0x00500000,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+static struct s3c2410_nand_set mini2440_nand_sets[] __initdata = {
+        [0] = {
+                .name           = "nand",
+                .nr_chips       = 1,
+                .nr_partitions  = ARRAY_SIZE(mini2440_default_nand_part),
+                .partitions     = mini2440_default_nand_part,
+                .flash_bbt      = 1, /* we use u-boot to create a BBT */
+        },
+};
+static struct s3c2410_platform_nand mini2440_nand_info __initdata = {
+        .tacls          = 0,
+        .twrph0         = 25,
+        .twrph1         = 15,
+        .nr_sets        = ARRAY_SIZE(mini2440_nand_sets),
+        .sets           = mini2440_nand_sets,
+        .ignore_unset_ecc = 1,
+};
+/* DM9000AEP 10/100 ethernet controller */
+static struct resource mini2440_dm9k_resource[] __initdata = {
+        [0] = {
+                .start = MACH_MINI2440_DM9K_BASE,
+                .end   = MACH_MINI2440_DM9K_BASE + 3,
+                .flags = IORESOURCE_MEM
+        },
+        [1] = {
+                .start = MACH_MINI2440_DM9K_BASE + 4,
+                .end   = MACH_MINI2440_DM9K_BASE + 7,
+                .flags = IORESOURCE_MEM
+        },
+        [2] = {
+                .start = IRQ_EINT7,
+                .end   = IRQ_EINT7,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        }
+};
+/*
+ * The DM9000 has no eeprom, and it's MAC address is set by
+ * the bootloader before starting the kernel.
+ */
+static struct dm9000_plat_data mini2440_dm9k_pdata __initdata = {
+        .flags          = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
+};
+static struct platform_device mini2440_device_eth __initdata = {
+        .name           = "dm9000",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(mini2440_dm9k_resource),
+        .resource       = mini2440_dm9k_resource,
+        .dev            = {
+                .platform_data  = &mini2440_dm9k_pdata,
+        },
+};
+/*  CON5
+ *      +--+     /-----\
+ *      |  |    |       |
+ *      |  |    |  BAT  |
+ *      |  |     \_____/
+ *      |  |
+ *      |  |  +----+  +----+
+ *      |  |  | K5 |  | K1 |
+ *      |  |  +----+  +----+
+ *      |  |  +----+  +----+
+ *      |  |  | K4 |  | K2 |
+ *      |  |  +----+  +----+
+ *      |  |  +----+  +----+
+ *      |  |  | K6 |  | K3 |
+ *      |  |  +----+  +----+
+ *        .....
+ */
+static struct gpio_keys_button mini2440_buttons[] __initdata = {
+        {
+                .gpio           = S3C2410_GPG(0),               /* K1 */
+                .code           = KEY_F1,
+                .desc           = "Button 1",
+                .active_low     = 1,
+        },
+        {
+                .gpio           = S3C2410_GPG(3),               /* K2 */
+                .code           = KEY_F2,
+                .desc           = "Button 2",
+                .active_low     = 1,
+        },
+        {
+                .gpio           = S3C2410_GPG(5),               /* K3 */
+                .code           = KEY_F3,
+                .desc           = "Button 3",
+                .active_low     = 1,
+        },
+        {
+                .gpio           = S3C2410_GPG(6),               /* K4 */
+                .code           = KEY_POWER,
+                .desc           = "Power",
+                .active_low     = 1,
+        },
+        {
+                .gpio           = S3C2410_GPG(7),               /* K5 */
+                .code           = KEY_F5,
+                .desc           = "Button 5",
+                .active_low     = 1,
+        },
+#if 0
+        /* this pin is also known as TCLK1 and seems to already
+         * marked as "in use" somehow in the kernel -- possibly wrongly */
+        {
+                .gpio           = S3C2410_GPG(11),      /* K6 */
+                .code           = KEY_F6,
+                .desc           = "Button 6",
+                .active_low     = 1,
+        },
+#endif
+};
+static struct gpio_keys_platform_data mini2440_button_data __initdata = {
+        .buttons        = mini2440_buttons,
+        .nbuttons       = ARRAY_SIZE(mini2440_buttons),
+};
+static struct platform_device mini2440_button_device __initdata = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &mini2440_button_data,
+        }
+};
+/* LEDS */
+static struct s3c24xx_led_platdata mini2440_led1_pdata __initdata = {
+        .name           = "led1",
+        .gpio           = S3C2410_GPB(5),
+        .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
+        .def_trigger    = "heartbeat",
+};
+static struct s3c24xx_led_platdata mini2440_led2_pdata __initdata = {
+        .name           = "led2",
+        .gpio           = S3C2410_GPB(6),
+        .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
+        .def_trigger    = "nand-disk",
+};
+static struct s3c24xx_led_platdata mini2440_led3_pdata __initdata = {
+        .name           = "led3",
+        .gpio           = S3C2410_GPB(7),
+        .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
+        .def_trigger    = "mmc0",
+};
+static struct s3c24xx_led_platdata mini2440_led4_pdata __initdata = {
+        .name           = "led4",
+        .gpio           = S3C2410_GPB(8),
+        .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
+        .def_trigger    = "",
+};
+static struct s3c24xx_led_platdata mini2440_led_backlight_pdata __initdata = {
+        .name           = "backlight",
+        .gpio           = S3C2410_GPG(4),
+        .def_trigger    = "backlight",
+};
+static struct platform_device mini2440_led1 __initdata = {
+        .name           = "s3c24xx_led",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &mini2440_led1_pdata,
+        },
+};
+static struct platform_device mini2440_led2 __initdata = {
+        .name           = "s3c24xx_led",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &mini2440_led2_pdata,
+        },
+};
+static struct platform_device mini2440_led3 __initdata = {
+        .name           = "s3c24xx_led",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &mini2440_led3_pdata,
+        },
+};
+static struct platform_device mini2440_led4 __initdata = {
+        .name           = "s3c24xx_led",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &mini2440_led4_pdata,
+        },
+};
+static struct platform_device mini2440_led_backlight __initdata = {
+        .name           = "s3c24xx_led",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &mini2440_led_backlight_pdata,
+        },
+};
+/* AUDIO */
+static struct s3c24xx_uda134x_platform_data mini2440_audio_pins __initdata = {
+        .l3_clk = S3C2410_GPB(4),
+        .l3_mode = S3C2410_GPB(2),
+        .l3_data = S3C2410_GPB(3),
+        .model = UDA134X_UDA1341
+};
+static struct platform_device mini2440_audio __initdata = {
+        .name           = "s3c24xx_uda134x",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &mini2440_audio_pins,
+        },
+};
+/*
+ * I2C devices
+ */
+static struct at24_platform_data at24c08 = {
+        .byte_len       = SZ_8K / 8,
+        .page_size      = 16,
+};
+static struct i2c_board_info mini2440_i2c_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("24c08", 0x50),
+                .platform_data = &at24c08,
+        },
+};
+static struct platform_device *mini2440_devices[] __initdata = {
+        &s3c_device_usb,
+        &s3c_device_wdt,
+/*      &s3c_device_adc,*/ /* ADC doesn't like living with touchscreen ! */
+        &s3c_device_i2c0,
+        &s3c_device_rtc,
+        &s3c_device_usbgadget,
+        &mini2440_device_eth,
+        &mini2440_led1,
+        &mini2440_led2,
+        &mini2440_led3,
+        &mini2440_led4,
+        &mini2440_button_device,
+        &s3c_device_nand,
+        &s3c_device_sdi,
+        &s3c_device_iis,
+        &mini2440_audio,
+/*      &s3c_device_timer[0],*/ /* buzzer pwm, no API for it */
+        /* remaining devices are optional */
+};
+static void __init mini2440_map_io(void)
+{
+        s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
+        s3c_device_nand.dev.platform_data = &mini2440_nand_info;
+        s3c_device_sdi.dev.platform_data = &mini2440_mmc_cfg;
+}
+/*
+ * mini2440_features string
+ *
+ * t = Touchscreen present
+ * b = backlight control
+ * c = camera [TODO]
+ * 0-9 LCD configuration
+ *
+ */
+static char mini2440_features_str[12] __initdata = "0tb";
+static int __init mini2440_features_setup(char *str)
+{
+        if (str)
+                strlcpy(mini2440_features_str, str, sizeof(mini2440_features_str));
+        return 1;
+}
+__setup("mini2440=", mini2440_features_setup);
+#define FEATURE_SCREEN (1 << 0)
+#define FEATURE_BACKLIGHT (1 << 1)
+#define FEATURE_TOUCH (1 << 2)
+#define FEATURE_CAMERA (1 << 3)
+struct mini2440_features_t {
+        int count;
+        int done;
+        int lcd_index;
+        struct platform_device *optional[8];
+};
+static void mini2440_parse_features(
+                struct mini2440_features_t * features,
+                const char * features_str )
+{
+        const char * fp = features_str;
+        features->count = 0;
+        features->done = 0;
+        features->lcd_index = -1;
+        while (*fp) {
+                char f = *fp++;
+                switch (f) {
+                case '0'...'9': /* tft screen */
+                        if (features->done & FEATURE_SCREEN) {
+                                printk(KERN_INFO "MINI2440: '%c' ignored, "
+                                        "screen type already set\n", f);
+                        } else {
+                                int li = f - '0';
+                                if (li >= ARRAY_SIZE(mini2440_lcd_cfg))
+                                        printk(KERN_INFO "MINI2440: "
+                                                "'%c' out of range LCD mode\n", f);
+                                else {
+                                        features->optional[features->count++] =
+                                                        &s3c_device_lcd;
+                                        features->lcd_index = li;
+                                }
+                        }
+                        features->done |= FEATURE_SCREEN;
+                        break;
+                case 'b':
+                        if (features->done & FEATURE_BACKLIGHT)
+                                printk(KERN_INFO "MINI2440: '%c' ignored, "
+                                        "backlight already set\n", f);
+                        else {
+                                features->optional[features->count++] =
+                                                &mini2440_led_backlight;
+                        }
+                        features->done |= FEATURE_BACKLIGHT;
+                        break;
+                case 't':
+                        printk(KERN_INFO "MINI2440: '%c' ignored, "
+                                "touchscreen not compiled in\n", f);
+                        break;
+                case 'c':
+                        if (features->done & FEATURE_CAMERA)
+                                printk(KERN_INFO "MINI2440: '%c' ignored, "
+                                        "camera already registered\n", f);
+                        else
+                                features->optional[features->count++] =
+                                        &s3c_device_camif;
+                        features->done |= FEATURE_CAMERA;
+                        break;
+                }
+        }
+}
+static void __init mini2440_init(void)
+{
+        struct mini2440_features_t features = { 0 };
+        int i;
+        printk(KERN_INFO "MINI2440: Option string mini2440=%s\n",
+                        mini2440_features_str);
+        /* Parse the feature string */
+        mini2440_parse_features(&features, mini2440_features_str);
+        /* turn LCD on */
+        s3c2410_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND);
+        /* Turn the backlight early on */
+        s3c2410_gpio_setpin(S3C2410_GPG(4), 1);
+        s3c2410_gpio_cfgpin(S3C2410_GPG(4), S3C2410_GPIO_OUTPUT);
+        /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */
+        s3c2410_gpio_pullup(S3C2410_GPB(1), 0);
+        s3c2410_gpio_setpin(S3C2410_GPB(1), 0);
+        s3c2410_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT);
+        /* Make sure the D+ pullup pin is output */
+        s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
+        /* mark the key as input, without pullups (there is one on the board) */
+        for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) {
+                s3c2410_gpio_pullup(mini2440_buttons[i].gpio, 0);
+                s3c2410_gpio_cfgpin(mini2440_buttons[i].gpio,
+                                        S3C2410_GPIO_INPUT);
+        }
+        if (features.lcd_index != -1) {
+                int li;
+                mini2440_fb_info.displays =
+                        &mini2440_lcd_cfg[features.lcd_index];
+                printk(KERN_INFO "MINI2440: LCD");
+                for (li = 0; li < ARRAY_SIZE(mini2440_lcd_cfg); li++)
+                        if (li == features.lcd_index)
+                                printk(" [%d:%dx%d]", li,
+                                        mini2440_lcd_cfg[li].width,
+                                        mini2440_lcd_cfg[li].height);
+                        else
+                                printk(" %d:%dx%d", li,
+                                        mini2440_lcd_cfg[li].width,
+                                        mini2440_lcd_cfg[li].height);
+                printk("\n");
+                s3c24xx_fb_set_platdata(&mini2440_fb_info);
+        }
+        s3c24xx_udc_set_platdata(&mini2440_udc_cfg);
+        s3c_i2c0_set_platdata(NULL);
+        i2c_register_board_info(0, mini2440_i2c_devs,
+                                ARRAY_SIZE(mini2440_i2c_devs));
+        platform_add_devices(mini2440_devices, ARRAY_SIZE(mini2440_devices));
+        if (features.count)     /* the optional features */
+                platform_add_devices(features.optional, features.count);
+}
+MACHINE_START(MINI2440, "MINI2440")
+        /* Maintainer: Michel Pollet <buserror@gmail.com> */
+        .phys_io        = S3C2410_PA_UART,
+        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .map_io         = mini2440_map_io,
+        .init_machine   = mini2440_init,
+        .init_irq       = s3c24xx_init_irq,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2442/Kconfig b/arch/arm/mach-s3c2442/Kconfig
index b289d198020e..103e913f2258 100644
--- a/arch/arm/mach-s3c2442/Kconfig
+++ b/arch/arm/mach-s3c2442/Kconfig
@@ -24,6 +24,18 @@ config SMDK2440_CPU2442
        depends on ARCH_S3C2440
        select CPU_S3C2442
+config MACH_NEO1973_GTA02
+        bool "Openmoko GTA02 / Freerunner phone"
+        select CPU_S3C2442
+        select MFD_PCF50633
+        select PCF50633_GPIO
+        select I2C
+        select POWER_SUPPLY
+        select MACH_NEO1973
+        select S3C2410_PWM
+        help
+           Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
 endmenu
diff --git a/arch/arm/mach-s3c2442/Makefile b/arch/arm/mach-s3c2442/Makefile
index 2a909c6c5798..2a19113a5769 100644
--- a/arch/arm/mach-s3c2442/Makefile
+++ b/arch/arm/mach-s3c2442/Makefile
@@ -12,5 +12,7 @@ obj-				:=
 obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
 obj-$(CONFIG_CPU_S3C2442)       += clock.o
+obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o
 # Machine support
diff --git a/arch/arm/mach-s3c2442/include/mach/gta02.h b/arch/arm/mach-s3c2442/include/mach/gta02.h
new file mode 100644
index 000000000000..953331d8d56a
--- /dev/null
+++ b/arch/arm/mach-s3c2442/include/mach/gta02.h
@@ -0,0 +1,84 @@
+#ifndef _GTA02_H
+#define _GTA02_H
+#include <mach/regs-gpio.h>
+/* Different hardware revisions, passed in ATAG_REVISION by u-boot */
+#define GTA02v1_SYSTEM_REV      0x00000310
+#define GTA02v2_SYSTEM_REV      0x00000320
+#define GTA02v3_SYSTEM_REV      0x00000330
+#define GTA02v4_SYSTEM_REV      0x00000340
+#define GTA02v5_SYSTEM_REV      0x00000350
+/* since A7 is basically same as A6, we use A6 PCB ID */
+#define GTA02v6_SYSTEM_REV      0x00000360
+#define GTA02_GPIO_n3DL_GSM     S3C2410_GPA(13) /* v1 + v2 + v3 only */
+#define GTA02_GPIO_PWR_LED1     S3C2410_GPB(0)
+#define GTA02_GPIO_PWR_LED2     S3C2410_GPB(1)
+#define GTA02_GPIO_AUX_LED      S3C2410_GPB(2)
+#define GTA02_GPIO_VIBRATOR_ON  S3C2410_GPB(3)
+#define GTA02_GPIO_MODEM_RST    S3C2410_GPB(5)
+#define GTA02_GPIO_BT_EN        S3C2410_GPB(6)
+#define GTA02_GPIO_MODEM_ON     S3C2410_GPB(7)
+#define GTA02_GPIO_EXTINT8      S3C2410_GPB(8)
+#define GTA02_GPIO_USB_PULLUP   S3C2410_GPB(9)
+#define GTA02_GPIO_PIO5         S3C2410_GPC(5)  /* v3 + v4 only */
+#define GTA02v3_GPIO_nG1_CS     S3C2410_GPD(12) /* v3 + v4 only */
+#define GTA02v3_GPIO_nG2_CS     S3C2410_GPD(13) /* v3 + v4 only */
+#define GTA02v5_GPIO_HDQ        S3C2410_GPD(14)   /* v5 + */
+#define GTA02_GPIO_nG1_INT      S3C2410_GPF(0)
+#define GTA02_GPIO_IO1          S3C2410_GPF(1)
+#define GTA02_GPIO_PIO_2        S3C2410_GPF(2)  /* v2 + v3 + v4 only */
+#define GTA02_GPIO_JACK_INSERT  S3C2410_GPF(4)
+#define GTA02_GPIO_WLAN_GPIO1   S3C2410_GPF(5)  /* v2 + v3 + v4 only */
+#define GTA02_GPIO_AUX_KEY      S3C2410_GPF(6)
+#define GTA02_GPIO_HOLD_KEY     S3C2410_GPF(7)
+#define GTA02_GPIO_3D_IRQ       S3C2410_GPG(4)
+#define GTA02v2_GPIO_nG2_INT    S3C2410_GPG(8)  /* v2 + v3 + v4 only */
+#define GTA02v3_GPIO_nUSB_OC    S3C2410_GPG(9)  /* v3 + v4 only */
+#define GTA02v3_GPIO_nUSB_FLT   S3C2410_GPG(10) /* v3 + v4 only */
+#define GTA02v3_GPIO_nGSM_OC    S3C2410_GPG(11) /* v3 + v4 only */
+#define GTA02_GPIO_AMP_SHUT     S3C2440_GPJ1    /* v2 + v3 + v4 only */
+#define GTA02v1_GPIO_WLAN_GPIO10        S3C2440_GPJ2
+#define GTA02_GPIO_HP_IN        S3C2440_GPJ2    /* v2 + v3 + v4 only */
+#define GTA02_GPIO_INT0         S3C2440_GPJ3    /* v2 + v3 + v4 only */
+#define GTA02_GPIO_nGSM_EN      S3C2440_GPJ4
+#define GTA02_GPIO_3D_RESET     S3C2440_GPJ5
+#define GTA02_GPIO_nDL_GSM      S3C2440_GPJ6    /* v4 + v5 only */
+#define GTA02_GPIO_WLAN_GPIO0   S3C2440_GPJ7
+#define GTA02v1_GPIO_BAT_ID     S3C2440_GPJ8
+#define GTA02_GPIO_KEEPACT      S3C2440_GPJ8
+#define GTA02v1_GPIO_HP_IN      S3C2440_GPJ10
+#define GTA02_CHIP_PWD          S3C2440_GPJ11   /* v2 + v3 + v4 only */
+#define GTA02_GPIO_nWLAN_RESET  S3C2440_GPJ12   /* v2 + v3 + v4 only */
+#define GTA02_IRQ_GSENSOR_1     IRQ_EINT0
+#define GTA02_IRQ_MODEM         IRQ_EINT1
+#define GTA02_IRQ_PIO_2         IRQ_EINT2       /* v2 + v3 + v4 only */
+#define GTA02_IRQ_nJACK_INSERT  IRQ_EINT4
+#define GTA02_IRQ_WLAN_GPIO1    IRQ_EINT5
+#define GTA02_IRQ_AUX           IRQ_EINT6
+#define GTA02_IRQ_nHOLD         IRQ_EINT7
+#define GTA02_IRQ_PCF50633      IRQ_EINT9
+#define GTA02_IRQ_3D            IRQ_EINT12
+#define GTA02_IRQ_GSENSOR_2     IRQ_EINT16      /* v2 + v3 + v4 only */
+#define GTA02v3_IRQ_nUSB_OC     IRQ_EINT17      /* v3 + v4 only */
+#define GTA02v3_IRQ_nUSB_FLT    IRQ_EINT18      /* v3 + v4 only */
+#define GTA02v3_IRQ_nGSM_OC     IRQ_EINT19      /* v3 + v4 only */
+/* returns 00 000 on GTA02 A5 and earlier, A6 returns 01 001 */
+#define GTA02_PCB_ID1_0         S3C2410_GPC(13)
+#define GTA02_PCB_ID1_1         S3C2410_GPC(15)
+#define GTA02_PCB_ID1_2         S3C2410_GPD(0)
+#define GTA02_PCB_ID2_0         S3C2410_GPD(3)
+#define GTA02_PCB_ID2_1         S3C2410_GPD(4)
+int gta02_get_pcb_revision(void);
+#endif /* _GTA02_H */
diff --git a/arch/arm/mach-s3c2442/mach-gta02.c b/arch/arm/mach-s3c2442/mach-gta02.c
new file mode 100644
index 000000000000..0fb385bd9cd9
--- /dev/null
+++ b/arch/arm/mach-s3c2442/mach-gta02.c
@@ -0,0 +1,645 @@
+/*
+ * linux/arch/arm/mach-s3c2442/mach-gta02.c
+ *
+ * S3C2442 Machine Support for Openmoko GTA02 / FreeRunner.
+ *
+ * Copyright (C) 2006-2009 by Openmoko, Inc.
+ * Authors: Harald Welte <laforge@openmoko.org>
+ *          Andy Green <andy@openmoko.org>
+ *          Werner Almesberger <werner@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/delay.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/workqueue.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/spi/spi.h>
+#include <linux/mmc/host.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/backlight.h>
+#include <linux/regulator/machine.h>
+#include <linux/mfd/pcf50633/core.h>
+#include <linux/mfd/pcf50633/mbc.h>
+#include <linux/mfd/pcf50633/adc.h>
+#include <linux/mfd/pcf50633/gpio.h>
+#include <linux/mfd/pcf50633/pmic.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-gpioj.h>
+#include <mach/fb.h>
+#include <mach/spi.h>
+#include <mach/spi-gpio.h>
+#include <plat/usb-control.h>
+#include <mach/regs-mem.h>
+#include <mach/hardware.h>
+#include <mach/gta02.h>
+#include <plat/regs-serial.h>
+#include <plat/nand.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/udc.h>
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
+static struct pcf50633 *gta02_pcf;
+/*
+ * This gets called every 1ms when we paniced.
+ */
+static long gta02_panic_blink(long count)
+{
+        long delay = 0;
+        static long last_blink;
+        static char led;
+        /* Fast blink: 200ms period. */
+        if (count - last_blink < 100)
+                return 0;
+        led ^= 1;
+        gpio_direction_output(GTA02_GPIO_AUX_LED, led);
+        last_blink = count;
+        return delay;
+}
+static struct map_desc gta02_iodesc[] __initdata = {
+        {
+                .virtual        = 0xe0000000,
+                .pfn            = __phys_to_pfn(S3C2410_CS3 + 0x01000000),
+                .length         = SZ_1M,
+                .type           = MT_DEVICE
+        },
+};
+#define UCON (S3C2410_UCON_DEFAULT | S3C2443_UCON_RXERR_IRQEN)
+#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
+#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
+static struct s3c2410_uartcfg gta02_uartcfgs[] = {
+        [0] = {
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = UCON,
+                .ulcon          = ULCON,
+                .ufcon          = UFCON,
+        },
+        [1] = {
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = UCON,
+                .ulcon          = ULCON,
+                .ufcon          = UFCON,
+        },
+        [2] = {
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = UCON,
+                .ulcon          = ULCON,
+                .ufcon          = UFCON,
+        },
+};
+#ifdef CONFIG_CHARGER_PCF50633
+/*
+ * On GTA02 the 1A charger features a 48K resistor to 0V on the ID pin.
+ * We use this to recognize that we can pull 1A from the USB socket.
+ *
+ * These constants are the measured pcf50633 ADC levels with the 1A
+ * charger / 48K resistor, and with no pulldown resistor.
+ */
+#define ADC_NOM_CHG_DETECT_1A 6
+#define ADC_NOM_CHG_DETECT_USB 43
+static void
+gta02_configure_pmu_for_charger(struct pcf50633 *pcf, void *unused, int res)
+{
+        int  ma;
+        /* Interpret charger type */
+        if (res < ((ADC_NOM_CHG_DETECT_USB + ADC_NOM_CHG_DETECT_1A) / 2)) {
+                /*
+                 * Sanity - stop GPO driving out now that we have a 1A charger
+                 * GPO controls USB Host power generation on GTA02
+                 */
+                pcf50633_gpio_set(pcf, PCF50633_GPO, 0);
+                ma = 1000;
+        } else
+                ma = 100;
+        pcf50633_mbc_usb_curlim_set(pcf, ma);
+}
+static struct delayed_work gta02_charger_work;
+static int gta02_usb_vbus_draw;
+static void gta02_charger_worker(struct work_struct *work)
+{
+        if (gta02_usb_vbus_draw) {
+                pcf50633_mbc_usb_curlim_set(gta02_pcf, gta02_usb_vbus_draw);
+                return;
+        }
+#ifdef CONFIG_PCF50633_ADC
+        pcf50633_adc_async_read(gta02_pcf,
+                                PCF50633_ADCC1_MUX_ADCIN1,
+                                PCF50633_ADCC1_AVERAGE_16,
+                                gta02_configure_pmu_for_charger,
+                                NULL);
+#else
+        /*
+         * If the PCF50633 ADC is disabled we fallback to a
+         * 100mA limit for safety.
+         */
+        pcf50633_mbc_usb_curlim_set(pcf, 100);
+#endif
+}
+#define GTA02_CHARGER_CONFIGURE_TIMEOUT ((3000 * HZ) / 1000)
+static void gta02_pmu_event_callback(struct pcf50633 *pcf, int irq)
+{
+        if (irq == PCF50633_IRQ_USBINS) {
+                schedule_delayed_work(&gta02_charger_work,
+                                      GTA02_CHARGER_CONFIGURE_TIMEOUT);
+                return;
+        }
+        if (irq == PCF50633_IRQ_USBREM) {
+                cancel_delayed_work_sync(&gta02_charger_work);
+                gta02_usb_vbus_draw = 0;
+        }
+}
+static void gta02_udc_vbus_draw(unsigned int ma)
+{
+        if (!gta02_pcf)
+                return;
+        gta02_usb_vbus_draw = ma;
+        schedule_delayed_work(&gta02_charger_work,
+                              GTA02_CHARGER_CONFIGURE_TIMEOUT);
+}
+#else /* !CONFIG_CHARGER_PCF50633 */
+#define gta02_pmu_event_callback        NULL
+#define gta02_udc_vbus_draw             NULL
+#endif
+/*
+ * This is called when pc50633 is probed, unfortunately quite late in the
+ * day since it is an I2C bus device. Here we can belatedly define some
+ * platform devices with the advantage that we can mark the pcf50633 as the
+ * parent. This makes them get suspended and resumed with their parent
+ * the pcf50633 still around.
+ */
+static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf);
+static char *gta02_batteries[] = {
+        "battery",
+};
+struct pcf50633_platform_data gta02_pcf_pdata = {
+        .resumers = {
+                [0] =   PCF50633_INT1_USBINS |
+                        PCF50633_INT1_USBREM |
+                        PCF50633_INT1_ALARM,
+                [1] =   PCF50633_INT2_ONKEYF,
+                [2] =   PCF50633_INT3_ONKEY1S,
+                [3] =   PCF50633_INT4_LOWSYS |
+                        PCF50633_INT4_LOWBAT |
+                        PCF50633_INT4_HIGHTMP,
+        },
+        .batteries = gta02_batteries,
+        .num_batteries = ARRAY_SIZE(gta02_batteries),
+        .reg_init_data = {
+                [PCF50633_REGULATOR_AUTO] = {
+                        .constraints = {
+                                .min_uV = 3300000,
+                                .max_uV = 3300000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .always_on = 1,
+                                .apply_uV = 1,
+                                .state_mem = {
+                                        .enabled = 1,
+                                },
+                        },
+                },
+                [PCF50633_REGULATOR_DOWN1] = {
+                        .constraints = {
+                                .min_uV = 1300000,
+                                .max_uV = 1600000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .always_on = 1,
+                                .apply_uV = 1,
+                        },
+                },
+                [PCF50633_REGULATOR_DOWN2] = {
+                        .constraints = {
+                                .min_uV = 1800000,
+                                .max_uV = 1800000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .apply_uV = 1,
+                                .always_on = 1,
+                                .state_mem = {
+                                        .enabled = 1,
+                                },
+                        },
+                },
+                [PCF50633_REGULATOR_HCLDO] = {
+                        .constraints = {
+                                .min_uV = 2000000,
+                                .max_uV = 3300000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                                .always_on = 1,
+                        },
+                },
+                [PCF50633_REGULATOR_LDO1] = {
+                        .constraints = {
+                                .min_uV = 3300000,
+                                .max_uV = 3300000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .apply_uV = 1,
+                                .state_mem = {
+                                        .enabled = 0,
+                                },
+                        },
+                },
+                [PCF50633_REGULATOR_LDO2] = {
+                        .constraints = {
+                                .min_uV = 3300000,
+                                .max_uV = 3300000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .apply_uV = 1,
+                        },
+                },
+                [PCF50633_REGULATOR_LDO3] = {
+                        .constraints = {
+                                .min_uV = 3000000,
+                                .max_uV = 3000000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .apply_uV = 1,
+                        },
+                },
+                [PCF50633_REGULATOR_LDO4] = {
+                        .constraints = {
+                                .min_uV = 3200000,
+                                .max_uV = 3200000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .apply_uV = 1,
+                        },
+                },
+                [PCF50633_REGULATOR_LDO5] = {
+                        .constraints = {
+                                .min_uV = 3000000,
+                                .max_uV = 3000000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .apply_uV = 1,
+                                .state_mem = {
+                                        .enabled = 1,
+                                },
+                        },
+                },
+                [PCF50633_REGULATOR_LDO6] = {
+                        .constraints = {
+                                .min_uV = 3000000,
+                                .max_uV = 3000000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                        },
+                },
+                [PCF50633_REGULATOR_MEMLDO] = {
+                        .constraints = {
+                                .min_uV = 1800000,
+                                .max_uV = 1800000,
+                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                                .state_mem = {
+                                        .enabled = 1,
+                                },
+                        },
+                },
+        },
+        .probe_done = gta02_pmu_attach_child_devices,
+        .mbc_event_callback = gta02_pmu_event_callback,
+};
+/* NOR Flash. */
+#define GTA02_FLASH_BASE        0x18000000 /* GCS3 */
+#define GTA02_FLASH_SIZE        0x200000 /* 2MBytes */
+static struct physmap_flash_data gta02_nor_flash_data = {
+        .width          = 2,
+};
+static struct resource gta02_nor_flash_resource = {
+        .start          = GTA02_FLASH_BASE,
+        .end            = GTA02_FLASH_BASE + GTA02_FLASH_SIZE - 1,
+        .flags          = IORESOURCE_MEM,
+};
+static struct platform_device gta02_nor_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &gta02_nor_flash_data,
+        },
+        .resource       = &gta02_nor_flash_resource,
+        .num_resources  = 1,
+};
+struct platform_device s3c24xx_pwm_device = {
+        .name           = "s3c24xx_pwm",
+        .num_resources  = 0,
+};
+static struct i2c_board_info gta02_i2c_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("pcf50633", 0x73),
+                .irq = GTA02_IRQ_PCF50633,
+                .platform_data = &gta02_pcf_pdata,
+        },
+        {
+                I2C_BOARD_INFO("wm8753", 0x1a),
+        },
+};
+static struct s3c2410_nand_set gta02_nand_sets[] = {
+        [0] = {
+                /*
+                 * This name is also hard-coded in the boot loaders, so
+                 * changing it would would require all users to upgrade
+                 * their boot loaders, some of which are stored in a NOR
+                 * that is considered to be immutable.
+                 */
+                .name           = "neo1973-nand",
+                .nr_chips       = 1,
+                .flash_bbt      = 1,
+        },
+};
+/*
+ * Choose a set of timings derived from S3C@2442B MCP54
+ * data sheet (K5D2G13ACM-D075 MCP Memory).
+ */
+static struct s3c2410_platform_nand gta02_nand_info = {
+        .tacls          = 0,
+        .twrph0         = 25,
+        .twrph1         = 15,
+        .nr_sets        = ARRAY_SIZE(gta02_nand_sets),
+        .sets           = gta02_nand_sets,
+};
+static void gta02_udc_command(enum s3c2410_udc_cmd_e cmd)
+{
+        switch (cmd) {
+        case S3C2410_UDC_P_ENABLE:
+                pr_debug("%s S3C2410_UDC_P_ENABLE\n", __func__);
+                gpio_direction_output(GTA02_GPIO_USB_PULLUP, 1);
+                break;
+        case S3C2410_UDC_P_DISABLE:
+                pr_debug("%s S3C2410_UDC_P_DISABLE\n", __func__);
+                gpio_direction_output(GTA02_GPIO_USB_PULLUP, 0);
+                break;
+        case S3C2410_UDC_P_RESET:
+                pr_debug("%s S3C2410_UDC_P_RESET\n", __func__);
+                /* FIXME: Do something here. */
+        }
+}
+/* Get PMU to set USB current limit accordingly. */
+static struct s3c2410_udc_mach_info gta02_udc_cfg = {
+        .vbus_draw      = gta02_udc_vbus_draw,
+        .udc_command    = gta02_udc_command,
+};
+static void gta02_bl_set_intensity(int intensity)
+{
+        struct pcf50633 *pcf = gta02_pcf;
+        int old_intensity = pcf50633_reg_read(pcf, PCF50633_REG_LEDOUT);
+        /* We map 8-bit intensity to 6-bit intensity in hardware. */
+        intensity >>= 2;
+        /*
+         * This can happen during, eg, print of panic on blanked console,
+         * but we can't service i2c without interrupts active, so abort.
+         */
+        if (in_atomic()) {
+                printk(KERN_ERR "gta02_bl_set_intensity called while atomic\n");
+                return;
+        }
+        old_intensity = pcf50633_reg_read(pcf, PCF50633_REG_LEDOUT);
+        if (intensity == old_intensity)
+                return;
+        /* We can't do this anywhere else. */
+        pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 5);
+        if (!(pcf50633_reg_read(pcf, PCF50633_REG_LEDENA) & 3))
+                old_intensity = 0;
+        /*
+         * The PCF50633 cannot handle LEDOUT = 0 (datasheet p60)
+         * if seen, you have to re-enable the LED unit.
+         */
+        if (!intensity || !old_intensity)
+                pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0);
+        /* Illegal to set LEDOUT to 0. */
+        if (!intensity)
+                pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_LEDOUT, 0x3f, 2);
+        else
+                pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_LEDOUT, 0x3f,
+                                          intensity);
+        if (intensity)
+                pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 2);
+}
+static struct generic_bl_info gta02_bl_info = {
+        .name                   = "gta02-bl",
+        .max_intensity          = 0xff,
+        .default_intensity      = 0xff,
+        .set_bl_intensity       = gta02_bl_set_intensity,
+};
+static struct platform_device gta02_bl_dev = {
+        .name                   = "generic-bl",
+        .id                     = 1,
+        .dev = {
+                .platform_data = &gta02_bl_info,
+        },
+};
+/* USB */
+static struct s3c2410_hcd_info gta02_usb_info = {
+        .port[0]        = {
+                .flags  = S3C_HCDFLG_USED,
+        },
+        .port[1]        = {
+                .flags  = 0,
+        },
+};
+static void __init gta02_map_io(void)
+{
+        s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
+}
+/* These are the guys that don't need to be children of PMU. */
+static struct platform_device *gta02_devices[] __initdata = {
+        &s3c_device_usb,
+        &s3c_device_wdt,
+        &s3c_device_sdi,
+        &s3c_device_usbgadget,
+        &s3c_device_nand,
+        &gta02_nor_flash,
+        &s3c24xx_pwm_device,
+        &s3c_device_iis,
+        &s3c_device_i2c0,
+};
+/* These guys DO need to be children of PMU. */
+static struct platform_device *gta02_devices_pmu_children[] = {
+        &gta02_bl_dev,
+};
+/*
+ * This is called when pc50633 is probed, quite late in the day since it is an
+ * I2C bus device.  Here we can define platform devices with the advantage that
+ * we can mark the pcf50633 as the parent.  This makes them get suspended and
+ * resumed with their parent the pcf50633 still around.  All devices whose
+ * operation depends on something from pcf50633 must have this relationship
+ * made explicit like this, or suspend and resume will become an unreliable
+ * hellworld.
+ */
+static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf)
+{
+        int n;
+        /* Grab a copy of the now probed PMU pointer. */
+        gta02_pcf = pcf;
+        for (n = 0; n < ARRAY_SIZE(gta02_devices_pmu_children); n++)
+                gta02_devices_pmu_children[n]->dev.parent = pcf->dev;
+        platform_add_devices(gta02_devices_pmu_children,
+                             ARRAY_SIZE(gta02_devices_pmu_children));
+}
+static void gta02_poweroff(void)
+{
+        pcf50633_reg_set_bit_mask(gta02_pcf, PCF50633_REG_OOCSHDWN, 1, 1);
+}
+static void __init gta02_machine_init(void)
+{
+        /* Set the panic callback to make AUX LED blink at ~5Hz. */
+        panic_blink = gta02_panic_blink;
+        s3c_pm_init();
+#ifdef CONFIG_CHARGER_PCF50633
+        INIT_DELAYED_WORK(&gta02_charger_work, gta02_charger_worker);
+#endif
+        s3c_device_usb.dev.platform_data = &gta02_usb_info;
+        s3c_device_nand.dev.platform_data = &gta02_nand_info;
+        s3c24xx_udc_set_platdata(&gta02_udc_cfg);
+        s3c_i2c0_set_platdata(NULL);
+        i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs));
+        platform_add_devices(gta02_devices, ARRAY_SIZE(gta02_devices));
+        pm_power_off = gta02_poweroff;
+}
+MACHINE_START(NEO1973_GTA02, "GTA02")
+        /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */
+        .phys_io        = S3C2410_PA_UART,
+        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+        .map_io         = gta02_map_io,
+        .init_irq       = s3c24xx_init_irq,
+        .init_machine   = gta02_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 3a398befed41..03cd27d917b9 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -62,6 +62,12 @@
 #define SHIFT_ASR       0x40
 #define SHIFT_RORRRX    0x60
+#define BAD_INSTR       0xdeadc0de
+/* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
+#define IS_T32(hi16) \
+        (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
 static unsigned long ai_user;
 static unsigned long ai_sys;
 static unsigned long ai_skipped;
@@ -332,38 +338,48 @@ do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
                      struct pt_regs *regs)
 {
        unsigned int rd = RD_BITS(instr);
+        unsigned int rd2;
-        if (((rd & 1) == 1) || (rd == 14))
+        int load;
+        if ((instr & 0xfe000000) == 0xe8000000) {
+                /* ARMv7 Thumb-2 32-bit LDRD/STRD */
+                rd2 = (instr >> 8) & 0xf;
+                load = !!(LDST_L_BIT(instr));
+        } else if (((rd & 1) == 1) || (rd == 14))
                goto bad;
+        else {
+                load = ((instr & 0xf0) == 0xd0);
+                rd2 = rd + 1;
+        }
        ai_dword += 1;
        if (user_mode(regs))
                goto user;
-        if ((instr & 0xf0) == 0xd0) {
+        if (load) {
                unsigned long val;
                get32_unaligned_check(val, addr);
                regs->uregs[rd] = val;
                get32_unaligned_check(val, addr + 4);
-                regs->uregs[rd + 1] = val;
+                regs->uregs[rd2] = val;
        } else {
                put32_unaligned_check(regs->uregs[rd], addr);
-                put32_unaligned_check(regs->uregs[rd + 1], addr + 4);
+                put32_unaligned_check(regs->uregs[rd2], addr + 4);
        }
        return TYPE_LDST;
 user:
-        if ((instr & 0xf0) == 0xd0) {
+        if (load) {
                unsigned long val;
                get32t_unaligned_check(val, addr);
                regs->uregs[rd] = val;
                get32t_unaligned_check(val, addr + 4);
-                regs->uregs[rd + 1] = val;
+                regs->uregs[rd2] = val;
        } else {
                put32t_unaligned_check(regs->uregs[rd], addr);
-                put32t_unaligned_check(regs->uregs[rd + 1], addr + 4);
+                put32t_unaligned_check(regs->uregs[rd2], addr + 4);
        }
        return TYPE_LDST;
@@ -616,8 +632,72 @@ thumb2arm(u16 tinstr)
                /* Else fall through for illegal instruction case */
        default:
-                return 0xdeadc0de;
+                return BAD_INSTR;
+        }
+}
+/*
+ * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
+ * handlable by ARM alignment handler, also find the corresponding handler,
+ * so that we can reuse ARM userland alignment fault fixups for Thumb.
+ *
+ * @pinstr: original Thumb-2 instruction; returns new handlable instruction
+ * @regs: register context.
+ * @poffset: return offset from faulted addr for later writeback
+ *
+ * NOTES:
+ * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
+ * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
+ */
+static void *
+do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
+                            union offset_union *poffset)
+{
+        unsigned long instr = *pinstr;
+        u16 tinst1 = (instr >> 16) & 0xffff;
+        u16 tinst2 = instr & 0xffff;
+        poffset->un = 0;
+        switch (tinst1 & 0xffe0) {
+        /* A6.3.5 Load/Store multiple */
+        case 0xe880:            /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */
+        case 0xe8a0:            /* ...above writeback version */
+        case 0xe900:            /* STMDB/STMFD, LDMDB/LDMEA */
+        case 0xe920:            /* ...above writeback version */
+                /* no need offset decision since handler calculates it */
+                return do_alignment_ldmstm;
+        case 0xf840:            /* POP/PUSH T3 (single register) */
+                if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {
+                        u32 L = !!(LDST_L_BIT(instr));
+                        const u32 subset[2] = {
+                                0xe92d0000,     /* STMDB sp!,{registers} */
+                                0xe8bd0000,     /* LDMIA sp!,{registers} */
+                        };
+                        *pinstr = subset[L] | (1<<RD_BITS(instr));
+                        return do_alignment_ldmstm;
+                }
+                /* Else fall through for illegal instruction case */
+                break;
+        /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */
+        case 0xe860:
+        case 0xe960:
+        case 0xe8e0:
+        case 0xe9e0:
+                poffset->un = (tinst2 & 0xff) << 2;
+        case 0xe940:
+        case 0xe9c0:
+                return do_alignment_ldrdstrd;
+        /*
+         * No need to handle load/store instructions up to word size
+         * since ARMv6 and later CPUs can perform unaligned accesses.
+         */
+        default:
+                break;
        }
+        return NULL;
 }
 static int
@@ -630,6 +710,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
        mm_segment_t fs;
        unsigned int fault;
        u16 tinstr = 0;
+        int isize = 4;
+        int thumb2_32b = 0;
        instrptr = instruction_pointer(regs);
@@ -637,8 +719,19 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
        set_fs(KERNEL_DS);
        if (thumb_mode(regs)) {
                fault = __get_user(tinstr, (u16 *)(instrptr & ~1));
-                if (!(fault))
+                if (!fault) {
-                        instr = thumb2arm(tinstr);
+                        if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
+                            IS_T32(tinstr)) {
+                                /* Thumb-2 32-bit */
+                                u16 tinst2 = 0;
+                                fault = __get_user(tinst2, (u16 *)(instrptr+2));
+                                instr = (tinstr << 16) | tinst2;
+                                thumb2_32b = 1;
+                        } else {
+                                isize = 2;
+                                instr = thumb2arm(tinstr);
+                        }
+                }
        } else
                fault = __get_user(instr, (u32 *)instrptr);
        set_fs(fs);
@@ -655,7 +748,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 fixup:
-        regs->ARM_pc += thumb_mode(regs) ? 2 : 4;
+        regs->ARM_pc += isize;
        switch (CODING_BITS(instr)) {
        case 0x00000000:        /* 3.13.4 load/store instruction extensions */
@@ -714,18 +807,25 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
                handler = do_alignment_ldrstr;
                break;
-        case 0x08000000:        /* ldm or stm */
+        case 0x08000000:        /* ldm or stm, or thumb-2 32bit instruction */
-                handler = do_alignment_ldmstm;
+                if (thumb2_32b)
+                        handler = do_alignment_t32_to_handler(&instr, regs, &offset);
+                else
+                        handler = do_alignment_ldmstm;
                break;
        default:
                goto bad;
        }
+        if (!handler)
+                goto bad;
        type = handler(addr, instr, regs);
-        if (type == TYPE_ERROR || type == TYPE_FAULT)
+        if (type == TYPE_ERROR || type == TYPE_FAULT) {
+                regs->ARM_pc -= isize;
                goto bad_or_fault;
+        }
        if (type == TYPE_LDST)
                do_alignment_finish_ldst(addr, instr, regs, offset);
@@ -735,7 +835,6 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 bad_or_fault:
        if (type == TYPE_ERROR)
                goto bad;
-        regs->ARM_pc -= thumb_mode(regs) ? 2 : 4;
        /*
         * We got a fault - fix it up, or die.
         */
@@ -751,8 +850,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
         */
        printk(KERN_ERR "Alignment trap: not handling instruction "
                "%0*lx at [<%08lx>]\n",
-                thumb_mode(regs) ? 4 : 8,
+                isize << 1,
-                thumb_mode(regs) ? tinstr : instr, instrptr);
+                isize == 2 ? tinstr : instr, instrptr);
        ai_skipped += 1;
        return 1;
@@ -763,8 +862,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
                printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
                       "Address=0x%08lx FSR 0x%03x\n", current->comm,
                        task_pid_nr(current), instrptr,
-                        thumb_mode(regs) ? 4 : 8,
+                        isize << 1,
-                        thumb_mode(regs) ? tinstr : instr,
+                        isize == 2 ? tinstr : instr,
                        addr, fsr);
        if (ai_usermode & UM_FIXUP)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index fdaa9bb87c16..4722582b17b8 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -836,6 +836,13 @@ void __init reserve_node_zero(pg_data_t *pgdat)
                                BOOTMEM_EXCLUSIVE);
        }
+        if (machine_is_treo680()) {
+                reserve_bootmem_node(pgdat, 0xa0000000, 0x1000,
+                                BOOTMEM_EXCLUSIVE);
+                reserve_bootmem_node(pgdat, 0xa2000000, 0x1000,
+                                BOOTMEM_EXCLUSIVE);
+        }
        if (machine_is_palmt5())
                reserve_bootmem_node(pgdat, 0xa0200000, 0x1000,
                                BOOTMEM_EXCLUSIVE);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index def14ec265b3..7677a4a1cef2 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2457,6 +2457,19 @@ static int __init omap_init_dma(void)
                setup_irq(irq, &omap24xx_dma_irq);
        }
+        /* Enable smartidle idlemodes and autoidle */
+        if (cpu_is_omap34xx()) {
+                u32 v = dma_read(OCP_SYSCONFIG);
+                v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
+                                DMA_SYSCONFIG_SIDLEMODE_MASK |
+                                DMA_SYSCONFIG_AUTOIDLE);
+                v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
+                        DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
+                        DMA_SYSCONFIG_AUTOIDLE);
+                dma_write(v , OCP_SYSCONFIG);
+        }
        /* FIXME: Update LCD DMA to work on 24xx */
        if (cpu_class_is_omap1()) {
                r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 7fd89ba8d3b5..26b387c12423 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -1585,6 +1585,7 @@ static int __init _omap_gpio_init(void)
                        __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
                        __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
                        __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
+                        __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
                        /* Initialize interface clock ungated, module enabled */
                        __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
index fc60c4ebcc28..285eaa3a8275 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -30,6 +30,17 @@
 #ifndef __ASM_ARCH_OMAP_CPU_H
 #define __ASM_ARCH_OMAP_CPU_H
+/*
+ * Omap device type i.e. EMU/HS/TST/GP/BAD
+ */
+#define OMAP2_DEVICE_TYPE_TEST          0
+#define OMAP2_DEVICE_TYPE_EMU           1
+#define OMAP2_DEVICE_TYPE_SEC           2
+#define OMAP2_DEVICE_TYPE_GP            3
+#define OMAP2_DEVICE_TYPE_BAD           4
+int omap_type(void);
 struct omap_chip_id {
        u8 oc;
        u8 type;
@@ -424,17 +435,6 @@ IS_OMAP_TYPE(3430, 0x3430)
 int omap_chip_is(struct omap_chip_id oci);
-int omap_type(void);
-/*
- * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
- */
-#define OMAP2_DEVICE_TYPE_TEST          0
-#define OMAP2_DEVICE_TYPE_EMU           1
-#define OMAP2_DEVICE_TYPE_SEC           2
-#define OMAP2_DEVICE_TYPE_GP            3
-#define OMAP2_DEVICE_TYPE_BAD           4
 void omap2_check_revision(void);
 #endif    /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
index 8c1eae88737e..7b939cc01962 100644
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/mach/dma.h
@@ -389,6 +389,21 @@
 #define DMA_THREAD_FIFO_25              (0x02 << 14)
 #define DMA_THREAD_FIFO_50              (0x03 << 14)
+/* DMA4_OCP_SYSCONFIG bits */
+#define DMA_SYSCONFIG_MIDLEMODE_MASK            (3 << 12)
+#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK        (3 << 8)
+#define DMA_SYSCONFIG_EMUFREE                   (1 << 5)
+#define DMA_SYSCONFIG_SIDLEMODE_MASK            (3 << 3)
+#define DMA_SYSCONFIG_SOFTRESET                 (1 << 2)
+#define DMA_SYSCONFIG_AUTOIDLE                  (1 << 0)
+#define DMA_SYSCONFIG_MIDLEMODE(n)              ((n) << 12)
+#define DMA_SYSCONFIG_SIDLEMODE(n)              ((n) << 3)
+#define DMA_IDLEMODE_SMARTIDLE                  0x2
+#define DMA_IDLEMODE_NO_IDLE                    0x1
+#define DMA_IDLEMODE_FORCE_IDLE                 0x0
 /* Chaining modes*/
 #ifndef CONFIG_ARCH_OMAP1
 #define OMAP_DMA_STATIC_CHAIN           0x1
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index 3b2814720569..73f483d56ca6 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -201,7 +201,7 @@
 #define OMAP2_IO_ADDRESS(pa)    IOMEM(__OMAP2_IO_ADDRESS(pa))
 #ifdef __ASSEMBLER__
-#define IOMEM(x)                x
+#define IOMEM(x)                (x)
 #else
 #define IOMEM(x)                ((void __force __iomem *)(x))
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index dca7c16ae903..4d53cc59d7a3 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -24,7 +24,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
                                     u32 sdrc_actim_ctrla,
                                     u32 sdrc_actim_ctrlb, u32 m2,
-                                     u32 unlock_dll);
+                                     u32 unlock_dll, u32 f, u32 sdrc_mr,
+                                     u32 inc);
 /* Do not use these */
 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@@ -62,7 +63,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
 extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
                                          u32 sdrc_actim_ctrla,
                                          u32 sdrc_actim_ctrlb, u32 m2,
-                                          u32 unlock_dll);
+                                          u32 unlock_dll, u32 f, u32 sdrc_mr,
+                                          u32 inc);
 extern unsigned long omap3_sram_configure_core_dpll_sz;
 #endif
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 4cf449fa2cb5..4a0301399013 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -298,7 +298,7 @@ void flush_iotlb_page(struct iommu *obj, u32 da)
                if ((start <= da) && (da < start + bytes)) {
                        dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
                                __func__, start, da, bytes);
+                        iotlb_load_cr(obj, &cr);
                        iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
                }
        }
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index a5b9bcd6b108..4ea73804d21e 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -133,7 +133,12 @@ void __init omap_detect_sram(void)
                        if (cpu_is_omap34xx()) {
                                omap_sram_base = OMAP3_SRAM_PUB_VA;
                                omap_sram_start = OMAP3_SRAM_PUB_PA;
-                                omap_sram_size = 0x8000; /* 32K */
+                                if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
+                                    (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
+                                        omap_sram_size = 0x7000; /* 28K */
+                                } else {
+                                        omap_sram_size = 0x8000; /* 32K */
+                                }
                        } else {
                                omap_sram_base = OMAP2_SRAM_PUB_VA;
                                omap_sram_start = OMAP2_SRAM_PUB_PA;
@@ -371,15 +376,17 @@ static inline int omap243x_sram_init(void)
 static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
                                              u32 sdrc_actim_ctrla,
                                              u32 sdrc_actim_ctrlb,
-                                              u32 m2, u32 unlock_dll);
+                                              u32 m2, u32 unlock_dll,
+                                              u32 f, u32 sdrc_mr, u32 inc);
 u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
-                              u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll)
+                              u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
+                              u32 f, u32 sdrc_mr, u32 inc)
 {
        BUG_ON(!_omap3_sram_configure_core_dpll);
        return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
                                               sdrc_actim_ctrla,
                                               sdrc_actim_ctrlb, m2,
-                                               unlock_dll);
+                                               unlock_dll, f, sdrc_mr, inc);
 }
 /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
index 610651455a78..0761766b1833 100644
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_S3C_DEV_HSMMC)	+= dev-hsmmc.o
 obj-$(CONFIG_S3C_DEV_HSMMC1)    += dev-hsmmc1.o
 obj-y                           += dev-i2c0.o
 obj-$(CONFIG_S3C_DEV_I2C1)      += dev-i2c1.o
+obj-$(CONFIG_SND_S3C64XX_SOC_I2S)       += dev-audio.o
 obj-$(CONFIG_S3C_DEV_FB)        += dev-fb.o
 obj-$(CONFIG_S3C_DEV_USB_HOST)  += dev-usb.o
 obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o
diff --git a/arch/arm/plat-s3c/dev-audio.c b/arch/arm/plat-s3c/dev-audio.c
new file mode 100644
index 000000000000..1322beb40dd7
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-audio.c
@@ -0,0 +1,68 @@
+/* linux/arch/arm/plat-s3c/dev-audio.c
+ *
+ * Copyright 2009 Wolfson Microelectronics
+ *      Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <plat/devs.h>
+static struct resource s3c64xx_iis0_resource[] = {
+        [0] = {
+                .start = S3C64XX_PA_IIS0,
+                .end   = S3C64XX_PA_IIS0 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+struct platform_device s3c64xx_device_iis0 = {
+        .name             = "s3c64xx-iis",
+        .id               = 0,
+        .num_resources    = ARRAY_SIZE(s3c64xx_iis0_resource),
+        .resource         = s3c64xx_iis0_resource,
+};
+EXPORT_SYMBOL(s3c64xx_device_iis0);
+static struct resource s3c64xx_iis1_resource[] = {
+        [0] = {
+                .start = S3C64XX_PA_IIS1,
+                .end   = S3C64XX_PA_IIS1 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+struct platform_device s3c64xx_device_iis1 = {
+        .name             = "s3c64xx-iis",
+        .id               = 1,
+        .num_resources    = ARRAY_SIZE(s3c64xx_iis1_resource),
+        .resource         = s3c64xx_iis1_resource,
+};
+EXPORT_SYMBOL(s3c64xx_device_iis1);
+static struct resource s3c64xx_iisv4_resource[] = {
+        [0] = {
+                .start = S3C64XX_PA_IISV4,
+                .end   = S3C64XX_PA_IISV4 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+struct platform_device s3c64xx_device_iisv4 = {
+        .name             = "s3c64xx-iis-v4",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(s3c64xx_iisv4_resource),
+        .resource         = s3c64xx_iisv4_resource,
+};
+EXPORT_SYMBOL(s3c64xx_device_iisv4);
diff --git a/arch/arm/plat-s3c/gpio-config.c b/arch/arm/plat-s3c/gpio-config.c
index 08044dec9731..456969b6fa0d 100644
--- a/arch/arm/plat-s3c/gpio-config.c
+++ b/arch/arm/plat-s3c/gpio-config.c
@@ -119,7 +119,7 @@ int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
        unsigned int shift = (off & 7) * 4;
        u32 con;
-        if (off < 8 && chip->chip.ngpio >= 8)
+        if (off < 8 && chip->chip.ngpio > 8)
                reg -= 4;
        if (s3c_gpio_is_cfg_special(cfg)) {
diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h
index a0b6768fddcf..2e170827e0b0 100644
--- a/arch/arm/plat-s3c/include/plat/devs.h
+++ b/arch/arm/plat-s3c/include/plat/devs.h
@@ -24,16 +24,20 @@ extern struct platform_device *s3c24xx_uart_src[];
 extern struct platform_device s3c_device_timer[];
+extern struct platform_device s3c64xx_device_iis0;
+extern struct platform_device s3c64xx_device_iis1;
+extern struct platform_device s3c64xx_device_iisv4;
 extern struct platform_device s3c_device_fb;
 extern struct platform_device s3c_device_usb;
 extern struct platform_device s3c_device_lcd;
 extern struct platform_device s3c_device_wdt;
 extern struct platform_device s3c_device_i2c0;
 extern struct platform_device s3c_device_i2c1;
-extern struct platform_device s3c_device_iis;
 extern struct platform_device s3c_device_rtc;
 extern struct platform_device s3c_device_adc;
 extern struct platform_device s3c_device_sdi;
+extern struct platform_device s3c_device_iis;
 extern struct platform_device s3c_device_hwmon;
 extern struct platform_device s3c_device_hsmmc0;
 extern struct platform_device s3c_device_hsmmc1;
diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h
index f4dcd14af059..18f958801e64 100644
--- a/arch/arm/plat-s3c/include/plat/nand.h
+++ b/arch/arm/plat-s3c/include/plat/nand.h
@@ -10,19 +10,26 @@
 * published by the Free Software Foundation.
 */
-/* struct s3c2410_nand_set
+/**
+ * struct s3c2410_nand_set - define a set of one or more nand chips
+ * @disable_ecc:        Entirely disable ECC - Dangerous
+ * @flash_bbt:          Openmoko u-boot can create a Bad Block Table
+ *                      Setting this flag will allow the kernel to
+ *                      look for it at boot time and also skip the NAND
+ *                      scan.
+ * @nr_chips:           Number of chips in this set
+ * @nr_partitions:      Number of partitions pointed to by @partitions
+ * @name:               Name of set (optional)
+ * @nr_map:             Map for low-layer logical to physical chip numbers (option)
+ * @partitions:         The mtd partition list
 *
- * define an set of one or more nand chips registered with an unique mtd
+ * define a set of one or more nand chips registered with an unique mtd. Also
- *
+ * allows to pass flag to the underlying NAND layer. 'disable_ecc' will trigger
- * nr_chips      = number of chips in this set
+ * a warning at boot time.
- * nr_partitions = number of partitions pointed to be partitoons (or zero)
+ */
- * name          = name of set (optional)
- * nr_map        = map for low-layer logical to physical chip numbers (option)
- * partitions    = mtd partition list
-*/
 struct s3c2410_nand_set {
-        unsigned int            disable_ecc : 1;
+        unsigned int            disable_ecc:1;
+        unsigned int            flash_bbt:1;
        int                     nr_chips;
        int                     nr_partitions;
@@ -39,7 +46,7 @@ struct s3c2410_platform_nand {
        int     twrph0; /* active time for nWE/nOE */
        int     twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
-        unsigned int    ignore_unset_ecc : 1;
+        unsigned int    ignore_unset_ecc:1;
        int                     nr_sets;
        struct s3c2410_nand_set *sets;
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 636cb12711df..579a165c2827 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -29,7 +29,7 @@ obj-$(CONFIG_PM_SIMTEC)		+= pm-simtec.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_PM)                += irq-pm.o
 obj-$(CONFIG_PM)                += sleep.o
-obj-$(CONFIG_HAVE_PWM)          += pwm.o
+obj-$(CONFIG_S3C24XX_PWM)       += pwm.o
 obj-$(CONFIG_S3C2410_CLOCK)     += s3c2410-clock.o
 obj-$(CONFIG_S3C2410_DMA)       += dma.o
 obj-$(CONFIG_S3C24XX_ADC)       += adc.o
diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
index 9edf7894eedd..da7a61728c18 100644
--- a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
+++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
@@ -12,8 +12,7 @@
 */
 #include <linux/kernel.h>
+#include <linux/gpio.h>
-#include <mach/hardware.h>
 #include <mach/spi.h>
 #include <mach/regs-gpio.h>
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
index f34d0fc69ad8..86b9edc67413 100644
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
@@ -12,8 +12,7 @@
 */
 #include <linux/kernel.h>
+#include <linux/gpio.h>
-#include <mach/hardware.h>
 #include <mach/spi.h>
 #include <mach/regs-gpio.h>
diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile
index 2ed5df34f9ea..3c8882cd6268 100644
--- a/arch/arm/plat-s3c64xx/Makefile
+++ b/arch/arm/plat-s3c64xx/Makefile
@@ -23,6 +23,7 @@ obj-y				+= gpiolib.o
 obj-$(CONFIG_CPU_S3C6400_INIT)  += s3c6400-init.o
 obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o
+obj-$(CONFIG_CPU_FREQ_S3C64XX)  += cpufreq.o
 # PM support
diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c
index 0bc2fa1dfc40..7a36e899360d 100644
--- a/arch/arm/plat-s3c64xx/clock.c
+++ b/arch/arm/plat-s3c64xx/clock.c
@@ -191,7 +191,7 @@ static struct clk init_clocks[] = {
                .id             = -1,
                .parent         = &clk_h,
                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
+                .ctrlbit        = S3C_CLKCON_HCLK_UHOST,
        }, {
                .name           = "hsmmc",
                .id             = 0,
diff --git a/arch/arm/plat-s3c64xx/cpufreq.c b/arch/arm/plat-s3c64xx/cpufreq.c
new file mode 100644
index 000000000000..e6e0843215df
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/cpufreq.c
@@ -0,0 +1,262 @@
+/* linux/arch/arm/plat-s3c64xx/cpufreq.c
+ *
+ * Copyright 2009 Wolfson Microelectronics plc
+ *
+ * S3C64xx CPUfreq Support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/cpufreq.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+static struct clk *armclk;
+static struct regulator *vddarm;
+#ifdef CONFIG_CPU_S3C6410
+struct s3c64xx_dvfs {
+        unsigned int vddarm_min;
+        unsigned int vddarm_max;
+};
+static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
+        [0] = { 1000000, 1000000 },
+        [1] = { 1000000, 1050000 },
+        [2] = { 1050000, 1100000 },
+        [3] = { 1050000, 1150000 },
+        [4] = { 1250000, 1350000 },
+};
+static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
+        { 0,  66000 },
+        { 0, 133000 },
+        { 1, 222000 },
+        { 1, 266000 },
+        { 2, 333000 },
+        { 2, 400000 },
+        { 3, 532000 },
+        { 3, 533000 },
+        { 4, 667000 },
+        { 0, CPUFREQ_TABLE_END },
+};
+#endif
+static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy)
+{
+        if (policy->cpu != 0)
+                return -EINVAL;
+        return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table);
+}
+static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu)
+{
+        if (cpu != 0)
+                return 0;
+        return clk_get_rate(armclk) / 1000;
+}
+static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
+                                      unsigned int target_freq,
+                                      unsigned int relation)
+{
+        int ret;
+        unsigned int i;
+        struct cpufreq_freqs freqs;
+        struct s3c64xx_dvfs *dvfs;
+        ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table,
+                                             target_freq, relation, &i);
+        if (ret != 0)
+                return ret;
+        freqs.cpu = 0;
+        freqs.old = clk_get_rate(armclk) / 1000;
+        freqs.new = s3c64xx_freq_table[i].frequency;
+        freqs.flags = 0;
+        dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index];
+        if (freqs.old == freqs.new)
+                return 0;
+        pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new);
+        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+#ifdef CONFIG_REGULATOR
+        if (vddarm && freqs.new > freqs.old) {
+                ret = regulator_set_voltage(vddarm,
+                                            dvfs->vddarm_min,
+                                            dvfs->vddarm_max);
+                if (ret != 0) {
+                        pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
+                               freqs.new, ret);
+                        goto err;
+                }
+        }
+#endif
+        ret = clk_set_rate(armclk, freqs.new * 1000);
+        if (ret < 0) {
+                pr_err("cpufreq: Failed to set rate %dkHz: %d\n",
+                       freqs.new, ret);
+                goto err;
+        }
+#ifdef CONFIG_REGULATOR
+        if (vddarm && freqs.new < freqs.old) {
+                ret = regulator_set_voltage(vddarm,
+                                            dvfs->vddarm_min,
+                                            dvfs->vddarm_max);
+                if (ret != 0) {
+                        pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
+                               freqs.new, ret);
+                        goto err_clk;
+                }
+        }
+#endif
+        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+        pr_debug("cpufreq: Set actual frequency %lukHz\n",
+                 clk_get_rate(armclk) / 1000);
+        return 0;
+err_clk:
+        if (clk_set_rate(armclk, freqs.old * 1000) < 0)
+                pr_err("Failed to restore original clock rate\n");
+err:
+        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+        return ret;
+}
+#ifdef CONFIG_REGULATOR
+static void __init s3c64xx_cpufreq_constrain_voltages(void)
+{
+        int count, v, i, found;
+        struct cpufreq_frequency_table *freq;
+        struct s3c64xx_dvfs *dvfs;
+        count = regulator_count_voltages(vddarm);
+        if (count < 0) {
+                pr_err("cpufreq: Unable to check supported voltages\n");
+                return;
+        }
+        freq = s3c64xx_freq_table;
+        while (freq->frequency != CPUFREQ_TABLE_END) {
+                if (freq->frequency == CPUFREQ_ENTRY_INVALID)
+                        continue;
+                dvfs = &s3c64xx_dvfs_table[freq->index];
+                found = 0;
+                for (i = 0; i < count; i++) {
+                        v = regulator_list_voltage(vddarm, i);
+                        if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
+                                found = 1;
+                }
+                if (!found) {
+                        pr_debug("cpufreq: %dkHz unsupported by regulator\n",
+                                 freq->frequency);
+                        freq->frequency = CPUFREQ_ENTRY_INVALID;
+                }
+                freq++;
+        }
+}
+#endif
+static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
+{
+        int ret;
+        struct cpufreq_frequency_table *freq;
+        if (policy->cpu != 0)
+                return -EINVAL;
+        if (s3c64xx_freq_table == NULL) {
+                pr_err("cpufreq: No frequency information for this CPU\n");
+                return -ENODEV;
+        }
+        armclk = clk_get(NULL, "armclk");
+        if (IS_ERR(armclk)) {
+                pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n",
+                       PTR_ERR(armclk));
+                return PTR_ERR(armclk);
+        }
+#ifdef CONFIG_REGULATOR
+        vddarm = regulator_get(NULL, "vddarm");
+        if (IS_ERR(vddarm)) {
+                ret = PTR_ERR(vddarm);
+                pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
+                pr_err("cpufreq: Only frequency scaling available\n");
+                vddarm = NULL;
+        } else {
+                s3c64xx_cpufreq_constrain_voltages();
+        }
+#endif
+        freq = s3c64xx_freq_table;
+        while (freq->frequency != CPUFREQ_TABLE_END) {
+                unsigned long r;
+                /* Check for frequencies we can generate */
+                r = clk_round_rate(armclk, freq->frequency * 1000);
+                r /= 1000;
+                if (r != freq->frequency)
+                        freq->frequency = CPUFREQ_ENTRY_INVALID;
+                /* If we have no regulator then assume startup
+                 * frequency is the maximum we can support. */
+                if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0))
+                        freq->frequency = CPUFREQ_ENTRY_INVALID;
+                freq++;
+        }
+        policy->cur = clk_get_rate(armclk) / 1000;
+        /* Pick a conservative guess in ns: we'll need ~1 I2C/SPI
+         * write plus clock reprogramming. */
+        policy->cpuinfo.transition_latency = 2 * 1000 * 1000;
+        ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
+        if (ret != 0) {
+                pr_err("cpufreq: Failed to configure frequency table: %d\n",
+                       ret);
+                regulator_put(vddarm);
+                clk_put(armclk);
+        }
+        return ret;
+}
+static struct cpufreq_driver s3c64xx_cpufreq_driver = {
+        .owner          = THIS_MODULE,
+        .flags          = 0,
+        .verify         = s3c64xx_cpufreq_verify_speed,
+        .target         = s3c64xx_cpufreq_set_target,
+        .get            = s3c64xx_cpufreq_get_speed,
+        .init           = s3c64xx_cpufreq_driver_init,
+        .name           = "s3c",
+};
+static int __init s3c64xx_cpufreq_init(void)
+{
+        return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
+}
+module_init(s3c64xx_cpufreq_init);
diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c
index da7b60ee5e67..92859290ea33 100644
--- a/arch/arm/plat-s3c64xx/gpiolib.c
+++ b/arch/arm/plat-s3c64xx/gpiolib.c
@@ -321,6 +321,11 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
        .get_pull       = s3c_gpio_getpull_updown,
 };
+int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
+{
+        return IRQ_EINT(0) + pin;
+}
 static struct s3c_gpio_chip gpio_2bit[] = {
        {
                .base   = S3C64XX_GPF_BASE,
@@ -353,6 +358,7 @@ static struct s3c_gpio_chip gpio_2bit[] = {
                        .base   = S3C64XX_GPN(0),
                        .ngpio  = S3C64XX_GPIO_N_NR,
                        .label  = "GPN",
+                        .to_irq = s3c64xx_gpio2int_gpn,
                },
        }, {
                .base   = S3C64XX_GPO_BASE,
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
index 52836d41e333..a8777a755dfa 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
@@ -88,11 +88,11 @@
 #define S3C6400_CLKDIV2_SPI0_SHIFT      (0)
 /* HCLK GATE Registers */
-#define S3C_CLKCON_HCLK_BUS     (1<<30)
+#define S3C_CLKCON_HCLK_3DSE    (1<<31)
-#define S3C_CLKCON_HCLK_SECUR   (1<<29)
+#define S3C_CLKCON_HCLK_UHOST   (1<<29)
-#define S3C_CLKCON_HCLK_SDMA1   (1<<28)
+#define S3C_CLKCON_HCLK_SECUR   (1<<28)
-#define S3C_CLKCON_HCLK_SDMA2   (1<<27)
+#define S3C_CLKCON_HCLK_SDMA1   (1<<27)
-#define S3C_CLKCON_HCLK_UHOST   (1<<26)
+#define S3C_CLKCON_HCLK_SDMA0   (1<<26)
 #define S3C_CLKCON_HCLK_IROM    (1<<25)
 #define S3C_CLKCON_HCLK_DDR1    (1<<24)
 #define S3C_CLKCON_HCLK_DDR0    (1<<23)
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index fec64678a63a..33026eff2aa4 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Fri May 29 10:14:20 2009
+# Last update: Sat Jun 20 22:28:39 2009
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -1455,7 +1455,7 @@ gba			MACH_GBA		GBA			1457
 h6044                   MACH_H6044              H6044                   1458
 app                     MACH_APP                APP                     1459
 tct_hammer              MACH_TCT_HAMMER         TCT_HAMMER              1460
-herald                  MACH_HERMES             HERMES                  1461
+herald                  MACH_HERALD             HERALD                  1461
 artemis                 MACH_ARTEMIS            ARTEMIS                 1462
 htctitan                MACH_HTCTITAN           HTCTITAN                1463
 qranium                 MACH_QRANIUM            QRANIUM                 1464
@@ -2245,3 +2245,38 @@ str9			MACH_STR9		STR9			2257
 omap3_wl_ff             MACH_OMAP3_WL_FF        OMAP3_WL_FF             2258
 simcom                  MACH_SIMCOM             SIMCOM                  2259
 mcwebio                 MACH_MCWEBIO            MCWEBIO                 2260
+omap3_phrazer           MACH_OMAP3_PHRAZER      OMAP3_PHRAZER           2261
+darwin                  MACH_DARWIN             DARWIN                  2262
+oratiscomu              MACH_ORATISCOMU         ORATISCOMU              2263
+rtsbc20                 MACH_RTSBC20            RTSBC20                 2264
+i780                    MACH_I780               I780                    2265
+gemini324               MACH_GEMINI324          GEMINI324               2266
+oratislan               MACH_ORATISLAN          ORATISLAN               2267
+oratisalog              MACH_ORATISALOG         ORATISALOG              2268
+oratismadi              MACH_ORATISMADI         ORATISMADI              2269
+oratisot16              MACH_ORATISOT16         ORATISOT16              2270
+oratisdesk              MACH_ORATISDESK         ORATISDESK              2271
+v2p_ca9                 MACH_V2P_CA9            V2P_CA9                 2272
+sintexo                 MACH_SINTEXO            SINTEXO                 2273
+cm3389                  MACH_CM3389             CM3389                  2274
+omap3_cio               MACH_OMAP3_CIO          OMAP3_CIO               2275
+sgh_i900                MACH_SGH_I900           SGH_I900                2276
+bst100                  MACH_BST100             BST100                  2277
+passion                 MACH_PASSION            PASSION                 2278
+indesign_at91sam        MACH_INDESIGN_AT91SAM   INDESIGN_AT91SAM        2279
+c4_badger               MACH_C4_BADGER          C4_BADGER               2280
+c4_viper                MACH_C4_VIPER           C4_VIPER                2281
+d2net                   MACH_D2NET              D2NET                   2282
+bigdisk                 MACH_BIGDISK            BIGDISK                 2283
+notalvision             MACH_NOTALVISION        NOTALVISION             2284
+omap3_kboc              MACH_OMAP3_KBOC         OMAP3_KBOC              2285
+cyclone                 MACH_CYCLONE            CYCLONE                 2286
+ninja                   MACH_NINJA              NINJA                   2287
+at91sam9g20ek_2mmc      MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC      2288
+bcmring                 MACH_BCMRING            BCMRING                 2289
+resol_dl2               MACH_RESOL_DL2          RESOL_DL2               2290
+ifosw                   MACH_IFOSW              IFOSW                   2291
+htcrhodium              MACH_HTCRHODIUM         HTCRHODIUM              2292
+htctopaz                MACH_HTCTOPAZ           HTCTOPAZ                2293
+matrix504               MACH_MATRIX504          MATRIX504               2294
+mrfsa                   MACH_MRFSA              MRFSA                   2295