52 files changed, 1401 insertions, 240 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 296bc03d1cf1..ec77721507cb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -324,7 +324,7 @@ menu "Kernel Features"
 
 config SMP
         bool "Symmetric Multi-Processing (EXPERIMENTAL)"
-        depends on EXPERIMENTAL && BROKEN #&& n
+        depends on EXPERIMENTAL && REALVIEW_MPCORE
         help
           This enables support for systems with more than one CPU. If you have
           a system with only one CPU, like most personal computers, say N. If
@@ -356,6 +356,16 @@ config HOTPLUG_CPU
           Say Y here to experiment with turning CPUs off and on.  CPUs
           can be controlled through /sys/devices/system/cpu.
 
+config LOCAL_TIMERS
+        bool "Use local timer interrupts"
+        depends on SMP && REALVIEW_MPCORE
+        default y
+        help
+          Enable support for local timers on SMP platforms, rather then the
+          legacy IPI broadcast method.  Local timers allows the system
+          accounting to be spread across the timer interval, preventing a
+          "thundering herd" at every timer tick.
+
 config PREEMPT
         bool "Preemptible Kernel (EXPERIMENTAL)"
         depends on EXPERIMENTAL
@@ -585,7 +595,7 @@ config FPE_NWFPE
 
 config FPE_NWFPE_XP
         bool "Support extended precision"
-        depends on FPE_NWFPE && !CPU_BIG_ENDIAN
+        depends on FPE_NWFPE
         help
           Say Y to include 80-bit support in the kernel floating-point
           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 50f13eec6cd7..5ab94584baee 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -283,8 +283,14 @@ void flush_window(void)
         putstr(".");
 }
 
+#ifndef arch_error
+#define arch_error(x)
+#endif
+
 static void error(char *x)
 {
+        arch_error(x);
+
         putstr("\n\n");
         putstr(x);
         putstr("\n\n -- System halted");
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c
index bb4eff614413..c7fdf390cef9 100644
--- a/arch/arm/common/scoop.c
+++ b/arch/arm/common/scoop.c
@@ -19,12 +19,6 @@
 
 #define SCOOP_REG(d,adr) (*(volatile unsigned short*)(d +(adr)))
 
-/* PCMCIA to Scoop linkage structures for pxa2xx_sharpsl.c
-   There is no easy way to link multiple scoop devices into one
-   single entity for the pxa2xx_pcmcia device */
-int scoop_num;
-struct scoop_pcmcia_dev *scoop_devs;
-
 struct  scoop_dev {
         void  *base;
         spinlock_t scoop_lock;
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 7b17a87a3311..7a3261f0bf79 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -9,6 +9,7 @@
  */
 #include <linux/module.h>
 #include <linux/string.h>
+#include <linux/cryptohash.h>
 #include <linux/delay.h>
 #include <linux/in6.h>
 #include <linux/syscalls.h>
@@ -126,6 +127,9 @@ EXPORT_SYMBOL(__put_user_2);
 EXPORT_SYMBOL(__put_user_4);
 EXPORT_SYMBOL(__put_user_8);
 
+        /* crypto hash */
+EXPORT_SYMBOL(sha_transform);
+
         /* gcc lib functions */
 EXPORT_SYMBOL(__ashldi3);
 EXPORT_SYMBOL(__ashrdi3);
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index be439cab92c6..d9fb819bf7cc 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -47,6 +47,13 @@
         movne   r0, sp
         adrne   lr, 1b
         bne     do_IPI
+
+#ifdef CONFIG_LOCAL_TIMERS
+        test_for_ltirq r0, r6, r5, lr
+        movne   r0, sp
+        adrne   lr, 1b
+        bne     do_local_timer
+#endif
 #endif
 
         .endm
@@ -785,7 +792,7 @@ __kuser_helper_end:
  * SP points to a minimal amount of processor-private memory, the address
  * of which is copied into r0 for the mode specific abort handler.
  */
-        .macro  vector_stub, name, correction=0
+        .macro  vector_stub, name, mode, correction=0
         .align  5
 
 vector_\name:
@@ -805,15 +812,14 @@ vector_\name:
         @ Prepare for SVC32 mode.  IRQs remain disabled.
         @
         mrs     r0, cpsr
-        bic     r0, r0, #MODE_MASK
-        orr     r0, r0, #SVC_MODE
+        eor     r0, r0, #(\mode ^ SVC_MODE)
         msr     spsr_cxsf, r0
 
         @
         @ the branch table must immediately follow this code
         @
-        mov     r0, sp
         and     lr, lr, #0x0f
+        mov     r0, sp
         ldr     lr, [pc, lr, lsl #2]
         movs    pc, lr                  @ branch to handler in SVC mode
         .endm
@@ -823,7 +829,7 @@ __stubs_start:
 /*
  * Interrupt dispatcher
  */
-        vector_stub     irq, 4
+        vector_stub     irq, IRQ_MODE, 4
 
         .long   __irq_usr                       @  0  (USR_26 / USR_32)
         .long   __irq_invalid                   @  1  (FIQ_26 / FIQ_32)
@@ -846,7 +852,7 @@ __stubs_start:
  * Data abort dispatcher
  * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
  */
-        vector_stub     dabt, 8
+        vector_stub     dabt, ABT_MODE, 8
 
         .long   __dabt_usr                      @  0  (USR_26 / USR_32)
         .long   __dabt_invalid                  @  1  (FIQ_26 / FIQ_32)
@@ -869,7 +875,7 @@ __stubs_start:
  * Prefetch abort dispatcher
  * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
  */
-        vector_stub     pabt, 4
+        vector_stub     pabt, ABT_MODE, 4
 
         .long   __pabt_usr                      @  0 (USR_26 / USR_32)
         .long   __pabt_invalid                  @  1 (FIQ_26 / FIQ_32)
@@ -892,7 +898,7 @@ __stubs_start:
  * Undef instr entry dispatcher
  * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
  */
-        vector_stub     und
+        vector_stub     und, UND_MODE
 
         .long   __und_usr                       @  0 (USR_26 / USR_32)
         .long   __und_invalid                   @  1 (FIQ_26 / FIQ_32)
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 9def4404e1f2..d7099dbbb879 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -264,6 +264,7 @@ unlock:
 #endif
 #ifdef CONFIG_SMP
                 show_ipi_list(p);
+                show_local_irqs(p);
 #endif
                 seq_printf(p, "Err: %10lu\n", irq_err_count);
         }
@@ -995,7 +996,7 @@ void __init init_irq_proc(void)
         struct proc_dir_entry *dir;
         int irq;
 
-        dir = proc_mkdir("irq", 0);
+        dir = proc_mkdir("irq", NULL);
         if (!dir)
                 return;
 
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index ba298277becd..30494aab829a 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -86,12 +86,16 @@ EXPORT_SYMBOL(pm_power_off);
  */
 void default_idle(void)
 {
-        local_irq_disable();
-        if (!need_resched() && !hlt_counter) {
-                timer_dyn_reprogram();
-                arch_idle();
+        if (hlt_counter)
+                cpu_relax();
+        else {
+                local_irq_disable();
+                if (!need_resched()) {
+                        timer_dyn_reprogram();
+                        arch_idle();
+                }
+                local_irq_enable();
         }
-        local_irq_enable();
 }
 
 /*
@@ -116,13 +120,13 @@ void cpu_idle(void)
 
                 if (!idle)
                         idle = default_idle;
-                preempt_disable();
                 leds_event(led_idle_start);
                 while (!need_resched())
                         idle();
                 leds_event(led_idle_end);
-                preempt_enable();
+                preempt_enable_no_resched();
                 schedule();
+                preempt_disable();
         }
 }
 
@@ -355,7 +359,7 @@ copy_thread(int nr, unsigned long clone_flags, unsigned long stack_start,
         struct thread_info *thread = p->thread_info;
         struct pt_regs *childregs;
 
-        childregs = ((struct pt_regs *)((unsigned long)thread + THREAD_START_SP)) - 1;
+        childregs = (void *)thread + THREAD_START_SP - sizeof(*regs);
         *childregs = *regs;
         childregs->ARM_r0 = 0;
         childregs->ARM_sp = stack_start;
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 9bd8609a2926..9a340e790da5 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -648,7 +648,7 @@ static int ptrace_setwmmxregs(struct task_struct *tsk, void __user *ufp)
 
 #endif
 
-static int do_ptrace(int request, struct task_struct *child, long addr, long data)
+long arch_ptrace(struct task_struct *child, long request, long addr, long data)
 {
         unsigned long tmp;
         int ret;
@@ -782,53 +782,6 @@ static int do_ptrace(int request, struct task_struct *child, long addr, long dat
         return ret;
 }
 
-asmlinkage long sys_ptrace(long request, long pid, long addr, long data)
-{
-        struct task_struct *child;
-        int ret;
-
-        lock_kernel();
-        ret = -EPERM;
-        if (request == PTRACE_TRACEME) {
-                /* are we already being traced? */
-                if (current->ptrace & PT_PTRACED)
-                        goto out;
-                ret = security_ptrace(current->parent, current);
-                if (ret)
-                        goto out;
-                /* set the ptrace bit in the process flags. */
-                current->ptrace |= PT_PTRACED;
-                ret = 0;
-                goto out;
-        }
-        ret = -ESRCH;
-        read_lock(&tasklist_lock);
-        child = find_task_by_pid(pid);
-        if (child)
-                get_task_struct(child);
-        read_unlock(&tasklist_lock);
-        if (!child)
-                goto out;
-
-        ret = -EPERM;
-        if (pid == 1)           /* you may not mess with init */
-                goto out_tsk;
-
-        if (request == PTRACE_ATTACH) {
-                ret = ptrace_attach(child);
-                goto out_tsk;
-        }
-        ret = ptrace_check_attach(child, request == PTRACE_KILL);
-        if (ret == 0)
-                ret = do_ptrace(request, child, addr, data);
-
-out_tsk:
-        put_task_struct(child);
-out:
-        unlock_kernel();
-        return ret;
-}
-
 asmlinkage void syscall_trace(int why, struct pt_regs *regs)
 {
         unsigned long ip;
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index c9b69771f92e..85774165e9fd 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -338,7 +338,8 @@ void cpu_init(void)
                 BUG();
         }
 
-        dump_cpu_info(cpu);
+        if (system_state == SYSTEM_BOOTING)
+                dump_cpu_info(cpu);
 
         /*
          * setup stacks for re-entrant exception handlers
@@ -838,7 +839,12 @@ static int c_show(struct seq_file *m, void *v)
 
 #if defined(CONFIG_SMP)
         for_each_online_cpu(i) {
-                seq_printf(m, "Processor\t: %d\n", i);
+                /*
+                 * glibc reads /proc/cpuinfo to determine the number of
+                 * online processors, looking for lines beginning with
+                 * "processor".  Give glibc what it expects.
+                 */
+                seq_printf(m, "processor\t: %d\n", i);
                 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n\n",
                            per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),
                            (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index edb5a406922f..e55ea952f7aa 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -142,7 +142,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
                         ret = -EIO;
         }
 
-        secondary_data.stack = 0;
+        secondary_data.stack = NULL;
         secondary_data.pgdir = 0;
 
         *pmd_offset(pgd, PHYS_OFFSET) = __pmd(0);
@@ -185,6 +185,11 @@ int __cpuexit __cpu_disable(void)
         migrate_irqs();
 
         /*
+         * Stop the local timer for this CPU.
+         */
+        local_timer_stop(cpu);
+
+        /*
          * Flush user cache and TLB mappings, and then remove this CPU
          * from the vm mask set of all processes.
          */
@@ -251,7 +256,9 @@ void __cpuexit cpu_die(void)
 asmlinkage void __cpuinit secondary_start_kernel(void)
 {
         struct mm_struct *mm = &init_mm;
-        unsigned int cpu = smp_processor_id();
+        unsigned int cpu;
+
+        cpu = smp_processor_id();
 
         printk("CPU%u: Booted secondary processor\n", cpu);
 
@@ -268,6 +275,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
         local_flush_tlb_all();
 
         cpu_init();
+        preempt_disable();
 
         /*
          * Give the platform a chance to do its own initialisation.
@@ -290,6 +298,11 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
         cpu_set(cpu, cpu_online_map);
 
         /*
+         * Setup local timer for this CPU.
+         */
+        local_timer_setup(cpu);
+
+        /*
          * OK, it's off to the idle thread for us
          */
         cpu_idle();
@@ -359,8 +372,8 @@ static void send_ipi_message(cpumask_t callmap, enum ipi_msg_type msg)
  * You must not call this function with disabled interrupts, from a
  * hardware interrupt handler, nor from a bottom half handler.
  */
-int smp_call_function_on_cpu(void (*func)(void *info), void *info, int retry,
-                             int wait, cpumask_t callmap)
+static int smp_call_function_on_cpu(void (*func)(void *info), void *info,
+                                    int retry, int wait, cpumask_t callmap)
 {
         struct smp_call_struct data;
         unsigned long timeout;
@@ -454,6 +467,18 @@ void show_ipi_list(struct seq_file *p)
         seq_putc(p, '\n');
 }
 
+void show_local_irqs(struct seq_file *p)
+{
+        unsigned int cpu;
+
+        seq_printf(p, "LOC: ");
+
+        for_each_present_cpu(cpu)
+                seq_printf(p, "%10u ", irq_stat[cpu].local_timer_irqs);
+
+        seq_putc(p, '\n');
+}
+
 static void ipi_timer(struct pt_regs *regs)
 {
         int user = user_mode(regs);
@@ -464,6 +489,18 @@ static void ipi_timer(struct pt_regs *regs)
         irq_exit();
 }
 
+#ifdef CONFIG_LOCAL_TIMERS
+asmlinkage void do_local_timer(struct pt_regs *regs)
+{
+        int cpu = smp_processor_id();
+
+        if (local_timer_ack()) {
+                irq_stat[cpu].local_timer_irqs++;
+                ipi_timer(regs);
+        }
+}
+#endif
+
 /*
  * ipi_call_function - handle IPI from smp_call_function()
  *
@@ -515,7 +552,7 @@ static void ipi_cpu_stop(unsigned int cpu)
  *
  *  Bit 0 - Inter-processor function call
  */
-void do_IPI(struct pt_regs *regs)
+asmlinkage void do_IPI(struct pt_regs *regs)
 {
         unsigned int cpu = smp_processor_id();
         struct ipi_data *ipi = &per_cpu(ipi_data, cpu);
diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h
index f35d91fbe117..b8c14e936697 100644
--- a/arch/arm/lib/bitops.h
+++ b/arch/arm/lib/bitops.h
@@ -34,7 +34,7 @@
         and     r2, r0, #7
         mov     r3, #1
         mov     r3, r3, lsl r2
-        save_and_disable_irqs ip, r2
+        save_and_disable_irqs ip
         ldrb    r2, [r1, r0, lsr #3]
         \instr  r2, r2, r3
         strb    r2, [r1, r0, lsr #3]
@@ -54,7 +54,7 @@
         add     r1, r1, r0, lsr #3
         and     r3, r0, #7
         mov     r0, #1
-        save_and_disable_irqs ip, r2
+        save_and_disable_irqs ip
         ldrb    r2, [r1]
         tst     r2, r0, lsl r3
         \instr  r2, r2, r0, lsl r3
diff --git a/arch/arm/mach-aaec2000/clock.c b/arch/arm/mach-aaec2000/clock.c
index 99e019169dda..0340ddc4824e 100644
--- a/arch/arm/mach-aaec2000/clock.c
+++ b/arch/arm/mach-aaec2000/clock.c
@@ -14,6 +14,7 @@
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/err.h>
+#include <linux/string.h>
 
 #include <asm/semaphore.h>
 #include <asm/hardware/clock.h>
diff --git a/arch/arm/mach-epxa10db/mm.c b/arch/arm/mach-epxa10db/mm.c
index e8832d0910ee..cfd0d2182d44 100644
--- a/arch/arm/mach-epxa10db/mm.c
+++ b/arch/arm/mach-epxa10db/mm.c
@@ -25,6 +25,7 @@
 #include <asm/hardware.h>
 #include <asm/io.h>
 #include <asm/sizes.h>
+#include <asm/page.h>
  
 #include <asm/mach/map.h>
 
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index a1b153d1626c..a4bafee77a06 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -420,8 +420,7 @@ static int impd1_probe(struct lm_device *dev)
  free_impd1:
         if (impd1 && impd1->base)
                 iounmap(impd1->base);
-        if (impd1)
-                kfree(impd1);
+        kfree(impd1);
  release_lm:
         release_mem_region(dev->resource.start, SZ_4K);
         return ret;
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index df140962bb0f..6851abaf5524 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -84,63 +84,54 @@ static struct map_desc ixp2000_io_desc[] __initdata = {
                 .virtual        = IXP2000_CAP_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
                 .length         = IXP2000_CAP_SIZE,
-                .type           = MT_DEVICE
+                .type           = MT_IXP2000_DEVICE,
         }, {
                 .virtual        = IXP2000_INTCTL_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
                 .length         = IXP2000_INTCTL_SIZE,
-                .type           = MT_DEVICE
+                .type           = MT_IXP2000_DEVICE,
         }, {
                 .virtual        = IXP2000_PCI_CREG_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
                 .length         = IXP2000_PCI_CREG_SIZE,
-                .type           = MT_DEVICE
+                .type           = MT_IXP2000_DEVICE,
         }, {
                 .virtual        = IXP2000_PCI_CSR_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
                 .length         = IXP2000_PCI_CSR_SIZE,
-                .type           = MT_DEVICE
+                .type           = MT_IXP2000_DEVICE,
         }, {
                 .virtual        = IXP2000_MSF_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
                 .length         = IXP2000_MSF_SIZE,
-                .type           = MT_DEVICE
+                .type           = MT_IXP2000_DEVICE,
         }, {
                 .virtual        = IXP2000_PCI_IO_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
                 .length         = IXP2000_PCI_IO_SIZE,
-                .type           = MT_DEVICE
+                .type           = MT_IXP2000_DEVICE,
         }, {
                 .virtual        = IXP2000_PCI_CFG0_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
                 .length         = IXP2000_PCI_CFG0_SIZE,
-                .type           = MT_DEVICE
+                .type           = MT_IXP2000_DEVICE,
         }, {
                 .virtual        = IXP2000_PCI_CFG1_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
                 .length         = IXP2000_PCI_CFG1_SIZE,
-                .type           = MT_DEVICE
+                .type           = MT_IXP2000_DEVICE,
         }
 };
 
 void __init ixp2000_map_io(void)
 {
-        extern unsigned int processor_id;
-
         /*
-         * On IXP2400 CPUs we need to use MT_IXP2000_DEVICE for
-         * tweaking the PMDs so XCB=101. On IXP2800s we use the normal
-         * PMD flags.
+         * On IXP2400 CPUs we need to use MT_IXP2000_DEVICE so that
+         * XCB=101 (to avoid triggering erratum #66), and given that
+         * this mode speeds up I/O accesses and we have write buffer
+         * flushes in the right places anyway, it doesn't hurt to use
+         * XCB=101 for all IXP2000s.
          */
-        if ((processor_id & 0xfffffff0) == 0x69054190) {
-                int i;
-
-                printk(KERN_INFO "Enabling IXP2400 erratum #66 workaround\n");
-
-                for(i=0;i<ARRAY_SIZE(ixp2000_io_desc);i++)
-                        ixp2000_io_desc[i].type = MT_IXP2000_DEVICE;
-        }
-
         iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
 
         /* Set slowport to 8-bit mode.  */
diff --git a/arch/arm/mach-ixp2000/uengine.c b/arch/arm/mach-ixp2000/uengine.c
index 43e234349d4a..ec4e007a22ef 100644
--- a/arch/arm/mach-ixp2000/uengine.c
+++ b/arch/arm/mach-ixp2000/uengine.c
@@ -91,8 +91,8 @@ EXPORT_SYMBOL(ixp2000_uengine_csr_write);
 
 void ixp2000_uengine_reset(u32 uengine_mask)
 {
-        ixp2000_reg_write(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask);
-        ixp2000_reg_write(IXP2000_RESET1, 0);
+        ixp2000_reg_wrb(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask);
+        ixp2000_reg_wrb(IXP2000_RESET1, 0);
 }
 EXPORT_SYMBOL(ixp2000_uengine_reset);
 
@@ -452,21 +452,20 @@ static int __init ixp2000_uengine_init(void)
         /*
          * Reset microengines.
          */
-        ixp2000_reg_write(IXP2000_RESET1, ixp2000_uengine_mask);
-        ixp2000_reg_write(IXP2000_RESET1, 0);
+        ixp2000_uengine_reset(ixp2000_uengine_mask);
 
         /*
          * Synchronise timestamp counters across all microengines.
          */
         value = ixp2000_reg_read(IXP2000_MISC_CONTROL);
-        ixp2000_reg_write(IXP2000_MISC_CONTROL, value & ~0x80);
+        ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value & ~0x80);
         for (uengine = 0; uengine < 32; uengine++) {
                 if (ixp2000_uengine_mask & (1 << uengine)) {
                         ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
                         ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
                 }
         }
-        ixp2000_reg_write(IXP2000_MISC_CONTROL, value | 0x80);
+        ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value | 0x80);
 
         return 0;
 }
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 2b544363c078..9795da270e3a 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -427,7 +427,7 @@ void __init ixp4xx_pci_preinit(void)
 #ifdef __ARMEB__
         *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
 #else
-        *PCI_CSR = PCI_CSR_IC;
+        *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE;
 #endif
 
         pr_debug("DONE\n");
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c
index be283cda63dd..399010c14036 100644
--- a/arch/arm/mach-omap1/leds-h2p2-debug.c
+++ b/arch/arm/mach-omap1/leds-h2p2-debug.c
@@ -13,7 +13,6 @@
 #include <linux/init.h>
 #include <linux/kernel_stat.h>
 #include <linux/sched.h>
-#include <linux/version.h>
 
 #include <asm/io.h>
 #include <asm/hardware.h>
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 3e5f69bb5ac4..b380a438e68f 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -27,7 +27,8 @@ config PXA_SHARPSL
           Say Y here if you intend to run this kernel on a
           Sharp Zaurus SL-5600 (Poodle), SL-C700 (Corgi),
           SL-C750 (Shepherd), SL-C760 (Husky), SL-C1000 (Akita),
-          SL-C3000 (Spitz) or SL-C3100 (Borzoi) handheld computer.
+          SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa)
+          handheld computer.
 
 endchoice
 
@@ -37,7 +38,7 @@ choice
         prompt "Select target Sharp Zaurus device range"
 
 config PXA_SHARPSL_25x
-        bool "Sharp PXA25x models (SL-5600 and SL-C7xx)"
+        bool "Sharp PXA25x models (SL-5600, SL-C7xx and SL-C6000x)"
         select PXA25x
 
 config PXA_SHARPSL_27x
@@ -80,6 +81,10 @@ config MACH_BORZOI
         depends PXA_SHARPSL_27x
         select PXA_SHARP_Cxx00
 
+config MACH_TOSA
+        bool "Enable Sharp SL-6000x (Tosa) Support"
+        depends PXA_SHARPSL
+
 config PXA25x
         bool
         help
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index f609a0f232cb..8bc72d07cea8 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
 obj-$(CONFIG_PXA_SHARP_C7xx)    += corgi.o corgi_ssp.o corgi_lcd.o ssp.o
 obj-$(CONFIG_PXA_SHARP_Cxx00)   += spitz.o corgi_ssp.o corgi_lcd.o ssp.o
 obj-$(CONFIG_MACH_POODLE)       += poodle.o
+obj-$(CONFIG_MACH_TOSA)         += tosa.o
 
 # Support for blinky lights
 led-y := leds.o
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index eb5f6d744a4a..100fb31b5156 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -62,6 +62,37 @@ static struct scoop_config corgi_scoop_setup = {
         .io_out         = CORGI_SCOOP_IO_OUT,
 };
 
+struct platform_device corgiscoop_device = {
+        .name           = "sharp-scoop",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &corgi_scoop_setup,
+        },
+        .num_resources  = ARRAY_SIZE(corgi_scoop_resources),
+        .resource       = corgi_scoop_resources,
+};
+
+static void corgi_pcmcia_init(void)
+{
+        /* Setup default state of GPIO outputs
+           before we enable them as outputs. */
+        GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
+                GPIO_bit(GPIO49_nPWE) | GPIO_bit(GPIO50_nPIOR) |
+                GPIO_bit(GPIO51_nPIOW) | GPIO_bit(GPIO52_nPCE_1) |
+                GPIO_bit(GPIO53_nPCE_2);
+
+        pxa_gpio_mode(GPIO48_nPOE_MD);
+        pxa_gpio_mode(GPIO49_nPWE_MD);
+        pxa_gpio_mode(GPIO50_nPIOR_MD);
+        pxa_gpio_mode(GPIO51_nPIOW_MD);
+        pxa_gpio_mode(GPIO55_nPREG_MD);
+        pxa_gpio_mode(GPIO56_nPWAIT_MD);
+        pxa_gpio_mode(GPIO57_nIOIS16_MD);
+        pxa_gpio_mode(GPIO52_nPCE_1_MD);
+        pxa_gpio_mode(GPIO53_nPCE_2_MD);
+        pxa_gpio_mode(GPIO54_pSKTSEL_MD);
+}
+
 static struct scoop_pcmcia_dev corgi_pcmcia_scoop[] = {
 {
         .dev        = &corgiscoop_device.dev,
@@ -71,16 +102,14 @@ static struct scoop_pcmcia_dev corgi_pcmcia_scoop[] = {
 },
 };
 
-struct platform_device corgiscoop_device = {
-        .name           = "sharp-scoop",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &corgi_scoop_setup,
-        },
-        .num_resources  = ARRAY_SIZE(corgi_scoop_resources),
-        .resource       = corgi_scoop_resources,
+static struct scoop_pcmcia_config corgi_pcmcia_config = {
+        .devs         = &corgi_pcmcia_scoop[0],
+        .num_devs     = 1,
+        .pcmcia_init  = corgi_pcmcia_init,
 };
 
+EXPORT_SYMBOL(corgiscoop_device);
+
 
 /*
  * Corgi SSP Device
@@ -294,8 +323,7 @@ static void __init corgi_init(void)
         pxa_set_mci_info(&corgi_mci_platform_data);
         pxa_set_ficp_info(&corgi_ficp_platform_data);
 
-        scoop_num = 1;
-        scoop_devs = &corgi_pcmcia_scoop[0];
+        platform_scoop_config = &corgi_pcmcia_config;
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c
index 54162ba95414..698eb06545c4 100644
--- a/arch/arm/mach-pxa/corgi_lcd.c
+++ b/arch/arm/mach-pxa/corgi_lcd.c
@@ -19,6 +19,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/module.h>
+#include <linux/string.h>
 #include <asm/arch/akita.h>
 #include <asm/arch/corgi.h>
 #include <asm/arch/hardware.h>
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index ac4dd4336160..f74b9af112dc 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -12,6 +12,7 @@
  */
 #include <linux/config.h>
 #include <linux/init.h>
+#include <linux/module.h>
 #include <linux/suspend.h>
 #include <linux/errno.h>
 #include <linux/time.h>
@@ -19,6 +20,7 @@
 #include <asm/hardware.h>
 #include <asm/memory.h>
 #include <asm/system.h>
+#include <asm/arch/pm.h>
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/lubbock.h>
 #include <asm/mach/time.h>
@@ -72,7 +74,7 @@ enum {	SLEEP_SAVE_START = 0,
 };
 
 
-static int pxa_pm_enter(suspend_state_t state)
+int pxa_pm_enter(suspend_state_t state)
 {
         unsigned long sleep_save[SLEEP_SAVE_SIZE];
         unsigned long checksum = 0;
@@ -191,6 +193,8 @@ static int pxa_pm_enter(suspend_state_t state)
         return 0;
 }
 
+EXPORT_SYMBOL_GPL(pxa_pm_enter);
+
 unsigned long sleep_phys_sp(void *sp)
 {
         return virt_to_phys(sp);
@@ -199,21 +203,25 @@ unsigned long sleep_phys_sp(void *sp)
 /*
  * Called after processes are frozen, but before we shut down devices.
  */
-static int pxa_pm_prepare(suspend_state_t state)
+int pxa_pm_prepare(suspend_state_t state)
 {
         extern int pxa_cpu_pm_prepare(suspend_state_t state);
 
         return pxa_cpu_pm_prepare(state);
 }
 
+EXPORT_SYMBOL_GPL(pxa_pm_prepare);
+
 /*
  * Called after devices are re-setup, but before processes are thawed.
  */
-static int pxa_pm_finish(suspend_state_t state)
+int pxa_pm_finish(suspend_state_t state)
 {
         return 0;
 }
 
+EXPORT_SYMBOL_GPL(pxa_pm_finish);
+
 /*
  * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
  */
@@ -230,4 +238,4 @@ static int __init pxa_pm_init(void)
         return 0;
 }
 
-late_initcall(pxa_pm_init);
+device_initcall(pxa_pm_init);
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index ad6a13f95a62..eef3de26ad37 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -65,6 +65,27 @@ struct platform_device poodle_scoop_device = {
         .resource       = poodle_scoop_resources,
 };
 
+static void poodle_pcmcia_init(void)
+{
+        /* Setup default state of GPIO outputs
+           before we enable them as outputs. */
+        GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
+                GPIO_bit(GPIO49_nPWE) | GPIO_bit(GPIO50_nPIOR) |
+                GPIO_bit(GPIO51_nPIOW) | GPIO_bit(GPIO52_nPCE_1) |
+                GPIO_bit(GPIO53_nPCE_2);
+
+        pxa_gpio_mode(GPIO48_nPOE_MD);
+        pxa_gpio_mode(GPIO49_nPWE_MD);
+        pxa_gpio_mode(GPIO50_nPIOR_MD);
+        pxa_gpio_mode(GPIO51_nPIOW_MD);
+        pxa_gpio_mode(GPIO55_nPREG_MD);
+        pxa_gpio_mode(GPIO56_nPWAIT_MD);
+        pxa_gpio_mode(GPIO57_nIOIS16_MD);
+        pxa_gpio_mode(GPIO52_nPCE_1_MD);
+        pxa_gpio_mode(GPIO53_nPCE_2_MD);
+        pxa_gpio_mode(GPIO54_pSKTSEL_MD);
+}
+
 static struct scoop_pcmcia_dev poodle_pcmcia_scoop[] = {
 {
         .dev        = &poodle_scoop_device.dev,
@@ -74,6 +95,14 @@ static struct scoop_pcmcia_dev poodle_pcmcia_scoop[] = {
 },
 };
 
+static struct scoop_pcmcia_config poodle_pcmcia_config = {
+        .devs         = &poodle_pcmcia_scoop[0],
+        .num_devs     = 1,
+        .pcmcia_init  = poodle_pcmcia_init,
+};
+
+EXPORT_SYMBOL(poodle_scoop_device);
+
 
 /* LoCoMo device */
 static struct resource locomo_resources[] = {
@@ -268,8 +297,7 @@ static void __init poodle_init(void)
         pxa_set_mci_info(&poodle_mci_platform_data);
         pxa_set_ficp_info(&poodle_ficp_platform_data);
 
-        scoop_num = 1;
-        scoop_devs = &poodle_pcmcia_scoop[0];
+        platform_scoop_config = &poodle_pcmcia_config;
 
         ret = platform_add_devices(devices, ARRAY_SIZE(devices));
         if (ret) {
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 6c6878cd2207..4e9a699ee428 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -104,6 +104,66 @@ struct platform_device spitzscoop2_device = {
         .resource       = spitz_scoop2_resources,
 };
 
+#define SPITZ_PWR_SD 0x01
+#define SPITZ_PWR_CF 0x02
+
+/* Power control is shared with between one of the CF slots and SD */
+static void spitz_card_pwr_ctrl(int device, unsigned short new_cpr)
+{
+        unsigned short cpr = read_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR);
+
+        if (new_cpr & 0x0007) {
+                set_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_CF_POWER);
+                if (!(cpr & 0x0002) && !(cpr & 0x0004))
+                        mdelay(5);
+                if (device == SPITZ_PWR_CF)
+                        cpr |= 0x0002;
+                if (device == SPITZ_PWR_SD)
+                        cpr |= 0x0004;
+                write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr);
+        } else {
+                if (device == SPITZ_PWR_CF)
+                        cpr &= ~0x0002;
+                if (device == SPITZ_PWR_SD)
+                        cpr &= ~0x0004;
+                write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr);
+                if (!(cpr & 0x0002) && !(cpr & 0x0004)) {
+                        mdelay(1);
+                        reset_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_CF_POWER);
+                }
+        }
+}
+
+static void spitz_pcmcia_init(void)
+{
+        /* Setup default state of GPIO outputs
+           before we enable them as outputs. */
+        GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
+                GPIO_bit(GPIO49_nPWE) | GPIO_bit(GPIO50_nPIOR) |
+                GPIO_bit(GPIO51_nPIOW) | GPIO_bit(GPIO54_nPCE_2);
+        GPSR(GPIO85_nPCE_1) = GPIO_bit(GPIO85_nPCE_1);
+
+        pxa_gpio_mode(GPIO48_nPOE_MD);
+        pxa_gpio_mode(GPIO49_nPWE_MD);
+        pxa_gpio_mode(GPIO50_nPIOR_MD);
+        pxa_gpio_mode(GPIO51_nPIOW_MD);
+        pxa_gpio_mode(GPIO55_nPREG_MD);
+        pxa_gpio_mode(GPIO56_nPWAIT_MD);
+        pxa_gpio_mode(GPIO57_nIOIS16_MD);
+        pxa_gpio_mode(GPIO85_nPCE_1_MD);
+        pxa_gpio_mode(GPIO54_nPCE_2_MD);
+        pxa_gpio_mode(GPIO104_pSKTSEL_MD);
+}
+
+static void spitz_pcmcia_pwr(struct device *scoop, unsigned short cpr, int nr)
+{
+        /* Only need to override behaviour for slot 0 */
+        if (nr == 0)
+                spitz_card_pwr_ctrl(SPITZ_PWR_CF, cpr);
+        else
+                write_scoop_reg(scoop, SCOOP_CPR, cpr);
+}
+
 static struct scoop_pcmcia_dev spitz_pcmcia_scoop[] = {
 {
         .dev        = &spitzscoop_device.dev,
@@ -117,6 +177,16 @@ static struct scoop_pcmcia_dev spitz_pcmcia_scoop[] = {
 },
 };
 
+static struct scoop_pcmcia_config spitz_pcmcia_config = {
+        .devs         = &spitz_pcmcia_scoop[0],
+        .num_devs     = 2,
+        .pcmcia_init  = spitz_pcmcia_init,
+        .power_ctrl   = spitz_pcmcia_pwr,
+};
+
+EXPORT_SYMBOL(spitzscoop_device);
+EXPORT_SYMBOL(spitzscoop2_device);
+
 
 /*
  * Spitz SSP Device
@@ -235,27 +305,14 @@ static int spitz_mci_init(struct device *dev, irqreturn_t (*spitz_detect_int)(in
         return 0;
 }
 
-/* Power control is shared with one of the CF slots so we have a mess */
 static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
 {
         struct pxamci_platform_data* p_d = dev->platform_data;
 
-        unsigned short cpr = read_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR);
-
-        if (( 1 << vdd) & p_d->ocr_mask) {
-                /* printk(KERN_DEBUG "%s: on\n", __FUNCTION__); */
-                set_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_CF_POWER);
-                mdelay(2);
-                write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | 0x04);
-        } else {
-                /* printk(KERN_DEBUG "%s: off\n", __FUNCTION__); */
-                write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr & ~0x04);
-
-                if (!(cpr | 0x02)) {
-                        mdelay(1);
-                        reset_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_CF_POWER);
-                }
-        }
+        if (( 1 << vdd) & p_d->ocr_mask)
+                spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0004);
+        else
+                spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0000);
 }
 
 static int spitz_mci_get_ro(struct device *dev)
@@ -351,8 +408,8 @@ static void __init common_init(void)
 
 static void __init spitz_init(void)
 {
-        scoop_num = 2;
-        scoop_devs = &spitz_pcmcia_scoop[0];
+        platform_scoop_config = &spitz_pcmcia_config;
+
         spitz_bl_machinfo.set_bl_intensity = spitz_bl_set_intensity;
 
         common_init();
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 7dad3f1465e0..b9b2057349eb 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -132,11 +132,13 @@ static void __init pxa_timer_init(void)
         tv.tv_sec = pxa_get_rtc_time();
         do_settimeofday(&tv);
 
-        OSMR0 = 0;              /* set initial match at 0 */
+        OIER = 0;               /* disable any timer interrupts */
+        OSCR = LATCH*2;         /* push OSCR out of the way */
+        OSMR0 = LATCH;          /* set initial match */
         OSSR = 0xf;             /* clear status on all timers */
         setup_irq(IRQ_OST0, &pxa_timer_irq);
-        OIER |= OIER_E0;        /* enable match on timer 0 to cause interrupts */
-        OSCR = 0;               /* initialize free-running timer, force first match */
+        OIER = OIER_E0;         /* enable match on timer 0 to cause interrupts */
+        OSCR = 0;               /* initialize free-running timer */
 }
 
 #ifdef CONFIG_NO_IDLE_HZ
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
new file mode 100644
index 000000000000..c312054dfb88
--- /dev/null
+++ b/arch/arm/mach-pxa/tosa.c
@@ -0,0 +1,306 @@
+/*
+ *  Support for Sharp SL-C6000x PDAs
+ *  Model: (Tosa)
+ *
+ *  Copyright (c) 2005 Dirk Opfer
+ *
+ *      Based on code written by Sharp/Lineo for 2.4 kernels
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/major.h>
+#include <linux/fs.h>
+#include <linux/interrupt.h>
+#include <linux/mmc/host.h>
+
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/mach-types.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/arch/irda.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/udc.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/irq.h>
+#include <asm/arch/tosa.h>
+
+#include <asm/hardware/scoop.h>
+#include <asm/mach/sharpsl_param.h>
+
+#include "generic.h"
+
+
+/*
+ * SCOOP Device
+ */
+static struct resource tosa_scoop_resources[] = {
+        [0] = {
+                .start  = TOSA_CF_PHYS,
+                .end    = TOSA_CF_PHYS + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct scoop_config tosa_scoop_setup = {
+        .io_dir         = TOSA_SCOOP_IO_DIR,
+        .io_out         = TOSA_SCOOP_IO_OUT,
+
+};
+
+struct platform_device tosascoop_device = {
+        .name           = "sharp-scoop",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &tosa_scoop_setup,
+        },
+        .num_resources  = ARRAY_SIZE(tosa_scoop_resources),
+        .resource       = tosa_scoop_resources,
+};
+
+
+/*
+ * SCOOP Device Jacket
+ */
+static struct resource tosa_scoop_jc_resources[] = {
+        [0] = {
+                .start          = TOSA_SCOOP_PHYS + 0x40,
+                .end            = TOSA_SCOOP_PHYS + 0xfff,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct scoop_config tosa_scoop_jc_setup = {
+        .io_dir         = TOSA_SCOOP_JC_IO_DIR,
+        .io_out         = TOSA_SCOOP_JC_IO_OUT,
+};
+
+struct platform_device tosascoop_jc_device = {
+        .name           = "sharp-scoop",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &tosa_scoop_jc_setup,
+                .parent         = &tosascoop_device.dev,
+        },
+        .num_resources  = ARRAY_SIZE(tosa_scoop_jc_resources),
+        .resource       = tosa_scoop_jc_resources,
+};
+
+/*
+ * PCMCIA
+ */
+static struct scoop_pcmcia_dev tosa_pcmcia_scoop[] = {
+{
+        .dev        = &tosascoop_device.dev,
+        .irq        = TOSA_IRQ_GPIO_CF_IRQ,
+        .cd_irq     = TOSA_IRQ_GPIO_CF_CD,
+        .cd_irq_str = "PCMCIA0 CD",
+},{
+        .dev        = &tosascoop_jc_device.dev,
+        .irq        = TOSA_IRQ_GPIO_JC_CF_IRQ,
+        .cd_irq     = -1,
+},
+};
+
+static void tosa_pcmcia_init(void)
+{
+        /* Setup default state of GPIO outputs
+           before we enable them as outputs. */
+        GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
+                GPIO_bit(GPIO49_nPWE) | GPIO_bit(GPIO50_nPIOR) |
+                GPIO_bit(GPIO51_nPIOW) | GPIO_bit(GPIO52_nPCE_1) |
+                GPIO_bit(GPIO53_nPCE_2);
+
+        pxa_gpio_mode(GPIO48_nPOE_MD);
+        pxa_gpio_mode(GPIO49_nPWE_MD);
+        pxa_gpio_mode(GPIO50_nPIOR_MD);
+        pxa_gpio_mode(GPIO51_nPIOW_MD);
+        pxa_gpio_mode(GPIO55_nPREG_MD);
+        pxa_gpio_mode(GPIO56_nPWAIT_MD);
+        pxa_gpio_mode(GPIO57_nIOIS16_MD);
+        pxa_gpio_mode(GPIO52_nPCE_1_MD);
+        pxa_gpio_mode(GPIO53_nPCE_2_MD);
+        pxa_gpio_mode(GPIO54_pSKTSEL_MD);
+}
+
+static struct scoop_pcmcia_config tosa_pcmcia_config = {
+        .devs         = &tosa_pcmcia_scoop[0],
+        .num_devs     = 2,
+        .pcmcia_init  = tosa_pcmcia_init,
+};
+
+/*
+ * USB Device Controller
+ */
+static void tosa_udc_command(int cmd)
+{
+        switch(cmd)     {
+                case PXA2XX_UDC_CMD_CONNECT:
+                        set_scoop_gpio(&tosascoop_jc_device.dev,TOSA_SCOOP_JC_USB_PULLUP);
+                        break;
+                case PXA2XX_UDC_CMD_DISCONNECT:
+                        reset_scoop_gpio(&tosascoop_jc_device.dev,TOSA_SCOOP_JC_USB_PULLUP);
+                        break;
+        }
+}
+
+static int tosa_udc_is_connected(void)
+{
+        return ((GPLR(TOSA_GPIO_USB_IN) & GPIO_bit(TOSA_GPIO_USB_IN)) == 0);
+}
+
+
+static struct pxa2xx_udc_mach_info udc_info __initdata = {
+        .udc_command            = tosa_udc_command,
+        .udc_is_connected       = tosa_udc_is_connected,
+};
+
+/*
+ * MMC/SD Device
+ */
+static struct pxamci_platform_data tosa_mci_platform_data;
+
+static int tosa_mci_init(struct device *dev, irqreturn_t (*tosa_detect_int)(int, void *, struct pt_regs *), void *data)
+{
+        int err;
+
+        /* setup GPIO for PXA25x MMC controller */
+        pxa_gpio_mode(GPIO6_MMCCLK_MD);
+        pxa_gpio_mode(GPIO8_MMCCS0_MD);
+        pxa_gpio_mode(TOSA_GPIO_nSD_DETECT | GPIO_IN);
+
+        tosa_mci_platform_data.detect_delay = msecs_to_jiffies(250);
+
+        err = request_irq(TOSA_IRQ_GPIO_nSD_DETECT, tosa_detect_int, SA_INTERRUPT,
+                                "MMC/SD card detect", data);
+        if (err) {
+                printk(KERN_ERR "tosa_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
+                return -1;
+        }
+
+        set_irq_type(TOSA_IRQ_GPIO_nSD_DETECT, IRQT_BOTHEDGE);
+
+        return 0;
+}
+
+static void tosa_mci_setpower(struct device *dev, unsigned int vdd)
+{
+        struct pxamci_platform_data* p_d = dev->platform_data;
+
+        if (( 1 << vdd) & p_d->ocr_mask) {
+                set_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_PWR_ON);
+        } else {
+                reset_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_PWR_ON);
+        }
+}
+
+static int tosa_mci_get_ro(struct device *dev)
+{
+        return (read_scoop_reg(&tosascoop_device.dev, SCOOP_GPWR)&TOSA_SCOOP_SD_WP);
+}
+
+static void tosa_mci_exit(struct device *dev, void *data)
+{
+        free_irq(TOSA_IRQ_GPIO_nSD_DETECT, data);
+}
+
+static struct pxamci_platform_data tosa_mci_platform_data = {
+        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
+        .init           = tosa_mci_init,
+        .get_ro         = tosa_mci_get_ro,
+        .setpower       = tosa_mci_setpower,
+        .exit           = tosa_mci_exit,
+};
+
+/*
+ * Irda
+ */
+static void tosa_irda_transceiver_mode(struct device *dev, int mode)
+{
+        if (mode & IR_OFF) {
+                reset_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_IR_POWERDWN);
+                pxa_gpio_mode(GPIO47_STTXD|GPIO_DFLT_LOW);
+                pxa_gpio_mode(GPIO47_STTXD|GPIO_OUT);
+        } else {
+                pxa_gpio_mode(GPIO47_STTXD_MD);
+                set_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_IR_POWERDWN);
+        }
+}
+
+static struct pxaficp_platform_data tosa_ficp_platform_data = {
+        .transceiver_cap  = IR_SIRMODE | IR_OFF,
+        .transceiver_mode = tosa_irda_transceiver_mode,
+};
+
+/*
+ * Tosa Keyboard
+ */
+static struct platform_device tosakbd_device = {
+        .name           = "tosa-keyboard",
+        .id             = -1,
+};
+
+static struct platform_device *devices[] __initdata = {
+        &tosascoop_device,
+        &tosascoop_jc_device,
+        &tosakbd_device,
+};
+
+static void __init tosa_init(void)
+{
+        pxa_gpio_mode(TOSA_GPIO_ON_RESET | GPIO_IN);
+        pxa_gpio_mode(TOSA_GPIO_TC6393_INT | GPIO_IN);
+        pxa_gpio_mode(TOSA_GPIO_USB_IN | GPIO_IN);
+
+        /* setup sleep mode values */
+        PWER  = 0x00000002;
+        PFER  = 0x00000000;
+        PRER  = 0x00000002;
+        PGSR0 = 0x00000000;
+        PGSR1 = 0x00FF0002;
+        PGSR2 = 0x00014000;
+        PCFR |= PCFR_OPDE;
+
+        /* enable batt_fault */
+        PMCR = 0x01;
+
+        pxa_set_mci_info(&tosa_mci_platform_data);
+        pxa_set_udc_info(&udc_info);
+        pxa_set_ficp_info(&tosa_ficp_platform_data);
+        platform_scoop_config = &tosa_pcmcia_config;
+
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+static void __init fixup_tosa(struct machine_desc *desc,
+                struct tag *tags, char **cmdline, struct meminfo *mi)
+{
+        sharpsl_save_param();
+        mi->nr_banks=1;
+        mi->bank[0].start = 0xa0000000;
+        mi->bank[0].node = 0;
+        mi->bank[0].size = (64*1024*1024);
+}
+
+MACHINE_START(TOSA, "SHARP Tosa")
+        .phys_ram       = 0xa0000000,
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .fixup          = fixup_tosa,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa_init_irq,
+        .init_machine   = tosa_init,
+        .timer          = &pxa_timer,
+MACHINE_END
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index 4b63dc9eabfe..129976866d47 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -8,4 +8,13 @@ config MACH_REALVIEW_EB
         help
           Include support for the ARM(R) RealView Emulation Baseboard platform.
 
+config REALVIEW_MPCORE
+        bool "Support MPcore tile"
+        depends on MACH_REALVIEW_EB
+        help
+          Enable support for the MPCore tile on the Realview platform.
+          Since there are device address and interrupt differences, a
+          kernel built with this option enabled is not compatible with
+          other tiles.
+
 endmenu
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index 8d37ea1605fd..36e76ba937fc 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -4,3 +4,6 @@
 
 obj-y                                   := core.o clock.o
 obj-$(CONFIG_MACH_REALVIEW_EB)          += realview_eb.o
+obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
+obj-$(CONFIG_LOCAL_TIMERS)              += localtimer.o
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 482eb512ebe8..e2c6fa23d3cd 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -550,6 +550,11 @@ static irqreturn_t realview_timer_interrupt(int irq, void *dev_id, struct pt_reg
 
         timer_tick(regs);
 
+#if defined(CONFIG_SMP) && !defined(CONFIG_LOCAL_TIMERS)
+        smp_send_timer();
+        update_process_times(user_mode(regs));
+#endif
+
         write_sequnlock(&xtime_lock);
 
         return IRQ_HANDLED;
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 575599db74db..d83e8bad2038 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -23,6 +23,7 @@
 #define __ASM_ARCH_REALVIEW_H
 
 #include <asm/hardware/amba.h>
+#include <asm/leds.h>
 #include <asm/io.h>
 
 #define __io_address(n)         __io(IO_ADDRESS(n))
diff --git a/arch/arm/mach-realview/headsmp.S b/arch/arm/mach-realview/headsmp.S
new file mode 100644
index 000000000000..4075473cf68a
--- /dev/null
+++ b/arch/arm/mach-realview/headsmp.S
@@ -0,0 +1,39 @@
+/*
+ *  linux/arch/arm/mach-realview/headsmp.S
+ *
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+        __INIT
+
+/*
+ * Realview specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(realview_secondary_startup)
+        mrc     p15, 0, r0, c0, c0, 5
+        and     r0, r0, #15
+        adr     r4, 1f
+        ldmia   r4, {r5, r6}
+        sub     r4, r4, r5
+        add     r6, r6, r4
+pen:    ldr     r7, [r6]
+        cmp     r7, r0
+        bne     pen
+
+        /*
+         * we've been released from the holding pen: secondary_stack
+         * should now contain the SVC stack for this core
+         */
+        b       secondary_startup
+
+1:      .long   .
+        .long   pen_release
diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
new file mode 100644
index 000000000000..09748cbcd10e
--- /dev/null
+++ b/arch/arm/mach-realview/hotplug.c
@@ -0,0 +1,138 @@
+/*
+ *  linux/arch/arm/mach-realview/hotplug.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <linux/completion.h>
+
+extern volatile int pen_release;
+
+static DECLARE_COMPLETION(cpu_killed);
+
+static inline void cpu_enter_lowpower(void)
+{
+        unsigned int v;
+
+        asm volatile(   "mcr    p15, 0, %1, c7, c14, 0\n"
+        "       mcr     p15, 0, %1, c7, c5, 0\n"
+        "       mcr     p15, 0, %1, c7, c10, 4\n"
+        /*
+         * Turn off coherency
+         */
+        "       mrc     p15, 0, %0, c1, c0, 1\n"
+        "       bic     %0, %0, #0x20\n"
+        "       mcr     p15, 0, %0, c1, c0, 1\n"
+        "       mrc     p15, 0, %0, c1, c0, 0\n"
+        "       bic     %0, %0, #0x04\n"
+        "       mcr     p15, 0, %0, c1, c0, 0\n"
+          : "=&r" (v)
+          : "r" (0)
+          : "cc");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+        unsigned int v;
+
+        asm volatile(   "mrc    p15, 0, %0, c1, c0, 0\n"
+        "       orr     %0, %0, #0x04\n"
+        "       mcr     p15, 0, %0, c1, c0, 0\n"
+        "       mrc     p15, 0, %0, c1, c0, 1\n"
+        "       orr     %0, %0, #0x20\n"
+        "       mcr     p15, 0, %0, c1, c0, 1\n"
+          : "=&r" (v)
+          :
+          : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu)
+{
+        /*
+         * there is no power-control hardware on this platform, so all
+         * we can do is put the core into WFI; this is safe as the calling
+         * code will have already disabled interrupts
+         */
+        for (;;) {
+                /*
+                 * here's the WFI
+                 */
+                asm(".word      0xe320f003\n"
+                    :
+                    :
+                    : "memory", "cc");
+
+                if (pen_release == cpu) {
+                        /*
+                         * OK, proper wakeup, we're done
+                         */
+                        break;
+                }
+
+                /*
+                 * getting here, means that we have come out of WFI without
+                 * having been woken up - this shouldn't happen
+                 *
+                 * The trouble is, letting people know about this is not really
+                 * possible, since we are currently running incoherently, and
+                 * therefore cannot safely call printk() or anything else
+                 */
+#ifdef DEBUG
+                printk("CPU%u: spurious wakeup call\n", cpu);
+#endif
+        }
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+        return wait_for_completion_timeout(&cpu_killed, 5000);
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+#ifdef DEBUG
+        unsigned int this_cpu = hard_smp_processor_id();
+
+        if (cpu != this_cpu) {
+                printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
+                           this_cpu, cpu);
+                BUG();
+        }
+#endif
+
+        printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
+        complete(&cpu_killed);
+
+        /*
+         * we're ready for shutdown now, so do it
+         */
+        cpu_enter_lowpower();
+        platform_do_lowpower(cpu);
+
+        /*
+         * bring this CPU back into the world of cache
+         * coherency, and then restore interrupts
+         */
+        cpu_leave_lowpower();
+}
+
+int mach_cpu_disable(unsigned int cpu)
+{
+        /*
+         * we don't allow CPU 0 to be shutdown (it is still too special
+         * e.g. clock tick interrupts)
+         */
+        return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c
new file mode 100644
index 000000000000..5e917e37d095
--- /dev/null
+++ b/arch/arm/mach-realview/localtimer.c
@@ -0,0 +1,130 @@
+/*
+ *  linux/arch/arm/mach-realview/localtimer.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+
+#include <asm/mach/time.h>
+#include <asm/hardware/arm_twd.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include "core.h"
+
+#define TWD_BASE(cpu)   (__io_address(REALVIEW_TWD_BASE) + \
+                         ((cpu) * REALVIEW_TWD_SIZE))
+
+static unsigned long mpcore_timer_rate;
+
+/*
+ * local_timer_ack: checks for a local timer interrupt.
+ *
+ * If a local timer interrupt has occured, acknowledge and return 1.
+ * Otherwise, return 0.
+ */
+int local_timer_ack(void)
+{
+        void __iomem *base = TWD_BASE(smp_processor_id());
+
+        if (__raw_readl(base + TWD_TIMER_INTSTAT)) {
+                __raw_writel(1, base + TWD_TIMER_INTSTAT);
+                return 1;
+        }
+
+        return 0;
+}
+
+void __cpuinit local_timer_setup(unsigned int cpu)
+{
+        void __iomem *base = TWD_BASE(cpu);
+        unsigned int load, offset;
+        u64 waitjiffies;
+        unsigned int count;
+
+        /*
+         * If this is the first time round, we need to work out how fast
+         * the timer ticks
+         */
+        if (mpcore_timer_rate == 0) {
+                printk("Calibrating local timer... ");
+
+                /* Wait for a tick to start */
+                waitjiffies = get_jiffies_64() + 1;
+
+                while (get_jiffies_64() < waitjiffies)
+                        udelay(10);
+
+                /* OK, now the tick has started, let's get the timer going */
+                waitjiffies += 5;
+
+                                 /* enable, no interrupt or reload */
+                __raw_writel(0x1, base + TWD_TIMER_CONTROL);
+
+                                 /* maximum value */
+                __raw_writel(0xFFFFFFFFU, base + TWD_TIMER_COUNTER);
+
+                while (get_jiffies_64() < waitjiffies)
+                        udelay(10);
+
+                count = __raw_readl(base + TWD_TIMER_COUNTER);
+
+                mpcore_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
+
+                printk("%lu.%02luMHz.\n", mpcore_timer_rate / 1000000,
+                        (mpcore_timer_rate / 100000) % 100);
+        }
+
+        load = mpcore_timer_rate / HZ;
+
+        __raw_writel(load, base + TWD_TIMER_LOAD);
+        __raw_writel(0x7,  base + TWD_TIMER_CONTROL);
+
+        /*
+         * Now maneuver our local tick into the right part of the jiffy.
+         * Start by working out where within the tick our local timer
+         * interrupt should go.
+         */
+        offset = ((mpcore_timer_rate / HZ) / (NR_CPUS + 1)) * (cpu + 1);
+
+        /*
+         * gettimeoffset() will return a number of us since the last tick.
+         * Convert this number of us to a local timer tick count.
+         * Be careful of integer overflow whilst keeping maximum precision.
+         *
+         * with HZ=100 and 1MHz (fpga) ~ 1GHz processor:
+         * load = 1 ~ 10,000
+         * mpcore_timer_rate/10000 = 100 ~ 100,000
+         *
+         * so the multiply value will be less than 10^9 always.
+         */
+        load = (system_timer->offset() * (mpcore_timer_rate / 10000)) / 100;
+
+        /* Add on our offset to get the load value */
+        load = (load + offset) % (mpcore_timer_rate / HZ);
+
+        __raw_writel(load, base + TWD_TIMER_COUNTER);
+
+        /* Make sure our local interrupt controller has this enabled */
+        __raw_writel(1 << IRQ_LOCALTIMER,
+                     __io_address(REALVIEW_GIC_DIST_BASE) + GIC_DIST_ENABLE_SET);
+}
+
+/*
+ * take a local timer down
+ */
+void __cpuexit local_timer_stop(unsigned int cpu)
+{
+        __raw_writel(0, TWD_BASE(cpu) + TWD_TIMER_CONTROL);
+}
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
new file mode 100644
index 000000000000..0c7d4ac9a7b3
--- /dev/null
+++ b/arch/arm/mach-realview/platsmp.c
@@ -0,0 +1,200 @@
+/*
+ *  linux/arch/arm/mach-realview/platsmp.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/arm_scu.h>
+#include <asm/hardware.h>
+
+#include "core.h"
+
+extern void realview_secondary_startup(void);
+
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __cpuinitdata pen_release = -1;
+
+static unsigned int __init get_core_count(void)
+{
+        unsigned int ncores;
+
+        ncores = __raw_readl(__io_address(REALVIEW_MPCORE_SCU_BASE) + SCU_CONFIG);
+
+        return (ncores & 0x03) + 1;
+}
+
+static DEFINE_SPINLOCK(boot_lock);
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+        /*
+         * the primary core may have used a "cross call" soft interrupt
+         * to get this processor out of WFI in the BootMonitor - make
+         * sure that we are no longer being sent this soft interrupt
+         */
+        smp_cross_call_done(cpumask_of_cpu(cpu));
+
+        /*
+         * if any interrupts are already enabled for the primary
+         * core (e.g. timer irq), then they will not have been enabled
+         * for us: do so
+         */
+        gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE));
+
+        /*
+         * let the primary processor know we're out of the
+         * pen, then head off into the C entry point
+         */
+        pen_release = -1;
+
+        /*
+         * Synchronise with the boot thread.
+         */
+        spin_lock(&boot_lock);
+        spin_unlock(&boot_lock);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        unsigned long timeout;
+
+        /*
+         * set synchronisation state between this boot processor
+         * and the secondary one
+         */
+        spin_lock(&boot_lock);
+
+        /*
+         * The secondary processor is waiting to be released from
+         * the holding pen - release it, then wait for it to flag
+         * that it has been released by resetting pen_release.
+         *
+         * Note that "pen_release" is the hardware CPU ID, whereas
+         * "cpu" is Linux's internal ID.
+         */
+        pen_release = cpu;
+        flush_cache_all();
+
+        /*
+         * XXX
+         *
+         * This is a later addition to the booting protocol: the
+         * bootMonitor now puts secondary cores into WFI, so
+         * poke_milo() no longer gets the cores moving; we need
+         * to send a soft interrupt to wake the secondary core.
+         * Use smp_cross_call() for this, since there's little
+         * point duplicating the code here
+         */
+        smp_cross_call(cpumask_of_cpu(cpu));
+
+        timeout = jiffies + (1 * HZ);
+        while (time_before(jiffies, timeout)) {
+                if (pen_release == -1)
+                        break;
+
+                udelay(10);
+        }
+
+        /*
+         * now the secondary core is starting up let it run its
+         * calibrations, then wait for it to finish
+         */
+        spin_unlock(&boot_lock);
+
+        return pen_release != -1 ? -ENOSYS : 0;
+}
+
+static void __init poke_milo(void)
+{
+        extern void secondary_startup(void);
+
+        /* nobody is to be released from the pen yet */
+        pen_release = -1;
+
+        /*
+         * write the address of secondary startup into the system-wide
+         * flags register, then clear the bottom two bits, which is what
+         * BootMonitor is waiting for
+         */
+#if 1
+#define REALVIEW_SYS_FLAGSS_OFFSET 0x30
+        __raw_writel(virt_to_phys(realview_secondary_startup),
+                     __io_address(REALVIEW_SYS_BASE) +
+                     REALVIEW_SYS_FLAGSS_OFFSET);
+#define REALVIEW_SYS_FLAGSC_OFFSET 0x34
+        __raw_writel(3,
+                     __io_address(REALVIEW_SYS_BASE) +
+                     REALVIEW_SYS_FLAGSC_OFFSET);
+#endif
+
+        mb();
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+        unsigned int ncores = get_core_count();
+        unsigned int cpu = smp_processor_id();
+        int i;
+
+        /* sanity check */
+        if (ncores == 0) {
+                printk(KERN_ERR
+                       "Realview: strange CM count of 0? Default to 1\n");
+
+                ncores = 1;
+        }
+
+        if (ncores > NR_CPUS) {
+                printk(KERN_WARNING
+                       "Realview: no. of cores (%d) greater than configured "
+                       "maximum of %d - clipping\n",
+                       ncores, NR_CPUS);
+                ncores = NR_CPUS;
+        }
+
+        smp_store_cpu_info(cpu);
+
+        /*
+         * are we trying to boot more cores than exist?
+         */
+        if (max_cpus > ncores)
+                max_cpus = ncores;
+
+        /*
+         * Enable the local timer for primary CPU
+         */
+        local_timer_setup(cpu);
+
+        /*
+         * Initialise the possible/present maps.
+         * cpu_possible_map describes the set of CPUs which may be present
+         * cpu_present_map describes the set of CPUs populated
+         */
+        for (i = 0; i < max_cpus; i++) {
+                cpu_set(i, cpu_possible_map);
+                cpu_set(i, cpu_present_map);
+        }
+
+        /*
+         * Do we need any more CPUs? If so, then let them know where
+         * to start. Note that, on modern versions of MILO, the "poke"
+         * doesn't actually do anything until each individual core is
+         * sent a soft interrupt to get it out of WFI
+         */
+        if (max_cpus > 1)
+                poke_milo();
+}
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 267bb07e39b7..7dc32503fdf2 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -136,6 +136,11 @@ static struct amba_device *amba_devs[] __initdata = {
 
 static void __init gic_init_irq(void)
 {
+#ifdef CONFIG_REALVIEW_MPCORE
+        writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
+        writel(0x008003c0, __io_address(REALVIEW_SYS_BASE) + 0xd8);
+        writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
+#endif
         gic_dist_init(__io_address(REALVIEW_GIC_DIST_BASE));
         gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE));
 }
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index c796bcdd6158..0b9d7ca49ec1 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -121,6 +121,14 @@ config S3C2410_BOOT_WATCHDOG
           system resets depends on the value of PCLK. The timeout on an
           200MHz s3c2410 should be about 30 seconds.
 
+config S3C2410_BOOT_ERROR_RESET
+        bool "S3C2410 Reboot on decompression error"
+        depends on ARCH_S3C2410
+        help
+          Say y here to use the watchdog to reset the system if the
+          kernel decompressor detects an error during decompression.
+
+
 comment "S3C2410 Setup"
 
 config S3C2410_DMA
diff --git a/arch/arm/mach-s3c2410/mach-anubis.c b/arch/arm/mach-s3c2410/mach-anubis.c
index 8390b685c2b6..0f81fc0c2f7f 100644
--- a/arch/arm/mach-s3c2410/mach-anubis.c
+++ b/arch/arm/mach-s3c2410/mach-anubis.c
@@ -56,8 +56,16 @@
 static struct map_desc anubis_iodesc[] __initdata = {
   /* ISA IO areas */
 
-  { (u32)S3C24XX_VA_ISA_BYTE, 0x0,         SZ_16M, MT_DEVICE },
-  { (u32)S3C24XX_VA_ISA_WORD, 0x0,         SZ_16M, MT_DEVICE },
+  {
+        .virtual        = (u32)S3C24XX_VA_ISA_BYTE,
+        .pfn            = __phys_to_pfn(0x0),
+        .length         = SZ_4M,
+        .type           = MT_DEVICE
+  }, {
+        .virtual        = (u32)S3C24XX_VA_ISA_WORD,
+        .pfn            = __phys_to_pfn(0x0),
+        .length         = SZ_4M, MT_DEVICE
+  },
 
   /* we could possibly compress the next set down into a set of smaller tables
    * pagetables, but that would mean using an L2 section, and it still means
@@ -66,16 +74,41 @@ static struct map_desc anubis_iodesc[] __initdata = {
 
   /* CPLD control registers */
 
-  { (u32)ANUBIS_VA_CTRL1,       ANUBIS_PA_CTRL1,        SZ_4K, MT_DEVICE },
-  { (u32)ANUBIS_VA_CTRL2,       ANUBIS_PA_CTRL2,        SZ_4K, MT_DEVICE },
+  {
+        .virtual        = (u32)ANUBIS_VA_CTRL1,
+        .pfn            = __phys_to_pfn(ANUBIS_PA_CTRL1),
+        .length         = SZ_4K,
+        .type           = MT_DEVICE
+  }, {
+        .virtual        = (u32)ANUBIS_VA_CTRL2,
+        .pfn            = __phys_to_pfn(ANUBIS_PA_CTRL2),
+        .length         = SZ_4K,
+        .type           =MT_DEVICE
+  },
 
   /* IDE drives */
 
-  { (u32)ANUBIS_IDEPRI,         S3C2410_CS3,            SZ_1M, MT_DEVICE },
-  { (u32)ANUBIS_IDEPRIAUX,      S3C2410_CS3+(1<<26),    SZ_1M, MT_DEVICE },
-
-  { (u32)ANUBIS_IDESEC,         S3C2410_CS4,            SZ_1M, MT_DEVICE },
-  { (u32)ANUBIS_IDESECAUX,      S3C2410_CS4+(1<<26),    SZ_1M, MT_DEVICE },
+  {
+        .virtual        = (u32)ANUBIS_IDEPRI,
+        .pfn            = __phys_to_pfn(S3C2410_CS3),
+        .length         = SZ_1M,
+        .type           = MT_DEVICE
+  }, {
+        .virtual        = (u32)ANUBIS_IDEPRIAUX,
+        .pfn            = __phys_to_pfn(S3C2410_CS3+(1<<26)),
+        .length         = SZ_1M,
+        .type           = MT_DEVICE
+  }, {
+        .virtual        = (u32)ANUBIS_IDESEC,
+        .pfn            = __phys_to_pfn(S3C2410_CS4),
+        .length         = SZ_1M,
+        .type           = MT_DEVICE
+  }, {
+        .virtual        = (u32)ANUBIS_IDESECAUX,
+        .pfn            = __phys_to_pfn(S3C2410_CS4+(1<<26)),
+        .length         = SZ_1M,
+        .type           = MT_DEVICE
+  },
 };
 
 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 0b71c896bbd1..1be2567a7486 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -89,32 +89,63 @@
 
 /* macros to modify the physical addresses for io space */
 
-#define PA_CS2(item) ((item) + S3C2410_CS2)
-#define PA_CS3(item) ((item) + S3C2410_CS3)
-#define PA_CS4(item) ((item) + S3C2410_CS4)
-#define PA_CS5(item) ((item) + S3C2410_CS5)
+#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
+#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
+#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
+#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
 
 static struct map_desc bast_iodesc[] __initdata = {
   /* ISA IO areas */
-
-  { (u32)S3C24XX_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO),   SZ_16M, MT_DEVICE },
-  { (u32)S3C24XX_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO),   SZ_16M, MT_DEVICE },
-
-  /* we could possibly compress the next set down into a set of smaller tables
-   * pagetables, but that would mean using an L2 section, and it still means
-   * we cannot actually feed the same register to an LDR due to 16K spacing
-   */
-
+  {
+          .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
+          .pfn          = PA_CS2(BAST_PA_ISAIO),
+          .length       = SZ_16M,
+          .type         = MT_DEVICE,
+  }, {
+          .virtual      = (u32)S3C24XX_VA_ISA_WORD,
+          .pfn          = PA_CS3(BAST_PA_ISAIO),
+          .length       = SZ_16M,
+          .type         = MT_DEVICE,
+  },
   /* bast CPLD control registers, and external interrupt controls */
-  { (u32)BAST_VA_CTRL1, BAST_PA_CTRL1,             SZ_1M, MT_DEVICE },
-  { (u32)BAST_VA_CTRL2, BAST_PA_CTRL2,             SZ_1M, MT_DEVICE },
-  { (u32)BAST_VA_CTRL3, BAST_PA_CTRL3,             SZ_1M, MT_DEVICE },
-  { (u32)BAST_VA_CTRL4, BAST_PA_CTRL4,             SZ_1M, MT_DEVICE },
-
+  {
+          .virtual      = (u32)BAST_VA_CTRL1,
+          .pfn          = __phys_to_pfn(BAST_PA_CTRL1),
+          .length       = SZ_1M,
+          .type         = MT_DEVICE,
+  }, {
+          .virtual      = (u32)BAST_VA_CTRL2,
+          .pfn          = __phys_to_pfn(BAST_PA_CTRL2),
+          .length       = SZ_1M,
+          .type         = MT_DEVICE,
+  }, {
+          .virtual      = (u32)BAST_VA_CTRL3,
+          .pfn          = __phys_to_pfn(BAST_PA_CTRL3),
+          .length       = SZ_1M,
+          .type         = MT_DEVICE,
+  }, {
+          .virtual      = (u32)BAST_VA_CTRL4,
+          .pfn          = __phys_to_pfn(BAST_PA_CTRL4),
+          .length       = SZ_1M,
+          .type         = MT_DEVICE,
+  },
   /* PC104 IRQ mux */
-  { (u32)BAST_VA_PC104_IRQREQ,  BAST_PA_PC104_IRQREQ,   SZ_1M, MT_DEVICE },
-  { (u32)BAST_VA_PC104_IRQRAW,  BAST_PA_PC104_IRQRAW,   SZ_1M, MT_DEVICE },
-  { (u32)BAST_VA_PC104_IRQMASK, BAST_PA_PC104_IRQMASK,  SZ_1M, MT_DEVICE },
+  {
+          .virtual      = (u32)BAST_VA_PC104_IRQREQ,
+          .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
+          .length       = SZ_1M,
+          .type         = MT_DEVICE,
+  }, {
+          .virtual      = (u32)BAST_VA_PC104_IRQRAW,
+          .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
+          .length       = SZ_1M,
+          .type         = MT_DEVICE,
+  }, {
+          .virtual      = (u32)BAST_VA_PC104_IRQMASK,
+          .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
+          .length       = SZ_1M,
+          .type         = MT_DEVICE,
+  },
 
   /* peripheral space... one for each of fast/slow/byte/16bit */
   /* note, ide is only decoded in word space, even though some registers
diff --git a/arch/arm/mach-s3c2410/mach-rx3715.c b/arch/arm/mach-s3c2410/mach-rx3715.c
index 24d69019a843..f8d86d1e16b6 100644
--- a/arch/arm/mach-s3c2410/mach-rx3715.c
+++ b/arch/arm/mach-s3c2410/mach-rx3715.c
@@ -56,8 +56,17 @@
 static struct map_desc rx3715_iodesc[] __initdata = {
         /* dump ISA space somewhere unused */
 
-        { (u32)S3C24XX_VA_ISA_WORD, S3C2410_CS3, SZ_16M, MT_DEVICE },
-        { (u32)S3C24XX_VA_ISA_BYTE, S3C2410_CS3, SZ_16M, MT_DEVICE },
+        {
+                .virtual        = (u32)S3C24XX_VA_ISA_WORD,
+                .pfn            = __phys_to_pfn(S3C2410_CS3),
+                .length         = SZ_1M,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (u32)S3C24XX_VA_ISA_BYTE,
+                .pfn            = __phys_to_pfn(S3C2410_CS3),
+                .length         = SZ_1M,
+                .type           = MT_DEVICE,
+        },
 };
 
 
diff --git a/arch/arm/mach-s3c2410/mach-smdk2440.c b/arch/arm/mach-s3c2410/mach-smdk2440.c
index d666c621ad06..4e31118533e6 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2440.c
@@ -58,8 +58,27 @@
 static struct map_desc smdk2440_iodesc[] __initdata = {
         /* ISA IO Space map (memory space selected by A24) */
 
-        { (u32)S3C24XX_VA_ISA_WORD, S3C2410_CS2, SZ_16M, MT_DEVICE },
-        { (u32)S3C24XX_VA_ISA_BYTE, S3C2410_CS2, SZ_16M, MT_DEVICE },
+        {
+                .virtual        = (u32)S3C24XX_VA_ISA_WORD,
+                .pfn            = __phys_to_pfn(S3C2410_CS2),
+                .length         = 0x10000,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
+                .pfn            = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
+                .length         = SZ_4M,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (u32)S3C24XX_VA_ISA_BYTE,
+                .pfn            = __phys_to_pfn(S3C2410_CS2),
+                .length         = 0x10000,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
+                .pfn            = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
+                .length         = SZ_4M,
+                .type           = MT_DEVICE,
+        }
 };
 
 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 46b259673c18..ae7e099bf6c8 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -74,27 +74,47 @@
 
 /* macros to modify the physical addresses for io space */
 
-#define PA_CS2(item) ((item) + S3C2410_CS2)
-#define PA_CS3(item) ((item) + S3C2410_CS3)
-#define PA_CS4(item) ((item) + S3C2410_CS4)
-#define PA_CS5(item) ((item) + S3C2410_CS5)
+#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
+#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
+#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
+#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
 
 static struct map_desc vr1000_iodesc[] __initdata = {
   /* ISA IO areas */
-
-  { (u32)S3C24XX_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO),       SZ_16M, MT_DEVICE },
-  { (u32)S3C24XX_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO),       SZ_16M, MT_DEVICE },
-
-  /* we could possibly compress the next set down into a set of smaller tables
-   * pagetables, but that would mean using an L2 section, and it still means
-   * we cannot actually feed the same register to an LDR due to 16K spacing
-   */
-
-  /* bast CPLD control registers, and external interrupt controls */
-  { (u32)VR1000_VA_CTRL1, VR1000_PA_CTRL1,             SZ_1M, MT_DEVICE },
-  { (u32)VR1000_VA_CTRL2, VR1000_PA_CTRL2,             SZ_1M, MT_DEVICE },
-  { (u32)VR1000_VA_CTRL3, VR1000_PA_CTRL3,             SZ_1M, MT_DEVICE },
-  { (u32)VR1000_VA_CTRL4, VR1000_PA_CTRL4,             SZ_1M, MT_DEVICE },
+  {
+          .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
+          .pfn          = PA_CS2(BAST_PA_ISAIO),
+          .length       = SZ_16M,
+          .type         = MT_DEVICE,
+  }, {
+          .virtual      = (u32)S3C24XX_VA_ISA_WORD,
+          .pfn          = PA_CS3(BAST_PA_ISAIO),
+          .length       = SZ_16M,
+          .type         = MT_DEVICE,
+  },
+
+  /*  CPLD control registers, and external interrupt controls */
+  {
+          .virtual      = (u32)VR1000_VA_CTRL1,
+          .pfn          = __phys_to_pfn(VR1000_PA_CTRL1),
+          .length       = SZ_1M,
+          .type         = MT_DEVICE,
+  }, {
+          .virtual      = (u32)VR1000_VA_CTRL2,
+          .pfn          = __phys_to_pfn(VR1000_PA_CTRL2),
+          .length       = SZ_1M,
+          .type         = MT_DEVICE,
+  }, {
+          .virtual      = (u32)VR1000_VA_CTRL3,
+          .pfn          = __phys_to_pfn(VR1000_PA_CTRL3),
+          .length       = SZ_1M,
+          .type         = MT_DEVICE,
+  }, {
+          .virtual      = (u32)VR1000_VA_CTRL4,
+          .pfn          = __phys_to_pfn(VR1000_PA_CTRL4),
+          .length       = SZ_1M,
+          .type         = MT_DEVICE,
+  },
 
   /* peripheral space... one for each of fast/slow/byte/16bit */
   /* note, ide is only decoded in word space, even though some registers
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 47e0420623fc..e4b435e634e4 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -124,11 +124,13 @@ static void __init sa1100_timer_init(void)
         tv.tv_sec = sa1100_get_rtc_time();
         do_settimeofday(&tv);
 
-        OSMR0 = 0;              /* set initial match at 0 */
+        OIER = 0;               /* disable any timer interrupts */
+        OSCR = LATCH*2;         /* push OSCR out of the way */
+        OSMR0 = LATCH;          /* set initial match */
         OSSR = 0xf;             /* clear status on all timers */
         setup_irq(IRQ_OST0, &sa1100_timer_irq);
-        OIER |= OIER_E0;        /* enable match on timer 0 to cause interrupts */
-        OSCR = 0;               /* initialize free-running timer, force first match */
+        OIER = OIER_E0;         /* enable match on timer 0 to cause interrupts */
+        OSCR = 0;               /* initialize free-running timer */
 }
 
 #ifdef CONFIG_NO_IDLE_HZ
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index fb5b40289de2..9e50127be635 100644
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -354,7 +354,7 @@ void __init build_mem_type_table(void)
 {
         struct cachepolicy *cp;
         unsigned int cr = get_cr();
-        unsigned int user_pgprot;
+        unsigned int user_pgprot, kern_pgprot;
         int cpu_arch = cpu_architecture();
         int i;
 
@@ -381,7 +381,7 @@ void __init build_mem_type_table(void)
         }
 
         cp = &cache_policies[cachepolicy];
-        user_pgprot = cp->pte;
+        kern_pgprot = user_pgprot = cp->pte;
 
         /*
          * ARMv6 and above have extended page tables.
@@ -393,6 +393,7 @@ void __init build_mem_type_table(void)
                  */
                 mem_types[MT_MEMORY].prot_sect &= ~PMD_BIT4;
                 mem_types[MT_ROM].prot_sect &= ~PMD_BIT4;
+
                 /*
                  * Mark cache clean areas and XIP ROM read only
                  * from SVC mode and no access from userspace.
@@ -412,32 +413,47 @@ void __init build_mem_type_table(void)
                  * (iow, non-global)
                  */
                 user_pgprot |= L_PTE_ASID;
+
+#ifdef CONFIG_SMP
+                /*
+                 * Mark memory with the "shared" attribute for SMP systems
+                 */
+                user_pgprot |= L_PTE_SHARED;
+                kern_pgprot |= L_PTE_SHARED;
+                mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+#endif
         }
 
+        for (i = 0; i < 16; i++) {
+                unsigned long v = pgprot_val(protection_map[i]);
+                v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot;
+                protection_map[i] = __pgprot(v);
+        }
+
+        mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot;
+        mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot;
+
         if (cpu_arch >= CPU_ARCH_ARMv5) {
-                mem_types[MT_LOW_VECTORS].prot_pte |= cp->pte & PTE_CACHEABLE;
-                mem_types[MT_HIGH_VECTORS].prot_pte |= cp->pte & PTE_CACHEABLE;
+#ifndef CONFIG_SMP
+                /*
+                 * Only use write-through for non-SMP systems
+                 */
+                mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
+                mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
+#endif
         } else {
-                mem_types[MT_LOW_VECTORS].prot_pte |= cp->pte;
-                mem_types[MT_HIGH_VECTORS].prot_pte |= cp->pte;
                 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
         }
 
+        pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
+                                 L_PTE_DIRTY | L_PTE_WRITE |
+                                 L_PTE_EXEC | kern_pgprot);
+
         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
         mem_types[MT_ROM].prot_sect |= cp->pmd;
 
-        for (i = 0; i < 16; i++) {
-                unsigned long v = pgprot_val(protection_map[i]);
-                v = (v & ~(PTE_BUFFERABLE|PTE_CACHEABLE)) | user_pgprot;
-                protection_map[i] = __pgprot(v);
-        }
-
-        pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
-                                 L_PTE_DIRTY | L_PTE_WRITE |
-                                 L_PTE_EXEC | cp->pte);
-
         switch (cp->pmd) {
         case PMD_SECT_WT:
                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 9bb5fff406fb..92f3ca31b7b9 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -12,6 +12,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/hardware/arm_scu.h>
 #include <asm/procinfo.h>
 #include <asm/pgtable.h>
 
@@ -112,6 +113,9 @@ ENTRY(cpu_v6_dcache_clean_area)
 ENTRY(cpu_v6_switch_mm)
         mov     r2, #0
         ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
+#ifdef CONFIG_SMP
+        orr     r0, r0, #2                      @ set shared pgtable
+#endif
         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
         mcr     p15, 0, r2, c7, c10, 4          @ drain write buffer
         mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
@@ -140,7 +144,7 @@ ENTRY(cpu_v6_switch_mm)
 ENTRY(cpu_v6_set_pte)
         str     r1, [r0], #-2048                @ linux version
 
-        bic     r2, r1, #0x000007f0
+        bic     r2, r1, #0x000003f0
         bic     r2, r2, #0x00000003
         orr     r2, r2, #PTE_EXT_AP0 | 2
 
@@ -191,6 +195,23 @@ cpu_v6_name:
  *      - cache type register is implemented
  */
 __v6_setup:
+#ifdef CONFIG_SMP
+        /* Set up the SCU on core 0 only */
+        mrc     p15, 0, r0, c0, c0, 5           @ CPU core number
+        ands    r0, r0, #15
+        moveq   r0, #0x10000000 @ SCU_BASE
+        orreq   r0, r0, #0x00100000
+        ldreq   r5, [r0, #SCU_CTRL]
+        orreq   r5, r5, #1
+        streq   r5, [r0, #SCU_CTRL]
+
+#ifndef CONFIG_CPU_DCACHE_DISABLE
+        mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode
+        orr     r0, r0, #0x20
+        mcr     p15, 0, r0, c1, c0, 1
+#endif
+#endif
+
         mov     r0, #0
         mcr     p15, 0, r0, c7, c14, 0          @ clean+invalidate D cache
         mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
@@ -198,6 +219,9 @@ __v6_setup:
         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
         mcr     p15, 0, r0, c8, c7, 0           @ invalidate I + D TLBs
         mcr     p15, 0, r0, c2, c0, 2           @ TTB control register
+#ifdef CONFIG_SMP
+        orr     r4, r4, #2                      @ set shared pgtable
+#endif
         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
 #ifdef CONFIG_VFP
         mrc     p15, 0, r0, c1, c0, 2
diff --git a/arch/arm/nwfpe/fpa11.h b/arch/arm/nwfpe/fpa11.h
index 9677ae8448e8..da4c616b6c49 100644
--- a/arch/arm/nwfpe/fpa11.h
+++ b/arch/arm/nwfpe/fpa11.h
@@ -60,7 +60,7 @@ typedef union tagFPREG {
 #ifdef CONFIG_FPE_NWFPE_XP
         floatx80 fExtended;
 #else
-        int padding[3];
+        u32 padding[3];
 #endif
 } FPREG;
 
diff --git a/arch/arm/nwfpe/fpa11_cpdt.c b/arch/arm/nwfpe/fpa11_cpdt.c
index b0db5cbcc3b1..32859fa8dcfc 100644
--- a/arch/arm/nwfpe/fpa11_cpdt.c
+++ b/arch/arm/nwfpe/fpa11_cpdt.c
@@ -59,8 +59,13 @@ static inline void loadExtended(const unsigned int Fn, const unsigned int __user
         p = (unsigned int *) &fpa11->fpreg[Fn].fExtended;
         fpa11->fType[Fn] = typeExtended;
         get_user(p[0], &pMem[0]);       /* sign & exponent */
+#ifdef __ARMEB__
+        get_user(p[1], &pMem[1]);       /* ms bits */
+        get_user(p[2], &pMem[2]);       /* ls bits */
+#else
         get_user(p[1], &pMem[2]);       /* ls bits */
         get_user(p[2], &pMem[1]);       /* ms bits */
+#endif
 }
 #endif
 
@@ -177,8 +182,13 @@ static inline void storeExtended(const unsigned int Fn, unsigned int __user *pMe
         }
 
         put_user(val.i[0], &pMem[0]);   /* sign & exp */
+#ifdef __ARMEB__
+        put_user(val.i[1], &pMem[1]);   /* msw */
+        put_user(val.i[2], &pMem[2]);
+#else
         put_user(val.i[1], &pMem[2]);
         put_user(val.i[2], &pMem[1]);   /* msw */
+#endif
 }
 #endif
 
diff --git a/arch/arm/nwfpe/fpopcode.c b/arch/arm/nwfpe/fpopcode.c
index 4c9f5703148c..67ff2ab08ea0 100644
--- a/arch/arm/nwfpe/fpopcode.c
+++ b/arch/arm/nwfpe/fpopcode.c
@@ -29,14 +29,14 @@
 
 #ifdef CONFIG_FPE_NWFPE_XP
 const floatx80 floatx80Constant[] = {
-        {0x0000, 0x0000000000000000ULL},        /* extended 0.0 */
-        {0x3fff, 0x8000000000000000ULL},        /* extended 1.0 */
-        {0x4000, 0x8000000000000000ULL},        /* extended 2.0 */
-        {0x4000, 0xc000000000000000ULL},        /* extended 3.0 */
-        {0x4001, 0x8000000000000000ULL},        /* extended 4.0 */
-        {0x4001, 0xa000000000000000ULL},        /* extended 5.0 */
-        {0x3ffe, 0x8000000000000000ULL},        /* extended 0.5 */
-        {0x4002, 0xa000000000000000ULL}         /* extended 10.0 */
+        { .high = 0x0000, .low = 0x0000000000000000ULL},/* extended 0.0 */
+        { .high = 0x3fff, .low = 0x8000000000000000ULL},/* extended 1.0 */
+        { .high = 0x4000, .low = 0x8000000000000000ULL},/* extended 2.0 */
+        { .high = 0x4000, .low = 0xc000000000000000ULL},/* extended 3.0 */
+        { .high = 0x4001, .low = 0x8000000000000000ULL},/* extended 4.0 */
+        { .high = 0x4001, .low = 0xa000000000000000ULL},/* extended 5.0 */
+        { .high = 0x3ffe, .low = 0x8000000000000000ULL},/* extended 0.5 */
+        { .high = 0x4002, .low = 0xa000000000000000ULL},/* extended 10.0 */
 };
 #endif
 
diff --git a/arch/arm/nwfpe/softfloat-specialize b/arch/arm/nwfpe/softfloat-specialize
index acf409144763..d4a4c8e06635 100644
--- a/arch/arm/nwfpe/softfloat-specialize
+++ b/arch/arm/nwfpe/softfloat-specialize
@@ -332,6 +332,7 @@ static floatx80 commonNaNToFloatx80( commonNaNT a )
 
     z.low = LIT64( 0xC000000000000000 ) | ( a.high>>1 );
     z.high = ( ( (bits16) a.sign )<<15 ) | 0x7FFF;
+    z.__padding = 0;
     return z;
 
 }
diff --git a/arch/arm/nwfpe/softfloat.c b/arch/arm/nwfpe/softfloat.c
index f9f049132a17..0f9656e482ba 100644
--- a/arch/arm/nwfpe/softfloat.c
+++ b/arch/arm/nwfpe/softfloat.c
@@ -531,6 +531,7 @@ INLINE floatx80 packFloatx80( flag zSign, int32 zExp, bits64 zSig )
 
     z.low = zSig;
     z.high = ( ( (bits16) zSign )<<15 ) + zExp;
+    z.__padding = 0;
     return z;
 
 }
@@ -2831,6 +2832,7 @@ static floatx80 subFloatx80Sigs( struct roundingData *roundData, floatx80 a, flo
         roundData->exception |= float_flag_invalid;
         z.low = floatx80_default_nan_low;
         z.high = floatx80_default_nan_high;
+        z.__padding = 0;
         return z;
     }
     if ( aExp == 0 ) {
@@ -2950,6 +2952,7 @@ floatx80 floatx80_mul( struct roundingData *roundData, floatx80 a, floatx80 b )
             roundData->exception |= float_flag_invalid;
             z.low = floatx80_default_nan_low;
             z.high = floatx80_default_nan_high;
+            z.__padding = 0;
             return z;
         }
         return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
@@ -3015,6 +3018,7 @@ floatx80 floatx80_div( struct roundingData *roundData, floatx80 a, floatx80 b )
                 roundData->exception |= float_flag_invalid;
                 z.low = floatx80_default_nan_low;
                 z.high = floatx80_default_nan_high;
+                z.__padding = 0;
                 return z;
             }
             roundData->exception |= float_flag_divbyzero;
@@ -3093,6 +3097,7 @@ floatx80 floatx80_rem( struct roundingData *roundData, floatx80 a, floatx80 b )
             roundData->exception |= float_flag_invalid;
             z.low = floatx80_default_nan_low;
             z.high = floatx80_default_nan_high;
+            z.__padding = 0;
             return z;
         }
         normalizeFloatx80Subnormal( bSig, &bExp, &bSig );
@@ -3184,6 +3189,7 @@ floatx80 floatx80_sqrt( struct roundingData *roundData, floatx80 a )
         roundData->exception |= float_flag_invalid;
         z.low = floatx80_default_nan_low;
         z.high = floatx80_default_nan_high;
+        z.__padding = 0;
         return z;
     }
     if ( aExp == 0 ) {
diff --git a/arch/arm/nwfpe/softfloat.h b/arch/arm/nwfpe/softfloat.h
index 14151700b6b2..978c699673c6 100644
--- a/arch/arm/nwfpe/softfloat.h
+++ b/arch/arm/nwfpe/softfloat.h
@@ -51,11 +51,17 @@ input or output the `floatx80' type will be defined.
 Software IEC/IEEE floating-point types.
 -------------------------------------------------------------------------------
 */
-typedef unsigned long int float32;
-typedef unsigned long long float64;
+typedef u32 float32;
+typedef u64 float64;
 typedef struct {
-    unsigned short high;
-    unsigned long long low;
+#ifdef __ARMEB__
+    u16 __padding;
+    u16 high;
+#else
+    u16 high;
+    u16 __padding;
+#endif
+    u64 low;
 } floatx80;
 
 /*
diff --git a/arch/arm/plat-omap/ocpi.c b/arch/arm/plat-omap/ocpi.c
index 1fb16f9edfd5..2ede2ee8cae4 100644
--- a/arch/arm/plat-omap/ocpi.c
+++ b/arch/arm/plat-omap/ocpi.c
@@ -25,7 +25,6 @@
 
 #include <linux/config.h>
 #include <linux/module.h>
-#include <linux/version.h>
 #include <linux/types.h>
 #include <linux/errno.h>
 #include <linux/kernel.h>