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-rw-r--r--arch/arm/Kconfig9
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/compressed/Makefile4
-rw-r--r--arch/arm/boot/compressed/head-clps7500.S86
-rw-r--r--arch/arm/include/asm/hardware/iomd.h41
-rw-r--r--arch/arm/lib/Makefile1
-rw-r--r--arch/arm/mach-clps7500/Makefile11
-rw-r--r--arch/arm/mach-clps7500/Makefile.boot2
-rw-r--r--arch/arm/mach-clps7500/core.c395
-rw-r--r--arch/arm/mach-clps7500/include/mach/acornfb.h33
-rw-r--r--arch/arm/mach-clps7500/include/mach/debug-macro.S21
-rw-r--r--arch/arm/mach-clps7500/include/mach/dma.h21
-rw-r--r--arch/arm/mach-clps7500/include/mach/entry-macro.S16
-rw-r--r--arch/arm/mach-clps7500/include/mach/hardware.h67
-rw-r--r--arch/arm/mach-clps7500/include/mach/io.h255
-rw-r--r--arch/arm/mach-clps7500/include/mach/irq.h32
-rw-r--r--arch/arm/mach-clps7500/include/mach/irqs.h66
-rw-r--r--arch/arm/mach-clps7500/include/mach/memory.h43
-rw-r--r--arch/arm/mach-clps7500/include/mach/system.h23
-rw-r--r--arch/arm/mach-clps7500/include/mach/timex.h13
-rw-r--r--arch/arm/mach-clps7500/include/mach/uncompress.h35
-rw-r--r--arch/arm/mach-clps7500/include/mach/vmalloc.h4
22 files changed, 0 insertions, 1179 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9722f8bb506c..6946d95c939e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -243,15 +243,6 @@ config ARCH_AT91
243 This enables support for systems based on the Atmel AT91RM9200, 243 This enables support for systems based on the Atmel AT91RM9200,
244 AT91SAM9 and AT91CAP9 processors. 244 AT91SAM9 and AT91CAP9 processors.
245 245
246config ARCH_CLPS7500
247 bool "Cirrus CL-PS7500FE"
248 select TIMER_ACORN
249 select ISA
250 select NO_IOPORT
251 select ARCH_SPARSEMEM_ENABLE
252 help
253 Support for the Cirrus Logic PS7500FE system-on-a-chip.
254
255config ARCH_CLPS711X 246config ARCH_CLPS711X
256 bool "Cirrus Logic CLPS711x/EP721x-based" 247 bool "Cirrus Logic CLPS711x/EP721x-based"
257 help 248 help
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index bd6e28115ebb..2eca2998f93e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -96,7 +96,6 @@ textofs-y := 0x00008000
96 96
97 machine-$(CONFIG_ARCH_RPC) := rpc 97 machine-$(CONFIG_ARCH_RPC) := rpc
98 machine-$(CONFIG_ARCH_EBSA110) := ebsa110 98 machine-$(CONFIG_ARCH_EBSA110) := ebsa110
99 machine-$(CONFIG_ARCH_CLPS7500) := clps7500
100 machine-$(CONFIG_FOOTBRIDGE) := footbridge 99 machine-$(CONFIG_FOOTBRIDGE) := footbridge
101 machine-$(CONFIG_ARCH_SHARK) := shark 100 machine-$(CONFIG_ARCH_SHARK) := shark
102 machine-$(CONFIG_ARCH_SA1100) := sa1100 101 machine-$(CONFIG_ARCH_SA1100) := sa1100
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index c47f2a3f8f8f..fbe5eef1f6c9 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -23,10 +23,6 @@ ifeq ($(CONFIG_ARCH_L7200),y)
23OBJS += head-l7200.o 23OBJS += head-l7200.o
24endif 24endif
25 25
26ifeq ($(CONFIG_ARCH_CLPS7500),y)
27HEAD = head-clps7500.o
28endif
29
30ifeq ($(CONFIG_ARCH_P720T),y) 26ifeq ($(CONFIG_ARCH_P720T),y)
31# Borrow this code from SA1100 27# Borrow this code from SA1100
32OBJS += head-sa1100.o 28OBJS += head-sa1100.o
diff --git a/arch/arm/boot/compressed/head-clps7500.S b/arch/arm/boot/compressed/head-clps7500.S
deleted file mode 100644
index 4f3c78ac30a0..000000000000
--- a/arch/arm/boot/compressed/head-clps7500.S
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 * linux/arch/arm/boot/compressed/head-clps7500.S
3 *
4 * Copyright (C) 1999, 2000, 2001 Nexus Electronics Ltd
5 */
6
7
8 /* There are three different ways the kernel can be
9 booted on a 7500 system: from Angel (loaded in RAM), from
10 16-bit ROM or from 32-bit Flash. Luckily, a single kernel
11 image does for them all. */
12 /* This branch is taken if the CPU memory width matches the
13 actual device in use. The default at power on is 16 bits
14 so we must be prepared for a mismatch. */
15 .section ".start", "ax"
162:
17 b 1f
18 .word 0xffff
19 .word 0xb632 @ mov r11, #0x03200000
20 .word 0xe3a0
21 .word 0x0000 @ mov r0, #0
22 .word 0xe3a0
23 .word 0x0080 @ strb r0, [r11, #0x80]
24 .word 0xe5cb
25 .word 0xf000 @ mov pc, #0
26 .word 0xe3a0
271:
28 adr r1, 2b
29 teq r1, #0
30 bne .Langel
31 /* This is a direct-from-ROM boot. Copy the kernel into
32 RAM and run it there. */
33 mov r0, #0x30
34 mcr p15, 0, r0, c1, c0, 0
35 mov r0, #0x13
36 msr cpsr_cxsf, r0
37 mov r12, #0x03000000 @ point to LEDs
38 orr r12, r12, #0x00020000
39 orr r12, r12, #0xba00
40 mov r0, #0x5500
41 str r0, [r12]
42 mov r0, #0x10000000
43 orr r0, r0, #0x8000
44 mov r4, r0
45 ldr r2, =_end
462:
47 ldr r3, [r1], #4
48 str r3, [r0], #4
49 teq r0, r2
50 bne 2b
51 mov r0, #0xff00
52 str r0, [r12]
531:
54 mov r12, #0x03000000 @ point to LEDs
55 orr r12, r12, #0x00020000
56 orr r12, r12, #0xba00
57 mov r0, #0xfe00
58 str r0, [r12]
59
60 adr lr, 1f
61 mov r0, #0
62 mov r1, #14 /* MACH_TYPE_CLPS7500 */
63 mov pc, lr
64.Langel:
65#ifdef CONFIG_ANGELBOOT
66 /* Call Angel to switch into SVC mode. */
67 mov r0, #0x17
68 swi 0x123456
69#endif
70 /* Ensure all interrupts are off and MMU disabled */
71 mrs r0, cpsr
72 orr r0, r0, #0xc0
73 msr cpsr_cxsf, r0
74
75 adr lr, 1b
76 orr lr, lr, #0x10000000
77 mov r0, #0x30 @ MMU off
78 mcr p15, 0, r0, c1, c0, 0
79 mov r0, r0
80 mov pc, lr
81
82 .ltorg
83
841:
85/* And the rest */
86#include "head.S"
diff --git a/arch/arm/include/asm/hardware/iomd.h b/arch/arm/include/asm/hardware/iomd.h
index 9c5afbd71a69..f9ee69e4f53e 100644
--- a/arch/arm/include/asm/hardware/iomd.h
+++ b/arch/arm/include/asm/hardware/iomd.h
@@ -32,19 +32,11 @@
32#define IOMD_KARTRX (0x004) 32#define IOMD_KARTRX (0x004)
33#define IOMD_KCTRL (0x008) 33#define IOMD_KCTRL (0x008)
34 34
35#ifdef CONFIG_ARCH_CLPS7500
36#define IOMD_IOLINES (0x00C)
37#endif
38
39#define IOMD_IRQSTATA (0x010) 35#define IOMD_IRQSTATA (0x010)
40#define IOMD_IRQREQA (0x014) 36#define IOMD_IRQREQA (0x014)
41#define IOMD_IRQCLRA (0x014) 37#define IOMD_IRQCLRA (0x014)
42#define IOMD_IRQMASKA (0x018) 38#define IOMD_IRQMASKA (0x018)
43 39
44#ifdef CONFIG_ARCH_CLPS7500
45#define IOMD_SUSMODE (0x01C)
46#endif
47
48#define IOMD_IRQSTATB (0x020) 40#define IOMD_IRQSTATB (0x020)
49#define IOMD_IRQREQB (0x024) 41#define IOMD_IRQREQB (0x024)
50#define IOMD_IRQMASKB (0x028) 42#define IOMD_IRQMASKB (0x028)
@@ -53,10 +45,6 @@
53#define IOMD_FIQREQ (0x034) 45#define IOMD_FIQREQ (0x034)
54#define IOMD_FIQMASK (0x038) 46#define IOMD_FIQMASK (0x038)
55 47
56#ifdef CONFIG_ARCH_CLPS7500
57#define IOMD_CLKCTL (0x03C)
58#endif
59
60#define IOMD_T0CNTL (0x040) 48#define IOMD_T0CNTL (0x040)
61#define IOMD_T0LTCHL (0x040) 49#define IOMD_T0LTCHL (0x040)
62#define IOMD_T0CNTH (0x044) 50#define IOMD_T0CNTH (0x044)
@@ -71,18 +59,6 @@
71#define IOMD_T1GO (0x058) 59#define IOMD_T1GO (0x058)
72#define IOMD_T1LATCH (0x05c) 60#define IOMD_T1LATCH (0x05c)
73 61
74#ifdef CONFIG_ARCH_CLPS7500
75#define IOMD_IRQSTATC (0x060)
76#define IOMD_IRQREQC (0x064)
77#define IOMD_IRQMASKC (0x068)
78
79#define IOMD_VIDMUX (0x06c)
80
81#define IOMD_IRQSTATD (0x070)
82#define IOMD_IRQREQD (0x074)
83#define IOMD_IRQMASKD (0x078)
84#endif
85
86#define IOMD_ROMCR0 (0x080) 62#define IOMD_ROMCR0 (0x080)
87#define IOMD_ROMCR1 (0x084) 63#define IOMD_ROMCR1 (0x084)
88#ifdef CONFIG_ARCH_RPC 64#ifdef CONFIG_ARCH_RPC
@@ -100,11 +76,6 @@
100#define IOMD_MOUSEY (0x0A4) 76#define IOMD_MOUSEY (0x0A4)
101#endif 77#endif
102 78
103#ifdef CONFIG_ARCH_CLPS7500
104#define IOMD_MSEDAT (0x0A8)
105#define IOMD_MSECTL (0x0Ac)
106#endif
107
108#ifdef CONFIG_ARCH_RPC 79#ifdef CONFIG_ARCH_RPC
109#define IOMD_DMATCR (0x0C0) 80#define IOMD_DMATCR (0x0C0)
110#endif 81#endif
@@ -113,18 +84,6 @@
113#ifdef CONFIG_ARCH_RPC 84#ifdef CONFIG_ARCH_RPC
114#define IOMD_DMAEXT (0x0CC) 85#define IOMD_DMAEXT (0x0CC)
115#endif 86#endif
116#ifdef CONFIG_ARCH_CLPS7500
117#define IOMD_ASTCR (0x0CC)
118#define IOMD_DRAMCR (0x0D0)
119#define IOMD_SELFREF (0x0D4)
120#define IOMD_ATODICR (0x0E0)
121#define IOMD_ATODSR (0x0E4)
122#define IOMD_ATODCC (0x0E8)
123#define IOMD_ATODCNT1 (0x0EC)
124#define IOMD_ATODCNT2 (0x0F0)
125#define IOMD_ATODCNT3 (0x0F4)
126#define IOMD_ATODCNT4 (0x0F8)
127#endif
128 87
129#ifdef CONFIG_ARCH_RPC 88#ifdef CONFIG_ARCH_RPC
130#define DMA_EXT_IO0 1 89#define DMA_EXT_IO0 1
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 30351cd4560d..866f84a586ff 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -38,7 +38,6 @@ else
38endif 38endif
39 39
40lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o 40lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o
41lib-$(CONFIG_ARCH_CLPS7500) += io-acorn.o
42lib-$(CONFIG_ARCH_L7200) += io-acorn.o 41lib-$(CONFIG_ARCH_L7200) += io-acorn.o
43lib-$(CONFIG_ARCH_SHARK) += io-shark.o 42lib-$(CONFIG_ARCH_SHARK) += io-shark.o
44 43
diff --git a/arch/arm/mach-clps7500/Makefile b/arch/arm/mach-clps7500/Makefile
deleted file mode 100644
index 4bd8ebd70e7b..000000000000
--- a/arch/arm/mach-clps7500/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7obj-y := core.o
8obj-m :=
9obj-n :=
10obj- :=
11
diff --git a/arch/arm/mach-clps7500/Makefile.boot b/arch/arm/mach-clps7500/Makefile.boot
deleted file mode 100644
index fe16506c1540..000000000000
--- a/arch/arm/mach-clps7500/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y := 0x10008000
2
diff --git a/arch/arm/mach-clps7500/core.c b/arch/arm/mach-clps7500/core.c
deleted file mode 100644
index 7e247c04d41c..000000000000
--- a/arch/arm/mach-clps7500/core.c
+++ /dev/null
@@ -1,395 +0,0 @@
1/*
2 * linux/arch/arm/mach-clps7500/core.c
3 *
4 * Copyright (C) 1998 Russell King
5 * Copyright (C) 1999 Nexus Electronics Ltd
6 *
7 * Extra MM routines for CL7500 architecture
8 */
9#include <linux/kernel.h>
10#include <linux/types.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/list.h>
14#include <linux/sched.h>
15#include <linux/init.h>
16#include <linux/device.h>
17#include <linux/serial_8250.h>
18#include <linux/io.h>
19
20#include <asm/mach/arch.h>
21#include <asm/mach/map.h>
22#include <asm/mach/irq.h>
23#include <asm/mach/time.h>
24
25#include <mach/hardware.h>
26#include <asm/hardware/iomd.h>
27#include <asm/irq.h>
28#include <asm/mach-types.h>
29
30unsigned int vram_size;
31
32static void cl7500_ack_irq_a(unsigned int irq)
33{
34 unsigned int val, mask;
35
36 mask = 1 << irq;
37 val = iomd_readb(IOMD_IRQMASKA);
38 iomd_writeb(val & ~mask, IOMD_IRQMASKA);
39 iomd_writeb(mask, IOMD_IRQCLRA);
40}
41
42static void cl7500_mask_irq_a(unsigned int irq)
43{
44 unsigned int val, mask;
45
46 mask = 1 << irq;
47 val = iomd_readb(IOMD_IRQMASKA);
48 iomd_writeb(val & ~mask, IOMD_IRQMASKA);
49}
50
51static void cl7500_unmask_irq_a(unsigned int irq)
52{
53 unsigned int val, mask;
54
55 mask = 1 << irq;
56 val = iomd_readb(IOMD_IRQMASKA);
57 iomd_writeb(val | mask, IOMD_IRQMASKA);
58}
59
60static struct irq_chip clps7500_a_chip = {
61 .ack = cl7500_ack_irq_a,
62 .mask = cl7500_mask_irq_a,
63 .unmask = cl7500_unmask_irq_a,
64};
65
66static void cl7500_mask_irq_b(unsigned int irq)
67{
68 unsigned int val, mask;
69
70 mask = 1 << (irq & 7);
71 val = iomd_readb(IOMD_IRQMASKB);
72 iomd_writeb(val & ~mask, IOMD_IRQMASKB);
73}
74
75static void cl7500_unmask_irq_b(unsigned int irq)
76{
77 unsigned int val, mask;
78
79 mask = 1 << (irq & 7);
80 val = iomd_readb(IOMD_IRQMASKB);
81 iomd_writeb(val | mask, IOMD_IRQMASKB);
82}
83
84static struct irq_chip clps7500_b_chip = {
85 .ack = cl7500_mask_irq_b,
86 .mask = cl7500_mask_irq_b,
87 .unmask = cl7500_unmask_irq_b,
88};
89
90static void cl7500_mask_irq_c(unsigned int irq)
91{
92 unsigned int val, mask;
93
94 mask = 1 << (irq & 7);
95 val = iomd_readb(IOMD_IRQMASKC);
96 iomd_writeb(val & ~mask, IOMD_IRQMASKC);
97}
98
99static void cl7500_unmask_irq_c(unsigned int irq)
100{
101 unsigned int val, mask;
102
103 mask = 1 << (irq & 7);
104 val = iomd_readb(IOMD_IRQMASKC);
105 iomd_writeb(val | mask, IOMD_IRQMASKC);
106}
107
108static struct irq_chip clps7500_c_chip = {
109 .ack = cl7500_mask_irq_c,
110 .mask = cl7500_mask_irq_c,
111 .unmask = cl7500_unmask_irq_c,
112};
113
114static void cl7500_mask_irq_d(unsigned int irq)
115{
116 unsigned int val, mask;
117
118 mask = 1 << (irq & 7);
119 val = iomd_readb(IOMD_IRQMASKD);
120 iomd_writeb(val & ~mask, IOMD_IRQMASKD);
121}
122
123static void cl7500_unmask_irq_d(unsigned int irq)
124{
125 unsigned int val, mask;
126
127 mask = 1 << (irq & 7);
128 val = iomd_readb(IOMD_IRQMASKD);
129 iomd_writeb(val | mask, IOMD_IRQMASKD);
130}
131
132static struct irq_chip clps7500_d_chip = {
133 .ack = cl7500_mask_irq_d,
134 .mask = cl7500_mask_irq_d,
135 .unmask = cl7500_unmask_irq_d,
136};
137
138static void cl7500_mask_irq_dma(unsigned int irq)
139{
140 unsigned int val, mask;
141
142 mask = 1 << (irq & 7);
143 val = iomd_readb(IOMD_DMAMASK);
144 iomd_writeb(val & ~mask, IOMD_DMAMASK);
145}
146
147static void cl7500_unmask_irq_dma(unsigned int irq)
148{
149 unsigned int val, mask;
150
151 mask = 1 << (irq & 7);
152 val = iomd_readb(IOMD_DMAMASK);
153 iomd_writeb(val | mask, IOMD_DMAMASK);
154}
155
156static struct irq_chip clps7500_dma_chip = {
157 .ack = cl7500_mask_irq_dma,
158 .mask = cl7500_mask_irq_dma,
159 .unmask = cl7500_unmask_irq_dma,
160};
161
162static void cl7500_mask_irq_fiq(unsigned int irq)
163{
164 unsigned int val, mask;
165
166 mask = 1 << (irq & 7);
167 val = iomd_readb(IOMD_FIQMASK);
168 iomd_writeb(val & ~mask, IOMD_FIQMASK);
169}
170
171static void cl7500_unmask_irq_fiq(unsigned int irq)
172{
173 unsigned int val, mask;
174
175 mask = 1 << (irq & 7);
176 val = iomd_readb(IOMD_FIQMASK);
177 iomd_writeb(val | mask, IOMD_FIQMASK);
178}
179
180static struct irq_chip clps7500_fiq_chip = {
181 .ack = cl7500_mask_irq_fiq,
182 .mask = cl7500_mask_irq_fiq,
183 .unmask = cl7500_unmask_irq_fiq,
184};
185
186static void cl7500_no_action(unsigned int irq)
187{
188}
189
190static struct irq_chip clps7500_no_chip = {
191 .ack = cl7500_no_action,
192 .mask = cl7500_no_action,
193 .unmask = cl7500_no_action,
194};
195
196static struct irqaction irq_isa = {
197 .handler = no_action,
198 .mask = CPU_MASK_NONE,
199 .name = "isa",
200};
201
202static void __init clps7500_init_irq(void)
203{
204 unsigned int irq, flags;
205
206 iomd_writeb(0, IOMD_IRQMASKA);
207 iomd_writeb(0, IOMD_IRQMASKB);
208 iomd_writeb(0, IOMD_FIQMASK);
209 iomd_writeb(0, IOMD_DMAMASK);
210
211 for (irq = 0; irq < NR_IRQS; irq++) {
212 flags = IRQF_VALID;
213
214 if (irq <= 6 || (irq >= 9 && irq <= 15) ||
215 (irq >= 48 && irq <= 55))
216 flags |= IRQF_PROBE;
217
218 switch (irq) {
219 case 0 ... 7:
220 set_irq_chip(irq, &clps7500_a_chip);
221 set_irq_handler(irq, handle_level_irq);
222 set_irq_flags(irq, flags);
223 break;
224
225 case 8 ... 15:
226 set_irq_chip(irq, &clps7500_b_chip);
227 set_irq_handler(irq, handle_level_irq);
228 set_irq_flags(irq, flags);
229 break;
230
231 case 16 ... 22:
232 set_irq_chip(irq, &clps7500_dma_chip);
233 set_irq_handler(irq, handle_level_irq);
234 set_irq_flags(irq, flags);
235 break;
236
237 case 24 ... 31:
238 set_irq_chip(irq, &clps7500_c_chip);
239 set_irq_handler(irq, handle_level_irq);
240 set_irq_flags(irq, flags);
241 break;
242
243 case 40 ... 47:
244 set_irq_chip(irq, &clps7500_d_chip);
245 set_irq_handler(irq, handle_level_irq);
246 set_irq_flags(irq, flags);
247 break;
248
249 case 48 ... 55:
250 set_irq_chip(irq, &clps7500_no_chip);
251 set_irq_handler(irq, handle_level_irq);
252 set_irq_flags(irq, flags);
253 break;
254
255 case 64 ... 72:
256 set_irq_chip(irq, &clps7500_fiq_chip);
257 set_irq_handler(irq, handle_level_irq);
258 set_irq_flags(irq, flags);
259 break;
260 }
261 }
262
263 setup_irq(IRQ_ISA, &irq_isa);
264}
265
266static struct map_desc cl7500_io_desc[] __initdata = {
267 { /* IO space */
268 .virtual = (unsigned long)IO_BASE,
269 .pfn = __phys_to_pfn(IO_START),
270 .length = IO_SIZE,
271 .type = MT_DEVICE
272 }, { /* ISA space */
273 .virtual = ISA_BASE,
274 .pfn = __phys_to_pfn(ISA_START),
275 .length = ISA_SIZE,
276 .type = MT_DEVICE
277 }, { /* Flash */
278 .virtual = CLPS7500_FLASH_BASE,
279 .pfn = __phys_to_pfn(CLPS7500_FLASH_START),
280 .length = CLPS7500_FLASH_SIZE,
281 .type = MT_DEVICE
282 }, { /* LED */
283 .virtual = LED_BASE,
284 .pfn = __phys_to_pfn(LED_START),
285 .length = LED_SIZE,
286 .type = MT_DEVICE
287 }
288};
289
290static void __init clps7500_map_io(void)
291{
292 iotable_init(cl7500_io_desc, ARRAY_SIZE(cl7500_io_desc));
293}
294
295extern void ioctime_init(void);
296extern unsigned long ioc_timer_gettimeoffset(void);
297
298static irqreturn_t
299clps7500_timer_interrupt(int irq, void *dev_id)
300{
301 timer_tick();
302
303 /* Why not using do_leds interface?? */
304 {
305 /* Twinkle the lights. */
306 static int count, state = 0xff00;
307 if (count-- == 0) {
308 state ^= 0x100;
309 count = 25;
310 *((volatile unsigned int *)LED_ADDRESS) = state;
311 }
312 }
313
314 return IRQ_HANDLED;
315}
316
317static struct irqaction clps7500_timer_irq = {
318 .name = "CLPS7500 Timer Tick",
319 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
320 .handler = clps7500_timer_interrupt,
321};
322
323/*
324 * Set up timer interrupt.
325 */
326static void __init clps7500_timer_init(void)
327{
328 ioctime_init();
329 setup_irq(IRQ_TIMER, &clps7500_timer_irq);
330}
331
332static struct sys_timer clps7500_timer = {
333 .init = clps7500_timer_init,
334 .offset = ioc_timer_gettimeoffset,
335};
336
337static struct plat_serial8250_port serial_platform_data[] = {
338 {
339 .mapbase = 0x03010fe0,
340 .irq = 10,
341 .uartclk = 1843200,
342 .regshift = 2,
343 .iotype = UPIO_MEM,
344 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
345 },
346 {
347 .mapbase = 0x03010be0,
348 .irq = 0,
349 .uartclk = 1843200,
350 .regshift = 2,
351 .iotype = UPIO_MEM,
352 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
353 },
354 {
355 .iobase = ISASLOT_IO + 0x2e8,
356 .irq = 41,
357 .uartclk = 1843200,
358 .regshift = 0,
359 .iotype = UPIO_PORT,
360 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
361 },
362 {
363 .iobase = ISASLOT_IO + 0x3e8,
364 .irq = 40,
365 .uartclk = 1843200,
366 .regshift = 0,
367 .iotype = UPIO_PORT,
368 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
369 },
370 { },
371};
372
373static struct platform_device serial_device = {
374 .name = "serial8250",
375 .id = PLAT8250_DEV_PLATFORM,
376 .dev = {
377 .platform_data = serial_platform_data,
378 },
379};
380
381static void __init clps7500_init(void)
382{
383 platform_device_register(&serial_device);
384}
385
386MACHINE_START(CLPS7500, "CL-PS7500")
387 /* Maintainer: Philip Blundell */
388 .phys_io = 0x03000000,
389 .io_pg_offst = ((0xe0000000) >> 18) & 0xfffc,
390 .map_io = clps7500_map_io,
391 .init_irq = clps7500_init_irq,
392 .init_machine = clps7500_init,
393 .timer = &clps7500_timer,
394MACHINE_END
395
diff --git a/arch/arm/mach-clps7500/include/mach/acornfb.h b/arch/arm/mach-clps7500/include/mach/acornfb.h
deleted file mode 100644
index aea6330c9745..000000000000
--- a/arch/arm/mach-clps7500/include/mach/acornfb.h
+++ /dev/null
@@ -1,33 +0,0 @@
1#define acornfb_valid_pixrate(var) (var->pixclock >= 39325 && var->pixclock <= 40119)
2
3static inline void
4acornfb_vidc20_find_rates(struct vidc_timing *vidc,
5 struct fb_var_screeninfo *var)
6{
7 u_int bandwidth;
8
9 vidc->control |= VIDC20_CTRL_PIX_CK;
10
11 /* Calculate bandwidth */
12 bandwidth = var->pixclock * 8 / var->bits_per_pixel;
13
14 /* Encode bandwidth as VIDC20 setting */
15 if (bandwidth > 16667*2)
16 vidc->control |= VIDC20_CTRL_FIFO_16;
17 else if (bandwidth > 13333*2)
18 vidc->control |= VIDC20_CTRL_FIFO_20;
19 else if (bandwidth > 11111*2)
20 vidc->control |= VIDC20_CTRL_FIFO_24;
21 else
22 vidc->control |= VIDC20_CTRL_FIFO_28;
23
24 vidc->pll_ctl = 0x2020;
25}
26
27#ifdef CONFIG_CHRONTEL_7003
28#define acornfb_default_control() VIDC20_CTRL_PIX_HCLK
29#else
30#define acornfb_default_control() VIDC20_CTRL_PIX_VCLK
31#endif
32
33#define acornfb_default_econtrol() VIDC20_ECTL_DAC | VIDC20_ECTL_REG(3) | VIDC20_ECTL_ECK
diff --git a/arch/arm/mach-clps7500/include/mach/debug-macro.S b/arch/arm/mach-clps7500/include/mach/debug-macro.S
deleted file mode 100644
index af4104e7e84a..000000000000
--- a/arch/arm/mach-clps7500/include/mach/debug-macro.S
+++ /dev/null
@@ -1,21 +0,0 @@
1/* arch/arm/mach-clps7500/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart,rx
15 mov \rx, #0xe0000000
16 orr \rx, \rx, #0x00010000
17 orr \rx, \rx, #0x00000be0
18 .endm
19
20#define UART_SHIFT 2
21#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-clps7500/include/mach/dma.h b/arch/arm/mach-clps7500/include/mach/dma.h
deleted file mode 100644
index 63fcde505498..000000000000
--- a/arch/arm/mach-clps7500/include/mach/dma.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/dma.h
3 *
4 * Copyright (C) 1999 Nexus Electronics Ltd.
5 */
6
7#ifndef __ASM_ARCH_DMA_H
8#define __ASM_ARCH_DMA_H
9
10/* DMA is not yet implemented! It should be the same as acorn, copy over.. */
11
12/*
13 * This is the maximum DMA address that can be DMAd to.
14 * There should not be more than (0xd0000000 - 0xc0000000)
15 * bytes of RAM.
16 */
17#define MAX_DMA_ADDRESS 0xd0000000
18
19#define DMA_S0 0
20
21#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-clps7500/include/mach/entry-macro.S b/arch/arm/mach-clps7500/include/mach/entry-macro.S
deleted file mode 100644
index 4e7e54144093..000000000000
--- a/arch/arm/mach-clps7500/include/mach/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
1#include <mach/hardware.h>
2#include <asm/hardware/entry-macro-iomd.S>
3
4 .equ ioc_base_high, IOC_BASE & 0xff000000
5 .equ ioc_base_low, IOC_BASE & 0x00ff0000
6
7 .macro get_irqnr_preamble, base, tmp
8 mov \base, #ioc_base_high @ point at IOC
9 .if ioc_base_low
10 orr \base, \base, #ioc_base_low
11 .endif
12 .endm
13
14 .macro arch_ret_to_user, tmp1, tmp2
15 .endm
16
diff --git a/arch/arm/mach-clps7500/include/mach/hardware.h b/arch/arm/mach-clps7500/include/mach/hardware.h
deleted file mode 100644
index a6ad1d44badf..000000000000
--- a/arch/arm/mach-clps7500/include/mach/hardware.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/hardware.h
3 *
4 * Copyright (C) 1996-1999 Russell King.
5 * Copyright (C) 1999 Nexus Electronics Ltd.
6 *
7 * This file contains the hardware definitions of the
8 * CL7500 evaluation board.
9 */
10#ifndef __ASM_ARCH_HARDWARE_H
11#define __ASM_ARCH_HARDWARE_H
12
13#include <mach/memory.h>
14#include <asm/hardware/iomd.h>
15
16#ifdef __ASSEMBLY__
17#define IOMEM(x) x
18#else
19#define IOMEM(x) ((void __iomem *)(x))
20#endif
21
22/*
23 * What hardware must be present
24 */
25#define HAS_IOMD
26#define HAS_VIDC20
27
28/* Hardware addresses of major areas.
29 * *_START is the physical address
30 * *_SIZE is the size of the region
31 * *_BASE is the virtual address
32 */
33
34#define IO_START 0x03000000 /* I/O */
35#define IO_SIZE 0x01000000
36#define IO_BASE IOMEM(0xe0000000)
37
38#define ISA_START 0x0c000000 /* ISA */
39#define ISA_SIZE 0x00010000
40#define ISA_BASE 0xe1000000
41
42#define CLPS7500_FLASH_START 0x01000000 /* XXX */
43#define CLPS7500_FLASH_SIZE 0x01000000
44#define CLPS7500_FLASH_BASE 0xe2000000
45
46#define LED_START 0x0302B000
47#define LED_SIZE 0x00001000
48#define LED_BASE 0xe3000000
49#define LED_ADDRESS (LED_BASE + 0xa00)
50
51/* Let's define SCREEN_START for CL7500, even though it's a lie. */
52#define SCREEN_START 0x02000000 /* VRAM */
53#define SCREEN_END 0xdfc00000
54#define SCREEN_BASE 0xdf800000
55
56#define VIDC_BASE (void __iomem *)0xe0400000
57#define IOMD_BASE IOMEM(0xe0200000)
58#define IOC_BASE IOMEM(0xe0200000)
59#define FLOPPYDMA_BASE IOMEM(0xe002a000)
60#define PCIO_BASE IOMEM(0xe0010000)
61
62#define vidc_writel(val) __raw_writel(val, VIDC_BASE)
63
64/* in/out bias for the ISA slot region */
65#define ISASLOT_IO 0x80400000
66
67#endif
diff --git a/arch/arm/mach-clps7500/include/mach/io.h b/arch/arm/mach-clps7500/include/mach/io.h
deleted file mode 100644
index 2ff2860889ed..000000000000
--- a/arch/arm/mach-clps7500/include/mach/io.h
+++ /dev/null
@@ -1,255 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/io.h
3 * from arch/arm/mach-rpc/include/mach/io.h
4 *
5 * Copyright (C) 1997 Russell King
6 *
7 * Modifications:
8 * 06-Dec-1997 RMK Created.
9 */
10#ifndef __ASM_ARM_ARCH_IO_H
11#define __ASM_ARM_ARCH_IO_H
12
13#include <mach/hardware.h>
14
15#define IO_SPACE_LIMIT 0xffffffff
16
17/*
18 * GCC is totally crap at loading/storing data. We try to persuade it
19 * to do the right thing by using these whereever possible instead of
20 * the above.
21 */
22#define __arch_base_getb(b,o) \
23 ({ \
24 unsigned int v, r = (b); \
25 __asm__ __volatile__( \
26 "ldrb %0, [%1, %2]" \
27 : "=r" (v) \
28 : "r" (r), "Ir" (o)); \
29 v; \
30 })
31
32#define __arch_base_getl(b,o) \
33 ({ \
34 unsigned int v, r = (b); \
35 __asm__ __volatile__( \
36 "ldr %0, [%1, %2]" \
37 : "=r" (v) \
38 : "r" (r), "Ir" (o)); \
39 v; \
40 })
41
42#define __arch_base_putb(v,b,o) \
43 ({ \
44 unsigned int r = (b); \
45 __asm__ __volatile__( \
46 "strb %0, [%1, %2]" \
47 : \
48 : "r" (v), "r" (r), "Ir" (o)); \
49 })
50
51#define __arch_base_putl(v,b,o) \
52 ({ \
53 unsigned int r = (b); \
54 __asm__ __volatile__( \
55 "str %0, [%1, %2]" \
56 : \
57 : "r" (v), "r" (r), "Ir" (o)); \
58 })
59
60/*
61 * We use two different types of addressing - PC style addresses, and ARM
62 * addresses. PC style accesses the PC hardware with the normal PC IO
63 * addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+
64 * and are translated to the start of IO. Note that all addresses are
65 * shifted left!
66 */
67#define __PORT_PCIO(x) (!((x) & 0x80000000))
68
69/*
70 * Dynamic IO functions - let the compiler
71 * optimize the expressions
72 */
73static inline void __outb (unsigned int value, unsigned int port)
74{
75 unsigned long temp;
76 __asm__ __volatile__(
77 "tst %2, #0x80000000\n\t"
78 "mov %0, %4\n\t"
79 "addeq %0, %0, %3\n\t"
80 "strb %1, [%0, %2, lsl #2] @ outb"
81 : "=&r" (temp)
82 : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
83 : "cc");
84}
85
86static inline void __outw (unsigned int value, unsigned int port)
87{
88 unsigned long temp;
89 __asm__ __volatile__(
90 "tst %2, #0x80000000\n\t"
91 "mov %0, %4\n\t"
92 "addeq %0, %0, %3\n\t"
93 "str %1, [%0, %2, lsl #2] @ outw"
94 : "=&r" (temp)
95 : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
96 : "cc");
97}
98
99static inline void __outl (unsigned int value, unsigned int port)
100{
101 unsigned long temp;
102 __asm__ __volatile__(
103 "tst %2, #0x80000000\n\t"
104 "mov %0, %4\n\t"
105 "addeq %0, %0, %3\n\t"
106 "str %1, [%0, %2, lsl #2] @ outl"
107 : "=&r" (temp)
108 : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
109 : "cc");
110}
111
112#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
113static inline unsigned sz __in##fnsuffix (unsigned int port) \
114{ \
115 unsigned long temp, value; \
116 __asm__ __volatile__( \
117 "tst %2, #0x80000000\n\t" \
118 "mov %0, %4\n\t" \
119 "addeq %0, %0, %3\n\t" \
120 "ldr" instr " %1, [%0, %2, lsl #2] @ in" #fnsuffix \
121 : "=&r" (temp), "=r" (value) \
122 : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \
123 : "cc"); \
124 return (unsigned sz)value; \
125}
126
127static inline unsigned int __ioaddr (unsigned int port) \
128{ \
129 if (__PORT_PCIO(port)) \
130 return (unsigned int)(PCIO_BASE + (port << 2)); \
131 else \
132 return (unsigned int)(IO_BASE + (port << 2)); \
133}
134
135#define DECLARE_IO(sz,fnsuffix,instr) \
136 DECLARE_DYN_IN(sz,fnsuffix,instr)
137
138DECLARE_IO(char,b,"b")
139DECLARE_IO(short,w,"")
140DECLARE_IO(int,l,"")
141
142#undef DECLARE_IO
143#undef DECLARE_DYN_IN
144
145/*
146 * Constant address IO functions
147 *
148 * These have to be macros for the 'J' constraint to work -
149 * +/-4096 immediate operand.
150 */
151#define __outbc(value,port) \
152({ \
153 if (__PORT_PCIO((port))) \
154 __asm__ __volatile__( \
155 "strb %0, [%1, %2] @ outbc" \
156 : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
157 else \
158 __asm__ __volatile__( \
159 "strb %0, [%1, %2] @ outbc" \
160 : : "r" (value), "r" (IO_BASE), "r" ((port) << 2)); \
161})
162
163#define __inbc(port) \
164({ \
165 unsigned char result; \
166 if (__PORT_PCIO((port))) \
167 __asm__ __volatile__( \
168 "ldrb %0, [%1, %2] @ inbc" \
169 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
170 else \
171 __asm__ __volatile__( \
172 "ldrb %0, [%1, %2] @ inbc" \
173 : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
174 result; \
175})
176
177#define __outwc(value,port) \
178({ \
179 unsigned long v = value; \
180 if (__PORT_PCIO((port))) \
181 __asm__ __volatile__( \
182 "str %0, [%1, %2] @ outwc" \
183 : : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
184 else \
185 __asm__ __volatile__( \
186 "str %0, [%1, %2] @ outwc" \
187 : : "r" (v|v<<16), "r" (IO_BASE), "r" ((port) << 2)); \
188})
189
190#define __inwc(port) \
191({ \
192 unsigned short result; \
193 if (__PORT_PCIO((port))) \
194 __asm__ __volatile__( \
195 "ldr %0, [%1, %2] @ inwc" \
196 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
197 else \
198 __asm__ __volatile__( \
199 "ldr %0, [%1, %2] @ inwc" \
200 : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
201 result & 0xffff; \
202})
203
204#define __outlc(value,port) \
205({ \
206 unsigned long v = value; \
207 if (__PORT_PCIO((port))) \
208 __asm__ __volatile__( \
209 "str %0, [%1, %2] @ outlc" \
210 : : "r" (v), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
211 else \
212 __asm__ __volatile__( \
213 "str %0, [%1, %2] @ outlc" \
214 : : "r" (v), "r" (IO_BASE), "r" ((port) << 2)); \
215})
216
217#define __inlc(port) \
218({ \
219 unsigned long result; \
220 if (__PORT_PCIO((port))) \
221 __asm__ __volatile__( \
222 "ldr %0, [%1, %2] @ inlc" \
223 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
224 else \
225 __asm__ __volatile__( \
226 "ldr %0, [%1, %2] @ inlc" \
227 : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
228 result; \
229})
230
231#define __ioaddrc(port) \
232 (__PORT_PCIO((port)) ? PCIO_BASE + ((port) << 2) : IO_BASE + ((port) << 2))
233
234#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
235#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
236#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p))
237#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
238#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
239#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
240#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p))
241/* the following macro is deprecated */
242#define ioaddr(port) __ioaddr((port))
243
244#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l)
245#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l)
246
247#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l)
248#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
249
250/*
251 * 1:1 mapping for ioremapped regions.
252 */
253#define __mem_pci(x) (x)
254
255#endif
diff --git a/arch/arm/mach-clps7500/include/mach/irq.h b/arch/arm/mach-clps7500/include/mach/irq.h
deleted file mode 100644
index d02fcf28ee05..000000000000
--- a/arch/arm/mach-clps7500/include/mach/irq.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/irq.h
3 *
4 * Copyright (C) 1996 Russell King
5 * Copyright (C) 1999, 2001 Nexus Electronics Ltd.
6 *
7 * Changelog:
8 * 10-10-1996 RMK Brought up to date with arch-sa110eval
9 * 22-08-1998 RMK Restructured IRQ routines
10 * 11-08-1999 PJB Created ARM7500 version, derived from RiscPC code
11 */
12
13#include <linux/io.h>
14#include <asm/hardware/iomd.h>
15
16static inline int fixup_irq(unsigned int irq)
17{
18 if (irq == IRQ_ISA) {
19 int isabits = *((volatile unsigned int *)0xe002b700);
20 if (isabits == 0) {
21 printk("Spurious ISA IRQ!\n");
22 return irq;
23 }
24 irq = IRQ_ISA_BASE;
25 while (!(isabits & 1)) {
26 irq++;
27 isabits >>= 1;
28 }
29 }
30
31 return irq;
32}
diff --git a/arch/arm/mach-clps7500/include/mach/irqs.h b/arch/arm/mach-clps7500/include/mach/irqs.h
deleted file mode 100644
index bee66b487f59..000000000000
--- a/arch/arm/mach-clps7500/include/mach/irqs.h
+++ /dev/null
@@ -1,66 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/irqs.h
3 *
4 * Copyright (C) 1999 Nexus Electronics Ltd
5 */
6
7#define IRQ_INT2 0
8#define IRQ_INT1 2
9#define IRQ_VSYNCPULSE 3
10#define IRQ_POWERON 4
11#define IRQ_TIMER0 5
12#define IRQ_TIMER1 6
13#define IRQ_FORCE 7
14#define IRQ_INT8 8
15#define IRQ_ISA 9
16#define IRQ_INT6 10
17#define IRQ_INT5 11
18#define IRQ_INT4 12
19#define IRQ_INT3 13
20#define IRQ_KEYBOARDTX 14
21#define IRQ_KEYBOARDRX 15
22
23#define IRQ_DMA0 16
24#define IRQ_DMA1 17
25#define IRQ_DMA2 18
26#define IRQ_DMA3 19
27#define IRQ_DMAS0 20
28#define IRQ_DMAS1 21
29
30#define IRQ_IOP0 24
31#define IRQ_IOP1 25
32#define IRQ_IOP2 26
33#define IRQ_IOP3 27
34#define IRQ_IOP4 28
35#define IRQ_IOP5 29
36#define IRQ_IOP6 30
37#define IRQ_IOP7 31
38
39#define IRQ_MOUSERX 40
40#define IRQ_MOUSETX 41
41#define IRQ_ADC 42
42#define IRQ_EVENT1 43
43#define IRQ_EVENT2 44
44
45#define IRQ_ISA_BASE 48
46#define IRQ_ISA_3 48
47#define IRQ_ISA_4 49
48#define IRQ_ISA_5 50
49#define IRQ_ISA_7 51
50#define IRQ_ISA_9 52
51#define IRQ_ISA_10 53
52#define IRQ_ISA_11 54
53#define IRQ_ISA_14 55
54
55#define FIQ_INT9 0
56#define FIQ_INT5 1
57#define FIQ_INT6 4
58#define FIQ_INT8 6
59#define FIQ_FORCE 7
60
61/*
62 * This is the offset of the FIQ "IRQ" numbers
63 */
64#define FIQ_START 64
65
66#define IRQ_TIMER IRQ_TIMER0
diff --git a/arch/arm/mach-clps7500/include/mach/memory.h b/arch/arm/mach-clps7500/include/mach/memory.h
deleted file mode 100644
index 87b32db470c8..000000000000
--- a/arch/arm/mach-clps7500/include/mach/memory.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/memory.h
3 *
4 * Copyright (c) 1996,1997,1998 Russell King.
5 *
6 * Changelog:
7 * 20-Oct-1996 RMK Created
8 * 31-Dec-1997 RMK Fixed definitions to reduce warnings
9 * 11-Jan-1998 RMK Uninlined to reduce hits on cache
10 * 08-Feb-1998 RMK Added __virt_to_bus and __bus_to_virt
11 * 21-Mar-1999 RMK Renamed to memory.h
12 * RMK Added TASK_SIZE and PAGE_OFFSET
13 */
14#ifndef __ASM_ARCH_MEMORY_H
15#define __ASM_ARCH_MEMORY_H
16
17/*
18 * Physical DRAM offset.
19 */
20#define PHYS_OFFSET UL(0x10000000)
21
22/*
23 * These are exactly the same on the RiscPC as the
24 * physical memory view.
25 */
26#define __virt_to_bus(x) __virt_to_phys(x)
27#define __bus_to_virt(x) __phys_to_virt(x)
28
29/*
30 * Cache flushing area - ROM
31 */
32#define FLUSH_BASE_PHYS 0x00000000
33#define FLUSH_BASE 0xdf000000
34
35/*
36 * Sparsemem support. Each section is a maximum of 64MB. The sections
37 * are offset by 128MB and can cover 128MB, so that gives us a maximum
38 * of 29 physmem bits.
39 */
40#define MAX_PHYSMEM_BITS 29
41#define SECTION_SIZE_BITS 26
42
43#endif
diff --git a/arch/arm/mach-clps7500/include/mach/system.h b/arch/arm/mach-clps7500/include/mach/system.h
deleted file mode 100644
index 6d325fbe8b08..000000000000
--- a/arch/arm/mach-clps7500/include/mach/system.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/system.h
3 *
4 * Copyright (c) 1999 Nexus Electronics Ltd.
5 */
6#ifndef __ASM_ARCH_SYSTEM_H
7#define __ASM_ARCH_SYSTEM_H
8
9#include <linux/io.h>
10#include <asm/hardware/iomd.h>
11
12static inline void arch_idle(void)
13{
14 iomd_writeb(0, IOMD_SUSMODE);
15}
16
17#define arch_reset(mode) \
18 do { \
19 iomd_writeb(0, IOMD_ROMCR0); \
20 cpu_reset(0); \
21 } while (0)
22
23#endif
diff --git a/arch/arm/mach-clps7500/include/mach/timex.h b/arch/arm/mach-clps7500/include/mach/timex.h
deleted file mode 100644
index dfaa9b425757..000000000000
--- a/arch/arm/mach-clps7500/include/mach/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/timex.h
3 *
4 * CL7500 architecture timex specifications
5 *
6 * Copyright (C) 1999 Nexus Electronics Ltd
7 */
8
9/*
10 * On the ARM7500, the clock ticks at 2MHz.
11 */
12#define CLOCK_TICK_RATE 2000000
13
diff --git a/arch/arm/mach-clps7500/include/mach/uncompress.h b/arch/arm/mach-clps7500/include/mach/uncompress.h
deleted file mode 100644
index d7d0af4b49fc..000000000000
--- a/arch/arm/mach-clps7500/include/mach/uncompress.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/uncompress.h
3 *
4 * Copyright (C) 1999, 2000 Nexus Electronics Ltd.
5 */
6#define BASE 0x03010000
7#define SERBASE (BASE + (0x2f8 << 2))
8
9static inline void putc(char c)
10{
11 while (!(*((volatile unsigned int *)(SERBASE + 0x14)) & 0x20))
12 barrier();
13
14 *((volatile unsigned int *)(SERBASE)) = c;
15}
16
17static inline void flush(void)
18{
19}
20
21static __inline__ void arch_decomp_setup(void)
22{
23 int baud = 3686400 / (9600 * 32);
24
25 *((volatile unsigned int *)(SERBASE + 0xC)) = 0x80;
26 *((volatile unsigned int *)(SERBASE + 0x0)) = baud & 0xff;
27 *((volatile unsigned int *)(SERBASE + 0x4)) = (baud & 0xff00) >> 8;
28 *((volatile unsigned int *)(SERBASE + 0xC)) = 3; /* 8 bits */
29 *((volatile unsigned int *)(SERBASE + 0x10)) = 3; /* DTR, RTS */
30}
31
32/*
33 * nothing to do
34 */
35#define arch_decomp_wdog()
diff --git a/arch/arm/mach-clps7500/include/mach/vmalloc.h b/arch/arm/mach-clps7500/include/mach/vmalloc.h
deleted file mode 100644
index 8fc5406d1b6d..000000000000
--- a/arch/arm/mach-clps7500/include/mach/vmalloc.h
+++ /dev/null
@@ -1,4 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/vmalloc.h
3 */
4#define VMALLOC_END (PAGE_OFFSET + 0x1c000000)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 17:10:30 -0500