diff options
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-imx/irq.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-integrator/integrator_cp.c | 5 | ||||
-rw-r--r-- | arch/arm/mach-pxa/spitz.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-sa1100/neponset.c | 8 | ||||
-rw-r--r-- | arch/arm/mach-versatile/core.c | 5 |
5 files changed, 13 insertions, 8 deletions
diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c index eeb8a6d4a399..a5de5f1da9f2 100644 --- a/arch/arm/mach-imx/irq.c +++ b/arch/arm/mach-imx/irq.c | |||
@@ -127,7 +127,7 @@ static void | |||
127 | imx_gpio_ack_irq(unsigned int irq) | 127 | imx_gpio_ack_irq(unsigned int irq) |
128 | { | 128 | { |
129 | DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq); | 129 | DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq); |
130 | ISR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32); | 130 | ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32); |
131 | } | 131 | } |
132 | 132 | ||
133 | static void | 133 | static void |
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index a0724f2b24ce..9f55f5ae1044 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c | |||
@@ -232,8 +232,6 @@ static void __init intcp_init_irq(void) | |||
232 | for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) { | 232 | for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) { |
233 | if (i == 11) | 233 | if (i == 11) |
234 | i = 22; | 234 | i = 22; |
235 | if (i == IRQ_CP_CPPLDINT) | ||
236 | i++; | ||
237 | if (i == 29) | 235 | if (i == 29) |
238 | break; | 236 | break; |
239 | set_irq_chip(i, &pic_chip); | 237 | set_irq_chip(i, &pic_chip); |
@@ -259,8 +257,7 @@ static void __init intcp_init_irq(void) | |||
259 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 257 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
260 | } | 258 | } |
261 | 259 | ||
262 | set_irq_handler(IRQ_CP_CPPLDINT, sic_handle_irq); | 260 | set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq); |
263 | pic_unmask_irq(IRQ_CP_CPPLDINT); | ||
264 | } | 261 | } |
265 | 262 | ||
266 | /* | 263 | /* |
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 19b372df544a..44bcb8097c7a 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c | |||
@@ -371,6 +371,7 @@ static int spitz_ohci_init(struct device *dev) | |||
371 | static struct pxaohci_platform_data spitz_ohci_platform_data = { | 371 | static struct pxaohci_platform_data spitz_ohci_platform_data = { |
372 | .port_mode = PMM_NPS_MODE, | 372 | .port_mode = PMM_NPS_MODE, |
373 | .init = spitz_ohci_init, | 373 | .init = spitz_ohci_init, |
374 | .power_budget = 150, | ||
374 | }; | 375 | }; |
375 | 376 | ||
376 | 377 | ||
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 9e02bc3712a0..af6d2775cf82 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c | |||
@@ -59,6 +59,14 @@ neponset_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *reg | |||
59 | if (irr & (IRR_ETHERNET | IRR_USAR)) { | 59 | if (irr & (IRR_ETHERNET | IRR_USAR)) { |
60 | desc->chip->mask(irq); | 60 | desc->chip->mask(irq); |
61 | 61 | ||
62 | /* | ||
63 | * Ack the interrupt now to prevent re-entering | ||
64 | * this neponset handler. Again, this is safe | ||
65 | * since we'll check the IRR register prior to | ||
66 | * leaving. | ||
67 | */ | ||
68 | desc->chip->ack(irq); | ||
69 | |||
62 | if (irr & IRR_ETHERNET) { | 70 | if (irr & IRR_ETHERNET) { |
63 | d = irq_desc + IRQ_NEPONSET_SMC9196; | 71 | d = irq_desc + IRQ_NEPONSET_SMC9196; |
64 | desc_handle_irq(IRQ_NEPONSET_SMC9196, d, regs); | 72 | desc_handle_irq(IRQ_NEPONSET_SMC9196, d, regs); |
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 799697d32dec..cebd48a3dae4 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c | |||
@@ -112,10 +112,9 @@ void __init versatile_init_irq(void) | |||
112 | { | 112 | { |
113 | unsigned int i; | 113 | unsigned int i; |
114 | 114 | ||
115 | vic_init(VA_VIC_BASE, IRQ_VIC_START, ~(1 << 31)); | 115 | vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0); |
116 | 116 | ||
117 | set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq); | 117 | set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq); |
118 | enable_irq(IRQ_VICSOURCE31); | ||
119 | 118 | ||
120 | /* Do second interrupt controller */ | 119 | /* Do second interrupt controller */ |
121 | writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); | 120 | writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); |