aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-orion5x/include/mach/gpio.h3
-rw-r--r--arch/arm/mach-orion5x/include/mach/orion5x.h3
-rw-r--r--arch/arm/mach-orion5x/irq.c183
-rw-r--r--arch/arm/plat-orion/gpio.c176
-rw-r--r--arch/arm/plat-orion/include/plat/gpio.h7
5 files changed, 200 insertions, 172 deletions
diff --git a/arch/arm/mach-orion5x/include/mach/gpio.h b/arch/arm/mach-orion5x/include/mach/gpio.h
index a1a387b189a0..d8182e87ac16 100644
--- a/arch/arm/mach-orion5x/include/mach/gpio.h
+++ b/arch/arm/mach-orion5x/include/mach/gpio.h
@@ -19,6 +19,9 @@
19#define GPIO_BLINK_EN(pin) ORION5X_DEV_BUS_REG(0x108) 19#define GPIO_BLINK_EN(pin) ORION5X_DEV_BUS_REG(0x108)
20#define GPIO_IN_POL(pin) ORION5X_DEV_BUS_REG(0x10c) 20#define GPIO_IN_POL(pin) ORION5X_DEV_BUS_REG(0x10c)
21#define GPIO_DATA_IN(pin) ORION5X_DEV_BUS_REG(0x110) 21#define GPIO_DATA_IN(pin) ORION5X_DEV_BUS_REG(0x110)
22#define GPIO_EDGE_CAUSE(pin) ORION5X_DEV_BUS_REG(0x114)
23#define GPIO_EDGE_MASK(pin) ORION5X_DEV_BUS_REG(0x118)
24#define GPIO_LEVEL_MASK(pin) ORION5X_DEV_BUS_REG(0x11c)
22 25
23static inline int gpio_to_irq(int pin) 26static inline int gpio_to_irq(int pin)
24{ 27{
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index a8915081773b..67bda31406dd 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -134,9 +134,6 @@
134#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) 134#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050)
135#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) 135#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008)
136#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) 136#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010)
137#define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114)
138#define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118)
139#define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c)
140#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) 137#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c)
141#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) 138#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460)
142#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) 139#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464)
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index 6b2f1353797e..0caae43301e5 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -19,193 +19,38 @@
19#include <plat/irq.h> 19#include <plat/irq.h>
20#include "common.h" 20#include "common.h"
21 21
22/***************************************************************************** 22static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
23 * Orion GPIO IRQ
24 *
25 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
26 * value of the line or the opposite value.
27 *
28 * Level IRQ handlers: DATA_IN is used directly as cause register.
29 * Interrupt are masked by LEVEL_MASK registers.
30 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
31 * Interrupt are masked by EDGE_MASK registers.
32 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
33 * the polarity to catch the next line transaction.
34 * This is a race condition that might not perfectly
35 * work on some use cases.
36 *
37 * Every eight GPIO lines are grouped (OR'ed) before going up to main
38 * cause register.
39 *
40 * EDGE cause mask
41 * data-in /--------| |-----| |----\
42 * -----| |----- ---- to main cause reg
43 * X \----------------| |----/
44 * polarity LEVEL mask
45 *
46 ****************************************************************************/
47static void orion5x_gpio_irq_ack(u32 irq)
48{
49 int pin = irq_to_gpio(irq);
50 if (irq_desc[irq].status & IRQ_LEVEL)
51 /*
52 * Mask bit for level interrupt
53 */
54 orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
55 else
56 /*
57 * Clear casue bit for egde interrupt
58 */
59 orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
60}
61
62static void orion5x_gpio_irq_mask(u32 irq)
63{
64 int pin = irq_to_gpio(irq);
65 if (irq_desc[irq].status & IRQ_LEVEL)
66 orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
67 else
68 orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin);
69}
70
71static void orion5x_gpio_irq_unmask(u32 irq)
72{ 23{
73 int pin = irq_to_gpio(irq);
74 if (irq_desc[irq].status & IRQ_LEVEL)
75 orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin);
76 else
77 orion5x_setbits(GPIO_EDGE_MASK, 1 << pin);
78}
79
80static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
81{
82 int pin = irq_to_gpio(irq);
83 struct irq_desc *desc;
84
85 if ((readl(GPIO_IO_CONF(pin)) & (1 << pin)) == 0) {
86 printk(KERN_ERR "orion5x_gpio_set_irq_type failed "
87 "(irq %d, pin %d).\n", irq, pin);
88 return -EINVAL;
89 }
90
91 desc = irq_desc + irq;
92
93 switch (type) {
94 case IRQ_TYPE_LEVEL_HIGH:
95 desc->handle_irq = handle_level_irq;
96 desc->status |= IRQ_LEVEL;
97 orion5x_clrbits(GPIO_IN_POL(pin), (1 << pin));
98 break;
99 case IRQ_TYPE_LEVEL_LOW:
100 desc->handle_irq = handle_level_irq;
101 desc->status |= IRQ_LEVEL;
102 orion5x_setbits(GPIO_IN_POL(pin), (1 << pin));
103 break;
104 case IRQ_TYPE_EDGE_RISING:
105 desc->handle_irq = handle_edge_irq;
106 desc->status &= ~IRQ_LEVEL;
107 orion5x_clrbits(GPIO_IN_POL(pin), (1 << pin));
108 break;
109 case IRQ_TYPE_EDGE_FALLING:
110 desc->handle_irq = handle_edge_irq;
111 desc->status &= ~IRQ_LEVEL;
112 orion5x_setbits(GPIO_IN_POL(pin), (1 << pin));
113 break;
114 case IRQ_TYPE_EDGE_BOTH:
115 desc->handle_irq = handle_edge_irq;
116 desc->status &= ~IRQ_LEVEL;
117 /*
118 * set initial polarity based on current input level
119 */
120 if ((readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin)))
121 & (1 << pin))
122 orion5x_setbits(GPIO_IN_POL(pin), (1 << pin)); /* falling */
123 else
124 orion5x_clrbits(GPIO_IN_POL(pin), (1 << pin)); /* rising */
125
126 break;
127 default:
128 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
129 return -EINVAL;
130 }
131
132 desc->status &= ~IRQ_TYPE_SENSE_MASK;
133 desc->status |= type & IRQ_TYPE_SENSE_MASK;
134
135 return 0;
136}
137
138static struct irq_chip orion5x_gpio_irq_chip = {
139 .name = "Orion-IRQ-GPIO",
140 .ack = orion5x_gpio_irq_ack,
141 .mask = orion5x_gpio_irq_mask,
142 .unmask = orion5x_gpio_irq_unmask,
143 .set_type = orion5x_gpio_set_irq_type,
144};
145
146static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
147{
148 u32 cause, offs, pin;
149
150 BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); 24 BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31);
151 offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8;
152 cause = (readl(GPIO_DATA_IN(offs)) & readl(GPIO_LEVEL_MASK)) |
153 (readl(GPIO_EDGE_CAUSE) & readl(GPIO_EDGE_MASK));
154 25
155 for (pin = offs; pin < offs + 8; pin++) { 26 orion_gpio_irq_handler((irq - IRQ_ORION5X_GPIO_0_7) << 3);
156 if (cause & (1 << pin)) {
157 irq = gpio_to_irq(pin);
158 desc = irq_desc + irq;
159 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
160 /* Swap polarity (race with GPIO line) */
161 u32 polarity = readl(GPIO_IN_POL(pin));
162 polarity ^= 1 << pin;
163 writel(polarity, GPIO_IN_POL(pin));
164 }
165 generic_handle_irq(irq);
166 }
167 }
168} 27}
169 28
170static void __init orion5x_init_gpio_irq(void) 29void __init orion5x_init_irq(void)
171{ 30{
172 int i; 31 int i;
173 struct irq_desc *desc; 32
33 orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
174 34
175 /* 35 /*
176 * Mask and clear GPIO IRQ interrupts 36 * Mask and clear GPIO IRQ interrupts
177 */ 37 */
178 writel(0x0, GPIO_LEVEL_MASK); 38 writel(0x0, GPIO_LEVEL_MASK(0));
179 writel(0x0, GPIO_EDGE_MASK); 39 writel(0x0, GPIO_EDGE_MASK(0));
180 writel(0x0, GPIO_EDGE_CAUSE); 40 writel(0x0, GPIO_EDGE_CAUSE(0));
181 41
182 /* 42 /*
183 * Register chained level handlers for GPIO IRQs by default. 43 * Register chained level handlers for GPIO IRQs by default.
184 * User can use set_type() if he wants to use edge types handlers. 44 * User can use set_type() if he wants to use edge types handlers.
185 */ 45 */
186 for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) { 46 for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
187 set_irq_chip(i, &orion5x_gpio_irq_chip); 47 set_irq_chip(i, &orion_gpio_irq_level_chip);
188 set_irq_handler(i, handle_level_irq); 48 set_irq_handler(i, handle_level_irq);
189 desc = irq_desc + i; 49 irq_desc[i].status |= IRQ_LEVEL;
190 desc->status |= IRQ_LEVEL;
191 set_irq_flags(i, IRQF_VALID); 50 set_irq_flags(i, IRQF_VALID);
192 } 51 }
193 set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler); 52 set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
194 set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler); 53 set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
195 set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler); 54 set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
196 set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler); 55 set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler);
197}
198
199/*****************************************************************************
200 * Orion Main IRQ
201 ****************************************************************************/
202static void __init orion5x_init_main_irq(void)
203{
204 orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
205}
206
207void __init orion5x_init_irq(void)
208{
209 orion5x_init_main_irq();
210 orion5x_init_gpio_irq();
211} 56}
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index d86fc085e489..967186425ca1 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -10,6 +10,7 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/irq.h>
13#include <linux/module.h> 14#include <linux/module.h>
14#include <linux/spinlock.h> 15#include <linux/spinlock.h>
15#include <linux/bitops.h> 16#include <linux/bitops.h>
@@ -237,3 +238,178 @@ void orion_gpio_set_blink(unsigned pin, int blink)
237 spin_unlock_irqrestore(&gpio_lock, flags); 238 spin_unlock_irqrestore(&gpio_lock, flags);
238} 239}
239EXPORT_SYMBOL(orion_gpio_set_blink); 240EXPORT_SYMBOL(orion_gpio_set_blink);
241
242
243/*****************************************************************************
244 * Orion GPIO IRQ
245 *
246 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
247 * value of the line or the opposite value.
248 *
249 * Level IRQ handlers: DATA_IN is used directly as cause register.
250 * Interrupt are masked by LEVEL_MASK registers.
251 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
252 * Interrupt are masked by EDGE_MASK registers.
253 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
254 * the polarity to catch the next line transaction.
255 * This is a race condition that might not perfectly
256 * work on some use cases.
257 *
258 * Every eight GPIO lines are grouped (OR'ed) before going up to main
259 * cause register.
260 *
261 * EDGE cause mask
262 * data-in /--------| |-----| |----\
263 * -----| |----- ---- to main cause reg
264 * X \----------------| |----/
265 * polarity LEVEL mask
266 *
267 ****************************************************************************/
268static void gpio_irq_edge_ack(u32 irq)
269{
270 int pin = irq_to_gpio(irq);
271
272 writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
273}
274
275static void gpio_irq_edge_mask(u32 irq)
276{
277 int pin = irq_to_gpio(irq);
278 u32 u;
279
280 u = readl(GPIO_EDGE_MASK(pin));
281 u &= ~(1 << (pin & 31));
282 writel(u, GPIO_EDGE_MASK(pin));
283}
284
285static void gpio_irq_edge_unmask(u32 irq)
286{
287 int pin = irq_to_gpio(irq);
288 u32 u;
289
290 u = readl(GPIO_EDGE_MASK(pin));
291 u |= 1 << (pin & 31);
292 writel(u, GPIO_EDGE_MASK(pin));
293}
294
295static void gpio_irq_level_mask(u32 irq)
296{
297 int pin = irq_to_gpio(irq);
298 u32 u;
299
300 u = readl(GPIO_LEVEL_MASK(pin));
301 u &= ~(1 << (pin & 31));
302 writel(u, GPIO_LEVEL_MASK(pin));
303}
304
305static void gpio_irq_level_unmask(u32 irq)
306{
307 int pin = irq_to_gpio(irq);
308 u32 u;
309
310 u = readl(GPIO_LEVEL_MASK(pin));
311 u |= 1 << (pin & 31);
312 writel(u, GPIO_LEVEL_MASK(pin));
313}
314
315static int gpio_irq_set_type(u32 irq, u32 type)
316{
317 int pin = irq_to_gpio(irq);
318 struct irq_desc *desc;
319 u32 u;
320
321 u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31));
322 if (!u) {
323 printk(KERN_ERR "orion gpio_irq_set_type failed "
324 "(irq %d, pin %d).\n", irq, pin);
325 return -EINVAL;
326 }
327
328 desc = irq_desc + irq;
329
330 /*
331 * Set edge/level type.
332 */
333 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
334 desc->chip = &orion_gpio_irq_edge_chip;
335 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
336 desc->chip = &orion_gpio_irq_level_chip;
337 } else {
338 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
339 return -EINVAL;
340 }
341
342 /*
343 * Configure interrupt polarity.
344 */
345 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
346 u = readl(GPIO_IN_POL(pin));
347 u &= ~(1 << (pin & 31));
348 writel(u, GPIO_IN_POL(pin));
349 } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
350 u = readl(GPIO_IN_POL(pin));
351 u |= 1 << (pin & 31);
352 writel(u, GPIO_IN_POL(pin));
353 } else if (type == IRQ_TYPE_EDGE_BOTH) {
354 u32 v;
355
356 v = readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin));
357
358 /*
359 * set initial polarity based on current input level
360 */
361 u = readl(GPIO_IN_POL(pin));
362 if (v & (1 << (pin & 31)))
363 u |= 1 << (pin & 31); /* falling */
364 else
365 u &= ~(1 << (pin & 31)); /* rising */
366 writel(u, GPIO_IN_POL(pin));
367 }
368
369 desc->status = (desc->status & ~IRQ_TYPE_SENSE_MASK) | type;
370
371 return 0;
372}
373
374struct irq_chip orion_gpio_irq_edge_chip = {
375 .name = "orion_gpio_irq_edge",
376 .ack = gpio_irq_edge_ack,
377 .mask = gpio_irq_edge_mask,
378 .unmask = gpio_irq_edge_unmask,
379 .set_type = gpio_irq_set_type,
380};
381
382struct irq_chip orion_gpio_irq_level_chip = {
383 .name = "orion_gpio_irq_level",
384 .mask = gpio_irq_level_mask,
385 .mask_ack = gpio_irq_level_mask,
386 .unmask = gpio_irq_level_unmask,
387 .set_type = gpio_irq_set_type,
388};
389
390void orion_gpio_irq_handler(int pinoff)
391{
392 u32 cause;
393 int pin;
394
395 cause = readl(GPIO_DATA_IN(pinoff)) & readl(GPIO_LEVEL_MASK(pinoff));
396 cause |= readl(GPIO_EDGE_CAUSE(pinoff)) & readl(GPIO_EDGE_MASK(pinoff));
397
398 for (pin = pinoff; pin < pinoff + 8; pin++) {
399 int irq = gpio_to_irq(pin);
400 struct irq_desc *desc = irq_desc + irq;
401
402 if (!(cause & (1 << (pin & 31))))
403 continue;
404
405 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
406 /* Swap polarity (race with GPIO line) */
407 u32 polarity;
408
409 polarity = readl(GPIO_IN_POL(pin));
410 polarity ^= 1 << (pin & 31);
411 writel(polarity, GPIO_IN_POL(pin));
412 }
413 desc_handle_irq(irq, desc);
414 }
415}
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index 956658df269f..54deaf274b52 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -28,5 +28,12 @@ void orion_gpio_set_unused(unsigned pin);
28void orion_gpio_set_valid(unsigned pin, int valid); 28void orion_gpio_set_valid(unsigned pin, int valid);
29void orion_gpio_set_blink(unsigned pin, int blink); 29void orion_gpio_set_blink(unsigned pin, int blink);
30 30
31/*
32 * GPIO interrupt handling.
33 */
34extern struct irq_chip orion_gpio_irq_edge_chip;
35extern struct irq_chip orion_gpio_irq_level_chip;
36void orion_gpio_irq_handler(int irqoff);
37
31 38
32#endif 39#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 19:47:00 -0500