2 files changed, 79 insertions, 0 deletions

diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 9a803492b28f..73e2971b1757 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -1003,6 +1003,74 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
 }
 
 /**
+ * pwrdm_enable_hdwr_sar - enable automatic hardware SAR for a pwrdm
+ * @pwrdm: struct powerdomain *
+ *
+ * Enable automatic context save-and-restore upon power state change
+ * for some devices in a powerdomain.  Warning: this only affects a
+ * subset of devices in a powerdomain; check the TRM closely.  Returns
+ * -EINVAL if the powerdomain pointer is null or if the powerdomain
+ * does not support automatic save-and-restore, or returns 0 upon
+ * success.
+ */
+int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
+{
+        if (!pwrdm)
+                return -EINVAL;
+
+        if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
+                return -EINVAL;
+
+        pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
+                 pwrdm->name);
+
+        prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+                             pwrdm->prcm_offs, PM_PWSTCTRL);
+
+        return 0;
+}
+
+/**
+ * pwrdm_disable_hdwr_sar - disable automatic hardware SAR for a pwrdm
+ * @pwrdm: struct powerdomain *
+ *
+ * Disable automatic context save-and-restore upon power state change
+ * for some devices in a powerdomain.  Warning: this only affects a
+ * subset of devices in a powerdomain; check the TRM closely.  Returns
+ * -EINVAL if the powerdomain pointer is null or if the powerdomain
+ * does not support automatic save-and-restore, or returns 0 upon
+ * success.
+ */
+int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
+{
+        if (!pwrdm)
+                return -EINVAL;
+
+        if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
+                return -EINVAL;
+
+        pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
+                 pwrdm->name);
+
+        prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0,
+                             pwrdm->prcm_offs, PM_PWSTCTRL);
+
+        return 0;
+}
+
+/**
+ * pwrdm_has_hdwr_sar - test whether powerdomain supports hardware SAR
+ * @pwrdm: struct powerdomain *
+ *
+ * Returns 1 if powerdomain 'pwrdm' supports hardware save-and-restore
+ * for some devices, or 0 if it does not.
+ */
+bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
+{
+        return (pwrdm && pwrdm->flags & PWRDM_HAS_HDWR_SAR) ? 1 : 0;
+}
+
+/**
  * pwrdm_wait_transition - wait for powerdomain power transition to finish
  * @pwrdm: struct powerdomain * to wait for
  *
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/mach/powerdomain.h
index 5fa666fa9be8..2806a9c8e4d7 100644
--- a/arch/arm/plat-omap/include/mach/powerdomain.h
+++ b/arch/arm/plat-omap/include/mach/powerdomain.h
@@ -38,6 +38,10 @@
 #define PWRSTS_OFF_RET_ON       (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
 
 
+/* Powerdomain flags */
+#define PWRDM_HAS_HDWR_SAR      (1 << 0) /* hardware save-and-restore support */
+
+
 /*
  * Number of memory banks that are power-controllable.  On OMAP3430, the
  * maximum is 4.
@@ -96,6 +100,9 @@ struct powerdomain {
         /* Possible logic power states when pwrdm in RETENTION */
         const u8 pwrsts_logic_ret;
 
+        /* Powerdomain flags */
+        const u8 flags;
+
         /* Number of software-controllable memory banks in this powerdomain */
         const u8 banks;
 
@@ -150,6 +157,10 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
 
+int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
+int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
+bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
+
 int pwrdm_wait_transition(struct powerdomain *pwrdm);
 
 #endif