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-rw-r--r--arch/arm/mach-omap2/Makefile2
-rw-r--r--arch/arm/mach-omap2/iommu2.c362
-rw-r--r--arch/arm/plat-omap/include/plat/iommu.h272
3 files changed, 14 insertions, 622 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fe40d9e488c9..d6721a7f4c3b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -184,8 +184,6 @@ obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o
184obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o 184obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
185mailbox_mach-objs := mailbox.o 185mailbox_mach-objs := mailbox.o
186 186
187obj-$(CONFIG_OMAP_IOMMU) += iommu2.o
188
189iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o 187iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o
190obj-y += $(iommu-m) $(iommu-y) 188obj-y += $(iommu-m) $(iommu-y)
191 189
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
deleted file mode 100644
index e8116cf58e15..000000000000
--- a/arch/arm/mach-omap2/iommu2.c
+++ /dev/null
@@ -1,362 +0,0 @@
1/*
2 * omap iommu: omap2/3 architecture specific functions
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/err.h>
15#include <linux/device.h>
16#include <linux/jiffies.h>
17#include <linux/module.h>
18#include <linux/omap-iommu.h>
19#include <linux/slab.h>
20#include <linux/stringify.h>
21
22#include <plat/iommu.h>
23
24/*
25 * omap2 architecture specific register bit definitions
26 */
27#define IOMMU_ARCH_VERSION 0x00000011
28
29/* SYSCONF */
30#define MMU_SYS_IDLE_SHIFT 3
31#define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT)
32#define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT)
33#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT)
34#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT)
35
36#define MMU_SYS_SOFTRESET (1 << 1)
37#define MMU_SYS_AUTOIDLE 1
38
39/* SYSSTATUS */
40#define MMU_SYS_RESETDONE 1
41
42/* IRQSTATUS & IRQENABLE */
43#define MMU_IRQ_MULTIHITFAULT (1 << 4)
44#define MMU_IRQ_TABLEWALKFAULT (1 << 3)
45#define MMU_IRQ_EMUMISS (1 << 2)
46#define MMU_IRQ_TRANSLATIONFAULT (1 << 1)
47#define MMU_IRQ_TLBMISS (1 << 0)
48
49#define __MMU_IRQ_FAULT \
50 (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
51#define MMU_IRQ_MASK \
52 (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
53#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
54#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
55
56/* MMU_CNTL */
57#define MMU_CNTL_SHIFT 1
58#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
59#define MMU_CNTL_EML_TLB (1 << 3)
60#define MMU_CNTL_TWL_EN (1 << 2)
61#define MMU_CNTL_MMU_EN (1 << 1)
62
63#define get_cam_va_mask(pgsz) \
64 (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
65 ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
66 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
67 ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
68
69
70static void __iommu_set_twl(struct omap_iommu *obj, bool on)
71{
72 u32 l = iommu_read_reg(obj, MMU_CNTL);
73
74 if (on)
75 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
76 else
77 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
78
79 l &= ~MMU_CNTL_MASK;
80 if (on)
81 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
82 else
83 l |= (MMU_CNTL_MMU_EN);
84
85 iommu_write_reg(obj, l, MMU_CNTL);
86}
87
88
89static int omap2_iommu_enable(struct omap_iommu *obj)
90{
91 u32 l, pa;
92 unsigned long timeout;
93
94 if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
95 return -EINVAL;
96
97 pa = virt_to_phys(obj->iopgd);
98 if (!IS_ALIGNED(pa, SZ_16K))
99 return -EINVAL;
100
101 iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
102
103 timeout = jiffies + msecs_to_jiffies(20);
104 do {
105 l = iommu_read_reg(obj, MMU_SYSSTATUS);
106 if (l & MMU_SYS_RESETDONE)
107 break;
108 } while (!time_after(jiffies, timeout));
109
110 if (!(l & MMU_SYS_RESETDONE)) {
111 dev_err(obj->dev, "can't take mmu out of reset\n");
112 return -ENODEV;
113 }
114
115 l = iommu_read_reg(obj, MMU_REVISION);
116 dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
117 (l >> 4) & 0xf, l & 0xf);
118
119 l = iommu_read_reg(obj, MMU_SYSCONFIG);
120 l &= ~MMU_SYS_IDLE_MASK;
121 l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
122 iommu_write_reg(obj, l, MMU_SYSCONFIG);
123
124 iommu_write_reg(obj, pa, MMU_TTB);
125
126 __iommu_set_twl(obj, true);
127
128 return 0;
129}
130
131static void omap2_iommu_disable(struct omap_iommu *obj)
132{
133 u32 l = iommu_read_reg(obj, MMU_CNTL);
134
135 l &= ~MMU_CNTL_MASK;
136 iommu_write_reg(obj, l, MMU_CNTL);
137 iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
138
139 dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
140}
141
142static void omap2_iommu_set_twl(struct omap_iommu *obj, bool on)
143{
144 __iommu_set_twl(obj, false);
145}
146
147static u32 omap2_iommu_fault_isr(struct omap_iommu *obj, u32 *ra)
148{
149 u32 stat, da;
150 u32 errs = 0;
151
152 stat = iommu_read_reg(obj, MMU_IRQSTATUS);
153 stat &= MMU_IRQ_MASK;
154 if (!stat) {
155 *ra = 0;
156 return 0;
157 }
158
159 da = iommu_read_reg(obj, MMU_FAULT_AD);
160 *ra = da;
161
162 if (stat & MMU_IRQ_TLBMISS)
163 errs |= OMAP_IOMMU_ERR_TLB_MISS;
164 if (stat & MMU_IRQ_TRANSLATIONFAULT)
165 errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
166 if (stat & MMU_IRQ_EMUMISS)
167 errs |= OMAP_IOMMU_ERR_EMU_MISS;
168 if (stat & MMU_IRQ_TABLEWALKFAULT)
169 errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
170 if (stat & MMU_IRQ_MULTIHITFAULT)
171 errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
172 iommu_write_reg(obj, stat, MMU_IRQSTATUS);
173
174 return errs;
175}
176
177static void omap2_tlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
178{
179 cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
180 cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
181}
182
183static void omap2_tlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
184{
185 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
186 iommu_write_reg(obj, cr->ram, MMU_RAM);
187}
188
189static u32 omap2_cr_to_virt(struct cr_regs *cr)
190{
191 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
192 u32 mask = get_cam_va_mask(cr->cam & page_size);
193
194 return cr->cam & mask;
195}
196
197static struct cr_regs *omap2_alloc_cr(struct omap_iommu *obj,
198 struct iotlb_entry *e)
199{
200 struct cr_regs *cr;
201
202 if (e->da & ~(get_cam_va_mask(e->pgsz))) {
203 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
204 e->da);
205 return ERR_PTR(-EINVAL);
206 }
207
208 cr = kmalloc(sizeof(*cr), GFP_KERNEL);
209 if (!cr)
210 return ERR_PTR(-ENOMEM);
211
212 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
213 cr->ram = e->pa | e->endian | e->elsz | e->mixed;
214
215 return cr;
216}
217
218static inline int omap2_cr_valid(struct cr_regs *cr)
219{
220 return cr->cam & MMU_CAM_V;
221}
222
223static u32 omap2_get_pte_attr(struct iotlb_entry *e)
224{
225 u32 attr;
226
227 attr = e->mixed << 5;
228 attr |= e->endian;
229 attr |= e->elsz >> 3;
230 attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
231 (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
232 return attr;
233}
234
235static ssize_t
236omap2_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, char *buf)
237{
238 char *p = buf;
239
240 /* FIXME: Need more detail analysis of cam/ram */
241 p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
242 (cr->cam & MMU_CAM_P) ? 1 : 0);
243
244 return p - buf;
245}
246
247#define pr_reg(name) \
248 do { \
249 ssize_t bytes; \
250 const char *str = "%20s: %08x\n"; \
251 const int maxcol = 32; \
252 bytes = snprintf(p, maxcol, str, __stringify(name), \
253 iommu_read_reg(obj, MMU_##name)); \
254 p += bytes; \
255 len -= bytes; \
256 if (len < maxcol) \
257 goto out; \
258 } while (0)
259
260static ssize_t
261omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len)
262{
263 char *p = buf;
264
265 pr_reg(REVISION);
266 pr_reg(SYSCONFIG);
267 pr_reg(SYSSTATUS);
268 pr_reg(IRQSTATUS);
269 pr_reg(IRQENABLE);
270 pr_reg(WALKING_ST);
271 pr_reg(CNTL);
272 pr_reg(FAULT_AD);
273 pr_reg(TTB);
274 pr_reg(LOCK);
275 pr_reg(LD_TLB);
276 pr_reg(CAM);
277 pr_reg(RAM);
278 pr_reg(GFLUSH);
279 pr_reg(FLUSH_ENTRY);
280 pr_reg(READ_CAM);
281 pr_reg(READ_RAM);
282 pr_reg(EMU_FAULT_AD);
283out:
284 return p - buf;
285}
286
287static void omap2_iommu_save_ctx(struct omap_iommu *obj)
288{
289 int i;
290 u32 *p = obj->ctx;
291
292 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
293 p[i] = iommu_read_reg(obj, i * sizeof(u32));
294 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
295 }
296
297 BUG_ON(p[0] != IOMMU_ARCH_VERSION);
298}
299
300static void omap2_iommu_restore_ctx(struct omap_iommu *obj)
301{
302 int i;
303 u32 *p = obj->ctx;
304
305 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
306 iommu_write_reg(obj, p[i], i * sizeof(u32));
307 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
308 }
309
310 BUG_ON(p[0] != IOMMU_ARCH_VERSION);
311}
312
313static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
314{
315 e->da = cr->cam & MMU_CAM_VATAG_MASK;
316 e->pa = cr->ram & MMU_RAM_PADDR_MASK;
317 e->valid = cr->cam & MMU_CAM_V;
318 e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK;
319 e->endian = cr->ram & MMU_RAM_ENDIAN_MASK;
320 e->elsz = cr->ram & MMU_RAM_ELSZ_MASK;
321 e->mixed = cr->ram & MMU_RAM_MIXED;
322}
323
324static const struct iommu_functions omap2_iommu_ops = {
325 .version = IOMMU_ARCH_VERSION,
326
327 .enable = omap2_iommu_enable,
328 .disable = omap2_iommu_disable,
329 .set_twl = omap2_iommu_set_twl,
330 .fault_isr = omap2_iommu_fault_isr,
331
332 .tlb_read_cr = omap2_tlb_read_cr,
333 .tlb_load_cr = omap2_tlb_load_cr,
334
335 .cr_to_e = omap2_cr_to_e,
336 .cr_to_virt = omap2_cr_to_virt,
337 .alloc_cr = omap2_alloc_cr,
338 .cr_valid = omap2_cr_valid,
339 .dump_cr = omap2_dump_cr,
340
341 .get_pte_attr = omap2_get_pte_attr,
342
343 .save_ctx = omap2_iommu_save_ctx,
344 .restore_ctx = omap2_iommu_restore_ctx,
345 .dump_ctx = omap2_iommu_dump_ctx,
346};
347
348static int __init omap2_iommu_init(void)
349{
350 return omap_install_iommu_arch(&omap2_iommu_ops);
351}
352module_init(omap2_iommu_init);
353
354static void __exit omap2_iommu_exit(void)
355{
356 omap_uninstall_iommu_arch(&omap2_iommu_ops);
357}
358module_exit(omap2_iommu_exit);
359
360MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
361MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
362MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index a4b71b14975a..c677b9f2fefa 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -10,103 +10,21 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12 12
13#ifndef __MACH_IOMMU_H 13#define MMU_REG_SIZE 256
14#define __MACH_IOMMU_H
15
16#include <linux/io.h>
17
18#if defined(CONFIG_ARCH_OMAP1)
19#error "iommu for this processor not implemented yet"
20#endif
21
22struct iotlb_entry {
23 u32 da;
24 u32 pa;
25 u32 pgsz, prsvd, valid;
26 union {
27 u16 ap;
28 struct {
29 u32 endian, elsz, mixed;
30 };
31 };
32};
33
34struct omap_iommu {
35 const char *name;
36 struct module *owner;
37 struct clk *clk;
38 void __iomem *regbase;
39 struct device *dev;
40 void *isr_priv;
41 struct iommu_domain *domain;
42
43 unsigned int refcount;
44 spinlock_t iommu_lock; /* global for this whole object */
45
46 /*
47 * We don't change iopgd for a situation like pgd for a task,
48 * but share it globally for each iommu.
49 */
50 u32 *iopgd;
51 spinlock_t page_table_lock; /* protect iopgd */
52
53 int nr_tlb_entries;
54
55 struct list_head mmap;
56 struct mutex mmap_lock; /* protect mmap */
57
58 void *ctx; /* iommu context: registres saved area */
59 u32 da_start;
60 u32 da_end;
61};
62
63struct cr_regs {
64 union {
65 struct {
66 u16 cam_l;
67 u16 cam_h;
68 };
69 u32 cam;
70 };
71 union {
72 struct {
73 u16 ram_l;
74 u16 ram_h;
75 };
76 u32 ram;
77 };
78};
79
80struct iotlb_lock {
81 short base;
82 short vict;
83};
84
85/* architecture specific functions */
86struct iommu_functions {
87 unsigned long version;
88
89 int (*enable)(struct omap_iommu *obj);
90 void (*disable)(struct omap_iommu *obj);
91 void (*set_twl)(struct omap_iommu *obj, bool on);
92 u32 (*fault_isr)(struct omap_iommu *obj, u32 *ra);
93
94 void (*tlb_read_cr)(struct omap_iommu *obj, struct cr_regs *cr);
95 void (*tlb_load_cr)(struct omap_iommu *obj, struct cr_regs *cr);
96
97 struct cr_regs *(*alloc_cr)(struct omap_iommu *obj,
98 struct iotlb_entry *e);
99 int (*cr_valid)(struct cr_regs *cr);
100 u32 (*cr_to_virt)(struct cr_regs *cr);
101 void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
102 ssize_t (*dump_cr)(struct omap_iommu *obj, struct cr_regs *cr,
103 char *buf);
104
105 u32 (*get_pte_attr)(struct iotlb_entry *e);
106 14
107 void (*save_ctx)(struct omap_iommu *obj); 15/**
108 void (*restore_ctx)(struct omap_iommu *obj); 16 * struct iommu_arch_data - omap iommu private data
109 ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len); 17 * @name: name of the iommu device
18 * @iommu_dev: handle of the iommu device
19 *
20 * This is an omap iommu private data object, which binds an iommu user
21 * to its iommu device. This object should be placed at the iommu user's
22 * dev_archdata so generic IOMMU API can be used without having to
23 * utilize omap-specific plumbing anymore.
24 */
25struct omap_iommu_arch_data {
26 const char *name;
27 struct omap_iommu *iommu_dev;
110}; 28};
111 29
112/** 30/**
@@ -129,165 +47,3 @@ struct iommu_platform_data {
129 u32 da_start; 47 u32 da_start;
130 u32 da_end; 48 u32 da_end;
131}; 49};
132
133/**
134 * struct iommu_arch_data - omap iommu private data
135 * @name: name of the iommu device
136 * @iommu_dev: handle of the iommu device
137 *
138 * This is an omap iommu private data object, which binds an iommu user
139 * to its iommu device. This object should be placed at the iommu user's
140 * dev_archdata so generic IOMMU API can be used without having to
141 * utilize omap-specific plumbing anymore.
142 */
143struct omap_iommu_arch_data {
144 const char *name;
145 struct omap_iommu *iommu_dev;
146};
147
148#ifdef CONFIG_IOMMU_API
149/**
150 * dev_to_omap_iommu() - retrieves an omap iommu object from a user device
151 * @dev: iommu client device
152 */
153static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
154{
155 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
156
157 return arch_data->iommu_dev;
158}
159#endif
160
161/* IOMMU errors */
162#define OMAP_IOMMU_ERR_TLB_MISS (1 << 0)
163#define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1)
164#define OMAP_IOMMU_ERR_EMU_MISS (1 << 2)
165#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 << 3)
166#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 << 4)
167
168/*
169 * MMU Register offsets
170 */
171#define MMU_REVISION 0x00
172#define MMU_SYSCONFIG 0x10
173#define MMU_SYSSTATUS 0x14
174#define MMU_IRQSTATUS 0x18
175#define MMU_IRQENABLE 0x1c
176#define MMU_WALKING_ST 0x40
177#define MMU_CNTL 0x44
178#define MMU_FAULT_AD 0x48
179#define MMU_TTB 0x4c
180#define MMU_LOCK 0x50
181#define MMU_LD_TLB 0x54
182#define MMU_CAM 0x58
183#define MMU_RAM 0x5c
184#define MMU_GFLUSH 0x60
185#define MMU_FLUSH_ENTRY 0x64
186#define MMU_READ_CAM 0x68
187#define MMU_READ_RAM 0x6c
188#define MMU_EMU_FAULT_AD 0x70
189
190#define MMU_REG_SIZE 256
191
192/*
193 * MMU Register bit definitions
194 */
195#define MMU_LOCK_BASE_SHIFT 10
196#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
197#define MMU_LOCK_BASE(x) \
198 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
199
200#define MMU_LOCK_VICT_SHIFT 4
201#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
202#define MMU_LOCK_VICT(x) \
203 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
204
205#define MMU_CAM_VATAG_SHIFT 12
206#define MMU_CAM_VATAG_MASK \
207 ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
208#define MMU_CAM_P (1 << 3)
209#define MMU_CAM_V (1 << 2)
210#define MMU_CAM_PGSZ_MASK 3
211#define MMU_CAM_PGSZ_1M (0 << 0)
212#define MMU_CAM_PGSZ_64K (1 << 0)
213#define MMU_CAM_PGSZ_4K (2 << 0)
214#define MMU_CAM_PGSZ_16M (3 << 0)
215
216#define MMU_RAM_PADDR_SHIFT 12
217#define MMU_RAM_PADDR_MASK \
218 ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
219
220#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
221#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
222
223#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
224#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
225#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
226#define MMU_RAM_MIXED_SHIFT 6
227#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
228#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
229
230/*
231 * utilities for super page(16MB, 1MB, 64KB and 4KB)
232 */
233
234#define iopgsz_max(bytes) \
235 (((bytes) >= SZ_16M) ? SZ_16M : \
236 ((bytes) >= SZ_1M) ? SZ_1M : \
237 ((bytes) >= SZ_64K) ? SZ_64K : \
238 ((bytes) >= SZ_4K) ? SZ_4K : 0)
239
240#define bytes_to_iopgsz(bytes) \
241 (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
242 ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
243 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
244 ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
245
246#define iopgsz_to_bytes(iopgsz) \
247 (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
248 ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
249 ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
250 ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
251
252#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
253
254/*
255 * global functions
256 */
257extern u32 omap_iommu_arch_version(void);
258
259extern void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
260
261extern int
262omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e);
263
264extern int omap_iommu_set_isr(const char *name,
265 int (*isr)(struct omap_iommu *obj, u32 da, u32 iommu_errs,
266 void *priv),
267 void *isr_priv);
268
269extern int omap_install_iommu_arch(const struct iommu_functions *ops);
270extern void omap_uninstall_iommu_arch(const struct iommu_functions *ops);
271
272extern int omap_foreach_iommu_device(void *data,
273 int (*fn)(struct device *, void *));
274
275extern ssize_t
276omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len);
277extern size_t
278omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len);
279
280/*
281 * register accessors
282 */
283static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
284{
285 return __raw_readl(obj->regbase + offs);
286}
287
288static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
289{
290 __raw_writel(val, obj->regbase + offs);
291}
292
293#endif /* __MACH_IOMMU_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 07:16:52 -0500