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-rw-r--r--arch/arm/Kconfig48
-rw-r--r--arch/arm/Kconfig.debug19
-rw-r--r--arch/arm/Makefile5
-rw-r--r--arch/arm/boot/compressed/Makefile2
-rw-r--r--arch/arm/boot/dts/Makefile7
-rw-r--r--arch/arm/boot/dts/armv7-m.dtsi18
-rw-r--r--arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts29
-rw-r--r--arch/arm/boot/dts/berlin2.dtsi227
-rw-r--r--arch/arm/boot/dts/berlin2cd-google-chromecast.dts29
-rw-r--r--arch/arm/boot/dts/berlin2cd.dtsi210
-rw-r--r--arch/arm/boot/dts/efm32gg-dk3750.dts86
-rw-r--r--arch/arm/boot/dts/efm32gg.dtsi172
-rw-r--r--arch/arm/boot/dts/hi3620-hi4511.dts649
-rw-r--r--arch/arm/boot/dts/hi3620.dtsi565
-rw-r--r--arch/arm/boot/dts/qcom-msm8974.dtsi33
-rw-r--r--arch/arm/common/timer-sp.c4
-rw-r--r--arch/arm/configs/ape6evm_defconfig2
-rw-r--r--arch/arm/configs/armadillo800eva_defconfig2
-rw-r--r--arch/arm/configs/bcm_defconfig3
-rw-r--r--arch/arm/configs/bockw_defconfig2
-rw-r--r--arch/arm/configs/efm32_defconfig102
-rw-r--r--arch/arm/configs/hi3xxx_defconfig56
-rw-r--r--arch/arm/configs/imx_v4_v5_defconfig2
-rw-r--r--arch/arm/configs/imx_v6_v7_defconfig13
-rw-r--r--arch/arm/configs/keystone_defconfig20
-rw-r--r--arch/arm/configs/koelsch_defconfig2
-rw-r--r--arch/arm/configs/kzm9d_defconfig2
-rw-r--r--arch/arm/configs/kzm9g_defconfig2
-rw-r--r--arch/arm/configs/lager_defconfig2
-rw-r--r--arch/arm/configs/mackerel_defconfig2
-rw-r--r--arch/arm/configs/marzen_defconfig2
-rw-r--r--arch/arm/configs/moxart_defconfig149
-rw-r--r--arch/arm/configs/msm_defconfig11
-rw-r--r--arch/arm/configs/multi_v7_defconfig4
-rw-r--r--arch/arm/configs/u8500_defconfig1
-rw-r--r--arch/arm/configs/versatile_defconfig26
-rw-r--r--arch/arm/include/debug/imx-uart.h10
-rw-r--r--arch/arm/include/debug/tegra.S34
-rw-r--r--arch/arm/mach-at91/Kconfig2
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h3
-rw-r--r--arch/arm/mach-at91/setup.c4
-rw-r--r--arch/arm/mach-berlin/Kconfig29
-rw-r--r--arch/arm/mach-berlin/Makefile1
-rw-r--r--arch/arm/mach-berlin/berlin.c39
-rw-r--r--arch/arm/mach-clps711x/common.c4
-rw-r--r--arch/arm/mach-davinci/clock.c2
-rw-r--r--arch/arm/mach-davinci/time.c4
-rw-r--r--arch/arm/mach-efm32/Makefile1
-rw-r--r--arch/arm/mach-efm32/Makefile.boot3
-rw-r--r--arch/arm/mach-efm32/dtmachine.c15
-rw-r--r--arch/arm/mach-efm32/include/mach/entry-macro.S4
-rw-r--r--arch/arm/mach-efm32/include/mach/timex.h3
-rw-r--r--arch/arm/mach-ep93xx/Kconfig1
-rw-r--r--arch/arm/mach-ep93xx/core.c110
-rw-r--r--arch/arm/mach-ep93xx/include/mach/platform.h3
-rw-r--r--arch/arm/mach-hisi/Kconfig17
-rw-r--r--arch/arm/mach-hisi/Makefile7
-rw-r--r--arch/arm/mach-hisi/core.h15
-rw-r--r--arch/arm/mach-hisi/hisilicon.c90
-rw-r--r--arch/arm/mach-hisi/hotplug.c200
-rw-r--r--arch/arm/mach-hisi/platsmp.c89
-rw-r--r--arch/arm/mach-imx/Kconfig35
-rw-r--r--arch/arm/mach-imx/Makefile2
-rw-r--r--arch/arm/mach-imx/avic.c25
-rw-r--r--arch/arm/mach-imx/clk-gate2.c2
-rw-r--r--arch/arm/mach-imx/clk-imx35.c14
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c804
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c5
-rw-r--r--arch/arm/mach-imx/clk-imx6sl.c11
-rw-r--r--arch/arm/mach-imx/clk-pfd.c11
-rw-r--r--arch/arm/mach-imx/clk-pllv1.c23
-rw-r--r--arch/arm/mach-imx/clk-vf610.c5
-rw-r--r--arch/arm/mach-imx/common.h1
-rw-r--r--arch/arm/mach-imx/imx31-dt.c2
-rw-r--r--arch/arm/mach-imx/imx35-dt.c50
-rw-r--r--arch/arm/mach-imx/imx51-dt.c2
-rw-r--r--arch/arm/mach-imx/irq-common.h1
-rw-r--r--arch/arm/mach-imx/mach-imx50.c38
-rw-r--r--arch/arm/mach-imx/mach-imx53.c2
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c32
-rw-r--r--arch/arm/mach-imx/mach-imx6sl.c10
-rw-r--r--arch/arm/mach-imx/mach-vf610.c2
-rw-r--r--arch/arm/mach-imx/mm-imx5.c8
-rw-r--r--arch/arm/mach-imx/pm-imx6q.c16
-rw-r--r--arch/arm/mach-imx/time.c4
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c4
-rw-r--r--arch/arm/mach-ixp4xx/common.c4
-rw-r--r--arch/arm/mach-keystone/Kconfig2
-rw-r--r--arch/arm/mach-keystone/keystone.c4
-rw-r--r--arch/arm/mach-keystone/keystone.h1
-rw-r--r--arch/arm/mach-keystone/pm_domain.c2
-rw-r--r--arch/arm/mach-mmp/time.c4
-rw-r--r--arch/arm/mach-moxart/Kconfig31
-rw-r--r--arch/arm/mach-moxart/Makefile3
-rw-r--r--arch/arm/mach-moxart/moxart.c15
-rw-r--r--arch/arm/mach-msm/Kconfig74
-rw-r--r--arch/arm/mach-msm/Makefile4
-rw-r--r--arch/arm/mach-msm/timer.c4
-rw-r--r--arch/arm/mach-omap1/time.c4
-rw-r--r--arch/arm/mach-omap2/timer.c4
-rw-r--r--arch/arm/mach-pxa/time.c4
-rw-r--r--arch/arm/mach-sa1100/time.c4
-rw-r--r--arch/arm/mach-shmobile/Kconfig24
-rw-r--r--arch/arm/mach-shmobile/Makefile1
-rw-r--r--arch/arm/mach-shmobile/Makefile.boot1
-rw-r--r--arch/arm/mach-shmobile/board-bockw.c1
-rw-r--r--arch/arm/mach-shmobile/board-kzm9d.c92
-rw-r--r--arch/arm/mach-shmobile/clock-r7s72100.c8
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c1
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7778.c31
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c11
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c62
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7791.c17
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c1
-rw-r--r--arch/arm/mach-shmobile/include/mach/emev2.h5
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7778.h39
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7791.h1
-rw-r--r--arch/arm/mach-shmobile/setup-emev2.c163
-rw-r--r--arch/arm/mach-shmobile/setup-r7s72100.c82
-rw-r--r--arch/arm/mach-shmobile/setup-r8a73a4.c68
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c195
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7778.c166
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c128
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7790.c141
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7791.c188
-rw-r--r--arch/arm/mach-shmobile/setup-rcar-gen2.c29
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c160
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c191
-rw-r--r--arch/arm/mach-sunxi/Kconfig3
-rw-r--r--arch/arm/mach-sunxi/Makefile1
-rw-r--r--arch/arm/mach-sunxi/common.h19
-rw-r--r--arch/arm/mach-sunxi/headsmp.S9
-rw-r--r--arch/arm/mach-sunxi/platsmp.c124
-rw-r--r--arch/arm/mach-sunxi/sunxi.c14
-rw-r--r--arch/arm/mach-tegra/Kconfig1
-rw-r--r--arch/arm/mach-tegra/fuse.c41
-rw-r--r--arch/arm/mach-tegra/iomap.h14
-rw-r--r--arch/arm/mach-tegra/powergate.c195
-rw-r--r--arch/arm/mach-tegra/tegra.c4
-rw-r--r--arch/arm/mach-u300/timer.c4
-rw-r--r--arch/arm/mach-ux500/pm.c27
-rw-r--r--arch/arm/mach-versatile/core.c16
-rw-r--r--arch/arm/mach-versatile/versatile_pb.c21
-rw-r--r--arch/arm/plat-iop/time.c4
-rw-r--r--arch/arm/plat-omap/counter_32k.c4
-rw-r--r--arch/arm/plat-orion/time.c4
-rw-r--r--arch/arm/plat-samsung/s5p-irq-eint.c4
-rw-r--r--arch/arm/plat-versatile/sched-clock.c4
148 files changed, 5102 insertions, 1688 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dbe173dfa4ae..ca64b4240271 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -414,6 +414,26 @@ config ARCH_EBSA110
414 Ethernet interface, two PCMCIA sockets, two serial ports and a 414 Ethernet interface, two PCMCIA sockets, two serial ports and a
415 parallel port. 415 parallel port.
416 416
417config ARCH_EFM32
418 bool "Energy Micro efm32"
419 depends on !MMU
420 select ARCH_REQUIRE_GPIOLIB
421 select ARM_NVIC
422 # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged,
423 # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO
424 select CLKSRC_MMIO
425 select CLKSRC_OF
426 select COMMON_CLK
427 select CPU_V7M
428 select GENERIC_CLOCKEVENTS
429 select NO_DMA
430 select NO_IOPORT
431 select SPARSE_IRQ
432 select USE_OF
433 help
434 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
435 processors.
436
417config ARCH_EP93XX 437config ARCH_EP93XX
418 bool "EP93xx-based" 438 bool "EP93xx-based"
419 select ARCH_HAS_HOLES_MEMORYMODEL 439 select ARCH_HAS_HOLES_MEMORYMODEL
@@ -635,10 +655,10 @@ config ARCH_PXA
635 help 655 help
636 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 656 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
637 657
638config ARCH_MSM 658config ARCH_MSM_NODT
639 bool "Qualcomm MSM" 659 bool "Qualcomm MSM"
660 select ARCH_MSM
640 select ARCH_REQUIRE_GPIOLIB 661 select ARCH_REQUIRE_GPIOLIB
641 select CLKSRC_OF if OF
642 select COMMON_CLK 662 select COMMON_CLK
643 select GENERIC_CLOCKEVENTS 663 select GENERIC_CLOCKEVENTS
644 help 664 help
@@ -648,8 +668,9 @@ config ARCH_MSM
648 stack and controls some vital subsystems 668 stack and controls some vital subsystems
649 (clock and power control, etc). 669 (clock and power control, etc).
650 670
651config ARCH_SHMOBILE 671config ARCH_SHMOBILE_LEGACY
652 bool "Renesas SH-Mobile / R-Mobile" 672 bool "Renesas SH-Mobile / R-Mobile (non-multiplatform)"
673 select ARCH_SHMOBILE
653 select ARM_PATCH_PHYS_VIRT 674 select ARM_PATCH_PHYS_VIRT
654 select CLKDEV_LOOKUP 675 select CLKDEV_LOOKUP
655 select GENERIC_CLOCKEVENTS 676 select GENERIC_CLOCKEVENTS
@@ -664,7 +685,8 @@ config ARCH_SHMOBILE
664 select PM_GENERIC_DOMAINS if PM 685 select PM_GENERIC_DOMAINS if PM
665 select SPARSE_IRQ 686 select SPARSE_IRQ
666 help 687 help
667 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 688 Support for Renesas's SH-Mobile and R-Mobile ARM platforms using
689 a non-multiplatform kernel.
668 690
669config ARCH_RPC 691config ARCH_RPC
670 bool "RiscPC" 692 bool "RiscPC"
@@ -731,7 +753,7 @@ config ARCH_S3C64XX
731 select CLKDEV_LOOKUP 753 select CLKDEV_LOOKUP
732 select CLKSRC_SAMSUNG_PWM 754 select CLKSRC_SAMSUNG_PWM
733 select COMMON_CLK 755 select COMMON_CLK
734 select CPU_V6 756 select CPU_V6K
735 select GENERIC_CLOCKEVENTS 757 select GENERIC_CLOCKEVENTS
736 select GPIO_SAMSUNG 758 select GPIO_SAMSUNG
737 select HAVE_S3C2410_I2C if I2C 759 select HAVE_S3C2410_I2C if I2C
@@ -913,6 +935,8 @@ source "arch/arm/mach-bcm/Kconfig"
913 935
914source "arch/arm/mach-bcm2835/Kconfig" 936source "arch/arm/mach-bcm2835/Kconfig"
915 937
938source "arch/arm/mach-berlin/Kconfig"
939
916source "arch/arm/mach-clps711x/Kconfig" 940source "arch/arm/mach-clps711x/Kconfig"
917 941
918source "arch/arm/mach-cns3xxx/Kconfig" 942source "arch/arm/mach-cns3xxx/Kconfig"
@@ -929,6 +953,8 @@ source "arch/arm/mach-gemini/Kconfig"
929 953
930source "arch/arm/mach-highbank/Kconfig" 954source "arch/arm/mach-highbank/Kconfig"
931 955
956source "arch/arm/mach-hisi/Kconfig"
957
932source "arch/arm/mach-integrator/Kconfig" 958source "arch/arm/mach-integrator/Kconfig"
933 959
934source "arch/arm/mach-iop32x/Kconfig" 960source "arch/arm/mach-iop32x/Kconfig"
@@ -947,6 +973,8 @@ source "arch/arm/mach-ks8695/Kconfig"
947 973
948source "arch/arm/mach-msm/Kconfig" 974source "arch/arm/mach-msm/Kconfig"
949 975
976source "arch/arm/mach-moxart/Kconfig"
977
950source "arch/arm/mach-mv78xx0/Kconfig" 978source "arch/arm/mach-mv78xx0/Kconfig"
951 979
952source "arch/arm/mach-imx/Kconfig" 980source "arch/arm/mach-imx/Kconfig"
@@ -1613,7 +1641,7 @@ config HZ_FIXED
1613 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ 1641 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1614 ARCH_S5PV210 || ARCH_EXYNOS4 1642 ARCH_S5PV210 || ARCH_EXYNOS4
1615 default AT91_TIMER_HZ if ARCH_AT91 1643 default AT91_TIMER_HZ if ARCH_AT91
1616 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1644 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1617 default 0 1645 default 0
1618 1646
1619choice 1647choice
@@ -1795,10 +1823,10 @@ config ARCH_WANT_GENERAL_HUGETLB
1795source "mm/Kconfig" 1823source "mm/Kconfig"
1796 1824
1797config FORCE_MAX_ZONEORDER 1825config FORCE_MAX_ZONEORDER
1798 int "Maximum zone order" if ARCH_SHMOBILE 1826 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1799 range 11 64 if ARCH_SHMOBILE 1827 range 11 64 if ARCH_SHMOBILE_LEGACY
1800 default "12" if SOC_AM33XX 1828 default "12" if SOC_AM33XX
1801 default "9" if SA1111 1829 default "9" if SA1111 || ARCH_EFM32
1802 default "11" 1830 default "11"
1803 help 1831 help
1804 The kernel memory allocator divides physically contiguous memory 1832 The kernel memory allocator divides physically contiguous memory
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 9afabbb5e798..0531da8e5216 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -117,6 +117,14 @@ choice
117 mobile SoCs in the Kona family of chips (e.g. bcm28155, 117 mobile SoCs in the Kona family of chips (e.g. bcm28155,
118 bcm11351, etc...) 118 bcm11351, etc...)
119 119
120 config DEBUG_BERLIN_UART
121 bool "Marvell Berlin SoC Debug UART"
122 depends on ARCH_BERLIN
123 select DEBUG_UART_8250
124 help
125 Say Y here if you want kernel low-level debugging support
126 on Marvell Berlin SoC based platforms.
127
120 config DEBUG_CLPS711X_UART1 128 config DEBUG_CLPS711X_UART1
121 bool "Kernel low-level debugging messages via UART1" 129 bool "Kernel low-level debugging messages via UART1"
122 depends on ARCH_CLPS711X 130 depends on ARCH_CLPS711X
@@ -278,6 +286,13 @@ choice
278 Say Y here if you want kernel low-level debugging support 286 Say Y here if you want kernel low-level debugging support
279 on i.MX35. 287 on i.MX35.
280 288
289 config DEBUG_IMX50_UART
290 bool "i.MX50 Debug UART"
291 depends on SOC_IMX50
292 help
293 Say Y here if you want kernel low-level debugging support
294 on i.MX50.
295
281 config DEBUG_IMX51_UART 296 config DEBUG_IMX51_UART
282 bool "i.MX51 Debug UART" 297 bool "i.MX51 Debug UART"
283 depends on SOC_IMX51 298 depends on SOC_IMX51
@@ -920,6 +935,7 @@ config DEBUG_IMX_UART_PORT
920 DEBUG_IMX21_IMX27_UART || \ 935 DEBUG_IMX21_IMX27_UART || \
921 DEBUG_IMX31_UART || \ 936 DEBUG_IMX31_UART || \
922 DEBUG_IMX35_UART || \ 937 DEBUG_IMX35_UART || \
938 DEBUG_IMX50_UART || \
923 DEBUG_IMX51_UART || \ 939 DEBUG_IMX51_UART || \
924 DEBUG_IMX53_UART || \ 940 DEBUG_IMX53_UART || \
925 DEBUG_IMX6Q_UART || \ 941 DEBUG_IMX6Q_UART || \
@@ -954,6 +970,7 @@ config DEBUG_LL_INCLUDE
954 DEBUG_IMX21_IMX27_UART || \ 970 DEBUG_IMX21_IMX27_UART || \
955 DEBUG_IMX31_UART || \ 971 DEBUG_IMX31_UART || \
956 DEBUG_IMX35_UART || \ 972 DEBUG_IMX35_UART || \
973 DEBUG_IMX50_UART || \
957 DEBUG_IMX51_UART || \ 974 DEBUG_IMX51_UART || \
958 DEBUG_IMX53_UART ||\ 975 DEBUG_IMX53_UART ||\
959 DEBUG_IMX6Q_UART || \ 976 DEBUG_IMX6Q_UART || \
@@ -1035,6 +1052,7 @@ config DEBUG_UART_PHYS
1035 default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE 1052 default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE
1036 default 0xf1012000 if ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \ 1053 default 0xf1012000 if ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \
1037 ARCH_ORION5X 1054 ARCH_ORION5X
1055 default 0xf7fc9000 if DEBUG_BERLIN_UART
1038 default 0xf8b00000 if DEBUG_HI3716_UART 1056 default 0xf8b00000 if DEBUG_HI3716_UART
1039 default 0xfcb00000 if DEBUG_HI3620_UART 1057 default 0xfcb00000 if DEBUG_HI3620_UART
1040 default 0xfe800000 if ARCH_IOP32X 1058 default 0xfe800000 if ARCH_IOP32X
@@ -1060,6 +1078,7 @@ config DEBUG_UART_VIRT
1060 default 0xf2100000 if DEBUG_PXA_UART1 1078 default 0xf2100000 if DEBUG_PXA_UART1
1061 default 0xf4090000 if ARCH_LPC32XX 1079 default 0xf4090000 if ARCH_LPC32XX
1062 default 0xf4200000 if ARCH_GEMINI 1080 default 0xf4200000 if ARCH_GEMINI
1081 default 0xf7fc9000 if DEBUG_BERLIN_UART
1063 default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9 1082 default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9
1064 default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1 1083 default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1
1065 default 0xfb009000 if DEBUG_REALVIEW_STD_PORT 1084 default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 55b4255ad6ed..d8605046792c 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -144,15 +144,18 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
144machine-$(CONFIG_ARCH_AT91) += at91 144machine-$(CONFIG_ARCH_AT91) += at91
145machine-$(CONFIG_ARCH_BCM) += bcm 145machine-$(CONFIG_ARCH_BCM) += bcm
146machine-$(CONFIG_ARCH_BCM2835) += bcm2835 146machine-$(CONFIG_ARCH_BCM2835) += bcm2835
147machine-$(CONFIG_ARCH_BERLIN) += berlin
147machine-$(CONFIG_ARCH_CLPS711X) += clps711x 148machine-$(CONFIG_ARCH_CLPS711X) += clps711x
148machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx 149machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
149machine-$(CONFIG_ARCH_DAVINCI) += davinci 150machine-$(CONFIG_ARCH_DAVINCI) += davinci
150machine-$(CONFIG_ARCH_DOVE) += dove 151machine-$(CONFIG_ARCH_DOVE) += dove
151machine-$(CONFIG_ARCH_EBSA110) += ebsa110 152machine-$(CONFIG_ARCH_EBSA110) += ebsa110
153machine-$(CONFIG_ARCH_EFM32) += efm32
152machine-$(CONFIG_ARCH_EP93XX) += ep93xx 154machine-$(CONFIG_ARCH_EP93XX) += ep93xx
153machine-$(CONFIG_ARCH_EXYNOS) += exynos 155machine-$(CONFIG_ARCH_EXYNOS) += exynos
154machine-$(CONFIG_ARCH_GEMINI) += gemini 156machine-$(CONFIG_ARCH_GEMINI) += gemini
155machine-$(CONFIG_ARCH_HIGHBANK) += highbank 157machine-$(CONFIG_ARCH_HIGHBANK) += highbank
158machine-$(CONFIG_ARCH_HI3xxx) += hisi
156machine-$(CONFIG_ARCH_INTEGRATOR) += integrator 159machine-$(CONFIG_ARCH_INTEGRATOR) += integrator
157machine-$(CONFIG_ARCH_IOP13XX) += iop13xx 160machine-$(CONFIG_ARCH_IOP13XX) += iop13xx
158machine-$(CONFIG_ARCH_IOP32X) += iop32x 161machine-$(CONFIG_ARCH_IOP32X) += iop32x
@@ -163,6 +166,7 @@ machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood
163machine-$(CONFIG_ARCH_KS8695) += ks8695 166machine-$(CONFIG_ARCH_KS8695) += ks8695
164machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx 167machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
165machine-$(CONFIG_ARCH_MMP) += mmp 168machine-$(CONFIG_ARCH_MMP) += mmp
169machine-$(CONFIG_ARCH_MOXART) += moxart
166machine-$(CONFIG_ARCH_MSM) += msm 170machine-$(CONFIG_ARCH_MSM) += msm
167machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 171machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
168machine-$(CONFIG_ARCH_MVEBU) += mvebu 172machine-$(CONFIG_ARCH_MVEBU) += mvebu
@@ -186,7 +190,6 @@ machine-$(CONFIG_ARCH_S5PC100) += s5pc100
186machine-$(CONFIG_ARCH_S5PV210) += s5pv210 190machine-$(CONFIG_ARCH_S5PV210) += s5pv210
187machine-$(CONFIG_ARCH_SA1100) += sa1100 191machine-$(CONFIG_ARCH_SA1100) += sa1100
188machine-$(CONFIG_ARCH_SHMOBILE) += shmobile 192machine-$(CONFIG_ARCH_SHMOBILE) += shmobile
189machine-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile
190machine-$(CONFIG_ARCH_SIRF) += prima2 193machine-$(CONFIG_ARCH_SIRF) += prima2
191machine-$(CONFIG_ARCH_SOCFPGA) += socfpga 194machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
192machine-$(CONFIG_ARCH_STI) += sti 195machine-$(CONFIG_ARCH_STI) += sti
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 4bb86d9a749d..68c918362b79 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -64,7 +64,7 @@ else
64endif 64endif
65endif 65endif
66 66
67ifeq ($(CONFIG_ARCH_SHMOBILE),y) 67ifeq ($(CONFIG_ARCH_SHMOBILE_LEGACY),y)
68OBJS += head-shmobile.o 68OBJS += head-shmobile.o
69endif 69endif
70 70
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 36e0d06d3efa..91896a3f703a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -46,6 +46,9 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
46dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \ 46dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
47 bcm28155-ap.dtb 47 bcm28155-ap.dtb
48dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 48dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
49dtb-$(CONFIG_ARCH_BERLIN) += \
50 berlin2-sony-nsz-gs7.dtb \
51 berlin2cd-google-chromecast.dtb
49dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ 52dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
50 da850-evm.dtb 53 da850-evm.dtb
51dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ 54dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
@@ -53,6 +56,7 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
53 dove-d2plug.dtb \ 56 dove-d2plug.dtb \
54 dove-d3plug.dtb \ 57 dove-d3plug.dtb \
55 dove-dove-db.dtb 58 dove-dove-db.dtb
59dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
56dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ 60dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
57 exynos4210-smdkv310.dtb \ 61 exynos4210-smdkv310.dtb \
58 exynos4210-trats.dtb \ 62 exynos4210-trats.dtb \
@@ -67,6 +71,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
67 exynos5420-smdk5420.dtb \ 71 exynos5420-smdk5420.dtb \
68 exynos5440-sd5v1.dtb \ 72 exynos5440-sd5v1.dtb \
69 exynos5440-ssdk5440.dtb 73 exynos5440-ssdk5440.dtb
74dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
70dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ 75dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
71 ecx-2000.dtb 76 ecx-2000.dtb
72dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ 77dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
@@ -217,7 +222,7 @@ dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
217dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb 222dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
218dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ 223dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
219 s3c6410-smdk6410.dtb 224 s3c6410-smdk6410.dtb
220dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ 225dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \
221 r7s72100-genmai.dtb \ 226 r7s72100-genmai.dtb \
222 r8a7740-armadillo800eva.dtb \ 227 r8a7740-armadillo800eva.dtb \
223 r8a7778-bockw.dtb \ 228 r8a7778-bockw.dtb \
diff --git a/arch/arm/boot/dts/armv7-m.dtsi b/arch/arm/boot/dts/armv7-m.dtsi
new file mode 100644
index 000000000000..5a660d0faf42
--- /dev/null
+++ b/arch/arm/boot/dts/armv7-m.dtsi
@@ -0,0 +1,18 @@
1#include "skeleton.dtsi"
2
3/ {
4 nvic: nv-interrupt-controller {
5 compatible = "arm,armv7m-nvic";
6 interrupt-controller;
7 #interrupt-cells = <1>;
8 reg = <0xe000e100 0xc00>;
9 };
10
11 soc {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "simple-bus";
15 interrupt-parent = <&nvic>;
16 ranges;
17 };
18};
diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
new file mode 100644
index 000000000000..c72bfd468d10
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
@@ -0,0 +1,29 @@
1/*
2 * Device Tree file for Sony NSZ-GS7
3 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12
13#include "berlin2.dtsi"
14
15/ {
16 model = "Sony NSZ-GS7";
17 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
18
19 chosen {
20 bootargs = "console=ttyS0,115200 earlyprintk";
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0x00000000 0x40000000>; /* 1 GB */
26 };
27};
28
29&uart0 { status = "okay"; };
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
new file mode 100644
index 000000000000..56a1af2f1052
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -0,0 +1,227 @@
1/*
2 * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
3 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * based on GPL'ed 2.6 kernel sources
7 * (c) Marvell International Ltd.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include "skeleton.dtsi"
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16
17/ {
18 model = "Marvell Armada 1500 (BG2) SoC";
19 compatible = "marvell,berlin2", "marvell,berlin";
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu@0 {
26 compatible = "marvell,pj4b";
27 device_type = "cpu";
28 next-level-cache = <&l2>;
29 reg = <0>;
30 };
31
32 cpu@1 {
33 compatible = "marvell,pj4b";
34 device_type = "cpu";
35 next-level-cache = <&l2>;
36 reg = <1>;
37 };
38 };
39
40 clocks {
41 smclk: sysmgr-clock {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <25000000>;
45 };
46
47 cfgclk: cfg-clock {
48 compatible = "fixed-clock";
49 #clock-cells = <0>;
50 clock-frequency = <100000000>;
51 };
52
53 sysclk: system-clock {
54 compatible = "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <400000000>;
57 };
58 };
59
60 soc {
61 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <1>;
64 interrupt-parent = <&gic>;
65
66 ranges = <0 0xf7000000 0x1000000>;
67
68 l2: l2-cache-controller@ac0000 {
69 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
70 reg = <0xac0000 0x1000>;
71 cache-unified;
72 cache-level = <2>;
73 };
74
75 gic: interrupt-controller@ad1000 {
76 compatible = "arm,cortex-a9-gic";
77 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
78 interrupt-controller;
79 #interrupt-cells = <3>;
80 };
81
82 local-timer@ad0600 {
83 compatible = "arm,cortex-a9-twd-timer";
84 reg = <0xad0600 0x20>;
85 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&sysclk>;
87 };
88
89 apb@e80000 {
90 compatible = "simple-bus";
91 #address-cells = <1>;
92 #size-cells = <1>;
93
94 ranges = <0 0xe80000 0x10000>;
95 interrupt-parent = <&aic>;
96
97 timer0: timer@2c00 {
98 compatible = "snps,dw-apb-timer";
99 reg = <0x2c00 0x14>;
100 interrupts = <8>;
101 clocks = <&cfgclk>;
102 clock-names = "timer";
103 status = "okay";
104 };
105
106 timer1: timer@2c14 {
107 compatible = "snps,dw-apb-timer";
108 reg = <0x2c14 0x14>;
109 interrupts = <9>;
110 clocks = <&cfgclk>;
111 clock-names = "timer";
112 status = "okay";
113 };
114
115 timer2: timer@2c28 {
116 compatible = "snps,dw-apb-timer";
117 reg = <0x2c28 0x14>;
118 interrupts = <10>;
119 clocks = <&cfgclk>;
120 clock-names = "timer";
121 status = "disabled";
122 };
123
124 timer3: timer@2c3c {
125 compatible = "snps,dw-apb-timer";
126 reg = <0x2c3c 0x14>;
127 interrupts = <11>;
128 clocks = <&cfgclk>;
129 clock-names = "timer";
130 status = "disabled";
131 };
132
133 timer4: timer@2c50 {
134 compatible = "snps,dw-apb-timer";
135 reg = <0x2c50 0x14>;
136 interrupts = <12>;
137 clocks = <&cfgclk>;
138 clock-names = "timer";
139 status = "disabled";
140 };
141
142 timer5: timer@2c64 {
143 compatible = "snps,dw-apb-timer";
144 reg = <0x2c64 0x14>;
145 interrupts = <13>;
146 clocks = <&cfgclk>;
147 clock-names = "timer";
148 status = "disabled";
149 };
150
151 timer6: timer@2c78 {
152 compatible = "snps,dw-apb-timer";
153 reg = <0x2c78 0x14>;
154 interrupts = <14>;
155 clocks = <&cfgclk>;
156 clock-names = "timer";
157 status = "disabled";
158 };
159
160 timer7: timer@2c8c {
161 compatible = "snps,dw-apb-timer";
162 reg = <0x2c8c 0x14>;
163 interrupts = <15>;
164 clocks = <&cfgclk>;
165 clock-names = "timer";
166 status = "disabled";
167 };
168
169 aic: interrupt-controller@3000 {
170 compatible = "snps,dw-apb-ictl";
171 reg = <0x3000 0xc00>;
172 interrupt-controller;
173 #interrupt-cells = <1>;
174 interrupt-parent = <&gic>;
175 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
176 };
177 };
178
179 apb@fc0000 {
180 compatible = "simple-bus";
181 #address-cells = <1>;
182 #size-cells = <1>;
183
184 ranges = <0 0xfc0000 0x10000>;
185 interrupt-parent = <&sic>;
186
187 uart0: serial@9000 {
188 compatible = "snps,dw-apb-uart";
189 reg = <0x9000 0x100>;
190 reg-shift = <2>;
191 reg-io-width = <1>;
192 interrupts = <8>;
193 clocks = <&smclk>;
194 status = "disabled";
195 };
196
197 uart1: serial@a000 {
198 compatible = "snps,dw-apb-uart";
199 reg = <0xa000 0x100>;
200 reg-shift = <2>;
201 reg-io-width = <1>;
202 interrupts = <9>;
203 clocks = <&smclk>;
204 status = "disabled";
205 };
206
207 uart2: serial@b000 {
208 compatible = "snps,dw-apb-uart";
209 reg = <0xb000 0x100>;
210 reg-shift = <2>;
211 reg-io-width = <1>;
212 interrupts = <10>;
213 clocks = <&smclk>;
214 status = "disabled";
215 };
216
217 sic: interrupt-controller@e000 {
218 compatible = "snps,dw-apb-ictl";
219 reg = <0xe000 0x400>;
220 interrupt-controller;
221 #interrupt-cells = <1>;
222 interrupt-parent = <&gic>;
223 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
224 };
225 };
226 };
227};
diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
new file mode 100644
index 000000000000..bcd81ffc495d
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
@@ -0,0 +1,29 @@
1/*
2 * Device Tree file for Google Chromecast
3 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12
13#include "berlin2cd.dtsi"
14
15/ {
16 model = "Google Chromecast";
17 compatible = "google,chromecast", "marvell,berlin2cd", "marvell,berlin";
18
19 chosen {
20 bootargs = "console=ttyS0,115200 earlyprintk";
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0x00000000 0x20000000>; /* 512 MB */
26 };
27};
28
29&uart0 { status = "okay"; };
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
new file mode 100644
index 000000000000..094968c27533
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -0,0 +1,210 @@
1/*
2 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
3 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * based on GPL'ed 2.6 kernel sources
7 * (c) Marvell International Ltd.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include "skeleton.dtsi"
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16
17/ {
18 model = "Marvell Armada 1500-mini (BG2CD) SoC";
19 compatible = "marvell,berlin2cd", "marvell,berlin";
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu@0 {
26 compatible = "arm,cortex-a9";
27 device_type = "cpu";
28 next-level-cache = <&l2>;
29 reg = <0>;
30 };
31 };
32
33 clocks {
34 smclk: sysmgr-clock {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <25000000>;
38 };
39
40 cfgclk: cfg-clock {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <75000000>;
44 };
45
46 sysclk: system-clock {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <300000000>;
50 };
51 };
52
53 soc {
54 compatible = "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 interrupt-parent = <&gic>;
58
59 ranges = <0 0xf7000000 0x1000000>;
60
61 l2: l2-cache-controller@ac0000 {
62 compatible = "arm,pl310-cache";
63 reg = <0xac0000 0x1000>;
64 cache-unified;
65 cache-level = <2>;
66 };
67
68 gic: interrupt-controller@ad1000 {
69 compatible = "arm,cortex-a9-gic";
70 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
71 interrupt-controller;
72 #interrupt-cells = <3>;
73 };
74
75 local-timer@ad0600 {
76 compatible = "arm,cortex-a9-twd-timer";
77 reg = <0xad0600 0x20>;
78 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
79 clocks = <&sysclk>;
80 };
81
82 apb@e80000 {
83 compatible = "simple-bus";
84 #address-cells = <1>;
85 #size-cells = <1>;
86
87 ranges = <0 0xe80000 0x10000>;
88 interrupt-parent = <&aic>;
89
90 timer0: timer@2c00 {
91 compatible = "snps,dw-apb-timer";
92 reg = <0x2c00 0x14>;
93 interrupts = <8>;
94 clocks = <&cfgclk>;
95 clock-names = "timer";
96 status = "okay";
97 };
98
99 timer1: timer@2c14 {
100 compatible = "snps,dw-apb-timer";
101 reg = <0x2c14 0x14>;
102 interrupts = <9>;
103 clocks = <&cfgclk>;
104 clock-names = "timer";
105 status = "okay";
106 };
107
108 timer2: timer@2c28 {
109 compatible = "snps,dw-apb-timer";
110 reg = <0x2c28 0x14>;
111 interrupts = <10>;
112 clocks = <&cfgclk>;
113 clock-names = "timer";
114 status = "disabled";
115 };
116
117 timer3: timer@2c3c {
118 compatible = "snps,dw-apb-timer";
119 reg = <0x2c3c 0x14>;
120 interrupts = <11>;
121 clocks = <&cfgclk>;
122 clock-names = "timer";
123 status = "disabled";
124 };
125
126 timer4: timer@2c50 {
127 compatible = "snps,dw-apb-timer";
128 reg = <0x2c50 0x14>;
129 interrupts = <12>;
130 clocks = <&cfgclk>;
131 clock-names = "timer";
132 status = "disabled";
133 };
134
135 timer5: timer@2c64 {
136 compatible = "snps,dw-apb-timer";
137 reg = <0x2c64 0x14>;
138 interrupts = <13>;
139 clocks = <&cfgclk>;
140 clock-names = "timer";
141 status = "disabled";
142 };
143
144 timer6: timer@2c78 {
145 compatible = "snps,dw-apb-timer";
146 reg = <0x2c78 0x14>;
147 interrupts = <14>;
148 clocks = <&cfgclk>;
149 clock-names = "timer";
150 status = "disabled";
151 };
152
153 timer7: timer@2c8c {
154 compatible = "snps,dw-apb-timer";
155 reg = <0x2c8c 0x14>;
156 interrupts = <15>;
157 clocks = <&cfgclk>;
158 clock-names = "timer";
159 status = "disabled";
160 };
161
162 aic: interrupt-controller@3000 {
163 compatible = "snps,dw-apb-ictl";
164 reg = <0x3000 0xc00>;
165 interrupt-controller;
166 #interrupt-cells = <1>;
167 interrupt-parent = <&gic>;
168 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
169 };
170 };
171
172 apb@fc0000 {
173 compatible = "simple-bus";
174 #address-cells = <1>;
175 #size-cells = <1>;
176
177 ranges = <0 0xfc0000 0x10000>;
178 interrupt-parent = <&sic>;
179
180 uart0: serial@9000 {
181 compatible = "snps,dw-apb-uart";
182 reg = <0x9000 0x100>;
183 reg-shift = <2>;
184 reg-io-width = <1>;
185 interrupts = <8>;
186 clocks = <&smclk>;
187 status = "disabled";
188 };
189
190 uart1: serial@a000 {
191 compatible = "snps,dw-apb-uart";
192 reg = <0xa000 0x100>;
193 reg-shift = <2>;
194 reg-io-width = <1>;
195 interrupts = <9>;
196 clocks = <&smclk>;
197 status = "disabled";
198 };
199
200 sic: interrupt-controller@e000 {
201 compatible = "snps,dw-apb-ictl";
202 reg = <0xe000 0x400>;
203 interrupt-controller;
204 #interrupt-cells = <1>;
205 interrupt-parent = <&gic>;
206 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
207 };
208 };
209 };
210};
diff --git a/arch/arm/boot/dts/efm32gg-dk3750.dts b/arch/arm/boot/dts/efm32gg-dk3750.dts
new file mode 100644
index 000000000000..aa5c0f6363d6
--- /dev/null
+++ b/arch/arm/boot/dts/efm32gg-dk3750.dts
@@ -0,0 +1,86 @@
1/*
2 * Device tree for EFM32GG-DK3750 development board.
3 *
4 * Documentation available from
5 * http://www.silabs.com/Support%20Documents/TechnicalDocs/efm32gg-dk3750-ug.pdf
6 */
7
8/dts-v1/;
9#include "efm32gg.dtsi"
10
11/ {
12 model = "Energy Micro Giant Gecko Development Kit";
13 compatible = "efm32,dk3750";
14
15 chosen {
16 bootargs = "console=ttyefm4,115200 init=/linuxrc ignore_loglevel ihash_entries=64 dhash_entries=64 earlyprintk uclinux.physaddr=0x8c400000 root=/dev/mtdblock0";
17 };
18
19 memory {
20 reg = <0x88000000 0x400000>;
21 };
22
23 soc {
24 adc@40002000 {
25 status = "ok";
26 };
27
28 i2c@4000a000 {
29 location = <3>;
30 status = "ok";
31
32 temp@48 {
33 compatible = "st,stds75";
34 reg = <0x48>;
35 };
36
37 eeprom@50 {
38 compatible = "microchip,24c02";
39 reg = <0x50>;
40 pagesize = <16>;
41 };
42 };
43
44 spi0: spi@4000c000 { /* USART0 */
45 cs-gpios = <&gpio 68 1>; // E4
46 location = <1>;
47 status = "ok";
48
49 microsd@0 {
50 compatible = "mmc-spi-slot";
51 spi-max-frequency = <100000>;
52 voltage-ranges = <3200 3400>;
53 broken-cd;
54 reg = <0>;
55 };
56 };
57
58 spi1: spi@4000c400 { /* USART1 */
59 cs-gpios = <&gpio 51 1>; // D3
60 location = <1>;
61 status = "ok";
62
63 ks8851@0 {
64 compatible = "ks8851";
65 spi-max-frequency = <6000000>;
66 reg = <0>;
67 interrupt-parent = <&boardfpga>;
68 interrupts = <4>;
69 };
70 };
71
72 uart4: uart@4000e400 { /* UART1 */
73 location = <2>;
74 status = "ok";
75 };
76
77 boardfpga: boardfpga {
78 compatible = "efm32board";
79 reg = <0x80000000 0x400>;
80 irq-gpios = <&gpio 64 1>;
81 interrupt-controller;
82 #interrupt-cells = <1>;
83 status = "ok";
84 };
85 };
86};
diff --git a/arch/arm/boot/dts/efm32gg.dtsi b/arch/arm/boot/dts/efm32gg.dtsi
new file mode 100644
index 000000000000..a342ab0e6e4f
--- /dev/null
+++ b/arch/arm/boot/dts/efm32gg.dtsi
@@ -0,0 +1,172 @@
1/*
2 * Device tree for Energy Micro EFM32 Giant Gecko SoC.
3 *
4 * Documentation available from
5 * http://www.silabs.com/Support%20Documents/TechnicalDocs/EFM32GG-RM.pdf
6 */
7#include "armv7-m.dtsi"
8#include "dt-bindings/clock/efm32-cmu.h"
9
10/ {
11 aliases {
12 i2c0 = &i2c0;
13 i2c1 = &i2c1;
14 serial0 = &uart0;
15 serial1 = &uart1;
16 serial2 = &uart2;
17 serial3 = &uart3;
18 serial4 = &uart4;
19 spi0 = &spi0;
20 spi1 = &spi1;
21 spi2 = &spi2;
22 };
23
24 soc {
25 adc: adc@40002000 {
26 compatible = "efm32,adc";
27 reg = <0x40002000 0x400>;
28 interrupts = <7>;
29 clocks = <&cmu clk_HFPERCLKADC0>;
30 status = "disabled";
31 };
32
33 gpio: gpio@40006000 {
34 compatible = "efm32,gpio";
35 reg = <0x40006000 0x1000>;
36 interrupts = <1 11>;
37 gpio-controller;
38 #gpio-cells = <2>;
39 interrupt-controller;
40 #interrupt-cells = <1>;
41 clocks = <&cmu clk_HFPERCLKGPIO>;
42 status = "ok";
43 };
44
45 i2c0: i2c@4000a000 {
46 #address-cells = <1>;
47 #size-cells = <0>;
48 compatible = "efm32,i2c";
49 reg = <0x4000a000 0x400>;
50 interrupts = <9>;
51 clocks = <&cmu clk_HFPERCLKI2C0>;
52 clock-frequency = <100000>;
53 status = "disabled";
54 };
55
56 i2c1: i2c@4000a400 {
57 #address-cells = <1>;
58 #size-cells = <0>;
59 compatible = "efm32,i2c";
60 reg = <0x4000a400 0x400>;
61 interrupts = <10>;
62 clocks = <&cmu clk_HFPERCLKI2C1>;
63 clock-frequency = <100000>;
64 status = "disabled";
65 };
66
67 spi0: spi@4000c000 { /* USART0 */
68 #address-cells = <1>;
69 #size-cells = <0>;
70 compatible = "efm32,spi";
71 reg = <0x4000c000 0x400>;
72 interrupts = <3 4>;
73 clocks = <&cmu clk_HFPERCLKUSART0>;
74 status = "disabled";
75 };
76
77 spi1: spi@4000c400 { /* USART1 */
78 #address-cells = <1>;
79 #size-cells = <0>;
80 compatible = "efm32,spi";
81 reg = <0x4000c400 0x400>;
82 interrupts = <15 16>;
83 clocks = <&cmu clk_HFPERCLKUSART1>;
84 status = "disabled";
85 };
86
87 spi2: spi@40x4000c800 { /* USART2 */
88 #address-cells = <1>;
89 #size-cells = <0>;
90 compatible = "efm32,spi";
91 reg = <0x4000c800 0x400>;
92 interrupts = <18 19>;
93 clocks = <&cmu clk_HFPERCLKUSART2>;
94 status = "disabled";
95 };
96
97 uart0: uart@4000c000 { /* USART0 */
98 compatible = "efm32,uart";
99 reg = <0x4000c000 0x400>;
100 interrupts = <3 4>;
101 clocks = <&cmu clk_HFPERCLKUSART0>;
102 status = "disabled";
103 };
104
105 uart1: uart@4000c400 { /* USART1 */
106 compatible = "efm32,uart";
107 reg = <0x4000c400 0x400>;
108 interrupts = <15 16>;
109 clocks = <&cmu clk_HFPERCLKUSART1>;
110 status = "disabled";
111 };
112
113 uart2: uart@40x4000c800 { /* USART2 */
114 compatible = "efm32,uart";
115 reg = <0x4000c800 0x400>;
116 interrupts = <18 19>;
117 clocks = <&cmu clk_HFPERCLKUSART2>;
118 status = "disabled";
119 };
120
121 uart3: uart@4000e000 { /* UART0 */
122 compatible = "efm32,uart";
123 reg = <0x4000e000 0x400>;
124 interrupts = <20 21>;
125 clocks = <&cmu clk_HFPERCLKUART0>;
126 status = "disabled";
127 };
128
129 uart4: uart@4000e400 { /* UART1 */
130 compatible = "efm32,uart";
131 reg = <0x4000e400 0x400>;
132 interrupts = <22 23>;
133 clocks = <&cmu clk_HFPERCLKUART1>;
134 status = "disabled";
135 };
136
137 timer0: timer@40010000 {
138 compatible = "efm32,timer";
139 reg = <0x40010000 0x400>;
140 interrupts = <2>;
141 clocks = <&cmu clk_HFPERCLKTIMER0>;
142 };
143
144 timer1: timer@40010400 {
145 compatible = "efm32,timer";
146 reg = <0x40010400 0x400>;
147 interrupts = <12>;
148 clocks = <&cmu clk_HFPERCLKTIMER1>;
149 };
150
151 timer2: timer@40010800 {
152 compatible = "efm32,timer";
153 reg = <0x40010800 0x400>;
154 interrupts = <13>;
155 clocks = <&cmu clk_HFPERCLKTIMER2>;
156 };
157
158 timer3: timer@40010c00 {
159 compatible = "efm32,timer";
160 reg = <0x40010c00 0x400>;
161 interrupts = <14>;
162 clocks = <&cmu clk_HFPERCLKTIMER3>;
163 };
164
165 cmu: cmu@400c8000 {
166 compatible = "efm32gg,cmu";
167 reg = <0x400c8000 0x400>;
168 interrupts = <32>;
169 #clock-cells = <1>;
170 };
171 };
172};
diff --git a/arch/arm/boot/dts/hi3620-hi4511.dts b/arch/arm/boot/dts/hi3620-hi4511.dts
new file mode 100644
index 000000000000..fe623928f687
--- /dev/null
+++ b/arch/arm/boot/dts/hi3620-hi4511.dts
@@ -0,0 +1,649 @@
1/*
2 * Copyright (C) 2012-2013 Linaro Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/dts-v1/;
11
12#include "hi3620.dtsi"
13
14/ {
15 model = "Hisilicon Hi4511 Development Board";
16 compatible = "hisilicon,hi3620-hi4511";
17
18 chosen {
19 bootargs = "console=ttyAMA0,115200 root=/dev/ram0 earlyprintk";
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x40000000 0x20000000>;
25 };
26
27 amba {
28 dual_timer0: dual_timer@800000 {
29 status = "ok";
30 };
31
32 uart0: uart@b00000 { /* console */
33 pinctrl-names = "default", "idle";
34 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
35 pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>;
36 status = "ok";
37 };
38
39 uart1: uart@b01000 { /* modem */
40 pinctrl-names = "default", "idle";
41 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
42 pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>;
43 status = "ok";
44 };
45
46 uart2: uart@b02000 { /* audience */
47 pinctrl-names = "default", "idle";
48 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
49 pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>;
50 status = "ok";
51 };
52
53 uart3: uart@b03000 {
54 pinctrl-names = "default", "idle";
55 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
56 pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>;
57 status = "ok";
58 };
59
60 uart4: uart@b04000 {
61 pinctrl-names = "default", "idle";
62 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
63 pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>;
64 status = "ok";
65 };
66
67 pmx0: pinmux@803000 {
68 pinctrl-names = "default";
69 pinctrl-0 = <&board_pmx_pins>;
70
71 board_pmx_pins: board_pmx_pins {
72 pinctrl-single,pins = <
73 0x008 0x0 /* GPIO -- eFUSE_DOUT */
74 0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */
75 >;
76 };
77 uart0_pmx_func: uart0_pmx_func {
78 pinctrl-single,pins = <
79 0x0f0 0x0
80 0x0f4 0x0 /* UART0_RX & UART0_TX */
81 >;
82 };
83 uart0_pmx_idle: uart0_pmx_idle {
84 pinctrl-single,pins = <
85 /*0x0f0 0x1*/ /* UART0_CTS & UART0_RTS */
86 0x0f4 0x1 /* UART0_RX & UART0_TX */
87 >;
88 };
89 uart1_pmx_func: uart1_pmx_func {
90 pinctrl-single,pins = <
91 0x0f8 0x0 /* UART1_CTS & UART1_RTS (IOMG61) */
92 0x0fc 0x0 /* UART1_RX & UART1_TX (IOMG62) */
93 >;
94 };
95 uart1_pmx_idle: uart1_pmx_idle {
96 pinctrl-single,pins = <
97 0x0f8 0x1 /* GPIO (IOMG61) */
98 0x0fc 0x1 /* GPIO (IOMG62) */
99 >;
100 };
101 uart2_pmx_func: uart2_pmx_func {
102 pinctrl-single,pins = <
103 0x104 0x2 /* UART2_RXD (IOMG96) */
104 0x108 0x2 /* UART2_TXD (IOMG64) */
105 >;
106 };
107 uart2_pmx_idle: uart2_pmx_idle {
108 pinctrl-single,pins = <
109 0x104 0x1 /* GPIO (IOMG96) */
110 0x108 0x1 /* GPIO (IOMG64) */
111 >;
112 };
113 uart3_pmx_func: uart3_pmx_func {
114 pinctrl-single,pins = <
115 0x160 0x2 /* UART3_CTS & UART3_RTS (IOMG85) */
116 0x164 0x2 /* UART3_RXD & UART3_TXD (IOMG86) */
117 >;
118 };
119 uart3_pmx_idle: uart3_pmx_idle {
120 pinctrl-single,pins = <
121 0x160 0x1 /* GPIO (IOMG85) */
122 0x164 0x1 /* GPIO (IOMG86) */
123 >;
124 };
125 uart4_pmx_func: uart4_pmx_func {
126 pinctrl-single,pins = <
127 0x168 0x0 /* UART4_CTS & UART4_RTS (IOMG87) */
128 0x16c 0x0 /* UART4_RXD (IOMG88) */
129 0x170 0x0 /* UART4_TXD (IOMG93) */
130 >;
131 };
132 uart4_pmx_idle: uart4_pmx_idle {
133 pinctrl-single,pins = <
134 0x168 0x1 /* GPIO (IOMG87) */
135 0x16c 0x1 /* GPIO (IOMG88) */
136 0x170 0x1 /* GPIO (IOMG93) */
137 >;
138 };
139 i2c0_pmx_func: i2c0_pmx_func {
140 pinctrl-single,pins = <
141 0x0b4 0x0 /* I2C0_SCL & I2C0_SDA (IOMG45) */
142 >;
143 };
144 i2c0_pmx_idle: i2c0_pmx_idle {
145 pinctrl-single,pins = <
146 0x0b4 0x1 /* GPIO (IOMG45) */
147 >;
148 };
149 i2c1_pmx_func: i2c1_pmx_func {
150 pinctrl-single,pins = <
151 0x0b8 0x0 /* I2C1_SCL & I2C1_SDA (IOMG46) */
152 >;
153 };
154 i2c1_pmx_idle: i2c1_pmx_idle {
155 pinctrl-single,pins = <
156 0x0b8 0x1 /* GPIO (IOMG46) */
157 >;
158 };
159 i2c2_pmx_func: i2c2_pmx_func {
160 pinctrl-single,pins = <
161 0x068 0x0 /* I2C2_SCL (IOMG26) */
162 0x06c 0x0 /* I2C2_SDA (IOMG27) */
163 >;
164 };
165 i2c2_pmx_idle: i2c2_pmx_idle {
166 pinctrl-single,pins = <
167 0x068 0x1 /* GPIO (IOMG26) */
168 0x06c 0x1 /* GPIO (IOMG27) */
169 >;
170 };
171 i2c3_pmx_func: i2c3_pmx_func {
172 pinctrl-single,pins = <
173 0x050 0x2 /* I2C3_SCL (IOMG20) */
174 0x054 0x2 /* I2C3_SDA (IOMG21) */
175 >;
176 };
177 i2c3_pmx_idle: i2c3_pmx_idle {
178 pinctrl-single,pins = <
179 0x050 0x1 /* GPIO (IOMG20) */
180 0x054 0x1 /* GPIO (IOMG21) */
181 >;
182 };
183 spi0_pmx_func: spi0_pmx_func {
184 pinctrl-single,pins = <
185 0x0d4 0x0 /* SPI0_CLK/SPI0_DI/SPI0_DO (IOMG53) */
186 0x0d8 0x0 /* SPI0_CS0 (IOMG54) */
187 0x0dc 0x0 /* SPI0_CS1 (IOMG55) */
188 0x0e0 0x0 /* SPI0_CS2 (IOMG56) */
189 0x0e4 0x0 /* SPI0_CS3 (IOMG57) */
190 >;
191 };
192 spi0_pmx_idle: spi0_pmx_idle {
193 pinctrl-single,pins = <
194 0x0d4 0x1 /* GPIO (IOMG53) */
195 0x0d8 0x1 /* GPIO (IOMG54) */
196 0x0dc 0x1 /* GPIO (IOMG55) */
197 0x0e0 0x1 /* GPIO (IOMG56) */
198 0x0e4 0x1 /* GPIO (IOMG57) */
199 >;
200 };
201 spi1_pmx_func: spi1_pmx_func {
202 pinctrl-single,pins = <
203 0x184 0x0 /* SPI1_CLK/SPI1_DI (IOMG98) */
204 0x0e8 0x0 /* SPI1_DO (IOMG58) */
205 0x0ec 0x0 /* SPI1_CS (IOMG95) */
206 >;
207 };
208 spi1_pmx_idle: spi1_pmx_idle {
209 pinctrl-single,pins = <
210 0x184 0x1 /* GPIO (IOMG98) */
211 0x0e8 0x1 /* GPIO (IOMG58) */
212 0x0ec 0x1 /* GPIO (IOMG95) */
213 >;
214 };
215 kpc_pmx_func: kpc_pmx_func {
216 pinctrl-single,pins = <
217 0x12c 0x0 /* KEY_IN0 (IOMG73) */
218 0x130 0x0 /* KEY_IN1 (IOMG74) */
219 0x134 0x0 /* KEY_IN2 (IOMG75) */
220 0x10c 0x0 /* KEY_OUT0 (IOMG65) */
221 0x110 0x0 /* KEY_OUT1 (IOMG66) */
222 0x114 0x0 /* KEY_OUT2 (IOMG67) */
223 >;
224 };
225 kpc_pmx_idle: kpc_pmx_idle {
226 pinctrl-single,pins = <
227 0x12c 0x1 /* GPIO (IOMG73) */
228 0x130 0x1 /* GPIO (IOMG74) */
229 0x134 0x1 /* GPIO (IOMG75) */
230 0x10c 0x1 /* GPIO (IOMG65) */
231 0x110 0x1 /* GPIO (IOMG66) */
232 0x114 0x1 /* GPIO (IOMG67) */
233 >;
234 };
235 gpio_key_func: gpio_key_func {
236 pinctrl-single,pins = <
237 0x10c 0x1 /* KEY_OUT0/GPIO (IOMG65) */
238 0x130 0x1 /* KEY_IN1/GPIO (IOMG74) */
239 >;
240 };
241 emmc_pmx_func: emmc_pmx_func {
242 pinctrl-single,pins = <
243 0x030 0x2 /* eMMC_CMD/eMMC_CLK (IOMG12) */
244 0x018 0x0 /* NAND_CS3_N (IOMG6) */
245 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */
246 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */
247 0x02c 0x2 /* eMMC_DATA[0:7] (IOMG10) */
248 >;
249 };
250 emmc_pmx_idle: emmc_pmx_idle {
251 pinctrl-single,pins = <
252 0x030 0x0 /* GPIO (IOMG12) */
253 0x018 0x1 /* GPIO (IOMG6) */
254 0x024 0x1 /* GPIO (IOMG8) */
255 0x028 0x1 /* GPIO (IOMG9) */
256 0x02c 0x1 /* GPIO (IOMG10) */
257 >;
258 };
259 sd_pmx_func: sd_pmx_func {
260 pinctrl-single,pins = <
261 0x0bc 0x0 /* SD_CLK/SD_CMD/SD_DATA0/SD_DATA1/SD_DATA2 (IOMG47) */
262 0x0c0 0x0 /* SD_DATA3 (IOMG48) */
263 >;
264 };
265 sd_pmx_idle: sd_pmx_idle {
266 pinctrl-single,pins = <
267 0x0bc 0x1 /* GPIO (IOMG47) */
268 0x0c0 0x1 /* GPIO (IOMG48) */
269 >;
270 };
271 nand_pmx_func: nand_pmx_func {
272 pinctrl-single,pins = <
273 0x00c 0x0 /* NAND_ALE/NAND_CLE/.../NAND_DATA[0:7] (IOMG3) */
274 0x010 0x0 /* NAND_CS1_N (IOMG4) */
275 0x014 0x0 /* NAND_CS2_N (IOMG5) */
276 0x018 0x0 /* NAND_CS3_N (IOMG6) */
277 0x01c 0x0 /* NAND_BUSY0_N (IOMG94) */
278 0x020 0x0 /* NAND_BUSY1_N (IOMG7) */
279 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */
280 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */
281 0x02c 0x0 /* NAND_DATA[8:15] (IOMG10) */
282 >;
283 };
284 nand_pmx_idle: nand_pmx_idle {
285 pinctrl-single,pins = <
286 0x00c 0x1 /* GPIO (IOMG3) */
287 0x010 0x1 /* GPIO (IOMG4) */
288 0x014 0x1 /* GPIO (IOMG5) */
289 0x018 0x1 /* GPIO (IOMG6) */
290 0x01c 0x1 /* GPIO (IOMG94) */
291 0x020 0x1 /* GPIO (IOMG7) */
292 0x024 0x1 /* GPIO (IOMG8) */
293 0x028 0x1 /* GPIO (IOMG9) */
294 0x02c 0x1 /* GPIO (IOMG10) */
295 >;
296 };
297 sdio_pmx_func: sdio_pmx_func {
298 pinctrl-single,pins = <
299 0x0c4 0x0 /* SDIO_CLK/SDIO_CMD/SDIO_DATA[0:3] (IOMG49) */
300 >;
301 };
302 sdio_pmx_idle: sdio_pmx_idle {
303 pinctrl-single,pins = <
304 0x0c4 0x1 /* GPIO (IOMG49) */
305 >;
306 };
307 audio_out_pmx_func: audio_out_pmx_func {
308 pinctrl-single,pins = <
309 0x0f0 0x1 /* GPIO (IOMG59), audio spk & earphone */
310 >;
311 };
312 };
313
314 pmx1: pinmux@803800 {
315 pinctrl-names = "default";
316 pinctrl-0 = < &board_pu_pins &board_pd_pins &board_pd_ps_pins
317 &board_np_pins &board_ps_pins &kpc_cfg_func
318 &audio_out_cfg_func>;
319 board_pu_pins: board_pu_pins {
320 pinctrl-single,pins = <
321 0x014 0 /* GPIO_158 (IOCFG2) */
322 0x018 0 /* GPIO_159 (IOCFG3) */
323 0x01c 0 /* BOOT_MODE0 (IOCFG4) */
324 0x020 0 /* BOOT_MODE1 (IOCFG5) */
325 >;
326 pinctrl-single,bias-pulldown = <0 2 0 2>;
327 pinctrl-single,bias-pullup = <1 1 0 1>;
328 };
329 board_pd_pins: board_pd_pins {
330 pinctrl-single,pins = <
331 0x038 0 /* eFUSE_DOUT (IOCFG11) */
332 0x150 0 /* ISP_GPIO8 (IOCFG93) */
333 0x154 0 /* ISP_GPIO9 (IOCFG94) */
334 >;
335 pinctrl-single,bias-pulldown = <2 2 0 2>;
336 pinctrl-single,bias-pullup = <0 1 0 1>;
337 };
338 board_pd_ps_pins: board_pd_ps_pins {
339 pinctrl-single,pins = <
340 0x2d8 0 /* CLK_OUT0 (IOCFG190) */
341 0x004 0 /* PMU_SPI_DATA (IOCFG192) */
342 >;
343 pinctrl-single,bias-pulldown = <2 2 0 2>;
344 pinctrl-single,bias-pullup = <0 1 0 1>;
345 pinctrl-single,drive-strength = <0x30 0xf0>;
346 };
347 board_np_pins: board_np_pins {
348 pinctrl-single,pins = <
349 0x24c 0 /* KEYPAD_OUT7 (IOCFG155) */
350 >;
351 pinctrl-single,bias-pulldown = <0 2 0 2>;
352 pinctrl-single,bias-pullup = <0 1 0 1>;
353 };
354 board_ps_pins: board_ps_pins {
355 pinctrl-single,pins = <
356 0x000 0 /* PMU_SPI_CLK (IOCFG191) */
357 0x008 0 /* PMU_SPI_CS_N (IOCFG193) */
358 >;
359 pinctrl-single,drive-strength = <0x30 0xf0>;
360 };
361 uart0_cfg_func: uart0_cfg_func {
362 pinctrl-single,pins = <
363 0x208 0 /* UART0_RXD (IOCFG138) */
364 0x20c 0 /* UART0_TXD (IOCFG139) */
365 >;
366 pinctrl-single,bias-pulldown = <0 2 0 2>;
367 pinctrl-single,bias-pullup = <0 1 0 1>;
368 };
369 uart0_cfg_idle: uart0_cfg_idle {
370 pinctrl-single,pins = <
371 0x208 0 /* UART0_RXD (IOCFG138) */
372 0x20c 0 /* UART0_TXD (IOCFG139) */
373 >;
374 pinctrl-single,bias-pulldown = <2 2 0 2>;
375 pinctrl-single,bias-pullup = <0 1 0 1>;
376 };
377 uart1_cfg_func: uart1_cfg_func {
378 pinctrl-single,pins = <
379 0x210 0 /* UART1_CTS (IOCFG140) */
380 0x214 0 /* UART1_RTS (IOCFG141) */
381 0x218 0 /* UART1_RXD (IOCFG142) */
382 0x21c 0 /* UART1_TXD (IOCFG143) */
383 >;
384 pinctrl-single,bias-pulldown = <0 2 0 2>;
385 pinctrl-single,bias-pullup = <0 1 0 1>;
386 };
387 uart1_cfg_idle: uart1_cfg_idle {
388 pinctrl-single,pins = <
389 0x210 0 /* UART1_CTS (IOCFG140) */
390 0x214 0 /* UART1_RTS (IOCFG141) */
391 0x218 0 /* UART1_RXD (IOCFG142) */
392 0x21c 0 /* UART1_TXD (IOCFG143) */
393 >;
394 pinctrl-single,bias-pulldown = <2 2 0 2>;
395 pinctrl-single,bias-pullup = <0 1 0 1>;
396 };
397 uart2_cfg_func: uart2_cfg_func {
398 pinctrl-single,pins = <
399 0x220 0 /* UART2_CTS (IOCFG144) */
400 0x224 0 /* UART2_RTS (IOCFG145) */
401 0x228 0 /* UART2_RXD (IOCFG146) */
402 0x22c 0 /* UART2_TXD (IOCFG147) */
403 >;
404 pinctrl-single,bias-pulldown = <0 2 0 2>;
405 pinctrl-single,bias-pullup = <0 1 0 1>;
406 };
407 uart2_cfg_idle: uart2_cfg_idle {
408 pinctrl-single,pins = <
409 0x220 0 /* GPIO (IOCFG144) */
410 0x224 0 /* GPIO (IOCFG145) */
411 0x228 0 /* GPIO (IOCFG146) */
412 0x22c 0 /* GPIO (IOCFG147) */
413 >;
414 pinctrl-single,bias-pulldown = <2 2 0 2>;
415 pinctrl-single,bias-pullup = <0 1 0 1>;
416 };
417 uart3_cfg_func: uart3_cfg_func {
418 pinctrl-single,pins = <
419 0x294 0 /* UART3_CTS (IOCFG173) */
420 0x298 0 /* UART3_RTS (IOCFG174) */
421 0x29c 0 /* UART3_RXD (IOCFG175) */
422 0x2a0 0 /* UART3_TXD (IOCFG176) */
423 >;
424 pinctrl-single,bias-pulldown = <0 2 0 2>;
425 pinctrl-single,bias-pullup = <0 1 0 1>;
426 };
427 uart3_cfg_idle: uart3_cfg_idle {
428 pinctrl-single,pins = <
429 0x294 0 /* UART3_CTS (IOCFG173) */
430 0x298 0 /* UART3_RTS (IOCFG174) */
431 0x29c 0 /* UART3_RXD (IOCFG175) */
432 0x2a0 0 /* UART3_TXD (IOCFG176) */
433 >;
434 pinctrl-single,bias-pulldown = <2 2 0 2>;
435 pinctrl-single,bias-pullup = <0 1 0 1>;
436 };
437 uart4_cfg_func: uart4_cfg_func {
438 pinctrl-single,pins = <
439 0x2a4 0 /* UART4_CTS (IOCFG177) */
440 0x2a8 0 /* UART4_RTS (IOCFG178) */
441 0x2ac 0 /* UART4_RXD (IOCFG179) */
442 0x2b0 0 /* UART4_TXD (IOCFG180) */
443 >;
444 pinctrl-single,bias-pulldown = <0 2 0 2>;
445 pinctrl-single,bias-pullup = <0 1 0 1>;
446 };
447 i2c0_cfg_func: i2c0_cfg_func {
448 pinctrl-single,pins = <
449 0x17c 0 /* I2C0_SCL (IOCFG103) */
450 0x180 0 /* I2C0_SDA (IOCFG104) */
451 >;
452 pinctrl-single,bias-pulldown = <0 2 0 2>;
453 pinctrl-single,bias-pullup = <0 1 0 1>;
454 pinctrl-single,drive-strength = <0x30 0xf0>;
455 };
456 i2c1_cfg_func: i2c1_cfg_func {
457 pinctrl-single,pins = <
458 0x184 0 /* I2C1_SCL (IOCFG105) */
459 0x188 0 /* I2C1_SDA (IOCFG106) */
460 >;
461 pinctrl-single,bias-pulldown = <0 2 0 2>;
462 pinctrl-single,bias-pullup = <0 1 0 1>;
463 pinctrl-single,drive-strength = <0x30 0xf0>;
464 };
465 i2c2_cfg_func: i2c2_cfg_func {
466 pinctrl-single,pins = <
467 0x118 0 /* I2C2_SCL (IOCFG79) */
468 0x11c 0 /* I2C2_SDA (IOCFG80) */
469 >;
470 pinctrl-single,bias-pulldown = <0 2 0 2>;
471 pinctrl-single,bias-pullup = <0 1 0 1>;
472 pinctrl-single,drive-strength = <0x30 0xf0>;
473 };
474 i2c3_cfg_func: i2c3_cfg_func {
475 pinctrl-single,pins = <
476 0x100 0 /* I2C3_SCL (IOCFG73) */
477 0x104 0 /* I2C3_SDA (IOCFG74) */
478 >;
479 pinctrl-single,bias-pulldown = <0 2 0 2>;
480 pinctrl-single,bias-pullup = <0 1 0 1>;
481 pinctrl-single,drive-strength = <0x30 0xf0>;
482 };
483 spi0_cfg_func1: spi0_cfg_func1 {
484 pinctrl-single,pins = <
485 0x1d4 0 /* SPI0_CLK (IOCFG125) */
486 0x1d8 0 /* SPI0_DI (IOCFG126) */
487 0x1dc 0 /* SPI0_DO (IOCFG127) */
488 >;
489 pinctrl-single,bias-pulldown = <2 2 0 2>;
490 pinctrl-single,bias-pullup = <0 1 0 1>;
491 pinctrl-single,drive-strength = <0x30 0xf0>;
492 };
493 spi0_cfg_func2: spi0_cfg_func2 {
494 pinctrl-single,pins = <
495 0x1e0 0 /* SPI0_CS0 (IOCFG128) */
496 0x1e4 0 /* SPI0_CS1 (IOCFG129) */
497 0x1e8 0 /* SPI0_CS2 (IOCFG130 */
498 0x1ec 0 /* SPI0_CS3 (IOCFG131) */
499 >;
500 pinctrl-single,bias-pulldown = <0 2 0 2>;
501 pinctrl-single,bias-pullup = <1 1 0 1>;
502 pinctrl-single,drive-strength = <0x30 0xf0>;
503 };
504 spi1_cfg_func1: spi1_cfg_func1 {
505 pinctrl-single,pins = <
506 0x1f0 0 /* SPI1_CLK (IOCFG132) */
507 0x1f4 0 /* SPI1_DI (IOCFG133) */
508 0x1f8 0 /* SPI1_DO (IOCFG134) */
509 >;
510 pinctrl-single,bias-pulldown = <2 2 0 2>;
511 pinctrl-single,bias-pullup = <0 1 0 1>;
512 pinctrl-single,drive-strength = <0x30 0xf0>;
513 };
514 spi1_cfg_func2: spi1_cfg_func2 {
515 pinctrl-single,pins = <
516 0x1fc 0 /* SPI1_CS (IOCFG135) */
517 >;
518 pinctrl-single,bias-pulldown = <0 2 0 2>;
519 pinctrl-single,bias-pullup = <1 1 0 1>;
520 pinctrl-single,drive-strength = <0x30 0xf0>;
521 };
522 kpc_cfg_func: kpc_cfg_func {
523 pinctrl-single,pins = <
524 0x250 0 /* KEY_IN0 (IOCFG156) */
525 0x254 0 /* KEY_IN1 (IOCFG157) */
526 0x258 0 /* KEY_IN2 (IOCFG158) */
527 0x230 0 /* KEY_OUT0 (IOCFG148) */
528 0x234 0 /* KEY_OUT1 (IOCFG149) */
529 0x238 0 /* KEY_OUT2 (IOCFG150) */
530 >;
531 pinctrl-single,bias-pulldown = <2 2 0 2>;
532 pinctrl-single,bias-pullup = <0 1 0 1>;
533 };
534 emmc_cfg_func: emmc_cfg_func {
535 pinctrl-single,pins = <
536 0x0ac 0 /* eMMC_CMD (IOCFG40) */
537 0x0b0 0 /* eMMC_CLK (IOCFG41) */
538 0x058 0 /* NAND_CS3_N (IOCFG19) */
539 0x064 0 /* NAND_BUSY2_N (IOCFG22) */
540 0x068 0 /* NAND_BUSY3_N (IOCFG23) */
541 0x08c 0 /* NAND_DATA8 (IOCFG32) */
542 0x090 0 /* NAND_DATA9 (IOCFG33) */
543 0x094 0 /* NAND_DATA10 (IOCFG34) */
544 0x098 0 /* NAND_DATA11 (IOCFG35) */
545 0x09c 0 /* NAND_DATA12 (IOCFG36) */
546 0x0a0 0 /* NAND_DATA13 (IOCFG37) */
547 0x0a4 0 /* NAND_DATA14 (IOCFG38) */
548 0x0a8 0 /* NAND_DATA15 (IOCFG39) */
549 >;
550 pinctrl-single,bias-pulldown = <0 2 0 2>;
551 pinctrl-single,bias-pullup = <1 1 0 1>;
552 pinctrl-single,drive-strength = <0x30 0xf0>;
553 };
554 sd_cfg_func1: sd_cfg_func1 {
555 pinctrl-single,pins = <
556 0x18c 0 /* SD_CLK (IOCFG107) */
557 0x190 0 /* SD_CMD (IOCFG108) */
558 >;
559 pinctrl-single,bias-pulldown = <2 2 0 2>;
560 pinctrl-single,bias-pullup = <0 1 0 1>;
561 pinctrl-single,drive-strength = <0x30 0xf0>;
562 };
563 sd_cfg_func2: sd_cfg_func2 {
564 pinctrl-single,pins = <
565 0x194 0 /* SD_DATA0 (IOCFG109) */
566 0x198 0 /* SD_DATA1 (IOCFG110) */
567 0x19c 0 /* SD_DATA2 (IOCFG111) */
568 0x1a0 0 /* SD_DATA3 (IOCFG112) */
569 >;
570 pinctrl-single,bias-pulldown = <2 2 0 2>;
571 pinctrl-single,bias-pullup = <0 1 0 1>;
572 pinctrl-single,drive-strength = <0x70 0xf0>;
573 };
574 nand_cfg_func1: nand_cfg_func1 {
575 pinctrl-single,pins = <
576 0x03c 0 /* NAND_ALE (IOCFG12) */
577 0x040 0 /* NAND_CLE (IOCFG13) */
578 0x06c 0 /* NAND_DATA0 (IOCFG24) */
579 0x070 0 /* NAND_DATA1 (IOCFG25) */
580 0x074 0 /* NAND_DATA2 (IOCFG26) */
581 0x078 0 /* NAND_DATA3 (IOCFG27) */
582 0x07c 0 /* NAND_DATA4 (IOCFG28) */
583 0x080 0 /* NAND_DATA5 (IOCFG29) */
584 0x084 0 /* NAND_DATA6 (IOCFG30) */
585 0x088 0 /* NAND_DATA7 (IOCFG31) */
586 0x08c 0 /* NAND_DATA8 (IOCFG32) */
587 0x090 0 /* NAND_DATA9 (IOCFG33) */
588 0x094 0 /* NAND_DATA10 (IOCFG34) */
589 0x098 0 /* NAND_DATA11 (IOCFG35) */
590 0x09c 0 /* NAND_DATA12 (IOCFG36) */
591 0x0a0 0 /* NAND_DATA13 (IOCFG37) */
592 0x0a4 0 /* NAND_DATA14 (IOCFG38) */
593 0x0a8 0 /* NAND_DATA15 (IOCFG39) */
594 >;
595 pinctrl-single,bias-pulldown = <2 2 0 2>;
596 pinctrl-single,bias-pullup = <0 1 0 1>;
597 pinctrl-single,drive-strength = <0x30 0xf0>;
598 };
599 nand_cfg_func2: nand_cfg_func2 {
600 pinctrl-single,pins = <
601 0x044 0 /* NAND_RE_N (IOCFG14) */
602 0x048 0 /* NAND_WE_N (IOCFG15) */
603 0x04c 0 /* NAND_CS0_N (IOCFG16) */
604 0x050 0 /* NAND_CS1_N (IOCFG17) */
605 0x054 0 /* NAND_CS2_N (IOCFG18) */
606 0x058 0 /* NAND_CS3_N (IOCFG19) */
607 0x05c 0 /* NAND_BUSY0_N (IOCFG20) */
608 0x060 0 /* NAND_BUSY1_N (IOCFG21) */
609 0x064 0 /* NAND_BUSY2_N (IOCFG22) */
610 0x068 0 /* NAND_BUSY3_N (IOCFG23) */
611 >;
612 pinctrl-single,bias-pulldown = <0 2 0 2>;
613 pinctrl-single,bias-pullup = <1 1 0 1>;
614 pinctrl-single,drive-strength = <0x30 0xf0>;
615 };
616 sdio_cfg_func: sdio_cfg_func {
617 pinctrl-single,pins = <
618 0x1a4 0 /* SDIO0_CLK (IOCG113) */
619 0x1a8 0 /* SDIO0_CMD (IOCG114) */
620 0x1ac 0 /* SDIO0_DATA0 (IOCG115) */
621 0x1b0 0 /* SDIO0_DATA1 (IOCG116) */
622 0x1b4 0 /* SDIO0_DATA2 (IOCG117) */
623 0x1b8 0 /* SDIO0_DATA3 (IOCG118) */
624 >;
625 pinctrl-single,bias-pulldown = <2 2 0 2>;
626 pinctrl-single,bias-pullup = <0 1 0 1>;
627 pinctrl-single,drive-strength = <0x30 0xf0>;
628 };
629 audio_out_cfg_func: audio_out_cfg_func {
630 pinctrl-single,pins = <
631 0x200 0 /* GPIO (IOCFG136) */
632 0x204 0 /* GPIO (IOCFG137) */
633 >;
634 pinctrl-single,bias-pulldown = <2 2 0 2>;
635 pinctrl-single,bias-pullup = <0 1 0 1>;
636 };
637 };
638 };
639
640 gpio-keys {
641 compatible = "gpio-keys";
642
643 call {
644 label = "call";
645 gpios = <&gpio17 2 0>;
646 linux,code = <169>; /* KEY_PHONE */
647 };
648 };
649};
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
new file mode 100644
index 000000000000..ab1116d086be
--- /dev/null
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -0,0 +1,565 @@
1/*
2 * Hisilicon Ltd. Hi3620 SoC
3 *
4 * Copyright (C) 2012-2013 Hisilicon Ltd.
5 * Copyright (C) 2012-2013 Linaro Ltd.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * publishhed by the Free Software Foundation.
12 */
13
14#include "skeleton.dtsi"
15#include <dt-bindings/clock/hi3620-clock.h>
16
17/ {
18 aliases {
19 serial0 = &uart0;
20 serial1 = &uart1;
21 serial2 = &uart2;
22 serial3 = &uart3;
23 serial4 = &uart4;
24 };
25
26 pclk: clk {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <26000000>;
30 clock-output-names = "apb_pclk";
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 cpu@0 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a9";
40 reg = <0x0>;
41 next-level-cache = <&L2>;
42 };
43
44 cpu@1 {
45 compatible = "arm,cortex-a9";
46 device_type = "cpu";
47 reg = <1>;
48 next-level-cache = <&L2>;
49 };
50
51 cpu@2 {
52 compatible = "arm,cortex-a9";
53 device_type = "cpu";
54 reg = <2>;
55 next-level-cache = <&L2>;
56 };
57
58 cpu@3 {
59 compatible = "arm,cortex-a9";
60 device_type = "cpu";
61 reg = <3>;
62 next-level-cache = <&L2>;
63 };
64 };
65
66 amba {
67
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "arm,amba-bus";
71 interrupt-parent = <&gic>;
72 ranges = <0 0xfc000000 0x2000000>;
73
74 L2: l2-cache {
75 compatible = "arm,pl310-cache";
76 reg = <0xfc10000 0x100000>;
77 interrupts = <0 15 4>;
78 cache-unified;
79 cache-level = <2>;
80 };
81
82 gic: interrupt-controller@1000 {
83 compatible = "arm,cortex-a9-gic";
84 #interrupt-cells = <3>;
85 #address-cells = <0>;
86 interrupt-controller;
87 /* gic dist base, gic cpu base */
88 reg = <0x1000 0x1000>, <0x100 0x100>;
89 };
90
91 sysctrl: system-controller@802000 {
92 compatible = "hisilicon,sysctrl";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0 0x802000 0x1000>;
96 reg = <0x802000 0x1000>;
97
98 smp-offset = <0x31c>;
99 resume-offset = <0x308>;
100 reboot-offset = <0x4>;
101
102 clock: clock@0 {
103 compatible = "hisilicon,hi3620-clock";
104 reg = <0 0x10000>;
105 #clock-cells = <1>;
106 };
107 };
108
109 dual_timer0: dual_timer@800000 {
110 compatible = "arm,sp804", "arm,primecell";
111 reg = <0x800000 0x1000>;
112 /* timer00 & timer01 */
113 interrupts = <0 0 4>, <0 1 4>;
114 clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
115 clock-names = "apb_pclk";
116 status = "disabled";
117 };
118
119 dual_timer1: dual_timer@801000 {
120 compatible = "arm,sp804", "arm,primecell";
121 reg = <0x801000 0x1000>;
122 /* timer10 & timer11 */
123 interrupts = <0 2 4>, <0 3 4>;
124 clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
125 clock-names = "apb_pclk";
126 status = "disabled";
127 };
128
129 dual_timer2: dual_timer@a01000 {
130 compatible = "arm,sp804", "arm,primecell";
131 reg = <0xa01000 0x1000>;
132 /* timer20 & timer21 */
133 interrupts = <0 4 4>, <0 5 4>;
134 clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
135 clock-names = "apb_pclk";
136 status = "disabled";
137 };
138
139 dual_timer3: dual_timer@a02000 {
140 compatible = "arm,sp804", "arm,primecell";
141 reg = <0xa02000 0x1000>;
142 /* timer30 & timer31 */
143 interrupts = <0 6 4>, <0 7 4>;
144 clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
145 clock-names = "apb_pclk";
146 status = "disabled";
147 };
148
149 dual_timer4: dual_timer@a03000 {
150 compatible = "arm,sp804", "arm,primecell";
151 reg = <0xa03000 0x1000>;
152 /* timer40 & timer41 */
153 interrupts = <0 96 4>, <0 97 4>;
154 clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
155 clock-names = "apb_pclk";
156 status = "disabled";
157 };
158
159 timer5: timer@600 {
160 compatible = "arm,cortex-a9-twd-timer";
161 reg = <0x600 0x20>;
162 interrupts = <1 13 0xf01>;
163 };
164
165 uart0: uart@b00000 {
166 compatible = "arm,pl011", "arm,primecell";
167 reg = <0xb00000 0x1000>;
168 interrupts = <0 20 4>;
169 clocks = <&clock HI3620_UARTCLK0>;
170 clock-names = "apb_pclk";
171 status = "disabled";
172 };
173
174 uart1: uart@b01000 {
175 compatible = "arm,pl011", "arm,primecell";
176 reg = <0xb01000 0x1000>;
177 interrupts = <0 21 4>;
178 clocks = <&clock HI3620_UARTCLK1>;
179 clock-names = "apb_pclk";
180 status = "disabled";
181 };
182
183 uart2: uart@b02000 {
184 compatible = "arm,pl011", "arm,primecell";
185 reg = <0xb02000 0x1000>;
186 interrupts = <0 22 4>;
187 clocks = <&clock HI3620_UARTCLK2>;
188 clock-names = "apb_pclk";
189 status = "disabled";
190 };
191
192 uart3: uart@b03000 {
193 compatible = "arm,pl011", "arm,primecell";
194 reg = <0xb03000 0x1000>;
195 interrupts = <0 23 4>;
196 clocks = <&clock HI3620_UARTCLK3>;
197 clock-names = "apb_pclk";
198 status = "disabled";
199 };
200
201 uart4: uart@b04000 {
202 compatible = "arm,pl011", "arm,primecell";
203 reg = <0xb04000 0x1000>;
204 interrupts = <0 24 4>;
205 clocks = <&clock HI3620_UARTCLK4>;
206 clock-names = "apb_pclk";
207 status = "disabled";
208 };
209
210 gpio0: gpio@806000 {
211 compatible = "arm,pl061", "arm,primecell";
212 reg = <0x806000 0x1000>;
213 interrupts = <0 64 0x4>;
214 gpio-controller;
215 #gpio-cells = <2>;
216 gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
217 &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
218 interrupt-controller;
219 #interrupt-cells = <2>;
220 clocks = <&clock HI3620_GPIOCLK0>;
221 clock-names = "apb_pclk";
222 };
223
224 gpio1: gpio@807000 {
225 compatible = "arm,pl061", "arm,primecell";
226 reg = <0x807000 0x1000>;
227 interrupts = <0 65 0x4>;
228 gpio-controller;
229 #gpio-cells = <2>;
230 gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
231 &pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
232 &pmx0 6 5 1 &pmx0 7 6 1>;
233 interrupt-controller;
234 #interrupt-cells = <2>;
235 clocks = <&clock HI3620_GPIOCLK1>;
236 clock-names = "apb_pclk";
237 };
238
239 gpio2: gpio@808000 {
240 compatible = "arm,pl061", "arm,primecell";
241 reg = <0x808000 0x1000>;
242 interrupts = <0 66 0x4>;
243 gpio-controller;
244 #gpio-cells = <2>;
245 gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
246 &pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
247 &pmx0 6 3 1 &pmx0 7 3 1>;
248 interrupt-controller;
249 #interrupt-cells = <2>;
250 clocks = <&clock HI3620_GPIOCLK2>;
251 clock-names = "apb_pclk";
252 };
253
254 gpio3: gpio@809000 {
255 compatible = "arm,pl061", "arm,primecell";
256 reg = <0x809000 0x1000>;
257 interrupts = <0 67 0x4>;
258 gpio-controller;
259 #gpio-cells = <2>;
260 gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
261 &pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
262 &pmx0 6 11 1 &pmx0 7 11 1>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
265 clocks = <&clock HI3620_GPIOCLK3>;
266 clock-names = "apb_pclk";
267 };
268
269 gpio4: gpio@80a000 {
270 compatible = "arm,pl061", "arm,primecell";
271 reg = <0x80a000 0x1000>;
272 interrupts = <0 68 0x4>;
273 gpio-controller;
274 #gpio-cells = <2>;
275 gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
276 &pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
277 &pmx0 6 13 1 &pmx0 7 13 1>;
278 interrupt-controller;
279 #interrupt-cells = <2>;
280 clocks = <&clock HI3620_GPIOCLK4>;
281 clock-names = "apb_pclk";
282 };
283
284 gpio5: gpio@80b000 {
285 compatible = "arm,pl061", "arm,primecell";
286 reg = <0x80b000 0x1000>;
287 interrupts = <0 69 0x4>;
288 gpio-controller;
289 #gpio-cells = <2>;
290 gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
291 &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
292 &pmx0 6 16 1 &pmx0 7 16 1>;
293 interrupt-controller;
294 #interrupt-cells = <2>;
295 clocks = <&clock HI3620_GPIOCLK5>;
296 clock-names = "apb_pclk";
297 };
298
299 gpio6: gpio@80c000 {
300 compatible = "arm,pl061", "arm,primecell";
301 reg = <0x80c000 0x1000>;
302 interrupts = <0 70 0x4>;
303 gpio-controller;
304 #gpio-cells = <2>;
305 gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
306 &pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
307 &pmx0 6 18 1 &pmx0 7 19 1>;
308 interrupt-controller;
309 #interrupt-cells = <2>;
310 clocks = <&clock HI3620_GPIOCLK6>;
311 clock-names = "apb_pclk";
312 };
313
314 gpio7: gpio@80d000 {
315 compatible = "arm,pl061", "arm,primecell";
316 reg = <0x80d000 0x1000>;
317 interrupts = <0 71 0x4>;
318 gpio-controller;
319 #gpio-cells = <2>;
320 gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
321 &pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
322 &pmx0 6 25 1 &pmx0 7 26 1>;
323 interrupt-controller;
324 #interrupt-cells = <2>;
325 clocks = <&clock HI3620_GPIOCLK7>;
326 clock-names = "apb_pclk";
327 };
328
329 gpio8: gpio@80e000 {
330 compatible = "arm,pl061", "arm,primecell";
331 reg = <0x80e000 0x1000>;
332 interrupts = <0 72 0x4>;
333 gpio-controller;
334 #gpio-cells = <2>;
335 gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
336 &pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
337 &pmx0 6 33 1 &pmx0 7 34 1>;
338 interrupt-controller;
339 #interrupt-cells = <2>;
340 clocks = <&clock HI3620_GPIOCLK8>;
341 clock-names = "apb_pclk";
342 };
343
344 gpio9: gpio@80f000 {
345 compatible = "arm,pl061", "arm,primecell";
346 reg = <0x80f000 0x1000>;
347 interrupts = <0 73 0x4>;
348 gpio-controller;
349 #gpio-cells = <2>;
350 gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
351 &pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
352 &pmx0 6 41 1>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
355 clocks = <&clock HI3620_GPIOCLK9>;
356 clock-names = "apb_pclk";
357 };
358
359 gpio10: gpio@810000 {
360 compatible = "arm,pl061", "arm,primecell";
361 reg = <0x810000 0x1000>;
362 interrupts = <0 74 0x4>;
363 gpio-controller;
364 #gpio-cells = <2>;
365 gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
366 &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
369 clocks = <&clock HI3620_GPIOCLK10>;
370 clock-names = "apb_pclk";
371 };
372
373 gpio11: gpio@811000 {
374 compatible = "arm,pl061", "arm,primecell";
375 reg = <0x811000 0x1000>;
376 interrupts = <0 75 0x4>;
377 gpio-controller;
378 #gpio-cells = <2>;
379 gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
380 &pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
381 &pmx0 6 49 1 &pmx0 7 49 1>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 clocks = <&clock HI3620_GPIOCLK11>;
385 clock-names = "apb_pclk";
386 };
387
388 gpio12: gpio@812000 {
389 compatible = "arm,pl061", "arm,primecell";
390 reg = <0x812000 0x1000>;
391 interrupts = <0 76 0x4>;
392 gpio-controller;
393 #gpio-cells = <2>;
394 gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
395 &pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
396 &pmx0 6 51 1 &pmx0 7 52 1>;
397 interrupt-controller;
398 #interrupt-cells = <2>;
399 clocks = <&clock HI3620_GPIOCLK12>;
400 clock-names = "apb_pclk";
401 };
402
403 gpio13: gpio@813000 {
404 compatible = "arm,pl061", "arm,primecell";
405 reg = <0x813000 0x1000>;
406 interrupts = <0 77 0x4>;
407 gpio-controller;
408 #gpio-cells = <2>;
409 gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
410 &pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
411 &pmx0 6 55 1 &pmx0 7 56 1>;
412 interrupt-controller;
413 #interrupt-cells = <2>;
414 clocks = <&clock HI3620_GPIOCLK13>;
415 clock-names = "apb_pclk";
416 };
417
418 gpio14: gpio@814000 {
419 compatible = "arm,pl061", "arm,primecell";
420 reg = <0x814000 0x1000>;
421 interrupts = <0 78 0x4>;
422 gpio-controller;
423 #gpio-cells = <2>;
424 gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
425 &pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
426 &pmx0 6 60 1 &pmx0 7 61 1>;
427 interrupt-controller;
428 #interrupt-cells = <2>;
429 clocks = <&clock HI3620_GPIOCLK14>;
430 clock-names = "apb_pclk";
431 };
432
433 gpio15: gpio@815000 {
434 compatible = "arm,pl061", "arm,primecell";
435 reg = <0x815000 0x1000>;
436 interrupts = <0 79 0x4>;
437 gpio-controller;
438 #gpio-cells = <2>;
439 gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
440 &pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
441 &pmx0 6 64 1 &pmx0 7 65 1>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
444 clocks = <&clock HI3620_GPIOCLK15>;
445 clock-names = "apb_pclk";
446 };
447
448 gpio16: gpio@816000 {
449 compatible = "arm,pl061", "arm,primecell";
450 reg = <0x816000 0x1000>;
451 interrupts = <0 80 0x4>;
452 gpio-controller;
453 #gpio-cells = <2>;
454 gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
455 &pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
456 &pmx0 6 72 1 &pmx0 7 73 1>;
457 interrupt-controller;
458 #interrupt-cells = <2>;
459 clocks = <&clock HI3620_GPIOCLK16>;
460 clock-names = "apb_pclk";
461 };
462
463 gpio17: gpio@817000 {
464 compatible = "arm,pl061", "arm,primecell";
465 reg = <0x817000 0x1000>;
466 interrupts = <0 81 0x4>;
467 gpio-controller;
468 #gpio-cells = <2>;
469 gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
470 &pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
471 &pmx0 6 80 1 &pmx0 7 81 1>;
472 interrupt-controller;
473 #interrupt-cells = <2>;
474 clocks = <&clock HI3620_GPIOCLK17>;
475 clock-names = "apb_pclk";
476 };
477
478 gpio18: gpio@818000 {
479 compatible = "arm,pl061", "arm,primecell";
480 reg = <0x818000 0x1000>;
481 interrupts = <0 82 0x4>;
482 gpio-controller;
483 #gpio-cells = <2>;
484 gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
485 &pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
486 &pmx0 6 86 1 &pmx0 7 87 1>;
487 interrupt-controller;
488 #interrupt-cells = <2>;
489 clocks = <&clock HI3620_GPIOCLK18>;
490 clock-names = "apb_pclk";
491 };
492
493 gpio19: gpio@819000 {
494 compatible = "arm,pl061", "arm,primecell";
495 reg = <0x819000 0x1000>;
496 interrupts = <0 83 0x4>;
497 gpio-controller;
498 #gpio-cells = <2>;
499 gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
500 &pmx0 3 88 1>;
501 interrupt-controller;
502 #interrupt-cells = <2>;
503 clocks = <&clock HI3620_GPIOCLK19>;
504 clock-names = "apb_pclk";
505 };
506
507 gpio20: gpio@81a000 {
508 compatible = "arm,pl061", "arm,primecell";
509 reg = <0x81a000 0x1000>;
510 interrupts = <0 84 0x4>;
511 gpio-controller;
512 #gpio-cells = <2>;
513 gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
514 &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
515 interrupt-controller;
516 #interrupt-cells = <2>;
517 clocks = <&clock HI3620_GPIOCLK20>;
518 clock-names = "apb_pclk";
519 };
520
521 gpio21: gpio@81b000 {
522 compatible = "arm,pl061", "arm,primecell";
523 reg = <0x81b000 0x1000>;
524 interrupts = <0 85 0x4>;
525 gpio-controller;
526 #gpio-cells = <2>;
527 gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
528 interrupt-controller;
529 #interrupt-cells = <2>;
530 clocks = <&clock HI3620_GPIOCLK21>;
531 clock-names = "apb_pclk";
532 };
533
534 pmx0: pinmux@803000 {
535 compatible = "pinctrl-single";
536 reg = <0x803000 0x188>;
537 #address-cells = <1>;
538 #size-cells = <1>;
539 #gpio-range-cells = <3>;
540 ranges;
541
542 pinctrl-single,register-width = <32>;
543 pinctrl-single,function-mask = <7>;
544 /* pin base, nr pins & gpio function */
545 pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
546 &range 12 1 0 &range 13 29 1
547 &range 43 1 0 &range 44 49 1
548 &range 94 1 1 &range 96 2 1>;
549
550 range: gpio-range {
551 #pinctrl-single,gpio-range-cells = <3>;
552 };
553 };
554
555 pmx1: pinmux@803800 {
556 compatible = "pinconf-single";
557 reg = <0x803800 0x2dc>;
558 #address-cells = <1>;
559 #size-cells = <1>;
560 ranges;
561
562 pinctrl-single,register-width = <32>;
563 };
564 };
565};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
new file mode 100644
index 000000000000..2ebb4f09a9b6
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -0,0 +1,33 @@
1/dts-v1/;
2
3#include "skeleton.dtsi"
4
5/ {
6 model = "Qualcomm MSM8974";
7 compatible = "qcom,msm8974";
8 interrupt-parent = <&intc>;
9
10 soc: soc {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges;
14 compatible = "simple-bus";
15
16 intc: interrupt-controller@f9000000 {
17 compatible = "qcom,msm-qgic2";
18 interrupt-controller;
19 #interrupt-cells = <3>;
20 reg = <0xf9000000 0x1000>,
21 <0xf9002000 0x1000>;
22 };
23
24 timer {
25 compatible = "arm,armv7-timer";
26 interrupts = <1 2 0xf08>,
27 <1 3 0xf08>,
28 <1 4 0xf08>,
29 <1 1 0xf08>;
30 clock-frequency = <19200000>;
31 };
32 };
33};
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c
index ce922d0ea7aa..53c6a26b633d 100644
--- a/arch/arm/common/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -66,7 +66,7 @@ static long __init sp804_get_clock_rate(struct clk *clk)
66 66
67static void __iomem *sched_clock_base; 67static void __iomem *sched_clock_base;
68 68
69static u32 sp804_read(void) 69static u64 notrace sp804_read(void)
70{ 70{
71 return ~readl_relaxed(sched_clock_base + TIMER_VALUE); 71 return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
72} 72}
@@ -104,7 +104,7 @@ void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
104 104
105 if (use_sched_clock) { 105 if (use_sched_clock) {
106 sched_clock_base = base; 106 sched_clock_base = base;
107 setup_sched_clock(sp804_read, 32, rate); 107 sched_clock_register(sp804_read, 32, rate);
108 } 108 }
109} 109}
110 110
diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig
index 1ce39940795d..cb26c62dc722 100644
--- a/arch/arm/configs/ape6evm_defconfig
+++ b/arch/arm/configs/ape6evm_defconfig
@@ -13,7 +13,7 @@ CONFIG_EMBEDDED=y
13CONFIG_PERF_EVENTS=y 13CONFIG_PERF_EVENTS=y
14CONFIG_SLAB=y 14CONFIG_SLAB=y
15# CONFIG_BLOCK is not set 15# CONFIG_BLOCK is not set
16CONFIG_ARCH_SHMOBILE=y 16CONFIG_ARCH_SHMOBILE_LEGACY=y
17CONFIG_ARCH_R8A73A4=y 17CONFIG_ARCH_R8A73A4=y
18CONFIG_MACH_APE6EVM=y 18CONFIG_MACH_APE6EVM=y
19# CONFIG_ARM_THUMB is not set 19# CONFIG_ARM_THUMB is not set
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index fae939d3d7f0..5abf1a2e3160 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -15,7 +15,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
15# CONFIG_BLK_DEV_BSG is not set 15# CONFIG_BLK_DEV_BSG is not set
16# CONFIG_IOSCHED_DEADLINE is not set 16# CONFIG_IOSCHED_DEADLINE is not set
17# CONFIG_IOSCHED_CFQ is not set 17# CONFIG_IOSCHED_CFQ is not set
18CONFIG_ARCH_SHMOBILE=y 18CONFIG_ARCH_SHMOBILE_LEGACY=y
19CONFIG_ARCH_R8A7740=y 19CONFIG_ARCH_R8A7740=y
20CONFIG_MACH_ARMADILLO800EVA=y 20CONFIG_MACH_ARMADILLO800EVA=y
21# CONFIG_SH_TIMER_TMU is not set 21# CONFIG_SH_TIMER_TMU is not set
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index bede51171d98..2c38fdf1951d 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -29,11 +29,9 @@ CONFIG_ARCH_BCM_MOBILE=y
29CONFIG_ARM_THUMBEE=y 29CONFIG_ARM_THUMBEE=y
30CONFIG_PREEMPT=y 30CONFIG_PREEMPT=y
31CONFIG_AEABI=y 31CONFIG_AEABI=y
32# CONFIG_OABI_COMPAT is not set
33# CONFIG_COMPACTION is not set 32# CONFIG_COMPACTION is not set
34CONFIG_ZBOOT_ROM_TEXT=0x0 33CONFIG_ZBOOT_ROM_TEXT=0x0
35CONFIG_ZBOOT_ROM_BSS=0x0 34CONFIG_ZBOOT_ROM_BSS=0x0
36CONFIG_ARM_APPENDED_DTB=y
37CONFIG_CMDLINE="console=ttyS0,115200n8 mem=128M" 35CONFIG_CMDLINE="console=ttyS0,115200n8 mem=128M"
38CONFIG_CPU_IDLE=y 36CONFIG_CPU_IDLE=y
39CONFIG_VFP=y 37CONFIG_VFP=y
@@ -120,6 +118,7 @@ CONFIG_DETECT_HUNG_TASK=y
120CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110 118CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110
121CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y 119CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
122# CONFIG_FTRACE is not set 120# CONFIG_FTRACE is not set
121# CONFIG_CRYPTO_ANSI_CPRNG is not set
123CONFIG_CRC_CCITT=y 122CONFIG_CRC_CCITT=y
124CONFIG_CRC_T10DIF=y 123CONFIG_CRC_T10DIF=y
125CONFIG_CRC_ITU_T=y 124CONFIG_CRC_ITU_T=y
diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig
index b38cd107f82d..1dd39716d7cb 100644
--- a/arch/arm/configs/bockw_defconfig
+++ b/arch/arm/configs/bockw_defconfig
@@ -8,7 +8,7 @@ CONFIG_SYSCTL_SYSCALL=y
8CONFIG_EMBEDDED=y 8CONFIG_EMBEDDED=y
9CONFIG_SLAB=y 9CONFIG_SLAB=y
10# CONFIG_IOSCHED_CFQ is not set 10# CONFIG_IOSCHED_CFQ is not set
11CONFIG_ARCH_SHMOBILE=y 11CONFIG_ARCH_SHMOBILE_LEGACY=y
12CONFIG_ARCH_R8A7778=y 12CONFIG_ARCH_R8A7778=y
13CONFIG_MACH_BOCKW=y 13CONFIG_MACH_BOCKW=y
14CONFIG_MEMORY_START=0x60000000 14CONFIG_MEMORY_START=0x60000000
diff --git a/arch/arm/configs/efm32_defconfig b/arch/arm/configs/efm32_defconfig
new file mode 100644
index 000000000000..f59fffb3d0c6
--- /dev/null
+++ b/arch/arm/configs/efm32_defconfig
@@ -0,0 +1,102 @@
1CONFIG_HIGH_RES_TIMERS=y
2CONFIG_LOG_BUF_SHIFT=12
3CONFIG_CC_OPTIMIZE_FOR_SIZE=y
4# CONFIG_UID16 is not set
5# CONFIG_BASE_FULL is not set
6# CONFIG_FUTEX is not set
7# CONFIG_EPOLL is not set
8# CONFIG_SIGNALFD is not set
9# CONFIG_EVENTFD is not set
10# CONFIG_AIO is not set
11CONFIG_EMBEDDED=y
12# CONFIG_VM_EVENT_COUNTERS is not set
13# CONFIG_SLUB_DEBUG is not set
14# CONFIG_LBDAF is not set
15# CONFIG_BLK_DEV_BSG is not set
16# CONFIG_IOSCHED_DEADLINE is not set
17# CONFIG_IOSCHED_CFQ is not set
18# CONFIG_MMU is not set
19CONFIG_ARCH_EFM32=y
20# CONFIG_KUSER_HELPERS is not set
21CONFIG_SET_MEM_PARAM=y
22CONFIG_DRAM_BASE=0x88000000
23CONFIG_DRAM_SIZE=0x00400000
24CONFIG_FLASH_MEM_BASE=0x8c000000
25CONFIG_FLASH_SIZE=0x01000000
26CONFIG_PREEMPT=y
27CONFIG_ZBOOT_ROM_TEXT=0x0
28CONFIG_ZBOOT_ROM_BSS=0x0
29CONFIG_XIP_KERNEL=y
30CONFIG_XIP_PHYS_ADDR=0x8c000000
31CONFIG_BINFMT_FLAT=y
32CONFIG_BINFMT_SHARED_FLAT=y
33# CONFIG_COREDUMP is not set
34CONFIG_NET=y
35CONFIG_PACKET=y
36CONFIG_UNIX=y
37CONFIG_INET=y
38# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
39# CONFIG_INET_XFRM_MODE_TUNNEL is not set
40# CONFIG_INET_XFRM_MODE_BEET is not set
41# CONFIG_INET_LRO is not set
42# CONFIG_INET_DIAG is not set
43# CONFIG_IPV6 is not set
44# CONFIG_WIRELESS is not set
45CONFIG_DEVTMPFS=y
46CONFIG_DEVTMPFS_MOUNT=y
47# CONFIG_FW_LOADER is not set
48CONFIG_MTD=y
49CONFIG_MTD_BLOCK_RO=y
50CONFIG_MTD_ROM=y
51CONFIG_MTD_UCLINUX=y
52CONFIG_PROC_DEVICETREE=y
53# CONFIG_BLK_DEV is not set
54CONFIG_NETDEVICES=y
55# CONFIG_NET_VENDOR_ARC is not set
56# CONFIG_NET_CADENCE is not set
57# CONFIG_NET_VENDOR_BROADCOM is not set
58# CONFIG_NET_VENDOR_CIRRUS is not set
59# CONFIG_NET_VENDOR_FARADAY is not set
60# CONFIG_NET_VENDOR_INTEL is not set
61# CONFIG_NET_VENDOR_MARVELL is not set
62CONFIG_KS8851=y
63# CONFIG_NET_VENDOR_MICROCHIP is not set
64# CONFIG_NET_VENDOR_NATSEMI is not set
65# CONFIG_NET_VENDOR_SEEQ is not set
66# CONFIG_NET_VENDOR_SMSC is not set
67# CONFIG_NET_VENDOR_STMICRO is not set
68# CONFIG_NET_VENDOR_VIA is not set
69# CONFIG_NET_VENDOR_WIZNET is not set
70# CONFIG_WLAN is not set
71# CONFIG_INPUT is not set
72# CONFIG_SERIO is not set
73# CONFIG_VT is not set
74# CONFIG_UNIX98_PTYS is not set
75# CONFIG_LEGACY_PTYS is not set
76CONFIG_SERIAL_NONSTANDARD=y
77# CONFIG_DEVKMEM is not set
78CONFIG_SERIAL_EFM32_UART=y
79CONFIG_SERIAL_EFM32_UART_CONSOLE=y
80# CONFIG_HW_RANDOM is not set
81CONFIG_SPI=y
82CONFIG_SPI_EFM32=y
83CONFIG_GPIO_SYSFS=y
84# CONFIG_USB_SUPPORT is not set
85CONFIG_MMC=y
86CONFIG_MMC_SPI=y
87# CONFIG_IOMMU_SUPPORT is not set
88CONFIG_EXT2_FS=y
89# CONFIG_FILE_LOCKING is not set
90# CONFIG_DNOTIFY is not set
91# CONFIG_INOTIFY_USER is not set
92CONFIG_ROMFS_FS=y
93CONFIG_ROMFS_BACKED_BY_MTD=y
94# CONFIG_NETWORK_FILESYSTEMS is not set
95CONFIG_PRINTK_TIME=y
96CONFIG_DEBUG_INFO=y
97# CONFIG_ENABLE_WARN_DEPRECATED is not set
98# CONFIG_ENABLE_MUST_CHECK is not set
99CONFIG_MAGIC_SYSRQ=y
100# CONFIG_SCHED_DEBUG is not set
101# CONFIG_DEBUG_BUGVERBOSE is not set
102# CONFIG_FTRACE is not set
diff --git a/arch/arm/configs/hi3xxx_defconfig b/arch/arm/configs/hi3xxx_defconfig
new file mode 100644
index 000000000000..f186bdfa2369
--- /dev/null
+++ b/arch/arm/configs/hi3xxx_defconfig
@@ -0,0 +1,56 @@
1CONFIG_IRQ_DOMAIN_DEBUG=y
2CONFIG_NO_HZ=y
3CONFIG_HIGH_RES_TIMERS=y
4CONFIG_BLK_DEV_INITRD=y
5CONFIG_RD_LZMA=y
6CONFIG_ARCH_HI3xxx=y
7CONFIG_SMP=y
8CONFIG_PREEMPT=y
9CONFIG_AEABI=y
10CONFIG_ARM_APPENDED_DTB=y
11CONFIG_NET=y
12CONFIG_UNIX=y
13CONFIG_INET=y
14CONFIG_IP_PNP=y
15CONFIG_IP_PNP_DHCP=y
16CONFIG_DEVTMPFS=y
17CONFIG_DEVTMPFS_MOUNT=y
18CONFIG_BLK_DEV_SD=y
19CONFIG_ATA=y
20CONFIG_SATA_AHCI_PLATFORM=y
21CONFIG_NETDEVICES=y
22CONFIG_SERIAL_AMBA_PL011=y
23CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
24CONFIG_SERIAL_OF_PLATFORM=y
25CONFIG_I2C_DESIGNWARE_PLATFORM=y
26CONFIG_SPI=y
27CONFIG_SPI_PL022=y
28CONFIG_PINCTRL_SINGLE=y
29CONFIG_GPIO_GENERIC_PLATFORM=y
30CONFIG_REGULATOR_GPIO=y
31CONFIG_DRM=y
32CONFIG_FB_SIMPLE=y
33CONFIG_USB=y
34CONFIG_USB_XHCI_HCD=y
35CONFIG_USB_EHCI_HCD=y
36CONFIG_USB_EHCI_MXC=y
37CONFIG_USB_EHCI_HCD_PLATFORM=y
38CONFIG_USB_STORAGE=y
39CONFIG_NOP_USB_XCEIV=y
40CONFIG_MMC=y
41CONFIG_RTC_CLASS=y
42CONFIG_RTC_DRV_PL031=y
43CONFIG_DMADEVICES=y
44CONFIG_DW_DMAC=y
45CONFIG_PL330_DMA=y
46CONFIG_PWM=y
47CONFIG_EXT4_FS=y
48CONFIG_TMPFS=y
49CONFIG_NFS_FS=y
50CONFIG_NFS_V3_ACL=y
51CONFIG_NFS_V4=y
52CONFIG_ROOT_NFS=y
53CONFIG_PRINTK_TIME=y
54CONFIG_DEBUG_FS=y
55CONFIG_DEBUG_KERNEL=y
56CONFIG_LOCKUP_DETECTOR=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index e958ebe79779..6309ee52ccfc 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -91,6 +91,7 @@ CONFIG_SMSC911X=y
91CONFIG_SMSC_PHY=y 91CONFIG_SMSC_PHY=y
92# CONFIG_INPUT_MOUSEDEV is not set 92# CONFIG_INPUT_MOUSEDEV is not set
93CONFIG_INPUT_EVDEV=y 93CONFIG_INPUT_EVDEV=y
94CONFIG_KEYBOARD_GPIO=y
94CONFIG_KEYBOARD_IMX=y 95CONFIG_KEYBOARD_IMX=y
95# CONFIG_INPUT_MOUSE is not set 96# CONFIG_INPUT_MOUSE is not set
96CONFIG_INPUT_TOUCHSCREEN=y 97CONFIG_INPUT_TOUCHSCREEN=y
@@ -118,6 +119,7 @@ CONFIG_IMX2_WDT=y
118CONFIG_MFD_MC13XXX_SPI=y 119CONFIG_MFD_MC13XXX_SPI=y
119CONFIG_REGULATOR=y 120CONFIG_REGULATOR=y
120CONFIG_REGULATOR_FIXED_VOLTAGE=y 121CONFIG_REGULATOR_FIXED_VOLTAGE=y
122CONFIG_REGULATOR_GPIO=y
121CONFIG_REGULATOR_MC13783=y 123CONFIG_REGULATOR_MC13783=y
122CONFIG_REGULATOR_MC13892=y 124CONFIG_REGULATOR_MC13892=y
123CONFIG_MEDIA_SUPPORT=y 125CONFIG_MEDIA_SUPPORT=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 8d0c5a018ed7..53e82c2523eb 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -28,11 +28,13 @@ CONFIG_MACH_QONG=y
28CONFIG_MACH_ARMADILLO5X0=y 28CONFIG_MACH_ARMADILLO5X0=y
29CONFIG_MACH_KZM_ARM11_01=y 29CONFIG_MACH_KZM_ARM11_01=y
30CONFIG_MACH_IMX31_DT=y 30CONFIG_MACH_IMX31_DT=y
31CONFIG_MACH_IMX35_DT=y
31CONFIG_MACH_PCM043=y 32CONFIG_MACH_PCM043=y
32CONFIG_MACH_MX35_3DS=y 33CONFIG_MACH_MX35_3DS=y
33CONFIG_MACH_VPR200=y 34CONFIG_MACH_VPR200=y
34CONFIG_MACH_IMX51_DT=y 35CONFIG_MACH_IMX51_DT=y
35CONFIG_MACH_EUKREA_CPUIMX51SD=y 36CONFIG_MACH_EUKREA_CPUIMX51SD=y
37CONFIG_SOC_IMX50=y
36CONFIG_SOC_IMX53=y 38CONFIG_SOC_IMX53=y
37CONFIG_SOC_IMX6Q=y 39CONFIG_SOC_IMX6Q=y
38CONFIG_SOC_IMX6SL=y 40CONFIG_SOC_IMX6SL=y
@@ -41,7 +43,7 @@ CONFIG_SMP=y
41CONFIG_VMSPLIT_2G=y 43CONFIG_VMSPLIT_2G=y
42CONFIG_PREEMPT_VOLUNTARY=y 44CONFIG_PREEMPT_VOLUNTARY=y
43CONFIG_AEABI=y 45CONFIG_AEABI=y
44# CONFIG_OABI_COMPAT is not set 46CONFIG_HIGHMEM=y
45CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" 47CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
46CONFIG_VFP=y 48CONFIG_VFP=y
47CONFIG_NEON=y 49CONFIG_NEON=y
@@ -89,7 +91,6 @@ CONFIG_MTD_UBI=y
89CONFIG_BLK_DEV_LOOP=y 91CONFIG_BLK_DEV_LOOP=y
90CONFIG_BLK_DEV_RAM=y 92CONFIG_BLK_DEV_RAM=y
91CONFIG_BLK_DEV_RAM_SIZE=65536 93CONFIG_BLK_DEV_RAM_SIZE=65536
92CONFIG_SRAM=y
93CONFIG_EEPROM_AT24=y 94CONFIG_EEPROM_AT24=y
94CONFIG_EEPROM_AT25=y 95CONFIG_EEPROM_AT25=y
95# CONFIG_SCSI_PROC_FS is not set 96# CONFIG_SCSI_PROC_FS is not set
@@ -118,6 +119,7 @@ CONFIG_SMC91X=y
118CONFIG_SMC911X=y 119CONFIG_SMC911X=y
119CONFIG_SMSC911X=y 120CONFIG_SMSC911X=y
120# CONFIG_NET_VENDOR_STMICRO is not set 121# CONFIG_NET_VENDOR_STMICRO is not set
122CONFIG_AT803X_PHY=y
121CONFIG_BRCMFMAC=m 123CONFIG_BRCMFMAC=m
122# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 124# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
123CONFIG_INPUT_EVDEV=y 125CONFIG_INPUT_EVDEV=y
@@ -129,6 +131,8 @@ CONFIG_MOUSE_PS2_ELANTECH=y
129CONFIG_INPUT_TOUCHSCREEN=y 131CONFIG_INPUT_TOUCHSCREEN=y
130CONFIG_TOUCHSCREEN_EGALAX=y 132CONFIG_TOUCHSCREEN_EGALAX=y
131CONFIG_TOUCHSCREEN_MC13783=y 133CONFIG_TOUCHSCREEN_MC13783=y
134CONFIG_TOUCHSCREEN_TSC2007=y
135CONFIG_TOUCHSCREEN_STMPE=y
132CONFIG_INPUT_MISC=y 136CONFIG_INPUT_MISC=y
133CONFIG_INPUT_MMA8450=y 137CONFIG_INPUT_MMA8450=y
134CONFIG_SERIO_SERPORT=m 138CONFIG_SERIO_SERPORT=m
@@ -156,14 +160,19 @@ CONFIG_IMX2_WDT=y
156CONFIG_MFD_DA9052_I2C=y 160CONFIG_MFD_DA9052_I2C=y
157CONFIG_MFD_MC13XXX_SPI=y 161CONFIG_MFD_MC13XXX_SPI=y
158CONFIG_MFD_MC13XXX_I2C=y 162CONFIG_MFD_MC13XXX_I2C=y
163CONFIG_MFD_STMPE=y
159CONFIG_REGULATOR=y 164CONFIG_REGULATOR=y
160CONFIG_REGULATOR_FIXED_VOLTAGE=y 165CONFIG_REGULATOR_FIXED_VOLTAGE=y
161CONFIG_REGULATOR_ANATOP=y 166CONFIG_REGULATOR_ANATOP=y
162CONFIG_REGULATOR_DA9052=y 167CONFIG_REGULATOR_DA9052=y
163CONFIG_REGULATOR_MC13783=y 168CONFIG_REGULATOR_MC13783=y
164CONFIG_REGULATOR_MC13892=y 169CONFIG_REGULATOR_MC13892=y
170CONFIG_REGULATOR_PFUZE100=y
165CONFIG_MEDIA_SUPPORT=y 171CONFIG_MEDIA_SUPPORT=y
166CONFIG_MEDIA_CAMERA_SUPPORT=y 172CONFIG_MEDIA_CAMERA_SUPPORT=y
173CONFIG_MEDIA_RC_SUPPORT=y
174CONFIG_RC_DEVICES=y
175CONFIG_IR_GPIO_CIR=y
167CONFIG_V4L_PLATFORM_DRIVERS=y 176CONFIG_V4L_PLATFORM_DRIVERS=y
168CONFIG_SOC_CAMERA=y 177CONFIG_SOC_CAMERA=y
169CONFIG_VIDEO_MX3=y 178CONFIG_VIDEO_MX3=y
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index 9943e5da74f1..a0182447d133 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -115,6 +115,8 @@ CONFIG_MTD_UBI=y
115CONFIG_PROC_DEVICETREE=y 115CONFIG_PROC_DEVICETREE=y
116CONFIG_BLK_DEV_LOOP=y 116CONFIG_BLK_DEV_LOOP=y
117CONFIG_EEPROM_AT24=y 117CONFIG_EEPROM_AT24=y
118CONFIG_SCSI=y
119CONFIG_BLK_DEV_SD=y
118CONFIG_NETDEVICES=y 120CONFIG_NETDEVICES=y
119CONFIG_SERIAL_8250=y 121CONFIG_SERIAL_8250=y
120CONFIG_SERIAL_8250_CONSOLE=y 122CONFIG_SERIAL_8250_CONSOLE=y
@@ -129,10 +131,24 @@ CONFIG_SPI_DAVINCI=y
129CONFIG_SPI_SPIDEV=y 131CONFIG_SPI_SPIDEV=y
130# CONFIG_HWMON is not set 132# CONFIG_HWMON is not set
131CONFIG_WATCHDOG=y 133CONFIG_WATCHDOG=y
132# CONFIG_USB_SUPPORT is not set 134CONFIG_USB=y
135CONFIG_USB_DEBUG=y
136CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
137CONFIG_USB_MON=y
138CONFIG_USB_XHCI_HCD=y
139CONFIG_USB_STORAGE=y
140CONFIG_USB_DWC3=y
141CONFIG_USB_DWC3_DEBUG=y
142CONFIG_USB_DWC3_VERBOSE=y
143CONFIG_KEYSTONE_USB_PHY=y
133CONFIG_DMADEVICES=y 144CONFIG_DMADEVICES=y
134CONFIG_COMMON_CLK_DEBUG=y 145CONFIG_COMMON_CLK_DEBUG=y
135CONFIG_MEMORY=y 146CONFIG_MEMORY=y
147CONFIG_EXT4_FS=y
148CONFIG_EXT4_FS_POSIX_ACL=y
149CONFIG_MSDOS_FS=y
150CONFIG_VFAT_FS=y
151CONFIG_NTFS_FS=y
136CONFIG_TMPFS=y 152CONFIG_TMPFS=y
137CONFIG_JFFS2_FS=y 153CONFIG_JFFS2_FS=y
138CONFIG_JFFS2_FS_WBUF_VERIFY=y 154CONFIG_JFFS2_FS_WBUF_VERIFY=y
@@ -144,6 +160,8 @@ CONFIG_ROOT_NFS=y
144CONFIG_NFSD=y 160CONFIG_NFSD=y
145CONFIG_NFSD_V3=y 161CONFIG_NFSD_V3=y
146CONFIG_NFSD_V3_ACL=y 162CONFIG_NFSD_V3_ACL=y
163CONFIG_NLS_CODEPAGE_437=y
164CONFIG_NLS_ISO8859_1=y
147CONFIG_PRINTK_TIME=y 165CONFIG_PRINTK_TIME=y
148CONFIG_DEBUG_SHIRQ=y 166CONFIG_DEBUG_SHIRQ=y
149CONFIG_DEBUG_INFO=y 167CONFIG_DEBUG_INFO=y
diff --git a/arch/arm/configs/koelsch_defconfig b/arch/arm/configs/koelsch_defconfig
index 825c16dee8a0..7fd65a01ec7e 100644
--- a/arch/arm/configs/koelsch_defconfig
+++ b/arch/arm/configs/koelsch_defconfig
@@ -9,7 +9,7 @@ CONFIG_EMBEDDED=y
9CONFIG_PERF_EVENTS=y 9CONFIG_PERF_EVENTS=y
10CONFIG_SLAB=y 10CONFIG_SLAB=y
11# CONFIG_BLOCK is not set 11# CONFIG_BLOCK is not set
12CONFIG_ARCH_SHMOBILE=y 12CONFIG_ARCH_SHMOBILE_LEGACY=y
13CONFIG_ARCH_R8A7791=y 13CONFIG_ARCH_R8A7791=y
14CONFIG_MACH_KOELSCH=y 14CONFIG_MACH_KOELSCH=y
15# CONFIG_SWP_EMULATE is not set 15# CONFIG_SWP_EMULATE is not set
diff --git a/arch/arm/configs/kzm9d_defconfig b/arch/arm/configs/kzm9d_defconfig
index 6c37f4a98eb8..217f1dda2965 100644
--- a/arch/arm/configs/kzm9d_defconfig
+++ b/arch/arm/configs/kzm9d_defconfig
@@ -13,7 +13,7 @@ CONFIG_SLAB=y
13# CONFIG_BLK_DEV_BSG is not set 13# CONFIG_BLK_DEV_BSG is not set
14# CONFIG_IOSCHED_DEADLINE is not set 14# CONFIG_IOSCHED_DEADLINE is not set
15# CONFIG_IOSCHED_CFQ is not set 15# CONFIG_IOSCHED_CFQ is not set
16CONFIG_ARCH_SHMOBILE=y 16CONFIG_ARCH_SHMOBILE_LEGACY=y
17CONFIG_ARCH_EMEV2=y 17CONFIG_ARCH_EMEV2=y
18CONFIG_MACH_KZM9D=y 18CONFIG_MACH_KZM9D=y
19CONFIG_MEMORY_START=0x40000000 19CONFIG_MEMORY_START=0x40000000
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index 1ad028023a64..9934dbc23d64 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -22,7 +22,7 @@ CONFIG_MODULE_UNLOAD=y
22# CONFIG_BLK_DEV_BSG is not set 22# CONFIG_BLK_DEV_BSG is not set
23# CONFIG_IOSCHED_DEADLINE is not set 23# CONFIG_IOSCHED_DEADLINE is not set
24# CONFIG_IOSCHED_CFQ is not set 24# CONFIG_IOSCHED_CFQ is not set
25CONFIG_ARCH_SHMOBILE=y 25CONFIG_ARCH_SHMOBILE_LEGACY=y
26CONFIG_ARCH_SH73A0=y 26CONFIG_ARCH_SH73A0=y
27CONFIG_MACH_KZM9G=y 27CONFIG_MACH_KZM9G=y
28CONFIG_MEMORY_START=0x41000000 28CONFIG_MEMORY_START=0x41000000
diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig
index 35bff5e0d57a..35dc8b2be47f 100644
--- a/arch/arm/configs/lager_defconfig
+++ b/arch/arm/configs/lager_defconfig
@@ -12,7 +12,7 @@ CONFIG_SLAB=y
12# CONFIG_BLK_DEV_BSG is not set 12# CONFIG_BLK_DEV_BSG is not set
13# CONFIG_IOSCHED_DEADLINE is not set 13# CONFIG_IOSCHED_DEADLINE is not set
14# CONFIG_IOSCHED_CFQ is not set 14# CONFIG_IOSCHED_CFQ is not set
15CONFIG_ARCH_SHMOBILE=y 15CONFIG_ARCH_SHMOBILE_LEGACY=y
16CONFIG_ARCH_R8A7790=y 16CONFIG_ARCH_R8A7790=y
17CONFIG_MACH_LAGER=y 17CONFIG_MACH_LAGER=y
18# CONFIG_SH_TIMER_TMU is not set 18# CONFIG_SH_TIMER_TMU is not set
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
index 9fb11895b2e2..a61e1653fc5e 100644
--- a/arch/arm/configs/mackerel_defconfig
+++ b/arch/arm/configs/mackerel_defconfig
@@ -14,7 +14,7 @@ CONFIG_MODULE_UNLOAD=y
14# CONFIG_BLK_DEV_BSG is not set 14# CONFIG_BLK_DEV_BSG is not set
15# CONFIG_IOSCHED_DEADLINE is not set 15# CONFIG_IOSCHED_DEADLINE is not set
16# CONFIG_IOSCHED_CFQ is not set 16# CONFIG_IOSCHED_CFQ is not set
17CONFIG_ARCH_SHMOBILE=y 17CONFIG_ARCH_SHMOBILE_LEGACY=y
18CONFIG_ARCH_SH7372=y 18CONFIG_ARCH_SH7372=y
19CONFIG_MACH_MACKEREL=y 19CONFIG_MACH_MACKEREL=y
20CONFIG_MEMORY_SIZE=0x10000000 20CONFIG_MEMORY_SIZE=0x10000000
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 5cc6360340b1..6981338cd08d 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -9,7 +9,7 @@ CONFIG_SYSCTL_SYSCALL=y
9CONFIG_EMBEDDED=y 9CONFIG_EMBEDDED=y
10CONFIG_SLAB=y 10CONFIG_SLAB=y
11# CONFIG_IOSCHED_CFQ is not set 11# CONFIG_IOSCHED_CFQ is not set
12CONFIG_ARCH_SHMOBILE=y 12CONFIG_ARCH_SHMOBILE_LEGACY=y
13CONFIG_ARCH_R8A7779=y 13CONFIG_ARCH_R8A7779=y
14CONFIG_MACH_MARZEN=y 14CONFIG_MACH_MARZEN=y
15CONFIG_MEMORY_START=0x60000000 15CONFIG_MEMORY_START=0x60000000
diff --git a/arch/arm/configs/moxart_defconfig b/arch/arm/configs/moxart_defconfig
new file mode 100644
index 000000000000..a3cb76cfb828
--- /dev/null
+++ b/arch/arm/configs/moxart_defconfig
@@ -0,0 +1,149 @@
1# CONFIG_LOCALVERSION_AUTO is not set
2# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y
4CONFIG_NO_HZ=y
5CONFIG_IKCONFIG=y
6CONFIG_IKCONFIG_PROC=y
7CONFIG_SYSCTL_SYSCALL=y
8# CONFIG_ELF_CORE is not set
9# CONFIG_BASE_FULL is not set
10# CONFIG_SIGNALFD is not set
11# CONFIG_TIMERFD is not set
12# CONFIG_EVENTFD is not set
13# CONFIG_AIO is not set
14CONFIG_EMBEDDED=y
15# CONFIG_VM_EVENT_COUNTERS is not set
16# CONFIG_SLUB_DEBUG is not set
17# CONFIG_COMPAT_BRK is not set
18# CONFIG_LBDAF is not set
19# CONFIG_BLK_DEV_BSG is not set
20# CONFIG_IOSCHED_DEADLINE is not set
21CONFIG_ARCH_MULTI_V4T=y
22# CONFIG_ARCH_MULTI_V7 is not set
23CONFIG_KEYBOARD_GPIO_POLLED=y
24CONFIG_ARCH_MOXART=y
25CONFIG_MACH_UC7112LX=y
26CONFIG_PREEMPT=y
27CONFIG_AEABI=y
28# CONFIG_ATAGS is not set
29CONFIG_ARM_APPENDED_DTB=y
30CONFIG_NET=y
31CONFIG_PACKET=y
32CONFIG_UNIX=y
33CONFIG_INET=y
34CONFIG_IP_MULTICAST=y
35CONFIG_IP_PNP=y
36CONFIG_IP_PNP_DHCP=y
37# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
38# CONFIG_INET_XFRM_MODE_TUNNEL is not set
39# CONFIG_INET_XFRM_MODE_BEET is not set
40# CONFIG_INET_LRO is not set
41# CONFIG_INET_DIAG is not set
42# CONFIG_IPV6 is not set
43# CONFIG_WIRELESS is not set
44CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
45CONFIG_DEVTMPFS=y
46CONFIG_DEVTMPFS_MOUNT=y
47# CONFIG_PREVENT_FIRMWARE_BUILD is not set
48# CONFIG_FW_LOADER is not set
49CONFIG_MTD=y
50CONFIG_MTD_BLOCK=y
51CONFIG_MTD_CFI=y
52CONFIG_MTD_CFI_ADV_OPTIONS=y
53CONFIG_MTD_CFI_GEOMETRY=y
54CONFIG_MTD_CFI_INTELEXT=y
55CONFIG_MTD_COMPLEX_MAPPINGS=y
56CONFIG_MTD_PHYSMAP=y
57CONFIG_MTD_PHYSMAP_OF=y
58CONFIG_PROC_DEVICETREE=y
59CONFIG_NETDEVICES=y
60CONFIG_NETCONSOLE=y
61CONFIG_NETCONSOLE_DYNAMIC=y
62# CONFIG_NET_VENDOR_ARC is not set
63# CONFIG_NET_CADENCE is not set
64# CONFIG_NET_VENDOR_BROADCOM is not set
65# CONFIG_NET_VENDOR_CIRRUS is not set
66# CONFIG_NET_VENDOR_FARADAY is not set
67# CONFIG_NET_VENDOR_INTEL is not set
68# CONFIG_NET_VENDOR_MARVELL is not set
69# CONFIG_NET_VENDOR_MICREL is not set
70CONFIG_ARM_MOXART_ETHER=y
71# CONFIG_NET_VENDOR_NATSEMI is not set
72# CONFIG_NET_VENDOR_SEEQ is not set
73# CONFIG_NET_VENDOR_SMSC is not set
74# CONFIG_NET_VENDOR_STMICRO is not set
75# CONFIG_NET_VENDOR_VIA is not set
76# CONFIG_NET_VENDOR_WIZNET is not set
77CONFIG_REALTEK_PHY=y
78CONFIG_MDIO_MOXART=y
79# CONFIG_WLAN is not set
80# CONFIG_INPUT_MOUSEDEV is not set
81CONFIG_INPUT_EVDEV=y
82CONFIG_INPUT_EVBUG=y
83# CONFIG_KEYBOARD_ATKBD is not set
84# CONFIG_INPUT_MOUSE is not set
85# CONFIG_SERIO is not set
86# CONFIG_VT is not set
87# CONFIG_LEGACY_PTYS is not set
88# CONFIG_DEVKMEM is not set
89CONFIG_SERIAL_8250=y
90CONFIG_SERIAL_8250_CONSOLE=y
91CONFIG_SERIAL_8250_NR_UARTS=1
92CONFIG_SERIAL_8250_RUNTIME_UARTS=1
93CONFIG_SERIAL_8250_EXTENDED=y
94CONFIG_SERIAL_8250_SHARE_IRQ=y
95CONFIG_SERIAL_OF_PLATFORM=y
96# CONFIG_HW_RANDOM is not set
97CONFIG_DEBUG_GPIO=y
98CONFIG_GPIO_SYSFS=y
99CONFIG_GPIO_MOXART=y
100CONFIG_POWER_SUPPLY=y
101CONFIG_POWER_RESET=y
102CONFIG_POWER_RESET_GPIO=y
103# CONFIG_HWMON is not set
104CONFIG_WATCHDOG=y
105CONFIG_WATCHDOG_CORE=y
106CONFIG_WATCHDOG_NOWAYOUT=y
107CONFIG_MOXART_WDT=y
108# CONFIG_USB_SUPPORT is not set
109CONFIG_MMC=y
110CONFIG_MMC_SDHCI_MOXART=y
111CONFIG_NEW_LEDS=y
112CONFIG_LEDS_CLASS=y
113CONFIG_LEDS_GPIO=y
114CONFIG_LEDS_TRIGGER_TIMER=y
115CONFIG_LEDS_TRIGGER_ONESHOT=y
116CONFIG_LEDS_TRIGGER_HEARTBEAT=y
117CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
118CONFIG_RTC_CLASS=y
119CONFIG_RTC_DRV_MOXART=y
120CONFIG_DMADEVICES=y
121CONFIG_MOXART_DMA=y
122# CONFIG_IOMMU_SUPPORT is not set
123CONFIG_EXT3_FS=y
124CONFIG_TMPFS=y
125CONFIG_CONFIGFS_FS=y
126CONFIG_JFFS2_FS=y
127CONFIG_PRINTK_TIME=y
128CONFIG_DEBUG_INFO=y
129# CONFIG_ENABLE_WARN_DEPRECATED is not set
130# CONFIG_ENABLE_MUST_CHECK is not set
131CONFIG_DEBUG_PAGEALLOC=y
132CONFIG_DEBUG_OBJECTS=y
133CONFIG_DEBUG_KMEMLEAK=y
134CONFIG_DEBUG_STACK_USAGE=y
135CONFIG_DEBUG_MEMORY_INIT=y
136CONFIG_DEBUG_SHIRQ=y
137CONFIG_DETECT_HUNG_TASK=y
138# CONFIG_SCHED_DEBUG is not set
139# CONFIG_DEBUG_PREEMPT is not set
140CONFIG_PROVE_LOCKING=y
141CONFIG_DMA_API_DEBUG=y
142CONFIG_KGDB=y
143CONFIG_DEBUG_LL=y
144CONFIG_DEBUG_LL_UART_8250=y
145CONFIG_DEBUG_UART_PHYS=0x98200000
146CONFIG_DEBUG_UART_VIRT=0xf9820000
147CONFIG_EARLY_PRINTK=y
148CONFIG_KEYS=y
149CONFIG_CRC32_BIT=y
diff --git a/arch/arm/configs/msm_defconfig b/arch/arm/configs/msm_defconfig
index 690b5f9c7462..b2671e5c8bd3 100644
--- a/arch/arm/configs/msm_defconfig
+++ b/arch/arm/configs/msm_defconfig
@@ -17,7 +17,7 @@ CONFIG_MODULE_UNLOAD=y
17CONFIG_MODULE_FORCE_UNLOAD=y 17CONFIG_MODULE_FORCE_UNLOAD=y
18CONFIG_MODVERSIONS=y 18CONFIG_MODVERSIONS=y
19CONFIG_PARTITION_ADVANCED=y 19CONFIG_PARTITION_ADVANCED=y
20CONFIG_ARCH_MSM=y 20CONFIG_ARCH_MSM_DT=y
21CONFIG_ARCH_MSM8X60=y 21CONFIG_ARCH_MSM8X60=y
22CONFIG_ARCH_MSM8960=y 22CONFIG_ARCH_MSM8960=y
23CONFIG_SMP=y 23CONFIG_SMP=y
@@ -29,7 +29,6 @@ CONFIG_CLEANCACHE=y
29CONFIG_CC_STACKPROTECTOR=y 29CONFIG_CC_STACKPROTECTOR=y
30CONFIG_ARM_APPENDED_DTB=y 30CONFIG_ARM_APPENDED_DTB=y
31CONFIG_ARM_ATAG_DTB_COMPAT=y 31CONFIG_ARM_ATAG_DTB_COMPAT=y
32CONFIG_AUTO_ZRELADDR=y
33CONFIG_VFP=y 32CONFIG_VFP=y
34CONFIG_NEON=y 33CONFIG_NEON=y
35# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 34# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
@@ -62,7 +61,6 @@ CONFIG_SCSI_LOGGING=y
62CONFIG_SCSI_SCAN_ASYNC=y 61CONFIG_SCSI_SCAN_ASYNC=y
63CONFIG_NETDEVICES=y 62CONFIG_NETDEVICES=y
64CONFIG_DUMMY=y 63CONFIG_DUMMY=y
65CONFIG_PHYLIB=y
66CONFIG_SLIP=y 64CONFIG_SLIP=y
67CONFIG_SLIP_COMPRESSED=y 65CONFIG_SLIP_COMPRESSED=y
68CONFIG_SLIP_MODE_SLIP6=y 66CONFIG_SLIP_MODE_SLIP6=y
@@ -81,10 +79,10 @@ CONFIG_SERIO_LIBPS2=y
81CONFIG_SERIAL_MSM=y 79CONFIG_SERIAL_MSM=y
82CONFIG_SERIAL_MSM_CONSOLE=y 80CONFIG_SERIAL_MSM_CONSOLE=y
83CONFIG_HW_RANDOM=y 81CONFIG_HW_RANDOM=y
82CONFIG_HW_RANDOM_MSM=y
84CONFIG_I2C=y 83CONFIG_I2C=y
85CONFIG_I2C_CHARDEV=y 84CONFIG_I2C_CHARDEV=y
86CONFIG_SPI=y 85CONFIG_SPI=y
87CONFIG_SSBI=y
88CONFIG_DEBUG_GPIO=y 86CONFIG_DEBUG_GPIO=y
89CONFIG_GPIO_SYSFS=y 87CONFIG_GPIO_SYSFS=y
90CONFIG_POWER_SUPPLY=y 88CONFIG_POWER_SUPPLY=y
@@ -101,7 +99,6 @@ CONFIG_SND_DYNAMIC_MINORS=y
101CONFIG_SND_SOC=y 99CONFIG_SND_SOC=y
102CONFIG_HID_BATTERY_STRENGTH=y 100CONFIG_HID_BATTERY_STRENGTH=y
103CONFIG_USB=y 101CONFIG_USB=y
104CONFIG_USB_PHY=y
105CONFIG_USB_ANNOUNCE_NEW_DEVICES=y 102CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
106CONFIG_USB_MON=y 103CONFIG_USB_MON=y
107CONFIG_USB_EHCI_HCD=y 104CONFIG_USB_EHCI_HCD=y
@@ -128,10 +125,10 @@ CONFIG_NFS_V3_ACL=y
128CONFIG_NFS_V4=y 125CONFIG_NFS_V4=y
129CONFIG_CIFS=y 126CONFIG_CIFS=y
130CONFIG_PRINTK_TIME=y 127CONFIG_PRINTK_TIME=y
128CONFIG_DYNAMIC_DEBUG=y
129CONFIG_DEBUG_INFO=y
131CONFIG_MAGIC_SYSRQ=y 130CONFIG_MAGIC_SYSRQ=y
132CONFIG_LOCKUP_DETECTOR=y 131CONFIG_LOCKUP_DETECTOR=y
133# CONFIG_DETECT_HUNG_TASK is not set 132# CONFIG_DETECT_HUNG_TASK is not set
134# CONFIG_SCHED_DEBUG is not set 133# CONFIG_SCHED_DEBUG is not set
135CONFIG_TIMER_STATS=y 134CONFIG_TIMER_STATS=y
136CONFIG_DEBUG_INFO=y
137CONFIG_DYNAMIC_DEBUG=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index c1df4e9db140..0ae6dc35209f 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -7,8 +7,12 @@ CONFIG_MACH_ARMADA_370=y
7CONFIG_MACH_ARMADA_XP=y 7CONFIG_MACH_ARMADA_XP=y
8CONFIG_ARCH_BCM=y 8CONFIG_ARCH_BCM=y
9CONFIG_ARCH_BCM_MOBILE=y 9CONFIG_ARCH_BCM_MOBILE=y
10CONFIG_ARCH_BERLIN=y
11CONFIG_MACH_BERLIN_BG2=y
12CONFIG_MACH_BERLIN_BG2CD=y
10CONFIG_GPIO_PCA953X=y 13CONFIG_GPIO_PCA953X=y
11CONFIG_ARCH_HIGHBANK=y 14CONFIG_ARCH_HIGHBANK=y
15CONFIG_ARCH_HI3xxx=y
12CONFIG_ARCH_KEYSTONE=y 16CONFIG_ARCH_KEYSTONE=y
13CONFIG_ARCH_MXC=y 17CONFIG_ARCH_MXC=y
14CONFIG_MACH_IMX51_DT=y 18CONFIG_MACH_IMX51_DT=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index c6ebc184bf68..65f77885c167 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -119,6 +119,7 @@ CONFIG_NFS_FS=y
119CONFIG_ROOT_NFS=y 119CONFIG_ROOT_NFS=y
120CONFIG_NLS_CODEPAGE_437=y 120CONFIG_NLS_CODEPAGE_437=y
121CONFIG_NLS_ISO8859_1=y 121CONFIG_NLS_ISO8859_1=y
122CONFIG_PRINTK_TIME=y
122CONFIG_DEBUG_INFO=y 123CONFIG_DEBUG_INFO=y
123CONFIG_DEBUG_FS=y 124CONFIG_DEBUG_FS=y
124CONFIG_MAGIC_SYSRQ=y 125CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index 2ba9e63d0f17..073541a50e23 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -1,5 +1,3 @@
1CONFIG_ARCH_VERSATILE=y
2CONFIG_EXPERIMENTAL=y
3# CONFIG_LOCALVERSION_AUTO is not set 1# CONFIG_LOCALVERSION_AUTO is not set
4CONFIG_SYSVIPC=y 2CONFIG_SYSVIPC=y
5CONFIG_LOG_BUF_SHIFT=14 3CONFIG_LOG_BUF_SHIFT=14
@@ -7,15 +5,16 @@ CONFIG_BLK_DEV_INITRD=y
7CONFIG_SLAB=y 5CONFIG_SLAB=y
8CONFIG_MODULES=y 6CONFIG_MODULES=y
9CONFIG_MODULE_UNLOAD=y 7CONFIG_MODULE_UNLOAD=y
8CONFIG_PARTITION_ADVANCED=y
9CONFIG_ARCH_VERSATILE=y
10CONFIG_MACH_VERSATILE_AB=y 10CONFIG_MACH_VERSATILE_AB=y
11CONFIG_LEDS=y 11CONFIG_AEABI=y
12CONFIG_LEDS_CPU=y 12CONFIG_OABI_COMPAT=y
13CONFIG_ZBOOT_ROM_TEXT=0x0 13CONFIG_ZBOOT_ROM_TEXT=0x0
14CONFIG_ZBOOT_ROM_BSS=0x0 14CONFIG_ZBOOT_ROM_BSS=0x0
15CONFIG_CMDLINE="root=1f03 mem=32M" 15CONFIG_CMDLINE="root=1f03 mem=32M"
16CONFIG_FPE_NWFPE=y 16CONFIG_FPE_NWFPE=y
17CONFIG_VFP=y 17CONFIG_VFP=y
18CONFIG_PM=y
19CONFIG_NET=y 18CONFIG_NET=y
20CONFIG_PACKET=y 19CONFIG_PACKET=y
21CONFIG_UNIX=y 20CONFIG_UNIX=y
@@ -26,9 +25,7 @@ CONFIG_IP_PNP_BOOTP=y
26# CONFIG_INET_DIAG is not set 25# CONFIG_INET_DIAG is not set
27# CONFIG_IPV6 is not set 26# CONFIG_IPV6 is not set
28CONFIG_MTD=y 27CONFIG_MTD=y
29CONFIG_MTD_PARTITIONS=y
30CONFIG_MTD_CMDLINE_PARTS=y 28CONFIG_MTD_CMDLINE_PARTS=y
31CONFIG_MTD_CHAR=y
32CONFIG_MTD_BLOCK=y 29CONFIG_MTD_BLOCK=y
33CONFIG_MTD_CFI=y 30CONFIG_MTD_CFI=y
34CONFIG_MTD_CFI_ADV_OPTIONS=y 31CONFIG_MTD_CFI_ADV_OPTIONS=y
@@ -37,10 +34,10 @@ CONFIG_MTD_PHYSMAP=y
37CONFIG_BLK_DEV_RAM=y 34CONFIG_BLK_DEV_RAM=y
38CONFIG_EEPROM_LEGACY=m 35CONFIG_EEPROM_LEGACY=m
39CONFIG_NETDEVICES=y 36CONFIG_NETDEVICES=y
40CONFIG_NET_ETHERNET=y
41CONFIG_SMC91X=y 37CONFIG_SMC91X=y
42# CONFIG_SERIO_SERPORT is not set 38# CONFIG_SERIO_SERPORT is not set
43CONFIG_SERIO_AMBAKMI=y 39CONFIG_SERIO_AMBAKMI=y
40CONFIG_LEGACY_PTY_COUNT=16
44CONFIG_SERIAL_8250=m 41CONFIG_SERIAL_8250=m
45CONFIG_SERIAL_8250_EXTENDED=y 42CONFIG_SERIAL_8250_EXTENDED=y
46CONFIG_SERIAL_8250_MANY_PORTS=y 43CONFIG_SERIAL_8250_MANY_PORTS=y
@@ -48,15 +45,14 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
48CONFIG_SERIAL_8250_RSA=y 45CONFIG_SERIAL_8250_RSA=y
49CONFIG_SERIAL_AMBA_PL011=y 46CONFIG_SERIAL_AMBA_PL011=y
50CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 47CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
51CONFIG_LEGACY_PTY_COUNT=16
52CONFIG_I2C=y 48CONFIG_I2C=y
53CONFIG_I2C_CHARDEV=m 49CONFIG_I2C_CHARDEV=m
50CONFIG_GPIOLIB=y
51CONFIG_GPIO_PL061=y
54# CONFIG_HWMON is not set 52# CONFIG_HWMON is not set
55CONFIG_FB=y 53CONFIG_FB=y
56CONFIG_FB_ARMCLCD=y 54CONFIG_FB_ARMCLCD=y
57CONFIG_FRAMEBUFFER_CONSOLE=y 55CONFIG_FRAMEBUFFER_CONSOLE=y
58CONFIG_FONTS=y
59CONFIG_FONT_ACORN_8x8=y
60CONFIG_SOUND=y 56CONFIG_SOUND=y
61CONFIG_SND=m 57CONFIG_SND=m
62CONFIG_SND_MIXER_OSS=m 58CONFIG_SND_MIXER_OSS=m
@@ -64,6 +60,9 @@ CONFIG_SND_PCM_OSS=m
64CONFIG_SND_ARMAACI=m 60CONFIG_SND_ARMAACI=m
65CONFIG_MMC=y 61CONFIG_MMC=y
66CONFIG_MMC_ARMMMCI=m 62CONFIG_MMC_ARMMMCI=m
63CONFIG_NEW_LEDS=y
64CONFIG_LEDS_TRIGGER_HEARTBEAT=y
65CONFIG_LEDS_TRIGGER_CPU=y
67CONFIG_EXT2_FS=y 66CONFIG_EXT2_FS=y
68CONFIG_VFAT_FS=m 67CONFIG_VFAT_FS=m
69CONFIG_JFFS2_FS=y 68CONFIG_JFFS2_FS=y
@@ -71,15 +70,14 @@ CONFIG_CRAMFS=y
71CONFIG_MINIX_FS=y 70CONFIG_MINIX_FS=y
72CONFIG_ROMFS_FS=y 71CONFIG_ROMFS_FS=y
73CONFIG_NFS_FS=y 72CONFIG_NFS_FS=y
74CONFIG_NFS_V3=y
75CONFIG_ROOT_NFS=y 73CONFIG_ROOT_NFS=y
76CONFIG_NFSD=y 74CONFIG_NFSD=y
77CONFIG_NFSD_V3=y 75CONFIG_NFSD_V3=y
78CONFIG_PARTITION_ADVANCED=y
79CONFIG_NLS_CODEPAGE_850=m 76CONFIG_NLS_CODEPAGE_850=m
80CONFIG_NLS_ISO8859_1=m 77CONFIG_NLS_ISO8859_1=m
81CONFIG_MAGIC_SYSRQ=y 78CONFIG_MAGIC_SYSRQ=y
82CONFIG_DEBUG_KERNEL=y 79CONFIG_DEBUG_KERNEL=y
83CONFIG_DEBUG_USER=y 80CONFIG_DEBUG_USER=y
84CONFIG_DEBUG_ERRORS=y
85CONFIG_DEBUG_LL=y 81CONFIG_DEBUG_LL=y
82CONFIG_FONTS=y
83CONFIG_FONT_ACORN_8x8=y
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 29da84e183f4..42b823cd2d22 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -43,6 +43,14 @@
43#define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR 43#define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR
44#define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n) 44#define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n)
45 45
46#define IMX50_UART1_BASE_ADDR 0x53fbc000
47#define IMX50_UART2_BASE_ADDR 0x53fc0000
48#define IMX50_UART3_BASE_ADDR 0x5000c000
49#define IMX50_UART4_BASE_ADDR 0x53ff0000
50#define IMX50_UART5_BASE_ADDR 0x63f90000
51#define IMX50_UART_BASE_ADDR(n) IMX50_UART##n##_BASE_ADDR
52#define IMX50_UART_BASE(n) IMX50_UART_BASE_ADDR(n)
53
46#define IMX51_UART1_BASE_ADDR 0x73fbc000 54#define IMX51_UART1_BASE_ADDR 0x73fbc000
47#define IMX51_UART2_BASE_ADDR 0x73fc0000 55#define IMX51_UART2_BASE_ADDR 0x73fc0000
48#define IMX51_UART3_BASE_ADDR 0x7000c000 56#define IMX51_UART3_BASE_ADDR 0x7000c000
@@ -85,6 +93,8 @@
85#define UART_PADDR IMX_DEBUG_UART_BASE(IMX31) 93#define UART_PADDR IMX_DEBUG_UART_BASE(IMX31)
86#elif defined(CONFIG_DEBUG_IMX35_UART) 94#elif defined(CONFIG_DEBUG_IMX35_UART)
87#define UART_PADDR IMX_DEBUG_UART_BASE(IMX35) 95#define UART_PADDR IMX_DEBUG_UART_BASE(IMX35)
96#elif defined(CONFIG_DEBUG_IMX50_UART)
97#define UART_PADDR IMX_DEBUG_UART_BASE(IMX50)
88#elif defined(CONFIG_DEBUG_IMX51_UART) 98#elif defined(CONFIG_DEBUG_IMX51_UART)
89#define UART_PADDR IMX_DEBUG_UART_BASE(IMX51) 99#define UART_PADDR IMX_DEBUG_UART_BASE(IMX51)
90#elif defined(CONFIG_DEBUG_IMX53_UART) 100#elif defined(CONFIG_DEBUG_IMX53_UART)
diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S
index be6a720dd183..f98763f0bc17 100644
--- a/arch/arm/include/debug/tegra.S
+++ b/arch/arm/include/debug/tegra.S
@@ -46,10 +46,10 @@
46#define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804) 46#define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804)
47 47
48/* 48/*
49 * Must be 1MB-aligned since a 1MB mapping is used early on. 49 * Must be section-aligned since a section mapping is used early on.
50 * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[]. 50 * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
51 */ 51 */
52#define UART_VIRTUAL_BASE 0xfe100000 52#define UART_VIRTUAL_BASE 0xfe800000
53 53
54#define checkuart(rp, rv, lhu, bit, uart) \ 54#define checkuart(rp, rv, lhu, bit, uart) \
55 /* Load address of CLK_RST register */ \ 55 /* Load address of CLK_RST register */ \
@@ -156,28 +156,6 @@
15692: and \rv, \rp, #0xffffff @ offset within 1MB section 15692: and \rv, \rp, #0xffffff @ offset within 1MB section
157 add \rv, \rv, #UART_VIRTUAL_BASE 157 add \rv, \rv, #UART_VIRTUAL_BASE
158 str \rv, [\tmp, #8] @ Store in tegra_uart_virt 158 str \rv, [\tmp, #8] @ Store in tegra_uart_virt
159 movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff
160 movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16
161 ldr \rv, [\rv, #0] @ Load HIDREV
162 ubfx \rv, \rv, #8, #8 @ 15:8 are SoC version
163 cmp \rv, #0x20 @ Tegra20?
164 moveq \rv, #0x75 @ Tegra20 divisor
165 movne \rv, #0xdd @ Tegra30 divisor
166 str \rv, [\tmp, #12] @ Save divisor to scratch
167 /* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */
168 mov \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB
169 str \rv, [\rp, #UART_LCR << UART_SHIFT]
170 /* uart[UART_DLL] = div & 0xff; */
171 ldr \rv, [\tmp, #12]
172 and \rv, \rv, #0xff
173 str \rv, [\rp, #UART_DLL << UART_SHIFT]
174 /* uart[UART_DLM] = div >> 8; */
175 ldr \rv, [\tmp, #12]
176 lsr \rv, \rv, #8
177 str \rv, [\rp, #UART_DLM << UART_SHIFT]
178 /* uart[UART_LCR] = UART_LCR_WLEN8; */
179 mov \rv, #UART_LCR_WLEN8
180 str \rv, [\rp, #UART_LCR << UART_SHIFT]
181 b 100f 159 b 100f
182 160
183 .align 161 .align
@@ -205,8 +183,8 @@
205 cmp \rx, #0 183 cmp \rx, #0
206 beq 1002f 184 beq 1002f
2071001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT] 1851001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
208 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE 186 and \rd, \rd, #UART_LSR_THRE
209 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE 187 teq \rd, #UART_LSR_THRE
210 bne 1001b 188 bne 1001b
2111002: 1891002:
212 .endm 190 .endm
@@ -225,7 +203,7 @@
225/* 203/*
226 * Storage for the state maintained by the macros above. 204 * Storage for the state maintained by the macros above.
227 * 205 *
228 * In the kernel proper, this data is located in arch/arm/mach-tegra/common.c. 206 * In the kernel proper, this data is located in arch/arm/mach-tegra/tegra.c.
229 * That's because this header is included from multiple files, and we only 207 * That's because this header is included from multiple files, and we only
230 * want a single copy of the data. In particular, the UART probing code above 208 * want a single copy of the data. In particular, the UART probing code above
231 * assumes it's running using physical addresses. This is true when this file 209 * assumes it's running using physical addresses. This is true when this file
@@ -247,6 +225,4 @@ tegra_uart_config:
247 .word 0 225 .word 0
248 /* Debug UART virtual address */ 226 /* Debug UART virtual address */
249 .word 0 227 .word 0
250 /* Scratch space for debug macro */
251 .word 0
252#endif 228#endif
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index f1bf952da747..4f0e800e7e71 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -90,7 +90,7 @@ config SOC_SAMA5D3
90 select HAVE_AT91_USB_CLK 90 select HAVE_AT91_USB_CLK
91 help 91 help
92 Select this if you are using one of Atmel's SAMA5D3 family SoC. 92 Select this if you are using one of Atmel's SAMA5D3 family SoC.
93 This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35. 93 This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
94endif 94endif
95 95
96if SOC_SAM_V4_V5 96if SOC_SAM_V4_V5
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index d3d7b993846b..86c71debab5b 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -53,6 +53,7 @@
53#define ARCH_EXID_SAMA5D33 0x00414300 53#define ARCH_EXID_SAMA5D33 0x00414300
54#define ARCH_EXID_SAMA5D34 0x00414301 54#define ARCH_EXID_SAMA5D34 0x00414301
55#define ARCH_EXID_SAMA5D35 0x00584300 55#define ARCH_EXID_SAMA5D35 0x00584300
56#define ARCH_EXID_SAMA5D36 0x00004301
56 57
57#define ARCH_FAMILY_AT91X92 0x09200000 58#define ARCH_FAMILY_AT91X92 0x09200000
58#define ARCH_FAMILY_AT91SAM9 0x01900000 59#define ARCH_FAMILY_AT91SAM9 0x01900000
@@ -105,7 +106,7 @@ enum at91_soc_subtype {
105 106
106 /* SAMA5D3 */ 107 /* SAMA5D3 */
107 AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34, 108 AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
108 AT91_SOC_SAMA5D35, 109 AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36,
109 110
110 /* No subtype for this SoC */ 111 /* No subtype for this SoC */
111 AT91_SOC_SUBTYPE_NONE, 112 AT91_SOC_SUBTYPE_NONE,
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 9dc8894c5623..f7ca97b7291e 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -233,6 +233,9 @@ static void __init soc_detect(u32 dbgu_base)
233 case ARCH_EXID_SAMA5D35: 233 case ARCH_EXID_SAMA5D35:
234 at91_soc_initdata.subtype = AT91_SOC_SAMA5D35; 234 at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
235 break; 235 break;
236 case ARCH_EXID_SAMA5D36:
237 at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
238 break;
236 } 239 }
237 } 240 }
238} 241}
@@ -275,6 +278,7 @@ static const char *soc_subtype_name[] = {
275 [AT91_SOC_SAMA5D33] = "sama5d33", 278 [AT91_SOC_SAMA5D33] = "sama5d33",
276 [AT91_SOC_SAMA5D34] = "sama5d34", 279 [AT91_SOC_SAMA5D34] = "sama5d34",
277 [AT91_SOC_SAMA5D35] = "sama5d35", 280 [AT91_SOC_SAMA5D35] = "sama5d35",
281 [AT91_SOC_SAMA5D36] = "sama5d36",
278 [AT91_SOC_SUBTYPE_NONE] = "None", 282 [AT91_SOC_SUBTYPE_NONE] = "None",
279 [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown", 283 [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
280}; 284};
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
new file mode 100644
index 000000000000..7a02d222c378
--- /dev/null
+++ b/arch/arm/mach-berlin/Kconfig
@@ -0,0 +1,29 @@
1config ARCH_BERLIN
2 bool "Marvell Berlin SoCs" if ARCH_MULTI_V7
3 select ARM_GIC
4 select GENERIC_CLOCKEVENTS
5 select GENERIC_IRQ_CHIP
6 select COMMON_CLK
7 select DW_APB_ICTL
8 select DW_APB_TIMER_OF
9
10if ARCH_BERLIN
11
12menu "Marvell Berlin SoC variants"
13
14config MACH_BERLIN_BG2
15 bool "Marvell Armada 1500 (BG2)"
16 select CACHE_L2X0
17 select CPU_PJ4B
18 select HAVE_ARM_TWD if SMP
19 select HAVE_SMP
20
21config MACH_BERLIN_BG2CD
22 bool "Marvell Armada 1500-mini (BG2CD)"
23 select CACHE_L2X0
24 select CPU_V7
25 select HAVE_ARM_TWD if SMP
26
27endmenu
28
29endif
diff --git a/arch/arm/mach-berlin/Makefile b/arch/arm/mach-berlin/Makefile
new file mode 100644
index 000000000000..ab69fe956f49
--- /dev/null
+++ b/arch/arm/mach-berlin/Makefile
@@ -0,0 +1 @@
obj-y += berlin.o
diff --git a/arch/arm/mach-berlin/berlin.c b/arch/arm/mach-berlin/berlin.c
new file mode 100644
index 000000000000..025bcb5473eb
--- /dev/null
+++ b/arch/arm/mach-berlin/berlin.c
@@ -0,0 +1,39 @@
1/*
2 * Device Tree support for Marvell Berlin SoCs.
3 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * based on GPL'ed 2.6 kernel sources
7 * (c) Marvell International Ltd.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <linux/of_platform.h>
18#include <asm/hardware/cache-l2x0.h>
19#include <asm/mach/arch.h>
20
21static void __init berlin_init_machine(void)
22{
23 /*
24 * with DT probing for L2CCs, berlin_init_machine can be removed.
25 * Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc
26 */
27 l2x0_of_init(0x70c00000, 0xfeffffff);
28 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
29}
30
31static const char * const berlin_dt_compat[] = {
32 "marvell,berlin",
33 NULL,
34};
35
36DT_MACHINE_START(BERLIN_DT, "Marvell Berlin")
37 .dt_compat = berlin_dt_compat,
38 .init_machine = berlin_init_machine,
39MACHINE_END
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 134641d688bb..a1935911e4f1 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -259,7 +259,7 @@ asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
259 } while (1); 259 } while (1);
260} 260}
261 261
262static u32 notrace clps711x_sched_clock_read(void) 262static u64 notrace clps711x_sched_clock_read(void)
263{ 263{
264 return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D); 264 return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D);
265} 265}
@@ -366,7 +366,7 @@ void __init clps711x_timer_init(void)
366 tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M); 366 tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M);
367 clps_writel(tmp, SYSCON1); 367 clps_writel(tmp, SYSCON1);
368 368
369 setup_sched_clock(clps711x_sched_clock_read, 16, timl); 369 sched_clock_register(clps711x_sched_clock_read, 16, timl);
370 370
371 clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D, 371 clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D,
372 "clps711x_clocksource", timl, 300, 16, 372 "clps711x_clocksource", timl, 300, 16,
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index dc9a470ff9c5..985e5fd00fb2 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -133,7 +133,7 @@ EXPORT_SYMBOL(clk_get_rate);
133long clk_round_rate(struct clk *clk, unsigned long rate) 133long clk_round_rate(struct clk *clk, unsigned long rate)
134{ 134{
135 if (clk == NULL || IS_ERR(clk)) 135 if (clk == NULL || IS_ERR(clk))
136 return -EINVAL; 136 return 0;
137 137
138 if (clk->round_rate) 138 if (clk->round_rate)
139 return clk->round_rate(clk, rate); 139 return clk->round_rate(clk, rate);
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 56c6eb5266ad..24ad30f32ae3 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -285,7 +285,7 @@ static struct clocksource clocksource_davinci = {
285/* 285/*
286 * Overwrite weak default sched_clock with something more precise 286 * Overwrite weak default sched_clock with something more precise
287 */ 287 */
288static u32 notrace davinci_read_sched_clock(void) 288static u64 notrace davinci_read_sched_clock(void)
289{ 289{
290 return timer32_read(&timers[TID_CLOCKSOURCE]); 290 return timer32_read(&timers[TID_CLOCKSOURCE]);
291} 291}
@@ -391,7 +391,7 @@ void __init davinci_timer_init(void)
391 davinci_clock_tick_rate)) 391 davinci_clock_tick_rate))
392 printk(err, clocksource_davinci.name); 392 printk(err, clocksource_davinci.name);
393 393
394 setup_sched_clock(davinci_read_sched_clock, 32, 394 sched_clock_register(davinci_read_sched_clock, 32,
395 davinci_clock_tick_rate); 395 davinci_clock_tick_rate);
396 396
397 /* setup clockevent */ 397 /* setup clockevent */
diff --git a/arch/arm/mach-efm32/Makefile b/arch/arm/mach-efm32/Makefile
new file mode 100644
index 000000000000..3a74af7413e8
--- /dev/null
+++ b/arch/arm/mach-efm32/Makefile
@@ -0,0 +1 @@
obj-y += dtmachine.o
diff --git a/arch/arm/mach-efm32/Makefile.boot b/arch/arm/mach-efm32/Makefile.boot
new file mode 100644
index 000000000000..eacfc3f5c33e
--- /dev/null
+++ b/arch/arm/mach-efm32/Makefile.boot
@@ -0,0 +1,3 @@
1# Empty file waiting for deletion once Makefile.boot isn't needed any more.
2# Patch waits for application at
3# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 .
diff --git a/arch/arm/mach-efm32/dtmachine.c b/arch/arm/mach-efm32/dtmachine.c
new file mode 100644
index 000000000000..2367495193c1
--- /dev/null
+++ b/arch/arm/mach-efm32/dtmachine.c
@@ -0,0 +1,15 @@
1#include <linux/kernel.h>
2
3#include <asm/v7m.h>
4
5#include <asm/mach/arch.h>
6
7static const char *const efm32gg_compat[] __initconst = {
8 "efm32,dk3750",
9 NULL
10};
11
12DT_MACHINE_START(EFM32DT, "EFM32 (Device Tree Support)")
13 .dt_compat = efm32gg_compat,
14 .restart = armv7m_restart,
15MACHINE_END
diff --git a/arch/arm/mach-efm32/include/mach/entry-macro.S b/arch/arm/mach-efm32/include/mach/entry-macro.S
new file mode 100644
index 000000000000..322159d5ed91
--- /dev/null
+++ b/arch/arm/mach-efm32/include/mach/entry-macro.S
@@ -0,0 +1,4 @@
1/*
2 * Empty file waiting for deletion once <mach/entry-macro.S> isn't needed any
3 * more. Patch "ARM: v7-M: drop using mach/entry-macro.S" sitting in next.
4 */
diff --git a/arch/arm/mach-efm32/include/mach/timex.h b/arch/arm/mach-efm32/include/mach/timex.h
new file mode 100644
index 000000000000..7a8b26da6599
--- /dev/null
+++ b/arch/arm/mach-efm32/include/mach/timex.h
@@ -0,0 +1,3 @@
1/*
2 * Empty file waiting for deletion once <mach/timex.h> isn't needed any more.
3 */
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index 93e54fd4e3d5..bec570ae6494 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -5,6 +5,7 @@ menu "Cirrus EP93xx Implementation Options"
5config EP93XX_SOC_COMMON 5config EP93XX_SOC_COMMON
6 bool 6 bool
7 default y 7 default y
8 select SOC_BUS
8 select LEDS_GPIO_REGISTER 9 select LEDS_GPIO_REGISTER
9 10
10config CRUNCH 11config CRUNCH
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index d95ee28a616a..157ba88433c9 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -21,6 +21,7 @@
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/dma-mapping.h> 23#include <linux/dma-mapping.h>
24#include <linux/sys_soc.h>
24#include <linux/timex.h> 25#include <linux/timex.h>
25#include <linux/irq.h> 26#include <linux/irq.h>
26#include <linux/io.h> 27#include <linux/io.h>
@@ -44,6 +45,7 @@
44#include <linux/platform_data/spi-ep93xx.h> 45#include <linux/platform_data/spi-ep93xx.h>
45#include <mach/gpio-ep93xx.h> 46#include <mach/gpio-ep93xx.h>
46 47
48#include <asm/mach/arch.h>
47#include <asm/mach/map.h> 49#include <asm/mach/map.h>
48#include <asm/mach/time.h> 50#include <asm/mach/time.h>
49 51
@@ -137,7 +139,7 @@ static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
137 139
138static struct irqaction ep93xx_timer_irq = { 140static struct irqaction ep93xx_timer_irq = {
139 .name = "ep93xx timer", 141 .name = "ep93xx timer",
140 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 142 .flags = IRQF_TIMER | IRQF_IRQPOLL,
141 .handler = ep93xx_timer_interrupt, 143 .handler = ep93xx_timer_interrupt,
142}; 144};
143 145
@@ -925,8 +927,108 @@ void ep93xx_ide_release_gpio(struct platform_device *pdev)
925} 927}
926EXPORT_SYMBOL(ep93xx_ide_release_gpio); 928EXPORT_SYMBOL(ep93xx_ide_release_gpio);
927 929
928void __init ep93xx_init_devices(void) 930/*************************************************************************
931 * EP93xx Security peripheral
932 *************************************************************************/
933
934/*
935 * The Maverick Key is 256 bits of micro fuses blown at the factory during
936 * manufacturing to uniquely identify a part.
937 *
938 * See: http://arm.cirrus.com/forum/viewtopic.php?t=486&highlight=maverick+key
939 */
940#define EP93XX_SECURITY_REG(x) (EP93XX_SECURITY_BASE + (x))
941#define EP93XX_SECURITY_SECFLG EP93XX_SECURITY_REG(0x2400)
942#define EP93XX_SECURITY_FUSEFLG EP93XX_SECURITY_REG(0x2410)
943#define EP93XX_SECURITY_UNIQID EP93XX_SECURITY_REG(0x2440)
944#define EP93XX_SECURITY_UNIQCHK EP93XX_SECURITY_REG(0x2450)
945#define EP93XX_SECURITY_UNIQVAL EP93XX_SECURITY_REG(0x2460)
946#define EP93XX_SECURITY_SECID1 EP93XX_SECURITY_REG(0x2500)
947#define EP93XX_SECURITY_SECID2 EP93XX_SECURITY_REG(0x2504)
948#define EP93XX_SECURITY_SECCHK1 EP93XX_SECURITY_REG(0x2520)
949#define EP93XX_SECURITY_SECCHK2 EP93XX_SECURITY_REG(0x2524)
950#define EP93XX_SECURITY_UNIQID2 EP93XX_SECURITY_REG(0x2700)
951#define EP93XX_SECURITY_UNIQID3 EP93XX_SECURITY_REG(0x2704)
952#define EP93XX_SECURITY_UNIQID4 EP93XX_SECURITY_REG(0x2708)
953#define EP93XX_SECURITY_UNIQID5 EP93XX_SECURITY_REG(0x270c)
954
955static char ep93xx_soc_id[33];
956
957static const char __init *ep93xx_get_soc_id(void)
929{ 958{
959 unsigned int id, id2, id3, id4, id5;
960
961 if (__raw_readl(EP93XX_SECURITY_UNIQVAL) != 1)
962 return "bad Hamming code";
963
964 id = __raw_readl(EP93XX_SECURITY_UNIQID);
965 id2 = __raw_readl(EP93XX_SECURITY_UNIQID2);
966 id3 = __raw_readl(EP93XX_SECURITY_UNIQID3);
967 id4 = __raw_readl(EP93XX_SECURITY_UNIQID4);
968 id5 = __raw_readl(EP93XX_SECURITY_UNIQID5);
969
970 if (id != id2)
971 return "invalid";
972
973 snprintf(ep93xx_soc_id, sizeof(ep93xx_soc_id),
974 "%08x%08x%08x%08x", id2, id3, id4, id5);
975
976 return ep93xx_soc_id;
977}
978
979static const char __init *ep93xx_get_soc_rev(void)
980{
981 int rev = ep93xx_chip_revision();
982
983 switch (rev) {
984 case EP93XX_CHIP_REV_D0:
985 return "D0";
986 case EP93XX_CHIP_REV_D1:
987 return "D1";
988 case EP93XX_CHIP_REV_E0:
989 return "E0";
990 case EP93XX_CHIP_REV_E1:
991 return "E1";
992 case EP93XX_CHIP_REV_E2:
993 return "E2";
994 default:
995 return "unknown";
996 }
997}
998
999static const char __init *ep93xx_get_machine_name(void)
1000{
1001 return kasprintf(GFP_KERNEL,"%s", machine_desc->name);
1002}
1003
1004static struct device __init *ep93xx_init_soc(void)
1005{
1006 struct soc_device_attribute *soc_dev_attr;
1007 struct soc_device *soc_dev;
1008
1009 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
1010 if (!soc_dev_attr)
1011 return NULL;
1012
1013 soc_dev_attr->machine = ep93xx_get_machine_name();
1014 soc_dev_attr->family = "Cirrus Logic EP93xx";
1015 soc_dev_attr->revision = ep93xx_get_soc_rev();
1016 soc_dev_attr->soc_id = ep93xx_get_soc_id();
1017
1018 soc_dev = soc_device_register(soc_dev_attr);
1019 if (IS_ERR(soc_dev)) {
1020 kfree(soc_dev_attr->machine);
1021 kfree(soc_dev_attr);
1022 return NULL;
1023 }
1024
1025 return soc_device_to_device(soc_dev);
1026}
1027
1028struct device __init *ep93xx_init_devices(void)
1029{
1030 struct device *parent;
1031
930 /* Disallow access to MaverickCrunch initially */ 1032 /* Disallow access to MaverickCrunch initially */
931 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA); 1033 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
932 1034
@@ -937,6 +1039,8 @@ void __init ep93xx_init_devices(void)
937 EP93XX_SYSCON_DEVCFG_GONIDE | 1039 EP93XX_SYSCON_DEVCFG_GONIDE |
938 EP93XX_SYSCON_DEVCFG_HONIDE); 1040 EP93XX_SYSCON_DEVCFG_HONIDE);
939 1041
1042 parent = ep93xx_init_soc();
1043
940 /* Get the GPIO working early, other devices need it */ 1044 /* Get the GPIO working early, other devices need it */
941 platform_device_register(&ep93xx_gpio_device); 1045 platform_device_register(&ep93xx_gpio_device);
942 1046
@@ -949,6 +1053,8 @@ void __init ep93xx_init_devices(void)
949 platform_device_register(&ep93xx_wdt_device); 1053 platform_device_register(&ep93xx_wdt_device);
950 1054
951 gpio_led_register_device(-1, &ep93xx_led_data); 1055 gpio_led_register_device(-1, &ep93xx_led_data);
1056
1057 return parent;
952} 1058}
953 1059
954void ep93xx_restart(enum reboot_mode mode, const char *cmd) 1060void ep93xx_restart(enum reboot_mode mode, const char *cmd)
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index e256e0baec2e..4c0bbd97f741 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -6,6 +6,7 @@
6 6
7#include <linux/reboot.h> 7#include <linux/reboot.h>
8 8
9struct device;
9struct i2c_gpio_platform_data; 10struct i2c_gpio_platform_data;
10struct i2c_board_info; 11struct i2c_board_info;
11struct spi_board_info; 12struct spi_board_info;
@@ -54,7 +55,7 @@ void ep93xx_register_ide(void);
54int ep93xx_ide_acquire_gpio(struct platform_device *pdev); 55int ep93xx_ide_acquire_gpio(struct platform_device *pdev);
55void ep93xx_ide_release_gpio(struct platform_device *pdev); 56void ep93xx_ide_release_gpio(struct platform_device *pdev);
56 57
57void ep93xx_init_devices(void); 58struct device *ep93xx_init_devices(void);
58extern void ep93xx_timer_init(void); 59extern void ep93xx_timer_init(void);
59 60
60void ep93xx_restart(enum reboot_mode, const char *); 61void ep93xx_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
new file mode 100644
index 000000000000..018ad67f1b38
--- /dev/null
+++ b/arch/arm/mach-hisi/Kconfig
@@ -0,0 +1,17 @@
1config ARCH_HI3xxx
2 bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
3 select ARM_AMBA
4 select ARM_GIC
5 select ARM_TIMER_SP804
6 select ARCH_WANT_OPTIONAL_GPIOLIB
7 select CACHE_L2X0
8 select CLKSRC_OF
9 select GENERIC_CLOCKEVENTS
10 select HAVE_ARM_SCU
11 select HAVE_ARM_TWD
12 select HAVE_SMP
13 select PINCTRL
14 select PINCTRL_SINGLE
15 select SMP
16 help
17 Support for Hisilicon Hi36xx/Hi37xx processor family
diff --git a/arch/arm/mach-hisi/Makefile b/arch/arm/mach-hisi/Makefile
new file mode 100644
index 000000000000..6870058d0a48
--- /dev/null
+++ b/arch/arm/mach-hisi/Makefile
@@ -0,0 +1,7 @@
1#
2# Makefile for Hisilicon processors family
3#
4
5obj-y += hisilicon.o
6obj-$(CONFIG_SMP) += platsmp.o
7obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-hisi/core.h b/arch/arm/mach-hisi/core.h
new file mode 100644
index 000000000000..af23ec204538
--- /dev/null
+++ b/arch/arm/mach-hisi/core.h
@@ -0,0 +1,15 @@
1#ifndef __HISILICON_CORE_H
2#define __HISILICON_CORE_H
3
4#include <linux/reboot.h>
5
6extern void hi3xxx_set_cpu_jump(int cpu, void *jump_addr);
7extern int hi3xxx_get_cpu_jump(int cpu);
8extern void secondary_startup(void);
9extern struct smp_operations hi3xxx_smp_ops;
10
11extern void hi3xxx_cpu_die(unsigned int cpu);
12extern int hi3xxx_cpu_kill(unsigned int cpu);
13extern void hi3xxx_set_cpu(int cpu, bool enable);
14
15#endif
diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c
new file mode 100644
index 000000000000..741faf3e7100
--- /dev/null
+++ b/arch/arm/mach-hisi/hisilicon.c
@@ -0,0 +1,90 @@
1/*
2 * (Hisilicon's SoC based) flattened device tree enabled machine
3 *
4 * Copyright (c) 2012-2013 Hisilicon Ltd.
5 * Copyright (c) 2012-2013 Linaro Ltd.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/clk-provider.h>
15#include <linux/clocksource.h>
16#include <linux/irqchip.h>
17#include <linux/of_address.h>
18#include <linux/of_platform.h>
19
20#include <asm/proc-fns.h>
21
22#include <asm/mach/arch.h>
23#include <asm/mach/map.h>
24
25#include "core.h"
26
27#define HI3620_SYSCTRL_PHYS_BASE 0xfc802000
28#define HI3620_SYSCTRL_VIRT_BASE 0xfe802000
29
30/*
31 * This table is only for optimization. Since ioremap() could always share
32 * the same mapping if it's defined as static IO mapping.
33 *
34 * Without this table, system could also work. The cost is some virtual address
35 * spaces wasted since ioremap() may be called multi times for the same
36 * IO space.
37 */
38static struct map_desc hi3620_io_desc[] __initdata = {
39 {
40 /* sysctrl */
41 .pfn = __phys_to_pfn(HI3620_SYSCTRL_PHYS_BASE),
42 .virtual = HI3620_SYSCTRL_VIRT_BASE,
43 .length = 0x1000,
44 .type = MT_DEVICE,
45 },
46};
47
48static void __init hi3620_map_io(void)
49{
50 debug_ll_io_init();
51 iotable_init(hi3620_io_desc, ARRAY_SIZE(hi3620_io_desc));
52}
53
54static void hi3xxx_restart(enum reboot_mode mode, const char *cmd)
55{
56 struct device_node *np;
57 void __iomem *base;
58 int offset;
59
60 np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
61 if (!np) {
62 pr_err("failed to find hisilicon,sysctrl node\n");
63 return;
64 }
65 base = of_iomap(np, 0);
66 if (!base) {
67 pr_err("failed to map address in hisilicon,sysctrl node\n");
68 return;
69 }
70 if (of_property_read_u32(np, "reboot-offset", &offset) < 0) {
71 pr_err("failed to find reboot-offset property\n");
72 return;
73 }
74 writel_relaxed(0xdeadbeef, base + offset);
75
76 while (1)
77 cpu_do_idle();
78}
79
80static const char *hi3xxx_compat[] __initconst = {
81 "hisilicon,hi3620-hi4511",
82 NULL,
83};
84
85DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
86 .map_io = hi3620_map_io,
87 .dt_compat = hi3xxx_compat,
88 .smp = smp_ops(hi3xxx_smp_ops),
89 .restart = hi3xxx_restart,
90MACHINE_END
diff --git a/arch/arm/mach-hisi/hotplug.c b/arch/arm/mach-hisi/hotplug.c
new file mode 100644
index 000000000000..b909854eee7f
--- /dev/null
+++ b/arch/arm/mach-hisi/hotplug.c
@@ -0,0 +1,200 @@
1/*
2 * Copyright (c) 2013 Linaro Ltd.
3 * Copyright (c) 2013 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10#include <linux/cpu.h>
11#include <linux/delay.h>
12#include <linux/io.h>
13#include <linux/of_address.h>
14#include <linux/of_platform.h>
15#include <asm/cacheflush.h>
16#include <asm/smp_plat.h>
17#include "core.h"
18
19/* Sysctrl registers in Hi3620 SoC */
20#define SCISOEN 0xc0
21#define SCISODIS 0xc4
22#define SCPERPWREN 0xd0
23#define SCPERPWRDIS 0xd4
24#define SCCPUCOREEN 0xf4
25#define SCCPUCOREDIS 0xf8
26#define SCPERCTRL0 0x200
27#define SCCPURSTEN 0x410
28#define SCCPURSTDIS 0x414
29
30/*
31 * bit definition in SCISOEN/SCPERPWREN/...
32 *
33 * CPU2_ISO_CTRL (1 << 5)
34 * CPU3_ISO_CTRL (1 << 6)
35 * ...
36 */
37#define CPU2_ISO_CTRL (1 << 5)
38
39/*
40 * bit definition in SCPERCTRL0
41 *
42 * CPU0_WFI_MASK_CFG (1 << 28)
43 * CPU1_WFI_MASK_CFG (1 << 29)
44 * ...
45 */
46#define CPU0_WFI_MASK_CFG (1 << 28)
47
48/*
49 * bit definition in SCCPURSTEN/...
50 *
51 * CPU0_SRST_REQ_EN (1 << 0)
52 * CPU1_SRST_REQ_EN (1 << 1)
53 * ...
54 */
55#define CPU0_HPM_SRST_REQ_EN (1 << 22)
56#define CPU0_DBG_SRST_REQ_EN (1 << 12)
57#define CPU0_NEON_SRST_REQ_EN (1 << 4)
58#define CPU0_SRST_REQ_EN (1 << 0)
59
60enum {
61 HI3620_CTRL,
62 ERROR_CTRL,
63};
64
65static void __iomem *ctrl_base;
66static int id;
67
68static void set_cpu_hi3620(int cpu, bool enable)
69{
70 u32 val = 0;
71
72 if (enable) {
73 /* MTCMOS set */
74 if ((cpu == 2) || (cpu == 3))
75 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
76 ctrl_base + SCPERPWREN);
77 udelay(100);
78
79 /* Enable core */
80 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN);
81
82 /* unreset */
83 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
84 | CPU0_SRST_REQ_EN;
85 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
86 /* reset */
87 val |= CPU0_HPM_SRST_REQ_EN;
88 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
89
90 /* ISO disable */
91 if ((cpu == 2) || (cpu == 3))
92 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
93 ctrl_base + SCISODIS);
94 udelay(1);
95
96 /* WFI Mask */
97 val = readl_relaxed(ctrl_base + SCPERCTRL0);
98 val &= ~(CPU0_WFI_MASK_CFG << cpu);
99 writel_relaxed(val, ctrl_base + SCPERCTRL0);
100
101 /* Unreset */
102 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
103 | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
104 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
105 } else {
106 /* wfi mask */
107 val = readl_relaxed(ctrl_base + SCPERCTRL0);
108 val |= (CPU0_WFI_MASK_CFG << cpu);
109 writel_relaxed(val, ctrl_base + SCPERCTRL0);
110
111 /* disable core*/
112 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS);
113
114 if ((cpu == 2) || (cpu == 3)) {
115 /* iso enable */
116 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
117 ctrl_base + SCISOEN);
118 udelay(1);
119 }
120
121 /* reset */
122 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
123 | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
124 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
125
126 if ((cpu == 2) || (cpu == 3)) {
127 /* MTCMOS unset */
128 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
129 ctrl_base + SCPERPWRDIS);
130 udelay(100);
131 }
132 }
133}
134
135static int hi3xxx_hotplug_init(void)
136{
137 struct device_node *node;
138
139 node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
140 if (node) {
141 ctrl_base = of_iomap(node, 0);
142 id = HI3620_CTRL;
143 return 0;
144 }
145 id = ERROR_CTRL;
146 return -ENOENT;
147}
148
149void hi3xxx_set_cpu(int cpu, bool enable)
150{
151 if (!ctrl_base) {
152 if (hi3xxx_hotplug_init() < 0)
153 return;
154 }
155
156 if (id == HI3620_CTRL)
157 set_cpu_hi3620(cpu, enable);
158}
159
160static inline void cpu_enter_lowpower(void)
161{
162 unsigned int v;
163
164 flush_cache_all();
165
166 /*
167 * Turn off coherency and L1 D-cache
168 */
169 asm volatile(
170 " mrc p15, 0, %0, c1, c0, 1\n"
171 " bic %0, %0, #0x40\n"
172 " mcr p15, 0, %0, c1, c0, 1\n"
173 " mrc p15, 0, %0, c1, c0, 0\n"
174 " bic %0, %0, #0x04\n"
175 " mcr p15, 0, %0, c1, c0, 0\n"
176 : "=&r" (v)
177 : "r" (0)
178 : "cc");
179}
180
181void hi3xxx_cpu_die(unsigned int cpu)
182{
183 cpu_enter_lowpower();
184 hi3xxx_set_cpu_jump(cpu, phys_to_virt(0));
185 cpu_do_idle();
186
187 /* We should have never returned from idle */
188 panic("cpu %d unexpectedly exit from shutdown\n", cpu);
189}
190
191int hi3xxx_cpu_kill(unsigned int cpu)
192{
193 unsigned long timeout = jiffies + msecs_to_jiffies(50);
194
195 while (hi3xxx_get_cpu_jump(cpu))
196 if (time_after(jiffies, timeout))
197 return 0;
198 hi3xxx_set_cpu(cpu, false);
199 return 1;
200}
diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c
new file mode 100644
index 000000000000..471f1ee3be2b
--- /dev/null
+++ b/arch/arm/mach-hisi/platsmp.c
@@ -0,0 +1,89 @@
1/*
2 * Copyright (c) 2013 Linaro Ltd.
3 * Copyright (c) 2013 Hisilicon Limited.
4 * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 */
10#include <linux/smp.h>
11#include <linux/io.h>
12#include <linux/of_address.h>
13
14#include <asm/cacheflush.h>
15#include <asm/smp_plat.h>
16#include <asm/smp_scu.h>
17
18#include "core.h"
19
20static void __iomem *ctrl_base;
21
22void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
23{
24 cpu = cpu_logical_map(cpu);
25 if (!cpu || !ctrl_base)
26 return;
27 writel_relaxed(virt_to_phys(jump_addr), ctrl_base + ((cpu - 1) << 2));
28}
29
30int hi3xxx_get_cpu_jump(int cpu)
31{
32 cpu = cpu_logical_map(cpu);
33 if (!cpu || !ctrl_base)
34 return 0;
35 return readl_relaxed(ctrl_base + ((cpu - 1) << 2));
36}
37
38static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
39{
40 struct device_node *np = NULL;
41 unsigned long base = 0;
42 u32 offset = 0;
43 void __iomem *scu_base = NULL;
44
45 if (scu_a9_has_base()) {
46 base = scu_a9_get_base();
47 scu_base = ioremap(base, SZ_4K);
48 if (!scu_base) {
49 pr_err("ioremap(scu_base) failed\n");
50 return;
51 }
52 scu_enable(scu_base);
53 iounmap(scu_base);
54 }
55 if (!ctrl_base) {
56 np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
57 if (!np) {
58 pr_err("failed to find hisilicon,sysctrl node\n");
59 return;
60 }
61 ctrl_base = of_iomap(np, 0);
62 if (!ctrl_base) {
63 pr_err("failed to map address\n");
64 return;
65 }
66 if (of_property_read_u32(np, "smp-offset", &offset) < 0) {
67 pr_err("failed to find smp-offset property\n");
68 return;
69 }
70 ctrl_base += offset;
71 }
72}
73
74static int hi3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle)
75{
76 hi3xxx_set_cpu(cpu, true);
77 hi3xxx_set_cpu_jump(cpu, secondary_startup);
78 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
79 return 0;
80}
81
82struct smp_operations hi3xxx_smp_ops __initdata = {
83 .smp_prepare_cpus = hi3xxx_smp_prepare_cpus,
84 .smp_boot_secondary = hi3xxx_boot_secondary,
85#ifdef CONFIG_HOTPLUG_CPU
86 .cpu_die = hi3xxx_cpu_die,
87 .cpu_kill = hi3xxx_cpu_kill,
88#endif
89};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index fae0578fec7e..33567aa5880f 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -10,6 +10,7 @@ config ARCH_MXC
10 select GENERIC_IRQ_CHIP 10 select GENERIC_IRQ_CHIP
11 select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7 11 select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7
12 select MULTI_IRQ_HANDLER 12 select MULTI_IRQ_HANDLER
13 select PINCTRL
13 select SOC_BUS 14 select SOC_BUS
14 select SPARSE_IRQ 15 select SPARSE_IRQ
15 select USE_OF 16 select USE_OF
@@ -19,16 +20,6 @@ config ARCH_MXC
19menu "Freescale i.MX support" 20menu "Freescale i.MX support"
20 depends on ARCH_MXC 21 depends on ARCH_MXC
21 22
22config MXC_IRQ_PRIOR
23 bool "Use IRQ priority"
24 help
25 Select this if you want to use prioritized IRQ handling.
26 This feature prevents higher priority ISR to be interrupted
27 by lower priority IRQ.
28 This may be useful in embedded applications, where are strong
29 requirements for timing.
30 Say N here, unless you have a specialized requirement.
31
32config MXC_TZIC 23config MXC_TZIC
33 bool 24 bool
34 25
@@ -108,6 +99,7 @@ config SOC_IMX25
108 select ARCH_MXC_IOMUX_V3 99 select ARCH_MXC_IOMUX_V3
109 select CPU_ARM926T 100 select CPU_ARM926T
110 select MXC_AVIC 101 select MXC_AVIC
102 select PINCTRL_IMX25
111 103
112config SOC_IMX27 104config SOC_IMX27
113 bool 105 bool
@@ -117,6 +109,7 @@ config SOC_IMX27
117 select IMX_HAVE_IOMUX_V1 109 select IMX_HAVE_IOMUX_V1
118 select MACH_MX27 110 select MACH_MX27
119 select MXC_AVIC 111 select MXC_AVIC
112 select PINCTRL_IMX27
120 113
121config SOC_IMX31 114config SOC_IMX31
122 bool 115 bool
@@ -132,6 +125,7 @@ config SOC_IMX35
132 select HAVE_EPIT 125 select HAVE_EPIT
133 select MXC_AVIC 126 select MXC_AVIC
134 select SMP_ON_UP if SMP 127 select SMP_ON_UP if SMP
128 select PINCTRL
135 129
136config SOC_IMX5 130config SOC_IMX5
137 bool 131 bool
@@ -144,7 +138,6 @@ config SOC_IMX5
144config SOC_IMX51 138config SOC_IMX51
145 bool 139 bool
146 select HAVE_IMX_SRC 140 select HAVE_IMX_SRC
147 select PINCTRL
148 select PINCTRL_IMX51 141 select PINCTRL_IMX51
149 select SOC_IMX5 142 select SOC_IMX5
150 143
@@ -618,6 +611,13 @@ config MACH_IMX31_DT
618 611
619comment "MX35 platforms:" 612comment "MX35 platforms:"
620 613
614config MACH_IMX35_DT
615 bool "Support i.MX35 platforms from device tree"
616 select SOC_IMX35
617 help
618 Include support for Freescale i.MX35 based platforms
619 using the device tree for discovery.
620
621config MACH_PCM043 621config MACH_PCM043
622 bool "Support Phytec pcm043 (i.MX35) platforms" 622 bool "Support Phytec pcm043 (i.MX35) platforms"
623 select IMX_HAVE_PLATFORM_FLEXCAN 623 select IMX_HAVE_PLATFORM_FLEXCAN
@@ -765,11 +765,19 @@ endchoice
765 765
766comment "Device tree only" 766comment "Device tree only"
767 767
768config SOC_IMX50
769 bool "i.MX50 support"
770 select HAVE_IMX_SRC
771 select PINCTRL_IMX50
772 select SOC_IMX5
773
774 help
775 This enables support for Freescale i.MX50 processor.
776
768config SOC_IMX53 777config SOC_IMX53
769 bool "i.MX53 support" 778 bool "i.MX53 support"
770 select HAVE_IMX_SRC 779 select HAVE_IMX_SRC
771 select IMX_HAVE_PLATFORM_IMX2_WDT 780 select IMX_HAVE_PLATFORM_IMX2_WDT
772 select PINCTRL
773 select PINCTRL_IMX53 781 select PINCTRL_IMX53
774 select SOC_IMX5 782 select SOC_IMX5
775 783
@@ -795,7 +803,6 @@ config SOC_IMX6Q
795 select MFD_SYSCON 803 select MFD_SYSCON
796 select MIGHT_HAVE_PCI 804 select MIGHT_HAVE_PCI
797 select PCI_DOMAINS if PCI 805 select PCI_DOMAINS if PCI
798 select PINCTRL
799 select PINCTRL_IMX6Q 806 select PINCTRL_IMX6Q
800 select PL310_ERRATA_588369 if CACHE_PL310 807 select PL310_ERRATA_588369 if CACHE_PL310
801 select PL310_ERRATA_727915 if CACHE_PL310 808 select PL310_ERRATA_727915 if CACHE_PL310
@@ -816,7 +823,6 @@ config SOC_IMX6SL
816 select HAVE_IMX_MMDC 823 select HAVE_IMX_MMDC
817 select HAVE_IMX_SRC 824 select HAVE_IMX_SRC
818 select MFD_SYSCON 825 select MFD_SYSCON
819 select PINCTRL
820 select PINCTRL_IMX6SL 826 select PINCTRL_IMX6SL
821 select PL310_ERRATA_588369 if CACHE_PL310 827 select PL310_ERRATA_588369 if CACHE_PL310
822 select PL310_ERRATA_727915 if CACHE_PL310 828 select PL310_ERRATA_727915 if CACHE_PL310
@@ -830,7 +836,6 @@ config SOC_VF610
830 select CPU_V7 836 select CPU_V7
831 select ARM_GIC 837 select ARM_GIC
832 select CLKSRC_OF 838 select CLKSRC_OF
833 select PINCTRL
834 select PINCTRL_VF610 839 select PINCTRL_VF610
835 select VF_PIT_TIMER 840 select VF_PIT_TIMER
836 select PL310_ERRATA_588369 if CACHE_PL310 841 select PL310_ERRATA_588369 if CACHE_PL310
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 1789e2b31903..befcaf5d0574 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -89,6 +89,7 @@ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
89obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o 89obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
90obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o 90obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
91obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o 91obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
92obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o
92 93
93obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o 94obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
94obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o 95obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
@@ -112,6 +113,7 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
112obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o 113obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
113 114
114obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o 115obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
116obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
115obj-$(CONFIG_SOC_IMX53) += mach-imx53.o 117obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
116 118
117obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o 119obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
index e163ec7a8441..8d1df2e4b7ac 100644
--- a/arch/arm/mach-imx/avic.c
+++ b/arch/arm/mach-imx/avic.c
@@ -54,28 +54,6 @@
54static void __iomem *avic_base; 54static void __iomem *avic_base;
55static struct irq_domain *domain; 55static struct irq_domain *domain;
56 56
57#ifdef CONFIG_MXC_IRQ_PRIOR
58static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
59{
60 struct irq_data *d = irq_get_irq_data(irq);
61 unsigned int temp;
62 unsigned int mask = 0x0F << irq % 8 * 4;
63
64 irq = d->hwirq;
65
66 if (irq >= AVIC_NUM_IRQS)
67 return -EINVAL;
68
69 temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
70 temp &= ~mask;
71 temp |= prio & mask;
72
73 __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
74
75 return 0;
76}
77#endif
78
79#ifdef CONFIG_FIQ 57#ifdef CONFIG_FIQ
80static int avic_set_irq_fiq(unsigned int irq, unsigned int type) 58static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
81{ 59{
@@ -102,9 +80,6 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
102 80
103 81
104static struct mxc_extra_irq avic_extra_irq = { 82static struct mxc_extra_irq avic_extra_irq = {
105#ifdef CONFIG_MXC_IRQ_PRIOR
106 .set_priority = avic_irq_set_priority,
107#endif
108#ifdef CONFIG_FIQ 83#ifdef CONFIG_FIQ
109 .set_irq_fiq = avic_set_irq_fiq, 84 .set_irq_fiq = avic_set_irq_fiq,
110#endif 85#endif
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
index a63e415609a8..a2ecc006b322 100644
--- a/arch/arm/mach-imx/clk-gate2.c
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -72,7 +72,7 @@ static int clk_gate2_is_enabled(struct clk_hw *hw)
72 72
73 reg = readl(gate->reg); 73 reg = readl(gate->reg);
74 74
75 if (((reg >> gate->bit_idx) & 3) == 3) 75 if (((reg >> gate->bit_idx) & 1) == 1)
76 return 1; 76 return 1;
77 77
78 return 0; 78 return 0;
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 2193c834f55c..a4d5e425cd82 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -45,6 +45,8 @@ static struct arm_ahb_div clk_consumer[] = {
45static char hsp_div_532[] = { 4, 8, 3, 0 }; 45static char hsp_div_532[] = { 4, 8, 3, 0 };
46static char hsp_div_400[] = { 3, 6, 3, 0 }; 46static char hsp_div_400[] = { 3, 6, 3, 0 };
47 47
48static struct clk_onecell_data clk_data;
49
48static const char *std_sel[] = {"ppll", "arm"}; 50static const char *std_sel[] = {"ppll", "arm"};
49static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"}; 51static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
50 52
@@ -286,3 +288,15 @@ int __init mx35_clocks_init(void)
286 288
287 return 0; 289 return 0;
288} 290}
291
292static int __init mx35_clocks_init_dt(struct device_node *ccm_node)
293{
294 clk_data.clks = clk;
295 clk_data.clk_num = ARRAY_SIZE(clk);
296 of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);
297
298 mx35_clocks_init();
299
300 return 0;
301}
302CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt);
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index ce37af26ff8c..19fca1fdc6fe 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -12,11 +12,11 @@
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/clkdev.h> 13#include <linux/clkdev.h>
14#include <linux/clk-provider.h> 14#include <linux/clk-provider.h>
15#include <linux/of.h>
16#include <linux/err.h> 15#include <linux/err.h>
17#include <linux/of.h> 16#include <linux/of.h>
18#include <linux/of_address.h> 17#include <linux/of_address.h>
19#include <linux/of_irq.h> 18#include <linux/of_irq.h>
19#include <dt-bindings/clock/imx5-clock.h>
20 20
21#include "crm-regs-imx5.h" 21#include "crm-regs-imx5.h"
22#include "clk.h" 22#include "clk.h"
@@ -83,50 +83,7 @@ static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_
83static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", }; 83static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
84static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", }; 84static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
85 85
86 86static struct clk *clk[IMX5_CLK_END];
87enum imx5_clks {
88 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
89 uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
90 emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
91 usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di_unused,
92 tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
93 uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
94 gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
95 gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
96 esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
97 ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
98 ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
99 ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate,
100 vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate,
101 uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate,
102 esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate,
103 mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate,
104 ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div,
105 ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm,
106 periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
107 tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
108 esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate,
109 usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw,
110 pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
111 ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
112 usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
113 ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel,
114 ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred,
115 ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
116 ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
117 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
118 epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
119 can_sel, can1_serial_gate, can1_ipg_gate,
120 owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
121 cko1_sel, cko1_podf, cko1,
122 cko2_sel, cko2_podf, cko2,
123 srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
124 spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
125 spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
126 ocram, clk_max
127};
128
129static struct clk *clk[clk_max];
130static struct clk_onecell_data clk_data; 87static struct clk_onecell_data clk_data;
131 88
132static void __init mx5_clocks_common_init(unsigned long rate_ckil, 89static void __init mx5_clocks_common_init(unsigned long rate_ckil,
@@ -135,236 +92,296 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
135{ 92{
136 int i; 93 int i;
137 94
138 clk[dummy] = imx_clk_fixed("dummy", 0); 95 clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
139 clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil); 96 clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", rate_ckil);
140 clk[osc] = imx_obtain_fixed_clock("osc", rate_osc); 97 clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", rate_osc);
141 clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1); 98 clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
142 clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2); 99 clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
143 100
144 clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, 101 clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
145 lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); 102 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
146 clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2, 103 clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
147 periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); 104 main_bus_sel, ARRAY_SIZE(main_bus_sel));
148 clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1, 105 clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
149 main_bus_sel, ARRAY_SIZE(main_bus_sel)); 106 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
150 clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1, 107 clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
151 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel)); 108 clk[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
152 clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); 109 clk[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
153 clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); 110 clk[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
154 clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); 111 per_root_sel, ARRAY_SIZE(per_root_sel));
155 clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1, 112 clk[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
156 per_root_sel, ARRAY_SIZE(per_root_sel)); 113 clk[IMX5_CLK_AHB_MAX] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
157 clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3); 114 clk[IMX5_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
158 clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28); 115 clk[IMX5_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
159 clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24); 116 clk[IMX5_CLK_TMAX1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
160 clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26); 117 clk[IMX5_CLK_TMAX2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
161 clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0); 118 clk[IMX5_CLK_TMAX3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
162 clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2); 119 clk[IMX5_CLK_SPBA] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
163 clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4); 120 clk[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
164 clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0); 121 clk[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
165 clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2); 122 clk[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
166 clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3); 123 clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
167 clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3); 124 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
168 clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2, 125 clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
169 standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); 126 clk[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
170 clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3); 127
171 clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3); 128 clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
172 129 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
173 clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2, 130 clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
174 standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); 131 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
175 clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2, 132 clk[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
176 standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); 133 clk[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
177 clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3); 134 clk[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
178 clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3); 135 clk[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
179 clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3); 136 clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
180 clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3); 137 clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
181 clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel)); 138
182 clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel)); 139 clk[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
183 140 emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
184 clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1, 141 clk[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
185 emi_slow_sel, ARRAY_SIZE(emi_slow_sel)); 142 clk[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
186 clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3); 143 clk[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
187 clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3); 144 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
188 clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2, 145 clk[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
189 standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); 146 clk[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
190 clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3); 147 clk[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
191 clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6); 148 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
192 clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2, 149 clk[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
193 standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); 150 clk[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
194 clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3); 151 clk[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
195 clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2); 152 clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
196 clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3); 153 clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
197 clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3); 154 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
198 clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1, 155 clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
199 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str)); 156 clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
200 clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3); 157 clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
201 clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3); 158 clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
202 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30); 159 clk[IMX5_CLK_UART1_PER_GATE] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
203 clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6); 160 clk[IMX5_CLK_UART2_IPG_GATE] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
204 clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8); 161 clk[IMX5_CLK_UART2_PER_GATE] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
205 clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10); 162 clk[IMX5_CLK_UART3_IPG_GATE] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
206 clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12); 163 clk[IMX5_CLK_UART3_PER_GATE] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
207 clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14); 164 clk[IMX5_CLK_I2C1_GATE] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
208 clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16); 165 clk[IMX5_CLK_I2C2_GATE] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
209 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18); 166 clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
210 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20); 167 clk[IMX5_CLK_PWM1_HF_GATE] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
211 clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); 168 clk[IMX5_CLK_PWM2_IPG_GATE] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
212 clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12); 169 clk[IMX5_CLK_PWM2_HF_GATE] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
213 clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); 170 clk[IMX5_CLK_GPT_IPG_GATE] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
214 clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16); 171 clk[IMX5_CLK_GPT_HF_GATE] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
215 clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18); 172 clk[IMX5_CLK_FEC_GATE] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
216 clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20); 173 clk[IMX5_CLK_USBOH3_GATE] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
217 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); 174 clk[IMX5_CLK_USBOH3_PER_GATE] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
218 clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); 175 clk[IMX5_CLK_ESDHC1_IPG_GATE] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
219 clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); 176 clk[IMX5_CLK_ESDHC2_IPG_GATE] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
220 clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0); 177 clk[IMX5_CLK_ESDHC3_IPG_GATE] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
221 clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4); 178 clk[IMX5_CLK_ESDHC4_IPG_GATE] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
222 clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8); 179 clk[IMX5_CLK_SSI1_IPG_GATE] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
223 clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12); 180 clk[IMX5_CLK_SSI2_IPG_GATE] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
224 clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16); 181 clk[IMX5_CLK_SSI3_IPG_GATE] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
225 clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20); 182 clk[IMX5_CLK_ECSPI1_IPG_GATE] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
226 clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24); 183 clk[IMX5_CLK_ECSPI1_PER_GATE] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
227 clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18); 184 clk[IMX5_CLK_ECSPI2_IPG_GATE] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
228 clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20); 185 clk[IMX5_CLK_ECSPI2_PER_GATE] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
229 clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22); 186 clk[IMX5_CLK_CSPI_IPG_GATE] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
230 clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24); 187 clk[IMX5_CLK_SDMA_GATE] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
231 clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26); 188 clk[IMX5_CLK_EMI_FAST_GATE] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
232 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30); 189 clk[IMX5_CLK_EMI_SLOW_GATE] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
233 clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14); 190 clk[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
234 clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16); 191 clk[IMX5_CLK_IPU_GATE] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
235 clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel)); 192 clk[IMX5_CLK_NFC_GATE] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
236 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10); 193 clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
237 clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20); 194 clk[IMX5_CLK_IPU_DI1_GATE] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
238 clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10); 195 clk[IMX5_CLK_GPU3D_SEL] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
239 clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12); 196 clk[IMX5_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
240 clk[gpu3d_s] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel)); 197 clk[IMX5_CLK_GPU3D_GATE] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
241 clk[gpu2d_s] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel)); 198 clk[IMX5_CLK_GARB_GATE] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
242 clk[gpu3d_gate] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2); 199 clk[IMX5_CLK_GPU2D_GATE] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
243 clk[garb_gate] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4); 200 clk[IMX5_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
244 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14); 201 clk[IMX5_CLK_VPU_GATE] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
245 clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel)); 202 clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
246 clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6); 203 clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
247 clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8); 204 clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
248 clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8); 205 clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
249 clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10); 206 clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
250 clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12); 207 clk[IMX5_CLK_GPC_DVFS] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
251 clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14); 208
252 clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24); 209 clk[IMX5_CLK_SSI_APM] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
253 210 clk[IMX5_CLK_SSI1_ROOT_SEL] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
254 clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels)); 211 clk[IMX5_CLK_SSI2_ROOT_SEL] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
255 clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); 212 clk[IMX5_CLK_SSI3_ROOT_SEL] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
256 clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); 213 clk[IMX5_CLK_SSI_EXT1_SEL] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
257 clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels)); 214 clk[IMX5_CLK_SSI_EXT2_SEL] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
258 clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); 215 clk[IMX5_CLK_SSI_EXT1_COM_SEL] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
259 clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); 216 clk[IMX5_CLK_SSI_EXT2_COM_SEL] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
260 clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels)); 217 clk[IMX5_CLK_SSI1_ROOT_PRED] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
261 clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels)); 218 clk[IMX5_CLK_SSI1_ROOT_PODF] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
262 clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3); 219 clk[IMX5_CLK_SSI2_ROOT_PRED] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
263 clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6); 220 clk[IMX5_CLK_SSI2_ROOT_PODF] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
264 clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3); 221 clk[IMX5_CLK_SSI_EXT1_PRED] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
265 clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6); 222 clk[IMX5_CLK_SSI_EXT1_PODF] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
266 clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3); 223 clk[IMX5_CLK_SSI_EXT2_PRED] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
267 clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6); 224 clk[IMX5_CLK_SSI_EXT2_PODF] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
268 clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3); 225 clk[IMX5_CLK_SSI1_ROOT_GATE] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
269 clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6); 226 clk[IMX5_CLK_SSI2_ROOT_GATE] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
270 clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18); 227 clk[IMX5_CLK_SSI3_ROOT_GATE] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
271 clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22); 228 clk[IMX5_CLK_SSI_EXT1_GATE] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
272 clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26); 229 clk[IMX5_CLK_SSI_EXT2_GATE] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
273 clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28); 230 clk[IMX5_CLK_EPIT1_IPG_GATE] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
274 clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30); 231 clk[IMX5_CLK_EPIT1_HF_GATE] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
275 clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2); 232 clk[IMX5_CLK_EPIT2_IPG_GATE] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
276 clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4); 233 clk[IMX5_CLK_EPIT2_HF_GATE] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
277 clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); 234 clk[IMX5_CLK_OWIRE_GATE] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
278 clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8); 235 clk[IMX5_CLK_SRTC_GATE] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
279 clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22); 236 clk[IMX5_CLK_PATA_GATE] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
280 clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28); 237 clk[IMX5_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
281 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0); 238 clk[IMX5_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
282 clk[spdif0_sel] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel)); 239 clk[IMX5_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
283 clk[spdif0_pred] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3); 240 clk[IMX5_CLK_SPDIF0_COM_SEL] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
284 clk[spdif0_podf] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6); 241 spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
285 clk[spdif0_com_s] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1, 242 clk[IMX5_CLK_SPDIF0_GATE] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
286 spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT); 243 clk[IMX5_CLK_SPDIF_IPG_GATE] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
287 clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26); 244 clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
288 clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30); 245 clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
289 246
290 for (i = 0; i < ARRAY_SIZE(clk); i++) 247 for (i = 0; i < ARRAY_SIZE(clk); i++)
291 if (IS_ERR(clk[i])) 248 if (IS_ERR(clk[i]))
292 pr_err("i.MX5 clk %d: register failed with %ld\n", 249 pr_err("i.MX5 clk %d: register failed with %ld\n",
293 i, PTR_ERR(clk[i])); 250 i, PTR_ERR(clk[i]));
294 251
295 clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0"); 252 clk_register_clkdev(clk[IMX5_CLK_GPT_HF_GATE], "per", "imx-gpt.0");
296 clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0"); 253 clk_register_clkdev(clk[IMX5_CLK_GPT_IPG_GATE], "ipg", "imx-gpt.0");
297 clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0"); 254 clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0");
298 clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); 255 clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
299 clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1"); 256 clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1");
300 clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1"); 257 clk_register_clkdev(clk[IMX5_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
301 clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2"); 258 clk_register_clkdev(clk[IMX5_CLK_UART3_PER_GATE], "per", "imx21-uart.2");
302 clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2"); 259 clk_register_clkdev(clk[IMX5_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
303 clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3"); 260 clk_register_clkdev(clk[IMX5_CLK_UART4_PER_GATE], "per", "imx21-uart.3");
304 clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3"); 261 clk_register_clkdev(clk[IMX5_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
305 clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4"); 262 clk_register_clkdev(clk[IMX5_CLK_UART5_PER_GATE], "per", "imx21-uart.4");
306 clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4"); 263 clk_register_clkdev(clk[IMX5_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
307 clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0"); 264 clk_register_clkdev(clk[IMX5_CLK_ECSPI1_PER_GATE], "per", "imx51-ecspi.0");
308 clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0"); 265 clk_register_clkdev(clk[IMX5_CLK_ECSPI1_IPG_GATE], "ipg", "imx51-ecspi.0");
309 clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1"); 266 clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1");
310 clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1"); 267 clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1");
311 clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2"); 268 clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2");
312 clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0"); 269 clk_register_clkdev(clk[IMX5_CLK_PWM1_IPG_GATE], "pwm", "mxc_pwm.0");
313 clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1"); 270 clk_register_clkdev(clk[IMX5_CLK_PWM2_IPG_GATE], "pwm", "mxc_pwm.1");
314 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); 271 clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0");
315 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); 272 clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1");
316 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0"); 273 clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0");
317 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0"); 274 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.0");
318 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0"); 275 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.0");
319 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1"); 276 clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.1");
320 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1"); 277 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.1");
321 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1"); 278 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.1");
322 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2"); 279 clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.2");
323 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2"); 280 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.2");
324 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2"); 281 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.2");
325 clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51"); 282 clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "imx-udc-mx51");
326 clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51"); 283 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "imx-udc-mx51");
327 clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51"); 284 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "imx-udc-mx51");
328 clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand"); 285 clk_register_clkdev(clk[IMX5_CLK_NFC_GATE], NULL, "imx51-nand");
329 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0"); 286 clk_register_clkdev(clk[IMX5_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
330 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1"); 287 clk_register_clkdev(clk[IMX5_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
331 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2"); 288 clk_register_clkdev(clk[IMX5_CLK_SSI3_IPG_GATE], NULL, "imx-ssi.2");
332 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); 289 clk_register_clkdev(clk[IMX5_CLK_SDMA_GATE], NULL, "imx35-sdma");
333 clk_register_clkdev(clk[cpu_podf], NULL, "cpu0"); 290 clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
334 clk_register_clkdev(clk[iim_gate], "iim", NULL); 291 clk_register_clkdev(clk[IMX5_CLK_IIM_GATE], "iim", NULL);
335 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0"); 292 clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.0");
336 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1"); 293 clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.1");
337 clk_register_clkdev(clk[dummy], NULL, "imx-keypad"); 294 clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx-keypad");
338 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0"); 295 clk_register_clkdev(clk[IMX5_CLK_IPU_DI1_GATE], "di1", "imx-tve.0");
339 clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL); 296 clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
340 clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0"); 297 clk_register_clkdev(clk[IMX5_CLK_EPIT1_IPG_GATE], "ipg", "imx-epit.0");
341 clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0"); 298 clk_register_clkdev(clk[IMX5_CLK_EPIT1_HF_GATE], "per", "imx-epit.0");
342 clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1"); 299 clk_register_clkdev(clk[IMX5_CLK_EPIT2_IPG_GATE], "ipg", "imx-epit.1");
343 clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1"); 300 clk_register_clkdev(clk[IMX5_CLK_EPIT2_HF_GATE], "per", "imx-epit.1");
344 301
345 /* Set SDHC parents to be PLL2 */ 302 /* Set SDHC parents to be PLL2 */
346 clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]); 303 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
347 clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]); 304 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
348 305
349 /* move usb phy clk to 24MHz */ 306 /* move usb phy clk to 24MHz */
350 clk_set_parent(clk[usb_phy_sel], clk[osc]); 307 clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
351 308
352 clk_prepare_enable(clk[gpc_dvfs]); 309 clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]);
353 clk_prepare_enable(clk[ahb_max]); /* esdhc3 */ 310 clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */
354 clk_prepare_enable(clk[aips_tz1]); 311 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]);
355 clk_prepare_enable(clk[aips_tz2]); /* fec */ 312 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */
356 clk_prepare_enable(clk[spba]); 313 clk_prepare_enable(clk[IMX5_CLK_SPBA]);
357 clk_prepare_enable(clk[emi_fast_gate]); /* fec */ 314 clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */
358 clk_prepare_enable(clk[emi_slow_gate]); /* eim */ 315 clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */
359 clk_prepare_enable(clk[mipi_hsc1_gate]); 316 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]);
360 clk_prepare_enable(clk[mipi_hsc2_gate]); 317 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]);
361 clk_prepare_enable(clk[mipi_esc_gate]); 318 clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]);
362 clk_prepare_enable(clk[mipi_hsp_gate]); 319 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]);
363 clk_prepare_enable(clk[tmax1]); 320 clk_prepare_enable(clk[IMX5_CLK_TMAX1]);
364 clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */ 321 clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */
365 clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */ 322 clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */
366} 323}
367 324
325static void __init mx50_clocks_init(struct device_node *np)
326{
327 void __iomem *base;
328 unsigned long r;
329 int i, irq;
330
331 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
332 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
333 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
334
335 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
336 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
337 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
338 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
339 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
340 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
341 clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
342 clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
343 clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
344
345 clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
346 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
347 clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
348 clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
349
350 clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
351 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
352 clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
353 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
354
355 for (i = 0; i < ARRAY_SIZE(clk); i++)
356 if (IS_ERR(clk[i]))
357 pr_err("i.MX50 clk %d: register failed with %ld\n",
358 i, PTR_ERR(clk[i]));
359
360 clk_data.clks = clk;
361 clk_data.clk_num = ARRAY_SIZE(clk);
362 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
363
364 mx5_clocks_common_init(0, 0, 0, 0);
365
366 /* set SDHC root clock to 200MHZ*/
367 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
368 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
369
370 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
371 imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1);
372 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
373
374 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
375 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
376
377 np = of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt");
378 base = of_iomap(np, 0);
379 WARN_ON(!base);
380 irq = irq_of_parse_and_map(np, 0);
381 mxc_timer_init(base, irq);
382}
383CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
384
368int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, 385int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
369 unsigned long rate_ckih1, unsigned long rate_ckih2) 386 unsigned long rate_ckih1, unsigned long rate_ckih2)
370{ 387{
@@ -372,38 +389,40 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
372 u32 val; 389 u32 val;
373 struct device_node *np; 390 struct device_node *np;
374 391
375 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE); 392 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
376 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE); 393 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
377 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE); 394 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
378 clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, 395 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
379 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel)); 396 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
380 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, 397 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
381 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel)); 398 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
382 clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, 399 clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
383 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT); 400 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
384 clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, 401 clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
385 mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel)); 402 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
386 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30); 403 clk[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
387 clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3); 404 mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
388 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); 405 clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
389 clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6); 406 clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
390 clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10); 407 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
391 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); 408 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
392 clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0); 409 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
393 clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22); 410 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
394 clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6); 411 clk[IMX5_CLK_USB_PHY_GATE] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
395 clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8); 412 clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
396 clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10); 413 clk[IMX5_CLK_MIPI_HSC1_GATE] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
397 clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12); 414 clk[IMX5_CLK_MIPI_HSC2_GATE] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
398 clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, 415 clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
399 mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel)); 416 clk[IMX5_CLK_MIPI_HSP_GATE] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
400 clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2, 417 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
401 spdif_sel, ARRAY_SIZE(spdif_sel)); 418 mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
402 clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3); 419 clk[IMX5_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
403 clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6); 420 spdif_sel, ARRAY_SIZE(spdif_sel));
404 clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1, 421 clk[IMX5_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
405 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel)); 422 clk[IMX5_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
406 clk[spdif1_gate] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28); 423 clk[IMX5_CLK_SPDIF1_COM_SEL] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
424 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
425 clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
407 426
408 for (i = 0; i < ARRAY_SIZE(clk); i++) 427 for (i = 0; i < ARRAY_SIZE(clk); i++)
409 if (IS_ERR(clk[i])) 428 if (IS_ERR(clk[i]))
@@ -417,37 +436,37 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
417 436
418 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2); 437 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
419 438
420 clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2"); 439 clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
421 clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL); 440 clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
422 clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0"); 441 clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx51-vpu.0");
423 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0"); 442 clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0");
424 clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0"); 443 clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0");
425 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0"); 444 clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0");
426 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0"); 445 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.0");
427 clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0"); 446 clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx51.0");
428 clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1"); 447 clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx51.1");
429 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1"); 448 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.1");
430 clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1"); 449 clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx51.1");
431 clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2"); 450 clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx51.2");
432 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2"); 451 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.2");
433 clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2"); 452 clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx51.2");
434 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3"); 453 clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx51.3");
435 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3"); 454 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.3");
436 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3"); 455 clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx51.3");
437 456
438 /* set the usboh3 parent to pll2_sw */ 457 /* set the usboh3 parent to pll2_sw */
439 clk_set_parent(clk[usboh3_sel], clk[pll2_sw]); 458 clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
440 459
441 /* set SDHC root clock to 166.25MHZ*/ 460 /* set SDHC root clock to 166.25MHZ*/
442 clk_set_rate(clk[esdhc_a_podf], 166250000); 461 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
443 clk_set_rate(clk[esdhc_b_podf], 166250000); 462 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
444 463
445 /* System timer */ 464 /* System timer */
446 mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT); 465 mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
447 466
448 clk_prepare_enable(clk[iim_gate]); 467 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
449 imx_print_silicon_rev("i.MX51", mx51_revision()); 468 imx_print_silicon_rev("i.MX51", mx51_revision());
450 clk_disable_unprepare(clk[iim_gate]); 469 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
451 470
452 /* 471 /*
453 * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no 472 * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
@@ -479,57 +498,59 @@ static void __init mx53_clocks_init(struct device_node *np)
479 unsigned long r; 498 unsigned long r;
480 void __iomem *base; 499 void __iomem *base;
481 500
482 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); 501 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
483 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); 502 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
484 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE); 503 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
485 clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE); 504 clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
486 505
487 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); 506 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
488 clk[ldb_di1_div] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0); 507 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
489 clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1, 508 clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
490 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT); 509 clk[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
491 clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3); 510 clk[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
492 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); 511 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
493 clk[ldb_di0_div] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0); 512 clk[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
494 clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1, 513 clk[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
495 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT); 514 clk[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
496 clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28); 515 clk[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
497 clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30); 516 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
498 clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, 517 clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
499 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel)); 518 clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
500 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, 519 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
501 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel)); 520 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
502 clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, 521 clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
503 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT); 522 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
504 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30); 523 clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
505 clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3); 524 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
506 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); 525 clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
507 clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6); 526 clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
508 clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10); 527 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
509 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); 528 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
510 clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); 529 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
511 clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); 530 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
512 clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2, 531 clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
513 mx53_can_sel, ARRAY_SIZE(mx53_can_sel)); 532 clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
514 clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); 533 clk[IMX5_CLK_CAN_SEL] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
515 clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); 534 mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
516 clk[ocram] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2); 535 clk[IMX5_CLK_CAN1_SERIAL_GATE] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
517 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); 536 clk[IMX5_CLK_CAN1_IPG_GATE] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
518 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); 537 clk[IMX5_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
519 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); 538 clk[IMX5_CLK_CAN2_SERIAL_GATE] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
520 clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2); 539 clk[IMX5_CLK_CAN2_IPG_GATE] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
521 540 clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
522 clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, 541 clk[IMX5_CLK_SATA_GATE] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
523 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel)); 542
524 clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3); 543 clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
525 clk[cko1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7); 544 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
526 545 clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
527 clk[cko2_sel] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5, 546 clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
528 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel)); 547
529 clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); 548 clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
530 clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); 549 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
531 clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, 550 clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
532 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel)); 551 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
552 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
553 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
533 554
534 for (i = 0; i < ARRAY_SIZE(clk); i++) 555 for (i = 0; i < ARRAY_SIZE(clk); i++)
535 if (IS_ERR(clk[i])) 556 if (IS_ERR(clk[i]))
@@ -542,33 +563,36 @@ static void __init mx53_clocks_init(struct device_node *np)
542 563
543 mx5_clocks_common_init(0, 0, 0, 0); 564 mx5_clocks_common_init(0, 0, 0, 0);
544 565
545 clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0"); 566 clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx53-vpu.0");
546 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); 567 clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2");
547 clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0"); 568 clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0");
548 clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0"); 569 clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0");
549 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0"); 570 clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx53.0");
550 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0"); 571 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.0");
551 clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0"); 572 clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx53.0");
552 clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1"); 573 clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx53.1");
553 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1"); 574 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.1");
554 clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1"); 575 clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx53.1");
555 clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2"); 576 clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx53.2");
556 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2"); 577 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.2");
557 clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2"); 578 clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx53.2");
558 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3"); 579 clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx53.3");
559 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3"); 580 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.3");
560 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3"); 581 clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx53.3");
561 582
562 /* set SDHC root clock to 200MHZ*/ 583 /* set SDHC root clock to 200MHZ*/
563 clk_set_rate(clk[esdhc_a_podf], 200000000); 584 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
564 clk_set_rate(clk[esdhc_b_podf], 200000000); 585 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
586
587 /* move can bus clk to 24MHz */
588 clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
565 589
566 clk_prepare_enable(clk[iim_gate]); 590 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
567 imx_print_silicon_rev("i.MX53", mx53_revision()); 591 imx_print_silicon_rev("i.MX53", mx53_revision());
568 clk_disable_unprepare(clk[iim_gate]); 592 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
569 593
570 r = clk_round_rate(clk[usboh3_per_gate], 54000000); 594 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
571 clk_set_rate(clk[usboh3_per_gate], r); 595 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
572 596
573 np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"); 597 np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt");
574 base = of_iomap(np, 0); 598 base = of_iomap(np, 0);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 04cfd0fcb0e5..af2e582d2b74 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -114,7 +114,7 @@ static struct clk *clk[clk_max];
114static struct clk_onecell_data clk_data; 114static struct clk_onecell_data clk_data;
115 115
116static enum mx6q_clks const clks_init_on[] __initconst = { 116static enum mx6q_clks const clks_init_on[] __initconst = {
117 mmdc_ch0_axi, rom, pll1_sys, 117 mmdc_ch0_axi, rom, arm,
118}; 118};
119 119
120static struct clk_div_table clk_enet_ref_table[] = { 120static struct clk_div_table clk_enet_ref_table[] = {
@@ -475,6 +475,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
475 if (ret) 475 if (ret)
476 pr_warn("failed to set up CLKO: %d\n", ret); 476 pr_warn("failed to set up CLKO: %d\n", ret);
477 477
478 /* Audio-related clocks configuration */
479 clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
480
478 /* All existing boards with PCIe use LVDS1 */ 481 /* All existing boards with PCIe use LVDS1 */
479 if (IS_ENABLED(CONFIG_PCI_IMX6)) 482 if (IS_ENABLED(CONFIG_PCI_IMX6))
480 clk_set_parent(clk[lvds1_sel], clk[sata_ref]); 483 clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index c0c4ef55e35b..3781a1853998 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -29,14 +29,14 @@ static const char const *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf"
29static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", }; 29static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
30static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", }; 30static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
31static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", }; 31static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
32static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_post_div", "dummy", }; 32static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
33static const char const *perclk_sels[] = { "ipg", "osc", }; 33static const char const *perclk_sels[] = { "ipg", "osc", };
34static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", }; 34static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
35static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", }; 35static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
36static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", }; 36static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
37static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", }; 37static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
38static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", }; 38static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
39static const char const *audio_sels[] = { "pll4_post_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; 39static const char const *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
40static const char const *ecspi_sels[] = { "pll3_60m", "osc", }; 40static const char const *ecspi_sels[] = { "pll3_60m", "osc", };
41static const char const *uart_sels[] = { "pll3_80m", "osc", }; 41static const char const *uart_sels[] = { "pll3_80m", "osc", };
42 42
@@ -63,7 +63,7 @@ static struct clk_div_table video_div_table[] = {
63 { } 63 { }
64}; 64};
65 65
66static struct clk *clks[IMX6SL_CLK_CLK_END]; 66static struct clk *clks[IMX6SL_CLK_END];
67static struct clk_onecell_data clk_data; 67static struct clk_onecell_data clk_data;
68 68
69static void __init imx6sl_clocks_init(struct device_node *ccm_node) 69static void __init imx6sl_clocks_init(struct device_node *ccm_node)
@@ -104,6 +104,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
104 104
105 /* dev name parent_name flags reg shift width div: flags, div_table lock */ 105 /* dev name parent_name flags reg shift width div: flags, div_table lock */
106 clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); 106 clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
107 clks[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
107 clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); 108 clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
108 clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); 109 clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
109 clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); 110 clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
@@ -232,6 +233,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
232 clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); 233 clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
233 clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); 234 clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
234 clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); 235 clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6);
236 clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
235 clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14); 237 clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14);
236 clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18); 238 clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18);
237 clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20); 239 clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20);
@@ -261,6 +263,9 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
261 clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); 263 clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
262 } 264 }
263 265
266 /* Audio-related clocks configuration */
267 clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
268
264 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt"); 269 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
265 base = of_iomap(np, 0); 270 base = of_iomap(np, 0);
266 WARN_ON(!base); 271 WARN_ON(!base);
diff --git a/arch/arm/mach-imx/clk-pfd.c b/arch/arm/mach-imx/clk-pfd.c
index e2ed4160f329..0b0f6f66ec56 100644
--- a/arch/arm/mach-imx/clk-pfd.c
+++ b/arch/arm/mach-imx/clk-pfd.c
@@ -109,12 +109,23 @@ static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
109 return 0; 109 return 0;
110} 110}
111 111
112static int clk_pfd_is_enabled(struct clk_hw *hw)
113{
114 struct clk_pfd *pfd = to_clk_pfd(hw);
115
116 if (readl_relaxed(pfd->reg) & (1 << ((pfd->idx + 1) * 8 - 1)))
117 return 0;
118
119 return 1;
120}
121
112static const struct clk_ops clk_pfd_ops = { 122static const struct clk_ops clk_pfd_ops = {
113 .enable = clk_pfd_enable, 123 .enable = clk_pfd_enable,
114 .disable = clk_pfd_disable, 124 .disable = clk_pfd_disable,
115 .recalc_rate = clk_pfd_recalc_rate, 125 .recalc_rate = clk_pfd_recalc_rate,
116 .round_rate = clk_pfd_round_rate, 126 .round_rate = clk_pfd_round_rate,
117 .set_rate = clk_pfd_set_rate, 127 .set_rate = clk_pfd_set_rate,
128 .is_enabled = clk_pfd_is_enabled,
118}; 129};
119 130
120struct clk *imx_clk_pfd(const char *name, const char *parent_name, 131struct clk *imx_clk_pfd(const char *name, const char *parent_name,
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index c1eaee346954..d21d14ca46c1 100644
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -18,6 +18,11 @@
18 * 18 *
19 * PLL clock version 1, found on i.MX1/21/25/27/31/35 19 * PLL clock version 1, found on i.MX1/21/25/27/31/35
20 */ 20 */
21
22#define MFN_BITS (10)
23#define MFN_SIGN (BIT(MFN_BITS - 1))
24#define MFN_MASK (MFN_SIGN - 1)
25
21struct clk_pllv1 { 26struct clk_pllv1 {
22 struct clk_hw hw; 27 struct clk_hw hw;
23 void __iomem *base; 28 void __iomem *base;
@@ -25,6 +30,11 @@ struct clk_pllv1 {
25 30
26#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk)) 31#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
27 32
33static inline bool mfn_is_negative(unsigned int mfn)
34{
35 return !cpu_is_mx1() && !cpu_is_mx21() && (mfn & MFN_SIGN);
36}
37
28static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, 38static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
29 unsigned long parent_rate) 39 unsigned long parent_rate)
30{ 40{
@@ -58,10 +68,15 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
58 68
59 /* 69 /*
60 * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit 70 * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
61 * 2's complements number 71 * 2's complements number.
72 * On i.MX27 the bit 9 is the sign bit.
62 */ 73 */
63 if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) 74 if (mfn_is_negative(mfn)) {
64 mfn_abs = 0x400 - mfn; 75 if (cpu_is_mx27())
76 mfn_abs = mfn & MFN_MASK;
77 else
78 mfn_abs = BIT(MFN_BITS) - mfn;
79 }
65 80
66 rate = parent_rate * 2; 81 rate = parent_rate * 2;
67 rate /= pd + 1; 82 rate /= pd + 1;
@@ -70,7 +85,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
70 85
71 do_div(ll, mfd + 1); 86 do_div(ll, mfd + 1);
72 87
73 if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) 88 if (mfn_is_negative(mfn))
74 ll = -ll; 89 ll = -ll;
75 90
76 ll = (rate * mfi) + ll; 91 ll = (rate * mfi) + ll;
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index b169a396d93b..ecd66d8e20b6 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -298,6 +298,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
298 clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0)); 298 clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
299 clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4)); 299 clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
300 300
301 clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4));
302 clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5));
303 clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1));
304 clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2));
305
301 clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); 306 clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
302 clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); 307 clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
303 clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); 308 clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 24a7899e36a8..59c3b9b26bb4 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -108,6 +108,7 @@ void tzic_handle_irq(struct pt_regs *);
108#define imx27_handle_irq avic_handle_irq 108#define imx27_handle_irq avic_handle_irq
109#define imx31_handle_irq avic_handle_irq 109#define imx31_handle_irq avic_handle_irq
110#define imx35_handle_irq avic_handle_irq 110#define imx35_handle_irq avic_handle_irq
111#define imx50_handle_irq tzic_handle_irq
111#define imx51_handle_irq tzic_handle_irq 112#define imx51_handle_irq tzic_handle_irq
112#define imx53_handle_irq tzic_handle_irq 113#define imx53_handle_irq tzic_handle_irq
113 114
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index 818a1cc2fe45..e1e70ef7bc2d 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -25,7 +25,7 @@ static void __init imx31_dt_init(void)
25 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 25 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
26} 26}
27 27
28static const char *imx31_dt_board_compat[] __initdata = { 28static const char *imx31_dt_board_compat[] __initconst = {
29 "fsl,imx31", 29 "fsl,imx31",
30 NULL 30 NULL
31}; 31};
diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c
new file mode 100644
index 000000000000..9d48e0065a63
--- /dev/null
+++ b/arch/arm/mach-imx/imx35-dt.c
@@ -0,0 +1,50 @@
1/*
2 * Copyright 2012 Steffen Trumtrar, Pengutronix
3 *
4 * based on imx27-dt.c
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License version 2 as published by the
8 * Free Software Foundation.
9 */
10
11#include <linux/irq.h>
12#include <linux/irqdomain.h>
13#include <linux/of_irq.h>
14#include <linux/of_platform.h>
15#include <linux/clk-provider.h>
16#include <linux/clocksource.h>
17#include <asm/mach/arch.h>
18#include <asm/mach/time.h>
19#include <asm/hardware/cache-l2x0.h>
20#include "common.h"
21#include "mx35.h"
22
23static void __init imx35_dt_init(void)
24{
25 mxc_arch_reset_init_dt();
26
27 of_platform_populate(NULL, of_default_bus_match_table,
28 NULL, NULL);
29}
30
31static void __init imx35_irq_init(void)
32{
33 imx_init_l2cache();
34 mx35_init_irq();
35}
36
37static const char *imx35_dt_board_compat[] __initconst = {
38 "fsl,imx35",
39 NULL
40};
41
42DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
43 .map_io = mx35_map_io,
44 .init_early = imx35_init_early,
45 .init_irq = imx35_irq_init,
46 .handle_irq = imx35_handle_irq,
47 .init_machine = imx35_dt_init,
48 .dt_compat = imx35_dt_board_compat,
49 .restart = mxc_restart,
50MACHINE_END
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index bece8a65e6f0..0230d78d1413 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -29,7 +29,7 @@ static void __init imx51_dt_init(void)
29 platform_device_register_full(&devinfo); 29 platform_device_register_full(&devinfo);
30} 30}
31 31
32static const char *imx51_dt_board_compat[] __initdata = { 32static const char *imx51_dt_board_compat[] __initconst = {
33 "fsl,imx51", 33 "fsl,imx51",
34 NULL 34 NULL
35}; 35};
diff --git a/arch/arm/mach-imx/irq-common.h b/arch/arm/mach-imx/irq-common.h
index 5b2dabba330f..6e3175dc0c0a 100644
--- a/arch/arm/mach-imx/irq-common.h
+++ b/arch/arm/mach-imx/irq-common.h
@@ -24,7 +24,6 @@
24 24
25struct mxc_extra_irq 25struct mxc_extra_irq
26{ 26{
27 int (*set_priority)(unsigned char irq, unsigned char prio);
28 int (*set_irq_fiq)(unsigned int irq, unsigned int type); 27 int (*set_irq_fiq)(unsigned int irq, unsigned int type);
29}; 28};
30 29
diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c
new file mode 100644
index 000000000000..77b77a92bb5d
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx50.c
@@ -0,0 +1,38 @@
1/*
2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#include <linux/of_platform.h>
15#include <asm/mach/arch.h>
16
17#include "common.h"
18
19static void __init imx50_dt_init(void)
20{
21 mxc_arch_reset_init_dt();
22
23 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
24}
25
26static const char *imx50_dt_board_compat[] __initconst = {
27 "fsl,imx50",
28 NULL
29};
30
31DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
32 .map_io = mx53_map_io,
33 .init_irq = mx53_init_irq,
34 .handle_irq = imx50_handle_irq,
35 .init_machine = imx50_dt_init,
36 .dt_compat = imx50_dt_board_compat,
37 .restart = mxc_restart,
38MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index c9c4d8d96931..65850908a4b4 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -31,7 +31,7 @@ static void __init imx53_dt_init(void)
31 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 31 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
32} 32}
33 33
34static const char *imx53_dt_board_compat[] __initdata = { 34static const char *imx53_dt_board_compat[] __initconst = {
35 "fsl,imx53", 35 "fsl,imx53",
36 NULL 36 NULL
37}; 37};
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index d0cfb225ec9a..d2ea6e60ea7b 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -13,6 +13,7 @@
13#include <linux/clk.h> 13#include <linux/clk.h>
14#include <linux/clkdev.h> 14#include <linux/clkdev.h>
15#include <linux/cpu.h> 15#include <linux/cpu.h>
16#include <linux/delay.h>
16#include <linux/export.h> 17#include <linux/export.h>
17#include <linux/init.h> 18#include <linux/init.h>
18#include <linux/io.h> 19#include <linux/io.h>
@@ -23,6 +24,7 @@
23#include <linux/of_irq.h> 24#include <linux/of_irq.h>
24#include <linux/of_platform.h> 25#include <linux/of_platform.h>
25#include <linux/pm_opp.h> 26#include <linux/pm_opp.h>
27#include <linux/pci.h>
26#include <linux/phy.h> 28#include <linux/phy.h>
27#include <linux/reboot.h> 29#include <linux/reboot.h>
28#include <linux/regmap.h> 30#include <linux/regmap.h>
@@ -78,6 +80,34 @@ static int ksz9031rn_phy_fixup(struct phy_device *dev)
78 return 0; 80 return 0;
79} 81}
80 82
83/*
84 * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
85 * as they are used for slots1-7 PERST#
86 */
87static void ventana_pciesw_early_fixup(struct pci_dev *dev)
88{
89 u32 dw;
90
91 if (!of_machine_is_compatible("gw,ventana"))
92 return;
93
94 if (dev->devfn != 0)
95 return;
96
97 pci_read_config_dword(dev, 0x62c, &dw);
98 dw |= 0xaaa8; // GPIO1-7 outputs
99 pci_write_config_dword(dev, 0x62c, dw);
100
101 pci_read_config_dword(dev, 0x644, &dw);
102 dw |= 0xfe; // GPIO1-7 output high
103 pci_write_config_dword(dev, 0x644, dw);
104
105 msleep(100);
106}
107DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
108DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
109DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
110
81static int ar8031_phy_fixup(struct phy_device *dev) 111static int ar8031_phy_fixup(struct phy_device *dev)
82{ 112{
83 u16 val; 113 u16 val;
@@ -243,7 +273,7 @@ static void __init imx6q_init_irq(void)
243 irqchip_init(); 273 irqchip_init();
244} 274}
245 275
246static const char *imx6q_dt_compat[] __initdata = { 276static const char *imx6q_dt_compat[] __initconst = {
247 "fsl,imx6dl", 277 "fsl,imx6dl",
248 "fsl,imx6q", 278 "fsl,imx6q",
249 NULL, 279 NULL,
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index 2f952e3fcf89..0f4fd4c0ab8e 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -34,6 +34,13 @@ static void __init imx6sl_fec_init(void)
34 } 34 }
35} 35}
36 36
37static void __init imx6sl_init_late(void)
38{
39 /* imx6sl reuses imx6q cpufreq driver */
40 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
41 platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
42}
43
37static void __init imx6sl_init_machine(void) 44static void __init imx6sl_init_machine(void)
38{ 45{
39 struct device *parent; 46 struct device *parent;
@@ -61,7 +68,7 @@ static void __init imx6sl_init_irq(void)
61 irqchip_init(); 68 irqchip_init();
62} 69}
63 70
64static const char *imx6sl_dt_compat[] __initdata = { 71static const char *imx6sl_dt_compat[] __initconst = {
65 "fsl,imx6sl", 72 "fsl,imx6sl",
66 NULL, 73 NULL,
67}; 74};
@@ -70,6 +77,7 @@ DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
70 .map_io = debug_ll_io_init, 77 .map_io = debug_ll_io_init,
71 .init_irq = imx6sl_init_irq, 78 .init_irq = imx6sl_init_irq,
72 .init_machine = imx6sl_init_machine, 79 .init_machine = imx6sl_init_machine,
80 .init_late = imx6sl_init_late,
73 .dt_compat = imx6sl_dt_compat, 81 .dt_compat = imx6sl_dt_compat,
74 .restart = mxc_restart, 82 .restart = mxc_restart,
75MACHINE_END 83MACHINE_END
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
index af0cb8a9dc48..2d8aef5a6efa 100644
--- a/arch/arm/mach-imx/mach-vf610.c
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -26,7 +26,7 @@ static void __init vf610_init_irq(void)
26 irqchip_init(); 26 irqchip_init();
27} 27}
28 28
29static const char *vf610_dt_compat[] __initdata = { 29static const char *vf610_dt_compat[] __initconst = {
30 "fsl,vf610", 30 "fsl,vf610",
31 NULL, 31 NULL,
32}; 32};
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index d1d52600f458..4c112021aa4e 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -89,15 +89,7 @@ void __init imx51_init_early(void)
89 89
90void __init imx53_init_early(void) 90void __init imx53_init_early(void)
91{ 91{
92 struct device_node *np;
93 void __iomem *base;
94
95 mxc_set_cpu_type(MXC_CPU_MX53); 92 mxc_set_cpu_type(MXC_CPU_MX53);
96
97 np = of_find_compatible_node(NULL, NULL, "fsl,imx53-iomuxc");
98 base = of_iomap(np, 0);
99 WARN_ON(!base);
100 mxc_iomux_v3_init(base);
101 imx_src_init(); 93 imx_src_init();
102} 94}
103 95
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index aecd9f8037e0..9d47adc078aa 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -156,10 +156,16 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
156 } 156 }
157 157
158 /* 158 /*
159 * Unmask the always pending IOMUXC interrupt #32 as wakeup source to 159 * ERR007265: CCM: When improper low-power sequence is used,
160 * deassert dsm_request signal, so that we can ensure dsm_request 160 * the SoC enters low power mode before the ARM core executes WFI.
161 * is not asserted when we're going to write CLPCR register to set LPM. 161 *
162 * After setting up LPM bits, we need to mask this wakeup source. 162 * Software workaround:
163 * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
164 * by setting IOMUX_GPR1_GINT.
165 * 2) Software should then unmask IRQ #32 in GPC before setting CCM
166 * Low-Power mode.
167 * 3) Software should mask IRQ #32 right after CCM Low-Power mode
168 * is set (set bits 0-1 of CCM_CLPCR).
163 */ 169 */
164 iomuxc_irq_desc = irq_to_desc(32); 170 iomuxc_irq_desc = irq_to_desc(32);
165 imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data); 171 imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data);
@@ -219,6 +225,8 @@ void __init imx6q_pm_init(void)
219 WARN_ON(!ccm_base); 225 WARN_ON(!ccm_base);
220 226
221 /* 227 /*
228 * This is for SW workaround step #1 of ERR007265, see comments
229 * in imx6q_set_lpm for details of this errata.
222 * Force IOMUXC irq pending, so that the interrupt to GPC can be 230 * Force IOMUXC irq pending, so that the interrupt to GPC can be
223 * used to deassert dsm_request signal when the signal gets 231 * used to deassert dsm_request signal when the signal gets
224 * asserted unexpectedly. 232 * asserted unexpectedly.
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index 9b6638aadeaa..1a3a5f615770 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -111,7 +111,7 @@ static void gpt_irq_acknowledge(void)
111 111
112static void __iomem *sched_clock_reg; 112static void __iomem *sched_clock_reg;
113 113
114static u32 notrace mxc_read_sched_clock(void) 114static u64 notrace mxc_read_sched_clock(void)
115{ 115{
116 return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; 116 return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
117} 117}
@@ -123,7 +123,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
123 123
124 sched_clock_reg = reg; 124 sched_clock_reg = reg;
125 125
126 setup_sched_clock(mxc_read_sched_clock, 32, c); 126 sched_clock_register(mxc_read_sched_clock, 32, c);
127 return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, 127 return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
128 clocksource_mmio_readl_up); 128 clocksource_mmio_readl_up);
129} 129}
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index d50dc2dbfd89..473e21b87364 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -277,7 +277,7 @@ struct amba_pl010_data ap_uart_data = {
277 277
278static unsigned long timer_reload; 278static unsigned long timer_reload;
279 279
280static u32 notrace integrator_read_sched_clock(void) 280static u64 notrace integrator_read_sched_clock(void)
281{ 281{
282 return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE); 282 return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
283} 283}
@@ -298,7 +298,7 @@ static void integrator_clocksource_init(unsigned long inrate,
298 298
299 clocksource_mmio_init(base + TIMER_VALUE, "timer2", 299 clocksource_mmio_init(base + TIMER_VALUE, "timer2",
300 rate, 200, 16, clocksource_mmio_readl_down); 300 rate, 200, 16, clocksource_mmio_readl_down);
301 setup_sched_clock(integrator_read_sched_clock, 16, rate); 301 sched_clock_register(integrator_read_sched_clock, 16, rate);
302} 302}
303 303
304static void __iomem * clkevt_base; 304static void __iomem * clkevt_base;
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index a7906ebedb19..6d68aed6548a 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -475,7 +475,7 @@ void __init ixp4xx_sys_init(void)
475/* 475/*
476 * sched_clock() 476 * sched_clock()
477 */ 477 */
478static u32 notrace ixp4xx_read_sched_clock(void) 478static u64 notrace ixp4xx_read_sched_clock(void)
479{ 479{
480 return *IXP4XX_OSTS; 480 return *IXP4XX_OSTS;
481} 481}
@@ -493,7 +493,7 @@ unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
493EXPORT_SYMBOL(ixp4xx_timer_freq); 493EXPORT_SYMBOL(ixp4xx_timer_freq);
494static void __init ixp4xx_clocksource_init(void) 494static void __init ixp4xx_clocksource_init(void)
495{ 495{
496 setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq); 496 sched_clock_register(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
497 497
498 clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32, 498 clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
499 ixp4xx_clocksource_read); 499 ixp4xx_clocksource_read);
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index f20c53e75ed9..dabc5eee52e7 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -11,6 +11,8 @@ config ARCH_KEYSTONE
11 select ARM_ERRATA_798181 if SMP 11 select ARM_ERRATA_798181 if SMP
12 select COMMON_CLK_KEYSTONE 12 select COMMON_CLK_KEYSTONE
13 select TI_EDMA 13 select TI_EDMA
14 select ARCH_SUPPORTS_BIG_ENDIAN
15 select ZONE_DMA if ARM_LPAE
14 help 16 help
15 Support for boards based on the Texas Instruments Keystone family of 17 Support for boards based on the Texas Instruments Keystone family of
16 SoCs. 18 SoCs.
diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c
index b661c5c2870a..6e6bb7d5ea30 100644
--- a/arch/arm/mach-keystone/keystone.c
+++ b/arch/arm/mach-keystone/keystone.c
@@ -41,6 +41,7 @@ static void __init keystone_init(void)
41 if (WARN_ON(!keystone_rstctrl)) 41 if (WARN_ON(!keystone_rstctrl))
42 pr_warn("ti,keystone-reset iomap error\n"); 42 pr_warn("ti,keystone-reset iomap error\n");
43 43
44 keystone_pm_runtime_init();
44 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 45 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
45} 46}
46 47
@@ -68,6 +69,9 @@ void keystone_restart(enum reboot_mode mode, const char *cmd)
68} 69}
69 70
70DT_MACHINE_START(KEYSTONE, "Keystone") 71DT_MACHINE_START(KEYSTONE, "Keystone")
72#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
73 .dma_zone_size = SZ_2G,
74#endif
71 .smp = smp_ops(keystone_smp_ops), 75 .smp = smp_ops(keystone_smp_ops),
72 .init_machine = keystone_init, 76 .init_machine = keystone_init,
73 .dt_compat = keystone_match, 77 .dt_compat = keystone_match,
diff --git a/arch/arm/mach-keystone/keystone.h b/arch/arm/mach-keystone/keystone.h
index 60bef9dedb12..cd04a1c14de8 100644
--- a/arch/arm/mach-keystone/keystone.h
+++ b/arch/arm/mach-keystone/keystone.h
@@ -18,6 +18,7 @@
18extern struct smp_operations keystone_smp_ops; 18extern struct smp_operations keystone_smp_ops;
19extern void secondary_startup(void); 19extern void secondary_startup(void);
20extern u32 keystone_cpu_smc(u32 command, u32 cpu, u32 addr); 20extern u32 keystone_cpu_smc(u32 command, u32 cpu, u32 addr);
21extern int keystone_pm_runtime_init(void);
21 22
22#endif /* __ASSEMBLER__ */ 23#endif /* __ASSEMBLER__ */
23#endif /* __KEYSTONE_H__ */ 24#endif /* __KEYSTONE_H__ */
diff --git a/arch/arm/mach-keystone/pm_domain.c b/arch/arm/mach-keystone/pm_domain.c
index 29625232e954..ca79ddac38bc 100644
--- a/arch/arm/mach-keystone/pm_domain.c
+++ b/arch/arm/mach-keystone/pm_domain.c
@@ -74,9 +74,7 @@ int __init keystone_pm_runtime_init(void)
74 if (!np) 74 if (!np)
75 return 0; 75 return 0;
76 76
77 of_clk_init(NULL);
78 pm_clk_add_notifier(&platform_bus_type, &platform_domain_notifier); 77 pm_clk_add_notifier(&platform_bus_type, &platform_domain_notifier);
79 78
80 return 0; 79 return 0;
81} 80}
82subsys_initcall(keystone_pm_runtime_init);
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 7ac41e83cfef..024022d91fe3 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -61,7 +61,7 @@ static inline uint32_t timer_read(void)
61 return __raw_readl(mmp_timer_base + TMR_CVWR(1)); 61 return __raw_readl(mmp_timer_base + TMR_CVWR(1));
62} 62}
63 63
64static u32 notrace mmp_read_sched_clock(void) 64static u64 notrace mmp_read_sched_clock(void)
65{ 65{
66 return timer_read(); 66 return timer_read();
67} 67}
@@ -195,7 +195,7 @@ void __init timer_init(int irq)
195{ 195{
196 timer_config(); 196 timer_config();
197 197
198 setup_sched_clock(mmp_read_sched_clock, 32, CLOCK_TICK_RATE); 198 sched_clock_register(mmp_read_sched_clock, 32, CLOCK_TICK_RATE);
199 199
200 ckevt.cpumask = cpumask_of(0); 200 ckevt.cpumask = cpumask_of(0);
201 201
diff --git a/arch/arm/mach-moxart/Kconfig b/arch/arm/mach-moxart/Kconfig
new file mode 100644
index 000000000000..ba470d64493b
--- /dev/null
+++ b/arch/arm/mach-moxart/Kconfig
@@ -0,0 +1,31 @@
1config ARCH_MOXART
2 bool "MOXA ART SoC" if ARCH_MULTI_V4T
3 select CPU_FA526
4 select ARM_DMA_MEM_BUFFERABLE
5 select DMA_OF
6 select USE_OF
7 select CLKSRC_OF
8 select CLKSRC_MMIO
9 select HAVE_CLK
10 select COMMON_CLK
11 select GENERIC_IRQ_CHIP
12 select ARCH_REQUIRE_GPIOLIB
13 select GENERIC_CLOCKEVENTS
14 select PHYLIB if NETDEVICES
15 help
16 Say Y here if you want to run your kernel on hardware with a
17 MOXA ART SoC.
18 The MOXA ART SoC is based on a Faraday FA526 ARMv4 32-bit
19 192 MHz CPU with MMU and 16KB/8KB D/I-cache (UC-7112-LX).
20 Used on models UC-7101, UC-7112/UC-7110, IA240/IA241, IA3341.
21
22if ARCH_MOXART
23
24config MACH_UC7112LX
25 bool "MOXA UC-7112-LX"
26 depends on ARCH_MOXART
27 help
28 Say Y here if you intend to run this kernel on a MOXA
29 UC-7112-LX embedded computer.
30
31endif
diff --git a/arch/arm/mach-moxart/Makefile b/arch/arm/mach-moxart/Makefile
new file mode 100644
index 000000000000..fa022eb10ca1
--- /dev/null
+++ b/arch/arm/mach-moxart/Makefile
@@ -0,0 +1,3 @@
1# Object file lists.
2
3obj-$(CONFIG_MACH_UC7112LX) += moxart.o
diff --git a/arch/arm/mach-moxart/moxart.c b/arch/arm/mach-moxart/moxart.c
new file mode 100644
index 000000000000..86b6d9b57c54
--- /dev/null
+++ b/arch/arm/mach-moxart/moxart.c
@@ -0,0 +1,15 @@
1/*
2 * arch/arm/mach-moxart/moxart.c
3 *
4 * (C) Copyright 2013, Jonas Jensen <jonas.jensen@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 2586c2865874..9625cf378931 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1,12 +1,50 @@
1config ARCH_MSM
2 bool
3
4config ARCH_MSM_DT
5 bool "Qualcomm MSM DT Support" if ARCH_MULTI_V7
6 select ARCH_MSM
7 select ARCH_REQUIRE_GPIOLIB
8 select CLKSRC_OF
9 select GENERIC_CLOCKEVENTS
10 help
11 Support for Qualcomm's devicetree based MSM systems.
12
1if ARCH_MSM 13if ARCH_MSM
2 14
3comment "Qualcomm MSM SoC Type" 15menu "Qualcomm MSM SoC Selection"
4 depends on ARCH_MSM_DT 16 depends on ARCH_MSM_DT
5 17
18config ARCH_MSM8X60
19 bool "Enable support for MSM8X60"
20 select ARM_GIC
21 select CPU_V7
22 select HAVE_SMP
23 select MSM_SCM if SMP
24 select MSM_TIMER
25
26config ARCH_MSM8960
27 bool "Enable support for MSM8960"
28 select ARM_GIC
29 select CPU_V7
30 select HAVE_SMP
31 select MSM_SCM if SMP
32 select MSM_TIMER
33
34config ARCH_MSM8974
35 bool "Enable support for MSM8974"
36 select ARM_GIC
37 select CPU_V7
38 select HAVE_ARM_ARCH_TIMER
39 select HAVE_SMP
40 select MSM_SCM if SMP
41
42endmenu
43
6choice 44choice
7 prompt "Qualcomm MSM SoC Type" 45 prompt "Qualcomm MSM SoC Type"
8 default ARCH_MSM7X00A 46 default ARCH_MSM7X00A
9 depends on !ARCH_MSM_DT 47 depends on ARCH_MSM_NODT
10 48
11config ARCH_MSM7X00A 49config ARCH_MSM7X00A
12 bool "MSM7x00A / MSM7x01A" 50 bool "MSM7x00A / MSM7x01A"
@@ -16,6 +54,7 @@ config ARCH_MSM7X00A
16 select MACH_TROUT if !MACH_HALIBUT 54 select MACH_TROUT if !MACH_HALIBUT
17 select MSM_PROC_COMM 55 select MSM_PROC_COMM
18 select MSM_SMD 56 select MSM_SMD
57 select MSM_TIMER
19 select MSM_SMD_PKG3 58 select MSM_SMD_PKG3
20 59
21config ARCH_MSM7X30 60config ARCH_MSM7X30
@@ -27,6 +66,7 @@ config ARCH_MSM7X30
27 select MSM_GPIOMUX 66 select MSM_GPIOMUX
28 select MSM_PROC_COMM 67 select MSM_PROC_COMM
29 select MSM_SMD 68 select MSM_SMD
69 select MSM_TIMER
30 select MSM_VIC 70 select MSM_VIC
31 71
32config ARCH_QSD8X50 72config ARCH_QSD8X50
@@ -38,32 +78,11 @@ config ARCH_QSD8X50
38 select MSM_GPIOMUX 78 select MSM_GPIOMUX
39 select MSM_PROC_COMM 79 select MSM_PROC_COMM
40 select MSM_SMD 80 select MSM_SMD
81 select MSM_TIMER
41 select MSM_VIC 82 select MSM_VIC
42 83
43endchoice 84endchoice
44 85
45config ARCH_MSM8X60
46 bool "MSM8X60"
47 select ARM_GIC
48 select CPU_V7
49 select GPIO_MSM_V2
50 select HAVE_SMP
51 select MSM_SCM if SMP
52
53config ARCH_MSM8960
54 bool "MSM8960"
55 select ARM_GIC
56 select CPU_V7
57 select HAVE_SMP
58 select GPIO_MSM_V2
59 select MSM_SCM if SMP
60
61config ARCH_MSM_DT
62 def_bool y
63 depends on (ARCH_MSM8X60 || ARCH_MSM8960)
64 select SPARSE_IRQ
65 select USE_OF
66
67config MSM_HAS_DEBUG_UART_HS 86config MSM_HAS_DEBUG_UART_HS
68 bool 87 bool
69 88
@@ -80,7 +99,7 @@ config MSM_VIC
80 bool 99 bool
81 100
82menu "Qualcomm MSM Board Type" 101menu "Qualcomm MSM Board Type"
83 depends on !ARCH_MSM_DT 102 depends on ARCH_MSM_NODT
84 103
85config MACH_HALIBUT 104config MACH_HALIBUT
86 depends on ARCH_MSM 105 depends on ARCH_MSM
@@ -128,10 +147,13 @@ config MSM_SMD
128 147
129config MSM_GPIOMUX 148config MSM_GPIOMUX
130 bool 149 bool
131 depends on !ARCH_MSM_DT
132 help 150 help
133 Support for MSM V1 TLMM GPIOMUX architecture. 151 Support for MSM V1 TLMM GPIOMUX architecture.
134 152
135config MSM_SCM 153config MSM_SCM
136 bool 154 bool
155
156config MSM_TIMER
157 bool
158
137endif 159endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 7ed4c1b2bdd2..8e307a10d3c3 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,5 +1,5 @@
1obj-y += timer.o 1obj-$(CONFIG_MSM_TIMER) += timer.o
2obj-y += clock.o 2obj-$(CONFIG_MSM_PROC_COMM) += clock.o
3 3
4obj-$(CONFIG_MSM_VIC) += irq-vic.o 4obj-$(CONFIG_MSM_VIC) += irq-vic.o
5 5
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 1e9c3383daba..fd1644987534 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -187,7 +187,7 @@ static struct notifier_block msm_timer_cpu_nb = {
187 .notifier_call = msm_timer_cpu_notify, 187 .notifier_call = msm_timer_cpu_notify,
188}; 188};
189 189
190static notrace u32 msm_sched_clock_read(void) 190static u64 notrace msm_sched_clock_read(void)
191{ 191{
192 return msm_clocksource.read(&msm_clocksource); 192 return msm_clocksource.read(&msm_clocksource);
193} 193}
@@ -229,7 +229,7 @@ err:
229 res = clocksource_register_hz(cs, dgt_hz); 229 res = clocksource_register_hz(cs, dgt_hz);
230 if (res) 230 if (res)
231 pr_err("clocksource_register failed\n"); 231 pr_err("clocksource_register failed\n");
232 setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz); 232 sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
233} 233}
234 234
235#ifdef CONFIG_OF 235#ifdef CONFIG_OF
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 6b5f298d6638..a7588cfd0286 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -181,7 +181,7 @@ static __init void omap_init_mpu_timer(unsigned long rate)
181 * --------------------------------------------------------------------------- 181 * ---------------------------------------------------------------------------
182 */ 182 */
183 183
184static u32 notrace omap_mpu_read_sched_clock(void) 184static u64 notrace omap_mpu_read_sched_clock(void)
185{ 185{
186 return ~omap_mpu_timer_read(1); 186 return ~omap_mpu_timer_read(1);
187} 187}
@@ -193,7 +193,7 @@ static void __init omap_init_clocksource(unsigned long rate)
193 "%s: can't register clocksource!\n"; 193 "%s: can't register clocksource!\n";
194 194
195 omap_mpu_timer_start(1, ~0, 1); 195 omap_mpu_timer_start(1, ~0, 1);
196 setup_sched_clock(omap_mpu_read_sched_clock, 32, rate); 196 sched_clock_register(omap_mpu_read_sched_clock, 32, rate);
197 197
198 if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate, 198 if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate,
199 300, 32, clocksource_mmio_readl_down)) 199 300, 32, clocksource_mmio_readl_down))
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 3ca81e0ada5e..ec084d158f64 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -379,7 +379,7 @@ static struct clocksource clocksource_gpt = {
379 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 379 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
380}; 380};
381 381
382static u32 notrace dmtimer_read_sched_clock(void) 382static u64 notrace dmtimer_read_sched_clock(void)
383{ 383{
384 if (clksrc.reserved) 384 if (clksrc.reserved)
385 return __omap_dm_timer_read_counter(&clksrc, 385 return __omap_dm_timer_read_counter(&clksrc,
@@ -471,7 +471,7 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
471 __omap_dm_timer_load_start(&clksrc, 471 __omap_dm_timer_load_start(&clksrc,
472 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 472 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
473 OMAP_TIMER_NONPOSTED); 473 OMAP_TIMER_NONPOSTED);
474 setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); 474 sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
475 475
476 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) 476 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
477 pr_err("Could not register clocksource %s\n", 477 pr_err("Could not register clocksource %s\n",
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 5fdc9c4f05be..fca174e3865d 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -33,7 +33,7 @@
33 * calls to sched_clock() which should always be the case in practice. 33 * calls to sched_clock() which should always be the case in practice.
34 */ 34 */
35 35
36static u32 notrace pxa_read_sched_clock(void) 36static u64 notrace pxa_read_sched_clock(void)
37{ 37{
38 return readl_relaxed(OSCR); 38 return readl_relaxed(OSCR);
39} 39}
@@ -149,7 +149,7 @@ void __init pxa_timer_init(void)
149 writel_relaxed(0, OIER); 149 writel_relaxed(0, OIER);
150 writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR); 150 writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
151 151
152 setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate); 152 sched_clock_register(pxa_read_sched_clock, 32, clock_tick_rate);
153 153
154 ckevt_pxa_osmr0.cpumask = cpumask_of(0); 154 ckevt_pxa_osmr0.cpumask = cpumask_of(0);
155 155
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 713c86cd3d64..6fd4acb8f187 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -20,7 +20,7 @@
20#include <mach/hardware.h> 20#include <mach/hardware.h>
21#include <mach/irqs.h> 21#include <mach/irqs.h>
22 22
23static u32 notrace sa1100_read_sched_clock(void) 23static u64 notrace sa1100_read_sched_clock(void)
24{ 24{
25 return readl_relaxed(OSCR); 25 return readl_relaxed(OSCR);
26} 26}
@@ -122,7 +122,7 @@ void __init sa1100_timer_init(void)
122 writel_relaxed(0, OIER); 122 writel_relaxed(0, OIER);
123 writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR); 123 writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
124 124
125 setup_sched_clock(sa1100_read_sched_clock, 32, 3686400); 125 sched_clock_register(sa1100_read_sched_clock, 32, 3686400);
126 126
127 ckevt_sa1100_osmr0.cpumask = cpumask_of(0); 127 ckevt_sa1100_osmr0.cpumask = cpumask_of(0);
128 128
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index a4a4b75109b2..8c8889211f6d 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -1,6 +1,10 @@
1config ARCH_SHMOBILE
2 bool
3
1config ARCH_SHMOBILE_MULTI 4config ARCH_SHMOBILE_MULTI
2 bool "SH-Mobile Series" if ARCH_MULTI_V7 5 bool "SH-Mobile Series" if ARCH_MULTI_V7
3 depends on MMU 6 depends on MMU
7 select ARCH_SHMOBILE
4 select CPU_V7 8 select CPU_V7
5 select GENERIC_CLOCKEVENTS 9 select GENERIC_CLOCKEVENTS
6 select HAVE_ARM_SCU if SMP 10 select HAVE_ARM_SCU if SMP
@@ -8,6 +12,7 @@ config ARCH_SHMOBILE_MULTI
8 select HAVE_SMP 12 select HAVE_SMP
9 select ARM_GIC 13 select ARM_GIC
10 select MIGHT_HAVE_CACHE_L2X0 14 select MIGHT_HAVE_CACHE_L2X0
15 select MIGHT_HAVE_PCI
11 select NO_IOPORT 16 select NO_IOPORT
12 select PINCTRL 17 select PINCTRL
13 select ARCH_REQUIRE_GPIOLIB 18 select ARCH_REQUIRE_GPIOLIB
@@ -30,7 +35,7 @@ config MACH_KZM9D
30comment "SH-Mobile System Configuration" 35comment "SH-Mobile System Configuration"
31endif 36endif
32 37
33if ARCH_SHMOBILE 38if ARCH_SHMOBILE_LEGACY
34 39
35comment "SH-Mobile System Type" 40comment "SH-Mobile System Type"
36 41
@@ -92,23 +97,31 @@ config ARCH_R8A7790
92 select ARCH_WANT_OPTIONAL_GPIOLIB 97 select ARCH_WANT_OPTIONAL_GPIOLIB
93 select ARM_GIC 98 select ARM_GIC
94 select CPU_V7 99 select CPU_V7
100 select MIGHT_HAVE_PCI
95 select SH_CLK_CPG 101 select SH_CLK_CPG
96 select RENESAS_IRQC 102 select RENESAS_IRQC
97 103
98config ARCH_R8A7791 104config ARCH_R8A7791
99 bool "R-Car M2 (R8A77910)" 105 bool "R-Car M2 (R8A77910)"
106 select ARCH_WANT_OPTIONAL_GPIOLIB
100 select ARM_GIC 107 select ARM_GIC
101 select CPU_V7 108 select CPU_V7
109 select MIGHT_HAVE_PCI
102 select SH_CLK_CPG 110 select SH_CLK_CPG
111 select RENESAS_IRQC
103 112
104config ARCH_EMEV2 113config ARCH_EMEV2
105 bool "Emma Mobile EV2" 114 bool "Emma Mobile EV2"
106 select ARCH_WANT_OPTIONAL_GPIOLIB 115 select ARCH_WANT_OPTIONAL_GPIOLIB
107 select ARM_GIC 116 select ARM_GIC
108 select CPU_V7 117 select CPU_V7
118 select MIGHT_HAVE_PCI
119 select USE_OF
120 select AUTO_ZRELADDR
109 121
110config ARCH_R7S72100 122config ARCH_R7S72100
111 bool "RZ/A1H (R7S72100)" 123 bool "RZ/A1H (R7S72100)"
124 select ARCH_WANT_OPTIONAL_GPIOLIB
112 select ARM_GIC 125 select ARM_GIC
113 select CPU_V7 126 select CPU_V7
114 select SH_CLK_CPG 127 select SH_CLK_CPG
@@ -230,12 +243,7 @@ config MACH_KOELSCH
230 bool "Koelsch board" 243 bool "Koelsch board"
231 depends on ARCH_R8A7791 244 depends on ARCH_R8A7791
232 select USE_OF 245 select USE_OF
233 246 select MICREL_PHY if SH_ETH
234config MACH_KZM9D
235 bool "KZM9D board"
236 depends on ARCH_EMEV2
237 select REGULATOR_FIXED_VOLTAGE if REGULATOR
238 select USE_OF
239 247
240config MACH_KZM9G 248config MACH_KZM9G
241 bool "KZM-A9-GT board" 249 bool "KZM-A9-GT board"
@@ -274,7 +282,7 @@ source "drivers/sh/Kconfig"
274 282
275endif 283endif
276 284
277if ARCH_SHMOBILE || ARCH_SHMOBILE_MULTI 285if ARCH_SHMOBILE
278 286
279menu "Timer and clock configuration" 287menu "Timer and clock configuration"
280 288
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 51db2bcafabf..c7e877499dc2 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -71,7 +71,6 @@ obj-$(CONFIG_MACH_LAGER_REFERENCE) += board-lager-reference.o
71obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o 71obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
72obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o 72obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o
73obj-$(CONFIG_MACH_KOELSCH) += board-koelsch.o 73obj-$(CONFIG_MACH_KOELSCH) += board-koelsch.o
74obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o
75obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o 74obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o
76obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o 75obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o
77endif 76endif
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 391d72a5536c..4f30e3dc0919 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -8,7 +8,6 @@ loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
8loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 8loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
9loadaddr-$(CONFIG_MACH_GENMAI) += 0x8008000 9loadaddr-$(CONFIG_MACH_GENMAI) += 0x8008000
10loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000 10loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000
11loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000
12loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 11loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
13loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 12loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
14loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000 13loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index 3c4995aebd22..37c42dc7f1a8 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -25,6 +25,7 @@
25#include <linux/mmc/sh_mmcif.h> 25#include <linux/mmc/sh_mmcif.h>
26#include <linux/mtd/partitions.h> 26#include <linux/mtd/partitions.h>
27#include <linux/pinctrl/machine.h> 27#include <linux/pinctrl/machine.h>
28#include <linux/platform_data/camera-rcar.h>
28#include <linux/platform_data/usb-rcar-phy.h> 29#include <linux/platform_data/usb-rcar-phy.h>
29#include <linux/platform_device.h> 30#include <linux/platform_device.h>
30#include <linux/regulator/fixed.h> 31#include <linux/regulator/fixed.h>
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
deleted file mode 100644
index 30c2cc695b12..000000000000
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * kzm9d board support
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 * Copyright (C) 2012 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/interrupt.h>
23#include <linux/platform_device.h>
24#include <linux/regulator/fixed.h>
25#include <linux/regulator/machine.h>
26#include <linux/smsc911x.h>
27#include <mach/common.h>
28#include <mach/emev2.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32/* Dummy supplies, where voltage doesn't matter */
33static struct regulator_consumer_supply dummy_supplies[] = {
34 REGULATOR_SUPPLY("vddvario", "smsc911x"),
35 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
36};
37
38/* Ether */
39static struct resource smsc911x_resources[] = {
40 [0] = {
41 .start = 0x20000000,
42 .end = 0x2000ffff,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = EMEV2_GPIO_IRQ(1),
47 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
48 },
49};
50
51static struct smsc911x_platform_config smsc911x_platdata = {
52 .flags = SMSC911X_USE_32BIT,
53 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
54 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
55};
56
57static struct platform_device smsc91x_device = {
58 .name = "smsc911x",
59 .id = -1,
60 .dev = {
61 .platform_data = &smsc911x_platdata,
62 },
63 .num_resources = ARRAY_SIZE(smsc911x_resources),
64 .resource = smsc911x_resources,
65};
66
67static struct platform_device *kzm9d_devices[] __initdata = {
68 &smsc91x_device,
69};
70
71void __init kzm9d_add_standard_devices(void)
72{
73 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
74
75 emev2_add_standard_devices();
76
77 platform_add_devices(kzm9d_devices, ARRAY_SIZE(kzm9d_devices));
78}
79
80static const char *kzm9d_boards_compat_dt[] __initdata = {
81 "renesas,kzm9d",
82 NULL,
83};
84
85DT_MACHINE_START(KZM9D_DT, "kzm9d")
86 .smp = smp_ops(emev2_smp_ops),
87 .map_io = emev2_map_io,
88 .init_early = emev2_init_delay,
89 .init_machine = kzm9d_add_standard_devices,
90 .init_late = shmobile_init_late,
91 .dt_compat = kzm9d_boards_compat_dt,
92MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
index 0814a508fd61..e6ab0cd5b286 100644
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ b/arch/arm/mach-shmobile/clock-r7s72100.c
@@ -27,6 +27,7 @@
27#define FRQCR2 0xfcfe0014 27#define FRQCR2 0xfcfe0014
28#define STBCR3 0xfcfe0420 28#define STBCR3 0xfcfe0420
29#define STBCR4 0xfcfe0424 29#define STBCR4 0xfcfe0424
30#define STBCR9 0xfcfe0438
30 31
31#define PLL_RATE 30 32#define PLL_RATE 30
32 33
@@ -144,10 +145,15 @@ struct clk div4_clks[DIV4_NR] = {
144 | CLK_ENABLE_ON_INIT), 145 | CLK_ENABLE_ON_INIT),
145}; 146};
146 147
147enum { MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, 148enum { MSTP97, MSTP96, MSTP95, MSTP94,
149 MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
148 MSTP33, MSTP_NR }; 150 MSTP33, MSTP_NR };
149 151
150static struct clk mstp_clks[MSTP_NR] = { 152static struct clk mstp_clks[MSTP_NR] = {
153 [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
154 [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
155 [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
156 [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
151 [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */ 157 [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
152 [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */ 158 [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
153 [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */ 159 [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index c826bca4024e..e9a3c6401845 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -585,6 +585,7 @@ static struct clk_lookup lookups[] = {
585 585
586 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), 586 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
587 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), 587 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]),
588 CLKDEV_DEV_ID("fe1f0000.sound", &mstp_clks[MSTP328]),
588 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), 589 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
589 CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), 590 CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]),
590 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), 591 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index fb6af83858e3..dfb0fff4d24c 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -115,6 +115,8 @@ static struct clk *main_clks[] = {
115}; 115};
116 116
117enum { 117enum {
118 MSTP531, MSTP530,
119 MSTP529, MSTP528, MSTP527, MSTP526, MSTP525, MSTP524, MSTP523,
118 MSTP331, 120 MSTP331,
119 MSTP323, MSTP322, MSTP321, 121 MSTP323, MSTP322, MSTP321,
120 MSTP311, MSTP310, 122 MSTP311, MSTP310,
@@ -129,6 +131,15 @@ enum {
129 MSTP_NR }; 131 MSTP_NR };
130 132
131static struct clk mstp_clks[MSTP_NR] = { 133static struct clk mstp_clks[MSTP_NR] = {
134 [MSTP531] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 31, 0), /* SCU0 */
135 [MSTP530] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 30, 0), /* SCU1 */
136 [MSTP529] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 29, 0), /* SCU2 */
137 [MSTP528] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 28, 0), /* SCU3 */
138 [MSTP527] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 27, 0), /* SCU4 */
139 [MSTP526] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 26, 0), /* SCU5 */
140 [MSTP525] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 25, 0), /* SCU6 */
141 [MSTP524] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 24, 0), /* SCU7 */
142 [MSTP523] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 23, 0), /* SCU8 */
132 [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */ 143 [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */
133 [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ 144 [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
134 [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ 145 [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
@@ -173,9 +184,13 @@ static struct clk_lookup lookups[] = {
173 184
174 /* MSTP32 clocks */ 185 /* MSTP32 clocks */
175 CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */ 186 CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */
187 CLKDEV_DEV_ID("ffe4e000.mmcif", &mstp_clks[MSTP331]), /* MMC */
176 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ 188 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
189 CLKDEV_DEV_ID("ffe4c000.sdhi", &mstp_clks[MSTP323]), /* SDHI0 */
177 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ 190 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
191 CLKDEV_DEV_ID("ffe4d000.sdhi", &mstp_clks[MSTP322]), /* SDHI1 */
178 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ 192 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
193 CLKDEV_DEV_ID("ffe4f000.sdhi", &mstp_clks[MSTP321]), /* SDHI2 */
179 CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */ 194 CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */
180 CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ 195 CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */
181 CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ 196 CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
@@ -183,9 +198,13 @@ static struct clk_lookup lookups[] = {
183 CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ 198 CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
184 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */ 199 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */
185 CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ 200 CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
201 CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
186 CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ 202 CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
203 CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */
187 CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ 204 CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
205 CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */
188 CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ 206 CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
207 CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
189 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ 208 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
190 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ 209 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
191 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ 210 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
@@ -195,8 +214,11 @@ static struct clk_lookup lookups[] = {
195 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ 214 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
196 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */ 215 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
197 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ 216 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
217 CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
198 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ 218 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
219 CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */
199 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ 220 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
221 CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
200 CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */ 222 CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */
201 223
202 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]), 224 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]),
@@ -208,6 +230,15 @@ static struct clk_lookup lookups[] = {
208 CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]), 230 CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]),
209 CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]), 231 CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]),
210 CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]), 232 CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]),
233 CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP531]),
234 CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP530]),
235 CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP529]),
236 CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP528]),
237 CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP527]),
238 CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP526]),
239 CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP525]),
240 CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP524]),
241 CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP523]),
211}; 242};
212 243
213void __init r8a7778_clock_init(void) 244void __init r8a7778_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 1f7080fab0a5..b545c8dbb818 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -184,9 +184,13 @@ static struct clk_lookup lookups[] = {
184 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */ 184 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
185 CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP016]), /* TMU02 */ 185 CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP016]), /* TMU02 */
186 CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ 186 CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
187 CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
187 CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ 188 CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
189 CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */
188 CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ 190 CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
191 CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */
189 CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ 192 CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
193 CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
190 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ 194 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
191 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ 195 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
192 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ 196 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
@@ -194,12 +198,19 @@ static struct clk_lookup lookups[] = {
194 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ 198 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
195 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ 199 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
196 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ 200 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
201 CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
197 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ 202 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
203 CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */
198 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ 204 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
205 CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
199 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ 206 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
207 CLKDEV_DEV_ID("ffe4c000.sdhi", &mstp_clks[MSTP323]), /* SDHI0 */
200 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ 208 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
209 CLKDEV_DEV_ID("ffe4d000.sdhi", &mstp_clks[MSTP322]), /* SDHI1 */
201 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ 210 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
211 CLKDEV_DEV_ID("ffe4e000.sdhi", &mstp_clks[MSTP321]), /* SDHI2 */
202 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ 212 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
213 CLKDEV_DEV_ID("ffe4f000.sdhi", &mstp_clks[MSTP320]), /* SDHI3 */
203 CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */ 214 CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */
204}; 215};
205 216
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index fa1b4773677a..30552448b056 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -53,6 +53,7 @@
53#define SMSTPCR7 0xe615014c 53#define SMSTPCR7 0xe615014c
54#define SMSTPCR8 0xe6150990 54#define SMSTPCR8 0xe6150990
55#define SMSTPCR9 0xe6150994 55#define SMSTPCR9 0xe6150994
56#define SMSTPCR10 0xe6150998
56 57
57#define SDCKCR 0xE6150074 58#define SDCKCR 0xE6150074
58#define SD2CKCR 0xE6150078 59#define SD2CKCR 0xE6150078
@@ -182,10 +183,14 @@ static struct clk div6_clks[DIV6_NR] = {
182 183
183/* MSTP */ 184/* MSTP */
184enum { 185enum {
186 MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010,
187 MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
185 MSTP931, MSTP930, MSTP929, MSTP928, 188 MSTP931, MSTP930, MSTP929, MSTP928,
189 MSTP917,
186 MSTP813, 190 MSTP813,
187 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720, 191 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
188 MSTP717, MSTP716, 192 MSTP717, MSTP716,
193 MSTP704,
189 MSTP522, 194 MSTP522,
190 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, 195 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
191 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, 196 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
@@ -194,10 +199,22 @@ enum {
194}; 199};
195 200
196static struct clk mstp_clks[MSTP_NR] = { 201static struct clk mstp_clks[MSTP_NR] = {
197 [MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */ 202 [MSTP1015] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 15, 0), /* SSI0 */
198 [MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */ 203 [MSTP1014] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 14, 0), /* SSI1 */
199 [MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */ 204 [MSTP1013] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 13, 0), /* SSI2 */
200 [MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */ 205 [MSTP1012] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 12, 0), /* SSI3 */
206 [MSTP1011] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 11, 0), /* SSI4 */
207 [MSTP1010] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 10, 0), /* SSI5 */
208 [MSTP1009] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 9, 0), /* SSI6 */
209 [MSTP1008] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 8, 0), /* SSI7 */
210 [MSTP1007] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 7, 0), /* SSI8 */
211 [MSTP1006] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 6, 0), /* SSI9 */
212 [MSTP1005] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 5, 0), /* SSI ALL */
213 [MSTP931] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 31, 0), /* I2C0 */
214 [MSTP930] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 30, 0), /* I2C1 */
215 [MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */
216 [MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */
217 [MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */
201 [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ 218 [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
202 [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */ 219 [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
203 [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */ 220 [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
@@ -208,6 +225,7 @@ static struct clk mstp_clks[MSTP_NR] = {
208 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ 225 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
209 [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ 226 [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
210 [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ 227 [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
228 [MSTP704] = SH_CLK_MSTP32(&mp_clk, SMSTPCR7, 4, 0), /* HSUSB */
211 [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ 229 [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
212 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ 230 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
213 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ 231 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
@@ -262,11 +280,7 @@ static struct clk_lookup lookups[] = {
262 CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), 280 CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
263 281
264 /* MSTP */ 282 /* MSTP */
265 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]), 283 CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]),
266 CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
267 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
268 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
269 CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
270 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), 284 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
271 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), 285 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
272 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), 286 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -278,10 +292,15 @@ static struct clk_lookup lookups[] = {
278 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), 292 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
279 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), 293 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
280 CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]), 294 CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
295 CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
281 CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]), 296 CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
297 CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
282 CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]), 298 CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
299 CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
283 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]), 300 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
301 CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
284 CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), 302 CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
303 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
285 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), 304 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
286 CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), 305 CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
287 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), 306 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
@@ -296,6 +315,27 @@ static struct clk_lookup lookups[] = {
296 CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), 315 CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
297 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), 316 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
298 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), 317 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
318 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
319 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
320
321 /* ICK */
322 CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
323 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
324 CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
325 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
326 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
327 CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
328 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
329 CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
330 CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
331 CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]),
332 CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]),
333 CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]),
334 CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]),
335 CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]),
336 CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]),
337 CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]),
338
299}; 339};
300 340
301#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ 341#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
@@ -321,10 +361,10 @@ void __init r8a7790_clock_init(void)
321 R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66); 361 R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
322 break; 362 break;
323 case MD(14): 363 case MD(14):
324 R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102); 364 R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102);
325 break; 365 break;
326 case MD(13) | MD(14): 366 case MD(13) | MD(14):
327 R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88); 367 R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88);
328 break; 368 break;
329 } 369 }
330 370
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index c9a26f16ce5b..f5461262ee25 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -103,6 +103,7 @@ SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
103SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24); 103SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
104SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024)); 104SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
105SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15); 105SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
106SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
106 107
107static struct clk *main_clks[] = { 108static struct clk *main_clks[] = {
108 &extal_clk, 109 &extal_clk,
@@ -116,12 +117,15 @@ static struct clk *main_clks[] = {
116 &rclk_clk, 117 &rclk_clk,
117 &mp_clk, 118 &mp_clk,
118 &cp_clk, 119 &cp_clk,
120 &zx_clk,
119}; 121};
120 122
121/* MSTP */ 123/* MSTP */
122enum { 124enum {
123 MSTP721, MSTP720, 125 MSTP813,
126 MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
124 MSTP719, MSTP718, MSTP715, MSTP714, 127 MSTP719, MSTP718, MSTP715, MSTP714,
128 MSTP522,
125 MSTP216, MSTP207, MSTP206, 129 MSTP216, MSTP207, MSTP206,
126 MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107, 130 MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107,
127 MSTP124, 131 MSTP124,
@@ -129,12 +133,17 @@ enum {
129}; 133};
130 134
131static struct clk mstp_clks[MSTP_NR] = { 135static struct clk mstp_clks[MSTP_NR] = {
136 [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
137 [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
138 [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
139 [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
132 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ 140 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
133 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ 141 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
134 [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */ 142 [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */
135 [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */ 143 [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */
136 [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */ 144 [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */
137 [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */ 145 [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */
146 [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
138 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ 147 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
139 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ 148 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
140 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ 149 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
@@ -164,6 +173,9 @@ static struct clk_lookup lookups[] = {
164 CLKDEV_CON_ID("peripheral_clk", &hp_clk), 173 CLKDEV_CON_ID("peripheral_clk", &hp_clk),
165 174
166 /* MSTP */ 175 /* MSTP */
176 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7791", &mstp_clks[MSTP726]),
177 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7791", &mstp_clks[MSTP724]),
178 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7791", &mstp_clks[MSTP723]),
167 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ 179 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
168 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ 180 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
169 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */ 181 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */
@@ -180,6 +192,9 @@ static struct clk_lookup lookups[] = {
180 CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */ 192 CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
181 CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */ 193 CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
182 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), 194 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
195 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
196 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
197 CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */
183}; 198};
184 199
185#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ 200#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 2aeec468cf7c..87e349ddba7c 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -652,6 +652,7 @@ static struct clk_lookup lookups[] = {
652 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ 652 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
653 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ 653 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
654 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */ 654 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
655 CLKDEV_DEV_ID("ec230000.sound", &mstp_clks[MSTP328]), /* FSI */
655 CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */ 656 CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
656 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ 657 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
657 CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ 658 CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h
index c2eb7568d9be..fcb142a14e07 100644
--- a/arch/arm/mach-shmobile/include/mach/emev2.h
+++ b/arch/arm/mach-shmobile/include/mach/emev2.h
@@ -3,12 +3,7 @@
3 3
4extern void emev2_map_io(void); 4extern void emev2_map_io(void);
5extern void emev2_init_delay(void); 5extern void emev2_init_delay(void);
6extern void emev2_add_standard_devices(void);
7extern void emev2_clock_init(void); 6extern void emev2_clock_init(void);
8
9#define EMEV2_GPIO_BASE 200
10#define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n))
11
12extern struct smp_operations emev2_smp_ops; 7extern struct smp_operations emev2_smp_ops;
13 8
14#endif /* __ASM_EMEV2_H__ */ 9#endif /* __ASM_EMEV2_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index 441886c9714b..f4076a50e970 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -20,13 +20,50 @@
20#define __ASM_R8A7778_H__ 20#define __ASM_R8A7778_H__
21 21
22#include <linux/sh_eth.h> 22#include <linux/sh_eth.h>
23#include <linux/platform_data/camera-rcar.h>
24 23
25/* HPB-DMA slave IDs */ 24/* HPB-DMA slave IDs */
26enum { 25enum {
27 HPBDMA_SLAVE_DUMMY, 26 HPBDMA_SLAVE_DUMMY,
28 HPBDMA_SLAVE_SDHI0_TX, 27 HPBDMA_SLAVE_SDHI0_TX,
29 HPBDMA_SLAVE_SDHI0_RX, 28 HPBDMA_SLAVE_SDHI0_RX,
29 HPBDMA_SLAVE_SSI0_TX,
30 HPBDMA_SLAVE_SSI0_RX,
31 HPBDMA_SLAVE_SSI1_TX,
32 HPBDMA_SLAVE_SSI1_RX,
33 HPBDMA_SLAVE_SSI2_TX,
34 HPBDMA_SLAVE_SSI2_RX,
35 HPBDMA_SLAVE_SSI3_TX,
36 HPBDMA_SLAVE_SSI3_RX,
37 HPBDMA_SLAVE_SSI4_TX,
38 HPBDMA_SLAVE_SSI4_RX,
39 HPBDMA_SLAVE_SSI5_TX,
40 HPBDMA_SLAVE_SSI5_RX,
41 HPBDMA_SLAVE_SSI6_TX,
42 HPBDMA_SLAVE_SSI6_RX,
43 HPBDMA_SLAVE_SSI7_TX,
44 HPBDMA_SLAVE_SSI7_RX,
45 HPBDMA_SLAVE_SSI8_TX,
46 HPBDMA_SLAVE_SSI8_RX,
47 HPBDMA_SLAVE_HPBIF0_TX,
48 HPBDMA_SLAVE_HPBIF0_RX,
49 HPBDMA_SLAVE_HPBIF1_TX,
50 HPBDMA_SLAVE_HPBIF1_RX,
51 HPBDMA_SLAVE_HPBIF2_TX,
52 HPBDMA_SLAVE_HPBIF2_RX,
53 HPBDMA_SLAVE_HPBIF3_TX,
54 HPBDMA_SLAVE_HPBIF3_RX,
55 HPBDMA_SLAVE_HPBIF4_TX,
56 HPBDMA_SLAVE_HPBIF4_RX,
57 HPBDMA_SLAVE_HPBIF5_TX,
58 HPBDMA_SLAVE_HPBIF5_RX,
59 HPBDMA_SLAVE_HPBIF6_TX,
60 HPBDMA_SLAVE_HPBIF6_RX,
61 HPBDMA_SLAVE_HPBIF7_TX,
62 HPBDMA_SLAVE_HPBIF7_RX,
63 HPBDMA_SLAVE_HPBIF8_TX,
64 HPBDMA_SLAVE_HPBIF8_RX,
65 HPBDMA_SLAVE_USBFUNC_TX,
66 HPBDMA_SLAVE_USBFUNC_RX,
30}; 67};
31 68
32extern void r8a7778_add_standard_devices(void); 69extern void r8a7778_add_standard_devices(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7791.h b/arch/arm/mach-shmobile/include/mach/r8a7791.h
index 051ead3c286e..200fa699f730 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7791.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7791.h
@@ -4,6 +4,7 @@
4void r8a7791_add_standard_devices(void); 4void r8a7791_add_standard_devices(void);
5void r8a7791_add_dt_devices(void); 5void r8a7791_add_dt_devices(void);
6void r8a7791_clock_init(void); 6void r8a7791_clock_init(void);
7void r8a7791_pinmux_init(void);
7void r8a7791_init_early(void); 8void r8a7791_init_early(void);
8extern struct smp_operations r8a7791_smp_ops; 9extern struct smp_operations r8a7791_smp_ops;
9 10
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 3ad531caf4f0..c8f2a1a69a52 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -16,24 +16,15 @@
16 * along with this program; if not, write to the Free Software 16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */ 18 */
19#include <linux/clk-provider.h>
19#include <linux/kernel.h> 20#include <linux/kernel.h>
20#include <linux/init.h> 21#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/platform_device.h>
24#include <linux/platform_data/gpio-em.h>
25#include <linux/of_platform.h> 22#include <linux/of_platform.h>
26#include <linux/delay.h>
27#include <linux/input.h>
28#include <linux/io.h>
29#include <linux/irqchip/arm-gic.h>
30#include <mach/common.h> 23#include <mach/common.h>
31#include <mach/emev2.h> 24#include <mach/emev2.h>
32#include <mach/irqs.h>
33#include <asm/mach-types.h> 25#include <asm/mach-types.h>
34#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
35#include <asm/mach/map.h> 27#include <asm/mach/map.h>
36#include <asm/mach/time.h>
37 28
38static struct map_desc emev2_io_desc[] __initdata = { 29static struct map_desc emev2_io_desc[] __initdata = {
39#ifdef CONFIG_SMP 30#ifdef CONFIG_SMP
@@ -52,150 +43,20 @@ void __init emev2_map_io(void)
52 iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc)); 43 iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc));
53} 44}
54 45
55/* UART */
56static struct resource uart0_resources[] = {
57 DEFINE_RES_MEM(0xe1020000, 0x38),
58 DEFINE_RES_IRQ(40),
59};
60
61static struct resource uart1_resources[] = {
62 DEFINE_RES_MEM(0xe1030000, 0x38),
63 DEFINE_RES_IRQ(41),
64};
65
66static struct resource uart2_resources[] = {
67 DEFINE_RES_MEM(0xe1040000, 0x38),
68 DEFINE_RES_IRQ(42),
69};
70
71static struct resource uart3_resources[] = {
72 DEFINE_RES_MEM(0xe1050000, 0x38),
73 DEFINE_RES_IRQ(43),
74};
75
76#define emev2_register_uart(idx) \
77 platform_device_register_simple("serial8250-em", idx, \
78 uart##idx##_resources, \
79 ARRAY_SIZE(uart##idx##_resources))
80
81/* STI */
82static struct resource sti_resources[] = {
83 DEFINE_RES_MEM(0xe0180000, 0x54),
84 DEFINE_RES_IRQ(157),
85};
86
87#define emev2_register_sti() \
88 platform_device_register_simple("em_sti", 0, \
89 sti_resources, \
90 ARRAY_SIZE(sti_resources))
91
92/* GIO */
93static struct gpio_em_config gio0_config = {
94 .gpio_base = 0,
95 .irq_base = EMEV2_GPIO_IRQ(0),
96 .number_of_pins = 32,
97};
98
99static struct resource gio0_resources[] = {
100 DEFINE_RES_MEM(0xe0050000, 0x2c),
101 DEFINE_RES_MEM(0xe0050040, 0x20),
102 DEFINE_RES_IRQ(99),
103 DEFINE_RES_IRQ(100),
104};
105
106static struct gpio_em_config gio1_config = {
107 .gpio_base = 32,
108 .irq_base = EMEV2_GPIO_IRQ(32),
109 .number_of_pins = 32,
110};
111
112static struct resource gio1_resources[] = {
113 DEFINE_RES_MEM(0xe0050080, 0x2c),
114 DEFINE_RES_MEM(0xe00500c0, 0x20),
115 DEFINE_RES_IRQ(101),
116 DEFINE_RES_IRQ(102),
117};
118
119static struct gpio_em_config gio2_config = {
120 .gpio_base = 64,
121 .irq_base = EMEV2_GPIO_IRQ(64),
122 .number_of_pins = 32,
123};
124
125static struct resource gio2_resources[] = {
126 DEFINE_RES_MEM(0xe0050100, 0x2c),
127 DEFINE_RES_MEM(0xe0050140, 0x20),
128 DEFINE_RES_IRQ(103),
129 DEFINE_RES_IRQ(104),
130};
131
132static struct gpio_em_config gio3_config = {
133 .gpio_base = 96,
134 .irq_base = EMEV2_GPIO_IRQ(96),
135 .number_of_pins = 32,
136};
137
138static struct resource gio3_resources[] = {
139 DEFINE_RES_MEM(0xe0050180, 0x2c),
140 DEFINE_RES_MEM(0xe00501c0, 0x20),
141 DEFINE_RES_IRQ(105),
142 DEFINE_RES_IRQ(106),
143};
144
145static struct gpio_em_config gio4_config = {
146 .gpio_base = 128,
147 .irq_base = EMEV2_GPIO_IRQ(128),
148 .number_of_pins = 31,
149};
150
151static struct resource gio4_resources[] = {
152 DEFINE_RES_MEM(0xe0050200, 0x2c),
153 DEFINE_RES_MEM(0xe0050240, 0x20),
154 DEFINE_RES_IRQ(107),
155 DEFINE_RES_IRQ(108),
156};
157
158#define emev2_register_gio(idx) \
159 platform_device_register_resndata(&platform_bus, "em_gio", \
160 idx, gio##idx##_resources, \
161 ARRAY_SIZE(gio##idx##_resources), \
162 &gio##idx##_config, \
163 sizeof(struct gpio_em_config))
164
165static struct resource pmu_resources[] = {
166 DEFINE_RES_IRQ(152),
167 DEFINE_RES_IRQ(153),
168};
169
170#define emev2_register_pmu() \
171 platform_device_register_simple("arm-pmu", -1, \
172 pmu_resources, \
173 ARRAY_SIZE(pmu_resources))
174
175void __init emev2_add_standard_devices(void)
176{
177 if (!IS_ENABLED(CONFIG_COMMON_CLK))
178 emev2_clock_init();
179
180 emev2_register_uart(0);
181 emev2_register_uart(1);
182 emev2_register_uart(2);
183 emev2_register_uart(3);
184 emev2_register_sti();
185 emev2_register_gio(0);
186 emev2_register_gio(1);
187 emev2_register_gio(2);
188 emev2_register_gio(3);
189 emev2_register_gio(4);
190 emev2_register_pmu();
191}
192
193void __init emev2_init_delay(void) 46void __init emev2_init_delay(void)
194{ 47{
195 shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ 48 shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
196} 49}
197 50
198#ifdef CONFIG_USE_OF 51static void __init emev2_add_standard_devices_dt(void)
52{
53#ifdef CONFIG_COMMON_CLK
54 of_clk_init(NULL);
55#else
56 emev2_clock_init();
57#endif
58 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
59}
199 60
200static const char *emev2_boards_compat_dt[] __initdata = { 61static const char *emev2_boards_compat_dt[] __initdata = {
201 "renesas,emev2", 62 "renesas,emev2",
@@ -206,7 +67,7 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
206 .smp = smp_ops(emev2_smp_ops), 67 .smp = smp_ops(emev2_smp_ops),
207 .map_io = emev2_map_io, 68 .map_io = emev2_map_io,
208 .init_early = emev2_init_delay, 69 .init_early = emev2_init_delay,
70 .init_machine = emev2_add_standard_devices_dt,
71 .init_late = shmobile_init_late,
209 .dt_compat = emev2_boards_compat_dt, 72 .dt_compat = emev2_boards_compat_dt,
210MACHINE_END 73MACHINE_END
211
212#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c
index d4eb509a1c87..9c0b3a9d5f7a 100644
--- a/arch/arm/mach-shmobile/setup-r7s72100.c
+++ b/arch/arm/mach-shmobile/setup-r7s72100.c
@@ -22,52 +22,76 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/of_platform.h> 23#include <linux/of_platform.h>
24#include <linux/serial_sci.h> 24#include <linux/serial_sci.h>
25#include <linux/sh_timer.h>
25#include <mach/common.h> 26#include <mach/common.h>
26#include <mach/irqs.h> 27#include <mach/irqs.h>
27#include <mach/r7s72100.h> 28#include <mach/r7s72100.h>
28#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
29 30
30#define SCIF_DATA(index, baseaddr, irq) \ 31#define R7S72100_SCIF(index, baseaddr, irq) \
31[index] = { \ 32static const struct plat_sci_port scif##index##_platform_data = { \
32 .type = PORT_SCIF, \ 33 .type = PORT_SCIF, \
33 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \ 34 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \
34 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 35 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
35 .scbrr_algo_id = SCBRR_ALGO_2, \
36 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \ 36 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \
37 SCSCR_REIE, \ 37 SCSCR_REIE, \
38 .mapbase = baseaddr, \ 38}; \
39 .irqs = { irq + 1, irq + 2, irq + 3, irq }, \ 39 \
40} 40static struct resource scif##index##_resources[] = { \
41 DEFINE_RES_MEM(baseaddr, 0x100), \
42 DEFINE_RES_IRQ(irq + 1), \
43 DEFINE_RES_IRQ(irq + 2), \
44 DEFINE_RES_IRQ(irq + 3), \
45 DEFINE_RES_IRQ(irq), \
46} \
47
48R7S72100_SCIF(0, 0xe8007000, gic_iid(221));
49R7S72100_SCIF(1, 0xe8007800, gic_iid(225));
50R7S72100_SCIF(2, 0xe8008000, gic_iid(229));
51R7S72100_SCIF(3, 0xe8008800, gic_iid(233));
52R7S72100_SCIF(4, 0xe8009000, gic_iid(237));
53R7S72100_SCIF(5, 0xe8009800, gic_iid(241));
54R7S72100_SCIF(6, 0xe800a000, gic_iid(245));
55R7S72100_SCIF(7, 0xe800a800, gic_iid(249));
41 56
42enum { SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 }; 57#define r7s72100_register_scif(index) \
58 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
59 scif##index##_resources, \
60 ARRAY_SIZE(scif##index##_resources), \
61 &scif##index##_platform_data, \
62 sizeof(scif##index##_platform_data))
43 63
44static const struct plat_sci_port scif[] __initconst = { 64
45 SCIF_DATA(SCIF0, 0xe8007000, gic_iid(221)), /* SCIF0 */ 65static struct sh_timer_config mtu2_0_platform_data __initdata = {
46 SCIF_DATA(SCIF1, 0xe8007800, gic_iid(225)), /* SCIF1 */ 66 .name = "MTU2_0",
47 SCIF_DATA(SCIF2, 0xe8008000, gic_iid(229)), /* SCIF2 */ 67 .timer_bit = 0,
48 SCIF_DATA(SCIF3, 0xe8008800, gic_iid(233)), /* SCIF3 */ 68 .channel_offset = -0x80,
49 SCIF_DATA(SCIF4, 0xe8009000, gic_iid(237)), /* SCIF4 */ 69 .clockevent_rating = 200,
50 SCIF_DATA(SCIF5, 0xe8009800, gic_iid(241)), /* SCIF5 */
51 SCIF_DATA(SCIF6, 0xe800a000, gic_iid(245)), /* SCIF6 */
52 SCIF_DATA(SCIF7, 0xe800a800, gic_iid(249)), /* SCIF7 */
53}; 70};
54 71
55static inline void r7s72100_register_scif(int idx) 72static struct resource mtu2_0_resources[] __initdata = {
56{ 73 DEFINE_RES_MEM(0xfcff0300, 0x27),
57 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], 74 DEFINE_RES_IRQ(gic_iid(139)), /* MTU2 TGI0A */
58 sizeof(struct plat_sci_port)); 75};
59} 76
77#define r7s72100_register_mtu2(idx) \
78 platform_device_register_resndata(&platform_bus, "sh_mtu2", \
79 idx, mtu2_##idx##_resources, \
80 ARRAY_SIZE(mtu2_##idx##_resources), \
81 &mtu2_##idx##_platform_data, \
82 sizeof(struct sh_timer_config))
60 83
61void __init r7s72100_add_dt_devices(void) 84void __init r7s72100_add_dt_devices(void)
62{ 85{
63 r7s72100_register_scif(SCIF0); 86 r7s72100_register_scif(0);
64 r7s72100_register_scif(SCIF1); 87 r7s72100_register_scif(1);
65 r7s72100_register_scif(SCIF2); 88 r7s72100_register_scif(2);
66 r7s72100_register_scif(SCIF3); 89 r7s72100_register_scif(3);
67 r7s72100_register_scif(SCIF4); 90 r7s72100_register_scif(4);
68 r7s72100_register_scif(SCIF5); 91 r7s72100_register_scif(5);
69 r7s72100_register_scif(SCIF6); 92 r7s72100_register_scif(6);
70 r7s72100_register_scif(SCIF7); 93 r7s72100_register_scif(7);
94 r7s72100_register_mtu2(0);
71} 95}
72 96
73void __init r7s72100_init_early(void) 97void __init r7s72100_init_early(void)
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index b0f2749071be..cd36f8078325 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -40,41 +40,39 @@ void __init r8a73a4_pinmux_init(void)
40 ARRAY_SIZE(pfc_resources)); 40 ARRAY_SIZE(pfc_resources));
41} 41}
42 42
43#define SCIF_COMMON(scif_type, baseaddr, irq) \ 43#define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \
44static struct plat_sci_port scif##index##_platform_data = { \
44 .type = scif_type, \ 45 .type = scif_type, \
45 .mapbase = baseaddr, \
46 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 46 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
47 .scbrr_algo_id = SCBRR_ALGO_4, \ 47 .scscr = _scscr, \
48 .irqs = SCIx_IRQ_MUXED(irq) 48}; \
49 49 \
50#define SCIFA_DATA(index, baseaddr, irq) \ 50static struct resource scif##index##_resources[] = { \
51[index] = { \ 51 DEFINE_RES_MEM(baseaddr, 0x100), \
52 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ 52 DEFINE_RES_IRQ(irq), \
53 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
54} 53}
55 54
56#define SCIFB_DATA(index, baseaddr, irq) \ 55#define R8A73A4_SCIFA(index, baseaddr, irq) \
57[index] = { \ 56 R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
58 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ 57 index, baseaddr, irq)
59 .scscr = SCSCR_RE | SCSCR_TE, \
60}
61 58
62enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 }; 59#define R8A73A4_SCIFB(index, baseaddr, irq) \
60 R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
61 index, baseaddr, irq)
63 62
64static const struct plat_sci_port scif[] = { 63R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
65 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ 64R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
66 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ 65R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
67 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ 66R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
68 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ 67R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
69 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ 68R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */
70 SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
71};
72 69
73static inline void r8a73a4_register_scif(int idx) 70#define r8a73a4_register_scif(index) \
74{ 71 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
75 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], 72 scif##index##_resources, \
76 sizeof(struct plat_sci_port)); 73 ARRAY_SIZE(scif##index##_resources), \
77} 74 &scif##index##_platform_data, \
75 sizeof(scif##index##_platform_data))
78 76
79static const struct renesas_irqc_config irqc0_data = { 77static const struct renesas_irqc_config irqc0_data = {
80 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ 78 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
@@ -192,12 +190,12 @@ static struct resource cmt10_resources[] = {
192 190
193void __init r8a73a4_add_dt_devices(void) 191void __init r8a73a4_add_dt_devices(void)
194{ 192{
195 r8a73a4_register_scif(SCIFA0); 193 r8a73a4_register_scif(0);
196 r8a73a4_register_scif(SCIFA1); 194 r8a73a4_register_scif(1);
197 r8a73a4_register_scif(SCIFB0); 195 r8a73a4_register_scif(2);
198 r8a73a4_register_scif(SCIFB1); 196 r8a73a4_register_scif(3);
199 r8a73a4_register_scif(SCIFB2); 197 r8a73a4_register_scif(4);
200 r8a73a4_register_scif(SCIFB3); 198 r8a73a4_register_scif(5);
201 r8a7790_register_cmt(10); 199 r8a7790_register_cmt(10);
202} 200}
203 201
@@ -275,7 +273,7 @@ static const struct sh_dmae_pdata dma_pdata = {
275 273
276static struct resource dma_resources[] = { 274static struct resource dma_resources[] = {
277 DEFINE_RES_MEM(0xe6700020, 0x89e0), 275 DEFINE_RES_MEM(0xe6700020, 0x89e0),
278 DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"), 276 DEFINE_RES_IRQ(gic_spi(220)),
279 { 277 {
280 /* IRQ for channels 0-19 */ 278 /* IRQ for channels 0-19 */
281 .start = gic_spi(200), 279 .start = gic_spi(200),
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index b7d4b2c3bc29..8f3c68101d59 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -203,167 +203,38 @@ static struct platform_device irqpin3_device = {
203 }, 203 },
204}; 204};
205 205
206/* SCIFA0 */ 206/* SCIF */
207static struct plat_sci_port scif0_platform_data = { 207#define R8A7740_SCIF(scif_type, index, baseaddr, irq) \
208 .mapbase = 0xe6c40000, 208static struct plat_sci_port scif##index##_platform_data = { \
209 .flags = UPF_BOOT_AUTOCONF, 209 .type = scif_type, \
210 .scscr = SCSCR_RE | SCSCR_TE, 210 .flags = UPF_BOOT_AUTOCONF, \
211 .scbrr_algo_id = SCBRR_ALGO_4, 211 .scscr = SCSCR_RE | SCSCR_TE, \
212 .type = PORT_SCIFA, 212}; \
213 .irqs = SCIx_IRQ_MUXED(gic_spi(100)), 213 \
214}; 214static struct resource scif##index##_resources[] = { \
215 215 DEFINE_RES_MEM(baseaddr, 0x100), \
216static struct platform_device scif0_device = { 216 DEFINE_RES_IRQ(irq), \
217 .name = "sh-sci", 217}; \
218 .id = 0, 218 \
219 .dev = { 219static struct platform_device scif##index##_device = { \
220 .platform_data = &scif0_platform_data, 220 .name = "sh-sci", \
221 }, 221 .id = index, \
222}; 222 .resource = scif##index##_resources, \
223 223 .num_resources = ARRAY_SIZE(scif##index##_resources), \
224/* SCIFA1 */ 224 .dev = { \
225static struct plat_sci_port scif1_platform_data = { 225 .platform_data = &scif##index##_platform_data, \
226 .mapbase = 0xe6c50000, 226 }, \
227 .flags = UPF_BOOT_AUTOCONF, 227}
228 .scscr = SCSCR_RE | SCSCR_TE,
229 .scbrr_algo_id = SCBRR_ALGO_4,
230 .type = PORT_SCIFA,
231 .irqs = SCIx_IRQ_MUXED(gic_spi(101)),
232};
233
234static struct platform_device scif1_device = {
235 .name = "sh-sci",
236 .id = 1,
237 .dev = {
238 .platform_data = &scif1_platform_data,
239 },
240};
241
242/* SCIFA2 */
243static struct plat_sci_port scif2_platform_data = {
244 .mapbase = 0xe6c60000,
245 .flags = UPF_BOOT_AUTOCONF,
246 .scscr = SCSCR_RE | SCSCR_TE,
247 .scbrr_algo_id = SCBRR_ALGO_4,
248 .type = PORT_SCIFA,
249 .irqs = SCIx_IRQ_MUXED(gic_spi(102)),
250};
251
252static struct platform_device scif2_device = {
253 .name = "sh-sci",
254 .id = 2,
255 .dev = {
256 .platform_data = &scif2_platform_data,
257 },
258};
259
260/* SCIFA3 */
261static struct plat_sci_port scif3_platform_data = {
262 .mapbase = 0xe6c70000,
263 .flags = UPF_BOOT_AUTOCONF,
264 .scscr = SCSCR_RE | SCSCR_TE,
265 .scbrr_algo_id = SCBRR_ALGO_4,
266 .type = PORT_SCIFA,
267 .irqs = SCIx_IRQ_MUXED(gic_spi(103)),
268};
269
270static struct platform_device scif3_device = {
271 .name = "sh-sci",
272 .id = 3,
273 .dev = {
274 .platform_data = &scif3_platform_data,
275 },
276};
277
278/* SCIFA4 */
279static struct plat_sci_port scif4_platform_data = {
280 .mapbase = 0xe6c80000,
281 .flags = UPF_BOOT_AUTOCONF,
282 .scscr = SCSCR_RE | SCSCR_TE,
283 .scbrr_algo_id = SCBRR_ALGO_4,
284 .type = PORT_SCIFA,
285 .irqs = SCIx_IRQ_MUXED(gic_spi(104)),
286};
287
288static struct platform_device scif4_device = {
289 .name = "sh-sci",
290 .id = 4,
291 .dev = {
292 .platform_data = &scif4_platform_data,
293 },
294};
295
296/* SCIFA5 */
297static struct plat_sci_port scif5_platform_data = {
298 .mapbase = 0xe6cb0000,
299 .flags = UPF_BOOT_AUTOCONF,
300 .scscr = SCSCR_RE | SCSCR_TE,
301 .scbrr_algo_id = SCBRR_ALGO_4,
302 .type = PORT_SCIFA,
303 .irqs = SCIx_IRQ_MUXED(gic_spi(105)),
304};
305
306static struct platform_device scif5_device = {
307 .name = "sh-sci",
308 .id = 5,
309 .dev = {
310 .platform_data = &scif5_platform_data,
311 },
312};
313
314/* SCIFA6 */
315static struct plat_sci_port scif6_platform_data = {
316 .mapbase = 0xe6cc0000,
317 .flags = UPF_BOOT_AUTOCONF,
318 .scscr = SCSCR_RE | SCSCR_TE,
319 .scbrr_algo_id = SCBRR_ALGO_4,
320 .type = PORT_SCIFA,
321 .irqs = SCIx_IRQ_MUXED(gic_spi(106)),
322};
323
324static struct platform_device scif6_device = {
325 .name = "sh-sci",
326 .id = 6,
327 .dev = {
328 .platform_data = &scif6_platform_data,
329 },
330};
331
332/* SCIFA7 */
333static struct plat_sci_port scif7_platform_data = {
334 .mapbase = 0xe6cd0000,
335 .flags = UPF_BOOT_AUTOCONF,
336 .scscr = SCSCR_RE | SCSCR_TE,
337 .scbrr_algo_id = SCBRR_ALGO_4,
338 .type = PORT_SCIFA,
339 .irqs = SCIx_IRQ_MUXED(gic_spi(107)),
340};
341
342static struct platform_device scif7_device = {
343 .name = "sh-sci",
344 .id = 7,
345 .dev = {
346 .platform_data = &scif7_platform_data,
347 },
348};
349
350/* SCIFB */
351static struct plat_sci_port scifb_platform_data = {
352 .mapbase = 0xe6c30000,
353 .flags = UPF_BOOT_AUTOCONF,
354 .scscr = SCSCR_RE | SCSCR_TE,
355 .scbrr_algo_id = SCBRR_ALGO_4,
356 .type = PORT_SCIFB,
357 .irqs = SCIx_IRQ_MUXED(gic_spi(108)),
358};
359 228
360static struct platform_device scifb_device = { 229R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
361 .name = "sh-sci", 230R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
362 .id = 8, 231R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
363 .dev = { 232R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
364 .platform_data = &scifb_platform_data, 233R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
365 }, 234R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
366}; 235R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
236R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
237R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
367 238
368/* CMT */ 239/* CMT */
369static struct sh_timer_config cmt10_platform_data = { 240static struct sh_timer_config cmt10_platform_data = {
@@ -528,7 +399,7 @@ static struct platform_device *r8a7740_devices_dt[] __initdata = {
528 &scif5_device, 399 &scif5_device,
529 &scif6_device, 400 &scif6_device,
530 &scif7_device, 401 &scif7_device,
531 &scifb_device, 402 &scif8_device,
532 &cmt10_device, 403 &cmt10_device,
533}; 404};
534 405
@@ -981,7 +852,7 @@ void __init r8a7740_add_standard_devices(void)
981 rmobile_add_device_to_domain("A3SP", &scif5_device); 852 rmobile_add_device_to_domain("A3SP", &scif5_device);
982 rmobile_add_device_to_domain("A3SP", &scif6_device); 853 rmobile_add_device_to_domain("A3SP", &scif6_device);
983 rmobile_add_device_to_domain("A3SP", &scif7_device); 854 rmobile_add_device_to_domain("A3SP", &scif7_device);
984 rmobile_add_device_to_domain("A3SP", &scifb_device); 855 rmobile_add_device_to_domain("A3SP", &scif8_device);
985 rmobile_add_device_to_domain("A3SP", &i2c1_device); 856 rmobile_add_device_to_domain("A3SP", &i2c1_device);
986} 857}
987 858
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 03fcc5974ef9..6d694526e4ca 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -44,24 +44,31 @@
44#include <asm/hardware/cache-l2x0.h> 44#include <asm/hardware/cache-l2x0.h>
45 45
46/* SCIF */ 46/* SCIF */
47#define SCIF_INFO(baseaddr, irq) \ 47#define R8A7778_SCIF(index, baseaddr, irq) \
48{ \ 48static struct plat_sci_port scif##index##_platform_data = { \
49 .mapbase = baseaddr, \
50 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 49 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 50 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
52 .scbrr_algo_id = SCBRR_ALGO_2, \
53 .type = PORT_SCIF, \ 51 .type = PORT_SCIF, \
54 .irqs = SCIx_IRQ_MUXED(irq), \ 52}; \
53 \
54static struct resource scif##index##_resources[] = { \
55 DEFINE_RES_MEM(baseaddr, 0x100), \
56 DEFINE_RES_IRQ(irq), \
55} 57}
56 58
57static struct plat_sci_port scif_platform_data[] __initdata = { 59R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66));
58 SCIF_INFO(0xffe40000, gic_iid(0x66)), 60R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67));
59 SCIF_INFO(0xffe41000, gic_iid(0x67)), 61R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68));
60 SCIF_INFO(0xffe42000, gic_iid(0x68)), 62R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69));
61 SCIF_INFO(0xffe43000, gic_iid(0x69)), 63R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a));
62 SCIF_INFO(0xffe44000, gic_iid(0x6a)), 64R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));
63 SCIF_INFO(0xffe45000, gic_iid(0x6b)), 65
64}; 66#define r8a7778_register_scif(index) \
67 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
68 scif##index##_resources, \
69 ARRAY_SIZE(scif##index##_resources), \
70 &scif##index##_platform_data, \
71 sizeof(scif##index##_platform_data))
65 72
66/* TMU */ 73/* TMU */
67static struct resource sh_tmu0_resources[] __initdata = { 74static struct resource sh_tmu0_resources[] __initdata = {
@@ -287,8 +294,6 @@ static void __init r8a7778_register_hspi(int id)
287 294
288void __init r8a7778_add_dt_devices(void) 295void __init r8a7778_add_dt_devices(void)
289{ 296{
290 int i;
291
292#ifdef CONFIG_CACHE_L2X0 297#ifdef CONFIG_CACHE_L2X0
293 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 298 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
294 if (base) { 299 if (base) {
@@ -300,11 +305,12 @@ void __init r8a7778_add_dt_devices(void)
300 } 305 }
301#endif 306#endif
302 307
303 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) 308 r8a7778_register_scif(0);
304 platform_device_register_data(&platform_bus, "sh-sci", i, 309 r8a7778_register_scif(1);
305 &scif_platform_data[i], 310 r8a7778_register_scif(2);
306 sizeof(struct plat_sci_port)); 311 r8a7778_register_scif(3);
307 312 r8a7778_register_scif(4);
313 r8a7778_register_scif(5);
308 r8a7778_register_tmu(0); 314 r8a7778_register_tmu(0);
309 r8a7778_register_tmu(1); 315 r8a7778_register_tmu(1);
310} 316}
@@ -319,6 +325,52 @@ void __init r8a7778_add_dt_devices(void)
319#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */ 325#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */
320#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ 326#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
321 327
328#define HPBDMA_SSI(_id) \
329{ \
330 .id = HPBDMA_SLAVE_SSI## _id ##_TX, \
331 .addr = 0xffd91008 + (_id * 0x40), \
332 .dcr = HPB_DMAE_DCR_CT | \
333 HPB_DMAE_DCR_DIP | \
334 HPB_DMAE_DCR_SPDS_32BIT | \
335 HPB_DMAE_DCR_DMDL | \
336 HPB_DMAE_DCR_DPDS_32BIT, \
337 .port = _id + (_id << 8), \
338 .dma_ch = (28 + _id), \
339}, { \
340 .id = HPBDMA_SLAVE_SSI## _id ##_RX, \
341 .addr = 0xffd9100c + (_id * 0x40), \
342 .dcr = HPB_DMAE_DCR_CT | \
343 HPB_DMAE_DCR_DIP | \
344 HPB_DMAE_DCR_SMDL | \
345 HPB_DMAE_DCR_SPDS_32BIT | \
346 HPB_DMAE_DCR_DPDS_32BIT, \
347 .port = _id + (_id << 8), \
348 .dma_ch = (28 + _id), \
349}
350
351#define HPBDMA_HPBIF(_id) \
352{ \
353 .id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \
354 .addr = 0xffda0000 + (_id * 0x1000), \
355 .dcr = HPB_DMAE_DCR_CT | \
356 HPB_DMAE_DCR_DIP | \
357 HPB_DMAE_DCR_SPDS_32BIT | \
358 HPB_DMAE_DCR_DMDL | \
359 HPB_DMAE_DCR_DPDS_32BIT, \
360 .port = 0x1111, \
361 .dma_ch = (28 + _id), \
362}, { \
363 .id = HPBDMA_SLAVE_HPBIF## _id ##_RX, \
364 .addr = 0xffda0000 + (_id * 0x1000), \
365 .dcr = HPB_DMAE_DCR_CT | \
366 HPB_DMAE_DCR_DIP | \
367 HPB_DMAE_DCR_SMDL | \
368 HPB_DMAE_DCR_SPDS_32BIT | \
369 HPB_DMAE_DCR_DPDS_32BIT, \
370 .port = 0x1111, \
371 .dma_ch = (28 + _id), \
372}
373
322static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { 374static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
323 { 375 {
324 .id = HPBDMA_SLAVE_SDHI0_TX, 376 .id = HPBDMA_SLAVE_SDHI0_TX,
@@ -348,12 +400,86 @@ static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
348 .port = 0x0D0C, 400 .port = 0x0D0C,
349 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 401 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
350 .dma_ch = 22, 402 .dma_ch = 22,
403 }, {
404 .id = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */
405 .addr = 0xffe60018,
406 .dcr = HPB_DMAE_DCR_SPDS_32BIT |
407 HPB_DMAE_DCR_DMDL |
408 HPB_DMAE_DCR_DPDS_32BIT,
409 .port = 0x0000,
410 .dma_ch = 14,
411 }, {
412 .id = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */
413 .addr = 0xffe6001c,
414 .dcr = HPB_DMAE_DCR_SMDL |
415 HPB_DMAE_DCR_SPDS_32BIT |
416 HPB_DMAE_DCR_DPDS_32BIT,
417 .port = 0x0101,
418 .dma_ch = 15,
351 }, 419 },
420
421 HPBDMA_SSI(0),
422 HPBDMA_SSI(1),
423 HPBDMA_SSI(2),
424 HPBDMA_SSI(3),
425 HPBDMA_SSI(4),
426 HPBDMA_SSI(5),
427 HPBDMA_SSI(6),
428 HPBDMA_SSI(7),
429 HPBDMA_SSI(8),
430
431 HPBDMA_HPBIF(0),
432 HPBDMA_HPBIF(1),
433 HPBDMA_HPBIF(2),
434 HPBDMA_HPBIF(3),
435 HPBDMA_HPBIF(4),
436 HPBDMA_HPBIF(5),
437 HPBDMA_HPBIF(6),
438 HPBDMA_HPBIF(7),
439 HPBDMA_HPBIF(8),
352}; 440};
353 441
354static const struct hpb_dmae_channel hpb_dmae_channels[] = { 442static const struct hpb_dmae_channel hpb_dmae_channels[] = {
443 HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */
444 HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */
355 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ 445 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
356 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ 446 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
447 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX), /* ch. 28 */
448 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX), /* ch. 28 */
449 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */
450 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */
451 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX), /* ch. 29 */
452 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX), /* ch. 29 */
453 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */
454 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */
455 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX), /* ch. 30 */
456 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX), /* ch. 30 */
457 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */
458 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */
459 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX), /* ch. 31 */
460 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX), /* ch. 31 */
461 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */
462 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */
463 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX), /* ch. 32 */
464 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX), /* ch. 32 */
465 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */
466 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */
467 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX), /* ch. 33 */
468 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX), /* ch. 33 */
469 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */
470 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */
471 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX), /* ch. 34 */
472 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX), /* ch. 34 */
473 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */
474 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */
475 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX), /* ch. 35 */
476 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX), /* ch. 35 */
477 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */
478 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */
479 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX), /* ch. 36 */
480 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX), /* ch. 36 */
481 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */
482 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */
357}; 483};
358 484
359static struct hpb_dmae_pdata dma_platform_data __initdata = { 485static struct hpb_dmae_pdata dma_platform_data __initdata = {
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 8f9453152fb9..8e860b36997a 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -188,107 +188,35 @@ void __init r8a7779_pinmux_init(void)
188 ARRAY_SIZE(r8a7779_pinctrl_devices)); 188 ARRAY_SIZE(r8a7779_pinctrl_devices));
189} 189}
190 190
191static struct plat_sci_port scif0_platform_data = { 191/* SCIF */
192 .mapbase = 0xffe40000, 192#define R8A7779_SCIF(index, baseaddr, irq) \
193 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 193static struct plat_sci_port scif##index##_platform_data = { \
194 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 194 .type = PORT_SCIF, \
195 .scbrr_algo_id = SCBRR_ALGO_2, 195 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
196 .type = PORT_SCIF, 196 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
197 .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)), 197}; \
198}; 198 \
199 199static struct resource scif##index##_resources[] = { \
200static struct platform_device scif0_device = { 200 DEFINE_RES_MEM(baseaddr, 0x100), \
201 .name = "sh-sci", 201 DEFINE_RES_IRQ(irq), \
202 .id = 0, 202}; \
203 .dev = { 203 \
204 .platform_data = &scif0_platform_data, 204static struct platform_device scif##index##_device = { \
205 }, 205 .name = "sh-sci", \
206}; 206 .id = index, \
207 207 .resource = scif##index##_resources, \
208static struct plat_sci_port scif1_platform_data = { 208 .num_resources = ARRAY_SIZE(scif##index##_resources), \
209 .mapbase = 0xffe41000, 209 .dev = { \
210 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 210 .platform_data = &scif##index##_platform_data, \
211 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 211 }, \
212 .scbrr_algo_id = SCBRR_ALGO_2, 212}
213 .type = PORT_SCIF,
214 .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)),
215};
216
217static struct platform_device scif1_device = {
218 .name = "sh-sci",
219 .id = 1,
220 .dev = {
221 .platform_data = &scif1_platform_data,
222 },
223};
224
225static struct plat_sci_port scif2_platform_data = {
226 .mapbase = 0xffe42000,
227 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
228 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
229 .scbrr_algo_id = SCBRR_ALGO_2,
230 .type = PORT_SCIF,
231 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)),
232};
233
234static struct platform_device scif2_device = {
235 .name = "sh-sci",
236 .id = 2,
237 .dev = {
238 .platform_data = &scif2_platform_data,
239 },
240};
241
242static struct plat_sci_port scif3_platform_data = {
243 .mapbase = 0xffe43000,
244 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
245 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
246 .scbrr_algo_id = SCBRR_ALGO_2,
247 .type = PORT_SCIF,
248 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)),
249};
250
251static struct platform_device scif3_device = {
252 .name = "sh-sci",
253 .id = 3,
254 .dev = {
255 .platform_data = &scif3_platform_data,
256 },
257};
258
259static struct plat_sci_port scif4_platform_data = {
260 .mapbase = 0xffe44000,
261 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
262 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
263 .scbrr_algo_id = SCBRR_ALGO_2,
264 .type = PORT_SCIF,
265 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)),
266};
267
268static struct platform_device scif4_device = {
269 .name = "sh-sci",
270 .id = 4,
271 .dev = {
272 .platform_data = &scif4_platform_data,
273 },
274};
275
276static struct plat_sci_port scif5_platform_data = {
277 .mapbase = 0xffe45000,
278 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
279 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
280 .scbrr_algo_id = SCBRR_ALGO_2,
281 .type = PORT_SCIF,
282 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)),
283};
284 213
285static struct platform_device scif5_device = { 214R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
286 .name = "sh-sci", 215R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
287 .id = 5, 216R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
288 .dev = { 217R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
289 .platform_data = &scif5_platform_data, 218R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
290 }, 219R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
291};
292 220
293/* TMU */ 221/* TMU */
294static struct sh_timer_config tmu00_platform_data = { 222static struct sh_timer_config tmu00_platform_data = {
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 3543c3bacb75..6ab37aa1e919 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -67,6 +67,27 @@ R8A7790_GPIO(5);
67 &r8a7790_gpio##idx##_platform_data, \ 67 &r8a7790_gpio##idx##_platform_data, \
68 sizeof(r8a7790_gpio##idx##_platform_data)) 68 sizeof(r8a7790_gpio##idx##_platform_data))
69 69
70static struct resource i2c_resources[] __initdata = {
71 /* I2C0 */
72 DEFINE_RES_MEM(0xE6508000, 0x40),
73 DEFINE_RES_IRQ(gic_spi(287)),
74 /* I2C1 */
75 DEFINE_RES_MEM(0xE6518000, 0x40),
76 DEFINE_RES_IRQ(gic_spi(288)),
77 /* I2C2 */
78 DEFINE_RES_MEM(0xE6530000, 0x40),
79 DEFINE_RES_IRQ(gic_spi(286)),
80 /* I2C3 */
81 DEFINE_RES_MEM(0xE6540000, 0x40),
82 DEFINE_RES_IRQ(gic_spi(290)),
83
84};
85
86#define r8a7790_register_i2c(idx) \
87 platform_device_register_simple( \
88 "i2c-rcar_gen2", idx, \
89 i2c_resources + (2 * idx), 2); \
90
70void __init r8a7790_pinmux_init(void) 91void __init r8a7790_pinmux_init(void)
71{ 92{
72 r8a7790_register_pfc(); 93 r8a7790_register_pfc();
@@ -76,63 +97,57 @@ void __init r8a7790_pinmux_init(void)
76 r8a7790_register_gpio(3); 97 r8a7790_register_gpio(3);
77 r8a7790_register_gpio(4); 98 r8a7790_register_gpio(4);
78 r8a7790_register_gpio(5); 99 r8a7790_register_gpio(5);
100 r8a7790_register_i2c(0);
101 r8a7790_register_i2c(1);
102 r8a7790_register_i2c(2);
103 r8a7790_register_i2c(3);
79} 104}
80 105
81#define SCIF_COMMON(scif_type, baseaddr, irq) \ 106#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
82 .type = scif_type, \ 107static struct plat_sci_port scif##index##_platform_data = { \
83 .mapbase = baseaddr, \ 108 .type = scif_type, \
84 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 109 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
85 .irqs = SCIx_IRQ_MUXED(irq) 110 .scscr = _scscr, \
86 111}; \
87#define SCIFA_DATA(index, baseaddr, irq) \ 112 \
88[index] = { \ 113static struct resource scif##index##_resources[] = { \
89 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ 114 DEFINE_RES_MEM(baseaddr, 0x100), \
90 .scbrr_algo_id = SCBRR_ALGO_4, \ 115 DEFINE_RES_IRQ(irq), \
91 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
92}
93
94#define SCIFB_DATA(index, baseaddr, irq) \
95[index] = { \
96 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
97 .scbrr_algo_id = SCBRR_ALGO_4, \
98 .scscr = SCSCR_RE | SCSCR_TE, \
99}
100
101#define SCIF_DATA(index, baseaddr, irq) \
102[index] = { \
103 SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
104 .scbrr_algo_id = SCBRR_ALGO_2, \
105 .scscr = SCSCR_RE | SCSCR_TE, \
106}
107
108#define HSCIF_DATA(index, baseaddr, irq) \
109[index] = { \
110 SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
111 .scbrr_algo_id = SCBRR_ALGO_6, \
112 .scscr = SCSCR_RE | SCSCR_TE, \
113} 116}
114 117
115enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, 118#define R8A7790_SCIF(index, baseaddr, irq) \
116 HSCIF0, HSCIF1 }; 119 __R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \
117 120 index, baseaddr, irq)
118static const struct plat_sci_port scif[] __initconst = { 121
119 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ 122#define R8A7790_SCIFA(index, baseaddr, irq) \
120 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ 123 __R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
121 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ 124 index, baseaddr, irq)
122 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ 125
123 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ 126#define R8A7790_SCIFB(index, baseaddr, irq) \
124 SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ 127 __R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
125 SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ 128 index, baseaddr, irq)
126 SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ 129
127 HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */ 130#define R8A7790_HSCIF(index, baseaddr, irq) \
128 HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */ 131 __R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \
129}; 132 index, baseaddr, irq)
130 133
131static inline void r8a7790_register_scif(int idx) 134R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
132{ 135R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
133 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], 136R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
134 sizeof(struct plat_sci_port)); 137R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
135} 138R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
139R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
140R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
141R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
142R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
143R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */
144
145#define r8a7790_register_scif(index) \
146 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
147 scif##index##_resources, \
148 ARRAY_SIZE(scif##index##_resources), \
149 &scif##index##_platform_data, \
150 sizeof(scif##index##_platform_data))
136 151
137static const struct renesas_irqc_config irqc0_data __initconst = { 152static const struct renesas_irqc_config irqc0_data __initconst = {
138 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 153 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
@@ -185,16 +200,16 @@ static const struct resource cmt00_resources[] __initconst = {
185 200
186void __init r8a7790_add_dt_devices(void) 201void __init r8a7790_add_dt_devices(void)
187{ 202{
188 r8a7790_register_scif(SCIFA0); 203 r8a7790_register_scif(0);
189 r8a7790_register_scif(SCIFA1); 204 r8a7790_register_scif(1);
190 r8a7790_register_scif(SCIFB0); 205 r8a7790_register_scif(2);
191 r8a7790_register_scif(SCIFB1); 206 r8a7790_register_scif(3);
192 r8a7790_register_scif(SCIFB2); 207 r8a7790_register_scif(4);
193 r8a7790_register_scif(SCIFA2); 208 r8a7790_register_scif(5);
194 r8a7790_register_scif(SCIF0); 209 r8a7790_register_scif(6);
195 r8a7790_register_scif(SCIF1); 210 r8a7790_register_scif(7);
196 r8a7790_register_scif(HSCIF0); 211 r8a7790_register_scif(8);
197 r8a7790_register_scif(HSCIF1); 212 r8a7790_register_scif(9);
198 r8a7790_register_cmt(00); 213 r8a7790_register_cmt(00);
199} 214}
200 215
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c
index d9393d61ee27..e28404e43860 100644
--- a/arch/arm/mach-shmobile/setup-r8a7791.c
+++ b/arch/arm/mach-shmobile/setup-r8a7791.c
@@ -22,6 +22,7 @@
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/kernel.h> 23#include <linux/kernel.h>
24#include <linux/of_platform.h> 24#include <linux/of_platform.h>
25#include <linux/platform_data/gpio-rcar.h>
25#include <linux/platform_data/irq-renesas-irqc.h> 26#include <linux/platform_data/irq-renesas-irqc.h>
26#include <linux/serial_sci.h> 27#include <linux/serial_sci.h>
27#include <linux/sh_timer.h> 28#include <linux/sh_timer.h>
@@ -31,66 +32,101 @@
31#include <mach/rcar-gen2.h> 32#include <mach/rcar-gen2.h>
32#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
33 34
34#define SCIF_COMMON(scif_type, baseaddr, irq) \ 35static const struct resource pfc_resources[] __initconst = {
35 .type = scif_type, \ 36 DEFINE_RES_MEM(0xe6060000, 0x250),
36 .mapbase = baseaddr, \ 37};
37 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
38 .irqs = SCIx_IRQ_MUXED(irq)
39
40#define SCIFA_DATA(index, baseaddr, irq) \
41[index] = { \
42 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
43 .scbrr_algo_id = SCBRR_ALGO_4, \
44 .scscr = SCSCR_RE | SCSCR_TE, \
45}
46
47#define SCIFB_DATA(index, baseaddr, irq) \
48[index] = { \
49 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
50 .scbrr_algo_id = SCBRR_ALGO_4, \
51 .scscr = SCSCR_RE | SCSCR_TE, \
52}
53 38
54#define SCIF_DATA(index, baseaddr, irq) \ 39#define r8a7791_register_pfc() \
55[index] = { \ 40 platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \
56 SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ 41 ARRAY_SIZE(pfc_resources))
57 .scbrr_algo_id = SCBRR_ALGO_2, \ 42
58 .scscr = SCSCR_RE | SCSCR_TE, \ 43#define R8A7791_GPIO(idx, base, nr) \
44static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \
45 DEFINE_RES_MEM((base), 0x50), \
46 DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
47}; \
48 \
49static const struct gpio_rcar_config \
50r8a7791_gpio##idx##_platform_data __initconst = { \
51 .gpio_base = 32 * (idx), \
52 .irq_base = 0, \
53 .number_of_pins = (nr), \
54 .pctl_name = "pfc-r8a7791", \
55 .has_both_edge_trigger = 1, \
56}; \
57
58R8A7791_GPIO(0, 0xe6050000, 32);
59R8A7791_GPIO(1, 0xe6051000, 32);
60R8A7791_GPIO(2, 0xe6052000, 32);
61R8A7791_GPIO(3, 0xe6053000, 32);
62R8A7791_GPIO(4, 0xe6054000, 32);
63R8A7791_GPIO(5, 0xe6055000, 32);
64R8A7791_GPIO(6, 0xe6055400, 32);
65R8A7791_GPIO(7, 0xe6055800, 26);
66
67#define r8a7791_register_gpio(idx) \
68 platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
69 r8a7791_gpio##idx##_resources, \
70 ARRAY_SIZE(r8a7791_gpio##idx##_resources), \
71 &r8a7791_gpio##idx##_platform_data, \
72 sizeof(r8a7791_gpio##idx##_platform_data))
73
74void __init r8a7791_pinmux_init(void)
75{
76 r8a7791_register_pfc();
77 r8a7791_register_gpio(0);
78 r8a7791_register_gpio(1);
79 r8a7791_register_gpio(2);
80 r8a7791_register_gpio(3);
81 r8a7791_register_gpio(4);
82 r8a7791_register_gpio(5);
83 r8a7791_register_gpio(6);
84 r8a7791_register_gpio(7);
59} 85}
60 86
61#define HSCIF_DATA(index, baseaddr, irq) \ 87#define __R8A7791_SCIF(scif_type, index, baseaddr, irq) \
62[index] = { \ 88static struct plat_sci_port scif##index##_platform_data = { \
63 SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \ 89 .type = scif_type, \
64 .scbrr_algo_id = SCBRR_ALGO_6, \ 90 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
65 .scscr = SCSCR_RE | SCSCR_TE, \ 91 .scscr = SCSCR_RE | SCSCR_TE, \
92}; \
93 \
94static struct resource scif##index##_resources[] = { \
95 DEFINE_RES_MEM(baseaddr, 0x100), \
96 DEFINE_RES_IRQ(irq), \
66} 97}
67 98
68enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, 99#define R8A7791_SCIF(index, baseaddr, irq) \
69 SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 }; 100 __R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq)
70 101
71static const struct plat_sci_port scif[] __initconst = { 102#define R8A7791_SCIFA(index, baseaddr, irq) \
72 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ 103 __R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq)
73 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ 104
74 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ 105#define R8A7791_SCIFB(index, baseaddr, irq) \
75 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ 106 __R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq)
76 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ 107
77 SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ 108R8A7791_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
78 SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ 109R8A7791_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
79 SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ 110R8A7791_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
80 SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */ 111R8A7791_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
81 SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */ 112R8A7791_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
82 SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */ 113R8A7791_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
83 SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */ 114R8A7791_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
84 SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */ 115R8A7791_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
85 SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */ 116R8A7791_SCIF(8, 0xe6e58000, gic_spi(22)); /* SCIF2 */
86 SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */ 117R8A7791_SCIF(9, 0xe6ea8000, gic_spi(23)); /* SCIF3 */
87}; 118R8A7791_SCIF(10, 0xe6ee0000, gic_spi(24)); /* SCIF4 */
88 119R8A7791_SCIF(11, 0xe6ee8000, gic_spi(25)); /* SCIF5 */
89static inline void r8a7791_register_scif(int idx) 120R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */
90{ 121R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */
91 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], 122R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */
92 sizeof(struct plat_sci_port)); 123
93} 124#define r8a7791_register_scif(index) \
125 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
126 scif##index##_resources, \
127 ARRAY_SIZE(scif##index##_resources), \
128 &scif##index##_platform_data, \
129 sizeof(scif##index##_platform_data))
94 130
95static const struct sh_timer_config cmt00_platform_data __initconst = { 131static const struct sh_timer_config cmt00_platform_data __initconst = {
96 .name = "CMT00", 132 .name = "CMT00",
@@ -136,23 +172,34 @@ static struct resource irqc0_resources[] = {
136 &irqc##idx##_data, \ 172 &irqc##idx##_data, \
137 sizeof(struct renesas_irqc_config)) 173 sizeof(struct renesas_irqc_config))
138 174
175static const struct resource thermal_resources[] __initconst = {
176 DEFINE_RES_MEM(0xe61f0000, 0x14),
177 DEFINE_RES_MEM(0xe61f0100, 0x38),
178 DEFINE_RES_IRQ(gic_spi(69)),
179};
180
181#define r8a7791_register_thermal() \
182 platform_device_register_simple("rcar_thermal", -1, \
183 thermal_resources, \
184 ARRAY_SIZE(thermal_resources))
185
139void __init r8a7791_add_dt_devices(void) 186void __init r8a7791_add_dt_devices(void)
140{ 187{
141 r8a7791_register_scif(SCIFA0); 188 r8a7791_register_scif(0);
142 r8a7791_register_scif(SCIFA1); 189 r8a7791_register_scif(1);
143 r8a7791_register_scif(SCIFB0); 190 r8a7791_register_scif(2);
144 r8a7791_register_scif(SCIFB1); 191 r8a7791_register_scif(3);
145 r8a7791_register_scif(SCIFB2); 192 r8a7791_register_scif(4);
146 r8a7791_register_scif(SCIFA2); 193 r8a7791_register_scif(5);
147 r8a7791_register_scif(SCIF0); 194 r8a7791_register_scif(6);
148 r8a7791_register_scif(SCIF1); 195 r8a7791_register_scif(7);
149 r8a7791_register_scif(SCIF2); 196 r8a7791_register_scif(8);
150 r8a7791_register_scif(SCIF3); 197 r8a7791_register_scif(9);
151 r8a7791_register_scif(SCIF4); 198 r8a7791_register_scif(10);
152 r8a7791_register_scif(SCIF5); 199 r8a7791_register_scif(11);
153 r8a7791_register_scif(SCIFA3); 200 r8a7791_register_scif(12);
154 r8a7791_register_scif(SCIFA4); 201 r8a7791_register_scif(13);
155 r8a7791_register_scif(SCIFA5); 202 r8a7791_register_scif(14);
156 r8a7791_register_cmt(00); 203 r8a7791_register_cmt(00);
157} 204}
158 205
@@ -160,6 +207,7 @@ void __init r8a7791_add_standard_devices(void)
160{ 207{
161 r8a7791_add_dt_devices(); 208 r8a7791_add_dt_devices();
162 r8a7791_register_irqc(0); 209 r8a7791_register_irqc(0);
210 r8a7791_register_thermal();
163} 211}
164 212
165void __init r8a7791_init_early(void) 213void __init r8a7791_init_early(void)
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 5734c24bf6c7..69ccc6c6fd33 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -18,6 +18,7 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 20
21#include <linux/clk/shmobile.h>
21#include <linux/clocksource.h> 22#include <linux/clocksource.h>
22#include <linux/io.h> 23#include <linux/io.h>
23#include <linux/kernel.h> 24#include <linux/kernel.h>
@@ -44,8 +45,10 @@ u32 __init rcar_gen2_read_mode_pins(void)
44 45
45void __init rcar_gen2_timer_init(void) 46void __init rcar_gen2_timer_init(void)
46{ 47{
47#ifdef CONFIG_ARM_ARCH_TIMER 48#if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK)
48 u32 mode = rcar_gen2_read_mode_pins(); 49 u32 mode = rcar_gen2_read_mode_pins();
50#endif
51#ifdef CONFIG_ARM_ARCH_TIMER
49 void __iomem *base; 52 void __iomem *base;
50 int extal_mhz = 0; 53 int extal_mhz = 0;
51 u32 freq; 54 u32 freq;
@@ -78,14 +81,28 @@ void __init rcar_gen2_timer_init(void)
78 /* Remap "armgcnt address map" space */ 81 /* Remap "armgcnt address map" space */
79 base = ioremap(0xe6080000, PAGE_SIZE); 82 base = ioremap(0xe6080000, PAGE_SIZE);
80 83
81 /* Update registers with correct frequency */ 84 /*
82 iowrite32(freq, base + CNTFID0); 85 * Update the timer if it is either not running, or is not at the
83 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); 86 * right frequency. The timer is only configurable in secure mode
87 * so this avoids an abort if the loader started the timer and
88 * entered the kernel in non-secure mode.
89 */
90
91 if ((ioread32(base + CNTCR) & 1) == 0 ||
92 ioread32(base + CNTFID0) != freq) {
93 /* Update registers with correct frequency */
94 iowrite32(freq, base + CNTFID0);
95 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
96
97 /* make sure arch timer is started by setting bit 0 of CNTCR */
98 iowrite32(1, base + CNTCR);
99 }
84 100
85 /* make sure arch timer is started by setting bit 0 of CNTCR */
86 iowrite32(1, base + CNTCR);
87 iounmap(base); 101 iounmap(base);
88#endif /* CONFIG_ARM_ARCH_TIMER */ 102#endif /* CONFIG_ARM_ARCH_TIMER */
89 103
104#ifdef CONFIG_COMMON_CLK
105 rcar_gen2_clocks_init(mode);
106#endif
90 clocksource_of_init(); 107 clocksource_of_init();
91} 108}
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 311878391e18..27301278c208 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -86,138 +86,36 @@ void __init sh7372_pinmux_init(void)
86 platform_device_register(&sh7372_pfc_device); 86 platform_device_register(&sh7372_pfc_device);
87} 87}
88 88
89/* SCIFA0 */ 89/* SCIF */
90static struct plat_sci_port scif0_platform_data = { 90#define SH7372_SCIF(scif_type, index, baseaddr, irq) \
91 .mapbase = 0xe6c40000, 91static struct plat_sci_port scif##index##_platform_data = { \
92 .flags = UPF_BOOT_AUTOCONF, 92 .type = scif_type, \
93 .scscr = SCSCR_RE | SCSCR_TE, 93 .flags = UPF_BOOT_AUTOCONF, \
94 .scbrr_algo_id = SCBRR_ALGO_4, 94 .scscr = SCSCR_RE | SCSCR_TE, \
95 .type = PORT_SCIFA, 95}; \
96 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00), 96 \
97 evt2irq(0x0c00), evt2irq(0x0c00) }, 97static struct resource scif##index##_resources[] = { \
98}; 98 DEFINE_RES_MEM(baseaddr, 0x100), \
99 99 DEFINE_RES_IRQ(irq), \
100static struct platform_device scif0_device = { 100}; \
101 .name = "sh-sci", 101 \
102 .id = 0, 102static struct platform_device scif##index##_device = { \
103 .dev = { 103 .name = "sh-sci", \
104 .platform_data = &scif0_platform_data, 104 .id = index, \
105 }, 105 .resource = scif##index##_resources, \
106}; 106 .num_resources = ARRAY_SIZE(scif##index##_resources), \
107 107 .dev = { \
108/* SCIFA1 */ 108 .platform_data = &scif##index##_platform_data, \
109static struct plat_sci_port scif1_platform_data = { 109 }, \
110 .mapbase = 0xe6c50000, 110}
111 .flags = UPF_BOOT_AUTOCONF,
112 .scscr = SCSCR_RE | SCSCR_TE,
113 .scbrr_algo_id = SCBRR_ALGO_4,
114 .type = PORT_SCIFA,
115 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
116 evt2irq(0x0c20), evt2irq(0x0c20) },
117};
118
119static struct platform_device scif1_device = {
120 .name = "sh-sci",
121 .id = 1,
122 .dev = {
123 .platform_data = &scif1_platform_data,
124 },
125};
126
127/* SCIFA2 */
128static struct plat_sci_port scif2_platform_data = {
129 .mapbase = 0xe6c60000,
130 .flags = UPF_BOOT_AUTOCONF,
131 .scscr = SCSCR_RE | SCSCR_TE,
132 .scbrr_algo_id = SCBRR_ALGO_4,
133 .type = PORT_SCIFA,
134 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
135 evt2irq(0x0c40), evt2irq(0x0c40) },
136};
137
138static struct platform_device scif2_device = {
139 .name = "sh-sci",
140 .id = 2,
141 .dev = {
142 .platform_data = &scif2_platform_data,
143 },
144};
145
146/* SCIFA3 */
147static struct plat_sci_port scif3_platform_data = {
148 .mapbase = 0xe6c70000,
149 .flags = UPF_BOOT_AUTOCONF,
150 .scscr = SCSCR_RE | SCSCR_TE,
151 .scbrr_algo_id = SCBRR_ALGO_4,
152 .type = PORT_SCIFA,
153 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
154 evt2irq(0x0c60), evt2irq(0x0c60) },
155};
156
157static struct platform_device scif3_device = {
158 .name = "sh-sci",
159 .id = 3,
160 .dev = {
161 .platform_data = &scif3_platform_data,
162 },
163};
164
165/* SCIFA4 */
166static struct plat_sci_port scif4_platform_data = {
167 .mapbase = 0xe6c80000,
168 .flags = UPF_BOOT_AUTOCONF,
169 .scscr = SCSCR_RE | SCSCR_TE,
170 .scbrr_algo_id = SCBRR_ALGO_4,
171 .type = PORT_SCIFA,
172 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
173 evt2irq(0x0d20), evt2irq(0x0d20) },
174};
175
176static struct platform_device scif4_device = {
177 .name = "sh-sci",
178 .id = 4,
179 .dev = {
180 .platform_data = &scif4_platform_data,
181 },
182};
183
184/* SCIFA5 */
185static struct plat_sci_port scif5_platform_data = {
186 .mapbase = 0xe6cb0000,
187 .flags = UPF_BOOT_AUTOCONF,
188 .scscr = SCSCR_RE | SCSCR_TE,
189 .scbrr_algo_id = SCBRR_ALGO_4,
190 .type = PORT_SCIFA,
191 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
192 evt2irq(0x0d40), evt2irq(0x0d40) },
193};
194
195static struct platform_device scif5_device = {
196 .name = "sh-sci",
197 .id = 5,
198 .dev = {
199 .platform_data = &scif5_platform_data,
200 },
201};
202
203/* SCIFB */
204static struct plat_sci_port scif6_platform_data = {
205 .mapbase = 0xe6c30000,
206 .flags = UPF_BOOT_AUTOCONF,
207 .scscr = SCSCR_RE | SCSCR_TE,
208 .scbrr_algo_id = SCBRR_ALGO_4,
209 .type = PORT_SCIFB,
210 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
211 evt2irq(0x0d60), evt2irq(0x0d60) },
212};
213 111
214static struct platform_device scif6_device = { 112SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
215 .name = "sh-sci", 113SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
216 .id = 6, 114SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
217 .dev = { 115SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
218 .platform_data = &scif6_platform_data, 116SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
219 }, 117SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
220}; 118SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
221 119
222/* CMT */ 120/* CMT */
223static struct sh_timer_config cmt2_platform_data = { 121static struct sh_timer_config cmt2_platform_data = {
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 65151c48cbd4..f74ab530c71d 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -71,167 +71,38 @@ void __init sh73a0_pinmux_init(void)
71 ARRAY_SIZE(pfc_resources)); 71 ARRAY_SIZE(pfc_resources));
72} 72}
73 73
74static struct plat_sci_port scif0_platform_data = { 74/* SCIF */
75 .mapbase = 0xe6c40000, 75#define SH73A0_SCIF(scif_type, index, baseaddr, irq) \
76 .flags = UPF_BOOT_AUTOCONF, 76static struct plat_sci_port scif##index##_platform_data = { \
77 .scscr = SCSCR_RE | SCSCR_TE, 77 .type = scif_type, \
78 .scbrr_algo_id = SCBRR_ALGO_4, 78 .flags = UPF_BOOT_AUTOCONF, \
79 .type = PORT_SCIFA, 79 .scscr = SCSCR_RE | SCSCR_TE, \
80 .irqs = { gic_spi(72), gic_spi(72), 80}; \
81 gic_spi(72), gic_spi(72) }, 81 \
82}; 82static struct resource scif##index##_resources[] = { \
83 83 DEFINE_RES_MEM(baseaddr, 0x100), \
84static struct platform_device scif0_device = { 84 DEFINE_RES_IRQ(irq), \
85 .name = "sh-sci", 85}; \
86 .id = 0, 86 \
87 .dev = { 87static struct platform_device scif##index##_device = { \
88 .platform_data = &scif0_platform_data, 88 .name = "sh-sci", \
89 }, 89 .id = index, \
90}; 90 .resource = scif##index##_resources, \
91 91 .num_resources = ARRAY_SIZE(scif##index##_resources), \
92static struct plat_sci_port scif1_platform_data = { 92 .dev = { \
93 .mapbase = 0xe6c50000, 93 .platform_data = &scif##index##_platform_data, \
94 .flags = UPF_BOOT_AUTOCONF, 94 }, \
95 .scscr = SCSCR_RE | SCSCR_TE, 95}
96 .scbrr_algo_id = SCBRR_ALGO_4,
97 .type = PORT_SCIFA,
98 .irqs = { gic_spi(73), gic_spi(73),
99 gic_spi(73), gic_spi(73) },
100};
101
102static struct platform_device scif1_device = {
103 .name = "sh-sci",
104 .id = 1,
105 .dev = {
106 .platform_data = &scif1_platform_data,
107 },
108};
109
110static struct plat_sci_port scif2_platform_data = {
111 .mapbase = 0xe6c60000,
112 .flags = UPF_BOOT_AUTOCONF,
113 .scscr = SCSCR_RE | SCSCR_TE,
114 .scbrr_algo_id = SCBRR_ALGO_4,
115 .type = PORT_SCIFA,
116 .irqs = { gic_spi(74), gic_spi(74),
117 gic_spi(74), gic_spi(74) },
118};
119
120static struct platform_device scif2_device = {
121 .name = "sh-sci",
122 .id = 2,
123 .dev = {
124 .platform_data = &scif2_platform_data,
125 },
126};
127
128static struct plat_sci_port scif3_platform_data = {
129 .mapbase = 0xe6c70000,
130 .flags = UPF_BOOT_AUTOCONF,
131 .scscr = SCSCR_RE | SCSCR_TE,
132 .scbrr_algo_id = SCBRR_ALGO_4,
133 .type = PORT_SCIFA,
134 .irqs = { gic_spi(75), gic_spi(75),
135 gic_spi(75), gic_spi(75) },
136};
137
138static struct platform_device scif3_device = {
139 .name = "sh-sci",
140 .id = 3,
141 .dev = {
142 .platform_data = &scif3_platform_data,
143 },
144};
145
146static struct plat_sci_port scif4_platform_data = {
147 .mapbase = 0xe6c80000,
148 .flags = UPF_BOOT_AUTOCONF,
149 .scscr = SCSCR_RE | SCSCR_TE,
150 .scbrr_algo_id = SCBRR_ALGO_4,
151 .type = PORT_SCIFA,
152 .irqs = { gic_spi(78), gic_spi(78),
153 gic_spi(78), gic_spi(78) },
154};
155
156static struct platform_device scif4_device = {
157 .name = "sh-sci",
158 .id = 4,
159 .dev = {
160 .platform_data = &scif4_platform_data,
161 },
162};
163
164static struct plat_sci_port scif5_platform_data = {
165 .mapbase = 0xe6cb0000,
166 .flags = UPF_BOOT_AUTOCONF,
167 .scscr = SCSCR_RE | SCSCR_TE,
168 .scbrr_algo_id = SCBRR_ALGO_4,
169 .type = PORT_SCIFA,
170 .irqs = { gic_spi(79), gic_spi(79),
171 gic_spi(79), gic_spi(79) },
172};
173
174static struct platform_device scif5_device = {
175 .name = "sh-sci",
176 .id = 5,
177 .dev = {
178 .platform_data = &scif5_platform_data,
179 },
180};
181
182static struct plat_sci_port scif6_platform_data = {
183 .mapbase = 0xe6cc0000,
184 .flags = UPF_BOOT_AUTOCONF,
185 .scscr = SCSCR_RE | SCSCR_TE,
186 .scbrr_algo_id = SCBRR_ALGO_4,
187 .type = PORT_SCIFA,
188 .irqs = { gic_spi(156), gic_spi(156),
189 gic_spi(156), gic_spi(156) },
190};
191
192static struct platform_device scif6_device = {
193 .name = "sh-sci",
194 .id = 6,
195 .dev = {
196 .platform_data = &scif6_platform_data,
197 },
198};
199
200static struct plat_sci_port scif7_platform_data = {
201 .mapbase = 0xe6cd0000,
202 .flags = UPF_BOOT_AUTOCONF,
203 .scscr = SCSCR_RE | SCSCR_TE,
204 .scbrr_algo_id = SCBRR_ALGO_4,
205 .type = PORT_SCIFA,
206 .irqs = { gic_spi(143), gic_spi(143),
207 gic_spi(143), gic_spi(143) },
208};
209
210static struct platform_device scif7_device = {
211 .name = "sh-sci",
212 .id = 7,
213 .dev = {
214 .platform_data = &scif7_platform_data,
215 },
216};
217
218static struct plat_sci_port scif8_platform_data = {
219 .mapbase = 0xe6c30000,
220 .flags = UPF_BOOT_AUTOCONF,
221 .scscr = SCSCR_RE | SCSCR_TE,
222 .scbrr_algo_id = SCBRR_ALGO_4,
223 .type = PORT_SCIFB,
224 .irqs = { gic_spi(80), gic_spi(80),
225 gic_spi(80), gic_spi(80) },
226};
227 96
228static struct platform_device scif8_device = { 97SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
229 .name = "sh-sci", 98SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
230 .id = 8, 99SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
231 .dev = { 100SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
232 .platform_data = &scif8_platform_data, 101SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
233 }, 102SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
234}; 103SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
104SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
105SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
235 106
236static struct sh_timer_config cmt10_platform_data = { 107static struct sh_timer_config cmt10_platform_data = {
237 .name = "CMT10", 108 .name = "CMT10",
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index bce0d4277f71..b9d6cad8669b 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1,7 +1,9 @@
1config ARCH_SUNXI 1config ARCH_SUNXI
2 bool "Allwinner A1X SOCs" if ARCH_MULTI_V7 2 bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
3 select ARCH_HAS_RESET_CONTROLLER
3 select ARCH_REQUIRE_GPIOLIB 4 select ARCH_REQUIRE_GPIOLIB
4 select ARM_GIC 5 select ARM_GIC
6 select ARM_PSCI
5 select CLKSRC_MMIO 7 select CLKSRC_MMIO
6 select CLKSRC_OF 8 select CLKSRC_OF
7 select COMMON_CLK 9 select COMMON_CLK
@@ -10,6 +12,7 @@ config ARCH_SUNXI
10 select HAVE_SMP 12 select HAVE_SMP
11 select PINCTRL 13 select PINCTRL
12 select PINCTRL_SUNXI 14 select PINCTRL_SUNXI
15 select RESET_CONTROLLER
13 select SPARSE_IRQ 16 select SPARSE_IRQ
14 select SUN4I_TIMER 17 select SUN4I_TIMER
15 select SUN5I_HSTIMER 18 select SUN5I_HSTIMER
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 93bebfc3ff9f..d9397202d6ec 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1 +1,2 @@
1obj-$(CONFIG_ARCH_SUNXI) += sunxi.o 1obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
2obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-sunxi/common.h b/arch/arm/mach-sunxi/common.h
new file mode 100644
index 000000000000..9e5ac4756cbb
--- /dev/null
+++ b/arch/arm/mach-sunxi/common.h
@@ -0,0 +1,19 @@
1/*
2 * Core functions for Allwinner SoCs
3 *
4 * Copyright (C) 2013 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __ARCH_SUNXI_COMMON_H_
14#define __ARCH_SUNXI_COMMON_H_
15
16void sun6i_secondary_startup(void);
17extern struct smp_operations sun6i_smp_ops;
18
19#endif /* __ARCH_SUNXI_COMMON_H_ */
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index 000000000000..a10d494fb37b
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,9 @@
1#include <linux/linkage.h>
2#include <linux/init.h>
3
4 .section ".text.head", "ax"
5
6ENTRY(sun6i_secondary_startup)
7 msr cpsr_fsxc, #0xd3
8 b secondary_startup
9ENDPROC(sun6i_secondary_startup)
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
new file mode 100644
index 000000000000..7b141d8342a1
--- /dev/null
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -0,0 +1,124 @@
1/*
2 * SMP support for Allwinner SoCs
3 *
4 * Copyright (C) 2013 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * Based on code
9 * Copyright (C) 2012-2013 Allwinner Ltd.
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/io.h>
19#include <linux/memory.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/smp.h>
23
24#include "common.h"
25
26#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64)
27#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40)
28#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04)
29#define CPUCFG_CPU_STATUS_REG(cpu) (((cpu) + 1) * 0x40 + 0x08)
30#define CPUCFG_GEN_CTRL_REG 0x184
31#define CPUCFG_PRIVATE0_REG 0x1a4
32#define CPUCFG_PRIVATE1_REG 0x1a8
33#define CPUCFG_DBG_CTL0_REG 0x1e0
34#define CPUCFG_DBG_CTL1_REG 0x1e4
35
36#define PRCM_CPU_PWROFF_REG 0x100
37#define PRCM_CPU_PWR_CLAMP_REG(cpu) (((cpu) * 4) + 0x140)
38
39static void __iomem *cpucfg_membase;
40static void __iomem *prcm_membase;
41
42static DEFINE_SPINLOCK(cpu_lock);
43
44static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
45{
46 struct device_node *node;
47
48 node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm");
49 if (!node) {
50 pr_err("Missing A31 PRCM node in the device tree\n");
51 return;
52 }
53
54 prcm_membase = of_iomap(node, 0);
55 if (!prcm_membase) {
56 pr_err("Couldn't map A31 PRCM registers\n");
57 return;
58 }
59
60 node = of_find_compatible_node(NULL, NULL,
61 "allwinner,sun6i-a31-cpuconfig");
62 if (!node) {
63 pr_err("Missing A31 CPU config node in the device tree\n");
64 return;
65 }
66
67 cpucfg_membase = of_iomap(node, 0);
68 if (!cpucfg_membase)
69 pr_err("Couldn't map A31 CPU config registers\n");
70
71}
72
73static int sun6i_smp_boot_secondary(unsigned int cpu,
74 struct task_struct *idle)
75{
76 u32 reg;
77 int i;
78
79 if (!(prcm_membase && cpucfg_membase))
80 return -EFAULT;
81
82 spin_lock(&cpu_lock);
83
84 /* Set CPU boot address */
85 writel(virt_to_phys(sun6i_secondary_startup),
86 cpucfg_membase + CPUCFG_PRIVATE0_REG);
87
88 /* Assert the CPU core in reset */
89 writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
90
91 /* Assert the L1 cache in reset */
92 reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
93 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
94
95 /* Disable external debug access */
96 reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
97 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
98
99 /* Power up the CPU */
100 for (i = 0; i <= 8; i++)
101 writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu));
102 mdelay(10);
103
104 /* Clear CPU power-off gating */
105 reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
106 writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
107 mdelay(1);
108
109 /* Deassert the CPU core reset */
110 writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
111
112 /* Enable back the external debug accesses */
113 reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
114 writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
115
116 spin_unlock(&cpu_lock);
117
118 return 0;
119}
120
121struct smp_operations sun6i_smp_ops __initdata = {
122 .smp_prepare_cpus = sun6i_smp_prepare_cpus,
123 .smp_boot_secondary = sun6i_smp_boot_secondary,
124};
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 61d3a387f01c..aeea6ceea725 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -10,6 +10,8 @@
10 * warranty of any kind, whether express or implied. 10 * warranty of any kind, whether express or implied.
11 */ 11 */
12 12
13#include <linux/clk-provider.h>
14#include <linux/clocksource.h>
13#include <linux/delay.h> 15#include <linux/delay.h>
14#include <linux/kernel.h> 16#include <linux/kernel.h>
15#include <linux/init.h> 17#include <linux/init.h>
@@ -23,6 +25,8 @@
23#include <asm/mach/map.h> 25#include <asm/mach/map.h>
24#include <asm/system_misc.h> 26#include <asm/system_misc.h>
25 27
28#include "common.h"
29
26#define SUN4I_WATCHDOG_CTRL_REG 0x00 30#define SUN4I_WATCHDOG_CTRL_REG 0x00
27#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0) 31#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
28#define SUN4I_WATCHDOG_MODE_REG 0x04 32#define SUN4I_WATCHDOG_MODE_REG 0x04
@@ -132,10 +136,20 @@ static const char * const sun6i_board_dt_compat[] = {
132 NULL, 136 NULL,
133}; 137};
134 138
139extern void __init sun6i_reset_init(void);
140static void __init sun6i_timer_init(void)
141{
142 of_clk_init(NULL);
143 sun6i_reset_init();
144 clocksource_of_init();
145}
146
135DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family") 147DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
136 .init_machine = sunxi_dt_init, 148 .init_machine = sunxi_dt_init,
149 .init_time = sun6i_timer_init,
137 .dt_compat = sun6i_board_dt_compat, 150 .dt_compat = sun6i_board_dt_compat,
138 .restart = sun6i_restart, 151 .restart = sun6i_restart,
152 .smp = smp_ops(sun6i_smp_ops),
139MACHINE_END 153MACHINE_END
140 154
141static const char * const sun7i_board_dt_compat[] = { 155static const char * const sun7i_board_dt_compat[] = {
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 15c09294effa..d1a12a496525 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -65,6 +65,7 @@ config ARCH_TEGRA_124_SOC
65 bool "Enable support for Tegra124 family" 65 bool "Enable support for Tegra124 family"
66 select ARM_L1_CACHE_SHIFT_6 66 select ARM_L1_CACHE_SHIFT_6
67 select HAVE_ARM_ARCH_TIMER 67 select HAVE_ARM_ARCH_TIMER
68 select PINCTRL_TEGRA124
68 help 69 help
69 Support for NVIDIA Tegra T124 processor family, based on the 70 Support for NVIDIA Tegra T124 processor family, based on the
70 ARM CortexA15MP CPU 71 ARM CortexA15MP CPU
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index 3a9c1f1c219d..c9ac23b385be 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -22,6 +22,7 @@
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/export.h> 23#include <linux/export.h>
24#include <linux/random.h> 24#include <linux/random.h>
25#include <linux/clk.h>
25#include <linux/tegra-soc.h> 26#include <linux/tegra-soc.h>
26 27
27#include "fuse.h" 28#include "fuse.h"
@@ -54,6 +55,7 @@ int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
54int tegra_soc_speedo_id; 55int tegra_soc_speedo_id;
55enum tegra_revision tegra_revision; 56enum tegra_revision tegra_revision;
56 57
58static struct clk *fuse_clk;
57static int tegra_fuse_spare_bit; 59static int tegra_fuse_spare_bit;
58static void (*tegra_init_speedo_data)(void); 60static void (*tegra_init_speedo_data)(void);
59 61
@@ -77,6 +79,22 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
77 [TEGRA_REVISION_A04] = "A04", 79 [TEGRA_REVISION_A04] = "A04",
78}; 80};
79 81
82static void tegra_fuse_enable_clk(void)
83{
84 if (IS_ERR(fuse_clk))
85 fuse_clk = clk_get_sys(NULL, "fuse");
86 if (IS_ERR(fuse_clk))
87 return;
88 clk_prepare_enable(fuse_clk);
89}
90
91static void tegra_fuse_disable_clk(void)
92{
93 if (IS_ERR(fuse_clk))
94 return;
95 clk_disable_unprepare(fuse_clk);
96}
97
80u32 tegra_fuse_readl(unsigned long offset) 98u32 tegra_fuse_readl(unsigned long offset)
81{ 99{
82 return tegra_apb_readl(TEGRA_FUSE_BASE + offset); 100 return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
@@ -84,7 +102,15 @@ u32 tegra_fuse_readl(unsigned long offset)
84 102
85bool tegra_spare_fuse(int bit) 103bool tegra_spare_fuse(int bit)
86{ 104{
87 return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4); 105 bool ret;
106
107 tegra_fuse_enable_clk();
108
109 ret = tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
110
111 tegra_fuse_disable_clk();
112
113 return ret;
88} 114}
89 115
90static enum tegra_revision tegra_get_revision(u32 id) 116static enum tegra_revision tegra_get_revision(u32 id)
@@ -113,10 +139,14 @@ static void tegra_get_process_id(void)
113{ 139{
114 u32 reg; 140 u32 reg;
115 141
142 tegra_fuse_enable_clk();
143
116 reg = tegra_fuse_readl(tegra_fuse_spare_bit); 144 reg = tegra_fuse_readl(tegra_fuse_spare_bit);
117 tegra_cpu_process_id = (reg >> 6) & 3; 145 tegra_cpu_process_id = (reg >> 6) & 3;
118 reg = tegra_fuse_readl(tegra_fuse_spare_bit); 146 reg = tegra_fuse_readl(tegra_fuse_spare_bit);
119 tegra_core_process_id = (reg >> 12) & 3; 147 tegra_core_process_id = (reg >> 12) & 3;
148
149 tegra_fuse_disable_clk();
120} 150}
121 151
122u32 tegra_read_chipid(void) 152u32 tegra_read_chipid(void)
@@ -159,6 +189,15 @@ void __init tegra_init_fuse(void)
159 reg |= 1 << 28; 189 reg |= 1 << 28;
160 writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); 190 writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
161 191
192 /*
193 * Enable FUSE clock. This needs to be hardcoded because the clock
194 * subsystem is not active during early boot.
195 */
196 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
197 reg |= 1 << 7;
198 writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
199 fuse_clk = ERR_PTR(-EINVAL);
200
162 reg = tegra_fuse_readl(FUSE_SKU_INFO); 201 reg = tegra_fuse_readl(FUSE_SKU_INFO);
163 randomness[0] = reg; 202 randomness[0] = reg;
164 tegra_sku_id = reg & 0xFF; 203 tegra_sku_id = reg & 0xFF;
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index 26b1c2ad0ceb..ee79808e93a3 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -19,6 +19,7 @@
19#ifndef __MACH_TEGRA_IOMAP_H 19#ifndef __MACH_TEGRA_IOMAP_H
20#define __MACH_TEGRA_IOMAP_H 20#define __MACH_TEGRA_IOMAP_H
21 21
22#include <asm/pgtable.h>
22#include <asm/sizes.h> 23#include <asm/sizes.h>
23 24
24#define TEGRA_IRAM_BASE 0x40000000 25#define TEGRA_IRAM_BASE 0x40000000
@@ -115,27 +116,26 @@
115 * two 256MB io windows (that actually only use about 64KB 116 * two 256MB io windows (that actually only use about 64KB
116 * at the start of each). 117 * at the start of each).
117 * 118 *
118 * We will just map the first 1MB of each window (to minimize 119 * We will just map the first MMU section of each window (to minimize
119 * pt entries needed) and provide a macro to transform physical 120 * pt entries needed) and provide a macro to transform physical
120 * io addresses to an appropriate void __iomem *. 121 * io addresses to an appropriate void __iomem *.
121 *
122 */ 122 */
123 123
124#define IO_IRAM_PHYS 0x40000000 124#define IO_IRAM_PHYS 0x40000000
125#define IO_IRAM_VIRT IOMEM(0xFE400000) 125#define IO_IRAM_VIRT IOMEM(0xFE400000)
126#define IO_IRAM_SIZE SZ_256K 126#define IO_IRAM_SIZE SZ_256K
127 127
128#define IO_CPU_PHYS 0x50040000 128#define IO_CPU_PHYS 0x50040000
129#define IO_CPU_VIRT IOMEM(0xFE000000) 129#define IO_CPU_VIRT IOMEM(0xFE440000)
130#define IO_CPU_SIZE SZ_16K 130#define IO_CPU_SIZE SZ_16K
131 131
132#define IO_PPSB_PHYS 0x60000000 132#define IO_PPSB_PHYS 0x60000000
133#define IO_PPSB_VIRT IOMEM(0xFE200000) 133#define IO_PPSB_VIRT IOMEM(0xFE200000)
134#define IO_PPSB_SIZE SZ_1M 134#define IO_PPSB_SIZE SECTION_SIZE
135 135
136#define IO_APB_PHYS 0x70000000 136#define IO_APB_PHYS 0x70000000
137#define IO_APB_VIRT IOMEM(0xFE300000) 137#define IO_APB_VIRT IOMEM(0xFE000000)
138#define IO_APB_SIZE SZ_1M 138#define IO_APB_SIZE SECTION_SIZE
139 139
140#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) 140#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
141#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) 141#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index f6f5b54ff95e..3d0c537d9b94 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -34,6 +34,10 @@
34#include "fuse.h" 34#include "fuse.h"
35#include "iomap.h" 35#include "iomap.h"
36 36
37#define DPD_SAMPLE 0x020
38#define DPD_SAMPLE_ENABLE (1 << 0)
39#define DPD_SAMPLE_DISABLE (0 << 0)
40
37#define PWRGATE_TOGGLE 0x30 41#define PWRGATE_TOGGLE 0x30
38#define PWRGATE_TOGGLE_START (1 << 8) 42#define PWRGATE_TOGGLE_START (1 << 8)
39 43
@@ -41,6 +45,19 @@
41 45
42#define PWRGATE_STATUS 0x38 46#define PWRGATE_STATUS 0x38
43 47
48#define IO_DPD_REQ 0x1b8
49#define IO_DPD_REQ_CODE_IDLE (0 << 30)
50#define IO_DPD_REQ_CODE_OFF (1 << 30)
51#define IO_DPD_REQ_CODE_ON (2 << 30)
52#define IO_DPD_REQ_CODE_MASK (3 << 30)
53
54#define IO_DPD_STATUS 0x1bc
55#define IO_DPD2_REQ 0x1c0
56#define IO_DPD2_STATUS 0x1c4
57#define SEL_DPD_TIM 0x1c8
58
59#define GPU_RG_CNTRL 0x2d4
60
44static int tegra_num_powerdomains; 61static int tegra_num_powerdomains;
45static int tegra_num_cpu_domains; 62static int tegra_num_cpu_domains;
46static const u8 *tegra_cpu_domains; 63static const u8 *tegra_cpu_domains;
@@ -59,6 +76,13 @@ static const u8 tegra114_cpu_domains[] = {
59 TEGRA_POWERGATE_CPU3, 76 TEGRA_POWERGATE_CPU3,
60}; 77};
61 78
79static const u8 tegra124_cpu_domains[] = {
80 TEGRA_POWERGATE_CPU0,
81 TEGRA_POWERGATE_CPU1,
82 TEGRA_POWERGATE_CPU2,
83 TEGRA_POWERGATE_CPU3,
84};
85
62static DEFINE_SPINLOCK(tegra_powergate_lock); 86static DEFINE_SPINLOCK(tegra_powergate_lock);
63 87
64static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); 88static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
@@ -109,6 +133,7 @@ int tegra_powergate_power_off(int id)
109 133
110 return tegra_powergate_set(id, false); 134 return tegra_powergate_set(id, false);
111} 135}
136EXPORT_SYMBOL(tegra_powergate_power_off);
112 137
113int tegra_powergate_is_powered(int id) 138int tegra_powergate_is_powered(int id)
114{ 139{
@@ -129,12 +154,23 @@ int tegra_powergate_remove_clamping(int id)
129 return -EINVAL; 154 return -EINVAL;
130 155
131 /* 156 /*
157 * The Tegra124 GPU has a separate register (with different semantics)
158 * to remove clamps.
159 */
160 if (tegra_chip_id == TEGRA124) {
161 if (id == TEGRA_POWERGATE_3D) {
162 pmc_write(0, GPU_RG_CNTRL);
163 return 0;
164 }
165 }
166
167 /*
132 * Tegra 2 has a bug where PCIE and VDE clamping masks are 168 * Tegra 2 has a bug where PCIE and VDE clamping masks are
133 * swapped relatively to the partition ids 169 * swapped relatively to the partition ids
134 */ 170 */
135 if (id == TEGRA_POWERGATE_VDEC) 171 if (id == TEGRA_POWERGATE_VDEC)
136 mask = (1 << TEGRA_POWERGATE_PCIE); 172 mask = (1 << TEGRA_POWERGATE_PCIE);
137 else if (id == TEGRA_POWERGATE_PCIE) 173 else if (id == TEGRA_POWERGATE_PCIE)
138 mask = (1 << TEGRA_POWERGATE_VDEC); 174 mask = (1 << TEGRA_POWERGATE_VDEC);
139 else 175 else
140 mask = (1 << id); 176 mask = (1 << id);
@@ -143,6 +179,7 @@ int tegra_powergate_remove_clamping(int id)
143 179
144 return 0; 180 return 0;
145} 181}
182EXPORT_SYMBOL(tegra_powergate_remove_clamping);
146 183
147/* Must be called with clk disabled, and returns with clk enabled */ 184/* Must be called with clk disabled, and returns with clk enabled */
148int tegra_powergate_sequence_power_up(int id, struct clk *clk, 185int tegra_powergate_sequence_power_up(int id, struct clk *clk,
@@ -204,6 +241,11 @@ int __init tegra_powergate_init(void)
204 tegra_num_cpu_domains = 4; 241 tegra_num_cpu_domains = 4;
205 tegra_cpu_domains = tegra114_cpu_domains; 242 tegra_cpu_domains = tegra114_cpu_domains;
206 break; 243 break;
244 case TEGRA124:
245 tegra_num_powerdomains = 25;
246 tegra_num_cpu_domains = 4;
247 tegra_cpu_domains = tegra124_cpu_domains;
248 break;
207 default: 249 default:
208 /* Unknown Tegra variant. Disable powergating */ 250 /* Unknown Tegra variant. Disable powergating */
209 tegra_num_powerdomains = 0; 251 tegra_num_powerdomains = 0;
@@ -245,12 +287,36 @@ static const char * const powergate_name_t30[] = {
245}; 287};
246 288
247static const char * const powergate_name_t114[] = { 289static const char * const powergate_name_t114[] = {
248 [TEGRA_POWERGATE_CPU] = "cpu0", 290 [TEGRA_POWERGATE_CPU] = "crail",
291 [TEGRA_POWERGATE_3D] = "3d",
292 [TEGRA_POWERGATE_VENC] = "venc",
293 [TEGRA_POWERGATE_VDEC] = "vdec",
294 [TEGRA_POWERGATE_MPE] = "mpe",
295 [TEGRA_POWERGATE_HEG] = "heg",
296 [TEGRA_POWERGATE_CPU1] = "cpu1",
297 [TEGRA_POWERGATE_CPU2] = "cpu2",
298 [TEGRA_POWERGATE_CPU3] = "cpu3",
299 [TEGRA_POWERGATE_CELP] = "celp",
300 [TEGRA_POWERGATE_CPU0] = "cpu0",
301 [TEGRA_POWERGATE_C0NC] = "c0nc",
302 [TEGRA_POWERGATE_C1NC] = "c1nc",
303 [TEGRA_POWERGATE_DIS] = "dis",
304 [TEGRA_POWERGATE_DISB] = "disb",
305 [TEGRA_POWERGATE_XUSBA] = "xusba",
306 [TEGRA_POWERGATE_XUSBB] = "xusbb",
307 [TEGRA_POWERGATE_XUSBC] = "xusbc",
308};
309
310static const char * const powergate_name_t124[] = {
311 [TEGRA_POWERGATE_CPU] = "crail",
249 [TEGRA_POWERGATE_3D] = "3d", 312 [TEGRA_POWERGATE_3D] = "3d",
250 [TEGRA_POWERGATE_VENC] = "venc", 313 [TEGRA_POWERGATE_VENC] = "venc",
314 [TEGRA_POWERGATE_PCIE] = "pcie",
251 [TEGRA_POWERGATE_VDEC] = "vdec", 315 [TEGRA_POWERGATE_VDEC] = "vdec",
316 [TEGRA_POWERGATE_L2] = "l2",
252 [TEGRA_POWERGATE_MPE] = "mpe", 317 [TEGRA_POWERGATE_MPE] = "mpe",
253 [TEGRA_POWERGATE_HEG] = "heg", 318 [TEGRA_POWERGATE_HEG] = "heg",
319 [TEGRA_POWERGATE_SATA] = "sata",
254 [TEGRA_POWERGATE_CPU1] = "cpu1", 320 [TEGRA_POWERGATE_CPU1] = "cpu1",
255 [TEGRA_POWERGATE_CPU2] = "cpu2", 321 [TEGRA_POWERGATE_CPU2] = "cpu2",
256 [TEGRA_POWERGATE_CPU3] = "cpu3", 322 [TEGRA_POWERGATE_CPU3] = "cpu3",
@@ -258,11 +324,14 @@ static const char * const powergate_name_t114[] = {
258 [TEGRA_POWERGATE_CPU0] = "cpu0", 324 [TEGRA_POWERGATE_CPU0] = "cpu0",
259 [TEGRA_POWERGATE_C0NC] = "c0nc", 325 [TEGRA_POWERGATE_C0NC] = "c0nc",
260 [TEGRA_POWERGATE_C1NC] = "c1nc", 326 [TEGRA_POWERGATE_C1NC] = "c1nc",
327 [TEGRA_POWERGATE_SOR] = "sor",
261 [TEGRA_POWERGATE_DIS] = "dis", 328 [TEGRA_POWERGATE_DIS] = "dis",
262 [TEGRA_POWERGATE_DISB] = "disb", 329 [TEGRA_POWERGATE_DISB] = "disb",
263 [TEGRA_POWERGATE_XUSBA] = "xusba", 330 [TEGRA_POWERGATE_XUSBA] = "xusba",
264 [TEGRA_POWERGATE_XUSBB] = "xusbb", 331 [TEGRA_POWERGATE_XUSBB] = "xusbb",
265 [TEGRA_POWERGATE_XUSBC] = "xusbc", 332 [TEGRA_POWERGATE_XUSBC] = "xusbc",
333 [TEGRA_POWERGATE_VIC] = "vic",
334 [TEGRA_POWERGATE_IRAM] = "iram",
266}; 335};
267 336
268static int powergate_show(struct seq_file *s, void *data) 337static int powergate_show(struct seq_file *s, void *data)
@@ -309,6 +378,9 @@ int __init tegra_powergate_debugfs_init(void)
309 case TEGRA114: 378 case TEGRA114:
310 powergate_name = powergate_name_t114; 379 powergate_name = powergate_name_t114;
311 break; 380 break;
381 case TEGRA124:
382 powergate_name = powergate_name_t124;
383 break;
312 } 384 }
313 385
314 if (powergate_name) { 386 if (powergate_name) {
@@ -322,3 +394,120 @@ int __init tegra_powergate_debugfs_init(void)
322} 394}
323 395
324#endif 396#endif
397
398static int tegra_io_rail_prepare(int id, unsigned long *request,
399 unsigned long *status, unsigned int *bit)
400{
401 unsigned long rate, value;
402 struct clk *clk;
403
404 *bit = id % 32;
405
406 /*
407 * There are two sets of 30 bits to select IO rails, but bits 30 and
408 * 31 are control bits rather than IO rail selection bits.
409 */
410 if (id > 63 || *bit == 30 || *bit == 31)
411 return -EINVAL;
412
413 if (id < 32) {
414 *status = IO_DPD_STATUS;
415 *request = IO_DPD_REQ;
416 } else {
417 *status = IO_DPD2_STATUS;
418 *request = IO_DPD2_REQ;
419 }
420
421 clk = clk_get_sys(NULL, "pclk");
422 if (IS_ERR(clk))
423 return PTR_ERR(clk);
424
425 rate = clk_get_rate(clk);
426 clk_put(clk);
427
428 pmc_write(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
429
430 /* must be at least 200 ns, in APB (PCLK) clock cycles */
431 value = DIV_ROUND_UP(1000000000, rate);
432 value = DIV_ROUND_UP(200, value);
433 pmc_write(value, SEL_DPD_TIM);
434
435 return 0;
436}
437
438static int tegra_io_rail_poll(unsigned long offset, unsigned long mask,
439 unsigned long val, unsigned long timeout)
440{
441 unsigned long value;
442
443 timeout = jiffies + msecs_to_jiffies(timeout);
444
445 while (time_after(timeout, jiffies)) {
446 value = pmc_read(offset);
447 if ((value & mask) == val)
448 return 0;
449
450 usleep_range(250, 1000);
451 }
452
453 return -ETIMEDOUT;
454}
455
456static void tegra_io_rail_unprepare(void)
457{
458 pmc_write(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
459}
460
461int tegra_io_rail_power_on(int id)
462{
463 unsigned long request, status, value;
464 unsigned int bit, mask;
465 int err;
466
467 err = tegra_io_rail_prepare(id, &request, &status, &bit);
468 if (err < 0)
469 return err;
470
471 mask = 1 << bit;
472
473 value = pmc_read(request);
474 value |= mask;
475 value &= ~IO_DPD_REQ_CODE_MASK;
476 value |= IO_DPD_REQ_CODE_OFF;
477 pmc_write(value, request);
478
479 err = tegra_io_rail_poll(status, mask, 0, 250);
480 if (err < 0)
481 return err;
482
483 tegra_io_rail_unprepare();
484
485 return 0;
486}
487
488int tegra_io_rail_power_off(int id)
489{
490 unsigned long request, status, value;
491 unsigned int bit, mask;
492 int err;
493
494 err = tegra_io_rail_prepare(id, &request, &status, &bit);
495 if (err < 0)
496 return err;
497
498 mask = 1 << bit;
499
500 value = pmc_read(request);
501 value |= mask;
502 value &= ~IO_DPD_REQ_CODE_MASK;
503 value |= IO_DPD_REQ_CODE_ON;
504 pmc_write(value, request);
505
506 err = tegra_io_rail_poll(status, mask, mask, 250);
507 if (err < 0)
508 return err;
509
510 tegra_io_rail_unprepare();
511
512 return 0;
513}
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 73368176c6e8..ea14d380fc0c 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -60,15 +60,13 @@
60 * kernel is loaded. The data is declared here rather than debug-macro.S so 60 * kernel is loaded. The data is declared here rather than debug-macro.S so
61 * that multiple inclusions of debug-macro.S point at the same data. 61 * that multiple inclusions of debug-macro.S point at the same data.
62 */ 62 */
63u32 tegra_uart_config[4] = { 63u32 tegra_uart_config[3] = {
64 /* Debug UART initialization required */ 64 /* Debug UART initialization required */
65 1, 65 1,
66 /* Debug UART physical address */ 66 /* Debug UART physical address */
67 0, 67 0,
68 /* Debug UART virtual address */ 68 /* Debug UART virtual address */
69 0, 69 0,
70 /* Scratch space for debug macro */
71 0,
72}; 70};
73 71
74static void __init tegra_init_cache(void) 72static void __init tegra_init_cache(void)
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 5226162fac69..fe08fd34c0ce 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -349,7 +349,7 @@ static struct irqaction u300_timer_irq = {
349 * stamp. (Inspired by OMAP implementation.) 349 * stamp. (Inspired by OMAP implementation.)
350 */ 350 */
351 351
352static u32 notrace u300_read_sched_clock(void) 352static u64 notrace u300_read_sched_clock(void)
353{ 353{
354 return readl(u300_timer_base + U300_TIMER_APP_GPT2CC); 354 return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
355} 355}
@@ -389,7 +389,7 @@ static void __init u300_timer_init_of(struct device_node *np)
389 389
390 u300_clockevent_data.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ); 390 u300_clockevent_data.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
391 391
392 setup_sched_clock(u300_read_sched_clock, 32, rate); 392 sched_clock_register(u300_read_sched_clock, 32, rate);
393 393
394 u300_delay_timer.read_current_timer = &u300_read_current_timer; 394 u300_delay_timer.read_current_timer = &u300_read_current_timer;
395 u300_delay_timer.freq = rate; 395 u300_delay_timer.freq = rate;
diff --git a/arch/arm/mach-ux500/pm.c b/arch/arm/mach-ux500/pm.c
index 1a468f0fd22e..b80a9a2e356e 100644
--- a/arch/arm/mach-ux500/pm.c
+++ b/arch/arm/mach-ux500/pm.c
@@ -3,6 +3,8 @@
3 * Author: Rickard Andersson <rickard.andersson@stericsson.com> for 3 * Author: Rickard Andersson <rickard.andersson@stericsson.com> for
4 * ST-Ericsson. 4 * ST-Ericsson.
5 * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro. 5 * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro.
6 * Author: Ulf Hansson <ulf.hansson@linaro.org> for Linaro.
7 *
6 * License terms: GNU General Public License (GPL) version 2 8 * License terms: GNU General Public License (GPL) version 2
7 * 9 *
8 */ 10 */
@@ -11,6 +13,7 @@
11#include <linux/irqchip/arm-gic.h> 13#include <linux/irqchip/arm-gic.h>
12#include <linux/delay.h> 14#include <linux/delay.h>
13#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/suspend.h>
14#include <linux/platform_data/arm-ux500-pm.h> 17#include <linux/platform_data/arm-ux500-pm.h>
15 18
16#include "db8500-regs.h" 19#include "db8500-regs.h"
@@ -152,6 +155,27 @@ int prcmu_copy_gic_settings(void)
152 return 0; 155 return 0;
153} 156}
154 157
158#ifdef CONFIG_SUSPEND
159static int ux500_suspend_enter(suspend_state_t state)
160{
161 cpu_do_idle();
162 return 0;
163}
164
165static int ux500_suspend_valid(suspend_state_t state)
166{
167 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
168}
169
170static const struct platform_suspend_ops ux500_suspend_ops = {
171 .enter = ux500_suspend_enter,
172 .valid = ux500_suspend_valid,
173};
174#define UX500_SUSPEND_OPS (&ux500_suspend_ops)
175#else
176#define UX500_SUSPEND_OPS NULL
177#endif
178
155void __init ux500_pm_init(u32 phy_base, u32 size) 179void __init ux500_pm_init(u32 phy_base, u32 size)
156{ 180{
157 prcmu_base = ioremap(phy_base, size); 181 prcmu_base = ioremap(phy_base, size);
@@ -164,4 +188,7 @@ void __init ux500_pm_init(u32 phy_base, u32 size)
164 * This will make sure that the GIC is correctly configured. 188 * This will make sure that the GIC is correctly configured.
165 */ 189 */
166 prcmu_gic_recouple(); 190 prcmu_gic_recouple();
191
192 /* Set up ux500 suspend callbacks. */
193 suspend_set_ops(UX500_SUSPEND_OPS);
167} 194}
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 3b0572f30d56..a335126ae18f 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -570,6 +570,16 @@ static struct pl061_platform_data gpio1_plat_data = {
570 .irq_base = IRQ_GPIO1_START, 570 .irq_base = IRQ_GPIO1_START,
571}; 571};
572 572
573static struct pl061_platform_data gpio2_plat_data = {
574 .gpio_base = 16,
575 .irq_base = IRQ_GPIO2_START,
576};
577
578static struct pl061_platform_data gpio3_plat_data = {
579 .gpio_base = 24,
580 .irq_base = IRQ_GPIO3_START,
581};
582
573static struct pl022_ssp_controller ssp0_plat_data = { 583static struct pl022_ssp_controller ssp0_plat_data = {
574 .bus_id = 0, 584 .bus_id = 0,
575 .enable_dma = 0, 585 .enable_dma = 0,
@@ -596,6 +606,8 @@ static struct pl022_ssp_controller ssp0_plat_data = {
596#define WATCHDOG_IRQ { IRQ_WDOGINT } 606#define WATCHDOG_IRQ { IRQ_WDOGINT }
597#define GPIO0_IRQ { IRQ_GPIOINT0 } 607#define GPIO0_IRQ { IRQ_GPIOINT0 }
598#define GPIO1_IRQ { IRQ_GPIOINT1 } 608#define GPIO1_IRQ { IRQ_GPIOINT1 }
609#define GPIO2_IRQ { IRQ_GPIOINT2 }
610#define GPIO3_IRQ { IRQ_GPIOINT3 }
599#define RTC_IRQ { IRQ_RTCINT } 611#define RTC_IRQ { IRQ_RTCINT }
600 612
601/* 613/*
@@ -622,6 +634,8 @@ APB_DEVICE(sctl, "dev:e0", SCTL, NULL);
622APB_DEVICE(wdog, "dev:e1", WATCHDOG, NULL); 634APB_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
623APB_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data); 635APB_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
624APB_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data); 636APB_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
637APB_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data);
638APB_DEVICE(gpio3, "dev:e7", GPIO3, &gpio3_plat_data);
625APB_DEVICE(rtc, "dev:e8", RTC, NULL); 639APB_DEVICE(rtc, "dev:e8", RTC, NULL);
626APB_DEVICE(sci0, "dev:f0", SCI, NULL); 640APB_DEVICE(sci0, "dev:f0", SCI, NULL);
627APB_DEVICE(uart0, "dev:f1", UART0, NULL); 641APB_DEVICE(uart0, "dev:f1", UART0, NULL);
@@ -641,6 +655,8 @@ static struct amba_device *amba_devs[] __initdata = {
641 &wdog_device, 655 &wdog_device,
642 &gpio0_device, 656 &gpio0_device,
643 &gpio1_device, 657 &gpio1_device,
658 &gpio2_device,
659 &gpio3_device,
644 &rtc_device, 660 &rtc_device,
645 &sci0_device, 661 &sci0_device,
646 &ssp0_device, 662 &ssp0_device,
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 611d140c8695..9a53d0bd9144 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -47,27 +47,11 @@ static struct mmci_platform_data mmc1_plat_data = {
47 .gpio_cd = -1, 47 .gpio_cd = -1,
48}; 48};
49 49
50static struct pl061_platform_data gpio2_plat_data = {
51 .gpio_base = 16,
52 .irq_base = IRQ_GPIO2_START,
53};
54
55static struct pl061_platform_data gpio3_plat_data = {
56 .gpio_base = 24,
57 .irq_base = IRQ_GPIO3_START,
58};
59
60#define UART3_IRQ { IRQ_SIC_UART3 } 50#define UART3_IRQ { IRQ_SIC_UART3 }
61#define SCI1_IRQ { IRQ_SIC_SCI3 } 51#define SCI1_IRQ { IRQ_SIC_SCI3 }
62#define MMCI1_IRQ { IRQ_MMCI1A, IRQ_SIC_MMCI1B } 52#define MMCI1_IRQ { IRQ_MMCI1A, IRQ_SIC_MMCI1B }
63 53
64/* 54/*
65 * These devices are connected via the core APB bridge
66 */
67#define GPIO2_IRQ { IRQ_GPIOINT2 }
68#define GPIO3_IRQ { IRQ_GPIOINT3 }
69
70/*
71 * These devices are connected via the DMA APB bridge 55 * These devices are connected via the DMA APB bridge
72 */ 56 */
73 57
@@ -76,14 +60,9 @@ APB_DEVICE(uart3, "fpga:09", UART3, NULL);
76APB_DEVICE(sci1, "fpga:0a", SCI1, NULL); 60APB_DEVICE(sci1, "fpga:0a", SCI1, NULL);
77APB_DEVICE(mmc1, "fpga:0b", MMCI1, &mmc1_plat_data); 61APB_DEVICE(mmc1, "fpga:0b", MMCI1, &mmc1_plat_data);
78 62
79/* DevChip Primecells */
80APB_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data);
81APB_DEVICE(gpio3, "dev:e7", GPIO3, &gpio3_plat_data);
82 63
83static struct amba_device *amba_devs[] __initdata = { 64static struct amba_device *amba_devs[] __initdata = {
84 &uart3_device, 65 &uart3_device,
85 &gpio2_device,
86 &gpio3_device,
87 &sci1_device, 66 &sci1_device,
88 &mmc1_device, 67 &mmc1_device,
89}; 68};
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 29606bd75f3f..d70b73364a3f 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -54,7 +54,7 @@ static struct clocksource iop_clocksource = {
54/* 54/*
55 * IOP sched_clock() implementation via its clocksource. 55 * IOP sched_clock() implementation via its clocksource.
56 */ 56 */
57static u32 notrace iop_read_sched_clock(void) 57static u64 notrace iop_read_sched_clock(void)
58{ 58{
59 return 0xffffffffu - read_tcr1(); 59 return 0xffffffffu - read_tcr1();
60} 60}
@@ -142,7 +142,7 @@ void __init iop_init_time(unsigned long tick_rate)
142{ 142{
143 u32 timer_ctl; 143 u32 timer_ctl;
144 144
145 setup_sched_clock(iop_read_sched_clock, 32, tick_rate); 145 sched_clock_register(iop_read_sched_clock, 32, tick_rate);
146 146
147 ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ); 147 ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
148 iop_tick_rate = tick_rate; 148 iop_tick_rate = tick_rate;
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index d9bc98eb2a6b..384a776d8eb2 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -38,7 +38,7 @@
38 */ 38 */
39static void __iomem *sync32k_cnt_reg; 39static void __iomem *sync32k_cnt_reg;
40 40
41static u32 notrace omap_32k_read_sched_clock(void) 41static u64 notrace omap_32k_read_sched_clock(void)
42{ 42{
43 return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0; 43 return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
44} 44}
@@ -115,7 +115,7 @@ int __init omap_init_clocksource_32k(void __iomem *vbase)
115 return ret; 115 return ret;
116 } 116 }
117 117
118 setup_sched_clock(omap_32k_read_sched_clock, 32, 32768); 118 sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
119 register_persistent_clock(NULL, omap_read_persistent_clock); 119 register_persistent_clock(NULL, omap_read_persistent_clock);
120 pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n"); 120 pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
121 121
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 15921a1839d7..261258f717fc 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -61,7 +61,7 @@ static u32 ticks_per_jiffy;
61 * at least 7.5ns (133MHz TCLK). 61 * at least 7.5ns (133MHz TCLK).
62 */ 62 */
63 63
64static u32 notrace orion_read_sched_clock(void) 64static u64 notrace orion_read_sched_clock(void)
65{ 65{
66 return ~readl(timer_base + TIMER0_VAL_OFF); 66 return ~readl(timer_base + TIMER0_VAL_OFF);
67} 67}
@@ -202,7 +202,7 @@ orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
202 /* 202 /*
203 * Set scale and timer for sched_clock. 203 * Set scale and timer for sched_clock.
204 */ 204 */
205 setup_sched_clock(orion_read_sched_clock, 32, tclk); 205 sched_clock_register(orion_read_sched_clock, 32, tclk);
206 206
207 /* 207 /*
208 * Setup free-running clocksource timer (interrupts 208 * Setup free-running clocksource timer (interrupts
diff --git a/arch/arm/plat-samsung/s5p-irq-eint.c b/arch/arm/plat-samsung/s5p-irq-eint.c
index faa651602780..ebee4dc11a94 100644
--- a/arch/arm/plat-samsung/s5p-irq-eint.c
+++ b/arch/arm/plat-samsung/s5p-irq-eint.c
@@ -16,6 +16,7 @@
16#include <linux/device.h> 16#include <linux/device.h>
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/irqchip/arm-vic.h> 18#include <linux/irqchip/arm-vic.h>
19#include <linux/of.h>
19 20
20#include <plat/regs-irqtype.h> 21#include <plat/regs-irqtype.h>
21 22
@@ -202,6 +203,9 @@ static int __init s5p_init_irq_eint(void)
202{ 203{
203 int irq; 204 int irq;
204 205
206 if (of_have_populated_dt())
207 return -ENODEV;
208
205 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) 209 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
206 irq_set_chip(irq, &s5p_irq_vic_eint); 210 irq_set_chip(irq, &s5p_irq_vic_eint);
207 211
diff --git a/arch/arm/plat-versatile/sched-clock.c b/arch/arm/plat-versatile/sched-clock.c
index 51b109e3b6c3..c966ae90f4a0 100644
--- a/arch/arm/plat-versatile/sched-clock.c
+++ b/arch/arm/plat-versatile/sched-clock.c
@@ -26,7 +26,7 @@
26 26
27static void __iomem *ctr; 27static void __iomem *ctr;
28 28
29static u32 notrace versatile_read_sched_clock(void) 29static u64 notrace versatile_read_sched_clock(void)
30{ 30{
31 if (ctr) 31 if (ctr)
32 return readl(ctr); 32 return readl(ctr);
@@ -37,5 +37,5 @@ static u32 notrace versatile_read_sched_clock(void)
37void __init versatile_sched_clock_init(void __iomem *reg, unsigned long rate) 37void __init versatile_sched_clock_init(void __iomem *reg, unsigned long rate)
38{ 38{
39 ctr = reg; 39 ctr = reg;
40 setup_sched_clock(versatile_read_sched_clock, 32, rate); 40 sched_clock_register(versatile_read_sched_clock, 32, rate);
41} 41}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 19:44:27 -0500