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-rw-r--r--arch/arm/mach-tegra/headsmp.S6
-rw-r--r--arch/arm/mach-tegra/sleep.S33
-rw-r--r--arch/arm/mach-tegra/sleep.h56
3 files changed, 58 insertions, 37 deletions
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fef9c2c51370..6addc78cb6b2 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -7,17 +7,13 @@
7 7
8#include "flowctrl.h" 8#include "flowctrl.h"
9#include "reset.h" 9#include "reset.h"
10#include "sleep.h"
10 11
11#define APB_MISC_GP_HIDREV 0x804 12#define APB_MISC_GP_HIDREV 0x804
12#define PMC_SCRATCH41 0x140 13#define PMC_SCRATCH41 0x140
13 14
14#define RESET_DATA(x) ((TEGRA_RESET_##x)*4) 15#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
15 16
16 .macro mov32, reg, val
17 movw \reg, #:lower16:\val
18 movt \reg, #:upper16:\val
19 .endm
20
21 .section ".text.head", "ax" 17 .section ".text.head", "ax"
22 __CPUINIT 18 __CPUINIT
23 19
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index d29b156a8011..ea81554c4833 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -29,36 +29,5 @@
29#include <mach/iomap.h> 29#include <mach/iomap.h>
30 30
31#include "flowctrl.h" 31#include "flowctrl.h"
32#include "sleep.h"
32 33
33#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
34 + IO_PPSB_VIRT)
35
36/* returns the offset of the flow controller halt register for a cpu */
37.macro cpu_to_halt_reg rd, rcpu
38 cmp \rcpu, #0
39 subne \rd, \rcpu, #1
40 movne \rd, \rd, lsl #3
41 addne \rd, \rd, #0x14
42 moveq \rd, #0
43.endm
44
45/* returns the offset of the flow controller csr register for a cpu */
46.macro cpu_to_csr_reg rd, rcpu
47 cmp \rcpu, #0
48 subne \rd, \rcpu, #1
49 movne \rd, \rd, lsl #3
50 addne \rd, \rd, #0x18
51 moveq \rd, #8
52.endm
53
54/* returns the ID of the current processor */
55.macro cpu_id, rd
56 mrc p15, 0, \rd, c0, c0, 5
57 and \rd, \rd, #0xF
58.endm
59
60/* loads a 32-bit value into a register without a data access */
61.macro mov32, reg, val
62 movw \reg, #:lower16:\val
63 movt \reg, #:upper16:\val
64.endm
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
new file mode 100644
index 000000000000..d0c7a8b1c885
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep.h
@@ -0,0 +1,56 @@
1/*
2 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __MACH_TEGRA_SLEEP_H
18#define __MACH_TEGRA_SLEEP_H
19
20#include <mach/iomap.h>
21
22#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
23 + IO_PPSB_VIRT)
24
25#ifdef __ASSEMBLY__
26/* returns the offset of the flow controller halt register for a cpu */
27.macro cpu_to_halt_reg rd, rcpu
28 cmp \rcpu, #0
29 subne \rd, \rcpu, #1
30 movne \rd, \rd, lsl #3
31 addne \rd, \rd, #0x14
32 moveq \rd, #0
33.endm
34
35/* returns the offset of the flow controller csr register for a cpu */
36.macro cpu_to_csr_reg rd, rcpu
37 cmp \rcpu, #0
38 subne \rd, \rcpu, #1
39 movne \rd, \rd, lsl #3
40 addne \rd, \rd, #0x18
41 moveq \rd, #8
42.endm
43
44/* returns the ID of the current processor */
45.macro cpu_id, rd
46 mrc p15, 0, \rd, c0, c0, 5
47 and \rd, \rd, #0xF
48.endm
49
50/* loads a 32-bit value into a register without a data access */
51.macro mov32, reg, val
52 movw \reg, #:lower16:\val
53 movt \reg, #:upper16:\val
54.endm
55#endif
56#endif