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-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/boot/compressed/.gitignore1
-rw-r--r--arch/arm/common/Makefile1
-rw-r--r--arch/arm/common/scoop.c2
-rw-r--r--arch/arm/include/asm/assembler.h50
-rw-r--r--arch/arm/include/asm/atomic.h44
-rw-r--r--arch/arm/include/asm/cmpxchg.h6
-rw-r--r--arch/arm/include/asm/cputype.h20
-rw-r--r--arch/arm/include/asm/floppy.h2
-rw-r--r--arch/arm/include/asm/futex.h9
-rw-r--r--arch/arm/include/asm/hw_breakpoint.h1
-rw-r--r--arch/arm/include/asm/hwcap.h3
-rw-r--r--arch/arm/include/asm/jump_label.h1
-rw-r--r--arch/arm/include/asm/memory.h50
-rw-r--r--arch/arm/include/asm/pgtable-2level.h1
-rw-r--r--arch/arm/include/asm/pgtable.h7
-rw-r--r--arch/arm/include/asm/sync_bitops.h1
-rw-r--r--arch/arm/include/asm/system.h7
-rw-r--r--arch/arm/include/asm/uaccess.h2
-rw-r--r--arch/arm/include/asm/unistd.h1
-rw-r--r--arch/arm/include/uapi/asm/hwcap.h9
-rw-r--r--arch/arm/kernel/armksyms.c2
-rw-r--r--arch/arm/kernel/bios32.c37
-rw-r--r--arch/arm/kernel/crash_dump.c2
-rw-r--r--arch/arm/kernel/entry-header.S11
-rw-r--r--arch/arm/kernel/head-common.S12
-rw-r--r--arch/arm/kernel/head.S19
-rw-r--r--arch/arm/kernel/hw_breakpoint.c3
-rw-r--r--arch/arm/kernel/pj4-cp0.c4
-rw-r--r--arch/arm/kernel/process.c3
-rw-r--r--arch/arm/kernel/setup.c16
-rw-r--r--arch/arm/kernel/traps.c1
-rw-r--r--arch/arm/kernel/unwind.c137
-rw-r--r--arch/arm/lib/bitops.h5
-rw-r--r--arch/arm/lib/copy_template.S36
-rw-r--r--arch/arm/lib/csumpartialcopygeneric.S96
-rw-r--r--arch/arm/lib/io-readsl.S12
-rw-r--r--arch/arm/lib/io-writesl.S12
-rw-r--r--arch/arm/lib/memmove.S36
-rw-r--r--arch/arm/lib/uaccess.S192
-rw-r--r--arch/arm/mach-cns3xxx/core.c2
-rw-r--r--arch/arm/mach-ebsa110/core.c2
-rw-r--r--arch/arm/mach-footbridge/dc21285-timer.c6
-rw-r--r--arch/arm/mach-footbridge/dc21285.c10
-rw-r--r--arch/arm/mach-footbridge/isa-timer.c2
-rw-r--r--arch/arm/mach-gemini/idle.c2
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c2
-rw-r--r--arch/arm/mach-ixp4xx/common.c2
-rw-r--r--arch/arm/mach-ixp4xx/dsmg600-setup.c3
-rw-r--r--arch/arm/mach-ixp4xx/fsg-setup.c6
-rw-r--r--arch/arm/mach-ixp4xx/nas100d-setup.c3
-rw-r--r--arch/arm/mach-ixp4xx/nslu2-setup.c6
-rw-r--r--arch/arm/mach-ks8695/time.c2
-rw-r--r--arch/arm/mach-lpc32xx/timer.c2
-rw-r--r--arch/arm/mach-mmp/time.c2
-rw-r--r--arch/arm/mach-netx/time.c2
-rw-r--r--arch/arm/mach-omap1/dma.c191
-rw-r--r--arch/arm/mach-omap2/am35xx-emac.c1
-rw-r--r--arch/arm/mach-omap2/dma.c183
-rw-r--r--arch/arm/mach-rpc/dma.c2
-rw-r--r--arch/arm/mach-rpc/time.c1
-rw-r--r--arch/arm/mach-sa1100/collie.c33
-rw-r--r--arch/arm/mach-sa1100/h3100.c7
-rw-r--r--arch/arm/mach-sa1100/h3600.c7
-rw-r--r--arch/arm/mach-sa1100/h3xxx.c58
-rw-r--r--arch/arm/mach-sa1100/include/mach/collie.h4
-rw-r--r--arch/arm/mach-sa1100/include/mach/h3xxx.h11
-rw-r--r--arch/arm/mach-sa1100/time.c2
-rw-r--r--arch/arm/mach-spear/time.c2
-rw-r--r--arch/arm/mach-u300/timer.c2
-rw-r--r--arch/arm/mach-vexpress/Makefile3
-rw-r--r--arch/arm/mach-vexpress/dcscb.c13
-rw-r--r--arch/arm/mach-w90x900/time.c2
-rw-r--r--arch/arm/mm/Kconfig3
-rw-r--r--arch/arm/mm/cache-feroceon-l2.c4
-rw-r--r--arch/arm/mm/dma-mapping.c3
-rw-r--r--arch/arm/mm/dump.c50
-rw-r--r--arch/arm/mm/mmu.c10
-rw-r--r--arch/arm/mm/proc-macros.S19
-rw-r--r--arch/arm/mm/proc-v7-2level.S7
-rw-r--r--arch/arm/mm/proc-v7.S11
-rw-r--r--arch/arm/plat-iop/time.c2
-rw-r--r--arch/arm/plat-omap/dma.c17
-rw-r--r--arch/arm/vfp/entry.S25
-rw-r--r--arch/arm/vfp/vfphw.S19
85 files changed, 870 insertions, 732 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fac6890b315d..19369c87b85a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1581,6 +1581,7 @@ config BL_SWITCHER_DUMMY_IF
1581 1581
1582choice 1582choice
1583 prompt "Memory split" 1583 prompt "Memory split"
1584 depends on MMU
1584 default VMSPLIT_3G 1585 default VMSPLIT_3G
1585 help 1586 help
1586 Select the desired split between kernel and user memory. 1587 Select the desired split between kernel and user memory.
@@ -1598,6 +1599,7 @@ endchoice
1598 1599
1599config PAGE_OFFSET 1600config PAGE_OFFSET
1600 hex 1601 hex
1602 default PHYS_OFFSET if !MMU
1601 default 0x40000000 if VMSPLIT_1G 1603 default 0x40000000 if VMSPLIT_1G
1602 default 0x80000000 if VMSPLIT_2G 1604 default 0x80000000 if VMSPLIT_2G
1603 default 0xC0000000 1605 default 0xC0000000
diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore
index 47279aa96a6a..0714e0334e33 100644
--- a/arch/arm/boot/compressed/.gitignore
+++ b/arch/arm/boot/compressed/.gitignore
@@ -1,4 +1,5 @@
1ashldi3.S 1ashldi3.S
2bswapsdi2.S
2font.c 3font.c
3lib1funcs.S 4lib1funcs.S
4hyp-stub.S 5hyp-stub.S
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 4bdc41622c36..70b1eff477b3 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SHARP_SCOOP) += scoop.o
13obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o 13obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
14obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o 14obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
15obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o 15obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
16CFLAGS_REMOVE_mcpm_entry.o = -pg
16AFLAGS_mcpm_head.o := -march=armv7-a 17AFLAGS_mcpm_head.o := -march=armv7-a
17AFLAGS_vlock.o := -march=armv7-a 18AFLAGS_vlock.o := -march=armv7-a
18obj-$(CONFIG_TI_PRIV_EDMA) += edma.o 19obj-$(CONFIG_TI_PRIV_EDMA) += edma.o
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c
index a5c3dc38aa18..6ef146edd0cd 100644
--- a/arch/arm/common/scoop.c
+++ b/arch/arm/common/scoop.c
@@ -232,8 +232,6 @@ static int scoop_probe(struct platform_device *pdev)
232 232
233 return 0; 233 return 0;
234 234
235 if (devptr->gpio.base != -1)
236 temp = gpiochip_remove(&devptr->gpio);
237err_gpio: 235err_gpio:
238 platform_set_drvdata(pdev, NULL); 236 platform_set_drvdata(pdev, NULL);
239err_ioremap: 237err_ioremap:
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 5c2285160575..b974184f9941 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -23,6 +23,7 @@
23#include <asm/ptrace.h> 23#include <asm/ptrace.h>
24#include <asm/domain.h> 24#include <asm/domain.h>
25#include <asm/opcodes-virt.h> 25#include <asm/opcodes-virt.h>
26#include <asm/asm-offsets.h>
26 27
27#define IOMEM(x) (x) 28#define IOMEM(x) (x)
28 29
@@ -30,8 +31,8 @@
30 * Endian independent macros for shifting bytes within registers. 31 * Endian independent macros for shifting bytes within registers.
31 */ 32 */
32#ifndef __ARMEB__ 33#ifndef __ARMEB__
33#define pull lsr 34#define lspull lsr
34#define push lsl 35#define lspush lsl
35#define get_byte_0 lsl #0 36#define get_byte_0 lsl #0
36#define get_byte_1 lsr #8 37#define get_byte_1 lsr #8
37#define get_byte_2 lsr #16 38#define get_byte_2 lsr #16
@@ -41,8 +42,8 @@
41#define put_byte_2 lsl #16 42#define put_byte_2 lsl #16
42#define put_byte_3 lsl #24 43#define put_byte_3 lsl #24
43#else 44#else
44#define pull lsl 45#define lspull lsl
45#define push lsr 46#define lspush lsr
46#define get_byte_0 lsr #24 47#define get_byte_0 lsr #24
47#define get_byte_1 lsr #16 48#define get_byte_1 lsr #16
48#define get_byte_2 lsr #8 49#define get_byte_2 lsr #8
@@ -174,6 +175,47 @@
174 restore_irqs_notrace \oldcpsr 175 restore_irqs_notrace \oldcpsr
175 .endm 176 .endm
176 177
178/*
179 * Get current thread_info.
180 */
181 .macro get_thread_info, rd
182 ARM( mov \rd, sp, lsr #13 )
183 THUMB( mov \rd, sp )
184 THUMB( lsr \rd, \rd, #13 )
185 mov \rd, \rd, lsl #13
186 .endm
187
188/*
189 * Increment/decrement the preempt count.
190 */
191#ifdef CONFIG_PREEMPT_COUNT
192 .macro inc_preempt_count, ti, tmp
193 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
194 add \tmp, \tmp, #1 @ increment it
195 str \tmp, [\ti, #TI_PREEMPT]
196 .endm
197
198 .macro dec_preempt_count, ti, tmp
199 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
200 sub \tmp, \tmp, #1 @ decrement it
201 str \tmp, [\ti, #TI_PREEMPT]
202 .endm
203
204 .macro dec_preempt_count_ti, ti, tmp
205 get_thread_info \ti
206 dec_preempt_count \ti, \tmp
207 .endm
208#else
209 .macro inc_preempt_count, ti, tmp
210 .endm
211
212 .macro dec_preempt_count, ti, tmp
213 .endm
214
215 .macro dec_preempt_count_ti, ti, tmp
216 .endm
217#endif
218
177#define USER(x...) \ 219#define USER(x...) \
1789999: x; \ 2209999: x; \
179 .pushsection __ex_table,"a"; \ 221 .pushsection __ex_table,"a"; \
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index 62d2cb53b069..9a92fd7864a8 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -60,6 +60,7 @@ static inline int atomic_add_return(int i, atomic_t *v)
60 int result; 60 int result;
61 61
62 smp_mb(); 62 smp_mb();
63 prefetchw(&v->counter);
63 64
64 __asm__ __volatile__("@ atomic_add_return\n" 65 __asm__ __volatile__("@ atomic_add_return\n"
65"1: ldrex %0, [%3]\n" 66"1: ldrex %0, [%3]\n"
@@ -99,6 +100,7 @@ static inline int atomic_sub_return(int i, atomic_t *v)
99 int result; 100 int result;
100 101
101 smp_mb(); 102 smp_mb();
103 prefetchw(&v->counter);
102 104
103 __asm__ __volatile__("@ atomic_sub_return\n" 105 __asm__ __volatile__("@ atomic_sub_return\n"
104"1: ldrex %0, [%3]\n" 106"1: ldrex %0, [%3]\n"
@@ -121,6 +123,7 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
121 unsigned long res; 123 unsigned long res;
122 124
123 smp_mb(); 125 smp_mb();
126 prefetchw(&ptr->counter);
124 127
125 do { 128 do {
126 __asm__ __volatile__("@ atomic_cmpxchg\n" 129 __asm__ __volatile__("@ atomic_cmpxchg\n"
@@ -138,6 +141,33 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
138 return oldval; 141 return oldval;
139} 142}
140 143
144static inline int __atomic_add_unless(atomic_t *v, int a, int u)
145{
146 int oldval, newval;
147 unsigned long tmp;
148
149 smp_mb();
150 prefetchw(&v->counter);
151
152 __asm__ __volatile__ ("@ atomic_add_unless\n"
153"1: ldrex %0, [%4]\n"
154" teq %0, %5\n"
155" beq 2f\n"
156" add %1, %0, %6\n"
157" strex %2, %1, [%4]\n"
158" teq %2, #0\n"
159" bne 1b\n"
160"2:"
161 : "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter)
162 : "r" (&v->counter), "r" (u), "r" (a)
163 : "cc");
164
165 if (oldval != u)
166 smp_mb();
167
168 return oldval;
169}
170
141#else /* ARM_ARCH_6 */ 171#else /* ARM_ARCH_6 */
142 172
143#ifdef CONFIG_SMP 173#ifdef CONFIG_SMP
@@ -186,10 +216,6 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
186 return ret; 216 return ret;
187} 217}
188 218
189#endif /* __LINUX_ARM_ARCH__ */
190
191#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
192
193static inline int __atomic_add_unless(atomic_t *v, int a, int u) 219static inline int __atomic_add_unless(atomic_t *v, int a, int u)
194{ 220{
195 int c, old; 221 int c, old;
@@ -200,6 +226,10 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u)
200 return c; 226 return c;
201} 227}
202 228
229#endif /* __LINUX_ARM_ARCH__ */
230
231#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
232
203#define atomic_inc(v) atomic_add(1, v) 233#define atomic_inc(v) atomic_add(1, v)
204#define atomic_dec(v) atomic_sub(1, v) 234#define atomic_dec(v) atomic_sub(1, v)
205 235
@@ -299,6 +329,7 @@ static inline long long atomic64_add_return(long long i, atomic64_t *v)
299 unsigned long tmp; 329 unsigned long tmp;
300 330
301 smp_mb(); 331 smp_mb();
332 prefetchw(&v->counter);
302 333
303 __asm__ __volatile__("@ atomic64_add_return\n" 334 __asm__ __volatile__("@ atomic64_add_return\n"
304"1: ldrexd %0, %H0, [%3]\n" 335"1: ldrexd %0, %H0, [%3]\n"
@@ -340,6 +371,7 @@ static inline long long atomic64_sub_return(long long i, atomic64_t *v)
340 unsigned long tmp; 371 unsigned long tmp;
341 372
342 smp_mb(); 373 smp_mb();
374 prefetchw(&v->counter);
343 375
344 __asm__ __volatile__("@ atomic64_sub_return\n" 376 __asm__ __volatile__("@ atomic64_sub_return\n"
345"1: ldrexd %0, %H0, [%3]\n" 377"1: ldrexd %0, %H0, [%3]\n"
@@ -364,6 +396,7 @@ static inline long long atomic64_cmpxchg(atomic64_t *ptr, long long old,
364 unsigned long res; 396 unsigned long res;
365 397
366 smp_mb(); 398 smp_mb();
399 prefetchw(&ptr->counter);
367 400
368 do { 401 do {
369 __asm__ __volatile__("@ atomic64_cmpxchg\n" 402 __asm__ __volatile__("@ atomic64_cmpxchg\n"
@@ -388,6 +421,7 @@ static inline long long atomic64_xchg(atomic64_t *ptr, long long new)
388 unsigned long tmp; 421 unsigned long tmp;
389 422
390 smp_mb(); 423 smp_mb();
424 prefetchw(&ptr->counter);
391 425
392 __asm__ __volatile__("@ atomic64_xchg\n" 426 __asm__ __volatile__("@ atomic64_xchg\n"
393"1: ldrexd %0, %H0, [%3]\n" 427"1: ldrexd %0, %H0, [%3]\n"
@@ -409,6 +443,7 @@ static inline long long atomic64_dec_if_positive(atomic64_t *v)
409 unsigned long tmp; 443 unsigned long tmp;
410 444
411 smp_mb(); 445 smp_mb();
446 prefetchw(&v->counter);
412 447
413 __asm__ __volatile__("@ atomic64_dec_if_positive\n" 448 __asm__ __volatile__("@ atomic64_dec_if_positive\n"
414"1: ldrexd %0, %H0, [%3]\n" 449"1: ldrexd %0, %H0, [%3]\n"
@@ -436,6 +471,7 @@ static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
436 int ret = 1; 471 int ret = 1;
437 472
438 smp_mb(); 473 smp_mb();
474 prefetchw(&v->counter);
439 475
440 __asm__ __volatile__("@ atomic64_add_unless\n" 476 __asm__ __volatile__("@ atomic64_add_unless\n"
441"1: ldrexd %0, %H0, [%4]\n" 477"1: ldrexd %0, %H0, [%4]\n"
diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
index df2fbba7efc8..abb2c3769b01 100644
--- a/arch/arm/include/asm/cmpxchg.h
+++ b/arch/arm/include/asm/cmpxchg.h
@@ -2,6 +2,7 @@
2#define __ASM_ARM_CMPXCHG_H 2#define __ASM_ARM_CMPXCHG_H
3 3
4#include <linux/irqflags.h> 4#include <linux/irqflags.h>
5#include <linux/prefetch.h>
5#include <asm/barrier.h> 6#include <asm/barrier.h>
6 7
7#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) 8#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
@@ -35,6 +36,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
35#endif 36#endif
36 37
37 smp_mb(); 38 smp_mb();
39 prefetchw((const void *)ptr);
38 40
39 switch (size) { 41 switch (size) {
40#if __LINUX_ARM_ARCH__ >= 6 42#if __LINUX_ARM_ARCH__ >= 6
@@ -138,6 +140,8 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
138{ 140{
139 unsigned long oldval, res; 141 unsigned long oldval, res;
140 142
143 prefetchw((const void *)ptr);
144
141 switch (size) { 145 switch (size) {
142#ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */ 146#ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */
143 case 1: 147 case 1:
@@ -230,6 +234,8 @@ static inline unsigned long long __cmpxchg64(unsigned long long *ptr,
230 unsigned long long oldval; 234 unsigned long long oldval;
231 unsigned long res; 235 unsigned long res;
232 236
237 prefetchw(ptr);
238
233 __asm__ __volatile__( 239 __asm__ __volatile__(
234"1: ldrexd %1, %H1, [%3]\n" 240"1: ldrexd %1, %H1, [%3]\n"
235" teq %1, %4\n" 241" teq %1, %4\n"
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index acdde76b39bb..c651e3b26ec7 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -71,6 +71,7 @@
71#define ARM_CPU_PART_CORTEX_A5 0xC050 71#define ARM_CPU_PART_CORTEX_A5 0xC050
72#define ARM_CPU_PART_CORTEX_A15 0xC0F0 72#define ARM_CPU_PART_CORTEX_A15 0xC0F0
73#define ARM_CPU_PART_CORTEX_A7 0xC070 73#define ARM_CPU_PART_CORTEX_A7 0xC070
74#define ARM_CPU_PART_CORTEX_A12 0xC0D0
74 75
75#define ARM_CPU_XSCALE_ARCH_MASK 0xe000 76#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
76#define ARM_CPU_XSCALE_ARCH_V1 0x2000 77#define ARM_CPU_XSCALE_ARCH_V1 0x2000
@@ -220,4 +221,23 @@ static inline int cpu_is_xsc3(void)
220#define cpu_is_xscale() 1 221#define cpu_is_xscale() 1
221#endif 222#endif
222 223
224/*
225 * Marvell's PJ4 core is based on V7 version. It has some modification
226 * for coprocessor setting. For this reason, we need a way to distinguish
227 * it.
228 */
229#ifndef CONFIG_CPU_PJ4
230#define cpu_is_pj4() 0
231#else
232static inline int cpu_is_pj4(void)
233{
234 unsigned int id;
235
236 id = read_cpuid_id();
237 if ((id & 0xfffffff0) == 0x562f5840)
238 return 1;
239
240 return 0;
241}
242#endif
223#endif 243#endif
diff --git a/arch/arm/include/asm/floppy.h b/arch/arm/include/asm/floppy.h
index c9f03eccc9d8..f4882553fbb0 100644
--- a/arch/arm/include/asm/floppy.h
+++ b/arch/arm/include/asm/floppy.h
@@ -25,7 +25,7 @@
25 25
26#define fd_inb(port) inb((port)) 26#define fd_inb(port) inb((port))
27#define fd_request_irq() request_irq(IRQ_FLOPPYDISK,floppy_interrupt,\ 27#define fd_request_irq() request_irq(IRQ_FLOPPYDISK,floppy_interrupt,\
28 IRQF_DISABLED,"floppy",NULL) 28 0,"floppy",NULL)
29#define fd_free_irq() free_irq(IRQ_FLOPPYDISK,NULL) 29#define fd_free_irq() free_irq(IRQ_FLOPPYDISK,NULL)
30#define fd_disable_irq() disable_irq(IRQ_FLOPPYDISK) 30#define fd_disable_irq() disable_irq(IRQ_FLOPPYDISK)
31#define fd_enable_irq() enable_irq(IRQ_FLOPPYDISK) 31#define fd_enable_irq() enable_irq(IRQ_FLOPPYDISK)
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index e42cf597f6e6..53e69dae796f 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -3,11 +3,6 @@
3 3
4#ifdef __KERNEL__ 4#ifdef __KERNEL__
5 5
6#if defined(CONFIG_CPU_USE_DOMAINS) && defined(CONFIG_SMP)
7/* ARM doesn't provide unprivileged exclusive memory accessors */
8#include <asm-generic/futex.h>
9#else
10
11#include <linux/futex.h> 6#include <linux/futex.h>
12#include <linux/uaccess.h> 7#include <linux/uaccess.h>
13#include <asm/errno.h> 8#include <asm/errno.h>
@@ -28,6 +23,7 @@
28 23
29#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ 24#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
30 smp_mb(); \ 25 smp_mb(); \
26 prefetchw(uaddr); \
31 __asm__ __volatile__( \ 27 __asm__ __volatile__( \
32 "1: ldrex %1, [%3]\n" \ 28 "1: ldrex %1, [%3]\n" \
33 " " insn "\n" \ 29 " " insn "\n" \
@@ -51,6 +47,8 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
51 return -EFAULT; 47 return -EFAULT;
52 48
53 smp_mb(); 49 smp_mb();
50 /* Prefetching cannot fault */
51 prefetchw(uaddr);
54 __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" 52 __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
55 "1: ldrex %1, [%4]\n" 53 "1: ldrex %1, [%4]\n"
56 " teq %1, %2\n" 54 " teq %1, %2\n"
@@ -164,6 +162,5 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
164 return ret; 162 return ret;
165} 163}
166 164
167#endif /* !(CPU_USE_DOMAINS && SMP) */
168#endif /* __KERNEL__ */ 165#endif /* __KERNEL__ */
169#endif /* _ASM_ARM_FUTEX_H */ 166#endif /* _ASM_ARM_FUTEX_H */
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
index eef55ea9ef00..8e427c7b4425 100644
--- a/arch/arm/include/asm/hw_breakpoint.h
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -51,6 +51,7 @@ static inline void decode_ctrl_reg(u32 reg,
51#define ARM_DEBUG_ARCH_V7_ECP14 3 51#define ARM_DEBUG_ARCH_V7_ECP14 3
52#define ARM_DEBUG_ARCH_V7_MM 4 52#define ARM_DEBUG_ARCH_V7_MM 4
53#define ARM_DEBUG_ARCH_V7_1 5 53#define ARM_DEBUG_ARCH_V7_1 5
54#define ARM_DEBUG_ARCH_V8 6
54 55
55/* Breakpoint */ 56/* Breakpoint */
56#define ARM_BREAKPOINT_EXECUTE 0 57#define ARM_BREAKPOINT_EXECUTE 0
diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index 6ff56eca3f1f..6e183fd269fb 100644
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -9,6 +9,7 @@
9 * instruction set this cpu supports. 9 * instruction set this cpu supports.
10 */ 10 */
11#define ELF_HWCAP (elf_hwcap) 11#define ELF_HWCAP (elf_hwcap)
12extern unsigned int elf_hwcap; 12#define ELF_HWCAP2 (elf_hwcap2)
13extern unsigned int elf_hwcap, elf_hwcap2;
13#endif 14#endif
14#endif 15#endif
diff --git a/arch/arm/include/asm/jump_label.h b/arch/arm/include/asm/jump_label.h
index 863c892b4aaa..70f9b9bfb1f9 100644
--- a/arch/arm/include/asm/jump_label.h
+++ b/arch/arm/include/asm/jump_label.h
@@ -4,7 +4,6 @@
4#ifdef __KERNEL__ 4#ifdef __KERNEL__
5 5
6#include <linux/types.h> 6#include <linux/types.h>
7#include <asm/system.h>
8 7
9#define JUMP_LABEL_NOP_SIZE 4 8#define JUMP_LABEL_NOP_SIZE 4
10 9
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 8756e4bcdba0..02fa2558f662 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -30,14 +30,15 @@
30 */ 30 */
31#define UL(x) _AC(x, UL) 31#define UL(x) _AC(x, UL)
32 32
33/* PAGE_OFFSET - the virtual address of the start of the kernel image */
34#define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)
35
33#ifdef CONFIG_MMU 36#ifdef CONFIG_MMU
34 37
35/* 38/*
36 * PAGE_OFFSET - the virtual address of the start of the kernel image
37 * TASK_SIZE - the maximum size of a user space task. 39 * TASK_SIZE - the maximum size of a user space task.
38 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area 40 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
39 */ 41 */
40#define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)
41#define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M)) 42#define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M))
42#define TASK_UNMAPPED_BASE ALIGN(TASK_SIZE / 3, SZ_16M) 43#define TASK_UNMAPPED_BASE ALIGN(TASK_SIZE / 3, SZ_16M)
43 44
@@ -104,10 +105,6 @@
104#define END_MEM (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE) 105#define END_MEM (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE)
105#endif 106#endif
106 107
107#ifndef PAGE_OFFSET
108#define PAGE_OFFSET PLAT_PHYS_OFFSET
109#endif
110
111/* 108/*
112 * The module can be at any place in ram in nommu mode. 109 * The module can be at any place in ram in nommu mode.
113 */ 110 */
@@ -169,9 +166,17 @@
169 * Physical vs virtual RAM address space conversion. These are 166 * Physical vs virtual RAM address space conversion. These are
170 * private definitions which should NOT be used outside memory.h 167 * private definitions which should NOT be used outside memory.h
171 * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. 168 * files. Use virt_to_phys/phys_to_virt/__pa/__va instead.
169 *
170 * PFNs are used to describe any physical page; this means
171 * PFN 0 == physical address 0.
172 */ 172 */
173#ifndef __virt_to_phys 173#if defined(__virt_to_phys)
174#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 174#define PHYS_OFFSET PLAT_PHYS_OFFSET
175#define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
176
177#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
178
179#elif defined(CONFIG_ARM_PATCH_PHYS_VIRT)
175 180
176/* 181/*
177 * Constants used to force the right instruction encodings and shifts 182 * Constants used to force the right instruction encodings and shifts
@@ -180,12 +185,17 @@
180#define __PV_BITS_31_24 0x81000000 185#define __PV_BITS_31_24 0x81000000
181#define __PV_BITS_7_0 0x81 186#define __PV_BITS_7_0 0x81
182 187
183extern u64 __pv_phys_offset; 188extern unsigned long __pv_phys_pfn_offset;
184extern u64 __pv_offset; 189extern u64 __pv_offset;
185extern void fixup_pv_table(const void *, unsigned long); 190extern void fixup_pv_table(const void *, unsigned long);
186extern const void *__pv_table_begin, *__pv_table_end; 191extern const void *__pv_table_begin, *__pv_table_end;
187 192
188#define PHYS_OFFSET __pv_phys_offset 193#define PHYS_OFFSET ((phys_addr_t)__pv_phys_pfn_offset << PAGE_SHIFT)
194#define PHYS_PFN_OFFSET (__pv_phys_pfn_offset)
195
196#define virt_to_pfn(kaddr) \
197 ((((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT) + \
198 PHYS_PFN_OFFSET)
189 199
190#define __pv_stub(from,to,instr,type) \ 200#define __pv_stub(from,to,instr,type) \
191 __asm__("@ __pv_stub\n" \ 201 __asm__("@ __pv_stub\n" \
@@ -246,6 +256,7 @@ static inline unsigned long __phys_to_virt(phys_addr_t x)
246#else 256#else
247 257
248#define PHYS_OFFSET PLAT_PHYS_OFFSET 258#define PHYS_OFFSET PLAT_PHYS_OFFSET
259#define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
249 260
250static inline phys_addr_t __virt_to_phys(unsigned long x) 261static inline phys_addr_t __virt_to_phys(unsigned long x)
251{ 262{
@@ -257,18 +268,11 @@ static inline unsigned long __phys_to_virt(phys_addr_t x)
257 return x - PHYS_OFFSET + PAGE_OFFSET; 268 return x - PHYS_OFFSET + PAGE_OFFSET;
258} 269}
259 270
260#endif 271#define virt_to_pfn(kaddr) \
261#endif 272 ((((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT) + \
273 PHYS_PFN_OFFSET)
262 274
263/* 275#endif
264 * PFNs are used to describe any physical page; this means
265 * PFN 0 == physical address 0.
266 *
267 * This is the PFN of the first RAM page in the kernel
268 * direct-mapped view. We assume this is the first page
269 * of RAM in the mem_map as well.
270 */
271#define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
272 276
273/* 277/*
274 * These are *only* valid on the kernel direct mapped RAM memory. 278 * These are *only* valid on the kernel direct mapped RAM memory.
@@ -346,9 +350,9 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
346 */ 350 */
347#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET 351#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET
348 352
349#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) 353#define virt_to_page(kaddr) pfn_to_page(virt_to_pfn(kaddr))
350#define virt_addr_valid(kaddr) (((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory) \ 354#define virt_addr_valid(kaddr) (((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory) \
351 && pfn_valid(__pa(kaddr) >> PAGE_SHIFT) ) 355 && pfn_valid(virt_to_pfn(kaddr)))
352 356
353#endif 357#endif
354 358
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index dfff709fda3c..219ac88a9542 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -140,6 +140,7 @@
140#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ 140#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
141#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ 141#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */
142#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ 142#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */
143#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x0f) << 2) /* 1111 */
143#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) 144#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
144 145
145#ifndef __ASSEMBLY__ 146#ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 7d59b524f2af..5478e5d6ad89 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -216,13 +216,16 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
216 216
217#define pte_none(pte) (!pte_val(pte)) 217#define pte_none(pte) (!pte_val(pte))
218#define pte_present(pte) (pte_val(pte) & L_PTE_PRESENT) 218#define pte_present(pte) (pte_val(pte) & L_PTE_PRESENT)
219#define pte_valid(pte) (pte_val(pte) & L_PTE_VALID)
220#define pte_accessible(mm, pte) (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
219#define pte_write(pte) (!(pte_val(pte) & L_PTE_RDONLY)) 221#define pte_write(pte) (!(pte_val(pte) & L_PTE_RDONLY))
220#define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY) 222#define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY)
221#define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG) 223#define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG)
222#define pte_exec(pte) (!(pte_val(pte) & L_PTE_XN)) 224#define pte_exec(pte) (!(pte_val(pte) & L_PTE_XN))
223#define pte_special(pte) (0) 225#define pte_special(pte) (0)
224 226
225#define pte_present_user(pte) (pte_present(pte) && (pte_val(pte) & L_PTE_USER)) 227#define pte_valid_user(pte) \
228 (pte_valid(pte) && (pte_val(pte) & L_PTE_USER) && pte_young(pte))
226 229
227#if __LINUX_ARM_ARCH__ < 6 230#if __LINUX_ARM_ARCH__ < 6
228static inline void __sync_icache_dcache(pte_t pteval) 231static inline void __sync_icache_dcache(pte_t pteval)
@@ -237,7 +240,7 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
237{ 240{
238 unsigned long ext = 0; 241 unsigned long ext = 0;
239 242
240 if (addr < TASK_SIZE && pte_present_user(pteval)) { 243 if (addr < TASK_SIZE && pte_valid_user(pteval)) {
241 __sync_icache_dcache(pteval); 244 __sync_icache_dcache(pteval);
242 ext |= PTE_EXT_NG; 245 ext |= PTE_EXT_NG;
243 } 246 }
diff --git a/arch/arm/include/asm/sync_bitops.h b/arch/arm/include/asm/sync_bitops.h
index 63479eecbf76..9732b8e11e63 100644
--- a/arch/arm/include/asm/sync_bitops.h
+++ b/arch/arm/include/asm/sync_bitops.h
@@ -2,7 +2,6 @@
2#define __ASM_SYNC_BITOPS_H__ 2#define __ASM_SYNC_BITOPS_H__
3 3
4#include <asm/bitops.h> 4#include <asm/bitops.h>
5#include <asm/system.h>
6 5
7/* sync_bitops functions are equivalent to the SMP implementation of the 6/* sync_bitops functions are equivalent to the SMP implementation of the
8 * original functions, independently from CONFIG_SMP being defined. 7 * original functions, independently from CONFIG_SMP being defined.
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
deleted file mode 100644
index 368165e33c1c..000000000000
--- a/arch/arm/include/asm/system.h
+++ /dev/null
@@ -1,7 +0,0 @@
1/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
2#include <asm/barrier.h>
3#include <asm/compiler.h>
4#include <asm/cmpxchg.h>
5#include <asm/switch_to.h>
6#include <asm/system_info.h>
7#include <asm/system_misc.h>
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 72abdc541f38..12c3a5decc60 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -19,7 +19,7 @@
19#include <asm/unified.h> 19#include <asm/unified.h>
20#include <asm/compiler.h> 20#include <asm/compiler.h>
21 21
22#if __LINUX_ARM_ARCH__ < 6 22#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
23#include <asm-generic/uaccess-unaligned.h> 23#include <asm-generic/uaccess-unaligned.h>
24#else 24#else
25#define __get_user_unaligned __get_user 25#define __get_user_unaligned __get_user
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index acabef1a75df..43876245fc57 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -48,6 +48,5 @@
48 */ 48 */
49#define __IGNORE_fadvise64_64 49#define __IGNORE_fadvise64_64
50#define __IGNORE_migrate_pages 50#define __IGNORE_migrate_pages
51#define __IGNORE_kcmp
52 51
53#endif /* __ASM_ARM_UNISTD_H */ 52#endif /* __ASM_ARM_UNISTD_H */
diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index 7dcc10d67253..20d12f230a2f 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -28,4 +28,13 @@
28#define HWCAP_LPAE (1 << 20) 28#define HWCAP_LPAE (1 << 20)
29#define HWCAP_EVTSTRM (1 << 21) 29#define HWCAP_EVTSTRM (1 << 21)
30 30
31/*
32 * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2
33 */
34#define HWCAP2_AES (1 << 0)
35#define HWCAP2_PMULL (1 << 1)
36#define HWCAP2_SHA1 (1 << 2)
37#define HWCAP2_SHA2 (1 << 3)
38#define HWCAP2_CRC32 (1 << 4)
39
31#endif /* _UAPI__ASMARM_HWCAP_H */ 40#endif /* _UAPI__ASMARM_HWCAP_H */
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 85e664b6a5f1..f7b450f97e68 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -158,6 +158,6 @@ EXPORT_SYMBOL(__gnu_mcount_nc);
158#endif 158#endif
159 159
160#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 160#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
161EXPORT_SYMBOL(__pv_phys_offset); 161EXPORT_SYMBOL(__pv_phys_pfn_offset);
162EXPORT_SYMBOL(__pv_offset); 162EXPORT_SYMBOL(__pv_offset);
163#endif 163#endif
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 317da88ae65b..91f48804e3bb 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -608,41 +608,10 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
608 */ 608 */
609int pcibios_enable_device(struct pci_dev *dev, int mask) 609int pcibios_enable_device(struct pci_dev *dev, int mask)
610{ 610{
611 u16 cmd, old_cmd; 611 if (pci_has_flag(PCI_PROBE_ONLY))
612 int idx; 612 return 0;
613 struct resource *r;
614
615 pci_read_config_word(dev, PCI_COMMAND, &cmd);
616 old_cmd = cmd;
617 for (idx = 0; idx < 6; idx++) {
618 /* Only set up the requested stuff */
619 if (!(mask & (1 << idx)))
620 continue;
621
622 r = dev->resource + idx;
623 if (!r->start && r->end) {
624 printk(KERN_ERR "PCI: Device %s not available because"
625 " of resource collisions\n", pci_name(dev));
626 return -EINVAL;
627 }
628 if (r->flags & IORESOURCE_IO)
629 cmd |= PCI_COMMAND_IO;
630 if (r->flags & IORESOURCE_MEM)
631 cmd |= PCI_COMMAND_MEMORY;
632 }
633 613
634 /* 614 return pci_enable_resources(dev, mask);
635 * Bridges (eg, cardbus bridges) need to be fully enabled
636 */
637 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
638 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
639
640 if (cmd != old_cmd) {
641 printk("PCI: enabling device %s (%04x -> %04x)\n",
642 pci_name(dev), old_cmd, cmd);
643 pci_write_config_word(dev, PCI_COMMAND, cmd);
644 }
645 return 0;
646} 615}
647 616
648int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 617int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
diff --git a/arch/arm/kernel/crash_dump.c b/arch/arm/kernel/crash_dump.c
index 90c50d4b43f7..5d1286d51154 100644
--- a/arch/arm/kernel/crash_dump.c
+++ b/arch/arm/kernel/crash_dump.c
@@ -39,7 +39,7 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
39 if (!csize) 39 if (!csize)
40 return 0; 40 return 0;
41 41
42 vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE); 42 vaddr = ioremap(__pfn_to_phys(pfn), PAGE_SIZE);
43 if (!vaddr) 43 if (!vaddr)
44 return -ENOMEM; 44 return -ENOMEM;
45 45
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 39f89fbd5111..1420725142ca 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -236,11 +236,6 @@
236 movs pc, lr @ return & move spsr_svc into cpsr 236 movs pc, lr @ return & move spsr_svc into cpsr
237 .endm 237 .endm
238 238
239 .macro get_thread_info, rd
240 mov \rd, sp, lsr #13
241 mov \rd, \rd, lsl #13
242 .endm
243
244 @ 239 @
245 @ 32-bit wide "mov pc, reg" 240 @ 32-bit wide "mov pc, reg"
246 @ 241 @
@@ -306,12 +301,6 @@
306 .endm 301 .endm
307#endif /* ifdef CONFIG_CPU_V7M / else */ 302#endif /* ifdef CONFIG_CPU_V7M / else */
308 303
309 .macro get_thread_info, rd
310 mov \rd, sp
311 lsr \rd, \rd, #13
312 mov \rd, \rd, lsl #13
313 .endm
314
315 @ 304 @
316 @ 32-bit wide "mov pc, reg" 305 @ 32-bit wide "mov pc, reg"
317 @ 306 @
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 47cd974e57ea..c96ecacb2021 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -177,6 +177,18 @@ __lookup_processor_type_data:
177 .long __proc_info_end 177 .long __proc_info_end
178 .size __lookup_processor_type_data, . - __lookup_processor_type_data 178 .size __lookup_processor_type_data, . - __lookup_processor_type_data
179 179
180__error_lpae:
181#ifdef CONFIG_DEBUG_LL
182 adr r0, str_lpae
183 bl printascii
184 b __error
185str_lpae: .asciz "\nError: Kernel with LPAE support, but CPU does not support LPAE.\n"
186#else
187 b __error
188#endif
189 .align
190ENDPROC(__error_lpae)
191
180__error_p: 192__error_p:
181#ifdef CONFIG_DEBUG_LL 193#ifdef CONFIG_DEBUG_LL
182 adr r0, str_p1 194 adr r0, str_p1
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 914616e0bdcd..f8c08839edf3 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -102,7 +102,7 @@ ENTRY(stext)
102 and r3, r3, #0xf @ extract VMSA support 102 and r3, r3, #0xf @ extract VMSA support
103 cmp r3, #5 @ long-descriptor translation table format? 103 cmp r3, #5 @ long-descriptor translation table format?
104 THUMB( it lo ) @ force fixup-able long branch encoding 104 THUMB( it lo ) @ force fixup-able long branch encoding
105 blo __error_p @ only classic page table format 105 blo __error_lpae @ only classic page table format
106#endif 106#endif
107 107
108#ifndef CONFIG_XIP_KERNEL 108#ifndef CONFIG_XIP_KERNEL
@@ -584,9 +584,10 @@ __fixup_pv_table:
584 subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET 584 subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
585 add r4, r4, r3 @ adjust table start address 585 add r4, r4, r3 @ adjust table start address
586 add r5, r5, r3 @ adjust table end address 586 add r5, r5, r3 @ adjust table end address
587 add r6, r6, r3 @ adjust __pv_phys_offset address 587 add r6, r6, r3 @ adjust __pv_phys_pfn_offset address
588 add r7, r7, r3 @ adjust __pv_offset address 588 add r7, r7, r3 @ adjust __pv_offset address
589 str r8, [r6, #LOW_OFFSET] @ save computed PHYS_OFFSET to __pv_phys_offset 589 mov r0, r8, lsr #12 @ convert to PFN
590 str r0, [r6, #LOW_OFFSET] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset
590 strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits 591 strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits
591 mov r6, r3, lsr #24 @ constant for add/sub instructions 592 mov r6, r3, lsr #24 @ constant for add/sub instructions
592 teq r3, r6, lsl #24 @ must be 16MiB aligned 593 teq r3, r6, lsl #24 @ must be 16MiB aligned
@@ -600,7 +601,7 @@ ENDPROC(__fixup_pv_table)
6001: .long . 6011: .long .
601 .long __pv_table_begin 602 .long __pv_table_begin
602 .long __pv_table_end 603 .long __pv_table_end
6032: .long __pv_phys_offset 6042: .long __pv_phys_pfn_offset
604 .long __pv_offset 605 .long __pv_offset
605 606
606 .text 607 .text
@@ -688,11 +689,11 @@ ENTRY(fixup_pv_table)
688ENDPROC(fixup_pv_table) 689ENDPROC(fixup_pv_table)
689 690
690 .data 691 .data
691 .globl __pv_phys_offset 692 .globl __pv_phys_pfn_offset
692 .type __pv_phys_offset, %object 693 .type __pv_phys_pfn_offset, %object
693__pv_phys_offset: 694__pv_phys_pfn_offset:
694 .quad 0 695 .word 0
695 .size __pv_phys_offset, . -__pv_phys_offset 696 .size __pv_phys_pfn_offset, . -__pv_phys_pfn_offset
696 697
697 .globl __pv_offset 698 .globl __pv_offset
698 .type __pv_offset, %object 699 .type __pv_offset, %object
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 3d446605cbf8..9da35c6d3411 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -167,7 +167,7 @@ static int debug_arch_supported(void)
167/* Can we determine the watchpoint access type from the fsr? */ 167/* Can we determine the watchpoint access type from the fsr? */
168static int debug_exception_updates_fsr(void) 168static int debug_exception_updates_fsr(void)
169{ 169{
170 return 0; 170 return get_debug_arch() >= ARM_DEBUG_ARCH_V8;
171} 171}
172 172
173/* Determine number of WRP registers available. */ 173/* Determine number of WRP registers available. */
@@ -257,6 +257,7 @@ static int enable_monitor_mode(void)
257 break; 257 break;
258 case ARM_DEBUG_ARCH_V7_ECP14: 258 case ARM_DEBUG_ARCH_V7_ECP14:
259 case ARM_DEBUG_ARCH_V7_1: 259 case ARM_DEBUG_ARCH_V7_1:
260 case ARM_DEBUG_ARCH_V8:
260 ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN)); 261 ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN));
261 isb(); 262 isb();
262 break; 263 break;
diff --git a/arch/arm/kernel/pj4-cp0.c b/arch/arm/kernel/pj4-cp0.c
index 679cf4d18c08..fc7208636284 100644
--- a/arch/arm/kernel/pj4-cp0.c
+++ b/arch/arm/kernel/pj4-cp0.c
@@ -17,6 +17,7 @@
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <asm/thread_notify.h> 19#include <asm/thread_notify.h>
20#include <asm/cputype.h>
20 21
21static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t) 22static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
22{ 23{
@@ -80,6 +81,9 @@ static int __init pj4_cp0_init(void)
80{ 81{
81 u32 cp_access; 82 u32 cp_access;
82 83
84 if (!cpu_is_pj4())
85 return 0;
86
83 cp_access = pj4_cp_access_read() & ~0xf; 87 cp_access = pj4_cp_access_read() & ~0xf;
84 pj4_cp_access_write(cp_access); 88 pj4_cp_access_write(cp_access);
85 89
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 204f7d273319..639bf32689dd 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -39,6 +39,7 @@
39#include <asm/processor.h> 39#include <asm/processor.h>
40#include <asm/thread_notify.h> 40#include <asm/thread_notify.h>
41#include <asm/stacktrace.h> 41#include <asm/stacktrace.h>
42#include <asm/system_misc.h>
42#include <asm/mach/time.h> 43#include <asm/mach/time.h>
43#include <asm/tls.h> 44#include <asm/tls.h>
44 45
@@ -100,7 +101,7 @@ void soft_restart(unsigned long addr)
100 u64 *stack = soft_restart_stack + ARRAY_SIZE(soft_restart_stack); 101 u64 *stack = soft_restart_stack + ARRAY_SIZE(soft_restart_stack);
101 102
102 /* Disable interrupts first */ 103 /* Disable interrupts first */
103 local_irq_disable(); 104 raw_local_irq_disable();
104 local_fiq_disable(); 105 local_fiq_disable();
105 106
106 /* Disable the L2 if we're the last man standing. */ 107 /* Disable the L2 if we're the last man standing. */
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 1e8b030dbefd..50e198c1e9c8 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -100,6 +100,9 @@ EXPORT_SYMBOL(system_serial_high);
100unsigned int elf_hwcap __read_mostly; 100unsigned int elf_hwcap __read_mostly;
101EXPORT_SYMBOL(elf_hwcap); 101EXPORT_SYMBOL(elf_hwcap);
102 102
103unsigned int elf_hwcap2 __read_mostly;
104EXPORT_SYMBOL(elf_hwcap2);
105
103 106
104#ifdef MULTI_CPU 107#ifdef MULTI_CPU
105struct processor processor __read_mostly; 108struct processor processor __read_mostly;
@@ -1005,6 +1008,15 @@ static const char *hwcap_str[] = {
1005 NULL 1008 NULL
1006}; 1009};
1007 1010
1011static const char *hwcap2_str[] = {
1012 "aes",
1013 "pmull",
1014 "sha1",
1015 "sha2",
1016 "crc32",
1017 NULL
1018};
1019
1008static int c_show(struct seq_file *m, void *v) 1020static int c_show(struct seq_file *m, void *v)
1009{ 1021{
1010 int i, j; 1022 int i, j;
@@ -1028,6 +1040,10 @@ static int c_show(struct seq_file *m, void *v)
1028 if (elf_hwcap & (1 << j)) 1040 if (elf_hwcap & (1 << j))
1029 seq_printf(m, "%s ", hwcap_str[j]); 1041 seq_printf(m, "%s ", hwcap_str[j]);
1030 1042
1043 for (j = 0; hwcap2_str[j]; j++)
1044 if (elf_hwcap2 & (1 << j))
1045 seq_printf(m, "%s ", hwcap2_str[j]);
1046
1031 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24); 1047 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24);
1032 seq_printf(m, "CPU architecture: %s\n", 1048 seq_printf(m, "CPU architecture: %s\n",
1033 proc_arch[cpu_architecture()]); 1049 proc_arch[cpu_architecture()]);
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 172ee18ff124..abd2fc067736 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -445,6 +445,7 @@ die_sig:
445 if (user_debug & UDBG_UNDEFINED) { 445 if (user_debug & UDBG_UNDEFINED) {
446 printk(KERN_INFO "%s (%d): undefined instruction: pc=%p\n", 446 printk(KERN_INFO "%s (%d): undefined instruction: pc=%p\n",
447 current->comm, task_pid_nr(current), pc); 447 current->comm, task_pid_nr(current), pc);
448 __show_regs(regs);
448 dump_instr(KERN_INFO, regs); 449 dump_instr(KERN_INFO, regs);
449 } 450 }
450#endif 451#endif
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index 00df012c4678..3c217694ebec 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -68,6 +68,12 @@ EXPORT_SYMBOL(__aeabi_unwind_cpp_pr2);
68struct unwind_ctrl_block { 68struct unwind_ctrl_block {
69 unsigned long vrs[16]; /* virtual register set */ 69 unsigned long vrs[16]; /* virtual register set */
70 const unsigned long *insn; /* pointer to the current instructions word */ 70 const unsigned long *insn; /* pointer to the current instructions word */
71 unsigned long sp_high; /* highest value of sp allowed */
72 /*
73 * 1 : check for stack overflow for each register pop.
74 * 0 : save overhead if there is plenty of stack remaining.
75 */
76 int check_each_pop;
71 int entries; /* number of entries left to interpret */ 77 int entries; /* number of entries left to interpret */
72 int byte; /* current byte number in the instructions word */ 78 int byte; /* current byte number in the instructions word */
73}; 79};
@@ -235,12 +241,85 @@ static unsigned long unwind_get_byte(struct unwind_ctrl_block *ctrl)
235 return ret; 241 return ret;
236} 242}
237 243
244/* Before poping a register check whether it is feasible or not */
245static int unwind_pop_register(struct unwind_ctrl_block *ctrl,
246 unsigned long **vsp, unsigned int reg)
247{
248 if (unlikely(ctrl->check_each_pop))
249 if (*vsp >= (unsigned long *)ctrl->sp_high)
250 return -URC_FAILURE;
251
252 ctrl->vrs[reg] = *(*vsp)++;
253 return URC_OK;
254}
255
256/* Helper functions to execute the instructions */
257static int unwind_exec_pop_subset_r4_to_r13(struct unwind_ctrl_block *ctrl,
258 unsigned long mask)
259{
260 unsigned long *vsp = (unsigned long *)ctrl->vrs[SP];
261 int load_sp, reg = 4;
262
263 load_sp = mask & (1 << (13 - 4));
264 while (mask) {
265 if (mask & 1)
266 if (unwind_pop_register(ctrl, &vsp, reg))
267 return -URC_FAILURE;
268 mask >>= 1;
269 reg++;
270 }
271 if (!load_sp)
272 ctrl->vrs[SP] = (unsigned long)vsp;
273
274 return URC_OK;
275}
276
277static int unwind_exec_pop_r4_to_rN(struct unwind_ctrl_block *ctrl,
278 unsigned long insn)
279{
280 unsigned long *vsp = (unsigned long *)ctrl->vrs[SP];
281 int reg;
282
283 /* pop R4-R[4+bbb] */
284 for (reg = 4; reg <= 4 + (insn & 7); reg++)
285 if (unwind_pop_register(ctrl, &vsp, reg))
286 return -URC_FAILURE;
287
288 if (insn & 0x80)
289 if (unwind_pop_register(ctrl, &vsp, 14))
290 return -URC_FAILURE;
291
292 ctrl->vrs[SP] = (unsigned long)vsp;
293
294 return URC_OK;
295}
296
297static int unwind_exec_pop_subset_r0_to_r3(struct unwind_ctrl_block *ctrl,
298 unsigned long mask)
299{
300 unsigned long *vsp = (unsigned long *)ctrl->vrs[SP];
301 int reg = 0;
302
303 /* pop R0-R3 according to mask */
304 while (mask) {
305 if (mask & 1)
306 if (unwind_pop_register(ctrl, &vsp, reg))
307 return -URC_FAILURE;
308 mask >>= 1;
309 reg++;
310 }
311 ctrl->vrs[SP] = (unsigned long)vsp;
312
313 return URC_OK;
314}
315
238/* 316/*
239 * Execute the current unwind instruction. 317 * Execute the current unwind instruction.
240 */ 318 */
241static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) 319static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
242{ 320{
243 unsigned long insn = unwind_get_byte(ctrl); 321 unsigned long insn = unwind_get_byte(ctrl);
322 int ret = URC_OK;
244 323
245 pr_debug("%s: insn = %08lx\n", __func__, insn); 324 pr_debug("%s: insn = %08lx\n", __func__, insn);
246 325
@@ -250,8 +329,6 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
250 ctrl->vrs[SP] -= ((insn & 0x3f) << 2) + 4; 329 ctrl->vrs[SP] -= ((insn & 0x3f) << 2) + 4;
251 else if ((insn & 0xf0) == 0x80) { 330 else if ((insn & 0xf0) == 0x80) {
252 unsigned long mask; 331 unsigned long mask;
253 unsigned long *vsp = (unsigned long *)ctrl->vrs[SP];
254 int load_sp, reg = 4;
255 332
256 insn = (insn << 8) | unwind_get_byte(ctrl); 333 insn = (insn << 8) | unwind_get_byte(ctrl);
257 mask = insn & 0x0fff; 334 mask = insn & 0x0fff;
@@ -261,29 +338,16 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
261 return -URC_FAILURE; 338 return -URC_FAILURE;
262 } 339 }
263 340
264 /* pop R4-R15 according to mask */ 341 ret = unwind_exec_pop_subset_r4_to_r13(ctrl, mask);
265 load_sp = mask & (1 << (13 - 4)); 342 if (ret)
266 while (mask) { 343 goto error;
267 if (mask & 1)
268 ctrl->vrs[reg] = *vsp++;
269 mask >>= 1;
270 reg++;
271 }
272 if (!load_sp)
273 ctrl->vrs[SP] = (unsigned long)vsp;
274 } else if ((insn & 0xf0) == 0x90 && 344 } else if ((insn & 0xf0) == 0x90 &&
275 (insn & 0x0d) != 0x0d) 345 (insn & 0x0d) != 0x0d)
276 ctrl->vrs[SP] = ctrl->vrs[insn & 0x0f]; 346 ctrl->vrs[SP] = ctrl->vrs[insn & 0x0f];
277 else if ((insn & 0xf0) == 0xa0) { 347 else if ((insn & 0xf0) == 0xa0) {
278 unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; 348 ret = unwind_exec_pop_r4_to_rN(ctrl, insn);
279 int reg; 349 if (ret)
280 350 goto error;
281 /* pop R4-R[4+bbb] */
282 for (reg = 4; reg <= 4 + (insn & 7); reg++)
283 ctrl->vrs[reg] = *vsp++;
284 if (insn & 0x80)
285 ctrl->vrs[14] = *vsp++;
286 ctrl->vrs[SP] = (unsigned long)vsp;
287 } else if (insn == 0xb0) { 351 } else if (insn == 0xb0) {
288 if (ctrl->vrs[PC] == 0) 352 if (ctrl->vrs[PC] == 0)
289 ctrl->vrs[PC] = ctrl->vrs[LR]; 353 ctrl->vrs[PC] = ctrl->vrs[LR];
@@ -291,8 +355,6 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
291 ctrl->entries = 0; 355 ctrl->entries = 0;
292 } else if (insn == 0xb1) { 356 } else if (insn == 0xb1) {
293 unsigned long mask = unwind_get_byte(ctrl); 357 unsigned long mask = unwind_get_byte(ctrl);
294 unsigned long *vsp = (unsigned long *)ctrl->vrs[SP];
295 int reg = 0;
296 358
297 if (mask == 0 || mask & 0xf0) { 359 if (mask == 0 || mask & 0xf0) {
298 pr_warning("unwind: Spare encoding %04lx\n", 360 pr_warning("unwind: Spare encoding %04lx\n",
@@ -300,14 +362,9 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
300 return -URC_FAILURE; 362 return -URC_FAILURE;
301 } 363 }
302 364
303 /* pop R0-R3 according to mask */ 365 ret = unwind_exec_pop_subset_r0_to_r3(ctrl, mask);
304 while (mask) { 366 if (ret)
305 if (mask & 1) 367 goto error;
306 ctrl->vrs[reg] = *vsp++;
307 mask >>= 1;
308 reg++;
309 }
310 ctrl->vrs[SP] = (unsigned long)vsp;
311 } else if (insn == 0xb2) { 368 } else if (insn == 0xb2) {
312 unsigned long uleb128 = unwind_get_byte(ctrl); 369 unsigned long uleb128 = unwind_get_byte(ctrl);
313 370
@@ -320,7 +377,8 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
320 pr_debug("%s: fp = %08lx sp = %08lx lr = %08lx pc = %08lx\n", __func__, 377 pr_debug("%s: fp = %08lx sp = %08lx lr = %08lx pc = %08lx\n", __func__,
321 ctrl->vrs[FP], ctrl->vrs[SP], ctrl->vrs[LR], ctrl->vrs[PC]); 378 ctrl->vrs[FP], ctrl->vrs[SP], ctrl->vrs[LR], ctrl->vrs[PC]);
322 379
323 return URC_OK; 380error:
381 return ret;
324} 382}
325 383
326/* 384/*
@@ -329,13 +387,13 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
329 */ 387 */
330int unwind_frame(struct stackframe *frame) 388int unwind_frame(struct stackframe *frame)
331{ 389{
332 unsigned long high, low; 390 unsigned long low;
333 const struct unwind_idx *idx; 391 const struct unwind_idx *idx;
334 struct unwind_ctrl_block ctrl; 392 struct unwind_ctrl_block ctrl;
335 393
336 /* only go to a higher address on the stack */ 394 /* store the highest address on the stack to avoid crossing it*/
337 low = frame->sp; 395 low = frame->sp;
338 high = ALIGN(low, THREAD_SIZE); 396 ctrl.sp_high = ALIGN(low, THREAD_SIZE);
339 397
340 pr_debug("%s(pc = %08lx lr = %08lx sp = %08lx)\n", __func__, 398 pr_debug("%s(pc = %08lx lr = %08lx sp = %08lx)\n", __func__,
341 frame->pc, frame->lr, frame->sp); 399 frame->pc, frame->lr, frame->sp);
@@ -382,11 +440,16 @@ int unwind_frame(struct stackframe *frame)
382 return -URC_FAILURE; 440 return -URC_FAILURE;
383 } 441 }
384 442
443 ctrl.check_each_pop = 0;
444
385 while (ctrl.entries > 0) { 445 while (ctrl.entries > 0) {
386 int urc = unwind_exec_insn(&ctrl); 446 int urc;
447 if ((ctrl.sp_high - ctrl.vrs[SP]) < sizeof(ctrl.vrs))
448 ctrl.check_each_pop = 1;
449 urc = unwind_exec_insn(&ctrl);
387 if (urc < 0) 450 if (urc < 0)
388 return urc; 451 return urc;
389 if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high) 452 if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= ctrl.sp_high)
390 return -URC_FAILURE; 453 return -URC_FAILURE;
391 } 454 }
392 455
diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h
index 52886b89706c..9f12ed1eea86 100644
--- a/arch/arm/lib/bitops.h
+++ b/arch/arm/lib/bitops.h
@@ -37,6 +37,11 @@ UNWIND( .fnstart )
37 add r1, r1, r0, lsl #2 @ Get word offset 37 add r1, r1, r0, lsl #2 @ Get word offset
38 mov r3, r2, lsl r3 @ create mask 38 mov r3, r2, lsl r3 @ create mask
39 smp_dmb 39 smp_dmb
40#if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
41 .arch_extension mp
42 ALT_SMP(W(pldw) [r1])
43 ALT_UP(W(nop))
44#endif
401: ldrex r2, [r1] 451: ldrex r2, [r1]
41 ands r0, r2, r3 @ save old value of bit 46 ands r0, r2, r3 @ save old value of bit
42 \instr r2, r2, r3 @ toggle bit 47 \instr r2, r2, r3 @ toggle bit
diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index 805e3f8fb007..3bc8eb811a73 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -197,24 +197,24 @@
197 197
19812: PLD( pld [r1, #124] ) 19812: PLD( pld [r1, #124] )
19913: ldr4w r1, r4, r5, r6, r7, abort=19f 19913: ldr4w r1, r4, r5, r6, r7, abort=19f
200 mov r3, lr, pull #\pull 200 mov r3, lr, lspull #\pull
201 subs r2, r2, #32 201 subs r2, r2, #32
202 ldr4w r1, r8, r9, ip, lr, abort=19f 202 ldr4w r1, r8, r9, ip, lr, abort=19f
203 orr r3, r3, r4, push #\push 203 orr r3, r3, r4, lspush #\push
204 mov r4, r4, pull #\pull 204 mov r4, r4, lspull #\pull
205 orr r4, r4, r5, push #\push 205 orr r4, r4, r5, lspush #\push
206 mov r5, r5, pull #\pull 206 mov r5, r5, lspull #\pull
207 orr r5, r5, r6, push #\push 207 orr r5, r5, r6, lspush #\push
208 mov r6, r6, pull #\pull 208 mov r6, r6, lspull #\pull
209 orr r6, r6, r7, push #\push 209 orr r6, r6, r7, lspush #\push
210 mov r7, r7, pull #\pull 210 mov r7, r7, lspull #\pull
211 orr r7, r7, r8, push #\push 211 orr r7, r7, r8, lspush #\push
212 mov r8, r8, pull #\pull 212 mov r8, r8, lspull #\pull
213 orr r8, r8, r9, push #\push 213 orr r8, r8, r9, lspush #\push
214 mov r9, r9, pull #\pull 214 mov r9, r9, lspull #\pull
215 orr r9, r9, ip, push #\push 215 orr r9, r9, ip, lspush #\push
216 mov ip, ip, pull #\pull 216 mov ip, ip, lspull #\pull
217 orr ip, ip, lr, push #\push 217 orr ip, ip, lr, lspush #\push
218 str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f 218 str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
219 bge 12b 219 bge 12b
220 PLD( cmn r2, #96 ) 220 PLD( cmn r2, #96 )
@@ -225,10 +225,10 @@
22514: ands ip, r2, #28 22514: ands ip, r2, #28
226 beq 16f 226 beq 16f
227 227
22815: mov r3, lr, pull #\pull 22815: mov r3, lr, lspull #\pull
229 ldr1w r1, lr, abort=21f 229 ldr1w r1, lr, abort=21f
230 subs ip, ip, #4 230 subs ip, ip, #4
231 orr r3, r3, lr, push #\push 231 orr r3, r3, lr, lspush #\push
232 str1w r0, r3, abort=21f 232 str1w r0, r3, abort=21f
233 bgt 15b 233 bgt 15b
234 CALGN( cmp r2, #0 ) 234 CALGN( cmp r2, #0 )
diff --git a/arch/arm/lib/csumpartialcopygeneric.S b/arch/arm/lib/csumpartialcopygeneric.S
index d620a5f22a09..d6e742d24007 100644
--- a/arch/arm/lib/csumpartialcopygeneric.S
+++ b/arch/arm/lib/csumpartialcopygeneric.S
@@ -141,7 +141,7 @@ FN_ENTRY
141 tst len, #2 141 tst len, #2
142 mov r5, r4, get_byte_0 142 mov r5, r4, get_byte_0
143 beq .Lexit 143 beq .Lexit
144 adcs sum, sum, r4, push #16 144 adcs sum, sum, r4, lspush #16
145 strb r5, [dst], #1 145 strb r5, [dst], #1
146 mov r5, r4, get_byte_1 146 mov r5, r4, get_byte_1
147 strb r5, [dst], #1 147 strb r5, [dst], #1
@@ -171,23 +171,23 @@ FN_ENTRY
171 cmp ip, #2 171 cmp ip, #2
172 beq .Lsrc2_aligned 172 beq .Lsrc2_aligned
173 bhi .Lsrc3_aligned 173 bhi .Lsrc3_aligned
174 mov r4, r5, pull #8 @ C = 0 174 mov r4, r5, lspull #8 @ C = 0
175 bics ip, len, #15 175 bics ip, len, #15
176 beq 2f 176 beq 2f
1771: load4l r5, r6, r7, r8 1771: load4l r5, r6, r7, r8
178 orr r4, r4, r5, push #24 178 orr r4, r4, r5, lspush #24
179 mov r5, r5, pull #8 179 mov r5, r5, lspull #8
180 orr r5, r5, r6, push #24 180 orr r5, r5, r6, lspush #24
181 mov r6, r6, pull #8 181 mov r6, r6, lspull #8
182 orr r6, r6, r7, push #24 182 orr r6, r6, r7, lspush #24
183 mov r7, r7, pull #8 183 mov r7, r7, lspull #8
184 orr r7, r7, r8, push #24 184 orr r7, r7, r8, lspush #24
185 stmia dst!, {r4, r5, r6, r7} 185 stmia dst!, {r4, r5, r6, r7}
186 adcs sum, sum, r4 186 adcs sum, sum, r4
187 adcs sum, sum, r5 187 adcs sum, sum, r5
188 adcs sum, sum, r6 188 adcs sum, sum, r6
189 adcs sum, sum, r7 189 adcs sum, sum, r7
190 mov r4, r8, pull #8 190 mov r4, r8, lspull #8
191 sub ip, ip, #16 191 sub ip, ip, #16
192 teq ip, #0 192 teq ip, #0
193 bne 1b 193 bne 1b
@@ -196,50 +196,50 @@ FN_ENTRY
196 tst ip, #8 196 tst ip, #8
197 beq 3f 197 beq 3f
198 load2l r5, r6 198 load2l r5, r6
199 orr r4, r4, r5, push #24 199 orr r4, r4, r5, lspush #24
200 mov r5, r5, pull #8 200 mov r5, r5, lspull #8
201 orr r5, r5, r6, push #24 201 orr r5, r5, r6, lspush #24
202 stmia dst!, {r4, r5} 202 stmia dst!, {r4, r5}
203 adcs sum, sum, r4 203 adcs sum, sum, r4
204 adcs sum, sum, r5 204 adcs sum, sum, r5
205 mov r4, r6, pull #8 205 mov r4, r6, lspull #8
206 tst ip, #4 206 tst ip, #4
207 beq 4f 207 beq 4f
2083: load1l r5 2083: load1l r5
209 orr r4, r4, r5, push #24 209 orr r4, r4, r5, lspush #24
210 str r4, [dst], #4 210 str r4, [dst], #4
211 adcs sum, sum, r4 211 adcs sum, sum, r4
212 mov r4, r5, pull #8 212 mov r4, r5, lspull #8
2134: ands len, len, #3 2134: ands len, len, #3
214 beq .Ldone 214 beq .Ldone
215 mov r5, r4, get_byte_0 215 mov r5, r4, get_byte_0
216 tst len, #2 216 tst len, #2
217 beq .Lexit 217 beq .Lexit
218 adcs sum, sum, r4, push #16 218 adcs sum, sum, r4, lspush #16
219 strb r5, [dst], #1 219 strb r5, [dst], #1
220 mov r5, r4, get_byte_1 220 mov r5, r4, get_byte_1
221 strb r5, [dst], #1 221 strb r5, [dst], #1
222 mov r5, r4, get_byte_2 222 mov r5, r4, get_byte_2
223 b .Lexit 223 b .Lexit
224 224
225.Lsrc2_aligned: mov r4, r5, pull #16 225.Lsrc2_aligned: mov r4, r5, lspull #16
226 adds sum, sum, #0 226 adds sum, sum, #0
227 bics ip, len, #15 227 bics ip, len, #15
228 beq 2f 228 beq 2f
2291: load4l r5, r6, r7, r8 2291: load4l r5, r6, r7, r8
230 orr r4, r4, r5, push #16 230 orr r4, r4, r5, lspush #16
231 mov r5, r5, pull #16 231 mov r5, r5, lspull #16
232 orr r5, r5, r6, push #16 232 orr r5, r5, r6, lspush #16
233 mov r6, r6, pull #16 233 mov r6, r6, lspull #16
234 orr r6, r6, r7, push #16 234 orr r6, r6, r7, lspush #16
235 mov r7, r7, pull #16 235 mov r7, r7, lspull #16
236 orr r7, r7, r8, push #16 236 orr r7, r7, r8, lspush #16
237 stmia dst!, {r4, r5, r6, r7} 237 stmia dst!, {r4, r5, r6, r7}
238 adcs sum, sum, r4 238 adcs sum, sum, r4
239 adcs sum, sum, r5 239 adcs sum, sum, r5
240 adcs sum, sum, r6 240 adcs sum, sum, r6
241 adcs sum, sum, r7 241 adcs sum, sum, r7
242 mov r4, r8, pull #16 242 mov r4, r8, lspull #16
243 sub ip, ip, #16 243 sub ip, ip, #16
244 teq ip, #0 244 teq ip, #0
245 bne 1b 245 bne 1b
@@ -248,20 +248,20 @@ FN_ENTRY
248 tst ip, #8 248 tst ip, #8
249 beq 3f 249 beq 3f
250 load2l r5, r6 250 load2l r5, r6
251 orr r4, r4, r5, push #16 251 orr r4, r4, r5, lspush #16
252 mov r5, r5, pull #16 252 mov r5, r5, lspull #16
253 orr r5, r5, r6, push #16 253 orr r5, r5, r6, lspush #16
254 stmia dst!, {r4, r5} 254 stmia dst!, {r4, r5}
255 adcs sum, sum, r4 255 adcs sum, sum, r4
256 adcs sum, sum, r5 256 adcs sum, sum, r5
257 mov r4, r6, pull #16 257 mov r4, r6, lspull #16
258 tst ip, #4 258 tst ip, #4
259 beq 4f 259 beq 4f
2603: load1l r5 2603: load1l r5
261 orr r4, r4, r5, push #16 261 orr r4, r4, r5, lspush #16
262 str r4, [dst], #4 262 str r4, [dst], #4
263 adcs sum, sum, r4 263 adcs sum, sum, r4
264 mov r4, r5, pull #16 264 mov r4, r5, lspull #16
2654: ands len, len, #3 2654: ands len, len, #3
266 beq .Ldone 266 beq .Ldone
267 mov r5, r4, get_byte_0 267 mov r5, r4, get_byte_0
@@ -276,24 +276,24 @@ FN_ENTRY
276 load1b r5 276 load1b r5
277 b .Lexit 277 b .Lexit
278 278
279.Lsrc3_aligned: mov r4, r5, pull #24 279.Lsrc3_aligned: mov r4, r5, lspull #24
280 adds sum, sum, #0 280 adds sum, sum, #0
281 bics ip, len, #15 281 bics ip, len, #15
282 beq 2f 282 beq 2f
2831: load4l r5, r6, r7, r8 2831: load4l r5, r6, r7, r8
284 orr r4, r4, r5, push #8 284 orr r4, r4, r5, lspush #8
285 mov r5, r5, pull #24 285 mov r5, r5, lspull #24
286 orr r5, r5, r6, push #8 286 orr r5, r5, r6, lspush #8
287 mov r6, r6, pull #24 287 mov r6, r6, lspull #24
288 orr r6, r6, r7, push #8 288 orr r6, r6, r7, lspush #8
289 mov r7, r7, pull #24 289 mov r7, r7, lspull #24
290 orr r7, r7, r8, push #8 290 orr r7, r7, r8, lspush #8
291 stmia dst!, {r4, r5, r6, r7} 291 stmia dst!, {r4, r5, r6, r7}
292 adcs sum, sum, r4 292 adcs sum, sum, r4
293 adcs sum, sum, r5 293 adcs sum, sum, r5
294 adcs sum, sum, r6 294 adcs sum, sum, r6
295 adcs sum, sum, r7 295 adcs sum, sum, r7
296 mov r4, r8, pull #24 296 mov r4, r8, lspull #24
297 sub ip, ip, #16 297 sub ip, ip, #16
298 teq ip, #0 298 teq ip, #0
299 bne 1b 299 bne 1b
@@ -302,20 +302,20 @@ FN_ENTRY
302 tst ip, #8 302 tst ip, #8
303 beq 3f 303 beq 3f
304 load2l r5, r6 304 load2l r5, r6
305 orr r4, r4, r5, push #8 305 orr r4, r4, r5, lspush #8
306 mov r5, r5, pull #24 306 mov r5, r5, lspull #24
307 orr r5, r5, r6, push #8 307 orr r5, r5, r6, lspush #8
308 stmia dst!, {r4, r5} 308 stmia dst!, {r4, r5}
309 adcs sum, sum, r4 309 adcs sum, sum, r4
310 adcs sum, sum, r5 310 adcs sum, sum, r5
311 mov r4, r6, pull #24 311 mov r4, r6, lspull #24
312 tst ip, #4 312 tst ip, #4
313 beq 4f 313 beq 4f
3143: load1l r5 3143: load1l r5
315 orr r4, r4, r5, push #8 315 orr r4, r4, r5, lspush #8
316 str r4, [dst], #4 316 str r4, [dst], #4
317 adcs sum, sum, r4 317 adcs sum, sum, r4
318 mov r4, r5, pull #24 318 mov r4, r5, lspull #24
3194: ands len, len, #3 3194: ands len, len, #3
320 beq .Ldone 320 beq .Ldone
321 mov r5, r4, get_byte_0 321 mov r5, r4, get_byte_0
@@ -326,7 +326,7 @@ FN_ENTRY
326 load1l r4 326 load1l r4
327 mov r5, r4, get_byte_0 327 mov r5, r4, get_byte_0
328 strb r5, [dst], #1 328 strb r5, [dst], #1
329 adcs sum, sum, r4, push #24 329 adcs sum, sum, r4, lspush #24
330 mov r5, r4, get_byte_1 330 mov r5, r4, get_byte_1
331 b .Lexit 331 b .Lexit
332FN_EXIT 332FN_EXIT
diff --git a/arch/arm/lib/io-readsl.S b/arch/arm/lib/io-readsl.S
index 5fb97e7f9f4b..7a7430950c79 100644
--- a/arch/arm/lib/io-readsl.S
+++ b/arch/arm/lib/io-readsl.S
@@ -47,25 +47,25 @@ ENTRY(__raw_readsl)
47 strb ip, [r1], #1 47 strb ip, [r1], #1
48 48
494: subs r2, r2, #1 494: subs r2, r2, #1
50 mov ip, r3, pull #24 50 mov ip, r3, lspull #24
51 ldrne r3, [r0] 51 ldrne r3, [r0]
52 orrne ip, ip, r3, push #8 52 orrne ip, ip, r3, lspush #8
53 strne ip, [r1], #4 53 strne ip, [r1], #4
54 bne 4b 54 bne 4b
55 b 8f 55 b 8f
56 56
575: subs r2, r2, #1 575: subs r2, r2, #1
58 mov ip, r3, pull #16 58 mov ip, r3, lspull #16
59 ldrne r3, [r0] 59 ldrne r3, [r0]
60 orrne ip, ip, r3, push #16 60 orrne ip, ip, r3, lspush #16
61 strne ip, [r1], #4 61 strne ip, [r1], #4
62 bne 5b 62 bne 5b
63 b 7f 63 b 7f
64 64
656: subs r2, r2, #1 656: subs r2, r2, #1
66 mov ip, r3, pull #8 66 mov ip, r3, lspull #8
67 ldrne r3, [r0] 67 ldrne r3, [r0]
68 orrne ip, ip, r3, push #24 68 orrne ip, ip, r3, lspush #24
69 strne ip, [r1], #4 69 strne ip, [r1], #4
70 bne 6b 70 bne 6b
71 71
diff --git a/arch/arm/lib/io-writesl.S b/arch/arm/lib/io-writesl.S
index 8d3b7813725c..d0d104a0dd11 100644
--- a/arch/arm/lib/io-writesl.S
+++ b/arch/arm/lib/io-writesl.S
@@ -41,26 +41,26 @@ ENTRY(__raw_writesl)
41 blt 5f 41 blt 5f
42 bgt 6f 42 bgt 6f
43 43
444: mov ip, r3, pull #16 444: mov ip, r3, lspull #16
45 ldr r3, [r1], #4 45 ldr r3, [r1], #4
46 subs r2, r2, #1 46 subs r2, r2, #1
47 orr ip, ip, r3, push #16 47 orr ip, ip, r3, lspush #16
48 str ip, [r0] 48 str ip, [r0]
49 bne 4b 49 bne 4b
50 mov pc, lr 50 mov pc, lr
51 51
525: mov ip, r3, pull #8 525: mov ip, r3, lspull #8
53 ldr r3, [r1], #4 53 ldr r3, [r1], #4
54 subs r2, r2, #1 54 subs r2, r2, #1
55 orr ip, ip, r3, push #24 55 orr ip, ip, r3, lspush #24
56 str ip, [r0] 56 str ip, [r0]
57 bne 5b 57 bne 5b
58 mov pc, lr 58 mov pc, lr
59 59
606: mov ip, r3, pull #24 606: mov ip, r3, lspull #24
61 ldr r3, [r1], #4 61 ldr r3, [r1], #4
62 subs r2, r2, #1 62 subs r2, r2, #1
63 orr ip, ip, r3, push #8 63 orr ip, ip, r3, lspush #8
64 str ip, [r0] 64 str ip, [r0]
65 bne 6b 65 bne 6b
66 mov pc, lr 66 mov pc, lr
diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S
index 938fc14f962d..d1fc0c0c342c 100644
--- a/arch/arm/lib/memmove.S
+++ b/arch/arm/lib/memmove.S
@@ -147,24 +147,24 @@ ENTRY(memmove)
147 147
14812: PLD( pld [r1, #-128] ) 14812: PLD( pld [r1, #-128] )
14913: ldmdb r1!, {r7, r8, r9, ip} 14913: ldmdb r1!, {r7, r8, r9, ip}
150 mov lr, r3, push #\push 150 mov lr, r3, lspush #\push
151 subs r2, r2, #32 151 subs r2, r2, #32
152 ldmdb r1!, {r3, r4, r5, r6} 152 ldmdb r1!, {r3, r4, r5, r6}
153 orr lr, lr, ip, pull #\pull 153 orr lr, lr, ip, lspull #\pull
154 mov ip, ip, push #\push 154 mov ip, ip, lspush #\push
155 orr ip, ip, r9, pull #\pull 155 orr ip, ip, r9, lspull #\pull
156 mov r9, r9, push #\push 156 mov r9, r9, lspush #\push
157 orr r9, r9, r8, pull #\pull 157 orr r9, r9, r8, lspull #\pull
158 mov r8, r8, push #\push 158 mov r8, r8, lspush #\push
159 orr r8, r8, r7, pull #\pull 159 orr r8, r8, r7, lspull #\pull
160 mov r7, r7, push #\push 160 mov r7, r7, lspush #\push
161 orr r7, r7, r6, pull #\pull 161 orr r7, r7, r6, lspull #\pull
162 mov r6, r6, push #\push 162 mov r6, r6, lspush #\push
163 orr r6, r6, r5, pull #\pull 163 orr r6, r6, r5, lspull #\pull
164 mov r5, r5, push #\push 164 mov r5, r5, lspush #\push
165 orr r5, r5, r4, pull #\pull 165 orr r5, r5, r4, lspull #\pull
166 mov r4, r4, push #\push 166 mov r4, r4, lspush #\push
167 orr r4, r4, r3, pull #\pull 167 orr r4, r4, r3, lspull #\pull
168 stmdb r0!, {r4 - r9, ip, lr} 168 stmdb r0!, {r4 - r9, ip, lr}
169 bge 12b 169 bge 12b
170 PLD( cmn r2, #96 ) 170 PLD( cmn r2, #96 )
@@ -175,10 +175,10 @@ ENTRY(memmove)
17514: ands ip, r2, #28 17514: ands ip, r2, #28
176 beq 16f 176 beq 16f
177 177
17815: mov lr, r3, push #\push 17815: mov lr, r3, lspush #\push
179 ldr r3, [r1, #-4]! 179 ldr r3, [r1, #-4]!
180 subs ip, ip, #4 180 subs ip, ip, #4
181 orr lr, lr, r3, pull #\pull 181 orr lr, lr, r3, lspull #\pull
182 str lr, [r0, #-4]! 182 str lr, [r0, #-4]!
183 bgt 15b 183 bgt 15b
184 CALGN( cmp r2, #0 ) 184 CALGN( cmp r2, #0 )
diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S
index 5c908b1cb8ed..e50520904b76 100644
--- a/arch/arm/lib/uaccess.S
+++ b/arch/arm/lib/uaccess.S
@@ -117,9 +117,9 @@ USER( TUSER( strgtb) r3, [r0], #1) @ May fault
117.Lc2u_1fupi: subs r2, r2, #4 117.Lc2u_1fupi: subs r2, r2, #4
118 addmi ip, r2, #4 118 addmi ip, r2, #4
119 bmi .Lc2u_1nowords 119 bmi .Lc2u_1nowords
120 mov r3, r7, pull #8 120 mov r3, r7, lspull #8
121 ldr r7, [r1], #4 121 ldr r7, [r1], #4
122 orr r3, r3, r7, push #24 122 orr r3, r3, r7, lspush #24
123USER( TUSER( str) r3, [r0], #4) @ May fault 123USER( TUSER( str) r3, [r0], #4) @ May fault
124 mov ip, r0, lsl #32 - PAGE_SHIFT 124 mov ip, r0, lsl #32 - PAGE_SHIFT
125 rsb ip, ip, #0 125 rsb ip, ip, #0
@@ -131,30 +131,30 @@ USER( TUSER( str) r3, [r0], #4) @ May fault
131 subs ip, ip, #16 131 subs ip, ip, #16
132 blt .Lc2u_1rem8lp 132 blt .Lc2u_1rem8lp
133 133
134.Lc2u_1cpy8lp: mov r3, r7, pull #8 134.Lc2u_1cpy8lp: mov r3, r7, lspull #8
135 ldmia r1!, {r4 - r7} 135 ldmia r1!, {r4 - r7}
136 subs ip, ip, #16 136 subs ip, ip, #16
137 orr r3, r3, r4, push #24 137 orr r3, r3, r4, lspush #24
138 mov r4, r4, pull #8 138 mov r4, r4, lspull #8
139 orr r4, r4, r5, push #24 139 orr r4, r4, r5, lspush #24
140 mov r5, r5, pull #8 140 mov r5, r5, lspull #8
141 orr r5, r5, r6, push #24 141 orr r5, r5, r6, lspush #24
142 mov r6, r6, pull #8 142 mov r6, r6, lspull #8
143 orr r6, r6, r7, push #24 143 orr r6, r6, r7, lspush #24
144 stmia r0!, {r3 - r6} @ Shouldnt fault 144 stmia r0!, {r3 - r6} @ Shouldnt fault
145 bpl .Lc2u_1cpy8lp 145 bpl .Lc2u_1cpy8lp
146 146
147.Lc2u_1rem8lp: tst ip, #8 147.Lc2u_1rem8lp: tst ip, #8
148 movne r3, r7, pull #8 148 movne r3, r7, lspull #8
149 ldmneia r1!, {r4, r7} 149 ldmneia r1!, {r4, r7}
150 orrne r3, r3, r4, push #24 150 orrne r3, r3, r4, lspush #24
151 movne r4, r4, pull #8 151 movne r4, r4, lspull #8
152 orrne r4, r4, r7, push #24 152 orrne r4, r4, r7, lspush #24
153 stmneia r0!, {r3 - r4} @ Shouldnt fault 153 stmneia r0!, {r3 - r4} @ Shouldnt fault
154 tst ip, #4 154 tst ip, #4
155 movne r3, r7, pull #8 155 movne r3, r7, lspull #8
156 ldrne r7, [r1], #4 156 ldrne r7, [r1], #4
157 orrne r3, r3, r7, push #24 157 orrne r3, r3, r7, lspush #24
158 TUSER( strne) r3, [r0], #4 @ Shouldnt fault 158 TUSER( strne) r3, [r0], #4 @ Shouldnt fault
159 ands ip, ip, #3 159 ands ip, ip, #3
160 beq .Lc2u_1fupi 160 beq .Lc2u_1fupi
@@ -172,9 +172,9 @@ USER( TUSER( strgtb) r3, [r0], #1) @ May fault
172.Lc2u_2fupi: subs r2, r2, #4 172.Lc2u_2fupi: subs r2, r2, #4
173 addmi ip, r2, #4 173 addmi ip, r2, #4
174 bmi .Lc2u_2nowords 174 bmi .Lc2u_2nowords
175 mov r3, r7, pull #16 175 mov r3, r7, lspull #16
176 ldr r7, [r1], #4 176 ldr r7, [r1], #4
177 orr r3, r3, r7, push #16 177 orr r3, r3, r7, lspush #16
178USER( TUSER( str) r3, [r0], #4) @ May fault 178USER( TUSER( str) r3, [r0], #4) @ May fault
179 mov ip, r0, lsl #32 - PAGE_SHIFT 179 mov ip, r0, lsl #32 - PAGE_SHIFT
180 rsb ip, ip, #0 180 rsb ip, ip, #0
@@ -186,30 +186,30 @@ USER( TUSER( str) r3, [r0], #4) @ May fault
186 subs ip, ip, #16 186 subs ip, ip, #16
187 blt .Lc2u_2rem8lp 187 blt .Lc2u_2rem8lp
188 188
189.Lc2u_2cpy8lp: mov r3, r7, pull #16 189.Lc2u_2cpy8lp: mov r3, r7, lspull #16
190 ldmia r1!, {r4 - r7} 190 ldmia r1!, {r4 - r7}
191 subs ip, ip, #16 191 subs ip, ip, #16
192 orr r3, r3, r4, push #16 192 orr r3, r3, r4, lspush #16
193 mov r4, r4, pull #16 193 mov r4, r4, lspull #16
194 orr r4, r4, r5, push #16 194 orr r4, r4, r5, lspush #16
195 mov r5, r5, pull #16 195 mov r5, r5, lspull #16
196 orr r5, r5, r6, push #16 196 orr r5, r5, r6, lspush #16
197 mov r6, r6, pull #16 197 mov r6, r6, lspull #16
198 orr r6, r6, r7, push #16 198 orr r6, r6, r7, lspush #16
199 stmia r0!, {r3 - r6} @ Shouldnt fault 199 stmia r0!, {r3 - r6} @ Shouldnt fault
200 bpl .Lc2u_2cpy8lp 200 bpl .Lc2u_2cpy8lp
201 201
202.Lc2u_2rem8lp: tst ip, #8 202.Lc2u_2rem8lp: tst ip, #8
203 movne r3, r7, pull #16 203 movne r3, r7, lspull #16
204 ldmneia r1!, {r4, r7} 204 ldmneia r1!, {r4, r7}
205 orrne r3, r3, r4, push #16 205 orrne r3, r3, r4, lspush #16
206 movne r4, r4, pull #16 206 movne r4, r4, lspull #16
207 orrne r4, r4, r7, push #16 207 orrne r4, r4, r7, lspush #16
208 stmneia r0!, {r3 - r4} @ Shouldnt fault 208 stmneia r0!, {r3 - r4} @ Shouldnt fault
209 tst ip, #4 209 tst ip, #4
210 movne r3, r7, pull #16 210 movne r3, r7, lspull #16
211 ldrne r7, [r1], #4 211 ldrne r7, [r1], #4
212 orrne r3, r3, r7, push #16 212 orrne r3, r3, r7, lspush #16
213 TUSER( strne) r3, [r0], #4 @ Shouldnt fault 213 TUSER( strne) r3, [r0], #4 @ Shouldnt fault
214 ands ip, ip, #3 214 ands ip, ip, #3
215 beq .Lc2u_2fupi 215 beq .Lc2u_2fupi
@@ -227,9 +227,9 @@ USER( TUSER( strgtb) r3, [r0], #1) @ May fault
227.Lc2u_3fupi: subs r2, r2, #4 227.Lc2u_3fupi: subs r2, r2, #4
228 addmi ip, r2, #4 228 addmi ip, r2, #4
229 bmi .Lc2u_3nowords 229 bmi .Lc2u_3nowords
230 mov r3, r7, pull #24 230 mov r3, r7, lspull #24
231 ldr r7, [r1], #4 231 ldr r7, [r1], #4
232 orr r3, r3, r7, push #8 232 orr r3, r3, r7, lspush #8
233USER( TUSER( str) r3, [r0], #4) @ May fault 233USER( TUSER( str) r3, [r0], #4) @ May fault
234 mov ip, r0, lsl #32 - PAGE_SHIFT 234 mov ip, r0, lsl #32 - PAGE_SHIFT
235 rsb ip, ip, #0 235 rsb ip, ip, #0
@@ -241,30 +241,30 @@ USER( TUSER( str) r3, [r0], #4) @ May fault
241 subs ip, ip, #16 241 subs ip, ip, #16
242 blt .Lc2u_3rem8lp 242 blt .Lc2u_3rem8lp
243 243
244.Lc2u_3cpy8lp: mov r3, r7, pull #24 244.Lc2u_3cpy8lp: mov r3, r7, lspull #24
245 ldmia r1!, {r4 - r7} 245 ldmia r1!, {r4 - r7}
246 subs ip, ip, #16 246 subs ip, ip, #16
247 orr r3, r3, r4, push #8 247 orr r3, r3, r4, lspush #8
248 mov r4, r4, pull #24 248 mov r4, r4, lspull #24
249 orr r4, r4, r5, push #8 249 orr r4, r4, r5, lspush #8
250 mov r5, r5, pull #24 250 mov r5, r5, lspull #24
251 orr r5, r5, r6, push #8 251 orr r5, r5, r6, lspush #8
252 mov r6, r6, pull #24 252 mov r6, r6, lspull #24
253 orr r6, r6, r7, push #8 253 orr r6, r6, r7, lspush #8
254 stmia r0!, {r3 - r6} @ Shouldnt fault 254 stmia r0!, {r3 - r6} @ Shouldnt fault
255 bpl .Lc2u_3cpy8lp 255 bpl .Lc2u_3cpy8lp
256 256
257.Lc2u_3rem8lp: tst ip, #8 257.Lc2u_3rem8lp: tst ip, #8
258 movne r3, r7, pull #24 258 movne r3, r7, lspull #24
259 ldmneia r1!, {r4, r7} 259 ldmneia r1!, {r4, r7}
260 orrne r3, r3, r4, push #8 260 orrne r3, r3, r4, lspush #8
261 movne r4, r4, pull #24 261 movne r4, r4, lspull #24
262 orrne r4, r4, r7, push #8 262 orrne r4, r4, r7, lspush #8
263 stmneia r0!, {r3 - r4} @ Shouldnt fault 263 stmneia r0!, {r3 - r4} @ Shouldnt fault
264 tst ip, #4 264 tst ip, #4
265 movne r3, r7, pull #24 265 movne r3, r7, lspull #24
266 ldrne r7, [r1], #4 266 ldrne r7, [r1], #4
267 orrne r3, r3, r7, push #8 267 orrne r3, r3, r7, lspush #8
268 TUSER( strne) r3, [r0], #4 @ Shouldnt fault 268 TUSER( strne) r3, [r0], #4 @ Shouldnt fault
269 ands ip, ip, #3 269 ands ip, ip, #3
270 beq .Lc2u_3fupi 270 beq .Lc2u_3fupi
@@ -382,9 +382,9 @@ USER( TUSER( ldr) r7, [r1], #4) @ May fault
382.Lcfu_1fupi: subs r2, r2, #4 382.Lcfu_1fupi: subs r2, r2, #4
383 addmi ip, r2, #4 383 addmi ip, r2, #4
384 bmi .Lcfu_1nowords 384 bmi .Lcfu_1nowords
385 mov r3, r7, pull #8 385 mov r3, r7, lspull #8
386USER( TUSER( ldr) r7, [r1], #4) @ May fault 386USER( TUSER( ldr) r7, [r1], #4) @ May fault
387 orr r3, r3, r7, push #24 387 orr r3, r3, r7, lspush #24
388 str r3, [r0], #4 388 str r3, [r0], #4
389 mov ip, r1, lsl #32 - PAGE_SHIFT 389 mov ip, r1, lsl #32 - PAGE_SHIFT
390 rsb ip, ip, #0 390 rsb ip, ip, #0
@@ -396,30 +396,30 @@ USER( TUSER( ldr) r7, [r1], #4) @ May fault
396 subs ip, ip, #16 396 subs ip, ip, #16
397 blt .Lcfu_1rem8lp 397 blt .Lcfu_1rem8lp
398 398
399.Lcfu_1cpy8lp: mov r3, r7, pull #8 399.Lcfu_1cpy8lp: mov r3, r7, lspull #8
400 ldmia r1!, {r4 - r7} @ Shouldnt fault 400 ldmia r1!, {r4 - r7} @ Shouldnt fault
401 subs ip, ip, #16 401 subs ip, ip, #16
402 orr r3, r3, r4, push #24 402 orr r3, r3, r4, lspush #24
403 mov r4, r4, pull #8 403 mov r4, r4, lspull #8
404 orr r4, r4, r5, push #24 404 orr r4, r4, r5, lspush #24
405 mov r5, r5, pull #8 405 mov r5, r5, lspull #8
406 orr r5, r5, r6, push #24 406 orr r5, r5, r6, lspush #24
407 mov r6, r6, pull #8 407 mov r6, r6, lspull #8
408 orr r6, r6, r7, push #24 408 orr r6, r6, r7, lspush #24
409 stmia r0!, {r3 - r6} 409 stmia r0!, {r3 - r6}
410 bpl .Lcfu_1cpy8lp 410 bpl .Lcfu_1cpy8lp
411 411
412.Lcfu_1rem8lp: tst ip, #8 412.Lcfu_1rem8lp: tst ip, #8
413 movne r3, r7, pull #8 413 movne r3, r7, lspull #8
414 ldmneia r1!, {r4, r7} @ Shouldnt fault 414 ldmneia r1!, {r4, r7} @ Shouldnt fault
415 orrne r3, r3, r4, push #24 415 orrne r3, r3, r4, lspush #24
416 movne r4, r4, pull #8 416 movne r4, r4, lspull #8
417 orrne r4, r4, r7, push #24 417 orrne r4, r4, r7, lspush #24
418 stmneia r0!, {r3 - r4} 418 stmneia r0!, {r3 - r4}
419 tst ip, #4 419 tst ip, #4
420 movne r3, r7, pull #8 420 movne r3, r7, lspull #8
421USER( TUSER( ldrne) r7, [r1], #4) @ May fault 421USER( TUSER( ldrne) r7, [r1], #4) @ May fault
422 orrne r3, r3, r7, push #24 422 orrne r3, r3, r7, lspush #24
423 strne r3, [r0], #4 423 strne r3, [r0], #4
424 ands ip, ip, #3 424 ands ip, ip, #3
425 beq .Lcfu_1fupi 425 beq .Lcfu_1fupi
@@ -437,9 +437,9 @@ USER( TUSER( ldrne) r7, [r1], #4) @ May fault
437.Lcfu_2fupi: subs r2, r2, #4 437.Lcfu_2fupi: subs r2, r2, #4
438 addmi ip, r2, #4 438 addmi ip, r2, #4
439 bmi .Lcfu_2nowords 439 bmi .Lcfu_2nowords
440 mov r3, r7, pull #16 440 mov r3, r7, lspull #16
441USER( TUSER( ldr) r7, [r1], #4) @ May fault 441USER( TUSER( ldr) r7, [r1], #4) @ May fault
442 orr r3, r3, r7, push #16 442 orr r3, r3, r7, lspush #16
443 str r3, [r0], #4 443 str r3, [r0], #4
444 mov ip, r1, lsl #32 - PAGE_SHIFT 444 mov ip, r1, lsl #32 - PAGE_SHIFT
445 rsb ip, ip, #0 445 rsb ip, ip, #0
@@ -452,30 +452,30 @@ USER( TUSER( ldr) r7, [r1], #4) @ May fault
452 blt .Lcfu_2rem8lp 452 blt .Lcfu_2rem8lp
453 453
454 454
455.Lcfu_2cpy8lp: mov r3, r7, pull #16 455.Lcfu_2cpy8lp: mov r3, r7, lspull #16
456 ldmia r1!, {r4 - r7} @ Shouldnt fault 456 ldmia r1!, {r4 - r7} @ Shouldnt fault
457 subs ip, ip, #16 457 subs ip, ip, #16
458 orr r3, r3, r4, push #16 458 orr r3, r3, r4, lspush #16
459 mov r4, r4, pull #16 459 mov r4, r4, lspull #16
460 orr r4, r4, r5, push #16 460 orr r4, r4, r5, lspush #16
461 mov r5, r5, pull #16 461 mov r5, r5, lspull #16
462 orr r5, r5, r6, push #16 462 orr r5, r5, r6, lspush #16
463 mov r6, r6, pull #16 463 mov r6, r6, lspull #16
464 orr r6, r6, r7, push #16 464 orr r6, r6, r7, lspush #16
465 stmia r0!, {r3 - r6} 465 stmia r0!, {r3 - r6}
466 bpl .Lcfu_2cpy8lp 466 bpl .Lcfu_2cpy8lp
467 467
468.Lcfu_2rem8lp: tst ip, #8 468.Lcfu_2rem8lp: tst ip, #8
469 movne r3, r7, pull #16 469 movne r3, r7, lspull #16
470 ldmneia r1!, {r4, r7} @ Shouldnt fault 470 ldmneia r1!, {r4, r7} @ Shouldnt fault
471 orrne r3, r3, r4, push #16 471 orrne r3, r3, r4, lspush #16
472 movne r4, r4, pull #16 472 movne r4, r4, lspull #16
473 orrne r4, r4, r7, push #16 473 orrne r4, r4, r7, lspush #16
474 stmneia r0!, {r3 - r4} 474 stmneia r0!, {r3 - r4}
475 tst ip, #4 475 tst ip, #4
476 movne r3, r7, pull #16 476 movne r3, r7, lspull #16
477USER( TUSER( ldrne) r7, [r1], #4) @ May fault 477USER( TUSER( ldrne) r7, [r1], #4) @ May fault
478 orrne r3, r3, r7, push #16 478 orrne r3, r3, r7, lspush #16
479 strne r3, [r0], #4 479 strne r3, [r0], #4
480 ands ip, ip, #3 480 ands ip, ip, #3
481 beq .Lcfu_2fupi 481 beq .Lcfu_2fupi
@@ -493,9 +493,9 @@ USER( TUSER( ldrgtb) r3, [r1], #0) @ May fault
493.Lcfu_3fupi: subs r2, r2, #4 493.Lcfu_3fupi: subs r2, r2, #4
494 addmi ip, r2, #4 494 addmi ip, r2, #4
495 bmi .Lcfu_3nowords 495 bmi .Lcfu_3nowords
496 mov r3, r7, pull #24 496 mov r3, r7, lspull #24
497USER( TUSER( ldr) r7, [r1], #4) @ May fault 497USER( TUSER( ldr) r7, [r1], #4) @ May fault
498 orr r3, r3, r7, push #8 498 orr r3, r3, r7, lspush #8
499 str r3, [r0], #4 499 str r3, [r0], #4
500 mov ip, r1, lsl #32 - PAGE_SHIFT 500 mov ip, r1, lsl #32 - PAGE_SHIFT
501 rsb ip, ip, #0 501 rsb ip, ip, #0
@@ -507,30 +507,30 @@ USER( TUSER( ldr) r7, [r1], #4) @ May fault
507 subs ip, ip, #16 507 subs ip, ip, #16
508 blt .Lcfu_3rem8lp 508 blt .Lcfu_3rem8lp
509 509
510.Lcfu_3cpy8lp: mov r3, r7, pull #24 510.Lcfu_3cpy8lp: mov r3, r7, lspull #24
511 ldmia r1!, {r4 - r7} @ Shouldnt fault 511 ldmia r1!, {r4 - r7} @ Shouldnt fault
512 orr r3, r3, r4, push #8 512 orr r3, r3, r4, lspush #8
513 mov r4, r4, pull #24 513 mov r4, r4, lspull #24
514 orr r4, r4, r5, push #8 514 orr r4, r4, r5, lspush #8
515 mov r5, r5, pull #24 515 mov r5, r5, lspull #24
516 orr r5, r5, r6, push #8 516 orr r5, r5, r6, lspush #8
517 mov r6, r6, pull #24 517 mov r6, r6, lspull #24
518 orr r6, r6, r7, push #8 518 orr r6, r6, r7, lspush #8
519 stmia r0!, {r3 - r6} 519 stmia r0!, {r3 - r6}
520 subs ip, ip, #16 520 subs ip, ip, #16
521 bpl .Lcfu_3cpy8lp 521 bpl .Lcfu_3cpy8lp
522 522
523.Lcfu_3rem8lp: tst ip, #8 523.Lcfu_3rem8lp: tst ip, #8
524 movne r3, r7, pull #24 524 movne r3, r7, lspull #24
525 ldmneia r1!, {r4, r7} @ Shouldnt fault 525 ldmneia r1!, {r4, r7} @ Shouldnt fault
526 orrne r3, r3, r4, push #8 526 orrne r3, r3, r4, lspush #8
527 movne r4, r4, pull #24 527 movne r4, r4, lspull #24
528 orrne r4, r4, r7, push #8 528 orrne r4, r4, r7, lspush #8
529 stmneia r0!, {r3 - r4} 529 stmneia r0!, {r3 - r4}
530 tst ip, #4 530 tst ip, #4
531 movne r3, r7, pull #24 531 movne r3, r7, lspull #24
532USER( TUSER( ldrne) r7, [r1], #4) @ May fault 532USER( TUSER( ldrne) r7, [r1], #4) @ May fault
533 orrne r3, r3, r7, push #8 533 orrne r3, r3, r7, lspush #8
534 strne r3, [r0], #4 534 strne r3, [r0], #4
535 ands ip, ip, #3 535 ands ip, ip, #3
536 beq .Lcfu_3fupi 536 beq .Lcfu_3fupi
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index e38b279f402c..384dc859e6c6 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -155,7 +155,7 @@ static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id)
155 155
156static struct irqaction cns3xxx_timer_irq = { 156static struct irqaction cns3xxx_timer_irq = {
157 .name = "timer", 157 .name = "timer",
158 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 158 .flags = IRQF_TIMER | IRQF_IRQPOLL,
159 .handler = cns3xxx_timer_interrupt, 159 .handler = cns3xxx_timer_interrupt,
160}; 160};
161 161
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 68ac934d4565..8254e716b095 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -206,7 +206,7 @@ ebsa110_timer_interrupt(int irq, void *dev_id)
206 206
207static struct irqaction ebsa110_timer_irq = { 207static struct irqaction ebsa110_timer_irq = {
208 .name = "EBSA110 Timer Tick", 208 .name = "EBSA110 Timer Tick",
209 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 209 .flags = IRQF_TIMER | IRQF_IRQPOLL,
210 .handler = ebsa110_timer_interrupt, 210 .handler = ebsa110_timer_interrupt,
211}; 211};
212 212
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c
index 3971104d32d4..bf7aa7d298e7 100644
--- a/arch/arm/mach-footbridge/dc21285-timer.c
+++ b/arch/arm/mach-footbridge/dc21285-timer.c
@@ -105,7 +105,7 @@ static irqreturn_t timer1_interrupt(int irq, void *dev_id)
105static struct irqaction footbridge_timer_irq = { 105static struct irqaction footbridge_timer_irq = {
106 .name = "dc21285_timer1", 106 .name = "dc21285_timer1",
107 .handler = timer1_interrupt, 107 .handler = timer1_interrupt,
108 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 108 .flags = IRQF_TIMER | IRQF_IRQPOLL,
109 .dev_id = &ckevt_dc21285, 109 .dev_id = &ckevt_dc21285,
110}; 110};
111 111
@@ -125,7 +125,7 @@ void __init footbridge_timer_init(void)
125 clockevents_config_and_register(ce, rate, 0x4, 0xffffff); 125 clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
126} 126}
127 127
128static u32 notrace footbridge_read_sched_clock(void) 128static u64 notrace footbridge_read_sched_clock(void)
129{ 129{
130 return ~*CSR_TIMER3_VALUE; 130 return ~*CSR_TIMER3_VALUE;
131} 131}
@@ -138,5 +138,5 @@ void __init footbridge_sched_clock(void)
138 *CSR_TIMER3_CLR = 0; 138 *CSR_TIMER3_CLR = 0;
139 *CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16; 139 *CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
140 140
141 setup_sched_clock(footbridge_read_sched_clock, 24, rate); 141 sched_clock_register(footbridge_read_sched_clock, 24, rate);
142} 142}
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 7c2fdae9a38b..96a3d73ef4bf 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -334,15 +334,15 @@ void __init dc21285_preinit(void)
334 /* 334 /*
335 * We don't care if these fail. 335 * We don't care if these fail.
336 */ 336 */
337 dc21285_request_irq(IRQ_PCI_SERR, dc21285_serr_irq, IRQF_DISABLED, 337 dc21285_request_irq(IRQ_PCI_SERR, dc21285_serr_irq, 0,
338 "PCI system error", &serr_timer); 338 "PCI system error", &serr_timer);
339 dc21285_request_irq(IRQ_PCI_PERR, dc21285_parity_irq, IRQF_DISABLED, 339 dc21285_request_irq(IRQ_PCI_PERR, dc21285_parity_irq, 0,
340 "PCI parity error", &perr_timer); 340 "PCI parity error", &perr_timer);
341 dc21285_request_irq(IRQ_PCI_ABORT, dc21285_abort_irq, IRQF_DISABLED, 341 dc21285_request_irq(IRQ_PCI_ABORT, dc21285_abort_irq, 0,
342 "PCI abort", NULL); 342 "PCI abort", NULL);
343 dc21285_request_irq(IRQ_DISCARD_TIMER, dc21285_discard_irq, IRQF_DISABLED, 343 dc21285_request_irq(IRQ_DISCARD_TIMER, dc21285_discard_irq, 0,
344 "Discard timer", NULL); 344 "Discard timer", NULL);
345 dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, IRQF_DISABLED, 345 dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, 0,
346 "PCI data parity", NULL); 346 "PCI data parity", NULL);
347 347
348 if (cfn_mode) { 348 if (cfn_mode) {
diff --git a/arch/arm/mach-footbridge/isa-timer.c b/arch/arm/mach-footbridge/isa-timer.c
index d9301dd56354..b73f52e196b9 100644
--- a/arch/arm/mach-footbridge/isa-timer.c
+++ b/arch/arm/mach-footbridge/isa-timer.c
@@ -27,7 +27,7 @@ static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
27static struct irqaction pit_timer_irq = { 27static struct irqaction pit_timer_irq = {
28 .name = "pit", 28 .name = "pit",
29 .handler = pit_timer_interrupt, 29 .handler = pit_timer_interrupt,
30 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 30 .flags = IRQF_TIMER | IRQF_IRQPOLL,
31 .dev_id = &i8253_clockevent, 31 .dev_id = &i8253_clockevent,
32}; 32};
33 33
diff --git a/arch/arm/mach-gemini/idle.c b/arch/arm/mach-gemini/idle.c
index 87dff4f5059e..ddf8ec9d203b 100644
--- a/arch/arm/mach-gemini/idle.c
+++ b/arch/arm/mach-gemini/idle.c
@@ -3,7 +3,7 @@
3 */ 3 */
4 4
5#include <linux/init.h> 5#include <linux/init.h>
6#include <asm/system.h> 6#include <asm/system_misc.h>
7#include <asm/proc-fns.h> 7#include <asm/proc-fns.h>
8 8
9static void gemini_idle(void) 9static void gemini_idle(void)
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 17c0fe627435..e4f27f0e56ac 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -358,7 +358,7 @@ static struct clock_event_device integrator_clockevent = {
358 358
359static struct irqaction integrator_timer_irq = { 359static struct irqaction integrator_timer_irq = {
360 .name = "timer", 360 .name = "timer",
361 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 361 .flags = IRQF_TIMER | IRQF_IRQPOLL,
362 .handler = integrator_timer_interrupt, 362 .handler = integrator_timer_interrupt,
363 .dev_id = &integrator_clockevent, 363 .dev_id = &integrator_clockevent,
364}; 364};
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 6d68aed6548a..a465f27bc263 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -312,7 +312,7 @@ static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
312 312
313static struct irqaction ixp4xx_timer_irq = { 313static struct irqaction ixp4xx_timer_irq = {
314 .name = "timer1", 314 .name = "timer1",
315 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 315 .flags = IRQF_TIMER | IRQF_IRQPOLL,
316 .handler = ixp4xx_timer_interrupt, 316 .handler = ixp4xx_timer_interrupt,
317 .dev_id = &clockevent_ixp4xx, 317 .dev_id = &clockevent_ixp4xx,
318}; 318};
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 736dc692d540..43ee06d3abe5 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -233,8 +233,7 @@ static int __init dsmg600_gpio_init(void)
233 233
234 gpio_request(DSMG600_RB_GPIO, "reset button"); 234 gpio_request(DSMG600_RB_GPIO, "reset button");
235 if (request_irq(gpio_to_irq(DSMG600_RB_GPIO), &dsmg600_reset_handler, 235 if (request_irq(gpio_to_irq(DSMG600_RB_GPIO), &dsmg600_reset_handler,
236 IRQF_DISABLED | IRQF_TRIGGER_LOW, 236 IRQF_TRIGGER_LOW, "DSM-G600 reset button", NULL) < 0) {
237 "DSM-G600 reset button", NULL) < 0) {
238 237
239 printk(KERN_DEBUG "Reset Button IRQ %d not available\n", 238 printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
240 gpio_to_irq(DSMG600_RB_GPIO)); 239 gpio_to_irq(DSMG600_RB_GPIO));
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index 429966b756ed..5c4b0c4a1b37 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -208,16 +208,14 @@ static void __init fsg_init(void)
208 platform_add_devices(fsg_devices, ARRAY_SIZE(fsg_devices)); 208 platform_add_devices(fsg_devices, ARRAY_SIZE(fsg_devices));
209 209
210 if (request_irq(gpio_to_irq(FSG_RB_GPIO), &fsg_reset_handler, 210 if (request_irq(gpio_to_irq(FSG_RB_GPIO), &fsg_reset_handler,
211 IRQF_DISABLED | IRQF_TRIGGER_LOW, 211 IRQF_TRIGGER_LOW, "FSG reset button", NULL) < 0) {
212 "FSG reset button", NULL) < 0) {
213 212
214 printk(KERN_DEBUG "Reset Button IRQ %d not available\n", 213 printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
215 gpio_to_irq(FSG_RB_GPIO)); 214 gpio_to_irq(FSG_RB_GPIO));
216 } 215 }
217 216
218 if (request_irq(gpio_to_irq(FSG_SB_GPIO), &fsg_power_handler, 217 if (request_irq(gpio_to_irq(FSG_SB_GPIO), &fsg_power_handler,
219 IRQF_DISABLED | IRQF_TRIGGER_LOW, 218 IRQF_TRIGGER_LOW, "FSG power button", NULL) < 0) {
220 "FSG power button", NULL) < 0) {
221 219
222 printk(KERN_DEBUG "Power Button IRQ %d not available\n", 220 printk(KERN_DEBUG "Power Button IRQ %d not available\n",
223 gpio_to_irq(FSG_SB_GPIO)); 221 gpio_to_irq(FSG_SB_GPIO));
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index 507cb5233537..4e0f762bc651 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -295,8 +295,7 @@ static void __init nas100d_init(void)
295 pm_power_off = nas100d_power_off; 295 pm_power_off = nas100d_power_off;
296 296
297 if (request_irq(gpio_to_irq(NAS100D_RB_GPIO), &nas100d_reset_handler, 297 if (request_irq(gpio_to_irq(NAS100D_RB_GPIO), &nas100d_reset_handler,
298 IRQF_DISABLED | IRQF_TRIGGER_LOW, 298 IRQF_TRIGGER_LOW, "NAS100D reset button", NULL) < 0) {
299 "NAS100D reset button", NULL) < 0) {
300 299
301 printk(KERN_DEBUG "Reset Button IRQ %d not available\n", 300 printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
302 gpio_to_irq(NAS100D_RB_GPIO)); 301 gpio_to_irq(NAS100D_RB_GPIO));
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index ba5f1cda2a9d..88c025f52d8d 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -265,16 +265,14 @@ static void __init nslu2_init(void)
265 pm_power_off = nslu2_power_off; 265 pm_power_off = nslu2_power_off;
266 266
267 if (request_irq(gpio_to_irq(NSLU2_RB_GPIO), &nslu2_reset_handler, 267 if (request_irq(gpio_to_irq(NSLU2_RB_GPIO), &nslu2_reset_handler,
268 IRQF_DISABLED | IRQF_TRIGGER_LOW, 268 IRQF_TRIGGER_LOW, "NSLU2 reset button", NULL) < 0) {
269 "NSLU2 reset button", NULL) < 0) {
270 269
271 printk(KERN_DEBUG "Reset Button IRQ %d not available\n", 270 printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
272 gpio_to_irq(NSLU2_RB_GPIO)); 271 gpio_to_irq(NSLU2_RB_GPIO));
273 } 272 }
274 273
275 if (request_irq(gpio_to_irq(NSLU2_PB_GPIO), &nslu2_power_handler, 274 if (request_irq(gpio_to_irq(NSLU2_PB_GPIO), &nslu2_power_handler,
276 IRQF_DISABLED | IRQF_TRIGGER_HIGH, 275 IRQF_TRIGGER_HIGH, "NSLU2 power button", NULL) < 0) {
277 "NSLU2 power button", NULL) < 0) {
278 276
279 printk(KERN_DEBUG "Power Button IRQ %d not available\n", 277 printk(KERN_DEBUG "Power Button IRQ %d not available\n",
280 gpio_to_irq(NSLU2_PB_GPIO)); 278 gpio_to_irq(NSLU2_PB_GPIO));
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index 426c97662f5b..a197874bf382 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -122,7 +122,7 @@ static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
122 122
123static struct irqaction ks8695_timer_irq = { 123static struct irqaction ks8695_timer_irq = {
124 .name = "ks8695_tick", 124 .name = "ks8695_tick",
125 .flags = IRQF_DISABLED | IRQF_TIMER, 125 .flags = IRQF_TIMER,
126 .handler = ks8695_timer_interrupt, 126 .handler = ks8695_timer_interrupt,
127}; 127};
128 128
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
index 20eab63d10ba..4e5837299c04 100644
--- a/arch/arm/mach-lpc32xx/timer.c
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -90,7 +90,7 @@ static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
90 90
91static struct irqaction lpc32xx_timer_irq = { 91static struct irqaction lpc32xx_timer_irq = {
92 .name = "LPC32XX Timer Tick", 92 .name = "LPC32XX Timer Tick",
93 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 93 .flags = IRQF_TIMER | IRQF_IRQPOLL,
94 .handler = lpc32xx_timer_interrupt, 94 .handler = lpc32xx_timer_interrupt,
95}; 95};
96 96
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 024022d91fe3..bbcd2322fd27 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -186,7 +186,7 @@ static void __init timer_config(void)
186 186
187static struct irqaction timer_irq = { 187static struct irqaction timer_irq = {
188 .name = "timer", 188 .name = "timer",
189 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 189 .flags = IRQF_TIMER | IRQF_IRQPOLL,
190 .handler = timer_interrupt, 190 .handler = timer_interrupt,
191 .dev_id = &ckevt, 191 .dev_id = &ckevt,
192}; 192};
diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c
index 6df42e643031..3177c7a40930 100644
--- a/arch/arm/mach-netx/time.c
+++ b/arch/arm/mach-netx/time.c
@@ -99,7 +99,7 @@ netx_timer_interrupt(int irq, void *dev_id)
99 99
100static struct irqaction netx_timer_irq = { 100static struct irqaction netx_timer_irq = {
101 .name = "NetX Timer Tick", 101 .name = "NetX Timer Tick",
102 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 102 .flags = IRQF_TIMER | IRQF_IRQPOLL,
103 .handler = netx_timer_interrupt, 103 .handler = netx_timer_interrupt,
104}; 104};
105 105
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 5bb8ce86d54b..4be601b638d7 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -32,55 +32,51 @@
32 32
33#define OMAP1_DMA_BASE (0xfffed800) 33#define OMAP1_DMA_BASE (0xfffed800)
34#define OMAP1_LOGICAL_DMA_CH_COUNT 17 34#define OMAP1_LOGICAL_DMA_CH_COUNT 17
35#define OMAP1_DMA_STRIDE 0x40
36 35
37static u32 errata;
38static u32 enable_1510_mode; 36static u32 enable_1510_mode;
39static u8 dma_stride; 37
40static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end; 38static const struct omap_dma_reg reg_map[] = {
41 39 [GCR] = { 0x0400, 0x00, OMAP_DMA_REG_16BIT },
42static u16 reg_map[] = { 40 [GSCR] = { 0x0404, 0x00, OMAP_DMA_REG_16BIT },
43 [GCR] = 0x400, 41 [GRST1] = { 0x0408, 0x00, OMAP_DMA_REG_16BIT },
44 [GSCR] = 0x404, 42 [HW_ID] = { 0x0442, 0x00, OMAP_DMA_REG_16BIT },
45 [GRST1] = 0x408, 43 [PCH2_ID] = { 0x0444, 0x00, OMAP_DMA_REG_16BIT },
46 [HW_ID] = 0x442, 44 [PCH0_ID] = { 0x0446, 0x00, OMAP_DMA_REG_16BIT },
47 [PCH2_ID] = 0x444, 45 [PCH1_ID] = { 0x0448, 0x00, OMAP_DMA_REG_16BIT },
48 [PCH0_ID] = 0x446, 46 [PCHG_ID] = { 0x044a, 0x00, OMAP_DMA_REG_16BIT },
49 [PCH1_ID] = 0x448, 47 [PCHD_ID] = { 0x044c, 0x00, OMAP_DMA_REG_16BIT },
50 [PCHG_ID] = 0x44a, 48 [CAPS_0] = { 0x044e, 0x00, OMAP_DMA_REG_2X16BIT },
51 [PCHD_ID] = 0x44c, 49 [CAPS_1] = { 0x0452, 0x00, OMAP_DMA_REG_2X16BIT },
52 [CAPS_0] = 0x44e, 50 [CAPS_2] = { 0x0456, 0x00, OMAP_DMA_REG_16BIT },
53 [CAPS_1] = 0x452, 51 [CAPS_3] = { 0x0458, 0x00, OMAP_DMA_REG_16BIT },
54 [CAPS_2] = 0x456, 52 [CAPS_4] = { 0x045a, 0x00, OMAP_DMA_REG_16BIT },
55 [CAPS_3] = 0x458, 53 [PCH2_SR] = { 0x0460, 0x00, OMAP_DMA_REG_16BIT },
56 [CAPS_4] = 0x45a, 54 [PCH0_SR] = { 0x0480, 0x00, OMAP_DMA_REG_16BIT },
57 [PCH2_SR] = 0x460, 55 [PCH1_SR] = { 0x0482, 0x00, OMAP_DMA_REG_16BIT },
58 [PCH0_SR] = 0x480, 56 [PCHD_SR] = { 0x04c0, 0x00, OMAP_DMA_REG_16BIT },
59 [PCH1_SR] = 0x482,
60 [PCHD_SR] = 0x4c0,
61 57
62 /* Common Registers */ 58 /* Common Registers */
63 [CSDP] = 0x00, 59 [CSDP] = { 0x0000, 0x40, OMAP_DMA_REG_16BIT },
64 [CCR] = 0x02, 60 [CCR] = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
65 [CICR] = 0x04, 61 [CICR] = { 0x0004, 0x40, OMAP_DMA_REG_16BIT },
66 [CSR] = 0x06, 62 [CSR] = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
67 [CEN] = 0x10, 63 [CEN] = { 0x0010, 0x40, OMAP_DMA_REG_16BIT },
68 [CFN] = 0x12, 64 [CFN] = { 0x0012, 0x40, OMAP_DMA_REG_16BIT },
69 [CSFI] = 0x14, 65 [CSFI] = { 0x0014, 0x40, OMAP_DMA_REG_16BIT },
70 [CSEI] = 0x16, 66 [CSEI] = { 0x0016, 0x40, OMAP_DMA_REG_16BIT },
71 [CPC] = 0x18, /* 15xx only */ 67 [CPC] = { 0x0018, 0x40, OMAP_DMA_REG_16BIT }, /* 15xx only */
72 [CSAC] = 0x18, 68 [CSAC] = { 0x0018, 0x40, OMAP_DMA_REG_16BIT },
73 [CDAC] = 0x1a, 69 [CDAC] = { 0x001a, 0x40, OMAP_DMA_REG_16BIT },
74 [CDEI] = 0x1c, 70 [CDEI] = { 0x001c, 0x40, OMAP_DMA_REG_16BIT },
75 [CDFI] = 0x1e, 71 [CDFI] = { 0x001e, 0x40, OMAP_DMA_REG_16BIT },
76 [CLNK_CTRL] = 0x28, 72 [CLNK_CTRL] = { 0x0028, 0x40, OMAP_DMA_REG_16BIT },
77 73
78 /* Channel specific register offsets */ 74 /* Channel specific register offsets */
79 [CSSA] = 0x08, 75 [CSSA] = { 0x0008, 0x40, OMAP_DMA_REG_2X16BIT },
80 [CDSA] = 0x0c, 76 [CDSA] = { 0x000c, 0x40, OMAP_DMA_REG_2X16BIT },
81 [COLOR] = 0x20, 77 [COLOR] = { 0x0020, 0x40, OMAP_DMA_REG_2X16BIT },
82 [CCR2] = 0x24, 78 [CCR2] = { 0x0024, 0x40, OMAP_DMA_REG_16BIT },
83 [LCH_CTRL] = 0x2a, 79 [LCH_CTRL] = { 0x002a, 0x40, OMAP_DMA_REG_16BIT },
84}; 80};
85 81
86static struct resource res[] __initdata = { 82static struct resource res[] __initdata = {
@@ -181,44 +177,36 @@ static struct resource res[] __initdata = {
181static void __iomem *dma_base; 177static void __iomem *dma_base;
182static inline void dma_write(u32 val, int reg, int lch) 178static inline void dma_write(u32 val, int reg, int lch)
183{ 179{
184 u8 stride; 180 void __iomem *addr = dma_base;
185 u32 offset;
186 181
187 stride = (reg >= dma_common_ch_start) ? dma_stride : 0; 182 addr += reg_map[reg].offset;
188 offset = reg_map[reg] + (stride * lch); 183 addr += reg_map[reg].stride * lch;
189 184
190 __raw_writew(val, dma_base + offset); 185 __raw_writew(val, addr);
191 if ((reg > CLNK_CTRL && reg < CCEN) || 186 if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
192 (reg > PCHD_ID && reg < CAPS_2)) { 187 __raw_writew(val >> 16, addr + 2);
193 u32 offset2 = reg_map[reg] + 2 + (stride * lch);
194 __raw_writew(val >> 16, dma_base + offset2);
195 }
196} 188}
197 189
198static inline u32 dma_read(int reg, int lch) 190static inline u32 dma_read(int reg, int lch)
199{ 191{
200 u8 stride; 192 void __iomem *addr = dma_base;
201 u32 offset, val; 193 uint32_t val;
202 194
203 stride = (reg >= dma_common_ch_start) ? dma_stride : 0; 195 addr += reg_map[reg].offset;
204 offset = reg_map[reg] + (stride * lch); 196 addr += reg_map[reg].stride * lch;
205 197
206 val = __raw_readw(dma_base + offset); 198 val = __raw_readw(addr);
207 if ((reg > CLNK_CTRL && reg < CCEN) || 199 if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
208 (reg > PCHD_ID && reg < CAPS_2)) { 200 val |= __raw_readw(addr + 2) << 16;
209 u16 upper; 201
210 u32 offset2 = reg_map[reg] + 2 + (stride * lch);
211 upper = __raw_readw(dma_base + offset2);
212 val |= (upper << 16);
213 }
214 return val; 202 return val;
215} 203}
216 204
217static void omap1_clear_lch_regs(int lch) 205static void omap1_clear_lch_regs(int lch)
218{ 206{
219 int i = dma_common_ch_start; 207 int i;
220 208
221 for (; i <= dma_common_ch_end; i += 1) 209 for (i = CPC; i <= COLOR; i += 1)
222 dma_write(0, i, lch); 210 dma_write(0, i, lch);
223} 211}
224 212
@@ -255,8 +243,9 @@ static void omap1_show_dma_caps(void)
255 return; 243 return;
256} 244}
257 245
258static u32 configure_dma_errata(void) 246static unsigned configure_dma_errata(void)
259{ 247{
248 unsigned errata = 0;
260 249
261 /* 250 /*
262 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is 251 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
@@ -272,11 +261,23 @@ static const struct platform_device_info omap_dma_dev_info = {
272 .name = "omap-dma-engine", 261 .name = "omap-dma-engine",
273 .id = -1, 262 .id = -1,
274 .dma_mask = DMA_BIT_MASK(32), 263 .dma_mask = DMA_BIT_MASK(32),
264 .res = res,
265 .num_res = 1,
266};
267
268static struct omap_system_dma_plat_info dma_plat_info __initdata = {
269 .reg_map = reg_map,
270 .channel_stride = 0x40,
271 .show_dma_caps = omap1_show_dma_caps,
272 .clear_lch_regs = omap1_clear_lch_regs,
273 .clear_dma = omap1_clear_dma,
274 .dma_write = dma_write,
275 .dma_read = dma_read,
275}; 276};
276 277
277static int __init omap1_system_dma_init(void) 278static int __init omap1_system_dma_init(void)
278{ 279{
279 struct omap_system_dma_plat_info *p; 280 struct omap_system_dma_plat_info p;
280 struct omap_dma_dev_attr *d; 281 struct omap_dma_dev_attr *d;
281 struct platform_device *pdev, *dma_pdev; 282 struct platform_device *pdev, *dma_pdev;
282 int ret; 283 int ret;
@@ -302,20 +303,12 @@ static int __init omap1_system_dma_init(void)
302 goto exit_iounmap; 303 goto exit_iounmap;
303 } 304 }
304 305
305 p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
306 if (!p) {
307 dev_err(&pdev->dev, "%s: Unable to allocate 'p' for %s\n",
308 __func__, pdev->name);
309 ret = -ENOMEM;
310 goto exit_iounmap;
311 }
312
313 d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL); 306 d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
314 if (!d) { 307 if (!d) {
315 dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n", 308 dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
316 __func__, pdev->name); 309 __func__, pdev->name);
317 ret = -ENOMEM; 310 ret = -ENOMEM;
318 goto exit_release_p; 311 goto exit_iounmap;
319 } 312 }
320 313
321 d->lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; 314 d->lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
@@ -336,17 +329,6 @@ static int __init omap1_system_dma_init(void)
336 d->dev_caps |= CLEAR_CSR_ON_READ; 329 d->dev_caps |= CLEAR_CSR_ON_READ;
337 d->dev_caps |= IS_WORD_16; 330 d->dev_caps |= IS_WORD_16;
338 331
339
340 d->chan = kzalloc(sizeof(struct omap_dma_lch) *
341 (d->lch_count), GFP_KERNEL);
342 if (!d->chan) {
343 dev_err(&pdev->dev,
344 "%s: Memory allocation failed for d->chan!\n",
345 __func__);
346 ret = -ENOMEM;
347 goto exit_release_d;
348 }
349
350 if (cpu_is_omap15xx()) 332 if (cpu_is_omap15xx())
351 d->chan_count = 9; 333 d->chan_count = 9;
352 else if (cpu_is_omap16xx() || cpu_is_omap7xx()) { 334 else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
@@ -356,35 +338,24 @@ static int __init omap1_system_dma_init(void)
356 d->chan_count = 9; 338 d->chan_count = 9;
357 } 339 }
358 340
359 p->dma_attr = d; 341 p = dma_plat_info;
360 342 p.dma_attr = d;
361 p->show_dma_caps = omap1_show_dma_caps; 343 p.errata = configure_dma_errata();
362 p->clear_lch_regs = omap1_clear_lch_regs;
363 p->clear_dma = omap1_clear_dma;
364 p->dma_write = dma_write;
365 p->dma_read = dma_read;
366 p->disable_irq_lch = NULL;
367
368 p->errata = configure_dma_errata();
369 344
370 ret = platform_device_add_data(pdev, p, sizeof(*p)); 345 ret = platform_device_add_data(pdev, &p, sizeof(p));
371 if (ret) { 346 if (ret) {
372 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n", 347 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
373 __func__, pdev->name, pdev->id); 348 __func__, pdev->name, pdev->id);
374 goto exit_release_chan; 349 goto exit_release_d;
375 } 350 }
376 351
377 ret = platform_device_add(pdev); 352 ret = platform_device_add(pdev);
378 if (ret) { 353 if (ret) {
379 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n", 354 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
380 __func__, pdev->name, pdev->id); 355 __func__, pdev->name, pdev->id);
381 goto exit_release_chan; 356 goto exit_release_d;
382 } 357 }
383 358
384 dma_stride = OMAP1_DMA_STRIDE;
385 dma_common_ch_start = CPC;
386 dma_common_ch_end = COLOR;
387
388 dma_pdev = platform_device_register_full(&omap_dma_dev_info); 359 dma_pdev = platform_device_register_full(&omap_dma_dev_info);
389 if (IS_ERR(dma_pdev)) { 360 if (IS_ERR(dma_pdev)) {
390 ret = PTR_ERR(dma_pdev); 361 ret = PTR_ERR(dma_pdev);
@@ -395,12 +366,8 @@ static int __init omap1_system_dma_init(void)
395 366
396exit_release_pdev: 367exit_release_pdev:
397 platform_device_del(pdev); 368 platform_device_del(pdev);
398exit_release_chan:
399 kfree(d->chan);
400exit_release_d: 369exit_release_d:
401 kfree(d); 370 kfree(d);
402exit_release_p:
403 kfree(p);
404exit_iounmap: 371exit_iounmap:
405 iounmap(dma_base); 372 iounmap(dma_base);
406exit_device_put: 373exit_device_put:
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index 25b79a297365..6a6935caac1e 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -17,7 +17,6 @@
17 17
18#include <linux/err.h> 18#include <linux/err.h>
19#include <linux/davinci_emac.h> 19#include <linux/davinci_emac.h>
20#include <asm/system.h>
21#include "omap_device.h" 20#include "omap_device.h"
22#include "am35xx.h" 21#include "am35xx.h"
23#include "control.h" 22#include "control.h"
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 49fd0d501c9b..5689c88d986d 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -35,97 +35,80 @@
35#include "omap_hwmod.h" 35#include "omap_hwmod.h"
36#include "omap_device.h" 36#include "omap_device.h"
37 37
38#define OMAP2_DMA_STRIDE 0x60 38static enum omap_reg_offsets dma_common_ch_end;
39 39
40static u32 errata; 40static const struct omap_dma_reg reg_map[] = {
41static u8 dma_stride; 41 [REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
42 42 [GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
43static struct omap_dma_dev_attr *d; 43 [IRQSTATUS_L0] = { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
44 44 [IRQSTATUS_L1] = { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
45static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end; 45 [IRQSTATUS_L2] = { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
46 46 [IRQSTATUS_L3] = { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
47static u16 reg_map[] = { 47 [IRQENABLE_L0] = { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
48 [REVISION] = 0x00, 48 [IRQENABLE_L1] = { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
49 [GCR] = 0x78, 49 [IRQENABLE_L2] = { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
50 [IRQSTATUS_L0] = 0x08, 50 [IRQENABLE_L3] = { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
51 [IRQSTATUS_L1] = 0x0c, 51 [SYSSTATUS] = { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
52 [IRQSTATUS_L2] = 0x10, 52 [OCP_SYSCONFIG] = { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
53 [IRQSTATUS_L3] = 0x14, 53 [CAPS_0] = { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
54 [IRQENABLE_L0] = 0x18, 54 [CAPS_2] = { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
55 [IRQENABLE_L1] = 0x1c, 55 [CAPS_3] = { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
56 [IRQENABLE_L2] = 0x20, 56 [CAPS_4] = { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
57 [IRQENABLE_L3] = 0x24,
58 [SYSSTATUS] = 0x28,
59 [OCP_SYSCONFIG] = 0x2c,
60 [CAPS_0] = 0x64,
61 [CAPS_2] = 0x6c,
62 [CAPS_3] = 0x70,
63 [CAPS_4] = 0x74,
64 57
65 /* Common register offsets */ 58 /* Common register offsets */
66 [CCR] = 0x80, 59 [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
67 [CLNK_CTRL] = 0x84, 60 [CLNK_CTRL] = { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
68 [CICR] = 0x88, 61 [CICR] = { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
69 [CSR] = 0x8c, 62 [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
70 [CSDP] = 0x90, 63 [CSDP] = { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
71 [CEN] = 0x94, 64 [CEN] = { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
72 [CFN] = 0x98, 65 [CFN] = { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
73 [CSEI] = 0xa4, 66 [CSEI] = { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
74 [CSFI] = 0xa8, 67 [CSFI] = { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
75 [CDEI] = 0xac, 68 [CDEI] = { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
76 [CDFI] = 0xb0, 69 [CDFI] = { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
77 [CSAC] = 0xb4, 70 [CSAC] = { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
78 [CDAC] = 0xb8, 71 [CDAC] = { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
79 72
80 /* Channel specific register offsets */ 73 /* Channel specific register offsets */
81 [CSSA] = 0x9c, 74 [CSSA] = { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
82 [CDSA] = 0xa0, 75 [CDSA] = { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
83 [CCEN] = 0xbc, 76 [CCEN] = { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
84 [CCFN] = 0xc0, 77 [CCFN] = { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
85 [COLOR] = 0xc4, 78 [COLOR] = { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
86 79
87 /* OMAP4 specific registers */ 80 /* OMAP4 specific registers */
88 [CDP] = 0xd0, 81 [CDP] = { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
89 [CNDP] = 0xd4, 82 [CNDP] = { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
90 [CCDN] = 0xd8, 83 [CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
91}; 84};
92 85
93static void __iomem *dma_base; 86static void __iomem *dma_base;
94static inline void dma_write(u32 val, int reg, int lch) 87static inline void dma_write(u32 val, int reg, int lch)
95{ 88{
96 u8 stride; 89 void __iomem *addr = dma_base;
97 u32 offset;
98 90
99 stride = (reg >= dma_common_ch_start) ? dma_stride : 0; 91 addr += reg_map[reg].offset;
100 offset = reg_map[reg] + (stride * lch); 92 addr += reg_map[reg].stride * lch;
101 __raw_writel(val, dma_base + offset); 93
94 __raw_writel(val, addr);
102} 95}
103 96
104static inline u32 dma_read(int reg, int lch) 97static inline u32 dma_read(int reg, int lch)
105{ 98{
106 u8 stride; 99 void __iomem *addr = dma_base;
107 u32 offset, val;
108
109 stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
110 offset = reg_map[reg] + (stride * lch);
111 val = __raw_readl(dma_base + offset);
112 return val;
113}
114 100
115static inline void omap2_disable_irq_lch(int lch) 101 addr += reg_map[reg].offset;
116{ 102 addr += reg_map[reg].stride * lch;
117 u32 val;
118 103
119 val = dma_read(IRQENABLE_L0, lch); 104 return __raw_readl(addr);
120 val &= ~(1 << lch);
121 dma_write(val, IRQENABLE_L0, lch);
122} 105}
123 106
124static void omap2_clear_dma(int lch) 107static void omap2_clear_dma(int lch)
125{ 108{
126 int i = dma_common_ch_start; 109 int i;
127 110
128 for (; i <= dma_common_ch_end; i += 1) 111 for (i = CSDP; i <= dma_common_ch_end; i += 1)
129 dma_write(0, i, lch); 112 dma_write(0, i, lch);
130} 113}
131 114
@@ -137,8 +120,9 @@ static void omap2_show_dma_caps(void)
137 return; 120 return;
138} 121}
139 122
140static u32 configure_dma_errata(void) 123static unsigned configure_dma_errata(void)
141{ 124{
125 unsigned errata = 0;
142 126
143 /* 127 /*
144 * Errata applicable for OMAP2430ES1.0 and all omap2420 128 * Errata applicable for OMAP2430ES1.0 and all omap2420
@@ -220,48 +204,50 @@ static u32 configure_dma_errata(void)
220 return errata; 204 return errata;
221} 205}
222 206
207static struct omap_system_dma_plat_info dma_plat_info __initdata = {
208 .reg_map = reg_map,
209 .channel_stride = 0x60,
210 .show_dma_caps = omap2_show_dma_caps,
211 .clear_dma = omap2_clear_dma,
212 .dma_write = dma_write,
213 .dma_read = dma_read,
214};
215
216static struct platform_device_info omap_dma_dev_info = {
217 .name = "omap-dma-engine",
218 .id = -1,
219 .dma_mask = DMA_BIT_MASK(32),
220};
221
223/* One time initializations */ 222/* One time initializations */
224static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) 223static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
225{ 224{
226 struct platform_device *pdev; 225 struct platform_device *pdev;
227 struct omap_system_dma_plat_info *p; 226 struct omap_system_dma_plat_info p;
227 struct omap_dma_dev_attr *d;
228 struct resource *mem; 228 struct resource *mem;
229 char *name = "omap_dma_system"; 229 char *name = "omap_dma_system";
230 230
231 dma_stride = OMAP2_DMA_STRIDE; 231 p = dma_plat_info;
232 dma_common_ch_start = CSDP; 232 p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
233 233 p.errata = configure_dma_errata();
234 p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
235 if (!p) {
236 pr_err("%s: Unable to allocate pdata for %s:%s\n",
237 __func__, name, oh->name);
238 return -ENOMEM;
239 }
240
241 p->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
242 p->disable_irq_lch = omap2_disable_irq_lch;
243 p->show_dma_caps = omap2_show_dma_caps;
244 p->clear_dma = omap2_clear_dma;
245 p->dma_write = dma_write;
246 p->dma_read = dma_read;
247
248 p->clear_lch_regs = NULL;
249
250 p->errata = configure_dma_errata();
251 234
252 pdev = omap_device_build(name, 0, oh, p, sizeof(*p)); 235 pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
253 kfree(p);
254 if (IS_ERR(pdev)) { 236 if (IS_ERR(pdev)) {
255 pr_err("%s: Can't build omap_device for %s:%s.\n", 237 pr_err("%s: Can't build omap_device for %s:%s.\n",
256 __func__, name, oh->name); 238 __func__, name, oh->name);
257 return PTR_ERR(pdev); 239 return PTR_ERR(pdev);
258 } 240 }
259 241
242 omap_dma_dev_info.res = pdev->resource;
243 omap_dma_dev_info.num_res = pdev->num_resources;
244
260 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 245 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
261 if (!mem) { 246 if (!mem) {
262 dev_err(&pdev->dev, "%s: no mem resource\n", __func__); 247 dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
263 return -EINVAL; 248 return -EINVAL;
264 } 249 }
250
265 dma_base = ioremap(mem->start, resource_size(mem)); 251 dma_base = ioremap(mem->start, resource_size(mem));
266 if (!dma_base) { 252 if (!dma_base) {
267 dev_err(&pdev->dev, "%s: ioremap fail\n", __func__); 253 dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
@@ -269,13 +255,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
269 } 255 }
270 256
271 d = oh->dev_attr; 257 d = oh->dev_attr;
272 d->chan = kzalloc(sizeof(struct omap_dma_lch) *
273 (d->lch_count), GFP_KERNEL);
274
275 if (!d->chan) {
276 dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
277 return -ENOMEM;
278 }
279 258
280 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) 259 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
281 d->dev_caps |= HS_CHANNELS_RESERVED; 260 d->dev_caps |= HS_CHANNELS_RESERVED;
@@ -289,12 +268,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
289 return 0; 268 return 0;
290} 269}
291 270
292static const struct platform_device_info omap_dma_dev_info = {
293 .name = "omap-dma-engine",
294 .id = -1,
295 .dma_mask = DMA_BIT_MASK(32),
296};
297
298static int __init omap2_system_dma_init(void) 271static int __init omap2_system_dma_init(void)
299{ 272{
300 struct platform_device *pdev; 273 struct platform_device *pdev;
diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c
index 85883b2e0e49..6d3517dc4772 100644
--- a/arch/arm/mach-rpc/dma.c
+++ b/arch/arm/mach-rpc/dma.c
@@ -141,7 +141,7 @@ static int iomd_request_dma(unsigned int chan, dma_t *dma)
141 struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); 141 struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
142 142
143 return request_irq(idma->irq, iomd_dma_handle, 143 return request_irq(idma->irq, iomd_dma_handle,
144 IRQF_DISABLED, idma->dma.device_id, idma); 144 0, idma->dma.device_id, idma);
145} 145}
146 146
147static void iomd_free_dma(unsigned int chan, dma_t *dma) 147static void iomd_free_dma(unsigned int chan, dma_t *dma)
diff --git a/arch/arm/mach-rpc/time.c b/arch/arm/mach-rpc/time.c
index 9a6def14df01..9a5158861ca9 100644
--- a/arch/arm/mach-rpc/time.c
+++ b/arch/arm/mach-rpc/time.c
@@ -75,7 +75,6 @@ ioc_timer_interrupt(int irq, void *dev_id)
75 75
76static struct irqaction ioc_timer_irq = { 76static struct irqaction ioc_timer_irq = {
77 .name = "timer", 77 .name = "timer",
78 .flags = IRQF_DISABLED,
79 .handler = ioc_timer_interrupt 78 .handler = ioc_timer_interrupt
80}; 79};
81 80
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 831a15824ec8..f9874ba60cc8 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -43,6 +43,7 @@
43#include <asm/mach/arch.h> 43#include <asm/mach/arch.h>
44#include <asm/mach/flash.h> 44#include <asm/mach/flash.h>
45#include <asm/mach/map.h> 45#include <asm/mach/map.h>
46#include <asm/mach/irda.h>
46 47
47#include <asm/hardware/scoop.h> 48#include <asm/hardware/scoop.h>
48#include <asm/mach/sharpsl_param.h> 49#include <asm/mach/sharpsl_param.h>
@@ -96,6 +97,37 @@ static struct mcp_plat_data collie_mcp_data = {
96 .codec_pdata = &collie_ucb1x00_data, 97 .codec_pdata = &collie_ucb1x00_data,
97}; 98};
98 99
100static int collie_ir_startup(struct device *dev)
101{
102 int rc = gpio_request(COLLIE_GPIO_IR_ON, "IrDA");
103 if (rc)
104 return rc;
105 rc = gpio_direction_output(COLLIE_GPIO_IR_ON, 1);
106
107 if (!rc)
108 return 0;
109
110 gpio_free(COLLIE_GPIO_IR_ON);
111 return rc;
112}
113
114static void collie_ir_shutdown(struct device *dev)
115{
116 gpio_free(COLLIE_GPIO_IR_ON);
117}
118
119static int collie_ir_set_power(struct device *dev, unsigned int state)
120{
121 gpio_set_value(COLLIE_GPIO_IR_ON, !state);
122 return 0;
123}
124
125static struct irda_platform_data collie_ir_data = {
126 .startup = collie_ir_startup,
127 .shutdown = collie_ir_shutdown,
128 .set_power = collie_ir_set_power,
129};
130
99/* 131/*
100 * Collie AC IN 132 * Collie AC IN
101 */ 133 */
@@ -400,6 +432,7 @@ static void __init collie_init(void)
400 sa11x0_register_mtd(&collie_flash_data, collie_flash_resources, 432 sa11x0_register_mtd(&collie_flash_data, collie_flash_resources,
401 ARRAY_SIZE(collie_flash_resources)); 433 ARRAY_SIZE(collie_flash_resources));
402 sa11x0_register_mcp(&collie_mcp_data); 434 sa11x0_register_mcp(&collie_mcp_data);
435 sa11x0_register_irda(&collie_ir_data);
403 436
404 sharpsl_save_param(); 437 sharpsl_save_param();
405} 438}
diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c
index daa27c474c13..3c43219bc881 100644
--- a/arch/arm/mach-sa1100/h3100.c
+++ b/arch/arm/mach-sa1100/h3100.c
@@ -122,15 +122,8 @@ static struct irda_platform_data h3100_irda_data = {
122 .shutdown = h3100_irda_shutdown, 122 .shutdown = h3100_irda_shutdown,
123}; 123};
124 124
125static struct gpio_default_state h3100_default_gpio[] = {
126 { H3XXX_GPIO_COM_DCD, GPIO_MODE_IN, "COM DCD" },
127 { H3XXX_GPIO_COM_CTS, GPIO_MODE_IN, "COM CTS" },
128 { H3XXX_GPIO_COM_RTS, GPIO_MODE_OUT0, "COM RTS" },
129};
130
131static void __init h3100_mach_init(void) 125static void __init h3100_mach_init(void)
132{ 126{
133 h3xxx_init_gpio(h3100_default_gpio, ARRAY_SIZE(h3100_default_gpio));
134 h3xxx_mach_init(); 127 h3xxx_mach_init();
135 128
136 sa11x0_register_lcd(&h3100_lcd_info); 129 sa11x0_register_lcd(&h3100_lcd_info);
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index a663e7230141..5be54c214c7c 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -130,15 +130,8 @@ static struct irda_platform_data h3600_irda_data = {
130 .shutdown = h3600_irda_shutdown, 130 .shutdown = h3600_irda_shutdown,
131}; 131};
132 132
133static struct gpio_default_state h3600_default_gpio[] = {
134 { H3XXX_GPIO_COM_DCD, GPIO_MODE_IN, "COM DCD" },
135 { H3XXX_GPIO_COM_CTS, GPIO_MODE_IN, "COM CTS" },
136 { H3XXX_GPIO_COM_RTS, GPIO_MODE_OUT0, "COM RTS" },
137};
138
139static void __init h3600_mach_init(void) 133static void __init h3600_mach_init(void)
140{ 134{
141 h3xxx_init_gpio(h3600_default_gpio, ARRAY_SIZE(h3600_default_gpio));
142 h3xxx_mach_init(); 135 h3xxx_mach_init();
143 136
144 sa11x0_register_lcd(&h3600_lcd_info); 137 sa11x0_register_lcd(&h3600_lcd_info);
diff --git a/arch/arm/mach-sa1100/h3xxx.c b/arch/arm/mach-sa1100/h3xxx.c
index f17e7382242a..c79bf467fb7f 100644
--- a/arch/arm/mach-sa1100/h3xxx.c
+++ b/arch/arm/mach-sa1100/h3xxx.c
@@ -28,37 +28,6 @@
28 28
29#include "generic.h" 29#include "generic.h"
30 30
31void h3xxx_init_gpio(struct gpio_default_state *s, size_t n)
32{
33 while (n--) {
34 const char *name = s->name;
35 int err;
36
37 if (!name)
38 name = "[init]";
39 err = gpio_request(s->gpio, name);
40 if (err) {
41 printk(KERN_ERR "gpio%u: unable to request: %d\n",
42 s->gpio, err);
43 continue;
44 }
45 if (s->mode >= 0) {
46 err = gpio_direction_output(s->gpio, s->mode);
47 } else {
48 err = gpio_direction_input(s->gpio);
49 }
50 if (err) {
51 printk(KERN_ERR "gpio%u: unable to set direction: %d\n",
52 s->gpio, err);
53 continue;
54 }
55 if (!s->name)
56 gpio_free(s->gpio);
57 s++;
58 }
59}
60
61
62/* 31/*
63 * H3xxx flash support 32 * H3xxx flash support
64 */ 33 */
@@ -116,9 +85,34 @@ static struct resource h3xxx_flash_resource =
116/* 85/*
117 * H3xxx uart support 86 * H3xxx uart support
118 */ 87 */
88static struct gpio h3xxx_uart_gpio[] = {
89 { H3XXX_GPIO_COM_DCD, GPIOF_IN, "COM DCD" },
90 { H3XXX_GPIO_COM_CTS, GPIOF_IN, "COM CTS" },
91 { H3XXX_GPIO_COM_RTS, GPIOF_OUT_INIT_LOW, "COM RTS" },
92};
93
94static bool h3xxx_uart_request_gpios(void)
95{
96 static bool h3xxx_uart_gpio_ok;
97 int rc;
98
99 if (h3xxx_uart_gpio_ok)
100 return true;
101
102 rc = gpio_request_array(h3xxx_uart_gpio, ARRAY_SIZE(h3xxx_uart_gpio));
103 if (rc)
104 pr_err("h3xxx_uart_request_gpios: error %d\n", rc);
105 else
106 h3xxx_uart_gpio_ok = true;
107
108 return h3xxx_uart_gpio_ok;
109}
110
119static void h3xxx_uart_set_mctrl(struct uart_port *port, u_int mctrl) 111static void h3xxx_uart_set_mctrl(struct uart_port *port, u_int mctrl)
120{ 112{
121 if (port->mapbase == _Ser3UTCR0) { 113 if (port->mapbase == _Ser3UTCR0) {
114 if (!h3xxx_uart_request_gpios())
115 return;
122 gpio_set_value(H3XXX_GPIO_COM_RTS, !(mctrl & TIOCM_RTS)); 116 gpio_set_value(H3XXX_GPIO_COM_RTS, !(mctrl & TIOCM_RTS));
123 } 117 }
124} 118}
@@ -128,6 +122,8 @@ static u_int h3xxx_uart_get_mctrl(struct uart_port *port)
128 u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; 122 u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
129 123
130 if (port->mapbase == _Ser3UTCR0) { 124 if (port->mapbase == _Ser3UTCR0) {
125 if (!h3xxx_uart_request_gpios())
126 return ret;
131 /* 127 /*
132 * DCD and CTS bits are inverted in GPLR by RS232 transceiver 128 * DCD and CTS bits are inverted in GPLR by RS232 transceiver
133 */ 129 */
diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h
index f33679d2d3ee..b478ca180c19 100644
--- a/arch/arm/mach-sa1100/include/mach/collie.h
+++ b/arch/arm/mach-sa1100/include/mach/collie.h
@@ -13,6 +13,8 @@
13#ifndef __ASM_ARCH_COLLIE_H 13#ifndef __ASM_ARCH_COLLIE_H
14#define __ASM_ARCH_COLLIE_H 14#define __ASM_ARCH_COLLIE_H
15 15
16#include "hardware.h" /* Gives GPIO_MAX */
17
16extern void locomolcd_power(int on); 18extern void locomolcd_power(int on);
17 19
18#define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1) 20#define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1)
@@ -78,7 +80,7 @@ extern void locomolcd_power(int on);
78#define COLLIE_TC35143_GPIO_VERSION0 UCB_IO_0 80#define COLLIE_TC35143_GPIO_VERSION0 UCB_IO_0
79#define COLLIE_TC35143_GPIO_TBL_CHK UCB_IO_1 81#define COLLIE_TC35143_GPIO_TBL_CHK UCB_IO_1
80#define COLLIE_TC35143_GPIO_VPEN_ON UCB_IO_2 82#define COLLIE_TC35143_GPIO_VPEN_ON UCB_IO_2
81#define COLLIE_TC35143_GPIO_IR_ON UCB_IO_3 83#define COLLIE_GPIO_IR_ON (COLLIE_TC35143_GPIO_BASE + 3)
82#define COLLIE_TC35143_GPIO_AMP_ON UCB_IO_4 84#define COLLIE_TC35143_GPIO_AMP_ON UCB_IO_4
83#define COLLIE_TC35143_GPIO_VERSION1 UCB_IO_5 85#define COLLIE_TC35143_GPIO_VERSION1 UCB_IO_5
84#define COLLIE_TC35143_GPIO_FS8KLPF UCB_IO_5 86#define COLLIE_TC35143_GPIO_FS8KLPF UCB_IO_5
diff --git a/arch/arm/mach-sa1100/include/mach/h3xxx.h b/arch/arm/mach-sa1100/include/mach/h3xxx.h
index c810620db53d..603d4343f7f6 100644
--- a/arch/arm/mach-sa1100/include/mach/h3xxx.h
+++ b/arch/arm/mach-sa1100/include/mach/h3xxx.h
@@ -79,17 +79,6 @@
79#define H3600_EGPIO_LCD_5V_ON (H3XXX_EGPIO_BASE + 14) /* enable 5V to LCD. active high. */ 79#define H3600_EGPIO_LCD_5V_ON (H3XXX_EGPIO_BASE + 14) /* enable 5V to LCD. active high. */
80#define H3600_EGPIO_LVDD_ON (H3XXX_EGPIO_BASE + 15) /* enable 9V and -6.5V to LCD. */ 80#define H3600_EGPIO_LVDD_ON (H3XXX_EGPIO_BASE + 15) /* enable 9V and -6.5V to LCD. */
81 81
82struct gpio_default_state {
83 int gpio;
84 int mode;
85 const char *name;
86};
87
88#define GPIO_MODE_IN -1
89#define GPIO_MODE_OUT0 0
90#define GPIO_MODE_OUT1 1
91
92void h3xxx_init_gpio(struct gpio_default_state *s, size_t n);
93void __init h3xxx_map_io(void); 82void __init h3xxx_map_io(void);
94void __init h3xxx_mach_init(void); 83void __init h3xxx_mach_init(void);
95 84
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 6fd4acb8f187..4852c08cb526 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -112,7 +112,7 @@ static struct clock_event_device ckevt_sa1100_osmr0 = {
112 112
113static struct irqaction sa1100_timer_irq = { 113static struct irqaction sa1100_timer_irq = {
114 .name = "ost0", 114 .name = "ost0",
115 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 115 .flags = IRQF_TIMER | IRQF_IRQPOLL,
116 .handler = sa1100_ost0_interrupt, 116 .handler = sa1100_ost0_interrupt,
117 .dev_id = &ckevt_sa1100_osmr0, 117 .dev_id = &ckevt_sa1100_osmr0,
118}; 118};
diff --git a/arch/arm/mach-spear/time.c b/arch/arm/mach-spear/time.c
index d449673e40f7..218ba5b67d92 100644
--- a/arch/arm/mach-spear/time.c
+++ b/arch/arm/mach-spear/time.c
@@ -172,7 +172,7 @@ static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
172 172
173static struct irqaction spear_timer_irq = { 173static struct irqaction spear_timer_irq = {
174 .name = "timer", 174 .name = "timer",
175 .flags = IRQF_DISABLED | IRQF_TIMER, 175 .flags = IRQF_TIMER,
176 .handler = spear_timer_interrupt 176 .handler = spear_timer_interrupt
177}; 177};
178 178
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index fe08fd34c0ce..de52cb37c479 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -337,7 +337,7 @@ static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
337 337
338static struct irqaction u300_timer_irq = { 338static struct irqaction u300_timer_irq = {
339 .name = "U300 Timer Tick", 339 .name = "U300 Timer Tick",
340 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 340 .flags = IRQF_TIMER | IRQF_IRQPOLL,
341 .handler = u300_timer_interrupt, 341 .handler = u300_timer_interrupt,
342}; 342};
343 343
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 0997e0b7494c..fc649bc09d0c 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -8,8 +8,11 @@ obj-y := v2m.o
8obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o 8obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
9obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o 9obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o
10CFLAGS_dcscb.o += -march=armv7-a 10CFLAGS_dcscb.o += -march=armv7-a
11CFLAGS_REMOVE_dcscb.o = -pg
11obj-$(CONFIG_ARCH_VEXPRESS_SPC) += spc.o 12obj-$(CONFIG_ARCH_VEXPRESS_SPC) += spc.o
13CFLAGS_REMOVE_spc.o = -pg
12obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o 14obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o
13CFLAGS_tc2_pm.o += -march=armv7-a 15CFLAGS_tc2_pm.o += -march=armv7-a
16CFLAGS_REMOVE_tc2_pm.o = -pg
14obj-$(CONFIG_SMP) += platsmp.o 17obj-$(CONFIG_SMP) += platsmp.o
15obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 18obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
index 14d499688736..788495d35cf9 100644
--- a/arch/arm/mach-vexpress/dcscb.c
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -137,11 +137,16 @@ static void dcscb_power_down(void)
137 v7_exit_coherency_flush(all); 137 v7_exit_coherency_flush(all);
138 138
139 /* 139 /*
140 * This is a harmless no-op. On platforms with a real 140 * A full outer cache flush could be needed at this point
141 * outer cache this might either be needed or not, 141 * on platforms with such a cache, depending on where the
142 * depending on where the outer cache sits. 142 * outer cache sits. In some cases the notion of a "last
143 * cluster standing" would need to be implemented if the
144 * outer cache is shared across clusters. In any case, when
145 * the outer cache needs flushing, there is no concurrent
146 * access to the cache controller to worry about and no
147 * special locking besides what is already provided by the
148 * MCPM state machinery is needed.
143 */ 149 */
144 outer_flush_all();
145 150
146 /* 151 /*
147 * Disable cluster-level coherency by masking 152 * Disable cluster-level coherency by masking
diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c
index 30fbca844575..9230d3725599 100644
--- a/arch/arm/mach-w90x900/time.c
+++ b/arch/arm/mach-w90x900/time.c
@@ -111,7 +111,7 @@ static irqreturn_t nuc900_timer0_interrupt(int irq, void *dev_id)
111 111
112static struct irqaction nuc900_timer0_irq = { 112static struct irqaction nuc900_timer0_irq = {
113 .name = "nuc900-timer0", 113 .name = "nuc900-timer0",
114 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 114 .flags = IRQF_TIMER | IRQF_IRQPOLL,
115 .handler = nuc900_timer0_interrupt, 115 .handler = nuc900_timer0_interrupt,
116}; 116};
117 117
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 1f8fed94c2a4..ca8ecdee47d8 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -446,7 +446,6 @@ config CPU_32v5
446 446
447config CPU_32v6 447config CPU_32v6
448 bool 448 bool
449 select CPU_USE_DOMAINS if CPU_V6 && MMU
450 select TLS_REG_EMUL if !CPU_32v6K && !MMU 449 select TLS_REG_EMUL if !CPU_32v6K && !MMU
451 450
452config CPU_32v6K 451config CPU_32v6K
@@ -671,7 +670,7 @@ config ARM_VIRT_EXT
671 670
672config SWP_EMULATE 671config SWP_EMULATE
673 bool "Emulate SWP/SWPB instructions" 672 bool "Emulate SWP/SWPB instructions"
674 depends on !CPU_USE_DOMAINS && CPU_V7 673 depends on CPU_V7
675 default y if SMP 674 default y if SMP
676 select HAVE_PROC_CPU if PROC_FS 675 select HAVE_PROC_CPU if PROC_FS
677 help 676 help
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index 48bc3c0a87ce..aae891820f8f 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -331,7 +331,9 @@ static void __init enable_l2(void)
331 enable_icache(); 331 enable_icache();
332 if (d) 332 if (d)
333 enable_dcache(); 333 enable_dcache();
334 } 334 } else
335 pr_err(FW_BUG
336 "Feroceon L2: bootloader left the L2 cache on!\n");
335} 337}
336 338
337void __init feroceon_l2_init(int __l2_wt_override) 339void __init feroceon_l2_init(int __l2_wt_override)
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 11b3914660d2..c9c6acdf90cc 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -284,9 +284,6 @@ static void __dma_free_buffer(struct page *page, size_t size)
284} 284}
285 285
286#ifdef CONFIG_MMU 286#ifdef CONFIG_MMU
287#ifdef CONFIG_HUGETLB_PAGE
288#warning ARM Coherent DMA allocator does not (yet) support huge TLB
289#endif
290 287
291static void *__alloc_from_contiguous(struct device *dev, size_t size, 288static void *__alloc_from_contiguous(struct device *dev, size_t size,
292 pgprot_t prot, struct page **ret_page, 289 pgprot_t prot, struct page **ret_page,
diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c
index 2b3a56414271..c508f41a43bc 100644
--- a/arch/arm/mm/dump.c
+++ b/arch/arm/mm/dump.c
@@ -120,34 +120,51 @@ static const struct prot_bits pte_bits[] = {
120}; 120};
121 121
122static const struct prot_bits section_bits[] = { 122static const struct prot_bits section_bits[] = {
123#ifndef CONFIG_ARM_LPAE 123#ifdef CONFIG_ARM_LPAE
124 /* These are approximate */ 124 {
125 .mask = PMD_SECT_USER,
126 .val = PMD_SECT_USER,
127 .set = "USR",
128 }, {
129 .mask = PMD_SECT_RDONLY,
130 .val = PMD_SECT_RDONLY,
131 .set = "ro",
132 .clear = "RW",
133#elif __LINUX_ARM_ARCH__ >= 6
125 { 134 {
126 .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, 135 .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
127 .val = 0, 136 .val = PMD_SECT_APX | PMD_SECT_AP_WRITE,
128 .set = " ro", 137 .set = " ro",
129 }, { 138 }, {
130 .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, 139 .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
131 .val = PMD_SECT_AP_WRITE, 140 .val = PMD_SECT_AP_WRITE,
132 .set = " RW", 141 .set = " RW",
133 }, { 142 }, {
134 .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, 143 .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
135 .val = PMD_SECT_AP_READ, 144 .val = PMD_SECT_AP_READ,
136 .set = "USR ro", 145 .set = "USR ro",
137 }, { 146 }, {
138 .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, 147 .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
139 .val = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, 148 .val = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
140 .set = "USR RW", 149 .set = "USR RW",
141#else 150#else /* ARMv4/ARMv5 */
151 /* These are approximate */
142 { 152 {
143 .mask = PMD_SECT_USER, 153 .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
144 .val = PMD_SECT_USER, 154 .val = 0,
145 .set = "USR", 155 .set = " ro",
146 }, { 156 }, {
147 .mask = PMD_SECT_RDONLY, 157 .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
148 .val = PMD_SECT_RDONLY, 158 .val = PMD_SECT_AP_WRITE,
149 .set = "ro", 159 .set = " RW",
150 .clear = "RW", 160 }, {
161 .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
162 .val = PMD_SECT_AP_READ,
163 .set = "USR ro",
164 }, {
165 .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
166 .val = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
167 .set = "USR RW",
151#endif 168#endif
152 }, { 169 }, {
153 .mask = PMD_SECT_XN, 170 .mask = PMD_SECT_XN,
@@ -264,6 +281,9 @@ static void walk_pmd(struct pg_state *st, pud_t *pud, unsigned long start)
264 note_page(st, addr, 3, pmd_val(*pmd)); 281 note_page(st, addr, 3, pmd_val(*pmd));
265 else 282 else
266 walk_pte(st, pmd, addr); 283 walk_pte(st, pmd, addr);
284
285 if (SECTION_SIZE < PMD_SIZE && pmd_large(pmd[1]))
286 note_page(st, addr + SECTION_SIZE, 3, pmd_val(pmd[1]));
267 } 287 }
268} 288}
269 289
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index a623cb3ad012..b68c6b22e1c8 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -516,6 +516,16 @@ static void __init build_mem_type_table(void)
516 s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2; 516 s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
517 517
518 /* 518 /*
519 * We don't use domains on ARMv6 (since this causes problems with
520 * v6/v7 kernels), so we must use a separate memory type for user
521 * r/o, kernel r/w to map the vectors page.
522 */
523#ifndef CONFIG_ARM_LPAE
524 if (cpu_arch == CPU_ARCH_ARMv6)
525 vecs_pgprot |= L_PTE_MT_VECTORS;
526#endif
527
528 /*
519 * ARMv6 and above have extended page tables. 529 * ARMv6 and above have extended page tables.
520 */ 530 */
521 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { 531 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index e3c48a3fe063..ee1d80593958 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -112,13 +112,9 @@
112 * 100x 1 0 1 r/o no acc 112 * 100x 1 0 1 r/o no acc
113 * 10x0 1 0 1 r/o no acc 113 * 10x0 1 0 1 r/o no acc
114 * 1011 0 0 1 r/w no acc 114 * 1011 0 0 1 r/w no acc
115 * 110x 0 1 0 r/w r/o
116 * 11x0 0 1 0 r/w r/o
117 * 1111 0 1 1 r/w r/w
118 *
119 * If !CONFIG_CPU_USE_DOMAINS, the following permissions are changed:
120 * 110x 1 1 1 r/o r/o 115 * 110x 1 1 1 r/o r/o
121 * 11x0 1 1 1 r/o r/o 116 * 11x0 1 1 1 r/o r/o
117 * 1111 0 1 1 r/w r/w
122 */ 118 */
123 .macro armv6_mt_table pfx 119 .macro armv6_mt_table pfx
124\pfx\()_mt_table: 120\pfx\()_mt_table:
@@ -137,7 +133,7 @@
137 .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED 133 .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
138 .long 0x00 @ unused 134 .long 0x00 @ unused
139 .long 0x00 @ unused 135 .long 0x00 @ unused
140 .long 0x00 @ unused 136 .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS
141 .endm 137 .endm
142 138
143 .macro armv6_set_pte_ext pfx 139 .macro armv6_set_pte_ext pfx
@@ -158,24 +154,21 @@
158 154
159 tst r1, #L_PTE_USER 155 tst r1, #L_PTE_USER
160 orrne r3, r3, #PTE_EXT_AP1 156 orrne r3, r3, #PTE_EXT_AP1
161#ifdef CONFIG_CPU_USE_DOMAINS
162 @ allow kernel read/write access to read-only user pages
163 tstne r3, #PTE_EXT_APX 157 tstne r3, #PTE_EXT_APX
164 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 158
165#endif 159 @ user read-only -> kernel read-only
160 bicne r3, r3, #PTE_EXT_AP0
166 161
167 tst r1, #L_PTE_XN 162 tst r1, #L_PTE_XN
168 orrne r3, r3, #PTE_EXT_XN 163 orrne r3, r3, #PTE_EXT_XN
169 164
170 orr r3, r3, r2 165 eor r3, r3, r2
171 166
172 tst r1, #L_PTE_YOUNG 167 tst r1, #L_PTE_YOUNG
173 tstne r1, #L_PTE_PRESENT 168 tstne r1, #L_PTE_PRESENT
174 moveq r3, #0 169 moveq r3, #0
175#ifndef CONFIG_CPU_USE_DOMAINS
176 tstne r1, #L_PTE_NONE 170 tstne r1, #L_PTE_NONE
177 movne r3, #0 171 movne r3, #0
178#endif
179 172
180 str r3, [r0] 173 str r3, [r0]
181 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 174 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index bdd3be4be77a..1f52915f2b28 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -90,21 +90,14 @@ ENTRY(cpu_v7_set_pte_ext)
90 90
91 tst r1, #L_PTE_USER 91 tst r1, #L_PTE_USER
92 orrne r3, r3, #PTE_EXT_AP1 92 orrne r3, r3, #PTE_EXT_AP1
93#ifdef CONFIG_CPU_USE_DOMAINS
94 @ allow kernel read/write access to read-only user pages
95 tstne r3, #PTE_EXT_APX
96 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
97#endif
98 93
99 tst r1, #L_PTE_XN 94 tst r1, #L_PTE_XN
100 orrne r3, r3, #PTE_EXT_XN 95 orrne r3, r3, #PTE_EXT_XN
101 96
102 tst r1, #L_PTE_YOUNG 97 tst r1, #L_PTE_YOUNG
103 tstne r1, #L_PTE_VALID 98 tstne r1, #L_PTE_VALID
104#ifndef CONFIG_CPU_USE_DOMAINS
105 eorne r1, r1, #L_PTE_NONE 99 eorne r1, r1, #L_PTE_NONE
106 tstne r1, #L_PTE_NONE 100 tstne r1, #L_PTE_NONE
107#endif
108 moveq r3, #0 101 moveq r3, #0
109 102
110 ARM( str r3, [r0, #2048]! ) 103 ARM( str r3, [r0, #2048]! )
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 74f6033e76dd..195731d3813b 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -192,6 +192,7 @@ __v7_cr7mp_setup:
192 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting 192 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
193 b 1f 193 b 1f
194__v7_ca7mp_setup: 194__v7_ca7mp_setup:
195__v7_ca12mp_setup:
195__v7_ca15mp_setup: 196__v7_ca15mp_setup:
196 mov r10, #0 197 mov r10, #0
1971: 1981:
@@ -484,6 +485,16 @@ __v7_ca7mp_proc_info:
484 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info 485 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
485 486
486 /* 487 /*
488 * ARM Ltd. Cortex A12 processor.
489 */
490 .type __v7_ca12mp_proc_info, #object
491__v7_ca12mp_proc_info:
492 .long 0x410fc0d0
493 .long 0xff0ffff0
494 __v7_proc __v7_ca12mp_setup
495 .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
496
497 /*
487 * ARM Ltd. Cortex A15 processor. 498 * ARM Ltd. Cortex A15 processor.
488 */ 499 */
489 .type __v7_ca15mp_proc_info, #object 500 .type __v7_ca15mp_proc_info, #object
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index d70b73364a3f..6ad65d8ae237 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -127,7 +127,7 @@ iop_timer_interrupt(int irq, void *dev_id)
127static struct irqaction iop_timer_irq = { 127static struct irqaction iop_timer_irq = {
128 .name = "IOP Timer Tick", 128 .name = "IOP Timer Tick",
129 .handler = iop_timer_interrupt, 129 .handler = iop_timer_interrupt,
130 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 130 .flags = IRQF_TIMER | IRQF_IRQPOLL,
131 .dev_id = &iop_clockevent, 131 .dev_id = &iop_clockevent,
132}; 132};
133 133
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 01619c2910e3..5f5b975887fc 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2000,6 +2000,12 @@ void omap_dma_global_context_restore(void)
2000 omap_clear_dma(ch); 2000 omap_clear_dma(ch);
2001} 2001}
2002 2002
2003struct omap_system_dma_plat_info *omap_get_plat_info(void)
2004{
2005 return p;
2006}
2007EXPORT_SYMBOL_GPL(omap_get_plat_info);
2008
2003static int omap_system_dma_probe(struct platform_device *pdev) 2009static int omap_system_dma_probe(struct platform_device *pdev)
2004{ 2010{
2005 int ch, ret = 0; 2011 int ch, ret = 0;
@@ -2024,9 +2030,16 @@ static int omap_system_dma_probe(struct platform_device *pdev)
2024 2030
2025 dma_lch_count = d->lch_count; 2031 dma_lch_count = d->lch_count;
2026 dma_chan_count = dma_lch_count; 2032 dma_chan_count = dma_lch_count;
2027 dma_chan = d->chan;
2028 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; 2033 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
2029 2034
2035 dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count,
2036 sizeof(struct omap_dma_lch), GFP_KERNEL);
2037 if (!dma_chan) {
2038 dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
2039 return -ENOMEM;
2040 }
2041
2042
2030 if (dma_omap2plus()) { 2043 if (dma_omap2plus()) {
2031 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * 2044 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2032 dma_lch_count, GFP_KERNEL); 2045 dma_lch_count, GFP_KERNEL);
@@ -2111,7 +2124,6 @@ exit_dma_irq_fail:
2111 } 2124 }
2112 2125
2113exit_dma_lch_fail: 2126exit_dma_lch_fail:
2114 kfree(dma_chan);
2115 return ret; 2127 return ret;
2116} 2128}
2117 2129
@@ -2131,7 +2143,6 @@ static int omap_system_dma_remove(struct platform_device *pdev)
2131 free_irq(dma_irq, (void *)(irq_rel + 1)); 2143 free_irq(dma_irq, (void *)(irq_rel + 1));
2132 } 2144 }
2133 } 2145 }
2134 kfree(dma_chan);
2135 return 0; 2146 return 0;
2136} 2147}
2137 2148
diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
index 46e17492fd1f..f0759e70fb86 100644
--- a/arch/arm/vfp/entry.S
+++ b/arch/arm/vfp/entry.S
@@ -8,9 +8,12 @@
8 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11#include <linux/init.h>
12#include <linux/linkage.h>
11#include <asm/thread_info.h> 13#include <asm/thread_info.h>
12#include <asm/vfpmacros.h> 14#include <asm/vfpmacros.h>
13#include "../kernel/entry-header.S" 15#include <asm/assembler.h>
16#include <asm/asm-offsets.h>
14 17
15@ VFP entry point. 18@ VFP entry point.
16@ 19@
@@ -22,11 +25,7 @@
22@ IRQs disabled. 25@ IRQs disabled.
23@ 26@
24ENTRY(do_vfp) 27ENTRY(do_vfp)
25#ifdef CONFIG_PREEMPT_COUNT 28 inc_preempt_count r10, r4
26 ldr r4, [r10, #TI_PREEMPT] @ get preempt count
27 add r11, r4, #1 @ increment it
28 str r11, [r10, #TI_PREEMPT]
29#endif
30 enable_irq 29 enable_irq
31 ldr r4, .LCvfp 30 ldr r4, .LCvfp
32 ldr r11, [r10, #TI_CPU] @ CPU number 31 ldr r11, [r10, #TI_CPU] @ CPU number
@@ -35,12 +34,7 @@ ENTRY(do_vfp)
35ENDPROC(do_vfp) 34ENDPROC(do_vfp)
36 35
37ENTRY(vfp_null_entry) 36ENTRY(vfp_null_entry)
38#ifdef CONFIG_PREEMPT_COUNT 37 dec_preempt_count_ti r10, r4
39 get_thread_info r10
40 ldr r4, [r10, #TI_PREEMPT] @ get preempt count
41 sub r11, r4, #1 @ decrement it
42 str r11, [r10, #TI_PREEMPT]
43#endif
44 mov pc, lr 38 mov pc, lr
45ENDPROC(vfp_null_entry) 39ENDPROC(vfp_null_entry)
46 40
@@ -53,12 +47,7 @@ ENDPROC(vfp_null_entry)
53 47
54 __INIT 48 __INIT
55ENTRY(vfp_testing_entry) 49ENTRY(vfp_testing_entry)
56#ifdef CONFIG_PREEMPT_COUNT 50 dec_preempt_count_ti r10, r4
57 get_thread_info r10
58 ldr r4, [r10, #TI_PREEMPT] @ get preempt count
59 sub r11, r4, #1 @ decrement it
60 str r11, [r10, #TI_PREEMPT]
61#endif
62 ldr r0, VFP_arch_address 51 ldr r0, VFP_arch_address
63 str r0, [r0] @ set to non-zero value 52 str r0, [r0] @ set to non-zero value
64 mov pc, r9 @ we have handled the fault 53 mov pc, r9 @ we have handled the fault
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index 3e5d3115a2a6..be807625ed8c 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -14,10 +14,13 @@
14 * r10 points at the start of the private FP workspace in the thread structure 14 * r10 points at the start of the private FP workspace in the thread structure
15 * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h) 15 * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
16 */ 16 */
17#include <linux/init.h>
18#include <linux/linkage.h>
17#include <asm/thread_info.h> 19#include <asm/thread_info.h>
18#include <asm/vfpmacros.h> 20#include <asm/vfpmacros.h>
19#include <linux/kern_levels.h> 21#include <linux/kern_levels.h>
20#include "../kernel/entry-header.S" 22#include <asm/assembler.h>
23#include <asm/asm-offsets.h>
21 24
22 .macro DBGSTR, str 25 .macro DBGSTR, str
23#ifdef DEBUG 26#ifdef DEBUG
@@ -179,12 +182,7 @@ vfp_hw_state_valid:
179 @ else it's one 32-bit instruction, so 182 @ else it's one 32-bit instruction, so
180 @ always subtract 4 from the following 183 @ always subtract 4 from the following
181 @ instruction address. 184 @ instruction address.
182#ifdef CONFIG_PREEMPT_COUNT 185 dec_preempt_count_ti r10, r4
183 get_thread_info r10
184 ldr r4, [r10, #TI_PREEMPT] @ get preempt count
185 sub r11, r4, #1 @ decrement it
186 str r11, [r10, #TI_PREEMPT]
187#endif
188 mov pc, r9 @ we think we have handled things 186 mov pc, r9 @ we think we have handled things
189 187
190 188
@@ -203,12 +201,7 @@ look_for_VFP_exceptions:
203 @ not recognised by VFP 201 @ not recognised by VFP
204 202
205 DBGSTR "not VFP" 203 DBGSTR "not VFP"
206#ifdef CONFIG_PREEMPT_COUNT 204 dec_preempt_count_ti r10, r4
207 get_thread_info r10
208 ldr r4, [r10, #TI_PREEMPT] @ get preempt count
209 sub r11, r4, #1 @ decrement it
210 str r11, [r10, #TI_PREEMPT]
211#endif
212 mov pc, lr 205 mov pc, lr
213 206
214process_exception: 207process_exception:
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 02:20:35 -0500