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-rw-r--r--arch/arm/boot/dts/Makefile4
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi5
-rw-r--r--arch/arm/boot/dts/exynos4x12-pinctrl.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5420-arndale-octa.dts4
-rw-r--r--arch/arm/boot/dts/exynos5420-peach-pit.dts8
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos5800-peach-pi.dts8
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts1
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts3
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts59
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064-ap148.dts8
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064.dtsi33
-rw-r--r--arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts17
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi12
-rw-r--r--arch/arm/boot/dts/socfpga_arria5.dtsi2
-rw-r--r--arch/arm/boot/dts/socfpga_arria5_socdk.dts12
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_socdk.dts15
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_sockit.dts12
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi24
-rw-r--r--arch/arm/configs/exynos_defconfig10
-rw-r--r--arch/arm/configs/multi_v7_defconfig2
-rw-r--r--arch/arm/configs/omap2plus_defconfig1
-rw-r--r--arch/arm/configs/sunxi_defconfig2
-rw-r--r--arch/arm/kernel/asm-offsets.c12
-rw-r--r--arch/arm/kernel/ptrace.c4
-rw-r--r--arch/arm/mach-exynos/exynos.c2
-rw-r--r--arch/arm/mach-highbank/highbank.c2
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c14
-rw-r--r--arch/arm/mach-socfpga/core.h2
-rw-r--r--arch/arm/mach-socfpga/headsmp.S25
-rw-r--r--arch/arm/mach-socfpga/platsmp.c4
-rw-r--r--arch/arm/mach-socfpga/socfpga.c4
-rw-r--r--arch/arm/mm/init.c8
-rw-r--r--arch/arm/mm/proc-macros.S2
-rw-r--r--arch/arm/plat-samsung/Kconfig5
-rw-r--r--arch/arm/plat-samsung/pm-debug.c1
36 files changed, 278 insertions, 55 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7c80af906897..38c89cafa1ab 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -354,13 +354,15 @@ dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \
354 orion5x-rd88f5182-nas.dtb 354 orion5x-rd88f5182-nas.dtb
355dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb 355dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
356dtb-$(CONFIG_ARCH_QCOM) += \ 356dtb-$(CONFIG_ARCH_QCOM) += \
357 qcom-apq8064-cm-qs600.dtb \
357 qcom-apq8064-ifc6410.dtb \ 358 qcom-apq8064-ifc6410.dtb \
358 qcom-apq8074-dragonboard.dtb \ 359 qcom-apq8074-dragonboard.dtb \
359 qcom-apq8084-ifc6540.dtb \ 360 qcom-apq8084-ifc6540.dtb \
360 qcom-apq8084-mtp.dtb \ 361 qcom-apq8084-mtp.dtb \
361 qcom-ipq8064-ap148.dtb \ 362 qcom-ipq8064-ap148.dtb \
362 qcom-msm8660-surf.dtb \ 363 qcom-msm8660-surf.dtb \
363 qcom-msm8960-cdp.dtb 364 qcom-msm8960-cdp.dtb \
365 qcom-msm8974-sony-xperia-honami.dtb
364dtb-$(CONFIG_ARCH_ROCKCHIP) += \ 366dtb-$(CONFIG_ARCH_ROCKCHIP) += \
365 rk3066a-bqcurie2.dtb \ 367 rk3066a-bqcurie2.dtb \
366 rk3188-radxarock.dtb \ 368 rk3188-radxarock.dtb \
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index d68b3c4862bc..51416c7d0625 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -122,9 +122,10 @@
122 interrupts-extended = <&pmc AT91_PMC_LOCKB>; 122 interrupts-extended = <&pmc AT91_PMC_LOCKB>;
123 clocks = <&main>; 123 clocks = <&main>;
124 reg = <1>; 124 reg = <1>;
125 atmel,clk-input-range = <1000000 5000000>; 125 atmel,clk-input-range = <1000000 32000000>;
126 #atmel,pll-clk-output-range-cells = <4>; 126 #atmel,pll-clk-output-range-cells = <4>;
127 atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; 127 atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
128 <190000000 240000000 2 1>;
128 }; 129 };
129 130
130 mck: masterck { 131 mck: masterck {
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
index 99b26df8dbc7..0865a2e33f97 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -675,7 +675,7 @@
675 sd4_bus8: sd4-bus-width8 { 675 sd4_bus8: sd4-bus-width8 {
676 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; 676 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
677 samsung,pin-function = <4>; 677 samsung,pin-function = <4>;
678 samsung,pin-pud = <4>; 678 samsung,pin-pud = <3>;
679 samsung,pin-drv = <3>; 679 samsung,pin-drv = <3>;
680 }; 680 };
681 681
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 4f2df61c1cfc..aa7a7d727a7e 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -368,3 +368,7 @@
368 }; 368 };
369 }; 369 };
370}; 370};
371
372&usbdrd_dwc3_1 {
373 dr_mode = "host";
374};
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 9a233828539c..82cdb74484cc 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -838,6 +838,14 @@
838 status = "okay"; 838 status = "okay";
839}; 839};
840 840
841&usbdrd_dwc3_0 {
842 dr_mode = "host";
843};
844
845&usbdrd_dwc3_1 {
846 dr_mode = "host";
847};
848
841&usbdrd_phy0 { 849&usbdrd_phy0 {
842 vbus-supply = <&usb300_vbus_reg>; 850 vbus-supply = <&usb300_vbus_reg>;
843}; 851};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index bfe056d9148c..8617a031cbc0 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -815,7 +815,7 @@
815 #size-cells = <1>; 815 #size-cells = <1>;
816 ranges; 816 ranges;
817 817
818 dwc3 { 818 usbdrd_dwc3_0: dwc3 {
819 compatible = "snps,dwc3"; 819 compatible = "snps,dwc3";
820 reg = <0x12000000 0x10000>; 820 reg = <0x12000000 0x10000>;
821 interrupts = <0 72 0>; 821 interrupts = <0 72 0>;
@@ -841,7 +841,7 @@
841 #size-cells = <1>; 841 #size-cells = <1>;
842 ranges; 842 ranges;
843 843
844 dwc3 { 844 usbdrd_dwc3_1: dwc3 {
845 compatible = "snps,dwc3"; 845 compatible = "snps,dwc3";
846 reg = <0x12400000 0x10000>; 846 reg = <0x12400000 0x10000>;
847 interrupts = <0 73 0>; 847 interrupts = <0 73 0>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 1d31c8132558..7bb1c8dd42dd 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -826,6 +826,14 @@
826 status = "okay"; 826 status = "okay";
827}; 827};
828 828
829&usbdrd_dwc3_0 {
830 dr_mode = "host";
831};
832
833&usbdrd_dwc3_1 {
834 dr_mode = "host";
835};
836
829&usbdrd_phy0 { 837&usbdrd_phy0 {
830 vbus-supply = <&usb300_vbus_reg>; 838 vbus-supply = <&usb300_vbus_reg>;
831}; 839};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 09664fcf5afb..0e13b4b10a92 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -193,7 +193,6 @@
193 i2c0: i2c@80058000 { 193 i2c0: i2c@80058000 {
194 pinctrl-names = "default"; 194 pinctrl-names = "default";
195 pinctrl-0 = <&i2c0_pins_a>; 195 pinctrl-0 = <&i2c0_pins_a>;
196 clock-frequency = <400000>;
197 status = "okay"; 196 status = "okay";
198 197
199 sgtl5000: codec@0a { 198 sgtl5000: codec@0a {
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 286bbf620c77..bc82a12d4c2c 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -659,6 +659,9 @@
659 659
660 ethernet@gpmc { 660 ethernet@gpmc {
661 compatible = "smsc,lan91c94"; 661 compatible = "smsc,lan91c94";
662
663 status = "disabled";
664
662 interrupt-parent = <&gpio2>; 665 interrupt-parent = <&gpio2>;
663 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ 666 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
664 reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */ 667 reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */
diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
new file mode 100644
index 000000000000..5d75666f7f6c
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
@@ -0,0 +1,59 @@
1#include "qcom-apq8064-v2.0.dtsi"
2
3/ {
4 model = "CompuLab CM-QS600";
5 compatible = "qcom,apq8064-cm-qs600", "qcom,apq8064";
6
7 soc {
8 pinctrl@800000 {
9 i2c1_pins: i2c1 {
10 mux {
11 pins = "gpio20", "gpio21";
12 function = "gsbi1";
13 };
14 };
15 };
16
17 gsbi@12440000 {
18 status = "okay";
19 qcom,mode = <GSBI_PROT_I2C>;
20
21 i2c@12460000 {
22 status = "okay";
23 clock-frequency = <200000>;
24 pinctrl-0 = <&i2c1_pins>;
25 pinctrl-names = "default";
26
27 eeprom: eeprom@50 {
28 compatible = "24c02";
29 reg = <0x50>;
30 pagesize = <32>;
31 };
32 };
33 };
34
35 gsbi@16600000 {
36 status = "ok";
37 qcom,mode = <GSBI_PROT_I2C_UART>;
38 serial@16640000 {
39 status = "ok";
40 };
41 };
42
43 amba {
44 /* eMMC */
45 sdcc1: sdcc@12400000 {
46 status = "okay";
47 };
48
49 /* External micro SD card */
50 sdcc3: sdcc@12180000 {
51 status = "okay";
52 };
53 /* WLAN */
54 sdcc4: sdcc@121c0000 {
55 status = "okay";
56 };
57 };
58 };
59};
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index 95e64955fb8e..55b2910efd87 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -81,5 +81,13 @@
81 }; 81 };
82 }; 82 };
83 }; 83 };
84
85 sata-phy@1b400000 {
86 status = "ok";
87 };
88
89 sata@29000000 {
90 status = "ok";
91 };
84 }; 92 };
85}; 93};
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 244f857f0e6f..63b2146f563b 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -234,6 +234,39 @@
234 }; 234 };
235 }; 235 };
236 236
237 sata_phy: sata-phy@1b400000 {
238 compatible = "qcom,ipq806x-sata-phy";
239 reg = <0x1b400000 0x200>;
240
241 clocks = <&gcc SATA_PHY_CFG_CLK>;
242 clock-names = "cfg";
243
244 #phy-cells = <0>;
245 status = "disabled";
246 };
247
248 sata@29000000 {
249 compatible = "qcom,ipq806x-ahci", "generic-ahci";
250 reg = <0x29000000 0x180>;
251
252 interrupts = <0 209 0x0>;
253
254 clocks = <&gcc SFAB_SATA_S_H_CLK>,
255 <&gcc SATA_H_CLK>,
256 <&gcc SATA_A_CLK>,
257 <&gcc SATA_RXOOB_CLK>,
258 <&gcc SATA_PMALIVE_CLK>;
259 clock-names = "slave_face", "iface", "core",
260 "rxoob", "pmalive";
261
262 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
263 assigned-clock-rates = <100000000>, <100000000>;
264
265 phys = <&sata_phy>;
266 phy-names = "sata-phy";
267 status = "disabled";
268 };
269
237 qcom,ssbi@500000 { 270 qcom,ssbi@500000 {
238 compatible = "qcom,ssbi"; 271 compatible = "qcom,ssbi";
239 reg = <0x00500000 0x1000>; 272 reg = <0x00500000 0x1000>;
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
new file mode 100644
index 000000000000..cccc21b7c8fd
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
@@ -0,0 +1,17 @@
1#include "qcom-msm8974.dtsi"
2
3/ {
4 model = "Sony Xperia Z1";
5 compatible = "sony,xperia-honami", "qcom,msm8974";
6
7 memory@0 {
8 reg = <0 0x40000000>, <0x40000000 0x40000000>;
9 device_type = "memory";
10 };
11};
12
13&soc {
14 serial@f991e000 {
15 status = "ok";
16 };
17};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 45fce2cf6fed..4472fd92685c 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -547,7 +547,7 @@
547 status = "disabled"; 547 status = "disabled";
548 }; 548 };
549 549
550 gpio@ff708000 { 550 gpio0: gpio@ff708000 {
551 #address-cells = <1>; 551 #address-cells = <1>;
552 #size-cells = <0>; 552 #size-cells = <0>;
553 compatible = "snps,dw-apb-gpio"; 553 compatible = "snps,dw-apb-gpio";
@@ -555,7 +555,7 @@
555 clocks = <&per_base_clk>; 555 clocks = <&per_base_clk>;
556 status = "disabled"; 556 status = "disabled";
557 557
558 gpio0: gpio-controller@0 { 558 porta: gpio-controller@0 {
559 compatible = "snps,dw-apb-gpio-port"; 559 compatible = "snps,dw-apb-gpio-port";
560 gpio-controller; 560 gpio-controller;
561 #gpio-cells = <2>; 561 #gpio-cells = <2>;
@@ -567,7 +567,7 @@
567 }; 567 };
568 }; 568 };
569 569
570 gpio@ff709000 { 570 gpio1: gpio@ff709000 {
571 #address-cells = <1>; 571 #address-cells = <1>;
572 #size-cells = <0>; 572 #size-cells = <0>;
573 compatible = "snps,dw-apb-gpio"; 573 compatible = "snps,dw-apb-gpio";
@@ -575,7 +575,7 @@
575 clocks = <&per_base_clk>; 575 clocks = <&per_base_clk>;
576 status = "disabled"; 576 status = "disabled";
577 577
578 gpio1: gpio-controller@0 { 578 portb: gpio-controller@0 {
579 compatible = "snps,dw-apb-gpio-port"; 579 compatible = "snps,dw-apb-gpio-port";
580 gpio-controller; 580 gpio-controller;
581 #gpio-cells = <2>; 581 #gpio-cells = <2>;
@@ -587,7 +587,7 @@
587 }; 587 };
588 }; 588 };
589 589
590 gpio@ff70a000 { 590 gpio2: gpio@ff70a000 {
591 #address-cells = <1>; 591 #address-cells = <1>;
592 #size-cells = <0>; 592 #size-cells = <0>;
593 compatible = "snps,dw-apb-gpio"; 593 compatible = "snps,dw-apb-gpio";
@@ -595,7 +595,7 @@
595 clocks = <&per_base_clk>; 595 clocks = <&per_base_clk>;
596 status = "disabled"; 596 status = "disabled";
597 597
598 gpio2: gpio-controller@0 { 598 portc: gpio-controller@0 {
599 compatible = "snps,dw-apb-gpio-port"; 599 compatible = "snps,dw-apb-gpio-port";
600 gpio-controller; 600 gpio-controller;
601 #gpio-cells = <2>; 601 #gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 03e8268ae219..1907cc600452 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -29,7 +29,7 @@
29 }; 29 };
30 }; 30 };
31 31
32 dwmmc0@ff704000 { 32 mmc0: dwmmc0@ff704000 {
33 num-slots = <1>; 33 num-slots = <1>;
34 broken-cd; 34 broken-cd;
35 bus-width = <4>; 35 bus-width = <4>;
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index 27d551c384d0..ccaf41742fc3 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -37,6 +37,13 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 regulator_3_3v: 3-3-v-regulator {
42 compatible = "regulator-fixed";
43 regulator-name = "3.3V";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
40}; 47};
41 48
42&gmac1 { 49&gmac1 {
@@ -68,6 +75,11 @@
68 }; 75 };
69}; 76};
70 77
78&mmc0 {
79 vmmc-supply = <&regulator_3_3v>;
80 vqmmc-supply = <&regulator_3_3v>;
81};
82
71&usb1 { 83&usb1 {
72 status = "okay"; 84 status = "okay";
73}; 85};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index d7296a5f750c..258865da8f6a 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -37,6 +37,13 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 regulator_3_3v: 3-3-v-regulator {
42 compatible = "regulator-fixed";
43 regulator-name = "3.3V";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
40}; 47};
41 48
42&gmac1 { 49&gmac1 {
@@ -53,6 +60,10 @@
53 rxc-skew-ps = <2000>; 60 rxc-skew-ps = <2000>;
54}; 61};
55 62
63&gpio1 {
64 status = "okay";
65};
66
56&i2c0 { 67&i2c0 {
57 status = "okay"; 68 status = "okay";
58 69
@@ -69,7 +80,9 @@
69}; 80};
70 81
71&mmc0 { 82&mmc0 {
72 cd-gpios = <&gpio1 18 0>; 83 cd-gpios = <&portb 18 0>;
84 vmmc-supply = <&regulator_3_3v>;
85 vqmmc-supply = <&regulator_3_3v>;
73}; 86};
74 87
75&usb1 { 88&usb1 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index d26f155f5fd9..16ea6f5f2ab8 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -37,6 +37,13 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 regulator_3_3v: vcc3p3-regulator {
42 compatible = "regulator-fixed";
43 regulator-name = "VCC3P3";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
40}; 47};
41 48
42&gmac1 { 49&gmac1 {
@@ -53,6 +60,11 @@
53 rxc-skew-ps = <2000>; 60 rxc-skew-ps = <2000>;
54}; 61};
55 62
63&mmc0 {
64 vmmc-supply = <&regulator_3_3v>;
65 vqmmc-supply = <&regulator_3_3v>;
66};
67
56&usb1 { 68&usb1 {
57 status = "okay"; 69 status = "okay";
58}; 70};
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 24036c440440..ce2ef5bec4f2 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -30,7 +30,6 @@
30 /* kHz uV */ 30 /* kHz uV */
31 666667 1000000 31 666667 1000000
32 333334 1000000 32 333334 1000000
33 222223 1000000
34 >; 33 >;
35 }; 34 };
36 35
@@ -65,7 +64,7 @@
65 interrupt-parent = <&intc>; 64 interrupt-parent = <&intc>;
66 ranges; 65 ranges;
67 66
68 adc@f8007100 { 67 adc: adc@f8007100 {
69 compatible = "xlnx,zynq-xadc-1.00.a"; 68 compatible = "xlnx,zynq-xadc-1.00.a";
70 reg = <0xf8007100 0x20>; 69 reg = <0xf8007100 0x20>;
71 interrupts = <0 7 4>; 70 interrupts = <0 7 4>;
@@ -137,7 +136,7 @@
137 <0xF8F00100 0x100>; 136 <0xF8F00100 0x100>;
138 }; 137 };
139 138
140 L2: cache-controller { 139 L2: cache-controller@f8f02000 {
141 compatible = "arm,pl310-cache"; 140 compatible = "arm,pl310-cache";
142 reg = <0xF8F02000 0x1000>; 141 reg = <0xF8F02000 0x1000>;
143 arm,data-latency = <3 2 2>; 142 arm,data-latency = <3 2 2>;
@@ -146,10 +145,10 @@
146 cache-level = <2>; 145 cache-level = <2>;
147 }; 146 };
148 147
149 memory-controller@f8006000 { 148 mc: memory-controller@f8006000 {
150 compatible = "xlnx,zynq-ddrc-a05"; 149 compatible = "xlnx,zynq-ddrc-a05";
151 reg = <0xf8006000 0x1000>; 150 reg = <0xf8006000 0x1000>;
152 } ; 151 };
153 152
154 uart0: serial@e0000000 { 153 uart0: serial@e0000000 {
155 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 154 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
@@ -195,7 +194,7 @@
195 194
196 gem0: ethernet@e000b000 { 195 gem0: ethernet@e000b000 {
197 compatible = "cdns,gem"; 196 compatible = "cdns,gem";
198 reg = <0xe000b000 0x4000>; 197 reg = <0xe000b000 0x1000>;
199 status = "disabled"; 198 status = "disabled";
200 interrupts = <0 22 4>; 199 interrupts = <0 22 4>;
201 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 200 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
@@ -206,7 +205,7 @@
206 205
207 gem1: ethernet@e000c000 { 206 gem1: ethernet@e000c000 {
208 compatible = "cdns,gem"; 207 compatible = "cdns,gem";
209 reg = <0xe000c000 0x4000>; 208 reg = <0xe000c000 0x1000>;
210 status = "disabled"; 209 status = "disabled";
211 interrupts = <0 45 4>; 210 interrupts = <0 45 4>;
212 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 211 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
@@ -315,5 +314,16 @@
315 reg = <0xf8f00600 0x20>; 314 reg = <0xf8f00600 0x20>;
316 clocks = <&clkc 4>; 315 clocks = <&clkc 4>;
317 }; 316 };
317
318 watchdog0: watchdog@f8005000 {
319 clocks = <&clkc 45>;
320 compatible = "xlnx,zynq-wdt-r1p2";
321 device_type = "watchdog";
322 interrupt-parent = <&intc>;
323 interrupts = <0 9 1>;
324 reg = <0xf8005000 0x1000>;
325 reset = <0>;
326 timeout-sec = <10>;
327 };
318 }; 328 };
319}; 329};
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index fc7d1683bf67..72058b8a6f4d 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -1,6 +1,7 @@
1CONFIG_SYSVIPC=y 1CONFIG_SYSVIPC=y
2CONFIG_NO_HZ=y 2CONFIG_NO_HZ=y
3CONFIG_HIGH_RES_TIMERS=y 3CONFIG_HIGH_RES_TIMERS=y
4CONFIG_CGROUPS=y
4CONFIG_BLK_DEV_INITRD=y 5CONFIG_BLK_DEV_INITRD=y
5CONFIG_KALLSYMS_ALL=y 6CONFIG_KALLSYMS_ALL=y
6CONFIG_MODULES=y 7CONFIG_MODULES=y
@@ -54,12 +55,14 @@ CONFIG_SMSC911X=y
54CONFIG_USB_USBNET=y 55CONFIG_USB_USBNET=y
55CONFIG_USB_NET_SMSC75XX=y 56CONFIG_USB_NET_SMSC75XX=y
56CONFIG_USB_NET_SMSC95XX=y 57CONFIG_USB_NET_SMSC95XX=y
58CONFIG_USB_GADGET=y
57CONFIG_INPUT_EVDEV=y 59CONFIG_INPUT_EVDEV=y
58CONFIG_KEYBOARD_GPIO=y 60CONFIG_KEYBOARD_GPIO=y
59CONFIG_KEYBOARD_CROS_EC=y 61CONFIG_KEYBOARD_CROS_EC=y
60# CONFIG_MOUSE_PS2 is not set 62# CONFIG_MOUSE_PS2 is not set
61CONFIG_MOUSE_CYAPA=y 63CONFIG_MOUSE_CYAPA=y
62CONFIG_INPUT_TOUCHSCREEN=y 64CONFIG_INPUT_TOUCHSCREEN=y
65CONFIG_TOUCHSCREEN_ATMEL_MXT=y
63CONFIG_SERIAL_8250=y 66CONFIG_SERIAL_8250=y
64CONFIG_SERIAL_SAMSUNG=y 67CONFIG_SERIAL_SAMSUNG=y
65CONFIG_SERIAL_SAMSUNG_CONSOLE=y 68CONFIG_SERIAL_SAMSUNG_CONSOLE=y
@@ -68,15 +71,18 @@ CONFIG_HW_RANDOM=y
68CONFIG_TCG_TPM=y 71CONFIG_TCG_TPM=y
69CONFIG_TCG_TIS_I2C_INFINEON=y 72CONFIG_TCG_TIS_I2C_INFINEON=y
70CONFIG_I2C=y 73CONFIG_I2C=y
74CONFIG_I2C_CHARDEV=y
71CONFIG_I2C_MUX=y 75CONFIG_I2C_MUX=y
72CONFIG_I2C_ARB_GPIO_CHALLENGE=y 76CONFIG_I2C_ARB_GPIO_CHALLENGE=y
73CONFIG_I2C_EXYNOS5=y 77CONFIG_I2C_EXYNOS5=y
78CONFIG_I2C_GPIO=y
74CONFIG_I2C_CROS_EC_TUNNEL=y 79CONFIG_I2C_CROS_EC_TUNNEL=y
75CONFIG_SPI=y 80CONFIG_SPI=y
76CONFIG_SPI_S3C64XX=y 81CONFIG_SPI_S3C64XX=y
77CONFIG_I2C_S3C2410=y 82CONFIG_I2C_S3C2410=y
78CONFIG_DEBUG_GPIO=y 83CONFIG_DEBUG_GPIO=y
79CONFIG_POWER_SUPPLY=y 84CONFIG_POWER_SUPPLY=y
85CONFIG_BATTERY_SBS=y
80CONFIG_CHARGER_TPS65090=y 86CONFIG_CHARGER_TPS65090=y
81# CONFIG_HWMON is not set 87# CONFIG_HWMON is not set
82CONFIG_THERMAL=y 88CONFIG_THERMAL=y
@@ -88,6 +94,7 @@ CONFIG_MFD_CROS_EC=y
88CONFIG_MFD_CROS_EC_I2C=y 94CONFIG_MFD_CROS_EC_I2C=y
89CONFIG_MFD_CROS_EC_SPI=y 95CONFIG_MFD_CROS_EC_SPI=y
90CONFIG_MFD_MAX77686=y 96CONFIG_MFD_MAX77686=y
97CONFIG_MFD_MAX77693=y
91CONFIG_MFD_MAX8997=y 98CONFIG_MFD_MAX8997=y
92CONFIG_MFD_SEC_CORE=y 99CONFIG_MFD_SEC_CORE=y
93CONFIG_MFD_TPS65090=y 100CONFIG_MFD_TPS65090=y
@@ -96,6 +103,8 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
96CONFIG_REGULATOR_GPIO=y 103CONFIG_REGULATOR_GPIO=y
97CONFIG_REGULATOR_MAX8997=y 104CONFIG_REGULATOR_MAX8997=y
98CONFIG_REGULATOR_MAX77686=y 105CONFIG_REGULATOR_MAX77686=y
106CONFIG_REGULATOR_MAX77802=y
107CONFIG_REGULATOR_MAX77693=y
99CONFIG_REGULATOR_S2MPA01=y 108CONFIG_REGULATOR_S2MPA01=y
100CONFIG_REGULATOR_S2MPS11=y 109CONFIG_REGULATOR_S2MPS11=y
101CONFIG_REGULATOR_S5M8767=y 110CONFIG_REGULATOR_S5M8767=y
@@ -115,6 +124,7 @@ CONFIG_SND_SOC=y
115CONFIG_SND_SOC_SAMSUNG=y 124CONFIG_SND_SOC_SAMSUNG=y
116CONFIG_SND_SOC_SNOW=y 125CONFIG_SND_SOC_SNOW=y
117CONFIG_USB=y 126CONFIG_USB=y
127CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
118CONFIG_USB_XHCI_HCD=y 128CONFIG_USB_XHCI_HCD=y
119CONFIG_USB_EHCI_HCD=y 129CONFIG_USB_EHCI_HCD=y
120CONFIG_USB_EHCI_EXYNOS=y 130CONFIG_USB_EHCI_EXYNOS=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 491b7d5523bf..f1dc7fc668f3 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -261,6 +261,7 @@ CONFIG_WATCHDOG=y
261CONFIG_XILINX_WATCHDOG=y 261CONFIG_XILINX_WATCHDOG=y
262CONFIG_ORION_WATCHDOG=y 262CONFIG_ORION_WATCHDOG=y
263CONFIG_SUNXI_WATCHDOG=y 263CONFIG_SUNXI_WATCHDOG=y
264CONFIG_MESON_WATCHDOG=y
264CONFIG_MFD_AS3722=y 265CONFIG_MFD_AS3722=y
265CONFIG_MFD_BCM590XX=y 266CONFIG_MFD_BCM590XX=y
266CONFIG_MFD_CROS_EC=y 267CONFIG_MFD_CROS_EC=y
@@ -353,6 +354,7 @@ CONFIG_MMC_MVSDIO=y
353CONFIG_MMC_SUNXI=y 354CONFIG_MMC_SUNXI=y
354CONFIG_MMC_DW=y 355CONFIG_MMC_DW=y
355CONFIG_MMC_DW_EXYNOS=y 356CONFIG_MMC_DW_EXYNOS=y
357CONFIG_MMC_DW_ROCKCHIP=y
356CONFIG_NEW_LEDS=y 358CONFIG_NEW_LEDS=y
357CONFIG_LEDS_CLASS=y 359CONFIG_LEDS_CLASS=y
358CONFIG_LEDS_GPIO=y 360CONFIG_LEDS_GPIO=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 69c7bed3c634..16e719c268dd 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -51,6 +51,7 @@ CONFIG_SOC_AM43XX=y
51CONFIG_SOC_DRA7XX=y 51CONFIG_SOC_DRA7XX=y
52CONFIG_ARM_THUMBEE=y 52CONFIG_ARM_THUMBEE=y
53CONFIG_ARM_ERRATA_411920=y 53CONFIG_ARM_ERRATA_411920=y
54CONFIG_ARM_ERRATA_430973=y
54CONFIG_SMP=y 55CONFIG_SMP=y
55CONFIG_NR_CPUS=2 56CONFIG_NR_CPUS=2
56CONFIG_CMA=y 57CONFIG_CMA=y
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index c1a4ca4f6e6d..f7ac0379850f 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -75,6 +75,8 @@ CONFIG_POWER_RESET_SUN6I=y
75CONFIG_WATCHDOG=y 75CONFIG_WATCHDOG=y
76CONFIG_SUNXI_WATCHDOG=y 76CONFIG_SUNXI_WATCHDOG=y
77CONFIG_MFD_AXP20X=y 77CONFIG_MFD_AXP20X=y
78CONFIG_REGULATOR=y
79CONFIG_REGULATOR_FIXED_VOLTAGE=y
78CONFIG_REGULATOR_GPIO=y 80CONFIG_REGULATOR_GPIO=y
79CONFIG_USB=y 81CONFIG_USB=y
80CONFIG_USB_EHCI_HCD=y 82CONFIG_USB_EHCI_HCD=y
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 713e807621d2..2d2d6087b9b1 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -10,6 +10,7 @@
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13#include <linux/compiler.h>
13#include <linux/sched.h> 14#include <linux/sched.h>
14#include <linux/mm.h> 15#include <linux/mm.h>
15#include <linux/dma-mapping.h> 16#include <linux/dma-mapping.h>
@@ -39,10 +40,19 @@
39 * GCC 3.2.x: miscompiles NEW_AUX_ENT in fs/binfmt_elf.c 40 * GCC 3.2.x: miscompiles NEW_AUX_ENT in fs/binfmt_elf.c
40 * (http://gcc.gnu.org/PR8896) and incorrect structure 41 * (http://gcc.gnu.org/PR8896) and incorrect structure
41 * initialisation in fs/jffs2/erase.c 42 * initialisation in fs/jffs2/erase.c
43 * GCC 4.8.0-4.8.2: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58854
44 * miscompiles find_get_entry(), and can result in EXT3 and EXT4
45 * filesystem corruption (possibly other FS too).
42 */ 46 */
47#ifdef __GNUC__
43#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3) 48#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
44#error Your compiler is too buggy; it is known to miscompile kernels. 49#error Your compiler is too buggy; it is known to miscompile kernels.
45#error Known good compilers: 3.3 50#error Known good compilers: 3.3, 4.x
51#endif
52#if GCC_VERSION >= 40800 && GCC_VERSION < 40803
53#error Your compiler is too buggy; it is known to miscompile kernels
54#error and result in filesystem corruption and oopses.
55#endif
46#endif 56#endif
47 57
48int main(void) 58int main(void)
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 5e772a21ab97..ef9119f7462e 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -949,8 +949,8 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
949 if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) 949 if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
950 trace_sys_enter(regs, scno); 950 trace_sys_enter(regs, scno);
951 951
952 audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0, regs->ARM_r1, 952 audit_syscall_entry(scno, regs->ARM_r0, regs->ARM_r1, regs->ARM_r2,
953 regs->ARM_r2, regs->ARM_r3); 953 regs->ARM_r3);
954 954
955 return scno; 955 return scno;
956} 956}
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index b89e5f35db84..6b283eb3202e 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -161,7 +161,9 @@ static void exynos_restart(enum reboot_mode mode, const char *cmd)
161 161
162static struct platform_device exynos_cpuidle = { 162static struct platform_device exynos_cpuidle = {
163 .name = "exynos_cpuidle", 163 .name = "exynos_cpuidle",
164#ifdef CONFIG_ARM_EXYNOS_CPUIDLE
164 .dev.platform_data = exynos_enter_aftr, 165 .dev.platform_data = exynos_enter_aftr,
166#endif
165 .id = -1, 167 .id = -1,
166}; 168};
167 169
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 8c35ae4ff176..07a09570175d 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -20,7 +20,7 @@
20#include <linux/input.h> 20#include <linux/input.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/irqchip.h> 22#include <linux/irqchip.h>
23#include <linux/mailbox.h> 23#include <linux/pl320-ipc.h>
24#include <linux/of.h> 24#include <linux/of.h>
25#include <linux/of_irq.h> 25#include <linux/of_irq.h>
26#include <linux/of_platform.h> 26#include <linux/of_platform.h>
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 1412daf4a714..4e79da7c5e30 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -50,8 +50,8 @@ static const char *pcie_axi_sels[] = { "axi", "ahb", };
50static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; 50static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", };
51static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; 51static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
52static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; 52static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
53static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; 53static const char *eim_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
54static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 54static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
55static const char *vdo_axi_sels[] = { "axi", "ahb", }; 55static const char *vdo_axi_sels[] = { "axi", "ahb", };
56static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 56static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
57static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", 57static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
@@ -302,8 +302,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
302 clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 302 clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
303 clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 303 clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
304 clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); 304 clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
305 clk[IMX6QDL_CLK_EMI_SEL] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup); 305 clk[IMX6QDL_CLK_EIM_SEL] = imx_clk_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup);
306 clk[IMX6QDL_CLK_EMI_SLOW_SEL] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup); 306 clk[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup);
307 clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); 307 clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
308 clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); 308 clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
309 clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); 309 clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
@@ -354,8 +354,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
354 clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); 354 clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
355 clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); 355 clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
356 clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); 356 clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
357 clk[IMX6QDL_CLK_EMI_PODF] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); 357 clk[IMX6QDL_CLK_EIM_PODF] = imx_clk_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
358 clk[IMX6QDL_CLK_EMI_SLOW_PODF] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); 358 clk[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
359 clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); 359 clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
360 clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); 360 clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
361 clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); 361 clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
@@ -456,7 +456,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
456 clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); 456 clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
457 clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); 457 clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
458 clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); 458 clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
459 clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10); 459 clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10);
460 clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); 460 clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
461 clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); 461 clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
462 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); 462 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 572b8f719ffb..60c443dadb58 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -40,7 +40,7 @@ extern void __iomem *rst_manager_base_addr;
40extern struct smp_operations socfpga_smp_ops; 40extern struct smp_operations socfpga_smp_ops;
41extern char secondary_trampoline, secondary_trampoline_end; 41extern char secondary_trampoline, secondary_trampoline_end;
42 42
43extern unsigned long cpu1start_addr; 43extern unsigned long socfpga_cpu1start_addr;
44 44
45#define SOCFPGA_SCU_VIRT_BASE 0xfffec000 45#define SOCFPGA_SCU_VIRT_BASE 0xfffec000
46 46
diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index 95c115d8b5ee..f65ea0af4af3 100644
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -9,21 +9,26 @@
9 */ 9 */
10#include <linux/linkage.h> 10#include <linux/linkage.h>
11#include <linux/init.h> 11#include <linux/init.h>
12#include <asm/memory.h>
12 13
13 .arch armv7-a 14 .arch armv7-a
14 15
15ENTRY(secondary_trampoline) 16ENTRY(secondary_trampoline)
16 movw r2, #:lower16:cpu1start_addr 17 /* CPU1 will always fetch from 0x0 when it is brought out of reset.
17 movt r2, #:upper16:cpu1start_addr 18 * Thus, we can just subtract the PAGE_OFFSET to get the physical
18 19 * address of &cpu1start_addr. This would not work for platforms
19 /* The socfpga VT cannot handle a 0xC0000000 page offset when loading 20 * where the physical memory does not start at 0x0.
20 the cpu1start_addr, we bit clear it. Tested on HW and VT. */ 21 */
21 bic r2, r2, #0x40000000 22 adr r0, 1f
22 23 ldmia r0, {r1, r2}
23 ldr r0, [r2] 24 sub r2, r2, #PAGE_OFFSET
24 ldr r1, [r0] 25 ldr r3, [r2]
25 bx r1 26 ldr r4, [r3]
27 bx r4
26 28
29 .align
301: .long .
31 .long socfpga_cpu1start_addr
27ENTRY(secondary_trampoline_end) 32ENTRY(secondary_trampoline_end)
28 33
29ENTRY(socfpga_secondary_startup) 34ENTRY(socfpga_secondary_startup)
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 5356a72bc8ce..16ca97b039f9 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -33,11 +33,11 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
33{ 33{
34 int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; 34 int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
35 35
36 if (cpu1start_addr) { 36 if (socfpga_cpu1start_addr) {
37 memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); 37 memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
38 38
39 __raw_writel(virt_to_phys(socfpga_secondary_startup), 39 __raw_writel(virt_to_phys(socfpga_secondary_startup),
40 (sys_manager_base_addr + (cpu1start_addr & 0x000000ff))); 40 (sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff)));
41 41
42 flush_cache_all(); 42 flush_cache_all();
43 smp_wmb(); 43 smp_wmb();
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index adbf38314ca8..383d61e138af 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -29,7 +29,7 @@
29void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE)); 29void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
30void __iomem *sys_manager_base_addr; 30void __iomem *sys_manager_base_addr;
31void __iomem *rst_manager_base_addr; 31void __iomem *rst_manager_base_addr;
32unsigned long cpu1start_addr; 32unsigned long socfpga_cpu1start_addr;
33 33
34static struct map_desc scu_io_desc __initdata = { 34static struct map_desc scu_io_desc __initdata = {
35 .virtual = SOCFPGA_SCU_VIRT_BASE, 35 .virtual = SOCFPGA_SCU_VIRT_BASE,
@@ -70,7 +70,7 @@ void __init socfpga_sysmgr_init(void)
70 np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr"); 70 np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
71 71
72 if (of_property_read_u32(np, "cpu1-start-addr", 72 if (of_property_read_u32(np, "cpu1-start-addr",
73 (u32 *) &cpu1start_addr)) 73 (u32 *) &socfpga_cpu1start_addr))
74 pr_err("SMP: Need cpu1-start-addr in device tree.\n"); 74 pr_err("SMP: Need cpu1-start-addr in device tree.\n");
75 75
76 sys_manager_base_addr = of_iomap(np, 0); 76 sys_manager_base_addr = of_iomap(np, 0);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 92bba32d9230..9481f85c56e6 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -559,10 +559,10 @@ void __init mem_init(void)
559#ifdef CONFIG_MODULES 559#ifdef CONFIG_MODULES
560 " modules : 0x%08lx - 0x%08lx (%4ld MB)\n" 560 " modules : 0x%08lx - 0x%08lx (%4ld MB)\n"
561#endif 561#endif
562 " .text : 0x%p" " - 0x%p" " (%4d kB)\n" 562 " .text : 0x%p" " - 0x%p" " (%4td kB)\n"
563 " .init : 0x%p" " - 0x%p" " (%4d kB)\n" 563 " .init : 0x%p" " - 0x%p" " (%4td kB)\n"
564 " .data : 0x%p" " - 0x%p" " (%4d kB)\n" 564 " .data : 0x%p" " - 0x%p" " (%4td kB)\n"
565 " .bss : 0x%p" " - 0x%p" " (%4d kB)\n", 565 " .bss : 0x%p" " - 0x%p" " (%4td kB)\n",
566 566
567 MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) + 567 MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) +
568 (PAGE_SIZE)), 568 (PAGE_SIZE)),
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index ee1d80593958..ba1196c968d8 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -279,7 +279,7 @@ ENTRY(\name\()_processor_functions)
279 279
280 .if \suspend 280 .if \suspend
281 .word cpu_\name\()_suspend_size 281 .word cpu_\name\()_suspend_size
282#ifdef CONFIG_PM_SLEEP 282#ifdef CONFIG_ARM_CPU_SUSPEND
283 .word cpu_\name\()_do_suspend 283 .word cpu_\name\()_do_suspend
284 .word cpu_\name\()_do_resume 284 .word cpu_\name\()_do_resume
285#else 285#else
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index c87aefbf3a13..9bd2776e7d05 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -268,8 +268,9 @@ config S5P_DEV_MFC
268comment "Power management" 268comment "Power management"
269 269
270config SAMSUNG_PM_DEBUG 270config SAMSUNG_PM_DEBUG
271 bool "S3C2410 PM Suspend debug" 271 bool "Samsung PM Suspend debug"
272 depends on PM && DEBUG_KERNEL && DEBUG_S3C_UART 272 depends on PM && DEBUG_KERNEL
273 depends on DEBUG_EXYNOS_UART || DEBUG_S3C24XX_UART || DEBUG_S3C2410_UART
273 help 274 help
274 Say Y here if you want verbose debugging from the PM Suspend and 275 Say Y here if you want verbose debugging from the PM Suspend and
275 Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> 276 Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
diff --git a/arch/arm/plat-samsung/pm-debug.c b/arch/arm/plat-samsung/pm-debug.c
index 8f19f66388dd..39609601f407 100644
--- a/arch/arm/plat-samsung/pm-debug.c
+++ b/arch/arm/plat-samsung/pm-debug.c
@@ -14,6 +14,7 @@
14 */ 14 */
15 15
16#include <linux/serial_core.h> 16#include <linux/serial_core.h>
17#include <linux/serial_s3c.h>
17#include <linux/io.h> 18#include <linux/io.h>
18 19
19#include <asm/mach/map.h> 20#include <asm/mach/map.h>
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 11:37:35 -0500