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-rw-r--r--arch/arm/Kconfig4
-rw-r--r--arch/arm/boot/dts/spear300-evb.dts38
-rw-r--r--arch/arm/boot/dts/spear300.dtsi5
-rw-r--r--arch/arm/boot/dts/spear310-evb.dts61
-rw-r--r--arch/arm/boot/dts/spear310.dtsi5
-rw-r--r--arch/arm/boot/dts/spear320-evb.dts61
-rw-r--r--arch/arm/boot/dts/spear320.dtsi7
-rw-r--r--arch/arm/boot/dts/tegra-cardhu.dts44
-rw-r--r--arch/arm/boot/dts/tegra-harmony.dts224
-rw-r--r--arch/arm/boot/dts/tegra-paz00.dts220
-rw-r--r--arch/arm/boot/dts/tegra-seaboard.dts243
-rw-r--r--arch/arm/boot/dts/tegra-trimslice.dts230
-rw-r--r--arch/arm/boot/dts/tegra-ventana.dts230
-rw-r--r--arch/arm/configs/nhk8815_defconfig1
-rw-r--r--arch/arm/mach-imx/Kconfig2
-rw-r--r--arch/arm/mach-imx/imx51-dt.c3
-rw-r--r--arch/arm/mach-imx/imx53-dt.c3
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c7
-rw-r--r--arch/arm/mach-imx/mm-imx1.c2
-rw-r--r--arch/arm/mach-imx/mm-imx21.c2
-rw-r--r--arch/arm/mach-imx/mm-imx25.c2
-rw-r--r--arch/arm/mach-imx/mm-imx27.c2
-rw-r--r--arch/arm/mach-imx/mm-imx3.c2
-rw-r--r--arch/arm/mach-imx/mm-imx5.c2
-rw-r--r--arch/arm/mach-mxs/Kconfig2
-rw-r--r--arch/arm/mach-mxs/include/mach/common.h2
-rw-r--r--arch/arm/mach-mxs/mach-apx4devkit.c2
-rw-r--r--arch/arm/mach-mxs/mach-m28evk.c2
-rw-r--r--arch/arm/mach-mxs/mach-mx23evk.c2
-rw-r--r--arch/arm/mach-mxs/mach-mx28evk.c2
-rw-r--r--arch/arm/mach-mxs/mach-stmp378x_devb.c2
-rw-r--r--arch/arm/mach-mxs/mach-tx28.c2
-rw-r--r--arch/arm/mach-mxs/mm.c11
-rw-r--r--arch/arm/mach-nomadik/Kconfig1
-rw-r--r--arch/arm/mach-spear3xx/Kconfig3
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h128
-rw-r--r--arch/arm/mach-spear3xx/spear300.c389
-rw-r--r--arch/arm/mach-spear3xx/spear310.c161
-rw-r--r--arch/arm/mach-spear3xx/spear320.c403
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c425
-rw-r--r--arch/arm/mach-tegra/Makefile3
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra20.c31
-rw-r--r--arch/arm/mach-tegra/board-harmony-pinmux.c266
-rw-r--r--arch/arm/mach-tegra/board-paz00-pinmux.c263
-rw-r--r--arch/arm/mach-tegra/board-pinmux.c105
-rw-r--r--arch/arm/mach-tegra/board-pinmux.h40
-rw-r--r--arch/arm/mach-tegra/board-seaboard-pinmux.c346
-rw-r--r--arch/arm/mach-tegra/board-seaboard.c21
-rw-r--r--arch/arm/mach-tegra/board-trimslice-pinmux.c264
-rw-r--r--arch/arm/mach-tegra/board-trimslice.c15
-rw-r--r--arch/arm/mach-tegra/devices.c5
-rw-r--r--arch/arm/mach-tegra/include/mach/gpio-tegra.h9
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux-tegra20.h184
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux-tegra30.h320
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux.h302
-rw-r--r--arch/arm/mach-tegra/pinmux-tegra20-tables.c244
-rw-r--r--arch/arm/mach-tegra/pinmux-tegra30-tables.c376
-rw-r--r--arch/arm/mach-tegra/pinmux.c987
-rw-r--r--arch/arm/mach-tegra/usb_phy.c1
-rw-r--r--arch/arm/mach-ux500/Kconfig3
-rw-r--r--arch/arm/mach-ux500/Makefile3
-rw-r--r--arch/arm/mach-ux500/board-mop500-msp.c267
-rw-r--r--arch/arm/mach-ux500/board-mop500-msp.h14
-rw-r--r--arch/arm/mach-ux500/board-mop500-pins.c733
-rw-r--r--arch/arm/mach-ux500/board-mop500.c99
-rw-r--r--arch/arm/mach-ux500/board-mop500.h10
-rw-r--r--arch/arm/mach-ux500/clock.c8
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c1
-rw-r--r--arch/arm/mach-ux500/cpu.c12
-rw-r--r--arch/arm/mach-ux500/devices-common.h12
-rw-r--r--arch/arm/mach-ux500/devices-db8500.h10
-rw-r--r--arch/arm/mach-ux500/include/mach/msp.h29
-rw-r--r--arch/arm/mach-ux500/pins-db8500.h72
-rw-r--r--arch/arm/plat-nomadik/include/plat/gpio-nomadik.h8
-rw-r--r--arch/arm/plat-nomadik/include/plat/pincfg.h32
-rw-r--r--arch/arm/plat-spear/Kconfig1
-rw-r--r--arch/arm/plat-spear/Makefile2
-rw-r--r--arch/arm/plat-spear/include/plat/padmux.h92
-rw-r--r--arch/arm/plat-spear/padmux.c164
79 files changed, 3020 insertions, 5271 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 82936f63cf16..58e2f7865f54 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -403,6 +403,8 @@ config ARCH_PRIMA2
403 select CLKDEV_LOOKUP 403 select CLKDEV_LOOKUP
404 select GENERIC_IRQ_CHIP 404 select GENERIC_IRQ_CHIP
405 select MIGHT_HAVE_CACHE_L2X0 405 select MIGHT_HAVE_CACHE_L2X0
406 select PINCTRL
407 select PINCTRL_SIRF
406 select USE_OF 408 select USE_OF
407 select ZONE_DMA 409 select ZONE_DMA
408 help 410 help
@@ -465,6 +467,7 @@ config ARCH_MXS
465 select CLKDEV_LOOKUP 467 select CLKDEV_LOOKUP
466 select CLKSRC_MMIO 468 select CLKSRC_MMIO
467 select HAVE_CLK_PREPARE 469 select HAVE_CLK_PREPARE
470 select PINCTRL
468 help 471 help
469 Support for Freescale MXS-based family of processors 472 Support for Freescale MXS-based family of processors
470 473
@@ -919,6 +922,7 @@ config ARCH_NOMADIK
919 select CPU_ARM926T 922 select CPU_ARM926T
920 select CLKDEV_LOOKUP 923 select CLKDEV_LOOKUP
921 select GENERIC_CLOCKEVENTS 924 select GENERIC_CLOCKEVENTS
925 select PINCTRL
922 select MIGHT_HAVE_CACHE_L2X0 926 select MIGHT_HAVE_CACHE_L2X0
923 select ARCH_REQUIRE_GPIOLIB 927 select ARCH_REQUIRE_GPIOLIB
924 help 928 help
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
index 6a79d69775b5..910e264b87c0 100644
--- a/arch/arm/boot/dts/spear300-evb.dts
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -25,6 +25,44 @@
25 }; 25 };
26 26
27 ahb { 27 ahb {
28 pinmux@99000000 {
29 st,pinmux-mode = <2>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 ssp0 {
39 st,pins = "ssp0_grp";
40 st,function = "ssp0";
41 };
42 mii0 {
43 st,pins = "mii0_grp";
44 st,function = "mii0";
45 };
46 uart0 {
47 st,pins = "uart0_grp";
48 st,function = "uart0";
49 };
50 clcd {
51 st,pins = "clcd_pfmode_grp";
52 st,function = "clcd";
53 };
54 sdhci {
55 st,pins = "sdhci_4bit_grp";
56 st,function = "sdhci";
57 };
58 gpio1 {
59 st,pins = "gpio1_4_to_7_grp",
60 "gpio1_0_to_3_grp";
61 st,function = "gpio1";
62 };
63 };
64 };
65
28 clcd@60000000 { 66 clcd@60000000 {
29 status = "okay"; 67 status = "okay";
30 }; 68 };
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
index f9fcbf4f477b..01c5e358fdb2 100644
--- a/arch/arm/boot/dts/spear300.dtsi
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -21,6 +21,11 @@
21 ranges = <0x60000000 0x60000000 0x50000000 21 ranges = <0x60000000 0x60000000 0x50000000
22 0xd0000000 0xd0000000 0x30000000>; 22 0xd0000000 0xd0000000 0x30000000>;
23 23
24 pinmux@99000000 {
25 compatible = "st,spear300-pinmux";
26 reg = <0x99000000 0x1000>;
27 };
28
24 clcd@60000000 { 29 clcd@60000000 {
25 compatible = "arm,clcd-pl110", "arm,primecell"; 30 compatible = "arm,clcd-pl110", "arm,primecell";
26 reg = <0x60000000 0x1000>; 31 reg = <0x60000000 0x1000>;
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
index c86af33f700e..6d95317100ad 100644
--- a/arch/arm/boot/dts/spear310-evb.dts
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -25,6 +25,67 @@
25 }; 25 };
26 26
27 ahb { 27 ahb {
28 pinmux@b4000000 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&state_default>;
31
32 state_default: pinmux {
33 gpio0 {
34 st,pins = "gpio0_pin0_grp",
35 "gpio0_pin1_grp",
36 "gpio0_pin2_grp",
37 "gpio0_pin3_grp",
38 "gpio0_pin4_grp",
39 "gpio0_pin5_grp";
40 st,function = "gpio0";
41 };
42 i2c0 {
43 st,pins = "i2c0_grp";
44 st,function = "i2c0";
45 };
46 mii0 {
47 st,pins = "mii0_grp";
48 st,function = "mii0";
49 };
50 ssp0 {
51 st,pins = "ssp0_grp";
52 st,function = "ssp0";
53 };
54 uart0 {
55 st,pins = "uart0_grp";
56 st,function = "uart0";
57 };
58 emi {
59 st,pins = "emi_cs_0_to_5_grp";
60 st,function = "emi";
61 };
62 fsmc {
63 st,pins = "fsmc_grp";
64 st,function = "fsmc";
65 };
66 uart1 {
67 st,pins = "uart1_grp";
68 st,function = "uart1";
69 };
70 uart2 {
71 st,pins = "uart2_grp";
72 st,function = "uart2";
73 };
74 uart3 {
75 st,pins = "uart3_grp";
76 st,function = "uart3";
77 };
78 uart4 {
79 st,pins = "uart4_grp";
80 st,function = "uart4";
81 };
82 uart5 {
83 st,pins = "uart5_grp";
84 st,function = "uart5";
85 };
86 };
87 };
88
28 dma@fc400000 { 89 dma@fc400000 {
29 status = "okay"; 90 status = "okay";
30 }; 91 };
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
index dc7fa14da846..e47081c494d9 100644
--- a/arch/arm/boot/dts/spear310.dtsi
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -22,6 +22,11 @@
22 0xb0000000 0xb0000000 0x10000000 22 0xb0000000 0xb0000000 0x10000000
23 0xd0000000 0xd0000000 0x30000000>; 23 0xd0000000 0xd0000000 0x30000000>;
24 24
25 pinmux@b4000000 {
26 compatible = "st,spear310-pinmux";
27 reg = <0xb4000000 0x1000>;
28 };
29
25 fsmc: flash@44000000 { 30 fsmc: flash@44000000 {
26 compatible = "st,spear600-fsmc-nand"; 31 compatible = "st,spear600-fsmc-nand";
27 #address-cells = <1>; 32 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index d43de712e863..0c6463b71a37 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -25,6 +25,67 @@
25 }; 25 };
26 26
27 ahb { 27 ahb {
28 pinmux@b3000000 {
29 st,pinmux-mode = <3>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 mii0 {
39 st,pins = "mii0_grp";
40 st,function = "mii0";
41 };
42 ssp0 {
43 st,pins = "ssp0_grp";
44 st,function = "ssp0";
45 };
46 uart0 {
47 st,pins = "uart0_grp";
48 st,function = "uart0";
49 };
50 sdhci {
51 st,pins = "sdhci_cd_51_grp";
52 st,function = "sdhci";
53 };
54 i2s {
55 st,pins = "i2s_grp";
56 st,function = "i2s";
57 };
58 uart1 {
59 st,pins = "uart1_grp";
60 st,function = "uart1";
61 };
62 uart2 {
63 st,pins = "uart2_grp";
64 st,function = "uart2";
65 };
66 can0 {
67 st,pins = "can0_grp";
68 st,function = "can0";
69 };
70 can1 {
71 st,pins = "can1_grp";
72 st,function = "can1";
73 };
74 mii2 {
75 st,pins = "mii2_grp";
76 st,function = "mii2";
77 };
78 pwm0_1 {
79 st,pins = "pwm0_1_pin_14_15_grp";
80 st,function = "pwm0_1";
81 };
82 pwm2 {
83 st,pins = "pwm2_pin_13_grp";
84 st,function = "pwm2";
85 };
86 };
87 };
88
28 clcd@90000000 { 89 clcd@90000000 {
29 status = "okay"; 90 status = "okay";
30 }; 91 };
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index 9a0267a5a0b7..5372ca399b1f 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -18,9 +18,14 @@
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 compatible = "simple-bus"; 20 compatible = "simple-bus";
21 ranges = <0x40000000 0x40000000 0x70000000 21 ranges = <0x40000000 0x40000000 0x80000000
22 0xd0000000 0xd0000000 0x30000000>; 22 0xd0000000 0xd0000000 0x30000000>;
23 23
24 pinmux@b3000000 {
25 compatible = "st,spear320-pinmux";
26 reg = <0xb3000000 0x1000>;
27 };
28
24 clcd@90000000 { 29 clcd@90000000 {
25 compatible = "arm,clcd-pl110", "arm,primecell"; 30 compatible = "arm,clcd-pl110", "arm,primecell";
26 reg = <0x90000000 0x1000>; 31 reg = <0x90000000 0x1000>;
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index ac3fb7558459..0a9f34a2c3aa 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -10,6 +10,50 @@
10 reg = < 0x80000000 0x40000000 >; 10 reg = < 0x80000000 0x40000000 >;
11 }; 11 };
12 12
13 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 sdmmc1_clk_pz0 {
19 nvidia,pins = "sdmmc1_clk_pz0";
20 nvidia,function = "sdmmc1";
21 nvidia,pull = <0>;
22 nvidia,tristate = <0>;
23 };
24 sdmmc1_cmd_pz1 {
25 nvidia,pins = "sdmmc1_cmd_pz1",
26 "sdmmc1_dat0_py7",
27 "sdmmc1_dat1_py6",
28 "sdmmc1_dat2_py5",
29 "sdmmc1_dat3_py4";
30 nvidia,function = "sdmmc1";
31 nvidia,pull = <2>;
32 nvidia,tristate = <0>;
33 };
34 sdmmc4_clk_pcc4 {
35 nvidia,pins = "sdmmc4_clk_pcc4",
36 "sdmmc4_rst_n_pcc3";
37 nvidia,function = "sdmmc4";
38 nvidia,pull = <0>;
39 nvidia,tristate = <0>;
40 };
41 sdmmc4_dat0_paa0 {
42 nvidia,pins = "sdmmc4_dat0_paa0",
43 "sdmmc4_dat1_paa1",
44 "sdmmc4_dat2_paa2",
45 "sdmmc4_dat3_paa3",
46 "sdmmc4_dat4_paa4",
47 "sdmmc4_dat5_paa5",
48 "sdmmc4_dat6_paa6",
49 "sdmmc4_dat7_paa7";
50 nvidia,function = "sdmmc4";
51 nvidia,pull = <2>;
52 nvidia,tristate = <0>;
53 };
54 };
55 };
56
13 serial@70006000 { 57 serial@70006000 {
14 clock-frequency = < 408000000 >; 58 clock-frequency = < 408000000 >;
15 }; 59 };
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 6e8447dc0202..1a0b1f182944 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -10,6 +10,230 @@
10 reg = < 0x00000000 0x40000000 >; 10 reg = < 0x00000000 0x40000000 >;
11 }; 11 };
12 12
13 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
32 "spia", "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
67 ddc {
68 nvidia,pins = "ddc";
69 nvidia,function = "i2c2";
70 };
71 dta {
72 nvidia,pins = "dta", "dtd";
73 nvidia,function = "sdio2";
74 };
75 dtb {
76 nvidia,pins = "dtb", "dtc", "dte";
77 nvidia,function = "rsvd1";
78 };
79 dtf {
80 nvidia,pins = "dtf";
81 nvidia,function = "i2c3";
82 };
83 gmc {
84 nvidia,pins = "gmc";
85 nvidia,function = "uartd";
86 };
87 gpu7 {
88 nvidia,pins = "gpu7";
89 nvidia,function = "rtck";
90 };
91 gpv {
92 nvidia,pins = "gpv", "slxa", "slxk";
93 nvidia,function = "pcie";
94 };
95 hdint {
96 nvidia,pins = "hdint", "pta";
97 nvidia,function = "hdmi";
98 };
99 i2cp {
100 nvidia,pins = "i2cp";
101 nvidia,function = "i2cp";
102 };
103 irrx {
104 nvidia,pins = "irrx", "irtx";
105 nvidia,function = "uarta";
106 };
107 kbca {
108 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
109 "kbce", "kbcf";
110 nvidia,function = "kbc";
111 };
112 lcsn {
113 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
114 "ld3", "ld4", "ld5", "ld6", "ld7",
115 "ld8", "ld9", "ld10", "ld11", "ld12",
116 "ld13", "ld14", "ld15", "ld16", "ld17",
117 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
118 "lhs", "lm0", "lm1", "lpp", "lpw0",
119 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
120 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
121 "lvs";
122 nvidia,function = "displaya";
123 };
124 owc {
125 nvidia,pins = "owc", "spdi", "spdo", "uac";
126 nvidia,function = "rsvd2";
127 };
128 pmc {
129 nvidia,pins = "pmc";
130 nvidia,function = "pwr_on";
131 };
132 rm {
133 nvidia,pins = "rm";
134 nvidia,function = "i2c1";
135 };
136 sdb {
137 nvidia,pins = "sdb", "sdc", "sdd";
138 nvidia,function = "pwm";
139 };
140 sdio1 {
141 nvidia,pins = "sdio1";
142 nvidia,function = "sdio1";
143 };
144 slxc {
145 nvidia,pins = "slxc", "slxd";
146 nvidia,function = "spdif";
147 };
148 spid {
149 nvidia,pins = "spid", "spie", "spif";
150 nvidia,function = "spi1";
151 };
152 spig {
153 nvidia,pins = "spig", "spih";
154 nvidia,function = "spi2_alt";
155 };
156 uaa {
157 nvidia,pins = "uaa", "uab", "uda";
158 nvidia,function = "ulpi";
159 };
160 uad {
161 nvidia,pins = "uad";
162 nvidia,function = "irda";
163 };
164 uca {
165 nvidia,pins = "uca", "ucb";
166 nvidia,function = "uartc";
167 };
168 conf_ata {
169 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
170 "cdev1", "dap1", "dtb", "gma", "gmb",
171 "gmc", "gmd", "gme", "gpu7", "gpv",
172 "i2cp", "pta", "rm", "slxa", "slxk",
173 "spia", "spib";
174 nvidia,pull = <0>;
175 nvidia,tristate = <0>;
176 };
177 conf_cdev2 {
178 nvidia,pins = "cdev2", "csus", "spid", "spif";
179 nvidia,pull = <1>;
180 nvidia,tristate = <1>;
181 };
182 conf_ck32 {
183 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
184 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
185 nvidia,pull = <0>;
186 };
187 conf_crtp {
188 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
189 "dtc", "dte", "dtf", "gpu", "sdio1",
190 "slxc", "slxd", "spdi", "spdo", "spig",
191 "uac", "uda";
192 nvidia,pull = <0>;
193 nvidia,tristate = <1>;
194 };
195 conf_ddc {
196 nvidia,pins = "ddc", "dta", "dtd", "kbca",
197 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
198 "sdc";
199 nvidia,pull = <2>;
200 nvidia,tristate = <0>;
201 };
202 conf_hdint {
203 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
204 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
205 "lvp0", "owc", "sdb";
206 nvidia,tristate = <1>;
207 };
208 conf_irrx {
209 nvidia,pins = "irrx", "irtx", "sdd", "spic",
210 "spie", "spih", "uaa", "uab", "uad",
211 "uca", "ucb";
212 nvidia,pull = <2>;
213 nvidia,tristate = <1>;
214 };
215 conf_lc {
216 nvidia,pins = "lc", "ls";
217 nvidia,pull = <2>;
218 };
219 conf_ld0 {
220 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
221 "ld5", "ld6", "ld7", "ld8", "ld9",
222 "ld10", "ld11", "ld12", "ld13", "ld14",
223 "ld15", "ld16", "ld17", "ldi", "lhp0",
224 "lhp1", "lhp2", "lhs", "lm0", "lpp",
225 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
226 "lvs", "pmc";
227 nvidia,tristate = <0>;
228 };
229 conf_ld17_0 {
230 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
231 "ld23_22";
232 nvidia,pull = <1>;
233 };
234 };
235 };
236
13 pmc@7000f400 { 237 pmc@7000f400 {
14 nvidia,invert-interrupt; 238 nvidia,invert-interrupt;
15 }; 239 };
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 6c02abb469d4..10943fb2561c 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -10,6 +10,226 @@
10 reg = <0x00000000 0x20000000>; 10 reg = <0x00000000 0x20000000>;
11 }; 11 };
12 12
13 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata", "atc", "atd", "ate",
20 "dap2", "gmb", "gmc", "gmd", "spia",
21 "spib", "spic", "spid", "spie";
22 nvidia,function = "gmi";
23 };
24 atb {
25 nvidia,pins = "atb", "gma", "gme";
26 nvidia,function = "sdio4";
27 };
28 cdev1 {
29 nvidia,pins = "cdev1";
30 nvidia,function = "plla_out";
31 };
32 cdev2 {
33 nvidia,pins = "cdev2";
34 nvidia,function = "pllp_out4";
35 };
36 crtp {
37 nvidia,pins = "crtp";
38 nvidia,function = "crt";
39 };
40 csus {
41 nvidia,pins = "csus";
42 nvidia,function = "pllc_out1";
43 };
44 dap1 {
45 nvidia,pins = "dap1";
46 nvidia,function = "dap1";
47 };
48 dap3 {
49 nvidia,pins = "dap3";
50 nvidia,function = "dap3";
51 };
52 dap4 {
53 nvidia,pins = "dap4";
54 nvidia,function = "dap4";
55 };
56 ddc {
57 nvidia,pins = "ddc";
58 nvidia,function = "i2c2";
59 };
60 dta {
61 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
62 nvidia,function = "rsvd1";
63 };
64 dtf {
65 nvidia,pins = "dtf";
66 nvidia,function = "i2c3";
67 };
68 gpu {
69 nvidia,pins = "gpu", "sdb", "sdd";
70 nvidia,function = "pwm";
71 };
72 gpu7 {
73 nvidia,pins = "gpu7";
74 nvidia,function = "rtck";
75 };
76 gpv {
77 nvidia,pins = "gpv", "slxa", "slxk";
78 nvidia,function = "pcie";
79 };
80 hdint {
81 nvidia,pins = "hdint", "pta";
82 nvidia,function = "hdmi";
83 };
84 i2cp {
85 nvidia,pins = "i2cp";
86 nvidia,function = "i2cp";
87 };
88 irrx {
89 nvidia,pins = "irrx", "irtx";
90 nvidia,function = "uarta";
91 };
92 kbca {
93 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
94 nvidia,function = "kbc";
95 };
96 kbcb {
97 nvidia,pins = "kbcb", "kbcd";
98 nvidia,function = "sdio2";
99 };
100 lcsn {
101 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
102 "ld3", "ld4", "ld5", "ld6", "ld7",
103 "ld8", "ld9", "ld10", "ld11", "ld12",
104 "ld13", "ld14", "ld15", "ld16", "ld17",
105 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
106 "lhs", "lm0", "lm1", "lpp", "lpw0",
107 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
108 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
109 "lvs";
110 nvidia,function = "displaya";
111 };
112 owc {
113 nvidia,pins = "owc";
114 nvidia,function = "owr";
115 };
116 pmc {
117 nvidia,pins = "pmc";
118 nvidia,function = "pwr_on";
119 };
120 rm {
121 nvidia,pins = "rm";
122 nvidia,function = "i2c1";
123 };
124 sdc {
125 nvidia,pins = "sdc";
126 nvidia,function = "twc";
127 };
128 sdio1 {
129 nvidia,pins = "sdio1";
130 nvidia,function = "sdio1";
131 };
132 slxc {
133 nvidia,pins = "slxc", "slxd";
134 nvidia,function = "spi4";
135 };
136 spdi {
137 nvidia,pins = "spdi", "spdo";
138 nvidia,function = "rsvd2";
139 };
140 spif {
141 nvidia,pins = "spif", "uac";
142 nvidia,function = "rsvd4";
143 };
144 spig {
145 nvidia,pins = "spig", "spih";
146 nvidia,function = "spi2_alt";
147 };
148 uaa {
149 nvidia,pins = "uaa", "uab", "uda";
150 nvidia,function = "ulpi";
151 };
152 uad {
153 nvidia,pins = "uad";
154 nvidia,function = "spdif";
155 };
156 uca {
157 nvidia,pins = "uca", "ucb";
158 nvidia,function = "uartc";
159 };
160 conf_ata {
161 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
162 "cdev1", "dap1", "dap2", "dtf", "gma",
163 "gmb", "gmc", "gmd", "gme", "gpu",
164 "gpu7", "gpv", "i2cp", "pta", "rm",
165 "sdio1", "slxk", "spdo", "uac", "uda";
166 nvidia,pull = <0>;
167 nvidia,tristate = <0>;
168 };
169 conf_cdev2 {
170 nvidia,pins = "cdev2";
171 nvidia,pull = <1>;
172 nvidia,tristate = <0>;
173 };
174 conf_ck32 {
175 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
176 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
177 nvidia,pull = <0>;
178 };
179 conf_crtp {
180 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
181 "dtc", "dte", "slxa", "slxc", "slxd",
182 "spdi";
183 nvidia,pull = <0>;
184 nvidia,tristate = <1>;
185 };
186 conf_csus {
187 nvidia,pins = "csus", "spia", "spib", "spid",
188 "spif";
189 nvidia,pull = <1>;
190 nvidia,tristate = <1>;
191 };
192 conf_ddc {
193 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
194 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
195 "spic", "spig", "uaa", "uab";
196 nvidia,pull = <2>;
197 nvidia,tristate = <0>;
198 };
199 conf_dta {
200 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
201 "spie", "spih", "uad", "uca", "ucb";
202 nvidia,pull = <2>;
203 nvidia,tristate = <1>;
204 };
205 conf_hdint {
206 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
207 "ld3", "ld4", "ld5", "ld6", "ld7",
208 "ld8", "ld9", "ld10", "ld11", "ld12",
209 "ld13", "ld14", "ld15", "ld16", "ld17",
210 "ldc", "ldi", "lhs", "lsc0", "lspi",
211 "lvs", "pmc";
212 nvidia,tristate = <0>;
213 };
214 conf_lc {
215 nvidia,pins = "lc", "ls";
216 nvidia,pull = <2>;
217 };
218 conf_lcsn {
219 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
220 "lm0", "lm1", "lpp", "lpw0", "lpw1",
221 "lpw2", "lsc1", "lsck", "lsda", "lsdi",
222 "lvp0", "lvp1", "sdb";
223 nvidia,tristate = <1>;
224 };
225 conf_ld17_0 {
226 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
227 "ld23_22";
228 nvidia,pull = <1>;
229 };
230 };
231 };
232
13 i2c@7000c000 { 233 i2c@7000c000 {
14 clock-frequency = <400000>; 234 clock-frequency = <400000>;
15 235
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index dbf1c5a171c2..ec33116f5df9 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -11,6 +11,249 @@
11 reg = < 0x00000000 0x40000000 >; 11 reg = < 0x00000000 0x40000000 >;
12 }; 12 };
13 13
14 pinmux@70000000 {
15 pinctrl-names = "default";
16 pinctrl-0 = <&state_default>;
17
18 state_default: pinmux {
19 ata {
20 nvidia,pins = "ata";
21 nvidia,function = "ide";
22 };
23 atb {
24 nvidia,pins = "atb", "gma", "gme";
25 nvidia,function = "sdio4";
26 };
27 atc {
28 nvidia,pins = "atc";
29 nvidia,function = "nand";
30 };
31 atd {
32 nvidia,pins = "atd", "ate", "gmb", "spia",
33 "spib", "spic";
34 nvidia,function = "gmi";
35 };
36 cdev1 {
37 nvidia,pins = "cdev1";
38 nvidia,function = "plla_out";
39 };
40 cdev2 {
41 nvidia,pins = "cdev2";
42 nvidia,function = "pllp_out4";
43 };
44 crtp {
45 nvidia,pins = "crtp", "lm1";
46 nvidia,function = "crt";
47 };
48 csus {
49 nvidia,pins = "csus";
50 nvidia,function = "vi_sensor_clk";
51 };
52 dap1 {
53 nvidia,pins = "dap1";
54 nvidia,function = "dap1";
55 };
56 dap2 {
57 nvidia,pins = "dap2";
58 nvidia,function = "dap2";
59 };
60 dap3 {
61 nvidia,pins = "dap3";
62 nvidia,function = "dap3";
63 };
64 dap4 {
65 nvidia,pins = "dap4";
66 nvidia,function = "dap4";
67 };
68 ddc {
69 nvidia,pins = "ddc", "owc", "spdi", "spdo",
70 "uac";
71 nvidia,function = "rsvd2";
72 };
73 dta {
74 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
75 nvidia,function = "vi";
76 };
77 dtf {
78 nvidia,pins = "dtf";
79 nvidia,function = "i2c3";
80 };
81 gmc {
82 nvidia,pins = "gmc";
83 nvidia,function = "uartd";
84 };
85 gmd {
86 nvidia,pins = "gmd";
87 nvidia,function = "sflash";
88 };
89 gpu {
90 nvidia,pins = "gpu";
91 nvidia,function = "pwm";
92 };
93 gpu7 {
94 nvidia,pins = "gpu7";
95 nvidia,function = "rtck";
96 };
97 gpv {
98 nvidia,pins = "gpv", "slxa", "slxk";
99 nvidia,function = "pcie";
100 };
101 hdint {
102 nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
103 "lsck", "lsda", "pta";
104 nvidia,function = "hdmi";
105 };
106 i2cp {
107 nvidia,pins = "i2cp";
108 nvidia,function = "i2cp";
109 };
110 irrx {
111 nvidia,pins = "irrx", "irtx";
112 nvidia,function = "uartb";
113 };
114 kbca {
115 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
116 "kbce", "kbcf";
117 nvidia,function = "kbc";
118 };
119 lcsn {
120 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
121 "lsdi", "lvp0";
122 nvidia,function = "rsvd4";
123 };
124 ld0 {
125 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
126 "ld5", "ld6", "ld7", "ld8", "ld9",
127 "ld10", "ld11", "ld12", "ld13", "ld14",
128 "ld15", "ld16", "ld17", "ldi", "lhp0",
129 "lhp1", "lhp2", "lhs", "lpp", "lsc0",
130 "lspi", "lvp1", "lvs";
131 nvidia,function = "displaya";
132 };
133 pmc {
134 nvidia,pins = "pmc";
135 nvidia,function = "pwr_on";
136 };
137 rm {
138 nvidia,pins = "rm";
139 nvidia,function = "i2c1";
140 };
141 sdb {
142 nvidia,pins = "sdb", "sdc", "sdd";
143 nvidia,function = "sdio3";
144 };
145 sdio1 {
146 nvidia,pins = "sdio1";
147 nvidia,function = "sdio1";
148 };
149 slxc {
150 nvidia,pins = "slxc", "slxd";
151 nvidia,function = "spdif";
152 };
153 spid {
154 nvidia,pins = "spid", "spie", "spif";
155 nvidia,function = "spi1";
156 };
157 spig {
158 nvidia,pins = "spig", "spih";
159 nvidia,function = "spi2_alt";
160 };
161 uaa {
162 nvidia,pins = "uaa", "uab", "uda";
163 nvidia,function = "ulpi";
164 };
165 uad {
166 nvidia,pins = "uad";
167 nvidia,function = "irda";
168 };
169 uca {
170 nvidia,pins = "uca", "ucb";
171 nvidia,function = "uartc";
172 };
173 conf_ata {
174 nvidia,pins = "ata", "atb", "atc", "atd",
175 "cdev1", "cdev2", "dap1", "dap2",
176 "dap4", "dtf", "gma", "gmc", "gmd",
177 "gme", "gpu", "gpu7", "i2cp", "irrx",
178 "irtx", "pta", "rm", "sdc", "sdd",
179 "slxd", "slxk", "spdi", "spdo", "uac",
180 "uad", "uca", "ucb", "uda";
181 nvidia,pull = <0>;
182 nvidia,tristate = <0>;
183 };
184 conf_ate {
185 nvidia,pins = "ate", "csus", "dap3", "ddc",
186 "gpv", "owc", "slxc", "spib", "spid",
187 "spie";
188 nvidia,pull = <0>;
189 nvidia,tristate = <1>;
190 };
191 conf_ck32 {
192 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
193 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
194 nvidia,pull = <0>;
195 };
196 conf_crtp {
197 nvidia,pins = "crtp", "gmb", "slxa", "spia",
198 "spig", "spih";
199 nvidia,pull = <2>;
200 nvidia,tristate = <1>;
201 };
202 conf_dta {
203 nvidia,pins = "dta", "dtb", "dtc", "dtd";
204 nvidia,pull = <1>;
205 nvidia,tristate = <0>;
206 };
207 conf_dte {
208 nvidia,pins = "dte", "spif";
209 nvidia,pull = <1>;
210 nvidia,tristate = <1>;
211 };
212 conf_hdint {
213 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
214 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
215 "lvp0";
216 nvidia,tristate = <1>;
217 };
218 conf_kbca {
219 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
220 "kbce", "kbcf", "sdio1", "spic", "uaa",
221 "uab";
222 nvidia,pull = <2>;
223 nvidia,tristate = <0>;
224 };
225 conf_lc {
226 nvidia,pins = "lc", "ls";
227 nvidia,pull = <2>;
228 };
229 conf_ld0 {
230 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
231 "ld5", "ld6", "ld7", "ld8", "ld9",
232 "ld10", "ld11", "ld12", "ld13", "ld14",
233 "ld15", "ld16", "ld17", "ldi", "lhp0",
234 "lhp1", "lhp2", "lhs", "lm0", "lpp",
235 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
236 "lvs", "pmc", "sdb";
237 nvidia,tristate = <0>;
238 };
239 conf_ld17_0 {
240 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
241 "ld23_22";
242 nvidia,pull = <1>;
243 };
244 drive_sdio1 {
245 nvidia,pins = "drive_sdio1";
246 nvidia,high-speed-mode = <0>;
247 nvidia,schmitt = <0>;
248 nvidia,low-power-mode = <3>;
249 nvidia,pull-down-strength = <31>;
250 nvidia,pull-up-strength = <31>;
251 nvidia,slew-rate-rising = <3>;
252 nvidia,slew-rate-falling = <3>;
253 };
254 };
255 };
256
14 i2c@7000c000 { 257 i2c@7000c000 {
15 clock-frequency = <400000>; 258 clock-frequency = <400000>;
16 259
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
index 252476867b54..98efd5b0d7f9 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -10,6 +10,236 @@
10 reg = < 0x00000000 0x40000000 >; 10 reg = < 0x00000000 0x40000000 >;
11 }; 11 };
12 12
13 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc", "gmb";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gme", "pta";
32 nvidia,function = "gmi";
33 };
34 cdev1 {
35 nvidia,pins = "cdev1";
36 nvidia,function = "plla_out";
37 };
38 cdev2 {
39 nvidia,pins = "cdev2";
40 nvidia,function = "pllp_out4";
41 };
42 crtp {
43 nvidia,pins = "crtp";
44 nvidia,function = "crt";
45 };
46 csus {
47 nvidia,pins = "csus";
48 nvidia,function = "vi_sensor_clk";
49 };
50 dap1 {
51 nvidia,pins = "dap1";
52 nvidia,function = "dap1";
53 };
54 dap2 {
55 nvidia,pins = "dap2";
56 nvidia,function = "dap2";
57 };
58 dap3 {
59 nvidia,pins = "dap3";
60 nvidia,function = "dap3";
61 };
62 dap4 {
63 nvidia,pins = "dap4";
64 nvidia,function = "dap4";
65 };
66 ddc {
67 nvidia,pins = "ddc";
68 nvidia,function = "i2c2";
69 };
70 dta {
71 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
72 nvidia,function = "vi";
73 };
74 dtf {
75 nvidia,pins = "dtf";
76 nvidia,function = "i2c3";
77 };
78 gmc {
79 nvidia,pins = "gmc", "gmd";
80 nvidia,function = "sflash";
81 };
82 gpu {
83 nvidia,pins = "gpu";
84 nvidia,function = "uarta";
85 };
86 gpu7 {
87 nvidia,pins = "gpu7";
88 nvidia,function = "rtck";
89 };
90 gpv {
91 nvidia,pins = "gpv", "slxa", "slxk";
92 nvidia,function = "pcie";
93 };
94 hdint {
95 nvidia,pins = "hdint";
96 nvidia,function = "hdmi";
97 };
98 i2cp {
99 nvidia,pins = "i2cp";
100 nvidia,function = "i2cp";
101 };
102 irrx {
103 nvidia,pins = "irrx", "irtx";
104 nvidia,function = "uartb";
105 };
106 kbca {
107 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
108 "kbce", "kbcf";
109 nvidia,function = "kbc";
110 };
111 lcsn {
112 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
113 "ld3", "ld4", "ld5", "ld6", "ld7",
114 "ld8", "ld9", "ld10", "ld11", "ld12",
115 "ld13", "ld14", "ld15", "ld16", "ld17",
116 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
117 "lhs", "lm0", "lm1", "lpp", "lpw0",
118 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
119 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
120 "lvs";
121 nvidia,function = "displaya";
122 };
123 owc {
124 nvidia,pins = "owc", "uac";
125 nvidia,function = "rsvd2";
126 };
127 pmc {
128 nvidia,pins = "pmc";
129 nvidia,function = "pwr_on";
130 };
131 rm {
132 nvidia,pins = "rm";
133 nvidia,function = "i2c1";
134 };
135 sdb {
136 nvidia,pins = "sdb", "sdc", "sdd";
137 nvidia,function = "pwm";
138 };
139 sdio1 {
140 nvidia,pins = "sdio1";
141 nvidia,function = "sdio1";
142 };
143 slxc {
144 nvidia,pins = "slxc", "slxd";
145 nvidia,function = "sdio3";
146 };
147 spdi {
148 nvidia,pins = "spdi", "spdo";
149 nvidia,function = "spdif";
150 };
151 spia {
152 nvidia,pins = "spia", "spib", "spic";
153 nvidia,function = "spi2";
154 };
155 spid {
156 nvidia,pins = "spid", "spie", "spif";
157 nvidia,function = "spi1";
158 };
159 spig {
160 nvidia,pins = "spig", "spih";
161 nvidia,function = "spi2_alt";
162 };
163 uaa {
164 nvidia,pins = "uaa", "uab", "uda";
165 nvidia,function = "ulpi";
166 };
167 uad {
168 nvidia,pins = "uad";
169 nvidia,function = "irda";
170 };
171 uca {
172 nvidia,pins = "uca", "ucb";
173 nvidia,function = "uartc";
174 };
175 conf_ata {
176 nvidia,pins = "ata", "atc", "atd", "ate",
177 "crtp", "dap2", "dap3", "dap4", "dta",
178 "dtb", "dtc", "dtd", "dte", "gmb",
179 "gme", "i2cp", "pta", "slxc", "slxd",
180 "spdi", "spdo", "uda";
181 nvidia,pull = <0>;
182 nvidia,tristate = <1>;
183 };
184 conf_atb {
185 nvidia,pins = "atb", "cdev1", "dap1", "gma",
186 "gmc", "gmd", "gpu", "gpu7", "gpv",
187 "sdio1", "slxa", "slxk", "uac";
188 nvidia,pull = <0>;
189 nvidia,tristate = <0>;
190 };
191 conf_cdev2 {
192 nvidia,pins = "cdev2", "csus", "spia", "spib",
193 "spid", "spif";
194 nvidia,pull = <1>;
195 nvidia,tristate = <1>;
196 };
197 conf_ck32 {
198 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
199 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
200 nvidia,pull = <0>;
201 };
202 conf_ddc {
203 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
204 nvidia,pull = <2>;
205 nvidia,tristate = <0>;
206 };
207 conf_hdint {
208 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
209 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
210 "lvp0", "pmc";
211 nvidia,tristate = <1>;
212 };
213 conf_irrx {
214 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
215 "kbcc", "kbcd", "kbce", "kbcf", "owc",
216 "spic", "spie", "spig", "spih", "uaa",
217 "uab", "uad", "uca", "ucb";
218 nvidia,pull = <2>;
219 nvidia,tristate = <1>;
220 };
221 conf_lc {
222 nvidia,pins = "lc", "ls";
223 nvidia,pull = <2>;
224 };
225 conf_ld0 {
226 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
227 "ld5", "ld6", "ld7", "ld8", "ld9",
228 "ld10", "ld11", "ld12", "ld13", "ld14",
229 "ld15", "ld16", "ld17", "ldi", "lhp0",
230 "lhp1", "lhp2", "lhs", "lm0", "lpp",
231 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
232 "lvs", "sdb";
233 nvidia,tristate = <0>;
234 };
235 conf_ld17_0 {
236 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
237 "ld23_22";
238 nvidia,pull = <1>;
239 };
240 };
241 };
242
13 i2c@7000c000 { 243 i2c@7000c000 {
14 clock-frequency = <400000>; 244 clock-frequency = <400000>;
15 }; 245 };
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index 2dcff8728e90..71eb2e50a668 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -10,6 +10,236 @@
10 reg = < 0x00000000 0x40000000 >; 10 reg = < 0x00000000 0x40000000 >;
11 }; 11 };
12 12
13 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "spia",
32 "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp", "lm1";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
67 ddc {
68 nvidia,pins = "ddc", "owc", "spdi", "spdo",
69 "uac";
70 nvidia,function = "rsvd2";
71 };
72 dta {
73 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
74 nvidia,function = "vi";
75 };
76 dtf {
77 nvidia,pins = "dtf";
78 nvidia,function = "i2c3";
79 };
80 gmc {
81 nvidia,pins = "gmc";
82 nvidia,function = "uartd";
83 };
84 gmd {
85 nvidia,pins = "gmd";
86 nvidia,function = "sflash";
87 };
88 gpu {
89 nvidia,pins = "gpu";
90 nvidia,function = "pwm";
91 };
92 gpu7 {
93 nvidia,pins = "gpu7";
94 nvidia,function = "rtck";
95 };
96 gpv {
97 nvidia,pins = "gpv", "slxa", "slxk";
98 nvidia,function = "pcie";
99 };
100 hdint {
101 nvidia,pins = "hdint", "pta";
102 nvidia,function = "hdmi";
103 };
104 i2cp {
105 nvidia,pins = "i2cp";
106 nvidia,function = "i2cp";
107 };
108 irrx {
109 nvidia,pins = "irrx", "irtx";
110 nvidia,function = "uartb";
111 };
112 kbca {
113 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
114 "kbce", "kbcf";
115 nvidia,function = "kbc";
116 };
117 lcsn {
118 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
119 "lsdi", "lvp0";
120 nvidia,function = "rsvd4";
121 };
122 ld0 {
123 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
124 "ld5", "ld6", "ld7", "ld8", "ld9",
125 "ld10", "ld11", "ld12", "ld13", "ld14",
126 "ld15", "ld16", "ld17", "ldi", "lhp0",
127 "lhp1", "lhp2", "lhs", "lpp", "lpw0",
128 "lpw2", "lsc0", "lsc1", "lsck", "lsda",
129 "lspi", "lvp1", "lvs";
130 nvidia,function = "displaya";
131 };
132 pmc {
133 nvidia,pins = "pmc";
134 nvidia,function = "pwr_on";
135 };
136 rm {
137 nvidia,pins = "rm";
138 nvidia,function = "i2c1";
139 };
140 sdb {
141 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
142 nvidia,function = "sdio3";
143 };
144 sdio1 {
145 nvidia,pins = "sdio1";
146 nvidia,function = "sdio1";
147 };
148 slxd {
149 nvidia,pins = "slxd";
150 nvidia,function = "spdif";
151 };
152 spid {
153 nvidia,pins = "spid", "spie", "spif";
154 nvidia,function = "spi1";
155 };
156 spig {
157 nvidia,pins = "spig", "spih";
158 nvidia,function = "spi2_alt";
159 };
160 uaa {
161 nvidia,pins = "uaa", "uab", "uda";
162 nvidia,function = "ulpi";
163 };
164 uad {
165 nvidia,pins = "uad";
166 nvidia,function = "irda";
167 };
168 uca {
169 nvidia,pins = "uca", "ucb";
170 nvidia,function = "uartc";
171 };
172 conf_ata {
173 nvidia,pins = "ata", "atb", "atc", "atd",
174 "cdev1", "cdev2", "dap1", "dap2",
175 "dap4", "ddc", "dtf", "gma", "gmc",
176 "gme", "gpu", "gpu7", "i2cp", "irrx",
177 "irtx", "pta", "rm", "sdc", "sdd",
178 "slxc", "slxd", "slxk", "spdi", "spdo",
179 "uac", "uad", "uca", "ucb", "uda";
180 nvidia,pull = <0>;
181 nvidia,tristate = <0>;
182 };
183 conf_ate {
184 nvidia,pins = "ate", "csus", "dap3", "gmd",
185 "gpv", "owc", "spia", "spib", "spic",
186 "spid", "spie", "spig";
187 nvidia,pull = <0>;
188 nvidia,tristate = <1>;
189 };
190 conf_ck32 {
191 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
192 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
193 nvidia,pull = <0>;
194 };
195 conf_crtp {
196 nvidia,pins = "crtp", "gmb", "slxa", "spih";
197 nvidia,pull = <2>;
198 nvidia,tristate = <1>;
199 };
200 conf_dta {
201 nvidia,pins = "dta", "dtb", "dtc", "dtd";
202 nvidia,pull = <1>;
203 nvidia,tristate = <0>;
204 };
205 conf_dte {
206 nvidia,pins = "dte", "spif";
207 nvidia,pull = <1>;
208 nvidia,tristate = <1>;
209 };
210 conf_hdint {
211 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
212 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
213 nvidia,tristate = <1>;
214 };
215 conf_kbca {
216 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
217 "kbce", "kbcf", "sdio1", "uaa", "uab";
218 nvidia,pull = <2>;
219 nvidia,tristate = <0>;
220 };
221 conf_lc {
222 nvidia,pins = "lc", "ls";
223 nvidia,pull = <2>;
224 };
225 conf_ld0 {
226 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
227 "ld5", "ld6", "ld7", "ld8", "ld9",
228 "ld10", "ld11", "ld12", "ld13", "ld14",
229 "ld15", "ld16", "ld17", "ldi", "lhp0",
230 "lhp1", "lhp2", "lhs", "lm0", "lpp",
231 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
232 "lvp1", "lvs", "pmc", "sdb";
233 nvidia,tristate = <0>;
234 };
235 conf_ld17_0 {
236 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
237 "ld23_22";
238 nvidia,pull = <1>;
239 };
240 };
241 };
242
13 i2c@7000c000 { 243 i2c@7000c000 {
14 clock-frequency = <400000>; 244 clock-frequency = <400000>;
15 245
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index 37207d1bf44b..bf123c5384d4 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -97,6 +97,7 @@ CONFIG_I2C=y
97CONFIG_I2C_CHARDEV=y 97CONFIG_I2C_CHARDEV=y
98CONFIG_I2C_GPIO=y 98CONFIG_I2C_GPIO=y
99CONFIG_DEBUG_GPIO=y 99CONFIG_DEBUG_GPIO=y
100CONFIG_PINCTRL_NOMADIK=y
100# CONFIG_HWMON is not set 101# CONFIG_HWMON is not set
101# CONFIG_VGA_CONSOLE is not set 102# CONFIG_VGA_CONSOLE is not set
102CONFIG_RTC_CLASS=y 103CONFIG_RTC_CLASS=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index f72d399ff3d6..c8f83e9e5633 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -844,6 +844,8 @@ config SOC_IMX6Q
844 select HAVE_IMX_MMDC 844 select HAVE_IMX_MMDC
845 select HAVE_IMX_SRC 845 select HAVE_IMX_SRC
846 select HAVE_SMP 846 select HAVE_SMP
847 select PINCTRL
848 select PINCTRL_IMX6Q
847 select USE_OF 849 select USE_OF
848 850
849 help 851 help
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 5cca573964f0..5f577fbda2c8 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -14,6 +14,7 @@
14#include <linux/irqdomain.h> 14#include <linux/irqdomain.h>
15#include <linux/of_irq.h> 15#include <linux/of_irq.h>
16#include <linux/of_platform.h> 16#include <linux/of_platform.h>
17#include <linux/pinctrl/machine.h>
17#include <asm/mach/arch.h> 18#include <asm/mach/arch.h>
18#include <asm/mach/time.h> 19#include <asm/mach/time.h>
19#include <mach/common.h> 20#include <mach/common.h>
@@ -81,6 +82,8 @@ static void __init imx51_dt_init(void)
81 82
82 of_irq_init(imx51_irq_match); 83 of_irq_init(imx51_irq_match);
83 84
85 pinctrl_provide_dummies();
86
84 node = of_find_matching_node(NULL, imx51_iomuxc_of_match); 87 node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
85 if (node) { 88 if (node) {
86 of_id = of_match_node(imx51_iomuxc_of_match, node); 89 of_id = of_match_node(imx51_iomuxc_of_match, node);
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index 4172279b3900..574eca4b89a5 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -15,6 +15,7 @@
15#include <linux/irqdomain.h> 15#include <linux/irqdomain.h>
16#include <linux/of_irq.h> 16#include <linux/of_irq.h>
17#include <linux/of_platform.h> 17#include <linux/of_platform.h>
18#include <linux/pinctrl/machine.h>
18#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
19#include <asm/mach/time.h> 20#include <asm/mach/time.h>
20#include <mach/common.h> 21#include <mach/common.h>
@@ -88,6 +89,8 @@ static void __init imx53_dt_init(void)
88 89
89 of_irq_init(imx53_irq_match); 90 of_irq_init(imx53_irq_match);
90 91
92 pinctrl_provide_dummies();
93
91 node = of_find_matching_node(NULL, imx53_iomuxc_of_match); 94 node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
92 if (node) { 95 if (node) {
93 of_id = of_match_node(imx53_iomuxc_of_match, node); 96 of_id = of_match_node(imx53_iomuxc_of_match, node);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index da6c1d9af768..3df360a52c17 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -19,6 +19,7 @@
19#include <linux/of_address.h> 19#include <linux/of_address.h>
20#include <linux/of_irq.h> 20#include <linux/of_irq.h>
21#include <linux/of_platform.h> 21#include <linux/of_platform.h>
22#include <linux/pinctrl/machine.h>
22#include <linux/phy.h> 23#include <linux/phy.h>
23#include <linux/micrel_phy.h> 24#include <linux/micrel_phy.h>
24#include <asm/smp_twd.h> 25#include <asm/smp_twd.h>
@@ -77,6 +78,12 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev)
77 78
78static void __init imx6q_init_machine(void) 79static void __init imx6q_init_machine(void)
79{ 80{
81 /*
82 * This should be removed when all imx6q boards have pinctrl
83 * states for devices defined in device tree.
84 */
85 pinctrl_provide_dummies();
86
80 if (of_machine_is_compatible("fsl,imx6q-sabrelite")) 87 if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
81 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, 88 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
82 ksz9021rn_phy_fixup); 89 ksz9021rn_phy_fixup);
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 2bded591d5c2..fcafd3dafb8c 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -18,6 +18,7 @@
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/pinctrl/machine.h>
21 22
22#include <asm/mach/map.h> 23#include <asm/mach/map.h>
23 24
@@ -58,4 +59,5 @@ void __init imx1_soc_init(void)
58 MX1_GPIO_INT_PORTC, 0); 59 MX1_GPIO_INT_PORTC, 0);
59 mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256, 60 mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
60 MX1_GPIO_INT_PORTD, 0); 61 MX1_GPIO_INT_PORTD, 0);
62 pinctrl_provide_dummies();
61} 63}
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 14d540edfd1e..5f43905e5290 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -20,6 +20,7 @@
20 20
21#include <linux/mm.h> 21#include <linux/mm.h>
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/pinctrl/machine.h>
23#include <mach/hardware.h> 24#include <mach/hardware.h>
24#include <mach/common.h> 25#include <mach/common.h>
25#include <mach/devices-common.h> 26#include <mach/devices-common.h>
@@ -88,6 +89,7 @@ void __init imx21_soc_init(void)
88 mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); 89 mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
89 mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); 90 mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
90 91
92 pinctrl_provide_dummies();
91 imx_add_imx_dma(); 93 imx_add_imx_dma();
92 platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res, 94 platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
93 ARRAY_SIZE(imx21_audmux_res)); 95 ARRAY_SIZE(imx21_audmux_res));
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 153b457acdc0..6ff37140a4f8 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -19,6 +19,7 @@
19#include <linux/mm.h> 19#include <linux/mm.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/pinctrl/machine.h>
22 23
23#include <asm/pgtable.h> 24#include <asm/pgtable.h>
24#include <asm/mach/map.h> 25#include <asm/mach/map.h>
@@ -95,6 +96,7 @@ void __init imx25_soc_init(void)
95 mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0); 96 mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
96 mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0); 97 mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
97 98
99 pinctrl_provide_dummies();
98 /* i.mx25 has the i.mx35 type sdma */ 100 /* i.mx25 has the i.mx35 type sdma */
99 imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata); 101 imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
100 /* i.mx25 has the i.mx31 type audmux */ 102 /* i.mx25 has the i.mx31 type audmux */
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 8cb3f5e3e569..25662558e018 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -20,6 +20,7 @@
20 20
21#include <linux/mm.h> 21#include <linux/mm.h>
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/pinctrl/machine.h>
23#include <mach/hardware.h> 24#include <mach/hardware.h>
24#include <mach/common.h> 25#include <mach/common.h>
25#include <mach/devices-common.h> 26#include <mach/devices-common.h>
@@ -89,6 +90,7 @@ void __init imx27_soc_init(void)
89 mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); 90 mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
90 mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); 91 mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
91 92
93 pinctrl_provide_dummies();
92 imx_add_imx_dma(); 94 imx_add_imx_dma();
93 /* imx27 has the imx21 type audmux */ 95 /* imx27 has the imx21 type audmux */
94 platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res, 96 platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 74127389e7ab..9128d15b1eb7 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -19,6 +19,7 @@
19#include <linux/mm.h> 19#include <linux/mm.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/pinctrl/machine.h>
22 23
23#include <asm/pgtable.h> 24#include <asm/pgtable.h>
24#include <asm/system_misc.h> 25#include <asm/system_misc.h>
@@ -267,6 +268,7 @@ void __init imx35_soc_init(void)
267 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); 268 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
268 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); 269 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
269 270
271 pinctrl_provide_dummies();
270 if (to_version == 1) { 272 if (to_version == 1) {
271 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin", 273 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
272 strlen(imx35_sdma_pdata.fw_name)); 274 strlen(imx35_sdma_pdata.fw_name));
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index e10f3914fcfe..ba91e6b31cf4 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -14,6 +14,7 @@
14#include <linux/mm.h> 14#include <linux/mm.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/clk.h> 16#include <linux/clk.h>
17#include <linux/pinctrl/machine.h>
17 18
18#include <asm/system_misc.h> 19#include <asm/system_misc.h>
19#include <asm/mach/map.h> 20#include <asm/mach/map.h>
@@ -223,6 +224,7 @@ void __init imx53_soc_init(void)
223 mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH); 224 mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
224 mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH); 225 mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
225 226
227 pinctrl_provide_dummies();
226 /* i.mx53 has the i.mx35 type sdma */ 228 /* i.mx53 has the i.mx35 type sdma */
227 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata); 229 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
228 230
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index c57f9964a713..07d5383d68ee 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -9,11 +9,13 @@ config SOC_IMX23
9 bool 9 bool
10 select CPU_ARM926T 10 select CPU_ARM926T
11 select HAVE_PWM 11 select HAVE_PWM
12 select PINCTRL_IMX23
12 13
13config SOC_IMX28 14config SOC_IMX28
14 bool 15 bool
15 select CPU_ARM926T 16 select CPU_ARM926T
16 select HAVE_PWM 17 select HAVE_PWM
18 select PINCTRL_IMX28
17 19
18comment "MXS platforms:" 20comment "MXS platforms:"
19 21
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index c50c3ea28a9d..8d88399b73ef 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -19,11 +19,13 @@ extern void mxs_timer_init(struct clk *, int);
19extern void mxs_restart(char, const char *); 19extern void mxs_restart(char, const char *);
20extern int mxs_saif_clkmux_select(unsigned int clkmux); 20extern int mxs_saif_clkmux_select(unsigned int clkmux);
21 21
22extern void mx23_soc_init(void);
22extern int mx23_register_gpios(void); 23extern int mx23_register_gpios(void);
23extern int mx23_clocks_init(void); 24extern int mx23_clocks_init(void);
24extern void mx23_map_io(void); 25extern void mx23_map_io(void);
25extern void mx23_init_irq(void); 26extern void mx23_init_irq(void);
26 27
28extern void mx28_soc_init(void);
27extern int mx28_register_gpios(void); 29extern int mx28_register_gpios(void);
28extern int mx28_clocks_init(void); 30extern int mx28_clocks_init(void);
29extern void mx28_map_io(void); 31extern void mx28_map_io(void);
diff --git a/arch/arm/mach-mxs/mach-apx4devkit.c b/arch/arm/mach-mxs/mach-apx4devkit.c
index 48a7fab571a6..5e90b9dcdef8 100644
--- a/arch/arm/mach-mxs/mach-apx4devkit.c
+++ b/arch/arm/mach-mxs/mach-apx4devkit.c
@@ -207,6 +207,8 @@ static int apx4devkit_phy_fixup(struct phy_device *phy)
207 207
208static void __init apx4devkit_init(void) 208static void __init apx4devkit_init(void)
209{ 209{
210 mx28_soc_init();
211
210 mxs_iomux_setup_multiple_pads(apx4devkit_pads, 212 mxs_iomux_setup_multiple_pads(apx4devkit_pads,
211 ARRAY_SIZE(apx4devkit_pads)); 213 ARRAY_SIZE(apx4devkit_pads));
212 214
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
index 06d79963611c..4c00c879b893 100644
--- a/arch/arm/mach-mxs/mach-m28evk.c
+++ b/arch/arm/mach-mxs/mach-m28evk.c
@@ -319,6 +319,8 @@ static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = {
319 319
320static void __init m28evk_init(void) 320static void __init m28evk_init(void)
321{ 321{
322 mx28_soc_init();
323
322 mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads)); 324 mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
323 325
324 mx28_add_duart(); 326 mx28_add_duart();
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index 5ea1c57d2606..e7272a41939d 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -141,6 +141,8 @@ static void __init mx23evk_init(void)
141{ 141{
142 int ret; 142 int ret;
143 143
144 mx23_soc_init();
145
144 mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads)); 146 mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
145 147
146 mx23_add_duart(); 148 mx23_add_duart();
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index e386c142f93c..da4610ebe9e6 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -413,6 +413,8 @@ static void __init mx28evk_init(void)
413{ 413{
414 int ret; 414 int ret;
415 415
416 mx28_soc_init();
417
416 mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads)); 418 mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
417 419
418 mx28_add_duart(); 420 mx28_add_duart();
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
index a626c07b8713..6548965e4a76 100644
--- a/arch/arm/mach-mxs/mach-stmp378x_devb.c
+++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c
@@ -85,6 +85,8 @@ static void __init stmp378x_dvb_init(void)
85{ 85{
86 int ret; 86 int ret;
87 87
88 mx23_soc_init();
89
88 mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads, 90 mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
89 ARRAY_SIZE(stmp378x_dvb_pads)); 91 ARRAY_SIZE(stmp378x_dvb_pads));
90 92
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
index 2c0862e655ee..8837029de1a4 100644
--- a/arch/arm/mach-mxs/mach-tx28.c
+++ b/arch/arm/mach-mxs/mach-tx28.c
@@ -146,6 +146,8 @@ static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = {
146 146
147static void __init tx28_stk5v3_init(void) 147static void __init tx28_stk5v3_init(void)
148{ 148{
149 mx28_soc_init();
150
149 mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads, 151 mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
150 ARRAY_SIZE(tx28_stk5v3_pads)); 152 ARRAY_SIZE(tx28_stk5v3_pads));
151 153
diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c
index 50af5ceebf6d..67a384edcf5b 100644
--- a/arch/arm/mach-mxs/mm.c
+++ b/arch/arm/mach-mxs/mm.c
@@ -13,6 +13,7 @@
13 13
14#include <linux/mm.h> 14#include <linux/mm.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/pinctrl/machine.h>
16 17
17#include <asm/mach/map.h> 18#include <asm/mach/map.h>
18 19
@@ -61,3 +62,13 @@ void __init mx28_init_irq(void)
61{ 62{
62 icoll_init_irq(); 63 icoll_init_irq();
63} 64}
65
66void __init mx23_soc_init(void)
67{
68 pinctrl_provide_dummies();
69}
70
71void __init mx28_soc_init(void)
72{
73 pinctrl_provide_dummies();
74}
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 3c5e0f522e9c..365879b47c0e 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -15,6 +15,7 @@ config NOMADIK_8815
15config I2C_BITBANG_8815NHK 15config I2C_BITBANG_8815NHK
16 tristate "Driver for bit-bang busses found on the 8815 NHK" 16 tristate "Driver for bit-bang busses found on the 8815 NHK"
17 depends on I2C && MACH_NOMADIK_8815NHK 17 depends on I2C && MACH_NOMADIK_8815NHK
18 depends on PINCTRL_NOMADIK
18 select I2C_ALGOBIT 19 select I2C_ALGOBIT
19 default y 20 default y
20 21
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index d9fe11cb6f16..8bd37291fa4f 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -7,16 +7,19 @@ if ARCH_SPEAR3XX
7menu "SPEAr3xx Implementations" 7menu "SPEAr3xx Implementations"
8config MACH_SPEAR300 8config MACH_SPEAR300
9 bool "SPEAr300 Machine support with Device Tree" 9 bool "SPEAr300 Machine support with Device Tree"
10 select PINCTRL_SPEAR300
10 help 11 help
11 Supports ST SPEAr300 machine configured via the device-tree 12 Supports ST SPEAr300 machine configured via the device-tree
12 13
13config MACH_SPEAR310 14config MACH_SPEAR310
14 bool "SPEAr310 Machine support with Device Tree" 15 bool "SPEAr310 Machine support with Device Tree"
16 select PINCTRL_SPEAR310
15 help 17 help
16 Supports ST SPEAr310 machine configured via the device-tree 18 Supports ST SPEAr310 machine configured via the device-tree
17 19
18config MACH_SPEAR320 20config MACH_SPEAR320
19 bool "SPEAr320 Machine support with Device Tree" 21 bool "SPEAr320 Machine support with Device Tree"
22 select PINCTRL_SPEAR320
20 help 23 help
21 Supports ST SPEAr320 machine configured via the device-tree 24 Supports ST SPEAr320 machine configured via the device-tree
22endmenu 25endmenu
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index e4f4d721cda2..bdb304551caf 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -20,7 +20,6 @@
20#include <linux/amba/bus.h> 20#include <linux/amba/bus.h>
21#include <asm/mach/time.h> 21#include <asm/mach/time.h>
22#include <asm/mach/map.h> 22#include <asm/mach/map.h>
23#include <plat/padmux.h>
24 23
25/* Add spear3xx family device structure declarations here */ 24/* Add spear3xx family device structure declarations here */
26extern struct sys_timer spear3xx_timer; 25extern struct sys_timer spear3xx_timer;
@@ -34,147 +33,20 @@ void __init spear3xx_dt_init_irq(void);
34 33
35void spear_restart(char, const char *); 34void spear_restart(char, const char *);
36 35
37/* pad mux declarations */
38#define PMX_FIRDA_MASK (1 << 14)
39#define PMX_I2C_MASK (1 << 13)
40#define PMX_SSP_CS_MASK (1 << 12)
41#define PMX_SSP_MASK (1 << 11)
42#define PMX_MII_MASK (1 << 10)
43#define PMX_GPIO_PIN0_MASK (1 << 9)
44#define PMX_GPIO_PIN1_MASK (1 << 8)
45#define PMX_GPIO_PIN2_MASK (1 << 7)
46#define PMX_GPIO_PIN3_MASK (1 << 6)
47#define PMX_GPIO_PIN4_MASK (1 << 5)
48#define PMX_GPIO_PIN5_MASK (1 << 4)
49#define PMX_UART0_MODEM_MASK (1 << 3)
50#define PMX_UART0_MASK (1 << 2)
51#define PMX_TIMER_3_4_MASK (1 << 1)
52#define PMX_TIMER_1_2_MASK (1 << 0)
53
54/* pad mux devices */
55extern struct pmx_dev spear3xx_pmx_firda;
56extern struct pmx_dev spear3xx_pmx_i2c;
57extern struct pmx_dev spear3xx_pmx_ssp_cs;
58extern struct pmx_dev spear3xx_pmx_ssp;
59extern struct pmx_dev spear3xx_pmx_mii;
60extern struct pmx_dev spear3xx_pmx_gpio_pin0;
61extern struct pmx_dev spear3xx_pmx_gpio_pin1;
62extern struct pmx_dev spear3xx_pmx_gpio_pin2;
63extern struct pmx_dev spear3xx_pmx_gpio_pin3;
64extern struct pmx_dev spear3xx_pmx_gpio_pin4;
65extern struct pmx_dev spear3xx_pmx_gpio_pin5;
66extern struct pmx_dev spear3xx_pmx_uart0_modem;
67extern struct pmx_dev spear3xx_pmx_uart0;
68extern struct pmx_dev spear3xx_pmx_timer_3_4;
69extern struct pmx_dev spear3xx_pmx_timer_1_2;
70
71#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
72/* padmux plgpio devices */
73extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
74extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
75extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
76extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
77extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
78extern struct pmx_dev spear3xx_pmx_plgpio_28;
79extern struct pmx_dev spear3xx_pmx_plgpio_29;
80extern struct pmx_dev spear3xx_pmx_plgpio_30;
81extern struct pmx_dev spear3xx_pmx_plgpio_31;
82extern struct pmx_dev spear3xx_pmx_plgpio_32;
83extern struct pmx_dev spear3xx_pmx_plgpio_33;
84extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
85extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
86extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
87extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
88#endif
89
90/* spear300 declarations */ 36/* spear300 declarations */
91#ifdef CONFIG_MACH_SPEAR300 37#ifdef CONFIG_MACH_SPEAR300
92/* pad mux modes */
93extern struct pmx_mode spear300_nand_mode;
94extern struct pmx_mode spear300_nor_mode;
95extern struct pmx_mode spear300_photo_frame_mode;
96extern struct pmx_mode spear300_lend_ip_phone_mode;
97extern struct pmx_mode spear300_hend_ip_phone_mode;
98extern struct pmx_mode spear300_lend_wifi_phone_mode;
99extern struct pmx_mode spear300_hend_wifi_phone_mode;
100extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
101extern struct pmx_mode spear300_ata_pabx_i2s_mode;
102extern struct pmx_mode spear300_caml_lcdw_mode;
103extern struct pmx_mode spear300_camu_lcd_mode;
104extern struct pmx_mode spear300_camu_wlcd_mode;
105extern struct pmx_mode spear300_caml_lcd_mode;
106
107/* pad mux devices */
108extern struct pmx_dev spear300_pmx_fsmc_2_chips;
109extern struct pmx_dev spear300_pmx_fsmc_4_chips;
110extern struct pmx_dev spear300_pmx_keyboard;
111extern struct pmx_dev spear300_pmx_clcd;
112extern struct pmx_dev spear300_pmx_telecom_gpio;
113extern struct pmx_dev spear300_pmx_telecom_tdm;
114extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
115extern struct pmx_dev spear300_pmx_telecom_camera;
116extern struct pmx_dev spear300_pmx_telecom_dac;
117extern struct pmx_dev spear300_pmx_telecom_i2s;
118extern struct pmx_dev spear300_pmx_telecom_boot_pins;
119extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
120extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
121extern struct pmx_dev spear300_pmx_gpio1;
122
123/* Add spear300 machine declarations here */
124void __init spear300_clk_init(void); 38void __init spear300_clk_init(void);
125 39
126#endif /* CONFIG_MACH_SPEAR300 */ 40#endif /* CONFIG_MACH_SPEAR300 */
127 41
128/* spear310 declarations */ 42/* spear310 declarations */
129#ifdef CONFIG_MACH_SPEAR310 43#ifdef CONFIG_MACH_SPEAR310
130/* pad mux devices */
131extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
132extern struct pmx_dev spear310_pmx_emi_cs_2_3;
133extern struct pmx_dev spear310_pmx_uart1;
134extern struct pmx_dev spear310_pmx_uart2;
135extern struct pmx_dev spear310_pmx_uart3_4_5;
136extern struct pmx_dev spear310_pmx_fsmc;
137extern struct pmx_dev spear310_pmx_rs485_0_1;
138extern struct pmx_dev spear310_pmx_tdm0;
139
140/* Add spear310 machine declarations here */
141void __init spear310_clk_init(void); 44void __init spear310_clk_init(void);
142 45
143#endif /* CONFIG_MACH_SPEAR310 */ 46#endif /* CONFIG_MACH_SPEAR310 */
144 47
145/* spear320 declarations */ 48/* spear320 declarations */
146#ifdef CONFIG_MACH_SPEAR320 49#ifdef CONFIG_MACH_SPEAR320
147/* pad mux modes */
148extern struct pmx_mode spear320_auto_net_smii_mode;
149extern struct pmx_mode spear320_auto_net_mii_mode;
150extern struct pmx_mode spear320_auto_exp_mode;
151extern struct pmx_mode spear320_small_printers_mode;
152
153/* pad mux devices */
154extern struct pmx_dev spear320_pmx_clcd;
155extern struct pmx_dev spear320_pmx_emi;
156extern struct pmx_dev spear320_pmx_fsmc;
157extern struct pmx_dev spear320_pmx_spp;
158extern struct pmx_dev spear320_pmx_sdhci;
159extern struct pmx_dev spear320_pmx_i2s;
160extern struct pmx_dev spear320_pmx_uart1;
161extern struct pmx_dev spear320_pmx_uart1_modem;
162extern struct pmx_dev spear320_pmx_uart2;
163extern struct pmx_dev spear320_pmx_touchscreen;
164extern struct pmx_dev spear320_pmx_can;
165extern struct pmx_dev spear320_pmx_sdhci_led;
166extern struct pmx_dev spear320_pmx_pwm0;
167extern struct pmx_dev spear320_pmx_pwm1;
168extern struct pmx_dev spear320_pmx_pwm2;
169extern struct pmx_dev spear320_pmx_pwm3;
170extern struct pmx_dev spear320_pmx_ssp1;
171extern struct pmx_dev spear320_pmx_ssp2;
172extern struct pmx_dev spear320_pmx_mii1;
173extern struct pmx_dev spear320_pmx_smii0;
174extern struct pmx_dev spear320_pmx_smii1;
175extern struct pmx_dev spear320_pmx_i2c1;
176
177/* Add spear320 machine declarations here */
178void __init spear320_clk_init(void); 50void __init spear320_clk_init(void);
179 51
180#endif /* CONFIG_MACH_SPEAR320 */ 52#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index febcdd8d4e92..f75fe25a620c 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -60,357 +60,6 @@
60/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ 60/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
61#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 61#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
62 62
63/* pad multiplexing support */
64/* muxing registers */
65#define PAD_MUX_CONFIG_REG 0x00
66#define MODE_CONFIG_REG 0x04
67
68/* modes */
69#define NAND_MODE (1 << 0)
70#define NOR_MODE (1 << 1)
71#define PHOTO_FRAME_MODE (1 << 2)
72#define LEND_IP_PHONE_MODE (1 << 3)
73#define HEND_IP_PHONE_MODE (1 << 4)
74#define LEND_WIFI_PHONE_MODE (1 << 5)
75#define HEND_WIFI_PHONE_MODE (1 << 6)
76#define ATA_PABX_WI2S_MODE (1 << 7)
77#define ATA_PABX_I2S_MODE (1 << 8)
78#define CAML_LCDW_MODE (1 << 9)
79#define CAMU_LCD_MODE (1 << 10)
80#define CAMU_WLCD_MODE (1 << 11)
81#define CAML_LCD_MODE (1 << 12)
82#define ALL_MODES 0x1FFF
83
84struct pmx_mode spear300_nand_mode = {
85 .id = NAND_MODE,
86 .name = "nand mode",
87 .mask = 0x00,
88};
89
90struct pmx_mode spear300_nor_mode = {
91 .id = NOR_MODE,
92 .name = "nor mode",
93 .mask = 0x01,
94};
95
96struct pmx_mode spear300_photo_frame_mode = {
97 .id = PHOTO_FRAME_MODE,
98 .name = "photo frame mode",
99 .mask = 0x02,
100};
101
102struct pmx_mode spear300_lend_ip_phone_mode = {
103 .id = LEND_IP_PHONE_MODE,
104 .name = "lend ip phone mode",
105 .mask = 0x03,
106};
107
108struct pmx_mode spear300_hend_ip_phone_mode = {
109 .id = HEND_IP_PHONE_MODE,
110 .name = "hend ip phone mode",
111 .mask = 0x04,
112};
113
114struct pmx_mode spear300_lend_wifi_phone_mode = {
115 .id = LEND_WIFI_PHONE_MODE,
116 .name = "lend wifi phone mode",
117 .mask = 0x05,
118};
119
120struct pmx_mode spear300_hend_wifi_phone_mode = {
121 .id = HEND_WIFI_PHONE_MODE,
122 .name = "hend wifi phone mode",
123 .mask = 0x06,
124};
125
126struct pmx_mode spear300_ata_pabx_wi2s_mode = {
127 .id = ATA_PABX_WI2S_MODE,
128 .name = "ata pabx wi2s mode",
129 .mask = 0x07,
130};
131
132struct pmx_mode spear300_ata_pabx_i2s_mode = {
133 .id = ATA_PABX_I2S_MODE,
134 .name = "ata pabx i2s mode",
135 .mask = 0x08,
136};
137
138struct pmx_mode spear300_caml_lcdw_mode = {
139 .id = CAML_LCDW_MODE,
140 .name = "caml lcdw mode",
141 .mask = 0x0C,
142};
143
144struct pmx_mode spear300_camu_lcd_mode = {
145 .id = CAMU_LCD_MODE,
146 .name = "camu lcd mode",
147 .mask = 0x0D,
148};
149
150struct pmx_mode spear300_camu_wlcd_mode = {
151 .id = CAMU_WLCD_MODE,
152 .name = "camu wlcd mode",
153 .mask = 0x0E,
154};
155
156struct pmx_mode spear300_caml_lcd_mode = {
157 .id = CAML_LCD_MODE,
158 .name = "caml lcd mode",
159 .mask = 0x0F,
160};
161
162/* devices */
163static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
164 {
165 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
166 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
167 .mask = PMX_FIRDA_MASK,
168 },
169};
170
171struct pmx_dev spear300_pmx_fsmc_2_chips = {
172 .name = "fsmc_2_chips",
173 .modes = pmx_fsmc_2_chips_modes,
174 .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
175 .enb_on_reset = 1,
176};
177
178static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
179 {
180 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
181 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
182 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
183 },
184};
185
186struct pmx_dev spear300_pmx_fsmc_4_chips = {
187 .name = "fsmc_4_chips",
188 .modes = pmx_fsmc_4_chips_modes,
189 .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
190 .enb_on_reset = 1,
191};
192
193static struct pmx_dev_mode pmx_keyboard_modes[] = {
194 {
195 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
196 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
197 CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
198 CAML_LCD_MODE,
199 .mask = 0x0,
200 },
201};
202
203struct pmx_dev spear300_pmx_keyboard = {
204 .name = "keyboard",
205 .modes = pmx_keyboard_modes,
206 .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
207 .enb_on_reset = 1,
208};
209
210static struct pmx_dev_mode pmx_clcd_modes[] = {
211 {
212 .ids = PHOTO_FRAME_MODE,
213 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
214 }, {
215 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
216 CAMU_LCD_MODE | CAML_LCD_MODE,
217 .mask = PMX_TIMER_3_4_MASK,
218 },
219};
220
221struct pmx_dev spear300_pmx_clcd = {
222 .name = "clcd",
223 .modes = pmx_clcd_modes,
224 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
225 .enb_on_reset = 1,
226};
227
228static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
229 {
230 .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
231 .mask = PMX_MII_MASK,
232 }, {
233 .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
234 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
235 }, {
236 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
237 .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
238 }, {
239 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
240 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
241 }, {
242 .ids = ATA_PABX_WI2S_MODE,
243 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
244 | PMX_UART0_MODEM_MASK,
245 },
246};
247
248struct pmx_dev spear300_pmx_telecom_gpio = {
249 .name = "telecom_gpio",
250 .modes = pmx_telecom_gpio_modes,
251 .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
252 .enb_on_reset = 1,
253};
254
255static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
256 {
257 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
258 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
259 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
260 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
261 | CAMU_WLCD_MODE | CAML_LCD_MODE,
262 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
263 },
264};
265
266struct pmx_dev spear300_pmx_telecom_tdm = {
267 .name = "telecom_tdm",
268 .modes = pmx_telecom_tdm_modes,
269 .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
270 .enb_on_reset = 1,
271};
272
273static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
274 {
275 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
276 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
277 | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
278 CAML_LCDW_MODE | CAML_LCD_MODE,
279 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
280 },
281};
282
283struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
284 .name = "telecom_spi_cs_i2c_clk",
285 .modes = pmx_telecom_spi_cs_i2c_clk_modes,
286 .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
287 .enb_on_reset = 1,
288};
289
290static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
291 {
292 .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
293 .mask = PMX_MII_MASK,
294 }, {
295 .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
296 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
297 },
298};
299
300struct pmx_dev spear300_pmx_telecom_camera = {
301 .name = "telecom_camera",
302 .modes = pmx_telecom_camera_modes,
303 .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
304 .enb_on_reset = 1,
305};
306
307static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
308 {
309 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
310 | CAMU_WLCD_MODE | CAML_LCD_MODE,
311 .mask = PMX_TIMER_1_2_MASK,
312 },
313};
314
315struct pmx_dev spear300_pmx_telecom_dac = {
316 .name = "telecom_dac",
317 .modes = pmx_telecom_dac_modes,
318 .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
319 .enb_on_reset = 1,
320};
321
322static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
323 {
324 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
325 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
326 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
327 | CAMU_WLCD_MODE | CAML_LCD_MODE,
328 .mask = PMX_UART0_MODEM_MASK,
329 },
330};
331
332struct pmx_dev spear300_pmx_telecom_i2s = {
333 .name = "telecom_i2s",
334 .modes = pmx_telecom_i2s_modes,
335 .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
336 .enb_on_reset = 1,
337};
338
339static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
340 {
341 .ids = NAND_MODE | NOR_MODE,
342 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
343 PMX_TIMER_3_4_MASK,
344 },
345};
346
347struct pmx_dev spear300_pmx_telecom_boot_pins = {
348 .name = "telecom_boot_pins",
349 .modes = pmx_telecom_boot_pins_modes,
350 .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
351 .enb_on_reset = 1,
352};
353
354static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
355 {
356 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
357 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
358 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
359 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
360 ATA_PABX_I2S_MODE,
361 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
362 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
363 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
364 },
365};
366
367struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
368 .name = "telecom_sdhci_4bit",
369 .modes = pmx_telecom_sdhci_4bit_modes,
370 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
371 .enb_on_reset = 1,
372};
373
374static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
375 {
376 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
377 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
378 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
379 CAMU_WLCD_MODE | CAML_LCD_MODE,
380 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
381 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
382 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
383 },
384};
385
386struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
387 .name = "telecom_sdhci_8bit",
388 .modes = pmx_telecom_sdhci_8bit_modes,
389 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
390 .enb_on_reset = 1,
391};
392
393static struct pmx_dev_mode pmx_gpio1_modes[] = {
394 {
395 .ids = PHOTO_FRAME_MODE,
396 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
397 PMX_TIMER_3_4_MASK,
398 },
399};
400
401struct pmx_dev spear300_pmx_gpio1 = {
402 .name = "arm gpio1",
403 .modes = pmx_gpio1_modes,
404 .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
405 .enb_on_reset = 1,
406};
407
408/* pmx driver structure */
409static struct pmx_driver pmx_driver = {
410 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
411 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
412};
413
414/* spear3xx shared irq */ 63/* spear3xx shared irq */
415static struct shirq_dev_config shirq_ras1_config[] = { 64static struct shirq_dev_config shirq_ras1_config[] = {
416 { 65 {
@@ -464,22 +113,6 @@ static struct spear_shirq shirq_ras1 = {
464 }, 113 },
465}; 114};
466 115
467/* padmux devices to enable */
468static struct pmx_dev *spear300_evb_pmx_devs[] = {
469 /* spear3xx specific devices */
470 &spear3xx_pmx_i2c,
471 &spear3xx_pmx_ssp_cs,
472 &spear3xx_pmx_ssp,
473 &spear3xx_pmx_mii,
474 &spear3xx_pmx_uart0,
475
476 /* spear300 specific devices */
477 &spear300_pmx_fsmc_2_chips,
478 &spear300_pmx_clcd,
479 &spear300_pmx_telecom_sdhci_4bit,
480 &spear300_pmx_gpio1,
481};
482
483/* DMAC platform data's slave info */ 116/* DMAC platform data's slave info */
484struct pl08x_channel_data spear300_dma_info[] = { 117struct pl08x_channel_data spear300_dma_info[] = {
485 { 118 {
@@ -678,7 +311,7 @@ static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
678 311
679static void __init spear300_dt_init(void) 312static void __init spear300_dt_init(void)
680{ 313{
681 int ret = -EINVAL; 314 int ret;
682 315
683 pl080_plat_data.slave_channels = spear300_dma_info; 316 pl080_plat_data.slave_channels = spear300_dma_info;
684 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info); 317 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
@@ -693,26 +326,6 @@ static void __init spear300_dt_init(void)
693 if (ret) 326 if (ret)
694 pr_err("Error registering Shared IRQ\n"); 327 pr_err("Error registering Shared IRQ\n");
695 } 328 }
696
697 if (of_machine_is_compatible("st,spear300-evb")) {
698 /* pmx initialization */
699 pmx_driver.mode = &spear300_photo_frame_mode;
700 pmx_driver.devs = spear300_evb_pmx_devs;
701 pmx_driver.devs_count = ARRAY_SIZE(spear300_evb_pmx_devs);
702
703 pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
704 if (pmx_driver.base) {
705 ret = pmx_register(&pmx_driver);
706 if (ret)
707 pr_err("padmux: registration failed. err no: %d\n",
708 ret);
709 /* Free Mapping, device selection already done */
710 iounmap(pmx_driver.base);
711 }
712
713 if (ret)
714 pr_err("Initialization Failed");
715 }
716} 329}
717 330
718static const char * const spear300_dt_board_compat[] = { 331static const char * const spear300_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index b26e41566b50..f0842a58dc02 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -82,128 +82,6 @@
82#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17) 82#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
83 83
84 84
85/* pad multiplexing support */
86/* muxing registers */
87#define PAD_MUX_CONFIG_REG 0x08
88
89/* devices */
90static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
91 {
92 .ids = 0x00,
93 .mask = PMX_TIMER_3_4_MASK,
94 },
95};
96
97struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
98 .name = "emi_cs_0_1_4_5",
99 .modes = pmx_emi_cs_0_1_4_5_modes,
100 .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
101 .enb_on_reset = 1,
102};
103
104static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
105 {
106 .ids = 0x00,
107 .mask = PMX_TIMER_1_2_MASK,
108 },
109};
110
111struct pmx_dev spear310_pmx_emi_cs_2_3 = {
112 .name = "emi_cs_2_3",
113 .modes = pmx_emi_cs_2_3_modes,
114 .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
115 .enb_on_reset = 1,
116};
117
118static struct pmx_dev_mode pmx_uart1_modes[] = {
119 {
120 .ids = 0x00,
121 .mask = PMX_FIRDA_MASK,
122 },
123};
124
125struct pmx_dev spear310_pmx_uart1 = {
126 .name = "uart1",
127 .modes = pmx_uart1_modes,
128 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
129 .enb_on_reset = 1,
130};
131
132static struct pmx_dev_mode pmx_uart2_modes[] = {
133 {
134 .ids = 0x00,
135 .mask = PMX_TIMER_1_2_MASK,
136 },
137};
138
139struct pmx_dev spear310_pmx_uart2 = {
140 .name = "uart2",
141 .modes = pmx_uart2_modes,
142 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
143 .enb_on_reset = 1,
144};
145
146static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
147 {
148 .ids = 0x00,
149 .mask = PMX_UART0_MODEM_MASK,
150 },
151};
152
153struct pmx_dev spear310_pmx_uart3_4_5 = {
154 .name = "uart3_4_5",
155 .modes = pmx_uart3_4_5_modes,
156 .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
157 .enb_on_reset = 1,
158};
159
160static struct pmx_dev_mode pmx_fsmc_modes[] = {
161 {
162 .ids = 0x00,
163 .mask = PMX_SSP_CS_MASK,
164 },
165};
166
167struct pmx_dev spear310_pmx_fsmc = {
168 .name = "fsmc",
169 .modes = pmx_fsmc_modes,
170 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
171 .enb_on_reset = 1,
172};
173
174static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
175 {
176 .ids = 0x00,
177 .mask = PMX_MII_MASK,
178 },
179};
180
181struct pmx_dev spear310_pmx_rs485_0_1 = {
182 .name = "rs485_0_1",
183 .modes = pmx_rs485_0_1_modes,
184 .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
185 .enb_on_reset = 1,
186};
187
188static struct pmx_dev_mode pmx_tdm0_modes[] = {
189 {
190 .ids = 0x00,
191 .mask = PMX_MII_MASK,
192 },
193};
194
195struct pmx_dev spear310_pmx_tdm0 = {
196 .name = "tdm0",
197 .modes = pmx_tdm0_modes,
198 .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
199 .enb_on_reset = 1,
200};
201
202/* pmx driver structure */
203static struct pmx_driver pmx_driver = {
204 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
205};
206
207/* spear3xx shared irq */ 85/* spear3xx shared irq */
208static struct shirq_dev_config shirq_ras1_config[] = { 86static struct shirq_dev_config shirq_ras1_config[] = {
209 { 87 {
@@ -320,30 +198,6 @@ static struct spear_shirq shirq_intrcomm_ras = {
320 }, 198 },
321}; 199};
322 200
323/* padmux devices to enable */
324static struct pmx_dev *spear310_evb_pmx_devs[] = {
325 /* spear3xx specific devices */
326 &spear3xx_pmx_i2c,
327 &spear3xx_pmx_ssp,
328 &spear3xx_pmx_gpio_pin0,
329 &spear3xx_pmx_gpio_pin1,
330 &spear3xx_pmx_gpio_pin2,
331 &spear3xx_pmx_gpio_pin3,
332 &spear3xx_pmx_gpio_pin4,
333 &spear3xx_pmx_gpio_pin5,
334 &spear3xx_pmx_uart0,
335
336 /* spear310 specific devices */
337 &spear310_pmx_emi_cs_0_1_4_5,
338 &spear310_pmx_emi_cs_2_3,
339 &spear310_pmx_uart1,
340 &spear310_pmx_uart2,
341 &spear310_pmx_uart3_4_5,
342 &spear310_pmx_fsmc,
343 &spear310_pmx_rs485_0_1,
344 &spear310_pmx_tdm0,
345};
346
347/* DMAC platform data's slave info */ 201/* DMAC platform data's slave info */
348struct pl08x_channel_data spear310_dma_info[] = { 202struct pl08x_channel_data spear310_dma_info[] = {
349 { 203 {
@@ -578,7 +432,7 @@ static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
578static void __init spear310_dt_init(void) 432static void __init spear310_dt_init(void)
579{ 433{
580 void __iomem *base; 434 void __iomem *base;
581 int ret = 0; 435 int ret;
582 436
583 pl080_plat_data.slave_channels = spear310_dma_info; 437 pl080_plat_data.slave_channels = spear310_dma_info;
584 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info); 438 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
@@ -613,19 +467,6 @@ static void __init spear310_dt_init(void)
613 if (ret) 467 if (ret)
614 pr_err("Error registering Shared IRQ 4\n"); 468 pr_err("Error registering Shared IRQ 4\n");
615 } 469 }
616
617 if (of_machine_is_compatible("st,spear310-evb")) {
618 /* pmx initialization */
619 pmx_driver.base = base;
620 pmx_driver.mode = NULL;
621 pmx_driver.devs = spear310_evb_pmx_devs;
622 pmx_driver.devs_count = ARRAY_SIZE(spear310_evb_pmx_devs);
623
624 ret = pmx_register(&pmx_driver);
625 if (ret)
626 pr_err("padmux: registration failed. err no: %d\n",
627 ret);
628 }
629} 470}
630 471
631static const char * const spear310_dt_board_compat[] = { 472static const char * const spear310_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 2f5979b0c169..e8caeef50a5c 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -83,373 +83,6 @@
83#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15) 83#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
84#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16) 84#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
85 85
86/* pad multiplexing support */
87/* muxing registers */
88#define PAD_MUX_CONFIG_REG 0x0C
89#define MODE_CONFIG_REG 0x10
90
91/* modes */
92#define AUTO_NET_SMII_MODE (1 << 0)
93#define AUTO_NET_MII_MODE (1 << 1)
94#define AUTO_EXP_MODE (1 << 2)
95#define SMALL_PRINTERS_MODE (1 << 3)
96#define ALL_MODES 0xF
97
98struct pmx_mode spear320_auto_net_smii_mode = {
99 .id = AUTO_NET_SMII_MODE,
100 .name = "Automation Networking SMII Mode",
101 .mask = 0x00,
102};
103
104struct pmx_mode spear320_auto_net_mii_mode = {
105 .id = AUTO_NET_MII_MODE,
106 .name = "Automation Networking MII Mode",
107 .mask = 0x01,
108};
109
110struct pmx_mode spear320_auto_exp_mode = {
111 .id = AUTO_EXP_MODE,
112 .name = "Automation Expanded Mode",
113 .mask = 0x02,
114};
115
116struct pmx_mode spear320_small_printers_mode = {
117 .id = SMALL_PRINTERS_MODE,
118 .name = "Small Printers Mode",
119 .mask = 0x03,
120};
121
122/* devices */
123static struct pmx_dev_mode pmx_clcd_modes[] = {
124 {
125 .ids = AUTO_NET_SMII_MODE,
126 .mask = 0x0,
127 },
128};
129
130struct pmx_dev spear320_pmx_clcd = {
131 .name = "clcd",
132 .modes = pmx_clcd_modes,
133 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
134 .enb_on_reset = 1,
135};
136
137static struct pmx_dev_mode pmx_emi_modes[] = {
138 {
139 .ids = AUTO_EXP_MODE,
140 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
141 },
142};
143
144struct pmx_dev spear320_pmx_emi = {
145 .name = "emi",
146 .modes = pmx_emi_modes,
147 .mode_count = ARRAY_SIZE(pmx_emi_modes),
148 .enb_on_reset = 1,
149};
150
151static struct pmx_dev_mode pmx_fsmc_modes[] = {
152 {
153 .ids = ALL_MODES,
154 .mask = 0x0,
155 },
156};
157
158struct pmx_dev spear320_pmx_fsmc = {
159 .name = "fsmc",
160 .modes = pmx_fsmc_modes,
161 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
162 .enb_on_reset = 1,
163};
164
165static struct pmx_dev_mode pmx_spp_modes[] = {
166 {
167 .ids = SMALL_PRINTERS_MODE,
168 .mask = 0x0,
169 },
170};
171
172struct pmx_dev spear320_pmx_spp = {
173 .name = "spp",
174 .modes = pmx_spp_modes,
175 .mode_count = ARRAY_SIZE(pmx_spp_modes),
176 .enb_on_reset = 1,
177};
178
179static struct pmx_dev_mode pmx_sdhci_modes[] = {
180 {
181 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
182 SMALL_PRINTERS_MODE,
183 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
184 },
185};
186
187struct pmx_dev spear320_pmx_sdhci = {
188 .name = "sdhci",
189 .modes = pmx_sdhci_modes,
190 .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
191 .enb_on_reset = 1,
192};
193
194static struct pmx_dev_mode pmx_i2s_modes[] = {
195 {
196 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
197 .mask = PMX_UART0_MODEM_MASK,
198 },
199};
200
201struct pmx_dev spear320_pmx_i2s = {
202 .name = "i2s",
203 .modes = pmx_i2s_modes,
204 .mode_count = ARRAY_SIZE(pmx_i2s_modes),
205 .enb_on_reset = 1,
206};
207
208static struct pmx_dev_mode pmx_uart1_modes[] = {
209 {
210 .ids = ALL_MODES,
211 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
212 },
213};
214
215struct pmx_dev spear320_pmx_uart1 = {
216 .name = "uart1",
217 .modes = pmx_uart1_modes,
218 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
219 .enb_on_reset = 1,
220};
221
222static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
223 {
224 .ids = AUTO_EXP_MODE,
225 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
226 PMX_SSP_CS_MASK,
227 }, {
228 .ids = SMALL_PRINTERS_MODE,
229 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
230 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
231 },
232};
233
234struct pmx_dev spear320_pmx_uart1_modem = {
235 .name = "uart1_modem",
236 .modes = pmx_uart1_modem_modes,
237 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
238 .enb_on_reset = 1,
239};
240
241static struct pmx_dev_mode pmx_uart2_modes[] = {
242 {
243 .ids = ALL_MODES,
244 .mask = PMX_FIRDA_MASK,
245 },
246};
247
248struct pmx_dev spear320_pmx_uart2 = {
249 .name = "uart2",
250 .modes = pmx_uart2_modes,
251 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
252 .enb_on_reset = 1,
253};
254
255static struct pmx_dev_mode pmx_touchscreen_modes[] = {
256 {
257 .ids = AUTO_NET_SMII_MODE,
258 .mask = PMX_SSP_CS_MASK,
259 },
260};
261
262struct pmx_dev spear320_pmx_touchscreen = {
263 .name = "touchscreen",
264 .modes = pmx_touchscreen_modes,
265 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
266 .enb_on_reset = 1,
267};
268
269static struct pmx_dev_mode pmx_can_modes[] = {
270 {
271 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
272 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
273 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
274 },
275};
276
277struct pmx_dev spear320_pmx_can = {
278 .name = "can",
279 .modes = pmx_can_modes,
280 .mode_count = ARRAY_SIZE(pmx_can_modes),
281 .enb_on_reset = 1,
282};
283
284static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
285 {
286 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
287 .mask = PMX_SSP_CS_MASK,
288 },
289};
290
291struct pmx_dev spear320_pmx_sdhci_led = {
292 .name = "sdhci_led",
293 .modes = pmx_sdhci_led_modes,
294 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
295 .enb_on_reset = 1,
296};
297
298static struct pmx_dev_mode pmx_pwm0_modes[] = {
299 {
300 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
301 .mask = PMX_UART0_MODEM_MASK,
302 }, {
303 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
304 .mask = PMX_MII_MASK,
305 },
306};
307
308struct pmx_dev spear320_pmx_pwm0 = {
309 .name = "pwm0",
310 .modes = pmx_pwm0_modes,
311 .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
312 .enb_on_reset = 1,
313};
314
315static struct pmx_dev_mode pmx_pwm1_modes[] = {
316 {
317 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
318 .mask = PMX_UART0_MODEM_MASK,
319 }, {
320 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
321 .mask = PMX_MII_MASK,
322 },
323};
324
325struct pmx_dev spear320_pmx_pwm1 = {
326 .name = "pwm1",
327 .modes = pmx_pwm1_modes,
328 .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
329 .enb_on_reset = 1,
330};
331
332static struct pmx_dev_mode pmx_pwm2_modes[] = {
333 {
334 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
335 .mask = PMX_SSP_CS_MASK,
336 }, {
337 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
338 .mask = PMX_MII_MASK,
339 },
340};
341
342struct pmx_dev spear320_pmx_pwm2 = {
343 .name = "pwm2",
344 .modes = pmx_pwm2_modes,
345 .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
346 .enb_on_reset = 1,
347};
348
349static struct pmx_dev_mode pmx_pwm3_modes[] = {
350 {
351 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
352 .mask = PMX_MII_MASK,
353 },
354};
355
356struct pmx_dev spear320_pmx_pwm3 = {
357 .name = "pwm3",
358 .modes = pmx_pwm3_modes,
359 .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
360 .enb_on_reset = 1,
361};
362
363static struct pmx_dev_mode pmx_ssp1_modes[] = {
364 {
365 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
366 .mask = PMX_MII_MASK,
367 },
368};
369
370struct pmx_dev spear320_pmx_ssp1 = {
371 .name = "ssp1",
372 .modes = pmx_ssp1_modes,
373 .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
374 .enb_on_reset = 1,
375};
376
377static struct pmx_dev_mode pmx_ssp2_modes[] = {
378 {
379 .ids = AUTO_NET_SMII_MODE,
380 .mask = PMX_MII_MASK,
381 },
382};
383
384struct pmx_dev spear320_pmx_ssp2 = {
385 .name = "ssp2",
386 .modes = pmx_ssp2_modes,
387 .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
388 .enb_on_reset = 1,
389};
390
391static struct pmx_dev_mode pmx_mii1_modes[] = {
392 {
393 .ids = AUTO_NET_MII_MODE,
394 .mask = 0x0,
395 },
396};
397
398struct pmx_dev spear320_pmx_mii1 = {
399 .name = "mii1",
400 .modes = pmx_mii1_modes,
401 .mode_count = ARRAY_SIZE(pmx_mii1_modes),
402 .enb_on_reset = 1,
403};
404
405static struct pmx_dev_mode pmx_smii0_modes[] = {
406 {
407 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
408 .mask = PMX_MII_MASK,
409 },
410};
411
412struct pmx_dev spear320_pmx_smii0 = {
413 .name = "smii0",
414 .modes = pmx_smii0_modes,
415 .mode_count = ARRAY_SIZE(pmx_smii0_modes),
416 .enb_on_reset = 1,
417};
418
419static struct pmx_dev_mode pmx_smii1_modes[] = {
420 {
421 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
422 .mask = PMX_MII_MASK,
423 },
424};
425
426struct pmx_dev spear320_pmx_smii1 = {
427 .name = "smii1",
428 .modes = pmx_smii1_modes,
429 .mode_count = ARRAY_SIZE(pmx_smii1_modes),
430 .enb_on_reset = 1,
431};
432
433static struct pmx_dev_mode pmx_i2c1_modes[] = {
434 {
435 .ids = AUTO_EXP_MODE,
436 .mask = 0x0,
437 },
438};
439
440struct pmx_dev spear320_pmx_i2c1 = {
441 .name = "i2c1",
442 .modes = pmx_i2c1_modes,
443 .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
444 .enb_on_reset = 1,
445};
446
447/* pmx driver structure */
448static struct pmx_driver pmx_driver = {
449 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
450 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
451};
452
453/* spear3xx shared irq */ 86/* spear3xx shared irq */
454static struct shirq_dev_config shirq_ras1_config[] = { 87static struct shirq_dev_config shirq_ras1_config[] = {
455 { 88 {
@@ -574,27 +207,6 @@ static struct spear_shirq shirq_intrcomm_ras = {
574 }, 207 },
575}; 208};
576 209
577/* padmux devices to enable */
578static struct pmx_dev *spear320_evb_pmx_devs[] = {
579 /* spear3xx specific devices */
580 &spear3xx_pmx_i2c,
581 &spear3xx_pmx_ssp,
582 &spear3xx_pmx_mii,
583 &spear3xx_pmx_uart0,
584
585 /* spear320 specific devices */
586 &spear320_pmx_fsmc,
587 &spear320_pmx_sdhci,
588 &spear320_pmx_i2s,
589 &spear320_pmx_uart1,
590 &spear320_pmx_uart2,
591 &spear320_pmx_can,
592 &spear320_pmx_pwm0,
593 &spear320_pmx_pwm1,
594 &spear320_pmx_pwm2,
595 &spear320_pmx_mii1,
596};
597
598/* DMAC platform data's slave info */ 210/* DMAC platform data's slave info */
599struct pl08x_channel_data spear320_dma_info[] = { 211struct pl08x_channel_data spear320_dma_info[] = {
600 { 212 {
@@ -832,7 +444,7 @@ static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
832static void __init spear320_dt_init(void) 444static void __init spear320_dt_init(void)
833{ 445{
834 void __iomem *base; 446 void __iomem *base;
835 int ret = 0; 447 int ret;
836 448
837 pl080_plat_data.slave_channels = spear320_dma_info; 449 pl080_plat_data.slave_channels = spear320_dma_info;
838 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); 450 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
@@ -861,19 +473,6 @@ static void __init spear320_dt_init(void)
861 if (ret) 473 if (ret)
862 pr_err("Error registering Shared IRQ 4\n"); 474 pr_err("Error registering Shared IRQ 4\n");
863 } 475 }
864
865 if (of_machine_is_compatible("st,spear320-evb")) {
866 /* pmx initialization */
867 pmx_driver.base = base;
868 pmx_driver.mode = &spear320_auto_net_mii_mode;
869 pmx_driver.devs = spear320_evb_pmx_devs;
870 pmx_driver.devs_count = ARRAY_SIZE(spear320_evb_pmx_devs);
871
872 ret = pmx_register(&pmx_driver);
873 if (ret)
874 pr_err("padmux: registration failed. err no: %d\n",
875 ret);
876 }
877} 476}
878 477
879static const char * const spear320_dt_board_compat[] = { 478static const char * const spear320_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index bbb11efa6056..826ac20ef1e7 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -23,431 +23,6 @@
23#include <mach/generic.h> 23#include <mach/generic.h>
24#include <mach/spear.h> 24#include <mach/spear.h>
25 25
26/* pad multiplexing support */
27/* devices */
28static struct pmx_dev_mode pmx_firda_modes[] = {
29 {
30 .ids = 0xffffffff,
31 .mask = PMX_FIRDA_MASK,
32 },
33};
34
35struct pmx_dev spear3xx_pmx_firda = {
36 .name = "firda",
37 .modes = pmx_firda_modes,
38 .mode_count = ARRAY_SIZE(pmx_firda_modes),
39 .enb_on_reset = 0,
40};
41
42static struct pmx_dev_mode pmx_i2c_modes[] = {
43 {
44 .ids = 0xffffffff,
45 .mask = PMX_I2C_MASK,
46 },
47};
48
49struct pmx_dev spear3xx_pmx_i2c = {
50 .name = "i2c",
51 .modes = pmx_i2c_modes,
52 .mode_count = ARRAY_SIZE(pmx_i2c_modes),
53 .enb_on_reset = 0,
54};
55
56static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
57 {
58 .ids = 0xffffffff,
59 .mask = PMX_SSP_CS_MASK,
60 },
61};
62
63struct pmx_dev spear3xx_pmx_ssp_cs = {
64 .name = "ssp_chip_selects",
65 .modes = pmx_ssp_cs_modes,
66 .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
67 .enb_on_reset = 0,
68};
69
70static struct pmx_dev_mode pmx_ssp_modes[] = {
71 {
72 .ids = 0xffffffff,
73 .mask = PMX_SSP_MASK,
74 },
75};
76
77struct pmx_dev spear3xx_pmx_ssp = {
78 .name = "ssp",
79 .modes = pmx_ssp_modes,
80 .mode_count = ARRAY_SIZE(pmx_ssp_modes),
81 .enb_on_reset = 0,
82};
83
84static struct pmx_dev_mode pmx_mii_modes[] = {
85 {
86 .ids = 0xffffffff,
87 .mask = PMX_MII_MASK,
88 },
89};
90
91struct pmx_dev spear3xx_pmx_mii = {
92 .name = "mii",
93 .modes = pmx_mii_modes,
94 .mode_count = ARRAY_SIZE(pmx_mii_modes),
95 .enb_on_reset = 0,
96};
97
98static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
99 {
100 .ids = 0xffffffff,
101 .mask = PMX_GPIO_PIN0_MASK,
102 },
103};
104
105struct pmx_dev spear3xx_pmx_gpio_pin0 = {
106 .name = "gpio_pin0",
107 .modes = pmx_gpio_pin0_modes,
108 .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
109 .enb_on_reset = 0,
110};
111
112static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
113 {
114 .ids = 0xffffffff,
115 .mask = PMX_GPIO_PIN1_MASK,
116 },
117};
118
119struct pmx_dev spear3xx_pmx_gpio_pin1 = {
120 .name = "gpio_pin1",
121 .modes = pmx_gpio_pin1_modes,
122 .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
123 .enb_on_reset = 0,
124};
125
126static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
127 {
128 .ids = 0xffffffff,
129 .mask = PMX_GPIO_PIN2_MASK,
130 },
131};
132
133struct pmx_dev spear3xx_pmx_gpio_pin2 = {
134 .name = "gpio_pin2",
135 .modes = pmx_gpio_pin2_modes,
136 .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
137 .enb_on_reset = 0,
138};
139
140static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
141 {
142 .ids = 0xffffffff,
143 .mask = PMX_GPIO_PIN3_MASK,
144 },
145};
146
147struct pmx_dev spear3xx_pmx_gpio_pin3 = {
148 .name = "gpio_pin3",
149 .modes = pmx_gpio_pin3_modes,
150 .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
151 .enb_on_reset = 0,
152};
153
154static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
155 {
156 .ids = 0xffffffff,
157 .mask = PMX_GPIO_PIN4_MASK,
158 },
159};
160
161struct pmx_dev spear3xx_pmx_gpio_pin4 = {
162 .name = "gpio_pin4",
163 .modes = pmx_gpio_pin4_modes,
164 .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
165 .enb_on_reset = 0,
166};
167
168static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
169 {
170 .ids = 0xffffffff,
171 .mask = PMX_GPIO_PIN5_MASK,
172 },
173};
174
175struct pmx_dev spear3xx_pmx_gpio_pin5 = {
176 .name = "gpio_pin5",
177 .modes = pmx_gpio_pin5_modes,
178 .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
179 .enb_on_reset = 0,
180};
181
182static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
183 {
184 .ids = 0xffffffff,
185 .mask = PMX_UART0_MODEM_MASK,
186 },
187};
188
189struct pmx_dev spear3xx_pmx_uart0_modem = {
190 .name = "uart0_modem",
191 .modes = pmx_uart0_modem_modes,
192 .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
193 .enb_on_reset = 0,
194};
195
196static struct pmx_dev_mode pmx_uart0_modes[] = {
197 {
198 .ids = 0xffffffff,
199 .mask = PMX_UART0_MASK,
200 },
201};
202
203struct pmx_dev spear3xx_pmx_uart0 = {
204 .name = "uart0",
205 .modes = pmx_uart0_modes,
206 .mode_count = ARRAY_SIZE(pmx_uart0_modes),
207 .enb_on_reset = 0,
208};
209
210static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
211 {
212 .ids = 0xffffffff,
213 .mask = PMX_TIMER_3_4_MASK,
214 },
215};
216
217struct pmx_dev spear3xx_pmx_timer_3_4 = {
218 .name = "timer_3_4",
219 .modes = pmx_timer_3_4_modes,
220 .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
221 .enb_on_reset = 0,
222};
223
224static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
225 {
226 .ids = 0xffffffff,
227 .mask = PMX_TIMER_1_2_MASK,
228 },
229};
230
231struct pmx_dev spear3xx_pmx_timer_1_2 = {
232 .name = "timer_1_2",
233 .modes = pmx_timer_1_2_modes,
234 .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
235 .enb_on_reset = 0,
236};
237
238#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
239/* plgpios devices */
240static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
241 {
242 .ids = 0x00,
243 .mask = PMX_FIRDA_MASK,
244 },
245};
246
247struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
248 .name = "plgpio 0 and 1",
249 .modes = pmx_plgpio_0_1_modes,
250 .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
251 .enb_on_reset = 1,
252};
253
254static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
255 {
256 .ids = 0x00,
257 .mask = PMX_UART0_MASK,
258 },
259};
260
261struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
262 .name = "plgpio 2 and 3",
263 .modes = pmx_plgpio_2_3_modes,
264 .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
265 .enb_on_reset = 1,
266};
267
268static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
269 {
270 .ids = 0x00,
271 .mask = PMX_I2C_MASK,
272 },
273};
274
275struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
276 .name = "plgpio 4 and 5",
277 .modes = pmx_plgpio_4_5_modes,
278 .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
279 .enb_on_reset = 1,
280};
281
282static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
283 {
284 .ids = 0x00,
285 .mask = PMX_SSP_MASK,
286 },
287};
288
289struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
290 .name = "plgpio 6 to 9",
291 .modes = pmx_plgpio_6_9_modes,
292 .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
293 .enb_on_reset = 1,
294};
295
296static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
297 {
298 .ids = 0x00,
299 .mask = PMX_MII_MASK,
300 },
301};
302
303struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
304 .name = "plgpio 10 to 27",
305 .modes = pmx_plgpio_10_27_modes,
306 .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
307 .enb_on_reset = 1,
308};
309
310static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
311 {
312 .ids = 0x00,
313 .mask = PMX_GPIO_PIN0_MASK,
314 },
315};
316
317struct pmx_dev spear3xx_pmx_plgpio_28 = {
318 .name = "plgpio 28",
319 .modes = pmx_plgpio_28_modes,
320 .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
321 .enb_on_reset = 1,
322};
323
324static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
325 {
326 .ids = 0x00,
327 .mask = PMX_GPIO_PIN1_MASK,
328 },
329};
330
331struct pmx_dev spear3xx_pmx_plgpio_29 = {
332 .name = "plgpio 29",
333 .modes = pmx_plgpio_29_modes,
334 .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
335 .enb_on_reset = 1,
336};
337
338static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
339 {
340 .ids = 0x00,
341 .mask = PMX_GPIO_PIN2_MASK,
342 },
343};
344
345struct pmx_dev spear3xx_pmx_plgpio_30 = {
346 .name = "plgpio 30",
347 .modes = pmx_plgpio_30_modes,
348 .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
349 .enb_on_reset = 1,
350};
351
352static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
353 {
354 .ids = 0x00,
355 .mask = PMX_GPIO_PIN3_MASK,
356 },
357};
358
359struct pmx_dev spear3xx_pmx_plgpio_31 = {
360 .name = "plgpio 31",
361 .modes = pmx_plgpio_31_modes,
362 .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
363 .enb_on_reset = 1,
364};
365
366static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
367 {
368 .ids = 0x00,
369 .mask = PMX_GPIO_PIN4_MASK,
370 },
371};
372
373struct pmx_dev spear3xx_pmx_plgpio_32 = {
374 .name = "plgpio 32",
375 .modes = pmx_plgpio_32_modes,
376 .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
377 .enb_on_reset = 1,
378};
379
380static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
381 {
382 .ids = 0x00,
383 .mask = PMX_GPIO_PIN5_MASK,
384 },
385};
386
387struct pmx_dev spear3xx_pmx_plgpio_33 = {
388 .name = "plgpio 33",
389 .modes = pmx_plgpio_33_modes,
390 .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
391 .enb_on_reset = 1,
392};
393
394static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
395 {
396 .ids = 0x00,
397 .mask = PMX_SSP_CS_MASK,
398 },
399};
400
401struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
402 .name = "plgpio 34 to 36",
403 .modes = pmx_plgpio_34_36_modes,
404 .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
405 .enb_on_reset = 1,
406};
407
408static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
409 {
410 .ids = 0x00,
411 .mask = PMX_UART0_MODEM_MASK,
412 },
413};
414
415struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
416 .name = "plgpio 37 to 42",
417 .modes = pmx_plgpio_37_42_modes,
418 .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
419 .enb_on_reset = 1,
420};
421
422static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
423 {
424 .ids = 0x00,
425 .mask = PMX_TIMER_1_2_MASK,
426 },
427};
428
429struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
430 .name = "plgpio 43, 44, 47 and 48",
431 .modes = pmx_plgpio_43_44_47_48_modes,
432 .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
433 .enb_on_reset = 1,
434};
435
436static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
437 {
438 .ids = 0x00,
439 .mask = PMX_TIMER_3_4_MASK,
440 },
441};
442
443struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
444 .name = "plgpio 45, 46, 49 and 50",
445 .modes = pmx_plgpio_45_46_49_50_modes,
446 .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
447 .enb_on_reset = 1,
448};
449#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
450
451/* ssp device registration */ 26/* ssp device registration */
452struct pl022_ssp_controller pl022_plat_data = { 27struct pl022_ssp_controller pl022_plat_data = {
453 .bus_id = 0, 28 .bus_id = 0,
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index d87d968115ec..2eb4445ddb14 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -5,7 +5,6 @@ obj-y += io.o
5obj-y += irq.o 5obj-y += irq.o
6obj-y += clock.o 6obj-y += clock.o
7obj-y += timer.o 7obj-y += timer.o
8obj-y += pinmux.o
9obj-y += fuse.o 8obj-y += fuse.o
10obj-y += pmc.o 9obj-y += pmc.o
11obj-y += flowctrl.o 10obj-y += flowctrl.o
@@ -14,8 +13,6 @@ obj-$(CONFIG_CPU_IDLE) += sleep.o
14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o 13obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o 14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o 15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
17obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o
18obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o
19obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o 16obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
20obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o 17obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
21obj-$(CONFIG_SMP) += platsmp.o headsmp.o 18obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 72ae62003520..8351c4c147ad 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -46,15 +46,7 @@
46#include "clock.h" 46#include "clock.h"
47#include "devices.h" 47#include "devices.h"
48 48
49void harmony_pinmux_init(void);
50void paz00_pinmux_init(void);
51void seaboard_pinmux_init(void);
52void trimslice_pinmux_init(void);
53void ventana_pinmux_init(void);
54
55struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { 49struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
56 OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL),
57 OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL),
58 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), 50 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
59 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), 51 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
60 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL), 52 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
@@ -94,33 +86,10 @@ static struct of_device_id tegra_dt_match_table[] __initdata = {
94 {} 86 {}
95}; 87};
96 88
97static struct {
98 char *machine;
99 void (*init)(void);
100} pinmux_configs[] = {
101 { "compulab,trimslice", trimslice_pinmux_init },
102 { "nvidia,harmony", harmony_pinmux_init },
103 { "compal,paz00", paz00_pinmux_init },
104 { "nvidia,seaboard", seaboard_pinmux_init },
105 { "nvidia,ventana", ventana_pinmux_init },
106};
107
108static void __init tegra_dt_init(void) 89static void __init tegra_dt_init(void)
109{ 90{
110 int i;
111
112 tegra_clk_init_from_table(tegra_dt_clk_init_table); 91 tegra_clk_init_from_table(tegra_dt_clk_init_table);
113 92
114 for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
115 if (of_machine_is_compatible(pinmux_configs[i].machine)) {
116 pinmux_configs[i].init();
117 break;
118 }
119 }
120
121 WARN(i == ARRAY_SIZE(pinmux_configs),
122 "Unknown platform! Pinmuxing not initialized\n");
123
124 /* 93 /*
125 * Finished with the static registrations now; fill in the missing 94 * Finished with the static registrations now; fill in the missing
126 * devices 95 * devices
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 1af85bccc0f1..83d420fbc58c 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -2,6 +2,7 @@
2 * arch/arm/mach-tegra/board-harmony-pinmux.c 2 * arch/arm/mach-tegra/board-harmony-pinmux.c
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 8 * License version 2, as published by the Free Software Foundation, and
@@ -15,153 +16,138 @@
15 */ 16 */
16 17
17#include <linux/kernel.h> 18#include <linux/kernel.h>
18#include <linux/gpio.h>
19#include <linux/of.h>
20 19
21#include <mach/pinmux.h>
22#include <mach/pinmux-tegra20.h>
23
24#include "gpio-names.h"
25#include "board-harmony.h" 20#include "board-harmony.h"
26#include "board-pinmux.h" 21#include "board-pinmux.h"
27 22
28static struct tegra_pingroup_config harmony_pinmux[] = { 23static struct pinctrl_map harmony_map[] = {
29 {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 24 TEGRA_MAP_MUXCONF("ata", "ide", none, driven),
30 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 25 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
31 {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 26 TEGRA_MAP_MUXCONF("atc", "nand", none, driven),
32 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 27 TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
33 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 28 TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
34 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 29 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
35 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 30 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
36 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 31 TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
37 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 32 TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
38 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 33 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
39 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 34 TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
40 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 35 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
41 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 36 TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
42 {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 37 TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
43 {TEGRA_PINGROUP_DTA, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 38 TEGRA_MAP_MUXCONF("dta", "sdio2", up, driven),
44 {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 39 TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, driven),
45 {TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 40 TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
46 {TEGRA_PINGROUP_DTD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 41 TEGRA_MAP_MUXCONF("dtd", "sdio2", up, driven),
47 {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 42 TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
48 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 43 TEGRA_MAP_MUXCONF("dtf", "i2c3", none, tristate),
49 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 44 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
50 {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 45 TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
51 {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 46 TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven),
52 {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 47 TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
53 {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 48 TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
54 {TEGRA_PINGROUP_GPU, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 49 TEGRA_MAP_MUXCONF("gpu", "gmi", none, tristate),
55 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 50 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
56 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 51 TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
57 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 52 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
58 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 53 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
59 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 54 TEGRA_MAP_MUXCONF("irrx", "uarta", up, tristate),
60 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 55 TEGRA_MAP_MUXCONF("irtx", "uarta", up, tristate),
61 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 56 TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
62 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 57 TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven),
63 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 58 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
64 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 59 TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven),
65 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 60 TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
66 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 61 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
67 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 62 TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
68 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 63 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
69 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 64 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
70 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 65 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
71 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 66 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
72 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 67 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
73 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 68 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
74 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 69 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
75 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 70 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
76 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 71 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
77 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 72 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
78 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 73 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
79 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 74 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
80 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 75 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
81 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 76 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
82 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 77 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
83 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 78 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
84 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 79 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
85 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 80 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
86 {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 81 TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
87 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 82 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
88 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 83 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
89 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 84 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
90 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 85 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
91 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 86 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
92 {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 87 TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
93 {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 88 TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
94 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 89 TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
95 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 90 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
96 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 91 TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
97 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 92 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
98 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 93 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
99 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 94 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
100 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 95 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
101 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 96 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
102 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 97 TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
103 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 98 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
104 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 99 TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
105 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 100 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
106 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 101 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
107 {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 102 TEGRA_MAP_MUXCONF("owc", "rsvd2", na, tristate),
108 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 103 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
109 {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 104 TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
110 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 105 TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
111 {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 106 TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
112 {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 107 TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
113 {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 108 TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
114 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 109 TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, tristate),
115 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 110 TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
116 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 111 TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate),
117 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 112 TEGRA_MAP_MUXCONF("slxd", "spdif", none, tristate),
118 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 113 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
119 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 114 TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
120 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 115 TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, tristate),
121 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 116 TEGRA_MAP_MUXCONF("spia", "gmi", none, driven),
122 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 117 TEGRA_MAP_MUXCONF("spib", "gmi", none, driven),
123 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 118 TEGRA_MAP_MUXCONF("spic", "gmi", up, tristate),
124 {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 119 TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
125 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 120 TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
126 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 121 TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
127 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 122 TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate),
128 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 123 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
129 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 124 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
130 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 125 TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
131 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 126 TEGRA_MAP_MUXCONF("uac", "rsvd2", none, tristate),
132 {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 127 TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
133 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 128 TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
134 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 129 TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
135 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 130 TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
136 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 131 TEGRA_MAP_CONF("ck32", none, na),
137 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 132 TEGRA_MAP_CONF("ddrc", none, na),
138 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 133 TEGRA_MAP_CONF("pmca", none, na),
139 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 134 TEGRA_MAP_CONF("pmcb", none, na),
140 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 135 TEGRA_MAP_CONF("pmcc", none, na),
141 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 136 TEGRA_MAP_CONF("pmcd", none, na),
142 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 137 TEGRA_MAP_CONF("pmce", none, na),
143 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 138 TEGRA_MAP_CONF("xm2c", none, na),
144 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 139 TEGRA_MAP_CONF("xm2d", none, na),
145}; 140 TEGRA_MAP_CONF("ls", up, na),
146 141 TEGRA_MAP_CONF("lc", up, na),
147static struct tegra_gpio_table gpio_table[] = { 142 TEGRA_MAP_CONF("ld17_0", down, na),
148 { .gpio = TEGRA_GPIO_SD2_CD, .enable = true }, 143 TEGRA_MAP_CONF("ld19_18", down, na),
149 { .gpio = TEGRA_GPIO_SD2_WP, .enable = true }, 144 TEGRA_MAP_CONF("ld21_20", down, na),
150 { .gpio = TEGRA_GPIO_SD2_POWER, .enable = true }, 145 TEGRA_MAP_CONF("ld23_22", down, na),
151 { .gpio = TEGRA_GPIO_SD4_CD, .enable = true },
152 { .gpio = TEGRA_GPIO_SD4_WP, .enable = true },
153 { .gpio = TEGRA_GPIO_SD4_POWER, .enable = true },
154 { .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true },
155 { .gpio = TEGRA_GPIO_HP_DET, .enable = true },
156 { .gpio = TEGRA_GPIO_INT_MIC_EN, .enable = true },
157 { .gpio = TEGRA_GPIO_EXT_MIC_EN, .enable = true },
158}; 146};
159 147
160static struct tegra_board_pinmux_conf conf = { 148static struct tegra_board_pinmux_conf conf = {
161 .pgs = harmony_pinmux, 149 .maps = harmony_map,
162 .pg_count = ARRAY_SIZE(harmony_pinmux), 150 .map_count = ARRAY_SIZE(harmony_map),
163 .gpios = gpio_table,
164 .gpio_count = ARRAY_SIZE(gpio_table),
165}; 151};
166 152
167void harmony_pinmux_init(void) 153void harmony_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index c775572dcea4..6f1111b48e7c 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -2,6 +2,7 @@
2 * arch/arm/mach-tegra/board-paz00-pinmux.c 2 * arch/arm/mach-tegra/board-paz00-pinmux.c
3 * 3 *
4 * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de> 4 * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 8 * License version 2, as published by the Free Software Foundation, and
@@ -15,150 +16,138 @@
15 */ 16 */
16 17
17#include <linux/kernel.h> 18#include <linux/kernel.h>
18#include <linux/gpio.h>
19#include <linux/of.h>
20 19
21#include <mach/pinmux.h>
22#include <mach/pinmux-tegra20.h>
23
24#include "gpio-names.h"
25#include "board-paz00.h" 20#include "board-paz00.h"
26#include "board-pinmux.h" 21#include "board-pinmux.h"
27 22
28static struct tegra_pingroup_config paz00_pinmux[] = { 23static struct pinctrl_map paz00_map[] = {
29 {TEGRA_PINGROUP_ATA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 24 TEGRA_MAP_MUXCONF("ata", "gmi", none, driven),
30 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 25 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
31 {TEGRA_PINGROUP_ATC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 26 TEGRA_MAP_MUXCONF("atc", "gmi", none, driven),
32 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 27 TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
33 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 28 TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
34 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 29 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
35 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 30 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, driven),
36 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 31 TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
37 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_PLLC_OUT1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 32 TEGRA_MAP_MUXCONF("csus", "pllc_out1", down, tristate),
38 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 33 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
39 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 34 TEGRA_MAP_MUXCONF("dap2", "gmi", none, driven),
40 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 35 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
41 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 36 TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
42 {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 37 TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
43 {TEGRA_PINGROUP_DTA, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 38 TEGRA_MAP_MUXCONF("dta", "rsvd1", up, tristate),
44 {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 39 TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, tristate),
45 {TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 40 TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
46 {TEGRA_PINGROUP_DTD, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 41 TEGRA_MAP_MUXCONF("dtd", "rsvd1", up, tristate),
47 {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 42 TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
48 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 43 TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven),
49 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 44 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
50 {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 45 TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
51 {TEGRA_PINGROUP_GMC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 46 TEGRA_MAP_MUXCONF("gmc", "gmi", none, driven),
52 {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 47 TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
53 {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 48 TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
54 {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 49 TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven),
55 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 50 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
56 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 51 TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
57 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 52 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, driven),
58 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 53 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
59 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 54 TEGRA_MAP_MUXCONF("irrx", "uarta", up, driven),
60 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 55 TEGRA_MAP_MUXCONF("irtx", "uarta", up, driven),
61 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 56 TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
62 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 57 TEGRA_MAP_MUXCONF("kbcb", "sdio2", up, driven),
63 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 58 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
64 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 59 TEGRA_MAP_MUXCONF("kbcd", "sdio2", up, driven),
65 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 60 TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
66 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 61 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
67 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 62 TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
68 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 63 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
69 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 64 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
70 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 65 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
71 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 66 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
72 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 67 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
73 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 68 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
74 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 69 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
75 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 70 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
76 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 71 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
77 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 72 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
78 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 73 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
79 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 74 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
80 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 75 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
81 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 76 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
82 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 77 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
83 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 78 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
84 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 79 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
85 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 80 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
86 {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 81 TEGRA_MAP_MUXCONF("ldc", "displaya", na, driven),
87 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 82 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
88 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 83 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, tristate),
89 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 84 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, tristate),
90 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 85 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, tristate),
91 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 86 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
92 {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 87 TEGRA_MAP_MUXCONF("lm0", "displaya", na, tristate),
93 {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 88 TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
94 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 89 TEGRA_MAP_MUXCONF("lpp", "displaya", na, tristate),
95 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 90 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, tristate),
96 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 91 TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
97 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 92 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, tristate),
98 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 93 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
99 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 94 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
100 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 95 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
101 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 96 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
102 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 97 TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
103 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 98 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
104 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 99 TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
105 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 100 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, tristate),
106 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 101 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
107 {TEGRA_PINGROUP_OWC, TEGRA_MUX_OWR, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 102 TEGRA_MAP_MUXCONF("owc", "owr", up, tristate),
108 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 103 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
109 {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 104 TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
110 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 105 TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
111 {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 106 TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
112 {TEGRA_PINGROUP_SDC, TEGRA_MUX_TWC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 107 TEGRA_MAP_MUXCONF("sdc", "twc", up, tristate),
113 {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 108 TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
114 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 109 TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven),
115 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 110 TEGRA_MAP_MUXCONF("slxa", "pcie", none, tristate),
116 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 111 TEGRA_MAP_MUXCONF("slxc", "spi4", none, tristate),
117 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 112 TEGRA_MAP_MUXCONF("slxd", "spi4", none, tristate),
118 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 113 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
119 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 114 TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
120 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 115 TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven),
121 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 116 TEGRA_MAP_MUXCONF("spia", "gmi", down, tristate),
122 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 117 TEGRA_MAP_MUXCONF("spib", "gmi", down, tristate),
123 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 118 TEGRA_MAP_MUXCONF("spic", "gmi", up, driven),
124 {TEGRA_PINGROUP_SPID, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 119 TEGRA_MAP_MUXCONF("spid", "gmi", down, tristate),
125 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 120 TEGRA_MAP_MUXCONF("spie", "gmi", up, tristate),
126 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_RSVD4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 121 TEGRA_MAP_MUXCONF("spif", "rsvd4", down, tristate),
127 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 122 TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, driven),
128 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 123 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
129 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 124 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven),
130 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 125 TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven),
131 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 126 TEGRA_MAP_MUXCONF("uac", "rsvd4", none, driven),
132 {TEGRA_PINGROUP_UAD, TEGRA_MUX_SPDIF, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 127 TEGRA_MAP_MUXCONF("uad", "spdif", up, tristate),
133 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 128 TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
134 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 129 TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
135 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 130 TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven),
136 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 131 TEGRA_MAP_CONF("ck32", none, na),
137 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 132 TEGRA_MAP_CONF("ddrc", none, na),
138 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 133 TEGRA_MAP_CONF("pmca", none, na),
139 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 134 TEGRA_MAP_CONF("pmcb", none, na),
140 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 135 TEGRA_MAP_CONF("pmcc", none, na),
141 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 136 TEGRA_MAP_CONF("pmcd", none, na),
142 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 137 TEGRA_MAP_CONF("pmce", none, na),
143 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 138 TEGRA_MAP_CONF("xm2c", none, na),
144 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 139 TEGRA_MAP_CONF("xm2d", none, na),
145}; 140 TEGRA_MAP_CONF("ls", up, na),
146 141 TEGRA_MAP_CONF("lc", up, na),
147static struct tegra_gpio_table gpio_table[] = { 142 TEGRA_MAP_CONF("ld17_0", down, na),
148 { .gpio = TEGRA_GPIO_SD1_CD, .enable = true }, 143 TEGRA_MAP_CONF("ld19_18", down, na),
149 { .gpio = TEGRA_GPIO_SD1_WP, .enable = true }, 144 TEGRA_MAP_CONF("ld21_20", down, na),
150 { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true }, 145 TEGRA_MAP_CONF("ld23_22", down, na),
151 { .gpio = TEGRA_ULPI_RST, .enable = true },
152 { .gpio = TEGRA_WIFI_PWRN, .enable = true },
153 { .gpio = TEGRA_WIFI_RST, .enable = true },
154 { .gpio = TEGRA_WIFI_LED, .enable = true },
155}; 146};
156 147
157static struct tegra_board_pinmux_conf conf = { 148static struct tegra_board_pinmux_conf conf = {
158 .pgs = paz00_pinmux, 149 .maps = paz00_map,
159 .pg_count = ARRAY_SIZE(paz00_pinmux), 150 .map_count = ARRAY_SIZE(paz00_map),
160 .gpios = gpio_table,
161 .gpio_count = ARRAY_SIZE(gpio_table),
162}; 151};
163 152
164void paz00_pinmux_init(void) 153void paz00_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
index adc3efe979b3..a5574c71b931 100644
--- a/arch/arm/mach-tegra/board-pinmux.c
+++ b/arch/arm/mach-tegra/board-pinmux.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This software is licensed under the terms of the GNU General Public 4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and 5 * License version 2, as published by the Free Software Foundation, and
@@ -15,75 +15,59 @@
15#include <linux/device.h> 15#include <linux/device.h>
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/notifier.h> 17#include <linux/notifier.h>
18#include <linux/of.h>
19#include <linux/string.h> 18#include <linux/string.h>
20 19
21#include <mach/gpio-tegra.h>
22#include <mach/pinmux.h>
23
24#include "board-pinmux.h" 20#include "board-pinmux.h"
25#include "devices.h" 21#include "devices.h"
26 22
27struct tegra_board_pinmux_conf *confs[2]; 23unsigned long tegra_pincfg_pullnone_driven[2] = {
28 24 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
29static void tegra_board_pinmux_setup_gpios(void) 25 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
30{ 26};
31 int i;
32
33 for (i = 0; i < ARRAY_SIZE(confs); i++) {
34 if (!confs[i])
35 continue;
36
37 tegra_gpio_config(confs[i]->gpios, confs[i]->gpio_count);
38 }
39}
40
41static void tegra_board_pinmux_setup_pinmux(void)
42{
43 int i;
44 27
45 for (i = 0; i < ARRAY_SIZE(confs); i++) { 28unsigned long tegra_pincfg_pullnone_tristate[2] = {
46 if (!confs[i]) 29 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
47 continue; 30 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
31};
48 32
49 tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count); 33unsigned long tegra_pincfg_pullnone_na[1] = {
34 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
35};
50 36
51 if (confs[i]->drives) 37unsigned long tegra_pincfg_pullup_driven[2] = {
52 tegra_drive_pinmux_config_table(confs[i]->drives, 38 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
53 confs[i]->drive_count); 39 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
54 } 40};
55}
56 41
57static int tegra_board_pinmux_bus_notify(struct notifier_block *nb, 42unsigned long tegra_pincfg_pullup_tristate[2] = {
58 unsigned long event, void *vdev) 43 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
59{ 44 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
60 static bool had_gpio; 45};
61 static bool had_pinmux;
62 46
63 struct device *dev = vdev; 47unsigned long tegra_pincfg_pullup_na[1] = {
64 const char *devname; 48 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
49};
65 50
66 if (event != BUS_NOTIFY_BOUND_DRIVER) 51unsigned long tegra_pincfg_pulldown_driven[2] = {
67 return NOTIFY_DONE; 52 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
53 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
54};
68 55
69 devname = dev_name(dev); 56unsigned long tegra_pincfg_pulldown_tristate[2] = {
57 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
58 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
59};
70 60
71 if (!had_gpio && !strcmp(devname, GPIO_DEV)) { 61unsigned long tegra_pincfg_pulldown_na[1] = {
72 tegra_board_pinmux_setup_gpios(); 62 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
73 had_gpio = true; 63};
74 } else if (!had_pinmux && !strcmp(devname, PINMUX_DEV)) {
75 tegra_board_pinmux_setup_pinmux();
76 had_pinmux = true;
77 }
78 64
79 if (had_gpio && had_pinmux) 65unsigned long tegra_pincfg_pullna_driven[1] = {
80 return NOTIFY_STOP_MASK; 66 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
81 else 67};
82 return NOTIFY_DONE;
83}
84 68
85static struct notifier_block nb = { 69unsigned long tegra_pincfg_pullna_tristate[1] = {
86 .notifier_call = tegra_board_pinmux_bus_notify, 70 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
87}; 71};
88 72
89static struct platform_device *devices[] = { 73static struct platform_device *devices[] = {
@@ -94,11 +78,10 @@ static struct platform_device *devices[] = {
94void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a, 78void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
95 struct tegra_board_pinmux_conf *conf_b) 79 struct tegra_board_pinmux_conf *conf_b)
96{ 80{
97 confs[0] = conf_a; 81 if (conf_a)
98 confs[1] = conf_b; 82 pinctrl_register_mappings(conf_a->maps, conf_a->map_count);
99 83 if (conf_b)
100 bus_register_notifier(&platform_bus_type, &nb); 84 pinctrl_register_mappings(conf_b->maps, conf_b->map_count);
101 85
102 if (!of_machine_is_compatible("nvidia,tegra20")) 86 platform_add_devices(devices, ARRAY_SIZE(devices));
103 platform_add_devices(devices, ARRAY_SIZE(devices));
104} 87}
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
index 4aac73546f54..c5f3f3381e86 100644
--- a/arch/arm/mach-tegra/board-pinmux.h
+++ b/arch/arm/mach-tegra/board-pinmux.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This software is licensed under the terms of the GNU General Public 4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and 5 * License version 2, as published by the Free Software Foundation, and
@@ -15,21 +15,37 @@
15#ifndef __MACH_TEGRA_BOARD_PINMUX_H 15#ifndef __MACH_TEGRA_BOARD_PINMUX_H
16#define __MACH_TEGRA_BOARD_PINMUX_H 16#define __MACH_TEGRA_BOARD_PINMUX_H
17 17
18#define GPIO_DEV "tegra-gpio" 18#include <linux/pinctrl/machine.h>
19#define PINMUX_DEV "tegra-pinmux"
20 19
21struct tegra_pingroup_config; 20#include <mach/pinconf-tegra.h>
22struct tegra_gpio_table;
23 21
24struct tegra_board_pinmux_conf { 22#define PINMUX_DEV "tegra20-pinctrl"
25 struct tegra_pingroup_config *pgs; 23
26 int pg_count; 24#define TEGRA_MAP_MUX(_group_, _function_) \
25 PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_)
26
27#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \
28 PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_)
27 29
28 struct tegra_drive_pingroup_config *drives; 30#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \
29 int drive_count; 31 TEGRA_MAP_MUX(_group_, _function_), \
32 TEGRA_MAP_CONF(_group_, _pull_, _drive_)
30 33
31 struct tegra_gpio_table *gpios; 34extern unsigned long tegra_pincfg_pullnone_driven[2];
32 int gpio_count; 35extern unsigned long tegra_pincfg_pullnone_tristate[2];
36extern unsigned long tegra_pincfg_pullnone_na[1];
37extern unsigned long tegra_pincfg_pullup_driven[2];
38extern unsigned long tegra_pincfg_pullup_tristate[2];
39extern unsigned long tegra_pincfg_pullup_na[1];
40extern unsigned long tegra_pincfg_pulldown_driven[2];
41extern unsigned long tegra_pincfg_pulldown_tristate[2];
42extern unsigned long tegra_pincfg_pulldown_na[1];
43extern unsigned long tegra_pincfg_pullna_driven[1];
44extern unsigned long tegra_pincfg_pullna_tristate[1];
45
46struct tegra_board_pinmux_conf {
47 struct pinctrl_map *maps;
48 int map_count;
33}; 49};
34 50
35void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a, 51void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index 55e7e43a14ad..11fc8a568c64 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2010,2011 NVIDIA Corporation 2 * Copyright (C) 2010-2012 NVIDIA Corporation
3 * Copyright (C) 2011 Google, Inc. 3 * Copyright (C) 2011 Google, Inc.
4 * 4 *
5 * This software is licensed under the terms of the GNU General Public 5 * This software is licensed under the terms of the GNU General Public
@@ -14,216 +14,176 @@
14 */ 14 */
15 15
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/gpio.h>
19#include <linux/of.h>
20 17
21#include <mach/pinmux.h>
22#include <mach/pinmux-tegra20.h>
23
24#include "gpio-names.h"
25#include "board-pinmux.h"
26#include "board-seaboard.h" 18#include "board-seaboard.h"
19#include "board-pinmux.h"
27 20
28#define DEFAULT_DRIVE(_name) \ 21static unsigned long seaboard_pincfg_drive_sdio1[] = {
29 { \ 22 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 0),
30 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ 23 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SCHMITT, 0),
31 .hsm = TEGRA_HSM_DISABLE, \ 24 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 3),
32 .schmitt = TEGRA_SCHMITT_ENABLE, \ 25 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 31),
33 .drive = TEGRA_DRIVE_DIV_1, \ 26 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 31),
34 .pull_down = TEGRA_PULL_31, \ 27 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 3),
35 .pull_up = TEGRA_PULL_31, \ 28 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 3),
36 .slew_rising = TEGRA_SLEW_SLOWEST, \
37 .slew_falling = TEGRA_SLEW_SLOWEST, \
38 }
39
40static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
41 DEFAULT_DRIVE(SDIO1),
42};
43
44static struct tegra_pingroup_config common_pinmux[] = {
45 {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
46 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
47 {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
48 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
49 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
50 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
51 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
52 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
53 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
54 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
55 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
56 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
57 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
58 {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
59 {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
60 {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
61 {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
62 {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
63 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
64 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
65 {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
66 {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
67 {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
68 {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
69 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
70 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
71 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
72 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
73 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
74 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
75 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
76 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
77 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
78 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
79 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
80 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
81 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
82 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
83 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
84 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
85 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
86 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
87 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
88 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
89 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
90 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
91 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
92 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
93 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
94 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
95 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
96 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
97 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
98 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
99 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
100 {TEGRA_PINGROUP_LDC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
101 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
102 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
103 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
104 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
105 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
106 {TEGRA_PINGROUP_LM0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
107 {TEGRA_PINGROUP_LM1, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
108 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
109 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
110 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
111 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
112 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
113 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
114 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
115 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
116 {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
117 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
118 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
119 {TEGRA_PINGROUP_SDB, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
120 {TEGRA_PINGROUP_SDC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
121 {TEGRA_PINGROUP_SDD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
122 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
123 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
124 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
125 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
126 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
127 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
128 {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
129 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
130 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
131 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
132 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
133 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
134 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
135 {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
136 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
137 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
138 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
139 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
140 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
141 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
142 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
143 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
144 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
145 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
146 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
147 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
148};
149
150static struct tegra_pingroup_config seaboard_pinmux[] = {
151 {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
152 {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
153 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
154 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
155 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
156 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
157 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
158 {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
159 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
160 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
161 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
162 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
163 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
164};
165
166static struct tegra_pingroup_config ventana_pinmux[] = {
167 {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
168 {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
169 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
170 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
171 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
172 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
173 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
174 {TEGRA_PINGROUP_PTA, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
175 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
176 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
177 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
178 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
179 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
180}; 29};
181 30
182static struct tegra_gpio_table common_gpio_table[] = { 31static struct pinctrl_map common_map[] = {
183 { .gpio = TEGRA_GPIO_SD2_CD, .enable = true }, 32 TEGRA_MAP_MUXCONF("ata", "ide", none, driven),
184 { .gpio = TEGRA_GPIO_SD2_WP, .enable = true }, 33 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
185 { .gpio = TEGRA_GPIO_SD2_POWER, .enable = true }, 34 TEGRA_MAP_MUXCONF("atc", "nand", none, driven),
186 { .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true }, 35 TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
36 TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate),
37 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
38 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", none, driven),
39 TEGRA_MAP_MUXCONF("crtp", "crt", up, tristate),
40 TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", none, tristate),
41 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
42 TEGRA_MAP_MUXCONF("dap2", "dap2", none, driven),
43 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
44 TEGRA_MAP_MUXCONF("dap4", "dap4", none, driven),
45 TEGRA_MAP_MUXCONF("dta", "vi", down, driven),
46 TEGRA_MAP_MUXCONF("dtb", "vi", down, driven),
47 TEGRA_MAP_MUXCONF("dtc", "vi", down, driven),
48 TEGRA_MAP_MUXCONF("dtd", "vi", down, driven),
49 TEGRA_MAP_MUXCONF("dte", "vi", down, tristate),
50 TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven),
51 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
52 TEGRA_MAP_MUXCONF("gmb", "gmi", up, tristate),
53 TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven),
54 TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
55 TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven),
56 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
57 TEGRA_MAP_MUXCONF("gpv", "pcie", none, tristate),
58 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
59 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
60 TEGRA_MAP_MUXCONF("irrx", "uartb", none, driven),
61 TEGRA_MAP_MUXCONF("irtx", "uartb", none, driven),
62 TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
63 TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven),
64 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
65 TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven),
66 TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
67 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
68 TEGRA_MAP_MUXCONF("lcsn", "rsvd4", na, tristate),
69 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
70 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
71 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
72 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
73 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
74 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
75 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
76 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
77 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
78 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
79 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
80 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
81 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
82 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
83 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
84 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
85 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
86 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
87 TEGRA_MAP_MUXCONF("ldc", "rsvd4", na, tristate),
88 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
89 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
90 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
91 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
92 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
93 TEGRA_MAP_MUXCONF("lm0", "rsvd4", na, driven),
94 TEGRA_MAP_MUXCONF("lm1", "crt", na, tristate),
95 TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
96 TEGRA_MAP_MUXCONF("lpw1", "rsvd4", na, tristate),
97 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
98 TEGRA_MAP_MUXCONF("lsdi", "rsvd4", na, tristate),
99 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
100 TEGRA_MAP_MUXCONF("lvp0", "rsvd4", na, tristate),
101 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
102 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
103 TEGRA_MAP_MUXCONF("owc", "rsvd2", none, tristate),
104 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
105 TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
106 TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
107 TEGRA_MAP_MUXCONF("sdb", "sdio3", na, driven),
108 TEGRA_MAP_MUXCONF("sdc", "sdio3", none, driven),
109 TEGRA_MAP_MUXCONF("sdd", "sdio3", none, driven),
110 TEGRA_MAP_MUXCONF("sdio1", "sdio1", up, driven),
111 TEGRA_MAP_MUXCONF("slxa", "pcie", up, tristate),
112 TEGRA_MAP_MUXCONF("slxd", "spdif", none, driven),
113 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
114 TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, driven),
115 TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven),
116 TEGRA_MAP_MUXCONF("spib", "gmi", none, tristate),
117 TEGRA_MAP_MUXCONF("spid", "spi1", none, tristate),
118 TEGRA_MAP_MUXCONF("spie", "spi1", none, tristate),
119 TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
120 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
121 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven),
122 TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven),
123 TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven),
124 TEGRA_MAP_MUXCONF("uad", "irda", none, driven),
125 TEGRA_MAP_MUXCONF("uca", "uartc", none, driven),
126 TEGRA_MAP_MUXCONF("ucb", "uartc", none, driven),
127 TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven),
128 TEGRA_MAP_CONF("ck32", none, na),
129 TEGRA_MAP_CONF("ddrc", none, na),
130 TEGRA_MAP_CONF("pmca", none, na),
131 TEGRA_MAP_CONF("pmcb", none, na),
132 TEGRA_MAP_CONF("pmcc", none, na),
133 TEGRA_MAP_CONF("pmcd", none, na),
134 TEGRA_MAP_CONF("pmce", none, na),
135 TEGRA_MAP_CONF("xm2c", none, na),
136 TEGRA_MAP_CONF("xm2d", none, na),
137 TEGRA_MAP_CONF("ls", up, na),
138 TEGRA_MAP_CONF("lc", up, na),
139 TEGRA_MAP_CONF("ld17_0", down, na),
140 TEGRA_MAP_CONF("ld19_18", down, na),
141 TEGRA_MAP_CONF("ld21_20", down, na),
142 TEGRA_MAP_CONF("ld23_22", down, na),
187}; 143};
188 144
189static struct tegra_gpio_table seaboard_gpio_table[] = { 145static struct pinctrl_map seaboard_map[] = {
190 { .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true }, 146 TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, tristate),
191 { .gpio = TEGRA_GPIO_POWERKEY, .enable = true }, 147 TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven),
192 { .gpio = TEGRA_GPIO_HP_DET, .enable = true }, 148 TEGRA_MAP_MUXCONF("lpw0", "hdmi", na, driven),
193 { .gpio = TEGRA_GPIO_ISL29018_IRQ, .enable = true }, 149 TEGRA_MAP_MUXCONF("lpw2", "hdmi", na, driven),
194 { .gpio = TEGRA_GPIO_USB1, .enable = true }, 150 TEGRA_MAP_MUXCONF("lsc1", "hdmi", na, tristate),
151 TEGRA_MAP_MUXCONF("lsck", "hdmi", na, tristate),
152 TEGRA_MAP_MUXCONF("lsda", "hdmi", na, tristate),
153 TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate),
154 TEGRA_MAP_MUXCONF("spia", "gmi", up, tristate),
155 TEGRA_MAP_MUXCONF("spic", "gmi", up, driven),
156 TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate),
157 PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, "drive_sdio1", seaboard_pincfg_drive_sdio1),
195}; 158};
196 159
197static struct tegra_gpio_table ventana_gpio_table[] = { 160static struct pinctrl_map ventana_map[] = {
198 /* hp_det */ 161 TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, driven),
199 { .gpio = TEGRA_GPIO_PW2, .enable = true }, 162 TEGRA_MAP_MUXCONF("gmd", "sflash", none, tristate),
200 /* int_mic_en */ 163 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
201 { .gpio = TEGRA_GPIO_PX0, .enable = true }, 164 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
202 /* ext_mic_en */ 165 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, driven),
203 { .gpio = TEGRA_GPIO_PX1, .enable = true }, 166 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
167 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
168 TEGRA_MAP_MUXCONF("slxc", "sdio3", none, driven),
169 TEGRA_MAP_MUXCONF("spia", "gmi", none, tristate),
170 TEGRA_MAP_MUXCONF("spic", "gmi", none, tristate),
171 TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate),
204}; 172};
205 173
206static struct tegra_board_pinmux_conf common_conf = { 174static struct tegra_board_pinmux_conf common_conf = {
207 .pgs = common_pinmux, 175 .maps = common_map,
208 .pg_count = ARRAY_SIZE(common_pinmux), 176 .map_count = ARRAY_SIZE(common_map),
209 .gpios = common_gpio_table,
210 .gpio_count = ARRAY_SIZE(common_gpio_table),
211}; 177};
212 178
213static struct tegra_board_pinmux_conf seaboard_conf = { 179static struct tegra_board_pinmux_conf seaboard_conf = {
214 .pgs = seaboard_pinmux, 180 .maps = seaboard_map,
215 .pg_count = ARRAY_SIZE(seaboard_pinmux), 181 .map_count = ARRAY_SIZE(seaboard_map),
216 .drives = seaboard_drive_pinmux,
217 .drive_count = ARRAY_SIZE(seaboard_drive_pinmux),
218 .gpios = seaboard_gpio_table,
219 .gpio_count = ARRAY_SIZE(seaboard_gpio_table),
220}; 182};
221 183
222static struct tegra_board_pinmux_conf ventana_conf = { 184static struct tegra_board_pinmux_conf ventana_conf = {
223 .pgs = ventana_pinmux, 185 .maps = ventana_map,
224 .pg_count = ARRAY_SIZE(ventana_pinmux), 186 .map_count = ARRAY_SIZE(ventana_map),
225 .gpios = ventana_gpio_table,
226 .gpio_count = ARRAY_SIZE(ventana_gpio_table),
227}; 187};
228 188
229void seaboard_pinmux_init(void) 189void seaboard_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index d669847f0485..a0184fb44222 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -24,6 +24,7 @@
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <linux/gpio_keys.h> 26#include <linux/gpio_keys.h>
27#include <linux/platform_data/tegra_usb.h>
27 28
28#include <sound/wm8903.h> 29#include <sound/wm8903.h>
29 30
@@ -186,20 +187,10 @@ static struct i2c_board_info __initdata wm8903_device = {
186 187
187static int seaboard_ehci_init(void) 188static int seaboard_ehci_init(void)
188{ 189{
189 int gpio_status; 190 struct tegra_ehci_platform_data *pdata;
190 191
191 gpio_status = gpio_request(TEGRA_GPIO_USB1, "VBUS_USB1"); 192 pdata = tegra_ehci1_device.dev.platform_data;
192 if (gpio_status < 0) { 193 pdata->vbus_gpio = TEGRA_GPIO_USB1;
193 pr_err("VBUS_USB1 request GPIO FAILED\n");
194 WARN_ON(1);
195 }
196
197 gpio_status = gpio_direction_output(TEGRA_GPIO_USB1, 1);
198 if (gpio_status < 0) {
199 pr_err("VBUS_USB1 request GPIO DIRECTION FAILED\n");
200 WARN_ON(1);
201 }
202 gpio_set_value(TEGRA_GPIO_USB1, 1);
203 194
204 platform_device_register(&tegra_ehci1_device); 195 platform_device_register(&tegra_ehci1_device);
205 platform_device_register(&tegra_ehci3_device); 196 platform_device_register(&tegra_ehci3_device);
@@ -209,9 +200,6 @@ static int seaboard_ehci_init(void)
209 200
210static void __init seaboard_i2c_init(void) 201static void __init seaboard_i2c_init(void)
211{ 202{
212 gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018");
213 gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ);
214
215 isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ); 203 isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ);
216 i2c_register_board_info(0, &isl29018_device, 1); 204 i2c_register_board_info(0, &isl29018_device, 1);
217 205
@@ -261,7 +249,6 @@ static void __init tegra_kaen_init(void)
261 debug_uart_platform_data[0].irq = INT_UARTB; 249 debug_uart_platform_data[0].irq = INT_UARTB;
262 250
263 seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE; 251 seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE;
264 tegra_gpio_enable(TEGRA_GPIO_KAEN_HP_MUTE);
265 252
266 seaboard_common_init(); 253 seaboard_common_init();
267 254
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index a21a2be57cb6..7b39511c0d4d 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -2,6 +2,7 @@
2 * arch/arm/mach-tegra/board-trimslice-pinmux.c 2 * arch/arm/mach-tegra/board-trimslice-pinmux.c
3 * 3 *
4 * Copyright (C) 2011 CompuLab, Ltd. 4 * Copyright (C) 2011 CompuLab, Ltd.
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 8 * License version 2, as published by the Free Software Foundation, and
@@ -13,150 +14,139 @@
13 * GNU General Public License for more details. 14 * GNU General Public License for more details.
14 * 15 *
15 */ 16 */
16#include <linux/gpio.h>
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/of.h>
20 18
21#include <mach/pinmux.h>
22#include <mach/pinmux-tegra20.h>
23
24#include "gpio-names.h"
25#include "board-pinmux.h"
26#include "board-trimslice.h" 19#include "board-trimslice.h"
20#include "board-pinmux.h"
27 21
28static struct tegra_pingroup_config trimslice_pinmux[] = { 22static struct pinctrl_map trimslice_map[] = {
29 {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 23 TEGRA_MAP_MUXCONF("ata", "ide", none, tristate),
30 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 24 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
31 {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 25 TEGRA_MAP_MUXCONF("atc", "nand", none, tristate),
32 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 26 TEGRA_MAP_MUXCONF("atd", "gmi", none, tristate),
33 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 27 TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate),
34 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 28 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
35 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 29 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
36 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 30 TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
37 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 31 TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
38 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 32 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
39 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 33 TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
40 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 34 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
41 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 35 TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
42 {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 36 TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
43 {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 37 TEGRA_MAP_MUXCONF("dta", "vi", none, tristate),
44 {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 38 TEGRA_MAP_MUXCONF("dtb", "vi", none, tristate),
45 {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 39 TEGRA_MAP_MUXCONF("dtc", "vi", none, tristate),
46 {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 40 TEGRA_MAP_MUXCONF("dtd", "vi", none, tristate),
47 {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 41 TEGRA_MAP_MUXCONF("dte", "vi", none, tristate),
48 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 42 TEGRA_MAP_MUXCONF("dtf", "i2c3", up, driven),
49 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 43 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
50 {TEGRA_PINGROUP_GMB, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 44 TEGRA_MAP_MUXCONF("gmb", "nand", none, tristate),
51 {TEGRA_PINGROUP_GMC, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 45 TEGRA_MAP_MUXCONF("gmc", "sflash", none, driven),
52 {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 46 TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven),
53 {TEGRA_PINGROUP_GME, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 47 TEGRA_MAP_MUXCONF("gme", "gmi", none, tristate),
54 {TEGRA_PINGROUP_GPU, TEGRA_MUX_UARTA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 48 TEGRA_MAP_MUXCONF("gpu", "uarta", none, driven),
55 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 49 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
56 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 50 TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
57 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 51 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
58 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 52 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, tristate),
59 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 53 TEGRA_MAP_MUXCONF("irrx", "uartb", up, tristate),
60 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 54 TEGRA_MAP_MUXCONF("irtx", "uartb", up, tristate),
61 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 55 TEGRA_MAP_MUXCONF("kbca", "kbc", up, tristate),
62 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 56 TEGRA_MAP_MUXCONF("kbcb", "kbc", up, tristate),
63 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 57 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, tristate),
64 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 58 TEGRA_MAP_MUXCONF("kbcd", "kbc", up, tristate),
65 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 59 TEGRA_MAP_MUXCONF("kbce", "kbc", up, tristate),
66 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 60 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, tristate),
67 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 61 TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
68 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 62 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
69 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 63 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
70 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 64 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
71 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 65 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
72 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 66 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
73 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 67 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
74 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 68 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
75 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 69 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
76 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 70 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
77 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 71 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
78 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 72 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
79 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 73 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
80 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 74 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
81 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 75 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
82 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 76 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
83 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 77 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
84 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 78 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
85 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 79 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
86 {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 80 TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
87 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 81 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
88 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 82 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
89 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 83 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
90 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 84 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
91 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 85 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
92 {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 86 TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
93 {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 87 TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
94 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 88 TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
95 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 89 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
96 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 90 TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
97 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 91 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
98 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 92 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
99 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 93 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
100 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 94 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
101 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 95 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
102 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 96 TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
103 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 97 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
104 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 98 TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
105 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 99 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
106 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 100 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
107 {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 101 TEGRA_MAP_MUXCONF("owc", "rsvd2", up, tristate),
108 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 102 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, tristate),
109 {TEGRA_PINGROUP_PTA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 103 TEGRA_MAP_MUXCONF("pta", "gmi", none, tristate),
110 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 104 TEGRA_MAP_MUXCONF("rm", "i2c1", up, driven),
111 {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 105 TEGRA_MAP_MUXCONF("sdb", "pwm", na, driven),
112 {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 106 TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
113 {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 107 TEGRA_MAP_MUXCONF("sdd", "pwm", up, driven),
114 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 108 TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven),
115 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 109 TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
116 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 110 TEGRA_MAP_MUXCONF("slxc", "sdio3", none, tristate),
117 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 111 TEGRA_MAP_MUXCONF("slxd", "sdio3", none, tristate),
118 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 112 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
119 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 113 TEGRA_MAP_MUXCONF("spdi", "spdif", none, tristate),
120 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 114 TEGRA_MAP_MUXCONF("spdo", "spdif", none, tristate),
121 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 115 TEGRA_MAP_MUXCONF("spia", "spi2", down, tristate),
122 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 116 TEGRA_MAP_MUXCONF("spib", "spi2", down, tristate),
123 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 117 TEGRA_MAP_MUXCONF("spic", "spi2", up, tristate),
124 {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 118 TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
125 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 119 TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
126 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 120 TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
127 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 121 TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate),
128 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 122 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
129 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 123 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
130 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 124 TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
131 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 125 TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven),
132 {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 126 TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
133 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 127 TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
134 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 128 TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
135 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 129 TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
136 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 130 TEGRA_MAP_CONF("ck32", none, na),
137 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 131 TEGRA_MAP_CONF("ddrc", none, na),
138 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 132 TEGRA_MAP_CONF("pmca", none, na),
139 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 133 TEGRA_MAP_CONF("pmcb", none, na),
140 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 134 TEGRA_MAP_CONF("pmcc", none, na),
141 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 135 TEGRA_MAP_CONF("pmcd", none, na),
142 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 136 TEGRA_MAP_CONF("pmce", none, na),
143 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 137 TEGRA_MAP_CONF("xm2c", none, na),
144 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 138 TEGRA_MAP_CONF("xm2d", none, na),
145}; 139 TEGRA_MAP_CONF("ls", up, na),
146 140 TEGRA_MAP_CONF("lc", up, na),
147static struct tegra_gpio_table gpio_table[] = { 141 TEGRA_MAP_CONF("ld17_0", down, na),
148 { .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */ 142 TEGRA_MAP_CONF("ld19_18", down, na),
149 { .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */ 143 TEGRA_MAP_CONF("ld21_20", down, na),
150 144 TEGRA_MAP_CONF("ld23_22", down, na),
151 { .gpio = TRIMSLICE_GPIO_USB1_MODE, .enable = true }, /* USB1 mode */
152 { .gpio = TRIMSLICE_GPIO_USB2_RST, .enable = true }, /* USB2 PHY rst */
153}; 145};
154 146
155static struct tegra_board_pinmux_conf conf = { 147static struct tegra_board_pinmux_conf conf = {
156 .pgs = trimslice_pinmux, 148 .maps = trimslice_map,
157 .pg_count = ARRAY_SIZE(trimslice_pinmux), 149 .map_count = ARRAY_SIZE(trimslice_map),
158 .gpios = gpio_table,
159 .gpio_count = ARRAY_SIZE(gpio_table),
160}; 150};
161 151
162void trimslice_pinmux_init(void) 152void trimslice_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index cd52820a3e37..f6f5b6a11325 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -25,6 +25,7 @@
25#include <linux/io.h> 25#include <linux/io.h>
26#include <linux/i2c.h> 26#include <linux/i2c.h>
27#include <linux/gpio.h> 27#include <linux/gpio.h>
28#include <linux/platform_data/tegra_usb.h>
28 29
29#include <asm/hardware/gic.h> 30#include <asm/hardware/gic.h>
30#include <asm/mach-types.h> 31#include <asm/mach-types.h>
@@ -111,19 +112,13 @@ static void trimslice_i2c_init(void)
111 112
112static void trimslice_usb_init(void) 113static void trimslice_usb_init(void)
113{ 114{
114 int err; 115 struct tegra_ehci_platform_data *pdata;
115 116
116 platform_device_register(&tegra_ehci3_device); 117 pdata = tegra_ehci1_device.dev.platform_data;
118 pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
117 119
120 platform_device_register(&tegra_ehci3_device);
118 platform_device_register(&tegra_ehci2_device); 121 platform_device_register(&tegra_ehci2_device);
119
120 err = gpio_request_one(TRIMSLICE_GPIO_USB1_MODE, GPIOF_OUT_INIT_HIGH,
121 "usb1mode");
122 if (err) {
123 pr_err("TrimSlice: failed to obtain USB1 mode gpio: %d\n", err);
124 return;
125 }
126
127 platform_device_register(&tegra_ehci1_device); 122 platform_device_register(&tegra_ehci1_device);
128} 123}
129 124
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 5f6b867e20b4..bd3035e0cea1 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -110,7 +110,7 @@ static struct resource pinmux_resource[] = {
110}; 110};
111 111
112struct platform_device tegra_pinmux_device = { 112struct platform_device tegra_pinmux_device = {
113 .name = "tegra-pinmux", 113 .name = "tegra20-pinctrl",
114 .id = -1, 114 .id = -1,
115 .resource = pinmux_resource, 115 .resource = pinmux_resource,
116 .num_resources = ARRAY_SIZE(pinmux_resource), 116 .num_resources = ARRAY_SIZE(pinmux_resource),
@@ -448,17 +448,20 @@ static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
448struct tegra_ehci_platform_data tegra_ehci1_pdata = { 448struct tegra_ehci_platform_data tegra_ehci1_pdata = {
449 .operating_mode = TEGRA_USB_OTG, 449 .operating_mode = TEGRA_USB_OTG,
450 .power_down_on_bus_suspend = 1, 450 .power_down_on_bus_suspend = 1,
451 .vbus_gpio = -1,
451}; 452};
452 453
453struct tegra_ehci_platform_data tegra_ehci2_pdata = { 454struct tegra_ehci_platform_data tegra_ehci2_pdata = {
454 .phy_config = &tegra_ehci2_ulpi_phy_config, 455 .phy_config = &tegra_ehci2_ulpi_phy_config,
455 .operating_mode = TEGRA_USB_HOST, 456 .operating_mode = TEGRA_USB_HOST,
456 .power_down_on_bus_suspend = 1, 457 .power_down_on_bus_suspend = 1,
458 .vbus_gpio = -1,
457}; 459};
458 460
459struct tegra_ehci_platform_data tegra_ehci3_pdata = { 461struct tegra_ehci_platform_data tegra_ehci3_pdata = {
460 .operating_mode = TEGRA_USB_HOST, 462 .operating_mode = TEGRA_USB_HOST,
461 .power_down_on_bus_suspend = 1, 463 .power_down_on_bus_suspend = 1,
464 .vbus_gpio = -1,
462}; 465};
463 466
464static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32); 467static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-tegra/include/mach/gpio-tegra.h b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
index 6140820555e1..a978b3cc3a8d 100644
--- a/arch/arm/mach-tegra/include/mach/gpio-tegra.h
+++ b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
@@ -25,13 +25,4 @@
25 25
26#define TEGRA_NR_GPIOS INT_GPIO_NR 26#define TEGRA_NR_GPIOS INT_GPIO_NR
27 27
28struct tegra_gpio_table {
29 int gpio; /* GPIO number */
30 bool enable; /* Enable for GPIO at init? */
31};
32
33void tegra_gpio_config(struct tegra_gpio_table *table, int num);
34void tegra_gpio_enable(int gpio);
35void tegra_gpio_disable(int gpio);
36
37#endif 28#endif
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
deleted file mode 100644
index 6a40c1dbab17..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
+++ /dev/null
@@ -1,184 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
18#define __MACH_TEGRA_PINMUX_TEGRA20_H
19
20enum tegra_pingroup {
21 TEGRA_PINGROUP_ATA = 0,
22 TEGRA_PINGROUP_ATB,
23 TEGRA_PINGROUP_ATC,
24 TEGRA_PINGROUP_ATD,
25 TEGRA_PINGROUP_ATE,
26 TEGRA_PINGROUP_CDEV1,
27 TEGRA_PINGROUP_CDEV2,
28 TEGRA_PINGROUP_CRTP,
29 TEGRA_PINGROUP_CSUS,
30 TEGRA_PINGROUP_DAP1,
31 TEGRA_PINGROUP_DAP2,
32 TEGRA_PINGROUP_DAP3,
33 TEGRA_PINGROUP_DAP4,
34 TEGRA_PINGROUP_DDC,
35 TEGRA_PINGROUP_DTA,
36 TEGRA_PINGROUP_DTB,
37 TEGRA_PINGROUP_DTC,
38 TEGRA_PINGROUP_DTD,
39 TEGRA_PINGROUP_DTE,
40 TEGRA_PINGROUP_DTF,
41 TEGRA_PINGROUP_GMA,
42 TEGRA_PINGROUP_GMB,
43 TEGRA_PINGROUP_GMC,
44 TEGRA_PINGROUP_GMD,
45 TEGRA_PINGROUP_GME,
46 TEGRA_PINGROUP_GPU,
47 TEGRA_PINGROUP_GPU7,
48 TEGRA_PINGROUP_GPV,
49 TEGRA_PINGROUP_HDINT,
50 TEGRA_PINGROUP_I2CP,
51 TEGRA_PINGROUP_IRRX,
52 TEGRA_PINGROUP_IRTX,
53 TEGRA_PINGROUP_KBCA,
54 TEGRA_PINGROUP_KBCB,
55 TEGRA_PINGROUP_KBCC,
56 TEGRA_PINGROUP_KBCD,
57 TEGRA_PINGROUP_KBCE,
58 TEGRA_PINGROUP_KBCF,
59 TEGRA_PINGROUP_LCSN,
60 TEGRA_PINGROUP_LD0,
61 TEGRA_PINGROUP_LD1,
62 TEGRA_PINGROUP_LD10,
63 TEGRA_PINGROUP_LD11,
64 TEGRA_PINGROUP_LD12,
65 TEGRA_PINGROUP_LD13,
66 TEGRA_PINGROUP_LD14,
67 TEGRA_PINGROUP_LD15,
68 TEGRA_PINGROUP_LD16,
69 TEGRA_PINGROUP_LD17,
70 TEGRA_PINGROUP_LD2,
71 TEGRA_PINGROUP_LD3,
72 TEGRA_PINGROUP_LD4,
73 TEGRA_PINGROUP_LD5,
74 TEGRA_PINGROUP_LD6,
75 TEGRA_PINGROUP_LD7,
76 TEGRA_PINGROUP_LD8,
77 TEGRA_PINGROUP_LD9,
78 TEGRA_PINGROUP_LDC,
79 TEGRA_PINGROUP_LDI,
80 TEGRA_PINGROUP_LHP0,
81 TEGRA_PINGROUP_LHP1,
82 TEGRA_PINGROUP_LHP2,
83 TEGRA_PINGROUP_LHS,
84 TEGRA_PINGROUP_LM0,
85 TEGRA_PINGROUP_LM1,
86 TEGRA_PINGROUP_LPP,
87 TEGRA_PINGROUP_LPW0,
88 TEGRA_PINGROUP_LPW1,
89 TEGRA_PINGROUP_LPW2,
90 TEGRA_PINGROUP_LSC0,
91 TEGRA_PINGROUP_LSC1,
92 TEGRA_PINGROUP_LSCK,
93 TEGRA_PINGROUP_LSDA,
94 TEGRA_PINGROUP_LSDI,
95 TEGRA_PINGROUP_LSPI,
96 TEGRA_PINGROUP_LVP0,
97 TEGRA_PINGROUP_LVP1,
98 TEGRA_PINGROUP_LVS,
99 TEGRA_PINGROUP_OWC,
100 TEGRA_PINGROUP_PMC,
101 TEGRA_PINGROUP_PTA,
102 TEGRA_PINGROUP_RM,
103 TEGRA_PINGROUP_SDB,
104 TEGRA_PINGROUP_SDC,
105 TEGRA_PINGROUP_SDD,
106 TEGRA_PINGROUP_SDIO1,
107 TEGRA_PINGROUP_SLXA,
108 TEGRA_PINGROUP_SLXC,
109 TEGRA_PINGROUP_SLXD,
110 TEGRA_PINGROUP_SLXK,
111 TEGRA_PINGROUP_SPDI,
112 TEGRA_PINGROUP_SPDO,
113 TEGRA_PINGROUP_SPIA,
114 TEGRA_PINGROUP_SPIB,
115 TEGRA_PINGROUP_SPIC,
116 TEGRA_PINGROUP_SPID,
117 TEGRA_PINGROUP_SPIE,
118 TEGRA_PINGROUP_SPIF,
119 TEGRA_PINGROUP_SPIG,
120 TEGRA_PINGROUP_SPIH,
121 TEGRA_PINGROUP_UAA,
122 TEGRA_PINGROUP_UAB,
123 TEGRA_PINGROUP_UAC,
124 TEGRA_PINGROUP_UAD,
125 TEGRA_PINGROUP_UCA,
126 TEGRA_PINGROUP_UCB,
127 TEGRA_PINGROUP_UDA,
128 /* these pin groups only have pullup and pull down control */
129 TEGRA_PINGROUP_CK32,
130 TEGRA_PINGROUP_DDRC,
131 TEGRA_PINGROUP_PMCA,
132 TEGRA_PINGROUP_PMCB,
133 TEGRA_PINGROUP_PMCC,
134 TEGRA_PINGROUP_PMCD,
135 TEGRA_PINGROUP_PMCE,
136 TEGRA_PINGROUP_XM2C,
137 TEGRA_PINGROUP_XM2D,
138 TEGRA_MAX_PINGROUP,
139};
140
141enum tegra_drive_pingroup {
142 TEGRA_DRIVE_PINGROUP_AO1 = 0,
143 TEGRA_DRIVE_PINGROUP_AO2,
144 TEGRA_DRIVE_PINGROUP_AT1,
145 TEGRA_DRIVE_PINGROUP_AT2,
146 TEGRA_DRIVE_PINGROUP_CDEV1,
147 TEGRA_DRIVE_PINGROUP_CDEV2,
148 TEGRA_DRIVE_PINGROUP_CSUS,
149 TEGRA_DRIVE_PINGROUP_DAP1,
150 TEGRA_DRIVE_PINGROUP_DAP2,
151 TEGRA_DRIVE_PINGROUP_DAP3,
152 TEGRA_DRIVE_PINGROUP_DAP4,
153 TEGRA_DRIVE_PINGROUP_DBG,
154 TEGRA_DRIVE_PINGROUP_LCD1,
155 TEGRA_DRIVE_PINGROUP_LCD2,
156 TEGRA_DRIVE_PINGROUP_SDMMC2,
157 TEGRA_DRIVE_PINGROUP_SDMMC3,
158 TEGRA_DRIVE_PINGROUP_SPI,
159 TEGRA_DRIVE_PINGROUP_UAA,
160 TEGRA_DRIVE_PINGROUP_UAB,
161 TEGRA_DRIVE_PINGROUP_UART2,
162 TEGRA_DRIVE_PINGROUP_UART3,
163 TEGRA_DRIVE_PINGROUP_VI1,
164 TEGRA_DRIVE_PINGROUP_VI2,
165 TEGRA_DRIVE_PINGROUP_XM2A,
166 TEGRA_DRIVE_PINGROUP_XM2C,
167 TEGRA_DRIVE_PINGROUP_XM2D,
168 TEGRA_DRIVE_PINGROUP_XM2CLK,
169 TEGRA_DRIVE_PINGROUP_MEMCOMP,
170 TEGRA_DRIVE_PINGROUP_SDIO1,
171 TEGRA_DRIVE_PINGROUP_CRT,
172 TEGRA_DRIVE_PINGROUP_DDC,
173 TEGRA_DRIVE_PINGROUP_GMA,
174 TEGRA_DRIVE_PINGROUP_GMB,
175 TEGRA_DRIVE_PINGROUP_GMC,
176 TEGRA_DRIVE_PINGROUP_GMD,
177 TEGRA_DRIVE_PINGROUP_GME,
178 TEGRA_DRIVE_PINGROUP_OWR,
179 TEGRA_DRIVE_PINGROUP_UAD,
180 TEGRA_MAX_DRIVE_PINGROUP,
181};
182
183#endif
184
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
deleted file mode 100644
index c1aee3eb2df1..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
+++ /dev/null
@@ -1,320 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2010,2011 Nvidia, Inc.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
19#define __MACH_TEGRA_PINMUX_TEGRA30_H
20
21enum tegra_pingroup {
22 TEGRA_PINGROUP_ULPI_DATA0 = 0,
23 TEGRA_PINGROUP_ULPI_DATA1,
24 TEGRA_PINGROUP_ULPI_DATA2,
25 TEGRA_PINGROUP_ULPI_DATA3,
26 TEGRA_PINGROUP_ULPI_DATA4,
27 TEGRA_PINGROUP_ULPI_DATA5,
28 TEGRA_PINGROUP_ULPI_DATA6,
29 TEGRA_PINGROUP_ULPI_DATA7,
30 TEGRA_PINGROUP_ULPI_CLK,
31 TEGRA_PINGROUP_ULPI_DIR,
32 TEGRA_PINGROUP_ULPI_NXT,
33 TEGRA_PINGROUP_ULPI_STP,
34 TEGRA_PINGROUP_DAP3_FS,
35 TEGRA_PINGROUP_DAP3_DIN,
36 TEGRA_PINGROUP_DAP3_DOUT,
37 TEGRA_PINGROUP_DAP3_SCLK,
38 TEGRA_PINGROUP_GPIO_PV0,
39 TEGRA_PINGROUP_GPIO_PV1,
40 TEGRA_PINGROUP_SDMMC1_CLK,
41 TEGRA_PINGROUP_SDMMC1_CMD,
42 TEGRA_PINGROUP_SDMMC1_DAT3,
43 TEGRA_PINGROUP_SDMMC1_DAT2,
44 TEGRA_PINGROUP_SDMMC1_DAT1,
45 TEGRA_PINGROUP_SDMMC1_DAT0,
46 TEGRA_PINGROUP_GPIO_PV2,
47 TEGRA_PINGROUP_GPIO_PV3,
48 TEGRA_PINGROUP_CLK2_OUT,
49 TEGRA_PINGROUP_CLK2_REQ,
50 TEGRA_PINGROUP_LCD_PWR1,
51 TEGRA_PINGROUP_LCD_PWR2,
52 TEGRA_PINGROUP_LCD_SDIN,
53 TEGRA_PINGROUP_LCD_SDOUT,
54 TEGRA_PINGROUP_LCD_WR_N,
55 TEGRA_PINGROUP_LCD_CS0_N,
56 TEGRA_PINGROUP_LCD_DC0,
57 TEGRA_PINGROUP_LCD_SCK,
58 TEGRA_PINGROUP_LCD_PWR0,
59 TEGRA_PINGROUP_LCD_PCLK,
60 TEGRA_PINGROUP_LCD_DE,
61 TEGRA_PINGROUP_LCD_HSYNC,
62 TEGRA_PINGROUP_LCD_VSYNC,
63 TEGRA_PINGROUP_LCD_D0,
64 TEGRA_PINGROUP_LCD_D1,
65 TEGRA_PINGROUP_LCD_D2,
66 TEGRA_PINGROUP_LCD_D3,
67 TEGRA_PINGROUP_LCD_D4,
68 TEGRA_PINGROUP_LCD_D5,
69 TEGRA_PINGROUP_LCD_D6,
70 TEGRA_PINGROUP_LCD_D7,
71 TEGRA_PINGROUP_LCD_D8,
72 TEGRA_PINGROUP_LCD_D9,
73 TEGRA_PINGROUP_LCD_D10,
74 TEGRA_PINGROUP_LCD_D11,
75 TEGRA_PINGROUP_LCD_D12,
76 TEGRA_PINGROUP_LCD_D13,
77 TEGRA_PINGROUP_LCD_D14,
78 TEGRA_PINGROUP_LCD_D15,
79 TEGRA_PINGROUP_LCD_D16,
80 TEGRA_PINGROUP_LCD_D17,
81 TEGRA_PINGROUP_LCD_D18,
82 TEGRA_PINGROUP_LCD_D19,
83 TEGRA_PINGROUP_LCD_D20,
84 TEGRA_PINGROUP_LCD_D21,
85 TEGRA_PINGROUP_LCD_D22,
86 TEGRA_PINGROUP_LCD_D23,
87 TEGRA_PINGROUP_LCD_CS1_N,
88 TEGRA_PINGROUP_LCD_M1,
89 TEGRA_PINGROUP_LCD_DC1,
90 TEGRA_PINGROUP_HDMI_INT,
91 TEGRA_PINGROUP_DDC_SCL,
92 TEGRA_PINGROUP_DDC_SDA,
93 TEGRA_PINGROUP_CRT_HSYNC,
94 TEGRA_PINGROUP_CRT_VSYNC,
95 TEGRA_PINGROUP_VI_D0,
96 TEGRA_PINGROUP_VI_D1,
97 TEGRA_PINGROUP_VI_D2,
98 TEGRA_PINGROUP_VI_D3,
99 TEGRA_PINGROUP_VI_D4,
100 TEGRA_PINGROUP_VI_D5,
101 TEGRA_PINGROUP_VI_D6,
102 TEGRA_PINGROUP_VI_D7,
103 TEGRA_PINGROUP_VI_D8,
104 TEGRA_PINGROUP_VI_D9,
105 TEGRA_PINGROUP_VI_D10,
106 TEGRA_PINGROUP_VI_D11,
107 TEGRA_PINGROUP_VI_PCLK,
108 TEGRA_PINGROUP_VI_MCLK,
109 TEGRA_PINGROUP_VI_VSYNC,
110 TEGRA_PINGROUP_VI_HSYNC,
111 TEGRA_PINGROUP_UART2_RXD,
112 TEGRA_PINGROUP_UART2_TXD,
113 TEGRA_PINGROUP_UART2_RTS_N,
114 TEGRA_PINGROUP_UART2_CTS_N,
115 TEGRA_PINGROUP_UART3_TXD,
116 TEGRA_PINGROUP_UART3_RXD,
117 TEGRA_PINGROUP_UART3_CTS_N,
118 TEGRA_PINGROUP_UART3_RTS_N,
119 TEGRA_PINGROUP_GPIO_PU0,
120 TEGRA_PINGROUP_GPIO_PU1,
121 TEGRA_PINGROUP_GPIO_PU2,
122 TEGRA_PINGROUP_GPIO_PU3,
123 TEGRA_PINGROUP_GPIO_PU4,
124 TEGRA_PINGROUP_GPIO_PU5,
125 TEGRA_PINGROUP_GPIO_PU6,
126 TEGRA_PINGROUP_GEN1_I2C_SDA,
127 TEGRA_PINGROUP_GEN1_I2C_SCL,
128 TEGRA_PINGROUP_DAP4_FS,
129 TEGRA_PINGROUP_DAP4_DIN,
130 TEGRA_PINGROUP_DAP4_DOUT,
131 TEGRA_PINGROUP_DAP4_SCLK,
132 TEGRA_PINGROUP_CLK3_OUT,
133 TEGRA_PINGROUP_CLK3_REQ,
134 TEGRA_PINGROUP_GMI_WP_N,
135 TEGRA_PINGROUP_GMI_IORDY,
136 TEGRA_PINGROUP_GMI_WAIT,
137 TEGRA_PINGROUP_GMI_ADV_N,
138 TEGRA_PINGROUP_GMI_CLK,
139 TEGRA_PINGROUP_GMI_CS0_N,
140 TEGRA_PINGROUP_GMI_CS1_N,
141 TEGRA_PINGROUP_GMI_CS2_N,
142 TEGRA_PINGROUP_GMI_CS3_N,
143 TEGRA_PINGROUP_GMI_CS4_N,
144 TEGRA_PINGROUP_GMI_CS6_N,
145 TEGRA_PINGROUP_GMI_CS7_N,
146 TEGRA_PINGROUP_GMI_AD0,
147 TEGRA_PINGROUP_GMI_AD1,
148 TEGRA_PINGROUP_GMI_AD2,
149 TEGRA_PINGROUP_GMI_AD3,
150 TEGRA_PINGROUP_GMI_AD4,
151 TEGRA_PINGROUP_GMI_AD5,
152 TEGRA_PINGROUP_GMI_AD6,
153 TEGRA_PINGROUP_GMI_AD7,
154 TEGRA_PINGROUP_GMI_AD8,
155 TEGRA_PINGROUP_GMI_AD9,
156 TEGRA_PINGROUP_GMI_AD10,
157 TEGRA_PINGROUP_GMI_AD11,
158 TEGRA_PINGROUP_GMI_AD12,
159 TEGRA_PINGROUP_GMI_AD13,
160 TEGRA_PINGROUP_GMI_AD14,
161 TEGRA_PINGROUP_GMI_AD15,
162 TEGRA_PINGROUP_GMI_A16,
163 TEGRA_PINGROUP_GMI_A17,
164 TEGRA_PINGROUP_GMI_A18,
165 TEGRA_PINGROUP_GMI_A19,
166 TEGRA_PINGROUP_GMI_WR_N,
167 TEGRA_PINGROUP_GMI_OE_N,
168 TEGRA_PINGROUP_GMI_DQS,
169 TEGRA_PINGROUP_GMI_RST_N,
170 TEGRA_PINGROUP_GEN2_I2C_SCL,
171 TEGRA_PINGROUP_GEN2_I2C_SDA,
172 TEGRA_PINGROUP_SDMMC4_CLK,
173 TEGRA_PINGROUP_SDMMC4_CMD,
174 TEGRA_PINGROUP_SDMMC4_DAT0,
175 TEGRA_PINGROUP_SDMMC4_DAT1,
176 TEGRA_PINGROUP_SDMMC4_DAT2,
177 TEGRA_PINGROUP_SDMMC4_DAT3,
178 TEGRA_PINGROUP_SDMMC4_DAT4,
179 TEGRA_PINGROUP_SDMMC4_DAT5,
180 TEGRA_PINGROUP_SDMMC4_DAT6,
181 TEGRA_PINGROUP_SDMMC4_DAT7,
182 TEGRA_PINGROUP_SDMMC4_RST_N,
183 TEGRA_PINGROUP_CAM_MCLK,
184 TEGRA_PINGROUP_GPIO_PCC1,
185 TEGRA_PINGROUP_GPIO_PBB0,
186 TEGRA_PINGROUP_CAM_I2C_SCL,
187 TEGRA_PINGROUP_CAM_I2C_SDA,
188 TEGRA_PINGROUP_GPIO_PBB3,
189 TEGRA_PINGROUP_GPIO_PBB4,
190 TEGRA_PINGROUP_GPIO_PBB5,
191 TEGRA_PINGROUP_GPIO_PBB6,
192 TEGRA_PINGROUP_GPIO_PBB7,
193 TEGRA_PINGROUP_GPIO_PCC2,
194 TEGRA_PINGROUP_JTAG_RTCK,
195 TEGRA_PINGROUP_PWR_I2C_SCL,
196 TEGRA_PINGROUP_PWR_I2C_SDA,
197 TEGRA_PINGROUP_KB_ROW0,
198 TEGRA_PINGROUP_KB_ROW1,
199 TEGRA_PINGROUP_KB_ROW2,
200 TEGRA_PINGROUP_KB_ROW3,
201 TEGRA_PINGROUP_KB_ROW4,
202 TEGRA_PINGROUP_KB_ROW5,
203 TEGRA_PINGROUP_KB_ROW6,
204 TEGRA_PINGROUP_KB_ROW7,
205 TEGRA_PINGROUP_KB_ROW8,
206 TEGRA_PINGROUP_KB_ROW9,
207 TEGRA_PINGROUP_KB_ROW10,
208 TEGRA_PINGROUP_KB_ROW11,
209 TEGRA_PINGROUP_KB_ROW12,
210 TEGRA_PINGROUP_KB_ROW13,
211 TEGRA_PINGROUP_KB_ROW14,
212 TEGRA_PINGROUP_KB_ROW15,
213 TEGRA_PINGROUP_KB_COL0,
214 TEGRA_PINGROUP_KB_COL1,
215 TEGRA_PINGROUP_KB_COL2,
216 TEGRA_PINGROUP_KB_COL3,
217 TEGRA_PINGROUP_KB_COL4,
218 TEGRA_PINGROUP_KB_COL5,
219 TEGRA_PINGROUP_KB_COL6,
220 TEGRA_PINGROUP_KB_COL7,
221 TEGRA_PINGROUP_CLK_32K_OUT,
222 TEGRA_PINGROUP_SYS_CLK_REQ,
223 TEGRA_PINGROUP_CORE_PWR_REQ,
224 TEGRA_PINGROUP_CPU_PWR_REQ,
225 TEGRA_PINGROUP_PWR_INT_N,
226 TEGRA_PINGROUP_CLK_32K_IN,
227 TEGRA_PINGROUP_OWR,
228 TEGRA_PINGROUP_DAP1_FS,
229 TEGRA_PINGROUP_DAP1_DIN,
230 TEGRA_PINGROUP_DAP1_DOUT,
231 TEGRA_PINGROUP_DAP1_SCLK,
232 TEGRA_PINGROUP_CLK1_REQ,
233 TEGRA_PINGROUP_CLK1_OUT,
234 TEGRA_PINGROUP_SPDIF_IN,
235 TEGRA_PINGROUP_SPDIF_OUT,
236 TEGRA_PINGROUP_DAP2_FS,
237 TEGRA_PINGROUP_DAP2_DIN,
238 TEGRA_PINGROUP_DAP2_DOUT,
239 TEGRA_PINGROUP_DAP2_SCLK,
240 TEGRA_PINGROUP_SPI2_MOSI,
241 TEGRA_PINGROUP_SPI2_MISO,
242 TEGRA_PINGROUP_SPI2_CS0_N,
243 TEGRA_PINGROUP_SPI2_SCK,
244 TEGRA_PINGROUP_SPI1_MOSI,
245 TEGRA_PINGROUP_SPI1_SCK,
246 TEGRA_PINGROUP_SPI1_CS0_N,
247 TEGRA_PINGROUP_SPI1_MISO,
248 TEGRA_PINGROUP_SPI2_CS1_N,
249 TEGRA_PINGROUP_SPI2_CS2_N,
250 TEGRA_PINGROUP_SDMMC3_CLK,
251 TEGRA_PINGROUP_SDMMC3_CMD,
252 TEGRA_PINGROUP_SDMMC3_DAT0,
253 TEGRA_PINGROUP_SDMMC3_DAT1,
254 TEGRA_PINGROUP_SDMMC3_DAT2,
255 TEGRA_PINGROUP_SDMMC3_DAT3,
256 TEGRA_PINGROUP_SDMMC3_DAT4,
257 TEGRA_PINGROUP_SDMMC3_DAT5,
258 TEGRA_PINGROUP_SDMMC3_DAT6,
259 TEGRA_PINGROUP_SDMMC3_DAT7,
260 TEGRA_PINGROUP_PEX_L0_PRSNT_N,
261 TEGRA_PINGROUP_PEX_L0_RST_N,
262 TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
263 TEGRA_PINGROUP_PEX_WAKE_N,
264 TEGRA_PINGROUP_PEX_L1_PRSNT_N,
265 TEGRA_PINGROUP_PEX_L1_RST_N,
266 TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
267 TEGRA_PINGROUP_PEX_L2_PRSNT_N,
268 TEGRA_PINGROUP_PEX_L2_RST_N,
269 TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
270 TEGRA_PINGROUP_HDMI_CEC,
271 TEGRA_MAX_PINGROUP,
272};
273
274enum tegra_drive_pingroup {
275 TEGRA_DRIVE_PINGROUP_AO1 = 0,
276 TEGRA_DRIVE_PINGROUP_AO2,
277 TEGRA_DRIVE_PINGROUP_AT1,
278 TEGRA_DRIVE_PINGROUP_AT2,
279 TEGRA_DRIVE_PINGROUP_AT3,
280 TEGRA_DRIVE_PINGROUP_AT4,
281 TEGRA_DRIVE_PINGROUP_AT5,
282 TEGRA_DRIVE_PINGROUP_CDEV1,
283 TEGRA_DRIVE_PINGROUP_CDEV2,
284 TEGRA_DRIVE_PINGROUP_CSUS,
285 TEGRA_DRIVE_PINGROUP_DAP1,
286 TEGRA_DRIVE_PINGROUP_DAP2,
287 TEGRA_DRIVE_PINGROUP_DAP3,
288 TEGRA_DRIVE_PINGROUP_DAP4,
289 TEGRA_DRIVE_PINGROUP_DBG,
290 TEGRA_DRIVE_PINGROUP_LCD1,
291 TEGRA_DRIVE_PINGROUP_LCD2,
292 TEGRA_DRIVE_PINGROUP_SDIO2,
293 TEGRA_DRIVE_PINGROUP_SDIO3,
294 TEGRA_DRIVE_PINGROUP_SPI,
295 TEGRA_DRIVE_PINGROUP_UAA,
296 TEGRA_DRIVE_PINGROUP_UAB,
297 TEGRA_DRIVE_PINGROUP_UART2,
298 TEGRA_DRIVE_PINGROUP_UART3,
299 TEGRA_DRIVE_PINGROUP_VI1,
300 TEGRA_DRIVE_PINGROUP_SDIO1,
301 TEGRA_DRIVE_PINGROUP_CRT,
302 TEGRA_DRIVE_PINGROUP_DDC,
303 TEGRA_DRIVE_PINGROUP_GMA,
304 TEGRA_DRIVE_PINGROUP_GMB,
305 TEGRA_DRIVE_PINGROUP_GMC,
306 TEGRA_DRIVE_PINGROUP_GMD,
307 TEGRA_DRIVE_PINGROUP_GME,
308 TEGRA_DRIVE_PINGROUP_GMF,
309 TEGRA_DRIVE_PINGROUP_GMG,
310 TEGRA_DRIVE_PINGROUP_GMH,
311 TEGRA_DRIVE_PINGROUP_OWR,
312 TEGRA_DRIVE_PINGROUP_UAD,
313 TEGRA_DRIVE_PINGROUP_GPV,
314 TEGRA_DRIVE_PINGROUP_DEV3,
315 TEGRA_DRIVE_PINGROUP_CEC,
316 TEGRA_MAX_DRIVE_PINGROUP,
317};
318
319#endif
320
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
deleted file mode 100644
index 055f1792c8ff..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ /dev/null
@@ -1,302 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2010,2011 Nvidia, Inc.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __MACH_TEGRA_PINMUX_H
19#define __MACH_TEGRA_PINMUX_H
20
21enum tegra_mux_func {
22 TEGRA_MUX_RSVD = 0x8000,
23 TEGRA_MUX_RSVD1 = 0x8000,
24 TEGRA_MUX_RSVD2 = 0x8001,
25 TEGRA_MUX_RSVD3 = 0x8002,
26 TEGRA_MUX_RSVD4 = 0x8003,
27 TEGRA_MUX_INVALID = 0x4000,
28 TEGRA_MUX_NONE = -1,
29 TEGRA_MUX_AHB_CLK,
30 TEGRA_MUX_APB_CLK,
31 TEGRA_MUX_AUDIO_SYNC,
32 TEGRA_MUX_CRT,
33 TEGRA_MUX_DAP1,
34 TEGRA_MUX_DAP2,
35 TEGRA_MUX_DAP3,
36 TEGRA_MUX_DAP4,
37 TEGRA_MUX_DAP5,
38 TEGRA_MUX_DISPLAYA,
39 TEGRA_MUX_DISPLAYB,
40 TEGRA_MUX_EMC_TEST0_DLL,
41 TEGRA_MUX_EMC_TEST1_DLL,
42 TEGRA_MUX_GMI,
43 TEGRA_MUX_GMI_INT,
44 TEGRA_MUX_HDMI,
45 TEGRA_MUX_I2C,
46 TEGRA_MUX_I2C2,
47 TEGRA_MUX_I2C3,
48 TEGRA_MUX_IDE,
49 TEGRA_MUX_IRDA,
50 TEGRA_MUX_KBC,
51 TEGRA_MUX_MIO,
52 TEGRA_MUX_MIPI_HS,
53 TEGRA_MUX_NAND,
54 TEGRA_MUX_OSC,
55 TEGRA_MUX_OWR,
56 TEGRA_MUX_PCIE,
57 TEGRA_MUX_PLLA_OUT,
58 TEGRA_MUX_PLLC_OUT1,
59 TEGRA_MUX_PLLM_OUT1,
60 TEGRA_MUX_PLLP_OUT2,
61 TEGRA_MUX_PLLP_OUT3,
62 TEGRA_MUX_PLLP_OUT4,
63 TEGRA_MUX_PWM,
64 TEGRA_MUX_PWR_INTR,
65 TEGRA_MUX_PWR_ON,
66 TEGRA_MUX_RTCK,
67 TEGRA_MUX_SDIO1,
68 TEGRA_MUX_SDIO2,
69 TEGRA_MUX_SDIO3,
70 TEGRA_MUX_SDIO4,
71 TEGRA_MUX_SFLASH,
72 TEGRA_MUX_SPDIF,
73 TEGRA_MUX_SPI1,
74 TEGRA_MUX_SPI2,
75 TEGRA_MUX_SPI2_ALT,
76 TEGRA_MUX_SPI3,
77 TEGRA_MUX_SPI4,
78 TEGRA_MUX_TRACE,
79 TEGRA_MUX_TWC,
80 TEGRA_MUX_UARTA,
81 TEGRA_MUX_UARTB,
82 TEGRA_MUX_UARTC,
83 TEGRA_MUX_UARTD,
84 TEGRA_MUX_UARTE,
85 TEGRA_MUX_ULPI,
86 TEGRA_MUX_VI,
87 TEGRA_MUX_VI_SENSOR_CLK,
88 TEGRA_MUX_XIO,
89 TEGRA_MUX_BLINK,
90 TEGRA_MUX_CEC,
91 TEGRA_MUX_CLK12,
92 TEGRA_MUX_DAP,
93 TEGRA_MUX_DAPSDMMC2,
94 TEGRA_MUX_DDR,
95 TEGRA_MUX_DEV3,
96 TEGRA_MUX_DTV,
97 TEGRA_MUX_VI_ALT1,
98 TEGRA_MUX_VI_ALT2,
99 TEGRA_MUX_VI_ALT3,
100 TEGRA_MUX_EMC_DLL,
101 TEGRA_MUX_EXTPERIPH1,
102 TEGRA_MUX_EXTPERIPH2,
103 TEGRA_MUX_EXTPERIPH3,
104 TEGRA_MUX_GMI_ALT,
105 TEGRA_MUX_HDA,
106 TEGRA_MUX_HSI,
107 TEGRA_MUX_I2C4,
108 TEGRA_MUX_I2C5,
109 TEGRA_MUX_I2CPWR,
110 TEGRA_MUX_I2S0,
111 TEGRA_MUX_I2S1,
112 TEGRA_MUX_I2S2,
113 TEGRA_MUX_I2S3,
114 TEGRA_MUX_I2S4,
115 TEGRA_MUX_NAND_ALT,
116 TEGRA_MUX_POPSDIO4,
117 TEGRA_MUX_POPSDMMC4,
118 TEGRA_MUX_PWM0,
119 TEGRA_MUX_PWM1,
120 TEGRA_MUX_PWM2,
121 TEGRA_MUX_PWM3,
122 TEGRA_MUX_SATA,
123 TEGRA_MUX_SPI5,
124 TEGRA_MUX_SPI6,
125 TEGRA_MUX_SYSCLK,
126 TEGRA_MUX_VGP1,
127 TEGRA_MUX_VGP2,
128 TEGRA_MUX_VGP3,
129 TEGRA_MUX_VGP4,
130 TEGRA_MUX_VGP5,
131 TEGRA_MUX_VGP6,
132 TEGRA_MUX_SAFE,
133 TEGRA_MAX_MUX,
134};
135
136enum tegra_pullupdown {
137 TEGRA_PUPD_NORMAL = 0,
138 TEGRA_PUPD_PULL_DOWN,
139 TEGRA_PUPD_PULL_UP,
140};
141
142enum tegra_tristate {
143 TEGRA_TRI_NORMAL = 0,
144 TEGRA_TRI_TRISTATE = 1,
145};
146
147enum tegra_pin_io {
148 TEGRA_PIN_OUTPUT = 0,
149 TEGRA_PIN_INPUT = 1,
150};
151
152enum tegra_vddio {
153 TEGRA_VDDIO_BB = 0,
154 TEGRA_VDDIO_LCD,
155 TEGRA_VDDIO_VI,
156 TEGRA_VDDIO_UART,
157 TEGRA_VDDIO_DDR,
158 TEGRA_VDDIO_NAND,
159 TEGRA_VDDIO_SYS,
160 TEGRA_VDDIO_AUDIO,
161 TEGRA_VDDIO_SD,
162 TEGRA_VDDIO_CAM,
163 TEGRA_VDDIO_GMI,
164 TEGRA_VDDIO_PEXCTL,
165 TEGRA_VDDIO_SDMMC1,
166 TEGRA_VDDIO_SDMMC3,
167 TEGRA_VDDIO_SDMMC4,
168};
169
170struct tegra_pingroup_config {
171 int pingroup;
172 enum tegra_mux_func func;
173 enum tegra_pullupdown pupd;
174 enum tegra_tristate tristate;
175};
176
177enum tegra_slew {
178 TEGRA_SLEW_FASTEST = 0,
179 TEGRA_SLEW_FAST,
180 TEGRA_SLEW_SLOW,
181 TEGRA_SLEW_SLOWEST,
182 TEGRA_MAX_SLEW,
183};
184
185enum tegra_pull_strength {
186 TEGRA_PULL_0 = 0,
187 TEGRA_PULL_1,
188 TEGRA_PULL_2,
189 TEGRA_PULL_3,
190 TEGRA_PULL_4,
191 TEGRA_PULL_5,
192 TEGRA_PULL_6,
193 TEGRA_PULL_7,
194 TEGRA_PULL_8,
195 TEGRA_PULL_9,
196 TEGRA_PULL_10,
197 TEGRA_PULL_11,
198 TEGRA_PULL_12,
199 TEGRA_PULL_13,
200 TEGRA_PULL_14,
201 TEGRA_PULL_15,
202 TEGRA_PULL_16,
203 TEGRA_PULL_17,
204 TEGRA_PULL_18,
205 TEGRA_PULL_19,
206 TEGRA_PULL_20,
207 TEGRA_PULL_21,
208 TEGRA_PULL_22,
209 TEGRA_PULL_23,
210 TEGRA_PULL_24,
211 TEGRA_PULL_25,
212 TEGRA_PULL_26,
213 TEGRA_PULL_27,
214 TEGRA_PULL_28,
215 TEGRA_PULL_29,
216 TEGRA_PULL_30,
217 TEGRA_PULL_31,
218 TEGRA_MAX_PULL,
219};
220
221enum tegra_drive {
222 TEGRA_DRIVE_DIV_8 = 0,
223 TEGRA_DRIVE_DIV_4,
224 TEGRA_DRIVE_DIV_2,
225 TEGRA_DRIVE_DIV_1,
226 TEGRA_MAX_DRIVE,
227};
228
229enum tegra_hsm {
230 TEGRA_HSM_DISABLE = 0,
231 TEGRA_HSM_ENABLE,
232};
233
234enum tegra_schmitt {
235 TEGRA_SCHMITT_DISABLE = 0,
236 TEGRA_SCHMITT_ENABLE,
237};
238
239struct tegra_drive_pingroup_config {
240 int pingroup;
241 enum tegra_hsm hsm;
242 enum tegra_schmitt schmitt;
243 enum tegra_drive drive;
244 enum tegra_pull_strength pull_down;
245 enum tegra_pull_strength pull_up;
246 enum tegra_slew slew_rising;
247 enum tegra_slew slew_falling;
248};
249
250struct tegra_drive_pingroup_desc {
251 const char *name;
252 s16 reg_bank;
253 s16 reg;
254};
255
256struct tegra_pingroup_desc {
257 const char *name;
258 int funcs[4];
259 int func_safe;
260 int vddio;
261 enum tegra_pin_io io_default;
262 s16 tri_bank; /* Register bank the tri_reg exists within */
263 s16 mux_bank; /* Register bank the mux_reg exists within */
264 s16 pupd_bank; /* Register bank the pupd_reg exists within */
265 s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */
266 s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */
267 s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */
268 s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
269 s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
270 s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
271 s8 lock_bit; /* offset of the LOCK bit into mux register bit */
272 s8 od_bit; /* offset of the OD bit into mux register bit */
273 s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
274};
275
276typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
277 int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
278 int *pgdrive_max);
279
280void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
281 const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
282
283void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
284 const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
285
286int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
287int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
288
289void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
290 int len);
291
292void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
293 int len);
294void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
295 int len);
296void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
297 int len);
298void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
299 int len, enum tegra_tristate tristate);
300void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
301 int len, enum tegra_pullupdown pupd);
302#endif
diff --git a/arch/arm/mach-tegra/pinmux-tegra20-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c
deleted file mode 100644
index 734add1280b7..000000000000
--- a/arch/arm/mach-tegra/pinmux-tegra20-tables.c
+++ /dev/null
@@ -1,244 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c
3 *
4 * Common pinmux configurations for Tegra20 SoCs
5 *
6 * Copyright (C) 2010 NVIDIA Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 */
22
23#include <linux/kernel.h>
24#include <linux/errno.h>
25#include <linux/spinlock.h>
26#include <linux/io.h>
27#include <linux/init.h>
28#include <linux/string.h>
29
30#include <mach/iomap.h>
31#include <mach/pinmux.h>
32#include <mach/pinmux-tegra20.h>
33#include <mach/suspend.h>
34
35#define TRISTATE_REG_A 0x14
36#define PIN_MUX_CTL_REG_A 0x80
37#define PULLUPDOWN_REG_A 0xa0
38#define PINGROUP_REG_A 0x868
39
40#define DRIVE_PINGROUP(pg_name, r) \
41 [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
42 .name = #pg_name, \
43 .reg_bank = 3, \
44 .reg = ((r) - PINGROUP_REG_A) \
45 }
46
47static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
48 DRIVE_PINGROUP(AO1, 0x868),
49 DRIVE_PINGROUP(AO2, 0x86c),
50 DRIVE_PINGROUP(AT1, 0x870),
51 DRIVE_PINGROUP(AT2, 0x874),
52 DRIVE_PINGROUP(CDEV1, 0x878),
53 DRIVE_PINGROUP(CDEV2, 0x87c),
54 DRIVE_PINGROUP(CSUS, 0x880),
55 DRIVE_PINGROUP(DAP1, 0x884),
56 DRIVE_PINGROUP(DAP2, 0x888),
57 DRIVE_PINGROUP(DAP3, 0x88c),
58 DRIVE_PINGROUP(DAP4, 0x890),
59 DRIVE_PINGROUP(DBG, 0x894),
60 DRIVE_PINGROUP(LCD1, 0x898),
61 DRIVE_PINGROUP(LCD2, 0x89c),
62 DRIVE_PINGROUP(SDMMC2, 0x8a0),
63 DRIVE_PINGROUP(SDMMC3, 0x8a4),
64 DRIVE_PINGROUP(SPI, 0x8a8),
65 DRIVE_PINGROUP(UAA, 0x8ac),
66 DRIVE_PINGROUP(UAB, 0x8b0),
67 DRIVE_PINGROUP(UART2, 0x8b4),
68 DRIVE_PINGROUP(UART3, 0x8b8),
69 DRIVE_PINGROUP(VI1, 0x8bc),
70 DRIVE_PINGROUP(VI2, 0x8c0),
71 DRIVE_PINGROUP(XM2A, 0x8c4),
72 DRIVE_PINGROUP(XM2C, 0x8c8),
73 DRIVE_PINGROUP(XM2D, 0x8cc),
74 DRIVE_PINGROUP(XM2CLK, 0x8d0),
75 DRIVE_PINGROUP(MEMCOMP, 0x8d4),
76 DRIVE_PINGROUP(SDIO1, 0x8e0),
77 DRIVE_PINGROUP(CRT, 0x8ec),
78 DRIVE_PINGROUP(DDC, 0x8f0),
79 DRIVE_PINGROUP(GMA, 0x8f4),
80 DRIVE_PINGROUP(GMB, 0x8f8),
81 DRIVE_PINGROUP(GMC, 0x8fc),
82 DRIVE_PINGROUP(GMD, 0x900),
83 DRIVE_PINGROUP(GME, 0x904),
84 DRIVE_PINGROUP(OWR, 0x908),
85 DRIVE_PINGROUP(UAD, 0x90c),
86};
87
88#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, f_safe, \
89 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
90 [TEGRA_PINGROUP_ ## pg_name] = { \
91 .name = #pg_name, \
92 .vddio = TEGRA_VDDIO_ ## vdd, \
93 .funcs = { \
94 TEGRA_MUX_ ## f0, \
95 TEGRA_MUX_ ## f1, \
96 TEGRA_MUX_ ## f2, \
97 TEGRA_MUX_ ## f3, \
98 }, \
99 .func_safe = TEGRA_MUX_ ## f_safe, \
100 .tri_bank = 0, \
101 .tri_reg = ((tri_r) - TRISTATE_REG_A), \
102 .tri_bit = tri_b, \
103 .mux_bank = 1, \
104 .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
105 .mux_bit = mux_b, \
106 .pupd_bank = 2, \
107 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
108 .pupd_bit = pupd_b, \
109 .lock_bit = -1, \
110 .od_bit = -1, \
111 .ioreset_bit = -1, \
112 .io_default = -1, \
113 }
114
115static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
116 PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0),
117 PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2),
118 PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4),
119 PINGROUP(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 3, 0x80, 20, 0xA0, 6),
120 PINGROUP(ATE, NAND, IDE, NAND, GMI, RSVD, IDE, 0x18, 25, 0x80, 12, 0xA0, 8),
121 PINGROUP(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC, 0x14, 4, 0x88, 2, 0xA8, 0),
122 PINGROUP(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC, 0x14, 5, 0x88, 4, 0xA8, 2),
123 PINGROUP(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD, 0x20, 14, 0x98, 20, 0xA4, 24),
124 PINGROUP(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6, 0x88, 6, 0xAC, 24),
125 PINGROUP(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1, 0x14, 7, 0x88, 20, 0xA0, 10),
126 PINGROUP(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2, 0x14, 8, 0x88, 22, 0xA0, 12),
127 PINGROUP(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3, 0x14, 9, 0x88, 24, 0xA0, 14),
128 PINGROUP(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4, 0x14, 10, 0x88, 26, 0xA0, 16),
129 PINGROUP(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4, 0x18, 31, 0x88, 0, 0xB0, 28),
130 PINGROUP(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4, 0x14, 11, 0x84, 20, 0xA0, 18),
131 PINGROUP(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 12, 0x84, 22, 0xA0, 20),
132 PINGROUP(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1, 0x14, 13, 0x84, 26, 0xA0, 22),
133 PINGROUP(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1, 0x14, 14, 0x84, 28, 0xA0, 24),
134 PINGROUP(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 15, 0x84, 30, 0xA0, 26),
135 PINGROUP(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4, 0x20, 12, 0x98, 30, 0xA0, 28),
136 PINGROUP(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3, 0x14, 28, 0x84, 0, 0xB0, 20),
137 PINGROUP(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI, 0x18, 29, 0x88, 28, 0xB0, 22),
138 PINGROUP(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4, 0x14, 29, 0x84, 2, 0xB0, 24),
139 PINGROUP(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI, 0x18, 30, 0x88, 30, 0xB0, 26),
140 PINGROUP(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI, 0x18, 0, 0x8C, 0, 0xA8, 24),
141 PINGROUP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4, 0x14, 16, 0x8C, 4, 0xA4, 20),
142 PINGROUP(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK, 0x20, 11, 0x98, 28, 0xA4, 6),
143 PINGROUP(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE, 0x14, 17, 0x8C, 2, 0xA0, 30),
144 PINGROUP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI, 0x1C, 23, 0x84, 4, 0xAC, 22),
145 PINGROUP(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 18, 0x88, 8, 0xA4, 2),
146 PINGROUP(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 20, 0x88, 18, 0xA8, 22),
147 PINGROUP(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 19, 0x88, 16, 0xA8, 20),
148 PINGROUP(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC, 0x14, 22, 0x88, 10, 0xA4, 8),
149 PINGROUP(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x14, 21, 0x88, 12, 0xA4, 10),
150 PINGROUP(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC, 0x18, 26, 0x88, 14, 0xA4, 12),
151 PINGROUP(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x20, 10, 0x98, 26, 0xA4, 14),
152 PINGROUP(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC, 0x14, 26, 0x80, 28, 0xB0, 2),
153 PINGROUP(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC, 0x14, 27, 0x80, 26, 0xB0, 0),
154 PINGROUP(LCSN, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 31, 0x90, 12, 0xAC, 20),
155 PINGROUP(LD0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 0, 0x94, 0, 0xAC, 12),
156 PINGROUP(LD1, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 1, 0x94, 2, 0xAC, 12),
157 PINGROUP(LD10, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 10, 0x94, 20, 0xAC, 12),
158 PINGROUP(LD11, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 11, 0x94, 22, 0xAC, 12),
159 PINGROUP(LD12, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 12, 0x94, 24, 0xAC, 12),
160 PINGROUP(LD13, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 13, 0x94, 26, 0xAC, 12),
161 PINGROUP(LD14, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 14, 0x94, 28, 0xAC, 12),
162 PINGROUP(LD15, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 15, 0x94, 30, 0xAC, 12),
163 PINGROUP(LD16, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 16, 0x98, 0, 0xAC, 12),
164 PINGROUP(LD17, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 17, 0x98, 2, 0xAC, 12),
165 PINGROUP(LD2, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 2, 0x94, 4, 0xAC, 12),
166 PINGROUP(LD3, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 3, 0x94, 6, 0xAC, 12),
167 PINGROUP(LD4, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 4, 0x94, 8, 0xAC, 12),
168 PINGROUP(LD5, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 5, 0x94, 10, 0xAC, 12),
169 PINGROUP(LD6, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 6, 0x94, 12, 0xAC, 12),
170 PINGROUP(LD7, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 7, 0x94, 14, 0xAC, 12),
171 PINGROUP(LD8, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 8, 0x94, 16, 0xAC, 12),
172 PINGROUP(LD9, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 9, 0x94, 18, 0xAC, 12),
173 PINGROUP(LDC, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 30, 0x90, 14, 0xAC, 20),
174 PINGROUP(LDI, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 6, 0x98, 16, 0xAC, 18),
175 PINGROUP(LHP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 18, 0x98, 10, 0xAC, 16),
176 PINGROUP(LHP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 19, 0x98, 4, 0xAC, 14),
177 PINGROUP(LHP2, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 20, 0x98, 6, 0xAC, 14),
178 PINGROUP(LHS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x20, 7, 0x90, 22, 0xAC, 22),
179 PINGROUP(LM0, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 24, 0x90, 26, 0xAC, 22),
180 PINGROUP(LM1, LCD, DISPLAYA, DISPLAYB, RSVD, CRT, RSVD3, 0x1C, 25, 0x90, 28, 0xAC, 22),
181 PINGROUP(LPP, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 8, 0x98, 14, 0xAC, 18),
182 PINGROUP(LPW0, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 3, 0x90, 0, 0xAC, 20),
183 PINGROUP(LPW1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 4, 0x90, 2, 0xAC, 20),
184 PINGROUP(LPW2, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 5, 0x90, 4, 0xAC, 20),
185 PINGROUP(LSC0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 27, 0x90, 18, 0xAC, 22),
186 PINGROUP(LSC1, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 28, 0x90, 20, 0xAC, 20),
187 PINGROUP(LSCK, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 29, 0x90, 16, 0xAC, 20),
188 PINGROUP(LSDA, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 1, 0x90, 8, 0xAC, 20),
189 PINGROUP(LSDI, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, DISPLAYA, 0x20, 2, 0x90, 6, 0xAC, 20),
190 PINGROUP(LSPI, LCD, DISPLAYA, DISPLAYB, XIO, HDMI, DISPLAYA, 0x20, 0, 0x90, 10, 0xAC, 22),
191 PINGROUP(LVP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 21, 0x90, 30, 0xAC, 22),
192 PINGROUP(LVP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 22, 0x98, 8, 0xAC, 16),
193 PINGROUP(LVS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 26, 0x90, 24, 0xAC, 22),
194 PINGROUP(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR, 0x14, 31, 0x84, 8, 0xB0, 30),
195 PINGROUP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, 0x14, 23, 0x98, 18, -1, -1),
196 PINGROUP(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4, 0x14, 24, 0x98, 22, 0xA4, 4),
197 PINGROUP(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 25, 0x80, 14, 0xA4, 0),
198 PINGROUP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, 0x20, 15, 0x8C, 10, -1, -1),
199 PINGROUP(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC, 0x18, 1, 0x8C, 12, 0xAC, 28),
200 PINGROUP(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM, 0x18, 2, 0x8C, 14, 0xAC, 30),
201 PINGROUP(SDIO1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2, 0x14, 30, 0x80, 30, 0xB0, 18),
202 PINGROUP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 3, 0x84, 6, 0xA4, 22),
203 PINGROUP(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 5, 0x84, 10, 0xA4, 26),
204 PINGROUP(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 6, 0x84, 12, 0xA4, 28),
205 PINGROUP(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 7, 0x84, 14, 0xA4, 30),
206 PINGROUP(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 8, 0x8C, 8, 0xA4, 16),
207 PINGROUP(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 9, 0x8C, 6, 0xA4, 18),
208 PINGROUP(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 10, 0x8C, 30, 0xA8, 4),
209 PINGROUP(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 11, 0x8C, 28, 0xA8, 6),
210 PINGROUP(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 12, 0x8C, 26, 0xA8, 8),
211 PINGROUP(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 13, 0x8C, 24, 0xA8, 10),
212 PINGROUP(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 14, 0x8C, 22, 0xA8, 12),
213 PINGROUP(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4, 0x18, 15, 0x8C, 20, 0xA8, 14),
214 PINGROUP(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 16, 0x8C, 18, 0xA8, 16),
215 PINGROUP(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 17, 0x8C, 16, 0xA8, 18),
216 PINGROUP(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 18, 0x80, 0, 0xAC, 0),
217 PINGROUP(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 19, 0x80, 2, 0xAC, 2),
218 PINGROUP(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4, 0x18, 20, 0x80, 4, 0xAC, 4),
219 PINGROUP(UAD, UART, IRDA, SPDIF, UARTA, SPI4, SPDIF, 0x18, 21, 0x80, 6, 0xAC, 6),
220 PINGROUP(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4, 0x18, 22, 0x84, 16, 0xAC, 8),
221 PINGROUP(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4, 0x18, 23, 0x84, 18, 0xAC, 10),
222 PINGROUP(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2, 0x20, 13, 0x80, 8, 0xB0, 16),
223 /* these pin groups only have pullup and pull down control */
224 PINGROUP(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 14),
225 PINGROUP(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xAC, 26),
226 PINGROUP(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 4),
227 PINGROUP(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 6),
228 PINGROUP(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 8),
229 PINGROUP(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 10),
230 PINGROUP(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 12),
231 PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30),
232 PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28),
233};
234
235void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg,
236 int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
237 int *pgdrive_max)
238{
239 *pg = tegra_soc_pingroups;
240 *pg_max = TEGRA_MAX_PINGROUP;
241 *pgdrive = tegra_soc_drive_pingroups;
242 *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
243}
244
diff --git a/arch/arm/mach-tegra/pinmux-tegra30-tables.c b/arch/arm/mach-tegra/pinmux-tegra30-tables.c
deleted file mode 100644
index 14fc0e4c1c44..000000000000
--- a/arch/arm/mach-tegra/pinmux-tegra30-tables.c
+++ /dev/null
@@ -1,376 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c
3 *
4 * Common pinmux configurations for Tegra30 SoCs
5 *
6 * Copyright (C) 2010,2011 NVIDIA Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
22#include <linux/kernel.h>
23#include <linux/errno.h>
24#include <linux/spinlock.h>
25#include <linux/io.h>
26#include <linux/init.h>
27#include <linux/string.h>
28
29#include <mach/iomap.h>
30#include <mach/pinmux.h>
31#include <mach/pinmux-tegra30.h>
32#include <mach/suspend.h>
33
34#define PINGROUP_REG_A 0x868
35#define MUXCTL_REG_A 0x3000
36
37#define DRIVE_PINGROUP(pg_name, r) \
38 [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
39 .name = #pg_name, \
40 .reg_bank = 0, \
41 .reg = ((r) - PINGROUP_REG_A) \
42 }
43
44static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
45 DRIVE_PINGROUP(AO1, 0x868),
46 DRIVE_PINGROUP(AO2, 0x86c),
47 DRIVE_PINGROUP(AT1, 0x870),
48 DRIVE_PINGROUP(AT2, 0x874),
49 DRIVE_PINGROUP(AT3, 0x878),
50 DRIVE_PINGROUP(AT4, 0x87c),
51 DRIVE_PINGROUP(AT5, 0x880),
52 DRIVE_PINGROUP(CDEV1, 0x884),
53 DRIVE_PINGROUP(CDEV2, 0x888),
54 DRIVE_PINGROUP(CSUS, 0x88c),
55 DRIVE_PINGROUP(DAP1, 0x890),
56 DRIVE_PINGROUP(DAP2, 0x894),
57 DRIVE_PINGROUP(DAP3, 0x898),
58 DRIVE_PINGROUP(DAP4, 0x89c),
59 DRIVE_PINGROUP(DBG, 0x8a0),
60 DRIVE_PINGROUP(LCD1, 0x8a4),
61 DRIVE_PINGROUP(LCD2, 0x8a8),
62 DRIVE_PINGROUP(SDIO2, 0x8ac),
63 DRIVE_PINGROUP(SDIO3, 0x8b0),
64 DRIVE_PINGROUP(SPI, 0x8b4),
65 DRIVE_PINGROUP(UAA, 0x8b8),
66 DRIVE_PINGROUP(UAB, 0x8bc),
67 DRIVE_PINGROUP(UART2, 0x8c0),
68 DRIVE_PINGROUP(UART3, 0x8c4),
69 DRIVE_PINGROUP(VI1, 0x8c8),
70 DRIVE_PINGROUP(SDIO1, 0x8ec),
71 DRIVE_PINGROUP(CRT, 0x8f8),
72 DRIVE_PINGROUP(DDC, 0x8fc),
73 DRIVE_PINGROUP(GMA, 0x900),
74 DRIVE_PINGROUP(GMB, 0x904),
75 DRIVE_PINGROUP(GMC, 0x908),
76 DRIVE_PINGROUP(GMD, 0x90c),
77 DRIVE_PINGROUP(GME, 0x910),
78 DRIVE_PINGROUP(GMF, 0x914),
79 DRIVE_PINGROUP(GMG, 0x918),
80 DRIVE_PINGROUP(GMH, 0x91c),
81 DRIVE_PINGROUP(OWR, 0x920),
82 DRIVE_PINGROUP(UAD, 0x924),
83 DRIVE_PINGROUP(GPV, 0x928),
84 DRIVE_PINGROUP(DEV3, 0x92c),
85 DRIVE_PINGROUP(CEC, 0x938),
86};
87
88#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg) \
89 [TEGRA_PINGROUP_ ## pg_name] = { \
90 .name = #pg_name, \
91 .vddio = TEGRA_VDDIO_ ## vdd, \
92 .funcs = { \
93 TEGRA_MUX_ ## f0, \
94 TEGRA_MUX_ ## f1, \
95 TEGRA_MUX_ ## f2, \
96 TEGRA_MUX_ ## f3, \
97 }, \
98 .func_safe = TEGRA_MUX_ ## fs, \
99 .tri_bank = 1, \
100 .tri_reg = ((reg) - MUXCTL_REG_A), \
101 .tri_bit = 4, \
102 .mux_bank = 1, \
103 .mux_reg = ((reg) - MUXCTL_REG_A), \
104 .mux_bit = 0, \
105 .pupd_bank = 1, \
106 .pupd_reg = ((reg) - MUXCTL_REG_A), \
107 .pupd_bit = 2, \
108 .io_default = TEGRA_PIN_ ## iod, \
109 .od_bit = 6, \
110 .lock_bit = 7, \
111 .ioreset_bit = 8, \
112 }
113
114static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
115 /* NAME VDD f0 f1 f2 f3 fSafe io reg */
116 PINGROUP(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3000),
117 PINGROUP(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3004),
118 PINGROUP(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3008),
119 PINGROUP(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x300c),
120 PINGROUP(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3010),
121 PINGROUP(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3014),
122 PINGROUP(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3018),
123 PINGROUP(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x301c),
124 PINGROUP(ULPI_CLK, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3020),
125 PINGROUP(ULPI_DIR, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3024),
126 PINGROUP(ULPI_NXT, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3028),
127 PINGROUP(ULPI_STP, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x302c),
128 PINGROUP(DAP3_FS, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3030),
129 PINGROUP(DAP3_DIN, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3034),
130 PINGROUP(DAP3_DOUT, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3038),
131 PINGROUP(DAP3_SCLK, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x303c),
132 PINGROUP(GPIO_PV0, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3040),
133 PINGROUP(GPIO_PV1, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3044),
134 PINGROUP(SDMMC1_CLK, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x3048),
135 PINGROUP(SDMMC1_CMD, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x304c),
136 PINGROUP(SDMMC1_DAT3, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3050),
137 PINGROUP(SDMMC1_DAT2, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3054),
138 PINGROUP(SDMMC1_DAT1, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3058),
139 PINGROUP(SDMMC1_DAT0, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x305c),
140 PINGROUP(GPIO_PV2, SDMMC1, OWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3060),
141 PINGROUP(GPIO_PV3, SDMMC1, INVALID, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3064),
142 PINGROUP(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3068),
143 PINGROUP(CLK2_REQ, SDMMC1, DAP, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x306c),
144 PINGROUP(LCD_PWR1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3070),
145 PINGROUP(LCD_PWR2, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3074),
146 PINGROUP(LCD_SDIN, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3078),
147 PINGROUP(LCD_SDOUT, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x307c),
148 PINGROUP(LCD_WR_N, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3080),
149 PINGROUP(LCD_CS0_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3084),
150 PINGROUP(LCD_DC0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3088),
151 PINGROUP(LCD_SCK, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x308c),
152 PINGROUP(LCD_PWR0, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3090),
153 PINGROUP(LCD_PCLK, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3094),
154 PINGROUP(LCD_DE, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3098),
155 PINGROUP(LCD_HSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x309c),
156 PINGROUP(LCD_VSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a0),
157 PINGROUP(LCD_D0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a4),
158 PINGROUP(LCD_D1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a8),
159 PINGROUP(LCD_D2, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ac),
160 PINGROUP(LCD_D3, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b0),
161 PINGROUP(LCD_D4, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b4),
162 PINGROUP(LCD_D5, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b8),
163 PINGROUP(LCD_D6, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30bc),
164 PINGROUP(LCD_D7, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c0),
165 PINGROUP(LCD_D8, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c4),
166 PINGROUP(LCD_D9, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c8),
167 PINGROUP(LCD_D10, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30cc),
168 PINGROUP(LCD_D11, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d0),
169 PINGROUP(LCD_D12, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d4),
170 PINGROUP(LCD_D13, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d8),
171 PINGROUP(LCD_D14, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30dc),
172 PINGROUP(LCD_D15, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e0),
173 PINGROUP(LCD_D16, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e4),
174 PINGROUP(LCD_D17, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e8),
175 PINGROUP(LCD_D18, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ec),
176 PINGROUP(LCD_D19, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f0),
177 PINGROUP(LCD_D20, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f4),
178 PINGROUP(LCD_D21, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f8),
179 PINGROUP(LCD_D22, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30fc),
180 PINGROUP(LCD_D23, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3100),
181 PINGROUP(LCD_CS1_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD2, RSVD, OUTPUT, 0x3104),
182 PINGROUP(LCD_M1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3108),
183 PINGROUP(LCD_DC1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x310c),
184 PINGROUP(HDMI_INT, LCD, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3110),
185 PINGROUP(DDC_SCL, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3114),
186 PINGROUP(DDC_SDA, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3118),
187 PINGROUP(CRT_HSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x311c),
188 PINGROUP(CRT_VSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3120),
189 PINGROUP(VI_D0, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3124),
190 PINGROUP(VI_D1, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3128),
191 PINGROUP(VI_D2, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x312c),
192 PINGROUP(VI_D3, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3130),
193 PINGROUP(VI_D4, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3134),
194 PINGROUP(VI_D5, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3138),
195 PINGROUP(VI_D6, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x313c),
196 PINGROUP(VI_D7, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3140),
197 PINGROUP(VI_D8, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3144),
198 PINGROUP(VI_D9, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3148),
199 PINGROUP(VI_D10, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x314c),
200 PINGROUP(VI_D11, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3150),
201 PINGROUP(VI_PCLK, VI, RSVD1, SDIO2, VI, RSVD2, RSVD, INPUT, 0x3154),
202 PINGROUP(VI_MCLK, VI, VI, INVALID, INVALID, INVALID, RSVD, INPUT, 0x3158),
203 PINGROUP(VI_VSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x315c),
204 PINGROUP(VI_HSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3160),
205 PINGROUP(UART2_RXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3164),
206 PINGROUP(UART2_TXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3168),
207 PINGROUP(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x316c),
208 PINGROUP(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x3170),
209 PINGROUP(UART3_TXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3174),
210 PINGROUP(UART3_RXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3178),
211 PINGROUP(UART3_CTS_N, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x317c),
212 PINGROUP(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD2, RSVD, INPUT, 0x3180),
213 PINGROUP(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3184),
214 PINGROUP(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x3188),
215 PINGROUP(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x318c),
216 PINGROUP(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3190),
217 PINGROUP(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3194),
218 PINGROUP(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3198),
219 PINGROUP(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD1, RSVD, INPUT, 0x319c),
220 PINGROUP(GEN1_I2C_SDA, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a0),
221 PINGROUP(GEN1_I2C_SCL, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a4),
222 PINGROUP(DAP4_FS, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31a8),
223 PINGROUP(DAP4_DIN, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31ac),
224 PINGROUP(DAP4_DOUT, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b0),
225 PINGROUP(DAP4_SCLK, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b4),
226 PINGROUP(CLK3_OUT, UART, EXTPERIPH3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31b8),
227 PINGROUP(CLK3_REQ, UART, DEV3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31bc),
228 PINGROUP(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31c0),
229 PINGROUP(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c4),
230 PINGROUP(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c8),
231 PINGROUP(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31cc),
232 PINGROUP(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31d0),
233 PINGROUP(GMI_CS0_N, GMI, RSVD1, NAND, GMI, INVALID, RSVD, INPUT, 0x31d4),
234 PINGROUP(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV, RSVD, INPUT, 0x31d8),
235 PINGROUP(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31dc),
236 PINGROUP(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31e0),
237 PINGROUP(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31e4),
238 PINGROUP(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA, RSVD, INPUT, 0x31e8),
239 PINGROUP(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT, RSVD, INPUT, 0x31ec),
240 PINGROUP(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f0),
241 PINGROUP(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f4),
242 PINGROUP(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f8),
243 PINGROUP(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31fc),
244 PINGROUP(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3200),
245 PINGROUP(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3204),
246 PINGROUP(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3208),
247 PINGROUP(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x320c),
248 PINGROUP(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD2, RSVD, INPUT, 0x3210),
249 PINGROUP(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3214),
250 PINGROUP(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD2, RSVD, INPUT, 0x3218),
251 PINGROUP(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD2, RSVD, INPUT, 0x321c),
252 PINGROUP(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3220),
253 PINGROUP(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3224),
254 PINGROUP(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3228),
255 PINGROUP(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x322c),
256 PINGROUP(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT, RSVD, INPUT, 0x3230),
257 PINGROUP(GMI_A17, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3234),
258 PINGROUP(GMI_A18, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3238),
259 PINGROUP(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD3, RSVD, INPUT, 0x323c),
260 PINGROUP(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3240),
261 PINGROUP(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3244),
262 PINGROUP(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3248),
263 PINGROUP(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD3, RSVD, INPUT, 0x324c),
264 PINGROUP(GEN2_I2C_SCL, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3250),
265 PINGROUP(GEN2_I2C_SDA, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3254),
266 PINGROUP(SDMMC4_CLK, SDMMC4, INVALID, NAND, GMI, SDIO4, RSVD, INPUT, 0x3258),
267 PINGROUP(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDIO4, RSVD, INPUT, 0x325c),
268 PINGROUP(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3260),
269 PINGROUP(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3264),
270 PINGROUP(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3268),
271 PINGROUP(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x326c),
272 PINGROUP(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3270),
273 PINGROUP(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3274),
274 PINGROUP(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3278),
275 PINGROUP(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDIO4, RSVD, INPUT, 0x327c),
276 PINGROUP(SDMMC4_RST_N, SDMMC4, VGP6, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3280),
277 PINGROUP(CAM_MCLK, CAM, VI, INVALID, VI_ALT2, POPSDMMC4, RSVD, INPUT, 0x3284),
278 PINGROUP(GPIO_PCC1, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3288),
279 PINGROUP(GPIO_PBB0, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x328c),
280 PINGROUP(CAM_I2C_SCL, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3290),
281 PINGROUP(CAM_I2C_SDA, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3294),
282 PINGROUP(GPIO_PBB3, CAM, VGP3, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x3298),
283 PINGROUP(GPIO_PBB4, CAM, VGP4, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x329c),
284 PINGROUP(GPIO_PBB5, CAM, VGP5, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a0),
285 PINGROUP(GPIO_PBB6, CAM, VGP6, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a4),
286 PINGROUP(GPIO_PBB7, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32a8),
287 PINGROUP(GPIO_PCC2, CAM, I2S4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32ac),
288 PINGROUP(JTAG_RTCK, SYS, RTCK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b0),
289 PINGROUP(PWR_I2C_SCL, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b4),
290 PINGROUP(PWR_I2C_SDA, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b8),
291 PINGROUP(KB_ROW0, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32bc),
292 PINGROUP(KB_ROW1, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c0),
293 PINGROUP(KB_ROW2, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c4),
294 PINGROUP(KB_ROW3, SYS, KBC, INVALID, RSVD2, INVALID, RSVD, INPUT, 0x32c8),
295 PINGROUP(KB_ROW4, SYS, KBC, INVALID, TRACE, RSVD3, RSVD, INPUT, 0x32cc),
296 PINGROUP(KB_ROW5, SYS, KBC, INVALID, TRACE, OWR, RSVD, INPUT, 0x32d0),
297 PINGROUP(KB_ROW6, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d4),
298 PINGROUP(KB_ROW7, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d8),
299 PINGROUP(KB_ROW8, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32dc),
300 PINGROUP(KB_ROW9, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e0),
301 PINGROUP(KB_ROW10, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e4),
302 PINGROUP(KB_ROW11, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e8),
303 PINGROUP(KB_ROW12, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32ec),
304 PINGROUP(KB_ROW13, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f0),
305 PINGROUP(KB_ROW14, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f4),
306 PINGROUP(KB_ROW15, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f8),
307 PINGROUP(KB_COL0, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x32fc),
308 PINGROUP(KB_COL1, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3300),
309 PINGROUP(KB_COL2, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3304),
310 PINGROUP(KB_COL3, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3308),
311 PINGROUP(KB_COL4, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x330c),
312 PINGROUP(KB_COL5, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3310),
313 PINGROUP(KB_COL6, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3314),
314 PINGROUP(KB_COL7, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3318),
315 PINGROUP(CLK_32K_OUT, SYS, BLINK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x331c),
316 PINGROUP(SYS_CLK_REQ, SYS, SYSCLK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3320),
317 PINGROUP(CORE_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3324),
318 PINGROUP(CPU_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3328),
319 PINGROUP(PWR_INT_N, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x332c),
320 PINGROUP(CLK_32K_IN, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3330),
321 PINGROUP(OWR, SYS, OWR, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3334),
322 PINGROUP(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3338),
323 PINGROUP(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x333c),
324 PINGROUP(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3340),
325 PINGROUP(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3344),
326 PINGROUP(CLK1_REQ, AUDIO, DAP, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x3348),
327 PINGROUP(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x334c),
328 PINGROUP(SPDIF_IN, AUDIO, SPDIF, HDA, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3350),
329 PINGROUP(SPDIF_OUT, AUDIO, SPDIF, RSVD1, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3354),
330 PINGROUP(DAP2_FS, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3358),
331 PINGROUP(DAP2_DIN, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x335c),
332 PINGROUP(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3360),
333 PINGROUP(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3364),
334 PINGROUP(SPI2_MOSI, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3368),
335 PINGROUP(SPI2_MISO, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x336c),
336 PINGROUP(SPI2_CS0_N, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3370),
337 PINGROUP(SPI2_SCK, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3374),
338 PINGROUP(SPI1_MOSI, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3378),
339 PINGROUP(SPI1_SCK, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x337c),
340 PINGROUP(SPI1_CS0_N, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3380),
341 PINGROUP(SPI1_MISO, AUDIO, INVALID, SPI1, INVALID, RSVD3, RSVD, INPUT, 0x3384),
342 PINGROUP(SPI2_CS1_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x3388),
343 PINGROUP(SPI2_CS2_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x338c),
344 PINGROUP(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDIO3, INVALID, RSVD, INPUT, 0x3390),
345 PINGROUP(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDIO3, INVALID, RSVD, INPUT, 0x3394),
346 PINGROUP(SDMMC3_DAT0, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x3398),
347 PINGROUP(SDMMC3_DAT1, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x339c),
348 PINGROUP(SDMMC3_DAT2, SDMMC3, RSVD, PWM1, SDIO3, INVALID, RSVD, INPUT, 0x33a0),
349 PINGROUP(SDMMC3_DAT3, SDMMC3, RSVD, PWM0, SDIO3, INVALID, RSVD, INPUT, 0x33a4),
350 PINGROUP(SDMMC3_DAT4, SDMMC3, PWM1, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33a8),
351 PINGROUP(SDMMC3_DAT5, SDMMC3, PWM0, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33ac),
352 PINGROUP(SDMMC3_DAT6, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b0),
353 PINGROUP(SDMMC3_DAT7, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b4),
354 PINGROUP(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33b8),
355 PINGROUP(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33bc),
356 PINGROUP(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c0),
357 PINGROUP(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c4),
358 PINGROUP(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c8),
359 PINGROUP(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33cc),
360 PINGROUP(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d0),
361 PINGROUP(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d4),
362 PINGROUP(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d8),
363 PINGROUP(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33dc),
364 PINGROUP(HDMI_CEC, SYS, CEC, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x33e0),
365};
366
367void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg,
368 int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
369 int *pgdrive_max)
370{
371 *pg = tegra_soc_pingroups;
372 *pg_max = TEGRA_MAX_PINGROUP;
373 *pgdrive = tegra_soc_drive_pingroups;
374 *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
375}
376
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
deleted file mode 100644
index ac35d2b76850..000000000000
--- a/arch/arm/mach-tegra/pinmux.c
+++ /dev/null
@@ -1,987 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/pinmux.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/spinlock.h>
22#include <linux/io.h>
23#include <linux/platform_device.h>
24#include <linux/of_device.h>
25
26#include <mach/iomap.h>
27#include <mach/pinmux.h>
28
29#define HSM_EN(reg) (((reg) >> 2) & 0x1)
30#define SCHMT_EN(reg) (((reg) >> 3) & 0x1)
31#define LPMD(reg) (((reg) >> 4) & 0x3)
32#define DRVDN(reg) (((reg) >> 12) & 0x1f)
33#define DRVUP(reg) (((reg) >> 20) & 0x1f)
34#define SLWR(reg) (((reg) >> 28) & 0x3)
35#define SLWF(reg) (((reg) >> 30) & 0x3)
36
37static const struct tegra_pingroup_desc *pingroups;
38static const struct tegra_drive_pingroup_desc *drive_pingroups;
39static int pingroup_max;
40static int drive_max;
41
42static char *tegra_mux_names[TEGRA_MAX_MUX] = {
43 [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
44 [TEGRA_MUX_APB_CLK] = "APB_CLK",
45 [TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
46 [TEGRA_MUX_CRT] = "CRT",
47 [TEGRA_MUX_DAP1] = "DAP1",
48 [TEGRA_MUX_DAP2] = "DAP2",
49 [TEGRA_MUX_DAP3] = "DAP3",
50 [TEGRA_MUX_DAP4] = "DAP4",
51 [TEGRA_MUX_DAP5] = "DAP5",
52 [TEGRA_MUX_DISPLAYA] = "DISPLAYA",
53 [TEGRA_MUX_DISPLAYB] = "DISPLAYB",
54 [TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
55 [TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
56 [TEGRA_MUX_GMI] = "GMI",
57 [TEGRA_MUX_GMI_INT] = "GMI_INT",
58 [TEGRA_MUX_HDMI] = "HDMI",
59 [TEGRA_MUX_I2C] = "I2C",
60 [TEGRA_MUX_I2C2] = "I2C2",
61 [TEGRA_MUX_I2C3] = "I2C3",
62 [TEGRA_MUX_IDE] = "IDE",
63 [TEGRA_MUX_IRDA] = "IRDA",
64 [TEGRA_MUX_KBC] = "KBC",
65 [TEGRA_MUX_MIO] = "MIO",
66 [TEGRA_MUX_MIPI_HS] = "MIPI_HS",
67 [TEGRA_MUX_NAND] = "NAND",
68 [TEGRA_MUX_OSC] = "OSC",
69 [TEGRA_MUX_OWR] = "OWR",
70 [TEGRA_MUX_PCIE] = "PCIE",
71 [TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
72 [TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
73 [TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
74 [TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
75 [TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
76 [TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
77 [TEGRA_MUX_PWM] = "PWM",
78 [TEGRA_MUX_PWR_INTR] = "PWR_INTR",
79 [TEGRA_MUX_PWR_ON] = "PWR_ON",
80 [TEGRA_MUX_RTCK] = "RTCK",
81 [TEGRA_MUX_SDIO1] = "SDIO1",
82 [TEGRA_MUX_SDIO2] = "SDIO2",
83 [TEGRA_MUX_SDIO3] = "SDIO3",
84 [TEGRA_MUX_SDIO4] = "SDIO4",
85 [TEGRA_MUX_SFLASH] = "SFLASH",
86 [TEGRA_MUX_SPDIF] = "SPDIF",
87 [TEGRA_MUX_SPI1] = "SPI1",
88 [TEGRA_MUX_SPI2] = "SPI2",
89 [TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
90 [TEGRA_MUX_SPI3] = "SPI3",
91 [TEGRA_MUX_SPI4] = "SPI4",
92 [TEGRA_MUX_TRACE] = "TRACE",
93 [TEGRA_MUX_TWC] = "TWC",
94 [TEGRA_MUX_UARTA] = "UARTA",
95 [TEGRA_MUX_UARTB] = "UARTB",
96 [TEGRA_MUX_UARTC] = "UARTC",
97 [TEGRA_MUX_UARTD] = "UARTD",
98 [TEGRA_MUX_UARTE] = "UARTE",
99 [TEGRA_MUX_ULPI] = "ULPI",
100 [TEGRA_MUX_VI] = "VI",
101 [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
102 [TEGRA_MUX_XIO] = "XIO",
103 [TEGRA_MUX_BLINK] = "BLINK",
104 [TEGRA_MUX_CEC] = "CEC",
105 [TEGRA_MUX_CLK12] = "CLK12",
106 [TEGRA_MUX_DAP] = "DAP",
107 [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
108 [TEGRA_MUX_DDR] = "DDR",
109 [TEGRA_MUX_DEV3] = "DEV3",
110 [TEGRA_MUX_DTV] = "DTV",
111 [TEGRA_MUX_VI_ALT1] = "VI_ALT1",
112 [TEGRA_MUX_VI_ALT2] = "VI_ALT2",
113 [TEGRA_MUX_VI_ALT3] = "VI_ALT3",
114 [TEGRA_MUX_EMC_DLL] = "EMC_DLL",
115 [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
116 [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
117 [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
118 [TEGRA_MUX_GMI_ALT] = "GMI_ALT",
119 [TEGRA_MUX_HDA] = "HDA",
120 [TEGRA_MUX_HSI] = "HSI",
121 [TEGRA_MUX_I2C4] = "I2C4",
122 [TEGRA_MUX_I2C5] = "I2C5",
123 [TEGRA_MUX_I2CPWR] = "I2CPWR",
124 [TEGRA_MUX_I2S0] = "I2S0",
125 [TEGRA_MUX_I2S1] = "I2S1",
126 [TEGRA_MUX_I2S2] = "I2S2",
127 [TEGRA_MUX_I2S3] = "I2S3",
128 [TEGRA_MUX_I2S4] = "I2S4",
129 [TEGRA_MUX_NAND_ALT] = "NAND_ALT",
130 [TEGRA_MUX_POPSDIO4] = "POPSDIO4",
131 [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
132 [TEGRA_MUX_PWM0] = "PWM0",
133 [TEGRA_MUX_PWM1] = "PWM2",
134 [TEGRA_MUX_PWM2] = "PWM2",
135 [TEGRA_MUX_PWM3] = "PWM3",
136 [TEGRA_MUX_SATA] = "SATA",
137 [TEGRA_MUX_SPI5] = "SPI5",
138 [TEGRA_MUX_SPI6] = "SPI6",
139 [TEGRA_MUX_SYSCLK] = "SYSCLK",
140 [TEGRA_MUX_VGP1] = "VGP1",
141 [TEGRA_MUX_VGP2] = "VGP2",
142 [TEGRA_MUX_VGP3] = "VGP3",
143 [TEGRA_MUX_VGP4] = "VGP4",
144 [TEGRA_MUX_VGP5] = "VGP5",
145 [TEGRA_MUX_VGP6] = "VGP6",
146 [TEGRA_MUX_SAFE] = "<safe>",
147};
148
149static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
150 [TEGRA_DRIVE_DIV_8] = "DIV_8",
151 [TEGRA_DRIVE_DIV_4] = "DIV_4",
152 [TEGRA_DRIVE_DIV_2] = "DIV_2",
153 [TEGRA_DRIVE_DIV_1] = "DIV_1",
154};
155
156static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
157 [TEGRA_SLEW_FASTEST] = "FASTEST",
158 [TEGRA_SLEW_FAST] = "FAST",
159 [TEGRA_SLEW_SLOW] = "SLOW",
160 [TEGRA_SLEW_SLOWEST] = "SLOWEST",
161};
162
163static DEFINE_SPINLOCK(mux_lock);
164
165static const char *pingroup_name(int pg)
166{
167 if (pg < 0 || pg >= pingroup_max)
168 return "<UNKNOWN>";
169
170 return pingroups[pg].name;
171}
172
173static const char *func_name(enum tegra_mux_func func)
174{
175 if (func == TEGRA_MUX_RSVD1)
176 return "RSVD1";
177
178 if (func == TEGRA_MUX_RSVD2)
179 return "RSVD2";
180
181 if (func == TEGRA_MUX_RSVD3)
182 return "RSVD3";
183
184 if (func == TEGRA_MUX_RSVD4)
185 return "RSVD4";
186
187 if (func == TEGRA_MUX_NONE)
188 return "NONE";
189
190 if (func < 0 || func >= TEGRA_MAX_MUX)
191 return "<UNKNOWN>";
192
193 return tegra_mux_names[func];
194}
195
196
197static const char *tri_name(unsigned long val)
198{
199 return val ? "TRISTATE" : "NORMAL";
200}
201
202static const char *pupd_name(unsigned long val)
203{
204 switch (val) {
205 case 0:
206 return "NORMAL";
207
208 case 1:
209 return "PULL_DOWN";
210
211 case 2:
212 return "PULL_UP";
213
214 default:
215 return "RSVD";
216 }
217}
218
219static int nbanks;
220static void __iomem **regs;
221
222static inline u32 pg_readl(u32 bank, u32 reg)
223{
224 return readl(regs[bank] + reg);
225}
226
227static inline void pg_writel(u32 val, u32 bank, u32 reg)
228{
229 writel(val, regs[bank] + reg);
230}
231
232static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
233{
234 int mux = -1;
235 int i;
236 unsigned long reg;
237 unsigned long flags;
238 int pg = config->pingroup;
239 enum tegra_mux_func func = config->func;
240
241 if (pg < 0 || pg >= pingroup_max)
242 return -ERANGE;
243
244 if (pingroups[pg].mux_reg < 0)
245 return -EINVAL;
246
247 if (func < 0)
248 return -ERANGE;
249
250 if (func == TEGRA_MUX_SAFE)
251 func = pingroups[pg].func_safe;
252
253 if (func & TEGRA_MUX_RSVD) {
254 mux = func & 0x3;
255 } else {
256 for (i = 0; i < 4; i++) {
257 if (pingroups[pg].funcs[i] == func) {
258 mux = i;
259 break;
260 }
261 }
262 }
263
264 if (mux < 0)
265 return -EINVAL;
266
267 spin_lock_irqsave(&mux_lock, flags);
268
269 reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
270 reg &= ~(0x3 << pingroups[pg].mux_bit);
271 reg |= mux << pingroups[pg].mux_bit;
272 pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
273
274 spin_unlock_irqrestore(&mux_lock, flags);
275
276 return 0;
277}
278
279int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
280{
281 unsigned long reg;
282 unsigned long flags;
283
284 if (pg < 0 || pg >= pingroup_max)
285 return -ERANGE;
286
287 if (pingroups[pg].tri_reg < 0)
288 return -EINVAL;
289
290 spin_lock_irqsave(&mux_lock, flags);
291
292 reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
293 reg &= ~(0x1 << pingroups[pg].tri_bit);
294 if (tristate)
295 reg |= 1 << pingroups[pg].tri_bit;
296 pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
297
298 spin_unlock_irqrestore(&mux_lock, flags);
299
300 return 0;
301}
302
303int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
304{
305 unsigned long reg;
306 unsigned long flags;
307
308 if (pg < 0 || pg >= pingroup_max)
309 return -ERANGE;
310
311 if (pingroups[pg].pupd_reg < 0)
312 return -EINVAL;
313
314 if (pupd != TEGRA_PUPD_NORMAL &&
315 pupd != TEGRA_PUPD_PULL_DOWN &&
316 pupd != TEGRA_PUPD_PULL_UP)
317 return -EINVAL;
318
319
320 spin_lock_irqsave(&mux_lock, flags);
321
322 reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
323 reg &= ~(0x3 << pingroups[pg].pupd_bit);
324 reg |= pupd << pingroups[pg].pupd_bit;
325 pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
326
327 spin_unlock_irqrestore(&mux_lock, flags);
328
329 return 0;
330}
331
332static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
333{
334 int pingroup = config->pingroup;
335 enum tegra_mux_func func = config->func;
336 enum tegra_pullupdown pupd = config->pupd;
337 enum tegra_tristate tristate = config->tristate;
338 int err;
339
340 if (pingroups[pingroup].mux_reg >= 0) {
341 err = tegra_pinmux_set_func(config);
342 if (err < 0)
343 pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
344 pingroup_name(pingroup), func_name(func), err);
345 }
346
347 if (pingroups[pingroup].pupd_reg >= 0) {
348 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
349 if (err < 0)
350 pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
351 pingroup_name(pingroup), pupd_name(pupd), err);
352 }
353
354 if (pingroups[pingroup].tri_reg >= 0) {
355 err = tegra_pinmux_set_tristate(pingroup, tristate);
356 if (err < 0)
357 pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
358 pingroup_name(pingroup), tri_name(func), err);
359 }
360}
361
362void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
363{
364 int i;
365
366 for (i = 0; i < len; i++)
367 tegra_pinmux_config_pingroup(&config[i]);
368}
369
370static const char *drive_pinmux_name(int pg)
371{
372 if (pg < 0 || pg >= drive_max)
373 return "<UNKNOWN>";
374
375 return drive_pingroups[pg].name;
376}
377
378static const char *enable_name(unsigned long val)
379{
380 return val ? "ENABLE" : "DISABLE";
381}
382
383static const char *drive_name(unsigned long val)
384{
385 if (val >= TEGRA_MAX_DRIVE)
386 return "<UNKNOWN>";
387
388 return tegra_drive_names[val];
389}
390
391static const char *slew_name(unsigned long val)
392{
393 if (val >= TEGRA_MAX_SLEW)
394 return "<UNKNOWN>";
395
396 return tegra_slew_names[val];
397}
398
399static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
400{
401 unsigned long flags;
402 u32 reg;
403 if (pg < 0 || pg >= drive_max)
404 return -ERANGE;
405
406 if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
407 return -EINVAL;
408
409 spin_lock_irqsave(&mux_lock, flags);
410
411 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
412 if (hsm == TEGRA_HSM_ENABLE)
413 reg |= (1 << 2);
414 else
415 reg &= ~(1 << 2);
416 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
417
418 spin_unlock_irqrestore(&mux_lock, flags);
419
420 return 0;
421}
422
423static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
424{
425 unsigned long flags;
426 u32 reg;
427 if (pg < 0 || pg >= drive_max)
428 return -ERANGE;
429
430 if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
431 return -EINVAL;
432
433 spin_lock_irqsave(&mux_lock, flags);
434
435 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
436 if (schmitt == TEGRA_SCHMITT_ENABLE)
437 reg |= (1 << 3);
438 else
439 reg &= ~(1 << 3);
440 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
441
442 spin_unlock_irqrestore(&mux_lock, flags);
443
444 return 0;
445}
446
447static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
448{
449 unsigned long flags;
450 u32 reg;
451 if (pg < 0 || pg >= drive_max)
452 return -ERANGE;
453
454 if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
455 return -EINVAL;
456
457 spin_lock_irqsave(&mux_lock, flags);
458
459 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
460 reg &= ~(0x3 << 4);
461 reg |= drive << 4;
462 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
463
464 spin_unlock_irqrestore(&mux_lock, flags);
465
466 return 0;
467}
468
469static int tegra_drive_pinmux_set_pull_down(int pg,
470 enum tegra_pull_strength pull_down)
471{
472 unsigned long flags;
473 u32 reg;
474 if (pg < 0 || pg >= drive_max)
475 return -ERANGE;
476
477 if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
478 return -EINVAL;
479
480 spin_lock_irqsave(&mux_lock, flags);
481
482 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
483 reg &= ~(0x1f << 12);
484 reg |= pull_down << 12;
485 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
486
487 spin_unlock_irqrestore(&mux_lock, flags);
488
489 return 0;
490}
491
492static int tegra_drive_pinmux_set_pull_up(int pg,
493 enum tegra_pull_strength pull_up)
494{
495 unsigned long flags;
496 u32 reg;
497 if (pg < 0 || pg >= drive_max)
498 return -ERANGE;
499
500 if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
501 return -EINVAL;
502
503 spin_lock_irqsave(&mux_lock, flags);
504
505 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
506 reg &= ~(0x1f << 12);
507 reg |= pull_up << 12;
508 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
509
510 spin_unlock_irqrestore(&mux_lock, flags);
511
512 return 0;
513}
514
515static int tegra_drive_pinmux_set_slew_rising(int pg,
516 enum tegra_slew slew_rising)
517{
518 unsigned long flags;
519 u32 reg;
520 if (pg < 0 || pg >= drive_max)
521 return -ERANGE;
522
523 if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
524 return -EINVAL;
525
526 spin_lock_irqsave(&mux_lock, flags);
527
528 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
529 reg &= ~(0x3 << 28);
530 reg |= slew_rising << 28;
531 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
532
533 spin_unlock_irqrestore(&mux_lock, flags);
534
535 return 0;
536}
537
538static int tegra_drive_pinmux_set_slew_falling(int pg,
539 enum tegra_slew slew_falling)
540{
541 unsigned long flags;
542 u32 reg;
543 if (pg < 0 || pg >= drive_max)
544 return -ERANGE;
545
546 if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
547 return -EINVAL;
548
549 spin_lock_irqsave(&mux_lock, flags);
550
551 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
552 reg &= ~(0x3 << 30);
553 reg |= slew_falling << 30;
554 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
555
556 spin_unlock_irqrestore(&mux_lock, flags);
557
558 return 0;
559}
560
561static void tegra_drive_pinmux_config_pingroup(int pingroup,
562 enum tegra_hsm hsm,
563 enum tegra_schmitt schmitt,
564 enum tegra_drive drive,
565 enum tegra_pull_strength pull_down,
566 enum tegra_pull_strength pull_up,
567 enum tegra_slew slew_rising,
568 enum tegra_slew slew_falling)
569{
570 int err;
571
572 err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
573 if (err < 0)
574 pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
575 drive_pinmux_name(pingroup),
576 enable_name(hsm), err);
577
578 err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
579 if (err < 0)
580 pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
581 drive_pinmux_name(pingroup),
582 enable_name(schmitt), err);
583
584 err = tegra_drive_pinmux_set_drive(pingroup, drive);
585 if (err < 0)
586 pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
587 drive_pinmux_name(pingroup),
588 drive_name(drive), err);
589
590 err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
591 if (err < 0)
592 pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
593 drive_pinmux_name(pingroup),
594 pull_down, err);
595
596 err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
597 if (err < 0)
598 pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
599 drive_pinmux_name(pingroup),
600 pull_up, err);
601
602 err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
603 if (err < 0)
604 pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
605 drive_pinmux_name(pingroup),
606 slew_name(slew_rising), err);
607
608 err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
609 if (err < 0)
610 pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
611 drive_pinmux_name(pingroup),
612 slew_name(slew_falling), err);
613}
614
615void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
616 int len)
617{
618 int i;
619
620 for (i = 0; i < len; i++)
621 tegra_drive_pinmux_config_pingroup(config[i].pingroup,
622 config[i].hsm,
623 config[i].schmitt,
624 config[i].drive,
625 config[i].pull_down,
626 config[i].pull_up,
627 config[i].slew_rising,
628 config[i].slew_falling);
629}
630
631void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
632 int len)
633{
634 int i;
635 struct tegra_pingroup_config c;
636
637 for (i = 0; i < len; i++) {
638 int err;
639 c = config[i];
640 if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
641 WARN_ON(1);
642 continue;
643 }
644 c.func = pingroups[c.pingroup].func_safe;
645 err = tegra_pinmux_set_func(&c);
646 if (err < 0)
647 pr_err("%s: tegra_pinmux_set_func returned %d setting "
648 "%s to %s\n", __func__, err,
649 pingroup_name(c.pingroup), func_name(c.func));
650 }
651}
652
653void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
654 int len)
655{
656 int i;
657
658 for (i = 0; i < len; i++) {
659 int err;
660 if (config[i].pingroup < 0 ||
661 config[i].pingroup >= pingroup_max) {
662 WARN_ON(1);
663 continue;
664 }
665 err = tegra_pinmux_set_func(&config[i]);
666 if (err < 0)
667 pr_err("%s: tegra_pinmux_set_func returned %d setting "
668 "%s to %s\n", __func__, err,
669 pingroup_name(config[i].pingroup),
670 func_name(config[i].func));
671 }
672}
673
674void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
675 int len, enum tegra_tristate tristate)
676{
677 int i;
678 int err;
679 int pingroup;
680
681 for (i = 0; i < len; i++) {
682 pingroup = config[i].pingroup;
683 if (pingroups[pingroup].tri_reg >= 0) {
684 err = tegra_pinmux_set_tristate(pingroup, tristate);
685 if (err < 0)
686 pr_err("pinmux: can't set pingroup %s tristate"
687 " to %s: %d\n", pingroup_name(pingroup),
688 tri_name(tristate), err);
689 }
690 }
691}
692
693void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
694 int len, enum tegra_pullupdown pupd)
695{
696 int i;
697 int err;
698 int pingroup;
699
700 for (i = 0; i < len; i++) {
701 pingroup = config[i].pingroup;
702 if (pingroups[pingroup].pupd_reg >= 0) {
703 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
704 if (err < 0)
705 pr_err("pinmux: can't set pingroup %s pullupdown"
706 " to %s: %d\n", pingroup_name(pingroup),
707 pupd_name(pupd), err);
708 }
709 }
710}
711
712static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
713#ifdef CONFIG_ARCH_TEGRA_2x_SOC
714 { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init },
715#endif
716#ifdef CONFIG_ARCH_TEGRA_3x_SOC
717 { .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init },
718#endif
719 { },
720};
721
722static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
723{
724 struct resource *res;
725 int i;
726 int config_bad = 0;
727 const struct of_device_id *match;
728
729 match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
730
731 if (match)
732 ((pinmux_init)(match->data))(&pingroups, &pingroup_max,
733 &drive_pingroups, &drive_max);
734#ifdef CONFIG_ARCH_TEGRA_2x_SOC
735 else
736 /* no device tree available, so we must be on tegra20 */
737 tegra20_pinmux_init(&pingroups, &pingroup_max,
738 &drive_pingroups, &drive_max);
739#else
740 pr_warn("non Tegra20 platform requires pinmux devicetree node\n");
741#endif
742
743 for (i = 0; ; i++) {
744 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
745 if (!res)
746 break;
747 }
748 nbanks = i;
749
750 for (i = 0; i < pingroup_max; i++) {
751 if (pingroups[i].tri_bank >= nbanks) {
752 dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
753 config_bad = 1;
754 }
755
756 if (pingroups[i].mux_bank >= nbanks) {
757 dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
758 config_bad = 1;
759 }
760
761 if (pingroups[i].pupd_bank >= nbanks) {
762 dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
763 config_bad = 1;
764 }
765 }
766
767 for (i = 0; i < drive_max; i++) {
768 if (drive_pingroups[i].reg_bank >= nbanks) {
769 dev_err(&pdev->dev,
770 "drive pingroup %d: bad reg_bank\n", i);
771 config_bad = 1;
772 }
773 }
774
775 if (config_bad)
776 return -ENODEV;
777
778 regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
779 if (!regs) {
780 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
781 return -ENODEV;
782 }
783
784 for (i = 0; i < nbanks; i++) {
785 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
786 if (!res) {
787 dev_err(&pdev->dev, "Missing MEM resource\n");
788 return -ENODEV;
789 }
790
791 if (!devm_request_mem_region(&pdev->dev, res->start,
792 resource_size(res),
793 dev_name(&pdev->dev))) {
794 dev_err(&pdev->dev,
795 "Couldn't request MEM resource %d\n", i);
796 return -ENODEV;
797 }
798
799 regs[i] = devm_ioremap(&pdev->dev, res->start,
800 resource_size(res));
801 if (!regs) {
802 dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
803 return -ENODEV;
804 }
805 }
806
807 return 0;
808}
809
810static struct platform_driver tegra_pinmux_driver = {
811 .driver = {
812 .name = "tegra-pinmux",
813 .owner = THIS_MODULE,
814 .of_match_table = tegra_pinmux_of_match,
815 },
816 .probe = tegra_pinmux_probe,
817};
818
819static int __init tegra_pinmux_init(void)
820{
821 return platform_driver_register(&tegra_pinmux_driver);
822}
823postcore_initcall(tegra_pinmux_init);
824
825#ifdef CONFIG_DEBUG_FS
826
827#include <linux/debugfs.h>
828#include <linux/seq_file.h>
829
830static void dbg_pad_field(struct seq_file *s, int len)
831{
832 seq_putc(s, ',');
833
834 while (len-- > -1)
835 seq_putc(s, ' ');
836}
837
838static int dbg_pinmux_show(struct seq_file *s, void *unused)
839{
840 int i;
841 int len;
842
843 for (i = 0; i < pingroup_max; i++) {
844 unsigned long reg;
845 unsigned long tri;
846 unsigned long mux;
847 unsigned long pupd;
848
849 seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
850 len = strlen(pingroups[i].name);
851 dbg_pad_field(s, 5 - len);
852
853 if (pingroups[i].mux_reg < 0) {
854 seq_printf(s, "TEGRA_MUX_NONE");
855 len = strlen("NONE");
856 } else {
857 reg = pg_readl(pingroups[i].mux_bank,
858 pingroups[i].mux_reg);
859 mux = (reg >> pingroups[i].mux_bit) & 0x3;
860 if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
861 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
862 len = 5;
863 } else {
864 seq_printf(s, "TEGRA_MUX_%s",
865 tegra_mux_names[pingroups[i].funcs[mux]]);
866 len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
867 }
868 }
869 dbg_pad_field(s, 13-len);
870
871 if (pingroups[i].pupd_reg < 0) {
872 seq_printf(s, "TEGRA_PUPD_NORMAL");
873 len = strlen("NORMAL");
874 } else {
875 reg = pg_readl(pingroups[i].pupd_bank,
876 pingroups[i].pupd_reg);
877 pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
878 seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
879 len = strlen(pupd_name(pupd));
880 }
881 dbg_pad_field(s, 9 - len);
882
883 if (pingroups[i].tri_reg < 0) {
884 seq_printf(s, "TEGRA_TRI_NORMAL");
885 } else {
886 reg = pg_readl(pingroups[i].tri_bank,
887 pingroups[i].tri_reg);
888 tri = (reg >> pingroups[i].tri_bit) & 0x1;
889
890 seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
891 }
892 seq_printf(s, "},\n");
893 }
894 return 0;
895}
896
897static int dbg_pinmux_open(struct inode *inode, struct file *file)
898{
899 return single_open(file, dbg_pinmux_show, &inode->i_private);
900}
901
902static const struct file_operations debug_fops = {
903 .open = dbg_pinmux_open,
904 .read = seq_read,
905 .llseek = seq_lseek,
906 .release = single_release,
907};
908
909static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
910{
911 int i;
912 int len;
913
914 for (i = 0; i < drive_max; i++) {
915 u32 reg;
916
917 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
918 drive_pingroups[i].name);
919 len = strlen(drive_pingroups[i].name);
920 dbg_pad_field(s, 7 - len);
921
922
923 reg = pg_readl(drive_pingroups[i].reg_bank,
924 drive_pingroups[i].reg);
925 if (HSM_EN(reg)) {
926 seq_printf(s, "TEGRA_HSM_ENABLE");
927 len = 16;
928 } else {
929 seq_printf(s, "TEGRA_HSM_DISABLE");
930 len = 17;
931 }
932 dbg_pad_field(s, 17 - len);
933
934 if (SCHMT_EN(reg)) {
935 seq_printf(s, "TEGRA_SCHMITT_ENABLE");
936 len = 21;
937 } else {
938 seq_printf(s, "TEGRA_SCHMITT_DISABLE");
939 len = 22;
940 }
941 dbg_pad_field(s, 22 - len);
942
943 seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
944 len = strlen(drive_name(LPMD(reg)));
945 dbg_pad_field(s, 5 - len);
946
947 seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
948 len = DRVDN(reg) < 10 ? 1 : 2;
949 dbg_pad_field(s, 2 - len);
950
951 seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
952 len = DRVUP(reg) < 10 ? 1 : 2;
953 dbg_pad_field(s, 2 - len);
954
955 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
956 len = strlen(slew_name(SLWR(reg)));
957 dbg_pad_field(s, 7 - len);
958
959 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
960
961 seq_printf(s, "},\n");
962 }
963 return 0;
964}
965
966static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
967{
968 return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
969}
970
971static const struct file_operations debug_drive_fops = {
972 .open = dbg_drive_pinmux_open,
973 .read = seq_read,
974 .llseek = seq_lseek,
975 .release = single_release,
976};
977
978static int __init tegra_pinmux_debuginit(void)
979{
980 (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
981 NULL, NULL, &debug_fops);
982 (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
983 NULL, NULL, &debug_drive_fops);
984 return 0;
985}
986late_initcall(tegra_pinmux_debuginit);
987#endif
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index c5b2ac04e2a0..d71d2fed6721 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -711,7 +711,6 @@ struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
711 err = -ENXIO; 711 err = -ENXIO;
712 goto err1; 712 goto err1;
713 } 713 }
714 tegra_gpio_enable(ulpi_config->reset_gpio);
715 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b"); 714 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
716 gpio_direction_output(ulpi_config->reset_gpio, 0); 715 gpio_direction_output(ulpi_config->reset_gpio, 0);
717 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0); 716 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 0e8470a3fbeb..53d3d46dec12 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -9,6 +9,8 @@ config UX500_SOC_COMMON
9 select ARM_ERRATA_754322 9 select ARM_ERRATA_754322
10 select ARM_ERRATA_764369 10 select ARM_ERRATA_764369
11 select CACHE_L2X0 11 select CACHE_L2X0
12 select PINCTRL
13 select PINCTRL_NOMADIK
12 14
13config UX500_SOC_DB8500 15config UX500_SOC_DB8500
14 bool 16 bool
@@ -16,6 +18,7 @@ config UX500_SOC_DB8500
16 select REGULATOR 18 select REGULATOR
17 select REGULATOR_DB8500_PRCMU 19 select REGULATOR_DB8500_PRCMU
18 select CPU_FREQ_TABLE if CPU_FREQ 20 select CPU_FREQ_TABLE if CPU_FREQ
21 select PINCTRL_DB8500
19 22
20menu "Ux500 target platform (boards)" 23menu "Ux500 target platform (boards)"
21 24
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index fc7db5df970b..041c35885981 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \
10 board-mop500-regulators.o \ 10 board-mop500-regulators.o \
11 board-mop500-uib.o board-mop500-stuib.o \ 11 board-mop500-uib.o board-mop500-stuib.o \
12 board-mop500-u8500uib.o \ 12 board-mop500-u8500uib.o \
13 board-mop500-pins.o 13 board-mop500-pins.o \
14 board-mop500-msp.o
14obj-$(CONFIG_SMP) += platsmp.o headsmp.o 15obj-$(CONFIG_SMP) += platsmp.o headsmp.o
15obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 16obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
new file mode 100644
index 000000000000..996048038743
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -0,0 +1,267 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL), version 2
5 */
6
7#include <linux/platform_device.h>
8#include <linux/init.h>
9#include <linux/gpio.h>
10#include <linux/pinctrl/consumer.h>
11
12#include <plat/gpio-nomadik.h>
13#include <plat/pincfg.h>
14#include <plat/ste_dma40.h>
15
16#include <mach/devices.h>
17#include <mach/hardware.h>
18#include <mach/irqs.h>
19#include <mach/msp.h>
20
21#include "ste-dma40-db8500.h"
22#include "board-mop500.h"
23#include "devices-db8500.h"
24#include "pins-db8500.h"
25
26/* MSP1/3 Tx/Rx usage protection */
27static DEFINE_SPINLOCK(msp_rxtx_lock);
28
29/* Reference Count */
30static int msp_rxtx_ref;
31
32/* Pin modes */
33struct pinctrl *msp1_p;
34struct pinctrl_state *msp1_def;
35struct pinctrl_state *msp1_sleep;
36
37int msp13_i2s_init(void)
38{
39 int retval = 0;
40 unsigned long flags;
41
42 spin_lock_irqsave(&msp_rxtx_lock, flags);
43 if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_def))) {
44 retval = pinctrl_select_state(msp1_p, msp1_def);
45 if (retval)
46 pr_err("could not set MSP1 defstate\n");
47 }
48 if (!retval)
49 msp_rxtx_ref++;
50 spin_unlock_irqrestore(&msp_rxtx_lock, flags);
51
52 return retval;
53}
54
55int msp13_i2s_exit(void)
56{
57 int retval = 0;
58 unsigned long flags;
59
60 spin_lock_irqsave(&msp_rxtx_lock, flags);
61 WARN_ON(!msp_rxtx_ref);
62 msp_rxtx_ref--;
63 if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_sleep))) {
64 retval = pinctrl_select_state(msp1_p, msp1_sleep);
65 if (retval)
66 pr_err("could not set MSP1 sleepstate\n");
67 }
68 spin_unlock_irqrestore(&msp_rxtx_lock, flags);
69
70 return retval;
71}
72
73static struct stedma40_chan_cfg msp0_dma_rx = {
74 .high_priority = true,
75 .dir = STEDMA40_PERIPH_TO_MEM,
76
77 .src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
78 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
79
80 .src_info.psize = STEDMA40_PSIZE_LOG_4,
81 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
82
83 /* data_width is set during configuration */
84};
85
86static struct stedma40_chan_cfg msp0_dma_tx = {
87 .high_priority = true,
88 .dir = STEDMA40_MEM_TO_PERIPH,
89
90 .src_dev_type = STEDMA40_DEV_DST_MEMORY,
91 .dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
92
93 .src_info.psize = STEDMA40_PSIZE_LOG_4,
94 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
95
96 /* data_width is set during configuration */
97};
98
99static struct msp_i2s_platform_data msp0_platform_data = {
100 .id = MSP_I2S_0,
101 .msp_i2s_dma_rx = &msp0_dma_rx,
102 .msp_i2s_dma_tx = &msp0_dma_tx,
103};
104
105static struct stedma40_chan_cfg msp1_dma_rx = {
106 .high_priority = true,
107 .dir = STEDMA40_PERIPH_TO_MEM,
108
109 .src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
110 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
111
112 .src_info.psize = STEDMA40_PSIZE_LOG_4,
113 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
114
115 /* data_width is set during configuration */
116};
117
118static struct stedma40_chan_cfg msp1_dma_tx = {
119 .high_priority = true,
120 .dir = STEDMA40_MEM_TO_PERIPH,
121
122 .src_dev_type = STEDMA40_DEV_DST_MEMORY,
123 .dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
124
125 .src_info.psize = STEDMA40_PSIZE_LOG_4,
126 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
127
128 /* data_width is set during configuration */
129};
130
131static struct msp_i2s_platform_data msp1_platform_data = {
132 .id = MSP_I2S_1,
133 .msp_i2s_dma_rx = NULL,
134 .msp_i2s_dma_tx = &msp1_dma_tx,
135 .msp_i2s_init = msp13_i2s_init,
136 .msp_i2s_exit = msp13_i2s_exit,
137};
138
139static struct stedma40_chan_cfg msp2_dma_rx = {
140 .high_priority = true,
141 .dir = STEDMA40_PERIPH_TO_MEM,
142
143 .src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
144 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
145
146 /* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
147 .src_info.psize = STEDMA40_PSIZE_LOG_1,
148 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
149
150 /* data_width is set during configuration */
151};
152
153static struct stedma40_chan_cfg msp2_dma_tx = {
154 .high_priority = true,
155 .dir = STEDMA40_MEM_TO_PERIPH,
156
157 .src_dev_type = STEDMA40_DEV_DST_MEMORY,
158 .dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
159
160 .src_info.psize = STEDMA40_PSIZE_LOG_4,
161 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
162
163 .use_fixed_channel = true,
164 .phy_channel = 1,
165
166 /* data_width is set during configuration */
167};
168
169static struct platform_device *db8500_add_msp_i2s(struct device *parent,
170 int id,
171 resource_size_t base, int irq,
172 struct msp_i2s_platform_data *pdata)
173{
174 struct platform_device *pdev;
175 struct resource res[] = {
176 DEFINE_RES_MEM(base, SZ_4K),
177 DEFINE_RES_IRQ(irq),
178 };
179
180 pr_info("Register platform-device 'ux500-msp-i2s', id %d, irq %d\n",
181 id, irq);
182 pdev = platform_device_register_resndata(parent, "ux500-msp-i2s", id,
183 res, ARRAY_SIZE(res),
184 pdata, sizeof(*pdata));
185 if (!pdev) {
186 pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n",
187 id);
188 return NULL;
189 }
190
191 return pdev;
192}
193
194/* Platform device for ASoC U8500 machine */
195static struct platform_device snd_soc_u8500 = {
196 .name = "snd-soc-u8500",
197 .id = 0,
198 .dev = {
199 .platform_data = NULL,
200 },
201};
202
203/* Platform device for Ux500-PCM */
204static struct platform_device ux500_pcm = {
205 .name = "ux500-pcm",
206 .id = 0,
207 .dev = {
208 .platform_data = NULL,
209 },
210};
211
212static struct msp_i2s_platform_data msp2_platform_data = {
213 .id = MSP_I2S_2,
214 .msp_i2s_dma_rx = &msp2_dma_rx,
215 .msp_i2s_dma_tx = &msp2_dma_tx,
216};
217
218static struct msp_i2s_platform_data msp3_platform_data = {
219 .id = MSP_I2S_3,
220 .msp_i2s_dma_rx = &msp1_dma_rx,
221 .msp_i2s_dma_tx = NULL,
222 .msp_i2s_init = msp13_i2s_init,
223 .msp_i2s_exit = msp13_i2s_exit,
224};
225
226int mop500_msp_init(struct device *parent)
227{
228 struct platform_device *msp1;
229
230 pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__);
231 platform_device_register(&snd_soc_u8500);
232
233 pr_info("Initialize MSP I2S-devices.\n");
234 db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
235 &msp0_platform_data);
236 msp1 = db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
237 &msp1_platform_data);
238 db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
239 &msp2_platform_data);
240 db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
241 &msp3_platform_data);
242
243 /* Get the pinctrl handle for MSP1 */
244 if (msp1) {
245 msp1_p = pinctrl_get(&msp1->dev);
246 if (IS_ERR(msp1_p))
247 dev_err(&msp1->dev, "could not get MSP1 pinctrl\n");
248 else {
249 msp1_def = pinctrl_lookup_state(msp1_p,
250 PINCTRL_STATE_DEFAULT);
251 if (IS_ERR(msp1_def)) {
252 dev_err(&msp1->dev,
253 "could not get MSP1 defstate\n");
254 }
255 msp1_sleep = pinctrl_lookup_state(msp1_p,
256 PINCTRL_STATE_SLEEP);
257 if (IS_ERR(msp1_sleep))
258 dev_err(&msp1->dev,
259 "could not get MSP1 idlestate\n");
260 }
261 }
262
263 pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
264 platform_device_register(&ux500_pcm);
265
266 return 0;
267}
diff --git a/arch/arm/mach-ux500/board-mop500-msp.h b/arch/arm/mach-ux500/board-mop500-msp.h
new file mode 100644
index 000000000000..6fcfb5e2cc94
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-msp.h
@@ -0,0 +1,14 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2012
3 *
4 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
5 * for ST-Ericsson.
6 *
7 * License terms:
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14void mop500_msp_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index f5413dca532c..32fd99204464 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -7,299 +7,508 @@
7#include <linux/kernel.h> 7#include <linux/kernel.h>
8#include <linux/init.h> 8#include <linux/init.h>
9#include <linux/bug.h> 9#include <linux/bug.h>
10#include <linux/string.h>
11#include <linux/pinctrl/machine.h>
10 12
11#include <asm/mach-types.h> 13#include <asm/mach-types.h>
12#include <plat/pincfg.h> 14#include <plat/pincfg.h>
13#include <plat/gpio-nomadik.h> 15#include <plat/gpio-nomadik.h>
16
14#include <mach/hardware.h> 17#include <mach/hardware.h>
15 18
16#include "pins-db8500.h" 19#include "pins-db8500.h"
20#include "board-mop500.h"
17 21
18static pin_cfg_t mop500_pins_common[] = { 22enum custom_pin_cfg_t {
19 /* I2C */ 23 PINS_FOR_DEFAULT,
20 GPIO147_I2C0_SCL, 24 PINS_FOR_U9500,
21 GPIO148_I2C0_SDA, 25};
22 GPIO16_I2C1_SCL,
23 GPIO17_I2C1_SDA,
24 GPIO10_I2C2_SDA,
25 GPIO11_I2C2_SCL,
26 GPIO229_I2C3_SDA,
27 GPIO230_I2C3_SCL,
28
29 /* MSP0 */
30 GPIO12_MSP0_TXD,
31 GPIO13_MSP0_TFS,
32 GPIO14_MSP0_TCK,
33 GPIO15_MSP0_RXD,
34
35 /* MSP2: HDMI */
36 GPIO193_MSP2_TXD,
37 GPIO194_MSP2_TCK,
38 GPIO195_MSP2_TFS,
39 GPIO196_MSP2_RXD | PIN_OUTPUT_LOW,
40
41 /* Touch screen INTERFACE */
42 GPIO84_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT1 */
43
44 /* STMPE1601/tc35893 keypad IRQ */
45 GPIO218_GPIO | PIN_INPUT_PULLUP,
46
47 /* MMC0 (MicroSD card) */
48 GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH,
49 GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH,
50 GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH,
51
52 GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL,
53 GPIO23_MC0_CLK | PIN_OUTPUT_LOW,
54 GPIO24_MC0_CMD | PIN_INPUT_PULLUP,
55 GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP,
56 GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP,
57 GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP,
58 GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP,
59
60 /* SDI1 (SDIO) */
61 GPIO208_MC1_CLK | PIN_OUTPUT_LOW,
62 GPIO209_MC1_FBCLK | PIN_INPUT_NOPULL,
63 GPIO210_MC1_CMD | PIN_INPUT_PULLUP,
64 GPIO211_MC1_DAT0 | PIN_INPUT_PULLUP,
65 GPIO212_MC1_DAT1 | PIN_INPUT_PULLUP,
66 GPIO213_MC1_DAT2 | PIN_INPUT_PULLUP,
67 GPIO214_MC1_DAT3 | PIN_INPUT_PULLUP,
68
69 /* MMC2 (On-board DATA INTERFACE eMMC) */
70 GPIO128_MC2_CLK | PIN_OUTPUT_LOW,
71 GPIO129_MC2_CMD | PIN_INPUT_PULLUP,
72 GPIO130_MC2_FBCLK | PIN_INPUT_NOPULL,
73 GPIO131_MC2_DAT0 | PIN_INPUT_PULLUP,
74 GPIO132_MC2_DAT1 | PIN_INPUT_PULLUP,
75 GPIO133_MC2_DAT2 | PIN_INPUT_PULLUP,
76 GPIO134_MC2_DAT3 | PIN_INPUT_PULLUP,
77 GPIO135_MC2_DAT4 | PIN_INPUT_PULLUP,
78 GPIO136_MC2_DAT5 | PIN_INPUT_PULLUP,
79 GPIO137_MC2_DAT6 | PIN_INPUT_PULLUP,
80 GPIO138_MC2_DAT7 | PIN_INPUT_PULLUP,
81
82 /* MMC4 (On-board STORAGE INTERFACE eMMC) */
83 GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP,
84 GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP,
85 GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP,
86 GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP,
87 GPIO201_MC4_CMD | PIN_INPUT_PULLUP,
88 GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL,
89 GPIO203_MC4_CLK | PIN_OUTPUT_LOW,
90 GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP,
91 GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP,
92 GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP,
93 GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP,
94
95 /* SKE keypad */
96 GPIO153_KP_I7,
97 GPIO154_KP_I6,
98 GPIO155_KP_I5,
99 GPIO156_KP_I4,
100 GPIO157_KP_O7,
101 GPIO158_KP_O6,
102 GPIO159_KP_O5,
103 GPIO160_KP_O4,
104 GPIO161_KP_I3,
105 GPIO162_KP_I2,
106 GPIO163_KP_I1,
107 GPIO164_KP_I0,
108 GPIO165_KP_O3,
109 GPIO166_KP_O2,
110 GPIO167_KP_O1,
111 GPIO168_KP_O0,
112 26
113 /* UART */ 27static enum custom_pin_cfg_t pinsfor;
114 /* uart-0 pins gpio configuration should be 28
115 * kept intact to prevent glitch in tx line 29/* These simply sets bias for pins */
116 * when tty dev is opened. Later these pins 30#define BIAS(a,b) static unsigned long a[] = { b }
31
32BIAS(pd, PIN_PULL_DOWN);
33BIAS(slpm_gpio_nopull, PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
34BIAS(in_nopull, PIN_INPUT_NOPULL);
35BIAS(in_nopull_sleep_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
36BIAS(in_pu, PIN_INPUT_PULLUP);
37BIAS(in_pd, PIN_INPUT_PULLDOWN);
38BIAS(in_pd_slpm_in_pu, PIN_INPUT_PULLDOWN|PIN_SLPM_INPUT_PULLUP);
39BIAS(in_pu_slpm_out_lo, PIN_INPUT_PULLUP|PIN_SLPM_OUTPUT_LOW);
40BIAS(out_hi, PIN_OUTPUT_HIGH);
41BIAS(out_lo, PIN_OUTPUT_LOW);
42BIAS(out_lo_sleep_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
43/* These also force them into GPIO mode */
44BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
45BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
46BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
47BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
48BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
49BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
50/* Sleep modes */
51BIAS(sleep_in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
52BIAS(sleep_in_nopull_wkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE);
53BIAS(sleep_out_hi_wkup_pdis, PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
54BIAS(sleep_out_lo_wkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
55BIAS(sleep_out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
56
57/* We use these to define hog settings that are always done on boot */
58#define DB8500_MUX_HOG(group,func) \
59 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
60#define DB8500_PIN_HOG(pin,conf) \
61 PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
62
63/* These are default states associated with device and changed runtime */
64#define DB8500_MUX(group,func,dev) \
65 PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
66#define DB8500_PIN(pin,conf,dev) \
67 PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
68
69#define DB8500_PIN_SLEEP(pin,conf,dev) \
70 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
71 pin, conf)
72
73/* Pin control settings */
74static struct pinctrl_map __initdata mop500_family_pinmap[] = {
75 /*
76 * uMSP0, mux in 4 pins, regular placement of RX/TX
77 * explicitly set the pins to no pull
78 */
79 DB8500_MUX_HOG("msp0txrx_a_1", "msp0"),
80 DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"),
81 DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */
82 DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */
83 DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */
84 DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */
85 /* MSP2 for HDMI, pull down TXD, TCK, TFS */
86 DB8500_MUX_HOG("msp2_a_1", "msp2"),
87 DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */
88 DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */
89 DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */
90 DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */
91 /*
92 * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
93 * pull-up
94 * TODO: is this really correct? Snowball doesn't have a LCD.
95 */
96 DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
97 DB8500_PIN_HOG("GPIO68_E1", in_pu),
98 DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
99 /*
100 * STMPE1601/tc35893 keypad IRQ GPIO 218
101 * TODO: set for snowball and HREF really??
102 */
103 DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
104 /*
105 * UART0, we do not mux in u0 here.
106 * uart-0 pins gpio configuration should be kept intact to prevent
107 * a glitch in tx line when the tty dev is opened. Later these pins
117 * are configured to uart mop500_pins_uart0 108 * are configured to uart mop500_pins_uart0
118 *
119 * It will be replaced with uart configuration
120 * once the issue is solved.
121 */ 109 */
122 GPIO0_GPIO | PIN_INPUT_PULLUP, 110 DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
123 GPIO1_GPIO | PIN_OUTPUT_HIGH, 111 DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
124 GPIO2_GPIO | PIN_INPUT_PULLUP, 112 DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
125 GPIO3_GPIO | PIN_OUTPUT_HIGH, 113 DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
126 114 /*
127 GPIO29_U2_RXD | PIN_INPUT_PULLUP, 115 * Mux in UART2 on altfunction C and set pull-ups.
128 GPIO30_U2_TXD | PIN_OUTPUT_HIGH, 116 * TODO: is this used on U8500 variants and Snowball really?
129 GPIO31_U2_CTSn | PIN_INPUT_PULLUP, 117 * The setting on GPIO31 conflicts with magnetometer use on hrefv60
130 GPIO32_U2_RTSn | PIN_OUTPUT_HIGH, 118 */
131 119 DB8500_MUX_HOG("u2rxtx_c_1", "u2"),
132 /* Display & HDMI HW sync */ 120 DB8500_MUX_HOG("u2ctsrts_c_1", "u2"),
133 GPIO68_LCD_VSI0 | PIN_INPUT_PULLUP, 121 DB8500_PIN_HOG("GPIO29_W2", in_pu), /* RXD */
134 GPIO69_LCD_VSI1 | PIN_INPUT_PULLUP, 122 DB8500_PIN_HOG("GPIO30_W3", out_hi), /* TXD */
123 DB8500_PIN_HOG("GPIO31_V3", in_pu), /* CTS */
124 DB8500_PIN_HOG("GPIO32_V2", out_hi), /* RTS */
125 /*
126 * The following pin sets were known as "runtime pins" before being
127 * converted to the pinctrl model. Here we model them as "default"
128 * states.
129 */
130 /* Mux in UART0 after initialization */
131 DB8500_MUX("u0_a_1", "u0", "uart0"),
132 DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
133 DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
134 DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
135 DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
136 /* UART0 sleep state */
137 DB8500_PIN_SLEEP("GPIO0_AJ5", sleep_in_wkup_pdis, "uart0"),
138 DB8500_PIN_SLEEP("GPIO1_AJ3", sleep_out_hi_wkup_pdis, "uart0"),
139 DB8500_PIN_SLEEP("GPIO2_AH4", sleep_in_wkup_pdis, "uart0"),
140 DB8500_PIN_SLEEP("GPIO3_AH3", sleep_out_wkup_pdis, "uart0"),
141 /* MSP1 for ALSA codec */
142 DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
143 DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
144 DB8500_PIN("GPIO33_AF2", out_lo_sleep_nowkup, "ux500-msp-i2s.1"),
145 DB8500_PIN("GPIO34_AE1", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
146 DB8500_PIN("GPIO35_AE2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
147 DB8500_PIN("GPIO36_AG2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
148 /* MSP1 sleep state */
149 DB8500_PIN_SLEEP("GPIO33_AF2", sleep_out_lo_wkup, "ux500-msp-i2s.1"),
150 DB8500_PIN_SLEEP("GPIO34_AE1", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
151 DB8500_PIN_SLEEP("GPIO35_AE2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
152 DB8500_PIN_SLEEP("GPIO36_AG2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
153 /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
154 DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
155 DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
156 /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
157 DB8500_MUX("lcdvsi1_a_1", "lcd", "av8100-hdmi"),
158 /* Mux in I2C blocks, put pins into GPIO in sleepmode no pull-up */
159 DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
160 DB8500_PIN("GPIO147_C15", slpm_gpio_nopull, "nmk-i2c.0"),
161 DB8500_PIN("GPIO148_B16", slpm_gpio_nopull, "nmk-i2c.0"),
162 DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
163 DB8500_PIN("GPIO16_AD3", slpm_gpio_nopull, "nmk-i2c.1"),
164 DB8500_PIN("GPIO17_AD4", slpm_gpio_nopull, "nmk-i2c.1"),
165 DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
166 DB8500_PIN("GPIO10_AF5", slpm_gpio_nopull, "nmk-i2c.2"),
167 DB8500_PIN("GPIO11_AG4", slpm_gpio_nopull, "nmk-i2c.2"),
168 DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
169 DB8500_PIN("GPIO229_AG7", slpm_gpio_nopull, "nmk-i2c.3"),
170 DB8500_PIN("GPIO230_AF7", slpm_gpio_nopull, "nmk-i2c.3"),
171 /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
172 DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
173 DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
174 DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */
175 DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */
176 DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */
177 DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */
178 DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */
179 DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */
180 DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
181 DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
182 DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
183 /* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
184 DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
185 DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
186 DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */
187 DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */
188 DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */
189 DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
190 DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
191 DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
192 /* Mux in SDI2 (here called MC2) used for for PoP eMMC */
193 DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
194 DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
195 DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */
196 DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */
197 DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */
198 DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */
199 DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */
200 DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */
201 DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */
202 DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
203 DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
204 DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
205 /* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
206 DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
207 DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
208 DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */
209 DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */
210 DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */
211 DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */
212 DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */
213 DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */
214 DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */
215 DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
216 DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
217 DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
218 /* Mux in USB pins, drive STP high */
219 DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
220 DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
221 /* Mux in SPI2 pins on the "other C1" altfunction */
222 DB8500_MUX("spi2_oc1_1", "spi2", "spi2"),
223 DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
224 DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
225 DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
226 DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
135}; 227};
136 228
137static pin_cfg_t mop500_pins_default[] = { 229/*
138 /* SSP0 */ 230 * These are specifically for the MOP500 and HREFP (pre-v60) version of the
139 GPIO143_SSP0_CLK, 231 * board, which utilized a TC35892 GPIO expander instead of using a lot of
140 GPIO144_SSP0_FRM, 232 * on-chip pins as the HREFv60 and later does.
141 GPIO145_SSP0_RXD | PIN_PULL_DOWN, 233 */
142 GPIO146_SSP0_TXD, 234static struct pinctrl_map __initdata mop500_pinmap[] = {
143 235 /* Mux in SSP0, pull down RXD pin */
144 236 DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
145 GPIO217_GPIO | PIN_INPUT_PULLUP, /* TC35892 IRQ */ 237 DB8500_PIN_HOG("GPIO145_C13", pd),
146 238 /*
147 /* SDI0 (MicroSD card) */ 239 * XENON Flashgun on image processor GPIO (controlled from image
148 GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, 240 * processor firmware), mux in these image processor GPIO lines 0
149 241 * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
150 /* UART */ 242 * the pins.
151 GPIO4_U1_RXD | PIN_INPUT_PULLUP, 243 */
152 GPIO5_U1_TXD | PIN_OUTPUT_HIGH, 244 DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
153 GPIO6_U1_CTSn | PIN_INPUT_PULLUP, 245 DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
154 GPIO7_U1_RTSn | PIN_OUTPUT_HIGH, 246 DB8500_PIN_HOG("GPIO6_AF6", in_pu),
247 DB8500_PIN_HOG("GPIO7_AG5", in_pu),
248 /* TC35892 IRQ, pull up the line, let the driver mux in the pin */
249 DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
250 /* Mux in UART1 and set the pull-ups */
251 DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
252 DB8500_MUX_HOG("u1ctsrts_a_1", "u1"),
253 DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
254 DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
255 DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* CTS */
256 DB8500_PIN_HOG("GPIO7_AG5", out_hi), /* RTS */
257 /*
258 * Runtime stuff: make it possible to mux in the SKE keypad
259 * and bias the pins
260 */
261 DB8500_MUX("kp_a_2", "kp", "ske"),
262 DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */
263 DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */
264 DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */
265 DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */
266 DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */
267 DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */
268 DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */
269 DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */
270 DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */
271 DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */
272 DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */
273 DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */
274 DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */
275 DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */
276 DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */
277 DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */
278 /* Mux in and drive the SDI0 DAT31DIR line high at runtime */
279 DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
280 DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
155}; 281};
156 282
157static pin_cfg_t hrefv60_pins[] = { 283/*
158 /* WLAN */ 284 * The HREFv60 series of platforms is using available pins on the DB8500
159 GPIO4_GPIO | PIN_INPUT_PULLUP,/* WLAN_IRQ */ 285 * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
160 GPIO85_GPIO | PIN_OUTPUT_LOW,/* WLAN_ENA */ 286 * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
161 287 */
162 /* XENON Flashgun INTERFACE */ 288static struct pinctrl_map __initdata hrefv60_pinmap[] = {
163 GPIO6_IP_GPIO0 | PIN_INPUT_PULLUP,/* XENON_FLASH_ID */ 289 /* Drive WLAN_ENA low */
164 GPIO7_IP_GPIO1 | PIN_INPUT_PULLUP,/* XENON_READY */ 290 DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
165 GPIO170_GPIO | PIN_OUTPUT_LOW, /* XENON_CHARGE */ 291 /*
166 292 * XENON Flashgun on image processor GPIO (controlled from image
167 /* Assistant LED INTERFACE */ 293 * processor firmware), mux in these image processor GPIO lines 0
168 GPIO21_GPIO | PIN_OUTPUT_LOW, /* XENON_EN1 */ 294 * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
169 GPIO64_IP_GPIO4 | PIN_OUTPUT_LOW, /* XENON_EN2 */ 295 * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
170 296 * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
171 /* Magnetometer */ 297 */
172 GPIO31_GPIO | PIN_INPUT_PULLUP, /* magnetometer_INT */ 298 DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
173 GPIO32_GPIO | PIN_INPUT_PULLDOWN, /* Magnetometer DRDY */ 299 DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
174 300 DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
175 /* Display Interface */ 301 DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
176 GPIO65_GPIO | PIN_OUTPUT_LOW, /* DISP1 RST */ 302 DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
177 GPIO66_GPIO | PIN_OUTPUT_LOW, /* DISP2 RST */ 303 DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
178 304 DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
179 /* Touch screen INTERFACE */ 305 /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
180 GPIO143_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST1 */ 306 DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
181 307 DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
182 /* Touch screen INTERFACE 2 */ 308 /*
183 GPIO67_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT2 */ 309 * Display Interface 1 uses GPIO 65 for RST (reset).
184 GPIO146_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST2 */ 310 * Display Interface 2 uses GPIO 66 for RST (reset).
185 311 * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
186 /* ETM_PTM_TRACE INTERFACE */ 312 */
187 GPIO70_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA23 */ 313 DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
188 GPIO71_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA22 */ 314 DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
189 GPIO72_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA21 */ 315 /*
190 GPIO73_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA20 */ 316 * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
191 GPIO74_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA19 */ 317 * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
192 318 * reset signals low.
193 /* NAHJ INTERFACE */ 319 */
194 GPIO76_GPIO | PIN_OUTPUT_LOW,/* NAHJ_CTRL */ 320 DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
195 GPIO216_GPIO | PIN_OUTPUT_HIGH,/* NAHJ_CTRL_INV */ 321 DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
196 322 DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
197 /* NFC INTERFACE */ 323 /*
198 GPIO77_GPIO | PIN_OUTPUT_LOW, /* NFC_ENA */ 324 * Drive D19-D23 for the ETM PTM trace interface low,
199 GPIO144_GPIO | PIN_INPUT_PULLDOWN, /* NFC_IRQ */ 325 * (presumably pins are unconnected therefore grounded here,
200 GPIO142_GPIO | PIN_OUTPUT_LOW, /* NFC_RESET */ 326 * the "other alt C1" setting enables these pins)
201 327 */
202 /* Keyboard MATRIX INTERFACE */ 328 DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
203 GPIO90_MC5_CMD | PIN_OUTPUT_LOW, /* KP_O_1 */ 329 DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
204 GPIO87_MC5_DAT1 | PIN_OUTPUT_LOW, /* KP_O_2 */ 330 DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
205 GPIO86_MC5_DAT0 | PIN_OUTPUT_LOW, /* KP_O_3 */ 331 DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
206 GPIO96_KP_O6 | PIN_OUTPUT_LOW, /* KP_O_6 */ 332 DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
207 GPIO94_KP_O7 | PIN_OUTPUT_LOW, /* KP_O_7 */ 333 /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
208 GPIO93_MC5_DAT4 | PIN_INPUT_PULLUP, /* KP_I_0 */ 334 DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
209 GPIO89_MC5_DAT3 | PIN_INPUT_PULLUP, /* KP_I_2 */ 335 DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
210 GPIO88_MC5_DAT2 | PIN_INPUT_PULLUP, /* KP_I_3 */ 336 /* NFC ENA and RESET to low, pulldown IRQ line */
211 GPIO91_GPIO | PIN_INPUT_PULLUP, /* FORCE_SENSING_INT */ 337 DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
212 GPIO92_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_RST */ 338 DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
213 GPIO97_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_WU */ 339 DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
214 340 /*
215 /* DiPro Sensor Interface */ 341 * SKE keyboard partly on alt A and partly on "Other alt C1"
216 GPIO139_GPIO | PIN_INPUT_PULLUP, /* DIPRO_INT */ 342 * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
217 343 * rows of 6 keys, then pull up force sensing interrup and
218 /* HAL SWITCH INTERFACE */ 344 * drive reset and force sensing WU low.
219 GPIO145_GPIO | PIN_INPUT_PULLDOWN,/* HAL_SW */ 345 */
220 346 DB8500_MUX_HOG("kp_a_1", "kp"),
221 /* Audio Amplifier Interface */ 347 DB8500_MUX_HOG("kp_oc1_1", "kp"),
222 GPIO149_GPIO | PIN_OUTPUT_LOW, /* VAUDIO_HF_EN */ 348 DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
223 349 DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
224 /* GBF INTERFACE */ 350 DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
225 GPIO171_GPIO | PIN_OUTPUT_LOW, /* GBF_ENA_RESET */ 351 DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
226 352 DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
227 /* MSP : HDTV INTERFACE */ 353 DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
228 GPIO192_GPIO | PIN_INPUT_PULLDOWN, 354 DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
229 355 DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
230 /* ACCELEROMETER_INTERFACE */ 356 DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
231 GPIO82_GPIO | PIN_INPUT_PULLUP, /* ACC_INT1 */ 357 DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
232 GPIO83_GPIO | PIN_INPUT_PULLUP, /* ACC_INT2 */ 358 DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
233 359 /* DiPro Sensor interrupt */
234 /* Proximity Sensor */ 360 DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
235 GPIO217_GPIO | PIN_INPUT_PULLUP, 361 /* Audio Amplifier HF enable */
236 362 DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
237 363 /* GBF interface, pull low to reset state */
364 DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
365 /* MSP : HDTV INTERFACE GPIO line */
366 DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
367 /* Accelerometer interrupt lines */
368 DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
369 DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
370 /* SD card detect GPIO pin */
371 DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu),
372 /*
373 * Runtime stuff
374 * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
375 * etc.
376 */
377 DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
378 DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
379 DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
380 /*
381 * Make it possible to mux in the SKE keypad and bias the pins
382 * FIXME: what's the point with this on HREFv60? KP/SKE is already
383 * muxed in at another place! Enabling this will bork.
384 */
385 DB8500_MUX("kp_a_2", "kp", "ske"),
386 DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */
387 DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */
388 DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */
389 DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */
390 DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */
391 DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */
392 DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */
393 DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */
394 DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */
395 DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */
396 DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */
397 DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */
398 DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */
399 DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */
400 DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */
401 DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */
238}; 402};
239 403
240static pin_cfg_t snowball_pins[] = { 404static struct pinctrl_map __initdata u9500_pinmap[] = {
241 /* SSP0, to AB8500 */ 405 /* Mux in UART1 (just RX/TX) and set the pull-ups */
242 GPIO143_SSP0_CLK, 406 DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
243 GPIO144_SSP0_FRM, 407 DB8500_PIN_HOG("GPIO4_AH6", in_pu),
244 GPIO145_SSP0_RXD | PIN_PULL_DOWN, 408 DB8500_PIN_HOG("GPIO5_AG6", out_hi),
245 GPIO146_SSP0_TXD, 409 /* WLAN_IRQ line */
410 DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
411 /* HSI */
412 DB8500_MUX_HOG("hsir_a_1", "hsi"),
413 DB8500_MUX_HOG("hsit_a_1", "hsi"),
414 DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
415 DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
416 DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
417 DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
418 DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
419 DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
420 DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
421 DB8500_PIN_HOG("GPIO226_AF8", out_hi), /* ACWAKE0 */
422};
246 423
247 /* MMC0: MicroSD card */ 424static struct pinctrl_map __initdata u8500_pinmap[] = {
248 GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, 425 DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
426 DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
427};
249 428
250 /* MMC2: LAN */ 429static struct pinctrl_map __initdata snowball_pinmap[] = {
251 GPIO86_SM_ADQ0, 430 /* Mux in SSP0 connected to AB8500, pull down RXD pin */
252 GPIO87_SM_ADQ1, 431 DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
253 GPIO88_SM_ADQ2, 432 DB8500_PIN_HOG("GPIO145_C13", pd),
254 GPIO89_SM_ADQ3, 433 /* Always drive the MC0 DAT31DIR line high on these boards */
255 GPIO90_SM_ADQ4, 434 DB8500_PIN_HOG("GPIO21_AB3", out_hi),
256 GPIO91_SM_ADQ5, 435 /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
257 GPIO92_SM_ADQ6, 436 DB8500_MUX_HOG("sm_b_1", "sm"),
258 GPIO93_SM_ADQ7, 437 /* Drive RSTn_LAN high */
438 DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
439 /* Accelerometer/Magnetometer */
440 DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
441 DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
442 DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
443 /* WLAN/GBF */
444 DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
445 DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
446 DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
447 DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
448};
259 449
260 GPIO94_SM_ADVn, 450/*
261 GPIO95_SM_CS0n, 451 * passing "pinsfor=" in kernel cmdline allows for custom
262 GPIO96_SM_OEn, 452 * configuration of GPIOs on u8500 derived boards.
263 GPIO97_SM_WEn, 453 */
454static int __init early_pinsfor(char *p)
455{
456 pinsfor = PINS_FOR_DEFAULT;
264 457
265 GPIO128_SM_CKO, 458 if (strcmp(p, "u9500-21") == 0)
266 GPIO130_SM_FBCLK, 459 pinsfor = PINS_FOR_U9500;
267 GPIO131_SM_ADQ8,
268 GPIO132_SM_ADQ9,
269 GPIO133_SM_ADQ10,
270 GPIO134_SM_ADQ11,
271 GPIO135_SM_ADQ12,
272 GPIO136_SM_ADQ13,
273 GPIO137_SM_ADQ14,
274 GPIO138_SM_ADQ15,
275 460
276 /* RSTn_LAN */ 461 return 0;
277 GPIO141_GPIO | PIN_OUTPUT_HIGH, 462}
278}; 463early_param("pinsfor", early_pinsfor);
279 464
280void __init mop500_pins_init(void) 465int pins_for_u9500(void)
281{ 466{
282 nmk_config_pins(mop500_pins_common, 467 if (pinsfor == PINS_FOR_U9500)
283 ARRAY_SIZE(mop500_pins_common)); 468 return 1;
284 469
285 nmk_config_pins(mop500_pins_default, 470 return 0;
286 ARRAY_SIZE(mop500_pins_default));
287} 471}
288 472
289void __init snowball_pins_init(void) 473static void __init mop500_href_family_pinmaps_init(void)
290{ 474{
291 nmk_config_pins(mop500_pins_common, 475 switch (pinsfor) {
292 ARRAY_SIZE(mop500_pins_common)); 476 case PINS_FOR_U9500:
477 pinctrl_register_mappings(u9500_pinmap,
478 ARRAY_SIZE(u9500_pinmap));
479 break;
480 case PINS_FOR_DEFAULT:
481 pinctrl_register_mappings(u8500_pinmap,
482 ARRAY_SIZE(u8500_pinmap));
483 default:
484 break;
485 }
486}
293 487
294 nmk_config_pins(snowball_pins, 488void __init mop500_pinmaps_init(void)
295 ARRAY_SIZE(snowball_pins)); 489{
490 pinctrl_register_mappings(mop500_family_pinmap,
491 ARRAY_SIZE(mop500_family_pinmap));
492 pinctrl_register_mappings(mop500_pinmap,
493 ARRAY_SIZE(mop500_pinmap));
494 mop500_href_family_pinmaps_init();
296} 495}
297 496
298void __init hrefv60_pins_init(void) 497void __init snowball_pinmaps_init(void)
299{ 498{
300 nmk_config_pins(mop500_pins_common, 499 pinctrl_register_mappings(mop500_family_pinmap,
301 ARRAY_SIZE(mop500_pins_common)); 500 ARRAY_SIZE(mop500_family_pinmap));
501 pinctrl_register_mappings(snowball_pinmap,
502 ARRAY_SIZE(snowball_pinmap));
503 pinctrl_register_mappings(u8500_pinmap,
504 ARRAY_SIZE(u8500_pinmap));
505}
302 506
303 nmk_config_pins(hrefv60_pins, 507void __init hrefv60_pinmaps_init(void)
304 ARRAY_SIZE(hrefv60_pins)); 508{
509 pinctrl_register_mappings(mop500_family_pinmap,
510 ARRAY_SIZE(mop500_family_pinmap));
511 pinctrl_register_mappings(hrefv60_pinmap,
512 ARRAY_SIZE(hrefv60_pinmap));
513 mop500_href_family_pinmaps_init();
305} 514}
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index f8150155a442..4bc0cbc5f071 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -1,3 +1,4 @@
1
1/* 2/*
2 * Copyright (C) 2008-2009 ST-Ericsson 3 * Copyright (C) 2008-2009 ST-Ericsson
3 * 4 *
@@ -29,18 +30,17 @@
29#include <linux/smsc911x.h> 30#include <linux/smsc911x.h>
30#include <linux/gpio_keys.h> 31#include <linux/gpio_keys.h>
31#include <linux/delay.h> 32#include <linux/delay.h>
32
33#include <linux/of.h> 33#include <linux/of.h>
34#include <linux/of_platform.h> 34#include <linux/of_platform.h>
35
36#include <linux/leds.h> 35#include <linux/leds.h>
36#include <linux/pinctrl/consumer.h>
37
37#include <asm/mach-types.h> 38#include <asm/mach-types.h>
38#include <asm/mach/arch.h> 39#include <asm/mach/arch.h>
39#include <asm/hardware/gic.h> 40#include <asm/hardware/gic.h>
40 41
41#include <plat/i2c.h> 42#include <plat/i2c.h>
42#include <plat/ste_dma40.h> 43#include <plat/ste_dma40.h>
43#include <plat/pincfg.h>
44#include <plat/gpio-nomadik.h> 44#include <plat/gpio-nomadik.h>
45 45
46#include <mach/hardware.h> 46#include <mach/hardware.h>
@@ -48,11 +48,11 @@
48#include <mach/devices.h> 48#include <mach/devices.h>
49#include <mach/irqs.h> 49#include <mach/irqs.h>
50 50
51#include "pins-db8500.h"
52#include "ste-dma40-db8500.h" 51#include "ste-dma40-db8500.h"
53#include "devices-db8500.h" 52#include "devices-db8500.h"
54#include "board-mop500.h" 53#include "board-mop500.h"
55#include "board-mop500-regulators.h" 54#include "board-mop500-regulators.h"
55#include "board-mop500-msp.h"
56 56
57static struct gpio_led snowball_led_array[] = { 57static struct gpio_led snowball_led_array[] = {
58 { 58 {
@@ -520,14 +520,6 @@ static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
520}; 520};
521#endif 521#endif
522 522
523
524static pin_cfg_t mop500_pins_uart0[] = {
525 GPIO0_U0_CTSn | PIN_INPUT_PULLUP,
526 GPIO1_U0_RTSn | PIN_OUTPUT_HIGH,
527 GPIO2_U0_RXD | PIN_INPUT_PULLUP,
528 GPIO3_U0_TXD | PIN_OUTPUT_HIGH,
529};
530
531#define PRCC_K_SOFTRST_SET 0x18 523#define PRCC_K_SOFTRST_SET 0x18
532#define PRCC_K_SOFTRST_CLEAR 0x1C 524#define PRCC_K_SOFTRST_CLEAR 0x1C
533static void ux500_uart0_reset(void) 525static void ux500_uart0_reset(void)
@@ -548,24 +540,33 @@ static void ux500_uart0_reset(void)
548 udelay(1); 540 udelay(1);
549} 541}
550 542
543/* This needs to be referenced by callbacks */
544struct pinctrl *u0_p;
545struct pinctrl_state *u0_def;
546struct pinctrl_state *u0_sleep;
547
551static void ux500_uart0_init(void) 548static void ux500_uart0_init(void)
552{ 549{
553 int ret; 550 int ret;
554 551
555 ret = nmk_config_pins(mop500_pins_uart0, 552 if (IS_ERR(u0_p) || IS_ERR(u0_def))
556 ARRAY_SIZE(mop500_pins_uart0)); 553 return;
557 if (ret < 0) 554
558 pr_err("pl011: uart pins_enable failed\n"); 555 ret = pinctrl_select_state(u0_p, u0_def);
556 if (ret)
557 pr_err("could not set UART0 defstate\n");
559} 558}
560 559
561static void ux500_uart0_exit(void) 560static void ux500_uart0_exit(void)
562{ 561{
563 int ret; 562 int ret;
564 563
565 ret = nmk_config_pins_sleep(mop500_pins_uart0, 564 if (IS_ERR(u0_p) || IS_ERR(u0_sleep))
566 ARRAY_SIZE(mop500_pins_uart0)); 565 return;
567 if (ret < 0) 566
568 pr_err("pl011: uart pins_disable failed\n"); 567 ret = pinctrl_select_state(u0_p, u0_sleep);
568 if (ret)
569 pr_err("could not set UART0 idlestate\n");
569} 570}
570 571
571static struct amba_pl011_data uart0_plat = { 572static struct amba_pl011_data uart0_plat = {
@@ -597,7 +598,28 @@ static struct amba_pl011_data uart2_plat = {
597 598
598static void __init mop500_uart_init(struct device *parent) 599static void __init mop500_uart_init(struct device *parent)
599{ 600{
600 db8500_add_uart0(parent, &uart0_plat); 601 struct amba_device *uart0_device;
602
603 uart0_device = db8500_add_uart0(parent, &uart0_plat);
604 if (uart0_device) {
605 u0_p = pinctrl_get(&uart0_device->dev);
606 if (IS_ERR(u0_p))
607 dev_err(&uart0_device->dev,
608 "could not get UART0 pinctrl\n");
609 else {
610 u0_def = pinctrl_lookup_state(u0_p,
611 PINCTRL_STATE_DEFAULT);
612 if (IS_ERR(u0_def)) {
613 dev_err(&uart0_device->dev,
614 "could not get UART0 defstate\n");
615 }
616 u0_sleep = pinctrl_lookup_state(u0_p,
617 PINCTRL_STATE_SLEEP);
618 if (IS_ERR(u0_sleep))
619 dev_err(&uart0_device->dev,
620 "could not get UART0 idlestate\n");
621 }
622 }
601 db8500_add_uart1(parent, &uart1_plat); 623 db8500_add_uart1(parent, &uart1_plat);
602 db8500_add_uart2(parent, &uart2_plat); 624 db8500_add_uart2(parent, &uart2_plat);
603} 625}
@@ -616,10 +638,9 @@ static void __init mop500_init_machine(void)
616 638
617 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; 639 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
618 640
641 mop500_pinmaps_init();
619 parent = u8500_init_devices(); 642 parent = u8500_init_devices();
620 643
621 mop500_pins_init();
622
623 /* FIXME: parent of ab8500 should be prcmu */ 644 /* FIXME: parent of ab8500 should be prcmu */
624 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) 645 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
625 mop500_platform_devs[i]->dev.parent = parent; 646 mop500_platform_devs[i]->dev.parent = parent;
@@ -630,6 +651,7 @@ static void __init mop500_init_machine(void)
630 mop500_i2c_init(parent); 651 mop500_i2c_init(parent);
631 mop500_sdi_init(parent); 652 mop500_sdi_init(parent);
632 mop500_spi_init(parent); 653 mop500_spi_init(parent);
654 mop500_msp_init(parent);
633 mop500_uart_init(parent); 655 mop500_uart_init(parent);
634 656
635 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); 657 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@@ -647,10 +669,9 @@ static void __init snowball_init_machine(void)
647 struct device *parent = NULL; 669 struct device *parent = NULL;
648 int i; 670 int i;
649 671
672 snowball_pinmaps_init();
650 parent = u8500_init_devices(); 673 parent = u8500_init_devices();
651 674
652 snowball_pins_init();
653
654 for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++) 675 for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
655 snowball_platform_devs[i]->dev.parent = parent; 676 snowball_platform_devs[i]->dev.parent = parent;
656 677
@@ -660,6 +681,7 @@ static void __init snowball_init_machine(void)
660 mop500_i2c_init(parent); 681 mop500_i2c_init(parent);
661 snowball_sdi_init(parent); 682 snowball_sdi_init(parent);
662 mop500_spi_init(parent); 683 mop500_spi_init(parent);
684 mop500_msp_init(parent);
663 mop500_uart_init(parent); 685 mop500_uart_init(parent);
664 686
665 /* This board has full regulator constraints */ 687 /* This board has full regulator constraints */
@@ -679,10 +701,9 @@ static void __init hrefv60_init_machine(void)
679 */ 701 */
680 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; 702 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
681 703
704 hrefv60_pinmaps_init();
682 parent = u8500_init_devices(); 705 parent = u8500_init_devices();
683 706
684 hrefv60_pins_init();
685
686 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) 707 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
687 mop500_platform_devs[i]->dev.parent = parent; 708 mop500_platform_devs[i]->dev.parent = parent;
688 709
@@ -692,6 +713,7 @@ static void __init hrefv60_init_machine(void)
692 mop500_i2c_init(parent); 713 mop500_i2c_init(parent);
693 hrefv60_sdi_init(parent); 714 hrefv60_sdi_init(parent);
694 mop500_spi_init(parent); 715 mop500_spi_init(parent);
716 mop500_msp_init(parent);
695 mop500_uart_init(parent); 717 mop500_uart_init(parent);
696 718
697 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); 719 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@@ -739,10 +761,22 @@ MACHINE_END
739#ifdef CONFIG_MACH_UX500_DT 761#ifdef CONFIG_MACH_UX500_DT
740 762
741struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { 763struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
764 /* Requires DMA and call-back bindings. */
742 OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), 765 OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
743 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat), 766 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
744 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), 767 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
768 /* Requires DMA bindings. */
745 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), 769 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
770 /* Requires clock name bindings. */
771 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
772 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
773 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
774 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
775 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
776 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
777 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
778 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
779 OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
746 {}, 780 {},
747}; 781};
748 782
@@ -759,6 +793,14 @@ static void __init u8500_init_machine(void)
759 int i2c0_devs; 793 int i2c0_devs;
760 int i; 794 int i;
761 795
796 /* Pinmaps must be in place before devices register */
797 if (of_machine_is_compatible("st-ericsson,mop500"))
798 mop500_pinmaps_init();
799 else if (of_machine_is_compatible("calaosystems,snowball-a9500"))
800 snowball_pinmaps_init();
801 else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
802 hrefv60_pinmaps_init();
803
762 parent = u8500_init_devices(); 804 parent = u8500_init_devices();
763 805
764 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) 806 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
@@ -771,7 +813,6 @@ static void __init u8500_init_machine(void)
771 813
772 if (of_machine_is_compatible("st-ericsson,mop500")) { 814 if (of_machine_is_compatible("st-ericsson,mop500")) {
773 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; 815 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
774 mop500_pins_init();
775 816
776 platform_add_devices(mop500_platform_devs, 817 platform_add_devices(mop500_platform_devs,
777 ARRAY_SIZE(mop500_platform_devs)); 818 ARRAY_SIZE(mop500_platform_devs));
@@ -784,7 +825,6 @@ static void __init u8500_init_machine(void)
784 ARRAY_SIZE(mop500_i2c2_devices)); 825 ARRAY_SIZE(mop500_i2c2_devices));
785 826
786 } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { 827 } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
787 snowball_pins_init();
788 platform_add_devices(snowball_platform_devs, 828 platform_add_devices(snowball_platform_devs,
789 ARRAY_SIZE(snowball_platform_devs)); 829 ARRAY_SIZE(snowball_platform_devs));
790 830
@@ -796,7 +836,6 @@ static void __init u8500_init_machine(void)
796 * instead. 836 * instead.
797 */ 837 */
798 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; 838 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
799 hrefv60_pins_init();
800 platform_add_devices(mop500_platform_devs, 839 platform_add_devices(mop500_platform_devs,
801 ARRAY_SIZE(mop500_platform_devs)); 840 ARRAY_SIZE(mop500_platform_devs));
802 841
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index fdcfa8721bb4..bc44c07c71a9 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -7,6 +7,9 @@
7#ifndef __BOARD_MOP500_H 7#ifndef __BOARD_MOP500_H
8#define __BOARD_MOP500_H 8#define __BOARD_MOP500_H
9 9
10/* For NOMADIK_NR_GPIO */
11#include <mach/irqs.h>
12
10/* Snowball specific GPIO assignments, this board has no GPIO expander */ 13/* Snowball specific GPIO assignments, this board has no GPIO expander */
11#define SNOWBALL_ACCEL_INT1_GPIO 163 14#define SNOWBALL_ACCEL_INT1_GPIO 163
12#define SNOWBALL_ACCEL_INT2_GPIO 164 15#define SNOWBALL_ACCEL_INT2_GPIO 164
@@ -73,6 +76,7 @@
73#define SNOWBALL_PME_ETH_GPIO MOP500_AB8500_PIN_GPIO(24) /* SYSCLKREQ7/GPIO24 */ 76#define SNOWBALL_PME_ETH_GPIO MOP500_AB8500_PIN_GPIO(24) /* SYSCLKREQ7/GPIO24 */
74#define SNOWBALL_EN_3V3_ETH_GPIO MOP500_AB8500_PIN_GPIO(26) /* GPIO26 */ 77#define SNOWBALL_EN_3V3_ETH_GPIO MOP500_AB8500_PIN_GPIO(26) /* GPIO26 */
75 78
79struct device;
76struct i2c_board_info; 80struct i2c_board_info;
77 81
78extern void mop500_sdi_init(struct device *parent); 82extern void mop500_sdi_init(struct device *parent);
@@ -81,9 +85,9 @@ extern void hrefv60_sdi_init(struct device *parent);
81extern void mop500_sdi_tc35892_init(struct device *parent); 85extern void mop500_sdi_tc35892_init(struct device *parent);
82void __init mop500_u8500uib_init(void); 86void __init mop500_u8500uib_init(void);
83void __init mop500_stuib_init(void); 87void __init mop500_stuib_init(void);
84void __init mop500_pins_init(void); 88void __init mop500_pinmaps_init(void);
85void __init hrefv60_pins_init(void); 89void __init snowball_pinmaps_init(void);
86void __init snowball_pins_init(void); 90void __init hrefv60_pinmaps_init(void);
87 91
88void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, 92void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
89 unsigned n); 93 unsigned n);
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 063f3dbd45a9..a121cb472dd6 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -334,6 +334,7 @@ static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */
334 */ 334 */
335 335
336/* Peripheral Cluster #1 */ 336/* Peripheral Cluster #1 */
337static DEFINE_PRCC_CLK(1, msp3, 11, 10, &clk_msp1clk);
337static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); 338static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk);
338static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); 339static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL);
339static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); 340static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk);
@@ -403,7 +404,7 @@ static struct clk_lookup u8500_clks[] = {
403 CLK(slimbus0, "slimbus0", NULL), 404 CLK(slimbus0, "slimbus0", NULL),
404 CLK(i2c2, "nmk-i2c.2", NULL), 405 CLK(i2c2, "nmk-i2c.2", NULL),
405 CLK(sdi0, "sdi0", NULL), 406 CLK(sdi0, "sdi0", NULL),
406 CLK(msp0, "msp0", NULL), 407 CLK(msp0, "ux500-msp-i2s.0", NULL),
407 CLK(i2c1, "nmk-i2c.1", NULL), 408 CLK(i2c1, "nmk-i2c.1", NULL),
408 CLK(uart1, "uart1", NULL), 409 CLK(uart1, "uart1", NULL),
409 CLK(uart0, "uart0", NULL), 410 CLK(uart0, "uart0", NULL),
@@ -453,7 +454,8 @@ static struct clk_lookup u8500_clks[] = {
453 /* Peripheral Cluster #1 */ 454 /* Peripheral Cluster #1 */
454 CLK(i2c4, "nmk-i2c.4", NULL), 455 CLK(i2c4, "nmk-i2c.4", NULL),
455 CLK(spi3, "spi3", NULL), 456 CLK(spi3, "spi3", NULL),
456 CLK(msp1, "msp1", NULL), 457 CLK(msp1, "ux500-msp-i2s.1", NULL),
458 CLK(msp3, "ux500-msp-i2s.3", NULL),
457 459
458 /* Peripheral Cluster #2 */ 460 /* Peripheral Cluster #2 */
459 CLK(gpio1, "gpio.6", NULL), 461 CLK(gpio1, "gpio.6", NULL),
@@ -463,7 +465,7 @@ static struct clk_lookup u8500_clks[] = {
463 CLK(spi0, "spi0", NULL), 465 CLK(spi0, "spi0", NULL),
464 CLK(sdi3, "sdi3", NULL), 466 CLK(sdi3, "sdi3", NULL),
465 CLK(sdi1, "sdi1", NULL), 467 CLK(sdi1, "sdi1", NULL),
466 CLK(msp2, "msp2", NULL), 468 CLK(msp2, "ux500-msp-i2s.2", NULL),
467 CLK(sdi4, "sdi4", NULL), 469 CLK(sdi4, "sdi4", NULL),
468 CLK(pwl, "pwl", NULL), 470 CLK(pwl, "pwl", NULL),
469 CLK(spi1, "spi1", NULL), 471 CLK(spi1, "spi1", NULL),
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 76a7503a11a2..16169c4bf6ca 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -163,6 +163,7 @@ static void __init db8500_add_gpios(struct device *parent)
163 163
164 dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base), 164 dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
165 IRQ_DB8500_GPIO0, &pdata); 165 IRQ_DB8500_GPIO0, &pdata);
166 dbx500_add_pinctrl(parent, "pinctrl-db8500");
166} 167}
167 168
168static int usb_db8500_rx_dma_cfg[] = { 169static int usb_db8500_rx_dma_cfg[] = {
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 0982279f51f3..a29a0e3adcf9 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -29,6 +29,18 @@
29 29
30void __iomem *_PRCMU_BASE; 30void __iomem *_PRCMU_BASE;
31 31
32/*
33 * FIXME: Should we set up the GPIO domain here?
34 *
35 * The problem is that we cannot put the interrupt resources into the platform
36 * device until the irqdomain has been added. Right now, we set the GIC interrupt
37 * domain from init_irq(), then load the gpio driver from
38 * core_initcall(nmk_gpio_init) and add the platform devices from
39 * arch_initcall(customize_machine).
40 *
41 * This feels fragile because it depends on the gpio device getting probed
42 * _before_ any device uses the gpio interrupts.
43*/
32static const struct of_device_id ux500_dt_irq_match[] = { 44static const struct of_device_id ux500_dt_irq_match[] = {
33 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, 45 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
34 {}, 46 {},
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index f75bcb2ab13b..7cbccfd9e158 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -90,4 +90,16 @@ struct nmk_gpio_platform_data;
90void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num, 90void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
91 int irq, struct nmk_gpio_platform_data *pdata); 91 int irq, struct nmk_gpio_platform_data *pdata);
92 92
93static inline void
94dbx500_add_pinctrl(struct device *parent, const char *name)
95{
96 struct platform_device_info pdevinfo = {
97 .parent = parent,
98 .name = name,
99 .id = -1,
100 };
101
102 platform_device_register_full(&pdevinfo);
103}
104
93#endif 105#endif
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index 6fc7eb24d9a0..0b9677a95bbc 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -34,7 +34,6 @@ db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
34 return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0); 34 return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0);
35} 35}
36 36
37
38#define db8500_add_i2c0(parent, pdata) \ 37#define db8500_add_i2c0(parent, pdata) \
39 dbx500_add_i2c(parent, 0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata) 38 dbx500_add_i2c(parent, 0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata)
40#define db8500_add_i2c1(parent, pdata) \ 39#define db8500_add_i2c1(parent, pdata) \
@@ -46,15 +45,6 @@ db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
46#define db8500_add_i2c4(parent, pdata) \ 45#define db8500_add_i2c4(parent, pdata) \
47 dbx500_add_i2c(parent, 4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata) 46 dbx500_add_i2c(parent, 4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata)
48 47
49#define db8500_add_msp0_i2s(parent, pdata) \
50 dbx500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata)
51#define db8500_add_msp1_i2s(parent, pdata) \
52 dbx500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata)
53#define db8500_add_msp2_i2s(parent, pdata) \
54 dbx500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata)
55#define db8500_add_msp3_i2s(parent, pdata) \
56 dbx500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata)
57
58#define db8500_add_msp0_spi(parent, pdata) \ 48#define db8500_add_msp0_spi(parent, pdata) \
59 dbx500_add_msp_spi(parent, "msp0", U8500_MSP0_BASE, \ 49 dbx500_add_msp_spi(parent, "msp0", U8500_MSP0_BASE, \
60 IRQ_DB8500_MSP0, pdata) 50 IRQ_DB8500_MSP0, pdata)
diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h
new file mode 100644
index 000000000000..798be19129ef
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/msp.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#ifndef __MSP_H
9#define __MSP_H
10
11#include <plat/ste_dma40.h>
12
13enum msp_i2s_id {
14 MSP_I2S_0 = 0,
15 MSP_I2S_1,
16 MSP_I2S_2,
17 MSP_I2S_3,
18};
19
20/* Platform data structure for a MSP I2S-device */
21struct msp_i2s_platform_data {
22 enum msp_i2s_id id;
23 struct stedma40_chan_cfg *msp_i2s_dma_rx;
24 struct stedma40_chan_cfg *msp_i2s_dma_tx;
25 int (*msp_i2s_init) (void);
26 int (*msp_i2s_exit) (void);
27};
28
29#endif
diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h
index 8b1d1a7a679e..062c7acf4576 100644
--- a/arch/arm/mach-ux500/pins-db8500.h
+++ b/arch/arm/mach-ux500/pins-db8500.h
@@ -35,40 +35,40 @@
35 35
36#define GPIO4_GPIO PIN_CFG(4, GPIO) 36#define GPIO4_GPIO PIN_CFG(4, GPIO)
37#define GPIO4_U1_RXD PIN_CFG(4, ALT_A) 37#define GPIO4_U1_RXD PIN_CFG(4, ALT_A)
38#define GPIO4_I2C4_SCL PIN_CFG_INPUT(4, ALT_B, PULLUP) 38#define GPIO4_I2C4_SCL PIN_CFG(4, ALT_B)
39#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C) 39#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C)
40 40
41#define GPIO5_GPIO PIN_CFG(5, GPIO) 41#define GPIO5_GPIO PIN_CFG(5, GPIO)
42#define GPIO5_U1_TXD PIN_CFG(5, ALT_A) 42#define GPIO5_U1_TXD PIN_CFG(5, ALT_A)
43#define GPIO5_I2C4_SDA PIN_CFG_INPUT(5, ALT_B, PULLUP) 43#define GPIO5_I2C4_SDA PIN_CFG(5, ALT_B)
44#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C) 44#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C)
45 45
46#define GPIO6_GPIO PIN_CFG(6, GPIO) 46#define GPIO6_GPIO PIN_CFG(6, GPIO)
47#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A) 47#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A)
48#define GPIO6_I2C1_SCL PIN_CFG_INPUT(6, ALT_B, PULLUP) 48#define GPIO6_I2C1_SCL PIN_CFG(6, ALT_B)
49#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C) 49#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C)
50 50
51#define GPIO7_GPIO PIN_CFG(7, GPIO) 51#define GPIO7_GPIO PIN_CFG(7, GPIO)
52#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A) 52#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A)
53#define GPIO7_I2C1_SDA PIN_CFG_INPUT(7, ALT_B, PULLUP) 53#define GPIO7_I2C1_SDA PIN_CFG(7, ALT_B)
54#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C) 54#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C)
55 55
56#define GPIO8_GPIO PIN_CFG(8, GPIO) 56#define GPIO8_GPIO PIN_CFG(8, GPIO)
57#define GPIO8_IPI2C_SDA PIN_CFG_INPUT(8, ALT_A, PULLUP) 57#define GPIO8_IPI2C_SDA PIN_CFG(8, ALT_A)
58#define GPIO8_I2C2_SDA PIN_CFG_INPUT(8, ALT_B, PULLUP) 58#define GPIO8_I2C2_SDA PIN_CFG(8, ALT_B)
59 59
60#define GPIO9_GPIO PIN_CFG(9, GPIO) 60#define GPIO9_GPIO PIN_CFG(9, GPIO)
61#define GPIO9_IPI2C_SCL PIN_CFG_INPUT(9, ALT_A, PULLUP) 61#define GPIO9_IPI2C_SCL PIN_CFG(9, ALT_A)
62#define GPIO9_I2C2_SCL PIN_CFG_INPUT(9, ALT_B, PULLUP) 62#define GPIO9_I2C2_SCL PIN_CFG(9, ALT_B)
63 63
64#define GPIO10_GPIO PIN_CFG(10, GPIO) 64#define GPIO10_GPIO PIN_CFG(10, GPIO)
65#define GPIO10_IPI2C_SDA PIN_CFG_INPUT(10, ALT_A, PULLUP) 65#define GPIO10_IPI2C_SDA PIN_CFG(10, ALT_A)
66#define GPIO10_I2C2_SDA PIN_CFG_INPUT(10, ALT_B, PULLUP) 66#define GPIO10_I2C2_SDA PIN_CFG(10, ALT_B)
67#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C) 67#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C)
68 68
69#define GPIO11_GPIO PIN_CFG(11, GPIO) 69#define GPIO11_GPIO PIN_CFG(11, GPIO)
70#define GPIO11_IPI2C_SCL PIN_CFG_INPUT(11, ALT_A, PULLUP) 70#define GPIO11_IPI2C_SCL PIN_CFG(11, ALT_A)
71#define GPIO11_I2C2_SCL PIN_CFG_INPUT(11, ALT_B, PULLUP) 71#define GPIO11_I2C2_SCL PIN_CFG(11, ALT_B)
72#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C) 72#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C)
73 73
74#define GPIO12_GPIO PIN_CFG(12, GPIO) 74#define GPIO12_GPIO PIN_CFG(12, GPIO)
@@ -87,12 +87,12 @@
87 87
88#define GPIO16_GPIO PIN_CFG(16, GPIO) 88#define GPIO16_GPIO PIN_CFG(16, GPIO)
89#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A) 89#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A)
90#define GPIO16_I2C1_SCL PIN_CFG_INPUT(16, ALT_B, PULLUP) 90#define GPIO16_I2C1_SCL PIN_CFG(16, ALT_B)
91#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C) 91#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C)
92 92
93#define GPIO17_GPIO PIN_CFG(17, GPIO) 93#define GPIO17_GPIO PIN_CFG(17, GPIO)
94#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A) 94#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A)
95#define GPIO17_I2C1_SDA PIN_CFG_INPUT(17, ALT_B, PULLUP) 95#define GPIO17_I2C1_SDA PIN_CFG(17, ALT_B)
96#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) 96#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C)
97 97
98#define GPIO18_GPIO PIN_CFG(18, GPIO) 98#define GPIO18_GPIO PIN_CFG(18, GPIO)
@@ -434,10 +434,10 @@
434#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A) 434#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A)
435 435
436#define GPIO147_GPIO PIN_CFG(147, GPIO) 436#define GPIO147_GPIO PIN_CFG(147, GPIO)
437#define GPIO147_I2C0_SCL PIN_CFG_INPUT(147, ALT_A, PULLUP) 437#define GPIO147_I2C0_SCL PIN_CFG(147, ALT_A)
438 438
439#define GPIO148_GPIO PIN_CFG(148, GPIO) 439#define GPIO148_GPIO PIN_CFG(148, GPIO)
440#define GPIO148_I2C0_SDA PIN_CFG_INPUT(148, ALT_A, PULLUP) 440#define GPIO148_I2C0_SDA PIN_CFG(148, ALT_A)
441 441
442#define GPIO149_GPIO PIN_CFG(149, GPIO) 442#define GPIO149_GPIO PIN_CFG(149, GPIO)
443#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A) 443#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A)
@@ -459,82 +459,82 @@
459#define GPIO152_KP_O9 PIN_CFG(152, ALT_C) 459#define GPIO152_KP_O9 PIN_CFG(152, ALT_C)
460 460
461#define GPIO153_GPIO PIN_CFG(153, GPIO) 461#define GPIO153_GPIO PIN_CFG(153, GPIO)
462#define GPIO153_KP_I7 PIN_CFG_INPUT(153, ALT_A, PULLDOWN) 462#define GPIO153_KP_I7 PIN_CFG(153, ALT_A)
463#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B) 463#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B)
464#define GPIO153_U2_RXD PIN_CFG(153, ALT_C) 464#define GPIO153_U2_RXD PIN_CFG(153, ALT_C)
465 465
466#define GPIO154_GPIO PIN_CFG(154, GPIO) 466#define GPIO154_GPIO PIN_CFG(154, GPIO)
467#define GPIO154_KP_I6 PIN_CFG_INPUT(154, ALT_A, PULLDOWN) 467#define GPIO154_KP_I6 PIN_CFG(154, ALT_A)
468#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B) 468#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B)
469#define GPIO154_U2_TXD PIN_CFG(154, ALT_C) 469#define GPIO154_U2_TXD PIN_CFG(154, ALT_C)
470 470
471#define GPIO155_GPIO PIN_CFG(155, GPIO) 471#define GPIO155_GPIO PIN_CFG(155, GPIO)
472#define GPIO155_KP_I5 PIN_CFG_INPUT(155, ALT_A, PULLDOWN) 472#define GPIO155_KP_I5 PIN_CFG(155, ALT_A)
473#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B) 473#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B)
474#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C) 474#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C)
475 475
476#define GPIO156_GPIO PIN_CFG(156, GPIO) 476#define GPIO156_GPIO PIN_CFG(156, GPIO)
477#define GPIO156_KP_I4 PIN_CFG_INPUT(156, ALT_A, PULLDOWN) 477#define GPIO156_KP_I4 PIN_CFG(156, ALT_A)
478#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B) 478#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B)
479#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C) 479#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C)
480 480
481#define GPIO157_GPIO PIN_CFG(157, GPIO) 481#define GPIO157_GPIO PIN_CFG(157, GPIO)
482#define GPIO157_KP_O7 PIN_CFG_INPUT(157, ALT_A, PULLUP) 482#define GPIO157_KP_O7 PIN_CFG(157, ALT_A)
483#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B) 483#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B)
484#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C) 484#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C)
485 485
486#define GPIO158_GPIO PIN_CFG(158, GPIO) 486#define GPIO158_GPIO PIN_CFG(158, GPIO)
487#define GPIO158_KP_O6 PIN_CFG_INPUT(158, ALT_A, PULLUP) 487#define GPIO158_KP_O6 PIN_CFG(158, ALT_A)
488#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B) 488#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B)
489#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C) 489#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C)
490 490
491#define GPIO159_GPIO PIN_CFG(159, GPIO) 491#define GPIO159_GPIO PIN_CFG(159, GPIO)
492#define GPIO159_KP_O5 PIN_CFG_INPUT(159, ALT_A, PULLUP) 492#define GPIO159_KP_O5 PIN_CFG(159, ALT_A)
493#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B) 493#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B)
494#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C) 494#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C)
495 495
496#define GPIO160_GPIO PIN_CFG(160, GPIO) 496#define GPIO160_GPIO PIN_CFG(160, GPIO)
497#define GPIO160_KP_O4 PIN_CFG_INPUT(160, ALT_A, PULLUP) 497#define GPIO160_KP_O4 PIN_CFG(160, ALT_A)
498#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B) 498#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B)
499#define GPIO160_NONE PIN_CFG(160, ALT_C) 499#define GPIO160_NONE PIN_CFG(160, ALT_C)
500 500
501#define GPIO161_GPIO PIN_CFG(161, GPIO) 501#define GPIO161_GPIO PIN_CFG(161, GPIO)
502#define GPIO161_KP_I3 PIN_CFG_INPUT(161, ALT_A, PULLDOWN) 502#define GPIO161_KP_I3 PIN_CFG(161, ALT_A)
503#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B) 503#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B)
504#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C) 504#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C)
505 505
506#define GPIO162_GPIO PIN_CFG(162, GPIO) 506#define GPIO162_GPIO PIN_CFG(162, GPIO)
507#define GPIO162_KP_I2 PIN_CFG_INPUT(162, ALT_A, PULLDOWN) 507#define GPIO162_KP_I2 PIN_CFG(162, ALT_A)
508#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B) 508#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B)
509#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C) 509#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C)
510 510
511#define GPIO163_GPIO PIN_CFG(163, GPIO) 511#define GPIO163_GPIO PIN_CFG(163, GPIO)
512#define GPIO163_KP_I1 PIN_CFG_INPUT(163, ALT_A, PULLDOWN) 512#define GPIO163_KP_I1 PIN_CFG(163, ALT_A)
513#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B) 513#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B)
514#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C) 514#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C)
515 515
516#define GPIO164_GPIO PIN_CFG(164, GPIO) 516#define GPIO164_GPIO PIN_CFG(164, GPIO)
517#define GPIO164_KP_I0 PIN_CFG_INPUT(164, ALT_A, PULLUP) 517#define GPIO164_KP_I0 PIN_CFG(164, ALT_A)
518#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B) 518#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B)
519#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C) 519#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C)
520 520
521#define GPIO165_GPIO PIN_CFG(165, GPIO) 521#define GPIO165_GPIO PIN_CFG(165, GPIO)
522#define GPIO165_KP_O3 PIN_CFG_INPUT(165, ALT_A, PULLUP) 522#define GPIO165_KP_O3 PIN_CFG(165, ALT_A)
523#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B) 523#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B)
524#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C) 524#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C)
525 525
526#define GPIO166_GPIO PIN_CFG(166, GPIO) 526#define GPIO166_GPIO PIN_CFG(166, GPIO)
527#define GPIO166_KP_O2 PIN_CFG_INPUT(166, ALT_A, PULLUP) 527#define GPIO166_KP_O2 PIN_CFG(166, ALT_A)
528#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B) 528#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B)
529#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C) 529#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C)
530 530
531#define GPIO167_GPIO PIN_CFG(167, GPIO) 531#define GPIO167_GPIO PIN_CFG(167, GPIO)
532#define GPIO167_KP_O1 PIN_CFG_INPUT(167, ALT_A, PULLUP) 532#define GPIO167_KP_O1 PIN_CFG(167, ALT_A)
533#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B) 533#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B)
534#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C) 534#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C)
535 535
536#define GPIO168_GPIO PIN_CFG(168, GPIO) 536#define GPIO168_GPIO PIN_CFG(168, GPIO)
537#define GPIO168_KP_O0 PIN_CFG_INPUT(168, ALT_A, PULLUP) 537#define GPIO168_KP_O0 PIN_CFG(168, ALT_A)
538#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B) 538#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B)
539#define GPIO168_NONE PIN_CFG(168, ALT_C) 539#define GPIO168_NONE PIN_CFG(168, ALT_C)
540 540
@@ -637,7 +637,7 @@
637#define GPIO216_GPIO PIN_CFG(216, GPIO) 637#define GPIO216_GPIO PIN_CFG(216, GPIO)
638#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A) 638#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A)
639#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B) 639#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B)
640#define GPIO216_I2C3_SDA PIN_CFG_INPUT(216, ALT_C, PULLUP) 640#define GPIO216_I2C3_SDA PIN_CFG(216, ALT_C)
641#define GPIO216_SPI2_FRM PIN_CFG(216, ALT_C) 641#define GPIO216_SPI2_FRM PIN_CFG(216, ALT_C)
642 642
643#define GPIO217_GPIO PIN_CFG(217, GPIO) 643#define GPIO217_GPIO PIN_CFG(217, GPIO)
@@ -649,7 +649,7 @@
649#define GPIO218_GPIO PIN_CFG(218, GPIO) 649#define GPIO218_GPIO PIN_CFG(218, GPIO)
650#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A) 650#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A)
651#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B) 651#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B)
652#define GPIO218_I2C3_SCL PIN_CFG_INPUT(218, ALT_C, PULLUP) 652#define GPIO218_I2C3_SCL PIN_CFG(218, ALT_C)
653#define GPIO218_SPI2_RXD PIN_CFG(218, ALT_C) 653#define GPIO218_SPI2_RXD PIN_CFG(218, ALT_C)
654 654
655#define GPIO219_GPIO PIN_CFG(219, GPIO) 655#define GPIO219_GPIO PIN_CFG(219, GPIO)
@@ -698,12 +698,12 @@
698#define GPIO229_GPIO PIN_CFG(229, GPIO) 698#define GPIO229_GPIO PIN_CFG(229, GPIO)
699#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A) 699#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A)
700#define GPIO229_PWL PIN_CFG(229, ALT_B) 700#define GPIO229_PWL PIN_CFG(229, ALT_B)
701#define GPIO229_I2C3_SDA PIN_CFG_INPUT(229, ALT_C, PULLUP) 701#define GPIO229_I2C3_SDA PIN_CFG(229, ALT_C)
702 702
703#define GPIO230_GPIO PIN_CFG(230, GPIO) 703#define GPIO230_GPIO PIN_CFG(230, GPIO)
704#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A) 704#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A)
705#define GPIO230_PWL PIN_CFG(230, ALT_B) 705#define GPIO230_PWL PIN_CFG(230, ALT_B)
706#define GPIO230_I2C3_SCL PIN_CFG_INPUT(230, ALT_C, PULLUP) 706#define GPIO230_I2C3_SCL PIN_CFG(230, ALT_C)
707 707
708#define GPIO256_GPIO PIN_CFG(256, GPIO) 708#define GPIO256_GPIO PIN_CFG(256, GPIO)
709#define GPIO256_USB_NXT PIN_CFG(256, ALT_A) 709#define GPIO256_USB_NXT PIN_CFG(256, ALT_A)
diff --git a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
index 9605bf227df9..826de74bfdd1 100644
--- a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
+++ b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
@@ -29,6 +29,7 @@
29#define NMK_GPIO_SLPC 0x1c 29#define NMK_GPIO_SLPC 0x1c
30#define NMK_GPIO_AFSLA 0x20 30#define NMK_GPIO_AFSLA 0x20
31#define NMK_GPIO_AFSLB 0x24 31#define NMK_GPIO_AFSLB 0x24
32#define NMK_GPIO_LOWEMI 0x28
32 33
33#define NMK_GPIO_RIMSC 0x40 34#define NMK_GPIO_RIMSC 0x40
34#define NMK_GPIO_FIMSC 0x44 35#define NMK_GPIO_FIMSC 0x44
@@ -61,7 +62,14 @@ enum nmk_gpio_slpm {
61 62
62extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode); 63extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode);
63extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull); 64extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull);
65#ifdef CONFIG_PINCTRL_NOMADIK
64extern int nmk_gpio_set_mode(int gpio, int gpio_mode); 66extern int nmk_gpio_set_mode(int gpio, int gpio_mode);
67#else
68static inline int nmk_gpio_set_mode(int gpio, int gpio_mode)
69{
70 return -ENODEV;
71}
72#endif
65extern int nmk_gpio_get_mode(int gpio); 73extern int nmk_gpio_get_mode(int gpio);
66 74
67extern void nmk_gpio_wakeups_suspend(void); 75extern void nmk_gpio_wakeups_suspend(void);
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
index 22cb97d2d8ad..9c949c7c98a7 100644
--- a/arch/arm/plat-nomadik/include/plat/pincfg.h
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -24,6 +24,7 @@
24 * bit 16..18 - SLPM pull up/down state 24 * bit 16..18 - SLPM pull up/down state
25 * bit 19..20 - SLPM direction 25 * bit 19..20 - SLPM direction
26 * bit 21..22 - SLPM Value (if output) 26 * bit 21..22 - SLPM Value (if output)
27 * bit 23..25 - PDIS value (if input)
27 * 28 *
28 * to facilitate the definition, the following macros are provided 29 * to facilitate the definition, the following macros are provided
29 * 30 *
@@ -67,6 +68,10 @@ typedef unsigned long pin_cfg_t;
67/* These two replace the above in DB8500v2+ */ 68/* These two replace the above in DB8500v2+ */
68#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) 69#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
69#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) 70#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
71#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
72
73#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
74#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
70 75
71#define PIN_DIR_SHIFT 14 76#define PIN_DIR_SHIFT 14
72#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) 77#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
@@ -105,6 +110,33 @@ typedef unsigned long pin_cfg_t;
105#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) 110#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
106#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) 111#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
107 112
113#define PIN_SLPM_PDIS_SHIFT 23
114#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
115#define PIN_SLPM_PDIS(x) \
116 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
117#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
118#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
119#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
120
121#define PIN_LOWEMI_SHIFT 25
122#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
123#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
124#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
125#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
126
127#define PIN_GPIOMODE_SHIFT 26
128#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
129#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
130#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
131#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
132
133#define PIN_SLEEPMODE_SHIFT 27
134#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
135#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
136#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
137#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
138
139
108/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ 140/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
109#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) 141#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
110#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) 142#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 6c066fcb2979..387655b5ce05 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -13,6 +13,7 @@ config ARCH_SPEAR3XX
13 select ARM_VIC 13 select ARM_VIC
14 select CPU_ARM926T 14 select CPU_ARM926T
15 select USE_OF 15 select USE_OF
16 select PINCTRL
16 help 17 help
17 Supports for ARM's SPEAR3XX family 18 Supports for ARM's SPEAR3XX family
18 19
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 4af6258d0fee..7744802c83e7 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -5,4 +5,4 @@
5# Common support 5# Common support
6obj-y := clock.o restart.o time.o pl080.o 6obj-y := clock.o restart.o time.o pl080.o
7 7
8obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o 8obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o
diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
deleted file mode 100644
index 877f3adcf610..000000000000
--- a/arch/arm/plat-spear/include/plat/padmux.h
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/padmux.h
3 *
4 * SPEAr platform specific gpio pads muxing file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_PADMUX_H
15#define __PLAT_PADMUX_H
16
17#include <linux/types.h>
18
19/*
20 * struct pmx_reg: configuration structure for mode reg and mux reg
21 *
22 * offset: offset of mode reg
23 * mask: mask of mode reg
24 */
25struct pmx_reg {
26 u32 offset;
27 u32 mask;
28};
29
30/*
31 * struct pmx_dev_mode: configuration structure every group of modes of a device
32 *
33 * ids: all modes for this configuration
34 * mask: mask for supported mode
35 */
36struct pmx_dev_mode {
37 u32 ids;
38 u32 mask;
39};
40
41/*
42 * struct pmx_mode: mode definition structure
43 *
44 * name: mode name
45 * mask: mode mask
46 */
47struct pmx_mode {
48 char *name;
49 u32 id;
50 u32 mask;
51};
52
53/*
54 * struct pmx_dev: device definition structure
55 *
56 * name: device name
57 * modes: device configuration array for different modes supported
58 * mode_count: size of modes array
59 * is_active: is peripheral active/enabled
60 * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
61 */
62struct pmx_dev {
63 char *name;
64 struct pmx_dev_mode *modes;
65 u8 mode_count;
66 bool is_active;
67 bool enb_on_reset;
68};
69
70/*
71 * struct pmx_driver: driver definition structure
72 *
73 * mode: mode to be set
74 * devs: array of pointer to pmx devices
75 * devs_count: ARRAY_SIZE of devs
76 * base: base address of soc config registers
77 * mode_reg: structure of mode config register
78 * mux_reg: structure of device mux config register
79 */
80struct pmx_driver {
81 struct pmx_mode *mode;
82 struct pmx_dev **devs;
83 u8 devs_count;
84 u32 *base;
85 struct pmx_reg mode_reg;
86 struct pmx_reg mux_reg;
87};
88
89/* pmx functions */
90int pmx_register(struct pmx_driver *driver);
91
92#endif /* __PLAT_PADMUX_H */
diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
deleted file mode 100644
index 555eec6dc1cb..000000000000
--- a/arch/arm/plat-spear/padmux.c
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/padmux.c
3 *
4 * SPEAr platform specific gpio pads muxing source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <plat/padmux.h>
18
19/*
20 * struct pmx: pmx definition structure
21 *
22 * base: base address of configuration registers
23 * mode_reg: mode configurations
24 * mux_reg: muxing configurations
25 * active_mode: pointer to current active mode
26 */
27struct pmx {
28 u32 base;
29 struct pmx_reg mode_reg;
30 struct pmx_reg mux_reg;
31 struct pmx_mode *active_mode;
32};
33
34static struct pmx *pmx;
35
36/**
37 * pmx_mode_set - Enables an multiplexing mode
38 * @mode - pointer to pmx mode
39 *
40 * It will set mode of operation in hardware.
41 * Returns -ve on Err otherwise 0
42 */
43static int pmx_mode_set(struct pmx_mode *mode)
44{
45 u32 val;
46
47 if (!mode->name)
48 return -EFAULT;
49
50 pmx->active_mode = mode;
51
52 val = readl(pmx->base + pmx->mode_reg.offset);
53 val &= ~pmx->mode_reg.mask;
54 val |= mode->mask & pmx->mode_reg.mask;
55 writel(val, pmx->base + pmx->mode_reg.offset);
56
57 return 0;
58}
59
60/**
61 * pmx_devs_enable - Enables list of devices
62 * @devs - pointer to pmx device array
63 * @count - number of devices to enable
64 *
65 * It will enable pads for all required peripherals once and only once.
66 * If peripheral is not supported by current mode then request is rejected.
67 * Conflicts between peripherals are not handled and peripherals will be
68 * enabled in the order they are present in pmx_dev array.
69 * In case of conflicts last peripheral enabled will be present.
70 * Returns -ve on Err otherwise 0
71 */
72static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
73{
74 u32 val, i, mask;
75
76 if (!count)
77 return -EINVAL;
78
79 val = readl(pmx->base + pmx->mux_reg.offset);
80 for (i = 0; i < count; i++) {
81 u8 j = 0;
82
83 if (!devs[i]->name || !devs[i]->modes) {
84 printk(KERN_ERR "padmux: dev name or modes is null\n");
85 continue;
86 }
87 /* check if peripheral exists in active mode */
88 if (pmx->active_mode) {
89 bool found = false;
90 for (j = 0; j < devs[i]->mode_count; j++) {
91 if (devs[i]->modes[j].ids &
92 pmx->active_mode->id) {
93 found = true;
94 break;
95 }
96 }
97 if (found == false) {
98 printk(KERN_ERR "%s device not available in %s"\
99 "mode\n", devs[i]->name,
100 pmx->active_mode->name);
101 continue;
102 }
103 }
104
105 /* enable peripheral */
106 mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
107 if (devs[i]->enb_on_reset)
108 val &= ~mask;
109 else
110 val |= mask;
111
112 devs[i]->is_active = true;
113 }
114 writel(val, pmx->base + pmx->mux_reg.offset);
115 kfree(pmx);
116
117 /* this will ensure that multiplexing can't be changed now */
118 pmx = (struct pmx *)-1;
119
120 return 0;
121}
122
123/**
124 * pmx_register - registers a platform requesting pad mux feature
125 * @driver - pointer to driver structure containing driver specific parameters
126 *
127 * Also this must be called only once. This will allocate memory for pmx
128 * structure, will call pmx_mode_set, will call pmx_devs_enable.
129 * Returns -ve on Err otherwise 0
130 */
131int pmx_register(struct pmx_driver *driver)
132{
133 int ret = 0;
134
135 if (pmx)
136 return -EPERM;
137 if (!driver->base || !driver->devs)
138 return -EFAULT;
139
140 pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
141 if (!pmx)
142 return -ENOMEM;
143
144 pmx->base = (u32)driver->base;
145 pmx->mode_reg.offset = driver->mode_reg.offset;
146 pmx->mode_reg.mask = driver->mode_reg.mask;
147 pmx->mux_reg.offset = driver->mux_reg.offset;
148 pmx->mux_reg.mask = driver->mux_reg.mask;
149
150 /* choose mode to enable */
151 if (driver->mode) {
152 ret = pmx_mode_set(driver->mode);
153 if (ret)
154 goto pmx_fail;
155 }
156 ret = pmx_devs_enable(driver->devs, driver->devs_count);
157 if (ret)
158 goto pmx_fail;
159
160 return 0;
161
162pmx_fail:
163 return ret;
164}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 22:03:59 -0500