diff options
Diffstat (limited to 'arch/arm')
65 files changed, 2978 insertions, 177 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 18194acab493..0298b00fe241 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
@@ -186,6 +186,8 @@ machine-$(CONFIG_ARCH_VEXPRESS) := vexpress | |||
186 | machine-$(CONFIG_ARCH_VT8500) := vt8500 | 186 | machine-$(CONFIG_ARCH_VT8500) := vt8500 |
187 | machine-$(CONFIG_ARCH_W90X900) := w90x900 | 187 | machine-$(CONFIG_ARCH_W90X900) := w90x900 |
188 | machine-$(CONFIG_FOOTBRIDGE) := footbridge | 188 | machine-$(CONFIG_FOOTBRIDGE) := footbridge |
189 | machine-$(CONFIG_MACH_SPEAR1310) := spear13xx | ||
190 | machine-$(CONFIG_MACH_SPEAR1340) := spear13xx | ||
189 | machine-$(CONFIG_MACH_SPEAR300) := spear3xx | 191 | machine-$(CONFIG_MACH_SPEAR300) := spear3xx |
190 | machine-$(CONFIG_MACH_SPEAR310) := spear3xx | 192 | machine-$(CONFIG_MACH_SPEAR310) := spear3xx |
191 | machine-$(CONFIG_MACH_SPEAR320) := spear3xx | 193 | machine-$(CONFIG_MACH_SPEAR320) := spear3xx |
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 399d17b231d2..49945cc1bc7d 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts | |||
@@ -23,4 +23,52 @@ | |||
23 | chosen { | 23 | chosen { |
24 | bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200"; | 24 | bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200"; |
25 | }; | 25 | }; |
26 | |||
27 | i2c@12C60000 { | ||
28 | samsung,i2c-sda-delay = <100>; | ||
29 | samsung,i2c-max-bus-freq = <20000>; | ||
30 | gpios = <&gpb3 0 2 3 0>, | ||
31 | <&gpb3 1 2 3 0>; | ||
32 | |||
33 | eeprom@50 { | ||
34 | compatible = "samsung,s524ad0xd1"; | ||
35 | reg = <0x50>; | ||
36 | }; | ||
37 | }; | ||
38 | |||
39 | i2c@12C70000 { | ||
40 | samsung,i2c-sda-delay = <100>; | ||
41 | samsung,i2c-max-bus-freq = <20000>; | ||
42 | gpios = <&gpb3 2 2 3 0>, | ||
43 | <&gpb3 3 2 3 0>; | ||
44 | |||
45 | eeprom@51 { | ||
46 | compatible = "samsung,s524ad0xd1"; | ||
47 | reg = <0x51>; | ||
48 | }; | ||
49 | }; | ||
50 | |||
51 | i2c@12C80000 { | ||
52 | status = "disabled"; | ||
53 | }; | ||
54 | |||
55 | i2c@12C90000 { | ||
56 | status = "disabled"; | ||
57 | }; | ||
58 | |||
59 | i2c@12CA0000 { | ||
60 | status = "disabled"; | ||
61 | }; | ||
62 | |||
63 | i2c@12CB0000 { | ||
64 | status = "disabled"; | ||
65 | }; | ||
66 | |||
67 | i2c@12CC0000 { | ||
68 | status = "disabled"; | ||
69 | }; | ||
70 | |||
71 | i2c@12CD0000 { | ||
72 | status = "disabled"; | ||
73 | }; | ||
26 | }; | 74 | }; |
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index dfc433599436..5ca0cdb76413 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi | |||
@@ -23,11 +23,11 @@ | |||
23 | compatible = "samsung,exynos5250"; | 23 | compatible = "samsung,exynos5250"; |
24 | interrupt-parent = <&gic>; | 24 | interrupt-parent = <&gic>; |
25 | 25 | ||
26 | gic:interrupt-controller@10490000 { | 26 | gic:interrupt-controller@10481000 { |
27 | compatible = "arm,cortex-a9-gic"; | 27 | compatible = "arm,cortex-a9-gic"; |
28 | #interrupt-cells = <3>; | 28 | #interrupt-cells = <3>; |
29 | interrupt-controller; | 29 | interrupt-controller; |
30 | reg = <0x10490000 0x1000>, <0x10480000 0x100>; | 30 | reg = <0x10481000 0x1000>, <0x10482000 0x2000>; |
31 | }; | 31 | }; |
32 | 32 | ||
33 | watchdog { | 33 | watchdog { |
@@ -42,30 +42,6 @@ | |||
42 | interrupts = <0 43 0>, <0 44 0>; | 42 | interrupts = <0 43 0>, <0 44 0>; |
43 | }; | 43 | }; |
44 | 44 | ||
45 | sdhci@12200000 { | ||
46 | compatible = "samsung,exynos4210-sdhci"; | ||
47 | reg = <0x12200000 0x100>; | ||
48 | interrupts = <0 75 0>; | ||
49 | }; | ||
50 | |||
51 | sdhci@12210000 { | ||
52 | compatible = "samsung,exynos4210-sdhci"; | ||
53 | reg = <0x12210000 0x100>; | ||
54 | interrupts = <0 76 0>; | ||
55 | }; | ||
56 | |||
57 | sdhci@12220000 { | ||
58 | compatible = "samsung,exynos4210-sdhci"; | ||
59 | reg = <0x12220000 0x100>; | ||
60 | interrupts = <0 77 0>; | ||
61 | }; | ||
62 | |||
63 | sdhci@12230000 { | ||
64 | compatible = "samsung,exynos4210-sdhci"; | ||
65 | reg = <0x12230000 0x100>; | ||
66 | interrupts = <0 78 0>; | ||
67 | }; | ||
68 | |||
69 | serial@12C00000 { | 45 | serial@12C00000 { |
70 | compatible = "samsung,exynos4210-uart"; | 46 | compatible = "samsung,exynos4210-uart"; |
71 | reg = <0x12C00000 0x100>; | 47 | reg = <0x12C00000 0x100>; |
@@ -94,48 +70,64 @@ | |||
94 | compatible = "samsung,s3c2440-i2c"; | 70 | compatible = "samsung,s3c2440-i2c"; |
95 | reg = <0x12C60000 0x100>; | 71 | reg = <0x12C60000 0x100>; |
96 | interrupts = <0 56 0>; | 72 | interrupts = <0 56 0>; |
73 | #address-cells = <1>; | ||
74 | #size-cells = <0>; | ||
97 | }; | 75 | }; |
98 | 76 | ||
99 | i2c@12C70000 { | 77 | i2c@12C70000 { |
100 | compatible = "samsung,s3c2440-i2c"; | 78 | compatible = "samsung,s3c2440-i2c"; |
101 | reg = <0x12C70000 0x100>; | 79 | reg = <0x12C70000 0x100>; |
102 | interrupts = <0 57 0>; | 80 | interrupts = <0 57 0>; |
81 | #address-cells = <1>; | ||
82 | #size-cells = <0>; | ||
103 | }; | 83 | }; |
104 | 84 | ||
105 | i2c@12C80000 { | 85 | i2c@12C80000 { |
106 | compatible = "samsung,s3c2440-i2c"; | 86 | compatible = "samsung,s3c2440-i2c"; |
107 | reg = <0x12C80000 0x100>; | 87 | reg = <0x12C80000 0x100>; |
108 | interrupts = <0 58 0>; | 88 | interrupts = <0 58 0>; |
89 | #address-cells = <1>; | ||
90 | #size-cells = <0>; | ||
109 | }; | 91 | }; |
110 | 92 | ||
111 | i2c@12C90000 { | 93 | i2c@12C90000 { |
112 | compatible = "samsung,s3c2440-i2c"; | 94 | compatible = "samsung,s3c2440-i2c"; |
113 | reg = <0x12C90000 0x100>; | 95 | reg = <0x12C90000 0x100>; |
114 | interrupts = <0 59 0>; | 96 | interrupts = <0 59 0>; |
97 | #address-cells = <1>; | ||
98 | #size-cells = <0>; | ||
115 | }; | 99 | }; |
116 | 100 | ||
117 | i2c@12CA0000 { | 101 | i2c@12CA0000 { |
118 | compatible = "samsung,s3c2440-i2c"; | 102 | compatible = "samsung,s3c2440-i2c"; |
119 | reg = <0x12CA0000 0x100>; | 103 | reg = <0x12CA0000 0x100>; |
120 | interrupts = <0 60 0>; | 104 | interrupts = <0 60 0>; |
105 | #address-cells = <1>; | ||
106 | #size-cells = <0>; | ||
121 | }; | 107 | }; |
122 | 108 | ||
123 | i2c@12CB0000 { | 109 | i2c@12CB0000 { |
124 | compatible = "samsung,s3c2440-i2c"; | 110 | compatible = "samsung,s3c2440-i2c"; |
125 | reg = <0x12CB0000 0x100>; | 111 | reg = <0x12CB0000 0x100>; |
126 | interrupts = <0 61 0>; | 112 | interrupts = <0 61 0>; |
113 | #address-cells = <1>; | ||
114 | #size-cells = <0>; | ||
127 | }; | 115 | }; |
128 | 116 | ||
129 | i2c@12CC0000 { | 117 | i2c@12CC0000 { |
130 | compatible = "samsung,s3c2440-i2c"; | 118 | compatible = "samsung,s3c2440-i2c"; |
131 | reg = <0x12CC0000 0x100>; | 119 | reg = <0x12CC0000 0x100>; |
132 | interrupts = <0 62 0>; | 120 | interrupts = <0 62 0>; |
121 | #address-cells = <1>; | ||
122 | #size-cells = <0>; | ||
133 | }; | 123 | }; |
134 | 124 | ||
135 | i2c@12CD0000 { | 125 | i2c@12CD0000 { |
136 | compatible = "samsung,s3c2440-i2c"; | 126 | compatible = "samsung,s3c2440-i2c"; |
137 | reg = <0x12CD0000 0x100>; | 127 | reg = <0x12CD0000 0x100>; |
138 | interrupts = <0 63 0>; | 128 | interrupts = <0 63 0>; |
129 | #address-cells = <1>; | ||
130 | #size-cells = <0>; | ||
139 | }; | 131 | }; |
140 | 132 | ||
141 | amba { | 133 | amba { |
@@ -157,13 +149,13 @@ | |||
157 | interrupts = <0 35 0>; | 149 | interrupts = <0 35 0>; |
158 | }; | 150 | }; |
159 | 151 | ||
160 | mdma0: pdma@10800000 { | 152 | mdma0: mdma@10800000 { |
161 | compatible = "arm,pl330", "arm,primecell"; | 153 | compatible = "arm,pl330", "arm,primecell"; |
162 | reg = <0x10800000 0x1000>; | 154 | reg = <0x10800000 0x1000>; |
163 | interrupts = <0 33 0>; | 155 | interrupts = <0 33 0>; |
164 | }; | 156 | }; |
165 | 157 | ||
166 | mdma1: pdma@11C10000 { | 158 | mdma1: mdma@11C10000 { |
167 | compatible = "arm,pl330", "arm,primecell"; | 159 | compatible = "arm,pl330", "arm,primecell"; |
168 | reg = <0x11C10000 0x1000>; | 160 | reg = <0x11C10000 0x1000>; |
169 | interrupts = <0 124 0>; | 161 | interrupts = <0 124 0>; |
@@ -242,6 +234,12 @@ | |||
242 | #gpio-cells = <4>; | 234 | #gpio-cells = <4>; |
243 | }; | 235 | }; |
244 | 236 | ||
237 | gpc4: gpio-controller@114002E0 { | ||
238 | compatible = "samsung,exynos4-gpio"; | ||
239 | reg = <0x114002E0 0x20>; | ||
240 | #gpio-cells = <4>; | ||
241 | }; | ||
242 | |||
245 | gpd0: gpio-controller@11400160 { | 243 | gpd0: gpio-controller@11400160 { |
246 | compatible = "samsung,exynos4-gpio"; | 244 | compatible = "samsung,exynos4-gpio"; |
247 | reg = <0x11400160 0x20>; | 245 | reg = <0x11400160 0x20>; |
@@ -388,19 +386,19 @@ | |||
388 | 386 | ||
389 | gpv2: gpio-controller@10D10040 { | 387 | gpv2: gpio-controller@10D10040 { |
390 | compatible = "samsung,exynos4-gpio"; | 388 | compatible = "samsung,exynos4-gpio"; |
391 | reg = <0x10D10040 0x20>; | 389 | reg = <0x10D10060 0x20>; |
392 | #gpio-cells = <4>; | 390 | #gpio-cells = <4>; |
393 | }; | 391 | }; |
394 | 392 | ||
395 | gpv3: gpio-controller@10D10060 { | 393 | gpv3: gpio-controller@10D10060 { |
396 | compatible = "samsung,exynos4-gpio"; | 394 | compatible = "samsung,exynos4-gpio"; |
397 | reg = <0x10D10060 0x20>; | 395 | reg = <0x10D10080 0x20>; |
398 | #gpio-cells = <4>; | 396 | #gpio-cells = <4>; |
399 | }; | 397 | }; |
400 | 398 | ||
401 | gpv4: gpio-controller@10D10080 { | 399 | gpv4: gpio-controller@10D10080 { |
402 | compatible = "samsung,exynos4-gpio"; | 400 | compatible = "samsung,exynos4-gpio"; |
403 | reg = <0x10D10080 0x20>; | 401 | reg = <0x10D100C0 0x20>; |
404 | #gpio-cells = <4>; | 402 | #gpio-cells = <4>; |
405 | }; | 403 | }; |
406 | 404 | ||
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts new file mode 100644 index 000000000000..8314e4171884 --- /dev/null +++ b/arch/arm/boot/dts/spear1310-evb.dts | |||
@@ -0,0 +1,292 @@ | |||
1 | /* | ||
2 | * DTS file for SPEAr1310 Evaluation Baord | ||
3 | * | ||
4 | * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> | ||
5 | * | ||
6 | * The code contained herein is licensed under the GNU General Public | ||
7 | * License. You may obtain a copy of the GNU General Public License | ||
8 | * Version 2 or later at the following locations: | ||
9 | * | ||
10 | * http://www.opensource.org/licenses/gpl-license.html | ||
11 | * http://www.gnu.org/copyleft/gpl.html | ||
12 | */ | ||
13 | |||
14 | /dts-v1/; | ||
15 | /include/ "spear1310.dtsi" | ||
16 | |||
17 | / { | ||
18 | model = "ST SPEAr1310 Evaluation Board"; | ||
19 | compatible = "st,spear1310-evb", "st,spear1310"; | ||
20 | #address-cells = <1>; | ||
21 | #size-cells = <1>; | ||
22 | |||
23 | memory { | ||
24 | reg = <0 0x40000000>; | ||
25 | }; | ||
26 | |||
27 | ahb { | ||
28 | pinmux@e0700000 { | ||
29 | pinctrl-names = "default"; | ||
30 | pinctrl-0 = <&state_default>; | ||
31 | |||
32 | state_default: pinmux { | ||
33 | i2c0-pmx { | ||
34 | st,pins = "i2c0_grp"; | ||
35 | st,function = "i2c0"; | ||
36 | }; | ||
37 | i2s1 { | ||
38 | st,pins = "i2s1_grp"; | ||
39 | st,function = "i2s1"; | ||
40 | }; | ||
41 | gpio { | ||
42 | st,pins = "arm_gpio_grp"; | ||
43 | st,function = "arm_gpio"; | ||
44 | }; | ||
45 | eth { | ||
46 | st,pins = "gmii_grp"; | ||
47 | st,function = "gmii"; | ||
48 | }; | ||
49 | ssp0 { | ||
50 | st,pins = "ssp0_grp"; | ||
51 | st,function = "ssp0"; | ||
52 | }; | ||
53 | kbd { | ||
54 | st,pins = "keyboard_6x6_grp"; | ||
55 | st,function = "keyboard"; | ||
56 | }; | ||
57 | sdhci { | ||
58 | st,pins = "sdhci_grp"; | ||
59 | st,function = "sdhci"; | ||
60 | }; | ||
61 | smi-pmx { | ||
62 | st,pins = "smi_2_chips_grp"; | ||
63 | st,function = "smi"; | ||
64 | }; | ||
65 | uart0 { | ||
66 | st,pins = "uart0_grp"; | ||
67 | st,function = "uart0"; | ||
68 | }; | ||
69 | rs485 { | ||
70 | st,pins = "rs485_0_1_tdm_0_1_grp"; | ||
71 | st,function = "rs485_0_1_tdm_0_1"; | ||
72 | }; | ||
73 | i2c1_2 { | ||
74 | st,pins = "i2c_1_2_grp"; | ||
75 | st,function = "i2c_1_2"; | ||
76 | }; | ||
77 | pci { | ||
78 | st,pins = "pcie0_grp","pcie1_grp", | ||
79 | "pcie2_grp"; | ||
80 | st,function = "pci"; | ||
81 | }; | ||
82 | smii { | ||
83 | st,pins = "smii_0_1_2_grp"; | ||
84 | st,function = "smii_0_1_2"; | ||
85 | }; | ||
86 | nand { | ||
87 | st,pins = "nand_8bit_grp", | ||
88 | "nand_16bit_grp"; | ||
89 | st,function = "nand"; | ||
90 | }; | ||
91 | }; | ||
92 | }; | ||
93 | |||
94 | ahci@b1000000 { | ||
95 | status = "okay"; | ||
96 | }; | ||
97 | |||
98 | cf@b2800000 { | ||
99 | status = "okay"; | ||
100 | }; | ||
101 | |||
102 | dma@ea800000 { | ||
103 | status = "okay"; | ||
104 | }; | ||
105 | |||
106 | dma@eb000000 { | ||
107 | status = "okay"; | ||
108 | }; | ||
109 | |||
110 | fsmc: flash@b0000000 { | ||
111 | status = "okay"; | ||
112 | }; | ||
113 | |||
114 | gmac0: eth@e2000000 { | ||
115 | status = "okay"; | ||
116 | }; | ||
117 | |||
118 | sdhci@b3000000 { | ||
119 | status = "okay"; | ||
120 | }; | ||
121 | |||
122 | smi: flash@ea000000 { | ||
123 | status = "okay"; | ||
124 | clock-rate=<50000000>; | ||
125 | |||
126 | flash@e6000000 { | ||
127 | #address-cells = <1>; | ||
128 | #size-cells = <1>; | ||
129 | reg = <0xe6000000 0x800000>; | ||
130 | st,smi-fast-mode; | ||
131 | |||
132 | partition@0 { | ||
133 | label = "xloader"; | ||
134 | reg = <0x0 0x10000>; | ||
135 | }; | ||
136 | partition@10000 { | ||
137 | label = "u-boot"; | ||
138 | reg = <0x10000 0x40000>; | ||
139 | }; | ||
140 | partition@50000 { | ||
141 | label = "linux"; | ||
142 | reg = <0x50000 0x2c0000>; | ||
143 | }; | ||
144 | partition@310000 { | ||
145 | label = "rootfs"; | ||
146 | reg = <0x310000 0x4f0000>; | ||
147 | }; | ||
148 | }; | ||
149 | }; | ||
150 | |||
151 | spi0: spi@e0100000 { | ||
152 | status = "okay"; | ||
153 | }; | ||
154 | |||
155 | ehci@e4800000 { | ||
156 | status = "okay"; | ||
157 | }; | ||
158 | |||
159 | ehci@e5800000 { | ||
160 | status = "okay"; | ||
161 | }; | ||
162 | |||
163 | ohci@e4000000 { | ||
164 | status = "okay"; | ||
165 | }; | ||
166 | |||
167 | ohci@e5000000 { | ||
168 | status = "okay"; | ||
169 | }; | ||
170 | |||
171 | apb { | ||
172 | adc@e0080000 { | ||
173 | status = "okay"; | ||
174 | }; | ||
175 | |||
176 | gpio0: gpio@e0600000 { | ||
177 | status = "okay"; | ||
178 | }; | ||
179 | |||
180 | gpio1: gpio@e0680000 { | ||
181 | status = "okay"; | ||
182 | }; | ||
183 | |||
184 | i2c0: i2c@e0280000 { | ||
185 | status = "okay"; | ||
186 | }; | ||
187 | |||
188 | i2c1: i2c@5cd00000 { | ||
189 | status = "okay"; | ||
190 | }; | ||
191 | |||
192 | kbd@e0300000 { | ||
193 | linux,keymap = < 0x00000001 | ||
194 | 0x00010002 | ||
195 | 0x00020003 | ||
196 | 0x00030004 | ||
197 | 0x00040005 | ||
198 | 0x00050006 | ||
199 | 0x00060007 | ||
200 | 0x00070008 | ||
201 | 0x00080009 | ||
202 | 0x0100000a | ||
203 | 0x0101000c | ||
204 | 0x0102000d | ||
205 | 0x0103000e | ||
206 | 0x0104000f | ||
207 | 0x01050010 | ||
208 | 0x01060011 | ||
209 | 0x01070012 | ||
210 | 0x01080013 | ||
211 | 0x02000014 | ||
212 | 0x02010015 | ||
213 | 0x02020016 | ||
214 | 0x02030017 | ||
215 | 0x02040018 | ||
216 | 0x02050019 | ||
217 | 0x0206001a | ||
218 | 0x0207001b | ||
219 | 0x0208001c | ||
220 | 0x0300001d | ||
221 | 0x0301001e | ||
222 | 0x0302001f | ||
223 | 0x03030020 | ||
224 | 0x03040021 | ||
225 | 0x03050022 | ||
226 | 0x03060023 | ||
227 | 0x03070024 | ||
228 | 0x03080025 | ||
229 | 0x04000026 | ||
230 | 0x04010027 | ||
231 | 0x04020028 | ||
232 | 0x04030029 | ||
233 | 0x0404002a | ||
234 | 0x0405002b | ||
235 | 0x0406002c | ||
236 | 0x0407002d | ||
237 | 0x0408002e | ||
238 | 0x0500002f | ||
239 | 0x05010030 | ||
240 | 0x05020031 | ||
241 | 0x05030032 | ||
242 | 0x05040033 | ||
243 | 0x05050034 | ||
244 | 0x05060035 | ||
245 | 0x05070036 | ||
246 | 0x05080037 | ||
247 | 0x06000038 | ||
248 | 0x06010039 | ||
249 | 0x0602003a | ||
250 | 0x0603003b | ||
251 | 0x0604003c | ||
252 | 0x0605003d | ||
253 | 0x0606003e | ||
254 | 0x0607003f | ||
255 | 0x06080040 | ||
256 | 0x07000041 | ||
257 | 0x07010042 | ||
258 | 0x07020043 | ||
259 | 0x07030044 | ||
260 | 0x07040045 | ||
261 | 0x07050046 | ||
262 | 0x07060047 | ||
263 | 0x07070048 | ||
264 | 0x07080049 | ||
265 | 0x0800004a | ||
266 | 0x0801004b | ||
267 | 0x0802004c | ||
268 | 0x0803004d | ||
269 | 0x0804004e | ||
270 | 0x0805004f | ||
271 | 0x08060050 | ||
272 | 0x08070051 | ||
273 | 0x08080052 >; | ||
274 | autorepeat; | ||
275 | st,mode = <0>; | ||
276 | status = "okay"; | ||
277 | }; | ||
278 | |||
279 | rtc@e0580000 { | ||
280 | status = "okay"; | ||
281 | }; | ||
282 | |||
283 | serial@e0000000 { | ||
284 | status = "okay"; | ||
285 | }; | ||
286 | |||
287 | wdt@ec800620 { | ||
288 | status = "okay"; | ||
289 | }; | ||
290 | }; | ||
291 | }; | ||
292 | }; | ||
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi new file mode 100644 index 000000000000..9e61da404d57 --- /dev/null +++ b/arch/arm/boot/dts/spear1310.dtsi | |||
@@ -0,0 +1,184 @@ | |||
1 | /* | ||
2 | * DTS file for all SPEAr1310 SoCs | ||
3 | * | ||
4 | * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> | ||
5 | * | ||
6 | * The code contained herein is licensed under the GNU General Public | ||
7 | * License. You may obtain a copy of the GNU General Public License | ||
8 | * Version 2 or later at the following locations: | ||
9 | * | ||
10 | * http://www.opensource.org/licenses/gpl-license.html | ||
11 | * http://www.gnu.org/copyleft/gpl.html | ||
12 | */ | ||
13 | |||
14 | /include/ "spear13xx.dtsi" | ||
15 | |||
16 | / { | ||
17 | compatible = "st,spear1310"; | ||
18 | |||
19 | ahb { | ||
20 | ahci@b1000000 { | ||
21 | compatible = "snps,spear-ahci"; | ||
22 | reg = <0xb1000000 0x10000>; | ||
23 | interrupts = <0 68 0x4>; | ||
24 | status = "disabled"; | ||
25 | }; | ||
26 | |||
27 | ahci@b1800000 { | ||
28 | compatible = "snps,spear-ahci"; | ||
29 | reg = <0xb1800000 0x10000>; | ||
30 | interrupts = <0 69 0x4>; | ||
31 | status = "disabled"; | ||
32 | }; | ||
33 | |||
34 | ahci@b4000000 { | ||
35 | compatible = "snps,spear-ahci"; | ||
36 | reg = <0xb4000000 0x10000>; | ||
37 | interrupts = <0 70 0x4>; | ||
38 | status = "disabled"; | ||
39 | }; | ||
40 | |||
41 | gmac1: eth@5c400000 { | ||
42 | compatible = "st,spear600-gmac"; | ||
43 | reg = <0x5c400000 0x8000>; | ||
44 | interrupts = <0 95 0x4>; | ||
45 | interrupt-names = "macirq"; | ||
46 | status = "disabled"; | ||
47 | }; | ||
48 | |||
49 | gmac2: eth@5c500000 { | ||
50 | compatible = "st,spear600-gmac"; | ||
51 | reg = <0x5c500000 0x8000>; | ||
52 | interrupts = <0 96 0x4>; | ||
53 | interrupt-names = "macirq"; | ||
54 | status = "disabled"; | ||
55 | }; | ||
56 | |||
57 | gmac3: eth@5c600000 { | ||
58 | compatible = "st,spear600-gmac"; | ||
59 | reg = <0x5c600000 0x8000>; | ||
60 | interrupts = <0 97 0x4>; | ||
61 | interrupt-names = "macirq"; | ||
62 | status = "disabled"; | ||
63 | }; | ||
64 | |||
65 | gmac4: eth@5c700000 { | ||
66 | compatible = "st,spear600-gmac"; | ||
67 | reg = <0x5c700000 0x8000>; | ||
68 | interrupts = <0 98 0x4>; | ||
69 | interrupt-names = "macirq"; | ||
70 | status = "disabled"; | ||
71 | }; | ||
72 | |||
73 | spi1: spi@5d400000 { | ||
74 | compatible = "arm,pl022", "arm,primecell"; | ||
75 | reg = <0x5d400000 0x1000>; | ||
76 | interrupts = <0 99 0x4>; | ||
77 | status = "disabled"; | ||
78 | }; | ||
79 | |||
80 | apb { | ||
81 | i2c1: i2c@5cd00000 { | ||
82 | #address-cells = <1>; | ||
83 | #size-cells = <0>; | ||
84 | compatible = "snps,designware-i2c"; | ||
85 | reg = <0x5cd00000 0x1000>; | ||
86 | interrupts = <0 87 0x4>; | ||
87 | status = "disabled"; | ||
88 | }; | ||
89 | |||
90 | i2c2: i2c@5ce00000 { | ||
91 | #address-cells = <1>; | ||
92 | #size-cells = <0>; | ||
93 | compatible = "snps,designware-i2c"; | ||
94 | reg = <0x5ce00000 0x1000>; | ||
95 | interrupts = <0 88 0x4>; | ||
96 | status = "disabled"; | ||
97 | }; | ||
98 | |||
99 | i2c3: i2c@5cf00000 { | ||
100 | #address-cells = <1>; | ||
101 | #size-cells = <0>; | ||
102 | compatible = "snps,designware-i2c"; | ||
103 | reg = <0x5cf00000 0x1000>; | ||
104 | interrupts = <0 89 0x4>; | ||
105 | status = "disabled"; | ||
106 | }; | ||
107 | |||
108 | i2c4: i2c@5d000000 { | ||
109 | #address-cells = <1>; | ||
110 | #size-cells = <0>; | ||
111 | compatible = "snps,designware-i2c"; | ||
112 | reg = <0x5d000000 0x1000>; | ||
113 | interrupts = <0 90 0x4>; | ||
114 | status = "disabled"; | ||
115 | }; | ||
116 | |||
117 | i2c5: i2c@5d100000 { | ||
118 | #address-cells = <1>; | ||
119 | #size-cells = <0>; | ||
120 | compatible = "snps,designware-i2c"; | ||
121 | reg = <0x5d100000 0x1000>; | ||
122 | interrupts = <0 91 0x4>; | ||
123 | status = "disabled"; | ||
124 | }; | ||
125 | |||
126 | i2c6: i2c@5d200000 { | ||
127 | #address-cells = <1>; | ||
128 | #size-cells = <0>; | ||
129 | compatible = "snps,designware-i2c"; | ||
130 | reg = <0x5d200000 0x1000>; | ||
131 | interrupts = <0 92 0x4>; | ||
132 | status = "disabled"; | ||
133 | }; | ||
134 | |||
135 | i2c7: i2c@5d300000 { | ||
136 | #address-cells = <1>; | ||
137 | #size-cells = <0>; | ||
138 | compatible = "snps,designware-i2c"; | ||
139 | reg = <0x5d300000 0x1000>; | ||
140 | interrupts = <0 93 0x4>; | ||
141 | status = "disabled"; | ||
142 | }; | ||
143 | |||
144 | serial@5c800000 { | ||
145 | compatible = "arm,pl011", "arm,primecell"; | ||
146 | reg = <0x5c800000 0x1000>; | ||
147 | interrupts = <0 82 0x4>; | ||
148 | status = "disabled"; | ||
149 | }; | ||
150 | |||
151 | serial@5c900000 { | ||
152 | compatible = "arm,pl011", "arm,primecell"; | ||
153 | reg = <0x5c900000 0x1000>; | ||
154 | interrupts = <0 83 0x4>; | ||
155 | status = "disabled"; | ||
156 | }; | ||
157 | |||
158 | serial@5ca00000 { | ||
159 | compatible = "arm,pl011", "arm,primecell"; | ||
160 | reg = <0x5ca00000 0x1000>; | ||
161 | interrupts = <0 84 0x4>; | ||
162 | status = "disabled"; | ||
163 | }; | ||
164 | |||
165 | serial@5cb00000 { | ||
166 | compatible = "arm,pl011", "arm,primecell"; | ||
167 | reg = <0x5cb00000 0x1000>; | ||
168 | interrupts = <0 85 0x4>; | ||
169 | status = "disabled"; | ||
170 | }; | ||
171 | |||
172 | serial@5cc00000 { | ||
173 | compatible = "arm,pl011", "arm,primecell"; | ||
174 | reg = <0x5cc00000 0x1000>; | ||
175 | interrupts = <0 86 0x4>; | ||
176 | status = "disabled"; | ||
177 | }; | ||
178 | |||
179 | thermal@e07008c4 { | ||
180 | st,thermal-flags = <0x7000>; | ||
181 | }; | ||
182 | }; | ||
183 | }; | ||
184 | }; | ||
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts new file mode 100644 index 000000000000..0d8472e5ab9f --- /dev/null +++ b/arch/arm/boot/dts/spear1340-evb.dts | |||
@@ -0,0 +1,308 @@ | |||
1 | /* | ||
2 | * DTS file for SPEAr1340 Evaluation Baord | ||
3 | * | ||
4 | * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> | ||
5 | * | ||
6 | * The code contained herein is licensed under the GNU General Public | ||
7 | * License. You may obtain a copy of the GNU General Public License | ||
8 | * Version 2 or later at the following locations: | ||
9 | * | ||
10 | * http://www.opensource.org/licenses/gpl-license.html | ||
11 | * http://www.gnu.org/copyleft/gpl.html | ||
12 | */ | ||
13 | |||
14 | /dts-v1/; | ||
15 | /include/ "spear1340.dtsi" | ||
16 | |||
17 | / { | ||
18 | model = "ST SPEAr1340 Evaluation Board"; | ||
19 | compatible = "st,spear1340-evb", "st,spear1340"; | ||
20 | #address-cells = <1>; | ||
21 | #size-cells = <1>; | ||
22 | |||
23 | memory { | ||
24 | reg = <0 0x40000000>; | ||
25 | }; | ||
26 | |||
27 | ahb { | ||
28 | pinmux@e0700000 { | ||
29 | pinctrl-names = "default"; | ||
30 | pinctrl-0 = <&state_default>; | ||
31 | |||
32 | state_default: pinmux { | ||
33 | pads_as_gpio { | ||
34 | st,pins = "pads_as_gpio_grp"; | ||
35 | st,function = "pads_as_gpio"; | ||
36 | }; | ||
37 | fsmc { | ||
38 | st,pins = "fsmc_8bit_grp"; | ||
39 | st,function = "fsmc"; | ||
40 | }; | ||
41 | kbd { | ||
42 | st,pins = "keyboard_row_col_grp", | ||
43 | "keyboard_col5_grp"; | ||
44 | st,function = "keyboard"; | ||
45 | }; | ||
46 | uart0 { | ||
47 | st,pins = "uart0_grp", "uart0_enh_grp"; | ||
48 | st,function = "uart0"; | ||
49 | }; | ||
50 | i2c0-pmx { | ||
51 | st,pins = "i2c0_grp"; | ||
52 | st,function = "i2c0"; | ||
53 | }; | ||
54 | i2c1-pmx { | ||
55 | st,pins = "i2c1_grp"; | ||
56 | st,function = "i2c1"; | ||
57 | }; | ||
58 | spdif-in { | ||
59 | st,pins = "spdif_in_grp"; | ||
60 | st,function = "spdif_in"; | ||
61 | }; | ||
62 | spdif-out { | ||
63 | st,pins = "spdif_out_grp"; | ||
64 | st,function = "spdif_out"; | ||
65 | }; | ||
66 | ssp0 { | ||
67 | st,pins = "ssp0_grp", "ssp0_cs1_grp", | ||
68 | "ssp0_cs3_grp"; | ||
69 | st,function = "ssp0"; | ||
70 | }; | ||
71 | pwm { | ||
72 | st,pins = "pwm2_grp", "pwm3_grp"; | ||
73 | st,function = "pwm"; | ||
74 | }; | ||
75 | smi-pmx { | ||
76 | st,pins = "smi_grp"; | ||
77 | st,function = "smi"; | ||
78 | }; | ||
79 | i2s { | ||
80 | st,pins = "i2s_in_grp", "i2s_out_grp"; | ||
81 | st,function = "i2s"; | ||
82 | }; | ||
83 | gmac { | ||
84 | st,pins = "gmii_grp", "rgmii_grp"; | ||
85 | st,function = "gmac"; | ||
86 | }; | ||
87 | cam3 { | ||
88 | st,pins = "cam3_grp"; | ||
89 | st,function = "cam3"; | ||
90 | }; | ||
91 | cec0 { | ||
92 | st,pins = "cec0_grp"; | ||
93 | st,function = "cec0"; | ||
94 | }; | ||
95 | cec1 { | ||
96 | st,pins = "cec1_grp"; | ||
97 | st,function = "cec1"; | ||
98 | }; | ||
99 | sdhci { | ||
100 | st,pins = "sdhci_grp"; | ||
101 | st,function = "sdhci"; | ||
102 | }; | ||
103 | clcd { | ||
104 | st,pins = "clcd_grp"; | ||
105 | st,function = "clcd"; | ||
106 | }; | ||
107 | sata { | ||
108 | st,pins = "sata_grp"; | ||
109 | st,function = "sata"; | ||
110 | }; | ||
111 | }; | ||
112 | }; | ||
113 | |||
114 | dma@ea800000 { | ||
115 | status = "okay"; | ||
116 | }; | ||
117 | |||
118 | dma@eb000000 { | ||
119 | status = "okay"; | ||
120 | }; | ||
121 | |||
122 | fsmc: flash@b0000000 { | ||
123 | status = "okay"; | ||
124 | }; | ||
125 | |||
126 | gmac0: eth@e2000000 { | ||
127 | status = "okay"; | ||
128 | }; | ||
129 | |||
130 | sdhci@b3000000 { | ||
131 | status = "okay"; | ||
132 | }; | ||
133 | |||
134 | smi: flash@ea000000 { | ||
135 | status = "okay"; | ||
136 | clock-rate=<50000000>; | ||
137 | |||
138 | flash@e6000000 { | ||
139 | #address-cells = <1>; | ||
140 | #size-cells = <1>; | ||
141 | reg = <0xe6000000 0x800000>; | ||
142 | st,smi-fast-mode; | ||
143 | |||
144 | partition@0 { | ||
145 | label = "xloader"; | ||
146 | reg = <0x0 0x10000>; | ||
147 | }; | ||
148 | partition@10000 { | ||
149 | label = "u-boot"; | ||
150 | reg = <0x10000 0x40000>; | ||
151 | }; | ||
152 | partition@50000 { | ||
153 | label = "linux"; | ||
154 | reg = <0x50000 0x2c0000>; | ||
155 | }; | ||
156 | partition@310000 { | ||
157 | label = "rootfs"; | ||
158 | reg = <0x310000 0x4f0000>; | ||
159 | }; | ||
160 | }; | ||
161 | }; | ||
162 | |||
163 | spi0: spi@e0100000 { | ||
164 | status = "okay"; | ||
165 | }; | ||
166 | |||
167 | ehci@e4800000 { | ||
168 | status = "okay"; | ||
169 | }; | ||
170 | |||
171 | ehci@e5800000 { | ||
172 | status = "okay"; | ||
173 | }; | ||
174 | |||
175 | ohci@e4000000 { | ||
176 | status = "okay"; | ||
177 | }; | ||
178 | |||
179 | ohci@e5000000 { | ||
180 | status = "okay"; | ||
181 | }; | ||
182 | |||
183 | apb { | ||
184 | adc@e0080000 { | ||
185 | status = "okay"; | ||
186 | }; | ||
187 | |||
188 | gpio0: gpio@e0600000 { | ||
189 | status = "okay"; | ||
190 | }; | ||
191 | |||
192 | gpio1: gpio@e0680000 { | ||
193 | status = "okay"; | ||
194 | }; | ||
195 | |||
196 | i2c0: i2c@e0280000 { | ||
197 | status = "okay"; | ||
198 | }; | ||
199 | |||
200 | i2c1: i2c@b4000000 { | ||
201 | status = "okay"; | ||
202 | }; | ||
203 | |||
204 | kbd@e0300000 { | ||
205 | linux,keymap = < 0x00000001 | ||
206 | 0x00010002 | ||
207 | 0x00020003 | ||
208 | 0x00030004 | ||
209 | 0x00040005 | ||
210 | 0x00050006 | ||
211 | 0x00060007 | ||
212 | 0x00070008 | ||
213 | 0x00080009 | ||
214 | 0x0100000a | ||
215 | 0x0101000c | ||
216 | 0x0102000d | ||
217 | 0x0103000e | ||
218 | 0x0104000f | ||
219 | 0x01050010 | ||
220 | 0x01060011 | ||
221 | 0x01070012 | ||
222 | 0x01080013 | ||
223 | 0x02000014 | ||
224 | 0x02010015 | ||
225 | 0x02020016 | ||
226 | 0x02030017 | ||
227 | 0x02040018 | ||
228 | 0x02050019 | ||
229 | 0x0206001a | ||
230 | 0x0207001b | ||
231 | 0x0208001c | ||
232 | 0x0300001d | ||
233 | 0x0301001e | ||
234 | 0x0302001f | ||
235 | 0x03030020 | ||
236 | 0x03040021 | ||
237 | 0x03050022 | ||
238 | 0x03060023 | ||
239 | 0x03070024 | ||
240 | 0x03080025 | ||
241 | 0x04000026 | ||
242 | 0x04010027 | ||
243 | 0x04020028 | ||
244 | 0x04030029 | ||
245 | 0x0404002a | ||
246 | 0x0405002b | ||
247 | 0x0406002c | ||
248 | 0x0407002d | ||
249 | 0x0408002e | ||
250 | 0x0500002f | ||
251 | 0x05010030 | ||
252 | 0x05020031 | ||
253 | 0x05030032 | ||
254 | 0x05040033 | ||
255 | 0x05050034 | ||
256 | 0x05060035 | ||
257 | 0x05070036 | ||
258 | 0x05080037 | ||
259 | 0x06000038 | ||
260 | 0x06010039 | ||
261 | 0x0602003a | ||
262 | 0x0603003b | ||
263 | 0x0604003c | ||
264 | 0x0605003d | ||
265 | 0x0606003e | ||
266 | 0x0607003f | ||
267 | 0x06080040 | ||
268 | 0x07000041 | ||
269 | 0x07010042 | ||
270 | 0x07020043 | ||
271 | 0x07030044 | ||
272 | 0x07040045 | ||
273 | 0x07050046 | ||
274 | 0x07060047 | ||
275 | 0x07070048 | ||
276 | 0x07080049 | ||
277 | 0x0800004a | ||
278 | 0x0801004b | ||
279 | 0x0802004c | ||
280 | 0x0803004d | ||
281 | 0x0804004e | ||
282 | 0x0805004f | ||
283 | 0x08060050 | ||
284 | 0x08070051 | ||
285 | 0x08080052 >; | ||
286 | autorepeat; | ||
287 | st,mode = <0>; | ||
288 | status = "okay"; | ||
289 | }; | ||
290 | |||
291 | rtc@e0580000 { | ||
292 | status = "okay"; | ||
293 | }; | ||
294 | |||
295 | serial@e0000000 { | ||
296 | status = "okay"; | ||
297 | }; | ||
298 | |||
299 | serial@b4100000 { | ||
300 | status = "okay"; | ||
301 | }; | ||
302 | |||
303 | wdt@ec800620 { | ||
304 | status = "okay"; | ||
305 | }; | ||
306 | }; | ||
307 | }; | ||
308 | }; | ||
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi new file mode 100644 index 000000000000..a26fc47a55e8 --- /dev/null +++ b/arch/arm/boot/dts/spear1340.dtsi | |||
@@ -0,0 +1,56 @@ | |||
1 | /* | ||
2 | * DTS file for all SPEAr1340 SoCs | ||
3 | * | ||
4 | * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> | ||
5 | * | ||
6 | * The code contained herein is licensed under the GNU General Public | ||
7 | * License. You may obtain a copy of the GNU General Public License | ||
8 | * Version 2 or later at the following locations: | ||
9 | * | ||
10 | * http://www.opensource.org/licenses/gpl-license.html | ||
11 | * http://www.gnu.org/copyleft/gpl.html | ||
12 | */ | ||
13 | |||
14 | /include/ "spear13xx.dtsi" | ||
15 | |||
16 | / { | ||
17 | compatible = "st,spear1340"; | ||
18 | |||
19 | ahb { | ||
20 | ahci@b1000000 { | ||
21 | compatible = "snps,spear-ahci"; | ||
22 | reg = <0xb1000000 0x10000>; | ||
23 | interrupts = <0 72 0x4>; | ||
24 | status = "disabled"; | ||
25 | }; | ||
26 | |||
27 | spi1: spi@5d400000 { | ||
28 | compatible = "arm,pl022", "arm,primecell"; | ||
29 | reg = <0x5d400000 0x1000>; | ||
30 | interrupts = <0 99 0x4>; | ||
31 | status = "disabled"; | ||
32 | }; | ||
33 | |||
34 | apb { | ||
35 | i2c1: i2c@b4000000 { | ||
36 | #address-cells = <1>; | ||
37 | #size-cells = <0>; | ||
38 | compatible = "snps,designware-i2c"; | ||
39 | reg = <0xb4000000 0x1000>; | ||
40 | interrupts = <0 104 0x4>; | ||
41 | status = "disabled"; | ||
42 | }; | ||
43 | |||
44 | serial@b4100000 { | ||
45 | compatible = "arm,pl011", "arm,primecell"; | ||
46 | reg = <0xb4100000 0x1000>; | ||
47 | interrupts = <0 105 0x4>; | ||
48 | status = "disabled"; | ||
49 | }; | ||
50 | |||
51 | thermal@e07008c4 { | ||
52 | st,thermal-flags = <0x2a00>; | ||
53 | }; | ||
54 | }; | ||
55 | }; | ||
56 | }; | ||
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi new file mode 100644 index 000000000000..1f8e1e1481df --- /dev/null +++ b/arch/arm/boot/dts/spear13xx.dtsi | |||
@@ -0,0 +1,262 @@ | |||
1 | /* | ||
2 | * DTS file for all SPEAr13xx SoCs | ||
3 | * | ||
4 | * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> | ||
5 | * | ||
6 | * The code contained herein is licensed under the GNU General Public | ||
7 | * License. You may obtain a copy of the GNU General Public License | ||
8 | * Version 2 or later at the following locations: | ||
9 | * | ||
10 | * http://www.opensource.org/licenses/gpl-license.html | ||
11 | * http://www.gnu.org/copyleft/gpl.html | ||
12 | */ | ||
13 | |||
14 | /include/ "skeleton.dtsi" | ||
15 | |||
16 | / { | ||
17 | interrupt-parent = <&gic>; | ||
18 | |||
19 | cpus { | ||
20 | #address-cells = <1>; | ||
21 | #size-cells = <0>; | ||
22 | |||
23 | cpu@0 { | ||
24 | compatible = "arm,cortex-a9"; | ||
25 | reg = <0>; | ||
26 | next-level-cache = <&L2>; | ||
27 | }; | ||
28 | |||
29 | cpu@1 { | ||
30 | compatible = "arm,cortex-a9"; | ||
31 | reg = <1>; | ||
32 | next-level-cache = <&L2>; | ||
33 | }; | ||
34 | }; | ||
35 | |||
36 | gic: interrupt-controller@ec801000 { | ||
37 | compatible = "arm,cortex-a9-gic"; | ||
38 | interrupt-controller; | ||
39 | #interrupt-cells = <3>; | ||
40 | reg = < 0xec801000 0x1000 >, | ||
41 | < 0xec800100 0x0100 >; | ||
42 | }; | ||
43 | |||
44 | pmu { | ||
45 | compatible = "arm,cortex-a9-pmu"; | ||
46 | interrupts = <0 8 0x04 | ||
47 | 0 9 0x04>; | ||
48 | }; | ||
49 | |||
50 | L2: l2-cache { | ||
51 | compatible = "arm,pl310-cache"; | ||
52 | reg = <0xed000000 0x1000>; | ||
53 | cache-unified; | ||
54 | cache-level = <2>; | ||
55 | }; | ||
56 | |||
57 | memory { | ||
58 | name = "memory"; | ||
59 | device_type = "memory"; | ||
60 | reg = <0 0x40000000>; | ||
61 | }; | ||
62 | |||
63 | chosen { | ||
64 | bootargs = "console=ttyAMA0,115200"; | ||
65 | }; | ||
66 | |||
67 | ahb { | ||
68 | #address-cells = <1>; | ||
69 | #size-cells = <1>; | ||
70 | compatible = "simple-bus"; | ||
71 | ranges = <0x50000000 0x50000000 0x10000000 | ||
72 | 0xb0000000 0xb0000000 0x10000000 | ||
73 | 0xe0000000 0xe0000000 0x10000000>; | ||
74 | |||
75 | sdhci@b3000000 { | ||
76 | compatible = "st,sdhci-spear"; | ||
77 | reg = <0xb3000000 0x100>; | ||
78 | interrupts = <0 28 0x4>; | ||
79 | status = "disabled"; | ||
80 | }; | ||
81 | |||
82 | cf@b2800000 { | ||
83 | compatible = "arasan,cf-spear1340"; | ||
84 | reg = <0xb2800000 0x100>; | ||
85 | interrupts = <0 29 0x4>; | ||
86 | status = "disabled"; | ||
87 | }; | ||
88 | |||
89 | dma@ea800000 { | ||
90 | compatible = "snps,dma-spear1340"; | ||
91 | reg = <0xea800000 0x1000>; | ||
92 | interrupts = <0 19 0x4>; | ||
93 | status = "disabled"; | ||
94 | }; | ||
95 | |||
96 | dma@eb000000 { | ||
97 | compatible = "snps,dma-spear1340"; | ||
98 | reg = <0xeb000000 0x1000>; | ||
99 | interrupts = <0 59 0x4>; | ||
100 | status = "disabled"; | ||
101 | }; | ||
102 | |||
103 | fsmc: flash@b0000000 { | ||
104 | compatible = "st,spear600-fsmc-nand"; | ||
105 | #address-cells = <1>; | ||
106 | #size-cells = <1>; | ||
107 | reg = <0xb0000000 0x1000 /* FSMC Register */ | ||
108 | 0xb0800000 0x0010>; /* NAND Base */ | ||
109 | reg-names = "fsmc_regs", "nand_data"; | ||
110 | interrupts = <0 20 0x4 | ||
111 | 0 21 0x4 | ||
112 | 0 22 0x4 | ||
113 | 0 23 0x4>; | ||
114 | st,ale-off = <0x20000>; | ||
115 | st,cle-off = <0x10000>; | ||
116 | status = "disabled"; | ||
117 | }; | ||
118 | |||
119 | gmac0: eth@e2000000 { | ||
120 | compatible = "st,spear600-gmac"; | ||
121 | reg = <0xe2000000 0x8000>; | ||
122 | interrupts = <0 23 0x4 | ||
123 | 0 24 0x4>; | ||
124 | interrupt-names = "macirq", "eth_wake_irq"; | ||
125 | status = "disabled"; | ||
126 | }; | ||
127 | |||
128 | smi: flash@ea000000 { | ||
129 | compatible = "st,spear600-smi"; | ||
130 | #address-cells = <1>; | ||
131 | #size-cells = <1>; | ||
132 | reg = <0xea000000 0x1000>; | ||
133 | interrupts = <0 30 0x4>; | ||
134 | status = "disabled"; | ||
135 | }; | ||
136 | |||
137 | spi0: spi@e0100000 { | ||
138 | compatible = "arm,pl022", "arm,primecell"; | ||
139 | reg = <0xe0100000 0x1000>; | ||
140 | interrupts = <0 31 0x4>; | ||
141 | status = "disabled"; | ||
142 | }; | ||
143 | |||
144 | ehci@e4800000 { | ||
145 | compatible = "st,spear600-ehci", "usb-ehci"; | ||
146 | reg = <0xe4800000 0x1000>; | ||
147 | interrupts = <0 64 0x4>; | ||
148 | status = "disabled"; | ||
149 | }; | ||
150 | |||
151 | ehci@e5800000 { | ||
152 | compatible = "st,spear600-ehci", "usb-ehci"; | ||
153 | reg = <0xe5800000 0x1000>; | ||
154 | interrupts = <0 66 0x4>; | ||
155 | status = "disabled"; | ||
156 | }; | ||
157 | |||
158 | ohci@e4000000 { | ||
159 | compatible = "st,spear600-ohci", "usb-ohci"; | ||
160 | reg = <0xe4000000 0x1000>; | ||
161 | interrupts = <0 65 0x4>; | ||
162 | status = "disabled"; | ||
163 | }; | ||
164 | |||
165 | ohci@e5000000 { | ||
166 | compatible = "st,spear600-ohci", "usb-ohci"; | ||
167 | reg = <0xe5000000 0x1000>; | ||
168 | interrupts = <0 67 0x4>; | ||
169 | status = "disabled"; | ||
170 | }; | ||
171 | |||
172 | apb { | ||
173 | #address-cells = <1>; | ||
174 | #size-cells = <1>; | ||
175 | compatible = "simple-bus"; | ||
176 | ranges = <0x50000000 0x50000000 0x10000000 | ||
177 | 0xb0000000 0xb0000000 0x10000000 | ||
178 | 0xe0000000 0xe0000000 0x10000000>; | ||
179 | |||
180 | gpio0: gpio@e0600000 { | ||
181 | compatible = "arm,pl061", "arm,primecell"; | ||
182 | reg = <0xe0600000 0x1000>; | ||
183 | interrupts = <0 24 0x4>; | ||
184 | gpio-controller; | ||
185 | #gpio-cells = <2>; | ||
186 | interrupt-controller; | ||
187 | #interrupt-cells = <2>; | ||
188 | status = "disabled"; | ||
189 | }; | ||
190 | |||
191 | gpio1: gpio@e0680000 { | ||
192 | compatible = "arm,pl061", "arm,primecell"; | ||
193 | reg = <0xe0680000 0x1000>; | ||
194 | interrupts = <0 25 0x4>; | ||
195 | gpio-controller; | ||
196 | #gpio-cells = <2>; | ||
197 | interrupt-controller; | ||
198 | #interrupt-cells = <2>; | ||
199 | status = "disabled"; | ||
200 | }; | ||
201 | |||
202 | kbd@e0300000 { | ||
203 | compatible = "st,spear300-kbd"; | ||
204 | reg = <0xe0300000 0x1000>; | ||
205 | status = "disabled"; | ||
206 | }; | ||
207 | |||
208 | i2c0: i2c@e0280000 { | ||
209 | #address-cells = <1>; | ||
210 | #size-cells = <0>; | ||
211 | compatible = "snps,designware-i2c"; | ||
212 | reg = <0xe0280000 0x1000>; | ||
213 | interrupts = <0 41 0x4>; | ||
214 | status = "disabled"; | ||
215 | }; | ||
216 | |||
217 | rtc@e0580000 { | ||
218 | compatible = "st,spear-rtc"; | ||
219 | reg = <0xe0580000 0x1000>; | ||
220 | interrupts = <0 36 0x4>; | ||
221 | status = "disabled"; | ||
222 | }; | ||
223 | |||
224 | serial@e0000000 { | ||
225 | compatible = "arm,pl011", "arm,primecell"; | ||
226 | reg = <0xe0000000 0x1000>; | ||
227 | interrupts = <0 36 0x4>; | ||
228 | status = "disabled"; | ||
229 | }; | ||
230 | |||
231 | adc@e0080000 { | ||
232 | compatible = "st,spear600-adc"; | ||
233 | reg = <0xe0080000 0x1000>; | ||
234 | interrupts = <0 44 0x4>; | ||
235 | status = "disabled"; | ||
236 | }; | ||
237 | |||
238 | timer@e0380000 { | ||
239 | compatible = "st,spear-timer"; | ||
240 | reg = <0xe0380000 0x400>; | ||
241 | interrupts = <0 37 0x4>; | ||
242 | }; | ||
243 | |||
244 | timer@ec800600 { | ||
245 | compatible = "arm,cortex-a9-twd-timer"; | ||
246 | reg = <0xec800600 0x20>; | ||
247 | interrupts = <1 13 0x301>; | ||
248 | }; | ||
249 | |||
250 | wdt@ec800620 { | ||
251 | compatible = "arm,cortex-a9-twd-wdt"; | ||
252 | reg = <0xec800620 0x20>; | ||
253 | status = "disabled"; | ||
254 | }; | ||
255 | |||
256 | thermal@e07008c4 { | ||
257 | compatible = "st,thermal-spear1340"; | ||
258 | reg = <0xe07008c4 0x4>; | ||
259 | }; | ||
260 | }; | ||
261 | }; | ||
262 | }; | ||
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig new file mode 100644 index 000000000000..1fdb82694ca2 --- /dev/null +++ b/arch/arm/configs/spear13xx_defconfig | |||
@@ -0,0 +1,95 @@ | |||
1 | CONFIG_EXPERIMENTAL=y | ||
2 | CONFIG_SYSVIPC=y | ||
3 | CONFIG_BSD_PROCESS_ACCT=y | ||
4 | CONFIG_BLK_DEV_INITRD=y | ||
5 | CONFIG_MODULES=y | ||
6 | CONFIG_MODULE_UNLOAD=y | ||
7 | CONFIG_MODVERSIONS=y | ||
8 | CONFIG_PARTITION_ADVANCED=y | ||
9 | CONFIG_PLAT_SPEAR=y | ||
10 | CONFIG_ARCH_SPEAR13XX=y | ||
11 | CONFIG_MACH_SPEAR1310=y | ||
12 | CONFIG_MACH_SPEAR1340=y | ||
13 | # CONFIG_SWP_EMULATE is not set | ||
14 | CONFIG_SMP=y | ||
15 | # CONFIG_SMP_ON_UP is not set | ||
16 | # CONFIG_ARM_CPU_TOPOLOGY is not set | ||
17 | CONFIG_ARM_APPENDED_DTB=y | ||
18 | CONFIG_ARM_ATAG_DTB_COMPAT=y | ||
19 | CONFIG_BINFMT_MISC=y | ||
20 | CONFIG_NET=y | ||
21 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
22 | CONFIG_MTD=y | ||
23 | CONFIG_MTD_OF_PARTS=y | ||
24 | CONFIG_MTD_CHAR=y | ||
25 | CONFIG_MTD_BLOCK=y | ||
26 | CONFIG_MTD_NAND=y | ||
27 | CONFIG_MTD_NAND_FSMC=y | ||
28 | CONFIG_BLK_DEV_RAM=y | ||
29 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
30 | CONFIG_ATA=y | ||
31 | # CONFIG_SATA_PMP is not set | ||
32 | CONFIG_SATA_AHCI_PLATFORM=y | ||
33 | CONFIG_PATA_ARASAN_CF=y | ||
34 | CONFIG_NETDEVICES=y | ||
35 | # CONFIG_NET_VENDOR_BROADCOM is not set | ||
36 | # CONFIG_NET_VENDOR_CIRRUS is not set | ||
37 | # CONFIG_NET_VENDOR_FARADAY is not set | ||
38 | # CONFIG_NET_VENDOR_INTEL is not set | ||
39 | # CONFIG_NET_VENDOR_MICREL is not set | ||
40 | # CONFIG_NET_VENDOR_NATSEMI is not set | ||
41 | # CONFIG_NET_VENDOR_SEEQ is not set | ||
42 | # CONFIG_NET_VENDOR_SMSC is not set | ||
43 | CONFIG_STMMAC_ETH=y | ||
44 | # CONFIG_WLAN is not set | ||
45 | CONFIG_INPUT_FF_MEMLESS=y | ||
46 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
47 | # CONFIG_KEYBOARD_ATKBD is not set | ||
48 | CONFIG_KEYBOARD_SPEAR=y | ||
49 | # CONFIG_INPUT_MOUSE is not set | ||
50 | # CONFIG_LEGACY_PTYS is not set | ||
51 | CONFIG_SERIAL_AMBA_PL011=y | ||
52 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y | ||
53 | # CONFIG_HW_RANDOM is not set | ||
54 | CONFIG_RAW_DRIVER=y | ||
55 | CONFIG_MAX_RAW_DEVS=8192 | ||
56 | CONFIG_I2C=y | ||
57 | CONFIG_I2C_DESIGNWARE_PLATFORM=y | ||
58 | CONFIG_SPI=y | ||
59 | CONFIG_SPI_PL022=y | ||
60 | CONFIG_GPIO_SYSFS=y | ||
61 | CONFIG_GPIO_PL061=y | ||
62 | # CONFIG_HWMON is not set | ||
63 | CONFIG_WATCHDOG=y | ||
64 | CONFIG_MPCORE_WATCHDOG=y | ||
65 | # CONFIG_HID_SUPPORT is not set | ||
66 | CONFIG_USB=y | ||
67 | # CONFIG_USB_DEVICE_CLASS is not set | ||
68 | CONFIG_USB_EHCI_HCD=y | ||
69 | CONFIG_USB_OHCI_HCD=y | ||
70 | CONFIG_MMC=y | ||
71 | CONFIG_MMC_SDHCI=y | ||
72 | CONFIG_MMC_SDHCI_SPEAR=y | ||
73 | CONFIG_RTC_CLASS=y | ||
74 | CONFIG_DMADEVICES=y | ||
75 | CONFIG_DW_DMAC=y | ||
76 | CONFIG_DMATEST=m | ||
77 | CONFIG_EXT2_FS=y | ||
78 | CONFIG_EXT2_FS_XATTR=y | ||
79 | CONFIG_EXT2_FS_SECURITY=y | ||
80 | CONFIG_EXT3_FS=y | ||
81 | CONFIG_EXT3_FS_SECURITY=y | ||
82 | CONFIG_AUTOFS4_FS=m | ||
83 | CONFIG_MSDOS_FS=m | ||
84 | CONFIG_VFAT_FS=m | ||
85 | CONFIG_FAT_DEFAULT_IOCHARSET="ascii" | ||
86 | CONFIG_TMPFS=y | ||
87 | CONFIG_JFFS2_FS=y | ||
88 | CONFIG_NLS_DEFAULT="utf8" | ||
89 | CONFIG_NLS_CODEPAGE_437=y | ||
90 | CONFIG_NLS_ASCII=m | ||
91 | CONFIG_MAGIC_SYSRQ=y | ||
92 | CONFIG_DEBUG_FS=y | ||
93 | CONFIG_DEBUG_KERNEL=y | ||
94 | CONFIG_DEBUG_SPINLOCK=y | ||
95 | CONFIG_DEBUG_INFO=y | ||
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index e3cfd5fd7dd5..43ebe9094411 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig | |||
@@ -61,6 +61,7 @@ config SOC_EXYNOS5250 | |||
61 | bool "SAMSUNG EXYNOS5250" | 61 | bool "SAMSUNG EXYNOS5250" |
62 | default y | 62 | default y |
63 | depends on ARCH_EXYNOS5 | 63 | depends on ARCH_EXYNOS5 |
64 | select SAMSUNG_DMADEV | ||
64 | help | 65 | help |
65 | Enable EXYNOS5250 SoC support | 66 | Enable EXYNOS5250 SoC support |
66 | 67 | ||
@@ -70,7 +71,7 @@ config EXYNOS4_MCT | |||
70 | help | 71 | help |
71 | Use MCT (Multi Core Timer) as kernel timers | 72 | Use MCT (Multi Core Timer) as kernel timers |
72 | 73 | ||
73 | config EXYNOS4_DEV_DMA | 74 | config EXYNOS_DEV_DMA |
74 | bool | 75 | bool |
75 | help | 76 | help |
76 | Compile in amba device definitions for DMA controller | 77 | Compile in amba device definitions for DMA controller |
@@ -80,6 +81,11 @@ config EXYNOS4_DEV_AHCI | |||
80 | help | 81 | help |
81 | Compile in platform device definitions for AHCI | 82 | Compile in platform device definitions for AHCI |
82 | 83 | ||
84 | config EXYNOS_DEV_DRM | ||
85 | bool | ||
86 | help | ||
87 | Compile in platform device definitions for core DRM device | ||
88 | |||
83 | config EXYNOS4_SETUP_FIMD0 | 89 | config EXYNOS4_SETUP_FIMD0 |
84 | bool | 90 | bool |
85 | help | 91 | help |
@@ -161,7 +167,7 @@ config EXYNOS4_SETUP_USB_PHY | |||
161 | help | 167 | help |
162 | Common setup code for USB PHY controller | 168 | Common setup code for USB PHY controller |
163 | 169 | ||
164 | config EXYNOS4_SETUP_SPI | 170 | config EXYNOS_SETUP_SPI |
165 | bool | 171 | bool |
166 | help | 172 | help |
167 | Common setup code for SPI GPIO configurations. | 173 | Common setup code for SPI GPIO configurations. |
@@ -224,7 +230,7 @@ config MACH_ARMLEX4210 | |||
224 | select S3C_DEV_HSMMC2 | 230 | select S3C_DEV_HSMMC2 |
225 | select S3C_DEV_HSMMC3 | 231 | select S3C_DEV_HSMMC3 |
226 | select EXYNOS4_DEV_AHCI | 232 | select EXYNOS4_DEV_AHCI |
227 | select EXYNOS4_DEV_DMA | 233 | select EXYNOS_DEV_DMA |
228 | select EXYNOS4_SETUP_SDHCI | 234 | select EXYNOS4_SETUP_SDHCI |
229 | help | 235 | help |
230 | Machine support for Samsung ARMLEX4210 based on EXYNOS4210 | 236 | Machine support for Samsung ARMLEX4210 based on EXYNOS4210 |
@@ -362,7 +368,7 @@ config MACH_SMDK4212 | |||
362 | select SAMSUNG_DEV_KEYPAD | 368 | select SAMSUNG_DEV_KEYPAD |
363 | select SAMSUNG_DEV_PWM | 369 | select SAMSUNG_DEV_PWM |
364 | select EXYNOS_DEV_SYSMMU | 370 | select EXYNOS_DEV_SYSMMU |
365 | select EXYNOS4_DEV_DMA | 371 | select EXYNOS_DEV_DMA |
366 | select EXYNOS4_SETUP_I2C1 | 372 | select EXYNOS4_SETUP_I2C1 |
367 | select EXYNOS4_SETUP_I2C3 | 373 | select EXYNOS4_SETUP_I2C3 |
368 | select EXYNOS4_SETUP_I2C7 | 374 | select EXYNOS4_SETUP_I2C7 |
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 272625231c73..440a637c76f1 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile | |||
@@ -50,10 +50,11 @@ obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o | |||
50 | obj-y += dev-uart.o | 50 | obj-y += dev-uart.o |
51 | obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o | 51 | obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o |
52 | obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o | 52 | obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o |
53 | obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o | ||
54 | obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o | 53 | obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o |
55 | obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o | 54 | obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o |
56 | obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o | 55 | obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o |
56 | obj-$(CONFIG_EXYNOS_DEV_DRM) += dev-drm.o | ||
57 | obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o | ||
57 | 58 | ||
58 | obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o | 59 | obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o |
59 | obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o | 60 | obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o |
@@ -68,4 +69,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o | |||
68 | obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o | 69 | obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o |
69 | obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o | 70 | obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o |
70 | obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o | 71 | obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o |
71 | obj-$(CONFIG_EXYNOS4_SETUP_SPI) += setup-spi.o | 72 | obj-$(CONFIG_EXYNOS_SETUP_SPI) += setup-spi.o |
diff --git a/arch/arm/mach-exynos/Makefile.boot b/arch/arm/mach-exynos/Makefile.boot index b9862e22bf10..31bd181b0514 100644 --- a/arch/arm/mach-exynos/Makefile.boot +++ b/arch/arm/mach-exynos/Makefile.boot | |||
@@ -1,2 +1,5 @@ | |||
1 | zreladdr-y += 0x40008000 | 1 | zreladdr-y += 0x40008000 |
2 | params_phys-y := 0x40000100 | 2 | params_phys-y := 0x40000100 |
3 | |||
4 | dtb-$(CONFIG_MACH_EXYNOS4_DT) += exynos4210-origen.dtb exynos4210-smdkv310.dtb | ||
5 | dtb-$(CONFIG_MACH_EXYNOS5_DT) += exynos5250-smdk5250.dtb | ||
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c index 98823120570e..da397d21bbcf 100644 --- a/arch/arm/mach-exynos/clock-exynos4212.c +++ b/arch/arm/mach-exynos/clock-exynos4212.c | |||
@@ -92,6 +92,16 @@ static struct clk init_clocks_off[] = { | |||
92 | .devname = SYSMMU_CLOCK_DEVNAME(isp, 9), | 92 | .devname = SYSMMU_CLOCK_DEVNAME(isp, 9), |
93 | .enable = exynos4212_clk_ip_isp1_ctrl, | 93 | .enable = exynos4212_clk_ip_isp1_ctrl, |
94 | .ctrlbit = (1 << 4), | 94 | .ctrlbit = (1 << 4), |
95 | }, { | ||
96 | .name = "flite", | ||
97 | .devname = "exynos-fimc-lite.0", | ||
98 | .enable = exynos4212_clk_ip_isp0_ctrl, | ||
99 | .ctrlbit = (1 << 4), | ||
100 | }, { | ||
101 | .name = "flite", | ||
102 | .devname = "exynos-fimc-lite.1", | ||
103 | .enable = exynos4212_clk_ip_isp0_ctrl, | ||
104 | .ctrlbit = (1 << 3), | ||
95 | } | 105 | } |
96 | }; | 106 | }; |
97 | 107 | ||
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index 9f87a07b0bf8..5aa460b01fdf 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c | |||
@@ -165,11 +165,29 @@ static struct clksrc_clk exynos5_clk_sclk_apll = { | |||
165 | .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 }, | 165 | .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 }, |
166 | }; | 166 | }; |
167 | 167 | ||
168 | static struct clksrc_clk exynos5_clk_mout_bpll_fout = { | ||
169 | .clk = { | ||
170 | .name = "mout_bpll_fout", | ||
171 | }, | ||
172 | .sources = &clk_src_bpll_fout, | ||
173 | .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 }, | ||
174 | }; | ||
175 | |||
176 | static struct clk *exynos5_clk_src_bpll_list[] = { | ||
177 | [0] = &clk_fin_bpll, | ||
178 | [1] = &exynos5_clk_mout_bpll_fout.clk, | ||
179 | }; | ||
180 | |||
181 | static struct clksrc_sources exynos5_clk_src_bpll = { | ||
182 | .sources = exynos5_clk_src_bpll_list, | ||
183 | .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list), | ||
184 | }; | ||
185 | |||
168 | static struct clksrc_clk exynos5_clk_mout_bpll = { | 186 | static struct clksrc_clk exynos5_clk_mout_bpll = { |
169 | .clk = { | 187 | .clk = { |
170 | .name = "mout_bpll", | 188 | .name = "mout_bpll", |
171 | }, | 189 | }, |
172 | .sources = &clk_src_bpll, | 190 | .sources = &exynos5_clk_src_bpll, |
173 | .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 }, | 191 | .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 }, |
174 | }; | 192 | }; |
175 | 193 | ||
@@ -207,11 +225,29 @@ static struct clksrc_clk exynos5_clk_mout_epll = { | |||
207 | .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 }, | 225 | .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 }, |
208 | }; | 226 | }; |
209 | 227 | ||
228 | static struct clksrc_clk exynos5_clk_mout_mpll_fout = { | ||
229 | .clk = { | ||
230 | .name = "mout_mpll_fout", | ||
231 | }, | ||
232 | .sources = &clk_src_mpll_fout, | ||
233 | .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 }, | ||
234 | }; | ||
235 | |||
236 | static struct clk *exynos5_clk_src_mpll_list[] = { | ||
237 | [0] = &clk_fin_mpll, | ||
238 | [1] = &exynos5_clk_mout_mpll_fout.clk, | ||
239 | }; | ||
240 | |||
241 | static struct clksrc_sources exynos5_clk_src_mpll = { | ||
242 | .sources = exynos5_clk_src_mpll_list, | ||
243 | .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list), | ||
244 | }; | ||
245 | |||
210 | struct clksrc_clk exynos5_clk_mout_mpll = { | 246 | struct clksrc_clk exynos5_clk_mout_mpll = { |
211 | .clk = { | 247 | .clk = { |
212 | .name = "mout_mpll", | 248 | .name = "mout_mpll", |
213 | }, | 249 | }, |
214 | .sources = &clk_src_mpll, | 250 | .sources = &exynos5_clk_src_mpll, |
215 | .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 }, | 251 | .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 }, |
216 | }; | 252 | }; |
217 | 253 | ||
@@ -474,6 +510,11 @@ static struct clk exynos5_init_clocks_off[] = { | |||
474 | .enable = exynos5_clk_ip_peris_ctrl, | 510 | .enable = exynos5_clk_ip_peris_ctrl, |
475 | .ctrlbit = (1 << 20), | 511 | .ctrlbit = (1 << 20), |
476 | }, { | 512 | }, { |
513 | .name = "watchdog", | ||
514 | .parent = &exynos5_clk_aclk_66.clk, | ||
515 | .enable = exynos5_clk_ip_peris_ctrl, | ||
516 | .ctrlbit = (1 << 19), | ||
517 | }, { | ||
477 | .name = "hsmmc", | 518 | .name = "hsmmc", |
478 | .devname = "exynos4-sdhci.0", | 519 | .devname = "exynos4-sdhci.0", |
479 | .parent = &exynos5_clk_aclk_200.clk, | 520 | .parent = &exynos5_clk_aclk_200.clk, |
@@ -1031,10 +1072,12 @@ static struct clksrc_clk *exynos5_sysclks[] = { | |||
1031 | &exynos5_clk_mout_apll, | 1072 | &exynos5_clk_mout_apll, |
1032 | &exynos5_clk_sclk_apll, | 1073 | &exynos5_clk_sclk_apll, |
1033 | &exynos5_clk_mout_bpll, | 1074 | &exynos5_clk_mout_bpll, |
1075 | &exynos5_clk_mout_bpll_fout, | ||
1034 | &exynos5_clk_mout_bpll_user, | 1076 | &exynos5_clk_mout_bpll_user, |
1035 | &exynos5_clk_mout_cpll, | 1077 | &exynos5_clk_mout_cpll, |
1036 | &exynos5_clk_mout_epll, | 1078 | &exynos5_clk_mout_epll, |
1037 | &exynos5_clk_mout_mpll, | 1079 | &exynos5_clk_mout_mpll, |
1080 | &exynos5_clk_mout_mpll_fout, | ||
1038 | &exynos5_clk_mout_mpll_user, | 1081 | &exynos5_clk_mout_mpll_user, |
1039 | &exynos5_clk_vpllsrc, | 1082 | &exynos5_clk_vpllsrc, |
1040 | &exynos5_clk_sclk_vpll, | 1083 | &exynos5_clk_sclk_vpll, |
@@ -1098,7 +1141,9 @@ static struct clk *exynos5_clks[] __initdata = { | |||
1098 | &exynos5_clk_sclk_hdmi27m, | 1141 | &exynos5_clk_sclk_hdmi27m, |
1099 | &exynos5_clk_sclk_hdmiphy, | 1142 | &exynos5_clk_sclk_hdmiphy, |
1100 | &clk_fout_bpll, | 1143 | &clk_fout_bpll, |
1144 | &clk_fout_bpll_div2, | ||
1101 | &clk_fout_cpll, | 1145 | &clk_fout_cpll, |
1146 | &clk_fout_mpll_div2, | ||
1102 | &exynos5_clk_armclk, | 1147 | &exynos5_clk_armclk, |
1103 | }; | 1148 | }; |
1104 | 1149 | ||
@@ -1263,8 +1308,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void) | |||
1263 | 1308 | ||
1264 | clk_fout_apll.ops = &exynos5_fout_apll_ops; | 1309 | clk_fout_apll.ops = &exynos5_fout_apll_ops; |
1265 | clk_fout_bpll.rate = bpll; | 1310 | clk_fout_bpll.rate = bpll; |
1311 | clk_fout_bpll_div2.rate = bpll >> 1; | ||
1266 | clk_fout_cpll.rate = cpll; | 1312 | clk_fout_cpll.rate = cpll; |
1267 | clk_fout_mpll.rate = mpll; | 1313 | clk_fout_mpll.rate = mpll; |
1314 | clk_fout_mpll_div2.rate = mpll >> 1; | ||
1268 | clk_fout_epll.rate = epll; | 1315 | clk_fout_epll.rate = epll; |
1269 | clk_fout_vpll.rate = vpll; | 1316 | clk_fout_vpll.rate = vpll; |
1270 | 1317 | ||
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 5ccd6e80a607..49134711f4c6 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c | |||
@@ -19,6 +19,9 @@ | |||
19 | #include <linux/serial_core.h> | 19 | #include <linux/serial_core.h> |
20 | #include <linux/of.h> | 20 | #include <linux/of.h> |
21 | #include <linux/of_irq.h> | 21 | #include <linux/of_irq.h> |
22 | #include <linux/export.h> | ||
23 | #include <linux/irqdomain.h> | ||
24 | #include <linux/of_address.h> | ||
22 | 25 | ||
23 | #include <asm/proc-fns.h> | 26 | #include <asm/proc-fns.h> |
24 | #include <asm/exception.h> | 27 | #include <asm/exception.h> |
@@ -265,12 +268,12 @@ static struct map_desc exynos5_iodesc[] __initdata = { | |||
265 | }, { | 268 | }, { |
266 | .virtual = (unsigned long)S5P_VA_GIC_CPU, | 269 | .virtual = (unsigned long)S5P_VA_GIC_CPU, |
267 | .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU), | 270 | .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU), |
268 | .length = SZ_64K, | 271 | .length = SZ_8K, |
269 | .type = MT_DEVICE, | 272 | .type = MT_DEVICE, |
270 | }, { | 273 | }, { |
271 | .virtual = (unsigned long)S5P_VA_GIC_DIST, | 274 | .virtual = (unsigned long)S5P_VA_GIC_DIST, |
272 | .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST), | 275 | .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST), |
273 | .length = SZ_64K, | 276 | .length = SZ_4K, |
274 | .type = MT_DEVICE, | 277 | .type = MT_DEVICE, |
275 | }, | 278 | }, |
276 | }; | 279 | }; |
@@ -399,6 +402,7 @@ struct combiner_chip_data { | |||
399 | void __iomem *base; | 402 | void __iomem *base; |
400 | }; | 403 | }; |
401 | 404 | ||
405 | static struct irq_domain *combiner_irq_domain; | ||
402 | static struct combiner_chip_data combiner_data[MAX_COMBINER_NR]; | 406 | static struct combiner_chip_data combiner_data[MAX_COMBINER_NR]; |
403 | 407 | ||
404 | static inline void __iomem *combiner_base(struct irq_data *data) | 408 | static inline void __iomem *combiner_base(struct irq_data *data) |
@@ -411,14 +415,14 @@ static inline void __iomem *combiner_base(struct irq_data *data) | |||
411 | 415 | ||
412 | static void combiner_mask_irq(struct irq_data *data) | 416 | static void combiner_mask_irq(struct irq_data *data) |
413 | { | 417 | { |
414 | u32 mask = 1 << (data->irq % 32); | 418 | u32 mask = 1 << (data->hwirq % 32); |
415 | 419 | ||
416 | __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); | 420 | __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); |
417 | } | 421 | } |
418 | 422 | ||
419 | static void combiner_unmask_irq(struct irq_data *data) | 423 | static void combiner_unmask_irq(struct irq_data *data) |
420 | { | 424 | { |
421 | u32 mask = 1 << (data->irq % 32); | 425 | u32 mask = 1 << (data->hwirq % 32); |
422 | 426 | ||
423 | __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET); | 427 | __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET); |
424 | } | 428 | } |
@@ -474,49 +478,131 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i | |||
474 | irq_set_chained_handler(irq, combiner_handle_cascade_irq); | 478 | irq_set_chained_handler(irq, combiner_handle_cascade_irq); |
475 | } | 479 | } |
476 | 480 | ||
477 | static void __init combiner_init(unsigned int combiner_nr, void __iomem *base, | 481 | static void __init combiner_init_one(unsigned int combiner_nr, |
478 | unsigned int irq_start) | 482 | void __iomem *base) |
479 | { | 483 | { |
480 | unsigned int i; | ||
481 | unsigned int max_nr; | ||
482 | |||
483 | if (soc_is_exynos5250()) | ||
484 | max_nr = EXYNOS5_MAX_COMBINER_NR; | ||
485 | else | ||
486 | max_nr = EXYNOS4_MAX_COMBINER_NR; | ||
487 | |||
488 | if (combiner_nr >= max_nr) | ||
489 | BUG(); | ||
490 | |||
491 | combiner_data[combiner_nr].base = base; | 484 | combiner_data[combiner_nr].base = base; |
492 | combiner_data[combiner_nr].irq_offset = irq_start; | 485 | combiner_data[combiner_nr].irq_offset = irq_find_mapping( |
486 | combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER); | ||
493 | combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3); | 487 | combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3); |
494 | 488 | ||
495 | /* Disable all interrupts */ | 489 | /* Disable all interrupts */ |
496 | |||
497 | __raw_writel(combiner_data[combiner_nr].irq_mask, | 490 | __raw_writel(combiner_data[combiner_nr].irq_mask, |
498 | base + COMBINER_ENABLE_CLEAR); | 491 | base + COMBINER_ENABLE_CLEAR); |
492 | } | ||
493 | |||
494 | #ifdef CONFIG_OF | ||
495 | static int combiner_irq_domain_xlate(struct irq_domain *d, | ||
496 | struct device_node *controller, | ||
497 | const u32 *intspec, unsigned int intsize, | ||
498 | unsigned long *out_hwirq, | ||
499 | unsigned int *out_type) | ||
500 | { | ||
501 | if (d->of_node != controller) | ||
502 | return -EINVAL; | ||
503 | |||
504 | if (intsize < 2) | ||
505 | return -EINVAL; | ||
506 | |||
507 | *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1]; | ||
508 | *out_type = 0; | ||
509 | |||
510 | return 0; | ||
511 | } | ||
512 | #else | ||
513 | static int combiner_irq_domain_xlate(struct irq_domain *d, | ||
514 | struct device_node *controller, | ||
515 | const u32 *intspec, unsigned int intsize, | ||
516 | unsigned long *out_hwirq, | ||
517 | unsigned int *out_type) | ||
518 | { | ||
519 | return -EINVAL; | ||
520 | } | ||
521 | #endif | ||
522 | |||
523 | static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq, | ||
524 | irq_hw_number_t hw) | ||
525 | { | ||
526 | irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq); | ||
527 | irq_set_chip_data(irq, &combiner_data[hw >> 3]); | ||
528 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
499 | 529 | ||
500 | /* Setup the Linux IRQ subsystem */ | 530 | return 0; |
531 | } | ||
532 | |||
533 | static struct irq_domain_ops combiner_irq_domain_ops = { | ||
534 | .xlate = combiner_irq_domain_xlate, | ||
535 | .map = combiner_irq_domain_map, | ||
536 | }; | ||
501 | 537 | ||
502 | for (i = irq_start; i < combiner_data[combiner_nr].irq_offset | 538 | void __init combiner_init(void __iomem *combiner_base, struct device_node *np) |
503 | + MAX_IRQ_IN_COMBINER; i++) { | 539 | { |
504 | irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq); | 540 | int i, irq, irq_base; |
505 | irq_set_chip_data(i, &combiner_data[combiner_nr]); | 541 | unsigned int max_nr, nr_irq; |
506 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 542 | |
543 | if (np) { | ||
544 | if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) { | ||
545 | pr_warning("%s: number of combiners not specified, " | ||
546 | "setting default as %d.\n", | ||
547 | __func__, EXYNOS4_MAX_COMBINER_NR); | ||
548 | max_nr = EXYNOS4_MAX_COMBINER_NR; | ||
549 | } | ||
550 | } else { | ||
551 | max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR : | ||
552 | EXYNOS4_MAX_COMBINER_NR; | ||
553 | } | ||
554 | nr_irq = max_nr * MAX_IRQ_IN_COMBINER; | ||
555 | |||
556 | irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0); | ||
557 | if (IS_ERR_VALUE(irq_base)) { | ||
558 | irq_base = COMBINER_IRQ(0, 0); | ||
559 | pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base); | ||
560 | } | ||
561 | |||
562 | combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0, | ||
563 | &combiner_irq_domain_ops, &combiner_data); | ||
564 | if (WARN_ON(!combiner_irq_domain)) { | ||
565 | pr_warning("%s: irq domain init failed\n", __func__); | ||
566 | return; | ||
567 | } | ||
568 | |||
569 | for (i = 0; i < max_nr; i++) { | ||
570 | combiner_init_one(i, combiner_base + (i >> 2) * 0x10); | ||
571 | irq = IRQ_SPI(i); | ||
572 | #ifdef CONFIG_OF | ||
573 | if (np) | ||
574 | irq = irq_of_parse_and_map(np, i); | ||
575 | #endif | ||
576 | combiner_cascade_irq(i, irq); | ||
507 | } | 577 | } |
508 | } | 578 | } |
509 | 579 | ||
510 | #ifdef CONFIG_OF | 580 | #ifdef CONFIG_OF |
581 | int __init combiner_of_init(struct device_node *np, struct device_node *parent) | ||
582 | { | ||
583 | void __iomem *combiner_base; | ||
584 | |||
585 | combiner_base = of_iomap(np, 0); | ||
586 | if (!combiner_base) { | ||
587 | pr_err("%s: failed to map combiner registers\n", __func__); | ||
588 | return -ENXIO; | ||
589 | } | ||
590 | |||
591 | combiner_init(combiner_base, np); | ||
592 | |||
593 | return 0; | ||
594 | } | ||
595 | |||
511 | static const struct of_device_id exynos4_dt_irq_match[] = { | 596 | static const struct of_device_id exynos4_dt_irq_match[] = { |
512 | { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, | 597 | { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, |
598 | { .compatible = "samsung,exynos4210-combiner", | ||
599 | .data = combiner_of_init, }, | ||
513 | {}, | 600 | {}, |
514 | }; | 601 | }; |
515 | #endif | 602 | #endif |
516 | 603 | ||
517 | void __init exynos4_init_irq(void) | 604 | void __init exynos4_init_irq(void) |
518 | { | 605 | { |
519 | int irq; | ||
520 | unsigned int gic_bank_offset; | 606 | unsigned int gic_bank_offset; |
521 | 607 | ||
522 | gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; | 608 | gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; |
@@ -528,12 +614,8 @@ void __init exynos4_init_irq(void) | |||
528 | of_irq_init(exynos4_dt_irq_match); | 614 | of_irq_init(exynos4_dt_irq_match); |
529 | #endif | 615 | #endif |
530 | 616 | ||
531 | for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) { | 617 | if (!of_have_populated_dt()) |
532 | 618 | combiner_init(S5P_VA_COMBINER_BASE, NULL); | |
533 | combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), | ||
534 | COMBINER_IRQ(irq, 0)); | ||
535 | combiner_cascade_irq(irq, IRQ_SPI(irq)); | ||
536 | } | ||
537 | 619 | ||
538 | /* | 620 | /* |
539 | * The parameters of s5p_init_irq() are for VIC init. | 621 | * The parameters of s5p_init_irq() are for VIC init. |
@@ -545,18 +627,9 @@ void __init exynos4_init_irq(void) | |||
545 | 627 | ||
546 | void __init exynos5_init_irq(void) | 628 | void __init exynos5_init_irq(void) |
547 | { | 629 | { |
548 | int irq; | ||
549 | |||
550 | #ifdef CONFIG_OF | 630 | #ifdef CONFIG_OF |
551 | of_irq_init(exynos4_dt_irq_match); | 631 | of_irq_init(exynos4_dt_irq_match); |
552 | #endif | 632 | #endif |
553 | |||
554 | for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) { | ||
555 | combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), | ||
556 | COMBINER_IRQ(irq, 0)); | ||
557 | combiner_cascade_irq(irq, IRQ_SPI(irq)); | ||
558 | } | ||
559 | |||
560 | /* | 633 | /* |
561 | * The parameters of s5p_init_irq() are for VIC init. | 634 | * The parameters of s5p_init_irq() are for VIC init. |
562 | * Theses parameters should be NULL and 0 because EXYNOS4 | 635 | * Theses parameters should be NULL and 0 because EXYNOS4 |
@@ -565,30 +638,18 @@ void __init exynos5_init_irq(void) | |||
565 | s5p_init_irq(NULL, 0); | 638 | s5p_init_irq(NULL, 0); |
566 | } | 639 | } |
567 | 640 | ||
568 | struct bus_type exynos4_subsys = { | 641 | struct bus_type exynos_subsys = { |
569 | .name = "exynos4-core", | 642 | .name = "exynos-core", |
570 | .dev_name = "exynos4-core", | 643 | .dev_name = "exynos-core", |
571 | }; | ||
572 | |||
573 | struct bus_type exynos5_subsys = { | ||
574 | .name = "exynos5-core", | ||
575 | .dev_name = "exynos5-core", | ||
576 | }; | 644 | }; |
577 | 645 | ||
578 | static struct device exynos4_dev = { | 646 | static struct device exynos4_dev = { |
579 | .bus = &exynos4_subsys, | 647 | .bus = &exynos_subsys, |
580 | }; | ||
581 | |||
582 | static struct device exynos5_dev = { | ||
583 | .bus = &exynos5_subsys, | ||
584 | }; | 648 | }; |
585 | 649 | ||
586 | static int __init exynos_core_init(void) | 650 | static int __init exynos_core_init(void) |
587 | { | 651 | { |
588 | if (soc_is_exynos5250()) | 652 | return subsys_system_register(&exynos_subsys, NULL); |
589 | return subsys_system_register(&exynos5_subsys, NULL); | ||
590 | else | ||
591 | return subsys_system_register(&exynos4_subsys, NULL); | ||
592 | } | 653 | } |
593 | core_initcall(exynos_core_init); | 654 | core_initcall(exynos_core_init); |
594 | 655 | ||
@@ -675,10 +736,7 @@ static int __init exynos_init(void) | |||
675 | { | 736 | { |
676 | printk(KERN_INFO "EXYNOS: Initializing architecture\n"); | 737 | printk(KERN_INFO "EXYNOS: Initializing architecture\n"); |
677 | 738 | ||
678 | if (soc_is_exynos5250()) | 739 | return device_register(&exynos4_dev); |
679 | return device_register(&exynos5_dev); | ||
680 | else | ||
681 | return device_register(&exynos4_dev); | ||
682 | } | 740 | } |
683 | 741 | ||
684 | /* uart registration process */ | 742 | /* uart registration process */ |
diff --git a/arch/arm/mach-exynos/dev-drm.c b/arch/arm/mach-exynos/dev-drm.c new file mode 100644 index 000000000000..17c9c6ecc2e0 --- /dev/null +++ b/arch/arm/mach-exynos/dev-drm.c | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-exynos/dev-drm.c | ||
3 | * | ||
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | ||
5 | * http://www.samsung.com | ||
6 | * | ||
7 | * EXYNOS - core DRM device | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/dma-mapping.h> | ||
17 | #include <linux/platform_device.h> | ||
18 | |||
19 | #include <plat/devs.h> | ||
20 | |||
21 | static u64 exynos_drm_dma_mask = DMA_BIT_MASK(32); | ||
22 | |||
23 | struct platform_device exynos_device_drm = { | ||
24 | .name = "exynos-drm", | ||
25 | .dev = { | ||
26 | .dma_mask = &exynos_drm_dma_mask, | ||
27 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
28 | } | ||
29 | }; | ||
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c index 69aaa4503205..f60b66dbcf84 100644 --- a/arch/arm/mach-exynos/dma.c +++ b/arch/arm/mach-exynos/dma.c | |||
@@ -103,10 +103,45 @@ static u8 exynos4212_pdma0_peri[] = { | |||
103 | DMACH_MIPI_HSI5, | 103 | DMACH_MIPI_HSI5, |
104 | }; | 104 | }; |
105 | 105 | ||
106 | struct dma_pl330_platdata exynos4_pdma0_pdata; | 106 | static u8 exynos5250_pdma0_peri[] = { |
107 | DMACH_PCM0_RX, | ||
108 | DMACH_PCM0_TX, | ||
109 | DMACH_PCM2_RX, | ||
110 | DMACH_PCM2_TX, | ||
111 | DMACH_SPI0_RX, | ||
112 | DMACH_SPI0_TX, | ||
113 | DMACH_SPI2_RX, | ||
114 | DMACH_SPI2_TX, | ||
115 | DMACH_I2S0S_TX, | ||
116 | DMACH_I2S0_RX, | ||
117 | DMACH_I2S0_TX, | ||
118 | DMACH_I2S2_RX, | ||
119 | DMACH_I2S2_TX, | ||
120 | DMACH_UART0_RX, | ||
121 | DMACH_UART0_TX, | ||
122 | DMACH_UART2_RX, | ||
123 | DMACH_UART2_TX, | ||
124 | DMACH_UART4_RX, | ||
125 | DMACH_UART4_TX, | ||
126 | DMACH_SLIMBUS0_RX, | ||
127 | DMACH_SLIMBUS0_TX, | ||
128 | DMACH_SLIMBUS2_RX, | ||
129 | DMACH_SLIMBUS2_TX, | ||
130 | DMACH_SLIMBUS4_RX, | ||
131 | DMACH_SLIMBUS4_TX, | ||
132 | DMACH_AC97_MICIN, | ||
133 | DMACH_AC97_PCMIN, | ||
134 | DMACH_AC97_PCMOUT, | ||
135 | DMACH_MIPI_HSI0, | ||
136 | DMACH_MIPI_HSI2, | ||
137 | DMACH_MIPI_HSI4, | ||
138 | DMACH_MIPI_HSI6, | ||
139 | }; | ||
140 | |||
141 | static struct dma_pl330_platdata exynos_pdma0_pdata; | ||
107 | 142 | ||
108 | static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, | 143 | static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330, |
109 | EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata); | 144 | EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata); |
110 | 145 | ||
111 | static u8 exynos4210_pdma1_peri[] = { | 146 | static u8 exynos4210_pdma1_peri[] = { |
112 | DMACH_PCM0_RX, | 147 | DMACH_PCM0_RX, |
@@ -169,10 +204,45 @@ static u8 exynos4212_pdma1_peri[] = { | |||
169 | DMACH_MIPI_HSI7, | 204 | DMACH_MIPI_HSI7, |
170 | }; | 205 | }; |
171 | 206 | ||
172 | static struct dma_pl330_platdata exynos4_pdma1_pdata; | 207 | static u8 exynos5250_pdma1_peri[] = { |
208 | DMACH_PCM0_RX, | ||
209 | DMACH_PCM0_TX, | ||
210 | DMACH_PCM1_RX, | ||
211 | DMACH_PCM1_TX, | ||
212 | DMACH_SPI1_RX, | ||
213 | DMACH_SPI1_TX, | ||
214 | DMACH_PWM, | ||
215 | DMACH_SPDIF, | ||
216 | DMACH_I2S0S_TX, | ||
217 | DMACH_I2S0_RX, | ||
218 | DMACH_I2S0_TX, | ||
219 | DMACH_I2S1_RX, | ||
220 | DMACH_I2S1_TX, | ||
221 | DMACH_UART0_RX, | ||
222 | DMACH_UART0_TX, | ||
223 | DMACH_UART1_RX, | ||
224 | DMACH_UART1_TX, | ||
225 | DMACH_UART3_RX, | ||
226 | DMACH_UART3_TX, | ||
227 | DMACH_SLIMBUS1_RX, | ||
228 | DMACH_SLIMBUS1_TX, | ||
229 | DMACH_SLIMBUS3_RX, | ||
230 | DMACH_SLIMBUS3_TX, | ||
231 | DMACH_SLIMBUS5_RX, | ||
232 | DMACH_SLIMBUS5_TX, | ||
233 | DMACH_SLIMBUS0AUX_RX, | ||
234 | DMACH_SLIMBUS0AUX_TX, | ||
235 | DMACH_DISP1, | ||
236 | DMACH_MIPI_HSI1, | ||
237 | DMACH_MIPI_HSI3, | ||
238 | DMACH_MIPI_HSI5, | ||
239 | DMACH_MIPI_HSI7, | ||
240 | }; | ||
173 | 241 | ||
174 | static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, | 242 | static struct dma_pl330_platdata exynos_pdma1_pdata; |
175 | EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata); | 243 | |
244 | static AMBA_AHB_DEVICE(exynos_pdma1, "dma-pl330.1", 0x00041330, | ||
245 | EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata); | ||
176 | 246 | ||
177 | static u8 mdma_peri[] = { | 247 | static u8 mdma_peri[] = { |
178 | DMACH_MTOM_0, | 248 | DMACH_MTOM_0, |
@@ -185,46 +255,63 @@ static u8 mdma_peri[] = { | |||
185 | DMACH_MTOM_7, | 255 | DMACH_MTOM_7, |
186 | }; | 256 | }; |
187 | 257 | ||
188 | static struct dma_pl330_platdata exynos4_mdma1_pdata = { | 258 | static struct dma_pl330_platdata exynos_mdma1_pdata = { |
189 | .nr_valid_peri = ARRAY_SIZE(mdma_peri), | 259 | .nr_valid_peri = ARRAY_SIZE(mdma_peri), |
190 | .peri_id = mdma_peri, | 260 | .peri_id = mdma_peri, |
191 | }; | 261 | }; |
192 | 262 | ||
193 | static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330, | 263 | static AMBA_AHB_DEVICE(exynos_mdma1, "dma-pl330.2", 0x00041330, |
194 | EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata); | 264 | EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata); |
195 | 265 | ||
196 | static int __init exynos4_dma_init(void) | 266 | static int __init exynos_dma_init(void) |
197 | { | 267 | { |
198 | if (of_have_populated_dt()) | 268 | if (of_have_populated_dt()) |
199 | return 0; | 269 | return 0; |
200 | 270 | ||
201 | if (soc_is_exynos4210()) { | 271 | if (soc_is_exynos4210()) { |
202 | exynos4_pdma0_pdata.nr_valid_peri = | 272 | exynos_pdma0_pdata.nr_valid_peri = |
203 | ARRAY_SIZE(exynos4210_pdma0_peri); | 273 | ARRAY_SIZE(exynos4210_pdma0_peri); |
204 | exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri; | 274 | exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri; |
205 | exynos4_pdma1_pdata.nr_valid_peri = | 275 | exynos_pdma1_pdata.nr_valid_peri = |
206 | ARRAY_SIZE(exynos4210_pdma1_peri); | 276 | ARRAY_SIZE(exynos4210_pdma1_peri); |
207 | exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri; | 277 | exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri; |
208 | } else if (soc_is_exynos4212() || soc_is_exynos4412()) { | 278 | } else if (soc_is_exynos4212() || soc_is_exynos4412()) { |
209 | exynos4_pdma0_pdata.nr_valid_peri = | 279 | exynos_pdma0_pdata.nr_valid_peri = |
210 | ARRAY_SIZE(exynos4212_pdma0_peri); | 280 | ARRAY_SIZE(exynos4212_pdma0_peri); |
211 | exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri; | 281 | exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri; |
212 | exynos4_pdma1_pdata.nr_valid_peri = | 282 | exynos_pdma1_pdata.nr_valid_peri = |
213 | ARRAY_SIZE(exynos4212_pdma1_peri); | 283 | ARRAY_SIZE(exynos4212_pdma1_peri); |
214 | exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri; | 284 | exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri; |
285 | } else if (soc_is_exynos5250()) { | ||
286 | exynos_pdma0_pdata.nr_valid_peri = | ||
287 | ARRAY_SIZE(exynos5250_pdma0_peri); | ||
288 | exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri; | ||
289 | exynos_pdma1_pdata.nr_valid_peri = | ||
290 | ARRAY_SIZE(exynos5250_pdma1_peri); | ||
291 | exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri; | ||
292 | |||
293 | exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0; | ||
294 | exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K; | ||
295 | exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0; | ||
296 | exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1; | ||
297 | exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K; | ||
298 | exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1; | ||
299 | exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1; | ||
300 | exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K; | ||
301 | exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1; | ||
215 | } | 302 | } |
216 | 303 | ||
217 | dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask); | 304 | dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask); |
218 | dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask); | 305 | dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask); |
219 | amba_device_register(&exynos4_pdma0_device, &iomem_resource); | 306 | amba_device_register(&exynos_pdma0_device, &iomem_resource); |
220 | 307 | ||
221 | dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask); | 308 | dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask); |
222 | dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask); | 309 | dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask); |
223 | amba_device_register(&exynos4_pdma1_device, &iomem_resource); | 310 | amba_device_register(&exynos_pdma1_device, &iomem_resource); |
224 | 311 | ||
225 | dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask); | 312 | dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask); |
226 | amba_device_register(&exynos4_mdma1_device, &iomem_resource); | 313 | amba_device_register(&exynos_mdma1_device, &iomem_resource); |
227 | 314 | ||
228 | return 0; | 315 | return 0; |
229 | } | 316 | } |
230 | arch_initcall(exynos4_dma_init); | 317 | arch_initcall(exynos_dma_init); |
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h index d7498afe036a..eb24f1eb8e3b 100644 --- a/arch/arm/mach-exynos/include/mach/gpio.h +++ b/arch/arm/mach-exynos/include/mach/gpio.h | |||
@@ -153,10 +153,11 @@ enum exynos4_gpio_number { | |||
153 | #define EXYNOS5_GPIO_B2_NR (4) | 153 | #define EXYNOS5_GPIO_B2_NR (4) |
154 | #define EXYNOS5_GPIO_B3_NR (4) | 154 | #define EXYNOS5_GPIO_B3_NR (4) |
155 | #define EXYNOS5_GPIO_C0_NR (7) | 155 | #define EXYNOS5_GPIO_C0_NR (7) |
156 | #define EXYNOS5_GPIO_C1_NR (7) | 156 | #define EXYNOS5_GPIO_C1_NR (4) |
157 | #define EXYNOS5_GPIO_C2_NR (7) | 157 | #define EXYNOS5_GPIO_C2_NR (7) |
158 | #define EXYNOS5_GPIO_C3_NR (7) | 158 | #define EXYNOS5_GPIO_C3_NR (7) |
159 | #define EXYNOS5_GPIO_D0_NR (8) | 159 | #define EXYNOS5_GPIO_C4_NR (7) |
160 | #define EXYNOS5_GPIO_D0_NR (4) | ||
160 | #define EXYNOS5_GPIO_D1_NR (8) | 161 | #define EXYNOS5_GPIO_D1_NR (8) |
161 | #define EXYNOS5_GPIO_Y0_NR (6) | 162 | #define EXYNOS5_GPIO_Y0_NR (6) |
162 | #define EXYNOS5_GPIO_Y1_NR (4) | 163 | #define EXYNOS5_GPIO_Y1_NR (4) |
@@ -199,7 +200,8 @@ enum exynos5_gpio_number { | |||
199 | EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0), | 200 | EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0), |
200 | EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1), | 201 | EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1), |
201 | EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2), | 202 | EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2), |
202 | EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3), | 203 | EXYNOS5_GPIO_C4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3), |
204 | EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4), | ||
203 | EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0), | 205 | EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0), |
204 | EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1), | 206 | EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1), |
205 | EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0), | 207 | EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0), |
@@ -242,6 +244,7 @@ enum exynos5_gpio_number { | |||
242 | #define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr)) | 244 | #define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr)) |
243 | #define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr)) | 245 | #define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr)) |
244 | #define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr)) | 246 | #define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr)) |
247 | #define EXYNOS5_GPC4(_nr) (EXYNOS5_GPIO_C4_START + (_nr)) | ||
245 | #define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr)) | 248 | #define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr)) |
246 | #define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr)) | 249 | #define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr)) |
247 | #define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr)) | 250 | #define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr)) |
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index ddde8f3a24d4..7a4b4789eb72 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h | |||
@@ -287,6 +287,7 @@ | |||
287 | #define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80) | 287 | #define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80) |
288 | #define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81) | 288 | #define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81) |
289 | #define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82) | 289 | #define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82) |
290 | #define EXYNOS5_IRQ_WDT_IOP IRQ_SPI(83) | ||
290 | #define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84) | 291 | #define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84) |
291 | #define EXYNOS5_IRQ_GSC0 IRQ_SPI(85) | 292 | #define EXYNOS5_IRQ_GSC0 IRQ_SPI(85) |
292 | #define EXYNOS5_IRQ_GSC1 IRQ_SPI(86) | 293 | #define EXYNOS5_IRQ_GSC1 IRQ_SPI(86) |
@@ -295,8 +296,8 @@ | |||
295 | #define EXYNOS5_IRQ_JPEG IRQ_SPI(89) | 296 | #define EXYNOS5_IRQ_JPEG IRQ_SPI(89) |
296 | #define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90) | 297 | #define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90) |
297 | #define EXYNOS5_IRQ_2D IRQ_SPI(91) | 298 | #define EXYNOS5_IRQ_2D IRQ_SPI(91) |
298 | #define EXYNOS5_IRQ_SFMC0 IRQ_SPI(92) | 299 | #define EXYNOS5_IRQ_EFNFCON_0 IRQ_SPI(92) |
299 | #define EXYNOS5_IRQ_SFMC1 IRQ_SPI(93) | 300 | #define EXYNOS5_IRQ_EFNFCON_1 IRQ_SPI(93) |
300 | #define EXYNOS5_IRQ_MIXER IRQ_SPI(94) | 301 | #define EXYNOS5_IRQ_MIXER IRQ_SPI(94) |
301 | #define EXYNOS5_IRQ_HDMI IRQ_SPI(95) | 302 | #define EXYNOS5_IRQ_HDMI IRQ_SPI(95) |
302 | #define EXYNOS5_IRQ_MFC IRQ_SPI(96) | 303 | #define EXYNOS5_IRQ_MFC IRQ_SPI(96) |
@@ -310,7 +311,7 @@ | |||
310 | #define EXYNOS5_IRQ_PCM2 IRQ_SPI(104) | 311 | #define EXYNOS5_IRQ_PCM2 IRQ_SPI(104) |
311 | #define EXYNOS5_IRQ_SPDIF IRQ_SPI(105) | 312 | #define EXYNOS5_IRQ_SPDIF IRQ_SPI(105) |
312 | #define EXYNOS5_IRQ_ADC0 IRQ_SPI(106) | 313 | #define EXYNOS5_IRQ_ADC0 IRQ_SPI(106) |
313 | 314 | #define EXYNOS5_IRQ_ADC1 IRQ_SPI(107) | |
314 | #define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108) | 315 | #define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108) |
315 | #define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109) | 316 | #define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109) |
316 | #define EXYNOS5_IRQ_CAM_C IRQ_SPI(110) | 317 | #define EXYNOS5_IRQ_CAM_C IRQ_SPI(110) |
@@ -319,8 +320,9 @@ | |||
319 | #define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113) | 320 | #define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113) |
320 | #define EXYNOS5_IRQ_CEC IRQ_SPI(114) | 321 | #define EXYNOS5_IRQ_CEC IRQ_SPI(114) |
321 | #define EXYNOS5_IRQ_SATA IRQ_SPI(115) | 322 | #define EXYNOS5_IRQ_SATA IRQ_SPI(115) |
322 | #define EXYNOS5_IRQ_NFCON IRQ_SPI(116) | ||
323 | 323 | ||
324 | #define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120) | ||
325 | #define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121) | ||
324 | #define EXYNOS5_IRQ_MMC44 IRQ_SPI(123) | 326 | #define EXYNOS5_IRQ_MMC44 IRQ_SPI(123) |
325 | #define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124) | 327 | #define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124) |
326 | #define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125) | 328 | #define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125) |
@@ -328,7 +330,6 @@ | |||
328 | #define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127) | 330 | #define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127) |
329 | 331 | ||
330 | #define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2) | 332 | #define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2) |
331 | #define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(1, 6) | ||
332 | 333 | ||
333 | #define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0) | 334 | #define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0) |
334 | #define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1) | 335 | #define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1) |
@@ -339,6 +340,8 @@ | |||
339 | #define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6) | 340 | #define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6) |
340 | #define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7) | 341 | #define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7) |
341 | 342 | ||
343 | #define EXYNOS5_IRQ_SYSMMU_LITE2_0 COMBINER_IRQ(3, 0) | ||
344 | #define EXYNOS5_IRQ_SYSMMU_LITE2_1 COMBINER_IRQ(3, 1) | ||
342 | #define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2) | 345 | #define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2) |
343 | #define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3) | 346 | #define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3) |
344 | #define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4) | 347 | #define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4) |
@@ -362,8 +365,8 @@ | |||
362 | 365 | ||
363 | #define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0) | 366 | #define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0) |
364 | #define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1) | 367 | #define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1) |
365 | #define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(6, 2) | 368 | #define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(6, 2) |
366 | #define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(6, 3) | 369 | #define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(6, 3) |
367 | #define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4) | 370 | #define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4) |
368 | #define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5) | 371 | #define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5) |
369 | #define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6) | 372 | #define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6) |
@@ -375,11 +378,9 @@ | |||
375 | #define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3) | 378 | #define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3) |
376 | #define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4) | 379 | #define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4) |
377 | #define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5) | 380 | #define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5) |
378 | #define EXYNOS5_IRQ_SYSMMU_GPSX_0 COMBINER_IRQ(7, 6) | ||
379 | #define EXYNOS5_IRQ_SYSMMU_GPSX_1 COMBINER_IRQ(7, 7) | ||
380 | 381 | ||
381 | #define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(8, 5) | 382 | #define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(8, 5) |
382 | #define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(8, 6) | 383 | #define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(8, 6) |
383 | 384 | ||
384 | #define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4) | 385 | #define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4) |
385 | #define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5) | 386 | #define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5) |
@@ -395,17 +396,24 @@ | |||
395 | #define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6) | 396 | #define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6) |
396 | #define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7) | 397 | #define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7) |
397 | 398 | ||
399 | #define EXYNOS5_IRQ_MDMA1_ABORT COMBINER_IRQ(13, 1) | ||
400 | |||
401 | #define EXYNOS5_IRQ_MDMA0_ABORT COMBINER_IRQ(15, 3) | ||
402 | |||
398 | #define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4) | 403 | #define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4) |
399 | #define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5) | 404 | #define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5) |
400 | #define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6) | 405 | #define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6) |
401 | 406 | ||
407 | #define EXYNOS5_IRQ_ARMIOP_GIC COMBINER_IRQ(19, 0) | ||
408 | #define EXYNOS5_IRQ_ARMISP_GIC COMBINER_IRQ(19, 1) | ||
409 | #define EXYNOS5_IRQ_IOP_GIC COMBINER_IRQ(19, 3) | ||
410 | #define EXYNOS5_IRQ_ISP_GIC COMBINER_IRQ(19, 4) | ||
411 | |||
412 | #define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4) | ||
413 | |||
402 | #define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0) | 414 | #define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0) |
403 | #define EXYNOS5_IRQ_MCT_L0 COMBINER_IRQ(23, 1) | ||
404 | #define EXYNOS5_IRQ_MCT_L1 COMBINER_IRQ(23, 2) | ||
405 | #define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3) | 415 | #define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3) |
406 | #define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4) | 416 | #define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4) |
407 | #define EXYNOS5_IRQ_MCT_G2 COMBINER_IRQ(23, 5) | ||
408 | #define EXYNOS5_IRQ_MCT_G3 COMBINER_IRQ(23, 6) | ||
409 | 417 | ||
410 | #define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0) | 418 | #define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0) |
411 | #define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1) | 419 | #define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1) |
@@ -436,7 +444,7 @@ | |||
436 | 444 | ||
437 | #define EXYNOS5_MAX_COMBINER_NR 32 | 445 | #define EXYNOS5_MAX_COMBINER_NR 32 |
438 | 446 | ||
439 | #define EXYNOS5_IRQ_GPIO1_NR_GROUPS 13 | 447 | #define EXYNOS5_IRQ_GPIO1_NR_GROUPS 14 |
440 | #define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9 | 448 | #define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9 |
441 | #define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5 | 449 | #define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5 |
442 | #define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1 | 450 | #define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1 |
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 2196af2d8218..ca4aa89aa46b 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h | |||
@@ -34,6 +34,9 @@ | |||
34 | 34 | ||
35 | #define EXYNOS4_PA_JPEG 0x11840000 | 35 | #define EXYNOS4_PA_JPEG 0x11840000 |
36 | 36 | ||
37 | /* x = 0...1 */ | ||
38 | #define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000)) | ||
39 | |||
37 | #define EXYNOS4_PA_G2D 0x12800000 | 40 | #define EXYNOS4_PA_G2D 0x12800000 |
38 | 41 | ||
39 | #define EXYNOS4_PA_I2S0 0x03830000 | 42 | #define EXYNOS4_PA_I2S0 0x03830000 |
@@ -78,8 +81,8 @@ | |||
78 | 81 | ||
79 | #define EXYNOS4_PA_GIC_CPU 0x10480000 | 82 | #define EXYNOS4_PA_GIC_CPU 0x10480000 |
80 | #define EXYNOS4_PA_GIC_DIST 0x10490000 | 83 | #define EXYNOS4_PA_GIC_DIST 0x10490000 |
81 | #define EXYNOS5_PA_GIC_CPU 0x10480000 | 84 | #define EXYNOS5_PA_GIC_CPU 0x10482000 |
82 | #define EXYNOS5_PA_GIC_DIST 0x10490000 | 85 | #define EXYNOS5_PA_GIC_DIST 0x10481000 |
83 | 86 | ||
84 | #define EXYNOS4_PA_COREPERI 0x10500000 | 87 | #define EXYNOS4_PA_COREPERI 0x10500000 |
85 | #define EXYNOS4_PA_TWD 0x10500600 | 88 | #define EXYNOS4_PA_TWD 0x10500600 |
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index dba83e91f0fd..b78b5f3ad9c0 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h | |||
@@ -322,6 +322,8 @@ | |||
322 | #define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200) | 322 | #define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200) |
323 | #define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500) | 323 | #define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500) |
324 | 324 | ||
325 | #define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24) | ||
326 | |||
325 | #define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030) | 327 | #define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030) |
326 | 328 | ||
327 | #define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) | 329 | #define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) |
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h index d457d052a420..4dbb8629b200 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h | |||
@@ -180,7 +180,7 @@ | |||
180 | 180 | ||
181 | #define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) | 181 | #define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) |
182 | 182 | ||
183 | /* Only for EXYNOS4212 */ | 183 | /* Only for EXYNOS4x12 */ |
184 | #define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050) | 184 | #define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050) |
185 | #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054) | 185 | #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054) |
186 | #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058) | 186 | #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058) |
@@ -221,4 +221,12 @@ | |||
221 | #define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8) | 221 | #define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8) |
222 | #define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48) | 222 | #define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48) |
223 | 223 | ||
224 | /* Only for EXYNOS4412 */ | ||
225 | #define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020) | ||
226 | #define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024) | ||
227 | #define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028) | ||
228 | #define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030) | ||
229 | #define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034) | ||
230 | #define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038) | ||
231 | |||
224 | #endif /* __ASM_ARCH_REGS_PMU_H */ | 232 | #endif /* __ASM_ARCH_REGS_PMU_H */ |
diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h index 576efdf6d091..c71a5fba6a84 100644 --- a/arch/arm/mach-exynos/include/mach/spi-clocks.h +++ b/arch/arm/mach-exynos/include/mach/spi-clocks.h | |||
@@ -11,6 +11,6 @@ | |||
11 | #define __ASM_ARCH_SPI_CLKS_H __FILE__ | 11 | #define __ASM_ARCH_SPI_CLKS_H __FILE__ |
12 | 12 | ||
13 | /* Must source from SCLK_SPI */ | 13 | /* Must source from SCLK_SPI */ |
14 | #define EXYNOS4_SPI_SRCCLK_SCLK 0 | 14 | #define EXYNOS_SPI_SRCCLK_SCLK 0 |
15 | 15 | ||
16 | #endif /* __ASM_ARCH_SPI_CLKS_H */ | 16 | #endif /* __ASM_ARCH_SPI_CLKS_H */ |
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 4711c8920e37..cf5d2228e998 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c | |||
@@ -43,6 +43,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { | |||
43 | "exynos4210-uart.2", NULL), | 43 | "exynos4210-uart.2", NULL), |
44 | OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3, | 44 | OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3, |
45 | "exynos4210-uart.3", NULL), | 45 | "exynos4210-uart.3", NULL), |
46 | OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0), | ||
47 | "s3c2440-i2c.0", NULL), | ||
48 | OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1), | ||
49 | "s3c2440-i2c.1", NULL), | ||
46 | OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), | 50 | OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), |
47 | OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), | 51 | OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), |
48 | OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), | 52 | OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), |
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c index 897d9a9cf226..b601fb8a408b 100644 --- a/arch/arm/mach-exynos/mct.c +++ b/arch/arm/mach-exynos/mct.c | |||
@@ -388,6 +388,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) | |||
388 | { | 388 | { |
389 | struct mct_clock_event_device *mevt; | 389 | struct mct_clock_event_device *mevt; |
390 | unsigned int cpu = smp_processor_id(); | 390 | unsigned int cpu = smp_processor_id(); |
391 | int mct_lx_irq; | ||
391 | 392 | ||
392 | mevt = this_cpu_ptr(&percpu_mct_tick); | 393 | mevt = this_cpu_ptr(&percpu_mct_tick); |
393 | mevt->evt = evt; | 394 | mevt->evt = evt; |
@@ -414,14 +415,18 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) | |||
414 | 415 | ||
415 | if (mct_int_type == MCT_INT_SPI) { | 416 | if (mct_int_type == MCT_INT_SPI) { |
416 | if (cpu == 0) { | 417 | if (cpu == 0) { |
418 | mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 : | ||
419 | EXYNOS5_IRQ_MCT_L0; | ||
417 | mct_tick0_event_irq.dev_id = mevt; | 420 | mct_tick0_event_irq.dev_id = mevt; |
418 | evt->irq = EXYNOS4_IRQ_MCT_L0; | 421 | evt->irq = mct_lx_irq; |
419 | setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq); | 422 | setup_irq(mct_lx_irq, &mct_tick0_event_irq); |
420 | } else { | 423 | } else { |
424 | mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 : | ||
425 | EXYNOS5_IRQ_MCT_L1; | ||
421 | mct_tick1_event_irq.dev_id = mevt; | 426 | mct_tick1_event_irq.dev_id = mevt; |
422 | evt->irq = EXYNOS4_IRQ_MCT_L1; | 427 | evt->irq = mct_lx_irq; |
423 | setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq); | 428 | setup_irq(mct_lx_irq, &mct_tick1_event_irq); |
424 | irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1)); | 429 | irq_set_affinity(mct_lx_irq, cpumask_of(1)); |
425 | } | 430 | } |
426 | } else { | 431 | } else { |
427 | enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0); | 432 | enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0); |
@@ -473,7 +478,7 @@ static void __init exynos4_timer_resources(void) | |||
473 | 478 | ||
474 | static void __init exynos4_timer_init(void) | 479 | static void __init exynos4_timer_init(void) |
475 | { | 480 | { |
476 | if (soc_is_exynos4210()) | 481 | if ((soc_is_exynos4210()) || (soc_is_exynos5250())) |
477 | mct_int_type = MCT_INT_SPI; | 482 | mct_int_type = MCT_INT_SPI; |
478 | else | 483 | else |
479 | mct_int_type = MCT_INT_PPI; | 484 | mct_int_type = MCT_INT_PPI; |
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 428cfeb57724..563dea9a6dbb 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c | |||
@@ -275,7 +275,7 @@ static void exynos4_restore_pll(void) | |||
275 | 275 | ||
276 | static struct subsys_interface exynos4_pm_interface = { | 276 | static struct subsys_interface exynos4_pm_interface = { |
277 | .name = "exynos4_pm", | 277 | .name = "exynos4_pm", |
278 | .subsys = &exynos4_subsys, | 278 | .subsys = &exynos_subsys, |
279 | .add_dev = exynos4_pm_add, | 279 | .add_dev = exynos4_pm_add, |
280 | }; | 280 | }; |
281 | 281 | ||
@@ -313,7 +313,7 @@ static int exynos4_pm_suspend(void) | |||
313 | tmp &= ~S5P_CENTRAL_LOWPWR_CFG; | 313 | tmp &= ~S5P_CENTRAL_LOWPWR_CFG; |
314 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); | 314 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); |
315 | 315 | ||
316 | if (soc_is_exynos4212()) { | 316 | if (soc_is_exynos4212() || soc_is_exynos4412()) { |
317 | tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION); | 317 | tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION); |
318 | tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM | | 318 | tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM | |
319 | S5P_USE_STANDBYWFE_ISP_ARM); | 319 | S5P_USE_STANDBYWFE_ISP_ARM); |
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index bba48f5c3e8f..77c6815eebee 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c | |||
@@ -94,7 +94,7 @@ static struct exynos4_pmu_conf exynos4210_pmu_config[] = { | |||
94 | { PMU_TABLE_END,}, | 94 | { PMU_TABLE_END,}, |
95 | }; | 95 | }; |
96 | 96 | ||
97 | static struct exynos4_pmu_conf exynos4212_pmu_config[] = { | 97 | static struct exynos4_pmu_conf exynos4x12_pmu_config[] = { |
98 | { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, | 98 | { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, |
99 | { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, | 99 | { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, |
100 | { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, | 100 | { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, |
@@ -202,6 +202,16 @@ static struct exynos4_pmu_conf exynos4212_pmu_config[] = { | |||
202 | { PMU_TABLE_END,}, | 202 | { PMU_TABLE_END,}, |
203 | }; | 203 | }; |
204 | 204 | ||
205 | static struct exynos4_pmu_conf exynos4412_pmu_config[] = { | ||
206 | { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } }, | ||
207 | { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } }, | ||
208 | { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } }, | ||
209 | { S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } }, | ||
210 | { S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } }, | ||
211 | { S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } }, | ||
212 | { PMU_TABLE_END,}, | ||
213 | }; | ||
214 | |||
205 | void exynos4_sys_powerdown_conf(enum sys_powerdown mode) | 215 | void exynos4_sys_powerdown_conf(enum sys_powerdown mode) |
206 | { | 216 | { |
207 | unsigned int i; | 217 | unsigned int i; |
@@ -209,6 +219,12 @@ void exynos4_sys_powerdown_conf(enum sys_powerdown mode) | |||
209 | for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++) | 219 | for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++) |
210 | __raw_writel(exynos4_pmu_config[i].val[mode], | 220 | __raw_writel(exynos4_pmu_config[i].val[mode], |
211 | exynos4_pmu_config[i].reg); | 221 | exynos4_pmu_config[i].reg); |
222 | |||
223 | if (soc_is_exynos4412()) { | ||
224 | for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++) | ||
225 | __raw_writel(exynos4412_pmu_config[i].val[mode], | ||
226 | exynos4412_pmu_config[i].reg); | ||
227 | } | ||
212 | } | 228 | } |
213 | 229 | ||
214 | static int __init exynos4_pmu_init(void) | 230 | static int __init exynos4_pmu_init(void) |
@@ -218,9 +234,9 @@ static int __init exynos4_pmu_init(void) | |||
218 | if (soc_is_exynos4210()) { | 234 | if (soc_is_exynos4210()) { |
219 | exynos4_pmu_config = exynos4210_pmu_config; | 235 | exynos4_pmu_config = exynos4210_pmu_config; |
220 | pr_info("EXYNOS4210 PMU Initialize\n"); | 236 | pr_info("EXYNOS4210 PMU Initialize\n"); |
221 | } else if (soc_is_exynos4212()) { | 237 | } else if (soc_is_exynos4212() || soc_is_exynos4412()) { |
222 | exynos4_pmu_config = exynos4212_pmu_config; | 238 | exynos4_pmu_config = exynos4x12_pmu_config; |
223 | pr_info("EXYNOS4212 PMU Initialize\n"); | 239 | pr_info("EXYNOS4x12 PMU Initialize\n"); |
224 | } else { | 240 | } else { |
225 | pr_info("EXYNOS4: PMU not supported\n"); | 241 | pr_info("EXYNOS4: PMU not supported\n"); |
226 | } | 242 | } |
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index b34287ab5afd..e24961109b70 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig | |||
@@ -518,6 +518,11 @@ config S3C2443_DMA | |||
518 | help | 518 | help |
519 | Internal config node for S3C2443 DMA support | 519 | Internal config node for S3C2443 DMA support |
520 | 520 | ||
521 | config S3C2443_SETUP_SPI | ||
522 | bool | ||
523 | help | ||
524 | Common setup code for SPI GPIO configurations | ||
525 | |||
521 | endif # CPU_S3C2443 || CPU_S3C2416 | 526 | endif # CPU_S3C2443 || CPU_S3C2416 |
522 | 527 | ||
523 | if CPU_S3C2443 | 528 | if CPU_S3C2443 |
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile index 270a0b6f4f22..0ab6ab15da4c 100644 --- a/arch/arm/mach-s3c24xx/Makefile +++ b/arch/arm/mach-s3c24xx/Makefile | |||
@@ -97,5 +97,6 @@ obj-$(CONFIG_MACH_OSIRIS_DVS) += mach-osiris-dvs.o | |||
97 | # device setup | 97 | # device setup |
98 | 98 | ||
99 | obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o | 99 | obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o |
100 | obj-$(CONFIG_S3C2443_SETUP_SPI) += setup-spi.o | ||
100 | obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c.o | 101 | obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c.o |
101 | obj-$(CONFIG_S3C24XX_SETUP_TS) += setup-ts.o | 102 | obj-$(CONFIG_S3C24XX_SETUP_TS) += setup-ts.o |
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c index dbc9ab4aaca2..8702ecfaab30 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2416.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c | |||
@@ -144,6 +144,7 @@ static struct clk_lookup s3c2416_clk_lookup[] = { | |||
144 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk), | 144 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk), |
145 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk), | 145 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk), |
146 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk), | 146 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk), |
147 | CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk), | ||
147 | }; | 148 | }; |
148 | 149 | ||
149 | void __init s3c2416_init_clocks(int xtal) | 150 | void __init s3c2416_init_clocks(int xtal) |
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c index efb3ac359566..a4c5a520d994 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2443.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c | |||
@@ -179,6 +179,11 @@ static struct clk *clks[] __initdata = { | |||
179 | &clk_hsmmc, | 179 | &clk_hsmmc, |
180 | }; | 180 | }; |
181 | 181 | ||
182 | static struct clk_lookup s3c2443_clk_lookup[] = { | ||
183 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc), | ||
184 | CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk), | ||
185 | }; | ||
186 | |||
182 | void __init s3c2443_init_clocks(int xtal) | 187 | void __init s3c2443_init_clocks(int xtal) |
183 | { | 188 | { |
184 | unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); | 189 | unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); |
@@ -210,6 +215,7 @@ void __init s3c2443_init_clocks(int xtal) | |||
210 | 215 | ||
211 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | 216 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
212 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | 217 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
218 | clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup)); | ||
213 | 219 | ||
214 | s3c_pwmclk_init(); | 220 | s3c_pwmclk_init(); |
215 | } | 221 | } |
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c index 460431589f39..aeeb2be283fa 100644 --- a/arch/arm/mach-s3c24xx/common-s3c2443.c +++ b/arch/arm/mach-s3c24xx/common-s3c2443.c | |||
@@ -424,11 +424,6 @@ static struct clk init_clocks_off[] = { | |||
424 | .enable = s3c2443_clkcon_enable_p, | 424 | .enable = s3c2443_clkcon_enable_p, |
425 | .ctrlbit = S3C2443_PCLKCON_IIS, | 425 | .ctrlbit = S3C2443_PCLKCON_IIS, |
426 | }, { | 426 | }, { |
427 | .name = "hsspi", | ||
428 | .parent = &clk_p, | ||
429 | .enable = s3c2443_clkcon_enable_p, | ||
430 | .ctrlbit = S3C2443_PCLKCON_HSSPI, | ||
431 | }, { | ||
432 | .name = "adc", | 427 | .name = "adc", |
433 | .parent = &clk_p, | 428 | .parent = &clk_p, |
434 | .enable = s3c2443_clkcon_enable_p, | 429 | .enable = s3c2443_clkcon_enable_p, |
@@ -562,6 +557,14 @@ static struct clk hsmmc1_clk = { | |||
562 | .ctrlbit = S3C2443_HCLKCON_HSMMC, | 557 | .ctrlbit = S3C2443_HCLKCON_HSMMC, |
563 | }; | 558 | }; |
564 | 559 | ||
560 | static struct clk hsspi_clk = { | ||
561 | .name = "spi", | ||
562 | .devname = "s3c64xx-spi.0", | ||
563 | .parent = &clk_p, | ||
564 | .enable = s3c2443_clkcon_enable_p, | ||
565 | .ctrlbit = S3C2443_PCLKCON_HSSPI, | ||
566 | }; | ||
567 | |||
565 | /* EPLLCON compatible enough to get on/off information */ | 568 | /* EPLLCON compatible enough to get on/off information */ |
566 | 569 | ||
567 | void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll) | 570 | void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll) |
@@ -612,6 +615,7 @@ static struct clk *clks[] __initdata = { | |||
612 | &clk_usb_bus, | 615 | &clk_usb_bus, |
613 | &clk_armdiv, | 616 | &clk_armdiv, |
614 | &hsmmc1_clk, | 617 | &hsmmc1_clk, |
618 | &hsspi_clk, | ||
615 | }; | 619 | }; |
616 | 620 | ||
617 | static struct clksrc_clk *clksrcs[] __initdata = { | 621 | static struct clksrc_clk *clksrcs[] __initdata = { |
@@ -629,6 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = { | |||
629 | CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), | 633 | CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), |
630 | CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), | 634 | CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), |
631 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk), | 635 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk), |
636 | CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk), | ||
632 | }; | 637 | }; |
633 | 638 | ||
634 | void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, | 639 | void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, |
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c index e227c472a40a..2d94228d2866 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2443.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c | |||
@@ -55,12 +55,20 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = { | |||
55 | .name = "sdi", | 55 | .name = "sdi", |
56 | .channels = MAP(S3C2443_DMAREQSEL_SDI), | 56 | .channels = MAP(S3C2443_DMAREQSEL_SDI), |
57 | }, | 57 | }, |
58 | [DMACH_SPI0] = { | 58 | [DMACH_SPI0_RX] = { |
59 | .name = "spi0", | 59 | .name = "spi0-rx", |
60 | .channels = MAP(S3C2443_DMAREQSEL_SPI0RX), | ||
61 | }, | ||
62 | [DMACH_SPI0_TX] = { | ||
63 | .name = "spi0-tx", | ||
60 | .channels = MAP(S3C2443_DMAREQSEL_SPI0TX), | 64 | .channels = MAP(S3C2443_DMAREQSEL_SPI0TX), |
61 | }, | 65 | }, |
62 | [DMACH_SPI1] = { /* only on S3C2443/S3C2450 */ | 66 | [DMACH_SPI1_RX] = { /* only on S3C2443/S3C2450 */ |
63 | .name = "spi1", | 67 | .name = "spi1-rx", |
68 | .channels = MAP(S3C2443_DMAREQSEL_SPI1RX), | ||
69 | }, | ||
70 | [DMACH_SPI1_TX] = { /* only on S3C2443/S3C2450 */ | ||
71 | .name = "spi1-tx", | ||
64 | .channels = MAP(S3C2443_DMAREQSEL_SPI1TX), | 72 | .channels = MAP(S3C2443_DMAREQSEL_SPI1TX), |
65 | }, | 73 | }, |
66 | [DMACH_UART0] = { | 74 | [DMACH_UART0] = { |
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h index acbdfecd4186..454831b66037 100644 --- a/arch/arm/mach-s3c24xx/include/mach/dma.h +++ b/arch/arm/mach-s3c24xx/include/mach/dma.h | |||
@@ -47,6 +47,10 @@ enum dma_ch { | |||
47 | DMACH_UART2_SRC2, | 47 | DMACH_UART2_SRC2, |
48 | DMACH_UART3, /* s3c2443 has extra uart */ | 48 | DMACH_UART3, /* s3c2443 has extra uart */ |
49 | DMACH_UART3_SRC2, | 49 | DMACH_UART3_SRC2, |
50 | DMACH_SPI0_TX, /* s3c2443/2416/2450 hsspi0 */ | ||
51 | DMACH_SPI0_RX, /* s3c2443/2416/2450 hsspi0 */ | ||
52 | DMACH_SPI1_TX, /* s3c2443/2450 hsspi1 */ | ||
53 | DMACH_SPI1_RX, /* s3c2443/2450 hsspi1 */ | ||
50 | DMACH_MAX, /* the end entry */ | 54 | DMACH_MAX, /* the end entry */ |
51 | }; | 55 | }; |
52 | 56 | ||
diff --git a/arch/arm/mach-s3c24xx/include/mach/map.h b/arch/arm/mach-s3c24xx/include/mach/map.h index 78ae807f1281..8ba381f2dbe1 100644 --- a/arch/arm/mach-s3c24xx/include/mach/map.h +++ b/arch/arm/mach-s3c24xx/include/mach/map.h | |||
@@ -98,6 +98,8 @@ | |||
98 | 98 | ||
99 | /* SPI */ | 99 | /* SPI */ |
100 | #define S3C2410_PA_SPI (0x59000000) | 100 | #define S3C2410_PA_SPI (0x59000000) |
101 | #define S3C2443_PA_SPI0 (0x52000000) | ||
102 | #define S3C2443_PA_SPI1 S3C2410_PA_SPI | ||
101 | 103 | ||
102 | /* SDI */ | 104 | /* SDI */ |
103 | #define S3C2410_PA_SDI (0x5A000000) | 105 | #define S3C2410_PA_SDI (0x5A000000) |
@@ -162,4 +164,7 @@ | |||
162 | #define S3C_PA_WDT S3C2410_PA_WATCHDOG | 164 | #define S3C_PA_WDT S3C2410_PA_WATCHDOG |
163 | #define S3C_PA_NAND S3C24XX_PA_NAND | 165 | #define S3C_PA_NAND S3C24XX_PA_NAND |
164 | 166 | ||
167 | #define S3C_PA_SPI0 S3C2443_PA_SPI0 | ||
168 | #define S3C_PA_SPI1 S3C2443_PA_SPI1 | ||
169 | |||
165 | #endif /* __ASM_ARCH_MAP_H */ | 170 | #endif /* __ASM_ARCH_MAP_H */ |
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c new file mode 100644 index 000000000000..5712c85f39b1 --- /dev/null +++ b/arch/arm/mach-s3c24xx/setup-spi.c | |||
@@ -0,0 +1,39 @@ | |||
1 | /* | ||
2 | * HS-SPI device setup for S3C2443/S3C2416 | ||
3 | * | ||
4 | * Copyright (C) 2011 Samsung Electronics Ltd. | ||
5 | * http://www.samsung.com/ | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #include <linux/gpio.h> | ||
13 | #include <linux/platform_device.h> | ||
14 | |||
15 | #include <plat/gpio-cfg.h> | ||
16 | #include <plat/s3c64xx-spi.h> | ||
17 | |||
18 | #include <mach/hardware.h> | ||
19 | #include <mach/regs-gpio.h> | ||
20 | |||
21 | #ifdef CONFIG_S3C64XX_DEV_SPI0 | ||
22 | struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { | ||
23 | .fifo_lvl_mask = 0x7f, | ||
24 | .rx_lvl_offset = 13, | ||
25 | .tx_st_done = 21, | ||
26 | .high_speed = 1, | ||
27 | }; | ||
28 | |||
29 | int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev) | ||
30 | { | ||
31 | /* enable hsspi bit in misccr */ | ||
32 | s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1); | ||
33 | |||
34 | s3c_gpio_cfgall_range(S3C2410_GPE(11), 3, | ||
35 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | ||
36 | |||
37 | return 0; | ||
38 | } | ||
39 | #endif | ||
diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig new file mode 100644 index 000000000000..eaadc66d96b3 --- /dev/null +++ b/arch/arm/mach-spear13xx/Kconfig | |||
@@ -0,0 +1,20 @@ | |||
1 | # | ||
2 | # SPEAr13XX Machine configuration file | ||
3 | # | ||
4 | |||
5 | if ARCH_SPEAR13XX | ||
6 | |||
7 | menu "SPEAr13xx Implementations" | ||
8 | config MACH_SPEAR1310 | ||
9 | bool "SPEAr1310 Machine support with Device Tree" | ||
10 | select PINCTRL_SPEAR1310 | ||
11 | help | ||
12 | Supports ST SPEAr1310 machine configured via the device-tree | ||
13 | |||
14 | config MACH_SPEAR1340 | ||
15 | bool "SPEAr1340 Machine support with Device Tree" | ||
16 | select PINCTRL_SPEAR1340 | ||
17 | help | ||
18 | Supports ST SPEAr1340 machine configured via the device-tree | ||
19 | endmenu | ||
20 | endif #ARCH_SPEAR13XX | ||
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile new file mode 100644 index 000000000000..3435ea78c15d --- /dev/null +++ b/arch/arm/mach-spear13xx/Makefile | |||
@@ -0,0 +1,10 @@ | |||
1 | # | ||
2 | # Makefile for SPEAr13XX machine series | ||
3 | # | ||
4 | |||
5 | obj-$(CONFIG_SMP) += headsmp.o platsmp.o | ||
6 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | ||
7 | |||
8 | obj-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o | ||
9 | obj-$(CONFIG_MACH_SPEAR1310) += spear1310.o | ||
10 | obj-$(CONFIG_MACH_SPEAR1340) += spear1340.o | ||
diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear13xx/Makefile.boot new file mode 100644 index 000000000000..403efd7e6d27 --- /dev/null +++ b/arch/arm/mach-spear13xx/Makefile.boot | |||
@@ -0,0 +1,6 @@ | |||
1 | zreladdr-y += 0x00008000 | ||
2 | params_phys-y := 0x00000100 | ||
3 | initrd_phys-y := 0x00800000 | ||
4 | |||
5 | dtb-$(CONFIG_MACH_SPEAR1310) += spear1310-evb.dtb | ||
6 | dtb-$(CONFIG_MACH_SPEAR1340) += spear1340-evb.dtb | ||
diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear13xx/headsmp.S new file mode 100644 index 000000000000..ed85473a047f --- /dev/null +++ b/arch/arm/mach-spear13xx/headsmp.S | |||
@@ -0,0 +1,47 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear13XX/headsmp.S | ||
3 | * | ||
4 | * Picked from realview | ||
5 | * Copyright (c) 2012 ST Microelectronics Limited | ||
6 | * Shiraz Hashim <shiraz.hashim@st.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/linkage.h> | ||
14 | #include <linux/init.h> | ||
15 | |||
16 | __INIT | ||
17 | |||
18 | /* | ||
19 | * spear13xx specific entry point for secondary CPUs. This provides | ||
20 | * a "holding pen" into which all secondary cores are held until we're | ||
21 | * ready for them to initialise. | ||
22 | */ | ||
23 | ENTRY(spear13xx_secondary_startup) | ||
24 | mrc p15, 0, r0, c0, c0, 5 | ||
25 | and r0, r0, #15 | ||
26 | adr r4, 1f | ||
27 | ldmia r4, {r5, r6} | ||
28 | sub r4, r4, r5 | ||
29 | add r6, r6, r4 | ||
30 | pen: ldr r7, [r6] | ||
31 | cmp r7, r0 | ||
32 | bne pen | ||
33 | |||
34 | /* re-enable coherency */ | ||
35 | mrc p15, 0, r0, c1, c0, 1 | ||
36 | orr r0, r0, #(1 << 6) | (1 << 0) | ||
37 | mcr p15, 0, r0, c1, c0, 1 | ||
38 | /* | ||
39 | * we've been released from the holding pen: secondary_stack | ||
40 | * should now contain the SVC stack for this core | ||
41 | */ | ||
42 | b secondary_startup | ||
43 | |||
44 | .align | ||
45 | 1: .long . | ||
46 | .long pen_release | ||
47 | ENDPROC(spear13xx_secondary_startup) | ||
diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear13xx/hotplug.c new file mode 100644 index 000000000000..5c6867b46d09 --- /dev/null +++ b/arch/arm/mach-spear13xx/hotplug.c | |||
@@ -0,0 +1,119 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-spear13xx/hotplug.c | ||
3 | * | ||
4 | * Copyright (C) 2012 ST Microelectronics Ltd. | ||
5 | * Deepak Sikri <deepak.sikri@st.com> | ||
6 | * | ||
7 | * based upon linux/arch/arm/mach-realview/hotplug.c | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/errno.h> | ||
15 | #include <linux/smp.h> | ||
16 | #include <asm/cacheflush.h> | ||
17 | #include <asm/cp15.h> | ||
18 | #include <asm/smp_plat.h> | ||
19 | |||
20 | extern volatile int pen_release; | ||
21 | |||
22 | static inline void cpu_enter_lowpower(void) | ||
23 | { | ||
24 | unsigned int v; | ||
25 | |||
26 | flush_cache_all(); | ||
27 | asm volatile( | ||
28 | " mcr p15, 0, %1, c7, c5, 0\n" | ||
29 | " dsb\n" | ||
30 | /* | ||
31 | * Turn off coherency | ||
32 | */ | ||
33 | " mrc p15, 0, %0, c1, c0, 1\n" | ||
34 | " bic %0, %0, #0x20\n" | ||
35 | " mcr p15, 0, %0, c1, c0, 1\n" | ||
36 | " mrc p15, 0, %0, c1, c0, 0\n" | ||
37 | " bic %0, %0, %2\n" | ||
38 | " mcr p15, 0, %0, c1, c0, 0\n" | ||
39 | : "=&r" (v) | ||
40 | : "r" (0), "Ir" (CR_C) | ||
41 | : "cc", "memory"); | ||
42 | } | ||
43 | |||
44 | static inline void cpu_leave_lowpower(void) | ||
45 | { | ||
46 | unsigned int v; | ||
47 | |||
48 | asm volatile("mrc p15, 0, %0, c1, c0, 0\n" | ||
49 | " orr %0, %0, %1\n" | ||
50 | " mcr p15, 0, %0, c1, c0, 0\n" | ||
51 | " mrc p15, 0, %0, c1, c0, 1\n" | ||
52 | " orr %0, %0, #0x20\n" | ||
53 | " mcr p15, 0, %0, c1, c0, 1\n" | ||
54 | : "=&r" (v) | ||
55 | : "Ir" (CR_C) | ||
56 | : "cc"); | ||
57 | } | ||
58 | |||
59 | static inline void platform_do_lowpower(unsigned int cpu, int *spurious) | ||
60 | { | ||
61 | for (;;) { | ||
62 | wfi(); | ||
63 | |||
64 | if (pen_release == cpu) { | ||
65 | /* | ||
66 | * OK, proper wakeup, we're done | ||
67 | */ | ||
68 | break; | ||
69 | } | ||
70 | |||
71 | /* | ||
72 | * Getting here, means that we have come out of WFI without | ||
73 | * having been woken up - this shouldn't happen | ||
74 | * | ||
75 | * Just note it happening - when we're woken, we can report | ||
76 | * its occurrence. | ||
77 | */ | ||
78 | (*spurious)++; | ||
79 | } | ||
80 | } | ||
81 | |||
82 | int platform_cpu_kill(unsigned int cpu) | ||
83 | { | ||
84 | return 1; | ||
85 | } | ||
86 | |||
87 | /* | ||
88 | * platform-specific code to shutdown a CPU | ||
89 | * | ||
90 | * Called with IRQs disabled | ||
91 | */ | ||
92 | void __cpuinit platform_cpu_die(unsigned int cpu) | ||
93 | { | ||
94 | int spurious = 0; | ||
95 | |||
96 | /* | ||
97 | * we're ready for shutdown now, so do it | ||
98 | */ | ||
99 | cpu_enter_lowpower(); | ||
100 | platform_do_lowpower(cpu, &spurious); | ||
101 | |||
102 | /* | ||
103 | * bring this CPU back into the world of cache | ||
104 | * coherency, and then restore interrupts | ||
105 | */ | ||
106 | cpu_leave_lowpower(); | ||
107 | |||
108 | if (spurious) | ||
109 | pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); | ||
110 | } | ||
111 | |||
112 | int platform_cpu_disable(unsigned int cpu) | ||
113 | { | ||
114 | /* | ||
115 | * we don't allow CPU 0 to be shutdown (it is still too special | ||
116 | * e.g. clock tick interrupts) | ||
117 | */ | ||
118 | return cpu == 0 ? -EPERM : 0; | ||
119 | } | ||
diff --git a/arch/arm/mach-spear13xx/include/mach/debug-macro.S b/arch/arm/mach-spear13xx/include/mach/debug-macro.S new file mode 100644 index 000000000000..ea1564609bd4 --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/debug-macro.S | |||
@@ -0,0 +1,14 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear13xx/include/mach/debug-macro.S | ||
3 | * | ||
4 | * Debugging macro include header spear13xx machine family | ||
5 | * | ||
6 | * Copyright (C) 2012 ST Microelectronics | ||
7 | * Viresh Kumar <viresh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #include <plat/debug-macro.S> | ||
diff --git a/arch/arm/mach-spear13xx/include/mach/dma.h b/arch/arm/mach-spear13xx/include/mach/dma.h new file mode 100644 index 000000000000..383ab04dc6c9 --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/dma.h | |||
@@ -0,0 +1,128 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear13xx/include/mach/dma.h | ||
3 | * | ||
4 | * DMA information for SPEAr13xx machine family | ||
5 | * | ||
6 | * Copyright (C) 2012 ST Microelectronics | ||
7 | * Viresh Kumar <viresh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_DMA_H | ||
15 | #define __MACH_DMA_H | ||
16 | |||
17 | /* request id of all the peripherals */ | ||
18 | enum dma_master_info { | ||
19 | /* Accessible from only one master */ | ||
20 | DMA_MASTER_MCIF = 0, | ||
21 | DMA_MASTER_FSMC = 1, | ||
22 | /* Accessible from both 0 & 1 */ | ||
23 | DMA_MASTER_MEMORY = 0, | ||
24 | DMA_MASTER_ADC = 0, | ||
25 | DMA_MASTER_UART0 = 0, | ||
26 | DMA_MASTER_SSP0 = 0, | ||
27 | DMA_MASTER_I2C0 = 0, | ||
28 | |||
29 | #ifdef CONFIG_MACH_SPEAR1310 | ||
30 | /* Accessible from only one master */ | ||
31 | SPEAR1310_DMA_MASTER_JPEG = 1, | ||
32 | |||
33 | /* Accessible from both 0 & 1 */ | ||
34 | SPEAR1310_DMA_MASTER_I2S = 0, | ||
35 | SPEAR1310_DMA_MASTER_UART1 = 0, | ||
36 | SPEAR1310_DMA_MASTER_UART2 = 0, | ||
37 | SPEAR1310_DMA_MASTER_UART3 = 0, | ||
38 | SPEAR1310_DMA_MASTER_UART4 = 0, | ||
39 | SPEAR1310_DMA_MASTER_UART5 = 0, | ||
40 | SPEAR1310_DMA_MASTER_I2C1 = 0, | ||
41 | SPEAR1310_DMA_MASTER_I2C2 = 0, | ||
42 | SPEAR1310_DMA_MASTER_I2C3 = 0, | ||
43 | SPEAR1310_DMA_MASTER_I2C4 = 0, | ||
44 | SPEAR1310_DMA_MASTER_I2C5 = 0, | ||
45 | SPEAR1310_DMA_MASTER_I2C6 = 0, | ||
46 | SPEAR1310_DMA_MASTER_I2C7 = 0, | ||
47 | SPEAR1310_DMA_MASTER_SSP1 = 0, | ||
48 | #endif | ||
49 | |||
50 | #ifdef CONFIG_MACH_SPEAR1340 | ||
51 | /* Accessible from only one master */ | ||
52 | SPEAR1340_DMA_MASTER_I2S_PLAY = 1, | ||
53 | SPEAR1340_DMA_MASTER_I2S_REC = 1, | ||
54 | SPEAR1340_DMA_MASTER_I2C1 = 1, | ||
55 | SPEAR1340_DMA_MASTER_UART1 = 1, | ||
56 | |||
57 | /* following are accessible from both master 0 & 1 */ | ||
58 | SPEAR1340_DMA_MASTER_SPDIF = 0, | ||
59 | SPEAR1340_DMA_MASTER_CAM = 1, | ||
60 | SPEAR1340_DMA_MASTER_VIDEO_IN = 0, | ||
61 | SPEAR1340_DMA_MASTER_MALI = 0, | ||
62 | #endif | ||
63 | }; | ||
64 | |||
65 | enum request_id { | ||
66 | DMA_REQ_ADC = 0, | ||
67 | DMA_REQ_SSP0_TX = 4, | ||
68 | DMA_REQ_SSP0_RX = 5, | ||
69 | DMA_REQ_UART0_TX = 6, | ||
70 | DMA_REQ_UART0_RX = 7, | ||
71 | DMA_REQ_I2C0_TX = 8, | ||
72 | DMA_REQ_I2C0_RX = 9, | ||
73 | |||
74 | #ifdef CONFIG_MACH_SPEAR1310 | ||
75 | SPEAR1310_DMA_REQ_FROM_JPEG = 2, | ||
76 | SPEAR1310_DMA_REQ_TO_JPEG = 3, | ||
77 | SPEAR1310_DMA_REQ_I2S_TX = 10, | ||
78 | SPEAR1310_DMA_REQ_I2S_RX = 11, | ||
79 | |||
80 | SPEAR1310_DMA_REQ_I2C1_RX = 0, | ||
81 | SPEAR1310_DMA_REQ_I2C1_TX = 1, | ||
82 | SPEAR1310_DMA_REQ_I2C2_RX = 2, | ||
83 | SPEAR1310_DMA_REQ_I2C2_TX = 3, | ||
84 | SPEAR1310_DMA_REQ_I2C3_RX = 4, | ||
85 | SPEAR1310_DMA_REQ_I2C3_TX = 5, | ||
86 | SPEAR1310_DMA_REQ_I2C4_RX = 6, | ||
87 | SPEAR1310_DMA_REQ_I2C4_TX = 7, | ||
88 | SPEAR1310_DMA_REQ_I2C5_RX = 8, | ||
89 | SPEAR1310_DMA_REQ_I2C5_TX = 9, | ||
90 | SPEAR1310_DMA_REQ_I2C6_RX = 10, | ||
91 | SPEAR1310_DMA_REQ_I2C6_TX = 11, | ||
92 | SPEAR1310_DMA_REQ_UART1_RX = 12, | ||
93 | SPEAR1310_DMA_REQ_UART1_TX = 13, | ||
94 | SPEAR1310_DMA_REQ_UART2_RX = 14, | ||
95 | SPEAR1310_DMA_REQ_UART2_TX = 15, | ||
96 | SPEAR1310_DMA_REQ_UART5_RX = 16, | ||
97 | SPEAR1310_DMA_REQ_UART5_TX = 17, | ||
98 | SPEAR1310_DMA_REQ_SSP1_RX = 18, | ||
99 | SPEAR1310_DMA_REQ_SSP1_TX = 19, | ||
100 | SPEAR1310_DMA_REQ_I2C7_RX = 20, | ||
101 | SPEAR1310_DMA_REQ_I2C7_TX = 21, | ||
102 | SPEAR1310_DMA_REQ_UART3_RX = 28, | ||
103 | SPEAR1310_DMA_REQ_UART3_TX = 29, | ||
104 | SPEAR1310_DMA_REQ_UART4_RX = 30, | ||
105 | SPEAR1310_DMA_REQ_UART4_TX = 31, | ||
106 | #endif | ||
107 | |||
108 | #ifdef CONFIG_MACH_SPEAR1340 | ||
109 | SPEAR1340_DMA_REQ_SPDIF_TX = 2, | ||
110 | SPEAR1340_DMA_REQ_SPDIF_RX = 3, | ||
111 | SPEAR1340_DMA_REQ_I2S_TX = 10, | ||
112 | SPEAR1340_DMA_REQ_I2S_RX = 11, | ||
113 | SPEAR1340_DMA_REQ_UART1_TX = 12, | ||
114 | SPEAR1340_DMA_REQ_UART1_RX = 13, | ||
115 | SPEAR1340_DMA_REQ_I2C1_TX = 14, | ||
116 | SPEAR1340_DMA_REQ_I2C1_RX = 15, | ||
117 | SPEAR1340_DMA_REQ_CAM0_EVEN = 0, | ||
118 | SPEAR1340_DMA_REQ_CAM0_ODD = 1, | ||
119 | SPEAR1340_DMA_REQ_CAM1_EVEN = 2, | ||
120 | SPEAR1340_DMA_REQ_CAM1_ODD = 3, | ||
121 | SPEAR1340_DMA_REQ_CAM2_EVEN = 4, | ||
122 | SPEAR1340_DMA_REQ_CAM2_ODD = 5, | ||
123 | SPEAR1340_DMA_REQ_CAM3_EVEN = 6, | ||
124 | SPEAR1340_DMA_REQ_CAM3_ODD = 7, | ||
125 | #endif | ||
126 | }; | ||
127 | |||
128 | #endif /* __MACH_DMA_H */ | ||
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h new file mode 100644 index 000000000000..6d8c45b9f298 --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/generic.h | |||
@@ -0,0 +1,49 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear13xx/include/mach/generic.h | ||
3 | * | ||
4 | * spear13xx machine family generic header file | ||
5 | * | ||
6 | * Copyright (C) 2012 ST Microelectronics | ||
7 | * Viresh Kumar <viresh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_GENERIC_H | ||
15 | #define __MACH_GENERIC_H | ||
16 | |||
17 | #include <linux/dmaengine.h> | ||
18 | #include <asm/mach/time.h> | ||
19 | |||
20 | /* Add spear13xx structure declarations here */ | ||
21 | extern struct sys_timer spear13xx_timer; | ||
22 | extern struct pl022_ssp_controller pl022_plat_data; | ||
23 | extern struct dw_dma_platform_data dmac_plat_data; | ||
24 | extern struct dw_dma_slave cf_dma_priv; | ||
25 | extern struct dw_dma_slave nand_read_dma_priv; | ||
26 | extern struct dw_dma_slave nand_write_dma_priv; | ||
27 | |||
28 | /* Add spear13xx family function declarations here */ | ||
29 | void __init spear_setup_of_timer(void); | ||
30 | void __init spear13xx_map_io(void); | ||
31 | void __init spear13xx_dt_init_irq(void); | ||
32 | void __init spear13xx_l2x0_init(void); | ||
33 | bool dw_dma_filter(struct dma_chan *chan, void *slave); | ||
34 | void spear_restart(char, const char *); | ||
35 | void spear13xx_secondary_startup(void); | ||
36 | |||
37 | #ifdef CONFIG_MACH_SPEAR1310 | ||
38 | void __init spear1310_clk_init(void); | ||
39 | #else | ||
40 | static inline void spear1310_clk_init(void) {} | ||
41 | #endif | ||
42 | |||
43 | #ifdef CONFIG_MACH_SPEAR1340 | ||
44 | void __init spear1340_clk_init(void); | ||
45 | #else | ||
46 | static inline void spear1340_clk_init(void) {} | ||
47 | #endif | ||
48 | |||
49 | #endif /* __MACH_GENERIC_H */ | ||
diff --git a/arch/arm/mach-spear13xx/include/mach/gpio.h b/arch/arm/mach-spear13xx/include/mach/gpio.h new file mode 100644 index 000000000000..cd6f4f86a56b --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/gpio.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear13xx/include/mach/gpio.h | ||
3 | * | ||
4 | * GPIO macros for SPEAr13xx machine family | ||
5 | * | ||
6 | * Copyright (C) 2012 ST Microelectronics | ||
7 | * Viresh Kumar <viresh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_GPIO_H | ||
15 | #define __MACH_GPIO_H | ||
16 | |||
17 | #include <plat/gpio.h> | ||
18 | |||
19 | #endif /* __MACH_GPIO_H */ | ||
diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h new file mode 100644 index 000000000000..40a8c178f10d --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/hardware.h | |||
@@ -0,0 +1 @@ | |||
/* empty */ | |||
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h new file mode 100644 index 000000000000..f542a24aa5f2 --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/irqs.h | |||
@@ -0,0 +1,20 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear13xx/include/mach/irqs.h | ||
3 | * | ||
4 | * IRQ helper macros for spear13xx machine family | ||
5 | * | ||
6 | * Copyright (C) 2012 ST Microelectronics | ||
7 | * Viresh Kumar <viresh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_IRQS_H | ||
15 | #define __MACH_IRQS_H | ||
16 | |||
17 | #define IRQ_GIC_END 160 | ||
18 | #define NR_IRQS IRQ_GIC_END | ||
19 | |||
20 | #endif /* __MACH_IRQS_H */ | ||
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h new file mode 100644 index 000000000000..30c57ef72686 --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/spear.h | |||
@@ -0,0 +1,62 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear13xx/include/mach/spear.h | ||
3 | * | ||
4 | * spear13xx Machine family specific definition | ||
5 | * | ||
6 | * Copyright (C) 2012 ST Microelectronics | ||
7 | * Viresh Kumar <viresh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_SPEAR13XX_H | ||
15 | #define __MACH_SPEAR13XX_H | ||
16 | |||
17 | #include <asm/memory.h> | ||
18 | |||
19 | #define PERIP_GRP2_BASE UL(0xB3000000) | ||
20 | #define VA_PERIP_GRP2_BASE UL(0xFE000000) | ||
21 | #define MCIF_SDHCI_BASE UL(0xB3000000) | ||
22 | #define SYSRAM0_BASE UL(0xB3800000) | ||
23 | #define VA_SYSRAM0_BASE UL(0xFE800000) | ||
24 | #define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600) | ||
25 | |||
26 | #define PERIP_GRP1_BASE UL(0xE0000000) | ||
27 | #define VA_PERIP_GRP1_BASE UL(0xFD000000) | ||
28 | #define UART_BASE UL(0xE0000000) | ||
29 | #define VA_UART_BASE UL(0xFD000000) | ||
30 | #define SSP_BASE UL(0xE0100000) | ||
31 | #define MISC_BASE UL(0xE0700000) | ||
32 | #define VA_MISC_BASE IOMEM(UL(0xFD700000)) | ||
33 | |||
34 | #define A9SM_AND_MPMC_BASE UL(0xEC000000) | ||
35 | #define VA_A9SM_AND_MPMC_BASE UL(0xFC000000) | ||
36 | |||
37 | /* A9SM peripheral offsets */ | ||
38 | #define A9SM_PERIP_BASE UL(0xEC800000) | ||
39 | #define VA_A9SM_PERIP_BASE UL(0xFC800000) | ||
40 | #define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00) | ||
41 | |||
42 | #define L2CC_BASE UL(0xED000000) | ||
43 | #define VA_L2CC_BASE IOMEM(UL(0xFB000000)) | ||
44 | |||
45 | /* others */ | ||
46 | #define DMAC0_BASE UL(0xEA800000) | ||
47 | #define DMAC1_BASE UL(0xEB000000) | ||
48 | #define MCIF_CF_BASE UL(0xB2800000) | ||
49 | |||
50 | /* Devices present in SPEAr1310 */ | ||
51 | #ifdef CONFIG_MACH_SPEAR1310 | ||
52 | #define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000) | ||
53 | #define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000) | ||
54 | #define SPEAR1310_RAS_BASE UL(0xD8400000) | ||
55 | #define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000)) | ||
56 | #endif /* CONFIG_MACH_SPEAR1310 */ | ||
57 | |||
58 | /* Debug uart for linux, will be used for debug and uncompress messages */ | ||
59 | #define SPEAR_DBG_UART_BASE UART_BASE | ||
60 | #define VA_SPEAR_DBG_UART_BASE VA_UART_BASE | ||
61 | |||
62 | #endif /* __MACH_SPEAR13XX_H */ | ||
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h b/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h new file mode 100644 index 000000000000..e69de29bb2d1 --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h | |||
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h b/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h new file mode 100644 index 000000000000..e69de29bb2d1 --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h | |||
diff --git a/arch/arm/mach-spear13xx/include/mach/timex.h b/arch/arm/mach-spear13xx/include/mach/timex.h new file mode 100644 index 000000000000..31af3e8d976e --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/timex.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear3xx/include/mach/timex.h | ||
3 | * | ||
4 | * SPEAr3XX machine family specific timex definitions | ||
5 | * | ||
6 | * Copyright (C) 2012 ST Microelectronics | ||
7 | * Viresh Kumar <viresh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_TIMEX_H | ||
15 | #define __MACH_TIMEX_H | ||
16 | |||
17 | #include <plat/timex.h> | ||
18 | |||
19 | #endif /* __MACH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-spear13xx/include/mach/uncompress.h b/arch/arm/mach-spear13xx/include/mach/uncompress.h new file mode 100644 index 000000000000..c7840896ae6e --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/uncompress.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear13xx/include/mach/uncompress.h | ||
3 | * | ||
4 | * Serial port stubs for kernel decompress status messages | ||
5 | * | ||
6 | * Copyright (C) 2012 ST Microelectronics | ||
7 | * Viresh Kumar <viresh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_UNCOMPRESS_H | ||
15 | #define __MACH_UNCOMPRESS_H | ||
16 | |||
17 | #include <plat/uncompress.h> | ||
18 | |||
19 | #endif /* __MACH_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c new file mode 100644 index 000000000000..f5d07f2663d7 --- /dev/null +++ b/arch/arm/mach-spear13xx/platsmp.c | |||
@@ -0,0 +1,127 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear13xx/platsmp.c | ||
3 | * | ||
4 | * based upon linux/arch/arm/mach-realview/platsmp.c | ||
5 | * | ||
6 | * Copyright (C) 2012 ST Microelectronics Ltd. | ||
7 | * Shiraz Hashim <shiraz.hashim@st.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/delay.h> | ||
15 | #include <linux/jiffies.h> | ||
16 | #include <linux/io.h> | ||
17 | #include <linux/smp.h> | ||
18 | #include <asm/cacheflush.h> | ||
19 | #include <asm/hardware/gic.h> | ||
20 | #include <asm/smp_scu.h> | ||
21 | #include <mach/spear.h> | ||
22 | |||
23 | /* | ||
24 | * control for which core is the next to come out of the secondary | ||
25 | * boot "holding pen" | ||
26 | */ | ||
27 | volatile int __cpuinitdata pen_release = -1; | ||
28 | static DEFINE_SPINLOCK(boot_lock); | ||
29 | |||
30 | static void __iomem *scu_base = IOMEM(VA_SCU_BASE); | ||
31 | extern void spear13xx_secondary_startup(void); | ||
32 | |||
33 | void __cpuinit platform_secondary_init(unsigned int cpu) | ||
34 | { | ||
35 | /* | ||
36 | * if any interrupts are already enabled for the primary | ||
37 | * core (e.g. timer irq), then they will not have been enabled | ||
38 | * for us: do so | ||
39 | */ | ||
40 | gic_secondary_init(0); | ||
41 | |||
42 | /* | ||
43 | * let the primary processor know we're out of the | ||
44 | * pen, then head off into the C entry point | ||
45 | */ | ||
46 | pen_release = -1; | ||
47 | smp_wmb(); | ||
48 | |||
49 | /* | ||
50 | * Synchronise with the boot thread. | ||
51 | */ | ||
52 | spin_lock(&boot_lock); | ||
53 | spin_unlock(&boot_lock); | ||
54 | } | ||
55 | |||
56 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | ||
57 | { | ||
58 | unsigned long timeout; | ||
59 | |||
60 | /* | ||
61 | * set synchronisation state between this boot processor | ||
62 | * and the secondary one | ||
63 | */ | ||
64 | spin_lock(&boot_lock); | ||
65 | |||
66 | /* | ||
67 | * The secondary processor is waiting to be released from | ||
68 | * the holding pen - release it, then wait for it to flag | ||
69 | * that it has been released by resetting pen_release. | ||
70 | * | ||
71 | * Note that "pen_release" is the hardware CPU ID, whereas | ||
72 | * "cpu" is Linux's internal ID. | ||
73 | */ | ||
74 | pen_release = cpu; | ||
75 | flush_cache_all(); | ||
76 | outer_flush_all(); | ||
77 | |||
78 | timeout = jiffies + (1 * HZ); | ||
79 | while (time_before(jiffies, timeout)) { | ||
80 | smp_rmb(); | ||
81 | if (pen_release == -1) | ||
82 | break; | ||
83 | |||
84 | udelay(10); | ||
85 | } | ||
86 | |||
87 | /* | ||
88 | * now the secondary core is starting up let it run its | ||
89 | * calibrations, then wait for it to finish | ||
90 | */ | ||
91 | spin_unlock(&boot_lock); | ||
92 | |||
93 | return pen_release != -1 ? -ENOSYS : 0; | ||
94 | } | ||
95 | |||
96 | /* | ||
97 | * Initialise the CPU possible map early - this describes the CPUs | ||
98 | * which may be present or become present in the system. | ||
99 | */ | ||
100 | void __init smp_init_cpus(void) | ||
101 | { | ||
102 | unsigned int i, ncores = scu_get_core_count(scu_base); | ||
103 | |||
104 | if (ncores > nr_cpu_ids) { | ||
105 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", | ||
106 | ncores, nr_cpu_ids); | ||
107 | ncores = nr_cpu_ids; | ||
108 | } | ||
109 | |||
110 | for (i = 0; i < ncores; i++) | ||
111 | set_cpu_possible(i, true); | ||
112 | |||
113 | set_smp_cross_call(gic_raise_softirq); | ||
114 | } | ||
115 | |||
116 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) | ||
117 | { | ||
118 | |||
119 | scu_enable(scu_base); | ||
120 | |||
121 | /* | ||
122 | * Write the address of secondary startup into the system-wide location | ||
123 | * (presently it is in SRAM). The BootMonitor waits until it receives a | ||
124 | * soft interrupt, and then the secondary CPU branches to this address. | ||
125 | */ | ||
126 | __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION); | ||
127 | } | ||
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c new file mode 100644 index 000000000000..fefd15b2f380 --- /dev/null +++ b/arch/arm/mach-spear13xx/spear1310.c | |||
@@ -0,0 +1,88 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear13xx/spear1310.c | ||
3 | * | ||
4 | * SPEAr1310 machine source file | ||
5 | * | ||
6 | * Copyright (C) 2012 ST Microelectronics | ||
7 | * Viresh Kumar <viresh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #define pr_fmt(fmt) "SPEAr1310: " fmt | ||
15 | |||
16 | #include <linux/amba/pl022.h> | ||
17 | #include <linux/of_platform.h> | ||
18 | #include <asm/hardware/gic.h> | ||
19 | #include <asm/mach/arch.h> | ||
20 | #include <asm/mach/map.h> | ||
21 | #include <mach/generic.h> | ||
22 | #include <mach/spear.h> | ||
23 | |||
24 | /* Base addresses */ | ||
25 | #define SPEAR1310_SSP1_BASE UL(0x5D400000) | ||
26 | #define SPEAR1310_SATA0_BASE UL(0xB1000000) | ||
27 | #define SPEAR1310_SATA1_BASE UL(0xB1800000) | ||
28 | #define SPEAR1310_SATA2_BASE UL(0xB4000000) | ||
29 | |||
30 | /* ssp device registration */ | ||
31 | static struct pl022_ssp_controller ssp1_plat_data = { | ||
32 | .bus_id = 0, | ||
33 | .enable_dma = 0, | ||
34 | .num_chipselect = 3, | ||
35 | }; | ||
36 | |||
37 | /* Add SPEAr1310 auxdata to pass platform data */ | ||
38 | static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = { | ||
39 | OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv), | ||
40 | OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data), | ||
41 | OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data), | ||
42 | OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data), | ||
43 | |||
44 | OF_DEV_AUXDATA("arm,pl022", SPEAR1310_SSP1_BASE, NULL, &ssp1_plat_data), | ||
45 | {} | ||
46 | }; | ||
47 | |||
48 | static void __init spear1310_dt_init(void) | ||
49 | { | ||
50 | of_platform_populate(NULL, of_default_bus_match_table, | ||
51 | spear1310_auxdata_lookup, NULL); | ||
52 | } | ||
53 | |||
54 | static const char * const spear1310_dt_board_compat[] = { | ||
55 | "st,spear1310", | ||
56 | "st,spear1310-evb", | ||
57 | NULL, | ||
58 | }; | ||
59 | |||
60 | /* | ||
61 | * Following will create 16MB static virtual/physical mappings | ||
62 | * PHYSICAL VIRTUAL | ||
63 | * 0xD8000000 0xFA000000 | ||
64 | */ | ||
65 | struct map_desc spear1310_io_desc[] __initdata = { | ||
66 | { | ||
67 | .virtual = VA_SPEAR1310_RAS_GRP1_BASE, | ||
68 | .pfn = __phys_to_pfn(SPEAR1310_RAS_GRP1_BASE), | ||
69 | .length = SZ_16M, | ||
70 | .type = MT_DEVICE | ||
71 | }, | ||
72 | }; | ||
73 | |||
74 | static void __init spear1310_map_io(void) | ||
75 | { | ||
76 | iotable_init(spear1310_io_desc, ARRAY_SIZE(spear1310_io_desc)); | ||
77 | spear13xx_map_io(); | ||
78 | } | ||
79 | |||
80 | DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree") | ||
81 | .map_io = spear1310_map_io, | ||
82 | .init_irq = spear13xx_dt_init_irq, | ||
83 | .handle_irq = gic_handle_irq, | ||
84 | .timer = &spear13xx_timer, | ||
85 | .init_machine = spear1310_dt_init, | ||
86 | .restart = spear_restart, | ||
87 | .dt_compat = spear1310_dt_board_compat, | ||
88 | MACHINE_END | ||
diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c new file mode 100644 index 000000000000..ee38cbc56869 --- /dev/null +++ b/arch/arm/mach-spear13xx/spear1340.c | |||
@@ -0,0 +1,192 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear13xx/spear1340.c | ||
3 | * | ||
4 | * SPEAr1340 machine source file | ||
5 | * | ||
6 | * Copyright (C) 2012 ST Microelectronics | ||
7 | * Viresh Kumar <viresh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #define pr_fmt(fmt) "SPEAr1340: " fmt | ||
15 | |||
16 | #include <linux/ahci_platform.h> | ||
17 | #include <linux/amba/serial.h> | ||
18 | #include <linux/delay.h> | ||
19 | #include <linux/dw_dmac.h> | ||
20 | #include <linux/of_platform.h> | ||
21 | #include <asm/hardware/gic.h> | ||
22 | #include <asm/mach/arch.h> | ||
23 | #include <mach/dma.h> | ||
24 | #include <mach/generic.h> | ||
25 | #include <mach/spear.h> | ||
26 | |||
27 | /* Base addresses */ | ||
28 | #define SPEAR1340_SATA_BASE UL(0xB1000000) | ||
29 | #define SPEAR1340_UART1_BASE UL(0xB4100000) | ||
30 | |||
31 | /* Power Management Registers */ | ||
32 | #define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100) | ||
33 | #define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104) | ||
34 | #define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108) | ||
35 | |||
36 | #define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318) | ||
37 | #define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C) | ||
38 | #define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320) | ||
39 | |||
40 | /* PCIE - SATA configuration registers */ | ||
41 | #define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424) | ||
42 | /* PCIE CFG MASks */ | ||
43 | #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11) | ||
44 | #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10) | ||
45 | #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9) | ||
46 | #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8) | ||
47 | #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4) | ||
48 | #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3) | ||
49 | #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2) | ||
50 | #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1) | ||
51 | #define SPEAR1340_PCIE_SATA_SEL_PCIE (0) | ||
52 | #define SPEAR1340_PCIE_SATA_SEL_SATA (1) | ||
53 | #define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F | ||
54 | #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \ | ||
55 | SPEAR1340_PCIE_CFG_AUX_CLK_EN | \ | ||
56 | SPEAR1340_PCIE_CFG_CORE_CLK_EN | \ | ||
57 | SPEAR1340_PCIE_CFG_POWERUP_RESET | \ | ||
58 | SPEAR1340_PCIE_CFG_DEVICE_PRESENT) | ||
59 | #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \ | ||
60 | SPEAR1340_SATA_CFG_PM_CLK_EN | \ | ||
61 | SPEAR1340_SATA_CFG_POWERUP_RESET | \ | ||
62 | SPEAR1340_SATA_CFG_RX_CLK_EN | \ | ||
63 | SPEAR1340_SATA_CFG_TX_CLK_EN) | ||
64 | |||
65 | #define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428) | ||
66 | #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31) | ||
67 | #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27) | ||
68 | #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27) | ||
69 | #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27) | ||
70 | #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0) | ||
71 | #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \ | ||
72 | (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ | ||
73 | SPEAR1340_MIPHY_CLK_REF_DIV2 | \ | ||
74 | SPEAR1340_MIPHY_PLL_RATIO_TOP(60)) | ||
75 | #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \ | ||
76 | (SPEAR1340_MIPHY_PLL_RATIO_TOP(120)) | ||
77 | #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \ | ||
78 | (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ | ||
79 | SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) | ||
80 | |||
81 | static struct dw_dma_slave uart1_dma_param[] = { | ||
82 | { | ||
83 | /* Tx */ | ||
84 | .cfg_hi = DWC_CFGH_DST_PER(SPEAR1340_DMA_REQ_UART1_TX), | ||
85 | .cfg_lo = 0, | ||
86 | .src_master = DMA_MASTER_MEMORY, | ||
87 | .dst_master = SPEAR1340_DMA_MASTER_UART1, | ||
88 | }, { | ||
89 | /* Rx */ | ||
90 | .cfg_hi = DWC_CFGH_SRC_PER(SPEAR1340_DMA_REQ_UART1_RX), | ||
91 | .cfg_lo = 0, | ||
92 | .src_master = SPEAR1340_DMA_MASTER_UART1, | ||
93 | .dst_master = DMA_MASTER_MEMORY, | ||
94 | } | ||
95 | }; | ||
96 | |||
97 | static struct amba_pl011_data uart1_data = { | ||
98 | .dma_filter = dw_dma_filter, | ||
99 | .dma_tx_param = &uart1_dma_param[0], | ||
100 | .dma_rx_param = &uart1_dma_param[1], | ||
101 | }; | ||
102 | |||
103 | /* SATA device registration */ | ||
104 | static int sata_miphy_init(struct device *dev, void __iomem *addr) | ||
105 | { | ||
106 | writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG); | ||
107 | writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK, | ||
108 | SPEAR1340_PCIE_MIPHY_CFG); | ||
109 | /* Switch on sata power domain */ | ||
110 | writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG); | ||
111 | msleep(20); | ||
112 | /* Disable PCIE SATA Controller reset */ | ||
113 | writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)), | ||
114 | SPEAR1340_PERIP1_SW_RST); | ||
115 | msleep(20); | ||
116 | |||
117 | return 0; | ||
118 | } | ||
119 | |||
120 | void sata_miphy_exit(struct device *dev) | ||
121 | { | ||
122 | writel(0, SPEAR1340_PCIE_SATA_CFG); | ||
123 | writel(0, SPEAR1340_PCIE_MIPHY_CFG); | ||
124 | |||
125 | /* Enable PCIE SATA Controller reset */ | ||
126 | writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)), | ||
127 | SPEAR1340_PERIP1_SW_RST); | ||
128 | msleep(20); | ||
129 | /* Switch off sata power domain */ | ||
130 | writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG); | ||
131 | msleep(20); | ||
132 | } | ||
133 | |||
134 | int sata_suspend(struct device *dev) | ||
135 | { | ||
136 | if (dev->power.power_state.event == PM_EVENT_FREEZE) | ||
137 | return 0; | ||
138 | |||
139 | sata_miphy_exit(dev); | ||
140 | |||
141 | return 0; | ||
142 | } | ||
143 | |||
144 | int sata_resume(struct device *dev) | ||
145 | { | ||
146 | if (dev->power.power_state.event == PM_EVENT_THAW) | ||
147 | return 0; | ||
148 | |||
149 | return sata_miphy_init(dev, NULL); | ||
150 | } | ||
151 | |||
152 | static struct ahci_platform_data sata_pdata = { | ||
153 | .init = sata_miphy_init, | ||
154 | .exit = sata_miphy_exit, | ||
155 | .suspend = sata_suspend, | ||
156 | .resume = sata_resume, | ||
157 | }; | ||
158 | |||
159 | /* Add SPEAr1340 auxdata to pass platform data */ | ||
160 | static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = { | ||
161 | OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv), | ||
162 | OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data), | ||
163 | OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data), | ||
164 | OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data), | ||
165 | |||
166 | OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL, | ||
167 | &sata_pdata), | ||
168 | OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data), | ||
169 | {} | ||
170 | }; | ||
171 | |||
172 | static void __init spear1340_dt_init(void) | ||
173 | { | ||
174 | of_platform_populate(NULL, of_default_bus_match_table, | ||
175 | spear1340_auxdata_lookup, NULL); | ||
176 | } | ||
177 | |||
178 | static const char * const spear1340_dt_board_compat[] = { | ||
179 | "st,spear1340", | ||
180 | "st,spear1340-evb", | ||
181 | NULL, | ||
182 | }; | ||
183 | |||
184 | DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree") | ||
185 | .map_io = spear13xx_map_io, | ||
186 | .init_irq = spear13xx_dt_init_irq, | ||
187 | .handle_irq = gic_handle_irq, | ||
188 | .timer = &spear13xx_timer, | ||
189 | .init_machine = spear1340_dt_init, | ||
190 | .restart = spear_restart, | ||
191 | .dt_compat = spear1340_dt_board_compat, | ||
192 | MACHINE_END | ||
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c new file mode 100644 index 000000000000..50b349ae863d --- /dev/null +++ b/arch/arm/mach-spear13xx/spear13xx.c | |||
@@ -0,0 +1,197 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear13xx/spear13xx.c | ||
3 | * | ||
4 | * SPEAr13XX machines common source file | ||
5 | * | ||
6 | * Copyright (C) 2012 ST Microelectronics | ||
7 | * Viresh Kumar <viresh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #define pr_fmt(fmt) "SPEAr13xx: " fmt | ||
15 | |||
16 | #include <linux/amba/pl022.h> | ||
17 | #include <linux/clk.h> | ||
18 | #include <linux/dw_dmac.h> | ||
19 | #include <linux/err.h> | ||
20 | #include <linux/of_irq.h> | ||
21 | #include <asm/hardware/cache-l2x0.h> | ||
22 | #include <asm/hardware/gic.h> | ||
23 | #include <asm/mach/map.h> | ||
24 | #include <asm/smp_twd.h> | ||
25 | #include <mach/dma.h> | ||
26 | #include <mach/generic.h> | ||
27 | #include <mach/spear.h> | ||
28 | |||
29 | /* common dw_dma filter routine to be used by peripherals */ | ||
30 | bool dw_dma_filter(struct dma_chan *chan, void *slave) | ||
31 | { | ||
32 | struct dw_dma_slave *dws = (struct dw_dma_slave *)slave; | ||
33 | |||
34 | if (chan->device->dev == dws->dma_dev) { | ||
35 | chan->private = slave; | ||
36 | return true; | ||
37 | } else { | ||
38 | return false; | ||
39 | } | ||
40 | } | ||
41 | |||
42 | /* ssp device registration */ | ||
43 | static struct dw_dma_slave ssp_dma_param[] = { | ||
44 | { | ||
45 | /* Tx */ | ||
46 | .cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX), | ||
47 | .cfg_lo = 0, | ||
48 | .src_master = DMA_MASTER_MEMORY, | ||
49 | .dst_master = DMA_MASTER_SSP0, | ||
50 | }, { | ||
51 | /* Rx */ | ||
52 | .cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX), | ||
53 | .cfg_lo = 0, | ||
54 | .src_master = DMA_MASTER_SSP0, | ||
55 | .dst_master = DMA_MASTER_MEMORY, | ||
56 | } | ||
57 | }; | ||
58 | |||
59 | struct pl022_ssp_controller pl022_plat_data = { | ||
60 | .bus_id = 0, | ||
61 | .enable_dma = 1, | ||
62 | .dma_filter = dw_dma_filter, | ||
63 | .dma_rx_param = &ssp_dma_param[1], | ||
64 | .dma_tx_param = &ssp_dma_param[0], | ||
65 | .num_chipselect = 3, | ||
66 | }; | ||
67 | |||
68 | /* CF device registration */ | ||
69 | struct dw_dma_slave cf_dma_priv = { | ||
70 | .cfg_hi = 0, | ||
71 | .cfg_lo = 0, | ||
72 | .src_master = 0, | ||
73 | .dst_master = 0, | ||
74 | }; | ||
75 | |||
76 | /* dmac device registeration */ | ||
77 | struct dw_dma_platform_data dmac_plat_data = { | ||
78 | .nr_channels = 8, | ||
79 | .chan_allocation_order = CHAN_ALLOCATION_DESCENDING, | ||
80 | .chan_priority = CHAN_PRIORITY_DESCENDING, | ||
81 | }; | ||
82 | |||
83 | void __init spear13xx_l2x0_init(void) | ||
84 | { | ||
85 | /* | ||
86 | * 512KB (64KB/way), 8-way associativity, parity supported | ||
87 | * | ||
88 | * FIXME: 9th bit, of Auxillary Controller register must be set | ||
89 | * for some spear13xx devices for stable L2 operation. | ||
90 | * | ||
91 | * Enable Early BRESP, L2 prefetch for Instruction and Data, | ||
92 | * write alloc and 'Full line of zero' options | ||
93 | * | ||
94 | */ | ||
95 | |||
96 | writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL); | ||
97 | |||
98 | /* | ||
99 | * Program following latencies in order to make | ||
100 | * SPEAr1340 work at 600 MHz | ||
101 | */ | ||
102 | writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL); | ||
103 | writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL); | ||
104 | l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff); | ||
105 | } | ||
106 | |||
107 | /* | ||
108 | * Following will create 16MB static virtual/physical mappings | ||
109 | * PHYSICAL VIRTUAL | ||
110 | * 0xB3000000 0xFE000000 | ||
111 | * 0xE0000000 0xFD000000 | ||
112 | * 0xEC000000 0xFC000000 | ||
113 | * 0xED000000 0xFB000000 | ||
114 | */ | ||
115 | struct map_desc spear13xx_io_desc[] __initdata = { | ||
116 | { | ||
117 | .virtual = VA_PERIP_GRP2_BASE, | ||
118 | .pfn = __phys_to_pfn(PERIP_GRP2_BASE), | ||
119 | .length = SZ_16M, | ||
120 | .type = MT_DEVICE | ||
121 | }, { | ||
122 | .virtual = VA_PERIP_GRP1_BASE, | ||
123 | .pfn = __phys_to_pfn(PERIP_GRP1_BASE), | ||
124 | .length = SZ_16M, | ||
125 | .type = MT_DEVICE | ||
126 | }, { | ||
127 | .virtual = VA_A9SM_AND_MPMC_BASE, | ||
128 | .pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE), | ||
129 | .length = SZ_16M, | ||
130 | .type = MT_DEVICE | ||
131 | }, { | ||
132 | .virtual = (unsigned long)VA_L2CC_BASE, | ||
133 | .pfn = __phys_to_pfn(L2CC_BASE), | ||
134 | .length = SZ_4K, | ||
135 | .type = MT_DEVICE | ||
136 | }, | ||
137 | }; | ||
138 | |||
139 | /* This will create static memory mapping for selected devices */ | ||
140 | void __init spear13xx_map_io(void) | ||
141 | { | ||
142 | iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc)); | ||
143 | } | ||
144 | |||
145 | static void __init spear13xx_clk_init(void) | ||
146 | { | ||
147 | if (of_machine_is_compatible("st,spear1310")) | ||
148 | spear1310_clk_init(); | ||
149 | else if (of_machine_is_compatible("st,spear1340")) | ||
150 | spear1340_clk_init(); | ||
151 | else | ||
152 | pr_err("%s: Unknown machine\n", __func__); | ||
153 | } | ||
154 | |||
155 | static void __init spear13xx_timer_init(void) | ||
156 | { | ||
157 | char pclk_name[] = "osc_24m_clk"; | ||
158 | struct clk *gpt_clk, *pclk; | ||
159 | |||
160 | spear13xx_clk_init(); | ||
161 | |||
162 | /* get the system timer clock */ | ||
163 | gpt_clk = clk_get_sys("gpt0", NULL); | ||
164 | if (IS_ERR(gpt_clk)) { | ||
165 | pr_err("%s:couldn't get clk for gpt\n", __func__); | ||
166 | BUG(); | ||
167 | } | ||
168 | |||
169 | /* get the suitable parent clock for timer*/ | ||
170 | pclk = clk_get(NULL, pclk_name); | ||
171 | if (IS_ERR(pclk)) { | ||
172 | pr_err("%s:couldn't get %s as parent for gpt\n", __func__, | ||
173 | pclk_name); | ||
174 | BUG(); | ||
175 | } | ||
176 | |||
177 | clk_set_parent(gpt_clk, pclk); | ||
178 | clk_put(gpt_clk); | ||
179 | clk_put(pclk); | ||
180 | |||
181 | spear_setup_of_timer(); | ||
182 | twd_local_timer_of_register(); | ||
183 | } | ||
184 | |||
185 | struct sys_timer spear13xx_timer = { | ||
186 | .init = spear13xx_timer_init, | ||
187 | }; | ||
188 | |||
189 | static const struct of_device_id gic_of_match[] __initconst = { | ||
190 | { .compatible = "arm,cortex-a9-gic", .data = gic_of_init }, | ||
191 | { /* Sentinel */ } | ||
192 | }; | ||
193 | |||
194 | void __init spear13xx_dt_init_irq(void) | ||
195 | { | ||
196 | of_irq_init(gic_of_match); | ||
197 | } | ||
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index f8c571031da8..a2fae4ea0936 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig | |||
@@ -419,7 +419,7 @@ config S3C_DMA | |||
419 | config SAMSUNG_DMADEV | 419 | config SAMSUNG_DMADEV |
420 | bool | 420 | bool |
421 | select DMADEVICES | 421 | select DMADEVICES |
422 | select PL330_DMA if (CPU_EXYNOS4210 || CPU_S5PV210 || CPU_S5PC100 || \ | 422 | select PL330_DMA if (ARCH_EXYNOS5 || ARCH_EXYNOS4 || CPU_S5PV210 || CPU_S5PC100 || \ |
423 | CPU_S5P6450 || CPU_S5P6440) | 423 | CPU_S5P6450 || CPU_S5P6440) |
424 | select ARM_AMBA | 424 | select ARM_AMBA |
425 | help | 425 | help |
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 787ceaca0be8..0721293fad63 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h | |||
@@ -202,7 +202,7 @@ extern struct bus_type s3c2443_subsys; | |||
202 | extern struct bus_type s3c6410_subsys; | 202 | extern struct bus_type s3c6410_subsys; |
203 | extern struct bus_type s5p64x0_subsys; | 203 | extern struct bus_type s5p64x0_subsys; |
204 | extern struct bus_type s5pv210_subsys; | 204 | extern struct bus_type s5pv210_subsys; |
205 | extern struct bus_type exynos4_subsys; | 205 | extern struct bus_type exynos_subsys; |
206 | 206 | ||
207 | extern void (*s5pc1xx_idle)(void); | 207 | extern void (*s5pc1xx_idle)(void); |
208 | 208 | ||
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index 4067d1dd7f1c..61ca2f356c52 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h | |||
@@ -134,6 +134,8 @@ extern struct platform_device exynos4_device_pcm2; | |||
134 | extern struct platform_device exynos4_device_pd[]; | 134 | extern struct platform_device exynos4_device_pd[]; |
135 | extern struct platform_device exynos4_device_spdif; | 135 | extern struct platform_device exynos4_device_spdif; |
136 | 136 | ||
137 | extern struct platform_device exynos_device_drm; | ||
138 | |||
137 | extern struct platform_device samsung_asoc_dma; | 139 | extern struct platform_device samsung_asoc_dma; |
138 | extern struct platform_device samsung_asoc_idma; | 140 | extern struct platform_device samsung_asoc_idma; |
139 | extern struct platform_device samsung_device_keypad; | 141 | extern struct platform_device samsung_device_keypad; |
diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h index 0670f37aaaed..d384a8016b47 100644 --- a/arch/arm/plat-samsung/include/plat/dma-pl330.h +++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h | |||
@@ -90,6 +90,7 @@ enum dma_ch { | |||
90 | DMACH_MIPI_HSI5, | 90 | DMACH_MIPI_HSI5, |
91 | DMACH_MIPI_HSI6, | 91 | DMACH_MIPI_HSI6, |
92 | DMACH_MIPI_HSI7, | 92 | DMACH_MIPI_HSI7, |
93 | DMACH_DISP1, | ||
93 | DMACH_MTOM_0, | 94 | DMACH_MTOM_0, |
94 | DMACH_MTOM_1, | 95 | DMACH_MTOM_1, |
95 | DMACH_MTOM_2, | 96 | DMACH_MTOM_2, |
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h index 1de4b32f98e9..8364b4bea8b8 100644 --- a/arch/arm/plat-samsung/include/plat/s5p-clock.h +++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h | |||
@@ -32,8 +32,10 @@ extern struct clk clk_48m; | |||
32 | extern struct clk s5p_clk_27m; | 32 | extern struct clk s5p_clk_27m; |
33 | extern struct clk clk_fout_apll; | 33 | extern struct clk clk_fout_apll; |
34 | extern struct clk clk_fout_bpll; | 34 | extern struct clk clk_fout_bpll; |
35 | extern struct clk clk_fout_bpll_div2; | ||
35 | extern struct clk clk_fout_cpll; | 36 | extern struct clk clk_fout_cpll; |
36 | extern struct clk clk_fout_mpll; | 37 | extern struct clk clk_fout_mpll; |
38 | extern struct clk clk_fout_mpll_div2; | ||
37 | extern struct clk clk_fout_epll; | 39 | extern struct clk clk_fout_epll; |
38 | extern struct clk clk_fout_dpll; | 40 | extern struct clk clk_fout_dpll; |
39 | extern struct clk clk_fout_vpll; | 41 | extern struct clk clk_fout_vpll; |
@@ -42,8 +44,10 @@ extern struct clk clk_vpll; | |||
42 | 44 | ||
43 | extern struct clksrc_sources clk_src_apll; | 45 | extern struct clksrc_sources clk_src_apll; |
44 | extern struct clksrc_sources clk_src_bpll; | 46 | extern struct clksrc_sources clk_src_bpll; |
47 | extern struct clksrc_sources clk_src_bpll_fout; | ||
45 | extern struct clksrc_sources clk_src_cpll; | 48 | extern struct clksrc_sources clk_src_cpll; |
46 | extern struct clksrc_sources clk_src_mpll; | 49 | extern struct clksrc_sources clk_src_mpll; |
50 | extern struct clksrc_sources clk_src_mpll_fout; | ||
47 | extern struct clksrc_sources clk_src_epll; | 51 | extern struct clksrc_sources clk_src_epll; |
48 | extern struct clksrc_sources clk_src_dpll; | 52 | extern struct clksrc_sources clk_src_dpll; |
49 | 53 | ||
diff --git a/arch/arm/plat-samsung/s5p-clock.c b/arch/arm/plat-samsung/s5p-clock.c index 41d3dfd5dddb..031a61899bef 100644 --- a/arch/arm/plat-samsung/s5p-clock.c +++ b/arch/arm/plat-samsung/s5p-clock.c | |||
@@ -67,6 +67,11 @@ struct clk clk_fout_bpll = { | |||
67 | .id = -1, | 67 | .id = -1, |
68 | }; | 68 | }; |
69 | 69 | ||
70 | struct clk clk_fout_bpll_div2 = { | ||
71 | .name = "fout_bpll_div2", | ||
72 | .id = -1, | ||
73 | }; | ||
74 | |||
70 | /* CPLL clock output */ | 75 | /* CPLL clock output */ |
71 | 76 | ||
72 | struct clk clk_fout_cpll = { | 77 | struct clk clk_fout_cpll = { |
@@ -82,6 +87,11 @@ struct clk clk_fout_mpll = { | |||
82 | .id = -1, | 87 | .id = -1, |
83 | }; | 88 | }; |
84 | 89 | ||
90 | struct clk clk_fout_mpll_div2 = { | ||
91 | .name = "fout_mpll_div2", | ||
92 | .id = -1, | ||
93 | }; | ||
94 | |||
85 | /* EPLL clock output */ | 95 | /* EPLL clock output */ |
86 | struct clk clk_fout_epll = { | 96 | struct clk clk_fout_epll = { |
87 | .name = "fout_epll", | 97 | .name = "fout_epll", |
@@ -125,6 +135,16 @@ struct clksrc_sources clk_src_bpll = { | |||
125 | .nr_sources = ARRAY_SIZE(clk_src_bpll_list), | 135 | .nr_sources = ARRAY_SIZE(clk_src_bpll_list), |
126 | }; | 136 | }; |
127 | 137 | ||
138 | static struct clk *clk_src_bpll_fout_list[] = { | ||
139 | [0] = &clk_fout_bpll_div2, | ||
140 | [1] = &clk_fout_bpll, | ||
141 | }; | ||
142 | |||
143 | struct clksrc_sources clk_src_bpll_fout = { | ||
144 | .sources = clk_src_bpll_fout_list, | ||
145 | .nr_sources = ARRAY_SIZE(clk_src_bpll_fout_list), | ||
146 | }; | ||
147 | |||
128 | /* Possible clock sources for CPLL Mux */ | 148 | /* Possible clock sources for CPLL Mux */ |
129 | static struct clk *clk_src_cpll_list[] = { | 149 | static struct clk *clk_src_cpll_list[] = { |
130 | [0] = &clk_fin_cpll, | 150 | [0] = &clk_fin_cpll, |
@@ -147,6 +167,16 @@ struct clksrc_sources clk_src_mpll = { | |||
147 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), | 167 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), |
148 | }; | 168 | }; |
149 | 169 | ||
170 | static struct clk *clk_src_mpll_fout_list[] = { | ||
171 | [0] = &clk_fout_mpll_div2, | ||
172 | [1] = &clk_fout_mpll, | ||
173 | }; | ||
174 | |||
175 | struct clksrc_sources clk_src_mpll_fout = { | ||
176 | .sources = clk_src_mpll_fout_list, | ||
177 | .nr_sources = ARRAY_SIZE(clk_src_mpll_fout_list), | ||
178 | }; | ||
179 | |||
150 | /* Possible clock sources for EPLL Mux */ | 180 | /* Possible clock sources for EPLL Mux */ |
151 | static struct clk *clk_src_epll_list[] = { | 181 | static struct clk *clk_src_epll_list[] = { |
152 | [0] = &clk_fin_epll, | 182 | [0] = &clk_fin_epll, |
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig index 387655b5ce05..4404f82d5979 100644 --- a/arch/arm/plat-spear/Kconfig +++ b/arch/arm/plat-spear/Kconfig | |||
@@ -8,6 +8,17 @@ choice | |||
8 | prompt "ST SPEAr Family" | 8 | prompt "ST SPEAr Family" |
9 | default ARCH_SPEAR3XX | 9 | default ARCH_SPEAR3XX |
10 | 10 | ||
11 | config ARCH_SPEAR13XX | ||
12 | bool "ST SPEAr13xx with Device Tree" | ||
13 | select ARM_GIC | ||
14 | select CPU_V7 | ||
15 | select USE_OF | ||
16 | select HAVE_SMP | ||
17 | select MIGHT_HAVE_CACHE_L2X0 | ||
18 | select PINCTRL | ||
19 | help | ||
20 | Supports for ARM's SPEAR13XX family | ||
21 | |||
11 | config ARCH_SPEAR3XX | 22 | config ARCH_SPEAR3XX |
12 | bool "ST SPEAr3xx with Device Tree" | 23 | bool "ST SPEAr3xx with Device Tree" |
13 | select ARM_VIC | 24 | select ARM_VIC |
@@ -27,6 +38,7 @@ config ARCH_SPEAR6XX | |||
27 | endchoice | 38 | endchoice |
28 | 39 | ||
29 | # Adding SPEAr machine specific configuration files | 40 | # Adding SPEAr machine specific configuration files |
41 | source "arch/arm/mach-spear13xx/Kconfig" | ||
30 | source "arch/arm/mach-spear3xx/Kconfig" | 42 | source "arch/arm/mach-spear3xx/Kconfig" |
31 | source "arch/arm/mach-spear6xx/Kconfig" | 43 | source "arch/arm/mach-spear6xx/Kconfig" |
32 | 44 | ||
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile index 38f1235f4632..2607bd05c525 100644 --- a/arch/arm/plat-spear/Makefile +++ b/arch/arm/plat-spear/Makefile | |||
@@ -3,6 +3,7 @@ | |||
3 | # | 3 | # |
4 | 4 | ||
5 | # Common support | 5 | # Common support |
6 | obj-y := restart.o time.o pl080.o | 6 | obj-y := restart.o time.o |
7 | 7 | ||
8 | obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o | 8 | obj-$(CONFIG_ARCH_SPEAR3XX) += pl080.o shirq.o |
9 | obj-$(CONFIG_ARCH_SPEAR6XX) += pl080.o | ||
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c index 4471a232713a..ea0a61302b7e 100644 --- a/arch/arm/plat-spear/restart.c +++ b/arch/arm/plat-spear/restart.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <mach/spear.h> | 16 | #include <mach/spear.h> |
17 | #include <mach/generic.h> | 17 | #include <mach/generic.h> |
18 | 18 | ||
19 | #define SPEAR13XX_SYS_SW_RES (VA_MISC_BASE + 0x204) | ||
19 | void spear_restart(char mode, const char *cmd) | 20 | void spear_restart(char mode, const char *cmd) |
20 | { | 21 | { |
21 | if (mode == 's') { | 22 | if (mode == 's') { |
@@ -23,6 +24,10 @@ void spear_restart(char mode, const char *cmd) | |||
23 | soft_restart(0); | 24 | soft_restart(0); |
24 | } else { | 25 | } else { |
25 | /* hardware reset, Use on-chip reset capability */ | 26 | /* hardware reset, Use on-chip reset capability */ |
27 | #ifdef CONFIG_ARCH_SPEAR13XX | ||
28 | writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES); | ||
29 | #else | ||
26 | sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE); | 30 | sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE); |
31 | #endif | ||
27 | } | 32 | } |
28 | } | 33 | } |