diff options
Diffstat (limited to 'arch/arm')
32 files changed, 0 insertions, 3504 deletions
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig deleted file mode 100644 index cddd194ac6eb..000000000000 --- a/arch/arm/mach-imx/Kconfig +++ /dev/null | |||
@@ -1,11 +0,0 @@ | |||
1 | menu "IMX Implementations" | ||
2 | depends on ARCH_IMX | ||
3 | |||
4 | config ARCH_MX1ADS | ||
5 | bool "mx1ads" | ||
6 | depends on ARCH_IMX | ||
7 | select ISA | ||
8 | help | ||
9 | Say Y here if you are using the Motorola MX1ADS board | ||
10 | |||
11 | endmenu | ||
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile deleted file mode 100644 index b047c7e795a9..000000000000 --- a/arch/arm/mach-imx/Makefile +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | # | ||
2 | # Makefile for the linux kernel. | ||
3 | # | ||
4 | |||
5 | # Object file lists. | ||
6 | |||
7 | obj-y += irq.o time.o dma.o generic.o clock.o | ||
8 | |||
9 | obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o | ||
10 | |||
11 | # Specific board support | ||
12 | obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o | ||
13 | |||
14 | # Support for blinky lights | ||
15 | led-y := leds.o | ||
16 | |||
17 | obj-$(CONFIG_LEDS) += $(led-y) | ||
18 | led-$(CONFIG_ARCH_MX1ADS) += leds-mx1ads.o | ||
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot deleted file mode 100644 index fd72ce5b8081..000000000000 --- a/arch/arm/mach-imx/Makefile.boot +++ /dev/null | |||
@@ -1,2 +0,0 @@ | |||
1 | zreladdr-$(CONFIG_ARCH_MX1ADS) := 0x08008000 | ||
2 | |||
diff --git a/arch/arm/mach-imx/clock.c b/arch/arm/mach-imx/clock.c deleted file mode 100644 index cf332aeb942e..000000000000 --- a/arch/arm/mach-imx/clock.c +++ /dev/null | |||
@@ -1,210 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
17 | */ | ||
18 | |||
19 | #include <linux/kernel.h> | ||
20 | #include <linux/device.h> | ||
21 | #include <linux/list.h> | ||
22 | #include <linux/math64.h> | ||
23 | #include <linux/err.h> | ||
24 | #include <linux/io.h> | ||
25 | |||
26 | #include <mach/hardware.h> | ||
27 | |||
28 | /* | ||
29 | * Very simple approach: We can't disable clocks, so we do | ||
30 | * not need refcounting | ||
31 | */ | ||
32 | |||
33 | struct clk { | ||
34 | struct list_head node; | ||
35 | const char *name; | ||
36 | unsigned long (*get_rate)(void); | ||
37 | }; | ||
38 | |||
39 | /* | ||
40 | * get the system pll clock in Hz | ||
41 | * | ||
42 | * mfi + mfn / (mfd +1) | ||
43 | * f = 2 * f_ref * -------------------- | ||
44 | * pd + 1 | ||
45 | */ | ||
46 | static unsigned long imx_decode_pll(unsigned int pll, u32 f_ref) | ||
47 | { | ||
48 | unsigned long long ll; | ||
49 | unsigned long quot; | ||
50 | |||
51 | u32 mfi = (pll >> 10) & 0xf; | ||
52 | u32 mfn = pll & 0x3ff; | ||
53 | u32 mfd = (pll >> 16) & 0x3ff; | ||
54 | u32 pd = (pll >> 26) & 0xf; | ||
55 | |||
56 | mfi = mfi <= 5 ? 5 : mfi; | ||
57 | |||
58 | ll = 2 * (unsigned long long)f_ref * | ||
59 | ((mfi << 16) + (mfn << 16) / (mfd + 1)); | ||
60 | quot = (pd + 1) * (1 << 16); | ||
61 | ll += quot / 2; | ||
62 | do_div(ll, quot); | ||
63 | return (unsigned long)ll; | ||
64 | } | ||
65 | |||
66 | static unsigned long imx_get_system_clk(void) | ||
67 | { | ||
68 | u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512); | ||
69 | |||
70 | return imx_decode_pll(SPCTL0, f_ref); | ||
71 | } | ||
72 | |||
73 | static unsigned long imx_get_mcu_clk(void) | ||
74 | { | ||
75 | return imx_decode_pll(MPCTL0, CLK32 * 512); | ||
76 | } | ||
77 | |||
78 | /* | ||
79 | * get peripheral clock 1 ( UART[12], Timer[12], PWM ) | ||
80 | */ | ||
81 | static unsigned long imx_get_perclk1(void) | ||
82 | { | ||
83 | return imx_get_system_clk() / (((PCDR) & 0xf)+1); | ||
84 | } | ||
85 | |||
86 | /* | ||
87 | * get peripheral clock 2 ( LCD, SD, SPI[12] ) | ||
88 | */ | ||
89 | static unsigned long imx_get_perclk2(void) | ||
90 | { | ||
91 | return imx_get_system_clk() / (((PCDR>>4) & 0xf)+1); | ||
92 | } | ||
93 | |||
94 | /* | ||
95 | * get peripheral clock 3 ( SSI ) | ||
96 | */ | ||
97 | static unsigned long imx_get_perclk3(void) | ||
98 | { | ||
99 | return imx_get_system_clk() / (((PCDR>>16) & 0x7f)+1); | ||
100 | } | ||
101 | |||
102 | /* | ||
103 | * get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA ) | ||
104 | */ | ||
105 | static unsigned long imx_get_hclk(void) | ||
106 | { | ||
107 | return imx_get_system_clk() / (((CSCR>>10) & 0xf)+1); | ||
108 | } | ||
109 | |||
110 | static struct clk clk_system_clk = { | ||
111 | .name = "system_clk", | ||
112 | .get_rate = imx_get_system_clk, | ||
113 | }; | ||
114 | |||
115 | static struct clk clk_hclk = { | ||
116 | .name = "hclk", | ||
117 | .get_rate = imx_get_hclk, | ||
118 | }; | ||
119 | |||
120 | static struct clk clk_mcu_clk = { | ||
121 | .name = "mcu_clk", | ||
122 | .get_rate = imx_get_mcu_clk, | ||
123 | }; | ||
124 | |||
125 | static struct clk clk_perclk1 = { | ||
126 | .name = "perclk1", | ||
127 | .get_rate = imx_get_perclk1, | ||
128 | }; | ||
129 | |||
130 | static struct clk clk_uart_clk = { | ||
131 | .name = "uart_clk", | ||
132 | .get_rate = imx_get_perclk1, | ||
133 | }; | ||
134 | |||
135 | static struct clk clk_perclk2 = { | ||
136 | .name = "perclk2", | ||
137 | .get_rate = imx_get_perclk2, | ||
138 | }; | ||
139 | |||
140 | static struct clk clk_perclk3 = { | ||
141 | .name = "perclk3", | ||
142 | .get_rate = imx_get_perclk3, | ||
143 | }; | ||
144 | |||
145 | static struct clk *clks[] = { | ||
146 | &clk_perclk1, | ||
147 | &clk_perclk2, | ||
148 | &clk_perclk3, | ||
149 | &clk_system_clk, | ||
150 | &clk_hclk, | ||
151 | &clk_mcu_clk, | ||
152 | &clk_uart_clk, | ||
153 | }; | ||
154 | |||
155 | static LIST_HEAD(clocks); | ||
156 | static DEFINE_MUTEX(clocks_mutex); | ||
157 | |||
158 | struct clk *clk_get(struct device *dev, const char *id) | ||
159 | { | ||
160 | struct clk *p, *clk = ERR_PTR(-ENOENT); | ||
161 | |||
162 | mutex_lock(&clocks_mutex); | ||
163 | list_for_each_entry(p, &clocks, node) { | ||
164 | if (!strcmp(p->name, id)) { | ||
165 | clk = p; | ||
166 | goto found; | ||
167 | } | ||
168 | } | ||
169 | |||
170 | found: | ||
171 | mutex_unlock(&clocks_mutex); | ||
172 | |||
173 | return clk; | ||
174 | } | ||
175 | EXPORT_SYMBOL(clk_get); | ||
176 | |||
177 | void clk_put(struct clk *clk) | ||
178 | { | ||
179 | } | ||
180 | EXPORT_SYMBOL(clk_put); | ||
181 | |||
182 | int clk_enable(struct clk *clk) | ||
183 | { | ||
184 | return 0; | ||
185 | } | ||
186 | EXPORT_SYMBOL(clk_enable); | ||
187 | |||
188 | void clk_disable(struct clk *clk) | ||
189 | { | ||
190 | } | ||
191 | EXPORT_SYMBOL(clk_disable); | ||
192 | |||
193 | unsigned long clk_get_rate(struct clk *clk) | ||
194 | { | ||
195 | return clk->get_rate(); | ||
196 | } | ||
197 | EXPORT_SYMBOL(clk_get_rate); | ||
198 | |||
199 | int imx_clocks_init(void) | ||
200 | { | ||
201 | int i; | ||
202 | |||
203 | mutex_lock(&clocks_mutex); | ||
204 | for (i = 0; i < ARRAY_SIZE(clks); i++) | ||
205 | list_add(&clks[i]->node, &clocks); | ||
206 | mutex_unlock(&clocks_mutex); | ||
207 | |||
208 | return 0; | ||
209 | } | ||
210 | |||
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c deleted file mode 100644 index 434b4ca0af67..000000000000 --- a/arch/arm/mach-imx/cpufreq.c +++ /dev/null | |||
@@ -1,315 +0,0 @@ | |||
1 | /* | ||
2 | * cpu.c: clock scaling for the iMX | ||
3 | * | ||
4 | * Copyright (C) 2000 2001, The Delft University of Technology | ||
5 | * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de> | ||
6 | * Copyright (C) 2006 Inky Lung <ilung@cwlinux.com> | ||
7 | * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> | ||
8 | * | ||
9 | * Based on SA1100 version written by: | ||
10 | * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version | ||
11 | * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl): | ||
12 | * | ||
13 | * This program is free software; you can redistribute it and/or modify | ||
14 | * it under the terms of the GNU General Public License as published by | ||
15 | * the Free Software Foundation; either version 2 of the License, or | ||
16 | * (at your option) any later version. | ||
17 | * | ||
18 | * This program is distributed in the hope that it will be useful, | ||
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
21 | * GNU General Public License for more details. | ||
22 | * | ||
23 | * You should have received a copy of the GNU General Public License | ||
24 | * along with this program; if not, write to the Free Software | ||
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
26 | * | ||
27 | */ | ||
28 | |||
29 | /*#define DEBUG*/ | ||
30 | |||
31 | #include <linux/kernel.h> | ||
32 | #include <linux/types.h> | ||
33 | #include <linux/init.h> | ||
34 | #include <linux/cpufreq.h> | ||
35 | #include <linux/clk.h> | ||
36 | #include <linux/err.h> | ||
37 | #include <asm/system.h> | ||
38 | |||
39 | #include <mach/hardware.h> | ||
40 | |||
41 | #include "generic.h" | ||
42 | |||
43 | #ifndef __val2mfld | ||
44 | #define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask)) | ||
45 | #endif | ||
46 | #ifndef __mfld2val | ||
47 | #define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1))) | ||
48 | #endif | ||
49 | |||
50 | #define CR_920T_CLOCK_MODE 0xC0000000 | ||
51 | #define CR_920T_FASTBUS_MODE 0x00000000 | ||
52 | #define CR_920T_ASYNC_MODE 0xC0000000 | ||
53 | |||
54 | static u32 mpctl0_at_boot; | ||
55 | static u32 bclk_div_at_boot; | ||
56 | |||
57 | static struct clk *system_clk, *mcu_clk; | ||
58 | |||
59 | static void imx_set_async_mode(void) | ||
60 | { | ||
61 | adjust_cr(CR_920T_CLOCK_MODE, CR_920T_ASYNC_MODE); | ||
62 | } | ||
63 | |||
64 | static void imx_set_fastbus_mode(void) | ||
65 | { | ||
66 | adjust_cr(CR_920T_CLOCK_MODE, CR_920T_FASTBUS_MODE); | ||
67 | } | ||
68 | |||
69 | static void imx_set_mpctl0(u32 mpctl0) | ||
70 | { | ||
71 | unsigned long flags; | ||
72 | |||
73 | if (mpctl0 == 0) { | ||
74 | local_irq_save(flags); | ||
75 | CSCR &= ~CSCR_MPEN; | ||
76 | local_irq_restore(flags); | ||
77 | return; | ||
78 | } | ||
79 | |||
80 | local_irq_save(flags); | ||
81 | MPCTL0 = mpctl0; | ||
82 | CSCR |= CSCR_MPEN; | ||
83 | local_irq_restore(flags); | ||
84 | } | ||
85 | |||
86 | /** | ||
87 | * imx_compute_mpctl - compute new PLL parameters | ||
88 | * @new_mpctl: pointer to location assigned by new PLL control register value | ||
89 | * @cur_mpctl: current PLL control register parameters | ||
90 | * @f_ref: reference source frequency Hz | ||
91 | * @freq: required frequency in Hz | ||
92 | * @relation: is one of %CPUFREQ_RELATION_L (supremum) | ||
93 | * and %CPUFREQ_RELATION_H (infimum) | ||
94 | */ | ||
95 | long imx_compute_mpctl(u32 *new_mpctl, u32 cur_mpctl, u32 f_ref, unsigned long freq, int relation) | ||
96 | { | ||
97 | u32 mfi; | ||
98 | u32 mfn; | ||
99 | u32 mfd; | ||
100 | u32 pd; | ||
101 | unsigned long long ll; | ||
102 | long l; | ||
103 | long quot; | ||
104 | |||
105 | /* Fdppl=2*Fref*(MFI+MFN/(MFD+1))/(PD+1) */ | ||
106 | /* PD=<0,15>, MFD=<1,1023>, MFI=<5,15> MFN=<0,1022> */ | ||
107 | |||
108 | if (cur_mpctl) { | ||
109 | mfd = ((cur_mpctl >> 16) & 0x3ff) + 1; | ||
110 | pd = ((cur_mpctl >> 26) & 0xf) + 1; | ||
111 | } else { | ||
112 | pd=2; mfd=313; | ||
113 | } | ||
114 | |||
115 | /* pd=2; mfd=313; mfi=8; mfn=183; */ | ||
116 | /* (MFI+MFN/(MFD)) = Fdppl / (2*Fref) * (PD); */ | ||
117 | |||
118 | quot = (f_ref + (1 << 9)) >> 10; | ||
119 | l = (freq * pd + quot) / (2 * quot); | ||
120 | mfi = l >> 10; | ||
121 | mfn = ((l & ((1 << 10) - 1)) * mfd + (1 << 9)) >> 10; | ||
122 | |||
123 | mfd -= 1; | ||
124 | pd -= 1; | ||
125 | |||
126 | *new_mpctl = ((mfi & 0xf) << 10) | (mfn & 0x3ff) | ((mfd & 0x3ff) << 16) | ||
127 | | ((pd & 0xf) << 26); | ||
128 | |||
129 | ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) ); | ||
130 | quot = (pd+1) * (1<<16); | ||
131 | ll += quot / 2; | ||
132 | do_div(ll, quot); | ||
133 | freq = ll; | ||
134 | |||
135 | pr_debug(KERN_DEBUG "imx: new PLL parameters pd=%d mfd=%d mfi=%d mfn=%d, freq=%ld\n", | ||
136 | pd, mfd, mfi, mfn, freq); | ||
137 | |||
138 | return freq; | ||
139 | } | ||
140 | |||
141 | |||
142 | static int imx_verify_speed(struct cpufreq_policy *policy) | ||
143 | { | ||
144 | if (policy->cpu != 0) | ||
145 | return -EINVAL; | ||
146 | |||
147 | cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); | ||
148 | |||
149 | return 0; | ||
150 | } | ||
151 | |||
152 | static unsigned int imx_get_speed(unsigned int cpu) | ||
153 | { | ||
154 | unsigned int freq; | ||
155 | unsigned int cr; | ||
156 | unsigned int cscr; | ||
157 | unsigned int bclk_div; | ||
158 | |||
159 | if (cpu) | ||
160 | return 0; | ||
161 | |||
162 | cscr = CSCR; | ||
163 | bclk_div = __mfld2val(CSCR_BCLK_DIV, cscr) + 1; | ||
164 | cr = get_cr(); | ||
165 | |||
166 | if((cr & CR_920T_CLOCK_MODE) == CR_920T_FASTBUS_MODE) { | ||
167 | freq = clk_get_rate(system_clk); | ||
168 | freq = (freq + bclk_div/2) / bclk_div; | ||
169 | } else { | ||
170 | freq = clk_get_rate(mcu_clk); | ||
171 | if (cscr & CSCR_MPU_PRESC) | ||
172 | freq /= 2; | ||
173 | } | ||
174 | |||
175 | freq = (freq + 500) / 1000; | ||
176 | |||
177 | return freq; | ||
178 | } | ||
179 | |||
180 | static int imx_set_target(struct cpufreq_policy *policy, | ||
181 | unsigned int target_freq, | ||
182 | unsigned int relation) | ||
183 | { | ||
184 | struct cpufreq_freqs freqs; | ||
185 | u32 mpctl0 = 0; | ||
186 | u32 cscr; | ||
187 | unsigned long flags; | ||
188 | long freq; | ||
189 | long sysclk; | ||
190 | unsigned int bclk_div = bclk_div_at_boot; | ||
191 | |||
192 | /* | ||
193 | * Some governors do not respects CPU and policy lower limits | ||
194 | * which leads to bad things (division by zero etc), ensure | ||
195 | * that such things do not happen. | ||
196 | */ | ||
197 | if(target_freq < policy->cpuinfo.min_freq) | ||
198 | target_freq = policy->cpuinfo.min_freq; | ||
199 | |||
200 | if(target_freq < policy->min) | ||
201 | target_freq = policy->min; | ||
202 | |||
203 | freq = target_freq * 1000; | ||
204 | |||
205 | pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n", | ||
206 | freq, mpctl0_at_boot); | ||
207 | |||
208 | sysclk = clk_get_rate(system_clk); | ||
209 | |||
210 | if (freq > sysclk / bclk_div_at_boot + 1000000) { | ||
211 | freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, CLK32 * 512, freq, relation); | ||
212 | if (freq < 0) { | ||
213 | printk(KERN_WARNING "imx: target frequency %ld Hz cannot be set\n", freq); | ||
214 | return -EINVAL; | ||
215 | } | ||
216 | } else { | ||
217 | if(freq + 1000 < sysclk) { | ||
218 | if (relation == CPUFREQ_RELATION_L) | ||
219 | bclk_div = (sysclk - 1000) / freq; | ||
220 | else | ||
221 | bclk_div = (sysclk + freq + 1000) / freq; | ||
222 | |||
223 | if(bclk_div > 16) | ||
224 | bclk_div = 16; | ||
225 | if(bclk_div < bclk_div_at_boot) | ||
226 | bclk_div = bclk_div_at_boot; | ||
227 | } | ||
228 | freq = (sysclk + bclk_div / 2) / bclk_div; | ||
229 | } | ||
230 | |||
231 | freqs.old = imx_get_speed(0); | ||
232 | freqs.new = (freq + 500) / 1000; | ||
233 | freqs.cpu = 0; | ||
234 | freqs.flags = 0; | ||
235 | |||
236 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | ||
237 | |||
238 | local_irq_save(flags); | ||
239 | |||
240 | imx_set_fastbus_mode(); | ||
241 | |||
242 | imx_set_mpctl0(mpctl0); | ||
243 | |||
244 | cscr = CSCR; | ||
245 | cscr &= ~CSCR_BCLK_DIV; | ||
246 | cscr |= __val2mfld(CSCR_BCLK_DIV, bclk_div - 1); | ||
247 | CSCR = cscr; | ||
248 | |||
249 | if(mpctl0) { | ||
250 | CSCR |= CSCR_MPLL_RESTART; | ||
251 | |||
252 | /* Wait until MPLL is stabilized */ | ||
253 | while( CSCR & CSCR_MPLL_RESTART ); | ||
254 | |||
255 | imx_set_async_mode(); | ||
256 | } | ||
257 | |||
258 | local_irq_restore(flags); | ||
259 | |||
260 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | ||
261 | |||
262 | pr_debug(KERN_INFO "imx: set frequency %ld Hz, running from %s\n", | ||
263 | freq, mpctl0? "MPLL": "SPLL"); | ||
264 | |||
265 | return 0; | ||
266 | } | ||
267 | |||
268 | static int __init imx_cpufreq_driver_init(struct cpufreq_policy *policy) | ||
269 | { | ||
270 | printk(KERN_INFO "i.MX cpu freq change driver v1.0\n"); | ||
271 | |||
272 | if (policy->cpu != 0) | ||
273 | return -EINVAL; | ||
274 | |||
275 | policy->cur = policy->min = policy->max = imx_get_speed(0); | ||
276 | policy->cpuinfo.min_freq = 8000; | ||
277 | policy->cpuinfo.max_freq = 200000; | ||
278 | /* Manual states, that PLL stabilizes in two CLK32 periods */ | ||
279 | policy->cpuinfo.transition_latency = 4 * 1000000000LL / CLK32; | ||
280 | return 0; | ||
281 | } | ||
282 | |||
283 | static struct cpufreq_driver imx_driver = { | ||
284 | .flags = CPUFREQ_STICKY, | ||
285 | .verify = imx_verify_speed, | ||
286 | .target = imx_set_target, | ||
287 | .get = imx_get_speed, | ||
288 | .init = imx_cpufreq_driver_init, | ||
289 | .name = "imx", | ||
290 | }; | ||
291 | |||
292 | static int __init imx_cpufreq_init(void) | ||
293 | { | ||
294 | bclk_div_at_boot = __mfld2val(CSCR_BCLK_DIV, CSCR) + 1; | ||
295 | mpctl0_at_boot = 0; | ||
296 | |||
297 | system_clk = clk_get(NULL, "system_clk"); | ||
298 | if (IS_ERR(system_clk)) | ||
299 | return PTR_ERR(system_clk); | ||
300 | |||
301 | mcu_clk = clk_get(NULL, "mcu_clk"); | ||
302 | if (IS_ERR(mcu_clk)) { | ||
303 | clk_put(system_clk); | ||
304 | return PTR_ERR(mcu_clk); | ||
305 | } | ||
306 | |||
307 | if((CSCR & CSCR_MPEN) && | ||
308 | ((get_cr() & CR_920T_CLOCK_MODE) != CR_920T_FASTBUS_MODE)) | ||
309 | mpctl0_at_boot = MPCTL0; | ||
310 | |||
311 | return cpufreq_register_driver(&imx_driver); | ||
312 | } | ||
313 | |||
314 | arch_initcall(imx_cpufreq_init); | ||
315 | |||
diff --git a/arch/arm/mach-imx/dma.c b/arch/arm/mach-imx/dma.c deleted file mode 100644 index 1536583eece0..000000000000 --- a/arch/arm/mach-imx/dma.c +++ /dev/null | |||
@@ -1,597 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-imx/dma.c | ||
3 | * | ||
4 | * imx DMA registration and IRQ dispatching | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * 2004-03-03 Sascha Hauer <sascha@saschahauer.de> | ||
11 | * initial version heavily inspired by | ||
12 | * linux/arch/arm/mach-pxa/dma.c | ||
13 | * | ||
14 | * 2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
15 | * Changed to support scatter gather DMA | ||
16 | * by taking Russell's code from RiscPC | ||
17 | * | ||
18 | * 2006-05-31 Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
19 | * Corrected error handling code. | ||
20 | * | ||
21 | */ | ||
22 | |||
23 | #undef DEBUG | ||
24 | |||
25 | #include <linux/module.h> | ||
26 | #include <linux/init.h> | ||
27 | #include <linux/kernel.h> | ||
28 | #include <linux/interrupt.h> | ||
29 | #include <linux/errno.h> | ||
30 | |||
31 | #include <asm/scatterlist.h> | ||
32 | #include <asm/system.h> | ||
33 | #include <asm/irq.h> | ||
34 | #include <mach/hardware.h> | ||
35 | #include <mach/dma.h> | ||
36 | #include <mach/imx-dma.h> | ||
37 | |||
38 | struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; | ||
39 | |||
40 | /* | ||
41 | * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation | ||
42 | * @dma_ch: i.MX DMA channel number | ||
43 | * @lastcount: number of bytes transferred during last transfer | ||
44 | * | ||
45 | * Functions prepares DMA controller for next sg data chunk transfer. | ||
46 | * The @lastcount argument informs function about number of bytes transferred | ||
47 | * during last block. Zero value can be used for @lastcount to setup DMA | ||
48 | * for the first chunk. | ||
49 | */ | ||
50 | static inline int imx_dma_sg_next(imx_dmach_t dma_ch, unsigned int lastcount) | ||
51 | { | ||
52 | struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; | ||
53 | unsigned int nextcount; | ||
54 | unsigned int nextaddr; | ||
55 | |||
56 | if (!imxdma->name) { | ||
57 | printk(KERN_CRIT "%s: called for not allocated channel %d\n", | ||
58 | __func__, dma_ch); | ||
59 | return 0; | ||
60 | } | ||
61 | |||
62 | imxdma->resbytes -= lastcount; | ||
63 | |||
64 | if (!imxdma->sg) { | ||
65 | pr_debug("imxdma%d: no sg data\n", dma_ch); | ||
66 | return 0; | ||
67 | } | ||
68 | |||
69 | imxdma->sgbc += lastcount; | ||
70 | if ((imxdma->sgbc >= imxdma->sg->length) || !imxdma->resbytes) { | ||
71 | if ((imxdma->sgcount <= 1) || !imxdma->resbytes) { | ||
72 | pr_debug("imxdma%d: sg transfer limit reached\n", | ||
73 | dma_ch); | ||
74 | imxdma->sgcount=0; | ||
75 | imxdma->sg = NULL; | ||
76 | return 0; | ||
77 | } else { | ||
78 | imxdma->sgcount--; | ||
79 | imxdma->sg++; | ||
80 | imxdma->sgbc = 0; | ||
81 | } | ||
82 | } | ||
83 | nextcount = imxdma->sg->length - imxdma->sgbc; | ||
84 | nextaddr = imxdma->sg->dma_address + imxdma->sgbc; | ||
85 | |||
86 | if(imxdma->resbytes < nextcount) | ||
87 | nextcount = imxdma->resbytes; | ||
88 | |||
89 | if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ) | ||
90 | DAR(dma_ch) = nextaddr; | ||
91 | else | ||
92 | SAR(dma_ch) = nextaddr; | ||
93 | |||
94 | CNTR(dma_ch) = nextcount; | ||
95 | pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, size 0x%08x\n", | ||
96 | dma_ch, DAR(dma_ch), SAR(dma_ch), CNTR(dma_ch)); | ||
97 | |||
98 | return nextcount; | ||
99 | } | ||
100 | |||
101 | /* | ||
102 | * imx_dma_setup_sg_base - scatter-gather DMA emulation | ||
103 | * @dma_ch: i.MX DMA channel number | ||
104 | * @sg: pointer to the scatter-gather list/vector | ||
105 | * @sgcount: scatter-gather list hungs count | ||
106 | * | ||
107 | * Functions sets up i.MX DMA state for emulated scatter-gather transfer | ||
108 | * and sets up channel registers to be ready for the first chunk | ||
109 | */ | ||
110 | static int | ||
111 | imx_dma_setup_sg_base(imx_dmach_t dma_ch, | ||
112 | struct scatterlist *sg, unsigned int sgcount) | ||
113 | { | ||
114 | struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; | ||
115 | |||
116 | imxdma->sg = sg; | ||
117 | imxdma->sgcount = sgcount; | ||
118 | imxdma->sgbc = 0; | ||
119 | return imx_dma_sg_next(dma_ch, 0); | ||
120 | } | ||
121 | |||
122 | /** | ||
123 | * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from device transfer | ||
124 | * @dma_ch: i.MX DMA channel number | ||
125 | * @dma_address: the DMA/physical memory address of the linear data block | ||
126 | * to transfer | ||
127 | * @dma_length: length of the data block in bytes | ||
128 | * @dev_addr: physical device port address | ||
129 | * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory | ||
130 | * or %DMA_MODE_WRITE from memory to the device | ||
131 | * | ||
132 | * The function setups DMA channel source and destination addresses for transfer | ||
133 | * specified by provided parameters. The scatter-gather emulation is disabled, | ||
134 | * because linear data block | ||
135 | * form the physical address range is transferred. | ||
136 | * Return value: if incorrect parameters are provided -%EINVAL. | ||
137 | * Zero indicates success. | ||
138 | */ | ||
139 | int | ||
140 | imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, | ||
141 | unsigned int dma_length, unsigned int dev_addr, | ||
142 | unsigned int dmamode) | ||
143 | { | ||
144 | struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; | ||
145 | |||
146 | imxdma->sg = NULL; | ||
147 | imxdma->sgcount = 0; | ||
148 | imxdma->dma_mode = dmamode; | ||
149 | imxdma->resbytes = dma_length; | ||
150 | |||
151 | if (!dma_address) { | ||
152 | printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n", | ||
153 | dma_ch); | ||
154 | return -EINVAL; | ||
155 | } | ||
156 | |||
157 | if (!dma_length) { | ||
158 | printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n", | ||
159 | dma_ch); | ||
160 | return -EINVAL; | ||
161 | } | ||
162 | |||
163 | if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) { | ||
164 | pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for read\n", | ||
165 | dma_ch, (unsigned int)dma_address, dma_length, | ||
166 | dev_addr); | ||
167 | SAR(dma_ch) = dev_addr; | ||
168 | DAR(dma_ch) = (unsigned int)dma_address; | ||
169 | } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { | ||
170 | pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for write\n", | ||
171 | dma_ch, (unsigned int)dma_address, dma_length, | ||
172 | dev_addr); | ||
173 | SAR(dma_ch) = (unsigned int)dma_address; | ||
174 | DAR(dma_ch) = dev_addr; | ||
175 | } else { | ||
176 | printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n", | ||
177 | dma_ch); | ||
178 | return -EINVAL; | ||
179 | } | ||
180 | |||
181 | CNTR(dma_ch) = dma_length; | ||
182 | |||
183 | return 0; | ||
184 | } | ||
185 | |||
186 | /** | ||
187 | * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer | ||
188 | * @dma_ch: i.MX DMA channel number | ||
189 | * @sg: pointer to the scatter-gather list/vector | ||
190 | * @sgcount: scatter-gather list hungs count | ||
191 | * @dma_length: total length of the transfer request in bytes | ||
192 | * @dev_addr: physical device port address | ||
193 | * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory | ||
194 | * or %DMA_MODE_WRITE from memory to the device | ||
195 | * | ||
196 | * The function sets up DMA channel state and registers to be ready for transfer | ||
197 | * specified by provided parameters. The scatter-gather emulation is set up | ||
198 | * according to the parameters. | ||
199 | * | ||
200 | * The full preparation of the transfer requires setup of more register | ||
201 | * by the caller before imx_dma_enable() can be called. | ||
202 | * | ||
203 | * %BLR(dma_ch) holds transfer burst length in bytes, 0 means 64 bytes | ||
204 | * | ||
205 | * %RSSR(dma_ch) has to be set to the DMA request line source %DMA_REQ_xxx | ||
206 | * | ||
207 | * %CCR(dma_ch) has to specify transfer parameters, the next settings is typical | ||
208 | * for linear or simple scatter-gather transfers if %DMA_MODE_READ is specified | ||
209 | * | ||
210 | * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x | ||
211 | * | ||
212 | * The typical setup for %DMA_MODE_WRITE is specified by next options combination | ||
213 | * | ||
214 | * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x | ||
215 | * | ||
216 | * Be careful here and do not mistakenly mix source and target device | ||
217 | * port sizes constants, they are really different: | ||
218 | * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32, | ||
219 | * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32 | ||
220 | * | ||
221 | * Return value: if incorrect parameters are provided -%EINVAL. | ||
222 | * Zero indicates success. | ||
223 | */ | ||
224 | int | ||
225 | imx_dma_setup_sg(imx_dmach_t dma_ch, | ||
226 | struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, | ||
227 | unsigned int dev_addr, unsigned int dmamode) | ||
228 | { | ||
229 | int res; | ||
230 | struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; | ||
231 | |||
232 | imxdma->sg = NULL; | ||
233 | imxdma->sgcount = 0; | ||
234 | imxdma->dma_mode = dmamode; | ||
235 | imxdma->resbytes = dma_length; | ||
236 | |||
237 | if (!sg || !sgcount) { | ||
238 | printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n", | ||
239 | dma_ch); | ||
240 | return -EINVAL; | ||
241 | } | ||
242 | |||
243 | if (!sg->length) { | ||
244 | printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n", | ||
245 | dma_ch); | ||
246 | return -EINVAL; | ||
247 | } | ||
248 | |||
249 | if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) { | ||
250 | pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for read\n", | ||
251 | dma_ch, sg, sgcount, dma_length, dev_addr); | ||
252 | SAR(dma_ch) = dev_addr; | ||
253 | } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { | ||
254 | pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for write\n", | ||
255 | dma_ch, sg, sgcount, dma_length, dev_addr); | ||
256 | DAR(dma_ch) = dev_addr; | ||
257 | } else { | ||
258 | printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n", | ||
259 | dma_ch); | ||
260 | return -EINVAL; | ||
261 | } | ||
262 | |||
263 | res = imx_dma_setup_sg_base(dma_ch, sg, sgcount); | ||
264 | if (res <= 0) { | ||
265 | printk(KERN_ERR "imxdma%d: no sg chunk ready\n", dma_ch); | ||
266 | return -EINVAL; | ||
267 | } | ||
268 | |||
269 | return 0; | ||
270 | } | ||
271 | |||
272 | /** | ||
273 | * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification handlers | ||
274 | * @dma_ch: i.MX DMA channel number | ||
275 | * @irq_handler: the pointer to the function called if the transfer | ||
276 | * ends successfully | ||
277 | * @err_handler: the pointer to the function called if the premature | ||
278 | * end caused by error occurs | ||
279 | * @data: user specified value to be passed to the handlers | ||
280 | */ | ||
281 | int | ||
282 | imx_dma_setup_handlers(imx_dmach_t dma_ch, | ||
283 | void (*irq_handler) (int, void *), | ||
284 | void (*err_handler) (int, void *, int), | ||
285 | void *data) | ||
286 | { | ||
287 | struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; | ||
288 | unsigned long flags; | ||
289 | |||
290 | if (!imxdma->name) { | ||
291 | printk(KERN_CRIT "%s: called for not allocated channel %d\n", | ||
292 | __func__, dma_ch); | ||
293 | return -ENODEV; | ||
294 | } | ||
295 | |||
296 | local_irq_save(flags); | ||
297 | DISR = (1 << dma_ch); | ||
298 | imxdma->irq_handler = irq_handler; | ||
299 | imxdma->err_handler = err_handler; | ||
300 | imxdma->data = data; | ||
301 | local_irq_restore(flags); | ||
302 | return 0; | ||
303 | } | ||
304 | |||
305 | /** | ||
306 | * imx_dma_enable - function to start i.MX DMA channel operation | ||
307 | * @dma_ch: i.MX DMA channel number | ||
308 | * | ||
309 | * The channel has to be allocated by driver through imx_dma_request() | ||
310 | * or imx_dma_request_by_prio() function. | ||
311 | * The transfer parameters has to be set to the channel registers through | ||
312 | * call of the imx_dma_setup_single() or imx_dma_setup_sg() function | ||
313 | * and registers %BLR(dma_ch), %RSSR(dma_ch) and %CCR(dma_ch) has to | ||
314 | * be set prior this function call by the channel user. | ||
315 | */ | ||
316 | void imx_dma_enable(imx_dmach_t dma_ch) | ||
317 | { | ||
318 | struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; | ||
319 | unsigned long flags; | ||
320 | |||
321 | pr_debug("imxdma%d: imx_dma_enable\n", dma_ch); | ||
322 | |||
323 | if (!imxdma->name) { | ||
324 | printk(KERN_CRIT "%s: called for not allocated channel %d\n", | ||
325 | __func__, dma_ch); | ||
326 | return; | ||
327 | } | ||
328 | |||
329 | local_irq_save(flags); | ||
330 | DISR = (1 << dma_ch); | ||
331 | DIMR &= ~(1 << dma_ch); | ||
332 | CCR(dma_ch) |= CCR_CEN; | ||
333 | local_irq_restore(flags); | ||
334 | } | ||
335 | |||
336 | /** | ||
337 | * imx_dma_disable - stop, finish i.MX DMA channel operatin | ||
338 | * @dma_ch: i.MX DMA channel number | ||
339 | */ | ||
340 | void imx_dma_disable(imx_dmach_t dma_ch) | ||
341 | { | ||
342 | unsigned long flags; | ||
343 | |||
344 | pr_debug("imxdma%d: imx_dma_disable\n", dma_ch); | ||
345 | |||
346 | local_irq_save(flags); | ||
347 | DIMR |= (1 << dma_ch); | ||
348 | CCR(dma_ch) &= ~CCR_CEN; | ||
349 | DISR = (1 << dma_ch); | ||
350 | local_irq_restore(flags); | ||
351 | } | ||
352 | |||
353 | /** | ||
354 | * imx_dma_request - request/allocate specified channel number | ||
355 | * @dma_ch: i.MX DMA channel number | ||
356 | * @name: the driver/caller own non-%NULL identification | ||
357 | */ | ||
358 | int imx_dma_request(imx_dmach_t dma_ch, const char *name) | ||
359 | { | ||
360 | struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; | ||
361 | unsigned long flags; | ||
362 | |||
363 | /* basic sanity checks */ | ||
364 | if (!name) | ||
365 | return -EINVAL; | ||
366 | |||
367 | if (dma_ch >= IMX_DMA_CHANNELS) { | ||
368 | printk(KERN_CRIT "%s: called for non-existed channel %d\n", | ||
369 | __func__, dma_ch); | ||
370 | return -EINVAL; | ||
371 | } | ||
372 | |||
373 | local_irq_save(flags); | ||
374 | if (imxdma->name) { | ||
375 | local_irq_restore(flags); | ||
376 | return -ENODEV; | ||
377 | } | ||
378 | |||
379 | imxdma->name = name; | ||
380 | imxdma->irq_handler = NULL; | ||
381 | imxdma->err_handler = NULL; | ||
382 | imxdma->data = NULL; | ||
383 | imxdma->sg = NULL; | ||
384 | local_irq_restore(flags); | ||
385 | return 0; | ||
386 | } | ||
387 | |||
388 | /** | ||
389 | * imx_dma_free - release previously acquired channel | ||
390 | * @dma_ch: i.MX DMA channel number | ||
391 | */ | ||
392 | void imx_dma_free(imx_dmach_t dma_ch) | ||
393 | { | ||
394 | unsigned long flags; | ||
395 | struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; | ||
396 | |||
397 | if (!imxdma->name) { | ||
398 | printk(KERN_CRIT | ||
399 | "%s: trying to free channel %d which is already freed\n", | ||
400 | __func__, dma_ch); | ||
401 | return; | ||
402 | } | ||
403 | |||
404 | local_irq_save(flags); | ||
405 | /* Disable interrupts */ | ||
406 | DIMR |= (1 << dma_ch); | ||
407 | CCR(dma_ch) &= ~CCR_CEN; | ||
408 | imxdma->name = NULL; | ||
409 | local_irq_restore(flags); | ||
410 | } | ||
411 | |||
412 | /** | ||
413 | * imx_dma_request_by_prio - find and request some of free channels best suiting requested priority | ||
414 | * @name: the driver/caller own non-%NULL identification | ||
415 | * @prio: one of the hardware distinguished priority level: | ||
416 | * %DMA_PRIO_HIGH, %DMA_PRIO_MEDIUM, %DMA_PRIO_LOW | ||
417 | * | ||
418 | * This function tries to find free channel in the specified priority group | ||
419 | * if the priority cannot be achieved it tries to look for free channel | ||
420 | * in the higher and then even lower priority groups. | ||
421 | * | ||
422 | * Return value: If there is no free channel to allocate, -%ENODEV is returned. | ||
423 | * On successful allocation channel is returned. | ||
424 | */ | ||
425 | imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio) | ||
426 | { | ||
427 | int i; | ||
428 | int best; | ||
429 | |||
430 | switch (prio) { | ||
431 | case (DMA_PRIO_HIGH): | ||
432 | best = 8; | ||
433 | break; | ||
434 | case (DMA_PRIO_MEDIUM): | ||
435 | best = 4; | ||
436 | break; | ||
437 | case (DMA_PRIO_LOW): | ||
438 | default: | ||
439 | best = 0; | ||
440 | break; | ||
441 | } | ||
442 | |||
443 | for (i = best; i < IMX_DMA_CHANNELS; i++) { | ||
444 | if (!imx_dma_request(i, name)) { | ||
445 | return i; | ||
446 | } | ||
447 | } | ||
448 | |||
449 | for (i = best - 1; i >= 0; i--) { | ||
450 | if (!imx_dma_request(i, name)) { | ||
451 | return i; | ||
452 | } | ||
453 | } | ||
454 | |||
455 | printk(KERN_ERR "%s: no free DMA channel found\n", __func__); | ||
456 | |||
457 | return -ENODEV; | ||
458 | } | ||
459 | |||
460 | static irqreturn_t dma_err_handler(int irq, void *dev_id) | ||
461 | { | ||
462 | int i, disr = DISR; | ||
463 | struct imx_dma_channel *channel; | ||
464 | unsigned int err_mask = DBTOSR | DRTOSR | DSESR | DBOSR; | ||
465 | int errcode; | ||
466 | |||
467 | DISR = disr & err_mask; | ||
468 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | ||
469 | if(!(err_mask & (1 << i))) | ||
470 | continue; | ||
471 | channel = &imx_dma_channels[i]; | ||
472 | errcode = 0; | ||
473 | |||
474 | if (DBTOSR & (1 << i)) { | ||
475 | DBTOSR = (1 << i); | ||
476 | errcode |= IMX_DMA_ERR_BURST; | ||
477 | } | ||
478 | if (DRTOSR & (1 << i)) { | ||
479 | DRTOSR = (1 << i); | ||
480 | errcode |= IMX_DMA_ERR_REQUEST; | ||
481 | } | ||
482 | if (DSESR & (1 << i)) { | ||
483 | DSESR = (1 << i); | ||
484 | errcode |= IMX_DMA_ERR_TRANSFER; | ||
485 | } | ||
486 | if (DBOSR & (1 << i)) { | ||
487 | DBOSR = (1 << i); | ||
488 | errcode |= IMX_DMA_ERR_BUFFER; | ||
489 | } | ||
490 | |||
491 | /* | ||
492 | * The cleaning of @sg field would be questionable | ||
493 | * there, because its value can help to compute | ||
494 | * remaining/transferred bytes count in the handler | ||
495 | */ | ||
496 | /*imx_dma_channels[i].sg = NULL;*/ | ||
497 | |||
498 | if (channel->name && channel->err_handler) { | ||
499 | channel->err_handler(i, channel->data, errcode); | ||
500 | continue; | ||
501 | } | ||
502 | |||
503 | imx_dma_channels[i].sg = NULL; | ||
504 | |||
505 | printk(KERN_WARNING | ||
506 | "DMA timeout on channel %d (%s) -%s%s%s%s\n", | ||
507 | i, channel->name, | ||
508 | errcode&IMX_DMA_ERR_BURST? " burst":"", | ||
509 | errcode&IMX_DMA_ERR_REQUEST? " request":"", | ||
510 | errcode&IMX_DMA_ERR_TRANSFER? " transfer":"", | ||
511 | errcode&IMX_DMA_ERR_BUFFER? " buffer":""); | ||
512 | } | ||
513 | return IRQ_HANDLED; | ||
514 | } | ||
515 | |||
516 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) | ||
517 | { | ||
518 | int i, disr = DISR; | ||
519 | |||
520 | pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n", | ||
521 | disr); | ||
522 | |||
523 | DISR = disr; | ||
524 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | ||
525 | if (disr & (1 << i)) { | ||
526 | struct imx_dma_channel *channel = &imx_dma_channels[i]; | ||
527 | if (channel->name) { | ||
528 | if (imx_dma_sg_next(i, CNTR(i))) { | ||
529 | CCR(i) &= ~CCR_CEN; | ||
530 | mb(); | ||
531 | CCR(i) |= CCR_CEN; | ||
532 | } else { | ||
533 | if (channel->irq_handler) | ||
534 | channel->irq_handler(i, | ||
535 | channel->data); | ||
536 | } | ||
537 | } else { | ||
538 | /* | ||
539 | * IRQ for an unregistered DMA channel: | ||
540 | * let's clear the interrupts and disable it. | ||
541 | */ | ||
542 | printk(KERN_WARNING | ||
543 | "spurious IRQ for DMA channel %d\n", i); | ||
544 | } | ||
545 | } | ||
546 | } | ||
547 | return IRQ_HANDLED; | ||
548 | } | ||
549 | |||
550 | static int __init imx_dma_init(void) | ||
551 | { | ||
552 | int ret; | ||
553 | int i; | ||
554 | |||
555 | /* reset DMA module */ | ||
556 | DCR = DCR_DRST; | ||
557 | |||
558 | ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL); | ||
559 | if (ret) { | ||
560 | printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n"); | ||
561 | return ret; | ||
562 | } | ||
563 | |||
564 | ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL); | ||
565 | if (ret) { | ||
566 | printk(KERN_CRIT "Wow! Can't register ERRIRQ for DMA\n"); | ||
567 | free_irq(DMA_INT, NULL); | ||
568 | } | ||
569 | |||
570 | /* enable DMA module */ | ||
571 | DCR = DCR_DEN; | ||
572 | |||
573 | /* clear all interrupts */ | ||
574 | DISR = (1 << IMX_DMA_CHANNELS) - 1; | ||
575 | |||
576 | /* enable interrupts */ | ||
577 | DIMR = (1 << IMX_DMA_CHANNELS) - 1; | ||
578 | |||
579 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | ||
580 | imx_dma_channels[i].sg = NULL; | ||
581 | imx_dma_channels[i].dma_num = i; | ||
582 | } | ||
583 | |||
584 | return ret; | ||
585 | } | ||
586 | |||
587 | arch_initcall(imx_dma_init); | ||
588 | |||
589 | EXPORT_SYMBOL(imx_dma_setup_single); | ||
590 | EXPORT_SYMBOL(imx_dma_setup_sg); | ||
591 | EXPORT_SYMBOL(imx_dma_setup_handlers); | ||
592 | EXPORT_SYMBOL(imx_dma_enable); | ||
593 | EXPORT_SYMBOL(imx_dma_disable); | ||
594 | EXPORT_SYMBOL(imx_dma_request); | ||
595 | EXPORT_SYMBOL(imx_dma_free); | ||
596 | EXPORT_SYMBOL(imx_dma_request_by_prio); | ||
597 | EXPORT_SYMBOL(imx_dma_channels); | ||
diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c deleted file mode 100644 index 05f1739ee127..000000000000 --- a/arch/arm/mach-imx/generic.c +++ /dev/null | |||
@@ -1,271 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-imx/generic.c | ||
3 | * | ||
4 | * author: Sascha Hauer | ||
5 | * Created: april 20th, 2004 | ||
6 | * Copyright: Synertronixx GmbH | ||
7 | * | ||
8 | * Common code for i.MX machines | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | * | ||
15 | * This program is distributed in the hope that it will be useful, | ||
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
18 | * GNU General Public License for more details. | ||
19 | * | ||
20 | * You should have received a copy of the GNU General Public License | ||
21 | * along with this program; if not, write to the Free Software | ||
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
23 | * | ||
24 | */ | ||
25 | #include <linux/platform_device.h> | ||
26 | #include <linux/init.h> | ||
27 | #include <linux/kernel.h> | ||
28 | #include <linux/module.h> | ||
29 | #include <linux/string.h> | ||
30 | |||
31 | #include <asm/errno.h> | ||
32 | #include <mach/hardware.h> | ||
33 | #include <mach/imx-regs.h> | ||
34 | |||
35 | #include <asm/mach/map.h> | ||
36 | #include <mach/mmc.h> | ||
37 | #include <mach/gpio.h> | ||
38 | |||
39 | unsigned long imx_gpio_alloc_map[(GPIO_PORT_MAX + 1) * 32 / BITS_PER_LONG]; | ||
40 | |||
41 | void imx_gpio_mode(int gpio_mode) | ||
42 | { | ||
43 | unsigned int pin = gpio_mode & GPIO_PIN_MASK; | ||
44 | unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; | ||
45 | unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; | ||
46 | unsigned int tmp; | ||
47 | |||
48 | /* Pullup enable */ | ||
49 | if(gpio_mode & GPIO_PUEN) | ||
50 | PUEN(port) |= (1<<pin); | ||
51 | else | ||
52 | PUEN(port) &= ~(1<<pin); | ||
53 | |||
54 | /* Data direction */ | ||
55 | if(gpio_mode & GPIO_OUT) | ||
56 | DDIR(port) |= 1<<pin; | ||
57 | else | ||
58 | DDIR(port) &= ~(1<<pin); | ||
59 | |||
60 | /* Primary / alternate function */ | ||
61 | if(gpio_mode & GPIO_AF) | ||
62 | GPR(port) |= (1<<pin); | ||
63 | else | ||
64 | GPR(port) &= ~(1<<pin); | ||
65 | |||
66 | /* use as gpio? */ | ||
67 | if(gpio_mode & GPIO_GIUS) | ||
68 | GIUS(port) |= (1<<pin); | ||
69 | else | ||
70 | GIUS(port) &= ~(1<<pin); | ||
71 | |||
72 | /* Output / input configuration */ | ||
73 | /* FIXME: I'm not very sure about OCR and ICONF, someone | ||
74 | * should have a look over it | ||
75 | */ | ||
76 | if(pin<16) { | ||
77 | tmp = OCR1(port); | ||
78 | tmp &= ~( 3<<(pin*2)); | ||
79 | tmp |= (ocr << (pin*2)); | ||
80 | OCR1(port) = tmp; | ||
81 | |||
82 | ICONFA1(port) &= ~( 3<<(pin*2)); | ||
83 | ICONFA1(port) |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2); | ||
84 | ICONFB1(port) &= ~( 3<<(pin*2)); | ||
85 | ICONFB1(port) |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2); | ||
86 | } else { | ||
87 | tmp = OCR2(port); | ||
88 | tmp &= ~( 3<<((pin-16)*2)); | ||
89 | tmp |= (ocr << ((pin-16)*2)); | ||
90 | OCR2(port) = tmp; | ||
91 | |||
92 | ICONFA2(port) &= ~( 3<<((pin-16)*2)); | ||
93 | ICONFA2(port) |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << ((pin-16) * 2); | ||
94 | ICONFB2(port) &= ~( 3<<((pin-16)*2)); | ||
95 | ICONFB2(port) |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << ((pin-16) * 2); | ||
96 | } | ||
97 | } | ||
98 | |||
99 | EXPORT_SYMBOL(imx_gpio_mode); | ||
100 | |||
101 | int imx_gpio_request(unsigned gpio, const char *label) | ||
102 | { | ||
103 | if(gpio >= (GPIO_PORT_MAX + 1) * 32) { | ||
104 | printk(KERN_ERR "imx_gpio: Attempt to request nonexistent GPIO %d for \"%s\"\n", | ||
105 | gpio, label ? label : "?"); | ||
106 | return -EINVAL; | ||
107 | } | ||
108 | |||
109 | if(test_and_set_bit(gpio, imx_gpio_alloc_map)) { | ||
110 | printk(KERN_ERR "imx_gpio: GPIO %d already used. Allocation for \"%s\" failed\n", | ||
111 | gpio, label ? label : "?"); | ||
112 | return -EBUSY; | ||
113 | } | ||
114 | |||
115 | return 0; | ||
116 | } | ||
117 | |||
118 | EXPORT_SYMBOL(imx_gpio_request); | ||
119 | |||
120 | void imx_gpio_free(unsigned gpio) | ||
121 | { | ||
122 | if(gpio >= (GPIO_PORT_MAX + 1) * 32) | ||
123 | return; | ||
124 | |||
125 | clear_bit(gpio, imx_gpio_alloc_map); | ||
126 | } | ||
127 | |||
128 | EXPORT_SYMBOL(imx_gpio_free); | ||
129 | |||
130 | int imx_gpio_direction_input(unsigned gpio) | ||
131 | { | ||
132 | imx_gpio_mode(gpio | GPIO_IN | GPIO_GIUS | GPIO_DR); | ||
133 | return 0; | ||
134 | } | ||
135 | |||
136 | EXPORT_SYMBOL(imx_gpio_direction_input); | ||
137 | |||
138 | int imx_gpio_direction_output(unsigned gpio, int value) | ||
139 | { | ||
140 | imx_gpio_set_value(gpio, value); | ||
141 | imx_gpio_mode(gpio | GPIO_OUT | GPIO_GIUS | GPIO_DR); | ||
142 | return 0; | ||
143 | } | ||
144 | |||
145 | EXPORT_SYMBOL(imx_gpio_direction_output); | ||
146 | |||
147 | int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count, | ||
148 | int alloc_mode, const char *label) | ||
149 | { | ||
150 | const int *p = pin_list; | ||
151 | int i; | ||
152 | unsigned gpio; | ||
153 | unsigned mode; | ||
154 | |||
155 | for (i = 0; i < count; i++) { | ||
156 | gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); | ||
157 | mode = *p & ~(GPIO_PIN_MASK | GPIO_PORT_MASK); | ||
158 | |||
159 | if (gpio >= (GPIO_PORT_MAX + 1) * 32) | ||
160 | goto setup_error; | ||
161 | |||
162 | if (alloc_mode & IMX_GPIO_ALLOC_MODE_RELEASE) | ||
163 | imx_gpio_free(gpio); | ||
164 | else if (!(alloc_mode & IMX_GPIO_ALLOC_MODE_NO_ALLOC)) | ||
165 | if (imx_gpio_request(gpio, label)) | ||
166 | if (!(alloc_mode & IMX_GPIO_ALLOC_MODE_TRY_ALLOC)) | ||
167 | goto setup_error; | ||
168 | |||
169 | if (!(alloc_mode & (IMX_GPIO_ALLOC_MODE_ALLOC_ONLY | | ||
170 | IMX_GPIO_ALLOC_MODE_RELEASE))) | ||
171 | imx_gpio_mode(gpio | mode); | ||
172 | |||
173 | p++; | ||
174 | } | ||
175 | return 0; | ||
176 | |||
177 | setup_error: | ||
178 | if(alloc_mode & (IMX_GPIO_ALLOC_MODE_NO_ALLOC | | ||
179 | IMX_GPIO_ALLOC_MODE_TRY_ALLOC)) | ||
180 | return -EINVAL; | ||
181 | |||
182 | while (p != pin_list) { | ||
183 | p--; | ||
184 | gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); | ||
185 | imx_gpio_free(gpio); | ||
186 | } | ||
187 | |||
188 | return -EINVAL; | ||
189 | } | ||
190 | |||
191 | EXPORT_SYMBOL(imx_gpio_setup_multiple_pins); | ||
192 | |||
193 | void __imx_gpio_set_value(unsigned gpio, int value) | ||
194 | { | ||
195 | imx_gpio_set_value_inline(gpio, value); | ||
196 | } | ||
197 | |||
198 | EXPORT_SYMBOL(__imx_gpio_set_value); | ||
199 | |||
200 | int imx_gpio_to_irq(unsigned gpio) | ||
201 | { | ||
202 | return IRQ_GPIOA(0) + gpio; | ||
203 | } | ||
204 | |||
205 | EXPORT_SYMBOL(imx_gpio_to_irq); | ||
206 | |||
207 | int imx_irq_to_gpio(unsigned irq) | ||
208 | { | ||
209 | if (irq < IRQ_GPIOA(0)) | ||
210 | return -EINVAL; | ||
211 | return irq - IRQ_GPIOA(0); | ||
212 | } | ||
213 | |||
214 | EXPORT_SYMBOL(imx_irq_to_gpio); | ||
215 | |||
216 | static struct resource imx_mmc_resources[] = { | ||
217 | [0] = { | ||
218 | .start = 0x00214000, | ||
219 | .end = 0x002140FF, | ||
220 | .flags = IORESOURCE_MEM, | ||
221 | }, | ||
222 | [1] = { | ||
223 | .start = (SDHC_INT), | ||
224 | .end = (SDHC_INT), | ||
225 | .flags = IORESOURCE_IRQ, | ||
226 | }, | ||
227 | }; | ||
228 | |||
229 | static u64 imxmmmc_dmamask = 0xffffffffUL; | ||
230 | |||
231 | static struct platform_device imx_mmc_device = { | ||
232 | .name = "imx-mmc", | ||
233 | .id = 0, | ||
234 | .dev = { | ||
235 | .dma_mask = &imxmmmc_dmamask, | ||
236 | .coherent_dma_mask = 0xffffffff, | ||
237 | }, | ||
238 | .num_resources = ARRAY_SIZE(imx_mmc_resources), | ||
239 | .resource = imx_mmc_resources, | ||
240 | }; | ||
241 | |||
242 | void __init imx_set_mmc_info(struct imxmmc_platform_data *info) | ||
243 | { | ||
244 | imx_mmc_device.dev.platform_data = info; | ||
245 | } | ||
246 | |||
247 | static struct platform_device *devices[] __initdata = { | ||
248 | &imx_mmc_device, | ||
249 | }; | ||
250 | |||
251 | static struct map_desc imx_io_desc[] __initdata = { | ||
252 | { | ||
253 | .virtual = IMX_IO_BASE, | ||
254 | .pfn = __phys_to_pfn(IMX_IO_PHYS), | ||
255 | .length = IMX_IO_SIZE, | ||
256 | .type = MT_DEVICE | ||
257 | } | ||
258 | }; | ||
259 | |||
260 | void __init | ||
261 | imx_map_io(void) | ||
262 | { | ||
263 | iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); | ||
264 | } | ||
265 | |||
266 | static int __init imx_init(void) | ||
267 | { | ||
268 | return platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
269 | } | ||
270 | |||
271 | subsys_initcall(imx_init); | ||
diff --git a/arch/arm/mach-imx/generic.h b/arch/arm/mach-imx/generic.h deleted file mode 100644 index e91003e4bef3..000000000000 --- a/arch/arm/mach-imx/generic.h +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-imx/generic.h | ||
3 | * | ||
4 | * Author: Sascha Hauer <sascha@saschahauer.de> | ||
5 | * Copyright: Synertronixx GmbH | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | extern void __init imx_map_io(void); | ||
13 | extern void __init imx_init_irq(void); | ||
14 | |||
15 | struct sys_timer; | ||
16 | extern struct sys_timer imx_timer; | ||
diff --git a/arch/arm/mach-imx/include/mach/debug-macro.S b/arch/arm/mach-imx/include/mach/debug-macro.S deleted file mode 100644 index 87802bbfe633..000000000000 --- a/arch/arm/mach-imx/include/mach/debug-macro.S +++ /dev/null | |||
@@ -1,34 +0,0 @@ | |||
1 | /* arch/arm/mach-imx/include/mach/debug-macro.S | ||
2 | * | ||
3 | * Debugging macro include header | ||
4 | * | ||
5 | * Copyright (C) 1994-1999 Russell King | ||
6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | .macro addruart,rx | ||
15 | mrc p15, 0, \rx, c1, c0 | ||
16 | tst \rx, #1 @ MMU enabled? | ||
17 | moveq \rx, #0x00000000 @ physical | ||
18 | movne \rx, #0xe0000000 @ virtual | ||
19 | orreq \rx, \rx, #0x00200000 @ physical | ||
20 | orr \rx, \rx, #0x00006000 @ UART1 offset | ||
21 | .endm | ||
22 | |||
23 | .macro senduart,rd,rx | ||
24 | str \rd, [\rx, #0x40] @ TXDATA | ||
25 | .endm | ||
26 | |||
27 | .macro waituart,rd,rx | ||
28 | .endm | ||
29 | |||
30 | .macro busyuart,rd,rx | ||
31 | 1002: ldr \rd, [\rx, #0x98] @ SR2 | ||
32 | tst \rd, #1 << 3 @ TXDC | ||
33 | beq 1002b @ wait until transmit done | ||
34 | .endm | ||
diff --git a/arch/arm/mach-imx/include/mach/dma.h b/arch/arm/mach-imx/include/mach/dma.h deleted file mode 100644 index 621ff2c730f2..000000000000 --- a/arch/arm/mach-imx/include/mach/dma.h +++ /dev/null | |||
@@ -1,56 +0,0 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/imxads/dma.h | ||
3 | * | ||
4 | * Copyright (C) 1997,1998 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | |||
21 | #ifndef __ASM_ARCH_DMA_H | ||
22 | #define __ASM_ARCH_DMA_H | ||
23 | |||
24 | typedef enum { | ||
25 | DMA_PRIO_HIGH = 0, | ||
26 | DMA_PRIO_MEDIUM = 1, | ||
27 | DMA_PRIO_LOW = 2 | ||
28 | } imx_dma_prio; | ||
29 | |||
30 | #define DMA_REQ_UART3_T 2 | ||
31 | #define DMA_REQ_UART3_R 3 | ||
32 | #define DMA_REQ_SSI2_T 4 | ||
33 | #define DMA_REQ_SSI2_R 5 | ||
34 | #define DMA_REQ_CSI_STAT 6 | ||
35 | #define DMA_REQ_CSI_R 7 | ||
36 | #define DMA_REQ_MSHC 8 | ||
37 | #define DMA_REQ_DSPA_DCT_DOUT 9 | ||
38 | #define DMA_REQ_DSPA_DCT_DIN 10 | ||
39 | #define DMA_REQ_DSPA_MAC 11 | ||
40 | #define DMA_REQ_EXT 12 | ||
41 | #define DMA_REQ_SDHC 13 | ||
42 | #define DMA_REQ_SPI1_R 14 | ||
43 | #define DMA_REQ_SPI1_T 15 | ||
44 | #define DMA_REQ_SSI_T 16 | ||
45 | #define DMA_REQ_SSI_R 17 | ||
46 | #define DMA_REQ_ASP_DAC 18 | ||
47 | #define DMA_REQ_ASP_ADC 19 | ||
48 | #define DMA_REQ_USP_EP(x) (20+(x)) | ||
49 | #define DMA_REQ_SPI2_R 26 | ||
50 | #define DMA_REQ_SPI2_T 27 | ||
51 | #define DMA_REQ_UART2_T 28 | ||
52 | #define DMA_REQ_UART2_R 29 | ||
53 | #define DMA_REQ_UART1_T 30 | ||
54 | #define DMA_REQ_UART1_R 31 | ||
55 | |||
56 | #endif /* _ASM_ARCH_DMA_H */ | ||
diff --git a/arch/arm/mach-imx/include/mach/entry-macro.S b/arch/arm/mach-imx/include/mach/entry-macro.S deleted file mode 100644 index e4db679f7766..000000000000 --- a/arch/arm/mach-imx/include/mach/entry-macro.S +++ /dev/null | |||
@@ -1,32 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-imx/include/mach/entry-macro.S | ||
3 | * | ||
4 | * Low-level IRQ helper macros for iMX-based platforms | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public | ||
7 | * License version 2. This program is licensed "as is" without any | ||
8 | * warranty of any kind, whether express or implied. | ||
9 | */ | ||
10 | #include <mach/hardware.h> | ||
11 | |||
12 | .macro disable_fiq | ||
13 | .endm | ||
14 | |||
15 | .macro get_irqnr_preamble, base, tmp | ||
16 | .endm | ||
17 | |||
18 | .macro arch_ret_to_user, tmp1, tmp2 | ||
19 | .endm | ||
20 | |||
21 | #define AITC_NIVECSR 0x40 | ||
22 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
23 | ldr \base, =IO_ADDRESS(IMX_AITC_BASE) | ||
24 | @ Load offset & priority of the highest priority | ||
25 | @ interrupt pending. | ||
26 | ldr \irqstat, [\base, #AITC_NIVECSR] | ||
27 | @ Shift off the priority leaving the offset or | ||
28 | @ "interrupt number", use arithmetic shift to | ||
29 | @ transform illegal source (0xffff) as -1 | ||
30 | mov \irqnr, \irqstat, asr #16 | ||
31 | adds \tmp, \irqnr, #1 | ||
32 | .endm | ||
diff --git a/arch/arm/mach-imx/include/mach/gpio.h b/arch/arm/mach-imx/include/mach/gpio.h deleted file mode 100644 index 6c2942f82922..000000000000 --- a/arch/arm/mach-imx/include/mach/gpio.h +++ /dev/null | |||
@@ -1,106 +0,0 @@ | |||
1 | #ifndef _IMX_GPIO_H | ||
2 | |||
3 | #include <linux/kernel.h> | ||
4 | #include <mach/hardware.h> | ||
5 | #include <mach/imx-regs.h> | ||
6 | |||
7 | #define IMX_GPIO_ALLOC_MODE_NORMAL 0 | ||
8 | #define IMX_GPIO_ALLOC_MODE_NO_ALLOC 1 | ||
9 | #define IMX_GPIO_ALLOC_MODE_TRY_ALLOC 2 | ||
10 | #define IMX_GPIO_ALLOC_MODE_ALLOC_ONLY 4 | ||
11 | #define IMX_GPIO_ALLOC_MODE_RELEASE 8 | ||
12 | |||
13 | extern int imx_gpio_request(unsigned gpio, const char *label); | ||
14 | |||
15 | extern void imx_gpio_free(unsigned gpio); | ||
16 | |||
17 | extern int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count, | ||
18 | int alloc_mode, const char *label); | ||
19 | |||
20 | extern int imx_gpio_direction_input(unsigned gpio); | ||
21 | |||
22 | extern int imx_gpio_direction_output(unsigned gpio, int value); | ||
23 | |||
24 | extern void __imx_gpio_set_value(unsigned gpio, int value); | ||
25 | |||
26 | static inline int imx_gpio_get_value(unsigned gpio) | ||
27 | { | ||
28 | return SSR(gpio >> GPIO_PORT_SHIFT) & (1 << (gpio & GPIO_PIN_MASK)); | ||
29 | } | ||
30 | |||
31 | static inline void imx_gpio_set_value_inline(unsigned gpio, int value) | ||
32 | { | ||
33 | unsigned long flags; | ||
34 | |||
35 | raw_local_irq_save(flags); | ||
36 | if(value) | ||
37 | DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK)); | ||
38 | else | ||
39 | DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK)); | ||
40 | raw_local_irq_restore(flags); | ||
41 | } | ||
42 | |||
43 | static inline void imx_gpio_set_value(unsigned gpio, int value) | ||
44 | { | ||
45 | if(__builtin_constant_p(gpio)) | ||
46 | imx_gpio_set_value_inline(gpio, value); | ||
47 | else | ||
48 | __imx_gpio_set_value(gpio, value); | ||
49 | } | ||
50 | |||
51 | extern int imx_gpio_to_irq(unsigned gpio); | ||
52 | |||
53 | extern int imx_irq_to_gpio(unsigned irq); | ||
54 | |||
55 | /*-------------------------------------------------------------------------*/ | ||
56 | |||
57 | /* Wrappers for "new style" GPIO calls. These calls i.MX specific versions | ||
58 | * to allow future extension of GPIO logic. | ||
59 | */ | ||
60 | |||
61 | static inline int gpio_request(unsigned gpio, const char *label) | ||
62 | { | ||
63 | return imx_gpio_request(gpio, label); | ||
64 | } | ||
65 | |||
66 | static inline void gpio_free(unsigned gpio) | ||
67 | { | ||
68 | might_sleep(); | ||
69 | |||
70 | imx_gpio_free(gpio); | ||
71 | } | ||
72 | |||
73 | static inline int gpio_direction_input(unsigned gpio) | ||
74 | { | ||
75 | return imx_gpio_direction_input(gpio); | ||
76 | } | ||
77 | |||
78 | static inline int gpio_direction_output(unsigned gpio, int value) | ||
79 | { | ||
80 | return imx_gpio_direction_output(gpio, value); | ||
81 | } | ||
82 | |||
83 | static inline int gpio_get_value(unsigned gpio) | ||
84 | { | ||
85 | return imx_gpio_get_value(gpio); | ||
86 | } | ||
87 | |||
88 | static inline void gpio_set_value(unsigned gpio, int value) | ||
89 | { | ||
90 | imx_gpio_set_value(gpio, value); | ||
91 | } | ||
92 | |||
93 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | ||
94 | |||
95 | static inline int gpio_to_irq(unsigned gpio) | ||
96 | { | ||
97 | return imx_gpio_to_irq(gpio); | ||
98 | } | ||
99 | |||
100 | static inline int irq_to_gpio(unsigned irq) | ||
101 | { | ||
102 | return imx_irq_to_gpio(irq); | ||
103 | } | ||
104 | |||
105 | |||
106 | #endif | ||
diff --git a/arch/arm/mach-imx/include/mach/hardware.h b/arch/arm/mach-imx/include/mach/hardware.h deleted file mode 100644 index c73e9e724c75..000000000000 --- a/arch/arm/mach-imx/include/mach/hardware.h +++ /dev/null | |||
@@ -1,91 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-imx/include/mach/hardware.h | ||
3 | * | ||
4 | * Copyright (C) 1999 ARM Limited. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | #ifndef __ASM_ARCH_HARDWARE_H | ||
21 | #define __ASM_ARCH_HARDWARE_H | ||
22 | |||
23 | #include <asm/sizes.h> | ||
24 | #include "imx-regs.h" | ||
25 | |||
26 | #ifndef __ASSEMBLY__ | ||
27 | # define __REG(x) (*((volatile u32 *)IO_ADDRESS(x))) | ||
28 | |||
29 | # define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) | ||
30 | #endif | ||
31 | |||
32 | /* | ||
33 | * Memory map | ||
34 | */ | ||
35 | |||
36 | #define IMX_IO_PHYS 0x00200000 | ||
37 | #define IMX_IO_SIZE 0x00100000 | ||
38 | #define IMX_IO_BASE 0xe0000000 | ||
39 | |||
40 | #define IMX_CS0_PHYS 0x10000000 | ||
41 | #define IMX_CS0_SIZE 0x02000000 | ||
42 | #define IMX_CS0_VIRT 0xe8000000 | ||
43 | |||
44 | #define IMX_CS1_PHYS 0x12000000 | ||
45 | #define IMX_CS1_SIZE 0x01000000 | ||
46 | #define IMX_CS1_VIRT 0xea000000 | ||
47 | |||
48 | #define IMX_CS2_PHYS 0x13000000 | ||
49 | #define IMX_CS2_SIZE 0x01000000 | ||
50 | #define IMX_CS2_VIRT 0xeb000000 | ||
51 | |||
52 | #define IMX_CS3_PHYS 0x14000000 | ||
53 | #define IMX_CS3_SIZE 0x01000000 | ||
54 | #define IMX_CS3_VIRT 0xec000000 | ||
55 | |||
56 | #define IMX_CS4_PHYS 0x15000000 | ||
57 | #define IMX_CS4_SIZE 0x01000000 | ||
58 | #define IMX_CS4_VIRT 0xed000000 | ||
59 | |||
60 | #define IMX_CS5_PHYS 0x16000000 | ||
61 | #define IMX_CS5_SIZE 0x01000000 | ||
62 | #define IMX_CS5_VIRT 0xee000000 | ||
63 | |||
64 | #define IMX_FB_VIRT 0xF1000000 | ||
65 | #define IMX_FB_SIZE (256*1024) | ||
66 | |||
67 | /* macro to get at IO space when running virtually */ | ||
68 | #define IO_ADDRESS(x) ((x) | IMX_IO_BASE) | ||
69 | |||
70 | #ifndef __ASSEMBLY__ | ||
71 | /* | ||
72 | * Handy routine to set GPIO functions | ||
73 | */ | ||
74 | extern void imx_gpio_mode( int gpio_mode ); | ||
75 | |||
76 | #endif | ||
77 | |||
78 | #define MAXIRQNUM 62 | ||
79 | #define MAXFIQNUM 62 | ||
80 | #define MAXSWINUM 62 | ||
81 | |||
82 | /* | ||
83 | * Use SDRAM for memory | ||
84 | */ | ||
85 | #define MEM_SIZE 0x01000000 | ||
86 | |||
87 | #ifdef CONFIG_ARCH_MX1ADS | ||
88 | #include "mx1ads.h" | ||
89 | #endif | ||
90 | |||
91 | #endif | ||
diff --git a/arch/arm/mach-imx/include/mach/imx-dma.h b/arch/arm/mach-imx/include/mach/imx-dma.h deleted file mode 100644 index bbe54df7f0de..000000000000 --- a/arch/arm/mach-imx/include/mach/imx-dma.h +++ /dev/null | |||
@@ -1,98 +0,0 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/imxads/dma.h | ||
3 | * | ||
4 | * Copyright (C) 1997,1998 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | |||
21 | #include <mach/dma.h> | ||
22 | |||
23 | #ifndef __ASM_ARCH_IMX_DMA_H | ||
24 | #define __ASM_ARCH_IMX_DMA_H | ||
25 | |||
26 | #define IMX_DMA_CHANNELS 11 | ||
27 | |||
28 | /* | ||
29 | * struct imx_dma_channel - i.MX specific DMA extension | ||
30 | * @name: name specified by DMA client | ||
31 | * @irq_handler: client callback for end of transfer | ||
32 | * @err_handler: client callback for error condition | ||
33 | * @data: clients context data for callbacks | ||
34 | * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE | ||
35 | * @sg: pointer to the actual read/written chunk for scatter-gather emulation | ||
36 | * @sgbc: counter of processed bytes in the actual read/written chunk | ||
37 | * @resbytes: total residual number of bytes to transfer | ||
38 | * (it can be lower or same as sum of SG mapped chunk sizes) | ||
39 | * @sgcount: number of chunks to be read/written | ||
40 | * | ||
41 | * Structure is used for IMX DMA processing. It would be probably good | ||
42 | * @struct dma_struct in the future for external interfacing and use | ||
43 | * @struct imx_dma_channel only as extension to it. | ||
44 | */ | ||
45 | |||
46 | struct imx_dma_channel { | ||
47 | const char *name; | ||
48 | void (*irq_handler) (int, void *); | ||
49 | void (*err_handler) (int, void *, int errcode); | ||
50 | void *data; | ||
51 | unsigned int dma_mode; | ||
52 | struct scatterlist *sg; | ||
53 | unsigned int sgbc; | ||
54 | unsigned int sgcount; | ||
55 | unsigned int resbytes; | ||
56 | int dma_num; | ||
57 | }; | ||
58 | |||
59 | extern struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; | ||
60 | |||
61 | #define IMX_DMA_ERR_BURST 1 | ||
62 | #define IMX_DMA_ERR_REQUEST 2 | ||
63 | #define IMX_DMA_ERR_TRANSFER 4 | ||
64 | #define IMX_DMA_ERR_BUFFER 8 | ||
65 | |||
66 | /* The type to distinguish channel numbers parameter from ordinal int type */ | ||
67 | typedef int imx_dmach_t; | ||
68 | |||
69 | #define DMA_MODE_READ 0 | ||
70 | #define DMA_MODE_WRITE 1 | ||
71 | #define DMA_MODE_MASK 1 | ||
72 | |||
73 | int | ||
74 | imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, | ||
75 | unsigned int dma_length, unsigned int dev_addr, unsigned int dmamode); | ||
76 | |||
77 | int | ||
78 | imx_dma_setup_sg(imx_dmach_t dma_ch, | ||
79 | struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, | ||
80 | unsigned int dev_addr, unsigned int dmamode); | ||
81 | |||
82 | int | ||
83 | imx_dma_setup_handlers(imx_dmach_t dma_ch, | ||
84 | void (*irq_handler) (int, void *), | ||
85 | void (*err_handler) (int, void *, int), void *data); | ||
86 | |||
87 | void imx_dma_enable(imx_dmach_t dma_ch); | ||
88 | |||
89 | void imx_dma_disable(imx_dmach_t dma_ch); | ||
90 | |||
91 | int imx_dma_request(imx_dmach_t dma_ch, const char *name); | ||
92 | |||
93 | void imx_dma_free(imx_dmach_t dma_ch); | ||
94 | |||
95 | imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio); | ||
96 | |||
97 | |||
98 | #endif /* _ASM_ARCH_IMX_DMA_H */ | ||
diff --git a/arch/arm/mach-imx/include/mach/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h deleted file mode 100644 index 490297fc0e38..000000000000 --- a/arch/arm/mach-imx/include/mach/imx-regs.h +++ /dev/null | |||
@@ -1,376 +0,0 @@ | |||
1 | #ifndef _IMX_REGS_H | ||
2 | #define _IMX_REGS_H | ||
3 | /* ------------------------------------------------------------------------ | ||
4 | * Motorola IMX system registers | ||
5 | * ------------------------------------------------------------------------ | ||
6 | * | ||
7 | */ | ||
8 | |||
9 | /* | ||
10 | * Register BASEs, based on OFFSETs | ||
11 | * | ||
12 | */ | ||
13 | #define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) | ||
14 | #define IMX_WDT_BASE (0x01000 + IMX_IO_BASE) | ||
15 | #define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE) | ||
16 | #define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) | ||
17 | #define IMX_RTC_BASE (0x04000 + IMX_IO_BASE) | ||
18 | #define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) | ||
19 | #define IMX_UART1_BASE (0x06000 + IMX_IO_BASE) | ||
20 | #define IMX_UART2_BASE (0x07000 + IMX_IO_BASE) | ||
21 | #define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) | ||
22 | #define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) | ||
23 | #define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) | ||
24 | #define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) | ||
25 | #define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) | ||
26 | #define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) | ||
27 | #define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) | ||
28 | #define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) | ||
29 | #define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) | ||
30 | #define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) | ||
31 | #define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) | ||
32 | #define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) | ||
33 | #define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) | ||
34 | #define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) | ||
35 | #define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) | ||
36 | #define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) | ||
37 | #define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) | ||
38 | #define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) | ||
39 | #define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) | ||
40 | #define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) | ||
41 | |||
42 | /* PLL registers */ | ||
43 | #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ | ||
44 | #define CSCR_SPLL_RESTART (1<<22) | ||
45 | #define CSCR_MPLL_RESTART (1<<21) | ||
46 | #define CSCR_SYSTEM_SEL (1<<16) | ||
47 | #define CSCR_BCLK_DIV (0xf<<10) | ||
48 | #define CSCR_MPU_PRESC (1<<15) | ||
49 | #define CSCR_SPEN (1<<1) | ||
50 | #define CSCR_MPEN (1<<0) | ||
51 | |||
52 | #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ | ||
53 | #define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ | ||
54 | #define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ | ||
55 | #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ | ||
56 | #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ | ||
57 | |||
58 | /* | ||
59 | * GPIO Module and I/O Multiplexer | ||
60 | * x = 0..3 for reg_A, reg_B, reg_C, reg_D | ||
61 | */ | ||
62 | #define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8) | ||
63 | #define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8) | ||
64 | #define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8) | ||
65 | #define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8) | ||
66 | #define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8) | ||
67 | #define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8) | ||
68 | #define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8) | ||
69 | #define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8) | ||
70 | #define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8) | ||
71 | #define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8) | ||
72 | #define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8) | ||
73 | #define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8) | ||
74 | #define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8) | ||
75 | #define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8) | ||
76 | #define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8) | ||
77 | #define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) | ||
78 | #define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) | ||
79 | |||
80 | #define GPIO_PORT_MAX 3 | ||
81 | |||
82 | #define GPIO_PIN_MASK 0x1f | ||
83 | #define GPIO_PORT_MASK (0x3 << 5) | ||
84 | |||
85 | #define GPIO_PORT_SHIFT 5 | ||
86 | #define GPIO_PORTA (0<<5) | ||
87 | #define GPIO_PORTB (1<<5) | ||
88 | #define GPIO_PORTC (2<<5) | ||
89 | #define GPIO_PORTD (3<<5) | ||
90 | |||
91 | #define GPIO_OUT (1<<7) | ||
92 | #define GPIO_IN (0<<7) | ||
93 | #define GPIO_PUEN (1<<8) | ||
94 | |||
95 | #define GPIO_PF (0<<9) | ||
96 | #define GPIO_AF (1<<9) | ||
97 | |||
98 | #define GPIO_OCR_SHIFT 10 | ||
99 | #define GPIO_OCR_MASK (3<<10) | ||
100 | #define GPIO_AIN (0<<10) | ||
101 | #define GPIO_BIN (1<<10) | ||
102 | #define GPIO_CIN (2<<10) | ||
103 | #define GPIO_DR (3<<10) | ||
104 | |||
105 | #define GPIO_AOUT_SHIFT 12 | ||
106 | #define GPIO_AOUT_MASK (3<<12) | ||
107 | #define GPIO_AOUT (0<<12) | ||
108 | #define GPIO_AOUT_ISR (1<<12) | ||
109 | #define GPIO_AOUT_0 (2<<12) | ||
110 | #define GPIO_AOUT_1 (3<<12) | ||
111 | |||
112 | #define GPIO_BOUT_SHIFT 14 | ||
113 | #define GPIO_BOUT_MASK (3<<14) | ||
114 | #define GPIO_BOUT (0<<14) | ||
115 | #define GPIO_BOUT_ISR (1<<14) | ||
116 | #define GPIO_BOUT_0 (2<<14) | ||
117 | #define GPIO_BOUT_1 (3<<14) | ||
118 | |||
119 | #define GPIO_GIUS (1<<16) | ||
120 | |||
121 | /* assignements for GPIO alternate/primary functions */ | ||
122 | |||
123 | /* FIXME: This list is not completed. The correct directions are | ||
124 | * missing on some (many) pins | ||
125 | */ | ||
126 | #define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 ) | ||
127 | #define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) | ||
128 | #define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 ) | ||
129 | #define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) | ||
130 | #define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) | ||
131 | #define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) | ||
132 | #define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) | ||
133 | #define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) | ||
134 | #define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) | ||
135 | #define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) | ||
136 | #define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) | ||
137 | #define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) | ||
138 | #define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) | ||
139 | #define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) | ||
140 | #define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) | ||
141 | #define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) | ||
142 | #define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) | ||
143 | #define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) | ||
144 | #define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) | ||
145 | #define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) | ||
146 | #define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 ) | ||
147 | #define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) | ||
148 | #define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) | ||
149 | #define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) | ||
150 | #define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) | ||
151 | #define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) | ||
152 | #define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) | ||
153 | #define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) | ||
154 | #define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) | ||
155 | #define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) | ||
156 | #define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) | ||
157 | #define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) | ||
158 | #define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) | ||
159 | #define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) | ||
160 | #define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) | ||
161 | #define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) | ||
162 | #define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) | ||
163 | #define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) | ||
164 | #define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) | ||
165 | #define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) | ||
166 | #define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) | ||
167 | #define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) | ||
168 | #define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) | ||
169 | #define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) | ||
170 | #define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) | ||
171 | #define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) | ||
172 | #define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) | ||
173 | #define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) | ||
174 | #define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) | ||
175 | #define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 ) | ||
176 | #define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) | ||
177 | #define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 ) | ||
178 | #define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) | ||
179 | #define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 ) | ||
180 | #define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) | ||
181 | #define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) | ||
182 | #define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) | ||
183 | #define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) | ||
184 | #define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) | ||
185 | #define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) | ||
186 | #define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) | ||
187 | #define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) | ||
188 | #define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) | ||
189 | #define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) | ||
190 | #define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) | ||
191 | #define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) | ||
192 | #define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) | ||
193 | #define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) | ||
194 | #define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) | ||
195 | #define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) | ||
196 | #define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) | ||
197 | #define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) | ||
198 | #define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) | ||
199 | #define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) | ||
200 | #define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) | ||
201 | #define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) | ||
202 | #define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) | ||
203 | #define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) | ||
204 | #define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) | ||
205 | #define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) | ||
206 | #define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) | ||
207 | #define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) | ||
208 | #define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) | ||
209 | #define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) | ||
210 | #define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) | ||
211 | #define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) | ||
212 | #define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) | ||
213 | #define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) | ||
214 | #define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 ) | ||
215 | #define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 ) | ||
216 | #define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 ) | ||
217 | #define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 ) | ||
218 | #define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 ) | ||
219 | #define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 ) | ||
220 | #define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 ) | ||
221 | #define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31) | ||
222 | #define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) | ||
223 | #define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) | ||
224 | #define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) | ||
225 | #define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 ) | ||
226 | #define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) | ||
227 | #define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) | ||
228 | #define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 ) | ||
229 | #define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) | ||
230 | #define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) | ||
231 | #define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 ) | ||
232 | #define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) | ||
233 | #define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) | ||
234 | #define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 ) | ||
235 | #define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) | ||
236 | #define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) | ||
237 | #define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) | ||
238 | #define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) | ||
239 | #define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) | ||
240 | #define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) | ||
241 | #define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) | ||
242 | #define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) | ||
243 | #define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) | ||
244 | #define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) | ||
245 | #define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) | ||
246 | #define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) | ||
247 | #define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) | ||
248 | #define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) | ||
249 | #define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) | ||
250 | #define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) | ||
251 | #define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) | ||
252 | #define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) | ||
253 | #define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) | ||
254 | #define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) | ||
255 | #define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) | ||
256 | #define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 ) | ||
257 | |||
258 | /* | ||
259 | * PWM controller | ||
260 | */ | ||
261 | #define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */ | ||
262 | #define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */ | ||
263 | #define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */ | ||
264 | #define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */ | ||
265 | |||
266 | #define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */ | ||
267 | #define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */ | ||
268 | #define PWMC_SWR (0x01<<16) /* Software Reset */ | ||
269 | #define PWMC_CLKSRC (0x01<<15) /* Clock Source */ | ||
270 | #define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */ | ||
271 | #define PWMC_IRQ (0x01<< 7) /* Interrupt Request */ | ||
272 | #define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */ | ||
273 | #define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */ | ||
274 | #define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */ | ||
275 | #define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */ | ||
276 | #define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */ | ||
277 | |||
278 | #define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */ | ||
279 | #define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */ | ||
280 | #define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */ | ||
281 | |||
282 | /* | ||
283 | * DMA Controller | ||
284 | */ | ||
285 | #define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */ | ||
286 | #define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */ | ||
287 | #define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */ | ||
288 | #define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */ | ||
289 | #define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */ | ||
290 | #define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */ | ||
291 | #define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */ | ||
292 | #define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */ | ||
293 | #define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */ | ||
294 | #define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */ | ||
295 | #define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */ | ||
296 | #define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */ | ||
297 | #define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */ | ||
298 | #define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */ | ||
299 | #define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */ | ||
300 | #define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */ | ||
301 | #define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */ | ||
302 | #define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ | ||
303 | #define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */ | ||
304 | #define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */ | ||
305 | #define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */ | ||
306 | #define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */ | ||
307 | |||
308 | #define DCR_DRST (1<<1) | ||
309 | #define DCR_DEN (1<<0) | ||
310 | #define DBTOCR_EN (1<<15) | ||
311 | #define DBTOCR_CNT(x) ((x) & 0x7fff ) | ||
312 | #define CNTR_CNT(x) ((x) & 0xffffff ) | ||
313 | #define CCR_DMOD_LINEAR ( 0x0 << 12 ) | ||
314 | #define CCR_DMOD_2D ( 0x1 << 12 ) | ||
315 | #define CCR_DMOD_FIFO ( 0x2 << 12 ) | ||
316 | #define CCR_DMOD_EOBFIFO ( 0x3 << 12 ) | ||
317 | #define CCR_SMOD_LINEAR ( 0x0 << 10 ) | ||
318 | #define CCR_SMOD_2D ( 0x1 << 10 ) | ||
319 | #define CCR_SMOD_FIFO ( 0x2 << 10 ) | ||
320 | #define CCR_SMOD_EOBFIFO ( 0x3 << 10 ) | ||
321 | #define CCR_MDIR_DEC (1<<9) | ||
322 | #define CCR_MSEL_B (1<<8) | ||
323 | #define CCR_DSIZ_32 ( 0x0 << 6 ) | ||
324 | #define CCR_DSIZ_8 ( 0x1 << 6 ) | ||
325 | #define CCR_DSIZ_16 ( 0x2 << 6 ) | ||
326 | #define CCR_SSIZ_32 ( 0x0 << 4 ) | ||
327 | #define CCR_SSIZ_8 ( 0x1 << 4 ) | ||
328 | #define CCR_SSIZ_16 ( 0x2 << 4 ) | ||
329 | #define CCR_REN (1<<3) | ||
330 | #define CCR_RPT (1<<2) | ||
331 | #define CCR_FRC (1<<1) | ||
332 | #define CCR_CEN (1<<0) | ||
333 | #define RTOR_EN (1<<15) | ||
334 | #define RTOR_CLK (1<<14) | ||
335 | #define RTOR_PSC (1<<13) | ||
336 | |||
337 | /* | ||
338 | * Interrupt controller | ||
339 | */ | ||
340 | |||
341 | #define IMX_INTCNTL __REG(IMX_AITC_BASE+0x00) | ||
342 | #define INTCNTL_FIAD (1<<19) | ||
343 | #define INTCNTL_NIAD (1<<20) | ||
344 | |||
345 | #define IMX_NIMASK __REG(IMX_AITC_BASE+0x04) | ||
346 | #define IMX_INTENNUM __REG(IMX_AITC_BASE+0x08) | ||
347 | #define IMX_INTDISNUM __REG(IMX_AITC_BASE+0x0c) | ||
348 | #define IMX_INTENABLEH __REG(IMX_AITC_BASE+0x10) | ||
349 | #define IMX_INTENABLEL __REG(IMX_AITC_BASE+0x14) | ||
350 | |||
351 | /* | ||
352 | * General purpose timers | ||
353 | */ | ||
354 | #define IMX_TCTL(x) __REG( 0x00 + (x)) | ||
355 | #define TCTL_SWR (1<<15) | ||
356 | #define TCTL_FRR (1<<8) | ||
357 | #define TCTL_CAP_RIS (1<<6) | ||
358 | #define TCTL_CAP_FAL (2<<6) | ||
359 | #define TCTL_CAP_RIS_FAL (3<<6) | ||
360 | #define TCTL_OM (1<<5) | ||
361 | #define TCTL_IRQEN (1<<4) | ||
362 | #define TCTL_CLK_PCLK1 (1<<1) | ||
363 | #define TCTL_CLK_PCLK1_16 (2<<1) | ||
364 | #define TCTL_CLK_TIN (3<<1) | ||
365 | #define TCTL_CLK_32 (4<<1) | ||
366 | #define TCTL_TEN (1<<0) | ||
367 | |||
368 | #define IMX_TPRER(x) __REG( 0x04 + (x)) | ||
369 | #define IMX_TCMP(x) __REG( 0x08 + (x)) | ||
370 | #define IMX_TCR(x) __REG( 0x0C + (x)) | ||
371 | #define IMX_TCN(x) __REG( 0x10 + (x)) | ||
372 | #define IMX_TSTAT(x) __REG( 0x14 + (x)) | ||
373 | #define TSTAT_CAPT (1<<1) | ||
374 | #define TSTAT_COMP (1<<0) | ||
375 | |||
376 | #endif // _IMX_REGS_H | ||
diff --git a/arch/arm/mach-imx/include/mach/imx-uart.h b/arch/arm/mach-imx/include/mach/imx-uart.h deleted file mode 100644 index d54eb1d48026..000000000000 --- a/arch/arm/mach-imx/include/mach/imx-uart.h +++ /dev/null | |||
@@ -1,12 +0,0 @@ | |||
1 | #ifndef ASMARM_ARCH_UART_H | ||
2 | #define ASMARM_ARCH_UART_H | ||
3 | |||
4 | #define IMXUART_HAVE_RTSCTS (1<<0) | ||
5 | |||
6 | struct imxuart_platform_data { | ||
7 | int (*init)(struct platform_device *pdev); | ||
8 | void (*exit)(struct platform_device *pdev); | ||
9 | unsigned int flags; | ||
10 | }; | ||
11 | |||
12 | #endif | ||
diff --git a/arch/arm/mach-imx/include/mach/io.h b/arch/arm/mach-imx/include/mach/io.h deleted file mode 100644 index 9e197ae4590f..000000000000 --- a/arch/arm/mach-imx/include/mach/io.h +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-imxads/include/mach/io.h | ||
3 | * | ||
4 | * Copyright (C) 1999 ARM Limited | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | #ifndef __ASM_ARM_ARCH_IO_H | ||
21 | #define __ASM_ARM_ARCH_IO_H | ||
22 | |||
23 | #define IO_SPACE_LIMIT 0xffffffff | ||
24 | |||
25 | #define __io(a) __typesafe_io(a) | ||
26 | #define __mem_pci(a) (a) | ||
27 | |||
28 | #endif | ||
diff --git a/arch/arm/mach-imx/include/mach/irqs.h b/arch/arm/mach-imx/include/mach/irqs.h deleted file mode 100644 index 67812c5ac1f9..000000000000 --- a/arch/arm/mach-imx/include/mach/irqs.h +++ /dev/null | |||
@@ -1,121 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-imxads/include/mach/irqs.h | ||
3 | * | ||
4 | * Copyright (C) 1999 ARM Limited | ||
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
20 | */ | ||
21 | |||
22 | #ifndef __ARM_IRQS_H__ | ||
23 | #define __ARM_IRQS_H__ | ||
24 | |||
25 | /* Use the imx definitions */ | ||
26 | #include <mach/hardware.h> | ||
27 | |||
28 | /* | ||
29 | * IMX Interrupt numbers | ||
30 | * | ||
31 | */ | ||
32 | #define INT_SOFTINT 0 | ||
33 | #define CSI_INT 6 | ||
34 | #define DSPA_MAC_INT 7 | ||
35 | #define DSPA_INT 8 | ||
36 | #define COMP_INT 9 | ||
37 | #define MSHC_XINT 10 | ||
38 | #define GPIO_INT_PORTA 11 | ||
39 | #define GPIO_INT_PORTB 12 | ||
40 | #define GPIO_INT_PORTC 13 | ||
41 | #define LCDC_INT 14 | ||
42 | #define SIM_INT 15 | ||
43 | #define SIM_DATA_INT 16 | ||
44 | #define RTC_INT 17 | ||
45 | #define RTC_SAMINT 18 | ||
46 | #define UART2_MINT_PFERR 19 | ||
47 | #define UART2_MINT_RTS 20 | ||
48 | #define UART2_MINT_DTR 21 | ||
49 | #define UART2_MINT_UARTC 22 | ||
50 | #define UART2_MINT_TX 23 | ||
51 | #define UART2_MINT_RX 24 | ||
52 | #define UART1_MINT_PFERR 25 | ||
53 | #define UART1_MINT_RTS 26 | ||
54 | #define UART1_MINT_DTR 27 | ||
55 | #define UART1_MINT_UARTC 28 | ||
56 | #define UART1_MINT_TX 29 | ||
57 | #define UART1_MINT_RX 30 | ||
58 | #define VOICE_DAC_INT 31 | ||
59 | #define VOICE_ADC_INT 32 | ||
60 | #define PEN_DATA_INT 33 | ||
61 | #define PWM_INT 34 | ||
62 | #define SDHC_INT 35 | ||
63 | #define I2C_INT 39 | ||
64 | #define CSPI_INT 41 | ||
65 | #define SSI_TX_INT 42 | ||
66 | #define SSI_TX_ERR_INT 43 | ||
67 | #define SSI_RX_INT 44 | ||
68 | #define SSI_RX_ERR_INT 45 | ||
69 | #define TOUCH_INT 46 | ||
70 | #define USBD_INT0 47 | ||
71 | #define USBD_INT1 48 | ||
72 | #define USBD_INT2 49 | ||
73 | #define USBD_INT3 50 | ||
74 | #define USBD_INT4 51 | ||
75 | #define USBD_INT5 52 | ||
76 | #define USBD_INT6 53 | ||
77 | #define BTSYS_INT 55 | ||
78 | #define BTTIM_INT 56 | ||
79 | #define BTWUI_INT 57 | ||
80 | #define TIM2_INT 58 | ||
81 | #define TIM1_INT 59 | ||
82 | #define DMA_ERR 60 | ||
83 | #define DMA_INT 61 | ||
84 | #define GPIO_INT_PORTD 62 | ||
85 | |||
86 | #define IMX_IRQS (64) | ||
87 | |||
88 | /* note: the IMX has four gpio ports (A-D), but only | ||
89 | * the following pins are connected to the outside | ||
90 | * world: | ||
91 | * | ||
92 | * PORT A: bits 0-31 | ||
93 | * PORT B: bits 8-31 | ||
94 | * PORT C: bits 3-17 | ||
95 | * PORT D: bits 6-31 | ||
96 | * | ||
97 | * We map these interrupts straight on. As a result we have | ||
98 | * several holes in the interrupt mapping. We do this for two | ||
99 | * reasons: | ||
100 | * - mapping the interrupts without holes would get | ||
101 | * far more complicated | ||
102 | * - Motorola could well decide to bring some processor | ||
103 | * with more pins connected | ||
104 | */ | ||
105 | |||
106 | #define IRQ_GPIOA(x) (IMX_IRQS + x) | ||
107 | #define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) | ||
108 | #define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) | ||
109 | #define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) | ||
110 | |||
111 | /* decode irq number to use with IMR(x), ISR(x) and friends */ | ||
112 | #define IRQ_TO_REG(irq) ((irq - IMX_IRQS) >> 5) | ||
113 | |||
114 | /* all normal IRQs can be FIQs */ | ||
115 | #define FIQ_START 0 | ||
116 | /* switch betwean IRQ and FIQ */ | ||
117 | extern int imx_set_irq_fiq(unsigned int irq, unsigned int type); | ||
118 | |||
119 | #define NR_IRQS (IRQ_GPIOD(32) + 1) | ||
120 | #define IRQ_GPIO(x) | ||
121 | #endif | ||
diff --git a/arch/arm/mach-imx/include/mach/memory.h b/arch/arm/mach-imx/include/mach/memory.h deleted file mode 100644 index a93df7cba694..000000000000 --- a/arch/arm/mach-imx/include/mach/memory.h +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-imx/include/mach/memory.h | ||
3 | * | ||
4 | * Copyright (C) 1999 ARM Limited | ||
5 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
20 | */ | ||
21 | #ifndef __ASM_ARCH_MMU_H | ||
22 | #define __ASM_ARCH_MMU_H | ||
23 | |||
24 | #define PHYS_OFFSET UL(0x08000000) | ||
25 | |||
26 | #endif | ||
diff --git a/arch/arm/mach-imx/include/mach/mmc.h b/arch/arm/mach-imx/include/mach/mmc.h deleted file mode 100644 index 4712f354dcca..000000000000 --- a/arch/arm/mach-imx/include/mach/mmc.h +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | #ifndef ASMARM_ARCH_MMC_H | ||
2 | #define ASMARM_ARCH_MMC_H | ||
3 | |||
4 | #include <linux/mmc/host.h> | ||
5 | |||
6 | struct device; | ||
7 | |||
8 | struct imxmmc_platform_data { | ||
9 | int (*card_present)(struct device *); | ||
10 | int (*get_ro)(struct device *); | ||
11 | }; | ||
12 | |||
13 | extern void imx_set_mmc_info(struct imxmmc_platform_data *info); | ||
14 | |||
15 | #endif | ||
diff --git a/arch/arm/mach-imx/include/mach/mx1ads.h b/arch/arm/mach-imx/include/mach/mx1ads.h deleted file mode 100644 index def05d510eb3..000000000000 --- a/arch/arm/mach-imx/include/mach/mx1ads.h +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-imx/include/mach/mx1ads.h | ||
3 | * | ||
4 | * Copyright (C) 2004 Robert Schwebel, Pengutronix | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | * | ||
20 | */ | ||
21 | |||
22 | #ifndef __ASM_ARCH_MX1ADS_H | ||
23 | #define __ASM_ARCH_MX1ADS_H | ||
24 | |||
25 | /* ------------------------------------------------------------------------ */ | ||
26 | /* Memory Map for the M9328MX1ADS (MX1ADS) Board */ | ||
27 | /* ------------------------------------------------------------------------ */ | ||
28 | |||
29 | #define MX1ADS_FLASH_PHYS 0x10000000 | ||
30 | #define MX1ADS_FLASH_SIZE (16*1024*1024) | ||
31 | |||
32 | #define IMX_FB_PHYS (0x0C000000 - 0x40000) | ||
33 | |||
34 | #define CLK32 32000 | ||
35 | |||
36 | #endif /* __ASM_ARCH_MX1ADS_H */ | ||
diff --git a/arch/arm/mach-imx/include/mach/spi_imx.h b/arch/arm/mach-imx/include/mach/spi_imx.h deleted file mode 100644 index 4186430feecf..000000000000 --- a/arch/arm/mach-imx/include/mach/spi_imx.h +++ /dev/null | |||
@@ -1,72 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-imx/include/mach/spi_imx.h | ||
3 | * | ||
4 | * Copyright (C) 2006 SWAPP | ||
5 | * Andrea Paterniani <a.paterniani@swapp-eng.it> | ||
6 | * | ||
7 | * Initial version inspired by: | ||
8 | * linux-2.6.17-rc3-mm1/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | * | ||
15 | * This program is distributed in the hope that it will be useful, | ||
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
18 | * GNU General Public License for more details. | ||
19 | * | ||
20 | * You should have received a copy of the GNU General Public License | ||
21 | * along with this program; if not, write to the Free Software | ||
22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
23 | */ | ||
24 | |||
25 | #ifndef SPI_IMX_H_ | ||
26 | #define SPI_IMX_H_ | ||
27 | |||
28 | |||
29 | /*-------------------------------------------------------------------------*/ | ||
30 | /** | ||
31 | * struct spi_imx_master - device.platform_data for SPI controller devices. | ||
32 | * @num_chipselect: chipselects are used to distinguish individual | ||
33 | * SPI slaves, and are numbered from zero to num_chipselects - 1. | ||
34 | * each slave has a chipselect signal, but it's common that not | ||
35 | * every chipselect is connected to a slave. | ||
36 | * @enable_dma: if true enables DMA driven transfers. | ||
37 | */ | ||
38 | struct spi_imx_master { | ||
39 | u8 num_chipselect; | ||
40 | u8 enable_dma:1; | ||
41 | }; | ||
42 | /*-------------------------------------------------------------------------*/ | ||
43 | |||
44 | |||
45 | /*-------------------------------------------------------------------------*/ | ||
46 | /** | ||
47 | * struct spi_imx_chip - spi_board_info.controller_data for SPI | ||
48 | * slave devices, copied to spi_device.controller_data. | ||
49 | * @enable_loopback : used for test purpouse to internally connect RX and TX | ||
50 | * sections. | ||
51 | * @enable_dma : enables dma transfer (provided that controller driver has | ||
52 | * dma enabled too). | ||
53 | * @ins_ss_pulse : enable /SS pulse insertion between SPI burst. | ||
54 | * @bclk_wait : number of bclk waits between each bits_per_word SPI burst. | ||
55 | * @cs_control : function pointer to board-specific function to assert/deassert | ||
56 | * I/O port to control HW generation of devices chip-select. | ||
57 | */ | ||
58 | struct spi_imx_chip { | ||
59 | u8 enable_loopback:1; | ||
60 | u8 enable_dma:1; | ||
61 | u8 ins_ss_pulse:1; | ||
62 | u16 bclk_wait:15; | ||
63 | void (*cs_control)(u32 control); | ||
64 | }; | ||
65 | |||
66 | /* Chip-select state */ | ||
67 | #define SPI_CS_ASSERT (1 << 0) | ||
68 | #define SPI_CS_DEASSERT (1 << 1) | ||
69 | /*-------------------------------------------------------------------------*/ | ||
70 | |||
71 | |||
72 | #endif /* SPI_IMX_H_*/ | ||
diff --git a/arch/arm/mach-imx/include/mach/system.h b/arch/arm/mach-imx/include/mach/system.h deleted file mode 100644 index 46d4ca91af79..000000000000 --- a/arch/arm/mach-imx/include/mach/system.h +++ /dev/null | |||
@@ -1,40 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-imxads/include/mach/system.h | ||
3 | * | ||
4 | * Copyright (C) 1999 ARM Limited | ||
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
20 | */ | ||
21 | #ifndef __ASM_ARCH_SYSTEM_H | ||
22 | #define __ASM_ARCH_SYSTEM_H | ||
23 | |||
24 | static void | ||
25 | arch_idle(void) | ||
26 | { | ||
27 | /* | ||
28 | * This should do all the clock switching | ||
29 | * and wait for interrupt tricks | ||
30 | */ | ||
31 | cpu_do_idle(); | ||
32 | } | ||
33 | |||
34 | static inline void | ||
35 | arch_reset(char mode, const char *cmd) | ||
36 | { | ||
37 | cpu_reset(0); | ||
38 | } | ||
39 | |||
40 | #endif | ||
diff --git a/arch/arm/mach-imx/include/mach/timex.h b/arch/arm/mach-imx/include/mach/timex.h deleted file mode 100644 index e22ba789546c..000000000000 --- a/arch/arm/mach-imx/include/mach/timex.h +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/imx/timex.h | ||
3 | * | ||
4 | * Copyright (C) 1999 ARM Limited | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | |||
21 | #ifndef __ASM_ARCH_TIMEX_H | ||
22 | #define __ASM_ARCH_TIMEX_H | ||
23 | |||
24 | #define CLOCK_TICK_RATE (16000000) | ||
25 | |||
26 | #endif | ||
diff --git a/arch/arm/mach-imx/include/mach/uncompress.h b/arch/arm/mach-imx/include/mach/uncompress.h deleted file mode 100644 index 70523e67a8f6..000000000000 --- a/arch/arm/mach-imx/include/mach/uncompress.h +++ /dev/null | |||
@@ -1,71 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-imxads/include/mach/uncompress.h | ||
3 | * | ||
4 | * | ||
5 | * | ||
6 | * Copyright (C) 1999 ARM Limited | ||
7 | * Copyright (C) Shane Nay (shane@minirl.com) | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this program; if not, write to the Free Software | ||
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
22 | */ | ||
23 | |||
24 | #define UART(x) (*(volatile unsigned long *)(serial_port + (x))) | ||
25 | |||
26 | #define UART1_BASE 0x206000 | ||
27 | #define UART2_BASE 0x207000 | ||
28 | #define USR2 0x98 | ||
29 | #define USR2_TXFE (1<<14) | ||
30 | #define TXR 0x40 | ||
31 | #define UCR1 0x80 | ||
32 | #define UCR1_UARTEN 1 | ||
33 | |||
34 | /* | ||
35 | * The following code assumes the serial port has already been | ||
36 | * initialized by the bootloader. We search for the first enabled | ||
37 | * port in the most probable order. If you didn't setup a port in | ||
38 | * your bootloader then nothing will appear (which might be desired). | ||
39 | * | ||
40 | * This does not append a newline | ||
41 | */ | ||
42 | static void putc(int c) | ||
43 | { | ||
44 | unsigned long serial_port; | ||
45 | |||
46 | do { | ||
47 | serial_port = UART1_BASE; | ||
48 | if ( UART(UCR1) & UCR1_UARTEN ) | ||
49 | break; | ||
50 | serial_port = UART2_BASE; | ||
51 | if ( UART(UCR1) & UCR1_UARTEN ) | ||
52 | break; | ||
53 | return; | ||
54 | } while(0); | ||
55 | |||
56 | while (!(UART(USR2) & USR2_TXFE)) | ||
57 | barrier(); | ||
58 | |||
59 | UART(TXR) = c; | ||
60 | } | ||
61 | |||
62 | static inline void flush(void) | ||
63 | { | ||
64 | } | ||
65 | |||
66 | /* | ||
67 | * nothing to do | ||
68 | */ | ||
69 | #define arch_decomp_setup() | ||
70 | |||
71 | #define arch_decomp_wdog() | ||
diff --git a/arch/arm/mach-imx/include/mach/vmalloc.h b/arch/arm/mach-imx/include/mach/vmalloc.h deleted file mode 100644 index 7d7cb0bde3e8..000000000000 --- a/arch/arm/mach-imx/include/mach/vmalloc.h +++ /dev/null | |||
@@ -1,20 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-imx/include/mach/vmalloc.h | ||
3 | * | ||
4 | * Copyright (C) 2000 Russell King. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | #define VMALLOC_END (PAGE_OFFSET + 0x10000000) | ||
diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c deleted file mode 100644 index 531b95deadc0..000000000000 --- a/arch/arm/mach-imx/irq.c +++ /dev/null | |||
@@ -1,311 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-imx/irq.c | ||
3 | * | ||
4 | * Copyright (C) 1999 ARM Limited | ||
5 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
20 | * | ||
21 | * 03/03/2004 Sascha Hauer <sascha@saschahauer.de> | ||
22 | * Copied from the motorola bsp package and added gpio demux | ||
23 | * interrupt handler | ||
24 | */ | ||
25 | |||
26 | #include <linux/init.h> | ||
27 | #include <linux/list.h> | ||
28 | #include <linux/timer.h> | ||
29 | #include <linux/io.h> | ||
30 | |||
31 | #include <mach/hardware.h> | ||
32 | #include <asm/irq.h> | ||
33 | |||
34 | #include <asm/mach/irq.h> | ||
35 | |||
36 | /* | ||
37 | * | ||
38 | * We simply use the ENABLE DISABLE registers inside of the IMX | ||
39 | * to turn on/off specific interrupts. | ||
40 | * | ||
41 | */ | ||
42 | |||
43 | #define INTCNTL_OFF 0x00 | ||
44 | #define NIMASK_OFF 0x04 | ||
45 | #define INTENNUM_OFF 0x08 | ||
46 | #define INTDISNUM_OFF 0x0C | ||
47 | #define INTENABLEH_OFF 0x10 | ||
48 | #define INTENABLEL_OFF 0x14 | ||
49 | #define INTTYPEH_OFF 0x18 | ||
50 | #define INTTYPEL_OFF 0x1C | ||
51 | #define NIPRIORITY_OFF(x) (0x20+4*(7-(x))) | ||
52 | #define NIVECSR_OFF 0x40 | ||
53 | #define FIVECSR_OFF 0x44 | ||
54 | #define INTSRCH_OFF 0x48 | ||
55 | #define INTSRCL_OFF 0x4C | ||
56 | #define INTFRCH_OFF 0x50 | ||
57 | #define INTFRCL_OFF 0x54 | ||
58 | #define NIPNDH_OFF 0x58 | ||
59 | #define NIPNDL_OFF 0x5C | ||
60 | #define FIPNDH_OFF 0x60 | ||
61 | #define FIPNDL_OFF 0x64 | ||
62 | |||
63 | #define VA_AITC_BASE IO_ADDRESS(IMX_AITC_BASE) | ||
64 | #define IMX_AITC_INTCNTL (VA_AITC_BASE + INTCNTL_OFF) | ||
65 | #define IMX_AITC_NIMASK (VA_AITC_BASE + NIMASK_OFF) | ||
66 | #define IMX_AITC_INTENNUM (VA_AITC_BASE + INTENNUM_OFF) | ||
67 | #define IMX_AITC_INTDISNUM (VA_AITC_BASE + INTDISNUM_OFF) | ||
68 | #define IMX_AITC_INTENABLEH (VA_AITC_BASE + INTENABLEH_OFF) | ||
69 | #define IMX_AITC_INTENABLEL (VA_AITC_BASE + INTENABLEL_OFF) | ||
70 | #define IMX_AITC_INTTYPEH (VA_AITC_BASE + INTTYPEH_OFF) | ||
71 | #define IMX_AITC_INTTYPEL (VA_AITC_BASE + INTTYPEL_OFF) | ||
72 | #define IMX_AITC_NIPRIORITY(x) (VA_AITC_BASE + NIPRIORITY_OFF(x)) | ||
73 | #define IMX_AITC_NIVECSR (VA_AITC_BASE + NIVECSR_OFF) | ||
74 | #define IMX_AITC_FIVECSR (VA_AITC_BASE + FIVECSR_OFF) | ||
75 | #define IMX_AITC_INTSRCH (VA_AITC_BASE + INTSRCH_OFF) | ||
76 | #define IMX_AITC_INTSRCL (VA_AITC_BASE + INTSRCL_OFF) | ||
77 | #define IMX_AITC_INTFRCH (VA_AITC_BASE + INTFRCH_OFF) | ||
78 | #define IMX_AITC_INTFRCL (VA_AITC_BASE + INTFRCL_OFF) | ||
79 | #define IMX_AITC_NIPNDH (VA_AITC_BASE + NIPNDH_OFF) | ||
80 | #define IMX_AITC_NIPNDL (VA_AITC_BASE + NIPNDL_OFF) | ||
81 | #define IMX_AITC_FIPNDH (VA_AITC_BASE + FIPNDH_OFF) | ||
82 | #define IMX_AITC_FIPNDL (VA_AITC_BASE + FIPNDL_OFF) | ||
83 | |||
84 | #if 0 | ||
85 | #define DEBUG_IRQ(fmt...) printk(fmt) | ||
86 | #else | ||
87 | #define DEBUG_IRQ(fmt...) do { } while (0) | ||
88 | #endif | ||
89 | |||
90 | static void | ||
91 | imx_mask_irq(unsigned int irq) | ||
92 | { | ||
93 | __raw_writel(irq, IMX_AITC_INTDISNUM); | ||
94 | } | ||
95 | |||
96 | static void | ||
97 | imx_unmask_irq(unsigned int irq) | ||
98 | { | ||
99 | __raw_writel(irq, IMX_AITC_INTENNUM); | ||
100 | } | ||
101 | |||
102 | #ifdef CONFIG_FIQ | ||
103 | int imx_set_irq_fiq(unsigned int irq, unsigned int type) | ||
104 | { | ||
105 | unsigned int irqt; | ||
106 | |||
107 | if (irq >= IMX_IRQS) | ||
108 | return -EINVAL; | ||
109 | |||
110 | if (irq < IMX_IRQS / 2) { | ||
111 | irqt = __raw_readl(IMX_AITC_INTTYPEL) & ~(1 << irq); | ||
112 | __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEL); | ||
113 | } else { | ||
114 | irq -= IMX_IRQS / 2; | ||
115 | irqt = __raw_readl(IMX_AITC_INTTYPEH) & ~(1 << irq); | ||
116 | __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEH); | ||
117 | } | ||
118 | |||
119 | return 0; | ||
120 | } | ||
121 | EXPORT_SYMBOL(imx_set_irq_fiq); | ||
122 | #endif /* CONFIG_FIQ */ | ||
123 | |||
124 | static int | ||
125 | imx_gpio_irq_type(unsigned int _irq, unsigned int type) | ||
126 | { | ||
127 | unsigned int irq_type = 0, irq, reg, bit; | ||
128 | |||
129 | irq = _irq - IRQ_GPIOA(0); | ||
130 | reg = irq >> 5; | ||
131 | bit = 1 << (irq % 32); | ||
132 | |||
133 | if (type == IRQ_TYPE_PROBE) { | ||
134 | /* Don't mess with enabled GPIOs using preconfigured edges or | ||
135 | GPIOs set to alternate function during probe */ | ||
136 | /* TODO: support probe */ | ||
137 | // if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx]) & | ||
138 | // GPIO_bit(gpio)) | ||
139 | // return 0; | ||
140 | // if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2))) | ||
141 | // return 0; | ||
142 | // type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | ||
143 | } | ||
144 | |||
145 | GIUS(reg) |= bit; | ||
146 | DDIR(reg) &= ~(bit); | ||
147 | |||
148 | DEBUG_IRQ("setting type of irq %d to ", _irq); | ||
149 | |||
150 | if (type & IRQ_TYPE_EDGE_RISING) { | ||
151 | DEBUG_IRQ("rising edges\n"); | ||
152 | irq_type = 0x0; | ||
153 | } | ||
154 | if (type & IRQ_TYPE_EDGE_FALLING) { | ||
155 | DEBUG_IRQ("falling edges\n"); | ||
156 | irq_type = 0x1; | ||
157 | } | ||
158 | if (type & IRQ_TYPE_LEVEL_LOW) { | ||
159 | DEBUG_IRQ("low level\n"); | ||
160 | irq_type = 0x3; | ||
161 | } | ||
162 | if (type & IRQ_TYPE_LEVEL_HIGH) { | ||
163 | DEBUG_IRQ("high level\n"); | ||
164 | irq_type = 0x2; | ||
165 | } | ||
166 | |||
167 | if (irq % 32 < 16) { | ||
168 | ICR1(reg) = (ICR1(reg) & ~(0x3 << ((irq % 16) * 2))) | | ||
169 | (irq_type << ((irq % 16) * 2)); | ||
170 | } else { | ||
171 | ICR2(reg) = (ICR2(reg) & ~(0x3 << ((irq % 16) * 2))) | | ||
172 | (irq_type << ((irq % 16) * 2)); | ||
173 | } | ||
174 | |||
175 | return 0; | ||
176 | |||
177 | } | ||
178 | |||
179 | static void | ||
180 | imx_gpio_ack_irq(unsigned int irq) | ||
181 | { | ||
182 | DEBUG_IRQ("%s: irq %d\n", __func__, irq); | ||
183 | ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32); | ||
184 | } | ||
185 | |||
186 | static void | ||
187 | imx_gpio_mask_irq(unsigned int irq) | ||
188 | { | ||
189 | DEBUG_IRQ("%s: irq %d\n", __func__, irq); | ||
190 | IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32)); | ||
191 | } | ||
192 | |||
193 | static void | ||
194 | imx_gpio_unmask_irq(unsigned int irq) | ||
195 | { | ||
196 | DEBUG_IRQ("%s: irq %d\n", __func__, irq); | ||
197 | IMR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32); | ||
198 | } | ||
199 | |||
200 | static void | ||
201 | imx_gpio_handler(unsigned int mask, unsigned int irq, | ||
202 | struct irq_desc *desc) | ||
203 | { | ||
204 | while (mask) { | ||
205 | if (mask & 1) { | ||
206 | DEBUG_IRQ("handling irq %d\n", irq); | ||
207 | generic_handle_irq(irq); | ||
208 | } | ||
209 | irq++; | ||
210 | mask >>= 1; | ||
211 | } | ||
212 | } | ||
213 | |||
214 | static void | ||
215 | imx_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc) | ||
216 | { | ||
217 | unsigned int mask, irq; | ||
218 | |||
219 | mask = ISR(0); | ||
220 | irq = IRQ_GPIOA(0); | ||
221 | imx_gpio_handler(mask, irq, desc); | ||
222 | } | ||
223 | |||
224 | static void | ||
225 | imx_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc) | ||
226 | { | ||
227 | unsigned int mask, irq; | ||
228 | |||
229 | mask = ISR(1); | ||
230 | irq = IRQ_GPIOB(0); | ||
231 | imx_gpio_handler(mask, irq, desc); | ||
232 | } | ||
233 | |||
234 | static void | ||
235 | imx_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc) | ||
236 | { | ||
237 | unsigned int mask, irq; | ||
238 | |||
239 | mask = ISR(2); | ||
240 | irq = IRQ_GPIOC(0); | ||
241 | imx_gpio_handler(mask, irq, desc); | ||
242 | } | ||
243 | |||
244 | static void | ||
245 | imx_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc) | ||
246 | { | ||
247 | unsigned int mask, irq; | ||
248 | |||
249 | mask = ISR(3); | ||
250 | irq = IRQ_GPIOD(0); | ||
251 | imx_gpio_handler(mask, irq, desc); | ||
252 | } | ||
253 | |||
254 | static struct irq_chip imx_internal_chip = { | ||
255 | .name = "MPU", | ||
256 | .ack = imx_mask_irq, | ||
257 | .mask = imx_mask_irq, | ||
258 | .unmask = imx_unmask_irq, | ||
259 | }; | ||
260 | |||
261 | static struct irq_chip imx_gpio_chip = { | ||
262 | .name = "GPIO", | ||
263 | .ack = imx_gpio_ack_irq, | ||
264 | .mask = imx_gpio_mask_irq, | ||
265 | .unmask = imx_gpio_unmask_irq, | ||
266 | .set_type = imx_gpio_irq_type, | ||
267 | }; | ||
268 | |||
269 | void __init | ||
270 | imx_init_irq(void) | ||
271 | { | ||
272 | unsigned int irq; | ||
273 | |||
274 | DEBUG_IRQ("Initializing imx interrupts\n"); | ||
275 | |||
276 | /* Disable all interrupts initially. */ | ||
277 | /* Do not rely on the bootloader. */ | ||
278 | __raw_writel(0, IMX_AITC_INTENABLEH); | ||
279 | __raw_writel(0, IMX_AITC_INTENABLEL); | ||
280 | |||
281 | /* Mask all GPIO interrupts as well */ | ||
282 | IMR(0) = 0; | ||
283 | IMR(1) = 0; | ||
284 | IMR(2) = 0; | ||
285 | IMR(3) = 0; | ||
286 | |||
287 | for (irq = 0; irq < IMX_IRQS; irq++) { | ||
288 | set_irq_chip(irq, &imx_internal_chip); | ||
289 | set_irq_handler(irq, handle_level_irq); | ||
290 | set_irq_flags(irq, IRQF_VALID); | ||
291 | } | ||
292 | |||
293 | for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) { | ||
294 | set_irq_chip(irq, &imx_gpio_chip); | ||
295 | set_irq_handler(irq, handle_edge_irq); | ||
296 | set_irq_flags(irq, IRQF_VALID); | ||
297 | } | ||
298 | |||
299 | set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler); | ||
300 | set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler); | ||
301 | set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler); | ||
302 | set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler); | ||
303 | |||
304 | /* Release masking of interrupts according to priority */ | ||
305 | __raw_writel(-1, IMX_AITC_NIMASK); | ||
306 | |||
307 | #ifdef CONFIG_FIQ | ||
308 | /* Initialize FIQ */ | ||
309 | init_FIQ(); | ||
310 | #endif | ||
311 | } | ||
diff --git a/arch/arm/mach-imx/leds-mx1ads.c b/arch/arm/mach-imx/leds-mx1ads.c deleted file mode 100644 index 1d48f2762cbc..000000000000 --- a/arch/arm/mach-imx/leds-mx1ads.c +++ /dev/null | |||
@@ -1,53 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-imx/leds-mx1ads.c | ||
3 | * | ||
4 | * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de> | ||
5 | * | ||
6 | * Original (leds-footbridge.c) by Russell King | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/init.h> | ||
16 | #include <linux/io.h> | ||
17 | #include <mach/hardware.h> | ||
18 | #include <asm/system.h> | ||
19 | #include <asm/leds.h> | ||
20 | #include "leds.h" | ||
21 | |||
22 | /* | ||
23 | * The MX1ADS Board has only one usable LED, | ||
24 | * so select only the timer led or the | ||
25 | * cpu usage led | ||
26 | */ | ||
27 | void | ||
28 | mx1ads_leds_event(led_event_t ledevt) | ||
29 | { | ||
30 | unsigned long flags; | ||
31 | |||
32 | local_irq_save(flags); | ||
33 | |||
34 | switch (ledevt) { | ||
35 | #ifdef CONFIG_LEDS_CPU | ||
36 | case led_idle_start: | ||
37 | DR(0) &= ~(1<<2); | ||
38 | break; | ||
39 | |||
40 | case led_idle_end: | ||
41 | DR(0) |= 1<<2; | ||
42 | break; | ||
43 | #endif | ||
44 | |||
45 | #ifdef CONFIG_LEDS_TIMER | ||
46 | case led_timer: | ||
47 | DR(0) ^= 1<<2; | ||
48 | #endif | ||
49 | default: | ||
50 | break; | ||
51 | } | ||
52 | local_irq_restore(flags); | ||
53 | } | ||
diff --git a/arch/arm/mach-imx/leds.c b/arch/arm/mach-imx/leds.c deleted file mode 100644 index cf30803e019b..000000000000 --- a/arch/arm/mach-imx/leds.c +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-imx/leds.c | ||
3 | * | ||
4 | * Copyright (C) 2004 Sascha Hauer <sascha@saschahauer.de> | ||
5 | * | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/init.h> | ||
15 | |||
16 | #include <asm/leds.h> | ||
17 | #include <asm/mach-types.h> | ||
18 | |||
19 | #include "leds.h" | ||
20 | |||
21 | static int __init | ||
22 | leds_init(void) | ||
23 | { | ||
24 | if (machine_is_mx1ads()) { | ||
25 | leds_event = mx1ads_leds_event; | ||
26 | } | ||
27 | |||
28 | return 0; | ||
29 | } | ||
30 | |||
31 | __initcall(leds_init); | ||
diff --git a/arch/arm/mach-imx/leds.h b/arch/arm/mach-imx/leds.h deleted file mode 100644 index 49dc1c1da338..000000000000 --- a/arch/arm/mach-imx/leds.h +++ /dev/null | |||
@@ -1,9 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-imx/leds.h | ||
3 | * | ||
4 | * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de> | ||
5 | * | ||
6 | * blinky lights for IMX-based systems | ||
7 | * | ||
8 | */ | ||
9 | extern void mx1ads_leds_event(led_event_t evt); | ||
diff --git a/arch/arm/mach-imx/mx1ads.c b/arch/arm/mach-imx/mx1ads.c deleted file mode 100644 index 87fa1ff43b0b..000000000000 --- a/arch/arm/mach-imx/mx1ads.c +++ /dev/null | |||
@@ -1,180 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-imx/mx1ads.c | ||
3 | * | ||
4 | * Initially based on: | ||
5 | * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c | ||
6 | * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de> | ||
7 | * | ||
8 | * 2004 (c) MontaVista Software, Inc. | ||
9 | * | ||
10 | * This file is licensed under the terms of the GNU General Public | ||
11 | * License version 2. This program is licensed "as is" without any | ||
12 | * warranty of any kind, whether express or implied. | ||
13 | */ | ||
14 | |||
15 | #include <linux/device.h> | ||
16 | #include <linux/init.h> | ||
17 | #include <linux/platform_device.h> | ||
18 | #include <asm/system.h> | ||
19 | #include <mach/hardware.h> | ||
20 | #include <asm/irq.h> | ||
21 | #include <asm/pgtable.h> | ||
22 | #include <asm/page.h> | ||
23 | |||
24 | #include <asm/mach/map.h> | ||
25 | #include <asm/mach-types.h> | ||
26 | |||
27 | #include <asm/mach/arch.h> | ||
28 | #include <mach/mmc.h> | ||
29 | #include <mach/imx-uart.h> | ||
30 | #include <linux/interrupt.h> | ||
31 | #include "generic.h" | ||
32 | |||
33 | static struct resource cs89x0_resources[] = { | ||
34 | [0] = { | ||
35 | .start = IMX_CS4_PHYS + 0x300, | ||
36 | .end = IMX_CS4_PHYS + 0x300 + 16, | ||
37 | .flags = IORESOURCE_MEM, | ||
38 | }, | ||
39 | [1] = { | ||
40 | .start = IRQ_GPIOC(17), | ||
41 | .end = IRQ_GPIOC(17), | ||
42 | .flags = IORESOURCE_IRQ, | ||
43 | }, | ||
44 | }; | ||
45 | |||
46 | static struct platform_device cs89x0_device = { | ||
47 | .name = "cirrus-cs89x0", | ||
48 | .num_resources = ARRAY_SIZE(cs89x0_resources), | ||
49 | .resource = cs89x0_resources, | ||
50 | }; | ||
51 | |||
52 | static struct imxuart_platform_data uart_pdata = { | ||
53 | .flags = IMXUART_HAVE_RTSCTS, | ||
54 | }; | ||
55 | |||
56 | static struct resource imx_uart1_resources[] = { | ||
57 | [0] = { | ||
58 | .start = 0x00206000, | ||
59 | .end = 0x002060FF, | ||
60 | .flags = IORESOURCE_MEM, | ||
61 | }, | ||
62 | [1] = { | ||
63 | .start = (UART1_MINT_RX), | ||
64 | .end = (UART1_MINT_RX), | ||
65 | .flags = IORESOURCE_IRQ, | ||
66 | }, | ||
67 | [2] = { | ||
68 | .start = (UART1_MINT_TX), | ||
69 | .end = (UART1_MINT_TX), | ||
70 | .flags = IORESOURCE_IRQ, | ||
71 | }, | ||
72 | [3] = { | ||
73 | .start = UART1_MINT_RTS, | ||
74 | .end = UART1_MINT_RTS, | ||
75 | .flags = IORESOURCE_IRQ, | ||
76 | }, | ||
77 | }; | ||
78 | |||
79 | static struct platform_device imx_uart1_device = { | ||
80 | .name = "imx-uart", | ||
81 | .id = 0, | ||
82 | .num_resources = ARRAY_SIZE(imx_uart1_resources), | ||
83 | .resource = imx_uart1_resources, | ||
84 | .dev = { | ||
85 | .platform_data = &uart_pdata, | ||
86 | } | ||
87 | }; | ||
88 | |||
89 | static struct resource imx_uart2_resources[] = { | ||
90 | [0] = { | ||
91 | .start = 0x00207000, | ||
92 | .end = 0x002070FF, | ||
93 | .flags = IORESOURCE_MEM, | ||
94 | }, | ||
95 | [1] = { | ||
96 | .start = (UART2_MINT_RX), | ||
97 | .end = (UART2_MINT_RX), | ||
98 | .flags = IORESOURCE_IRQ, | ||
99 | }, | ||
100 | [2] = { | ||
101 | .start = (UART2_MINT_TX), | ||
102 | .end = (UART2_MINT_TX), | ||
103 | .flags = IORESOURCE_IRQ, | ||
104 | }, | ||
105 | [3] = { | ||
106 | .start = UART2_MINT_RTS, | ||
107 | .end = UART2_MINT_RTS, | ||
108 | .flags = IORESOURCE_IRQ, | ||
109 | }, | ||
110 | }; | ||
111 | |||
112 | static struct platform_device imx_uart2_device = { | ||
113 | .name = "imx-uart", | ||
114 | .id = 1, | ||
115 | .num_resources = ARRAY_SIZE(imx_uart2_resources), | ||
116 | .resource = imx_uart2_resources, | ||
117 | .dev = { | ||
118 | .platform_data = &uart_pdata, | ||
119 | } | ||
120 | }; | ||
121 | |||
122 | static struct platform_device *devices[] __initdata = { | ||
123 | &cs89x0_device, | ||
124 | &imx_uart1_device, | ||
125 | &imx_uart2_device, | ||
126 | }; | ||
127 | |||
128 | #if defined(CONFIG_MMC_IMX) || defined(CONFIG_MMC_IMX_MODULE) | ||
129 | static int mx1ads_mmc_card_present(struct device *dev) | ||
130 | { | ||
131 | /* MMC/SD Card Detect is PB 20 on MX1ADS V1.0.7 */ | ||
132 | return (SSR(1) & (1 << 20) ? 0 : 1); | ||
133 | } | ||
134 | |||
135 | static struct imxmmc_platform_data mx1ads_mmc_info = { | ||
136 | .card_present = mx1ads_mmc_card_present, | ||
137 | }; | ||
138 | #endif | ||
139 | |||
140 | static void __init | ||
141 | mx1ads_init(void) | ||
142 | { | ||
143 | #ifdef CONFIG_LEDS | ||
144 | imx_gpio_mode(GPIO_PORTA | GPIO_OUT | 2); | ||
145 | #endif | ||
146 | #if defined(CONFIG_MMC_IMX) || defined(CONFIG_MMC_IMX_MODULE) | ||
147 | /* SD/MMC card detect */ | ||
148 | imx_gpio_mode(GPIO_PORTB | GPIO_GIUS | GPIO_IN | 20); | ||
149 | imx_set_mmc_info(&mx1ads_mmc_info); | ||
150 | #endif | ||
151 | |||
152 | imx_gpio_mode(PC9_PF_UART1_CTS); | ||
153 | imx_gpio_mode(PC10_PF_UART1_RTS); | ||
154 | imx_gpio_mode(PC11_PF_UART1_TXD); | ||
155 | imx_gpio_mode(PC12_PF_UART1_RXD); | ||
156 | |||
157 | imx_gpio_mode(PB28_PF_UART2_CTS); | ||
158 | imx_gpio_mode(PB29_PF_UART2_RTS); | ||
159 | imx_gpio_mode(PB30_PF_UART2_TXD); | ||
160 | imx_gpio_mode(PB31_PF_UART2_RXD); | ||
161 | |||
162 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
163 | } | ||
164 | |||
165 | static void __init | ||
166 | mx1ads_map_io(void) | ||
167 | { | ||
168 | imx_map_io(); | ||
169 | } | ||
170 | |||
171 | MACHINE_START(MX1ADS, "Motorola MX1ADS") | ||
172 | /* Maintainer: Sascha Hauer, Pengutronix */ | ||
173 | .phys_io = 0x00200000, | ||
174 | .io_pg_offst = ((0xe0000000) >> 18) & 0xfffc, | ||
175 | .boot_params = 0x08000100, | ||
176 | .map_io = mx1ads_map_io, | ||
177 | .init_irq = imx_init_irq, | ||
178 | .timer = &imx_timer, | ||
179 | .init_machine = mx1ads_init, | ||
180 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c deleted file mode 100644 index 5aef18b599e5..000000000000 --- a/arch/arm/mach-imx/time.c +++ /dev/null | |||
@@ -1,220 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-imx/time.c | ||
3 | * | ||
4 | * Copyright (C) 2000-2001 Deep Blue Solutions | ||
5 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | ||
6 | * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | #include <linux/kernel.h> | ||
13 | #include <linux/sched.h> | ||
14 | #include <linux/init.h> | ||
15 | #include <linux/interrupt.h> | ||
16 | #include <linux/irq.h> | ||
17 | #include <linux/time.h> | ||
18 | #include <linux/clocksource.h> | ||
19 | #include <linux/clockchips.h> | ||
20 | #include <linux/clk.h> | ||
21 | #include <linux/io.h> | ||
22 | |||
23 | #include <mach/hardware.h> | ||
24 | #include <asm/leds.h> | ||
25 | #include <asm/irq.h> | ||
26 | #include <asm/mach/time.h> | ||
27 | |||
28 | /* Use timer 1 as system timer */ | ||
29 | #define TIMER_BASE IMX_TIM1_BASE | ||
30 | |||
31 | static struct clock_event_device clockevent_imx; | ||
32 | static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; | ||
33 | |||
34 | /* | ||
35 | * IRQ handler for the timer | ||
36 | */ | ||
37 | static irqreturn_t | ||
38 | imx_timer_interrupt(int irq, void *dev_id) | ||
39 | { | ||
40 | struct clock_event_device *evt = &clockevent_imx; | ||
41 | uint32_t tstat; | ||
42 | irqreturn_t ret = IRQ_NONE; | ||
43 | |||
44 | /* clear the interrupt */ | ||
45 | tstat = IMX_TSTAT(TIMER_BASE); | ||
46 | IMX_TSTAT(TIMER_BASE) = 0; | ||
47 | |||
48 | if (tstat & TSTAT_COMP) { | ||
49 | evt->event_handler(evt); | ||
50 | ret = IRQ_HANDLED; | ||
51 | } | ||
52 | |||
53 | return ret; | ||
54 | } | ||
55 | |||
56 | static struct irqaction imx_timer_irq = { | ||
57 | .name = "i.MX Timer Tick", | ||
58 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
59 | .handler = imx_timer_interrupt, | ||
60 | }; | ||
61 | |||
62 | /* | ||
63 | * Set up timer hardware into expected mode and state. | ||
64 | */ | ||
65 | static void __init imx_timer_hardware_init(void) | ||
66 | { | ||
67 | /* | ||
68 | * Initialise to a known state (all timers off, and timing reset) | ||
69 | */ | ||
70 | IMX_TCTL(TIMER_BASE) = 0; | ||
71 | IMX_TPRER(TIMER_BASE) = 0; | ||
72 | |||
73 | IMX_TCTL(TIMER_BASE) = TCTL_FRR | TCTL_CLK_PCLK1 | TCTL_TEN; | ||
74 | } | ||
75 | |||
76 | cycle_t imx_get_cycles(struct clocksource *cs) | ||
77 | { | ||
78 | return IMX_TCN(TIMER_BASE); | ||
79 | } | ||
80 | |||
81 | static struct clocksource clocksource_imx = { | ||
82 | .name = "imx_timer1", | ||
83 | .rating = 200, | ||
84 | .read = imx_get_cycles, | ||
85 | .mask = 0xFFFFFFFF, | ||
86 | .shift = 20, | ||
87 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
88 | }; | ||
89 | |||
90 | static int __init imx_clocksource_init(unsigned long rate) | ||
91 | { | ||
92 | clocksource_imx.mult = | ||
93 | clocksource_hz2mult(rate, clocksource_imx.shift); | ||
94 | clocksource_register(&clocksource_imx); | ||
95 | |||
96 | return 0; | ||
97 | } | ||
98 | |||
99 | static int imx_set_next_event(unsigned long evt, | ||
100 | struct clock_event_device *unused) | ||
101 | { | ||
102 | unsigned long tcmp; | ||
103 | |||
104 | tcmp = IMX_TCN(TIMER_BASE) + evt; | ||
105 | IMX_TCMP(TIMER_BASE) = tcmp; | ||
106 | |||
107 | return (int32_t)(tcmp - IMX_TCN(TIMER_BASE)) < 0 ? -ETIME : 0; | ||
108 | } | ||
109 | |||
110 | #ifdef DEBUG | ||
111 | static const char *clock_event_mode_label[]={ | ||
112 | [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC", | ||
113 | [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT", | ||
114 | [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN", | ||
115 | [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED" | ||
116 | }; | ||
117 | #endif /*DEBUG*/ | ||
118 | |||
119 | static void imx_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) | ||
120 | { | ||
121 | unsigned long flags; | ||
122 | |||
123 | /* | ||
124 | * The timer interrupt generation is disabled at least | ||
125 | * for enough time to call imx_set_next_event() | ||
126 | */ | ||
127 | local_irq_save(flags); | ||
128 | /* Disable interrupt in GPT module */ | ||
129 | IMX_TCTL(TIMER_BASE) &= ~TCTL_IRQEN; | ||
130 | if (mode != clockevent_mode) { | ||
131 | /* Set event time into far-far future */ | ||
132 | IMX_TCMP(TIMER_BASE) = IMX_TCN(TIMER_BASE) - 3; | ||
133 | /* Clear pending interrupt */ | ||
134 | IMX_TSTAT(TIMER_BASE) &= ~TSTAT_COMP; | ||
135 | } | ||
136 | |||
137 | #ifdef DEBUG | ||
138 | printk(KERN_INFO "imx_set_mode: changing mode from %s to %s\n", | ||
139 | clock_event_mode_label[clockevent_mode], clock_event_mode_label[mode]); | ||
140 | #endif /*DEBUG*/ | ||
141 | |||
142 | /* Remember timer mode */ | ||
143 | clockevent_mode = mode; | ||
144 | local_irq_restore(flags); | ||
145 | |||
146 | switch (mode) { | ||
147 | case CLOCK_EVT_MODE_PERIODIC: | ||
148 | printk(KERN_ERR "imx_set_mode: Periodic mode is not supported for i.MX\n"); | ||
149 | break; | ||
150 | case CLOCK_EVT_MODE_ONESHOT: | ||
151 | /* | ||
152 | * Do not put overhead of interrupt enable/disable into | ||
153 | * imx_set_next_event(), the core has about 4 minutes | ||
154 | * to call imx_set_next_event() or shutdown clock after | ||
155 | * mode switching | ||
156 | */ | ||
157 | local_irq_save(flags); | ||
158 | IMX_TCTL(TIMER_BASE) |= TCTL_IRQEN; | ||
159 | local_irq_restore(flags); | ||
160 | break; | ||
161 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
162 | case CLOCK_EVT_MODE_UNUSED: | ||
163 | case CLOCK_EVT_MODE_RESUME: | ||
164 | /* Left event sources disabled, no more interrupts appears */ | ||
165 | break; | ||
166 | } | ||
167 | } | ||
168 | |||
169 | static struct clock_event_device clockevent_imx = { | ||
170 | .name = "imx_timer1", | ||
171 | .features = CLOCK_EVT_FEAT_ONESHOT, | ||
172 | .shift = 32, | ||
173 | .set_mode = imx_set_mode, | ||
174 | .set_next_event = imx_set_next_event, | ||
175 | .rating = 200, | ||
176 | }; | ||
177 | |||
178 | static int __init imx_clockevent_init(unsigned long rate) | ||
179 | { | ||
180 | clockevent_imx.mult = div_sc(rate, NSEC_PER_SEC, | ||
181 | clockevent_imx.shift); | ||
182 | clockevent_imx.max_delta_ns = | ||
183 | clockevent_delta2ns(0xfffffffe, &clockevent_imx); | ||
184 | clockevent_imx.min_delta_ns = | ||
185 | clockevent_delta2ns(0xf, &clockevent_imx); | ||
186 | |||
187 | clockevent_imx.cpumask = cpumask_of(0); | ||
188 | |||
189 | clockevents_register_device(&clockevent_imx); | ||
190 | |||
191 | return 0; | ||
192 | } | ||
193 | |||
194 | extern int imx_clocks_init(void); | ||
195 | |||
196 | static void __init imx_timer_init(void) | ||
197 | { | ||
198 | struct clk *clk; | ||
199 | unsigned long rate; | ||
200 | |||
201 | imx_clocks_init(); | ||
202 | |||
203 | clk = clk_get(NULL, "perclk1"); | ||
204 | clk_enable(clk); | ||
205 | rate = clk_get_rate(clk); | ||
206 | |||
207 | imx_timer_hardware_init(); | ||
208 | imx_clocksource_init(rate); | ||
209 | |||
210 | imx_clockevent_init(rate); | ||
211 | |||
212 | /* | ||
213 | * Make irqs happen for the system timer | ||
214 | */ | ||
215 | setup_irq(TIM1_INT, &imx_timer_irq); | ||
216 | } | ||
217 | |||
218 | struct sys_timer imx_timer = { | ||
219 | .init = imx_timer_init, | ||
220 | }; | ||