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-rw-r--r--arch/arm/Kconfig50
-rw-r--r--arch/arm/Kconfig-nommu8
-rw-r--r--arch/arm/Makefile9
-rw-r--r--arch/arm/boot/compressed/Makefile4
-rw-r--r--arch/arm/boot/compressed/head.S22
-rw-r--r--arch/arm/boot/compressed/misc.c21
-rw-r--r--arch/arm/common/icst307.c4
-rw-r--r--arch/arm/common/icst525.c4
-rw-r--r--arch/arm/common/locomo.c61
-rw-r--r--arch/arm/common/sharpsl_pm.c4
-rw-r--r--arch/arm/configs/ep93xx_defconfig1
-rw-r--r--arch/arm/configs/iop32x_defconfig (renamed from arch/arm/configs/ep80219_defconfig)602
-rw-r--r--arch/arm/configs/iop33x_defconfig (renamed from arch/arm/configs/iq80332_defconfig)473
-rw-r--r--arch/arm/configs/iq31244_defconfig922
-rw-r--r--arch/arm/configs/iq80321_defconfig843
-rw-r--r--arch/arm/configs/iq80331_defconfig916
-rw-r--r--arch/arm/configs/s3c2410_defconfig46
-rw-r--r--arch/arm/kernel/apm.c33
-rw-r--r--arch/arm/kernel/debug.S35
-rw-r--r--arch/arm/kernel/entry-armv.S13
-rw-r--r--arch/arm/kernel/head-nommu.S12
-rw-r--r--arch/arm/kernel/module.c8
-rw-r--r--arch/arm/kernel/process.c22
-rw-r--r--arch/arm/kernel/time.c6
-rw-r--r--arch/arm/kernel/traps.c2
-rw-r--r--arch/arm/mach-at91rm9200/at91rm9200.c250
-rw-r--r--arch/arm/mach-at91rm9200/board-1arm.c20
-rw-r--r--arch/arm/mach-at91rm9200/board-carmeva.c21
-rw-r--r--arch/arm/mach-at91rm9200/board-csb337.c20
-rw-r--r--arch/arm/mach-at91rm9200/board-csb637.c20
-rw-r--r--arch/arm/mach-at91rm9200/board-dk.c45
-rw-r--r--arch/arm/mach-at91rm9200/board-eb9200.c20
-rw-r--r--arch/arm/mach-at91rm9200/board-ek.c20
-rw-r--r--arch/arm/mach-at91rm9200/board-kafa.c20
-rw-r--r--arch/arm/mach-at91rm9200/board-kb9202.c45
-rw-r--r--arch/arm/mach-at91rm9200/clock.c324
-rw-r--r--arch/arm/mach-at91rm9200/clock.h30
-rw-r--r--arch/arm/mach-at91rm9200/devices.c72
-rw-r--r--arch/arm/mach-at91rm9200/generic.h20
-rw-r--r--arch/arm/mach-at91rm9200/gpio.c89
-rw-r--r--arch/arm/mach-at91rm9200/irq.c6
-rw-r--r--arch/arm/mach-at91rm9200/pm.c14
-rw-r--r--arch/arm/mach-ep93xx/Kconfig6
-rw-r--r--arch/arm/mach-ep93xx/Makefile1
-rw-r--r--arch/arm/mach-ep93xx/edb9312.c63
-rw-r--r--arch/arm/mach-footbridge/dc21285.c27
-rw-r--r--arch/arm/mach-iop32x/Kconfig35
-rw-r--r--arch/arm/mach-iop32x/Makefile13
-rw-r--r--arch/arm/mach-iop32x/Makefile.boot3
-rw-r--r--arch/arm/mach-iop32x/glantank.c195
-rw-r--r--arch/arm/mach-iop32x/iq31244.c293
-rw-r--r--arch/arm/mach-iop32x/iq80321.c193
-rw-r--r--arch/arm/mach-iop32x/irq.c76
-rw-r--r--arch/arm/mach-iop32x/n2100.c251
-rw-r--r--arch/arm/mach-iop33x/Kconfig21
-rw-r--r--arch/arm/mach-iop33x/Makefile11
-rw-r--r--arch/arm/mach-iop33x/Makefile.boot3
-rw-r--r--arch/arm/mach-iop33x/iq80331.c148
-rw-r--r--arch/arm/mach-iop33x/iq80332.c148
-rw-r--r--arch/arm/mach-iop33x/irq.c127
-rw-r--r--arch/arm/mach-iop33x/uart.c105
-rw-r--r--arch/arm/mach-iop3xx/Kconfig66
-rw-r--r--arch/arm/mach-iop3xx/Makefile23
-rw-r--r--arch/arm/mach-iop3xx/Makefile.boot9
-rw-r--r--arch/arm/mach-iop3xx/common.c72
-rw-r--r--arch/arm/mach-iop3xx/iop321-irq.c97
-rw-r--r--arch/arm/mach-iop3xx/iop321-pci.c220
-rw-r--r--arch/arm/mach-iop3xx/iop321-setup.c173
-rw-r--r--arch/arm/mach-iop3xx/iop321-time.c108
-rw-r--r--arch/arm/mach-iop3xx/iop331-irq.c129
-rw-r--r--arch/arm/mach-iop3xx/iop331-pci.c222
-rw-r--r--arch/arm/mach-iop3xx/iop331-setup.c221
-rw-r--r--arch/arm/mach-iop3xx/iop331-time.c106
-rw-r--r--arch/arm/mach-iop3xx/iq31244-mm.c45
-rw-r--r--arch/arm/mach-iop3xx/iq31244-pci.c129
-rw-r--r--arch/arm/mach-iop3xx/iq80321-mm.c45
-rw-r--r--arch/arm/mach-iop3xx/iq80321-pci.c123
-rw-r--r--arch/arm/mach-iop3xx/iq80331-mm.c35
-rw-r--r--arch/arm/mach-iop3xx/iq80331-pci.c119
-rw-r--r--arch/arm/mach-iop3xx/iq80332-mm.c35
-rw-r--r--arch/arm/mach-iop3xx/iq80332-pci.c125
-rw-r--r--arch/arm/mach-ixp4xx/common.c38
-rw-r--r--arch/arm/mach-ixp4xx/nslu2-setup.c2
-rw-r--r--arch/arm/mach-omap1/clock.c107
-rw-r--r--arch/arm/mach-omap1/clock.h14
-rw-r--r--arch/arm/mach-omap1/mux.c11
-rw-r--r--arch/arm/mach-omap2/board-apollon.c7
-rw-r--r--arch/arm/mach-omap2/clock.c146
-rw-r--r--arch/arm/mach-omap2/clock.h20
-rw-r--r--arch/arm/mach-omap2/gpmc.c180
-rw-r--r--arch/arm/mach-omap2/irq.c12
-rw-r--r--arch/arm/mach-omap2/mux.c14
-rw-r--r--arch/arm/mach-omap2/prcm.c10
-rw-r--r--arch/arm/mach-s3c2410/Kconfig38
-rw-r--r--arch/arm/mach-s3c2410/Makefile16
-rw-r--r--arch/arm/mach-s3c2410/bast-irq.c4
-rw-r--r--arch/arm/mach-s3c2410/cpu.c9
-rw-r--r--arch/arm/mach-s3c2410/devs.h5
-rw-r--r--arch/arm/mach-s3c2410/dma.c241
-rw-r--r--arch/arm/mach-s3c2410/dma.h45
-rw-r--r--arch/arm/mach-s3c2410/gpio.c16
-rw-r--r--arch/arm/mach-s3c2410/irq.c165
-rw-r--r--arch/arm/mach-s3c2410/mach-amlm5900.c266
-rw-r--r--arch/arm/mach-s3c2410/mach-anubis.c6
-rw-r--r--arch/arm/mach-s3c2410/mach-smdk2440.c9
-rw-r--r--arch/arm/mach-s3c2410/mach-vstms.c168
-rw-r--r--arch/arm/mach-s3c2410/pm-simtec.c3
-rw-r--r--arch/arm/mach-s3c2410/pm.c72
-rw-r--r--arch/arm/mach-s3c2410/pm.h16
-rw-r--r--arch/arm/mach-s3c2410/s3c2410-dma.c158
-rw-r--r--arch/arm/mach-s3c2410/s3c2410-irq.c48
-rw-r--r--arch/arm/mach-s3c2410/s3c2410-pm.c120
-rw-r--r--arch/arm/mach-s3c2410/s3c2410-sleep.S68
-rw-r--r--arch/arm/mach-s3c2410/s3c2410.c11
-rw-r--r--arch/arm/mach-s3c2410/s3c2412-dma.c160
-rw-r--r--arch/arm/mach-s3c2410/s3c2412-irq.c3
-rw-r--r--arch/arm/mach-s3c2410/s3c2412-pm.c128
-rw-r--r--arch/arm/mach-s3c2410/s3c2412.c61
-rw-r--r--arch/arm/mach-s3c2410/s3c2440-dma.c164
-rw-r--r--arch/arm/mach-s3c2410/s3c2440-dsc.c5
-rw-r--r--arch/arm/mach-s3c2410/s3c2440-irq.c2
-rw-r--r--arch/arm/mach-s3c2410/s3c244x-irq.c9
-rw-r--r--arch/arm/mach-s3c2410/sleep.S54
-rw-r--r--arch/arm/mach-s3c2410/usb-simtec.c6
-rw-r--r--arch/arm/mach-sa1100/collie.c23
-rw-r--r--arch/arm/mach-versatile/pci.c1
-rw-r--r--arch/arm/mm/Kconfig154
-rw-r--r--arch/arm/mm/Makefile10
-rw-r--r--arch/arm/mm/abort-lv4t.S7
-rw-r--r--arch/arm/mm/abort-nommu.S19
-rw-r--r--arch/arm/mm/alignment.c2
-rw-r--r--arch/arm/mm/cache-v4.S10
-rw-r--r--arch/arm/mm/context.c45
-rw-r--r--arch/arm/mm/copypage-v4mc.c4
-rw-r--r--arch/arm/mm/copypage-v6.c4
-rw-r--r--arch/arm/mm/copypage-xscale.c4
-rw-r--r--arch/arm/mm/fault.c15
-rw-r--r--arch/arm/mm/fault.h5
-rw-r--r--arch/arm/mm/flush.c6
-rw-r--r--arch/arm/mm/init.c224
-rw-r--r--arch/arm/mm/mm-armv.c663
-rw-r--r--arch/arm/mm/mm.h22
-rw-r--r--arch/arm/mm/mmap.c22
-rw-r--r--arch/arm/mm/mmu.c768
-rw-r--r--arch/arm/mm/nommu.c43
-rw-r--r--arch/arm/mm/pgd.c101
-rw-r--r--arch/arm/mm/proc-arm740.S174
-rw-r--r--arch/arm/mm/proc-arm7tdmi.S249
-rw-r--r--arch/arm/mm/proc-arm940.S369
-rw-r--r--arch/arm/mm/proc-arm946.S424
-rw-r--r--arch/arm/mm/proc-arm9tdmi.S134
-rw-r--r--arch/arm/mm/proc-xscale.S58
-rw-r--r--arch/arm/oprofile/op_model_xscale.c10
-rw-r--r--arch/arm/plat-iop/Makefile8
-rw-r--r--arch/arm/plat-iop/gpio.c48
-rw-r--r--arch/arm/plat-iop/i2c.c81
-rw-r--r--arch/arm/plat-iop/pci.c247
-rw-r--r--arch/arm/plat-iop/setup.c38
-rw-r--r--arch/arm/plat-iop/time.c98
-rw-r--r--arch/arm/plat-omap/clock.c26
-rw-r--r--arch/arm/plat-omap/devices.c20
-rw-r--r--arch/arm/plat-omap/dma.c95
-rw-r--r--arch/arm/plat-omap/dmtimer.c76
-rw-r--r--arch/arm/plat-omap/gpio.c45
-rw-r--r--arch/arm/plat-omap/mcbsp.c9
-rw-r--r--arch/arm/plat-omap/pm.c670
-rw-r--r--arch/arm/plat-omap/sram.c5
-rw-r--r--arch/arm/plat-omap/timer32k.c38
-rw-r--r--arch/arm/tools/mach-types74
-rw-r--r--arch/arm/vfp/vfp.h15
-rw-r--r--arch/arm/vfp/vfpdouble.c95
-rw-r--r--arch/arm/vfp/vfpinstr.h8
-rw-r--r--arch/arm/vfp/vfpmodule.c40
-rw-r--r--arch/arm/vfp/vfpsingle.c95
174 files changed, 9075 insertions, 7941 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f81a62380add..f9362ee9955f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -17,6 +17,10 @@ config ARM
17 Europe. There is an ARM Linux project with a web page at 17 Europe. There is an ARM Linux project with a web page at
18 <http://www.arm.linux.org.uk/>. 18 <http://www.arm.linux.org.uk/>.
19 19
20config GENERIC_TIME
21 bool
22 default n
23
20config MMU 24config MMU
21 bool 25 bool
22 default y 26 default y
@@ -51,6 +55,10 @@ config GENERIC_HARDIRQS
51 bool 55 bool
52 default y 56 default y
53 57
58config TRACE_IRQFLAGS_SUPPORT
59 bool
60 default y
61
54config HARDIRQS_SW_RESEND 62config HARDIRQS_SW_RESEND
55 bool 63 bool
56 default y 64 default y
@@ -91,7 +99,7 @@ config ARCH_MTD_XIP
91 99
92config VECTORS_BASE 100config VECTORS_BASE
93 hex 101 hex
94 default 0xffff0000 if MMU 102 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
95 default DRAM_BASE if REMAP_VECTORS_TO_RAM 103 default DRAM_BASE if REMAP_VECTORS_TO_RAM
96 default 0x00000000 104 default 0x00000000
97 help 105 help
@@ -198,16 +206,27 @@ config ARCH_IMX
198 help 206 help
199 Support for Motorola's i.MX family of processors (MX1, MXL). 207 Support for Motorola's i.MX family of processors (MX1, MXL).
200 208
201config ARCH_IOP3XX 209config ARCH_IOP32X
202 bool "IOP3xx-based" 210 bool "IOP32x-based"
211 depends on MMU
212 select PLAT_IOP
213 select PCI
214 help
215 Support for Intel's 80219 and IOP32X (XScale) family of
216 processors.
217
218config ARCH_IOP33X
219 bool "IOP33x-based"
203 depends on MMU 220 depends on MMU
221 select PLAT_IOP
204 select PCI 222 select PCI
205 help 223 help
206 Support for Intel's IOP3XX (XScale) family of processors. 224 Support for Intel's IOP33X (XScale) family of processors.
207 225
208config ARCH_IXP4XX 226config ARCH_IXP4XX
209 bool "IXP4xx-based" 227 bool "IXP4xx-based"
210 depends on MMU 228 depends on MMU
229 select GENERIC_TIME
211 help 230 help
212 Support for Intel's IXP4XX (XScale) family of processors. 231 Support for Intel's IXP4XX (XScale) family of processors.
213 232
@@ -308,7 +327,9 @@ source "arch/arm/mach-footbridge/Kconfig"
308 327
309source "arch/arm/mach-integrator/Kconfig" 328source "arch/arm/mach-integrator/Kconfig"
310 329
311source "arch/arm/mach-iop3xx/Kconfig" 330source "arch/arm/mach-iop32x/Kconfig"
331
332source "arch/arm/mach-iop33x/Kconfig"
312 333
313source "arch/arm/mach-ixp4xx/Kconfig" 334source "arch/arm/mach-ixp4xx/Kconfig"
314 335
@@ -348,6 +369,9 @@ source "arch/arm/mach-netx/Kconfig"
348config ARCH_ACORN 369config ARCH_ACORN
349 bool 370 bool
350 371
372config PLAT_IOP
373 bool
374
351source arch/arm/mm/Kconfig 375source arch/arm/mm/Kconfig
352 376
353# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER 377# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
@@ -602,6 +626,7 @@ config LEDS_CPU
602 626
603config ALIGNMENT_TRAP 627config ALIGNMENT_TRAP
604 bool 628 bool
629 depends on CPU_CP15_MMU
605 default y if !ARCH_EBSA110 630 default y if !ARCH_EBSA110
606 help 631 help
607 ARM processors can not fetch/store information which is not 632 ARM processors can not fetch/store information which is not
@@ -633,11 +658,12 @@ config ZBOOT_ROM_BSS
633 hex "Compressed ROM boot loader BSS address" 658 hex "Compressed ROM boot loader BSS address"
634 default "0" 659 default "0"
635 help 660 help
636 The base address of 64KiB of read/write memory in the target 661 The base address of an area of read/write memory in the target
637 for the ROM-able zImage, which must be available while the 662 for the ROM-able zImage which must be available while the
638 decompressor is running. Platforms which normally make use of 663 decompressor is running. It must be large enough to hold the
639 ROM-able zImage formats normally set this to a suitable 664 entire decompressed kernel plus an additional 128 KiB.
640 value in their defconfig file. 665 Platforms which normally make use of ROM-able zImage formats
666 normally set this to a suitable value in their defconfig file.
641 667
642 If ZBOOT_ROM is not enabled, this has no effect. 668 If ZBOOT_ROM is not enabled, this has no effect.
643 669
@@ -832,7 +858,7 @@ source "drivers/base/Kconfig"
832 858
833source "drivers/connector/Kconfig" 859source "drivers/connector/Kconfig"
834 860
835if ALIGNMENT_TRAP 861if ALIGNMENT_TRAP || !CPU_CP15_MMU
836source "drivers/mtd/Kconfig" 862source "drivers/mtd/Kconfig"
837endif 863endif
838 864
@@ -844,7 +870,7 @@ source "drivers/block/Kconfig"
844 870
845source "drivers/acorn/block/Kconfig" 871source "drivers/acorn/block/Kconfig"
846 872
847if PCMCIA || ARCH_CLPS7500 || ARCH_IOP3XX || ARCH_IXP4XX \ 873if PCMCIA || ARCH_CLPS7500 || ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX \
848 || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC \ 874 || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC \
849 || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE \ 875 || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE \
850 || ARCH_IXP23XX 876 || ARCH_IXP23XX
diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu
index e1574be2ded6..f087376748d1 100644
--- a/arch/arm/Kconfig-nommu
+++ b/arch/arm/Kconfig-nommu
@@ -25,6 +25,14 @@ config FLASH_SIZE
25 hex 'FLASH Size' if SET_MEM_PARAM 25 hex 'FLASH Size' if SET_MEM_PARAM
26 default 0x00400000 26 default 0x00400000
27 27
28config PROCESSOR_ID
29 hex
30 default 0x00007700
31 depends on !CPU_CP15
32 help
33 If processor has no CP15 register, this processor ID is
34 used instead of the auto-probing which utilizes the register.
35
28config REMAP_VECTORS_TO_RAM 36config REMAP_VECTORS_TO_RAM
29 bool 'Install vectors to the begining of RAM' if DRAM_BASE 37 bool 'Install vectors to the begining of RAM' if DRAM_BASE
30 depends on DRAM_BASE 38 depends on DRAM_BASE
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 92873cdee31f..2a0b2c8a1fe0 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -55,7 +55,12 @@ arch-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3 -march=armv3
55# This selects how we optimise for the processor. 55# This selects how we optimise for the processor.
56tune-$(CONFIG_CPU_ARM610) :=-mtune=arm610 56tune-$(CONFIG_CPU_ARM610) :=-mtune=arm610
57tune-$(CONFIG_CPU_ARM710) :=-mtune=arm710 57tune-$(CONFIG_CPU_ARM710) :=-mtune=arm710
58tune-$(CONFIG_CPU_ARM7TDMI) :=-mtune=arm7tdmi
58tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi 59tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi
60tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi
61tune-$(CONFIG_CPU_ARM9TDMI) :=-mtune=arm9tdmi
62tune-$(CONFIG_CPU_ARM940T) :=-mtune=arm9tdmi
63tune-$(CONFIG_CPU_ARM946T) :=$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
59tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi 64tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi
60tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi 65tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi
61tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi 66tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi
@@ -101,7 +106,8 @@ endif
101 machine-$(CONFIG_ARCH_INTEGRATOR) := integrator 106 machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
102 textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 107 textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
103 machine-$(CONFIG_ARCH_CLPS711X) := clps711x 108 machine-$(CONFIG_ARCH_CLPS711X) := clps711x
104 machine-$(CONFIG_ARCH_IOP3XX) := iop3xx 109 machine-$(CONFIG_ARCH_IOP32X) := iop32x
110 machine-$(CONFIG_ARCH_IOP33X) := iop33x
105 machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx 111 machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
106 machine-$(CONFIG_ARCH_IXP2000) := ixp2000 112 machine-$(CONFIG_ARCH_IXP2000) := ixp2000
107 machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx 113 machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
@@ -157,6 +163,7 @@ core-$(CONFIG_FPE_FASTFPE) += $(FASTFPE_OBJ)
157core-$(CONFIG_VFP) += arch/arm/vfp/ 163core-$(CONFIG_VFP) += arch/arm/vfp/
158 164
159# If we have a common platform directory, then include it in the build. 165# If we have a common platform directory, then include it in the build.
166core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/
160core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/ 167core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/
161 168
162drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ 169drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 2adc1527e0eb..adddc7131685 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -51,7 +51,11 @@ OBJS += head-at91rm9200.o
51endif 51endif
52 52
53ifeq ($(CONFIG_CPU_BIG_ENDIAN),y) 53ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
54ifeq ($(CONFIG_CPU_CP15),y)
54OBJS += big-endian.o 55OBJS += big-endian.o
56else
57# The endian should be set by h/w design.
58endif
55endif 59endif
56 60
57# 61#
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 14a9ff9c68df..e5ab51b9cceb 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -20,11 +20,21 @@
20#ifdef DEBUG 20#ifdef DEBUG
21 21
22#if defined(CONFIG_DEBUG_ICEDCC) 22#if defined(CONFIG_DEBUG_ICEDCC)
23
24#ifdef CONFIG_CPU_V6
25 .macro loadsp, rb
26 .endm
27 .macro writeb, ch, rb
28 mcr p14, 0, \ch, c0, c5, 0
29 .endm
30#else
23 .macro loadsp, rb 31 .macro loadsp, rb
24 .endm 32 .endm
25 .macro writeb, ch, rb 33 .macro writeb, ch, rb
26 mcr p14, 0, \ch, c0, c1, 0 34 mcr p14, 0, \ch, c0, c1, 0
27 .endm 35 .endm
36#endif
37
28#else 38#else
29 39
30#include <asm/arch/debug-macro.S> 40#include <asm/arch/debug-macro.S>
@@ -42,12 +52,6 @@
42 add \rb, \rb, #0x00010000 @ Ser1 52 add \rb, \rb, #0x00010000 @ Ser1
43#endif 53#endif
44 .endm 54 .endm
45#elif defined(CONFIG_ARCH_IOP331)
46 .macro loadsp, rb
47 mov \rb, #0xff000000
48 orr \rb, \rb, #0x00ff0000
49 orr \rb, \rb, #0x0000f700 @ location of the UART
50 .endm
51#elif defined(CONFIG_ARCH_S3C2410) 55#elif defined(CONFIG_ARCH_S3C2410)
52 .macro loadsp, rb 56 .macro loadsp, rb
53 mov \rb, #0x50000000 57 mov \rb, #0x50000000
@@ -78,9 +82,11 @@
78 kphex r6, 8 /* processor id */ 82 kphex r6, 8 /* processor id */
79 kputc #':' 83 kputc #':'
80 kphex r7, 8 /* architecture id */ 84 kphex r7, 8 /* architecture id */
85#ifdef CONFIG_CPU_CP15
81 kputc #':' 86 kputc #':'
82 mrc p15, 0, r0, c1, c0 87 mrc p15, 0, r0, c1, c0
83 kphex r0, 8 /* control reg */ 88 kphex r0, 8 /* control reg */
89#endif
84 kputc #'\n' 90 kputc #'\n'
85 kphex r5, 8 /* decompressed kernel start */ 91 kphex r5, 8 /* decompressed kernel start */
86 kputc #'-' 92 kputc #'-'
@@ -503,7 +509,11 @@ call_kernel: bl cache_clean_flush
503 */ 509 */
504 510
505call_cache_fn: adr r12, proc_types 511call_cache_fn: adr r12, proc_types
512#ifdef CONFIG_CPU_CP15
506 mrc p15, 0, r6, c0, c0 @ get processor ID 513 mrc p15, 0, r6, c0, c0 @ get processor ID
514#else
515 ldr r6, =CONFIG_PROCESSOR_ID
516#endif
5071: ldr r1, [r12, #0] @ get value 5171: ldr r1, [r12, #0] @ get value
508 ldr r2, [r12, #4] @ get mask 518 ldr r2, [r12, #4] @ get mask
509 eor r1, r1, r6 @ (real ^ match) 519 eor r1, r1, r6 @ (real ^ match)
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index ace3fb5835d9..283891c736c4 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -30,6 +30,25 @@ static void putstr(const char *ptr);
30#include <asm/arch/uncompress.h> 30#include <asm/arch/uncompress.h>
31 31
32#ifdef CONFIG_DEBUG_ICEDCC 32#ifdef CONFIG_DEBUG_ICEDCC
33
34#ifdef CONFIG_CPU_V6
35
36static void icedcc_putc(int ch)
37{
38 int status, i = 0x4000000;
39
40 do {
41 if (--i < 0)
42 return;
43
44 asm volatile ("mrc p14, 0, %0, c0, c1, 0" : "=r" (status));
45 } while (status & (1 << 29));
46
47 asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch));
48}
49
50#else
51
33static void icedcc_putc(int ch) 52static void icedcc_putc(int ch)
34{ 53{
35 int status, i = 0x4000000; 54 int status, i = 0x4000000;
@@ -44,6 +63,8 @@ static void icedcc_putc(int ch)
44 asm("mcr p14, 0, %0, c1, c0, 0" : : "r" (ch)); 63 asm("mcr p14, 0, %0, c1, c0, 0" : : "r" (ch));
45} 64}
46 65
66#endif
67
47#define putc(ch) icedcc_putc(ch) 68#define putc(ch) icedcc_putc(ch)
48#define flush() do { } while (0) 69#define flush() do { } while (0)
49#endif 70#endif
diff --git a/arch/arm/common/icst307.c b/arch/arm/common/icst307.c
index bafe8b19be82..6d094c157540 100644
--- a/arch/arm/common/icst307.c
+++ b/arch/arm/common/icst307.c
@@ -57,7 +57,7 @@ icst307_khz_to_vco(const struct icst307_params *p, unsigned long freq)
57 break; 57 break;
58 } while (i < ARRAY_SIZE(idx2s)); 58 } while (i < ARRAY_SIZE(idx2s));
59 59
60 if (i > ARRAY_SIZE(idx2s)) 60 if (i >= ARRAY_SIZE(idx2s))
61 return vco; 61 return vco;
62 62
63 vco.s = idx2s[i]; 63 vco.s = idx2s[i];
@@ -119,7 +119,7 @@ icst307_ps_to_vco(const struct icst307_params *p, unsigned long period)
119 break; 119 break;
120 } while (i < ARRAY_SIZE(idx2s)); 120 } while (i < ARRAY_SIZE(idx2s));
121 121
122 if (i > ARRAY_SIZE(idx2s)) 122 if (i >= ARRAY_SIZE(idx2s))
123 return vco; 123 return vco;
124 124
125 vco.s = idx2s[i]; 125 vco.s = idx2s[i];
diff --git a/arch/arm/common/icst525.c b/arch/arm/common/icst525.c
index 943ef88c0379..3d377c5bdef6 100644
--- a/arch/arm/common/icst525.c
+++ b/arch/arm/common/icst525.c
@@ -55,7 +55,7 @@ icst525_khz_to_vco(const struct icst525_params *p, unsigned long freq)
55 break; 55 break;
56 } while (i < ARRAY_SIZE(idx2s)); 56 } while (i < ARRAY_SIZE(idx2s));
57 57
58 if (i > ARRAY_SIZE(idx2s)) 58 if (i >= ARRAY_SIZE(idx2s))
59 return vco; 59 return vco;
60 60
61 vco.s = idx2s[i]; 61 vco.s = idx2s[i];
@@ -118,7 +118,7 @@ icst525_ps_to_vco(const struct icst525_params *p, unsigned long period)
118 break; 118 break;
119 } while (i < ARRAY_SIZE(idx2s)); 119 } while (i < ARRAY_SIZE(idx2s));
120 120
121 if (i > ARRAY_SIZE(idx2s)) 121 if (i >= ARRAY_SIZE(idx2s))
122 return vco; 122 return vco;
123 123
124 vco.s = idx2s[i]; 124 vco.s = idx2s[i];
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index 4e0dcaef6eb2..181ef1ead5b8 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -121,6 +121,13 @@ static struct locomo_dev_info locomo_devices[] = {
121 .offset = 0, 121 .offset = 0,
122 .length = 0, 122 .length = 0,
123 }, 123 },
124 {
125 .devid = LOCOMO_DEVID_SPI,
126 .irq = {},
127 .name = "locomo-spi",
128 .offset = LOCOMO_SPI,
129 .length = 0x30,
130 },
124}; 131};
125 132
126 133
@@ -374,7 +381,7 @@ static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc,
374 struct irqdesc *d; 381 struct irqdesc *d;
375 void __iomem *mapbase = get_irq_chipdata(irq); 382 void __iomem *mapbase = get_irq_chipdata(irq);
376 383
377 req = locomo_readl(mapbase + LOCOMO_SPIIR) & 0x000F; 384 req = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIR) & 0x000F;
378 if (req) { 385 if (req) {
379 irq = LOCOMO_IRQ_SPI_START; 386 irq = LOCOMO_IRQ_SPI_START;
380 d = irq_desc + irq; 387 d = irq_desc + irq;
@@ -391,35 +398,35 @@ static void locomo_spi_ack_irq(unsigned int irq)
391{ 398{
392 void __iomem *mapbase = get_irq_chipdata(irq); 399 void __iomem *mapbase = get_irq_chipdata(irq);
393 unsigned int r; 400 unsigned int r;
394 r = locomo_readl(mapbase + LOCOMO_SPIWE); 401 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIWE);
395 r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START)); 402 r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START));
396 locomo_writel(r, mapbase + LOCOMO_SPIWE); 403 locomo_writel(r, mapbase + LOCOMO_SPI + LOCOMO_SPIWE);
397 404
398 r = locomo_readl(mapbase + LOCOMO_SPIIS); 405 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIS);
399 r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START)); 406 r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START));
400 locomo_writel(r, mapbase + LOCOMO_SPIIS); 407 locomo_writel(r, mapbase + LOCOMO_SPI + LOCOMO_SPIIS);
401 408
402 r = locomo_readl(mapbase + LOCOMO_SPIWE); 409 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIWE);
403 r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START)); 410 r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START));
404 locomo_writel(r, mapbase + LOCOMO_SPIWE); 411 locomo_writel(r, mapbase + LOCOMO_SPI + LOCOMO_SPIWE);
405} 412}
406 413
407static void locomo_spi_mask_irq(unsigned int irq) 414static void locomo_spi_mask_irq(unsigned int irq)
408{ 415{
409 void __iomem *mapbase = get_irq_chipdata(irq); 416 void __iomem *mapbase = get_irq_chipdata(irq);
410 unsigned int r; 417 unsigned int r;
411 r = locomo_readl(mapbase + LOCOMO_SPIIE); 418 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE);
412 r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START)); 419 r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START));
413 locomo_writel(r, mapbase + LOCOMO_SPIIE); 420 locomo_writel(r, mapbase + LOCOMO_SPI + LOCOMO_SPIIE);
414} 421}
415 422
416static void locomo_spi_unmask_irq(unsigned int irq) 423static void locomo_spi_unmask_irq(unsigned int irq)
417{ 424{
418 void __iomem *mapbase = get_irq_chipdata(irq); 425 void __iomem *mapbase = get_irq_chipdata(irq);
419 unsigned int r; 426 unsigned int r;
420 r = locomo_readl(mapbase + LOCOMO_SPIIE); 427 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE);
421 r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START)); 428 r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START));
422 locomo_writel(r, mapbase + LOCOMO_SPIIE); 429 locomo_writel(r, mapbase + LOCOMO_SPI + LOCOMO_SPIIE);
423} 430}
424 431
425static struct irq_chip locomo_spi_chip = { 432static struct irq_chip locomo_spi_chip = {
@@ -814,12 +821,15 @@ static inline struct locomo *locomo_chip_driver(struct locomo_dev *ldev)
814 return (struct locomo *)dev_get_drvdata(ldev->dev.parent); 821 return (struct locomo *)dev_get_drvdata(ldev->dev.parent);
815} 822}
816 823
817void locomo_gpio_set_dir(struct locomo_dev *ldev, unsigned int bits, unsigned int dir) 824void locomo_gpio_set_dir(struct device *dev, unsigned int bits, unsigned int dir)
818{ 825{
819 struct locomo *lchip = locomo_chip_driver(ldev); 826 struct locomo *lchip = dev_get_drvdata(dev);
820 unsigned long flags; 827 unsigned long flags;
821 unsigned int r; 828 unsigned int r;
822 829
830 if (!lchip)
831 return;
832
823 spin_lock_irqsave(&lchip->lock, flags); 833 spin_lock_irqsave(&lchip->lock, flags);
824 834
825 r = locomo_readl(lchip->base + LOCOMO_GPD); 835 r = locomo_readl(lchip->base + LOCOMO_GPD);
@@ -836,12 +846,15 @@ void locomo_gpio_set_dir(struct locomo_dev *ldev, unsigned int bits, unsigned in
836 spin_unlock_irqrestore(&lchip->lock, flags); 846 spin_unlock_irqrestore(&lchip->lock, flags);
837} 847}
838 848
839unsigned int locomo_gpio_read_level(struct locomo_dev *ldev, unsigned int bits) 849int locomo_gpio_read_level(struct device *dev, unsigned int bits)
840{ 850{
841 struct locomo *lchip = locomo_chip_driver(ldev); 851 struct locomo *lchip = dev_get_drvdata(dev);
842 unsigned long flags; 852 unsigned long flags;
843 unsigned int ret; 853 unsigned int ret;
844 854
855 if (!lchip)
856 return -ENODEV;
857
845 spin_lock_irqsave(&lchip->lock, flags); 858 spin_lock_irqsave(&lchip->lock, flags);
846 ret = locomo_readl(lchip->base + LOCOMO_GPL); 859 ret = locomo_readl(lchip->base + LOCOMO_GPL);
847 spin_unlock_irqrestore(&lchip->lock, flags); 860 spin_unlock_irqrestore(&lchip->lock, flags);
@@ -850,12 +863,15 @@ unsigned int locomo_gpio_read_level(struct locomo_dev *ldev, unsigned int bits)
850 return ret; 863 return ret;
851} 864}
852 865
853unsigned int locomo_gpio_read_output(struct locomo_dev *ldev, unsigned int bits) 866int locomo_gpio_read_output(struct device *dev, unsigned int bits)
854{ 867{
855 struct locomo *lchip = locomo_chip_driver(ldev); 868 struct locomo *lchip = dev_get_drvdata(dev);
856 unsigned long flags; 869 unsigned long flags;
857 unsigned int ret; 870 unsigned int ret;
858 871
872 if (!lchip)
873 return -ENODEV;
874
859 spin_lock_irqsave(&lchip->lock, flags); 875 spin_lock_irqsave(&lchip->lock, flags);
860 ret = locomo_readl(lchip->base + LOCOMO_GPO); 876 ret = locomo_readl(lchip->base + LOCOMO_GPO);
861 spin_unlock_irqrestore(&lchip->lock, flags); 877 spin_unlock_irqrestore(&lchip->lock, flags);
@@ -864,12 +880,15 @@ unsigned int locomo_gpio_read_output(struct locomo_dev *ldev, unsigned int bits)
864 return ret; 880 return ret;
865} 881}
866 882
867void locomo_gpio_write(struct locomo_dev *ldev, unsigned int bits, unsigned int set) 883void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set)
868{ 884{
869 struct locomo *lchip = locomo_chip_driver(ldev); 885 struct locomo *lchip = dev_get_drvdata(dev);
870 unsigned long flags; 886 unsigned long flags;
871 unsigned int r; 887 unsigned int r;
872 888
889 if (!lchip)
890 return;
891
873 spin_lock_irqsave(&lchip->lock, flags); 892 spin_lock_irqsave(&lchip->lock, flags);
874 893
875 r = locomo_readl(lchip->base + LOCOMO_GPO); 894 r = locomo_readl(lchip->base + LOCOMO_GPO);
@@ -1058,9 +1077,9 @@ void locomo_frontlight_set(struct locomo_dev *dev, int duty, int vr, int bpwf)
1058 struct locomo *lchip = locomo_chip_driver(dev); 1077 struct locomo *lchip = locomo_chip_driver(dev);
1059 1078
1060 if (vr) 1079 if (vr)
1061 locomo_gpio_write(dev, LOCOMO_GPIO_FL_VR, 1); 1080 locomo_gpio_write(dev->dev.parent, LOCOMO_GPIO_FL_VR, 1);
1062 else 1081 else
1063 locomo_gpio_write(dev, LOCOMO_GPIO_FL_VR, 0); 1082 locomo_gpio_write(dev->dev.parent, LOCOMO_GPIO_FL_VR, 0);
1064 1083
1065 spin_lock_irqsave(&lchip->lock, flags); 1084 spin_lock_irqsave(&lchip->lock, flags);
1066 locomo_writel(bpwf, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS); 1085 locomo_writel(bpwf, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS);
diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c
index 59b5ddec480f..f412dedda684 100644
--- a/arch/arm/common/sharpsl_pm.c
+++ b/arch/arm/common/sharpsl_pm.c
@@ -40,6 +40,7 @@
40#define SHARPSL_CHARGE_FINISH_TIME (msecs_to_jiffies(10*60*1000)) /* 10 min */ 40#define SHARPSL_CHARGE_FINISH_TIME (msecs_to_jiffies(10*60*1000)) /* 10 min */
41#define SHARPSL_BATCHK_TIME (msecs_to_jiffies(15*1000)) /* 15 sec */ 41#define SHARPSL_BATCHK_TIME (msecs_to_jiffies(15*1000)) /* 15 sec */
42#define SHARPSL_BATCHK_TIME_SUSPEND (60*10) /* 10 min */ 42#define SHARPSL_BATCHK_TIME_SUSPEND (60*10) /* 10 min */
43
43#define SHARPSL_WAIT_CO_TIME 15 /* 15 sec */ 44#define SHARPSL_WAIT_CO_TIME 15 /* 15 sec */
44#define SHARPSL_WAIT_DISCHARGE_ON 100 /* 100 msec */ 45#define SHARPSL_WAIT_DISCHARGE_ON 100 /* 100 msec */
45#define SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP 10 /* 10 msec */ 46#define SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP 10 /* 10 msec */
@@ -575,6 +576,9 @@ static int corgi_pxa_pm_enter(suspend_state_t state)
575 while (corgi_enter_suspend(alarm_time,alarm_status,state)) 576 while (corgi_enter_suspend(alarm_time,alarm_status,state))
576 {} 577 {}
577 578
579 if (sharpsl_pm.machinfo->earlyresume)
580 sharpsl_pm.machinfo->earlyresume();
581
578 dev_dbg(sharpsl_pm.dev, "SharpSL resuming...\n"); 582 dev_dbg(sharpsl_pm.dev, "SharpSL resuming...\n");
579 583
580 return 0; 584 return 0;
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index 2948b4589a8b..3b4802a849e4 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -126,6 +126,7 @@ CONFIG_CRUNCH=y
126# EP93xx Platforms 126# EP93xx Platforms
127# 127#
128CONFIG_MACH_EDB9302=y 128CONFIG_MACH_EDB9302=y
129CONFIG_MACH_EDB9312=y
129CONFIG_MACH_EDB9315=y 130CONFIG_MACH_EDB9315=y
130CONFIG_MACH_EDB9315A=y 131CONFIG_MACH_EDB9315A=y
131CONFIG_MACH_GESBC9312=y 132CONFIG_MACH_GESBC9312=y
diff --git a/arch/arm/configs/ep80219_defconfig b/arch/arm/configs/iop32x_defconfig
index 3c73b707c2f3..0d67f66e78c2 100644
--- a/arch/arm/configs/ep80219_defconfig
+++ b/arch/arm/configs/iop32x_defconfig
@@ -1,50 +1,63 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc1-bk2 3# Linux kernel version: 2.6.18-rc7
4# Sun Mar 27 22:34:12 2005 4# Tue Sep 19 00:30:18 2006
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_MMU=y 7CONFIG_MMU=y
8CONFIG_UID16=y 8CONFIG_GENERIC_HARDIRQS=y
9CONFIG_TRACE_IRQFLAGS_SUPPORT=y
10CONFIG_HARDIRQS_SW_RESEND=y
11CONFIG_GENERIC_IRQ_PROBE=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 12CONFIG_RWSEM_GENERIC_SPINLOCK=y
13CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 14CONFIG_GENERIC_CALIBRATE_DELAY=y
11CONFIG_GENERIC_IOMAP=y 15CONFIG_VECTORS_BASE=0xffff0000
16CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
12 17
13# 18#
14# Code maturity level options 19# Code maturity level options
15# 20#
16CONFIG_EXPERIMENTAL=y 21CONFIG_EXPERIMENTAL=y
17CONFIG_CLEAN_COMPILE=y
18CONFIG_BROKEN_ON_SMP=y 22CONFIG_BROKEN_ON_SMP=y
23CONFIG_INIT_ENV_ARG_LIMIT=32
19 24
20# 25#
21# General setup 26# General setup
22# 27#
23CONFIG_LOCALVERSION="" 28CONFIG_LOCALVERSION=""
29CONFIG_LOCALVERSION_AUTO=y
24CONFIG_SWAP=y 30CONFIG_SWAP=y
25CONFIG_SYSVIPC=y 31CONFIG_SYSVIPC=y
26# CONFIG_POSIX_MQUEUE is not set 32# CONFIG_POSIX_MQUEUE is not set
27CONFIG_BSD_PROCESS_ACCT=y 33CONFIG_BSD_PROCESS_ACCT=y
28# CONFIG_BSD_PROCESS_ACCT_V3 is not set 34# CONFIG_BSD_PROCESS_ACCT_V3 is not set
35# CONFIG_TASKSTATS is not set
29CONFIG_SYSCTL=y 36CONFIG_SYSCTL=y
30# CONFIG_AUDIT is not set 37# CONFIG_AUDIT is not set
31# CONFIG_HOTPLUG is not set
32CONFIG_KOBJECT_UEVENT=y
33# CONFIG_IKCONFIG is not set 38# CONFIG_IKCONFIG is not set
39# CONFIG_RELAY is not set
40CONFIG_INITRAMFS_SOURCE=""
41CONFIG_UID16=y
42CONFIG_CC_OPTIMIZE_FOR_SIZE=y
34# CONFIG_EMBEDDED is not set 43# CONFIG_EMBEDDED is not set
35CONFIG_KALLSYMS=y 44CONFIG_KALLSYMS=y
45CONFIG_KALLSYMS_ALL=y
36# CONFIG_KALLSYMS_EXTRA_PASS is not set 46# CONFIG_KALLSYMS_EXTRA_PASS is not set
47CONFIG_HOTPLUG=y
48CONFIG_PRINTK=y
49CONFIG_BUG=y
50CONFIG_ELF_CORE=y
37CONFIG_BASE_FULL=y 51CONFIG_BASE_FULL=y
52CONFIG_RT_MUTEXES=y
38CONFIG_FUTEX=y 53CONFIG_FUTEX=y
39CONFIG_EPOLL=y 54CONFIG_EPOLL=y
40CONFIG_CC_OPTIMIZE_FOR_SIZE=y
41CONFIG_SHMEM=y 55CONFIG_SHMEM=y
42CONFIG_CC_ALIGN_FUNCTIONS=0 56CONFIG_SLAB=y
43CONFIG_CC_ALIGN_LABELS=0 57CONFIG_VM_EVENT_COUNTERS=y
44CONFIG_CC_ALIGN_LOOPS=0
45CONFIG_CC_ALIGN_JUMPS=0
46# CONFIG_TINY_SHMEM is not set 58# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0 59CONFIG_BASE_SMALL=0
60# CONFIG_SLOB is not set
48 61
49# 62#
50# Loadable module support 63# Loadable module support
@@ -52,24 +65,52 @@ CONFIG_BASE_SMALL=0
52CONFIG_MODULES=y 65CONFIG_MODULES=y
53CONFIG_MODULE_UNLOAD=y 66CONFIG_MODULE_UNLOAD=y
54# CONFIG_MODULE_FORCE_UNLOAD is not set 67# CONFIG_MODULE_FORCE_UNLOAD is not set
55CONFIG_OBSOLETE_MODPARM=y
56# CONFIG_MODVERSIONS is not set 68# CONFIG_MODVERSIONS is not set
57# CONFIG_MODULE_SRCVERSION_ALL is not set 69# CONFIG_MODULE_SRCVERSION_ALL is not set
58CONFIG_KMOD=y 70CONFIG_KMOD=y
59 71
60# 72#
73# Block layer
74#
75# CONFIG_BLK_DEV_IO_TRACE is not set
76
77#
78# IO Schedulers
79#
80CONFIG_IOSCHED_NOOP=y
81CONFIG_IOSCHED_AS=y
82CONFIG_IOSCHED_DEADLINE=y
83CONFIG_IOSCHED_CFQ=y
84# CONFIG_DEFAULT_AS is not set
85# CONFIG_DEFAULT_DEADLINE is not set
86CONFIG_DEFAULT_CFQ=y
87# CONFIG_DEFAULT_NOOP is not set
88CONFIG_DEFAULT_IOSCHED="cfq"
89
90#
61# System Type 91# System Type
62# 92#
93# CONFIG_ARCH_AAEC2000 is not set
94# CONFIG_ARCH_INTEGRATOR is not set
95# CONFIG_ARCH_REALVIEW is not set
96# CONFIG_ARCH_VERSATILE is not set
97# CONFIG_ARCH_AT91 is not set
63# CONFIG_ARCH_CLPS7500 is not set 98# CONFIG_ARCH_CLPS7500 is not set
64# CONFIG_ARCH_CLPS711X is not set 99# CONFIG_ARCH_CLPS711X is not set
65# CONFIG_ARCH_CO285 is not set 100# CONFIG_ARCH_CO285 is not set
66# CONFIG_ARCH_EBSA110 is not set 101# CONFIG_ARCH_EBSA110 is not set
102# CONFIG_ARCH_EP93XX is not set
67# CONFIG_ARCH_FOOTBRIDGE is not set 103# CONFIG_ARCH_FOOTBRIDGE is not set
68# CONFIG_ARCH_INTEGRATOR is not set 104# CONFIG_ARCH_NETX is not set
69CONFIG_ARCH_IOP3XX=y 105# CONFIG_ARCH_H720X is not set
106# CONFIG_ARCH_IMX is not set
107CONFIG_ARCH_IOP32X=y
108# CONFIG_ARCH_IOP33X is not set
70# CONFIG_ARCH_IXP4XX is not set 109# CONFIG_ARCH_IXP4XX is not set
71# CONFIG_ARCH_IXP2000 is not set 110# CONFIG_ARCH_IXP2000 is not set
111# CONFIG_ARCH_IXP23XX is not set
72# CONFIG_ARCH_L7200 is not set 112# CONFIG_ARCH_L7200 is not set
113# CONFIG_ARCH_PNX4008 is not set
73# CONFIG_ARCH_PXA is not set 114# CONFIG_ARCH_PXA is not set
74# CONFIG_ARCH_RPC is not set 115# CONFIG_ARCH_RPC is not set
75# CONFIG_ARCH_SA1100 is not set 116# CONFIG_ARCH_SA1100 is not set
@@ -77,28 +118,19 @@ CONFIG_ARCH_IOP3XX=y
77# CONFIG_ARCH_SHARK is not set 118# CONFIG_ARCH_SHARK is not set
78# CONFIG_ARCH_LH7A40X is not set 119# CONFIG_ARCH_LH7A40X is not set
79# CONFIG_ARCH_OMAP is not set 120# CONFIG_ARCH_OMAP is not set
80# CONFIG_ARCH_VERSATILE is not set
81# CONFIG_ARCH_IMX is not set
82# CONFIG_ARCH_H720X is not set
83 121
84# 122#
85# IOP3xx Implementation Options 123# IOP32x Implementation Options
86# 124#
87 125
88# 126#
89# IOP3xx Platform Types 127# IOP32x Platform Types
90# 128#
91# CONFIG_ARCH_IQ80321 is not set 129CONFIG_MACH_GLANTANK=y
130CONFIG_ARCH_IQ80321=y
92CONFIG_ARCH_IQ31244=y 131CONFIG_ARCH_IQ31244=y
93# CONFIG_ARCH_IQ80331 is not set 132CONFIG_MACH_N2100=y
94# CONFIG_MACH_IQ80332 is not set 133CONFIG_PLAT_IOP=y
95CONFIG_ARCH_EP80219=y
96CONFIG_ARCH_IOP321=y
97# CONFIG_ARCH_IOP331 is not set
98
99#
100# IOP3xx Chipset Features
101#
102 134
103# 135#
104# Processor Type 136# Processor Type
@@ -109,7 +141,6 @@ CONFIG_CPU_32v5=y
109CONFIG_CPU_ABRT_EV5T=y 141CONFIG_CPU_ABRT_EV5T=y
110CONFIG_CPU_CACHE_VIVT=y 142CONFIG_CPU_CACHE_VIVT=y
111CONFIG_CPU_TLB_V4WBI=y 143CONFIG_CPU_TLB_V4WBI=y
112CONFIG_CPU_MINICACHE=y
113 144
114# 145#
115# Processor Features 146# Processor Features
@@ -121,8 +152,7 @@ CONFIG_XSCALE_PMU=y
121# Bus support 152# Bus support
122# 153#
123CONFIG_PCI=y 154CONFIG_PCI=y
124# CONFIG_PCI_LEGACY_PROC is not set 155# CONFIG_PCI_DEBUG is not set
125CONFIG_PCI_NAMES=y
126 156
127# 157#
128# PCCARD (PCMCIA/CardBus) support 158# PCCARD (PCMCIA/CardBus) support
@@ -133,6 +163,19 @@ CONFIG_PCI_NAMES=y
133# Kernel Features 163# Kernel Features
134# 164#
135# CONFIG_PREEMPT is not set 165# CONFIG_PREEMPT is not set
166# CONFIG_NO_IDLE_HZ is not set
167CONFIG_HZ=100
168# CONFIG_AEABI is not set
169# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
170CONFIG_SELECT_MEMORY_MODEL=y
171CONFIG_FLATMEM_MANUAL=y
172# CONFIG_DISCONTIGMEM_MANUAL is not set
173# CONFIG_SPARSEMEM_MANUAL is not set
174CONFIG_FLATMEM=y
175CONFIG_FLAT_NODE_MEM_MAP=y
176# CONFIG_SPARSEMEM_STATIC is not set
177CONFIG_SPLIT_PTLOCK_CPUS=4096
178# CONFIG_RESOURCES_64BIT is not set
136CONFIG_ALIGNMENT_TRAP=y 179CONFIG_ALIGNMENT_TRAP=y
137 180
138# 181#
@@ -140,7 +183,7 @@ CONFIG_ALIGNMENT_TRAP=y
140# 183#
141CONFIG_ZBOOT_ROM_TEXT=0x0 184CONFIG_ZBOOT_ROM_TEXT=0x0
142CONFIG_ZBOOT_ROM_BSS=0x0 185CONFIG_ZBOOT_ROM_BSS=0x0
143CONFIG_CMDLINE="ip=boot root=nfs console=ttyS0,115200" 186CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp"
144# CONFIG_XIP_KERNEL is not set 187# CONFIG_XIP_KERNEL is not set
145 188
146# 189#
@@ -166,6 +209,93 @@ CONFIG_BINFMT_AOUT=y
166# Power management options 209# Power management options
167# 210#
168# CONFIG_PM is not set 211# CONFIG_PM is not set
212# CONFIG_APM is not set
213
214#
215# Networking
216#
217CONFIG_NET=y
218
219#
220# Networking options
221#
222# CONFIG_NETDEBUG is not set
223CONFIG_PACKET=y
224CONFIG_PACKET_MMAP=y
225CONFIG_UNIX=y
226CONFIG_XFRM=y
227# CONFIG_XFRM_USER is not set
228# CONFIG_NET_KEY is not set
229CONFIG_INET=y
230CONFIG_IP_MULTICAST=y
231# CONFIG_IP_ADVANCED_ROUTER is not set
232CONFIG_IP_FIB_HASH=y
233CONFIG_IP_PNP=y
234# CONFIG_IP_PNP_DHCP is not set
235CONFIG_IP_PNP_BOOTP=y
236# CONFIG_IP_PNP_RARP is not set
237# CONFIG_NET_IPIP is not set
238# CONFIG_NET_IPGRE is not set
239# CONFIG_IP_MROUTE is not set
240# CONFIG_ARPD is not set
241# CONFIG_SYN_COOKIES is not set
242# CONFIG_INET_AH is not set
243# CONFIG_INET_ESP is not set
244# CONFIG_INET_IPCOMP is not set
245# CONFIG_INET_XFRM_TUNNEL is not set
246# CONFIG_INET_TUNNEL is not set
247CONFIG_INET_XFRM_MODE_TRANSPORT=y
248CONFIG_INET_XFRM_MODE_TUNNEL=y
249CONFIG_INET_DIAG=y
250CONFIG_INET_TCP_DIAG=y
251# CONFIG_TCP_CONG_ADVANCED is not set
252CONFIG_TCP_CONG_BIC=y
253# CONFIG_IPV6 is not set
254# CONFIG_INET6_XFRM_TUNNEL is not set
255# CONFIG_INET6_TUNNEL is not set
256# CONFIG_NETWORK_SECMARK is not set
257# CONFIG_NETFILTER is not set
258
259#
260# DCCP Configuration (EXPERIMENTAL)
261#
262# CONFIG_IP_DCCP is not set
263
264#
265# SCTP Configuration (EXPERIMENTAL)
266#
267# CONFIG_IP_SCTP is not set
268
269#
270# TIPC Configuration (EXPERIMENTAL)
271#
272# CONFIG_TIPC is not set
273# CONFIG_ATM is not set
274# CONFIG_BRIDGE is not set
275# CONFIG_VLAN_8021Q is not set
276# CONFIG_DECNET is not set
277# CONFIG_LLC2 is not set
278# CONFIG_IPX is not set
279# CONFIG_ATALK is not set
280# CONFIG_X25 is not set
281# CONFIG_LAPB is not set
282# CONFIG_NET_DIVERT is not set
283# CONFIG_ECONET is not set
284# CONFIG_WAN_ROUTER is not set
285
286#
287# QoS and/or fair queueing
288#
289# CONFIG_NET_SCHED is not set
290
291#
292# Network testing
293#
294# CONFIG_NET_PKTGEN is not set
295# CONFIG_HAMRADIO is not set
296# CONFIG_IRDA is not set
297# CONFIG_BT is not set
298# CONFIG_IEEE80211 is not set
169 299
170# 300#
171# Device Drivers 301# Device Drivers
@@ -177,6 +307,13 @@ CONFIG_BINFMT_AOUT=y
177CONFIG_STANDALONE=y 307CONFIG_STANDALONE=y
178CONFIG_PREVENT_FIRMWARE_BUILD=y 308CONFIG_PREVENT_FIRMWARE_BUILD=y
179# CONFIG_FW_LOADER is not set 309# CONFIG_FW_LOADER is not set
310# CONFIG_DEBUG_DRIVER is not set
311# CONFIG_SYS_HYPERVISOR is not set
312
313#
314# Connector - unified userspace <-> kernelspace linker
315#
316# CONFIG_CONNECTOR is not set
180 317
181# 318#
182# Memory Technology Devices (MTD) 319# Memory Technology Devices (MTD)
@@ -200,6 +337,7 @@ CONFIG_MTD_BLOCK=y
200# CONFIG_FTL is not set 337# CONFIG_FTL is not set
201# CONFIG_NFTL is not set 338# CONFIG_NFTL is not set
202# CONFIG_INFTL is not set 339# CONFIG_INFTL is not set
340# CONFIG_RFD_FTL is not set
203 341
204# 342#
205# RAM/ROM/Flash chip drivers 343# RAM/ROM/Flash chip drivers
@@ -225,18 +363,18 @@ CONFIG_MTD_CFI_UTIL=y
225# CONFIG_MTD_RAM is not set 363# CONFIG_MTD_RAM is not set
226# CONFIG_MTD_ROM is not set 364# CONFIG_MTD_ROM is not set
227# CONFIG_MTD_ABSENT is not set 365# CONFIG_MTD_ABSENT is not set
228# CONFIG_MTD_XIP is not set 366# CONFIG_MTD_OBSOLETE_CHIPS is not set
229 367
230# 368#
231# Mapping drivers for chip access 369# Mapping drivers for chip access
232# 370#
233# CONFIG_MTD_COMPLEX_MAPPINGS is not set 371# CONFIG_MTD_COMPLEX_MAPPINGS is not set
234CONFIG_MTD_PHYSMAP=y 372CONFIG_MTD_PHYSMAP=y
235CONFIG_MTD_PHYSMAP_START=0xf0000000 373CONFIG_MTD_PHYSMAP_START=0x0
236CONFIG_MTD_PHYSMAP_LEN=0x00800000 374CONFIG_MTD_PHYSMAP_LEN=0x0
237CONFIG_MTD_PHYSMAP_BANKWIDTH=2 375CONFIG_MTD_PHYSMAP_BANKWIDTH=1
238# CONFIG_MTD_ARM_INTEGRATOR is not set 376# CONFIG_MTD_ARM_INTEGRATOR is not set
239# CONFIG_MTD_EDB7312 is not set 377# CONFIG_MTD_PLATRAM is not set
240 378
241# 379#
242# Self-contained MTD device drivers 380# Self-contained MTD device drivers
@@ -245,7 +383,6 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
245# CONFIG_MTD_SLRAM is not set 383# CONFIG_MTD_SLRAM is not set
246# CONFIG_MTD_PHRAM is not set 384# CONFIG_MTD_PHRAM is not set
247# CONFIG_MTD_MTDRAM is not set 385# CONFIG_MTD_MTDRAM is not set
248# CONFIG_MTD_BLKMTD is not set
249# CONFIG_MTD_BLOCK2MTD is not set 386# CONFIG_MTD_BLOCK2MTD is not set
250 387
251# 388#
@@ -261,6 +398,11 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
261# CONFIG_MTD_NAND is not set 398# CONFIG_MTD_NAND is not set
262 399
263# 400#
401# OneNAND Flash Device Drivers
402#
403# CONFIG_MTD_ONENAND is not set
404
405#
264# Parallel port support 406# Parallel port support
265# 407#
266# CONFIG_PARPORT is not set 408# CONFIG_PARPORT is not set
@@ -272,7 +414,6 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
272# 414#
273# Block devices 415# Block devices
274# 416#
275# CONFIG_BLK_DEV_FD is not set
276# CONFIG_BLK_CPQ_DA is not set 417# CONFIG_BLK_CPQ_DA is not set
277# CONFIG_BLK_CPQ_CISS_DA is not set 418# CONFIG_BLK_CPQ_CISS_DA is not set
278# CONFIG_BLK_DEV_DAC960 is not set 419# CONFIG_BLK_DEV_DAC960 is not set
@@ -284,17 +425,9 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
284CONFIG_BLK_DEV_RAM=y 425CONFIG_BLK_DEV_RAM=y
285CONFIG_BLK_DEV_RAM_COUNT=16 426CONFIG_BLK_DEV_RAM_COUNT=16
286CONFIG_BLK_DEV_RAM_SIZE=8192 427CONFIG_BLK_DEV_RAM_SIZE=8192
287# CONFIG_BLK_DEV_INITRD is not set 428CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
288CONFIG_INITRAMFS_SOURCE="" 429CONFIG_BLK_DEV_INITRD=y
289# CONFIG_CDROM_PKTCDVD is not set 430# CONFIG_CDROM_PKTCDVD is not set
290
291#
292# IO Schedulers
293#
294CONFIG_IOSCHED_NOOP=y
295CONFIG_IOSCHED_AS=y
296CONFIG_IOSCHED_DEADLINE=y
297CONFIG_IOSCHED_CFQ=y
298# CONFIG_ATA_OVER_ETH is not set 431# CONFIG_ATA_OVER_ETH is not set
299 432
300# 433#
@@ -305,6 +438,7 @@ CONFIG_IOSCHED_CFQ=y
305# 438#
306# SCSI device support 439# SCSI device support
307# 440#
441# CONFIG_RAID_ATTRS is not set
308CONFIG_SCSI=y 442CONFIG_SCSI=y
309CONFIG_SCSI_PROC_FS=y 443CONFIG_SCSI_PROC_FS=y
310 444
@@ -316,6 +450,7 @@ CONFIG_BLK_DEV_SD=y
316# CONFIG_CHR_DEV_OSST is not set 450# CONFIG_CHR_DEV_OSST is not set
317# CONFIG_BLK_DEV_SR is not set 451# CONFIG_BLK_DEV_SR is not set
318CONFIG_CHR_DEV_SG=y 452CONFIG_CHR_DEV_SG=y
453# CONFIG_CHR_DEV_SCH is not set
319 454
320# 455#
321# Some SCSI devices (e.g. CD jukebox) support multiple LUNs 456# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -330,10 +465,12 @@ CONFIG_CHR_DEV_SG=y
330# CONFIG_SCSI_SPI_ATTRS is not set 465# CONFIG_SCSI_SPI_ATTRS is not set
331# CONFIG_SCSI_FC_ATTRS is not set 466# CONFIG_SCSI_FC_ATTRS is not set
332# CONFIG_SCSI_ISCSI_ATTRS is not set 467# CONFIG_SCSI_ISCSI_ATTRS is not set
468# CONFIG_SCSI_SAS_ATTRS is not set
333 469
334# 470#
335# SCSI low-level drivers 471# SCSI low-level drivers
336# 472#
473# CONFIG_ISCSI_TCP is not set
337# CONFIG_BLK_DEV_3W_XXXX_RAID is not set 474# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
338# CONFIG_SCSI_3W_9XXX is not set 475# CONFIG_SCSI_3W_9XXX is not set
339# CONFIG_SCSI_ACARD is not set 476# CONFIG_SCSI_ACARD is not set
@@ -344,25 +481,19 @@ CONFIG_CHR_DEV_SG=y
344# CONFIG_SCSI_DPT_I2O is not set 481# CONFIG_SCSI_DPT_I2O is not set
345# CONFIG_MEGARAID_NEWGEN is not set 482# CONFIG_MEGARAID_NEWGEN is not set
346# CONFIG_MEGARAID_LEGACY is not set 483# CONFIG_MEGARAID_LEGACY is not set
484# CONFIG_MEGARAID_SAS is not set
347# CONFIG_SCSI_SATA is not set 485# CONFIG_SCSI_SATA is not set
348# CONFIG_SCSI_BUSLOGIC is not set 486# CONFIG_SCSI_HPTIOP is not set
349# CONFIG_SCSI_DMX3191D is not set 487# CONFIG_SCSI_DMX3191D is not set
350# CONFIG_SCSI_EATA is not set
351# CONFIG_SCSI_FUTURE_DOMAIN is not set 488# CONFIG_SCSI_FUTURE_DOMAIN is not set
352# CONFIG_SCSI_GDTH is not set
353# CONFIG_SCSI_IPS is not set 489# CONFIG_SCSI_IPS is not set
354# CONFIG_SCSI_INITIO is not set 490# CONFIG_SCSI_INITIO is not set
355# CONFIG_SCSI_INIA100 is not set 491# CONFIG_SCSI_INIA100 is not set
356# CONFIG_SCSI_SYM53C8XX_2 is not set 492# CONFIG_SCSI_SYM53C8XX_2 is not set
357# CONFIG_SCSI_IPR is not set 493# CONFIG_SCSI_IPR is not set
358# CONFIG_SCSI_QLOGIC_FC is not set
359# CONFIG_SCSI_QLOGIC_1280 is not set 494# CONFIG_SCSI_QLOGIC_1280 is not set
360CONFIG_SCSI_QLA2XXX=y 495# CONFIG_SCSI_QLA_FC is not set
361# CONFIG_SCSI_QLA21XX is not set 496# CONFIG_SCSI_LPFC is not set
362# CONFIG_SCSI_QLA22XX is not set
363# CONFIG_SCSI_QLA2300 is not set
364# CONFIG_SCSI_QLA2322 is not set
365# CONFIG_SCSI_QLA6312 is not set
366# CONFIG_SCSI_DC395x is not set 497# CONFIG_SCSI_DC395x is not set
367# CONFIG_SCSI_DC390T is not set 498# CONFIG_SCSI_DC390T is not set
368# CONFIG_SCSI_NSP32 is not set 499# CONFIG_SCSI_NSP32 is not set
@@ -377,8 +508,7 @@ CONFIG_BLK_DEV_MD=y
377CONFIG_MD_RAID0=y 508CONFIG_MD_RAID0=y
378CONFIG_MD_RAID1=y 509CONFIG_MD_RAID1=y
379# CONFIG_MD_RAID10 is not set 510# CONFIG_MD_RAID10 is not set
380CONFIG_MD_RAID5=y 511# CONFIG_MD_RAID456 is not set
381# CONFIG_MD_RAID6 is not set
382# CONFIG_MD_MULTIPATH is not set 512# CONFIG_MD_MULTIPATH is not set
383# CONFIG_MD_FAULTY is not set 513# CONFIG_MD_FAULTY is not set
384CONFIG_BLK_DEV_DM=y 514CONFIG_BLK_DEV_DM=y
@@ -392,6 +522,9 @@ CONFIG_BLK_DEV_DM=y
392# Fusion MPT device support 522# Fusion MPT device support
393# 523#
394# CONFIG_FUSION is not set 524# CONFIG_FUSION is not set
525# CONFIG_FUSION_SPI is not set
526# CONFIG_FUSION_FC is not set
527# CONFIG_FUSION_SAS is not set
395 528
396# 529#
397# IEEE 1394 (FireWire) support 530# IEEE 1394 (FireWire) support
@@ -404,71 +537,8 @@ CONFIG_BLK_DEV_DM=y
404# CONFIG_I2O is not set 537# CONFIG_I2O is not set
405 538
406# 539#
407# Networking support 540# Network device support
408#
409CONFIG_NET=y
410
411#
412# Networking options
413#
414CONFIG_PACKET=y
415CONFIG_PACKET_MMAP=y
416# CONFIG_NETLINK_DEV is not set
417CONFIG_UNIX=y
418# CONFIG_NET_KEY is not set
419CONFIG_INET=y
420CONFIG_IP_MULTICAST=y
421# CONFIG_IP_ADVANCED_ROUTER is not set
422CONFIG_IP_PNP=y
423# CONFIG_IP_PNP_DHCP is not set
424CONFIG_IP_PNP_BOOTP=y
425# CONFIG_IP_PNP_RARP is not set
426# CONFIG_NET_IPIP is not set
427# CONFIG_NET_IPGRE is not set
428# CONFIG_IP_MROUTE is not set
429# CONFIG_ARPD is not set
430# CONFIG_SYN_COOKIES is not set
431# CONFIG_INET_AH is not set
432# CONFIG_INET_ESP is not set
433# CONFIG_INET_IPCOMP is not set
434# CONFIG_INET_TUNNEL is not set
435CONFIG_IP_TCPDIAG=y
436# CONFIG_IP_TCPDIAG_IPV6 is not set
437# CONFIG_IPV6 is not set
438# CONFIG_NETFILTER is not set
439
440#
441# SCTP Configuration (EXPERIMENTAL)
442#
443# CONFIG_IP_SCTP is not set
444# CONFIG_ATM is not set
445# CONFIG_BRIDGE is not set
446# CONFIG_VLAN_8021Q is not set
447# CONFIG_DECNET is not set
448# CONFIG_LLC2 is not set
449# CONFIG_IPX is not set
450# CONFIG_ATALK is not set
451# CONFIG_X25 is not set
452# CONFIG_LAPB is not set
453# CONFIG_NET_DIVERT is not set
454# CONFIG_ECONET is not set
455# CONFIG_WAN_ROUTER is not set
456
457#
458# QoS and/or fair queueing
459#
460# CONFIG_NET_SCHED is not set
461# CONFIG_NET_CLS_ROUTE is not set
462
463#
464# Network testing
465# 541#
466# CONFIG_NET_PKTGEN is not set
467# CONFIG_NETPOLL is not set
468# CONFIG_NET_POLL_CONTROLLER is not set
469# CONFIG_HAMRADIO is not set
470# CONFIG_IRDA is not set
471# CONFIG_BT is not set
472CONFIG_NETDEVICES=y 542CONFIG_NETDEVICES=y
473# CONFIG_DUMMY is not set 543# CONFIG_DUMMY is not set
474# CONFIG_BONDING is not set 544# CONFIG_BONDING is not set
@@ -481,14 +551,21 @@ CONFIG_NETDEVICES=y
481# CONFIG_ARCNET is not set 551# CONFIG_ARCNET is not set
482 552
483# 553#
554# PHY device support
555#
556# CONFIG_PHYLIB is not set
557
558#
484# Ethernet (10 or 100Mbit) 559# Ethernet (10 or 100Mbit)
485# 560#
486CONFIG_NET_ETHERNET=y 561CONFIG_NET_ETHERNET=y
487CONFIG_MII=y 562CONFIG_MII=y
488# CONFIG_HAPPYMEAL is not set 563# CONFIG_HAPPYMEAL is not set
489# CONFIG_SUNGEM is not set 564# CONFIG_SUNGEM is not set
565# CONFIG_CASSINI is not set
490# CONFIG_NET_VENDOR_3COM is not set 566# CONFIG_NET_VENDOR_3COM is not set
491# CONFIG_SMC91X is not set 567# CONFIG_SMC91X is not set
568# CONFIG_DM9000 is not set
492 569
493# 570#
494# Tulip family network device support 571# Tulip family network device support
@@ -526,16 +603,23 @@ CONFIG_E1000_NAPI=y
526# CONFIG_NS83820 is not set 603# CONFIG_NS83820 is not set
527# CONFIG_HAMACHI is not set 604# CONFIG_HAMACHI is not set
528# CONFIG_YELLOWFIN is not set 605# CONFIG_YELLOWFIN is not set
529# CONFIG_R8169 is not set 606CONFIG_R8169=y
607# CONFIG_R8169_NAPI is not set
608# CONFIG_SIS190 is not set
609# CONFIG_SKGE is not set
610# CONFIG_SKY2 is not set
530# CONFIG_SK98LIN is not set 611# CONFIG_SK98LIN is not set
531# CONFIG_VIA_VELOCITY is not set 612# CONFIG_VIA_VELOCITY is not set
532# CONFIG_TIGON3 is not set 613# CONFIG_TIGON3 is not set
614# CONFIG_BNX2 is not set
533 615
534# 616#
535# Ethernet (10000 Mbit) 617# Ethernet (10000 Mbit)
536# 618#
619# CONFIG_CHELSIO_T1 is not set
537# CONFIG_IXGB is not set 620# CONFIG_IXGB is not set
538# CONFIG_S2IO is not set 621# CONFIG_S2IO is not set
622# CONFIG_MYRI10GE is not set
539 623
540# 624#
541# Token Ring devices 625# Token Ring devices
@@ -558,6 +642,8 @@ CONFIG_E1000_NAPI=y
558# CONFIG_NET_FC is not set 642# CONFIG_NET_FC is not set
559# CONFIG_SHAPER is not set 643# CONFIG_SHAPER is not set
560# CONFIG_NETCONSOLE is not set 644# CONFIG_NETCONSOLE is not set
645# CONFIG_NETPOLL is not set
646# CONFIG_NET_POLL_CONTROLLER is not set
561 647
562# 648#
563# ISDN subsystem 649# ISDN subsystem
@@ -595,7 +681,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
595# 681#
596# CONFIG_SERIO is not set 682# CONFIG_SERIO is not set
597# CONFIG_GAMEPORT is not set 683# CONFIG_GAMEPORT is not set
598CONFIG_SOUND_GAMEPORT=y
599 684
600# 685#
601# Character devices 686# Character devices
@@ -603,6 +688,7 @@ CONFIG_SOUND_GAMEPORT=y
603CONFIG_VT=y 688CONFIG_VT=y
604CONFIG_VT_CONSOLE=y 689CONFIG_VT_CONSOLE=y
605CONFIG_HW_CONSOLE=y 690CONFIG_HW_CONSOLE=y
691# CONFIG_VT_HW_CONSOLE_BINDING is not set
606# CONFIG_SERIAL_NONSTANDARD is not set 692# CONFIG_SERIAL_NONSTANDARD is not set
607 693
608# 694#
@@ -610,7 +696,9 @@ CONFIG_HW_CONSOLE=y
610# 696#
611CONFIG_SERIAL_8250=y 697CONFIG_SERIAL_8250=y
612CONFIG_SERIAL_8250_CONSOLE=y 698CONFIG_SERIAL_8250_CONSOLE=y
699CONFIG_SERIAL_8250_PCI=y
613CONFIG_SERIAL_8250_NR_UARTS=4 700CONFIG_SERIAL_8250_NR_UARTS=4
701CONFIG_SERIAL_8250_RUNTIME_UARTS=4
614# CONFIG_SERIAL_8250_EXTENDED is not set 702# CONFIG_SERIAL_8250_EXTENDED is not set
615 703
616# 704#
@@ -618,6 +706,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
618# 706#
619CONFIG_SERIAL_CORE=y 707CONFIG_SERIAL_CORE=y
620CONFIG_SERIAL_CORE_CONSOLE=y 708CONFIG_SERIAL_CORE_CONSOLE=y
709# CONFIG_SERIAL_JSM is not set
621CONFIG_UNIX98_PTYS=y 710CONFIG_UNIX98_PTYS=y
622CONFIG_LEGACY_PTYS=y 711CONFIG_LEGACY_PTYS=y
623CONFIG_LEGACY_PTY_COUNT=256 712CONFIG_LEGACY_PTY_COUNT=256
@@ -631,8 +720,8 @@ CONFIG_LEGACY_PTY_COUNT=256
631# Watchdog Cards 720# Watchdog Cards
632# 721#
633# CONFIG_WATCHDOG is not set 722# CONFIG_WATCHDOG is not set
723CONFIG_HW_RANDOM=y
634# CONFIG_NVRAM is not set 724# CONFIG_NVRAM is not set
635# CONFIG_RTC is not set
636# CONFIG_DTLK is not set 725# CONFIG_DTLK is not set
637# CONFIG_R3964 is not set 726# CONFIG_R3964 is not set
638# CONFIG_APPLICOM is not set 727# CONFIG_APPLICOM is not set
@@ -647,6 +736,7 @@ CONFIG_LEGACY_PTY_COUNT=256
647# TPM devices 736# TPM devices
648# 737#
649# CONFIG_TCG_TPM is not set 738# CONFIG_TCG_TPM is not set
739# CONFIG_TELCLOCK is not set
650 740
651# 741#
652# I2C support 742# I2C support
@@ -671,14 +761,13 @@ CONFIG_I2C_CHARDEV=y
671# CONFIG_I2C_AMD8111 is not set 761# CONFIG_I2C_AMD8111 is not set
672# CONFIG_I2C_I801 is not set 762# CONFIG_I2C_I801 is not set
673# CONFIG_I2C_I810 is not set 763# CONFIG_I2C_I810 is not set
764# CONFIG_I2C_PIIX4 is not set
674CONFIG_I2C_IOP3XX=y 765CONFIG_I2C_IOP3XX=y
675# CONFIG_I2C_ISA is not set
676# CONFIG_I2C_NFORCE2 is not set 766# CONFIG_I2C_NFORCE2 is not set
767# CONFIG_I2C_OCORES is not set
677# CONFIG_I2C_PARPORT_LIGHT is not set 768# CONFIG_I2C_PARPORT_LIGHT is not set
678# CONFIG_I2C_PIIX4 is not set
679# CONFIG_I2C_PROSAVAGE is not set 769# CONFIG_I2C_PROSAVAGE is not set
680# CONFIG_I2C_SAVAGE4 is not set 770# CONFIG_I2C_SAVAGE4 is not set
681# CONFIG_SCx200_ACB is not set
682# CONFIG_I2C_SIS5595 is not set 771# CONFIG_I2C_SIS5595 is not set
683# CONFIG_I2C_SIS630 is not set 772# CONFIG_I2C_SIS630 is not set
684# CONFIG_I2C_SIS96X is not set 773# CONFIG_I2C_SIS96X is not set
@@ -689,15 +778,45 @@ CONFIG_I2C_IOP3XX=y
689# CONFIG_I2C_PCA_ISA is not set 778# CONFIG_I2C_PCA_ISA is not set
690 779
691# 780#
692# Hardware Sensors Chip support 781# Miscellaneous I2C Chip support
782#
783# CONFIG_SENSORS_DS1337 is not set
784# CONFIG_SENSORS_DS1374 is not set
785# CONFIG_SENSORS_EEPROM is not set
786# CONFIG_SENSORS_PCF8574 is not set
787# CONFIG_SENSORS_PCA9539 is not set
788# CONFIG_SENSORS_PCF8591 is not set
789# CONFIG_SENSORS_MAX6875 is not set
790# CONFIG_I2C_DEBUG_CORE is not set
791# CONFIG_I2C_DEBUG_ALGO is not set
792# CONFIG_I2C_DEBUG_BUS is not set
793# CONFIG_I2C_DEBUG_CHIP is not set
794
795#
796# SPI support
797#
798# CONFIG_SPI is not set
799# CONFIG_SPI_MASTER is not set
800
801#
802# Dallas's 1-wire bus
693# 803#
694# CONFIG_I2C_SENSOR is not set 804
805#
806# Hardware Monitoring support
807#
808CONFIG_HWMON=y
809# CONFIG_HWMON_VID is not set
810# CONFIG_SENSORS_ABITUGURU is not set
695# CONFIG_SENSORS_ADM1021 is not set 811# CONFIG_SENSORS_ADM1021 is not set
696# CONFIG_SENSORS_ADM1025 is not set 812# CONFIG_SENSORS_ADM1025 is not set
697# CONFIG_SENSORS_ADM1026 is not set 813# CONFIG_SENSORS_ADM1026 is not set
698# CONFIG_SENSORS_ADM1031 is not set 814# CONFIG_SENSORS_ADM1031 is not set
815# CONFIG_SENSORS_ADM9240 is not set
699# CONFIG_SENSORS_ASB100 is not set 816# CONFIG_SENSORS_ASB100 is not set
817# CONFIG_SENSORS_ATXP1 is not set
700# CONFIG_SENSORS_DS1621 is not set 818# CONFIG_SENSORS_DS1621 is not set
819# CONFIG_SENSORS_F71805F is not set
701# CONFIG_SENSORS_FSCHER is not set 820# CONFIG_SENSORS_FSCHER is not set
702# CONFIG_SENSORS_FSCPOS is not set 821# CONFIG_SENSORS_FSCPOS is not set
703# CONFIG_SENSORS_GL518SM is not set 822# CONFIG_SENSORS_GL518SM is not set
@@ -712,36 +831,45 @@ CONFIG_I2C_IOP3XX=y
712# CONFIG_SENSORS_LM85 is not set 831# CONFIG_SENSORS_LM85 is not set
713# CONFIG_SENSORS_LM87 is not set 832# CONFIG_SENSORS_LM87 is not set
714# CONFIG_SENSORS_LM90 is not set 833# CONFIG_SENSORS_LM90 is not set
834# CONFIG_SENSORS_LM92 is not set
715# CONFIG_SENSORS_MAX1619 is not set 835# CONFIG_SENSORS_MAX1619 is not set
716# CONFIG_SENSORS_PC87360 is not set 836# CONFIG_SENSORS_PC87360 is not set
717# CONFIG_SENSORS_SMSC47B397 is not set
718# CONFIG_SENSORS_SIS5595 is not set 837# CONFIG_SENSORS_SIS5595 is not set
719# CONFIG_SENSORS_SMSC47M1 is not set 838# CONFIG_SENSORS_SMSC47M1 is not set
839# CONFIG_SENSORS_SMSC47M192 is not set
840# CONFIG_SENSORS_SMSC47B397 is not set
720# CONFIG_SENSORS_VIA686A is not set 841# CONFIG_SENSORS_VIA686A is not set
842# CONFIG_SENSORS_VT8231 is not set
721# CONFIG_SENSORS_W83781D is not set 843# CONFIG_SENSORS_W83781D is not set
844# CONFIG_SENSORS_W83791D is not set
845# CONFIG_SENSORS_W83792D is not set
722# CONFIG_SENSORS_W83L785TS is not set 846# CONFIG_SENSORS_W83L785TS is not set
723# CONFIG_SENSORS_W83627HF is not set 847# CONFIG_SENSORS_W83627HF is not set
848# CONFIG_SENSORS_W83627EHF is not set
849# CONFIG_HWMON_DEBUG_CHIP is not set
724 850
725# 851#
726# Other I2C Chip support 852# Misc devices
727# 853#
728# CONFIG_SENSORS_EEPROM is not set
729# CONFIG_SENSORS_PCF8574 is not set
730# CONFIG_SENSORS_PCF8591 is not set
731# CONFIG_SENSORS_RTC8564 is not set
732# CONFIG_I2C_DEBUG_CORE is not set
733# CONFIG_I2C_DEBUG_ALGO is not set
734# CONFIG_I2C_DEBUG_BUS is not set
735# CONFIG_I2C_DEBUG_CHIP is not set
736 854
737# 855#
738# Misc devices 856# LED devices
857#
858# CONFIG_NEW_LEDS is not set
859
860#
861# LED drivers
862#
863
864#
865# LED Triggers
739# 866#
740 867
741# 868#
742# Multimedia devices 869# Multimedia devices
743# 870#
744# CONFIG_VIDEO_DEV is not set 871# CONFIG_VIDEO_DEV is not set
872CONFIG_VIDEO_V4L2=y
745 873
746# 874#
747# Digital Video Broadcasting Devices 875# Digital Video Broadcasting Devices
@@ -751,6 +879,7 @@ CONFIG_I2C_IOP3XX=y
751# 879#
752# Graphics support 880# Graphics support
753# 881#
882CONFIG_FIRMWARE_EDID=y
754# CONFIG_FB is not set 883# CONFIG_FB is not set
755 884
756# 885#
@@ -758,6 +887,7 @@ CONFIG_I2C_IOP3XX=y
758# 887#
759# CONFIG_VGA_CONSOLE is not set 888# CONFIG_VGA_CONSOLE is not set
760CONFIG_DUMMY_CONSOLE=y 889CONFIG_DUMMY_CONSOLE=y
890# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
761 891
762# 892#
763# Sound 893# Sound
@@ -769,7 +899,125 @@ CONFIG_DUMMY_CONSOLE=y
769# 899#
770CONFIG_USB_ARCH_HAS_HCD=y 900CONFIG_USB_ARCH_HAS_HCD=y
771CONFIG_USB_ARCH_HAS_OHCI=y 901CONFIG_USB_ARCH_HAS_OHCI=y
772# CONFIG_USB is not set 902CONFIG_USB_ARCH_HAS_EHCI=y
903CONFIG_USB=y
904# CONFIG_USB_DEBUG is not set
905
906#
907# Miscellaneous USB options
908#
909# CONFIG_USB_DEVICEFS is not set
910# CONFIG_USB_BANDWIDTH is not set
911# CONFIG_USB_DYNAMIC_MINORS is not set
912# CONFIG_USB_OTG is not set
913
914#
915# USB Host Controller Drivers
916#
917CONFIG_USB_EHCI_HCD=y
918CONFIG_USB_EHCI_SPLIT_ISO=y
919CONFIG_USB_EHCI_ROOT_HUB_TT=y
920CONFIG_USB_EHCI_TT_NEWSCHED=y
921# CONFIG_USB_ISP116X_HCD is not set
922# CONFIG_USB_OHCI_HCD is not set
923CONFIG_USB_UHCI_HCD=y
924# CONFIG_USB_SL811_HCD is not set
925
926#
927# USB Device Class drivers
928#
929# CONFIG_USB_ACM is not set
930# CONFIG_USB_PRINTER is not set
931
932#
933# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
934#
935
936#
937# may also be needed; see USB_STORAGE Help for more information
938#
939CONFIG_USB_STORAGE=y
940# CONFIG_USB_STORAGE_DEBUG is not set
941# CONFIG_USB_STORAGE_DATAFAB is not set
942# CONFIG_USB_STORAGE_FREECOM is not set
943# CONFIG_USB_STORAGE_DPCM is not set
944# CONFIG_USB_STORAGE_USBAT is not set
945# CONFIG_USB_STORAGE_SDDR09 is not set
946# CONFIG_USB_STORAGE_SDDR55 is not set
947# CONFIG_USB_STORAGE_JUMPSHOT is not set
948# CONFIG_USB_STORAGE_ALAUDA is not set
949# CONFIG_USB_LIBUSUAL is not set
950
951#
952# USB Input Devices
953#
954# CONFIG_USB_HID is not set
955
956#
957# USB HID Boot Protocol drivers
958#
959# CONFIG_USB_KBD is not set
960# CONFIG_USB_MOUSE is not set
961# CONFIG_USB_AIPTEK is not set
962# CONFIG_USB_WACOM is not set
963# CONFIG_USB_ACECAD is not set
964# CONFIG_USB_KBTAB is not set
965# CONFIG_USB_POWERMATE is not set
966# CONFIG_USB_TOUCHSCREEN is not set
967# CONFIG_USB_YEALINK is not set
968# CONFIG_USB_XPAD is not set
969# CONFIG_USB_ATI_REMOTE is not set
970# CONFIG_USB_ATI_REMOTE2 is not set
971# CONFIG_USB_KEYSPAN_REMOTE is not set
972# CONFIG_USB_APPLETOUCH is not set
973
974#
975# USB Imaging devices
976#
977# CONFIG_USB_MDC800 is not set
978# CONFIG_USB_MICROTEK is not set
979
980#
981# USB Network Adapters
982#
983# CONFIG_USB_CATC is not set
984# CONFIG_USB_KAWETH is not set
985# CONFIG_USB_PEGASUS is not set
986# CONFIG_USB_RTL8150 is not set
987# CONFIG_USB_USBNET is not set
988CONFIG_USB_MON=y
989
990#
991# USB port drivers
992#
993
994#
995# USB Serial Converter support
996#
997# CONFIG_USB_SERIAL is not set
998
999#
1000# USB Miscellaneous drivers
1001#
1002# CONFIG_USB_EMI62 is not set
1003# CONFIG_USB_EMI26 is not set
1004# CONFIG_USB_AUERSWALD is not set
1005# CONFIG_USB_RIO500 is not set
1006# CONFIG_USB_LEGOTOWER is not set
1007# CONFIG_USB_LCD is not set
1008# CONFIG_USB_LED is not set
1009# CONFIG_USB_CYPRESS_CY7C63 is not set
1010# CONFIG_USB_CYTHERM is not set
1011# CONFIG_USB_PHIDGETKIT is not set
1012# CONFIG_USB_PHIDGETSERVO is not set
1013# CONFIG_USB_IDMOUSE is not set
1014# CONFIG_USB_APPLEDISPLAY is not set
1015# CONFIG_USB_SISUSBVGA is not set
1016# CONFIG_USB_LD is not set
1017
1018#
1019# USB DSL modem support
1020#
773 1021
774# 1022#
775# USB Gadget Support 1023# USB Gadget Support
@@ -782,10 +1030,17 @@ CONFIG_USB_ARCH_HAS_OHCI=y
782# CONFIG_MMC is not set 1030# CONFIG_MMC is not set
783 1031
784# 1032#
1033# Real Time Clock
1034#
1035CONFIG_RTC_LIB=y
1036# CONFIG_RTC_CLASS is not set
1037
1038#
785# File systems 1039# File systems
786# 1040#
787CONFIG_EXT2_FS=y 1041CONFIG_EXT2_FS=y
788# CONFIG_EXT2_FS_XATTR is not set 1042# CONFIG_EXT2_FS_XATTR is not set
1043# CONFIG_EXT2_FS_XIP is not set
789CONFIG_EXT3_FS=y 1044CONFIG_EXT3_FS=y
790CONFIG_EXT3_FS_XATTR=y 1045CONFIG_EXT3_FS_XATTR=y
791# CONFIG_EXT3_FS_POSIX_ACL is not set 1046# CONFIG_EXT3_FS_POSIX_ACL is not set
@@ -795,22 +1050,22 @@ CONFIG_JBD=y
795CONFIG_FS_MBCACHE=y 1050CONFIG_FS_MBCACHE=y
796# CONFIG_REISERFS_FS is not set 1051# CONFIG_REISERFS_FS is not set
797# CONFIG_JFS_FS is not set 1052# CONFIG_JFS_FS is not set
798 1053# CONFIG_FS_POSIX_ACL is not set
799#
800# XFS support
801#
802CONFIG_XFS_FS=y 1054CONFIG_XFS_FS=y
803CONFIG_XFS_EXPORT=y
804# CONFIG_XFS_RT is not set
805# CONFIG_XFS_QUOTA is not set 1055# CONFIG_XFS_QUOTA is not set
806CONFIG_XFS_SECURITY=y 1056CONFIG_XFS_SECURITY=y
807CONFIG_XFS_POSIX_ACL=y 1057CONFIG_XFS_POSIX_ACL=y
1058# CONFIG_XFS_RT is not set
1059# CONFIG_OCFS2_FS is not set
808# CONFIG_MINIX_FS is not set 1060# CONFIG_MINIX_FS is not set
809# CONFIG_ROMFS_FS is not set 1061# CONFIG_ROMFS_FS is not set
1062CONFIG_INOTIFY=y
1063CONFIG_INOTIFY_USER=y
810# CONFIG_QUOTA is not set 1064# CONFIG_QUOTA is not set
811CONFIG_DNOTIFY=y 1065CONFIG_DNOTIFY=y
812# CONFIG_AUTOFS_FS is not set 1066# CONFIG_AUTOFS_FS is not set
813# CONFIG_AUTOFS4_FS is not set 1067# CONFIG_AUTOFS4_FS is not set
1068# CONFIG_FUSE_FS is not set
814 1069
815# 1070#
816# CD-ROM/DVD Filesystems 1071# CD-ROM/DVD Filesystems
@@ -830,12 +1085,10 @@ CONFIG_DNOTIFY=y
830# 1085#
831CONFIG_PROC_FS=y 1086CONFIG_PROC_FS=y
832CONFIG_SYSFS=y 1087CONFIG_SYSFS=y
833# CONFIG_DEVFS_FS is not set
834# CONFIG_DEVPTS_FS_XATTR is not set
835CONFIG_TMPFS=y 1088CONFIG_TMPFS=y
836# CONFIG_TMPFS_XATTR is not set
837# CONFIG_HUGETLB_PAGE is not set 1089# CONFIG_HUGETLB_PAGE is not set
838CONFIG_RAMFS=y 1090CONFIG_RAMFS=y
1091# CONFIG_CONFIGFS_FS is not set
839 1092
840# 1093#
841# Miscellaneous filesystems 1094# Miscellaneous filesystems
@@ -850,8 +1103,9 @@ CONFIG_RAMFS=y
850# CONFIG_JFFS_FS is not set 1103# CONFIG_JFFS_FS is not set
851CONFIG_JFFS2_FS=y 1104CONFIG_JFFS2_FS=y
852CONFIG_JFFS2_FS_DEBUG=0 1105CONFIG_JFFS2_FS_DEBUG=0
853# CONFIG_JFFS2_FS_NAND is not set 1106CONFIG_JFFS2_FS_WRITEBUFFER=y
854# CONFIG_JFFS2_FS_NOR_ECC is not set 1107# CONFIG_JFFS2_SUMMARY is not set
1108# CONFIG_JFFS2_FS_XATTR is not set
855# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set 1109# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
856CONFIG_JFFS2_ZLIB=y 1110CONFIG_JFFS2_ZLIB=y
857CONFIG_JFFS2_RTIME=y 1111CONFIG_JFFS2_RTIME=y
@@ -868,16 +1122,19 @@ CONFIG_JFFS2_RTIME=y
868# 1122#
869CONFIG_NFS_FS=y 1123CONFIG_NFS_FS=y
870CONFIG_NFS_V3=y 1124CONFIG_NFS_V3=y
1125# CONFIG_NFS_V3_ACL is not set
871# CONFIG_NFS_V4 is not set 1126# CONFIG_NFS_V4 is not set
872# CONFIG_NFS_DIRECTIO is not set 1127# CONFIG_NFS_DIRECTIO is not set
873CONFIG_NFSD=y 1128CONFIG_NFSD=y
874CONFIG_NFSD_V3=y 1129CONFIG_NFSD_V3=y
1130# CONFIG_NFSD_V3_ACL is not set
875# CONFIG_NFSD_V4 is not set 1131# CONFIG_NFSD_V4 is not set
876# CONFIG_NFSD_TCP is not set 1132# CONFIG_NFSD_TCP is not set
877CONFIG_ROOT_NFS=y 1133CONFIG_ROOT_NFS=y
878CONFIG_LOCKD=y 1134CONFIG_LOCKD=y
879CONFIG_LOCKD_V4=y 1135CONFIG_LOCKD_V4=y
880CONFIG_EXPORTFS=y 1136CONFIG_EXPORTFS=y
1137CONFIG_NFS_COMMON=y
881CONFIG_SUNRPC=y 1138CONFIG_SUNRPC=y
882# CONFIG_RPCSEC_GSS_KRB5 is not set 1139# CONFIG_RPCSEC_GSS_KRB5 is not set
883# CONFIG_RPCSEC_GSS_SPKM3 is not set 1140# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -886,6 +1143,7 @@ CONFIG_SUNRPC=y
886# CONFIG_NCP_FS is not set 1143# CONFIG_NCP_FS is not set
887# CONFIG_CODA_FS is not set 1144# CONFIG_CODA_FS is not set
888# CONFIG_AFS_FS is not set 1145# CONFIG_AFS_FS is not set
1146# CONFIG_9P_FS is not set
889 1147
890# 1148#
891# Partition Types 1149# Partition Types
@@ -905,6 +1163,7 @@ CONFIG_MSDOS_PARTITION=y
905# CONFIG_SGI_PARTITION is not set 1163# CONFIG_SGI_PARTITION is not set
906# CONFIG_ULTRIX_PARTITION is not set 1164# CONFIG_ULTRIX_PARTITION is not set
907# CONFIG_SUN_PARTITION is not set 1165# CONFIG_SUN_PARTITION is not set
1166# CONFIG_KARMA_PARTITION is not set
908# CONFIG_EFI_PARTITION is not set 1167# CONFIG_EFI_PARTITION is not set
909 1168
910# 1169#
@@ -921,11 +1180,34 @@ CONFIG_MSDOS_PARTITION=y
921# Kernel hacking 1180# Kernel hacking
922# 1181#
923# CONFIG_PRINTK_TIME is not set 1182# CONFIG_PRINTK_TIME is not set
924# CONFIG_DEBUG_KERNEL is not set 1183CONFIG_MAGIC_SYSRQ=y
1184# CONFIG_UNUSED_SYMBOLS is not set
1185CONFIG_DEBUG_KERNEL=y
925CONFIG_LOG_BUF_SHIFT=14 1186CONFIG_LOG_BUF_SHIFT=14
1187CONFIG_DETECT_SOFTLOCKUP=y
1188# CONFIG_SCHEDSTATS is not set
1189# CONFIG_DEBUG_SLAB is not set
1190# CONFIG_DEBUG_RT_MUTEXES is not set
1191# CONFIG_RT_MUTEX_TESTER is not set
1192# CONFIG_DEBUG_SPINLOCK is not set
1193# CONFIG_DEBUG_MUTEXES is not set
1194# CONFIG_DEBUG_RWSEMS is not set
1195# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1196# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1197# CONFIG_DEBUG_KOBJECT is not set
926CONFIG_DEBUG_BUGVERBOSE=y 1198CONFIG_DEBUG_BUGVERBOSE=y
1199# CONFIG_DEBUG_INFO is not set
1200# CONFIG_DEBUG_FS is not set
1201# CONFIG_DEBUG_VM is not set
927CONFIG_FRAME_POINTER=y 1202CONFIG_FRAME_POINTER=y
1203# CONFIG_UNWIND_INFO is not set
1204# CONFIG_FORCED_INLINING is not set
1205# CONFIG_RCU_TORTURE_TEST is not set
928CONFIG_DEBUG_USER=y 1206CONFIG_DEBUG_USER=y
1207# CONFIG_DEBUG_WAITQ is not set
1208# CONFIG_DEBUG_ERRORS is not set
1209CONFIG_DEBUG_LL=y
1210# CONFIG_DEBUG_ICEDCC is not set
929 1211
930# 1212#
931# Security options 1213# Security options
@@ -946,7 +1228,9 @@ CONFIG_DEBUG_USER=y
946# Library routines 1228# Library routines
947# 1229#
948# CONFIG_CRC_CCITT is not set 1230# CONFIG_CRC_CCITT is not set
1231# CONFIG_CRC16 is not set
949CONFIG_CRC32=y 1232CONFIG_CRC32=y
950# CONFIG_LIBCRC32C is not set 1233# CONFIG_LIBCRC32C is not set
951CONFIG_ZLIB_INFLATE=y 1234CONFIG_ZLIB_INFLATE=y
952CONFIG_ZLIB_DEFLATE=y 1235CONFIG_ZLIB_DEFLATE=y
1236CONFIG_PLIST=y
diff --git a/arch/arm/configs/iq80332_defconfig b/arch/arm/configs/iop33x_defconfig
index 11959b705d82..2a8fc153969d 100644
--- a/arch/arm/configs/iq80332_defconfig
+++ b/arch/arm/configs/iop33x_defconfig
@@ -1,50 +1,63 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc1-bk2 3# Linux kernel version: 2.6.18-rc7
4# Sun Mar 27 17:33:39 2005 4# Tue Sep 19 00:30:42 2006
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_MMU=y 7CONFIG_MMU=y
8CONFIG_UID16=y 8CONFIG_GENERIC_HARDIRQS=y
9CONFIG_TRACE_IRQFLAGS_SUPPORT=y
10CONFIG_HARDIRQS_SW_RESEND=y
11CONFIG_GENERIC_IRQ_PROBE=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 12CONFIG_RWSEM_GENERIC_SPINLOCK=y
13CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 14CONFIG_GENERIC_CALIBRATE_DELAY=y
11CONFIG_GENERIC_IOMAP=y 15CONFIG_VECTORS_BASE=0xffff0000
16CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
12 17
13# 18#
14# Code maturity level options 19# Code maturity level options
15# 20#
16CONFIG_EXPERIMENTAL=y 21CONFIG_EXPERIMENTAL=y
17CONFIG_CLEAN_COMPILE=y
18CONFIG_BROKEN_ON_SMP=y 22CONFIG_BROKEN_ON_SMP=y
23CONFIG_INIT_ENV_ARG_LIMIT=32
19 24
20# 25#
21# General setup 26# General setup
22# 27#
23CONFIG_LOCALVERSION="" 28CONFIG_LOCALVERSION=""
29CONFIG_LOCALVERSION_AUTO=y
24CONFIG_SWAP=y 30CONFIG_SWAP=y
25CONFIG_SYSVIPC=y 31CONFIG_SYSVIPC=y
26# CONFIG_POSIX_MQUEUE is not set 32# CONFIG_POSIX_MQUEUE is not set
27CONFIG_BSD_PROCESS_ACCT=y 33CONFIG_BSD_PROCESS_ACCT=y
28# CONFIG_BSD_PROCESS_ACCT_V3 is not set 34# CONFIG_BSD_PROCESS_ACCT_V3 is not set
35# CONFIG_TASKSTATS is not set
29CONFIG_SYSCTL=y 36CONFIG_SYSCTL=y
30# CONFIG_AUDIT is not set 37# CONFIG_AUDIT is not set
31# CONFIG_HOTPLUG is not set
32CONFIG_KOBJECT_UEVENT=y
33# CONFIG_IKCONFIG is not set 38# CONFIG_IKCONFIG is not set
39# CONFIG_RELAY is not set
40CONFIG_INITRAMFS_SOURCE=""
41CONFIG_UID16=y
42CONFIG_CC_OPTIMIZE_FOR_SIZE=y
34# CONFIG_EMBEDDED is not set 43# CONFIG_EMBEDDED is not set
35CONFIG_KALLSYMS=y 44CONFIG_KALLSYMS=y
45CONFIG_KALLSYMS_ALL=y
36# CONFIG_KALLSYMS_EXTRA_PASS is not set 46# CONFIG_KALLSYMS_EXTRA_PASS is not set
47CONFIG_HOTPLUG=y
48CONFIG_PRINTK=y
49CONFIG_BUG=y
50CONFIG_ELF_CORE=y
37CONFIG_BASE_FULL=y 51CONFIG_BASE_FULL=y
52CONFIG_RT_MUTEXES=y
38CONFIG_FUTEX=y 53CONFIG_FUTEX=y
39CONFIG_EPOLL=y 54CONFIG_EPOLL=y
40CONFIG_CC_OPTIMIZE_FOR_SIZE=y
41CONFIG_SHMEM=y 55CONFIG_SHMEM=y
42CONFIG_CC_ALIGN_FUNCTIONS=0 56CONFIG_SLAB=y
43CONFIG_CC_ALIGN_LABELS=0 57CONFIG_VM_EVENT_COUNTERS=y
44CONFIG_CC_ALIGN_LOOPS=0
45CONFIG_CC_ALIGN_JUMPS=0
46# CONFIG_TINY_SHMEM is not set 58# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0 59CONFIG_BASE_SMALL=0
60# CONFIG_SLOB is not set
48 61
49# 62#
50# Loadable module support 63# Loadable module support
@@ -52,24 +65,52 @@ CONFIG_BASE_SMALL=0
52CONFIG_MODULES=y 65CONFIG_MODULES=y
53CONFIG_MODULE_UNLOAD=y 66CONFIG_MODULE_UNLOAD=y
54# CONFIG_MODULE_FORCE_UNLOAD is not set 67# CONFIG_MODULE_FORCE_UNLOAD is not set
55CONFIG_OBSOLETE_MODPARM=y
56# CONFIG_MODVERSIONS is not set 68# CONFIG_MODVERSIONS is not set
57# CONFIG_MODULE_SRCVERSION_ALL is not set 69# CONFIG_MODULE_SRCVERSION_ALL is not set
58CONFIG_KMOD=y 70CONFIG_KMOD=y
59 71
60# 72#
73# Block layer
74#
75# CONFIG_BLK_DEV_IO_TRACE is not set
76
77#
78# IO Schedulers
79#
80CONFIG_IOSCHED_NOOP=y
81CONFIG_IOSCHED_AS=y
82CONFIG_IOSCHED_DEADLINE=y
83CONFIG_IOSCHED_CFQ=y
84# CONFIG_DEFAULT_AS is not set
85# CONFIG_DEFAULT_DEADLINE is not set
86CONFIG_DEFAULT_CFQ=y
87# CONFIG_DEFAULT_NOOP is not set
88CONFIG_DEFAULT_IOSCHED="cfq"
89
90#
61# System Type 91# System Type
62# 92#
93# CONFIG_ARCH_AAEC2000 is not set
94# CONFIG_ARCH_INTEGRATOR is not set
95# CONFIG_ARCH_REALVIEW is not set
96# CONFIG_ARCH_VERSATILE is not set
97# CONFIG_ARCH_AT91 is not set
63# CONFIG_ARCH_CLPS7500 is not set 98# CONFIG_ARCH_CLPS7500 is not set
64# CONFIG_ARCH_CLPS711X is not set 99# CONFIG_ARCH_CLPS711X is not set
65# CONFIG_ARCH_CO285 is not set 100# CONFIG_ARCH_CO285 is not set
66# CONFIG_ARCH_EBSA110 is not set 101# CONFIG_ARCH_EBSA110 is not set
102# CONFIG_ARCH_EP93XX is not set
67# CONFIG_ARCH_FOOTBRIDGE is not set 103# CONFIG_ARCH_FOOTBRIDGE is not set
68# CONFIG_ARCH_INTEGRATOR is not set 104# CONFIG_ARCH_NETX is not set
69CONFIG_ARCH_IOP3XX=y 105# CONFIG_ARCH_H720X is not set
106# CONFIG_ARCH_IMX is not set
107# CONFIG_ARCH_IOP32X is not set
108CONFIG_ARCH_IOP33X=y
70# CONFIG_ARCH_IXP4XX is not set 109# CONFIG_ARCH_IXP4XX is not set
71# CONFIG_ARCH_IXP2000 is not set 110# CONFIG_ARCH_IXP2000 is not set
111# CONFIG_ARCH_IXP23XX is not set
72# CONFIG_ARCH_L7200 is not set 112# CONFIG_ARCH_L7200 is not set
113# CONFIG_ARCH_PNX4008 is not set
73# CONFIG_ARCH_PXA is not set 114# CONFIG_ARCH_PXA is not set
74# CONFIG_ARCH_RPC is not set 115# CONFIG_ARCH_RPC is not set
75# CONFIG_ARCH_SA1100 is not set 116# CONFIG_ARCH_SA1100 is not set
@@ -77,28 +118,17 @@ CONFIG_ARCH_IOP3XX=y
77# CONFIG_ARCH_SHARK is not set 118# CONFIG_ARCH_SHARK is not set
78# CONFIG_ARCH_LH7A40X is not set 119# CONFIG_ARCH_LH7A40X is not set
79# CONFIG_ARCH_OMAP is not set 120# CONFIG_ARCH_OMAP is not set
80# CONFIG_ARCH_VERSATILE is not set
81# CONFIG_ARCH_IMX is not set
82# CONFIG_ARCH_H720X is not set
83 121
84# 122#
85# IOP3xx Implementation Options 123# IOP33x Implementation Options
86# 124#
87 125
88# 126#
89# IOP3xx Platform Types 127# IOP33x Platform Types
90# 128#
91# CONFIG_ARCH_IQ80321 is not set 129CONFIG_ARCH_IQ80331=y
92# CONFIG_ARCH_IQ31244 is not set
93# CONFIG_ARCH_IQ80331 is not set
94CONFIG_MACH_IQ80332=y 130CONFIG_MACH_IQ80332=y
95# CONFIG_ARCH_EP80219 is not set 131CONFIG_PLAT_IOP=y
96CONFIG_ARCH_IOP331=y
97
98#
99# IOP3xx Chipset Features
100#
101# CONFIG_IOP331_STEPD is not set
102 132
103# 133#
104# Processor Type 134# Processor Type
@@ -109,7 +139,6 @@ CONFIG_CPU_32v5=y
109CONFIG_CPU_ABRT_EV5T=y 139CONFIG_CPU_ABRT_EV5T=y
110CONFIG_CPU_CACHE_VIVT=y 140CONFIG_CPU_CACHE_VIVT=y
111CONFIG_CPU_TLB_V4WBI=y 141CONFIG_CPU_TLB_V4WBI=y
112CONFIG_CPU_MINICACHE=y
113 142
114# 143#
115# Processor Features 144# Processor Features
@@ -121,8 +150,7 @@ CONFIG_XSCALE_PMU=y
121# Bus support 150# Bus support
122# 151#
123CONFIG_PCI=y 152CONFIG_PCI=y
124# CONFIG_PCI_LEGACY_PROC is not set 153# CONFIG_PCI_DEBUG is not set
125CONFIG_PCI_NAMES=y
126 154
127# 155#
128# PCCARD (PCMCIA/CardBus) support 156# PCCARD (PCMCIA/CardBus) support
@@ -133,6 +161,19 @@ CONFIG_PCI_NAMES=y
133# Kernel Features 161# Kernel Features
134# 162#
135# CONFIG_PREEMPT is not set 163# CONFIG_PREEMPT is not set
164# CONFIG_NO_IDLE_HZ is not set
165CONFIG_HZ=100
166# CONFIG_AEABI is not set
167# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
168CONFIG_SELECT_MEMORY_MODEL=y
169CONFIG_FLATMEM_MANUAL=y
170# CONFIG_DISCONTIGMEM_MANUAL is not set
171# CONFIG_SPARSEMEM_MANUAL is not set
172CONFIG_FLATMEM=y
173CONFIG_FLAT_NODE_MEM_MAP=y
174# CONFIG_SPARSEMEM_STATIC is not set
175CONFIG_SPLIT_PTLOCK_CPUS=4096
176# CONFIG_RESOURCES_64BIT is not set
136CONFIG_ALIGNMENT_TRAP=y 177CONFIG_ALIGNMENT_TRAP=y
137 178
138# 179#
@@ -140,7 +181,7 @@ CONFIG_ALIGNMENT_TRAP=y
140# 181#
141CONFIG_ZBOOT_ROM_TEXT=0x0 182CONFIG_ZBOOT_ROM_TEXT=0x0
142CONFIG_ZBOOT_ROM_BSS=0x0 183CONFIG_ZBOOT_ROM_BSS=0x0
143CONFIG_CMDLINE="ip=boot root=nfs console=ttyS0,115200" 184CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp"
144# CONFIG_XIP_KERNEL is not set 185# CONFIG_XIP_KERNEL is not set
145 186
146# 187#
@@ -166,6 +207,93 @@ CONFIG_BINFMT_AOUT=y
166# Power management options 207# Power management options
167# 208#
168# CONFIG_PM is not set 209# CONFIG_PM is not set
210# CONFIG_APM is not set
211
212#
213# Networking
214#
215CONFIG_NET=y
216
217#
218# Networking options
219#
220# CONFIG_NETDEBUG is not set
221CONFIG_PACKET=y
222CONFIG_PACKET_MMAP=y
223CONFIG_UNIX=y
224CONFIG_XFRM=y
225# CONFIG_XFRM_USER is not set
226# CONFIG_NET_KEY is not set
227CONFIG_INET=y
228CONFIG_IP_MULTICAST=y
229# CONFIG_IP_ADVANCED_ROUTER is not set
230CONFIG_IP_FIB_HASH=y
231CONFIG_IP_PNP=y
232# CONFIG_IP_PNP_DHCP is not set
233CONFIG_IP_PNP_BOOTP=y
234# CONFIG_IP_PNP_RARP is not set
235# CONFIG_NET_IPIP is not set
236# CONFIG_NET_IPGRE is not set
237# CONFIG_IP_MROUTE is not set
238# CONFIG_ARPD is not set
239# CONFIG_SYN_COOKIES is not set
240# CONFIG_INET_AH is not set
241# CONFIG_INET_ESP is not set
242# CONFIG_INET_IPCOMP is not set
243# CONFIG_INET_XFRM_TUNNEL is not set
244# CONFIG_INET_TUNNEL is not set
245CONFIG_INET_XFRM_MODE_TRANSPORT=y
246CONFIG_INET_XFRM_MODE_TUNNEL=y
247CONFIG_INET_DIAG=y
248CONFIG_INET_TCP_DIAG=y
249# CONFIG_TCP_CONG_ADVANCED is not set
250CONFIG_TCP_CONG_BIC=y
251# CONFIG_IPV6 is not set
252# CONFIG_INET6_XFRM_TUNNEL is not set
253# CONFIG_INET6_TUNNEL is not set
254# CONFIG_NETWORK_SECMARK is not set
255# CONFIG_NETFILTER is not set
256
257#
258# DCCP Configuration (EXPERIMENTAL)
259#
260# CONFIG_IP_DCCP is not set
261
262#
263# SCTP Configuration (EXPERIMENTAL)
264#
265# CONFIG_IP_SCTP is not set
266
267#
268# TIPC Configuration (EXPERIMENTAL)
269#
270# CONFIG_TIPC is not set
271# CONFIG_ATM is not set
272# CONFIG_BRIDGE is not set
273# CONFIG_VLAN_8021Q is not set
274# CONFIG_DECNET is not set
275# CONFIG_LLC2 is not set
276# CONFIG_IPX is not set
277# CONFIG_ATALK is not set
278# CONFIG_X25 is not set
279# CONFIG_LAPB is not set
280# CONFIG_NET_DIVERT is not set
281# CONFIG_ECONET is not set
282# CONFIG_WAN_ROUTER is not set
283
284#
285# QoS and/or fair queueing
286#
287# CONFIG_NET_SCHED is not set
288
289#
290# Network testing
291#
292# CONFIG_NET_PKTGEN is not set
293# CONFIG_HAMRADIO is not set
294# CONFIG_IRDA is not set
295# CONFIG_BT is not set
296# CONFIG_IEEE80211 is not set
169 297
170# 298#
171# Device Drivers 299# Device Drivers
@@ -177,6 +305,13 @@ CONFIG_BINFMT_AOUT=y
177CONFIG_STANDALONE=y 305CONFIG_STANDALONE=y
178CONFIG_PREVENT_FIRMWARE_BUILD=y 306CONFIG_PREVENT_FIRMWARE_BUILD=y
179# CONFIG_FW_LOADER is not set 307# CONFIG_FW_LOADER is not set
308# CONFIG_DEBUG_DRIVER is not set
309# CONFIG_SYS_HYPERVISOR is not set
310
311#
312# Connector - unified userspace <-> kernelspace linker
313#
314# CONFIG_CONNECTOR is not set
180 315
181# 316#
182# Memory Technology Devices (MTD) 317# Memory Technology Devices (MTD)
@@ -200,6 +335,7 @@ CONFIG_MTD_BLOCK=y
200# CONFIG_FTL is not set 335# CONFIG_FTL is not set
201# CONFIG_NFTL is not set 336# CONFIG_NFTL is not set
202# CONFIG_INFTL is not set 337# CONFIG_INFTL is not set
338# CONFIG_RFD_FTL is not set
203 339
204# 340#
205# RAM/ROM/Flash chip drivers 341# RAM/ROM/Flash chip drivers
@@ -222,6 +358,7 @@ CONFIG_MTD_CFI_I1=y
222CONFIG_MTD_CFI_I2=y 358CONFIG_MTD_CFI_I2=y
223# CONFIG_MTD_CFI_I4 is not set 359# CONFIG_MTD_CFI_I4 is not set
224# CONFIG_MTD_CFI_I8 is not set 360# CONFIG_MTD_CFI_I8 is not set
361# CONFIG_MTD_OTP is not set
225CONFIG_MTD_CFI_INTELEXT=y 362CONFIG_MTD_CFI_INTELEXT=y
226# CONFIG_MTD_CFI_AMDSTD is not set 363# CONFIG_MTD_CFI_AMDSTD is not set
227# CONFIG_MTD_CFI_STAA is not set 364# CONFIG_MTD_CFI_STAA is not set
@@ -229,18 +366,18 @@ CONFIG_MTD_CFI_UTIL=y
229# CONFIG_MTD_RAM is not set 366# CONFIG_MTD_RAM is not set
230# CONFIG_MTD_ROM is not set 367# CONFIG_MTD_ROM is not set
231# CONFIG_MTD_ABSENT is not set 368# CONFIG_MTD_ABSENT is not set
232# CONFIG_MTD_XIP is not set 369# CONFIG_MTD_OBSOLETE_CHIPS is not set
233 370
234# 371#
235# Mapping drivers for chip access 372# Mapping drivers for chip access
236# 373#
237# CONFIG_MTD_COMPLEX_MAPPINGS is not set 374# CONFIG_MTD_COMPLEX_MAPPINGS is not set
238CONFIG_MTD_PHYSMAP=y 375CONFIG_MTD_PHYSMAP=y
239CONFIG_MTD_PHYSMAP_START=0xc0000000 376CONFIG_MTD_PHYSMAP_START=0x0
240CONFIG_MTD_PHYSMAP_LEN=0x00800000 377CONFIG_MTD_PHYSMAP_LEN=0x0
241CONFIG_MTD_PHYSMAP_BANKWIDTH=1 378CONFIG_MTD_PHYSMAP_BANKWIDTH=1
242# CONFIG_MTD_ARM_INTEGRATOR is not set 379# CONFIG_MTD_ARM_INTEGRATOR is not set
243# CONFIG_MTD_EDB7312 is not set 380# CONFIG_MTD_PLATRAM is not set
244 381
245# 382#
246# Self-contained MTD device drivers 383# Self-contained MTD device drivers
@@ -249,7 +386,6 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=1
249# CONFIG_MTD_SLRAM is not set 386# CONFIG_MTD_SLRAM is not set
250# CONFIG_MTD_PHRAM is not set 387# CONFIG_MTD_PHRAM is not set
251# CONFIG_MTD_MTDRAM is not set 388# CONFIG_MTD_MTDRAM is not set
252# CONFIG_MTD_BLKMTD is not set
253# CONFIG_MTD_BLOCK2MTD is not set 389# CONFIG_MTD_BLOCK2MTD is not set
254 390
255# 391#
@@ -265,6 +401,11 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=1
265# CONFIG_MTD_NAND is not set 401# CONFIG_MTD_NAND is not set
266 402
267# 403#
404# OneNAND Flash Device Drivers
405#
406# CONFIG_MTD_ONENAND is not set
407
408#
268# Parallel port support 409# Parallel port support
269# 410#
270# CONFIG_PARPORT is not set 411# CONFIG_PARPORT is not set
@@ -276,7 +417,6 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=1
276# 417#
277# Block devices 418# Block devices
278# 419#
279# CONFIG_BLK_DEV_FD is not set
280# CONFIG_BLK_CPQ_DA is not set 420# CONFIG_BLK_CPQ_DA is not set
281# CONFIG_BLK_CPQ_CISS_DA is not set 421# CONFIG_BLK_CPQ_CISS_DA is not set
282# CONFIG_BLK_DEV_DAC960 is not set 422# CONFIG_BLK_DEV_DAC960 is not set
@@ -288,17 +428,9 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=1
288CONFIG_BLK_DEV_RAM=y 428CONFIG_BLK_DEV_RAM=y
289CONFIG_BLK_DEV_RAM_COUNT=16 429CONFIG_BLK_DEV_RAM_COUNT=16
290CONFIG_BLK_DEV_RAM_SIZE=8192 430CONFIG_BLK_DEV_RAM_SIZE=8192
291# CONFIG_BLK_DEV_INITRD is not set 431CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
292CONFIG_INITRAMFS_SOURCE="" 432CONFIG_BLK_DEV_INITRD=y
293# CONFIG_CDROM_PKTCDVD is not set 433# CONFIG_CDROM_PKTCDVD is not set
294
295#
296# IO Schedulers
297#
298CONFIG_IOSCHED_NOOP=y
299CONFIG_IOSCHED_AS=y
300CONFIG_IOSCHED_DEADLINE=y
301CONFIG_IOSCHED_CFQ=y
302# CONFIG_ATA_OVER_ETH is not set 434# CONFIG_ATA_OVER_ETH is not set
303 435
304# 436#
@@ -309,6 +441,7 @@ CONFIG_IOSCHED_CFQ=y
309# 441#
310# SCSI device support 442# SCSI device support
311# 443#
444# CONFIG_RAID_ATTRS is not set
312CONFIG_SCSI=y 445CONFIG_SCSI=y
313CONFIG_SCSI_PROC_FS=y 446CONFIG_SCSI_PROC_FS=y
314 447
@@ -320,6 +453,7 @@ CONFIG_BLK_DEV_SD=y
320# CONFIG_CHR_DEV_OSST is not set 453# CONFIG_CHR_DEV_OSST is not set
321# CONFIG_BLK_DEV_SR is not set 454# CONFIG_BLK_DEV_SR is not set
322CONFIG_CHR_DEV_SG=y 455CONFIG_CHR_DEV_SG=y
456# CONFIG_CHR_DEV_SCH is not set
323 457
324# 458#
325# Some SCSI devices (e.g. CD jukebox) support multiple LUNs 459# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -334,10 +468,12 @@ CONFIG_CHR_DEV_SG=y
334# CONFIG_SCSI_SPI_ATTRS is not set 468# CONFIG_SCSI_SPI_ATTRS is not set
335# CONFIG_SCSI_FC_ATTRS is not set 469# CONFIG_SCSI_FC_ATTRS is not set
336# CONFIG_SCSI_ISCSI_ATTRS is not set 470# CONFIG_SCSI_ISCSI_ATTRS is not set
471# CONFIG_SCSI_SAS_ATTRS is not set
337 472
338# 473#
339# SCSI low-level drivers 474# SCSI low-level drivers
340# 475#
476# CONFIG_ISCSI_TCP is not set
341# CONFIG_BLK_DEV_3W_XXXX_RAID is not set 477# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
342# CONFIG_SCSI_3W_9XXX is not set 478# CONFIG_SCSI_3W_9XXX is not set
343# CONFIG_SCSI_ACARD is not set 479# CONFIG_SCSI_ACARD is not set
@@ -348,25 +484,19 @@ CONFIG_CHR_DEV_SG=y
348# CONFIG_SCSI_DPT_I2O is not set 484# CONFIG_SCSI_DPT_I2O is not set
349# CONFIG_MEGARAID_NEWGEN is not set 485# CONFIG_MEGARAID_NEWGEN is not set
350# CONFIG_MEGARAID_LEGACY is not set 486# CONFIG_MEGARAID_LEGACY is not set
487# CONFIG_MEGARAID_SAS is not set
351# CONFIG_SCSI_SATA is not set 488# CONFIG_SCSI_SATA is not set
352# CONFIG_SCSI_BUSLOGIC is not set 489# CONFIG_SCSI_HPTIOP is not set
353# CONFIG_SCSI_DMX3191D is not set 490# CONFIG_SCSI_DMX3191D is not set
354# CONFIG_SCSI_EATA is not set
355# CONFIG_SCSI_FUTURE_DOMAIN is not set 491# CONFIG_SCSI_FUTURE_DOMAIN is not set
356# CONFIG_SCSI_GDTH is not set
357# CONFIG_SCSI_IPS is not set 492# CONFIG_SCSI_IPS is not set
358# CONFIG_SCSI_INITIO is not set 493# CONFIG_SCSI_INITIO is not set
359# CONFIG_SCSI_INIA100 is not set 494# CONFIG_SCSI_INIA100 is not set
360# CONFIG_SCSI_SYM53C8XX_2 is not set 495# CONFIG_SCSI_SYM53C8XX_2 is not set
361# CONFIG_SCSI_IPR is not set 496# CONFIG_SCSI_IPR is not set
362# CONFIG_SCSI_QLOGIC_FC is not set
363# CONFIG_SCSI_QLOGIC_1280 is not set 497# CONFIG_SCSI_QLOGIC_1280 is not set
364CONFIG_SCSI_QLA2XXX=y 498# CONFIG_SCSI_QLA_FC is not set
365# CONFIG_SCSI_QLA21XX is not set 499# CONFIG_SCSI_LPFC is not set
366# CONFIG_SCSI_QLA22XX is not set
367# CONFIG_SCSI_QLA2300 is not set
368# CONFIG_SCSI_QLA2322 is not set
369# CONFIG_SCSI_QLA6312 is not set
370# CONFIG_SCSI_DC395x is not set 500# CONFIG_SCSI_DC395x is not set
371# CONFIG_SCSI_DC390T is not set 501# CONFIG_SCSI_DC390T is not set
372# CONFIG_SCSI_NSP32 is not set 502# CONFIG_SCSI_NSP32 is not set
@@ -381,8 +511,7 @@ CONFIG_MD_LINEAR=y
381CONFIG_MD_RAID0=y 511CONFIG_MD_RAID0=y
382CONFIG_MD_RAID1=y 512CONFIG_MD_RAID1=y
383# CONFIG_MD_RAID10 is not set 513# CONFIG_MD_RAID10 is not set
384CONFIG_MD_RAID5=y 514# CONFIG_MD_RAID456 is not set
385# CONFIG_MD_RAID6 is not set
386# CONFIG_MD_MULTIPATH is not set 515# CONFIG_MD_MULTIPATH is not set
387# CONFIG_MD_FAULTY is not set 516# CONFIG_MD_FAULTY is not set
388CONFIG_BLK_DEV_DM=y 517CONFIG_BLK_DEV_DM=y
@@ -396,6 +525,9 @@ CONFIG_BLK_DEV_DM=y
396# Fusion MPT device support 525# Fusion MPT device support
397# 526#
398# CONFIG_FUSION is not set 527# CONFIG_FUSION is not set
528# CONFIG_FUSION_SPI is not set
529# CONFIG_FUSION_FC is not set
530# CONFIG_FUSION_SAS is not set
399 531
400# 532#
401# IEEE 1394 (FireWire) support 533# IEEE 1394 (FireWire) support
@@ -408,71 +540,8 @@ CONFIG_BLK_DEV_DM=y
408# CONFIG_I2O is not set 540# CONFIG_I2O is not set
409 541
410# 542#
411# Networking support 543# Network device support
412#
413CONFIG_NET=y
414
415#
416# Networking options
417#
418CONFIG_PACKET=y
419CONFIG_PACKET_MMAP=y
420# CONFIG_NETLINK_DEV is not set
421CONFIG_UNIX=y
422# CONFIG_NET_KEY is not set
423CONFIG_INET=y
424CONFIG_IP_MULTICAST=y
425# CONFIG_IP_ADVANCED_ROUTER is not set
426CONFIG_IP_PNP=y
427# CONFIG_IP_PNP_DHCP is not set
428CONFIG_IP_PNP_BOOTP=y
429# CONFIG_IP_PNP_RARP is not set
430# CONFIG_NET_IPIP is not set
431# CONFIG_NET_IPGRE is not set
432# CONFIG_IP_MROUTE is not set
433# CONFIG_ARPD is not set
434# CONFIG_SYN_COOKIES is not set
435# CONFIG_INET_AH is not set
436# CONFIG_INET_ESP is not set
437# CONFIG_INET_IPCOMP is not set
438# CONFIG_INET_TUNNEL is not set
439CONFIG_IP_TCPDIAG=y
440# CONFIG_IP_TCPDIAG_IPV6 is not set
441# CONFIG_IPV6 is not set
442# CONFIG_NETFILTER is not set
443
444# 544#
445# SCTP Configuration (EXPERIMENTAL)
446#
447# CONFIG_IP_SCTP is not set
448# CONFIG_ATM is not set
449# CONFIG_BRIDGE is not set
450# CONFIG_VLAN_8021Q is not set
451# CONFIG_DECNET is not set
452# CONFIG_LLC2 is not set
453# CONFIG_IPX is not set
454# CONFIG_ATALK is not set
455# CONFIG_X25 is not set
456# CONFIG_LAPB is not set
457# CONFIG_NET_DIVERT is not set
458# CONFIG_ECONET is not set
459# CONFIG_WAN_ROUTER is not set
460
461#
462# QoS and/or fair queueing
463#
464# CONFIG_NET_SCHED is not set
465# CONFIG_NET_CLS_ROUTE is not set
466
467#
468# Network testing
469#
470# CONFIG_NET_PKTGEN is not set
471# CONFIG_NETPOLL is not set
472# CONFIG_NET_POLL_CONTROLLER is not set
473# CONFIG_HAMRADIO is not set
474# CONFIG_IRDA is not set
475# CONFIG_BT is not set
476CONFIG_NETDEVICES=y 545CONFIG_NETDEVICES=y
477# CONFIG_DUMMY is not set 546# CONFIG_DUMMY is not set
478# CONFIG_BONDING is not set 547# CONFIG_BONDING is not set
@@ -485,6 +554,10 @@ CONFIG_NETDEVICES=y
485# CONFIG_ARCNET is not set 554# CONFIG_ARCNET is not set
486 555
487# 556#
557# PHY device support
558#
559
560#
488# Ethernet (10 or 100Mbit) 561# Ethernet (10 or 100Mbit)
489# 562#
490# CONFIG_NET_ETHERNET is not set 563# CONFIG_NET_ETHERNET is not set
@@ -501,14 +574,20 @@ CONFIG_E1000_NAPI=y
501# CONFIG_HAMACHI is not set 574# CONFIG_HAMACHI is not set
502# CONFIG_YELLOWFIN is not set 575# CONFIG_YELLOWFIN is not set
503# CONFIG_R8169 is not set 576# CONFIG_R8169 is not set
577# CONFIG_SIS190 is not set
578# CONFIG_SKGE is not set
579# CONFIG_SKY2 is not set
504# CONFIG_SK98LIN is not set 580# CONFIG_SK98LIN is not set
505# CONFIG_TIGON3 is not set 581# CONFIG_TIGON3 is not set
582# CONFIG_BNX2 is not set
506 583
507# 584#
508# Ethernet (10000 Mbit) 585# Ethernet (10000 Mbit)
509# 586#
587# CONFIG_CHELSIO_T1 is not set
510# CONFIG_IXGB is not set 588# CONFIG_IXGB is not set
511# CONFIG_S2IO is not set 589# CONFIG_S2IO is not set
590# CONFIG_MYRI10GE is not set
512 591
513# 592#
514# Token Ring devices 593# Token Ring devices
@@ -531,6 +610,8 @@ CONFIG_E1000_NAPI=y
531# CONFIG_NET_FC is not set 610# CONFIG_NET_FC is not set
532# CONFIG_SHAPER is not set 611# CONFIG_SHAPER is not set
533# CONFIG_NETCONSOLE is not set 612# CONFIG_NETCONSOLE is not set
613# CONFIG_NETPOLL is not set
614# CONFIG_NET_POLL_CONTROLLER is not set
534 615
535# 616#
536# ISDN subsystem 617# ISDN subsystem
@@ -568,7 +649,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
568# 649#
569# CONFIG_SERIO is not set 650# CONFIG_SERIO is not set
570# CONFIG_GAMEPORT is not set 651# CONFIG_GAMEPORT is not set
571CONFIG_SOUND_GAMEPORT=y
572 652
573# 653#
574# Character devices 654# Character devices
@@ -576,6 +656,7 @@ CONFIG_SOUND_GAMEPORT=y
576CONFIG_VT=y 656CONFIG_VT=y
577CONFIG_VT_CONSOLE=y 657CONFIG_VT_CONSOLE=y
578CONFIG_HW_CONSOLE=y 658CONFIG_HW_CONSOLE=y
659# CONFIG_VT_HW_CONSOLE_BINDING is not set
579# CONFIG_SERIAL_NONSTANDARD is not set 660# CONFIG_SERIAL_NONSTANDARD is not set
580 661
581# 662#
@@ -583,7 +664,9 @@ CONFIG_HW_CONSOLE=y
583# 664#
584CONFIG_SERIAL_8250=y 665CONFIG_SERIAL_8250=y
585CONFIG_SERIAL_8250_CONSOLE=y 666CONFIG_SERIAL_8250_CONSOLE=y
667CONFIG_SERIAL_8250_PCI=y
586CONFIG_SERIAL_8250_NR_UARTS=4 668CONFIG_SERIAL_8250_NR_UARTS=4
669CONFIG_SERIAL_8250_RUNTIME_UARTS=4
587# CONFIG_SERIAL_8250_EXTENDED is not set 670# CONFIG_SERIAL_8250_EXTENDED is not set
588 671
589# 672#
@@ -591,6 +674,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4
591# 674#
592CONFIG_SERIAL_CORE=y 675CONFIG_SERIAL_CORE=y
593CONFIG_SERIAL_CORE_CONSOLE=y 676CONFIG_SERIAL_CORE_CONSOLE=y
677# CONFIG_SERIAL_JSM is not set
594CONFIG_UNIX98_PTYS=y 678CONFIG_UNIX98_PTYS=y
595CONFIG_LEGACY_PTYS=y 679CONFIG_LEGACY_PTYS=y
596CONFIG_LEGACY_PTY_COUNT=256 680CONFIG_LEGACY_PTY_COUNT=256
@@ -604,8 +688,8 @@ CONFIG_LEGACY_PTY_COUNT=256
604# Watchdog Cards 688# Watchdog Cards
605# 689#
606# CONFIG_WATCHDOG is not set 690# CONFIG_WATCHDOG is not set
691CONFIG_HW_RANDOM=y
607# CONFIG_NVRAM is not set 692# CONFIG_NVRAM is not set
608# CONFIG_RTC is not set
609# CONFIG_DTLK is not set 693# CONFIG_DTLK is not set
610# CONFIG_R3964 is not set 694# CONFIG_R3964 is not set
611# CONFIG_APPLICOM is not set 695# CONFIG_APPLICOM is not set
@@ -620,6 +704,7 @@ CONFIG_LEGACY_PTY_COUNT=256
620# TPM devices 704# TPM devices
621# 705#
622# CONFIG_TCG_TPM is not set 706# CONFIG_TCG_TPM is not set
707# CONFIG_TELCLOCK is not set
623 708
624# 709#
625# I2C support 710# I2C support
@@ -644,14 +729,13 @@ CONFIG_I2C_CHARDEV=y
644# CONFIG_I2C_AMD8111 is not set 729# CONFIG_I2C_AMD8111 is not set
645# CONFIG_I2C_I801 is not set 730# CONFIG_I2C_I801 is not set
646# CONFIG_I2C_I810 is not set 731# CONFIG_I2C_I810 is not set
732# CONFIG_I2C_PIIX4 is not set
647CONFIG_I2C_IOP3XX=y 733CONFIG_I2C_IOP3XX=y
648# CONFIG_I2C_ISA is not set
649# CONFIG_I2C_NFORCE2 is not set 734# CONFIG_I2C_NFORCE2 is not set
735# CONFIG_I2C_OCORES is not set
650# CONFIG_I2C_PARPORT_LIGHT is not set 736# CONFIG_I2C_PARPORT_LIGHT is not set
651# CONFIG_I2C_PIIX4 is not set
652# CONFIG_I2C_PROSAVAGE is not set 737# CONFIG_I2C_PROSAVAGE is not set
653# CONFIG_I2C_SAVAGE4 is not set 738# CONFIG_I2C_SAVAGE4 is not set
654# CONFIG_SCx200_ACB is not set
655# CONFIG_I2C_SIS5595 is not set 739# CONFIG_I2C_SIS5595 is not set
656# CONFIG_I2C_SIS630 is not set 740# CONFIG_I2C_SIS630 is not set
657# CONFIG_I2C_SIS96X is not set 741# CONFIG_I2C_SIS96X is not set
@@ -662,15 +746,45 @@ CONFIG_I2C_IOP3XX=y
662# CONFIG_I2C_PCA_ISA is not set 746# CONFIG_I2C_PCA_ISA is not set
663 747
664# 748#
665# Hardware Sensors Chip support 749# Miscellaneous I2C Chip support
666# 750#
667# CONFIG_I2C_SENSOR is not set 751# CONFIG_SENSORS_DS1337 is not set
752# CONFIG_SENSORS_DS1374 is not set
753# CONFIG_SENSORS_EEPROM is not set
754# CONFIG_SENSORS_PCF8574 is not set
755# CONFIG_SENSORS_PCA9539 is not set
756# CONFIG_SENSORS_PCF8591 is not set
757# CONFIG_SENSORS_MAX6875 is not set
758# CONFIG_I2C_DEBUG_CORE is not set
759# CONFIG_I2C_DEBUG_ALGO is not set
760# CONFIG_I2C_DEBUG_BUS is not set
761# CONFIG_I2C_DEBUG_CHIP is not set
762
763#
764# SPI support
765#
766# CONFIG_SPI is not set
767# CONFIG_SPI_MASTER is not set
768
769#
770# Dallas's 1-wire bus
771#
772
773#
774# Hardware Monitoring support
775#
776CONFIG_HWMON=y
777# CONFIG_HWMON_VID is not set
778# CONFIG_SENSORS_ABITUGURU is not set
668# CONFIG_SENSORS_ADM1021 is not set 779# CONFIG_SENSORS_ADM1021 is not set
669# CONFIG_SENSORS_ADM1025 is not set 780# CONFIG_SENSORS_ADM1025 is not set
670# CONFIG_SENSORS_ADM1026 is not set 781# CONFIG_SENSORS_ADM1026 is not set
671# CONFIG_SENSORS_ADM1031 is not set 782# CONFIG_SENSORS_ADM1031 is not set
783# CONFIG_SENSORS_ADM9240 is not set
672# CONFIG_SENSORS_ASB100 is not set 784# CONFIG_SENSORS_ASB100 is not set
785# CONFIG_SENSORS_ATXP1 is not set
673# CONFIG_SENSORS_DS1621 is not set 786# CONFIG_SENSORS_DS1621 is not set
787# CONFIG_SENSORS_F71805F is not set
674# CONFIG_SENSORS_FSCHER is not set 788# CONFIG_SENSORS_FSCHER is not set
675# CONFIG_SENSORS_FSCPOS is not set 789# CONFIG_SENSORS_FSCPOS is not set
676# CONFIG_SENSORS_GL518SM is not set 790# CONFIG_SENSORS_GL518SM is not set
@@ -685,36 +799,45 @@ CONFIG_I2C_IOP3XX=y
685# CONFIG_SENSORS_LM85 is not set 799# CONFIG_SENSORS_LM85 is not set
686# CONFIG_SENSORS_LM87 is not set 800# CONFIG_SENSORS_LM87 is not set
687# CONFIG_SENSORS_LM90 is not set 801# CONFIG_SENSORS_LM90 is not set
802# CONFIG_SENSORS_LM92 is not set
688# CONFIG_SENSORS_MAX1619 is not set 803# CONFIG_SENSORS_MAX1619 is not set
689# CONFIG_SENSORS_PC87360 is not set 804# CONFIG_SENSORS_PC87360 is not set
690# CONFIG_SENSORS_SMSC47B397 is not set
691# CONFIG_SENSORS_SIS5595 is not set 805# CONFIG_SENSORS_SIS5595 is not set
692# CONFIG_SENSORS_SMSC47M1 is not set 806# CONFIG_SENSORS_SMSC47M1 is not set
807# CONFIG_SENSORS_SMSC47M192 is not set
808# CONFIG_SENSORS_SMSC47B397 is not set
693# CONFIG_SENSORS_VIA686A is not set 809# CONFIG_SENSORS_VIA686A is not set
810# CONFIG_SENSORS_VT8231 is not set
694# CONFIG_SENSORS_W83781D is not set 811# CONFIG_SENSORS_W83781D is not set
812# CONFIG_SENSORS_W83791D is not set
813# CONFIG_SENSORS_W83792D is not set
695# CONFIG_SENSORS_W83L785TS is not set 814# CONFIG_SENSORS_W83L785TS is not set
696# CONFIG_SENSORS_W83627HF is not set 815# CONFIG_SENSORS_W83627HF is not set
816# CONFIG_SENSORS_W83627EHF is not set
817# CONFIG_HWMON_DEBUG_CHIP is not set
697 818
698# 819#
699# Other I2C Chip support 820# Misc devices
700# 821#
701# CONFIG_SENSORS_EEPROM is not set
702# CONFIG_SENSORS_PCF8574 is not set
703# CONFIG_SENSORS_PCF8591 is not set
704# CONFIG_SENSORS_RTC8564 is not set
705# CONFIG_I2C_DEBUG_CORE is not set
706# CONFIG_I2C_DEBUG_ALGO is not set
707# CONFIG_I2C_DEBUG_BUS is not set
708# CONFIG_I2C_DEBUG_CHIP is not set
709 822
710# 823#
711# Misc devices 824# LED devices
825#
826# CONFIG_NEW_LEDS is not set
827
828#
829# LED drivers
830#
831
832#
833# LED Triggers
712# 834#
713 835
714# 836#
715# Multimedia devices 837# Multimedia devices
716# 838#
717# CONFIG_VIDEO_DEV is not set 839# CONFIG_VIDEO_DEV is not set
840CONFIG_VIDEO_V4L2=y
718 841
719# 842#
720# Digital Video Broadcasting Devices 843# Digital Video Broadcasting Devices
@@ -724,6 +847,7 @@ CONFIG_I2C_IOP3XX=y
724# 847#
725# Graphics support 848# Graphics support
726# 849#
850CONFIG_FIRMWARE_EDID=y
727# CONFIG_FB is not set 851# CONFIG_FB is not set
728 852
729# 853#
@@ -731,6 +855,7 @@ CONFIG_I2C_IOP3XX=y
731# 855#
732# CONFIG_VGA_CONSOLE is not set 856# CONFIG_VGA_CONSOLE is not set
733CONFIG_DUMMY_CONSOLE=y 857CONFIG_DUMMY_CONSOLE=y
858# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
734 859
735# 860#
736# Sound 861# Sound
@@ -742,9 +867,14 @@ CONFIG_DUMMY_CONSOLE=y
742# 867#
743CONFIG_USB_ARCH_HAS_HCD=y 868CONFIG_USB_ARCH_HAS_HCD=y
744CONFIG_USB_ARCH_HAS_OHCI=y 869CONFIG_USB_ARCH_HAS_OHCI=y
870CONFIG_USB_ARCH_HAS_EHCI=y
745# CONFIG_USB is not set 871# CONFIG_USB is not set
746 872
747# 873#
874# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
875#
876
877#
748# USB Gadget Support 878# USB Gadget Support
749# 879#
750# CONFIG_USB_GADGET is not set 880# CONFIG_USB_GADGET is not set
@@ -755,10 +885,17 @@ CONFIG_USB_ARCH_HAS_OHCI=y
755# CONFIG_MMC is not set 885# CONFIG_MMC is not set
756 886
757# 887#
888# Real Time Clock
889#
890CONFIG_RTC_LIB=y
891# CONFIG_RTC_CLASS is not set
892
893#
758# File systems 894# File systems
759# 895#
760CONFIG_EXT2_FS=y 896CONFIG_EXT2_FS=y
761# CONFIG_EXT2_FS_XATTR is not set 897# CONFIG_EXT2_FS_XATTR is not set
898# CONFIG_EXT2_FS_XIP is not set
762CONFIG_EXT3_FS=y 899CONFIG_EXT3_FS=y
763CONFIG_EXT3_FS_XATTR=y 900CONFIG_EXT3_FS_XATTR=y
764# CONFIG_EXT3_FS_POSIX_ACL is not set 901# CONFIG_EXT3_FS_POSIX_ACL is not set
@@ -768,22 +905,22 @@ CONFIG_JBD=y
768CONFIG_FS_MBCACHE=y 905CONFIG_FS_MBCACHE=y
769# CONFIG_REISERFS_FS is not set 906# CONFIG_REISERFS_FS is not set
770# CONFIG_JFS_FS is not set 907# CONFIG_JFS_FS is not set
771 908# CONFIG_FS_POSIX_ACL is not set
772#
773# XFS support
774#
775CONFIG_XFS_FS=y 909CONFIG_XFS_FS=y
776CONFIG_XFS_EXPORT=y
777# CONFIG_XFS_RT is not set
778# CONFIG_XFS_QUOTA is not set 910# CONFIG_XFS_QUOTA is not set
779CONFIG_XFS_SECURITY=y 911CONFIG_XFS_SECURITY=y
780CONFIG_XFS_POSIX_ACL=y 912CONFIG_XFS_POSIX_ACL=y
913# CONFIG_XFS_RT is not set
914# CONFIG_OCFS2_FS is not set
781# CONFIG_MINIX_FS is not set 915# CONFIG_MINIX_FS is not set
782# CONFIG_ROMFS_FS is not set 916# CONFIG_ROMFS_FS is not set
917CONFIG_INOTIFY=y
918CONFIG_INOTIFY_USER=y
783# CONFIG_QUOTA is not set 919# CONFIG_QUOTA is not set
784CONFIG_DNOTIFY=y 920CONFIG_DNOTIFY=y
785# CONFIG_AUTOFS_FS is not set 921# CONFIG_AUTOFS_FS is not set
786# CONFIG_AUTOFS4_FS is not set 922# CONFIG_AUTOFS4_FS is not set
923# CONFIG_FUSE_FS is not set
787 924
788# 925#
789# CD-ROM/DVD Filesystems 926# CD-ROM/DVD Filesystems
@@ -803,12 +940,10 @@ CONFIG_DNOTIFY=y
803# 940#
804CONFIG_PROC_FS=y 941CONFIG_PROC_FS=y
805CONFIG_SYSFS=y 942CONFIG_SYSFS=y
806# CONFIG_DEVFS_FS is not set
807# CONFIG_DEVPTS_FS_XATTR is not set
808CONFIG_TMPFS=y 943CONFIG_TMPFS=y
809# CONFIG_TMPFS_XATTR is not set
810# CONFIG_HUGETLB_PAGE is not set 944# CONFIG_HUGETLB_PAGE is not set
811CONFIG_RAMFS=y 945CONFIG_RAMFS=y
946# CONFIG_CONFIGFS_FS is not set
812 947
813# 948#
814# Miscellaneous filesystems 949# Miscellaneous filesystems
@@ -834,16 +969,19 @@ CONFIG_RAMFS=y
834# 969#
835CONFIG_NFS_FS=y 970CONFIG_NFS_FS=y
836CONFIG_NFS_V3=y 971CONFIG_NFS_V3=y
972# CONFIG_NFS_V3_ACL is not set
837# CONFIG_NFS_V4 is not set 973# CONFIG_NFS_V4 is not set
838# CONFIG_NFS_DIRECTIO is not set 974# CONFIG_NFS_DIRECTIO is not set
839CONFIG_NFSD=y 975CONFIG_NFSD=y
840CONFIG_NFSD_V3=y 976CONFIG_NFSD_V3=y
977# CONFIG_NFSD_V3_ACL is not set
841# CONFIG_NFSD_V4 is not set 978# CONFIG_NFSD_V4 is not set
842# CONFIG_NFSD_TCP is not set 979# CONFIG_NFSD_TCP is not set
843CONFIG_ROOT_NFS=y 980CONFIG_ROOT_NFS=y
844CONFIG_LOCKD=y 981CONFIG_LOCKD=y
845CONFIG_LOCKD_V4=y 982CONFIG_LOCKD_V4=y
846CONFIG_EXPORTFS=y 983CONFIG_EXPORTFS=y
984CONFIG_NFS_COMMON=y
847CONFIG_SUNRPC=y 985CONFIG_SUNRPC=y
848# CONFIG_RPCSEC_GSS_KRB5 is not set 986# CONFIG_RPCSEC_GSS_KRB5 is not set
849# CONFIG_RPCSEC_GSS_SPKM3 is not set 987# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -852,6 +990,7 @@ CONFIG_SUNRPC=y
852# CONFIG_NCP_FS is not set 990# CONFIG_NCP_FS is not set
853# CONFIG_CODA_FS is not set 991# CONFIG_CODA_FS is not set
854# CONFIG_AFS_FS is not set 992# CONFIG_AFS_FS is not set
993# CONFIG_9P_FS is not set
855 994
856# 995#
857# Partition Types 996# Partition Types
@@ -871,6 +1010,7 @@ CONFIG_MSDOS_PARTITION=y
871# CONFIG_SGI_PARTITION is not set 1010# CONFIG_SGI_PARTITION is not set
872# CONFIG_ULTRIX_PARTITION is not set 1011# CONFIG_ULTRIX_PARTITION is not set
873# CONFIG_SUN_PARTITION is not set 1012# CONFIG_SUN_PARTITION is not set
1013# CONFIG_KARMA_PARTITION is not set
874# CONFIG_EFI_PARTITION is not set 1014# CONFIG_EFI_PARTITION is not set
875 1015
876# 1016#
@@ -887,11 +1027,34 @@ CONFIG_MSDOS_PARTITION=y
887# Kernel hacking 1027# Kernel hacking
888# 1028#
889# CONFIG_PRINTK_TIME is not set 1029# CONFIG_PRINTK_TIME is not set
890# CONFIG_DEBUG_KERNEL is not set 1030CONFIG_MAGIC_SYSRQ=y
1031# CONFIG_UNUSED_SYMBOLS is not set
1032CONFIG_DEBUG_KERNEL=y
891CONFIG_LOG_BUF_SHIFT=14 1033CONFIG_LOG_BUF_SHIFT=14
1034CONFIG_DETECT_SOFTLOCKUP=y
1035# CONFIG_SCHEDSTATS is not set
1036# CONFIG_DEBUG_SLAB is not set
1037# CONFIG_DEBUG_RT_MUTEXES is not set
1038# CONFIG_RT_MUTEX_TESTER is not set
1039# CONFIG_DEBUG_SPINLOCK is not set
1040# CONFIG_DEBUG_MUTEXES is not set
1041# CONFIG_DEBUG_RWSEMS is not set
1042# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1043# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1044# CONFIG_DEBUG_KOBJECT is not set
892CONFIG_DEBUG_BUGVERBOSE=y 1045CONFIG_DEBUG_BUGVERBOSE=y
1046# CONFIG_DEBUG_INFO is not set
1047# CONFIG_DEBUG_FS is not set
1048# CONFIG_DEBUG_VM is not set
893CONFIG_FRAME_POINTER=y 1049CONFIG_FRAME_POINTER=y
1050# CONFIG_UNWIND_INFO is not set
1051# CONFIG_FORCED_INLINING is not set
1052# CONFIG_RCU_TORTURE_TEST is not set
894CONFIG_DEBUG_USER=y 1053CONFIG_DEBUG_USER=y
1054# CONFIG_DEBUG_WAITQ is not set
1055# CONFIG_DEBUG_ERRORS is not set
1056CONFIG_DEBUG_LL=y
1057# CONFIG_DEBUG_ICEDCC is not set
895 1058
896# 1059#
897# Security options 1060# Security options
@@ -912,5 +1075,7 @@ CONFIG_DEBUG_USER=y
912# Library routines 1075# Library routines
913# 1076#
914# CONFIG_CRC_CCITT is not set 1077# CONFIG_CRC_CCITT is not set
1078# CONFIG_CRC16 is not set
915# CONFIG_CRC32 is not set 1079# CONFIG_CRC32 is not set
916# CONFIG_LIBCRC32C is not set 1080# CONFIG_LIBCRC32C is not set
1081CONFIG_PLIST=y
diff --git a/arch/arm/configs/iq31244_defconfig b/arch/arm/configs/iq31244_defconfig
deleted file mode 100644
index 32467160a6df..000000000000
--- a/arch/arm/configs/iq31244_defconfig
+++ /dev/null
@@ -1,922 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc1-bk2
4# Sun Mar 27 02:10:38 2005
5#
6CONFIG_ARM=y
7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y
11CONFIG_GENERIC_IOMAP=y
12
13#
14# Code maturity level options
15#
16CONFIG_EXPERIMENTAL=y
17CONFIG_CLEAN_COMPILE=y
18CONFIG_BROKEN_ON_SMP=y
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION=""
24CONFIG_SWAP=y
25CONFIG_SYSVIPC=y
26# CONFIG_POSIX_MQUEUE is not set
27CONFIG_BSD_PROCESS_ACCT=y
28# CONFIG_BSD_PROCESS_ACCT_V3 is not set
29CONFIG_SYSCTL=y
30# CONFIG_AUDIT is not set
31# CONFIG_HOTPLUG is not set
32CONFIG_KOBJECT_UEVENT=y
33CONFIG_IKCONFIG=y
34CONFIG_IKCONFIG_PROC=y
35# CONFIG_EMBEDDED is not set
36CONFIG_KALLSYMS=y
37# CONFIG_KALLSYMS_EXTRA_PASS is not set
38CONFIG_BASE_FULL=y
39CONFIG_FUTEX=y
40CONFIG_EPOLL=y
41CONFIG_CC_OPTIMIZE_FOR_SIZE=y
42CONFIG_SHMEM=y
43CONFIG_CC_ALIGN_FUNCTIONS=0
44CONFIG_CC_ALIGN_LABELS=0
45CONFIG_CC_ALIGN_LOOPS=0
46CONFIG_CC_ALIGN_JUMPS=0
47# CONFIG_TINY_SHMEM is not set
48CONFIG_BASE_SMALL=0
49
50#
51# Loadable module support
52#
53CONFIG_MODULES=y
54CONFIG_MODULE_UNLOAD=y
55# CONFIG_MODULE_FORCE_UNLOAD is not set
56CONFIG_OBSOLETE_MODPARM=y
57# CONFIG_MODVERSIONS is not set
58# CONFIG_MODULE_SRCVERSION_ALL is not set
59CONFIG_KMOD=y
60
61#
62# System Type
63#
64# CONFIG_ARCH_CLPS7500 is not set
65# CONFIG_ARCH_CLPS711X is not set
66# CONFIG_ARCH_CO285 is not set
67# CONFIG_ARCH_EBSA110 is not set
68# CONFIG_ARCH_FOOTBRIDGE is not set
69# CONFIG_ARCH_INTEGRATOR is not set
70CONFIG_ARCH_IOP3XX=y
71# CONFIG_ARCH_IXP4XX is not set
72# CONFIG_ARCH_IXP2000 is not set
73# CONFIG_ARCH_L7200 is not set
74# CONFIG_ARCH_PXA is not set
75# CONFIG_ARCH_RPC is not set
76# CONFIG_ARCH_SA1100 is not set
77# CONFIG_ARCH_S3C2410 is not set
78# CONFIG_ARCH_SHARK is not set
79# CONFIG_ARCH_LH7A40X is not set
80# CONFIG_ARCH_OMAP is not set
81# CONFIG_ARCH_VERSATILE is not set
82# CONFIG_ARCH_IMX is not set
83# CONFIG_ARCH_H720X is not set
84
85#
86# IOP3xx Implementation Options
87#
88
89#
90# IOP3xx Platform Types
91#
92# CONFIG_ARCH_IQ80321 is not set
93CONFIG_ARCH_IQ31244=y
94# CONFIG_ARCH_IQ80331 is not set
95# CONFIG_MACH_IQ80332 is not set
96# CONFIG_ARCH_EP80219 is not set
97CONFIG_ARCH_IOP321=y
98# CONFIG_ARCH_IOP331 is not set
99
100#
101# IOP3xx Chipset Features
102#
103
104#
105# Processor Type
106#
107CONFIG_CPU_32=y
108CONFIG_CPU_XSCALE=y
109CONFIG_CPU_32v5=y
110CONFIG_CPU_ABRT_EV5T=y
111CONFIG_CPU_CACHE_VIVT=y
112CONFIG_CPU_TLB_V4WBI=y
113CONFIG_CPU_MINICACHE=y
114
115#
116# Processor Features
117#
118# CONFIG_ARM_THUMB is not set
119CONFIG_XSCALE_PMU=y
120
121#
122# Bus support
123#
124CONFIG_PCI=y
125# CONFIG_PCI_LEGACY_PROC is not set
126CONFIG_PCI_NAMES=y
127
128#
129# PCCARD (PCMCIA/CardBus) support
130#
131# CONFIG_PCCARD is not set
132
133#
134# Kernel Features
135#
136# CONFIG_PREEMPT is not set
137CONFIG_ALIGNMENT_TRAP=y
138
139#
140# Boot options
141#
142CONFIG_ZBOOT_ROM_TEXT=0x0
143CONFIG_ZBOOT_ROM_BSS=0x0
144CONFIG_CMDLINE="ip=boot root=nfs console=ttyS0,115200"
145# CONFIG_XIP_KERNEL is not set
146
147#
148# Floating point emulation
149#
150
151#
152# At least one emulation must be selected
153#
154CONFIG_FPE_NWFPE=y
155# CONFIG_FPE_NWFPE_XP is not set
156# CONFIG_FPE_FASTFPE is not set
157
158#
159# Userspace binary formats
160#
161CONFIG_BINFMT_ELF=y
162CONFIG_BINFMT_AOUT=y
163# CONFIG_BINFMT_MISC is not set
164# CONFIG_ARTHUR is not set
165
166#
167# Power management options
168#
169# CONFIG_PM is not set
170
171#
172# Device Drivers
173#
174
175#
176# Generic Driver Options
177#
178CONFIG_STANDALONE=y
179CONFIG_PREVENT_FIRMWARE_BUILD=y
180# CONFIG_FW_LOADER is not set
181
182#
183# Memory Technology Devices (MTD)
184#
185CONFIG_MTD=y
186# CONFIG_MTD_DEBUG is not set
187# CONFIG_MTD_CONCAT is not set
188CONFIG_MTD_PARTITIONS=y
189CONFIG_MTD_REDBOOT_PARTS=y
190CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
191CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
192CONFIG_MTD_REDBOOT_PARTS_READONLY=y
193# CONFIG_MTD_CMDLINE_PARTS is not set
194# CONFIG_MTD_AFS_PARTS is not set
195
196#
197# User Modules And Translation Layers
198#
199CONFIG_MTD_CHAR=y
200CONFIG_MTD_BLOCK=y
201# CONFIG_FTL is not set
202# CONFIG_NFTL is not set
203# CONFIG_INFTL is not set
204
205#
206# RAM/ROM/Flash chip drivers
207#
208CONFIG_MTD_CFI=y
209# CONFIG_MTD_JEDECPROBE is not set
210CONFIG_MTD_GEN_PROBE=y
211# CONFIG_MTD_CFI_ADV_OPTIONS is not set
212CONFIG_MTD_MAP_BANK_WIDTH_1=y
213CONFIG_MTD_MAP_BANK_WIDTH_2=y
214CONFIG_MTD_MAP_BANK_WIDTH_4=y
215# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
216# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
217# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
218CONFIG_MTD_CFI_I1=y
219CONFIG_MTD_CFI_I2=y
220# CONFIG_MTD_CFI_I4 is not set
221# CONFIG_MTD_CFI_I8 is not set
222CONFIG_MTD_CFI_INTELEXT=y
223# CONFIG_MTD_CFI_AMDSTD is not set
224# CONFIG_MTD_CFI_STAA is not set
225CONFIG_MTD_CFI_UTIL=y
226# CONFIG_MTD_RAM is not set
227# CONFIG_MTD_ROM is not set
228# CONFIG_MTD_ABSENT is not set
229# CONFIG_MTD_XIP is not set
230
231#
232# Mapping drivers for chip access
233#
234# CONFIG_MTD_COMPLEX_MAPPINGS is not set
235CONFIG_MTD_PHYSMAP=y
236CONFIG_MTD_PHYSMAP_START=0xf0000000
237CONFIG_MTD_PHYSMAP_LEN=0x00800000
238CONFIG_MTD_PHYSMAP_BANKWIDTH=2
239# CONFIG_MTD_ARM_INTEGRATOR is not set
240# CONFIG_MTD_EDB7312 is not set
241
242#
243# Self-contained MTD device drivers
244#
245# CONFIG_MTD_PMC551 is not set
246# CONFIG_MTD_SLRAM is not set
247# CONFIG_MTD_PHRAM is not set
248# CONFIG_MTD_MTDRAM is not set
249# CONFIG_MTD_BLKMTD is not set
250# CONFIG_MTD_BLOCK2MTD is not set
251
252#
253# Disk-On-Chip Device Drivers
254#
255# CONFIG_MTD_DOC2000 is not set
256# CONFIG_MTD_DOC2001 is not set
257# CONFIG_MTD_DOC2001PLUS is not set
258
259#
260# NAND Flash Device Drivers
261#
262# CONFIG_MTD_NAND is not set
263
264#
265# Parallel port support
266#
267# CONFIG_PARPORT is not set
268
269#
270# Plug and Play support
271#
272
273#
274# Block devices
275#
276# CONFIG_BLK_DEV_FD is not set
277# CONFIG_BLK_CPQ_DA is not set
278# CONFIG_BLK_CPQ_CISS_DA is not set
279# CONFIG_BLK_DEV_DAC960 is not set
280# CONFIG_BLK_DEV_UMEM is not set
281# CONFIG_BLK_DEV_COW_COMMON is not set
282# CONFIG_BLK_DEV_LOOP is not set
283# CONFIG_BLK_DEV_NBD is not set
284# CONFIG_BLK_DEV_SX8 is not set
285CONFIG_BLK_DEV_RAM=y
286CONFIG_BLK_DEV_RAM_COUNT=16
287CONFIG_BLK_DEV_RAM_SIZE=8192
288# CONFIG_BLK_DEV_INITRD is not set
289CONFIG_INITRAMFS_SOURCE=""
290# CONFIG_CDROM_PKTCDVD is not set
291
292#
293# IO Schedulers
294#
295CONFIG_IOSCHED_NOOP=y
296CONFIG_IOSCHED_AS=y
297CONFIG_IOSCHED_DEADLINE=y
298CONFIG_IOSCHED_CFQ=y
299# CONFIG_ATA_OVER_ETH is not set
300
301#
302# ATA/ATAPI/MFM/RLL support
303#
304# CONFIG_IDE is not set
305
306#
307# SCSI device support
308#
309CONFIG_SCSI=y
310CONFIG_SCSI_PROC_FS=y
311
312#
313# SCSI support type (disk, tape, CD-ROM)
314#
315CONFIG_BLK_DEV_SD=y
316# CONFIG_CHR_DEV_ST is not set
317# CONFIG_CHR_DEV_OSST is not set
318# CONFIG_BLK_DEV_SR is not set
319CONFIG_CHR_DEV_SG=y
320
321#
322# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
323#
324# CONFIG_SCSI_MULTI_LUN is not set
325# CONFIG_SCSI_CONSTANTS is not set
326# CONFIG_SCSI_LOGGING is not set
327
328#
329# SCSI Transport Attributes
330#
331# CONFIG_SCSI_SPI_ATTRS is not set
332# CONFIG_SCSI_FC_ATTRS is not set
333# CONFIG_SCSI_ISCSI_ATTRS is not set
334
335#
336# SCSI low-level drivers
337#
338# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
339# CONFIG_SCSI_3W_9XXX is not set
340# CONFIG_SCSI_ACARD is not set
341# CONFIG_SCSI_AACRAID is not set
342# CONFIG_SCSI_AIC7XXX is not set
343# CONFIG_SCSI_AIC7XXX_OLD is not set
344# CONFIG_SCSI_AIC79XX is not set
345# CONFIG_SCSI_DPT_I2O is not set
346# CONFIG_MEGARAID_NEWGEN is not set
347# CONFIG_MEGARAID_LEGACY is not set
348# CONFIG_SCSI_SATA is not set
349# CONFIG_SCSI_BUSLOGIC is not set
350# CONFIG_SCSI_DMX3191D is not set
351# CONFIG_SCSI_EATA is not set
352# CONFIG_SCSI_FUTURE_DOMAIN is not set
353# CONFIG_SCSI_GDTH is not set
354# CONFIG_SCSI_IPS is not set
355# CONFIG_SCSI_INITIO is not set
356# CONFIG_SCSI_INIA100 is not set
357# CONFIG_SCSI_SYM53C8XX_2 is not set
358# CONFIG_SCSI_IPR is not set
359# CONFIG_SCSI_QLOGIC_FC is not set
360# CONFIG_SCSI_QLOGIC_1280 is not set
361CONFIG_SCSI_QLA2XXX=y
362# CONFIG_SCSI_QLA21XX is not set
363# CONFIG_SCSI_QLA22XX is not set
364# CONFIG_SCSI_QLA2300 is not set
365# CONFIG_SCSI_QLA2322 is not set
366# CONFIG_SCSI_QLA6312 is not set
367# CONFIG_SCSI_DC395x is not set
368# CONFIG_SCSI_DC390T is not set
369# CONFIG_SCSI_NSP32 is not set
370# CONFIG_SCSI_DEBUG is not set
371
372#
373# Multi-device support (RAID and LVM)
374#
375CONFIG_MD=y
376CONFIG_BLK_DEV_MD=y
377# CONFIG_MD_LINEAR is not set
378CONFIG_MD_RAID0=y
379CONFIG_MD_RAID1=y
380# CONFIG_MD_RAID10 is not set
381CONFIG_MD_RAID5=y
382# CONFIG_MD_RAID6 is not set
383# CONFIG_MD_MULTIPATH is not set
384# CONFIG_MD_FAULTY is not set
385CONFIG_BLK_DEV_DM=y
386# CONFIG_DM_CRYPT is not set
387# CONFIG_DM_SNAPSHOT is not set
388# CONFIG_DM_MIRROR is not set
389# CONFIG_DM_ZERO is not set
390# CONFIG_DM_MULTIPATH is not set
391
392#
393# Fusion MPT device support
394#
395# CONFIG_FUSION is not set
396
397#
398# IEEE 1394 (FireWire) support
399#
400# CONFIG_IEEE1394 is not set
401
402#
403# I2O device support
404#
405# CONFIG_I2O is not set
406
407#
408# Networking support
409#
410CONFIG_NET=y
411
412#
413# Networking options
414#
415CONFIG_PACKET=y
416CONFIG_PACKET_MMAP=y
417# CONFIG_NETLINK_DEV is not set
418CONFIG_UNIX=y
419# CONFIG_NET_KEY is not set
420CONFIG_INET=y
421CONFIG_IP_MULTICAST=y
422# CONFIG_IP_ADVANCED_ROUTER is not set
423CONFIG_IP_PNP=y
424# CONFIG_IP_PNP_DHCP is not set
425CONFIG_IP_PNP_BOOTP=y
426# CONFIG_IP_PNP_RARP is not set
427# CONFIG_NET_IPIP is not set
428# CONFIG_NET_IPGRE is not set
429# CONFIG_IP_MROUTE is not set
430# CONFIG_ARPD is not set
431# CONFIG_SYN_COOKIES is not set
432# CONFIG_INET_AH is not set
433# CONFIG_INET_ESP is not set
434# CONFIG_INET_IPCOMP is not set
435# CONFIG_INET_TUNNEL is not set
436CONFIG_IP_TCPDIAG=y
437# CONFIG_IP_TCPDIAG_IPV6 is not set
438# CONFIG_IPV6 is not set
439# CONFIG_NETFILTER is not set
440
441#
442# SCTP Configuration (EXPERIMENTAL)
443#
444# CONFIG_IP_SCTP is not set
445# CONFIG_ATM is not set
446# CONFIG_BRIDGE is not set
447# CONFIG_VLAN_8021Q is not set
448# CONFIG_DECNET is not set
449# CONFIG_LLC2 is not set
450# CONFIG_IPX is not set
451# CONFIG_ATALK is not set
452# CONFIG_X25 is not set
453# CONFIG_LAPB is not set
454# CONFIG_NET_DIVERT is not set
455# CONFIG_ECONET is not set
456# CONFIG_WAN_ROUTER is not set
457
458#
459# QoS and/or fair queueing
460#
461# CONFIG_NET_SCHED is not set
462# CONFIG_NET_CLS_ROUTE is not set
463
464#
465# Network testing
466#
467# CONFIG_NET_PKTGEN is not set
468# CONFIG_NETPOLL is not set
469# CONFIG_NET_POLL_CONTROLLER is not set
470# CONFIG_HAMRADIO is not set
471# CONFIG_IRDA is not set
472# CONFIG_BT is not set
473CONFIG_NETDEVICES=y
474# CONFIG_DUMMY is not set
475# CONFIG_BONDING is not set
476# CONFIG_EQUALIZER is not set
477# CONFIG_TUN is not set
478
479#
480# ARCnet devices
481#
482# CONFIG_ARCNET is not set
483
484#
485# Ethernet (10 or 100Mbit)
486#
487# CONFIG_NET_ETHERNET is not set
488
489#
490# Ethernet (1000 Mbit)
491#
492# CONFIG_ACENIC is not set
493# CONFIG_DL2K is not set
494CONFIG_E1000=y
495CONFIG_E1000_NAPI=y
496# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
497# CONFIG_NS83820 is not set
498# CONFIG_HAMACHI is not set
499# CONFIG_YELLOWFIN is not set
500# CONFIG_R8169 is not set
501# CONFIG_SK98LIN is not set
502# CONFIG_TIGON3 is not set
503
504#
505# Ethernet (10000 Mbit)
506#
507# CONFIG_IXGB is not set
508# CONFIG_S2IO is not set
509
510#
511# Token Ring devices
512#
513# CONFIG_TR is not set
514
515#
516# Wireless LAN (non-hamradio)
517#
518# CONFIG_NET_RADIO is not set
519
520#
521# Wan interfaces
522#
523# CONFIG_WAN is not set
524# CONFIG_FDDI is not set
525# CONFIG_HIPPI is not set
526# CONFIG_PPP is not set
527# CONFIG_SLIP is not set
528# CONFIG_NET_FC is not set
529# CONFIG_SHAPER is not set
530# CONFIG_NETCONSOLE is not set
531
532#
533# ISDN subsystem
534#
535# CONFIG_ISDN is not set
536
537#
538# Input device support
539#
540CONFIG_INPUT=y
541
542#
543# Userland interfaces
544#
545CONFIG_INPUT_MOUSEDEV=y
546# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
547CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
548CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
549# CONFIG_INPUT_JOYDEV is not set
550# CONFIG_INPUT_TSDEV is not set
551# CONFIG_INPUT_EVDEV is not set
552# CONFIG_INPUT_EVBUG is not set
553
554#
555# Input Device Drivers
556#
557# CONFIG_INPUT_KEYBOARD is not set
558# CONFIG_INPUT_MOUSE is not set
559# CONFIG_INPUT_JOYSTICK is not set
560# CONFIG_INPUT_TOUCHSCREEN is not set
561# CONFIG_INPUT_MISC is not set
562
563#
564# Hardware I/O ports
565#
566# CONFIG_SERIO is not set
567# CONFIG_GAMEPORT is not set
568CONFIG_SOUND_GAMEPORT=y
569
570#
571# Character devices
572#
573CONFIG_VT=y
574CONFIG_VT_CONSOLE=y
575CONFIG_HW_CONSOLE=y
576# CONFIG_SERIAL_NONSTANDARD is not set
577
578#
579# Serial drivers
580#
581CONFIG_SERIAL_8250=y
582CONFIG_SERIAL_8250_CONSOLE=y
583CONFIG_SERIAL_8250_NR_UARTS=4
584# CONFIG_SERIAL_8250_EXTENDED is not set
585
586#
587# Non-8250 serial port support
588#
589CONFIG_SERIAL_CORE=y
590CONFIG_SERIAL_CORE_CONSOLE=y
591CONFIG_UNIX98_PTYS=y
592CONFIG_LEGACY_PTYS=y
593CONFIG_LEGACY_PTY_COUNT=256
594
595#
596# IPMI
597#
598# CONFIG_IPMI_HANDLER is not set
599
600#
601# Watchdog Cards
602#
603# CONFIG_WATCHDOG is not set
604# CONFIG_NVRAM is not set
605# CONFIG_RTC is not set
606# CONFIG_DTLK is not set
607# CONFIG_R3964 is not set
608# CONFIG_APPLICOM is not set
609
610#
611# Ftape, the floppy tape device driver
612#
613# CONFIG_DRM is not set
614# CONFIG_RAW_DRIVER is not set
615
616#
617# TPM devices
618#
619# CONFIG_TCG_TPM is not set
620
621#
622# I2C support
623#
624CONFIG_I2C=y
625CONFIG_I2C_CHARDEV=y
626
627#
628# I2C Algorithms
629#
630# CONFIG_I2C_ALGOBIT is not set
631# CONFIG_I2C_ALGOPCF is not set
632# CONFIG_I2C_ALGOPCA is not set
633
634#
635# I2C Hardware Bus support
636#
637# CONFIG_I2C_ALI1535 is not set
638# CONFIG_I2C_ALI1563 is not set
639# CONFIG_I2C_ALI15X3 is not set
640# CONFIG_I2C_AMD756 is not set
641# CONFIG_I2C_AMD8111 is not set
642# CONFIG_I2C_I801 is not set
643# CONFIG_I2C_I810 is not set
644CONFIG_I2C_IOP3XX=y
645# CONFIG_I2C_ISA is not set
646# CONFIG_I2C_NFORCE2 is not set
647# CONFIG_I2C_PARPORT_LIGHT is not set
648# CONFIG_I2C_PIIX4 is not set
649# CONFIG_I2C_PROSAVAGE is not set
650# CONFIG_I2C_SAVAGE4 is not set
651# CONFIG_SCx200_ACB is not set
652# CONFIG_I2C_SIS5595 is not set
653# CONFIG_I2C_SIS630 is not set
654# CONFIG_I2C_SIS96X is not set
655# CONFIG_I2C_STUB is not set
656# CONFIG_I2C_VIA is not set
657# CONFIG_I2C_VIAPRO is not set
658# CONFIG_I2C_VOODOO3 is not set
659# CONFIG_I2C_PCA_ISA is not set
660
661#
662# Hardware Sensors Chip support
663#
664# CONFIG_I2C_SENSOR is not set
665# CONFIG_SENSORS_ADM1021 is not set
666# CONFIG_SENSORS_ADM1025 is not set
667# CONFIG_SENSORS_ADM1026 is not set
668# CONFIG_SENSORS_ADM1031 is not set
669# CONFIG_SENSORS_ASB100 is not set
670# CONFIG_SENSORS_DS1621 is not set
671# CONFIG_SENSORS_FSCHER is not set
672# CONFIG_SENSORS_FSCPOS is not set
673# CONFIG_SENSORS_GL518SM is not set
674# CONFIG_SENSORS_GL520SM is not set
675# CONFIG_SENSORS_IT87 is not set
676# CONFIG_SENSORS_LM63 is not set
677# CONFIG_SENSORS_LM75 is not set
678# CONFIG_SENSORS_LM77 is not set
679# CONFIG_SENSORS_LM78 is not set
680# CONFIG_SENSORS_LM80 is not set
681# CONFIG_SENSORS_LM83 is not set
682# CONFIG_SENSORS_LM85 is not set
683# CONFIG_SENSORS_LM87 is not set
684# CONFIG_SENSORS_LM90 is not set
685# CONFIG_SENSORS_MAX1619 is not set
686# CONFIG_SENSORS_PC87360 is not set
687# CONFIG_SENSORS_SMSC47B397 is not set
688# CONFIG_SENSORS_SIS5595 is not set
689# CONFIG_SENSORS_SMSC47M1 is not set
690# CONFIG_SENSORS_VIA686A is not set
691# CONFIG_SENSORS_W83781D is not set
692# CONFIG_SENSORS_W83L785TS is not set
693# CONFIG_SENSORS_W83627HF is not set
694
695#
696# Other I2C Chip support
697#
698# CONFIG_SENSORS_EEPROM is not set
699# CONFIG_SENSORS_PCF8574 is not set
700# CONFIG_SENSORS_PCF8591 is not set
701# CONFIG_SENSORS_RTC8564 is not set
702# CONFIG_I2C_DEBUG_CORE is not set
703# CONFIG_I2C_DEBUG_ALGO is not set
704# CONFIG_I2C_DEBUG_BUS is not set
705# CONFIG_I2C_DEBUG_CHIP is not set
706
707#
708# Misc devices
709#
710
711#
712# Multimedia devices
713#
714# CONFIG_VIDEO_DEV is not set
715
716#
717# Digital Video Broadcasting Devices
718#
719# CONFIG_DVB is not set
720
721#
722# Graphics support
723#
724# CONFIG_FB is not set
725
726#
727# Console display driver support
728#
729# CONFIG_VGA_CONSOLE is not set
730CONFIG_DUMMY_CONSOLE=y
731
732#
733# Sound
734#
735# CONFIG_SOUND is not set
736
737#
738# USB support
739#
740CONFIG_USB_ARCH_HAS_HCD=y
741CONFIG_USB_ARCH_HAS_OHCI=y
742# CONFIG_USB is not set
743
744#
745# USB Gadget Support
746#
747# CONFIG_USB_GADGET is not set
748
749#
750# MMC/SD Card support
751#
752# CONFIG_MMC is not set
753
754#
755# File systems
756#
757CONFIG_EXT2_FS=y
758# CONFIG_EXT2_FS_XATTR is not set
759CONFIG_EXT3_FS=y
760CONFIG_EXT3_FS_XATTR=y
761# CONFIG_EXT3_FS_POSIX_ACL is not set
762# CONFIG_EXT3_FS_SECURITY is not set
763CONFIG_JBD=y
764# CONFIG_JBD_DEBUG is not set
765CONFIG_FS_MBCACHE=y
766# CONFIG_REISERFS_FS is not set
767# CONFIG_JFS_FS is not set
768
769#
770# XFS support
771#
772CONFIG_XFS_FS=y
773CONFIG_XFS_EXPORT=y
774# CONFIG_XFS_RT is not set
775# CONFIG_XFS_QUOTA is not set
776CONFIG_XFS_SECURITY=y
777CONFIG_XFS_POSIX_ACL=y
778# CONFIG_MINIX_FS is not set
779# CONFIG_ROMFS_FS is not set
780# CONFIG_QUOTA is not set
781CONFIG_DNOTIFY=y
782# CONFIG_AUTOFS_FS is not set
783# CONFIG_AUTOFS4_FS is not set
784
785#
786# CD-ROM/DVD Filesystems
787#
788# CONFIG_ISO9660_FS is not set
789# CONFIG_UDF_FS is not set
790
791#
792# DOS/FAT/NT Filesystems
793#
794# CONFIG_MSDOS_FS is not set
795# CONFIG_VFAT_FS is not set
796# CONFIG_NTFS_FS is not set
797
798#
799# Pseudo filesystems
800#
801CONFIG_PROC_FS=y
802CONFIG_SYSFS=y
803# CONFIG_DEVFS_FS is not set
804# CONFIG_DEVPTS_FS_XATTR is not set
805CONFIG_TMPFS=y
806# CONFIG_TMPFS_XATTR is not set
807# CONFIG_HUGETLB_PAGE is not set
808CONFIG_RAMFS=y
809
810#
811# Miscellaneous filesystems
812#
813# CONFIG_ADFS_FS is not set
814# CONFIG_AFFS_FS is not set
815# CONFIG_HFS_FS is not set
816# CONFIG_HFSPLUS_FS is not set
817# CONFIG_BEFS_FS is not set
818# CONFIG_BFS_FS is not set
819# CONFIG_EFS_FS is not set
820# CONFIG_JFFS_FS is not set
821CONFIG_JFFS2_FS=y
822CONFIG_JFFS2_FS_DEBUG=0
823# CONFIG_JFFS2_FS_NAND is not set
824# CONFIG_JFFS2_FS_NOR_ECC is not set
825# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
826CONFIG_JFFS2_ZLIB=y
827CONFIG_JFFS2_RTIME=y
828# CONFIG_JFFS2_RUBIN is not set
829# CONFIG_CRAMFS is not set
830# CONFIG_VXFS_FS is not set
831# CONFIG_HPFS_FS is not set
832# CONFIG_QNX4FS_FS is not set
833# CONFIG_SYSV_FS is not set
834# CONFIG_UFS_FS is not set
835
836#
837# Network File Systems
838#
839CONFIG_NFS_FS=y
840CONFIG_NFS_V3=y
841# CONFIG_NFS_V4 is not set
842# CONFIG_NFS_DIRECTIO is not set
843CONFIG_NFSD=y
844CONFIG_NFSD_V3=y
845# CONFIG_NFSD_V4 is not set
846# CONFIG_NFSD_TCP is not set
847CONFIG_ROOT_NFS=y
848CONFIG_LOCKD=y
849CONFIG_LOCKD_V4=y
850CONFIG_EXPORTFS=y
851CONFIG_SUNRPC=y
852# CONFIG_RPCSEC_GSS_KRB5 is not set
853# CONFIG_RPCSEC_GSS_SPKM3 is not set
854# CONFIG_SMB_FS is not set
855# CONFIG_CIFS is not set
856# CONFIG_NCP_FS is not set
857# CONFIG_CODA_FS is not set
858# CONFIG_AFS_FS is not set
859
860#
861# Partition Types
862#
863CONFIG_PARTITION_ADVANCED=y
864# CONFIG_ACORN_PARTITION is not set
865# CONFIG_OSF_PARTITION is not set
866# CONFIG_AMIGA_PARTITION is not set
867# CONFIG_ATARI_PARTITION is not set
868# CONFIG_MAC_PARTITION is not set
869CONFIG_MSDOS_PARTITION=y
870# CONFIG_BSD_DISKLABEL is not set
871# CONFIG_MINIX_SUBPARTITION is not set
872# CONFIG_SOLARIS_X86_PARTITION is not set
873# CONFIG_UNIXWARE_DISKLABEL is not set
874# CONFIG_LDM_PARTITION is not set
875# CONFIG_SGI_PARTITION is not set
876# CONFIG_ULTRIX_PARTITION is not set
877# CONFIG_SUN_PARTITION is not set
878# CONFIG_EFI_PARTITION is not set
879
880#
881# Native Language Support
882#
883# CONFIG_NLS is not set
884
885#
886# Profiling support
887#
888# CONFIG_PROFILING is not set
889
890#
891# Kernel hacking
892#
893# CONFIG_PRINTK_TIME is not set
894# CONFIG_DEBUG_KERNEL is not set
895CONFIG_LOG_BUF_SHIFT=14
896CONFIG_DEBUG_BUGVERBOSE=y
897CONFIG_FRAME_POINTER=y
898CONFIG_DEBUG_USER=y
899
900#
901# Security options
902#
903# CONFIG_KEYS is not set
904# CONFIG_SECURITY is not set
905
906#
907# Cryptographic options
908#
909# CONFIG_CRYPTO is not set
910
911#
912# Hardware crypto devices
913#
914
915#
916# Library routines
917#
918# CONFIG_CRC_CCITT is not set
919CONFIG_CRC32=y
920# CONFIG_LIBCRC32C is not set
921CONFIG_ZLIB_INFLATE=y
922CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/arm/configs/iq80321_defconfig b/arch/arm/configs/iq80321_defconfig
deleted file mode 100644
index b000da753c41..000000000000
--- a/arch/arm/configs/iq80321_defconfig
+++ /dev/null
@@ -1,843 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc1-bk2
4# Sun Mar 27 13:24:10 2005
5#
6CONFIG_ARM=y
7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y
11CONFIG_GENERIC_IOMAP=y
12
13#
14# Code maturity level options
15#
16CONFIG_EXPERIMENTAL=y
17CONFIG_CLEAN_COMPILE=y
18CONFIG_BROKEN_ON_SMP=y
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION=""
24CONFIG_SWAP=y
25CONFIG_SYSVIPC=y
26# CONFIG_POSIX_MQUEUE is not set
27CONFIG_BSD_PROCESS_ACCT=y
28# CONFIG_BSD_PROCESS_ACCT_V3 is not set
29CONFIG_SYSCTL=y
30# CONFIG_AUDIT is not set
31# CONFIG_HOTPLUG is not set
32CONFIG_KOBJECT_UEVENT=y
33# CONFIG_IKCONFIG is not set
34# CONFIG_EMBEDDED is not set
35CONFIG_KALLSYMS=y
36# CONFIG_KALLSYMS_EXTRA_PASS is not set
37CONFIG_BASE_FULL=y
38CONFIG_FUTEX=y
39CONFIG_EPOLL=y
40CONFIG_CC_OPTIMIZE_FOR_SIZE=y
41CONFIG_SHMEM=y
42CONFIG_CC_ALIGN_FUNCTIONS=0
43CONFIG_CC_ALIGN_LABELS=0
44CONFIG_CC_ALIGN_LOOPS=0
45CONFIG_CC_ALIGN_JUMPS=0
46# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0
48
49#
50# Loadable module support
51#
52CONFIG_MODULES=y
53CONFIG_MODULE_UNLOAD=y
54# CONFIG_MODULE_FORCE_UNLOAD is not set
55CONFIG_OBSOLETE_MODPARM=y
56# CONFIG_MODVERSIONS is not set
57# CONFIG_MODULE_SRCVERSION_ALL is not set
58CONFIG_KMOD=y
59
60#
61# System Type
62#
63# CONFIG_ARCH_CLPS7500 is not set
64# CONFIG_ARCH_CLPS711X is not set
65# CONFIG_ARCH_CO285 is not set
66# CONFIG_ARCH_EBSA110 is not set
67# CONFIG_ARCH_FOOTBRIDGE is not set
68# CONFIG_ARCH_INTEGRATOR is not set
69CONFIG_ARCH_IOP3XX=y
70# CONFIG_ARCH_IXP4XX is not set
71# CONFIG_ARCH_IXP2000 is not set
72# CONFIG_ARCH_L7200 is not set
73# CONFIG_ARCH_PXA is not set
74# CONFIG_ARCH_RPC is not set
75# CONFIG_ARCH_SA1100 is not set
76# CONFIG_ARCH_S3C2410 is not set
77# CONFIG_ARCH_SHARK is not set
78# CONFIG_ARCH_LH7A40X is not set
79# CONFIG_ARCH_OMAP is not set
80# CONFIG_ARCH_VERSATILE is not set
81# CONFIG_ARCH_IMX is not set
82# CONFIG_ARCH_H720X is not set
83
84#
85# IOP3xx Implementation Options
86#
87
88#
89# IOP3xx Platform Types
90#
91CONFIG_ARCH_IQ80321=y
92# CONFIG_ARCH_IQ31244 is not set
93# CONFIG_ARCH_IQ80331 is not set
94# CONFIG_MACH_IQ80332 is not set
95# CONFIG_ARCH_EP80219 is not set
96CONFIG_ARCH_IOP321=y
97# CONFIG_ARCH_IOP331 is not set
98
99#
100# IOP3xx Chipset Features
101#
102
103#
104# Processor Type
105#
106CONFIG_CPU_32=y
107CONFIG_CPU_XSCALE=y
108CONFIG_CPU_32v5=y
109CONFIG_CPU_ABRT_EV5T=y
110CONFIG_CPU_CACHE_VIVT=y
111CONFIG_CPU_TLB_V4WBI=y
112CONFIG_CPU_MINICACHE=y
113
114#
115# Processor Features
116#
117# CONFIG_ARM_THUMB is not set
118CONFIG_XSCALE_PMU=y
119
120#
121# Bus support
122#
123CONFIG_PCI=y
124# CONFIG_PCI_LEGACY_PROC is not set
125CONFIG_PCI_NAMES=y
126
127#
128# PCCARD (PCMCIA/CardBus) support
129#
130# CONFIG_PCCARD is not set
131
132#
133# Kernel Features
134#
135# CONFIG_PREEMPT is not set
136CONFIG_ALIGNMENT_TRAP=y
137
138#
139# Boot options
140#
141CONFIG_ZBOOT_ROM_TEXT=0x0
142CONFIG_ZBOOT_ROM_BSS=0x0
143CONFIG_CMDLINE="ip=boot root=nfs console=ttyS0,115200"
144# CONFIG_XIP_KERNEL is not set
145
146#
147# Floating point emulation
148#
149
150#
151# At least one emulation must be selected
152#
153CONFIG_FPE_NWFPE=y
154# CONFIG_FPE_NWFPE_XP is not set
155# CONFIG_FPE_FASTFPE is not set
156
157#
158# Userspace binary formats
159#
160CONFIG_BINFMT_ELF=y
161CONFIG_BINFMT_AOUT=y
162# CONFIG_BINFMT_MISC is not set
163# CONFIG_ARTHUR is not set
164
165#
166# Power management options
167#
168# CONFIG_PM is not set
169
170#
171# Device Drivers
172#
173
174#
175# Generic Driver Options
176#
177CONFIG_STANDALONE=y
178CONFIG_PREVENT_FIRMWARE_BUILD=y
179# CONFIG_FW_LOADER is not set
180
181#
182# Memory Technology Devices (MTD)
183#
184CONFIG_MTD=y
185# CONFIG_MTD_DEBUG is not set
186# CONFIG_MTD_CONCAT is not set
187CONFIG_MTD_PARTITIONS=y
188CONFIG_MTD_REDBOOT_PARTS=y
189CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
190CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
191CONFIG_MTD_REDBOOT_PARTS_READONLY=y
192# CONFIG_MTD_CMDLINE_PARTS is not set
193# CONFIG_MTD_AFS_PARTS is not set
194
195#
196# User Modules And Translation Layers
197#
198CONFIG_MTD_CHAR=y
199CONFIG_MTD_BLOCK=y
200# CONFIG_FTL is not set
201# CONFIG_NFTL is not set
202# CONFIG_INFTL is not set
203
204#
205# RAM/ROM/Flash chip drivers
206#
207CONFIG_MTD_CFI=y
208# CONFIG_MTD_JEDECPROBE is not set
209CONFIG_MTD_GEN_PROBE=y
210# CONFIG_MTD_CFI_ADV_OPTIONS is not set
211CONFIG_MTD_MAP_BANK_WIDTH_1=y
212CONFIG_MTD_MAP_BANK_WIDTH_2=y
213CONFIG_MTD_MAP_BANK_WIDTH_4=y
214# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
215# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
216# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
217CONFIG_MTD_CFI_I1=y
218CONFIG_MTD_CFI_I2=y
219# CONFIG_MTD_CFI_I4 is not set
220# CONFIG_MTD_CFI_I8 is not set
221CONFIG_MTD_CFI_INTELEXT=y
222# CONFIG_MTD_CFI_AMDSTD is not set
223# CONFIG_MTD_CFI_STAA is not set
224CONFIG_MTD_CFI_UTIL=y
225# CONFIG_MTD_RAM is not set
226# CONFIG_MTD_ROM is not set
227# CONFIG_MTD_ABSENT is not set
228# CONFIG_MTD_XIP is not set
229
230#
231# Mapping drivers for chip access
232#
233# CONFIG_MTD_COMPLEX_MAPPINGS is not set
234CONFIG_MTD_PHYSMAP=y
235CONFIG_MTD_PHYSMAP_START=0xf0000000
236CONFIG_MTD_PHYSMAP_LEN=0x00800000
237CONFIG_MTD_PHYSMAP_BANKWIDTH=1
238# CONFIG_MTD_ARM_INTEGRATOR is not set
239# CONFIG_MTD_EDB7312 is not set
240
241#
242# Self-contained MTD device drivers
243#
244# CONFIG_MTD_PMC551 is not set
245# CONFIG_MTD_SLRAM is not set
246# CONFIG_MTD_PHRAM is not set
247# CONFIG_MTD_MTDRAM is not set
248# CONFIG_MTD_BLKMTD is not set
249# CONFIG_MTD_BLOCK2MTD is not set
250
251#
252# Disk-On-Chip Device Drivers
253#
254# CONFIG_MTD_DOC2000 is not set
255# CONFIG_MTD_DOC2001 is not set
256# CONFIG_MTD_DOC2001PLUS is not set
257
258#
259# NAND Flash Device Drivers
260#
261# CONFIG_MTD_NAND is not set
262
263#
264# Parallel port support
265#
266# CONFIG_PARPORT is not set
267
268#
269# Plug and Play support
270#
271
272#
273# Block devices
274#
275# CONFIG_BLK_DEV_FD is not set
276# CONFIG_BLK_CPQ_DA is not set
277# CONFIG_BLK_CPQ_CISS_DA is not set
278# CONFIG_BLK_DEV_DAC960 is not set
279# CONFIG_BLK_DEV_UMEM is not set
280# CONFIG_BLK_DEV_COW_COMMON is not set
281# CONFIG_BLK_DEV_LOOP is not set
282# CONFIG_BLK_DEV_NBD is not set
283# CONFIG_BLK_DEV_SX8 is not set
284CONFIG_BLK_DEV_RAM=y
285CONFIG_BLK_DEV_RAM_COUNT=16
286CONFIG_BLK_DEV_RAM_SIZE=8192
287# CONFIG_BLK_DEV_INITRD is not set
288CONFIG_INITRAMFS_SOURCE=""
289# CONFIG_CDROM_PKTCDVD is not set
290
291#
292# IO Schedulers
293#
294CONFIG_IOSCHED_NOOP=y
295CONFIG_IOSCHED_AS=y
296CONFIG_IOSCHED_DEADLINE=y
297CONFIG_IOSCHED_CFQ=y
298# CONFIG_ATA_OVER_ETH is not set
299
300#
301# ATA/ATAPI/MFM/RLL support
302#
303# CONFIG_IDE is not set
304
305#
306# SCSI device support
307#
308# CONFIG_SCSI is not set
309
310#
311# Multi-device support (RAID and LVM)
312#
313# CONFIG_MD is not set
314
315#
316# Fusion MPT device support
317#
318
319#
320# IEEE 1394 (FireWire) support
321#
322# CONFIG_IEEE1394 is not set
323
324#
325# I2O device support
326#
327# CONFIG_I2O is not set
328
329#
330# Networking support
331#
332CONFIG_NET=y
333
334#
335# Networking options
336#
337CONFIG_PACKET=y
338CONFIG_PACKET_MMAP=y
339# CONFIG_NETLINK_DEV is not set
340CONFIG_UNIX=y
341# CONFIG_NET_KEY is not set
342CONFIG_INET=y
343CONFIG_IP_MULTICAST=y
344# CONFIG_IP_ADVANCED_ROUTER is not set
345CONFIG_IP_PNP=y
346# CONFIG_IP_PNP_DHCP is not set
347CONFIG_IP_PNP_BOOTP=y
348# CONFIG_IP_PNP_RARP is not set
349# CONFIG_NET_IPIP is not set
350# CONFIG_NET_IPGRE is not set
351# CONFIG_IP_MROUTE is not set
352# CONFIG_ARPD is not set
353# CONFIG_SYN_COOKIES is not set
354# CONFIG_INET_AH is not set
355# CONFIG_INET_ESP is not set
356# CONFIG_INET_IPCOMP is not set
357# CONFIG_INET_TUNNEL is not set
358CONFIG_IP_TCPDIAG=y
359# CONFIG_IP_TCPDIAG_IPV6 is not set
360# CONFIG_IPV6 is not set
361# CONFIG_NETFILTER is not set
362
363#
364# SCTP Configuration (EXPERIMENTAL)
365#
366# CONFIG_IP_SCTP is not set
367# CONFIG_ATM is not set
368# CONFIG_BRIDGE is not set
369# CONFIG_VLAN_8021Q is not set
370# CONFIG_DECNET is not set
371# CONFIG_LLC2 is not set
372# CONFIG_IPX is not set
373# CONFIG_ATALK is not set
374# CONFIG_X25 is not set
375# CONFIG_LAPB is not set
376# CONFIG_NET_DIVERT is not set
377# CONFIG_ECONET is not set
378# CONFIG_WAN_ROUTER is not set
379
380#
381# QoS and/or fair queueing
382#
383# CONFIG_NET_SCHED is not set
384# CONFIG_NET_CLS_ROUTE is not set
385
386#
387# Network testing
388#
389# CONFIG_NET_PKTGEN is not set
390# CONFIG_NETPOLL is not set
391# CONFIG_NET_POLL_CONTROLLER is not set
392# CONFIG_HAMRADIO is not set
393# CONFIG_IRDA is not set
394# CONFIG_BT is not set
395CONFIG_NETDEVICES=y
396# CONFIG_DUMMY is not set
397# CONFIG_BONDING is not set
398# CONFIG_EQUALIZER is not set
399# CONFIG_TUN is not set
400
401#
402# ARCnet devices
403#
404# CONFIG_ARCNET is not set
405
406#
407# Ethernet (10 or 100Mbit)
408#
409# CONFIG_NET_ETHERNET is not set
410
411#
412# Ethernet (1000 Mbit)
413#
414# CONFIG_ACENIC is not set
415# CONFIG_DL2K is not set
416CONFIG_E1000=y
417CONFIG_E1000_NAPI=y
418# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
419# CONFIG_NS83820 is not set
420# CONFIG_HAMACHI is not set
421# CONFIG_YELLOWFIN is not set
422# CONFIG_R8169 is not set
423# CONFIG_SK98LIN is not set
424# CONFIG_TIGON3 is not set
425
426#
427# Ethernet (10000 Mbit)
428#
429# CONFIG_IXGB is not set
430# CONFIG_S2IO is not set
431
432#
433# Token Ring devices
434#
435# CONFIG_TR is not set
436
437#
438# Wireless LAN (non-hamradio)
439#
440# CONFIG_NET_RADIO is not set
441
442#
443# Wan interfaces
444#
445# CONFIG_WAN is not set
446# CONFIG_FDDI is not set
447# CONFIG_HIPPI is not set
448# CONFIG_PPP is not set
449# CONFIG_SLIP is not set
450# CONFIG_SHAPER is not set
451# CONFIG_NETCONSOLE is not set
452
453#
454# ISDN subsystem
455#
456# CONFIG_ISDN is not set
457
458#
459# Input device support
460#
461CONFIG_INPUT=y
462
463#
464# Userland interfaces
465#
466CONFIG_INPUT_MOUSEDEV=y
467# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
468CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
469CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
470# CONFIG_INPUT_JOYDEV is not set
471# CONFIG_INPUT_TSDEV is not set
472# CONFIG_INPUT_EVDEV is not set
473# CONFIG_INPUT_EVBUG is not set
474
475#
476# Input Device Drivers
477#
478# CONFIG_INPUT_KEYBOARD is not set
479# CONFIG_INPUT_MOUSE is not set
480# CONFIG_INPUT_JOYSTICK is not set
481# CONFIG_INPUT_TOUCHSCREEN is not set
482# CONFIG_INPUT_MISC is not set
483
484#
485# Hardware I/O ports
486#
487# CONFIG_SERIO is not set
488# CONFIG_GAMEPORT is not set
489CONFIG_SOUND_GAMEPORT=y
490
491#
492# Character devices
493#
494CONFIG_VT=y
495CONFIG_VT_CONSOLE=y
496CONFIG_HW_CONSOLE=y
497# CONFIG_SERIAL_NONSTANDARD is not set
498
499#
500# Serial drivers
501#
502CONFIG_SERIAL_8250=y
503CONFIG_SERIAL_8250_CONSOLE=y
504CONFIG_SERIAL_8250_NR_UARTS=4
505# CONFIG_SERIAL_8250_EXTENDED is not set
506
507#
508# Non-8250 serial port support
509#
510CONFIG_SERIAL_CORE=y
511CONFIG_SERIAL_CORE_CONSOLE=y
512CONFIG_UNIX98_PTYS=y
513CONFIG_LEGACY_PTYS=y
514CONFIG_LEGACY_PTY_COUNT=256
515
516#
517# IPMI
518#
519# CONFIG_IPMI_HANDLER is not set
520
521#
522# Watchdog Cards
523#
524# CONFIG_WATCHDOG is not set
525# CONFIG_NVRAM is not set
526# CONFIG_RTC is not set
527# CONFIG_DTLK is not set
528# CONFIG_R3964 is not set
529# CONFIG_APPLICOM is not set
530
531#
532# Ftape, the floppy tape device driver
533#
534# CONFIG_DRM is not set
535# CONFIG_RAW_DRIVER is not set
536
537#
538# TPM devices
539#
540# CONFIG_TCG_TPM is not set
541
542#
543# I2C support
544#
545CONFIG_I2C=y
546CONFIG_I2C_CHARDEV=y
547
548#
549# I2C Algorithms
550#
551# CONFIG_I2C_ALGOBIT is not set
552# CONFIG_I2C_ALGOPCF is not set
553# CONFIG_I2C_ALGOPCA is not set
554
555#
556# I2C Hardware Bus support
557#
558# CONFIG_I2C_ALI1535 is not set
559# CONFIG_I2C_ALI1563 is not set
560# CONFIG_I2C_ALI15X3 is not set
561# CONFIG_I2C_AMD756 is not set
562# CONFIG_I2C_AMD8111 is not set
563# CONFIG_I2C_I801 is not set
564# CONFIG_I2C_I810 is not set
565CONFIG_I2C_IOP3XX=y
566# CONFIG_I2C_ISA is not set
567# CONFIG_I2C_NFORCE2 is not set
568# CONFIG_I2C_PARPORT_LIGHT is not set
569# CONFIG_I2C_PIIX4 is not set
570# CONFIG_I2C_PROSAVAGE is not set
571# CONFIG_I2C_SAVAGE4 is not set
572# CONFIG_SCx200_ACB is not set
573# CONFIG_I2C_SIS5595 is not set
574# CONFIG_I2C_SIS630 is not set
575# CONFIG_I2C_SIS96X is not set
576# CONFIG_I2C_STUB is not set
577# CONFIG_I2C_VIA is not set
578# CONFIG_I2C_VIAPRO is not set
579# CONFIG_I2C_VOODOO3 is not set
580# CONFIG_I2C_PCA_ISA is not set
581
582#
583# Hardware Sensors Chip support
584#
585# CONFIG_I2C_SENSOR is not set
586# CONFIG_SENSORS_ADM1021 is not set
587# CONFIG_SENSORS_ADM1025 is not set
588# CONFIG_SENSORS_ADM1026 is not set
589# CONFIG_SENSORS_ADM1031 is not set
590# CONFIG_SENSORS_ASB100 is not set
591# CONFIG_SENSORS_DS1621 is not set
592# CONFIG_SENSORS_FSCHER is not set
593# CONFIG_SENSORS_FSCPOS is not set
594# CONFIG_SENSORS_GL518SM is not set
595# CONFIG_SENSORS_GL520SM is not set
596# CONFIG_SENSORS_IT87 is not set
597# CONFIG_SENSORS_LM63 is not set
598# CONFIG_SENSORS_LM75 is not set
599# CONFIG_SENSORS_LM77 is not set
600# CONFIG_SENSORS_LM78 is not set
601# CONFIG_SENSORS_LM80 is not set
602# CONFIG_SENSORS_LM83 is not set
603# CONFIG_SENSORS_LM85 is not set
604# CONFIG_SENSORS_LM87 is not set
605# CONFIG_SENSORS_LM90 is not set
606# CONFIG_SENSORS_MAX1619 is not set
607# CONFIG_SENSORS_PC87360 is not set
608# CONFIG_SENSORS_SMSC47B397 is not set
609# CONFIG_SENSORS_SIS5595 is not set
610# CONFIG_SENSORS_SMSC47M1 is not set
611# CONFIG_SENSORS_VIA686A is not set
612# CONFIG_SENSORS_W83781D is not set
613# CONFIG_SENSORS_W83L785TS is not set
614# CONFIG_SENSORS_W83627HF is not set
615
616#
617# Other I2C Chip support
618#
619# CONFIG_SENSORS_EEPROM is not set
620# CONFIG_SENSORS_PCF8574 is not set
621# CONFIG_SENSORS_PCF8591 is not set
622# CONFIG_SENSORS_RTC8564 is not set
623# CONFIG_I2C_DEBUG_CORE is not set
624# CONFIG_I2C_DEBUG_ALGO is not set
625# CONFIG_I2C_DEBUG_BUS is not set
626# CONFIG_I2C_DEBUG_CHIP is not set
627
628#
629# Misc devices
630#
631
632#
633# Multimedia devices
634#
635# CONFIG_VIDEO_DEV is not set
636
637#
638# Digital Video Broadcasting Devices
639#
640# CONFIG_DVB is not set
641
642#
643# Graphics support
644#
645# CONFIG_FB is not set
646
647#
648# Console display driver support
649#
650# CONFIG_VGA_CONSOLE is not set
651CONFIG_DUMMY_CONSOLE=y
652
653#
654# Sound
655#
656# CONFIG_SOUND is not set
657
658#
659# USB support
660#
661CONFIG_USB_ARCH_HAS_HCD=y
662CONFIG_USB_ARCH_HAS_OHCI=y
663# CONFIG_USB is not set
664
665#
666# USB Gadget Support
667#
668# CONFIG_USB_GADGET is not set
669
670#
671# MMC/SD Card support
672#
673# CONFIG_MMC is not set
674
675#
676# File systems
677#
678CONFIG_EXT2_FS=y
679# CONFIG_EXT2_FS_XATTR is not set
680CONFIG_EXT3_FS=y
681CONFIG_EXT3_FS_XATTR=y
682# CONFIG_EXT3_FS_POSIX_ACL is not set
683# CONFIG_EXT3_FS_SECURITY is not set
684CONFIG_JBD=y
685# CONFIG_JBD_DEBUG is not set
686CONFIG_FS_MBCACHE=y
687# CONFIG_REISERFS_FS is not set
688# CONFIG_JFS_FS is not set
689
690#
691# XFS support
692#
693CONFIG_XFS_FS=y
694CONFIG_XFS_EXPORT=y
695# CONFIG_XFS_RT is not set
696# CONFIG_XFS_QUOTA is not set
697CONFIG_XFS_SECURITY=y
698CONFIG_XFS_POSIX_ACL=y
699# CONFIG_MINIX_FS is not set
700# CONFIG_ROMFS_FS is not set
701# CONFIG_QUOTA is not set
702CONFIG_DNOTIFY=y
703# CONFIG_AUTOFS_FS is not set
704# CONFIG_AUTOFS4_FS is not set
705
706#
707# CD-ROM/DVD Filesystems
708#
709# CONFIG_ISO9660_FS is not set
710# CONFIG_UDF_FS is not set
711
712#
713# DOS/FAT/NT Filesystems
714#
715# CONFIG_MSDOS_FS is not set
716# CONFIG_VFAT_FS is not set
717# CONFIG_NTFS_FS is not set
718
719#
720# Pseudo filesystems
721#
722CONFIG_PROC_FS=y
723CONFIG_SYSFS=y
724# CONFIG_DEVFS_FS is not set
725# CONFIG_DEVPTS_FS_XATTR is not set
726CONFIG_TMPFS=y
727# CONFIG_TMPFS_XATTR is not set
728# CONFIG_HUGETLB_PAGE is not set
729CONFIG_RAMFS=y
730
731#
732# Miscellaneous filesystems
733#
734# CONFIG_ADFS_FS is not set
735# CONFIG_AFFS_FS is not set
736# CONFIG_HFS_FS is not set
737# CONFIG_HFSPLUS_FS is not set
738# CONFIG_BEFS_FS is not set
739# CONFIG_BFS_FS is not set
740# CONFIG_EFS_FS is not set
741# CONFIG_JFFS_FS is not set
742CONFIG_JFFS2_FS=y
743CONFIG_JFFS2_FS_DEBUG=0
744# CONFIG_JFFS2_FS_NAND is not set
745# CONFIG_JFFS2_FS_NOR_ECC is not set
746# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
747CONFIG_JFFS2_ZLIB=y
748CONFIG_JFFS2_RTIME=y
749# CONFIG_JFFS2_RUBIN is not set
750# CONFIG_CRAMFS is not set
751# CONFIG_VXFS_FS is not set
752# CONFIG_HPFS_FS is not set
753# CONFIG_QNX4FS_FS is not set
754# CONFIG_SYSV_FS is not set
755# CONFIG_UFS_FS is not set
756
757#
758# Network File Systems
759#
760CONFIG_NFS_FS=y
761CONFIG_NFS_V3=y
762# CONFIG_NFS_V4 is not set
763# CONFIG_NFS_DIRECTIO is not set
764CONFIG_NFSD=y
765CONFIG_NFSD_V3=y
766# CONFIG_NFSD_V4 is not set
767# CONFIG_NFSD_TCP is not set
768CONFIG_ROOT_NFS=y
769CONFIG_LOCKD=y
770CONFIG_LOCKD_V4=y
771CONFIG_EXPORTFS=y
772CONFIG_SUNRPC=y
773# CONFIG_RPCSEC_GSS_KRB5 is not set
774# CONFIG_RPCSEC_GSS_SPKM3 is not set
775# CONFIG_SMB_FS is not set
776# CONFIG_CIFS is not set
777# CONFIG_NCP_FS is not set
778# CONFIG_CODA_FS is not set
779# CONFIG_AFS_FS is not set
780
781#
782# Partition Types
783#
784CONFIG_PARTITION_ADVANCED=y
785# CONFIG_ACORN_PARTITION is not set
786# CONFIG_OSF_PARTITION is not set
787# CONFIG_AMIGA_PARTITION is not set
788# CONFIG_ATARI_PARTITION is not set
789# CONFIG_MAC_PARTITION is not set
790CONFIG_MSDOS_PARTITION=y
791# CONFIG_BSD_DISKLABEL is not set
792# CONFIG_MINIX_SUBPARTITION is not set
793# CONFIG_SOLARIS_X86_PARTITION is not set
794# CONFIG_UNIXWARE_DISKLABEL is not set
795# CONFIG_LDM_PARTITION is not set
796# CONFIG_SGI_PARTITION is not set
797# CONFIG_ULTRIX_PARTITION is not set
798# CONFIG_SUN_PARTITION is not set
799# CONFIG_EFI_PARTITION is not set
800
801#
802# Native Language Support
803#
804# CONFIG_NLS is not set
805
806#
807# Profiling support
808#
809# CONFIG_PROFILING is not set
810
811#
812# Kernel hacking
813#
814# CONFIG_PRINTK_TIME is not set
815# CONFIG_DEBUG_KERNEL is not set
816CONFIG_LOG_BUF_SHIFT=14
817CONFIG_DEBUG_BUGVERBOSE=y
818CONFIG_FRAME_POINTER=y
819CONFIG_DEBUG_USER=y
820
821#
822# Security options
823#
824# CONFIG_KEYS is not set
825# CONFIG_SECURITY is not set
826
827#
828# Cryptographic options
829#
830# CONFIG_CRYPTO is not set
831
832#
833# Hardware crypto devices
834#
835
836#
837# Library routines
838#
839# CONFIG_CRC_CCITT is not set
840CONFIG_CRC32=y
841# CONFIG_LIBCRC32C is not set
842CONFIG_ZLIB_INFLATE=y
843CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/arm/configs/iq80331_defconfig b/arch/arm/configs/iq80331_defconfig
deleted file mode 100644
index 46c79e1efe07..000000000000
--- a/arch/arm/configs/iq80331_defconfig
+++ /dev/null
@@ -1,916 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc1-bk2
4# Sun Mar 27 15:13:37 2005
5#
6CONFIG_ARM=y
7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y
11CONFIG_GENERIC_IOMAP=y
12
13#
14# Code maturity level options
15#
16CONFIG_EXPERIMENTAL=y
17CONFIG_CLEAN_COMPILE=y
18CONFIG_BROKEN_ON_SMP=y
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION=""
24CONFIG_SWAP=y
25CONFIG_SYSVIPC=y
26# CONFIG_POSIX_MQUEUE is not set
27CONFIG_BSD_PROCESS_ACCT=y
28# CONFIG_BSD_PROCESS_ACCT_V3 is not set
29CONFIG_SYSCTL=y
30# CONFIG_AUDIT is not set
31# CONFIG_HOTPLUG is not set
32CONFIG_KOBJECT_UEVENT=y
33# CONFIG_IKCONFIG is not set
34# CONFIG_EMBEDDED is not set
35CONFIG_KALLSYMS=y
36# CONFIG_KALLSYMS_EXTRA_PASS is not set
37CONFIG_BASE_FULL=y
38CONFIG_FUTEX=y
39CONFIG_EPOLL=y
40CONFIG_CC_OPTIMIZE_FOR_SIZE=y
41CONFIG_SHMEM=y
42CONFIG_CC_ALIGN_FUNCTIONS=0
43CONFIG_CC_ALIGN_LABELS=0
44CONFIG_CC_ALIGN_LOOPS=0
45CONFIG_CC_ALIGN_JUMPS=0
46# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0
48
49#
50# Loadable module support
51#
52CONFIG_MODULES=y
53CONFIG_MODULE_UNLOAD=y
54# CONFIG_MODULE_FORCE_UNLOAD is not set
55CONFIG_OBSOLETE_MODPARM=y
56# CONFIG_MODVERSIONS is not set
57# CONFIG_MODULE_SRCVERSION_ALL is not set
58CONFIG_KMOD=y
59
60#
61# System Type
62#
63# CONFIG_ARCH_CLPS7500 is not set
64# CONFIG_ARCH_CLPS711X is not set
65# CONFIG_ARCH_CO285 is not set
66# CONFIG_ARCH_EBSA110 is not set
67# CONFIG_ARCH_FOOTBRIDGE is not set
68# CONFIG_ARCH_INTEGRATOR is not set
69CONFIG_ARCH_IOP3XX=y
70# CONFIG_ARCH_IXP4XX is not set
71# CONFIG_ARCH_IXP2000 is not set
72# CONFIG_ARCH_L7200 is not set
73# CONFIG_ARCH_PXA is not set
74# CONFIG_ARCH_RPC is not set
75# CONFIG_ARCH_SA1100 is not set
76# CONFIG_ARCH_S3C2410 is not set
77# CONFIG_ARCH_SHARK is not set
78# CONFIG_ARCH_LH7A40X is not set
79# CONFIG_ARCH_OMAP is not set
80# CONFIG_ARCH_VERSATILE is not set
81# CONFIG_ARCH_IMX is not set
82# CONFIG_ARCH_H720X is not set
83
84#
85# IOP3xx Implementation Options
86#
87
88#
89# IOP3xx Platform Types
90#
91# CONFIG_ARCH_IQ80321 is not set
92# CONFIG_ARCH_IQ31244 is not set
93CONFIG_ARCH_IQ80331=y
94# CONFIG_MACH_IQ80332 is not set
95# CONFIG_ARCH_EP80219 is not set
96CONFIG_ARCH_IOP331=y
97
98#
99# IOP3xx Chipset Features
100#
101CONFIG_IOP331_STEPD=y
102
103#
104# Processor Type
105#
106CONFIG_CPU_32=y
107CONFIG_CPU_XSCALE=y
108CONFIG_CPU_32v5=y
109CONFIG_CPU_ABRT_EV5T=y
110CONFIG_CPU_CACHE_VIVT=y
111CONFIG_CPU_TLB_V4WBI=y
112CONFIG_CPU_MINICACHE=y
113
114#
115# Processor Features
116#
117# CONFIG_ARM_THUMB is not set
118CONFIG_XSCALE_PMU=y
119
120#
121# Bus support
122#
123CONFIG_PCI=y
124# CONFIG_PCI_LEGACY_PROC is not set
125CONFIG_PCI_NAMES=y
126
127#
128# PCCARD (PCMCIA/CardBus) support
129#
130# CONFIG_PCCARD is not set
131
132#
133# Kernel Features
134#
135# CONFIG_PREEMPT is not set
136CONFIG_ALIGNMENT_TRAP=y
137
138#
139# Boot options
140#
141CONFIG_ZBOOT_ROM_TEXT=0x0
142CONFIG_ZBOOT_ROM_BSS=0x0
143CONFIG_CMDLINE="ip=boot root=nfs console=ttyS0,115200"
144# CONFIG_XIP_KERNEL is not set
145
146#
147# Floating point emulation
148#
149
150#
151# At least one emulation must be selected
152#
153CONFIG_FPE_NWFPE=y
154# CONFIG_FPE_NWFPE_XP is not set
155# CONFIG_FPE_FASTFPE is not set
156
157#
158# Userspace binary formats
159#
160CONFIG_BINFMT_ELF=y
161CONFIG_BINFMT_AOUT=y
162# CONFIG_BINFMT_MISC is not set
163# CONFIG_ARTHUR is not set
164
165#
166# Power management options
167#
168# CONFIG_PM is not set
169
170#
171# Device Drivers
172#
173
174#
175# Generic Driver Options
176#
177CONFIG_STANDALONE=y
178CONFIG_PREVENT_FIRMWARE_BUILD=y
179# CONFIG_FW_LOADER is not set
180
181#
182# Memory Technology Devices (MTD)
183#
184CONFIG_MTD=y
185# CONFIG_MTD_DEBUG is not set
186# CONFIG_MTD_CONCAT is not set
187CONFIG_MTD_PARTITIONS=y
188CONFIG_MTD_REDBOOT_PARTS=y
189CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
190CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
191CONFIG_MTD_REDBOOT_PARTS_READONLY=y
192# CONFIG_MTD_CMDLINE_PARTS is not set
193# CONFIG_MTD_AFS_PARTS is not set
194
195#
196# User Modules And Translation Layers
197#
198CONFIG_MTD_CHAR=y
199CONFIG_MTD_BLOCK=y
200# CONFIG_FTL is not set
201# CONFIG_NFTL is not set
202# CONFIG_INFTL is not set
203
204#
205# RAM/ROM/Flash chip drivers
206#
207CONFIG_MTD_CFI=y
208# CONFIG_MTD_JEDECPROBE is not set
209CONFIG_MTD_GEN_PROBE=y
210CONFIG_MTD_CFI_ADV_OPTIONS=y
211CONFIG_MTD_CFI_NOSWAP=y
212# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
213# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
214# CONFIG_MTD_CFI_GEOMETRY is not set
215CONFIG_MTD_MAP_BANK_WIDTH_1=y
216CONFIG_MTD_MAP_BANK_WIDTH_2=y
217CONFIG_MTD_MAP_BANK_WIDTH_4=y
218# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
219# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
220# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
221CONFIG_MTD_CFI_I1=y
222CONFIG_MTD_CFI_I2=y
223# CONFIG_MTD_CFI_I4 is not set
224# CONFIG_MTD_CFI_I8 is not set
225CONFIG_MTD_CFI_INTELEXT=y
226# CONFIG_MTD_CFI_AMDSTD is not set
227# CONFIG_MTD_CFI_STAA is not set
228CONFIG_MTD_CFI_UTIL=y
229# CONFIG_MTD_RAM is not set
230# CONFIG_MTD_ROM is not set
231# CONFIG_MTD_ABSENT is not set
232# CONFIG_MTD_XIP is not set
233
234#
235# Mapping drivers for chip access
236#
237# CONFIG_MTD_COMPLEX_MAPPINGS is not set
238CONFIG_MTD_PHYSMAP=y
239CONFIG_MTD_PHYSMAP_START=0xc0000000
240CONFIG_MTD_PHYSMAP_LEN=0x00800000
241CONFIG_MTD_PHYSMAP_BANKWIDTH=1
242# CONFIG_MTD_ARM_INTEGRATOR is not set
243# CONFIG_MTD_EDB7312 is not set
244
245#
246# Self-contained MTD device drivers
247#
248# CONFIG_MTD_PMC551 is not set
249# CONFIG_MTD_SLRAM is not set
250# CONFIG_MTD_PHRAM is not set
251# CONFIG_MTD_MTDRAM is not set
252# CONFIG_MTD_BLKMTD is not set
253# CONFIG_MTD_BLOCK2MTD is not set
254
255#
256# Disk-On-Chip Device Drivers
257#
258# CONFIG_MTD_DOC2000 is not set
259# CONFIG_MTD_DOC2001 is not set
260# CONFIG_MTD_DOC2001PLUS is not set
261
262#
263# NAND Flash Device Drivers
264#
265# CONFIG_MTD_NAND is not set
266
267#
268# Parallel port support
269#
270# CONFIG_PARPORT is not set
271
272#
273# Plug and Play support
274#
275
276#
277# Block devices
278#
279# CONFIG_BLK_DEV_FD is not set
280# CONFIG_BLK_CPQ_DA is not set
281# CONFIG_BLK_CPQ_CISS_DA is not set
282# CONFIG_BLK_DEV_DAC960 is not set
283# CONFIG_BLK_DEV_UMEM is not set
284# CONFIG_BLK_DEV_COW_COMMON is not set
285# CONFIG_BLK_DEV_LOOP is not set
286# CONFIG_BLK_DEV_NBD is not set
287# CONFIG_BLK_DEV_SX8 is not set
288CONFIG_BLK_DEV_RAM=y
289CONFIG_BLK_DEV_RAM_COUNT=16
290CONFIG_BLK_DEV_RAM_SIZE=8192
291# CONFIG_BLK_DEV_INITRD is not set
292CONFIG_INITRAMFS_SOURCE=""
293# CONFIG_CDROM_PKTCDVD is not set
294
295#
296# IO Schedulers
297#
298CONFIG_IOSCHED_NOOP=y
299CONFIG_IOSCHED_AS=y
300CONFIG_IOSCHED_DEADLINE=y
301CONFIG_IOSCHED_CFQ=y
302# CONFIG_ATA_OVER_ETH is not set
303
304#
305# ATA/ATAPI/MFM/RLL support
306#
307# CONFIG_IDE is not set
308
309#
310# SCSI device support
311#
312CONFIG_SCSI=y
313CONFIG_SCSI_PROC_FS=y
314
315#
316# SCSI support type (disk, tape, CD-ROM)
317#
318CONFIG_BLK_DEV_SD=y
319# CONFIG_CHR_DEV_ST is not set
320# CONFIG_CHR_DEV_OSST is not set
321# CONFIG_BLK_DEV_SR is not set
322CONFIG_CHR_DEV_SG=y
323
324#
325# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
326#
327# CONFIG_SCSI_MULTI_LUN is not set
328# CONFIG_SCSI_CONSTANTS is not set
329# CONFIG_SCSI_LOGGING is not set
330
331#
332# SCSI Transport Attributes
333#
334# CONFIG_SCSI_SPI_ATTRS is not set
335# CONFIG_SCSI_FC_ATTRS is not set
336# CONFIG_SCSI_ISCSI_ATTRS is not set
337
338#
339# SCSI low-level drivers
340#
341# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
342# CONFIG_SCSI_3W_9XXX is not set
343# CONFIG_SCSI_ACARD is not set
344# CONFIG_SCSI_AACRAID is not set
345# CONFIG_SCSI_AIC7XXX is not set
346# CONFIG_SCSI_AIC7XXX_OLD is not set
347# CONFIG_SCSI_AIC79XX is not set
348# CONFIG_SCSI_DPT_I2O is not set
349# CONFIG_MEGARAID_NEWGEN is not set
350# CONFIG_MEGARAID_LEGACY is not set
351# CONFIG_SCSI_SATA is not set
352# CONFIG_SCSI_BUSLOGIC is not set
353# CONFIG_SCSI_DMX3191D is not set
354# CONFIG_SCSI_EATA is not set
355# CONFIG_SCSI_FUTURE_DOMAIN is not set
356# CONFIG_SCSI_GDTH is not set
357# CONFIG_SCSI_IPS is not set
358# CONFIG_SCSI_INITIO is not set
359# CONFIG_SCSI_INIA100 is not set
360# CONFIG_SCSI_SYM53C8XX_2 is not set
361# CONFIG_SCSI_IPR is not set
362# CONFIG_SCSI_QLOGIC_FC is not set
363# CONFIG_SCSI_QLOGIC_1280 is not set
364CONFIG_SCSI_QLA2XXX=y
365# CONFIG_SCSI_QLA21XX is not set
366# CONFIG_SCSI_QLA22XX is not set
367# CONFIG_SCSI_QLA2300 is not set
368# CONFIG_SCSI_QLA2322 is not set
369# CONFIG_SCSI_QLA6312 is not set
370# CONFIG_SCSI_DC395x is not set
371# CONFIG_SCSI_DC390T is not set
372# CONFIG_SCSI_NSP32 is not set
373# CONFIG_SCSI_DEBUG is not set
374
375#
376# Multi-device support (RAID and LVM)
377#
378CONFIG_MD=y
379CONFIG_BLK_DEV_MD=y
380CONFIG_MD_LINEAR=y
381CONFIG_MD_RAID0=y
382CONFIG_MD_RAID1=y
383# CONFIG_MD_RAID10 is not set
384CONFIG_MD_RAID5=y
385# CONFIG_MD_RAID6 is not set
386# CONFIG_MD_MULTIPATH is not set
387# CONFIG_MD_FAULTY is not set
388CONFIG_BLK_DEV_DM=y
389# CONFIG_DM_CRYPT is not set
390# CONFIG_DM_SNAPSHOT is not set
391# CONFIG_DM_MIRROR is not set
392# CONFIG_DM_ZERO is not set
393# CONFIG_DM_MULTIPATH is not set
394
395#
396# Fusion MPT device support
397#
398# CONFIG_FUSION is not set
399
400#
401# IEEE 1394 (FireWire) support
402#
403# CONFIG_IEEE1394 is not set
404
405#
406# I2O device support
407#
408# CONFIG_I2O is not set
409
410#
411# Networking support
412#
413CONFIG_NET=y
414
415#
416# Networking options
417#
418CONFIG_PACKET=y
419CONFIG_PACKET_MMAP=y
420# CONFIG_NETLINK_DEV is not set
421CONFIG_UNIX=y
422# CONFIG_NET_KEY is not set
423CONFIG_INET=y
424CONFIG_IP_MULTICAST=y
425# CONFIG_IP_ADVANCED_ROUTER is not set
426CONFIG_IP_PNP=y
427# CONFIG_IP_PNP_DHCP is not set
428CONFIG_IP_PNP_BOOTP=y
429# CONFIG_IP_PNP_RARP is not set
430# CONFIG_NET_IPIP is not set
431# CONFIG_NET_IPGRE is not set
432# CONFIG_IP_MROUTE is not set
433# CONFIG_ARPD is not set
434# CONFIG_SYN_COOKIES is not set
435# CONFIG_INET_AH is not set
436# CONFIG_INET_ESP is not set
437# CONFIG_INET_IPCOMP is not set
438# CONFIG_INET_TUNNEL is not set
439CONFIG_IP_TCPDIAG=y
440# CONFIG_IP_TCPDIAG_IPV6 is not set
441# CONFIG_IPV6 is not set
442# CONFIG_NETFILTER is not set
443
444#
445# SCTP Configuration (EXPERIMENTAL)
446#
447# CONFIG_IP_SCTP is not set
448# CONFIG_ATM is not set
449# CONFIG_BRIDGE is not set
450# CONFIG_VLAN_8021Q is not set
451# CONFIG_DECNET is not set
452# CONFIG_LLC2 is not set
453# CONFIG_IPX is not set
454# CONFIG_ATALK is not set
455# CONFIG_X25 is not set
456# CONFIG_LAPB is not set
457# CONFIG_NET_DIVERT is not set
458# CONFIG_ECONET is not set
459# CONFIG_WAN_ROUTER is not set
460
461#
462# QoS and/or fair queueing
463#
464# CONFIG_NET_SCHED is not set
465# CONFIG_NET_CLS_ROUTE is not set
466
467#
468# Network testing
469#
470# CONFIG_NET_PKTGEN is not set
471# CONFIG_NETPOLL is not set
472# CONFIG_NET_POLL_CONTROLLER is not set
473# CONFIG_HAMRADIO is not set
474# CONFIG_IRDA is not set
475# CONFIG_BT is not set
476CONFIG_NETDEVICES=y
477# CONFIG_DUMMY is not set
478# CONFIG_BONDING is not set
479# CONFIG_EQUALIZER is not set
480# CONFIG_TUN is not set
481
482#
483# ARCnet devices
484#
485# CONFIG_ARCNET is not set
486
487#
488# Ethernet (10 or 100Mbit)
489#
490# CONFIG_NET_ETHERNET is not set
491
492#
493# Ethernet (1000 Mbit)
494#
495# CONFIG_ACENIC is not set
496# CONFIG_DL2K is not set
497CONFIG_E1000=y
498CONFIG_E1000_NAPI=y
499# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
500# CONFIG_NS83820 is not set
501# CONFIG_HAMACHI is not set
502# CONFIG_YELLOWFIN is not set
503# CONFIG_R8169 is not set
504# CONFIG_SK98LIN is not set
505# CONFIG_TIGON3 is not set
506
507#
508# Ethernet (10000 Mbit)
509#
510# CONFIG_IXGB is not set
511# CONFIG_S2IO is not set
512
513#
514# Token Ring devices
515#
516# CONFIG_TR is not set
517
518#
519# Wireless LAN (non-hamradio)
520#
521# CONFIG_NET_RADIO is not set
522
523#
524# Wan interfaces
525#
526# CONFIG_WAN is not set
527# CONFIG_FDDI is not set
528# CONFIG_HIPPI is not set
529# CONFIG_PPP is not set
530# CONFIG_SLIP is not set
531# CONFIG_NET_FC is not set
532# CONFIG_SHAPER is not set
533# CONFIG_NETCONSOLE is not set
534
535#
536# ISDN subsystem
537#
538# CONFIG_ISDN is not set
539
540#
541# Input device support
542#
543CONFIG_INPUT=y
544
545#
546# Userland interfaces
547#
548CONFIG_INPUT_MOUSEDEV=y
549# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
550CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
551CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
552# CONFIG_INPUT_JOYDEV is not set
553# CONFIG_INPUT_TSDEV is not set
554# CONFIG_INPUT_EVDEV is not set
555# CONFIG_INPUT_EVBUG is not set
556
557#
558# Input Device Drivers
559#
560# CONFIG_INPUT_KEYBOARD is not set
561# CONFIG_INPUT_MOUSE is not set
562# CONFIG_INPUT_JOYSTICK is not set
563# CONFIG_INPUT_TOUCHSCREEN is not set
564# CONFIG_INPUT_MISC is not set
565
566#
567# Hardware I/O ports
568#
569# CONFIG_SERIO is not set
570# CONFIG_GAMEPORT is not set
571CONFIG_SOUND_GAMEPORT=y
572
573#
574# Character devices
575#
576CONFIG_VT=y
577CONFIG_VT_CONSOLE=y
578CONFIG_HW_CONSOLE=y
579# CONFIG_SERIAL_NONSTANDARD is not set
580
581#
582# Serial drivers
583#
584CONFIG_SERIAL_8250=y
585CONFIG_SERIAL_8250_CONSOLE=y
586CONFIG_SERIAL_8250_NR_UARTS=4
587# CONFIG_SERIAL_8250_EXTENDED is not set
588
589#
590# Non-8250 serial port support
591#
592CONFIG_SERIAL_CORE=y
593CONFIG_SERIAL_CORE_CONSOLE=y
594CONFIG_UNIX98_PTYS=y
595CONFIG_LEGACY_PTYS=y
596CONFIG_LEGACY_PTY_COUNT=256
597
598#
599# IPMI
600#
601# CONFIG_IPMI_HANDLER is not set
602
603#
604# Watchdog Cards
605#
606# CONFIG_WATCHDOG is not set
607# CONFIG_NVRAM is not set
608# CONFIG_RTC is not set
609# CONFIG_DTLK is not set
610# CONFIG_R3964 is not set
611# CONFIG_APPLICOM is not set
612
613#
614# Ftape, the floppy tape device driver
615#
616# CONFIG_DRM is not set
617# CONFIG_RAW_DRIVER is not set
618
619#
620# TPM devices
621#
622# CONFIG_TCG_TPM is not set
623
624#
625# I2C support
626#
627CONFIG_I2C=y
628CONFIG_I2C_CHARDEV=y
629
630#
631# I2C Algorithms
632#
633# CONFIG_I2C_ALGOBIT is not set
634# CONFIG_I2C_ALGOPCF is not set
635# CONFIG_I2C_ALGOPCA is not set
636
637#
638# I2C Hardware Bus support
639#
640# CONFIG_I2C_ALI1535 is not set
641# CONFIG_I2C_ALI1563 is not set
642# CONFIG_I2C_ALI15X3 is not set
643# CONFIG_I2C_AMD756 is not set
644# CONFIG_I2C_AMD8111 is not set
645# CONFIG_I2C_I801 is not set
646# CONFIG_I2C_I810 is not set
647CONFIG_I2C_IOP3XX=y
648# CONFIG_I2C_ISA is not set
649# CONFIG_I2C_NFORCE2 is not set
650# CONFIG_I2C_PARPORT_LIGHT is not set
651# CONFIG_I2C_PIIX4 is not set
652# CONFIG_I2C_PROSAVAGE is not set
653# CONFIG_I2C_SAVAGE4 is not set
654# CONFIG_SCx200_ACB is not set
655# CONFIG_I2C_SIS5595 is not set
656# CONFIG_I2C_SIS630 is not set
657# CONFIG_I2C_SIS96X is not set
658# CONFIG_I2C_STUB is not set
659# CONFIG_I2C_VIA is not set
660# CONFIG_I2C_VIAPRO is not set
661# CONFIG_I2C_VOODOO3 is not set
662# CONFIG_I2C_PCA_ISA is not set
663
664#
665# Hardware Sensors Chip support
666#
667# CONFIG_I2C_SENSOR is not set
668# CONFIG_SENSORS_ADM1021 is not set
669# CONFIG_SENSORS_ADM1025 is not set
670# CONFIG_SENSORS_ADM1026 is not set
671# CONFIG_SENSORS_ADM1031 is not set
672# CONFIG_SENSORS_ASB100 is not set
673# CONFIG_SENSORS_DS1621 is not set
674# CONFIG_SENSORS_FSCHER is not set
675# CONFIG_SENSORS_FSCPOS is not set
676# CONFIG_SENSORS_GL518SM is not set
677# CONFIG_SENSORS_GL520SM is not set
678# CONFIG_SENSORS_IT87 is not set
679# CONFIG_SENSORS_LM63 is not set
680# CONFIG_SENSORS_LM75 is not set
681# CONFIG_SENSORS_LM77 is not set
682# CONFIG_SENSORS_LM78 is not set
683# CONFIG_SENSORS_LM80 is not set
684# CONFIG_SENSORS_LM83 is not set
685# CONFIG_SENSORS_LM85 is not set
686# CONFIG_SENSORS_LM87 is not set
687# CONFIG_SENSORS_LM90 is not set
688# CONFIG_SENSORS_MAX1619 is not set
689# CONFIG_SENSORS_PC87360 is not set
690# CONFIG_SENSORS_SMSC47B397 is not set
691# CONFIG_SENSORS_SIS5595 is not set
692# CONFIG_SENSORS_SMSC47M1 is not set
693# CONFIG_SENSORS_VIA686A is not set
694# CONFIG_SENSORS_W83781D is not set
695# CONFIG_SENSORS_W83L785TS is not set
696# CONFIG_SENSORS_W83627HF is not set
697
698#
699# Other I2C Chip support
700#
701# CONFIG_SENSORS_EEPROM is not set
702# CONFIG_SENSORS_PCF8574 is not set
703# CONFIG_SENSORS_PCF8591 is not set
704# CONFIG_SENSORS_RTC8564 is not set
705# CONFIG_I2C_DEBUG_CORE is not set
706# CONFIG_I2C_DEBUG_ALGO is not set
707# CONFIG_I2C_DEBUG_BUS is not set
708# CONFIG_I2C_DEBUG_CHIP is not set
709
710#
711# Misc devices
712#
713
714#
715# Multimedia devices
716#
717# CONFIG_VIDEO_DEV is not set
718
719#
720# Digital Video Broadcasting Devices
721#
722# CONFIG_DVB is not set
723
724#
725# Graphics support
726#
727# CONFIG_FB is not set
728
729#
730# Console display driver support
731#
732# CONFIG_VGA_CONSOLE is not set
733CONFIG_DUMMY_CONSOLE=y
734
735#
736# Sound
737#
738# CONFIG_SOUND is not set
739
740#
741# USB support
742#
743CONFIG_USB_ARCH_HAS_HCD=y
744CONFIG_USB_ARCH_HAS_OHCI=y
745# CONFIG_USB is not set
746
747#
748# USB Gadget Support
749#
750# CONFIG_USB_GADGET is not set
751
752#
753# MMC/SD Card support
754#
755# CONFIG_MMC is not set
756
757#
758# File systems
759#
760CONFIG_EXT2_FS=y
761# CONFIG_EXT2_FS_XATTR is not set
762CONFIG_EXT3_FS=y
763CONFIG_EXT3_FS_XATTR=y
764# CONFIG_EXT3_FS_POSIX_ACL is not set
765# CONFIG_EXT3_FS_SECURITY is not set
766CONFIG_JBD=y
767# CONFIG_JBD_DEBUG is not set
768CONFIG_FS_MBCACHE=y
769# CONFIG_REISERFS_FS is not set
770# CONFIG_JFS_FS is not set
771
772#
773# XFS support
774#
775CONFIG_XFS_FS=y
776CONFIG_XFS_EXPORT=y
777# CONFIG_XFS_RT is not set
778# CONFIG_XFS_QUOTA is not set
779CONFIG_XFS_SECURITY=y
780CONFIG_XFS_POSIX_ACL=y
781# CONFIG_MINIX_FS is not set
782# CONFIG_ROMFS_FS is not set
783# CONFIG_QUOTA is not set
784CONFIG_DNOTIFY=y
785# CONFIG_AUTOFS_FS is not set
786# CONFIG_AUTOFS4_FS is not set
787
788#
789# CD-ROM/DVD Filesystems
790#
791# CONFIG_ISO9660_FS is not set
792# CONFIG_UDF_FS is not set
793
794#
795# DOS/FAT/NT Filesystems
796#
797# CONFIG_MSDOS_FS is not set
798# CONFIG_VFAT_FS is not set
799# CONFIG_NTFS_FS is not set
800
801#
802# Pseudo filesystems
803#
804CONFIG_PROC_FS=y
805CONFIG_SYSFS=y
806# CONFIG_DEVFS_FS is not set
807# CONFIG_DEVPTS_FS_XATTR is not set
808CONFIG_TMPFS=y
809# CONFIG_TMPFS_XATTR is not set
810# CONFIG_HUGETLB_PAGE is not set
811CONFIG_RAMFS=y
812
813#
814# Miscellaneous filesystems
815#
816# CONFIG_ADFS_FS is not set
817# CONFIG_AFFS_FS is not set
818# CONFIG_HFS_FS is not set
819# CONFIG_HFSPLUS_FS is not set
820# CONFIG_BEFS_FS is not set
821# CONFIG_BFS_FS is not set
822# CONFIG_EFS_FS is not set
823# CONFIG_JFFS_FS is not set
824# CONFIG_JFFS2_FS is not set
825# CONFIG_CRAMFS is not set
826# CONFIG_VXFS_FS is not set
827# CONFIG_HPFS_FS is not set
828# CONFIG_QNX4FS_FS is not set
829# CONFIG_SYSV_FS is not set
830# CONFIG_UFS_FS is not set
831
832#
833# Network File Systems
834#
835CONFIG_NFS_FS=y
836CONFIG_NFS_V3=y
837# CONFIG_NFS_V4 is not set
838# CONFIG_NFS_DIRECTIO is not set
839CONFIG_NFSD=y
840CONFIG_NFSD_V3=y
841# CONFIG_NFSD_V4 is not set
842# CONFIG_NFSD_TCP is not set
843CONFIG_ROOT_NFS=y
844CONFIG_LOCKD=y
845CONFIG_LOCKD_V4=y
846CONFIG_EXPORTFS=y
847CONFIG_SUNRPC=y
848# CONFIG_RPCSEC_GSS_KRB5 is not set
849# CONFIG_RPCSEC_GSS_SPKM3 is not set
850# CONFIG_SMB_FS is not set
851# CONFIG_CIFS is not set
852# CONFIG_NCP_FS is not set
853# CONFIG_CODA_FS is not set
854# CONFIG_AFS_FS is not set
855
856#
857# Partition Types
858#
859CONFIG_PARTITION_ADVANCED=y
860# CONFIG_ACORN_PARTITION is not set
861# CONFIG_OSF_PARTITION is not set
862# CONFIG_AMIGA_PARTITION is not set
863# CONFIG_ATARI_PARTITION is not set
864# CONFIG_MAC_PARTITION is not set
865CONFIG_MSDOS_PARTITION=y
866# CONFIG_BSD_DISKLABEL is not set
867# CONFIG_MINIX_SUBPARTITION is not set
868# CONFIG_SOLARIS_X86_PARTITION is not set
869# CONFIG_UNIXWARE_DISKLABEL is not set
870# CONFIG_LDM_PARTITION is not set
871# CONFIG_SGI_PARTITION is not set
872# CONFIG_ULTRIX_PARTITION is not set
873# CONFIG_SUN_PARTITION is not set
874# CONFIG_EFI_PARTITION is not set
875
876#
877# Native Language Support
878#
879# CONFIG_NLS is not set
880
881#
882# Profiling support
883#
884# CONFIG_PROFILING is not set
885
886#
887# Kernel hacking
888#
889# CONFIG_PRINTK_TIME is not set
890# CONFIG_DEBUG_KERNEL is not set
891CONFIG_LOG_BUF_SHIFT=14
892CONFIG_DEBUG_BUGVERBOSE=y
893CONFIG_FRAME_POINTER=y
894CONFIG_DEBUG_USER=y
895
896#
897# Security options
898#
899# CONFIG_KEYS is not set
900# CONFIG_SECURITY is not set
901
902#
903# Cryptographic options
904#
905# CONFIG_CRYPTO is not set
906
907#
908# Hardware crypto devices
909#
910
911#
912# Library routines
913#
914# CONFIG_CRC_CCITT is not set
915# CONFIG_CRC32 is not set
916# CONFIG_LIBCRC32C is not set
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
index f20814e6f497..a83222641045 100644
--- a/arch/arm/configs/s3c2410_defconfig
+++ b/arch/arm/configs/s3c2410_defconfig
@@ -1,14 +1,19 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.17-git9 3# Linux kernel version: 2.6.18
4# Sun Jun 25 23:56:32 2006 4# Wed Sep 20 20:27:31 2006
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_MMU=y 7CONFIG_MMU=y
8CONFIG_GENERIC_HARDIRQS=y
9CONFIG_TRACE_IRQFLAGS_SUPPORT=y
10CONFIG_HARDIRQS_SW_RESEND=y
11CONFIG_GENERIC_IRQ_PROBE=y
8CONFIG_RWSEM_GENERIC_SPINLOCK=y 12CONFIG_RWSEM_GENERIC_SPINLOCK=y
9CONFIG_GENERIC_HWEIGHT=y 13CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 14CONFIG_GENERIC_CALIBRATE_DELAY=y
11CONFIG_VECTORS_BASE=0xffff0000 15CONFIG_VECTORS_BASE=0xffff0000
16CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
12 17
13# 18#
14# Code maturity level options 19# Code maturity level options
@@ -26,14 +31,15 @@ CONFIG_SWAP=y
26CONFIG_SYSVIPC=y 31CONFIG_SYSVIPC=y
27# CONFIG_POSIX_MQUEUE is not set 32# CONFIG_POSIX_MQUEUE is not set
28# CONFIG_BSD_PROCESS_ACCT is not set 33# CONFIG_BSD_PROCESS_ACCT is not set
29CONFIG_SYSCTL=y 34# CONFIG_TASKSTATS is not set
30# CONFIG_AUDIT is not set 35# CONFIG_AUDIT is not set
31# CONFIG_IKCONFIG is not set 36# CONFIG_IKCONFIG is not set
32# CONFIG_RELAY is not set 37# CONFIG_RELAY is not set
33CONFIG_INITRAMFS_SOURCE="" 38CONFIG_INITRAMFS_SOURCE=""
34CONFIG_UID16=y
35CONFIG_CC_OPTIMIZE_FOR_SIZE=y 39CONFIG_CC_OPTIMIZE_FOR_SIZE=y
36# CONFIG_EMBEDDED is not set 40# CONFIG_EMBEDDED is not set
41CONFIG_UID16=y
42CONFIG_SYSCTL=y
37CONFIG_KALLSYMS=y 43CONFIG_KALLSYMS=y
38# CONFIG_KALLSYMS_ALL is not set 44# CONFIG_KALLSYMS_ALL is not set
39# CONFIG_KALLSYMS_EXTRA_PASS is not set 45# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -46,6 +52,8 @@ CONFIG_FUTEX=y
46CONFIG_EPOLL=y 52CONFIG_EPOLL=y
47CONFIG_SHMEM=y 53CONFIG_SHMEM=y
48CONFIG_SLAB=y 54CONFIG_SLAB=y
55CONFIG_VM_EVENT_COUNTERS=y
56CONFIG_RT_MUTEXES=y
49# CONFIG_TINY_SHMEM is not set 57# CONFIG_TINY_SHMEM is not set
50CONFIG_BASE_SMALL=0 58CONFIG_BASE_SMALL=0
51# CONFIG_SLOB is not set 59# CONFIG_SLOB is not set
@@ -84,7 +92,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
84# CONFIG_ARCH_INTEGRATOR is not set 92# CONFIG_ARCH_INTEGRATOR is not set
85# CONFIG_ARCH_REALVIEW is not set 93# CONFIG_ARCH_REALVIEW is not set
86# CONFIG_ARCH_VERSATILE is not set 94# CONFIG_ARCH_VERSATILE is not set
87# CONFIG_ARCH_AT91RM9200 is not set 95# CONFIG_ARCH_AT91 is not set
88# CONFIG_ARCH_CLPS7500 is not set 96# CONFIG_ARCH_CLPS7500 is not set
89# CONFIG_ARCH_CLPS711X is not set 97# CONFIG_ARCH_CLPS711X is not set
90# CONFIG_ARCH_CO285 is not set 98# CONFIG_ARCH_CO285 is not set
@@ -94,7 +102,8 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
94# CONFIG_ARCH_NETX is not set 102# CONFIG_ARCH_NETX is not set
95# CONFIG_ARCH_H720X is not set 103# CONFIG_ARCH_H720X is not set
96# CONFIG_ARCH_IMX is not set 104# CONFIG_ARCH_IMX is not set
97# CONFIG_ARCH_IOP3XX is not set 105# CONFIG_ARCH_IOP32X is not set
106# CONFIG_ARCH_IOP33X is not set
98# CONFIG_ARCH_IXP4XX is not set 107# CONFIG_ARCH_IXP4XX is not set
99# CONFIG_ARCH_IXP2000 is not set 108# CONFIG_ARCH_IXP2000 is not set
100# CONFIG_ARCH_IXP23XX is not set 109# CONFIG_ARCH_IXP23XX is not set
@@ -122,13 +131,18 @@ CONFIG_ARCH_SMDK2410=y
122CONFIG_ARCH_S3C2440=y 131CONFIG_ARCH_S3C2440=y
123CONFIG_SMDK2440_CPU2440=y 132CONFIG_SMDK2440_CPU2440=y
124CONFIG_SMDK2440_CPU2442=y 133CONFIG_SMDK2440_CPU2442=y
134CONFIG_MACH_S3C2413=y
125CONFIG_MACH_SMDK2413=y 135CONFIG_MACH_SMDK2413=y
126CONFIG_MACH_VR1000=y 136CONFIG_MACH_VR1000=y
127CONFIG_MACH_RX3715=y 137CONFIG_MACH_RX3715=y
128CONFIG_MACH_OTOM=y 138CONFIG_MACH_OTOM=y
129CONFIG_MACH_NEXCODER_2440=y 139CONFIG_MACH_NEXCODER_2440=y
140CONFIG_MACH_VSTMS=y
130CONFIG_S3C2410_CLOCK=y 141CONFIG_S3C2410_CLOCK=y
142CONFIG_S3C2410_PM=y
143CONFIG_CPU_S3C2410_DMA=y
131CONFIG_CPU_S3C2410=y 144CONFIG_CPU_S3C2410=y
145CONFIG_S3C2412_PM=y
132CONFIG_CPU_S3C2412=y 146CONFIG_CPU_S3C2412=y
133CONFIG_CPU_S3C244X=y 147CONFIG_CPU_S3C244X=y
134CONFIG_CPU_S3C2440=y 148CONFIG_CPU_S3C2440=y
@@ -156,7 +170,7 @@ CONFIG_S3C2410_LOWLEVEL_UART_PORT=0
156CONFIG_CPU_32=y 170CONFIG_CPU_32=y
157CONFIG_CPU_ARM920T=y 171CONFIG_CPU_ARM920T=y
158CONFIG_CPU_ARM926T=y 172CONFIG_CPU_ARM926T=y
159CONFIG_CPU_32v4=y 173CONFIG_CPU_32v4T=y
160CONFIG_CPU_32v5=y 174CONFIG_CPU_32v5=y
161CONFIG_CPU_ABRT_EV4T=y 175CONFIG_CPU_ABRT_EV4T=y
162CONFIG_CPU_ABRT_EV5TJ=y 176CONFIG_CPU_ABRT_EV5TJ=y
@@ -200,6 +214,7 @@ CONFIG_FLATMEM=y
200CONFIG_FLAT_NODE_MEM_MAP=y 214CONFIG_FLAT_NODE_MEM_MAP=y
201# CONFIG_SPARSEMEM_STATIC is not set 215# CONFIG_SPARSEMEM_STATIC is not set
202CONFIG_SPLIT_PTLOCK_CPUS=4096 216CONFIG_SPLIT_PTLOCK_CPUS=4096
217# CONFIG_RESOURCES_64BIT is not set
203CONFIG_ALIGNMENT_TRAP=y 218CONFIG_ALIGNMENT_TRAP=y
204 219
205# 220#
@@ -304,7 +319,6 @@ CONFIG_TCP_CONG_BIC=y
304# CONFIG_ATALK is not set 319# CONFIG_ATALK is not set
305# CONFIG_X25 is not set 320# CONFIG_X25 is not set
306# CONFIG_LAPB is not set 321# CONFIG_LAPB is not set
307# CONFIG_NET_DIVERT is not set
308# CONFIG_ECONET is not set 322# CONFIG_ECONET is not set
309# CONFIG_WAN_ROUTER is not set 323# CONFIG_WAN_ROUTER is not set
310 324
@@ -460,6 +474,7 @@ CONFIG_BLK_DEV_NBD=m
460CONFIG_BLK_DEV_RAM=y 474CONFIG_BLK_DEV_RAM=y
461CONFIG_BLK_DEV_RAM_COUNT=16 475CONFIG_BLK_DEV_RAM_COUNT=16
462CONFIG_BLK_DEV_RAM_SIZE=4096 476CONFIG_BLK_DEV_RAM_SIZE=4096
477CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
463CONFIG_BLK_DEV_INITRD=y 478CONFIG_BLK_DEV_INITRD=y
464# CONFIG_CDROM_PKTCDVD is not set 479# CONFIG_CDROM_PKTCDVD is not set
465CONFIG_ATA_OVER_ETH=m 480CONFIG_ATA_OVER_ETH=m
@@ -640,6 +655,7 @@ CONFIG_SERIO_LIBPS2=y
640CONFIG_VT=y 655CONFIG_VT=y
641CONFIG_VT_CONSOLE=y 656CONFIG_VT_CONSOLE=y
642CONFIG_HW_CONSOLE=y 657CONFIG_HW_CONSOLE=y
658# CONFIG_VT_HW_CONSOLE_BINDING is not set
643CONFIG_SERIAL_NONSTANDARD=y 659CONFIG_SERIAL_NONSTANDARD=y
644# CONFIG_COMPUTONE is not set 660# CONFIG_COMPUTONE is not set
645# CONFIG_ROCKETPORT is not set 661# CONFIG_ROCKETPORT is not set
@@ -716,6 +732,7 @@ CONFIG_S3C2410_WATCHDOG=y
716# USB-based Watchdog Cards 732# USB-based Watchdog Cards
717# 733#
718# CONFIG_USBPCWATCHDOG is not set 734# CONFIG_USBPCWATCHDOG is not set
735CONFIG_HW_RANDOM=y
719# CONFIG_NVRAM is not set 736# CONFIG_NVRAM is not set
720CONFIG_S3C2410_RTC=y 737CONFIG_S3C2410_RTC=y
721# CONFIG_DTLK is not set 738# CONFIG_DTLK is not set
@@ -857,12 +874,12 @@ CONFIG_VIDEO_V4L2=y
857# 874#
858# Graphics support 875# Graphics support
859# 876#
877CONFIG_FIRMWARE_EDID=y
860CONFIG_FB=y 878CONFIG_FB=y
861CONFIG_FB_CFB_FILLRECT=y 879CONFIG_FB_CFB_FILLRECT=y
862CONFIG_FB_CFB_COPYAREA=y 880CONFIG_FB_CFB_COPYAREA=y
863CONFIG_FB_CFB_IMAGEBLIT=y 881CONFIG_FB_CFB_IMAGEBLIT=y
864# CONFIG_FB_MACMODES is not set 882# CONFIG_FB_MACMODES is not set
865CONFIG_FB_FIRMWARE_EDID=y
866# CONFIG_FB_BACKLIGHT is not set 883# CONFIG_FB_BACKLIGHT is not set
867CONFIG_FB_MODE_HELPERS=y 884CONFIG_FB_MODE_HELPERS=y
868# CONFIG_FB_TILEBLITTING is not set 885# CONFIG_FB_TILEBLITTING is not set
@@ -995,7 +1012,7 @@ CONFIG_USB_MON=y
995# CONFIG_USB_LEGOTOWER is not set 1012# CONFIG_USB_LEGOTOWER is not set
996# CONFIG_USB_LCD is not set 1013# CONFIG_USB_LCD is not set
997# CONFIG_USB_LED is not set 1014# CONFIG_USB_LED is not set
998# CONFIG_USB_CY7C63 is not set 1015# CONFIG_USB_CYPRESS_CY7C63 is not set
999# CONFIG_USB_CYTHERM is not set 1016# CONFIG_USB_CYTHERM is not set
1000# CONFIG_USB_PHIDGETKIT is not set 1017# CONFIG_USB_PHIDGETKIT is not set
1001# CONFIG_USB_PHIDGETSERVO is not set 1018# CONFIG_USB_PHIDGETSERVO is not set
@@ -1095,6 +1112,7 @@ CONFIG_JFFS2_FS=y
1095CONFIG_JFFS2_FS_DEBUG=0 1112CONFIG_JFFS2_FS_DEBUG=0
1096CONFIG_JFFS2_FS_WRITEBUFFER=y 1113CONFIG_JFFS2_FS_WRITEBUFFER=y
1097# CONFIG_JFFS2_SUMMARY is not set 1114# CONFIG_JFFS2_SUMMARY is not set
1115# CONFIG_JFFS2_FS_XATTR is not set
1098# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set 1116# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1099CONFIG_JFFS2_ZLIB=y 1117CONFIG_JFFS2_ZLIB=y
1100CONFIG_JFFS2_RTIME=y 1118CONFIG_JFFS2_RTIME=y
@@ -1202,14 +1220,19 @@ CONFIG_NLS_DEFAULT="iso8859-1"
1202# 1220#
1203# CONFIG_PRINTK_TIME is not set 1221# CONFIG_PRINTK_TIME is not set
1204CONFIG_MAGIC_SYSRQ=y 1222CONFIG_MAGIC_SYSRQ=y
1223# CONFIG_UNUSED_SYMBOLS is not set
1205CONFIG_DEBUG_KERNEL=y 1224CONFIG_DEBUG_KERNEL=y
1206CONFIG_LOG_BUF_SHIFT=16 1225CONFIG_LOG_BUF_SHIFT=16
1207CONFIG_DETECT_SOFTLOCKUP=y 1226CONFIG_DETECT_SOFTLOCKUP=y
1208# CONFIG_SCHEDSTATS is not set 1227# CONFIG_SCHEDSTATS is not set
1209# CONFIG_DEBUG_SLAB is not set 1228# CONFIG_DEBUG_SLAB is not set
1210CONFIG_DEBUG_MUTEXES=y 1229# CONFIG_DEBUG_RT_MUTEXES is not set
1230# CONFIG_RT_MUTEX_TESTER is not set
1211# CONFIG_DEBUG_SPINLOCK is not set 1231# CONFIG_DEBUG_SPINLOCK is not set
1232CONFIG_DEBUG_MUTEXES=y
1233# CONFIG_DEBUG_RWSEMS is not set
1212# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1234# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1235# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1213# CONFIG_DEBUG_KOBJECT is not set 1236# CONFIG_DEBUG_KOBJECT is not set
1214CONFIG_DEBUG_BUGVERBOSE=y 1237CONFIG_DEBUG_BUGVERBOSE=y
1215CONFIG_DEBUG_INFO=y 1238CONFIG_DEBUG_INFO=y
@@ -1251,3 +1274,4 @@ CONFIG_CRC32=y
1251# CONFIG_LIBCRC32C is not set 1274# CONFIG_LIBCRC32C is not set
1252CONFIG_ZLIB_INFLATE=y 1275CONFIG_ZLIB_INFLATE=y
1253CONFIG_ZLIB_DEFLATE=y 1276CONFIG_ZLIB_DEFLATE=y
1277CONFIG_PLIST=y
diff --git a/arch/arm/kernel/apm.c b/arch/arm/kernel/apm.c
index 33c55689f999..ecf4f9472d94 100644
--- a/arch/arm/kernel/apm.c
+++ b/arch/arm/kernel/apm.c
@@ -25,6 +25,7 @@
25#include <linux/list.h> 25#include <linux/list.h>
26#include <linux/init.h> 26#include <linux/init.h>
27#include <linux/completion.h> 27#include <linux/completion.h>
28#include <linux/kthread.h>
28 29
29#include <asm/apm.h> /* apm_power_info */ 30#include <asm/apm.h> /* apm_power_info */
30#include <asm/system.h> 31#include <asm/system.h>
@@ -80,7 +81,7 @@ struct apm_user {
80 */ 81 */
81static int suspends_pending; 82static int suspends_pending;
82static int apm_disabled; 83static int apm_disabled;
83static int arm_apm_active; 84static struct task_struct *kapmd_tsk;
84 85
85static DECLARE_WAIT_QUEUE_HEAD(apm_waitqueue); 86static DECLARE_WAIT_QUEUE_HEAD(apm_waitqueue);
86static DECLARE_WAIT_QUEUE_HEAD(apm_suspend_waitqueue); 87static DECLARE_WAIT_QUEUE_HEAD(apm_suspend_waitqueue);
@@ -97,7 +98,6 @@ static LIST_HEAD(apm_user_list);
97 * to be suspending the system. 98 * to be suspending the system.
98 */ 99 */
99static DECLARE_WAIT_QUEUE_HEAD(kapmd_wait); 100static DECLARE_WAIT_QUEUE_HEAD(kapmd_wait);
100static DECLARE_COMPLETION(kapmd_exit);
101static DEFINE_SPINLOCK(kapmd_queue_lock); 101static DEFINE_SPINLOCK(kapmd_queue_lock);
102static struct apm_queue kapmd_queue; 102static struct apm_queue kapmd_queue;
103 103
@@ -468,16 +468,13 @@ static int apm_get_info(char *buf, char **start, off_t fpos, int length)
468 468
469static int kapmd(void *arg) 469static int kapmd(void *arg)
470{ 470{
471 daemonize("kapmd");
472 current->flags |= PF_NOFREEZE;
473
474 do { 471 do {
475 apm_event_t event; 472 apm_event_t event;
476 473
477 wait_event_interruptible(kapmd_wait, 474 wait_event_interruptible(kapmd_wait,
478 !queue_empty(&kapmd_queue) || !arm_apm_active); 475 !queue_empty(&kapmd_queue) || kthread_should_stop());
479 476
480 if (!arm_apm_active) 477 if (kthread_should_stop())
481 break; 478 break;
482 479
483 spin_lock_irq(&kapmd_queue_lock); 480 spin_lock_irq(&kapmd_queue_lock);
@@ -508,7 +505,7 @@ static int kapmd(void *arg)
508 } 505 }
509 } while (1); 506 } while (1);
510 507
511 complete_and_exit(&kapmd_exit, 0); 508 return 0;
512} 509}
513 510
514static int __init apm_init(void) 511static int __init apm_init(void)
@@ -520,13 +517,14 @@ static int __init apm_init(void)
520 return -ENODEV; 517 return -ENODEV;
521 } 518 }
522 519
523 arm_apm_active = 1; 520 kapmd_tsk = kthread_create(kapmd, NULL, "kapmd");
524 521 if (IS_ERR(kapmd_tsk)) {
525 ret = kernel_thread(kapmd, NULL, CLONE_KERNEL); 522 ret = PTR_ERR(kapmd_tsk);
526 if (ret < 0) { 523 kapmd_tsk = NULL;
527 arm_apm_active = 0;
528 return ret; 524 return ret;
529 } 525 }
526 kapmd_tsk->flags |= PF_NOFREEZE;
527 wake_up_process(kapmd_tsk);
530 528
531#ifdef CONFIG_PROC_FS 529#ifdef CONFIG_PROC_FS
532 create_proc_info_entry("apm", 0, NULL, apm_get_info); 530 create_proc_info_entry("apm", 0, NULL, apm_get_info);
@@ -535,10 +533,7 @@ static int __init apm_init(void)
535 ret = misc_register(&apm_device); 533 ret = misc_register(&apm_device);
536 if (ret != 0) { 534 if (ret != 0) {
537 remove_proc_entry("apm", NULL); 535 remove_proc_entry("apm", NULL);
538 536 kthread_stop(kapmd_tsk);
539 arm_apm_active = 0;
540 wake_up(&kapmd_wait);
541 wait_for_completion(&kapmd_exit);
542 } 537 }
543 538
544 return ret; 539 return ret;
@@ -549,9 +544,7 @@ static void __exit apm_exit(void)
549 misc_deregister(&apm_device); 544 misc_deregister(&apm_device);
550 remove_proc_entry("apm", NULL); 545 remove_proc_entry("apm", NULL);
551 546
552 arm_apm_active = 0; 547 kthread_stop(kapmd_tsk);
553 wake_up(&kapmd_wait);
554 wait_for_completion(&kapmd_exit);
555} 548}
556 549
557module_init(apm_init); 550module_init(apm_init);
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index a5747e58a9dc..5617566477b4 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -21,6 +21,36 @@
21 21
22#if defined(CONFIG_DEBUG_ICEDCC) 22#if defined(CONFIG_DEBUG_ICEDCC)
23 @@ debug using ARM EmbeddedICE DCC channel 23 @@ debug using ARM EmbeddedICE DCC channel
24
25#if defined(CONFIG_CPU_V6)
26
27 .macro addruart, rx
28 .endm
29
30 .macro senduart, rd, rx
31 mcr p14, 0, \rd, c0, c5, 0
32 .endm
33
34 .macro busyuart, rd, rx
351001:
36 mrc p14, 0, \rx, c0, c1, 0
37 tst \rx, #0x20000000
38 beq 1001b
39 .endm
40
41 .macro waituart, rd, rx
42 mov \rd, #0x2000000
431001:
44 subs \rd, \rd, #1
45 bmi 1002f
46 mrc p14, 0, \rx, c0, c1, 0
47 tst \rx, #0x20000000
48 bne 1001b
491002:
50 .endm
51
52#else
53
24 .macro addruart, rx 54 .macro addruart, rx
25 .endm 55 .endm
26 56
@@ -46,9 +76,12 @@
46 bne 1001b 76 bne 1001b
471002: 771002:
48 .endm 78 .endm
79
80#endif /* CONFIG_CPU_V6 */
81
49#else 82#else
50#include <asm/arch/debug-macro.S> 83#include <asm/arch/debug-macro.S>
51#endif 84#endif /* CONFIG_DEBUG_ICEDCC */
52 85
53/* 86/*
54 * Useful debugging routines 87 * Useful debugging routines
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index de4e33137901..bd623b73445f 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -191,6 +191,9 @@ __dabt_svc:
191__irq_svc: 191__irq_svc:
192 svc_entry 192 svc_entry
193 193
194#ifdef CONFIG_TRACE_IRQFLAGS
195 bl trace_hardirqs_off
196#endif
194#ifdef CONFIG_PREEMPT 197#ifdef CONFIG_PREEMPT
195 get_thread_info tsk 198 get_thread_info tsk
196 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 199 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
@@ -211,6 +214,10 @@ preempt_return:
211#endif 214#endif
212 ldr r0, [sp, #S_PSR] @ irqs are already disabled 215 ldr r0, [sp, #S_PSR] @ irqs are already disabled
213 msr spsr_cxsf, r0 216 msr spsr_cxsf, r0
217#ifdef CONFIG_TRACE_IRQFLAGS
218 tst r0, #PSR_I_BIT
219 bleq trace_hardirqs_on
220#endif
214 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 221 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
215 222
216 .ltorg 223 .ltorg
@@ -398,6 +405,9 @@ __dabt_usr:
398__irq_usr: 405__irq_usr:
399 usr_entry 406 usr_entry
400 407
408#ifdef CONFIG_TRACE_IRQFLAGS
409 bl trace_hardirqs_off
410#endif
401 get_thread_info tsk 411 get_thread_info tsk
402#ifdef CONFIG_PREEMPT 412#ifdef CONFIG_PREEMPT
403 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 413 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
@@ -412,6 +422,9 @@ __irq_usr:
412 teq r0, r7 422 teq r0, r7
413 strne r0, [r0, -r0] 423 strne r0, [r0, -r0]
414#endif 424#endif
425#ifdef CONFIG_TRACE_IRQFLAGS
426 bl trace_hardirqs_on
427#endif
415 428
416 mov why, #0 429 mov why, #0
417 b ret_to_user 430 b ret_to_user
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index ac9eb3d30518..f359a189dcf2 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -9,7 +9,6 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 * 10 *
11 * Common kernel startup code (non-paged MM) 11 * Common kernel startup code (non-paged MM)
12 * for 32-bit CPUs which has a process ID register(CP15).
13 * 12 *
14 */ 13 */
15#include <linux/linkage.h> 14#include <linux/linkage.h>
@@ -40,7 +39,11 @@
40ENTRY(stext) 39ENTRY(stext)
41 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode 40 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
42 @ and irqs disabled 41 @ and irqs disabled
42#ifndef CONFIG_CPU_CP15
43 ldr r9, =CONFIG_PROCESSOR_ID
44#else
43 mrc p15, 0, r9, c0, c0 @ get processor id 45 mrc p15, 0, r9, c0, c0 @ get processor id
46#endif
44 bl __lookup_processor_type @ r5=procinfo r9=cpuid 47 bl __lookup_processor_type @ r5=procinfo r9=cpuid
45 movs r10, r5 @ invalid processor (r5=0)? 48 movs r10, r5 @ invalid processor (r5=0)?
46 beq __error_p @ yes, error 'p' 49 beq __error_p @ yes, error 'p'
@@ -58,6 +61,7 @@ ENTRY(stext)
58 */ 61 */
59 .type __after_proc_init, %function 62 .type __after_proc_init, %function
60__after_proc_init: 63__after_proc_init:
64#ifdef CONFIG_CPU_CP15
61 mrc p15, 0, r0, c1, c0, 0 @ read control reg 65 mrc p15, 0, r0, c1, c0, 0 @ read control reg
62#ifdef CONFIG_ALIGNMENT_TRAP 66#ifdef CONFIG_ALIGNMENT_TRAP
63 orr r0, r0, #CR_A 67 orr r0, r0, #CR_A
@@ -73,7 +77,13 @@ __after_proc_init:
73#ifdef CONFIG_CPU_ICACHE_DISABLE 77#ifdef CONFIG_CPU_ICACHE_DISABLE
74 bic r0, r0, #CR_I 78 bic r0, r0, #CR_I
75#endif 79#endif
80#ifdef CONFIG_CPU_HIGH_VECTOR
81 orr r0, r0, #CR_V
82#else
83 bic r0, r0, #CR_V
84#endif
76 mcr p15, 0, r0, c1, c0, 0 @ write control reg 85 mcr p15, 0, r0, c1, c0, 0 @ write control reg
86#endif /* CONFIG_CPU_CP15 */
77 87
78 mov pc, r13 @ clear the BSS and jump 88 mov pc, r13 @ clear the BSS and jump
79 @ to start_kernel 89 @ to start_kernel
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 298363d97047..1b061583408e 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -2,6 +2,7 @@
2 * linux/arch/arm/kernel/module.c 2 * linux/arch/arm/kernel/module.c
3 * 3 *
4 * Copyright (C) 2002 Russell King. 4 * Copyright (C) 2002 Russell King.
5 * Modified for nommu by Hyok S. Choi
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -32,6 +33,7 @@ extern void _etext;
32#define MODULE_START (((unsigned long)&_etext + ~PGDIR_MASK) & PGDIR_MASK) 33#define MODULE_START (((unsigned long)&_etext + ~PGDIR_MASK) & PGDIR_MASK)
33#endif 34#endif
34 35
36#ifdef CONFIG_MMU
35void *module_alloc(unsigned long size) 37void *module_alloc(unsigned long size)
36{ 38{
37 struct vm_struct *area; 39 struct vm_struct *area;
@@ -46,6 +48,12 @@ void *module_alloc(unsigned long size)
46 48
47 return __vmalloc_area(area, GFP_KERNEL, PAGE_KERNEL); 49 return __vmalloc_area(area, GFP_KERNEL, PAGE_KERNEL);
48} 50}
51#else /* CONFIG_MMU */
52void *module_alloc(unsigned long size)
53{
54 return size == 0 ? NULL : vmalloc(size);
55}
56#endif /* !CONFIG_MMU */
49 57
50void module_free(struct module *module, void *region) 58void module_free(struct module *module, void *region)
51{ 59{
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 3079535afccd..bf35c178a877 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -221,16 +221,26 @@ void __show_regs(struct pt_regs *regs)
221 processor_modes[processor_mode(regs)], 221 processor_modes[processor_mode(regs)],
222 thumb_mode(regs) ? " (T)" : "", 222 thumb_mode(regs) ? " (T)" : "",
223 get_fs() == get_ds() ? "kernel" : "user"); 223 get_fs() == get_ds() ? "kernel" : "user");
224#if CONFIG_CPU_CP15
224 { 225 {
225 unsigned int ctrl, transbase, dac; 226 unsigned int ctrl;
226 __asm__ ( 227 __asm__ (
227 " mrc p15, 0, %0, c1, c0\n" 228 " mrc p15, 0, %0, c1, c0\n"
228 " mrc p15, 0, %1, c2, c0\n" 229 : "=r" (ctrl));
229 " mrc p15, 0, %2, c3, c0\n" 230 printk("Control: %04X\n", ctrl);
230 : "=r" (ctrl), "=r" (transbase), "=r" (dac));
231 printk("Control: %04X Table: %08X DAC: %08X\n",
232 ctrl, transbase, dac);
233 } 231 }
232#ifdef CONFIG_CPU_CP15_MMU
233 {
234 unsigned int transbase, dac;
235 __asm__ (
236 " mrc p15, 0, %0, c2, c0\n"
237 " mrc p15, 0, %1, c3, c0\n"
238 : "=r" (transbase), "=r" (dac));
239 printk("Table: %08X DAC: %08X\n",
240 transbase, dac);
241 }
242#endif
243#endif
234} 244}
235 245
236void show_regs(struct pt_regs * regs) 246void show_regs(struct pt_regs * regs)
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index 09a67d771857..d4dceb5f06e9 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -69,10 +69,12 @@ EXPORT_SYMBOL(profile_pc);
69 */ 69 */
70int (*set_rtc)(void); 70int (*set_rtc)(void);
71 71
72#ifndef CONFIG_GENERIC_TIME
72static unsigned long dummy_gettimeoffset(void) 73static unsigned long dummy_gettimeoffset(void)
73{ 74{
74 return 0; 75 return 0;
75} 76}
77#endif
76 78
77/* 79/*
78 * Scheduler clock - returns current time in nanosec units. 80 * Scheduler clock - returns current time in nanosec units.
@@ -230,6 +232,7 @@ static inline void do_leds(void)
230#define do_leds() 232#define do_leds()
231#endif 233#endif
232 234
235#ifndef CONFIG_GENERIC_TIME
233void do_gettimeofday(struct timeval *tv) 236void do_gettimeofday(struct timeval *tv)
234{ 237{
235 unsigned long flags; 238 unsigned long flags;
@@ -291,6 +294,7 @@ int do_settimeofday(struct timespec *tv)
291} 294}
292 295
293EXPORT_SYMBOL(do_settimeofday); 296EXPORT_SYMBOL(do_settimeofday);
297#endif /* !CONFIG_GENERIC_TIME */
294 298
295/** 299/**
296 * save_time_delta - Save the offset between system time and RTC time 300 * save_time_delta - Save the offset between system time and RTC time
@@ -500,8 +504,10 @@ device_initcall(timer_init_sysfs);
500 504
501void __init time_init(void) 505void __init time_init(void)
502{ 506{
507#ifndef CONFIG_GENERIC_TIME
503 if (system_timer->offset == NULL) 508 if (system_timer->offset == NULL)
504 system_timer->offset = dummy_gettimeoffset; 509 system_timer->offset = dummy_gettimeoffset;
510#endif
505 system_timer->init(); 511 system_timer->init();
506 512
507#ifdef CONFIG_NO_IDLE_HZ 513#ifdef CONFIG_NO_IDLE_HZ
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index aeeed806f991..bede380c07a9 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -191,7 +191,7 @@ void show_stack(struct task_struct *tsk, unsigned long *sp)
191 if (tsk != current) 191 if (tsk != current)
192 fp = thread_saved_fp(tsk); 192 fp = thread_saved_fp(tsk);
193 else 193 else
194 asm("mov%? %0, fp" : "=r" (fp)); 194 asm("mov %0, fp" : "=r" (fp) : : "cc");
195 195
196 c_backtrace(fp, 0x10); 196 c_backtrace(fp, 0x10);
197 barrier(); 197 barrier();
diff --git a/arch/arm/mach-at91rm9200/at91rm9200.c b/arch/arm/mach-at91rm9200/at91rm9200.c
index 0985b1c42c7c..dcf6136fedf9 100644
--- a/arch/arm/mach-at91rm9200/at91rm9200.c
+++ b/arch/arm/mach-at91rm9200/at91rm9200.c
@@ -17,6 +17,7 @@
17 17
18#include <asm/hardware.h> 18#include <asm/hardware.h>
19#include "generic.h" 19#include "generic.h"
20#include "clock.h"
20 21
21static struct map_desc at91rm9200_io_desc[] __initdata = { 22static struct map_desc at91rm9200_io_desc[] __initdata = {
22 { 23 {
@@ -26,87 +27,224 @@ static struct map_desc at91rm9200_io_desc[] __initdata = {
26 .type = MT_DEVICE, 27 .type = MT_DEVICE,
27 }, { 28 }, {
28 .virtual = AT91_VA_BASE_SPI, 29 .virtual = AT91_VA_BASE_SPI,
29 .pfn = __phys_to_pfn(AT91_BASE_SPI), 30 .pfn = __phys_to_pfn(AT91RM9200_BASE_SPI),
30 .length = SZ_16K,
31 .type = MT_DEVICE,
32 }, {
33 .virtual = AT91_VA_BASE_SSC2,
34 .pfn = __phys_to_pfn(AT91_BASE_SSC2),
35 .length = SZ_16K,
36 .type = MT_DEVICE,
37 }, {
38 .virtual = AT91_VA_BASE_SSC1,
39 .pfn = __phys_to_pfn(AT91_BASE_SSC1),
40 .length = SZ_16K,
41 .type = MT_DEVICE,
42 }, {
43 .virtual = AT91_VA_BASE_SSC0,
44 .pfn = __phys_to_pfn(AT91_BASE_SSC0),
45 .length = SZ_16K,
46 .type = MT_DEVICE,
47 }, {
48 .virtual = AT91_VA_BASE_US3,
49 .pfn = __phys_to_pfn(AT91_BASE_US3),
50 .length = SZ_16K,
51 .type = MT_DEVICE,
52 }, {
53 .virtual = AT91_VA_BASE_US2,
54 .pfn = __phys_to_pfn(AT91_BASE_US2),
55 .length = SZ_16K,
56 .type = MT_DEVICE,
57 }, {
58 .virtual = AT91_VA_BASE_US1,
59 .pfn = __phys_to_pfn(AT91_BASE_US1),
60 .length = SZ_16K,
61 .type = MT_DEVICE,
62 }, {
63 .virtual = AT91_VA_BASE_US0,
64 .pfn = __phys_to_pfn(AT91_BASE_US0),
65 .length = SZ_16K, 31 .length = SZ_16K,
66 .type = MT_DEVICE, 32 .type = MT_DEVICE,
67 }, { 33 }, {
68 .virtual = AT91_VA_BASE_EMAC, 34 .virtual = AT91_VA_BASE_EMAC,
69 .pfn = __phys_to_pfn(AT91_BASE_EMAC), 35 .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC),
70 .length = SZ_16K, 36 .length = SZ_16K,
71 .type = MT_DEVICE, 37 .type = MT_DEVICE,
72 }, { 38 }, {
73 .virtual = AT91_VA_BASE_TWI, 39 .virtual = AT91_VA_BASE_TWI,
74 .pfn = __phys_to_pfn(AT91_BASE_TWI), 40 .pfn = __phys_to_pfn(AT91RM9200_BASE_TWI),
75 .length = SZ_16K, 41 .length = SZ_16K,
76 .type = MT_DEVICE, 42 .type = MT_DEVICE,
77 }, { 43 }, {
78 .virtual = AT91_VA_BASE_MCI, 44 .virtual = AT91_VA_BASE_MCI,
79 .pfn = __phys_to_pfn(AT91_BASE_MCI), 45 .pfn = __phys_to_pfn(AT91RM9200_BASE_MCI),
80 .length = SZ_16K, 46 .length = SZ_16K,
81 .type = MT_DEVICE, 47 .type = MT_DEVICE,
82 }, { 48 }, {
83 .virtual = AT91_VA_BASE_UDP, 49 .virtual = AT91_VA_BASE_UDP,
84 .pfn = __phys_to_pfn(AT91_BASE_UDP), 50 .pfn = __phys_to_pfn(AT91RM9200_BASE_UDP),
85 .length = SZ_16K,
86 .type = MT_DEVICE,
87 }, {
88 .virtual = AT91_VA_BASE_TCB1,
89 .pfn = __phys_to_pfn(AT91_BASE_TCB1),
90 .length = SZ_16K,
91 .type = MT_DEVICE,
92 }, {
93 .virtual = AT91_VA_BASE_TCB0,
94 .pfn = __phys_to_pfn(AT91_BASE_TCB0),
95 .length = SZ_16K, 51 .length = SZ_16K,
96 .type = MT_DEVICE, 52 .type = MT_DEVICE,
97 }, { 53 }, {
98 .virtual = AT91_SRAM_VIRT_BASE, 54 .virtual = AT91_SRAM_VIRT_BASE,
99 .pfn = __phys_to_pfn(AT91_SRAM_BASE), 55 .pfn = __phys_to_pfn(AT91RM9200_SRAM_BASE),
100 .length = AT91_SRAM_SIZE, 56 .length = AT91RM9200_SRAM_SIZE,
101 .type = MT_DEVICE, 57 .type = MT_DEVICE,
102 }, 58 },
103}; 59};
104 60
105void __init at91rm9200_map_io(void) 61/* --------------------------------------------------------------------
62 * Clocks
63 * -------------------------------------------------------------------- */
64
65/*
66 * The peripheral clocks.
67 */
68static struct clk udc_clk = {
69 .name = "udc_clk",
70 .pmc_mask = 1 << AT91RM9200_ID_UDP,
71 .type = CLK_TYPE_PERIPHERAL,
72};
73static struct clk ohci_clk = {
74 .name = "ohci_clk",
75 .pmc_mask = 1 << AT91RM9200_ID_UHP,
76 .type = CLK_TYPE_PERIPHERAL,
77};
78static struct clk ether_clk = {
79 .name = "ether_clk",
80 .pmc_mask = 1 << AT91RM9200_ID_EMAC,
81 .type = CLK_TYPE_PERIPHERAL,
82};
83static struct clk mmc_clk = {
84 .name = "mci_clk",
85 .pmc_mask = 1 << AT91RM9200_ID_MCI,
86 .type = CLK_TYPE_PERIPHERAL,
87};
88static struct clk twi_clk = {
89 .name = "twi_clk",
90 .pmc_mask = 1 << AT91RM9200_ID_TWI,
91 .type = CLK_TYPE_PERIPHERAL,
92};
93static struct clk usart0_clk = {
94 .name = "usart0_clk",
95 .pmc_mask = 1 << AT91RM9200_ID_US0,
96 .type = CLK_TYPE_PERIPHERAL,
97};
98static struct clk usart1_clk = {
99 .name = "usart1_clk",
100 .pmc_mask = 1 << AT91RM9200_ID_US1,
101 .type = CLK_TYPE_PERIPHERAL,
102};
103static struct clk usart2_clk = {
104 .name = "usart2_clk",
105 .pmc_mask = 1 << AT91RM9200_ID_US2,
106 .type = CLK_TYPE_PERIPHERAL,
107};
108static struct clk usart3_clk = {
109 .name = "usart3_clk",
110 .pmc_mask = 1 << AT91RM9200_ID_US3,
111 .type = CLK_TYPE_PERIPHERAL,
112};
113static struct clk spi_clk = {
114 .name = "spi_clk",
115 .pmc_mask = 1 << AT91RM9200_ID_SPI,
116 .type = CLK_TYPE_PERIPHERAL,
117};
118static struct clk pioA_clk = {
119 .name = "pioA_clk",
120 .pmc_mask = 1 << AT91RM9200_ID_PIOA,
121 .type = CLK_TYPE_PERIPHERAL,
122};
123static struct clk pioB_clk = {
124 .name = "pioB_clk",
125 .pmc_mask = 1 << AT91RM9200_ID_PIOB,
126 .type = CLK_TYPE_PERIPHERAL,
127};
128static struct clk pioC_clk = {
129 .name = "pioC_clk",
130 .pmc_mask = 1 << AT91RM9200_ID_PIOC,
131 .type = CLK_TYPE_PERIPHERAL,
132};
133static struct clk pioD_clk = {
134 .name = "pioD_clk",
135 .pmc_mask = 1 << AT91RM9200_ID_PIOD,
136 .type = CLK_TYPE_PERIPHERAL,
137};
138
139static struct clk *periph_clocks[] __initdata = {
140 &pioA_clk,
141 &pioB_clk,
142 &pioC_clk,
143 &pioD_clk,
144 &usart0_clk,
145 &usart1_clk,
146 &usart2_clk,
147 &usart3_clk,
148 &mmc_clk,
149 &udc_clk,
150 &twi_clk,
151 &spi_clk,
152 // ssc 0 .. ssc2
153 // tc0 .. tc5
154 &ohci_clk,
155 &ether_clk,
156 // irq0 .. irq6
157};
158
159/*
160 * The four programmable clocks.
161 * You must configure pin multiplexing to bring these signals out.
162 */
163static struct clk pck0 = {
164 .name = "pck0",
165 .pmc_mask = AT91_PMC_PCK0,
166 .type = CLK_TYPE_PROGRAMMABLE,
167 .id = 0,
168};
169static struct clk pck1 = {
170 .name = "pck1",
171 .pmc_mask = AT91_PMC_PCK1,
172 .type = CLK_TYPE_PROGRAMMABLE,
173 .id = 1,
174};
175static struct clk pck2 = {
176 .name = "pck2",
177 .pmc_mask = AT91_PMC_PCK2,
178 .type = CLK_TYPE_PROGRAMMABLE,
179 .id = 2,
180};
181static struct clk pck3 = {
182 .name = "pck3",
183 .pmc_mask = AT91_PMC_PCK3,
184 .type = CLK_TYPE_PROGRAMMABLE,
185 .id = 3,
186};
187
188static void __init at91rm9200_register_clocks(void)
106{ 189{
190 int i;
191
192 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
193 clk_register(periph_clocks[i]);
194
195 clk_register(&pck0);
196 clk_register(&pck1);
197 clk_register(&pck2);
198 clk_register(&pck3);
199}
200
201/* --------------------------------------------------------------------
202 * GPIO
203 * -------------------------------------------------------------------- */
204
205static struct at91_gpio_bank at91rm9200_gpio[] = {
206 {
207 .id = AT91RM9200_ID_PIOA,
208 .offset = AT91_PIOA,
209 .clock = &pioA_clk,
210 }, {
211 .id = AT91RM9200_ID_PIOB,
212 .offset = AT91_PIOB,
213 .clock = &pioB_clk,
214 }, {
215 .id = AT91RM9200_ID_PIOC,
216 .offset = AT91_PIOC,
217 .clock = &pioC_clk,
218 }, {
219 .id = AT91RM9200_ID_PIOD,
220 .offset = AT91_PIOD,
221 .clock = &pioD_clk,
222 }
223};
224
225/* --------------------------------------------------------------------
226 * AT91RM9200 processor initialization
227 * -------------------------------------------------------------------- */
228void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks)
229{
230 /* Map peripherals */
107 iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); 231 iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
232
233 /* Init clock subsystem */
234 at91_clock_init(main_clock);
235
236 /* Register the processor-specific clocks */
237 at91rm9200_register_clocks();
238
239 /* Initialize GPIO subsystem */
240 at91_gpio_init(at91rm9200_gpio, banks);
108} 241}
109 242
243
244/* --------------------------------------------------------------------
245 * Interrupt initialization
246 * -------------------------------------------------------------------- */
247
110/* 248/*
111 * The default interrupt priority levels (0 = lowest, 7 = highest). 249 * The default interrupt priority levels (0 = lowest, 7 = highest).
112 */ 250 */
@@ -145,10 +283,14 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
145 0 /* Advanced Interrupt Controller (IRQ6) */ 283 0 /* Advanced Interrupt Controller (IRQ6) */
146}; 284};
147 285
148void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS]) 286void __init at91rm9200_init_interrupts(unsigned int priority[NR_AIC_IRQS])
149{ 287{
150 if (!priority) 288 if (!priority)
151 priority = at91rm9200_default_irq_priority; 289 priority = at91rm9200_default_irq_priority;
152 290
291 /* Initialize the AIC interrupt controller */
153 at91_aic_init(priority); 292 at91_aic_init(priority);
293
294 /* Enable GPIO interrupts */
295 at91_gpio_irq_setup();
154} 296}
diff --git a/arch/arm/mach-at91rm9200/board-1arm.c b/arch/arm/mach-at91rm9200/board-1arm.c
index dc79e0992af7..36eecd7161f5 100644
--- a/arch/arm/mach-at91rm9200/board-1arm.c
+++ b/arch/arm/mach-at91rm9200/board-1arm.c
@@ -34,20 +34,11 @@
34#include <asm/mach/map.h> 34#include <asm/mach/map.h>
35#include <asm/mach/irq.h> 35#include <asm/mach/irq.h>
36 36
37#include <asm/hardware.h>
38#include <asm/arch/board.h> 37#include <asm/arch/board.h>
39#include <asm/arch/gpio.h> 38#include <asm/arch/gpio.h>
40 39
41#include "generic.h" 40#include "generic.h"
42 41
43static void __init onearm_init_irq(void)
44{
45 /* Initialize AIC controller */
46 at91rm9200_init_irq(NULL);
47
48 /* Set up the GPIO interrupts */
49 at91_gpio_irq_setup(PQFP_GPIO_BANKS);
50}
51 42
52/* 43/*
53 * Serial port configuration. 44 * Serial port configuration.
@@ -62,15 +53,18 @@ static struct at91_uart_config __initdata onearm_uart_config = {
62 53
63static void __init onearm_map_io(void) 54static void __init onearm_map_io(void)
64{ 55{
65 at91rm9200_map_io(); 56 /* Initialize processor: 18.432 MHz crystal */
66 57 at91rm9200_initialize(18432000, AT91RM9200_PQFP);
67 /* Initialize clocks: 18.432 MHz crystal */
68 at91_clock_init(18432000);
69 58
70 /* Setup the serial ports and console */ 59 /* Setup the serial ports and console */
71 at91_init_serial(&onearm_uart_config); 60 at91_init_serial(&onearm_uart_config);
72} 61}
73 62
63static void __init onearm_init_irq(void)
64{
65 at91rm9200_init_interrupts(NULL);
66}
67
74static struct at91_eth_data __initdata onearm_eth_data = { 68static struct at91_eth_data __initdata onearm_eth_data = {
75 .phy_irq_pin = AT91_PIN_PC4, 69 .phy_irq_pin = AT91_PIN_PC4,
76 .is_rmii = 1, 70 .is_rmii = 1,
diff --git a/arch/arm/mach-at91rm9200/board-carmeva.c b/arch/arm/mach-at91rm9200/board-carmeva.c
index 2c138b542ebe..50e513681ae6 100644
--- a/arch/arm/mach-at91rm9200/board-carmeva.c
+++ b/arch/arm/mach-at91rm9200/board-carmeva.c
@@ -35,20 +35,11 @@
35#include <asm/mach/map.h> 35#include <asm/mach/map.h>
36#include <asm/mach/irq.h> 36#include <asm/mach/irq.h>
37 37
38#include <asm/hardware.h>
39#include <asm/arch/board.h> 38#include <asm/arch/board.h>
40#include <asm/arch/gpio.h> 39#include <asm/arch/gpio.h>
41 40
42#include "generic.h" 41#include "generic.h"
43 42
44static void __init carmeva_init_irq(void)
45{
46 /* Initialize AIC controller */
47 at91rm9200_init_irq(NULL);
48
49 /* Set up the GPIO interrupts */
50 at91_gpio_irq_setup(BGA_GPIO_BANKS);
51}
52 43
53/* 44/*
54 * Serial port configuration. 45 * Serial port configuration.
@@ -63,15 +54,19 @@ static struct at91_uart_config __initdata carmeva_uart_config = {
63 54
64static void __init carmeva_map_io(void) 55static void __init carmeva_map_io(void)
65{ 56{
66 at91rm9200_map_io(); 57 /* Initialize processor: 20.000 MHz crystal */
67 58 at91rm9200_initialize(20000000, AT91RM9200_BGA);
68 /* Initialize clocks: 20.000 MHz crystal */
69 at91_clock_init(20000000);
70 59
71 /* Setup the serial ports and console */ 60 /* Setup the serial ports and console */
72 at91_init_serial(&carmeva_uart_config); 61 at91_init_serial(&carmeva_uart_config);
73} 62}
74 63
64static void __init carmeva_init_irq(void)
65{
66 at91rm9200_init_interrupts(NULL);
67}
68
69
75static struct at91_eth_data __initdata carmeva_eth_data = { 70static struct at91_eth_data __initdata carmeva_eth_data = {
76 .phy_irq_pin = AT91_PIN_PC4, 71 .phy_irq_pin = AT91_PIN_PC4,
77 .is_rmii = 1, 72 .is_rmii = 1,
diff --git a/arch/arm/mach-at91rm9200/board-csb337.c b/arch/arm/mach-at91rm9200/board-csb337.c
index 794d3fbb449b..8eeae491ce71 100644
--- a/arch/arm/mach-at91rm9200/board-csb337.c
+++ b/arch/arm/mach-at91rm9200/board-csb337.c
@@ -34,20 +34,11 @@
34#include <asm/mach/map.h> 34#include <asm/mach/map.h>
35#include <asm/mach/irq.h> 35#include <asm/mach/irq.h>
36 36
37#include <asm/hardware.h>
38#include <asm/arch/board.h> 37#include <asm/arch/board.h>
39#include <asm/arch/gpio.h> 38#include <asm/arch/gpio.h>
40 39
41#include "generic.h" 40#include "generic.h"
42 41
43static void __init csb337_init_irq(void)
44{
45 /* Initialize AIC controller */
46 at91rm9200_init_irq(NULL);
47
48 /* Set up the GPIO interrupts */
49 at91_gpio_irq_setup(BGA_GPIO_BANKS);
50}
51 42
52/* 43/*
53 * Serial port configuration. 44 * Serial port configuration.
@@ -62,10 +53,8 @@ static struct at91_uart_config __initdata csb337_uart_config = {
62 53
63static void __init csb337_map_io(void) 54static void __init csb337_map_io(void)
64{ 55{
65 at91rm9200_map_io(); 56 /* Initialize processor: 3.6864 MHz crystal */
66 57 at91rm9200_initialize(3686400, AT91RM9200_BGA);
67 /* Initialize clocks: 3.6864 MHz crystal */
68 at91_clock_init(3686400);
69 58
70 /* Setup the LEDs */ 59 /* Setup the LEDs */
71 at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); 60 at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
@@ -74,6 +63,11 @@ static void __init csb337_map_io(void)
74 at91_init_serial(&csb337_uart_config); 63 at91_init_serial(&csb337_uart_config);
75} 64}
76 65
66static void __init csb337_init_irq(void)
67{
68 at91rm9200_init_interrupts(NULL);
69}
70
77static struct at91_eth_data __initdata csb337_eth_data = { 71static struct at91_eth_data __initdata csb337_eth_data = {
78 .phy_irq_pin = AT91_PIN_PC2, 72 .phy_irq_pin = AT91_PIN_PC2,
79 .is_rmii = 0, 73 .is_rmii = 0,
diff --git a/arch/arm/mach-at91rm9200/board-csb637.c b/arch/arm/mach-at91rm9200/board-csb637.c
index c8b6f334246a..a29fa0e822ce 100644
--- a/arch/arm/mach-at91rm9200/board-csb637.c
+++ b/arch/arm/mach-at91rm9200/board-csb637.c
@@ -33,20 +33,11 @@
33#include <asm/mach/map.h> 33#include <asm/mach/map.h>
34#include <asm/mach/irq.h> 34#include <asm/mach/irq.h>
35 35
36#include <asm/hardware.h>
37#include <asm/arch/board.h> 36#include <asm/arch/board.h>
38#include <asm/arch/gpio.h> 37#include <asm/arch/gpio.h>
39 38
40#include "generic.h" 39#include "generic.h"
41 40
42static void __init csb637_init_irq(void)
43{
44 /* Initialize AIC controller */
45 at91rm9200_init_irq(NULL);
46
47 /* Set up the GPIO interrupts */
48 at91_gpio_irq_setup(BGA_GPIO_BANKS);
49}
50 41
51/* 42/*
52 * Serial port configuration. 43 * Serial port configuration.
@@ -61,10 +52,8 @@ static struct at91_uart_config __initdata csb637_uart_config = {
61 52
62static void __init csb637_map_io(void) 53static void __init csb637_map_io(void)
63{ 54{
64 at91rm9200_map_io(); 55 /* Initialize processor: 3.6864 MHz crystal */
65 56 at91rm9200_initialize(3686400, AT91RM9200_BGA);
66 /* Initialize clocks: 3.6864 MHz crystal */
67 at91_clock_init(3686400);
68 57
69 /* Setup the LEDs */ 58 /* Setup the LEDs */
70 at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); 59 at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
@@ -73,6 +62,11 @@ static void __init csb637_map_io(void)
73 at91_init_serial(&csb637_uart_config); 62 at91_init_serial(&csb637_uart_config);
74} 63}
75 64
65static void __init csb637_init_irq(void)
66{
67 at91rm9200_init_interrupts(NULL);
68}
69
76static struct at91_eth_data __initdata csb637_eth_data = { 70static struct at91_eth_data __initdata csb637_eth_data = {
77 .phy_irq_pin = AT91_PIN_PC0, 71 .phy_irq_pin = AT91_PIN_PC0,
78 .is_rmii = 0, 72 .is_rmii = 0,
diff --git a/arch/arm/mach-at91rm9200/board-dk.c b/arch/arm/mach-at91rm9200/board-dk.c
index 65873037e02a..c699f3984d4b 100644
--- a/arch/arm/mach-at91rm9200/board-dk.c
+++ b/arch/arm/mach-at91rm9200/board-dk.c
@@ -37,20 +37,11 @@
37#include <asm/mach/map.h> 37#include <asm/mach/map.h>
38#include <asm/mach/irq.h> 38#include <asm/mach/irq.h>
39 39
40#include <asm/hardware.h>
41#include <asm/arch/board.h> 40#include <asm/arch/board.h>
42#include <asm/arch/gpio.h> 41#include <asm/arch/gpio.h>
43 42
44#include "generic.h" 43#include "generic.h"
45 44
46static void __init dk_init_irq(void)
47{
48 /* Initialize AIC controller */
49 at91rm9200_init_irq(NULL);
50
51 /* Set up the GPIO interrupts */
52 at91_gpio_irq_setup(BGA_GPIO_BANKS);
53}
54 45
55/* 46/*
56 * Serial port configuration. 47 * Serial port configuration.
@@ -65,10 +56,8 @@ static struct at91_uart_config __initdata dk_uart_config = {
65 56
66static void __init dk_map_io(void) 57static void __init dk_map_io(void)
67{ 58{
68 at91rm9200_map_io(); 59 /* Initialize processor: 18.432 MHz crystal */
69 60 at91rm9200_initialize(18432000, AT91RM9200_BGA);
70 /* Initialize clocks: 18.432 MHz crystal */
71 at91_clock_init(18432000);
72 61
73 /* Setup the LEDs */ 62 /* Setup the LEDs */
74 at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); 63 at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
@@ -77,6 +66,11 @@ static void __init dk_map_io(void)
77 at91_init_serial(&dk_uart_config); 66 at91_init_serial(&dk_uart_config);
78} 67}
79 68
69static void __init dk_init_irq(void)
70{
71 at91rm9200_init_interrupts(NULL);
72}
73
80static struct at91_eth_data __initdata dk_eth_data = { 74static struct at91_eth_data __initdata dk_eth_data = {
81 .phy_irq_pin = AT91_PIN_PC4, 75 .phy_irq_pin = AT91_PIN_PC4,
82 .is_rmii = 1, 76 .is_rmii = 1,
@@ -128,6 +122,29 @@ static struct spi_board_info dk_spi_devices[] = {
128#endif 122#endif
129}; 123};
130 124
125static struct mtd_partition __initdata dk_nand_partition[] = {
126 {
127 .name = "NAND Partition 1",
128 .offset = 0,
129 .size = MTDPART_SIZ_FULL,
130 },
131};
132
133static struct mtd_partition *nand_partitions(int size, int *num_partitions)
134{
135 *num_partitions = ARRAY_SIZE(dk_nand_partition);
136 return dk_nand_partition;
137}
138
139static struct at91_nand_data __initdata dk_nand_data = {
140 .ale = 22,
141 .cle = 21,
142 .det_pin = AT91_PIN_PB1,
143 .rdy_pin = AT91_PIN_PC2,
144 // .enable_pin = ... not there
145 .partition_info = nand_partitions,
146};
147
131static void __init dk_board_init(void) 148static void __init dk_board_init(void)
132{ 149{
133 /* Serial */ 150 /* Serial */
@@ -153,6 +170,8 @@ static void __init dk_board_init(void)
153 at91_set_gpio_output(AT91_PIN_PB7, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */ 170 at91_set_gpio_output(AT91_PIN_PB7, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
154 at91_add_device_mmc(&dk_mmc_data); 171 at91_add_device_mmc(&dk_mmc_data);
155#endif 172#endif
173 /* NAND */
174 at91_add_device_nand(&dk_nand_data);
156 /* VGA */ 175 /* VGA */
157// dk_add_device_video(); 176// dk_add_device_video();
158} 177}
diff --git a/arch/arm/mach-at91rm9200/board-eb9200.c b/arch/arm/mach-at91rm9200/board-eb9200.c
index a3e2df968a66..c6e0d51fbea0 100644
--- a/arch/arm/mach-at91rm9200/board-eb9200.c
+++ b/arch/arm/mach-at91rm9200/board-eb9200.c
@@ -35,20 +35,11 @@
35#include <asm/mach/map.h> 35#include <asm/mach/map.h>
36#include <asm/mach/irq.h> 36#include <asm/mach/irq.h>
37 37
38#include <asm/hardware.h>
39#include <asm/arch/board.h> 38#include <asm/arch/board.h>
40#include <asm/arch/gpio.h> 39#include <asm/arch/gpio.h>
41 40
42#include "generic.h" 41#include "generic.h"
43 42
44static void __init eb9200_init_irq(void)
45{
46 /* Initialize AIC controller */
47 at91rm9200_init_irq(NULL);
48
49 /* Set up the GPIO interrupts */
50 at91_gpio_irq_setup(BGA_GPIO_BANKS);
51}
52 43
53/* 44/*
54 * Serial port configuration. 45 * Serial port configuration.
@@ -63,15 +54,18 @@ static struct at91_uart_config __initdata eb9200_uart_config = {
63 54
64static void __init eb9200_map_io(void) 55static void __init eb9200_map_io(void)
65{ 56{
66 at91rm9200_map_io(); 57 /* Initialize processor: 18.432 MHz crystal */
67 58 at91rm9200_initialize(18432000, AT91RM9200_BGA);
68 /* Initialize clocks: 18.432 MHz crystal */
69 at91_clock_init(18432000);
70 59
71 /* Setup the serial ports and console */ 60 /* Setup the serial ports and console */
72 at91_init_serial(&eb9200_uart_config); 61 at91_init_serial(&eb9200_uart_config);
73} 62}
74 63
64static void __init eb9200_init_irq(void)
65{
66 at91rm9200_init_interrupts(NULL);
67}
68
75static struct at91_eth_data __initdata eb9200_eth_data = { 69static struct at91_eth_data __initdata eb9200_eth_data = {
76 .phy_irq_pin = AT91_PIN_PC4, 70 .phy_irq_pin = AT91_PIN_PC4,
77 .is_rmii = 1, 71 .is_rmii = 1,
diff --git a/arch/arm/mach-at91rm9200/board-ek.c b/arch/arm/mach-at91rm9200/board-ek.c
index 868192351dda..830eb7932178 100644
--- a/arch/arm/mach-at91rm9200/board-ek.c
+++ b/arch/arm/mach-at91rm9200/board-ek.c
@@ -37,20 +37,11 @@
37#include <asm/mach/map.h> 37#include <asm/mach/map.h>
38#include <asm/mach/irq.h> 38#include <asm/mach/irq.h>
39 39
40#include <asm/hardware.h>
41#include <asm/arch/board.h> 40#include <asm/arch/board.h>
42#include <asm/arch/gpio.h> 41#include <asm/arch/gpio.h>
43 42
44#include "generic.h" 43#include "generic.h"
45 44
46static void __init ek_init_irq(void)
47{
48 /* Initialize AIC controller */
49 at91rm9200_init_irq(NULL);
50
51 /* Set up the GPIO interrupts */
52 at91_gpio_irq_setup(BGA_GPIO_BANKS);
53}
54 45
55/* 46/*
56 * Serial port configuration. 47 * Serial port configuration.
@@ -65,10 +56,8 @@ static struct at91_uart_config __initdata ek_uart_config = {
65 56
66static void __init ek_map_io(void) 57static void __init ek_map_io(void)
67{ 58{
68 at91rm9200_map_io(); 59 /* Initialize processor: 18.432 MHz crystal */
69 60 at91rm9200_initialize(18432000, AT91RM9200_BGA);
70 /* Initialize clocks: 18.432 MHz crystal */
71 at91_clock_init(18432000);
72 61
73 /* Setup the LEDs */ 62 /* Setup the LEDs */
74 at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2); 63 at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2);
@@ -77,6 +66,11 @@ static void __init ek_map_io(void)
77 at91_init_serial(&ek_uart_config); 66 at91_init_serial(&ek_uart_config);
78} 67}
79 68
69static void __init ek_init_irq(void)
70{
71 at91rm9200_init_interrupts(NULL);
72}
73
80static struct at91_eth_data __initdata ek_eth_data = { 74static struct at91_eth_data __initdata ek_eth_data = {
81 .phy_irq_pin = AT91_PIN_PC4, 75 .phy_irq_pin = AT91_PIN_PC4,
82 .is_rmii = 1, 76 .is_rmii = 1,
diff --git a/arch/arm/mach-at91rm9200/board-kafa.c b/arch/arm/mach-at91rm9200/board-kafa.c
index bf760c5e0c46..91e301924f2c 100644
--- a/arch/arm/mach-at91rm9200/board-kafa.c
+++ b/arch/arm/mach-at91rm9200/board-kafa.c
@@ -34,20 +34,11 @@
34#include <asm/mach/map.h> 34#include <asm/mach/map.h>
35#include <asm/mach/irq.h> 35#include <asm/mach/irq.h>
36 36
37#include <asm/hardware.h>
38#include <asm/arch/board.h> 37#include <asm/arch/board.h>
39#include <asm/arch/gpio.h> 38#include <asm/arch/gpio.h>
40 39
41#include "generic.h" 40#include "generic.h"
42 41
43static void __init kafa_init_irq(void)
44{
45 /* Initialize AIC controller */
46 at91rm9200_init_irq(NULL);
47
48 /* Set up the GPIO interrupts */
49 at91_gpio_irq_setup(PQFP_GPIO_BANKS);
50}
51 42
52/* 43/*
53 * Serial port configuration. 44 * Serial port configuration.
@@ -62,10 +53,8 @@ static struct at91_uart_config __initdata kafa_uart_config = {
62 53
63static void __init kafa_map_io(void) 54static void __init kafa_map_io(void)
64{ 55{
65 at91rm9200_map_io(); 56 /* Initialize processor: 18.432 MHz crystal */
66 57 at91rm9200_initialize(18432000, AT91RM9200_PQFP);
67 /* Initialize clocks: 18.432 MHz crystal */
68 at91_clock_init(18432000);
69 58
70 /* Set up the LEDs */ 59 /* Set up the LEDs */
71 at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4); 60 at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4);
@@ -74,6 +63,11 @@ static void __init kafa_map_io(void)
74 at91_init_serial(&kafa_uart_config); 63 at91_init_serial(&kafa_uart_config);
75} 64}
76 65
66static void __init kafa_init_irq(void)
67{
68 at91rm9200_init_interrupts(NULL);
69}
70
77static struct at91_eth_data __initdata kafa_eth_data = { 71static struct at91_eth_data __initdata kafa_eth_data = {
78 .phy_irq_pin = AT91_PIN_PC4, 72 .phy_irq_pin = AT91_PIN_PC4,
79 .is_rmii = 0, 73 .is_rmii = 0,
diff --git a/arch/arm/mach-at91rm9200/board-kb9202.c b/arch/arm/mach-at91rm9200/board-kb9202.c
index f06d2b54cc9a..272fe43bceca 100644
--- a/arch/arm/mach-at91rm9200/board-kb9202.c
+++ b/arch/arm/mach-at91rm9200/board-kb9202.c
@@ -35,20 +35,11 @@
35#include <asm/mach/map.h> 35#include <asm/mach/map.h>
36#include <asm/mach/irq.h> 36#include <asm/mach/irq.h>
37 37
38#include <asm/hardware.h>
39#include <asm/arch/board.h> 38#include <asm/arch/board.h>
40#include <asm/arch/gpio.h> 39#include <asm/arch/gpio.h>
41 40
42#include "generic.h" 41#include "generic.h"
43 42
44static void __init kb9202_init_irq(void)
45{
46 /* Initialize AIC controller */
47 at91rm9200_init_irq(NULL);
48
49 /* Set up the GPIO interrupts */
50 at91_gpio_irq_setup(PQFP_GPIO_BANKS);
51}
52 43
53/* 44/*
54 * Serial port configuration. 45 * Serial port configuration.
@@ -63,10 +54,8 @@ static struct at91_uart_config __initdata kb9202_uart_config = {
63 54
64static void __init kb9202_map_io(void) 55static void __init kb9202_map_io(void)
65{ 56{
66 at91rm9200_map_io(); 57 /* Initialize processor: 10 MHz crystal */
67 58 at91rm9200_initialize(10000000, AT91RM9200_PQFP);
68 /* Initialize clocks: 10 MHz crystal */
69 at91_clock_init(10000000);
70 59
71 /* Set up the LEDs */ 60 /* Set up the LEDs */
72 at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18); 61 at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18);
@@ -75,6 +64,11 @@ static void __init kb9202_map_io(void)
75 at91_init_serial(&kb9202_uart_config); 64 at91_init_serial(&kb9202_uart_config);
76} 65}
77 66
67static void __init kb9202_init_irq(void)
68{
69 at91rm9200_init_interrupts(NULL);
70}
71
78static struct at91_eth_data __initdata kb9202_eth_data = { 72static struct at91_eth_data __initdata kb9202_eth_data = {
79 .phy_irq_pin = AT91_PIN_PB29, 73 .phy_irq_pin = AT91_PIN_PB29,
80 .is_rmii = 0, 74 .is_rmii = 0,
@@ -95,6 +89,29 @@ static struct at91_mmc_data __initdata kb9202_mmc_data = {
95 .wire4 = 1, 89 .wire4 = 1,
96}; 90};
97 91
92static struct mtd_partition __initdata kb9202_nand_partition[] = {
93 {
94 .name = "nand_fs",
95 .offset = 0,
96 .size = MTDPART_SIZ_FULL,
97 },
98};
99
100static struct mtd_partition *nand_partitions(int size, int *num_partitions)
101{
102 *num_partitions = ARRAY_SIZE(kb9202_nand_partition);
103 return kb9202_nand_partition;
104}
105
106static struct at91_nand_data __initdata kb9202_nand_data = {
107 .ale = 22,
108 .cle = 21,
109 // .det_pin = ... not there
110 .rdy_pin = AT91_PIN_PC29,
111 .enable_pin = AT91_PIN_PC28,
112 .partition_info = nand_partitions,
113};
114
98static void __init kb9202_board_init(void) 115static void __init kb9202_board_init(void)
99{ 116{
100 /* Serial */ 117 /* Serial */
@@ -111,6 +128,8 @@ static void __init kb9202_board_init(void)
111 at91_add_device_i2c(); 128 at91_add_device_i2c();
112 /* SPI */ 129 /* SPI */
113 at91_add_device_spi(NULL, 0); 130 at91_add_device_spi(NULL, 0);
131 /* NAND */
132 at91_add_device_nand(&kb9202_nand_data);
114} 133}
115 134
116MACHINE_START(KB9200, "KB920x") 135MACHINE_START(KB9200, "KB920x")
diff --git a/arch/arm/mach-at91rm9200/clock.c b/arch/arm/mach-at91rm9200/clock.c
index edc2cc837ae6..a43b061a7c85 100644
--- a/arch/arm/mach-at91rm9200/clock.c
+++ b/arch/arm/mach-at91rm9200/clock.c
@@ -29,7 +29,7 @@
29 29
30#include <asm/hardware.h> 30#include <asm/hardware.h>
31 31
32#include "generic.h" 32#include "clock.h"
33 33
34 34
35/* 35/*
@@ -38,23 +38,15 @@
38 * PLLB be used at other rates (on boards that don't need USB), etc. 38 * PLLB be used at other rates (on boards that don't need USB), etc.
39 */ 39 */
40 40
41struct clk { 41#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
42 const char *name; /* unique clock name */ 42#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
43 const char *function; /* function of the clock */ 43#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
44 struct device *dev; /* device associated with function */ 44
45 unsigned long rate_hz; 45
46 struct clk *parent; 46static LIST_HEAD(clocks);
47 u32 pmc_mask; 47static DEFINE_SPINLOCK(clk_lock);
48 void (*mode)(struct clk *, int);
49 unsigned id:2; /* PCK0..3, or 32k/main/a/b */
50 unsigned primary:1;
51 unsigned pll:1;
52 unsigned programmable:1;
53 u16 users;
54};
55 48
56static spinlock_t clk_lock; 49static u32 at91_pllb_usb_init;
57static u32 at91_pllb_usb_init;
58 50
59/* 51/*
60 * Four primary clock sources: two crystal oscillators (32K, main), and 52 * Four primary clock sources: two crystal oscillators (32K, main), and
@@ -67,21 +59,20 @@ static struct clk clk32k = {
67 .rate_hz = AT91_SLOW_CLOCK, 59 .rate_hz = AT91_SLOW_CLOCK,
68 .users = 1, /* always on */ 60 .users = 1, /* always on */
69 .id = 0, 61 .id = 0,
70 .primary = 1, 62 .type = CLK_TYPE_PRIMARY,
71}; 63};
72static struct clk main_clk = { 64static struct clk main_clk = {
73 .name = "main", 65 .name = "main",
74 .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */ 66 .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
75 .id = 1, 67 .id = 1,
76 .primary = 1, 68 .type = CLK_TYPE_PRIMARY,
77}; 69};
78static struct clk plla = { 70static struct clk plla = {
79 .name = "plla", 71 .name = "plla",
80 .parent = &main_clk, 72 .parent = &main_clk,
81 .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */ 73 .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
82 .id = 2, 74 .id = 2,
83 .primary = 1, 75 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
84 .pll = 1,
85}; 76};
86 77
87static void pllb_mode(struct clk *clk, int is_on) 78static void pllb_mode(struct clk *clk, int is_on)
@@ -94,6 +85,7 @@ static void pllb_mode(struct clk *clk, int is_on)
94 } else 85 } else
95 value = 0; 86 value = 0;
96 87
88 // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
97 at91_sys_write(AT91_CKGR_PLLBR, value); 89 at91_sys_write(AT91_CKGR_PLLBR, value);
98 90
99 do { 91 do {
@@ -107,8 +99,7 @@ static struct clk pllb = {
107 .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */ 99 .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
108 .mode = pllb_mode, 100 .mode = pllb_mode,
109 .id = 3, 101 .id = 3,
110 .primary = 1, 102 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
111 .pll = 1,
112}; 103};
113 104
114static void pmc_sys_mode(struct clk *clk, int is_on) 105static void pmc_sys_mode(struct clk *clk, int is_on)
@@ -133,41 +124,6 @@ static struct clk uhpck = {
133 .mode = pmc_sys_mode, 124 .mode = pmc_sys_mode,
134}; 125};
135 126
136#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
137/*
138 * The four programmable clocks can be parented by any primary clock.
139 * You must configure pin multiplexing to bring these signals out.
140 */
141static struct clk pck0 = {
142 .name = "pck0",
143 .pmc_mask = AT91_PMC_PCK0,
144 .mode = pmc_sys_mode,
145 .programmable = 1,
146 .id = 0,
147};
148static struct clk pck1 = {
149 .name = "pck1",
150 .pmc_mask = AT91_PMC_PCK1,
151 .mode = pmc_sys_mode,
152 .programmable = 1,
153 .id = 1,
154};
155static struct clk pck2 = {
156 .name = "pck2",
157 .pmc_mask = AT91_PMC_PCK2,
158 .mode = pmc_sys_mode,
159 .programmable = 1,
160 .id = 2,
161};
162static struct clk pck3 = {
163 .name = "pck3",
164 .pmc_mask = AT91_PMC_PCK3,
165 .mode = pmc_sys_mode,
166 .programmable = 1,
167 .id = 3,
168};
169#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
170
171 127
172/* 128/*
173 * The master clock is divided from the CPU clock (by 1-4). It's used for 129 * The master clock is divided from the CPU clock (by 1-4). It's used for
@@ -187,131 +143,21 @@ static void pmc_periph_mode(struct clk *clk, int is_on)
187 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask); 143 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
188} 144}
189 145
190static struct clk udc_clk = { 146static struct clk __init *at91_css_to_clk(unsigned long css)
191 .name = "udc_clk", 147{
192 .parent = &mck, 148 switch (css) {
193 .pmc_mask = 1 << AT91_ID_UDP, 149 case AT91_PMC_CSS_SLOW:
194 .mode = pmc_periph_mode, 150 return &clk32k;
195}; 151 case AT91_PMC_CSS_MAIN:
196static struct clk ohci_clk = { 152 return &main_clk;
197 .name = "ohci_clk", 153 case AT91_PMC_CSS_PLLA:
198 .parent = &mck, 154 return &plla;
199 .pmc_mask = 1 << AT91_ID_UHP, 155 case AT91_PMC_CSS_PLLB:
200 .mode = pmc_periph_mode, 156 return &pllb;
201}; 157 }
202static struct clk ether_clk = {
203 .name = "ether_clk",
204 .parent = &mck,
205 .pmc_mask = 1 << AT91_ID_EMAC,
206 .mode = pmc_periph_mode,
207};
208static struct clk mmc_clk = {
209 .name = "mci_clk",
210 .parent = &mck,
211 .pmc_mask = 1 << AT91_ID_MCI,
212 .mode = pmc_periph_mode,
213};
214static struct clk twi_clk = {
215 .name = "twi_clk",
216 .parent = &mck,
217 .pmc_mask = 1 << AT91_ID_TWI,
218 .mode = pmc_periph_mode,
219};
220static struct clk usart0_clk = {
221 .name = "usart0_clk",
222 .parent = &mck,
223 .pmc_mask = 1 << AT91_ID_US0,
224 .mode = pmc_periph_mode,
225};
226static struct clk usart1_clk = {
227 .name = "usart1_clk",
228 .parent = &mck,
229 .pmc_mask = 1 << AT91_ID_US1,
230 .mode = pmc_periph_mode,
231};
232static struct clk usart2_clk = {
233 .name = "usart2_clk",
234 .parent = &mck,
235 .pmc_mask = 1 << AT91_ID_US2,
236 .mode = pmc_periph_mode,
237};
238static struct clk usart3_clk = {
239 .name = "usart3_clk",
240 .parent = &mck,
241 .pmc_mask = 1 << AT91_ID_US3,
242 .mode = pmc_periph_mode,
243};
244static struct clk spi_clk = {
245 .name = "spi0_clk",
246 .parent = &mck,
247 .pmc_mask = 1 << AT91_ID_SPI,
248 .mode = pmc_periph_mode,
249};
250static struct clk pioA_clk = {
251 .name = "pioA_clk",
252 .parent = &mck,
253 .pmc_mask = 1 << AT91_ID_PIOA,
254 .mode = pmc_periph_mode,
255};
256static struct clk pioB_clk = {
257 .name = "pioB_clk",
258 .parent = &mck,
259 .pmc_mask = 1 << AT91_ID_PIOB,
260 .mode = pmc_periph_mode,
261};
262static struct clk pioC_clk = {
263 .name = "pioC_clk",
264 .parent = &mck,
265 .pmc_mask = 1 << AT91_ID_PIOC,
266 .mode = pmc_periph_mode,
267};
268static struct clk pioD_clk = {
269 .name = "pioD_clk",
270 .parent = &mck,
271 .pmc_mask = 1 << AT91_ID_PIOD,
272 .mode = pmc_periph_mode,
273};
274
275static struct clk *const clock_list[] = {
276 /* four primary clocks -- MUST BE FIRST! */
277 &clk32k,
278 &main_clk,
279 &plla,
280 &pllb,
281
282 /* PLLB children (USB) */
283 &udpck,
284 &uhpck,
285
286#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
287 /* programmable clocks */
288 &pck0,
289 &pck1,
290 &pck2,
291 &pck3,
292#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
293
294 /* MCK and peripherals */
295 &mck,
296 &usart0_clk,
297 &usart1_clk,
298 &usart2_clk,
299 &usart3_clk,
300 &mmc_clk,
301 &udc_clk,
302 &twi_clk,
303 &spi_clk,
304 &pioA_clk,
305 &pioB_clk,
306 &pioC_clk,
307 &pioD_clk,
308 // ssc0..ssc2
309 // tc0..tc5
310 // irq0..irq6
311 &ohci_clk,
312 &ether_clk,
313};
314 158
159 return NULL;
160}
315 161
316/* 162/*
317 * Associate a particular clock with a function (eg, "uart") and device. 163 * Associate a particular clock with a function (eg, "uart") and device.
@@ -329,14 +175,12 @@ void __init at91_clock_associate(const char *id, struct device *dev, const char
329 clk->dev = dev; 175 clk->dev = dev;
330} 176}
331 177
332/* clocks are all static for now; no refcounting necessary */ 178/* clocks cannot be de-registered no refcounting necessary */
333struct clk *clk_get(struct device *dev, const char *id) 179struct clk *clk_get(struct device *dev, const char *id)
334{ 180{
335 int i; 181 struct clk *clk;
336
337 for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
338 struct clk *clk = clock_list[i];
339 182
183 list_for_each_entry(clk, &clocks, node) {
340 if (strcmp(id, clk->name) == 0) 184 if (strcmp(id, clk->name) == 0)
341 return clk; 185 return clk;
342 if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0) 186 if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
@@ -424,7 +268,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
424 unsigned prescale; 268 unsigned prescale;
425 unsigned long actual; 269 unsigned long actual;
426 270
427 if (!clk->programmable) 271 if (!clk_is_programmable(clk))
428 return -EINVAL; 272 return -EINVAL;
429 spin_lock_irqsave(&clk_lock, flags); 273 spin_lock_irqsave(&clk_lock, flags);
430 274
@@ -446,7 +290,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
446 unsigned prescale; 290 unsigned prescale;
447 unsigned long actual; 291 unsigned long actual;
448 292
449 if (!clk->programmable) 293 if (!clk_is_programmable(clk))
450 return -EINVAL; 294 return -EINVAL;
451 if (clk->users) 295 if (clk->users)
452 return -EBUSY; 296 return -EBUSY;
@@ -484,7 +328,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
484 328
485 if (clk->users) 329 if (clk->users)
486 return -EBUSY; 330 return -EBUSY;
487 if (!parent->primary || !clk->programmable) 331 if (!clk_is_primary(parent) || !clk_is_programmable(clk))
488 return -EINVAL; 332 return -EINVAL;
489 spin_lock_irqsave(&clk_lock, flags); 333 spin_lock_irqsave(&clk_lock, flags);
490 334
@@ -497,6 +341,18 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
497} 341}
498EXPORT_SYMBOL(clk_set_parent); 342EXPORT_SYMBOL(clk_set_parent);
499 343
344/* establish PCK0..PCK3 parentage and rate */
345static void init_programmable_clock(struct clk *clk)
346{
347 struct clk *parent;
348 u32 pckr;
349
350 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
351 parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
352 clk->parent = parent;
353 clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));
354}
355
500#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ 356#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
501 357
502/*------------------------------------------------------------------------*/ 358/*------------------------------------------------------------------------*/
@@ -506,6 +362,7 @@ EXPORT_SYMBOL(clk_set_parent);
506static int at91_clk_show(struct seq_file *s, void *unused) 362static int at91_clk_show(struct seq_file *s, void *unused)
507{ 363{
508 u32 scsr, pcsr, sr; 364 u32 scsr, pcsr, sr;
365 struct clk *clk;
509 unsigned i; 366 unsigned i;
510 367
511 seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR)); 368 seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
@@ -523,9 +380,8 @@ static int at91_clk_show(struct seq_file *s, void *unused)
523 380
524 seq_printf(s, "\n"); 381 seq_printf(s, "\n");
525 382
526 for (i = 0; i < ARRAY_SIZE(clock_list); i++) { 383 list_for_each_entry(clk, &clocks, node) {
527 char *state; 384 char *state;
528 struct clk *clk = clock_list[i];
529 385
530 if (clk->mode == pmc_sys_mode) 386 if (clk->mode == pmc_sys_mode)
531 state = (scsr & clk->pmc_mask) ? "on" : "off"; 387 state = (scsr & clk->pmc_mask) ? "on" : "off";
@@ -570,6 +426,28 @@ postcore_initcall(at91_clk_debugfs_init);
570 426
571/*------------------------------------------------------------------------*/ 427/*------------------------------------------------------------------------*/
572 428
429/* Register a new clock */
430int __init clk_register(struct clk *clk)
431{
432 if (clk_is_peripheral(clk)) {
433 clk->parent = &mck;
434 clk->mode = pmc_periph_mode;
435 list_add_tail(&clk->node, &clocks);
436 }
437#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
438 else if (clk_is_programmable(clk)) {
439 clk->mode = pmc_sys_mode;
440 init_programmable_clock(clk);
441 list_add_tail(&clk->node, &clocks);
442 }
443#endif
444
445 return 0;
446}
447
448
449/*------------------------------------------------------------------------*/
450
573static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg) 451static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
574{ 452{
575 unsigned mul, div; 453 unsigned mul, div;
@@ -640,20 +518,17 @@ fail:
640 return 0; 518 return 0;
641} 519}
642 520
643
644/* 521/*
645 * Several unused clocks may be active. Turn them off. 522 * Several unused clocks may be active. Turn them off.
646 */ 523 */
647static void at91_periphclk_reset(void) 524static void __init at91_periphclk_reset(void)
648{ 525{
649 unsigned long reg; 526 unsigned long reg;
650 int i; 527 struct clk *clk;
651 528
652 reg = at91_sys_read(AT91_PMC_PCSR); 529 reg = at91_sys_read(AT91_PMC_PCSR);
653 530
654 for (i = 0; i < ARRAY_SIZE(clock_list); i++) { 531 list_for_each_entry(clk, &clocks, node) {
655 struct clk *clk = clock_list[i];
656
657 if (clk->mode != pmc_periph_mode) 532 if (clk->mode != pmc_periph_mode)
658 continue; 533 continue;
659 534
@@ -664,11 +539,25 @@ static void at91_periphclk_reset(void)
664 at91_sys_write(AT91_PMC_PCDR, reg); 539 at91_sys_write(AT91_PMC_PCDR, reg);
665} 540}
666 541
542static struct clk *const standard_pmc_clocks[] __initdata = {
543 /* four primary clocks */
544 &clk32k,
545 &main_clk,
546 &plla,
547 &pllb,
548
549 /* PLLB children (USB) */
550 &udpck,
551 &uhpck,
552
553 /* MCK */
554 &mck
555};
556
667int __init at91_clock_init(unsigned long main_clock) 557int __init at91_clock_init(unsigned long main_clock)
668{ 558{
669 unsigned tmp, freq, mckr; 559 unsigned tmp, freq, mckr;
670 560 int i;
671 spin_lock_init(&clk_lock);
672 561
673 /* 562 /*
674 * When the bootloader initialized the main oscillator correctly, 563 * When the bootloader initialized the main oscillator correctly,
@@ -709,11 +598,15 @@ int __init at91_clock_init(unsigned long main_clock)
709 * For now, assume this parentage won't change. 598 * For now, assume this parentage won't change.
710 */ 599 */
711 mckr = at91_sys_read(AT91_PMC_MCKR); 600 mckr = at91_sys_read(AT91_PMC_MCKR);
712 mck.parent = clock_list[mckr & AT91_PMC_CSS]; 601 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
713 freq = mck.parent->rate_hz; 602 freq = mck.parent->rate_hz;
714 freq /= (1 << ((mckr >> 2) & 3)); /* prescale */ 603 freq /= (1 << ((mckr >> 2) & 3)); /* prescale */
715 mck.rate_hz = freq / (1 + ((mckr >> 8) & 3)); /* mdiv */ 604 mck.rate_hz = freq / (1 + ((mckr >> 8) & 3)); /* mdiv */
716 605
606 /* Register the PMC's standard clocks */
607 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
608 list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
609
717 /* MCK and CPU clock are "always on" */ 610 /* MCK and CPU clock are "always on" */
718 clk_enable(&mck); 611 clk_enable(&mck);
719 612
@@ -722,35 +615,8 @@ int __init at91_clock_init(unsigned long main_clock)
722 (unsigned) main_clock / 1000000, 615 (unsigned) main_clock / 1000000,
723 ((unsigned) main_clock % 1000000) / 1000); 616 ((unsigned) main_clock % 1000000) / 1000);
724 617
725#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
726 /* establish PCK0..PCK3 parentage */
727 for (tmp = 0; tmp < ARRAY_SIZE(clock_list); tmp++) {
728 struct clk *clk = clock_list[tmp], *parent;
729 u32 pckr;
730
731 if (!clk->programmable)
732 continue;
733
734 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
735 parent = clock_list[pckr & AT91_PMC_CSS];
736 clk->parent = parent;
737 clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));
738
739 if (clk->users == 0) {
740 /* not being used, so switch it off */
741 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
742 }
743 }
744#else
745 /* disable all programmable clocks */ 618 /* disable all programmable clocks */
746 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 | AT91_PMC_PCK1 | AT91_PMC_PCK2 | AT91_PMC_PCK3); 619 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 | AT91_PMC_PCK1 | AT91_PMC_PCK2 | AT91_PMC_PCK3);
747#endif
748
749 /* enable the PIO clocks */
750 clk_enable(&pioA_clk);
751 clk_enable(&pioB_clk);
752 clk_enable(&pioC_clk);
753 clk_enable(&pioD_clk);
754 620
755 /* disable all other unused peripheral clocks */ 621 /* disable all other unused peripheral clocks */
756 at91_periphclk_reset(); 622 at91_periphclk_reset();
diff --git a/arch/arm/mach-at91rm9200/clock.h b/arch/arm/mach-at91rm9200/clock.h
new file mode 100644
index 000000000000..0592e662ab37
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/clock.h
@@ -0,0 +1,30 @@
1/*
2 * linux/arch/arm/mach-at91rm9200/clock.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#define CLK_TYPE_PRIMARY 0x1
10#define CLK_TYPE_PLL 0x2
11#define CLK_TYPE_PROGRAMMABLE 0x4
12#define CLK_TYPE_PERIPHERAL 0x8
13
14
15struct clk {
16 struct list_head node;
17 const char *name; /* unique clock name */
18 const char *function; /* function of the clock */
19 struct device *dev; /* device associated with function */
20 unsigned long rate_hz;
21 struct clk *parent;
22 u32 pmc_mask;
23 void (*mode)(struct clk *, int);
24 unsigned id:2; /* PCK0..3, or 32k/main/a/b */
25 unsigned type; /* clock type */
26 u16 users;
27};
28
29
30extern int __init clk_register(struct clk *clk);
diff --git a/arch/arm/mach-at91rm9200/devices.c b/arch/arm/mach-at91rm9200/devices.c
index 4352acb88178..01525530c287 100644
--- a/arch/arm/mach-at91rm9200/devices.c
+++ b/arch/arm/mach-at91rm9200/devices.c
@@ -35,13 +35,13 @@ static struct at91_usbh_data usbh_data;
35 35
36static struct resource at91_usbh_resources[] = { 36static struct resource at91_usbh_resources[] = {
37 [0] = { 37 [0] = {
38 .start = AT91_UHP_BASE, 38 .start = AT91RM9200_UHP_BASE,
39 .end = AT91_UHP_BASE + SZ_1M - 1, 39 .end = AT91RM9200_UHP_BASE + SZ_1M - 1,
40 .flags = IORESOURCE_MEM, 40 .flags = IORESOURCE_MEM,
41 }, 41 },
42 [1] = { 42 [1] = {
43 .start = AT91_ID_UHP, 43 .start = AT91RM9200_ID_UHP,
44 .end = AT91_ID_UHP, 44 .end = AT91RM9200_ID_UHP,
45 .flags = IORESOURCE_IRQ, 45 .flags = IORESOURCE_IRQ,
46 }, 46 },
47}; 47};
@@ -80,13 +80,13 @@ static struct at91_udc_data udc_data;
80 80
81static struct resource at91_udc_resources[] = { 81static struct resource at91_udc_resources[] = {
82 [0] = { 82 [0] = {
83 .start = AT91_BASE_UDP, 83 .start = AT91RM9200_BASE_UDP,
84 .end = AT91_BASE_UDP + SZ_16K - 1, 84 .end = AT91RM9200_BASE_UDP + SZ_16K - 1,
85 .flags = IORESOURCE_MEM, 85 .flags = IORESOURCE_MEM,
86 }, 86 },
87 [1] = { 87 [1] = {
88 .start = AT91_ID_UDP, 88 .start = AT91RM9200_ID_UDP,
89 .end = AT91_ID_UDP, 89 .end = AT91RM9200_ID_UDP,
90 .flags = IORESOURCE_IRQ, 90 .flags = IORESOURCE_IRQ,
91 }, 91 },
92}; 92};
@@ -131,13 +131,13 @@ static struct at91_eth_data eth_data;
131 131
132static struct resource at91_eth_resources[] = { 132static struct resource at91_eth_resources[] = {
133 [0] = { 133 [0] = {
134 .start = AT91_BASE_EMAC, 134 .start = AT91_VA_BASE_EMAC,
135 .end = AT91_BASE_EMAC + SZ_16K - 1, 135 .end = AT91_VA_BASE_EMAC + SZ_16K - 1,
136 .flags = IORESOURCE_MEM, 136 .flags = IORESOURCE_MEM,
137 }, 137 },
138 [1] = { 138 [1] = {
139 .start = AT91_ID_EMAC, 139 .start = AT91RM9200_ID_EMAC,
140 .end = AT91_ID_EMAC, 140 .end = AT91RM9200_ID_EMAC,
141 .flags = IORESOURCE_IRQ, 141 .flags = IORESOURCE_IRQ,
142 }, 142 },
143}; 143};
@@ -263,13 +263,13 @@ static struct at91_mmc_data mmc_data;
263 263
264static struct resource at91_mmc_resources[] = { 264static struct resource at91_mmc_resources[] = {
265 [0] = { 265 [0] = {
266 .start = AT91_BASE_MCI, 266 .start = AT91RM9200_BASE_MCI,
267 .end = AT91_BASE_MCI + SZ_16K - 1, 267 .end = AT91RM9200_BASE_MCI + SZ_16K - 1,
268 .flags = IORESOURCE_MEM, 268 .flags = IORESOURCE_MEM,
269 }, 269 },
270 [1] = { 270 [1] = {
271 .start = AT91_ID_MCI, 271 .start = AT91RM9200_ID_MCI,
272 .end = AT91_ID_MCI, 272 .end = AT91RM9200_ID_MCI,
273 .flags = IORESOURCE_IRQ, 273 .flags = IORESOURCE_IRQ,
274 }, 274 },
275}; 275};
@@ -423,13 +423,13 @@ static u64 spi_dmamask = 0xffffffffUL;
423 423
424static struct resource at91_spi_resources[] = { 424static struct resource at91_spi_resources[] = {
425 [0] = { 425 [0] = {
426 .start = AT91_BASE_SPI, 426 .start = AT91RM9200_BASE_SPI,
427 .end = AT91_BASE_SPI + SZ_16K - 1, 427 .end = AT91RM9200_BASE_SPI + SZ_16K - 1,
428 .flags = IORESOURCE_MEM, 428 .flags = IORESOURCE_MEM,
429 }, 429 },
430 [1] = { 430 [1] = {
431 .start = AT91_ID_SPI, 431 .start = AT91RM9200_ID_SPI,
432 .end = AT91_ID_SPI, 432 .end = AT91RM9200_ID_SPI,
433 .flags = IORESOURCE_IRQ, 433 .flags = IORESOURCE_IRQ,
434 }, 434 },
435}; 435};
@@ -582,13 +582,13 @@ static inline void configure_dbgu_pins(void)
582 582
583static struct resource uart0_resources[] = { 583static struct resource uart0_resources[] = {
584 [0] = { 584 [0] = {
585 .start = AT91_BASE_US0, 585 .start = AT91RM9200_BASE_US0,
586 .end = AT91_BASE_US0 + SZ_16K - 1, 586 .end = AT91RM9200_BASE_US0 + SZ_16K - 1,
587 .flags = IORESOURCE_MEM, 587 .flags = IORESOURCE_MEM,
588 }, 588 },
589 [1] = { 589 [1] = {
590 .start = AT91_ID_US0, 590 .start = AT91RM9200_ID_US0,
591 .end = AT91_ID_US0, 591 .end = AT91RM9200_ID_US0,
592 .flags = IORESOURCE_IRQ, 592 .flags = IORESOURCE_IRQ,
593 }, 593 },
594}; 594};
@@ -624,13 +624,13 @@ static inline void configure_usart0_pins(void)
624 624
625static struct resource uart1_resources[] = { 625static struct resource uart1_resources[] = {
626 [0] = { 626 [0] = {
627 .start = AT91_BASE_US1, 627 .start = AT91RM9200_BASE_US1,
628 .end = AT91_BASE_US1 + SZ_16K - 1, 628 .end = AT91RM9200_BASE_US1 + SZ_16K - 1,
629 .flags = IORESOURCE_MEM, 629 .flags = IORESOURCE_MEM,
630 }, 630 },
631 [1] = { 631 [1] = {
632 .start = AT91_ID_US1, 632 .start = AT91RM9200_ID_US1,
633 .end = AT91_ID_US1, 633 .end = AT91RM9200_ID_US1,
634 .flags = IORESOURCE_IRQ, 634 .flags = IORESOURCE_IRQ,
635 }, 635 },
636}; 636};
@@ -665,13 +665,13 @@ static inline void configure_usart1_pins(void)
665 665
666static struct resource uart2_resources[] = { 666static struct resource uart2_resources[] = {
667 [0] = { 667 [0] = {
668 .start = AT91_BASE_US2, 668 .start = AT91RM9200_BASE_US2,
669 .end = AT91_BASE_US2 + SZ_16K - 1, 669 .end = AT91RM9200_BASE_US2 + SZ_16K - 1,
670 .flags = IORESOURCE_MEM, 670 .flags = IORESOURCE_MEM,
671 }, 671 },
672 [1] = { 672 [1] = {
673 .start = AT91_ID_US2, 673 .start = AT91RM9200_ID_US2,
674 .end = AT91_ID_US2, 674 .end = AT91RM9200_ID_US2,
675 .flags = IORESOURCE_IRQ, 675 .flags = IORESOURCE_IRQ,
676 }, 676 },
677}; 677};
@@ -700,13 +700,13 @@ static inline void configure_usart2_pins(void)
700 700
701static struct resource uart3_resources[] = { 701static struct resource uart3_resources[] = {
702 [0] = { 702 [0] = {
703 .start = AT91_BASE_US3, 703 .start = AT91RM9200_BASE_US3,
704 .end = AT91_BASE_US3 + SZ_16K - 1, 704 .end = AT91RM9200_BASE_US3 + SZ_16K - 1,
705 .flags = IORESOURCE_MEM, 705 .flags = IORESOURCE_MEM,
706 }, 706 },
707 [1] = { 707 [1] = {
708 .start = AT91_ID_US3, 708 .start = AT91RM9200_ID_US3,
709 .end = AT91_ID_US3, 709 .end = AT91RM9200_ID_US3,
710 .flags = IORESOURCE_IRQ, 710 .flags = IORESOURCE_IRQ,
711 }, 711 },
712}; 712};
diff --git a/arch/arm/mach-at91rm9200/generic.h b/arch/arm/mach-at91rm9200/generic.h
index 7979d8ab7e07..694e411e285f 100644
--- a/arch/arm/mach-at91rm9200/generic.h
+++ b/arch/arm/mach-at91rm9200/generic.h
@@ -8,18 +8,17 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11 /* Processors */
12extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks);
13
11 /* Interrupts */ 14 /* Interrupts */
12extern void __init at91rm9200_init_irq(unsigned int priority[]); 15extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
13extern void __init at91_aic_init(unsigned int priority[]); 16extern void __init at91_aic_init(unsigned int priority[]);
14extern void __init at91_gpio_irq_setup(unsigned banks);
15 17
16 /* Timer */ 18 /* Timer */
17struct sys_timer; 19struct sys_timer;
18extern struct sys_timer at91rm9200_timer; 20extern struct sys_timer at91rm9200_timer;
19 21
20 /* Memory Map */
21extern void __init at91rm9200_map_io(void);
22
23 /* Clocks */ 22 /* Clocks */
24extern int __init at91_clock_init(unsigned long main_clock); 23extern int __init at91_clock_init(unsigned long main_clock);
25struct device; 24struct device;
@@ -29,3 +28,14 @@ extern void __init at91_clock_associate(const char *id, struct device *dev, cons
29extern void at91_irq_suspend(void); 28extern void at91_irq_suspend(void);
30extern void at91_irq_resume(void); 29extern void at91_irq_resume(void);
31 30
31 /* GPIO */
32#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */
33#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */
34
35struct at91_gpio_bank {
36 unsigned short id; /* peripheral ID */
37 unsigned long offset; /* offset from system peripheral base */
38 struct clk *clock; /* associated clock */
39};
40extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
41extern void __init at91_gpio_irq_setup(void);
diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c
index cec199fd6721..58c9bf5e9520 100644
--- a/arch/arm/mach-at91rm9200/gpio.c
+++ b/arch/arm/mach-at91rm9200/gpio.c
@@ -9,6 +9,7 @@
9 * (at your option) any later version. 9 * (at your option) any later version.
10 */ 10 */
11 11
12#include <linux/clk.h>
12#include <linux/errno.h> 13#include <linux/errno.h>
13#include <linux/interrupt.h> 14#include <linux/interrupt.h>
14#include <linux/irq.h> 15#include <linux/irq.h>
@@ -20,12 +21,12 @@
20#include <asm/hardware.h> 21#include <asm/hardware.h>
21#include <asm/arch/gpio.h> 22#include <asm/arch/gpio.h>
22 23
23static const u32 pio_controller_offset[4] = { 24#include "generic.h"
24 AT91_PIOA, 25
25 AT91_PIOB, 26
26 AT91_PIOC, 27static struct at91_gpio_bank *gpio;
27 AT91_PIOD, 28static int gpio_banks;
28}; 29
29 30
30static inline void __iomem *pin_to_controller(unsigned pin) 31static inline void __iomem *pin_to_controller(unsigned pin)
31{ 32{
@@ -33,8 +34,8 @@ static inline void __iomem *pin_to_controller(unsigned pin)
33 34
34 pin -= PIN_BASE; 35 pin -= PIN_BASE;
35 pin /= 32; 36 pin /= 32;
36 if (likely(pin < BGA_GPIO_BANKS)) 37 if (likely(pin < gpio_banks))
37 return sys_base + pio_controller_offset[pin]; 38 return sys_base + gpio[pin].offset;
38 39
39 return NULL; 40 return NULL;
40} 41}
@@ -179,7 +180,6 @@ EXPORT_SYMBOL(at91_set_multi_drive);
179 180
180/*--------------------------------------------------------------------------*/ 181/*--------------------------------------------------------------------------*/
181 182
182
183/* 183/*
184 * assuming the pin is muxed as a gpio output, set its value. 184 * assuming the pin is muxed as a gpio output, set its value.
185 */ 185 */
@@ -216,8 +216,8 @@ EXPORT_SYMBOL(at91_get_gpio_value);
216 216
217#ifdef CONFIG_PM 217#ifdef CONFIG_PM
218 218
219static u32 wakeups[BGA_GPIO_BANKS]; 219static u32 wakeups[MAX_GPIO_BANKS];
220static u32 backups[BGA_GPIO_BANKS]; 220static u32 backups[MAX_GPIO_BANKS];
221 221
222static int gpio_irq_set_wake(unsigned pin, unsigned state) 222static int gpio_irq_set_wake(unsigned pin, unsigned state)
223{ 223{
@@ -226,7 +226,7 @@ static int gpio_irq_set_wake(unsigned pin, unsigned state)
226 pin -= PIN_BASE; 226 pin -= PIN_BASE;
227 pin /= 32; 227 pin /= 32;
228 228
229 if (unlikely(pin >= BGA_GPIO_BANKS)) 229 if (unlikely(pin >= MAX_GPIO_BANKS))
230 return -EINVAL; 230 return -EINVAL;
231 231
232 if (state) 232 if (state)
@@ -241,8 +241,8 @@ void at91_gpio_suspend(void)
241{ 241{
242 int i; 242 int i;
243 243
244 for (i = 0; i < BGA_GPIO_BANKS; i++) { 244 for (i = 0; i < gpio_banks; i++) {
245 u32 pio = pio_controller_offset[i]; 245 u32 pio = gpio[i].offset;
246 246
247 /* 247 /*
248 * Note: drivers should have disabled GPIO interrupts that 248 * Note: drivers should have disabled GPIO interrupts that
@@ -257,14 +257,14 @@ void at91_gpio_suspend(void)
257 * first place! 257 * first place!
258 */ 258 */
259 backups[i] = at91_sys_read(pio + PIO_IMR); 259 backups[i] = at91_sys_read(pio + PIO_IMR);
260 at91_sys_write(pio_controller_offset[i] + PIO_IDR, backups[i]); 260 at91_sys_write(pio + PIO_IDR, backups[i]);
261 at91_sys_write(pio_controller_offset[i] + PIO_IER, wakeups[i]); 261 at91_sys_write(pio + PIO_IER, wakeups[i]);
262 262
263 if (!wakeups[i]) { 263 if (!wakeups[i]) {
264 disable_irq_wake(AT91_ID_PIOA + i); 264 disable_irq_wake(gpio[i].id);
265 at91_sys_write(AT91_PMC_PCDR, 1 << (AT91_ID_PIOA + i)); 265 at91_sys_write(AT91_PMC_PCDR, 1 << gpio[i].id);
266 } else { 266 } else {
267 enable_irq_wake(AT91_ID_PIOA + i); 267 enable_irq_wake(gpio[i].id);
268#ifdef CONFIG_PM_DEBUG 268#ifdef CONFIG_PM_DEBUG
269 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", "ABCD"[i], wakeups[i]); 269 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", "ABCD"[i], wakeups[i]);
270#endif 270#endif
@@ -276,16 +276,13 @@ void at91_gpio_resume(void)
276{ 276{
277 int i; 277 int i;
278 278
279 for (i = 0; i < BGA_GPIO_BANKS; i++) { 279 for (i = 0; i < gpio_banks; i++) {
280 at91_sys_write(pio_controller_offset[i] + PIO_IDR, wakeups[i]); 280 u32 pio = gpio[i].offset;
281 at91_sys_write(pio_controller_offset[i] + PIO_IER, backups[i]);
282 }
283 281
284 at91_sys_write(AT91_PMC_PCER, 282 at91_sys_write(pio + PIO_IDR, wakeups[i]);
285 (1 << AT91_ID_PIOA) 283 at91_sys_write(pio + PIO_IER, backups[i]);
286 | (1 << AT91_ID_PIOB) 284 at91_sys_write(AT91_PMC_PCER, 1 << gpio[i].id);
287 | (1 << AT91_ID_PIOC) 285 }
288 | (1 << AT91_ID_PIOD));
289} 286}
290 287
291#else 288#else
@@ -377,20 +374,25 @@ static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs
377 /* now it may re-trigger */ 374 /* now it may re-trigger */
378} 375}
379 376
380/* call this from board-specific init_irq */ 377/*--------------------------------------------------------------------------*/
381void __init at91_gpio_irq_setup(unsigned banks) 378
379/*
380 * Called from the processor-specific init to enable GPIO interrupt support.
381 */
382void __init at91_gpio_irq_setup(void)
382{ 383{
383 unsigned pioc, pin, id; 384 unsigned pioc, pin;
384 385
385 if (banks > 4) 386 for (pioc = 0, pin = PIN_BASE;
386 banks = 4; 387 pioc < gpio_banks;
387 for (pioc = 0, pin = PIN_BASE, id = AT91_ID_PIOA; 388 pioc++) {
388 pioc < banks;
389 pioc++, id++) {
390 void __iomem *controller; 389 void __iomem *controller;
390 unsigned id = gpio[pioc].id;
391 unsigned i; 391 unsigned i;
392 392
393 controller = (void __iomem *) AT91_VA_BASE_SYS + pio_controller_offset[pioc]; 393 clk_enable(gpio[pioc].clock); /* enable PIO controller's clock */
394
395 controller = (void __iomem *) AT91_VA_BASE_SYS + gpio[pioc].offset;
394 __raw_writel(~0, controller + PIO_IDR); 396 __raw_writel(~0, controller + PIO_IDR);
395 397
396 set_irq_data(id, (void *) pin); 398 set_irq_data(id, (void *) pin);
@@ -408,5 +410,16 @@ void __init at91_gpio_irq_setup(unsigned banks)
408 410
409 set_irq_chained_handler(id, gpio_irq_handler); 411 set_irq_chained_handler(id, gpio_irq_handler);
410 } 412 }
411 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, banks); 413 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
414}
415
416/*
417 * Called from the processor-specific init to enable GPIO pin support.
418 */
419void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
420{
421 BUG_ON(nr_banks > MAX_GPIO_BANKS);
422
423 gpio = data;
424 gpio_banks = nr_banks;
412} 425}
diff --git a/arch/arm/mach-at91rm9200/irq.c b/arch/arm/mach-at91rm9200/irq.c
index c3a5e777f9f8..3e488117ca91 100644
--- a/arch/arm/mach-at91rm9200/irq.c
+++ b/arch/arm/mach-at91rm9200/irq.c
@@ -34,8 +34,6 @@
34#include <asm/mach/irq.h> 34#include <asm/mach/irq.h>
35#include <asm/mach/map.h> 35#include <asm/mach/map.h>
36 36
37#include "generic.h"
38
39 37
40static void at91_aic_mask_irq(unsigned int irq) 38static void at91_aic_mask_irq(unsigned int irq)
41{ 39{
@@ -61,12 +59,12 @@ static int at91_aic_set_type(unsigned irq, unsigned type)
61 srctype = AT91_AIC_SRCTYPE_RISING; 59 srctype = AT91_AIC_SRCTYPE_RISING;
62 break; 60 break;
63 case IRQT_LOW: 61 case IRQT_LOW:
64 if ((irq > AT91_ID_FIQ) && (irq < AT91_ID_IRQ0)) /* only supported on external interrupts */ 62 if ((irq > AT91_ID_FIQ) && (irq < AT91RM9200_ID_IRQ0)) /* only supported on external interrupts */
65 return -EINVAL; 63 return -EINVAL;
66 srctype = AT91_AIC_SRCTYPE_LOW; 64 srctype = AT91_AIC_SRCTYPE_LOW;
67 break; 65 break;
68 case IRQT_FALLING: 66 case IRQT_FALLING:
69 if ((irq > AT91_ID_FIQ) && (irq < AT91_ID_IRQ0)) /* only supported on external interrupts */ 67 if ((irq > AT91_ID_FIQ) && (irq < AT91RM9200_ID_IRQ0)) /* only supported on external interrupts */
70 return -EINVAL; 68 return -EINVAL;
71 srctype = AT91_AIC_SRCTYPE_FALLING; 69 srctype = AT91_AIC_SRCTYPE_FALLING;
72 break; 70 break;
diff --git a/arch/arm/mach-at91rm9200/pm.c b/arch/arm/mach-at91rm9200/pm.c
index 47e5480feb7e..32c95d8eaacf 100644
--- a/arch/arm/mach-at91rm9200/pm.c
+++ b/arch/arm/mach-at91rm9200/pm.c
@@ -123,13 +123,13 @@ static int at91_pm_enter(suspend_state_t state)
123 (at91_sys_read(AT91_PMC_PCSR) 123 (at91_sys_read(AT91_PMC_PCSR)
124 | (1 << AT91_ID_FIQ) 124 | (1 << AT91_ID_FIQ)
125 | (1 << AT91_ID_SYS) 125 | (1 << AT91_ID_SYS)
126 | (1 << AT91_ID_IRQ0) 126 | (1 << AT91RM9200_ID_IRQ0)
127 | (1 << AT91_ID_IRQ1) 127 | (1 << AT91RM9200_ID_IRQ1)
128 | (1 << AT91_ID_IRQ2) 128 | (1 << AT91RM9200_ID_IRQ2)
129 | (1 << AT91_ID_IRQ3) 129 | (1 << AT91RM9200_ID_IRQ3)
130 | (1 << AT91_ID_IRQ4) 130 | (1 << AT91RM9200_ID_IRQ4)
131 | (1 << AT91_ID_IRQ5) 131 | (1 << AT91RM9200_ID_IRQ5)
132 | (1 << AT91_ID_IRQ6)) 132 | (1 << AT91RM9200_ID_IRQ6))
133 & at91_sys_read(AT91_AIC_IMR), 133 & at91_sys_read(AT91_AIC_IMR),
134 state); 134 state);
135 135
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index f1b740083aee..e346b03cd921 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -15,6 +15,12 @@ config MACH_EDB9302
15 Say 'Y' here if you want your kernel to support the Cirrus 15 Say 'Y' here if you want your kernel to support the Cirrus
16 Logic EDB9302 Evaluation Board. 16 Logic EDB9302 Evaluation Board.
17 17
18config MACH_EDB9312
19 bool "Support Cirrus Logic EDB9312"
20 help
21 Say 'Y' here if you want your kernel to support the Cirrus
22 Logic EDB9312 Evaluation Board.
23
18config MACH_EDB9315 24config MACH_EDB9315
19 bool "Support Cirrus Logic EDB9315" 25 bool "Support Cirrus Logic EDB9315"
20 help 26 help
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index 1f5a6b0487ee..c2eb18b530c2 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -7,6 +7,7 @@ obj-n :=
7obj- := 7obj- :=
8 8
9obj-$(CONFIG_MACH_EDB9302) += edb9302.o 9obj-$(CONFIG_MACH_EDB9302) += edb9302.o
10obj-$(CONFIG_MACH_EDB9312) += edb9312.o
10obj-$(CONFIG_MACH_EDB9315) += edb9315.o 11obj-$(CONFIG_MACH_EDB9315) += edb9315.o
11obj-$(CONFIG_MACH_EDB9315A) += edb9315a.o 12obj-$(CONFIG_MACH_EDB9315A) += edb9315a.o
12obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o 13obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o
diff --git a/arch/arm/mach-ep93xx/edb9312.c b/arch/arm/mach-ep93xx/edb9312.c
new file mode 100644
index 000000000000..9e399211108c
--- /dev/null
+++ b/arch/arm/mach-ep93xx/edb9312.c
@@ -0,0 +1,63 @@
1/*
2 * arch/arm/mach-ep93xx/edb9312.c
3 * Cirrus Logic EDB9312 support.
4 *
5 * Copyright (C) 2006 Infosys Technologies Limited
6 * Toufeeq Hussain <toufeeq_hussain@infosys.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or (at
11 * your option) any later version.
12 */
13
14#include <linux/config.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/mm.h>
18#include <linux/sched.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/mtd/physmap.h>
22#include <linux/platform_device.h>
23#include <asm/io.h>
24#include <asm/hardware.h>
25#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
27
28static struct physmap_flash_data edb9312_flash_data = {
29 .width = 4,
30};
31
32static struct resource edb9312_flash_resource = {
33 .start = 0x60000000,
34 .end = 0x61ffffff,
35 .flags = IORESOURCE_MEM,
36};
37
38static struct platform_device edb9312_flash = {
39 .name = "physmap-flash",
40 .id = 0,
41 .dev = {
42 .platform_data = &edb9312_flash_data,
43 },
44 .num_resources = 1,
45 .resource = &edb9312_flash_resource,
46};
47
48static void __init edb9312_init_machine(void)
49{
50 ep93xx_init_devices();
51 platform_device_register(&edb9312_flash);
52}
53
54MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
55 /* Maintainer: Toufeeq Hussain <toufeeq_hussain@infosys.com> */
56 .phys_io = EP93XX_APB_PHYS_BASE,
57 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
58 .boot_params = 0x00000100,
59 .map_io = ep93xx_map_io,
60 .init_irq = ep93xx_init_irq,
61 .timer = &ep93xx_timer,
62 .init_machine = edb9312_init_machine,
63MACHINE_END
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 823e25d4547e..a1ae49df5c3b 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -69,16 +69,16 @@ dc21285_read_config(struct pci_bus *bus, unsigned int devfn, int where,
69 if (addr) 69 if (addr)
70 switch (size) { 70 switch (size) {
71 case 1: 71 case 1:
72 asm("ldr%?b %0, [%1, %2]" 72 asm("ldrb %0, [%1, %2]"
73 : "=r" (v) : "r" (addr), "r" (where)); 73 : "=r" (v) : "r" (addr), "r" (where) : "cc");
74 break; 74 break;
75 case 2: 75 case 2:
76 asm("ldr%?h %0, [%1, %2]" 76 asm("ldrh %0, [%1, %2]"
77 : "=r" (v) : "r" (addr), "r" (where)); 77 : "=r" (v) : "r" (addr), "r" (where) : "cc");
78 break; 78 break;
79 case 4: 79 case 4:
80 asm("ldr%? %0, [%1, %2]" 80 asm("ldr %0, [%1, %2]"
81 : "=r" (v) : "r" (addr), "r" (where)); 81 : "=r" (v) : "r" (addr), "r" (where) : "cc");
82 break; 82 break;
83 } 83 }
84 84
@@ -103,16 +103,19 @@ dc21285_write_config(struct pci_bus *bus, unsigned int devfn, int where,
103 if (addr) 103 if (addr)
104 switch (size) { 104 switch (size) {
105 case 1: 105 case 1:
106 asm("str%?b %0, [%1, %2]" 106 asm("strb %0, [%1, %2]"
107 : : "r" (value), "r" (addr), "r" (where)); 107 : : "r" (value), "r" (addr), "r" (where)
108 : "cc");
108 break; 109 break;
109 case 2: 110 case 2:
110 asm("str%?h %0, [%1, %2]" 111 asm("strh %0, [%1, %2]"
111 : : "r" (value), "r" (addr), "r" (where)); 112 : : "r" (value), "r" (addr), "r" (where)
113 : "cc");
112 break; 114 break;
113 case 4: 115 case 4:
114 asm("str%? %0, [%1, %2]" 116 asm("str %0, [%1, %2]"
115 : : "r" (value), "r" (addr), "r" (where)); 117 : : "r" (value), "r" (addr), "r" (where)
118 : "cc");
116 break; 119 break;
117 } 120 }
118 121
diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig
new file mode 100644
index 000000000000..c072d94070da
--- /dev/null
+++ b/arch/arm/mach-iop32x/Kconfig
@@ -0,0 +1,35 @@
1if ARCH_IOP32X
2
3menu "IOP32x Implementation Options"
4
5comment "IOP32x Platform Types"
6
7config MACH_GLANTANK
8 bool "Enable support for the IO-Data GLAN Tank"
9 help
10 Say Y here if you want to run your kernel on the GLAN Tank
11 NAS appliance or machines from IO-Data's HDL-Gxxx, HDL-GWxxx
12 and HDL-GZxxx series.
13
14config ARCH_IQ80321
15 bool "Enable support for IQ80321"
16 help
17 Say Y here if you want to run your kernel on the Intel IQ80321
18 evaluation kit for the IOP321 processor.
19
20config ARCH_IQ31244
21 bool "Enable support for EP80219/IQ31244"
22 help
23 Say Y here if you want to run your kernel on the Intel EP80219
24 evaluation kit for the Intel 80219 processor (a IOP321 variant)
25 or the IQ31244 evaluation kit for the IOP321 processor.
26
27config MACH_N2100
28 bool "Enable support for the Thecus n2100"
29 help
30 Say Y here if you want to run your kernel on the Thecus n2100
31 NAS appliance.
32
33endmenu
34
35endif
diff --git a/arch/arm/mach-iop32x/Makefile b/arch/arm/mach-iop32x/Makefile
new file mode 100644
index 000000000000..7b05b37e1f94
--- /dev/null
+++ b/arch/arm/mach-iop32x/Makefile
@@ -0,0 +1,13 @@
1#
2# Makefile for the linux kernel.
3#
4
5obj-y := irq.o
6obj-m :=
7obj-n :=
8obj- :=
9
10obj-$(CONFIG_MACH_GLANTANK) += glantank.o
11obj-$(CONFIG_ARCH_IQ80321) += iq80321.o
12obj-$(CONFIG_ARCH_IQ31244) += iq31244.o
13obj-$(CONFIG_MACH_N2100) += n2100.o
diff --git a/arch/arm/mach-iop32x/Makefile.boot b/arch/arm/mach-iop32x/Makefile.boot
new file mode 100644
index 000000000000..47000dccd61f
--- /dev/null
+++ b/arch/arm/mach-iop32x/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0xa0008000
2params_phys-y := 0xa0000100
3initrd_phys-y := 0xa0800000
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
new file mode 100644
index 000000000000..b9b765057dbe
--- /dev/null
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -0,0 +1,195 @@
1/*
2 * arch/arm/mach-iop32x/glantank.c
3 *
4 * Board support code for the GLAN Tank.
5 *
6 * Copyright (C) 2006 Martin Michlmayr <tbm@cyrius.com>
7 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/mm.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/string.h>
20#include <linux/slab.h>
21#include <linux/serial_core.h>
22#include <linux/serial_8250.h>
23#include <linux/mtd/physmap.h>
24#include <linux/platform_device.h>
25#include <asm/hardware.h>
26#include <asm/io.h>
27#include <asm/irq.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/pci.h>
31#include <asm/mach/time.h>
32#include <asm/mach-types.h>
33#include <asm/page.h>
34
35/*
36 * GLAN Tank timer tick configuration.
37 */
38static void __init glantank_timer_init(void)
39{
40 /* 33.333 MHz crystal. */
41 iop3xx_init_time(200000000);
42}
43
44static struct sys_timer glantank_timer = {
45 .init = glantank_timer_init,
46 .offset = iop3xx_gettimeoffset,
47};
48
49
50/*
51 * GLAN Tank I/O.
52 */
53static struct map_desc glantank_io_desc[] __initdata = {
54 { /* on-board devices */
55 .virtual = GLANTANK_UART,
56 .pfn = __phys_to_pfn(GLANTANK_UART),
57 .length = 0x00100000,
58 .type = MT_DEVICE
59 },
60};
61
62void __init glantank_map_io(void)
63{
64 iop3xx_map_io();
65 iotable_init(glantank_io_desc, ARRAY_SIZE(glantank_io_desc));
66}
67
68
69/*
70 * GLAN Tank PCI.
71 */
72#define INTA IRQ_IOP32X_XINT0
73#define INTB IRQ_IOP32X_XINT1
74#define INTC IRQ_IOP32X_XINT2
75#define INTD IRQ_IOP32X_XINT3
76
77static inline int __init
78glantank_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
79{
80 static int pci_irq_table[][4] = {
81 /*
82 * PCI IDSEL/INTPIN->INTLINE
83 * A B C D
84 */
85 {INTD, INTD, INTD, INTD}, /* UART (8250) */
86 {INTA, INTA, INTA, INTA}, /* Ethernet (E1000) */
87 {INTB, INTB, INTB, INTB}, /* IDE (AEC6280R) */
88 {INTC, INTC, INTC, INTC}, /* USB (NEC) */
89 };
90
91 BUG_ON(pin < 1 || pin > 4);
92
93 return pci_irq_table[slot % 4][pin - 1];
94}
95
96static struct hw_pci glantank_pci __initdata = {
97 .swizzle = pci_std_swizzle,
98 .nr_controllers = 1,
99 .setup = iop3xx_pci_setup,
100 .preinit = iop3xx_pci_preinit,
101 .scan = iop3xx_pci_scan_bus,
102 .map_irq = glantank_pci_map_irq,
103};
104
105static int __init glantank_pci_init(void)
106{
107 if (machine_is_glantank())
108 pci_common_init(&glantank_pci);
109
110 return 0;
111}
112
113subsys_initcall(glantank_pci_init);
114
115
116/*
117 * GLAN Tank machine initialization.
118 */
119static struct physmap_flash_data glantank_flash_data = {
120 .width = 1,
121};
122
123static struct resource glantank_flash_resource = {
124 .start = 0xf0000000,
125 .end = 0xf007ffff,
126 .flags = IORESOURCE_MEM,
127};
128
129static struct platform_device glantank_flash_device = {
130 .name = "physmap-flash",
131 .id = 0,
132 .dev = {
133 .platform_data = &glantank_flash_data,
134 },
135 .num_resources = 1,
136 .resource = &glantank_flash_resource,
137};
138
139static struct plat_serial8250_port glantank_serial_port[] = {
140 {
141 .mapbase = GLANTANK_UART,
142 .membase = (char *)GLANTANK_UART,
143 .irq = IRQ_IOP32X_XINT3,
144 .flags = UPF_SKIP_TEST,
145 .iotype = UPIO_MEM,
146 .regshift = 0,
147 .uartclk = 1843200,
148 },
149 { },
150};
151
152static struct resource glantank_uart_resource = {
153 .start = GLANTANK_UART,
154 .end = GLANTANK_UART + 7,
155 .flags = IORESOURCE_MEM,
156};
157
158static struct platform_device glantank_serial_device = {
159 .name = "serial8250",
160 .id = PLAT8250_DEV_PLATFORM,
161 .dev = {
162 .platform_data = glantank_serial_port,
163 },
164 .num_resources = 1,
165 .resource = &glantank_uart_resource,
166};
167
168static void glantank_power_off(void)
169{
170 __raw_writeb(0x01, 0xfe8d0004);
171
172 while (1)
173 ;
174}
175
176static void __init glantank_init_machine(void)
177{
178 platform_device_register(&iop3xx_i2c0_device);
179 platform_device_register(&iop3xx_i2c1_device);
180 platform_device_register(&glantank_flash_device);
181 platform_device_register(&glantank_serial_device);
182
183 pm_power_off = glantank_power_off;
184}
185
186MACHINE_START(GLANTANK, "GLAN Tank")
187 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
188 .phys_io = GLANTANK_UART,
189 .io_pg_offst = ((GLANTANK_UART) >> 18) & 0xfffc,
190 .boot_params = 0xa0000100,
191 .map_io = glantank_map_io,
192 .init_irq = iop32x_init_irq,
193 .timer = &glantank_timer,
194 .init_machine = glantank_init_machine,
195MACHINE_END
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
new file mode 100644
index 000000000000..be4aedfa0de6
--- /dev/null
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -0,0 +1,293 @@
1/*
2 * arch/arm/mach-iop32x/iq31244.c
3 *
4 * Board support code for the Intel EP80219 and IQ31244 platforms.
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright 2003 (c) MontaVista, Software, Inc.
9 * Copyright (C) 2004 Intel Corp.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/pm.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/serial_core.h>
26#include <linux/serial_8250.h>
27#include <linux/mtd/physmap.h>
28#include <linux/platform_device.h>
29#include <asm/hardware.h>
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/map.h>
34#include <asm/mach/pci.h>
35#include <asm/mach/time.h>
36#include <asm/mach-types.h>
37#include <asm/page.h>
38#include <asm/pgtable.h>
39
40
41/*
42 * The EP80219 and IQ31244 use the same machine ID. To find out
43 * which of the two we're running on, we look at the processor ID.
44 */
45static int is_80219(void)
46{
47 extern int processor_id;
48 return !!((processor_id & 0xffffffe0) == 0x69052e20);
49}
50
51
52/*
53 * EP80219/IQ31244 timer tick configuration.
54 */
55static void __init iq31244_timer_init(void)
56{
57 if (is_80219()) {
58 /* 33.333 MHz crystal. */
59 iop3xx_init_time(200000000);
60 } else {
61 /* 33.000 MHz crystal. */
62 iop3xx_init_time(198000000);
63 }
64}
65
66static struct sys_timer iq31244_timer = {
67 .init = iq31244_timer_init,
68 .offset = iop3xx_gettimeoffset,
69};
70
71
72/*
73 * IQ31244 I/O.
74 */
75static struct map_desc iq31244_io_desc[] __initdata = {
76 { /* on-board devices */
77 .virtual = IQ31244_UART,
78 .pfn = __phys_to_pfn(IQ31244_UART),
79 .length = 0x00100000,
80 .type = MT_DEVICE,
81 },
82};
83
84void __init iq31244_map_io(void)
85{
86 iop3xx_map_io();
87 iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
88}
89
90
91/*
92 * EP80219/IQ31244 PCI.
93 */
94static inline int __init
95ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
96{
97 int irq;
98
99 if (slot == 0) {
100 /* CFlash */
101 irq = IRQ_IOP32X_XINT1;
102 } else if (slot == 1) {
103 /* 82551 Pro 100 */
104 irq = IRQ_IOP32X_XINT0;
105 } else if (slot == 2) {
106 /* PCI-X Slot */
107 irq = IRQ_IOP32X_XINT3;
108 } else if (slot == 3) {
109 /* SATA */
110 irq = IRQ_IOP32X_XINT2;
111 } else {
112 printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
113 "device PCI:%d:%d:%d\n", dev->bus->number,
114 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
115 irq = -1;
116 }
117
118 return irq;
119}
120
121static struct hw_pci ep80219_pci __initdata = {
122 .swizzle = pci_std_swizzle,
123 .nr_controllers = 1,
124 .setup = iop3xx_pci_setup,
125 .preinit = iop3xx_pci_preinit,
126 .scan = iop3xx_pci_scan_bus,
127 .map_irq = ep80219_pci_map_irq,
128};
129
130static inline int __init
131iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
132{
133 int irq;
134
135 if (slot == 0) {
136 /* CFlash */
137 irq = IRQ_IOP32X_XINT1;
138 } else if (slot == 1) {
139 /* SATA */
140 irq = IRQ_IOP32X_XINT2;
141 } else if (slot == 2) {
142 /* PCI-X Slot */
143 irq = IRQ_IOP32X_XINT3;
144 } else if (slot == 3) {
145 /* 82546 GigE */
146 irq = IRQ_IOP32X_XINT0;
147 } else {
148 printk(KERN_ERR "iq31244_pci_map_irq called for unknown "
149 "device PCI:%d:%d:%d\n", dev->bus->number,
150 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
151 irq = -1;
152 }
153
154 return irq;
155}
156
157static struct hw_pci iq31244_pci __initdata = {
158 .swizzle = pci_std_swizzle,
159 .nr_controllers = 1,
160 .setup = iop3xx_pci_setup,
161 .preinit = iop3xx_pci_preinit,
162 .scan = iop3xx_pci_scan_bus,
163 .map_irq = iq31244_pci_map_irq,
164};
165
166static int __init iq31244_pci_init(void)
167{
168 if (machine_is_iq31244()) {
169 if (is_80219()) {
170 pci_common_init(&ep80219_pci);
171 } else {
172 pci_common_init(&iq31244_pci);
173 }
174 }
175
176 return 0;
177}
178
179subsys_initcall(iq31244_pci_init);
180
181
182/*
183 * IQ31244 machine initialisation.
184 */
185static struct physmap_flash_data iq31244_flash_data = {
186 .width = 2,
187};
188
189static struct resource iq31244_flash_resource = {
190 .start = 0xf0000000,
191 .end = 0xf07fffff,
192 .flags = IORESOURCE_MEM,
193};
194
195static struct platform_device iq31244_flash_device = {
196 .name = "physmap-flash",
197 .id = 0,
198 .dev = {
199 .platform_data = &iq31244_flash_data,
200 },
201 .num_resources = 1,
202 .resource = &iq31244_flash_resource,
203};
204
205static struct plat_serial8250_port iq31244_serial_port[] = {
206 {
207 .mapbase = IQ31244_UART,
208 .membase = (char *)IQ31244_UART,
209 .irq = IRQ_IOP32X_XINT1,
210 .flags = UPF_SKIP_TEST,
211 .iotype = UPIO_MEM,
212 .regshift = 0,
213 .uartclk = 1843200,
214 },
215 { },
216};
217
218static struct resource iq31244_uart_resource = {
219 .start = IQ31244_UART,
220 .end = IQ31244_UART + 7,
221 .flags = IORESOURCE_MEM,
222};
223
224static struct platform_device iq31244_serial_device = {
225 .name = "serial8250",
226 .id = PLAT8250_DEV_PLATFORM,
227 .dev = {
228 .platform_data = iq31244_serial_port,
229 },
230 .num_resources = 1,
231 .resource = &iq31244_uart_resource,
232};
233
234/*
235 * This function will send a SHUTDOWN_COMPLETE message to the PIC
236 * controller over I2C. We are not using the i2c subsystem since
237 * we are going to power off and it may be removed
238 */
239void ep80219_power_off(void)
240{
241 /*
242 * Send the Address byte w/ the start condition
243 */
244 *IOP3XX_IDBR1 = 0x60;
245 *IOP3XX_ICR1 = 0xE9;
246 mdelay(1);
247
248 /*
249 * Send the START_MSG byte w/ no start or stop condition
250 */
251 *IOP3XX_IDBR1 = 0x0F;
252 *IOP3XX_ICR1 = 0xE8;
253 mdelay(1);
254
255 /*
256 * Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or
257 * stop condition
258 */
259 *IOP3XX_IDBR1 = 0x03;
260 *IOP3XX_ICR1 = 0xE8;
261 mdelay(1);
262
263 /*
264 * Send an ignored byte w/ stop condition
265 */
266 *IOP3XX_IDBR1 = 0x00;
267 *IOP3XX_ICR1 = 0xEA;
268
269 while (1)
270 ;
271}
272
273static void __init iq31244_init_machine(void)
274{
275 platform_device_register(&iop3xx_i2c0_device);
276 platform_device_register(&iop3xx_i2c1_device);
277 platform_device_register(&iq31244_flash_device);
278 platform_device_register(&iq31244_serial_device);
279
280 if (is_80219())
281 pm_power_off = ep80219_power_off;
282}
283
284MACHINE_START(IQ31244, "Intel IQ31244")
285 /* Maintainer: Intel Corp. */
286 .phys_io = IQ31244_UART,
287 .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
288 .boot_params = 0xa0000100,
289 .map_io = iq31244_map_io,
290 .init_irq = iop32x_init_irq,
291 .timer = &iq31244_timer,
292 .init_machine = iq31244_init_machine,
293MACHINE_END
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
new file mode 100644
index 000000000000..1f37b5501888
--- /dev/null
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -0,0 +1,193 @@
1/*
2 * arch/arm/mach-iop32x/iq80321.c
3 *
4 * Board support code for the Intel IQ80321 platform.
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/mm.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/pci.h>
20#include <linux/string.h>
21#include <linux/slab.h>
22#include <linux/serial_core.h>
23#include <linux/serial_8250.h>
24#include <linux/mtd/physmap.h>
25#include <linux/platform_device.h>
26#include <asm/hardware.h>
27#include <asm/io.h>
28#include <asm/irq.h>
29#include <asm/mach/arch.h>
30#include <asm/mach/map.h>
31#include <asm/mach/pci.h>
32#include <asm/mach/time.h>
33#include <asm/mach-types.h>
34#include <asm/page.h>
35#include <asm/pgtable.h>
36
37/*
38 * IQ80321 timer tick configuration.
39 */
40static void __init iq80321_timer_init(void)
41{
42 /* 33.333 MHz crystal. */
43 iop3xx_init_time(200000000);
44}
45
46static struct sys_timer iq80321_timer = {
47 .init = iq80321_timer_init,
48 .offset = iop3xx_gettimeoffset,
49};
50
51
52/*
53 * IQ80321 I/O.
54 */
55static struct map_desc iq80321_io_desc[] __initdata = {
56 { /* on-board devices */
57 .virtual = IQ80321_UART,
58 .pfn = __phys_to_pfn(IQ80321_UART),
59 .length = 0x00100000,
60 .type = MT_DEVICE,
61 },
62};
63
64void __init iq80321_map_io(void)
65{
66 iop3xx_map_io();
67 iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc));
68}
69
70
71/*
72 * IQ80321 PCI.
73 */
74static inline int __init
75iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
76{
77 int irq;
78
79 if ((slot == 2 || slot == 6) && pin == 1) {
80 /* PCI-X Slot INTA */
81 irq = IRQ_IOP32X_XINT2;
82 } else if ((slot == 2 || slot == 6) && pin == 2) {
83 /* PCI-X Slot INTA */
84 irq = IRQ_IOP32X_XINT3;
85 } else if ((slot == 2 || slot == 6) && pin == 3) {
86 /* PCI-X Slot INTA */
87 irq = IRQ_IOP32X_XINT0;
88 } else if ((slot == 2 || slot == 6) && pin == 4) {
89 /* PCI-X Slot INTA */
90 irq = IRQ_IOP32X_XINT1;
91 } else if (slot == 4 || slot == 8) {
92 /* Gig-E */
93 irq = IRQ_IOP32X_XINT0;
94 } else {
95 printk(KERN_ERR "iq80321_pci_map_irq() called for unknown "
96 "device PCI:%d:%d:%d\n", dev->bus->number,
97 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
98 irq = -1;
99 }
100
101 return irq;
102}
103
104static struct hw_pci iq80321_pci __initdata = {
105 .swizzle = pci_std_swizzle,
106 .nr_controllers = 1,
107 .setup = iop3xx_pci_setup,
108 .preinit = iop3xx_pci_preinit,
109 .scan = iop3xx_pci_scan_bus,
110 .map_irq = iq80321_pci_map_irq,
111};
112
113static int __init iq80321_pci_init(void)
114{
115 if (machine_is_iq80321())
116 pci_common_init(&iq80321_pci);
117
118 return 0;
119}
120
121subsys_initcall(iq80321_pci_init);
122
123
124/*
125 * IQ80321 machine initialisation.
126 */
127static struct physmap_flash_data iq80321_flash_data = {
128 .width = 1,
129};
130
131static struct resource iq80321_flash_resource = {
132 .start = 0xf0000000,
133 .end = 0xf07fffff,
134 .flags = IORESOURCE_MEM,
135};
136
137static struct platform_device iq80321_flash_device = {
138 .name = "physmap-flash",
139 .id = 0,
140 .dev = {
141 .platform_data = &iq80321_flash_data,
142 },
143 .num_resources = 1,
144 .resource = &iq80321_flash_resource,
145};
146
147static struct plat_serial8250_port iq80321_serial_port[] = {
148 {
149 .mapbase = IQ80321_UART,
150 .membase = (char *)IQ80321_UART,
151 .irq = IRQ_IOP32X_XINT1,
152 .flags = UPF_SKIP_TEST,
153 .iotype = UPIO_MEM,
154 .regshift = 0,
155 .uartclk = 1843200,
156 },
157 { },
158};
159
160static struct resource iq80321_uart_resource = {
161 .start = IQ80321_UART,
162 .end = IQ80321_UART + 7,
163 .flags = IORESOURCE_MEM,
164};
165
166static struct platform_device iq80321_serial_device = {
167 .name = "serial8250",
168 .id = PLAT8250_DEV_PLATFORM,
169 .dev = {
170 .platform_data = iq80321_serial_port,
171 },
172 .num_resources = 1,
173 .resource = &iq80321_uart_resource,
174};
175
176static void __init iq80321_init_machine(void)
177{
178 platform_device_register(&iop3xx_i2c0_device);
179 platform_device_register(&iop3xx_i2c1_device);
180 platform_device_register(&iq80321_flash_device);
181 platform_device_register(&iq80321_serial_device);
182}
183
184MACHINE_START(IQ80321, "Intel IQ80321")
185 /* Maintainer: Intel Corp. */
186 .phys_io = IQ80321_UART,
187 .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc,
188 .boot_params = 0xa0000100,
189 .map_io = iq80321_map_io,
190 .init_irq = iop32x_init_irq,
191 .timer = &iq80321_timer,
192 .init_machine = iq80321_init_machine,
193MACHINE_END
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
new file mode 100644
index 000000000000..69d6302f40cf
--- /dev/null
+++ b/arch/arm/mach-iop32x/irq.c
@@ -0,0 +1,76 @@
1/*
2 * arch/arm/mach-iop32x/irq.c
3 *
4 * Generic IOP32X IRQ handling functionality
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <asm/mach/irq.h>
18#include <asm/irq.h>
19#include <asm/hardware.h>
20#include <asm/mach-types.h>
21
22static u32 iop32x_mask;
23
24static inline void intctl_write(u32 val)
25{
26 iop3xx_cp6_enable();
27 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
28 iop3xx_cp6_disable();
29}
30
31static inline void intstr_write(u32 val)
32{
33 iop3xx_cp6_enable();
34 asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
35 iop3xx_cp6_disable();
36}
37
38static void
39iop32x_irq_mask(unsigned int irq)
40{
41 iop32x_mask &= ~(1 << irq);
42 intctl_write(iop32x_mask);
43}
44
45static void
46iop32x_irq_unmask(unsigned int irq)
47{
48 iop32x_mask |= 1 << irq;
49 intctl_write(iop32x_mask);
50}
51
52struct irq_chip ext_chip = {
53 .name = "IOP32x",
54 .ack = iop32x_irq_mask,
55 .mask = iop32x_irq_mask,
56 .unmask = iop32x_irq_unmask,
57};
58
59void __init iop32x_init_irq(void)
60{
61 int i;
62
63 intctl_write(0);
64 intstr_write(0);
65 if (machine_is_glantank() ||
66 machine_is_iq80321() ||
67 machine_is_iq31244() ||
68 machine_is_n2100())
69 *IOP3XX_PCIIRSR = 0x0f;
70
71 for (i = 0; i < NR_IRQS; i++) {
72 set_irq_chip(i, &ext_chip);
73 set_irq_handler(i, do_level_IRQ);
74 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
75 }
76}
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
new file mode 100644
index 000000000000..a2c94a47b2b2
--- /dev/null
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -0,0 +1,251 @@
1/*
2 * arch/arm/mach-iop32x/n2100.c
3 *
4 * Board support code for the Thecus N2100 platform.
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright 2003 (c) MontaVista, Software, Inc.
9 * Copyright (C) 2004 Intel Corp.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/pm.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/serial_core.h>
26#include <linux/serial_8250.h>
27#include <linux/mtd/physmap.h>
28#include <linux/platform_device.h>
29#include <linux/reboot.h>
30#include <asm/hardware.h>
31#include <asm/io.h>
32#include <asm/irq.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/pci.h>
36#include <asm/mach/time.h>
37#include <asm/mach-types.h>
38#include <asm/page.h>
39#include <asm/pgtable.h>
40
41/*
42 * N2100 timer tick configuration.
43 */
44static void __init n2100_timer_init(void)
45{
46 /* 33.000 MHz crystal. */
47 iop3xx_init_time(198000000);
48}
49
50static struct sys_timer n2100_timer = {
51 .init = n2100_timer_init,
52 .offset = iop3xx_gettimeoffset,
53};
54
55
56/*
57 * N2100 I/O.
58 */
59static struct map_desc n2100_io_desc[] __initdata = {
60 { /* on-board devices */
61 .virtual = N2100_UART,
62 .pfn = __phys_to_pfn(N2100_UART),
63 .length = 0x00100000,
64 .type = MT_DEVICE
65 },
66};
67
68void __init n2100_map_io(void)
69{
70 iop3xx_map_io();
71 iotable_init(n2100_io_desc, ARRAY_SIZE(n2100_io_desc));
72}
73
74
75/*
76 * N2100 PCI.
77 */
78static inline int __init
79n2100_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
80{
81 int irq;
82
83 if (PCI_SLOT(dev->devfn) == 1) {
84 /* RTL8110SB #1 */
85 irq = IRQ_IOP32X_XINT0;
86 } else if (PCI_SLOT(dev->devfn) == 2) {
87 /* RTL8110SB #2 */
88 irq = IRQ_IOP32X_XINT1;
89 } else if (PCI_SLOT(dev->devfn) == 3) {
90 /* Sil3512 */
91 irq = IRQ_IOP32X_XINT2;
92 } else if (PCI_SLOT(dev->devfn) == 4 && pin == 1) {
93 /* VT6212 INTA */
94 irq = IRQ_IOP32X_XINT1;
95 } else if (PCI_SLOT(dev->devfn) == 4 && pin == 2) {
96 /* VT6212 INTB */
97 irq = IRQ_IOP32X_XINT0;
98 } else if (PCI_SLOT(dev->devfn) == 4 && pin == 3) {
99 /* VT6212 INTC */
100 irq = IRQ_IOP32X_XINT2;
101 } else if (PCI_SLOT(dev->devfn) == 5) {
102 /* Mini-PCI slot */
103 irq = IRQ_IOP32X_XINT3;
104 } else {
105 printk(KERN_ERR "n2100_pci_map_irq() called for unknown "
106 "device PCI:%d:%d:%d\n", dev->bus->number,
107 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
108 irq = -1;
109 }
110
111 return irq;
112}
113
114static struct hw_pci n2100_pci __initdata = {
115 .swizzle = pci_std_swizzle,
116 .nr_controllers = 1,
117 .setup = iop3xx_pci_setup,
118 .preinit = iop3xx_pci_preinit,
119 .scan = iop3xx_pci_scan_bus,
120 .map_irq = n2100_pci_map_irq,
121};
122
123static int __init n2100_pci_init(void)
124{
125 if (machine_is_n2100())
126 pci_common_init(&n2100_pci);
127
128 return 0;
129}
130
131subsys_initcall(n2100_pci_init);
132
133
134/*
135 * N2100 machine initialisation.
136 */
137static struct physmap_flash_data n2100_flash_data = {
138 .width = 2,
139};
140
141static struct resource n2100_flash_resource = {
142 .start = 0xf0000000,
143 .end = 0xf0ffffff,
144 .flags = IORESOURCE_MEM,
145};
146
147static struct platform_device n2100_flash_device = {
148 .name = "physmap-flash",
149 .id = 0,
150 .dev = {
151 .platform_data = &n2100_flash_data,
152 },
153 .num_resources = 1,
154 .resource = &n2100_flash_resource,
155};
156
157
158static struct plat_serial8250_port n2100_serial_port[] = {
159 {
160 .mapbase = N2100_UART,
161 .membase = (char *)N2100_UART,
162 .irq = 0,
163 .flags = UPF_SKIP_TEST,
164 .iotype = UPIO_MEM,
165 .regshift = 0,
166 .uartclk = 1843200,
167 },
168 { },
169};
170
171static struct resource n2100_uart_resource = {
172 .start = N2100_UART,
173 .end = N2100_UART + 7,
174 .flags = IORESOURCE_MEM,
175};
176
177static struct platform_device n2100_serial_device = {
178 .name = "serial8250",
179 .id = PLAT8250_DEV_PLATFORM,
180 .dev = {
181 .platform_data = n2100_serial_port,
182 },
183 .num_resources = 1,
184 .resource = &n2100_uart_resource,
185};
186
187
188/*
189 * Pull PCA9532 GPIO #8 low to power off the machine.
190 */
191static void n2100_power_off(void)
192{
193 local_irq_disable();
194
195 /* Start condition, I2C address of PCA9532, write transaction. */
196 *IOP3XX_IDBR0 = 0xc0;
197 *IOP3XX_ICR0 = 0xe9;
198 mdelay(1);
199
200 /* Write address 0x08. */
201 *IOP3XX_IDBR0 = 0x08;
202 *IOP3XX_ICR0 = 0xe8;
203 mdelay(1);
204
205 /* Write data 0x01, stop condition. */
206 *IOP3XX_IDBR0 = 0x01;
207 *IOP3XX_ICR0 = 0xea;
208
209 while (1)
210 ;
211}
212
213
214static struct timer_list power_button_poll_timer;
215
216static void power_button_poll(unsigned long dummy)
217{
218 if (gpio_line_get(N2100_POWER_BUTTON) == 0) {
219 ctrl_alt_del();
220 return;
221 }
222
223 power_button_poll_timer.expires = jiffies + (HZ / 10);
224 add_timer(&power_button_poll_timer);
225}
226
227
228static void __init n2100_init_machine(void)
229{
230 platform_device_register(&iop3xx_i2c0_device);
231 platform_device_register(&n2100_flash_device);
232 platform_device_register(&n2100_serial_device);
233
234 pm_power_off = n2100_power_off;
235
236 init_timer(&power_button_poll_timer);
237 power_button_poll_timer.function = power_button_poll;
238 power_button_poll_timer.expires = jiffies + (HZ / 10);
239 add_timer(&power_button_poll_timer);
240}
241
242MACHINE_START(N2100, "Thecus N2100")
243 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
244 .phys_io = N2100_UART,
245 .io_pg_offst = ((N2100_UART) >> 18) & 0xfffc,
246 .boot_params = 0xa0000100,
247 .map_io = n2100_map_io,
248 .init_irq = iop32x_init_irq,
249 .timer = &n2100_timer,
250 .init_machine = n2100_init_machine,
251MACHINE_END
diff --git a/arch/arm/mach-iop33x/Kconfig b/arch/arm/mach-iop33x/Kconfig
new file mode 100644
index 000000000000..9aa016bb18f9
--- /dev/null
+++ b/arch/arm/mach-iop33x/Kconfig
@@ -0,0 +1,21 @@
1if ARCH_IOP33X
2
3menu "IOP33x Implementation Options"
4
5comment "IOP33x Platform Types"
6
7config ARCH_IQ80331
8 bool "Enable support for IQ80331"
9 help
10 Say Y here if you want to run your kernel on the Intel IQ80331
11 evaluation kit for the IOP331 chipset.
12
13config MACH_IQ80332
14 bool "Enable support for IQ80332"
15 help
16 Say Y here if you want to run your kernel on the Intel IQ80332
17 evaluation kit for the IOP332 chipset.
18
19endmenu
20
21endif
diff --git a/arch/arm/mach-iop33x/Makefile b/arch/arm/mach-iop33x/Makefile
new file mode 100644
index 000000000000..90081d8c9d16
--- /dev/null
+++ b/arch/arm/mach-iop33x/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for the linux kernel.
3#
4
5obj-y := irq.o uart.o
6obj-m :=
7obj-n :=
8obj- :=
9
10obj-$(CONFIG_ARCH_IQ80331) += iq80331.o
11obj-$(CONFIG_MACH_IQ80332) += iq80332.o
diff --git a/arch/arm/mach-iop33x/Makefile.boot b/arch/arm/mach-iop33x/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-iop33x/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
new file mode 100644
index 000000000000..97a7b7488264
--- /dev/null
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -0,0 +1,148 @@
1/*
2 * arch/arm/mach-iop33x/iq80331.c
3 *
4 * Board support code for the Intel IQ80331 platform.
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2003 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/mm.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/string.h>
20#include <linux/slab.h>
21#include <linux/serial_core.h>
22#include <linux/serial_8250.h>
23#include <linux/mtd/physmap.h>
24#include <linux/platform_device.h>
25#include <asm/hardware.h>
26#include <asm/io.h>
27#include <asm/irq.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/pci.h>
31#include <asm/mach/time.h>
32#include <asm/mach-types.h>
33#include <asm/page.h>
34#include <asm/pgtable.h>
35
36/*
37 * IQ80331 timer tick configuration.
38 */
39static void __init iq80331_timer_init(void)
40{
41 /* D-Step parts run at a higher internal bus frequency */
42 if (*IOP3XX_ATURID >= 0xa)
43 iop3xx_init_time(333000000);
44 else
45 iop3xx_init_time(266000000);
46}
47
48static struct sys_timer iq80331_timer = {
49 .init = iq80331_timer_init,
50 .offset = iop3xx_gettimeoffset,
51};
52
53
54/*
55 * IQ80331 PCI.
56 */
57static inline int __init
58iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
59{
60 int irq;
61
62 if (slot == 1 && pin == 1) {
63 /* PCI-X Slot INTA */
64 irq = IRQ_IOP33X_XINT1;
65 } else if (slot == 1 && pin == 2) {
66 /* PCI-X Slot INTB */
67 irq = IRQ_IOP33X_XINT2;
68 } else if (slot == 1 && pin == 3) {
69 /* PCI-X Slot INTC */
70 irq = IRQ_IOP33X_XINT3;
71 } else if (slot == 1 && pin == 4) {
72 /* PCI-X Slot INTD */
73 irq = IRQ_IOP33X_XINT0;
74 } else if (slot == 2) {
75 /* GigE */
76 irq = IRQ_IOP33X_XINT2;
77 } else {
78 printk(KERN_ERR "iq80331_pci_map_irq() called for unknown "
79 "device PCI:%d:%d:%d\n", dev->bus->number,
80 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
81 irq = -1;
82 }
83
84 return irq;
85}
86
87static struct hw_pci iq80331_pci __initdata = {
88 .swizzle = pci_std_swizzle,
89 .nr_controllers = 1,
90 .setup = iop3xx_pci_setup,
91 .preinit = iop3xx_pci_preinit,
92 .scan = iop3xx_pci_scan_bus,
93 .map_irq = iq80331_pci_map_irq,
94};
95
96static int __init iq80331_pci_init(void)
97{
98 if (machine_is_iq80331())
99 pci_common_init(&iq80331_pci);
100
101 return 0;
102}
103
104subsys_initcall(iq80331_pci_init);
105
106
107/*
108 * IQ80331 machine initialisation.
109 */
110static struct physmap_flash_data iq80331_flash_data = {
111 .width = 1,
112};
113
114static struct resource iq80331_flash_resource = {
115 .start = 0xc0000000,
116 .end = 0xc07fffff,
117 .flags = IORESOURCE_MEM,
118};
119
120static struct platform_device iq80331_flash_device = {
121 .name = "physmap-flash",
122 .id = 0,
123 .dev = {
124 .platform_data = &iq80331_flash_data,
125 },
126 .num_resources = 1,
127 .resource = &iq80331_flash_resource,
128};
129
130static void __init iq80331_init_machine(void)
131{
132 platform_device_register(&iop3xx_i2c0_device);
133 platform_device_register(&iop3xx_i2c1_device);
134 platform_device_register(&iop33x_uart0_device);
135 platform_device_register(&iop33x_uart1_device);
136 platform_device_register(&iq80331_flash_device);
137}
138
139MACHINE_START(IQ80331, "Intel IQ80331")
140 /* Maintainer: Intel Corp. */
141 .phys_io = 0xfefff000,
142 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc,
143 .boot_params = 0x00000100,
144 .map_io = iop3xx_map_io,
145 .init_irq = iop33x_init_irq,
146 .timer = &iq80331_timer,
147 .init_machine = iq80331_init_machine,
148MACHINE_END
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
new file mode 100644
index 000000000000..9887bfc1c078
--- /dev/null
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -0,0 +1,148 @@
1/*
2 * arch/arm/mach-iop33x/iq80332.c
3 *
4 * Board support code for the Intel IQ80332 platform.
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/mm.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/string.h>
20#include <linux/slab.h>
21#include <linux/serial_core.h>
22#include <linux/serial_8250.h>
23#include <linux/mtd/physmap.h>
24#include <linux/platform_device.h>
25#include <asm/hardware.h>
26#include <asm/io.h>
27#include <asm/irq.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/pci.h>
31#include <asm/mach/time.h>
32#include <asm/mach-types.h>
33#include <asm/page.h>
34#include <asm/pgtable.h>
35
36/*
37 * IQ80332 timer tick configuration.
38 */
39static void __init iq80332_timer_init(void)
40{
41 /* D-Step parts and the iop333 run at a higher internal bus frequency */
42 if (*IOP3XX_ATURID >= 0xa || *IOP3XX_ATUDID == 0x374)
43 iop3xx_init_time(333000000);
44 else
45 iop3xx_init_time(266000000);
46}
47
48static struct sys_timer iq80332_timer = {
49 .init = iq80332_timer_init,
50 .offset = iop3xx_gettimeoffset,
51};
52
53
54/*
55 * IQ80332 PCI.
56 */
57static inline int __init
58iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
59{
60 int irq;
61
62 if (slot == 4 && pin == 1) {
63 /* PCI-X Slot INTA */
64 irq = IRQ_IOP33X_XINT0;
65 } else if (slot == 4 && pin == 2) {
66 /* PCI-X Slot INTB */
67 irq = IRQ_IOP33X_XINT1;
68 } else if (slot == 4 && pin == 3) {
69 /* PCI-X Slot INTC */
70 irq = IRQ_IOP33X_XINT2;
71 } else if (slot == 4 && pin == 4) {
72 /* PCI-X Slot INTD */
73 irq = IRQ_IOP33X_XINT3;
74 } else if (slot == 6) {
75 /* GigE */
76 irq = IRQ_IOP33X_XINT2;
77 } else {
78 printk(KERN_ERR "iq80332_pci_map_irq() called for unknown "
79 "device PCI:%d:%d:%d\n", dev->bus->number,
80 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
81 irq = -1;
82 }
83
84 return irq;
85}
86
87static struct hw_pci iq80332_pci __initdata = {
88 .swizzle = pci_std_swizzle,
89 .nr_controllers = 1,
90 .setup = iop3xx_pci_setup,
91 .preinit = iop3xx_pci_preinit,
92 .scan = iop3xx_pci_scan_bus,
93 .map_irq = iq80332_pci_map_irq,
94};
95
96static int __init iq80332_pci_init(void)
97{
98 if (machine_is_iq80332())
99 pci_common_init(&iq80332_pci);
100
101 return 0;
102}
103
104subsys_initcall(iq80332_pci_init);
105
106
107/*
108 * IQ80332 machine initialisation.
109 */
110static struct physmap_flash_data iq80332_flash_data = {
111 .width = 1,
112};
113
114static struct resource iq80332_flash_resource = {
115 .start = 0xc0000000,
116 .end = 0xc07fffff,
117 .flags = IORESOURCE_MEM,
118};
119
120static struct platform_device iq80332_flash_device = {
121 .name = "physmap-flash",
122 .id = 0,
123 .dev = {
124 .platform_data = &iq80332_flash_data,
125 },
126 .num_resources = 1,
127 .resource = &iq80332_flash_resource,
128};
129
130static void __init iq80332_init_machine(void)
131{
132 platform_device_register(&iop3xx_i2c0_device);
133 platform_device_register(&iop3xx_i2c1_device);
134 platform_device_register(&iop33x_uart0_device);
135 platform_device_register(&iop33x_uart1_device);
136 platform_device_register(&iq80332_flash_device);
137}
138
139MACHINE_START(IQ80332, "Intel IQ80332")
140 /* Maintainer: Intel Corp. */
141 .phys_io = 0xfefff000,
142 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc,
143 .boot_params = 0x00000100,
144 .map_io = iop3xx_map_io,
145 .init_irq = iop33x_init_irq,
146 .timer = &iq80332_timer,
147 .init_machine = iq80332_init_machine,
148MACHINE_END
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
new file mode 100644
index 000000000000..63304b3d0d76
--- /dev/null
+++ b/arch/arm/mach-iop33x/irq.c
@@ -0,0 +1,127 @@
1/*
2 * arch/arm/mach-iop33x/irq.c
3 *
4 * Generic IOP331 IRQ handling functionality
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2003 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <asm/mach/irq.h>
18#include <asm/irq.h>
19#include <asm/hardware.h>
20#include <asm/mach-types.h>
21
22static u32 iop33x_mask0;
23static u32 iop33x_mask1;
24
25static inline void intctl0_write(u32 val)
26{
27 iop3xx_cp6_enable();
28 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
29 iop3xx_cp6_disable();
30}
31
32static inline void intctl1_write(u32 val)
33{
34 iop3xx_cp6_enable();
35 asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
36 iop3xx_cp6_disable();
37}
38
39static inline void intstr0_write(u32 val)
40{
41 iop3xx_cp6_enable();
42 asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
43 iop3xx_cp6_disable();
44}
45
46static inline void intstr1_write(u32 val)
47{
48 iop3xx_cp6_enable();
49 asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
50 iop3xx_cp6_disable();
51}
52
53static inline void intbase_write(u32 val)
54{
55 iop3xx_cp6_enable();
56 asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
57 iop3xx_cp6_disable();
58}
59
60static inline void intsize_write(u32 val)
61{
62 iop3xx_cp6_enable();
63 asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
64 iop3xx_cp6_disable();
65}
66
67static void
68iop33x_irq_mask1 (unsigned int irq)
69{
70 iop33x_mask0 &= ~(1 << irq);
71 intctl0_write(iop33x_mask0);
72}
73
74static void
75iop33x_irq_mask2 (unsigned int irq)
76{
77 iop33x_mask1 &= ~(1 << (irq - 32));
78 intctl1_write(iop33x_mask1);
79}
80
81static void
82iop33x_irq_unmask1(unsigned int irq)
83{
84 iop33x_mask0 |= 1 << irq;
85 intctl0_write(iop33x_mask0);
86}
87
88static void
89iop33x_irq_unmask2(unsigned int irq)
90{
91 iop33x_mask1 |= (1 << (irq - 32));
92 intctl1_write(iop33x_mask1);
93}
94
95struct irq_chip iop33x_irqchip1 = {
96 .name = "IOP33x-1",
97 .ack = iop33x_irq_mask1,
98 .mask = iop33x_irq_mask1,
99 .unmask = iop33x_irq_unmask1,
100};
101
102struct irq_chip iop33x_irqchip2 = {
103 .name = "IOP33x-2",
104 .ack = iop33x_irq_mask2,
105 .mask = iop33x_irq_mask2,
106 .unmask = iop33x_irq_unmask2,
107};
108
109void __init iop33x_init_irq(void)
110{
111 int i;
112
113 intctl0_write(0);
114 intctl1_write(0);
115 intstr0_write(0);
116 intstr1_write(0);
117 intbase_write(0);
118 intsize_write(1);
119 if (machine_is_iq80331())
120 *IOP3XX_PCIIRSR = 0x0f;
121
122 for (i = 0; i < NR_IRQS; i++) {
123 set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
124 set_irq_handler(i, do_level_IRQ);
125 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
126 }
127}
diff --git a/arch/arm/mach-iop33x/uart.c b/arch/arm/mach-iop33x/uart.c
new file mode 100644
index 000000000000..ac297cd0276c
--- /dev/null
+++ b/arch/arm/mach-iop33x/uart.c
@@ -0,0 +1,105 @@
1/*
2 * arch/arm/mach-iop33x/uart.c
3 *
4 * Author: Dave Jiang (dave.jiang@intel.com)
5 * Copyright (C) 2004 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/mm.h>
13#include <linux/init.h>
14#include <linux/major.h>
15#include <linux/fs.h>
16#include <linux/platform_device.h>
17#include <linux/serial.h>
18#include <linux/tty.h>
19#include <linux/serial_8250.h>
20#include <asm/io.h>
21#include <asm/pgtable.h>
22#include <asm/page.h>
23#include <asm/mach/map.h>
24#include <asm/setup.h>
25#include <asm/system.h>
26#include <asm/memory.h>
27#include <asm/hardware.h>
28#include <asm/hardware/iop3xx.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32#define IOP33X_UART_XTAL 33334000
33
34static struct plat_serial8250_port iop33x_uart0_data[] = {
35 {
36 .membase = (char *)IOP33X_UART0_VIRT,
37 .mapbase = IOP33X_UART0_PHYS,
38 .irq = IRQ_IOP33X_UART0,
39 .uartclk = IOP33X_UART_XTAL,
40 .regshift = 2,
41 .iotype = UPIO_MEM,
42 .flags = UPF_SKIP_TEST,
43 },
44 { },
45};
46
47static struct resource iop33x_uart0_resources[] = {
48 [0] = {
49 .start = IOP33X_UART0_PHYS,
50 .end = IOP33X_UART0_PHYS + 0x3f,
51 .flags = IORESOURCE_MEM,
52 },
53 [1] = {
54 .start = IRQ_IOP33X_UART0,
55 .end = IRQ_IOP33X_UART0,
56 .flags = IORESOURCE_IRQ,
57 },
58};
59
60struct platform_device iop33x_uart0_device = {
61 .name = "serial8250",
62 .id = PLAT8250_DEV_PLATFORM,
63 .dev = {
64 .platform_data = iop33x_uart0_data,
65 },
66 .num_resources = 2,
67 .resource = iop33x_uart0_resources,
68};
69
70
71static struct resource iop33x_uart1_resources[] = {
72 [0] = {
73 .start = IOP33X_UART1_PHYS,
74 .end = IOP33X_UART1_PHYS + 0x3f,
75 .flags = IORESOURCE_MEM,
76 },
77 [1] = {
78 .start = IRQ_IOP33X_UART1,
79 .end = IRQ_IOP33X_UART1,
80 .flags = IORESOURCE_IRQ,
81 },
82};
83
84static struct plat_serial8250_port iop33x_uart1_data[] = {
85 {
86 .membase = (char *)IOP33X_UART1_VIRT,
87 .mapbase = IOP33X_UART1_PHYS,
88 .irq = IRQ_IOP33X_UART1,
89 .uartclk = IOP33X_UART_XTAL,
90 .regshift = 2,
91 .iotype = UPIO_MEM,
92 .flags = UPF_SKIP_TEST,
93 },
94 { },
95};
96
97struct platform_device iop33x_uart1_device = {
98 .name = "serial8250",
99 .id = PLAT8250_DEV_PLATFORM1,
100 .dev = {
101 .platform_data = iop33x_uart1_data,
102 },
103 .num_resources = 2,
104 .resource = iop33x_uart1_resources,
105};
diff --git a/arch/arm/mach-iop3xx/Kconfig b/arch/arm/mach-iop3xx/Kconfig
deleted file mode 100644
index 4422f2388607..000000000000
--- a/arch/arm/mach-iop3xx/Kconfig
+++ /dev/null
@@ -1,66 +0,0 @@
1if ARCH_IOP3XX
2
3menu "IOP3xx Implementation Options"
4
5comment "IOP3xx Platform Types"
6
7config ARCH_IQ80321
8 bool "Enable support for IQ80321"
9 select ARCH_IOP321
10 help
11 Say Y here if you want to run your kernel on the Intel IQ80321
12 evaluation kit for the IOP321 chipset.
13
14config ARCH_IQ31244
15 bool "Enable support for IQ31244"
16 select ARCH_IOP321
17 help
18 Say Y here if you want to run your kernel on the Intel IQ31244
19 evaluation kit for the IOP321 chipset.
20
21config ARCH_IQ80331
22 bool "Enable support for IQ80331"
23 select ARCH_IOP331
24 help
25 Say Y here if you want to run your kernel on the Intel IQ80331
26 evaluation kit for the IOP331 chipset.
27
28config MACH_IQ80332
29 bool "Enable support for IQ80332"
30 select ARCH_IOP331
31 help
32 Say Y here if you want to run your kernel on the Intel IQ80332
33 evaluation kit for the IOP332 chipset.
34
35config ARCH_EP80219
36 bool "Enable support for EP80219"
37 select ARCH_IOP321
38 select ARCH_IQ31244
39 help
40 Say Y here if you want to run your kernel on the Intel EP80219
41 evaluation kit for the Intel 80219 chipset (a IOP321 variant).
42
43# Which IOP variant are we running?
44config ARCH_IOP321
45 bool
46 help
47 The IQ80321 uses the IOP321 variant.
48 The IQ31244 and EP80219 uses the IOP321 variant.
49
50config ARCH_IOP331
51 bool
52 default ARCH_IQ80331
53 help
54 The IQ80331, IQ80332, and IQ80333 uses the IOP331 variant.
55
56comment "IOP3xx Chipset Features"
57
58config IOP331_STEPD
59 bool "Chip stepping D of the IOP80331 processor or IOP80333"
60 depends on (ARCH_IOP331)
61 help
62 Say Y here if you have StepD of the IOP80331 or IOP8033
63 based platforms.
64
65endmenu
66endif
diff --git a/arch/arm/mach-iop3xx/Makefile b/arch/arm/mach-iop3xx/Makefile
deleted file mode 100644
index b17eb1f46102..000000000000
--- a/arch/arm/mach-iop3xx/Makefile
+++ /dev/null
@@ -1,23 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7obj-y := common.o
8
9obj-m :=
10obj-n :=
11obj- :=
12
13obj-$(CONFIG_ARCH_IOP321) += iop321-setup.o iop321-irq.o iop321-pci.o iop321-time.o
14
15obj-$(CONFIG_ARCH_IOP331) += iop331-setup.o iop331-irq.o iop331-pci.o iop331-time.o
16
17obj-$(CONFIG_ARCH_IQ80321) += iq80321-mm.o iq80321-pci.o
18
19obj-$(CONFIG_ARCH_IQ31244) += iq31244-mm.o iq31244-pci.o
20
21obj-$(CONFIG_ARCH_IQ80331) += iq80331-mm.o iq80331-pci.o
22
23obj-$(CONFIG_MACH_IQ80332) += iq80332-mm.o iq80332-pci.o
diff --git a/arch/arm/mach-iop3xx/Makefile.boot b/arch/arm/mach-iop3xx/Makefile.boot
deleted file mode 100644
index 6387aa20461b..000000000000
--- a/arch/arm/mach-iop3xx/Makefile.boot
+++ /dev/null
@@ -1,9 +0,0 @@
1 zreladdr-y := 0xa0008000
2params_phys-y := 0xa0000100
3initrd_phys-y := 0xa0800000
4ifeq ($(CONFIG_ARCH_IOP331),y)
5 zreladdr-y := 0x00008000
6params_phys-y := 0x00000100
7initrd_phys-y := 0x00800000
8endif
9
diff --git a/arch/arm/mach-iop3xx/common.c b/arch/arm/mach-iop3xx/common.c
deleted file mode 100644
index d7f50e57e753..000000000000
--- a/arch/arm/mach-iop3xx/common.c
+++ /dev/null
@@ -1,72 +0,0 @@
1/*
2 * arch/arm/mach-iop3xx/common.c
3 *
4 * Common routines shared across all IOP3xx implementations
5 *
6 * Author: Deepak Saxena <dsaxena@mvista.com>
7 *
8 * Copyright 2003 (c) MontaVista, Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/delay.h>
16#include <asm/hardware.h>
17
18/*
19 * Shared variables
20 */
21unsigned long iop3xx_pcibios_min_io = 0;
22unsigned long iop3xx_pcibios_min_mem = 0;
23
24#ifdef CONFIG_ARCH_EP80219
25#include <linux/kernel.h>
26/*
27 * Default power-off for EP80219
28 */
29
30static inline void ep80219_send_to_pic(__u8 c) {
31}
32
33void ep80219_power_off(void)
34{
35 /*
36 * This function will send a SHUTDOWN_COMPLETE message to the PIC controller
37 * over I2C. We are not using the i2c subsystem since we are going to power
38 * off and it may be removed
39 */
40
41 /* Send the Address byte w/ the start condition */
42 *IOP321_IDBR1 = 0x60;
43 *IOP321_ICR1 = 0xE9;
44 mdelay(1);
45
46 /* Send the START_MSG byte w/ no start or stop condition */
47 *IOP321_IDBR1 = 0x0F;
48 *IOP321_ICR1 = 0xE8;
49 mdelay(1);
50
51 /* Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or stop condition */
52 *IOP321_IDBR1 = 0x03;
53 *IOP321_ICR1 = 0xE8;
54 mdelay(1);
55
56 /* Send an ignored byte w/ stop condition */
57 *IOP321_IDBR1 = 0x00;
58 *IOP321_ICR1 = 0xEA;
59
60 while (1) ;
61}
62
63#include <linux/init.h>
64#include <linux/pm.h>
65
66static int __init ep80219_init(void)
67{
68 pm_power_off = ep80219_power_off;
69 return 0;
70}
71arch_initcall(ep80219_init);
72#endif
diff --git a/arch/arm/mach-iop3xx/iop321-irq.c b/arch/arm/mach-iop3xx/iop321-irq.c
deleted file mode 100644
index 88ac333472c8..000000000000
--- a/arch/arm/mach-iop3xx/iop321-irq.c
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * linux/arch/arm/mach-iop3xx/iop321-irq.c
3 *
4 * Generic IOP321 IRQ handling functionality
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Added IOP3XX chipset and IQ80321 board masking code.
14 *
15 */
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19
20#include <asm/mach/irq.h>
21#include <asm/irq.h>
22#include <asm/hardware.h>
23
24#include <asm/mach-types.h>
25
26static u32 iop321_mask /* = 0 */;
27
28static inline void intctl_write(u32 val)
29{
30 asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
31}
32
33static inline void intstr_write(u32 val)
34{
35 asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val));
36}
37
38static void
39iop321_irq_mask (unsigned int irq)
40{
41
42 iop321_mask &= ~(1 << (irq - IOP321_IRQ_OFS));
43
44 intctl_write(iop321_mask);
45}
46
47static void
48iop321_irq_unmask (unsigned int irq)
49{
50 iop321_mask |= (1 << (irq - IOP321_IRQ_OFS));
51
52 intctl_write(iop321_mask);
53}
54
55struct irq_chip ext_chip = {
56 .name = "IOP",
57 .ack = iop321_irq_mask,
58 .mask = iop321_irq_mask,
59 .unmask = iop321_irq_unmask,
60};
61
62void __init iop321_init_irq(void)
63{
64 unsigned int i, tmp;
65
66 /* Enable access to coprocessor 6 for dealing with IRQs.
67 * From RMK:
68 * Basically, the Intel documentation here is poor. It appears that
69 * you need to set the bit to be able to access the coprocessor from
70 * SVC mode. Whether that allows access from user space or not is
71 * unclear.
72 */
73 asm volatile (
74 "mrc p15, 0, %0, c15, c1, 0\n\t"
75 "orr %0, %0, %1\n\t"
76 "mcr p15, 0, %0, c15, c1, 0\n\t"
77 /* The action is delayed, so we have to do this: */
78 "mrc p15, 0, %0, c15, c1, 0\n\t"
79 "mov %0, %0\n\t"
80 "sub pc, pc, #4"
81 : "=r" (tmp) : "i" (1 << 6) );
82
83 intctl_write(0); // disable all interrupts
84 intstr_write(0); // treat all as IRQ
85 if(machine_is_iq80321() ||
86 machine_is_iq31244()) // all interrupts are inputs to chip
87 *IOP321_PCIIRSR = 0x0f;
88
89 for(i = IOP321_IRQ_OFS; i < NR_IOP321_IRQS; i++)
90 {
91 set_irq_chip(i, &ext_chip);
92 set_irq_handler(i, do_level_IRQ);
93 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
94
95 }
96}
97
diff --git a/arch/arm/mach-iop3xx/iop321-pci.c b/arch/arm/mach-iop3xx/iop321-pci.c
deleted file mode 100644
index 8ba6a0e23134..000000000000
--- a/arch/arm/mach-iop3xx/iop321-pci.c
+++ /dev/null
@@ -1,220 +0,0 @@
1/*
2 * arch/arm/mach-iop3xx/iop321-pci.c
3 *
4 * PCI support for the Intel IOP321 chipset
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/ioport.h>
20
21#include <asm/io.h>
22#include <asm/irq.h>
23#include <asm/system.h>
24#include <asm/hardware.h>
25#include <asm/mach/pci.h>
26
27#include <asm/arch/iop321.h>
28
29// #define DEBUG
30
31#ifdef DEBUG
32#define DBG(x...) printk(x)
33#else
34#define DBG(x...) do { } while (0)
35#endif
36
37/*
38 * This routine builds either a type0 or type1 configuration command. If the
39 * bus is on the 80321 then a type0 made, else a type1 is created.
40 */
41static u32 iop321_cfg_address(struct pci_bus *bus, int devfn, int where)
42{
43 struct pci_sys_data *sys = bus->sysdata;
44 u32 addr;
45
46 if (sys->busnr == bus->number)
47 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
48 else
49 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
50
51 addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
52
53 return addr;
54}
55
56/*
57 * This routine checks the status of the last configuration cycle. If an error
58 * was detected it returns a 1, else it returns a 0. The errors being checked
59 * are parity, master abort, target abort (master and target). These types of
60 * errors occure during a config cycle where there is no device, like during
61 * the discovery stage.
62 */
63static int iop321_pci_status(void)
64{
65 unsigned int status;
66 int ret = 0;
67
68 /*
69 * Check the status registers.
70 */
71 status = *IOP321_ATUSR;
72 if (status & 0xf900)
73 {
74 DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
75 *IOP321_ATUSR = status & 0xf900;
76 ret = 1;
77 }
78 status = *IOP321_ATUISR;
79 if (status & 0x679f)
80 {
81 DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
82 *IOP321_ATUISR = status & 0x679f;
83 ret = 1;
84 }
85 return ret;
86}
87
88/*
89 * Simply write the address register and read the configuration
90 * data. Note that the 4 nop's ensure that we are able to handle
91 * a delayed abort (in theory.)
92 */
93static inline u32 iop321_read(unsigned long addr)
94{
95 u32 val;
96
97 __asm__ __volatile__(
98 "str %1, [%2]\n\t"
99 "ldr %0, [%3]\n\t"
100 "nop\n\t"
101 "nop\n\t"
102 "nop\n\t"
103 "nop\n\t"
104 : "=r" (val)
105 : "r" (addr), "r" (IOP321_OCCAR), "r" (IOP321_OCCDR));
106
107 return val;
108}
109
110/*
111 * The read routines must check the error status of the last configuration
112 * cycle. If there was an error, the routine returns all hex f's.
113 */
114static int
115iop321_read_config(struct pci_bus *bus, unsigned int devfn, int where,
116 int size, u32 *value)
117{
118 unsigned long addr = iop321_cfg_address(bus, devfn, where);
119 u32 val = iop321_read(addr) >> ((where & 3) * 8);
120
121 if( iop321_pci_status() )
122 val = 0xffffffff;
123
124 *value = val;
125
126 return PCIBIOS_SUCCESSFUL;
127}
128
129static int
130iop321_write_config(struct pci_bus *bus, unsigned int devfn, int where,
131 int size, u32 value)
132{
133 unsigned long addr = iop321_cfg_address(bus, devfn, where);
134 u32 val;
135
136 if (size != 4) {
137 val = iop321_read(addr);
138 if (!iop321_pci_status() == 0)
139 return PCIBIOS_SUCCESSFUL;
140
141 where = (where & 3) * 8;
142
143 if (size == 1)
144 val &= ~(0xff << where);
145 else
146 val &= ~(0xffff << where);
147
148 *IOP321_OCCDR = val | value << where;
149 } else {
150 asm volatile(
151 "str %1, [%2]\n\t"
152 "str %0, [%3]\n\t"
153 "nop\n\t"
154 "nop\n\t"
155 "nop\n\t"
156 "nop\n\t"
157 :
158 : "r" (value), "r" (addr),
159 "r" (IOP321_OCCAR), "r" (IOP321_OCCDR));
160 }
161
162 return PCIBIOS_SUCCESSFUL;
163}
164
165static struct pci_ops iop321_ops = {
166 .read = iop321_read_config,
167 .write = iop321_write_config,
168};
169
170/*
171 * When a PCI device does not exist during config cycles, the 80200 gets a
172 * bus error instead of returning 0xffffffff. This handler simply returns.
173 */
174int
175iop321_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
176{
177 DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
178 addr, fsr, regs->ARM_pc, regs->ARM_lr);
179
180 /*
181 * If it was an imprecise abort, then we need to correct the
182 * return address to be _after_ the instruction.
183 */
184 if (fsr & (1 << 10))
185 regs->ARM_pc += 4;
186
187 return 0;
188}
189
190/*
191 * Scan an IOP321 PCI bus. sys->bus defines which bus we scan.
192 */
193struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *sys)
194{
195 return pci_scan_bus(sys->busnr, &iop321_ops, sys);
196}
197
198void iop321_init(void)
199{
200 DBG("PCI: Intel 80321 PCI init code.\n");
201 DBG("ATU: IOP321_ATUCMD=0x%04x\n", *IOP321_ATUCMD);
202 DBG("ATU: IOP321_OMWTVR0=0x%04x, IOP321_OIOWTVR=0x%04x\n",
203 *IOP321_OMWTVR0,
204 *IOP321_OIOWTVR);
205 DBG("ATU: IOP321_ATUCR=0x%08x\n", *IOP321_ATUCR);
206 DBG("ATU: IOP321_IABAR0=0x%08x IOP321_IALR0=0x%08x IOP321_IATVR0=%08x\n",
207 *IOP321_IABAR0, *IOP321_IALR0, *IOP321_IATVR0);
208 DBG("ATU: IOP321_OMWTVR0=0x%08x\n", *IOP321_OMWTVR0);
209 DBG("ATU: IOP321_IABAR1=0x%08x IOP321_IALR1=0x%08x\n",
210 *IOP321_IABAR1, *IOP321_IALR1);
211 DBG("ATU: IOP321_ERBAR=0x%08x IOP321_ERLR=0x%08x IOP321_ERTVR=%08x\n",
212 *IOP321_ERBAR, *IOP321_ERLR, *IOP321_ERTVR);
213 DBG("ATU: IOP321_IABAR2=0x%08x IOP321_IALR2=0x%08x IOP321_IATVR2=%08x\n",
214 *IOP321_IABAR2, *IOP321_IALR2, *IOP321_IATVR2);
215 DBG("ATU: IOP321_IABAR3=0x%08x IOP321_IALR3=0x%08x IOP321_IATVR3=%08x\n",
216 *IOP321_IABAR3, *IOP321_IALR3, *IOP321_IATVR3);
217
218 hook_fault_code(16+6, iop321_pci_abort, SIGBUS, "imprecise external abort");
219}
220
diff --git a/arch/arm/mach-iop3xx/iop321-setup.c b/arch/arm/mach-iop3xx/iop321-setup.c
deleted file mode 100644
index b6d096903c4a..000000000000
--- a/arch/arm/mach-iop3xx/iop321-setup.c
+++ /dev/null
@@ -1,173 +0,0 @@
1/*
2 * linux/arch/arm/mach-iop3xx/iop321-setup.c
3 *
4 * Author: Nicolas Pitre <nico@cam.org>
5 * Copyright (C) 2001 MontaVista Software, Inc.
6 * Copyright (C) 2004 Intel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13#include <linux/mm.h>
14#include <linux/init.h>
15#include <linux/major.h>
16#include <linux/fs.h>
17#include <linux/platform_device.h>
18#include <linux/serial.h>
19#include <linux/tty.h>
20#include <linux/serial_core.h>
21
22#include <asm/io.h>
23#include <asm/pgtable.h>
24#include <asm/page.h>
25#include <asm/mach/map.h>
26#include <asm/setup.h>
27#include <asm/system.h>
28#include <asm/memory.h>
29#include <asm/hardware.h>
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32
33#define IOP321_UART_XTAL 1843200
34
35/*
36 * Standard IO mapping for all IOP321 based systems
37 */
38static struct map_desc iop321_std_desc[] __initdata = {
39 { /* mem mapped registers */
40 .virtual = IOP321_VIRT_MEM_BASE,
41 .pfn = __phys_to_pfn(IOP321_PHYS_MEM_BASE),
42 .length = 0x00002000,
43 .type = MT_DEVICE
44 }, { /* PCI IO space */
45 .virtual = IOP321_PCI_LOWER_IO_VA,
46 .pfn = __phys_to_pfn(IOP321_PCI_LOWER_IO_PA),
47 .length = IOP321_PCI_IO_WINDOW_SIZE,
48 .type = MT_DEVICE
49 }
50};
51
52#ifdef CONFIG_ARCH_IQ80321
53#define UARTBASE IQ80321_UART
54#define IRQ_UART IRQ_IQ80321_UART
55#endif
56
57#ifdef CONFIG_ARCH_IQ31244
58#define UARTBASE IQ31244_UART
59#define IRQ_UART IRQ_IQ31244_UART
60#endif
61
62static struct uart_port iop321_serial_ports[] = {
63 {
64 .membase = (char*)(UARTBASE),
65 .mapbase = (UARTBASE),
66 .irq = IRQ_UART,
67 .flags = UPF_SKIP_TEST,
68 .iotype = UPIO_MEM,
69 .regshift = 0,
70 .uartclk = IOP321_UART_XTAL,
71 .line = 0,
72 .type = PORT_16550A,
73 .fifosize = 16
74 }
75};
76
77static struct resource iop32x_i2c_0_resources[] = {
78 [0] = {
79 .start = 0xfffff680,
80 .end = 0xfffff698,
81 .flags = IORESOURCE_MEM,
82 },
83 [1] = {
84 .start = IRQ_IOP321_I2C_0,
85 .end = IRQ_IOP321_I2C_0,
86 .flags = IORESOURCE_IRQ
87 }
88};
89
90static struct resource iop32x_i2c_1_resources[] = {
91 [0] = {
92 .start = 0xfffff6a0,
93 .end = 0xfffff6b8,
94 .flags = IORESOURCE_MEM,
95 },
96 [1] = {
97 .start = IRQ_IOP321_I2C_1,
98 .end = IRQ_IOP321_I2C_1,
99 .flags = IORESOURCE_IRQ
100 }
101};
102
103static struct platform_device iop32x_i2c_0_controller = {
104 .name = "IOP3xx-I2C",
105 .id = 0,
106 .num_resources = 2,
107 .resource = iop32x_i2c_0_resources
108};
109
110static struct platform_device iop32x_i2c_1_controller = {
111 .name = "IOP3xx-I2C",
112 .id = 1,
113 .num_resources = 2,
114 .resource = iop32x_i2c_1_resources
115};
116
117static struct platform_device *iop32x_devices[] __initdata = {
118 &iop32x_i2c_0_controller,
119 &iop32x_i2c_1_controller
120};
121
122void __init iop32x_init(void)
123{
124 if(iop_is_321())
125 {
126 platform_add_devices(iop32x_devices,
127 ARRAY_SIZE(iop32x_devices));
128 }
129}
130
131void __init iop321_map_io(void)
132{
133 iotable_init(iop321_std_desc, ARRAY_SIZE(iop321_std_desc));
134 early_serial_setup(&iop321_serial_ports[0]);
135}
136
137#ifdef CONFIG_ARCH_IQ80321
138extern void iq80321_map_io(void);
139extern struct sys_timer iop321_timer;
140extern void iop321_init_time(void);
141#endif
142
143#ifdef CONFIG_ARCH_IQ31244
144extern void iq31244_map_io(void);
145extern struct sys_timer iop321_timer;
146extern void iop321_init_time(void);
147#endif
148
149#if defined(CONFIG_ARCH_IQ80321)
150MACHINE_START(IQ80321, "Intel IQ80321")
151 /* Maintainer: Intel Corporation */
152 .phys_io = IQ80321_UART,
153 .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc,
154 .map_io = iq80321_map_io,
155 .init_irq = iop321_init_irq,
156 .timer = &iop321_timer,
157 .boot_params = 0xa0000100,
158 .init_machine = iop32x_init,
159MACHINE_END
160#elif defined(CONFIG_ARCH_IQ31244)
161MACHINE_START(IQ31244, "Intel IQ31244")
162 /* Maintainer: Intel Corp. */
163 .phys_io = IQ31244_UART,
164 .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
165 .map_io = iq31244_map_io,
166 .init_irq = iop321_init_irq,
167 .timer = &iop321_timer,
168 .boot_params = 0xa0000100,
169 .init_machine = iop32x_init,
170MACHINE_END
171#else
172#error No machine descriptor defined for this IOP3XX implementation
173#endif
diff --git a/arch/arm/mach-iop3xx/iop321-time.c b/arch/arm/mach-iop3xx/iop321-time.c
deleted file mode 100644
index 04b1a6f7ebae..000000000000
--- a/arch/arm/mach-iop3xx/iop321-time.c
+++ /dev/null
@@ -1,108 +0,0 @@
1/*
2 * arch/arm/mach-iop3xx/iop321-time.c
3 *
4 * Timer code for IOP321 based systems
5 *
6 * Author: Deepak Saxena <dsaxena@mvista.com>
7 *
8 * Copyright 2002-2003 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/time.h>
19#include <linux/init.h>
20#include <linux/timex.h>
21
22#include <asm/hardware.h>
23#include <asm/io.h>
24#include <asm/irq.h>
25#include <asm/uaccess.h>
26#include <asm/mach/irq.h>
27#include <asm/mach/time.h>
28
29#define IOP321_TIME_SYNC 0
30
31static inline unsigned long get_elapsed(void)
32{
33 return LATCH - *IOP321_TU_TCR0;
34}
35
36static unsigned long iop321_gettimeoffset(void)
37{
38 unsigned long elapsed, usec;
39 u32 tisr1, tisr2;
40
41 /*
42 * If an interrupt was pending before we read the timer,
43 * we've already wrapped. Factor this into the time.
44 * If an interrupt was pending after we read the timer,
45 * it may have wrapped between checking the interrupt
46 * status and reading the timer. Re-read the timer to
47 * be sure its value is after the wrap.
48 */
49
50 asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr1));
51 elapsed = get_elapsed();
52 asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr2));
53
54 if(tisr1 & 1)
55 elapsed += LATCH;
56 else if (tisr2 & 1)
57 elapsed = LATCH + get_elapsed();
58
59 /*
60 * Now convert them to usec.
61 */
62 usec = (unsigned long)(elapsed / (CLOCK_TICK_RATE/1000000));
63
64 return usec;
65}
66
67static irqreturn_t
68iop321_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
69{
70 u32 tisr;
71
72 write_seqlock(&xtime_lock);
73
74 asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr));
75 tisr |= 1;
76 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (tisr));
77
78 timer_tick(regs);
79
80 write_sequnlock(&xtime_lock);
81
82 return IRQ_HANDLED;
83}
84
85static struct irqaction iop321_timer_irq = {
86 .name = "IOP321 Timer Tick",
87 .handler = iop321_timer_interrupt,
88 .flags = IRQF_DISABLED | IRQF_TIMER,
89};
90
91static void __init iop321_timer_init(void)
92{
93 u32 timer_ctl;
94
95 setup_irq(IRQ_IOP321_TIMER0, &iop321_timer_irq);
96
97 timer_ctl = IOP321_TMR_EN | IOP321_TMR_PRIVILEGED | IOP321_TMR_RELOAD |
98 IOP321_TMR_RATIO_1_1;
99
100 asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (LATCH));
101
102 asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl));
103}
104
105struct sys_timer iop321_timer = {
106 .init = &iop321_timer_init,
107 .offset = iop321_gettimeoffset,
108};
diff --git a/arch/arm/mach-iop3xx/iop331-irq.c b/arch/arm/mach-iop3xx/iop331-irq.c
deleted file mode 100644
index cab11722ced2..000000000000
--- a/arch/arm/mach-iop3xx/iop331-irq.c
+++ /dev/null
@@ -1,129 +0,0 @@
1/*
2 * linux/arch/arm/mach-iop3xx/iop331-irq.c
3 *
4 * Generic IOP331 IRQ handling functionality
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2003 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 *
14 */
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18
19#include <asm/mach/irq.h>
20#include <asm/irq.h>
21#include <asm/hardware.h>
22
23#include <asm/mach-types.h>
24
25static u32 iop331_mask0 = 0;
26static u32 iop331_mask1 = 0;
27
28static inline void intctl_write0(u32 val)
29{
30 // INTCTL0
31 asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
32}
33
34static inline void intctl_write1(u32 val)
35{
36 // INTCTL1
37 asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val));
38}
39
40static inline void intstr_write0(u32 val)
41{
42 // INTSTR0
43 asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val));
44}
45
46static inline void intstr_write1(u32 val)
47{
48 // INTSTR1
49 asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val));
50}
51
52static void
53iop331_irq_mask1 (unsigned int irq)
54{
55 iop331_mask0 &= ~(1 << (irq - IOP331_IRQ_OFS));
56 intctl_write0(iop331_mask0);
57}
58
59static void
60iop331_irq_mask2 (unsigned int irq)
61{
62 iop331_mask1 &= ~(1 << (irq - IOP331_IRQ_OFS - 32));
63 intctl_write1(iop331_mask1);
64}
65
66static void
67iop331_irq_unmask1(unsigned int irq)
68{
69 iop331_mask0 |= (1 << (irq - IOP331_IRQ_OFS));
70 intctl_write0(iop331_mask0);
71}
72
73static void
74iop331_irq_unmask2(unsigned int irq)
75{
76 iop331_mask1 |= (1 << (irq - IOP331_IRQ_OFS - 32));
77 intctl_write1(iop331_mask1);
78}
79
80struct irq_chip iop331_irqchip1 = {
81 .name = "IOP-1",
82 .ack = iop331_irq_mask1,
83 .mask = iop331_irq_mask1,
84 .unmask = iop331_irq_unmask1,
85};
86
87struct irq_chip iop331_irqchip2 = {
88 .name = "IOP-2",
89 .ack = iop331_irq_mask2,
90 .mask = iop331_irq_mask2,
91 .unmask = iop331_irq_unmask2,
92};
93
94void __init iop331_init_irq(void)
95{
96 unsigned int i, tmp;
97
98 /* Enable access to coprocessor 6 for dealing with IRQs.
99 * From RMK:
100 * Basically, the Intel documentation here is poor. It appears that
101 * you need to set the bit to be able to access the coprocessor from
102 * SVC mode. Whether that allows access from user space or not is
103 * unclear.
104 */
105 asm volatile (
106 "mrc p15, 0, %0, c15, c1, 0\n\t"
107 "orr %0, %0, %1\n\t"
108 "mcr p15, 0, %0, c15, c1, 0\n\t"
109 /* The action is delayed, so we have to do this: */
110 "mrc p15, 0, %0, c15, c1, 0\n\t"
111 "mov %0, %0\n\t"
112 "sub pc, pc, #4"
113 : "=r" (tmp) : "i" (1 << 6) );
114
115 intctl_write0(0); // disable all interrupts
116 intctl_write1(0);
117 intstr_write0(0); // treat all as IRQ
118 intstr_write1(0);
119 if(machine_is_iq80331()) // all interrupts are inputs to chip
120 *IOP331_PCIIRSR = 0x0f;
121
122 for(i = IOP331_IRQ_OFS; i < NR_IOP331_IRQS; i++)
123 {
124 set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2);
125 set_irq_handler(i, do_level_IRQ);
126 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
127 }
128}
129
diff --git a/arch/arm/mach-iop3xx/iop331-pci.c b/arch/arm/mach-iop3xx/iop331-pci.c
deleted file mode 100644
index 44dd213b48a3..000000000000
--- a/arch/arm/mach-iop3xx/iop331-pci.c
+++ /dev/null
@@ -1,222 +0,0 @@
1/*
2 * arch/arm/mach-iop3xx/iop331-pci.c
3 *
4 * PCI support for the Intel IOP331 chipset
5 *
6 * Author: Dave Jiang (dave.jiang@intel.com)
7 * Copyright (C) 2003, 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/ioport.h>
20
21#include <asm/io.h>
22#include <asm/irq.h>
23#include <asm/system.h>
24#include <asm/hardware.h>
25#include <asm/mach/pci.h>
26
27#include <asm/arch/iop331.h>
28
29#undef DEBUG
30#undef DEBUG1
31
32#ifdef DEBUG
33#define DBG(x...) printk(x)
34#else
35#define DBG(x...) do { } while (0)
36#endif
37
38#ifdef DEBUG1
39#define DBG1(x...) printk(x)
40#else
41#define DBG1(x...) do { } while (0)
42#endif
43
44/*
45 * This routine builds either a type0 or type1 configuration command. If the
46 * bus is on the 80331 then a type0 made, else a type1 is created.
47 */
48static u32 iop331_cfg_address(struct pci_bus *bus, int devfn, int where)
49{
50 struct pci_sys_data *sys = bus->sysdata;
51 u32 addr;
52
53 if (sys->busnr == bus->number)
54 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
55 else
56 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
57
58 addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
59
60 return addr;
61}
62
63/*
64 * This routine checks the status of the last configuration cycle. If an error
65 * was detected it returns a 1, else it returns a 0. The errors being checked
66 * are parity, master abort, target abort (master and target). These types of
67 * errors occure during a config cycle where there is no device, like during
68 * the discovery stage.
69 */
70static int iop331_pci_status(void)
71{
72 unsigned int status;
73 int ret = 0;
74
75 /*
76 * Check the status registers.
77 */
78 status = *IOP331_ATUSR;
79 if (status & 0xf900)
80 {
81 DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
82 *IOP331_ATUSR = status & 0xf900;
83 ret = 1;
84 }
85 status = *IOP331_ATUISR;
86 if (status & 0x679f)
87 {
88 DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
89 *IOP331_ATUISR = status & 0x679f;
90 ret = 1;
91 }
92 return ret;
93}
94
95/*
96 * Simply write the address register and read the configuration
97 * data. Note that the 4 nop's ensure that we are able to handle
98 * a delayed abort (in theory.)
99 */
100static inline u32 iop331_read(unsigned long addr)
101{
102 u32 val;
103
104 __asm__ __volatile__(
105 "str %1, [%2]\n\t"
106 "ldr %0, [%3]\n\t"
107 "nop\n\t"
108 "nop\n\t"
109 "nop\n\t"
110 "nop\n\t"
111 : "=r" (val)
112 : "r" (addr), "r" (IOP331_OCCAR), "r" (IOP331_OCCDR));
113
114 return val;
115}
116
117/*
118 * The read routines must check the error status of the last configuration
119 * cycle. If there was an error, the routine returns all hex f's.
120 */
121static int
122iop331_read_config(struct pci_bus *bus, unsigned int devfn, int where,
123 int size, u32 *value)
124{
125 unsigned long addr = iop331_cfg_address(bus, devfn, where);
126 u32 val = iop331_read(addr) >> ((where & 3) * 8);
127
128 if( iop331_pci_status() )
129 val = 0xffffffff;
130
131 *value = val;
132
133 return PCIBIOS_SUCCESSFUL;
134}
135
136static int
137iop331_write_config(struct pci_bus *bus, unsigned int devfn, int where,
138 int size, u32 value)
139{
140 unsigned long addr = iop331_cfg_address(bus, devfn, where);
141 u32 val;
142
143 if (size != 4) {
144 val = iop331_read(addr);
145 if (!iop331_pci_status() == 0)
146 return PCIBIOS_SUCCESSFUL;
147
148 where = (where & 3) * 8;
149
150 if (size == 1)
151 val &= ~(0xff << where);
152 else
153 val &= ~(0xffff << where);
154
155 *IOP331_OCCDR = val | value << where;
156 } else {
157 asm volatile(
158 "str %1, [%2]\n\t"
159 "str %0, [%3]\n\t"
160 "nop\n\t"
161 "nop\n\t"
162 "nop\n\t"
163 "nop\n\t"
164 :
165 : "r" (value), "r" (addr),
166 "r" (IOP331_OCCAR), "r" (IOP331_OCCDR));
167 }
168
169 return PCIBIOS_SUCCESSFUL;
170}
171
172static struct pci_ops iop331_ops = {
173 .read = iop331_read_config,
174 .write = iop331_write_config,
175};
176
177/*
178 * When a PCI device does not exist during config cycles, the XScale gets a
179 * bus error instead of returning 0xffffffff. This handler simply returns.
180 */
181int
182iop331_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
183{
184 DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
185 addr, fsr, regs->ARM_pc, regs->ARM_lr);
186
187 /*
188 * If it was an imprecise abort, then we need to correct the
189 * return address to be _after_ the instruction.
190 */
191 if (fsr & (1 << 10))
192 regs->ARM_pc += 4;
193
194 return 0;
195}
196
197/*
198 * Scan an IOP331 PCI bus. sys->bus defines which bus we scan.
199 */
200struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *sys)
201{
202 return pci_scan_bus(sys->busnr, &iop331_ops, sys);
203}
204
205void iop331_init(void)
206{
207 DBG1("PCI: Intel 80331 PCI init code.\n");
208 DBG1("\tATU: IOP331_ATUCMD=0x%04x\n", *IOP331_ATUCMD);
209 DBG1("\tATU: IOP331_OMWTVR0=0x%04x, IOP331_OIOWTVR=0x%04x\n",
210 *IOP331_OMWTVR0,
211 *IOP331_OIOWTVR);
212 DBG1("\tATU: IOP331_OMWTVR1=0x%04x\n", *IOP331_OMWTVR1);
213 DBG1("\tATU: IOP331_ATUCR=0x%08x\n", *IOP331_ATUCR);
214 DBG1("\tATU: IOP331_IABAR0=0x%08x IOP331_IALR0=0x%08x IOP331_IATVR0=%08x\n", *IOP331_IABAR0, *IOP331_IALR0, *IOP331_IATVR0);
215 DBG1("\tATU: IOP31_IABAR1=0x%08x IOP331_IALR1=0x%08x\n", *IOP331_IABAR1, *IOP331_IALR1);
216 DBG1("\tATU: IOP331_ERBAR=0x%08x IOP331_ERLR=0x%08x IOP331_ERTVR=%08x\n", *IOP331_ERBAR, *IOP331_ERLR, *IOP331_ERTVR);
217 DBG1("\tATU: IOP331_IABAR2=0x%08x IOP331_IALR2=0x%08x IOP331_IATVR2=%08x\n", *IOP331_IABAR2, *IOP331_IALR2, *IOP331_IATVR2);
218 DBG1("\tATU: IOP331_IABAR3=0x%08x IOP331_IALR3=0x%08x IOP331_IATVR3=%08x\n", *IOP331_IABAR3, *IOP331_IALR3, *IOP331_IATVR3);
219
220 hook_fault_code(16+6, iop331_pci_abort, SIGBUS, "imprecise external abort");
221}
222
diff --git a/arch/arm/mach-iop3xx/iop331-setup.c b/arch/arm/mach-iop3xx/iop331-setup.c
deleted file mode 100644
index 3cc98d892ad4..000000000000
--- a/arch/arm/mach-iop3xx/iop331-setup.c
+++ /dev/null
@@ -1,221 +0,0 @@
1/*
2 * linux/arch/arm/mach-iop3xx/iop331-setup.c
3 *
4 * Author: Dave Jiang (dave.jiang@intel.com)
5 * Copyright (C) 2004 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12#include <linux/mm.h>
13#include <linux/init.h>
14#include <linux/major.h>
15#include <linux/fs.h>
16#include <linux/platform_device.h>
17#include <linux/serial.h>
18#include <linux/tty.h>
19#include <linux/serial_8250.h>
20
21#include <asm/io.h>
22#include <asm/pgtable.h>
23#include <asm/page.h>
24#include <asm/mach/map.h>
25#include <asm/setup.h>
26#include <asm/system.h>
27#include <asm/memory.h>
28#include <asm/hardware.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32#define IOP331_UART_XTAL 33334000
33
34/*
35 * Standard IO mapping for all IOP331 based systems
36 */
37static struct map_desc iop331_std_desc[] __initdata = {
38 { /* mem mapped registers */
39 .virtual = IOP331_VIRT_MEM_BASE,
40 .pfn = __phys_to_pfn(IOP331_PHYS_MEM_BASE),
41 .length = 0x00002000,
42 .type = MT_DEVICE
43 }, { /* PCI IO space */
44 .virtual = IOP331_PCI_LOWER_IO_VA,
45 .pfn = __phys_to_pfn(IOP331_PCI_LOWER_IO_PA),
46 .length = IOP331_PCI_IO_WINDOW_SIZE,
47 .type = MT_DEVICE
48 }
49};
50
51static struct resource iop33x_uart0_resources[] = {
52 [0] = {
53 .start = IOP331_UART0_PHYS,
54 .end = IOP331_UART0_PHYS + 0x3f,
55 .flags = IORESOURCE_MEM,
56 },
57 [1] = {
58 .start = IRQ_IOP331_UART0,
59 .end = IRQ_IOP331_UART0,
60 .flags = IORESOURCE_IRQ
61 }
62};
63
64static struct resource iop33x_uart1_resources[] = {
65 [0] = {
66 .start = IOP331_UART1_PHYS,
67 .end = IOP331_UART1_PHYS + 0x3f,
68 .flags = IORESOURCE_MEM,
69 },
70 [1] = {
71 .start = IRQ_IOP331_UART1,
72 .end = IRQ_IOP331_UART1,
73 .flags = IORESOURCE_IRQ
74 }
75};
76
77static struct plat_serial8250_port iop33x_uart0_data[] = {
78 {
79 .membase = (char*)(IOP331_UART0_VIRT),
80 .mapbase = (IOP331_UART0_PHYS),
81 .irq = IRQ_IOP331_UART0,
82 .uartclk = IOP331_UART_XTAL,
83 .regshift = 2,
84 .iotype = UPIO_MEM,
85 .flags = UPF_SKIP_TEST,
86 },
87 { },
88};
89
90static struct plat_serial8250_port iop33x_uart1_data[] = {
91 {
92 .membase = (char*)(IOP331_UART1_VIRT),
93 .mapbase = (IOP331_UART1_PHYS),
94 .irq = IRQ_IOP331_UART1,
95 .uartclk = IOP331_UART_XTAL,
96 .regshift = 2,
97 .iotype = UPIO_MEM,
98 .flags = UPF_SKIP_TEST,
99 },
100 { },
101};
102
103static struct platform_device iop33x_uart0 = {
104 .name = "serial8250",
105 .id = PLAT8250_DEV_PLATFORM,
106 .dev.platform_data = iop33x_uart0_data,
107 .num_resources = 2,
108 .resource = iop33x_uart0_resources,
109};
110
111static struct platform_device iop33x_uart1 = {
112 .name = "serial8250",
113 .id = PLAT8250_DEV_PLATFORM1,
114 .dev.platform_data = iop33x_uart1_data,
115 .num_resources = 2,
116 .resource = iop33x_uart1_resources,
117};
118
119static struct resource iop33x_i2c_0_resources[] = {
120 [0] = {
121 .start = 0xfffff680,
122 .end = 0xfffff698,
123 .flags = IORESOURCE_MEM,
124 },
125 [1] = {
126 .start = IRQ_IOP331_I2C_0,
127 .end = IRQ_IOP331_I2C_0,
128 .flags = IORESOURCE_IRQ
129 }
130};
131
132static struct resource iop33x_i2c_1_resources[] = {
133 [0] = {
134 .start = 0xfffff6a0,
135 .end = 0xfffff6b8,
136 .flags = IORESOURCE_MEM,
137 },
138 [1] = {
139 .start = IRQ_IOP331_I2C_1,
140 .end = IRQ_IOP331_I2C_1,
141 .flags = IORESOURCE_IRQ
142 }
143};
144
145static struct platform_device iop33x_i2c_0_controller = {
146 .name = "IOP3xx-I2C",
147 .id = 0,
148 .num_resources = 2,
149 .resource = iop33x_i2c_0_resources
150};
151
152static struct platform_device iop33x_i2c_1_controller = {
153 .name = "IOP3xx-I2C",
154 .id = 1,
155 .num_resources = 2,
156 .resource = iop33x_i2c_1_resources
157};
158
159static struct platform_device *iop33x_devices[] __initdata = {
160 &iop33x_uart0,
161 &iop33x_uart1,
162 &iop33x_i2c_0_controller,
163 &iop33x_i2c_1_controller
164};
165
166void __init iop33x_init(void)
167{
168 if(iop_is_331())
169 {
170 platform_add_devices(iop33x_devices,
171 ARRAY_SIZE(iop33x_devices));
172 }
173}
174
175void __init iop331_map_io(void)
176{
177 iotable_init(iop331_std_desc, ARRAY_SIZE(iop331_std_desc));
178}
179
180#ifdef CONFIG_ARCH_IOP331
181extern void iop331_init_irq(void);
182extern struct sys_timer iop331_timer;
183#endif
184
185#ifdef CONFIG_ARCH_IQ80331
186extern void iq80331_map_io(void);
187#endif
188
189#ifdef CONFIG_MACH_IQ80332
190extern void iq80332_map_io(void);
191#endif
192
193#if defined(CONFIG_ARCH_IQ80331)
194MACHINE_START(IQ80331, "Intel IQ80331")
195 /* Maintainer: Intel Corp. */
196 .phys_io = 0xfefff000,
197 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, // virtual, physical
198 .map_io = iq80331_map_io,
199 .init_irq = iop331_init_irq,
200 .timer = &iop331_timer,
201 .boot_params = 0x0100,
202 .init_machine = iop33x_init,
203MACHINE_END
204
205#elif defined(CONFIG_MACH_IQ80332)
206MACHINE_START(IQ80332, "Intel IQ80332")
207 /* Maintainer: Intel Corp. */
208 .phys_io = 0xfefff000,
209 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, // virtual, physical
210 .map_io = iq80332_map_io,
211 .init_irq = iop331_init_irq,
212 .timer = &iop331_timer,
213 .boot_params = 0x0100,
214 .init_machine = iop33x_init,
215MACHINE_END
216
217#else
218#error No machine descriptor defined for this IOP3XX implementation
219#endif
220
221
diff --git a/arch/arm/mach-iop3xx/iop331-time.c b/arch/arm/mach-iop3xx/iop331-time.c
deleted file mode 100644
index 0c09e74c5740..000000000000
--- a/arch/arm/mach-iop3xx/iop331-time.c
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * arch/arm/mach-iop3xx/iop331-time.c
3 *
4 * Timer code for IOP331 based systems
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 *
8 * Copyright 2003 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/time.h>
19#include <linux/init.h>
20#include <linux/timex.h>
21
22#include <asm/hardware.h>
23#include <asm/io.h>
24#include <asm/irq.h>
25#include <asm/uaccess.h>
26#include <asm/mach/irq.h>
27#include <asm/mach/time.h>
28
29static inline unsigned long get_elapsed(void)
30{
31 return LATCH - *IOP331_TU_TCR0;
32}
33
34static unsigned long iop331_gettimeoffset(void)
35{
36 unsigned long elapsed, usec;
37 u32 tisr1, tisr2;
38
39 /*
40 * If an interrupt was pending before we read the timer,
41 * we've already wrapped. Factor this into the time.
42 * If an interrupt was pending after we read the timer,
43 * it may have wrapped between checking the interrupt
44 * status and reading the timer. Re-read the timer to
45 * be sure its value is after the wrap.
46 */
47
48 asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr1));
49 elapsed = get_elapsed();
50 asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr2));
51
52 if(tisr1 & 1)
53 elapsed += LATCH;
54 else if (tisr2 & 1)
55 elapsed = LATCH + get_elapsed();
56
57 /*
58 * Now convert them to usec.
59 */
60 usec = (unsigned long)(elapsed / (CLOCK_TICK_RATE/1000000));
61
62 return usec;
63}
64
65static irqreturn_t
66iop331_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
67{
68 u32 tisr;
69
70 write_seqlock(&xtime_lock);
71
72 asm volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (tisr));
73 tisr |= 1;
74 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (tisr));
75
76 timer_tick(regs);
77
78 write_sequnlock(&xtime_lock);
79 return IRQ_HANDLED;
80}
81
82static struct irqaction iop331_timer_irq = {
83 .name = "IOP331 Timer Tick",
84 .handler = iop331_timer_interrupt,
85 .flags = IRQF_DISABLED | IRQF_TIMER,
86};
87
88static void __init iop331_timer_init(void)
89{
90 u32 timer_ctl;
91
92 setup_irq(IRQ_IOP331_TIMER0, &iop331_timer_irq);
93
94 timer_ctl = IOP331_TMR_EN | IOP331_TMR_PRIVILEGED | IOP331_TMR_RELOAD |
95 IOP331_TMR_RATIO_1_1;
96
97 asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (LATCH));
98
99 asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl));
100
101}
102
103struct sys_timer iop331_timer = {
104 .init = iop331_timer_init,
105 .offset = iop331_gettimeoffset,
106};
diff --git a/arch/arm/mach-iop3xx/iq31244-mm.c b/arch/arm/mach-iop3xx/iq31244-mm.c
deleted file mode 100644
index e874b54eefe3..000000000000
--- a/arch/arm/mach-iop3xx/iq31244-mm.c
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * linux/arch/arm/mach-iop3xx/mm.c
3 *
4 * Low level memory initialization for iq80321 platform
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/mm.h>
17#include <linux/init.h>
18
19#include <asm/io.h>
20#include <asm/pgtable.h>
21#include <asm/page.h>
22
23#include <asm/mach/map.h>
24
25
26/*
27 * IQ80321 specific IO mappings
28 *
29 * We use RedBoot's setup for the onboard devices.
30 */
31static struct map_desc iq31244_io_desc[] __initdata = {
32 { /* on-board devices */
33 .virtual = IQ31244_UART,
34 .pfn = __phys_to_pfn(IQ31244_UART),
35 .length = 0x00100000,
36 .type = MT_DEVICE
37 }
38};
39
40void __init iq31244_map_io(void)
41{
42 iop321_map_io();
43
44 iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
45}
diff --git a/arch/arm/mach-iop3xx/iq31244-pci.c b/arch/arm/mach-iop3xx/iq31244-pci.c
deleted file mode 100644
index f3c6413fa5bd..000000000000
--- a/arch/arm/mach-iop3xx/iq31244-pci.c
+++ /dev/null
@@ -1,129 +0,0 @@
1/*
2 * arch/arm/mach-iop3xx/iq80321-pci.c
3 *
4 * PCI support for the Intel IQ80321 reference board
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/init.h>
17#include <linux/string.h>
18#include <linux/slab.h>
19
20#include <asm/hardware.h>
21#include <asm/irq.h>
22#include <asm/mach/pci.h>
23#include <asm/mach-types.h>
24
25/*
26 * The following macro is used to lookup irqs in a standard table
27 * format for those systems that do not already have PCI
28 * interrupts properly routed. We assume 1 <= pin <= 4
29 */
30#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
31({ int _ctl_ = -1; \
32 unsigned int _idsel = idsel - minid; \
33 if (_idsel <= maxid) \
34 _ctl_ = pci_irq_table[_idsel][pin-1]; \
35 _ctl_; })
36
37#define INTA IRQ_IQ31244_INTA
38#define INTB IRQ_IQ31244_INTB
39#define INTC IRQ_IQ31244_INTC
40#define INTD IRQ_IQ31244_INTD
41
42#define INTE IRQ_IQ31244_I82546
43
44static inline int __init
45iq31244_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
46{
47 static int pci_irq_table[][4] = {
48 /*
49 * PCI IDSEL/INTPIN->INTLINE
50 * A B C D
51 */
52#ifdef CONFIG_ARCH_EP80219
53 {INTB, INTB, INTB, INTB}, /* CFlash */
54 {INTE, INTE, INTE, INTE}, /* 82551 Pro 100 */
55 {INTD, INTD, INTD, INTD}, /* PCI-X Slot */
56 {INTC, INTC, INTC, INTC}, /* SATA */
57#else
58 {INTB, INTB, INTB, INTB}, /* CFlash */
59 {INTC, INTC, INTC, INTC}, /* SATA */
60 {INTD, INTD, INTD, INTD}, /* PCI-X Slot */
61 {INTE, INTE, INTE, INTE}, /* 82546 GigE */
62#endif // CONFIG_ARCH_EP80219
63 };
64
65 BUG_ON(pin < 1 || pin > 4);
66
67 return PCI_IRQ_TABLE_LOOKUP(0, 7);
68}
69
70static int iq31244_setup(int nr, struct pci_sys_data *sys)
71{
72 struct resource *res;
73
74 if(nr != 0)
75 return 0;
76
77 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
78 if (!res)
79 panic("PCI: unable to alloc resources");
80
81 res[0].start = IOP321_PCI_LOWER_IO_VA;
82 res[0].end = IOP321_PCI_UPPER_IO_VA;
83 res[0].name = "IQ31244 PCI I/O Space";
84 res[0].flags = IORESOURCE_IO;
85
86 res[1].start = IOP321_PCI_LOWER_MEM_PA;
87 res[1].end = IOP321_PCI_UPPER_MEM_PA;
88 res[1].name = "IQ31244 PCI Memory Space";
89 res[1].flags = IORESOURCE_MEM;
90
91 request_resource(&ioport_resource, &res[0]);
92 request_resource(&iomem_resource, &res[1]);
93
94 sys->mem_offset = IOP321_PCI_MEM_OFFSET;
95 sys->io_offset = IOP321_PCI_IO_OFFSET;
96
97 sys->resource[0] = &res[0];
98 sys->resource[1] = &res[1];
99 sys->resource[2] = NULL;
100
101 return 1;
102}
103
104static void iq31244_preinit(void)
105{
106 iop321_init();
107}
108
109static struct hw_pci iq31244_pci __initdata = {
110 .swizzle = pci_std_swizzle,
111 .nr_controllers = 1,
112 .setup = iq31244_setup,
113 .scan = iop321_scan_bus,
114 .preinit = iq31244_preinit,
115 .map_irq = iq31244_map_irq
116};
117
118static int __init iq31244_pci_init(void)
119{
120 if (machine_is_iq31244())
121 pci_common_init(&iq31244_pci);
122 return 0;
123}
124
125subsys_initcall(iq31244_pci_init);
126
127
128
129
diff --git a/arch/arm/mach-iop3xx/iq80321-mm.c b/arch/arm/mach-iop3xx/iq80321-mm.c
deleted file mode 100644
index d9cac5e1fc3d..000000000000
--- a/arch/arm/mach-iop3xx/iq80321-mm.c
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * linux/arch/arm/mach-iop3xx/mm.c
3 *
4 * Low level memory initialization for iq80321 platform
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/mm.h>
17#include <linux/init.h>
18
19#include <asm/io.h>
20#include <asm/pgtable.h>
21#include <asm/page.h>
22
23#include <asm/mach/map.h>
24
25
26/*
27 * IQ80321 specific IO mappings
28 *
29 * We use RedBoot's setup for the onboard devices.
30 */
31static struct map_desc iq80321_io_desc[] __initdata = {
32 { /* on-board devices */
33 .virtual = IQ80321_UART,
34 .pfn = __phys_to_pfn(IQ80321_UART),
35 .length = 0x00100000,
36 .type = MT_DEVICE
37 }
38};
39
40void __init iq80321_map_io(void)
41{
42 iop321_map_io();
43
44 iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc));
45}
diff --git a/arch/arm/mach-iop3xx/iq80321-pci.c b/arch/arm/mach-iop3xx/iq80321-pci.c
deleted file mode 100644
index d9758d3f6e7f..000000000000
--- a/arch/arm/mach-iop3xx/iq80321-pci.c
+++ /dev/null
@@ -1,123 +0,0 @@
1/*
2 * arch/arm/mach-iop3xx/iq80321-pci.c
3 *
4 * PCI support for the Intel IQ80321 reference board
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/init.h>
17#include <linux/string.h>
18#include <linux/slab.h>
19
20#include <asm/hardware.h>
21#include <asm/irq.h>
22#include <asm/mach/pci.h>
23#include <asm/mach-types.h>
24
25/*
26 * The following macro is used to lookup irqs in a standard table
27 * format for those systems that do not already have PCI
28 * interrupts properly routed. We assume 1 <= pin <= 4
29 */
30#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
31({ int _ctl_ = -1; \
32 unsigned int _idsel = idsel - minid; \
33 if (_idsel <= maxid) \
34 _ctl_ = pci_irq_table[_idsel][pin-1]; \
35 _ctl_; })
36
37#define INTA IRQ_IQ80321_INTA
38#define INTB IRQ_IQ80321_INTB
39#define INTC IRQ_IQ80321_INTC
40#define INTD IRQ_IQ80321_INTD
41
42#define INTE IRQ_IQ80321_I82544
43
44static inline int __init
45iq80321_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
46{
47 static int pci_irq_table[][4] = {
48 /*
49 * PCI IDSEL/INTPIN->INTLINE
50 * A B C D
51 */
52 {INTE, INTE, INTE, INTE}, /* Gig-E */
53 {-1, -1, -1, -1}, /* Unused */
54 {INTC, INTD, INTA, INTB}, /* PCI-X Slot */
55 {-1, -1, -1, -1},
56 };
57
58 BUG_ON(pin < 1 || pin > 4);
59
60// return PCI_IRQ_TABLE_LOOKUP(4, 7);
61 return pci_irq_table[idsel%4][pin-1];
62}
63
64static int iq80321_setup(int nr, struct pci_sys_data *sys)
65{
66 struct resource *res;
67
68 if(nr != 0)
69 return 0;
70
71 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
72 if (!res)
73 panic("PCI: unable to alloc resources");
74
75 res[0].start = IOP321_PCI_LOWER_IO_VA;
76 res[0].end = IOP321_PCI_UPPER_IO_VA;
77 res[0].name = "IQ80321 PCI I/O Space";
78 res[0].flags = IORESOURCE_IO;
79
80 res[1].start = IOP321_PCI_LOWER_MEM_PA;
81 res[1].end = IOP321_PCI_UPPER_MEM_PA;
82 res[1].name = "IQ80321 PCI Memory Space";
83 res[1].flags = IORESOURCE_MEM;
84
85 request_resource(&ioport_resource, &res[0]);
86 request_resource(&iomem_resource, &res[1]);
87
88 sys->mem_offset = IOP321_PCI_MEM_OFFSET;
89 sys->io_offset = IOP321_PCI_IO_OFFSET;
90
91 sys->resource[0] = &res[0];
92 sys->resource[1] = &res[1];
93 sys->resource[2] = NULL;
94
95 return 1;
96}
97
98static void iq80321_preinit(void)
99{
100 iop321_init();
101}
102
103static struct hw_pci iq80321_pci __initdata = {
104 .swizzle = pci_std_swizzle,
105 .nr_controllers = 1,
106 .setup = iq80321_setup,
107 .scan = iop321_scan_bus,
108 .preinit = iq80321_preinit,
109 .map_irq = iq80321_map_irq
110};
111
112static int __init iq80321_pci_init(void)
113{
114 if (machine_is_iq80321())
115 pci_common_init(&iq80321_pci);
116 return 0;
117}
118
119subsys_initcall(iq80321_pci_init);
120
121
122
123
diff --git a/arch/arm/mach-iop3xx/iq80331-mm.c b/arch/arm/mach-iop3xx/iq80331-mm.c
deleted file mode 100644
index 129eb49b0670..000000000000
--- a/arch/arm/mach-iop3xx/iq80331-mm.c
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * linux/arch/arm/mach-iop3xx/mm.c
3 *
4 * Low level memory initialization for iq80331 platform
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2003 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/mm.h>
17#include <linux/init.h>
18
19#include <asm/io.h>
20#include <asm/pgtable.h>
21#include <asm/page.h>
22
23#include <asm/mach/map.h>
24
25
26/*
27 * IQ80331 specific IO mappings
28 *
29 * We use RedBoot's setup for the onboard devices.
30 */
31
32void __init iq80331_map_io(void)
33{
34 iop331_map_io();
35}
diff --git a/arch/arm/mach-iop3xx/iq80331-pci.c b/arch/arm/mach-iop3xx/iq80331-pci.c
deleted file mode 100644
index 40d861002492..000000000000
--- a/arch/arm/mach-iop3xx/iq80331-pci.c
+++ /dev/null
@@ -1,119 +0,0 @@
1/*
2 * arch/arm/mach-iop3xx/iq80331-pci.c
3 *
4 * PCI support for the Intel IQ80331 reference board
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2003, 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/init.h>
16#include <linux/string.h>
17#include <linux/slab.h>
18
19#include <asm/hardware.h>
20#include <asm/irq.h>
21#include <asm/mach/pci.h>
22#include <asm/mach-types.h>
23
24/*
25 * The following macro is used to lookup irqs in a standard table
26 * format for those systems that do not already have PCI
27 * interrupts properly routed. We assume 1 <= pin <= 4
28 */
29#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
30({ int _ctl_ = -1; \
31 unsigned int _idsel = idsel - minid; \
32 if (_idsel <= maxid) \
33 _ctl_ = pci_irq_table[_idsel][pin-1]; \
34 _ctl_; })
35
36#define INTA IRQ_IQ80331_INTA
37#define INTB IRQ_IQ80331_INTB
38#define INTC IRQ_IQ80331_INTC
39#define INTD IRQ_IQ80331_INTD
40
41//#define INTE IRQ_IQ80331_I82544
42
43static inline int __init
44iq80331_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
45{
46 static int pci_irq_table[][4] = {
47 /*
48 * PCI IDSEL/INTPIN->INTLINE
49 * A B C D
50 */
51 {INTB, INTC, INTD, INTA}, /* PCI-X Slot */
52 {INTC, INTC, INTC, INTC}, /* GigE */
53 };
54
55 BUG_ON(pin < 1 || pin > 4);
56
57 return PCI_IRQ_TABLE_LOOKUP(1, 7);
58}
59
60static int iq80331_setup(int nr, struct pci_sys_data *sys)
61{
62 struct resource *res;
63
64 if(nr != 0)
65 return 0;
66
67 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
68 if (!res)
69 panic("PCI: unable to alloc resources");
70
71 res[0].start = IOP331_PCI_LOWER_IO_VA;
72 res[0].end = IOP331_PCI_UPPER_IO_VA;
73 res[0].name = "IQ80331 PCI I/O Space";
74 res[0].flags = IORESOURCE_IO;
75
76 res[1].start = IOP331_PCI_LOWER_MEM_PA;
77 res[1].end = IOP331_PCI_UPPER_MEM_PA;
78 res[1].name = "IQ80331 PCI Memory Space";
79 res[1].flags = IORESOURCE_MEM;
80
81 request_resource(&ioport_resource, &res[0]);
82 request_resource(&iomem_resource, &res[1]);
83
84 sys->mem_offset = IOP331_PCI_MEM_OFFSET;
85 sys->io_offset = IOP331_PCI_IO_OFFSET;
86
87 sys->resource[0] = &res[0];
88 sys->resource[1] = &res[1];
89 sys->resource[2] = NULL;
90
91 return 1;
92}
93
94static void iq80331_preinit(void)
95{
96 iop331_init();
97}
98
99static struct hw_pci iq80331_pci __initdata = {
100 .swizzle = pci_std_swizzle,
101 .nr_controllers = 1,
102 .setup = iq80331_setup,
103 .scan = iop331_scan_bus,
104 .preinit = iq80331_preinit,
105 .map_irq = iq80331_map_irq
106};
107
108static int __init iq80331_pci_init(void)
109{
110 if (machine_is_iq80331())
111 pci_common_init(&iq80331_pci);
112 return 0;
113}
114
115subsys_initcall(iq80331_pci_init);
116
117
118
119
diff --git a/arch/arm/mach-iop3xx/iq80332-mm.c b/arch/arm/mach-iop3xx/iq80332-mm.c
deleted file mode 100644
index 2feaf7591f53..000000000000
--- a/arch/arm/mach-iop3xx/iq80332-mm.c
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * linux/arch/arm/mach-iop3xx/mm.c
3 *
4 * Low level memory initialization for iq80332 platform
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/mm.h>
17#include <linux/init.h>
18
19#include <asm/io.h>
20#include <asm/pgtable.h>
21#include <asm/page.h>
22
23#include <asm/mach/map.h>
24
25
26/*
27 * IQ80332 specific IO mappings
28 *
29 * We use RedBoot's setup for the onboard devices.
30 */
31
32void __init iq80332_map_io(void)
33{
34 iop331_map_io();
35}
diff --git a/arch/arm/mach-iop3xx/iq80332-pci.c b/arch/arm/mach-iop3xx/iq80332-pci.c
deleted file mode 100644
index afc0676318e4..000000000000
--- a/arch/arm/mach-iop3xx/iq80332-pci.c
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * arch/arm/mach-iop3xx/iq80332-pci.c
3 *
4 * PCI support for the Intel IQ80332 reference board
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/init.h>
16#include <linux/string.h>
17#include <linux/slab.h>
18
19#include <asm/hardware.h>
20#include <asm/irq.h>
21#include <asm/mach/pci.h>
22#include <asm/mach-types.h>
23
24/*
25 * The following macro is used to lookup irqs in a standard table
26 * format for those systems that do not already have PCI
27 * interrupts properly routed. We assume 1 <= pin <= 4
28 */
29#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
30({ int _ctl_ = -1; \
31 unsigned int _idsel = idsel - minid; \
32 if (_idsel <= maxid) \
33 _ctl_ = pci_irq_table[_idsel][pin-1]; \
34 _ctl_; })
35
36#define INTA IRQ_IQ80332_INTA
37#define INTB IRQ_IQ80332_INTB
38#define INTC IRQ_IQ80332_INTC
39#define INTD IRQ_IQ80332_INTD
40
41//#define INTE IRQ_IQ80332_I82544
42
43static inline int __init
44iq80332_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
45{
46 static int pci_irq_table[][8] = {
47 /*
48 * PCI IDSEL/INTPIN->INTLINE
49 * A B C D
50 */
51 {-1, -1, -1, -1},
52 {-1, -1, -1, -1},
53 {-1, -1, -1, -1},
54 {INTA, INTB, INTC, INTD}, /* PCI-X Slot */
55 {-1, -1, -1, -1},
56 {INTC, INTC, INTC, INTC}, /* GigE */
57 {-1, -1, -1, -1},
58 {-1, -1, -1, -1},
59 };
60
61 BUG_ON(pin < 1 || pin > 4);
62
63 return PCI_IRQ_TABLE_LOOKUP(1, 7);
64}
65
66static int iq80332_setup(int nr, struct pci_sys_data *sys)
67{
68 struct resource *res;
69
70 if(nr != 0)
71 return 0;
72
73 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
74 if (!res)
75 panic("PCI: unable to alloc resources");
76
77 res[0].start = IOP331_PCI_LOWER_IO_VA;
78 res[0].end = IOP331_PCI_UPPER_IO_VA;
79 res[0].name = "IQ80332 PCI I/O Space";
80 res[0].flags = IORESOURCE_IO;
81
82 res[1].start = IOP331_PCI_LOWER_MEM_PA;
83 res[1].end = IOP331_PCI_UPPER_MEM_PA;
84 res[1].name = "IQ80332 PCI Memory Space";
85 res[1].flags = IORESOURCE_MEM;
86
87 request_resource(&ioport_resource, &res[0]);
88 request_resource(&iomem_resource, &res[1]);
89
90 sys->mem_offset = IOP331_PCI_MEM_OFFSET;
91 sys->io_offset = IOP331_PCI_IO_OFFSET;
92
93 sys->resource[0] = &res[0];
94 sys->resource[1] = &res[1];
95 sys->resource[2] = NULL;
96
97 return 1;
98}
99
100static void iq80332_preinit(void)
101{
102 iop331_init();
103}
104
105static struct hw_pci iq80332_pci __initdata = {
106 .swizzle = pci_std_swizzle,
107 .nr_controllers = 1,
108 .setup = iq80332_setup,
109 .scan = iop331_scan_bus,
110 .preinit = iq80332_preinit,
111 .map_irq = iq80332_map_irq
112};
113
114static int __init iq80332_pci_init(void)
115{
116 if (machine_is_iq80332())
117 pci_common_init(&iq80332_pci);
118 return 0;
119}
120
121subsys_initcall(iq80332_pci_init);
122
123
124
125
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 7c25dbd5a181..35dd8b3824b0 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -26,6 +26,7 @@
26#include <linux/bitops.h> 26#include <linux/bitops.h>
27#include <linux/time.h> 27#include <linux/time.h>
28#include <linux/timex.h> 28#include <linux/timex.h>
29#include <linux/clocksource.h>
29 30
30#include <asm/hardware.h> 31#include <asm/hardware.h>
31#include <asm/uaccess.h> 32#include <asm/uaccess.h>
@@ -255,16 +256,6 @@ static unsigned volatile last_jiffy_time;
255 256
256#define CLOCK_TICKS_PER_USEC ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC) 257#define CLOCK_TICKS_PER_USEC ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
257 258
258/* IRQs are disabled before entering here from do_gettimeofday() */
259static unsigned long ixp4xx_gettimeoffset(void)
260{
261 u32 elapsed;
262
263 elapsed = *IXP4XX_OSTS - last_jiffy_time;
264
265 return elapsed / CLOCK_TICKS_PER_USEC;
266}
267
268static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) 259static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
269{ 260{
270 write_seqlock(&xtime_lock); 261 write_seqlock(&xtime_lock);
@@ -309,7 +300,6 @@ static void __init ixp4xx_timer_init(void)
309 300
310struct sys_timer ixp4xx_timer = { 301struct sys_timer ixp4xx_timer = {
311 .init = ixp4xx_timer_init, 302 .init = ixp4xx_timer_init,
312 .offset = ixp4xx_gettimeoffset,
313}; 303};
314 304
315static struct resource ixp46x_i2c_resources[] = { 305static struct resource ixp46x_i2c_resources[] = {
@@ -365,3 +355,29 @@ void __init ixp4xx_sys_init(void)
365 ixp4xx_exp_bus_size >> 20); 355 ixp4xx_exp_bus_size >> 20);
366} 356}
367 357
358cycle_t ixp4xx_get_cycles(void)
359{
360 return *IXP4XX_OSTS;
361}
362
363static struct clocksource clocksource_ixp4xx = {
364 .name = "OSTS",
365 .rating = 200,
366 .read = ixp4xx_get_cycles,
367 .mask = CLOCKSOURCE_MASK(32),
368 .shift = 20,
369 .is_continuous = 1,
370};
371
372unsigned long ixp4xx_timer_freq = FREQ;
373static int __init ixp4xx_clocksource_init(void)
374{
375 clocksource_ixp4xx.mult =
376 clocksource_hz2mult(ixp4xx_timer_freq,
377 clocksource_ixp4xx.shift);
378 clocksource_register(&clocksource_ixp4xx);
379
380 return 0;
381}
382
383device_initcall(ixp4xx_clocksource_init);
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index 749a337494d3..162c266e5f8f 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -159,6 +159,8 @@ static void nslu2_power_off(void)
159 159
160static void __init nslu2_init(void) 160static void __init nslu2_init(void)
161{ 161{
162 ixp4xx_timer_freq = NSLU2_FREQ;
163
162 ixp4xx_sys_init(); 164 ixp4xx_sys_init();
163 165
164 nslu2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); 166 nslu2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index f1958e882e86..638490e62d5f 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -20,6 +20,7 @@
20#include <linux/clk.h> 20#include <linux/clk.h>
21 21
22#include <asm/io.h> 22#include <asm/io.h>
23#include <asm/mach-types.h>
23 24
24#include <asm/arch/cpu.h> 25#include <asm/arch/cpu.h>
25#include <asm/arch/usb.h> 26#include <asm/arch/usb.h>
@@ -586,77 +587,53 @@ static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
586 *-------------------------------------------------------------------------*/ 587 *-------------------------------------------------------------------------*/
587 588
588#ifdef CONFIG_OMAP_RESET_CLOCKS 589#ifdef CONFIG_OMAP_RESET_CLOCKS
589/*
590 * Resets some clocks that may be left on from bootloader,
591 * but leaves serial clocks on. See also omap_late_clk_reset().
592 */
593static inline void omap1_early_clk_reset(void)
594{
595 //omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
596}
597 590
598static int __init omap1_late_clk_reset(void) 591static void __init omap1_clk_disable_unused(struct clk *clk)
599{ 592{
600 /* Turn off all unused clocks */
601 struct clk *p;
602 __u32 regval32; 593 __u32 regval32;
603 594
604 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ 595 /* Clocks in the DSP domain need api_ck. Just assume bootloader
605 regval32 = omap_readw(SOFT_REQ_REG) & (1 << 4); 596 * has not enabled any DSP clocks */
606 omap_writew(regval32, SOFT_REQ_REG); 597 if ((u32)clk->enable_reg == DSP_IDLECT2) {
607 omap_writew(0, SOFT_REQ_REG2); 598 printk(KERN_INFO "Skipping reset check for DSP domain "
608 599 "clock \"%s\"\n", clk->name);
609 list_for_each_entry(p, &clocks, node) { 600 return;
610 if (p->usecount > 0 || (p->flags & ALWAYS_ENABLED) || 601 }
611 p->enable_reg == 0)
612 continue;
613
614 /* Clocks in the DSP domain need api_ck. Just assume bootloader
615 * has not enabled any DSP clocks */
616 if ((u32)p->enable_reg == DSP_IDLECT2) {
617 printk(KERN_INFO "Skipping reset check for DSP domain "
618 "clock \"%s\"\n", p->name);
619 continue;
620 }
621 602
622 /* Is the clock already disabled? */ 603 /* Is the clock already disabled? */
623 if (p->flags & ENABLE_REG_32BIT) { 604 if (clk->flags & ENABLE_REG_32BIT) {
624 if (p->flags & VIRTUAL_IO_ADDRESS) 605 if (clk->flags & VIRTUAL_IO_ADDRESS)
625 regval32 = __raw_readl(p->enable_reg); 606 regval32 = __raw_readl(clk->enable_reg);
626 else
627 regval32 = omap_readl(p->enable_reg);
628 } else {
629 if (p->flags & VIRTUAL_IO_ADDRESS)
630 regval32 = __raw_readw(p->enable_reg);
631 else 607 else
632 regval32 = omap_readw(p->enable_reg); 608 regval32 = omap_readl(clk->enable_reg);
633 } 609 } else {
634 610 if (clk->flags & VIRTUAL_IO_ADDRESS)
635 if ((regval32 & (1 << p->enable_bit)) == 0) 611 regval32 = __raw_readw(clk->enable_reg);
636 continue; 612 else
613 regval32 = omap_readw(clk->enable_reg);
614 }
637 615
638 /* FIXME: This clock seems to be necessary but no-one 616 if ((regval32 & (1 << clk->enable_bit)) == 0)
639 * has asked for its activation. */ 617 return;
640 if (p == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera
641 || p == &ck_dpll1out.clk // FIX: SoSSI, SSR
642 || p == &arm_gpio_ck // FIX: GPIO code for 1510
643 ) {
644 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
645 p->name);
646 continue;
647 }
648 618
649 printk(KERN_INFO "Disabling unused clock \"%s\"... ", p->name); 619 /* FIXME: This clock seems to be necessary but no-one
650 p->disable(p); 620 * has asked for its activation. */
651 printk(" done\n"); 621 if (clk == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera
622 || clk == &ck_dpll1out.clk // FIX: SoSSI, SSR
623 || clk == &arm_gpio_ck // FIX: GPIO code for 1510
624 ) {
625 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
626 clk->name);
627 return;
652 } 628 }
653 629
654 return 0; 630 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
631 clk->disable(clk);
632 printk(" done\n");
655} 633}
656late_initcall(omap1_late_clk_reset);
657 634
658#else 635#else
659#define omap1_early_clk_reset() {} 636#define omap1_clk_disable_unused NULL
660#endif 637#endif
661 638
662static struct clk_functions omap1_clk_functions = { 639static struct clk_functions omap1_clk_functions = {
@@ -664,6 +641,7 @@ static struct clk_functions omap1_clk_functions = {
664 .clk_disable = omap1_clk_disable, 641 .clk_disable = omap1_clk_disable,
665 .clk_round_rate = omap1_clk_round_rate, 642 .clk_round_rate = omap1_clk_round_rate,
666 .clk_set_rate = omap1_clk_set_rate, 643 .clk_set_rate = omap1_clk_set_rate,
644 .clk_disable_unused = omap1_clk_disable_unused,
667}; 645};
668 646
669int __init omap1_clk_init(void) 647int __init omap1_clk_init(void)
@@ -671,8 +649,13 @@ int __init omap1_clk_init(void)
671 struct clk ** clkp; 649 struct clk ** clkp;
672 const struct omap_clock_config *info; 650 const struct omap_clock_config *info;
673 int crystal_type = 0; /* Default 12 MHz */ 651 int crystal_type = 0; /* Default 12 MHz */
652 u32 reg;
653
654 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
655 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
656 omap_writew(reg, SOFT_REQ_REG);
657 omap_writew(0, SOFT_REQ_REG2);
674 658
675 omap1_early_clk_reset();
676 clk_init(&omap1_clk_functions); 659 clk_init(&omap1_clk_functions);
677 660
678 /* By default all idlect1 clocks are allowed to idle */ 661 /* By default all idlect1 clocks are allowed to idle */
@@ -772,6 +755,12 @@ int __init omap1_clk_init(void)
772 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL); 755 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
773#endif 756#endif
774 757
758 /* Amstrad Delta wants BCLK high when inactive */
759 if (machine_is_ams_delta())
760 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
761 (1 << SDW_MCLK_INV_BIT),
762 ULPD_CLOCK_CTRL);
763
775 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ 764 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
776 /* (on 730, bit 13 must not be cleared) */ 765 /* (on 730, bit 13 must not be cleared) */
777 if (cpu_is_omap730()) 766 if (cpu_is_omap730())
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index b7c68819c4e7..f7df00205c4a 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -89,6 +89,7 @@ struct arm_idlect1_clk {
89#define EN_DSPTIMCK 5 89#define EN_DSPTIMCK 5
90 90
91/* Various register defines for clock controls scattered around OMAP chip */ 91/* Various register defines for clock controls scattered around OMAP chip */
92#define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */
92#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ 93#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
93#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ 94#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
94#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */ 95#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
@@ -741,6 +742,18 @@ static struct clk i2c_fck = {
741 .disable = &omap1_clk_disable_generic, 742 .disable = &omap1_clk_disable_generic,
742}; 743};
743 744
745static struct clk i2c_ick = {
746 .name = "i2c_ick",
747 .id = 1,
748 .flags = CLOCK_IN_OMAP16XX |
749 VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |
750 ALWAYS_ENABLED,
751 .parent = &armper_ck.clk,
752 .recalc = &followparent_recalc,
753 .enable = &omap1_clk_enable_generic,
754 .disable = &omap1_clk_disable_generic,
755};
756
744static struct clk * onchip_clks[] = { 757static struct clk * onchip_clks[] = {
745 /* non-ULPD clocks */ 758 /* non-ULPD clocks */
746 &ck_ref, 759 &ck_ref,
@@ -790,6 +803,7 @@ static struct clk * onchip_clks[] = {
790 /* Virtual clocks */ 803 /* Virtual clocks */
791 &virtual_ck_mpu, 804 &virtual_ck_mpu,
792 &i2c_fck, 805 &i2c_fck,
806 &i2c_ick,
793}; 807};
794 808
795#endif 809#endif
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index fa74ef7af15f..5432335bc493 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -199,6 +199,17 @@ MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
199MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1) 199MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
200MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1) 200MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
201 201
202/* OMAP-1610 SPI */
203MUX_CFG("U19_1610_SPIF_SCK", 7, 21, 6, 1, 15, 0, 1, 1, 1)
204MUX_CFG("U18_1610_SPIF_DIN", 8, 0, 6, 1, 18, 1, 1, 0, 1)
205MUX_CFG("P20_1610_SPIF_DIN", 6, 27, 4, 1, 7, 1, 1, 0, 1)
206MUX_CFG("W21_1610_SPIF_DOUT", 8, 3, 6, 1, 19, 0, 1, 0, 1)
207MUX_CFG("R18_1610_SPIF_DOUT", 7, 9, 3, 1, 11, 0, 1, 0, 1)
208MUX_CFG("N14_1610_SPIF_CS0", 8, 9, 6, 1, 21, 0, 1, 1, 1)
209MUX_CFG("N15_1610_SPIF_CS1", 7, 18, 6, 1, 14, 0, 1, 1, 1)
210MUX_CFG("T19_1610_SPIF_CS2", 7, 15, 4, 1, 13, 0, 1, 1, 1)
211MUX_CFG("P15_1610_SPIF_CS3", 8, 12, 3, 1, 22, 0, 1, 1, 1)
212
202/* OMAP-1610 Flash */ 213/* OMAP-1610 Flash */
203MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1) 214MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
204MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1) 215MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 7993b7bae2bd..2db6b732b084 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -166,8 +166,8 @@ static struct omap_uart_config apollon_uart_config __initdata = {
166 166
167static struct omap_mmc_config apollon_mmc_config __initdata = { 167static struct omap_mmc_config apollon_mmc_config __initdata = {
168 .mmc [0] = { 168 .mmc [0] = {
169 .enabled = 0, 169 .enabled = 1,
170 .wire4 = 0, 170 .wire4 = 1,
171 .wp_pin = -1, 171 .wp_pin = -1,
172 .power_pin = -1, 172 .power_pin = -1,
173 .switch_pin = -1, 173 .switch_pin = -1,
@@ -257,6 +257,9 @@ static void __init omap_apollon_init(void)
257 /* REVISIT: where's the correct place */ 257 /* REVISIT: where's the correct place */
258 omap_cfg_reg(W19_24XX_SYS_NIRQ); 258 omap_cfg_reg(W19_24XX_SYS_NIRQ);
259 259
260 /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */
261 CONTROL_DEVCONF |= (1 << 24);
262
260 /* 263 /*
261 * Make sure the serial ports are muxed on at this point. 264 * Make sure the serial ports are muxed on at this point.
262 * You have to mux them off in device drivers later on 265 * You have to mux them off in device drivers later on
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index d1b648a4efbf..0de201c3d50b 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -32,10 +32,14 @@
32#include "memory.h" 32#include "memory.h"
33#include "clock.h" 33#include "clock.h"
34 34
35#undef DEBUG
36
35//#define DOWN_VARIABLE_DPLL 1 /* Experimental */ 37//#define DOWN_VARIABLE_DPLL 1 /* Experimental */
36 38
37static struct prcm_config *curr_prcm_set; 39static struct prcm_config *curr_prcm_set;
38static u32 curr_perf_level = PRCM_FULL_SPEED; 40static u32 curr_perf_level = PRCM_FULL_SPEED;
41static struct clk *vclk;
42static struct clk *sclk;
39 43
40/*------------------------------------------------------------------------- 44/*-------------------------------------------------------------------------
41 * Omap2 specific clock functions 45 * Omap2 specific clock functions
@@ -79,6 +83,14 @@ static void omap2_propagate_rate(struct clk * clk)
79 propagate_rate(clk); 83 propagate_rate(clk);
80} 84}
81 85
86static void omap2_set_osc_ck(int enable)
87{
88 if (enable)
89 PRCM_CLKSRC_CTRL &= ~(0x3 << 3);
90 else
91 PRCM_CLKSRC_CTRL |= 0x3 << 3;
92}
93
82/* Enable an APLL if off */ 94/* Enable an APLL if off */
83static void omap2_clk_fixed_enable(struct clk *clk) 95static void omap2_clk_fixed_enable(struct clk *clk)
84{ 96{
@@ -101,12 +113,54 @@ static void omap2_clk_fixed_enable(struct clk *clk)
101 else if (clk == &apll54_ck) 113 else if (clk == &apll54_ck)
102 cval = (1 << 6); 114 cval = (1 << 6);
103 115
104 while (!CM_IDLEST_CKGEN & cval) { /* Wait for lock */ 116 while (!(CM_IDLEST_CKGEN & cval)) { /* Wait for lock */
105 ++i; 117 ++i;
106 udelay(1); 118 udelay(1);
107 if (i == 100000) 119 if (i == 100000) {
120 printk(KERN_ERR "Clock %s didn't lock\n", clk->name);
121 break;
122 }
123 }
124}
125
126static void omap2_clk_wait_ready(struct clk *clk)
127{
128 unsigned long reg, other_reg, st_reg;
129 u32 bit;
130 int i;
131
132 reg = (unsigned long) clk->enable_reg;
133 if (reg == (unsigned long) &CM_FCLKEN1_CORE ||
134 reg == (unsigned long) &CM_FCLKEN2_CORE)
135 other_reg = (reg & ~0xf0) | 0x10;
136 else if (reg == (unsigned long) &CM_ICLKEN1_CORE ||
137 reg == (unsigned long) &CM_ICLKEN2_CORE)
138 other_reg = (reg & ~0xf0) | 0x00;
139 else
140 return;
141
142 /* No check for DSS or cam clocks */
143 if ((reg & 0x0f) == 0) {
144 if (clk->enable_bit <= 1 || clk->enable_bit == 31)
145 return;
146 }
147
148 /* Check if both functional and interface clocks
149 * are running. */
150 bit = 1 << clk->enable_bit;
151 if (!(__raw_readl(other_reg) & bit))
152 return;
153 st_reg = (other_reg & ~0xf0) | 0x20;
154 i = 0;
155 while (!(__raw_readl(st_reg) & bit)) {
156 i++;
157 if (i == 100000) {
158 printk(KERN_ERR "Timeout enabling clock %s\n", clk->name);
108 break; 159 break;
160 }
109 } 161 }
162 if (i)
163 pr_debug("Clock %s stable after %d loops\n", clk->name, i);
110} 164}
111 165
112/* Enables clock without considering parent dependencies or use count 166/* Enables clock without considering parent dependencies or use count
@@ -119,6 +173,11 @@ static int _omap2_clk_enable(struct clk * clk)
119 if (clk->flags & ALWAYS_ENABLED) 173 if (clk->flags & ALWAYS_ENABLED)
120 return 0; 174 return 0;
121 175
176 if (unlikely(clk == &osc_ck)) {
177 omap2_set_osc_ck(1);
178 return 0;
179 }
180
122 if (unlikely(clk->enable_reg == 0)) { 181 if (unlikely(clk->enable_reg == 0)) {
123 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 182 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
124 clk->name); 183 clk->name);
@@ -133,6 +192,9 @@ static int _omap2_clk_enable(struct clk * clk)
133 regval32 = __raw_readl(clk->enable_reg); 192 regval32 = __raw_readl(clk->enable_reg);
134 regval32 |= (1 << clk->enable_bit); 193 regval32 |= (1 << clk->enable_bit);
135 __raw_writel(regval32, clk->enable_reg); 194 __raw_writel(regval32, clk->enable_reg);
195 wmb();
196
197 omap2_clk_wait_ready(clk);
136 198
137 return 0; 199 return 0;
138} 200}
@@ -155,6 +217,11 @@ static void _omap2_clk_disable(struct clk *clk)
155{ 217{
156 u32 regval32; 218 u32 regval32;
157 219
220 if (unlikely(clk == &osc_ck)) {
221 omap2_set_osc_ck(0);
222 return;
223 }
224
158 if (clk->enable_reg == 0) 225 if (clk->enable_reg == 0)
159 return; 226 return;
160 227
@@ -166,6 +233,7 @@ static void _omap2_clk_disable(struct clk *clk)
166 regval32 = __raw_readl(clk->enable_reg); 233 regval32 = __raw_readl(clk->enable_reg);
167 regval32 &= ~(1 << clk->enable_bit); 234 regval32 &= ~(1 << clk->enable_bit);
168 __raw_writel(regval32, clk->enable_reg); 235 __raw_writel(regval32, clk->enable_reg);
236 wmb();
169} 237}
170 238
171static int omap2_clk_enable(struct clk *clk) 239static int omap2_clk_enable(struct clk *clk)
@@ -695,12 +763,14 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
695 reg_val = __raw_readl(reg); 763 reg_val = __raw_readl(reg);
696 reg_val &= ~(field_mask << div_off); 764 reg_val &= ~(field_mask << div_off);
697 reg_val |= (field_val << div_off); 765 reg_val |= (field_val << div_off);
698
699 __raw_writel(reg_val, reg); 766 __raw_writel(reg_val, reg);
767 wmb();
700 clk->rate = clk->parent->rate / field_val; 768 clk->rate = clk->parent->rate / field_val;
701 769
702 if (clk->flags & DELAYED_APP) 770 if (clk->flags & DELAYED_APP) {
703 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); 771 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
772 wmb();
773 }
704 ret = 0; 774 ret = 0;
705 } else if (clk->set_rate != 0) 775 } else if (clk->set_rate != 0)
706 ret = clk->set_rate(clk, rate); 776 ret = clk->set_rate(clk, rate);
@@ -836,10 +906,12 @@ static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
836 reg_val = __raw_readl(reg) & ~(field_mask << src_off); 906 reg_val = __raw_readl(reg) & ~(field_mask << src_off);
837 reg_val |= (field_val << src_off); 907 reg_val |= (field_val << src_off);
838 __raw_writel(reg_val, reg); 908 __raw_writel(reg_val, reg);
909 wmb();
839 910
840 if (clk->flags & DELAYED_APP) 911 if (clk->flags & DELAYED_APP) {
841 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); 912 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
842 913 wmb();
914 }
843 if (clk->usecount > 0) 915 if (clk->usecount > 0)
844 _omap2_clk_enable(clk); 916 _omap2_clk_enable(clk);
845 917
@@ -953,12 +1025,29 @@ static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
953 * Omap2 clock reset and init functions 1025 * Omap2 clock reset and init functions
954 *-------------------------------------------------------------------------*/ 1026 *-------------------------------------------------------------------------*/
955 1027
1028#ifdef CONFIG_OMAP_RESET_CLOCKS
1029static void __init omap2_clk_disable_unused(struct clk *clk)
1030{
1031 u32 regval32;
1032
1033 regval32 = __raw_readl(clk->enable_reg);
1034 if ((regval32 & (1 << clk->enable_bit)) == 0)
1035 return;
1036
1037 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1038 _omap2_clk_disable(clk);
1039}
1040#else
1041#define omap2_clk_disable_unused NULL
1042#endif
1043
956static struct clk_functions omap2_clk_functions = { 1044static struct clk_functions omap2_clk_functions = {
957 .clk_enable = omap2_clk_enable, 1045 .clk_enable = omap2_clk_enable,
958 .clk_disable = omap2_clk_disable, 1046 .clk_disable = omap2_clk_disable,
959 .clk_round_rate = omap2_clk_round_rate, 1047 .clk_round_rate = omap2_clk_round_rate,
960 .clk_set_rate = omap2_clk_set_rate, 1048 .clk_set_rate = omap2_clk_set_rate,
961 .clk_set_parent = omap2_clk_set_parent, 1049 .clk_set_parent = omap2_clk_set_parent,
1050 .clk_disable_unused = omap2_clk_disable_unused,
962}; 1051};
963 1052
964static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys) 1053static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
@@ -984,27 +1073,19 @@ static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
984 sys->rate = sclk; 1073 sys->rate = sclk;
985} 1074}
986 1075
987#ifdef CONFIG_OMAP_RESET_CLOCKS 1076/*
988static void __init omap2_disable_unused_clocks(void) 1077 * Set clocks for bypass mode for reboot to work.
1078 */
1079void omap2_clk_prepare_for_reboot(void)
989{ 1080{
990 struct clk *ck; 1081 u32 rate;
991 u32 regval32;
992 1082
993 list_for_each_entry(ck, &clocks, node) { 1083 if (vclk == NULL || sclk == NULL)
994 if (ck->usecount > 0 || (ck->flags & ALWAYS_ENABLED) || 1084 return;
995 ck->enable_reg == 0)
996 continue;
997
998 regval32 = __raw_readl(ck->enable_reg);
999 if ((regval32 & (1 << ck->enable_bit)) == 0)
1000 continue;
1001 1085
1002 printk(KERN_INFO "Disabling unused clock \"%s\"\n", ck->name); 1086 rate = clk_get_rate(sclk);
1003 _omap2_clk_disable(ck); 1087 clk_set_rate(vclk, rate);
1004 }
1005} 1088}
1006late_initcall(omap2_disable_unused_clocks);
1007#endif
1008 1089
1009/* 1090/*
1010 * Switch the MPU rate if specified on cmdline. 1091 * Switch the MPU rate if specified on cmdline.
@@ -1077,8 +1158,27 @@ int __init omap2_clk_init(void)
1077 */ 1158 */
1078 clk_enable(&sync_32k_ick); 1159 clk_enable(&sync_32k_ick);
1079 clk_enable(&omapctrl_ick); 1160 clk_enable(&omapctrl_ick);
1161
1162 /* Force the APLLs active during bootup to avoid disabling and
1163 * enabling them unnecessarily. */
1164 clk_enable(&apll96_ck);
1165 clk_enable(&apll54_ck);
1166
1080 if (cpu_is_omap2430()) 1167 if (cpu_is_omap2430())
1081 clk_enable(&sdrc_ick); 1168 clk_enable(&sdrc_ick);
1082 1169
1170 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1171 vclk = clk_get(NULL, "virt_prcm_set");
1172 sclk = clk_get(NULL, "sys_ck");
1173
1174 return 0;
1175}
1176
1177static int __init omap2_disable_aplls(void)
1178{
1179 clk_disable(&apll96_ck);
1180 clk_disable(&apll54_ck);
1181
1083 return 0; 1182 return 0;
1084} 1183}
1184late_initcall(omap2_disable_aplls);
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2781dfbc5164..8816f5a33a28 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -560,7 +560,7 @@ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
560 .name = "osc_ck", 560 .name = "osc_ck",
561 .rate = 26000000, /* fixed up in clock init */ 561 .rate = 26000000, /* fixed up in clock init */
562 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 562 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
563 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, 563 RATE_FIXED | RATE_PROPAGATES,
564}; 564};
565 565
566/* With out modem likely 12MHz, with modem likely 13MHz */ 566/* With out modem likely 12MHz, with modem likely 13MHz */
@@ -1368,7 +1368,8 @@ static struct clk mcbsp5_fck = {
1368}; 1368};
1369 1369
1370static struct clk mcspi1_ick = { 1370static struct clk mcspi1_ick = {
1371 .name = "mcspi1_ick", 1371 .name = "mcspi_ick",
1372 .id = 1,
1372 .parent = &l4_ck, 1373 .parent = &l4_ck,
1373 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1374 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1374 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1375 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
@@ -1377,7 +1378,8 @@ static struct clk mcspi1_ick = {
1377}; 1378};
1378 1379
1379static struct clk mcspi1_fck = { 1380static struct clk mcspi1_fck = {
1380 .name = "mcspi1_fck", 1381 .name = "mcspi_fck",
1382 .id = 1,
1381 .parent = &func_48m_ck, 1383 .parent = &func_48m_ck,
1382 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1384 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1383 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1385 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
@@ -1386,7 +1388,8 @@ static struct clk mcspi1_fck = {
1386}; 1388};
1387 1389
1388static struct clk mcspi2_ick = { 1390static struct clk mcspi2_ick = {
1389 .name = "mcspi2_ick", 1391 .name = "mcspi_ick",
1392 .id = 2,
1390 .parent = &l4_ck, 1393 .parent = &l4_ck,
1391 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1394 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1392 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1395 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
@@ -1395,7 +1398,8 @@ static struct clk mcspi2_ick = {
1395}; 1398};
1396 1399
1397static struct clk mcspi2_fck = { 1400static struct clk mcspi2_fck = {
1398 .name = "mcspi2_fck", 1401 .name = "mcspi_fck",
1402 .id = 2,
1399 .parent = &func_48m_ck, 1403 .parent = &func_48m_ck,
1400 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1404 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1401 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1405 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
@@ -1404,7 +1408,8 @@ static struct clk mcspi2_fck = {
1404}; 1408};
1405 1409
1406static struct clk mcspi3_ick = { 1410static struct clk mcspi3_ick = {
1407 .name = "mcspi3_ick", 1411 .name = "mcspi_ick",
1412 .id = 3,
1408 .parent = &l4_ck, 1413 .parent = &l4_ck,
1409 .flags = CLOCK_IN_OMAP243X, 1414 .flags = CLOCK_IN_OMAP243X,
1410 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, 1415 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
@@ -1413,7 +1418,8 @@ static struct clk mcspi3_ick = {
1413}; 1418};
1414 1419
1415static struct clk mcspi3_fck = { 1420static struct clk mcspi3_fck = {
1416 .name = "mcspi3_fck", 1421 .name = "mcspi_fck",
1422 .id = 3,
1417 .parent = &func_48m_ck, 1423 .parent = &func_48m_ck,
1418 .flags = CLOCK_IN_OMAP243X, 1424 .flags = CLOCK_IN_OMAP243X,
1419 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, 1425 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index c7a48f921fef..f4f04d87df32 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -13,6 +13,8 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/clk.h> 15#include <linux/clk.h>
16#include <linux/ioport.h>
17#include <linux/spinlock.h>
16 18
17#include <asm/io.h> 19#include <asm/io.h>
18#include <asm/arch/gpmc.h> 20#include <asm/arch/gpmc.h>
@@ -41,6 +43,19 @@
41#define GPMC_CS0 0x60 43#define GPMC_CS0 0x60
42#define GPMC_CS_SIZE 0x30 44#define GPMC_CS_SIZE 0x30
43 45
46#define GPMC_CS_NUM 8
47#define GPMC_MEM_START 0x00000000
48#define GPMC_MEM_END 0x3FFFFFFF
49#define BOOT_ROM_SPACE 0x100000 /* 1MB */
50
51#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
52#define GPMC_SECTION_SHIFT 28 /* 128 MB */
53
54static struct resource gpmc_mem_root;
55static struct resource gpmc_cs_mem[GPMC_CS_NUM];
56static spinlock_t gpmc_mem_lock = SPIN_LOCK_UNLOCKED;
57static unsigned gpmc_cs_map;
58
44static void __iomem *gpmc_base = 59static void __iomem *gpmc_base =
45 (void __iomem *) IO_ADDRESS(GPMC_BASE); 60 (void __iomem *) IO_ADDRESS(GPMC_BASE);
46static void __iomem *gpmc_cs_base = 61static void __iomem *gpmc_cs_base =
@@ -187,9 +202,168 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
187 return 0; 202 return 0;
188} 203}
189 204
190unsigned long gpmc_cs_get_base_addr(int cs) 205static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
206{
207 u32 l;
208 u32 mask;
209
210 mask = (1 << GPMC_SECTION_SHIFT) - size;
211 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
212 l &= ~0x3f;
213 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
214 l &= ~(0x0f << 8);
215 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
216 l |= 1 << 6; /* CSVALID */
217 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
218}
219
220static void gpmc_cs_disable_mem(int cs)
221{
222 u32 l;
223
224 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
225 l &= ~(1 << 6); /* CSVALID */
226 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
227}
228
229static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
230{
231 u32 l;
232 u32 mask;
233
234 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
235 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
236 mask = (l >> 8) & 0x0f;
237 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
238}
239
240static int gpmc_cs_mem_enabled(int cs)
241{
242 u32 l;
243
244 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
245 return l & (1 << 6);
246}
247
248static void gpmc_cs_set_reserved(int cs, int reserved)
191{ 249{
192 return (gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7) & 0x1f) << 24; 250 gpmc_cs_map &= ~(1 << cs);
251 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
252}
253
254static int gpmc_cs_reserved(int cs)
255{
256 return gpmc_cs_map & (1 << cs);
257}
258
259static unsigned long gpmc_mem_align(unsigned long size)
260{
261 int order;
262
263 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
264 order = GPMC_CHUNK_SHIFT - 1;
265 do {
266 size >>= 1;
267 order++;
268 } while (size);
269 size = 1 << order;
270 return size;
271}
272
273static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
274{
275 struct resource *res = &gpmc_cs_mem[cs];
276 int r;
277
278 size = gpmc_mem_align(size);
279 spin_lock(&gpmc_mem_lock);
280 res->start = base;
281 res->end = base + size - 1;
282 r = request_resource(&gpmc_mem_root, res);
283 spin_unlock(&gpmc_mem_lock);
284
285 return r;
286}
287
288int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
289{
290 struct resource *res = &gpmc_cs_mem[cs];
291 int r = -1;
292
293 if (cs > GPMC_CS_NUM)
294 return -ENODEV;
295
296 size = gpmc_mem_align(size);
297 if (size > (1 << GPMC_SECTION_SHIFT))
298 return -ENOMEM;
299
300 spin_lock(&gpmc_mem_lock);
301 if (gpmc_cs_reserved(cs)) {
302 r = -EBUSY;
303 goto out;
304 }
305 if (gpmc_cs_mem_enabled(cs))
306 r = adjust_resource(res, res->start & ~(size - 1), size);
307 if (r < 0)
308 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
309 size, NULL, NULL);
310 if (r < 0)
311 goto out;
312
313 gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
314 *base = res->start;
315 gpmc_cs_set_reserved(cs, 1);
316out:
317 spin_unlock(&gpmc_mem_lock);
318 return r;
319}
320
321void gpmc_cs_free(int cs)
322{
323 spin_lock(&gpmc_mem_lock);
324 if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
325 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
326 BUG();
327 spin_unlock(&gpmc_mem_lock);
328 return;
329 }
330 gpmc_cs_disable_mem(cs);
331 release_resource(&gpmc_cs_mem[cs]);
332 gpmc_cs_set_reserved(cs, 0);
333 spin_unlock(&gpmc_mem_lock);
334}
335
336void __init gpmc_mem_init(void)
337{
338 int cs;
339 unsigned long boot_rom_space = 0;
340
341 if (cpu_is_omap242x()) {
342 u32 l;
343 l = omap_readl(OMAP242X_CONTROL_STATUS);
344 /* In case of internal boot the 1st MB is redirected to the
345 * boot ROM memory space.
346 */
347 if (l & (1 << 3))
348 boot_rom_space = BOOT_ROM_SPACE;
349 } else
350 /* We assume internal boot if the mode can't be
351 * determined.
352 */
353 boot_rom_space = BOOT_ROM_SPACE;
354 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
355 gpmc_mem_root.end = GPMC_MEM_END;
356
357 /* Reserve all regions that has been set up by bootloader */
358 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
359 u32 base, size;
360
361 if (!gpmc_cs_mem_enabled(cs))
362 continue;
363 gpmc_cs_get_memconf(cs, &base, &size);
364 if (gpmc_cs_insert_mem(cs, base, size) < 0)
365 BUG();
366 }
193} 367}
194 368
195void __init gpmc_init(void) 369void __init gpmc_init(void)
@@ -206,4 +380,6 @@ void __init gpmc_init(void)
206 l &= 0x03 << 3; 380 l &= 0x03 << 3;
207 l |= (0x02 << 3) | (1 << 0); 381 l |= (0x02 << 3) | (1 << 0);
208 gpmc_write_reg(GPMC_SYSCONFIG, l); 382 gpmc_write_reg(GPMC_SYSCONFIG, l);
383
384 gpmc_mem_init();
209} 385}
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index dfc3b35cc1ff..1ed2fff4691a 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -41,18 +41,6 @@ static struct omap_irq_bank {
41 .nr_irqs = 96, 41 .nr_irqs = 96,
42 }, { 42 }, {
43 /* XXX: DSP INTC */ 43 /* XXX: DSP INTC */
44
45#if 0
46 /*
47 * Commented out for now until we fix the IVA clocking
48 */
49#ifdef CONFIG_ARCH_OMAP2420
50 }, {
51 /* IVA INTC (2420 only) */
52 .base_reg = OMAP24XX_IVA_INTC_BASE,
53 .nr_irqs = 16, /* Actually 32, but only 16 are used */
54#endif
55#endif
56 } 44 }
57}; 45};
58 46
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 60ef084faffd..f538d0fdb13c 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -104,6 +104,20 @@ MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1)
104MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1) 104MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1)
105MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1) 105MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1)
106 106
107/* MMC/SDIO */
108MUX_CFG_24XX("G19_24XX_MMC_CLKO", 0x0f3, 0, 0, 0, 1)
109MUX_CFG_24XX("H18_24XX_MMC_CMD", 0x0f4, 0, 0, 0, 1)
110MUX_CFG_24XX("F20_24XX_MMC_DAT0", 0x0f5, 0, 0, 0, 1)
111MUX_CFG_24XX("H14_24XX_MMC_DAT1", 0x0f6, 0, 0, 0, 1)
112MUX_CFG_24XX("E19_24XX_MMC_DAT2", 0x0f7, 0, 0, 0, 1)
113MUX_CFG_24XX("D19_24XX_MMC_DAT3", 0x0f8, 0, 0, 0, 1)
114MUX_CFG_24XX("F19_24XX_MMC_DAT_DIR0", 0x0f9, 0, 0, 0, 1)
115MUX_CFG_24XX("E20_24XX_MMC_DAT_DIR1", 0x0fa, 0, 0, 0, 1)
116MUX_CFG_24XX("F18_24XX_MMC_DAT_DIR2", 0x0fb, 0, 0, 0, 1)
117MUX_CFG_24XX("E18_24XX_MMC_DAT_DIR3", 0x0fc, 0, 0, 0, 1)
118MUX_CFG_24XX("G18_24XX_MMC_CMD_DIR", 0x0fd, 0, 0, 0, 1)
119MUX_CFG_24XX("H15_24XX_MMC_CLKI", 0x0fe, 0, 0, 0, 1)
120
107/* Keypad GPIO*/ 121/* Keypad GPIO*/
108MUX_CFG_24XX("T19_24XX_KBR0", 0x106, 3, 1, 1, 1) 122MUX_CFG_24XX("T19_24XX_KBR0", 0x106, 3, 1, 1, 1)
109MUX_CFG_24XX("R19_24XX_KBR1", 0x107, 3, 1, 1, 1) 123MUX_CFG_24XX("R19_24XX_KBR1", 0x107, 3, 1, 1, 1)
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index c2bf57ef6825..90f530540c65 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -19,6 +19,8 @@
19 19
20#include "prcm-regs.h" 20#include "prcm-regs.h"
21 21
22extern void omap2_clk_prepare_for_reboot(void);
23
22u32 omap_prcm_get_reset_sources(void) 24u32 omap_prcm_get_reset_sources(void)
23{ 25{
24 return RM_RSTST_WKUP & 0x7f; 26 return RM_RSTST_WKUP & 0x7f;
@@ -28,12 +30,6 @@ EXPORT_SYMBOL(omap_prcm_get_reset_sources);
28/* Resets clock rates and reboots the system. Only called from system.h */ 30/* Resets clock rates and reboots the system. Only called from system.h */
29void omap_prcm_arch_reset(char mode) 31void omap_prcm_arch_reset(char mode)
30{ 32{
31 u32 rate; 33 omap2_clk_prepare_for_reboot();
32 struct clk *vclk, *sclk;
33
34 vclk = clk_get(NULL, "virt_prcm_set");
35 sclk = clk_get(NULL, "sys_ck");
36 rate = clk_get_rate(sclk);
37 clk_set_rate(vclk, rate); /* go to bypass for OMAP limitation */
38 RM_RSTCTRL_WKUP |= 2; 34 RM_RSTCTRL_WKUP |= 2;
39} 35}
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index bbd138be6a70..df37594c30f8 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -2,6 +2,13 @@ if ARCH_S3C2410
2 2
3menu "S3C24XX Implementations" 3menu "S3C24XX Implementations"
4 4
5config MACH_AML_M5900
6 bool "AML M5900 Series"
7 select CPU_S3C2410
8 help
9 Say Y here if you are using the American Microsystems M5900 Series
10 <http://www.amltd.com>
11
5config MACH_ANUBIS 12config MACH_ANUBIS
6 bool "Simtec Electronics ANUBIS" 13 bool "Simtec Electronics ANUBIS"
7 select CPU_S3C2440 14 select CPU_S3C2440
@@ -126,6 +133,12 @@ config MACH_NEXCODER_2440
126 help 133 help
127 Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board 134 Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
128 135
136config MACH_VSTMS
137 bool "VMSTMS"
138 select CPU_S3C2412
139 help
140 Say Y here if you are using an VSTMS board
141
129endmenu 142endmenu
130 143
131config S3C2410_CLOCK 144config S3C2410_CLOCK
@@ -133,10 +146,24 @@ config S3C2410_CLOCK
133 help 146 help
134 Clock code for the S3C2410, and similar processors 147 Clock code for the S3C2410, and similar processors
135 148
149config S3C2410_PM
150 bool
151 depends on CONFIG_PM
152 help
153 Power Management code common to S3C2410 and better
154
155config CPU_S3C2410_DMA
156 bool
157 depends on S3C2410_DMA && (CPU_S3C2410 || CPU_S3C2442)
158 default y if CPU_S3C2410 || CPU_S3C2442
159 help
160 DMA device selection for S3C2410 and compatible CPUs
161
136config CPU_S3C2410 162config CPU_S3C2410
137 bool 163 bool
138 depends on ARCH_S3C2410 164 depends on ARCH_S3C2410
139 select S3C2410_CLOCK 165 select S3C2410_CLOCK
166 select S3C2410_PM
140 help 167 help
141 Support for S3C2410 and S3C2410A family from the S3C24XX line 168 Support for S3C2410 and S3C2410A family from the S3C24XX line
142 of Samsung Mobile CPUs. 169 of Samsung Mobile CPUs.
@@ -149,6 +176,13 @@ config CPU_S3C2412_ONLY
149 !CPU_S3C2440 && !CPU_S3C2442 && CPU_S3C2412 176 !CPU_S3C2440 && !CPU_S3C2442 && CPU_S3C2412
150 default y if CPU_S3C2412 177 default y if CPU_S3C2412
151 178
179config S3C2412_PM
180 bool
181 default y if PM
182 depends on CPU_S3C2412
183 help
184 Internal config node to apply S3C2412 power management
185
152config CPU_S3C2412 186config CPU_S3C2412
153 bool 187 bool
154 depends on ARCH_S3C2410 188 depends on ARCH_S3C2410
@@ -165,6 +199,7 @@ config CPU_S3C2440
165 bool 199 bool
166 depends on ARCH_S3C2410 200 depends on ARCH_S3C2410
167 select S3C2410_CLOCK 201 select S3C2410_CLOCK
202 select S3C2410_PM
168 select CPU_S3C244X 203 select CPU_S3C244X
169 help 204 help
170 Support for S3C2440 Samsung Mobile CPU based systems. 205 Support for S3C2440 Samsung Mobile CPU based systems.
@@ -173,6 +208,7 @@ config CPU_S3C2442
173 bool 208 bool
174 depends on ARCH_S3C2420 209 depends on ARCH_S3C2420
175 select S3C2410_CLOCK 210 select S3C2410_CLOCK
211 select S3C2410_PM
176 select CPU_S3C244X 212 select CPU_S3C244X
177 help 213 help
178 Support for S3C2442 Samsung Mobile CPU based systems. 214 Support for S3C2442 Samsung Mobile CPU based systems.
@@ -256,7 +292,7 @@ config S3C2410_PM_CHECK_CHUNKSIZE
256 292
257config PM_SIMTEC 293config PM_SIMTEC
258 bool 294 bool
259 depends on PM && (ARCH_BAST || MACH_VR1000) 295 depends on PM && (ARCH_BAST || MACH_VR1000 || MACH_AML_M5900)
260 default y 296 default y
261 297
262config S3C2410_LOWLEVEL_UART_PORT 298config S3C2410_LOWLEVEL_UART_PORT
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 0eadec916214..d66013365b6b 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -9,6 +9,8 @@ obj-y := cpu.o irq.o time.o gpio.o clock.o devs.o
9obj-m := 9obj-m :=
10obj-n := 10obj-n :=
11obj- := 11obj- :=
12obj-dma-y :=
13obj-dma-n :=
12 14
13# DMA 15# DMA
14obj-$(CONFIG_S3C2410_DMA) += dma.o 16obj-$(CONFIG_S3C2410_DMA) += dma.o
@@ -20,6 +22,10 @@ obj-$(CONFIG_CPU_S3C2400) += s3c2400-gpio.o
20 22
21obj-$(CONFIG_CPU_S3C2410) += s3c2410.o 23obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
22obj-$(CONFIG_CPU_S3C2410) += s3c2410-gpio.o 24obj-$(CONFIG_CPU_S3C2410) += s3c2410-gpio.o
25obj-$(CONFIG_CPU_S3C2410) += s3c2410-irq.o
26
27obj-$(CONFIG_S3C2410_PM) += s3c2410-pm.o s3c2410-sleep.o
28obj-$(CONFIG_CPU_S3C2410_DMA) += s3c2410-dma.o
23 29
24# Power Management support 30# Power Management support
25 31
@@ -30,6 +36,9 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
30obj-$(CONFIG_CPU_S3C2412) += s3c2412.o 36obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
31obj-$(CONFIG_CPU_S3C2412) += s3c2412-irq.o 37obj-$(CONFIG_CPU_S3C2412) += s3c2412-irq.o
32obj-$(CONFIG_CPU_S3C2412) += s3c2412-clock.o 38obj-$(CONFIG_CPU_S3C2412) += s3c2412-clock.o
39obj-dma-$(CONFIG_CPU_S3C2412) += s3c2412-dma.o
40
41obj-$(CONFIG_S3C2412_PM) += s3c2412-pm.o
33 42
34# 43#
35# S3C244X support 44# S3C244X support
@@ -47,6 +56,7 @@ obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o
47obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o 56obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o
48obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o 57obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o
49obj-$(CONFIG_CPU_S3C2440) += s3c2410-gpio.o 58obj-$(CONFIG_CPU_S3C2440) += s3c2410-gpio.o
59obj-dma-$(CONFIG_CPU_S3C2440) += s3c2440-dma.o
50 60
51# S3C2442 support 61# S3C2442 support
52 62
@@ -57,8 +67,13 @@ obj-$(CONFIG_CPU_S3C2442) += s3c2442-clock.o
57 67
58obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o 68obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o
59 69
70# merge in dma objects
71
72obj-y += $(obj-dma-y)
73
60# machine specific support 74# machine specific support
61 75
76obj-$(CONFIG_MACH_AML_M5900) += mach-amlm5900.o
62obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o 77obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o
63obj-$(CONFIG_MACH_OSIRIS) += mach-osiris.o 78obj-$(CONFIG_MACH_OSIRIS) += mach-osiris.o
64obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o 79obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o
@@ -71,5 +86,6 @@ obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o usb-simtec.o
71obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o 86obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o
72obj-$(CONFIG_MACH_OTOM) += mach-otom.o 87obj-$(CONFIG_MACH_OTOM) += mach-otom.o
73obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o 88obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
89obj-$(CONFIG_MACH_VSTMS) += mach-vstms.o
74 90
75obj-$(CONFIG_MACH_SMDK) += common-smdk.o \ No newline at end of file 91obj-$(CONFIG_MACH_SMDK) += common-smdk.o \ No newline at end of file
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index def4441d2442..440e9aa0211a 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -18,10 +18,6 @@
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 * Modifications:
23 * 08-Jan-2003 BJD Moved from central IRQ code
24 * 21-Aug-2005 BJD Fixed missing code and compile errors
25*/ 21*/
26 22
27 23
diff --git a/arch/arm/mach-s3c2410/cpu.c b/arch/arm/mach-s3c2410/cpu.c
index 1c3c6adae6c4..9d4899eddf1f 100644
--- a/arch/arm/mach-s3c2410/cpu.c
+++ b/arch/arm/mach-s3c2410/cpu.c
@@ -124,6 +124,15 @@ static struct cpu_table cpu_ids[] __initdata = {
124 .init = s3c2412_init, 124 .init = s3c2412_init,
125 .name = name_s3c2412, 125 .name = name_s3c2412,
126 }, 126 },
127 { /* a newer version of the s3c2412 */
128 .idcode = 0x32412003,
129 .idmask = 0xffffffff,
130 .map_io = s3c2412_map_io,
131 .init_clocks = s3c2412_init_clocks,
132 .init_uarts = s3c2412_init_uarts,
133 .init = s3c2412_init,
134 .name = name_s3c2412,
135 },
127 { 136 {
128 .idcode = 0x0, /* S3C2400 doesn't have an idcode */ 137 .idcode = 0x0, /* S3C2400 doesn't have an idcode */
129 .idmask = 0xffffffff, 138 .idmask = 0xffffffff,
diff --git a/arch/arm/mach-s3c2410/devs.h b/arch/arm/mach-s3c2410/devs.h
index 726e2eaf8797..14fb0bade716 100644
--- a/arch/arm/mach-s3c2410/devs.h
+++ b/arch/arm/mach-s3c2410/devs.h
@@ -8,11 +8,6 @@
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 *
12 * Modifications:
13 * 18-Aug-2004 BJD Created initial version
14 * 27-Aug-2004 BJD Added timers 0 through 3
15 * 10-Feb-2005 BJD Added camera from guillaume.gourat@nexvision.tv
16*/ 11*/
17#include <linux/platform_device.h> 12#include <linux/platform_device.h>
18 13
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index cc92a7b2db88..d264bbbd8bef 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -1,35 +1,16 @@
1/* linux/arch/arm/mach-bast/dma.c 1/* linux/arch/arm/mach-s3c2410/dma.c
2 * 2 *
3 * (c) 2003-2005 Simtec Electronics 3 * (c) 2003-2005,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * S3C2410 DMA core 6 * S3C2410 DMA core
7 * 7 *
8 * http://www.simtec.co.uk/products/EB2410ITX/ 8 * http://armlinux.simtec.co.uk/
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 * 13*/
14 * Changelog:
15 * 27-Feb-2005 BJD Added kmem cache for dma descriptors
16 * 18-Nov-2004 BJD Removed error for loading onto stopped channel
17 * 10-Nov-2004 BJD Ensure all external symbols exported for modules
18 * 10-Nov-2004 BJD Use sys_device and sysdev_class for power management
19 * 08-Aug-2004 BJD Apply rmk's suggestions
20 * 21-Jul-2004 BJD Ported to linux 2.6
21 * 12-Jul-2004 BJD Finished re-write and change of API
22 * 06-Jul-2004 BJD Rewrote dma code to try and cope with various problems
23 * 23-May-2003 BJD Created file
24 * 19-Aug-2003 BJD Cleanup, header fix, added URL
25 *
26 * This file is based on the Sangwook Lee/Samsung patches, re-written due
27 * to various ommisions from the code (such as flexible dma configuration)
28 * for use with the BAST system board.
29 *
30 * The re-write is pretty much complete, and should be good enough for any
31 * possible DMA function
32 */
33 14
34 15
35#ifdef CONFIG_S3C2410_DMA_DEBUG 16#ifdef CONFIG_S3C2410_DMA_DEBUG
@@ -55,10 +36,14 @@
55#include <asm/mach/dma.h> 36#include <asm/mach/dma.h>
56#include <asm/arch/map.h> 37#include <asm/arch/map.h>
57 38
39#include "dma.h"
40
58/* io map for dma */ 41/* io map for dma */
59static void __iomem *dma_base; 42static void __iomem *dma_base;
60static kmem_cache_t *dma_kmem; 43static kmem_cache_t *dma_kmem;
61 44
45struct s3c24xx_dma_selection dma_sel;
46
62/* dma channel state information */ 47/* dma channel state information */
63struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS]; 48struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
64 49
@@ -79,7 +64,6 @@ dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val)
79 pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg); 64 pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
80 writel(val, dma_regaddr(chan, reg)); 65 writel(val, dma_regaddr(chan, reg));
81} 66}
82
83#endif 67#endif
84 68
85#define dma_rdreg(chan, reg) readl((chan)->regs + (reg)) 69#define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
@@ -151,12 +135,20 @@ dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
151#define dbg_showchan(chan) do { } while(0) 135#define dbg_showchan(chan) do { } while(0)
152#endif /* CONFIG_S3C2410_DMA_DEBUG */ 136#endif /* CONFIG_S3C2410_DMA_DEBUG */
153 137
154#define check_channel(chan) \ 138static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
155 do { if ((chan) >= S3C2410_DMA_CHANNELS) { \
156 printk(KERN_ERR "%s: invalid channel %d\n", __FUNCTION__, (chan)); \
157 return -EINVAL; \
158 } } while(0)
159 139
140/* lookup_dma_channel
141 *
142 * change the dma channel number given into a real dma channel id
143*/
144
145static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
146{
147 if (channel & DMACH_LOW_LEVEL)
148 return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
149 else
150 return dma_chan_map[channel];
151}
160 152
161/* s3c2410_dma_stats_timeout 153/* s3c2410_dma_stats_timeout
162 * 154 *
@@ -321,8 +313,10 @@ static inline void
321s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf, 313s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf,
322 enum s3c2410_dma_buffresult result) 314 enum s3c2410_dma_buffresult result)
323{ 315{
316#if 0
324 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n", 317 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
325 chan->callback_fn, buf, buf->id, buf->size, result); 318 chan->callback_fn, buf, buf->id, buf->size, result);
319#endif
326 320
327 if (chan->callback_fn != NULL) { 321 if (chan->callback_fn != NULL) {
328 (chan->callback_fn)(chan, buf->id, buf->size, result); 322 (chan->callback_fn)(chan, buf->id, buf->size, result);
@@ -439,7 +433,6 @@ s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
439 return 0; 433 return 0;
440} 434}
441 435
442
443/* s3c2410_dma_enqueue 436/* s3c2410_dma_enqueue
444 * 437 *
445 * queue an given buffer for dma transfer. 438 * queue an given buffer for dma transfer.
@@ -460,11 +453,12 @@ s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
460int s3c2410_dma_enqueue(unsigned int channel, void *id, 453int s3c2410_dma_enqueue(unsigned int channel, void *id,
461 dma_addr_t data, int size) 454 dma_addr_t data, int size)
462{ 455{
463 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 456 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
464 struct s3c2410_dma_buf *buf; 457 struct s3c2410_dma_buf *buf;
465 unsigned long flags; 458 unsigned long flags;
466 459
467 check_channel(channel); 460 if (chan == NULL)
461 return -EINVAL;
468 462
469 pr_debug("%s: id=%p, data=%08x, size=%d\n", 463 pr_debug("%s: id=%p, data=%08x, size=%d\n",
470 __FUNCTION__, id, (unsigned int)data, size); 464 __FUNCTION__, id, (unsigned int)data, size);
@@ -562,8 +556,10 @@ s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf)
562static inline void 556static inline void
563s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan) 557s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
564{ 558{
559#if 0
565 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n", 560 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
566 chan->number, chan->load_state); 561 chan->number, chan->load_state);
562#endif
567 563
568 switch (chan->load_state) { 564 switch (chan->load_state) {
569 case S3C2410_DMALOAD_NONE: 565 case S3C2410_DMALOAD_NONE:
@@ -718,7 +714,8 @@ s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs)
718 if (chan->load_state == S3C2410_DMALOAD_NONE) { 714 if (chan->load_state == S3C2410_DMALOAD_NONE) {
719 pr_debug("dma%d: end of transfer, stopping channel (%ld)\n", 715 pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
720 chan->number, jiffies); 716 chan->number, jiffies);
721 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP); 717 s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
718 S3C2410_DMAOP_STOP);
722 } 719 }
723 } 720 }
724 721
@@ -726,37 +723,34 @@ s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs)
726 return IRQ_HANDLED; 723 return IRQ_HANDLED;
727} 724}
728 725
726static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel);
727
729/* s3c2410_request_dma 728/* s3c2410_request_dma
730 * 729 *
731 * get control of an dma channel 730 * get control of an dma channel
732*/ 731*/
733 732
734int s3c2410_dma_request(unsigned int channel, struct s3c2410_dma_client *client, 733int s3c2410_dma_request(unsigned int channel,
734 struct s3c2410_dma_client *client,
735 void *dev) 735 void *dev)
736{ 736{
737 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 737 struct s3c2410_dma_chan *chan;
738 unsigned long flags; 738 unsigned long flags;
739 int err; 739 int err;
740 740
741 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n", 741 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
742 channel, client->name, dev); 742 channel, client->name, dev);
743 743
744 check_channel(channel);
745
746 local_irq_save(flags); 744 local_irq_save(flags);
747 745
748 dbg_showchan(chan); 746 chan = s3c2410_dma_map_channel(channel);
749 747 if (chan == NULL) {
750 if (chan->in_use) { 748 local_irq_restore(flags);
751 if (client != chan->client) { 749 return -EBUSY;
752 printk(KERN_ERR "dma%d: already in use\n", channel);
753 local_irq_restore(flags);
754 return -EBUSY;
755 } else {
756 printk(KERN_ERR "dma%d: client already has channel\n", channel);
757 }
758 } 750 }
759 751
752 dbg_showchan(chan);
753
760 chan->client = client; 754 chan->client = client;
761 chan->in_use = 1; 755 chan->in_use = 1;
762 756
@@ -809,14 +803,14 @@ EXPORT_SYMBOL(s3c2410_dma_request);
809 803
810int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client) 804int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client)
811{ 805{
812 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 806 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
813 unsigned long flags; 807 unsigned long flags;
814 808
815 check_channel(channel); 809 if (chan == NULL)
810 return -EINVAL;
816 811
817 local_irq_save(flags); 812 local_irq_save(flags);
818 813
819
820 if (chan->client != client) { 814 if (chan->client != client) {
821 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n", 815 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
822 channel, chan->client, client); 816 channel, chan->client, client);
@@ -837,8 +831,12 @@ int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client)
837 831
838 if (chan->irq_claimed) 832 if (chan->irq_claimed)
839 free_irq(chan->irq, (void *)chan); 833 free_irq(chan->irq, (void *)chan);
834
840 chan->irq_claimed = 0; 835 chan->irq_claimed = 0;
841 836
837 if (!(channel & DMACH_LOW_LEVEL))
838 dma_chan_map[channel] = NULL;
839
842 local_irq_restore(flags); 840 local_irq_restore(flags);
843 841
844 return 0; 842 return 0;
@@ -848,8 +846,8 @@ EXPORT_SYMBOL(s3c2410_dma_free);
848 846
849static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan) 847static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan)
850{ 848{
851 unsigned long tmp;
852 unsigned long flags; 849 unsigned long flags;
850 unsigned long tmp;
853 851
854 pr_debug("%s:\n", __FUNCTION__); 852 pr_debug("%s:\n", __FUNCTION__);
855 853
@@ -997,9 +995,10 @@ s3c2410_dma_started(struct s3c2410_dma_chan *chan)
997int 995int
998s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op) 996s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op)
999{ 997{
1000 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 998 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1001 999
1002 check_channel(channel); 1000 if (chan == NULL)
1001 return -EINVAL;
1003 1002
1004 switch (op) { 1003 switch (op) {
1005 case S3C2410_DMAOP_START: 1004 case S3C2410_DMAOP_START:
@@ -1046,12 +1045,19 @@ int s3c2410_dma_config(dmach_t channel,
1046 int xferunit, 1045 int xferunit,
1047 int dcon) 1046 int dcon)
1048{ 1047{
1049 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 1048 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1050 1049
1051 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n", 1050 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
1052 __FUNCTION__, channel, xferunit, dcon); 1051 __FUNCTION__, channel, xferunit, dcon);
1053 1052
1054 check_channel(channel); 1053 if (chan == NULL)
1054 return -EINVAL;
1055
1056 printk("Initial dcon is %08x\n", dcon);
1057
1058 dcon |= chan->dcon & dma_sel.dcon_mask;
1059
1060 printk("New dcon is %08x\n", dcon);
1055 1061
1056 switch (xferunit) { 1062 switch (xferunit) {
1057 case 1: 1063 case 1:
@@ -1086,9 +1092,10 @@ EXPORT_SYMBOL(s3c2410_dma_config);
1086 1092
1087int s3c2410_dma_setflags(dmach_t channel, unsigned int flags) 1093int s3c2410_dma_setflags(dmach_t channel, unsigned int flags)
1088{ 1094{
1089 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 1095 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1090 1096
1091 check_channel(channel); 1097 if (chan == NULL)
1098 return -EINVAL;
1092 1099
1093 pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags); 1100 pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags);
1094 1101
@@ -1106,9 +1113,10 @@ EXPORT_SYMBOL(s3c2410_dma_setflags);
1106 1113
1107int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn) 1114int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn)
1108{ 1115{
1109 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 1116 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1110 1117
1111 check_channel(channel); 1118 if (chan == NULL)
1119 return -EINVAL;
1112 1120
1113 pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn); 1121 pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn);
1114 1122
@@ -1121,9 +1129,10 @@ EXPORT_SYMBOL(s3c2410_dma_set_opfn);
1121 1129
1122int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn) 1130int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn)
1123{ 1131{
1124 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 1132 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1125 1133
1126 check_channel(channel); 1134 if (chan == NULL)
1135 return -EINVAL;
1127 1136
1128 pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn); 1137 pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn);
1129 1138
@@ -1153,9 +1162,10 @@ int s3c2410_dma_devconfig(int channel,
1153 int hwcfg, 1162 int hwcfg,
1154 unsigned long devaddr) 1163 unsigned long devaddr)
1155{ 1164{
1156 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 1165 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1157 1166
1158 check_channel(channel); 1167 if (chan == NULL)
1168 return -EINVAL;
1159 1169
1160 pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n", 1170 pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
1161 __FUNCTION__, (int)source, hwcfg, devaddr); 1171 __FUNCTION__, (int)source, hwcfg, devaddr);
@@ -1200,9 +1210,10 @@ EXPORT_SYMBOL(s3c2410_dma_devconfig);
1200 1210
1201int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst) 1211int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst)
1202{ 1212{
1203 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 1213 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1204 1214
1205 check_channel(channel); 1215 if (chan == NULL)
1216 return -EINVAL;
1206 1217
1207 if (src != NULL) 1218 if (src != NULL)
1208 *src = dma_rdreg(chan, S3C2410_DMA_DCSRC); 1219 *src = dma_rdreg(chan, S3C2410_DMA_DCSRC);
@@ -1252,7 +1263,7 @@ static int s3c2410_dma_resume(struct sys_device *dev)
1252#define s3c2410_dma_resume NULL 1263#define s3c2410_dma_resume NULL
1253#endif /* CONFIG_PM */ 1264#endif /* CONFIG_PM */
1254 1265
1255static struct sysdev_class dma_sysclass = { 1266struct sysdev_class dma_sysclass = {
1256 set_kset_name("s3c24xx-dma"), 1267 set_kset_name("s3c24xx-dma"),
1257 .suspend = s3c2410_dma_suspend, 1268 .suspend = s3c2410_dma_suspend,
1258 .resume = s3c2410_dma_resume, 1269 .resume = s3c2410_dma_resume,
@@ -1265,7 +1276,6 @@ static void s3c2410_dma_cache_ctor(void *p, kmem_cache_t *c, unsigned long f)
1265 memset(p, 0, sizeof(struct s3c2410_dma_buf)); 1276 memset(p, 0, sizeof(struct s3c2410_dma_buf));
1266} 1277}
1267 1278
1268
1269/* initialisation code */ 1279/* initialisation code */
1270 1280
1271static int __init s3c2410_init_dma(void) 1281static int __init s3c2410_init_dma(void)
@@ -1274,7 +1284,7 @@ static int __init s3c2410_init_dma(void)
1274 int channel; 1284 int channel;
1275 int ret; 1285 int ret;
1276 1286
1277 printk("S3C2410 DMA Driver, (c) 2003-2004 Simtec Electronics\n"); 1287 printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n");
1278 1288
1279 dma_base = ioremap(S3C24XX_PA_DMA, 0x200); 1289 dma_base = ioremap(S3C24XX_PA_DMA, 0x200);
1280 if (dma_base == NULL) { 1290 if (dma_base == NULL) {
@@ -1282,6 +1292,8 @@ static int __init s3c2410_init_dma(void)
1282 return -ENOMEM; 1292 return -ENOMEM;
1283 } 1293 }
1284 1294
1295 printk("Registering sysclass\n");
1296
1285 ret = sysdev_class_register(&dma_sysclass); 1297 ret = sysdev_class_register(&dma_sysclass);
1286 if (ret != 0) { 1298 if (ret != 0) {
1287 printk(KERN_ERR "dma sysclass registration failed\n"); 1299 printk(KERN_ERR "dma sysclass registration failed\n");
@@ -1335,4 +1347,95 @@ static int __init s3c2410_init_dma(void)
1335 return ret; 1347 return ret;
1336} 1348}
1337 1349
1338__initcall(s3c2410_init_dma); 1350core_initcall(s3c2410_init_dma);
1351
1352static inline int is_channel_valid(unsigned int channel)
1353{
1354 return (channel & DMA_CH_VALID);
1355}
1356
1357/* s3c2410_dma_map_channel()
1358 *
1359 * turn the virtual channel number into a real, and un-used hardware
1360 * channel.
1361 *
1362 * currently this code uses first-free channel from the specified harware
1363 * map, not taking into account anything that the board setup code may
1364 * have to say about the likely peripheral set to be in use.
1365*/
1366
1367struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
1368{
1369 struct s3c24xx_dma_map *ch_map;
1370 struct s3c2410_dma_chan *dmach;
1371 int ch;
1372
1373 if (dma_sel.map == NULL || channel > dma_sel.map_size)
1374 return NULL;
1375
1376 ch_map = dma_sel.map + channel;
1377
1378 for (ch = 0; ch < S3C2410_DMA_CHANNELS; ch++) {
1379 if (!is_channel_valid(ch_map->channels[ch]))
1380 continue;
1381
1382 if (s3c2410_chans[ch].in_use == 0) {
1383 printk("mapped channel %d to %d\n", channel, ch);
1384 break;
1385 }
1386 }
1387
1388 if (ch >= S3C2410_DMA_CHANNELS)
1389 return NULL;
1390
1391 /* update our channel mapping */
1392
1393 dmach = &s3c2410_chans[ch];
1394 dma_chan_map[channel] = dmach;
1395
1396 /* select the channel */
1397
1398 (dma_sel.select)(dmach, ch_map);
1399
1400 return dmach;
1401}
1402
1403static void s3c24xx_dma_show_ch(struct s3c24xx_dma_map *map, int ch)
1404{
1405 /* show the channel configuration */
1406
1407 printk("%2d: %20s, channels %c%c%c%c\n", ch, map->name,
1408 (is_channel_valid(map->channels[0]) ? '0' : '-'),
1409 (is_channel_valid(map->channels[1]) ? '1' : '-'),
1410 (is_channel_valid(map->channels[2]) ? '2' : '-'),
1411 (is_channel_valid(map->channels[3]) ? '3' : '-'));
1412}
1413
1414static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
1415{
1416 if (1)
1417 s3c24xx_dma_show_ch(map, ch);
1418
1419 return 0;
1420}
1421
1422int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
1423{
1424 struct s3c24xx_dma_map *nmap;
1425 size_t map_sz = sizeof(*nmap) * sel->map_size;
1426 int ptr;
1427
1428 nmap = kmalloc(map_sz, GFP_KERNEL);
1429 if (nmap == NULL)
1430 return -ENOMEM;
1431
1432 memcpy(nmap, sel->map, map_sz);
1433 memcpy(&dma_sel, sel, sizeof(*sel));
1434
1435 dma_sel.map = nmap;
1436
1437 for (ptr = 0; ptr < sel->map_size; ptr++)
1438 s3c24xx_dma_check_entry(nmap+ptr, ptr);
1439
1440 return 0;
1441}
diff --git a/arch/arm/mach-s3c2410/dma.h b/arch/arm/mach-s3c2410/dma.h
new file mode 100644
index 000000000000..0ebfe0aab80b
--- /dev/null
+++ b/arch/arm/mach-s3c2410/dma.h
@@ -0,0 +1,45 @@
1/* arch/arm/mach-s3c2410/dma.h
2 *
3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13extern struct sysdev_class dma_sysclass;
14extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
15
16#define DMA_CH_VALID (1<<31)
17
18struct s3c24xx_dma_addr {
19 unsigned long from;
20 unsigned long to;
21};
22
23/* struct s3c24xx_dma_map
24 *
25 * this holds the mapping information for the channel selected
26 * to be connected to the specified device
27*/
28
29struct s3c24xx_dma_map {
30 const char *name;
31 struct s3c24xx_dma_addr hw_addr;
32
33 unsigned long channels[S3C2410_DMA_CHANNELS];
34};
35
36struct s3c24xx_dma_selection {
37 struct s3c24xx_dma_map *map;
38 unsigned long map_size;
39 unsigned long dcon_mask;
40
41 void (*select)(struct s3c2410_dma_chan *chan,
42 struct s3c24xx_dma_map *map);
43};
44
45extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
index cd39e8684584..db6393c99860 100644
--- a/arch/arm/mach-s3c2410/gpio.c
+++ b/arch/arm/mach-s3c2410/gpio.c
@@ -18,21 +18,7 @@
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 * 21*/
22 * Changelog
23 * 13-Sep-2004 BJD Implemented change of MISCCR
24 * 14-Sep-2004 BJD Added getpin call
25 * 14-Sep-2004 BJD Fixed bug in setpin() call
26 * 30-Sep-2004 BJD Fixed cfgpin() mask bug
27 * 01-Oct-2004 BJD Added getcfg() to get pin configuration
28 * 01-Oct-2004 BJD Fixed mask bug in pullup() call
29 * 01-Oct-2004 BJD Added getirq() to turn pin into irqno
30 * 04-Oct-2004 BJD Added irq filter controls for GPIO
31 * 05-Nov-2004 BJD EXPORT_SYMBOL() added for all code
32 * 13-Mar-2005 BJD Updates for __iomem
33 * 26-Oct-2005 BJD Added generic configuration types
34 * 15-Jan-2006 LCVR Added support for the S3C2400
35 */
36 22
37 23
38#include <linux/kernel.h> 24#include <linux/kernel.h>
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index cd6139b35999..3e9f3462c61b 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -181,17 +181,19 @@ s3c_irq_unmask(unsigned int irqno)
181} 181}
182 182
183struct irqchip s3c_irq_level_chip = { 183struct irqchip s3c_irq_level_chip = {
184 .ack = s3c_irq_maskack, 184 .name = "s3c-level",
185 .mask = s3c_irq_mask, 185 .ack = s3c_irq_maskack,
186 .unmask = s3c_irq_unmask, 186 .mask = s3c_irq_mask,
187 .set_wake = s3c_irq_wake 187 .unmask = s3c_irq_unmask,
188 .set_wake = s3c_irq_wake
188}; 189};
189 190
190static struct irqchip s3c_irq_chip = { 191static struct irqchip s3c_irq_chip = {
191 .ack = s3c_irq_ack, 192 .name = "s3c",
192 .mask = s3c_irq_mask, 193 .ack = s3c_irq_ack,
193 .unmask = s3c_irq_unmask, 194 .mask = s3c_irq_mask,
194 .set_wake = s3c_irq_wake 195 .unmask = s3c_irq_unmask,
196 .set_wake = s3c_irq_wake
195}; 197};
196 198
197static void 199static void
@@ -343,19 +345,21 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
343} 345}
344 346
345static struct irqchip s3c_irqext_chip = { 347static struct irqchip s3c_irqext_chip = {
346 .mask = s3c_irqext_mask, 348 .name = "s3c-ext",
347 .unmask = s3c_irqext_unmask, 349 .mask = s3c_irqext_mask,
348 .ack = s3c_irqext_ack, 350 .unmask = s3c_irqext_unmask,
349 .set_type = s3c_irqext_type, 351 .ack = s3c_irqext_ack,
350 .set_wake = s3c_irqext_wake 352 .set_type = s3c_irqext_type,
353 .set_wake = s3c_irqext_wake
351}; 354};
352 355
353static struct irqchip s3c_irq_eint0t4 = { 356static struct irqchip s3c_irq_eint0t4 = {
354 .ack = s3c_irq_ack, 357 .name = "s3c-ext0",
355 .mask = s3c_irq_mask, 358 .ack = s3c_irq_ack,
356 .unmask = s3c_irq_unmask, 359 .mask = s3c_irq_mask,
357 .set_wake = s3c_irq_wake, 360 .unmask = s3c_irq_unmask,
358 .set_type = s3c_irqext_type, 361 .set_wake = s3c_irq_wake,
362 .set_type = s3c_irqext_type,
359}; 363};
360 364
361/* mask values for the parent registers for each of the interrupt types */ 365/* mask values for the parent registers for each of the interrupt types */
@@ -387,9 +391,10 @@ s3c_irq_uart0_ack(unsigned int irqno)
387} 391}
388 392
389static struct irqchip s3c_irq_uart0 = { 393static struct irqchip s3c_irq_uart0 = {
390 .mask = s3c_irq_uart0_mask, 394 .name = "s3c-uart0",
391 .unmask = s3c_irq_uart0_unmask, 395 .mask = s3c_irq_uart0_mask,
392 .ack = s3c_irq_uart0_ack, 396 .unmask = s3c_irq_uart0_unmask,
397 .ack = s3c_irq_uart0_ack,
393}; 398};
394 399
395/* UART1 */ 400/* UART1 */
@@ -413,9 +418,10 @@ s3c_irq_uart1_ack(unsigned int irqno)
413} 418}
414 419
415static struct irqchip s3c_irq_uart1 = { 420static struct irqchip s3c_irq_uart1 = {
416 .mask = s3c_irq_uart1_mask, 421 .name = "s3c-uart1",
417 .unmask = s3c_irq_uart1_unmask, 422 .mask = s3c_irq_uart1_mask,
418 .ack = s3c_irq_uart1_ack, 423 .unmask = s3c_irq_uart1_unmask,
424 .ack = s3c_irq_uart1_ack,
419}; 425};
420 426
421/* UART2 */ 427/* UART2 */
@@ -439,9 +445,10 @@ s3c_irq_uart2_ack(unsigned int irqno)
439} 445}
440 446
441static struct irqchip s3c_irq_uart2 = { 447static struct irqchip s3c_irq_uart2 = {
442 .mask = s3c_irq_uart2_mask, 448 .name = "s3c-uart2",
443 .unmask = s3c_irq_uart2_unmask, 449 .mask = s3c_irq_uart2_mask,
444 .ack = s3c_irq_uart2_ack, 450 .unmask = s3c_irq_uart2_unmask,
451 .ack = s3c_irq_uart2_ack,
445}; 452};
446 453
447/* ADC and Touchscreen */ 454/* ADC and Touchscreen */
@@ -465,9 +472,10 @@ s3c_irq_adc_ack(unsigned int irqno)
465} 472}
466 473
467static struct irqchip s3c_irq_adc = { 474static struct irqchip s3c_irq_adc = {
468 .mask = s3c_irq_adc_mask, 475 .name = "s3c-adc",
469 .unmask = s3c_irq_adc_unmask, 476 .mask = s3c_irq_adc_mask,
470 .ack = s3c_irq_adc_ack, 477 .unmask = s3c_irq_adc_unmask,
478 .ack = s3c_irq_adc_ack,
471}; 479};
472 480
473/* irq demux for adc */ 481/* irq demux for adc */
@@ -569,23 +577,104 @@ s3c_irq_demux_uart2(unsigned int irq,
569} 577}
570 578
571static void 579static void
572s3c_irq_demux_extint(unsigned int irq, 580s3c_irq_demux_extint8(unsigned int irq,
573 struct irqdesc *desc, 581 struct irqdesc *desc,
574 struct pt_regs *regs) 582 struct pt_regs *regs)
575{ 583{
576 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); 584 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
577 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); 585 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
578 586
579 eintpnd &= ~eintmsk; 587 eintpnd &= ~eintmsk;
588 eintpnd &= ~0xff; /* ignore lower irqs */
580 589
581 if (eintpnd) { 590 /* we may as well handle all the pending IRQs here */
582 irq = fls(eintpnd);
583 irq += (IRQ_EINT4 - (4 + 1));
584 591
592 while (eintpnd) {
593 irq = __ffs(eintpnd);
594 eintpnd &= ~(1<<irq);
595
596 irq += (IRQ_EINT4 - 4);
585 desc_handle_irq(irq, irq_desc + irq, regs); 597 desc_handle_irq(irq, irq_desc + irq, regs);
586 } 598 }
599
600}
601
602static void
603s3c_irq_demux_extint4t7(unsigned int irq,
604 struct irqdesc *desc,
605 struct pt_regs *regs)
606{
607 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
608 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
609
610 eintpnd &= ~eintmsk;
611 eintpnd &= 0xff; /* only lower irqs */
612
613 /* we may as well handle all the pending IRQs here */
614
615 while (eintpnd) {
616 irq = __ffs(eintpnd);
617 eintpnd &= ~(1<<irq);
618
619 irq += (IRQ_EINT4 - 4);
620
621 desc_handle_irq(irq, irq_desc + irq, regs);
622 }
623}
624
625#ifdef CONFIG_PM
626
627static struct sleep_save irq_save[] = {
628 SAVE_ITEM(S3C2410_INTMSK),
629 SAVE_ITEM(S3C2410_INTSUBMSK),
630};
631
632/* the extint values move between the s3c2410/s3c2440 and the s3c2412
633 * so we use an array to hold them, and to calculate the address of
634 * the register at run-time
635*/
636
637static unsigned long save_extint[3];
638static unsigned long save_eintflt[4];
639static unsigned long save_eintmask;
640
641int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
642{
643 unsigned int i;
644
645 for (i = 0; i < ARRAY_SIZE(save_extint); i++)
646 save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
647
648 for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
649 save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
650
651 s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
652 save_eintmask = __raw_readl(S3C24XX_EINTMASK);
653
654 return 0;
587} 655}
588 656
657int s3c24xx_irq_resume(struct sys_device *dev)
658{
659 unsigned int i;
660
661 for (i = 0; i < ARRAY_SIZE(save_extint); i++)
662 __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
663
664 for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
665 __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
666
667 s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
668 __raw_writel(save_eintmask, S3C24XX_EINTMASK);
669
670 return 0;
671}
672
673#else
674#define s3c24xx_irq_suspend NULL
675#define s3c24xx_irq_resume NULL
676#endif
677
589/* s3c24xx_init_irq 678/* s3c24xx_init_irq
590 * 679 *
591 * Initialise S3C2410 IRQ system 680 * Initialise S3C2410 IRQ system
@@ -674,8 +763,8 @@ void __init s3c24xx_init_irq(void)
674 763
675 /* setup the cascade irq handlers */ 764 /* setup the cascade irq handlers */
676 765
677 set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint); 766 set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
678 set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint); 767 set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
679 768
680 set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0); 769 set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
681 set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1); 770 set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
new file mode 100644
index 000000000000..ba5109af40b4
--- /dev/null
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -0,0 +1,266 @@
1/***********************************************************************
2 *
3 * linux/arch/arm/mach-s3c2410/mach-amlm5900.c
4 *
5 * Copyright (c) 2006 American Microsystems Limited
6 * David Anders <danders@amltd.com>
7
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * @History:
24 * derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by
25 * Ben Dooks <ben@simtec.co.uk>
26 *
27 ***********************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/types.h>
31#include <linux/interrupt.h>
32#include <linux/list.h>
33#include <linux/timer.h>
34#include <linux/init.h>
35#include <linux/device.h>
36#include <linux/platform_device.h>
37#include <linux/proc_fs.h>
38
39
40#include <asm/mach/arch.h>
41#include <asm/mach/map.h>
42#include <asm/mach/irq.h>
43#include <asm/mach/flash.h>
44
45#include <asm/hardware.h>
46#include <asm/io.h>
47#include <asm/irq.h>
48#include <asm/mach-types.h>
49#include <asm/arch/fb.h>
50
51#include <asm/arch/regs-serial.h>
52#include <asm/arch/regs-lcd.h>
53#include <asm/arch/regs-gpio.h>
54
55#include "devs.h"
56#include "cpu.h"
57
58#ifdef CONFIG_MTD_PARTITIONS
59
60#include <linux/mtd/mtd.h>
61#include <linux/mtd/partitions.h>
62#include <linux/mtd/map.h>
63#include <linux/mtd/physmap.h>
64
65static struct resource amlm5900_nor_resource = {
66 .start = 0x00000000,
67 .end = 0x01000000 - 1,
68 .flags = IORESOURCE_MEM,
69};
70
71
72
73static struct mtd_partition amlm5900_mtd_partitions[] = {
74 {
75 .name = "System",
76 .size = 0x240000,
77 .offset = 0,
78 .mask_flags = MTD_WRITEABLE, /* force read-only */
79 }, {
80 .name = "Kernel",
81 .size = 0x100000,
82 .offset = MTDPART_OFS_APPEND,
83 }, {
84 .name = "Ramdisk",
85 .size = 0x300000,
86 .offset = MTDPART_OFS_APPEND,
87 }, {
88 .name = "JFFS2",
89 .size = 0x9A0000,
90 .offset = MTDPART_OFS_APPEND,
91 }, {
92 .name = "Settings",
93 .size = MTDPART_SIZ_FULL,
94 .offset = MTDPART_OFS_APPEND,
95 }
96};
97
98static struct physmap_flash_data amlm5900_flash_data = {
99 .width = 2,
100 .parts = amlm5900_mtd_partitions,
101 .nr_parts = ARRAY_SIZE(amlm5900_mtd_partitions),
102};
103
104static struct platform_device amlm5900_device_nor = {
105 .name = "physmap-flash",
106 .id = 0,
107 .dev = {
108 .platform_data = &amlm5900_flash_data,
109 },
110 .num_resources = 1,
111 .resource = &amlm5900_nor_resource,
112};
113#endif
114
115static struct map_desc amlm5900_iodesc[] __initdata = {
116 {
117 .virtual = (u32)S3C24XX_VA_SPI,
118 .pfn = __phys_to_pfn(S3C2410_PA_SPI),
119 .length = SZ_1M,
120 .type = MT_DEVICE
121 }
122};
123
124#define UCON S3C2410_UCON_DEFAULT
125#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
126#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
127
128static struct s3c2410_uartcfg amlm5900_uartcfgs[] = {
129 [0] = {
130 .hwport = 0,
131 .flags = 0,
132 .ucon = UCON,
133 .ulcon = ULCON,
134 .ufcon = UFCON,
135 },
136 [1] = {
137 .hwport = 1,
138 .flags = 0,
139 .ucon = UCON,
140 .ulcon = ULCON,
141 .ufcon = UFCON,
142 },
143 [2] = {
144 .hwport = 2,
145 .flags = 0,
146 .ucon = UCON,
147 .ulcon = ULCON,
148 .ufcon = UFCON,
149 }
150};
151
152
153static struct platform_device *amlm5900_devices[] __initdata = {
154#ifdef CONFIG_FB_S3C2410
155 &s3c_device_lcd,
156#endif
157 &s3c_device_adc,
158 &s3c_device_wdt,
159 &s3c_device_i2c,
160 &s3c_device_usb,
161 &s3c_device_rtc,
162 &s3c_device_usbgadget,
163 &s3c_device_sdi,
164#ifdef CONFIG_MTD_PARTITIONS
165 &amlm5900_device_nor,
166#endif
167};
168
169static struct s3c24xx_board amlm5900_board __initdata = {
170 .devices = amlm5900_devices,
171 .devices_count = ARRAY_SIZE(amlm5900_devices)
172};
173
174void __init amlm5900_map_io(void)
175{
176 s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
177 s3c24xx_init_clocks(0);
178 s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
179 s3c24xx_set_board(&amlm5900_board);
180}
181
182#ifdef CONFIG_FB_S3C2410
183static struct s3c2410fb_mach_info __initdata amlm5900_lcd_info = {
184 .width = 160,
185 .height = 160,
186
187/* commented out until stn patch is submitted
188* .type = S3C2410_LCDCON1_STN4,
189*/
190 .gpccon = 0xaaaaaaaa,
191 .gpccon_mask = 0xffffffff,
192 .gpcup = 0x0000ffff,
193 .gpcup_mask = 0xffffffff,
194
195 .gpdcon = 0xaaaaaaaa,
196 .gpdcon_mask = 0xffffffff,
197 .gpdup = 0x0000ffff,
198 .gpdup_mask = 0xffffffff,
199
200 .xres = {
201 .min = 160,
202 .max = 160,
203 .defval = 160,
204 },
205
206 .yres = {
207 .min = 160,
208 .max = 160,
209 .defval = 160,
210 },
211
212 .bpp = {
213 .min = 4,
214 .max = 4,
215 .defval = 4,
216 },
217
218 .regs = {
219 .lcdcon1 = 0x00008225,
220 .lcdcon2 = 0x0027c000,
221 .lcdcon3 = 0x00182708,
222 .lcdcon4 = 0x00000002,
223 .lcdcon5 = 0x00000001,
224 }
225};
226#endif
227
228static irqreturn_t
229amlm5900_wake_interrupt(int irq, void *ignored, struct pt_regs *regs)
230{
231 return IRQ_HANDLED;
232}
233
234static void amlm5900_init_pm(void)
235{
236 int ret = 0;
237
238 ret = request_irq(IRQ_EINT9, &amlm5900_wake_interrupt,
239 IRQF_TRIGGER_RISING | IRQF_SHARED,
240 "amlm5900_wakeup", &amlm5900_wake_interrupt);
241 if (ret != 0) {
242 printk(KERN_ERR "AML-M5900: no wakeup irq, %d?\n", ret);
243 } else {
244 enable_irq_wake(IRQ_EINT9);
245 /* configure the suspend/resume status pin */
246 s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP);
247 s3c2410_gpio_pullup(S3C2410_GPF2, 0);
248 }
249}
250static void __init amlm5900_init(void)
251{
252 amlm5900_init_pm();
253#ifdef CONFIG_FB_S3C2410
254 s3c24xx_fb_set_platdata(&amlm5900_lcd_info);
255#endif
256}
257
258MACHINE_START(AML_M5900, "AML_M5900")
259 .phys_io = S3C2410_PA_UART,
260 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
261 .boot_params = S3C2410_SDRAM_PA + 0x100,
262 .map_io = amlm5900_map_io,
263 .init_irq = s3c24xx_init_irq,
264 .init_machine = amlm5900_init,
265 .timer = &s3c24xx_timer,
266MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-anubis.c b/arch/arm/mach-s3c2410/mach-anubis.c
index 60641d452db3..e94cdcd96591 100644
--- a/arch/arm/mach-s3c2410/mach-anubis.c
+++ b/arch/arm/mach-s3c2410/mach-anubis.c
@@ -4,15 +4,9 @@
4 * http://armlinux.simtec.co.uk/ 4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk> 5 * Ben Dooks <ben@simtec.co.uk>
6 * 6 *
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
12 *
13 * Modifications:
14 * 02-May-2005 BJD Copied from mach-bast.c
15 * 20-Sep-2005 BJD Added static to non-exported items
16*/ 10*/
17 11
18#include <linux/kernel.h> 12#include <linux/kernel.h>
diff --git a/arch/arm/mach-s3c2410/mach-smdk2440.c b/arch/arm/mach-s3c2410/mach-smdk2440.c
index d661c6b7ff56..e2205ff1b0ee 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2440.c
@@ -11,15 +11,6 @@
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 * 13 *
14 * Modifications:
15 * 01-Nov-2004 BJD Initial version
16 * 12-Nov-2004 BJD Updated for release
17 * 04-Jan-2005 BJD Fixes for pre-release
18 * 22-Feb-2005 BJD Updated for 2.6.11-rc5 relesa
19 * 10-Mar-2005 LCVR Replaced S3C2410_VA by S3C24XX_VA
20 * 14-Mar-2005 BJD void __iomem fixes
21 * 20-Sep-2005 BJD Added static to non-exported items
22 * 26-Oct-2005 BJD Added framebuffer data
23*/ 14*/
24 15
25#include <linux/kernel.h> 16#include <linux/kernel.h>
diff --git a/arch/arm/mach-s3c2410/mach-vstms.c b/arch/arm/mach-s3c2410/mach-vstms.c
new file mode 100644
index 000000000000..ea554e7c006e
--- /dev/null
+++ b/arch/arm/mach-s3c2410/mach-vstms.c
@@ -0,0 +1,168 @@
1/* linux/arch/arm/mach-s3c2410/mach-vstms.c
2 *
3 * (C) 2006 Thomas Gleixner <tglx@linutronix.de>
4 *
5 * Derived from mach-smdk2413.c - (C) 2006 Simtec Electronics
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/platform_device.h>
19
20#include <linux/mtd/mtd.h>
21#include <linux/mtd/nand.h>
22#include <linux/mtd/nand_ecc.h>
23#include <linux/mtd/partitions.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28
29#include <asm/hardware.h>
30#include <asm/hardware/iomd.h>
31#include <asm/setup.h>
32#include <asm/io.h>
33#include <asm/irq.h>
34#include <asm/mach-types.h>
35
36#include <asm/arch/regs-serial.h>
37#include <asm/arch/regs-gpio.h>
38#include <asm/arch/regs-lcd.h>
39
40#include <asm/arch/idle.h>
41#include <asm/arch/fb.h>
42
43#include <asm/arch/nand.h>
44
45#include "s3c2410.h"
46#include "s3c2412.h"
47#include "clock.h"
48#include "devs.h"
49#include "cpu.h"
50
51
52static struct map_desc vstms_iodesc[] __initdata = {
53};
54
55static struct s3c2410_uartcfg vstms_uartcfgs[] __initdata = {
56 [0] = {
57 .hwport = 0,
58 .flags = 0,
59 .ucon = 0x3c5,
60 .ulcon = 0x03,
61 .ufcon = 0x51,
62 },
63 [1] = {
64 .hwport = 1,
65 .flags = 0,
66 .ucon = 0x3c5,
67 .ulcon = 0x03,
68 .ufcon = 0x51,
69 },
70 [2] = {
71 .hwport = 2,
72 .flags = 0,
73 .ucon = 0x3c5,
74 .ulcon = 0x03,
75 .ufcon = 0x51,
76 }
77};
78
79static struct mtd_partition vstms_nand_part[] = {
80 [0] = {
81 .name = "Boot Agent",
82 .size = 0x7C000,
83 .offset = 0,
84 },
85 [1] = {
86 .name = "UBoot Config",
87 .offset = 0x7C000,
88 .size = 0x4000,
89 },
90 [2] = {
91 .name = "Kernel",
92 .offset = 0x80000,
93 .size = 0x200000,
94 },
95 [3] = {
96 .name = "RFS",
97 .offset = 0x280000,
98 .size = 0x3d80000,
99 },
100};
101
102static struct s3c2410_nand_set vstms_nand_sets[] = {
103 [0] = {
104 .name = "NAND",
105 .nr_chips = 1,
106 .nr_partitions = ARRAY_SIZE(vstms_nand_part),
107 .partitions = vstms_nand_part,
108 },
109};
110
111/* choose a set of timings which should suit most 512Mbit
112 * chips and beyond.
113*/
114
115static struct s3c2410_platform_nand vstms_nand_info = {
116 .tacls = 20,
117 .twrph0 = 60,
118 .twrph1 = 20,
119 .nr_sets = ARRAY_SIZE(vstms_nand_sets),
120 .sets = vstms_nand_sets,
121};
122
123static struct platform_device *vstms_devices[] __initdata = {
124 &s3c_device_usb,
125 &s3c_device_wdt,
126 &s3c_device_i2c,
127 &s3c_device_iis,
128 &s3c_device_rtc,
129 &s3c_device_nand,
130};
131
132static struct s3c24xx_board vstms_board __initdata = {
133 .devices = vstms_devices,
134 .devices_count = ARRAY_SIZE(vstms_devices)
135};
136
137static void __init vstms_fixup(struct machine_desc *desc,
138 struct tag *tags, char **cmdline,
139 struct meminfo *mi)
140{
141 if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) {
142 mi->nr_banks=1;
143 mi->bank[0].start = 0x30000000;
144 mi->bank[0].size = SZ_64M;
145 mi->bank[0].node = 0;
146 }
147}
148
149static void __init vstms_map_io(void)
150{
151 s3c_device_nand.dev.platform_data = &vstms_nand_info;
152
153 s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
154 s3c24xx_init_clocks(12000000);
155 s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
156 s3c24xx_set_board(&vstms_board);
157}
158
159MACHINE_START(VSTMS, "VSTMS")
160 .phys_io = S3C2410_PA_UART,
161 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
162 .boot_params = S3C2410_SDRAM_PA + 0x100,
163
164 .fixup = vstms_fixup,
165 .init_irq = s3c24xx_init_irq,
166 .map_io = vstms_map_io,
167 .timer = &s3c24xx_timer,
168MACHINE_END
diff --git a/arch/arm/mach-s3c2410/pm-simtec.c b/arch/arm/mach-s3c2410/pm-simtec.c
index 7b244566a436..42cd05e298f8 100644
--- a/arch/arm/mach-s3c2410/pm-simtec.c
+++ b/arch/arm/mach-s3c2410/pm-simtec.c
@@ -49,7 +49,8 @@ static __init int pm_simtec_init(void)
49 /* check which machine we are running on */ 49 /* check which machine we are running on */
50 50
51 if (!machine_is_bast() && !machine_is_vr1000() && 51 if (!machine_is_bast() && !machine_is_vr1000() &&
52 !machine_is_anubis() && !machine_is_osiris()) 52 !machine_is_anubis() && !machine_is_osiris() &&
53 !machine_is_aml_m5900())
53 return 0; 54 return 0;
54 55
55 printk(KERN_INFO "Simtec Board Power Manangement" COPYRIGHT "\n"); 56 printk(KERN_INFO "Simtec Board Power Manangement" COPYRIGHT "\n");
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index a589fe76d915..b49a0b3b72b3 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s3c2410/pm.c 1/* linux/arch/arm/mach-s3c2410/pm.c
2 * 2 *
3 * Copyright (c) 2004 Simtec Electronics 3 * Copyright (c) 2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * S3C2410 Power Manager (Suspend-To-RAM) support 6 * S3C24XX Power Manager (Suspend-To-RAM) support
7 * 7 *
8 * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information 8 * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
9 * 9 *
@@ -24,9 +24,6 @@
24 * Parts based on arch/arm/mach-pxa/pm.c 24 * Parts based on arch/arm/mach-pxa/pm.c
25 * 25 *
26 * Thanks to Dimitry Andric for debugging 26 * Thanks to Dimitry Andric for debugging
27 *
28 * Modifications:
29 * 10-Mar-2005 LCVR Changed S3C2410_VA_UART to S3C24XX_VA_UART
30*/ 27*/
31 28
32#include <linux/init.h> 29#include <linux/init.h>
@@ -38,6 +35,7 @@
38#include <linux/ioport.h> 35#include <linux/ioport.h>
39#include <linux/delay.h> 36#include <linux/delay.h>
40 37
38#include <asm/cacheflush.h>
41#include <asm/hardware.h> 39#include <asm/hardware.h>
42#include <asm/io.h> 40#include <asm/io.h>
43 41
@@ -55,14 +53,6 @@
55 53
56unsigned long s3c_pm_flags; 54unsigned long s3c_pm_flags;
57 55
58/* cache functions from arch/arm/mm/proc-arm920.S */
59
60#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
61extern void arm920_flush_kern_cache_all(void);
62#else
63static void arm920_flush_kern_cache_all(void) { }
64#endif
65
66#define PFX "s3c24xx-pm: " 56#define PFX "s3c24xx-pm: "
67 57
68static struct sleep_save core_save[] = { 58static struct sleep_save core_save[] = {
@@ -92,19 +82,6 @@ static struct sleep_save core_save[] = {
92 SAVE_ITEM(S3C2410_REFRESH), 82 SAVE_ITEM(S3C2410_REFRESH),
93}; 83};
94 84
95/* this lot should be really saved by the IRQ code */
96static struct sleep_save irq_save[] = {
97 SAVE_ITEM(S3C2410_EXTINT0),
98 SAVE_ITEM(S3C2410_EXTINT1),
99 SAVE_ITEM(S3C2410_EXTINT2),
100 SAVE_ITEM(S3C2410_EINFLT0),
101 SAVE_ITEM(S3C2410_EINFLT1),
102 SAVE_ITEM(S3C2410_EINFLT2),
103 SAVE_ITEM(S3C2410_EINFLT3),
104 SAVE_ITEM(S3C2410_EINTMASK),
105 SAVE_ITEM(S3C2410_INTMSK)
106};
107
108static struct sleep_save gpio_save[] = { 85static struct sleep_save gpio_save[] = {
109 SAVE_ITEM(S3C2410_GPACON), 86 SAVE_ITEM(S3C2410_GPACON),
110 SAVE_ITEM(S3C2410_GPADAT), 87 SAVE_ITEM(S3C2410_GPADAT),
@@ -165,7 +142,7 @@ static struct sleep_save uart_save[] = {
165 142
166extern void printascii(const char *); 143extern void printascii(const char *);
167 144
168static void pm_dbg(const char *fmt, ...) 145void pm_dbg(const char *fmt, ...)
169{ 146{
170 va_list va; 147 va_list va;
171 char buff[256]; 148 char buff[256];
@@ -509,6 +486,9 @@ static void s3c2410_pm_configure_extint(void)
509 } 486 }
510} 487}
511 488
489void (*pm_cpu_prep)(void);
490void (*pm_cpu_sleep)(void);
491
512#define any_allowed(mask, allow) (((mask) & (allow)) != (allow)) 492#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
513 493
514/* s3c2410_pm_enter 494/* s3c2410_pm_enter
@@ -519,7 +499,6 @@ static void s3c2410_pm_configure_extint(void)
519static int s3c2410_pm_enter(suspend_state_t state) 499static int s3c2410_pm_enter(suspend_state_t state)
520{ 500{
521 unsigned long regs_save[16]; 501 unsigned long regs_save[16];
522 unsigned long tmp;
523 502
524 /* ensure the debug is initialised (if enabled) */ 503 /* ensure the debug is initialised (if enabled) */
525 504
@@ -527,6 +506,11 @@ static int s3c2410_pm_enter(suspend_state_t state)
527 506
528 DBG("s3c2410_pm_enter(%d)\n", state); 507 DBG("s3c2410_pm_enter(%d)\n", state);
529 508
509 if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
510 printk(KERN_ERR PFX "error: no cpu sleep functions set\n");
511 return -EINVAL;
512 }
513
530 if (state != PM_SUSPEND_MEM) { 514 if (state != PM_SUSPEND_MEM) {
531 printk(KERN_ERR PFX "error: only PM_SUSPEND_MEM supported\n"); 515 printk(KERN_ERR PFX "error: only PM_SUSPEND_MEM supported\n");
532 return -EINVAL; 516 return -EINVAL;
@@ -554,17 +538,9 @@ static int s3c2410_pm_enter(suspend_state_t state)
554 538
555 DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys); 539 DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys);
556 540
557 /* ensure at least GESTATUS3 has the resume address */
558
559 __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3);
560
561 DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
562 DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
563
564 /* save all necessary core registers not covered by the drivers */ 541 /* save all necessary core registers not covered by the drivers */
565 542
566 s3c2410_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save)); 543 s3c2410_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save));
567 s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
568 s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save)); 544 s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
569 s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save)); 545 s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
570 546
@@ -581,10 +557,16 @@ static int s3c2410_pm_enter(suspend_state_t state)
581 /* ack any outstanding external interrupts before we go to sleep */ 557 /* ack any outstanding external interrupts before we go to sleep */
582 558
583 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); 559 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
560 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
561 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
562
563 /* call cpu specific preperation */
564
565 pm_cpu_prep();
584 566
585 /* flush cache back to ram */ 567 /* flush cache back to ram */
586 568
587 arm920_flush_kern_cache_all(); 569 flush_cache_all();
588 570
589 s3c2410_pm_check_store(); 571 s3c2410_pm_check_store();
590 572
@@ -592,23 +574,23 @@ static int s3c2410_pm_enter(suspend_state_t state)
592 574
593 __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ 575 __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
594 576
595 s3c2410_cpu_suspend(regs_save); 577 /* s3c2410_cpu_save will also act as our return point from when
578 * we resume as it saves its own register state, so use the return
579 * code to differentiate return from save and return from sleep */
580
581 if (s3c2410_cpu_save(regs_save) == 0) {
582 flush_cache_all();
583 pm_cpu_sleep();
584 }
596 585
597 /* restore the cpu state */ 586 /* restore the cpu state */
598 587
599 cpu_init(); 588 cpu_init();
600 589
601 /* unset the return-from-sleep flag, to ensure reset */
602
603 tmp = __raw_readl(S3C2410_GSTATUS2);
604 tmp &= S3C2410_GSTATUS2_OFFRESET;
605 __raw_writel(tmp, S3C2410_GSTATUS2);
606
607 /* restore the system state */ 590 /* restore the system state */
608 591
609 s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); 592 s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
610 s3c2410_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save)); 593 s3c2410_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save));
611 s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
612 s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save)); 594 s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
613 595
614 s3c2410_pm_debug_init(); 596 s3c2410_pm_debug_init();
diff --git a/arch/arm/mach-s3c2410/pm.h b/arch/arm/mach-s3c2410/pm.h
index 7a5e714c7386..ffe197a119fb 100644
--- a/arch/arm/mach-s3c2410/pm.h
+++ b/arch/arm/mach-s3c2410/pm.h
@@ -34,13 +34,19 @@ extern unsigned long s3c_irqwake_eintmask;
34extern unsigned long s3c_irqwake_intallow; 34extern unsigned long s3c_irqwake_intallow;
35extern unsigned long s3c_irqwake_eintallow; 35extern unsigned long s3c_irqwake_eintallow;
36 36
37/* per-cpu sleep functions */
38
39extern void (*pm_cpu_prep)(void);
40extern void (*pm_cpu_sleep)(void);
41
37/* Flags for PM Control */ 42/* Flags for PM Control */
38 43
39extern unsigned long s3c_pm_flags; 44extern unsigned long s3c_pm_flags;
40 45
41/* from sleep.S */ 46/* from sleep.S */
42 47
43extern void s3c2410_cpu_suspend(unsigned long *saveblk); 48extern int s3c2410_cpu_save(unsigned long *saveblk);
49extern void s3c2410_cpu_suspend(void);
44extern void s3c2410_cpu_resume(void); 50extern void s3c2410_cpu_resume(void);
45 51
46extern unsigned long s3c2410_sleep_save_phys; 52extern unsigned long s3c2410_sleep_save_phys;
@@ -57,3 +63,11 @@ struct sleep_save {
57 63
58extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count); 64extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count);
59extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count); 65extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count);
66
67#ifdef CONFIG_PM
68extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
69extern int s3c24xx_irq_resume(struct sys_device *dev);
70#else
71#define s3c24xx_irq_suspend NULL
72#define s3c24xx_irq_resume NULL
73#endif
diff --git a/arch/arm/mach-s3c2410/s3c2410-dma.c b/arch/arm/mach-s3c2410/s3c2410-dma.c
new file mode 100644
index 000000000000..51e5098b32e8
--- /dev/null
+++ b/arch/arm/mach-s3c2410/s3c2410-dma.c
@@ -0,0 +1,158 @@
1/* linux/arch/arm/mach-s3c2410/s3c2410-dma.c
2 *
3 * (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/sysdev.h>
18
19#include <asm/dma.h>
20#include <asm/arch/dma.h>
21#include "dma.h"
22
23#include "cpu.h"
24
25#include <asm/arch/regs-serial.h>
26#include <asm/arch/regs-gpio.h>
27#include <asm/arch/regs-ac97.h>
28#include <asm/arch/regs-mem.h>
29#include <asm/arch/regs-lcd.h>
30#include <asm/arch/regs-sdi.h>
31#include <asm/arch/regs-iis.h>
32#include <asm/arch/regs-spi.h>
33
34static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
35 [DMACH_XD0] = {
36 .name = "xdreq0",
37 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
38 },
39 [DMACH_XD1] = {
40 .name = "xdreq1",
41 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
42 },
43 [DMACH_SDI] = {
44 .name = "sdi",
45 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
46 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
47 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
48 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
49 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
50 },
51 [DMACH_SPI0] = {
52 .name = "spi0",
53 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
54 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
55 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
56 },
57 [DMACH_SPI1] = {
58 .name = "spi1",
59 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
60 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
61 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
62 },
63 [DMACH_UART0] = {
64 .name = "uart0",
65 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
66 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
67 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
68 },
69 [DMACH_UART1] = {
70 .name = "uart1",
71 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
72 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
73 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
74 },
75 [DMACH_UART2] = {
76 .name = "uart2",
77 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
78 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
79 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
80 },
81 [DMACH_TIMER] = {
82 .name = "timer",
83 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
84 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
85 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
86 },
87 [DMACH_I2S_IN] = {
88 .name = "i2s-sdi",
89 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
90 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
91 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
92 },
93 [DMACH_I2S_OUT] = {
94 .name = "i2s-sdo",
95 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
96 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
97 },
98 [DMACH_USB_EP1] = {
99 .name = "usb-ep1",
100 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
101 },
102 [DMACH_USB_EP2] = {
103 .name = "usb-ep2",
104 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
105 },
106 [DMACH_USB_EP3] = {
107 .name = "usb-ep3",
108 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
109 },
110 [DMACH_USB_EP4] = {
111 .name = "usb-ep4",
112 .channels[3] =S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
113 },
114};
115
116static void s3c2410_dma_select(struct s3c2410_dma_chan *chan,
117 struct s3c24xx_dma_map *map)
118{
119 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
120}
121
122static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = {
123 .select = s3c2410_dma_select,
124 .dcon_mask = 7 << 24,
125 .map = s3c2410_dma_mappings,
126 .map_size = ARRAY_SIZE(s3c2410_dma_mappings),
127};
128
129static int s3c2410_dma_add(struct sys_device *sysdev)
130{
131 return s3c24xx_dma_init_map(&s3c2410_dma_sel);
132}
133
134static struct sysdev_driver s3c2410_dma_driver = {
135 .add = s3c2410_dma_add,
136};
137
138static int __init s3c2410_dma_init(void)
139{
140 return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_dma_driver);
141}
142
143arch_initcall(s3c2410_dma_init);
144
145/* S3C2442 DMA contains the same selection table as the S3C2410 */
146
147static struct sysdev_driver s3c2442_dma_driver = {
148 .add = s3c2410_dma_add,
149};
150
151static int __init s3c2442_dma_init(void)
152{
153 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_dma_driver);
154}
155
156arch_initcall(s3c2442_dma_init);
157
158
diff --git a/arch/arm/mach-s3c2410/s3c2410-irq.c b/arch/arm/mach-s3c2410/s3c2410-irq.c
new file mode 100644
index 000000000000..c796c9c76e78
--- /dev/null
+++ b/arch/arm/mach-s3c2410/s3c2410-irq.c
@@ -0,0 +1,48 @@
1/* linux/arch/arm/mach-s3c2410/s3c2410-irq.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/ptrace.h>
27#include <linux/sysdev.h>
28
29#include "cpu.h"
30#include "pm.h"
31
32static int s3c2410_irq_add(struct sys_device *sysdev)
33{
34 return 0;
35}
36
37static struct sysdev_driver s3c2410_irq_driver = {
38 .add = s3c2410_irq_add,
39 .suspend = s3c24xx_irq_suspend,
40 .resume = s3c24xx_irq_resume,
41};
42
43static int s3c2410_irq_init(void)
44{
45 return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_irq_driver);
46}
47
48arch_initcall(s3c2410_irq_init);
diff --git a/arch/arm/mach-s3c2410/s3c2410-pm.c b/arch/arm/mach-s3c2410/s3c2410-pm.c
new file mode 100644
index 000000000000..e51d76669512
--- /dev/null
+++ b/arch/arm/mach-s3c2410/s3c2410-pm.c
@@ -0,0 +1,120 @@
1/* linux/arch/arm/mach-s3c2410/s3c2410-pm.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23#include <linux/init.h>
24#include <linux/suspend.h>
25#include <linux/errno.h>
26#include <linux/time.h>
27#include <linux/sysdev.h>
28
29#include <asm/hardware.h>
30#include <asm/io.h>
31
32#include <asm/mach-types.h>
33
34#include <asm/arch/regs-gpio.h>
35
36#include "cpu.h"
37#include "pm.h"
38
39#ifdef CONFIG_S3C2410_PM_DEBUG
40extern void pm_dbg(const char *fmt, ...);
41#define DBG(fmt...) pm_dbg(fmt)
42#else
43#define DBG(fmt...) printk(KERN_DEBUG fmt)
44#endif
45
46static void s3c2410_pm_prepare(void)
47{
48 /* ensure at least GSTATUS3 has the resume address */
49
50 __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3);
51
52 DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
53 DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
54
55 if ( machine_is_aml_m5900() )
56 s3c2410_gpio_setpin(S3C2410_GPF2, 1);
57
58}
59
60int s3c2410_pm_resume(struct sys_device *dev)
61{
62 unsigned long tmp;
63
64 /* unset the return-from-sleep flag, to ensure reset */
65
66 tmp = __raw_readl(S3C2410_GSTATUS2);
67 tmp &= S3C2410_GSTATUS2_OFFRESET;
68 __raw_writel(tmp, S3C2410_GSTATUS2);
69
70 if ( machine_is_aml_m5900() )
71 s3c2410_gpio_setpin(S3C2410_GPF2, 0);
72
73 return 0;
74}
75
76static int s3c2410_pm_add(struct sys_device *dev)
77{
78 pm_cpu_prep = s3c2410_pm_prepare;
79 pm_cpu_sleep = s3c2410_cpu_suspend;
80
81 return 0;
82}
83
84static struct sysdev_driver s3c2410_pm_driver = {
85 .add = s3c2410_pm_add,
86 .resume = s3c2410_pm_resume,
87};
88
89/* register ourselves */
90
91static int __init s3c2410_pm_drvinit(void)
92{
93 return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_pm_driver);
94}
95
96arch_initcall(s3c2410_pm_drvinit);
97
98static struct sysdev_driver s3c2440_pm_driver = {
99 .add = s3c2410_pm_add,
100 .resume = s3c2410_pm_resume,
101};
102
103static int __init s3c2440_pm_drvinit(void)
104{
105 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_pm_driver);
106}
107
108arch_initcall(s3c2440_pm_drvinit);
109
110static struct sysdev_driver s3c2442_pm_driver = {
111 .add = s3c2410_pm_add,
112 .resume = s3c2410_pm_resume,
113};
114
115static int __init s3c2442_pm_drvinit(void)
116{
117 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_pm_driver);
118}
119
120arch_initcall(s3c2442_pm_drvinit);
diff --git a/arch/arm/mach-s3c2410/s3c2410-sleep.S b/arch/arm/mach-s3c2410/s3c2410-sleep.S
new file mode 100644
index 000000000000..9179a1024588
--- /dev/null
+++ b/arch/arm/mach-s3c2410/s3c2410-sleep.S
@@ -0,0 +1,68 @@
1/* linux/arch/arm/mach-s3c2410/s3c2410-sleep.S
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 Power Manager (Suspend-To-RAM) support
7 *
8 * Based on PXA/SA1100 sleep code by:
9 * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
10 * Cliff Brake, (c) 2001
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25*/
26
27#include <linux/linkage.h>
28#include <asm/assembler.h>
29#include <asm/hardware.h>
30#include <asm/arch/map.h>
31
32#include <asm/arch/regs-gpio.h>
33#include <asm/arch/regs-clock.h>
34#include <asm/arch/regs-mem.h>
35#include <asm/arch/regs-serial.h>
36
37 /* s3c2410_cpu_suspend
38 *
39 * put the cpu into sleep mode
40 */
41
42ENTRY(s3c2410_cpu_suspend)
43 @@ prepare cpu to sleep
44
45 ldr r4, =S3C2410_REFRESH
46 ldr r5, =S3C24XX_MISCCR
47 ldr r6, =S3C2410_CLKCON
48 ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB)
49 ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB)
50 ldr r9, [ r6 ] @ get CLKCON (and ensure in TLB)
51
52 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
53 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
54 orr r9, r9, #S3C2410_CLKCON_POWER @ power down command
55
56 teq pc, #0 @ first as a trial-run to load cache
57 bl s3c2410_do_sleep
58 teq r0, r0 @ now do it for real
59 b s3c2410_do_sleep @
60
61 @@ align next bit of code to cache line
62 .align 8
63s3c2410_do_sleep:
64 streq r7, [ r4 ] @ SDRAM sleep command
65 streq r8, [ r5 ] @ SDRAM power-down config
66 streq r9, [ r6 ] @ CPU sleep
671: beq 1b
68 mov pc, r14
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index a110cff9cf6b..183e4033ce61 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -8,17 +8,6 @@
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 *
12 * Modifications:
13 * 16-May-2003 BJD Created initial version
14 * 16-Aug-2003 BJD Fixed header files and copyright, added URL
15 * 05-Sep-2003 BJD Moved to kernel v2.6
16 * 18-Jan-2004 BJD Added serial port configuration
17 * 21-Aug-2004 BJD Added new struct s3c2410_board handler
18 * 28-Sep-2004 BJD Updates for new serial port bits
19 * 04-Nov-2004 BJD Updated UART configuration process
20 * 10-Jan-2005 BJD Removed s3c2410_clock_tick_rate
21 * 13-Aug-2005 DA Removed UART from initial I/O mappings
22*/ 11*/
23 12
24#include <linux/kernel.h> 13#include <linux/kernel.h>
diff --git a/arch/arm/mach-s3c2410/s3c2412-dma.c b/arch/arm/mach-s3c2410/s3c2412-dma.c
new file mode 100644
index 000000000000..171f3706d36d
--- /dev/null
+++ b/arch/arm/mach-s3c2410/s3c2412-dma.c
@@ -0,0 +1,160 @@
1/* linux/arch/arm/mach-s3c2410/s3c2412-dma.c
2 *
3 * (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/sysdev.h>
18
19#include <asm/dma.h>
20#include <asm/arch/dma.h>
21#include <asm/io.h>
22
23#include "dma.h"
24#include "cpu.h"
25
26#include <asm/arch/regs-serial.h>
27#include <asm/arch/regs-gpio.h>
28#include <asm/arch/regs-ac97.h>
29#include <asm/arch/regs-mem.h>
30#include <asm/arch/regs-lcd.h>
31#include <asm/arch/regs-sdi.h>
32#include <asm/arch/regs-iis.h>
33#include <asm/arch/regs-spi.h>
34
35#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
36
37static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
38 [DMACH_XD0] = {
39 .name = "xdreq0",
40 .channels = MAP(S3C2412_DMAREQSEL_XDREQ0),
41 },
42 [DMACH_XD1] = {
43 .name = "xdreq1",
44 .channels = MAP(S3C2412_DMAREQSEL_XDREQ1),
45 },
46 [DMACH_SDI] = {
47 .name = "sdi",
48 .channels = MAP(S3C2412_DMAREQSEL_SDI),
49 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
50 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
51 },
52 [DMACH_SPI0] = {
53 .name = "spi0",
54 .channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
55 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
56 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
57 },
58 [DMACH_SPI1] = {
59 .name = "spi1",
60 .channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
61 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
62 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
63 },
64 [DMACH_UART0] = {
65 .name = "uart0",
66 .channels = MAP(S3C2412_DMAREQSEL_UART0_0),
67 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
68 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
69 },
70 [DMACH_UART1] = {
71 .name = "uart1",
72 .channels = MAP(S3C2412_DMAREQSEL_UART1_0),
73 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
74 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
75 },
76 [DMACH_UART2] = {
77 .name = "uart2",
78 .channels = MAP(S3C2412_DMAREQSEL_UART2_0),
79 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
80 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
81 },
82 [DMACH_UART0_SRC2] = {
83 .name = "uart0",
84 .channels = MAP(S3C2412_DMAREQSEL_UART0_1),
85 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
86 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
87 },
88 [DMACH_UART1_SRC2] = {
89 .name = "uart1",
90 .channels = MAP(S3C2412_DMAREQSEL_UART1_1),
91 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
92 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
93 },
94 [DMACH_UART2_SRC2] = {
95 .name = "uart2",
96 .channels = MAP(S3C2412_DMAREQSEL_UART2_1),
97 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
98 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
99 },
100 [DMACH_TIMER] = {
101 .name = "timer",
102 .channels = MAP(S3C2412_DMAREQSEL_TIMER),
103 },
104 [DMACH_I2S_IN] = {
105 .name = "i2s-sdi",
106 .channels = MAP(S3C2412_DMAREQSEL_I2SRX),
107 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
108 },
109 [DMACH_I2S_OUT] = {
110 .name = "i2s-sdo",
111 .channels = MAP(S3C2412_DMAREQSEL_I2STX),
112 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
113 },
114 [DMACH_USB_EP1] = {
115 .name = "usb-ep1",
116 .channels = MAP(S3C2412_DMAREQSEL_USBEP1),
117 },
118 [DMACH_USB_EP2] = {
119 .name = "usb-ep2",
120 .channels = MAP(S3C2412_DMAREQSEL_USBEP2),
121 },
122 [DMACH_USB_EP3] = {
123 .name = "usb-ep3",
124 .channels = MAP(S3C2412_DMAREQSEL_USBEP3),
125 },
126 [DMACH_USB_EP4] = {
127 .name = "usb-ep4",
128 .channels = MAP(S3C2412_DMAREQSEL_USBEP4),
129 },
130};
131
132static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
133 struct s3c24xx_dma_map *map)
134{
135 writel(chan->regs + S3C2412_DMA_DMAREQSEL,
136 map->channels[0] | S3C2412_DMAREQSEL_HW);
137}
138
139static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
140 .select = s3c2412_dma_select,
141 .dcon_mask = 0,
142 .map = s3c2412_dma_mappings,
143 .map_size = ARRAY_SIZE(s3c2412_dma_mappings),
144};
145
146static int s3c2412_dma_add(struct sys_device *sysdev)
147{
148 return s3c24xx_dma_init_map(&s3c2412_dma_sel);
149}
150
151static struct sysdev_driver s3c2412_dma_driver = {
152 .add = s3c2412_dma_add,
153};
154
155static int __init s3c2412_dma_init(void)
156{
157 return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver);
158}
159
160arch_initcall(s3c2412_dma_init);
diff --git a/arch/arm/mach-s3c2410/s3c2412-irq.c b/arch/arm/mach-s3c2410/s3c2412-irq.c
index c80ec93dfea9..7f741547658f 100644
--- a/arch/arm/mach-s3c2410/s3c2412-irq.c
+++ b/arch/arm/mach-s3c2410/s3c2412-irq.c
@@ -37,6 +37,7 @@
37 37
38#include "cpu.h" 38#include "cpu.h"
39#include "irq.h" 39#include "irq.h"
40#include "pm.h"
40 41
41/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by 42/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
42 * having them turn up in both the INT* and the EINT* registers. Whilst 43 * having them turn up in both the INT* and the EINT* registers. Whilst
@@ -120,6 +121,8 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
120 121
121static struct sysdev_driver s3c2412_irq_driver = { 122static struct sysdev_driver s3c2412_irq_driver = {
122 .add = s3c2412_irq_add, 123 .add = s3c2412_irq_add,
124 .suspend = s3c24xx_irq_suspend,
125 .resume = s3c24xx_irq_resume,
123}; 126};
124 127
125static int s3c2412_irq_init(void) 128static int s3c2412_irq_init(void)
diff --git a/arch/arm/mach-s3c2410/s3c2412-pm.c b/arch/arm/mach-s3c2410/s3c2412-pm.c
new file mode 100644
index 000000000000..19b63322d259
--- /dev/null
+++ b/arch/arm/mach-s3c2410/s3c2412-pm.c
@@ -0,0 +1,128 @@
1/* linux/arch/arm/mach-s3c2410/s3c2412-pm.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://armlinux.simtec.co.uk/.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/sysdev.h>
20#include <linux/platform_device.h>
21
22#include <asm/hardware.h>
23#include <asm/io.h>
24#include <asm/irq.h>
25
26#include <asm/arch/regs-power.h>
27#include <asm/arch/regs-gpioj.h>
28#include <asm/arch/regs-gpio.h>
29#include <asm/arch/regs-dsc.h>
30
31#include "cpu.h"
32#include "pm.h"
33
34#include "s3c2412.h"
35
36static void s3c2412_cpu_suspend(void)
37{
38 unsigned long tmp;
39
40 /* set our standby method to sleep */
41
42 tmp = __raw_readl(S3C2412_PWRCFG);
43 tmp |= S3C2412_PWRCFG_STANDBYWFI_SLEEP;
44 __raw_writel(tmp, S3C2412_PWRCFG);
45
46 /* issue the standby signal into the pm unit. Note, we
47 * issue a write-buffer drain just in case */
48
49 tmp = 0;
50
51 asm("b 1f\n\t"
52 ".align 5\n\t"
53 "1:\n\t"
54 "mcr p15, 0, %0, c7, c10, 4\n\t"
55 "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
56
57 /* we should never get past here */
58
59 panic("sleep resumed to originator?");
60}
61
62static void s3c2412_pm_prepare(void)
63{
64}
65
66static int s3c2412_pm_add(struct sys_device *sysdev)
67{
68 pm_cpu_prep = s3c2412_pm_prepare;
69 pm_cpu_sleep = s3c2412_cpu_suspend;
70
71 return 0;
72}
73
74static struct sleep_save s3c2412_sleep[] = {
75 SAVE_ITEM(S3C2412_DSC0),
76 SAVE_ITEM(S3C2412_DSC1),
77 SAVE_ITEM(S3C2413_GPJDAT),
78 SAVE_ITEM(S3C2413_GPJCON),
79 SAVE_ITEM(S3C2413_GPJUP),
80
81 /* save the PWRCFG to get back to original sleep method */
82
83 SAVE_ITEM(S3C2412_PWRCFG),
84
85 /* save the sleep configuration anyway, just in case these
86 * get damaged during wakeup */
87
88 SAVE_ITEM(S3C2412_GPBSLPCON),
89 SAVE_ITEM(S3C2412_GPCSLPCON),
90 SAVE_ITEM(S3C2412_GPDSLPCON),
91 SAVE_ITEM(S3C2412_GPESLPCON),
92 SAVE_ITEM(S3C2412_GPFSLPCON),
93 SAVE_ITEM(S3C2412_GPGSLPCON),
94 SAVE_ITEM(S3C2412_GPHSLPCON),
95 SAVE_ITEM(S3C2413_GPJSLPCON),
96};
97
98static int s3c2412_pm_suspend(struct sys_device *dev, pm_message_t state)
99{
100 s3c2410_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
101 return 0;
102}
103
104static int s3c2412_pm_resume(struct sys_device *dev)
105{
106 unsigned long tmp;
107
108 tmp = __raw_readl(S3C2412_PWRCFG);
109 tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
110 tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
111 __raw_writel(tmp, S3C2412_PWRCFG);
112
113 s3c2410_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
114 return 0;
115}
116
117static struct sysdev_driver s3c2412_pm_driver = {
118 .add = s3c2412_pm_add,
119 .suspend = s3c2412_pm_suspend,
120 .resume = s3c2412_pm_resume,
121};
122
123static __init int s3c2412_pm_init(void)
124{
125 return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_pm_driver);
126}
127
128arch_initcall(s3c2412_pm_init);
diff --git a/arch/arm/mach-s3c2410/s3c2412.c b/arch/arm/mach-s3c2410/s3c2412.c
index 2d163f7600be..e76431c41461 100644
--- a/arch/arm/mach-s3c2410/s3c2412.c
+++ b/arch/arm/mach-s3c2410/s3c2412.c
@@ -8,17 +8,6 @@
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 *
12 * Modifications:
13 * 16-May-2003 BJD Created initial version
14 * 16-Aug-2003 BJD Fixed header files and copyright, added URL
15 * 05-Sep-2003 BJD Moved to kernel v2.6
16 * 18-Jan-2004 BJD Added serial port configuration
17 * 21-Aug-2004 BJD Added new struct s3c2410_board handler
18 * 28-Sep-2004 BJD Updates for new serial port bits
19 * 04-Nov-2004 BJD Updated UART configuration process
20 * 10-Jan-2005 BJD Removed s3c2410_clock_tick_rate
21 * 13-Aug-2005 DA Removed UART from initial I/O mappings
22*/ 11*/
23 12
24#include <linux/kernel.h> 13#include <linux/kernel.h>
@@ -56,6 +45,13 @@
56 45
57#ifndef CONFIG_CPU_S3C2412_ONLY 46#ifndef CONFIG_CPU_S3C2412_ONLY
58void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO; 47void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
48
49static inline void s3c2412_init_gpio2(void)
50{
51 s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
52}
53#else
54#define s3c2412_init_gpio2() do { } while(0)
59#endif 55#endif
60 56
61/* Initial IO mappings */ 57/* Initial IO mappings */
@@ -76,6 +72,7 @@ void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
76 72
77 /* rename devices that are s3c2412/s3c2413 specific */ 73 /* rename devices that are s3c2412/s3c2413 specific */
78 s3c_device_sdi.name = "s3c2412-sdi"; 74 s3c_device_sdi.name = "s3c2412-sdi";
75 s3c_device_lcd.name = "s3c2412-lcd";
79 s3c_device_nand.name = "s3c2412-nand"; 76 s3c_device_nand.name = "s3c2412-nand";
80} 77}
81 78
@@ -110,7 +107,7 @@ void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size)
110{ 107{
111 /* move base of IO */ 108 /* move base of IO */
112 109
113 s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10; 110 s3c2412_init_gpio2();
114 111
115 /* set our idle function */ 112 /* set our idle function */
116 113
@@ -161,48 +158,8 @@ void __init s3c2412_init_clocks(int xtal)
161 * as a driver which may support both 2410 and 2440 may try and use it. 158 * as a driver which may support both 2410 and 2440 may try and use it.
162*/ 159*/
163 160
164#ifdef CONFIG_PM
165static struct sleep_save s3c2412_sleep[] = {
166 SAVE_ITEM(S3C2412_DSC0),
167 SAVE_ITEM(S3C2412_DSC1),
168 SAVE_ITEM(S3C2413_GPJDAT),
169 SAVE_ITEM(S3C2413_GPJCON),
170 SAVE_ITEM(S3C2413_GPJUP),
171
172 /* save the sleep configuration anyway, just in case these
173 * get damaged during wakeup */
174
175 SAVE_ITEM(S3C2412_GPBSLPCON),
176 SAVE_ITEM(S3C2412_GPCSLPCON),
177 SAVE_ITEM(S3C2412_GPDSLPCON),
178 SAVE_ITEM(S3C2412_GPESLPCON),
179 SAVE_ITEM(S3C2412_GPFSLPCON),
180 SAVE_ITEM(S3C2412_GPGSLPCON),
181 SAVE_ITEM(S3C2412_GPHSLPCON),
182 SAVE_ITEM(S3C2413_GPJSLPCON),
183};
184
185static int s3c2412_suspend(struct sys_device *dev, pm_message_t state)
186{
187 s3c2410_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
188 return 0;
189}
190
191static int s3c2412_resume(struct sys_device *dev)
192{
193 s3c2410_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
194 return 0;
195}
196
197#else
198#define s3c2412_suspend NULL
199#define s3c2412_resume NULL
200#endif
201
202struct sysdev_class s3c2412_sysclass = { 161struct sysdev_class s3c2412_sysclass = {
203 set_kset_name("s3c2412-core"), 162 set_kset_name("s3c2412-core"),
204 .suspend = s3c2412_suspend,
205 .resume = s3c2412_resume
206}; 163};
207 164
208static int __init s3c2412_core_init(void) 165static int __init s3c2412_core_init(void)
diff --git a/arch/arm/mach-s3c2410/s3c2440-dma.c b/arch/arm/mach-s3c2410/s3c2440-dma.c
new file mode 100644
index 000000000000..11e109c84a15
--- /dev/null
+++ b/arch/arm/mach-s3c2410/s3c2440-dma.c
@@ -0,0 +1,164 @@
1/* linux/arch/arm/mach-s3c2410/s3c2440-dma.c
2 *
3 * (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2440 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/sysdev.h>
18
19#include <asm/dma.h>
20#include <asm/arch/dma.h>
21#include "dma.h"
22
23#include "cpu.h"
24
25#include <asm/arch/regs-serial.h>
26#include <asm/arch/regs-gpio.h>
27#include <asm/arch/regs-ac97.h>
28#include <asm/arch/regs-mem.h>
29#include <asm/arch/regs-lcd.h>
30#include <asm/arch/regs-sdi.h>
31#include <asm/arch/regs-iis.h>
32#include <asm/arch/regs-spi.h>
33
34static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
35 [DMACH_XD0] = {
36 .name = "xdreq0",
37 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
38 },
39 [DMACH_XD1] = {
40 .name = "xdreq1",
41 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
42 },
43 [DMACH_SDI] = {
44 .name = "sdi",
45 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
46 .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
47 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
48 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
49 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
50 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
51 },
52 [DMACH_SPI0] = {
53 .name = "spi0",
54 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
55 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
56 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
57 },
58 [DMACH_SPI1] = {
59 .name = "spi1",
60 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
61 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
62 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
63 },
64 [DMACH_UART0] = {
65 .name = "uart0",
66 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
67 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
68 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
69 },
70 [DMACH_UART1] = {
71 .name = "uart1",
72 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
73 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
74 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
75 },
76 [DMACH_UART2] = {
77 .name = "uart2",
78 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
79 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
80 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
81 },
82 [DMACH_TIMER] = {
83 .name = "timer",
84 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
85 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
86 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
87 },
88 [DMACH_I2S_IN] = {
89 .name = "i2s-sdi",
90 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
91 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
92 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
93 },
94 [DMACH_I2S_OUT] = {
95 .name = "i2s-sdo",
96 .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
97 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
98 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
99 },
100 [DMACH_PCM_IN] = {
101 .name = "pcm-in",
102 .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
103 .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
104 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
105 },
106 [DMACH_PCM_OUT] = {
107 .name = "pcm-out",
108 .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
109 .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
110 .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
111 },
112 [DMACH_MIC_IN] = {
113 .name = "mic-in",
114 .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
115 .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
116 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
117 },
118 [DMACH_USB_EP1] = {
119 .name = "usb-ep1",
120 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
121 },
122 [DMACH_USB_EP2] = {
123 .name = "usb-ep2",
124 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
125 },
126 [DMACH_USB_EP3] = {
127 .name = "usb-ep3",
128 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
129 },
130 [DMACH_USB_EP4] = {
131 .name = "usb-ep4",
132 .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
133 },
134};
135
136static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
137 struct s3c24xx_dma_map *map)
138{
139 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
140}
141
142static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
143 .select = s3c2440_dma_select,
144 .dcon_mask = 7 << 24,
145 .map = s3c2440_dma_mappings,
146 .map_size = ARRAY_SIZE(s3c2440_dma_mappings),
147};
148
149static int s3c2440_dma_add(struct sys_device *sysdev)
150{
151 return s3c24xx_dma_init_map(&s3c2440_dma_sel);
152}
153
154static struct sysdev_driver s3c2440_dma_driver = {
155 .add = s3c2440_dma_add,
156};
157
158static int __init s3c2440_dma_init(void)
159{
160 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_dma_driver);
161}
162
163arch_initcall(s3c2440_dma_init);
164
diff --git a/arch/arm/mach-s3c2410/s3c2440-dsc.c b/arch/arm/mach-s3c2410/s3c2440-dsc.c
index 16fa2a3b38fa..c92ea66ba45e 100644
--- a/arch/arm/mach-s3c2410/s3c2440-dsc.c
+++ b/arch/arm/mach-s3c2410/s3c2440-dsc.c
@@ -8,11 +8,6 @@
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 *
12 * Modifications:
13 * 29-Aug-2004 BJD Start of drive-strength control
14 * 09-Nov-2004 BJD Added symbol export
15 * 11-Jan-2005 BJD Include fix
16*/ 11*/
17 12
18#include <linux/kernel.h> 13#include <linux/kernel.h>
diff --git a/arch/arm/mach-s3c2410/s3c2440-irq.c b/arch/arm/mach-s3c2410/s3c2440-irq.c
index 1667ba1fa43d..fc08febe2e54 100644
--- a/arch/arm/mach-s3c2410/s3c2440-irq.c
+++ b/arch/arm/mach-s3c2410/s3c2440-irq.c
@@ -119,7 +119,7 @@ static int s3c2440_irq_add(struct sys_device *sysdev)
119} 119}
120 120
121static struct sysdev_driver s3c2440_irq_driver = { 121static struct sysdev_driver s3c2440_irq_driver = {
122 .add = s3c2440_irq_add, 122 .add = s3c2440_irq_add,
123}; 123};
124 124
125static int s3c2440_irq_init(void) 125static int s3c2440_irq_init(void)
diff --git a/arch/arm/mach-s3c2410/s3c244x-irq.c b/arch/arm/mach-s3c2410/s3c244x-irq.c
index 44c5affa9b89..0d13546c3500 100644
--- a/arch/arm/mach-s3c2410/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2410/s3c244x-irq.c
@@ -120,7 +120,9 @@ static int s3c244x_irq_add(struct sys_device *sysdev)
120} 120}
121 121
122static struct sysdev_driver s3c2440_irq_driver = { 122static struct sysdev_driver s3c2440_irq_driver = {
123 .add = s3c244x_irq_add, 123 .add = s3c244x_irq_add,
124 .suspend = s3c24xx_irq_suspend,
125 .resume = s3c24xx_irq_resume,
124}; 126};
125 127
126static int s3c2440_irq_init(void) 128static int s3c2440_irq_init(void)
@@ -131,9 +133,12 @@ static int s3c2440_irq_init(void)
131arch_initcall(s3c2440_irq_init); 133arch_initcall(s3c2440_irq_init);
132 134
133static struct sysdev_driver s3c2442_irq_driver = { 135static struct sysdev_driver s3c2442_irq_driver = {
134 .add = s3c244x_irq_add, 136 .add = s3c244x_irq_add,
137 .suspend = s3c24xx_irq_suspend,
138 .resume = s3c24xx_irq_resume,
135}; 139};
136 140
141
137static int s3c2442_irq_init(void) 142static int s3c2442_irq_init(void)
138{ 143{
139 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_irq_driver); 144 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_irq_driver);
diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
index a7561a79fc82..2018c2e1dcc5 100644
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c2410/sleep.S
@@ -41,15 +41,25 @@
41 41
42 .text 42 .text
43 43
44 /* s3c2410_cpu_suspend 44 /* s3c2410_cpu_save
45 * 45 *
46 * put the cpu into sleep mode 46 * save enough of the CPU state to allow us to re-start
47 * pm.c code. as we store items like the sp/lr, we will
48 * end up returning from this function when the cpu resumes
49 * so the return value is set to mark this.
50 *
51 * This arangement means we avoid having to flush the cache
52 * from this code.
47 * 53 *
48 * entry: 54 * entry:
49 * r0 = sleep save block 55 * r0 = pointer to save block
56 *
57 * exit:
58 * r0 = 0 => we stored everything
59 * 1 => resumed from sleep
50 */ 60 */
51 61
52ENTRY(s3c2410_cpu_suspend) 62ENTRY(s3c2410_cpu_save)
53 stmfd sp!, { r4 - r12, lr } 63 stmfd sp!, { r4 - r12, lr }
54 64
55 @@ store co-processor registers 65 @@ store co-processor registers
@@ -62,44 +72,14 @@ ENTRY(s3c2410_cpu_suspend)
62 72
63 stmia r0, { r4 - r13 } 73 stmia r0, { r4 - r13 }
64 74
65 @@ flush the caches to ensure everything is back out to 75 mov r0, #0
66 @@ SDRAM before the core powers down 76 ldmfd sp, { r4 - r12, pc }
67
68#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
69 bl arm920_flush_kern_cache_all
70#endif
71
72 @@ prepare cpu to sleep
73
74 ldr r4, =S3C2410_REFRESH
75 ldr r5, =S3C24XX_MISCCR
76 ldr r6, =S3C2410_CLKCON
77 ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB)
78 ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB)
79 ldr r9, [ r6 ] @ get CLKCON (and ensure in TLB)
80
81 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
82 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
83 orr r9, r9, #S3C2410_CLKCON_POWER @ power down command
84
85 teq pc, #0 @ first as a trial-run to load cache
86 bl s3c2410_do_sleep
87 teq r0, r0 @ now do it for real
88 b s3c2410_do_sleep @
89
90 @@ align next bit of code to cache line
91 .align 8
92s3c2410_do_sleep:
93 streq r7, [ r4 ] @ SDRAM sleep command
94 streq r8, [ r5 ] @ SDRAM power-down config
95 streq r9, [ r6 ] @ CPU sleep
961: beq 1b
97 mov pc, r14
98 77
99 @@ return to the caller, after having the MMU 78 @@ return to the caller, after having the MMU
100 @@ turned on, this restores the last bits from the 79 @@ turned on, this restores the last bits from the
101 @@ stack 80 @@ stack
102resume_with_mmu: 81resume_with_mmu:
82 mov r0, #1
103 ldmfd sp!, { r4 - r12, pc } 83 ldmfd sp!, { r4 - r12, pc }
104 84
105 .ltorg 85 .ltorg
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c
index 6b22d8f0a00d..c635efa7cd31 100644
--- a/arch/arm/mach-s3c2410/usb-simtec.c
+++ b/arch/arm/mach-s3c2410/usb-simtec.c
@@ -10,12 +10,6 @@
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 *
14 * Modifications:
15 * 14-Sep-2004 BJD Created
16 * 18-Oct-2004 BJD Cleanups, and added code to report OC cleared
17 * 09-Aug-2005 BJD Renamed s3c2410_report_oc to s3c2410_usb_report_oc
18 * 09-Aug-2005 BJD Ports powered only if both are enabled
19*/ 13*/
20 14
21#define DEBUG 15#define DEBUG
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index a0dfa390e34b..6496eb645cee 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -91,30 +91,29 @@ static struct mcp_plat_data collie_mcp_data = {
91/* 91/*
92 * low-level UART features. 92 * low-level UART features.
93 */ 93 */
94static struct locomo_dev *uart_dev = NULL; 94struct platform_device collie_locomo_device;
95 95
96static void collie_uart_set_mctrl(struct uart_port *port, u_int mctrl) 96static void collie_uart_set_mctrl(struct uart_port *port, u_int mctrl)
97{ 97{
98 if (!uart_dev) return;
99
100 if (mctrl & TIOCM_RTS) 98 if (mctrl & TIOCM_RTS)
101 locomo_gpio_write(uart_dev, LOCOMO_GPIO_RTS, 0); 99 locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 0);
102 else 100 else
103 locomo_gpio_write(uart_dev, LOCOMO_GPIO_RTS, 1); 101 locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 1);
104 102
105 if (mctrl & TIOCM_DTR) 103 if (mctrl & TIOCM_DTR)
106 locomo_gpio_write(uart_dev, LOCOMO_GPIO_DTR, 0); 104 locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 0);
107 else 105 else
108 locomo_gpio_write(uart_dev, LOCOMO_GPIO_DTR, 1); 106 locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 1);
109} 107}
110 108
111static u_int collie_uart_get_mctrl(struct uart_port *port) 109static u_int collie_uart_get_mctrl(struct uart_port *port)
112{ 110{
113 int ret = TIOCM_CD; 111 int ret = TIOCM_CD;
114 unsigned int r; 112 unsigned int r;
115 if (!uart_dev) return ret;
116 113
117 r = locomo_gpio_read_output(uart_dev, LOCOMO_GPIO_CTS & LOCOMO_GPIO_DSR); 114 r = locomo_gpio_read_output(&collie_locomo_device.dev, LOCOMO_GPIO_CTS & LOCOMO_GPIO_DSR);
115 if (r == -ENODEV)
116 return ret;
118 if (r & LOCOMO_GPIO_CTS) 117 if (r & LOCOMO_GPIO_CTS)
119 ret |= TIOCM_CTS; 118 ret |= TIOCM_CTS;
120 if (r & LOCOMO_GPIO_DSR) 119 if (r & LOCOMO_GPIO_DSR)
@@ -130,13 +129,11 @@ static struct sa1100_port_fns collie_port_fns __initdata = {
130 129
131static int collie_uart_probe(struct locomo_dev *dev) 130static int collie_uart_probe(struct locomo_dev *dev)
132{ 131{
133 uart_dev = dev;
134 return 0; 132 return 0;
135} 133}
136 134
137static int collie_uart_remove(struct locomo_dev *dev) 135static int collie_uart_remove(struct locomo_dev *dev)
138{ 136{
139 uart_dev = NULL;
140 return 0; 137 return 0;
141} 138}
142 139
@@ -170,7 +167,7 @@ static struct resource locomo_resources[] = {
170 }, 167 },
171}; 168};
172 169
173static struct platform_device locomo_device = { 170struct platform_device collie_locomo_device = {
174 .name = "locomo", 171 .name = "locomo",
175 .id = 0, 172 .id = 0,
176 .num_resources = ARRAY_SIZE(locomo_resources), 173 .num_resources = ARRAY_SIZE(locomo_resources),
@@ -178,7 +175,7 @@ static struct platform_device locomo_device = {
178}; 175};
179 176
180static struct platform_device *devices[] __initdata = { 177static struct platform_device *devices[] __initdata = {
181 &locomo_device, 178 &collie_locomo_device,
182 &colliescoop_device, 179 &colliescoop_device,
183}; 180};
184 181
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 41b370090b60..13bbd08ff841 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -117,7 +117,6 @@ static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int wh
117 } else { 117 } else {
118 switch (size) { 118 switch (size) {
119 case 1: 119 case 1:
120 addr &= ~3;
121 v = __raw_readb(addr); 120 v = __raw_readb(addr);
122 break; 121 break;
123 122
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index b4f220dd5eb8..c0bfb8212b77 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -15,6 +15,7 @@ config CPU_ARM610
15 select CPU_32v3 15 select CPU_32v3
16 select CPU_CACHE_V3 16 select CPU_CACHE_V3
17 select CPU_CACHE_VIVT 17 select CPU_CACHE_VIVT
18 select CPU_CP15_MMU
18 select CPU_COPY_V3 if MMU 19 select CPU_COPY_V3 if MMU
19 select CPU_TLB_V3 if MMU 20 select CPU_TLB_V3 if MMU
20 help 21 help
@@ -24,6 +25,20 @@ config CPU_ARM610
24 Say Y if you want support for the ARM610 processor. 25 Say Y if you want support for the ARM610 processor.
25 Otherwise, say N. 26 Otherwise, say N.
26 27
28# ARM7TDMI
29config CPU_ARM7TDMI
30 bool "Support ARM7TDMI processor"
31 depends on !MMU
32 select CPU_32v4T
33 select CPU_ABRT_LV4T
34 select CPU_CACHE_V4
35 help
36 A 32-bit RISC microprocessor based on the ARM7 processor core
37 which has no memory control unit and cache.
38
39 Say Y if you want support for the ARM7TDMI processor.
40 Otherwise, say N.
41
27# ARM710 42# ARM710
28config CPU_ARM710 43config CPU_ARM710
29 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC 44 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
@@ -31,6 +46,7 @@ config CPU_ARM710
31 select CPU_32v3 46 select CPU_32v3
32 select CPU_CACHE_V3 47 select CPU_CACHE_V3
33 select CPU_CACHE_VIVT 48 select CPU_CACHE_VIVT
49 select CPU_CP15_MMU
34 select CPU_COPY_V3 if MMU 50 select CPU_COPY_V3 if MMU
35 select CPU_TLB_V3 if MMU 51 select CPU_TLB_V3 if MMU
36 help 52 help
@@ -50,6 +66,7 @@ config CPU_ARM720T
50 select CPU_ABRT_LV4T 66 select CPU_ABRT_LV4T
51 select CPU_CACHE_V4 67 select CPU_CACHE_V4
52 select CPU_CACHE_VIVT 68 select CPU_CACHE_VIVT
69 select CPU_CP15_MMU
53 select CPU_COPY_V4WT if MMU 70 select CPU_COPY_V4WT if MMU
54 select CPU_TLB_V4WT if MMU 71 select CPU_TLB_V4WT if MMU
55 help 72 help
@@ -59,6 +76,36 @@ config CPU_ARM720T
59 Say Y if you want support for the ARM720T processor. 76 Say Y if you want support for the ARM720T processor.
60 Otherwise, say N. 77 Otherwise, say N.
61 78
79# ARM740T
80config CPU_ARM740T
81 bool "Support ARM740T processor" if ARCH_INTEGRATOR
82 depends on !MMU
83 select CPU_32v4T
84 select CPU_ABRT_LV4T
85 select CPU_CACHE_V3 # although the core is v4t
86 select CPU_CP15_MPU
87 help
88 A 32-bit RISC processor with 8KB cache or 4KB variants,
89 write buffer and MPU(Protection Unit) built around
90 an ARM7TDMI core.
91
92 Say Y if you want support for the ARM740T processor.
93 Otherwise, say N.
94
95# ARM9TDMI
96config CPU_ARM9TDMI
97 bool "Support ARM9TDMI processor"
98 depends on !MMU
99 select CPU_32v4T
100 select CPU_ABRT_NOMMU
101 select CPU_CACHE_V4
102 help
103 A 32-bit RISC microprocessor based on the ARM9 processor core
104 which has no memory control unit and cache.
105
106 Say Y if you want support for the ARM9TDMI processor.
107 Otherwise, say N.
108
62# ARM920T 109# ARM920T
63config CPU_ARM920T 110config CPU_ARM920T
64 bool "Support ARM920T processor" 111 bool "Support ARM920T processor"
@@ -68,6 +115,7 @@ config CPU_ARM920T
68 select CPU_ABRT_EV4T 115 select CPU_ABRT_EV4T
69 select CPU_CACHE_V4WT 116 select CPU_CACHE_V4WT
70 select CPU_CACHE_VIVT 117 select CPU_CACHE_VIVT
118 select CPU_CP15_MMU
71 select CPU_COPY_V4WB if MMU 119 select CPU_COPY_V4WB if MMU
72 select CPU_TLB_V4WBI if MMU 120 select CPU_TLB_V4WBI if MMU
73 help 121 help
@@ -89,6 +137,7 @@ config CPU_ARM922T
89 select CPU_ABRT_EV4T 137 select CPU_ABRT_EV4T
90 select CPU_CACHE_V4WT 138 select CPU_CACHE_V4WT
91 select CPU_CACHE_VIVT 139 select CPU_CACHE_VIVT
140 select CPU_CP15_MMU
92 select CPU_COPY_V4WB if MMU 141 select CPU_COPY_V4WB if MMU
93 select CPU_TLB_V4WBI if MMU 142 select CPU_TLB_V4WBI if MMU
94 help 143 help
@@ -108,6 +157,7 @@ config CPU_ARM925T
108 select CPU_ABRT_EV4T 157 select CPU_ABRT_EV4T
109 select CPU_CACHE_V4WT 158 select CPU_CACHE_V4WT
110 select CPU_CACHE_VIVT 159 select CPU_CACHE_VIVT
160 select CPU_CP15_MMU
111 select CPU_COPY_V4WB if MMU 161 select CPU_COPY_V4WB if MMU
112 select CPU_TLB_V4WBI if MMU 162 select CPU_TLB_V4WBI if MMU
113 help 163 help
@@ -126,6 +176,7 @@ config CPU_ARM926T
126 select CPU_32v5 176 select CPU_32v5
127 select CPU_ABRT_EV5TJ 177 select CPU_ABRT_EV5TJ
128 select CPU_CACHE_VIVT 178 select CPU_CACHE_VIVT
179 select CPU_CP15_MMU
129 select CPU_COPY_V4WB if MMU 180 select CPU_COPY_V4WB if MMU
130 select CPU_TLB_V4WBI if MMU 181 select CPU_TLB_V4WBI if MMU
131 help 182 help
@@ -136,6 +187,39 @@ config CPU_ARM926T
136 Say Y if you want support for the ARM926T processor. 187 Say Y if you want support for the ARM926T processor.
137 Otherwise, say N. 188 Otherwise, say N.
138 189
190# ARM940T
191config CPU_ARM940T
192 bool "Support ARM940T processor" if ARCH_INTEGRATOR
193 depends on !MMU
194 select CPU_32v4T
195 select CPU_ABRT_NOMMU
196 select CPU_CACHE_VIVT
197 select CPU_CP15_MPU
198 help
199 ARM940T is a member of the ARM9TDMI family of general-
200 purpose microprocessors with MPU and seperate 4KB
201 instruction and 4KB data cases, each with a 4-word line
202 length.
203
204 Say Y if you want support for the ARM940T processor.
205 Otherwise, say N.
206
207# ARM946E-S
208config CPU_ARM946E
209 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
210 depends on !MMU
211 select CPU_32v5
212 select CPU_ABRT_NOMMU
213 select CPU_CACHE_VIVT
214 select CPU_CP15_MPU
215 help
216 ARM946E-S is a member of the ARM9E-S family of high-
217 performance, 32-bit system-on-chip processor solutions.
218 The TCM and ARMv5TE 32-bit instruction set is supported.
219
220 Say Y if you want support for the ARM946E-S processor.
221 Otherwise, say N.
222
139# ARM1020 - needs validating 223# ARM1020 - needs validating
140config CPU_ARM1020 224config CPU_ARM1020
141 bool "Support ARM1020T (rev 0) processor" 225 bool "Support ARM1020T (rev 0) processor"
@@ -144,6 +228,7 @@ config CPU_ARM1020
144 select CPU_ABRT_EV4T 228 select CPU_ABRT_EV4T
145 select CPU_CACHE_V4WT 229 select CPU_CACHE_V4WT
146 select CPU_CACHE_VIVT 230 select CPU_CACHE_VIVT
231 select CPU_CP15_MMU
147 select CPU_COPY_V4WB if MMU 232 select CPU_COPY_V4WB if MMU
148 select CPU_TLB_V4WBI if MMU 233 select CPU_TLB_V4WBI if MMU
149 help 234 help
@@ -161,6 +246,7 @@ config CPU_ARM1020E
161 select CPU_ABRT_EV4T 246 select CPU_ABRT_EV4T
162 select CPU_CACHE_V4WT 247 select CPU_CACHE_V4WT
163 select CPU_CACHE_VIVT 248 select CPU_CACHE_VIVT
249 select CPU_CP15_MMU
164 select CPU_COPY_V4WB if MMU 250 select CPU_COPY_V4WB if MMU
165 select CPU_TLB_V4WBI if MMU 251 select CPU_TLB_V4WBI if MMU
166 depends on n 252 depends on n
@@ -172,6 +258,7 @@ config CPU_ARM1022
172 select CPU_32v5 258 select CPU_32v5
173 select CPU_ABRT_EV4T 259 select CPU_ABRT_EV4T
174 select CPU_CACHE_VIVT 260 select CPU_CACHE_VIVT
261 select CPU_CP15_MMU
175 select CPU_COPY_V4WB if MMU # can probably do better 262 select CPU_COPY_V4WB if MMU # can probably do better
176 select CPU_TLB_V4WBI if MMU 263 select CPU_TLB_V4WBI if MMU
177 help 264 help
@@ -189,6 +276,7 @@ config CPU_ARM1026
189 select CPU_32v5 276 select CPU_32v5
190 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 277 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
191 select CPU_CACHE_VIVT 278 select CPU_CACHE_VIVT
279 select CPU_CP15_MMU
192 select CPU_COPY_V4WB if MMU # can probably do better 280 select CPU_COPY_V4WB if MMU # can probably do better
193 select CPU_TLB_V4WBI if MMU 281 select CPU_TLB_V4WBI if MMU
194 help 282 help
@@ -207,6 +295,7 @@ config CPU_SA110
207 select CPU_ABRT_EV4 295 select CPU_ABRT_EV4
208 select CPU_CACHE_V4WB 296 select CPU_CACHE_V4WB
209 select CPU_CACHE_VIVT 297 select CPU_CACHE_VIVT
298 select CPU_CP15_MMU
210 select CPU_COPY_V4WB if MMU 299 select CPU_COPY_V4WB if MMU
211 select CPU_TLB_V4WB if MMU 300 select CPU_TLB_V4WB if MMU
212 help 301 help
@@ -227,16 +316,18 @@ config CPU_SA1100
227 select CPU_ABRT_EV4 316 select CPU_ABRT_EV4
228 select CPU_CACHE_V4WB 317 select CPU_CACHE_V4WB
229 select CPU_CACHE_VIVT 318 select CPU_CACHE_VIVT
319 select CPU_CP15_MMU
230 select CPU_TLB_V4WB if MMU 320 select CPU_TLB_V4WB if MMU
231 321
232# XScale 322# XScale
233config CPU_XSCALE 323config CPU_XSCALE
234 bool 324 bool
235 depends on ARCH_IOP3XX || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000 325 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
236 default y 326 default y
237 select CPU_32v5 327 select CPU_32v5
238 select CPU_ABRT_EV5T 328 select CPU_ABRT_EV5T
239 select CPU_CACHE_VIVT 329 select CPU_CACHE_VIVT
330 select CPU_CP15_MMU
240 select CPU_TLB_V4WBI if MMU 331 select CPU_TLB_V4WBI if MMU
241 332
242# XScale Core Version 3 333# XScale Core Version 3
@@ -247,6 +338,7 @@ config CPU_XSC3
247 select CPU_32v5 338 select CPU_32v5
248 select CPU_ABRT_EV5T 339 select CPU_ABRT_EV5T
249 select CPU_CACHE_VIVT 340 select CPU_CACHE_VIVT
341 select CPU_CP15_MMU
250 select CPU_TLB_V4WBI if MMU 342 select CPU_TLB_V4WBI if MMU
251 select IO_36 343 select IO_36
252 344
@@ -258,6 +350,7 @@ config CPU_V6
258 select CPU_ABRT_EV6 350 select CPU_ABRT_EV6
259 select CPU_CACHE_V6 351 select CPU_CACHE_V6
260 select CPU_CACHE_VIPT 352 select CPU_CACHE_VIPT
353 select CPU_CP15_MMU
261 select CPU_COPY_V6 if MMU 354 select CPU_COPY_V6 if MMU
262 select CPU_TLB_V6 if MMU 355 select CPU_TLB_V6 if MMU
263 356
@@ -299,6 +392,9 @@ config CPU_32v6
299 bool 392 bool
300 393
301# The abort model 394# The abort model
395config CPU_ABRT_NOMMU
396 bool
397
302config CPU_ABRT_EV4 398config CPU_ABRT_EV4
303 bool 399 bool
304 400
@@ -380,6 +476,23 @@ config CPU_TLB_V6
380 476
381endif 477endif
382 478
479config CPU_CP15
480 bool
481 help
482 Processor has the CP15 register.
483
484config CPU_CP15_MMU
485 bool
486 select CPU_CP15
487 help
488 Processor has the CP15 register, which has MMU related registers.
489
490config CPU_CP15_MPU
491 bool
492 select CPU_CP15
493 help
494 Processor has the CP15 register, which has MPU related registers.
495
383# 496#
384# CPU supports 36-bit I/O 497# CPU supports 36-bit I/O
385# 498#
@@ -390,7 +503,7 @@ comment "Processor Features"
390 503
391config ARM_THUMB 504config ARM_THUMB
392 bool "Support Thumb user binaries" 505 bool "Support Thumb user binaries"
393 depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 506 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
394 default y 507 default y
395 help 508 help
396 Say Y if you want to include kernel support for running user space 509 Say Y if you want to include kernel support for running user space
@@ -411,23 +524,48 @@ config CPU_BIG_ENDIAN
411 port must properly enable any big-endian related features 524 port must properly enable any big-endian related features
412 of your chipset/board/processor. 525 of your chipset/board/processor.
413 526
527config CPU_HIGH_VECTOR
528 depends !MMU && CPU_CP15 && !CPU_ARM740T
529 bool "Select the High exception vector"
530 default n
531 help
532 Say Y here to select high exception vector(0xFFFF0000~).
533 The exception vector can be vary depending on the platform
534 design in nommu mode. If your platform needs to select
535 high exception vector, say Y.
536 Otherwise or if you are unsure, say N, and the low exception
537 vector (0x00000000~) will be used.
538
414config CPU_ICACHE_DISABLE 539config CPU_ICACHE_DISABLE
415 bool "Disable I-Cache" 540 bool "Disable I-Cache (I-bit)"
416 depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6 541 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
417 help 542 help
418 Say Y here to disable the processor instruction cache. Unless 543 Say Y here to disable the processor instruction cache. Unless
419 you have a reason not to or are unsure, say N. 544 you have a reason not to or are unsure, say N.
420 545
421config CPU_DCACHE_DISABLE 546config CPU_DCACHE_DISABLE
422 bool "Disable D-Cache" 547 bool "Disable D-Cache (C-bit)"
423 depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6 548 depends on CPU_CP15
424 help 549 help
425 Say Y here to disable the processor data cache. Unless 550 Say Y here to disable the processor data cache. Unless
426 you have a reason not to or are unsure, say N. 551 you have a reason not to or are unsure, say N.
427 552
553config CPU_DCACHE_SIZE
554 hex
555 depends on CPU_ARM740T || CPU_ARM946E
556 default 0x00001000 if CPU_ARM740T
557 default 0x00002000 # default size for ARM946E-S
558 help
559 Some cores are synthesizable to have various sized cache. For
560 ARM946E-S case, it can vary from 0KB to 1MB.
561 To support such cache operations, it is efficient to know the size
562 before compile time.
563 If your SoC is configured to have a different size, define the value
564 here with proper conditions.
565
428config CPU_DCACHE_WRITETHROUGH 566config CPU_DCACHE_WRITETHROUGH
429 bool "Force write through D-cache" 567 bool "Force write through D-cache"
430 depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE 568 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
431 default y if CPU_ARM925T 569 default y if CPU_ARM925T
432 help 570 help
433 Say Y here to use the data cache in writethrough mode. Unless you 571 Say Y here to use the data cache in writethrough mode. Unless you
@@ -435,7 +573,7 @@ config CPU_DCACHE_WRITETHROUGH
435 573
436config CPU_CACHE_ROUND_ROBIN 574config CPU_CACHE_ROUND_ROBIN
437 bool "Round robin I and D cache replacement algorithm" 575 bool "Round robin I and D cache replacement algorithm"
438 depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) 576 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
439 help 577 help
440 Say Y here to use the predictable round-robin cache replacement 578 Say Y here to use the predictable round-robin cache replacement
441 policy. Unless you specifically require this or are unsure, say N. 579 policy. Unless you specifically require this or are unsure, say N.
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 21a2770226ee..d2f5672ecf62 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -6,7 +6,7 @@ obj-y := consistent.o extable.o fault.o init.o \
6 iomap.o 6 iomap.o
7 7
8obj-$(CONFIG_MMU) += fault-armv.o flush.o ioremap.o mmap.o \ 8obj-$(CONFIG_MMU) += fault-armv.o flush.o ioremap.o mmap.o \
9 mm-armv.o 9 pgd.o mmu.o
10 10
11ifneq ($(CONFIG_MMU),y) 11ifneq ($(CONFIG_MMU),y)
12obj-y += nommu.o 12obj-y += nommu.o
@@ -17,6 +17,7 @@ obj-$(CONFIG_MODULES) += proc-syms.o
17obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o 17obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o
18obj-$(CONFIG_DISCONTIGMEM) += discontig.o 18obj-$(CONFIG_DISCONTIGMEM) += discontig.o
19 19
20obj-$(CONFIG_CPU_ABRT_NOMMU) += abort-nommu.o
20obj-$(CONFIG_CPU_ABRT_EV4) += abort-ev4.o 21obj-$(CONFIG_CPU_ABRT_EV4) += abort-ev4.o
21obj-$(CONFIG_CPU_ABRT_EV4T) += abort-ev4t.o 22obj-$(CONFIG_CPU_ABRT_EV4T) += abort-ev4t.o
22obj-$(CONFIG_CPU_ABRT_LV4T) += abort-lv4t.o 23obj-$(CONFIG_CPU_ABRT_LV4T) += abort-lv4t.o
@@ -33,7 +34,7 @@ obj-$(CONFIG_CPU_CACHE_V6) += cache-v6.o
33obj-$(CONFIG_CPU_COPY_V3) += copypage-v3.o 34obj-$(CONFIG_CPU_COPY_V3) += copypage-v3.o
34obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o 35obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o
35obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o 36obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o
36obj-$(CONFIG_CPU_COPY_V6) += copypage-v6.o mmu.o 37obj-$(CONFIG_CPU_COPY_V6) += copypage-v6.o context.o
37obj-$(CONFIG_CPU_SA1100) += copypage-v4mc.o 38obj-$(CONFIG_CPU_SA1100) += copypage-v4mc.o
38obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o 39obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o
39obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o 40obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o
@@ -46,11 +47,16 @@ obj-$(CONFIG_CPU_TLB_V6) += tlb-v6.o
46 47
47obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o 48obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o
48obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o 49obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o
50obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o
49obj-$(CONFIG_CPU_ARM720T) += proc-arm720.o 51obj-$(CONFIG_CPU_ARM720T) += proc-arm720.o
52obj-$(CONFIG_CPU_ARM740T) += proc-arm740.o
53obj-$(CONFIG_CPU_ARM9TDMI) += proc-arm9tdmi.o
50obj-$(CONFIG_CPU_ARM920T) += proc-arm920.o 54obj-$(CONFIG_CPU_ARM920T) += proc-arm920.o
51obj-$(CONFIG_CPU_ARM922T) += proc-arm922.o 55obj-$(CONFIG_CPU_ARM922T) += proc-arm922.o
52obj-$(CONFIG_CPU_ARM925T) += proc-arm925.o 56obj-$(CONFIG_CPU_ARM925T) += proc-arm925.o
53obj-$(CONFIG_CPU_ARM926T) += proc-arm926.o 57obj-$(CONFIG_CPU_ARM926T) += proc-arm926.o
58obj-$(CONFIG_CPU_ARM940T) += proc-arm940.o
59obj-$(CONFIG_CPU_ARM946E) += proc-arm946.o
54obj-$(CONFIG_CPU_ARM1020) += proc-arm1020.o 60obj-$(CONFIG_CPU_ARM1020) += proc-arm1020.o
55obj-$(CONFIG_CPU_ARM1020E) += proc-arm1020e.o 61obj-$(CONFIG_CPU_ARM1020E) += proc-arm1020e.o
56obj-$(CONFIG_CPU_ARM1022) += proc-arm1022.o 62obj-$(CONFIG_CPU_ARM1022) += proc-arm1022.o
diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
index db743e510214..9fb7b0e25ea1 100644
--- a/arch/arm/mm/abort-lv4t.S
+++ b/arch/arm/mm/abort-lv4t.S
@@ -19,11 +19,16 @@
19 */ 19 */
20ENTRY(v4t_late_abort) 20ENTRY(v4t_late_abort)
21 tst r3, #PSR_T_BIT @ check for thumb mode 21 tst r3, #PSR_T_BIT @ check for thumb mode
22#ifdef CONFIG_CPU_CP15_MMU
22 mrc p15, 0, r1, c5, c0, 0 @ get FSR 23 mrc p15, 0, r1, c5, c0, 0 @ get FSR
23 mrc p15, 0, r0, c6, c0, 0 @ get FAR 24 mrc p15, 0, r0, c6, c0, 0 @ get FAR
25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
26#else
27 mov r0, #0 @ clear r0, r1 (no FSR/FAR)
28 mov r1, #0
29#endif
24 bne .data_thumb_abort 30 bne .data_thumb_abort
25 ldr r8, [r2] @ read arm instruction 31 ldr r8, [r2] @ read arm instruction
26 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
27 tst r8, #1 << 20 @ L = 1 -> write? 32 tst r8, #1 << 20 @ L = 1 -> write?
28 orreq r1, r1, #1 << 11 @ yes. 33 orreq r1, r1, #1 << 11 @ yes.
29 and r7, r8, #15 << 24 34 and r7, r8, #15 << 24
diff --git a/arch/arm/mm/abort-nommu.S b/arch/arm/mm/abort-nommu.S
new file mode 100644
index 000000000000..a7cc7f9ee45d
--- /dev/null
+++ b/arch/arm/mm/abort-nommu.S
@@ -0,0 +1,19 @@
1#include <linux/linkage.h>
2#include <asm/assembler.h>
3/*
4 * Function: nommu_early_abort
5 *
6 * Params : r2 = address of aborted instruction
7 * : r3 = saved SPSR
8 *
9 * Returns : r0 = 0 (abort address)
10 * : r1 = 0 (FSR)
11 *
12 * Note: There is no FSR/FAR on !CPU_CP15_MMU cores.
13 * Just fill zero into the registers.
14 */
15 .align 5
16ENTRY(nommu_early_abort)
17 mov r0, #0 @ clear r0, r1 (no FSR/FAR)
18 mov r1, #0
19 mov pc, lr
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index e0d21bbbe7d7..aa109f074dd9 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -735,7 +735,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
735 /* 735 /*
736 * We got a fault - fix it up, or die. 736 * We got a fault - fix it up, or die.
737 */ 737 */
738 do_bad_area(current, current->mm, addr, fsr, regs); 738 do_bad_area(addr, fsr, regs);
739 return 0; 739 return 0;
740 740
741 swp: 741 swp:
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index b8ad5d58ebe2..b2908063ed6a 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -29,9 +29,13 @@ ENTRY(v4_flush_user_cache_all)
29 * Clean and invalidate the entire cache. 29 * Clean and invalidate the entire cache.
30 */ 30 */
31ENTRY(v4_flush_kern_cache_all) 31ENTRY(v4_flush_kern_cache_all)
32#ifdef CPU_CP15
32 mov r0, #0 33 mov r0, #0
33 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache 34 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
34 mov pc, lr 35 mov pc, lr
36#else
37 /* FALLTHROUGH */
38#endif
35 39
36/* 40/*
37 * flush_user_cache_range(start, end, flags) 41 * flush_user_cache_range(start, end, flags)
@@ -44,9 +48,13 @@ ENTRY(v4_flush_kern_cache_all)
44 * - flags - vma_area_struct flags describing address space 48 * - flags - vma_area_struct flags describing address space
45 */ 49 */
46ENTRY(v4_flush_user_cache_range) 50ENTRY(v4_flush_user_cache_range)
51#ifdef CPU_CP15
47 mov ip, #0 52 mov ip, #0
48 mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache 53 mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache
49 mov pc, lr 54 mov pc, lr
55#else
56 /* FALLTHROUGH */
57#endif
50 58
51/* 59/*
52 * coherent_kern_range(start, end) 60 * coherent_kern_range(start, end)
@@ -108,8 +116,10 @@ ENTRY(v4_dma_inv_range)
108 * - end - virtual end address 116 * - end - virtual end address
109 */ 117 */
110ENTRY(v4_dma_flush_range) 118ENTRY(v4_dma_flush_range)
119#ifdef CPU_CP15
111 mov r0, #0 120 mov r0, #0
112 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache 121 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
122#endif
113 /* FALLTHROUGH */ 123 /* FALLTHROUGH */
114 124
115/* 125/*
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
new file mode 100644
index 000000000000..79e800202424
--- /dev/null
+++ b/arch/arm/mm/context.c
@@ -0,0 +1,45 @@
1/*
2 * linux/arch/arm/mm/context.c
3 *
4 * Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/init.h>
11#include <linux/sched.h>
12#include <linux/mm.h>
13
14#include <asm/mmu_context.h>
15#include <asm/tlbflush.h>
16
17unsigned int cpu_last_asid = { 1 << ASID_BITS };
18
19/*
20 * We fork()ed a process, and we need a new context for the child
21 * to run in. We reserve version 0 for initial tasks so we will
22 * always allocate an ASID.
23 */
24void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
25{
26 mm->context.id = 0;
27}
28
29void __new_context(struct mm_struct *mm)
30{
31 unsigned int asid;
32
33 asid = ++cpu_last_asid;
34 if (asid == 0)
35 asid = cpu_last_asid = 1 << ASID_BITS;
36
37 /*
38 * If we've used up all our ASIDs, we need
39 * to start a new version and flush the TLB.
40 */
41 if ((asid & ~ASID_MASK) == 0)
42 flush_tlb_all();
43
44 mm->context.id = asid;
45}
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index fc69dccdace1..df1645e14b4c 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -20,6 +20,8 @@
20#include <asm/pgtable.h> 20#include <asm/pgtable.h>
21#include <asm/tlbflush.h> 21#include <asm/tlbflush.h>
22 22
23#include "mm.h"
24
23/* 25/*
24 * 0xffff8000 to 0xffffffff is reserved for any ARM architecture 26 * 0xffff8000 to 0xffffffff is reserved for any ARM architecture
25 * specific hacks for copying pages efficiently. 27 * specific hacks for copying pages efficiently.
@@ -27,8 +29,6 @@
27#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \ 29#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
28 L_PTE_CACHEABLE) 30 L_PTE_CACHEABLE)
29 31
30#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)
31
32static DEFINE_SPINLOCK(minicache_lock); 32static DEFINE_SPINLOCK(minicache_lock);
33 33
34/* 34/*
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 269ce6913ee9..3d0d3a963d20 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -17,6 +17,8 @@
17#include <asm/tlbflush.h> 17#include <asm/tlbflush.h>
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19 19
20#include "mm.h"
21
20#if SHMLBA > 16384 22#if SHMLBA > 16384
21#error FIX ME 23#error FIX ME
22#endif 24#endif
@@ -24,8 +26,6 @@
24#define from_address (0xffff8000) 26#define from_address (0xffff8000)
25#define to_address (0xffffc000) 27#define to_address (0xffffc000)
26 28
27#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)
28
29static DEFINE_SPINLOCK(v6_lock); 29static DEFINE_SPINLOCK(v6_lock);
30 30
31/* 31/*
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 42a6ee255ce0..84ebe0aa379e 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -20,6 +20,8 @@
20#include <asm/pgtable.h> 20#include <asm/pgtable.h>
21#include <asm/tlbflush.h> 21#include <asm/tlbflush.h>
22 22
23#include "mm.h"
24
23/* 25/*
24 * 0xffff8000 to 0xffffffff is reserved for any ARM architecture 26 * 0xffff8000 to 0xffffffff is reserved for any ARM architecture
25 * specific hacks for copying pages efficiently. 27 * specific hacks for copying pages efficiently.
@@ -29,8 +31,6 @@
29#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \ 31#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
30 L_PTE_CACHEABLE) 32 L_PTE_CACHEABLE)
31 33
32#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)
33
34static DEFINE_SPINLOCK(minicache_lock); 34static DEFINE_SPINLOCK(minicache_lock);
35 35
36/* 36/*
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index c5e0622c7765..f0943d160ffe 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -131,10 +131,11 @@ __do_user_fault(struct task_struct *tsk, unsigned long addr,
131 force_sig_info(sig, &si, tsk); 131 force_sig_info(sig, &si, tsk);
132} 132}
133 133
134void 134void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
135do_bad_area(struct task_struct *tsk, struct mm_struct *mm, unsigned long addr,
136 unsigned int fsr, struct pt_regs *regs)
137{ 135{
136 struct task_struct *tsk = current;
137 struct mm_struct *mm = tsk->active_mm;
138
138 /* 139 /*
139 * If we are in kernel mode at this point, we 140 * If we are in kernel mode at this point, we
140 * have no context to handle this fault with. 141 * have no context to handle this fault with.
@@ -319,7 +320,6 @@ static int
319do_translation_fault(unsigned long addr, unsigned int fsr, 320do_translation_fault(unsigned long addr, unsigned int fsr,
320 struct pt_regs *regs) 321 struct pt_regs *regs)
321{ 322{
322 struct task_struct *tsk;
323 unsigned int index; 323 unsigned int index;
324 pgd_t *pgd, *pgd_k; 324 pgd_t *pgd, *pgd_k;
325 pmd_t *pmd, *pmd_k; 325 pmd_t *pmd, *pmd_k;
@@ -351,9 +351,7 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
351 return 0; 351 return 0;
352 352
353bad_area: 353bad_area:
354 tsk = current; 354 do_bad_area(addr, fsr, regs);
355
356 do_bad_area(tsk, tsk->active_mm, addr, fsr, regs);
357 return 0; 355 return 0;
358} 356}
359 357
@@ -364,8 +362,7 @@ bad_area:
364static int 362static int
365do_sect_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) 363do_sect_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
366{ 364{
367 struct task_struct *tsk = current; 365 do_bad_area(addr, fsr, regs);
368 do_bad_area(tsk, tsk->active_mm, addr, fsr, regs);
369 return 0; 366 return 0;
370} 367}
371 368
diff --git a/arch/arm/mm/fault.h b/arch/arm/mm/fault.h
index 73b59e83227f..49e9e3804de4 100644
--- a/arch/arm/mm/fault.h
+++ b/arch/arm/mm/fault.h
@@ -1,6 +1,3 @@
1void do_bad_area(struct task_struct *tsk, struct mm_struct *mm, 1void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs);
2 unsigned long addr, unsigned int fsr, struct pt_regs *regs);
3
4void show_pte(struct mm_struct *mm, unsigned long addr);
5 2
6unsigned long search_exception_table(unsigned long addr); 3unsigned long search_exception_table(unsigned long addr);
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index d438ce41cdd5..454205b789d5 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -15,12 +15,12 @@
15#include <asm/system.h> 15#include <asm/system.h>
16#include <asm/tlbflush.h> 16#include <asm/tlbflush.h>
17 17
18#include "mm.h"
19
18#ifdef CONFIG_CPU_CACHE_VIPT 20#ifdef CONFIG_CPU_CACHE_VIPT
19 21
20#define ALIAS_FLUSH_START 0xffff4000 22#define ALIAS_FLUSH_START 0xffff4000
21 23
22#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)
23
24static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) 24static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
25{ 25{
26 unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT); 26 unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
@@ -107,7 +107,7 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
107 107
108 /* VIPT non-aliasing cache */ 108 /* VIPT non-aliasing cache */
109 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask) && 109 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask) &&
110 vma->vm_flags | VM_EXEC) { 110 vma->vm_flags & VM_EXEC) {
111 unsigned long addr = (unsigned long)kaddr; 111 unsigned long addr = (unsigned long)kaddr;
112 /* only flushing the kernel mapping on non-aliasing VIPT */ 112 /* only flushing the kernel mapping on non-aliasing VIPT */
113 __cpuc_coherent_kern_range(addr, addr + len); 113 __cpuc_coherent_kern_range(addr, addr + len);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index fe3f7f625008..22217fe2650b 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -25,10 +25,9 @@
25#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
26#include <asm/mach/map.h> 26#include <asm/mach/map.h>
27 27
28DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); 28#include "mm.h"
29 29
30extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 30extern void _text, _etext, __data_start, _end, __init_begin, __init_end;
31extern void _stext, _text, _etext, __data_start, _end, __init_begin, __init_end;
32extern unsigned long phys_initrd_start; 31extern unsigned long phys_initrd_start;
33extern unsigned long phys_initrd_size; 32extern unsigned long phys_initrd_size;
34 33
@@ -38,12 +37,6 @@ extern unsigned long phys_initrd_size;
38 */ 37 */
39static struct meminfo meminfo __initdata = { 0, }; 38static struct meminfo meminfo __initdata = { 0, };
40 39
41/*
42 * empty_zero_page is a special page that is used for
43 * zero-initialized data and COW.
44 */
45struct page *empty_zero_page;
46
47void show_mem(void) 40void show_mem(void)
48{ 41{
49 int free = 0, total = 0, reserved = 0; 42 int free = 0, total = 0, reserved = 0;
@@ -83,16 +76,6 @@ void show_mem(void)
83 printk("%d pages swap cached\n", cached); 76 printk("%d pages swap cached\n", cached);
84} 77}
85 78
86static inline pmd_t *pmd_off(pgd_t *pgd, unsigned long virt)
87{
88 return pmd_offset(pgd, virt);
89}
90
91static inline pmd_t *pmd_off_k(unsigned long virt)
92{
93 return pmd_off(pgd_offset_k(virt), virt);
94}
95
96#define for_each_nodebank(iter,mi,no) \ 79#define for_each_nodebank(iter,mi,no) \
97 for (iter = 0; iter < mi->nr_banks; iter++) \ 80 for (iter = 0; iter < mi->nr_banks; iter++) \
98 if (mi->bank[iter].node == no) 81 if (mi->bank[iter].node == no)
@@ -176,62 +159,20 @@ static int __init check_initrd(struct meminfo *mi)
176 return initrd_node; 159 return initrd_node;
177} 160}
178 161
179/* 162static inline void map_memory_bank(struct membank *bank)
180 * Reserve the various regions of node 0
181 */
182static __init void reserve_node_zero(pg_data_t *pgdat)
183{ 163{
184 unsigned long res_size = 0; 164#ifdef CONFIG_MMU
185 165 struct map_desc map;
186 /*
187 * Register the kernel text and data with bootmem.
188 * Note that this can only be in node 0.
189 */
190#ifdef CONFIG_XIP_KERNEL
191 reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start);
192#else
193 reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext);
194#endif
195
196 /*
197 * Reserve the page tables. These are already in use,
198 * and can only be in node 0.
199 */
200 reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
201 PTRS_PER_PGD * sizeof(pgd_t));
202
203 /*
204 * Hmm... This should go elsewhere, but we really really need to
205 * stop things allocating the low memory; ideally we need a better
206 * implementation of GFP_DMA which does not assume that DMA-able
207 * memory starts at zero.
208 */
209 if (machine_is_integrator() || machine_is_cintegrator())
210 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
211 166
212 /* 167 map.pfn = __phys_to_pfn(bank->start);
213 * These should likewise go elsewhere. They pre-reserve the 168 map.virtual = __phys_to_virt(bank->start);
214 * screen memory region at the start of main system memory. 169 map.length = bank->size;
215 */ 170 map.type = MT_MEMORY;
216 if (machine_is_edb7211())
217 res_size = 0x00020000;
218 if (machine_is_p720t())
219 res_size = 0x00014000;
220 171
221#ifdef CONFIG_SA1111 172 create_mapping(&map);
222 /*
223 * Because of the SA1111 DMA bug, we want to preserve our
224 * precious DMA-able memory...
225 */
226 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
227#endif 173#endif
228 if (res_size)
229 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size);
230} 174}
231 175
232void __init build_mem_type_table(void);
233void __init create_mapping(struct map_desc *md);
234
235static unsigned long __init 176static unsigned long __init
236bootmem_init_node(int node, int initrd_node, struct meminfo *mi) 177bootmem_init_node(int node, int initrd_node, struct meminfo *mi)
237{ 178{
@@ -248,23 +189,18 @@ bootmem_init_node(int node, int initrd_node, struct meminfo *mi)
248 * Calculate the pfn range, and map the memory banks for this node. 189 * Calculate the pfn range, and map the memory banks for this node.
249 */ 190 */
250 for_each_nodebank(i, mi, node) { 191 for_each_nodebank(i, mi, node) {
192 struct membank *bank = &mi->bank[i];
251 unsigned long start, end; 193 unsigned long start, end;
252 struct map_desc map;
253 194
254 start = mi->bank[i].start >> PAGE_SHIFT; 195 start = bank->start >> PAGE_SHIFT;
255 end = (mi->bank[i].start + mi->bank[i].size) >> PAGE_SHIFT; 196 end = (bank->start + bank->size) >> PAGE_SHIFT;
256 197
257 if (start_pfn > start) 198 if (start_pfn > start)
258 start_pfn = start; 199 start_pfn = start;
259 if (end_pfn < end) 200 if (end_pfn < end)
260 end_pfn = end; 201 end_pfn = end;
261 202
262 map.pfn = __phys_to_pfn(mi->bank[i].start); 203 map_memory_bank(bank);
263 map.virtual = __phys_to_virt(mi->bank[i].start);
264 map.length = mi->bank[i].size;
265 map.type = MT_MEMORY;
266
267 create_mapping(&map);
268 } 204 }
269 205
270 /* 206 /*
@@ -346,9 +282,9 @@ bootmem_init_node(int node, int initrd_node, struct meminfo *mi)
346 return end_pfn; 282 return end_pfn;
347} 283}
348 284
349static void __init bootmem_init(struct meminfo *mi) 285void __init bootmem_init(struct meminfo *mi)
350{ 286{
351 unsigned long addr, memend_pfn = 0; 287 unsigned long memend_pfn = 0;
352 int node, initrd_node, i; 288 int node, initrd_node, i;
353 289
354 /* 290 /*
@@ -361,26 +297,6 @@ static void __init bootmem_init(struct meminfo *mi)
361 memcpy(&meminfo, mi, sizeof(meminfo)); 297 memcpy(&meminfo, mi, sizeof(meminfo));
362 298
363 /* 299 /*
364 * Clear out all the mappings below the kernel image.
365 */
366 for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE)
367 pmd_clear(pmd_off_k(addr));
368#ifdef CONFIG_XIP_KERNEL
369 /* The XIP kernel is mapped in the module area -- skip over it */
370 addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
371#endif
372 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
373 pmd_clear(pmd_off_k(addr));
374
375 /*
376 * Clear out all the kernel space mappings, except for the first
377 * memory bank, up to the end of the vmalloc region.
378 */
379 for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size);
380 addr < VMALLOC_END; addr += PGDIR_SIZE)
381 pmd_clear(pmd_off_k(addr));
382
383 /*
384 * Locate which node contains the ramdisk image, if any. 300 * Locate which node contains the ramdisk image, if any.
385 */ 301 */
386 initrd_node = check_initrd(mi); 302 initrd_node = check_initrd(mi);
@@ -413,114 +329,6 @@ static void __init bootmem_init(struct meminfo *mi)
413 max_pfn = max_low_pfn = memend_pfn - PHYS_PFN_OFFSET; 329 max_pfn = max_low_pfn = memend_pfn - PHYS_PFN_OFFSET;
414} 330}
415 331
416/*
417 * Set up device the mappings. Since we clear out the page tables for all
418 * mappings above VMALLOC_END, we will remove any debug device mappings.
419 * This means you have to be careful how you debug this function, or any
420 * called function. This means you can't use any function or debugging
421 * method which may touch any device, otherwise the kernel _will_ crash.
422 */
423static void __init devicemaps_init(struct machine_desc *mdesc)
424{
425 struct map_desc map;
426 unsigned long addr;
427 void *vectors;
428
429 /*
430 * Allocate the vector page early.
431 */
432 vectors = alloc_bootmem_low_pages(PAGE_SIZE);
433 BUG_ON(!vectors);
434
435 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
436 pmd_clear(pmd_off_k(addr));
437
438 /*
439 * Map the kernel if it is XIP.
440 * It is always first in the modulearea.
441 */
442#ifdef CONFIG_XIP_KERNEL
443 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & PGDIR_MASK);
444 map.virtual = MODULE_START;
445 map.length = ((unsigned long)&_etext - map.virtual + ~PGDIR_MASK) & PGDIR_MASK;
446 map.type = MT_ROM;
447 create_mapping(&map);
448#endif
449
450 /*
451 * Map the cache flushing regions.
452 */
453#ifdef FLUSH_BASE
454 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
455 map.virtual = FLUSH_BASE;
456 map.length = SZ_1M;
457 map.type = MT_CACHECLEAN;
458 create_mapping(&map);
459#endif
460#ifdef FLUSH_BASE_MINICACHE
461 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
462 map.virtual = FLUSH_BASE_MINICACHE;
463 map.length = SZ_1M;
464 map.type = MT_MINICLEAN;
465 create_mapping(&map);
466#endif
467
468 /*
469 * Create a mapping for the machine vectors at the high-vectors
470 * location (0xffff0000). If we aren't using high-vectors, also
471 * create a mapping at the low-vectors virtual address.
472 */
473 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
474 map.virtual = 0xffff0000;
475 map.length = PAGE_SIZE;
476 map.type = MT_HIGH_VECTORS;
477 create_mapping(&map);
478
479 if (!vectors_high()) {
480 map.virtual = 0;
481 map.type = MT_LOW_VECTORS;
482 create_mapping(&map);
483 }
484
485 /*
486 * Ask the machine support to map in the statically mapped devices.
487 */
488 if (mdesc->map_io)
489 mdesc->map_io();
490
491 /*
492 * Finally flush the caches and tlb to ensure that we're in a
493 * consistent state wrt the writebuffer. This also ensures that
494 * any write-allocated cache lines in the vector page are written
495 * back. After this point, we can start to touch devices again.
496 */
497 local_flush_tlb_all();
498 flush_cache_all();
499}
500
501/*
502 * paging_init() sets up the page tables, initialises the zone memory
503 * maps, and sets up the zero page, bad page and bad page tables.
504 */
505void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
506{
507 void *zero_page;
508
509 build_mem_type_table();
510 bootmem_init(mi);
511 devicemaps_init(mdesc);
512
513 top_pmd = pmd_off_k(0xffff0000);
514
515 /*
516 * allocate the zero page. Note that we count on this going ok.
517 */
518 zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
519 memzero(zero_page, PAGE_SIZE);
520 empty_zero_page = virt_to_page(zero_page);
521 flush_dcache_page(empty_zero_page);
522}
523
524static inline void free_area(unsigned long addr, unsigned long end, char *s) 332static inline void free_area(unsigned long addr, unsigned long end, char *s)
525{ 333{
526 unsigned int size = (end - addr) >> 10; 334 unsigned int size = (end - addr) >> 10;
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
deleted file mode 100644
index 38769f5862bc..000000000000
--- a/arch/arm/mm/mm-armv.c
+++ /dev/null
@@ -1,663 +0,0 @@
1/*
2 * linux/arch/arm/mm/mm-armv.c
3 *
4 * Copyright (C) 1998-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Page table sludge for ARM v3 and v4 processor architectures.
11 */
12#include <linux/module.h>
13#include <linux/mm.h>
14#include <linux/init.h>
15#include <linux/bootmem.h>
16#include <linux/highmem.h>
17#include <linux/nodemask.h>
18
19#include <asm/pgalloc.h>
20#include <asm/page.h>
21#include <asm/setup.h>
22#include <asm/tlbflush.h>
23
24#include <asm/mach/map.h>
25
26#define CPOLICY_UNCACHED 0
27#define CPOLICY_BUFFERED 1
28#define CPOLICY_WRITETHROUGH 2
29#define CPOLICY_WRITEBACK 3
30#define CPOLICY_WRITEALLOC 4
31
32static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
33static unsigned int ecc_mask __initdata = 0;
34pgprot_t pgprot_kernel;
35
36EXPORT_SYMBOL(pgprot_kernel);
37
38pmd_t *top_pmd;
39
40struct cachepolicy {
41 const char policy[16];
42 unsigned int cr_mask;
43 unsigned int pmd;
44 unsigned int pte;
45};
46
47static struct cachepolicy cache_policies[] __initdata = {
48 {
49 .policy = "uncached",
50 .cr_mask = CR_W|CR_C,
51 .pmd = PMD_SECT_UNCACHED,
52 .pte = 0,
53 }, {
54 .policy = "buffered",
55 .cr_mask = CR_C,
56 .pmd = PMD_SECT_BUFFERED,
57 .pte = PTE_BUFFERABLE,
58 }, {
59 .policy = "writethrough",
60 .cr_mask = 0,
61 .pmd = PMD_SECT_WT,
62 .pte = PTE_CACHEABLE,
63 }, {
64 .policy = "writeback",
65 .cr_mask = 0,
66 .pmd = PMD_SECT_WB,
67 .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
68 }, {
69 .policy = "writealloc",
70 .cr_mask = 0,
71 .pmd = PMD_SECT_WBWA,
72 .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
73 }
74};
75
76/*
77 * These are useful for identifing cache coherency
78 * problems by allowing the cache or the cache and
79 * writebuffer to be turned off. (Note: the write
80 * buffer should not be on and the cache off).
81 */
82static void __init early_cachepolicy(char **p)
83{
84 int i;
85
86 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
87 int len = strlen(cache_policies[i].policy);
88
89 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
90 cachepolicy = i;
91 cr_alignment &= ~cache_policies[i].cr_mask;
92 cr_no_alignment &= ~cache_policies[i].cr_mask;
93 *p += len;
94 break;
95 }
96 }
97 if (i == ARRAY_SIZE(cache_policies))
98 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
99 flush_cache_all();
100 set_cr(cr_alignment);
101}
102
103static void __init early_nocache(char **__unused)
104{
105 char *p = "buffered";
106 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
107 early_cachepolicy(&p);
108}
109
110static void __init early_nowrite(char **__unused)
111{
112 char *p = "uncached";
113 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
114 early_cachepolicy(&p);
115}
116
117static void __init early_ecc(char **p)
118{
119 if (memcmp(*p, "on", 2) == 0) {
120 ecc_mask = PMD_PROTECTION;
121 *p += 2;
122 } else if (memcmp(*p, "off", 3) == 0) {
123 ecc_mask = 0;
124 *p += 3;
125 }
126}
127
128__early_param("nocache", early_nocache);
129__early_param("nowb", early_nowrite);
130__early_param("cachepolicy=", early_cachepolicy);
131__early_param("ecc=", early_ecc);
132
133static int __init noalign_setup(char *__unused)
134{
135 cr_alignment &= ~CR_A;
136 cr_no_alignment &= ~CR_A;
137 set_cr(cr_alignment);
138 return 1;
139}
140
141__setup("noalign", noalign_setup);
142
143#define FIRST_KERNEL_PGD_NR (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD)
144
145static inline pmd_t *pmd_off(pgd_t *pgd, unsigned long virt)
146{
147 return pmd_offset(pgd, virt);
148}
149
150static inline pmd_t *pmd_off_k(unsigned long virt)
151{
152 return pmd_off(pgd_offset_k(virt), virt);
153}
154
155/*
156 * need to get a 16k page for level 1
157 */
158pgd_t *get_pgd_slow(struct mm_struct *mm)
159{
160 pgd_t *new_pgd, *init_pgd;
161 pmd_t *new_pmd, *init_pmd;
162 pte_t *new_pte, *init_pte;
163
164 new_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, 2);
165 if (!new_pgd)
166 goto no_pgd;
167
168 memzero(new_pgd, FIRST_KERNEL_PGD_NR * sizeof(pgd_t));
169
170 /*
171 * Copy over the kernel and IO PGD entries
172 */
173 init_pgd = pgd_offset_k(0);
174 memcpy(new_pgd + FIRST_KERNEL_PGD_NR, init_pgd + FIRST_KERNEL_PGD_NR,
175 (PTRS_PER_PGD - FIRST_KERNEL_PGD_NR) * sizeof(pgd_t));
176
177 clean_dcache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t));
178
179 if (!vectors_high()) {
180 /*
181 * On ARM, first page must always be allocated since it
182 * contains the machine vectors.
183 */
184 new_pmd = pmd_alloc(mm, new_pgd, 0);
185 if (!new_pmd)
186 goto no_pmd;
187
188 new_pte = pte_alloc_map(mm, new_pmd, 0);
189 if (!new_pte)
190 goto no_pte;
191
192 init_pmd = pmd_offset(init_pgd, 0);
193 init_pte = pte_offset_map_nested(init_pmd, 0);
194 set_pte(new_pte, *init_pte);
195 pte_unmap_nested(init_pte);
196 pte_unmap(new_pte);
197 }
198
199 return new_pgd;
200
201no_pte:
202 pmd_free(new_pmd);
203no_pmd:
204 free_pages((unsigned long)new_pgd, 2);
205no_pgd:
206 return NULL;
207}
208
209void free_pgd_slow(pgd_t *pgd)
210{
211 pmd_t *pmd;
212 struct page *pte;
213
214 if (!pgd)
215 return;
216
217 /* pgd is always present and good */
218 pmd = pmd_off(pgd, 0);
219 if (pmd_none(*pmd))
220 goto free;
221 if (pmd_bad(*pmd)) {
222 pmd_ERROR(*pmd);
223 pmd_clear(pmd);
224 goto free;
225 }
226
227 pte = pmd_page(*pmd);
228 pmd_clear(pmd);
229 dec_zone_page_state(virt_to_page((unsigned long *)pgd), NR_PAGETABLE);
230 pte_lock_deinit(pte);
231 pte_free(pte);
232 pmd_free(pmd);
233free:
234 free_pages((unsigned long) pgd, 2);
235}
236
237/*
238 * Create a SECTION PGD between VIRT and PHYS in domain
239 * DOMAIN with protection PROT. This operates on half-
240 * pgdir entry increments.
241 */
242static inline void
243alloc_init_section(unsigned long virt, unsigned long phys, int prot)
244{
245 pmd_t *pmdp = pmd_off_k(virt);
246
247 if (virt & (1 << 20))
248 pmdp++;
249
250 *pmdp = __pmd(phys | prot);
251 flush_pmd_entry(pmdp);
252}
253
254/*
255 * Create a SUPER SECTION PGD between VIRT and PHYS with protection PROT
256 */
257static inline void
258alloc_init_supersection(unsigned long virt, unsigned long phys, int prot)
259{
260 int i;
261
262 for (i = 0; i < 16; i += 1) {
263 alloc_init_section(virt, phys, prot | PMD_SECT_SUPER);
264
265 virt += (PGDIR_SIZE / 2);
266 }
267}
268
269/*
270 * Add a PAGE mapping between VIRT and PHYS in domain
271 * DOMAIN with protection PROT. Note that due to the
272 * way we map the PTEs, we must allocate two PTE_SIZE'd
273 * blocks - one for the Linux pte table, and one for
274 * the hardware pte table.
275 */
276static inline void
277alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pgprot_t prot)
278{
279 pmd_t *pmdp = pmd_off_k(virt);
280 pte_t *ptep;
281
282 if (pmd_none(*pmdp)) {
283 ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
284 sizeof(pte_t));
285
286 __pmd_populate(pmdp, __pa(ptep) | prot_l1);
287 }
288 ptep = pte_offset_kernel(pmdp, virt);
289
290 set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
291}
292
293struct mem_types {
294 unsigned int prot_pte;
295 unsigned int prot_l1;
296 unsigned int prot_sect;
297 unsigned int domain;
298};
299
300static struct mem_types mem_types[] __initdata = {
301 [MT_DEVICE] = {
302 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
303 L_PTE_WRITE,
304 .prot_l1 = PMD_TYPE_TABLE,
305 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
306 PMD_SECT_AP_WRITE,
307 .domain = DOMAIN_IO,
308 },
309 [MT_CACHECLEAN] = {
310 .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
311 .domain = DOMAIN_KERNEL,
312 },
313 [MT_MINICLEAN] = {
314 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_MINICACHE,
315 .domain = DOMAIN_KERNEL,
316 },
317 [MT_LOW_VECTORS] = {
318 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
319 L_PTE_EXEC,
320 .prot_l1 = PMD_TYPE_TABLE,
321 .domain = DOMAIN_USER,
322 },
323 [MT_HIGH_VECTORS] = {
324 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
325 L_PTE_USER | L_PTE_EXEC,
326 .prot_l1 = PMD_TYPE_TABLE,
327 .domain = DOMAIN_USER,
328 },
329 [MT_MEMORY] = {
330 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_AP_WRITE,
331 .domain = DOMAIN_KERNEL,
332 },
333 [MT_ROM] = {
334 .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
335 .domain = DOMAIN_KERNEL,
336 },
337 [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
338 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
339 L_PTE_WRITE,
340 .prot_l1 = PMD_TYPE_TABLE,
341 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
342 PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
343 PMD_SECT_TEX(1),
344 .domain = DOMAIN_IO,
345 },
346 [MT_NONSHARED_DEVICE] = {
347 .prot_l1 = PMD_TYPE_TABLE,
348 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_NONSHARED_DEV |
349 PMD_SECT_AP_WRITE,
350 .domain = DOMAIN_IO,
351 }
352};
353
354/*
355 * Adjust the PMD section entries according to the CPU in use.
356 */
357void __init build_mem_type_table(void)
358{
359 struct cachepolicy *cp;
360 unsigned int cr = get_cr();
361 unsigned int user_pgprot, kern_pgprot;
362 int cpu_arch = cpu_architecture();
363 int i;
364
365#if defined(CONFIG_CPU_DCACHE_DISABLE)
366 if (cachepolicy > CPOLICY_BUFFERED)
367 cachepolicy = CPOLICY_BUFFERED;
368#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
369 if (cachepolicy > CPOLICY_WRITETHROUGH)
370 cachepolicy = CPOLICY_WRITETHROUGH;
371#endif
372 if (cpu_arch < CPU_ARCH_ARMv5) {
373 if (cachepolicy >= CPOLICY_WRITEALLOC)
374 cachepolicy = CPOLICY_WRITEBACK;
375 ecc_mask = 0;
376 }
377
378 /*
379 * Xscale must not have PMD bit 4 set for section mappings.
380 */
381 if (cpu_is_xscale())
382 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
383 mem_types[i].prot_sect &= ~PMD_BIT4;
384
385 /*
386 * ARMv5 and lower, excluding Xscale, bit 4 must be set for
387 * page tables.
388 */
389 if (cpu_arch < CPU_ARCH_ARMv6 && !cpu_is_xscale())
390 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
391 if (mem_types[i].prot_l1)
392 mem_types[i].prot_l1 |= PMD_BIT4;
393
394 cp = &cache_policies[cachepolicy];
395 kern_pgprot = user_pgprot = cp->pte;
396
397 /*
398 * Enable CPU-specific coherency if supported.
399 * (Only available on XSC3 at the moment.)
400 */
401 if (arch_is_coherent()) {
402 if (cpu_is_xsc3()) {
403 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
404 mem_types[MT_MEMORY].prot_pte |= L_PTE_COHERENT;
405 }
406 }
407
408 /*
409 * ARMv6 and above have extended page tables.
410 */
411 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
412 /*
413 * bit 4 becomes XN which we must clear for the
414 * kernel memory mapping.
415 */
416 mem_types[MT_MEMORY].prot_sect &= ~PMD_SECT_XN;
417 mem_types[MT_ROM].prot_sect &= ~PMD_SECT_XN;
418
419 /*
420 * Mark cache clean areas and XIP ROM read only
421 * from SVC mode and no access from userspace.
422 */
423 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
424 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
425 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
426
427 /*
428 * Mark the device area as "shared device"
429 */
430 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
431 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
432
433 /*
434 * User pages need to be mapped with the ASID
435 * (iow, non-global)
436 */
437 user_pgprot |= L_PTE_ASID;
438
439#ifdef CONFIG_SMP
440 /*
441 * Mark memory with the "shared" attribute for SMP systems
442 */
443 user_pgprot |= L_PTE_SHARED;
444 kern_pgprot |= L_PTE_SHARED;
445 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
446#endif
447 }
448
449 for (i = 0; i < 16; i++) {
450 unsigned long v = pgprot_val(protection_map[i]);
451 v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot;
452 protection_map[i] = __pgprot(v);
453 }
454
455 mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot;
456 mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot;
457
458 if (cpu_arch >= CPU_ARCH_ARMv5) {
459#ifndef CONFIG_SMP
460 /*
461 * Only use write-through for non-SMP systems
462 */
463 mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
464 mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
465#endif
466 } else {
467 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
468 }
469
470 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
471 L_PTE_DIRTY | L_PTE_WRITE |
472 L_PTE_EXEC | kern_pgprot);
473
474 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
475 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
476 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
477 mem_types[MT_ROM].prot_sect |= cp->pmd;
478
479 switch (cp->pmd) {
480 case PMD_SECT_WT:
481 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
482 break;
483 case PMD_SECT_WB:
484 case PMD_SECT_WBWA:
485 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
486 break;
487 }
488 printk("Memory policy: ECC %sabled, Data cache %s\n",
489 ecc_mask ? "en" : "dis", cp->policy);
490}
491
492#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
493
494/*
495 * Create the page directory entries and any necessary
496 * page tables for the mapping specified by `md'. We
497 * are able to cope here with varying sizes and address
498 * offsets, and we take full advantage of sections and
499 * supersections.
500 */
501void __init create_mapping(struct map_desc *md)
502{
503 unsigned long virt, length;
504 int prot_sect, prot_l1, domain;
505 pgprot_t prot_pte;
506 unsigned long off = (u32)__pfn_to_phys(md->pfn);
507
508 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
509 printk(KERN_WARNING "BUG: not creating mapping for "
510 "0x%08llx at 0x%08lx in user region\n",
511 __pfn_to_phys((u64)md->pfn), md->virtual);
512 return;
513 }
514
515 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
516 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
517 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
518 "overlaps vmalloc space\n",
519 __pfn_to_phys((u64)md->pfn), md->virtual);
520 }
521
522 domain = mem_types[md->type].domain;
523 prot_pte = __pgprot(mem_types[md->type].prot_pte);
524 prot_l1 = mem_types[md->type].prot_l1 | PMD_DOMAIN(domain);
525 prot_sect = mem_types[md->type].prot_sect | PMD_DOMAIN(domain);
526
527 /*
528 * Catch 36-bit addresses
529 */
530 if(md->pfn >= 0x100000) {
531 if(domain) {
532 printk(KERN_ERR "MM: invalid domain in supersection "
533 "mapping for 0x%08llx at 0x%08lx\n",
534 __pfn_to_phys((u64)md->pfn), md->virtual);
535 return;
536 }
537 if((md->virtual | md->length | __pfn_to_phys(md->pfn))
538 & ~SUPERSECTION_MASK) {
539 printk(KERN_ERR "MM: cannot create mapping for "
540 "0x%08llx at 0x%08lx invalid alignment\n",
541 __pfn_to_phys((u64)md->pfn), md->virtual);
542 return;
543 }
544
545 /*
546 * Shift bits [35:32] of address into bits [23:20] of PMD
547 * (See ARMv6 spec).
548 */
549 off |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
550 }
551
552 virt = md->virtual;
553 off -= virt;
554 length = md->length;
555
556 if (mem_types[md->type].prot_l1 == 0 &&
557 (virt & 0xfffff || (virt + off) & 0xfffff || (virt + length) & 0xfffff)) {
558 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
559 "be mapped using pages, ignoring.\n",
560 __pfn_to_phys(md->pfn), md->virtual);
561 return;
562 }
563
564 while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) {
565 alloc_init_page(virt, virt + off, prot_l1, prot_pte);
566
567 virt += PAGE_SIZE;
568 length -= PAGE_SIZE;
569 }
570
571 /* N.B. ARMv6 supersections are only defined to work with domain 0.
572 * Since domain assignments can in fact be arbitrary, the
573 * 'domain == 0' check below is required to insure that ARMv6
574 * supersections are only allocated for domain 0 regardless
575 * of the actual domain assignments in use.
576 */
577 if ((cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())
578 && domain == 0) {
579 /*
580 * Align to supersection boundary if !high pages.
581 * High pages have already been checked for proper
582 * alignment above and they will fail the SUPSERSECTION_MASK
583 * check because of the way the address is encoded into
584 * offset.
585 */
586 if (md->pfn <= 0x100000) {
587 while ((virt & ~SUPERSECTION_MASK ||
588 (virt + off) & ~SUPERSECTION_MASK) &&
589 length >= (PGDIR_SIZE / 2)) {
590 alloc_init_section(virt, virt + off, prot_sect);
591
592 virt += (PGDIR_SIZE / 2);
593 length -= (PGDIR_SIZE / 2);
594 }
595 }
596
597 while (length >= SUPERSECTION_SIZE) {
598 alloc_init_supersection(virt, virt + off, prot_sect);
599
600 virt += SUPERSECTION_SIZE;
601 length -= SUPERSECTION_SIZE;
602 }
603 }
604
605 /*
606 * A section mapping covers half a "pgdir" entry.
607 */
608 while (length >= (PGDIR_SIZE / 2)) {
609 alloc_init_section(virt, virt + off, prot_sect);
610
611 virt += (PGDIR_SIZE / 2);
612 length -= (PGDIR_SIZE / 2);
613 }
614
615 while (length >= PAGE_SIZE) {
616 alloc_init_page(virt, virt + off, prot_l1, prot_pte);
617
618 virt += PAGE_SIZE;
619 length -= PAGE_SIZE;
620 }
621}
622
623/*
624 * In order to soft-boot, we need to insert a 1:1 mapping in place of
625 * the user-mode pages. This will then ensure that we have predictable
626 * results when turning the mmu off
627 */
628void setup_mm_for_reboot(char mode)
629{
630 unsigned long base_pmdval;
631 pgd_t *pgd;
632 int i;
633
634 if (current->mm && current->mm->pgd)
635 pgd = current->mm->pgd;
636 else
637 pgd = init_mm.pgd;
638
639 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
640 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
641 base_pmdval |= PMD_BIT4;
642
643 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
644 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
645 pmd_t *pmd;
646
647 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
648 pmd[0] = __pmd(pmdval);
649 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
650 flush_pmd_entry(pmd);
651 }
652}
653
654/*
655 * Create the architecture specific mappings
656 */
657void __init iotable_init(struct map_desc *io_desc, int nr)
658{
659 int i;
660
661 for (i = 0; i < nr; i++)
662 create_mapping(io_desc + i);
663}
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
new file mode 100644
index 000000000000..bb2bc9ab6bd3
--- /dev/null
+++ b/arch/arm/mm/mm.h
@@ -0,0 +1,22 @@
1/* the upper-most page table pointer */
2extern pmd_t *top_pmd;
3
4#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)
5
6static inline pmd_t *pmd_off(pgd_t *pgd, unsigned long virt)
7{
8 return pmd_offset(pgd, virt);
9}
10
11static inline pmd_t *pmd_off_k(unsigned long virt)
12{
13 return pmd_off(pgd_offset_k(virt), virt);
14}
15
16struct map_desc;
17struct meminfo;
18struct pglist_data;
19
20void __init create_mapping(struct map_desc *md);
21void __init bootmem_init(struct meminfo *mi);
22void reserve_node_zero(struct pglist_data *pgdat);
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index 29e54807c5bc..b0b5f4694070 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -114,3 +114,25 @@ full_search:
114 } 114 }
115} 115}
116 116
117
118/*
119 * You really shouldn't be using read() or write() on /dev/mem. This
120 * might go away in the future.
121 */
122int valid_phys_addr_range(unsigned long addr, size_t size)
123{
124 if (addr + size > __pa(high_memory))
125 return 0;
126
127 return 1;
128}
129
130/*
131 * We don't use supersection mappings for mmap() on /dev/mem, which
132 * means that we can't map the memory area above the 4G barrier into
133 * userspace.
134 */
135int valid_mmap_phys_addr_range(unsigned long pfn, size_t size)
136{
137 return !(pfn + (size >> PAGE_SHIFT) > 0x00100000);
138}
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 0d90227a0a32..e566cbe4b222 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1,45 +1,771 @@
1/* 1/*
2 * linux/arch/arm/mm/mmu.c 2 * linux/arch/arm/mm/mmu.c
3 * 3 *
4 * Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved. 4 * Copyright (C) 1995-2005 Russell King
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/errno.h>
10#include <linux/init.h> 13#include <linux/init.h>
11#include <linux/sched.h> 14#include <linux/bootmem.h>
12#include <linux/mm.h> 15#include <linux/mman.h>
16#include <linux/nodemask.h>
13 17
14#include <asm/mmu_context.h> 18#include <asm/mach-types.h>
15#include <asm/tlbflush.h> 19#include <asm/setup.h>
20#include <asm/sizes.h>
21#include <asm/tlb.h>
16 22
17unsigned int cpu_last_asid = { 1 << ASID_BITS }; 23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25
26#include "mm.h"
27
28DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
29
30extern void _stext, __data_start, _end;
31extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
32
33/*
34 * empty_zero_page is a special page that is used for
35 * zero-initialized data and COW.
36 */
37struct page *empty_zero_page;
18 38
19/* 39/*
20 * We fork()ed a process, and we need a new context for the child 40 * The pmd table for the upper-most set of pages.
21 * to run in. We reserve version 0 for initial tasks so we will
22 * always allocate an ASID.
23 */ 41 */
24void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) 42pmd_t *top_pmd;
43
44#define CPOLICY_UNCACHED 0
45#define CPOLICY_BUFFERED 1
46#define CPOLICY_WRITETHROUGH 2
47#define CPOLICY_WRITEBACK 3
48#define CPOLICY_WRITEALLOC 4
49
50static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
51static unsigned int ecc_mask __initdata = 0;
52pgprot_t pgprot_kernel;
53
54EXPORT_SYMBOL(pgprot_kernel);
55
56struct cachepolicy {
57 const char policy[16];
58 unsigned int cr_mask;
59 unsigned int pmd;
60 unsigned int pte;
61};
62
63static struct cachepolicy cache_policies[] __initdata = {
64 {
65 .policy = "uncached",
66 .cr_mask = CR_W|CR_C,
67 .pmd = PMD_SECT_UNCACHED,
68 .pte = 0,
69 }, {
70 .policy = "buffered",
71 .cr_mask = CR_C,
72 .pmd = PMD_SECT_BUFFERED,
73 .pte = PTE_BUFFERABLE,
74 }, {
75 .policy = "writethrough",
76 .cr_mask = 0,
77 .pmd = PMD_SECT_WT,
78 .pte = PTE_CACHEABLE,
79 }, {
80 .policy = "writeback",
81 .cr_mask = 0,
82 .pmd = PMD_SECT_WB,
83 .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
84 }, {
85 .policy = "writealloc",
86 .cr_mask = 0,
87 .pmd = PMD_SECT_WBWA,
88 .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
89 }
90};
91
92/*
93 * These are useful for identifing cache coherency
94 * problems by allowing the cache or the cache and
95 * writebuffer to be turned off. (Note: the write
96 * buffer should not be on and the cache off).
97 */
98static void __init early_cachepolicy(char **p)
99{
100 int i;
101
102 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
103 int len = strlen(cache_policies[i].policy);
104
105 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
106 cachepolicy = i;
107 cr_alignment &= ~cache_policies[i].cr_mask;
108 cr_no_alignment &= ~cache_policies[i].cr_mask;
109 *p += len;
110 break;
111 }
112 }
113 if (i == ARRAY_SIZE(cache_policies))
114 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
115 flush_cache_all();
116 set_cr(cr_alignment);
117}
118__early_param("cachepolicy=", early_cachepolicy);
119
120static void __init early_nocache(char **__unused)
121{
122 char *p = "buffered";
123 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
124 early_cachepolicy(&p);
125}
126__early_param("nocache", early_nocache);
127
128static void __init early_nowrite(char **__unused)
129{
130 char *p = "uncached";
131 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
132 early_cachepolicy(&p);
133}
134__early_param("nowb", early_nowrite);
135
136static void __init early_ecc(char **p)
137{
138 if (memcmp(*p, "on", 2) == 0) {
139 ecc_mask = PMD_PROTECTION;
140 *p += 2;
141 } else if (memcmp(*p, "off", 3) == 0) {
142 ecc_mask = 0;
143 *p += 3;
144 }
145}
146__early_param("ecc=", early_ecc);
147
148static int __init noalign_setup(char *__unused)
25{ 149{
26 mm->context.id = 0; 150 cr_alignment &= ~CR_A;
151 cr_no_alignment &= ~CR_A;
152 set_cr(cr_alignment);
153 return 1;
27} 154}
155__setup("noalign", noalign_setup);
156
157struct mem_types {
158 unsigned int prot_pte;
159 unsigned int prot_l1;
160 unsigned int prot_sect;
161 unsigned int domain;
162};
28 163
29void __new_context(struct mm_struct *mm) 164static struct mem_types mem_types[] __initdata = {
165 [MT_DEVICE] = {
166 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
167 L_PTE_WRITE,
168 .prot_l1 = PMD_TYPE_TABLE,
169 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
170 PMD_SECT_AP_WRITE,
171 .domain = DOMAIN_IO,
172 },
173 [MT_CACHECLEAN] = {
174 .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
175 .domain = DOMAIN_KERNEL,
176 },
177 [MT_MINICLEAN] = {
178 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_MINICACHE,
179 .domain = DOMAIN_KERNEL,
180 },
181 [MT_LOW_VECTORS] = {
182 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
183 L_PTE_EXEC,
184 .prot_l1 = PMD_TYPE_TABLE,
185 .domain = DOMAIN_USER,
186 },
187 [MT_HIGH_VECTORS] = {
188 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
189 L_PTE_USER | L_PTE_EXEC,
190 .prot_l1 = PMD_TYPE_TABLE,
191 .domain = DOMAIN_USER,
192 },
193 [MT_MEMORY] = {
194 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_AP_WRITE,
195 .domain = DOMAIN_KERNEL,
196 },
197 [MT_ROM] = {
198 .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
199 .domain = DOMAIN_KERNEL,
200 },
201 [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
202 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
203 L_PTE_WRITE,
204 .prot_l1 = PMD_TYPE_TABLE,
205 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
206 PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
207 PMD_SECT_TEX(1),
208 .domain = DOMAIN_IO,
209 },
210 [MT_NONSHARED_DEVICE] = {
211 .prot_l1 = PMD_TYPE_TABLE,
212 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_NONSHARED_DEV |
213 PMD_SECT_AP_WRITE,
214 .domain = DOMAIN_IO,
215 }
216};
217
218/*
219 * Adjust the PMD section entries according to the CPU in use.
220 */
221static void __init build_mem_type_table(void)
30{ 222{
31 unsigned int asid; 223 struct cachepolicy *cp;
224 unsigned int cr = get_cr();
225 unsigned int user_pgprot, kern_pgprot;
226 int cpu_arch = cpu_architecture();
227 int i;
32 228
33 asid = ++cpu_last_asid; 229#if defined(CONFIG_CPU_DCACHE_DISABLE)
34 if (asid == 0) 230 if (cachepolicy > CPOLICY_BUFFERED)
35 asid = cpu_last_asid = 1 << ASID_BITS; 231 cachepolicy = CPOLICY_BUFFERED;
232#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
233 if (cachepolicy > CPOLICY_WRITETHROUGH)
234 cachepolicy = CPOLICY_WRITETHROUGH;
235#endif
236 if (cpu_arch < CPU_ARCH_ARMv5) {
237 if (cachepolicy >= CPOLICY_WRITEALLOC)
238 cachepolicy = CPOLICY_WRITEBACK;
239 ecc_mask = 0;
240 }
241
242 /*
243 * Xscale must not have PMD bit 4 set for section mappings.
244 */
245 if (cpu_is_xscale())
246 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
247 mem_types[i].prot_sect &= ~PMD_BIT4;
36 248
37 /* 249 /*
38 * If we've used up all our ASIDs, we need 250 * ARMv5 and lower, excluding Xscale, bit 4 must be set for
39 * to start a new version and flush the TLB. 251 * page tables.
40 */ 252 */
41 if ((asid & ~ASID_MASK) == 0) 253 if (cpu_arch < CPU_ARCH_ARMv6 && !cpu_is_xscale())
42 flush_tlb_all(); 254 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
255 if (mem_types[i].prot_l1)
256 mem_types[i].prot_l1 |= PMD_BIT4;
257
258 cp = &cache_policies[cachepolicy];
259 kern_pgprot = user_pgprot = cp->pte;
260
261 /*
262 * Enable CPU-specific coherency if supported.
263 * (Only available on XSC3 at the moment.)
264 */
265 if (arch_is_coherent()) {
266 if (cpu_is_xsc3()) {
267 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
268 mem_types[MT_MEMORY].prot_pte |= L_PTE_COHERENT;
269 }
270 }
271
272 /*
273 * ARMv6 and above have extended page tables.
274 */
275 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
276 /*
277 * bit 4 becomes XN which we must clear for the
278 * kernel memory mapping.
279 */
280 mem_types[MT_MEMORY].prot_sect &= ~PMD_SECT_XN;
281 mem_types[MT_ROM].prot_sect &= ~PMD_SECT_XN;
282
283 /*
284 * Mark cache clean areas and XIP ROM read only
285 * from SVC mode and no access from userspace.
286 */
287 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
288 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
289 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
290
291 /*
292 * Mark the device area as "shared device"
293 */
294 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
295 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
296
297 /*
298 * User pages need to be mapped with the ASID
299 * (iow, non-global)
300 */
301 user_pgprot |= L_PTE_ASID;
302
303#ifdef CONFIG_SMP
304 /*
305 * Mark memory with the "shared" attribute for SMP systems
306 */
307 user_pgprot |= L_PTE_SHARED;
308 kern_pgprot |= L_PTE_SHARED;
309 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
310#endif
311 }
312
313 for (i = 0; i < 16; i++) {
314 unsigned long v = pgprot_val(protection_map[i]);
315 v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot;
316 protection_map[i] = __pgprot(v);
317 }
318
319 mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot;
320 mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot;
321
322 if (cpu_arch >= CPU_ARCH_ARMv5) {
323#ifndef CONFIG_SMP
324 /*
325 * Only use write-through for non-SMP systems
326 */
327 mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
328 mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
329#endif
330 } else {
331 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
332 }
333
334 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
335 L_PTE_DIRTY | L_PTE_WRITE |
336 L_PTE_EXEC | kern_pgprot);
337
338 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
339 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
340 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
341 mem_types[MT_ROM].prot_sect |= cp->pmd;
342
343 switch (cp->pmd) {
344 case PMD_SECT_WT:
345 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
346 break;
347 case PMD_SECT_WB:
348 case PMD_SECT_WBWA:
349 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
350 break;
351 }
352 printk("Memory policy: ECC %sabled, Data cache %s\n",
353 ecc_mask ? "en" : "dis", cp->policy);
354}
355
356#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
357
358/*
359 * Create a SECTION PGD between VIRT and PHYS in domain
360 * DOMAIN with protection PROT. This operates on half-
361 * pgdir entry increments.
362 */
363static inline void
364alloc_init_section(unsigned long virt, unsigned long phys, int prot)
365{
366 pmd_t *pmdp = pmd_off_k(virt);
367
368 if (virt & (1 << 20))
369 pmdp++;
370
371 *pmdp = __pmd(phys | prot);
372 flush_pmd_entry(pmdp);
373}
374
375/*
376 * Create a SUPER SECTION PGD between VIRT and PHYS with protection PROT
377 */
378static inline void
379alloc_init_supersection(unsigned long virt, unsigned long phys, int prot)
380{
381 int i;
382
383 for (i = 0; i < 16; i += 1) {
384 alloc_init_section(virt, phys, prot | PMD_SECT_SUPER);
385
386 virt += (PGDIR_SIZE / 2);
387 }
388}
389
390/*
391 * Add a PAGE mapping between VIRT and PHYS in domain
392 * DOMAIN with protection PROT. Note that due to the
393 * way we map the PTEs, we must allocate two PTE_SIZE'd
394 * blocks - one for the Linux pte table, and one for
395 * the hardware pte table.
396 */
397static inline void
398alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pgprot_t prot)
399{
400 pmd_t *pmdp = pmd_off_k(virt);
401 pte_t *ptep;
402
403 if (pmd_none(*pmdp)) {
404 ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
405 sizeof(pte_t));
406
407 __pmd_populate(pmdp, __pa(ptep) | prot_l1);
408 }
409 ptep = pte_offset_kernel(pmdp, virt);
410
411 set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
412}
413
414/*
415 * Create the page directory entries and any necessary
416 * page tables for the mapping specified by `md'. We
417 * are able to cope here with varying sizes and address
418 * offsets, and we take full advantage of sections and
419 * supersections.
420 */
421void __init create_mapping(struct map_desc *md)
422{
423 unsigned long virt, length;
424 int prot_sect, prot_l1, domain;
425 pgprot_t prot_pte;
426 unsigned long off = (u32)__pfn_to_phys(md->pfn);
427
428 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
429 printk(KERN_WARNING "BUG: not creating mapping for "
430 "0x%08llx at 0x%08lx in user region\n",
431 __pfn_to_phys((u64)md->pfn), md->virtual);
432 return;
433 }
434
435 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
436 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
437 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
438 "overlaps vmalloc space\n",
439 __pfn_to_phys((u64)md->pfn), md->virtual);
440 }
441
442 domain = mem_types[md->type].domain;
443 prot_pte = __pgprot(mem_types[md->type].prot_pte);
444 prot_l1 = mem_types[md->type].prot_l1 | PMD_DOMAIN(domain);
445 prot_sect = mem_types[md->type].prot_sect | PMD_DOMAIN(domain);
446
447 /*
448 * Catch 36-bit addresses
449 */
450 if(md->pfn >= 0x100000) {
451 if(domain) {
452 printk(KERN_ERR "MM: invalid domain in supersection "
453 "mapping for 0x%08llx at 0x%08lx\n",
454 __pfn_to_phys((u64)md->pfn), md->virtual);
455 return;
456 }
457 if((md->virtual | md->length | __pfn_to_phys(md->pfn))
458 & ~SUPERSECTION_MASK) {
459 printk(KERN_ERR "MM: cannot create mapping for "
460 "0x%08llx at 0x%08lx invalid alignment\n",
461 __pfn_to_phys((u64)md->pfn), md->virtual);
462 return;
463 }
464
465 /*
466 * Shift bits [35:32] of address into bits [23:20] of PMD
467 * (See ARMv6 spec).
468 */
469 off |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
470 }
471
472 virt = md->virtual;
473 off -= virt;
474 length = md->length;
475
476 if (mem_types[md->type].prot_l1 == 0 &&
477 (virt & 0xfffff || (virt + off) & 0xfffff || (virt + length) & 0xfffff)) {
478 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
479 "be mapped using pages, ignoring.\n",
480 __pfn_to_phys(md->pfn), md->virtual);
481 return;
482 }
483
484 while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) {
485 alloc_init_page(virt, virt + off, prot_l1, prot_pte);
486
487 virt += PAGE_SIZE;
488 length -= PAGE_SIZE;
489 }
490
491 /* N.B. ARMv6 supersections are only defined to work with domain 0.
492 * Since domain assignments can in fact be arbitrary, the
493 * 'domain == 0' check below is required to insure that ARMv6
494 * supersections are only allocated for domain 0 regardless
495 * of the actual domain assignments in use.
496 */
497 if ((cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())
498 && domain == 0) {
499 /*
500 * Align to supersection boundary if !high pages.
501 * High pages have already been checked for proper
502 * alignment above and they will fail the SUPSERSECTION_MASK
503 * check because of the way the address is encoded into
504 * offset.
505 */
506 if (md->pfn <= 0x100000) {
507 while ((virt & ~SUPERSECTION_MASK ||
508 (virt + off) & ~SUPERSECTION_MASK) &&
509 length >= (PGDIR_SIZE / 2)) {
510 alloc_init_section(virt, virt + off, prot_sect);
511
512 virt += (PGDIR_SIZE / 2);
513 length -= (PGDIR_SIZE / 2);
514 }
515 }
516
517 while (length >= SUPERSECTION_SIZE) {
518 alloc_init_supersection(virt, virt + off, prot_sect);
519
520 virt += SUPERSECTION_SIZE;
521 length -= SUPERSECTION_SIZE;
522 }
523 }
524
525 /*
526 * A section mapping covers half a "pgdir" entry.
527 */
528 while (length >= (PGDIR_SIZE / 2)) {
529 alloc_init_section(virt, virt + off, prot_sect);
530
531 virt += (PGDIR_SIZE / 2);
532 length -= (PGDIR_SIZE / 2);
533 }
534
535 while (length >= PAGE_SIZE) {
536 alloc_init_page(virt, virt + off, prot_l1, prot_pte);
537
538 virt += PAGE_SIZE;
539 length -= PAGE_SIZE;
540 }
541}
542
543/*
544 * Create the architecture specific mappings
545 */
546void __init iotable_init(struct map_desc *io_desc, int nr)
547{
548 int i;
549
550 for (i = 0; i < nr; i++)
551 create_mapping(io_desc + i);
552}
553
554static inline void prepare_page_table(struct meminfo *mi)
555{
556 unsigned long addr;
557
558 /*
559 * Clear out all the mappings below the kernel image.
560 */
561 for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE)
562 pmd_clear(pmd_off_k(addr));
563
564#ifdef CONFIG_XIP_KERNEL
565 /* The XIP kernel is mapped in the module area -- skip over it */
566 addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
567#endif
568 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
569 pmd_clear(pmd_off_k(addr));
570
571 /*
572 * Clear out all the kernel space mappings, except for the first
573 * memory bank, up to the end of the vmalloc region.
574 */
575 for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size);
576 addr < VMALLOC_END; addr += PGDIR_SIZE)
577 pmd_clear(pmd_off_k(addr));
578}
579
580/*
581 * Reserve the various regions of node 0
582 */
583void __init reserve_node_zero(pg_data_t *pgdat)
584{
585 unsigned long res_size = 0;
586
587 /*
588 * Register the kernel text and data with bootmem.
589 * Note that this can only be in node 0.
590 */
591#ifdef CONFIG_XIP_KERNEL
592 reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start);
593#else
594 reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext);
595#endif
596
597 /*
598 * Reserve the page tables. These are already in use,
599 * and can only be in node 0.
600 */
601 reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
602 PTRS_PER_PGD * sizeof(pgd_t));
603
604 /*
605 * Hmm... This should go elsewhere, but we really really need to
606 * stop things allocating the low memory; ideally we need a better
607 * implementation of GFP_DMA which does not assume that DMA-able
608 * memory starts at zero.
609 */
610 if (machine_is_integrator() || machine_is_cintegrator())
611 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
612
613 /*
614 * These should likewise go elsewhere. They pre-reserve the
615 * screen memory region at the start of main system memory.
616 */
617 if (machine_is_edb7211())
618 res_size = 0x00020000;
619 if (machine_is_p720t())
620 res_size = 0x00014000;
621
622#ifdef CONFIG_SA1111
623 /*
624 * Because of the SA1111 DMA bug, we want to preserve our
625 * precious DMA-able memory...
626 */
627 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
628#endif
629 if (res_size)
630 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size);
631}
632
633/*
634 * Set up device the mappings. Since we clear out the page tables for all
635 * mappings above VMALLOC_END, we will remove any debug device mappings.
636 * This means you have to be careful how you debug this function, or any
637 * called function. This means you can't use any function or debugging
638 * method which may touch any device, otherwise the kernel _will_ crash.
639 */
640static void __init devicemaps_init(struct machine_desc *mdesc)
641{
642 struct map_desc map;
643 unsigned long addr;
644 void *vectors;
645
646 /*
647 * Allocate the vector page early.
648 */
649 vectors = alloc_bootmem_low_pages(PAGE_SIZE);
650 BUG_ON(!vectors);
651
652 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
653 pmd_clear(pmd_off_k(addr));
654
655 /*
656 * Map the kernel if it is XIP.
657 * It is always first in the modulearea.
658 */
659#ifdef CONFIG_XIP_KERNEL
660 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
661 map.virtual = MODULE_START;
662 map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
663 map.type = MT_ROM;
664 create_mapping(&map);
665#endif
666
667 /*
668 * Map the cache flushing regions.
669 */
670#ifdef FLUSH_BASE
671 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
672 map.virtual = FLUSH_BASE;
673 map.length = SZ_1M;
674 map.type = MT_CACHECLEAN;
675 create_mapping(&map);
676#endif
677#ifdef FLUSH_BASE_MINICACHE
678 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
679 map.virtual = FLUSH_BASE_MINICACHE;
680 map.length = SZ_1M;
681 map.type = MT_MINICLEAN;
682 create_mapping(&map);
683#endif
684
685 /*
686 * Create a mapping for the machine vectors at the high-vectors
687 * location (0xffff0000). If we aren't using high-vectors, also
688 * create a mapping at the low-vectors virtual address.
689 */
690 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
691 map.virtual = 0xffff0000;
692 map.length = PAGE_SIZE;
693 map.type = MT_HIGH_VECTORS;
694 create_mapping(&map);
695
696 if (!vectors_high()) {
697 map.virtual = 0;
698 map.type = MT_LOW_VECTORS;
699 create_mapping(&map);
700 }
701
702 /*
703 * Ask the machine support to map in the statically mapped devices.
704 */
705 if (mdesc->map_io)
706 mdesc->map_io();
707
708 /*
709 * Finally flush the caches and tlb to ensure that we're in a
710 * consistent state wrt the writebuffer. This also ensures that
711 * any write-allocated cache lines in the vector page are written
712 * back. After this point, we can start to touch devices again.
713 */
714 local_flush_tlb_all();
715 flush_cache_all();
716}
717
718/*
719 * paging_init() sets up the page tables, initialises the zone memory
720 * maps, and sets up the zero page, bad page and bad page tables.
721 */
722void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
723{
724 void *zero_page;
725
726 build_mem_type_table();
727 prepare_page_table(mi);
728 bootmem_init(mi);
729 devicemaps_init(mdesc);
730
731 top_pmd = pmd_off_k(0xffff0000);
732
733 /*
734 * allocate the zero page. Note that we count on this going ok.
735 */
736 zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
737 memzero(zero_page, PAGE_SIZE);
738 empty_zero_page = virt_to_page(zero_page);
739 flush_dcache_page(empty_zero_page);
740}
741
742/*
743 * In order to soft-boot, we need to insert a 1:1 mapping in place of
744 * the user-mode pages. This will then ensure that we have predictable
745 * results when turning the mmu off
746 */
747void setup_mm_for_reboot(char mode)
748{
749 unsigned long base_pmdval;
750 pgd_t *pgd;
751 int i;
752
753 if (current->mm && current->mm->pgd)
754 pgd = current->mm->pgd;
755 else
756 pgd = init_mm.pgd;
757
758 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
759 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
760 base_pmdval |= PMD_BIT4;
761
762 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
763 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
764 pmd_t *pmd;
43 765
44 mm->context.id = asid; 766 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
767 pmd[0] = __pmd(pmdval);
768 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
769 flush_pmd_entry(pmd);
770 }
45} 771}
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 1464ed817b5d..d0e66424a597 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -11,6 +11,49 @@
11#include <asm/io.h> 11#include <asm/io.h>
12#include <asm/page.h> 12#include <asm/page.h>
13 13
14#include "mm.h"
15
16extern void _stext, __data_start, _end;
17
18/*
19 * Reserve the various regions of node 0
20 */
21void __init reserve_node_zero(pg_data_t *pgdat)
22{
23 /*
24 * Register the kernel text and data with bootmem.
25 * Note that this can only be in node 0.
26 */
27#ifdef CONFIG_XIP_KERNEL
28 reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start);
29#else
30 reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext);
31#endif
32
33 /*
34 * Register the exception vector page.
35 * some architectures which the DRAM is the exception vector to trap,
36 * alloc_page breaks with error, although it is not NULL, but "0."
37 */
38 reserve_bootmem_node(pgdat, CONFIG_VECTORS_BASE, PAGE_SIZE);
39}
40
41/*
42 * paging_init() sets up the page tables, initialises the zone memory
43 * maps, and sets up the zero page, bad page and bad page tables.
44 */
45void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
46{
47 bootmem_init(mi);
48}
49
50/*
51 * We don't need to do anything here for nommu machines.
52 */
53void setup_mm_for_reboot(char mode)
54{
55}
56
14void flush_dcache_page(struct page *page) 57void flush_dcache_page(struct page *page)
15{ 58{
16 __cpuc_flush_dcache_page(page_address(page)); 59 __cpuc_flush_dcache_page(page_address(page));
diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c
new file mode 100644
index 000000000000..20c1b0df75f2
--- /dev/null
+++ b/arch/arm/mm/pgd.c
@@ -0,0 +1,101 @@
1/*
2 * linux/arch/arm/mm/pgd.c
3 *
4 * Copyright (C) 1998-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/mm.h>
11#include <linux/highmem.h>
12
13#include <asm/pgalloc.h>
14#include <asm/page.h>
15#include <asm/tlbflush.h>
16
17#include "mm.h"
18
19#define FIRST_KERNEL_PGD_NR (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD)
20
21/*
22 * need to get a 16k page for level 1
23 */
24pgd_t *get_pgd_slow(struct mm_struct *mm)
25{
26 pgd_t *new_pgd, *init_pgd;
27 pmd_t *new_pmd, *init_pmd;
28 pte_t *new_pte, *init_pte;
29
30 new_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, 2);
31 if (!new_pgd)
32 goto no_pgd;
33
34 memzero(new_pgd, FIRST_KERNEL_PGD_NR * sizeof(pgd_t));
35
36 /*
37 * Copy over the kernel and IO PGD entries
38 */
39 init_pgd = pgd_offset_k(0);
40 memcpy(new_pgd + FIRST_KERNEL_PGD_NR, init_pgd + FIRST_KERNEL_PGD_NR,
41 (PTRS_PER_PGD - FIRST_KERNEL_PGD_NR) * sizeof(pgd_t));
42
43 clean_dcache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t));
44
45 if (!vectors_high()) {
46 /*
47 * On ARM, first page must always be allocated since it
48 * contains the machine vectors.
49 */
50 new_pmd = pmd_alloc(mm, new_pgd, 0);
51 if (!new_pmd)
52 goto no_pmd;
53
54 new_pte = pte_alloc_map(mm, new_pmd, 0);
55 if (!new_pte)
56 goto no_pte;
57
58 init_pmd = pmd_offset(init_pgd, 0);
59 init_pte = pte_offset_map_nested(init_pmd, 0);
60 set_pte(new_pte, *init_pte);
61 pte_unmap_nested(init_pte);
62 pte_unmap(new_pte);
63 }
64
65 return new_pgd;
66
67no_pte:
68 pmd_free(new_pmd);
69no_pmd:
70 free_pages((unsigned long)new_pgd, 2);
71no_pgd:
72 return NULL;
73}
74
75void free_pgd_slow(pgd_t *pgd)
76{
77 pmd_t *pmd;
78 struct page *pte;
79
80 if (!pgd)
81 return;
82
83 /* pgd is always present and good */
84 pmd = pmd_off(pgd, 0);
85 if (pmd_none(*pmd))
86 goto free;
87 if (pmd_bad(*pmd)) {
88 pmd_ERROR(*pmd);
89 pmd_clear(pmd);
90 goto free;
91 }
92
93 pte = pmd_page(*pmd);
94 pmd_clear(pmd);
95 dec_zone_page_state(virt_to_page((unsigned long *)pgd), NR_PAGETABLE);
96 pte_lock_deinit(pte);
97 pte_free(pte);
98 pmd_free(pmd);
99free:
100 free_pages((unsigned long) pgd, 2);
101}
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
new file mode 100644
index 000000000000..40713818a87b
--- /dev/null
+++ b/arch/arm/mm/proc-arm740.S
@@ -0,0 +1,174 @@
1/*
2 * linux/arch/arm/mm/arm740.S: utility functions for ARM740
3 *
4 * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11#include <linux/linkage.h>
12#include <linux/init.h>
13#include <asm/assembler.h>
14#include <asm/asm-offsets.h>
15#include <asm/pgtable-hwdef.h>
16#include <asm/pgtable.h>
17#include <asm/procinfo.h>
18#include <asm/ptrace.h>
19
20 .text
21/*
22 * cpu_arm740_proc_init()
23 * cpu_arm740_do_idle()
24 * cpu_arm740_dcache_clean_area()
25 * cpu_arm740_switch_mm()
26 *
27 * These are not required.
28 */
29ENTRY(cpu_arm740_proc_init)
30ENTRY(cpu_arm740_do_idle)
31ENTRY(cpu_arm740_dcache_clean_area)
32ENTRY(cpu_arm740_switch_mm)
33 mov pc, lr
34
35/*
36 * cpu_arm740_proc_fin()
37 */
38ENTRY(cpu_arm740_proc_fin)
39 stmfd sp!, {lr}
40 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
41 msr cpsr_c, ip
42 mrc p15, 0, r0, c1, c0, 0
43 bic r0, r0, #0x3f000000 @ bank/f/lock/s
44 bic r0, r0, #0x0000000c @ w-buffer/cache
45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
46 mcr p15, 0, r0, c7, c0, 0 @ invalidate cache
47 ldmfd sp!, {pc}
48
49/*
50 * cpu_arm740_reset(loc)
51 * Params : r0 = address to jump to
52 * Notes : This sets up everything for a reset
53 */
54ENTRY(cpu_arm740_reset)
55 mov ip, #0
56 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
57 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
58 bic ip, ip, #0x0000000c @ ............wc..
59 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
60 mov pc, r0
61
62 __INIT
63
64 .type __arm740_setup, #function
65__arm740_setup:
66 mov r0, #0
67 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
68
69 mcr p15, 0, r0, c6, c3 @ disable area 3~7
70 mcr p15, 0, r0, c6, c4
71 mcr p15, 0, r0, c6, c5
72 mcr p15, 0, r0, c6, c6
73 mcr p15, 0, r0, c6, c7
74
75 mov r0, #0x0000003F @ base = 0, size = 4GB
76 mcr p15, 0, r0, c6, c0 @ set area 0, default
77
78 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
79 ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
80 mov r2, #10 @ 11 is the minimum (4KB)
811: add r2, r2, #1 @ area size *= 2
82 mov r1, r1, lsr #1
83 bne 1b @ count not zero r-shift
84 orr r0, r0, r2, lsl #1 @ the area register value
85 orr r0, r0, #1 @ set enable bit
86 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
87
88 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
89 ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
90 mov r2, #10 @ 11 is the minimum (4KB)
911: add r2, r2, #1 @ area size *= 2
92 mov r1, r1, lsr #1
93 bne 1b @ count not zero r-shift
94 orr r0, r0, r2, lsl #1 @ the area register value
95 orr r0, r0, #1 @ set enable bit
96 mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
97
98 mov r0, #0x06
99 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
100#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
101 mov r0, #0x00 @ disable whole write buffer
102#else
103 mov r0, #0x02 @ Region 1 write bufferred
104#endif
105 mcr p15, 0, r0, c3, c0
106
107 mov r0, #0x10000
108 sub r0, r0, #1 @ r0 = 0xffff
109 mcr p15, 0, r0, c5, c0 @ all read/write access
110
111 mrc p15, 0, r0, c1, c0 @ get control register
112 bic r0, r0, #0x3F000000 @ set to standard caching mode
113 @ need some benchmark
114 orr r0, r0, #0x0000000d @ MPU/Cache/WB
115
116 mov pc, lr
117
118 .size __arm740_setup, . - __arm740_setup
119
120 __INITDATA
121
122/*
123 * Purpose : Function pointers used to access above functions - all calls
124 * come through these
125 */
126 .type arm740_processor_functions, #object
127ENTRY(arm740_processor_functions)
128 .word v4t_late_abort
129 .word cpu_arm740_proc_init
130 .word cpu_arm740_proc_fin
131 .word cpu_arm740_reset
132 .word cpu_arm740_do_idle
133 .word cpu_arm740_dcache_clean_area
134 .word cpu_arm740_switch_mm
135 .word 0 @ cpu_*_set_pte
136 .size arm740_processor_functions, . - arm740_processor_functions
137
138 .section ".rodata"
139
140 .type cpu_arch_name, #object
141cpu_arch_name:
142 .asciz "armv4"
143 .size cpu_arch_name, . - cpu_arch_name
144
145 .type cpu_elf_name, #object
146cpu_elf_name:
147 .asciz "v4"
148 .size cpu_elf_name, . - cpu_elf_name
149
150 .type cpu_arm740_name, #object
151cpu_arm740_name:
152 .ascii "ARM740T"
153 .size cpu_arm740_name, . - cpu_arm740_name
154
155 .align
156
157 .section ".proc.info.init", #alloc, #execinstr
158 .type __arm740_proc_info,#object
159__arm740_proc_info:
160 .long 0x41807400
161 .long 0xfffffff0
162 .long 0
163 b __arm740_setup
164 .long cpu_arch_name
165 .long cpu_elf_name
166 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT
167 .long cpu_arm740_name
168 .long arm740_processor_functions
169 .long 0
170 .long 0
171 .long v3_cache_fns @ cache model
172 .size __arm740_proc_info, . - __arm740_proc_info
173
174
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
new file mode 100644
index 000000000000..22d7e3100ea6
--- /dev/null
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -0,0 +1,249 @@
1/*
2 * linux/arch/arm/mm/proc-arm7tdmi.S: utility functions for ARM7TDMI
3 *
4 * Copyright (C) 2003-2006 Hyok S. Choi <hyok.choi@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11#include <linux/linkage.h>
12#include <linux/init.h>
13#include <asm/assembler.h>
14#include <asm/asm-offsets.h>
15#include <asm/pgtable-hwdef.h>
16#include <asm/pgtable.h>
17#include <asm/procinfo.h>
18#include <asm/ptrace.h>
19
20 .text
21/*
22 * cpu_arm7tdmi_proc_init()
23 * cpu_arm7tdmi_do_idle()
24 * cpu_arm7tdmi_dcache_clean_area()
25 * cpu_arm7tdmi_switch_mm()
26 *
27 * These are not required.
28 */
29ENTRY(cpu_arm7tdmi_proc_init)
30ENTRY(cpu_arm7tdmi_do_idle)
31ENTRY(cpu_arm7tdmi_dcache_clean_area)
32ENTRY(cpu_arm7tdmi_switch_mm)
33 mov pc, lr
34
35/*
36 * cpu_arm7tdmi_proc_fin()
37 */
38ENTRY(cpu_arm7tdmi_proc_fin)
39 mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
40 msr cpsr_c, r0
41 mov pc, lr
42
43/*
44 * Function: cpu_arm7tdmi_reset(loc)
45 * Params : loc(r0) address to jump to
46 * Purpose : Sets up everything for a reset and jump to the location for soft reset.
47 */
48ENTRY(cpu_arm7tdmi_reset)
49 mov pc, r0
50
51 __INIT
52
53 .type __arm7tdmi_setup, #function
54__arm7tdmi_setup:
55 mov pc, lr
56 .size __arm7tdmi_setup, . - __arm7tdmi_setup
57
58 __INITDATA
59
60/*
61 * Purpose : Function pointers used to access above functions - all calls
62 * come through these
63 */
64 .type arm7tdmi_processor_functions, #object
65ENTRY(arm7tdmi_processor_functions)
66 .word v4t_late_abort
67 .word cpu_arm7tdmi_proc_init
68 .word cpu_arm7tdmi_proc_fin
69 .word cpu_arm7tdmi_reset
70 .word cpu_arm7tdmi_do_idle
71 .word cpu_arm7tdmi_dcache_clean_area
72 .word cpu_arm7tdmi_switch_mm
73 .word 0 @ cpu_*_set_pte
74 .size arm7tdmi_processor_functions, . - arm7tdmi_processor_functions
75
76 .section ".rodata"
77
78 .type cpu_arch_name, #object
79cpu_arch_name:
80 .asciz "armv4t"
81 .size cpu_arch_name, . - cpu_arch_name
82
83 .type cpu_elf_name, #object
84cpu_elf_name:
85 .asciz "v4"
86 .size cpu_elf_name, . - cpu_elf_name
87
88 .type cpu_arm7tdmi_name, #object
89cpu_arm7tdmi_name:
90 .asciz "ARM7TDMI"
91 .size cpu_arm7tdmi_name, . - cpu_arm7tdmi_name
92
93 .type cpu_triscenda7_name, #object
94cpu_triscenda7_name:
95 .asciz "Triscend-A7x"
96 .size cpu_triscenda7_name, . - cpu_triscenda7_name
97
98 .type cpu_at91_name, #object
99cpu_at91_name:
100 .asciz "Atmel-AT91M40xxx"
101 .size cpu_at91_name, . - cpu_at91_name
102
103 .type cpu_s3c3410_name, #object
104cpu_s3c3410_name:
105 .asciz "Samsung-S3C3410"
106 .size cpu_s3c3410_name, . - cpu_s3c3410_name
107
108 .type cpu_s3c44b0x_name, #object
109cpu_s3c44b0x_name:
110 .asciz "Samsung-S3C44B0x"
111 .size cpu_s3c44b0x_name, . - cpu_s3c44b0x_name
112
113 .type cpu_s3c4510b, #object
114cpu_s3c4510b_name:
115 .asciz "Samsung-S3C4510B"
116 .size cpu_s3c4510b_name, . - cpu_s3c4510b_name
117
118 .type cpu_s3c4530_name, #object
119cpu_s3c4530_name:
120 .asciz "Samsung-S3C4530"
121 .size cpu_s3c4530_name, . - cpu_s3c4530_name
122
123 .type cpu_netarm_name, #object
124cpu_netarm_name:
125 .asciz "NETARM"
126 .size cpu_netarm_name, . - cpu_netarm_name
127
128 .align
129
130 .section ".proc.info.init", #alloc, #execinstr
131
132 .type __arm7tdmi_proc_info, #object
133__arm7tdmi_proc_info:
134 .long 0x41007700
135 .long 0xfff8ff00
136 .long 0
137 .long 0
138 b __arm7tdmi_setup
139 .long cpu_arch_name
140 .long cpu_elf_name
141 .long HWCAP_SWP | HWCAP_26BIT
142 .long cpu_arm7tdmi_name
143 .long arm7tdmi_processor_functions
144 .long 0
145 .long 0
146 .long v4_cache_fns
147 .size __arm7tdmi_proc_info, . - __arm7dmi_proc_info
148
149 .type __triscenda7_proc_info, #object
150__triscenda7_proc_info:
151 .long 0x0001d2ff
152 .long 0x0001ffff
153 .long 0
154 .long 0
155 b __arm7tdmi_setup
156 .long cpu_arch_name
157 .long cpu_elf_name
158 .long HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT
159 .long cpu_triscenda7_name
160 .long arm7tdmi_processor_functions
161 .long 0
162 .long 0
163 .long v4_cache_fns
164 .size __triscenda7_proc_info, . - __triscenda7_proc_info
165
166 .type __at91_proc_info, #object
167__at91_proc_info:
168 .long 0x14000040
169 .long 0xfff000e0
170 .long 0
171 .long 0
172 b __arm7tdmi_setup
173 .long cpu_arch_name
174 .long cpu_elf_name
175 .long HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT
176 .long cpu_at91_name
177 .long arm7tdmi_processor_functions
178 .long 0
179 .long 0
180 .long v4_cache_fns
181 .size __at91_proc_info, . - __at91_proc_info
182
183 .type __s3c4510b_proc_info, #object
184__s3c4510b_proc_info:
185 .long 0x36365000
186 .long 0xfffff000
187 .long 0
188 .long 0
189 b __arm7tdmi_setup
190 .long cpu_arch_name
191 .long cpu_elf_name
192 .long HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT
193 .long cpu_s3c4510b_name
194 .long arm7tdmi_processor_functions
195 .long 0
196 .long 0
197 .long v4_cache_fns
198 .size __s3c4510b_proc_info, . - __s3c4510b_proc_info
199
200 .type __s3c4530_proc_info, #object
201__s3c4530_proc_info:
202 .long 0x4c000000
203 .long 0xfff000e0
204 .long 0
205 .long 0
206 b __arm7tdmi_setup
207 .long cpu_arch_name
208 .long cpu_elf_name
209 .long HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT
210 .long cpu_s3c4530_name
211 .long arm7tdmi_processor_functions
212 .long 0
213 .long 0
214 .long v4_cache_fns
215 .size __s3c4530_proc_info, . - __s3c4530_proc_info
216
217 .type __s3c3410_proc_info, #object
218__s3c3410_proc_info:
219 .long 0x34100000
220 .long 0xffff0000
221 .long 0
222 .long 0
223 b __arm7tdmi_setup
224 .long cpu_arch_name
225 .long cpu_elf_name
226 .long HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT
227 .long cpu_s3c3410_name
228 .long arm7tdmi_processor_functions
229 .long 0
230 .long 0
231 .long v4_cache_fns
232 .size __s3c3410_proc_info, . - __s3c3410_proc_info
233
234 .type __s3c44b0x_proc_info, #object
235__s3c44b0x_proc_info:
236 .long 0x44b00000
237 .long 0xffff0000
238 .long 0
239 .long 0
240 b __arm7tdmi_setup
241 .long cpu_arch_name
242 .long cpu_elf_name
243 .long HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT
244 .long cpu_s3c44b0x_name
245 .long arm7tdmi_processor_functions
246 .long 0
247 .long 0
248 .long v4_cache_fns
249 .size __s3c44b0x_proc_info, . - __s3c44b0x_proc_info
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
new file mode 100644
index 000000000000..2397f4b6e151
--- /dev/null
+++ b/arch/arm/mm/proc-arm940.S
@@ -0,0 +1,369 @@
1/*
2 * linux/arch/arm/mm/arm940.S: utility functions for ARM940T
3 *
4 * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11#include <linux/linkage.h>
12#include <linux/init.h>
13#include <asm/assembler.h>
14#include <asm/pgtable-hwdef.h>
15#include <asm/pgtable.h>
16#include <asm/procinfo.h>
17#include <asm/ptrace.h>
18
19/* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
20#define CACHE_DLINESIZE 16
21#define CACHE_DSEGMENTS 4
22#define CACHE_DENTRIES 64
23
24 .text
25/*
26 * cpu_arm940_proc_init()
27 * cpu_arm940_switch_mm()
28 *
29 * These are not required.
30 */
31ENTRY(cpu_arm940_proc_init)
32ENTRY(cpu_arm940_switch_mm)
33 mov pc, lr
34
35/*
36 * cpu_arm940_proc_fin()
37 */
38ENTRY(cpu_arm940_proc_fin)
39 stmfd sp!, {lr}
40 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
41 msr cpsr_c, ip
42 bl arm940_flush_kern_cache_all
43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 bic r0, r0, #0x00001000 @ i-cache
45 bic r0, r0, #0x00000004 @ d-cache
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
47 ldmfd sp!, {pc}
48
49/*
50 * cpu_arm940_reset(loc)
51 * Params : r0 = address to jump to
52 * Notes : This sets up everything for a reset
53 */
54ENTRY(cpu_arm940_reset)
55 mov ip, #0
56 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
57 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
58 mcr p15, 0, ip, c7, c10, 4 @ drain WB
59 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
60 bic ip, ip, #0x00000005 @ .............c.p
61 bic ip, ip, #0x00001000 @ i-cache
62 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
63 mov pc, r0
64
65/*
66 * cpu_arm940_do_idle()
67 */
68 .align 5
69ENTRY(cpu_arm940_do_idle)
70 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
71 mov pc, lr
72
73/*
74 * flush_user_cache_all()
75 */
76ENTRY(arm940_flush_user_cache_all)
77 /* FALLTHROUGH */
78
79/*
80 * flush_kern_cache_all()
81 *
82 * Clean and invalidate the entire cache.
83 */
84ENTRY(arm940_flush_kern_cache_all)
85 mov r2, #VM_EXEC
86 /* FALLTHROUGH */
87
88/*
89 * flush_user_cache_range(start, end, flags)
90 *
91 * There is no efficient way to flush a range of cache entries
92 * in the specified address range. Thus, flushes all.
93 *
94 * - start - start address (inclusive)
95 * - end - end address (exclusive)
96 * - flags - vm_flags describing address space
97 */
98ENTRY(arm940_flush_user_cache_range)
99 mov ip, #0
100#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
101 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
102#else
103 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
1041: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
1052: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
106 subs r3, r3, #1 << 26
107 bcs 2b @ entries 63 to 0
108 subs r1, r1, #1 << 4
109 bcs 1b @ segments 3 to 0
110#endif
111 tst r2, #VM_EXEC
112 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
113 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
114 mov pc, lr
115
116/*
117 * coherent_kern_range(start, end)
118 *
119 * Ensure coherency between the Icache and the Dcache in the
120 * region described by start, end. If you have non-snooping
121 * Harvard caches, you need to implement this function.
122 *
123 * - start - virtual start address
124 * - end - virtual end address
125 */
126ENTRY(arm940_coherent_kern_range)
127 /* FALLTHROUGH */
128
129/*
130 * coherent_user_range(start, end)
131 *
132 * Ensure coherency between the Icache and the Dcache in the
133 * region described by start, end. If you have non-snooping
134 * Harvard caches, you need to implement this function.
135 *
136 * - start - virtual start address
137 * - end - virtual end address
138 */
139ENTRY(arm940_coherent_user_range)
140 /* FALLTHROUGH */
141
142/*
143 * flush_kern_dcache_page(void *page)
144 *
145 * Ensure no D cache aliasing occurs, either with itself or
146 * the I cache
147 *
148 * - addr - page aligned address
149 */
150ENTRY(arm940_flush_kern_dcache_page)
151 mov ip, #0
152 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
1531: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
1542: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
155 subs r3, r3, #1 << 26
156 bcs 2b @ entries 63 to 0
157 subs r1, r1, #1 << 4
158 bcs 1b @ segments 7 to 0
159 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
160 mcr p15, 0, ip, c7, c10, 4 @ drain WB
161 mov pc, lr
162
163/*
164 * dma_inv_range(start, end)
165 *
166 * There is no efficient way to invalidate a specifid virtual
167 * address range. Thus, invalidates all.
168 *
169 * - start - virtual start address
170 * - end - virtual end address
171 */
172ENTRY(arm940_dma_inv_range)
173 mov ip, #0
174 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
1751: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
1762: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
177 subs r3, r3, #1 << 26
178 bcs 2b @ entries 63 to 0
179 subs r1, r1, #1 << 4
180 bcs 1b @ segments 7 to 0
181 mcr p15, 0, ip, c7, c10, 4 @ drain WB
182 mov pc, lr
183
184/*
185 * dma_clean_range(start, end)
186 *
187 * There is no efficient way to clean a specifid virtual
188 * address range. Thus, cleans all.
189 *
190 * - start - virtual start address
191 * - end - virtual end address
192 */
193ENTRY(arm940_dma_clean_range)
194ENTRY(cpu_arm940_dcache_clean_area)
195 mov ip, #0
196#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
197 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
1981: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
1992: mcr p15, 0, r3, c7, c10, 2 @ clean D entry
200 subs r3, r3, #1 << 26
201 bcs 2b @ entries 63 to 0
202 subs r1, r1, #1 << 4
203 bcs 1b @ segments 7 to 0
204#endif
205 mcr p15, 0, ip, c7, c10, 4 @ drain WB
206 mov pc, lr
207
208/*
209 * dma_flush_range(start, end)
210 *
211 * There is no efficient way to clean and invalidate a specifid
212 * virtual address range.
213 *
214 * - start - virtual start address
215 * - end - virtual end address
216 */
217ENTRY(arm940_dma_flush_range)
218 mov ip, #0
219 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
2201: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2212:
222#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
223 mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
224#else
225 mcr p15, 0, r3, c7, c10, 2 @ clean D entry
226#endif
227 subs r3, r3, #1 << 26
228 bcs 2b @ entries 63 to 0
229 subs r1, r1, #1 << 4
230 bcs 1b @ segments 7 to 0
231 mcr p15, 0, ip, c7, c10, 4 @ drain WB
232 mov pc, lr
233
234ENTRY(arm940_cache_fns)
235 .long arm940_flush_kern_cache_all
236 .long arm940_flush_user_cache_all
237 .long arm940_flush_user_cache_range
238 .long arm940_coherent_kern_range
239 .long arm940_coherent_user_range
240 .long arm940_flush_kern_dcache_page
241 .long arm940_dma_inv_range
242 .long arm940_dma_clean_range
243 .long arm940_dma_flush_range
244
245 __INIT
246
247 .type __arm940_setup, #function
248__arm940_setup:
249 mov r0, #0
250 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
251 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
252 mcr p15, 0, r0, c7, c10, 4 @ drain WB
253
254 mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
255 mcr p15, 0, r0, c6, c4, 0
256 mcr p15, 0, r0, c6, c5, 0
257 mcr p15, 0, r0, c6, c6, 0
258 mcr p15, 0, r0, c6, c7, 0
259
260 mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7
261 mcr p15, 0, r0, c6, c4, 1
262 mcr p15, 0, r0, c6, c5, 1
263 mcr p15, 0, r0, c6, c6, 1
264 mcr p15, 0, r0, c6, c7, 1
265
266 mov r0, #0x0000003F @ base = 0, size = 4GB
267 mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
268 mcr p15, 0, r0, c6, c0, 1
269
270 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
271 ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
272 mov r2, #10 @ 11 is the minimum (4KB)
2731: add r2, r2, #1 @ area size *= 2
274 mov r1, r1, lsr #1
275 bne 1b @ count not zero r-shift
276 orr r0, r0, r2, lsl #1 @ the area register value
277 orr r0, r0, #1 @ set enable bit
278 mcr p15, 0, r0, c6, c1, 0 @ set area 1, RAM
279 mcr p15, 0, r0, c6, c1, 1
280
281 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
282 ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
283 mov r2, #10 @ 11 is the minimum (4KB)
2841: add r2, r2, #1 @ area size *= 2
285 mov r1, r1, lsr #1
286 bne 1b @ count not zero r-shift
287 orr r0, r0, r2, lsl #1 @ the area register value
288 orr r0, r0, #1 @ set enable bit
289 mcr p15, 0, r0, c6, c2, 0 @ set area 2, ROM/FLASH
290 mcr p15, 0, r0, c6, c2, 1
291
292 mov r0, #0x06
293 mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
294 mcr p15, 0, r0, c2, c0, 1
295#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
296 mov r0, #0x00 @ disable whole write buffer
297#else
298 mov r0, #0x02 @ Region 1 write bufferred
299#endif
300 mcr p15, 0, r0, c3, c0, 0
301
302 mov r0, #0x10000
303 sub r0, r0, #1 @ r0 = 0xffff
304 mcr p15, 0, r0, c5, c0, 0 @ all read/write access
305 mcr p15, 0, r0, c5, c0, 1
306
307 mrc p15, 0, r0, c1, c0 @ get control register
308 orr r0, r0, #0x00001000 @ I-cache
309 orr r0, r0, #0x00000005 @ MPU/D-cache
310
311 mov pc, lr
312
313 .size __arm940_setup, . - __arm940_setup
314
315 __INITDATA
316
317/*
318 * Purpose : Function pointers used to access above functions - all calls
319 * come through these
320 */
321 .type arm940_processor_functions, #object
322ENTRY(arm940_processor_functions)
323 .word nommu_early_abort
324 .word cpu_arm940_proc_init
325 .word cpu_arm940_proc_fin
326 .word cpu_arm940_reset
327 .word cpu_arm940_do_idle
328 .word cpu_arm940_dcache_clean_area
329 .word cpu_arm940_switch_mm
330 .word 0 @ cpu_*_set_pte
331 .size arm940_processor_functions, . - arm940_processor_functions
332
333 .section ".rodata"
334
335.type cpu_arch_name, #object
336cpu_arch_name:
337 .asciz "armv4t"
338 .size cpu_arch_name, . - cpu_arch_name
339
340 .type cpu_elf_name, #object
341cpu_elf_name:
342 .asciz "v4"
343 .size cpu_elf_name, . - cpu_elf_name
344
345 .type cpu_arm940_name, #object
346cpu_arm940_name:
347 .ascii "ARM940T"
348 .size cpu_arm940_name, . - cpu_arm940_name
349
350 .align
351
352 .section ".proc.info.init", #alloc, #execinstr
353
354 .type __arm940_proc_info,#object
355__arm940_proc_info:
356 .long 0x41009400
357 .long 0xff00fff0
358 .long 0
359 b __arm940_setup
360 .long cpu_arch_name
361 .long cpu_elf_name
362 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
363 .long cpu_arm940_name
364 .long arm940_processor_functions
365 .long 0
366 .long 0
367 .long arm940_cache_fns
368 .size __arm940_proc_info, . - __arm940_proc_info
369
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
new file mode 100644
index 000000000000..e18617564421
--- /dev/null
+++ b/arch/arm/mm/proc-arm946.S
@@ -0,0 +1,424 @@
1/*
2 * linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S
3 *
4 * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
5 *
6 * (Many of cache codes are from proc-arm926.S)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13#include <linux/linkage.h>
14#include <linux/init.h>
15#include <asm/assembler.h>
16#include <asm/pgtable-hwdef.h>
17#include <asm/pgtable.h>
18#include <asm/procinfo.h>
19#include <asm/ptrace.h>
20
21/*
22 * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
23 * comprising 256 lines of 32 bytes (8 words).
24 */
25#define CACHE_DSIZE (CONFIG_CPU_DCACHE_SIZE) /* typically 8KB. */
26#define CACHE_DLINESIZE 32 /* fixed */
27#define CACHE_DSEGMENTS 4 /* fixed */
28#define CACHE_DENTRIES (CACHE_DSIZE / CACHE_DSEGMENTS / CACHE_DLINESIZE)
29#define CACHE_DLIMIT (CACHE_DSIZE * 4) /* benchmark needed */
30
31 .text
32/*
33 * cpu_arm946_proc_init()
34 * cpu_arm946_switch_mm()
35 *
36 * These are not required.
37 */
38ENTRY(cpu_arm946_proc_init)
39ENTRY(cpu_arm946_switch_mm)
40 mov pc, lr
41
42/*
43 * cpu_arm946_proc_fin()
44 */
45ENTRY(cpu_arm946_proc_fin)
46 stmfd sp!, {lr}
47 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
48 msr cpsr_c, ip
49 bl arm946_flush_kern_cache_all
50 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
51 bic r0, r0, #0x00001000 @ i-cache
52 bic r0, r0, #0x00000004 @ d-cache
53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
54 ldmfd sp!, {pc}
55
56/*
57 * cpu_arm946_reset(loc)
58 * Params : r0 = address to jump to
59 * Notes : This sets up everything for a reset
60 */
61ENTRY(cpu_arm946_reset)
62 mov ip, #0
63 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
64 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
65 mcr p15, 0, ip, c7, c10, 4 @ drain WB
66 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
67 bic ip, ip, #0x00000005 @ .............c.p
68 bic ip, ip, #0x00001000 @ i-cache
69 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
70 mov pc, r0
71
72/*
73 * cpu_arm946_do_idle()
74 */
75 .align 5
76ENTRY(cpu_arm946_do_idle)
77 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
78 mov pc, lr
79
80/*
81 * flush_user_cache_all()
82 */
83ENTRY(arm946_flush_user_cache_all)
84 /* FALLTHROUGH */
85
86/*
87 * flush_kern_cache_all()
88 *
89 * Clean and invalidate the entire cache.
90 */
91ENTRY(arm946_flush_kern_cache_all)
92 mov r2, #VM_EXEC
93 mov ip, #0
94__flush_whole_cache:
95#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
96 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
97#else
98 mov r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments
991: orr r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries
1002: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
101 subs r3, r3, #1 << 4
102 bcs 2b @ entries n to 0
103 subs r1, r1, #1 << 29
104 bcs 1b @ segments 3 to 0
105#endif
106 tst r2, #VM_EXEC
107 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
108 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
109 mov pc, lr
110
111/*
112 * flush_user_cache_range(start, end, flags)
113 *
114 * Clean and invalidate a range of cache entries in the
115 * specified address range.
116 *
117 * - start - start address (inclusive)
118 * - end - end address (exclusive)
119 * - flags - vm_flags describing address space
120 * (same as arm926)
121 */
122ENTRY(arm946_flush_user_cache_range)
123 mov ip, #0
124 sub r3, r1, r0 @ calculate total size
125 cmp r3, #CACHE_DLIMIT
126 bhs __flush_whole_cache
127
1281: tst r2, #VM_EXEC
129#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
130 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
131 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
132 add r0, r0, #CACHE_DLINESIZE
133 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
134 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
135 add r0, r0, #CACHE_DLINESIZE
136#else
137 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
139 add r0, r0, #CACHE_DLINESIZE
140 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
141 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
142 add r0, r0, #CACHE_DLINESIZE
143#endif
144 cmp r0, r1
145 blo 1b
146 tst r2, #VM_EXEC
147 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
148 mov pc, lr
149
150/*
151 * coherent_kern_range(start, end)
152 *
153 * Ensure coherency between the Icache and the Dcache in the
154 * region described by start, end. If you have non-snooping
155 * Harvard caches, you need to implement this function.
156 *
157 * - start - virtual start address
158 * - end - virtual end address
159 */
160ENTRY(arm946_coherent_kern_range)
161 /* FALLTHROUGH */
162
163/*
164 * coherent_user_range(start, end)
165 *
166 * Ensure coherency between the Icache and the Dcache in the
167 * region described by start, end. If you have non-snooping
168 * Harvard caches, you need to implement this function.
169 *
170 * - start - virtual start address
171 * - end - virtual end address
172 * (same as arm926)
173 */
174ENTRY(arm946_coherent_user_range)
175 bic r0, r0, #CACHE_DLINESIZE - 1
1761: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
177 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
178 add r0, r0, #CACHE_DLINESIZE
179 cmp r0, r1
180 blo 1b
181 mcr p15, 0, r0, c7, c10, 4 @ drain WB
182 mov pc, lr
183
184/*
185 * flush_kern_dcache_page(void *page)
186 *
187 * Ensure no D cache aliasing occurs, either with itself or
188 * the I cache
189 *
190 * - addr - page aligned address
191 * (same as arm926)
192 */
193ENTRY(arm946_flush_kern_dcache_page)
194 add r1, r0, #PAGE_SZ
1951: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
196 add r0, r0, #CACHE_DLINESIZE
197 cmp r0, r1
198 blo 1b
199 mov r0, #0
200 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
201 mcr p15, 0, r0, c7, c10, 4 @ drain WB
202 mov pc, lr
203
204/*
205 * dma_inv_range(start, end)
206 *
207 * Invalidate (discard) the specified virtual address range.
208 * May not write back any entries. If 'start' or 'end'
209 * are not cache line aligned, those lines must be written
210 * back.
211 *
212 * - start - virtual start address
213 * - end - virtual end address
214 * (same as arm926)
215 */
216ENTRY(arm946_dma_inv_range)
217#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
218 tst r0, #CACHE_DLINESIZE - 1
219 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
220 tst r1, #CACHE_DLINESIZE - 1
221 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
222#endif
223 bic r0, r0, #CACHE_DLINESIZE - 1
2241: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
225 add r0, r0, #CACHE_DLINESIZE
226 cmp r0, r1
227 blo 1b
228 mcr p15, 0, r0, c7, c10, 4 @ drain WB
229 mov pc, lr
230
231/*
232 * dma_clean_range(start, end)
233 *
234 * Clean the specified virtual address range.
235 *
236 * - start - virtual start address
237 * - end - virtual end address
238 *
239 * (same as arm926)
240 */
241ENTRY(arm946_dma_clean_range)
242#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
243 bic r0, r0, #CACHE_DLINESIZE - 1
2441: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
245 add r0, r0, #CACHE_DLINESIZE
246 cmp r0, r1
247 blo 1b
248#endif
249 mcr p15, 0, r0, c7, c10, 4 @ drain WB
250 mov pc, lr
251
252/*
253 * dma_flush_range(start, end)
254 *
255 * Clean and invalidate the specified virtual address range.
256 *
257 * - start - virtual start address
258 * - end - virtual end address
259 *
260 * (same as arm926)
261 */
262ENTRY(arm946_dma_flush_range)
263 bic r0, r0, #CACHE_DLINESIZE - 1
2641:
265#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
266 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
267#else
268 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
269#endif
270 add r0, r0, #CACHE_DLINESIZE
271 cmp r0, r1
272 blo 1b
273 mcr p15, 0, r0, c7, c10, 4 @ drain WB
274 mov pc, lr
275
276ENTRY(arm946_cache_fns)
277 .long arm946_flush_kern_cache_all
278 .long arm946_flush_user_cache_all
279 .long arm946_flush_user_cache_range
280 .long arm946_coherent_kern_range
281 .long arm946_coherent_user_range
282 .long arm946_flush_kern_dcache_page
283 .long arm946_dma_inv_range
284 .long arm946_dma_clean_range
285 .long arm946_dma_flush_range
286
287
288ENTRY(cpu_arm946_dcache_clean_area)
289#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
2901: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
291 add r0, r0, #CACHE_DLINESIZE
292 subs r1, r1, #CACHE_DLINESIZE
293 bhi 1b
294#endif
295 mcr p15, 0, r0, c7, c10, 4 @ drain WB
296 mov pc, lr
297
298 __INIT
299
300 .type __arm946_setup, #function
301__arm946_setup:
302 mov r0, #0
303 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
304 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
305 mcr p15, 0, r0, c7, c10, 4 @ drain WB
306
307 mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7
308 mcr p15, 0, r0, c6, c4, 0
309 mcr p15, 0, r0, c6, c5, 0
310 mcr p15, 0, r0, c6, c6, 0
311 mcr p15, 0, r0, c6, c7, 0
312
313 mov r0, #0x0000003F @ base = 0, size = 4GB
314 mcr p15, 0, r0, c6, c0, 0 @ set region 0, default
315
316 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
317 ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
318 mov r2, #10 @ 11 is the minimum (4KB)
3191: add r2, r2, #1 @ area size *= 2
320 mov r1, r1, lsr #1
321 bne 1b @ count not zero r-shift
322 orr r0, r0, r2, lsl #1 @ the region register value
323 orr r0, r0, #1 @ set enable bit
324 mcr p15, 0, r0, c6, c1, 0 @ set region 1, RAM
325
326 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
327 ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
328 mov r2, #10 @ 11 is the minimum (4KB)
3291: add r2, r2, #1 @ area size *= 2
330 mov r1, r1, lsr #1
331 bne 1b @ count not zero r-shift
332 orr r0, r0, r2, lsl #1 @ the region register value
333 orr r0, r0, #1 @ set enable bit
334 mcr p15, 0, r0, c6, c2, 0 @ set region 2, ROM/FLASH
335
336 mov r0, #0x06
337 mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
338 mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
339#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
340 mov r0, #0x00 @ disable whole write buffer
341#else
342 mov r0, #0x02 @ region 1 write bufferred
343#endif
344 mcr p15, 0, r0, c3, c0, 0
345
346/*
347 * Access Permission Settings for future permission control by PU.
348 *
349 * priv. user
350 * region 0 (whole) rw -- : b0001
351 * region 1 (RAM) rw rw : b0011
352 * region 2 (FLASH) rw r- : b0010
353 * region 3~7 (none) -- -- : b0000
354 */
355 mov r0, #0x00000031
356 orr r0, r0, #0x00000200
357 mcr p15, 0, r0, c5, c0, 2 @ set data access permission
358 mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission
359
360 mrc p15, 0, r0, c1, c0 @ get control register
361 orr r0, r0, #0x00001000 @ I-cache
362 orr r0, r0, #0x00000005 @ MPU/D-cache
363#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
364 orr r0, r0, #0x00004000 @ .1.. .... .... ....
365#endif
366 mov pc, lr
367
368 .size __arm946_setup, . - __arm946_setup
369
370 __INITDATA
371
372/*
373 * Purpose : Function pointers used to access above functions - all calls
374 * come through these
375 */
376 .type arm946_processor_functions, #object
377ENTRY(arm946_processor_functions)
378 .word nommu_early_abort
379 .word cpu_arm946_proc_init
380 .word cpu_arm946_proc_fin
381 .word cpu_arm946_reset
382 .word cpu_arm946_do_idle
383
384 .word cpu_arm946_dcache_clean_area
385 .word cpu_arm946_switch_mm
386 .word 0 @ cpu_*_set_pte
387 .size arm946_processor_functions, . - arm946_processor_functions
388
389 .section ".rodata"
390
391 .type cpu_arch_name, #object
392cpu_arch_name:
393 .asciz "armv5te"
394 .size cpu_arch_name, . - cpu_arch_name
395
396 .type cpu_elf_name, #object
397cpu_elf_name:
398 .asciz "v5t"
399 .size cpu_elf_name, . - cpu_elf_name
400
401 .type cpu_arm946_name, #object
402cpu_arm946_name:
403 .ascii "ARM946E-S"
404 .size cpu_arm946_name, . - cpu_arm946_name
405
406 .align
407
408 .section ".proc.info.init", #alloc, #execinstr
409 .type __arm946_proc_info,#object
410__arm946_proc_info:
411 .long 0x41009460
412 .long 0xff00fff0
413 .long 0
414 b __arm946_setup
415 .long cpu_arch_name
416 .long cpu_elf_name
417 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
418 .long cpu_arm946_name
419 .long arm946_processor_functions
420 .long 0
421 .long 0
422 .long arm940_cache_fns
423 .size __arm946_proc_info, . - __arm946_proc_info
424
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
new file mode 100644
index 000000000000..918ebf65d4f6
--- /dev/null
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -0,0 +1,134 @@
1/*
2 * linux/arch/arm/mm/proc-arm9tdmi.S: utility functions for ARM9TDMI
3 *
4 * Copyright (C) 2003-2006 Hyok S. Choi <hyok.choi@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11#include <linux/linkage.h>
12#include <linux/init.h>
13#include <asm/assembler.h>
14#include <asm/asm-offsets.h>
15#include <asm/pgtable-hwdef.h>
16#include <asm/pgtable.h>
17#include <asm/procinfo.h>
18#include <asm/ptrace.h>
19
20 .text
21/*
22 * cpu_arm9tdmi_proc_init()
23 * cpu_arm9tdmi_do_idle()
24 * cpu_arm9tdmi_dcache_clean_area()
25 * cpu_arm9tdmi_switch_mm()
26 *
27 * These are not required.
28 */
29ENTRY(cpu_arm9tdmi_proc_init)
30ENTRY(cpu_arm9tdmi_do_idle)
31ENTRY(cpu_arm9tdmi_dcache_clean_area)
32ENTRY(cpu_arm9tdmi_switch_mm)
33 mov pc, lr
34
35/*
36 * cpu_arm9tdmi_proc_fin()
37 */
38ENTRY(cpu_arm9tdmi_proc_fin)
39 mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
40 msr cpsr_c, r0
41 mov pc, lr
42
43/*
44 * Function: cpu_arm9tdmi_reset(loc)
45 * Params : loc(r0) address to jump to
46 * Purpose : Sets up everything for a reset and jump to the location for soft reset.
47 */
48ENTRY(cpu_arm9tdmi_reset)
49 mov pc, r0
50
51 __INIT
52
53 .type __arm9tdmi_setup, #function
54__arm9tdmi_setup:
55 mov pc, lr
56 .size __arm9tdmi_setup, . - __arm9tdmi_setup
57
58 __INITDATA
59
60/*
61 * Purpose : Function pointers used to access above functions - all calls
62 * come through these
63 */
64 .type arm9tdmi_processor_functions, #object
65ENTRY(arm9tdmi_processor_functions)
66 .word nommu_early_abort
67 .word cpu_arm9tdmi_proc_init
68 .word cpu_arm9tdmi_proc_fin
69 .word cpu_arm9tdmi_reset
70 .word cpu_arm9tdmi_do_idle
71 .word cpu_arm9tdmi_dcache_clean_area
72 .word cpu_arm9tdmi_switch_mm
73 .word 0 @ cpu_*_set_pte
74 .size arm9tdmi_processor_functions, . - arm9tdmi_processor_functions
75
76 .section ".rodata"
77
78 .type cpu_arch_name, #object
79cpu_arch_name:
80 .asciz "armv4t"
81 .size cpu_arch_name, . - cpu_arch_name
82
83 .type cpu_elf_name, #object
84cpu_elf_name:
85 .asciz "v4"
86 .size cpu_elf_name, . - cpu_elf_name
87
88 .type cpu_arm9tdmi_name, #object
89cpu_arm9tdmi_name:
90 .asciz "ARM9TDMI"
91 .size cpu_arm9tdmi_name, . - cpu_arm9tdmi_name
92
93 .type cpu_p2001_name, #object
94cpu_p2001_name:
95 .asciz "P2001"
96 .size cpu_p2001_name, . - cpu_p2001_name
97
98 .align
99
100 .section ".proc.info.init", #alloc, #execinstr
101
102 .type __arm9tdmi_proc_info, #object
103__arm9tdmi_proc_info:
104 .long 0x41009900
105 .long 0xfff8ff00
106 .long 0
107 .long 0
108 b __arm9tdmi_setup
109 .long cpu_arch_name
110 .long cpu_elf_name
111 .long HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT
112 .long cpu_arm9tdmi_name
113 .long arm9tdmi_processor_functions
114 .long 0
115 .long 0
116 .long v4_cache_fns
117 .size __arm9tdmi_proc_info, . - __arm9dmi_proc_info
118
119 .type __p2001_proc_info, #object
120__p2001_proc_info:
121 .long 0x41029000
122 .long 0xffffffff
123 .long 0
124 .long 0
125 b __arm9tdmi_setup
126 .long cpu_arch_name
127 .long cpu_elf_name
128 .long HWCAP_SWP | HWCAP_THUMB | HWCAP_26BIT
129 .long cpu_p2001_name
130 .long arm9tdmi_processor_functions
131 .long 0
132 .long 0
133 .long v4_cache_fns
134 .size __p2001_proc_info, . - __p2001_proc_info
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 3ca0c92e98a2..e8b377d637f6 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -311,12 +311,6 @@ ENTRY(xscale_flush_kern_dcache_page)
311 * - end - virtual end address 311 * - end - virtual end address
312 */ 312 */
313ENTRY(xscale_dma_inv_range) 313ENTRY(xscale_dma_inv_range)
314 mrc p15, 0, r2, c0, c0, 0 @ read ID
315 eor r2, r2, #0x69000000
316 eor r2, r2, #0x00052000
317 bics r2, r2, #1
318 beq xscale_dma_flush_range
319
320 tst r0, #CACHELINESIZE - 1 314 tst r0, #CACHELINESIZE - 1
321 bic r0, r0, #CACHELINESIZE - 1 315 bic r0, r0, #CACHELINESIZE - 1
322 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 316 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -375,6 +369,30 @@ ENTRY(xscale_cache_fns)
375 .long xscale_dma_clean_range 369 .long xscale_dma_clean_range
376 .long xscale_dma_flush_range 370 .long xscale_dma_flush_range
377 371
372/*
373 * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
374 * clear the dirty bits, which means that if we invalidate a dirty line,
375 * the dirty data can still be written back to external memory later on.
376 *
377 * The recommended workaround is to always do a clean D-cache line before
378 * doing an invalidate D-cache line, so on the affected processors,
379 * dma_inv_range() is implemented as dma_flush_range().
380 *
381 * See erratum #25 of "Intel 80200 Processor Specification Update",
382 * revision January 22, 2003, available at:
383 * http://www.intel.com/design/iio/specupdt/273415.htm
384 */
385ENTRY(xscale_80200_A0_A1_cache_fns)
386 .long xscale_flush_kern_cache_all
387 .long xscale_flush_user_cache_all
388 .long xscale_flush_user_cache_range
389 .long xscale_coherent_kern_range
390 .long xscale_coherent_user_range
391 .long xscale_flush_kern_dcache_page
392 .long xscale_dma_flush_range
393 .long xscale_dma_clean_range
394 .long xscale_dma_flush_range
395
378ENTRY(cpu_xscale_dcache_clean_area) 396ENTRY(cpu_xscale_dcache_clean_area)
3791: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3971: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
380 add r0, r0, #CACHELINESIZE 398 add r0, r0, #CACHELINESIZE
@@ -531,6 +549,11 @@ cpu_elf_name:
531 .asciz "v5" 549 .asciz "v5"
532 .size cpu_elf_name, . - cpu_elf_name 550 .size cpu_elf_name, . - cpu_elf_name
533 551
552 .type cpu_80200_A0_A1_name, #object
553cpu_80200_A0_A1_name:
554 .asciz "XScale-80200 A0/A1"
555 .size cpu_80200_A0_A1_name, . - cpu_80200_A0_A1_name
556
534 .type cpu_80200_name, #object 557 .type cpu_80200_name, #object
535cpu_80200_name: 558cpu_80200_name:
536 .asciz "XScale-80200" 559 .asciz "XScale-80200"
@@ -595,6 +618,29 @@ cpu_pxa270_name:
595 618
596 .section ".proc.info.init", #alloc, #execinstr 619 .section ".proc.info.init", #alloc, #execinstr
597 620
621 .type __80200_A0_A1_proc_info,#object
622__80200_A0_A1_proc_info:
623 .long 0x69052000
624 .long 0xfffffffe
625 .long PMD_TYPE_SECT | \
626 PMD_SECT_BUFFERABLE | \
627 PMD_SECT_CACHEABLE | \
628 PMD_SECT_AP_WRITE | \
629 PMD_SECT_AP_READ
630 .long PMD_TYPE_SECT | \
631 PMD_SECT_AP_WRITE | \
632 PMD_SECT_AP_READ
633 b __xscale_setup
634 .long cpu_arch_name
635 .long cpu_elf_name
636 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
637 .long cpu_80200_name
638 .long xscale_processor_functions
639 .long v4wbi_tlb_fns
640 .long xscale_mc_user_fns
641 .long xscale_80200_A0_A1_cache_fns
642 .size __80200_A0_A1_proc_info, . - __80200_A0_A1_proc_info
643
598 .type __80200_proc_info,#object 644 .type __80200_proc_info,#object
599__80200_proc_info: 645__80200_proc_info:
600 .long 0x69052000 646 .long 0x69052000
diff --git a/arch/arm/oprofile/op_model_xscale.c b/arch/arm/oprofile/op_model_xscale.c
index 34fdc733743b..6576143f2559 100644
--- a/arch/arm/oprofile/op_model_xscale.c
+++ b/arch/arm/oprofile/op_model_xscale.c
@@ -36,11 +36,11 @@
36#ifdef CONFIG_ARCH_IOP310 36#ifdef CONFIG_ARCH_IOP310
37#define XSCALE_PMU_IRQ IRQ_XS80200_PMU 37#define XSCALE_PMU_IRQ IRQ_XS80200_PMU
38#endif 38#endif
39#ifdef CONFIG_ARCH_IOP321 39#ifdef CONFIG_ARCH_IOP32X
40#define XSCALE_PMU_IRQ IRQ_IOP321_CORE_PMU 40#define XSCALE_PMU_IRQ IRQ_IOP32X_CORE_PMU
41#endif 41#endif
42#ifdef CONFIG_ARCH_IOP331 42#ifdef CONFIG_ARCH_IOP33X
43#define XSCALE_PMU_IRQ IRQ_IOP331_CORE_PMU 43#define XSCALE_PMU_IRQ IRQ_IOP33X_CORE_PMU
44#endif 44#endif
45#ifdef CONFIG_ARCH_PXA 45#ifdef CONFIG_ARCH_PXA
46#define XSCALE_PMU_IRQ IRQ_PMU 46#define XSCALE_PMU_IRQ IRQ_PMU
@@ -88,7 +88,7 @@ static struct pmu_counter results[MAX_COUNTERS];
88/* 88/*
89 * There are two versions of the PMU in current XScale processors 89 * There are two versions of the PMU in current XScale processors
90 * with differing register layouts and number of performance counters. 90 * with differing register layouts and number of performance counters.
91 * e.g. IOP321 is xsc1 whilst IOP331 is xsc2. 91 * e.g. IOP32x is xsc1 whilst IOP33x is xsc2.
92 * We detect which register layout to use in xscale_detect_pmu() 92 * We detect which register layout to use in xscale_detect_pmu()
93 */ 93 */
94enum { PMU_XSC1, PMU_XSC2 }; 94enum { PMU_XSC1, PMU_XSC2 };
diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile
new file mode 100644
index 000000000000..23da00b11517
--- /dev/null
+++ b/arch/arm/plat-iop/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for the linux kernel.
3#
4
5obj-y := gpio.o i2c.o pci.o setup.o time.o
6obj-m :=
7obj-n :=
8obj- :=
diff --git a/arch/arm/plat-iop/gpio.c b/arch/arm/plat-iop/gpio.c
new file mode 100644
index 000000000000..eda436083417
--- /dev/null
+++ b/arch/arm/plat-iop/gpio.c
@@ -0,0 +1,48 @@
1/*
2 * arch/arm/plat-iop/gpio.c
3 * GPIO handling for Intel IOP3xx processors.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or (at
10 * your option) any later version.
11 */
12
13#include <linux/device.h>
14#include <asm/hardware/iop3xx.h>
15
16void gpio_line_config(int line, int direction)
17{
18 unsigned long flags;
19
20 local_irq_save(flags);
21 if (direction == GPIO_IN) {
22 *IOP3XX_GPOE |= 1 << line;
23 } else if (direction == GPIO_OUT) {
24 *IOP3XX_GPOE &= ~(1 << line);
25 }
26 local_irq_restore(flags);
27}
28EXPORT_SYMBOL(gpio_line_config);
29
30int gpio_line_get(int line)
31{
32 return !!(*IOP3XX_GPID & (1 << line));
33}
34EXPORT_SYMBOL(gpio_line_get);
35
36void gpio_line_set(int line, int value)
37{
38 unsigned long flags;
39
40 local_irq_save(flags);
41 if (value == GPIO_LOW) {
42 *IOP3XX_GPOD &= ~(1 << line);
43 } else if (value == GPIO_HIGH) {
44 *IOP3XX_GPOD |= 1 << line;
45 }
46 local_irq_restore(flags);
47}
48EXPORT_SYMBOL(gpio_line_set);
diff --git a/arch/arm/plat-iop/i2c.c b/arch/arm/plat-iop/i2c.c
new file mode 100644
index 000000000000..e99909bdba71
--- /dev/null
+++ b/arch/arm/plat-iop/i2c.c
@@ -0,0 +1,81 @@
1/*
2 * arch/arm/plat-iop/i2c.c
3 *
4 * Author: Nicolas Pitre <nico@cam.org>
5 * Copyright (C) 2001 MontaVista Software, Inc.
6 * Copyright (C) 2004 Intel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/mm.h>
14#include <linux/init.h>
15#include <linux/major.h>
16#include <linux/fs.h>
17#include <linux/platform_device.h>
18#include <linux/serial.h>
19#include <linux/tty.h>
20#include <linux/serial_core.h>
21#include <asm/io.h>
22#include <asm/pgtable.h>
23#include <asm/page.h>
24#include <asm/mach/map.h>
25#include <asm/setup.h>
26#include <asm/system.h>
27#include <asm/memory.h>
28#include <asm/hardware.h>
29#include <asm/hardware/iop3xx.h>
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32
33#ifdef CONFIG_ARCH_IOP32X
34#define IRQ_IOP3XX_I2C_0 IRQ_IOP32X_I2C_0
35#define IRQ_IOP3XX_I2C_1 IRQ_IOP32X_I2C_1
36#endif
37#ifdef CONFIG_ARCH_IOP33X
38#define IRQ_IOP3XX_I2C_0 IRQ_IOP33X_I2C_0
39#define IRQ_IOP3XX_I2C_1 IRQ_IOP33X_I2C_1
40#endif
41
42static struct resource iop3xx_i2c0_resources[] = {
43 [0] = {
44 .start = 0xfffff680,
45 .end = 0xfffff697,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = IRQ_IOP3XX_I2C_0,
50 .end = IRQ_IOP3XX_I2C_0,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55struct platform_device iop3xx_i2c0_device = {
56 .name = "IOP3xx-I2C",
57 .id = 0,
58 .num_resources = 2,
59 .resource = iop3xx_i2c0_resources,
60};
61
62
63static struct resource iop3xx_i2c1_resources[] = {
64 [0] = {
65 .start = 0xfffff6a0,
66 .end = 0xfffff6b7,
67 .flags = IORESOURCE_MEM,
68 },
69 [1] = {
70 .start = IRQ_IOP3XX_I2C_1,
71 .end = IRQ_IOP3XX_I2C_1,
72 .flags = IORESOURCE_IRQ,
73 }
74};
75
76struct platform_device iop3xx_i2c1_device = {
77 .name = "IOP3xx-I2C",
78 .id = 1,
79 .num_resources = 2,
80 .resource = iop3xx_i2c1_resources,
81};
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
new file mode 100644
index 000000000000..e647812654f2
--- /dev/null
+++ b/arch/arm/plat-iop/pci.c
@@ -0,0 +1,247 @@
1/*
2 * arch/arm/plat-iop/pci.c
3 *
4 * PCI support for the Intel IOP32X and IOP33X processors
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/ioport.h>
20#include <asm/io.h>
21#include <asm/irq.h>
22#include <asm/system.h>
23#include <asm/hardware.h>
24#include <asm/mach/pci.h>
25#include <asm/hardware/iop3xx.h>
26
27// #define DEBUG
28
29#ifdef DEBUG
30#define DBG(x...) printk(x)
31#else
32#define DBG(x...) do { } while (0)
33#endif
34
35/*
36 * This routine builds either a type0 or type1 configuration command. If the
37 * bus is on the 803xx then a type0 made, else a type1 is created.
38 */
39static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where)
40{
41 struct pci_sys_data *sys = bus->sysdata;
42 u32 addr;
43
44 if (sys->busnr == bus->number)
45 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
46 else
47 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
48
49 addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
50
51 return addr;
52}
53
54/*
55 * This routine checks the status of the last configuration cycle. If an error
56 * was detected it returns a 1, else it returns a 0. The errors being checked
57 * are parity, master abort, target abort (master and target). These types of
58 * errors occure during a config cycle where there is no device, like during
59 * the discovery stage.
60 */
61static int iop3xx_pci_status(void)
62{
63 unsigned int status;
64 int ret = 0;
65
66 /*
67 * Check the status registers.
68 */
69 status = *IOP3XX_ATUSR;
70 if (status & 0xf900) {
71 DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
72 *IOP3XX_ATUSR = status & 0xf900;
73 ret = 1;
74 }
75
76 status = *IOP3XX_ATUISR;
77 if (status & 0x679f) {
78 DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
79 *IOP3XX_ATUISR = status & 0x679f;
80 ret = 1;
81 }
82
83 return ret;
84}
85
86/*
87 * Simply write the address register and read the configuration
88 * data. Note that the 4 nop's ensure that we are able to handle
89 * a delayed abort (in theory.)
90 */
91static inline u32 iop3xx_read(unsigned long addr)
92{
93 u32 val;
94
95 __asm__ __volatile__(
96 "str %1, [%2]\n\t"
97 "ldr %0, [%3]\n\t"
98 "nop\n\t"
99 "nop\n\t"
100 "nop\n\t"
101 "nop\n\t"
102 : "=r" (val)
103 : "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
104
105 return val;
106}
107
108/*
109 * The read routines must check the error status of the last configuration
110 * cycle. If there was an error, the routine returns all hex f's.
111 */
112static int
113iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where,
114 int size, u32 *value)
115{
116 unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
117 u32 val = iop3xx_read(addr) >> ((where & 3) * 8);
118
119 if (iop3xx_pci_status())
120 val = 0xffffffff;
121
122 *value = val;
123
124 return PCIBIOS_SUCCESSFUL;
125}
126
127static int
128iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where,
129 int size, u32 value)
130{
131 unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
132 u32 val;
133
134 if (size != 4) {
135 val = iop3xx_read(addr);
136 if (iop3xx_pci_status())
137 return PCIBIOS_SUCCESSFUL;
138
139 where = (where & 3) * 8;
140
141 if (size == 1)
142 val &= ~(0xff << where);
143 else
144 val &= ~(0xffff << where);
145
146 *IOP3XX_OCCDR = val | value << where;
147 } else {
148 asm volatile(
149 "str %1, [%2]\n\t"
150 "str %0, [%3]\n\t"
151 "nop\n\t"
152 "nop\n\t"
153 "nop\n\t"
154 "nop\n\t"
155 :
156 : "r" (value), "r" (addr),
157 "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
158 }
159
160 return PCIBIOS_SUCCESSFUL;
161}
162
163static struct pci_ops iop3xx_ops = {
164 .read = iop3xx_read_config,
165 .write = iop3xx_write_config,
166};
167
168/*
169 * When a PCI device does not exist during config cycles, the 80200 gets a
170 * bus error instead of returning 0xffffffff. This handler simply returns.
171 */
172static int
173iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
174{
175 DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
176 addr, fsr, regs->ARM_pc, regs->ARM_lr);
177
178 /*
179 * If it was an imprecise abort, then we need to correct the
180 * return address to be _after_ the instruction.
181 */
182 if (fsr & (1 << 10))
183 regs->ARM_pc += 4;
184
185 return 0;
186}
187
188int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
189{
190 struct resource *res;
191
192 if (nr != 0)
193 return 0;
194
195 res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL);
196 if (!res)
197 panic("PCI: unable to alloc resources");
198
199 res[0].start = IOP3XX_PCI_LOWER_IO_VA;
200 res[0].end = IOP3XX_PCI_LOWER_IO_VA + IOP3XX_PCI_IO_WINDOW_SIZE - 1;
201 res[0].name = "IOP3XX PCI I/O Space";
202 res[0].flags = IORESOURCE_IO;
203 request_resource(&ioport_resource, &res[0]);
204
205 res[1].start = IOP3XX_PCI_LOWER_MEM_PA;
206 res[1].end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
207 res[1].name = "IOP3XX PCI Memory Space";
208 res[1].flags = IORESOURCE_MEM;
209 request_resource(&iomem_resource, &res[1]);
210
211 sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA;
212 sys->io_offset = IOP3XX_PCI_LOWER_IO_VA - IOP3XX_PCI_LOWER_IO_BA;
213
214 sys->resource[0] = &res[0];
215 sys->resource[1] = &res[1];
216 sys->resource[2] = NULL;
217
218 return 1;
219}
220
221struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys)
222{
223 return pci_scan_bus(sys->busnr, &iop3xx_ops, sys);
224}
225
226void iop3xx_pci_preinit(void)
227{
228 DBG("PCI: Intel 803xx PCI init code.\n");
229 DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
230 DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n",
231 *IOP3XX_OMWTVR0,
232 *IOP3XX_OIOWTVR);
233 DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
234 DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n",
235 *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
236 DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0);
237 DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n",
238 *IOP3XX_IABAR1, *IOP3XX_IALR1);
239 DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n",
240 *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
241 DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n",
242 *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
243 DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n",
244 *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
245
246 hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");
247}
diff --git a/arch/arm/plat-iop/setup.c b/arch/arm/plat-iop/setup.c
new file mode 100644
index 000000000000..4689db638e95
--- /dev/null
+++ b/arch/arm/plat-iop/setup.c
@@ -0,0 +1,38 @@
1/*
2 * arch/arm/plat-iop/setup.c
3 *
4 * Author: Nicolas Pitre <nico@cam.org>
5 * Copyright (C) 2001 MontaVista Software, Inc.
6 * Copyright (C) 2004 Intel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/mm.h>
14#include <linux/init.h>
15#include <asm/mach/map.h>
16#include <asm/hardware/iop3xx.h>
17
18/*
19 * Standard IO mapping for all IOP3xx based systems
20 */
21static struct map_desc iop3xx_std_desc[] __initdata = {
22 { /* mem mapped registers */
23 .virtual = IOP3XX_PERIPHERAL_VIRT_BASE,
24 .pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE),
25 .length = IOP3XX_PERIPHERAL_SIZE,
26 .type = MT_DEVICE,
27 }, { /* PCI IO space */
28 .virtual = IOP3XX_PCI_LOWER_IO_VA,
29 .pfn = __phys_to_pfn(IOP3XX_PCI_LOWER_IO_PA),
30 .length = IOP3XX_PCI_IO_WINDOW_SIZE,
31 .type = MT_DEVICE,
32 },
33};
34
35void __init iop3xx_map_io(void)
36{
37 iotable_init(iop3xx_std_desc, ARRAY_SIZE(iop3xx_std_desc));
38}
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
new file mode 100644
index 000000000000..06282dffbdc6
--- /dev/null
+++ b/arch/arm/plat-iop/time.c
@@ -0,0 +1,98 @@
1/*
2 * arch/arm/plat-iop/time.c
3 *
4 * Timer code for IOP32x and IOP33x based systems
5 *
6 * Author: Deepak Saxena <dsaxena@mvista.com>
7 *
8 * Copyright 2002-2003 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/time.h>
19#include <linux/init.h>
20#include <linux/timex.h>
21#include <asm/hardware.h>
22#include <asm/io.h>
23#include <asm/irq.h>
24#include <asm/uaccess.h>
25#include <asm/mach/irq.h>
26#include <asm/mach/time.h>
27
28#ifdef CONFIG_ARCH_IOP32X
29#define IRQ_IOP3XX_TIMER0 IRQ_IOP32X_TIMER0
30#else
31#ifdef CONFIG_ARCH_IOP33X
32#define IRQ_IOP3XX_TIMER0 IRQ_IOP33X_TIMER0
33#endif
34#endif
35
36static unsigned long ticks_per_jiffy;
37static unsigned long ticks_per_usec;
38static unsigned long next_jiffy_time;
39
40unsigned long iop3xx_gettimeoffset(void)
41{
42 unsigned long offset;
43
44 offset = next_jiffy_time - *IOP3XX_TU_TCR1;
45
46 return offset / ticks_per_usec;
47}
48
49static irqreturn_t
50iop3xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
51{
52 write_seqlock(&xtime_lock);
53
54 iop3xx_cp6_enable();
55 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1));
56 iop3xx_cp6_disable();
57
58 while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1)
59 >= ticks_per_jiffy) {
60 timer_tick(regs);
61 next_jiffy_time -= ticks_per_jiffy;
62 }
63
64 write_sequnlock(&xtime_lock);
65
66 return IRQ_HANDLED;
67}
68
69static struct irqaction iop3xx_timer_irq = {
70 .name = "IOP3XX Timer Tick",
71 .handler = iop3xx_timer_interrupt,
72 .flags = IRQF_DISABLED | IRQF_TIMER,
73};
74
75void __init iop3xx_init_time(unsigned long tick_rate)
76{
77 u32 timer_ctl;
78
79 ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
80 ticks_per_usec = tick_rate / 1000000;
81 next_jiffy_time = 0xffffffff;
82
83 timer_ctl = IOP3XX_TMR_EN | IOP3XX_TMR_PRIVILEGED |
84 IOP3XX_TMR_RELOAD | IOP3XX_TMR_RATIO_1_1;
85
86 /*
87 * We use timer 0 for our timer interrupt, and timer 1 as
88 * monotonic counter for tracking missed jiffies.
89 */
90 iop3xx_cp6_enable();
91 asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1));
92 asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl));
93 asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff));
94 asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl));
95 iop3xx_cp6_disable();
96
97 setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq);
98}
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 7f45c7c3e673..f1179ad4be1b 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -100,6 +100,7 @@ void clk_disable(struct clk *clk)
100 return; 100 return;
101 101
102 spin_lock_irqsave(&clockfw_lock, flags); 102 spin_lock_irqsave(&clockfw_lock, flags);
103 BUG_ON(clk->usecount == 0);
103 if (arch_clock->clk_disable) 104 if (arch_clock->clk_disable)
104 arch_clock->clk_disable(clk); 105 arch_clock->clk_disable(clk);
105 spin_unlock_irqrestore(&clockfw_lock, flags); 106 spin_unlock_irqrestore(&clockfw_lock, flags);
@@ -322,6 +323,31 @@ EXPORT_SYMBOL(clk_allow_idle);
322 323
323/*-------------------------------------------------------------------------*/ 324/*-------------------------------------------------------------------------*/
324 325
326#ifdef CONFIG_OMAP_RESET_CLOCKS
327/*
328 * Disable any unused clocks left on by the bootloader
329 */
330static int __init clk_disable_unused(void)
331{
332 struct clk *ck;
333 unsigned long flags;
334
335 list_for_each_entry(ck, &clocks, node) {
336 if (ck->usecount > 0 || (ck->flags & ALWAYS_ENABLED) ||
337 ck->enable_reg == 0)
338 continue;
339
340 spin_lock_irqsave(&clockfw_lock, flags);
341 if (arch_clock->clk_disable_unused)
342 arch_clock->clk_disable_unused(ck);
343 spin_unlock_irqrestore(&clockfw_lock, flags);
344 }
345
346 return 0;
347}
348late_initcall(clk_disable_unused);
349#endif
350
325int __init clk_init(struct clk_functions * custom_clocks) 351int __init clk_init(struct clk_functions * custom_clocks)
326{ 352{
327 if (!custom_clocks) { 353 if (!custom_clocks) {
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 1812f237d12f..dbc3f44e07a6 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -148,7 +148,7 @@ static inline void omap_init_kp(void) {}
148 148
149#ifdef CONFIG_ARCH_OMAP24XX 149#ifdef CONFIG_ARCH_OMAP24XX
150#define OMAP_MMC1_BASE 0x4809c000 150#define OMAP_MMC1_BASE 0x4809c000
151#define OMAP_MMC1_INT 83 151#define OMAP_MMC1_INT INT_24XX_MMC_IRQ
152#else 152#else
153#define OMAP_MMC1_BASE 0xfffb7800 153#define OMAP_MMC1_BASE 0xfffb7800
154#define OMAP_MMC1_INT INT_MMC 154#define OMAP_MMC1_INT INT_MMC
@@ -225,7 +225,14 @@ static void __init omap_init_mmc(void)
225 /* block 1 is always available and has just one pinout option */ 225 /* block 1 is always available and has just one pinout option */
226 mmc = &mmc_conf->mmc[0]; 226 mmc = &mmc_conf->mmc[0];
227 if (mmc->enabled) { 227 if (mmc->enabled) {
228 if (!cpu_is_omap24xx()) { 228 if (cpu_is_omap24xx()) {
229 omap_cfg_reg(H18_24XX_MMC_CMD);
230 omap_cfg_reg(H15_24XX_MMC_CLKI);
231 omap_cfg_reg(G19_24XX_MMC_CLKO);
232 omap_cfg_reg(F20_24XX_MMC_DAT0);
233 omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
234 omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
235 } else {
229 omap_cfg_reg(MMC_CMD); 236 omap_cfg_reg(MMC_CMD);
230 omap_cfg_reg(MMC_CLK); 237 omap_cfg_reg(MMC_CLK);
231 omap_cfg_reg(MMC_DAT0); 238 omap_cfg_reg(MMC_DAT0);
@@ -236,7 +243,14 @@ static void __init omap_init_mmc(void)
236 } 243 }
237 } 244 }
238 if (mmc->wire4) { 245 if (mmc->wire4) {
239 if (!cpu_is_omap24xx()) { 246 if (cpu_is_omap24xx()) {
247 omap_cfg_reg(H14_24XX_MMC_DAT1);
248 omap_cfg_reg(E19_24XX_MMC_DAT2);
249 omap_cfg_reg(D19_24XX_MMC_DAT3);
250 omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
251 omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
252 omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
253 } else {
240 omap_cfg_reg(MMC_DAT1); 254 omap_cfg_reg(MMC_DAT1);
241 /* NOTE: DAT2 can be on W10 (here) or M15 */ 255 /* NOTE: DAT2 can be on W10 (here) or M15 */
242 if (!mmc->nomux) 256 if (!mmc->nomux)
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 9eddc9507147..1bbb431843ce 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -119,32 +119,41 @@ static void clear_lch_regs(int lch)
119 omap_writew(0, lch_base + i); 119 omap_writew(0, lch_base + i);
120} 120}
121 121
122void omap_set_dma_priority(int dst_port, int priority) 122void omap_set_dma_priority(int lch, int dst_port, int priority)
123{ 123{
124 unsigned long reg; 124 unsigned long reg;
125 u32 l; 125 u32 l;
126 126
127 switch (dst_port) { 127 if (cpu_class_is_omap1()) {
128 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ 128 switch (dst_port) {
129 reg = OMAP_TC_OCPT1_PRIOR; 129 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
130 break; 130 reg = OMAP_TC_OCPT1_PRIOR;
131 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */ 131 break;
132 reg = OMAP_TC_OCPT2_PRIOR; 132 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
133 break; 133 reg = OMAP_TC_OCPT2_PRIOR;
134 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */ 134 break;
135 reg = OMAP_TC_EMIFF_PRIOR; 135 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
136 break; 136 reg = OMAP_TC_EMIFF_PRIOR;
137 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */ 137 break;
138 reg = OMAP_TC_EMIFS_PRIOR; 138 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
139 break; 139 reg = OMAP_TC_EMIFS_PRIOR;
140 default: 140 break;
141 BUG(); 141 default:
142 return; 142 BUG();
143 return;
144 }
145 l = omap_readl(reg);
146 l &= ~(0xf << 8);
147 l |= (priority & 0xf) << 8;
148 omap_writel(l, reg);
149 }
150
151 if (cpu_is_omap24xx()) {
152 if (priority)
153 OMAP_DMA_CCR_REG(lch) |= (1 << 6);
154 else
155 OMAP_DMA_CCR_REG(lch) &= ~(1 << 6);
143 } 156 }
144 l = omap_readl(reg);
145 l &= ~(0xf << 8);
146 l |= (priority & 0xf) << 8;
147 omap_writel(l, reg);
148} 157}
149 158
150void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, 159void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
@@ -234,6 +243,14 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
234 OMAP1_DMA_LCH_CTRL_REG(lch) = w; 243 OMAP1_DMA_LCH_CTRL_REG(lch) = w;
235} 244}
236 245
246void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
247{
248 if (cpu_is_omap24xx()) {
249 OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16);
250 OMAP_DMA_CSDP_REG(lch) |= (mode << 16);
251 }
252}
253
237/* Note that src_port is only for omap1 */ 254/* Note that src_port is only for omap1 */
238void omap_set_dma_src_params(int lch, int src_port, int src_amode, 255void omap_set_dma_src_params(int lch, int src_port, int src_amode,
239 unsigned long src_start, 256 unsigned long src_start,
@@ -698,6 +715,32 @@ void omap_stop_dma(int lch)
698} 715}
699 716
700/* 717/*
718 * Allows changing the DMA callback function or data. This may be needed if
719 * the driver shares a single DMA channel for multiple dma triggers.
720 */
721int omap_set_dma_callback(int lch,
722 void (* callback)(int lch, u16 ch_status, void *data),
723 void *data)
724{
725 unsigned long flags;
726
727 if (lch < 0)
728 return -ENODEV;
729
730 spin_lock_irqsave(&dma_chan_lock, flags);
731 if (dma_chan[lch].dev_id == -1) {
732 printk(KERN_ERR "DMA callback for not set for free channel\n");
733 spin_unlock_irqrestore(&dma_chan_lock, flags);
734 return -EINVAL;
735 }
736 dma_chan[lch].callback = callback;
737 dma_chan[lch].data = data;
738 spin_unlock_irqrestore(&dma_chan_lock, flags);
739
740 return 0;
741}
742
743/*
701 * Returns current physical source address for the given DMA channel. 744 * Returns current physical source address for the given DMA channel.
702 * If the channel is running the caller must disable interrupts prior calling 745 * If the channel is running the caller must disable interrupts prior calling
703 * this function and process the returned value before re-enabling interrupt to 746 * this function and process the returned value before re-enabling interrupt to
@@ -1339,6 +1382,14 @@ static int __init omap_init_dma(void)
1339 dma_chan_count = 16; 1382 dma_chan_count = 16;
1340 } else 1383 } else
1341 dma_chan_count = 9; 1384 dma_chan_count = 9;
1385 if (cpu_is_omap16xx()) {
1386 u16 w;
1387
1388 /* this would prevent OMAP sleep */
1389 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1390 w &= ~(1 << 8);
1391 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1392 }
1342 } else if (cpu_is_omap24xx()) { 1393 } else if (cpu_is_omap24xx()) {
1343 u8 revision = omap_readb(OMAP_DMA4_REVISION); 1394 u8 revision = omap_readb(OMAP_DMA4_REVISION);
1344 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", 1395 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
@@ -1414,11 +1465,13 @@ EXPORT_SYMBOL(omap_request_dma);
1414EXPORT_SYMBOL(omap_free_dma); 1465EXPORT_SYMBOL(omap_free_dma);
1415EXPORT_SYMBOL(omap_start_dma); 1466EXPORT_SYMBOL(omap_start_dma);
1416EXPORT_SYMBOL(omap_stop_dma); 1467EXPORT_SYMBOL(omap_stop_dma);
1468EXPORT_SYMBOL(omap_set_dma_callback);
1417EXPORT_SYMBOL(omap_enable_dma_irq); 1469EXPORT_SYMBOL(omap_enable_dma_irq);
1418EXPORT_SYMBOL(omap_disable_dma_irq); 1470EXPORT_SYMBOL(omap_disable_dma_irq);
1419 1471
1420EXPORT_SYMBOL(omap_set_dma_transfer_params); 1472EXPORT_SYMBOL(omap_set_dma_transfer_params);
1421EXPORT_SYMBOL(omap_set_dma_color_mode); 1473EXPORT_SYMBOL(omap_set_dma_color_mode);
1474EXPORT_SYMBOL(omap_set_dma_write_mode);
1422 1475
1423EXPORT_SYMBOL(omap_set_dma_src_params); 1476EXPORT_SYMBOL(omap_set_dma_src_params);
1424EXPORT_SYMBOL(omap_set_dma_src_index); 1477EXPORT_SYMBOL(omap_set_dma_src_index);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 50524436de63..bcbb8d7392be 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -75,10 +75,14 @@ struct omap_dm_timer {
75#endif 75#endif
76 void __iomem *io_base; 76 void __iomem *io_base;
77 unsigned reserved:1; 77 unsigned reserved:1;
78 unsigned enabled:1;
78}; 79};
79 80
80#ifdef CONFIG_ARCH_OMAP1 81#ifdef CONFIG_ARCH_OMAP1
81 82
83#define omap_dm_clk_enable(x)
84#define omap_dm_clk_disable(x)
85
82static struct omap_dm_timer dm_timers[] = { 86static struct omap_dm_timer dm_timers[] = {
83 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, 87 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
84 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 }, 88 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
@@ -92,6 +96,9 @@ static struct omap_dm_timer dm_timers[] = {
92 96
93#elif defined(CONFIG_ARCH_OMAP2) 97#elif defined(CONFIG_ARCH_OMAP2)
94 98
99#define omap_dm_clk_enable(x) clk_enable(x)
100#define omap_dm_clk_disable(x) clk_disable(x)
101
95static struct omap_dm_timer dm_timers[] = { 102static struct omap_dm_timer dm_timers[] = {
96 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, 103 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
97 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 }, 104 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
@@ -154,24 +161,28 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
154{ 161{
155 u32 l; 162 u32 l;
156 163
157 if (timer != &dm_timers[0]) { 164 if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
158 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); 165 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
159 omap_dm_timer_wait_for_reset(timer); 166 omap_dm_timer_wait_for_reset(timer);
160 } 167 }
161 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_SYS_CLK); 168 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
162 169
163 /* Set to smart-idle mode */ 170 /* Set to smart-idle mode */
164 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG); 171 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
165 l |= 0x02 << 3; 172 l |= 0x02 << 3;
173
174 if (cpu_class_is_omap2() && timer == &dm_timers[0]) {
175 /* Enable wake-up only for GPT1 on OMAP2 CPUs*/
176 l |= 1 << 2;
177 /* Non-posted mode */
178 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0);
179 }
166 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l); 180 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
167} 181}
168 182
169static void omap_dm_timer_prepare(struct omap_dm_timer *timer) 183static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
170{ 184{
171#ifdef CONFIG_ARCH_OMAP2 185 omap_dm_timer_enable(timer);
172 clk_enable(timer->iclk);
173 clk_enable(timer->fclk);
174#endif
175 omap_dm_timer_reset(timer); 186 omap_dm_timer_reset(timer);
176} 187}
177 188
@@ -223,15 +234,36 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
223 234
224void omap_dm_timer_free(struct omap_dm_timer *timer) 235void omap_dm_timer_free(struct omap_dm_timer *timer)
225{ 236{
237 omap_dm_timer_enable(timer);
226 omap_dm_timer_reset(timer); 238 omap_dm_timer_reset(timer);
227#ifdef CONFIG_ARCH_OMAP2 239 omap_dm_timer_disable(timer);
228 clk_disable(timer->iclk); 240
229 clk_disable(timer->fclk);
230#endif
231 WARN_ON(!timer->reserved); 241 WARN_ON(!timer->reserved);
232 timer->reserved = 0; 242 timer->reserved = 0;
233} 243}
234 244
245void omap_dm_timer_enable(struct omap_dm_timer *timer)
246{
247 if (timer->enabled)
248 return;
249
250 omap_dm_clk_enable(timer->fclk);
251 omap_dm_clk_enable(timer->iclk);
252
253 timer->enabled = 1;
254}
255
256void omap_dm_timer_disable(struct omap_dm_timer *timer)
257{
258 if (!timer->enabled)
259 return;
260
261 omap_dm_clk_disable(timer->iclk);
262 omap_dm_clk_disable(timer->fclk);
263
264 timer->enabled = 0;
265}
266
235int omap_dm_timer_get_irq(struct omap_dm_timer *timer) 267int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
236{ 268{
237 return timer->irq; 269 return timer->irq;
@@ -276,7 +308,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
276 308
277struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) 309struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
278{ 310{
279 return timer->fclk; 311 return timer->fclk;
280} 312}
281 313
282__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) 314__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
@@ -406,11 +438,16 @@ void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
406 unsigned int value) 438 unsigned int value)
407{ 439{
408 omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value); 440 omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
441 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
409} 442}
410 443
411unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) 444unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
412{ 445{
413 return omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG); 446 unsigned int l;
447
448 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
449
450 return l;
414} 451}
415 452
416void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) 453void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
@@ -420,12 +457,16 @@ void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
420 457
421unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) 458unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
422{ 459{
423 return omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG); 460 unsigned int l;
461
462 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
463
464 return l;
424} 465}
425 466
426void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) 467void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
427{ 468{
428 return omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); 469 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
429} 470}
430 471
431int omap_dm_timers_active(void) 472int omap_dm_timers_active(void)
@@ -436,9 +477,14 @@ int omap_dm_timers_active(void)
436 struct omap_dm_timer *timer; 477 struct omap_dm_timer *timer;
437 478
438 timer = &dm_timers[i]; 479 timer = &dm_timers[i];
480
481 if (!timer->enabled)
482 continue;
483
439 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & 484 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
440 OMAP_TIMER_CTRL_ST) 485 OMAP_TIMER_CTRL_ST) {
441 return 1; 486 return 1;
487 }
442 } 488 }
443 return 0; 489 return 0;
444} 490}
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index cd7f973fb286..f55f99ae58ae 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -94,6 +94,8 @@
94#define OMAP24XX_GPIO_SYSCONFIG 0x0010 94#define OMAP24XX_GPIO_SYSCONFIG 0x0010
95#define OMAP24XX_GPIO_SYSSTATUS 0x0014 95#define OMAP24XX_GPIO_SYSSTATUS 0x0014
96#define OMAP24XX_GPIO_IRQSTATUS1 0x0018 96#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
97#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
98#define OMAP24XX_GPIO_IRQENABLE2 0x002c
97#define OMAP24XX_GPIO_IRQENABLE1 0x001c 99#define OMAP24XX_GPIO_IRQENABLE1 0x001c
98#define OMAP24XX_GPIO_CTRL 0x0030 100#define OMAP24XX_GPIO_CTRL 0x0030
99#define OMAP24XX_GPIO_OE 0x0034 101#define OMAP24XX_GPIO_OE 0x0034
@@ -110,8 +112,6 @@
110#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 112#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
111#define OMAP24XX_GPIO_SETDATAOUT 0x0094 113#define OMAP24XX_GPIO_SETDATAOUT 0x0094
112 114
113#define OMAP_MPUIO_MASK (~OMAP_MAX_GPIO_LINES & 0xff)
114
115struct gpio_bank { 115struct gpio_bank {
116 void __iomem *base; 116 void __iomem *base;
117 u16 irq; 117 u16 irq;
@@ -216,11 +216,13 @@ static inline int gpio_valid(int gpio)
216{ 216{
217 if (gpio < 0) 217 if (gpio < 0)
218 return -1; 218 return -1;
219#ifndef CONFIG_ARCH_OMAP24XX
219 if (OMAP_GPIO_IS_MPUIO(gpio)) { 220 if (OMAP_GPIO_IS_MPUIO(gpio)) {
220 if ((gpio & OMAP_MPUIO_MASK) > 16) 221 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
221 return -1; 222 return -1;
222 return 0; 223 return 0;
223 } 224 }
225#endif
224#ifdef CONFIG_ARCH_OMAP15XX 226#ifdef CONFIG_ARCH_OMAP15XX
225 if (cpu_is_omap15xx() && gpio < 16) 227 if (cpu_is_omap15xx() && gpio < 16)
226 return 0; 228 return 0;
@@ -529,6 +531,10 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
529 return; 531 return;
530 } 532 }
531 __raw_writel(gpio_mask, reg); 533 __raw_writel(gpio_mask, reg);
534
535 /* Workaround for clearing DSP GPIO interrupts to allow retention */
536 if (cpu_is_omap2420())
537 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
532} 538}
533 539
534static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) 540static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
@@ -662,6 +668,14 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
662 } 668 }
663} 669}
664 670
671static void _reset_gpio(struct gpio_bank *bank, int gpio)
672{
673 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
674 _set_gpio_irqenable(bank, gpio, 0);
675 _clear_gpio_irqstatus(bank, gpio);
676 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
677}
678
665/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ 679/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
666static int gpio_wake_enable(unsigned int irq, unsigned int enable) 680static int gpio_wake_enable(unsigned int irq, unsigned int enable)
667{ 681{
@@ -672,9 +686,7 @@ static int gpio_wake_enable(unsigned int irq, unsigned int enable)
672 if (check_gpio(gpio) < 0) 686 if (check_gpio(gpio) < 0)
673 return -ENODEV; 687 return -ENODEV;
674 bank = get_gpio_bank(gpio); 688 bank = get_gpio_bank(gpio);
675 spin_lock(&bank->lock);
676 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); 689 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
677 spin_unlock(&bank->lock);
678 690
679 return retval; 691 return retval;
680} 692}
@@ -696,7 +708,9 @@ int omap_request_gpio(int gpio)
696 } 708 }
697 bank->reserved_map |= (1 << get_gpio_index(gpio)); 709 bank->reserved_map |= (1 << get_gpio_index(gpio));
698 710
699 /* Set trigger to none. You need to enable the trigger after request_irq */ 711 /* Set trigger to none. You need to enable the desired trigger with
712 * request_irq() or set_irq_type().
713 */
700 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE); 714 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
701 715
702#ifdef CONFIG_ARCH_OMAP15XX 716#ifdef CONFIG_ARCH_OMAP15XX
@@ -756,9 +770,7 @@ void omap_free_gpio(int gpio)
756 } 770 }
757#endif 771#endif
758 bank->reserved_map &= ~(1 << get_gpio_index(gpio)); 772 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
759 _set_gpio_direction(bank, get_gpio_index(gpio), 1); 773 _reset_gpio(bank, gpio);
760 _set_gpio_irqenable(bank, gpio, 0);
761 _clear_gpio_irqstatus(bank, gpio);
762 spin_unlock(&bank->lock); 774 spin_unlock(&bank->lock);
763} 775}
764 776
@@ -898,6 +910,14 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
898 910
899} 911}
900 912
913static void gpio_irq_shutdown(unsigned int irq)
914{
915 unsigned int gpio = irq - IH_GPIO_BASE;
916 struct gpio_bank *bank = get_gpio_bank(gpio);
917
918 _reset_gpio(bank, gpio);
919}
920
901static void gpio_ack_irq(unsigned int irq) 921static void gpio_ack_irq(unsigned int irq)
902{ 922{
903 unsigned int gpio = irq - IH_GPIO_BASE; 923 unsigned int gpio = irq - IH_GPIO_BASE;
@@ -946,6 +966,7 @@ static void mpuio_unmask_irq(unsigned int irq)
946 966
947static struct irq_chip gpio_irq_chip = { 967static struct irq_chip gpio_irq_chip = {
948 .name = "GPIO", 968 .name = "GPIO",
969 .shutdown = gpio_irq_shutdown,
949 .ack = gpio_ack_irq, 970 .ack = gpio_ack_irq,
950 .mask = gpio_mask_irq, 971 .mask = gpio_mask_irq,
951 .unmask = gpio_unmask_irq, 972 .unmask = gpio_unmask_irq,
@@ -985,7 +1006,7 @@ static int __init _omap_gpio_init(void)
985 else 1006 else
986 clk_enable(gpio_ick); 1007 clk_enable(gpio_ick);
987 gpio_fck = clk_get(NULL, "gpios_fck"); 1008 gpio_fck = clk_get(NULL, "gpios_fck");
988 if (IS_ERR(gpio_ick)) 1009 if (IS_ERR(gpio_fck))
989 printk("Could not get gpios_fck\n"); 1010 printk("Could not get gpios_fck\n");
990 else 1011 else
991 clk_enable(gpio_fck); 1012 clk_enable(gpio_fck);
@@ -1144,8 +1165,8 @@ static int omap_gpio_resume(struct sys_device *dev)
1144 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1165 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1145 break; 1166 break;
1146 case METHOD_GPIO_24XX: 1167 case METHOD_GPIO_24XX:
1147 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; 1168 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1148 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1169 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1149 break; 1170 break;
1150 default: 1171 default:
1151 continue; 1172 continue;
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 196aac3ac329..ade9a0fa6ef6 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -75,8 +75,6 @@ static struct clk *mcbsp1_ick = 0;
75static struct clk *mcbsp1_fck = 0; 75static struct clk *mcbsp1_fck = 0;
76static struct clk *mcbsp2_ick = 0; 76static struct clk *mcbsp2_ick = 0;
77static struct clk *mcbsp2_fck = 0; 77static struct clk *mcbsp2_fck = 0;
78static struct clk *sys_ck = 0;
79static struct clk *sys_clkout = 0;
80#endif 78#endif
81 79
82static void omap_mcbsp_dump_reg(u8 id) 80static void omap_mcbsp_dump_reg(u8 id)
@@ -232,7 +230,6 @@ static void omap2_mcbsp2_mux_setup(void)
232 omap_cfg_reg(W15_24XX_MCBSP2_DR); 230 omap_cfg_reg(W15_24XX_MCBSP2_DR);
233 omap_cfg_reg(V15_24XX_MCBSP2_DX); 231 omap_cfg_reg(V15_24XX_MCBSP2_DX);
234 omap_cfg_reg(V14_24XX_GPIO117); 232 omap_cfg_reg(V14_24XX_GPIO117);
235 omap_cfg_reg(W14_24XX_SYS_CLKOUT);
236} 233}
237#endif 234#endif
238 235
@@ -984,13 +981,7 @@ static int __init omap_mcbsp_init(void)
984 if (cpu_is_omap24xx()) { 981 if (cpu_is_omap24xx()) {
985 mcbsp_info = mcbsp_24xx; 982 mcbsp_info = mcbsp_24xx;
986 mcbsp_count = ARRAY_SIZE(mcbsp_24xx); 983 mcbsp_count = ARRAY_SIZE(mcbsp_24xx);
987
988 /* REVISIT: where's the right place? */
989 omap2_mcbsp2_mux_setup(); 984 omap2_mcbsp2_mux_setup();
990 sys_ck = clk_get(0, "sys_ck");
991 sys_clkout = clk_get(0, "sys_clkout");
992 clk_set_parent(sys_clkout, sys_ck);
993 clk_enable(sys_clkout);
994 } 985 }
995#endif 986#endif
996 for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) { 987 for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
diff --git a/arch/arm/plat-omap/pm.c b/arch/arm/plat-omap/pm.c
deleted file mode 100644
index 04b4102727a8..000000000000
--- a/arch/arm/plat-omap/pm.c
+++ /dev/null
@@ -1,670 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/pm.c
3 *
4 * OMAP Power Management Routines
5 *
6 * Original code for the SA11x0:
7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
8 *
9 * Modified for the PXA250 by Nicolas Pitre:
10 * Copyright (c) 2002 Monta Vista Software, Inc.
11 *
12 * Modified for the OMAP1510 by David Singleton:
13 * Copyright (c) 2002 Monta Vista Software, Inc.
14 *
15 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
21 *
22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 */
37
38#include <linux/pm.h>
39#include <linux/sched.h>
40#include <linux/proc_fs.h>
41#include <linux/pm.h>
42#include <linux/interrupt.h>
43
44#include <asm/io.h>
45#include <asm/irq.h>
46#include <asm/mach/time.h>
47#include <asm/mach/irq.h>
48
49#include <asm/mach-types.h>
50#include <asm/arch/irqs.h>
51#include <asm/arch/tc.h>
52#include <asm/arch/pm.h>
53#include <asm/arch/mux.h>
54#include <asm/arch/tps65010.h>
55#include <asm/arch/dsp_common.h>
56
57#include <asm/arch/clock.h>
58#include <asm/arch/sram.h>
59
60static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
61static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
62static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
63static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
64static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
65
66static void (*omap_sram_idle)(void) = NULL;
67static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
68
69/*
70 * Let's power down on idle, but only if we are really
71 * idle, because once we start down the path of
72 * going idle we continue to do idle even if we get
73 * a clock tick interrupt . .
74 */
75void omap_pm_idle(void)
76{
77 unsigned int mask32 = 0;
78
79 /*
80 * If the DSP is being used let's just idle the CPU, the overhead
81 * to wake up from Big Sleep is big, milliseconds versus micro
82 * seconds for wait for interrupt.
83 */
84
85 local_irq_disable();
86 local_fiq_disable();
87 if (need_resched()) {
88 local_fiq_enable();
89 local_irq_enable();
90 return;
91 }
92 mask32 = omap_readl(ARM_SYSST);
93
94 /*
95 * Prevent the ULPD from entering low power state by setting
96 * POWER_CTRL_REG:4 = 0
97 */
98 omap_writew(omap_readw(ULPD_POWER_CTRL) &
99 ~ULPD_DEEP_SLEEP_TRANSITION_EN, ULPD_POWER_CTRL);
100
101 /*
102 * Since an interrupt may set up a timer, we don't want to
103 * reprogram the hardware timer with interrupts enabled.
104 * Re-enable interrupts only after returning from idle.
105 */
106 timer_dyn_reprogram();
107
108 if ((mask32 & DSP_IDLE) == 0) {
109 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
110 } else
111 omap_sram_idle();
112
113 local_fiq_enable();
114 local_irq_enable();
115}
116
117/*
118 * Configuration of the wakeup event is board specific. For the
119 * moment we put it into this helper function. Later it may move
120 * to board specific files.
121 */
122static void omap_pm_wakeup_setup(void)
123{
124 u32 level1_wake = 0;
125 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
126
127 /*
128 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
129 * and the L2 wakeup interrupts: keypad and UART2. Note that the
130 * drivers must still separately call omap_set_gpio_wakeup() to
131 * wake up to a GPIO interrupt.
132 */
133 if (cpu_is_omap730())
134 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
135 OMAP_IRQ_BIT(INT_730_IH2_IRQ);
136 else if (cpu_is_omap1510())
137 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
138 OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
139 else if (cpu_is_omap16xx())
140 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
141 OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
142
143 omap_writel(~level1_wake, OMAP_IH1_MIR);
144
145 if (cpu_is_omap730()) {
146 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
147 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) | OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)), OMAP_IH2_1_MIR);
148 } else if (cpu_is_omap1510()) {
149 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
150 omap_writel(~level2_wake, OMAP_IH2_MIR);
151 } else if (cpu_is_omap16xx()) {
152 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
153 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
154
155 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
156 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), OMAP_IH2_1_MIR);
157 omap_writel(~0x0, OMAP_IH2_2_MIR);
158 omap_writel(~0x0, OMAP_IH2_3_MIR);
159 }
160
161 /* New IRQ agreement, recalculate in cascade order */
162 omap_writel(1, OMAP_IH2_CONTROL);
163 omap_writel(1, OMAP_IH1_CONTROL);
164}
165
166void omap_pm_suspend(void)
167{
168 unsigned long arg0 = 0, arg1 = 0;
169
170 printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
171
172 omap_serial_wake_trigger(1);
173
174 if (machine_is_omap_osk()) {
175 /* Stop LED1 (D9) blink */
176 tps65010_set_led(LED1, OFF);
177 }
178
179 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
180
181 /*
182 * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
183 */
184
185 local_irq_disable();
186 local_fiq_disable();
187
188 /*
189 * Step 2: save registers
190 *
191 * The omap is a strange/beautiful device. The caches, memory
192 * and register state are preserved across power saves.
193 * We have to save and restore very little register state to
194 * idle the omap.
195 *
196 * Save interrupt, MPUI, ARM and UPLD control registers.
197 */
198
199 if (cpu_is_omap730()) {
200 MPUI730_SAVE(OMAP_IH1_MIR);
201 MPUI730_SAVE(OMAP_IH2_0_MIR);
202 MPUI730_SAVE(OMAP_IH2_1_MIR);
203 MPUI730_SAVE(MPUI_CTRL);
204 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
205 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
206 MPUI730_SAVE(EMIFS_CONFIG);
207 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
208
209 } else if (cpu_is_omap1510()) {
210 MPUI1510_SAVE(OMAP_IH1_MIR);
211 MPUI1510_SAVE(OMAP_IH2_MIR);
212 MPUI1510_SAVE(MPUI_CTRL);
213 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
214 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
215 MPUI1510_SAVE(EMIFS_CONFIG);
216 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
217 } else if (cpu_is_omap16xx()) {
218 MPUI1610_SAVE(OMAP_IH1_MIR);
219 MPUI1610_SAVE(OMAP_IH2_0_MIR);
220 MPUI1610_SAVE(OMAP_IH2_1_MIR);
221 MPUI1610_SAVE(OMAP_IH2_2_MIR);
222 MPUI1610_SAVE(OMAP_IH2_3_MIR);
223 MPUI1610_SAVE(MPUI_CTRL);
224 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
225 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
226 MPUI1610_SAVE(EMIFS_CONFIG);
227 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
228 }
229
230 ARM_SAVE(ARM_CKCTL);
231 ARM_SAVE(ARM_IDLECT1);
232 ARM_SAVE(ARM_IDLECT2);
233 if (!(cpu_is_omap1510()))
234 ARM_SAVE(ARM_IDLECT3);
235 ARM_SAVE(ARM_EWUPCT);
236 ARM_SAVE(ARM_RSTCT1);
237 ARM_SAVE(ARM_RSTCT2);
238 ARM_SAVE(ARM_SYSST);
239 ULPD_SAVE(ULPD_CLOCK_CTRL);
240 ULPD_SAVE(ULPD_STATUS_REQ);
241
242 /* (Step 3 removed - we now allow deep sleep by default) */
243
244 /*
245 * Step 4: OMAP DSP Shutdown
246 */
247
248
249 /*
250 * Step 5: Wakeup Event Setup
251 */
252
253 omap_pm_wakeup_setup();
254
255 /*
256 * Step 6: ARM and Traffic controller shutdown
257 */
258
259 /* disable ARM watchdog */
260 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
261 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
262
263 /*
264 * Step 6b: ARM and Traffic controller shutdown
265 *
266 * Step 6 continues here. Prepare jump to power management
267 * assembly code in internal SRAM.
268 *
269 * Since the omap_cpu_suspend routine has been copied to
270 * SRAM, we'll do an indirect procedure call to it and pass the
271 * contents of arm_idlect1 and arm_idlect2 so it can restore
272 * them when it wakes up and it will return.
273 */
274
275 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
276 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
277
278 /*
279 * Step 6c: ARM and Traffic controller shutdown
280 *
281 * Jump to assembly code. The processor will stay there
282 * until wake up.
283 */
284 omap_sram_suspend(arg0, arg1);
285
286 /*
287 * If we are here, processor is woken up!
288 */
289
290 /*
291 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
292 */
293
294 if (!(cpu_is_omap1510()))
295 ARM_RESTORE(ARM_IDLECT3);
296 ARM_RESTORE(ARM_CKCTL);
297 ARM_RESTORE(ARM_EWUPCT);
298 ARM_RESTORE(ARM_RSTCT1);
299 ARM_RESTORE(ARM_RSTCT2);
300 ARM_RESTORE(ARM_SYSST);
301 ULPD_RESTORE(ULPD_CLOCK_CTRL);
302 ULPD_RESTORE(ULPD_STATUS_REQ);
303
304 if (cpu_is_omap730()) {
305 MPUI730_RESTORE(EMIFS_CONFIG);
306 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
307 MPUI730_RESTORE(OMAP_IH1_MIR);
308 MPUI730_RESTORE(OMAP_IH2_0_MIR);
309 MPUI730_RESTORE(OMAP_IH2_1_MIR);
310 } else if (cpu_is_omap1510()) {
311 MPUI1510_RESTORE(MPUI_CTRL);
312 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
313 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
314 MPUI1510_RESTORE(EMIFS_CONFIG);
315 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
316 MPUI1510_RESTORE(OMAP_IH1_MIR);
317 MPUI1510_RESTORE(OMAP_IH2_MIR);
318 } else if (cpu_is_omap16xx()) {
319 MPUI1610_RESTORE(MPUI_CTRL);
320 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
321 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
322 MPUI1610_RESTORE(EMIFS_CONFIG);
323 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
324
325 MPUI1610_RESTORE(OMAP_IH1_MIR);
326 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
327 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
328 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
329 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
330 }
331
332 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
333
334 /*
335 * Reenable interrupts
336 */
337
338 local_irq_enable();
339 local_fiq_enable();
340
341 omap_serial_wake_trigger(0);
342
343 printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
344
345 if (machine_is_omap_osk()) {
346 /* Let LED1 (D9) blink again */
347 tps65010_set_led(LED1, BLINK);
348 }
349}
350
351#if defined(DEBUG) && defined(CONFIG_PROC_FS)
352static int g_read_completed;
353
354/*
355 * Read system PM registers for debugging
356 */
357static int omap_pm_read_proc(
358 char *page_buffer,
359 char **my_first_byte,
360 off_t virtual_start,
361 int length,
362 int *eof,
363 void *data)
364{
365 int my_buffer_offset = 0;
366 char * const my_base = page_buffer;
367
368 ARM_SAVE(ARM_CKCTL);
369 ARM_SAVE(ARM_IDLECT1);
370 ARM_SAVE(ARM_IDLECT2);
371 if (!(cpu_is_omap1510()))
372 ARM_SAVE(ARM_IDLECT3);
373 ARM_SAVE(ARM_EWUPCT);
374 ARM_SAVE(ARM_RSTCT1);
375 ARM_SAVE(ARM_RSTCT2);
376 ARM_SAVE(ARM_SYSST);
377
378 ULPD_SAVE(ULPD_IT_STATUS);
379 ULPD_SAVE(ULPD_CLOCK_CTRL);
380 ULPD_SAVE(ULPD_SOFT_REQ);
381 ULPD_SAVE(ULPD_STATUS_REQ);
382 ULPD_SAVE(ULPD_DPLL_CTRL);
383 ULPD_SAVE(ULPD_POWER_CTRL);
384
385 if (cpu_is_omap730()) {
386 MPUI730_SAVE(MPUI_CTRL);
387 MPUI730_SAVE(MPUI_DSP_STATUS);
388 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
389 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
390 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
391 MPUI730_SAVE(EMIFS_CONFIG);
392 } else if (cpu_is_omap1510()) {
393 MPUI1510_SAVE(MPUI_CTRL);
394 MPUI1510_SAVE(MPUI_DSP_STATUS);
395 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
396 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
397 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
398 MPUI1510_SAVE(EMIFS_CONFIG);
399 } else if (cpu_is_omap16xx()) {
400 MPUI1610_SAVE(MPUI_CTRL);
401 MPUI1610_SAVE(MPUI_DSP_STATUS);
402 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
403 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
404 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
405 MPUI1610_SAVE(EMIFS_CONFIG);
406 }
407
408 if (virtual_start == 0) {
409 g_read_completed = 0;
410
411 my_buffer_offset += sprintf(my_base + my_buffer_offset,
412 "ARM_CKCTL_REG: 0x%-8x \n"
413 "ARM_IDLECT1_REG: 0x%-8x \n"
414 "ARM_IDLECT2_REG: 0x%-8x \n"
415 "ARM_IDLECT3_REG: 0x%-8x \n"
416 "ARM_EWUPCT_REG: 0x%-8x \n"
417 "ARM_RSTCT1_REG: 0x%-8x \n"
418 "ARM_RSTCT2_REG: 0x%-8x \n"
419 "ARM_SYSST_REG: 0x%-8x \n"
420 "ULPD_IT_STATUS_REG: 0x%-4x \n"
421 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
422 "ULPD_SOFT_REQ_REG: 0x%-4x \n"
423 "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
424 "ULPD_STATUS_REQ_REG: 0x%-4x \n"
425 "ULPD_POWER_CTRL_REG: 0x%-4x \n",
426 ARM_SHOW(ARM_CKCTL),
427 ARM_SHOW(ARM_IDLECT1),
428 ARM_SHOW(ARM_IDLECT2),
429 ARM_SHOW(ARM_IDLECT3),
430 ARM_SHOW(ARM_EWUPCT),
431 ARM_SHOW(ARM_RSTCT1),
432 ARM_SHOW(ARM_RSTCT2),
433 ARM_SHOW(ARM_SYSST),
434 ULPD_SHOW(ULPD_IT_STATUS),
435 ULPD_SHOW(ULPD_CLOCK_CTRL),
436 ULPD_SHOW(ULPD_SOFT_REQ),
437 ULPD_SHOW(ULPD_DPLL_CTRL),
438 ULPD_SHOW(ULPD_STATUS_REQ),
439 ULPD_SHOW(ULPD_POWER_CTRL));
440
441 if (cpu_is_omap730()) {
442 my_buffer_offset += sprintf(my_base + my_buffer_offset,
443 "MPUI730_CTRL_REG 0x%-8x \n"
444 "MPUI730_DSP_STATUS_REG: 0x%-8x \n"
445 "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
446 "MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n"
447 "MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n"
448 "MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n",
449 MPUI730_SHOW(MPUI_CTRL),
450 MPUI730_SHOW(MPUI_DSP_STATUS),
451 MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
452 MPUI730_SHOW(MPUI_DSP_API_CONFIG),
453 MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
454 MPUI730_SHOW(EMIFS_CONFIG));
455 } else if (cpu_is_omap1510()) {
456 my_buffer_offset += sprintf(my_base + my_buffer_offset,
457 "MPUI1510_CTRL_REG 0x%-8x \n"
458 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
459 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
460 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
461 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
462 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
463 MPUI1510_SHOW(MPUI_CTRL),
464 MPUI1510_SHOW(MPUI_DSP_STATUS),
465 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
466 MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
467 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
468 MPUI1510_SHOW(EMIFS_CONFIG));
469 } else if (cpu_is_omap16xx()) {
470 my_buffer_offset += sprintf(my_base + my_buffer_offset,
471 "MPUI1610_CTRL_REG 0x%-8x \n"
472 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
473 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
474 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
475 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
476 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
477 MPUI1610_SHOW(MPUI_CTRL),
478 MPUI1610_SHOW(MPUI_DSP_STATUS),
479 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
480 MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
481 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
482 MPUI1610_SHOW(EMIFS_CONFIG));
483 }
484
485 g_read_completed++;
486 } else if (g_read_completed >= 1) {
487 *eof = 1;
488 return 0;
489 }
490 g_read_completed++;
491
492 *my_first_byte = page_buffer;
493 return my_buffer_offset;
494}
495
496static void omap_pm_init_proc(void)
497{
498 struct proc_dir_entry *entry;
499
500 entry = create_proc_read_entry("driver/omap_pm",
501 S_IWUSR | S_IRUGO, NULL,
502 omap_pm_read_proc, NULL);
503}
504
505#endif /* DEBUG && CONFIG_PROC_FS */
506
507/*
508 * omap_pm_prepare - Do preliminary suspend work.
509 * @state: suspend state we're entering.
510 *
511 */
512//#include <asm/hardware.h>
513
514static int omap_pm_prepare(suspend_state_t state)
515{
516 int error = 0;
517
518 switch (state)
519 {
520 case PM_SUSPEND_STANDBY:
521 case PM_SUSPEND_MEM:
522 break;
523
524 case PM_SUSPEND_DISK:
525 return -ENOTSUPP;
526
527 default:
528 return -EINVAL;
529 }
530
531 return error;
532}
533
534
535/*
536 * omap_pm_enter - Actually enter a sleep state.
537 * @state: State we're entering.
538 *
539 */
540
541static int omap_pm_enter(suspend_state_t state)
542{
543 switch (state)
544 {
545 case PM_SUSPEND_STANDBY:
546 case PM_SUSPEND_MEM:
547 omap_pm_suspend();
548 break;
549
550 case PM_SUSPEND_DISK:
551 return -ENOTSUPP;
552
553 default:
554 return -EINVAL;
555 }
556
557 return 0;
558}
559
560
561/**
562 * omap_pm_finish - Finish up suspend sequence.
563 * @state: State we're coming out of.
564 *
565 * This is called after we wake back up (or if entering the sleep state
566 * failed).
567 */
568
569static int omap_pm_finish(suspend_state_t state)
570{
571 return 0;
572}
573
574
575static irqreturn_t omap_wakeup_interrupt(int irq, void * dev,
576 struct pt_regs * regs)
577{
578 return IRQ_HANDLED;
579}
580
581static struct irqaction omap_wakeup_irq = {
582 .name = "peripheral wakeup",
583 .flags = IRQF_DISABLED,
584 .handler = omap_wakeup_interrupt
585};
586
587
588
589static struct pm_ops omap_pm_ops ={
590 .pm_disk_mode = 0,
591 .prepare = omap_pm_prepare,
592 .enter = omap_pm_enter,
593 .finish = omap_pm_finish,
594};
595
596static int __init omap_pm_init(void)
597{
598 printk("Power Management for TI OMAP.\n");
599 /*
600 * We copy the assembler sleep/wakeup routines to SRAM.
601 * These routines need to be in SRAM as that's the only
602 * memory the MPU can see when it wakes up.
603 */
604 if (cpu_is_omap730()) {
605 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
606 omap730_idle_loop_suspend_sz);
607 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
608 omap730_cpu_suspend_sz);
609 } else if (cpu_is_omap1510()) {
610 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
611 omap1510_idle_loop_suspend_sz);
612 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
613 omap1510_cpu_suspend_sz);
614 } else if (cpu_is_omap16xx()) {
615 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
616 omap1610_idle_loop_suspend_sz);
617 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
618 omap1610_cpu_suspend_sz);
619 }
620
621 if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
622 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
623 return -ENODEV;
624 }
625
626 pm_idle = omap_pm_idle;
627
628 if (cpu_is_omap730())
629 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
630 else if (cpu_is_omap16xx())
631 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
632
633#if 0
634 /* --- BEGIN BOARD-DEPENDENT CODE --- */
635 /* Sleepx mask direction */
636 omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
637 /* Unmask sleepx signal */
638 omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
639 /* --- END BOARD-DEPENDENT CODE --- */
640#endif
641
642 /* Program new power ramp-up time
643 * (0 for most boards since we don't lower voltage when in deep sleep)
644 */
645 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
646
647 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
648 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
649
650 /* Configure IDLECT3 */
651 if (cpu_is_omap730())
652 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
653 else if (cpu_is_omap16xx())
654 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
655
656 pm_set_ops(&omap_pm_ops);
657
658#if defined(DEBUG) && defined(CONFIG_PROC_FS)
659 omap_pm_init_proc();
660#endif
661
662 if (cpu_is_omap16xx()) {
663 /* configure LOW_PWR pin */
664 omap_cfg_reg(T20_1610_LOW_PWR);
665 }
666
667 return 0;
668}
669__initcall(omap_pm_init);
670
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index e75718301b0f..19014b2ff4c6 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -174,10 +174,7 @@ void __init omap_map_sram(void)
174 if (cpu_is_omap24xx()) { 174 if (cpu_is_omap24xx()) {
175 omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA; 175 omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
176 176
177 if (is_sram_locked()) 177 base = OMAP2_SRAM_PA;
178 base = OMAP2_SRAM_PUB_PA;
179 else
180 base = OMAP2_SRAM_PA;
181 base = ROUND_DOWN(base, PAGE_SIZE); 178 base = ROUND_DOWN(base, PAGE_SIZE);
182 omap_sram_io_desc[0].pfn = __phys_to_pfn(base); 179 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
183 } 180 }
diff --git a/arch/arm/plat-omap/timer32k.c b/arch/arm/plat-omap/timer32k.c
index 281ecc7fcdfc..cf6df3378d37 100644
--- a/arch/arm/plat-omap/timer32k.c
+++ b/arch/arm/plat-omap/timer32k.c
@@ -105,6 +105,8 @@ static inline unsigned long omap_32k_timer_read(int reg)
105 105
106static inline void omap_32k_timer_start(unsigned long load_val) 106static inline void omap_32k_timer_start(unsigned long load_val)
107{ 107{
108 if (!load_val)
109 load_val = 1;
108 omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR); 110 omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
109 omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR); 111 omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
110} 112}
@@ -192,14 +194,11 @@ unsigned long long sched_clock(void)
192 * issues with dynamic tick. In the dynamic tick case, we need to lock 194 * issues with dynamic tick. In the dynamic tick case, we need to lock
193 * with irqsave. 195 * with irqsave.
194 */ 196 */
195static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id, 197static inline irqreturn_t _omap_32k_timer_interrupt(int irq, void *dev_id,
196 struct pt_regs *regs) 198 struct pt_regs *regs)
197{ 199{
198 unsigned long flags;
199 unsigned long now; 200 unsigned long now;
200 201
201 write_seqlock_irqsave(&xtime_lock, flags);
202
203 omap_32k_timer_ack_irq(); 202 omap_32k_timer_ack_irq();
204 now = omap_32k_sync_timer_read(); 203 now = omap_32k_sync_timer_read();
205 204
@@ -215,6 +214,23 @@ static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
215 * continuous timer can be overridden from pm_idle to be longer. 214 * continuous timer can be overridden from pm_idle to be longer.
216 */ 215 */
217 omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now); 216 omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now);
217
218 return IRQ_HANDLED;
219}
220
221static irqreturn_t omap_32k_timer_handler(int irq, void *dev_id,
222 struct pt_regs *regs)
223{
224 return _omap_32k_timer_interrupt(irq, dev_id, regs);
225}
226
227static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
228 struct pt_regs *regs)
229{
230 unsigned long flags;
231
232 write_seqlock_irqsave(&xtime_lock, flags);
233 _omap_32k_timer_interrupt(irq, dev_id, regs);
218 write_sequnlock_irqrestore(&xtime_lock, flags); 234 write_sequnlock_irqrestore(&xtime_lock, flags);
219 235
220 return IRQ_HANDLED; 236 return IRQ_HANDLED;
@@ -230,7 +246,15 @@ static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
230 */ 246 */
231void omap_32k_timer_reprogram(unsigned long next_tick) 247void omap_32k_timer_reprogram(unsigned long next_tick)
232{ 248{
233 omap_32k_timer_start(JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1); 249 unsigned long ticks = JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1;
250 unsigned long now = omap_32k_sync_timer_read();
251 unsigned long idled = now - omap_32k_last_tick;
252
253 if (idled + 1 < ticks)
254 ticks -= idled;
255 else
256 ticks = 1;
257 omap_32k_timer_start(ticks);
234} 258}
235 259
236static struct irqaction omap_32k_timer_irq; 260static struct irqaction omap_32k_timer_irq;
@@ -252,7 +276,7 @@ static struct dyn_tick_timer omap_dyn_tick_timer = {
252 .enable = omap_32k_timer_enable_dyn_tick, 276 .enable = omap_32k_timer_enable_dyn_tick,
253 .disable = omap_32k_timer_disable_dyn_tick, 277 .disable = omap_32k_timer_disable_dyn_tick,
254 .reprogram = omap_32k_timer_reprogram, 278 .reprogram = omap_32k_timer_reprogram,
255 .handler = omap_32k_timer_interrupt, 279 .handler = omap_32k_timer_handler,
256}; 280};
257#endif /* CONFIG_NO_IDLE_HZ */ 281#endif /* CONFIG_NO_IDLE_HZ */
258 282
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index e1372a25311d..b02af1d740fa 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
12# 12#
13# http://www.arm.linux.org.uk/developer/machines/?action=new 13# http://www.arm.linux.org.uk/developer/machines/?action=new
14# 14#
15# Last update: Mon Jun 26 22:26:08 2006 15# Last update: Sat Sep 23 13:20:43 2006
16# 16#
17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number 17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
18# 18#
@@ -329,7 +329,7 @@ nimbra29x ARCH_NIMBRA29X NIMBRA29X 311
329nimbra210 ARCH_NIMBRA210 NIMBRA210 312 329nimbra210 ARCH_NIMBRA210 NIMBRA210 312
330hhp_d95xx ARCH_HHP_D95XX HHP_D95XX 313 330hhp_d95xx ARCH_HHP_D95XX HHP_D95XX 313
331labarm ARCH_LABARM LABARM 314 331labarm ARCH_LABARM LABARM 314
332comcerto ARCH_M825XX M825XX 315 332m825xx ARCH_M825XX M825XX 315
333m7100 SA1100_M7100 M7100 316 333m7100 SA1100_M7100 M7100 316
334nipc2 ARCH_NIPC2 NIPC2 317 334nipc2 ARCH_NIPC2 NIPC2 317
335fu7202 ARCH_FU7202 FU7202 318 335fu7202 ARCH_FU7202 FU7202 318
@@ -857,12 +857,12 @@ osiris MACH_OSIRIS OSIRIS 842
857maestro MACH_MAESTRO MAESTRO 843 857maestro MACH_MAESTRO MAESTRO 843
858tunge2 MACH_TUNGE2 TUNGE2 844 858tunge2 MACH_TUNGE2 TUNGE2 844
859ixbbm MACH_IXBBM IXBBM 845 859ixbbm MACH_IXBBM IXBBM 845
860mx27ads MACH_MX27 MX27 846 860mx27ads MACH_MX27ADS MX27ADS 846
861ax8004 MACH_AX8004 AX8004 847 861ax8004 MACH_AX8004 AX8004 847
862at91sam9261ek MACH_AT91SAM9261EK AT91SAM9261EK 848 862at91sam9261ek MACH_AT91SAM9261EK AT91SAM9261EK 848
863loft MACH_LOFT LOFT 849 863loft MACH_LOFT LOFT 849
864magpie MACH_MAGPIE MAGPIE 850 864magpie MACH_MAGPIE MAGPIE 850
865mx21ads MACH_MX21 MX21 851 865mx21ads MACH_MX21ADS MX21ADS 851
866mb87m3400 MACH_MB87M3400 MB87M3400 852 866mb87m3400 MACH_MB87M3400 MB87M3400 852
867mguard_delta MACH_MGUARD_DELTA MGUARD_DELTA 853 867mguard_delta MACH_MGUARD_DELTA MGUARD_DELTA 853
868davinci_dvdp MACH_DAVINCI_DVDP DAVINCI_DVDP 854 868davinci_dvdp MACH_DAVINCI_DVDP DAVINCI_DVDP 854
@@ -1058,7 +1058,7 @@ akai9307 MACH_AKAI9307 AKAI9307 1044
1058fontaine MACH_FONTAINE FONTAINE 1045 1058fontaine MACH_FONTAINE FONTAINE 1045
1059wombat MACH_WOMBAT WOMBAT 1046 1059wombat MACH_WOMBAT WOMBAT 1046
1060acq300 MACH_ACQ300 ACQ300 1047 1060acq300 MACH_ACQ300 ACQ300 1047
1061mod_270 MACH_MOD_270 MOD_270 1048 1061mod272 MACH_MOD_270 MOD_270 1048
1062vmc_vc0820 MACH_VC0820 VC0820 1049 1062vmc_vc0820 MACH_VC0820 VC0820 1049
1063ani_aim MACH_ANI_AIM ANI_AIM 1050 1063ani_aim MACH_ANI_AIM ANI_AIM 1050
1064jellyfish MACH_JELLYFISH JELLYFISH 1051 1064jellyfish MACH_JELLYFISH JELLYFISH 1051
@@ -1093,3 +1093,67 @@ msm6100 MACH_MSM6100 MSM6100 1079
1093eti_b1 MACH_ETI_B1 ETI_B1 1080 1093eti_b1 MACH_ETI_B1 ETI_B1 1080
1094za9l_series MACH_ZILOG_ZA9L ZILOG_ZA9L 1081 1094za9l_series MACH_ZILOG_ZA9L ZILOG_ZA9L 1081
1095bit2440 MACH_BIT2440 BIT2440 1082 1095bit2440 MACH_BIT2440 BIT2440 1082
1096nbi MACH_NBI NBI 1083
1097smdk2443 MACH_SMDK2443 SMDK2443 1084
1098vdavinci MACH_VDAVINCI VDAVINCI 1085
1099atc6 MACH_ATC6 ATC6 1086
1100multmdw MACH_MULTMDW MULTMDW 1087
1101mba2440 MACH_MBA2440 MBA2440 1088
1102ecsd MACH_ECSD ECSD 1089
1103zire31 MACH_ZIRE31 ZIRE31 1090
1104fsg MACH_FSG FSG 1091
1105razor101 MACH_RAZOR101 RAZOR101 1092
1106opera_tdm MACH_OPERA_TDM OPERA_TDM 1093
1107comcerto MACH_COMCERTO COMCERTO 1094
1108tb0319 MACH_TB0319 TB0319 1095
1109kws8000 MACH_KWS8000 KWS8000 1096
1110b2 MACH_B2 B2 1097
1111lcl54 MACH_LCL54 LCL54 1098
1112at91sam9260ek MACH_AT91SAM9260EK AT91SAM9260EK 1099
1113glantank MACH_GLANTANK GLANTANK 1100
1114n2100 MACH_N2100 N2100 1101
1115n4100 MACH_N4100 N4100 1102
1116rsc4 MACH_VERTICAL_RSC4 VERTICAL_RSC4 1103
1117sg8100 MACH_SG8100 SG8100 1104
1118im42xx MACH_IM42XX IM42XX 1105
1119ftxx MACH_FTXX FTXX 1106
1120lwfusion MACH_LWFUSION LWFUSION 1107
1121qt2410 MACH_QT2410 QT2410 1108
1122kixrp435 MACH_KIXRP435 KIXRP435 1109
1123ccw9c MACH_CCW9C CCW9C 1110
1124dabhs MACH_DABHS DABHS 1111
1125gzmx MACH_GZMX GZMX 1112
1126ipnw100ap MACH_IPNW100AP IPNW100AP 1113
1127cc9p9360dev MACH_CC9P9360DEV CC9P9360DEV 1114
1128cc9p9750dev MACH_CC9P9750DEV CC9P9750DEV 1115
1129cc9p9360val MACH_CC9P9360VAL CC9P9360VAL 1116
1130cc9p9750val MACH_CC9P9750VAL CC9P9750VAL 1117
1131nx70v MACH_NX70V NX70V 1118
1132at91rm9200df MACH_AT91RM9200DF AT91RM9200DF 1119
1133se_pilot2 MACH_SE_PILOT2 SE_PILOT2 1120
1134mtcn_t800 MACH_MTCN_T800 MTCN_T800 1121
1135vcmx212 MACH_VCMX212 VCMX212 1122
1136lynx MACH_LYNX LYNX 1123
1137at91sam9260id MACH_AT91SAM9260ID AT91SAM9260ID 1124
1138hw86052 MACH_HW86052 HW86052 1125
1139pilz_pmi3 MACH_PILZ_PMI3 PILZ_PMI3 1126
1140edb9302a MACH_EDB9302A EDB9302A 1127
1141edb9307a MACH_EDB9307A EDB9307A 1128
1142ct_dfs MACH_CT_DFS CT_DFS 1129
1143pilz_pmi4 MACH_PILZ_PMI4 PILZ_PMI4 1130
1144xceednp_ixp MACH_XCEEDNP_IXP XCEEDNP_IXP 1131
1145smdk2442b MACH_SMDK2442B SMDK2442B 1132
1146xnode MACH_XNODE XNODE 1133
1147aidx270 MACH_AIDX270 AIDX270 1134
1148rema MACH_REMA REMA 1135
1149bps1000 MACH_BPS1000 BPS1000 1136
1150hw90350 MACH_HW90350 HW90350 1137
1151omap_sdp3430 MACH_OMAP_SDP3430 OMAP_SDP3430 1138
1152bluetouch MACH_BLUETOUCH BLUETOUCH 1139
1153vstms MACH_VSTMS VSTMS 1140
1154xsbase270 MACH_XSBASE270 XSBASE270 1141
1155at91sam9260ek_cn MACH_AT91SAM9260EK_CN AT91SAM9260EK_CN 1142
1156adsturboxb MACH_ADSTURBOXB ADSTURBOXB 1143
1157oti4110 MACH_OTI4110 OTI4110 1144
1158hme_pxa MACH_HME_PXA HME_PXA 1145
1159deisterdca MACH_DEISTERDCA DEISTERDCA 1146
diff --git a/arch/arm/vfp/vfp.h b/arch/arm/vfp/vfp.h
index 96fdf30f6a3b..f2797896e6d5 100644
--- a/arch/arm/vfp/vfp.h
+++ b/arch/arm/vfp/vfp.h
@@ -355,3 +355,18 @@ u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand);
355 * we check for an error. 355 * we check for an error.
356 */ 356 */
357#define VFP_EXCEPTION_ERROR ((u32)-1 & ~VFP_NAN_FLAG) 357#define VFP_EXCEPTION_ERROR ((u32)-1 & ~VFP_NAN_FLAG)
358
359/*
360 * A flag to tell vfp instruction type.
361 * OP_SCALAR - this operation always operates in scalar mode
362 * OP_SD - the instruction exceptionally writes to a single precision result.
363 * OP_DD - the instruction exceptionally writes to a double precision result.
364 */
365#define OP_SCALAR (1 << 0)
366#define OP_SD (1 << 1)
367#define OP_DD (1 << 1)
368
369struct op {
370 u32 (* const fn)(int dd, int dn, int dm, u32 fpscr);
371 u32 flags;
372};
diff --git a/arch/arm/vfp/vfpdouble.c b/arch/arm/vfp/vfpdouble.c
index add48e36c2dc..4fc05ee0a2ef 100644
--- a/arch/arm/vfp/vfpdouble.c
+++ b/arch/arm/vfp/vfpdouble.c
@@ -659,22 +659,22 @@ static u32 vfp_double_ftosiz(int dd, int unused, int dm, u32 fpscr)
659} 659}
660 660
661 661
662static u32 (* const fop_extfns[32])(int dd, int unused, int dm, u32 fpscr) = { 662static struct op fops_ext[32] = {
663 [FEXT_TO_IDX(FEXT_FCPY)] = vfp_double_fcpy, 663 [FEXT_TO_IDX(FEXT_FCPY)] = { vfp_double_fcpy, 0 },
664 [FEXT_TO_IDX(FEXT_FABS)] = vfp_double_fabs, 664 [FEXT_TO_IDX(FEXT_FABS)] = { vfp_double_fabs, 0 },
665 [FEXT_TO_IDX(FEXT_FNEG)] = vfp_double_fneg, 665 [FEXT_TO_IDX(FEXT_FNEG)] = { vfp_double_fneg, 0 },
666 [FEXT_TO_IDX(FEXT_FSQRT)] = vfp_double_fsqrt, 666 [FEXT_TO_IDX(FEXT_FSQRT)] = { vfp_double_fsqrt, 0 },
667 [FEXT_TO_IDX(FEXT_FCMP)] = vfp_double_fcmp, 667 [FEXT_TO_IDX(FEXT_FCMP)] = { vfp_double_fcmp, OP_SCALAR },
668 [FEXT_TO_IDX(FEXT_FCMPE)] = vfp_double_fcmpe, 668 [FEXT_TO_IDX(FEXT_FCMPE)] = { vfp_double_fcmpe, OP_SCALAR },
669 [FEXT_TO_IDX(FEXT_FCMPZ)] = vfp_double_fcmpz, 669 [FEXT_TO_IDX(FEXT_FCMPZ)] = { vfp_double_fcmpz, OP_SCALAR },
670 [FEXT_TO_IDX(FEXT_FCMPEZ)] = vfp_double_fcmpez, 670 [FEXT_TO_IDX(FEXT_FCMPEZ)] = { vfp_double_fcmpez, OP_SCALAR },
671 [FEXT_TO_IDX(FEXT_FCVT)] = vfp_double_fcvts, 671 [FEXT_TO_IDX(FEXT_FCVT)] = { vfp_double_fcvts, OP_SCALAR|OP_SD },
672 [FEXT_TO_IDX(FEXT_FUITO)] = vfp_double_fuito, 672 [FEXT_TO_IDX(FEXT_FUITO)] = { vfp_double_fuito, OP_SCALAR },
673 [FEXT_TO_IDX(FEXT_FSITO)] = vfp_double_fsito, 673 [FEXT_TO_IDX(FEXT_FSITO)] = { vfp_double_fsito, OP_SCALAR },
674 [FEXT_TO_IDX(FEXT_FTOUI)] = vfp_double_ftoui, 674 [FEXT_TO_IDX(FEXT_FTOUI)] = { vfp_double_ftoui, OP_SCALAR|OP_SD },
675 [FEXT_TO_IDX(FEXT_FTOUIZ)] = vfp_double_ftouiz, 675 [FEXT_TO_IDX(FEXT_FTOUIZ)] = { vfp_double_ftouiz, OP_SCALAR|OP_SD },
676 [FEXT_TO_IDX(FEXT_FTOSI)] = vfp_double_ftosi, 676 [FEXT_TO_IDX(FEXT_FTOSI)] = { vfp_double_ftosi, OP_SCALAR|OP_SD },
677 [FEXT_TO_IDX(FEXT_FTOSIZ)] = vfp_double_ftosiz, 677 [FEXT_TO_IDX(FEXT_FTOSIZ)] = { vfp_double_ftosiz, OP_SCALAR|OP_SD },
678}; 678};
679 679
680 680
@@ -1108,16 +1108,16 @@ static u32 vfp_double_fdiv(int dd, int dn, int dm, u32 fpscr)
1108 return FPSCR_IOC; 1108 return FPSCR_IOC;
1109} 1109}
1110 1110
1111static u32 (* const fop_fns[16])(int dd, int dn, int dm, u32 fpscr) = { 1111static struct op fops[16] = {
1112 [FOP_TO_IDX(FOP_FMAC)] = vfp_double_fmac, 1112 [FOP_TO_IDX(FOP_FMAC)] = { vfp_double_fmac, 0 },
1113 [FOP_TO_IDX(FOP_FNMAC)] = vfp_double_fnmac, 1113 [FOP_TO_IDX(FOP_FNMAC)] = { vfp_double_fnmac, 0 },
1114 [FOP_TO_IDX(FOP_FMSC)] = vfp_double_fmsc, 1114 [FOP_TO_IDX(FOP_FMSC)] = { vfp_double_fmsc, 0 },
1115 [FOP_TO_IDX(FOP_FNMSC)] = vfp_double_fnmsc, 1115 [FOP_TO_IDX(FOP_FNMSC)] = { vfp_double_fnmsc, 0 },
1116 [FOP_TO_IDX(FOP_FMUL)] = vfp_double_fmul, 1116 [FOP_TO_IDX(FOP_FMUL)] = { vfp_double_fmul, 0 },
1117 [FOP_TO_IDX(FOP_FNMUL)] = vfp_double_fnmul, 1117 [FOP_TO_IDX(FOP_FNMUL)] = { vfp_double_fnmul, 0 },
1118 [FOP_TO_IDX(FOP_FADD)] = vfp_double_fadd, 1118 [FOP_TO_IDX(FOP_FADD)] = { vfp_double_fadd, 0 },
1119 [FOP_TO_IDX(FOP_FSUB)] = vfp_double_fsub, 1119 [FOP_TO_IDX(FOP_FSUB)] = { vfp_double_fsub, 0 },
1120 [FOP_TO_IDX(FOP_FDIV)] = vfp_double_fdiv, 1120 [FOP_TO_IDX(FOP_FDIV)] = { vfp_double_fdiv, 0 },
1121}; 1121};
1122 1122
1123#define FREG_BANK(x) ((x) & 0x0c) 1123#define FREG_BANK(x) ((x) & 0x0c)
@@ -1131,69 +1131,60 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
1131 unsigned int dn = vfp_get_dn(inst); 1131 unsigned int dn = vfp_get_dn(inst);
1132 unsigned int dm = vfp_get_dm(inst); 1132 unsigned int dm = vfp_get_dm(inst);
1133 unsigned int vecitr, veclen, vecstride; 1133 unsigned int vecitr, veclen, vecstride;
1134 u32 (*fop)(int, int, s32, u32); 1134 struct op *fop;
1135 1135
1136 veclen = fpscr & FPSCR_LENGTH_MASK;
1137 vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2; 1136 vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2;
1138 1137
1138 fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
1139
1139 /* 1140 /*
1140 * fcvtds takes an sN register number as destination, not dN. 1141 * fcvtds takes an sN register number as destination, not dN.
1141 * It also always operates on scalars. 1142 * It also always operates on scalars.
1142 */ 1143 */
1143 if ((inst & FEXT_MASK) == FEXT_FCVT) { 1144 if (fop->flags & OP_SD)
1144 veclen = 0;
1145 dest = vfp_get_sd(inst); 1145 dest = vfp_get_sd(inst);
1146 } else 1146 else
1147 dest = vfp_get_dd(inst); 1147 dest = vfp_get_dd(inst);
1148 1148
1149 /* 1149 /*
1150 * If destination bank is zero, vector length is always '1'. 1150 * If destination bank is zero, vector length is always '1'.
1151 * ARM DDI0100F C5.1.3, C5.3.2. 1151 * ARM DDI0100F C5.1.3, C5.3.2.
1152 */ 1152 */
1153 if (FREG_BANK(dest) == 0) 1153 if ((fop->flags & OP_SCALAR) || (FREG_BANK(dest) == 0))
1154 veclen = 0; 1154 veclen = 0;
1155 else
1156 veclen = fpscr & FPSCR_LENGTH_MASK;
1155 1157
1156 pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride, 1158 pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride,
1157 (veclen >> FPSCR_LENGTH_BIT) + 1); 1159 (veclen >> FPSCR_LENGTH_BIT) + 1);
1158 1160
1159 fop = (op == FOP_EXT) ? fop_extfns[FEXT_TO_IDX(inst)] : fop_fns[FOP_TO_IDX(op)]; 1161 if (!fop->fn)
1160 if (!fop)
1161 goto invalid; 1162 goto invalid;
1162 1163
1163 for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) { 1164 for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) {
1164 u32 except; 1165 u32 except;
1166 char type;
1165 1167
1166 if (op == FOP_EXT && (inst & FEXT_MASK) == FEXT_FCVT) 1168 type = fop->flags & OP_SD ? 's' : 'd';
1167 pr_debug("VFP: itr%d (s%u) = op[%u] (d%u)\n", 1169 if (op == FOP_EXT)
1168 vecitr >> FPSCR_LENGTH_BIT, 1170 pr_debug("VFP: itr%d (%c%u) = op[%u] (d%u)\n",
1169 dest, dn, dm);
1170 else if (op == FOP_EXT)
1171 pr_debug("VFP: itr%d (d%u) = op[%u] (d%u)\n",
1172 vecitr >> FPSCR_LENGTH_BIT, 1171 vecitr >> FPSCR_LENGTH_BIT,
1173 dest, dn, dm); 1172 type, dest, dn, dm);
1174 else 1173 else
1175 pr_debug("VFP: itr%d (d%u) = (d%u) op[%u] (d%u)\n", 1174 pr_debug("VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)\n",
1176 vecitr >> FPSCR_LENGTH_BIT, 1175 vecitr >> FPSCR_LENGTH_BIT,
1177 dest, dn, FOP_TO_IDX(op), dm); 1176 type, dest, dn, FOP_TO_IDX(op), dm);
1178 1177
1179 except = fop(dest, dn, dm, fpscr); 1178 except = fop->fn(dest, dn, dm, fpscr);
1180 pr_debug("VFP: itr%d: exceptions=%08x\n", 1179 pr_debug("VFP: itr%d: exceptions=%08x\n",
1181 vecitr >> FPSCR_LENGTH_BIT, except); 1180 vecitr >> FPSCR_LENGTH_BIT, except);
1182 1181
1183 exceptions |= except; 1182 exceptions |= except;
1184 1183
1185 /* 1184 /*
1186 * This ensures that comparisons only operate on scalars;
1187 * comparisons always return with one FPSCR status bit set.
1188 */
1189 if (except & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))
1190 break;
1191
1192 /*
1193 * CHECK: It appears to be undefined whether we stop when 1185 * CHECK: It appears to be undefined whether we stop when
1194 * we encounter an exception. We continue. 1186 * we encounter an exception. We continue.
1195 */ 1187 */
1196
1197 dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 6); 1188 dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 6);
1198 dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 6); 1189 dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 6);
1199 if (FREG_BANK(dm) != 0) 1190 if (FREG_BANK(dm) != 0)
diff --git a/arch/arm/vfp/vfpinstr.h b/arch/arm/vfp/vfpinstr.h
index 6c819aeae006..7f343a4beca0 100644
--- a/arch/arm/vfp/vfpinstr.h
+++ b/arch/arm/vfp/vfpinstr.h
@@ -73,14 +73,14 @@
73 73
74#define fmrx(_vfp_) ({ \ 74#define fmrx(_vfp_) ({ \
75 u32 __v; \ 75 u32 __v; \
76 asm("mrc%? p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \ 76 asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \
77 : "=r" (__v)); \ 77 : "=r" (__v) : : "cc"); \
78 __v; \ 78 __v; \
79 }) 79 })
80 80
81#define fmxr(_vfp_,_var_) \ 81#define fmxr(_vfp_,_var_) \
82 asm("mcr%? p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \ 82 asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
83 : : "r" (_var_)) 83 : : "r" (_var_) : "cc")
84 84
85u32 vfp_single_cpdo(u32 inst, u32 fpscr); 85u32 vfp_single_cpdo(u32 inst, u32 fpscr);
86u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs); 86u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs);
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 4178f6cc3d37..dedbb449632e 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -40,10 +40,19 @@ unsigned int VFP_arch;
40static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) 40static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
41{ 41{
42 struct thread_info *thread = v; 42 struct thread_info *thread = v;
43 union vfp_state *vfp = &thread->vfpstate; 43 union vfp_state *vfp;
44 44
45 switch (cmd) { 45 if (likely(cmd == THREAD_NOTIFY_SWITCH)) {
46 case THREAD_NOTIFY_FLUSH: 46 /*
47 * Always disable VFP so we can lazily save/restore the
48 * old state.
49 */
50 fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_ENABLE);
51 return NOTIFY_DONE;
52 }
53
54 vfp = &thread->vfpstate;
55 if (cmd == THREAD_NOTIFY_FLUSH) {
47 /* 56 /*
48 * Per-thread VFP initialisation. 57 * Per-thread VFP initialisation.
49 */ 58 */
@@ -56,29 +65,12 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
56 * Disable VFP to ensure we initialise it first. 65 * Disable VFP to ensure we initialise it first.
57 */ 66 */
58 fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_ENABLE); 67 fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_ENABLE);
59
60 /*
61 * FALLTHROUGH: Ensure we don't try to overwrite our newly
62 * initialised state information on the first fault.
63 */
64
65 case THREAD_NOTIFY_RELEASE:
66 /*
67 * Per-thread VFP cleanup.
68 */
69 if (last_VFP_context == vfp)
70 last_VFP_context = NULL;
71 break;
72
73 case THREAD_NOTIFY_SWITCH:
74 /*
75 * Always disable VFP so we can lazily save/restore the
76 * old state.
77 */
78 fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_ENABLE);
79 break;
80 } 68 }
81 69
70 /* flush and release case: Per-thread VFP cleanup. */
71 if (last_VFP_context == vfp)
72 last_VFP_context = NULL;
73
82 return NOTIFY_DONE; 74 return NOTIFY_DONE;
83} 75}
84 76
diff --git a/arch/arm/vfp/vfpsingle.c b/arch/arm/vfp/vfpsingle.c
index 8f6c179cafbe..ab5e9503bae5 100644
--- a/arch/arm/vfp/vfpsingle.c
+++ b/arch/arm/vfp/vfpsingle.c
@@ -702,22 +702,22 @@ static u32 vfp_single_ftosiz(int sd, int unused, s32 m, u32 fpscr)
702 return vfp_single_ftosi(sd, unused, m, FPSCR_ROUND_TOZERO); 702 return vfp_single_ftosi(sd, unused, m, FPSCR_ROUND_TOZERO);
703} 703}
704 704
705static u32 (* const fop_extfns[32])(int sd, int unused, s32 m, u32 fpscr) = { 705static struct op fops_ext[32] = {
706 [FEXT_TO_IDX(FEXT_FCPY)] = vfp_single_fcpy, 706 [FEXT_TO_IDX(FEXT_FCPY)] = { vfp_single_fcpy, 0 },
707 [FEXT_TO_IDX(FEXT_FABS)] = vfp_single_fabs, 707 [FEXT_TO_IDX(FEXT_FABS)] = { vfp_single_fabs, 0 },
708 [FEXT_TO_IDX(FEXT_FNEG)] = vfp_single_fneg, 708 [FEXT_TO_IDX(FEXT_FNEG)] = { vfp_single_fneg, 0 },
709 [FEXT_TO_IDX(FEXT_FSQRT)] = vfp_single_fsqrt, 709 [FEXT_TO_IDX(FEXT_FSQRT)] = { vfp_single_fsqrt, 0 },
710 [FEXT_TO_IDX(FEXT_FCMP)] = vfp_single_fcmp, 710 [FEXT_TO_IDX(FEXT_FCMP)] = { vfp_single_fcmp, OP_SCALAR },
711 [FEXT_TO_IDX(FEXT_FCMPE)] = vfp_single_fcmpe, 711 [FEXT_TO_IDX(FEXT_FCMPE)] = { vfp_single_fcmpe, OP_SCALAR },
712 [FEXT_TO_IDX(FEXT_FCMPZ)] = vfp_single_fcmpz, 712 [FEXT_TO_IDX(FEXT_FCMPZ)] = { vfp_single_fcmpz, OP_SCALAR },
713 [FEXT_TO_IDX(FEXT_FCMPEZ)] = vfp_single_fcmpez, 713 [FEXT_TO_IDX(FEXT_FCMPEZ)] = { vfp_single_fcmpez, OP_SCALAR },
714 [FEXT_TO_IDX(FEXT_FCVT)] = vfp_single_fcvtd, 714 [FEXT_TO_IDX(FEXT_FCVT)] = { vfp_single_fcvtd, OP_SCALAR|OP_DD },
715 [FEXT_TO_IDX(FEXT_FUITO)] = vfp_single_fuito, 715 [FEXT_TO_IDX(FEXT_FUITO)] = { vfp_single_fuito, OP_SCALAR },
716 [FEXT_TO_IDX(FEXT_FSITO)] = vfp_single_fsito, 716 [FEXT_TO_IDX(FEXT_FSITO)] = { vfp_single_fsito, OP_SCALAR },
717 [FEXT_TO_IDX(FEXT_FTOUI)] = vfp_single_ftoui, 717 [FEXT_TO_IDX(FEXT_FTOUI)] = { vfp_single_ftoui, OP_SCALAR },
718 [FEXT_TO_IDX(FEXT_FTOUIZ)] = vfp_single_ftouiz, 718 [FEXT_TO_IDX(FEXT_FTOUIZ)] = { vfp_single_ftouiz, OP_SCALAR },
719 [FEXT_TO_IDX(FEXT_FTOSI)] = vfp_single_ftosi, 719 [FEXT_TO_IDX(FEXT_FTOSI)] = { vfp_single_ftosi, OP_SCALAR },
720 [FEXT_TO_IDX(FEXT_FTOSIZ)] = vfp_single_ftosiz, 720 [FEXT_TO_IDX(FEXT_FTOSIZ)] = { vfp_single_ftosiz, OP_SCALAR },
721}; 721};
722 722
723 723
@@ -1151,16 +1151,16 @@ static u32 vfp_single_fdiv(int sd, int sn, s32 m, u32 fpscr)
1151 return FPSCR_IOC; 1151 return FPSCR_IOC;
1152} 1152}
1153 1153
1154static u32 (* const fop_fns[16])(int sd, int sn, s32 m, u32 fpscr) = { 1154static struct op fops[16] = {
1155 [FOP_TO_IDX(FOP_FMAC)] = vfp_single_fmac, 1155 [FOP_TO_IDX(FOP_FMAC)] = { vfp_single_fmac, 0 },
1156 [FOP_TO_IDX(FOP_FNMAC)] = vfp_single_fnmac, 1156 [FOP_TO_IDX(FOP_FNMAC)] = { vfp_single_fnmac, 0 },
1157 [FOP_TO_IDX(FOP_FMSC)] = vfp_single_fmsc, 1157 [FOP_TO_IDX(FOP_FMSC)] = { vfp_single_fmsc, 0 },
1158 [FOP_TO_IDX(FOP_FNMSC)] = vfp_single_fnmsc, 1158 [FOP_TO_IDX(FOP_FNMSC)] = { vfp_single_fnmsc, 0 },
1159 [FOP_TO_IDX(FOP_FMUL)] = vfp_single_fmul, 1159 [FOP_TO_IDX(FOP_FMUL)] = { vfp_single_fmul, 0 },
1160 [FOP_TO_IDX(FOP_FNMUL)] = vfp_single_fnmul, 1160 [FOP_TO_IDX(FOP_FNMUL)] = { vfp_single_fnmul, 0 },
1161 [FOP_TO_IDX(FOP_FADD)] = vfp_single_fadd, 1161 [FOP_TO_IDX(FOP_FADD)] = { vfp_single_fadd, 0 },
1162 [FOP_TO_IDX(FOP_FSUB)] = vfp_single_fsub, 1162 [FOP_TO_IDX(FOP_FSUB)] = { vfp_single_fsub, 0 },
1163 [FOP_TO_IDX(FOP_FDIV)] = vfp_single_fdiv, 1163 [FOP_TO_IDX(FOP_FDIV)] = { vfp_single_fdiv, 0 },
1164}; 1164};
1165 1165
1166#define FREG_BANK(x) ((x) & 0x18) 1166#define FREG_BANK(x) ((x) & 0x18)
@@ -1174,70 +1174,63 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
1174 unsigned int sn = vfp_get_sn(inst); 1174 unsigned int sn = vfp_get_sn(inst);
1175 unsigned int sm = vfp_get_sm(inst); 1175 unsigned int sm = vfp_get_sm(inst);
1176 unsigned int vecitr, veclen, vecstride; 1176 unsigned int vecitr, veclen, vecstride;
1177 u32 (*fop)(int, int, s32, u32); 1177 struct op *fop;
1178 1178
1179 veclen = fpscr & FPSCR_LENGTH_MASK;
1180 vecstride = 1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK); 1179 vecstride = 1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK);
1181 1180
1181 fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
1182
1182 /* 1183 /*
1183 * fcvtsd takes a dN register number as destination, not sN. 1184 * fcvtsd takes a dN register number as destination, not sN.
1184 * Technically, if bit 0 of dd is set, this is an invalid 1185 * Technically, if bit 0 of dd is set, this is an invalid
1185 * instruction. However, we ignore this for efficiency. 1186 * instruction. However, we ignore this for efficiency.
1186 * It also only operates on scalars. 1187 * It also only operates on scalars.
1187 */ 1188 */
1188 if ((inst & FEXT_MASK) == FEXT_FCVT) { 1189 if (fop->flags & OP_DD)
1189 veclen = 0;
1190 dest = vfp_get_dd(inst); 1190 dest = vfp_get_dd(inst);
1191 } else 1191 else
1192 dest = vfp_get_sd(inst); 1192 dest = vfp_get_sd(inst);
1193 1193
1194 /* 1194 /*
1195 * If destination bank is zero, vector length is always '1'. 1195 * If destination bank is zero, vector length is always '1'.
1196 * ARM DDI0100F C5.1.3, C5.3.2. 1196 * ARM DDI0100F C5.1.3, C5.3.2.
1197 */ 1197 */
1198 if (FREG_BANK(dest) == 0) 1198 if ((fop->flags & OP_SCALAR) || FREG_BANK(dest) == 0)
1199 veclen = 0; 1199 veclen = 0;
1200 else
1201 veclen = fpscr & FPSCR_LENGTH_MASK;
1200 1202
1201 pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride, 1203 pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride,
1202 (veclen >> FPSCR_LENGTH_BIT) + 1); 1204 (veclen >> FPSCR_LENGTH_BIT) + 1);
1203 1205
1204 fop = (op == FOP_EXT) ? fop_extfns[FEXT_TO_IDX(inst)] : fop_fns[FOP_TO_IDX(op)]; 1206 if (!fop->fn)
1205 if (!fop)
1206 goto invalid; 1207 goto invalid;
1207 1208
1208 for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) { 1209 for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) {
1209 s32 m = vfp_get_float(sm); 1210 s32 m = vfp_get_float(sm);
1210 u32 except; 1211 u32 except;
1212 char type;
1211 1213
1212 if (op == FOP_EXT && (inst & FEXT_MASK) == FEXT_FCVT) 1214 type = fop->flags & OP_DD ? 'd' : 's';
1213 pr_debug("VFP: itr%d (d%u) = op[%u] (s%u=%08x)\n", 1215 if (op == FOP_EXT)
1214 vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m); 1216 pr_debug("VFP: itr%d (%c%u) = op[%u] (s%u=%08x)\n",
1215 else if (op == FOP_EXT) 1217 vecitr >> FPSCR_LENGTH_BIT, type, dest, sn,
1216 pr_debug("VFP: itr%d (s%u) = op[%u] (s%u=%08x)\n", 1218 sm, m);
1217 vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m);
1218 else 1219 else
1219 pr_debug("VFP: itr%d (s%u) = (s%u) op[%u] (s%u=%08x)\n", 1220 pr_debug("VFP: itr%d (%c%u) = (s%u) op[%u] (s%u=%08x)\n",
1220 vecitr >> FPSCR_LENGTH_BIT, dest, sn, 1221 vecitr >> FPSCR_LENGTH_BIT, type, dest, sn,
1221 FOP_TO_IDX(op), sm, m); 1222 FOP_TO_IDX(op), sm, m);
1222 1223
1223 except = fop(dest, sn, m, fpscr); 1224 except = fop->fn(dest, sn, m, fpscr);
1224 pr_debug("VFP: itr%d: exceptions=%08x\n", 1225 pr_debug("VFP: itr%d: exceptions=%08x\n",
1225 vecitr >> FPSCR_LENGTH_BIT, except); 1226 vecitr >> FPSCR_LENGTH_BIT, except);
1226 1227
1227 exceptions |= except; 1228 exceptions |= except;
1228 1229
1229 /* 1230 /*
1230 * This ensures that comparisons only operate on scalars;
1231 * comparisons always return with one FPSCR status bit set.
1232 */
1233 if (except & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))
1234 break;
1235
1236 /*
1237 * CHECK: It appears to be undefined whether we stop when 1231 * CHECK: It appears to be undefined whether we stop when
1238 * we encounter an exception. We continue. 1232 * we encounter an exception. We continue.
1239 */ 1233 */
1240
1241 dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 7); 1234 dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 7);
1242 sn = FREG_BANK(sn) + ((FREG_IDX(sn) + vecstride) & 7); 1235 sn = FREG_BANK(sn) + ((FREG_IDX(sn) + vecstride) & 7);
1243 if (FREG_BANK(sm) != 0) 1236 if (FREG_BANK(sm) != 0)