diff options
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-omap2/clock.c | 46 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock34xx.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock34xx.h | 196 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clockdomains.h | 9 |
5 files changed, 232 insertions, 24 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 1d891e4a6933..aa9b37370d44 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <asm/io.h> | 26 | #include <asm/io.h> |
27 | 27 | ||
28 | #include <mach/clock.h> | 28 | #include <mach/clock.h> |
29 | #include <mach/clockdomain.h> | ||
29 | #include <mach/sram.h> | 30 | #include <mach/sram.h> |
30 | #include <mach/cpu.h> | 31 | #include <mach/cpu.h> |
31 | #include <asm/div64.h> | 32 | #include <asm/div64.h> |
@@ -62,10 +63,36 @@ | |||
62 | u8 cpu_mask; | 63 | u8 cpu_mask; |
63 | 64 | ||
64 | /*------------------------------------------------------------------------- | 65 | /*------------------------------------------------------------------------- |
65 | * Omap2 specific clock functions | 66 | * OMAP2/3 specific clock functions |
66 | *-------------------------------------------------------------------------*/ | 67 | *-------------------------------------------------------------------------*/ |
67 | 68 | ||
68 | /** | 69 | /** |
70 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk | ||
71 | * @clk: OMAP clock struct ptr to use | ||
72 | * | ||
73 | * Convert a clockdomain name stored in a struct clk 'clk' into a | ||
74 | * clockdomain pointer, and save it into the struct clk. Intended to be | ||
75 | * called during clk_register(). No return value. | ||
76 | */ | ||
77 | void omap2_init_clk_clkdm(struct clk *clk) | ||
78 | { | ||
79 | struct clockdomain *clkdm; | ||
80 | |||
81 | if (!clk->clkdm_name) | ||
82 | return; | ||
83 | |||
84 | clkdm = clkdm_lookup(clk->clkdm_name); | ||
85 | if (clkdm) { | ||
86 | pr_debug("clock: associated clk %s to clkdm %s\n", | ||
87 | clk->name, clk->clkdm_name); | ||
88 | clk->clkdm = clkdm; | ||
89 | } else { | ||
90 | pr_debug("clock: could not associate clk %s to " | ||
91 | "clkdm %s\n", clk->name, clk->clkdm_name); | ||
92 | } | ||
93 | } | ||
94 | |||
95 | /** | ||
69 | * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware | 96 | * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware |
70 | * @clk: OMAP clock struct ptr to use | 97 | * @clk: OMAP clock struct ptr to use |
71 | * | 98 | * |
@@ -308,6 +335,9 @@ void omap2_clk_disable(struct clk *clk) | |||
308 | _omap2_clk_disable(clk); | 335 | _omap2_clk_disable(clk); |
309 | if (likely((u32)clk->parent)) | 336 | if (likely((u32)clk->parent)) |
310 | omap2_clk_disable(clk->parent); | 337 | omap2_clk_disable(clk->parent); |
338 | if (clk->clkdm) | ||
339 | omap2_clkdm_clk_disable(clk->clkdm, clk); | ||
340 | |||
311 | } | 341 | } |
312 | } | 342 | } |
313 | 343 | ||
@@ -324,11 +354,19 @@ int omap2_clk_enable(struct clk *clk) | |||
324 | return ret; | 354 | return ret; |
325 | } | 355 | } |
326 | 356 | ||
357 | if (clk->clkdm) | ||
358 | omap2_clkdm_clk_enable(clk->clkdm, clk); | ||
359 | |||
327 | ret = _omap2_clk_enable(clk); | 360 | ret = _omap2_clk_enable(clk); |
328 | 361 | ||
329 | if (unlikely(ret != 0) && clk->parent) { | 362 | if (unlikely(ret != 0)) { |
330 | omap2_clk_disable(clk->parent); | 363 | if (clk->clkdm) |
331 | clk->usecount--; | 364 | omap2_clkdm_clk_disable(clk->clkdm, clk); |
365 | |||
366 | if (clk->parent) { | ||
367 | omap2_clk_disable(clk->parent); | ||
368 | clk->usecount--; | ||
369 | } | ||
332 | } | 370 | } |
333 | } | 371 | } |
334 | 372 | ||
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 626e5fa93b6a..ea55f286f47d 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h | |||
@@ -36,6 +36,7 @@ void omap2_clk_disable_unused(struct clk *clk); | |||
36 | #endif | 36 | #endif |
37 | 37 | ||
38 | void omap2_clksel_recalc(struct clk *clk); | 38 | void omap2_clksel_recalc(struct clk *clk); |
39 | void omap2_init_clk_clkdm(struct clk *clk); | ||
39 | void omap2_init_clksel_parent(struct clk *clk); | 40 | void omap2_init_clksel_parent(struct clk *clk); |
40 | u32 omap2_clksel_get_divisor(struct clk *clk); | 41 | u32 omap2_clksel_get_divisor(struct clk *clk); |
41 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | 42 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, |
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index dff7a72fefc9..0bf661df6643 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c | |||
@@ -489,8 +489,10 @@ int __init omap2_clk_init(void) | |||
489 | for (clkp = onchip_34xx_clks; | 489 | for (clkp = onchip_34xx_clks; |
490 | clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks); | 490 | clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks); |
491 | clkp++) { | 491 | clkp++) { |
492 | if ((*clkp)->flags & cpu_clkflg) | 492 | if ((*clkp)->flags & cpu_clkflg) { |
493 | clk_register(*clkp); | 493 | clk_register(*clkp); |
494 | omap2_init_clk_clkdm(*clkp); | ||
495 | } | ||
494 | } | 496 | } |
495 | 497 | ||
496 | /* REVISIT: Not yet ready for OMAP3 */ | 498 | /* REVISIT: Not yet ready for OMAP3 */ |
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index ec664457a11a..bb01e2014818 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h | |||
@@ -478,7 +478,7 @@ static struct clk dpll3_m2_ck = { | |||
478 | }; | 478 | }; |
479 | 479 | ||
480 | static const struct clksel core_ck_clksel[] = { | 480 | static const struct clksel core_ck_clksel[] = { |
481 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | 481 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
482 | { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, | 482 | { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, |
483 | { .parent = NULL } | 483 | { .parent = NULL } |
484 | }; | 484 | }; |
@@ -495,7 +495,7 @@ static struct clk core_ck = { | |||
495 | }; | 495 | }; |
496 | 496 | ||
497 | static const struct clksel dpll3_m2x2_ck_clksel[] = { | 497 | static const struct clksel dpll3_m2x2_ck_clksel[] = { |
498 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | 498 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
499 | { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, | 499 | { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, |
500 | { .parent = NULL } | 500 | { .parent = NULL } |
501 | }; | 501 | }; |
@@ -541,7 +541,7 @@ static struct clk dpll3_m3x2_ck = { | |||
541 | }; | 541 | }; |
542 | 542 | ||
543 | static const struct clksel emu_core_alwon_ck_clksel[] = { | 543 | static const struct clksel emu_core_alwon_ck_clksel[] = { |
544 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | 544 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
545 | { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, | 545 | { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, |
546 | { .parent = NULL } | 546 | { .parent = NULL } |
547 | }; | 547 | }; |
@@ -633,7 +633,7 @@ static struct clk dpll4_m2x2_ck = { | |||
633 | }; | 633 | }; |
634 | 634 | ||
635 | static const struct clksel omap_96m_alwon_fck_clksel[] = { | 635 | static const struct clksel omap_96m_alwon_fck_clksel[] = { |
636 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | 636 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
637 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, | 637 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, |
638 | { .parent = NULL } | 638 | { .parent = NULL } |
639 | }; | 639 | }; |
@@ -659,7 +659,7 @@ static struct clk omap_96m_fck = { | |||
659 | }; | 659 | }; |
660 | 660 | ||
661 | static const struct clksel cm_96m_fck_clksel[] = { | 661 | static const struct clksel cm_96m_fck_clksel[] = { |
662 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | 662 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
663 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, | 663 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, |
664 | { .parent = NULL } | 664 | { .parent = NULL } |
665 | }; | 665 | }; |
@@ -701,7 +701,7 @@ static struct clk dpll4_m3x2_ck = { | |||
701 | }; | 701 | }; |
702 | 702 | ||
703 | static const struct clksel virt_omap_54m_fck_clksel[] = { | 703 | static const struct clksel virt_omap_54m_fck_clksel[] = { |
704 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | 704 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
705 | { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, | 705 | { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, |
706 | { .parent = NULL } | 706 | { .parent = NULL } |
707 | }; | 707 | }; |
@@ -911,7 +911,7 @@ static struct clk dpll5_m2_ck = { | |||
911 | }; | 911 | }; |
912 | 912 | ||
913 | static const struct clksel omap_120m_fck_clksel[] = { | 913 | static const struct clksel omap_120m_fck_clksel[] = { |
914 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | 914 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
915 | { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, | 915 | { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, |
916 | { .parent = NULL } | 916 | { .parent = NULL } |
917 | }; | 917 | }; |
@@ -919,13 +919,13 @@ static const struct clksel omap_120m_fck_clksel[] = { | |||
919 | static struct clk omap_120m_fck = { | 919 | static struct clk omap_120m_fck = { |
920 | .name = "omap_120m_fck", | 920 | .name = "omap_120m_fck", |
921 | .parent = &dpll5_m2_ck, | 921 | .parent = &dpll5_m2_ck, |
922 | .init = &omap2_init_clksel_parent, | 922 | .init = &omap2_init_clksel_parent, |
923 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), | 923 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), |
924 | .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, | 924 | .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, |
925 | .clksel = omap_120m_fck_clksel, | 925 | .clksel = omap_120m_fck_clksel, |
926 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | | 926 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | |
927 | PARENT_CONTROLS_CLOCK, | 927 | PARENT_CONTROLS_CLOCK, |
928 | .recalc = &omap2_clksel_recalc, | 928 | .recalc = &omap2_clksel_recalc, |
929 | }; | 929 | }; |
930 | 930 | ||
931 | /* CM EXTERNAL CLOCK OUTPUTS */ | 931 | /* CM EXTERNAL CLOCK OUTPUTS */ |
@@ -1034,7 +1034,7 @@ static struct clk dpll1_fck = { | |||
1034 | * called 'dpll1_fck' | 1034 | * called 'dpll1_fck' |
1035 | */ | 1035 | */ |
1036 | static const struct clksel mpu_clksel[] = { | 1036 | static const struct clksel mpu_clksel[] = { |
1037 | { .parent = &dpll1_fck, .rates = dpll_bypass_rates }, | 1037 | { .parent = &dpll1_fck, .rates = dpll_bypass_rates }, |
1038 | { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, | 1038 | { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, |
1039 | { .parent = NULL } | 1039 | { .parent = NULL } |
1040 | }; | 1040 | }; |
@@ -1048,6 +1048,7 @@ static struct clk mpu_ck = { | |||
1048 | .clksel = mpu_clksel, | 1048 | .clksel = mpu_clksel, |
1049 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 1049 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
1050 | PARENT_CONTROLS_CLOCK, | 1050 | PARENT_CONTROLS_CLOCK, |
1051 | .clkdm_name = "mpu_clkdm", | ||
1051 | .recalc = &omap2_clksel_recalc, | 1052 | .recalc = &omap2_clksel_recalc, |
1052 | }; | 1053 | }; |
1053 | 1054 | ||
@@ -1075,6 +1076,8 @@ static struct clk arm_fck = { | |||
1075 | .recalc = &omap2_clksel_recalc, | 1076 | .recalc = &omap2_clksel_recalc, |
1076 | }; | 1077 | }; |
1077 | 1078 | ||
1079 | /* XXX What about neon_clkdm ? */ | ||
1080 | |||
1078 | /* | 1081 | /* |
1079 | * REVISIT: This clock is never specifically defined in the 3430 TRM, | 1082 | * REVISIT: This clock is never specifically defined in the 3430 TRM, |
1080 | * although it is referenced - so this is a guess | 1083 | * although it is referenced - so this is a guess |
@@ -1107,7 +1110,7 @@ static struct clk dpll2_fck = { | |||
1107 | */ | 1110 | */ |
1108 | 1111 | ||
1109 | static const struct clksel iva2_clksel[] = { | 1112 | static const struct clksel iva2_clksel[] = { |
1110 | { .parent = &dpll2_fck, .rates = dpll_bypass_rates }, | 1113 | { .parent = &dpll2_fck, .rates = dpll_bypass_rates }, |
1111 | { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, | 1114 | { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, |
1112 | { .parent = NULL } | 1115 | { .parent = NULL } |
1113 | }; | 1116 | }; |
@@ -1123,6 +1126,7 @@ static struct clk iva2_ck = { | |||
1123 | .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, | 1126 | .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, |
1124 | .clksel = iva2_clksel, | 1127 | .clksel = iva2_clksel, |
1125 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | 1128 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
1129 | .clkdm_name = "iva2_clkdm", | ||
1126 | .recalc = &omap2_clksel_recalc, | 1130 | .recalc = &omap2_clksel_recalc, |
1127 | }; | 1131 | }; |
1128 | 1132 | ||
@@ -1137,6 +1141,7 @@ static struct clk l3_ick = { | |||
1137 | .clksel = div2_core_clksel, | 1141 | .clksel = div2_core_clksel, |
1138 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 1142 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
1139 | PARENT_CONTROLS_CLOCK, | 1143 | PARENT_CONTROLS_CLOCK, |
1144 | .clkdm_name = "core_l3_clkdm", | ||
1140 | .recalc = &omap2_clksel_recalc, | 1145 | .recalc = &omap2_clksel_recalc, |
1141 | }; | 1146 | }; |
1142 | 1147 | ||
@@ -1154,6 +1159,7 @@ static struct clk l4_ick = { | |||
1154 | .clksel = div2_l3_clksel, | 1159 | .clksel = div2_l3_clksel, |
1155 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 1160 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
1156 | PARENT_CONTROLS_CLOCK, | 1161 | PARENT_CONTROLS_CLOCK, |
1162 | .clkdm_name = "core_l4_clkdm", | ||
1157 | .recalc = &omap2_clksel_recalc, | 1163 | .recalc = &omap2_clksel_recalc, |
1158 | 1164 | ||
1159 | }; | 1165 | }; |
@@ -1193,33 +1199,40 @@ static struct clk gfx_l3_fck = { | |||
1193 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | 1199 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
1194 | .clksel = gfx_l3_clksel, | 1200 | .clksel = gfx_l3_clksel, |
1195 | .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES, | 1201 | .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES, |
1202 | .clkdm_name = "gfx_3430es1_clkdm", | ||
1196 | .recalc = &omap2_clksel_recalc, | 1203 | .recalc = &omap2_clksel_recalc, |
1197 | }; | 1204 | }; |
1198 | 1205 | ||
1199 | static struct clk gfx_l3_ick = { | 1206 | static struct clk gfx_l3_ick = { |
1200 | .name = "gfx_l3_ick", | 1207 | .name = "gfx_l3_ick", |
1201 | .parent = &l3_ick, | 1208 | .parent = &l3_ick, |
1209 | .init = &omap2_init_clk_clkdm, | ||
1202 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | 1210 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
1203 | .enable_bit = OMAP_EN_GFX_SHIFT, | 1211 | .enable_bit = OMAP_EN_GFX_SHIFT, |
1204 | .flags = CLOCK_IN_OMAP3430ES1, | 1212 | .flags = CLOCK_IN_OMAP3430ES1, |
1213 | .clkdm_name = "gfx_3430es1_clkdm", | ||
1205 | .recalc = &followparent_recalc, | 1214 | .recalc = &followparent_recalc, |
1206 | }; | 1215 | }; |
1207 | 1216 | ||
1208 | static struct clk gfx_cg1_ck = { | 1217 | static struct clk gfx_cg1_ck = { |
1209 | .name = "gfx_cg1_ck", | 1218 | .name = "gfx_cg1_ck", |
1210 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | 1219 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
1220 | .init = &omap2_init_clk_clkdm, | ||
1211 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 1221 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
1212 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, | 1222 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, |
1213 | .flags = CLOCK_IN_OMAP3430ES1, | 1223 | .flags = CLOCK_IN_OMAP3430ES1, |
1224 | .clkdm_name = "gfx_3430es1_clkdm", | ||
1214 | .recalc = &followparent_recalc, | 1225 | .recalc = &followparent_recalc, |
1215 | }; | 1226 | }; |
1216 | 1227 | ||
1217 | static struct clk gfx_cg2_ck = { | 1228 | static struct clk gfx_cg2_ck = { |
1218 | .name = "gfx_cg2_ck", | 1229 | .name = "gfx_cg2_ck", |
1219 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | 1230 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
1231 | .init = &omap2_init_clk_clkdm, | ||
1220 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 1232 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
1221 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, | 1233 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, |
1222 | .flags = CLOCK_IN_OMAP3430ES1, | 1234 | .flags = CLOCK_IN_OMAP3430ES1, |
1235 | .clkdm_name = "gfx_3430es1_clkdm", | ||
1223 | .recalc = &followparent_recalc, | 1236 | .recalc = &followparent_recalc, |
1224 | }; | 1237 | }; |
1225 | 1238 | ||
@@ -1252,15 +1265,18 @@ static struct clk sgx_fck = { | |||
1252 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, | 1265 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, |
1253 | .clksel = sgx_clksel, | 1266 | .clksel = sgx_clksel, |
1254 | .flags = CLOCK_IN_OMAP3430ES2, | 1267 | .flags = CLOCK_IN_OMAP3430ES2, |
1268 | .clkdm_name = "sgx_clkdm", | ||
1255 | .recalc = &omap2_clksel_recalc, | 1269 | .recalc = &omap2_clksel_recalc, |
1256 | }; | 1270 | }; |
1257 | 1271 | ||
1258 | static struct clk sgx_ick = { | 1272 | static struct clk sgx_ick = { |
1259 | .name = "sgx_ick", | 1273 | .name = "sgx_ick", |
1260 | .parent = &l3_ick, | 1274 | .parent = &l3_ick, |
1275 | .init = &omap2_init_clk_clkdm, | ||
1261 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), | 1276 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), |
1262 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, | 1277 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, |
1263 | .flags = CLOCK_IN_OMAP3430ES2, | 1278 | .flags = CLOCK_IN_OMAP3430ES2, |
1279 | .clkdm_name = "sgx_clkdm", | ||
1264 | .recalc = &followparent_recalc, | 1280 | .recalc = &followparent_recalc, |
1265 | }; | 1281 | }; |
1266 | 1282 | ||
@@ -1269,9 +1285,11 @@ static struct clk sgx_ick = { | |||
1269 | static struct clk d2d_26m_fck = { | 1285 | static struct clk d2d_26m_fck = { |
1270 | .name = "d2d_26m_fck", | 1286 | .name = "d2d_26m_fck", |
1271 | .parent = &sys_ck, | 1287 | .parent = &sys_ck, |
1288 | .init = &omap2_init_clk_clkdm, | ||
1272 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1289 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1273 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, | 1290 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, |
1274 | .flags = CLOCK_IN_OMAP3430ES1, | 1291 | .flags = CLOCK_IN_OMAP3430ES1, |
1292 | .clkdm_name = "d2d_clkdm", | ||
1275 | .recalc = &followparent_recalc, | 1293 | .recalc = &followparent_recalc, |
1276 | }; | 1294 | }; |
1277 | 1295 | ||
@@ -1291,6 +1309,7 @@ static struct clk gpt10_fck = { | |||
1291 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, | 1309 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, |
1292 | .clksel = omap343x_gpt_clksel, | 1310 | .clksel = omap343x_gpt_clksel, |
1293 | .flags = CLOCK_IN_OMAP343X, | 1311 | .flags = CLOCK_IN_OMAP343X, |
1312 | .clkdm_name = "core_l4_clkdm", | ||
1294 | .recalc = &omap2_clksel_recalc, | 1313 | .recalc = &omap2_clksel_recalc, |
1295 | }; | 1314 | }; |
1296 | 1315 | ||
@@ -1304,6 +1323,7 @@ static struct clk gpt11_fck = { | |||
1304 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, | 1323 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, |
1305 | .clksel = omap343x_gpt_clksel, | 1324 | .clksel = omap343x_gpt_clksel, |
1306 | .flags = CLOCK_IN_OMAP343X, | 1325 | .flags = CLOCK_IN_OMAP343X, |
1326 | .clkdm_name = "core_l4_clkdm", | ||
1307 | .recalc = &omap2_clksel_recalc, | 1327 | .recalc = &omap2_clksel_recalc, |
1308 | }; | 1328 | }; |
1309 | 1329 | ||
@@ -1341,6 +1361,7 @@ static struct clk core_96m_fck = { | |||
1341 | .parent = &omap_96m_fck, | 1361 | .parent = &omap_96m_fck, |
1342 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 1362 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
1343 | PARENT_CONTROLS_CLOCK, | 1363 | PARENT_CONTROLS_CLOCK, |
1364 | .clkdm_name = "core_l4_clkdm", | ||
1344 | .recalc = &followparent_recalc, | 1365 | .recalc = &followparent_recalc, |
1345 | }; | 1366 | }; |
1346 | 1367 | ||
@@ -1351,6 +1372,7 @@ static struct clk mmchs3_fck = { | |||
1351 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1372 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1352 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | 1373 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
1353 | .flags = CLOCK_IN_OMAP3430ES2, | 1374 | .flags = CLOCK_IN_OMAP3430ES2, |
1375 | .clkdm_name = "core_l4_clkdm", | ||
1354 | .recalc = &followparent_recalc, | 1376 | .recalc = &followparent_recalc, |
1355 | }; | 1377 | }; |
1356 | 1378 | ||
@@ -1361,6 +1383,7 @@ static struct clk mmchs2_fck = { | |||
1361 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1383 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1362 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | 1384 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
1363 | .flags = CLOCK_IN_OMAP343X, | 1385 | .flags = CLOCK_IN_OMAP343X, |
1386 | .clkdm_name = "core_l4_clkdm", | ||
1364 | .recalc = &followparent_recalc, | 1387 | .recalc = &followparent_recalc, |
1365 | }; | 1388 | }; |
1366 | 1389 | ||
@@ -1370,6 +1393,7 @@ static struct clk mspro_fck = { | |||
1370 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1393 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1371 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | 1394 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, |
1372 | .flags = CLOCK_IN_OMAP343X, | 1395 | .flags = CLOCK_IN_OMAP343X, |
1396 | .clkdm_name = "core_l4_clkdm", | ||
1373 | .recalc = &followparent_recalc, | 1397 | .recalc = &followparent_recalc, |
1374 | }; | 1398 | }; |
1375 | 1399 | ||
@@ -1380,6 +1404,7 @@ static struct clk mmchs1_fck = { | |||
1380 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1404 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1381 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | 1405 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, |
1382 | .flags = CLOCK_IN_OMAP343X, | 1406 | .flags = CLOCK_IN_OMAP343X, |
1407 | .clkdm_name = "core_l4_clkdm", | ||
1383 | .recalc = &followparent_recalc, | 1408 | .recalc = &followparent_recalc, |
1384 | }; | 1409 | }; |
1385 | 1410 | ||
@@ -1390,16 +1415,18 @@ static struct clk i2c3_fck = { | |||
1390 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1415 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1391 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | 1416 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
1392 | .flags = CLOCK_IN_OMAP343X, | 1417 | .flags = CLOCK_IN_OMAP343X, |
1418 | .clkdm_name = "core_l4_clkdm", | ||
1393 | .recalc = &followparent_recalc, | 1419 | .recalc = &followparent_recalc, |
1394 | }; | 1420 | }; |
1395 | 1421 | ||
1396 | static struct clk i2c2_fck = { | 1422 | static struct clk i2c2_fck = { |
1397 | .name = "i2c_fck", | 1423 | .name = "i2c_fck", |
1398 | .id = 2, | 1424 | .id = 2, |
1399 | .parent = &core_96m_fck, | 1425 | .parent = &core_96m_fck, |
1400 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1426 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1401 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | 1427 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
1402 | .flags = CLOCK_IN_OMAP343X, | 1428 | .flags = CLOCK_IN_OMAP343X, |
1429 | .clkdm_name = "core_l4_clkdm", | ||
1403 | .recalc = &followparent_recalc, | 1430 | .recalc = &followparent_recalc, |
1404 | }; | 1431 | }; |
1405 | 1432 | ||
@@ -1410,6 +1437,7 @@ static struct clk i2c1_fck = { | |||
1410 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1437 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1411 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | 1438 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
1412 | .flags = CLOCK_IN_OMAP343X, | 1439 | .flags = CLOCK_IN_OMAP343X, |
1440 | .clkdm_name = "core_l4_clkdm", | ||
1413 | .recalc = &followparent_recalc, | 1441 | .recalc = &followparent_recalc, |
1414 | }; | 1442 | }; |
1415 | 1443 | ||
@@ -1443,6 +1471,7 @@ static struct clk mcbsp5_fck = { | |||
1443 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, | 1471 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, |
1444 | .clksel = mcbsp_15_clksel, | 1472 | .clksel = mcbsp_15_clksel, |
1445 | .flags = CLOCK_IN_OMAP343X, | 1473 | .flags = CLOCK_IN_OMAP343X, |
1474 | .clkdm_name = "core_l4_clkdm", | ||
1446 | .recalc = &omap2_clksel_recalc, | 1475 | .recalc = &omap2_clksel_recalc, |
1447 | }; | 1476 | }; |
1448 | 1477 | ||
@@ -1456,6 +1485,7 @@ static struct clk mcbsp1_fck = { | |||
1456 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, | 1485 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, |
1457 | .clksel = mcbsp_15_clksel, | 1486 | .clksel = mcbsp_15_clksel, |
1458 | .flags = CLOCK_IN_OMAP343X, | 1487 | .flags = CLOCK_IN_OMAP343X, |
1488 | .clkdm_name = "core_l4_clkdm", | ||
1459 | .recalc = &omap2_clksel_recalc, | 1489 | .recalc = &omap2_clksel_recalc, |
1460 | }; | 1490 | }; |
1461 | 1491 | ||
@@ -1466,6 +1496,7 @@ static struct clk core_48m_fck = { | |||
1466 | .parent = &omap_48m_fck, | 1496 | .parent = &omap_48m_fck, |
1467 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 1497 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
1468 | PARENT_CONTROLS_CLOCK, | 1498 | PARENT_CONTROLS_CLOCK, |
1499 | .clkdm_name = "core_l4_clkdm", | ||
1469 | .recalc = &followparent_recalc, | 1500 | .recalc = &followparent_recalc, |
1470 | }; | 1501 | }; |
1471 | 1502 | ||
@@ -1543,6 +1574,7 @@ static struct clk core_12m_fck = { | |||
1543 | .parent = &omap_12m_fck, | 1574 | .parent = &omap_12m_fck, |
1544 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 1575 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
1545 | PARENT_CONTROLS_CLOCK, | 1576 | PARENT_CONTROLS_CLOCK, |
1577 | .clkdm_name = "core_l4_clkdm", | ||
1546 | .recalc = &followparent_recalc, | 1578 | .recalc = &followparent_recalc, |
1547 | }; | 1579 | }; |
1548 | 1580 | ||
@@ -1581,6 +1613,7 @@ static struct clk ssi_ssr_fck = { | |||
1581 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, | 1613 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, |
1582 | .clksel = ssi_ssr_clksel, | 1614 | .clksel = ssi_ssr_clksel, |
1583 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | 1615 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
1616 | .clkdm_name = "core_l4_clkdm", | ||
1584 | .recalc = &omap2_clksel_recalc, | 1617 | .recalc = &omap2_clksel_recalc, |
1585 | }; | 1618 | }; |
1586 | 1619 | ||
@@ -1596,11 +1629,17 @@ static struct clk ssi_sst_fck = { | |||
1596 | 1629 | ||
1597 | /* CORE_L3_ICK based clocks */ | 1630 | /* CORE_L3_ICK based clocks */ |
1598 | 1631 | ||
1632 | /* | ||
1633 | * XXX must add clk_enable/clk_disable for these if standard code won't | ||
1634 | * handle it | ||
1635 | */ | ||
1599 | static struct clk core_l3_ick = { | 1636 | static struct clk core_l3_ick = { |
1600 | .name = "core_l3_ick", | 1637 | .name = "core_l3_ick", |
1601 | .parent = &l3_ick, | 1638 | .parent = &l3_ick, |
1639 | .init = &omap2_init_clk_clkdm, | ||
1602 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 1640 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
1603 | PARENT_CONTROLS_CLOCK, | 1641 | PARENT_CONTROLS_CLOCK, |
1642 | .clkdm_name = "core_l3_clkdm", | ||
1604 | .recalc = &followparent_recalc, | 1643 | .recalc = &followparent_recalc, |
1605 | }; | 1644 | }; |
1606 | 1645 | ||
@@ -1610,6 +1649,7 @@ static struct clk hsotgusb_ick = { | |||
1610 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1649 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1611 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | 1650 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
1612 | .flags = CLOCK_IN_OMAP343X, | 1651 | .flags = CLOCK_IN_OMAP343X, |
1652 | .clkdm_name = "core_l3_clkdm", | ||
1613 | .recalc = &followparent_recalc, | 1653 | .recalc = &followparent_recalc, |
1614 | }; | 1654 | }; |
1615 | 1655 | ||
@@ -1619,6 +1659,7 @@ static struct clk sdrc_ick = { | |||
1619 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1659 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1620 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, | 1660 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, |
1621 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, | 1661 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, |
1662 | .clkdm_name = "core_l3_clkdm", | ||
1622 | .recalc = &followparent_recalc, | 1663 | .recalc = &followparent_recalc, |
1623 | }; | 1664 | }; |
1624 | 1665 | ||
@@ -1627,6 +1668,7 @@ static struct clk gpmc_fck = { | |||
1627 | .parent = &core_l3_ick, | 1668 | .parent = &core_l3_ick, |
1628 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | | 1669 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | |
1629 | ENABLE_ON_INIT, | 1670 | ENABLE_ON_INIT, |
1671 | .clkdm_name = "core_l3_clkdm", | ||
1630 | .recalc = &followparent_recalc, | 1672 | .recalc = &followparent_recalc, |
1631 | }; | 1673 | }; |
1632 | 1674 | ||
@@ -1654,8 +1696,10 @@ static struct clk pka_ick = { | |||
1654 | static struct clk core_l4_ick = { | 1696 | static struct clk core_l4_ick = { |
1655 | .name = "core_l4_ick", | 1697 | .name = "core_l4_ick", |
1656 | .parent = &l4_ick, | 1698 | .parent = &l4_ick, |
1699 | .init = &omap2_init_clk_clkdm, | ||
1657 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 1700 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
1658 | PARENT_CONTROLS_CLOCK, | 1701 | PARENT_CONTROLS_CLOCK, |
1702 | .clkdm_name = "core_l4_clkdm", | ||
1659 | .recalc = &followparent_recalc, | 1703 | .recalc = &followparent_recalc, |
1660 | }; | 1704 | }; |
1661 | 1705 | ||
@@ -1665,6 +1709,7 @@ static struct clk usbtll_ick = { | |||
1665 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | 1709 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
1666 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | 1710 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
1667 | .flags = CLOCK_IN_OMAP3430ES2, | 1711 | .flags = CLOCK_IN_OMAP3430ES2, |
1712 | .clkdm_name = "core_l4_clkdm", | ||
1668 | .recalc = &followparent_recalc, | 1713 | .recalc = &followparent_recalc, |
1669 | }; | 1714 | }; |
1670 | 1715 | ||
@@ -1675,6 +1720,7 @@ static struct clk mmchs3_ick = { | |||
1675 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1720 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1676 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | 1721 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
1677 | .flags = CLOCK_IN_OMAP3430ES2, | 1722 | .flags = CLOCK_IN_OMAP3430ES2, |
1723 | .clkdm_name = "core_l4_clkdm", | ||
1678 | .recalc = &followparent_recalc, | 1724 | .recalc = &followparent_recalc, |
1679 | }; | 1725 | }; |
1680 | 1726 | ||
@@ -1685,6 +1731,7 @@ static struct clk icr_ick = { | |||
1685 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1731 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1686 | .enable_bit = OMAP3430_EN_ICR_SHIFT, | 1732 | .enable_bit = OMAP3430_EN_ICR_SHIFT, |
1687 | .flags = CLOCK_IN_OMAP343X, | 1733 | .flags = CLOCK_IN_OMAP343X, |
1734 | .clkdm_name = "core_l4_clkdm", | ||
1688 | .recalc = &followparent_recalc, | 1735 | .recalc = &followparent_recalc, |
1689 | }; | 1736 | }; |
1690 | 1737 | ||
@@ -1694,6 +1741,7 @@ static struct clk aes2_ick = { | |||
1694 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1741 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1695 | .enable_bit = OMAP3430_EN_AES2_SHIFT, | 1742 | .enable_bit = OMAP3430_EN_AES2_SHIFT, |
1696 | .flags = CLOCK_IN_OMAP343X, | 1743 | .flags = CLOCK_IN_OMAP343X, |
1744 | .clkdm_name = "core_l4_clkdm", | ||
1697 | .recalc = &followparent_recalc, | 1745 | .recalc = &followparent_recalc, |
1698 | }; | 1746 | }; |
1699 | 1747 | ||
@@ -1703,6 +1751,7 @@ static struct clk sha12_ick = { | |||
1703 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1751 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1704 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, | 1752 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, |
1705 | .flags = CLOCK_IN_OMAP343X, | 1753 | .flags = CLOCK_IN_OMAP343X, |
1754 | .clkdm_name = "core_l4_clkdm", | ||
1706 | .recalc = &followparent_recalc, | 1755 | .recalc = &followparent_recalc, |
1707 | }; | 1756 | }; |
1708 | 1757 | ||
@@ -1712,6 +1761,7 @@ static struct clk des2_ick = { | |||
1712 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1761 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1713 | .enable_bit = OMAP3430_EN_DES2_SHIFT, | 1762 | .enable_bit = OMAP3430_EN_DES2_SHIFT, |
1714 | .flags = CLOCK_IN_OMAP343X, | 1763 | .flags = CLOCK_IN_OMAP343X, |
1764 | .clkdm_name = "core_l4_clkdm", | ||
1715 | .recalc = &followparent_recalc, | 1765 | .recalc = &followparent_recalc, |
1716 | }; | 1766 | }; |
1717 | 1767 | ||
@@ -1722,6 +1772,7 @@ static struct clk mmchs2_ick = { | |||
1722 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1772 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1723 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | 1773 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
1724 | .flags = CLOCK_IN_OMAP343X, | 1774 | .flags = CLOCK_IN_OMAP343X, |
1775 | .clkdm_name = "core_l4_clkdm", | ||
1725 | .recalc = &followparent_recalc, | 1776 | .recalc = &followparent_recalc, |
1726 | }; | 1777 | }; |
1727 | 1778 | ||
@@ -1732,6 +1783,7 @@ static struct clk mmchs1_ick = { | |||
1732 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1783 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1733 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | 1784 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, |
1734 | .flags = CLOCK_IN_OMAP343X, | 1785 | .flags = CLOCK_IN_OMAP343X, |
1786 | .clkdm_name = "core_l4_clkdm", | ||
1735 | .recalc = &followparent_recalc, | 1787 | .recalc = &followparent_recalc, |
1736 | }; | 1788 | }; |
1737 | 1789 | ||
@@ -1741,6 +1793,7 @@ static struct clk mspro_ick = { | |||
1741 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1793 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1742 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | 1794 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, |
1743 | .flags = CLOCK_IN_OMAP343X, | 1795 | .flags = CLOCK_IN_OMAP343X, |
1796 | .clkdm_name = "core_l4_clkdm", | ||
1744 | .recalc = &followparent_recalc, | 1797 | .recalc = &followparent_recalc, |
1745 | }; | 1798 | }; |
1746 | 1799 | ||
@@ -1750,6 +1803,7 @@ static struct clk hdq_ick = { | |||
1750 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1803 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1751 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | 1804 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, |
1752 | .flags = CLOCK_IN_OMAP343X, | 1805 | .flags = CLOCK_IN_OMAP343X, |
1806 | .clkdm_name = "core_l4_clkdm", | ||
1753 | .recalc = &followparent_recalc, | 1807 | .recalc = &followparent_recalc, |
1754 | }; | 1808 | }; |
1755 | 1809 | ||
@@ -1760,6 +1814,7 @@ static struct clk mcspi4_ick = { | |||
1760 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1814 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1761 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | 1815 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
1762 | .flags = CLOCK_IN_OMAP343X, | 1816 | .flags = CLOCK_IN_OMAP343X, |
1817 | .clkdm_name = "core_l4_clkdm", | ||
1763 | .recalc = &followparent_recalc, | 1818 | .recalc = &followparent_recalc, |
1764 | }; | 1819 | }; |
1765 | 1820 | ||
@@ -1770,6 +1825,7 @@ static struct clk mcspi3_ick = { | |||
1770 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1825 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1771 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | 1826 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
1772 | .flags = CLOCK_IN_OMAP343X, | 1827 | .flags = CLOCK_IN_OMAP343X, |
1828 | .clkdm_name = "core_l4_clkdm", | ||
1773 | .recalc = &followparent_recalc, | 1829 | .recalc = &followparent_recalc, |
1774 | }; | 1830 | }; |
1775 | 1831 | ||
@@ -1780,6 +1836,7 @@ static struct clk mcspi2_ick = { | |||
1780 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1836 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1781 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | 1837 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
1782 | .flags = CLOCK_IN_OMAP343X, | 1838 | .flags = CLOCK_IN_OMAP343X, |
1839 | .clkdm_name = "core_l4_clkdm", | ||
1783 | .recalc = &followparent_recalc, | 1840 | .recalc = &followparent_recalc, |
1784 | }; | 1841 | }; |
1785 | 1842 | ||
@@ -1790,6 +1847,7 @@ static struct clk mcspi1_ick = { | |||
1790 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1847 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1791 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | 1848 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
1792 | .flags = CLOCK_IN_OMAP343X, | 1849 | .flags = CLOCK_IN_OMAP343X, |
1850 | .clkdm_name = "core_l4_clkdm", | ||
1793 | .recalc = &followparent_recalc, | 1851 | .recalc = &followparent_recalc, |
1794 | }; | 1852 | }; |
1795 | 1853 | ||
@@ -1800,6 +1858,7 @@ static struct clk i2c3_ick = { | |||
1800 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1858 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1801 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | 1859 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
1802 | .flags = CLOCK_IN_OMAP343X, | 1860 | .flags = CLOCK_IN_OMAP343X, |
1861 | .clkdm_name = "core_l4_clkdm", | ||
1803 | .recalc = &followparent_recalc, | 1862 | .recalc = &followparent_recalc, |
1804 | }; | 1863 | }; |
1805 | 1864 | ||
@@ -1810,6 +1869,7 @@ static struct clk i2c2_ick = { | |||
1810 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1869 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1811 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | 1870 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
1812 | .flags = CLOCK_IN_OMAP343X, | 1871 | .flags = CLOCK_IN_OMAP343X, |
1872 | .clkdm_name = "core_l4_clkdm", | ||
1813 | .recalc = &followparent_recalc, | 1873 | .recalc = &followparent_recalc, |
1814 | }; | 1874 | }; |
1815 | 1875 | ||
@@ -1820,6 +1880,7 @@ static struct clk i2c1_ick = { | |||
1820 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1880 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1821 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | 1881 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
1822 | .flags = CLOCK_IN_OMAP343X, | 1882 | .flags = CLOCK_IN_OMAP343X, |
1883 | .clkdm_name = "core_l4_clkdm", | ||
1823 | .recalc = &followparent_recalc, | 1884 | .recalc = &followparent_recalc, |
1824 | }; | 1885 | }; |
1825 | 1886 | ||
@@ -1829,6 +1890,7 @@ static struct clk uart2_ick = { | |||
1829 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1890 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1830 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | 1891 | .enable_bit = OMAP3430_EN_UART2_SHIFT, |
1831 | .flags = CLOCK_IN_OMAP343X, | 1892 | .flags = CLOCK_IN_OMAP343X, |
1893 | .clkdm_name = "core_l4_clkdm", | ||
1832 | .recalc = &followparent_recalc, | 1894 | .recalc = &followparent_recalc, |
1833 | }; | 1895 | }; |
1834 | 1896 | ||
@@ -1838,6 +1900,7 @@ static struct clk uart1_ick = { | |||
1838 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1900 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1839 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | 1901 | .enable_bit = OMAP3430_EN_UART1_SHIFT, |
1840 | .flags = CLOCK_IN_OMAP343X, | 1902 | .flags = CLOCK_IN_OMAP343X, |
1903 | .clkdm_name = "core_l4_clkdm", | ||
1841 | .recalc = &followparent_recalc, | 1904 | .recalc = &followparent_recalc, |
1842 | }; | 1905 | }; |
1843 | 1906 | ||
@@ -1847,6 +1910,7 @@ static struct clk gpt11_ick = { | |||
1847 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1910 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1848 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | 1911 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, |
1849 | .flags = CLOCK_IN_OMAP343X, | 1912 | .flags = CLOCK_IN_OMAP343X, |
1913 | .clkdm_name = "core_l4_clkdm", | ||
1850 | .recalc = &followparent_recalc, | 1914 | .recalc = &followparent_recalc, |
1851 | }; | 1915 | }; |
1852 | 1916 | ||
@@ -1856,6 +1920,7 @@ static struct clk gpt10_ick = { | |||
1856 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1920 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1857 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | 1921 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, |
1858 | .flags = CLOCK_IN_OMAP343X, | 1922 | .flags = CLOCK_IN_OMAP343X, |
1923 | .clkdm_name = "core_l4_clkdm", | ||
1859 | .recalc = &followparent_recalc, | 1924 | .recalc = &followparent_recalc, |
1860 | }; | 1925 | }; |
1861 | 1926 | ||
@@ -1866,6 +1931,7 @@ static struct clk mcbsp5_ick = { | |||
1866 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1931 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1867 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | 1932 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
1868 | .flags = CLOCK_IN_OMAP343X, | 1933 | .flags = CLOCK_IN_OMAP343X, |
1934 | .clkdm_name = "core_l4_clkdm", | ||
1869 | .recalc = &followparent_recalc, | 1935 | .recalc = &followparent_recalc, |
1870 | }; | 1936 | }; |
1871 | 1937 | ||
@@ -1876,6 +1942,7 @@ static struct clk mcbsp1_ick = { | |||
1876 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1942 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1877 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | 1943 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
1878 | .flags = CLOCK_IN_OMAP343X, | 1944 | .flags = CLOCK_IN_OMAP343X, |
1945 | .clkdm_name = "core_l4_clkdm", | ||
1879 | .recalc = &followparent_recalc, | 1946 | .recalc = &followparent_recalc, |
1880 | }; | 1947 | }; |
1881 | 1948 | ||
@@ -1885,6 +1952,7 @@ static struct clk fac_ick = { | |||
1885 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1952 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1886 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, | 1953 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, |
1887 | .flags = CLOCK_IN_OMAP3430ES1, | 1954 | .flags = CLOCK_IN_OMAP3430ES1, |
1955 | .clkdm_name = "core_l4_clkdm", | ||
1888 | .recalc = &followparent_recalc, | 1956 | .recalc = &followparent_recalc, |
1889 | }; | 1957 | }; |
1890 | 1958 | ||
@@ -1894,6 +1962,7 @@ static struct clk mailboxes_ick = { | |||
1894 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1962 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1895 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, | 1963 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
1896 | .flags = CLOCK_IN_OMAP343X, | 1964 | .flags = CLOCK_IN_OMAP343X, |
1965 | .clkdm_name = "core_l4_clkdm", | ||
1897 | .recalc = &followparent_recalc, | 1966 | .recalc = &followparent_recalc, |
1898 | }; | 1967 | }; |
1899 | 1968 | ||
@@ -1913,6 +1982,7 @@ static struct clk ssi_l4_ick = { | |||
1913 | .parent = &l4_ick, | 1982 | .parent = &l4_ick, |
1914 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 1983 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
1915 | PARENT_CONTROLS_CLOCK, | 1984 | PARENT_CONTROLS_CLOCK, |
1985 | .clkdm_name = "core_l4_clkdm", | ||
1916 | .recalc = &followparent_recalc, | 1986 | .recalc = &followparent_recalc, |
1917 | }; | 1987 | }; |
1918 | 1988 | ||
@@ -1922,6 +1992,7 @@ static struct clk ssi_ick = { | |||
1922 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1992 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1923 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | 1993 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
1924 | .flags = CLOCK_IN_OMAP343X, | 1994 | .flags = CLOCK_IN_OMAP343X, |
1995 | .clkdm_name = "core_l4_clkdm", | ||
1925 | .recalc = &followparent_recalc, | 1996 | .recalc = &followparent_recalc, |
1926 | }; | 1997 | }; |
1927 | 1998 | ||
@@ -1996,7 +2067,7 @@ static struct clk des1_ick = { | |||
1996 | 2067 | ||
1997 | /* DSS */ | 2068 | /* DSS */ |
1998 | static const struct clksel dss1_alwon_fck_clksel[] = { | 2069 | static const struct clksel dss1_alwon_fck_clksel[] = { |
1999 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | 2070 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
2000 | { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, | 2071 | { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, |
2001 | { .parent = NULL } | 2072 | { .parent = NULL } |
2002 | }; | 2073 | }; |
@@ -2011,33 +2082,40 @@ static struct clk dss1_alwon_fck = { | |||
2011 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, | 2082 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
2012 | .clksel = dss1_alwon_fck_clksel, | 2083 | .clksel = dss1_alwon_fck_clksel, |
2013 | .flags = CLOCK_IN_OMAP343X, | 2084 | .flags = CLOCK_IN_OMAP343X, |
2085 | .clkdm_name = "dss_clkdm", | ||
2014 | .recalc = &omap2_clksel_recalc, | 2086 | .recalc = &omap2_clksel_recalc, |
2015 | }; | 2087 | }; |
2016 | 2088 | ||
2017 | static struct clk dss_tv_fck = { | 2089 | static struct clk dss_tv_fck = { |
2018 | .name = "dss_tv_fck", | 2090 | .name = "dss_tv_fck", |
2019 | .parent = &omap_54m_fck, | 2091 | .parent = &omap_54m_fck, |
2092 | .init = &omap2_init_clk_clkdm, | ||
2020 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2093 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
2021 | .enable_bit = OMAP3430_EN_TV_SHIFT, | 2094 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
2022 | .flags = CLOCK_IN_OMAP343X, | 2095 | .flags = CLOCK_IN_OMAP343X, |
2096 | .clkdm_name = "dss_clkdm", | ||
2023 | .recalc = &followparent_recalc, | 2097 | .recalc = &followparent_recalc, |
2024 | }; | 2098 | }; |
2025 | 2099 | ||
2026 | static struct clk dss_96m_fck = { | 2100 | static struct clk dss_96m_fck = { |
2027 | .name = "dss_96m_fck", | 2101 | .name = "dss_96m_fck", |
2028 | .parent = &omap_96m_fck, | 2102 | .parent = &omap_96m_fck, |
2103 | .init = &omap2_init_clk_clkdm, | ||
2029 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2104 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
2030 | .enable_bit = OMAP3430_EN_TV_SHIFT, | 2105 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
2031 | .flags = CLOCK_IN_OMAP343X, | 2106 | .flags = CLOCK_IN_OMAP343X, |
2107 | .clkdm_name = "dss_clkdm", | ||
2032 | .recalc = &followparent_recalc, | 2108 | .recalc = &followparent_recalc, |
2033 | }; | 2109 | }; |
2034 | 2110 | ||
2035 | static struct clk dss2_alwon_fck = { | 2111 | static struct clk dss2_alwon_fck = { |
2036 | .name = "dss2_alwon_fck", | 2112 | .name = "dss2_alwon_fck", |
2037 | .parent = &sys_ck, | 2113 | .parent = &sys_ck, |
2114 | .init = &omap2_init_clk_clkdm, | ||
2038 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2115 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
2039 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, | 2116 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, |
2040 | .flags = CLOCK_IN_OMAP343X, | 2117 | .flags = CLOCK_IN_OMAP343X, |
2118 | .clkdm_name = "dss_clkdm", | ||
2041 | .recalc = &followparent_recalc, | 2119 | .recalc = &followparent_recalc, |
2042 | }; | 2120 | }; |
2043 | 2121 | ||
@@ -2045,16 +2123,18 @@ static struct clk dss_ick = { | |||
2045 | /* Handles both L3 and L4 clocks */ | 2123 | /* Handles both L3 and L4 clocks */ |
2046 | .name = "dss_ick", | 2124 | .name = "dss_ick", |
2047 | .parent = &l4_ick, | 2125 | .parent = &l4_ick, |
2126 | .init = &omap2_init_clk_clkdm, | ||
2048 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | 2127 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), |
2049 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | 2128 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, |
2050 | .flags = CLOCK_IN_OMAP343X, | 2129 | .flags = CLOCK_IN_OMAP343X, |
2130 | .clkdm_name = "dss_clkdm", | ||
2051 | .recalc = &followparent_recalc, | 2131 | .recalc = &followparent_recalc, |
2052 | }; | 2132 | }; |
2053 | 2133 | ||
2054 | /* CAM */ | 2134 | /* CAM */ |
2055 | 2135 | ||
2056 | static const struct clksel cam_mclk_clksel[] = { | 2136 | static const struct clksel cam_mclk_clksel[] = { |
2057 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | 2137 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
2058 | { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, | 2138 | { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, |
2059 | { .parent = NULL } | 2139 | { .parent = NULL } |
2060 | }; | 2140 | }; |
@@ -2069,24 +2149,29 @@ static struct clk cam_mclk = { | |||
2069 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | 2149 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), |
2070 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | 2150 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
2071 | .flags = CLOCK_IN_OMAP343X, | 2151 | .flags = CLOCK_IN_OMAP343X, |
2152 | .clkdm_name = "cam_clkdm", | ||
2072 | .recalc = &omap2_clksel_recalc, | 2153 | .recalc = &omap2_clksel_recalc, |
2073 | }; | 2154 | }; |
2074 | 2155 | ||
2075 | static struct clk cam_l3_ick = { | 2156 | static struct clk cam_l3_ick = { |
2076 | .name = "cam_l3_ick", | 2157 | .name = "cam_l3_ick", |
2077 | .parent = &l3_ick, | 2158 | .parent = &l3_ick, |
2159 | .init = &omap2_init_clk_clkdm, | ||
2078 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), | 2160 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), |
2079 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | 2161 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
2080 | .flags = CLOCK_IN_OMAP343X, | 2162 | .flags = CLOCK_IN_OMAP343X, |
2163 | .clkdm_name = "cam_clkdm", | ||
2081 | .recalc = &followparent_recalc, | 2164 | .recalc = &followparent_recalc, |
2082 | }; | 2165 | }; |
2083 | 2166 | ||
2084 | static struct clk cam_l4_ick = { | 2167 | static struct clk cam_l4_ick = { |
2085 | .name = "cam_l4_ick", | 2168 | .name = "cam_l4_ick", |
2086 | .parent = &l4_ick, | 2169 | .parent = &l4_ick, |
2170 | .init = &omap2_init_clk_clkdm, | ||
2087 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), | 2171 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), |
2088 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | 2172 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
2089 | .flags = CLOCK_IN_OMAP343X, | 2173 | .flags = CLOCK_IN_OMAP343X, |
2174 | .clkdm_name = "cam_clkdm", | ||
2090 | .recalc = &followparent_recalc, | 2175 | .recalc = &followparent_recalc, |
2091 | }; | 2176 | }; |
2092 | 2177 | ||
@@ -2095,45 +2180,55 @@ static struct clk cam_l4_ick = { | |||
2095 | static struct clk usbhost_120m_fck = { | 2180 | static struct clk usbhost_120m_fck = { |
2096 | .name = "usbhost_120m_fck", | 2181 | .name = "usbhost_120m_fck", |
2097 | .parent = &omap_120m_fck, | 2182 | .parent = &omap_120m_fck, |
2183 | .init = &omap2_init_clk_clkdm, | ||
2098 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | 2184 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
2099 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, | 2185 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, |
2100 | .flags = CLOCK_IN_OMAP3430ES2, | 2186 | .flags = CLOCK_IN_OMAP3430ES2, |
2187 | .clkdm_name = "usbhost_clkdm", | ||
2101 | .recalc = &followparent_recalc, | 2188 | .recalc = &followparent_recalc, |
2102 | }; | 2189 | }; |
2103 | 2190 | ||
2104 | static struct clk usbhost_48m_fck = { | 2191 | static struct clk usbhost_48m_fck = { |
2105 | .name = "usbhost_48m_fck", | 2192 | .name = "usbhost_48m_fck", |
2106 | .parent = &omap_48m_fck, | 2193 | .parent = &omap_48m_fck, |
2194 | .init = &omap2_init_clk_clkdm, | ||
2107 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | 2195 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
2108 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, | 2196 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
2109 | .flags = CLOCK_IN_OMAP3430ES2, | 2197 | .flags = CLOCK_IN_OMAP3430ES2, |
2198 | .clkdm_name = "usbhost_clkdm", | ||
2110 | .recalc = &followparent_recalc, | 2199 | .recalc = &followparent_recalc, |
2111 | }; | 2200 | }; |
2112 | 2201 | ||
2113 | static struct clk usbhost_l3_ick = { | 2202 | static struct clk usbhost_l3_ick = { |
2114 | .name = "usbhost_l3_ick", | 2203 | .name = "usbhost_l3_ick", |
2115 | .parent = &l3_ick, | 2204 | .parent = &l3_ick, |
2205 | .init = &omap2_init_clk_clkdm, | ||
2116 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), | 2206 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), |
2117 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | 2207 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, |
2118 | .flags = CLOCK_IN_OMAP3430ES2, | 2208 | .flags = CLOCK_IN_OMAP3430ES2, |
2209 | .clkdm_name = "usbhost_clkdm", | ||
2119 | .recalc = &followparent_recalc, | 2210 | .recalc = &followparent_recalc, |
2120 | }; | 2211 | }; |
2121 | 2212 | ||
2122 | static struct clk usbhost_l4_ick = { | 2213 | static struct clk usbhost_l4_ick = { |
2123 | .name = "usbhost_l4_ick", | 2214 | .name = "usbhost_l4_ick", |
2124 | .parent = &l4_ick, | 2215 | .parent = &l4_ick, |
2216 | .init = &omap2_init_clk_clkdm, | ||
2125 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), | 2217 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), |
2126 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | 2218 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, |
2127 | .flags = CLOCK_IN_OMAP3430ES2, | 2219 | .flags = CLOCK_IN_OMAP3430ES2, |
2220 | .clkdm_name = "usbhost_clkdm", | ||
2128 | .recalc = &followparent_recalc, | 2221 | .recalc = &followparent_recalc, |
2129 | }; | 2222 | }; |
2130 | 2223 | ||
2131 | static struct clk usbhost_sar_fck = { | 2224 | static struct clk usbhost_sar_fck = { |
2132 | .name = "usbhost_sar_fck", | 2225 | .name = "usbhost_sar_fck", |
2133 | .parent = &osc_sys_ck, | 2226 | .parent = &osc_sys_ck, |
2227 | .init = &omap2_init_clk_clkdm, | ||
2134 | .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), | 2228 | .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), |
2135 | .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, | 2229 | .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, |
2136 | .flags = CLOCK_IN_OMAP3430ES2, | 2230 | .flags = CLOCK_IN_OMAP3430ES2, |
2231 | .clkdm_name = "usbhost_clkdm", | ||
2137 | .recalc = &followparent_recalc, | 2232 | .recalc = &followparent_recalc, |
2138 | }; | 2233 | }; |
2139 | 2234 | ||
@@ -2175,6 +2270,7 @@ static struct clk usim_fck = { | |||
2175 | .recalc = &omap2_clksel_recalc, | 2270 | .recalc = &omap2_clksel_recalc, |
2176 | }; | 2271 | }; |
2177 | 2272 | ||
2273 | /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ | ||
2178 | static struct clk gpt1_fck = { | 2274 | static struct clk gpt1_fck = { |
2179 | .name = "gpt1_fck", | 2275 | .name = "gpt1_fck", |
2180 | .init = &omap2_init_clksel_parent, | 2276 | .init = &omap2_init_clksel_parent, |
@@ -2184,13 +2280,16 @@ static struct clk gpt1_fck = { | |||
2184 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, | 2280 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, |
2185 | .clksel = omap343x_gpt_clksel, | 2281 | .clksel = omap343x_gpt_clksel, |
2186 | .flags = CLOCK_IN_OMAP343X, | 2282 | .flags = CLOCK_IN_OMAP343X, |
2283 | .clkdm_name = "wkup_clkdm", | ||
2187 | .recalc = &omap2_clksel_recalc, | 2284 | .recalc = &omap2_clksel_recalc, |
2188 | }; | 2285 | }; |
2189 | 2286 | ||
2190 | static struct clk wkup_32k_fck = { | 2287 | static struct clk wkup_32k_fck = { |
2191 | .name = "wkup_32k_fck", | 2288 | .name = "wkup_32k_fck", |
2289 | .init = &omap2_init_clk_clkdm, | ||
2192 | .parent = &omap_32k_fck, | 2290 | .parent = &omap_32k_fck, |
2193 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 2291 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, |
2292 | .clkdm_name = "wkup_clkdm", | ||
2194 | .recalc = &followparent_recalc, | 2293 | .recalc = &followparent_recalc, |
2195 | }; | 2294 | }; |
2196 | 2295 | ||
@@ -2200,6 +2299,7 @@ static struct clk gpio1_fck = { | |||
2200 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2299 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
2201 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | 2300 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, |
2202 | .flags = CLOCK_IN_OMAP343X, | 2301 | .flags = CLOCK_IN_OMAP343X, |
2302 | .clkdm_name = "wkup_clkdm", | ||
2203 | .recalc = &followparent_recalc, | 2303 | .recalc = &followparent_recalc, |
2204 | }; | 2304 | }; |
2205 | 2305 | ||
@@ -2209,6 +2309,7 @@ static struct clk wdt2_fck = { | |||
2209 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2309 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
2210 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | 2310 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, |
2211 | .flags = CLOCK_IN_OMAP343X, | 2311 | .flags = CLOCK_IN_OMAP343X, |
2312 | .clkdm_name = "wkup_clkdm", | ||
2212 | .recalc = &followparent_recalc, | 2313 | .recalc = &followparent_recalc, |
2213 | }; | 2314 | }; |
2214 | 2315 | ||
@@ -2216,6 +2317,7 @@ static struct clk wkup_l4_ick = { | |||
2216 | .name = "wkup_l4_ick", | 2317 | .name = "wkup_l4_ick", |
2217 | .parent = &sys_ck, | 2318 | .parent = &sys_ck, |
2218 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 2319 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, |
2320 | .clkdm_name = "wkup_clkdm", | ||
2219 | .recalc = &followparent_recalc, | 2321 | .recalc = &followparent_recalc, |
2220 | }; | 2322 | }; |
2221 | 2323 | ||
@@ -2227,6 +2329,7 @@ static struct clk usim_ick = { | |||
2227 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2329 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2228 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | 2330 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, |
2229 | .flags = CLOCK_IN_OMAP3430ES2, | 2331 | .flags = CLOCK_IN_OMAP3430ES2, |
2332 | .clkdm_name = "wkup_clkdm", | ||
2230 | .recalc = &followparent_recalc, | 2333 | .recalc = &followparent_recalc, |
2231 | }; | 2334 | }; |
2232 | 2335 | ||
@@ -2236,6 +2339,7 @@ static struct clk wdt2_ick = { | |||
2236 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2339 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2237 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | 2340 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, |
2238 | .flags = CLOCK_IN_OMAP343X, | 2341 | .flags = CLOCK_IN_OMAP343X, |
2342 | .clkdm_name = "wkup_clkdm", | ||
2239 | .recalc = &followparent_recalc, | 2343 | .recalc = &followparent_recalc, |
2240 | }; | 2344 | }; |
2241 | 2345 | ||
@@ -2245,6 +2349,7 @@ static struct clk wdt1_ick = { | |||
2245 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2349 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2246 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, | 2350 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, |
2247 | .flags = CLOCK_IN_OMAP343X, | 2351 | .flags = CLOCK_IN_OMAP343X, |
2352 | .clkdm_name = "wkup_clkdm", | ||
2248 | .recalc = &followparent_recalc, | 2353 | .recalc = &followparent_recalc, |
2249 | }; | 2354 | }; |
2250 | 2355 | ||
@@ -2254,6 +2359,7 @@ static struct clk gpio1_ick = { | |||
2254 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2359 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2255 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | 2360 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, |
2256 | .flags = CLOCK_IN_OMAP343X, | 2361 | .flags = CLOCK_IN_OMAP343X, |
2362 | .clkdm_name = "wkup_clkdm", | ||
2257 | .recalc = &followparent_recalc, | 2363 | .recalc = &followparent_recalc, |
2258 | }; | 2364 | }; |
2259 | 2365 | ||
@@ -2263,15 +2369,18 @@ static struct clk omap_32ksync_ick = { | |||
2263 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2369 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2264 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, | 2370 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, |
2265 | .flags = CLOCK_IN_OMAP343X, | 2371 | .flags = CLOCK_IN_OMAP343X, |
2372 | .clkdm_name = "wkup_clkdm", | ||
2266 | .recalc = &followparent_recalc, | 2373 | .recalc = &followparent_recalc, |
2267 | }; | 2374 | }; |
2268 | 2375 | ||
2376 | /* XXX This clock no longer exists in 3430 TRM rev F */ | ||
2269 | static struct clk gpt12_ick = { | 2377 | static struct clk gpt12_ick = { |
2270 | .name = "gpt12_ick", | 2378 | .name = "gpt12_ick", |
2271 | .parent = &wkup_l4_ick, | 2379 | .parent = &wkup_l4_ick, |
2272 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2380 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2273 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, | 2381 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, |
2274 | .flags = CLOCK_IN_OMAP343X, | 2382 | .flags = CLOCK_IN_OMAP343X, |
2383 | .clkdm_name = "wkup_clkdm", | ||
2275 | .recalc = &followparent_recalc, | 2384 | .recalc = &followparent_recalc, |
2276 | }; | 2385 | }; |
2277 | 2386 | ||
@@ -2281,6 +2390,7 @@ static struct clk gpt1_ick = { | |||
2281 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2390 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2282 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | 2391 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, |
2283 | .flags = CLOCK_IN_OMAP343X, | 2392 | .flags = CLOCK_IN_OMAP343X, |
2393 | .clkdm_name = "wkup_clkdm", | ||
2284 | .recalc = &followparent_recalc, | 2394 | .recalc = &followparent_recalc, |
2285 | }; | 2395 | }; |
2286 | 2396 | ||
@@ -2291,16 +2401,20 @@ static struct clk gpt1_ick = { | |||
2291 | static struct clk per_96m_fck = { | 2401 | static struct clk per_96m_fck = { |
2292 | .name = "per_96m_fck", | 2402 | .name = "per_96m_fck", |
2293 | .parent = &omap_96m_alwon_fck, | 2403 | .parent = &omap_96m_alwon_fck, |
2404 | .init = &omap2_init_clk_clkdm, | ||
2294 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 2405 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
2295 | PARENT_CONTROLS_CLOCK, | 2406 | PARENT_CONTROLS_CLOCK, |
2407 | .clkdm_name = "per_clkdm", | ||
2296 | .recalc = &followparent_recalc, | 2408 | .recalc = &followparent_recalc, |
2297 | }; | 2409 | }; |
2298 | 2410 | ||
2299 | static struct clk per_48m_fck = { | 2411 | static struct clk per_48m_fck = { |
2300 | .name = "per_48m_fck", | 2412 | .name = "per_48m_fck", |
2301 | .parent = &omap_48m_fck, | 2413 | .parent = &omap_48m_fck, |
2414 | .init = &omap2_init_clk_clkdm, | ||
2302 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 2415 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
2303 | PARENT_CONTROLS_CLOCK, | 2416 | PARENT_CONTROLS_CLOCK, |
2417 | .clkdm_name = "per_clkdm", | ||
2304 | .recalc = &followparent_recalc, | 2418 | .recalc = &followparent_recalc, |
2305 | }; | 2419 | }; |
2306 | 2420 | ||
@@ -2310,6 +2424,7 @@ static struct clk uart3_fck = { | |||
2310 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2424 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2311 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | 2425 | .enable_bit = OMAP3430_EN_UART3_SHIFT, |
2312 | .flags = CLOCK_IN_OMAP343X, | 2426 | .flags = CLOCK_IN_OMAP343X, |
2427 | .clkdm_name = "per_clkdm", | ||
2313 | .recalc = &followparent_recalc, | 2428 | .recalc = &followparent_recalc, |
2314 | }; | 2429 | }; |
2315 | 2430 | ||
@@ -2322,6 +2437,7 @@ static struct clk gpt2_fck = { | |||
2322 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, | 2437 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, |
2323 | .clksel = omap343x_gpt_clksel, | 2438 | .clksel = omap343x_gpt_clksel, |
2324 | .flags = CLOCK_IN_OMAP343X, | 2439 | .flags = CLOCK_IN_OMAP343X, |
2440 | .clkdm_name = "per_clkdm", | ||
2325 | .recalc = &omap2_clksel_recalc, | 2441 | .recalc = &omap2_clksel_recalc, |
2326 | }; | 2442 | }; |
2327 | 2443 | ||
@@ -2334,6 +2450,7 @@ static struct clk gpt3_fck = { | |||
2334 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, | 2450 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, |
2335 | .clksel = omap343x_gpt_clksel, | 2451 | .clksel = omap343x_gpt_clksel, |
2336 | .flags = CLOCK_IN_OMAP343X, | 2452 | .flags = CLOCK_IN_OMAP343X, |
2453 | .clkdm_name = "per_clkdm", | ||
2337 | .recalc = &omap2_clksel_recalc, | 2454 | .recalc = &omap2_clksel_recalc, |
2338 | }; | 2455 | }; |
2339 | 2456 | ||
@@ -2346,6 +2463,7 @@ static struct clk gpt4_fck = { | |||
2346 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, | 2463 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, |
2347 | .clksel = omap343x_gpt_clksel, | 2464 | .clksel = omap343x_gpt_clksel, |
2348 | .flags = CLOCK_IN_OMAP343X, | 2465 | .flags = CLOCK_IN_OMAP343X, |
2466 | .clkdm_name = "per_clkdm", | ||
2349 | .recalc = &omap2_clksel_recalc, | 2467 | .recalc = &omap2_clksel_recalc, |
2350 | }; | 2468 | }; |
2351 | 2469 | ||
@@ -2358,6 +2476,7 @@ static struct clk gpt5_fck = { | |||
2358 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, | 2476 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, |
2359 | .clksel = omap343x_gpt_clksel, | 2477 | .clksel = omap343x_gpt_clksel, |
2360 | .flags = CLOCK_IN_OMAP343X, | 2478 | .flags = CLOCK_IN_OMAP343X, |
2479 | .clkdm_name = "per_clkdm", | ||
2361 | .recalc = &omap2_clksel_recalc, | 2480 | .recalc = &omap2_clksel_recalc, |
2362 | }; | 2481 | }; |
2363 | 2482 | ||
@@ -2370,6 +2489,7 @@ static struct clk gpt6_fck = { | |||
2370 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, | 2489 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, |
2371 | .clksel = omap343x_gpt_clksel, | 2490 | .clksel = omap343x_gpt_clksel, |
2372 | .flags = CLOCK_IN_OMAP343X, | 2491 | .flags = CLOCK_IN_OMAP343X, |
2492 | .clkdm_name = "per_clkdm", | ||
2373 | .recalc = &omap2_clksel_recalc, | 2493 | .recalc = &omap2_clksel_recalc, |
2374 | }; | 2494 | }; |
2375 | 2495 | ||
@@ -2382,6 +2502,7 @@ static struct clk gpt7_fck = { | |||
2382 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, | 2502 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, |
2383 | .clksel = omap343x_gpt_clksel, | 2503 | .clksel = omap343x_gpt_clksel, |
2384 | .flags = CLOCK_IN_OMAP343X, | 2504 | .flags = CLOCK_IN_OMAP343X, |
2505 | .clkdm_name = "per_clkdm", | ||
2385 | .recalc = &omap2_clksel_recalc, | 2506 | .recalc = &omap2_clksel_recalc, |
2386 | }; | 2507 | }; |
2387 | 2508 | ||
@@ -2394,6 +2515,7 @@ static struct clk gpt8_fck = { | |||
2394 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, | 2515 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, |
2395 | .clksel = omap343x_gpt_clksel, | 2516 | .clksel = omap343x_gpt_clksel, |
2396 | .flags = CLOCK_IN_OMAP343X, | 2517 | .flags = CLOCK_IN_OMAP343X, |
2518 | .clkdm_name = "per_clkdm", | ||
2397 | .recalc = &omap2_clksel_recalc, | 2519 | .recalc = &omap2_clksel_recalc, |
2398 | }; | 2520 | }; |
2399 | 2521 | ||
@@ -2406,12 +2528,14 @@ static struct clk gpt9_fck = { | |||
2406 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, | 2528 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, |
2407 | .clksel = omap343x_gpt_clksel, | 2529 | .clksel = omap343x_gpt_clksel, |
2408 | .flags = CLOCK_IN_OMAP343X, | 2530 | .flags = CLOCK_IN_OMAP343X, |
2531 | .clkdm_name = "per_clkdm", | ||
2409 | .recalc = &omap2_clksel_recalc, | 2532 | .recalc = &omap2_clksel_recalc, |
2410 | }; | 2533 | }; |
2411 | 2534 | ||
2412 | static struct clk per_32k_alwon_fck = { | 2535 | static struct clk per_32k_alwon_fck = { |
2413 | .name = "per_32k_alwon_fck", | 2536 | .name = "per_32k_alwon_fck", |
2414 | .parent = &omap_32k_fck, | 2537 | .parent = &omap_32k_fck, |
2538 | .clkdm_name = "per_clkdm", | ||
2415 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 2539 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, |
2416 | .recalc = &followparent_recalc, | 2540 | .recalc = &followparent_recalc, |
2417 | }; | 2541 | }; |
@@ -2422,6 +2546,7 @@ static struct clk gpio6_fck = { | |||
2422 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2546 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2423 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | 2547 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
2424 | .flags = CLOCK_IN_OMAP343X, | 2548 | .flags = CLOCK_IN_OMAP343X, |
2549 | .clkdm_name = "per_clkdm", | ||
2425 | .recalc = &followparent_recalc, | 2550 | .recalc = &followparent_recalc, |
2426 | }; | 2551 | }; |
2427 | 2552 | ||
@@ -2431,6 +2556,7 @@ static struct clk gpio5_fck = { | |||
2431 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2556 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2432 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | 2557 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
2433 | .flags = CLOCK_IN_OMAP343X, | 2558 | .flags = CLOCK_IN_OMAP343X, |
2559 | .clkdm_name = "per_clkdm", | ||
2434 | .recalc = &followparent_recalc, | 2560 | .recalc = &followparent_recalc, |
2435 | }; | 2561 | }; |
2436 | 2562 | ||
@@ -2440,6 +2566,7 @@ static struct clk gpio4_fck = { | |||
2440 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2566 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2441 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | 2567 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
2442 | .flags = CLOCK_IN_OMAP343X, | 2568 | .flags = CLOCK_IN_OMAP343X, |
2569 | .clkdm_name = "per_clkdm", | ||
2443 | .recalc = &followparent_recalc, | 2570 | .recalc = &followparent_recalc, |
2444 | }; | 2571 | }; |
2445 | 2572 | ||
@@ -2449,6 +2576,7 @@ static struct clk gpio3_fck = { | |||
2449 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2576 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2450 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | 2577 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
2451 | .flags = CLOCK_IN_OMAP343X, | 2578 | .flags = CLOCK_IN_OMAP343X, |
2579 | .clkdm_name = "per_clkdm", | ||
2452 | .recalc = &followparent_recalc, | 2580 | .recalc = &followparent_recalc, |
2453 | }; | 2581 | }; |
2454 | 2582 | ||
@@ -2458,6 +2586,7 @@ static struct clk gpio2_fck = { | |||
2458 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2586 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2459 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | 2587 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
2460 | .flags = CLOCK_IN_OMAP343X, | 2588 | .flags = CLOCK_IN_OMAP343X, |
2589 | .clkdm_name = "per_clkdm", | ||
2461 | .recalc = &followparent_recalc, | 2590 | .recalc = &followparent_recalc, |
2462 | }; | 2591 | }; |
2463 | 2592 | ||
@@ -2467,6 +2596,7 @@ static struct clk wdt3_fck = { | |||
2467 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2596 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2468 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | 2597 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, |
2469 | .flags = CLOCK_IN_OMAP343X, | 2598 | .flags = CLOCK_IN_OMAP343X, |
2599 | .clkdm_name = "per_clkdm", | ||
2470 | .recalc = &followparent_recalc, | 2600 | .recalc = &followparent_recalc, |
2471 | }; | 2601 | }; |
2472 | 2602 | ||
@@ -2475,6 +2605,7 @@ static struct clk per_l4_ick = { | |||
2475 | .parent = &l4_ick, | 2605 | .parent = &l4_ick, |
2476 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 2606 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
2477 | PARENT_CONTROLS_CLOCK, | 2607 | PARENT_CONTROLS_CLOCK, |
2608 | .clkdm_name = "per_clkdm", | ||
2478 | .recalc = &followparent_recalc, | 2609 | .recalc = &followparent_recalc, |
2479 | }; | 2610 | }; |
2480 | 2611 | ||
@@ -2484,6 +2615,7 @@ static struct clk gpio6_ick = { | |||
2484 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2615 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2485 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | 2616 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
2486 | .flags = CLOCK_IN_OMAP343X, | 2617 | .flags = CLOCK_IN_OMAP343X, |
2618 | .clkdm_name = "per_clkdm", | ||
2487 | .recalc = &followparent_recalc, | 2619 | .recalc = &followparent_recalc, |
2488 | }; | 2620 | }; |
2489 | 2621 | ||
@@ -2493,6 +2625,7 @@ static struct clk gpio5_ick = { | |||
2493 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2625 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2494 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | 2626 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
2495 | .flags = CLOCK_IN_OMAP343X, | 2627 | .flags = CLOCK_IN_OMAP343X, |
2628 | .clkdm_name = "per_clkdm", | ||
2496 | .recalc = &followparent_recalc, | 2629 | .recalc = &followparent_recalc, |
2497 | }; | 2630 | }; |
2498 | 2631 | ||
@@ -2502,6 +2635,7 @@ static struct clk gpio4_ick = { | |||
2502 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2635 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2503 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | 2636 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
2504 | .flags = CLOCK_IN_OMAP343X, | 2637 | .flags = CLOCK_IN_OMAP343X, |
2638 | .clkdm_name = "per_clkdm", | ||
2505 | .recalc = &followparent_recalc, | 2639 | .recalc = &followparent_recalc, |
2506 | }; | 2640 | }; |
2507 | 2641 | ||
@@ -2511,6 +2645,7 @@ static struct clk gpio3_ick = { | |||
2511 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2645 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2512 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | 2646 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
2513 | .flags = CLOCK_IN_OMAP343X, | 2647 | .flags = CLOCK_IN_OMAP343X, |
2648 | .clkdm_name = "per_clkdm", | ||
2514 | .recalc = &followparent_recalc, | 2649 | .recalc = &followparent_recalc, |
2515 | }; | 2650 | }; |
2516 | 2651 | ||
@@ -2520,6 +2655,7 @@ static struct clk gpio2_ick = { | |||
2520 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2655 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2521 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | 2656 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
2522 | .flags = CLOCK_IN_OMAP343X, | 2657 | .flags = CLOCK_IN_OMAP343X, |
2658 | .clkdm_name = "per_clkdm", | ||
2523 | .recalc = &followparent_recalc, | 2659 | .recalc = &followparent_recalc, |
2524 | }; | 2660 | }; |
2525 | 2661 | ||
@@ -2529,6 +2665,7 @@ static struct clk wdt3_ick = { | |||
2529 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2665 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2530 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | 2666 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, |
2531 | .flags = CLOCK_IN_OMAP343X, | 2667 | .flags = CLOCK_IN_OMAP343X, |
2668 | .clkdm_name = "per_clkdm", | ||
2532 | .recalc = &followparent_recalc, | 2669 | .recalc = &followparent_recalc, |
2533 | }; | 2670 | }; |
2534 | 2671 | ||
@@ -2538,6 +2675,7 @@ static struct clk uart3_ick = { | |||
2538 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2675 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2539 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | 2676 | .enable_bit = OMAP3430_EN_UART3_SHIFT, |
2540 | .flags = CLOCK_IN_OMAP343X, | 2677 | .flags = CLOCK_IN_OMAP343X, |
2678 | .clkdm_name = "per_clkdm", | ||
2541 | .recalc = &followparent_recalc, | 2679 | .recalc = &followparent_recalc, |
2542 | }; | 2680 | }; |
2543 | 2681 | ||
@@ -2547,6 +2685,7 @@ static struct clk gpt9_ick = { | |||
2547 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2685 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2548 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | 2686 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, |
2549 | .flags = CLOCK_IN_OMAP343X, | 2687 | .flags = CLOCK_IN_OMAP343X, |
2688 | .clkdm_name = "per_clkdm", | ||
2550 | .recalc = &followparent_recalc, | 2689 | .recalc = &followparent_recalc, |
2551 | }; | 2690 | }; |
2552 | 2691 | ||
@@ -2556,6 +2695,7 @@ static struct clk gpt8_ick = { | |||
2556 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2695 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2557 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | 2696 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, |
2558 | .flags = CLOCK_IN_OMAP343X, | 2697 | .flags = CLOCK_IN_OMAP343X, |
2698 | .clkdm_name = "per_clkdm", | ||
2559 | .recalc = &followparent_recalc, | 2699 | .recalc = &followparent_recalc, |
2560 | }; | 2700 | }; |
2561 | 2701 | ||
@@ -2565,6 +2705,7 @@ static struct clk gpt7_ick = { | |||
2565 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2705 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2566 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | 2706 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, |
2567 | .flags = CLOCK_IN_OMAP343X, | 2707 | .flags = CLOCK_IN_OMAP343X, |
2708 | .clkdm_name = "per_clkdm", | ||
2568 | .recalc = &followparent_recalc, | 2709 | .recalc = &followparent_recalc, |
2569 | }; | 2710 | }; |
2570 | 2711 | ||
@@ -2574,6 +2715,7 @@ static struct clk gpt6_ick = { | |||
2574 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2715 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2575 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | 2716 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, |
2576 | .flags = CLOCK_IN_OMAP343X, | 2717 | .flags = CLOCK_IN_OMAP343X, |
2718 | .clkdm_name = "per_clkdm", | ||
2577 | .recalc = &followparent_recalc, | 2719 | .recalc = &followparent_recalc, |
2578 | }; | 2720 | }; |
2579 | 2721 | ||
@@ -2583,6 +2725,7 @@ static struct clk gpt5_ick = { | |||
2583 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2725 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2584 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | 2726 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, |
2585 | .flags = CLOCK_IN_OMAP343X, | 2727 | .flags = CLOCK_IN_OMAP343X, |
2728 | .clkdm_name = "per_clkdm", | ||
2586 | .recalc = &followparent_recalc, | 2729 | .recalc = &followparent_recalc, |
2587 | }; | 2730 | }; |
2588 | 2731 | ||
@@ -2592,6 +2735,7 @@ static struct clk gpt4_ick = { | |||
2592 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2735 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2593 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | 2736 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, |
2594 | .flags = CLOCK_IN_OMAP343X, | 2737 | .flags = CLOCK_IN_OMAP343X, |
2738 | .clkdm_name = "per_clkdm", | ||
2595 | .recalc = &followparent_recalc, | 2739 | .recalc = &followparent_recalc, |
2596 | }; | 2740 | }; |
2597 | 2741 | ||
@@ -2601,6 +2745,7 @@ static struct clk gpt3_ick = { | |||
2601 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2745 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2602 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | 2746 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, |
2603 | .flags = CLOCK_IN_OMAP343X, | 2747 | .flags = CLOCK_IN_OMAP343X, |
2748 | .clkdm_name = "per_clkdm", | ||
2604 | .recalc = &followparent_recalc, | 2749 | .recalc = &followparent_recalc, |
2605 | }; | 2750 | }; |
2606 | 2751 | ||
@@ -2610,6 +2755,7 @@ static struct clk gpt2_ick = { | |||
2610 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2755 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2611 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | 2756 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, |
2612 | .flags = CLOCK_IN_OMAP343X, | 2757 | .flags = CLOCK_IN_OMAP343X, |
2758 | .clkdm_name = "per_clkdm", | ||
2613 | .recalc = &followparent_recalc, | 2759 | .recalc = &followparent_recalc, |
2614 | }; | 2760 | }; |
2615 | 2761 | ||
@@ -2620,6 +2766,7 @@ static struct clk mcbsp2_ick = { | |||
2620 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2766 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2621 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | 2767 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
2622 | .flags = CLOCK_IN_OMAP343X, | 2768 | .flags = CLOCK_IN_OMAP343X, |
2769 | .clkdm_name = "per_clkdm", | ||
2623 | .recalc = &followparent_recalc, | 2770 | .recalc = &followparent_recalc, |
2624 | }; | 2771 | }; |
2625 | 2772 | ||
@@ -2630,6 +2777,7 @@ static struct clk mcbsp3_ick = { | |||
2630 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2777 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2631 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | 2778 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
2632 | .flags = CLOCK_IN_OMAP343X, | 2779 | .flags = CLOCK_IN_OMAP343X, |
2780 | .clkdm_name = "per_clkdm", | ||
2633 | .recalc = &followparent_recalc, | 2781 | .recalc = &followparent_recalc, |
2634 | }; | 2782 | }; |
2635 | 2783 | ||
@@ -2640,12 +2788,13 @@ static struct clk mcbsp4_ick = { | |||
2640 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2788 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2641 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | 2789 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
2642 | .flags = CLOCK_IN_OMAP343X, | 2790 | .flags = CLOCK_IN_OMAP343X, |
2791 | .clkdm_name = "per_clkdm", | ||
2643 | .recalc = &followparent_recalc, | 2792 | .recalc = &followparent_recalc, |
2644 | }; | 2793 | }; |
2645 | 2794 | ||
2646 | static const struct clksel mcbsp_234_clksel[] = { | 2795 | static const struct clksel mcbsp_234_clksel[] = { |
2647 | { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, | 2796 | { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, |
2648 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | 2797 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, |
2649 | { .parent = NULL } | 2798 | { .parent = NULL } |
2650 | }; | 2799 | }; |
2651 | 2800 | ||
@@ -2659,6 +2808,7 @@ static struct clk mcbsp2_fck = { | |||
2659 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, | 2808 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, |
2660 | .clksel = mcbsp_234_clksel, | 2809 | .clksel = mcbsp_234_clksel, |
2661 | .flags = CLOCK_IN_OMAP343X, | 2810 | .flags = CLOCK_IN_OMAP343X, |
2811 | .clkdm_name = "per_clkdm", | ||
2662 | .recalc = &omap2_clksel_recalc, | 2812 | .recalc = &omap2_clksel_recalc, |
2663 | }; | 2813 | }; |
2664 | 2814 | ||
@@ -2672,6 +2822,7 @@ static struct clk mcbsp3_fck = { | |||
2672 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, | 2822 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, |
2673 | .clksel = mcbsp_234_clksel, | 2823 | .clksel = mcbsp_234_clksel, |
2674 | .flags = CLOCK_IN_OMAP343X, | 2824 | .flags = CLOCK_IN_OMAP343X, |
2825 | .clkdm_name = "per_clkdm", | ||
2675 | .recalc = &omap2_clksel_recalc, | 2826 | .recalc = &omap2_clksel_recalc, |
2676 | }; | 2827 | }; |
2677 | 2828 | ||
@@ -2685,6 +2836,7 @@ static struct clk mcbsp4_fck = { | |||
2685 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, | 2836 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, |
2686 | .clksel = mcbsp_234_clksel, | 2837 | .clksel = mcbsp_234_clksel, |
2687 | .flags = CLOCK_IN_OMAP343X, | 2838 | .flags = CLOCK_IN_OMAP343X, |
2839 | .clkdm_name = "per_clkdm", | ||
2688 | .recalc = &omap2_clksel_recalc, | 2840 | .recalc = &omap2_clksel_recalc, |
2689 | }; | 2841 | }; |
2690 | 2842 | ||
@@ -2732,6 +2884,7 @@ static struct clk emu_src_ck = { | |||
2732 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, | 2884 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, |
2733 | .clksel = emu_src_clksel, | 2885 | .clksel = emu_src_clksel, |
2734 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 2886 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, |
2887 | .clkdm_name = "emu_clkdm", | ||
2735 | .recalc = &omap2_clksel_recalc, | 2888 | .recalc = &omap2_clksel_recalc, |
2736 | }; | 2889 | }; |
2737 | 2890 | ||
@@ -2755,6 +2908,7 @@ static struct clk pclk_fck = { | |||
2755 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, | 2908 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, |
2756 | .clksel = pclk_emu_clksel, | 2909 | .clksel = pclk_emu_clksel, |
2757 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 2910 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, |
2911 | .clkdm_name = "emu_clkdm", | ||
2758 | .recalc = &omap2_clksel_recalc, | 2912 | .recalc = &omap2_clksel_recalc, |
2759 | }; | 2913 | }; |
2760 | 2914 | ||
@@ -2777,6 +2931,7 @@ static struct clk pclkx2_fck = { | |||
2777 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, | 2931 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, |
2778 | .clksel = pclkx2_emu_clksel, | 2932 | .clksel = pclkx2_emu_clksel, |
2779 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 2933 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, |
2934 | .clkdm_name = "emu_clkdm", | ||
2780 | .recalc = &omap2_clksel_recalc, | 2935 | .recalc = &omap2_clksel_recalc, |
2781 | }; | 2936 | }; |
2782 | 2937 | ||
@@ -2792,6 +2947,7 @@ static struct clk atclk_fck = { | |||
2792 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, | 2947 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, |
2793 | .clksel = atclk_emu_clksel, | 2948 | .clksel = atclk_emu_clksel, |
2794 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 2949 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, |
2950 | .clkdm_name = "emu_clkdm", | ||
2795 | .recalc = &omap2_clksel_recalc, | 2951 | .recalc = &omap2_clksel_recalc, |
2796 | }; | 2952 | }; |
2797 | 2953 | ||
@@ -2802,6 +2958,7 @@ static struct clk traceclk_src_fck = { | |||
2802 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, | 2958 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, |
2803 | .clksel = emu_src_clksel, | 2959 | .clksel = emu_src_clksel, |
2804 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 2960 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, |
2961 | .clkdm_name = "emu_clkdm", | ||
2805 | .recalc = &omap2_clksel_recalc, | 2962 | .recalc = &omap2_clksel_recalc, |
2806 | }; | 2963 | }; |
2807 | 2964 | ||
@@ -2824,6 +2981,7 @@ static struct clk traceclk_fck = { | |||
2824 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, | 2981 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, |
2825 | .clksel = traceclk_clksel, | 2982 | .clksel = traceclk_clksel, |
2826 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | 2983 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, |
2984 | .clkdm_name = "emu_clkdm", | ||
2827 | .recalc = &omap2_clksel_recalc, | 2985 | .recalc = &omap2_clksel_recalc, |
2828 | }; | 2986 | }; |
2829 | 2987 | ||
@@ -2853,11 +3011,13 @@ static struct clk sr_l4_ick = { | |||
2853 | .name = "sr_l4_ick", | 3011 | .name = "sr_l4_ick", |
2854 | .parent = &l4_ick, | 3012 | .parent = &l4_ick, |
2855 | .flags = CLOCK_IN_OMAP343X, | 3013 | .flags = CLOCK_IN_OMAP343X, |
3014 | .clkdm_name = "core_l4_clkdm", | ||
2856 | .recalc = &followparent_recalc, | 3015 | .recalc = &followparent_recalc, |
2857 | }; | 3016 | }; |
2858 | 3017 | ||
2859 | /* SECURE_32K_FCK clocks */ | 3018 | /* SECURE_32K_FCK clocks */ |
2860 | 3019 | ||
3020 | /* XXX This clock no longer exists in 3430 TRM rev F */ | ||
2861 | static struct clk gpt12_fck = { | 3021 | static struct clk gpt12_fck = { |
2862 | .name = "gpt12_fck", | 3022 | .name = "gpt12_fck", |
2863 | .parent = &secure_32k_fck, | 3023 | .parent = &secure_32k_fck, |
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h index a27632037138..cd86dcc7b424 100644 --- a/arch/arm/mach-omap2/clockdomains.h +++ b/arch/arm/mach-omap2/clockdomains.h | |||
@@ -168,12 +168,19 @@ static struct clockdomain sgx_clkdm = { | |||
168 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), | 168 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), |
169 | }; | 169 | }; |
170 | 170 | ||
171 | /* | ||
172 | * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but | ||
173 | * then that information was removed from the 34xx ES2+ TRM. It is | ||
174 | * unclear whether the core is still there, but the clockdomain logic | ||
175 | * is there, and must be programmed to an appropriate state if the | ||
176 | * CORE clockdomain is to become inactive. | ||
177 | */ | ||
171 | static struct clockdomain d2d_clkdm = { | 178 | static struct clockdomain d2d_clkdm = { |
172 | .name = "d2d_clkdm", | 179 | .name = "d2d_clkdm", |
173 | .pwrdm_name = "core_pwrdm", | 180 | .pwrdm_name = "core_pwrdm", |
174 | .flags = CLKDM_CAN_HWSUP, | 181 | .flags = CLKDM_CAN_HWSUP, |
175 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, | 182 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, |
176 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), | 183 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
177 | }; | 184 | }; |
178 | 185 | ||
179 | static struct clockdomain core_l3_34xx_clkdm = { | 186 | static struct clockdomain core_l3_34xx_clkdm = { |