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-rw-r--r--arch/arm/include/asm/io.h5
-rw-r--r--arch/arm/include/asm/mach/map.h15
-rw-r--r--arch/arm/include/asm/pgtable.h1
-rw-r--r--arch/arm/mach-ixp2000/core.c27
-rw-r--r--arch/arm/mach-ixp2000/enp2611.c6
-rw-r--r--arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h8
-rw-r--r--arch/arm/mm/mmu.c7
-rw-r--r--arch/arm/mm/proc-macros.S2
-rw-r--r--arch/arm/mm/proc-xsc3.S2
-rw-r--r--arch/arm/mm/proc-xscale.S2
10 files changed, 26 insertions, 49 deletions
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 71934856fc22..a8094451be57 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -60,10 +60,9 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
60#define MT_DEVICE 0 60#define MT_DEVICE 0
61#define MT_DEVICE_NONSHARED 1 61#define MT_DEVICE_NONSHARED 1
62#define MT_DEVICE_CACHED 2 62#define MT_DEVICE_CACHED 2
63#define MT_DEVICE_IXP2000 3 63#define MT_DEVICE_WC 3
64#define MT_DEVICE_WC 4
65/* 64/*
66 * types 5 onwards can be found in asm/mach/map.h and are undefined 65 * types 4 onwards can be found in asm/mach/map.h and are undefined
67 * for ioremap 66 * for ioremap
68 */ 67 */
69 68
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index 9eb936e49cc3..72586cd4372e 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -18,16 +18,15 @@ struct map_desc {
18 unsigned int type; 18 unsigned int type;
19}; 19};
20 20
21/* types 0-4 are defined in asm/io.h */ 21/* types 0-3 are defined in asm/io.h */
22#define MT_CACHECLEAN 5 22#define MT_CACHECLEAN 4
23#define MT_MINICLEAN 6 23#define MT_MINICLEAN 5
24#define MT_LOW_VECTORS 7 24#define MT_LOW_VECTORS 6
25#define MT_HIGH_VECTORS 8 25#define MT_HIGH_VECTORS 7
26#define MT_MEMORY 9 26#define MT_MEMORY 8
27#define MT_ROM 10 27#define MT_ROM 9
28 28
29#define MT_NONSHARED_DEVICE MT_DEVICE_NONSHARED 29#define MT_NONSHARED_DEVICE MT_DEVICE_NONSHARED
30#define MT_IXP2000_DEVICE MT_DEVICE_IXP2000
31 30
32#ifdef CONFIG_MMU 31#ifdef CONFIG_MMU
33extern void iotable_init(struct map_desc *, int); 32extern void iotable_init(struct map_desc *, int);
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index dfeff814a942..e5054b026c24 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -184,7 +184,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
184#define L_PTE_MT_WRITEALLOC (0x07 << 2) /* 0111 */ 184#define L_PTE_MT_WRITEALLOC (0x07 << 2) /* 0111 */
185#define L_PTE_MT_DEV_SHARED (0x04 << 2) /* 0100 */ 185#define L_PTE_MT_DEV_SHARED (0x04 << 2) /* 0100 */
186#define L_PTE_MT_DEV_NONSHARED (0x0c << 2) /* 1100 */ 186#define L_PTE_MT_DEV_NONSHARED (0x0c << 2) /* 1100 */
187#define L_PTE_MT_DEV_IXP2000 (0x0d << 2) /* 1101 */
188#define L_PTE_MT_DEV_WC (0x09 << 2) /* 1001 */ 187#define L_PTE_MT_DEV_WC (0x09 << 2) /* 1001 */
189#define L_PTE_MT_DEV_CACHED (0x0b << 2) /* 1011 */ 188#define L_PTE_MT_DEV_CACHED (0x0b << 2) /* 1011 */
190#define L_PTE_MT_MASK (0x0f << 2) 189#define L_PTE_MT_MASK (0x0f << 2)
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index a6a4f93085fd..628063ca31e6 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -84,64 +84,57 @@ static struct map_desc ixp2000_io_desc[] __initdata = {
84 .virtual = IXP2000_CAP_VIRT_BASE, 84 .virtual = IXP2000_CAP_VIRT_BASE,
85 .pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE), 85 .pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
86 .length = IXP2000_CAP_SIZE, 86 .length = IXP2000_CAP_SIZE,
87 .type = MT_DEVICE_IXP2000, 87 .type = MT_DEVICE,
88 }, { 88 }, {
89 .virtual = IXP2000_INTCTL_VIRT_BASE, 89 .virtual = IXP2000_INTCTL_VIRT_BASE,
90 .pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE), 90 .pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
91 .length = IXP2000_INTCTL_SIZE, 91 .length = IXP2000_INTCTL_SIZE,
92 .type = MT_DEVICE_IXP2000, 92 .type = MT_DEVICE,
93 }, { 93 }, {
94 .virtual = IXP2000_PCI_CREG_VIRT_BASE, 94 .virtual = IXP2000_PCI_CREG_VIRT_BASE,
95 .pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE), 95 .pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
96 .length = IXP2000_PCI_CREG_SIZE, 96 .length = IXP2000_PCI_CREG_SIZE,
97 .type = MT_DEVICE_IXP2000, 97 .type = MT_DEVICE,
98 }, { 98 }, {
99 .virtual = IXP2000_PCI_CSR_VIRT_BASE, 99 .virtual = IXP2000_PCI_CSR_VIRT_BASE,
100 .pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE), 100 .pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
101 .length = IXP2000_PCI_CSR_SIZE, 101 .length = IXP2000_PCI_CSR_SIZE,
102 .type = MT_DEVICE_IXP2000, 102 .type = MT_DEVICE,
103 }, { 103 }, {
104 .virtual = IXP2000_MSF_VIRT_BASE, 104 .virtual = IXP2000_MSF_VIRT_BASE,
105 .pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE), 105 .pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
106 .length = IXP2000_MSF_SIZE, 106 .length = IXP2000_MSF_SIZE,
107 .type = MT_DEVICE_IXP2000, 107 .type = MT_DEVICE,
108 }, { 108 }, {
109 .virtual = IXP2000_SCRATCH_RING_VIRT_BASE, 109 .virtual = IXP2000_SCRATCH_RING_VIRT_BASE,
110 .pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE), 110 .pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
111 .length = IXP2000_SCRATCH_RING_SIZE, 111 .length = IXP2000_SCRATCH_RING_SIZE,
112 .type = MT_DEVICE_IXP2000, 112 .type = MT_DEVICE,
113 }, { 113 }, {
114 .virtual = IXP2000_SRAM0_VIRT_BASE, 114 .virtual = IXP2000_SRAM0_VIRT_BASE,
115 .pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE), 115 .pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
116 .length = IXP2000_SRAM0_SIZE, 116 .length = IXP2000_SRAM0_SIZE,
117 .type = MT_DEVICE_IXP2000, 117 .type = MT_DEVICE,
118 }, { 118 }, {
119 .virtual = IXP2000_PCI_IO_VIRT_BASE, 119 .virtual = IXP2000_PCI_IO_VIRT_BASE,
120 .pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE), 120 .pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
121 .length = IXP2000_PCI_IO_SIZE, 121 .length = IXP2000_PCI_IO_SIZE,
122 .type = MT_DEVICE_IXP2000, 122 .type = MT_DEVICE,
123 }, { 123 }, {
124 .virtual = IXP2000_PCI_CFG0_VIRT_BASE, 124 .virtual = IXP2000_PCI_CFG0_VIRT_BASE,
125 .pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE), 125 .pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
126 .length = IXP2000_PCI_CFG0_SIZE, 126 .length = IXP2000_PCI_CFG0_SIZE,
127 .type = MT_DEVICE_IXP2000, 127 .type = MT_DEVICE,
128 }, { 128 }, {
129 .virtual = IXP2000_PCI_CFG1_VIRT_BASE, 129 .virtual = IXP2000_PCI_CFG1_VIRT_BASE,
130 .pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE), 130 .pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
131 .length = IXP2000_PCI_CFG1_SIZE, 131 .length = IXP2000_PCI_CFG1_SIZE,
132 .type = MT_DEVICE_IXP2000, 132 .type = MT_DEVICE,
133 } 133 }
134}; 134};
135 135
136void __init ixp2000_map_io(void) 136void __init ixp2000_map_io(void)
137{ 137{
138 /*
139 * On IXP2400 CPUs we need to use MT_DEVICE_IXP2000 so that
140 * XCB=101 (to avoid triggering erratum #66), and given that
141 * this mode speeds up I/O accesses and we have write buffer
142 * flushes in the right places anyway, it doesn't hurt to use
143 * XCB=101 for all IXP2000s.
144 */
145 iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc)); 138 iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
146 139
147 /* Set slowport to 8-bit mode. */ 140 /* Set slowport to 8-bit mode. */
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index c62ed655c1a7..8bb184dbc187 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -70,17 +70,17 @@ static struct map_desc enp2611_io_desc[] __initdata = {
70 .virtual = ENP2611_CALEB_VIRT_BASE, 70 .virtual = ENP2611_CALEB_VIRT_BASE,
71 .pfn = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE), 71 .pfn = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE),
72 .length = ENP2611_CALEB_SIZE, 72 .length = ENP2611_CALEB_SIZE,
73 .type = MT_DEVICE_IXP2000, 73 .type = MT_DEVICE,
74 }, { 74 }, {
75 .virtual = ENP2611_PM3386_0_VIRT_BASE, 75 .virtual = ENP2611_PM3386_0_VIRT_BASE,
76 .pfn = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE), 76 .pfn = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE),
77 .length = ENP2611_PM3386_0_SIZE, 77 .length = ENP2611_PM3386_0_SIZE,
78 .type = MT_DEVICE_IXP2000, 78 .type = MT_DEVICE,
79 }, { 79 }, {
80 .virtual = ENP2611_PM3386_1_VIRT_BASE, 80 .virtual = ENP2611_PM3386_1_VIRT_BASE,
81 .pfn = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE), 81 .pfn = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE),
82 .length = ENP2611_PM3386_1_SIZE, 82 .length = ENP2611_PM3386_1_SIZE,
83 .type = MT_DEVICE_IXP2000, 83 .type = MT_DEVICE,
84 } 84 }
85}; 85};
86 86
diff --git a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
index 19d80379a3e3..822f63f2f4a2 100644
--- a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
+++ b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
@@ -41,13 +41,7 @@
41 * Most of the registers are clumped in 4K regions spread throughout 41 * Most of the registers are clumped in 4K regions spread throughout
42 * the 0xc0000000 -> 0xc0100000 address range, but we just map in 42 * the 0xc0000000 -> 0xc0100000 address range, but we just map in
43 * the whole range using a single 1 MB section instead of small 43 * the whole range using a single 1 MB section instead of small
44 * 4K pages. This has two advantages for us: 44 * 4K pages.
45 *
46 * 1) We use only one TLB entry for large number of on-chip I/O devices.
47 *
48 * 2) We can easily set the Section attributes to XCB=101 on the IXP2400
49 * as required per erratum #66. We accomplish this by using a
50 * new MT_IXP2000_DEVICE memory type with the bits set as required.
51 * 45 *
52 * CAP stands for CSR Access Proxy. 46 * CAP stands for CSR Access Proxy.
53 * 47 *
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 685dc1bf0083..06ad914928cf 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -204,13 +204,6 @@ static struct mem_type mem_types[] = {
204 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, 204 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
205 .domain = DOMAIN_IO, 205 .domain = DOMAIN_IO,
206 }, 206 },
207 [MT_DEVICE_IXP2000] = { /* IXP2400 requires XCB=101 for on-chip I/O */
208 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_IXP2000,
209 .prot_l1 = PMD_TYPE_TABLE,
210 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE |
211 PMD_SECT_TEX(1),
212 .domain = DOMAIN_IO,
213 },
214 [MT_DEVICE_WC] = { /* ioremap_wc */ 207 [MT_DEVICE_WC] = { /* ioremap_wc */
215 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, 208 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
216 .prot_l1 = PMD_TYPE_TABLE, 209 .prot_l1 = PMD_TYPE_TABLE,
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 64e593020857..54b1f721dec8 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -119,7 +119,7 @@
119 .long 0x00 @ unused 119 .long 0x00 @ unused
120 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED 120 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
121 .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED 121 .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
122 .long 0x00 @ L_PTE_MT_DEV_IXP2000 122 .long 0x00 @ unused
123 .long 0x00 @ unused 123 .long 0x00 @ unused
124 .long 0x00 @ unused 124 .long 0x00 @ unused
125 .endm 125 .endm
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 22ecef533a84..ecdd944bc2b9 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -360,7 +360,7 @@ cpu_xsc3_mt_table:
360 .long 0x00 @ unused 360 .long 0x00 @ unused
361 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED 361 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
362 .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED 362 .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
363 .long 0x00 @ L_PTE_MT_DEV_IXP2000 (not present) 363 .long 0x00 @ unused
364 .long 0x00 @ unused 364 .long 0x00 @ unused
365 .long 0x00 @ unused 365 .long 0x00 @ unused
366 366
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 534b4be86ae5..01adbd9462f8 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -443,7 +443,7 @@ cpu_xscale_mt_table:
443 .long 0x00 @ unused 443 .long 0x00 @ unused
444 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED 444 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
445 .long 0x00 @ L_PTE_MT_DEV_NONSHARED 445 .long 0x00 @ L_PTE_MT_DEV_NONSHARED
446 .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_IXP2000 446 .long 0x00 @ unused
447 .long 0x00 @ unused 447 .long 0x00 @ unused
448 .long 0x00 @ unused 448 .long 0x00 @ unused
449 449