diff options
Diffstat (limited to 'arch/arm')
218 files changed, 25404 insertions, 10007 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4039a133006e..d8d253285a94 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -255,6 +255,7 @@ config ARCH_EP93XX | |||
| 255 | select ARM_AMBA | 255 | select ARM_AMBA |
| 256 | select ARM_VIC | 256 | select ARM_VIC |
| 257 | select GENERIC_GPIO | 257 | select GENERIC_GPIO |
| 258 | select HAVE_GPIO_LIB | ||
| 258 | help | 259 | help |
| 259 | This enables support for the Cirrus EP93xx series of CPUs. | 260 | This enables support for the Cirrus EP93xx series of CPUs. |
| 260 | 261 | ||
| @@ -377,15 +378,17 @@ config ARCH_MXC | |||
| 377 | help | 378 | help |
| 378 | Support for Freescale MXC/iMX-based family of processors | 379 | Support for Freescale MXC/iMX-based family of processors |
| 379 | 380 | ||
| 380 | config ARCH_ORION | 381 | config ARCH_ORION5X |
| 381 | bool "Marvell Orion" | 382 | bool "Marvell Orion" |
| 382 | depends on MMU | 383 | depends on MMU |
| 383 | select PCI | 384 | select PCI |
| 384 | select GENERIC_GPIO | 385 | select GENERIC_GPIO |
| 385 | select GENERIC_TIME | 386 | select GENERIC_TIME |
| 386 | select GENERIC_CLOCKEVENTS | 387 | select GENERIC_CLOCKEVENTS |
| 388 | select PLAT_ORION | ||
| 387 | help | 389 | help |
| 388 | Support for Marvell Orion System on Chip family. | 390 | Support for the following Marvell Orion 5x series SoCs: |
| 391 | Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.) | ||
| 389 | 392 | ||
| 390 | config ARCH_PNX4008 | 393 | config ARCH_PNX4008 |
| 391 | bool "Philips Nexperia PNX4008 Mobile" | 394 | bool "Philips Nexperia PNX4008 Mobile" |
| @@ -422,10 +425,15 @@ config ARCH_SA1100 | |||
| 422 | bool "SA1100-based" | 425 | bool "SA1100-based" |
| 423 | select ISA | 426 | select ISA |
| 424 | select ARCH_DISCONTIGMEM_ENABLE | 427 | select ARCH_DISCONTIGMEM_ENABLE |
| 428 | select ARCH_SPARSEMEM_ENABLE | ||
| 429 | select ARCH_SELECT_MEMORY_MODEL | ||
| 425 | select ARCH_MTD_XIP | 430 | select ARCH_MTD_XIP |
| 426 | select GENERIC_GPIO | 431 | select GENERIC_GPIO |
| 427 | select GENERIC_TIME | 432 | select GENERIC_TIME |
| 433 | select GENERIC_CLOCKEVENTS | ||
| 434 | select TICK_ONESHOT | ||
| 428 | select HAVE_IDE | 435 | select HAVE_IDE |
| 436 | select HAVE_GPIO_LIB | ||
| 429 | help | 437 | help |
| 430 | Support for StrongARM 11x0 based boards. | 438 | Support for StrongARM 11x0 based boards. |
| 431 | 439 | ||
| @@ -468,6 +476,7 @@ config ARCH_DAVINCI | |||
| 468 | config ARCH_OMAP | 476 | config ARCH_OMAP |
| 469 | bool "TI OMAP" | 477 | bool "TI OMAP" |
| 470 | select GENERIC_GPIO | 478 | select GENERIC_GPIO |
| 479 | select HAVE_GPIO_LIB | ||
| 471 | select GENERIC_TIME | 480 | select GENERIC_TIME |
| 472 | select GENERIC_CLOCKEVENTS | 481 | select GENERIC_CLOCKEVENTS |
| 473 | help | 482 | help |
| @@ -516,7 +525,7 @@ source "arch/arm/mach-omap1/Kconfig" | |||
| 516 | 525 | ||
| 517 | source "arch/arm/mach-omap2/Kconfig" | 526 | source "arch/arm/mach-omap2/Kconfig" |
| 518 | 527 | ||
| 519 | source "arch/arm/mach-orion/Kconfig" | 528 | source "arch/arm/mach-orion5x/Kconfig" |
| 520 | 529 | ||
| 521 | source "arch/arm/plat-s3c24xx/Kconfig" | 530 | source "arch/arm/plat-s3c24xx/Kconfig" |
| 522 | source "arch/arm/plat-s3c/Kconfig" | 531 | source "arch/arm/plat-s3c/Kconfig" |
| @@ -563,6 +572,9 @@ config ARCH_ACORN | |||
| 563 | config PLAT_IOP | 572 | config PLAT_IOP |
| 564 | bool | 573 | bool |
| 565 | 574 | ||
| 575 | config PLAT_ORION | ||
| 576 | bool | ||
| 577 | |||
| 566 | source arch/arm/mm/Kconfig | 578 | source arch/arm/mm/Kconfig |
| 567 | 579 | ||
| 568 | config IWMMXT | 580 | config IWMMXT |
| @@ -650,7 +662,7 @@ source "kernel/time/Kconfig" | |||
| 650 | 662 | ||
| 651 | config SMP | 663 | config SMP |
| 652 | bool "Symmetric Multi-Processing (EXPERIMENTAL)" | 664 | bool "Symmetric Multi-Processing (EXPERIMENTAL)" |
| 653 | depends on EXPERIMENTAL && REALVIEW_EB_ARM11MP | 665 | depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP) |
| 654 | help | 666 | help |
| 655 | This enables support for systems with more than one CPU. If you have | 667 | This enables support for systems with more than one CPU. If you have |
| 656 | a system with only one CPU, like most personal computers, say N. If | 668 | a system with only one CPU, like most personal computers, say N. If |
| @@ -683,7 +695,7 @@ config HOTPLUG_CPU | |||
| 683 | 695 | ||
| 684 | config LOCAL_TIMERS | 696 | config LOCAL_TIMERS |
| 685 | bool "Use local timer interrupts" | 697 | bool "Use local timer interrupts" |
| 686 | depends on SMP && REALVIEW_EB_ARM11MP | 698 | depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP) |
| 687 | default y | 699 | default y |
| 688 | help | 700 | help |
| 689 | Enable support for local timers on SMP platforms, rather then the | 701 | Enable support for local timers on SMP platforms, rather then the |
| @@ -774,6 +786,12 @@ config ARCH_DISCONTIGMEM_ENABLE | |||
| 774 | or have huge holes in the physical address space for other reasons. | 786 | or have huge holes in the physical address space for other reasons. |
| 775 | See <file:Documentation/vm/numa> for more. | 787 | See <file:Documentation/vm/numa> for more. |
| 776 | 788 | ||
| 789 | config ARCH_SPARSEMEM_ENABLE | ||
| 790 | bool | ||
| 791 | |||
| 792 | config ARCH_SELECT_MEMORY_MODEL | ||
| 793 | bool | ||
| 794 | |||
| 777 | config NODES_SHIFT | 795 | config NODES_SHIFT |
| 778 | int | 796 | int |
| 779 | default "4" if ARCH_LH7A40X | 797 | default "4" if ARCH_LH7A40X |
| @@ -1174,6 +1192,8 @@ source "drivers/dma/Kconfig" | |||
| 1174 | 1192 | ||
| 1175 | source "drivers/dca/Kconfig" | 1193 | source "drivers/dca/Kconfig" |
| 1176 | 1194 | ||
| 1195 | source "drivers/uio/Kconfig" | ||
| 1196 | |||
| 1177 | endmenu | 1197 | endmenu |
| 1178 | 1198 | ||
| 1179 | source "fs/Kconfig" | 1199 | source "fs/Kconfig" |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 1a4649667ec8..e72db27e0ba0 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
| @@ -134,12 +134,11 @@ endif | |||
| 134 | machine-$(CONFIG_ARCH_PNX4008) := pnx4008 | 134 | machine-$(CONFIG_ARCH_PNX4008) := pnx4008 |
| 135 | machine-$(CONFIG_ARCH_NETX) := netx | 135 | machine-$(CONFIG_ARCH_NETX) := netx |
| 136 | machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx | 136 | machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx |
| 137 | textofs-$(CONFIG_ARCH_NS9XXX) := 0x00108000 | ||
| 138 | machine-$(CONFIG_ARCH_DAVINCI) := davinci | 137 | machine-$(CONFIG_ARCH_DAVINCI) := davinci |
| 139 | machine-$(CONFIG_ARCH_KS8695) := ks8695 | 138 | machine-$(CONFIG_ARCH_KS8695) := ks8695 |
| 140 | incdir-$(CONFIG_ARCH_MXC) := mxc | 139 | incdir-$(CONFIG_ARCH_MXC) := mxc |
| 141 | machine-$(CONFIG_ARCH_MX3) := mx3 | 140 | machine-$(CONFIG_ARCH_MX3) := mx3 |
| 142 | machine-$(CONFIG_ARCH_ORION) := orion | 141 | machine-$(CONFIG_ARCH_ORION5X) := orion5x |
| 143 | machine-$(CONFIG_ARCH_MSM7X00A) := msm | 142 | machine-$(CONFIG_ARCH_MSM7X00A) := msm |
| 144 | 143 | ||
| 145 | ifeq ($(CONFIG_ARCH_EBSA110),y) | 144 | ifeq ($(CONFIG_ARCH_EBSA110),y) |
| @@ -185,6 +184,7 @@ core-$(CONFIG_VFP) += arch/arm/vfp/ | |||
| 185 | 184 | ||
| 186 | # If we have a common platform directory, then include it in the build. | 185 | # If we have a common platform directory, then include it in the build. |
| 187 | core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/ | 186 | core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/ |
| 187 | core-$(CONFIG_PLAT_ORION) += arch/arm/plat-orion/ | ||
| 188 | core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/ | 188 | core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/ |
| 189 | core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/ | 189 | core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/ |
| 190 | core-$(CONFIG_ARCH_MXC) += arch/arm/plat-mxc/ | 190 | core-$(CONFIG_ARCH_MXC) += arch/arm/plat-mxc/ |
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile index 25f12303b106..da226abce2d0 100644 --- a/arch/arm/boot/Makefile +++ b/arch/arm/boot/Makefile | |||
| @@ -61,9 +61,15 @@ endif | |||
| 61 | 61 | ||
| 62 | quiet_cmd_uimage = UIMAGE $@ | 62 | quiet_cmd_uimage = UIMAGE $@ |
| 63 | cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \ | 63 | cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \ |
| 64 | -C none -a $(ZRELADDR) -e $(ZRELADDR) \ | 64 | -C none -a $(LOADADDR) -e $(LOADADDR) \ |
| 65 | -n 'Linux-$(KERNELRELEASE)' -d $< $@ | 65 | -n 'Linux-$(KERNELRELEASE)' -d $< $@ |
| 66 | 66 | ||
| 67 | ifeq ($(CONFIG_ZBOOT_ROM),y) | ||
| 68 | $(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT) | ||
| 69 | else | ||
| 70 | $(obj)/uImage: LOADADDR=$(ZRELADDR) | ||
| 71 | endif | ||
| 72 | |||
| 67 | $(obj)/uImage: $(obj)/zImage FORCE | 73 | $(obj)/uImage: $(obj)/zImage FORCE |
| 68 | $(call if_changed,uimage) | 74 | $(call if_changed,uimage) |
| 69 | @echo ' Image $@ is ready' | 75 | @echo ' Image $@ is ready' |
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index 538262241483..5fe9588db077 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c | |||
| @@ -120,6 +120,7 @@ void it8152_irq_demux(unsigned int irq, struct irq_desc *desc) | |||
| 120 | time, when they all three were 0. */ | 120 | time, when they all three were 0. */ |
| 121 | bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); | 121 | bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); |
| 122 | bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); | 122 | bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); |
| 123 | bits_ld = __raw_readl(IT8152_INTC_LDCNIRR); | ||
| 123 | if (!(bits_ld | bits_lp | bits_pd)) | 124 | if (!(bits_ld | bits_lp | bits_pd)) |
| 124 | return; | 125 | return; |
| 125 | } | 126 | } |
| @@ -133,14 +134,14 @@ void it8152_irq_demux(unsigned int irq, struct irq_desc *desc) | |||
| 133 | 134 | ||
| 134 | bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1); | 135 | bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1); |
| 135 | while (bits_lp) { | 136 | while (bits_lp) { |
| 136 | i = __ffs(bits_pd); | 137 | i = __ffs(bits_lp); |
| 137 | it8152_irq(IT8152_LP_IRQ(i)); | 138 | it8152_irq(IT8152_LP_IRQ(i)); |
| 138 | bits_lp &= ~(1 << i); | 139 | bits_lp &= ~(1 << i); |
| 139 | } | 140 | } |
| 140 | 141 | ||
| 141 | bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1); | 142 | bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1); |
| 142 | while (bits_ld) { | 143 | while (bits_ld) { |
| 143 | i = __ffs(bits_pd); | 144 | i = __ffs(bits_ld); |
| 144 | it8152_irq(IT8152_LD_IRQ(i)); | 145 | it8152_irq(IT8152_LD_IRQ(i)); |
| 145 | bits_ld &= ~(1 << i); | 146 | bits_ld &= ~(1 << i); |
| 146 | } | 147 | } |
diff --git a/arch/arm/common/rtctime.c b/arch/arm/common/rtctime.c index f53bca46e23c..aa8f7739c822 100644 --- a/arch/arm/common/rtctime.c +++ b/arch/arm/common/rtctime.c | |||
| @@ -22,7 +22,6 @@ | |||
| 22 | #include <linux/mutex.h> | 22 | #include <linux/mutex.h> |
| 23 | 23 | ||
| 24 | #include <asm/rtc.h> | 24 | #include <asm/rtc.h> |
| 25 | #include <asm/semaphore.h> | ||
| 26 | 25 | ||
| 27 | static DECLARE_WAIT_QUEUE_HEAD(rtc_wait); | 26 | static DECLARE_WAIT_QUEUE_HEAD(rtc_wait); |
| 28 | static struct fasync_struct *rtc_async_queue; | 27 | static struct fasync_struct *rtc_async_queue; |
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c index 314ebd3a1d71..bc299b07a6fa 100644 --- a/arch/arm/common/scoop.c +++ b/arch/arm/common/scoop.c | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | #include <linux/slab.h> | 16 | #include <linux/slab.h> |
| 17 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
| 18 | #include <asm/io.h> | 18 | #include <asm/io.h> |
| 19 | #include <asm/gpio.h> | ||
| 19 | #include <asm/hardware/scoop.h> | 20 | #include <asm/hardware/scoop.h> |
| 20 | 21 | ||
| 21 | /* PCMCIA to Scoop linkage | 22 | /* PCMCIA to Scoop linkage |
| @@ -30,10 +31,9 @@ | |||
| 30 | struct scoop_pcmcia_config *platform_scoop_config; | 31 | struct scoop_pcmcia_config *platform_scoop_config; |
| 31 | EXPORT_SYMBOL(platform_scoop_config); | 32 | EXPORT_SYMBOL(platform_scoop_config); |
| 32 | 33 | ||
| 33 | #define SCOOP_REG(d,adr) (*(volatile unsigned short*)(d +(adr))) | ||
| 34 | |||
| 35 | struct scoop_dev { | 34 | struct scoop_dev { |
| 36 | void *base; | 35 | void __iomem *base; |
| 36 | struct gpio_chip gpio; | ||
| 37 | spinlock_t scoop_lock; | 37 | spinlock_t scoop_lock; |
| 38 | unsigned short suspend_clr; | 38 | unsigned short suspend_clr; |
| 39 | unsigned short suspend_set; | 39 | unsigned short suspend_set; |
| @@ -44,13 +44,84 @@ void reset_scoop(struct device *dev) | |||
| 44 | { | 44 | { |
| 45 | struct scoop_dev *sdev = dev_get_drvdata(dev); | 45 | struct scoop_dev *sdev = dev_get_drvdata(dev); |
| 46 | 46 | ||
| 47 | SCOOP_REG(sdev->base,SCOOP_MCR) = 0x0100; // 00 | 47 | iowrite16(0x0100, sdev->base + SCOOP_MCR); // 00 |
| 48 | SCOOP_REG(sdev->base,SCOOP_CDR) = 0x0000; // 04 | 48 | iowrite16(0x0000, sdev->base + SCOOP_CDR); // 04 |
| 49 | SCOOP_REG(sdev->base,SCOOP_CCR) = 0x0000; // 10 | 49 | iowrite16(0x0000, sdev->base + SCOOP_CCR); // 10 |
| 50 | SCOOP_REG(sdev->base,SCOOP_IMR) = 0x0000; // 18 | 50 | iowrite16(0x0000, sdev->base + SCOOP_IMR); // 18 |
| 51 | SCOOP_REG(sdev->base,SCOOP_IRM) = 0x00FF; // 14 | 51 | iowrite16(0x00FF, sdev->base + SCOOP_IRM); // 14 |
| 52 | SCOOP_REG(sdev->base,SCOOP_ISR) = 0x0000; // 1C | 52 | iowrite16(0x0000, sdev->base + SCOOP_ISR); // 1C |
| 53 | SCOOP_REG(sdev->base,SCOOP_IRM) = 0x0000; | 53 | iowrite16(0x0000, sdev->base + SCOOP_IRM); |
| 54 | } | ||
| 55 | |||
| 56 | static void __scoop_gpio_set(struct scoop_dev *sdev, | ||
| 57 | unsigned offset, int value) | ||
| 58 | { | ||
| 59 | unsigned short gpwr; | ||
| 60 | |||
| 61 | gpwr = ioread16(sdev->base + SCOOP_GPWR); | ||
| 62 | if (value) | ||
| 63 | gpwr |= 1 << (offset + 1); | ||
| 64 | else | ||
| 65 | gpwr &= ~(1 << (offset + 1)); | ||
| 66 | iowrite16(gpwr, sdev->base + SCOOP_GPWR); | ||
| 67 | } | ||
| 68 | |||
| 69 | static void scoop_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | ||
| 70 | { | ||
| 71 | struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio); | ||
| 72 | unsigned long flags; | ||
| 73 | |||
| 74 | spin_lock_irqsave(&sdev->scoop_lock, flags); | ||
| 75 | |||
| 76 | __scoop_gpio_set(sdev, offset, value); | ||
| 77 | |||
| 78 | spin_unlock_irqrestore(&sdev->scoop_lock, flags); | ||
| 79 | } | ||
| 80 | |||
| 81 | static int scoop_gpio_get(struct gpio_chip *chip, unsigned offset) | ||
| 82 | { | ||
| 83 | struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio); | ||
| 84 | |||
| 85 | /* XXX: I'm usure, but it seems so */ | ||
| 86 | return ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1)); | ||
| 87 | } | ||
| 88 | |||
| 89 | static int scoop_gpio_direction_input(struct gpio_chip *chip, | ||
| 90 | unsigned offset) | ||
| 91 | { | ||
| 92 | struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio); | ||
| 93 | unsigned long flags; | ||
| 94 | unsigned short gpcr; | ||
| 95 | |||
| 96 | spin_lock_irqsave(&sdev->scoop_lock, flags); | ||
| 97 | |||
| 98 | gpcr = ioread16(sdev->base + SCOOP_GPCR); | ||
| 99 | gpcr &= ~(1 << (offset + 1)); | ||
| 100 | iowrite16(gpcr, sdev->base + SCOOP_GPCR); | ||
| 101 | |||
| 102 | spin_unlock_irqrestore(&sdev->scoop_lock, flags); | ||
| 103 | |||
| 104 | return 0; | ||
| 105 | } | ||
| 106 | |||
| 107 | static int scoop_gpio_direction_output(struct gpio_chip *chip, | ||
| 108 | unsigned offset, int value) | ||
| 109 | { | ||
| 110 | struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio); | ||
| 111 | unsigned long flags; | ||
| 112 | unsigned short gpcr; | ||
| 113 | |||
| 114 | spin_lock_irqsave(&sdev->scoop_lock, flags); | ||
| 115 | |||
| 116 | __scoop_gpio_set(sdev, offset, value); | ||
| 117 | |||
| 118 | gpcr = ioread16(sdev->base + SCOOP_GPCR); | ||
| 119 | gpcr |= 1 << (offset + 1); | ||
| 120 | iowrite16(gpcr, sdev->base + SCOOP_GPCR); | ||
| 121 | |||
| 122 | spin_unlock_irqrestore(&sdev->scoop_lock, flags); | ||
| 123 | |||
| 124 | return 0; | ||
| 54 | } | 125 | } |
| 55 | 126 | ||
| 56 | unsigned short set_scoop_gpio(struct device *dev, unsigned short bit) | 127 | unsigned short set_scoop_gpio(struct device *dev, unsigned short bit) |
| @@ -60,8 +131,8 @@ unsigned short set_scoop_gpio(struct device *dev, unsigned short bit) | |||
| 60 | struct scoop_dev *sdev = dev_get_drvdata(dev); | 131 | struct scoop_dev *sdev = dev_get_drvdata(dev); |
| 61 | 132 | ||
| 62 | spin_lock_irqsave(&sdev->scoop_lock, flag); | 133 | spin_lock_irqsave(&sdev->scoop_lock, flag); |
| 63 | gpio_bit = SCOOP_REG(sdev->base, SCOOP_GPWR) | bit; | 134 | gpio_bit = ioread16(sdev->base + SCOOP_GPWR) | bit; |
| 64 | SCOOP_REG(sdev->base, SCOOP_GPWR) = gpio_bit; | 135 | iowrite16(gpio_bit, sdev->base + SCOOP_GPWR); |
| 65 | spin_unlock_irqrestore(&sdev->scoop_lock, flag); | 136 | spin_unlock_irqrestore(&sdev->scoop_lock, flag); |
| 66 | 137 | ||
| 67 | return gpio_bit; | 138 | return gpio_bit; |
| @@ -74,8 +145,8 @@ unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit) | |||
| 74 | struct scoop_dev *sdev = dev_get_drvdata(dev); | 145 | struct scoop_dev *sdev = dev_get_drvdata(dev); |
| 75 | 146 | ||
| 76 | spin_lock_irqsave(&sdev->scoop_lock, flag); | 147 | spin_lock_irqsave(&sdev->scoop_lock, flag); |
| 77 | gpio_bit = SCOOP_REG(sdev->base, SCOOP_GPWR) & ~bit; | 148 | gpio_bit = ioread16(sdev->base + SCOOP_GPWR) & ~bit; |
| 78 | SCOOP_REG(sdev->base,SCOOP_GPWR) = gpio_bit; | 149 | iowrite16(gpio_bit, sdev->base + SCOOP_GPWR); |
| 79 | spin_unlock_irqrestore(&sdev->scoop_lock, flag); | 150 | spin_unlock_irqrestore(&sdev->scoop_lock, flag); |
| 80 | 151 | ||
| 81 | return gpio_bit; | 152 | return gpio_bit; |
| @@ -87,13 +158,13 @@ EXPORT_SYMBOL(reset_scoop_gpio); | |||
| 87 | unsigned short read_scoop_reg(struct device *dev, unsigned short reg) | 158 | unsigned short read_scoop_reg(struct device *dev, unsigned short reg) |
| 88 | { | 159 | { |
| 89 | struct scoop_dev *sdev = dev_get_drvdata(dev); | 160 | struct scoop_dev *sdev = dev_get_drvdata(dev); |
| 90 | return SCOOP_REG(sdev->base,reg); | 161 | return ioread16(sdev->base + reg); |
| 91 | } | 162 | } |
| 92 | 163 | ||
| 93 | void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data) | 164 | void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data) |
| 94 | { | 165 | { |
| 95 | struct scoop_dev *sdev = dev_get_drvdata(dev); | 166 | struct scoop_dev *sdev = dev_get_drvdata(dev); |
| 96 | SCOOP_REG(sdev->base,reg)=data; | 167 | iowrite16(data, sdev->base + reg); |
| 97 | } | 168 | } |
| 98 | 169 | ||
| 99 | EXPORT_SYMBOL(reset_scoop); | 170 | EXPORT_SYMBOL(reset_scoop); |
| @@ -104,9 +175,9 @@ static void check_scoop_reg(struct scoop_dev *sdev) | |||
| 104 | { | 175 | { |
| 105 | unsigned short mcr; | 176 | unsigned short mcr; |
| 106 | 177 | ||
| 107 | mcr = SCOOP_REG(sdev->base, SCOOP_MCR); | 178 | mcr = ioread16(sdev->base + SCOOP_MCR); |
| 108 | if ((mcr & 0x100) == 0) | 179 | if ((mcr & 0x100) == 0) |
| 109 | SCOOP_REG(sdev->base, SCOOP_MCR) = 0x0101; | 180 | iowrite16(0x0101, sdev->base + SCOOP_MCR); |
| 110 | } | 181 | } |
| 111 | 182 | ||
| 112 | #ifdef CONFIG_PM | 183 | #ifdef CONFIG_PM |
| @@ -115,8 +186,8 @@ static int scoop_suspend(struct platform_device *dev, pm_message_t state) | |||
| 115 | struct scoop_dev *sdev = platform_get_drvdata(dev); | 186 | struct scoop_dev *sdev = platform_get_drvdata(dev); |
| 116 | 187 | ||
| 117 | check_scoop_reg(sdev); | 188 | check_scoop_reg(sdev); |
| 118 | sdev->scoop_gpwr = SCOOP_REG(sdev->base, SCOOP_GPWR); | 189 | sdev->scoop_gpwr = ioread16(sdev->base + SCOOP_GPWR); |
| 119 | SCOOP_REG(sdev->base, SCOOP_GPWR) = (sdev->scoop_gpwr & ~sdev->suspend_clr) | sdev->suspend_set; | 190 | iowrite16((sdev->scoop_gpwr & ~sdev->suspend_clr) | sdev->suspend_set, sdev->base + SCOOP_GPWR); |
| 120 | 191 | ||
| 121 | return 0; | 192 | return 0; |
| 122 | } | 193 | } |
| @@ -126,7 +197,7 @@ static int scoop_resume(struct platform_device *dev) | |||
| 126 | struct scoop_dev *sdev = platform_get_drvdata(dev); | 197 | struct scoop_dev *sdev = platform_get_drvdata(dev); |
| 127 | 198 | ||
| 128 | check_scoop_reg(sdev); | 199 | check_scoop_reg(sdev); |
| 129 | SCOOP_REG(sdev->base,SCOOP_GPWR) = sdev->scoop_gpwr; | 200 | iowrite16(sdev->scoop_gpwr, sdev->base + SCOOP_GPWR); |
| 130 | 201 | ||
| 131 | return 0; | 202 | return 0; |
| 132 | } | 203 | } |
| @@ -135,11 +206,13 @@ static int scoop_resume(struct platform_device *dev) | |||
| 135 | #define scoop_resume NULL | 206 | #define scoop_resume NULL |
| 136 | #endif | 207 | #endif |
| 137 | 208 | ||
| 138 | int __init scoop_probe(struct platform_device *pdev) | 209 | static int __devinit scoop_probe(struct platform_device *pdev) |
| 139 | { | 210 | { |
| 140 | struct scoop_dev *devptr; | 211 | struct scoop_dev *devptr; |
| 141 | struct scoop_config *inf; | 212 | struct scoop_config *inf; |
| 142 | struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 213 | struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 214 | int ret; | ||
| 215 | int temp; | ||
| 143 | 216 | ||
| 144 | if (!mem) | 217 | if (!mem) |
| 145 | return -EINVAL; | 218 | return -EINVAL; |
| @@ -154,40 +227,78 @@ int __init scoop_probe(struct platform_device *pdev) | |||
| 154 | devptr->base = ioremap(mem->start, mem->end - mem->start + 1); | 227 | devptr->base = ioremap(mem->start, mem->end - mem->start + 1); |
| 155 | 228 | ||
| 156 | if (!devptr->base) { | 229 | if (!devptr->base) { |
| 157 | kfree(devptr); | 230 | ret = -ENOMEM; |
| 158 | return -ENOMEM; | 231 | goto err_ioremap; |
| 159 | } | 232 | } |
| 160 | 233 | ||
| 161 | platform_set_drvdata(pdev, devptr); | 234 | platform_set_drvdata(pdev, devptr); |
| 162 | 235 | ||
| 163 | printk("Sharp Scoop Device found at 0x%08x -> 0x%08x\n",(unsigned int)mem->start,(unsigned int)devptr->base); | 236 | printk("Sharp Scoop Device found at 0x%08x -> 0x%8p\n",(unsigned int)mem->start, devptr->base); |
| 164 | 237 | ||
| 165 | SCOOP_REG(devptr->base, SCOOP_MCR) = 0x0140; | 238 | iowrite16(0x0140, devptr->base + SCOOP_MCR); |
| 166 | reset_scoop(&pdev->dev); | 239 | reset_scoop(&pdev->dev); |
| 167 | SCOOP_REG(devptr->base, SCOOP_CPR) = 0x0000; | 240 | iowrite16(0x0000, devptr->base + SCOOP_CPR); |
| 168 | SCOOP_REG(devptr->base, SCOOP_GPCR) = inf->io_dir & 0xffff; | 241 | iowrite16(inf->io_dir & 0xffff, devptr->base + SCOOP_GPCR); |
| 169 | SCOOP_REG(devptr->base, SCOOP_GPWR) = inf->io_out & 0xffff; | 242 | iowrite16(inf->io_out & 0xffff, devptr->base + SCOOP_GPWR); |
| 170 | 243 | ||
| 171 | devptr->suspend_clr = inf->suspend_clr; | 244 | devptr->suspend_clr = inf->suspend_clr; |
| 172 | devptr->suspend_set = inf->suspend_set; | 245 | devptr->suspend_set = inf->suspend_set; |
| 173 | 246 | ||
| 247 | devptr->gpio.base = -1; | ||
| 248 | |||
| 249 | if (inf->gpio_base != 0) { | ||
| 250 | devptr->gpio.label = pdev->dev.bus_id; | ||
| 251 | devptr->gpio.base = inf->gpio_base; | ||
| 252 | devptr->gpio.ngpio = 12; /* PA11 = 0, PA12 = 1, etc. up to PA22 = 11 */ | ||
| 253 | devptr->gpio.set = scoop_gpio_set; | ||
| 254 | devptr->gpio.get = scoop_gpio_get; | ||
| 255 | devptr->gpio.direction_input = scoop_gpio_direction_input; | ||
| 256 | devptr->gpio.direction_output = scoop_gpio_direction_output; | ||
| 257 | |||
| 258 | ret = gpiochip_add(&devptr->gpio); | ||
| 259 | if (ret) | ||
| 260 | goto err_gpio; | ||
| 261 | } | ||
| 262 | |||
| 174 | return 0; | 263 | return 0; |
| 264 | |||
| 265 | if (devptr->gpio.base != -1) | ||
| 266 | temp = gpiochip_remove(&devptr->gpio); | ||
| 267 | err_gpio: | ||
| 268 | platform_set_drvdata(pdev, NULL); | ||
| 269 | err_ioremap: | ||
| 270 | iounmap(devptr->base); | ||
| 271 | kfree(devptr); | ||
| 272 | |||
| 273 | return ret; | ||
| 175 | } | 274 | } |
| 176 | 275 | ||
| 177 | static int scoop_remove(struct platform_device *pdev) | 276 | static int __devexit scoop_remove(struct platform_device *pdev) |
| 178 | { | 277 | { |
| 179 | struct scoop_dev *sdev = platform_get_drvdata(pdev); | 278 | struct scoop_dev *sdev = platform_get_drvdata(pdev); |
| 180 | if (sdev) { | 279 | int ret; |
| 181 | iounmap(sdev->base); | 280 | |
| 182 | kfree(sdev); | 281 | if (!sdev) |
| 183 | platform_set_drvdata(pdev, NULL); | 282 | return -EINVAL; |
| 283 | |||
| 284 | if (sdev->gpio.base != -1) { | ||
| 285 | ret = gpiochip_remove(&sdev->gpio); | ||
| 286 | if (ret) { | ||
| 287 | dev_err(&pdev->dev, "Can't remove gpio chip: %d\n", ret); | ||
| 288 | return ret; | ||
| 289 | } | ||
| 184 | } | 290 | } |
| 291 | |||
| 292 | platform_set_drvdata(pdev, NULL); | ||
| 293 | iounmap(sdev->base); | ||
| 294 | kfree(sdev); | ||
| 295 | |||
| 185 | return 0; | 296 | return 0; |
| 186 | } | 297 | } |
| 187 | 298 | ||
| 188 | static struct platform_driver scoop_driver = { | 299 | static struct platform_driver scoop_driver = { |
| 189 | .probe = scoop_probe, | 300 | .probe = scoop_probe, |
| 190 | .remove = scoop_remove, | 301 | .remove = __devexit_p(scoop_remove), |
| 191 | .suspend = scoop_suspend, | 302 | .suspend = scoop_suspend, |
| 192 | .resume = scoop_resume, | 303 | .resume = scoop_resume, |
| 193 | .driver = { | 304 | .driver = { |
| @@ -195,7 +306,7 @@ static struct platform_driver scoop_driver = { | |||
| 195 | }, | 306 | }, |
| 196 | }; | 307 | }; |
| 197 | 308 | ||
| 198 | int __init scoop_init(void) | 309 | static int __init scoop_init(void) |
| 199 | { | 310 | { |
| 200 | return platform_driver_register(&scoop_driver); | 311 | return platform_driver_register(&scoop_driver); |
| 201 | } | 312 | } |
diff --git a/arch/arm/configs/at91rm9200dk_defconfig b/arch/arm/configs/at91rm9200dk_defconfig index e10d003566d6..2dbbbc3d4ac3 100644 --- a/arch/arm/configs/at91rm9200dk_defconfig +++ b/arch/arm/configs/at91rm9200dk_defconfig | |||
| @@ -620,14 +620,14 @@ CONFIG_I2C_CHARDEV=y | |||
| 620 | # | 620 | # |
| 621 | # I2C Algorithms | 621 | # I2C Algorithms |
| 622 | # | 622 | # |
| 623 | # CONFIG_I2C_ALGOBIT is not set | 623 | CONFIG_I2C_ALGOBIT=y |
| 624 | # CONFIG_I2C_ALGOPCF is not set | 624 | # CONFIG_I2C_ALGOPCF is not set |
| 625 | # CONFIG_I2C_ALGOPCA is not set | 625 | # CONFIG_I2C_ALGOPCA is not set |
| 626 | 626 | ||
| 627 | # | 627 | # |
| 628 | # I2C Hardware Bus support | 628 | # I2C Hardware Bus support |
| 629 | # | 629 | # |
| 630 | CONFIG_I2C_AT91=y | 630 | CONFIG_I2C_GPIO=y |
| 631 | # CONFIG_I2C_PARPORT_LIGHT is not set | 631 | # CONFIG_I2C_PARPORT_LIGHT is not set |
| 632 | # CONFIG_I2C_STUB is not set | 632 | # CONFIG_I2C_STUB is not set |
| 633 | # CONFIG_I2C_PCA_ISA is not set | 633 | # CONFIG_I2C_PCA_ISA is not set |
diff --git a/arch/arm/configs/at91rm9200ek_defconfig b/arch/arm/configs/at91rm9200ek_defconfig index 834dddb51314..6e994f7820c6 100644 --- a/arch/arm/configs/at91rm9200ek_defconfig +++ b/arch/arm/configs/at91rm9200ek_defconfig | |||
| @@ -594,14 +594,14 @@ CONFIG_I2C_CHARDEV=y | |||
| 594 | # | 594 | # |
| 595 | # I2C Algorithms | 595 | # I2C Algorithms |
| 596 | # | 596 | # |
| 597 | # CONFIG_I2C_ALGOBIT is not set | 597 | CONFIG_I2C_ALGOBIT=y |
| 598 | # CONFIG_I2C_ALGOPCF is not set | 598 | # CONFIG_I2C_ALGOPCF is not set |
| 599 | # CONFIG_I2C_ALGOPCA is not set | 599 | # CONFIG_I2C_ALGOPCA is not set |
| 600 | 600 | ||
| 601 | # | 601 | # |
| 602 | # I2C Hardware Bus support | 602 | # I2C Hardware Bus support |
| 603 | # | 603 | # |
| 604 | CONFIG_I2C_AT91=y | 604 | CONFIG_I2C_GPIO=y |
| 605 | # CONFIG_I2C_PARPORT_LIGHT is not set | 605 | # CONFIG_I2C_PARPORT_LIGHT is not set |
| 606 | # CONFIG_I2C_STUB is not set | 606 | # CONFIG_I2C_STUB is not set |
| 607 | # CONFIG_I2C_PCA_ISA is not set | 607 | # CONFIG_I2C_PCA_ISA is not set |
diff --git a/arch/arm/configs/at91sam9260ek_defconfig b/arch/arm/configs/at91sam9260ek_defconfig index 46b0c734aeb9..f659c938473f 100644 --- a/arch/arm/configs/at91sam9260ek_defconfig +++ b/arch/arm/configs/at91sam9260ek_defconfig | |||
| @@ -1,43 +1,56 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.19-rc6 | 3 | # Linux kernel version: 2.6.24-rc7 |
| 4 | # Fri Nov 17 18:42:21 2006 | 4 | # Tue Jan 8 22:20:50 2008 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 7 | # CONFIG_GENERIC_TIME is not set | 9 | # CONFIG_GENERIC_TIME is not set |
| 10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
| 8 | CONFIG_MMU=y | 11 | CONFIG_MMU=y |
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 9 | CONFIG_GENERIC_HARDIRQS=y | 13 | CONFIG_GENERIC_HARDIRQS=y |
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 10 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y |
| 11 | CONFIG_HARDIRQS_SW_RESEND=y | 17 | CONFIG_HARDIRQS_SW_RESEND=y |
| 12 | CONFIG_GENERIC_IRQ_PROBE=y | 18 | CONFIG_GENERIC_IRQ_PROBE=y |
| 13 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 20 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 14 | CONFIG_GENERIC_HWEIGHT=y | 22 | CONFIG_GENERIC_HWEIGHT=y |
| 15 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 24 | CONFIG_ZONE_DMA=y | ||
| 16 | CONFIG_VECTORS_BASE=0xffff0000 | 25 | CONFIG_VECTORS_BASE=0xffff0000 |
| 17 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 26 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 18 | 27 | ||
| 19 | # | 28 | # |
| 20 | # Code maturity level options | 29 | # General setup |
| 21 | # | 30 | # |
| 22 | CONFIG_EXPERIMENTAL=y | 31 | CONFIG_EXPERIMENTAL=y |
| 23 | CONFIG_BROKEN_ON_SMP=y | 32 | CONFIG_BROKEN_ON_SMP=y |
| 24 | CONFIG_INIT_ENV_ARG_LIMIT=32 | 33 | CONFIG_INIT_ENV_ARG_LIMIT=32 |
| 25 | |||
| 26 | # | ||
| 27 | # General setup | ||
| 28 | # | ||
| 29 | CONFIG_LOCALVERSION="" | 34 | CONFIG_LOCALVERSION="" |
| 30 | # CONFIG_LOCALVERSION_AUTO is not set | 35 | # CONFIG_LOCALVERSION_AUTO is not set |
| 31 | # CONFIG_SWAP is not set | 36 | # CONFIG_SWAP is not set |
| 32 | CONFIG_SYSVIPC=y | 37 | CONFIG_SYSVIPC=y |
| 33 | # CONFIG_IPC_NS is not set | 38 | CONFIG_SYSVIPC_SYSCTL=y |
| 34 | # CONFIG_POSIX_MQUEUE is not set | 39 | # CONFIG_POSIX_MQUEUE is not set |
| 35 | # CONFIG_BSD_PROCESS_ACCT is not set | 40 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 36 | # CONFIG_TASKSTATS is not set | 41 | # CONFIG_TASKSTATS is not set |
| 37 | # CONFIG_UTS_NS is not set | 42 | # CONFIG_USER_NS is not set |
| 43 | # CONFIG_PID_NS is not set | ||
| 38 | # CONFIG_AUDIT is not set | 44 | # CONFIG_AUDIT is not set |
| 39 | # CONFIG_IKCONFIG is not set | 45 | # CONFIG_IKCONFIG is not set |
| 46 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 47 | # CONFIG_CGROUPS is not set | ||
| 48 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 49 | CONFIG_FAIR_USER_SCHED=y | ||
| 50 | # CONFIG_FAIR_CGROUP_SCHED is not set | ||
| 51 | CONFIG_SYSFS_DEPRECATED=y | ||
| 40 | # CONFIG_RELAY is not set | 52 | # CONFIG_RELAY is not set |
| 53 | CONFIG_BLK_DEV_INITRD=y | ||
| 41 | CONFIG_INITRAMFS_SOURCE="" | 54 | CONFIG_INITRAMFS_SOURCE="" |
| 42 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 55 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 43 | CONFIG_SYSCTL=y | 56 | CONFIG_SYSCTL=y |
| @@ -53,30 +66,30 @@ CONFIG_BUG=y | |||
| 53 | CONFIG_ELF_CORE=y | 66 | CONFIG_ELF_CORE=y |
| 54 | CONFIG_BASE_FULL=y | 67 | CONFIG_BASE_FULL=y |
| 55 | CONFIG_FUTEX=y | 68 | CONFIG_FUTEX=y |
| 69 | CONFIG_ANON_INODES=y | ||
| 56 | CONFIG_EPOLL=y | 70 | CONFIG_EPOLL=y |
| 71 | CONFIG_SIGNALFD=y | ||
| 72 | CONFIG_EVENTFD=y | ||
| 57 | CONFIG_SHMEM=y | 73 | CONFIG_SHMEM=y |
| 58 | CONFIG_SLAB=y | ||
| 59 | CONFIG_VM_EVENT_COUNTERS=y | 74 | CONFIG_VM_EVENT_COUNTERS=y |
| 75 | CONFIG_SLAB=y | ||
| 76 | # CONFIG_SLUB is not set | ||
| 77 | # CONFIG_SLOB is not set | ||
| 78 | CONFIG_SLABINFO=y | ||
| 60 | CONFIG_RT_MUTEXES=y | 79 | CONFIG_RT_MUTEXES=y |
| 61 | # CONFIG_TINY_SHMEM is not set | 80 | # CONFIG_TINY_SHMEM is not set |
| 62 | CONFIG_BASE_SMALL=0 | 81 | CONFIG_BASE_SMALL=0 |
| 63 | # CONFIG_SLOB is not set | ||
| 64 | |||
| 65 | # | ||
| 66 | # Loadable module support | ||
| 67 | # | ||
| 68 | CONFIG_MODULES=y | 82 | CONFIG_MODULES=y |
| 69 | CONFIG_MODULE_UNLOAD=y | 83 | CONFIG_MODULE_UNLOAD=y |
| 70 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 84 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 71 | # CONFIG_MODVERSIONS is not set | 85 | # CONFIG_MODVERSIONS is not set |
| 72 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 86 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 73 | CONFIG_KMOD=y | 87 | CONFIG_KMOD=y |
| 74 | |||
| 75 | # | ||
| 76 | # Block layer | ||
| 77 | # | ||
| 78 | CONFIG_BLOCK=y | 88 | CONFIG_BLOCK=y |
| 89 | # CONFIG_LBD is not set | ||
| 79 | # CONFIG_BLK_DEV_IO_TRACE is not set | 90 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 91 | # CONFIG_LSF is not set | ||
| 92 | # CONFIG_BLK_DEV_BSG is not set | ||
| 80 | 93 | ||
| 81 | # | 94 | # |
| 82 | # IO Schedulers | 95 | # IO Schedulers |
| @@ -108,12 +121,16 @@ CONFIG_ARCH_AT91=y | |||
| 108 | # CONFIG_ARCH_NETX is not set | 121 | # CONFIG_ARCH_NETX is not set |
| 109 | # CONFIG_ARCH_H720X is not set | 122 | # CONFIG_ARCH_H720X is not set |
| 110 | # CONFIG_ARCH_IMX is not set | 123 | # CONFIG_ARCH_IMX is not set |
| 124 | # CONFIG_ARCH_IOP13XX is not set | ||
| 111 | # CONFIG_ARCH_IOP32X is not set | 125 | # CONFIG_ARCH_IOP32X is not set |
| 112 | # CONFIG_ARCH_IOP33X is not set | 126 | # CONFIG_ARCH_IOP33X is not set |
| 113 | # CONFIG_ARCH_IXP4XX is not set | ||
| 114 | # CONFIG_ARCH_IXP2000 is not set | ||
| 115 | # CONFIG_ARCH_IXP23XX is not set | 127 | # CONFIG_ARCH_IXP23XX is not set |
| 128 | # CONFIG_ARCH_IXP2000 is not set | ||
| 129 | # CONFIG_ARCH_IXP4XX is not set | ||
| 116 | # CONFIG_ARCH_L7200 is not set | 130 | # CONFIG_ARCH_L7200 is not set |
| 131 | # CONFIG_ARCH_KS8695 is not set | ||
| 132 | # CONFIG_ARCH_NS9XXX is not set | ||
| 133 | # CONFIG_ARCH_MXC is not set | ||
| 117 | # CONFIG_ARCH_PNX4008 is not set | 134 | # CONFIG_ARCH_PNX4008 is not set |
| 118 | # CONFIG_ARCH_PXA is not set | 135 | # CONFIG_ARCH_PXA is not set |
| 119 | # CONFIG_ARCH_RPC is not set | 136 | # CONFIG_ARCH_RPC is not set |
| @@ -121,29 +138,52 @@ CONFIG_ARCH_AT91=y | |||
| 121 | # CONFIG_ARCH_S3C2410 is not set | 138 | # CONFIG_ARCH_S3C2410 is not set |
| 122 | # CONFIG_ARCH_SHARK is not set | 139 | # CONFIG_ARCH_SHARK is not set |
| 123 | # CONFIG_ARCH_LH7A40X is not set | 140 | # CONFIG_ARCH_LH7A40X is not set |
| 141 | # CONFIG_ARCH_DAVINCI is not set | ||
| 124 | # CONFIG_ARCH_OMAP is not set | 142 | # CONFIG_ARCH_OMAP is not set |
| 125 | 143 | ||
| 126 | # | 144 | # |
| 145 | # Boot options | ||
| 146 | # | ||
| 147 | |||
| 148 | # | ||
| 149 | # Power management | ||
| 150 | # | ||
| 151 | |||
| 152 | # | ||
| 127 | # Atmel AT91 System-on-Chip | 153 | # Atmel AT91 System-on-Chip |
| 128 | # | 154 | # |
| 129 | # CONFIG_ARCH_AT91RM9200 is not set | 155 | # CONFIG_ARCH_AT91RM9200 is not set |
| 130 | CONFIG_ARCH_AT91SAM9260=y | 156 | CONFIG_ARCH_AT91SAM9260=y |
| 131 | # CONFIG_ARCH_AT91SAM9261 is not set | 157 | # CONFIG_ARCH_AT91SAM9261 is not set |
| 158 | # CONFIG_ARCH_AT91SAM9263 is not set | ||
| 159 | # CONFIG_ARCH_AT91SAM9RL is not set | ||
| 160 | # CONFIG_ARCH_AT91X40 is not set | ||
| 161 | CONFIG_AT91_PMC_UNIT=y | ||
| 162 | |||
| 163 | # | ||
| 164 | # AT91SAM9260 Variants | ||
| 165 | # | ||
| 166 | # CONFIG_ARCH_AT91SAM9260_SAM9XE is not set | ||
| 132 | 167 | ||
| 133 | # | 168 | # |
| 134 | # AT91SAM9260 Board Type | 169 | # AT91SAM9260 / AT91SAM9XE Board Type |
| 135 | # | 170 | # |
| 136 | CONFIG_MACH_AT91SAM9260EK=y | 171 | CONFIG_MACH_AT91SAM9260EK=y |
| 172 | # CONFIG_MACH_CAM60 is not set | ||
| 173 | # CONFIG_MACH_SAM9_L9260 is not set | ||
| 137 | 174 | ||
| 138 | # | 175 | # |
| 139 | # AT91 Board Options | 176 | # AT91 Board Options |
| 140 | # | 177 | # |
| 178 | # CONFIG_MTD_AT91_DATAFLASH_CARD is not set | ||
| 141 | # CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set | 179 | # CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set |
| 142 | 180 | ||
| 143 | # | 181 | # |
| 144 | # AT91 Feature Selections | 182 | # AT91 Feature Selections |
| 145 | # | 183 | # |
| 146 | # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set | 184 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y |
| 185 | # CONFIG_ATMEL_TCLIB is not set | ||
| 186 | CONFIG_AT91_TIMER_HZ=100 | ||
| 147 | 187 | ||
| 148 | # | 188 | # |
| 149 | # Processor Type | 189 | # Processor Type |
| @@ -166,19 +206,19 @@ CONFIG_CPU_CP15_MMU=y | |||
| 166 | # CONFIG_CPU_DCACHE_DISABLE is not set | 206 | # CONFIG_CPU_DCACHE_DISABLE is not set |
| 167 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | 207 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set |
| 168 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set | 208 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set |
| 209 | # CONFIG_OUTER_CACHE is not set | ||
| 169 | 210 | ||
| 170 | # | 211 | # |
| 171 | # Bus support | 212 | # Bus support |
| 172 | # | 213 | # |
| 173 | 214 | # CONFIG_PCI_SYSCALL is not set | |
| 174 | # | 215 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 175 | # PCCARD (PCMCIA/CardBus) support | ||
| 176 | # | ||
| 177 | # CONFIG_PCCARD is not set | 216 | # CONFIG_PCCARD is not set |
| 178 | 217 | ||
| 179 | # | 218 | # |
| 180 | # Kernel Features | 219 | # Kernel Features |
| 181 | # | 220 | # |
| 221 | # CONFIG_TICK_ONESHOT is not set | ||
| 182 | # CONFIG_PREEMPT is not set | 222 | # CONFIG_PREEMPT is not set |
| 183 | # CONFIG_NO_IDLE_HZ is not set | 223 | # CONFIG_NO_IDLE_HZ is not set |
| 184 | CONFIG_HZ=100 | 224 | CONFIG_HZ=100 |
| @@ -191,8 +231,12 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 191 | CONFIG_FLATMEM=y | 231 | CONFIG_FLATMEM=y |
| 192 | CONFIG_FLAT_NODE_MEM_MAP=y | 232 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 193 | # CONFIG_SPARSEMEM_STATIC is not set | 233 | # CONFIG_SPARSEMEM_STATIC is not set |
| 234 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 194 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 235 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 195 | # CONFIG_RESOURCES_64BIT is not set | 236 | # CONFIG_RESOURCES_64BIT is not set |
| 237 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 238 | CONFIG_BOUNCE=y | ||
| 239 | CONFIG_VIRT_TO_BUS=y | ||
| 196 | # CONFIG_LEDS is not set | 240 | # CONFIG_LEDS is not set |
| 197 | CONFIG_ALIGNMENT_TRAP=y | 241 | CONFIG_ALIGNMENT_TRAP=y |
| 198 | 242 | ||
| @@ -203,6 +247,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 | |||
| 203 | CONFIG_ZBOOT_ROM_BSS=0x0 | 247 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 204 | CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" | 248 | CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" |
| 205 | # CONFIG_XIP_KERNEL is not set | 249 | # CONFIG_XIP_KERNEL is not set |
| 250 | # CONFIG_KEXEC is not set | ||
| 206 | 251 | ||
| 207 | # | 252 | # |
| 208 | # Floating point emulation | 253 | # Floating point emulation |
| @@ -228,7 +273,7 @@ CONFIG_BINFMT_ELF=y | |||
| 228 | # Power management options | 273 | # Power management options |
| 229 | # | 274 | # |
| 230 | # CONFIG_PM is not set | 275 | # CONFIG_PM is not set |
| 231 | # CONFIG_APM is not set | 276 | CONFIG_SUSPEND_UP_POSSIBLE=y |
| 232 | 277 | ||
| 233 | # | 278 | # |
| 234 | # Networking | 279 | # Networking |
| @@ -238,13 +283,9 @@ CONFIG_NET=y | |||
| 238 | # | 283 | # |
| 239 | # Networking options | 284 | # Networking options |
| 240 | # | 285 | # |
| 241 | # CONFIG_NETDEBUG is not set | ||
| 242 | CONFIG_PACKET=y | 286 | CONFIG_PACKET=y |
| 243 | # CONFIG_PACKET_MMAP is not set | 287 | # CONFIG_PACKET_MMAP is not set |
| 244 | CONFIG_UNIX=y | 288 | CONFIG_UNIX=y |
| 245 | CONFIG_XFRM=y | ||
| 246 | # CONFIG_XFRM_USER is not set | ||
| 247 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 248 | # CONFIG_NET_KEY is not set | 289 | # CONFIG_NET_KEY is not set |
| 249 | CONFIG_INET=y | 290 | CONFIG_INET=y |
| 250 | # CONFIG_IP_MULTICAST is not set | 291 | # CONFIG_IP_MULTICAST is not set |
| @@ -263,33 +304,23 @@ CONFIG_IP_PNP_BOOTP=y | |||
| 263 | # CONFIG_INET_IPCOMP is not set | 304 | # CONFIG_INET_IPCOMP is not set |
| 264 | # CONFIG_INET_XFRM_TUNNEL is not set | 305 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 265 | # CONFIG_INET_TUNNEL is not set | 306 | # CONFIG_INET_TUNNEL is not set |
| 266 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 307 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 267 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 308 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 268 | CONFIG_INET_XFRM_MODE_BEET=y | 309 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 310 | # CONFIG_INET_LRO is not set | ||
| 269 | CONFIG_INET_DIAG=y | 311 | CONFIG_INET_DIAG=y |
| 270 | CONFIG_INET_TCP_DIAG=y | 312 | CONFIG_INET_TCP_DIAG=y |
| 271 | # CONFIG_TCP_CONG_ADVANCED is not set | 313 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 272 | CONFIG_TCP_CONG_CUBIC=y | 314 | CONFIG_TCP_CONG_CUBIC=y |
| 273 | CONFIG_DEFAULT_TCP_CONG="cubic" | 315 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 316 | # CONFIG_TCP_MD5SIG is not set | ||
| 274 | # CONFIG_IPV6 is not set | 317 | # CONFIG_IPV6 is not set |
| 275 | # CONFIG_INET6_XFRM_TUNNEL is not set | 318 | # CONFIG_INET6_XFRM_TUNNEL is not set |
| 276 | # CONFIG_INET6_TUNNEL is not set | 319 | # CONFIG_INET6_TUNNEL is not set |
| 277 | # CONFIG_NETWORK_SECMARK is not set | 320 | # CONFIG_NETWORK_SECMARK is not set |
| 278 | # CONFIG_NETFILTER is not set | 321 | # CONFIG_NETFILTER is not set |
| 279 | |||
| 280 | # | ||
| 281 | # DCCP Configuration (EXPERIMENTAL) | ||
| 282 | # | ||
| 283 | # CONFIG_IP_DCCP is not set | 322 | # CONFIG_IP_DCCP is not set |
| 284 | |||
| 285 | # | ||
| 286 | # SCTP Configuration (EXPERIMENTAL) | ||
| 287 | # | ||
| 288 | # CONFIG_IP_SCTP is not set | 323 | # CONFIG_IP_SCTP is not set |
| 289 | |||
| 290 | # | ||
| 291 | # TIPC Configuration (EXPERIMENTAL) | ||
| 292 | # | ||
| 293 | # CONFIG_TIPC is not set | 324 | # CONFIG_TIPC is not set |
| 294 | # CONFIG_ATM is not set | 325 | # CONFIG_ATM is not set |
| 295 | # CONFIG_BRIDGE is not set | 326 | # CONFIG_BRIDGE is not set |
| @@ -302,10 +333,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 302 | # CONFIG_LAPB is not set | 333 | # CONFIG_LAPB is not set |
| 303 | # CONFIG_ECONET is not set | 334 | # CONFIG_ECONET is not set |
| 304 | # CONFIG_WAN_ROUTER is not set | 335 | # CONFIG_WAN_ROUTER is not set |
| 305 | |||
| 306 | # | ||
| 307 | # QoS and/or fair queueing | ||
| 308 | # | ||
| 309 | # CONFIG_NET_SCHED is not set | 336 | # CONFIG_NET_SCHED is not set |
| 310 | 337 | ||
| 311 | # | 338 | # |
| @@ -315,7 +342,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 315 | # CONFIG_HAMRADIO is not set | 342 | # CONFIG_HAMRADIO is not set |
| 316 | # CONFIG_IRDA is not set | 343 | # CONFIG_IRDA is not set |
| 317 | # CONFIG_BT is not set | 344 | # CONFIG_BT is not set |
| 345 | # CONFIG_AF_RXRPC is not set | ||
| 346 | |||
| 347 | # | ||
| 348 | # Wireless | ||
| 349 | # | ||
| 350 | # CONFIG_CFG80211 is not set | ||
| 351 | # CONFIG_WIRELESS_EXT is not set | ||
| 352 | # CONFIG_MAC80211 is not set | ||
| 318 | # CONFIG_IEEE80211 is not set | 353 | # CONFIG_IEEE80211 is not set |
| 354 | # CONFIG_RFKILL is not set | ||
| 355 | # CONFIG_NET_9P is not set | ||
| 319 | 356 | ||
| 320 | # | 357 | # |
| 321 | # Device Drivers | 358 | # Device Drivers |
| @@ -324,34 +361,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 324 | # | 361 | # |
| 325 | # Generic Driver Options | 362 | # Generic Driver Options |
| 326 | # | 363 | # |
| 364 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 327 | CONFIG_STANDALONE=y | 365 | CONFIG_STANDALONE=y |
| 328 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 366 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 329 | # CONFIG_FW_LOADER is not set | 367 | # CONFIG_FW_LOADER is not set |
| 330 | # CONFIG_DEBUG_DRIVER is not set | 368 | # CONFIG_DEBUG_DRIVER is not set |
| 369 | # CONFIG_DEBUG_DEVRES is not set | ||
| 331 | # CONFIG_SYS_HYPERVISOR is not set | 370 | # CONFIG_SYS_HYPERVISOR is not set |
| 332 | |||
| 333 | # | ||
| 334 | # Connector - unified userspace <-> kernelspace linker | ||
| 335 | # | ||
| 336 | # CONFIG_CONNECTOR is not set | 371 | # CONFIG_CONNECTOR is not set |
| 337 | |||
| 338 | # | ||
| 339 | # Memory Technology Devices (MTD) | ||
| 340 | # | ||
| 341 | # CONFIG_MTD is not set | 372 | # CONFIG_MTD is not set |
| 342 | |||
| 343 | # | ||
| 344 | # Parallel port support | ||
| 345 | # | ||
| 346 | # CONFIG_PARPORT is not set | 373 | # CONFIG_PARPORT is not set |
| 347 | 374 | CONFIG_BLK_DEV=y | |
| 348 | # | ||
| 349 | # Plug and Play support | ||
| 350 | # | ||
| 351 | |||
| 352 | # | ||
| 353 | # Block devices | ||
| 354 | # | ||
| 355 | # CONFIG_BLK_DEV_COW_COMMON is not set | 375 | # CONFIG_BLK_DEV_COW_COMMON is not set |
| 356 | # CONFIG_BLK_DEV_LOOP is not set | 376 | # CONFIG_BLK_DEV_LOOP is not set |
| 357 | # CONFIG_BLK_DEV_NBD is not set | 377 | # CONFIG_BLK_DEV_NBD is not set |
| @@ -360,15 +380,19 @@ CONFIG_BLK_DEV_RAM=y | |||
| 360 | CONFIG_BLK_DEV_RAM_COUNT=16 | 380 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 361 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 381 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 362 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 382 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 |
| 363 | CONFIG_BLK_DEV_INITRD=y | ||
| 364 | # CONFIG_CDROM_PKTCDVD is not set | 383 | # CONFIG_CDROM_PKTCDVD is not set |
| 365 | # CONFIG_ATA_OVER_ETH is not set | 384 | # CONFIG_ATA_OVER_ETH is not set |
| 385 | CONFIG_MISC_DEVICES=y | ||
| 386 | # CONFIG_EEPROM_93CX6 is not set | ||
| 387 | CONFIG_ATMEL_SSC=y | ||
| 366 | 388 | ||
| 367 | # | 389 | # |
| 368 | # SCSI device support | 390 | # SCSI device support |
| 369 | # | 391 | # |
| 370 | # CONFIG_RAID_ATTRS is not set | 392 | # CONFIG_RAID_ATTRS is not set |
| 371 | CONFIG_SCSI=y | 393 | CONFIG_SCSI=y |
| 394 | CONFIG_SCSI_DMA=y | ||
| 395 | # CONFIG_SCSI_TGT is not set | ||
| 372 | # CONFIG_SCSI_NETLINK is not set | 396 | # CONFIG_SCSI_NETLINK is not set |
| 373 | CONFIG_SCSI_PROC_FS=y | 397 | CONFIG_SCSI_PROC_FS=y |
| 374 | 398 | ||
| @@ -388,6 +412,8 @@ CONFIG_BLK_DEV_SD=y | |||
| 388 | CONFIG_SCSI_MULTI_LUN=y | 412 | CONFIG_SCSI_MULTI_LUN=y |
| 389 | # CONFIG_SCSI_CONSTANTS is not set | 413 | # CONFIG_SCSI_CONSTANTS is not set |
| 390 | # CONFIG_SCSI_LOGGING is not set | 414 | # CONFIG_SCSI_LOGGING is not set |
| 415 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 416 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 391 | 417 | ||
| 392 | # | 418 | # |
| 393 | # SCSI Transports | 419 | # SCSI Transports |
| @@ -395,43 +421,72 @@ CONFIG_SCSI_MULTI_LUN=y | |||
| 395 | # CONFIG_SCSI_SPI_ATTRS is not set | 421 | # CONFIG_SCSI_SPI_ATTRS is not set |
| 396 | # CONFIG_SCSI_FC_ATTRS is not set | 422 | # CONFIG_SCSI_FC_ATTRS is not set |
| 397 | # CONFIG_SCSI_ISCSI_ATTRS is not set | 423 | # CONFIG_SCSI_ISCSI_ATTRS is not set |
| 398 | # CONFIG_SCSI_SAS_ATTRS is not set | ||
| 399 | # CONFIG_SCSI_SAS_LIBSAS is not set | 424 | # CONFIG_SCSI_SAS_LIBSAS is not set |
| 400 | 425 | # CONFIG_SCSI_SRP_ATTRS is not set | |
| 401 | # | 426 | CONFIG_SCSI_LOWLEVEL=y |
| 402 | # SCSI low-level drivers | ||
| 403 | # | ||
| 404 | # CONFIG_ISCSI_TCP is not set | 427 | # CONFIG_ISCSI_TCP is not set |
| 405 | # CONFIG_SCSI_DEBUG is not set | 428 | # CONFIG_SCSI_DEBUG is not set |
| 406 | 429 | # CONFIG_ATA is not set | |
| 407 | # | ||
| 408 | # Multi-device support (RAID and LVM) | ||
| 409 | # | ||
| 410 | # CONFIG_MD is not set | 430 | # CONFIG_MD is not set |
| 431 | CONFIG_NETDEVICES=y | ||
| 432 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 433 | # CONFIG_DUMMY is not set | ||
| 434 | # CONFIG_BONDING is not set | ||
| 435 | # CONFIG_MACVLAN is not set | ||
| 436 | # CONFIG_EQUALIZER is not set | ||
| 437 | # CONFIG_TUN is not set | ||
| 438 | # CONFIG_VETH is not set | ||
| 439 | CONFIG_PHYLIB=y | ||
| 440 | |||
| 441 | # | ||
| 442 | # MII PHY device drivers | ||
| 443 | # | ||
| 444 | # CONFIG_MARVELL_PHY is not set | ||
| 445 | # CONFIG_DAVICOM_PHY is not set | ||
| 446 | # CONFIG_QSEMI_PHY is not set | ||
| 447 | # CONFIG_LXT_PHY is not set | ||
| 448 | # CONFIG_CICADA_PHY is not set | ||
| 449 | # CONFIG_VITESSE_PHY is not set | ||
| 450 | # CONFIG_SMSC_PHY is not set | ||
| 451 | # CONFIG_BROADCOM_PHY is not set | ||
| 452 | # CONFIG_ICPLUS_PHY is not set | ||
| 453 | # CONFIG_FIXED_PHY is not set | ||
| 454 | # CONFIG_MDIO_BITBANG is not set | ||
| 455 | CONFIG_NET_ETHERNET=y | ||
| 456 | CONFIG_MII=y | ||
| 457 | CONFIG_MACB=y | ||
| 458 | # CONFIG_AX88796 is not set | ||
| 459 | # CONFIG_SMC91X is not set | ||
| 460 | # CONFIG_DM9000 is not set | ||
| 461 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 462 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 463 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 464 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 465 | # CONFIG_B44 is not set | ||
| 466 | CONFIG_NETDEV_1000=y | ||
| 467 | CONFIG_NETDEV_10000=y | ||
| 468 | |||
| 469 | # | ||
| 470 | # Wireless LAN | ||
| 471 | # | ||
| 472 | # CONFIG_WLAN_PRE80211 is not set | ||
| 473 | # CONFIG_WLAN_80211 is not set | ||
| 411 | 474 | ||
| 412 | # | 475 | # |
| 413 | # Fusion MPT device support | 476 | # USB Network Adapters |
| 414 | # | ||
| 415 | # CONFIG_FUSION is not set | ||
| 416 | |||
| 417 | # | ||
| 418 | # IEEE 1394 (FireWire) support | ||
| 419 | # | ||
| 420 | |||
| 421 | # | ||
| 422 | # I2O device support | ||
| 423 | # | ||
| 424 | |||
| 425 | # | ||
| 426 | # Network device support | ||
| 427 | # | 477 | # |
| 428 | # CONFIG_NETDEVICES is not set | 478 | # CONFIG_USB_CATC is not set |
| 479 | # CONFIG_USB_KAWETH is not set | ||
| 480 | # CONFIG_USB_PEGASUS is not set | ||
| 481 | # CONFIG_USB_RTL8150 is not set | ||
| 482 | # CONFIG_USB_USBNET is not set | ||
| 483 | # CONFIG_WAN is not set | ||
| 484 | # CONFIG_PPP is not set | ||
| 485 | # CONFIG_SLIP is not set | ||
| 486 | # CONFIG_SHAPER is not set | ||
| 487 | # CONFIG_NETCONSOLE is not set | ||
| 429 | # CONFIG_NETPOLL is not set | 488 | # CONFIG_NETPOLL is not set |
| 430 | # CONFIG_NET_POLL_CONTROLLER is not set | 489 | # CONFIG_NET_POLL_CONTROLLER is not set |
| 431 | |||
| 432 | # | ||
| 433 | # ISDN subsystem | ||
| 434 | # | ||
| 435 | # CONFIG_ISDN is not set | 490 | # CONFIG_ISDN is not set |
| 436 | 491 | ||
| 437 | # | 492 | # |
| @@ -439,6 +494,7 @@ CONFIG_SCSI_MULTI_LUN=y | |||
| 439 | # | 494 | # |
| 440 | CONFIG_INPUT=y | 495 | CONFIG_INPUT=y |
| 441 | # CONFIG_INPUT_FF_MEMLESS is not set | 496 | # CONFIG_INPUT_FF_MEMLESS is not set |
| 497 | # CONFIG_INPUT_POLLDEV is not set | ||
| 442 | 498 | ||
| 443 | # | 499 | # |
| 444 | # Userland interfaces | 500 | # Userland interfaces |
| @@ -448,7 +504,6 @@ CONFIG_INPUT_MOUSEDEV=y | |||
| 448 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | 504 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 |
| 449 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | 505 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 |
| 450 | # CONFIG_INPUT_JOYDEV is not set | 506 | # CONFIG_INPUT_JOYDEV is not set |
| 451 | # CONFIG_INPUT_TSDEV is not set | ||
| 452 | # CONFIG_INPUT_EVDEV is not set | 507 | # CONFIG_INPUT_EVDEV is not set |
| 453 | # CONFIG_INPUT_EVBUG is not set | 508 | # CONFIG_INPUT_EVBUG is not set |
| 454 | 509 | ||
| @@ -458,6 +513,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | |||
| 458 | # CONFIG_INPUT_KEYBOARD is not set | 513 | # CONFIG_INPUT_KEYBOARD is not set |
| 459 | # CONFIG_INPUT_MOUSE is not set | 514 | # CONFIG_INPUT_MOUSE is not set |
| 460 | # CONFIG_INPUT_JOYSTICK is not set | 515 | # CONFIG_INPUT_JOYSTICK is not set |
| 516 | # CONFIG_INPUT_TABLET is not set | ||
| 461 | # CONFIG_INPUT_TOUCHSCREEN is not set | 517 | # CONFIG_INPUT_TOUCHSCREEN is not set |
| 462 | # CONFIG_INPUT_MISC is not set | 518 | # CONFIG_INPUT_MISC is not set |
| 463 | 519 | ||
| @@ -492,114 +548,131 @@ CONFIG_SERIAL_CORE_CONSOLE=y | |||
| 492 | CONFIG_UNIX98_PTYS=y | 548 | CONFIG_UNIX98_PTYS=y |
| 493 | CONFIG_LEGACY_PTYS=y | 549 | CONFIG_LEGACY_PTYS=y |
| 494 | CONFIG_LEGACY_PTY_COUNT=256 | 550 | CONFIG_LEGACY_PTY_COUNT=256 |
| 495 | |||
| 496 | # | ||
| 497 | # IPMI | ||
| 498 | # | ||
| 499 | # CONFIG_IPMI_HANDLER is not set | 551 | # CONFIG_IPMI_HANDLER is not set |
| 500 | 552 | # CONFIG_HW_RANDOM is not set | |
| 501 | # | ||
| 502 | # Watchdog Cards | ||
| 503 | # | ||
| 504 | CONFIG_WATCHDOG=y | ||
| 505 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 506 | |||
| 507 | # | ||
| 508 | # Watchdog Device Drivers | ||
| 509 | # | ||
| 510 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 511 | |||
| 512 | # | ||
| 513 | # USB-based Watchdog Cards | ||
| 514 | # | ||
| 515 | # CONFIG_USBPCWATCHDOG is not set | ||
| 516 | CONFIG_HW_RANDOM=y | ||
| 517 | # CONFIG_NVRAM is not set | 553 | # CONFIG_NVRAM is not set |
| 518 | # CONFIG_DTLK is not set | ||
| 519 | # CONFIG_R3964 is not set | 554 | # CONFIG_R3964 is not set |
| 555 | # CONFIG_RAW_DRIVER is not set | ||
| 556 | # CONFIG_TCG_TPM is not set | ||
| 557 | CONFIG_I2C=y | ||
| 558 | CONFIG_I2C_BOARDINFO=y | ||
| 559 | CONFIG_I2C_CHARDEV=y | ||
| 520 | 560 | ||
| 521 | # | 561 | # |
| 522 | # Ftape, the floppy tape device driver | 562 | # I2C Algorithms |
| 523 | # | 563 | # |
| 524 | # CONFIG_RAW_DRIVER is not set | 564 | CONFIG_I2C_ALGOBIT=y |
| 565 | # CONFIG_I2C_ALGOPCF is not set | ||
| 566 | # CONFIG_I2C_ALGOPCA is not set | ||
| 525 | 567 | ||
| 526 | # | 568 | # |
| 527 | # TPM devices | 569 | # I2C Hardware Bus support |
| 528 | # | 570 | # |
| 529 | # CONFIG_TCG_TPM is not set | 571 | CONFIG_I2C_GPIO=y |
| 572 | # CONFIG_I2C_OCORES is not set | ||
| 573 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 574 | # CONFIG_I2C_SIMTEC is not set | ||
| 575 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 576 | # CONFIG_I2C_STUB is not set | ||
| 577 | # CONFIG_I2C_TINY_USB is not set | ||
| 578 | # CONFIG_I2C_PCA is not set | ||
| 530 | 579 | ||
| 531 | # | 580 | # |
| 532 | # I2C support | 581 | # Miscellaneous I2C Chip support |
| 533 | # | 582 | # |
| 534 | # CONFIG_I2C is not set | 583 | # CONFIG_SENSORS_DS1337 is not set |
| 584 | # CONFIG_SENSORS_DS1374 is not set | ||
| 585 | # CONFIG_DS1682 is not set | ||
| 586 | # CONFIG_SENSORS_EEPROM is not set | ||
| 587 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 588 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 589 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 590 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 591 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 592 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 593 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 594 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 595 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 535 | 596 | ||
| 536 | # | 597 | # |
| 537 | # SPI support | 598 | # SPI support |
| 538 | # | 599 | # |
| 539 | # CONFIG_SPI is not set | 600 | # CONFIG_SPI is not set |
| 540 | # CONFIG_SPI_MASTER is not set | 601 | # CONFIG_SPI_MASTER is not set |
| 541 | |||
| 542 | # | ||
| 543 | # Dallas's 1-wire bus | ||
| 544 | # | ||
| 545 | # CONFIG_W1 is not set | 602 | # CONFIG_W1 is not set |
| 546 | 603 | # CONFIG_POWER_SUPPLY is not set | |
| 547 | # | ||
| 548 | # Hardware Monitoring support | ||
| 549 | # | ||
| 550 | # CONFIG_HWMON is not set | 604 | # CONFIG_HWMON is not set |
| 551 | # CONFIG_HWMON_VID is not set | 605 | CONFIG_WATCHDOG=y |
| 606 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 552 | 607 | ||
| 553 | # | 608 | # |
| 554 | # Misc devices | 609 | # Watchdog Device Drivers |
| 555 | # | 610 | # |
| 556 | # CONFIG_TIFM_CORE is not set | 611 | # CONFIG_SOFT_WATCHDOG is not set |
| 612 | CONFIG_AT91SAM9_WATCHDOG=y | ||
| 557 | 613 | ||
| 558 | # | 614 | # |
| 559 | # LED devices | 615 | # USB-based Watchdog Cards |
| 560 | # | 616 | # |
| 561 | # CONFIG_NEW_LEDS is not set | 617 | # CONFIG_USBPCWATCHDOG is not set |
| 562 | 618 | ||
| 563 | # | 619 | # |
| 564 | # LED drivers | 620 | # Sonics Silicon Backplane |
| 565 | # | 621 | # |
| 622 | CONFIG_SSB_POSSIBLE=y | ||
| 623 | # CONFIG_SSB is not set | ||
| 566 | 624 | ||
| 567 | # | 625 | # |
| 568 | # LED Triggers | 626 | # Multifunction device drivers |
| 569 | # | 627 | # |
| 628 | # CONFIG_MFD_SM501 is not set | ||
| 570 | 629 | ||
| 571 | # | 630 | # |
| 572 | # Multimedia devices | 631 | # Multimedia devices |
| 573 | # | 632 | # |
| 574 | # CONFIG_VIDEO_DEV is not set | 633 | # CONFIG_VIDEO_DEV is not set |
| 634 | # CONFIG_DVB_CORE is not set | ||
| 635 | # CONFIG_DAB is not set | ||
| 575 | 636 | ||
| 576 | # | 637 | # |
| 577 | # Digital Video Broadcasting Devices | 638 | # Graphics support |
| 578 | # | 639 | # |
| 579 | # CONFIG_DVB is not set | 640 | # CONFIG_VGASTATE is not set |
| 580 | # CONFIG_USB_DABUSB is not set | 641 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set |
| 642 | # CONFIG_FB is not set | ||
| 643 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 581 | 644 | ||
| 582 | # | 645 | # |
| 583 | # Graphics support | 646 | # Display device support |
| 584 | # | 647 | # |
| 585 | # CONFIG_FIRMWARE_EDID is not set | 648 | # CONFIG_DISPLAY_SUPPORT is not set |
| 586 | # CONFIG_FB is not set | ||
| 587 | 649 | ||
| 588 | # | 650 | # |
| 589 | # Console display driver support | 651 | # Console display driver support |
| 590 | # | 652 | # |
| 591 | # CONFIG_VGA_CONSOLE is not set | 653 | # CONFIG_VGA_CONSOLE is not set |
| 592 | CONFIG_DUMMY_CONSOLE=y | 654 | CONFIG_DUMMY_CONSOLE=y |
| 593 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 594 | 655 | ||
| 595 | # | 656 | # |
| 596 | # Sound | 657 | # Sound |
| 597 | # | 658 | # |
| 598 | # CONFIG_SOUND is not set | 659 | # CONFIG_SOUND is not set |
| 660 | CONFIG_HID_SUPPORT=y | ||
| 661 | CONFIG_HID=y | ||
| 662 | # CONFIG_HID_DEBUG is not set | ||
| 663 | # CONFIG_HIDRAW is not set | ||
| 599 | 664 | ||
| 600 | # | 665 | # |
| 601 | # USB support | 666 | # USB Input Devices |
| 602 | # | 667 | # |
| 668 | # CONFIG_USB_HID is not set | ||
| 669 | |||
| 670 | # | ||
| 671 | # USB HID Boot Protocol drivers | ||
| 672 | # | ||
| 673 | # CONFIG_USB_KBD is not set | ||
| 674 | # CONFIG_USB_MOUSE is not set | ||
| 675 | CONFIG_USB_SUPPORT=y | ||
| 603 | CONFIG_USB_ARCH_HAS_HCD=y | 676 | CONFIG_USB_ARCH_HAS_HCD=y |
| 604 | CONFIG_USB_ARCH_HAS_OHCI=y | 677 | CONFIG_USB_ARCH_HAS_OHCI=y |
| 605 | # CONFIG_USB_ARCH_HAS_EHCI is not set | 678 | # CONFIG_USB_ARCH_HAS_EHCI is not set |
| @@ -610,7 +683,7 @@ CONFIG_USB=y | |||
| 610 | # Miscellaneous USB options | 683 | # Miscellaneous USB options |
| 611 | # | 684 | # |
| 612 | CONFIG_USB_DEVICEFS=y | 685 | CONFIG_USB_DEVICEFS=y |
| 613 | # CONFIG_USB_BANDWIDTH is not set | 686 | CONFIG_USB_DEVICE_CLASS=y |
| 614 | # CONFIG_USB_DYNAMIC_MINORS is not set | 687 | # CONFIG_USB_DYNAMIC_MINORS is not set |
| 615 | # CONFIG_USB_OTG is not set | 688 | # CONFIG_USB_OTG is not set |
| 616 | 689 | ||
| @@ -619,9 +692,11 @@ CONFIG_USB_DEVICEFS=y | |||
| 619 | # | 692 | # |
| 620 | # CONFIG_USB_ISP116X_HCD is not set | 693 | # CONFIG_USB_ISP116X_HCD is not set |
| 621 | CONFIG_USB_OHCI_HCD=y | 694 | CONFIG_USB_OHCI_HCD=y |
| 622 | # CONFIG_USB_OHCI_BIG_ENDIAN is not set | 695 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set |
| 696 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 623 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | 697 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y |
| 624 | # CONFIG_USB_SL811_HCD is not set | 698 | # CONFIG_USB_SL811_HCD is not set |
| 699 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 625 | 700 | ||
| 626 | # | 701 | # |
| 627 | # USB Device Class drivers | 702 | # USB Device Class drivers |
| @@ -640,6 +715,7 @@ CONFIG_USB_STORAGE=y | |||
| 640 | CONFIG_USB_STORAGE_DEBUG=y | 715 | CONFIG_USB_STORAGE_DEBUG=y |
| 641 | # CONFIG_USB_STORAGE_DATAFAB is not set | 716 | # CONFIG_USB_STORAGE_DATAFAB is not set |
| 642 | # CONFIG_USB_STORAGE_FREECOM is not set | 717 | # CONFIG_USB_STORAGE_FREECOM is not set |
| 718 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 643 | # CONFIG_USB_STORAGE_DPCM is not set | 719 | # CONFIG_USB_STORAGE_DPCM is not set |
| 644 | # CONFIG_USB_STORAGE_USBAT is not set | 720 | # CONFIG_USB_STORAGE_USBAT is not set |
| 645 | # CONFIG_USB_STORAGE_SDDR09 is not set | 721 | # CONFIG_USB_STORAGE_SDDR09 is not set |
| @@ -650,43 +726,10 @@ CONFIG_USB_STORAGE_DEBUG=y | |||
| 650 | # CONFIG_USB_LIBUSUAL is not set | 726 | # CONFIG_USB_LIBUSUAL is not set |
| 651 | 727 | ||
| 652 | # | 728 | # |
| 653 | # USB Input Devices | ||
| 654 | # | ||
| 655 | # CONFIG_USB_HID is not set | ||
| 656 | |||
| 657 | # | ||
| 658 | # USB HID Boot Protocol drivers | ||
| 659 | # | ||
| 660 | # CONFIG_USB_KBD is not set | ||
| 661 | # CONFIG_USB_MOUSE is not set | ||
| 662 | # CONFIG_USB_AIPTEK is not set | ||
| 663 | # CONFIG_USB_WACOM is not set | ||
| 664 | # CONFIG_USB_ACECAD is not set | ||
| 665 | # CONFIG_USB_KBTAB is not set | ||
| 666 | # CONFIG_USB_POWERMATE is not set | ||
| 667 | # CONFIG_USB_TOUCHSCREEN is not set | ||
| 668 | # CONFIG_USB_YEALINK is not set | ||
| 669 | # CONFIG_USB_XPAD is not set | ||
| 670 | # CONFIG_USB_ATI_REMOTE is not set | ||
| 671 | # CONFIG_USB_ATI_REMOTE2 is not set | ||
| 672 | # CONFIG_USB_KEYSPAN_REMOTE is not set | ||
| 673 | # CONFIG_USB_APPLETOUCH is not set | ||
| 674 | |||
| 675 | # | ||
| 676 | # USB Imaging devices | 729 | # USB Imaging devices |
| 677 | # | 730 | # |
| 678 | # CONFIG_USB_MDC800 is not set | 731 | # CONFIG_USB_MDC800 is not set |
| 679 | # CONFIG_USB_MICROTEK is not set | 732 | # CONFIG_USB_MICROTEK is not set |
| 680 | |||
| 681 | # | ||
| 682 | # USB Network Adapters | ||
| 683 | # | ||
| 684 | # CONFIG_USB_CATC is not set | ||
| 685 | # CONFIG_USB_KAWETH is not set | ||
| 686 | # CONFIG_USB_PEGASUS is not set | ||
| 687 | # CONFIG_USB_RTL8150 is not set | ||
| 688 | # CONFIG_USB_USBNET_MII is not set | ||
| 689 | # CONFIG_USB_USBNET is not set | ||
| 690 | CONFIG_USB_MON=y | 733 | CONFIG_USB_MON=y |
| 691 | 734 | ||
| 692 | # | 735 | # |
| @@ -708,6 +751,7 @@ CONFIG_USB_MON=y | |||
| 708 | # CONFIG_USB_RIO500 is not set | 751 | # CONFIG_USB_RIO500 is not set |
| 709 | # CONFIG_USB_LEGOTOWER is not set | 752 | # CONFIG_USB_LEGOTOWER is not set |
| 710 | # CONFIG_USB_LCD is not set | 753 | # CONFIG_USB_LCD is not set |
| 754 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 711 | # CONFIG_USB_LED is not set | 755 | # CONFIG_USB_LED is not set |
| 712 | # CONFIG_USB_CYPRESS_CY7C63 is not set | 756 | # CONFIG_USB_CYPRESS_CY7C63 is not set |
| 713 | # CONFIG_USB_CYTHERM is not set | 757 | # CONFIG_USB_CYTHERM is not set |
| @@ -717,6 +761,7 @@ CONFIG_USB_MON=y | |||
| 717 | # CONFIG_USB_APPLEDISPLAY is not set | 761 | # CONFIG_USB_APPLEDISPLAY is not set |
| 718 | # CONFIG_USB_LD is not set | 762 | # CONFIG_USB_LD is not set |
| 719 | # CONFIG_USB_TRANCEVIBRATOR is not set | 763 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 764 | # CONFIG_USB_IOWARRIOR is not set | ||
| 720 | # CONFIG_USB_TEST is not set | 765 | # CONFIG_USB_TEST is not set |
| 721 | 766 | ||
| 722 | # | 767 | # |
| @@ -727,13 +772,19 @@ CONFIG_USB_MON=y | |||
| 727 | # USB Gadget Support | 772 | # USB Gadget Support |
| 728 | # | 773 | # |
| 729 | CONFIG_USB_GADGET=y | 774 | CONFIG_USB_GADGET=y |
| 775 | # CONFIG_USB_GADGET_DEBUG is not set | ||
| 730 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | 776 | # CONFIG_USB_GADGET_DEBUG_FILES is not set |
| 731 | CONFIG_USB_GADGET_SELECTED=y | 777 | CONFIG_USB_GADGET_SELECTED=y |
| 778 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 779 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 780 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 732 | # CONFIG_USB_GADGET_NET2280 is not set | 781 | # CONFIG_USB_GADGET_NET2280 is not set |
| 733 | # CONFIG_USB_GADGET_PXA2XX is not set | 782 | # CONFIG_USB_GADGET_PXA2XX is not set |
| 783 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 734 | # CONFIG_USB_GADGET_GOKU is not set | 784 | # CONFIG_USB_GADGET_GOKU is not set |
| 735 | # CONFIG_USB_GADGET_LH7A40X is not set | 785 | # CONFIG_USB_GADGET_LH7A40X is not set |
| 736 | # CONFIG_USB_GADGET_OMAP is not set | 786 | # CONFIG_USB_GADGET_OMAP is not set |
| 787 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 737 | CONFIG_USB_GADGET_AT91=y | 788 | CONFIG_USB_GADGET_AT91=y |
| 738 | CONFIG_USB_AT91=y | 789 | CONFIG_USB_AT91=y |
| 739 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | 790 | # CONFIG_USB_GADGET_DUMMY_HCD is not set |
| @@ -745,17 +796,56 @@ CONFIG_USB_FILE_STORAGE=m | |||
| 745 | # CONFIG_USB_FILE_STORAGE_TEST is not set | 796 | # CONFIG_USB_FILE_STORAGE_TEST is not set |
| 746 | CONFIG_USB_G_SERIAL=m | 797 | CONFIG_USB_G_SERIAL=m |
| 747 | # CONFIG_USB_MIDI_GADGET is not set | 798 | # CONFIG_USB_MIDI_GADGET is not set |
| 799 | # CONFIG_MMC is not set | ||
| 800 | # CONFIG_NEW_LEDS is not set | ||
| 801 | CONFIG_RTC_LIB=y | ||
| 802 | CONFIG_RTC_CLASS=y | ||
| 803 | CONFIG_RTC_HCTOSYS=y | ||
| 804 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 805 | # CONFIG_RTC_DEBUG is not set | ||
| 748 | 806 | ||
| 749 | # | 807 | # |
| 750 | # MMC/SD Card support | 808 | # RTC interfaces |
| 751 | # | 809 | # |
| 752 | # CONFIG_MMC is not set | 810 | CONFIG_RTC_INTF_SYSFS=y |
| 811 | CONFIG_RTC_INTF_PROC=y | ||
| 812 | CONFIG_RTC_INTF_DEV=y | ||
| 813 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 814 | # CONFIG_RTC_DRV_TEST is not set | ||
| 753 | 815 | ||
| 754 | # | 816 | # |
| 755 | # Real Time Clock | 817 | # I2C RTC drivers |
| 818 | # | ||
| 819 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 820 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 821 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 822 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 823 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 824 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 825 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 826 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 827 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 828 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 829 | |||
| 830 | # | ||
| 831 | # SPI RTC drivers | ||
| 756 | # | 832 | # |
| 757 | CONFIG_RTC_LIB=y | 833 | |
| 758 | # CONFIG_RTC_CLASS is not set | 834 | # |
| 835 | # Platform RTC drivers | ||
| 836 | # | ||
| 837 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 838 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 839 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 840 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 841 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 842 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 843 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 844 | |||
| 845 | # | ||
| 846 | # on-CPU RTC drivers | ||
| 847 | # | ||
| 848 | CONFIG_RTC_DRV_AT91SAM9=y | ||
| 759 | 849 | ||
| 760 | # | 850 | # |
| 761 | # File systems | 851 | # File systems |
| @@ -806,7 +896,6 @@ CONFIG_SYSFS=y | |||
| 806 | CONFIG_TMPFS=y | 896 | CONFIG_TMPFS=y |
| 807 | # CONFIG_TMPFS_POSIX_ACL is not set | 897 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 808 | # CONFIG_HUGETLB_PAGE is not set | 898 | # CONFIG_HUGETLB_PAGE is not set |
| 809 | CONFIG_RAMFS=y | ||
| 810 | # CONFIG_CONFIGFS_FS is not set | 899 | # CONFIG_CONFIGFS_FS is not set |
| 811 | 900 | ||
| 812 | # | 901 | # |
| @@ -825,10 +914,7 @@ CONFIG_CRAMFS=y | |||
| 825 | # CONFIG_QNX4FS_FS is not set | 914 | # CONFIG_QNX4FS_FS is not set |
| 826 | # CONFIG_SYSV_FS is not set | 915 | # CONFIG_SYSV_FS is not set |
| 827 | # CONFIG_UFS_FS is not set | 916 | # CONFIG_UFS_FS is not set |
| 828 | 917 | CONFIG_NETWORK_FILESYSTEMS=y | |
| 829 | # | ||
| 830 | # Network File Systems | ||
| 831 | # | ||
| 832 | # CONFIG_NFS_FS is not set | 918 | # CONFIG_NFS_FS is not set |
| 833 | # CONFIG_NFSD is not set | 919 | # CONFIG_NFSD is not set |
| 834 | # CONFIG_SMB_FS is not set | 920 | # CONFIG_SMB_FS is not set |
| @@ -836,17 +922,12 @@ CONFIG_CRAMFS=y | |||
| 836 | # CONFIG_NCP_FS is not set | 922 | # CONFIG_NCP_FS is not set |
| 837 | # CONFIG_CODA_FS is not set | 923 | # CONFIG_CODA_FS is not set |
| 838 | # CONFIG_AFS_FS is not set | 924 | # CONFIG_AFS_FS is not set |
| 839 | # CONFIG_9P_FS is not set | ||
| 840 | 925 | ||
| 841 | # | 926 | # |
| 842 | # Partition Types | 927 | # Partition Types |
| 843 | # | 928 | # |
| 844 | # CONFIG_PARTITION_ADVANCED is not set | 929 | # CONFIG_PARTITION_ADVANCED is not set |
| 845 | CONFIG_MSDOS_PARTITION=y | 930 | CONFIG_MSDOS_PARTITION=y |
| 846 | |||
| 847 | # | ||
| 848 | # Native Language Support | ||
| 849 | # | ||
| 850 | CONFIG_NLS=y | 931 | CONFIG_NLS=y |
| 851 | CONFIG_NLS_DEFAULT="iso8859-1" | 932 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 852 | CONFIG_NLS_CODEPAGE_437=y | 933 | CONFIG_NLS_CODEPAGE_437=y |
| @@ -887,41 +968,49 @@ CONFIG_NLS_ISO8859_1=y | |||
| 887 | # CONFIG_NLS_KOI8_R is not set | 968 | # CONFIG_NLS_KOI8_R is not set |
| 888 | # CONFIG_NLS_KOI8_U is not set | 969 | # CONFIG_NLS_KOI8_U is not set |
| 889 | # CONFIG_NLS_UTF8 is not set | 970 | # CONFIG_NLS_UTF8 is not set |
| 890 | 971 | # CONFIG_DLM is not set | |
| 891 | # | 972 | CONFIG_INSTRUMENTATION=y |
| 892 | # Profiling support | ||
| 893 | # | ||
| 894 | # CONFIG_PROFILING is not set | 973 | # CONFIG_PROFILING is not set |
| 974 | # CONFIG_MARKERS is not set | ||
| 895 | 975 | ||
| 896 | # | 976 | # |
| 897 | # Kernel hacking | 977 | # Kernel hacking |
| 898 | # | 978 | # |
| 899 | # CONFIG_PRINTK_TIME is not set | 979 | # CONFIG_PRINTK_TIME is not set |
| 980 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 900 | CONFIG_ENABLE_MUST_CHECK=y | 981 | CONFIG_ENABLE_MUST_CHECK=y |
| 901 | # CONFIG_MAGIC_SYSRQ is not set | 982 | # CONFIG_MAGIC_SYSRQ is not set |
| 902 | # CONFIG_UNUSED_SYMBOLS is not set | 983 | # CONFIG_UNUSED_SYMBOLS is not set |
| 984 | # CONFIG_DEBUG_FS is not set | ||
| 985 | # CONFIG_HEADERS_CHECK is not set | ||
| 903 | CONFIG_DEBUG_KERNEL=y | 986 | CONFIG_DEBUG_KERNEL=y |
| 904 | CONFIG_LOG_BUF_SHIFT=14 | 987 | # CONFIG_DEBUG_SHIRQ is not set |
| 905 | CONFIG_DETECT_SOFTLOCKUP=y | 988 | CONFIG_DETECT_SOFTLOCKUP=y |
| 989 | CONFIG_SCHED_DEBUG=y | ||
| 906 | # CONFIG_SCHEDSTATS is not set | 990 | # CONFIG_SCHEDSTATS is not set |
| 991 | # CONFIG_TIMER_STATS is not set | ||
| 907 | # CONFIG_DEBUG_SLAB is not set | 992 | # CONFIG_DEBUG_SLAB is not set |
| 908 | # CONFIG_DEBUG_RT_MUTEXES is not set | 993 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| 909 | # CONFIG_RT_MUTEX_TESTER is not set | 994 | # CONFIG_RT_MUTEX_TESTER is not set |
| 910 | # CONFIG_DEBUG_SPINLOCK is not set | 995 | # CONFIG_DEBUG_SPINLOCK is not set |
| 911 | # CONFIG_DEBUG_MUTEXES is not set | 996 | # CONFIG_DEBUG_MUTEXES is not set |
| 912 | # CONFIG_DEBUG_RWSEMS is not set | 997 | # CONFIG_DEBUG_LOCK_ALLOC is not set |
| 998 | # CONFIG_PROVE_LOCKING is not set | ||
| 999 | # CONFIG_LOCK_STAT is not set | ||
| 913 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1000 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 914 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | 1001 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set |
| 915 | # CONFIG_DEBUG_KOBJECT is not set | 1002 | # CONFIG_DEBUG_KOBJECT is not set |
| 916 | CONFIG_DEBUG_BUGVERBOSE=y | 1003 | CONFIG_DEBUG_BUGVERBOSE=y |
| 917 | # CONFIG_DEBUG_INFO is not set | 1004 | # CONFIG_DEBUG_INFO is not set |
| 918 | # CONFIG_DEBUG_FS is not set | ||
| 919 | # CONFIG_DEBUG_VM is not set | 1005 | # CONFIG_DEBUG_VM is not set |
| 920 | # CONFIG_DEBUG_LIST is not set | 1006 | # CONFIG_DEBUG_LIST is not set |
| 1007 | # CONFIG_DEBUG_SG is not set | ||
| 921 | CONFIG_FRAME_POINTER=y | 1008 | CONFIG_FRAME_POINTER=y |
| 922 | CONFIG_FORCED_INLINING=y | 1009 | CONFIG_FORCED_INLINING=y |
| 923 | # CONFIG_HEADERS_CHECK is not set | 1010 | # CONFIG_BOOT_PRINTK_DELAY is not set |
| 924 | # CONFIG_RCU_TORTURE_TEST is not set | 1011 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1012 | # CONFIG_FAULT_INJECTION is not set | ||
| 1013 | # CONFIG_SAMPLES is not set | ||
| 925 | CONFIG_DEBUG_USER=y | 1014 | CONFIG_DEBUG_USER=y |
| 926 | # CONFIG_DEBUG_ERRORS is not set | 1015 | # CONFIG_DEBUG_ERRORS is not set |
| 927 | CONFIG_DEBUG_LL=y | 1016 | CONFIG_DEBUG_LL=y |
| @@ -932,18 +1021,21 @@ CONFIG_DEBUG_LL=y | |||
| 932 | # | 1021 | # |
| 933 | # CONFIG_KEYS is not set | 1022 | # CONFIG_KEYS is not set |
| 934 | # CONFIG_SECURITY is not set | 1023 | # CONFIG_SECURITY is not set |
| 935 | 1024 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | |
| 936 | # | ||
| 937 | # Cryptographic options | ||
| 938 | # | ||
| 939 | # CONFIG_CRYPTO is not set | 1025 | # CONFIG_CRYPTO is not set |
| 940 | 1026 | ||
| 941 | # | 1027 | # |
| 942 | # Library routines | 1028 | # Library routines |
| 943 | # | 1029 | # |
| 1030 | CONFIG_BITREVERSE=y | ||
| 944 | # CONFIG_CRC_CCITT is not set | 1031 | # CONFIG_CRC_CCITT is not set |
| 945 | # CONFIG_CRC16 is not set | 1032 | # CONFIG_CRC16 is not set |
| 1033 | # CONFIG_CRC_ITU_T is not set | ||
| 946 | CONFIG_CRC32=y | 1034 | CONFIG_CRC32=y |
| 1035 | # CONFIG_CRC7 is not set | ||
| 947 | # CONFIG_LIBCRC32C is not set | 1036 | # CONFIG_LIBCRC32C is not set |
| 948 | CONFIG_ZLIB_INFLATE=y | 1037 | CONFIG_ZLIB_INFLATE=y |
| 949 | CONFIG_PLIST=y | 1038 | CONFIG_PLIST=y |
| 1039 | CONFIG_HAS_IOMEM=y | ||
| 1040 | CONFIG_HAS_IOPORT=y | ||
| 1041 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/at91sam9261ek_defconfig b/arch/arm/configs/at91sam9261ek_defconfig index fcd8fa091e9d..3802e85f7483 100644 --- a/arch/arm/configs/at91sam9261ek_defconfig +++ b/arch/arm/configs/at91sam9261ek_defconfig | |||
| @@ -1,43 +1,56 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.19-rc6 | 3 | # Linux kernel version: 2.6.24-rc7 |
| 4 | # Fri Nov 17 18:00:38 2006 | 4 | # Tue Jan 8 22:21:49 2008 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 7 | # CONFIG_GENERIC_TIME is not set | 9 | # CONFIG_GENERIC_TIME is not set |
| 10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
| 8 | CONFIG_MMU=y | 11 | CONFIG_MMU=y |
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 9 | CONFIG_GENERIC_HARDIRQS=y | 13 | CONFIG_GENERIC_HARDIRQS=y |
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 10 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y |
| 11 | CONFIG_HARDIRQS_SW_RESEND=y | 17 | CONFIG_HARDIRQS_SW_RESEND=y |
| 12 | CONFIG_GENERIC_IRQ_PROBE=y | 18 | CONFIG_GENERIC_IRQ_PROBE=y |
| 13 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 20 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 14 | CONFIG_GENERIC_HWEIGHT=y | 22 | CONFIG_GENERIC_HWEIGHT=y |
| 15 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 24 | CONFIG_ZONE_DMA=y | ||
| 16 | CONFIG_VECTORS_BASE=0xffff0000 | 25 | CONFIG_VECTORS_BASE=0xffff0000 |
| 17 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 26 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 18 | 27 | ||
| 19 | # | 28 | # |
| 20 | # Code maturity level options | 29 | # General setup |
| 21 | # | 30 | # |
| 22 | CONFIG_EXPERIMENTAL=y | 31 | CONFIG_EXPERIMENTAL=y |
| 23 | CONFIG_BROKEN_ON_SMP=y | 32 | CONFIG_BROKEN_ON_SMP=y |
| 24 | CONFIG_INIT_ENV_ARG_LIMIT=32 | 33 | CONFIG_INIT_ENV_ARG_LIMIT=32 |
| 25 | |||
| 26 | # | ||
| 27 | # General setup | ||
| 28 | # | ||
| 29 | CONFIG_LOCALVERSION="" | 34 | CONFIG_LOCALVERSION="" |
| 30 | # CONFIG_LOCALVERSION_AUTO is not set | 35 | # CONFIG_LOCALVERSION_AUTO is not set |
| 31 | # CONFIG_SWAP is not set | 36 | # CONFIG_SWAP is not set |
| 32 | CONFIG_SYSVIPC=y | 37 | CONFIG_SYSVIPC=y |
| 33 | # CONFIG_IPC_NS is not set | 38 | CONFIG_SYSVIPC_SYSCTL=y |
| 34 | # CONFIG_POSIX_MQUEUE is not set | 39 | # CONFIG_POSIX_MQUEUE is not set |
| 35 | # CONFIG_BSD_PROCESS_ACCT is not set | 40 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 36 | # CONFIG_TASKSTATS is not set | 41 | # CONFIG_TASKSTATS is not set |
| 37 | # CONFIG_UTS_NS is not set | 42 | # CONFIG_USER_NS is not set |
| 43 | # CONFIG_PID_NS is not set | ||
| 38 | # CONFIG_AUDIT is not set | 44 | # CONFIG_AUDIT is not set |
| 39 | # CONFIG_IKCONFIG is not set | 45 | # CONFIG_IKCONFIG is not set |
| 46 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 47 | # CONFIG_CGROUPS is not set | ||
| 48 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 49 | CONFIG_FAIR_USER_SCHED=y | ||
| 50 | # CONFIG_FAIR_CGROUP_SCHED is not set | ||
| 51 | CONFIG_SYSFS_DEPRECATED=y | ||
| 40 | # CONFIG_RELAY is not set | 52 | # CONFIG_RELAY is not set |
| 53 | CONFIG_BLK_DEV_INITRD=y | ||
| 41 | CONFIG_INITRAMFS_SOURCE="" | 54 | CONFIG_INITRAMFS_SOURCE="" |
| 42 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 55 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 43 | CONFIG_SYSCTL=y | 56 | CONFIG_SYSCTL=y |
| @@ -53,30 +66,30 @@ CONFIG_BUG=y | |||
| 53 | CONFIG_ELF_CORE=y | 66 | CONFIG_ELF_CORE=y |
| 54 | CONFIG_BASE_FULL=y | 67 | CONFIG_BASE_FULL=y |
| 55 | CONFIG_FUTEX=y | 68 | CONFIG_FUTEX=y |
| 69 | CONFIG_ANON_INODES=y | ||
| 56 | CONFIG_EPOLL=y | 70 | CONFIG_EPOLL=y |
| 71 | CONFIG_SIGNALFD=y | ||
| 72 | CONFIG_EVENTFD=y | ||
| 57 | CONFIG_SHMEM=y | 73 | CONFIG_SHMEM=y |
| 58 | CONFIG_SLAB=y | ||
| 59 | CONFIG_VM_EVENT_COUNTERS=y | 74 | CONFIG_VM_EVENT_COUNTERS=y |
| 75 | CONFIG_SLAB=y | ||
| 76 | # CONFIG_SLUB is not set | ||
| 77 | # CONFIG_SLOB is not set | ||
| 78 | CONFIG_SLABINFO=y | ||
| 60 | CONFIG_RT_MUTEXES=y | 79 | CONFIG_RT_MUTEXES=y |
| 61 | # CONFIG_TINY_SHMEM is not set | 80 | # CONFIG_TINY_SHMEM is not set |
| 62 | CONFIG_BASE_SMALL=0 | 81 | CONFIG_BASE_SMALL=0 |
| 63 | # CONFIG_SLOB is not set | ||
| 64 | |||
| 65 | # | ||
| 66 | # Loadable module support | ||
| 67 | # | ||
| 68 | CONFIG_MODULES=y | 82 | CONFIG_MODULES=y |
| 69 | CONFIG_MODULE_UNLOAD=y | 83 | CONFIG_MODULE_UNLOAD=y |
| 70 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 84 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 71 | # CONFIG_MODVERSIONS is not set | 85 | # CONFIG_MODVERSIONS is not set |
| 72 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 86 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 73 | CONFIG_KMOD=y | 87 | CONFIG_KMOD=y |
| 74 | |||
| 75 | # | ||
| 76 | # Block layer | ||
| 77 | # | ||
| 78 | CONFIG_BLOCK=y | 88 | CONFIG_BLOCK=y |
| 89 | # CONFIG_LBD is not set | ||
| 79 | # CONFIG_BLK_DEV_IO_TRACE is not set | 90 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 91 | # CONFIG_LSF is not set | ||
| 92 | # CONFIG_BLK_DEV_BSG is not set | ||
| 80 | 93 | ||
| 81 | # | 94 | # |
| 82 | # IO Schedulers | 95 | # IO Schedulers |
| @@ -108,12 +121,16 @@ CONFIG_ARCH_AT91=y | |||
| 108 | # CONFIG_ARCH_NETX is not set | 121 | # CONFIG_ARCH_NETX is not set |
| 109 | # CONFIG_ARCH_H720X is not set | 122 | # CONFIG_ARCH_H720X is not set |
| 110 | # CONFIG_ARCH_IMX is not set | 123 | # CONFIG_ARCH_IMX is not set |
| 124 | # CONFIG_ARCH_IOP13XX is not set | ||
| 111 | # CONFIG_ARCH_IOP32X is not set | 125 | # CONFIG_ARCH_IOP32X is not set |
| 112 | # CONFIG_ARCH_IOP33X is not set | 126 | # CONFIG_ARCH_IOP33X is not set |
| 113 | # CONFIG_ARCH_IXP4XX is not set | ||
| 114 | # CONFIG_ARCH_IXP2000 is not set | ||
| 115 | # CONFIG_ARCH_IXP23XX is not set | 127 | # CONFIG_ARCH_IXP23XX is not set |
| 128 | # CONFIG_ARCH_IXP2000 is not set | ||
| 129 | # CONFIG_ARCH_IXP4XX is not set | ||
| 116 | # CONFIG_ARCH_L7200 is not set | 130 | # CONFIG_ARCH_L7200 is not set |
| 131 | # CONFIG_ARCH_KS8695 is not set | ||
| 132 | # CONFIG_ARCH_NS9XXX is not set | ||
| 133 | # CONFIG_ARCH_MXC is not set | ||
| 117 | # CONFIG_ARCH_PNX4008 is not set | 134 | # CONFIG_ARCH_PNX4008 is not set |
| 118 | # CONFIG_ARCH_PXA is not set | 135 | # CONFIG_ARCH_PXA is not set |
| 119 | # CONFIG_ARCH_RPC is not set | 136 | # CONFIG_ARCH_RPC is not set |
| @@ -121,14 +138,27 @@ CONFIG_ARCH_AT91=y | |||
| 121 | # CONFIG_ARCH_S3C2410 is not set | 138 | # CONFIG_ARCH_S3C2410 is not set |
| 122 | # CONFIG_ARCH_SHARK is not set | 139 | # CONFIG_ARCH_SHARK is not set |
| 123 | # CONFIG_ARCH_LH7A40X is not set | 140 | # CONFIG_ARCH_LH7A40X is not set |
| 141 | # CONFIG_ARCH_DAVINCI is not set | ||
| 124 | # CONFIG_ARCH_OMAP is not set | 142 | # CONFIG_ARCH_OMAP is not set |
| 125 | 143 | ||
| 126 | # | 144 | # |
| 145 | # Boot options | ||
| 146 | # | ||
| 147 | |||
| 148 | # | ||
| 149 | # Power management | ||
| 150 | # | ||
| 151 | |||
| 152 | # | ||
| 127 | # Atmel AT91 System-on-Chip | 153 | # Atmel AT91 System-on-Chip |
| 128 | # | 154 | # |
| 129 | # CONFIG_ARCH_AT91RM9200 is not set | 155 | # CONFIG_ARCH_AT91RM9200 is not set |
| 130 | # CONFIG_ARCH_AT91SAM9260 is not set | 156 | # CONFIG_ARCH_AT91SAM9260 is not set |
| 131 | CONFIG_ARCH_AT91SAM9261=y | 157 | CONFIG_ARCH_AT91SAM9261=y |
| 158 | # CONFIG_ARCH_AT91SAM9263 is not set | ||
| 159 | # CONFIG_ARCH_AT91SAM9RL is not set | ||
| 160 | # CONFIG_ARCH_AT91X40 is not set | ||
| 161 | CONFIG_AT91_PMC_UNIT=y | ||
| 132 | 162 | ||
| 133 | # | 163 | # |
| 134 | # AT91SAM9261 Board Type | 164 | # AT91SAM9261 Board Type |
| @@ -138,12 +168,15 @@ CONFIG_MACH_AT91SAM9261EK=y | |||
| 138 | # | 168 | # |
| 139 | # AT91 Board Options | 169 | # AT91 Board Options |
| 140 | # | 170 | # |
| 171 | # CONFIG_MTD_AT91_DATAFLASH_CARD is not set | ||
| 141 | # CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set | 172 | # CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set |
| 142 | 173 | ||
| 143 | # | 174 | # |
| 144 | # AT91 Feature Selections | 175 | # AT91 Feature Selections |
| 145 | # | 176 | # |
| 146 | # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set | 177 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y |
| 178 | # CONFIG_ATMEL_TCLIB is not set | ||
| 179 | CONFIG_AT91_TIMER_HZ=100 | ||
| 147 | 180 | ||
| 148 | # | 181 | # |
| 149 | # Processor Type | 182 | # Processor Type |
| @@ -166,19 +199,19 @@ CONFIG_CPU_CP15_MMU=y | |||
| 166 | # CONFIG_CPU_DCACHE_DISABLE is not set | 199 | # CONFIG_CPU_DCACHE_DISABLE is not set |
| 167 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | 200 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set |
| 168 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set | 201 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set |
| 202 | # CONFIG_OUTER_CACHE is not set | ||
| 169 | 203 | ||
| 170 | # | 204 | # |
| 171 | # Bus support | 205 | # Bus support |
| 172 | # | 206 | # |
| 173 | 207 | # CONFIG_PCI_SYSCALL is not set | |
| 174 | # | 208 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 175 | # PCCARD (PCMCIA/CardBus) support | ||
| 176 | # | ||
| 177 | # CONFIG_PCCARD is not set | 209 | # CONFIG_PCCARD is not set |
| 178 | 210 | ||
| 179 | # | 211 | # |
| 180 | # Kernel Features | 212 | # Kernel Features |
| 181 | # | 213 | # |
| 214 | # CONFIG_TICK_ONESHOT is not set | ||
| 182 | # CONFIG_PREEMPT is not set | 215 | # CONFIG_PREEMPT is not set |
| 183 | # CONFIG_NO_IDLE_HZ is not set | 216 | # CONFIG_NO_IDLE_HZ is not set |
| 184 | CONFIG_HZ=100 | 217 | CONFIG_HZ=100 |
| @@ -191,8 +224,12 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 191 | CONFIG_FLATMEM=y | 224 | CONFIG_FLATMEM=y |
| 192 | CONFIG_FLAT_NODE_MEM_MAP=y | 225 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 193 | # CONFIG_SPARSEMEM_STATIC is not set | 226 | # CONFIG_SPARSEMEM_STATIC is not set |
| 227 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 194 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 228 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 195 | # CONFIG_RESOURCES_64BIT is not set | 229 | # CONFIG_RESOURCES_64BIT is not set |
| 230 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 231 | CONFIG_BOUNCE=y | ||
| 232 | CONFIG_VIRT_TO_BUS=y | ||
| 196 | # CONFIG_LEDS is not set | 233 | # CONFIG_LEDS is not set |
| 197 | CONFIG_ALIGNMENT_TRAP=y | 234 | CONFIG_ALIGNMENT_TRAP=y |
| 198 | 235 | ||
| @@ -203,6 +240,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 | |||
| 203 | CONFIG_ZBOOT_ROM_BSS=0x0 | 240 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 204 | CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" | 241 | CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" |
| 205 | # CONFIG_XIP_KERNEL is not set | 242 | # CONFIG_XIP_KERNEL is not set |
| 243 | # CONFIG_KEXEC is not set | ||
| 206 | 244 | ||
| 207 | # | 245 | # |
| 208 | # Floating point emulation | 246 | # Floating point emulation |
| @@ -228,7 +266,7 @@ CONFIG_BINFMT_ELF=y | |||
| 228 | # Power management options | 266 | # Power management options |
| 229 | # | 267 | # |
| 230 | # CONFIG_PM is not set | 268 | # CONFIG_PM is not set |
| 231 | # CONFIG_APM is not set | 269 | CONFIG_SUSPEND_UP_POSSIBLE=y |
| 232 | 270 | ||
| 233 | # | 271 | # |
| 234 | # Networking | 272 | # Networking |
| @@ -238,13 +276,13 @@ CONFIG_NET=y | |||
| 238 | # | 276 | # |
| 239 | # Networking options | 277 | # Networking options |
| 240 | # | 278 | # |
| 241 | # CONFIG_NETDEBUG is not set | ||
| 242 | CONFIG_PACKET=y | 279 | CONFIG_PACKET=y |
| 243 | # CONFIG_PACKET_MMAP is not set | 280 | # CONFIG_PACKET_MMAP is not set |
| 244 | CONFIG_UNIX=y | 281 | CONFIG_UNIX=y |
| 245 | CONFIG_XFRM=y | 282 | CONFIG_XFRM=y |
| 246 | # CONFIG_XFRM_USER is not set | 283 | # CONFIG_XFRM_USER is not set |
| 247 | # CONFIG_XFRM_SUB_POLICY is not set | 284 | # CONFIG_XFRM_SUB_POLICY is not set |
| 285 | # CONFIG_XFRM_MIGRATE is not set | ||
| 248 | # CONFIG_NET_KEY is not set | 286 | # CONFIG_NET_KEY is not set |
| 249 | CONFIG_INET=y | 287 | CONFIG_INET=y |
| 250 | # CONFIG_IP_MULTICAST is not set | 288 | # CONFIG_IP_MULTICAST is not set |
| @@ -266,30 +304,20 @@ CONFIG_IP_PNP_BOOTP=y | |||
| 266 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 304 | CONFIG_INET_XFRM_MODE_TRANSPORT=y |
| 267 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 305 | CONFIG_INET_XFRM_MODE_TUNNEL=y |
| 268 | CONFIG_INET_XFRM_MODE_BEET=y | 306 | CONFIG_INET_XFRM_MODE_BEET=y |
| 307 | # CONFIG_INET_LRO is not set | ||
| 269 | CONFIG_INET_DIAG=y | 308 | CONFIG_INET_DIAG=y |
| 270 | CONFIG_INET_TCP_DIAG=y | 309 | CONFIG_INET_TCP_DIAG=y |
| 271 | # CONFIG_TCP_CONG_ADVANCED is not set | 310 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 272 | CONFIG_TCP_CONG_CUBIC=y | 311 | CONFIG_TCP_CONG_CUBIC=y |
| 273 | CONFIG_DEFAULT_TCP_CONG="cubic" | 312 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 313 | # CONFIG_TCP_MD5SIG is not set | ||
| 274 | # CONFIG_IPV6 is not set | 314 | # CONFIG_IPV6 is not set |
| 275 | # CONFIG_INET6_XFRM_TUNNEL is not set | 315 | # CONFIG_INET6_XFRM_TUNNEL is not set |
| 276 | # CONFIG_INET6_TUNNEL is not set | 316 | # CONFIG_INET6_TUNNEL is not set |
| 277 | # CONFIG_NETWORK_SECMARK is not set | 317 | # CONFIG_NETWORK_SECMARK is not set |
| 278 | # CONFIG_NETFILTER is not set | 318 | # CONFIG_NETFILTER is not set |
| 279 | |||
| 280 | # | ||
| 281 | # DCCP Configuration (EXPERIMENTAL) | ||
| 282 | # | ||
| 283 | # CONFIG_IP_DCCP is not set | 319 | # CONFIG_IP_DCCP is not set |
| 284 | |||
| 285 | # | ||
| 286 | # SCTP Configuration (EXPERIMENTAL) | ||
| 287 | # | ||
| 288 | # CONFIG_IP_SCTP is not set | 320 | # CONFIG_IP_SCTP is not set |
| 289 | |||
| 290 | # | ||
| 291 | # TIPC Configuration (EXPERIMENTAL) | ||
| 292 | # | ||
| 293 | # CONFIG_TIPC is not set | 321 | # CONFIG_TIPC is not set |
| 294 | # CONFIG_ATM is not set | 322 | # CONFIG_ATM is not set |
| 295 | # CONFIG_BRIDGE is not set | 323 | # CONFIG_BRIDGE is not set |
| @@ -302,10 +330,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 302 | # CONFIG_LAPB is not set | 330 | # CONFIG_LAPB is not set |
| 303 | # CONFIG_ECONET is not set | 331 | # CONFIG_ECONET is not set |
| 304 | # CONFIG_WAN_ROUTER is not set | 332 | # CONFIG_WAN_ROUTER is not set |
| 305 | |||
| 306 | # | ||
| 307 | # QoS and/or fair queueing | ||
| 308 | # | ||
| 309 | # CONFIG_NET_SCHED is not set | 333 | # CONFIG_NET_SCHED is not set |
| 310 | 334 | ||
| 311 | # | 335 | # |
| @@ -315,7 +339,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 315 | # CONFIG_HAMRADIO is not set | 339 | # CONFIG_HAMRADIO is not set |
| 316 | # CONFIG_IRDA is not set | 340 | # CONFIG_IRDA is not set |
| 317 | # CONFIG_BT is not set | 341 | # CONFIG_BT is not set |
| 342 | # CONFIG_AF_RXRPC is not set | ||
| 343 | |||
| 344 | # | ||
| 345 | # Wireless | ||
| 346 | # | ||
| 347 | # CONFIG_CFG80211 is not set | ||
| 348 | # CONFIG_WIRELESS_EXT is not set | ||
| 349 | # CONFIG_MAC80211 is not set | ||
| 318 | # CONFIG_IEEE80211 is not set | 350 | # CONFIG_IEEE80211 is not set |
| 351 | # CONFIG_RFKILL is not set | ||
| 352 | # CONFIG_NET_9P is not set | ||
| 319 | 353 | ||
| 320 | # | 354 | # |
| 321 | # Device Drivers | 355 | # Device Drivers |
| @@ -324,20 +358,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 324 | # | 358 | # |
| 325 | # Generic Driver Options | 359 | # Generic Driver Options |
| 326 | # | 360 | # |
| 361 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 327 | CONFIG_STANDALONE=y | 362 | CONFIG_STANDALONE=y |
| 328 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 363 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 329 | # CONFIG_FW_LOADER is not set | 364 | # CONFIG_FW_LOADER is not set |
| 330 | # CONFIG_DEBUG_DRIVER is not set | 365 | # CONFIG_DEBUG_DRIVER is not set |
| 366 | # CONFIG_DEBUG_DEVRES is not set | ||
| 331 | # CONFIG_SYS_HYPERVISOR is not set | 367 | # CONFIG_SYS_HYPERVISOR is not set |
| 332 | |||
| 333 | # | ||
| 334 | # Connector - unified userspace <-> kernelspace linker | ||
| 335 | # | ||
| 336 | # CONFIG_CONNECTOR is not set | 368 | # CONFIG_CONNECTOR is not set |
| 337 | |||
| 338 | # | ||
| 339 | # Memory Technology Devices (MTD) | ||
| 340 | # | ||
| 341 | CONFIG_MTD=y | 369 | CONFIG_MTD=y |
| 342 | # CONFIG_MTD_DEBUG is not set | 370 | # CONFIG_MTD_DEBUG is not set |
| 343 | # CONFIG_MTD_CONCAT is not set | 371 | # CONFIG_MTD_CONCAT is not set |
| @@ -350,12 +378,14 @@ CONFIG_MTD_CMDLINE_PARTS=y | |||
| 350 | # User Modules And Translation Layers | 378 | # User Modules And Translation Layers |
| 351 | # | 379 | # |
| 352 | # CONFIG_MTD_CHAR is not set | 380 | # CONFIG_MTD_CHAR is not set |
| 381 | CONFIG_MTD_BLKDEVS=y | ||
| 353 | CONFIG_MTD_BLOCK=y | 382 | CONFIG_MTD_BLOCK=y |
| 354 | # CONFIG_FTL is not set | 383 | # CONFIG_FTL is not set |
| 355 | # CONFIG_NFTL is not set | 384 | # CONFIG_NFTL is not set |
| 356 | # CONFIG_INFTL is not set | 385 | # CONFIG_INFTL is not set |
| 357 | # CONFIG_RFD_FTL is not set | 386 | # CONFIG_RFD_FTL is not set |
| 358 | # CONFIG_SSFDC is not set | 387 | # CONFIG_SSFDC is not set |
| 388 | # CONFIG_MTD_OOPS is not set | ||
| 359 | 389 | ||
| 360 | # | 390 | # |
| 361 | # RAM/ROM/Flash chip drivers | 391 | # RAM/ROM/Flash chip drivers |
| @@ -375,7 +405,6 @@ CONFIG_MTD_CFI_I2=y | |||
| 375 | # CONFIG_MTD_RAM is not set | 405 | # CONFIG_MTD_RAM is not set |
| 376 | # CONFIG_MTD_ROM is not set | 406 | # CONFIG_MTD_ROM is not set |
| 377 | # CONFIG_MTD_ABSENT is not set | 407 | # CONFIG_MTD_ABSENT is not set |
| 378 | # CONFIG_MTD_OBSOLETE_CHIPS is not set | ||
| 379 | 408 | ||
| 380 | # | 409 | # |
| 381 | # Mapping drivers for chip access | 410 | # Mapping drivers for chip access |
| @@ -386,6 +415,8 @@ CONFIG_MTD_CFI_I2=y | |||
| 386 | # | 415 | # |
| 387 | # Self-contained MTD device drivers | 416 | # Self-contained MTD device drivers |
| 388 | # | 417 | # |
| 418 | # CONFIG_MTD_DATAFLASH is not set | ||
| 419 | # CONFIG_MTD_M25P80 is not set | ||
| 389 | # CONFIG_MTD_SLRAM is not set | 420 | # CONFIG_MTD_SLRAM is not set |
| 390 | # CONFIG_MTD_PHRAM is not set | 421 | # CONFIG_MTD_PHRAM is not set |
| 391 | # CONFIG_MTD_MTDRAM is not set | 422 | # CONFIG_MTD_MTDRAM is not set |
| @@ -397,35 +428,24 @@ CONFIG_MTD_CFI_I2=y | |||
| 397 | # CONFIG_MTD_DOC2000 is not set | 428 | # CONFIG_MTD_DOC2000 is not set |
| 398 | # CONFIG_MTD_DOC2001 is not set | 429 | # CONFIG_MTD_DOC2001 is not set |
| 399 | # CONFIG_MTD_DOC2001PLUS is not set | 430 | # CONFIG_MTD_DOC2001PLUS is not set |
| 400 | |||
| 401 | # | ||
| 402 | # NAND Flash Device Drivers | ||
| 403 | # | ||
| 404 | CONFIG_MTD_NAND=y | 431 | CONFIG_MTD_NAND=y |
| 405 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | 432 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set |
| 406 | # CONFIG_MTD_NAND_ECC_SMC is not set | 433 | # CONFIG_MTD_NAND_ECC_SMC is not set |
| 434 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 407 | CONFIG_MTD_NAND_IDS=y | 435 | CONFIG_MTD_NAND_IDS=y |
| 408 | # CONFIG_MTD_NAND_DISKONCHIP is not set | 436 | # CONFIG_MTD_NAND_DISKONCHIP is not set |
| 409 | CONFIG_MTD_NAND_AT91=y | 437 | CONFIG_MTD_NAND_AT91=y |
| 410 | # CONFIG_MTD_NAND_NANDSIM is not set | 438 | # CONFIG_MTD_NAND_NANDSIM is not set |
| 411 | 439 | # CONFIG_MTD_NAND_PLATFORM is not set | |
| 412 | # | 440 | # CONFIG_MTD_ALAUDA is not set |
| 413 | # OneNAND Flash Device Drivers | ||
| 414 | # | ||
| 415 | # CONFIG_MTD_ONENAND is not set | 441 | # CONFIG_MTD_ONENAND is not set |
| 416 | 442 | ||
| 417 | # | 443 | # |
| 418 | # Parallel port support | 444 | # UBI - Unsorted block images |
| 419 | # | 445 | # |
| 446 | # CONFIG_MTD_UBI is not set | ||
| 420 | # CONFIG_PARPORT is not set | 447 | # CONFIG_PARPORT is not set |
| 421 | 448 | CONFIG_BLK_DEV=y | |
| 422 | # | ||
| 423 | # Plug and Play support | ||
| 424 | # | ||
| 425 | |||
| 426 | # | ||
| 427 | # Block devices | ||
| 428 | # | ||
| 429 | # CONFIG_BLK_DEV_COW_COMMON is not set | 449 | # CONFIG_BLK_DEV_COW_COMMON is not set |
| 430 | # CONFIG_BLK_DEV_LOOP is not set | 450 | # CONFIG_BLK_DEV_LOOP is not set |
| 431 | # CONFIG_BLK_DEV_NBD is not set | 451 | # CONFIG_BLK_DEV_NBD is not set |
| @@ -434,15 +454,19 @@ CONFIG_BLK_DEV_RAM=y | |||
| 434 | CONFIG_BLK_DEV_RAM_COUNT=16 | 454 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 435 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 455 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 436 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 456 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 |
| 437 | CONFIG_BLK_DEV_INITRD=y | ||
| 438 | # CONFIG_CDROM_PKTCDVD is not set | 457 | # CONFIG_CDROM_PKTCDVD is not set |
| 439 | # CONFIG_ATA_OVER_ETH is not set | 458 | # CONFIG_ATA_OVER_ETH is not set |
| 459 | CONFIG_MISC_DEVICES=y | ||
| 460 | # CONFIG_EEPROM_93CX6 is not set | ||
| 461 | CONFIG_ATMEL_SSC=y | ||
| 440 | 462 | ||
| 441 | # | 463 | # |
| 442 | # SCSI device support | 464 | # SCSI device support |
| 443 | # | 465 | # |
| 444 | # CONFIG_RAID_ATTRS is not set | 466 | # CONFIG_RAID_ATTRS is not set |
| 445 | CONFIG_SCSI=y | 467 | CONFIG_SCSI=y |
| 468 | CONFIG_SCSI_DMA=y | ||
| 469 | # CONFIG_SCSI_TGT is not set | ||
| 446 | # CONFIG_SCSI_NETLINK is not set | 470 | # CONFIG_SCSI_NETLINK is not set |
| 447 | CONFIG_SCSI_PROC_FS=y | 471 | CONFIG_SCSI_PROC_FS=y |
| 448 | 472 | ||
| @@ -462,6 +486,8 @@ CONFIG_BLK_DEV_SD=y | |||
| 462 | CONFIG_SCSI_MULTI_LUN=y | 486 | CONFIG_SCSI_MULTI_LUN=y |
| 463 | # CONFIG_SCSI_CONSTANTS is not set | 487 | # CONFIG_SCSI_CONSTANTS is not set |
| 464 | # CONFIG_SCSI_LOGGING is not set | 488 | # CONFIG_SCSI_LOGGING is not set |
| 489 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 490 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 465 | 491 | ||
| 466 | # | 492 | # |
| 467 | # SCSI Transports | 493 | # SCSI Transports |
| @@ -469,75 +495,49 @@ CONFIG_SCSI_MULTI_LUN=y | |||
| 469 | # CONFIG_SCSI_SPI_ATTRS is not set | 495 | # CONFIG_SCSI_SPI_ATTRS is not set |
| 470 | # CONFIG_SCSI_FC_ATTRS is not set | 496 | # CONFIG_SCSI_FC_ATTRS is not set |
| 471 | # CONFIG_SCSI_ISCSI_ATTRS is not set | 497 | # CONFIG_SCSI_ISCSI_ATTRS is not set |
| 472 | # CONFIG_SCSI_SAS_ATTRS is not set | ||
| 473 | # CONFIG_SCSI_SAS_LIBSAS is not set | 498 | # CONFIG_SCSI_SAS_LIBSAS is not set |
| 474 | 499 | # CONFIG_SCSI_SRP_ATTRS is not set | |
| 475 | # | 500 | CONFIG_SCSI_LOWLEVEL=y |
| 476 | # SCSI low-level drivers | ||
| 477 | # | ||
| 478 | # CONFIG_ISCSI_TCP is not set | 501 | # CONFIG_ISCSI_TCP is not set |
| 479 | # CONFIG_SCSI_DEBUG is not set | 502 | # CONFIG_SCSI_DEBUG is not set |
| 480 | 503 | # CONFIG_ATA is not set | |
| 481 | # | ||
| 482 | # Multi-device support (RAID and LVM) | ||
| 483 | # | ||
| 484 | # CONFIG_MD is not set | 504 | # CONFIG_MD is not set |
| 485 | |||
| 486 | # | ||
| 487 | # Fusion MPT device support | ||
| 488 | # | ||
| 489 | # CONFIG_FUSION is not set | ||
| 490 | |||
| 491 | # | ||
| 492 | # IEEE 1394 (FireWire) support | ||
| 493 | # | ||
| 494 | |||
| 495 | # | ||
| 496 | # I2O device support | ||
| 497 | # | ||
| 498 | |||
| 499 | # | ||
| 500 | # Network device support | ||
| 501 | # | ||
| 502 | CONFIG_NETDEVICES=y | 505 | CONFIG_NETDEVICES=y |
| 506 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 503 | # CONFIG_DUMMY is not set | 507 | # CONFIG_DUMMY is not set |
| 504 | # CONFIG_BONDING is not set | 508 | # CONFIG_BONDING is not set |
| 509 | # CONFIG_MACVLAN is not set | ||
| 505 | # CONFIG_EQUALIZER is not set | 510 | # CONFIG_EQUALIZER is not set |
| 506 | # CONFIG_TUN is not set | 511 | # CONFIG_TUN is not set |
| 507 | 512 | # CONFIG_VETH is not set | |
| 508 | # | ||
| 509 | # PHY device support | ||
| 510 | # | ||
| 511 | # CONFIG_PHYLIB is not set | 513 | # CONFIG_PHYLIB is not set |
| 512 | |||
| 513 | # | ||
| 514 | # Ethernet (10 or 100Mbit) | ||
| 515 | # | ||
| 516 | CONFIG_NET_ETHERNET=y | 514 | CONFIG_NET_ETHERNET=y |
| 517 | CONFIG_MII=y | 515 | CONFIG_MII=y |
| 516 | # CONFIG_AX88796 is not set | ||
| 518 | # CONFIG_SMC91X is not set | 517 | # CONFIG_SMC91X is not set |
| 519 | CONFIG_DM9000=y | 518 | CONFIG_DM9000=y |
| 519 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 520 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 521 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 522 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 523 | # CONFIG_B44 is not set | ||
| 524 | # CONFIG_NETDEV_1000 is not set | ||
| 525 | # CONFIG_NETDEV_10000 is not set | ||
| 520 | 526 | ||
| 521 | # | 527 | # |
| 522 | # Ethernet (1000 Mbit) | 528 | # Wireless LAN |
| 523 | # | ||
| 524 | |||
| 525 | # | ||
| 526 | # Ethernet (10000 Mbit) | ||
| 527 | # | ||
| 528 | |||
| 529 | # | ||
| 530 | # Token Ring devices | ||
| 531 | # | 529 | # |
| 530 | # CONFIG_WLAN_PRE80211 is not set | ||
| 531 | # CONFIG_WLAN_80211 is not set | ||
| 532 | 532 | ||
| 533 | # | 533 | # |
| 534 | # Wireless LAN (non-hamradio) | 534 | # USB Network Adapters |
| 535 | # | ||
| 536 | # CONFIG_NET_RADIO is not set | ||
| 537 | |||
| 538 | # | ||
| 539 | # Wan interfaces | ||
| 540 | # | 535 | # |
| 536 | # CONFIG_USB_CATC is not set | ||
| 537 | # CONFIG_USB_KAWETH is not set | ||
| 538 | # CONFIG_USB_PEGASUS is not set | ||
| 539 | # CONFIG_USB_RTL8150 is not set | ||
| 540 | # CONFIG_USB_USBNET is not set | ||
| 541 | # CONFIG_WAN is not set | 541 | # CONFIG_WAN is not set |
| 542 | # CONFIG_PPP is not set | 542 | # CONFIG_PPP is not set |
| 543 | # CONFIG_SLIP is not set | 543 | # CONFIG_SLIP is not set |
| @@ -545,10 +545,6 @@ CONFIG_DM9000=y | |||
| 545 | # CONFIG_NETCONSOLE is not set | 545 | # CONFIG_NETCONSOLE is not set |
| 546 | # CONFIG_NETPOLL is not set | 546 | # CONFIG_NETPOLL is not set |
| 547 | # CONFIG_NET_POLL_CONTROLLER is not set | 547 | # CONFIG_NET_POLL_CONTROLLER is not set |
| 548 | |||
| 549 | # | ||
| 550 | # ISDN subsystem | ||
| 551 | # | ||
| 552 | # CONFIG_ISDN is not set | 548 | # CONFIG_ISDN is not set |
| 553 | 549 | ||
| 554 | # | 550 | # |
| @@ -556,6 +552,7 @@ CONFIG_DM9000=y | |||
| 556 | # | 552 | # |
| 557 | CONFIG_INPUT=y | 553 | CONFIG_INPUT=y |
| 558 | # CONFIG_INPUT_FF_MEMLESS is not set | 554 | # CONFIG_INPUT_FF_MEMLESS is not set |
| 555 | # CONFIG_INPUT_POLLDEV is not set | ||
| 559 | 556 | ||
| 560 | # | 557 | # |
| 561 | # Userland interfaces | 558 | # Userland interfaces |
| @@ -565,23 +562,43 @@ CONFIG_INPUT_MOUSEDEV=y | |||
| 565 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | 562 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 |
| 566 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | 563 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 |
| 567 | # CONFIG_INPUT_JOYDEV is not set | 564 | # CONFIG_INPUT_JOYDEV is not set |
| 568 | # CONFIG_INPUT_TSDEV is not set | ||
| 569 | # CONFIG_INPUT_EVDEV is not set | 565 | # CONFIG_INPUT_EVDEV is not set |
| 570 | # CONFIG_INPUT_EVBUG is not set | 566 | # CONFIG_INPUT_EVBUG is not set |
| 571 | 567 | ||
| 572 | # | 568 | # |
| 573 | # Input Device Drivers | 569 | # Input Device Drivers |
| 574 | # | 570 | # |
| 575 | # CONFIG_INPUT_KEYBOARD is not set | 571 | CONFIG_INPUT_KEYBOARD=y |
| 572 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 573 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 574 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 575 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 576 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 577 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 578 | CONFIG_KEYBOARD_GPIO=y | ||
| 576 | # CONFIG_INPUT_MOUSE is not set | 579 | # CONFIG_INPUT_MOUSE is not set |
| 577 | # CONFIG_INPUT_JOYSTICK is not set | 580 | # CONFIG_INPUT_JOYSTICK is not set |
| 578 | # CONFIG_INPUT_TOUCHSCREEN is not set | 581 | # CONFIG_INPUT_TABLET is not set |
| 582 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 583 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 584 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 585 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
| 586 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
| 587 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
| 588 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
| 589 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
| 590 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
| 591 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
| 592 | # CONFIG_TOUCHSCREEN_UCB1400 is not set | ||
| 593 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
| 579 | # CONFIG_INPUT_MISC is not set | 594 | # CONFIG_INPUT_MISC is not set |
| 580 | 595 | ||
| 581 | # | 596 | # |
| 582 | # Hardware I/O ports | 597 | # Hardware I/O ports |
| 583 | # | 598 | # |
| 584 | # CONFIG_SERIO is not set | 599 | CONFIG_SERIO=y |
| 600 | CONFIG_SERIO_SERPORT=y | ||
| 601 | # CONFIG_SERIO_RAW is not set | ||
| 585 | # CONFIG_GAMEPORT is not set | 602 | # CONFIG_GAMEPORT is not set |
| 586 | 603 | ||
| 587 | # | 604 | # |
| @@ -609,75 +626,47 @@ CONFIG_SERIAL_CORE_CONSOLE=y | |||
| 609 | CONFIG_UNIX98_PTYS=y | 626 | CONFIG_UNIX98_PTYS=y |
| 610 | CONFIG_LEGACY_PTYS=y | 627 | CONFIG_LEGACY_PTYS=y |
| 611 | CONFIG_LEGACY_PTY_COUNT=256 | 628 | CONFIG_LEGACY_PTY_COUNT=256 |
| 612 | |||
| 613 | # | ||
| 614 | # IPMI | ||
| 615 | # | ||
| 616 | # CONFIG_IPMI_HANDLER is not set | 629 | # CONFIG_IPMI_HANDLER is not set |
| 617 | |||
| 618 | # | ||
| 619 | # Watchdog Cards | ||
| 620 | # | ||
| 621 | CONFIG_WATCHDOG=y | ||
| 622 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 623 | |||
| 624 | # | ||
| 625 | # Watchdog Device Drivers | ||
| 626 | # | ||
| 627 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 628 | |||
| 629 | # | ||
| 630 | # USB-based Watchdog Cards | ||
| 631 | # | ||
| 632 | # CONFIG_USBPCWATCHDOG is not set | ||
| 633 | CONFIG_HW_RANDOM=y | 630 | CONFIG_HW_RANDOM=y |
| 634 | # CONFIG_NVRAM is not set | 631 | # CONFIG_NVRAM is not set |
| 635 | # CONFIG_DTLK is not set | ||
| 636 | # CONFIG_R3964 is not set | 632 | # CONFIG_R3964 is not set |
| 637 | |||
| 638 | # | ||
| 639 | # Ftape, the floppy tape device driver | ||
| 640 | # | ||
| 641 | # CONFIG_RAW_DRIVER is not set | 633 | # CONFIG_RAW_DRIVER is not set |
| 642 | |||
| 643 | # | ||
| 644 | # TPM devices | ||
| 645 | # | ||
| 646 | # CONFIG_TCG_TPM is not set | 634 | # CONFIG_TCG_TPM is not set |
| 647 | |||
| 648 | # | ||
| 649 | # I2C support | ||
| 650 | # | ||
| 651 | CONFIG_I2C=y | 635 | CONFIG_I2C=y |
| 636 | CONFIG_I2C_BOARDINFO=y | ||
| 652 | CONFIG_I2C_CHARDEV=y | 637 | CONFIG_I2C_CHARDEV=y |
| 653 | 638 | ||
| 654 | # | 639 | # |
| 655 | # I2C Algorithms | 640 | # I2C Algorithms |
| 656 | # | 641 | # |
| 657 | # CONFIG_I2C_ALGOBIT is not set | 642 | CONFIG_I2C_ALGOBIT=y |
| 658 | # CONFIG_I2C_ALGOPCF is not set | 643 | # CONFIG_I2C_ALGOPCF is not set |
| 659 | # CONFIG_I2C_ALGOPCA is not set | 644 | # CONFIG_I2C_ALGOPCA is not set |
| 660 | 645 | ||
| 661 | # | 646 | # |
| 662 | # I2C Hardware Bus support | 647 | # I2C Hardware Bus support |
| 663 | # | 648 | # |
| 664 | CONFIG_I2C_AT91=y | 649 | CONFIG_I2C_GPIO=y |
| 665 | # CONFIG_I2C_OCORES is not set | 650 | # CONFIG_I2C_OCORES is not set |
| 666 | # CONFIG_I2C_PARPORT_LIGHT is not set | 651 | # CONFIG_I2C_PARPORT_LIGHT is not set |
| 652 | # CONFIG_I2C_SIMTEC is not set | ||
| 653 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 667 | # CONFIG_I2C_STUB is not set | 654 | # CONFIG_I2C_STUB is not set |
| 655 | # CONFIG_I2C_TINY_USB is not set | ||
| 668 | # CONFIG_I2C_PCA is not set | 656 | # CONFIG_I2C_PCA is not set |
| 669 | # CONFIG_I2C_PCA_ISA is not set | ||
| 670 | 657 | ||
| 671 | # | 658 | # |
| 672 | # Miscellaneous I2C Chip support | 659 | # Miscellaneous I2C Chip support |
| 673 | # | 660 | # |
| 674 | # CONFIG_SENSORS_DS1337 is not set | 661 | # CONFIG_SENSORS_DS1337 is not set |
| 675 | # CONFIG_SENSORS_DS1374 is not set | 662 | # CONFIG_SENSORS_DS1374 is not set |
| 663 | # CONFIG_DS1682 is not set | ||
| 676 | # CONFIG_SENSORS_EEPROM is not set | 664 | # CONFIG_SENSORS_EEPROM is not set |
| 677 | # CONFIG_SENSORS_PCF8574 is not set | 665 | # CONFIG_SENSORS_PCF8574 is not set |
| 678 | # CONFIG_SENSORS_PCA9539 is not set | 666 | # CONFIG_SENSORS_PCA9539 is not set |
| 679 | # CONFIG_SENSORS_PCF8591 is not set | 667 | # CONFIG_SENSORS_PCF8591 is not set |
| 680 | # CONFIG_SENSORS_MAX6875 is not set | 668 | # CONFIG_SENSORS_MAX6875 is not set |
| 669 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 681 | # CONFIG_I2C_DEBUG_CORE is not set | 670 | # CONFIG_I2C_DEBUG_CORE is not set |
| 682 | # CONFIG_I2C_DEBUG_ALGO is not set | 671 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 683 | # CONFIG_I2C_DEBUG_BUS is not set | 672 | # CONFIG_I2C_DEBUG_BUS is not set |
| @@ -686,70 +675,125 @@ CONFIG_I2C_AT91=y | |||
| 686 | # | 675 | # |
| 687 | # SPI support | 676 | # SPI support |
| 688 | # | 677 | # |
| 689 | # CONFIG_SPI is not set | 678 | CONFIG_SPI=y |
| 690 | # CONFIG_SPI_MASTER is not set | 679 | # CONFIG_SPI_DEBUG is not set |
| 680 | CONFIG_SPI_MASTER=y | ||
| 691 | 681 | ||
| 692 | # | 682 | # |
| 693 | # Dallas's 1-wire bus | 683 | # SPI Master Controller Drivers |
| 694 | # | 684 | # |
| 695 | # CONFIG_W1 is not set | 685 | CONFIG_SPI_ATMEL=y |
| 686 | # CONFIG_SPI_BITBANG is not set | ||
| 696 | 687 | ||
| 697 | # | 688 | # |
| 698 | # Hardware Monitoring support | 689 | # SPI Protocol Masters |
| 699 | # | 690 | # |
| 691 | # CONFIG_SPI_AT25 is not set | ||
| 692 | # CONFIG_SPI_SPIDEV is not set | ||
| 693 | # CONFIG_SPI_TLE62X0 is not set | ||
| 694 | # CONFIG_W1 is not set | ||
| 695 | # CONFIG_POWER_SUPPLY is not set | ||
| 700 | # CONFIG_HWMON is not set | 696 | # CONFIG_HWMON is not set |
| 701 | # CONFIG_HWMON_VID is not set | 697 | CONFIG_WATCHDOG=y |
| 698 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 702 | 699 | ||
| 703 | # | 700 | # |
| 704 | # Misc devices | 701 | # Watchdog Device Drivers |
| 705 | # | 702 | # |
| 706 | # CONFIG_TIFM_CORE is not set | 703 | # CONFIG_SOFT_WATCHDOG is not set |
| 704 | CONFIG_AT91SAM9_WATCHDOG=y | ||
| 707 | 705 | ||
| 708 | # | 706 | # |
| 709 | # LED devices | 707 | # USB-based Watchdog Cards |
| 710 | # | 708 | # |
| 711 | # CONFIG_NEW_LEDS is not set | 709 | # CONFIG_USBPCWATCHDOG is not set |
| 712 | 710 | ||
| 713 | # | 711 | # |
| 714 | # LED drivers | 712 | # Sonics Silicon Backplane |
| 715 | # | 713 | # |
| 714 | CONFIG_SSB_POSSIBLE=y | ||
| 715 | # CONFIG_SSB is not set | ||
| 716 | 716 | ||
| 717 | # | 717 | # |
| 718 | # LED Triggers | 718 | # Multifunction device drivers |
| 719 | # | 719 | # |
| 720 | # CONFIG_MFD_SM501 is not set | ||
| 720 | 721 | ||
| 721 | # | 722 | # |
| 722 | # Multimedia devices | 723 | # Multimedia devices |
| 723 | # | 724 | # |
| 724 | # CONFIG_VIDEO_DEV is not set | 725 | # CONFIG_VIDEO_DEV is not set |
| 725 | 726 | # CONFIG_DVB_CORE is not set | |
| 726 | # | 727 | CONFIG_DAB=y |
| 727 | # Digital Video Broadcasting Devices | ||
| 728 | # | ||
| 729 | # CONFIG_DVB is not set | ||
| 730 | # CONFIG_USB_DABUSB is not set | 728 | # CONFIG_USB_DABUSB is not set |
| 731 | 729 | ||
| 732 | # | 730 | # |
| 733 | # Graphics support | 731 | # Graphics support |
| 734 | # | 732 | # |
| 733 | # CONFIG_VGASTATE is not set | ||
| 734 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 735 | CONFIG_FB=y | ||
| 735 | # CONFIG_FIRMWARE_EDID is not set | 736 | # CONFIG_FIRMWARE_EDID is not set |
| 736 | # CONFIG_FB is not set | 737 | # CONFIG_FB_DDC is not set |
| 738 | CONFIG_FB_CFB_FILLRECT=y | ||
| 739 | CONFIG_FB_CFB_COPYAREA=y | ||
| 740 | CONFIG_FB_CFB_IMAGEBLIT=y | ||
| 741 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 742 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 743 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 744 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 745 | # CONFIG_FB_SYS_FOPS is not set | ||
| 746 | CONFIG_FB_DEFERRED_IO=y | ||
| 747 | # CONFIG_FB_SVGALIB is not set | ||
| 748 | # CONFIG_FB_MACMODES is not set | ||
| 749 | # CONFIG_FB_BACKLIGHT is not set | ||
| 750 | # CONFIG_FB_MODE_HELPERS is not set | ||
| 751 | # CONFIG_FB_TILEBLITTING is not set | ||
| 752 | |||
| 753 | # | ||
| 754 | # Frame buffer hardware drivers | ||
| 755 | # | ||
| 756 | # CONFIG_FB_S1D15605 is not set | ||
| 757 | # CONFIG_FB_S1D13XXX is not set | ||
| 758 | CONFIG_FB_ATMEL=y | ||
| 759 | # CONFIG_FB_INTSRAM is not set | ||
| 760 | # CONFIG_FB_ATMEL_STN is not set | ||
| 761 | # CONFIG_FB_VIRTUAL is not set | ||
| 762 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 763 | |||
| 764 | # | ||
| 765 | # Display device support | ||
| 766 | # | ||
| 767 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 737 | 768 | ||
| 738 | # | 769 | # |
| 739 | # Console display driver support | 770 | # Console display driver support |
| 740 | # | 771 | # |
| 741 | # CONFIG_VGA_CONSOLE is not set | 772 | # CONFIG_VGA_CONSOLE is not set |
| 742 | CONFIG_DUMMY_CONSOLE=y | 773 | CONFIG_DUMMY_CONSOLE=y |
| 743 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 774 | # CONFIG_FRAMEBUFFER_CONSOLE is not set |
| 775 | # CONFIG_LOGO is not set | ||
| 744 | 776 | ||
| 745 | # | 777 | # |
| 746 | # Sound | 778 | # Sound |
| 747 | # | 779 | # |
| 748 | # CONFIG_SOUND is not set | 780 | # CONFIG_SOUND is not set |
| 781 | CONFIG_HID_SUPPORT=y | ||
| 782 | CONFIG_HID=y | ||
| 783 | # CONFIG_HID_DEBUG is not set | ||
| 784 | # CONFIG_HIDRAW is not set | ||
| 749 | 785 | ||
| 750 | # | 786 | # |
| 751 | # USB support | 787 | # USB Input Devices |
| 752 | # | 788 | # |
| 789 | # CONFIG_USB_HID is not set | ||
| 790 | |||
| 791 | # | ||
| 792 | # USB HID Boot Protocol drivers | ||
| 793 | # | ||
| 794 | # CONFIG_USB_KBD is not set | ||
| 795 | # CONFIG_USB_MOUSE is not set | ||
| 796 | CONFIG_USB_SUPPORT=y | ||
| 753 | CONFIG_USB_ARCH_HAS_HCD=y | 797 | CONFIG_USB_ARCH_HAS_HCD=y |
| 754 | CONFIG_USB_ARCH_HAS_OHCI=y | 798 | CONFIG_USB_ARCH_HAS_OHCI=y |
| 755 | # CONFIG_USB_ARCH_HAS_EHCI is not set | 799 | # CONFIG_USB_ARCH_HAS_EHCI is not set |
| @@ -760,7 +804,7 @@ CONFIG_USB=y | |||
| 760 | # Miscellaneous USB options | 804 | # Miscellaneous USB options |
| 761 | # | 805 | # |
| 762 | CONFIG_USB_DEVICEFS=y | 806 | CONFIG_USB_DEVICEFS=y |
| 763 | # CONFIG_USB_BANDWIDTH is not set | 807 | CONFIG_USB_DEVICE_CLASS=y |
| 764 | # CONFIG_USB_DYNAMIC_MINORS is not set | 808 | # CONFIG_USB_DYNAMIC_MINORS is not set |
| 765 | # CONFIG_USB_OTG is not set | 809 | # CONFIG_USB_OTG is not set |
| 766 | 810 | ||
| @@ -769,9 +813,11 @@ CONFIG_USB_DEVICEFS=y | |||
| 769 | # | 813 | # |
| 770 | # CONFIG_USB_ISP116X_HCD is not set | 814 | # CONFIG_USB_ISP116X_HCD is not set |
| 771 | CONFIG_USB_OHCI_HCD=y | 815 | CONFIG_USB_OHCI_HCD=y |
| 772 | # CONFIG_USB_OHCI_BIG_ENDIAN is not set | 816 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set |
| 817 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 773 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | 818 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y |
| 774 | # CONFIG_USB_SL811_HCD is not set | 819 | # CONFIG_USB_SL811_HCD is not set |
| 820 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 775 | 821 | ||
| 776 | # | 822 | # |
| 777 | # USB Device Class drivers | 823 | # USB Device Class drivers |
| @@ -790,6 +836,7 @@ CONFIG_USB_STORAGE=y | |||
| 790 | CONFIG_USB_STORAGE_DEBUG=y | 836 | CONFIG_USB_STORAGE_DEBUG=y |
| 791 | # CONFIG_USB_STORAGE_DATAFAB is not set | 837 | # CONFIG_USB_STORAGE_DATAFAB is not set |
| 792 | # CONFIG_USB_STORAGE_FREECOM is not set | 838 | # CONFIG_USB_STORAGE_FREECOM is not set |
| 839 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 793 | # CONFIG_USB_STORAGE_DPCM is not set | 840 | # CONFIG_USB_STORAGE_DPCM is not set |
| 794 | # CONFIG_USB_STORAGE_USBAT is not set | 841 | # CONFIG_USB_STORAGE_USBAT is not set |
| 795 | # CONFIG_USB_STORAGE_SDDR09 is not set | 842 | # CONFIG_USB_STORAGE_SDDR09 is not set |
| @@ -800,43 +847,10 @@ CONFIG_USB_STORAGE_DEBUG=y | |||
| 800 | # CONFIG_USB_LIBUSUAL is not set | 847 | # CONFIG_USB_LIBUSUAL is not set |
| 801 | 848 | ||
| 802 | # | 849 | # |
| 803 | # USB Input Devices | ||
| 804 | # | ||
| 805 | # CONFIG_USB_HID is not set | ||
| 806 | |||
| 807 | # | ||
| 808 | # USB HID Boot Protocol drivers | ||
| 809 | # | ||
| 810 | # CONFIG_USB_KBD is not set | ||
| 811 | # CONFIG_USB_MOUSE is not set | ||
| 812 | # CONFIG_USB_AIPTEK is not set | ||
| 813 | # CONFIG_USB_WACOM is not set | ||
| 814 | # CONFIG_USB_ACECAD is not set | ||
| 815 | # CONFIG_USB_KBTAB is not set | ||
| 816 | # CONFIG_USB_POWERMATE is not set | ||
| 817 | # CONFIG_USB_TOUCHSCREEN is not set | ||
| 818 | # CONFIG_USB_YEALINK is not set | ||
| 819 | # CONFIG_USB_XPAD is not set | ||
| 820 | # CONFIG_USB_ATI_REMOTE is not set | ||
| 821 | # CONFIG_USB_ATI_REMOTE2 is not set | ||
| 822 | # CONFIG_USB_KEYSPAN_REMOTE is not set | ||
| 823 | # CONFIG_USB_APPLETOUCH is not set | ||
| 824 | |||
| 825 | # | ||
| 826 | # USB Imaging devices | 850 | # USB Imaging devices |
| 827 | # | 851 | # |
| 828 | # CONFIG_USB_MDC800 is not set | 852 | # CONFIG_USB_MDC800 is not set |
| 829 | # CONFIG_USB_MICROTEK is not set | 853 | # CONFIG_USB_MICROTEK is not set |
| 830 | |||
| 831 | # | ||
| 832 | # USB Network Adapters | ||
| 833 | # | ||
| 834 | # CONFIG_USB_CATC is not set | ||
| 835 | # CONFIG_USB_KAWETH is not set | ||
| 836 | # CONFIG_USB_PEGASUS is not set | ||
| 837 | # CONFIG_USB_RTL8150 is not set | ||
| 838 | # CONFIG_USB_USBNET_MII is not set | ||
| 839 | # CONFIG_USB_USBNET is not set | ||
| 840 | CONFIG_USB_MON=y | 854 | CONFIG_USB_MON=y |
| 841 | 855 | ||
| 842 | # | 856 | # |
| @@ -858,6 +872,7 @@ CONFIG_USB_MON=y | |||
| 858 | # CONFIG_USB_RIO500 is not set | 872 | # CONFIG_USB_RIO500 is not set |
| 859 | # CONFIG_USB_LEGOTOWER is not set | 873 | # CONFIG_USB_LEGOTOWER is not set |
| 860 | # CONFIG_USB_LCD is not set | 874 | # CONFIG_USB_LCD is not set |
| 875 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 861 | # CONFIG_USB_LED is not set | 876 | # CONFIG_USB_LED is not set |
| 862 | # CONFIG_USB_CYPRESS_CY7C63 is not set | 877 | # CONFIG_USB_CYPRESS_CY7C63 is not set |
| 863 | # CONFIG_USB_CYTHERM is not set | 878 | # CONFIG_USB_CYTHERM is not set |
| @@ -867,6 +882,7 @@ CONFIG_USB_MON=y | |||
| 867 | # CONFIG_USB_APPLEDISPLAY is not set | 882 | # CONFIG_USB_APPLEDISPLAY is not set |
| 868 | # CONFIG_USB_LD is not set | 883 | # CONFIG_USB_LD is not set |
| 869 | # CONFIG_USB_TRANCEVIBRATOR is not set | 884 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 885 | # CONFIG_USB_IOWARRIOR is not set | ||
| 870 | # CONFIG_USB_TEST is not set | 886 | # CONFIG_USB_TEST is not set |
| 871 | 887 | ||
| 872 | # | 888 | # |
| @@ -877,13 +893,19 @@ CONFIG_USB_MON=y | |||
| 877 | # USB Gadget Support | 893 | # USB Gadget Support |
| 878 | # | 894 | # |
| 879 | CONFIG_USB_GADGET=y | 895 | CONFIG_USB_GADGET=y |
| 896 | # CONFIG_USB_GADGET_DEBUG is not set | ||
| 880 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | 897 | # CONFIG_USB_GADGET_DEBUG_FILES is not set |
| 881 | CONFIG_USB_GADGET_SELECTED=y | 898 | CONFIG_USB_GADGET_SELECTED=y |
| 899 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 900 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 901 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 882 | # CONFIG_USB_GADGET_NET2280 is not set | 902 | # CONFIG_USB_GADGET_NET2280 is not set |
| 883 | # CONFIG_USB_GADGET_PXA2XX is not set | 903 | # CONFIG_USB_GADGET_PXA2XX is not set |
| 904 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 884 | # CONFIG_USB_GADGET_GOKU is not set | 905 | # CONFIG_USB_GADGET_GOKU is not set |
| 885 | # CONFIG_USB_GADGET_LH7A40X is not set | 906 | # CONFIG_USB_GADGET_LH7A40X is not set |
| 886 | # CONFIG_USB_GADGET_OMAP is not set | 907 | # CONFIG_USB_GADGET_OMAP is not set |
| 908 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 887 | CONFIG_USB_GADGET_AT91=y | 909 | CONFIG_USB_GADGET_AT91=y |
| 888 | CONFIG_USB_AT91=y | 910 | CONFIG_USB_AT91=y |
| 889 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | 911 | # CONFIG_USB_GADGET_DUMMY_HCD is not set |
| @@ -895,21 +917,73 @@ CONFIG_USB_FILE_STORAGE=m | |||
| 895 | # CONFIG_USB_FILE_STORAGE_TEST is not set | 917 | # CONFIG_USB_FILE_STORAGE_TEST is not set |
| 896 | CONFIG_USB_G_SERIAL=m | 918 | CONFIG_USB_G_SERIAL=m |
| 897 | # CONFIG_USB_MIDI_GADGET is not set | 919 | # CONFIG_USB_MIDI_GADGET is not set |
| 920 | CONFIG_MMC=y | ||
| 921 | # CONFIG_MMC_DEBUG is not set | ||
| 922 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 898 | 923 | ||
| 899 | # | 924 | # |
| 900 | # MMC/SD Card support | 925 | # MMC/SD Card Drivers |
| 901 | # | 926 | # |
| 902 | CONFIG_MMC=y | ||
| 903 | # CONFIG_MMC_DEBUG is not set | ||
| 904 | CONFIG_MMC_BLOCK=y | 927 | CONFIG_MMC_BLOCK=y |
| 905 | CONFIG_MMC_AT91=m | 928 | CONFIG_MMC_BLOCK_BOUNCE=y |
| 906 | # CONFIG_MMC_TIFM_SD is not set | 929 | # CONFIG_SDIO_UART is not set |
| 907 | 930 | ||
| 908 | # | 931 | # |
| 909 | # Real Time Clock | 932 | # MMC/SD Host Controller Drivers |
| 910 | # | 933 | # |
| 934 | CONFIG_MMC_AT91=y | ||
| 935 | # CONFIG_MMC_SPI is not set | ||
| 936 | # CONFIG_NEW_LEDS is not set | ||
| 911 | CONFIG_RTC_LIB=y | 937 | CONFIG_RTC_LIB=y |
| 912 | # CONFIG_RTC_CLASS is not set | 938 | CONFIG_RTC_CLASS=y |
| 939 | CONFIG_RTC_HCTOSYS=y | ||
| 940 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 941 | # CONFIG_RTC_DEBUG is not set | ||
| 942 | |||
| 943 | # | ||
| 944 | # RTC interfaces | ||
| 945 | # | ||
| 946 | CONFIG_RTC_INTF_SYSFS=y | ||
| 947 | CONFIG_RTC_INTF_PROC=y | ||
| 948 | CONFIG_RTC_INTF_DEV=y | ||
| 949 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 950 | # CONFIG_RTC_DRV_TEST is not set | ||
| 951 | |||
| 952 | # | ||
| 953 | # I2C RTC drivers | ||
| 954 | # | ||
| 955 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 956 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 957 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 958 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 959 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 960 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 961 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 962 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 963 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 964 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 965 | |||
| 966 | # | ||
| 967 | # SPI RTC drivers | ||
| 968 | # | ||
| 969 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 970 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 971 | |||
| 972 | # | ||
| 973 | # Platform RTC drivers | ||
| 974 | # | ||
| 975 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 976 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 977 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 978 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 979 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 980 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 981 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 982 | |||
| 983 | # | ||
| 984 | # on-CPU RTC drivers | ||
| 985 | # | ||
| 986 | CONFIG_RTC_DRV_AT91SAM9=y | ||
| 913 | 987 | ||
| 914 | # | 988 | # |
| 915 | # File systems | 989 | # File systems |
| @@ -960,7 +1034,6 @@ CONFIG_SYSFS=y | |||
| 960 | CONFIG_TMPFS=y | 1034 | CONFIG_TMPFS=y |
| 961 | # CONFIG_TMPFS_POSIX_ACL is not set | 1035 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 962 | # CONFIG_HUGETLB_PAGE is not set | 1036 | # CONFIG_HUGETLB_PAGE is not set |
| 963 | CONFIG_RAMFS=y | ||
| 964 | # CONFIG_CONFIGFS_FS is not set | 1037 | # CONFIG_CONFIGFS_FS is not set |
| 965 | 1038 | ||
| 966 | # | 1039 | # |
| @@ -973,7 +1046,6 @@ CONFIG_RAMFS=y | |||
| 973 | # CONFIG_BEFS_FS is not set | 1046 | # CONFIG_BEFS_FS is not set |
| 974 | # CONFIG_BFS_FS is not set | 1047 | # CONFIG_BFS_FS is not set |
| 975 | # CONFIG_EFS_FS is not set | 1048 | # CONFIG_EFS_FS is not set |
| 976 | # CONFIG_JFFS_FS is not set | ||
| 977 | # CONFIG_JFFS2_FS is not set | 1049 | # CONFIG_JFFS2_FS is not set |
| 978 | CONFIG_CRAMFS=y | 1050 | CONFIG_CRAMFS=y |
| 979 | # CONFIG_VXFS_FS is not set | 1051 | # CONFIG_VXFS_FS is not set |
| @@ -981,10 +1053,7 @@ CONFIG_CRAMFS=y | |||
| 981 | # CONFIG_QNX4FS_FS is not set | 1053 | # CONFIG_QNX4FS_FS is not set |
| 982 | # CONFIG_SYSV_FS is not set | 1054 | # CONFIG_SYSV_FS is not set |
| 983 | # CONFIG_UFS_FS is not set | 1055 | # CONFIG_UFS_FS is not set |
| 984 | 1056 | CONFIG_NETWORK_FILESYSTEMS=y | |
| 985 | # | ||
| 986 | # Network File Systems | ||
| 987 | # | ||
| 988 | # CONFIG_NFS_FS is not set | 1057 | # CONFIG_NFS_FS is not set |
| 989 | # CONFIG_NFSD is not set | 1058 | # CONFIG_NFSD is not set |
| 990 | # CONFIG_SMB_FS is not set | 1059 | # CONFIG_SMB_FS is not set |
| @@ -992,17 +1061,12 @@ CONFIG_CRAMFS=y | |||
| 992 | # CONFIG_NCP_FS is not set | 1061 | # CONFIG_NCP_FS is not set |
| 993 | # CONFIG_CODA_FS is not set | 1062 | # CONFIG_CODA_FS is not set |
| 994 | # CONFIG_AFS_FS is not set | 1063 | # CONFIG_AFS_FS is not set |
| 995 | # CONFIG_9P_FS is not set | ||
| 996 | 1064 | ||
| 997 | # | 1065 | # |
| 998 | # Partition Types | 1066 | # Partition Types |
| 999 | # | 1067 | # |
| 1000 | # CONFIG_PARTITION_ADVANCED is not set | 1068 | # CONFIG_PARTITION_ADVANCED is not set |
| 1001 | CONFIG_MSDOS_PARTITION=y | 1069 | CONFIG_MSDOS_PARTITION=y |
| 1002 | |||
| 1003 | # | ||
| 1004 | # Native Language Support | ||
| 1005 | # | ||
| 1006 | CONFIG_NLS=y | 1070 | CONFIG_NLS=y |
| 1007 | CONFIG_NLS_DEFAULT="iso8859-1" | 1071 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 1008 | CONFIG_NLS_CODEPAGE_437=y | 1072 | CONFIG_NLS_CODEPAGE_437=y |
| @@ -1043,41 +1107,49 @@ CONFIG_NLS_ISO8859_1=y | |||
| 1043 | # CONFIG_NLS_KOI8_R is not set | 1107 | # CONFIG_NLS_KOI8_R is not set |
| 1044 | # CONFIG_NLS_KOI8_U is not set | 1108 | # CONFIG_NLS_KOI8_U is not set |
| 1045 | # CONFIG_NLS_UTF8 is not set | 1109 | # CONFIG_NLS_UTF8 is not set |
| 1046 | 1110 | # CONFIG_DLM is not set | |
| 1047 | # | 1111 | CONFIG_INSTRUMENTATION=y |
| 1048 | # Profiling support | ||
| 1049 | # | ||
| 1050 | # CONFIG_PROFILING is not set | 1112 | # CONFIG_PROFILING is not set |
| 1113 | # CONFIG_MARKERS is not set | ||
| 1051 | 1114 | ||
| 1052 | # | 1115 | # |
| 1053 | # Kernel hacking | 1116 | # Kernel hacking |
| 1054 | # | 1117 | # |
| 1055 | # CONFIG_PRINTK_TIME is not set | 1118 | # CONFIG_PRINTK_TIME is not set |
| 1119 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1056 | CONFIG_ENABLE_MUST_CHECK=y | 1120 | CONFIG_ENABLE_MUST_CHECK=y |
| 1057 | # CONFIG_MAGIC_SYSRQ is not set | 1121 | # CONFIG_MAGIC_SYSRQ is not set |
| 1058 | # CONFIG_UNUSED_SYMBOLS is not set | 1122 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1123 | # CONFIG_DEBUG_FS is not set | ||
| 1124 | # CONFIG_HEADERS_CHECK is not set | ||
| 1059 | CONFIG_DEBUG_KERNEL=y | 1125 | CONFIG_DEBUG_KERNEL=y |
| 1060 | CONFIG_LOG_BUF_SHIFT=14 | 1126 | # CONFIG_DEBUG_SHIRQ is not set |
| 1061 | CONFIG_DETECT_SOFTLOCKUP=y | 1127 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1128 | CONFIG_SCHED_DEBUG=y | ||
| 1062 | # CONFIG_SCHEDSTATS is not set | 1129 | # CONFIG_SCHEDSTATS is not set |
| 1130 | # CONFIG_TIMER_STATS is not set | ||
| 1063 | # CONFIG_DEBUG_SLAB is not set | 1131 | # CONFIG_DEBUG_SLAB is not set |
| 1064 | # CONFIG_DEBUG_RT_MUTEXES is not set | 1132 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| 1065 | # CONFIG_RT_MUTEX_TESTER is not set | 1133 | # CONFIG_RT_MUTEX_TESTER is not set |
| 1066 | # CONFIG_DEBUG_SPINLOCK is not set | 1134 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1067 | # CONFIG_DEBUG_MUTEXES is not set | 1135 | # CONFIG_DEBUG_MUTEXES is not set |
| 1068 | # CONFIG_DEBUG_RWSEMS is not set | 1136 | # CONFIG_DEBUG_LOCK_ALLOC is not set |
| 1137 | # CONFIG_PROVE_LOCKING is not set | ||
| 1138 | # CONFIG_LOCK_STAT is not set | ||
| 1069 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1139 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1070 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | 1140 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set |
| 1071 | # CONFIG_DEBUG_KOBJECT is not set | 1141 | # CONFIG_DEBUG_KOBJECT is not set |
| 1072 | CONFIG_DEBUG_BUGVERBOSE=y | 1142 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1073 | # CONFIG_DEBUG_INFO is not set | 1143 | # CONFIG_DEBUG_INFO is not set |
| 1074 | # CONFIG_DEBUG_FS is not set | ||
| 1075 | # CONFIG_DEBUG_VM is not set | 1144 | # CONFIG_DEBUG_VM is not set |
| 1076 | # CONFIG_DEBUG_LIST is not set | 1145 | # CONFIG_DEBUG_LIST is not set |
| 1146 | # CONFIG_DEBUG_SG is not set | ||
| 1077 | CONFIG_FRAME_POINTER=y | 1147 | CONFIG_FRAME_POINTER=y |
| 1078 | CONFIG_FORCED_INLINING=y | 1148 | CONFIG_FORCED_INLINING=y |
| 1079 | # CONFIG_HEADERS_CHECK is not set | 1149 | # CONFIG_BOOT_PRINTK_DELAY is not set |
| 1080 | # CONFIG_RCU_TORTURE_TEST is not set | 1150 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1151 | # CONFIG_FAULT_INJECTION is not set | ||
| 1152 | # CONFIG_SAMPLES is not set | ||
| 1081 | CONFIG_DEBUG_USER=y | 1153 | CONFIG_DEBUG_USER=y |
| 1082 | # CONFIG_DEBUG_ERRORS is not set | 1154 | # CONFIG_DEBUG_ERRORS is not set |
| 1083 | CONFIG_DEBUG_LL=y | 1155 | CONFIG_DEBUG_LL=y |
| @@ -1088,18 +1160,21 @@ CONFIG_DEBUG_LL=y | |||
| 1088 | # | 1160 | # |
| 1089 | # CONFIG_KEYS is not set | 1161 | # CONFIG_KEYS is not set |
| 1090 | # CONFIG_SECURITY is not set | 1162 | # CONFIG_SECURITY is not set |
| 1091 | 1163 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | |
| 1092 | # | ||
| 1093 | # Cryptographic options | ||
| 1094 | # | ||
| 1095 | # CONFIG_CRYPTO is not set | 1164 | # CONFIG_CRYPTO is not set |
| 1096 | 1165 | ||
| 1097 | # | 1166 | # |
| 1098 | # Library routines | 1167 | # Library routines |
| 1099 | # | 1168 | # |
| 1169 | CONFIG_BITREVERSE=y | ||
| 1100 | # CONFIG_CRC_CCITT is not set | 1170 | # CONFIG_CRC_CCITT is not set |
| 1101 | # CONFIG_CRC16 is not set | 1171 | # CONFIG_CRC16 is not set |
| 1172 | # CONFIG_CRC_ITU_T is not set | ||
| 1102 | CONFIG_CRC32=y | 1173 | CONFIG_CRC32=y |
| 1174 | # CONFIG_CRC7 is not set | ||
| 1103 | # CONFIG_LIBCRC32C is not set | 1175 | # CONFIG_LIBCRC32C is not set |
| 1104 | CONFIG_ZLIB_INFLATE=y | 1176 | CONFIG_ZLIB_INFLATE=y |
| 1105 | CONFIG_PLIST=y | 1177 | CONFIG_PLIST=y |
| 1178 | CONFIG_HAS_IOMEM=y | ||
| 1179 | CONFIG_HAS_IOPORT=y | ||
| 1180 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/at91sam9263ek_defconfig b/arch/arm/configs/at91sam9263ek_defconfig index c72ab82873d5..32a0d74e0c89 100644 --- a/arch/arm/configs/at91sam9263ek_defconfig +++ b/arch/arm/configs/at91sam9263ek_defconfig | |||
| @@ -1,12 +1,18 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.20-rc1 | 3 | # Linux kernel version: 2.6.24-rc7 |
| 4 | # Mon Jan 8 16:06:54 2007 | 4 | # Tue Jan 8 22:12:20 2008 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 7 | # CONFIG_GENERIC_TIME is not set | 9 | # CONFIG_GENERIC_TIME is not set |
| 10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
| 8 | CONFIG_MMU=y | 11 | CONFIG_MMU=y |
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 9 | CONFIG_GENERIC_HARDIRQS=y | 13 | CONFIG_GENERIC_HARDIRQS=y |
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 10 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y |
| 11 | CONFIG_HARDIRQS_SW_RESEND=y | 17 | CONFIG_HARDIRQS_SW_RESEND=y |
| 12 | CONFIG_GENERIC_IRQ_PROBE=y | 18 | CONFIG_GENERIC_IRQ_PROBE=y |
| @@ -15,32 +21,36 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 15 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set |
| 16 | CONFIG_GENERIC_HWEIGHT=y | 22 | CONFIG_GENERIC_HWEIGHT=y |
| 17 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 24 | CONFIG_ZONE_DMA=y | ||
| 18 | CONFIG_VECTORS_BASE=0xffff0000 | 25 | CONFIG_VECTORS_BASE=0xffff0000 |
| 19 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 26 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 20 | 27 | ||
| 21 | # | 28 | # |
| 22 | # Code maturity level options | 29 | # General setup |
| 23 | # | 30 | # |
| 24 | CONFIG_EXPERIMENTAL=y | 31 | CONFIG_EXPERIMENTAL=y |
| 25 | CONFIG_BROKEN_ON_SMP=y | 32 | CONFIG_BROKEN_ON_SMP=y |
| 26 | CONFIG_INIT_ENV_ARG_LIMIT=32 | 33 | CONFIG_INIT_ENV_ARG_LIMIT=32 |
| 27 | |||
| 28 | # | ||
| 29 | # General setup | ||
| 30 | # | ||
| 31 | CONFIG_LOCALVERSION="" | 34 | CONFIG_LOCALVERSION="" |
| 32 | # CONFIG_LOCALVERSION_AUTO is not set | 35 | # CONFIG_LOCALVERSION_AUTO is not set |
| 33 | # CONFIG_SWAP is not set | 36 | # CONFIG_SWAP is not set |
| 34 | CONFIG_SYSVIPC=y | 37 | CONFIG_SYSVIPC=y |
| 35 | # CONFIG_IPC_NS is not set | 38 | CONFIG_SYSVIPC_SYSCTL=y |
| 36 | # CONFIG_POSIX_MQUEUE is not set | 39 | # CONFIG_POSIX_MQUEUE is not set |
| 37 | # CONFIG_BSD_PROCESS_ACCT is not set | 40 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 38 | # CONFIG_TASKSTATS is not set | 41 | # CONFIG_TASKSTATS is not set |
| 39 | # CONFIG_UTS_NS is not set | 42 | # CONFIG_USER_NS is not set |
| 43 | # CONFIG_PID_NS is not set | ||
| 40 | # CONFIG_AUDIT is not set | 44 | # CONFIG_AUDIT is not set |
| 41 | # CONFIG_IKCONFIG is not set | 45 | # CONFIG_IKCONFIG is not set |
| 46 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 47 | # CONFIG_CGROUPS is not set | ||
| 48 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 49 | CONFIG_FAIR_USER_SCHED=y | ||
| 50 | # CONFIG_FAIR_CGROUP_SCHED is not set | ||
| 42 | CONFIG_SYSFS_DEPRECATED=y | 51 | CONFIG_SYSFS_DEPRECATED=y |
| 43 | # CONFIG_RELAY is not set | 52 | # CONFIG_RELAY is not set |
| 53 | CONFIG_BLK_DEV_INITRD=y | ||
| 44 | CONFIG_INITRAMFS_SOURCE="" | 54 | CONFIG_INITRAMFS_SOURCE="" |
| 45 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 55 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 46 | CONFIG_SYSCTL=y | 56 | CONFIG_SYSCTL=y |
| @@ -56,32 +66,30 @@ CONFIG_BUG=y | |||
| 56 | CONFIG_ELF_CORE=y | 66 | CONFIG_ELF_CORE=y |
| 57 | CONFIG_BASE_FULL=y | 67 | CONFIG_BASE_FULL=y |
| 58 | CONFIG_FUTEX=y | 68 | CONFIG_FUTEX=y |
| 69 | CONFIG_ANON_INODES=y | ||
| 59 | CONFIG_EPOLL=y | 70 | CONFIG_EPOLL=y |
| 71 | CONFIG_SIGNALFD=y | ||
| 72 | CONFIG_EVENTFD=y | ||
| 60 | CONFIG_SHMEM=y | 73 | CONFIG_SHMEM=y |
| 61 | CONFIG_SLAB=y | ||
| 62 | CONFIG_VM_EVENT_COUNTERS=y | 74 | CONFIG_VM_EVENT_COUNTERS=y |
| 75 | CONFIG_SLAB=y | ||
| 76 | # CONFIG_SLUB is not set | ||
| 77 | # CONFIG_SLOB is not set | ||
| 78 | CONFIG_SLABINFO=y | ||
| 63 | CONFIG_RT_MUTEXES=y | 79 | CONFIG_RT_MUTEXES=y |
| 64 | # CONFIG_TINY_SHMEM is not set | 80 | # CONFIG_TINY_SHMEM is not set |
| 65 | CONFIG_BASE_SMALL=0 | 81 | CONFIG_BASE_SMALL=0 |
| 66 | # CONFIG_SLOB is not set | ||
| 67 | |||
| 68 | # | ||
| 69 | # Loadable module support | ||
| 70 | # | ||
| 71 | CONFIG_MODULES=y | 82 | CONFIG_MODULES=y |
| 72 | CONFIG_MODULE_UNLOAD=y | 83 | CONFIG_MODULE_UNLOAD=y |
| 73 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 84 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 74 | # CONFIG_MODVERSIONS is not set | 85 | # CONFIG_MODVERSIONS is not set |
| 75 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 86 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 76 | CONFIG_KMOD=y | 87 | CONFIG_KMOD=y |
| 77 | |||
| 78 | # | ||
| 79 | # Block layer | ||
| 80 | # | ||
| 81 | CONFIG_BLOCK=y | 88 | CONFIG_BLOCK=y |
| 82 | # CONFIG_LBD is not set | 89 | # CONFIG_LBD is not set |
| 83 | # CONFIG_BLK_DEV_IO_TRACE is not set | 90 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 84 | # CONFIG_LSF is not set | 91 | # CONFIG_LSF is not set |
| 92 | # CONFIG_BLK_DEV_BSG is not set | ||
| 85 | 93 | ||
| 86 | # | 94 | # |
| 87 | # IO Schedulers | 95 | # IO Schedulers |
| @@ -113,13 +121,16 @@ CONFIG_ARCH_AT91=y | |||
| 113 | # CONFIG_ARCH_NETX is not set | 121 | # CONFIG_ARCH_NETX is not set |
| 114 | # CONFIG_ARCH_H720X is not set | 122 | # CONFIG_ARCH_H720X is not set |
| 115 | # CONFIG_ARCH_IMX is not set | 123 | # CONFIG_ARCH_IMX is not set |
| 124 | # CONFIG_ARCH_IOP13XX is not set | ||
| 116 | # CONFIG_ARCH_IOP32X is not set | 125 | # CONFIG_ARCH_IOP32X is not set |
| 117 | # CONFIG_ARCH_IOP33X is not set | 126 | # CONFIG_ARCH_IOP33X is not set |
| 118 | # CONFIG_ARCH_IOP13XX is not set | ||
| 119 | # CONFIG_ARCH_IXP4XX is not set | ||
| 120 | # CONFIG_ARCH_IXP2000 is not set | ||
| 121 | # CONFIG_ARCH_IXP23XX is not set | 127 | # CONFIG_ARCH_IXP23XX is not set |
| 128 | # CONFIG_ARCH_IXP2000 is not set | ||
| 129 | # CONFIG_ARCH_IXP4XX is not set | ||
| 122 | # CONFIG_ARCH_L7200 is not set | 130 | # CONFIG_ARCH_L7200 is not set |
| 131 | # CONFIG_ARCH_KS8695 is not set | ||
| 132 | # CONFIG_ARCH_NS9XXX is not set | ||
| 133 | # CONFIG_ARCH_MXC is not set | ||
| 123 | # CONFIG_ARCH_PNX4008 is not set | 134 | # CONFIG_ARCH_PNX4008 is not set |
| 124 | # CONFIG_ARCH_PXA is not set | 135 | # CONFIG_ARCH_PXA is not set |
| 125 | # CONFIG_ARCH_RPC is not set | 136 | # CONFIG_ARCH_RPC is not set |
| @@ -127,15 +138,27 @@ CONFIG_ARCH_AT91=y | |||
| 127 | # CONFIG_ARCH_S3C2410 is not set | 138 | # CONFIG_ARCH_S3C2410 is not set |
| 128 | # CONFIG_ARCH_SHARK is not set | 139 | # CONFIG_ARCH_SHARK is not set |
| 129 | # CONFIG_ARCH_LH7A40X is not set | 140 | # CONFIG_ARCH_LH7A40X is not set |
| 141 | # CONFIG_ARCH_DAVINCI is not set | ||
| 130 | # CONFIG_ARCH_OMAP is not set | 142 | # CONFIG_ARCH_OMAP is not set |
| 131 | 143 | ||
| 132 | # | 144 | # |
| 145 | # Boot options | ||
| 146 | # | ||
| 147 | |||
| 148 | # | ||
| 149 | # Power management | ||
| 150 | # | ||
| 151 | |||
| 152 | # | ||
| 133 | # Atmel AT91 System-on-Chip | 153 | # Atmel AT91 System-on-Chip |
| 134 | # | 154 | # |
| 135 | # CONFIG_ARCH_AT91RM9200 is not set | 155 | # CONFIG_ARCH_AT91RM9200 is not set |
| 136 | # CONFIG_ARCH_AT91SAM9260 is not set | 156 | # CONFIG_ARCH_AT91SAM9260 is not set |
| 137 | # CONFIG_ARCH_AT91SAM9261 is not set | 157 | # CONFIG_ARCH_AT91SAM9261 is not set |
| 138 | CONFIG_ARCH_AT91SAM9263=y | 158 | CONFIG_ARCH_AT91SAM9263=y |
| 159 | # CONFIG_ARCH_AT91SAM9RL is not set | ||
| 160 | # CONFIG_ARCH_AT91X40 is not set | ||
| 161 | CONFIG_AT91_PMC_UNIT=y | ||
| 139 | 162 | ||
| 140 | # | 163 | # |
| 141 | # AT91SAM9263 Board Type | 164 | # AT91SAM9263 Board Type |
| @@ -152,6 +175,8 @@ CONFIG_MTD_AT91_DATAFLASH_CARD=y | |||
| 152 | # AT91 Feature Selections | 175 | # AT91 Feature Selections |
| 153 | # | 176 | # |
| 154 | # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set | 177 | # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set |
| 178 | # CONFIG_ATMEL_TCLIB is not set | ||
| 179 | CONFIG_AT91_TIMER_HZ=100 | ||
| 155 | 180 | ||
| 156 | # | 181 | # |
| 157 | # Processor Type | 182 | # Processor Type |
| @@ -174,19 +199,19 @@ CONFIG_CPU_CP15_MMU=y | |||
| 174 | # CONFIG_CPU_DCACHE_DISABLE is not set | 199 | # CONFIG_CPU_DCACHE_DISABLE is not set |
| 175 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | 200 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set |
| 176 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set | 201 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set |
| 202 | # CONFIG_OUTER_CACHE is not set | ||
| 177 | 203 | ||
| 178 | # | 204 | # |
| 179 | # Bus support | 205 | # Bus support |
| 180 | # | 206 | # |
| 181 | 207 | # CONFIG_PCI_SYSCALL is not set | |
| 182 | # | 208 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 183 | # PCCARD (PCMCIA/CardBus) support | ||
| 184 | # | ||
| 185 | # CONFIG_PCCARD is not set | 209 | # CONFIG_PCCARD is not set |
| 186 | 210 | ||
| 187 | # | 211 | # |
| 188 | # Kernel Features | 212 | # Kernel Features |
| 189 | # | 213 | # |
| 214 | # CONFIG_TICK_ONESHOT is not set | ||
| 190 | # CONFIG_PREEMPT is not set | 215 | # CONFIG_PREEMPT is not set |
| 191 | # CONFIG_NO_IDLE_HZ is not set | 216 | # CONFIG_NO_IDLE_HZ is not set |
| 192 | CONFIG_HZ=100 | 217 | CONFIG_HZ=100 |
| @@ -199,8 +224,12 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 199 | CONFIG_FLATMEM=y | 224 | CONFIG_FLATMEM=y |
| 200 | CONFIG_FLAT_NODE_MEM_MAP=y | 225 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 201 | # CONFIG_SPARSEMEM_STATIC is not set | 226 | # CONFIG_SPARSEMEM_STATIC is not set |
| 227 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 202 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 228 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 203 | # CONFIG_RESOURCES_64BIT is not set | 229 | # CONFIG_RESOURCES_64BIT is not set |
| 230 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 231 | CONFIG_BOUNCE=y | ||
| 232 | CONFIG_VIRT_TO_BUS=y | ||
| 204 | # CONFIG_LEDS is not set | 233 | # CONFIG_LEDS is not set |
| 205 | CONFIG_ALIGNMENT_TRAP=y | 234 | CONFIG_ALIGNMENT_TRAP=y |
| 206 | 235 | ||
| @@ -211,6 +240,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 | |||
| 211 | CONFIG_ZBOOT_ROM_BSS=0x0 | 240 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 212 | CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" | 241 | CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" |
| 213 | # CONFIG_XIP_KERNEL is not set | 242 | # CONFIG_XIP_KERNEL is not set |
| 243 | # CONFIG_KEXEC is not set | ||
| 214 | 244 | ||
| 215 | # | 245 | # |
| 216 | # Floating point emulation | 246 | # Floating point emulation |
| @@ -236,7 +266,7 @@ CONFIG_BINFMT_ELF=y | |||
| 236 | # Power management options | 266 | # Power management options |
| 237 | # | 267 | # |
| 238 | # CONFIG_PM is not set | 268 | # CONFIG_PM is not set |
| 239 | # CONFIG_APM is not set | 269 | CONFIG_SUSPEND_UP_POSSIBLE=y |
| 240 | 270 | ||
| 241 | # | 271 | # |
| 242 | # Networking | 272 | # Networking |
| @@ -246,7 +276,6 @@ CONFIG_NET=y | |||
| 246 | # | 276 | # |
| 247 | # Networking options | 277 | # Networking options |
| 248 | # | 278 | # |
| 249 | # CONFIG_NETDEBUG is not set | ||
| 250 | CONFIG_PACKET=y | 279 | CONFIG_PACKET=y |
| 251 | # CONFIG_PACKET_MMAP is not set | 280 | # CONFIG_PACKET_MMAP is not set |
| 252 | CONFIG_UNIX=y | 281 | CONFIG_UNIX=y |
| @@ -271,6 +300,7 @@ CONFIG_IP_PNP_RARP=y | |||
| 271 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | 300 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 272 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | 301 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 273 | # CONFIG_INET_XFRM_MODE_BEET is not set | 302 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 303 | # CONFIG_INET_LRO is not set | ||
| 274 | # CONFIG_INET_DIAG is not set | 304 | # CONFIG_INET_DIAG is not set |
| 275 | # CONFIG_TCP_CONG_ADVANCED is not set | 305 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 276 | CONFIG_TCP_CONG_CUBIC=y | 306 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -281,20 +311,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 281 | # CONFIG_INET6_TUNNEL is not set | 311 | # CONFIG_INET6_TUNNEL is not set |
| 282 | # CONFIG_NETWORK_SECMARK is not set | 312 | # CONFIG_NETWORK_SECMARK is not set |
| 283 | # CONFIG_NETFILTER is not set | 313 | # CONFIG_NETFILTER is not set |
| 284 | |||
| 285 | # | ||
| 286 | # DCCP Configuration (EXPERIMENTAL) | ||
| 287 | # | ||
| 288 | # CONFIG_IP_DCCP is not set | 314 | # CONFIG_IP_DCCP is not set |
| 289 | |||
| 290 | # | ||
| 291 | # SCTP Configuration (EXPERIMENTAL) | ||
| 292 | # | ||
| 293 | # CONFIG_IP_SCTP is not set | 315 | # CONFIG_IP_SCTP is not set |
| 294 | |||
| 295 | # | ||
| 296 | # TIPC Configuration (EXPERIMENTAL) | ||
| 297 | # | ||
| 298 | # CONFIG_TIPC is not set | 316 | # CONFIG_TIPC is not set |
| 299 | # CONFIG_ATM is not set | 317 | # CONFIG_ATM is not set |
| 300 | # CONFIG_BRIDGE is not set | 318 | # CONFIG_BRIDGE is not set |
| @@ -307,10 +325,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 307 | # CONFIG_LAPB is not set | 325 | # CONFIG_LAPB is not set |
| 308 | # CONFIG_ECONET is not set | 326 | # CONFIG_ECONET is not set |
| 309 | # CONFIG_WAN_ROUTER is not set | 327 | # CONFIG_WAN_ROUTER is not set |
| 310 | |||
| 311 | # | ||
| 312 | # QoS and/or fair queueing | ||
| 313 | # | ||
| 314 | # CONFIG_NET_SCHED is not set | 328 | # CONFIG_NET_SCHED is not set |
| 315 | 329 | ||
| 316 | # | 330 | # |
| @@ -320,7 +334,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 320 | # CONFIG_HAMRADIO is not set | 334 | # CONFIG_HAMRADIO is not set |
| 321 | # CONFIG_IRDA is not set | 335 | # CONFIG_IRDA is not set |
| 322 | # CONFIG_BT is not set | 336 | # CONFIG_BT is not set |
| 337 | # CONFIG_AF_RXRPC is not set | ||
| 338 | |||
| 339 | # | ||
| 340 | # Wireless | ||
| 341 | # | ||
| 342 | # CONFIG_CFG80211 is not set | ||
| 343 | # CONFIG_WIRELESS_EXT is not set | ||
| 344 | # CONFIG_MAC80211 is not set | ||
| 323 | # CONFIG_IEEE80211 is not set | 345 | # CONFIG_IEEE80211 is not set |
| 346 | # CONFIG_RFKILL is not set | ||
| 347 | # CONFIG_NET_9P is not set | ||
| 324 | 348 | ||
| 325 | # | 349 | # |
| 326 | # Device Drivers | 350 | # Device Drivers |
| @@ -329,20 +353,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 329 | # | 353 | # |
| 330 | # Generic Driver Options | 354 | # Generic Driver Options |
| 331 | # | 355 | # |
| 356 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 332 | CONFIG_STANDALONE=y | 357 | CONFIG_STANDALONE=y |
| 333 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 358 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 334 | # CONFIG_FW_LOADER is not set | 359 | # CONFIG_FW_LOADER is not set |
| 335 | # CONFIG_DEBUG_DRIVER is not set | 360 | # CONFIG_DEBUG_DRIVER is not set |
| 361 | # CONFIG_DEBUG_DEVRES is not set | ||
| 336 | # CONFIG_SYS_HYPERVISOR is not set | 362 | # CONFIG_SYS_HYPERVISOR is not set |
| 337 | |||
| 338 | # | ||
| 339 | # Connector - unified userspace <-> kernelspace linker | ||
| 340 | # | ||
| 341 | # CONFIG_CONNECTOR is not set | 363 | # CONFIG_CONNECTOR is not set |
| 342 | |||
| 343 | # | ||
| 344 | # Memory Technology Devices (MTD) | ||
| 345 | # | ||
| 346 | CONFIG_MTD=y | 364 | CONFIG_MTD=y |
| 347 | # CONFIG_MTD_DEBUG is not set | 365 | # CONFIG_MTD_DEBUG is not set |
| 348 | # CONFIG_MTD_CONCAT is not set | 366 | # CONFIG_MTD_CONCAT is not set |
| @@ -362,6 +380,7 @@ CONFIG_MTD_BLOCK=y | |||
| 362 | # CONFIG_INFTL is not set | 380 | # CONFIG_INFTL is not set |
| 363 | # CONFIG_RFD_FTL is not set | 381 | # CONFIG_RFD_FTL is not set |
| 364 | # CONFIG_SSFDC is not set | 382 | # CONFIG_SSFDC is not set |
| 383 | # CONFIG_MTD_OOPS is not set | ||
| 365 | 384 | ||
| 366 | # | 385 | # |
| 367 | # RAM/ROM/Flash chip drivers | 386 | # RAM/ROM/Flash chip drivers |
| @@ -381,7 +400,6 @@ CONFIG_MTD_CFI_I2=y | |||
| 381 | # CONFIG_MTD_RAM is not set | 400 | # CONFIG_MTD_RAM is not set |
| 382 | # CONFIG_MTD_ROM is not set | 401 | # CONFIG_MTD_ROM is not set |
| 383 | # CONFIG_MTD_ABSENT is not set | 402 | # CONFIG_MTD_ABSENT is not set |
| 384 | # CONFIG_MTD_OBSOLETE_CHIPS is not set | ||
| 385 | 403 | ||
| 386 | # | 404 | # |
| 387 | # Mapping drivers for chip access | 405 | # Mapping drivers for chip access |
| @@ -405,35 +423,24 @@ CONFIG_MTD_DATAFLASH=y | |||
| 405 | # CONFIG_MTD_DOC2000 is not set | 423 | # CONFIG_MTD_DOC2000 is not set |
| 406 | # CONFIG_MTD_DOC2001 is not set | 424 | # CONFIG_MTD_DOC2001 is not set |
| 407 | # CONFIG_MTD_DOC2001PLUS is not set | 425 | # CONFIG_MTD_DOC2001PLUS is not set |
| 408 | |||
| 409 | # | ||
| 410 | # NAND Flash Device Drivers | ||
| 411 | # | ||
| 412 | CONFIG_MTD_NAND=y | 426 | CONFIG_MTD_NAND=y |
| 413 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | 427 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set |
| 414 | # CONFIG_MTD_NAND_ECC_SMC is not set | 428 | # CONFIG_MTD_NAND_ECC_SMC is not set |
| 429 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 415 | CONFIG_MTD_NAND_IDS=y | 430 | CONFIG_MTD_NAND_IDS=y |
| 416 | # CONFIG_MTD_NAND_DISKONCHIP is not set | 431 | # CONFIG_MTD_NAND_DISKONCHIP is not set |
| 417 | CONFIG_MTD_NAND_AT91=y | 432 | CONFIG_MTD_NAND_AT91=y |
| 418 | # CONFIG_MTD_NAND_NANDSIM is not set | 433 | # CONFIG_MTD_NAND_NANDSIM is not set |
| 419 | 434 | # CONFIG_MTD_NAND_PLATFORM is not set | |
| 420 | # | 435 | # CONFIG_MTD_ALAUDA is not set |
| 421 | # OneNAND Flash Device Drivers | ||
| 422 | # | ||
| 423 | # CONFIG_MTD_ONENAND is not set | 436 | # CONFIG_MTD_ONENAND is not set |
| 424 | 437 | ||
| 425 | # | 438 | # |
| 426 | # Parallel port support | 439 | # UBI - Unsorted block images |
| 427 | # | 440 | # |
| 441 | # CONFIG_MTD_UBI is not set | ||
| 428 | # CONFIG_PARPORT is not set | 442 | # CONFIG_PARPORT is not set |
| 429 | 443 | CONFIG_BLK_DEV=y | |
| 430 | # | ||
| 431 | # Plug and Play support | ||
| 432 | # | ||
| 433 | |||
| 434 | # | ||
| 435 | # Block devices | ||
| 436 | # | ||
| 437 | # CONFIG_BLK_DEV_COW_COMMON is not set | 444 | # CONFIG_BLK_DEV_COW_COMMON is not set |
| 438 | CONFIG_BLK_DEV_LOOP=y | 445 | CONFIG_BLK_DEV_LOOP=y |
| 439 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | 446 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set |
| @@ -443,15 +450,18 @@ CONFIG_BLK_DEV_RAM=y | |||
| 443 | CONFIG_BLK_DEV_RAM_COUNT=16 | 450 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 444 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 451 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 445 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 452 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 |
| 446 | CONFIG_BLK_DEV_INITRD=y | ||
| 447 | # CONFIG_CDROM_PKTCDVD is not set | 453 | # CONFIG_CDROM_PKTCDVD is not set |
| 448 | # CONFIG_ATA_OVER_ETH is not set | 454 | # CONFIG_ATA_OVER_ETH is not set |
| 455 | CONFIG_MISC_DEVICES=y | ||
| 456 | # CONFIG_EEPROM_93CX6 is not set | ||
| 457 | CONFIG_ATMEL_SSC=y | ||
| 449 | 458 | ||
| 450 | # | 459 | # |
| 451 | # SCSI device support | 460 | # SCSI device support |
| 452 | # | 461 | # |
| 453 | # CONFIG_RAID_ATTRS is not set | 462 | # CONFIG_RAID_ATTRS is not set |
| 454 | CONFIG_SCSI=y | 463 | CONFIG_SCSI=y |
| 464 | CONFIG_SCSI_DMA=y | ||
| 455 | # CONFIG_SCSI_TGT is not set | 465 | # CONFIG_SCSI_TGT is not set |
| 456 | # CONFIG_SCSI_NETLINK is not set | 466 | # CONFIG_SCSI_NETLINK is not set |
| 457 | CONFIG_SCSI_PROC_FS=y | 467 | CONFIG_SCSI_PROC_FS=y |
| @@ -473,6 +483,7 @@ CONFIG_SCSI_MULTI_LUN=y | |||
| 473 | # CONFIG_SCSI_CONSTANTS is not set | 483 | # CONFIG_SCSI_CONSTANTS is not set |
| 474 | # CONFIG_SCSI_LOGGING is not set | 484 | # CONFIG_SCSI_LOGGING is not set |
| 475 | # CONFIG_SCSI_SCAN_ASYNC is not set | 485 | # CONFIG_SCSI_SCAN_ASYNC is not set |
| 486 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 476 | 487 | ||
| 477 | # | 488 | # |
| 478 | # SCSI Transports | 489 | # SCSI Transports |
| @@ -480,80 +491,65 @@ CONFIG_SCSI_MULTI_LUN=y | |||
| 480 | # CONFIG_SCSI_SPI_ATTRS is not set | 491 | # CONFIG_SCSI_SPI_ATTRS is not set |
| 481 | # CONFIG_SCSI_FC_ATTRS is not set | 492 | # CONFIG_SCSI_FC_ATTRS is not set |
| 482 | # CONFIG_SCSI_ISCSI_ATTRS is not set | 493 | # CONFIG_SCSI_ISCSI_ATTRS is not set |
| 483 | # CONFIG_SCSI_SAS_ATTRS is not set | ||
| 484 | # CONFIG_SCSI_SAS_LIBSAS is not set | 494 | # CONFIG_SCSI_SAS_LIBSAS is not set |
| 485 | 495 | # CONFIG_SCSI_SRP_ATTRS is not set | |
| 486 | # | 496 | CONFIG_SCSI_LOWLEVEL=y |
| 487 | # SCSI low-level drivers | ||
| 488 | # | ||
| 489 | # CONFIG_ISCSI_TCP is not set | 497 | # CONFIG_ISCSI_TCP is not set |
| 490 | # CONFIG_SCSI_DEBUG is not set | 498 | # CONFIG_SCSI_DEBUG is not set |
| 491 | |||
| 492 | # | ||
| 493 | # Serial ATA (prod) and Parallel ATA (experimental) drivers | ||
| 494 | # | ||
| 495 | # CONFIG_ATA is not set | 499 | # CONFIG_ATA is not set |
| 496 | |||
| 497 | # | ||
| 498 | # Multi-device support (RAID and LVM) | ||
| 499 | # | ||
| 500 | # CONFIG_MD is not set | 500 | # CONFIG_MD is not set |
| 501 | |||
| 502 | # | ||
| 503 | # Fusion MPT device support | ||
| 504 | # | ||
| 505 | # CONFIG_FUSION is not set | ||
| 506 | |||
| 507 | # | ||
| 508 | # IEEE 1394 (FireWire) support | ||
| 509 | # | ||
| 510 | |||
| 511 | # | ||
| 512 | # I2O device support | ||
| 513 | # | ||
| 514 | |||
| 515 | # | ||
| 516 | # Network device support | ||
| 517 | # | ||
| 518 | CONFIG_NETDEVICES=y | 501 | CONFIG_NETDEVICES=y |
| 502 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 519 | # CONFIG_DUMMY is not set | 503 | # CONFIG_DUMMY is not set |
| 520 | # CONFIG_BONDING is not set | 504 | # CONFIG_BONDING is not set |
| 505 | # CONFIG_MACVLAN is not set | ||
| 521 | # CONFIG_EQUALIZER is not set | 506 | # CONFIG_EQUALIZER is not set |
| 522 | # CONFIG_TUN is not set | 507 | # CONFIG_TUN is not set |
| 523 | 508 | # CONFIG_VETH is not set | |
| 524 | # | 509 | CONFIG_PHYLIB=y |
| 525 | # PHY device support | 510 | |
| 526 | # | 511 | # |
| 527 | # CONFIG_PHYLIB is not set | 512 | # MII PHY device drivers |
| 528 | 513 | # | |
| 529 | # | 514 | # CONFIG_MARVELL_PHY is not set |
| 530 | # Ethernet (10 or 100Mbit) | 515 | # CONFIG_DAVICOM_PHY is not set |
| 531 | # | 516 | # CONFIG_QSEMI_PHY is not set |
| 517 | # CONFIG_LXT_PHY is not set | ||
| 518 | # CONFIG_CICADA_PHY is not set | ||
| 519 | # CONFIG_VITESSE_PHY is not set | ||
| 520 | # CONFIG_SMSC_PHY is not set | ||
| 521 | # CONFIG_BROADCOM_PHY is not set | ||
| 522 | # CONFIG_ICPLUS_PHY is not set | ||
| 523 | # CONFIG_FIXED_PHY is not set | ||
| 524 | # CONFIG_MDIO_BITBANG is not set | ||
| 532 | CONFIG_NET_ETHERNET=y | 525 | CONFIG_NET_ETHERNET=y |
| 533 | CONFIG_MII=y | 526 | CONFIG_MII=y |
| 527 | CONFIG_MACB=y | ||
| 528 | # CONFIG_AX88796 is not set | ||
| 534 | # CONFIG_SMC91X is not set | 529 | # CONFIG_SMC91X is not set |
| 535 | # CONFIG_DM9000 is not set | 530 | # CONFIG_DM9000 is not set |
| 531 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 532 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 533 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 534 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 535 | # CONFIG_B44 is not set | ||
| 536 | CONFIG_NETDEV_1000=y | ||
| 537 | CONFIG_NETDEV_10000=y | ||
| 536 | 538 | ||
| 537 | # | 539 | # |
| 538 | # Ethernet (1000 Mbit) | 540 | # Wireless LAN |
| 539 | # | ||
| 540 | |||
| 541 | # | ||
| 542 | # Ethernet (10000 Mbit) | ||
| 543 | # | ||
| 544 | |||
| 545 | # | ||
| 546 | # Token Ring devices | ||
| 547 | # | ||
| 548 | |||
| 549 | # | ||
| 550 | # Wireless LAN (non-hamradio) | ||
| 551 | # | 541 | # |
| 552 | # CONFIG_NET_RADIO is not set | 542 | # CONFIG_WLAN_PRE80211 is not set |
| 543 | # CONFIG_WLAN_80211 is not set | ||
| 553 | 544 | ||
| 554 | # | 545 | # |
| 555 | # Wan interfaces | 546 | # USB Network Adapters |
| 556 | # | 547 | # |
| 548 | # CONFIG_USB_CATC is not set | ||
| 549 | # CONFIG_USB_KAWETH is not set | ||
| 550 | # CONFIG_USB_PEGASUS is not set | ||
| 551 | # CONFIG_USB_RTL8150 is not set | ||
| 552 | # CONFIG_USB_USBNET is not set | ||
| 557 | # CONFIG_WAN is not set | 553 | # CONFIG_WAN is not set |
| 558 | # CONFIG_PPP is not set | 554 | # CONFIG_PPP is not set |
| 559 | # CONFIG_SLIP is not set | 555 | # CONFIG_SLIP is not set |
| @@ -561,10 +557,6 @@ CONFIG_MII=y | |||
| 561 | # CONFIG_NETCONSOLE is not set | 557 | # CONFIG_NETCONSOLE is not set |
| 562 | # CONFIG_NETPOLL is not set | 558 | # CONFIG_NETPOLL is not set |
| 563 | # CONFIG_NET_POLL_CONTROLLER is not set | 559 | # CONFIG_NET_POLL_CONTROLLER is not set |
| 564 | |||
| 565 | # | ||
| 566 | # ISDN subsystem | ||
| 567 | # | ||
| 568 | # CONFIG_ISDN is not set | 560 | # CONFIG_ISDN is not set |
| 569 | 561 | ||
| 570 | # | 562 | # |
| @@ -572,6 +564,7 @@ CONFIG_MII=y | |||
| 572 | # | 564 | # |
| 573 | CONFIG_INPUT=y | 565 | CONFIG_INPUT=y |
| 574 | # CONFIG_INPUT_FF_MEMLESS is not set | 566 | # CONFIG_INPUT_FF_MEMLESS is not set |
| 567 | # CONFIG_INPUT_POLLDEV is not set | ||
| 575 | 568 | ||
| 576 | # | 569 | # |
| 577 | # Userland interfaces | 570 | # Userland interfaces |
| @@ -581,20 +574,26 @@ CONFIG_INPUT_MOUSEDEV=y | |||
| 581 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | 574 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 |
| 582 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | 575 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 |
| 583 | # CONFIG_INPUT_JOYDEV is not set | 576 | # CONFIG_INPUT_JOYDEV is not set |
| 584 | CONFIG_INPUT_TSDEV=y | ||
| 585 | CONFIG_INPUT_TSDEV_SCREEN_X=240 | ||
| 586 | CONFIG_INPUT_TSDEV_SCREEN_Y=320 | ||
| 587 | CONFIG_INPUT_EVDEV=y | 577 | CONFIG_INPUT_EVDEV=y |
| 588 | # CONFIG_INPUT_EVBUG is not set | 578 | # CONFIG_INPUT_EVBUG is not set |
| 589 | 579 | ||
| 590 | # | 580 | # |
| 591 | # Input Device Drivers | 581 | # Input Device Drivers |
| 592 | # | 582 | # |
| 593 | # CONFIG_INPUT_KEYBOARD is not set | 583 | CONFIG_INPUT_KEYBOARD=y |
| 584 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 585 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 586 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 587 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 588 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 589 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 590 | CONFIG_KEYBOARD_GPIO=y | ||
| 594 | # CONFIG_INPUT_MOUSE is not set | 591 | # CONFIG_INPUT_MOUSE is not set |
| 595 | # CONFIG_INPUT_JOYSTICK is not set | 592 | # CONFIG_INPUT_JOYSTICK is not set |
| 593 | # CONFIG_INPUT_TABLET is not set | ||
| 596 | CONFIG_INPUT_TOUCHSCREEN=y | 594 | CONFIG_INPUT_TOUCHSCREEN=y |
| 597 | CONFIG_TOUCHSCREEN_ADS7846=y | 595 | CONFIG_TOUCHSCREEN_ADS7846=y |
| 596 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 598 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 597 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| 599 | # CONFIG_TOUCHSCREEN_ELO is not set | 598 | # CONFIG_TOUCHSCREEN_ELO is not set |
| 600 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | 599 | # CONFIG_TOUCHSCREEN_MTOUCH is not set |
| @@ -603,6 +602,7 @@ CONFIG_TOUCHSCREEN_ADS7846=y | |||
| 603 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | 602 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set |
| 604 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | 603 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set |
| 605 | # CONFIG_TOUCHSCREEN_UCB1400 is not set | 604 | # CONFIG_TOUCHSCREEN_UCB1400 is not set |
| 605 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
| 606 | # CONFIG_INPUT_MISC is not set | 606 | # CONFIG_INPUT_MISC is not set |
| 607 | 607 | ||
| 608 | # | 608 | # |
| @@ -636,71 +636,47 @@ CONFIG_SERIAL_CORE_CONSOLE=y | |||
| 636 | CONFIG_UNIX98_PTYS=y | 636 | CONFIG_UNIX98_PTYS=y |
| 637 | CONFIG_LEGACY_PTYS=y | 637 | CONFIG_LEGACY_PTYS=y |
| 638 | CONFIG_LEGACY_PTY_COUNT=256 | 638 | CONFIG_LEGACY_PTY_COUNT=256 |
| 639 | |||
| 640 | # | ||
| 641 | # IPMI | ||
| 642 | # | ||
| 643 | # CONFIG_IPMI_HANDLER is not set | 639 | # CONFIG_IPMI_HANDLER is not set |
| 644 | |||
| 645 | # | ||
| 646 | # Watchdog Cards | ||
| 647 | # | ||
| 648 | CONFIG_WATCHDOG=y | ||
| 649 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 650 | |||
| 651 | # | ||
| 652 | # Watchdog Device Drivers | ||
| 653 | # | ||
| 654 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 655 | |||
| 656 | # | ||
| 657 | # USB-based Watchdog Cards | ||
| 658 | # | ||
| 659 | # CONFIG_USBPCWATCHDOG is not set | ||
| 660 | CONFIG_HW_RANDOM=y | 640 | CONFIG_HW_RANDOM=y |
| 661 | # CONFIG_NVRAM is not set | 641 | # CONFIG_NVRAM is not set |
| 662 | # CONFIG_DTLK is not set | ||
| 663 | # CONFIG_R3964 is not set | 642 | # CONFIG_R3964 is not set |
| 664 | # CONFIG_RAW_DRIVER is not set | 643 | # CONFIG_RAW_DRIVER is not set |
| 665 | |||
| 666 | # | ||
| 667 | # TPM devices | ||
| 668 | # | ||
| 669 | # CONFIG_TCG_TPM is not set | 644 | # CONFIG_TCG_TPM is not set |
| 670 | |||
| 671 | # | ||
| 672 | # I2C support | ||
| 673 | # | ||
| 674 | CONFIG_I2C=y | 645 | CONFIG_I2C=y |
| 646 | CONFIG_I2C_BOARDINFO=y | ||
| 675 | CONFIG_I2C_CHARDEV=y | 647 | CONFIG_I2C_CHARDEV=y |
| 676 | 648 | ||
| 677 | # | 649 | # |
| 678 | # I2C Algorithms | 650 | # I2C Algorithms |
| 679 | # | 651 | # |
| 680 | # CONFIG_I2C_ALGOBIT is not set | 652 | CONFIG_I2C_ALGOBIT=y |
| 681 | # CONFIG_I2C_ALGOPCF is not set | 653 | # CONFIG_I2C_ALGOPCF is not set |
| 682 | # CONFIG_I2C_ALGOPCA is not set | 654 | # CONFIG_I2C_ALGOPCA is not set |
| 683 | 655 | ||
| 684 | # | 656 | # |
| 685 | # I2C Hardware Bus support | 657 | # I2C Hardware Bus support |
| 686 | # | 658 | # |
| 687 | CONFIG_I2C_AT91=y | 659 | CONFIG_I2C_GPIO=y |
| 688 | # CONFIG_I2C_OCORES is not set | 660 | # CONFIG_I2C_OCORES is not set |
| 689 | # CONFIG_I2C_PARPORT_LIGHT is not set | 661 | # CONFIG_I2C_PARPORT_LIGHT is not set |
| 662 | # CONFIG_I2C_SIMTEC is not set | ||
| 663 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 690 | # CONFIG_I2C_STUB is not set | 664 | # CONFIG_I2C_STUB is not set |
| 665 | # CONFIG_I2C_TINY_USB is not set | ||
| 691 | # CONFIG_I2C_PCA is not set | 666 | # CONFIG_I2C_PCA is not set |
| 692 | # CONFIG_I2C_PCA_ISA is not set | ||
| 693 | 667 | ||
| 694 | # | 668 | # |
| 695 | # Miscellaneous I2C Chip support | 669 | # Miscellaneous I2C Chip support |
| 696 | # | 670 | # |
| 697 | # CONFIG_SENSORS_DS1337 is not set | 671 | # CONFIG_SENSORS_DS1337 is not set |
| 698 | # CONFIG_SENSORS_DS1374 is not set | 672 | # CONFIG_SENSORS_DS1374 is not set |
| 673 | # CONFIG_DS1682 is not set | ||
| 699 | # CONFIG_SENSORS_EEPROM is not set | 674 | # CONFIG_SENSORS_EEPROM is not set |
| 700 | # CONFIG_SENSORS_PCF8574 is not set | 675 | # CONFIG_SENSORS_PCF8574 is not set |
| 701 | # CONFIG_SENSORS_PCA9539 is not set | 676 | # CONFIG_SENSORS_PCA9539 is not set |
| 702 | # CONFIG_SENSORS_PCF8591 is not set | 677 | # CONFIG_SENSORS_PCF8591 is not set |
| 703 | # CONFIG_SENSORS_MAX6875 is not set | 678 | # CONFIG_SENSORS_MAX6875 is not set |
| 679 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 704 | # CONFIG_I2C_DEBUG_CORE is not set | 680 | # CONFIG_I2C_DEBUG_CORE is not set |
| 705 | # CONFIG_I2C_DEBUG_ALGO is not set | 681 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 706 | # CONFIG_I2C_DEBUG_BUS is not set | 682 | # CONFIG_I2C_DEBUG_BUS is not set |
| @@ -722,61 +698,80 @@ CONFIG_SPI_ATMEL=y | |||
| 722 | # | 698 | # |
| 723 | # SPI Protocol Masters | 699 | # SPI Protocol Masters |
| 724 | # | 700 | # |
| 725 | 701 | # CONFIG_SPI_AT25 is not set | |
| 726 | # | 702 | # CONFIG_SPI_SPIDEV is not set |
| 727 | # Dallas's 1-wire bus | 703 | # CONFIG_SPI_TLE62X0 is not set |
| 728 | # | ||
| 729 | # CONFIG_W1 is not set | 704 | # CONFIG_W1 is not set |
| 730 | 705 | # CONFIG_POWER_SUPPLY is not set | |
| 731 | # | ||
| 732 | # Hardware Monitoring support | ||
| 733 | # | ||
| 734 | # CONFIG_HWMON is not set | 706 | # CONFIG_HWMON is not set |
| 735 | # CONFIG_HWMON_VID is not set | 707 | CONFIG_WATCHDOG=y |
| 708 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 736 | 709 | ||
| 737 | # | 710 | # |
| 738 | # Misc devices | 711 | # Watchdog Device Drivers |
| 739 | # | 712 | # |
| 740 | # CONFIG_TIFM_CORE is not set | 713 | # CONFIG_SOFT_WATCHDOG is not set |
| 714 | CONFIG_AT91SAM9_WATCHDOG=y | ||
| 741 | 715 | ||
| 742 | # | 716 | # |
| 743 | # LED devices | 717 | # USB-based Watchdog Cards |
| 744 | # | 718 | # |
| 745 | # CONFIG_NEW_LEDS is not set | 719 | # CONFIG_USBPCWATCHDOG is not set |
| 746 | 720 | ||
| 747 | # | 721 | # |
| 748 | # LED drivers | 722 | # Sonics Silicon Backplane |
| 749 | # | 723 | # |
| 724 | CONFIG_SSB_POSSIBLE=y | ||
| 725 | # CONFIG_SSB is not set | ||
| 750 | 726 | ||
| 751 | # | 727 | # |
| 752 | # LED Triggers | 728 | # Multifunction device drivers |
| 753 | # | 729 | # |
| 730 | # CONFIG_MFD_SM501 is not set | ||
| 754 | 731 | ||
| 755 | # | 732 | # |
| 756 | # Multimedia devices | 733 | # Multimedia devices |
| 757 | # | 734 | # |
| 758 | # CONFIG_VIDEO_DEV is not set | 735 | # CONFIG_VIDEO_DEV is not set |
| 759 | 736 | # CONFIG_DVB_CORE is not set | |
| 760 | # | 737 | # CONFIG_DAB is not set |
| 761 | # Digital Video Broadcasting Devices | ||
| 762 | # | ||
| 763 | # CONFIG_DVB is not set | ||
| 764 | # CONFIG_USB_DABUSB is not set | ||
| 765 | 738 | ||
| 766 | # | 739 | # |
| 767 | # Graphics support | 740 | # Graphics support |
| 768 | # | 741 | # |
| 769 | # CONFIG_FIRMWARE_EDID is not set | 742 | # CONFIG_VGASTATE is not set |
| 743 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 770 | CONFIG_FB=y | 744 | CONFIG_FB=y |
| 771 | # CONFIG_FB_CFB_FILLRECT is not set | 745 | # CONFIG_FIRMWARE_EDID is not set |
| 772 | # CONFIG_FB_CFB_COPYAREA is not set | 746 | # CONFIG_FB_DDC is not set |
| 773 | # CONFIG_FB_CFB_IMAGEBLIT is not set | 747 | CONFIG_FB_CFB_FILLRECT=y |
| 748 | CONFIG_FB_CFB_COPYAREA=y | ||
| 749 | CONFIG_FB_CFB_IMAGEBLIT=y | ||
| 750 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 751 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 752 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 753 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 754 | # CONFIG_FB_SYS_FOPS is not set | ||
| 755 | CONFIG_FB_DEFERRED_IO=y | ||
| 756 | # CONFIG_FB_SVGALIB is not set | ||
| 774 | # CONFIG_FB_MACMODES is not set | 757 | # CONFIG_FB_MACMODES is not set |
| 775 | # CONFIG_FB_BACKLIGHT is not set | 758 | # CONFIG_FB_BACKLIGHT is not set |
| 776 | # CONFIG_FB_MODE_HELPERS is not set | 759 | # CONFIG_FB_MODE_HELPERS is not set |
| 777 | # CONFIG_FB_TILEBLITTING is not set | 760 | # CONFIG_FB_TILEBLITTING is not set |
| 761 | |||
| 762 | # | ||
| 763 | # Frame buffer hardware drivers | ||
| 764 | # | ||
| 765 | # CONFIG_FB_S1D15605 is not set | ||
| 778 | # CONFIG_FB_S1D13XXX is not set | 766 | # CONFIG_FB_S1D13XXX is not set |
| 767 | CONFIG_FB_ATMEL=y | ||
| 779 | # CONFIG_FB_VIRTUAL is not set | 768 | # CONFIG_FB_VIRTUAL is not set |
| 769 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 770 | |||
| 771 | # | ||
| 772 | # Display device support | ||
| 773 | # | ||
| 774 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 780 | 775 | ||
| 781 | # | 776 | # |
| 782 | # Console display driver support | 777 | # Console display driver support |
| @@ -784,26 +779,28 @@ CONFIG_FB=y | |||
| 784 | # CONFIG_VGA_CONSOLE is not set | 779 | # CONFIG_VGA_CONSOLE is not set |
| 785 | CONFIG_DUMMY_CONSOLE=y | 780 | CONFIG_DUMMY_CONSOLE=y |
| 786 | # CONFIG_FRAMEBUFFER_CONSOLE is not set | 781 | # CONFIG_FRAMEBUFFER_CONSOLE is not set |
| 787 | |||
| 788 | # | ||
| 789 | # Logo configuration | ||
| 790 | # | ||
| 791 | # CONFIG_LOGO is not set | 782 | # CONFIG_LOGO is not set |
| 792 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 793 | 783 | ||
| 794 | # | 784 | # |
| 795 | # Sound | 785 | # Sound |
| 796 | # | 786 | # |
| 797 | # CONFIG_SOUND is not set | 787 | # CONFIG_SOUND is not set |
| 788 | CONFIG_HID_SUPPORT=y | ||
| 789 | CONFIG_HID=y | ||
| 790 | # CONFIG_HID_DEBUG is not set | ||
| 791 | # CONFIG_HIDRAW is not set | ||
| 798 | 792 | ||
| 799 | # | 793 | # |
| 800 | # HID Devices | 794 | # USB Input Devices |
| 801 | # | 795 | # |
| 802 | CONFIG_HID=y | 796 | # CONFIG_USB_HID is not set |
| 803 | 797 | ||
| 804 | # | 798 | # |
| 805 | # USB support | 799 | # USB HID Boot Protocol drivers |
| 806 | # | 800 | # |
| 801 | # CONFIG_USB_KBD is not set | ||
| 802 | # CONFIG_USB_MOUSE is not set | ||
| 803 | CONFIG_USB_SUPPORT=y | ||
| 807 | CONFIG_USB_ARCH_HAS_HCD=y | 804 | CONFIG_USB_ARCH_HAS_HCD=y |
| 808 | CONFIG_USB_ARCH_HAS_OHCI=y | 805 | CONFIG_USB_ARCH_HAS_OHCI=y |
| 809 | # CONFIG_USB_ARCH_HAS_EHCI is not set | 806 | # CONFIG_USB_ARCH_HAS_EHCI is not set |
| @@ -814,9 +811,8 @@ CONFIG_USB=y | |||
| 814 | # Miscellaneous USB options | 811 | # Miscellaneous USB options |
| 815 | # | 812 | # |
| 816 | CONFIG_USB_DEVICEFS=y | 813 | CONFIG_USB_DEVICEFS=y |
| 817 | # CONFIG_USB_BANDWIDTH is not set | 814 | CONFIG_USB_DEVICE_CLASS=y |
| 818 | # CONFIG_USB_DYNAMIC_MINORS is not set | 815 | # CONFIG_USB_DYNAMIC_MINORS is not set |
| 819 | # CONFIG_USB_MULTITHREAD_PROBE is not set | ||
| 820 | # CONFIG_USB_OTG is not set | 816 | # CONFIG_USB_OTG is not set |
| 821 | 817 | ||
| 822 | # | 818 | # |
| @@ -824,9 +820,11 @@ CONFIG_USB_DEVICEFS=y | |||
| 824 | # | 820 | # |
| 825 | # CONFIG_USB_ISP116X_HCD is not set | 821 | # CONFIG_USB_ISP116X_HCD is not set |
| 826 | CONFIG_USB_OHCI_HCD=y | 822 | CONFIG_USB_OHCI_HCD=y |
| 827 | # CONFIG_USB_OHCI_BIG_ENDIAN is not set | 823 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set |
| 824 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 828 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | 825 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y |
| 829 | # CONFIG_USB_SL811_HCD is not set | 826 | # CONFIG_USB_SL811_HCD is not set |
| 827 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 830 | 828 | ||
| 831 | # | 829 | # |
| 832 | # USB Device Class drivers | 830 | # USB Device Class drivers |
| @@ -845,6 +843,7 @@ CONFIG_USB_STORAGE=y | |||
| 845 | # CONFIG_USB_STORAGE_DEBUG is not set | 843 | # CONFIG_USB_STORAGE_DEBUG is not set |
| 846 | # CONFIG_USB_STORAGE_DATAFAB is not set | 844 | # CONFIG_USB_STORAGE_DATAFAB is not set |
| 847 | # CONFIG_USB_STORAGE_FREECOM is not set | 845 | # CONFIG_USB_STORAGE_FREECOM is not set |
| 846 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 848 | # CONFIG_USB_STORAGE_DPCM is not set | 847 | # CONFIG_USB_STORAGE_DPCM is not set |
| 849 | # CONFIG_USB_STORAGE_USBAT is not set | 848 | # CONFIG_USB_STORAGE_USBAT is not set |
| 850 | # CONFIG_USB_STORAGE_SDDR09 is not set | 849 | # CONFIG_USB_STORAGE_SDDR09 is not set |
| @@ -856,43 +855,10 @@ CONFIG_USB_STORAGE=y | |||
| 856 | # CONFIG_USB_LIBUSUAL is not set | 855 | # CONFIG_USB_LIBUSUAL is not set |
| 857 | 856 | ||
| 858 | # | 857 | # |
| 859 | # USB Input Devices | ||
| 860 | # | ||
| 861 | # CONFIG_USB_HID is not set | ||
| 862 | |||
| 863 | # | ||
| 864 | # USB HID Boot Protocol drivers | ||
| 865 | # | ||
| 866 | # CONFIG_USB_KBD is not set | ||
| 867 | # CONFIG_USB_MOUSE is not set | ||
| 868 | # CONFIG_USB_AIPTEK is not set | ||
| 869 | # CONFIG_USB_WACOM is not set | ||
| 870 | # CONFIG_USB_ACECAD is not set | ||
| 871 | # CONFIG_USB_KBTAB is not set | ||
| 872 | # CONFIG_USB_POWERMATE is not set | ||
| 873 | # CONFIG_USB_TOUCHSCREEN is not set | ||
| 874 | # CONFIG_USB_YEALINK is not set | ||
| 875 | # CONFIG_USB_XPAD is not set | ||
| 876 | # CONFIG_USB_ATI_REMOTE is not set | ||
| 877 | # CONFIG_USB_ATI_REMOTE2 is not set | ||
| 878 | # CONFIG_USB_KEYSPAN_REMOTE is not set | ||
| 879 | # CONFIG_USB_APPLETOUCH is not set | ||
| 880 | |||
| 881 | # | ||
| 882 | # USB Imaging devices | 858 | # USB Imaging devices |
| 883 | # | 859 | # |
| 884 | # CONFIG_USB_MDC800 is not set | 860 | # CONFIG_USB_MDC800 is not set |
| 885 | # CONFIG_USB_MICROTEK is not set | 861 | # CONFIG_USB_MICROTEK is not set |
| 886 | |||
| 887 | # | ||
| 888 | # USB Network Adapters | ||
| 889 | # | ||
| 890 | # CONFIG_USB_CATC is not set | ||
| 891 | # CONFIG_USB_KAWETH is not set | ||
| 892 | # CONFIG_USB_PEGASUS is not set | ||
| 893 | # CONFIG_USB_RTL8150 is not set | ||
| 894 | # CONFIG_USB_USBNET_MII is not set | ||
| 895 | # CONFIG_USB_USBNET is not set | ||
| 896 | CONFIG_USB_MON=y | 862 | CONFIG_USB_MON=y |
| 897 | 863 | ||
| 898 | # | 864 | # |
| @@ -914,6 +880,7 @@ CONFIG_USB_MON=y | |||
| 914 | # CONFIG_USB_RIO500 is not set | 880 | # CONFIG_USB_RIO500 is not set |
| 915 | # CONFIG_USB_LEGOTOWER is not set | 881 | # CONFIG_USB_LEGOTOWER is not set |
| 916 | # CONFIG_USB_LCD is not set | 882 | # CONFIG_USB_LCD is not set |
| 883 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 917 | # CONFIG_USB_LED is not set | 884 | # CONFIG_USB_LED is not set |
| 918 | # CONFIG_USB_CYPRESS_CY7C63 is not set | 885 | # CONFIG_USB_CYPRESS_CY7C63 is not set |
| 919 | # CONFIG_USB_CYTHERM is not set | 886 | # CONFIG_USB_CYTHERM is not set |
| @@ -923,6 +890,7 @@ CONFIG_USB_MON=y | |||
| 923 | # CONFIG_USB_APPLEDISPLAY is not set | 890 | # CONFIG_USB_APPLEDISPLAY is not set |
| 924 | # CONFIG_USB_LD is not set | 891 | # CONFIG_USB_LD is not set |
| 925 | # CONFIG_USB_TRANCEVIBRATOR is not set | 892 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 893 | # CONFIG_USB_IOWARRIOR is not set | ||
| 926 | # CONFIG_USB_TEST is not set | 894 | # CONFIG_USB_TEST is not set |
| 927 | 895 | ||
| 928 | # | 896 | # |
| @@ -933,13 +901,19 @@ CONFIG_USB_MON=y | |||
| 933 | # USB Gadget Support | 901 | # USB Gadget Support |
| 934 | # | 902 | # |
| 935 | CONFIG_USB_GADGET=y | 903 | CONFIG_USB_GADGET=y |
| 904 | # CONFIG_USB_GADGET_DEBUG is not set | ||
| 936 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | 905 | # CONFIG_USB_GADGET_DEBUG_FILES is not set |
| 937 | CONFIG_USB_GADGET_SELECTED=y | 906 | CONFIG_USB_GADGET_SELECTED=y |
| 907 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 908 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 909 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 938 | # CONFIG_USB_GADGET_NET2280 is not set | 910 | # CONFIG_USB_GADGET_NET2280 is not set |
| 939 | # CONFIG_USB_GADGET_PXA2XX is not set | 911 | # CONFIG_USB_GADGET_PXA2XX is not set |
| 912 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 940 | # CONFIG_USB_GADGET_GOKU is not set | 913 | # CONFIG_USB_GADGET_GOKU is not set |
| 941 | # CONFIG_USB_GADGET_LH7A40X is not set | 914 | # CONFIG_USB_GADGET_LH7A40X is not set |
| 942 | # CONFIG_USB_GADGET_OMAP is not set | 915 | # CONFIG_USB_GADGET_OMAP is not set |
| 916 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 943 | CONFIG_USB_GADGET_AT91=y | 917 | CONFIG_USB_GADGET_AT91=y |
| 944 | CONFIG_USB_AT91=y | 918 | CONFIG_USB_AT91=y |
| 945 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | 919 | # CONFIG_USB_GADGET_DUMMY_HCD is not set |
| @@ -951,21 +925,73 @@ CONFIG_USB_FILE_STORAGE=m | |||
| 951 | # CONFIG_USB_FILE_STORAGE_TEST is not set | 925 | # CONFIG_USB_FILE_STORAGE_TEST is not set |
| 952 | CONFIG_USB_G_SERIAL=m | 926 | CONFIG_USB_G_SERIAL=m |
| 953 | # CONFIG_USB_MIDI_GADGET is not set | 927 | # CONFIG_USB_MIDI_GADGET is not set |
| 928 | CONFIG_MMC=y | ||
| 929 | # CONFIG_MMC_DEBUG is not set | ||
| 930 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 954 | 931 | ||
| 955 | # | 932 | # |
| 956 | # MMC/SD Card support | 933 | # MMC/SD Card Drivers |
| 957 | # | 934 | # |
| 958 | CONFIG_MMC=y | ||
| 959 | # CONFIG_MMC_DEBUG is not set | ||
| 960 | CONFIG_MMC_BLOCK=y | 935 | CONFIG_MMC_BLOCK=y |
| 961 | CONFIG_MMC_AT91=m | 936 | CONFIG_MMC_BLOCK_BOUNCE=y |
| 962 | # CONFIG_MMC_TIFM_SD is not set | 937 | # CONFIG_SDIO_UART is not set |
| 963 | 938 | ||
| 964 | # | 939 | # |
| 965 | # Real Time Clock | 940 | # MMC/SD Host Controller Drivers |
| 966 | # | 941 | # |
| 942 | CONFIG_MMC_AT91=m | ||
| 943 | # CONFIG_MMC_SPI is not set | ||
| 944 | # CONFIG_NEW_LEDS is not set | ||
| 967 | CONFIG_RTC_LIB=y | 945 | CONFIG_RTC_LIB=y |
| 968 | # CONFIG_RTC_CLASS is not set | 946 | CONFIG_RTC_CLASS=y |
| 947 | CONFIG_RTC_HCTOSYS=y | ||
| 948 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 949 | # CONFIG_RTC_DEBUG is not set | ||
| 950 | |||
| 951 | # | ||
| 952 | # RTC interfaces | ||
| 953 | # | ||
| 954 | CONFIG_RTC_INTF_SYSFS=y | ||
| 955 | CONFIG_RTC_INTF_PROC=y | ||
| 956 | CONFIG_RTC_INTF_DEV=y | ||
| 957 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 958 | # CONFIG_RTC_DRV_TEST is not set | ||
| 959 | |||
| 960 | # | ||
| 961 | # I2C RTC drivers | ||
| 962 | # | ||
| 963 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 964 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 965 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 966 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 967 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 968 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 969 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 970 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 971 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 972 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 973 | |||
| 974 | # | ||
| 975 | # SPI RTC drivers | ||
| 976 | # | ||
| 977 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 978 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 979 | |||
| 980 | # | ||
| 981 | # Platform RTC drivers | ||
| 982 | # | ||
| 983 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 984 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 985 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 986 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 987 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 988 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 989 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 990 | |||
| 991 | # | ||
| 992 | # on-CPU RTC drivers | ||
| 993 | # | ||
| 994 | CONFIG_RTC_DRV_AT91SAM9=y | ||
| 969 | 995 | ||
| 970 | # | 996 | # |
| 971 | # File systems | 997 | # File systems |
| @@ -1016,7 +1042,6 @@ CONFIG_SYSFS=y | |||
| 1016 | CONFIG_TMPFS=y | 1042 | CONFIG_TMPFS=y |
| 1017 | # CONFIG_TMPFS_POSIX_ACL is not set | 1043 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 1018 | # CONFIG_HUGETLB_PAGE is not set | 1044 | # CONFIG_HUGETLB_PAGE is not set |
| 1019 | CONFIG_RAMFS=y | ||
| 1020 | # CONFIG_CONFIGFS_FS is not set | 1045 | # CONFIG_CONFIGFS_FS is not set |
| 1021 | 1046 | ||
| 1022 | # | 1047 | # |
| @@ -1032,10 +1057,12 @@ CONFIG_RAMFS=y | |||
| 1032 | CONFIG_JFFS2_FS=y | 1057 | CONFIG_JFFS2_FS=y |
| 1033 | CONFIG_JFFS2_FS_DEBUG=0 | 1058 | CONFIG_JFFS2_FS_DEBUG=0 |
| 1034 | CONFIG_JFFS2_FS_WRITEBUFFER=y | 1059 | CONFIG_JFFS2_FS_WRITEBUFFER=y |
| 1060 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1035 | # CONFIG_JFFS2_SUMMARY is not set | 1061 | # CONFIG_JFFS2_SUMMARY is not set |
| 1036 | # CONFIG_JFFS2_FS_XATTR is not set | 1062 | # CONFIG_JFFS2_FS_XATTR is not set |
| 1037 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | 1063 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set |
| 1038 | CONFIG_JFFS2_ZLIB=y | 1064 | CONFIG_JFFS2_ZLIB=y |
| 1065 | # CONFIG_JFFS2_LZO is not set | ||
| 1039 | CONFIG_JFFS2_RTIME=y | 1066 | CONFIG_JFFS2_RTIME=y |
| 1040 | # CONFIG_JFFS2_RUBIN is not set | 1067 | # CONFIG_JFFS2_RUBIN is not set |
| 1041 | CONFIG_CRAMFS=y | 1068 | CONFIG_CRAMFS=y |
| @@ -1044,10 +1071,7 @@ CONFIG_CRAMFS=y | |||
| 1044 | # CONFIG_QNX4FS_FS is not set | 1071 | # CONFIG_QNX4FS_FS is not set |
| 1045 | # CONFIG_SYSV_FS is not set | 1072 | # CONFIG_SYSV_FS is not set |
| 1046 | # CONFIG_UFS_FS is not set | 1073 | # CONFIG_UFS_FS is not set |
| 1047 | 1074 | CONFIG_NETWORK_FILESYSTEMS=y | |
| 1048 | # | ||
| 1049 | # Network File Systems | ||
| 1050 | # | ||
| 1051 | CONFIG_NFS_FS=y | 1075 | CONFIG_NFS_FS=y |
| 1052 | # CONFIG_NFS_V3 is not set | 1076 | # CONFIG_NFS_V3 is not set |
| 1053 | # CONFIG_NFS_V4 is not set | 1077 | # CONFIG_NFS_V4 is not set |
| @@ -1057,6 +1081,7 @@ CONFIG_ROOT_NFS=y | |||
| 1057 | CONFIG_LOCKD=y | 1081 | CONFIG_LOCKD=y |
| 1058 | CONFIG_NFS_COMMON=y | 1082 | CONFIG_NFS_COMMON=y |
| 1059 | CONFIG_SUNRPC=y | 1083 | CONFIG_SUNRPC=y |
| 1084 | # CONFIG_SUNRPC_BIND34 is not set | ||
| 1060 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 1085 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 1061 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1086 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1062 | # CONFIG_SMB_FS is not set | 1087 | # CONFIG_SMB_FS is not set |
| @@ -1064,17 +1089,12 @@ CONFIG_SUNRPC=y | |||
| 1064 | # CONFIG_NCP_FS is not set | 1089 | # CONFIG_NCP_FS is not set |
| 1065 | # CONFIG_CODA_FS is not set | 1090 | # CONFIG_CODA_FS is not set |
| 1066 | # CONFIG_AFS_FS is not set | 1091 | # CONFIG_AFS_FS is not set |
| 1067 | # CONFIG_9P_FS is not set | ||
| 1068 | 1092 | ||
| 1069 | # | 1093 | # |
| 1070 | # Partition Types | 1094 | # Partition Types |
| 1071 | # | 1095 | # |
| 1072 | # CONFIG_PARTITION_ADVANCED is not set | 1096 | # CONFIG_PARTITION_ADVANCED is not set |
| 1073 | CONFIG_MSDOS_PARTITION=y | 1097 | CONFIG_MSDOS_PARTITION=y |
| 1074 | |||
| 1075 | # | ||
| 1076 | # Native Language Support | ||
| 1077 | # | ||
| 1078 | CONFIG_NLS=y | 1098 | CONFIG_NLS=y |
| 1079 | CONFIG_NLS_DEFAULT="iso8859-1" | 1099 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 1080 | CONFIG_NLS_CODEPAGE_437=y | 1100 | CONFIG_NLS_CODEPAGE_437=y |
| @@ -1115,36 +1135,35 @@ CONFIG_NLS_ISO8859_1=y | |||
| 1115 | # CONFIG_NLS_KOI8_R is not set | 1135 | # CONFIG_NLS_KOI8_R is not set |
| 1116 | # CONFIG_NLS_KOI8_U is not set | 1136 | # CONFIG_NLS_KOI8_U is not set |
| 1117 | # CONFIG_NLS_UTF8 is not set | 1137 | # CONFIG_NLS_UTF8 is not set |
| 1118 | |||
| 1119 | # | ||
| 1120 | # Distributed Lock Manager | ||
| 1121 | # | ||
| 1122 | # CONFIG_DLM is not set | 1138 | # CONFIG_DLM is not set |
| 1123 | 1139 | CONFIG_INSTRUMENTATION=y | |
| 1124 | # | ||
| 1125 | # Profiling support | ||
| 1126 | # | ||
| 1127 | # CONFIG_PROFILING is not set | 1140 | # CONFIG_PROFILING is not set |
| 1141 | # CONFIG_MARKERS is not set | ||
| 1128 | 1142 | ||
| 1129 | # | 1143 | # |
| 1130 | # Kernel hacking | 1144 | # Kernel hacking |
| 1131 | # | 1145 | # |
| 1132 | # CONFIG_PRINTK_TIME is not set | 1146 | # CONFIG_PRINTK_TIME is not set |
| 1147 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1133 | CONFIG_ENABLE_MUST_CHECK=y | 1148 | CONFIG_ENABLE_MUST_CHECK=y |
| 1134 | # CONFIG_MAGIC_SYSRQ is not set | 1149 | # CONFIG_MAGIC_SYSRQ is not set |
| 1135 | # CONFIG_UNUSED_SYMBOLS is not set | 1150 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1136 | # CONFIG_DEBUG_FS is not set | 1151 | # CONFIG_DEBUG_FS is not set |
| 1137 | # CONFIG_HEADERS_CHECK is not set | 1152 | # CONFIG_HEADERS_CHECK is not set |
| 1138 | CONFIG_DEBUG_KERNEL=y | 1153 | CONFIG_DEBUG_KERNEL=y |
| 1139 | CONFIG_LOG_BUF_SHIFT=14 | 1154 | # CONFIG_DEBUG_SHIRQ is not set |
| 1140 | CONFIG_DETECT_SOFTLOCKUP=y | 1155 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1156 | CONFIG_SCHED_DEBUG=y | ||
| 1141 | # CONFIG_SCHEDSTATS is not set | 1157 | # CONFIG_SCHEDSTATS is not set |
| 1158 | # CONFIG_TIMER_STATS is not set | ||
| 1142 | # CONFIG_DEBUG_SLAB is not set | 1159 | # CONFIG_DEBUG_SLAB is not set |
| 1143 | # CONFIG_DEBUG_RT_MUTEXES is not set | 1160 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| 1144 | # CONFIG_RT_MUTEX_TESTER is not set | 1161 | # CONFIG_RT_MUTEX_TESTER is not set |
| 1145 | # CONFIG_DEBUG_SPINLOCK is not set | 1162 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1146 | # CONFIG_DEBUG_MUTEXES is not set | 1163 | # CONFIG_DEBUG_MUTEXES is not set |
| 1147 | # CONFIG_DEBUG_RWSEMS is not set | 1164 | # CONFIG_DEBUG_LOCK_ALLOC is not set |
| 1165 | # CONFIG_PROVE_LOCKING is not set | ||
| 1166 | # CONFIG_LOCK_STAT is not set | ||
| 1148 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1167 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1149 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | 1168 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set |
| 1150 | # CONFIG_DEBUG_KOBJECT is not set | 1169 | # CONFIG_DEBUG_KOBJECT is not set |
| @@ -1152,9 +1171,13 @@ CONFIG_DEBUG_BUGVERBOSE=y | |||
| 1152 | # CONFIG_DEBUG_INFO is not set | 1171 | # CONFIG_DEBUG_INFO is not set |
| 1153 | # CONFIG_DEBUG_VM is not set | 1172 | # CONFIG_DEBUG_VM is not set |
| 1154 | # CONFIG_DEBUG_LIST is not set | 1173 | # CONFIG_DEBUG_LIST is not set |
| 1174 | # CONFIG_DEBUG_SG is not set | ||
| 1155 | CONFIG_FRAME_POINTER=y | 1175 | CONFIG_FRAME_POINTER=y |
| 1156 | CONFIG_FORCED_INLINING=y | 1176 | CONFIG_FORCED_INLINING=y |
| 1177 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1157 | # CONFIG_RCU_TORTURE_TEST is not set | 1178 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1179 | # CONFIG_FAULT_INJECTION is not set | ||
| 1180 | # CONFIG_SAMPLES is not set | ||
| 1158 | CONFIG_DEBUG_USER=y | 1181 | CONFIG_DEBUG_USER=y |
| 1159 | # CONFIG_DEBUG_ERRORS is not set | 1182 | # CONFIG_DEBUG_ERRORS is not set |
| 1160 | CONFIG_DEBUG_LL=y | 1183 | CONFIG_DEBUG_LL=y |
| @@ -1165,10 +1188,7 @@ CONFIG_DEBUG_LL=y | |||
| 1165 | # | 1188 | # |
| 1166 | # CONFIG_KEYS is not set | 1189 | # CONFIG_KEYS is not set |
| 1167 | # CONFIG_SECURITY is not set | 1190 | # CONFIG_SECURITY is not set |
| 1168 | 1191 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | |
| 1169 | # | ||
| 1170 | # Cryptographic options | ||
| 1171 | # | ||
| 1172 | # CONFIG_CRYPTO is not set | 1192 | # CONFIG_CRYPTO is not set |
| 1173 | 1193 | ||
| 1174 | # | 1194 | # |
| @@ -1177,8 +1197,13 @@ CONFIG_DEBUG_LL=y | |||
| 1177 | CONFIG_BITREVERSE=y | 1197 | CONFIG_BITREVERSE=y |
| 1178 | # CONFIG_CRC_CCITT is not set | 1198 | # CONFIG_CRC_CCITT is not set |
| 1179 | # CONFIG_CRC16 is not set | 1199 | # CONFIG_CRC16 is not set |
| 1200 | # CONFIG_CRC_ITU_T is not set | ||
| 1180 | CONFIG_CRC32=y | 1201 | CONFIG_CRC32=y |
| 1202 | # CONFIG_CRC7 is not set | ||
| 1181 | # CONFIG_LIBCRC32C is not set | 1203 | # CONFIG_LIBCRC32C is not set |
| 1182 | CONFIG_ZLIB_INFLATE=y | 1204 | CONFIG_ZLIB_INFLATE=y |
| 1205 | CONFIG_ZLIB_DEFLATE=y | ||
| 1183 | CONFIG_PLIST=y | 1206 | CONFIG_PLIST=y |
| 1184 | CONFIG_IOMAP_COPY=y | 1207 | CONFIG_HAS_IOMEM=y |
| 1208 | CONFIG_HAS_IOPORT=y | ||
| 1209 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/at91sam9rlek_defconfig b/arch/arm/configs/at91sam9rlek_defconfig index fbe8b3049343..98e6746d02be 100644 --- a/arch/arm/configs/at91sam9rlek_defconfig +++ b/arch/arm/configs/at91sam9rlek_defconfig | |||
| @@ -1,15 +1,18 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.21 | 3 | # Linux kernel version: 2.6.24-rc7 |
| 4 | # Mon May 7 16:30:40 2007 | 4 | # Tue Jan 8 22:24:14 2008 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| 8 | CONFIG_GENERIC_GPIO=y | 8 | CONFIG_GENERIC_GPIO=y |
| 9 | # CONFIG_GENERIC_TIME is not set | 9 | # CONFIG_GENERIC_TIME is not set |
| 10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
| 10 | CONFIG_MMU=y | 11 | CONFIG_MMU=y |
| 11 | # CONFIG_NO_IOPORT is not set | 12 | # CONFIG_NO_IOPORT is not set |
| 12 | CONFIG_GENERIC_HARDIRQS=y | 13 | CONFIG_GENERIC_HARDIRQS=y |
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 13 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y |
| 14 | CONFIG_HARDIRQS_SW_RESEND=y | 17 | CONFIG_HARDIRQS_SW_RESEND=y |
| 15 | CONFIG_GENERIC_IRQ_PROBE=y | 18 | CONFIG_GENERIC_IRQ_PROBE=y |
| @@ -23,27 +26,28 @@ CONFIG_VECTORS_BASE=0xffff0000 | |||
| 23 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 26 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 24 | 27 | ||
| 25 | # | 28 | # |
| 26 | # Code maturity level options | 29 | # General setup |
| 27 | # | 30 | # |
| 28 | CONFIG_EXPERIMENTAL=y | 31 | CONFIG_EXPERIMENTAL=y |
| 29 | CONFIG_BROKEN_ON_SMP=y | 32 | CONFIG_BROKEN_ON_SMP=y |
| 30 | CONFIG_INIT_ENV_ARG_LIMIT=32 | 33 | CONFIG_INIT_ENV_ARG_LIMIT=32 |
| 31 | |||
| 32 | # | ||
| 33 | # General setup | ||
| 34 | # | ||
| 35 | CONFIG_LOCALVERSION="" | 34 | CONFIG_LOCALVERSION="" |
| 36 | # CONFIG_LOCALVERSION_AUTO is not set | 35 | # CONFIG_LOCALVERSION_AUTO is not set |
| 37 | # CONFIG_SWAP is not set | 36 | # CONFIG_SWAP is not set |
| 38 | CONFIG_SYSVIPC=y | 37 | CONFIG_SYSVIPC=y |
| 39 | # CONFIG_IPC_NS is not set | ||
| 40 | CONFIG_SYSVIPC_SYSCTL=y | 38 | CONFIG_SYSVIPC_SYSCTL=y |
| 41 | # CONFIG_POSIX_MQUEUE is not set | 39 | # CONFIG_POSIX_MQUEUE is not set |
| 42 | # CONFIG_BSD_PROCESS_ACCT is not set | 40 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 43 | # CONFIG_TASKSTATS is not set | 41 | # CONFIG_TASKSTATS is not set |
| 44 | # CONFIG_UTS_NS is not set | 42 | # CONFIG_USER_NS is not set |
| 43 | # CONFIG_PID_NS is not set | ||
| 45 | # CONFIG_AUDIT is not set | 44 | # CONFIG_AUDIT is not set |
| 46 | # CONFIG_IKCONFIG is not set | 45 | # CONFIG_IKCONFIG is not set |
| 46 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 47 | # CONFIG_CGROUPS is not set | ||
| 48 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 49 | CONFIG_FAIR_USER_SCHED=y | ||
| 50 | # CONFIG_FAIR_CGROUP_SCHED is not set | ||
| 47 | CONFIG_SYSFS_DEPRECATED=y | 51 | CONFIG_SYSFS_DEPRECATED=y |
| 48 | # CONFIG_RELAY is not set | 52 | # CONFIG_RELAY is not set |
| 49 | CONFIG_BLK_DEV_INITRD=y | 53 | CONFIG_BLK_DEV_INITRD=y |
| @@ -62,32 +66,30 @@ CONFIG_BUG=y | |||
| 62 | CONFIG_ELF_CORE=y | 66 | CONFIG_ELF_CORE=y |
| 63 | CONFIG_BASE_FULL=y | 67 | CONFIG_BASE_FULL=y |
| 64 | CONFIG_FUTEX=y | 68 | CONFIG_FUTEX=y |
| 69 | CONFIG_ANON_INODES=y | ||
| 65 | CONFIG_EPOLL=y | 70 | CONFIG_EPOLL=y |
| 71 | CONFIG_SIGNALFD=y | ||
| 72 | CONFIG_EVENTFD=y | ||
| 66 | CONFIG_SHMEM=y | 73 | CONFIG_SHMEM=y |
| 67 | CONFIG_SLAB=y | ||
| 68 | CONFIG_VM_EVENT_COUNTERS=y | 74 | CONFIG_VM_EVENT_COUNTERS=y |
| 75 | CONFIG_SLAB=y | ||
| 76 | # CONFIG_SLUB is not set | ||
| 77 | # CONFIG_SLOB is not set | ||
| 78 | CONFIG_SLABINFO=y | ||
| 69 | CONFIG_RT_MUTEXES=y | 79 | CONFIG_RT_MUTEXES=y |
| 70 | # CONFIG_TINY_SHMEM is not set | 80 | # CONFIG_TINY_SHMEM is not set |
| 71 | CONFIG_BASE_SMALL=0 | 81 | CONFIG_BASE_SMALL=0 |
| 72 | # CONFIG_SLOB is not set | ||
| 73 | |||
| 74 | # | ||
| 75 | # Loadable module support | ||
| 76 | # | ||
| 77 | CONFIG_MODULES=y | 82 | CONFIG_MODULES=y |
| 78 | CONFIG_MODULE_UNLOAD=y | 83 | CONFIG_MODULE_UNLOAD=y |
| 79 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 84 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 80 | # CONFIG_MODVERSIONS is not set | 85 | # CONFIG_MODVERSIONS is not set |
| 81 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 86 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 82 | CONFIG_KMOD=y | 87 | CONFIG_KMOD=y |
| 83 | |||
| 84 | # | ||
| 85 | # Block layer | ||
| 86 | # | ||
| 87 | CONFIG_BLOCK=y | 88 | CONFIG_BLOCK=y |
| 88 | # CONFIG_LBD is not set | 89 | # CONFIG_LBD is not set |
| 89 | # CONFIG_BLK_DEV_IO_TRACE is not set | 90 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 90 | # CONFIG_LSF is not set | 91 | # CONFIG_LSF is not set |
| 92 | # CONFIG_BLK_DEV_BSG is not set | ||
| 91 | 93 | ||
| 92 | # | 94 | # |
| 93 | # IO Schedulers | 95 | # IO Schedulers |
| @@ -119,14 +121,16 @@ CONFIG_ARCH_AT91=y | |||
| 119 | # CONFIG_ARCH_NETX is not set | 121 | # CONFIG_ARCH_NETX is not set |
| 120 | # CONFIG_ARCH_H720X is not set | 122 | # CONFIG_ARCH_H720X is not set |
| 121 | # CONFIG_ARCH_IMX is not set | 123 | # CONFIG_ARCH_IMX is not set |
| 124 | # CONFIG_ARCH_IOP13XX is not set | ||
| 122 | # CONFIG_ARCH_IOP32X is not set | 125 | # CONFIG_ARCH_IOP32X is not set |
| 123 | # CONFIG_ARCH_IOP33X is not set | 126 | # CONFIG_ARCH_IOP33X is not set |
| 124 | # CONFIG_ARCH_IOP13XX is not set | ||
| 125 | # CONFIG_ARCH_IXP4XX is not set | ||
| 126 | # CONFIG_ARCH_IXP2000 is not set | ||
| 127 | # CONFIG_ARCH_IXP23XX is not set | 127 | # CONFIG_ARCH_IXP23XX is not set |
| 128 | # CONFIG_ARCH_IXP2000 is not set | ||
| 129 | # CONFIG_ARCH_IXP4XX is not set | ||
| 128 | # CONFIG_ARCH_L7200 is not set | 130 | # CONFIG_ARCH_L7200 is not set |
| 131 | # CONFIG_ARCH_KS8695 is not set | ||
| 129 | # CONFIG_ARCH_NS9XXX is not set | 132 | # CONFIG_ARCH_NS9XXX is not set |
| 133 | # CONFIG_ARCH_MXC is not set | ||
| 130 | # CONFIG_ARCH_PNX4008 is not set | 134 | # CONFIG_ARCH_PNX4008 is not set |
| 131 | # CONFIG_ARCH_PXA is not set | 135 | # CONFIG_ARCH_PXA is not set |
| 132 | # CONFIG_ARCH_RPC is not set | 136 | # CONFIG_ARCH_RPC is not set |
| @@ -134,9 +138,18 @@ CONFIG_ARCH_AT91=y | |||
| 134 | # CONFIG_ARCH_S3C2410 is not set | 138 | # CONFIG_ARCH_S3C2410 is not set |
| 135 | # CONFIG_ARCH_SHARK is not set | 139 | # CONFIG_ARCH_SHARK is not set |
| 136 | # CONFIG_ARCH_LH7A40X is not set | 140 | # CONFIG_ARCH_LH7A40X is not set |
| 141 | # CONFIG_ARCH_DAVINCI is not set | ||
| 137 | # CONFIG_ARCH_OMAP is not set | 142 | # CONFIG_ARCH_OMAP is not set |
| 138 | 143 | ||
| 139 | # | 144 | # |
| 145 | # Boot options | ||
| 146 | # | ||
| 147 | |||
| 148 | # | ||
| 149 | # Power management | ||
| 150 | # | ||
| 151 | |||
| 152 | # | ||
| 140 | # Atmel AT91 System-on-Chip | 153 | # Atmel AT91 System-on-Chip |
| 141 | # | 154 | # |
| 142 | # CONFIG_ARCH_AT91RM9200 is not set | 155 | # CONFIG_ARCH_AT91RM9200 is not set |
| @@ -144,6 +157,8 @@ CONFIG_ARCH_AT91=y | |||
| 144 | # CONFIG_ARCH_AT91SAM9261 is not set | 157 | # CONFIG_ARCH_AT91SAM9261 is not set |
| 145 | # CONFIG_ARCH_AT91SAM9263 is not set | 158 | # CONFIG_ARCH_AT91SAM9263 is not set |
| 146 | CONFIG_ARCH_AT91SAM9RL=y | 159 | CONFIG_ARCH_AT91SAM9RL=y |
| 160 | # CONFIG_ARCH_AT91X40 is not set | ||
| 161 | CONFIG_AT91_PMC_UNIT=y | ||
| 147 | 162 | ||
| 148 | # | 163 | # |
| 149 | # AT91SAM9RL Board Type | 164 | # AT91SAM9RL Board Type |
| @@ -157,7 +172,9 @@ CONFIG_MACH_AT91SAM9RLEK=y | |||
| 157 | # | 172 | # |
| 158 | # AT91 Feature Selections | 173 | # AT91 Feature Selections |
| 159 | # | 174 | # |
| 160 | # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set | 175 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y |
| 176 | # CONFIG_ATMEL_TCLIB is not set | ||
| 177 | CONFIG_AT91_TIMER_HZ=100 | ||
| 161 | 178 | ||
| 162 | # | 179 | # |
| 163 | # Processor Type | 180 | # Processor Type |
| @@ -185,15 +202,14 @@ CONFIG_CPU_CP15_MMU=y | |||
| 185 | # | 202 | # |
| 186 | # Bus support | 203 | # Bus support |
| 187 | # | 204 | # |
| 188 | 205 | # CONFIG_PCI_SYSCALL is not set | |
| 189 | # | 206 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 190 | # PCCARD (PCMCIA/CardBus) support | ||
| 191 | # | ||
| 192 | # CONFIG_PCCARD is not set | 207 | # CONFIG_PCCARD is not set |
| 193 | 208 | ||
| 194 | # | 209 | # |
| 195 | # Kernel Features | 210 | # Kernel Features |
| 196 | # | 211 | # |
| 212 | # CONFIG_TICK_ONESHOT is not set | ||
| 197 | # CONFIG_PREEMPT is not set | 213 | # CONFIG_PREEMPT is not set |
| 198 | # CONFIG_NO_IDLE_HZ is not set | 214 | # CONFIG_NO_IDLE_HZ is not set |
| 199 | CONFIG_HZ=100 | 215 | CONFIG_HZ=100 |
| @@ -206,9 +222,12 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 206 | CONFIG_FLATMEM=y | 222 | CONFIG_FLATMEM=y |
| 207 | CONFIG_FLAT_NODE_MEM_MAP=y | 223 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 208 | # CONFIG_SPARSEMEM_STATIC is not set | 224 | # CONFIG_SPARSEMEM_STATIC is not set |
| 225 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 209 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 226 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 210 | # CONFIG_RESOURCES_64BIT is not set | 227 | # CONFIG_RESOURCES_64BIT is not set |
| 211 | CONFIG_ZONE_DMA_FLAG=1 | 228 | CONFIG_ZONE_DMA_FLAG=1 |
| 229 | CONFIG_BOUNCE=y | ||
| 230 | CONFIG_VIRT_TO_BUS=y | ||
| 212 | # CONFIG_LEDS is not set | 231 | # CONFIG_LEDS is not set |
| 213 | CONFIG_ALIGNMENT_TRAP=y | 232 | CONFIG_ALIGNMENT_TRAP=y |
| 214 | 233 | ||
| @@ -245,6 +264,7 @@ CONFIG_BINFMT_ELF=y | |||
| 245 | # Power management options | 264 | # Power management options |
| 246 | # | 265 | # |
| 247 | # CONFIG_PM is not set | 266 | # CONFIG_PM is not set |
| 267 | CONFIG_SUSPEND_UP_POSSIBLE=y | ||
| 248 | 268 | ||
| 249 | # | 269 | # |
| 250 | # Networking | 270 | # Networking |
| @@ -254,7 +274,6 @@ CONFIG_NET=y | |||
| 254 | # | 274 | # |
| 255 | # Networking options | 275 | # Networking options |
| 256 | # | 276 | # |
| 257 | # CONFIG_NETDEBUG is not set | ||
| 258 | # CONFIG_PACKET is not set | 277 | # CONFIG_PACKET is not set |
| 259 | CONFIG_UNIX=y | 278 | CONFIG_UNIX=y |
| 260 | # CONFIG_NET_KEY is not set | 279 | # CONFIG_NET_KEY is not set |
| @@ -271,10 +290,6 @@ CONFIG_UNIX=y | |||
| 271 | # CONFIG_X25 is not set | 290 | # CONFIG_X25 is not set |
| 272 | # CONFIG_LAPB is not set | 291 | # CONFIG_LAPB is not set |
| 273 | # CONFIG_WAN_ROUTER is not set | 292 | # CONFIG_WAN_ROUTER is not set |
| 274 | |||
| 275 | # | ||
| 276 | # QoS and/or fair queueing | ||
| 277 | # | ||
| 278 | # CONFIG_NET_SCHED is not set | 293 | # CONFIG_NET_SCHED is not set |
| 279 | 294 | ||
| 280 | # | 295 | # |
| @@ -284,7 +299,16 @@ CONFIG_UNIX=y | |||
| 284 | # CONFIG_HAMRADIO is not set | 299 | # CONFIG_HAMRADIO is not set |
| 285 | # CONFIG_IRDA is not set | 300 | # CONFIG_IRDA is not set |
| 286 | # CONFIG_BT is not set | 301 | # CONFIG_BT is not set |
| 302 | |||
| 303 | # | ||
| 304 | # Wireless | ||
| 305 | # | ||
| 306 | # CONFIG_CFG80211 is not set | ||
| 307 | # CONFIG_WIRELESS_EXT is not set | ||
| 308 | # CONFIG_MAC80211 is not set | ||
| 287 | # CONFIG_IEEE80211 is not set | 309 | # CONFIG_IEEE80211 is not set |
| 310 | # CONFIG_RFKILL is not set | ||
| 311 | # CONFIG_NET_9P is not set | ||
| 288 | 312 | ||
| 289 | # | 313 | # |
| 290 | # Device Drivers | 314 | # Device Drivers |
| @@ -293,21 +317,14 @@ CONFIG_UNIX=y | |||
| 293 | # | 317 | # |
| 294 | # Generic Driver Options | 318 | # Generic Driver Options |
| 295 | # | 319 | # |
| 320 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 296 | CONFIG_STANDALONE=y | 321 | CONFIG_STANDALONE=y |
| 297 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 322 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 298 | # CONFIG_FW_LOADER is not set | 323 | # CONFIG_FW_LOADER is not set |
| 299 | # CONFIG_DEBUG_DRIVER is not set | 324 | # CONFIG_DEBUG_DRIVER is not set |
| 300 | # CONFIG_DEBUG_DEVRES is not set | 325 | # CONFIG_DEBUG_DEVRES is not set |
| 301 | # CONFIG_SYS_HYPERVISOR is not set | 326 | # CONFIG_SYS_HYPERVISOR is not set |
| 302 | |||
| 303 | # | ||
| 304 | # Connector - unified userspace <-> kernelspace linker | ||
| 305 | # | ||
| 306 | # CONFIG_CONNECTOR is not set | 327 | # CONFIG_CONNECTOR is not set |
| 307 | |||
| 308 | # | ||
| 309 | # Memory Technology Devices (MTD) | ||
| 310 | # | ||
| 311 | CONFIG_MTD=y | 328 | CONFIG_MTD=y |
| 312 | # CONFIG_MTD_DEBUG is not set | 329 | # CONFIG_MTD_DEBUG is not set |
| 313 | CONFIG_MTD_CONCAT=y | 330 | CONFIG_MTD_CONCAT=y |
| @@ -327,6 +344,7 @@ CONFIG_MTD_BLOCK=y | |||
| 327 | # CONFIG_INFTL is not set | 344 | # CONFIG_INFTL is not set |
| 328 | # CONFIG_RFD_FTL is not set | 345 | # CONFIG_RFD_FTL is not set |
| 329 | # CONFIG_SSFDC is not set | 346 | # CONFIG_SSFDC is not set |
| 347 | # CONFIG_MTD_OOPS is not set | ||
| 330 | 348 | ||
| 331 | # | 349 | # |
| 332 | # RAM/ROM/Flash chip drivers | 350 | # RAM/ROM/Flash chip drivers |
| @@ -346,7 +364,6 @@ CONFIG_MTD_CFI_I2=y | |||
| 346 | # CONFIG_MTD_RAM is not set | 364 | # CONFIG_MTD_RAM is not set |
| 347 | # CONFIG_MTD_ROM is not set | 365 | # CONFIG_MTD_ROM is not set |
| 348 | # CONFIG_MTD_ABSENT is not set | 366 | # CONFIG_MTD_ABSENT is not set |
| 349 | # CONFIG_MTD_OBSOLETE_CHIPS is not set | ||
| 350 | 367 | ||
| 351 | # | 368 | # |
| 352 | # Mapping drivers for chip access | 369 | # Mapping drivers for chip access |
| @@ -370,36 +387,23 @@ CONFIG_MTD_DATAFLASH=y | |||
| 370 | # CONFIG_MTD_DOC2000 is not set | 387 | # CONFIG_MTD_DOC2000 is not set |
| 371 | # CONFIG_MTD_DOC2001 is not set | 388 | # CONFIG_MTD_DOC2001 is not set |
| 372 | # CONFIG_MTD_DOC2001PLUS is not set | 389 | # CONFIG_MTD_DOC2001PLUS is not set |
| 373 | |||
| 374 | # | ||
| 375 | # NAND Flash Device Drivers | ||
| 376 | # | ||
| 377 | CONFIG_MTD_NAND=y | 390 | CONFIG_MTD_NAND=y |
| 378 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | 391 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set |
| 379 | # CONFIG_MTD_NAND_ECC_SMC is not set | 392 | # CONFIG_MTD_NAND_ECC_SMC is not set |
| 393 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 380 | CONFIG_MTD_NAND_IDS=y | 394 | CONFIG_MTD_NAND_IDS=y |
| 381 | # CONFIG_MTD_NAND_DISKONCHIP is not set | 395 | # CONFIG_MTD_NAND_DISKONCHIP is not set |
| 382 | CONFIG_MTD_NAND_AT91=y | 396 | CONFIG_MTD_NAND_AT91=y |
| 383 | # CONFIG_MTD_NAND_NANDSIM is not set | 397 | # CONFIG_MTD_NAND_NANDSIM is not set |
| 384 | 398 | # CONFIG_MTD_NAND_PLATFORM is not set | |
| 385 | # | ||
| 386 | # OneNAND Flash Device Drivers | ||
| 387 | # | ||
| 388 | # CONFIG_MTD_ONENAND is not set | 399 | # CONFIG_MTD_ONENAND is not set |
| 389 | 400 | ||
| 390 | # | 401 | # |
| 391 | # Parallel port support | 402 | # UBI - Unsorted block images |
| 392 | # | 403 | # |
| 404 | # CONFIG_MTD_UBI is not set | ||
| 393 | # CONFIG_PARPORT is not set | 405 | # CONFIG_PARPORT is not set |
| 394 | 406 | CONFIG_BLK_DEV=y | |
| 395 | # | ||
| 396 | # Plug and Play support | ||
| 397 | # | ||
| 398 | # CONFIG_PNPACPI is not set | ||
| 399 | |||
| 400 | # | ||
| 401 | # Block devices | ||
| 402 | # | ||
| 403 | # CONFIG_BLK_DEV_COW_COMMON is not set | 407 | # CONFIG_BLK_DEV_COW_COMMON is not set |
| 404 | CONFIG_BLK_DEV_LOOP=y | 408 | CONFIG_BLK_DEV_LOOP=y |
| 405 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | 409 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set |
| @@ -410,12 +414,16 @@ CONFIG_BLK_DEV_RAM_SIZE=24576 | |||
| 410 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 414 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 |
| 411 | # CONFIG_CDROM_PKTCDVD is not set | 415 | # CONFIG_CDROM_PKTCDVD is not set |
| 412 | # CONFIG_ATA_OVER_ETH is not set | 416 | # CONFIG_ATA_OVER_ETH is not set |
| 417 | CONFIG_MISC_DEVICES=y | ||
| 418 | # CONFIG_EEPROM_93CX6 is not set | ||
| 419 | CONFIG_ATMEL_SSC=y | ||
| 413 | 420 | ||
| 414 | # | 421 | # |
| 415 | # SCSI device support | 422 | # SCSI device support |
| 416 | # | 423 | # |
| 417 | # CONFIG_RAID_ATTRS is not set | 424 | # CONFIG_RAID_ATTRS is not set |
| 418 | CONFIG_SCSI=y | 425 | CONFIG_SCSI=y |
| 426 | CONFIG_SCSI_DMA=y | ||
| 419 | # CONFIG_SCSI_TGT is not set | 427 | # CONFIG_SCSI_TGT is not set |
| 420 | # CONFIG_SCSI_NETLINK is not set | 428 | # CONFIG_SCSI_NETLINK is not set |
| 421 | CONFIG_SCSI_PROC_FS=y | 429 | CONFIG_SCSI_PROC_FS=y |
| @@ -437,6 +445,7 @@ CONFIG_SCSI_MULTI_LUN=y | |||
| 437 | # CONFIG_SCSI_CONSTANTS is not set | 445 | # CONFIG_SCSI_CONSTANTS is not set |
| 438 | # CONFIG_SCSI_LOGGING is not set | 446 | # CONFIG_SCSI_LOGGING is not set |
| 439 | # CONFIG_SCSI_SCAN_ASYNC is not set | 447 | # CONFIG_SCSI_SCAN_ASYNC is not set |
| 448 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 440 | 449 | ||
| 441 | # | 450 | # |
| 442 | # SCSI Transports | 451 | # SCSI Transports |
| @@ -444,47 +453,13 @@ CONFIG_SCSI_MULTI_LUN=y | |||
| 444 | # CONFIG_SCSI_SPI_ATTRS is not set | 453 | # CONFIG_SCSI_SPI_ATTRS is not set |
| 445 | # CONFIG_SCSI_FC_ATTRS is not set | 454 | # CONFIG_SCSI_FC_ATTRS is not set |
| 446 | # CONFIG_SCSI_ISCSI_ATTRS is not set | 455 | # CONFIG_SCSI_ISCSI_ATTRS is not set |
| 447 | # CONFIG_SCSI_SAS_ATTRS is not set | ||
| 448 | # CONFIG_SCSI_SAS_LIBSAS is not set | 456 | # CONFIG_SCSI_SAS_LIBSAS is not set |
| 449 | 457 | # CONFIG_SCSI_SRP_ATTRS is not set | |
| 450 | # | 458 | CONFIG_SCSI_LOWLEVEL=y |
| 451 | # SCSI low-level drivers | ||
| 452 | # | ||
| 453 | # CONFIG_SCSI_DEBUG is not set | 459 | # CONFIG_SCSI_DEBUG is not set |
| 454 | |||
| 455 | # | ||
| 456 | # Serial ATA (prod) and Parallel ATA (experimental) drivers | ||
| 457 | # | ||
| 458 | # CONFIG_ATA is not set | 460 | # CONFIG_ATA is not set |
| 459 | |||
| 460 | # | ||
| 461 | # Multi-device support (RAID and LVM) | ||
| 462 | # | ||
| 463 | # CONFIG_MD is not set | 461 | # CONFIG_MD is not set |
| 464 | |||
| 465 | # | ||
| 466 | # Fusion MPT device support | ||
| 467 | # | ||
| 468 | # CONFIG_FUSION is not set | ||
| 469 | |||
| 470 | # | ||
| 471 | # IEEE 1394 (FireWire) support | ||
| 472 | # | ||
| 473 | |||
| 474 | # | ||
| 475 | # I2O device support | ||
| 476 | # | ||
| 477 | |||
| 478 | # | ||
| 479 | # Network device support | ||
| 480 | # | ||
| 481 | # CONFIG_NETDEVICES is not set | 462 | # CONFIG_NETDEVICES is not set |
| 482 | # CONFIG_NETPOLL is not set | ||
| 483 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 484 | |||
| 485 | # | ||
| 486 | # ISDN subsystem | ||
| 487 | # | ||
| 488 | # CONFIG_ISDN is not set | 463 | # CONFIG_ISDN is not set |
| 489 | 464 | ||
| 490 | # | 465 | # |
| @@ -492,6 +467,7 @@ CONFIG_SCSI_MULTI_LUN=y | |||
| 492 | # | 467 | # |
| 493 | CONFIG_INPUT=y | 468 | CONFIG_INPUT=y |
| 494 | # CONFIG_INPUT_FF_MEMLESS is not set | 469 | # CONFIG_INPUT_FF_MEMLESS is not set |
| 470 | # CONFIG_INPUT_POLLDEV is not set | ||
| 495 | 471 | ||
| 496 | # | 472 | # |
| 497 | # Userland interfaces | 473 | # Userland interfaces |
| @@ -501,7 +477,6 @@ CONFIG_INPUT_MOUSEDEV=y | |||
| 501 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 | 477 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 |
| 502 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 | 478 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 |
| 503 | # CONFIG_INPUT_JOYDEV is not set | 479 | # CONFIG_INPUT_JOYDEV is not set |
| 504 | # CONFIG_INPUT_TSDEV is not set | ||
| 505 | CONFIG_INPUT_EVDEV=y | 480 | CONFIG_INPUT_EVDEV=y |
| 506 | # CONFIG_INPUT_EVBUG is not set | 481 | # CONFIG_INPUT_EVBUG is not set |
| 507 | 482 | ||
| @@ -511,8 +486,10 @@ CONFIG_INPUT_EVDEV=y | |||
| 511 | # CONFIG_INPUT_KEYBOARD is not set | 486 | # CONFIG_INPUT_KEYBOARD is not set |
| 512 | # CONFIG_INPUT_MOUSE is not set | 487 | # CONFIG_INPUT_MOUSE is not set |
| 513 | # CONFIG_INPUT_JOYSTICK is not set | 488 | # CONFIG_INPUT_JOYSTICK is not set |
| 489 | # CONFIG_INPUT_TABLET is not set | ||
| 514 | CONFIG_INPUT_TOUCHSCREEN=y | 490 | CONFIG_INPUT_TOUCHSCREEN=y |
| 515 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | 491 | # CONFIG_TOUCHSCREEN_ADS7846 is not set |
| 492 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 516 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 493 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| 517 | # CONFIG_TOUCHSCREEN_ELO is not set | 494 | # CONFIG_TOUCHSCREEN_ELO is not set |
| 518 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | 495 | # CONFIG_TOUCHSCREEN_MTOUCH is not set |
| @@ -521,6 +498,7 @@ CONFIG_INPUT_TOUCHSCREEN=y | |||
| 521 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | 498 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set |
| 522 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | 499 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set |
| 523 | # CONFIG_TOUCHSCREEN_UCB1400 is not set | 500 | # CONFIG_TOUCHSCREEN_UCB1400 is not set |
| 501 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
| 524 | # CONFIG_INPUT_MISC is not set | 502 | # CONFIG_INPUT_MISC is not set |
| 525 | 503 | ||
| 526 | # | 504 | # |
| @@ -554,37 +532,50 @@ CONFIG_SERIAL_CORE_CONSOLE=y | |||
| 554 | CONFIG_UNIX98_PTYS=y | 532 | CONFIG_UNIX98_PTYS=y |
| 555 | CONFIG_LEGACY_PTYS=y | 533 | CONFIG_LEGACY_PTYS=y |
| 556 | CONFIG_LEGACY_PTY_COUNT=256 | 534 | CONFIG_LEGACY_PTY_COUNT=256 |
| 557 | |||
| 558 | # | ||
| 559 | # IPMI | ||
| 560 | # | ||
| 561 | # CONFIG_IPMI_HANDLER is not set | 535 | # CONFIG_IPMI_HANDLER is not set |
| 562 | 536 | # CONFIG_HW_RANDOM is not set | |
| 563 | # | ||
| 564 | # Watchdog Cards | ||
| 565 | # | ||
| 566 | CONFIG_WATCHDOG=y | ||
| 567 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 568 | |||
| 569 | # | ||
| 570 | # Watchdog Device Drivers | ||
| 571 | # | ||
| 572 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 573 | CONFIG_HW_RANDOM=y | ||
| 574 | # CONFIG_NVRAM is not set | 537 | # CONFIG_NVRAM is not set |
| 575 | # CONFIG_DTLK is not set | ||
| 576 | # CONFIG_R3964 is not set | 538 | # CONFIG_R3964 is not set |
| 577 | # CONFIG_RAW_DRIVER is not set | 539 | # CONFIG_RAW_DRIVER is not set |
| 540 | # CONFIG_TCG_TPM is not set | ||
| 541 | CONFIG_I2C=y | ||
| 542 | CONFIG_I2C_BOARDINFO=y | ||
| 543 | CONFIG_I2C_CHARDEV=y | ||
| 578 | 544 | ||
| 579 | # | 545 | # |
| 580 | # TPM devices | 546 | # I2C Algorithms |
| 581 | # | 547 | # |
| 582 | # CONFIG_TCG_TPM is not set | 548 | CONFIG_I2C_ALGOBIT=y |
| 549 | # CONFIG_I2C_ALGOPCF is not set | ||
| 550 | # CONFIG_I2C_ALGOPCA is not set | ||
| 583 | 551 | ||
| 584 | # | 552 | # |
| 585 | # I2C support | 553 | # I2C Hardware Bus support |
| 586 | # | 554 | # |
| 587 | # CONFIG_I2C is not set | 555 | CONFIG_I2C_GPIO=y |
| 556 | # CONFIG_I2C_OCORES is not set | ||
| 557 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 558 | # CONFIG_I2C_SIMTEC is not set | ||
| 559 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 560 | # CONFIG_I2C_STUB is not set | ||
| 561 | # CONFIG_I2C_PCA is not set | ||
| 562 | |||
| 563 | # | ||
| 564 | # Miscellaneous I2C Chip support | ||
| 565 | # | ||
| 566 | # CONFIG_SENSORS_DS1337 is not set | ||
| 567 | # CONFIG_SENSORS_DS1374 is not set | ||
| 568 | # CONFIG_DS1682 is not set | ||
| 569 | # CONFIG_SENSORS_EEPROM is not set | ||
| 570 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 571 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 572 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 573 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 574 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 575 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 576 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 577 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 578 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 588 | 579 | ||
| 589 | # | 580 | # |
| 590 | # SPI support | 581 | # SPI support |
| @@ -603,21 +594,25 @@ CONFIG_SPI_ATMEL=y | |||
| 603 | # SPI Protocol Masters | 594 | # SPI Protocol Masters |
| 604 | # | 595 | # |
| 605 | # CONFIG_SPI_AT25 is not set | 596 | # CONFIG_SPI_AT25 is not set |
| 606 | 597 | # CONFIG_SPI_SPIDEV is not set | |
| 607 | # | 598 | # CONFIG_SPI_TLE62X0 is not set |
| 608 | # Dallas's 1-wire bus | ||
| 609 | # | ||
| 610 | # CONFIG_W1 is not set | 599 | # CONFIG_W1 is not set |
| 600 | # CONFIG_POWER_SUPPLY is not set | ||
| 601 | # CONFIG_HWMON is not set | ||
| 602 | CONFIG_WATCHDOG=y | ||
| 603 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 611 | 604 | ||
| 612 | # | 605 | # |
| 613 | # Hardware Monitoring support | 606 | # Watchdog Device Drivers |
| 614 | # | 607 | # |
| 615 | # CONFIG_HWMON is not set | 608 | # CONFIG_SOFT_WATCHDOG is not set |
| 616 | # CONFIG_HWMON_VID is not set | 609 | CONFIG_AT91SAM9_WATCHDOG=y |
| 617 | 610 | ||
| 618 | # | 611 | # |
| 619 | # Misc devices | 612 | # Sonics Silicon Backplane |
| 620 | # | 613 | # |
| 614 | CONFIG_SSB_POSSIBLE=y | ||
| 615 | # CONFIG_SSB is not set | ||
| 621 | 616 | ||
| 622 | # | 617 | # |
| 623 | # Multifunction device drivers | 618 | # Multifunction device drivers |
| @@ -625,37 +620,28 @@ CONFIG_SPI_ATMEL=y | |||
| 625 | # CONFIG_MFD_SM501 is not set | 620 | # CONFIG_MFD_SM501 is not set |
| 626 | 621 | ||
| 627 | # | 622 | # |
| 628 | # LED devices | ||
| 629 | # | ||
| 630 | # CONFIG_NEW_LEDS is not set | ||
| 631 | |||
| 632 | # | ||
| 633 | # LED drivers | ||
| 634 | # | ||
| 635 | |||
| 636 | # | ||
| 637 | # LED Triggers | ||
| 638 | # | ||
| 639 | |||
| 640 | # | ||
| 641 | # Multimedia devices | 623 | # Multimedia devices |
| 642 | # | 624 | # |
| 643 | # CONFIG_VIDEO_DEV is not set | 625 | # CONFIG_VIDEO_DEV is not set |
| 644 | 626 | # CONFIG_DAB is not set | |
| 645 | # | ||
| 646 | # Digital Video Broadcasting Devices | ||
| 647 | # | ||
| 648 | 627 | ||
| 649 | # | 628 | # |
| 650 | # Graphics support | 629 | # Graphics support |
| 651 | # | 630 | # |
| 652 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 631 | # CONFIG_VGASTATE is not set |
| 632 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 653 | CONFIG_FB=y | 633 | CONFIG_FB=y |
| 654 | # CONFIG_FIRMWARE_EDID is not set | 634 | # CONFIG_FIRMWARE_EDID is not set |
| 655 | # CONFIG_FB_DDC is not set | 635 | # CONFIG_FB_DDC is not set |
| 656 | CONFIG_FB_CFB_FILLRECT=y | 636 | CONFIG_FB_CFB_FILLRECT=y |
| 657 | CONFIG_FB_CFB_COPYAREA=y | 637 | CONFIG_FB_CFB_COPYAREA=y |
| 658 | CONFIG_FB_CFB_IMAGEBLIT=y | 638 | CONFIG_FB_CFB_IMAGEBLIT=y |
| 639 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 640 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 641 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 642 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 643 | # CONFIG_FB_SYS_FOPS is not set | ||
| 644 | CONFIG_FB_DEFERRED_IO=y | ||
| 659 | # CONFIG_FB_SVGALIB is not set | 645 | # CONFIG_FB_SVGALIB is not set |
| 660 | # CONFIG_FB_MACMODES is not set | 646 | # CONFIG_FB_MACMODES is not set |
| 661 | # CONFIG_FB_BACKLIGHT is not set | 647 | # CONFIG_FB_BACKLIGHT is not set |
| @@ -665,9 +651,16 @@ CONFIG_FB_CFB_IMAGEBLIT=y | |||
| 665 | # | 651 | # |
| 666 | # Frame buffer hardware drivers | 652 | # Frame buffer hardware drivers |
| 667 | # | 653 | # |
| 654 | # CONFIG_FB_S1D15605 is not set | ||
| 668 | # CONFIG_FB_S1D13XXX is not set | 655 | # CONFIG_FB_S1D13XXX is not set |
| 669 | CONFIG_FB_ATMEL=y | 656 | CONFIG_FB_ATMEL=y |
| 670 | # CONFIG_FB_VIRTUAL is not set | 657 | # CONFIG_FB_VIRTUAL is not set |
| 658 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 659 | |||
| 660 | # | ||
| 661 | # Display device support | ||
| 662 | # | ||
| 663 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 671 | 664 | ||
| 672 | # | 665 | # |
| 673 | # Console display driver support | 666 | # Console display driver support |
| @@ -675,97 +668,97 @@ CONFIG_FB_ATMEL=y | |||
| 675 | # CONFIG_VGA_CONSOLE is not set | 668 | # CONFIG_VGA_CONSOLE is not set |
| 676 | CONFIG_DUMMY_CONSOLE=y | 669 | CONFIG_DUMMY_CONSOLE=y |
| 677 | # CONFIG_FRAMEBUFFER_CONSOLE is not set | 670 | # CONFIG_FRAMEBUFFER_CONSOLE is not set |
| 678 | |||
| 679 | # | ||
| 680 | # Logo configuration | ||
| 681 | # | ||
| 682 | # CONFIG_LOGO is not set | 671 | # CONFIG_LOGO is not set |
| 683 | 672 | ||
| 684 | # | 673 | # |
| 685 | # Sound | 674 | # Sound |
| 686 | # | 675 | # |
| 687 | CONFIG_SOUND=y | 676 | # CONFIG_SOUND is not set |
| 688 | 677 | CONFIG_HID_SUPPORT=y | |
| 689 | # | 678 | CONFIG_HID=y |
| 690 | # Advanced Linux Sound Architecture | 679 | # CONFIG_HID_DEBUG is not set |
| 691 | # | 680 | # CONFIG_HIDRAW is not set |
| 692 | CONFIG_SND=y | 681 | CONFIG_USB_SUPPORT=y |
| 693 | CONFIG_SND_TIMER=y | 682 | CONFIG_USB_ARCH_HAS_HCD=y |
| 694 | CONFIG_SND_PCM=y | 683 | CONFIG_USB_ARCH_HAS_OHCI=y |
| 695 | CONFIG_SND_SEQUENCER=y | 684 | # CONFIG_USB_ARCH_HAS_EHCI is not set |
| 696 | CONFIG_SND_SEQ_DUMMY=y | 685 | # CONFIG_USB is not set |
| 697 | CONFIG_SND_OSSEMUL=y | ||
| 698 | CONFIG_SND_MIXER_OSS=y | ||
| 699 | CONFIG_SND_PCM_OSS=y | ||
| 700 | CONFIG_SND_PCM_OSS_PLUGINS=y | ||
| 701 | CONFIG_SND_SEQUENCER_OSS=y | ||
| 702 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
| 703 | CONFIG_SND_SUPPORT_OLD_API=y | ||
| 704 | CONFIG_SND_VERBOSE_PROCFS=y | ||
| 705 | CONFIG_SND_VERBOSE_PRINTK=y | ||
| 706 | CONFIG_SND_DEBUG=y | ||
| 707 | CONFIG_SND_DEBUG_DETECT=y | ||
| 708 | # CONFIG_SND_PCM_XRUN_DEBUG is not set | ||
| 709 | |||
| 710 | # | ||
| 711 | # Generic devices | ||
| 712 | # | ||
| 713 | # CONFIG_SND_DUMMY is not set | ||
| 714 | # CONFIG_SND_VIRMIDI is not set | ||
| 715 | # CONFIG_SND_MTPAV is not set | ||
| 716 | # CONFIG_SND_SERIAL_U16550 is not set | ||
| 717 | # CONFIG_SND_MPU401 is not set | ||
| 718 | 686 | ||
| 719 | # | 687 | # |
| 720 | # ALSA ARM devices | 688 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' |
| 721 | # | 689 | # |
| 722 | 690 | ||
| 723 | # | 691 | # |
| 724 | # SoC audio support | 692 | # USB Gadget Support |
| 725 | # | 693 | # |
| 726 | # CONFIG_SND_SOC is not set | 694 | # CONFIG_USB_GADGET is not set |
| 695 | CONFIG_MMC=y | ||
| 696 | # CONFIG_MMC_DEBUG is not set | ||
| 697 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 727 | 698 | ||
| 728 | # | 699 | # |
| 729 | # Open Sound System | 700 | # MMC/SD Card Drivers |
| 730 | # | 701 | # |
| 731 | # CONFIG_SOUND_PRIME is not set | 702 | CONFIG_MMC_BLOCK=y |
| 703 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 704 | # CONFIG_SDIO_UART is not set | ||
| 732 | 705 | ||
| 733 | # | 706 | # |
| 734 | # HID Devices | 707 | # MMC/SD Host Controller Drivers |
| 735 | # | 708 | # |
| 736 | CONFIG_HID=y | 709 | CONFIG_MMC_AT91=y |
| 737 | # CONFIG_HID_DEBUG is not set | 710 | # CONFIG_MMC_SPI is not set |
| 711 | # CONFIG_NEW_LEDS is not set | ||
| 712 | CONFIG_RTC_LIB=y | ||
| 713 | CONFIG_RTC_CLASS=y | ||
| 714 | CONFIG_RTC_HCTOSYS=y | ||
| 715 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 716 | # CONFIG_RTC_DEBUG is not set | ||
| 738 | 717 | ||
| 739 | # | 718 | # |
| 740 | # USB support | 719 | # RTC interfaces |
| 741 | # | 720 | # |
| 742 | CONFIG_USB_ARCH_HAS_HCD=y | 721 | CONFIG_RTC_INTF_SYSFS=y |
| 743 | CONFIG_USB_ARCH_HAS_OHCI=y | 722 | CONFIG_RTC_INTF_PROC=y |
| 744 | # CONFIG_USB_ARCH_HAS_EHCI is not set | 723 | CONFIG_RTC_INTF_DEV=y |
| 745 | # CONFIG_USB is not set | 724 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set |
| 725 | # CONFIG_RTC_DRV_TEST is not set | ||
| 746 | 726 | ||
| 747 | # | 727 | # |
| 748 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 728 | # I2C RTC drivers |
| 749 | # | 729 | # |
| 730 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 731 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 732 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 733 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 734 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 735 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 736 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 737 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 738 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 739 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 750 | 740 | ||
| 751 | # | 741 | # |
| 752 | # USB Gadget Support | 742 | # SPI RTC drivers |
| 753 | # | 743 | # |
| 754 | # CONFIG_USB_GADGET is not set | 744 | # CONFIG_RTC_DRV_RS5C348 is not set |
| 745 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 755 | 746 | ||
| 756 | # | 747 | # |
| 757 | # MMC/SD Card support | 748 | # Platform RTC drivers |
| 758 | # | 749 | # |
| 759 | CONFIG_MMC=y | 750 | # CONFIG_RTC_DRV_CMOS is not set |
| 760 | # CONFIG_MMC_DEBUG is not set | 751 | # CONFIG_RTC_DRV_DS1553 is not set |
| 761 | CONFIG_MMC_BLOCK=y | 752 | # CONFIG_RTC_DRV_STK17TA8 is not set |
| 762 | CONFIG_MMC_AT91=y | 753 | # CONFIG_RTC_DRV_DS1742 is not set |
| 754 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 755 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 756 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 763 | 757 | ||
| 764 | # | 758 | # |
| 765 | # Real Time Clock | 759 | # on-CPU RTC drivers |
| 766 | # | 760 | # |
| 767 | CONFIG_RTC_LIB=y | 761 | CONFIG_RTC_DRV_AT91SAM9=y |
| 768 | # CONFIG_RTC_CLASS is not set | ||
| 769 | 762 | ||
| 770 | # | 763 | # |
| 771 | # File systems | 764 | # File systems |
| @@ -816,7 +809,6 @@ CONFIG_SYSFS=y | |||
| 816 | CONFIG_TMPFS=y | 809 | CONFIG_TMPFS=y |
| 817 | # CONFIG_TMPFS_POSIX_ACL is not set | 810 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 818 | # CONFIG_HUGETLB_PAGE is not set | 811 | # CONFIG_HUGETLB_PAGE is not set |
| 819 | CONFIG_RAMFS=y | ||
| 820 | # CONFIG_CONFIGFS_FS is not set | 812 | # CONFIG_CONFIGFS_FS is not set |
| 821 | 813 | ||
| 822 | # | 814 | # |
| @@ -836,20 +828,13 @@ CONFIG_CRAMFS=y | |||
| 836 | # CONFIG_QNX4FS_FS is not set | 828 | # CONFIG_QNX4FS_FS is not set |
| 837 | # CONFIG_SYSV_FS is not set | 829 | # CONFIG_SYSV_FS is not set |
| 838 | # CONFIG_UFS_FS is not set | 830 | # CONFIG_UFS_FS is not set |
| 839 | 831 | CONFIG_NETWORK_FILESYSTEMS=y | |
| 840 | # | ||
| 841 | # Network File Systems | ||
| 842 | # | ||
| 843 | 832 | ||
| 844 | # | 833 | # |
| 845 | # Partition Types | 834 | # Partition Types |
| 846 | # | 835 | # |
| 847 | # CONFIG_PARTITION_ADVANCED is not set | 836 | # CONFIG_PARTITION_ADVANCED is not set |
| 848 | CONFIG_MSDOS_PARTITION=y | 837 | CONFIG_MSDOS_PARTITION=y |
| 849 | |||
| 850 | # | ||
| 851 | # Native Language Support | ||
| 852 | # | ||
| 853 | CONFIG_NLS=y | 838 | CONFIG_NLS=y |
| 854 | CONFIG_NLS_DEFAULT="iso8859-1" | 839 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 855 | CONFIG_NLS_CODEPAGE_437=y | 840 | CONFIG_NLS_CODEPAGE_437=y |
| @@ -890,16 +875,15 @@ CONFIG_NLS_ISO8859_15=y | |||
| 890 | # CONFIG_NLS_KOI8_R is not set | 875 | # CONFIG_NLS_KOI8_R is not set |
| 891 | # CONFIG_NLS_KOI8_U is not set | 876 | # CONFIG_NLS_KOI8_U is not set |
| 892 | CONFIG_NLS_UTF8=y | 877 | CONFIG_NLS_UTF8=y |
| 893 | 878 | CONFIG_INSTRUMENTATION=y | |
| 894 | # | ||
| 895 | # Profiling support | ||
| 896 | # | ||
| 897 | # CONFIG_PROFILING is not set | 879 | # CONFIG_PROFILING is not set |
| 880 | # CONFIG_MARKERS is not set | ||
| 898 | 881 | ||
| 899 | # | 882 | # |
| 900 | # Kernel hacking | 883 | # Kernel hacking |
| 901 | # | 884 | # |
| 902 | # CONFIG_PRINTK_TIME is not set | 885 | # CONFIG_PRINTK_TIME is not set |
| 886 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 903 | CONFIG_ENABLE_MUST_CHECK=y | 887 | CONFIG_ENABLE_MUST_CHECK=y |
| 904 | # CONFIG_MAGIC_SYSRQ is not set | 888 | # CONFIG_MAGIC_SYSRQ is not set |
| 905 | # CONFIG_UNUSED_SYMBOLS is not set | 889 | # CONFIG_UNUSED_SYMBOLS is not set |
| @@ -907,8 +891,8 @@ CONFIG_ENABLE_MUST_CHECK=y | |||
| 907 | # CONFIG_HEADERS_CHECK is not set | 891 | # CONFIG_HEADERS_CHECK is not set |
| 908 | CONFIG_DEBUG_KERNEL=y | 892 | CONFIG_DEBUG_KERNEL=y |
| 909 | # CONFIG_DEBUG_SHIRQ is not set | 893 | # CONFIG_DEBUG_SHIRQ is not set |
| 910 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 911 | CONFIG_DETECT_SOFTLOCKUP=y | 894 | CONFIG_DETECT_SOFTLOCKUP=y |
| 895 | CONFIG_SCHED_DEBUG=y | ||
| 912 | # CONFIG_SCHEDSTATS is not set | 896 | # CONFIG_SCHEDSTATS is not set |
| 913 | # CONFIG_TIMER_STATS is not set | 897 | # CONFIG_TIMER_STATS is not set |
| 914 | # CONFIG_DEBUG_SLAB is not set | 898 | # CONFIG_DEBUG_SLAB is not set |
| @@ -916,6 +900,9 @@ CONFIG_DETECT_SOFTLOCKUP=y | |||
| 916 | # CONFIG_RT_MUTEX_TESTER is not set | 900 | # CONFIG_RT_MUTEX_TESTER is not set |
| 917 | # CONFIG_DEBUG_SPINLOCK is not set | 901 | # CONFIG_DEBUG_SPINLOCK is not set |
| 918 | # CONFIG_DEBUG_MUTEXES is not set | 902 | # CONFIG_DEBUG_MUTEXES is not set |
| 903 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 904 | # CONFIG_PROVE_LOCKING is not set | ||
| 905 | # CONFIG_LOCK_STAT is not set | ||
| 919 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 906 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 920 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | 907 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set |
| 921 | # CONFIG_DEBUG_KOBJECT is not set | 908 | # CONFIG_DEBUG_KOBJECT is not set |
| @@ -923,10 +910,13 @@ CONFIG_DEBUG_BUGVERBOSE=y | |||
| 923 | CONFIG_DEBUG_INFO=y | 910 | CONFIG_DEBUG_INFO=y |
| 924 | # CONFIG_DEBUG_VM is not set | 911 | # CONFIG_DEBUG_VM is not set |
| 925 | # CONFIG_DEBUG_LIST is not set | 912 | # CONFIG_DEBUG_LIST is not set |
| 913 | # CONFIG_DEBUG_SG is not set | ||
| 926 | CONFIG_FRAME_POINTER=y | 914 | CONFIG_FRAME_POINTER=y |
| 927 | CONFIG_FORCED_INLINING=y | 915 | CONFIG_FORCED_INLINING=y |
| 916 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 928 | # CONFIG_RCU_TORTURE_TEST is not set | 917 | # CONFIG_RCU_TORTURE_TEST is not set |
| 929 | # CONFIG_FAULT_INJECTION is not set | 918 | # CONFIG_FAULT_INJECTION is not set |
| 919 | # CONFIG_SAMPLES is not set | ||
| 930 | CONFIG_DEBUG_USER=y | 920 | CONFIG_DEBUG_USER=y |
| 931 | # CONFIG_DEBUG_ERRORS is not set | 921 | # CONFIG_DEBUG_ERRORS is not set |
| 932 | CONFIG_DEBUG_LL=y | 922 | CONFIG_DEBUG_LL=y |
| @@ -937,10 +927,7 @@ CONFIG_DEBUG_LL=y | |||
| 937 | # | 927 | # |
| 938 | # CONFIG_KEYS is not set | 928 | # CONFIG_KEYS is not set |
| 939 | # CONFIG_SECURITY is not set | 929 | # CONFIG_SECURITY is not set |
| 940 | 930 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | |
| 941 | # | ||
| 942 | # Cryptographic options | ||
| 943 | # | ||
| 944 | # CONFIG_CRYPTO is not set | 931 | # CONFIG_CRYPTO is not set |
| 945 | 932 | ||
| 946 | # | 933 | # |
| @@ -949,9 +936,12 @@ CONFIG_DEBUG_LL=y | |||
| 949 | CONFIG_BITREVERSE=y | 936 | CONFIG_BITREVERSE=y |
| 950 | # CONFIG_CRC_CCITT is not set | 937 | # CONFIG_CRC_CCITT is not set |
| 951 | # CONFIG_CRC16 is not set | 938 | # CONFIG_CRC16 is not set |
| 939 | # CONFIG_CRC_ITU_T is not set | ||
| 952 | CONFIG_CRC32=y | 940 | CONFIG_CRC32=y |
| 941 | # CONFIG_CRC7 is not set | ||
| 953 | # CONFIG_LIBCRC32C is not set | 942 | # CONFIG_LIBCRC32C is not set |
| 954 | CONFIG_ZLIB_INFLATE=y | 943 | CONFIG_ZLIB_INFLATE=y |
| 955 | CONFIG_PLIST=y | 944 | CONFIG_PLIST=y |
| 956 | CONFIG_HAS_IOMEM=y | 945 | CONFIG_HAS_IOMEM=y |
| 957 | CONFIG_HAS_IOPORT=y | 946 | CONFIG_HAS_IOPORT=y |
| 947 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/ateb9200_defconfig b/arch/arm/configs/ateb9200_defconfig index baa97698c744..d846a492e5ce 100644 --- a/arch/arm/configs/ateb9200_defconfig +++ b/arch/arm/configs/ateb9200_defconfig | |||
| @@ -714,7 +714,7 @@ CONFIG_I2C_ALGOPCA=m | |||
| 714 | # | 714 | # |
| 715 | # I2C Hardware Bus support | 715 | # I2C Hardware Bus support |
| 716 | # | 716 | # |
| 717 | CONFIG_I2C_AT91=m | 717 | CONFIG_I2C_GPIO=m |
| 718 | # CONFIG_I2C_PARPORT_LIGHT is not set | 718 | # CONFIG_I2C_PARPORT_LIGHT is not set |
| 719 | # CONFIG_I2C_STUB is not set | 719 | # CONFIG_I2C_STUB is not set |
| 720 | # CONFIG_I2C_PCA_ISA is not set | 720 | # CONFIG_I2C_PCA_ISA is not set |
diff --git a/arch/arm/configs/cam60_defconfig b/arch/arm/configs/cam60_defconfig new file mode 100644 index 000000000000..f3cd4a95373a --- /dev/null +++ b/arch/arm/configs/cam60_defconfig | |||
| @@ -0,0 +1,1228 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.24 | ||
| 4 | # Thu Mar 6 10:07:26 2008 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 18 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 20 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 22 | CONFIG_GENERIC_HWEIGHT=y | ||
| 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 24 | CONFIG_ZONE_DMA=y | ||
| 25 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 26 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 27 | |||
| 28 | # | ||
| 29 | # General setup | ||
| 30 | # | ||
| 31 | CONFIG_EXPERIMENTAL=y | ||
| 32 | CONFIG_BROKEN_ON_SMP=y | ||
| 33 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 34 | CONFIG_LOCALVERSION="" | ||
| 35 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 36 | CONFIG_SWAP=y | ||
| 37 | CONFIG_SYSVIPC=y | ||
| 38 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 39 | CONFIG_POSIX_MQUEUE=y | ||
| 40 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 41 | CONFIG_BSD_PROCESS_ACCT_V3=y | ||
| 42 | # CONFIG_TASKSTATS is not set | ||
| 43 | # CONFIG_USER_NS is not set | ||
| 44 | # CONFIG_PID_NS is not set | ||
| 45 | CONFIG_AUDIT=y | ||
| 46 | CONFIG_IKCONFIG=y | ||
| 47 | CONFIG_IKCONFIG_PROC=y | ||
| 48 | CONFIG_LOG_BUF_SHIFT=17 | ||
| 49 | # CONFIG_CGROUPS is not set | ||
| 50 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 51 | CONFIG_FAIR_USER_SCHED=y | ||
| 52 | # CONFIG_FAIR_CGROUP_SCHED is not set | ||
| 53 | CONFIG_SYSFS_DEPRECATED=y | ||
| 54 | CONFIG_RELAY=y | ||
| 55 | CONFIG_BLK_DEV_INITRD=y | ||
| 56 | CONFIG_INITRAMFS_SOURCE="" | ||
| 57 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
| 58 | CONFIG_SYSCTL=y | ||
| 59 | # CONFIG_EMBEDDED is not set | ||
| 60 | CONFIG_UID16=y | ||
| 61 | CONFIG_SYSCTL_SYSCALL=y | ||
| 62 | CONFIG_KALLSYMS=y | ||
| 63 | CONFIG_KALLSYMS_ALL=y | ||
| 64 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 65 | CONFIG_HOTPLUG=y | ||
| 66 | CONFIG_PRINTK=y | ||
| 67 | CONFIG_BUG=y | ||
| 68 | CONFIG_ELF_CORE=y | ||
| 69 | CONFIG_BASE_FULL=y | ||
| 70 | CONFIG_FUTEX=y | ||
| 71 | CONFIG_ANON_INODES=y | ||
| 72 | CONFIG_EPOLL=y | ||
| 73 | CONFIG_SIGNALFD=y | ||
| 74 | CONFIG_EVENTFD=y | ||
| 75 | CONFIG_SHMEM=y | ||
| 76 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 77 | CONFIG_SLUB_DEBUG=y | ||
| 78 | # CONFIG_SLAB is not set | ||
| 79 | CONFIG_SLUB=y | ||
| 80 | # CONFIG_SLOB is not set | ||
| 81 | CONFIG_SLABINFO=y | ||
| 82 | CONFIG_RT_MUTEXES=y | ||
| 83 | # CONFIG_TINY_SHMEM is not set | ||
| 84 | CONFIG_BASE_SMALL=0 | ||
| 85 | CONFIG_MODULES=y | ||
| 86 | CONFIG_MODULE_UNLOAD=y | ||
| 87 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 88 | CONFIG_MODVERSIONS=y | ||
| 89 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 90 | # CONFIG_KMOD is not set | ||
| 91 | CONFIG_BLOCK=y | ||
| 92 | CONFIG_LBD=y | ||
| 93 | CONFIG_BLK_DEV_IO_TRACE=y | ||
| 94 | # CONFIG_LSF is not set | ||
| 95 | # CONFIG_BLK_DEV_BSG is not set | ||
| 96 | |||
| 97 | # | ||
| 98 | # IO Schedulers | ||
| 99 | # | ||
| 100 | CONFIG_IOSCHED_NOOP=y | ||
| 101 | CONFIG_IOSCHED_AS=y | ||
| 102 | CONFIG_IOSCHED_DEADLINE=y | ||
| 103 | CONFIG_IOSCHED_CFQ=y | ||
| 104 | # CONFIG_DEFAULT_AS is not set | ||
| 105 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 106 | CONFIG_DEFAULT_CFQ=y | ||
| 107 | # CONFIG_DEFAULT_NOOP is not set | ||
| 108 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 109 | |||
| 110 | # | ||
| 111 | # System Type | ||
| 112 | # | ||
| 113 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 114 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 115 | # CONFIG_ARCH_REALVIEW is not set | ||
| 116 | # CONFIG_ARCH_VERSATILE is not set | ||
| 117 | CONFIG_ARCH_AT91=y | ||
| 118 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 119 | # CONFIG_ARCH_CLPS711X is not set | ||
| 120 | # CONFIG_ARCH_CO285 is not set | ||
| 121 | # CONFIG_ARCH_EBSA110 is not set | ||
| 122 | # CONFIG_ARCH_EP93XX is not set | ||
| 123 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 124 | # CONFIG_ARCH_NETX is not set | ||
| 125 | # CONFIG_ARCH_H720X is not set | ||
| 126 | # CONFIG_ARCH_IMX is not set | ||
| 127 | # CONFIG_ARCH_IOP13XX is not set | ||
| 128 | # CONFIG_ARCH_IOP32X is not set | ||
| 129 | # CONFIG_ARCH_IOP33X is not set | ||
| 130 | # CONFIG_ARCH_IXP23XX is not set | ||
| 131 | # CONFIG_ARCH_IXP2000 is not set | ||
| 132 | # CONFIG_ARCH_IXP4XX is not set | ||
| 133 | # CONFIG_ARCH_L7200 is not set | ||
| 134 | # CONFIG_ARCH_KS8695 is not set | ||
| 135 | # CONFIG_ARCH_NS9XXX is not set | ||
| 136 | # CONFIG_ARCH_MXC is not set | ||
| 137 | # CONFIG_ARCH_PNX4008 is not set | ||
| 138 | # CONFIG_ARCH_PXA is not set | ||
| 139 | # CONFIG_ARCH_RPC is not set | ||
| 140 | # CONFIG_ARCH_SA1100 is not set | ||
| 141 | # CONFIG_ARCH_S3C2410 is not set | ||
| 142 | # CONFIG_ARCH_SHARK is not set | ||
| 143 | # CONFIG_ARCH_LH7A40X is not set | ||
| 144 | # CONFIG_ARCH_DAVINCI is not set | ||
| 145 | # CONFIG_ARCH_OMAP is not set | ||
| 146 | |||
| 147 | # | ||
| 148 | # Boot options | ||
| 149 | # | ||
| 150 | |||
| 151 | # | ||
| 152 | # Power management | ||
| 153 | # | ||
| 154 | |||
| 155 | # | ||
| 156 | # Atmel AT91 System-on-Chip | ||
| 157 | # | ||
| 158 | # CONFIG_ARCH_AT91RM9200 is not set | ||
| 159 | CONFIG_ARCH_AT91SAM9260=y | ||
| 160 | # CONFIG_ARCH_AT91SAM9261 is not set | ||
| 161 | # CONFIG_ARCH_AT91SAM9263 is not set | ||
| 162 | # CONFIG_ARCH_AT91SAM9RL is not set | ||
| 163 | # CONFIG_ARCH_AT91CAP9 is not set | ||
| 164 | # CONFIG_ARCH_AT91X40 is not set | ||
| 165 | CONFIG_AT91_PMC_UNIT=y | ||
| 166 | |||
| 167 | # | ||
| 168 | # AT91SAM9260 Variants | ||
| 169 | # | ||
| 170 | # CONFIG_ARCH_AT91SAM9260_SAM9XE is not set | ||
| 171 | |||
| 172 | # | ||
| 173 | # AT91SAM9260 / AT91SAM9XE Board Type | ||
| 174 | # | ||
| 175 | # CONFIG_MACH_AT91SAM9260EK is not set | ||
| 176 | CONFIG_MACH_CAM60=y | ||
| 177 | # CONFIG_MACH_SAM9_L9260 is not set | ||
| 178 | |||
| 179 | # | ||
| 180 | # AT91 Board Options | ||
| 181 | # | ||
| 182 | |||
| 183 | # | ||
| 184 | # AT91 Feature Selections | ||
| 185 | # | ||
| 186 | # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set | ||
| 187 | CONFIG_AT91_TIMER_HZ=100 | ||
| 188 | CONFIG_AT91_EARLY_DBGU=y | ||
| 189 | # CONFIG_AT91_EARLY_USART0 is not set | ||
| 190 | # CONFIG_AT91_EARLY_USART1 is not set | ||
| 191 | # CONFIG_AT91_EARLY_USART2 is not set | ||
| 192 | # CONFIG_AT91_EARLY_USART3 is not set | ||
| 193 | # CONFIG_AT91_EARLY_USART4 is not set | ||
| 194 | # CONFIG_AT91_EARLY_USART5 is not set | ||
| 195 | |||
| 196 | # | ||
| 197 | # Processor Type | ||
| 198 | # | ||
| 199 | CONFIG_CPU_32=y | ||
| 200 | CONFIG_CPU_ARM926T=y | ||
| 201 | CONFIG_CPU_32v5=y | ||
| 202 | CONFIG_CPU_ABRT_EV5TJ=y | ||
| 203 | CONFIG_CPU_CACHE_VIVT=y | ||
| 204 | CONFIG_CPU_COPY_V4WB=y | ||
| 205 | CONFIG_CPU_TLB_V4WBI=y | ||
| 206 | CONFIG_CPU_CP15=y | ||
| 207 | CONFIG_CPU_CP15_MMU=y | ||
| 208 | |||
| 209 | # | ||
| 210 | # Processor Features | ||
| 211 | # | ||
| 212 | CONFIG_ARM_THUMB=y | ||
| 213 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 214 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 215 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 216 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set | ||
| 217 | # CONFIG_OUTER_CACHE is not set | ||
| 218 | |||
| 219 | # | ||
| 220 | # Bus support | ||
| 221 | # | ||
| 222 | # CONFIG_PCI_SYSCALL is not set | ||
| 223 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 224 | # CONFIG_PCCARD is not set | ||
| 225 | |||
| 226 | # | ||
| 227 | # Kernel Features | ||
| 228 | # | ||
| 229 | # CONFIG_TICK_ONESHOT is not set | ||
| 230 | # CONFIG_NO_HZ is not set | ||
| 231 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 232 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 233 | # CONFIG_PREEMPT is not set | ||
| 234 | CONFIG_HZ=100 | ||
| 235 | # CONFIG_AEABI is not set | ||
| 236 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | ||
| 237 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 238 | CONFIG_FLATMEM_MANUAL=y | ||
| 239 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 240 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 241 | CONFIG_FLATMEM=y | ||
| 242 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 243 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 244 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 245 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 246 | # CONFIG_RESOURCES_64BIT is not set | ||
| 247 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 248 | CONFIG_BOUNCE=y | ||
| 249 | CONFIG_VIRT_TO_BUS=y | ||
| 250 | # CONFIG_LEDS is not set | ||
| 251 | CONFIG_ALIGNMENT_TRAP=y | ||
| 252 | |||
| 253 | # | ||
| 254 | # Boot options | ||
| 255 | # | ||
| 256 | CONFIG_ZBOOT_ROM_TEXT=0 | ||
| 257 | CONFIG_ZBOOT_ROM_BSS=0x20004000 | ||
| 258 | # CONFIG_ZBOOT_ROM is not set | ||
| 259 | CONFIG_CMDLINE="console=ttyS0,115200 noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M" | ||
| 260 | # CONFIG_XIP_KERNEL is not set | ||
| 261 | # CONFIG_KEXEC is not set | ||
| 262 | |||
| 263 | # | ||
| 264 | # Floating point emulation | ||
| 265 | # | ||
| 266 | |||
| 267 | # | ||
| 268 | # At least one emulation must be selected | ||
| 269 | # | ||
| 270 | CONFIG_FPE_NWFPE=y | ||
| 271 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 272 | # CONFIG_FPE_FASTFPE is not set | ||
| 273 | # CONFIG_VFP is not set | ||
| 274 | |||
| 275 | # | ||
| 276 | # Userspace binary formats | ||
| 277 | # | ||
| 278 | CONFIG_BINFMT_ELF=y | ||
| 279 | CONFIG_BINFMT_AOUT=y | ||
| 280 | CONFIG_BINFMT_MISC=y | ||
| 281 | # CONFIG_ARTHUR is not set | ||
| 282 | |||
| 283 | # | ||
| 284 | # Power management options | ||
| 285 | # | ||
| 286 | # CONFIG_PM is not set | ||
| 287 | CONFIG_SUSPEND_UP_POSSIBLE=y | ||
| 288 | |||
| 289 | # | ||
| 290 | # Networking | ||
| 291 | # | ||
| 292 | CONFIG_NET=y | ||
| 293 | |||
| 294 | # | ||
| 295 | # Networking options | ||
| 296 | # | ||
| 297 | CONFIG_PACKET=y | ||
| 298 | # CONFIG_PACKET_MMAP is not set | ||
| 299 | CONFIG_UNIX=y | ||
| 300 | # CONFIG_NET_KEY is not set | ||
| 301 | CONFIG_INET=y | ||
| 302 | CONFIG_IP_MULTICAST=y | ||
| 303 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 304 | CONFIG_IP_FIB_HASH=y | ||
| 305 | CONFIG_IP_PNP=y | ||
| 306 | CONFIG_IP_PNP_DHCP=y | ||
| 307 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 308 | # CONFIG_IP_PNP_RARP is not set | ||
| 309 | # CONFIG_NET_IPIP is not set | ||
| 310 | # CONFIG_NET_IPGRE is not set | ||
| 311 | # CONFIG_IP_MROUTE is not set | ||
| 312 | # CONFIG_ARPD is not set | ||
| 313 | # CONFIG_SYN_COOKIES is not set | ||
| 314 | # CONFIG_INET_AH is not set | ||
| 315 | # CONFIG_INET_ESP is not set | ||
| 316 | # CONFIG_INET_IPCOMP is not set | ||
| 317 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 318 | # CONFIG_INET_TUNNEL is not set | ||
| 319 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 320 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 321 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 322 | # CONFIG_INET_LRO is not set | ||
| 323 | # CONFIG_INET_DIAG is not set | ||
| 324 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 325 | CONFIG_TCP_CONG_CUBIC=y | ||
| 326 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 327 | # CONFIG_TCP_MD5SIG is not set | ||
| 328 | # CONFIG_IPV6 is not set | ||
| 329 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 330 | # CONFIG_INET6_TUNNEL is not set | ||
| 331 | CONFIG_NETWORK_SECMARK=y | ||
| 332 | # CONFIG_NETFILTER is not set | ||
| 333 | # CONFIG_IP_DCCP is not set | ||
| 334 | # CONFIG_IP_SCTP is not set | ||
| 335 | # CONFIG_TIPC is not set | ||
| 336 | # CONFIG_ATM is not set | ||
| 337 | # CONFIG_BRIDGE is not set | ||
| 338 | # CONFIG_VLAN_8021Q is not set | ||
| 339 | # CONFIG_DECNET is not set | ||
| 340 | # CONFIG_LLC2 is not set | ||
| 341 | # CONFIG_IPX is not set | ||
| 342 | # CONFIG_ATALK is not set | ||
| 343 | # CONFIG_X25 is not set | ||
| 344 | # CONFIG_LAPB is not set | ||
| 345 | # CONFIG_ECONET is not set | ||
| 346 | # CONFIG_WAN_ROUTER is not set | ||
| 347 | # CONFIG_NET_SCHED is not set | ||
| 348 | CONFIG_NET_SCH_FIFO=y | ||
| 349 | |||
| 350 | # | ||
| 351 | # Network testing | ||
| 352 | # | ||
| 353 | # CONFIG_NET_PKTGEN is not set | ||
| 354 | # CONFIG_HAMRADIO is not set | ||
| 355 | # CONFIG_IRDA is not set | ||
| 356 | # CONFIG_BT is not set | ||
| 357 | # CONFIG_AF_RXRPC is not set | ||
| 358 | |||
| 359 | # | ||
| 360 | # Wireless | ||
| 361 | # | ||
| 362 | CONFIG_CFG80211=m | ||
| 363 | CONFIG_NL80211=y | ||
| 364 | CONFIG_WIRELESS_EXT=y | ||
| 365 | CONFIG_MAC80211=m | ||
| 366 | CONFIG_MAC80211_RCSIMPLE=y | ||
| 367 | # CONFIG_MAC80211_DEBUGFS is not set | ||
| 368 | # CONFIG_MAC80211_DEBUG is not set | ||
| 369 | CONFIG_IEEE80211=m | ||
| 370 | # CONFIG_IEEE80211_DEBUG is not set | ||
| 371 | CONFIG_IEEE80211_CRYPT_WEP=m | ||
| 372 | CONFIG_IEEE80211_CRYPT_CCMP=m | ||
| 373 | CONFIG_IEEE80211_CRYPT_TKIP=m | ||
| 374 | CONFIG_IEEE80211_SOFTMAC=m | ||
| 375 | # CONFIG_IEEE80211_SOFTMAC_DEBUG is not set | ||
| 376 | # CONFIG_RFKILL is not set | ||
| 377 | # CONFIG_NET_9P is not set | ||
| 378 | |||
| 379 | # | ||
| 380 | # Device Drivers | ||
| 381 | # | ||
| 382 | |||
| 383 | # | ||
| 384 | # Generic Driver Options | ||
| 385 | # | ||
| 386 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 387 | CONFIG_STANDALONE=y | ||
| 388 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 389 | # CONFIG_FW_LOADER is not set | ||
| 390 | # CONFIG_DEBUG_DRIVER is not set | ||
| 391 | # CONFIG_DEBUG_DEVRES is not set | ||
| 392 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 393 | # CONFIG_CONNECTOR is not set | ||
| 394 | CONFIG_MTD=y | ||
| 395 | # CONFIG_MTD_DEBUG is not set | ||
| 396 | CONFIG_MTD_CONCAT=y | ||
| 397 | CONFIG_MTD_PARTITIONS=y | ||
| 398 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 399 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 400 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 401 | |||
| 402 | # | ||
| 403 | # User Modules And Translation Layers | ||
| 404 | # | ||
| 405 | CONFIG_MTD_CHAR=y | ||
| 406 | CONFIG_MTD_BLKDEVS=y | ||
| 407 | CONFIG_MTD_BLOCK=y | ||
| 408 | # CONFIG_FTL is not set | ||
| 409 | # CONFIG_NFTL is not set | ||
| 410 | # CONFIG_INFTL is not set | ||
| 411 | # CONFIG_RFD_FTL is not set | ||
| 412 | # CONFIG_SSFDC is not set | ||
| 413 | # CONFIG_MTD_OOPS is not set | ||
| 414 | |||
| 415 | # | ||
| 416 | # RAM/ROM/Flash chip drivers | ||
| 417 | # | ||
| 418 | CONFIG_MTD_CFI=y | ||
| 419 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 420 | CONFIG_MTD_GEN_PROBE=y | ||
| 421 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 422 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 423 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 424 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 425 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 426 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 427 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 428 | CONFIG_MTD_CFI_I1=y | ||
| 429 | CONFIG_MTD_CFI_I2=y | ||
| 430 | # CONFIG_MTD_CFI_I4 is not set | ||
| 431 | # CONFIG_MTD_CFI_I8 is not set | ||
| 432 | # CONFIG_MTD_CFI_INTELEXT is not set | ||
| 433 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
| 434 | # CONFIG_MTD_CFI_STAA is not set | ||
| 435 | CONFIG_MTD_RAM=m | ||
| 436 | # CONFIG_MTD_ROM is not set | ||
| 437 | # CONFIG_MTD_ABSENT is not set | ||
| 438 | |||
| 439 | # | ||
| 440 | # Mapping drivers for chip access | ||
| 441 | # | ||
| 442 | CONFIG_MTD_COMPLEX_MAPPINGS=y | ||
| 443 | # CONFIG_MTD_PHYSMAP is not set | ||
| 444 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 445 | CONFIG_MTD_PLATRAM=m | ||
| 446 | |||
| 447 | # | ||
| 448 | # Self-contained MTD device drivers | ||
| 449 | # | ||
| 450 | CONFIG_MTD_DATAFLASH=y | ||
| 451 | # CONFIG_MTD_M25P80 is not set | ||
| 452 | # CONFIG_MTD_SLRAM is not set | ||
| 453 | # CONFIG_MTD_PHRAM is not set | ||
| 454 | # CONFIG_MTD_MTDRAM is not set | ||
| 455 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 456 | |||
| 457 | # | ||
| 458 | # Disk-On-Chip Device Drivers | ||
| 459 | # | ||
| 460 | # CONFIG_MTD_DOC2000 is not set | ||
| 461 | # CONFIG_MTD_DOC2001 is not set | ||
| 462 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 463 | CONFIG_MTD_NAND=y | ||
| 464 | CONFIG_MTD_NAND_VERIFY_WRITE=y | ||
| 465 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 466 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 467 | CONFIG_MTD_NAND_IDS=y | ||
| 468 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 469 | CONFIG_MTD_NAND_AT91=y | ||
| 470 | # CONFIG_MTD_NAND_AT91_ECC_SOFT is not set | ||
| 471 | CONFIG_MTD_NAND_AT91_ECC_HW=y | ||
| 472 | # CONFIG_MTD_NAND_AT91_ECC_NONE is not set | ||
| 473 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 474 | # CONFIG_MTD_NAND_PLATFORM is not set | ||
| 475 | # CONFIG_MTD_ALAUDA is not set | ||
| 476 | # CONFIG_MTD_ONENAND is not set | ||
| 477 | |||
| 478 | # | ||
| 479 | # UBI - Unsorted block images | ||
| 480 | # | ||
| 481 | # CONFIG_MTD_UBI is not set | ||
| 482 | # CONFIG_PARPORT is not set | ||
| 483 | CONFIG_BLK_DEV=y | ||
| 484 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 485 | CONFIG_BLK_DEV_LOOP=y | ||
| 486 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 487 | # CONFIG_BLK_DEV_NBD is not set | ||
| 488 | # CONFIG_BLK_DEV_UB is not set | ||
| 489 | CONFIG_BLK_DEV_RAM=y | ||
| 490 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 491 | CONFIG_BLK_DEV_RAM_SIZE=4096 | ||
| 492 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | ||
| 493 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 494 | # CONFIG_ATA_OVER_ETH is not set | ||
| 495 | # CONFIG_MISC_DEVICES is not set | ||
| 496 | |||
| 497 | # | ||
| 498 | # SCSI device support | ||
| 499 | # | ||
| 500 | # CONFIG_RAID_ATTRS is not set | ||
| 501 | CONFIG_SCSI=y | ||
| 502 | CONFIG_SCSI_DMA=y | ||
| 503 | CONFIG_SCSI_TGT=y | ||
| 504 | CONFIG_SCSI_NETLINK=y | ||
| 505 | CONFIG_SCSI_PROC_FS=y | ||
| 506 | |||
| 507 | # | ||
| 508 | # SCSI support type (disk, tape, CD-ROM) | ||
| 509 | # | ||
| 510 | CONFIG_BLK_DEV_SD=y | ||
| 511 | # CONFIG_CHR_DEV_ST is not set | ||
| 512 | # CONFIG_CHR_DEV_OSST is not set | ||
| 513 | # CONFIG_BLK_DEV_SR is not set | ||
| 514 | CONFIG_CHR_DEV_SG=y | ||
| 515 | CONFIG_CHR_DEV_SCH=y | ||
| 516 | |||
| 517 | # | ||
| 518 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 519 | # | ||
| 520 | CONFIG_SCSI_MULTI_LUN=y | ||
| 521 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 522 | CONFIG_SCSI_LOGGING=y | ||
| 523 | CONFIG_SCSI_SCAN_ASYNC=y | ||
| 524 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 525 | |||
| 526 | # | ||
| 527 | # SCSI Transports | ||
| 528 | # | ||
| 529 | CONFIG_SCSI_SPI_ATTRS=m | ||
| 530 | CONFIG_SCSI_FC_ATTRS=m | ||
| 531 | # CONFIG_SCSI_FC_TGT_ATTRS is not set | ||
| 532 | CONFIG_SCSI_ISCSI_ATTRS=m | ||
| 533 | CONFIG_SCSI_SAS_ATTRS=m | ||
| 534 | CONFIG_SCSI_SAS_LIBSAS=m | ||
| 535 | # CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set | ||
| 536 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 537 | # CONFIG_SCSI_LOWLEVEL is not set | ||
| 538 | # CONFIG_ATA is not set | ||
| 539 | # CONFIG_MD is not set | ||
| 540 | CONFIG_NETDEVICES=y | ||
| 541 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 542 | # CONFIG_DUMMY is not set | ||
| 543 | # CONFIG_BONDING is not set | ||
| 544 | # CONFIG_MACVLAN is not set | ||
| 545 | # CONFIG_EQUALIZER is not set | ||
| 546 | # CONFIG_TUN is not set | ||
| 547 | # CONFIG_VETH is not set | ||
| 548 | CONFIG_PHYLIB=y | ||
| 549 | |||
| 550 | # | ||
| 551 | # MII PHY device drivers | ||
| 552 | # | ||
| 553 | CONFIG_MARVELL_PHY=m | ||
| 554 | CONFIG_DAVICOM_PHY=m | ||
| 555 | CONFIG_QSEMI_PHY=m | ||
| 556 | CONFIG_LXT_PHY=m | ||
| 557 | CONFIG_CICADA_PHY=m | ||
| 558 | CONFIG_VITESSE_PHY=m | ||
| 559 | CONFIG_SMSC_PHY=m | ||
| 560 | CONFIG_BROADCOM_PHY=m | ||
| 561 | # CONFIG_ICPLUS_PHY is not set | ||
| 562 | CONFIG_FIXED_PHY=m | ||
| 563 | # CONFIG_FIXED_MII_10_FDX is not set | ||
| 564 | # CONFIG_FIXED_MII_100_FDX is not set | ||
| 565 | # CONFIG_FIXED_MII_1000_FDX is not set | ||
| 566 | CONFIG_FIXED_MII_AMNT=1 | ||
| 567 | # CONFIG_MDIO_BITBANG is not set | ||
| 568 | CONFIG_NET_ETHERNET=y | ||
| 569 | CONFIG_MII=y | ||
| 570 | CONFIG_MACB=y | ||
| 571 | # CONFIG_AX88796 is not set | ||
| 572 | # CONFIG_SMC91X is not set | ||
| 573 | # CONFIG_DM9000 is not set | ||
| 574 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 575 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 576 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 577 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 578 | # CONFIG_B44 is not set | ||
| 579 | # CONFIG_NETDEV_1000 is not set | ||
| 580 | # CONFIG_NETDEV_10000 is not set | ||
| 581 | |||
| 582 | # | ||
| 583 | # Wireless LAN | ||
| 584 | # | ||
| 585 | # CONFIG_WLAN_PRE80211 is not set | ||
| 586 | # CONFIG_WLAN_80211 is not set | ||
| 587 | |||
| 588 | # | ||
| 589 | # USB Network Adapters | ||
| 590 | # | ||
| 591 | # CONFIG_USB_CATC is not set | ||
| 592 | # CONFIG_USB_KAWETH is not set | ||
| 593 | # CONFIG_USB_PEGASUS is not set | ||
| 594 | # CONFIG_USB_RTL8150 is not set | ||
| 595 | # CONFIG_USB_USBNET is not set | ||
| 596 | # CONFIG_WAN is not set | ||
| 597 | # CONFIG_PPP is not set | ||
| 598 | # CONFIG_SLIP is not set | ||
| 599 | # CONFIG_SHAPER is not set | ||
| 600 | # CONFIG_NETCONSOLE is not set | ||
| 601 | # CONFIG_NETPOLL is not set | ||
| 602 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 603 | # CONFIG_ISDN is not set | ||
| 604 | |||
| 605 | # | ||
| 606 | # Input device support | ||
| 607 | # | ||
| 608 | CONFIG_INPUT=y | ||
| 609 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 610 | # CONFIG_INPUT_POLLDEV is not set | ||
| 611 | |||
| 612 | # | ||
| 613 | # Userland interfaces | ||
| 614 | # | ||
| 615 | CONFIG_INPUT_MOUSEDEV=y | ||
| 616 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
| 617 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 618 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 619 | # CONFIG_INPUT_JOYDEV is not set | ||
| 620 | CONFIG_INPUT_EVDEV=y | ||
| 621 | # CONFIG_INPUT_EVBUG is not set | ||
| 622 | |||
| 623 | # | ||
| 624 | # Input Device Drivers | ||
| 625 | # | ||
| 626 | CONFIG_INPUT_KEYBOARD=y | ||
| 627 | CONFIG_KEYBOARD_ATKBD=y | ||
| 628 | CONFIG_KEYBOARD_SUNKBD=m | ||
| 629 | CONFIG_KEYBOARD_LKKBD=m | ||
| 630 | CONFIG_KEYBOARD_XTKBD=m | ||
| 631 | CONFIG_KEYBOARD_NEWTON=m | ||
| 632 | CONFIG_KEYBOARD_STOWAWAY=m | ||
| 633 | # CONFIG_KEYBOARD_GPIO is not set | ||
| 634 | CONFIG_INPUT_MOUSE=y | ||
| 635 | CONFIG_MOUSE_PS2=y | ||
| 636 | CONFIG_MOUSE_PS2_ALPS=y | ||
| 637 | CONFIG_MOUSE_PS2_LOGIPS2PP=y | ||
| 638 | CONFIG_MOUSE_PS2_SYNAPTICS=y | ||
| 639 | CONFIG_MOUSE_PS2_LIFEBOOK=y | ||
| 640 | CONFIG_MOUSE_PS2_TRACKPOINT=y | ||
| 641 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | ||
| 642 | CONFIG_MOUSE_SERIAL=m | ||
| 643 | CONFIG_MOUSE_APPLETOUCH=m | ||
| 644 | CONFIG_MOUSE_VSXXXAA=m | ||
| 645 | # CONFIG_MOUSE_GPIO is not set | ||
| 646 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 647 | # CONFIG_INPUT_TABLET is not set | ||
| 648 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 649 | # CONFIG_INPUT_MISC is not set | ||
| 650 | |||
| 651 | # | ||
| 652 | # Hardware I/O ports | ||
| 653 | # | ||
| 654 | CONFIG_SERIO=y | ||
| 655 | # CONFIG_SERIO_SERPORT is not set | ||
| 656 | CONFIG_SERIO_LIBPS2=y | ||
| 657 | # CONFIG_SERIO_RAW is not set | ||
| 658 | # CONFIG_GAMEPORT is not set | ||
| 659 | |||
| 660 | # | ||
| 661 | # Character devices | ||
| 662 | # | ||
| 663 | CONFIG_VT=y | ||
| 664 | CONFIG_VT_CONSOLE=y | ||
| 665 | CONFIG_HW_CONSOLE=y | ||
| 666 | CONFIG_VT_HW_CONSOLE_BINDING=y | ||
| 667 | CONFIG_SERIAL_NONSTANDARD=y | ||
| 668 | # CONFIG_MOXA_SMARTIO is not set | ||
| 669 | # CONFIG_N_HDLC is not set | ||
| 670 | # CONFIG_RISCOM8 is not set | ||
| 671 | # CONFIG_SPECIALIX is not set | ||
| 672 | # CONFIG_RIO is not set | ||
| 673 | # CONFIG_STALDRV is not set | ||
| 674 | |||
| 675 | # | ||
| 676 | # Serial drivers | ||
| 677 | # | ||
| 678 | # CONFIG_SERIAL_8250 is not set | ||
| 679 | |||
| 680 | # | ||
| 681 | # Non-8250 serial port support | ||
| 682 | # | ||
| 683 | CONFIG_SERIAL_ATMEL=y | ||
| 684 | CONFIG_SERIAL_ATMEL_CONSOLE=y | ||
| 685 | # CONFIG_SERIAL_ATMEL_TTYAT is not set | ||
| 686 | CONFIG_SERIAL_CORE=y | ||
| 687 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 688 | CONFIG_UNIX98_PTYS=y | ||
| 689 | # CONFIG_LEGACY_PTYS is not set | ||
| 690 | # CONFIG_IPMI_HANDLER is not set | ||
| 691 | CONFIG_HW_RANDOM=y | ||
| 692 | # CONFIG_NVRAM is not set | ||
| 693 | # CONFIG_R3964 is not set | ||
| 694 | # CONFIG_RAW_DRIVER is not set | ||
| 695 | # CONFIG_TCG_TPM is not set | ||
| 696 | CONFIG_I2C=y | ||
| 697 | CONFIG_I2C_BOARDINFO=y | ||
| 698 | CONFIG_I2C_CHARDEV=y | ||
| 699 | |||
| 700 | # | ||
| 701 | # I2C Algorithms | ||
| 702 | # | ||
| 703 | CONFIG_I2C_ALGOBIT=y | ||
| 704 | # CONFIG_I2C_ALGOPCF is not set | ||
| 705 | # CONFIG_I2C_ALGOPCA is not set | ||
| 706 | |||
| 707 | # | ||
| 708 | # I2C Hardware Bus support | ||
| 709 | # | ||
| 710 | # CONFIG_I2C_GPIO is not set | ||
| 711 | # CONFIG_I2C_OCORES is not set | ||
| 712 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 713 | # CONFIG_I2C_SIMTEC is not set | ||
| 714 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 715 | # CONFIG_I2C_STUB is not set | ||
| 716 | # CONFIG_I2C_TINY_USB is not set | ||
| 717 | # CONFIG_I2C_PCA is not set | ||
| 718 | |||
| 719 | # | ||
| 720 | # Miscellaneous I2C Chip support | ||
| 721 | # | ||
| 722 | # CONFIG_SENSORS_DS1337 is not set | ||
| 723 | # CONFIG_SENSORS_DS1374 is not set | ||
| 724 | # CONFIG_DS1682 is not set | ||
| 725 | # CONFIG_SENSORS_EEPROM is not set | ||
| 726 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 727 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 728 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 729 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 730 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 731 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 732 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 733 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 734 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 735 | |||
| 736 | # | ||
| 737 | # SPI support | ||
| 738 | # | ||
| 739 | CONFIG_SPI=y | ||
| 740 | # CONFIG_SPI_DEBUG is not set | ||
| 741 | CONFIG_SPI_MASTER=y | ||
| 742 | |||
| 743 | # | ||
| 744 | # SPI Master Controller Drivers | ||
| 745 | # | ||
| 746 | CONFIG_SPI_ATMEL=y | ||
| 747 | # CONFIG_SPI_BITBANG is not set | ||
| 748 | |||
| 749 | # | ||
| 750 | # SPI Protocol Masters | ||
| 751 | # | ||
| 752 | # CONFIG_SPI_AT25 is not set | ||
| 753 | # CONFIG_SPI_SPIDEV is not set | ||
| 754 | # CONFIG_SPI_TLE62X0 is not set | ||
| 755 | # CONFIG_W1 is not set | ||
| 756 | # CONFIG_POWER_SUPPLY is not set | ||
| 757 | # CONFIG_HWMON is not set | ||
| 758 | # CONFIG_WATCHDOG is not set | ||
| 759 | |||
| 760 | # | ||
| 761 | # Sonics Silicon Backplane | ||
| 762 | # | ||
| 763 | CONFIG_SSB_POSSIBLE=y | ||
| 764 | # CONFIG_SSB is not set | ||
| 765 | |||
| 766 | # | ||
| 767 | # Multifunction device drivers | ||
| 768 | # | ||
| 769 | # CONFIG_MFD_SM501 is not set | ||
| 770 | |||
| 771 | # | ||
| 772 | # Multimedia devices | ||
| 773 | # | ||
| 774 | # CONFIG_VIDEO_DEV is not set | ||
| 775 | # CONFIG_DVB_CORE is not set | ||
| 776 | # CONFIG_DAB is not set | ||
| 777 | |||
| 778 | # | ||
| 779 | # Graphics support | ||
| 780 | # | ||
| 781 | # CONFIG_VGASTATE is not set | ||
| 782 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 783 | # CONFIG_FB is not set | ||
| 784 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 785 | |||
| 786 | # | ||
| 787 | # Display device support | ||
| 788 | # | ||
| 789 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 790 | |||
| 791 | # | ||
| 792 | # Console display driver support | ||
| 793 | # | ||
| 794 | # CONFIG_VGA_CONSOLE is not set | ||
| 795 | CONFIG_DUMMY_CONSOLE=y | ||
| 796 | |||
| 797 | # | ||
| 798 | # Sound | ||
| 799 | # | ||
| 800 | # CONFIG_SOUND is not set | ||
| 801 | # CONFIG_HID_SUPPORT is not set | ||
| 802 | CONFIG_USB_SUPPORT=y | ||
| 803 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 804 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 805 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 806 | CONFIG_USB=y | ||
| 807 | # CONFIG_USB_DEBUG is not set | ||
| 808 | |||
| 809 | # | ||
| 810 | # Miscellaneous USB options | ||
| 811 | # | ||
| 812 | CONFIG_USB_DEVICEFS=y | ||
| 813 | CONFIG_USB_DEVICE_CLASS=y | ||
| 814 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 815 | # CONFIG_USB_OTG is not set | ||
| 816 | |||
| 817 | # | ||
| 818 | # USB Host Controller Drivers | ||
| 819 | # | ||
| 820 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 821 | CONFIG_USB_OHCI_HCD=y | ||
| 822 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
| 823 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 824 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
| 825 | # CONFIG_USB_SL811_HCD is not set | ||
| 826 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 827 | |||
| 828 | # | ||
| 829 | # USB Device Class drivers | ||
| 830 | # | ||
| 831 | # CONFIG_USB_ACM is not set | ||
| 832 | # CONFIG_USB_PRINTER is not set | ||
| 833 | |||
| 834 | # | ||
| 835 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
| 836 | # | ||
| 837 | |||
| 838 | # | ||
| 839 | # may also be needed; see USB_STORAGE Help for more information | ||
| 840 | # | ||
| 841 | CONFIG_USB_STORAGE=y | ||
| 842 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 843 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 844 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 845 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 846 | # CONFIG_USB_STORAGE_DPCM is not set | ||
| 847 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 848 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 849 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 850 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 851 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 852 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 853 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 854 | CONFIG_USB_LIBUSUAL=y | ||
| 855 | |||
| 856 | # | ||
| 857 | # USB Imaging devices | ||
| 858 | # | ||
| 859 | # CONFIG_USB_MDC800 is not set | ||
| 860 | # CONFIG_USB_MICROTEK is not set | ||
| 861 | # CONFIG_USB_MON is not set | ||
| 862 | |||
| 863 | # | ||
| 864 | # USB port drivers | ||
| 865 | # | ||
| 866 | |||
| 867 | # | ||
| 868 | # USB Serial Converter support | ||
| 869 | # | ||
| 870 | # CONFIG_USB_SERIAL is not set | ||
| 871 | |||
| 872 | # | ||
| 873 | # USB Miscellaneous drivers | ||
| 874 | # | ||
| 875 | # CONFIG_USB_EMI62 is not set | ||
| 876 | # CONFIG_USB_EMI26 is not set | ||
| 877 | # CONFIG_USB_ADUTUX is not set | ||
| 878 | # CONFIG_USB_AUERSWALD is not set | ||
| 879 | # CONFIG_USB_RIO500 is not set | ||
| 880 | # CONFIG_USB_LEGOTOWER is not set | ||
| 881 | # CONFIG_USB_LCD is not set | ||
| 882 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 883 | # CONFIG_USB_LED is not set | ||
| 884 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 885 | # CONFIG_USB_CYTHERM is not set | ||
| 886 | # CONFIG_USB_PHIDGET is not set | ||
| 887 | # CONFIG_USB_IDMOUSE is not set | ||
| 888 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 889 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 890 | # CONFIG_USB_LD is not set | ||
| 891 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 892 | # CONFIG_USB_IOWARRIOR is not set | ||
| 893 | # CONFIG_USB_TEST is not set | ||
| 894 | |||
| 895 | # | ||
| 896 | # USB DSL modem support | ||
| 897 | # | ||
| 898 | |||
| 899 | # | ||
| 900 | # USB Gadget Support | ||
| 901 | # | ||
| 902 | # CONFIG_USB_GADGET is not set | ||
| 903 | # CONFIG_MMC is not set | ||
| 904 | # CONFIG_NEW_LEDS is not set | ||
| 905 | CONFIG_RTC_LIB=y | ||
| 906 | CONFIG_RTC_CLASS=y | ||
| 907 | CONFIG_RTC_HCTOSYS=y | ||
| 908 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 909 | # CONFIG_RTC_DEBUG is not set | ||
| 910 | |||
| 911 | # | ||
| 912 | # RTC interfaces | ||
| 913 | # | ||
| 914 | CONFIG_RTC_INTF_SYSFS=y | ||
| 915 | CONFIG_RTC_INTF_PROC=y | ||
| 916 | CONFIG_RTC_INTF_DEV=y | ||
| 917 | CONFIG_RTC_INTF_DEV_UIE_EMUL=y | ||
| 918 | CONFIG_RTC_DRV_TEST=m | ||
| 919 | |||
| 920 | # | ||
| 921 | # I2C RTC drivers | ||
| 922 | # | ||
| 923 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 924 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 925 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 926 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 927 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 928 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 929 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 930 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 931 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 932 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 933 | |||
| 934 | # | ||
| 935 | # SPI RTC drivers | ||
| 936 | # | ||
| 937 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 938 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 939 | |||
| 940 | # | ||
| 941 | # Platform RTC drivers | ||
| 942 | # | ||
| 943 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 944 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 945 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 946 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 947 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 948 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 949 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 950 | |||
| 951 | # | ||
| 952 | # on-CPU RTC drivers | ||
| 953 | # | ||
| 954 | CONFIG_RTC_DRV_AT91SAM9=y | ||
| 955 | CONFIG_RTC_DRV_AT91SAM9_RTT=0 | ||
| 956 | CONFIG_RTC_DRV_AT91SAM9_GPBR=0 | ||
| 957 | |||
| 958 | # | ||
| 959 | # File systems | ||
| 960 | # | ||
| 961 | CONFIG_EXT2_FS=y | ||
| 962 | CONFIG_EXT2_FS_XATTR=y | ||
| 963 | CONFIG_EXT2_FS_POSIX_ACL=y | ||
| 964 | # CONFIG_EXT2_FS_SECURITY is not set | ||
| 965 | # CONFIG_EXT2_FS_XIP is not set | ||
| 966 | CONFIG_EXT3_FS=y | ||
| 967 | CONFIG_EXT3_FS_XATTR=y | ||
| 968 | # CONFIG_EXT3_FS_POSIX_ACL is not set | ||
| 969 | # CONFIG_EXT3_FS_SECURITY is not set | ||
| 970 | # CONFIG_EXT4DEV_FS is not set | ||
| 971 | CONFIG_JBD=y | ||
| 972 | # CONFIG_JBD_DEBUG is not set | ||
| 973 | CONFIG_FS_MBCACHE=y | ||
| 974 | # CONFIG_REISERFS_FS is not set | ||
| 975 | # CONFIG_JFS_FS is not set | ||
| 976 | CONFIG_FS_POSIX_ACL=y | ||
| 977 | # CONFIG_XFS_FS is not set | ||
| 978 | # CONFIG_GFS2_FS is not set | ||
| 979 | # CONFIG_OCFS2_FS is not set | ||
| 980 | # CONFIG_MINIX_FS is not set | ||
| 981 | # CONFIG_ROMFS_FS is not set | ||
| 982 | CONFIG_INOTIFY=y | ||
| 983 | CONFIG_INOTIFY_USER=y | ||
| 984 | CONFIG_QUOTA=y | ||
| 985 | # CONFIG_QUOTA_NETLINK_INTERFACE is not set | ||
| 986 | CONFIG_PRINT_QUOTA_WARNING=y | ||
| 987 | # CONFIG_QFMT_V1 is not set | ||
| 988 | # CONFIG_QFMT_V2 is not set | ||
| 989 | CONFIG_QUOTACTL=y | ||
| 990 | CONFIG_DNOTIFY=y | ||
| 991 | CONFIG_AUTOFS_FS=y | ||
| 992 | CONFIG_AUTOFS4_FS=y | ||
| 993 | # CONFIG_FUSE_FS is not set | ||
| 994 | |||
| 995 | # | ||
| 996 | # CD-ROM/DVD Filesystems | ||
| 997 | # | ||
| 998 | # CONFIG_ISO9660_FS is not set | ||
| 999 | # CONFIG_UDF_FS is not set | ||
| 1000 | |||
| 1001 | # | ||
| 1002 | # DOS/FAT/NT Filesystems | ||
| 1003 | # | ||
| 1004 | CONFIG_FAT_FS=y | ||
| 1005 | CONFIG_MSDOS_FS=y | ||
| 1006 | CONFIG_VFAT_FS=y | ||
| 1007 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1008 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1009 | # CONFIG_NTFS_FS is not set | ||
| 1010 | |||
| 1011 | # | ||
| 1012 | # Pseudo filesystems | ||
| 1013 | # | ||
| 1014 | CONFIG_PROC_FS=y | ||
| 1015 | CONFIG_PROC_SYSCTL=y | ||
| 1016 | CONFIG_SYSFS=y | ||
| 1017 | CONFIG_TMPFS=y | ||
| 1018 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1019 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1020 | CONFIG_CONFIGFS_FS=y | ||
| 1021 | |||
| 1022 | # | ||
| 1023 | # Miscellaneous filesystems | ||
| 1024 | # | ||
| 1025 | # CONFIG_ADFS_FS is not set | ||
| 1026 | # CONFIG_AFFS_FS is not set | ||
| 1027 | # CONFIG_HFS_FS is not set | ||
| 1028 | # CONFIG_HFSPLUS_FS is not set | ||
| 1029 | # CONFIG_BEFS_FS is not set | ||
| 1030 | # CONFIG_BFS_FS is not set | ||
| 1031 | # CONFIG_EFS_FS is not set | ||
| 1032 | CONFIG_YAFFS_FS=y | ||
| 1033 | CONFIG_YAFFS_YAFFS1=y | ||
| 1034 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1035 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 1036 | CONFIG_YAFFS_YAFFS2=y | ||
| 1037 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 1038 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 1039 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 1040 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 1041 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 1042 | # CONFIG_JFFS2_FS is not set | ||
| 1043 | # CONFIG_CRAMFS is not set | ||
| 1044 | # CONFIG_VXFS_FS is not set | ||
| 1045 | # CONFIG_HPFS_FS is not set | ||
| 1046 | # CONFIG_QNX4FS_FS is not set | ||
| 1047 | # CONFIG_SYSV_FS is not set | ||
| 1048 | # CONFIG_UFS_FS is not set | ||
| 1049 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1050 | CONFIG_NFS_FS=y | ||
| 1051 | CONFIG_NFS_V3=y | ||
| 1052 | # CONFIG_NFS_V3_ACL is not set | ||
| 1053 | # CONFIG_NFS_V4 is not set | ||
| 1054 | # CONFIG_NFS_DIRECTIO is not set | ||
| 1055 | # CONFIG_NFSD is not set | ||
| 1056 | CONFIG_ROOT_NFS=y | ||
| 1057 | CONFIG_LOCKD=y | ||
| 1058 | CONFIG_LOCKD_V4=y | ||
| 1059 | CONFIG_NFS_COMMON=y | ||
| 1060 | CONFIG_SUNRPC=y | ||
| 1061 | # CONFIG_SUNRPC_BIND34 is not set | ||
| 1062 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 1063 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1064 | # CONFIG_SMB_FS is not set | ||
| 1065 | # CONFIG_CIFS is not set | ||
| 1066 | # CONFIG_NCP_FS is not set | ||
| 1067 | # CONFIG_CODA_FS is not set | ||
| 1068 | # CONFIG_AFS_FS is not set | ||
| 1069 | |||
| 1070 | # | ||
| 1071 | # Partition Types | ||
| 1072 | # | ||
| 1073 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 1074 | CONFIG_MSDOS_PARTITION=y | ||
| 1075 | CONFIG_NLS=y | ||
| 1076 | CONFIG_NLS_DEFAULT="cp437" | ||
| 1077 | CONFIG_NLS_CODEPAGE_437=y | ||
| 1078 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1079 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1080 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1081 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1082 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1083 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1084 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1085 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1086 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1087 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1088 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1089 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1090 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1091 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1092 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1093 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1094 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1095 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1096 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1097 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1098 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1099 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1100 | CONFIG_NLS_ASCII=y | ||
| 1101 | CONFIG_NLS_ISO8859_1=y | ||
| 1102 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1103 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1104 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1105 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1106 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1107 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1108 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1109 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1110 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1111 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1112 | # CONFIG_NLS_KOI8_R is not set | ||
| 1113 | # CONFIG_NLS_KOI8_U is not set | ||
| 1114 | CONFIG_NLS_UTF8=y | ||
| 1115 | # CONFIG_DLM is not set | ||
| 1116 | # CONFIG_INSTRUMENTATION is not set | ||
| 1117 | |||
| 1118 | # | ||
| 1119 | # Kernel hacking | ||
| 1120 | # | ||
| 1121 | CONFIG_PRINTK_TIME=y | ||
| 1122 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1123 | # CONFIG_ENABLE_MUST_CHECK is not set | ||
| 1124 | CONFIG_MAGIC_SYSRQ=y | ||
| 1125 | CONFIG_UNUSED_SYMBOLS=y | ||
| 1126 | CONFIG_DEBUG_FS=y | ||
| 1127 | # CONFIG_HEADERS_CHECK is not set | ||
| 1128 | CONFIG_DEBUG_KERNEL=y | ||
| 1129 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1130 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1131 | CONFIG_SCHED_DEBUG=y | ||
| 1132 | # CONFIG_SCHEDSTATS is not set | ||
| 1133 | # CONFIG_TIMER_STATS is not set | ||
| 1134 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 1135 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1136 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1137 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1138 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1139 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1140 | # CONFIG_PROVE_LOCKING is not set | ||
| 1141 | # CONFIG_LOCK_STAT is not set | ||
| 1142 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1143 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1144 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1145 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1146 | # CONFIG_DEBUG_INFO is not set | ||
| 1147 | # CONFIG_DEBUG_VM is not set | ||
| 1148 | # CONFIG_DEBUG_LIST is not set | ||
| 1149 | # CONFIG_DEBUG_SG is not set | ||
| 1150 | CONFIG_FRAME_POINTER=y | ||
| 1151 | # CONFIG_FORCED_INLINING is not set | ||
| 1152 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1153 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1154 | # CONFIG_FAULT_INJECTION is not set | ||
| 1155 | # CONFIG_SAMPLES is not set | ||
| 1156 | # CONFIG_DEBUG_USER is not set | ||
| 1157 | # CONFIG_DEBUG_ERRORS is not set | ||
| 1158 | CONFIG_DEBUG_LL=y | ||
| 1159 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 1160 | |||
| 1161 | # | ||
| 1162 | # Security options | ||
| 1163 | # | ||
| 1164 | # CONFIG_KEYS is not set | ||
| 1165 | # CONFIG_SECURITY is not set | ||
| 1166 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1167 | CONFIG_CRYPTO=y | ||
| 1168 | CONFIG_CRYPTO_ALGAPI=y | ||
| 1169 | CONFIG_CRYPTO_ABLKCIPHER=m | ||
| 1170 | CONFIG_CRYPTO_BLKCIPHER=m | ||
| 1171 | CONFIG_CRYPTO_HASH=y | ||
| 1172 | CONFIG_CRYPTO_MANAGER=y | ||
| 1173 | CONFIG_CRYPTO_HMAC=y | ||
| 1174 | CONFIG_CRYPTO_XCBC=m | ||
| 1175 | CONFIG_CRYPTO_NULL=m | ||
| 1176 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1177 | CONFIG_CRYPTO_MD5=y | ||
| 1178 | CONFIG_CRYPTO_SHA1=y | ||
| 1179 | CONFIG_CRYPTO_SHA256=y | ||
| 1180 | CONFIG_CRYPTO_SHA512=y | ||
| 1181 | CONFIG_CRYPTO_WP512=m | ||
| 1182 | CONFIG_CRYPTO_TGR192=m | ||
| 1183 | CONFIG_CRYPTO_GF128MUL=m | ||
| 1184 | CONFIG_CRYPTO_ECB=m | ||
| 1185 | CONFIG_CRYPTO_CBC=m | ||
| 1186 | CONFIG_CRYPTO_PCBC=m | ||
| 1187 | CONFIG_CRYPTO_LRW=m | ||
| 1188 | # CONFIG_CRYPTO_XTS is not set | ||
| 1189 | CONFIG_CRYPTO_CRYPTD=m | ||
| 1190 | CONFIG_CRYPTO_DES=y | ||
| 1191 | CONFIG_CRYPTO_FCRYPT=m | ||
| 1192 | CONFIG_CRYPTO_BLOWFISH=m | ||
| 1193 | CONFIG_CRYPTO_TWOFISH=m | ||
| 1194 | CONFIG_CRYPTO_TWOFISH_COMMON=m | ||
| 1195 | CONFIG_CRYPTO_SERPENT=m | ||
| 1196 | CONFIG_CRYPTO_AES=m | ||
| 1197 | CONFIG_CRYPTO_CAST5=m | ||
| 1198 | CONFIG_CRYPTO_CAST6=m | ||
| 1199 | CONFIG_CRYPTO_TEA=m | ||
| 1200 | CONFIG_CRYPTO_ARC4=m | ||
| 1201 | CONFIG_CRYPTO_KHAZAD=m | ||
| 1202 | CONFIG_CRYPTO_ANUBIS=m | ||
| 1203 | # CONFIG_CRYPTO_SEED is not set | ||
| 1204 | CONFIG_CRYPTO_DEFLATE=m | ||
| 1205 | CONFIG_CRYPTO_MICHAEL_MIC=m | ||
| 1206 | CONFIG_CRYPTO_CRC32C=m | ||
| 1207 | CONFIG_CRYPTO_CAMELLIA=m | ||
| 1208 | CONFIG_CRYPTO_TEST=m | ||
| 1209 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1210 | # CONFIG_CRYPTO_HW is not set | ||
| 1211 | |||
| 1212 | # | ||
| 1213 | # Library routines | ||
| 1214 | # | ||
| 1215 | CONFIG_BITREVERSE=m | ||
| 1216 | # CONFIG_CRC_CCITT is not set | ||
| 1217 | # CONFIG_CRC16 is not set | ||
| 1218 | # CONFIG_CRC_ITU_T is not set | ||
| 1219 | CONFIG_CRC32=m | ||
| 1220 | # CONFIG_CRC7 is not set | ||
| 1221 | CONFIG_LIBCRC32C=m | ||
| 1222 | CONFIG_AUDIT_GENERIC=y | ||
| 1223 | CONFIG_ZLIB_INFLATE=m | ||
| 1224 | CONFIG_ZLIB_DEFLATE=m | ||
| 1225 | CONFIG_PLIST=y | ||
| 1226 | CONFIG_HAS_IOMEM=y | ||
| 1227 | CONFIG_HAS_IOPORT=y | ||
| 1228 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/csb337_defconfig b/arch/arm/configs/csb337_defconfig index 88e5d28aeec7..67e65e4f0cdc 100644 --- a/arch/arm/configs/csb337_defconfig +++ b/arch/arm/configs/csb337_defconfig | |||
| @@ -1,69 +1,96 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.15 | 3 | # Linux kernel version: 2.6.24-rc7 |
| 4 | # Mon Jan 9 21:51:31 2006 | 4 | # Wed Jan 9 22:19:24 2008 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 7 | CONFIG_MMU=y | 11 | CONFIG_MMU=y |
| 8 | CONFIG_UID16=y | 12 | # CONFIG_NO_IOPORT is not set |
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 18 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 9 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 20 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 22 | CONFIG_GENERIC_HWEIGHT=y | ||
| 10 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 24 | CONFIG_ZONE_DMA=y | ||
| 25 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 26 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 11 | 27 | ||
| 12 | # | 28 | # |
| 13 | # Code maturity level options | 29 | # General setup |
| 14 | # | 30 | # |
| 15 | CONFIG_EXPERIMENTAL=y | 31 | CONFIG_EXPERIMENTAL=y |
| 16 | CONFIG_CLEAN_COMPILE=y | ||
| 17 | CONFIG_BROKEN_ON_SMP=y | 32 | CONFIG_BROKEN_ON_SMP=y |
| 18 | CONFIG_INIT_ENV_ARG_LIMIT=32 | 33 | CONFIG_INIT_ENV_ARG_LIMIT=32 |
| 19 | |||
| 20 | # | ||
| 21 | # General setup | ||
| 22 | # | ||
| 23 | CONFIG_LOCALVERSION="" | 34 | CONFIG_LOCALVERSION="" |
| 24 | CONFIG_LOCALVERSION_AUTO=y | 35 | CONFIG_LOCALVERSION_AUTO=y |
| 25 | # CONFIG_SWAP is not set | 36 | # CONFIG_SWAP is not set |
| 26 | CONFIG_SYSVIPC=y | 37 | CONFIG_SYSVIPC=y |
| 38 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 27 | # CONFIG_POSIX_MQUEUE is not set | 39 | # CONFIG_POSIX_MQUEUE is not set |
| 28 | # CONFIG_BSD_PROCESS_ACCT is not set | 40 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 29 | CONFIG_SYSCTL=y | 41 | # CONFIG_TASKSTATS is not set |
| 42 | # CONFIG_USER_NS is not set | ||
| 43 | # CONFIG_PID_NS is not set | ||
| 30 | # CONFIG_AUDIT is not set | 44 | # CONFIG_AUDIT is not set |
| 31 | CONFIG_HOTPLUG=y | ||
| 32 | CONFIG_KOBJECT_UEVENT=y | ||
| 33 | # CONFIG_IKCONFIG is not set | 45 | # CONFIG_IKCONFIG is not set |
| 46 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 47 | # CONFIG_CGROUPS is not set | ||
| 48 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 49 | CONFIG_FAIR_USER_SCHED=y | ||
| 50 | # CONFIG_FAIR_CGROUP_SCHED is not set | ||
| 51 | CONFIG_SYSFS_DEPRECATED=y | ||
| 52 | # CONFIG_RELAY is not set | ||
| 53 | CONFIG_BLK_DEV_INITRD=y | ||
| 34 | CONFIG_INITRAMFS_SOURCE="" | 54 | CONFIG_INITRAMFS_SOURCE="" |
| 35 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 55 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 56 | CONFIG_SYSCTL=y | ||
| 36 | # CONFIG_EMBEDDED is not set | 57 | # CONFIG_EMBEDDED is not set |
| 58 | CONFIG_UID16=y | ||
| 59 | CONFIG_SYSCTL_SYSCALL=y | ||
| 37 | CONFIG_KALLSYMS=y | 60 | CONFIG_KALLSYMS=y |
| 38 | # CONFIG_KALLSYMS_ALL is not set | 61 | # CONFIG_KALLSYMS_ALL is not set |
| 39 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 62 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 63 | CONFIG_HOTPLUG=y | ||
| 40 | CONFIG_PRINTK=y | 64 | CONFIG_PRINTK=y |
| 41 | CONFIG_BUG=y | 65 | CONFIG_BUG=y |
| 66 | CONFIG_ELF_CORE=y | ||
| 42 | CONFIG_BASE_FULL=y | 67 | CONFIG_BASE_FULL=y |
| 43 | CONFIG_FUTEX=y | 68 | CONFIG_FUTEX=y |
| 69 | CONFIG_ANON_INODES=y | ||
| 44 | CONFIG_EPOLL=y | 70 | CONFIG_EPOLL=y |
| 71 | CONFIG_SIGNALFD=y | ||
| 72 | CONFIG_EVENTFD=y | ||
| 45 | CONFIG_SHMEM=y | 73 | CONFIG_SHMEM=y |
| 46 | CONFIG_CC_ALIGN_FUNCTIONS=0 | 74 | CONFIG_VM_EVENT_COUNTERS=y |
| 47 | CONFIG_CC_ALIGN_LABELS=0 | 75 | CONFIG_SLUB_DEBUG=y |
| 48 | CONFIG_CC_ALIGN_LOOPS=0 | 76 | # CONFIG_SLAB is not set |
| 49 | CONFIG_CC_ALIGN_JUMPS=0 | 77 | CONFIG_SLUB=y |
| 78 | # CONFIG_SLOB is not set | ||
| 79 | CONFIG_SLABINFO=y | ||
| 80 | CONFIG_RT_MUTEXES=y | ||
| 50 | # CONFIG_TINY_SHMEM is not set | 81 | # CONFIG_TINY_SHMEM is not set |
| 51 | CONFIG_BASE_SMALL=0 | 82 | CONFIG_BASE_SMALL=0 |
| 52 | |||
| 53 | # | ||
| 54 | # Loadable module support | ||
| 55 | # | ||
| 56 | CONFIG_MODULES=y | 83 | CONFIG_MODULES=y |
| 57 | CONFIG_MODULE_UNLOAD=y | 84 | CONFIG_MODULE_UNLOAD=y |
| 58 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 85 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 59 | CONFIG_OBSOLETE_MODPARM=y | ||
| 60 | # CONFIG_MODVERSIONS is not set | 86 | # CONFIG_MODVERSIONS is not set |
| 61 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 87 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 62 | CONFIG_KMOD=y | 88 | CONFIG_KMOD=y |
| 63 | 89 | CONFIG_BLOCK=y | |
| 64 | # | 90 | # CONFIG_LBD is not set |
| 65 | # Block layer | 91 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 66 | # | 92 | # CONFIG_LSF is not set |
| 93 | # CONFIG_BLK_DEV_BSG is not set | ||
| 67 | 94 | ||
| 68 | # | 95 | # |
| 69 | # IO Schedulers | 96 | # IO Schedulers |
| @@ -81,62 +108,101 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" | |||
| 81 | # | 108 | # |
| 82 | # System Type | 109 | # System Type |
| 83 | # | 110 | # |
| 111 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 112 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 113 | # CONFIG_ARCH_REALVIEW is not set | ||
| 114 | # CONFIG_ARCH_VERSATILE is not set | ||
| 115 | CONFIG_ARCH_AT91=y | ||
| 84 | # CONFIG_ARCH_CLPS7500 is not set | 116 | # CONFIG_ARCH_CLPS7500 is not set |
| 85 | # CONFIG_ARCH_CLPS711X is not set | 117 | # CONFIG_ARCH_CLPS711X is not set |
| 86 | # CONFIG_ARCH_CO285 is not set | 118 | # CONFIG_ARCH_CO285 is not set |
| 87 | # CONFIG_ARCH_EBSA110 is not set | 119 | # CONFIG_ARCH_EBSA110 is not set |
| 120 | # CONFIG_ARCH_EP93XX is not set | ||
| 88 | # CONFIG_ARCH_FOOTBRIDGE is not set | 121 | # CONFIG_ARCH_FOOTBRIDGE is not set |
| 89 | # CONFIG_ARCH_INTEGRATOR is not set | 122 | # CONFIG_ARCH_NETX is not set |
| 90 | # CONFIG_ARCH_IOP3XX is not set | 123 | # CONFIG_ARCH_H720X is not set |
| 91 | # CONFIG_ARCH_IXP4XX is not set | 124 | # CONFIG_ARCH_IMX is not set |
| 125 | # CONFIG_ARCH_IOP13XX is not set | ||
| 126 | # CONFIG_ARCH_IOP32X is not set | ||
| 127 | # CONFIG_ARCH_IOP33X is not set | ||
| 128 | # CONFIG_ARCH_IXP23XX is not set | ||
| 92 | # CONFIG_ARCH_IXP2000 is not set | 129 | # CONFIG_ARCH_IXP2000 is not set |
| 130 | # CONFIG_ARCH_IXP4XX is not set | ||
| 93 | # CONFIG_ARCH_L7200 is not set | 131 | # CONFIG_ARCH_L7200 is not set |
| 132 | # CONFIG_ARCH_KS8695 is not set | ||
| 133 | # CONFIG_ARCH_NS9XXX is not set | ||
| 134 | # CONFIG_ARCH_MXC is not set | ||
| 135 | # CONFIG_ARCH_PNX4008 is not set | ||
| 94 | # CONFIG_ARCH_PXA is not set | 136 | # CONFIG_ARCH_PXA is not set |
| 95 | # CONFIG_ARCH_RPC is not set | 137 | # CONFIG_ARCH_RPC is not set |
| 96 | # CONFIG_ARCH_SA1100 is not set | 138 | # CONFIG_ARCH_SA1100 is not set |
| 97 | # CONFIG_ARCH_S3C2410 is not set | 139 | # CONFIG_ARCH_S3C2410 is not set |
| 98 | # CONFIG_ARCH_SHARK is not set | 140 | # CONFIG_ARCH_SHARK is not set |
| 99 | # CONFIG_ARCH_LH7A40X is not set | 141 | # CONFIG_ARCH_LH7A40X is not set |
| 142 | # CONFIG_ARCH_DAVINCI is not set | ||
| 100 | # CONFIG_ARCH_OMAP is not set | 143 | # CONFIG_ARCH_OMAP is not set |
| 101 | # CONFIG_ARCH_VERSATILE is not set | ||
| 102 | # CONFIG_ARCH_REALVIEW is not set | ||
| 103 | # CONFIG_ARCH_IMX is not set | ||
| 104 | # CONFIG_ARCH_H720X is not set | ||
| 105 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 106 | CONFIG_ARCH_AT91=y | ||
| 107 | CONFIG_ARCH_AT91RM9200=y | ||
| 108 | 144 | ||
| 109 | # | 145 | # |
| 110 | # AT91RM9200 Implementations | 146 | # Boot options |
| 111 | # | 147 | # |
| 112 | 148 | ||
| 113 | # | 149 | # |
| 150 | # Power management | ||
| 151 | # | ||
| 152 | |||
| 153 | # | ||
| 154 | # Atmel AT91 System-on-Chip | ||
| 155 | # | ||
| 156 | CONFIG_ARCH_AT91RM9200=y | ||
| 157 | # CONFIG_ARCH_AT91SAM9260 is not set | ||
| 158 | # CONFIG_ARCH_AT91SAM9261 is not set | ||
| 159 | # CONFIG_ARCH_AT91SAM9263 is not set | ||
| 160 | # CONFIG_ARCH_AT91SAM9RL is not set | ||
| 161 | # CONFIG_ARCH_AT91X40 is not set | ||
| 162 | CONFIG_AT91_PMC_UNIT=y | ||
| 163 | |||
| 164 | # | ||
| 114 | # AT91RM9200 Board Type | 165 | # AT91RM9200 Board Type |
| 115 | # | 166 | # |
| 167 | # CONFIG_MACH_ONEARM is not set | ||
| 116 | # CONFIG_ARCH_AT91RM9200DK is not set | 168 | # CONFIG_ARCH_AT91RM9200DK is not set |
| 117 | # CONFIG_MACH_AT91RM9200EK is not set | 169 | # CONFIG_MACH_AT91RM9200EK is not set |
| 118 | CONFIG_MACH_CSB337=y | 170 | CONFIG_MACH_CSB337=y |
| 119 | # CONFIG_MACH_CSB637 is not set | 171 | # CONFIG_MACH_CSB637 is not set |
| 120 | # CONFIG_MACH_CARMEVA is not set | 172 | # CONFIG_MACH_CARMEVA is not set |
| 121 | # CONFIG_MACH_KB9200 is not set | ||
| 122 | # CONFIG_MACH_ATEB9200 is not set | 173 | # CONFIG_MACH_ATEB9200 is not set |
| 174 | # CONFIG_MACH_KB9200 is not set | ||
| 175 | # CONFIG_MACH_PICOTUX2XX is not set | ||
| 176 | # CONFIG_MACH_KAFA is not set | ||
| 177 | # CONFIG_MACH_CHUB is not set | ||
| 178 | # CONFIG_MACH_HOMEMATIC is not set | ||
| 179 | # CONFIG_MACH_ECBAT91 is not set | ||
| 180 | # CONFIG_MACH_SWEDATMS is not set | ||
| 181 | |||
| 182 | # | ||
| 183 | # AT91 Board Options | ||
| 184 | # | ||
| 123 | 185 | ||
| 124 | # | 186 | # |
| 125 | # AT91RM9200 Feature Selections | 187 | # AT91 Feature Selections |
| 126 | # | 188 | # |
| 127 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | 189 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y |
| 190 | # CONFIG_ATMEL_TCLIB is not set | ||
| 191 | CONFIG_AT91_TIMER_HZ=128 | ||
| 128 | 192 | ||
| 129 | # | 193 | # |
| 130 | # Processor Type | 194 | # Processor Type |
| 131 | # | 195 | # |
| 132 | CONFIG_CPU_32=y | 196 | CONFIG_CPU_32=y |
| 133 | CONFIG_CPU_ARM920T=y | 197 | CONFIG_CPU_ARM920T=y |
| 134 | CONFIG_CPU_32v4=y | 198 | CONFIG_CPU_32v4T=y |
| 135 | CONFIG_CPU_ABRT_EV4T=y | 199 | CONFIG_CPU_ABRT_EV4T=y |
| 136 | CONFIG_CPU_CACHE_V4WT=y | 200 | CONFIG_CPU_CACHE_V4WT=y |
| 137 | CONFIG_CPU_CACHE_VIVT=y | 201 | CONFIG_CPU_CACHE_VIVT=y |
| 138 | CONFIG_CPU_COPY_V4WB=y | 202 | CONFIG_CPU_COPY_V4WB=y |
| 139 | CONFIG_CPU_TLB_V4WBI=y | 203 | CONFIG_CPU_TLB_V4WBI=y |
| 204 | CONFIG_CPU_CP15=y | ||
| 205 | CONFIG_CPU_CP15_MMU=y | ||
| 140 | 206 | ||
| 141 | # | 207 | # |
| 142 | # Processor Features | 208 | # Processor Features |
| @@ -145,15 +211,13 @@ CONFIG_CPU_TLB_V4WBI=y | |||
| 145 | # CONFIG_CPU_ICACHE_DISABLE is not set | 211 | # CONFIG_CPU_ICACHE_DISABLE is not set |
| 146 | # CONFIG_CPU_DCACHE_DISABLE is not set | 212 | # CONFIG_CPU_DCACHE_DISABLE is not set |
| 147 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | 213 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set |
| 214 | # CONFIG_OUTER_CACHE is not set | ||
| 148 | 215 | ||
| 149 | # | 216 | # |
| 150 | # Bus support | 217 | # Bus support |
| 151 | # | 218 | # |
| 152 | CONFIG_ISA_DMA_API=y | 219 | # CONFIG_PCI_SYSCALL is not set |
| 153 | 220 | # CONFIG_ARCH_SUPPORTS_MSI is not set | |
| 154 | # | ||
| 155 | # PCCARD (PCMCIA/CardBus) support | ||
| 156 | # | ||
| 157 | CONFIG_PCCARD=y | 221 | CONFIG_PCCARD=y |
| 158 | # CONFIG_PCMCIA_DEBUG is not set | 222 | # CONFIG_PCMCIA_DEBUG is not set |
| 159 | CONFIG_PCMCIA=y | 223 | CONFIG_PCMCIA=y |
| @@ -168,8 +232,13 @@ CONFIG_AT91_CF=y | |||
| 168 | # | 232 | # |
| 169 | # Kernel Features | 233 | # Kernel Features |
| 170 | # | 234 | # |
| 235 | # CONFIG_TICK_ONESHOT is not set | ||
| 236 | # CONFIG_NO_HZ is not set | ||
| 237 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 238 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 171 | # CONFIG_PREEMPT is not set | 239 | # CONFIG_PREEMPT is not set |
| 172 | # CONFIG_NO_IDLE_HZ is not set | 240 | CONFIG_HZ=128 |
| 241 | # CONFIG_AEABI is not set | ||
| 173 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | 242 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set |
| 174 | CONFIG_SELECT_MEMORY_MODEL=y | 243 | CONFIG_SELECT_MEMORY_MODEL=y |
| 175 | CONFIG_FLATMEM_MANUAL=y | 244 | CONFIG_FLATMEM_MANUAL=y |
| @@ -178,9 +247,13 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 178 | CONFIG_FLATMEM=y | 247 | CONFIG_FLATMEM=y |
| 179 | CONFIG_FLAT_NODE_MEM_MAP=y | 248 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 180 | # CONFIG_SPARSEMEM_STATIC is not set | 249 | # CONFIG_SPARSEMEM_STATIC is not set |
| 250 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 181 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 251 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 252 | # CONFIG_RESOURCES_64BIT is not set | ||
| 253 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 254 | CONFIG_BOUNCE=y | ||
| 255 | CONFIG_VIRT_TO_BUS=y | ||
| 182 | CONFIG_LEDS=y | 256 | CONFIG_LEDS=y |
| 183 | CONFIG_LEDS_TIMER=y | ||
| 184 | CONFIG_LEDS_CPU=y | 257 | CONFIG_LEDS_CPU=y |
| 185 | CONFIG_ALIGNMENT_TRAP=y | 258 | CONFIG_ALIGNMENT_TRAP=y |
| 186 | 259 | ||
| @@ -191,6 +264,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 | |||
| 191 | CONFIG_ZBOOT_ROM_BSS=0x0 | 264 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 192 | CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw" | 265 | CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw" |
| 193 | # CONFIG_XIP_KERNEL is not set | 266 | # CONFIG_XIP_KERNEL is not set |
| 267 | # CONFIG_KEXEC is not set | ||
| 194 | 268 | ||
| 195 | # | 269 | # |
| 196 | # Floating point emulation | 270 | # Floating point emulation |
| @@ -215,6 +289,7 @@ CONFIG_BINFMT_ELF=y | |||
| 215 | # Power management options | 289 | # Power management options |
| 216 | # | 290 | # |
| 217 | # CONFIG_PM is not set | 291 | # CONFIG_PM is not set |
| 292 | CONFIG_SUSPEND_UP_POSSIBLE=y | ||
| 218 | 293 | ||
| 219 | # | 294 | # |
| 220 | # Networking | 295 | # Networking |
| @@ -227,6 +302,10 @@ CONFIG_NET=y | |||
| 227 | CONFIG_PACKET=y | 302 | CONFIG_PACKET=y |
| 228 | # CONFIG_PACKET_MMAP is not set | 303 | # CONFIG_PACKET_MMAP is not set |
| 229 | CONFIG_UNIX=y | 304 | CONFIG_UNIX=y |
| 305 | CONFIG_XFRM=y | ||
| 306 | # CONFIG_XFRM_USER is not set | ||
| 307 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 308 | # CONFIG_XFRM_MIGRATE is not set | ||
| 230 | # CONFIG_NET_KEY is not set | 309 | # CONFIG_NET_KEY is not set |
| 231 | CONFIG_INET=y | 310 | CONFIG_INET=y |
| 232 | # CONFIG_IP_MULTICAST is not set | 311 | # CONFIG_IP_MULTICAST is not set |
| @@ -243,23 +322,26 @@ CONFIG_IP_PNP_BOOTP=y | |||
| 243 | # CONFIG_INET_AH is not set | 322 | # CONFIG_INET_AH is not set |
| 244 | # CONFIG_INET_ESP is not set | 323 | # CONFIG_INET_ESP is not set |
| 245 | # CONFIG_INET_IPCOMP is not set | 324 | # CONFIG_INET_IPCOMP is not set |
| 325 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 246 | # CONFIG_INET_TUNNEL is not set | 326 | # CONFIG_INET_TUNNEL is not set |
| 327 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 328 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 329 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 330 | # CONFIG_INET_LRO is not set | ||
| 247 | CONFIG_INET_DIAG=y | 331 | CONFIG_INET_DIAG=y |
| 248 | CONFIG_INET_TCP_DIAG=y | 332 | CONFIG_INET_TCP_DIAG=y |
| 249 | # CONFIG_TCP_CONG_ADVANCED is not set | 333 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 250 | CONFIG_TCP_CONG_BIC=y | 334 | CONFIG_TCP_CONG_CUBIC=y |
| 335 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 336 | # CONFIG_TCP_MD5SIG is not set | ||
| 251 | # CONFIG_IPV6 is not set | 337 | # CONFIG_IPV6 is not set |
| 338 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 339 | # CONFIG_INET6_TUNNEL is not set | ||
| 340 | # CONFIG_NETWORK_SECMARK is not set | ||
| 252 | # CONFIG_NETFILTER is not set | 341 | # CONFIG_NETFILTER is not set |
| 253 | |||
| 254 | # | ||
| 255 | # DCCP Configuration (EXPERIMENTAL) | ||
| 256 | # | ||
| 257 | # CONFIG_IP_DCCP is not set | 342 | # CONFIG_IP_DCCP is not set |
| 258 | |||
| 259 | # | ||
| 260 | # SCTP Configuration (EXPERIMENTAL) | ||
| 261 | # | ||
| 262 | # CONFIG_IP_SCTP is not set | 343 | # CONFIG_IP_SCTP is not set |
| 344 | # CONFIG_TIPC is not set | ||
| 263 | # CONFIG_ATM is not set | 345 | # CONFIG_ATM is not set |
| 264 | # CONFIG_BRIDGE is not set | 346 | # CONFIG_BRIDGE is not set |
| 265 | # CONFIG_VLAN_8021Q is not set | 347 | # CONFIG_VLAN_8021Q is not set |
| @@ -269,13 +351,8 @@ CONFIG_TCP_CONG_BIC=y | |||
| 269 | # CONFIG_ATALK is not set | 351 | # CONFIG_ATALK is not set |
| 270 | # CONFIG_X25 is not set | 352 | # CONFIG_X25 is not set |
| 271 | # CONFIG_LAPB is not set | 353 | # CONFIG_LAPB is not set |
| 272 | # CONFIG_NET_DIVERT is not set | ||
| 273 | # CONFIG_ECONET is not set | 354 | # CONFIG_ECONET is not set |
| 274 | # CONFIG_WAN_ROUTER is not set | 355 | # CONFIG_WAN_ROUTER is not set |
| 275 | |||
| 276 | # | ||
| 277 | # QoS and/or fair queueing | ||
| 278 | # | ||
| 279 | # CONFIG_NET_SCHED is not set | 356 | # CONFIG_NET_SCHED is not set |
| 280 | 357 | ||
| 281 | # | 358 | # |
| @@ -285,7 +362,17 @@ CONFIG_TCP_CONG_BIC=y | |||
| 285 | # CONFIG_HAMRADIO is not set | 362 | # CONFIG_HAMRADIO is not set |
| 286 | # CONFIG_IRDA is not set | 363 | # CONFIG_IRDA is not set |
| 287 | # CONFIG_BT is not set | 364 | # CONFIG_BT is not set |
| 365 | # CONFIG_AF_RXRPC is not set | ||
| 366 | |||
| 367 | # | ||
| 368 | # Wireless | ||
| 369 | # | ||
| 370 | # CONFIG_CFG80211 is not set | ||
| 371 | # CONFIG_WIRELESS_EXT is not set | ||
| 372 | # CONFIG_MAC80211 is not set | ||
| 288 | # CONFIG_IEEE80211 is not set | 373 | # CONFIG_IEEE80211 is not set |
| 374 | # CONFIG_RFKILL is not set | ||
| 375 | # CONFIG_NET_9P is not set | ||
| 289 | 376 | ||
| 290 | # | 377 | # |
| 291 | # Device Drivers | 378 | # Device Drivers |
| @@ -294,19 +381,14 @@ CONFIG_TCP_CONG_BIC=y | |||
| 294 | # | 381 | # |
| 295 | # Generic Driver Options | 382 | # Generic Driver Options |
| 296 | # | 383 | # |
| 384 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 297 | CONFIG_STANDALONE=y | 385 | CONFIG_STANDALONE=y |
| 298 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 386 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 299 | CONFIG_FW_LOADER=y | 387 | CONFIG_FW_LOADER=y |
| 300 | # CONFIG_DEBUG_DRIVER is not set | 388 | # CONFIG_DEBUG_DRIVER is not set |
| 301 | 389 | # CONFIG_DEBUG_DEVRES is not set | |
| 302 | # | 390 | # CONFIG_SYS_HYPERVISOR is not set |
| 303 | # Connector - unified userspace <-> kernelspace linker | ||
| 304 | # | ||
| 305 | # CONFIG_CONNECTOR is not set | 391 | # CONFIG_CONNECTOR is not set |
| 306 | |||
| 307 | # | ||
| 308 | # Memory Technology Devices (MTD) | ||
| 309 | # | ||
| 310 | CONFIG_MTD=y | 392 | CONFIG_MTD=y |
| 311 | # CONFIG_MTD_DEBUG is not set | 393 | # CONFIG_MTD_DEBUG is not set |
| 312 | # CONFIG_MTD_CONCAT is not set | 394 | # CONFIG_MTD_CONCAT is not set |
| @@ -319,11 +401,14 @@ CONFIG_MTD_CMDLINE_PARTS=y | |||
| 319 | # User Modules And Translation Layers | 401 | # User Modules And Translation Layers |
| 320 | # | 402 | # |
| 321 | CONFIG_MTD_CHAR=y | 403 | CONFIG_MTD_CHAR=y |
| 404 | CONFIG_MTD_BLKDEVS=y | ||
| 322 | CONFIG_MTD_BLOCK=y | 405 | CONFIG_MTD_BLOCK=y |
| 323 | # CONFIG_FTL is not set | 406 | # CONFIG_FTL is not set |
| 324 | # CONFIG_NFTL is not set | 407 | # CONFIG_NFTL is not set |
| 325 | # CONFIG_INFTL is not set | 408 | # CONFIG_INFTL is not set |
| 326 | # CONFIG_RFD_FTL is not set | 409 | # CONFIG_RFD_FTL is not set |
| 410 | # CONFIG_SSFDC is not set | ||
| 411 | # CONFIG_MTD_OOPS is not set | ||
| 327 | 412 | ||
| 328 | # | 413 | # |
| 329 | # RAM/ROM/Flash chip drivers | 414 | # RAM/ROM/Flash chip drivers |
| @@ -349,15 +434,14 @@ CONFIG_MTD_CFI_UTIL=y | |||
| 349 | # CONFIG_MTD_RAM is not set | 434 | # CONFIG_MTD_RAM is not set |
| 350 | # CONFIG_MTD_ROM is not set | 435 | # CONFIG_MTD_ROM is not set |
| 351 | # CONFIG_MTD_ABSENT is not set | 436 | # CONFIG_MTD_ABSENT is not set |
| 352 | # CONFIG_MTD_XIP is not set | ||
| 353 | 437 | ||
| 354 | # | 438 | # |
| 355 | # Mapping drivers for chip access | 439 | # Mapping drivers for chip access |
| 356 | # | 440 | # |
| 357 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | 441 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set |
| 358 | CONFIG_MTD_PHYSMAP=y | 442 | CONFIG_MTD_PHYSMAP=y |
| 359 | CONFIG_MTD_PHYSMAP_START=0 | 443 | CONFIG_MTD_PHYSMAP_START=0x0 |
| 360 | CONFIG_MTD_PHYSMAP_LEN=0 | 444 | CONFIG_MTD_PHYSMAP_LEN=0x0 |
| 361 | CONFIG_MTD_PHYSMAP_BANKWIDTH=0 | 445 | CONFIG_MTD_PHYSMAP_BANKWIDTH=0 |
| 362 | # CONFIG_MTD_ARM_INTEGRATOR is not set | 446 | # CONFIG_MTD_ARM_INTEGRATOR is not set |
| 363 | # CONFIG_MTD_PLATRAM is not set | 447 | # CONFIG_MTD_PLATRAM is not set |
| @@ -368,7 +452,6 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=0 | |||
| 368 | # CONFIG_MTD_SLRAM is not set | 452 | # CONFIG_MTD_SLRAM is not set |
| 369 | # CONFIG_MTD_PHRAM is not set | 453 | # CONFIG_MTD_PHRAM is not set |
| 370 | # CONFIG_MTD_MTDRAM is not set | 454 | # CONFIG_MTD_MTDRAM is not set |
| 371 | # CONFIG_MTD_BLKMTD is not set | ||
| 372 | # CONFIG_MTD_BLOCK2MTD is not set | 455 | # CONFIG_MTD_BLOCK2MTD is not set |
| 373 | 456 | ||
| 374 | # | 457 | # |
| @@ -378,29 +461,15 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=0 | |||
| 378 | # CONFIG_MTD_DOC2001 is not set | 461 | # CONFIG_MTD_DOC2001 is not set |
| 379 | # CONFIG_MTD_DOC2001PLUS is not set | 462 | # CONFIG_MTD_DOC2001PLUS is not set |
| 380 | # CONFIG_MTD_AT91_DATAFLASH is not set | 463 | # CONFIG_MTD_AT91_DATAFLASH is not set |
| 381 | |||
| 382 | # | ||
| 383 | # NAND Flash Device Drivers | ||
| 384 | # | ||
| 385 | # CONFIG_MTD_NAND is not set | 464 | # CONFIG_MTD_NAND is not set |
| 386 | |||
| 387 | # | ||
| 388 | # OneNAND Flash Device Drivers | ||
| 389 | # | ||
| 390 | # CONFIG_MTD_ONENAND is not set | 465 | # CONFIG_MTD_ONENAND is not set |
| 391 | 466 | ||
| 392 | # | 467 | # |
| 393 | # Parallel port support | 468 | # UBI - Unsorted block images |
| 394 | # | 469 | # |
| 470 | # CONFIG_MTD_UBI is not set | ||
| 395 | # CONFIG_PARPORT is not set | 471 | # CONFIG_PARPORT is not set |
| 396 | 472 | CONFIG_BLK_DEV=y | |
| 397 | # | ||
| 398 | # Plug and Play support | ||
| 399 | # | ||
| 400 | |||
| 401 | # | ||
| 402 | # Block devices | ||
| 403 | # | ||
| 404 | # CONFIG_BLK_DEV_COW_COMMON is not set | 473 | # CONFIG_BLK_DEV_COW_COMMON is not set |
| 405 | CONFIG_BLK_DEV_LOOP=y | 474 | CONFIG_BLK_DEV_LOOP=y |
| 406 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | 475 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set |
| @@ -409,13 +478,12 @@ CONFIG_BLK_DEV_LOOP=y | |||
| 409 | CONFIG_BLK_DEV_RAM=y | 478 | CONFIG_BLK_DEV_RAM=y |
| 410 | CONFIG_BLK_DEV_RAM_COUNT=16 | 479 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 411 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 480 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 412 | CONFIG_BLK_DEV_INITRD=y | 481 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 |
| 413 | # CONFIG_CDROM_PKTCDVD is not set | 482 | # CONFIG_CDROM_PKTCDVD is not set |
| 414 | # CONFIG_ATA_OVER_ETH is not set | 483 | # CONFIG_ATA_OVER_ETH is not set |
| 415 | 484 | CONFIG_MISC_DEVICES=y | |
| 416 | # | 485 | # CONFIG_EEPROM_93CX6 is not set |
| 417 | # ATA/ATAPI/MFM/RLL support | 486 | CONFIG_ATMEL_SSC=y |
| 418 | # | ||
| 419 | # CONFIG_IDE is not set | 487 | # CONFIG_IDE is not set |
| 420 | 488 | ||
| 421 | # | 489 | # |
| @@ -423,6 +491,9 @@ CONFIG_BLK_DEV_INITRD=y | |||
| 423 | # | 491 | # |
| 424 | # CONFIG_RAID_ATTRS is not set | 492 | # CONFIG_RAID_ATTRS is not set |
| 425 | CONFIG_SCSI=y | 493 | CONFIG_SCSI=y |
| 494 | CONFIG_SCSI_DMA=y | ||
| 495 | # CONFIG_SCSI_TGT is not set | ||
| 496 | # CONFIG_SCSI_NETLINK is not set | ||
| 426 | CONFIG_SCSI_PROC_FS=y | 497 | CONFIG_SCSI_PROC_FS=y |
| 427 | 498 | ||
| 428 | # | 499 | # |
| @@ -441,97 +512,61 @@ CONFIG_SCSI_PROC_FS=y | |||
| 441 | # CONFIG_SCSI_MULTI_LUN is not set | 512 | # CONFIG_SCSI_MULTI_LUN is not set |
| 442 | # CONFIG_SCSI_CONSTANTS is not set | 513 | # CONFIG_SCSI_CONSTANTS is not set |
| 443 | # CONFIG_SCSI_LOGGING is not set | 514 | # CONFIG_SCSI_LOGGING is not set |
| 515 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 516 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 444 | 517 | ||
| 445 | # | 518 | # |
| 446 | # SCSI Transport Attributes | 519 | # SCSI Transports |
| 447 | # | 520 | # |
| 448 | # CONFIG_SCSI_SPI_ATTRS is not set | 521 | # CONFIG_SCSI_SPI_ATTRS is not set |
| 449 | # CONFIG_SCSI_FC_ATTRS is not set | 522 | # CONFIG_SCSI_FC_ATTRS is not set |
| 450 | # CONFIG_SCSI_ISCSI_ATTRS is not set | 523 | # CONFIG_SCSI_ISCSI_ATTRS is not set |
| 451 | # CONFIG_SCSI_SAS_ATTRS is not set | 524 | # CONFIG_SCSI_SAS_LIBSAS is not set |
| 452 | 525 | # CONFIG_SCSI_SRP_ATTRS is not set | |
| 453 | # | 526 | CONFIG_SCSI_LOWLEVEL=y |
| 454 | # SCSI low-level drivers | ||
| 455 | # | ||
| 456 | # CONFIG_ISCSI_TCP is not set | 527 | # CONFIG_ISCSI_TCP is not set |
| 457 | # CONFIG_SCSI_SATA is not set | ||
| 458 | # CONFIG_SCSI_DEBUG is not set | 528 | # CONFIG_SCSI_DEBUG is not set |
| 459 | 529 | # CONFIG_SCSI_LOWLEVEL_PCMCIA is not set | |
| 460 | # | 530 | # CONFIG_ATA is not set |
| 461 | # PCMCIA SCSI adapter support | ||
| 462 | # | ||
| 463 | # CONFIG_PCMCIA_AHA152X is not set | ||
| 464 | # CONFIG_PCMCIA_FDOMAIN is not set | ||
| 465 | # CONFIG_PCMCIA_NINJA_SCSI is not set | ||
| 466 | # CONFIG_PCMCIA_QLOGIC is not set | ||
| 467 | # CONFIG_PCMCIA_SYM53C500 is not set | ||
| 468 | |||
| 469 | # | ||
| 470 | # Multi-device support (RAID and LVM) | ||
| 471 | # | ||
| 472 | # CONFIG_MD is not set | 531 | # CONFIG_MD is not set |
| 473 | |||
| 474 | # | ||
| 475 | # Fusion MPT device support | ||
| 476 | # | ||
| 477 | # CONFIG_FUSION is not set | ||
| 478 | |||
| 479 | # | ||
| 480 | # IEEE 1394 (FireWire) support | ||
| 481 | # | ||
| 482 | |||
| 483 | # | ||
| 484 | # I2O device support | ||
| 485 | # | ||
| 486 | |||
| 487 | # | ||
| 488 | # Network device support | ||
| 489 | # | ||
| 490 | CONFIG_NETDEVICES=y | 532 | CONFIG_NETDEVICES=y |
| 533 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 491 | # CONFIG_DUMMY is not set | 534 | # CONFIG_DUMMY is not set |
| 492 | # CONFIG_BONDING is not set | 535 | # CONFIG_BONDING is not set |
| 536 | # CONFIG_MACVLAN is not set | ||
| 493 | # CONFIG_EQUALIZER is not set | 537 | # CONFIG_EQUALIZER is not set |
| 494 | # CONFIG_TUN is not set | 538 | # CONFIG_TUN is not set |
| 495 | 539 | # CONFIG_VETH is not set | |
| 496 | # | ||
| 497 | # PHY device support | ||
| 498 | # | ||
| 499 | # CONFIG_PHYLIB is not set | 540 | # CONFIG_PHYLIB is not set |
| 500 | |||
| 501 | # | ||
| 502 | # Ethernet (10 or 100Mbit) | ||
| 503 | # | ||
| 504 | CONFIG_NET_ETHERNET=y | 541 | CONFIG_NET_ETHERNET=y |
| 505 | CONFIG_MII=y | 542 | CONFIG_MII=y |
| 506 | CONFIG_ARM_AT91_ETHER=y | 543 | CONFIG_ARM_AT91_ETHER=y |
| 544 | # CONFIG_AX88796 is not set | ||
| 507 | # CONFIG_SMC91X is not set | 545 | # CONFIG_SMC91X is not set |
| 508 | # CONFIG_DM9000 is not set | 546 | # CONFIG_DM9000 is not set |
| 547 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 548 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 549 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 550 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 551 | # CONFIG_B44 is not set | ||
| 552 | CONFIG_NETDEV_1000=y | ||
| 553 | CONFIG_NETDEV_10000=y | ||
| 509 | 554 | ||
| 510 | # | 555 | # |
| 511 | # Ethernet (1000 Mbit) | 556 | # Wireless LAN |
| 512 | # | ||
| 513 | |||
| 514 | # | ||
| 515 | # Ethernet (10000 Mbit) | ||
| 516 | # | 557 | # |
| 558 | # CONFIG_WLAN_PRE80211 is not set | ||
| 559 | # CONFIG_WLAN_80211 is not set | ||
| 517 | 560 | ||
| 518 | # | 561 | # |
| 519 | # Token Ring devices | 562 | # USB Network Adapters |
| 520 | # | ||
| 521 | |||
| 522 | # | ||
| 523 | # Wireless LAN (non-hamradio) | ||
| 524 | # | ||
| 525 | # CONFIG_NET_RADIO is not set | ||
| 526 | |||
| 527 | # | ||
| 528 | # PCMCIA network device support | ||
| 529 | # | 563 | # |
| 564 | # CONFIG_USB_CATC is not set | ||
| 565 | # CONFIG_USB_KAWETH is not set | ||
| 566 | # CONFIG_USB_PEGASUS is not set | ||
| 567 | # CONFIG_USB_RTL8150 is not set | ||
| 568 | # CONFIG_USB_USBNET is not set | ||
| 530 | # CONFIG_NET_PCMCIA is not set | 569 | # CONFIG_NET_PCMCIA is not set |
| 531 | |||
| 532 | # | ||
| 533 | # Wan interfaces | ||
| 534 | # | ||
| 535 | # CONFIG_WAN is not set | 570 | # CONFIG_WAN is not set |
| 536 | # CONFIG_PPP is not set | 571 | # CONFIG_PPP is not set |
| 537 | # CONFIG_SLIP is not set | 572 | # CONFIG_SLIP is not set |
| @@ -539,26 +574,23 @@ CONFIG_ARM_AT91_ETHER=y | |||
| 539 | # CONFIG_NETCONSOLE is not set | 574 | # CONFIG_NETCONSOLE is not set |
| 540 | # CONFIG_NETPOLL is not set | 575 | # CONFIG_NETPOLL is not set |
| 541 | # CONFIG_NET_POLL_CONTROLLER is not set | 576 | # CONFIG_NET_POLL_CONTROLLER is not set |
| 542 | |||
| 543 | # | ||
| 544 | # ISDN subsystem | ||
| 545 | # | ||
| 546 | # CONFIG_ISDN is not set | 577 | # CONFIG_ISDN is not set |
| 547 | 578 | ||
| 548 | # | 579 | # |
| 549 | # Input device support | 580 | # Input device support |
| 550 | # | 581 | # |
| 551 | CONFIG_INPUT=y | 582 | CONFIG_INPUT=y |
| 583 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 584 | # CONFIG_INPUT_POLLDEV is not set | ||
| 552 | 585 | ||
| 553 | # | 586 | # |
| 554 | # Userland interfaces | 587 | # Userland interfaces |
| 555 | # | 588 | # |
| 556 | CONFIG_INPUT_MOUSEDEV=y | 589 | CONFIG_INPUT_MOUSEDEV=y |
| 557 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | 590 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 558 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | 591 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 |
| 559 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | 592 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 |
| 560 | # CONFIG_INPUT_JOYDEV is not set | 593 | # CONFIG_INPUT_JOYDEV is not set |
| 561 | # CONFIG_INPUT_TSDEV is not set | ||
| 562 | # CONFIG_INPUT_EVDEV is not set | 594 | # CONFIG_INPUT_EVDEV is not set |
| 563 | # CONFIG_INPUT_EVBUG is not set | 595 | # CONFIG_INPUT_EVBUG is not set |
| 564 | 596 | ||
| @@ -568,6 +600,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | |||
| 568 | # CONFIG_INPUT_KEYBOARD is not set | 600 | # CONFIG_INPUT_KEYBOARD is not set |
| 569 | # CONFIG_INPUT_MOUSE is not set | 601 | # CONFIG_INPUT_MOUSE is not set |
| 570 | # CONFIG_INPUT_JOYSTICK is not set | 602 | # CONFIG_INPUT_JOYSTICK is not set |
| 603 | # CONFIG_INPUT_TABLET is not set | ||
| 571 | # CONFIG_INPUT_TOUCHSCREEN is not set | 604 | # CONFIG_INPUT_TOUCHSCREEN is not set |
| 572 | # CONFIG_INPUT_MISC is not set | 605 | # CONFIG_INPUT_MISC is not set |
| 573 | 606 | ||
| @@ -583,6 +616,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | |||
| 583 | CONFIG_VT=y | 616 | CONFIG_VT=y |
| 584 | CONFIG_VT_CONSOLE=y | 617 | CONFIG_VT_CONSOLE=y |
| 585 | CONFIG_HW_CONSOLE=y | 618 | CONFIG_HW_CONSOLE=y |
| 619 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 586 | # CONFIG_SERIAL_NONSTANDARD is not set | 620 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 587 | 621 | ||
| 588 | # | 622 | # |
| @@ -601,152 +635,114 @@ CONFIG_SERIAL_CORE_CONSOLE=y | |||
| 601 | CONFIG_UNIX98_PTYS=y | 635 | CONFIG_UNIX98_PTYS=y |
| 602 | CONFIG_LEGACY_PTYS=y | 636 | CONFIG_LEGACY_PTYS=y |
| 603 | CONFIG_LEGACY_PTY_COUNT=256 | 637 | CONFIG_LEGACY_PTY_COUNT=256 |
| 604 | |||
| 605 | # | ||
| 606 | # IPMI | ||
| 607 | # | ||
| 608 | # CONFIG_IPMI_HANDLER is not set | 638 | # CONFIG_IPMI_HANDLER is not set |
| 609 | |||
| 610 | # | ||
| 611 | # Watchdog Cards | ||
| 612 | # | ||
| 613 | CONFIG_WATCHDOG=y | ||
| 614 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 615 | |||
| 616 | # | ||
| 617 | # Watchdog Device Drivers | ||
| 618 | # | ||
| 619 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 620 | CONFIG_AT91RM9200_WATCHDOG=y | ||
| 621 | |||
| 622 | # | ||
| 623 | # USB-based Watchdog Cards | ||
| 624 | # | ||
| 625 | # CONFIG_USBPCWATCHDOG is not set | ||
| 626 | # CONFIG_HW_RANDOM is not set | 639 | # CONFIG_HW_RANDOM is not set |
| 627 | # CONFIG_NVRAM is not set | 640 | # CONFIG_NVRAM is not set |
| 628 | # CONFIG_DTLK is not set | ||
| 629 | # CONFIG_R3964 is not set | 641 | # CONFIG_R3964 is not set |
| 630 | 642 | ||
| 631 | # | 643 | # |
| 632 | # Ftape, the floppy tape device driver | ||
| 633 | # | ||
| 634 | |||
| 635 | # | ||
| 636 | # PCMCIA character devices | 644 | # PCMCIA character devices |
| 637 | # | 645 | # |
| 638 | # CONFIG_SYNCLINK_CS is not set | 646 | # CONFIG_SYNCLINK_CS is not set |
| 639 | # CONFIG_CARDMAN_4000 is not set | 647 | # CONFIG_CARDMAN_4000 is not set |
| 640 | # CONFIG_CARDMAN_4040 is not set | 648 | # CONFIG_CARDMAN_4040 is not set |
| 641 | # CONFIG_RAW_DRIVER is not set | 649 | # CONFIG_RAW_DRIVER is not set |
| 642 | |||
| 643 | # | ||
| 644 | # TPM devices | ||
| 645 | # | ||
| 646 | # CONFIG_TCG_TPM is not set | 650 | # CONFIG_TCG_TPM is not set |
| 647 | # CONFIG_TELCLOCK is not set | ||
| 648 | CONFIG_AT91_SPI=y | 651 | CONFIG_AT91_SPI=y |
| 649 | CONFIG_AT91_SPIDEV=y | 652 | CONFIG_AT91_SPIDEV=y |
| 650 | |||
| 651 | # | ||
| 652 | # I2C support | ||
| 653 | # | ||
| 654 | CONFIG_I2C=y | 653 | CONFIG_I2C=y |
| 654 | CONFIG_I2C_BOARDINFO=y | ||
| 655 | CONFIG_I2C_CHARDEV=y | 655 | CONFIG_I2C_CHARDEV=y |
| 656 | 656 | ||
| 657 | # | 657 | # |
| 658 | # I2C Algorithms | 658 | # I2C Algorithms |
| 659 | # | 659 | # |
| 660 | # CONFIG_I2C_ALGOBIT is not set | 660 | CONFIG_I2C_ALGOBIT=y |
| 661 | # CONFIG_I2C_ALGOPCF is not set | 661 | # CONFIG_I2C_ALGOPCF is not set |
| 662 | # CONFIG_I2C_ALGOPCA is not set | 662 | # CONFIG_I2C_ALGOPCA is not set |
| 663 | 663 | ||
| 664 | # | 664 | # |
| 665 | # I2C Hardware Bus support | 665 | # I2C Hardware Bus support |
| 666 | # | 666 | # |
| 667 | CONFIG_I2C_AT91=y | 667 | CONFIG_I2C_GPIO=y |
| 668 | # CONFIG_I2C_OCORES is not set | ||
| 668 | # CONFIG_I2C_PARPORT_LIGHT is not set | 669 | # CONFIG_I2C_PARPORT_LIGHT is not set |
| 670 | # CONFIG_I2C_SIMTEC is not set | ||
| 671 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 669 | # CONFIG_I2C_STUB is not set | 672 | # CONFIG_I2C_STUB is not set |
| 670 | # CONFIG_I2C_PCA_ISA is not set | 673 | # CONFIG_I2C_TINY_USB is not set |
| 674 | # CONFIG_I2C_PCA is not set | ||
| 671 | 675 | ||
| 672 | # | 676 | # |
| 673 | # Miscellaneous I2C Chip support | 677 | # Miscellaneous I2C Chip support |
| 674 | # | 678 | # |
| 675 | # CONFIG_SENSORS_DS1337 is not set | 679 | # CONFIG_SENSORS_DS1337 is not set |
| 676 | # CONFIG_SENSORS_DS1374 is not set | 680 | # CONFIG_SENSORS_DS1374 is not set |
| 681 | # CONFIG_DS1682 is not set | ||
| 677 | # CONFIG_SENSORS_EEPROM is not set | 682 | # CONFIG_SENSORS_EEPROM is not set |
| 678 | # CONFIG_SENSORS_PCF8574 is not set | 683 | # CONFIG_SENSORS_PCF8574 is not set |
| 679 | # CONFIG_SENSORS_PCA9539 is not set | 684 | # CONFIG_SENSORS_PCA9539 is not set |
| 680 | # CONFIG_SENSORS_PCF8591 is not set | 685 | # CONFIG_SENSORS_PCF8591 is not set |
| 681 | # CONFIG_SENSORS_RTC8564 is not set | ||
| 682 | # CONFIG_SENSORS_MAX6875 is not set | 686 | # CONFIG_SENSORS_MAX6875 is not set |
| 683 | # CONFIG_RTC_X1205_I2C is not set | 687 | # CONFIG_SENSORS_TSL2550 is not set |
| 684 | # CONFIG_I2C_DEBUG_CORE is not set | 688 | # CONFIG_I2C_DEBUG_CORE is not set |
| 685 | # CONFIG_I2C_DEBUG_ALGO is not set | 689 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 686 | # CONFIG_I2C_DEBUG_BUS is not set | 690 | # CONFIG_I2C_DEBUG_BUS is not set |
| 687 | # CONFIG_I2C_DEBUG_CHIP is not set | 691 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 688 | 692 | ||
| 689 | # | 693 | # |
| 690 | # Hardware Monitoring support | 694 | # SPI support |
| 691 | # | ||
| 692 | CONFIG_HWMON=y | ||
| 693 | # CONFIG_HWMON_VID is not set | ||
| 694 | # CONFIG_SENSORS_ADM1021 is not set | ||
| 695 | # CONFIG_SENSORS_ADM1025 is not set | ||
| 696 | # CONFIG_SENSORS_ADM1026 is not set | ||
| 697 | # CONFIG_SENSORS_ADM1031 is not set | ||
| 698 | # CONFIG_SENSORS_ADM9240 is not set | ||
| 699 | # CONFIG_SENSORS_ASB100 is not set | ||
| 700 | # CONFIG_SENSORS_ATXP1 is not set | ||
| 701 | # CONFIG_SENSORS_DS1621 is not set | ||
| 702 | # CONFIG_SENSORS_FSCHER is not set | ||
| 703 | # CONFIG_SENSORS_FSCPOS is not set | ||
| 704 | # CONFIG_SENSORS_GL518SM is not set | ||
| 705 | # CONFIG_SENSORS_GL520SM is not set | ||
| 706 | # CONFIG_SENSORS_IT87 is not set | ||
| 707 | # CONFIG_SENSORS_LM63 is not set | ||
| 708 | # CONFIG_SENSORS_LM75 is not set | ||
| 709 | # CONFIG_SENSORS_LM77 is not set | ||
| 710 | # CONFIG_SENSORS_LM78 is not set | ||
| 711 | # CONFIG_SENSORS_LM80 is not set | ||
| 712 | # CONFIG_SENSORS_LM83 is not set | ||
| 713 | # CONFIG_SENSORS_LM85 is not set | ||
| 714 | # CONFIG_SENSORS_LM87 is not set | ||
| 715 | # CONFIG_SENSORS_LM90 is not set | ||
| 716 | # CONFIG_SENSORS_LM92 is not set | ||
| 717 | # CONFIG_SENSORS_MAX1619 is not set | ||
| 718 | # CONFIG_SENSORS_PC87360 is not set | ||
| 719 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
| 720 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
| 721 | # CONFIG_SENSORS_W83781D is not set | ||
| 722 | # CONFIG_SENSORS_W83792D is not set | ||
| 723 | # CONFIG_SENSORS_W83L785TS is not set | ||
| 724 | # CONFIG_SENSORS_W83627HF is not set | ||
| 725 | # CONFIG_SENSORS_W83627EHF is not set | ||
| 726 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
| 727 | |||
| 728 | # | ||
| 729 | # Misc devices | ||
| 730 | # | ||
| 731 | |||
| 732 | # | ||
| 733 | # Multimedia Capabilities Port drivers | ||
| 734 | # | 695 | # |
| 696 | # CONFIG_SPI is not set | ||
| 697 | # CONFIG_SPI_MASTER is not set | ||
| 698 | # CONFIG_W1 is not set | ||
| 699 | # CONFIG_POWER_SUPPLY is not set | ||
| 700 | # CONFIG_HWMON is not set | ||
| 701 | CONFIG_WATCHDOG=y | ||
| 702 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 735 | 703 | ||
| 736 | # | 704 | # |
| 737 | # Multimedia devices | 705 | # Watchdog Device Drivers |
| 738 | # | 706 | # |
| 739 | # CONFIG_VIDEO_DEV is not set | 707 | # CONFIG_SOFT_WATCHDOG is not set |
| 708 | CONFIG_AT91RM9200_WATCHDOG=y | ||
| 709 | |||
| 710 | # | ||
| 711 | # USB-based Watchdog Cards | ||
| 712 | # | ||
| 713 | # CONFIG_USBPCWATCHDOG is not set | ||
| 714 | |||
| 715 | # | ||
| 716 | # Sonics Silicon Backplane | ||
| 717 | # | ||
| 718 | CONFIG_SSB_POSSIBLE=y | ||
| 719 | # CONFIG_SSB is not set | ||
| 740 | 720 | ||
| 741 | # | 721 | # |
| 742 | # Digital Video Broadcasting Devices | 722 | # Multifunction device drivers |
| 743 | # | 723 | # |
| 744 | # CONFIG_DVB is not set | 724 | # CONFIG_MFD_SM501 is not set |
| 725 | |||
| 726 | # | ||
| 727 | # Multimedia devices | ||
| 728 | # | ||
| 729 | # CONFIG_VIDEO_DEV is not set | ||
| 730 | # CONFIG_DVB_CORE is not set | ||
| 731 | CONFIG_DAB=y | ||
| 732 | # CONFIG_USB_DABUSB is not set | ||
| 745 | 733 | ||
| 746 | # | 734 | # |
| 747 | # Graphics support | 735 | # Graphics support |
| 748 | # | 736 | # |
| 737 | # CONFIG_VGASTATE is not set | ||
| 738 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 749 | # CONFIG_FB is not set | 739 | # CONFIG_FB is not set |
| 740 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 741 | |||
| 742 | # | ||
| 743 | # Display device support | ||
| 744 | # | ||
| 745 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 750 | 746 | ||
| 751 | # | 747 | # |
| 752 | # Console display driver support | 748 | # Console display driver support |
| @@ -758,12 +754,25 @@ CONFIG_DUMMY_CONSOLE=y | |||
| 758 | # Sound | 754 | # Sound |
| 759 | # | 755 | # |
| 760 | # CONFIG_SOUND is not set | 756 | # CONFIG_SOUND is not set |
| 757 | CONFIG_HID_SUPPORT=y | ||
| 758 | CONFIG_HID=y | ||
| 759 | CONFIG_HID_DEBUG=y | ||
| 760 | # CONFIG_HIDRAW is not set | ||
| 761 | |||
| 762 | # | ||
| 763 | # USB Input Devices | ||
| 764 | # | ||
| 765 | # CONFIG_USB_HID is not set | ||
| 761 | 766 | ||
| 762 | # | 767 | # |
| 763 | # USB support | 768 | # USB HID Boot Protocol drivers |
| 764 | # | 769 | # |
| 770 | # CONFIG_USB_KBD is not set | ||
| 771 | # CONFIG_USB_MOUSE is not set | ||
| 772 | CONFIG_USB_SUPPORT=y | ||
| 765 | CONFIG_USB_ARCH_HAS_HCD=y | 773 | CONFIG_USB_ARCH_HAS_HCD=y |
| 766 | CONFIG_USB_ARCH_HAS_OHCI=y | 774 | CONFIG_USB_ARCH_HAS_OHCI=y |
| 775 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 767 | CONFIG_USB=y | 776 | CONFIG_USB=y |
| 768 | CONFIG_USB_DEBUG=y | 777 | CONFIG_USB_DEBUG=y |
| 769 | 778 | ||
| @@ -771,7 +780,7 @@ CONFIG_USB_DEBUG=y | |||
| 771 | # Miscellaneous USB options | 780 | # Miscellaneous USB options |
| 772 | # | 781 | # |
| 773 | CONFIG_USB_DEVICEFS=y | 782 | CONFIG_USB_DEVICEFS=y |
| 774 | # CONFIG_USB_BANDWIDTH is not set | 783 | CONFIG_USB_DEVICE_CLASS=y |
| 775 | # CONFIG_USB_DYNAMIC_MINORS is not set | 784 | # CONFIG_USB_DYNAMIC_MINORS is not set |
| 776 | # CONFIG_USB_OTG is not set | 785 | # CONFIG_USB_OTG is not set |
| 777 | 786 | ||
| @@ -780,9 +789,11 @@ CONFIG_USB_DEVICEFS=y | |||
| 780 | # | 789 | # |
| 781 | # CONFIG_USB_ISP116X_HCD is not set | 790 | # CONFIG_USB_ISP116X_HCD is not set |
| 782 | CONFIG_USB_OHCI_HCD=y | 791 | CONFIG_USB_OHCI_HCD=y |
| 783 | # CONFIG_USB_OHCI_BIG_ENDIAN is not set | 792 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set |
| 793 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 784 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | 794 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y |
| 785 | # CONFIG_USB_SL811_HCD is not set | 795 | # CONFIG_USB_SL811_HCD is not set |
| 796 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 786 | 797 | ||
| 787 | # | 798 | # |
| 788 | # USB Device Class drivers | 799 | # USB Device Class drivers |
| @@ -801,59 +812,21 @@ CONFIG_USB_STORAGE=y | |||
| 801 | # CONFIG_USB_STORAGE_DEBUG is not set | 812 | # CONFIG_USB_STORAGE_DEBUG is not set |
| 802 | # CONFIG_USB_STORAGE_DATAFAB is not set | 813 | # CONFIG_USB_STORAGE_DATAFAB is not set |
| 803 | # CONFIG_USB_STORAGE_FREECOM is not set | 814 | # CONFIG_USB_STORAGE_FREECOM is not set |
| 815 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 804 | # CONFIG_USB_STORAGE_DPCM is not set | 816 | # CONFIG_USB_STORAGE_DPCM is not set |
| 805 | # CONFIG_USB_STORAGE_USBAT is not set | 817 | # CONFIG_USB_STORAGE_USBAT is not set |
| 806 | # CONFIG_USB_STORAGE_SDDR09 is not set | 818 | # CONFIG_USB_STORAGE_SDDR09 is not set |
| 807 | # CONFIG_USB_STORAGE_SDDR55 is not set | 819 | # CONFIG_USB_STORAGE_SDDR55 is not set |
| 808 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | 820 | # CONFIG_USB_STORAGE_JUMPSHOT is not set |
| 809 | 821 | # CONFIG_USB_STORAGE_ALAUDA is not set | |
| 810 | # | 822 | # CONFIG_USB_STORAGE_KARMA is not set |
| 811 | # USB Input Devices | 823 | # CONFIG_USB_LIBUSUAL is not set |
| 812 | # | ||
| 813 | # CONFIG_USB_HID is not set | ||
| 814 | |||
| 815 | # | ||
| 816 | # USB HID Boot Protocol drivers | ||
| 817 | # | ||
| 818 | # CONFIG_USB_KBD is not set | ||
| 819 | # CONFIG_USB_MOUSE is not set | ||
| 820 | # CONFIG_USB_AIPTEK is not set | ||
| 821 | # CONFIG_USB_WACOM is not set | ||
| 822 | # CONFIG_USB_ACECAD is not set | ||
| 823 | # CONFIG_USB_KBTAB is not set | ||
| 824 | # CONFIG_USB_POWERMATE is not set | ||
| 825 | # CONFIG_USB_MTOUCH is not set | ||
| 826 | # CONFIG_USB_ITMTOUCH is not set | ||
| 827 | # CONFIG_USB_EGALAX is not set | ||
| 828 | # CONFIG_USB_YEALINK is not set | ||
| 829 | # CONFIG_USB_XPAD is not set | ||
| 830 | # CONFIG_USB_ATI_REMOTE is not set | ||
| 831 | # CONFIG_USB_KEYSPAN_REMOTE is not set | ||
| 832 | # CONFIG_USB_APPLETOUCH is not set | ||
| 833 | 824 | ||
| 834 | # | 825 | # |
| 835 | # USB Imaging devices | 826 | # USB Imaging devices |
| 836 | # | 827 | # |
| 837 | # CONFIG_USB_MDC800 is not set | 828 | # CONFIG_USB_MDC800 is not set |
| 838 | # CONFIG_USB_MICROTEK is not set | 829 | # CONFIG_USB_MICROTEK is not set |
| 839 | |||
| 840 | # | ||
| 841 | # USB Multimedia devices | ||
| 842 | # | ||
| 843 | # CONFIG_USB_DABUSB is not set | ||
| 844 | |||
| 845 | # | ||
| 846 | # Video4Linux support is needed for USB Multimedia device support | ||
| 847 | # | ||
| 848 | |||
| 849 | # | ||
| 850 | # USB Network Adapters | ||
| 851 | # | ||
| 852 | # CONFIG_USB_CATC is not set | ||
| 853 | # CONFIG_USB_KAWETH is not set | ||
| 854 | # CONFIG_USB_PEGASUS is not set | ||
| 855 | # CONFIG_USB_RTL8150 is not set | ||
| 856 | # CONFIG_USB_USBNET is not set | ||
| 857 | CONFIG_USB_MON=y | 830 | CONFIG_USB_MON=y |
| 858 | 831 | ||
| 859 | # | 832 | # |
| @@ -866,15 +839,18 @@ CONFIG_USB_MON=y | |||
| 866 | CONFIG_USB_SERIAL=y | 839 | CONFIG_USB_SERIAL=y |
| 867 | CONFIG_USB_SERIAL_CONSOLE=y | 840 | CONFIG_USB_SERIAL_CONSOLE=y |
| 868 | CONFIG_USB_SERIAL_GENERIC=y | 841 | CONFIG_USB_SERIAL_GENERIC=y |
| 842 | # CONFIG_USB_SERIAL_AIRCABLE is not set | ||
| 869 | # CONFIG_USB_SERIAL_AIRPRIME is not set | 843 | # CONFIG_USB_SERIAL_AIRPRIME is not set |
| 870 | # CONFIG_USB_SERIAL_ANYDATA is not set | 844 | # CONFIG_USB_SERIAL_ARK3116 is not set |
| 871 | # CONFIG_USB_SERIAL_BELKIN is not set | 845 | # CONFIG_USB_SERIAL_BELKIN is not set |
| 846 | # CONFIG_USB_SERIAL_CH341 is not set | ||
| 872 | # CONFIG_USB_SERIAL_WHITEHEAT is not set | 847 | # CONFIG_USB_SERIAL_WHITEHEAT is not set |
| 873 | # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set | 848 | # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set |
| 874 | # CONFIG_USB_SERIAL_CP2101 is not set | 849 | # CONFIG_USB_SERIAL_CP2101 is not set |
| 875 | # CONFIG_USB_SERIAL_CYPRESS_M8 is not set | 850 | # CONFIG_USB_SERIAL_CYPRESS_M8 is not set |
| 876 | # CONFIG_USB_SERIAL_EMPEG is not set | 851 | # CONFIG_USB_SERIAL_EMPEG is not set |
| 877 | CONFIG_USB_SERIAL_FTDI_SIO=y | 852 | CONFIG_USB_SERIAL_FTDI_SIO=y |
| 853 | # CONFIG_USB_SERIAL_FUNSOFT is not set | ||
| 878 | # CONFIG_USB_SERIAL_VISOR is not set | 854 | # CONFIG_USB_SERIAL_VISOR is not set |
| 879 | # CONFIG_USB_SERIAL_IPAQ is not set | 855 | # CONFIG_USB_SERIAL_IPAQ is not set |
| 880 | # CONFIG_USB_SERIAL_IR is not set | 856 | # CONFIG_USB_SERIAL_IR is not set |
| @@ -899,14 +875,20 @@ CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y | |||
| 899 | # CONFIG_USB_SERIAL_KLSI is not set | 875 | # CONFIG_USB_SERIAL_KLSI is not set |
| 900 | # CONFIG_USB_SERIAL_KOBIL_SCT is not set | 876 | # CONFIG_USB_SERIAL_KOBIL_SCT is not set |
| 901 | CONFIG_USB_SERIAL_MCT_U232=y | 877 | CONFIG_USB_SERIAL_MCT_U232=y |
| 878 | # CONFIG_USB_SERIAL_MOS7720 is not set | ||
| 879 | # CONFIG_USB_SERIAL_MOS7840 is not set | ||
| 880 | # CONFIG_USB_SERIAL_NAVMAN is not set | ||
| 902 | # CONFIG_USB_SERIAL_PL2303 is not set | 881 | # CONFIG_USB_SERIAL_PL2303 is not set |
| 882 | # CONFIG_USB_SERIAL_OTI6858 is not set | ||
| 903 | # CONFIG_USB_SERIAL_HP4X is not set | 883 | # CONFIG_USB_SERIAL_HP4X is not set |
| 904 | # CONFIG_USB_SERIAL_SAFE is not set | 884 | # CONFIG_USB_SERIAL_SAFE is not set |
| 885 | # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set | ||
| 905 | # CONFIG_USB_SERIAL_TI is not set | 886 | # CONFIG_USB_SERIAL_TI is not set |
| 906 | # CONFIG_USB_SERIAL_CYBERJACK is not set | 887 | # CONFIG_USB_SERIAL_CYBERJACK is not set |
| 907 | # CONFIG_USB_SERIAL_XIRCOM is not set | 888 | # CONFIG_USB_SERIAL_XIRCOM is not set |
| 908 | # CONFIG_USB_SERIAL_OPTION is not set | 889 | # CONFIG_USB_SERIAL_OPTION is not set |
| 909 | # CONFIG_USB_SERIAL_OMNINET is not set | 890 | # CONFIG_USB_SERIAL_OMNINET is not set |
| 891 | # CONFIG_USB_SERIAL_DEBUG is not set | ||
| 910 | CONFIG_USB_EZUSB=y | 892 | CONFIG_USB_EZUSB=y |
| 911 | 893 | ||
| 912 | # | 894 | # |
| @@ -914,16 +896,22 @@ CONFIG_USB_EZUSB=y | |||
| 914 | # | 896 | # |
| 915 | # CONFIG_USB_EMI62 is not set | 897 | # CONFIG_USB_EMI62 is not set |
| 916 | # CONFIG_USB_EMI26 is not set | 898 | # CONFIG_USB_EMI26 is not set |
| 899 | # CONFIG_USB_ADUTUX is not set | ||
| 917 | # CONFIG_USB_AUERSWALD is not set | 900 | # CONFIG_USB_AUERSWALD is not set |
| 918 | # CONFIG_USB_RIO500 is not set | 901 | # CONFIG_USB_RIO500 is not set |
| 919 | # CONFIG_USB_LEGOTOWER is not set | 902 | # CONFIG_USB_LEGOTOWER is not set |
| 920 | # CONFIG_USB_LCD is not set | 903 | # CONFIG_USB_LCD is not set |
| 904 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 921 | # CONFIG_USB_LED is not set | 905 | # CONFIG_USB_LED is not set |
| 906 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 922 | # CONFIG_USB_CYTHERM is not set | 907 | # CONFIG_USB_CYTHERM is not set |
| 923 | # CONFIG_USB_PHIDGETKIT is not set | 908 | # CONFIG_USB_PHIDGET is not set |
| 924 | # CONFIG_USB_PHIDGETSERVO is not set | ||
| 925 | # CONFIG_USB_IDMOUSE is not set | 909 | # CONFIG_USB_IDMOUSE is not set |
| 910 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 911 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 926 | # CONFIG_USB_LD is not set | 912 | # CONFIG_USB_LD is not set |
| 913 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 914 | # CONFIG_USB_IOWARRIOR is not set | ||
| 927 | # CONFIG_USB_TEST is not set | 915 | # CONFIG_USB_TEST is not set |
| 928 | 916 | ||
| 929 | # | 917 | # |
| @@ -934,13 +922,19 @@ CONFIG_USB_EZUSB=y | |||
| 934 | # USB Gadget Support | 922 | # USB Gadget Support |
| 935 | # | 923 | # |
| 936 | CONFIG_USB_GADGET=y | 924 | CONFIG_USB_GADGET=y |
| 925 | # CONFIG_USB_GADGET_DEBUG is not set | ||
| 937 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | 926 | # CONFIG_USB_GADGET_DEBUG_FILES is not set |
| 938 | CONFIG_USB_GADGET_SELECTED=y | 927 | CONFIG_USB_GADGET_SELECTED=y |
| 928 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 929 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 930 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 939 | # CONFIG_USB_GADGET_NET2280 is not set | 931 | # CONFIG_USB_GADGET_NET2280 is not set |
| 940 | # CONFIG_USB_GADGET_PXA2XX is not set | 932 | # CONFIG_USB_GADGET_PXA2XX is not set |
| 933 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 941 | # CONFIG_USB_GADGET_GOKU is not set | 934 | # CONFIG_USB_GADGET_GOKU is not set |
| 942 | # CONFIG_USB_GADGET_LH7A40X is not set | 935 | # CONFIG_USB_GADGET_LH7A40X is not set |
| 943 | # CONFIG_USB_GADGET_OMAP is not set | 936 | # CONFIG_USB_GADGET_OMAP is not set |
| 937 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 944 | CONFIG_USB_GADGET_AT91=y | 938 | CONFIG_USB_GADGET_AT91=y |
| 945 | CONFIG_USB_AT91=y | 939 | CONFIG_USB_AT91=y |
| 946 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | 940 | # CONFIG_USB_GADGET_DUMMY_HCD is not set |
| @@ -950,22 +944,28 @@ CONFIG_USB_AT91=y | |||
| 950 | # CONFIG_USB_GADGETFS is not set | 944 | # CONFIG_USB_GADGETFS is not set |
| 951 | # CONFIG_USB_FILE_STORAGE is not set | 945 | # CONFIG_USB_FILE_STORAGE is not set |
| 952 | # CONFIG_USB_G_SERIAL is not set | 946 | # CONFIG_USB_G_SERIAL is not set |
| 947 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 948 | CONFIG_MMC=y | ||
| 949 | # CONFIG_MMC_DEBUG is not set | ||
| 950 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 953 | 951 | ||
| 954 | # | 952 | # |
| 955 | # MMC/SD Card support | 953 | # MMC/SD Card Drivers |
| 956 | # | 954 | # |
| 957 | CONFIG_MMC=y | ||
| 958 | # CONFIG_MMC_DEBUG is not set | ||
| 959 | CONFIG_MMC_BLOCK=y | 955 | CONFIG_MMC_BLOCK=y |
| 960 | CONFIG_MMC_AT91RM9200=y | 956 | CONFIG_MMC_BLOCK_BOUNCE=y |
| 957 | # CONFIG_SDIO_UART is not set | ||
| 961 | 958 | ||
| 962 | # | 959 | # |
| 963 | # Real Time Clock | 960 | # MMC/SD Host Controller Drivers |
| 964 | # | 961 | # |
| 962 | # CONFIG_MMC_AT91 is not set | ||
| 963 | # CONFIG_NEW_LEDS is not set | ||
| 965 | CONFIG_RTC_LIB=y | 964 | CONFIG_RTC_LIB=y |
| 966 | CONFIG_RTC_CLASS=y | 965 | CONFIG_RTC_CLASS=y |
| 967 | CONFIG_RTC_HCTOSYS=y | 966 | CONFIG_RTC_HCTOSYS=y |
| 968 | CONFIG_RTC_HCTOSYS_DEVICE="rtc1" | 967 | CONFIG_RTC_HCTOSYS_DEVICE="rtc1" |
| 968 | # CONFIG_RTC_DEBUG is not set | ||
| 969 | 969 | ||
| 970 | # | 970 | # |
| 971 | # RTC interfaces | 971 | # RTC interfaces |
| @@ -974,39 +974,60 @@ CONFIG_RTC_HCTOSYS_DEVICE="rtc1" | |||
| 974 | CONFIG_RTC_INTF_PROC=y | 974 | CONFIG_RTC_INTF_PROC=y |
| 975 | CONFIG_RTC_INTF_DEV=y | 975 | CONFIG_RTC_INTF_DEV=y |
| 976 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | 976 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set |
| 977 | # CONFIG_RTC_DRV_TEST is not set | ||
| 977 | 978 | ||
| 978 | # | 979 | # |
| 979 | # RTC drivers | 980 | # I2C RTC drivers |
| 980 | # | 981 | # |
| 981 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 982 | CONFIG_RTC_DRV_DS1307=y | 982 | CONFIG_RTC_DRV_DS1307=y |
| 983 | # CONFIG_RTC_DRV_DS1553 is not set | 983 | # CONFIG_RTC_DRV_DS1374 is not set |
| 984 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 985 | # CONFIG_RTC_DRV_DS1672 is not set | 984 | # CONFIG_RTC_DRV_DS1672 is not set |
| 986 | # CONFIG_RTC_DRV_DS1742 is not set | 985 | # CONFIG_RTC_DRV_MAX6900 is not set |
| 986 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 987 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 988 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 987 | # CONFIG_RTC_DRV_PCF8563 is not set | 989 | # CONFIG_RTC_DRV_PCF8563 is not set |
| 988 | # CONFIG_RTC_DRV_PCF8583 is not set | 990 | # CONFIG_RTC_DRV_PCF8583 is not set |
| 989 | # CONFIG_RTC_DRV_RS5C372 is not set | 991 | # CONFIG_RTC_DRV_M41T80 is not set |
| 992 | |||
| 993 | # | ||
| 994 | # SPI RTC drivers | ||
| 995 | # | ||
| 996 | |||
| 997 | # | ||
| 998 | # Platform RTC drivers | ||
| 999 | # | ||
| 1000 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 1001 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1002 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1003 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 990 | # CONFIG_RTC_DRV_M48T86 is not set | 1004 | # CONFIG_RTC_DRV_M48T86 is not set |
| 991 | CONFIG_RTC_DRV_AT91RM9200=y | 1005 | # CONFIG_RTC_DRV_M48T59 is not set |
| 992 | # CONFIG_RTC_DRV_TEST is not set | ||
| 993 | # CONFIG_RTC_DRV_V3020 is not set | 1006 | # CONFIG_RTC_DRV_V3020 is not set |
| 994 | 1007 | ||
| 995 | # | 1008 | # |
| 1009 | # on-CPU RTC drivers | ||
| 1010 | # | ||
| 1011 | CONFIG_RTC_DRV_AT91RM9200=y | ||
| 1012 | |||
| 1013 | # | ||
| 996 | # File systems | 1014 | # File systems |
| 997 | # | 1015 | # |
| 998 | CONFIG_EXT2_FS=y | 1016 | CONFIG_EXT2_FS=y |
| 999 | # CONFIG_EXT2_FS_XATTR is not set | 1017 | # CONFIG_EXT2_FS_XATTR is not set |
| 1000 | # CONFIG_EXT2_FS_XIP is not set | 1018 | # CONFIG_EXT2_FS_XIP is not set |
| 1001 | # CONFIG_EXT3_FS is not set | 1019 | # CONFIG_EXT3_FS is not set |
| 1002 | # CONFIG_JBD is not set | 1020 | # CONFIG_EXT4DEV_FS is not set |
| 1003 | # CONFIG_REISERFS_FS is not set | 1021 | # CONFIG_REISERFS_FS is not set |
| 1004 | # CONFIG_JFS_FS is not set | 1022 | # CONFIG_JFS_FS is not set |
| 1005 | # CONFIG_FS_POSIX_ACL is not set | 1023 | # CONFIG_FS_POSIX_ACL is not set |
| 1006 | # CONFIG_XFS_FS is not set | 1024 | # CONFIG_XFS_FS is not set |
| 1025 | # CONFIG_GFS2_FS is not set | ||
| 1026 | # CONFIG_OCFS2_FS is not set | ||
| 1007 | # CONFIG_MINIX_FS is not set | 1027 | # CONFIG_MINIX_FS is not set |
| 1008 | # CONFIG_ROMFS_FS is not set | 1028 | # CONFIG_ROMFS_FS is not set |
| 1009 | CONFIG_INOTIFY=y | 1029 | CONFIG_INOTIFY=y |
| 1030 | CONFIG_INOTIFY_USER=y | ||
| 1010 | # CONFIG_QUOTA is not set | 1031 | # CONFIG_QUOTA is not set |
| 1011 | CONFIG_DNOTIFY=y | 1032 | CONFIG_DNOTIFY=y |
| 1012 | # CONFIG_AUTOFS_FS is not set | 1033 | # CONFIG_AUTOFS_FS is not set |
| @@ -1030,11 +1051,12 @@ CONFIG_DNOTIFY=y | |||
| 1030 | # Pseudo filesystems | 1051 | # Pseudo filesystems |
| 1031 | # | 1052 | # |
| 1032 | CONFIG_PROC_FS=y | 1053 | CONFIG_PROC_FS=y |
| 1054 | CONFIG_PROC_SYSCTL=y | ||
| 1033 | CONFIG_SYSFS=y | 1055 | CONFIG_SYSFS=y |
| 1034 | CONFIG_TMPFS=y | 1056 | CONFIG_TMPFS=y |
| 1057 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1035 | # CONFIG_HUGETLB_PAGE is not set | 1058 | # CONFIG_HUGETLB_PAGE is not set |
| 1036 | CONFIG_RAMFS=y | 1059 | # CONFIG_CONFIGFS_FS is not set |
| 1037 | # CONFIG_RELAYFS_FS is not set | ||
| 1038 | 1060 | ||
| 1039 | # | 1061 | # |
| 1040 | # Miscellaneous filesystems | 1062 | # Miscellaneous filesystems |
| @@ -1046,7 +1068,6 @@ CONFIG_RAMFS=y | |||
| 1046 | # CONFIG_BEFS_FS is not set | 1068 | # CONFIG_BEFS_FS is not set |
| 1047 | # CONFIG_BFS_FS is not set | 1069 | # CONFIG_BFS_FS is not set |
| 1048 | # CONFIG_EFS_FS is not set | 1070 | # CONFIG_EFS_FS is not set |
| 1049 | # CONFIG_JFFS_FS is not set | ||
| 1050 | # CONFIG_JFFS2_FS is not set | 1071 | # CONFIG_JFFS2_FS is not set |
| 1051 | CONFIG_CRAMFS=y | 1072 | CONFIG_CRAMFS=y |
| 1052 | # CONFIG_VXFS_FS is not set | 1073 | # CONFIG_VXFS_FS is not set |
| @@ -1054,10 +1075,7 @@ CONFIG_CRAMFS=y | |||
| 1054 | # CONFIG_QNX4FS_FS is not set | 1075 | # CONFIG_QNX4FS_FS is not set |
| 1055 | # CONFIG_SYSV_FS is not set | 1076 | # CONFIG_SYSV_FS is not set |
| 1056 | # CONFIG_UFS_FS is not set | 1077 | # CONFIG_UFS_FS is not set |
| 1057 | 1078 | CONFIG_NETWORK_FILESYSTEMS=y | |
| 1058 | # | ||
| 1059 | # Network File Systems | ||
| 1060 | # | ||
| 1061 | CONFIG_NFS_FS=y | 1079 | CONFIG_NFS_FS=y |
| 1062 | CONFIG_NFS_V3=y | 1080 | CONFIG_NFS_V3=y |
| 1063 | # CONFIG_NFS_V3_ACL is not set | 1081 | # CONFIG_NFS_V3_ACL is not set |
| @@ -1070,6 +1088,7 @@ CONFIG_LOCKD_V4=y | |||
| 1070 | CONFIG_NFS_COMMON=y | 1088 | CONFIG_NFS_COMMON=y |
| 1071 | CONFIG_SUNRPC=y | 1089 | CONFIG_SUNRPC=y |
| 1072 | CONFIG_SUNRPC_GSS=y | 1090 | CONFIG_SUNRPC_GSS=y |
| 1091 | # CONFIG_SUNRPC_BIND34 is not set | ||
| 1073 | CONFIG_RPCSEC_GSS_KRB5=y | 1092 | CONFIG_RPCSEC_GSS_KRB5=y |
| 1074 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1093 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1075 | # CONFIG_SMB_FS is not set | 1094 | # CONFIG_SMB_FS is not set |
| @@ -1077,43 +1096,56 @@ CONFIG_RPCSEC_GSS_KRB5=y | |||
| 1077 | # CONFIG_NCP_FS is not set | 1096 | # CONFIG_NCP_FS is not set |
| 1078 | # CONFIG_CODA_FS is not set | 1097 | # CONFIG_CODA_FS is not set |
| 1079 | # CONFIG_AFS_FS is not set | 1098 | # CONFIG_AFS_FS is not set |
| 1080 | # CONFIG_9P_FS is not set | ||
| 1081 | 1099 | ||
| 1082 | # | 1100 | # |
| 1083 | # Partition Types | 1101 | # Partition Types |
| 1084 | # | 1102 | # |
| 1085 | # CONFIG_PARTITION_ADVANCED is not set | 1103 | # CONFIG_PARTITION_ADVANCED is not set |
| 1086 | CONFIG_MSDOS_PARTITION=y | 1104 | CONFIG_MSDOS_PARTITION=y |
| 1087 | |||
| 1088 | # | ||
| 1089 | # Native Language Support | ||
| 1090 | # | ||
| 1091 | # CONFIG_NLS is not set | 1105 | # CONFIG_NLS is not set |
| 1092 | 1106 | # CONFIG_DLM is not set | |
| 1093 | # | 1107 | CONFIG_INSTRUMENTATION=y |
| 1094 | # Profiling support | ||
| 1095 | # | ||
| 1096 | # CONFIG_PROFILING is not set | 1108 | # CONFIG_PROFILING is not set |
| 1109 | # CONFIG_MARKERS is not set | ||
| 1097 | 1110 | ||
| 1098 | # | 1111 | # |
| 1099 | # Kernel hacking | 1112 | # Kernel hacking |
| 1100 | # | 1113 | # |
| 1101 | # CONFIG_PRINTK_TIME is not set | 1114 | # CONFIG_PRINTK_TIME is not set |
| 1102 | CONFIG_DEBUG_KERNEL=y | 1115 | CONFIG_ENABLE_WARN_DEPRECATED=y |
| 1116 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1103 | # CONFIG_MAGIC_SYSRQ is not set | 1117 | # CONFIG_MAGIC_SYSRQ is not set |
| 1104 | CONFIG_LOG_BUF_SHIFT=14 | 1118 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1119 | # CONFIG_DEBUG_FS is not set | ||
| 1120 | # CONFIG_HEADERS_CHECK is not set | ||
| 1121 | CONFIG_DEBUG_KERNEL=y | ||
| 1122 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1105 | CONFIG_DETECT_SOFTLOCKUP=y | 1123 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1124 | CONFIG_SCHED_DEBUG=y | ||
| 1106 | # CONFIG_SCHEDSTATS is not set | 1125 | # CONFIG_SCHEDSTATS is not set |
| 1107 | # CONFIG_DEBUG_SLAB is not set | 1126 | # CONFIG_TIMER_STATS is not set |
| 1127 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 1128 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1129 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1108 | # CONFIG_DEBUG_SPINLOCK is not set | 1130 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1131 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1132 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1133 | # CONFIG_PROVE_LOCKING is not set | ||
| 1134 | # CONFIG_LOCK_STAT is not set | ||
| 1109 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1135 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1136 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1110 | # CONFIG_DEBUG_KOBJECT is not set | 1137 | # CONFIG_DEBUG_KOBJECT is not set |
| 1111 | CONFIG_DEBUG_BUGVERBOSE=y | 1138 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1112 | # CONFIG_DEBUG_INFO is not set | 1139 | # CONFIG_DEBUG_INFO is not set |
| 1113 | # CONFIG_DEBUG_FS is not set | ||
| 1114 | # CONFIG_DEBUG_VM is not set | 1140 | # CONFIG_DEBUG_VM is not set |
| 1141 | # CONFIG_DEBUG_LIST is not set | ||
| 1142 | # CONFIG_DEBUG_SG is not set | ||
| 1115 | CONFIG_FRAME_POINTER=y | 1143 | CONFIG_FRAME_POINTER=y |
| 1144 | CONFIG_FORCED_INLINING=y | ||
| 1145 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1116 | # CONFIG_RCU_TORTURE_TEST is not set | 1146 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1147 | # CONFIG_FAULT_INJECTION is not set | ||
| 1148 | # CONFIG_SAMPLES is not set | ||
| 1117 | CONFIG_DEBUG_USER=y | 1149 | CONFIG_DEBUG_USER=y |
| 1118 | # CONFIG_DEBUG_ERRORS is not set | 1150 | # CONFIG_DEBUG_ERRORS is not set |
| 1119 | CONFIG_DEBUG_LL=y | 1151 | CONFIG_DEBUG_LL=y |
| @@ -1124,12 +1156,13 @@ CONFIG_DEBUG_LL=y | |||
| 1124 | # | 1156 | # |
| 1125 | # CONFIG_KEYS is not set | 1157 | # CONFIG_KEYS is not set |
| 1126 | # CONFIG_SECURITY is not set | 1158 | # CONFIG_SECURITY is not set |
| 1127 | 1159 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | |
| 1128 | # | ||
| 1129 | # Cryptographic options | ||
| 1130 | # | ||
| 1131 | CONFIG_CRYPTO=y | 1160 | CONFIG_CRYPTO=y |
| 1161 | CONFIG_CRYPTO_ALGAPI=y | ||
| 1162 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 1163 | CONFIG_CRYPTO_MANAGER=y | ||
| 1132 | # CONFIG_CRYPTO_HMAC is not set | 1164 | # CONFIG_CRYPTO_HMAC is not set |
| 1165 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1133 | # CONFIG_CRYPTO_NULL is not set | 1166 | # CONFIG_CRYPTO_NULL is not set |
| 1134 | # CONFIG_CRYPTO_MD4 is not set | 1167 | # CONFIG_CRYPTO_MD4 is not set |
| 1135 | CONFIG_CRYPTO_MD5=y | 1168 | CONFIG_CRYPTO_MD5=y |
| @@ -1138,7 +1171,15 @@ CONFIG_CRYPTO_MD5=y | |||
| 1138 | # CONFIG_CRYPTO_SHA512 is not set | 1171 | # CONFIG_CRYPTO_SHA512 is not set |
| 1139 | # CONFIG_CRYPTO_WP512 is not set | 1172 | # CONFIG_CRYPTO_WP512 is not set |
| 1140 | # CONFIG_CRYPTO_TGR192 is not set | 1173 | # CONFIG_CRYPTO_TGR192 is not set |
| 1174 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1175 | # CONFIG_CRYPTO_ECB is not set | ||
| 1176 | CONFIG_CRYPTO_CBC=y | ||
| 1177 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1178 | # CONFIG_CRYPTO_LRW is not set | ||
| 1179 | # CONFIG_CRYPTO_XTS is not set | ||
| 1180 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1141 | CONFIG_CRYPTO_DES=y | 1181 | CONFIG_CRYPTO_DES=y |
| 1182 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1142 | # CONFIG_CRYPTO_BLOWFISH is not set | 1183 | # CONFIG_CRYPTO_BLOWFISH is not set |
| 1143 | # CONFIG_CRYPTO_TWOFISH is not set | 1184 | # CONFIG_CRYPTO_TWOFISH is not set |
| 1144 | # CONFIG_CRYPTO_SERPENT is not set | 1185 | # CONFIG_CRYPTO_SERPENT is not set |
| @@ -1149,20 +1190,27 @@ CONFIG_CRYPTO_DES=y | |||
| 1149 | # CONFIG_CRYPTO_ARC4 is not set | 1190 | # CONFIG_CRYPTO_ARC4 is not set |
| 1150 | # CONFIG_CRYPTO_KHAZAD is not set | 1191 | # CONFIG_CRYPTO_KHAZAD is not set |
| 1151 | # CONFIG_CRYPTO_ANUBIS is not set | 1192 | # CONFIG_CRYPTO_ANUBIS is not set |
| 1193 | # CONFIG_CRYPTO_SEED is not set | ||
| 1152 | # CONFIG_CRYPTO_DEFLATE is not set | 1194 | # CONFIG_CRYPTO_DEFLATE is not set |
| 1153 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | 1195 | # CONFIG_CRYPTO_MICHAEL_MIC is not set |
| 1154 | # CONFIG_CRYPTO_CRC32C is not set | 1196 | # CONFIG_CRYPTO_CRC32C is not set |
| 1197 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1155 | # CONFIG_CRYPTO_TEST is not set | 1198 | # CONFIG_CRYPTO_TEST is not set |
| 1156 | 1199 | # CONFIG_CRYPTO_AUTHENC is not set | |
| 1157 | # | 1200 | CONFIG_CRYPTO_HW=y |
| 1158 | # Hardware crypto devices | ||
| 1159 | # | ||
| 1160 | 1201 | ||
| 1161 | # | 1202 | # |
| 1162 | # Library routines | 1203 | # Library routines |
| 1163 | # | 1204 | # |
| 1205 | CONFIG_BITREVERSE=y | ||
| 1164 | # CONFIG_CRC_CCITT is not set | 1206 | # CONFIG_CRC_CCITT is not set |
| 1165 | # CONFIG_CRC16 is not set | 1207 | # CONFIG_CRC16 is not set |
| 1208 | # CONFIG_CRC_ITU_T is not set | ||
| 1166 | CONFIG_CRC32=y | 1209 | CONFIG_CRC32=y |
| 1210 | # CONFIG_CRC7 is not set | ||
| 1167 | # CONFIG_LIBCRC32C is not set | 1211 | # CONFIG_LIBCRC32C is not set |
| 1168 | CONFIG_ZLIB_INFLATE=y | 1212 | CONFIG_ZLIB_INFLATE=y |
| 1213 | CONFIG_PLIST=y | ||
| 1214 | CONFIG_HAS_IOMEM=y | ||
| 1215 | CONFIG_HAS_IOPORT=y | ||
| 1216 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/csb637_defconfig b/arch/arm/configs/csb637_defconfig index 669f035896f9..99702146c9fc 100644 --- a/arch/arm/configs/csb637_defconfig +++ b/arch/arm/configs/csb637_defconfig | |||
| @@ -1,69 +1,112 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.15 | 3 | # Linux kernel version: 2.6.25-rc8 |
| 4 | # Mon Jan 9 21:52:00 2006 | 4 | # Fri Apr 4 22:06:15 2008 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 7 | CONFIG_MMU=y | 11 | CONFIG_MMU=y |
| 8 | CONFIG_UID16=y | 12 | # CONFIG_NO_IOPORT is not set |
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 18 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 9 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 20 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 22 | CONFIG_GENERIC_HWEIGHT=y | ||
| 10 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 24 | CONFIG_ARCH_SUPPORTS_AOUT=y | ||
| 25 | CONFIG_ZONE_DMA=y | ||
| 26 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 11 | 28 | ||
| 12 | # | 29 | # |
| 13 | # Code maturity level options | 30 | # General setup |
| 14 | # | 31 | # |
| 15 | CONFIG_EXPERIMENTAL=y | 32 | CONFIG_EXPERIMENTAL=y |
| 16 | CONFIG_CLEAN_COMPILE=y | ||
| 17 | CONFIG_BROKEN_ON_SMP=y | 33 | CONFIG_BROKEN_ON_SMP=y |
| 18 | CONFIG_INIT_ENV_ARG_LIMIT=32 | 34 | CONFIG_INIT_ENV_ARG_LIMIT=32 |
| 19 | |||
| 20 | # | ||
| 21 | # General setup | ||
| 22 | # | ||
| 23 | CONFIG_LOCALVERSION="" | 35 | CONFIG_LOCALVERSION="" |
| 24 | CONFIG_LOCALVERSION_AUTO=y | 36 | CONFIG_LOCALVERSION_AUTO=y |
| 25 | # CONFIG_SWAP is not set | 37 | # CONFIG_SWAP is not set |
| 26 | CONFIG_SYSVIPC=y | 38 | CONFIG_SYSVIPC=y |
| 39 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 27 | # CONFIG_POSIX_MQUEUE is not set | 40 | # CONFIG_POSIX_MQUEUE is not set |
| 28 | # CONFIG_BSD_PROCESS_ACCT is not set | 41 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 29 | CONFIG_SYSCTL=y | 42 | # CONFIG_TASKSTATS is not set |
| 30 | # CONFIG_AUDIT is not set | 43 | # CONFIG_AUDIT is not set |
| 31 | CONFIG_HOTPLUG=y | ||
| 32 | CONFIG_KOBJECT_UEVENT=y | ||
| 33 | # CONFIG_IKCONFIG is not set | 44 | # CONFIG_IKCONFIG is not set |
| 45 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 46 | # CONFIG_CGROUPS is not set | ||
| 47 | CONFIG_GROUP_SCHED=y | ||
| 48 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 49 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 50 | CONFIG_USER_SCHED=y | ||
| 51 | # CONFIG_CGROUP_SCHED is not set | ||
| 52 | CONFIG_SYSFS_DEPRECATED=y | ||
| 53 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 54 | # CONFIG_RELAY is not set | ||
| 55 | CONFIG_NAMESPACES=y | ||
| 56 | # CONFIG_UTS_NS is not set | ||
| 57 | # CONFIG_IPC_NS is not set | ||
| 58 | # CONFIG_USER_NS is not set | ||
| 59 | # CONFIG_PID_NS is not set | ||
| 60 | CONFIG_BLK_DEV_INITRD=y | ||
| 34 | CONFIG_INITRAMFS_SOURCE="" | 61 | CONFIG_INITRAMFS_SOURCE="" |
| 35 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 62 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 63 | CONFIG_SYSCTL=y | ||
| 36 | # CONFIG_EMBEDDED is not set | 64 | # CONFIG_EMBEDDED is not set |
| 65 | CONFIG_UID16=y | ||
| 66 | CONFIG_SYSCTL_SYSCALL=y | ||
| 37 | CONFIG_KALLSYMS=y | 67 | CONFIG_KALLSYMS=y |
| 38 | # CONFIG_KALLSYMS_ALL is not set | 68 | # CONFIG_KALLSYMS_ALL is not set |
| 39 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 69 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 70 | CONFIG_HOTPLUG=y | ||
| 40 | CONFIG_PRINTK=y | 71 | CONFIG_PRINTK=y |
| 41 | CONFIG_BUG=y | 72 | CONFIG_BUG=y |
| 73 | CONFIG_ELF_CORE=y | ||
| 74 | CONFIG_COMPAT_BRK=y | ||
| 42 | CONFIG_BASE_FULL=y | 75 | CONFIG_BASE_FULL=y |
| 43 | CONFIG_FUTEX=y | 76 | CONFIG_FUTEX=y |
| 77 | CONFIG_ANON_INODES=y | ||
| 44 | CONFIG_EPOLL=y | 78 | CONFIG_EPOLL=y |
| 79 | CONFIG_SIGNALFD=y | ||
| 80 | CONFIG_TIMERFD=y | ||
| 81 | CONFIG_EVENTFD=y | ||
| 45 | CONFIG_SHMEM=y | 82 | CONFIG_SHMEM=y |
| 46 | CONFIG_CC_ALIGN_FUNCTIONS=0 | 83 | CONFIG_VM_EVENT_COUNTERS=y |
| 47 | CONFIG_CC_ALIGN_LABELS=0 | 84 | CONFIG_SLUB_DEBUG=y |
| 48 | CONFIG_CC_ALIGN_LOOPS=0 | 85 | # CONFIG_SLAB is not set |
| 49 | CONFIG_CC_ALIGN_JUMPS=0 | 86 | CONFIG_SLUB=y |
| 87 | # CONFIG_SLOB is not set | ||
| 88 | # CONFIG_PROFILING is not set | ||
| 89 | # CONFIG_MARKERS is not set | ||
| 90 | CONFIG_HAVE_OPROFILE=y | ||
| 91 | # CONFIG_KPROBES is not set | ||
| 92 | CONFIG_HAVE_KPROBES=y | ||
| 93 | CONFIG_HAVE_KRETPROBES=y | ||
| 94 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 95 | CONFIG_SLABINFO=y | ||
| 96 | CONFIG_RT_MUTEXES=y | ||
| 50 | # CONFIG_TINY_SHMEM is not set | 97 | # CONFIG_TINY_SHMEM is not set |
| 51 | CONFIG_BASE_SMALL=0 | 98 | CONFIG_BASE_SMALL=0 |
| 52 | |||
| 53 | # | ||
| 54 | # Loadable module support | ||
| 55 | # | ||
| 56 | CONFIG_MODULES=y | 99 | CONFIG_MODULES=y |
| 57 | CONFIG_MODULE_UNLOAD=y | 100 | CONFIG_MODULE_UNLOAD=y |
| 58 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 101 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 59 | CONFIG_OBSOLETE_MODPARM=y | ||
| 60 | # CONFIG_MODVERSIONS is not set | 102 | # CONFIG_MODVERSIONS is not set |
| 61 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 103 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 62 | CONFIG_KMOD=y | 104 | CONFIG_KMOD=y |
| 63 | 105 | CONFIG_BLOCK=y | |
| 64 | # | 106 | # CONFIG_LBD is not set |
| 65 | # Block layer | 107 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 66 | # | 108 | # CONFIG_LSF is not set |
| 109 | # CONFIG_BLK_DEV_BSG is not set | ||
| 67 | 110 | ||
| 68 | # | 111 | # |
| 69 | # IO Schedulers | 112 | # IO Schedulers |
| @@ -77,66 +120,111 @@ CONFIG_DEFAULT_AS=y | |||
| 77 | # CONFIG_DEFAULT_CFQ is not set | 120 | # CONFIG_DEFAULT_CFQ is not set |
| 78 | # CONFIG_DEFAULT_NOOP is not set | 121 | # CONFIG_DEFAULT_NOOP is not set |
| 79 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 122 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 123 | CONFIG_CLASSIC_RCU=y | ||
| 80 | 124 | ||
| 81 | # | 125 | # |
| 82 | # System Type | 126 | # System Type |
| 83 | # | 127 | # |
| 128 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 129 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 130 | # CONFIG_ARCH_REALVIEW is not set | ||
| 131 | # CONFIG_ARCH_VERSATILE is not set | ||
| 132 | CONFIG_ARCH_AT91=y | ||
| 84 | # CONFIG_ARCH_CLPS7500 is not set | 133 | # CONFIG_ARCH_CLPS7500 is not set |
| 85 | # CONFIG_ARCH_CLPS711X is not set | 134 | # CONFIG_ARCH_CLPS711X is not set |
| 86 | # CONFIG_ARCH_CO285 is not set | 135 | # CONFIG_ARCH_CO285 is not set |
| 87 | # CONFIG_ARCH_EBSA110 is not set | 136 | # CONFIG_ARCH_EBSA110 is not set |
| 137 | # CONFIG_ARCH_EP93XX is not set | ||
| 88 | # CONFIG_ARCH_FOOTBRIDGE is not set | 138 | # CONFIG_ARCH_FOOTBRIDGE is not set |
| 89 | # CONFIG_ARCH_INTEGRATOR is not set | 139 | # CONFIG_ARCH_NETX is not set |
| 90 | # CONFIG_ARCH_IOP3XX is not set | 140 | # CONFIG_ARCH_H720X is not set |
| 91 | # CONFIG_ARCH_IXP4XX is not set | 141 | # CONFIG_ARCH_IMX is not set |
| 142 | # CONFIG_ARCH_IOP13XX is not set | ||
| 143 | # CONFIG_ARCH_IOP32X is not set | ||
| 144 | # CONFIG_ARCH_IOP33X is not set | ||
| 145 | # CONFIG_ARCH_IXP23XX is not set | ||
| 92 | # CONFIG_ARCH_IXP2000 is not set | 146 | # CONFIG_ARCH_IXP2000 is not set |
| 147 | # CONFIG_ARCH_IXP4XX is not set | ||
| 93 | # CONFIG_ARCH_L7200 is not set | 148 | # CONFIG_ARCH_L7200 is not set |
| 149 | # CONFIG_ARCH_KS8695 is not set | ||
| 150 | # CONFIG_ARCH_NS9XXX is not set | ||
| 151 | # CONFIG_ARCH_MXC is not set | ||
| 152 | # CONFIG_ARCH_ORION is not set | ||
| 153 | # CONFIG_ARCH_PNX4008 is not set | ||
| 94 | # CONFIG_ARCH_PXA is not set | 154 | # CONFIG_ARCH_PXA is not set |
| 95 | # CONFIG_ARCH_RPC is not set | 155 | # CONFIG_ARCH_RPC is not set |
| 96 | # CONFIG_ARCH_SA1100 is not set | 156 | # CONFIG_ARCH_SA1100 is not set |
| 97 | # CONFIG_ARCH_S3C2410 is not set | 157 | # CONFIG_ARCH_S3C2410 is not set |
| 98 | # CONFIG_ARCH_SHARK is not set | 158 | # CONFIG_ARCH_SHARK is not set |
| 99 | # CONFIG_ARCH_LH7A40X is not set | 159 | # CONFIG_ARCH_LH7A40X is not set |
| 160 | # CONFIG_ARCH_DAVINCI is not set | ||
| 100 | # CONFIG_ARCH_OMAP is not set | 161 | # CONFIG_ARCH_OMAP is not set |
| 101 | # CONFIG_ARCH_VERSATILE is not set | 162 | # CONFIG_ARCH_MSM7X00A is not set |
| 102 | # CONFIG_ARCH_REALVIEW is not set | 163 | |
| 103 | # CONFIG_ARCH_IMX is not set | 164 | # |
| 104 | # CONFIG_ARCH_H720X is not set | 165 | # Boot options |
| 105 | # CONFIG_ARCH_AAEC2000 is not set | 166 | # |
| 106 | CONFIG_ARCH_AT91=y | 167 | |
| 107 | CONFIG_ARCH_AT91RM9200=y | 168 | # |
| 169 | # Power management | ||
| 170 | # | ||
| 108 | 171 | ||
| 109 | # | 172 | # |
| 110 | # AT91RM9200 Implementations | 173 | # Atmel AT91 System-on-Chip |
| 111 | # | 174 | # |
| 175 | CONFIG_ARCH_AT91RM9200=y | ||
| 176 | # CONFIG_ARCH_AT91SAM9260 is not set | ||
| 177 | # CONFIG_ARCH_AT91SAM9261 is not set | ||
| 178 | # CONFIG_ARCH_AT91SAM9263 is not set | ||
| 179 | # CONFIG_ARCH_AT91SAM9RL is not set | ||
| 180 | # CONFIG_ARCH_AT91CAP9 is not set | ||
| 181 | # CONFIG_ARCH_AT91X40 is not set | ||
| 182 | CONFIG_AT91_PMC_UNIT=y | ||
| 112 | 183 | ||
| 113 | # | 184 | # |
| 114 | # AT91RM9200 Board Type | 185 | # AT91RM9200 Board Type |
| 115 | # | 186 | # |
| 187 | # CONFIG_MACH_ONEARM is not set | ||
| 116 | # CONFIG_ARCH_AT91RM9200DK is not set | 188 | # CONFIG_ARCH_AT91RM9200DK is not set |
| 117 | # CONFIG_MACH_AT91RM9200EK is not set | 189 | # CONFIG_MACH_AT91RM9200EK is not set |
| 118 | # CONFIG_MACH_CSB337 is not set | 190 | # CONFIG_MACH_CSB337 is not set |
| 119 | CONFIG_MACH_CSB637=y | 191 | CONFIG_MACH_CSB637=y |
| 120 | # CONFIG_MACH_CARMEVA is not set | 192 | # CONFIG_MACH_CARMEVA is not set |
| 121 | # CONFIG_MACH_KB9200 is not set | ||
| 122 | # CONFIG_MACH_ATEB9200 is not set | 193 | # CONFIG_MACH_ATEB9200 is not set |
| 194 | # CONFIG_MACH_KB9200 is not set | ||
| 195 | # CONFIG_MACH_PICOTUX2XX is not set | ||
| 196 | # CONFIG_MACH_KAFA is not set | ||
| 123 | 197 | ||
| 124 | # | 198 | # |
| 125 | # AT91RM9200 Feature Selections | 199 | # AT91 Board Options |
| 200 | # | ||
| 201 | |||
| 202 | # | ||
| 203 | # AT91 Feature Selections | ||
| 126 | # | 204 | # |
| 127 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | 205 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y |
| 206 | CONFIG_AT91_TIMER_HZ=128 | ||
| 207 | CONFIG_AT91_EARLY_DBGU=y | ||
| 208 | # CONFIG_AT91_EARLY_USART0 is not set | ||
| 209 | # CONFIG_AT91_EARLY_USART1 is not set | ||
| 210 | # CONFIG_AT91_EARLY_USART2 is not set | ||
| 211 | # CONFIG_AT91_EARLY_USART3 is not set | ||
| 212 | # CONFIG_AT91_EARLY_USART4 is not set | ||
| 213 | # CONFIG_AT91_EARLY_USART5 is not set | ||
| 128 | 214 | ||
| 129 | # | 215 | # |
| 130 | # Processor Type | 216 | # Processor Type |
| 131 | # | 217 | # |
| 132 | CONFIG_CPU_32=y | 218 | CONFIG_CPU_32=y |
| 133 | CONFIG_CPU_ARM920T=y | 219 | CONFIG_CPU_ARM920T=y |
| 134 | CONFIG_CPU_32v4=y | 220 | CONFIG_CPU_32v4T=y |
| 135 | CONFIG_CPU_ABRT_EV4T=y | 221 | CONFIG_CPU_ABRT_EV4T=y |
| 136 | CONFIG_CPU_CACHE_V4WT=y | 222 | CONFIG_CPU_CACHE_V4WT=y |
| 137 | CONFIG_CPU_CACHE_VIVT=y | 223 | CONFIG_CPU_CACHE_VIVT=y |
| 138 | CONFIG_CPU_COPY_V4WB=y | 224 | CONFIG_CPU_COPY_V4WB=y |
| 139 | CONFIG_CPU_TLB_V4WBI=y | 225 | CONFIG_CPU_TLB_V4WBI=y |
| 226 | CONFIG_CPU_CP15=y | ||
| 227 | CONFIG_CPU_CP15_MMU=y | ||
| 140 | 228 | ||
| 141 | # | 229 | # |
| 142 | # Processor Features | 230 | # Processor Features |
| @@ -145,15 +233,13 @@ CONFIG_CPU_TLB_V4WBI=y | |||
| 145 | # CONFIG_CPU_ICACHE_DISABLE is not set | 233 | # CONFIG_CPU_ICACHE_DISABLE is not set |
| 146 | # CONFIG_CPU_DCACHE_DISABLE is not set | 234 | # CONFIG_CPU_DCACHE_DISABLE is not set |
| 147 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | 235 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set |
| 236 | # CONFIG_OUTER_CACHE is not set | ||
| 148 | 237 | ||
| 149 | # | 238 | # |
| 150 | # Bus support | 239 | # Bus support |
| 151 | # | 240 | # |
| 152 | CONFIG_ISA_DMA_API=y | 241 | # CONFIG_PCI_SYSCALL is not set |
| 153 | 242 | # CONFIG_ARCH_SUPPORTS_MSI is not set | |
| 154 | # | ||
| 155 | # PCCARD (PCMCIA/CardBus) support | ||
| 156 | # | ||
| 157 | CONFIG_PCCARD=y | 243 | CONFIG_PCCARD=y |
| 158 | # CONFIG_PCMCIA_DEBUG is not set | 244 | # CONFIG_PCMCIA_DEBUG is not set |
| 159 | CONFIG_PCMCIA=y | 245 | CONFIG_PCMCIA=y |
| @@ -168,8 +254,13 @@ CONFIG_AT91_CF=y | |||
| 168 | # | 254 | # |
| 169 | # Kernel Features | 255 | # Kernel Features |
| 170 | # | 256 | # |
| 257 | # CONFIG_TICK_ONESHOT is not set | ||
| 258 | # CONFIG_NO_HZ is not set | ||
| 259 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 260 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 171 | # CONFIG_PREEMPT is not set | 261 | # CONFIG_PREEMPT is not set |
| 172 | # CONFIG_NO_IDLE_HZ is not set | 262 | CONFIG_HZ=128 |
| 263 | # CONFIG_AEABI is not set | ||
| 173 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | 264 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set |
| 174 | CONFIG_SELECT_MEMORY_MODEL=y | 265 | CONFIG_SELECT_MEMORY_MODEL=y |
| 175 | CONFIG_FLATMEM_MANUAL=y | 266 | CONFIG_FLATMEM_MANUAL=y |
| @@ -178,9 +269,13 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 178 | CONFIG_FLATMEM=y | 269 | CONFIG_FLATMEM=y |
| 179 | CONFIG_FLAT_NODE_MEM_MAP=y | 270 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 180 | # CONFIG_SPARSEMEM_STATIC is not set | 271 | # CONFIG_SPARSEMEM_STATIC is not set |
| 272 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 181 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 273 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 274 | # CONFIG_RESOURCES_64BIT is not set | ||
| 275 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 276 | CONFIG_BOUNCE=y | ||
| 277 | CONFIG_VIRT_TO_BUS=y | ||
| 182 | CONFIG_LEDS=y | 278 | CONFIG_LEDS=y |
| 183 | CONFIG_LEDS_TIMER=y | ||
| 184 | CONFIG_LEDS_CPU=y | 279 | CONFIG_LEDS_CPU=y |
| 185 | CONFIG_ALIGNMENT_TRAP=y | 280 | CONFIG_ALIGNMENT_TRAP=y |
| 186 | 281 | ||
| @@ -191,6 +286,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 | |||
| 191 | CONFIG_ZBOOT_ROM_BSS=0x0 | 286 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 192 | CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw" | 287 | CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw" |
| 193 | # CONFIG_XIP_KERNEL is not set | 288 | # CONFIG_XIP_KERNEL is not set |
| 289 | # CONFIG_KEXEC is not set | ||
| 194 | 290 | ||
| 195 | # | 291 | # |
| 196 | # Floating point emulation | 292 | # Floating point emulation |
| @@ -215,6 +311,7 @@ CONFIG_BINFMT_ELF=y | |||
| 215 | # Power management options | 311 | # Power management options |
| 216 | # | 312 | # |
| 217 | # CONFIG_PM is not set | 313 | # CONFIG_PM is not set |
| 314 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 218 | 315 | ||
| 219 | # | 316 | # |
| 220 | # Networking | 317 | # Networking |
| @@ -227,6 +324,11 @@ CONFIG_NET=y | |||
| 227 | CONFIG_PACKET=y | 324 | CONFIG_PACKET=y |
| 228 | # CONFIG_PACKET_MMAP is not set | 325 | # CONFIG_PACKET_MMAP is not set |
| 229 | CONFIG_UNIX=y | 326 | CONFIG_UNIX=y |
| 327 | CONFIG_XFRM=y | ||
| 328 | # CONFIG_XFRM_USER is not set | ||
| 329 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 330 | # CONFIG_XFRM_MIGRATE is not set | ||
| 331 | # CONFIG_XFRM_STATISTICS is not set | ||
| 230 | # CONFIG_NET_KEY is not set | 332 | # CONFIG_NET_KEY is not set |
| 231 | CONFIG_INET=y | 333 | CONFIG_INET=y |
| 232 | # CONFIG_IP_MULTICAST is not set | 334 | # CONFIG_IP_MULTICAST is not set |
| @@ -243,23 +345,26 @@ CONFIG_IP_PNP_BOOTP=y | |||
| 243 | # CONFIG_INET_AH is not set | 345 | # CONFIG_INET_AH is not set |
| 244 | # CONFIG_INET_ESP is not set | 346 | # CONFIG_INET_ESP is not set |
| 245 | # CONFIG_INET_IPCOMP is not set | 347 | # CONFIG_INET_IPCOMP is not set |
| 348 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 246 | # CONFIG_INET_TUNNEL is not set | 349 | # CONFIG_INET_TUNNEL is not set |
| 350 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 351 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 352 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 353 | # CONFIG_INET_LRO is not set | ||
| 247 | CONFIG_INET_DIAG=y | 354 | CONFIG_INET_DIAG=y |
| 248 | CONFIG_INET_TCP_DIAG=y | 355 | CONFIG_INET_TCP_DIAG=y |
| 249 | # CONFIG_TCP_CONG_ADVANCED is not set | 356 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 250 | CONFIG_TCP_CONG_BIC=y | 357 | CONFIG_TCP_CONG_CUBIC=y |
| 358 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 359 | # CONFIG_TCP_MD5SIG is not set | ||
| 251 | # CONFIG_IPV6 is not set | 360 | # CONFIG_IPV6 is not set |
| 361 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 362 | # CONFIG_INET6_TUNNEL is not set | ||
| 363 | # CONFIG_NETWORK_SECMARK is not set | ||
| 252 | # CONFIG_NETFILTER is not set | 364 | # CONFIG_NETFILTER is not set |
| 253 | |||
| 254 | # | ||
| 255 | # DCCP Configuration (EXPERIMENTAL) | ||
| 256 | # | ||
| 257 | # CONFIG_IP_DCCP is not set | 365 | # CONFIG_IP_DCCP is not set |
| 258 | |||
| 259 | # | ||
| 260 | # SCTP Configuration (EXPERIMENTAL) | ||
| 261 | # | ||
| 262 | # CONFIG_IP_SCTP is not set | 366 | # CONFIG_IP_SCTP is not set |
| 367 | # CONFIG_TIPC is not set | ||
| 263 | # CONFIG_ATM is not set | 368 | # CONFIG_ATM is not set |
| 264 | # CONFIG_BRIDGE is not set | 369 | # CONFIG_BRIDGE is not set |
| 265 | # CONFIG_VLAN_8021Q is not set | 370 | # CONFIG_VLAN_8021Q is not set |
| @@ -269,13 +374,8 @@ CONFIG_TCP_CONG_BIC=y | |||
| 269 | # CONFIG_ATALK is not set | 374 | # CONFIG_ATALK is not set |
| 270 | # CONFIG_X25 is not set | 375 | # CONFIG_X25 is not set |
| 271 | # CONFIG_LAPB is not set | 376 | # CONFIG_LAPB is not set |
| 272 | # CONFIG_NET_DIVERT is not set | ||
| 273 | # CONFIG_ECONET is not set | 377 | # CONFIG_ECONET is not set |
| 274 | # CONFIG_WAN_ROUTER is not set | 378 | # CONFIG_WAN_ROUTER is not set |
| 275 | |||
| 276 | # | ||
| 277 | # QoS and/or fair queueing | ||
| 278 | # | ||
| 279 | # CONFIG_NET_SCHED is not set | 379 | # CONFIG_NET_SCHED is not set |
| 280 | 380 | ||
| 281 | # | 381 | # |
| @@ -283,9 +383,20 @@ CONFIG_TCP_CONG_BIC=y | |||
| 283 | # | 383 | # |
| 284 | # CONFIG_NET_PKTGEN is not set | 384 | # CONFIG_NET_PKTGEN is not set |
| 285 | # CONFIG_HAMRADIO is not set | 385 | # CONFIG_HAMRADIO is not set |
| 386 | # CONFIG_CAN is not set | ||
| 286 | # CONFIG_IRDA is not set | 387 | # CONFIG_IRDA is not set |
| 287 | # CONFIG_BT is not set | 388 | # CONFIG_BT is not set |
| 389 | # CONFIG_AF_RXRPC is not set | ||
| 390 | |||
| 391 | # | ||
| 392 | # Wireless | ||
| 393 | # | ||
| 394 | # CONFIG_CFG80211 is not set | ||
| 395 | # CONFIG_WIRELESS_EXT is not set | ||
| 396 | # CONFIG_MAC80211 is not set | ||
| 288 | # CONFIG_IEEE80211 is not set | 397 | # CONFIG_IEEE80211 is not set |
| 398 | # CONFIG_RFKILL is not set | ||
| 399 | # CONFIG_NET_9P is not set | ||
| 289 | 400 | ||
| 290 | # | 401 | # |
| 291 | # Device Drivers | 402 | # Device Drivers |
| @@ -294,19 +405,14 @@ CONFIG_TCP_CONG_BIC=y | |||
| 294 | # | 405 | # |
| 295 | # Generic Driver Options | 406 | # Generic Driver Options |
| 296 | # | 407 | # |
| 408 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 297 | CONFIG_STANDALONE=y | 409 | CONFIG_STANDALONE=y |
| 298 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 410 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 299 | CONFIG_FW_LOADER=y | 411 | CONFIG_FW_LOADER=y |
| 300 | # CONFIG_DEBUG_DRIVER is not set | 412 | # CONFIG_DEBUG_DRIVER is not set |
| 301 | 413 | # CONFIG_DEBUG_DEVRES is not set | |
| 302 | # | 414 | # CONFIG_SYS_HYPERVISOR is not set |
| 303 | # Connector - unified userspace <-> kernelspace linker | ||
| 304 | # | ||
| 305 | # CONFIG_CONNECTOR is not set | 415 | # CONFIG_CONNECTOR is not set |
| 306 | |||
| 307 | # | ||
| 308 | # Memory Technology Devices (MTD) | ||
| 309 | # | ||
| 310 | CONFIG_MTD=y | 416 | CONFIG_MTD=y |
| 311 | # CONFIG_MTD_DEBUG is not set | 417 | # CONFIG_MTD_DEBUG is not set |
| 312 | # CONFIG_MTD_CONCAT is not set | 418 | # CONFIG_MTD_CONCAT is not set |
| @@ -319,11 +425,14 @@ CONFIG_MTD_CMDLINE_PARTS=y | |||
| 319 | # User Modules And Translation Layers | 425 | # User Modules And Translation Layers |
| 320 | # | 426 | # |
| 321 | CONFIG_MTD_CHAR=y | 427 | CONFIG_MTD_CHAR=y |
| 428 | CONFIG_MTD_BLKDEVS=y | ||
| 322 | CONFIG_MTD_BLOCK=y | 429 | CONFIG_MTD_BLOCK=y |
| 323 | # CONFIG_FTL is not set | 430 | # CONFIG_FTL is not set |
| 324 | # CONFIG_NFTL is not set | 431 | # CONFIG_NFTL is not set |
| 325 | # CONFIG_INFTL is not set | 432 | # CONFIG_INFTL is not set |
| 326 | # CONFIG_RFD_FTL is not set | 433 | # CONFIG_RFD_FTL is not set |
| 434 | # CONFIG_SSFDC is not set | ||
| 435 | # CONFIG_MTD_OOPS is not set | ||
| 327 | 436 | ||
| 328 | # | 437 | # |
| 329 | # RAM/ROM/Flash chip drivers | 438 | # RAM/ROM/Flash chip drivers |
| @@ -349,15 +458,14 @@ CONFIG_MTD_CFI_UTIL=y | |||
| 349 | # CONFIG_MTD_RAM is not set | 458 | # CONFIG_MTD_RAM is not set |
| 350 | # CONFIG_MTD_ROM is not set | 459 | # CONFIG_MTD_ROM is not set |
| 351 | # CONFIG_MTD_ABSENT is not set | 460 | # CONFIG_MTD_ABSENT is not set |
| 352 | # CONFIG_MTD_XIP is not set | ||
| 353 | 461 | ||
| 354 | # | 462 | # |
| 355 | # Mapping drivers for chip access | 463 | # Mapping drivers for chip access |
| 356 | # | 464 | # |
| 357 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | 465 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set |
| 358 | CONFIG_MTD_PHYSMAP=y | 466 | CONFIG_MTD_PHYSMAP=y |
| 359 | CONFIG_MTD_PHYSMAP_START=0 | 467 | CONFIG_MTD_PHYSMAP_START=0x0 |
| 360 | CONFIG_MTD_PHYSMAP_LEN=0 | 468 | CONFIG_MTD_PHYSMAP_LEN=0x0 |
| 361 | CONFIG_MTD_PHYSMAP_BANKWIDTH=0 | 469 | CONFIG_MTD_PHYSMAP_BANKWIDTH=0 |
| 362 | # CONFIG_MTD_ARM_INTEGRATOR is not set | 470 | # CONFIG_MTD_ARM_INTEGRATOR is not set |
| 363 | # CONFIG_MTD_PLATRAM is not set | 471 | # CONFIG_MTD_PLATRAM is not set |
| @@ -368,7 +476,6 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=0 | |||
| 368 | # CONFIG_MTD_SLRAM is not set | 476 | # CONFIG_MTD_SLRAM is not set |
| 369 | # CONFIG_MTD_PHRAM is not set | 477 | # CONFIG_MTD_PHRAM is not set |
| 370 | # CONFIG_MTD_MTDRAM is not set | 478 | # CONFIG_MTD_MTDRAM is not set |
| 371 | # CONFIG_MTD_BLKMTD is not set | ||
| 372 | # CONFIG_MTD_BLOCK2MTD is not set | 479 | # CONFIG_MTD_BLOCK2MTD is not set |
| 373 | 480 | ||
| 374 | # | 481 | # |
| @@ -377,30 +484,15 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=0 | |||
| 377 | # CONFIG_MTD_DOC2000 is not set | 484 | # CONFIG_MTD_DOC2000 is not set |
| 378 | # CONFIG_MTD_DOC2001 is not set | 485 | # CONFIG_MTD_DOC2001 is not set |
| 379 | # CONFIG_MTD_DOC2001PLUS is not set | 486 | # CONFIG_MTD_DOC2001PLUS is not set |
| 380 | # CONFIG_MTD_AT91_DATAFLASH is not set | ||
| 381 | |||
| 382 | # | ||
| 383 | # NAND Flash Device Drivers | ||
| 384 | # | ||
| 385 | # CONFIG_MTD_NAND is not set | 487 | # CONFIG_MTD_NAND is not set |
| 386 | |||
| 387 | # | ||
| 388 | # OneNAND Flash Device Drivers | ||
| 389 | # | ||
| 390 | # CONFIG_MTD_ONENAND is not set | 488 | # CONFIG_MTD_ONENAND is not set |
| 391 | 489 | ||
| 392 | # | 490 | # |
| 393 | # Parallel port support | 491 | # UBI - Unsorted block images |
| 394 | # | 492 | # |
| 493 | # CONFIG_MTD_UBI is not set | ||
| 395 | # CONFIG_PARPORT is not set | 494 | # CONFIG_PARPORT is not set |
| 396 | 495 | CONFIG_BLK_DEV=y | |
| 397 | # | ||
| 398 | # Plug and Play support | ||
| 399 | # | ||
| 400 | |||
| 401 | # | ||
| 402 | # Block devices | ||
| 403 | # | ||
| 404 | # CONFIG_BLK_DEV_COW_COMMON is not set | 496 | # CONFIG_BLK_DEV_COW_COMMON is not set |
| 405 | CONFIG_BLK_DEV_LOOP=y | 497 | CONFIG_BLK_DEV_LOOP=y |
| 406 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | 498 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set |
| @@ -409,13 +501,15 @@ CONFIG_BLK_DEV_LOOP=y | |||
| 409 | CONFIG_BLK_DEV_RAM=y | 501 | CONFIG_BLK_DEV_RAM=y |
| 410 | CONFIG_BLK_DEV_RAM_COUNT=16 | 502 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 411 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 503 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
| 412 | CONFIG_BLK_DEV_INITRD=y | 504 | # CONFIG_BLK_DEV_XIP is not set |
| 413 | # CONFIG_CDROM_PKTCDVD is not set | 505 | # CONFIG_CDROM_PKTCDVD is not set |
| 414 | # CONFIG_ATA_OVER_ETH is not set | 506 | # CONFIG_ATA_OVER_ETH is not set |
| 415 | 507 | CONFIG_MISC_DEVICES=y | |
| 416 | # | 508 | # CONFIG_ATMEL_PWM is not set |
| 417 | # ATA/ATAPI/MFM/RLL support | 509 | # CONFIG_EEPROM_93CX6 is not set |
| 418 | # | 510 | # CONFIG_ATMEL_SSC is not set |
| 511 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 512 | CONFIG_HAVE_IDE=y | ||
| 419 | # CONFIG_IDE is not set | 513 | # CONFIG_IDE is not set |
| 420 | 514 | ||
| 421 | # | 515 | # |
| @@ -423,6 +517,9 @@ CONFIG_BLK_DEV_INITRD=y | |||
| 423 | # | 517 | # |
| 424 | # CONFIG_RAID_ATTRS is not set | 518 | # CONFIG_RAID_ATTRS is not set |
| 425 | CONFIG_SCSI=y | 519 | CONFIG_SCSI=y |
| 520 | CONFIG_SCSI_DMA=y | ||
| 521 | # CONFIG_SCSI_TGT is not set | ||
| 522 | # CONFIG_SCSI_NETLINK is not set | ||
| 426 | CONFIG_SCSI_PROC_FS=y | 523 | CONFIG_SCSI_PROC_FS=y |
| 427 | 524 | ||
| 428 | # | 525 | # |
| @@ -441,114 +538,78 @@ CONFIG_SCSI_PROC_FS=y | |||
| 441 | # CONFIG_SCSI_MULTI_LUN is not set | 538 | # CONFIG_SCSI_MULTI_LUN is not set |
| 442 | # CONFIG_SCSI_CONSTANTS is not set | 539 | # CONFIG_SCSI_CONSTANTS is not set |
| 443 | # CONFIG_SCSI_LOGGING is not set | 540 | # CONFIG_SCSI_LOGGING is not set |
| 541 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 542 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 444 | 543 | ||
| 445 | # | 544 | # |
| 446 | # SCSI Transport Attributes | 545 | # SCSI Transports |
| 447 | # | 546 | # |
| 448 | # CONFIG_SCSI_SPI_ATTRS is not set | 547 | # CONFIG_SCSI_SPI_ATTRS is not set |
| 449 | # CONFIG_SCSI_FC_ATTRS is not set | 548 | # CONFIG_SCSI_FC_ATTRS is not set |
| 450 | # CONFIG_SCSI_ISCSI_ATTRS is not set | 549 | # CONFIG_SCSI_ISCSI_ATTRS is not set |
| 451 | # CONFIG_SCSI_SAS_ATTRS is not set | 550 | # CONFIG_SCSI_SAS_LIBSAS is not set |
| 452 | 551 | # CONFIG_SCSI_SRP_ATTRS is not set | |
| 453 | # | 552 | CONFIG_SCSI_LOWLEVEL=y |
| 454 | # SCSI low-level drivers | ||
| 455 | # | ||
| 456 | # CONFIG_ISCSI_TCP is not set | 553 | # CONFIG_ISCSI_TCP is not set |
| 457 | # CONFIG_SCSI_SATA is not set | ||
| 458 | # CONFIG_SCSI_DEBUG is not set | 554 | # CONFIG_SCSI_DEBUG is not set |
| 459 | 555 | # CONFIG_SCSI_LOWLEVEL_PCMCIA is not set | |
| 460 | # | 556 | # CONFIG_ATA is not set |
| 461 | # PCMCIA SCSI adapter support | ||
| 462 | # | ||
| 463 | # CONFIG_PCMCIA_AHA152X is not set | ||
| 464 | # CONFIG_PCMCIA_FDOMAIN is not set | ||
| 465 | # CONFIG_PCMCIA_NINJA_SCSI is not set | ||
| 466 | # CONFIG_PCMCIA_QLOGIC is not set | ||
| 467 | # CONFIG_PCMCIA_SYM53C500 is not set | ||
| 468 | |||
| 469 | # | ||
| 470 | # Multi-device support (RAID and LVM) | ||
| 471 | # | ||
| 472 | # CONFIG_MD is not set | 557 | # CONFIG_MD is not set |
| 473 | |||
| 474 | # | ||
| 475 | # Fusion MPT device support | ||
| 476 | # | ||
| 477 | # CONFIG_FUSION is not set | ||
| 478 | |||
| 479 | # | ||
| 480 | # IEEE 1394 (FireWire) support | ||
| 481 | # | ||
| 482 | |||
| 483 | # | ||
| 484 | # I2O device support | ||
| 485 | # | ||
| 486 | |||
| 487 | # | ||
| 488 | # Network device support | ||
| 489 | # | ||
| 490 | CONFIG_NETDEVICES=y | 558 | CONFIG_NETDEVICES=y |
| 559 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 491 | # CONFIG_DUMMY is not set | 560 | # CONFIG_DUMMY is not set |
| 492 | # CONFIG_BONDING is not set | 561 | # CONFIG_BONDING is not set |
| 562 | # CONFIG_MACVLAN is not set | ||
| 493 | # CONFIG_EQUALIZER is not set | 563 | # CONFIG_EQUALIZER is not set |
| 494 | # CONFIG_TUN is not set | 564 | # CONFIG_TUN is not set |
| 495 | 565 | # CONFIG_VETH is not set | |
| 496 | # | ||
| 497 | # PHY device support | ||
| 498 | # | ||
| 499 | # CONFIG_PHYLIB is not set | 566 | # CONFIG_PHYLIB is not set |
| 500 | |||
| 501 | # | ||
| 502 | # Ethernet (10 or 100Mbit) | ||
| 503 | # | ||
| 504 | CONFIG_NET_ETHERNET=y | 567 | CONFIG_NET_ETHERNET=y |
| 505 | CONFIG_MII=y | 568 | CONFIG_MII=y |
| 506 | CONFIG_ARM_AT91_ETHER=y | 569 | CONFIG_ARM_AT91_ETHER=y |
| 570 | # CONFIG_AX88796 is not set | ||
| 507 | # CONFIG_SMC91X is not set | 571 | # CONFIG_SMC91X is not set |
| 572 | # CONFIG_SMSC911X is not set | ||
| 508 | # CONFIG_DM9000 is not set | 573 | # CONFIG_DM9000 is not set |
| 574 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 575 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 576 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 577 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 578 | # CONFIG_B44 is not set | ||
| 579 | # CONFIG_CS89x0 is not set | ||
| 580 | CONFIG_NETDEV_1000=y | ||
| 581 | # CONFIG_E1000E_ENABLED is not set | ||
| 582 | CONFIG_NETDEV_10000=y | ||
| 509 | 583 | ||
| 510 | # | 584 | # |
| 511 | # Ethernet (1000 Mbit) | 585 | # Wireless LAN |
| 512 | # | 586 | # |
| 587 | # CONFIG_WLAN_PRE80211 is not set | ||
| 588 | # CONFIG_WLAN_80211 is not set | ||
| 513 | 589 | ||
| 514 | # | 590 | # |
| 515 | # Ethernet (10000 Mbit) | 591 | # USB Network Adapters |
| 516 | # | ||
| 517 | |||
| 518 | # | ||
| 519 | # Token Ring devices | ||
| 520 | # | ||
| 521 | |||
| 522 | # | ||
| 523 | # Wireless LAN (non-hamradio) | ||
| 524 | # | ||
| 525 | # CONFIG_NET_RADIO is not set | ||
| 526 | |||
| 527 | # | ||
| 528 | # PCMCIA network device support | ||
| 529 | # | 592 | # |
| 593 | # CONFIG_USB_CATC is not set | ||
| 594 | # CONFIG_USB_KAWETH is not set | ||
| 595 | # CONFIG_USB_PEGASUS is not set | ||
| 596 | # CONFIG_USB_RTL8150 is not set | ||
| 597 | # CONFIG_USB_USBNET is not set | ||
| 530 | # CONFIG_NET_PCMCIA is not set | 598 | # CONFIG_NET_PCMCIA is not set |
| 531 | |||
| 532 | # | ||
| 533 | # Wan interfaces | ||
| 534 | # | ||
| 535 | # CONFIG_WAN is not set | 599 | # CONFIG_WAN is not set |
| 536 | # CONFIG_PPP is not set | 600 | # CONFIG_PPP is not set |
| 537 | # CONFIG_SLIP is not set | 601 | # CONFIG_SLIP is not set |
| 538 | # CONFIG_SHAPER is not set | ||
| 539 | # CONFIG_NETCONSOLE is not set | 602 | # CONFIG_NETCONSOLE is not set |
| 540 | # CONFIG_NETPOLL is not set | 603 | # CONFIG_NETPOLL is not set |
| 541 | # CONFIG_NET_POLL_CONTROLLER is not set | 604 | # CONFIG_NET_POLL_CONTROLLER is not set |
| 542 | |||
| 543 | # | ||
| 544 | # ISDN subsystem | ||
| 545 | # | ||
| 546 | # CONFIG_ISDN is not set | 605 | # CONFIG_ISDN is not set |
| 547 | 606 | ||
| 548 | # | 607 | # |
| 549 | # Input device support | 608 | # Input device support |
| 550 | # | 609 | # |
| 551 | CONFIG_INPUT=y | 610 | CONFIG_INPUT=y |
| 611 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 612 | # CONFIG_INPUT_POLLDEV is not set | ||
| 552 | 613 | ||
| 553 | # | 614 | # |
| 554 | # Userland interfaces | 615 | # Userland interfaces |
| @@ -558,7 +619,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y | |||
| 558 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | 619 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 |
| 559 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | 620 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 |
| 560 | # CONFIG_INPUT_JOYDEV is not set | 621 | # CONFIG_INPUT_JOYDEV is not set |
| 561 | # CONFIG_INPUT_TSDEV is not set | ||
| 562 | # CONFIG_INPUT_EVDEV is not set | 622 | # CONFIG_INPUT_EVDEV is not set |
| 563 | # CONFIG_INPUT_EVBUG is not set | 623 | # CONFIG_INPUT_EVBUG is not set |
| 564 | 624 | ||
| @@ -568,6 +628,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | |||
| 568 | # CONFIG_INPUT_KEYBOARD is not set | 628 | # CONFIG_INPUT_KEYBOARD is not set |
| 569 | # CONFIG_INPUT_MOUSE is not set | 629 | # CONFIG_INPUT_MOUSE is not set |
| 570 | # CONFIG_INPUT_JOYSTICK is not set | 630 | # CONFIG_INPUT_JOYSTICK is not set |
| 631 | # CONFIG_INPUT_TABLET is not set | ||
| 571 | # CONFIG_INPUT_TOUCHSCREEN is not set | 632 | # CONFIG_INPUT_TOUCHSCREEN is not set |
| 572 | # CONFIG_INPUT_MISC is not set | 633 | # CONFIG_INPUT_MISC is not set |
| 573 | 634 | ||
| @@ -583,6 +644,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | |||
| 583 | CONFIG_VT=y | 644 | CONFIG_VT=y |
| 584 | CONFIG_VT_CONSOLE=y | 645 | CONFIG_VT_CONSOLE=y |
| 585 | CONFIG_HW_CONSOLE=y | 646 | CONFIG_HW_CONSOLE=y |
| 647 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 586 | # CONFIG_SERIAL_NONSTANDARD is not set | 648 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 587 | 649 | ||
| 588 | # | 650 | # |
| @@ -595,64 +657,29 @@ CONFIG_HW_CONSOLE=y | |||
| 595 | # | 657 | # |
| 596 | CONFIG_SERIAL_ATMEL=y | 658 | CONFIG_SERIAL_ATMEL=y |
| 597 | CONFIG_SERIAL_ATMEL_CONSOLE=y | 659 | CONFIG_SERIAL_ATMEL_CONSOLE=y |
| 660 | CONFIG_SERIAL_ATMEL_PDC=y | ||
| 598 | # CONFIG_SERIAL_ATMEL_TTYAT is not set | 661 | # CONFIG_SERIAL_ATMEL_TTYAT is not set |
| 599 | CONFIG_SERIAL_CORE=y | 662 | CONFIG_SERIAL_CORE=y |
| 600 | CONFIG_SERIAL_CORE_CONSOLE=y | 663 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 601 | CONFIG_UNIX98_PTYS=y | 664 | CONFIG_UNIX98_PTYS=y |
| 602 | CONFIG_LEGACY_PTYS=y | 665 | CONFIG_LEGACY_PTYS=y |
| 603 | CONFIG_LEGACY_PTY_COUNT=256 | 666 | CONFIG_LEGACY_PTY_COUNT=256 |
| 604 | |||
| 605 | # | ||
| 606 | # IPMI | ||
| 607 | # | ||
| 608 | # CONFIG_IPMI_HANDLER is not set | 667 | # CONFIG_IPMI_HANDLER is not set |
| 609 | 668 | CONFIG_HW_RANDOM=m | |
| 610 | # | ||
| 611 | # Watchdog Cards | ||
| 612 | # | ||
| 613 | CONFIG_WATCHDOG=y | ||
| 614 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 615 | |||
| 616 | # | ||
| 617 | # Watchdog Device Drivers | ||
| 618 | # | ||
| 619 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 620 | CONFIG_AT91RM9200_WATCHDOG=y | ||
| 621 | |||
| 622 | # | ||
| 623 | # USB-based Watchdog Cards | ||
| 624 | # | ||
| 625 | # CONFIG_USBPCWATCHDOG is not set | ||
| 626 | # CONFIG_NVRAM is not set | 669 | # CONFIG_NVRAM is not set |
| 627 | CONFIG_RTC=y | ||
| 628 | # CONFIG_AT91RM9200_RTC is not set | ||
| 629 | # CONFIG_DTLK is not set | ||
| 630 | # CONFIG_R3964 is not set | 670 | # CONFIG_R3964 is not set |
| 631 | 671 | ||
| 632 | # | 672 | # |
| 633 | # Ftape, the floppy tape device driver | ||
| 634 | # | ||
| 635 | |||
| 636 | # | ||
| 637 | # PCMCIA character devices | 673 | # PCMCIA character devices |
| 638 | # | 674 | # |
| 639 | # CONFIG_SYNCLINK_CS is not set | 675 | # CONFIG_SYNCLINK_CS is not set |
| 640 | # CONFIG_CARDMAN_4000 is not set | 676 | # CONFIG_CARDMAN_4000 is not set |
| 641 | # CONFIG_CARDMAN_4040 is not set | 677 | # CONFIG_CARDMAN_4040 is not set |
| 678 | # CONFIG_IPWIRELESS is not set | ||
| 642 | # CONFIG_RAW_DRIVER is not set | 679 | # CONFIG_RAW_DRIVER is not set |
| 643 | |||
| 644 | # | ||
| 645 | # TPM devices | ||
| 646 | # | ||
| 647 | # CONFIG_TCG_TPM is not set | 680 | # CONFIG_TCG_TPM is not set |
| 648 | # CONFIG_TELCLOCK is not set | ||
| 649 | CONFIG_AT91_SPI=y | ||
| 650 | CONFIG_AT91_SPIDEV=y | ||
| 651 | |||
| 652 | # | ||
| 653 | # I2C support | ||
| 654 | # | ||
| 655 | CONFIG_I2C=y | 681 | CONFIG_I2C=y |
| 682 | CONFIG_I2C_BOARDINFO=y | ||
| 656 | CONFIG_I2C_CHARDEV=y | 683 | CONFIG_I2C_CHARDEV=y |
| 657 | 684 | ||
| 658 | # | 685 | # |
| @@ -665,43 +692,53 @@ CONFIG_I2C_CHARDEV=y | |||
| 665 | # | 692 | # |
| 666 | # I2C Hardware Bus support | 693 | # I2C Hardware Bus support |
| 667 | # | 694 | # |
| 668 | CONFIG_I2C_AT91=y | 695 | # CONFIG_I2C_GPIO is not set |
| 696 | # CONFIG_I2C_OCORES is not set | ||
| 669 | # CONFIG_I2C_PARPORT_LIGHT is not set | 697 | # CONFIG_I2C_PARPORT_LIGHT is not set |
| 698 | # CONFIG_I2C_SIMTEC is not set | ||
| 699 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 670 | # CONFIG_I2C_STUB is not set | 700 | # CONFIG_I2C_STUB is not set |
| 671 | # CONFIG_I2C_PCA_ISA is not set | 701 | # CONFIG_I2C_TINY_USB is not set |
| 672 | 702 | ||
| 673 | # | 703 | # |
| 674 | # Miscellaneous I2C Chip support | 704 | # Miscellaneous I2C Chip support |
| 675 | # | 705 | # |
| 676 | # CONFIG_SENSORS_DS1337 is not set | 706 | # CONFIG_DS1682 is not set |
| 677 | # CONFIG_SENSORS_DS1374 is not set | ||
| 678 | # CONFIG_SENSORS_EEPROM is not set | 707 | # CONFIG_SENSORS_EEPROM is not set |
| 679 | # CONFIG_SENSORS_PCF8574 is not set | 708 | # CONFIG_SENSORS_PCF8574 is not set |
| 680 | # CONFIG_SENSORS_PCA9539 is not set | 709 | # CONFIG_PCF8575 is not set |
| 681 | # CONFIG_SENSORS_PCF8591 is not set | 710 | # CONFIG_SENSORS_PCF8591 is not set |
| 682 | # CONFIG_SENSORS_RTC8564 is not set | 711 | # CONFIG_TPS65010 is not set |
| 683 | # CONFIG_SENSORS_MAX6875 is not set | 712 | # CONFIG_SENSORS_MAX6875 is not set |
| 684 | # CONFIG_RTC_X1205_I2C is not set | 713 | # CONFIG_SENSORS_TSL2550 is not set |
| 685 | # CONFIG_I2C_DEBUG_CORE is not set | 714 | # CONFIG_I2C_DEBUG_CORE is not set |
| 686 | # CONFIG_I2C_DEBUG_ALGO is not set | 715 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 687 | # CONFIG_I2C_DEBUG_BUS is not set | 716 | # CONFIG_I2C_DEBUG_BUS is not set |
| 688 | # CONFIG_I2C_DEBUG_CHIP is not set | 717 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 689 | 718 | ||
| 690 | # | 719 | # |
| 691 | # Hardware Monitoring support | 720 | # SPI support |
| 692 | # | 721 | # |
| 722 | # CONFIG_SPI is not set | ||
| 723 | # CONFIG_SPI_MASTER is not set | ||
| 724 | # CONFIG_W1 is not set | ||
| 725 | # CONFIG_POWER_SUPPLY is not set | ||
| 693 | CONFIG_HWMON=y | 726 | CONFIG_HWMON=y |
| 694 | # CONFIG_HWMON_VID is not set | 727 | # CONFIG_HWMON_VID is not set |
| 728 | # CONFIG_SENSORS_AD7418 is not set | ||
| 695 | # CONFIG_SENSORS_ADM1021 is not set | 729 | # CONFIG_SENSORS_ADM1021 is not set |
| 696 | # CONFIG_SENSORS_ADM1025 is not set | 730 | # CONFIG_SENSORS_ADM1025 is not set |
| 697 | # CONFIG_SENSORS_ADM1026 is not set | 731 | # CONFIG_SENSORS_ADM1026 is not set |
| 732 | # CONFIG_SENSORS_ADM1029 is not set | ||
| 698 | # CONFIG_SENSORS_ADM1031 is not set | 733 | # CONFIG_SENSORS_ADM1031 is not set |
| 699 | # CONFIG_SENSORS_ADM9240 is not set | 734 | # CONFIG_SENSORS_ADM9240 is not set |
| 700 | # CONFIG_SENSORS_ASB100 is not set | 735 | # CONFIG_SENSORS_ADT7470 is not set |
| 736 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 701 | # CONFIG_SENSORS_ATXP1 is not set | 737 | # CONFIG_SENSORS_ATXP1 is not set |
| 702 | # CONFIG_SENSORS_DS1621 is not set | 738 | # CONFIG_SENSORS_DS1621 is not set |
| 703 | # CONFIG_SENSORS_FSCHER is not set | 739 | # CONFIG_SENSORS_F71805F is not set |
| 704 | # CONFIG_SENSORS_FSCPOS is not set | 740 | # CONFIG_SENSORS_F71882FG is not set |
| 741 | # CONFIG_SENSORS_F75375S is not set | ||
| 705 | # CONFIG_SENSORS_GL518SM is not set | 742 | # CONFIG_SENSORS_GL518SM is not set |
| 706 | # CONFIG_SENSORS_GL520SM is not set | 743 | # CONFIG_SENSORS_GL520SM is not set |
| 707 | # CONFIG_SENSORS_IT87 is not set | 744 | # CONFIG_SENSORS_IT87 is not set |
| @@ -715,39 +752,72 @@ CONFIG_HWMON=y | |||
| 715 | # CONFIG_SENSORS_LM87 is not set | 752 | # CONFIG_SENSORS_LM87 is not set |
| 716 | # CONFIG_SENSORS_LM90 is not set | 753 | # CONFIG_SENSORS_LM90 is not set |
| 717 | # CONFIG_SENSORS_LM92 is not set | 754 | # CONFIG_SENSORS_LM92 is not set |
| 755 | # CONFIG_SENSORS_LM93 is not set | ||
| 718 | # CONFIG_SENSORS_MAX1619 is not set | 756 | # CONFIG_SENSORS_MAX1619 is not set |
| 757 | # CONFIG_SENSORS_MAX6650 is not set | ||
| 719 | # CONFIG_SENSORS_PC87360 is not set | 758 | # CONFIG_SENSORS_PC87360 is not set |
| 759 | # CONFIG_SENSORS_PC87427 is not set | ||
| 760 | # CONFIG_SENSORS_DME1737 is not set | ||
| 720 | # CONFIG_SENSORS_SMSC47M1 is not set | 761 | # CONFIG_SENSORS_SMSC47M1 is not set |
| 762 | # CONFIG_SENSORS_SMSC47M192 is not set | ||
| 721 | # CONFIG_SENSORS_SMSC47B397 is not set | 763 | # CONFIG_SENSORS_SMSC47B397 is not set |
| 764 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 765 | # CONFIG_SENSORS_THMC50 is not set | ||
| 766 | # CONFIG_SENSORS_VT1211 is not set | ||
| 722 | # CONFIG_SENSORS_W83781D is not set | 767 | # CONFIG_SENSORS_W83781D is not set |
| 768 | # CONFIG_SENSORS_W83791D is not set | ||
| 723 | # CONFIG_SENSORS_W83792D is not set | 769 | # CONFIG_SENSORS_W83792D is not set |
| 770 | # CONFIG_SENSORS_W83793 is not set | ||
| 724 | # CONFIG_SENSORS_W83L785TS is not set | 771 | # CONFIG_SENSORS_W83L785TS is not set |
| 772 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 725 | # CONFIG_SENSORS_W83627HF is not set | 773 | # CONFIG_SENSORS_W83627HF is not set |
| 726 | # CONFIG_SENSORS_W83627EHF is not set | 774 | # CONFIG_SENSORS_W83627EHF is not set |
| 727 | # CONFIG_HWMON_DEBUG_CHIP is not set | 775 | # CONFIG_HWMON_DEBUG_CHIP is not set |
| 776 | CONFIG_WATCHDOG=y | ||
| 777 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 728 | 778 | ||
| 729 | # | 779 | # |
| 730 | # Misc devices | 780 | # Watchdog Device Drivers |
| 731 | # | 781 | # |
| 782 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 783 | CONFIG_AT91RM9200_WATCHDOG=y | ||
| 732 | 784 | ||
| 733 | # | 785 | # |
| 734 | # Multimedia Capabilities Port drivers | 786 | # USB-based Watchdog Cards |
| 735 | # | 787 | # |
| 788 | # CONFIG_USBPCWATCHDOG is not set | ||
| 736 | 789 | ||
| 737 | # | 790 | # |
| 738 | # Multimedia devices | 791 | # Sonics Silicon Backplane |
| 739 | # | 792 | # |
| 740 | # CONFIG_VIDEO_DEV is not set | 793 | CONFIG_SSB_POSSIBLE=y |
| 794 | # CONFIG_SSB is not set | ||
| 741 | 795 | ||
| 742 | # | 796 | # |
| 743 | # Digital Video Broadcasting Devices | 797 | # Multifunction device drivers |
| 744 | # | 798 | # |
| 745 | # CONFIG_DVB is not set | 799 | # CONFIG_MFD_SM501 is not set |
| 800 | # CONFIG_MFD_ASIC3 is not set | ||
| 801 | |||
| 802 | # | ||
| 803 | # Multimedia devices | ||
| 804 | # | ||
| 805 | # CONFIG_VIDEO_DEV is not set | ||
| 806 | # CONFIG_DVB_CORE is not set | ||
| 807 | # CONFIG_DAB is not set | ||
| 746 | 808 | ||
| 747 | # | 809 | # |
| 748 | # Graphics support | 810 | # Graphics support |
| 749 | # | 811 | # |
| 812 | # CONFIG_VGASTATE is not set | ||
| 813 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 750 | # CONFIG_FB is not set | 814 | # CONFIG_FB is not set |
| 815 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 816 | |||
| 817 | # | ||
| 818 | # Display device support | ||
| 819 | # | ||
| 820 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 751 | 821 | ||
| 752 | # | 822 | # |
| 753 | # Console display driver support | 823 | # Console display driver support |
| @@ -759,20 +829,34 @@ CONFIG_DUMMY_CONSOLE=y | |||
| 759 | # Sound | 829 | # Sound |
| 760 | # | 830 | # |
| 761 | # CONFIG_SOUND is not set | 831 | # CONFIG_SOUND is not set |
| 832 | CONFIG_HID_SUPPORT=y | ||
| 833 | CONFIG_HID=y | ||
| 834 | CONFIG_HID_DEBUG=y | ||
| 835 | # CONFIG_HIDRAW is not set | ||
| 762 | 836 | ||
| 763 | # | 837 | # |
| 764 | # USB support | 838 | # USB Input Devices |
| 765 | # | 839 | # |
| 840 | # CONFIG_USB_HID is not set | ||
| 841 | |||
| 842 | # | ||
| 843 | # USB HID Boot Protocol drivers | ||
| 844 | # | ||
| 845 | # CONFIG_USB_KBD is not set | ||
| 846 | # CONFIG_USB_MOUSE is not set | ||
| 847 | CONFIG_USB_SUPPORT=y | ||
| 766 | CONFIG_USB_ARCH_HAS_HCD=y | 848 | CONFIG_USB_ARCH_HAS_HCD=y |
| 767 | CONFIG_USB_ARCH_HAS_OHCI=y | 849 | CONFIG_USB_ARCH_HAS_OHCI=y |
| 850 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 768 | CONFIG_USB=y | 851 | CONFIG_USB=y |
| 769 | CONFIG_USB_DEBUG=y | 852 | CONFIG_USB_DEBUG=y |
| 853 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 770 | 854 | ||
| 771 | # | 855 | # |
| 772 | # Miscellaneous USB options | 856 | # Miscellaneous USB options |
| 773 | # | 857 | # |
| 774 | CONFIG_USB_DEVICEFS=y | 858 | CONFIG_USB_DEVICEFS=y |
| 775 | # CONFIG_USB_BANDWIDTH is not set | 859 | CONFIG_USB_DEVICE_CLASS=y |
| 776 | # CONFIG_USB_DYNAMIC_MINORS is not set | 860 | # CONFIG_USB_DYNAMIC_MINORS is not set |
| 777 | # CONFIG_USB_OTG is not set | 861 | # CONFIG_USB_OTG is not set |
| 778 | 862 | ||
| @@ -781,9 +865,11 @@ CONFIG_USB_DEVICEFS=y | |||
| 781 | # | 865 | # |
| 782 | # CONFIG_USB_ISP116X_HCD is not set | 866 | # CONFIG_USB_ISP116X_HCD is not set |
| 783 | CONFIG_USB_OHCI_HCD=y | 867 | CONFIG_USB_OHCI_HCD=y |
| 784 | # CONFIG_USB_OHCI_BIG_ENDIAN is not set | 868 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set |
| 869 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 785 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | 870 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y |
| 786 | # CONFIG_USB_SL811_HCD is not set | 871 | # CONFIG_USB_SL811_HCD is not set |
| 872 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 787 | 873 | ||
| 788 | # | 874 | # |
| 789 | # USB Device Class drivers | 875 | # USB Device Class drivers |
| @@ -802,80 +888,42 @@ CONFIG_USB_STORAGE=y | |||
| 802 | # CONFIG_USB_STORAGE_DEBUG is not set | 888 | # CONFIG_USB_STORAGE_DEBUG is not set |
| 803 | # CONFIG_USB_STORAGE_DATAFAB is not set | 889 | # CONFIG_USB_STORAGE_DATAFAB is not set |
| 804 | # CONFIG_USB_STORAGE_FREECOM is not set | 890 | # CONFIG_USB_STORAGE_FREECOM is not set |
| 891 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 805 | # CONFIG_USB_STORAGE_DPCM is not set | 892 | # CONFIG_USB_STORAGE_DPCM is not set |
| 806 | # CONFIG_USB_STORAGE_USBAT is not set | 893 | # CONFIG_USB_STORAGE_USBAT is not set |
| 807 | # CONFIG_USB_STORAGE_SDDR09 is not set | 894 | # CONFIG_USB_STORAGE_SDDR09 is not set |
| 808 | # CONFIG_USB_STORAGE_SDDR55 is not set | 895 | # CONFIG_USB_STORAGE_SDDR55 is not set |
| 809 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | 896 | # CONFIG_USB_STORAGE_JUMPSHOT is not set |
| 810 | 897 | # CONFIG_USB_STORAGE_ALAUDA is not set | |
| 811 | # | 898 | # CONFIG_USB_STORAGE_KARMA is not set |
| 812 | # USB Input Devices | 899 | # CONFIG_USB_LIBUSUAL is not set |
| 813 | # | ||
| 814 | # CONFIG_USB_HID is not set | ||
| 815 | |||
| 816 | # | ||
| 817 | # USB HID Boot Protocol drivers | ||
| 818 | # | ||
| 819 | # CONFIG_USB_KBD is not set | ||
| 820 | # CONFIG_USB_MOUSE is not set | ||
| 821 | # CONFIG_USB_AIPTEK is not set | ||
| 822 | # CONFIG_USB_WACOM is not set | ||
| 823 | # CONFIG_USB_ACECAD is not set | ||
| 824 | # CONFIG_USB_KBTAB is not set | ||
| 825 | # CONFIG_USB_POWERMATE is not set | ||
| 826 | # CONFIG_USB_MTOUCH is not set | ||
| 827 | # CONFIG_USB_ITMTOUCH is not set | ||
| 828 | # CONFIG_USB_EGALAX is not set | ||
| 829 | # CONFIG_USB_YEALINK is not set | ||
| 830 | # CONFIG_USB_XPAD is not set | ||
| 831 | # CONFIG_USB_ATI_REMOTE is not set | ||
| 832 | # CONFIG_USB_KEYSPAN_REMOTE is not set | ||
| 833 | # CONFIG_USB_APPLETOUCH is not set | ||
| 834 | 900 | ||
| 835 | # | 901 | # |
| 836 | # USB Imaging devices | 902 | # USB Imaging devices |
| 837 | # | 903 | # |
| 838 | # CONFIG_USB_MDC800 is not set | 904 | # CONFIG_USB_MDC800 is not set |
| 839 | # CONFIG_USB_MICROTEK is not set | 905 | # CONFIG_USB_MICROTEK is not set |
| 840 | |||
| 841 | # | ||
| 842 | # USB Multimedia devices | ||
| 843 | # | ||
| 844 | # CONFIG_USB_DABUSB is not set | ||
| 845 | |||
| 846 | # | ||
| 847 | # Video4Linux support is needed for USB Multimedia device support | ||
| 848 | # | ||
| 849 | |||
| 850 | # | ||
| 851 | # USB Network Adapters | ||
| 852 | # | ||
| 853 | # CONFIG_USB_CATC is not set | ||
| 854 | # CONFIG_USB_KAWETH is not set | ||
| 855 | # CONFIG_USB_PEGASUS is not set | ||
| 856 | # CONFIG_USB_RTL8150 is not set | ||
| 857 | # CONFIG_USB_USBNET is not set | ||
| 858 | CONFIG_USB_MON=y | 906 | CONFIG_USB_MON=y |
| 859 | 907 | ||
| 860 | # | 908 | # |
| 861 | # USB port drivers | 909 | # USB port drivers |
| 862 | # | 910 | # |
| 863 | |||
| 864 | # | ||
| 865 | # USB Serial Converter support | ||
| 866 | # | ||
| 867 | CONFIG_USB_SERIAL=y | 911 | CONFIG_USB_SERIAL=y |
| 868 | CONFIG_USB_SERIAL_CONSOLE=y | 912 | CONFIG_USB_SERIAL_CONSOLE=y |
| 913 | CONFIG_USB_EZUSB=y | ||
| 869 | CONFIG_USB_SERIAL_GENERIC=y | 914 | CONFIG_USB_SERIAL_GENERIC=y |
| 915 | # CONFIG_USB_SERIAL_AIRCABLE is not set | ||
| 870 | # CONFIG_USB_SERIAL_AIRPRIME is not set | 916 | # CONFIG_USB_SERIAL_AIRPRIME is not set |
| 871 | # CONFIG_USB_SERIAL_ANYDATA is not set | 917 | # CONFIG_USB_SERIAL_ARK3116 is not set |
| 872 | # CONFIG_USB_SERIAL_BELKIN is not set | 918 | # CONFIG_USB_SERIAL_BELKIN is not set |
| 919 | # CONFIG_USB_SERIAL_CH341 is not set | ||
| 873 | # CONFIG_USB_SERIAL_WHITEHEAT is not set | 920 | # CONFIG_USB_SERIAL_WHITEHEAT is not set |
| 874 | # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set | 921 | # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set |
| 875 | # CONFIG_USB_SERIAL_CP2101 is not set | 922 | # CONFIG_USB_SERIAL_CP2101 is not set |
| 876 | # CONFIG_USB_SERIAL_CYPRESS_M8 is not set | 923 | # CONFIG_USB_SERIAL_CYPRESS_M8 is not set |
| 877 | # CONFIG_USB_SERIAL_EMPEG is not set | 924 | # CONFIG_USB_SERIAL_EMPEG is not set |
| 878 | CONFIG_USB_SERIAL_FTDI_SIO=y | 925 | CONFIG_USB_SERIAL_FTDI_SIO=y |
| 926 | # CONFIG_USB_SERIAL_FUNSOFT is not set | ||
| 879 | # CONFIG_USB_SERIAL_VISOR is not set | 927 | # CONFIG_USB_SERIAL_VISOR is not set |
| 880 | # CONFIG_USB_SERIAL_IPAQ is not set | 928 | # CONFIG_USB_SERIAL_IPAQ is not set |
| 881 | # CONFIG_USB_SERIAL_IR is not set | 929 | # CONFIG_USB_SERIAL_IR is not set |
| @@ -883,6 +931,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=y | |||
| 883 | # CONFIG_USB_SERIAL_EDGEPORT_TI is not set | 931 | # CONFIG_USB_SERIAL_EDGEPORT_TI is not set |
| 884 | # CONFIG_USB_SERIAL_GARMIN is not set | 932 | # CONFIG_USB_SERIAL_GARMIN is not set |
| 885 | # CONFIG_USB_SERIAL_IPW is not set | 933 | # CONFIG_USB_SERIAL_IPW is not set |
| 934 | # CONFIG_USB_SERIAL_IUU is not set | ||
| 886 | # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set | 935 | # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set |
| 887 | CONFIG_USB_SERIAL_KEYSPAN=y | 936 | CONFIG_USB_SERIAL_KEYSPAN=y |
| 888 | CONFIG_USB_SERIAL_KEYSPAN_MPR=y | 937 | CONFIG_USB_SERIAL_KEYSPAN_MPR=y |
| @@ -900,46 +949,66 @@ CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y | |||
| 900 | # CONFIG_USB_SERIAL_KLSI is not set | 949 | # CONFIG_USB_SERIAL_KLSI is not set |
| 901 | # CONFIG_USB_SERIAL_KOBIL_SCT is not set | 950 | # CONFIG_USB_SERIAL_KOBIL_SCT is not set |
| 902 | CONFIG_USB_SERIAL_MCT_U232=y | 951 | CONFIG_USB_SERIAL_MCT_U232=y |
| 952 | # CONFIG_USB_SERIAL_MOS7720 is not set | ||
| 953 | # CONFIG_USB_SERIAL_MOS7840 is not set | ||
| 954 | # CONFIG_USB_SERIAL_NAVMAN is not set | ||
| 903 | # CONFIG_USB_SERIAL_PL2303 is not set | 955 | # CONFIG_USB_SERIAL_PL2303 is not set |
| 956 | # CONFIG_USB_SERIAL_OTI6858 is not set | ||
| 904 | # CONFIG_USB_SERIAL_HP4X is not set | 957 | # CONFIG_USB_SERIAL_HP4X is not set |
| 905 | # CONFIG_USB_SERIAL_SAFE is not set | 958 | # CONFIG_USB_SERIAL_SAFE is not set |
| 959 | # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set | ||
| 906 | # CONFIG_USB_SERIAL_TI is not set | 960 | # CONFIG_USB_SERIAL_TI is not set |
| 907 | # CONFIG_USB_SERIAL_CYBERJACK is not set | 961 | # CONFIG_USB_SERIAL_CYBERJACK is not set |
| 908 | # CONFIG_USB_SERIAL_XIRCOM is not set | 962 | # CONFIG_USB_SERIAL_XIRCOM is not set |
| 909 | # CONFIG_USB_SERIAL_OPTION is not set | 963 | # CONFIG_USB_SERIAL_OPTION is not set |
| 910 | # CONFIG_USB_SERIAL_OMNINET is not set | 964 | # CONFIG_USB_SERIAL_OMNINET is not set |
| 911 | CONFIG_USB_EZUSB=y | 965 | # CONFIG_USB_SERIAL_DEBUG is not set |
| 912 | 966 | ||
| 913 | # | 967 | # |
| 914 | # USB Miscellaneous drivers | 968 | # USB Miscellaneous drivers |
| 915 | # | 969 | # |
| 916 | # CONFIG_USB_EMI62 is not set | 970 | # CONFIG_USB_EMI62 is not set |
| 917 | # CONFIG_USB_EMI26 is not set | 971 | # CONFIG_USB_EMI26 is not set |
| 972 | # CONFIG_USB_ADUTUX is not set | ||
| 918 | # CONFIG_USB_AUERSWALD is not set | 973 | # CONFIG_USB_AUERSWALD is not set |
| 919 | # CONFIG_USB_RIO500 is not set | 974 | # CONFIG_USB_RIO500 is not set |
| 920 | # CONFIG_USB_LEGOTOWER is not set | 975 | # CONFIG_USB_LEGOTOWER is not set |
| 921 | # CONFIG_USB_LCD is not set | 976 | # CONFIG_USB_LCD is not set |
| 977 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 922 | # CONFIG_USB_LED is not set | 978 | # CONFIG_USB_LED is not set |
| 979 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 923 | # CONFIG_USB_CYTHERM is not set | 980 | # CONFIG_USB_CYTHERM is not set |
| 924 | # CONFIG_USB_PHIDGETKIT is not set | 981 | # CONFIG_USB_PHIDGET is not set |
| 925 | # CONFIG_USB_PHIDGETSERVO is not set | ||
| 926 | # CONFIG_USB_IDMOUSE is not set | 982 | # CONFIG_USB_IDMOUSE is not set |
| 983 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 984 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 927 | # CONFIG_USB_LD is not set | 985 | # CONFIG_USB_LD is not set |
| 986 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 987 | # CONFIG_USB_IOWARRIOR is not set | ||
| 928 | # CONFIG_USB_TEST is not set | 988 | # CONFIG_USB_TEST is not set |
| 989 | # CONFIG_USB_GADGET is not set | ||
| 990 | # CONFIG_MMC is not set | ||
| 991 | CONFIG_NEW_LEDS=y | ||
| 992 | CONFIG_LEDS_CLASS=y | ||
| 929 | 993 | ||
| 930 | # | 994 | # |
| 931 | # USB DSL modem support | 995 | # LED drivers |
| 932 | # | 996 | # |
| 997 | CONFIG_LEDS_GPIO=y | ||
| 933 | 998 | ||
| 934 | # | 999 | # |
| 935 | # USB Gadget Support | 1000 | # LED Triggers |
| 936 | # | 1001 | # |
| 937 | # CONFIG_USB_GADGET is not set | 1002 | CONFIG_LEDS_TRIGGERS=y |
| 1003 | # CONFIG_LEDS_TRIGGER_TIMER is not set | ||
| 1004 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 1005 | CONFIG_RTC_LIB=y | ||
| 1006 | # CONFIG_RTC_CLASS is not set | ||
| 938 | 1007 | ||
| 939 | # | 1008 | # |
| 940 | # MMC/SD Card support | 1009 | # Userspace I/O |
| 941 | # | 1010 | # |
| 942 | # CONFIG_MMC is not set | 1011 | # CONFIG_UIO is not set |
| 943 | 1012 | ||
| 944 | # | 1013 | # |
| 945 | # File systems | 1014 | # File systems |
| @@ -948,16 +1017,17 @@ CONFIG_EXT2_FS=y | |||
| 948 | # CONFIG_EXT2_FS_XATTR is not set | 1017 | # CONFIG_EXT2_FS_XATTR is not set |
| 949 | # CONFIG_EXT2_FS_XIP is not set | 1018 | # CONFIG_EXT2_FS_XIP is not set |
| 950 | # CONFIG_EXT3_FS is not set | 1019 | # CONFIG_EXT3_FS is not set |
| 951 | # CONFIG_JBD is not set | 1020 | # CONFIG_EXT4DEV_FS is not set |
| 952 | # CONFIG_REISERFS_FS is not set | 1021 | # CONFIG_REISERFS_FS is not set |
| 953 | # CONFIG_JFS_FS is not set | 1022 | # CONFIG_JFS_FS is not set |
| 954 | # CONFIG_FS_POSIX_ACL is not set | 1023 | # CONFIG_FS_POSIX_ACL is not set |
| 955 | # CONFIG_XFS_FS is not set | 1024 | # CONFIG_XFS_FS is not set |
| 956 | # CONFIG_MINIX_FS is not set | 1025 | # CONFIG_GFS2_FS is not set |
| 957 | # CONFIG_ROMFS_FS is not set | 1026 | # CONFIG_OCFS2_FS is not set |
| 1027 | CONFIG_DNOTIFY=y | ||
| 958 | CONFIG_INOTIFY=y | 1028 | CONFIG_INOTIFY=y |
| 1029 | CONFIG_INOTIFY_USER=y | ||
| 959 | # CONFIG_QUOTA is not set | 1030 | # CONFIG_QUOTA is not set |
| 960 | CONFIG_DNOTIFY=y | ||
| 961 | # CONFIG_AUTOFS_FS is not set | 1031 | # CONFIG_AUTOFS_FS is not set |
| 962 | # CONFIG_AUTOFS4_FS is not set | 1032 | # CONFIG_AUTOFS4_FS is not set |
| 963 | # CONFIG_FUSE_FS is not set | 1033 | # CONFIG_FUSE_FS is not set |
| @@ -979,11 +1049,12 @@ CONFIG_DNOTIFY=y | |||
| 979 | # Pseudo filesystems | 1049 | # Pseudo filesystems |
| 980 | # | 1050 | # |
| 981 | CONFIG_PROC_FS=y | 1051 | CONFIG_PROC_FS=y |
| 1052 | CONFIG_PROC_SYSCTL=y | ||
| 982 | CONFIG_SYSFS=y | 1053 | CONFIG_SYSFS=y |
| 983 | CONFIG_TMPFS=y | 1054 | CONFIG_TMPFS=y |
| 1055 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 984 | # CONFIG_HUGETLB_PAGE is not set | 1056 | # CONFIG_HUGETLB_PAGE is not set |
| 985 | CONFIG_RAMFS=y | 1057 | # CONFIG_CONFIGFS_FS is not set |
| 986 | # CONFIG_RELAYFS_FS is not set | ||
| 987 | 1058 | ||
| 988 | # | 1059 | # |
| 989 | # Miscellaneous filesystems | 1060 | # Miscellaneous filesystems |
| @@ -995,18 +1066,16 @@ CONFIG_RAMFS=y | |||
| 995 | # CONFIG_BEFS_FS is not set | 1066 | # CONFIG_BEFS_FS is not set |
| 996 | # CONFIG_BFS_FS is not set | 1067 | # CONFIG_BFS_FS is not set |
| 997 | # CONFIG_EFS_FS is not set | 1068 | # CONFIG_EFS_FS is not set |
| 998 | # CONFIG_JFFS_FS is not set | ||
| 999 | # CONFIG_JFFS2_FS is not set | 1069 | # CONFIG_JFFS2_FS is not set |
| 1000 | CONFIG_CRAMFS=y | 1070 | CONFIG_CRAMFS=y |
| 1001 | # CONFIG_VXFS_FS is not set | 1071 | # CONFIG_VXFS_FS is not set |
| 1072 | # CONFIG_MINIX_FS is not set | ||
| 1002 | # CONFIG_HPFS_FS is not set | 1073 | # CONFIG_HPFS_FS is not set |
| 1003 | # CONFIG_QNX4FS_FS is not set | 1074 | # CONFIG_QNX4FS_FS is not set |
| 1075 | # CONFIG_ROMFS_FS is not set | ||
| 1004 | # CONFIG_SYSV_FS is not set | 1076 | # CONFIG_SYSV_FS is not set |
| 1005 | # CONFIG_UFS_FS is not set | 1077 | # CONFIG_UFS_FS is not set |
| 1006 | 1078 | CONFIG_NETWORK_FILESYSTEMS=y | |
| 1007 | # | ||
| 1008 | # Network File Systems | ||
| 1009 | # | ||
| 1010 | CONFIG_NFS_FS=y | 1079 | CONFIG_NFS_FS=y |
| 1011 | CONFIG_NFS_V3=y | 1080 | CONFIG_NFS_V3=y |
| 1012 | # CONFIG_NFS_V3_ACL is not set | 1081 | # CONFIG_NFS_V3_ACL is not set |
| @@ -1019,6 +1088,7 @@ CONFIG_LOCKD_V4=y | |||
| 1019 | CONFIG_NFS_COMMON=y | 1088 | CONFIG_NFS_COMMON=y |
| 1020 | CONFIG_SUNRPC=y | 1089 | CONFIG_SUNRPC=y |
| 1021 | CONFIG_SUNRPC_GSS=y | 1090 | CONFIG_SUNRPC_GSS=y |
| 1091 | # CONFIG_SUNRPC_BIND34 is not set | ||
| 1022 | CONFIG_RPCSEC_GSS_KRB5=y | 1092 | CONFIG_RPCSEC_GSS_KRB5=y |
| 1023 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1093 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1024 | # CONFIG_SMB_FS is not set | 1094 | # CONFIG_SMB_FS is not set |
| @@ -1026,45 +1096,57 @@ CONFIG_RPCSEC_GSS_KRB5=y | |||
| 1026 | # CONFIG_NCP_FS is not set | 1096 | # CONFIG_NCP_FS is not set |
| 1027 | # CONFIG_CODA_FS is not set | 1097 | # CONFIG_CODA_FS is not set |
| 1028 | # CONFIG_AFS_FS is not set | 1098 | # CONFIG_AFS_FS is not set |
| 1029 | # CONFIG_9P_FS is not set | ||
| 1030 | 1099 | ||
| 1031 | # | 1100 | # |
| 1032 | # Partition Types | 1101 | # Partition Types |
| 1033 | # | 1102 | # |
| 1034 | # CONFIG_PARTITION_ADVANCED is not set | 1103 | # CONFIG_PARTITION_ADVANCED is not set |
| 1035 | CONFIG_MSDOS_PARTITION=y | 1104 | CONFIG_MSDOS_PARTITION=y |
| 1036 | |||
| 1037 | # | ||
| 1038 | # Native Language Support | ||
| 1039 | # | ||
| 1040 | # CONFIG_NLS is not set | 1105 | # CONFIG_NLS is not set |
| 1041 | 1106 | # CONFIG_DLM is not set | |
| 1042 | # | ||
| 1043 | # Profiling support | ||
| 1044 | # | ||
| 1045 | # CONFIG_PROFILING is not set | ||
| 1046 | 1107 | ||
| 1047 | # | 1108 | # |
| 1048 | # Kernel hacking | 1109 | # Kernel hacking |
| 1049 | # | 1110 | # |
| 1050 | # CONFIG_PRINTK_TIME is not set | 1111 | # CONFIG_PRINTK_TIME is not set |
| 1051 | CONFIG_DEBUG_KERNEL=y | 1112 | CONFIG_ENABLE_WARN_DEPRECATED=y |
| 1113 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1052 | # CONFIG_MAGIC_SYSRQ is not set | 1114 | # CONFIG_MAGIC_SYSRQ is not set |
| 1053 | CONFIG_LOG_BUF_SHIFT=14 | 1115 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1116 | # CONFIG_DEBUG_FS is not set | ||
| 1117 | # CONFIG_HEADERS_CHECK is not set | ||
| 1118 | CONFIG_DEBUG_KERNEL=y | ||
| 1119 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1054 | CONFIG_DETECT_SOFTLOCKUP=y | 1120 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1121 | CONFIG_SCHED_DEBUG=y | ||
| 1055 | # CONFIG_SCHEDSTATS is not set | 1122 | # CONFIG_SCHEDSTATS is not set |
| 1056 | # CONFIG_DEBUG_SLAB is not set | 1123 | # CONFIG_TIMER_STATS is not set |
| 1124 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 1125 | # CONFIG_SLUB_STATS is not set | ||
| 1126 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1127 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1057 | # CONFIG_DEBUG_SPINLOCK is not set | 1128 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1129 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1130 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1131 | # CONFIG_PROVE_LOCKING is not set | ||
| 1132 | # CONFIG_LOCK_STAT is not set | ||
| 1058 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1133 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1134 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1059 | # CONFIG_DEBUG_KOBJECT is not set | 1135 | # CONFIG_DEBUG_KOBJECT is not set |
| 1060 | CONFIG_DEBUG_BUGVERBOSE=y | 1136 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1061 | # CONFIG_DEBUG_INFO is not set | 1137 | # CONFIG_DEBUG_INFO is not set |
| 1062 | # CONFIG_DEBUG_FS is not set | ||
| 1063 | # CONFIG_DEBUG_VM is not set | 1138 | # CONFIG_DEBUG_VM is not set |
| 1139 | # CONFIG_DEBUG_LIST is not set | ||
| 1140 | # CONFIG_DEBUG_SG is not set | ||
| 1064 | CONFIG_FRAME_POINTER=y | 1141 | CONFIG_FRAME_POINTER=y |
| 1142 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1065 | # CONFIG_RCU_TORTURE_TEST is not set | 1143 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1144 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1145 | # CONFIG_FAULT_INJECTION is not set | ||
| 1146 | # CONFIG_SAMPLES is not set | ||
| 1066 | CONFIG_DEBUG_USER=y | 1147 | CONFIG_DEBUG_USER=y |
| 1067 | # CONFIG_DEBUG_ERRORS is not set | 1148 | # CONFIG_DEBUG_ERRORS is not set |
| 1149 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1068 | CONFIG_DEBUG_LL=y | 1150 | CONFIG_DEBUG_LL=y |
| 1069 | # CONFIG_DEBUG_ICEDCC is not set | 1151 | # CONFIG_DEBUG_ICEDCC is not set |
| 1070 | 1152 | ||
| @@ -1073,12 +1155,14 @@ CONFIG_DEBUG_LL=y | |||
| 1073 | # | 1155 | # |
| 1074 | # CONFIG_KEYS is not set | 1156 | # CONFIG_KEYS is not set |
| 1075 | # CONFIG_SECURITY is not set | 1157 | # CONFIG_SECURITY is not set |
| 1076 | 1158 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | |
| 1077 | # | ||
| 1078 | # Cryptographic options | ||
| 1079 | # | ||
| 1080 | CONFIG_CRYPTO=y | 1159 | CONFIG_CRYPTO=y |
| 1160 | CONFIG_CRYPTO_ALGAPI=y | ||
| 1161 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 1162 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1163 | CONFIG_CRYPTO_MANAGER=y | ||
| 1081 | # CONFIG_CRYPTO_HMAC is not set | 1164 | # CONFIG_CRYPTO_HMAC is not set |
| 1165 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1082 | # CONFIG_CRYPTO_NULL is not set | 1166 | # CONFIG_CRYPTO_NULL is not set |
| 1083 | # CONFIG_CRYPTO_MD4 is not set | 1167 | # CONFIG_CRYPTO_MD4 is not set |
| 1084 | CONFIG_CRYPTO_MD5=y | 1168 | CONFIG_CRYPTO_MD5=y |
| @@ -1087,7 +1171,18 @@ CONFIG_CRYPTO_MD5=y | |||
| 1087 | # CONFIG_CRYPTO_SHA512 is not set | 1171 | # CONFIG_CRYPTO_SHA512 is not set |
| 1088 | # CONFIG_CRYPTO_WP512 is not set | 1172 | # CONFIG_CRYPTO_WP512 is not set |
| 1089 | # CONFIG_CRYPTO_TGR192 is not set | 1173 | # CONFIG_CRYPTO_TGR192 is not set |
| 1174 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1175 | # CONFIG_CRYPTO_ECB is not set | ||
| 1176 | CONFIG_CRYPTO_CBC=y | ||
| 1177 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1178 | # CONFIG_CRYPTO_LRW is not set | ||
| 1179 | # CONFIG_CRYPTO_XTS is not set | ||
| 1180 | # CONFIG_CRYPTO_CTR is not set | ||
| 1181 | # CONFIG_CRYPTO_GCM is not set | ||
| 1182 | # CONFIG_CRYPTO_CCM is not set | ||
| 1183 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1090 | CONFIG_CRYPTO_DES=y | 1184 | CONFIG_CRYPTO_DES=y |
| 1185 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1091 | # CONFIG_CRYPTO_BLOWFISH is not set | 1186 | # CONFIG_CRYPTO_BLOWFISH is not set |
| 1092 | # CONFIG_CRYPTO_TWOFISH is not set | 1187 | # CONFIG_CRYPTO_TWOFISH is not set |
| 1093 | # CONFIG_CRYPTO_SERPENT is not set | 1188 | # CONFIG_CRYPTO_SERPENT is not set |
| @@ -1098,20 +1193,29 @@ CONFIG_CRYPTO_DES=y | |||
| 1098 | # CONFIG_CRYPTO_ARC4 is not set | 1193 | # CONFIG_CRYPTO_ARC4 is not set |
| 1099 | # CONFIG_CRYPTO_KHAZAD is not set | 1194 | # CONFIG_CRYPTO_KHAZAD is not set |
| 1100 | # CONFIG_CRYPTO_ANUBIS is not set | 1195 | # CONFIG_CRYPTO_ANUBIS is not set |
| 1196 | # CONFIG_CRYPTO_SEED is not set | ||
| 1197 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1101 | # CONFIG_CRYPTO_DEFLATE is not set | 1198 | # CONFIG_CRYPTO_DEFLATE is not set |
| 1102 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | 1199 | # CONFIG_CRYPTO_MICHAEL_MIC is not set |
| 1103 | # CONFIG_CRYPTO_CRC32C is not set | 1200 | # CONFIG_CRYPTO_CRC32C is not set |
| 1201 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1104 | # CONFIG_CRYPTO_TEST is not set | 1202 | # CONFIG_CRYPTO_TEST is not set |
| 1105 | 1203 | # CONFIG_CRYPTO_AUTHENC is not set | |
| 1106 | # | 1204 | # CONFIG_CRYPTO_LZO is not set |
| 1107 | # Hardware crypto devices | 1205 | CONFIG_CRYPTO_HW=y |
| 1108 | # | ||
| 1109 | 1206 | ||
| 1110 | # | 1207 | # |
| 1111 | # Library routines | 1208 | # Library routines |
| 1112 | # | 1209 | # |
| 1210 | CONFIG_BITREVERSE=y | ||
| 1113 | # CONFIG_CRC_CCITT is not set | 1211 | # CONFIG_CRC_CCITT is not set |
| 1114 | # CONFIG_CRC16 is not set | 1212 | # CONFIG_CRC16 is not set |
| 1213 | # CONFIG_CRC_ITU_T is not set | ||
| 1115 | CONFIG_CRC32=y | 1214 | CONFIG_CRC32=y |
| 1215 | # CONFIG_CRC7 is not set | ||
| 1116 | # CONFIG_LIBCRC32C is not set | 1216 | # CONFIG_LIBCRC32C is not set |
| 1117 | CONFIG_ZLIB_INFLATE=y | 1217 | CONFIG_ZLIB_INFLATE=y |
| 1218 | CONFIG_PLIST=y | ||
| 1219 | CONFIG_HAS_IOMEM=y | ||
| 1220 | CONFIG_HAS_IOPORT=y | ||
| 1221 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/ecbat91_defconfig b/arch/arm/configs/ecbat91_defconfig new file mode 100644 index 000000000000..90ed214e3673 --- /dev/null +++ b/arch/arm/configs/ecbat91_defconfig | |||
| @@ -0,0 +1,1315 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.22-rc4 | ||
| 4 | # Sat Jun 9 01:30:18 2007 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | # CONFIG_GENERIC_TIME is not set | ||
| 10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 18 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 20 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 22 | CONFIG_GENERIC_HWEIGHT=y | ||
| 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 24 | CONFIG_ZONE_DMA=y | ||
| 25 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 26 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 27 | |||
| 28 | # | ||
| 29 | # Code maturity level options | ||
| 30 | # | ||
| 31 | CONFIG_EXPERIMENTAL=y | ||
| 32 | CONFIG_BROKEN_ON_SMP=y | ||
| 33 | CONFIG_LOCK_KERNEL=y | ||
| 34 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 35 | |||
| 36 | # | ||
| 37 | # General setup | ||
| 38 | # | ||
| 39 | CONFIG_LOCALVERSION="" | ||
| 40 | CONFIG_LOCALVERSION_AUTO=y | ||
| 41 | CONFIG_SWAP=y | ||
| 42 | CONFIG_SYSVIPC=y | ||
| 43 | # CONFIG_IPC_NS is not set | ||
| 44 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 45 | # CONFIG_POSIX_MQUEUE is not set | ||
| 46 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 47 | # CONFIG_TASKSTATS is not set | ||
| 48 | # CONFIG_UTS_NS is not set | ||
| 49 | # CONFIG_AUDIT is not set | ||
| 50 | CONFIG_IKCONFIG=y | ||
| 51 | CONFIG_IKCONFIG_PROC=y | ||
| 52 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 53 | CONFIG_SYSFS_DEPRECATED=y | ||
| 54 | # CONFIG_RELAY is not set | ||
| 55 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 56 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 57 | CONFIG_SYSCTL=y | ||
| 58 | # CONFIG_EMBEDDED is not set | ||
| 59 | CONFIG_UID16=y | ||
| 60 | CONFIG_SYSCTL_SYSCALL=y | ||
| 61 | CONFIG_KALLSYMS=y | ||
| 62 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 63 | CONFIG_HOTPLUG=y | ||
| 64 | CONFIG_PRINTK=y | ||
| 65 | CONFIG_BUG=y | ||
| 66 | CONFIG_ELF_CORE=y | ||
| 67 | CONFIG_BASE_FULL=y | ||
| 68 | CONFIG_FUTEX=y | ||
| 69 | CONFIG_ANON_INODES=y | ||
| 70 | CONFIG_EPOLL=y | ||
| 71 | CONFIG_SIGNALFD=y | ||
| 72 | CONFIG_TIMERFD=y | ||
| 73 | CONFIG_EVENTFD=y | ||
| 74 | CONFIG_SHMEM=y | ||
| 75 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 76 | CONFIG_SLAB=y | ||
| 77 | # CONFIG_SLUB is not set | ||
| 78 | # CONFIG_SLOB is not set | ||
| 79 | CONFIG_RT_MUTEXES=y | ||
| 80 | # CONFIG_TINY_SHMEM is not set | ||
| 81 | CONFIG_BASE_SMALL=0 | ||
| 82 | |||
| 83 | # | ||
| 84 | # Loadable module support | ||
| 85 | # | ||
| 86 | CONFIG_MODULES=y | ||
| 87 | CONFIG_MODULE_UNLOAD=y | ||
| 88 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 89 | # CONFIG_MODVERSIONS is not set | ||
| 90 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 91 | CONFIG_KMOD=y | ||
| 92 | |||
| 93 | # | ||
| 94 | # Block layer | ||
| 95 | # | ||
| 96 | CONFIG_BLOCK=y | ||
| 97 | # CONFIG_LBD is not set | ||
| 98 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 99 | # CONFIG_LSF is not set | ||
| 100 | |||
| 101 | # | ||
| 102 | # IO Schedulers | ||
| 103 | # | ||
| 104 | CONFIG_IOSCHED_NOOP=y | ||
| 105 | CONFIG_IOSCHED_AS=y | ||
| 106 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 107 | # CONFIG_IOSCHED_CFQ is not set | ||
| 108 | CONFIG_DEFAULT_AS=y | ||
| 109 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 110 | # CONFIG_DEFAULT_CFQ is not set | ||
| 111 | # CONFIG_DEFAULT_NOOP is not set | ||
| 112 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
| 113 | |||
| 114 | # | ||
| 115 | # System Type | ||
| 116 | # | ||
| 117 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 118 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 119 | # CONFIG_ARCH_REALVIEW is not set | ||
| 120 | # CONFIG_ARCH_VERSATILE is not set | ||
| 121 | CONFIG_ARCH_AT91=y | ||
| 122 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 123 | # CONFIG_ARCH_CLPS711X is not set | ||
| 124 | # CONFIG_ARCH_CO285 is not set | ||
| 125 | # CONFIG_ARCH_EBSA110 is not set | ||
| 126 | # CONFIG_ARCH_EP93XX is not set | ||
| 127 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 128 | # CONFIG_ARCH_NETX is not set | ||
| 129 | # CONFIG_ARCH_H720X is not set | ||
| 130 | # CONFIG_ARCH_IMX is not set | ||
| 131 | # CONFIG_ARCH_IOP13XX is not set | ||
| 132 | # CONFIG_ARCH_IOP32X is not set | ||
| 133 | # CONFIG_ARCH_IOP33X is not set | ||
| 134 | # CONFIG_ARCH_IXP23XX is not set | ||
| 135 | # CONFIG_ARCH_IXP2000 is not set | ||
| 136 | # CONFIG_ARCH_IXP4XX is not set | ||
| 137 | # CONFIG_ARCH_L7200 is not set | ||
| 138 | # CONFIG_ARCH_KS8695 is not set | ||
| 139 | # CONFIG_ARCH_NS9XXX is not set | ||
| 140 | # CONFIG_ARCH_PNX4008 is not set | ||
| 141 | # CONFIG_ARCH_PXA is not set | ||
| 142 | # CONFIG_ARCH_RPC is not set | ||
| 143 | # CONFIG_ARCH_SA1100 is not set | ||
| 144 | # CONFIG_ARCH_S3C2410 is not set | ||
| 145 | # CONFIG_ARCH_SHARK is not set | ||
| 146 | # CONFIG_ARCH_LH7A40X is not set | ||
| 147 | # CONFIG_ARCH_DAVINCI is not set | ||
| 148 | # CONFIG_ARCH_OMAP is not set | ||
| 149 | |||
| 150 | # | ||
| 151 | # Atmel AT91 System-on-Chip | ||
| 152 | # | ||
| 153 | CONFIG_ARCH_AT91RM9200=y | ||
| 154 | # CONFIG_ARCH_AT91SAM9260 is not set | ||
| 155 | # CONFIG_ARCH_AT91SAM9261 is not set | ||
| 156 | # CONFIG_ARCH_AT91SAM9263 is not set | ||
| 157 | # CONFIG_ARCH_AT91SAM9RL is not set | ||
| 158 | |||
| 159 | # | ||
| 160 | # AT91RM9200 Board Type | ||
| 161 | # | ||
| 162 | # CONFIG_MACH_ONEARM is not set | ||
| 163 | # CONFIG_ARCH_AT91RM9200DK is not set | ||
| 164 | # CONFIG_MACH_AT91RM9200EK is not set | ||
| 165 | # CONFIG_MACH_CSB337 is not set | ||
| 166 | # CONFIG_MACH_CSB637 is not set | ||
| 167 | # CONFIG_MACH_CARMEVA is not set | ||
| 168 | # CONFIG_MACH_ATEB9200 is not set | ||
| 169 | # CONFIG_MACH_KB9200 is not set | ||
| 170 | # CONFIG_MACH_PICOTUX2XX is not set | ||
| 171 | # CONFIG_MACH_KAFA is not set | ||
| 172 | # CONFIG_MACH_CHUB is not set | ||
| 173 | CONFIG_MACH_ECBAT91=y | ||
| 174 | |||
| 175 | # | ||
| 176 | # AT91 Board Options | ||
| 177 | # | ||
| 178 | # CONFIG_MTD_AT91_DATAFLASH_CARD is not set | ||
| 179 | |||
| 180 | # | ||
| 181 | # AT91 Feature Selections | ||
| 182 | # | ||
| 183 | CONFIG_AT91_PROGRAMMABLE_CLOCKS=y | ||
| 184 | # CONFIG_ATMEL_TCLIB is not set | ||
| 185 | |||
| 186 | # | ||
| 187 | # Processor Type | ||
| 188 | # | ||
| 189 | CONFIG_CPU_32=y | ||
| 190 | CONFIG_CPU_ARM920T=y | ||
| 191 | CONFIG_CPU_32v4T=y | ||
| 192 | CONFIG_CPU_ABRT_EV4T=y | ||
| 193 | CONFIG_CPU_CACHE_V4WT=y | ||
| 194 | CONFIG_CPU_CACHE_VIVT=y | ||
| 195 | CONFIG_CPU_COPY_V4WB=y | ||
| 196 | CONFIG_CPU_TLB_V4WBI=y | ||
| 197 | CONFIG_CPU_CP15=y | ||
| 198 | CONFIG_CPU_CP15_MMU=y | ||
| 199 | |||
| 200 | # | ||
| 201 | # Processor Features | ||
| 202 | # | ||
| 203 | CONFIG_ARM_THUMB=y | ||
| 204 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 205 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 206 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 207 | # CONFIG_OUTER_CACHE is not set | ||
| 208 | |||
| 209 | # | ||
| 210 | # Bus support | ||
| 211 | # | ||
| 212 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 213 | |||
| 214 | # | ||
| 215 | # PCCARD (PCMCIA/CardBus) support | ||
| 216 | # | ||
| 217 | CONFIG_PCCARD=y | ||
| 218 | # CONFIG_PCMCIA_DEBUG is not set | ||
| 219 | CONFIG_PCMCIA=y | ||
| 220 | CONFIG_PCMCIA_LOAD_CIS=y | ||
| 221 | CONFIG_PCMCIA_IOCTL=y | ||
| 222 | |||
| 223 | # | ||
| 224 | # PC-card bridges | ||
| 225 | # | ||
| 226 | CONFIG_AT91_CF=y | ||
| 227 | |||
| 228 | # | ||
| 229 | # Kernel Features | ||
| 230 | # | ||
| 231 | # CONFIG_TICK_ONESHOT is not set | ||
| 232 | CONFIG_PREEMPT=y | ||
| 233 | # CONFIG_NO_IDLE_HZ is not set | ||
| 234 | CONFIG_HZ=100 | ||
| 235 | # CONFIG_AEABI is not set | ||
| 236 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | ||
| 237 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 238 | CONFIG_FLATMEM_MANUAL=y | ||
| 239 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 240 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 241 | CONFIG_FLATMEM=y | ||
| 242 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 243 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 244 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 245 | # CONFIG_RESOURCES_64BIT is not set | ||
| 246 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 247 | CONFIG_LEDS=y | ||
| 248 | CONFIG_LEDS_TIMER=y | ||
| 249 | CONFIG_LEDS_CPU=y | ||
| 250 | CONFIG_ALIGNMENT_TRAP=y | ||
| 251 | |||
| 252 | # | ||
| 253 | # Boot options | ||
| 254 | # | ||
| 255 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 256 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 257 | CONFIG_CMDLINE="rootfstype=reiserfs root=/dev/mmcblk0p1 console=ttyS0,115200n8 rootdelay=1" | ||
| 258 | # CONFIG_XIP_KERNEL is not set | ||
| 259 | # CONFIG_KEXEC is not set | ||
| 260 | |||
| 261 | # | ||
| 262 | # Floating point emulation | ||
| 263 | # | ||
| 264 | |||
| 265 | # | ||
| 266 | # At least one emulation must be selected | ||
| 267 | # | ||
| 268 | CONFIG_FPE_NWFPE=y | ||
| 269 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 270 | # CONFIG_FPE_FASTFPE is not set | ||
| 271 | |||
| 272 | # | ||
| 273 | # Userspace binary formats | ||
| 274 | # | ||
| 275 | CONFIG_BINFMT_ELF=y | ||
| 276 | # CONFIG_BINFMT_AOUT is not set | ||
| 277 | # CONFIG_BINFMT_MISC is not set | ||
| 278 | # CONFIG_ARTHUR is not set | ||
| 279 | |||
| 280 | # | ||
| 281 | # Power management options | ||
| 282 | # | ||
| 283 | # CONFIG_PM is not set | ||
| 284 | |||
| 285 | # | ||
| 286 | # Networking | ||
| 287 | # | ||
| 288 | CONFIG_NET=y | ||
| 289 | |||
| 290 | # | ||
| 291 | # Networking options | ||
| 292 | # | ||
| 293 | CONFIG_PACKET=y | ||
| 294 | # CONFIG_PACKET_MMAP is not set | ||
| 295 | CONFIG_UNIX=y | ||
| 296 | CONFIG_XFRM=y | ||
| 297 | # CONFIG_XFRM_USER is not set | ||
| 298 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 299 | # CONFIG_XFRM_MIGRATE is not set | ||
| 300 | # CONFIG_NET_KEY is not set | ||
| 301 | CONFIG_INET=y | ||
| 302 | # CONFIG_IP_MULTICAST is not set | ||
| 303 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 304 | CONFIG_IP_FIB_HASH=y | ||
| 305 | CONFIG_IP_PNP=y | ||
| 306 | CONFIG_IP_PNP_DHCP=y | ||
| 307 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 308 | # CONFIG_IP_PNP_RARP is not set | ||
| 309 | # CONFIG_NET_IPIP is not set | ||
| 310 | # CONFIG_NET_IPGRE is not set | ||
| 311 | # CONFIG_ARPD is not set | ||
| 312 | # CONFIG_SYN_COOKIES is not set | ||
| 313 | # CONFIG_INET_AH is not set | ||
| 314 | # CONFIG_INET_ESP is not set | ||
| 315 | # CONFIG_INET_IPCOMP is not set | ||
| 316 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 317 | # CONFIG_INET_TUNNEL is not set | ||
| 318 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 319 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 320 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 321 | CONFIG_INET_DIAG=y | ||
| 322 | CONFIG_INET_TCP_DIAG=y | ||
| 323 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 324 | CONFIG_TCP_CONG_CUBIC=y | ||
| 325 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 326 | # CONFIG_TCP_MD5SIG is not set | ||
| 327 | # CONFIG_IPV6 is not set | ||
| 328 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 329 | # CONFIG_INET6_TUNNEL is not set | ||
| 330 | # CONFIG_NETWORK_SECMARK is not set | ||
| 331 | # CONFIG_NETFILTER is not set | ||
| 332 | # CONFIG_IP_DCCP is not set | ||
| 333 | # CONFIG_IP_SCTP is not set | ||
| 334 | # CONFIG_TIPC is not set | ||
| 335 | # CONFIG_ATM is not set | ||
| 336 | # CONFIG_BRIDGE is not set | ||
| 337 | # CONFIG_VLAN_8021Q is not set | ||
| 338 | # CONFIG_DECNET is not set | ||
| 339 | # CONFIG_LLC2 is not set | ||
| 340 | # CONFIG_IPX is not set | ||
| 341 | # CONFIG_ATALK is not set | ||
| 342 | # CONFIG_X25 is not set | ||
| 343 | # CONFIG_LAPB is not set | ||
| 344 | # CONFIG_ECONET is not set | ||
| 345 | # CONFIG_WAN_ROUTER is not set | ||
| 346 | |||
| 347 | # | ||
| 348 | # QoS and/or fair queueing | ||
| 349 | # | ||
| 350 | # CONFIG_NET_SCHED is not set | ||
| 351 | CONFIG_NET_SCH_FIFO=y | ||
| 352 | |||
| 353 | # | ||
| 354 | # Network testing | ||
| 355 | # | ||
| 356 | # CONFIG_NET_PKTGEN is not set | ||
| 357 | # CONFIG_HAMRADIO is not set | ||
| 358 | # CONFIG_IRDA is not set | ||
| 359 | # CONFIG_BT is not set | ||
| 360 | # CONFIG_AF_RXRPC is not set | ||
| 361 | |||
| 362 | # | ||
| 363 | # Wireless | ||
| 364 | # | ||
| 365 | CONFIG_CFG80211=y | ||
| 366 | CONFIG_WIRELESS_EXT=y | ||
| 367 | CONFIG_MAC80211=y | ||
| 368 | # CONFIG_MAC80211_DEBUG is not set | ||
| 369 | CONFIG_IEEE80211=y | ||
| 370 | # CONFIG_IEEE80211_DEBUG is not set | ||
| 371 | CONFIG_IEEE80211_CRYPT_WEP=y | ||
| 372 | # CONFIG_IEEE80211_CRYPT_CCMP is not set | ||
| 373 | # CONFIG_IEEE80211_CRYPT_TKIP is not set | ||
| 374 | CONFIG_IEEE80211_SOFTMAC=y | ||
| 375 | CONFIG_IEEE80211_SOFTMAC_DEBUG=y | ||
| 376 | # CONFIG_RFKILL is not set | ||
| 377 | |||
| 378 | # | ||
| 379 | # Device Drivers | ||
| 380 | # | ||
| 381 | |||
| 382 | # | ||
| 383 | # Generic Driver Options | ||
| 384 | # | ||
| 385 | # CONFIG_STANDALONE is not set | ||
| 386 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | ||
| 387 | CONFIG_FW_LOADER=y | ||
| 388 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 389 | |||
| 390 | # | ||
| 391 | # Connector - unified userspace <-> kernelspace linker | ||
| 392 | # | ||
| 393 | # CONFIG_CONNECTOR is not set | ||
| 394 | CONFIG_MTD=y | ||
| 395 | # CONFIG_MTD_DEBUG is not set | ||
| 396 | # CONFIG_MTD_CONCAT is not set | ||
| 397 | CONFIG_MTD_PARTITIONS=y | ||
| 398 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 399 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 400 | CONFIG_MTD_AFS_PARTS=y | ||
| 401 | |||
| 402 | # | ||
| 403 | # User Modules And Translation Layers | ||
| 404 | # | ||
| 405 | CONFIG_MTD_CHAR=y | ||
| 406 | CONFIG_MTD_BLKDEVS=y | ||
| 407 | CONFIG_MTD_BLOCK=y | ||
| 408 | # CONFIG_FTL is not set | ||
| 409 | # CONFIG_NFTL is not set | ||
| 410 | # CONFIG_INFTL is not set | ||
| 411 | # CONFIG_RFD_FTL is not set | ||
| 412 | # CONFIG_SSFDC is not set | ||
| 413 | |||
| 414 | # | ||
| 415 | # RAM/ROM/Flash chip drivers | ||
| 416 | # | ||
| 417 | # CONFIG_MTD_CFI is not set | ||
| 418 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 419 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 420 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 421 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 422 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 423 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 424 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 425 | CONFIG_MTD_CFI_I1=y | ||
| 426 | CONFIG_MTD_CFI_I2=y | ||
| 427 | # CONFIG_MTD_CFI_I4 is not set | ||
| 428 | # CONFIG_MTD_CFI_I8 is not set | ||
| 429 | # CONFIG_MTD_RAM is not set | ||
| 430 | # CONFIG_MTD_ROM is not set | ||
| 431 | # CONFIG_MTD_ABSENT is not set | ||
| 432 | |||
| 433 | # | ||
| 434 | # Mapping drivers for chip access | ||
| 435 | # | ||
| 436 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 437 | # CONFIG_MTD_PLATRAM is not set | ||
| 438 | |||
| 439 | # | ||
| 440 | # Self-contained MTD device drivers | ||
| 441 | # | ||
| 442 | CONFIG_MTD_DATAFLASH=y | ||
| 443 | # CONFIG_MTD_M25P80 is not set | ||
| 444 | # CONFIG_MTD_SLRAM is not set | ||
| 445 | # CONFIG_MTD_PHRAM is not set | ||
| 446 | # CONFIG_MTD_MTDRAM is not set | ||
| 447 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 448 | |||
| 449 | # | ||
| 450 | # Disk-On-Chip Device Drivers | ||
| 451 | # | ||
| 452 | # CONFIG_MTD_DOC2000 is not set | ||
| 453 | # CONFIG_MTD_DOC2001 is not set | ||
| 454 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 455 | # CONFIG_MTD_NAND is not set | ||
| 456 | # CONFIG_MTD_ONENAND is not set | ||
| 457 | |||
| 458 | # | ||
| 459 | # UBI - Unsorted block images | ||
| 460 | # | ||
| 461 | # CONFIG_MTD_UBI is not set | ||
| 462 | |||
| 463 | # | ||
| 464 | # Parallel port support | ||
| 465 | # | ||
| 466 | # CONFIG_PARPORT is not set | ||
| 467 | |||
| 468 | # | ||
| 469 | # Plug and Play support | ||
| 470 | # | ||
| 471 | # CONFIG_PNPACPI is not set | ||
| 472 | |||
| 473 | # | ||
| 474 | # Block devices | ||
| 475 | # | ||
| 476 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 477 | CONFIG_BLK_DEV_LOOP=y | ||
| 478 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 479 | # CONFIG_BLK_DEV_NBD is not set | ||
| 480 | # CONFIG_BLK_DEV_UB is not set | ||
| 481 | # CONFIG_BLK_DEV_RAM is not set | ||
| 482 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 483 | # CONFIG_ATA_OVER_ETH is not set | ||
| 484 | # CONFIG_IDE is not set | ||
| 485 | |||
| 486 | # | ||
| 487 | # SCSI device support | ||
| 488 | # | ||
| 489 | # CONFIG_RAID_ATTRS is not set | ||
| 490 | CONFIG_SCSI=y | ||
| 491 | # CONFIG_SCSI_TGT is not set | ||
| 492 | # CONFIG_SCSI_NETLINK is not set | ||
| 493 | CONFIG_SCSI_PROC_FS=y | ||
| 494 | |||
| 495 | # | ||
| 496 | # SCSI support type (disk, tape, CD-ROM) | ||
| 497 | # | ||
| 498 | CONFIG_BLK_DEV_SD=y | ||
| 499 | # CONFIG_CHR_DEV_ST is not set | ||
| 500 | # CONFIG_CHR_DEV_OSST is not set | ||
| 501 | # CONFIG_BLK_DEV_SR is not set | ||
| 502 | CONFIG_CHR_DEV_SG=y | ||
| 503 | # CONFIG_CHR_DEV_SCH is not set | ||
| 504 | |||
| 505 | # | ||
| 506 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 507 | # | ||
| 508 | # CONFIG_SCSI_MULTI_LUN is not set | ||
| 509 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 510 | # CONFIG_SCSI_LOGGING is not set | ||
| 511 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 512 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 513 | |||
| 514 | # | ||
| 515 | # SCSI Transports | ||
| 516 | # | ||
| 517 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 518 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 519 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 520 | # CONFIG_SCSI_SAS_ATTRS is not set | ||
| 521 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 522 | |||
| 523 | # | ||
| 524 | # SCSI low-level drivers | ||
| 525 | # | ||
| 526 | # CONFIG_ISCSI_TCP is not set | ||
| 527 | # CONFIG_SCSI_DEBUG is not set | ||
| 528 | |||
| 529 | # | ||
| 530 | # PCMCIA SCSI adapter support | ||
| 531 | # | ||
| 532 | # CONFIG_PCMCIA_AHA152X is not set | ||
| 533 | # CONFIG_PCMCIA_FDOMAIN is not set | ||
| 534 | # CONFIG_PCMCIA_NINJA_SCSI is not set | ||
| 535 | # CONFIG_PCMCIA_QLOGIC is not set | ||
| 536 | # CONFIG_PCMCIA_SYM53C500 is not set | ||
| 537 | # CONFIG_ATA is not set | ||
| 538 | |||
| 539 | # | ||
| 540 | # Multi-device support (RAID and LVM) | ||
| 541 | # | ||
| 542 | # CONFIG_MD is not set | ||
| 543 | |||
| 544 | # | ||
| 545 | # Network device support | ||
| 546 | # | ||
| 547 | CONFIG_NETDEVICES=y | ||
| 548 | # CONFIG_DUMMY is not set | ||
| 549 | # CONFIG_BONDING is not set | ||
| 550 | # CONFIG_EQUALIZER is not set | ||
| 551 | # CONFIG_TUN is not set | ||
| 552 | # CONFIG_PHYLIB is not set | ||
| 553 | |||
| 554 | # | ||
| 555 | # Ethernet (10 or 100Mbit) | ||
| 556 | # | ||
| 557 | CONFIG_NET_ETHERNET=y | ||
| 558 | CONFIG_MII=y | ||
| 559 | CONFIG_ARM_AT91_ETHER=y | ||
| 560 | # CONFIG_SMC91X is not set | ||
| 561 | # CONFIG_DM9000 is not set | ||
| 562 | # CONFIG_NETDEV_1000 is not set | ||
| 563 | # CONFIG_NETDEV_10000 is not set | ||
| 564 | |||
| 565 | # | ||
| 566 | # Wireless LAN | ||
| 567 | # | ||
| 568 | # CONFIG_WLAN_PRE80211 is not set | ||
| 569 | # CONFIG_WLAN_80211 is not set | ||
| 570 | |||
| 571 | # | ||
| 572 | # USB Network Adapters | ||
| 573 | # | ||
| 574 | # CONFIG_USB_CATC is not set | ||
| 575 | # CONFIG_USB_KAWETH is not set | ||
| 576 | # CONFIG_USB_PEGASUS is not set | ||
| 577 | # CONFIG_USB_RTL8150 is not set | ||
| 578 | # CONFIG_USB_USBNET_MII is not set | ||
| 579 | # CONFIG_USB_USBNET is not set | ||
| 580 | # CONFIG_NET_PCMCIA is not set | ||
| 581 | # CONFIG_WAN is not set | ||
| 582 | CONFIG_PPP=y | ||
| 583 | CONFIG_PPP_MULTILINK=y | ||
| 584 | CONFIG_PPP_FILTER=y | ||
| 585 | CONFIG_PPP_ASYNC=y | ||
| 586 | # CONFIG_PPP_SYNC_TTY is not set | ||
| 587 | # CONFIG_PPP_DEFLATE is not set | ||
| 588 | # CONFIG_PPP_BSDCOMP is not set | ||
| 589 | # CONFIG_PPP_MPPE is not set | ||
| 590 | # CONFIG_PPPOE is not set | ||
| 591 | # CONFIG_SLIP is not set | ||
| 592 | CONFIG_SLHC=y | ||
| 593 | # CONFIG_SHAPER is not set | ||
| 594 | # CONFIG_NETCONSOLE is not set | ||
| 595 | # CONFIG_NETPOLL is not set | ||
| 596 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 597 | |||
| 598 | # | ||
| 599 | # ISDN subsystem | ||
| 600 | # | ||
| 601 | # CONFIG_ISDN is not set | ||
| 602 | |||
| 603 | # | ||
| 604 | # Input device support | ||
| 605 | # | ||
| 606 | CONFIG_INPUT=y | ||
| 607 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 608 | |||
| 609 | # | ||
| 610 | # Userland interfaces | ||
| 611 | # | ||
| 612 | CONFIG_INPUT_MOUSEDEV=y | ||
| 613 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 614 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 615 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 616 | # CONFIG_INPUT_JOYDEV is not set | ||
| 617 | # CONFIG_INPUT_TSDEV is not set | ||
| 618 | # CONFIG_INPUT_EVDEV is not set | ||
| 619 | # CONFIG_INPUT_EVBUG is not set | ||
| 620 | |||
| 621 | # | ||
| 622 | # Input Device Drivers | ||
| 623 | # | ||
| 624 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 625 | # CONFIG_INPUT_MOUSE is not set | ||
| 626 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 627 | # CONFIG_INPUT_TABLET is not set | ||
| 628 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 629 | # CONFIG_INPUT_MISC is not set | ||
| 630 | |||
| 631 | # | ||
| 632 | # Hardware I/O ports | ||
| 633 | # | ||
| 634 | # CONFIG_SERIO is not set | ||
| 635 | # CONFIG_GAMEPORT is not set | ||
| 636 | |||
| 637 | # | ||
| 638 | # Character devices | ||
| 639 | # | ||
| 640 | CONFIG_VT=y | ||
| 641 | CONFIG_VT_CONSOLE=y | ||
| 642 | CONFIG_HW_CONSOLE=y | ||
| 643 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 644 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 645 | |||
| 646 | # | ||
| 647 | # Serial drivers | ||
| 648 | # | ||
| 649 | # CONFIG_SERIAL_8250 is not set | ||
| 650 | |||
| 651 | # | ||
| 652 | # Non-8250 serial port support | ||
| 653 | # | ||
| 654 | CONFIG_SERIAL_ATMEL=y | ||
| 655 | CONFIG_SERIAL_ATMEL_CONSOLE=y | ||
| 656 | # CONFIG_SERIAL_ATMEL_TTYAT is not set | ||
| 657 | CONFIG_SERIAL_CORE=y | ||
| 658 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 659 | CONFIG_UNIX98_PTYS=y | ||
| 660 | CONFIG_LEGACY_PTYS=y | ||
| 661 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 662 | |||
| 663 | # | ||
| 664 | # IPMI | ||
| 665 | # | ||
| 666 | # CONFIG_IPMI_HANDLER is not set | ||
| 667 | CONFIG_WATCHDOG=y | ||
| 668 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 669 | |||
| 670 | # | ||
| 671 | # Watchdog Device Drivers | ||
| 672 | # | ||
| 673 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 674 | # CONFIG_AT91RM9200_WATCHDOG is not set | ||
| 675 | |||
| 676 | # | ||
| 677 | # USB-based Watchdog Cards | ||
| 678 | # | ||
| 679 | # CONFIG_USBPCWATCHDOG is not set | ||
| 680 | CONFIG_HW_RANDOM=y | ||
| 681 | # CONFIG_NVRAM is not set | ||
| 682 | # CONFIG_R3964 is not set | ||
| 683 | |||
| 684 | # | ||
| 685 | # PCMCIA character devices | ||
| 686 | # | ||
| 687 | # CONFIG_SYNCLINK_CS is not set | ||
| 688 | # CONFIG_CARDMAN_4000 is not set | ||
| 689 | # CONFIG_CARDMAN_4040 is not set | ||
| 690 | # CONFIG_RAW_DRIVER is not set | ||
| 691 | |||
| 692 | # | ||
| 693 | # TPM devices | ||
| 694 | # | ||
| 695 | # CONFIG_TCG_TPM is not set | ||
| 696 | # CONFIG_AT91_SPI is not set | ||
| 697 | CONFIG_I2C=y | ||
| 698 | CONFIG_I2C_BOARDINFO=y | ||
| 699 | CONFIG_I2C_CHARDEV=y | ||
| 700 | |||
| 701 | # | ||
| 702 | # I2C Algorithms | ||
| 703 | # | ||
| 704 | CONFIG_I2C_ALGOBIT=y | ||
| 705 | # CONFIG_I2C_ALGOPCF is not set | ||
| 706 | # CONFIG_I2C_ALGOPCA is not set | ||
| 707 | |||
| 708 | # | ||
| 709 | # I2C Hardware Bus support | ||
| 710 | # | ||
| 711 | CONFIG_I2C_GPIO=y | ||
| 712 | # CONFIG_I2C_GPIO is not set | ||
| 713 | # CONFIG_I2C_OCORES is not set | ||
| 714 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 715 | # CONFIG_I2C_SIMTEC is not set | ||
| 716 | # CONFIG_I2C_STUB is not set | ||
| 717 | # CONFIG_I2C_TINY_USB is not set | ||
| 718 | # CONFIG_I2C_PCA is not set | ||
| 719 | |||
| 720 | # | ||
| 721 | # Miscellaneous I2C Chip support | ||
| 722 | # | ||
| 723 | # CONFIG_SENSORS_DS1337 is not set | ||
| 724 | # CONFIG_SENSORS_DS1374 is not set | ||
| 725 | # CONFIG_SENSORS_EEPROM is not set | ||
| 726 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 727 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 728 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 729 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 730 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 731 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 732 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 733 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 734 | |||
| 735 | # | ||
| 736 | # SPI support | ||
| 737 | # | ||
| 738 | CONFIG_SPI=y | ||
| 739 | CONFIG_SPI_MASTER=y | ||
| 740 | |||
| 741 | # | ||
| 742 | # SPI Master Controller Drivers | ||
| 743 | # | ||
| 744 | # CONFIG_SPI_ATMEL is not set | ||
| 745 | CONFIG_SPI_BITBANG=y | ||
| 746 | CONFIG_SPI_AT91=y | ||
| 747 | |||
| 748 | # | ||
| 749 | # SPI Protocol Masters | ||
| 750 | # | ||
| 751 | # CONFIG_SPI_AT25 is not set | ||
| 752 | # CONFIG_SPI_SPIDEV is not set | ||
| 753 | |||
| 754 | # | ||
| 755 | # Dallas's 1-wire bus | ||
| 756 | # | ||
| 757 | # CONFIG_W1 is not set | ||
| 758 | CONFIG_HWMON=y | ||
| 759 | # CONFIG_HWMON_VID is not set | ||
| 760 | # CONFIG_SENSORS_ABITUGURU is not set | ||
| 761 | # CONFIG_SENSORS_AD7418 is not set | ||
| 762 | # CONFIG_SENSORS_ADM1021 is not set | ||
| 763 | # CONFIG_SENSORS_ADM1025 is not set | ||
| 764 | # CONFIG_SENSORS_ADM1026 is not set | ||
| 765 | # CONFIG_SENSORS_ADM1029 is not set | ||
| 766 | # CONFIG_SENSORS_ADM1031 is not set | ||
| 767 | # CONFIG_SENSORS_ADM9240 is not set | ||
| 768 | # CONFIG_SENSORS_ASB100 is not set | ||
| 769 | # CONFIG_SENSORS_ATXP1 is not set | ||
| 770 | # CONFIG_SENSORS_DS1621 is not set | ||
| 771 | # CONFIG_SENSORS_F71805F is not set | ||
| 772 | # CONFIG_SENSORS_FSCHER is not set | ||
| 773 | # CONFIG_SENSORS_FSCPOS is not set | ||
| 774 | # CONFIG_SENSORS_GL518SM is not set | ||
| 775 | # CONFIG_SENSORS_GL520SM is not set | ||
| 776 | # CONFIG_SENSORS_IT87 is not set | ||
| 777 | # CONFIG_SENSORS_LM63 is not set | ||
| 778 | # CONFIG_SENSORS_LM70 is not set | ||
| 779 | # CONFIG_SENSORS_LM75 is not set | ||
| 780 | # CONFIG_SENSORS_LM77 is not set | ||
| 781 | # CONFIG_SENSORS_LM78 is not set | ||
| 782 | # CONFIG_SENSORS_LM80 is not set | ||
| 783 | # CONFIG_SENSORS_LM83 is not set | ||
| 784 | # CONFIG_SENSORS_LM85 is not set | ||
| 785 | # CONFIG_SENSORS_LM87 is not set | ||
| 786 | # CONFIG_SENSORS_LM90 is not set | ||
| 787 | # CONFIG_SENSORS_LM92 is not set | ||
| 788 | # CONFIG_SENSORS_MAX1619 is not set | ||
| 789 | # CONFIG_SENSORS_MAX6650 is not set | ||
| 790 | # CONFIG_SENSORS_PC87360 is not set | ||
| 791 | # CONFIG_SENSORS_PC87427 is not set | ||
| 792 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
| 793 | # CONFIG_SENSORS_SMSC47M192 is not set | ||
| 794 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
| 795 | # CONFIG_SENSORS_VT1211 is not set | ||
| 796 | # CONFIG_SENSORS_W83781D is not set | ||
| 797 | # CONFIG_SENSORS_W83791D is not set | ||
| 798 | # CONFIG_SENSORS_W83792D is not set | ||
| 799 | # CONFIG_SENSORS_W83793 is not set | ||
| 800 | # CONFIG_SENSORS_W83L785TS is not set | ||
| 801 | # CONFIG_SENSORS_W83627HF is not set | ||
| 802 | # CONFIG_SENSORS_W83627EHF is not set | ||
| 803 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
| 804 | |||
| 805 | # | ||
| 806 | # Misc devices | ||
| 807 | # | ||
| 808 | # CONFIG_BLINK is not set | ||
| 809 | |||
| 810 | # | ||
| 811 | # Multifunction device drivers | ||
| 812 | # | ||
| 813 | # CONFIG_MFD_SM501 is not set | ||
| 814 | |||
| 815 | # | ||
| 816 | # LED devices | ||
| 817 | # | ||
| 818 | CONFIG_NEW_LEDS=y | ||
| 819 | CONFIG_LEDS_CLASS=y | ||
| 820 | |||
| 821 | # | ||
| 822 | # LED drivers | ||
| 823 | # | ||
| 824 | |||
| 825 | # | ||
| 826 | # LED Triggers | ||
| 827 | # | ||
| 828 | # CONFIG_LEDS_TRIGGERS is not set | ||
| 829 | |||
| 830 | # | ||
| 831 | # Multimedia devices | ||
| 832 | # | ||
| 833 | # CONFIG_VIDEO_DEV is not set | ||
| 834 | # CONFIG_DVB_CORE is not set | ||
| 835 | CONFIG_DAB=y | ||
| 836 | # CONFIG_USB_DABUSB is not set | ||
| 837 | |||
| 838 | # | ||
| 839 | # Graphics support | ||
| 840 | # | ||
| 841 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 842 | |||
| 843 | # | ||
| 844 | # Display device support | ||
| 845 | # | ||
| 846 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 847 | # CONFIG_VGASTATE is not set | ||
| 848 | # CONFIG_FB is not set | ||
| 849 | |||
| 850 | # | ||
| 851 | # Console display driver support | ||
| 852 | # | ||
| 853 | # CONFIG_VGA_CONSOLE is not set | ||
| 854 | CONFIG_DUMMY_CONSOLE=y | ||
| 855 | |||
| 856 | # | ||
| 857 | # Sound | ||
| 858 | # | ||
| 859 | # CONFIG_SOUND is not set | ||
| 860 | |||
| 861 | # | ||
| 862 | # HID Devices | ||
| 863 | # | ||
| 864 | CONFIG_HID=y | ||
| 865 | # CONFIG_HID_DEBUG is not set | ||
| 866 | |||
| 867 | # | ||
| 868 | # USB Input Devices | ||
| 869 | # | ||
| 870 | # CONFIG_USB_HID is not set | ||
| 871 | |||
| 872 | # | ||
| 873 | # USB HID Boot Protocol drivers | ||
| 874 | # | ||
| 875 | # CONFIG_USB_KBD is not set | ||
| 876 | # CONFIG_USB_MOUSE is not set | ||
| 877 | |||
| 878 | # | ||
| 879 | # USB support | ||
| 880 | # | ||
| 881 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 882 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 883 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 884 | CONFIG_USB=y | ||
| 885 | # CONFIG_USB_DEBUG is not set | ||
| 886 | |||
| 887 | # | ||
| 888 | # Miscellaneous USB options | ||
| 889 | # | ||
| 890 | CONFIG_USB_DEVICEFS=y | ||
| 891 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 892 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 893 | # CONFIG_USB_OTG is not set | ||
| 894 | |||
| 895 | # | ||
| 896 | # USB Host Controller Drivers | ||
| 897 | # | ||
| 898 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 899 | CONFIG_USB_OHCI_HCD=y | ||
| 900 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
| 901 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 902 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
| 903 | # CONFIG_USB_SL811_HCD is not set | ||
| 904 | |||
| 905 | # | ||
| 906 | # USB Device Class drivers | ||
| 907 | # | ||
| 908 | # CONFIG_USB_ACM is not set | ||
| 909 | CONFIG_USB_PRINTER=y | ||
| 910 | |||
| 911 | # | ||
| 912 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
| 913 | # | ||
| 914 | |||
| 915 | # | ||
| 916 | # may also be needed; see USB_STORAGE Help for more information | ||
| 917 | # | ||
| 918 | CONFIG_USB_STORAGE=y | ||
| 919 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 920 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 921 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 922 | # CONFIG_USB_STORAGE_DPCM is not set | ||
| 923 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 924 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 925 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 926 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 927 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 928 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 929 | # CONFIG_USB_LIBUSUAL is not set | ||
| 930 | |||
| 931 | # | ||
| 932 | # USB Imaging devices | ||
| 933 | # | ||
| 934 | # CONFIG_USB_MDC800 is not set | ||
| 935 | # CONFIG_USB_MICROTEK is not set | ||
| 936 | # CONFIG_USB_MON is not set | ||
| 937 | |||
| 938 | # | ||
| 939 | # USB port drivers | ||
| 940 | # | ||
| 941 | |||
| 942 | # | ||
| 943 | # USB Serial Converter support | ||
| 944 | # | ||
| 945 | # CONFIG_USB_SERIAL is not set | ||
| 946 | |||
| 947 | # | ||
| 948 | # USB Miscellaneous drivers | ||
| 949 | # | ||
| 950 | # CONFIG_USB_EMI62 is not set | ||
| 951 | # CONFIG_USB_EMI26 is not set | ||
| 952 | # CONFIG_USB_ADUTUX is not set | ||
| 953 | # CONFIG_USB_AUERSWALD is not set | ||
| 954 | # CONFIG_USB_RIO500 is not set | ||
| 955 | # CONFIG_USB_LEGOTOWER is not set | ||
| 956 | # CONFIG_USB_LCD is not set | ||
| 957 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 958 | # CONFIG_USB_LED is not set | ||
| 959 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 960 | # CONFIG_USB_CYTHERM is not set | ||
| 961 | # CONFIG_USB_PHIDGET is not set | ||
| 962 | # CONFIG_USB_IDMOUSE is not set | ||
| 963 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 964 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 965 | # CONFIG_USB_LD is not set | ||
| 966 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 967 | # CONFIG_USB_IOWARRIOR is not set | ||
| 968 | # CONFIG_USB_TEST is not set | ||
| 969 | |||
| 970 | # | ||
| 971 | # USB DSL modem support | ||
| 972 | # | ||
| 973 | |||
| 974 | # | ||
| 975 | # USB Gadget Support | ||
| 976 | # | ||
| 977 | CONFIG_USB_GADGET=y | ||
| 978 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
| 979 | CONFIG_USB_GADGET_SELECTED=y | ||
| 980 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 981 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 982 | # CONFIG_USB_GADGET_PXA2XX is not set | ||
| 983 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 984 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 985 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 986 | CONFIG_USB_GADGET_AT91=y | ||
| 987 | CONFIG_USB_AT91=y | ||
| 988 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 989 | # CONFIG_USB_GADGET_DUALSPEED is not set | ||
| 990 | # CONFIG_USB_ZERO is not set | ||
| 991 | # CONFIG_USB_ETH is not set | ||
| 992 | # CONFIG_USB_GADGETFS is not set | ||
| 993 | # CONFIG_USB_FILE_STORAGE is not set | ||
| 994 | # CONFIG_USB_G_SERIAL is not set | ||
| 995 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 996 | CONFIG_MMC=y | ||
| 997 | CONFIG_MMC_DEBUG=y | ||
| 998 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 999 | |||
| 1000 | # | ||
| 1001 | # MMC/SD Card Drivers | ||
| 1002 | # | ||
| 1003 | CONFIG_MMC_BLOCK=y | ||
| 1004 | |||
| 1005 | # | ||
| 1006 | # MMC/SD Host Controller Drivers | ||
| 1007 | # | ||
| 1008 | CONFIG_MMC_AT91=y | ||
| 1009 | |||
| 1010 | # | ||
| 1011 | # Real Time Clock | ||
| 1012 | # | ||
| 1013 | CONFIG_RTC_LIB=y | ||
| 1014 | CONFIG_RTC_CLASS=y | ||
| 1015 | # CONFIG_RTC_HCTOSYS is not set | ||
| 1016 | # CONFIG_RTC_DEBUG is not set | ||
| 1017 | |||
| 1018 | # | ||
| 1019 | # RTC interfaces | ||
| 1020 | # | ||
| 1021 | CONFIG_RTC_INTF_SYSFS=y | ||
| 1022 | CONFIG_RTC_INTF_PROC=y | ||
| 1023 | CONFIG_RTC_INTF_DEV=y | ||
| 1024 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 1025 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1026 | |||
| 1027 | # | ||
| 1028 | # I2C RTC drivers | ||
| 1029 | # | ||
| 1030 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 1031 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 1032 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 1033 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 1034 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 1035 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 1036 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 1037 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 1038 | |||
| 1039 | # | ||
| 1040 | # SPI RTC drivers | ||
| 1041 | # | ||
| 1042 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1043 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 1044 | |||
| 1045 | # | ||
| 1046 | # Platform RTC drivers | ||
| 1047 | # | ||
| 1048 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 1049 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1050 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1051 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1052 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 1053 | |||
| 1054 | # | ||
| 1055 | # on-CPU RTC drivers | ||
| 1056 | # | ||
| 1057 | CONFIG_RTC_DRV_AT91RM9200=y | ||
| 1058 | |||
| 1059 | # | ||
| 1060 | # File systems | ||
| 1061 | # | ||
| 1062 | CONFIG_EXT2_FS=y | ||
| 1063 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 1064 | # CONFIG_EXT2_FS_XIP is not set | ||
| 1065 | CONFIG_EXT3_FS=y | ||
| 1066 | CONFIG_EXT3_FS_XATTR=y | ||
| 1067 | # CONFIG_EXT3_FS_POSIX_ACL is not set | ||
| 1068 | # CONFIG_EXT3_FS_SECURITY is not set | ||
| 1069 | # CONFIG_EXT4DEV_FS is not set | ||
| 1070 | CONFIG_JBD=y | ||
| 1071 | # CONFIG_JBD_DEBUG is not set | ||
| 1072 | CONFIG_FS_MBCACHE=y | ||
| 1073 | CONFIG_REISERFS_FS=y | ||
| 1074 | # CONFIG_REISERFS_CHECK is not set | ||
| 1075 | # CONFIG_REISERFS_PROC_INFO is not set | ||
| 1076 | # CONFIG_REISERFS_FS_XATTR is not set | ||
| 1077 | # CONFIG_JFS_FS is not set | ||
| 1078 | CONFIG_FS_POSIX_ACL=y | ||
| 1079 | # CONFIG_XFS_FS is not set | ||
| 1080 | # CONFIG_GFS2_FS is not set | ||
| 1081 | # CONFIG_OCFS2_FS is not set | ||
| 1082 | # CONFIG_MINIX_FS is not set | ||
| 1083 | # CONFIG_ROMFS_FS is not set | ||
| 1084 | CONFIG_INOTIFY=y | ||
| 1085 | CONFIG_INOTIFY_USER=y | ||
| 1086 | # CONFIG_QUOTA is not set | ||
| 1087 | CONFIG_DNOTIFY=y | ||
| 1088 | # CONFIG_AUTOFS_FS is not set | ||
| 1089 | # CONFIG_AUTOFS4_FS is not set | ||
| 1090 | # CONFIG_FUSE_FS is not set | ||
| 1091 | |||
| 1092 | # | ||
| 1093 | # CD-ROM/DVD Filesystems | ||
| 1094 | # | ||
| 1095 | # CONFIG_ISO9660_FS is not set | ||
| 1096 | # CONFIG_UDF_FS is not set | ||
| 1097 | |||
| 1098 | # | ||
| 1099 | # DOS/FAT/NT Filesystems | ||
| 1100 | # | ||
| 1101 | # CONFIG_MSDOS_FS is not set | ||
| 1102 | # CONFIG_VFAT_FS is not set | ||
| 1103 | # CONFIG_NTFS_FS is not set | ||
| 1104 | |||
| 1105 | # | ||
| 1106 | # Pseudo filesystems | ||
| 1107 | # | ||
| 1108 | CONFIG_PROC_FS=y | ||
| 1109 | CONFIG_PROC_SYSCTL=y | ||
| 1110 | CONFIG_SYSFS=y | ||
| 1111 | CONFIG_TMPFS=y | ||
| 1112 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1113 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1114 | CONFIG_RAMFS=y | ||
| 1115 | CONFIG_CONFIGFS_FS=y | ||
| 1116 | |||
| 1117 | # | ||
| 1118 | # Miscellaneous filesystems | ||
| 1119 | # | ||
| 1120 | # CONFIG_ADFS_FS is not set | ||
| 1121 | # CONFIG_AFFS_FS is not set | ||
| 1122 | # CONFIG_HFS_FS is not set | ||
| 1123 | # CONFIG_HFSPLUS_FS is not set | ||
| 1124 | # CONFIG_BEFS_FS is not set | ||
| 1125 | # CONFIG_BFS_FS is not set | ||
| 1126 | # CONFIG_EFS_FS is not set | ||
| 1127 | # CONFIG_JFFS2_FS is not set | ||
| 1128 | CONFIG_CRAMFS=y | ||
| 1129 | # CONFIG_VXFS_FS is not set | ||
| 1130 | # CONFIG_HPFS_FS is not set | ||
| 1131 | # CONFIG_QNX4FS_FS is not set | ||
| 1132 | # CONFIG_SYSV_FS is not set | ||
| 1133 | # CONFIG_UFS_FS is not set | ||
| 1134 | |||
| 1135 | # | ||
| 1136 | # Network File Systems | ||
| 1137 | # | ||
| 1138 | CONFIG_NFS_FS=y | ||
| 1139 | CONFIG_NFS_V3=y | ||
| 1140 | CONFIG_NFS_V3_ACL=y | ||
| 1141 | CONFIG_NFS_V4=y | ||
| 1142 | # CONFIG_NFS_DIRECTIO is not set | ||
| 1143 | # CONFIG_NFSD is not set | ||
| 1144 | CONFIG_ROOT_NFS=y | ||
| 1145 | CONFIG_LOCKD=y | ||
| 1146 | CONFIG_LOCKD_V4=y | ||
| 1147 | CONFIG_NFS_ACL_SUPPORT=y | ||
| 1148 | CONFIG_NFS_COMMON=y | ||
| 1149 | CONFIG_SUNRPC=y | ||
| 1150 | CONFIG_SUNRPC_GSS=y | ||
| 1151 | # CONFIG_SUNRPC_BIND34 is not set | ||
| 1152 | CONFIG_RPCSEC_GSS_KRB5=y | ||
| 1153 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1154 | # CONFIG_SMB_FS is not set | ||
| 1155 | # CONFIG_CIFS is not set | ||
| 1156 | # CONFIG_NCP_FS is not set | ||
| 1157 | # CONFIG_CODA_FS is not set | ||
| 1158 | # CONFIG_AFS_FS is not set | ||
| 1159 | # CONFIG_9P_FS is not set | ||
| 1160 | |||
| 1161 | # | ||
| 1162 | # Partition Types | ||
| 1163 | # | ||
| 1164 | CONFIG_PARTITION_ADVANCED=y | ||
| 1165 | # CONFIG_ACORN_PARTITION is not set | ||
| 1166 | # CONFIG_OSF_PARTITION is not set | ||
| 1167 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1168 | # CONFIG_ATARI_PARTITION is not set | ||
| 1169 | # CONFIG_MAC_PARTITION is not set | ||
| 1170 | CONFIG_MSDOS_PARTITION=y | ||
| 1171 | # CONFIG_BSD_DISKLABEL is not set | ||
| 1172 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 1173 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 1174 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 1175 | # CONFIG_LDM_PARTITION is not set | ||
| 1176 | # CONFIG_SGI_PARTITION is not set | ||
| 1177 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1178 | # CONFIG_SUN_PARTITION is not set | ||
| 1179 | # CONFIG_KARMA_PARTITION is not set | ||
| 1180 | # CONFIG_EFI_PARTITION is not set | ||
| 1181 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1182 | |||
| 1183 | # | ||
| 1184 | # Native Language Support | ||
| 1185 | # | ||
| 1186 | CONFIG_NLS=y | ||
| 1187 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1188 | # CONFIG_NLS_CODEPAGE_437 is not set | ||
| 1189 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1190 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1191 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1192 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1193 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1194 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1195 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1196 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1197 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1198 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1199 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1200 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1201 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1202 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1203 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1204 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1205 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1206 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1207 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1208 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1209 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1210 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1211 | # CONFIG_NLS_ASCII is not set | ||
| 1212 | # CONFIG_NLS_ISO8859_1 is not set | ||
| 1213 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1214 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1215 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1216 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1217 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1218 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1219 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1220 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1221 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1222 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1223 | # CONFIG_NLS_KOI8_R is not set | ||
| 1224 | # CONFIG_NLS_KOI8_U is not set | ||
| 1225 | # CONFIG_NLS_UTF8 is not set | ||
| 1226 | |||
| 1227 | # | ||
| 1228 | # Distributed Lock Manager | ||
| 1229 | # | ||
| 1230 | # CONFIG_DLM is not set | ||
| 1231 | |||
| 1232 | # | ||
| 1233 | # Profiling support | ||
| 1234 | # | ||
| 1235 | # CONFIG_PROFILING is not set | ||
| 1236 | |||
| 1237 | # | ||
| 1238 | # Kernel hacking | ||
| 1239 | # | ||
| 1240 | # CONFIG_PRINTK_TIME is not set | ||
| 1241 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1242 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1243 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1244 | # CONFIG_DEBUG_FS is not set | ||
| 1245 | # CONFIG_HEADERS_CHECK is not set | ||
| 1246 | # CONFIG_DEBUG_KERNEL is not set | ||
| 1247 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1248 | CONFIG_FRAME_POINTER=y | ||
| 1249 | CONFIG_DEBUG_USER=y | ||
| 1250 | |||
| 1251 | # | ||
| 1252 | # Security options | ||
| 1253 | # | ||
| 1254 | # CONFIG_KEYS is not set | ||
| 1255 | # CONFIG_SECURITY is not set | ||
| 1256 | |||
| 1257 | # | ||
| 1258 | # Cryptographic options | ||
| 1259 | # | ||
| 1260 | CONFIG_CRYPTO=y | ||
| 1261 | CONFIG_CRYPTO_ALGAPI=y | ||
| 1262 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 1263 | CONFIG_CRYPTO_MANAGER=y | ||
| 1264 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1265 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1266 | # CONFIG_CRYPTO_NULL is not set | ||
| 1267 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1268 | CONFIG_CRYPTO_MD5=y | ||
| 1269 | CONFIG_CRYPTO_SHA1=y | ||
| 1270 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1271 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1272 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1273 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1274 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1275 | CONFIG_CRYPTO_ECB=y | ||
| 1276 | CONFIG_CRYPTO_CBC=y | ||
| 1277 | CONFIG_CRYPTO_PCBC=y | ||
| 1278 | # CONFIG_CRYPTO_LRW is not set | ||
| 1279 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1280 | CONFIG_CRYPTO_DES=y | ||
| 1281 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1282 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1283 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1284 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1285 | CONFIG_CRYPTO_AES=y | ||
| 1286 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1287 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1288 | # CONFIG_CRYPTO_TEA is not set | ||
| 1289 | CONFIG_CRYPTO_ARC4=y | ||
| 1290 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1291 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1292 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1293 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1294 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1295 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1296 | # CONFIG_CRYPTO_TEST is not set | ||
| 1297 | |||
| 1298 | # | ||
| 1299 | # Hardware crypto devices | ||
| 1300 | # | ||
| 1301 | |||
| 1302 | # | ||
| 1303 | # Library routines | ||
| 1304 | # | ||
| 1305 | CONFIG_BITREVERSE=y | ||
| 1306 | CONFIG_CRC_CCITT=y | ||
| 1307 | # CONFIG_CRC16 is not set | ||
| 1308 | # CONFIG_CRC_ITU_T is not set | ||
| 1309 | CONFIG_CRC32=y | ||
| 1310 | # CONFIG_LIBCRC32C is not set | ||
| 1311 | CONFIG_ZLIB_INFLATE=y | ||
| 1312 | CONFIG_PLIST=y | ||
| 1313 | CONFIG_HAS_IOMEM=y | ||
| 1314 | CONFIG_HAS_IOPORT=y | ||
| 1315 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/kafa_defconfig b/arch/arm/configs/kafa_defconfig index a0f48d54fbcc..ae51a40db6f9 100644 --- a/arch/arm/configs/kafa_defconfig +++ b/arch/arm/configs/kafa_defconfig | |||
| @@ -587,14 +587,14 @@ CONFIG_I2C_CHARDEV=y | |||
| 587 | # | 587 | # |
| 588 | # I2C Algorithms | 588 | # I2C Algorithms |
| 589 | # | 589 | # |
| 590 | # CONFIG_I2C_ALGOBIT is not set | 590 | CONFIG_I2C_ALGOBIT=y |
| 591 | # CONFIG_I2C_ALGOPCF is not set | 591 | # CONFIG_I2C_ALGOPCF is not set |
| 592 | # CONFIG_I2C_ALGOPCA is not set | 592 | # CONFIG_I2C_ALGOPCA is not set |
| 593 | 593 | ||
| 594 | # | 594 | # |
| 595 | # I2C Hardware Bus support | 595 | # I2C Hardware Bus support |
| 596 | # | 596 | # |
| 597 | CONFIG_I2C_AT91=y | 597 | CONFIG_I2C_GPIO=y |
| 598 | # CONFIG_I2C_PARPORT_LIGHT is not set | 598 | # CONFIG_I2C_PARPORT_LIGHT is not set |
| 599 | # CONFIG_I2C_STUB is not set | 599 | # CONFIG_I2C_STUB is not set |
| 600 | # CONFIG_I2C_PCA_ISA is not set | 600 | # CONFIG_I2C_PCA_ISA is not set |
diff --git a/arch/arm/configs/ns9xxx_defconfig b/arch/arm/configs/ns9xxx_defconfig index 0e5794c6a48e..7dc1580e4d99 100644 --- a/arch/arm/configs/ns9xxx_defconfig +++ b/arch/arm/configs/ns9xxx_defconfig | |||
| @@ -1,621 +1,79 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.20 | ||
| 4 | # Thu Feb 15 20:51:47 2007 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | # CONFIG_GENERIC_TIME is not set | ||
| 8 | CONFIG_MMU=y | ||
| 9 | CONFIG_GENERIC_HARDIRQS=y | ||
| 10 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 11 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 12 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 13 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 14 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 15 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 16 | CONFIG_GENERIC_HWEIGHT=y | ||
| 17 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 18 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 19 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 20 | |||
| 21 | # | ||
| 22 | # Code maturity level options | ||
| 23 | # | ||
| 24 | CONFIG_EXPERIMENTAL=y | ||
| 25 | CONFIG_BROKEN_ON_SMP=y | ||
| 26 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 27 | |||
| 28 | # | ||
| 29 | # General setup | ||
| 30 | # | ||
| 31 | CONFIG_LOCALVERSION="" | ||
| 32 | CONFIG_LOCALVERSION_AUTO=y | ||
| 33 | CONFIG_SWAP=y | ||
| 34 | CONFIG_SYSVIPC=y | ||
| 35 | # CONFIG_IPC_NS is not set | ||
| 36 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 37 | # CONFIG_UTS_NS is not set | ||
| 38 | CONFIG_IKCONFIG=y | 1 | CONFIG_IKCONFIG=y |
| 39 | CONFIG_IKCONFIG_PROC=y | 2 | CONFIG_IKCONFIG_PROC=y |
| 40 | CONFIG_SYSFS_DEPRECATED=y | 3 | CONFIG_BLK_DEV_INITRD=y |
| 41 | # CONFIG_RELAY is not set | ||
| 42 | CONFIG_INITRAMFS_SOURCE="" | ||
| 43 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
| 44 | CONFIG_SYSCTL=y | ||
| 45 | CONFIG_EMBEDDED=y | ||
| 46 | CONFIG_UID16=y | ||
| 47 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 48 | CONFIG_KALLSYMS=y | ||
| 49 | # CONFIG_KALLSYMS_ALL is not set | ||
| 50 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 51 | CONFIG_HOTPLUG=y | ||
| 52 | CONFIG_PRINTK=y | ||
| 53 | CONFIG_BUG=y | ||
| 54 | CONFIG_ELF_CORE=y | ||
| 55 | CONFIG_BASE_FULL=y | ||
| 56 | CONFIG_FUTEX=y | ||
| 57 | CONFIG_EPOLL=y | ||
| 58 | CONFIG_SHMEM=y | ||
| 59 | CONFIG_SLAB=y | ||
| 60 | # CONFIG_VM_EVENT_COUNTERS is not set | ||
| 61 | CONFIG_RT_MUTEXES=y | ||
| 62 | # CONFIG_TINY_SHMEM is not set | ||
| 63 | CONFIG_BASE_SMALL=0 | ||
| 64 | # CONFIG_SLOB is not set | ||
| 65 | |||
| 66 | # | ||
| 67 | # Loadable module support | ||
| 68 | # | ||
| 69 | CONFIG_MODULES=y | 4 | CONFIG_MODULES=y |
| 70 | CONFIG_MODULE_UNLOAD=y | 5 | CONFIG_MODULE_UNLOAD=y |
| 71 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 72 | CONFIG_MODVERSIONS=y | ||
| 73 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 74 | CONFIG_KMOD=y | ||
| 75 | |||
| 76 | # | ||
| 77 | # Block layer | ||
| 78 | # | ||
| 79 | CONFIG_BLOCK=y | ||
| 80 | # CONFIG_LBD is not set | ||
| 81 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 82 | # CONFIG_LSF is not set | ||
| 83 | |||
| 84 | # | ||
| 85 | # IO Schedulers | ||
| 86 | # | ||
| 87 | CONFIG_IOSCHED_NOOP=y | ||
| 88 | # CONFIG_IOSCHED_AS is not set | 6 | # CONFIG_IOSCHED_AS is not set |
| 89 | # CONFIG_IOSCHED_DEADLINE is not set | 7 | # CONFIG_IOSCHED_DEADLINE is not set |
| 90 | # CONFIG_IOSCHED_CFQ is not set | 8 | # CONFIG_IOSCHED_CFQ is not set |
| 91 | # CONFIG_DEFAULT_AS is not set | ||
| 92 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 93 | # CONFIG_DEFAULT_CFQ is not set | ||
| 94 | CONFIG_DEFAULT_NOOP=y | ||
| 95 | CONFIG_DEFAULT_IOSCHED="noop" | ||
| 96 | |||
| 97 | # | ||
| 98 | # System Type | ||
| 99 | # | ||
| 100 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 101 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 102 | # CONFIG_ARCH_REALVIEW is not set | ||
| 103 | # CONFIG_ARCH_VERSATILE is not set | ||
| 104 | # CONFIG_ARCH_AT91 is not set | ||
| 105 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 106 | # CONFIG_ARCH_CLPS711X is not set | ||
| 107 | # CONFIG_ARCH_CO285 is not set | ||
| 108 | # CONFIG_ARCH_EBSA110 is not set | ||
| 109 | # CONFIG_ARCH_EP93XX is not set | ||
| 110 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 111 | # CONFIG_ARCH_NETX is not set | ||
| 112 | # CONFIG_ARCH_H720X is not set | ||
| 113 | # CONFIG_ARCH_IMX is not set | ||
| 114 | # CONFIG_ARCH_IOP32X is not set | ||
| 115 | # CONFIG_ARCH_IOP33X is not set | ||
| 116 | # CONFIG_ARCH_IOP13XX is not set | ||
| 117 | # CONFIG_ARCH_IXP4XX is not set | ||
| 118 | # CONFIG_ARCH_IXP2000 is not set | ||
| 119 | # CONFIG_ARCH_IXP23XX is not set | ||
| 120 | # CONFIG_ARCH_L7200 is not set | ||
| 121 | CONFIG_ARCH_NS9XXX=y | 9 | CONFIG_ARCH_NS9XXX=y |
| 122 | # CONFIG_ARCH_PNX4008 is not set | 10 | CONFIG_MACH_A9M9360=y |
| 123 | # CONFIG_ARCH_PXA is not set | 11 | CONFIG_MACH_A9M9750=y |
| 124 | # CONFIG_ARCH_RPC is not set | 12 | CONFIG_MACH_CC7UCAMRY=y |
| 125 | # CONFIG_ARCH_SA1100 is not set | 13 | CONFIG_MACH_CC9C=y |
| 126 | # CONFIG_ARCH_S3C2410 is not set | 14 | CONFIG_MACH_CC9P9210=y |
| 127 | # CONFIG_ARCH_SHARK is not set | 15 | CONFIG_MACH_CC9P9210JS=y |
| 128 | # CONFIG_ARCH_LH7A40X is not set | 16 | CONFIG_MACH_CC9P9215=y |
| 129 | # CONFIG_ARCH_OMAP is not set | 17 | CONFIG_MACH_CC9P9215JS=y |
| 130 | |||
| 131 | # | ||
| 132 | # NS9xxx Implementations | ||
| 133 | # | ||
| 134 | CONFIG_MACH_CC9P9360DEV=y | 18 | CONFIG_MACH_CC9P9360DEV=y |
| 135 | CONFIG_PROCESSOR_NS9360=y | 19 | CONFIG_MACH_CC9P9360JS=y |
| 136 | CONFIG_BOARD_A9M9750DEV=y | 20 | CONFIG_MACH_CC9P9360VAL=y |
| 137 | 21 | CONFIG_MACH_CC9P9750DEV=y | |
| 138 | # | 22 | CONFIG_MACH_CC9P9750VAL=y |
| 139 | # Processor Type | 23 | CONFIG_MACH_CCW9C=y |
| 140 | # | 24 | CONFIG_MACH_INC20OTTER=y |
| 141 | CONFIG_CPU_32=y | 25 | CONFIG_MACH_OTTER=y |
| 142 | CONFIG_CPU_ARM926T=y | 26 | CONFIG_NO_HZ=y |
| 143 | CONFIG_CPU_32v5=y | 27 | CONFIG_HIGH_RES_TIMERS=y |
| 144 | CONFIG_CPU_ABRT_EV5TJ=y | ||
| 145 | CONFIG_CPU_CACHE_VIVT=y | ||
| 146 | CONFIG_CPU_COPY_V4WB=y | ||
| 147 | CONFIG_CPU_TLB_V4WBI=y | ||
| 148 | CONFIG_CPU_CP15=y | ||
| 149 | CONFIG_CPU_CP15_MMU=y | ||
| 150 | |||
| 151 | # | ||
| 152 | # Processor Features | ||
| 153 | # | ||
| 154 | # CONFIG_ARM_THUMB is not set | ||
| 155 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 156 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 157 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 158 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set | ||
| 159 | |||
| 160 | # | ||
| 161 | # Bus support | ||
| 162 | # | ||
| 163 | |||
| 164 | # | ||
| 165 | # PCCARD (PCMCIA/CardBus) support | ||
| 166 | # | ||
| 167 | # CONFIG_PCCARD is not set | ||
| 168 | |||
| 169 | # | ||
| 170 | # Kernel Features | ||
| 171 | # | ||
| 172 | # CONFIG_PREEMPT is not set | ||
| 173 | # CONFIG_NO_IDLE_HZ is not set | ||
| 174 | CONFIG_HZ=100 | ||
| 175 | # CONFIG_AEABI is not set | ||
| 176 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | ||
| 177 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 178 | CONFIG_FLATMEM_MANUAL=y | ||
| 179 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 180 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 181 | CONFIG_FLATMEM=y | ||
| 182 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 183 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 184 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 185 | # CONFIG_RESOURCES_64BIT is not set | ||
| 186 | CONFIG_ALIGNMENT_TRAP=y | ||
| 187 | |||
| 188 | # | ||
| 189 | # Boot options | ||
| 190 | # | ||
| 191 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 192 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 193 | CONFIG_CMDLINE="" | ||
| 194 | # CONFIG_XIP_KERNEL is not set | ||
| 195 | |||
| 196 | # | ||
| 197 | # Floating point emulation | ||
| 198 | # | ||
| 199 | |||
| 200 | # | ||
| 201 | # At least one emulation must be selected | ||
| 202 | # | ||
| 203 | CONFIG_FPE_NWFPE=y | 28 | CONFIG_FPE_NWFPE=y |
| 204 | # CONFIG_FPE_NWFPE_XP is not set | 29 | CONFIG_NET=y |
| 205 | # CONFIG_FPE_FASTFPE is not set | 30 | CONFIG_PACKET=m |
| 206 | # CONFIG_VFP is not set | 31 | CONFIG_INET=y |
| 207 | 32 | CONFIG_IP_PNP=y | |
| 208 | # | 33 | CONFIG_SYN_COOKIES=y |
| 209 | # Userspace binary formats | 34 | CONFIG_MTD=m |
| 210 | # | 35 | CONFIG_MTD_CONCAT=m |
| 211 | CONFIG_BINFMT_ELF=y | 36 | CONFIG_MTD_CHAR=m |
| 212 | # CONFIG_BINFMT_AOUT is not set | 37 | CONFIG_MTD_BLOCK=m |
| 213 | # CONFIG_BINFMT_MISC is not set | 38 | CONFIG_MTD_CFI=m |
| 214 | # CONFIG_ARTHUR is not set | 39 | CONFIG_MTD_JEDECPROBE=m |
| 215 | 40 | CONFIG_MTD_CFI_AMDSTD=m | |
| 216 | # | 41 | CONFIG_MTD_PHYSMAP=m |
| 217 | # Power management options | 42 | CONFIG_MTD_PHYSMAP_START=0x0 |
| 218 | # | 43 | CONFIG_BLK_DEV_LOOP=m |
| 219 | # CONFIG_PM is not set | 44 | CONFIG_NETDEVICES=y |
| 220 | # CONFIG_APM is not set | 45 | CONFIG_NET_ETHERNET=y |
| 221 | 46 | CONFIG_NS9XXX_ETH=y | |
| 222 | # | ||
| 223 | # Networking | ||
| 224 | # | ||
| 225 | # CONFIG_NET is not set | ||
| 226 | |||
| 227 | # | ||
| 228 | # Device Drivers | ||
| 229 | # | ||
| 230 | |||
| 231 | # | ||
| 232 | # Generic Driver Options | ||
| 233 | # | ||
| 234 | CONFIG_STANDALONE=y | ||
| 235 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 236 | # CONFIG_FW_LOADER is not set | ||
| 237 | # CONFIG_DEBUG_DRIVER is not set | ||
| 238 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 239 | |||
| 240 | # | ||
| 241 | # Connector - unified userspace <-> kernelspace linker | ||
| 242 | # | ||
| 243 | |||
| 244 | # | ||
| 245 | # Memory Technology Devices (MTD) | ||
| 246 | # | ||
| 247 | # CONFIG_MTD is not set | ||
| 248 | |||
| 249 | # | ||
| 250 | # Parallel port support | ||
| 251 | # | ||
| 252 | # CONFIG_PARPORT is not set | ||
| 253 | |||
| 254 | # | ||
| 255 | # Plug and Play support | ||
| 256 | # | ||
| 257 | |||
| 258 | # | ||
| 259 | # Block devices | ||
| 260 | # | ||
| 261 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 262 | # CONFIG_BLK_DEV_LOOP is not set | ||
| 263 | CONFIG_BLK_DEV_RAM=y | ||
| 264 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 265 | CONFIG_BLK_DEV_RAM_SIZE=4096 | ||
| 266 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | ||
| 267 | CONFIG_BLK_DEV_INITRD=y | ||
| 268 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 269 | |||
| 270 | # | ||
| 271 | # SCSI device support | ||
| 272 | # | ||
| 273 | # CONFIG_RAID_ATTRS is not set | ||
| 274 | # CONFIG_SCSI is not set | ||
| 275 | # CONFIG_SCSI_NETLINK is not set | ||
| 276 | |||
| 277 | # | ||
| 278 | # Serial ATA (prod) and Parallel ATA (experimental) drivers | ||
| 279 | # | ||
| 280 | # CONFIG_ATA is not set | ||
| 281 | |||
| 282 | # | ||
| 283 | # Multi-device support (RAID and LVM) | ||
| 284 | # | ||
| 285 | # CONFIG_MD is not set | ||
| 286 | |||
| 287 | # | ||
| 288 | # Fusion MPT device support | ||
| 289 | # | ||
| 290 | # CONFIG_FUSION is not set | ||
| 291 | |||
| 292 | # | ||
| 293 | # IEEE 1394 (FireWire) support | ||
| 294 | # | ||
| 295 | |||
| 296 | # | ||
| 297 | # I2O device support | ||
| 298 | # | ||
| 299 | |||
| 300 | # | ||
| 301 | # ISDN subsystem | ||
| 302 | # | ||
| 303 | |||
| 304 | # | ||
| 305 | # Input device support | ||
| 306 | # | ||
| 307 | CONFIG_INPUT=y | ||
| 308 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 309 | |||
| 310 | # | ||
| 311 | # Userland interfaces | ||
| 312 | # | ||
| 313 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 314 | # CONFIG_INPUT_JOYDEV is not set | ||
| 315 | # CONFIG_INPUT_TSDEV is not set | ||
| 316 | # CONFIG_INPUT_EVDEV is not set | ||
| 317 | # CONFIG_INPUT_EVBUG is not set | ||
| 318 | |||
| 319 | # | ||
| 320 | # Input Device Drivers | ||
| 321 | # | ||
| 322 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 323 | # CONFIG_INPUT_MOUSE is not set | ||
| 324 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 325 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 326 | # CONFIG_INPUT_MISC is not set | ||
| 327 | |||
| 328 | # | ||
| 329 | # Hardware I/O ports | ||
| 330 | # | ||
| 331 | CONFIG_SERIO=y | ||
| 332 | # CONFIG_SERIO_SERPORT is not set | 47 | # CONFIG_SERIO_SERPORT is not set |
| 333 | CONFIG_SERIO_LIBPS2=y | ||
| 334 | # CONFIG_SERIO_RAW is not set | ||
| 335 | # CONFIG_GAMEPORT is not set | ||
| 336 | |||
| 337 | # | ||
| 338 | # Character devices | ||
| 339 | # | ||
| 340 | CONFIG_VT=y | ||
| 341 | CONFIG_VT_CONSOLE=y | ||
| 342 | CONFIG_HW_CONSOLE=y | ||
| 343 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 344 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 345 | |||
| 346 | # | ||
| 347 | # Serial drivers | ||
| 348 | # | ||
| 349 | CONFIG_SERIAL_8250=y | 48 | CONFIG_SERIAL_8250=y |
| 350 | CONFIG_SERIAL_8250_CONSOLE=y | 49 | CONFIG_SERIAL_8250_CONSOLE=y |
| 351 | CONFIG_SERIAL_8250_NR_UARTS=4 | 50 | CONFIG_SERIAL_NS921X=y |
| 352 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | 51 | CONFIG_SERIAL_NS921X_CONSOLE=y |
| 353 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 354 | # CONFIG_SERIAL_8250_MANY_PORTS is not set | ||
| 355 | # CONFIG_SERIAL_8250_SHARE_IRQ is not set | ||
| 356 | # CONFIG_SERIAL_8250_DETECT_IRQ is not set | ||
| 357 | # CONFIG_SERIAL_8250_RSA is not set | ||
| 358 | |||
| 359 | # | ||
| 360 | # Non-8250 serial port support | ||
| 361 | # | ||
| 362 | CONFIG_SERIAL_CORE=y | ||
| 363 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 364 | CONFIG_UNIX98_PTYS=y | ||
| 365 | # CONFIG_LEGACY_PTYS is not set | 52 | # CONFIG_LEGACY_PTYS is not set |
| 366 | |||
| 367 | # | ||
| 368 | # IPMI | ||
| 369 | # | ||
| 370 | # CONFIG_IPMI_HANDLER is not set | ||
| 371 | |||
| 372 | # | ||
| 373 | # Watchdog Cards | ||
| 374 | # | ||
| 375 | # CONFIG_WATCHDOG is not set | ||
| 376 | # CONFIG_HW_RANDOM is not set | 53 | # CONFIG_HW_RANDOM is not set |
| 377 | # CONFIG_NVRAM is not set | 54 | CONFIG_ADC_NS9215=m |
| 378 | # CONFIG_DTLK is not set | 55 | CONFIG_I2C=m |
| 379 | # CONFIG_R3964 is not set | 56 | CONFIG_I2C_GPIO=m |
| 380 | # CONFIG_RAW_DRIVER is not set | ||
| 381 | |||
| 382 | # | ||
| 383 | # TPM devices | ||
| 384 | # | ||
| 385 | # CONFIG_TCG_TPM is not set | ||
| 386 | |||
| 387 | # | ||
| 388 | # I2C support | ||
| 389 | # | ||
| 390 | # CONFIG_I2C is not set | ||
| 391 | |||
| 392 | # | ||
| 393 | # SPI support | ||
| 394 | # | ||
| 395 | # CONFIG_SPI is not set | ||
| 396 | # CONFIG_SPI_MASTER is not set | ||
| 397 | |||
| 398 | # | ||
| 399 | # Dallas's 1-wire bus | ||
| 400 | # | ||
| 401 | # CONFIG_W1 is not set | ||
| 402 | |||
| 403 | # | ||
| 404 | # Hardware Monitoring support | ||
| 405 | # | ||
| 406 | # CONFIG_HWMON is not set | 57 | # CONFIG_HWMON is not set |
| 407 | # CONFIG_HWMON_VID is not set | ||
| 408 | |||
| 409 | # | ||
| 410 | # Misc devices | ||
| 411 | # | ||
| 412 | # CONFIG_TIFM_CORE is not set | ||
| 413 | |||
| 414 | # | ||
| 415 | # LED devices | ||
| 416 | # | ||
| 417 | # CONFIG_NEW_LEDS is not set | ||
| 418 | |||
| 419 | # | ||
| 420 | # LED drivers | ||
| 421 | # | ||
| 422 | |||
| 423 | # | ||
| 424 | # LED Triggers | ||
| 425 | # | ||
| 426 | |||
| 427 | # | ||
| 428 | # Multimedia devices | ||
| 429 | # | ||
| 430 | # CONFIG_VIDEO_DEV is not set | ||
| 431 | |||
| 432 | # | ||
| 433 | # Digital Video Broadcasting Devices | ||
| 434 | # | ||
| 435 | |||
| 436 | # | ||
| 437 | # Graphics support | ||
| 438 | # | ||
| 439 | # CONFIG_FIRMWARE_EDID is not set | ||
| 440 | # CONFIG_FB is not set | ||
| 441 | |||
| 442 | # | ||
| 443 | # Console display driver support | ||
| 444 | # | ||
| 445 | # CONFIG_VGA_CONSOLE is not set | 58 | # CONFIG_VGA_CONSOLE is not set |
| 446 | CONFIG_DUMMY_CONSOLE=y | 59 | # CONFIG_HID_DEBUG is not set |
| 447 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 60 | # CONFIG_USB_SUPPORT is not set |
| 448 | 61 | CONFIG_NEW_LEDS=y | |
| 449 | # | 62 | CONFIG_LEDS_CLASS=m |
| 450 | # Sound | 63 | CONFIG_LEDS_GPIO=m |
| 451 | # | 64 | CONFIG_LEDS_TRIGGERS=y |
| 452 | # CONFIG_SOUND is not set | 65 | CONFIG_LEDS_TRIGGER_TIMER=m |
| 453 | 66 | CONFIG_LEDS_TRIGGER_HEARTBEAT=m | |
| 454 | # | 67 | CONFIG_RTC_CLASS=m |
| 455 | # HID Devices | 68 | CONFIG_RTC_DRV_NS9215=m |
| 456 | # | 69 | CONFIG_EXT2_FS=m |
| 457 | CONFIG_HID=y | ||
| 458 | |||
| 459 | # | ||
| 460 | # USB support | ||
| 461 | # | ||
| 462 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 463 | # CONFIG_USB_ARCH_HAS_OHCI is not set | ||
| 464 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 465 | # CONFIG_USB is not set | ||
| 466 | |||
| 467 | # | ||
| 468 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
| 469 | # | ||
| 470 | |||
| 471 | # | ||
| 472 | # USB Gadget Support | ||
| 473 | # | ||
| 474 | # CONFIG_USB_GADGET is not set | ||
| 475 | |||
| 476 | # | ||
| 477 | # MMC/SD Card support | ||
| 478 | # | ||
| 479 | # CONFIG_MMC is not set | ||
| 480 | |||
| 481 | # | ||
| 482 | # Real Time Clock | ||
| 483 | # | ||
| 484 | CONFIG_RTC_LIB=y | ||
| 485 | # CONFIG_RTC_CLASS is not set | ||
| 486 | |||
| 487 | # | ||
| 488 | # File systems | ||
| 489 | # | ||
| 490 | CONFIG_EXT2_FS=y | ||
| 491 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 492 | # CONFIG_EXT2_FS_XIP is not set | ||
| 493 | # CONFIG_EXT3_FS is not set | ||
| 494 | # CONFIG_EXT4DEV_FS is not set | ||
| 495 | # CONFIG_REISERFS_FS is not set | ||
| 496 | # CONFIG_JFS_FS is not set | ||
| 497 | # CONFIG_FS_POSIX_ACL is not set | ||
| 498 | # CONFIG_XFS_FS is not set | ||
| 499 | # CONFIG_GFS2_FS is not set | ||
| 500 | # CONFIG_MINIX_FS is not set | ||
| 501 | # CONFIG_ROMFS_FS is not set | ||
| 502 | CONFIG_INOTIFY=y | ||
| 503 | CONFIG_INOTIFY_USER=y | ||
| 504 | # CONFIG_QUOTA is not set | ||
| 505 | # CONFIG_DNOTIFY is not set | ||
| 506 | # CONFIG_AUTOFS_FS is not set | ||
| 507 | # CONFIG_AUTOFS4_FS is not set | ||
| 508 | # CONFIG_FUSE_FS is not set | ||
| 509 | |||
| 510 | # | ||
| 511 | # CD-ROM/DVD Filesystems | ||
| 512 | # | ||
| 513 | # CONFIG_ISO9660_FS is not set | ||
| 514 | # CONFIG_UDF_FS is not set | ||
| 515 | |||
| 516 | # | ||
| 517 | # DOS/FAT/NT Filesystems | ||
| 518 | # | ||
| 519 | # CONFIG_MSDOS_FS is not set | ||
| 520 | # CONFIG_VFAT_FS is not set | ||
| 521 | # CONFIG_NTFS_FS is not set | ||
| 522 | |||
| 523 | # | ||
| 524 | # Pseudo filesystems | ||
| 525 | # | ||
| 526 | CONFIG_PROC_FS=y | ||
| 527 | CONFIG_PROC_SYSCTL=y | ||
| 528 | CONFIG_SYSFS=y | ||
| 529 | CONFIG_TMPFS=y | 70 | CONFIG_TMPFS=y |
| 530 | # CONFIG_TMPFS_POSIX_ACL is not set | 71 | CONFIG_JFFS2_FS=m |
| 531 | # CONFIG_HUGETLB_PAGE is not set | 72 | CONFIG_NFS_FS=y |
| 532 | CONFIG_RAMFS=y | 73 | CONFIG_ROOT_NFS=y |
| 533 | # CONFIG_CONFIGFS_FS is not set | ||
| 534 | |||
| 535 | # | ||
| 536 | # Miscellaneous filesystems | ||
| 537 | # | ||
| 538 | # CONFIG_ADFS_FS is not set | ||
| 539 | # CONFIG_AFFS_FS is not set | ||
| 540 | # CONFIG_HFS_FS is not set | ||
| 541 | # CONFIG_HFSPLUS_FS is not set | ||
| 542 | # CONFIG_BEFS_FS is not set | ||
| 543 | # CONFIG_BFS_FS is not set | ||
| 544 | # CONFIG_EFS_FS is not set | ||
| 545 | # CONFIG_CRAMFS is not set | ||
| 546 | # CONFIG_VXFS_FS is not set | ||
| 547 | # CONFIG_HPFS_FS is not set | ||
| 548 | # CONFIG_QNX4FS_FS is not set | ||
| 549 | # CONFIG_SYSV_FS is not set | ||
| 550 | # CONFIG_UFS_FS is not set | ||
| 551 | |||
| 552 | # | ||
| 553 | # Partition Types | ||
| 554 | # | ||
| 555 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 556 | CONFIG_MSDOS_PARTITION=y | ||
| 557 | |||
| 558 | # | ||
| 559 | # Native Language Support | ||
| 560 | # | ||
| 561 | # CONFIG_NLS is not set | ||
| 562 | |||
| 563 | # | ||
| 564 | # Profiling support | ||
| 565 | # | ||
| 566 | # CONFIG_PROFILING is not set | ||
| 567 | |||
| 568 | # | ||
| 569 | # Kernel hacking | ||
| 570 | # | ||
| 571 | # CONFIG_PRINTK_TIME is not set | ||
| 572 | # CONFIG_ENABLE_MUST_CHECK is not set | 74 | # CONFIG_ENABLE_MUST_CHECK is not set |
| 573 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 574 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 575 | # CONFIG_DEBUG_FS is not set | ||
| 576 | # CONFIG_HEADERS_CHECK is not set | ||
| 577 | CONFIG_DEBUG_KERNEL=y | 75 | CONFIG_DEBUG_KERNEL=y |
| 578 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 579 | # CONFIG_DETECT_SOFTLOCKUP is not set | ||
| 580 | # CONFIG_SCHEDSTATS is not set | ||
| 581 | # CONFIG_DEBUG_SLAB is not set | ||
| 582 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 583 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 584 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 585 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 586 | # CONFIG_DEBUG_RWSEMS is not set | ||
| 587 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 588 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 589 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 590 | CONFIG_DEBUG_BUGVERBOSE=y | 76 | CONFIG_DEBUG_BUGVERBOSE=y |
| 591 | CONFIG_DEBUG_INFO=y | 77 | CONFIG_DEBUG_INFO=y |
| 592 | # CONFIG_DEBUG_VM is not set | ||
| 593 | # CONFIG_DEBUG_LIST is not set | ||
| 594 | CONFIG_FRAME_POINTER=y | ||
| 595 | CONFIG_FORCED_INLINING=y | ||
| 596 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 597 | CONFIG_DEBUG_USER=y | 78 | CONFIG_DEBUG_USER=y |
| 598 | CONFIG_DEBUG_ERRORS=y | 79 | CONFIG_DEBUG_ERRORS=y |
| 599 | CONFIG_DEBUG_LL=y | ||
| 600 | CONFIG_DEBUG_ICEDCC=y | ||
| 601 | |||
| 602 | # | ||
| 603 | # Security options | ||
| 604 | # | ||
| 605 | # CONFIG_KEYS is not set | ||
| 606 | # CONFIG_SECURITY is not set | ||
| 607 | |||
| 608 | # | ||
| 609 | # Cryptographic options | ||
| 610 | # | ||
| 611 | # CONFIG_CRYPTO is not set | ||
| 612 | |||
| 613 | # | ||
| 614 | # Library routines | ||
| 615 | # | ||
| 616 | # CONFIG_CRC_CCITT is not set | ||
| 617 | # CONFIG_CRC16 is not set | ||
| 618 | # CONFIG_CRC32 is not set | ||
| 619 | # CONFIG_LIBCRC32C is not set | ||
| 620 | CONFIG_PLIST=y | ||
| 621 | CONFIG_IOMAP_COPY=y | ||
diff --git a/arch/arm/configs/orion_defconfig b/arch/arm/configs/orion5x_defconfig index 1e5aaa645fcd..52cd99bd52fb 100644 --- a/arch/arm/configs/orion_defconfig +++ b/arch/arm/configs/orion5x_defconfig | |||
| @@ -140,7 +140,7 @@ CONFIG_CLASSIC_RCU=y | |||
| 140 | # CONFIG_ARCH_KS8695 is not set | 140 | # CONFIG_ARCH_KS8695 is not set |
| 141 | # CONFIG_ARCH_NS9XXX is not set | 141 | # CONFIG_ARCH_NS9XXX is not set |
| 142 | # CONFIG_ARCH_MXC is not set | 142 | # CONFIG_ARCH_MXC is not set |
| 143 | CONFIG_ARCH_ORION=y | 143 | CONFIG_ARCH_ORION5X=y |
| 144 | # CONFIG_ARCH_PNX4008 is not set | 144 | # CONFIG_ARCH_PNX4008 is not set |
| 145 | # CONFIG_ARCH_PXA is not set | 145 | # CONFIG_ARCH_PXA is not set |
| 146 | # CONFIG_ARCH_RPC is not set | 146 | # CONFIG_ARCH_RPC is not set |
diff --git a/arch/arm/configs/picotux200_defconfig b/arch/arm/configs/picotux200_defconfig index 3c0c4f192dc1..95a22f512805 100644 --- a/arch/arm/configs/picotux200_defconfig +++ b/arch/arm/configs/picotux200_defconfig | |||
| @@ -727,14 +727,14 @@ CONFIG_I2C_CHARDEV=m | |||
| 727 | # | 727 | # |
| 728 | # I2C Algorithms | 728 | # I2C Algorithms |
| 729 | # | 729 | # |
| 730 | # CONFIG_I2C_ALGOBIT is not set | 730 | CONFIG_I2C_ALGOBIT=m |
| 731 | # CONFIG_I2C_ALGOPCF is not set | 731 | # CONFIG_I2C_ALGOPCF is not set |
| 732 | # CONFIG_I2C_ALGOPCA is not set | 732 | # CONFIG_I2C_ALGOPCA is not set |
| 733 | 733 | ||
| 734 | # | 734 | # |
| 735 | # I2C Hardware Bus support | 735 | # I2C Hardware Bus support |
| 736 | # | 736 | # |
| 737 | CONFIG_I2C_AT91=m | 737 | CONFIG_I2C_GPIO=m |
| 738 | # CONFIG_I2C_OCORES is not set | 738 | # CONFIG_I2C_OCORES is not set |
| 739 | # CONFIG_I2C_PARPORT_LIGHT is not set | 739 | # CONFIG_I2C_PARPORT_LIGHT is not set |
| 740 | # CONFIG_I2C_STUB is not set | 740 | # CONFIG_I2C_STUB is not set |
diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig new file mode 100644 index 000000000000..484dc9739dfc --- /dev/null +++ b/arch/arm/configs/sam9_l9260_defconfig | |||
| @@ -0,0 +1,1098 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.23 | ||
| 4 | # Sun Oct 14 02:01:07 2007 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | # CONFIG_GENERIC_TIME is not set | ||
| 10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 18 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 20 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 22 | CONFIG_GENERIC_HWEIGHT=y | ||
| 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 24 | CONFIG_ZONE_DMA=y | ||
| 25 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 26 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 27 | |||
| 28 | # | ||
| 29 | # General setup | ||
| 30 | # | ||
| 31 | CONFIG_EXPERIMENTAL=y | ||
| 32 | CONFIG_BROKEN_ON_SMP=y | ||
| 33 | CONFIG_LOCK_KERNEL=y | ||
| 34 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 35 | CONFIG_LOCALVERSION="" | ||
| 36 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 37 | CONFIG_SWAP=y | ||
| 38 | CONFIG_SYSVIPC=y | ||
| 39 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 40 | CONFIG_POSIX_MQUEUE=y | ||
| 41 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 42 | CONFIG_BSD_PROCESS_ACCT_V3=y | ||
| 43 | # CONFIG_TASKSTATS is not set | ||
| 44 | # CONFIG_USER_NS is not set | ||
| 45 | CONFIG_AUDIT=y | ||
| 46 | # CONFIG_IKCONFIG is not set | ||
| 47 | CONFIG_LOG_BUF_SHIFT=15 | ||
| 48 | CONFIG_SYSFS_DEPRECATED=y | ||
| 49 | # CONFIG_RELAY is not set | ||
| 50 | CONFIG_BLK_DEV_INITRD=y | ||
| 51 | CONFIG_INITRAMFS_SOURCE="" | ||
| 52 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 53 | CONFIG_SYSCTL=y | ||
| 54 | # CONFIG_EMBEDDED is not set | ||
| 55 | CONFIG_UID16=y | ||
| 56 | CONFIG_SYSCTL_SYSCALL=y | ||
| 57 | CONFIG_KALLSYMS=y | ||
| 58 | # CONFIG_KALLSYMS_ALL is not set | ||
| 59 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 60 | CONFIG_HOTPLUG=y | ||
| 61 | CONFIG_PRINTK=y | ||
| 62 | CONFIG_BUG=y | ||
| 63 | CONFIG_ELF_CORE=y | ||
| 64 | CONFIG_BASE_FULL=y | ||
| 65 | CONFIG_FUTEX=y | ||
| 66 | CONFIG_ANON_INODES=y | ||
| 67 | CONFIG_EPOLL=y | ||
| 68 | CONFIG_SIGNALFD=y | ||
| 69 | CONFIG_EVENTFD=y | ||
| 70 | CONFIG_SHMEM=y | ||
| 71 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 72 | CONFIG_SLAB=y | ||
| 73 | # CONFIG_SLUB is not set | ||
| 74 | # CONFIG_SLOB is not set | ||
| 75 | CONFIG_RT_MUTEXES=y | ||
| 76 | # CONFIG_TINY_SHMEM is not set | ||
| 77 | CONFIG_BASE_SMALL=0 | ||
| 78 | # CONFIG_MODULES is not set | ||
| 79 | CONFIG_BLOCK=y | ||
| 80 | CONFIG_LBD=y | ||
| 81 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 82 | CONFIG_LSF=y | ||
| 83 | # CONFIG_BLK_DEV_BSG is not set | ||
| 84 | |||
| 85 | # | ||
| 86 | # IO Schedulers | ||
| 87 | # | ||
| 88 | CONFIG_IOSCHED_NOOP=y | ||
| 89 | CONFIG_IOSCHED_AS=y | ||
| 90 | CONFIG_IOSCHED_DEADLINE=y | ||
| 91 | CONFIG_IOSCHED_CFQ=y | ||
| 92 | # CONFIG_DEFAULT_AS is not set | ||
| 93 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 94 | CONFIG_DEFAULT_CFQ=y | ||
| 95 | # CONFIG_DEFAULT_NOOP is not set | ||
| 96 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 97 | |||
| 98 | # | ||
| 99 | # System Type | ||
| 100 | # | ||
| 101 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 102 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 103 | # CONFIG_ARCH_REALVIEW is not set | ||
| 104 | # CONFIG_ARCH_VERSATILE is not set | ||
| 105 | CONFIG_ARCH_AT91=y | ||
| 106 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 107 | # CONFIG_ARCH_CLPS711X is not set | ||
| 108 | # CONFIG_ARCH_CO285 is not set | ||
| 109 | # CONFIG_ARCH_EBSA110 is not set | ||
| 110 | # CONFIG_ARCH_EP93XX is not set | ||
| 111 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 112 | # CONFIG_ARCH_NETX is not set | ||
| 113 | # CONFIG_ARCH_H720X is not set | ||
| 114 | # CONFIG_ARCH_IMX is not set | ||
| 115 | # CONFIG_ARCH_IOP13XX is not set | ||
| 116 | # CONFIG_ARCH_IOP32X is not set | ||
| 117 | # CONFIG_ARCH_IOP33X is not set | ||
| 118 | # CONFIG_ARCH_IXP23XX is not set | ||
| 119 | # CONFIG_ARCH_IXP2000 is not set | ||
| 120 | # CONFIG_ARCH_IXP4XX is not set | ||
| 121 | # CONFIG_ARCH_L7200 is not set | ||
| 122 | # CONFIG_ARCH_KS8695 is not set | ||
| 123 | # CONFIG_ARCH_NS9XXX is not set | ||
| 124 | # CONFIG_ARCH_MXC is not set | ||
| 125 | # CONFIG_ARCH_PNX4008 is not set | ||
| 126 | # CONFIG_ARCH_PXA is not set | ||
| 127 | # CONFIG_ARCH_RPC is not set | ||
| 128 | # CONFIG_ARCH_SA1100 is not set | ||
| 129 | # CONFIG_ARCH_S3C2410 is not set | ||
| 130 | # CONFIG_ARCH_SHARK is not set | ||
| 131 | # CONFIG_ARCH_LH7A40X is not set | ||
| 132 | # CONFIG_ARCH_DAVINCI is not set | ||
| 133 | # CONFIG_ARCH_OMAP is not set | ||
| 134 | |||
| 135 | # | ||
| 136 | # Boot options | ||
| 137 | # | ||
| 138 | |||
| 139 | # | ||
| 140 | # Power management | ||
| 141 | # | ||
| 142 | |||
| 143 | # | ||
| 144 | # Atmel AT91 System-on-Chip | ||
| 145 | # | ||
| 146 | # CONFIG_ARCH_AT91RM9200 is not set | ||
| 147 | CONFIG_ARCH_AT91SAM9260=y | ||
| 148 | # CONFIG_ARCH_AT91SAM9261 is not set | ||
| 149 | # CONFIG_ARCH_AT91SAM9263 is not set | ||
| 150 | # CONFIG_ARCH_AT91SAM9RL is not set | ||
| 151 | |||
| 152 | # | ||
| 153 | # AT91SAM9260 Variants | ||
| 154 | # | ||
| 155 | # CONFIG_ARCH_AT91SAM9260_SAM9XE is not set | ||
| 156 | |||
| 157 | # | ||
| 158 | # AT91SAM9260 / AT91SAM9XE Board Type | ||
| 159 | # | ||
| 160 | # CONFIG_MACH_AT91SAM9260EK is not set | ||
| 161 | # CONFIG_MACH_CAM60 is not set | ||
| 162 | CONFIG_MACH_SAM9_L9260=y | ||
| 163 | |||
| 164 | # | ||
| 165 | # AT91 Board Options | ||
| 166 | # | ||
| 167 | CONFIG_MTD_AT91_DATAFLASH_CARD=y | ||
| 168 | |||
| 169 | # | ||
| 170 | # AT91 Feature Selections | ||
| 171 | # | ||
| 172 | # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set | ||
| 173 | # CONFIG_ATMEL_TCLIB is not set | ||
| 174 | |||
| 175 | # | ||
| 176 | # Processor Type | ||
| 177 | # | ||
| 178 | CONFIG_CPU_32=y | ||
| 179 | CONFIG_CPU_ARM926T=y | ||
| 180 | CONFIG_CPU_32v5=y | ||
| 181 | CONFIG_CPU_ABRT_EV5TJ=y | ||
| 182 | CONFIG_CPU_CACHE_VIVT=y | ||
| 183 | CONFIG_CPU_COPY_V4WB=y | ||
| 184 | CONFIG_CPU_TLB_V4WBI=y | ||
| 185 | CONFIG_CPU_CP15=y | ||
| 186 | CONFIG_CPU_CP15_MMU=y | ||
| 187 | |||
| 188 | # | ||
| 189 | # Processor Features | ||
| 190 | # | ||
| 191 | CONFIG_ARM_THUMB=y | ||
| 192 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 193 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 194 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 195 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set | ||
| 196 | # CONFIG_OUTER_CACHE is not set | ||
| 197 | |||
| 198 | # | ||
| 199 | # Bus support | ||
| 200 | # | ||
| 201 | # CONFIG_PCI_SYSCALL is not set | ||
| 202 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 203 | |||
| 204 | # | ||
| 205 | # PCCARD (PCMCIA/CardBus) support | ||
| 206 | # | ||
| 207 | # CONFIG_PCCARD is not set | ||
| 208 | |||
| 209 | # | ||
| 210 | # Kernel Features | ||
| 211 | # | ||
| 212 | # CONFIG_TICK_ONESHOT is not set | ||
| 213 | CONFIG_PREEMPT=y | ||
| 214 | # CONFIG_NO_IDLE_HZ is not set | ||
| 215 | CONFIG_HZ=100 | ||
| 216 | # CONFIG_AEABI is not set | ||
| 217 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | ||
| 218 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 219 | CONFIG_FLATMEM_MANUAL=y | ||
| 220 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 221 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 222 | CONFIG_FLATMEM=y | ||
| 223 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 224 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 225 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 226 | # CONFIG_RESOURCES_64BIT is not set | ||
| 227 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 228 | CONFIG_BOUNCE=y | ||
| 229 | CONFIG_VIRT_TO_BUS=y | ||
| 230 | CONFIG_LEDS=y | ||
| 231 | CONFIG_LEDS_TIMER=y | ||
| 232 | CONFIG_LEDS_CPU=y | ||
| 233 | CONFIG_ALIGNMENT_TRAP=y | ||
| 234 | |||
| 235 | # | ||
| 236 | # Boot options | ||
| 237 | # | ||
| 238 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 239 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 240 | CONFIG_CMDLINE="console=ttyS0,115200 mem=64M initrd=0x21100000,4194304 root=/dev/ram0 rw" | ||
| 241 | # CONFIG_XIP_KERNEL is not set | ||
| 242 | # CONFIG_KEXEC is not set | ||
| 243 | |||
| 244 | # | ||
| 245 | # Floating point emulation | ||
| 246 | # | ||
| 247 | |||
| 248 | # | ||
| 249 | # At least one emulation must be selected | ||
| 250 | # | ||
| 251 | CONFIG_FPE_NWFPE=y | ||
| 252 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 253 | # CONFIG_FPE_FASTFPE is not set | ||
| 254 | # CONFIG_VFP is not set | ||
| 255 | |||
| 256 | # | ||
| 257 | # Userspace binary formats | ||
| 258 | # | ||
| 259 | CONFIG_BINFMT_ELF=y | ||
| 260 | # CONFIG_BINFMT_AOUT is not set | ||
| 261 | # CONFIG_BINFMT_MISC is not set | ||
| 262 | # CONFIG_ARTHUR is not set | ||
| 263 | |||
| 264 | # | ||
| 265 | # Power management options | ||
| 266 | # | ||
| 267 | # CONFIG_PM is not set | ||
| 268 | CONFIG_SUSPEND_UP_POSSIBLE=y | ||
| 269 | |||
| 270 | # | ||
| 271 | # Networking | ||
| 272 | # | ||
| 273 | CONFIG_NET=y | ||
| 274 | |||
| 275 | # | ||
| 276 | # Networking options | ||
| 277 | # | ||
| 278 | CONFIG_PACKET=y | ||
| 279 | CONFIG_PACKET_MMAP=y | ||
| 280 | CONFIG_UNIX=y | ||
| 281 | CONFIG_XFRM=y | ||
| 282 | CONFIG_XFRM_USER=y | ||
| 283 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 284 | # CONFIG_XFRM_MIGRATE is not set | ||
| 285 | CONFIG_NET_KEY=y | ||
| 286 | # CONFIG_NET_KEY_MIGRATE is not set | ||
| 287 | CONFIG_INET=y | ||
| 288 | # CONFIG_IP_MULTICAST is not set | ||
| 289 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 290 | CONFIG_IP_FIB_HASH=y | ||
| 291 | # CONFIG_IP_PNP is not set | ||
| 292 | # CONFIG_NET_IPIP is not set | ||
| 293 | # CONFIG_NET_IPGRE is not set | ||
| 294 | # CONFIG_ARPD is not set | ||
| 295 | # CONFIG_SYN_COOKIES is not set | ||
| 296 | # CONFIG_INET_AH is not set | ||
| 297 | # CONFIG_INET_ESP is not set | ||
| 298 | # CONFIG_INET_IPCOMP is not set | ||
| 299 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 300 | # CONFIG_INET_TUNNEL is not set | ||
| 301 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 302 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 303 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 304 | CONFIG_INET_DIAG=y | ||
| 305 | CONFIG_INET_TCP_DIAG=y | ||
| 306 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 307 | CONFIG_TCP_CONG_CUBIC=y | ||
| 308 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 309 | # CONFIG_TCP_MD5SIG is not set | ||
| 310 | # CONFIG_IPV6 is not set | ||
| 311 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 312 | # CONFIG_INET6_TUNNEL is not set | ||
| 313 | # CONFIG_NETWORK_SECMARK is not set | ||
| 314 | # CONFIG_NETFILTER is not set | ||
| 315 | # CONFIG_IP_DCCP is not set | ||
| 316 | # CONFIG_IP_SCTP is not set | ||
| 317 | # CONFIG_TIPC is not set | ||
| 318 | # CONFIG_ATM is not set | ||
| 319 | # CONFIG_BRIDGE is not set | ||
| 320 | # CONFIG_VLAN_8021Q is not set | ||
| 321 | # CONFIG_DECNET is not set | ||
| 322 | # CONFIG_LLC2 is not set | ||
| 323 | # CONFIG_IPX is not set | ||
| 324 | # CONFIG_ATALK is not set | ||
| 325 | # CONFIG_X25 is not set | ||
| 326 | # CONFIG_LAPB is not set | ||
| 327 | # CONFIG_ECONET is not set | ||
| 328 | # CONFIG_WAN_ROUTER is not set | ||
| 329 | |||
| 330 | # | ||
| 331 | # QoS and/or fair queueing | ||
| 332 | # | ||
| 333 | # CONFIG_NET_SCHED is not set | ||
| 334 | |||
| 335 | # | ||
| 336 | # Network testing | ||
| 337 | # | ||
| 338 | # CONFIG_NET_PKTGEN is not set | ||
| 339 | # CONFIG_HAMRADIO is not set | ||
| 340 | # CONFIG_IRDA is not set | ||
| 341 | # CONFIG_BT is not set | ||
| 342 | # CONFIG_AF_RXRPC is not set | ||
| 343 | |||
| 344 | # | ||
| 345 | # Wireless | ||
| 346 | # | ||
| 347 | # CONFIG_CFG80211 is not set | ||
| 348 | # CONFIG_WIRELESS_EXT is not set | ||
| 349 | # CONFIG_MAC80211 is not set | ||
| 350 | # CONFIG_IEEE80211 is not set | ||
| 351 | # CONFIG_RFKILL is not set | ||
| 352 | # CONFIG_NET_9P is not set | ||
| 353 | |||
| 354 | # | ||
| 355 | # Device Drivers | ||
| 356 | # | ||
| 357 | |||
| 358 | # | ||
| 359 | # Generic Driver Options | ||
| 360 | # | ||
| 361 | CONFIG_STANDALONE=y | ||
| 362 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 363 | CONFIG_FW_LOADER=y | ||
| 364 | # CONFIG_DEBUG_DRIVER is not set | ||
| 365 | # CONFIG_DEBUG_DEVRES is not set | ||
| 366 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 367 | # CONFIG_CONNECTOR is not set | ||
| 368 | CONFIG_MTD=y | ||
| 369 | # CONFIG_MTD_DEBUG is not set | ||
| 370 | # CONFIG_MTD_CONCAT is not set | ||
| 371 | CONFIG_MTD_PARTITIONS=y | ||
| 372 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 373 | # CONFIG_MTD_CMDLINE_PARTS is not set | ||
| 374 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 375 | |||
| 376 | # | ||
| 377 | # User Modules And Translation Layers | ||
| 378 | # | ||
| 379 | CONFIG_MTD_CHAR=y | ||
| 380 | CONFIG_MTD_BLKDEVS=y | ||
| 381 | CONFIG_MTD_BLOCK=y | ||
| 382 | # CONFIG_FTL is not set | ||
| 383 | # CONFIG_NFTL is not set | ||
| 384 | # CONFIG_INFTL is not set | ||
| 385 | # CONFIG_RFD_FTL is not set | ||
| 386 | # CONFIG_SSFDC is not set | ||
| 387 | |||
| 388 | # | ||
| 389 | # RAM/ROM/Flash chip drivers | ||
| 390 | # | ||
| 391 | # CONFIG_MTD_CFI is not set | ||
| 392 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 393 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 394 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 395 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 396 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 397 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 398 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 399 | CONFIG_MTD_CFI_I1=y | ||
| 400 | CONFIG_MTD_CFI_I2=y | ||
| 401 | # CONFIG_MTD_CFI_I4 is not set | ||
| 402 | # CONFIG_MTD_CFI_I8 is not set | ||
| 403 | # CONFIG_MTD_RAM is not set | ||
| 404 | # CONFIG_MTD_ROM is not set | ||
| 405 | # CONFIG_MTD_ABSENT is not set | ||
| 406 | |||
| 407 | # | ||
| 408 | # Mapping drivers for chip access | ||
| 409 | # | ||
| 410 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 411 | # CONFIG_MTD_PLATRAM is not set | ||
| 412 | |||
| 413 | # | ||
| 414 | # Self-contained MTD device drivers | ||
| 415 | # | ||
| 416 | # CONFIG_MTD_SLRAM is not set | ||
| 417 | # CONFIG_MTD_PHRAM is not set | ||
| 418 | # CONFIG_MTD_MTDRAM is not set | ||
| 419 | CONFIG_MTD_BLOCK2MTD=y | ||
| 420 | |||
| 421 | # | ||
| 422 | # Disk-On-Chip Device Drivers | ||
| 423 | # | ||
| 424 | # CONFIG_MTD_DOC2000 is not set | ||
| 425 | # CONFIG_MTD_DOC2001 is not set | ||
| 426 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 427 | CONFIG_MTD_NAND=y | ||
| 428 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
| 429 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 430 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 431 | CONFIG_MTD_NAND_IDS=y | ||
| 432 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 433 | CONFIG_MTD_NAND_AT91=y | ||
| 434 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 435 | CONFIG_MTD_NAND_PLATFORM=y | ||
| 436 | # CONFIG_MTD_ONENAND is not set | ||
| 437 | |||
| 438 | # | ||
| 439 | # UBI - Unsorted block images | ||
| 440 | # | ||
| 441 | CONFIG_MTD_UBI=y | ||
| 442 | CONFIG_MTD_UBI_WL_THRESHOLD=4096 | ||
| 443 | CONFIG_MTD_UBI_BEB_RESERVE=3 | ||
| 444 | CONFIG_MTD_UBI_GLUEBI=y | ||
| 445 | |||
| 446 | # | ||
| 447 | # UBI debugging options | ||
| 448 | # | ||
| 449 | # CONFIG_MTD_UBI_DEBUG is not set | ||
| 450 | # CONFIG_PARPORT is not set | ||
| 451 | CONFIG_BLK_DEV=y | ||
| 452 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 453 | CONFIG_BLK_DEV_LOOP=y | ||
| 454 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 455 | # CONFIG_BLK_DEV_NBD is not set | ||
| 456 | # CONFIG_BLK_DEV_UB is not set | ||
| 457 | CONFIG_BLK_DEV_RAM=y | ||
| 458 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 459 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 460 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | ||
| 461 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 462 | # CONFIG_ATA_OVER_ETH is not set | ||
| 463 | |||
| 464 | # | ||
| 465 | # SCSI device support | ||
| 466 | # | ||
| 467 | CONFIG_RAID_ATTRS=y | ||
| 468 | CONFIG_SCSI=y | ||
| 469 | CONFIG_SCSI_DMA=y | ||
| 470 | # CONFIG_SCSI_TGT is not set | ||
| 471 | # CONFIG_SCSI_NETLINK is not set | ||
| 472 | CONFIG_SCSI_PROC_FS=y | ||
| 473 | |||
| 474 | # | ||
| 475 | # SCSI support type (disk, tape, CD-ROM) | ||
| 476 | # | ||
| 477 | CONFIG_BLK_DEV_SD=y | ||
| 478 | # CONFIG_CHR_DEV_ST is not set | ||
| 479 | # CONFIG_CHR_DEV_OSST is not set | ||
| 480 | # CONFIG_BLK_DEV_SR is not set | ||
| 481 | CONFIG_CHR_DEV_SG=y | ||
| 482 | # CONFIG_CHR_DEV_SCH is not set | ||
| 483 | |||
| 484 | # | ||
| 485 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 486 | # | ||
| 487 | CONFIG_SCSI_MULTI_LUN=y | ||
| 488 | CONFIG_SCSI_CONSTANTS=y | ||
| 489 | CONFIG_SCSI_LOGGING=y | ||
| 490 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 491 | |||
| 492 | # | ||
| 493 | # SCSI Transports | ||
| 494 | # | ||
| 495 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 496 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 497 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 498 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 499 | # CONFIG_SCSI_LOWLEVEL is not set | ||
| 500 | # CONFIG_ATA is not set | ||
| 501 | # CONFIG_MD is not set | ||
| 502 | CONFIG_NETDEVICES=y | ||
| 503 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 504 | # CONFIG_DUMMY is not set | ||
| 505 | # CONFIG_BONDING is not set | ||
| 506 | # CONFIG_MACVLAN is not set | ||
| 507 | # CONFIG_EQUALIZER is not set | ||
| 508 | # CONFIG_TUN is not set | ||
| 509 | CONFIG_PHYLIB=y | ||
| 510 | |||
| 511 | # | ||
| 512 | # MII PHY device drivers | ||
| 513 | # | ||
| 514 | # CONFIG_MARVELL_PHY is not set | ||
| 515 | # CONFIG_DAVICOM_PHY is not set | ||
| 516 | # CONFIG_QSEMI_PHY is not set | ||
| 517 | # CONFIG_LXT_PHY is not set | ||
| 518 | # CONFIG_CICADA_PHY is not set | ||
| 519 | # CONFIG_VITESSE_PHY is not set | ||
| 520 | # CONFIG_SMSC_PHY is not set | ||
| 521 | # CONFIG_BROADCOM_PHY is not set | ||
| 522 | # CONFIG_ICPLUS_PHY is not set | ||
| 523 | # CONFIG_FIXED_PHY is not set | ||
| 524 | CONFIG_NET_ETHERNET=y | ||
| 525 | CONFIG_MII=y | ||
| 526 | CONFIG_MACB=y | ||
| 527 | # CONFIG_AX88796 is not set | ||
| 528 | # CONFIG_SMC91X is not set | ||
| 529 | # CONFIG_DM9000 is not set | ||
| 530 | # CONFIG_NETDEV_1000 is not set | ||
| 531 | # CONFIG_NETDEV_10000 is not set | ||
| 532 | |||
| 533 | # | ||
| 534 | # Wireless LAN | ||
| 535 | # | ||
| 536 | # CONFIG_WLAN_PRE80211 is not set | ||
| 537 | # CONFIG_WLAN_80211 is not set | ||
| 538 | |||
| 539 | # | ||
| 540 | # USB Network Adapters | ||
| 541 | # | ||
| 542 | # CONFIG_USB_CATC is not set | ||
| 543 | # CONFIG_USB_KAWETH is not set | ||
| 544 | # CONFIG_USB_PEGASUS is not set | ||
| 545 | # CONFIG_USB_RTL8150 is not set | ||
| 546 | # CONFIG_USB_USBNET_MII is not set | ||
| 547 | # CONFIG_USB_USBNET is not set | ||
| 548 | # CONFIG_WAN is not set | ||
| 549 | # CONFIG_PPP is not set | ||
| 550 | # CONFIG_SLIP is not set | ||
| 551 | # CONFIG_SHAPER is not set | ||
| 552 | # CONFIG_NETCONSOLE is not set | ||
| 553 | # CONFIG_NETPOLL is not set | ||
| 554 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 555 | # CONFIG_ISDN is not set | ||
| 556 | |||
| 557 | # | ||
| 558 | # Input device support | ||
| 559 | # | ||
| 560 | CONFIG_INPUT=y | ||
| 561 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 562 | # CONFIG_INPUT_POLLDEV is not set | ||
| 563 | |||
| 564 | # | ||
| 565 | # Userland interfaces | ||
| 566 | # | ||
| 567 | CONFIG_INPUT_MOUSEDEV=y | ||
| 568 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 569 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 570 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 571 | # CONFIG_INPUT_JOYDEV is not set | ||
| 572 | # CONFIG_INPUT_TSDEV is not set | ||
| 573 | # CONFIG_INPUT_EVDEV is not set | ||
| 574 | # CONFIG_INPUT_EVBUG is not set | ||
| 575 | |||
| 576 | # | ||
| 577 | # Input Device Drivers | ||
| 578 | # | ||
| 579 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 580 | # CONFIG_INPUT_MOUSE is not set | ||
| 581 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 582 | # CONFIG_INPUT_TABLET is not set | ||
| 583 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 584 | # CONFIG_INPUT_MISC is not set | ||
| 585 | |||
| 586 | # | ||
| 587 | # Hardware I/O ports | ||
| 588 | # | ||
| 589 | # CONFIG_SERIO is not set | ||
| 590 | # CONFIG_GAMEPORT is not set | ||
| 591 | |||
| 592 | # | ||
| 593 | # Character devices | ||
| 594 | # | ||
| 595 | CONFIG_VT=y | ||
| 596 | CONFIG_VT_CONSOLE=y | ||
| 597 | CONFIG_HW_CONSOLE=y | ||
| 598 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 599 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 600 | |||
| 601 | # | ||
| 602 | # Serial drivers | ||
| 603 | # | ||
| 604 | # CONFIG_SERIAL_8250 is not set | ||
| 605 | |||
| 606 | # | ||
| 607 | # Non-8250 serial port support | ||
| 608 | # | ||
| 609 | CONFIG_SERIAL_ATMEL=y | ||
| 610 | CONFIG_SERIAL_ATMEL_CONSOLE=y | ||
| 611 | # CONFIG_SERIAL_ATMEL_TTYAT is not set | ||
| 612 | CONFIG_SERIAL_CORE=y | ||
| 613 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 614 | CONFIG_UNIX98_PTYS=y | ||
| 615 | CONFIG_LEGACY_PTYS=y | ||
| 616 | CONFIG_LEGACY_PTY_COUNT=16 | ||
| 617 | # CONFIG_IPMI_HANDLER is not set | ||
| 618 | # CONFIG_WATCHDOG is not set | ||
| 619 | # CONFIG_HW_RANDOM is not set | ||
| 620 | # CONFIG_NVRAM is not set | ||
| 621 | # CONFIG_R3964 is not set | ||
| 622 | # CONFIG_RAW_DRIVER is not set | ||
| 623 | # CONFIG_TCG_TPM is not set | ||
| 624 | # CONFIG_I2C is not set | ||
| 625 | |||
| 626 | # | ||
| 627 | # SPI support | ||
| 628 | # | ||
| 629 | # CONFIG_SPI is not set | ||
| 630 | # CONFIG_SPI_MASTER is not set | ||
| 631 | # CONFIG_W1 is not set | ||
| 632 | # CONFIG_HWMON is not set | ||
| 633 | # CONFIG_MISC_DEVICES is not set | ||
| 634 | |||
| 635 | # | ||
| 636 | # Multifunction device drivers | ||
| 637 | # | ||
| 638 | # CONFIG_MFD_SM501 is not set | ||
| 639 | CONFIG_NEW_LEDS=y | ||
| 640 | CONFIG_LEDS_CLASS=y | ||
| 641 | |||
| 642 | # | ||
| 643 | # LED drivers | ||
| 644 | # | ||
| 645 | CONFIG_LEDS_GPIO=y | ||
| 646 | |||
| 647 | # | ||
| 648 | # LED Triggers | ||
| 649 | # | ||
| 650 | CONFIG_LEDS_TRIGGERS=y | ||
| 651 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 652 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 653 | |||
| 654 | # | ||
| 655 | # Multimedia devices | ||
| 656 | # | ||
| 657 | # CONFIG_VIDEO_DEV is not set | ||
| 658 | # CONFIG_DVB_CORE is not set | ||
| 659 | # CONFIG_DAB is not set | ||
| 660 | |||
| 661 | # | ||
| 662 | # Graphics support | ||
| 663 | # | ||
| 664 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 665 | |||
| 666 | # | ||
| 667 | # Display device support | ||
| 668 | # | ||
| 669 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 670 | # CONFIG_VGASTATE is not set | ||
| 671 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 672 | # CONFIG_FB is not set | ||
| 673 | |||
| 674 | # | ||
| 675 | # Console display driver support | ||
| 676 | # | ||
| 677 | # CONFIG_VGA_CONSOLE is not set | ||
| 678 | CONFIG_DUMMY_CONSOLE=y | ||
| 679 | |||
| 680 | # | ||
| 681 | # Sound | ||
| 682 | # | ||
| 683 | # CONFIG_SOUND is not set | ||
| 684 | # CONFIG_HID_SUPPORT is not set | ||
| 685 | CONFIG_USB_SUPPORT=y | ||
| 686 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 687 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 688 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 689 | CONFIG_USB=y | ||
| 690 | # CONFIG_USB_DEBUG is not set | ||
| 691 | |||
| 692 | # | ||
| 693 | # Miscellaneous USB options | ||
| 694 | # | ||
| 695 | CONFIG_USB_DEVICEFS=y | ||
| 696 | CONFIG_USB_DEVICE_CLASS=y | ||
| 697 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 698 | # CONFIG_USB_OTG is not set | ||
| 699 | |||
| 700 | # | ||
| 701 | # USB Host Controller Drivers | ||
| 702 | # | ||
| 703 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 704 | CONFIG_USB_OHCI_HCD=y | ||
| 705 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
| 706 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 707 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
| 708 | # CONFIG_USB_SL811_HCD is not set | ||
| 709 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 710 | |||
| 711 | # | ||
| 712 | # USB Device Class drivers | ||
| 713 | # | ||
| 714 | # CONFIG_USB_ACM is not set | ||
| 715 | # CONFIG_USB_PRINTER is not set | ||
| 716 | |||
| 717 | # | ||
| 718 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
| 719 | # | ||
| 720 | |||
| 721 | # | ||
| 722 | # may also be needed; see USB_STORAGE Help for more information | ||
| 723 | # | ||
| 724 | CONFIG_USB_STORAGE=y | ||
| 725 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 726 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 727 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 728 | # CONFIG_USB_STORAGE_DPCM is not set | ||
| 729 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 730 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 731 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 732 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 733 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 734 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 735 | CONFIG_USB_LIBUSUAL=y | ||
| 736 | |||
| 737 | # | ||
| 738 | # USB Imaging devices | ||
| 739 | # | ||
| 740 | # CONFIG_USB_MDC800 is not set | ||
| 741 | # CONFIG_USB_MICROTEK is not set | ||
| 742 | # CONFIG_USB_MON is not set | ||
| 743 | |||
| 744 | # | ||
| 745 | # USB port drivers | ||
| 746 | # | ||
| 747 | |||
| 748 | # | ||
| 749 | # USB Serial Converter support | ||
| 750 | # | ||
| 751 | # CONFIG_USB_SERIAL is not set | ||
| 752 | |||
| 753 | # | ||
| 754 | # USB Miscellaneous drivers | ||
| 755 | # | ||
| 756 | # CONFIG_USB_EMI62 is not set | ||
| 757 | # CONFIG_USB_EMI26 is not set | ||
| 758 | # CONFIG_USB_ADUTUX is not set | ||
| 759 | # CONFIG_USB_AUERSWALD is not set | ||
| 760 | # CONFIG_USB_RIO500 is not set | ||
| 761 | # CONFIG_USB_LEGOTOWER is not set | ||
| 762 | # CONFIG_USB_LCD is not set | ||
| 763 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 764 | # CONFIG_USB_LED is not set | ||
| 765 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 766 | # CONFIG_USB_CYTHERM is not set | ||
| 767 | # CONFIG_USB_PHIDGET is not set | ||
| 768 | # CONFIG_USB_IDMOUSE is not set | ||
| 769 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 770 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 771 | # CONFIG_USB_LD is not set | ||
| 772 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 773 | # CONFIG_USB_IOWARRIOR is not set | ||
| 774 | # CONFIG_USB_TEST is not set | ||
| 775 | |||
| 776 | # | ||
| 777 | # USB DSL modem support | ||
| 778 | # | ||
| 779 | |||
| 780 | # | ||
| 781 | # USB Gadget Support | ||
| 782 | # | ||
| 783 | CONFIG_USB_GADGET=y | ||
| 784 | # CONFIG_USB_GADGET_DEBUG is not set | ||
| 785 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
| 786 | CONFIG_USB_GADGET_SELECTED=y | ||
| 787 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 788 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 789 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 790 | # CONFIG_USB_GADGET_PXA2XX is not set | ||
| 791 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 792 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 793 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 794 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 795 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 796 | CONFIG_USB_GADGET_AT91=y | ||
| 797 | CONFIG_USB_AT91=y | ||
| 798 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 799 | # CONFIG_USB_GADGET_DUALSPEED is not set | ||
| 800 | # CONFIG_USB_ZERO is not set | ||
| 801 | CONFIG_USB_ETH=y | ||
| 802 | CONFIG_USB_ETH_RNDIS=y | ||
| 803 | # CONFIG_USB_GADGETFS is not set | ||
| 804 | # CONFIG_USB_FILE_STORAGE is not set | ||
| 805 | # CONFIG_USB_G_SERIAL is not set | ||
| 806 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 807 | CONFIG_MMC=y | ||
| 808 | CONFIG_MMC_DEBUG=y | ||
| 809 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 810 | |||
| 811 | # | ||
| 812 | # MMC/SD Card Drivers | ||
| 813 | # | ||
| 814 | CONFIG_MMC_BLOCK=y | ||
| 815 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 816 | |||
| 817 | # | ||
| 818 | # MMC/SD Host Controller Drivers | ||
| 819 | # | ||
| 820 | CONFIG_MMC_AT91=y | ||
| 821 | CONFIG_RTC_LIB=y | ||
| 822 | CONFIG_RTC_CLASS=y | ||
| 823 | CONFIG_RTC_HCTOSYS=y | ||
| 824 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 825 | # CONFIG_RTC_DEBUG is not set | ||
| 826 | |||
| 827 | # | ||
| 828 | # RTC interfaces | ||
| 829 | # | ||
| 830 | CONFIG_RTC_INTF_SYSFS=y | ||
| 831 | CONFIG_RTC_INTF_PROC=y | ||
| 832 | CONFIG_RTC_INTF_DEV=y | ||
| 833 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 834 | # CONFIG_RTC_DRV_TEST is not set | ||
| 835 | |||
| 836 | # | ||
| 837 | # SPI RTC drivers | ||
| 838 | # | ||
| 839 | |||
| 840 | # | ||
| 841 | # Platform RTC drivers | ||
| 842 | # | ||
| 843 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 844 | CONFIG_RTC_DRV_DS1553=y | ||
| 845 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 846 | CONFIG_RTC_DRV_DS1742=y | ||
| 847 | CONFIG_RTC_DRV_M48T86=y | ||
| 848 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 849 | CONFIG_RTC_DRV_V3020=y | ||
| 850 | |||
| 851 | # | ||
| 852 | # on-CPU RTC drivers | ||
| 853 | # | ||
| 854 | |||
| 855 | # | ||
| 856 | # DMA Engine support | ||
| 857 | # | ||
| 858 | # CONFIG_DMA_ENGINE is not set | ||
| 859 | |||
| 860 | # | ||
| 861 | # DMA Clients | ||
| 862 | # | ||
| 863 | |||
| 864 | # | ||
| 865 | # DMA Devices | ||
| 866 | # | ||
| 867 | |||
| 868 | # | ||
| 869 | # File systems | ||
| 870 | # | ||
| 871 | CONFIG_EXT2_FS=y | ||
| 872 | CONFIG_EXT2_FS_XATTR=y | ||
| 873 | CONFIG_EXT2_FS_POSIX_ACL=y | ||
| 874 | CONFIG_EXT2_FS_SECURITY=y | ||
| 875 | # CONFIG_EXT2_FS_XIP is not set | ||
| 876 | CONFIG_EXT3_FS=y | ||
| 877 | CONFIG_EXT3_FS_XATTR=y | ||
| 878 | CONFIG_EXT3_FS_POSIX_ACL=y | ||
| 879 | CONFIG_EXT3_FS_SECURITY=y | ||
| 880 | # CONFIG_EXT4DEV_FS is not set | ||
| 881 | CONFIG_JBD=y | ||
| 882 | # CONFIG_JBD_DEBUG is not set | ||
| 883 | CONFIG_FS_MBCACHE=y | ||
| 884 | # CONFIG_REISERFS_FS is not set | ||
| 885 | # CONFIG_JFS_FS is not set | ||
| 886 | CONFIG_FS_POSIX_ACL=y | ||
| 887 | # CONFIG_XFS_FS is not set | ||
| 888 | # CONFIG_GFS2_FS is not set | ||
| 889 | # CONFIG_OCFS2_FS is not set | ||
| 890 | # CONFIG_MINIX_FS is not set | ||
| 891 | # CONFIG_ROMFS_FS is not set | ||
| 892 | CONFIG_INOTIFY=y | ||
| 893 | CONFIG_INOTIFY_USER=y | ||
| 894 | # CONFIG_QUOTA is not set | ||
| 895 | CONFIG_DNOTIFY=y | ||
| 896 | # CONFIG_AUTOFS_FS is not set | ||
| 897 | # CONFIG_AUTOFS4_FS is not set | ||
| 898 | # CONFIG_FUSE_FS is not set | ||
| 899 | |||
| 900 | # | ||
| 901 | # CD-ROM/DVD Filesystems | ||
| 902 | # | ||
| 903 | # CONFIG_ISO9660_FS is not set | ||
| 904 | # CONFIG_UDF_FS is not set | ||
| 905 | |||
| 906 | # | ||
| 907 | # DOS/FAT/NT Filesystems | ||
| 908 | # | ||
| 909 | CONFIG_FAT_FS=y | ||
| 910 | CONFIG_MSDOS_FS=y | ||
| 911 | CONFIG_VFAT_FS=y | ||
| 912 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 913 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 914 | # CONFIG_NTFS_FS is not set | ||
| 915 | |||
| 916 | # | ||
| 917 | # Pseudo filesystems | ||
| 918 | # | ||
| 919 | CONFIG_PROC_FS=y | ||
| 920 | CONFIG_PROC_SYSCTL=y | ||
| 921 | CONFIG_SYSFS=y | ||
| 922 | CONFIG_TMPFS=y | ||
| 923 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 924 | # CONFIG_HUGETLB_PAGE is not set | ||
| 925 | CONFIG_RAMFS=y | ||
| 926 | # CONFIG_CONFIGFS_FS is not set | ||
| 927 | |||
| 928 | # | ||
| 929 | # Miscellaneous filesystems | ||
| 930 | # | ||
| 931 | # CONFIG_ADFS_FS is not set | ||
| 932 | # CONFIG_AFFS_FS is not set | ||
| 933 | # CONFIG_HFS_FS is not set | ||
| 934 | # CONFIG_HFSPLUS_FS is not set | ||
| 935 | # CONFIG_BEFS_FS is not set | ||
| 936 | # CONFIG_BFS_FS is not set | ||
| 937 | # CONFIG_EFS_FS is not set | ||
| 938 | CONFIG_JFFS2_FS=y | ||
| 939 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 940 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 941 | # CONFIG_JFFS2_SUMMARY is not set | ||
| 942 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 943 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | ||
| 944 | CONFIG_JFFS2_ZLIB=y | ||
| 945 | CONFIG_JFFS2_RTIME=y | ||
| 946 | # CONFIG_JFFS2_RUBIN is not set | ||
| 947 | # CONFIG_CRAMFS is not set | ||
| 948 | # CONFIG_VXFS_FS is not set | ||
| 949 | # CONFIG_HPFS_FS is not set | ||
| 950 | # CONFIG_QNX4FS_FS is not set | ||
| 951 | # CONFIG_SYSV_FS is not set | ||
| 952 | # CONFIG_UFS_FS is not set | ||
| 953 | |||
| 954 | # | ||
| 955 | # Network File Systems | ||
| 956 | # | ||
| 957 | CONFIG_NFS_FS=y | ||
| 958 | CONFIG_NFS_V3=y | ||
| 959 | # CONFIG_NFS_V3_ACL is not set | ||
| 960 | # CONFIG_NFS_V4 is not set | ||
| 961 | CONFIG_NFS_DIRECTIO=y | ||
| 962 | # CONFIG_NFSD is not set | ||
| 963 | CONFIG_LOCKD=y | ||
| 964 | CONFIG_LOCKD_V4=y | ||
| 965 | CONFIG_NFS_COMMON=y | ||
| 966 | CONFIG_SUNRPC=y | ||
| 967 | # CONFIG_SUNRPC_BIND34 is not set | ||
| 968 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 969 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 970 | # CONFIG_SMB_FS is not set | ||
| 971 | # CONFIG_CIFS is not set | ||
| 972 | # CONFIG_NCP_FS is not set | ||
| 973 | # CONFIG_CODA_FS is not set | ||
| 974 | # CONFIG_AFS_FS is not set | ||
| 975 | |||
| 976 | # | ||
| 977 | # Partition Types | ||
| 978 | # | ||
| 979 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 980 | CONFIG_MSDOS_PARTITION=y | ||
| 981 | |||
| 982 | # | ||
| 983 | # Native Language Support | ||
| 984 | # | ||
| 985 | CONFIG_NLS=y | ||
| 986 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 987 | CONFIG_NLS_CODEPAGE_437=y | ||
| 988 | CONFIG_NLS_CODEPAGE_737=y | ||
| 989 | CONFIG_NLS_CODEPAGE_775=y | ||
| 990 | CONFIG_NLS_CODEPAGE_850=y | ||
| 991 | CONFIG_NLS_CODEPAGE_852=y | ||
| 992 | CONFIG_NLS_CODEPAGE_855=y | ||
| 993 | CONFIG_NLS_CODEPAGE_857=y | ||
| 994 | CONFIG_NLS_CODEPAGE_860=y | ||
| 995 | CONFIG_NLS_CODEPAGE_861=y | ||
| 996 | CONFIG_NLS_CODEPAGE_862=y | ||
| 997 | CONFIG_NLS_CODEPAGE_863=y | ||
| 998 | CONFIG_NLS_CODEPAGE_864=y | ||
| 999 | CONFIG_NLS_CODEPAGE_865=y | ||
| 1000 | CONFIG_NLS_CODEPAGE_866=y | ||
| 1001 | CONFIG_NLS_CODEPAGE_869=y | ||
| 1002 | CONFIG_NLS_CODEPAGE_936=y | ||
| 1003 | CONFIG_NLS_CODEPAGE_950=y | ||
| 1004 | CONFIG_NLS_CODEPAGE_932=y | ||
| 1005 | CONFIG_NLS_CODEPAGE_949=y | ||
| 1006 | CONFIG_NLS_CODEPAGE_874=y | ||
| 1007 | CONFIG_NLS_ISO8859_8=y | ||
| 1008 | CONFIG_NLS_CODEPAGE_1250=y | ||
| 1009 | CONFIG_NLS_CODEPAGE_1251=y | ||
| 1010 | CONFIG_NLS_ASCII=y | ||
| 1011 | CONFIG_NLS_ISO8859_1=y | ||
| 1012 | CONFIG_NLS_ISO8859_2=y | ||
| 1013 | CONFIG_NLS_ISO8859_3=y | ||
| 1014 | CONFIG_NLS_ISO8859_4=y | ||
| 1015 | CONFIG_NLS_ISO8859_5=y | ||
| 1016 | CONFIG_NLS_ISO8859_6=y | ||
| 1017 | CONFIG_NLS_ISO8859_7=y | ||
| 1018 | CONFIG_NLS_ISO8859_9=y | ||
| 1019 | CONFIG_NLS_ISO8859_13=y | ||
| 1020 | CONFIG_NLS_ISO8859_14=y | ||
| 1021 | CONFIG_NLS_ISO8859_15=y | ||
| 1022 | CONFIG_NLS_KOI8_R=y | ||
| 1023 | CONFIG_NLS_KOI8_U=y | ||
| 1024 | CONFIG_NLS_UTF8=y | ||
| 1025 | |||
| 1026 | # | ||
| 1027 | # Distributed Lock Manager | ||
| 1028 | # | ||
| 1029 | # CONFIG_DLM is not set | ||
| 1030 | |||
| 1031 | # | ||
| 1032 | # Profiling support | ||
| 1033 | # | ||
| 1034 | # CONFIG_PROFILING is not set | ||
| 1035 | |||
| 1036 | # | ||
| 1037 | # Kernel hacking | ||
| 1038 | # | ||
| 1039 | # CONFIG_PRINTK_TIME is not set | ||
| 1040 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1041 | CONFIG_MAGIC_SYSRQ=y | ||
| 1042 | CONFIG_UNUSED_SYMBOLS=y | ||
| 1043 | CONFIG_DEBUG_FS=y | ||
| 1044 | # CONFIG_HEADERS_CHECK is not set | ||
| 1045 | CONFIG_DEBUG_KERNEL=y | ||
| 1046 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1047 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1048 | CONFIG_SCHED_DEBUG=y | ||
| 1049 | # CONFIG_SCHEDSTATS is not set | ||
| 1050 | # CONFIG_TIMER_STATS is not set | ||
| 1051 | # CONFIG_DEBUG_SLAB is not set | ||
| 1052 | CONFIG_DEBUG_PREEMPT=y | ||
| 1053 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1054 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1055 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1056 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1057 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1058 | # CONFIG_PROVE_LOCKING is not set | ||
| 1059 | # CONFIG_LOCK_STAT is not set | ||
| 1060 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1061 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1062 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1063 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1064 | # CONFIG_DEBUG_INFO is not set | ||
| 1065 | # CONFIG_DEBUG_VM is not set | ||
| 1066 | # CONFIG_DEBUG_LIST is not set | ||
| 1067 | CONFIG_FRAME_POINTER=y | ||
| 1068 | CONFIG_FORCED_INLINING=y | ||
| 1069 | # CONFIG_FAULT_INJECTION is not set | ||
| 1070 | # CONFIG_DEBUG_USER is not set | ||
| 1071 | # CONFIG_DEBUG_ERRORS is not set | ||
| 1072 | CONFIG_DEBUG_LL=y | ||
| 1073 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 1074 | |||
| 1075 | # | ||
| 1076 | # Security options | ||
| 1077 | # | ||
| 1078 | # CONFIG_KEYS is not set | ||
| 1079 | # CONFIG_SECURITY is not set | ||
| 1080 | # CONFIG_CRYPTO is not set | ||
| 1081 | |||
| 1082 | # | ||
| 1083 | # Library routines | ||
| 1084 | # | ||
| 1085 | CONFIG_BITREVERSE=y | ||
| 1086 | # CONFIG_CRC_CCITT is not set | ||
| 1087 | # CONFIG_CRC16 is not set | ||
| 1088 | # CONFIG_CRC_ITU_T is not set | ||
| 1089 | CONFIG_CRC32=y | ||
| 1090 | # CONFIG_CRC7 is not set | ||
| 1091 | # CONFIG_LIBCRC32C is not set | ||
| 1092 | CONFIG_AUDIT_GENERIC=y | ||
| 1093 | CONFIG_ZLIB_INFLATE=y | ||
| 1094 | CONFIG_ZLIB_DEFLATE=y | ||
| 1095 | CONFIG_PLIST=y | ||
| 1096 | CONFIG_HAS_IOMEM=y | ||
| 1097 | CONFIG_HAS_IOPORT=y | ||
| 1098 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig new file mode 100644 index 000000000000..576b8339f0d6 --- /dev/null +++ b/arch/arm/configs/tct_hammer_defconfig | |||
| @@ -0,0 +1,886 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.25-rc7-hammer | ||
| 4 | # Thu Mar 27 16:39:48 2008 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | # CONFIG_GENERIC_TIME is not set | ||
| 10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
| 11 | CONFIG_MMU=y | ||
| 12 | CONFIG_NO_IOPORT=y | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 18 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 20 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 22 | CONFIG_GENERIC_HWEIGHT=y | ||
| 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 24 | CONFIG_ARCH_SUPPORTS_AOUT=y | ||
| 25 | CONFIG_ZONE_DMA=y | ||
| 26 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 28 | |||
| 29 | # | ||
| 30 | # General setup | ||
| 31 | # | ||
| 32 | CONFIG_EXPERIMENTAL=y | ||
| 33 | CONFIG_BROKEN_ON_SMP=y | ||
| 34 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 35 | CONFIG_LOCALVERSION="" | ||
| 36 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 37 | # CONFIG_SWAP is not set | ||
| 38 | CONFIG_SYSVIPC=y | ||
| 39 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 40 | # CONFIG_POSIX_MQUEUE is not set | ||
| 41 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 42 | # CONFIG_TASKSTATS is not set | ||
| 43 | # CONFIG_AUDIT is not set | ||
| 44 | # CONFIG_IKCONFIG is not set | ||
| 45 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 46 | # CONFIG_CGROUPS is not set | ||
| 47 | CONFIG_GROUP_SCHED=y | ||
| 48 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 49 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 50 | CONFIG_USER_SCHED=y | ||
| 51 | # CONFIG_CGROUP_SCHED is not set | ||
| 52 | CONFIG_SYSFS_DEPRECATED=y | ||
| 53 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 54 | # CONFIG_RELAY is not set | ||
| 55 | # CONFIG_NAMESPACES is not set | ||
| 56 | CONFIG_BLK_DEV_INITRD=y | ||
| 57 | CONFIG_INITRAMFS_SOURCE="" | ||
| 58 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 59 | CONFIG_SYSCTL=y | ||
| 60 | CONFIG_EMBEDDED=y | ||
| 61 | CONFIG_UID16=y | ||
| 62 | CONFIG_SYSCTL_SYSCALL=y | ||
| 63 | # CONFIG_KALLSYMS is not set | ||
| 64 | CONFIG_HOTPLUG=y | ||
| 65 | CONFIG_PRINTK=y | ||
| 66 | # CONFIG_BUG is not set | ||
| 67 | # CONFIG_ELF_CORE is not set | ||
| 68 | CONFIG_COMPAT_BRK=y | ||
| 69 | CONFIG_BASE_FULL=y | ||
| 70 | CONFIG_FUTEX=y | ||
| 71 | CONFIG_ANON_INODES=y | ||
| 72 | CONFIG_EPOLL=y | ||
| 73 | CONFIG_SIGNALFD=y | ||
| 74 | CONFIG_TIMERFD=y | ||
| 75 | CONFIG_EVENTFD=y | ||
| 76 | # CONFIG_SHMEM is not set | ||
| 77 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 78 | # CONFIG_SLAB is not set | ||
| 79 | # CONFIG_SLUB is not set | ||
| 80 | CONFIG_SLOB=y | ||
| 81 | # CONFIG_PROFILING is not set | ||
| 82 | # CONFIG_MARKERS is not set | ||
| 83 | CONFIG_HAVE_OPROFILE=y | ||
| 84 | CONFIG_HAVE_KPROBES=y | ||
| 85 | CONFIG_HAVE_KRETPROBES=y | ||
| 86 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 87 | CONFIG_RT_MUTEXES=y | ||
| 88 | CONFIG_TINY_SHMEM=y | ||
| 89 | CONFIG_BASE_SMALL=0 | ||
| 90 | CONFIG_MODULES=y | ||
| 91 | CONFIG_MODULE_UNLOAD=y | ||
| 92 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 93 | # CONFIG_MODVERSIONS is not set | ||
| 94 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 95 | # CONFIG_KMOD is not set | ||
| 96 | CONFIG_BLOCK=y | ||
| 97 | # CONFIG_LBD is not set | ||
| 98 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 99 | # CONFIG_LSF is not set | ||
| 100 | # CONFIG_BLK_DEV_BSG is not set | ||
| 101 | |||
| 102 | # | ||
| 103 | # IO Schedulers | ||
| 104 | # | ||
| 105 | CONFIG_IOSCHED_NOOP=y | ||
| 106 | CONFIG_IOSCHED_AS=y | ||
| 107 | CONFIG_IOSCHED_DEADLINE=y | ||
| 108 | CONFIG_IOSCHED_CFQ=y | ||
| 109 | CONFIG_DEFAULT_AS=y | ||
| 110 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 111 | # CONFIG_DEFAULT_CFQ is not set | ||
| 112 | # CONFIG_DEFAULT_NOOP is not set | ||
| 113 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
| 114 | CONFIG_CLASSIC_RCU=y | ||
| 115 | |||
| 116 | # | ||
| 117 | # System Type | ||
| 118 | # | ||
| 119 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 120 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 121 | # CONFIG_ARCH_REALVIEW is not set | ||
| 122 | # CONFIG_ARCH_VERSATILE is not set | ||
| 123 | # CONFIG_ARCH_AT91 is not set | ||
| 124 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 125 | # CONFIG_ARCH_CLPS711X is not set | ||
| 126 | # CONFIG_ARCH_CO285 is not set | ||
| 127 | # CONFIG_ARCH_EBSA110 is not set | ||
| 128 | # CONFIG_ARCH_EP93XX is not set | ||
| 129 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 130 | # CONFIG_ARCH_NETX is not set | ||
| 131 | # CONFIG_ARCH_H720X is not set | ||
| 132 | # CONFIG_ARCH_IMX is not set | ||
| 133 | # CONFIG_ARCH_IOP13XX is not set | ||
| 134 | # CONFIG_ARCH_IOP32X is not set | ||
| 135 | # CONFIG_ARCH_IOP33X is not set | ||
| 136 | # CONFIG_ARCH_IXP23XX is not set | ||
| 137 | # CONFIG_ARCH_IXP2000 is not set | ||
| 138 | # CONFIG_ARCH_IXP4XX is not set | ||
| 139 | # CONFIG_ARCH_L7200 is not set | ||
| 140 | # CONFIG_ARCH_KS8695 is not set | ||
| 141 | # CONFIG_ARCH_NS9XXX is not set | ||
| 142 | # CONFIG_ARCH_MXC is not set | ||
| 143 | # CONFIG_ARCH_ORION is not set | ||
| 144 | # CONFIG_ARCH_PNX4008 is not set | ||
| 145 | # CONFIG_ARCH_PXA is not set | ||
| 146 | # CONFIG_ARCH_RPC is not set | ||
| 147 | # CONFIG_ARCH_SA1100 is not set | ||
| 148 | CONFIG_ARCH_S3C2410=y | ||
| 149 | # CONFIG_ARCH_SHARK is not set | ||
| 150 | # CONFIG_ARCH_LH7A40X is not set | ||
| 151 | # CONFIG_ARCH_DAVINCI is not set | ||
| 152 | # CONFIG_ARCH_OMAP is not set | ||
| 153 | # CONFIG_ARCH_MSM7X00A is not set | ||
| 154 | CONFIG_PLAT_S3C24XX=y | ||
| 155 | # CONFIG_S3C2410_DMA is not set | ||
| 156 | CONFIG_PLAT_S3C=y | ||
| 157 | CONFIG_CPU_LLSERIAL_S3C2410_ONLY=y | ||
| 158 | CONFIG_CPU_LLSERIAL_S3C2410=y | ||
| 159 | |||
| 160 | # | ||
| 161 | # Boot options | ||
| 162 | # | ||
| 163 | # CONFIG_S3C_BOOT_ERROR_RESET is not set | ||
| 164 | |||
| 165 | # | ||
| 166 | # Power management | ||
| 167 | # | ||
| 168 | CONFIG_S3C_LOWLEVEL_UART_PORT=0 | ||
| 169 | |||
| 170 | # | ||
| 171 | # S3C2400 Machines | ||
| 172 | # | ||
| 173 | CONFIG_CPU_S3C2410=y | ||
| 174 | CONFIG_S3C2410_GPIO=y | ||
| 175 | CONFIG_S3C2410_CLOCK=y | ||
| 176 | |||
| 177 | # | ||
| 178 | # S3C2410 Machines | ||
| 179 | # | ||
| 180 | # CONFIG_ARCH_SMDK2410 is not set | ||
| 181 | # CONFIG_ARCH_H1940 is not set | ||
| 182 | # CONFIG_MACH_N30 is not set | ||
| 183 | # CONFIG_ARCH_BAST is not set | ||
| 184 | # CONFIG_MACH_OTOM is not set | ||
| 185 | # CONFIG_MACH_AML_M5900 is not set | ||
| 186 | CONFIG_MACH_TCT_HAMMER=y | ||
| 187 | # CONFIG_MACH_VR1000 is not set | ||
| 188 | # CONFIG_MACH_QT2410 is not set | ||
| 189 | |||
| 190 | # | ||
| 191 | # S3C2412 Machines | ||
| 192 | # | ||
| 193 | # CONFIG_MACH_SMDK2413 is not set | ||
| 194 | # CONFIG_MACH_SMDK2412 is not set | ||
| 195 | # CONFIG_MACH_VSTMS is not set | ||
| 196 | |||
| 197 | # | ||
| 198 | # S3C2440 Machines | ||
| 199 | # | ||
| 200 | # CONFIG_MACH_ANUBIS is not set | ||
| 201 | # CONFIG_MACH_OSIRIS is not set | ||
| 202 | # CONFIG_MACH_RX3715 is not set | ||
| 203 | # CONFIG_ARCH_S3C2440 is not set | ||
| 204 | # CONFIG_MACH_NEXCODER_2440 is not set | ||
| 205 | |||
| 206 | # | ||
| 207 | # S3C2442 Machines | ||
| 208 | # | ||
| 209 | |||
| 210 | # | ||
| 211 | # S3C2443 Machines | ||
| 212 | # | ||
| 213 | # CONFIG_MACH_SMDK2443 is not set | ||
| 214 | |||
| 215 | # | ||
| 216 | # Processor Type | ||
| 217 | # | ||
| 218 | CONFIG_CPU_32=y | ||
| 219 | CONFIG_CPU_ARM920T=y | ||
| 220 | CONFIG_CPU_32v4T=y | ||
| 221 | CONFIG_CPU_ABRT_EV4T=y | ||
| 222 | CONFIG_CPU_CACHE_V4WT=y | ||
| 223 | CONFIG_CPU_CACHE_VIVT=y | ||
| 224 | CONFIG_CPU_COPY_V4WB=y | ||
| 225 | CONFIG_CPU_TLB_V4WBI=y | ||
| 226 | CONFIG_CPU_CP15=y | ||
| 227 | CONFIG_CPU_CP15_MMU=y | ||
| 228 | |||
| 229 | # | ||
| 230 | # Processor Features | ||
| 231 | # | ||
| 232 | CONFIG_ARM_THUMB=y | ||
| 233 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 234 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 235 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 236 | # CONFIG_OUTER_CACHE is not set | ||
| 237 | |||
| 238 | # | ||
| 239 | # Bus support | ||
| 240 | # | ||
| 241 | # CONFIG_PCI_SYSCALL is not set | ||
| 242 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 243 | # CONFIG_PCCARD is not set | ||
| 244 | |||
| 245 | # | ||
| 246 | # Kernel Features | ||
| 247 | # | ||
| 248 | # CONFIG_TICK_ONESHOT is not set | ||
| 249 | # CONFIG_PREEMPT is not set | ||
| 250 | # CONFIG_NO_IDLE_HZ is not set | ||
| 251 | CONFIG_HZ=200 | ||
| 252 | # CONFIG_AEABI is not set | ||
| 253 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | ||
| 254 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 255 | CONFIG_FLATMEM_MANUAL=y | ||
| 256 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 257 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 258 | CONFIG_FLATMEM=y | ||
| 259 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 260 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 261 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 262 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 263 | # CONFIG_RESOURCES_64BIT is not set | ||
| 264 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 265 | CONFIG_BOUNCE=y | ||
| 266 | CONFIG_VIRT_TO_BUS=y | ||
| 267 | CONFIG_ALIGNMENT_TRAP=y | ||
| 268 | |||
| 269 | # | ||
| 270 | # Boot options | ||
| 271 | # | ||
| 272 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 273 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 274 | CONFIG_CMDLINE="mem=64M root=/dev/ram0 init=/linuxrc rw" | ||
| 275 | # CONFIG_XIP_KERNEL is not set | ||
| 276 | # CONFIG_KEXEC is not set | ||
| 277 | |||
| 278 | # | ||
| 279 | # Floating point emulation | ||
| 280 | # | ||
| 281 | |||
| 282 | # | ||
| 283 | # At least one emulation must be selected | ||
| 284 | # | ||
| 285 | CONFIG_FPE_NWFPE=y | ||
| 286 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 287 | # CONFIG_FPE_FASTFPE is not set | ||
| 288 | |||
| 289 | # | ||
| 290 | # Userspace binary formats | ||
| 291 | # | ||
| 292 | CONFIG_BINFMT_ELF=y | ||
| 293 | # CONFIG_BINFMT_AOUT is not set | ||
| 294 | # CONFIG_BINFMT_MISC is not set | ||
| 295 | # CONFIG_ARTHUR is not set | ||
| 296 | |||
| 297 | # | ||
| 298 | # Power management options | ||
| 299 | # | ||
| 300 | # CONFIG_PM is not set | ||
| 301 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 302 | |||
| 303 | # | ||
| 304 | # Networking | ||
| 305 | # | ||
| 306 | CONFIG_NET=y | ||
| 307 | |||
| 308 | # | ||
| 309 | # Networking options | ||
| 310 | # | ||
| 311 | CONFIG_PACKET=y | ||
| 312 | # CONFIG_PACKET_MMAP is not set | ||
| 313 | CONFIG_UNIX=y | ||
| 314 | # CONFIG_NET_KEY is not set | ||
| 315 | # CONFIG_INET is not set | ||
| 316 | # CONFIG_NETWORK_SECMARK is not set | ||
| 317 | # CONFIG_NETFILTER is not set | ||
| 318 | # CONFIG_ATM is not set | ||
| 319 | # CONFIG_BRIDGE is not set | ||
| 320 | # CONFIG_VLAN_8021Q is not set | ||
| 321 | # CONFIG_DECNET is not set | ||
| 322 | # CONFIG_LLC2 is not set | ||
| 323 | # CONFIG_IPX is not set | ||
| 324 | # CONFIG_ATALK is not set | ||
| 325 | # CONFIG_X25 is not set | ||
| 326 | # CONFIG_LAPB is not set | ||
| 327 | # CONFIG_WAN_ROUTER is not set | ||
| 328 | # CONFIG_NET_SCHED is not set | ||
| 329 | |||
| 330 | # | ||
| 331 | # Network testing | ||
| 332 | # | ||
| 333 | # CONFIG_NET_PKTGEN is not set | ||
| 334 | # CONFIG_HAMRADIO is not set | ||
| 335 | # CONFIG_CAN is not set | ||
| 336 | # CONFIG_IRDA is not set | ||
| 337 | # CONFIG_BT is not set | ||
| 338 | |||
| 339 | # | ||
| 340 | # Wireless | ||
| 341 | # | ||
| 342 | # CONFIG_CFG80211 is not set | ||
| 343 | # CONFIG_WIRELESS_EXT is not set | ||
| 344 | # CONFIG_MAC80211 is not set | ||
| 345 | # CONFIG_IEEE80211 is not set | ||
| 346 | # CONFIG_RFKILL is not set | ||
| 347 | # CONFIG_NET_9P is not set | ||
| 348 | |||
| 349 | # | ||
| 350 | # Device Drivers | ||
| 351 | # | ||
| 352 | |||
| 353 | # | ||
| 354 | # Generic Driver Options | ||
| 355 | # | ||
| 356 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 357 | CONFIG_STANDALONE=y | ||
| 358 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | ||
| 359 | CONFIG_FW_LOADER=y | ||
| 360 | # CONFIG_DEBUG_DRIVER is not set | ||
| 361 | # CONFIG_DEBUG_DEVRES is not set | ||
| 362 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 363 | # CONFIG_CONNECTOR is not set | ||
| 364 | CONFIG_MTD=y | ||
| 365 | # CONFIG_MTD_DEBUG is not set | ||
| 366 | # CONFIG_MTD_CONCAT is not set | ||
| 367 | CONFIG_MTD_PARTITIONS=y | ||
| 368 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 369 | # CONFIG_MTD_CMDLINE_PARTS is not set | ||
| 370 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 371 | |||
| 372 | # | ||
| 373 | # User Modules And Translation Layers | ||
| 374 | # | ||
| 375 | CONFIG_MTD_CHAR=y | ||
| 376 | CONFIG_MTD_BLKDEVS=y | ||
| 377 | CONFIG_MTD_BLOCK=y | ||
| 378 | # CONFIG_FTL is not set | ||
| 379 | # CONFIG_NFTL is not set | ||
| 380 | # CONFIG_INFTL is not set | ||
| 381 | # CONFIG_RFD_FTL is not set | ||
| 382 | # CONFIG_SSFDC is not set | ||
| 383 | # CONFIG_MTD_OOPS is not set | ||
| 384 | |||
| 385 | # | ||
| 386 | # RAM/ROM/Flash chip drivers | ||
| 387 | # | ||
| 388 | CONFIG_MTD_CFI=y | ||
| 389 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 390 | CONFIG_MTD_GEN_PROBE=y | ||
| 391 | CONFIG_MTD_CFI_ADV_OPTIONS=y | ||
| 392 | CONFIG_MTD_CFI_NOSWAP=y | ||
| 393 | # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set | ||
| 394 | # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set | ||
| 395 | CONFIG_MTD_CFI_GEOMETRY=y | ||
| 396 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 397 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 398 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 399 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 400 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 401 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 402 | CONFIG_MTD_CFI_I1=y | ||
| 403 | CONFIG_MTD_CFI_I2=y | ||
| 404 | # CONFIG_MTD_CFI_I4 is not set | ||
| 405 | # CONFIG_MTD_CFI_I8 is not set | ||
| 406 | # CONFIG_MTD_OTP is not set | ||
| 407 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 408 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
| 409 | # CONFIG_MTD_CFI_STAA is not set | ||
| 410 | CONFIG_MTD_CFI_UTIL=y | ||
| 411 | # CONFIG_MTD_RAM is not set | ||
| 412 | # CONFIG_MTD_ROM is not set | ||
| 413 | # CONFIG_MTD_ABSENT is not set | ||
| 414 | |||
| 415 | # | ||
| 416 | # Mapping drivers for chip access | ||
| 417 | # | ||
| 418 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 419 | CONFIG_MTD_PHYSMAP=y | ||
| 420 | CONFIG_MTD_PHYSMAP_START=0x00000000 | ||
| 421 | CONFIG_MTD_PHYSMAP_LEN=0x0 | ||
| 422 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | ||
| 423 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 424 | # CONFIG_MTD_PLATRAM is not set | ||
| 425 | |||
| 426 | # | ||
| 427 | # Self-contained MTD device drivers | ||
| 428 | # | ||
| 429 | # CONFIG_MTD_SLRAM is not set | ||
| 430 | # CONFIG_MTD_PHRAM is not set | ||
| 431 | # CONFIG_MTD_MTDRAM is not set | ||
| 432 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 433 | |||
| 434 | # | ||
| 435 | # Disk-On-Chip Device Drivers | ||
| 436 | # | ||
| 437 | # CONFIG_MTD_DOC2000 is not set | ||
| 438 | # CONFIG_MTD_DOC2001 is not set | ||
| 439 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 440 | # CONFIG_MTD_NAND is not set | ||
| 441 | # CONFIG_MTD_ONENAND is not set | ||
| 442 | |||
| 443 | # | ||
| 444 | # UBI - Unsorted block images | ||
| 445 | # | ||
| 446 | # CONFIG_MTD_UBI is not set | ||
| 447 | # CONFIG_PARPORT is not set | ||
| 448 | CONFIG_BLK_DEV=y | ||
| 449 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 450 | # CONFIG_BLK_DEV_LOOP is not set | ||
| 451 | # CONFIG_BLK_DEV_NBD is not set | ||
| 452 | # CONFIG_BLK_DEV_UB is not set | ||
| 453 | CONFIG_BLK_DEV_RAM=y | ||
| 454 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 455 | CONFIG_BLK_DEV_RAM_SIZE=10240 | ||
| 456 | # CONFIG_BLK_DEV_XIP is not set | ||
| 457 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 458 | # CONFIG_ATA_OVER_ETH is not set | ||
| 459 | # CONFIG_MISC_DEVICES is not set | ||
| 460 | CONFIG_HAVE_IDE=y | ||
| 461 | # CONFIG_IDE is not set | ||
| 462 | |||
| 463 | # | ||
| 464 | # SCSI device support | ||
| 465 | # | ||
| 466 | # CONFIG_RAID_ATTRS is not set | ||
| 467 | # CONFIG_SCSI is not set | ||
| 468 | # CONFIG_SCSI_DMA is not set | ||
| 469 | # CONFIG_SCSI_NETLINK is not set | ||
| 470 | # CONFIG_ATA is not set | ||
| 471 | # CONFIG_MD is not set | ||
| 472 | # CONFIG_NETDEVICES is not set | ||
| 473 | # CONFIG_ISDN is not set | ||
| 474 | |||
| 475 | # | ||
| 476 | # Input device support | ||
| 477 | # | ||
| 478 | CONFIG_INPUT=y | ||
| 479 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 480 | # CONFIG_INPUT_POLLDEV is not set | ||
| 481 | |||
| 482 | # | ||
| 483 | # Userland interfaces | ||
| 484 | # | ||
| 485 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 486 | # CONFIG_INPUT_JOYDEV is not set | ||
| 487 | # CONFIG_INPUT_EVDEV is not set | ||
| 488 | # CONFIG_INPUT_EVBUG is not set | ||
| 489 | |||
| 490 | # | ||
| 491 | # Input Device Drivers | ||
| 492 | # | ||
| 493 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 494 | # CONFIG_INPUT_MOUSE is not set | ||
| 495 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 496 | # CONFIG_INPUT_TABLET is not set | ||
| 497 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 498 | # CONFIG_INPUT_MISC is not set | ||
| 499 | |||
| 500 | # | ||
| 501 | # Hardware I/O ports | ||
| 502 | # | ||
| 503 | # CONFIG_SERIO is not set | ||
| 504 | # CONFIG_GAMEPORT is not set | ||
| 505 | |||
| 506 | # | ||
| 507 | # Character devices | ||
| 508 | # | ||
| 509 | CONFIG_VT=y | ||
| 510 | # CONFIG_VT_CONSOLE is not set | ||
| 511 | CONFIG_HW_CONSOLE=y | ||
| 512 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 513 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 514 | |||
| 515 | # | ||
| 516 | # Serial drivers | ||
| 517 | # | ||
| 518 | # CONFIG_SERIAL_8250 is not set | ||
| 519 | |||
| 520 | # | ||
| 521 | # Non-8250 serial port support | ||
| 522 | # | ||
| 523 | CONFIG_SERIAL_S3C2410=y | ||
| 524 | CONFIG_SERIAL_S3C2410_CONSOLE=y | ||
| 525 | CONFIG_SERIAL_CORE=y | ||
| 526 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 527 | CONFIG_UNIX98_PTYS=y | ||
| 528 | CONFIG_LEGACY_PTYS=y | ||
| 529 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 530 | # CONFIG_IPMI_HANDLER is not set | ||
| 531 | # CONFIG_HW_RANDOM is not set | ||
| 532 | # CONFIG_NVRAM is not set | ||
| 533 | # CONFIG_R3964 is not set | ||
| 534 | # CONFIG_RAW_DRIVER is not set | ||
| 535 | # CONFIG_TCG_TPM is not set | ||
| 536 | # CONFIG_I2C is not set | ||
| 537 | |||
| 538 | # | ||
| 539 | # SPI support | ||
| 540 | # | ||
| 541 | # CONFIG_SPI is not set | ||
| 542 | # CONFIG_SPI_MASTER is not set | ||
| 543 | # CONFIG_W1 is not set | ||
| 544 | # CONFIG_POWER_SUPPLY is not set | ||
| 545 | # CONFIG_HWMON is not set | ||
| 546 | # CONFIG_WATCHDOG is not set | ||
| 547 | |||
| 548 | # | ||
| 549 | # Sonics Silicon Backplane | ||
| 550 | # | ||
| 551 | CONFIG_SSB_POSSIBLE=y | ||
| 552 | # CONFIG_SSB is not set | ||
| 553 | |||
| 554 | # | ||
| 555 | # Multifunction device drivers | ||
| 556 | # | ||
| 557 | # CONFIG_MFD_SM501 is not set | ||
| 558 | # CONFIG_MFD_ASIC3 is not set | ||
| 559 | |||
| 560 | # | ||
| 561 | # Multimedia devices | ||
| 562 | # | ||
| 563 | # CONFIG_VIDEO_DEV is not set | ||
| 564 | # CONFIG_DAB is not set | ||
| 565 | |||
| 566 | # | ||
| 567 | # Graphics support | ||
| 568 | # | ||
| 569 | # CONFIG_VGASTATE is not set | ||
| 570 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 571 | # CONFIG_FB is not set | ||
| 572 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 573 | |||
| 574 | # | ||
| 575 | # Display device support | ||
| 576 | # | ||
| 577 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 578 | |||
| 579 | # | ||
| 580 | # Console display driver support | ||
| 581 | # | ||
| 582 | # CONFIG_VGA_CONSOLE is not set | ||
| 583 | CONFIG_DUMMY_CONSOLE=y | ||
| 584 | |||
| 585 | # | ||
| 586 | # Sound | ||
| 587 | # | ||
| 588 | # CONFIG_SOUND is not set | ||
| 589 | # CONFIG_HID_SUPPORT is not set | ||
| 590 | CONFIG_USB_SUPPORT=y | ||
| 591 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 592 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 593 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 594 | CONFIG_USB=y | ||
| 595 | CONFIG_USB_DEBUG=y | ||
| 596 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 597 | |||
| 598 | # | ||
| 599 | # Miscellaneous USB options | ||
| 600 | # | ||
| 601 | # CONFIG_USB_DEVICEFS is not set | ||
| 602 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 603 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 604 | # CONFIG_USB_OTG is not set | ||
| 605 | |||
| 606 | # | ||
| 607 | # USB Host Controller Drivers | ||
| 608 | # | ||
| 609 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 610 | CONFIG_USB_OHCI_HCD=y | ||
| 611 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
| 612 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 613 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
| 614 | # CONFIG_USB_SL811_HCD is not set | ||
| 615 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 616 | |||
| 617 | # | ||
| 618 | # USB Device Class drivers | ||
| 619 | # | ||
| 620 | # CONFIG_USB_ACM is not set | ||
| 621 | # CONFIG_USB_PRINTER is not set | ||
| 622 | |||
| 623 | # | ||
| 624 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
| 625 | # | ||
| 626 | |||
| 627 | # | ||
| 628 | # may also be needed; see USB_STORAGE Help for more information | ||
| 629 | # | ||
| 630 | # CONFIG_USB_LIBUSUAL is not set | ||
| 631 | |||
| 632 | # | ||
| 633 | # USB Imaging devices | ||
| 634 | # | ||
| 635 | # CONFIG_USB_MDC800 is not set | ||
| 636 | CONFIG_USB_MON=y | ||
| 637 | |||
| 638 | # | ||
| 639 | # USB port drivers | ||
| 640 | # | ||
| 641 | # CONFIG_USB_SERIAL is not set | ||
| 642 | |||
| 643 | # | ||
| 644 | # USB Miscellaneous drivers | ||
| 645 | # | ||
| 646 | # CONFIG_USB_EMI62 is not set | ||
| 647 | # CONFIG_USB_EMI26 is not set | ||
| 648 | # CONFIG_USB_ADUTUX is not set | ||
| 649 | # CONFIG_USB_AUERSWALD is not set | ||
| 650 | # CONFIG_USB_RIO500 is not set | ||
| 651 | # CONFIG_USB_LEGOTOWER is not set | ||
| 652 | # CONFIG_USB_LCD is not set | ||
| 653 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 654 | # CONFIG_USB_LED is not set | ||
| 655 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 656 | # CONFIG_USB_CYTHERM is not set | ||
| 657 | # CONFIG_USB_PHIDGET is not set | ||
| 658 | # CONFIG_USB_IDMOUSE is not set | ||
| 659 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 660 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 661 | # CONFIG_USB_LD is not set | ||
| 662 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 663 | # CONFIG_USB_IOWARRIOR is not set | ||
| 664 | CONFIG_USB_GADGET=y | ||
| 665 | # CONFIG_USB_GADGET_DEBUG is not set | ||
| 666 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
| 667 | CONFIG_USB_GADGET_SELECTED=y | ||
| 668 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 669 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 670 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 671 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 672 | # CONFIG_USB_GADGET_PXA2XX is not set | ||
| 673 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 674 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 675 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 676 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 677 | CONFIG_USB_GADGET_S3C2410=y | ||
| 678 | CONFIG_USB_S3C2410=y | ||
| 679 | # CONFIG_USB_S3C2410_DEBUG is not set | ||
| 680 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 681 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 682 | # CONFIG_USB_GADGET_DUALSPEED is not set | ||
| 683 | # CONFIG_USB_ZERO is not set | ||
| 684 | CONFIG_USB_ETH=y | ||
| 685 | CONFIG_USB_ETH_RNDIS=y | ||
| 686 | # CONFIG_USB_GADGETFS is not set | ||
| 687 | # CONFIG_USB_FILE_STORAGE is not set | ||
| 688 | # CONFIG_USB_G_SERIAL is not set | ||
| 689 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 690 | # CONFIG_USB_G_PRINTER is not set | ||
| 691 | # CONFIG_MMC is not set | ||
| 692 | # CONFIG_NEW_LEDS is not set | ||
| 693 | CONFIG_RTC_LIB=y | ||
| 694 | # CONFIG_RTC_CLASS is not set | ||
| 695 | |||
| 696 | # | ||
| 697 | # File systems | ||
| 698 | # | ||
| 699 | CONFIG_EXT2_FS=y | ||
| 700 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 701 | # CONFIG_EXT2_FS_XIP is not set | ||
| 702 | # CONFIG_EXT3_FS is not set | ||
| 703 | # CONFIG_EXT4DEV_FS is not set | ||
| 704 | # CONFIG_REISERFS_FS is not set | ||
| 705 | # CONFIG_JFS_FS is not set | ||
| 706 | # CONFIG_FS_POSIX_ACL is not set | ||
| 707 | # CONFIG_XFS_FS is not set | ||
| 708 | # CONFIG_GFS2_FS is not set | ||
| 709 | # CONFIG_OCFS2_FS is not set | ||
| 710 | # CONFIG_DNOTIFY is not set | ||
| 711 | # CONFIG_INOTIFY is not set | ||
| 712 | # CONFIG_QUOTA is not set | ||
| 713 | # CONFIG_AUTOFS_FS is not set | ||
| 714 | # CONFIG_AUTOFS4_FS is not set | ||
| 715 | # CONFIG_FUSE_FS is not set | ||
| 716 | |||
| 717 | # | ||
| 718 | # CD-ROM/DVD Filesystems | ||
| 719 | # | ||
| 720 | # CONFIG_ISO9660_FS is not set | ||
| 721 | # CONFIG_UDF_FS is not set | ||
| 722 | |||
| 723 | # | ||
| 724 | # DOS/FAT/NT Filesystems | ||
| 725 | # | ||
| 726 | CONFIG_FAT_FS=y | ||
| 727 | CONFIG_MSDOS_FS=y | ||
| 728 | CONFIG_VFAT_FS=y | ||
| 729 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 730 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 731 | # CONFIG_NTFS_FS is not set | ||
| 732 | |||
| 733 | # | ||
| 734 | # Pseudo filesystems | ||
| 735 | # | ||
| 736 | CONFIG_PROC_FS=y | ||
| 737 | # CONFIG_PROC_SYSCTL is not set | ||
| 738 | CONFIG_SYSFS=y | ||
| 739 | # CONFIG_TMPFS is not set | ||
| 740 | # CONFIG_HUGETLB_PAGE is not set | ||
| 741 | # CONFIG_CONFIGFS_FS is not set | ||
| 742 | |||
| 743 | # | ||
| 744 | # Miscellaneous filesystems | ||
| 745 | # | ||
| 746 | # CONFIG_ADFS_FS is not set | ||
| 747 | # CONFIG_AFFS_FS is not set | ||
| 748 | # CONFIG_HFS_FS is not set | ||
| 749 | # CONFIG_HFSPLUS_FS is not set | ||
| 750 | # CONFIG_BEFS_FS is not set | ||
| 751 | # CONFIG_BFS_FS is not set | ||
| 752 | # CONFIG_EFS_FS is not set | ||
| 753 | CONFIG_JFFS2_FS=y | ||
| 754 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 755 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 756 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 757 | # CONFIG_JFFS2_SUMMARY is not set | ||
| 758 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 759 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | ||
| 760 | CONFIG_JFFS2_ZLIB=y | ||
| 761 | # CONFIG_JFFS2_LZO is not set | ||
| 762 | CONFIG_JFFS2_RTIME=y | ||
| 763 | # CONFIG_JFFS2_RUBIN is not set | ||
| 764 | # CONFIG_CRAMFS is not set | ||
| 765 | # CONFIG_VXFS_FS is not set | ||
| 766 | # CONFIG_MINIX_FS is not set | ||
| 767 | # CONFIG_HPFS_FS is not set | ||
| 768 | # CONFIG_QNX4FS_FS is not set | ||
| 769 | # CONFIG_ROMFS_FS is not set | ||
| 770 | # CONFIG_SYSV_FS is not set | ||
| 771 | # CONFIG_UFS_FS is not set | ||
| 772 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 773 | |||
| 774 | # | ||
| 775 | # Partition Types | ||
| 776 | # | ||
| 777 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 778 | CONFIG_MSDOS_PARTITION=y | ||
| 779 | CONFIG_NLS=y | ||
| 780 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 781 | CONFIG_NLS_CODEPAGE_437=y | ||
| 782 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 783 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 784 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 785 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 786 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 787 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 788 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 789 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 790 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 791 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 792 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 793 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 794 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 795 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 796 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 797 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 798 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 799 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 800 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 801 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 802 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 803 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 804 | # CONFIG_NLS_ASCII is not set | ||
| 805 | CONFIG_NLS_ISO8859_1=y | ||
| 806 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 807 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 808 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 809 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 810 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 811 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 812 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 813 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 814 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 815 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 816 | # CONFIG_NLS_KOI8_R is not set | ||
| 817 | # CONFIG_NLS_KOI8_U is not set | ||
| 818 | # CONFIG_NLS_UTF8 is not set | ||
| 819 | |||
| 820 | # | ||
| 821 | # Kernel hacking | ||
| 822 | # | ||
| 823 | # CONFIG_PRINTK_TIME is not set | ||
| 824 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 825 | # CONFIG_ENABLE_MUST_CHECK is not set | ||
| 826 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 827 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 828 | # CONFIG_DEBUG_FS is not set | ||
| 829 | # CONFIG_HEADERS_CHECK is not set | ||
| 830 | CONFIG_DEBUG_KERNEL=y | ||
| 831 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 832 | # CONFIG_DETECT_SOFTLOCKUP is not set | ||
| 833 | CONFIG_SCHED_DEBUG=y | ||
| 834 | # CONFIG_SCHEDSTATS is not set | ||
| 835 | # CONFIG_TIMER_STATS is not set | ||
| 836 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 837 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 838 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 839 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 840 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 841 | # CONFIG_PROVE_LOCKING is not set | ||
| 842 | # CONFIG_LOCK_STAT is not set | ||
| 843 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 844 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 845 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 846 | # CONFIG_DEBUG_INFO is not set | ||
| 847 | # CONFIG_DEBUG_VM is not set | ||
| 848 | # CONFIG_DEBUG_LIST is not set | ||
| 849 | # CONFIG_DEBUG_SG is not set | ||
| 850 | CONFIG_FRAME_POINTER=y | ||
| 851 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 852 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 853 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 854 | # CONFIG_FAULT_INJECTION is not set | ||
| 855 | # CONFIG_SAMPLES is not set | ||
| 856 | # CONFIG_DEBUG_USER is not set | ||
| 857 | CONFIG_DEBUG_ERRORS=y | ||
| 858 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 859 | CONFIG_DEBUG_LL=y | ||
| 860 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 861 | # CONFIG_DEBUG_S3C_PORT is not set | ||
| 862 | CONFIG_DEBUG_S3C_UART=0 | ||
| 863 | |||
| 864 | # | ||
| 865 | # Security options | ||
| 866 | # | ||
| 867 | # CONFIG_KEYS is not set | ||
| 868 | # CONFIG_SECURITY is not set | ||
| 869 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 870 | # CONFIG_CRYPTO is not set | ||
| 871 | |||
| 872 | # | ||
| 873 | # Library routines | ||
| 874 | # | ||
| 875 | CONFIG_BITREVERSE=y | ||
| 876 | CONFIG_CRC_CCITT=y | ||
| 877 | # CONFIG_CRC16 is not set | ||
| 878 | # CONFIG_CRC_ITU_T is not set | ||
| 879 | CONFIG_CRC32=y | ||
| 880 | # CONFIG_CRC7 is not set | ||
| 881 | # CONFIG_LIBCRC32C is not set | ||
| 882 | CONFIG_ZLIB_INFLATE=y | ||
| 883 | CONFIG_ZLIB_DEFLATE=y | ||
| 884 | CONFIG_PLIST=y | ||
| 885 | CONFIG_HAS_IOMEM=y | ||
| 886 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/yl9200_defconfig b/arch/arm/configs/yl9200_defconfig new file mode 100644 index 000000000000..26de37f74686 --- /dev/null +++ b/arch/arm/configs/yl9200_defconfig | |||
| @@ -0,0 +1,1216 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.24-rc6 | ||
| 4 | # Fri Jan 11 09:53:59 2008 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 18 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 20 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 22 | CONFIG_GENERIC_HWEIGHT=y | ||
| 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 24 | CONFIG_ZONE_DMA=y | ||
| 25 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 26 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 27 | |||
| 28 | # | ||
| 29 | # General setup | ||
| 30 | # | ||
| 31 | # CONFIG_EXPERIMENTAL is not set | ||
| 32 | CONFIG_BROKEN_ON_SMP=y | ||
| 33 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 34 | CONFIG_LOCALVERSION="" | ||
| 35 | CONFIG_LOCALVERSION_AUTO=y | ||
| 36 | # CONFIG_SWAP is not set | ||
| 37 | CONFIG_SYSVIPC=y | ||
| 38 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 39 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 40 | # CONFIG_TASKSTATS is not set | ||
| 41 | # CONFIG_AUDIT is not set | ||
| 42 | # CONFIG_IKCONFIG is not set | ||
| 43 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 44 | # CONFIG_CGROUPS is not set | ||
| 45 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 46 | CONFIG_FAIR_USER_SCHED=y | ||
| 47 | # CONFIG_FAIR_CGROUP_SCHED is not set | ||
| 48 | # CONFIG_SYSFS_DEPRECATED is not set | ||
| 49 | # CONFIG_RELAY is not set | ||
| 50 | CONFIG_BLK_DEV_INITRD=y | ||
| 51 | CONFIG_INITRAMFS_SOURCE="" | ||
| 52 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
| 53 | CONFIG_SYSCTL=y | ||
| 54 | # CONFIG_EMBEDDED is not set | ||
| 55 | CONFIG_UID16=y | ||
| 56 | CONFIG_SYSCTL_SYSCALL=y | ||
| 57 | CONFIG_KALLSYMS=y | ||
| 58 | # CONFIG_KALLSYMS_ALL is not set | ||
| 59 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 60 | CONFIG_HOTPLUG=y | ||
| 61 | CONFIG_PRINTK=y | ||
| 62 | CONFIG_BUG=y | ||
| 63 | CONFIG_ELF_CORE=y | ||
| 64 | CONFIG_BASE_FULL=y | ||
| 65 | CONFIG_FUTEX=y | ||
| 66 | CONFIG_ANON_INODES=y | ||
| 67 | CONFIG_EPOLL=y | ||
| 68 | CONFIG_SIGNALFD=y | ||
| 69 | CONFIG_EVENTFD=y | ||
| 70 | CONFIG_SHMEM=y | ||
| 71 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 72 | CONFIG_SLUB_DEBUG=y | ||
| 73 | # CONFIG_SLAB is not set | ||
| 74 | CONFIG_SLUB=y | ||
| 75 | # CONFIG_SLOB is not set | ||
| 76 | CONFIG_RT_MUTEXES=y | ||
| 77 | # CONFIG_TINY_SHMEM is not set | ||
| 78 | CONFIG_BASE_SMALL=0 | ||
| 79 | CONFIG_MODULES=y | ||
| 80 | CONFIG_MODULE_UNLOAD=y | ||
| 81 | # CONFIG_MODVERSIONS is not set | ||
| 82 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 83 | CONFIG_KMOD=y | ||
| 84 | CONFIG_BLOCK=y | ||
| 85 | # CONFIG_LBD is not set | ||
| 86 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 87 | # CONFIG_LSF is not set | ||
| 88 | |||
| 89 | # | ||
| 90 | # IO Schedulers | ||
| 91 | # | ||
| 92 | CONFIG_IOSCHED_NOOP=y | ||
| 93 | # CONFIG_IOSCHED_AS is not set | ||
| 94 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 95 | # CONFIG_IOSCHED_CFQ is not set | ||
| 96 | # CONFIG_DEFAULT_AS is not set | ||
| 97 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 98 | # CONFIG_DEFAULT_CFQ is not set | ||
| 99 | CONFIG_DEFAULT_NOOP=y | ||
| 100 | CONFIG_DEFAULT_IOSCHED="noop" | ||
| 101 | |||
| 102 | # | ||
| 103 | # System Type | ||
| 104 | # | ||
| 105 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 106 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 107 | # CONFIG_ARCH_REALVIEW is not set | ||
| 108 | # CONFIG_ARCH_VERSATILE is not set | ||
| 109 | CONFIG_ARCH_AT91=y | ||
| 110 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 111 | # CONFIG_ARCH_CLPS711X is not set | ||
| 112 | # CONFIG_ARCH_CO285 is not set | ||
| 113 | # CONFIG_ARCH_EBSA110 is not set | ||
| 114 | # CONFIG_ARCH_EP93XX is not set | ||
| 115 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 116 | # CONFIG_ARCH_NETX is not set | ||
| 117 | # CONFIG_ARCH_H720X is not set | ||
| 118 | # CONFIG_ARCH_IMX is not set | ||
| 119 | # CONFIG_ARCH_IOP13XX is not set | ||
| 120 | # CONFIG_ARCH_IOP32X is not set | ||
| 121 | # CONFIG_ARCH_IOP33X is not set | ||
| 122 | # CONFIG_ARCH_IXP23XX is not set | ||
| 123 | # CONFIG_ARCH_IXP2000 is not set | ||
| 124 | # CONFIG_ARCH_IXP4XX is not set | ||
| 125 | # CONFIG_ARCH_L7200 is not set | ||
| 126 | # CONFIG_ARCH_KS8695 is not set | ||
| 127 | # CONFIG_ARCH_NS9XXX is not set | ||
| 128 | # CONFIG_ARCH_MXC is not set | ||
| 129 | # CONFIG_ARCH_PNX4008 is not set | ||
| 130 | # CONFIG_ARCH_PXA is not set | ||
| 131 | # CONFIG_ARCH_RPC is not set | ||
| 132 | # CONFIG_ARCH_SA1100 is not set | ||
| 133 | # CONFIG_ARCH_S3C2410 is not set | ||
| 134 | # CONFIG_ARCH_SHARK is not set | ||
| 135 | # CONFIG_ARCH_LH7A40X is not set | ||
| 136 | # CONFIG_ARCH_DAVINCI is not set | ||
| 137 | # CONFIG_ARCH_OMAP is not set | ||
| 138 | |||
| 139 | # | ||
| 140 | # Boot options | ||
| 141 | # | ||
| 142 | |||
| 143 | # | ||
| 144 | # Power management | ||
| 145 | # | ||
| 146 | |||
| 147 | # | ||
| 148 | # Atmel AT91 System-on-Chip | ||
| 149 | # | ||
| 150 | CONFIG_ARCH_AT91RM9200=y | ||
| 151 | # CONFIG_ARCH_AT91SAM9260 is not set | ||
| 152 | # CONFIG_ARCH_AT91SAM9261 is not set | ||
| 153 | # CONFIG_ARCH_AT91SAM9263 is not set | ||
| 154 | # CONFIG_ARCH_AT91SAM9RL is not set | ||
| 155 | # CONFIG_ARCH_AT91X40 is not set | ||
| 156 | CONFIG_AT91_PMC_UNIT=y | ||
| 157 | |||
| 158 | # | ||
| 159 | # AT91RM9200 Board Type | ||
| 160 | # | ||
| 161 | # CONFIG_MACH_ONEARM is not set | ||
| 162 | CONFIG_ARCH_AT91RM9200DK=y | ||
| 163 | # CONFIG_MACH_AT91RM9200EK is not set | ||
| 164 | # CONFIG_MACH_CSB337 is not set | ||
| 165 | # CONFIG_MACH_CSB637 is not set | ||
| 166 | # CONFIG_MACH_CARMEVA is not set | ||
| 167 | # CONFIG_MACH_ATEB9200 is not set | ||
| 168 | # CONFIG_MACH_KB9200 is not set | ||
| 169 | # CONFIG_MACH_PICOTUX2XX is not set | ||
| 170 | # CONFIG_MACH_KAFA is not set | ||
| 171 | CONFIG_MACH_YL9200=y | ||
| 172 | |||
| 173 | # | ||
| 174 | # AT91 Board Options | ||
| 175 | # | ||
| 176 | # CONFIG_MTD_AT91_DATAFLASH_CARD is not set | ||
| 177 | |||
| 178 | # | ||
| 179 | # AT91 Feature Selections | ||
| 180 | # | ||
| 181 | # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set | ||
| 182 | |||
| 183 | # | ||
| 184 | # Processor Type | ||
| 185 | # | ||
| 186 | CONFIG_CPU_32=y | ||
| 187 | CONFIG_CPU_ARM920T=y | ||
| 188 | CONFIG_CPU_32v4T=y | ||
| 189 | CONFIG_CPU_ABRT_EV4T=y | ||
| 190 | CONFIG_CPU_CACHE_V4WT=y | ||
| 191 | CONFIG_CPU_CACHE_VIVT=y | ||
| 192 | CONFIG_CPU_COPY_V4WB=y | ||
| 193 | CONFIG_CPU_TLB_V4WBI=y | ||
| 194 | CONFIG_CPU_CP15=y | ||
| 195 | CONFIG_CPU_CP15_MMU=y | ||
| 196 | |||
| 197 | # | ||
| 198 | # Processor Features | ||
| 199 | # | ||
| 200 | # CONFIG_ARM_THUMB is not set | ||
| 201 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 202 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 203 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 204 | # CONFIG_OUTER_CACHE is not set | ||
| 205 | |||
| 206 | # | ||
| 207 | # Bus support | ||
| 208 | # | ||
| 209 | # CONFIG_PCI_SYSCALL is not set | ||
| 210 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 211 | # CONFIG_PCCARD is not set | ||
| 212 | |||
| 213 | # | ||
| 214 | # Kernel Features | ||
| 215 | # | ||
| 216 | # CONFIG_TICK_ONESHOT is not set | ||
| 217 | # CONFIG_NO_HZ is not set | ||
| 218 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 219 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 220 | CONFIG_HZ=100 | ||
| 221 | # CONFIG_AEABI is not set | ||
| 222 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | ||
| 223 | CONFIG_FLATMEM=y | ||
| 224 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 225 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 226 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 227 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 228 | # CONFIG_RESOURCES_64BIT is not set | ||
| 229 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 230 | CONFIG_BOUNCE=y | ||
| 231 | CONFIG_VIRT_TO_BUS=y | ||
| 232 | # CONFIG_LEDS is not set | ||
| 233 | CONFIG_ALIGNMENT_TRAP=y | ||
| 234 | |||
| 235 | # | ||
| 236 | # Boot options | ||
| 237 | # | ||
| 238 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 239 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 240 | CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw" | ||
| 241 | # CONFIG_XIP_KERNEL is not set | ||
| 242 | |||
| 243 | # | ||
| 244 | # Floating point emulation | ||
| 245 | # | ||
| 246 | |||
| 247 | # | ||
| 248 | # At least one emulation must be selected | ||
| 249 | # | ||
| 250 | CONFIG_FPE_NWFPE=y | ||
| 251 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 252 | |||
| 253 | # | ||
| 254 | # Userspace binary formats | ||
| 255 | # | ||
| 256 | CONFIG_BINFMT_ELF=y | ||
| 257 | # CONFIG_BINFMT_AOUT is not set | ||
| 258 | # CONFIG_BINFMT_MISC is not set | ||
| 259 | # CONFIG_ARTHUR is not set | ||
| 260 | |||
| 261 | # | ||
| 262 | # Power management options | ||
| 263 | # | ||
| 264 | # CONFIG_PM is not set | ||
| 265 | CONFIG_SUSPEND_UP_POSSIBLE=y | ||
| 266 | |||
| 267 | # | ||
| 268 | # Networking | ||
| 269 | # | ||
| 270 | CONFIG_NET=y | ||
| 271 | |||
| 272 | # | ||
| 273 | # Networking options | ||
| 274 | # | ||
| 275 | CONFIG_PACKET=y | ||
| 276 | # CONFIG_PACKET_MMAP is not set | ||
| 277 | CONFIG_UNIX=y | ||
| 278 | # CONFIG_NET_KEY is not set | ||
| 279 | CONFIG_INET=y | ||
| 280 | # CONFIG_IP_MULTICAST is not set | ||
| 281 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 282 | CONFIG_IP_FIB_HASH=y | ||
| 283 | CONFIG_IP_PNP=y | ||
| 284 | CONFIG_IP_PNP_DHCP=y | ||
| 285 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 286 | # CONFIG_IP_PNP_RARP is not set | ||
| 287 | # CONFIG_NET_IPIP is not set | ||
| 288 | # CONFIG_NET_IPGRE is not set | ||
| 289 | # CONFIG_SYN_COOKIES is not set | ||
| 290 | # CONFIG_INET_AH is not set | ||
| 291 | # CONFIG_INET_ESP is not set | ||
| 292 | # CONFIG_INET_IPCOMP is not set | ||
| 293 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 294 | # CONFIG_INET_TUNNEL is not set | ||
| 295 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 296 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 297 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 298 | # CONFIG_INET_LRO is not set | ||
| 299 | # CONFIG_INET_DIAG is not set | ||
| 300 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 301 | CONFIG_TCP_CONG_CUBIC=y | ||
| 302 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 303 | # CONFIG_IPV6 is not set | ||
| 304 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 305 | # CONFIG_INET6_TUNNEL is not set | ||
| 306 | # CONFIG_NETWORK_SECMARK is not set | ||
| 307 | # CONFIG_NETFILTER is not set | ||
| 308 | # CONFIG_BRIDGE is not set | ||
| 309 | # CONFIG_VLAN_8021Q is not set | ||
| 310 | # CONFIG_DECNET is not set | ||
| 311 | # CONFIG_LLC2 is not set | ||
| 312 | # CONFIG_IPX is not set | ||
| 313 | # CONFIG_ATALK is not set | ||
| 314 | # CONFIG_NET_SCHED is not set | ||
| 315 | |||
| 316 | # | ||
| 317 | # Network testing | ||
| 318 | # | ||
| 319 | # CONFIG_NET_PKTGEN is not set | ||
| 320 | # CONFIG_HAMRADIO is not set | ||
| 321 | # CONFIG_IRDA is not set | ||
| 322 | # CONFIG_BT is not set | ||
| 323 | |||
| 324 | # | ||
| 325 | # Wireless | ||
| 326 | # | ||
| 327 | # CONFIG_CFG80211 is not set | ||
| 328 | # CONFIG_WIRELESS_EXT is not set | ||
| 329 | # CONFIG_IEEE80211 is not set | ||
| 330 | # CONFIG_RFKILL is not set | ||
| 331 | |||
| 332 | # | ||
| 333 | # Device Drivers | ||
| 334 | # | ||
| 335 | |||
| 336 | # | ||
| 337 | # Generic Driver Options | ||
| 338 | # | ||
| 339 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 340 | CONFIG_STANDALONE=y | ||
| 341 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 342 | CONFIG_FW_LOADER=y | ||
| 343 | # CONFIG_DEBUG_DRIVER is not set | ||
| 344 | # CONFIG_DEBUG_DEVRES is not set | ||
| 345 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 346 | # CONFIG_CONNECTOR is not set | ||
| 347 | CONFIG_MTD=y | ||
| 348 | # CONFIG_MTD_DEBUG is not set | ||
| 349 | CONFIG_MTD_CONCAT=y | ||
| 350 | CONFIG_MTD_PARTITIONS=y | ||
| 351 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 352 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 353 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 354 | |||
| 355 | # | ||
| 356 | # User Modules And Translation Layers | ||
| 357 | # | ||
| 358 | CONFIG_MTD_CHAR=y | ||
| 359 | CONFIG_MTD_BLKDEVS=y | ||
| 360 | CONFIG_MTD_BLOCK=y | ||
| 361 | # CONFIG_FTL is not set | ||
| 362 | # CONFIG_NFTL is not set | ||
| 363 | # CONFIG_INFTL is not set | ||
| 364 | # CONFIG_RFD_FTL is not set | ||
| 365 | # CONFIG_SSFDC is not set | ||
| 366 | # CONFIG_MTD_OOPS is not set | ||
| 367 | |||
| 368 | # | ||
| 369 | # RAM/ROM/Flash chip drivers | ||
| 370 | # | ||
| 371 | CONFIG_MTD_CFI=y | ||
| 372 | CONFIG_MTD_JEDECPROBE=y | ||
| 373 | CONFIG_MTD_GEN_PROBE=y | ||
| 374 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 375 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 376 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 377 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 378 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 379 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 380 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 381 | CONFIG_MTD_CFI_I1=y | ||
| 382 | CONFIG_MTD_CFI_I2=y | ||
| 383 | # CONFIG_MTD_CFI_I4 is not set | ||
| 384 | # CONFIG_MTD_CFI_I8 is not set | ||
| 385 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 386 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
| 387 | # CONFIG_MTD_CFI_STAA is not set | ||
| 388 | CONFIG_MTD_CFI_UTIL=y | ||
| 389 | CONFIG_MTD_RAM=y | ||
| 390 | # CONFIG_MTD_ROM is not set | ||
| 391 | # CONFIG_MTD_ABSENT is not set | ||
| 392 | |||
| 393 | # | ||
| 394 | # Mapping drivers for chip access | ||
| 395 | # | ||
| 396 | CONFIG_MTD_COMPLEX_MAPPINGS=y | ||
| 397 | CONFIG_MTD_PHYSMAP=y | ||
| 398 | CONFIG_MTD_PHYSMAP_START=0x0000000 | ||
| 399 | CONFIG_MTD_PHYSMAP_LEN=0 | ||
| 400 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | ||
| 401 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 402 | # CONFIG_MTD_IMPA7 is not set | ||
| 403 | CONFIG_MTD_PLATRAM=y | ||
| 404 | |||
| 405 | # | ||
| 406 | # Self-contained MTD device drivers | ||
| 407 | # | ||
| 408 | # CONFIG_MTD_SLRAM is not set | ||
| 409 | # CONFIG_MTD_PHRAM is not set | ||
| 410 | # CONFIG_MTD_MTDRAM is not set | ||
| 411 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 412 | |||
| 413 | # | ||
| 414 | # Disk-On-Chip Device Drivers | ||
| 415 | # | ||
| 416 | # CONFIG_MTD_DOC2000 is not set | ||
| 417 | # CONFIG_MTD_DOC2001 is not set | ||
| 418 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 419 | CONFIG_MTD_NAND=y | ||
| 420 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
| 421 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 422 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 423 | CONFIG_MTD_NAND_IDS=y | ||
| 424 | CONFIG_MTD_NAND_AT91=y | ||
| 425 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 426 | CONFIG_MTD_NAND_PLATFORM=y | ||
| 427 | # CONFIG_MTD_ALAUDA is not set | ||
| 428 | # CONFIG_MTD_ONENAND is not set | ||
| 429 | |||
| 430 | # | ||
| 431 | # UBI - Unsorted block images | ||
| 432 | # | ||
| 433 | # CONFIG_MTD_UBI is not set | ||
| 434 | # CONFIG_PARPORT is not set | ||
| 435 | CONFIG_BLK_DEV=y | ||
| 436 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 437 | CONFIG_BLK_DEV_LOOP=y | ||
| 438 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 439 | # CONFIG_BLK_DEV_NBD is not set | ||
| 440 | # CONFIG_BLK_DEV_UB is not set | ||
| 441 | CONFIG_BLK_DEV_RAM=y | ||
| 442 | CONFIG_BLK_DEV_RAM_COUNT=3 | ||
| 443 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 444 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | ||
| 445 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 446 | # CONFIG_ATA_OVER_ETH is not set | ||
| 447 | # CONFIG_MISC_DEVICES is not set | ||
| 448 | |||
| 449 | # | ||
| 450 | # SCSI device support | ||
| 451 | # | ||
| 452 | # CONFIG_RAID_ATTRS is not set | ||
| 453 | CONFIG_SCSI=y | ||
| 454 | CONFIG_SCSI_DMA=y | ||
| 455 | # CONFIG_SCSI_NETLINK is not set | ||
| 456 | CONFIG_SCSI_PROC_FS=y | ||
| 457 | |||
| 458 | # | ||
| 459 | # SCSI support type (disk, tape, CD-ROM) | ||
| 460 | # | ||
| 461 | CONFIG_BLK_DEV_SD=y | ||
| 462 | # CONFIG_CHR_DEV_ST is not set | ||
| 463 | # CONFIG_CHR_DEV_OSST is not set | ||
| 464 | # CONFIG_BLK_DEV_SR is not set | ||
| 465 | # CONFIG_CHR_DEV_SG is not set | ||
| 466 | # CONFIG_CHR_DEV_SCH is not set | ||
| 467 | |||
| 468 | # | ||
| 469 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 470 | # | ||
| 471 | # CONFIG_SCSI_MULTI_LUN is not set | ||
| 472 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 473 | # CONFIG_SCSI_LOGGING is not set | ||
| 474 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 475 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 476 | |||
| 477 | # | ||
| 478 | # SCSI Transports | ||
| 479 | # | ||
| 480 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 481 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 482 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 483 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 484 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 485 | CONFIG_SCSI_LOWLEVEL=y | ||
| 486 | # CONFIG_ISCSI_TCP is not set | ||
| 487 | # CONFIG_SCSI_DEBUG is not set | ||
| 488 | CONFIG_ATA=y | ||
| 489 | # CONFIG_ATA_NONSTANDARD is not set | ||
| 490 | # CONFIG_MD is not set | ||
| 491 | CONFIG_NETDEVICES=y | ||
| 492 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 493 | # CONFIG_DUMMY is not set | ||
| 494 | # CONFIG_BONDING is not set | ||
| 495 | # CONFIG_EQUALIZER is not set | ||
| 496 | # CONFIG_TUN is not set | ||
| 497 | # CONFIG_VETH is not set | ||
| 498 | CONFIG_PHYLIB=y | ||
| 499 | |||
| 500 | # | ||
| 501 | # MII PHY device drivers | ||
| 502 | # | ||
| 503 | # CONFIG_MARVELL_PHY is not set | ||
| 504 | CONFIG_DAVICOM_PHY=y | ||
| 505 | # CONFIG_QSEMI_PHY is not set | ||
| 506 | # CONFIG_LXT_PHY is not set | ||
| 507 | # CONFIG_CICADA_PHY is not set | ||
| 508 | # CONFIG_VITESSE_PHY is not set | ||
| 509 | # CONFIG_SMSC_PHY is not set | ||
| 510 | # CONFIG_BROADCOM_PHY is not set | ||
| 511 | # CONFIG_ICPLUS_PHY is not set | ||
| 512 | # CONFIG_FIXED_PHY is not set | ||
| 513 | # CONFIG_MDIO_BITBANG is not set | ||
| 514 | CONFIG_NET_ETHERNET=y | ||
| 515 | CONFIG_MII=y | ||
| 516 | CONFIG_ARM_AT91_ETHER=y | ||
| 517 | # CONFIG_AX88796 is not set | ||
| 518 | # CONFIG_SMC91X is not set | ||
| 519 | # CONFIG_DM9000 is not set | ||
| 520 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 521 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 522 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 523 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 524 | # CONFIG_B44 is not set | ||
| 525 | # CONFIG_NETDEV_1000 is not set | ||
| 526 | # CONFIG_NETDEV_10000 is not set | ||
| 527 | |||
| 528 | # | ||
| 529 | # Wireless LAN | ||
| 530 | # | ||
| 531 | # CONFIG_WLAN_PRE80211 is not set | ||
| 532 | # CONFIG_WLAN_80211 is not set | ||
| 533 | |||
| 534 | # | ||
| 535 | # USB Network Adapters | ||
| 536 | # | ||
| 537 | # CONFIG_USB_KAWETH is not set | ||
| 538 | # CONFIG_USB_PEGASUS is not set | ||
| 539 | # CONFIG_USB_USBNET is not set | ||
| 540 | # CONFIG_WAN is not set | ||
| 541 | # CONFIG_PPP is not set | ||
| 542 | # CONFIG_SLIP is not set | ||
| 543 | # CONFIG_NETPOLL is not set | ||
| 544 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 545 | # CONFIG_ISDN is not set | ||
| 546 | |||
| 547 | # | ||
| 548 | # Input device support | ||
| 549 | # | ||
| 550 | CONFIG_INPUT=y | ||
| 551 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 552 | # CONFIG_INPUT_POLLDEV is not set | ||
| 553 | |||
| 554 | # | ||
| 555 | # Userland interfaces | ||
| 556 | # | ||
| 557 | CONFIG_INPUT_MOUSEDEV=y | ||
| 558 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 559 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=640 | ||
| 560 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 | ||
| 561 | # CONFIG_INPUT_JOYDEV is not set | ||
| 562 | CONFIG_INPUT_EVDEV=y | ||
| 563 | # CONFIG_INPUT_EVBUG is not set | ||
| 564 | |||
| 565 | # | ||
| 566 | # Input Device Drivers | ||
| 567 | # | ||
| 568 | CONFIG_INPUT_KEYBOARD=y | ||
| 569 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 570 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 571 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 572 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 573 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 574 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 575 | CONFIG_KEYBOARD_GPIO=y | ||
| 576 | CONFIG_INPUT_MOUSE=y | ||
| 577 | CONFIG_MOUSE_PS2=y | ||
| 578 | CONFIG_MOUSE_PS2_ALPS=y | ||
| 579 | CONFIG_MOUSE_PS2_LOGIPS2PP=y | ||
| 580 | CONFIG_MOUSE_PS2_SYNAPTICS=y | ||
| 581 | CONFIG_MOUSE_PS2_LIFEBOOK=y | ||
| 582 | CONFIG_MOUSE_PS2_TRACKPOINT=y | ||
| 583 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | ||
| 584 | # CONFIG_MOUSE_SERIAL is not set | ||
| 585 | # CONFIG_MOUSE_APPLETOUCH is not set | ||
| 586 | # CONFIG_MOUSE_VSXXXAA is not set | ||
| 587 | # CONFIG_MOUSE_GPIO is not set | ||
| 588 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 589 | # CONFIG_INPUT_TABLET is not set | ||
| 590 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 591 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 592 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 593 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
| 594 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
| 595 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
| 596 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
| 597 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
| 598 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
| 599 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
| 600 | # CONFIG_TOUCHSCREEN_UCB1400 is not set | ||
| 601 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
| 602 | # CONFIG_INPUT_MISC is not set | ||
| 603 | |||
| 604 | # | ||
| 605 | # Hardware I/O ports | ||
| 606 | # | ||
| 607 | CONFIG_SERIO=y | ||
| 608 | # CONFIG_SERIO_SERPORT is not set | ||
| 609 | CONFIG_SERIO_LIBPS2=y | ||
| 610 | # CONFIG_SERIO_RAW is not set | ||
| 611 | # CONFIG_GAMEPORT is not set | ||
| 612 | |||
| 613 | # | ||
| 614 | # Character devices | ||
| 615 | # | ||
| 616 | CONFIG_VT=y | ||
| 617 | CONFIG_VT_CONSOLE=y | ||
| 618 | CONFIG_HW_CONSOLE=y | ||
| 619 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 620 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 621 | |||
| 622 | # | ||
| 623 | # Serial drivers | ||
| 624 | # | ||
| 625 | # CONFIG_SERIAL_8250 is not set | ||
| 626 | |||
| 627 | # | ||
| 628 | # Non-8250 serial port support | ||
| 629 | # | ||
| 630 | CONFIG_SERIAL_ATMEL=y | ||
| 631 | CONFIG_SERIAL_ATMEL_CONSOLE=y | ||
| 632 | # CONFIG_SERIAL_ATMEL_TTYAT is not set | ||
| 633 | CONFIG_SERIAL_CORE=y | ||
| 634 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 635 | CONFIG_UNIX98_PTYS=y | ||
| 636 | CONFIG_LEGACY_PTYS=y | ||
| 637 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 638 | # CONFIG_IPMI_HANDLER is not set | ||
| 639 | # CONFIG_HW_RANDOM is not set | ||
| 640 | # CONFIG_NVRAM is not set | ||
| 641 | # CONFIG_R3964 is not set | ||
| 642 | # CONFIG_RAW_DRIVER is not set | ||
| 643 | CONFIG_I2C=y | ||
| 644 | CONFIG_I2C_BOARDINFO=y | ||
| 645 | # CONFIG_I2C_CHARDEV is not set | ||
| 646 | |||
| 647 | # | ||
| 648 | # I2C Algorithms | ||
| 649 | # | ||
| 650 | # CONFIG_I2C_ALGOBIT is not set | ||
| 651 | # CONFIG_I2C_ALGOPCF is not set | ||
| 652 | # CONFIG_I2C_ALGOPCA is not set | ||
| 653 | |||
| 654 | # | ||
| 655 | # I2C Hardware Bus support | ||
| 656 | # | ||
| 657 | # CONFIG_I2C_GPIO is not set | ||
| 658 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 659 | # CONFIG_I2C_SIMTEC is not set | ||
| 660 | # CONFIG_I2C_TINY_USB is not set | ||
| 661 | |||
| 662 | # | ||
| 663 | # Miscellaneous I2C Chip support | ||
| 664 | # | ||
| 665 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 666 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 667 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 668 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 669 | |||
| 670 | # | ||
| 671 | # SPI support | ||
| 672 | # | ||
| 673 | CONFIG_SPI=y | ||
| 674 | CONFIG_SPI_DEBUG=y | ||
| 675 | CONFIG_SPI_MASTER=y | ||
| 676 | |||
| 677 | # | ||
| 678 | # SPI Master Controller Drivers | ||
| 679 | # | ||
| 680 | CONFIG_SPI_ATMEL=y | ||
| 681 | |||
| 682 | # | ||
| 683 | # SPI Protocol Masters | ||
| 684 | # | ||
| 685 | # CONFIG_SPI_AT25 is not set | ||
| 686 | # CONFIG_SPI_TLE62X0 is not set | ||
| 687 | # CONFIG_W1 is not set | ||
| 688 | # CONFIG_POWER_SUPPLY is not set | ||
| 689 | CONFIG_HWMON=y | ||
| 690 | # CONFIG_HWMON_VID is not set | ||
| 691 | # CONFIG_SENSORS_ADM1021 is not set | ||
| 692 | # CONFIG_SENSORS_ADM1025 is not set | ||
| 693 | # CONFIG_SENSORS_DS1621 is not set | ||
| 694 | # CONFIG_SENSORS_GL518SM is not set | ||
| 695 | # CONFIG_SENSORS_GL520SM is not set | ||
| 696 | # CONFIG_SENSORS_IT87 is not set | ||
| 697 | # CONFIG_SENSORS_LM63 is not set | ||
| 698 | # CONFIG_SENSORS_LM75 is not set | ||
| 699 | # CONFIG_SENSORS_LM77 is not set | ||
| 700 | # CONFIG_SENSORS_LM78 is not set | ||
| 701 | # CONFIG_SENSORS_LM83 is not set | ||
| 702 | # CONFIG_SENSORS_LM87 is not set | ||
| 703 | # CONFIG_SENSORS_LM90 is not set | ||
| 704 | # CONFIG_SENSORS_LM92 is not set | ||
| 705 | # CONFIG_SENSORS_LM93 is not set | ||
| 706 | # CONFIG_SENSORS_MAX1619 is not set | ||
| 707 | # CONFIG_SENSORS_PC87360 is not set | ||
| 708 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
| 709 | # CONFIG_SENSORS_W83781D is not set | ||
| 710 | # CONFIG_SENSORS_W83627HF is not set | ||
| 711 | # CONFIG_SENSORS_W83627EHF is not set | ||
| 712 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
| 713 | # CONFIG_WATCHDOG is not set | ||
| 714 | |||
| 715 | # | ||
| 716 | # Sonics Silicon Backplane | ||
| 717 | # | ||
| 718 | CONFIG_SSB_POSSIBLE=y | ||
| 719 | # CONFIG_SSB is not set | ||
| 720 | |||
| 721 | # | ||
| 722 | # Multifunction device drivers | ||
| 723 | # | ||
| 724 | # CONFIG_MFD_SM501 is not set | ||
| 725 | |||
| 726 | # | ||
| 727 | # Multimedia devices | ||
| 728 | # | ||
| 729 | # CONFIG_VIDEO_DEV is not set | ||
| 730 | # CONFIG_DVB_CORE is not set | ||
| 731 | # CONFIG_DAB is not set | ||
| 732 | |||
| 733 | # | ||
| 734 | # Graphics support | ||
| 735 | # | ||
| 736 | # CONFIG_VGASTATE is not set | ||
| 737 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 738 | CONFIG_FB=y | ||
| 739 | # CONFIG_FIRMWARE_EDID is not set | ||
| 740 | # CONFIG_FB_DDC is not set | ||
| 741 | CONFIG_FB_CFB_FILLRECT=y | ||
| 742 | CONFIG_FB_CFB_COPYAREA=y | ||
| 743 | CONFIG_FB_CFB_IMAGEBLIT=y | ||
| 744 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 745 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 746 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 747 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 748 | # CONFIG_FB_SYS_FOPS is not set | ||
| 749 | CONFIG_FB_DEFERRED_IO=y | ||
| 750 | # CONFIG_FB_SVGALIB is not set | ||
| 751 | # CONFIG_FB_MACMODES is not set | ||
| 752 | # CONFIG_FB_BACKLIGHT is not set | ||
| 753 | # CONFIG_FB_MODE_HELPERS is not set | ||
| 754 | # CONFIG_FB_TILEBLITTING is not set | ||
| 755 | |||
| 756 | # | ||
| 757 | # Frame buffer hardware drivers | ||
| 758 | # | ||
| 759 | # CONFIG_FB_S1D13XXX is not set | ||
| 760 | CONFIG_FB_S1D135XX=y | ||
| 761 | # CONFIG_FB_VIRTUAL is not set | ||
| 762 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 763 | CONFIG_LCD_CLASS_DEVICE=y | ||
| 764 | # CONFIG_LCD_LTV350QV is not set | ||
| 765 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | ||
| 766 | # CONFIG_BACKLIGHT_CORGI is not set | ||
| 767 | |||
| 768 | # | ||
| 769 | # Display device support | ||
| 770 | # | ||
| 771 | CONFIG_DISPLAY_SUPPORT=y | ||
| 772 | |||
| 773 | # | ||
| 774 | # Display hardware drivers | ||
| 775 | # | ||
| 776 | |||
| 777 | # | ||
| 778 | # Console display driver support | ||
| 779 | # | ||
| 780 | # CONFIG_VGA_CONSOLE is not set | ||
| 781 | CONFIG_DUMMY_CONSOLE=y | ||
| 782 | # CONFIG_FRAMEBUFFER_CONSOLE is not set | ||
| 783 | CONFIG_LOGO=y | ||
| 784 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 785 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 786 | CONFIG_LOGO_LINUX_CLUT224=y | ||
| 787 | |||
| 788 | # | ||
| 789 | # Sound | ||
| 790 | # | ||
| 791 | # CONFIG_SOUND is not set | ||
| 792 | CONFIG_HID_SUPPORT=y | ||
| 793 | CONFIG_HID=y | ||
| 794 | CONFIG_HID_DEBUG=y | ||
| 795 | # CONFIG_HIDRAW is not set | ||
| 796 | |||
| 797 | # | ||
| 798 | # USB Input Devices | ||
| 799 | # | ||
| 800 | CONFIG_USB_HID=y | ||
| 801 | # CONFIG_USB_HIDINPUT_POWERBOOK is not set | ||
| 802 | # CONFIG_USB_HIDDEV is not set | ||
| 803 | CONFIG_USB_SUPPORT=y | ||
| 804 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 805 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 806 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 807 | CONFIG_USB=y | ||
| 808 | CONFIG_USB_DEBUG=y | ||
| 809 | |||
| 810 | # | ||
| 811 | # Miscellaneous USB options | ||
| 812 | # | ||
| 813 | CONFIG_USB_DEVICEFS=y | ||
| 814 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 815 | |||
| 816 | # | ||
| 817 | # USB Host Controller Drivers | ||
| 818 | # | ||
| 819 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 820 | CONFIG_USB_OHCI_HCD=y | ||
| 821 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
| 822 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 823 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
| 824 | # CONFIG_USB_SL811_HCD is not set | ||
| 825 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 826 | |||
| 827 | # | ||
| 828 | # USB Device Class drivers | ||
| 829 | # | ||
| 830 | # CONFIG_USB_ACM is not set | ||
| 831 | # CONFIG_USB_PRINTER is not set | ||
| 832 | |||
| 833 | # | ||
| 834 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
| 835 | # | ||
| 836 | |||
| 837 | # | ||
| 838 | # may also be needed; see USB_STORAGE Help for more information | ||
| 839 | # | ||
| 840 | CONFIG_USB_STORAGE=y | ||
| 841 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 842 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 843 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 844 | # CONFIG_USB_STORAGE_DPCM is not set | ||
| 845 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 846 | # CONFIG_USB_LIBUSUAL is not set | ||
| 847 | |||
| 848 | # | ||
| 849 | # USB Imaging devices | ||
| 850 | # | ||
| 851 | # CONFIG_USB_MICROTEK is not set | ||
| 852 | CONFIG_USB_MON=y | ||
| 853 | |||
| 854 | # | ||
| 855 | # USB port drivers | ||
| 856 | # | ||
| 857 | |||
| 858 | # | ||
| 859 | # USB Serial Converter support | ||
| 860 | # | ||
| 861 | # CONFIG_USB_SERIAL is not set | ||
| 862 | |||
| 863 | # | ||
| 864 | # USB Miscellaneous drivers | ||
| 865 | # | ||
| 866 | # CONFIG_USB_EMI62 is not set | ||
| 867 | # CONFIG_USB_EMI26 is not set | ||
| 868 | # CONFIG_USB_LCD is not set | ||
| 869 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 870 | # CONFIG_USB_LED is not set | ||
| 871 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 872 | # CONFIG_USB_CYTHERM is not set | ||
| 873 | # CONFIG_USB_PHIDGET is not set | ||
| 874 | # CONFIG_USB_IDMOUSE is not set | ||
| 875 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 876 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 877 | # CONFIG_USB_LD is not set | ||
| 878 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 879 | # CONFIG_USB_IOWARRIOR is not set | ||
| 880 | |||
| 881 | # | ||
| 882 | # USB DSL modem support | ||
| 883 | # | ||
| 884 | |||
| 885 | # | ||
| 886 | # USB Gadget Support | ||
| 887 | # | ||
| 888 | CONFIG_USB_GADGET=y | ||
| 889 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
| 890 | # CONFIG_USB_GADGET_DEBUG_FS is not set | ||
| 891 | CONFIG_USB_GADGET_SELECTED=y | ||
| 892 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 893 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 894 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 895 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 896 | # CONFIG_USB_GADGET_PXA2XX is not set | ||
| 897 | CONFIG_USB_GADGET_M66592=y | ||
| 898 | CONFIG_USB_M66592=y | ||
| 899 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 900 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 901 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 902 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 903 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 904 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 905 | CONFIG_USB_GADGET_DUALSPEED=y | ||
| 906 | # CONFIG_USB_ZERO is not set | ||
| 907 | # CONFIG_USB_ETH is not set | ||
| 908 | # CONFIG_USB_GADGETFS is not set | ||
| 909 | CONFIG_USB_FILE_STORAGE=y | ||
| 910 | # CONFIG_USB_FILE_STORAGE_TEST is not set | ||
| 911 | # CONFIG_USB_G_SERIAL is not set | ||
| 912 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 913 | CONFIG_MMC=y | ||
| 914 | CONFIG_MMC_DEBUG=y | ||
| 915 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 916 | |||
| 917 | # | ||
| 918 | # MMC/SD Card Drivers | ||
| 919 | # | ||
| 920 | CONFIG_MMC_BLOCK=y | ||
| 921 | # CONFIG_MMC_BLOCK_BOUNCE is not set | ||
| 922 | # CONFIG_SDIO_UART is not set | ||
| 923 | |||
| 924 | # | ||
| 925 | # MMC/SD Host Controller Drivers | ||
| 926 | # | ||
| 927 | CONFIG_MMC_AT91=y | ||
| 928 | CONFIG_NEW_LEDS=y | ||
| 929 | CONFIG_LEDS_CLASS=y | ||
| 930 | |||
| 931 | # | ||
| 932 | # LED drivers | ||
| 933 | # | ||
| 934 | CONFIG_LEDS_GPIO=y | ||
| 935 | |||
| 936 | # | ||
| 937 | # LED Triggers | ||
| 938 | # | ||
| 939 | CONFIG_LEDS_TRIGGERS=y | ||
| 940 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 941 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 942 | CONFIG_RTC_LIB=y | ||
| 943 | CONFIG_RTC_CLASS=y | ||
| 944 | CONFIG_RTC_HCTOSYS=y | ||
| 945 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 946 | # CONFIG_RTC_DEBUG is not set | ||
| 947 | |||
| 948 | # | ||
| 949 | # RTC interfaces | ||
| 950 | # | ||
| 951 | CONFIG_RTC_INTF_SYSFS=y | ||
| 952 | CONFIG_RTC_INTF_PROC=y | ||
| 953 | CONFIG_RTC_INTF_DEV=y | ||
| 954 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 955 | # CONFIG_RTC_DRV_TEST is not set | ||
| 956 | |||
| 957 | # | ||
| 958 | # I2C RTC drivers | ||
| 959 | # | ||
| 960 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 961 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 962 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 963 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 964 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 965 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 966 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 967 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 968 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 969 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 970 | |||
| 971 | # | ||
| 972 | # SPI RTC drivers | ||
| 973 | # | ||
| 974 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 975 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 976 | |||
| 977 | # | ||
| 978 | # Platform RTC drivers | ||
| 979 | # | ||
| 980 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 981 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 982 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 983 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 984 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 985 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 986 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 987 | |||
| 988 | # | ||
| 989 | # on-CPU RTC drivers | ||
| 990 | # | ||
| 991 | CONFIG_RTC_DRV_AT91RM9200=y | ||
| 992 | |||
| 993 | # | ||
| 994 | # File systems | ||
| 995 | # | ||
| 996 | CONFIG_EXT2_FS=y | ||
| 997 | CONFIG_EXT2_FS_XATTR=y | ||
| 998 | # CONFIG_EXT2_FS_POSIX_ACL is not set | ||
| 999 | # CONFIG_EXT2_FS_SECURITY is not set | ||
| 1000 | # CONFIG_EXT2_FS_XIP is not set | ||
| 1001 | CONFIG_EXT3_FS=y | ||
| 1002 | CONFIG_EXT3_FS_XATTR=y | ||
| 1003 | # CONFIG_EXT3_FS_POSIX_ACL is not set | ||
| 1004 | # CONFIG_EXT3_FS_SECURITY is not set | ||
| 1005 | CONFIG_JBD=y | ||
| 1006 | # CONFIG_JBD_DEBUG is not set | ||
| 1007 | CONFIG_FS_MBCACHE=y | ||
| 1008 | CONFIG_REISERFS_FS=y | ||
| 1009 | # CONFIG_REISERFS_CHECK is not set | ||
| 1010 | # CONFIG_REISERFS_PROC_INFO is not set | ||
| 1011 | # CONFIG_REISERFS_FS_XATTR is not set | ||
| 1012 | # CONFIG_JFS_FS is not set | ||
| 1013 | # CONFIG_FS_POSIX_ACL is not set | ||
| 1014 | # CONFIG_XFS_FS is not set | ||
| 1015 | # CONFIG_OCFS2_FS is not set | ||
| 1016 | # CONFIG_MINIX_FS is not set | ||
| 1017 | # CONFIG_ROMFS_FS is not set | ||
| 1018 | CONFIG_INOTIFY=y | ||
| 1019 | CONFIG_INOTIFY_USER=y | ||
| 1020 | # CONFIG_QUOTA is not set | ||
| 1021 | CONFIG_DNOTIFY=y | ||
| 1022 | # CONFIG_AUTOFS_FS is not set | ||
| 1023 | # CONFIG_AUTOFS4_FS is not set | ||
| 1024 | # CONFIG_FUSE_FS is not set | ||
| 1025 | |||
| 1026 | # | ||
| 1027 | # CD-ROM/DVD Filesystems | ||
| 1028 | # | ||
| 1029 | CONFIG_ISO9660_FS=y | ||
| 1030 | CONFIG_JOLIET=y | ||
| 1031 | CONFIG_ZISOFS=y | ||
| 1032 | CONFIG_UDF_FS=y | ||
| 1033 | CONFIG_UDF_NLS=y | ||
| 1034 | |||
| 1035 | # | ||
| 1036 | # DOS/FAT/NT Filesystems | ||
| 1037 | # | ||
| 1038 | CONFIG_FAT_FS=y | ||
| 1039 | CONFIG_MSDOS_FS=y | ||
| 1040 | CONFIG_VFAT_FS=y | ||
| 1041 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1042 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1043 | # CONFIG_NTFS_FS is not set | ||
| 1044 | |||
| 1045 | # | ||
| 1046 | # Pseudo filesystems | ||
| 1047 | # | ||
| 1048 | CONFIG_PROC_FS=y | ||
| 1049 | CONFIG_PROC_SYSCTL=y | ||
| 1050 | CONFIG_SYSFS=y | ||
| 1051 | CONFIG_TMPFS=y | ||
| 1052 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1053 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1054 | |||
| 1055 | # | ||
| 1056 | # Miscellaneous filesystems | ||
| 1057 | # | ||
| 1058 | # CONFIG_HFSPLUS_FS is not set | ||
| 1059 | CONFIG_JFFS2_FS=y | ||
| 1060 | CONFIG_JFFS2_FS_DEBUG=1 | ||
| 1061 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 1062 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1063 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 1064 | CONFIG_JFFS2_ZLIB=y | ||
| 1065 | # CONFIG_JFFS2_LZO is not set | ||
| 1066 | CONFIG_JFFS2_RTIME=y | ||
| 1067 | CONFIG_JFFS2_RUBIN=y | ||
| 1068 | # CONFIG_JFFS2_CMODE_NONE is not set | ||
| 1069 | CONFIG_JFFS2_CMODE_PRIORITY=y | ||
| 1070 | # CONFIG_JFFS2_CMODE_SIZE is not set | ||
| 1071 | # CONFIG_JFFS2_CMODE_FAVOURLZO is not set | ||
| 1072 | CONFIG_CRAMFS=y | ||
| 1073 | # CONFIG_VXFS_FS is not set | ||
| 1074 | # CONFIG_HPFS_FS is not set | ||
| 1075 | # CONFIG_QNX4FS_FS is not set | ||
| 1076 | # CONFIG_SYSV_FS is not set | ||
| 1077 | # CONFIG_UFS_FS is not set | ||
| 1078 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1079 | # CONFIG_NFS_FS is not set | ||
| 1080 | # CONFIG_NFSD is not set | ||
| 1081 | # CONFIG_SMB_FS is not set | ||
| 1082 | # CONFIG_CIFS is not set | ||
| 1083 | # CONFIG_NCP_FS is not set | ||
| 1084 | # CONFIG_CODA_FS is not set | ||
| 1085 | |||
| 1086 | # | ||
| 1087 | # Partition Types | ||
| 1088 | # | ||
| 1089 | CONFIG_PARTITION_ADVANCED=y | ||
| 1090 | # CONFIG_ACORN_PARTITION is not set | ||
| 1091 | # CONFIG_OSF_PARTITION is not set | ||
| 1092 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1093 | # CONFIG_ATARI_PARTITION is not set | ||
| 1094 | CONFIG_MAC_PARTITION=y | ||
| 1095 | CONFIG_MSDOS_PARTITION=y | ||
| 1096 | # CONFIG_BSD_DISKLABEL is not set | ||
| 1097 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 1098 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 1099 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 1100 | # CONFIG_LDM_PARTITION is not set | ||
| 1101 | # CONFIG_SGI_PARTITION is not set | ||
| 1102 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1103 | # CONFIG_SUN_PARTITION is not set | ||
| 1104 | # CONFIG_KARMA_PARTITION is not set | ||
| 1105 | # CONFIG_EFI_PARTITION is not set | ||
| 1106 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1107 | CONFIG_NLS=y | ||
| 1108 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1109 | CONFIG_NLS_CODEPAGE_437=y | ||
| 1110 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1111 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1112 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1113 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1114 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1115 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1116 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1117 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1118 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1119 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1120 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1121 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1122 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1123 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1124 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1125 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1126 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1127 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1128 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1129 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1130 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1131 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1132 | # CONFIG_NLS_ASCII is not set | ||
| 1133 | CONFIG_NLS_ISO8859_1=y | ||
| 1134 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1135 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1136 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1137 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1138 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1139 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1140 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1141 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1142 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1143 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1144 | # CONFIG_NLS_KOI8_R is not set | ||
| 1145 | # CONFIG_NLS_KOI8_U is not set | ||
| 1146 | # CONFIG_NLS_UTF8 is not set | ||
| 1147 | CONFIG_INSTRUMENTATION=y | ||
| 1148 | # CONFIG_PROFILING is not set | ||
| 1149 | # CONFIG_MARKERS is not set | ||
| 1150 | |||
| 1151 | # | ||
| 1152 | # Kernel hacking | ||
| 1153 | # | ||
| 1154 | # CONFIG_PRINTK_TIME is not set | ||
| 1155 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1156 | # CONFIG_ENABLE_MUST_CHECK is not set | ||
| 1157 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1158 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1159 | CONFIG_DEBUG_FS=y | ||
| 1160 | # CONFIG_HEADERS_CHECK is not set | ||
| 1161 | CONFIG_DEBUG_KERNEL=y | ||
| 1162 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1163 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1164 | CONFIG_SCHED_DEBUG=y | ||
| 1165 | # CONFIG_SCHEDSTATS is not set | ||
| 1166 | # CONFIG_TIMER_STATS is not set | ||
| 1167 | CONFIG_SLUB_DEBUG_ON=y | ||
| 1168 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1169 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1170 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1171 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1172 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1173 | # CONFIG_PROVE_LOCKING is not set | ||
| 1174 | # CONFIG_LOCK_STAT is not set | ||
| 1175 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1176 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1177 | CONFIG_DEBUG_KOBJECT=y | ||
| 1178 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1179 | CONFIG_DEBUG_INFO=y | ||
| 1180 | # CONFIG_DEBUG_VM is not set | ||
| 1181 | CONFIG_DEBUG_LIST=y | ||
| 1182 | # CONFIG_DEBUG_SG is not set | ||
| 1183 | CONFIG_FRAME_POINTER=y | ||
| 1184 | CONFIG_FORCED_INLINING=y | ||
| 1185 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1186 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1187 | # CONFIG_FAULT_INJECTION is not set | ||
| 1188 | # CONFIG_SAMPLES is not set | ||
| 1189 | CONFIG_DEBUG_USER=y | ||
| 1190 | CONFIG_DEBUG_ERRORS=y | ||
| 1191 | CONFIG_DEBUG_LL=y | ||
| 1192 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 1193 | |||
| 1194 | # | ||
| 1195 | # Security options | ||
| 1196 | # | ||
| 1197 | # CONFIG_KEYS is not set | ||
| 1198 | # CONFIG_SECURITY is not set | ||
| 1199 | # CONFIG_CRYPTO is not set | ||
| 1200 | |||
| 1201 | # | ||
| 1202 | # Library routines | ||
| 1203 | # | ||
| 1204 | CONFIG_BITREVERSE=y | ||
| 1205 | # CONFIG_CRC_CCITT is not set | ||
| 1206 | # CONFIG_CRC16 is not set | ||
| 1207 | # CONFIG_CRC_ITU_T is not set | ||
| 1208 | CONFIG_CRC32=y | ||
| 1209 | # CONFIG_CRC7 is not set | ||
| 1210 | # CONFIG_LIBCRC32C is not set | ||
| 1211 | CONFIG_ZLIB_INFLATE=y | ||
| 1212 | CONFIG_ZLIB_DEFLATE=y | ||
| 1213 | CONFIG_PLIST=y | ||
| 1214 | CONFIG_HAS_IOMEM=y | ||
| 1215 | CONFIG_HAS_IOPORT=y | ||
| 1216 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 00d44c6fbfe9..ad455ff5aebe 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile | |||
| @@ -7,7 +7,7 @@ AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET) | |||
| 7 | # Object file lists. | 7 | # Object file lists. |
| 8 | 8 | ||
| 9 | obj-y := compat.o entry-armv.o entry-common.o irq.o \ | 9 | obj-y := compat.o entry-armv.o entry-common.o irq.o \ |
| 10 | process.o ptrace.o semaphore.o setup.o signal.o \ | 10 | process.o ptrace.o setup.o signal.o \ |
| 11 | sys_arm.o stacktrace.o time.o traps.o | 11 | sys_arm.o stacktrace.o time.o traps.o |
| 12 | 12 | ||
| 13 | obj-$(CONFIG_ISA_DMA_API) += dma.o | 13 | obj-$(CONFIG_ISA_DMA_API) += dma.o |
| @@ -22,6 +22,7 @@ obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o | |||
| 22 | obj-$(CONFIG_KPROBES) += kprobes.o kprobes-decode.o | 22 | obj-$(CONFIG_KPROBES) += kprobes.o kprobes-decode.o |
| 23 | obj-$(CONFIG_ATAGS_PROC) += atags.o | 23 | obj-$(CONFIG_ATAGS_PROC) += atags.o |
| 24 | obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o | 24 | obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o |
| 25 | obj-$(CONFIG_ARM_THUMBEE) += thumbee.o | ||
| 25 | 26 | ||
| 26 | obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o | 27 | obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o |
| 27 | AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 | 28 | AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 |
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index 3278e713c32a..0a0d2479274b 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c | |||
| @@ -58,6 +58,9 @@ int main(void) | |||
| 58 | DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value)); | 58 | DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value)); |
| 59 | DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate)); | 59 | DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate)); |
| 60 | DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate)); | 60 | DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate)); |
| 61 | #ifdef CONFIG_ARM_THUMBEE | ||
| 62 | DEFINE(TI_THUMBEE_STATE, offsetof(struct thread_info, thumbee_state)); | ||
| 63 | #endif | ||
| 61 | #ifdef CONFIG_IWMMXT | 64 | #ifdef CONFIG_IWMMXT |
| 62 | DEFINE(TI_IWMMXT_STATE, offsetof(struct thread_info, fpstate.iwmmxt)); | 65 | DEFINE(TI_IWMMXT_STATE, offsetof(struct thread_info, fpstate.iwmmxt)); |
| 63 | #endif | 66 | #endif |
| @@ -108,5 +111,12 @@ int main(void) | |||
| 108 | DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush)); | 111 | DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush)); |
| 109 | DEFINE(PROCINFO_MM_MMUFLAGS, offsetof(struct proc_info_list, __cpu_mm_mmu_flags)); | 112 | DEFINE(PROCINFO_MM_MMUFLAGS, offsetof(struct proc_info_list, __cpu_mm_mmu_flags)); |
| 110 | DEFINE(PROCINFO_IO_MMUFLAGS, offsetof(struct proc_info_list, __cpu_io_mmu_flags)); | 113 | DEFINE(PROCINFO_IO_MMUFLAGS, offsetof(struct proc_info_list, __cpu_io_mmu_flags)); |
| 114 | BLANK(); | ||
| 115 | #ifdef MULTI_DABORT | ||
| 116 | DEFINE(PROCESSOR_DABT_FUNC, offsetof(struct processor, _data_abort)); | ||
| 117 | #endif | ||
| 118 | #ifdef MULTI_PABORT | ||
| 119 | DEFINE(PROCESSOR_PABT_FUNC, offsetof(struct processor, _prefetch_abort)); | ||
| 120 | #endif | ||
| 111 | return 0; | 121 | return 0; |
| 112 | } | 122 | } |
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index 283e14fff993..30a67a5a40a8 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S | |||
| @@ -336,7 +336,7 @@ | |||
| 336 | CALL(sys_mknodat) | 336 | CALL(sys_mknodat) |
| 337 | /* 325 */ CALL(sys_fchownat) | 337 | /* 325 */ CALL(sys_fchownat) |
| 338 | CALL(sys_futimesat) | 338 | CALL(sys_futimesat) |
| 339 | CALL(sys_fstatat64) | 339 | CALL(ABI(sys_fstatat64, sys_oabi_fstatat64)) |
| 340 | CALL(sys_unlinkat) | 340 | CALL(sys_unlinkat) |
| 341 | CALL(sys_renameat) | 341 | CALL(sys_renameat) |
| 342 | /* 330 */ CALL(sys_linkat) | 342 | /* 330 */ CALL(sys_linkat) |
| @@ -359,9 +359,11 @@ | |||
| 359 | CALL(sys_kexec_load) | 359 | CALL(sys_kexec_load) |
| 360 | CALL(sys_utimensat) | 360 | CALL(sys_utimensat) |
| 361 | CALL(sys_signalfd) | 361 | CALL(sys_signalfd) |
| 362 | /* 350 */ CALL(sys_ni_syscall) | 362 | /* 350 */ CALL(sys_timerfd_create) |
| 363 | CALL(sys_eventfd) | 363 | CALL(sys_eventfd) |
| 364 | CALL(sys_fallocate) | 364 | CALL(sys_fallocate) |
| 365 | CALL(sys_timerfd_settime) | ||
| 366 | CALL(sys_timerfd_gettime) | ||
| 365 | #ifndef syscalls_counted | 367 | #ifndef syscalls_counted |
| 366 | .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls | 368 | .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls |
| 367 | #define syscalls_counted | 369 | #define syscalls_counted |
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index a46d5b456765..7dca225752c1 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S | |||
| @@ -166,12 +166,12 @@ __dabt_svc: | |||
| 166 | @ The abort handler must return the aborted address in r0, and | 166 | @ The abort handler must return the aborted address in r0, and |
| 167 | @ the fault status register in r1. r9 must be preserved. | 167 | @ the fault status register in r1. r9 must be preserved. |
| 168 | @ | 168 | @ |
| 169 | #ifdef MULTI_ABORT | 169 | #ifdef MULTI_DABORT |
| 170 | ldr r4, .LCprocfns | 170 | ldr r4, .LCprocfns |
| 171 | mov lr, pc | 171 | mov lr, pc |
| 172 | ldr pc, [r4] | 172 | ldr pc, [r4, #PROCESSOR_DABT_FUNC] |
| 173 | #else | 173 | #else |
| 174 | bl CPU_ABORT_HANDLER | 174 | bl CPU_DABORT_HANDLER |
| 175 | #endif | 175 | #endif |
| 176 | 176 | ||
| 177 | @ | 177 | @ |
| @@ -209,14 +209,12 @@ __irq_svc: | |||
| 209 | 209 | ||
| 210 | irq_handler | 210 | irq_handler |
| 211 | #ifdef CONFIG_PREEMPT | 211 | #ifdef CONFIG_PREEMPT |
| 212 | str r8, [tsk, #TI_PREEMPT] @ restore preempt count | ||
| 212 | ldr r0, [tsk, #TI_FLAGS] @ get flags | 213 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
| 214 | teq r8, #0 @ if preempt count != 0 | ||
| 215 | movne r0, #0 @ force flags to 0 | ||
| 213 | tst r0, #_TIF_NEED_RESCHED | 216 | tst r0, #_TIF_NEED_RESCHED |
| 214 | blne svc_preempt | 217 | blne svc_preempt |
| 215 | preempt_return: | ||
| 216 | ldr r0, [tsk, #TI_PREEMPT] @ read preempt value | ||
| 217 | str r8, [tsk, #TI_PREEMPT] @ restore preempt count | ||
| 218 | teq r0, r7 | ||
| 219 | strne r0, [r0, -r0] @ bug() | ||
| 220 | #endif | 218 | #endif |
| 221 | ldr r0, [sp, #S_PSR] @ irqs are already disabled | 219 | ldr r0, [sp, #S_PSR] @ irqs are already disabled |
| 222 | msr spsr_cxsf, r0 | 220 | msr spsr_cxsf, r0 |
| @@ -230,19 +228,11 @@ preempt_return: | |||
| 230 | 228 | ||
| 231 | #ifdef CONFIG_PREEMPT | 229 | #ifdef CONFIG_PREEMPT |
| 232 | svc_preempt: | 230 | svc_preempt: |
| 233 | teq r8, #0 @ was preempt count = 0 | 231 | mov r8, lr |
| 234 | ldreq r6, .LCirq_stat | ||
| 235 | movne pc, lr @ no | ||
| 236 | ldr r0, [r6, #4] @ local_irq_count | ||
| 237 | ldr r1, [r6, #8] @ local_bh_count | ||
| 238 | adds r0, r0, r1 | ||
| 239 | movne pc, lr | ||
| 240 | mov r7, #0 @ preempt_schedule_irq | ||
| 241 | str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0 | ||
| 242 | 1: bl preempt_schedule_irq @ irq en/disable is done inside | 232 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
| 243 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS | 233 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
| 244 | tst r0, #_TIF_NEED_RESCHED | 234 | tst r0, #_TIF_NEED_RESCHED |
| 245 | beq preempt_return @ go again | 235 | moveq pc, r8 @ go again |
| 246 | b 1b | 236 | b 1b |
| 247 | #endif | 237 | #endif |
| 248 | 238 | ||
| @@ -293,7 +283,6 @@ __pabt_svc: | |||
| 293 | mrs r9, cpsr | 283 | mrs r9, cpsr |
| 294 | tst r3, #PSR_I_BIT | 284 | tst r3, #PSR_I_BIT |
| 295 | biceq r9, r9, #PSR_I_BIT | 285 | biceq r9, r9, #PSR_I_BIT |
| 296 | msr cpsr_c, r9 | ||
| 297 | 286 | ||
| 298 | @ | 287 | @ |
| 299 | @ set args, then call main handler | 288 | @ set args, then call main handler |
| @@ -301,7 +290,15 @@ __pabt_svc: | |||
| 301 | @ r0 - address of faulting instruction | 290 | @ r0 - address of faulting instruction |
| 302 | @ r1 - pointer to registers on stack | 291 | @ r1 - pointer to registers on stack |
| 303 | @ | 292 | @ |
| 304 | mov r0, r2 @ address (pc) | 293 | #ifdef MULTI_PABORT |
| 294 | mov r0, r2 @ pass address of aborted instruction. | ||
| 295 | ldr r4, .LCprocfns | ||
| 296 | mov lr, pc | ||
| 297 | ldr pc, [r4, #PROCESSOR_PABT_FUNC] | ||
| 298 | #else | ||
| 299 | CPU_PABORT_HANDLER(r0, r2) | ||
| 300 | #endif | ||
| 301 | msr cpsr_c, r9 @ Maybe enable interrupts | ||
| 305 | mov r1, sp @ regs | 302 | mov r1, sp @ regs |
| 306 | bl do_PrefetchAbort @ call abort handler | 303 | bl do_PrefetchAbort @ call abort handler |
| 307 | 304 | ||
| @@ -320,16 +317,12 @@ __pabt_svc: | |||
| 320 | .align 5 | 317 | .align 5 |
| 321 | .LCcralign: | 318 | .LCcralign: |
| 322 | .word cr_alignment | 319 | .word cr_alignment |
| 323 | #ifdef MULTI_ABORT | 320 | #ifdef MULTI_DABORT |
| 324 | .LCprocfns: | 321 | .LCprocfns: |
| 325 | .word processor | 322 | .word processor |
| 326 | #endif | 323 | #endif |
| 327 | .LCfp: | 324 | .LCfp: |
| 328 | .word fp_enter | 325 | .word fp_enter |
| 329 | #ifdef CONFIG_PREEMPT | ||
| 330 | .LCirq_stat: | ||
| 331 | .word irq_stat | ||
| 332 | #endif | ||
| 333 | 326 | ||
| 334 | /* | 327 | /* |
| 335 | * User mode handlers | 328 | * User mode handlers |
| @@ -404,12 +397,12 @@ __dabt_usr: | |||
| 404 | @ The abort handler must return the aborted address in r0, and | 397 | @ The abort handler must return the aborted address in r0, and |
| 405 | @ the fault status register in r1. | 398 | @ the fault status register in r1. |
| 406 | @ | 399 | @ |
| 407 | #ifdef MULTI_ABORT | 400 | #ifdef MULTI_DABORT |
| 408 | ldr r4, .LCprocfns | 401 | ldr r4, .LCprocfns |
| 409 | mov lr, pc | 402 | mov lr, pc |
| 410 | ldr pc, [r4] | 403 | ldr pc, [r4, #PROCESSOR_DABT_FUNC] |
| 411 | #else | 404 | #else |
| 412 | bl CPU_ABORT_HANDLER | 405 | bl CPU_DABORT_HANDLER |
| 413 | #endif | 406 | #endif |
| 414 | 407 | ||
| 415 | @ | 408 | @ |
| @@ -455,10 +448,6 @@ __irq_usr: | |||
| 455 | __und_usr: | 448 | __und_usr: |
| 456 | usr_entry | 449 | usr_entry |
| 457 | 450 | ||
| 458 | tst r3, #PSR_T_BIT @ Thumb mode? | ||
| 459 | bne __und_usr_unknown @ ignore FP | ||
| 460 | sub r4, r2, #4 | ||
| 461 | |||
| 462 | @ | 451 | @ |
| 463 | @ fall through to the emulation code, which returns using r9 if | 452 | @ fall through to the emulation code, which returns using r9 if |
| 464 | @ it has emulated the instruction, or the more conventional lr | 453 | @ it has emulated the instruction, or the more conventional lr |
| @@ -468,7 +457,24 @@ __und_usr: | |||
| 468 | @ | 457 | @ |
| 469 | adr r9, ret_from_exception | 458 | adr r9, ret_from_exception |
| 470 | adr lr, __und_usr_unknown | 459 | adr lr, __und_usr_unknown |
| 471 | 1: ldrt r0, [r4] | 460 | tst r3, #PSR_T_BIT @ Thumb mode? |
| 461 | subeq r4, r2, #4 @ ARM instr at LR - 4 | ||
| 462 | subne r4, r2, #2 @ Thumb instr at LR - 2 | ||
| 463 | 1: ldreqt r0, [r4] | ||
| 464 | beq call_fpe | ||
| 465 | @ Thumb instruction | ||
| 466 | #if __LINUX_ARM_ARCH__ >= 7 | ||
| 467 | 2: ldrht r5, [r4], #2 | ||
| 468 | and r0, r5, #0xf800 @ mask bits 111x x... .... .... | ||
| 469 | cmp r0, #0xe800 @ 32bit instruction if xx != 0 | ||
| 470 | blo __und_usr_unknown | ||
| 471 | 3: ldrht r0, [r4] | ||
| 472 | add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 | ||
| 473 | orr r0, r0, r5, lsl #16 | ||
| 474 | #else | ||
| 475 | b __und_usr_unknown | ||
| 476 | #endif | ||
| 477 | |||
| 472 | @ | 478 | @ |
| 473 | @ fallthrough to call_fpe | 479 | @ fallthrough to call_fpe |
| 474 | @ | 480 | @ |
| @@ -477,10 +483,14 @@ __und_usr: | |||
| 477 | * The out of line fixup for the ldrt above. | 483 | * The out of line fixup for the ldrt above. |
| 478 | */ | 484 | */ |
| 479 | .section .fixup, "ax" | 485 | .section .fixup, "ax" |
| 480 | 2: mov pc, r9 | 486 | 4: mov pc, r9 |
| 481 | .previous | 487 | .previous |
| 482 | .section __ex_table,"a" | 488 | .section __ex_table,"a" |
| 483 | .long 1b, 2b | 489 | .long 1b, 4b |
| 490 | #if __LINUX_ARM_ARCH__ >= 7 | ||
| 491 | .long 2b, 4b | ||
| 492 | .long 3b, 4b | ||
| 493 | #endif | ||
| 484 | .previous | 494 | .previous |
| 485 | 495 | ||
| 486 | /* | 496 | /* |
| @@ -507,9 +517,16 @@ __und_usr: | |||
| 507 | * r10 = this threads thread_info structure. | 517 | * r10 = this threads thread_info structure. |
| 508 | * lr = unrecognised instruction return address | 518 | * lr = unrecognised instruction return address |
| 509 | */ | 519 | */ |
| 520 | @ | ||
| 521 | @ Fall-through from Thumb-2 __und_usr | ||
| 522 | @ | ||
| 523 | #ifdef CONFIG_NEON | ||
| 524 | adr r6, .LCneon_thumb_opcodes | ||
| 525 | b 2f | ||
| 526 | #endif | ||
| 510 | call_fpe: | 527 | call_fpe: |
| 511 | #ifdef CONFIG_NEON | 528 | #ifdef CONFIG_NEON |
| 512 | adr r6, .LCneon_opcodes | 529 | adr r6, .LCneon_arm_opcodes |
| 513 | 2: | 530 | 2: |
| 514 | ldr r7, [r6], #4 @ mask value | 531 | ldr r7, [r6], #4 @ mask value |
| 515 | cmp r7, #0 @ end mask? | 532 | cmp r7, #0 @ end mask? |
| @@ -526,6 +543,7 @@ call_fpe: | |||
| 526 | 1: | 543 | 1: |
| 527 | #endif | 544 | #endif |
| 528 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 | 545 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
| 546 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 | ||
| 529 | #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) | 547 | #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) |
| 530 | and r8, r0, #0x0f000000 @ mask out op-code bits | 548 | and r8, r0, #0x0f000000 @ mask out op-code bits |
| 531 | teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? | 549 | teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? |
| @@ -577,7 +595,7 @@ call_fpe: | |||
| 577 | #ifdef CONFIG_NEON | 595 | #ifdef CONFIG_NEON |
| 578 | .align 6 | 596 | .align 6 |
| 579 | 597 | ||
| 580 | .LCneon_opcodes: | 598 | .LCneon_arm_opcodes: |
| 581 | .word 0xfe000000 @ mask | 599 | .word 0xfe000000 @ mask |
| 582 | .word 0xf2000000 @ opcode | 600 | .word 0xf2000000 @ opcode |
| 583 | 601 | ||
| @@ -586,6 +604,16 @@ call_fpe: | |||
| 586 | 604 | ||
| 587 | .word 0x00000000 @ mask | 605 | .word 0x00000000 @ mask |
| 588 | .word 0x00000000 @ opcode | 606 | .word 0x00000000 @ opcode |
| 607 | |||
| 608 | .LCneon_thumb_opcodes: | ||
| 609 | .word 0xef000000 @ mask | ||
| 610 | .word 0xef000000 @ opcode | ||
| 611 | |||
| 612 | .word 0xff100000 @ mask | ||
| 613 | .word 0xf9000000 @ opcode | ||
| 614 | |||
| 615 | .word 0x00000000 @ mask | ||
| 616 | .word 0x00000000 @ opcode | ||
| 589 | #endif | 617 | #endif |
| 590 | 618 | ||
| 591 | do_fpe: | 619 | do_fpe: |
| @@ -619,8 +647,15 @@ __und_usr_unknown: | |||
| 619 | __pabt_usr: | 647 | __pabt_usr: |
| 620 | usr_entry | 648 | usr_entry |
| 621 | 649 | ||
| 650 | #ifdef MULTI_PABORT | ||
| 651 | mov r0, r2 @ pass address of aborted instruction. | ||
| 652 | ldr r4, .LCprocfns | ||
| 653 | mov lr, pc | ||
| 654 | ldr pc, [r4, #PROCESSOR_PABT_FUNC] | ||
| 655 | #else | ||
| 656 | CPU_PABORT_HANDLER(r0, r2) | ||
| 657 | #endif | ||
| 622 | enable_irq @ Enable interrupts | 658 | enable_irq @ Enable interrupts |
| 623 | mov r0, r2 @ address (pc) | ||
| 624 | mov r1, sp @ regs | 659 | mov r1, sp @ regs |
| 625 | bl do_PrefetchAbort @ call abort handler | 660 | bl do_PrefetchAbort @ call abort handler |
| 626 | /* fall through */ | 661 | /* fall through */ |
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 6c90c50a9ee3..597ed00a08d8 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S | |||
| @@ -352,6 +352,11 @@ sys_mmap2: | |||
| 352 | b do_mmap2 | 352 | b do_mmap2 |
| 353 | #endif | 353 | #endif |
| 354 | 354 | ||
| 355 | ENTRY(pabort_ifar) | ||
| 356 | mrc p15, 0, r0, cr6, cr0, 2 | ||
| 357 | ENTRY(pabort_noifar) | ||
| 358 | mov pc, lr | ||
| 359 | |||
| 355 | #ifdef CONFIG_OABI_COMPAT | 360 | #ifdef CONFIG_OABI_COMPAT |
| 356 | 361 | ||
| 357 | /* | 362 | /* |
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S index 50f667febe29..7e9c00a8a412 100644 --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S | |||
| @@ -75,8 +75,13 @@ __error_p: | |||
| 75 | #ifdef CONFIG_DEBUG_LL | 75 | #ifdef CONFIG_DEBUG_LL |
| 76 | adr r0, str_p1 | 76 | adr r0, str_p1 |
| 77 | bl printascii | 77 | bl printascii |
| 78 | mov r0, r9 | ||
| 79 | bl printhex8 | ||
| 80 | adr r0, str_p2 | ||
| 81 | bl printascii | ||
| 78 | b __error | 82 | b __error |
| 79 | str_p1: .asciz "\nError: unrecognized/unsupported processor variant.\n" | 83 | str_p1: .asciz "\nError: unrecognized/unsupported processor variant (0x" |
| 84 | str_p2: .asciz ").\n" | ||
| 80 | .align | 85 | .align |
| 81 | #endif | 86 | #endif |
| 82 | 87 | ||
diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c index d51bc8b60557..b4565bb133c1 100644 --- a/arch/arm/kernel/kprobes-decode.c +++ b/arch/arm/kernel/kprobes-decode.c | |||
| @@ -1176,7 +1176,7 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi) | |||
| 1176 | * *S (bit 20) updates condition codes | 1176 | * *S (bit 20) updates condition codes |
| 1177 | * ADC/SBC/RSC reads the C flag | 1177 | * ADC/SBC/RSC reads the C flag |
| 1178 | */ | 1178 | */ |
| 1179 | insn &= 0xfff00ff0; /* Rn = r0, Rd = r0 */ | 1179 | insn &= 0xfff00fff; /* Rn = r0, Rd = r0 */ |
| 1180 | asi->insn[0] = insn; | 1180 | asi->insn[0] = insn; |
| 1181 | asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */ | 1181 | asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */ |
| 1182 | emulate_alu_imm_rwflags : emulate_alu_imm_rflags; | 1182 | emulate_alu_imm_rwflags : emulate_alu_imm_rflags; |
diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c index 13e371aad879..5593dd207216 100644 --- a/arch/arm/kernel/kprobes.c +++ b/arch/arm/kernel/kprobes.c | |||
| @@ -66,7 +66,7 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p) | |||
| 66 | return -ENOMEM; | 66 | return -ENOMEM; |
| 67 | for (is = 0; is < MAX_INSN_SIZE; ++is) | 67 | for (is = 0; is < MAX_INSN_SIZE; ++is) |
| 68 | p->ainsn.insn[is] = tmp_insn[is]; | 68 | p->ainsn.insn[is] = tmp_insn[is]; |
| 69 | flush_insns(&p->ainsn.insn, MAX_INSN_SIZE); | 69 | flush_insns(p->ainsn.insn, MAX_INSN_SIZE); |
| 70 | break; | 70 | break; |
| 71 | 71 | ||
| 72 | case INSN_GOOD_NO_SLOT: /* instruction doesn't need insn slot */ | 72 | case INSN_GOOD_NO_SLOT: /* instruction doesn't need insn slot */ |
diff --git a/arch/arm/kernel/semaphore.c b/arch/arm/kernel/semaphore.c deleted file mode 100644 index 981fe5c6ccbe..000000000000 --- a/arch/arm/kernel/semaphore.c +++ /dev/null | |||
| @@ -1,221 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * ARM semaphore implementation, taken from | ||
| 3 | * | ||
| 4 | * i386 semaphore implementation. | ||
| 5 | * | ||
| 6 | * (C) Copyright 1999 Linus Torvalds | ||
| 7 | * | ||
| 8 | * Modified for ARM by Russell King | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | #include <linux/module.h> | ||
| 15 | #include <linux/sched.h> | ||
| 16 | #include <linux/errno.h> | ||
| 17 | #include <linux/init.h> | ||
| 18 | |||
| 19 | #include <asm/semaphore.h> | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Semaphores are implemented using a two-way counter: | ||
| 23 | * The "count" variable is decremented for each process | ||
| 24 | * that tries to acquire the semaphore, while the "sleeping" | ||
| 25 | * variable is a count of such acquires. | ||
| 26 | * | ||
| 27 | * Notably, the inline "up()" and "down()" functions can | ||
| 28 | * efficiently test if they need to do any extra work (up | ||
| 29 | * needs to do something only if count was negative before | ||
| 30 | * the increment operation. | ||
| 31 | * | ||
| 32 | * "sleeping" and the contention routine ordering is | ||
| 33 | * protected by the semaphore spinlock. | ||
| 34 | * | ||
| 35 | * Note that these functions are only called when there is | ||
| 36 | * contention on the lock, and as such all this is the | ||
| 37 | * "non-critical" part of the whole semaphore business. The | ||
| 38 | * critical part is the inline stuff in <asm/semaphore.h> | ||
| 39 | * where we want to avoid any extra jumps and calls. | ||
| 40 | */ | ||
| 41 | |||
| 42 | /* | ||
| 43 | * Logic: | ||
| 44 | * - only on a boundary condition do we need to care. When we go | ||
| 45 | * from a negative count to a non-negative, we wake people up. | ||
| 46 | * - when we go from a non-negative count to a negative do we | ||
| 47 | * (a) synchronize with the "sleeper" count and (b) make sure | ||
| 48 | * that we're on the wakeup list before we synchronize so that | ||
| 49 | * we cannot lose wakeup events. | ||
| 50 | */ | ||
| 51 | |||
| 52 | void __up(struct semaphore *sem) | ||
| 53 | { | ||
| 54 | wake_up(&sem->wait); | ||
| 55 | } | ||
| 56 | |||
| 57 | static DEFINE_SPINLOCK(semaphore_lock); | ||
| 58 | |||
| 59 | void __sched __down(struct semaphore * sem) | ||
| 60 | { | ||
| 61 | struct task_struct *tsk = current; | ||
| 62 | DECLARE_WAITQUEUE(wait, tsk); | ||
| 63 | tsk->state = TASK_UNINTERRUPTIBLE; | ||
| 64 | add_wait_queue_exclusive(&sem->wait, &wait); | ||
| 65 | |||
| 66 | spin_lock_irq(&semaphore_lock); | ||
| 67 | sem->sleepers++; | ||
| 68 | for (;;) { | ||
| 69 | int sleepers = sem->sleepers; | ||
| 70 | |||
| 71 | /* | ||
| 72 | * Add "everybody else" into it. They aren't | ||
| 73 | * playing, because we own the spinlock. | ||
| 74 | */ | ||
| 75 | if (!atomic_add_negative(sleepers - 1, &sem->count)) { | ||
| 76 | sem->sleepers = 0; | ||
| 77 | break; | ||
| 78 | } | ||
| 79 | sem->sleepers = 1; /* us - see -1 above */ | ||
| 80 | spin_unlock_irq(&semaphore_lock); | ||
| 81 | |||
| 82 | schedule(); | ||
| 83 | tsk->state = TASK_UNINTERRUPTIBLE; | ||
| 84 | spin_lock_irq(&semaphore_lock); | ||
| 85 | } | ||
| 86 | spin_unlock_irq(&semaphore_lock); | ||
| 87 | remove_wait_queue(&sem->wait, &wait); | ||
| 88 | tsk->state = TASK_RUNNING; | ||
| 89 | wake_up(&sem->wait); | ||
| 90 | } | ||
| 91 | |||
| 92 | int __sched __down_interruptible(struct semaphore * sem) | ||
| 93 | { | ||
| 94 | int retval = 0; | ||
| 95 | struct task_struct *tsk = current; | ||
| 96 | DECLARE_WAITQUEUE(wait, tsk); | ||
| 97 | tsk->state = TASK_INTERRUPTIBLE; | ||
| 98 | add_wait_queue_exclusive(&sem->wait, &wait); | ||
| 99 | |||
| 100 | spin_lock_irq(&semaphore_lock); | ||
| 101 | sem->sleepers ++; | ||
| 102 | for (;;) { | ||
| 103 | int sleepers = sem->sleepers; | ||
| 104 | |||
| 105 | /* | ||
| 106 | * With signals pending, this turns into | ||
| 107 | * the trylock failure case - we won't be | ||
| 108 | * sleeping, and we* can't get the lock as | ||
| 109 | * it has contention. Just correct the count | ||
| 110 | * and exit. | ||
| 111 | */ | ||
| 112 | if (signal_pending(current)) { | ||
| 113 | retval = -EINTR; | ||
| 114 | sem->sleepers = 0; | ||
| 115 | atomic_add(sleepers, &sem->count); | ||
| 116 | break; | ||
| 117 | } | ||
| 118 | |||
| 119 | /* | ||
| 120 | * Add "everybody else" into it. They aren't | ||
| 121 | * playing, because we own the spinlock. The | ||
| 122 | * "-1" is because we're still hoping to get | ||
| 123 | * the lock. | ||
| 124 | */ | ||
| 125 | if (!atomic_add_negative(sleepers - 1, &sem->count)) { | ||
| 126 | sem->sleepers = 0; | ||
| 127 | break; | ||
| 128 | } | ||
| 129 | sem->sleepers = 1; /* us - see -1 above */ | ||
| 130 | spin_unlock_irq(&semaphore_lock); | ||
| 131 | |||
| 132 | schedule(); | ||
| 133 | tsk->state = TASK_INTERRUPTIBLE; | ||
| 134 | spin_lock_irq(&semaphore_lock); | ||
| 135 | } | ||
| 136 | spin_unlock_irq(&semaphore_lock); | ||
| 137 | tsk->state = TASK_RUNNING; | ||
| 138 | remove_wait_queue(&sem->wait, &wait); | ||
| 139 | wake_up(&sem->wait); | ||
| 140 | return retval; | ||
| 141 | } | ||
| 142 | |||
| 143 | /* | ||
| 144 | * Trylock failed - make sure we correct for | ||
| 145 | * having decremented the count. | ||
| 146 | * | ||
| 147 | * We could have done the trylock with a | ||
| 148 | * single "cmpxchg" without failure cases, | ||
| 149 | * but then it wouldn't work on a 386. | ||
| 150 | */ | ||
| 151 | int __down_trylock(struct semaphore * sem) | ||
| 152 | { | ||
| 153 | int sleepers; | ||
| 154 | unsigned long flags; | ||
| 155 | |||
| 156 | spin_lock_irqsave(&semaphore_lock, flags); | ||
| 157 | sleepers = sem->sleepers + 1; | ||
| 158 | sem->sleepers = 0; | ||
| 159 | |||
| 160 | /* | ||
| 161 | * Add "everybody else" and us into it. They aren't | ||
| 162 | * playing, because we own the spinlock. | ||
| 163 | */ | ||
| 164 | if (!atomic_add_negative(sleepers, &sem->count)) | ||
| 165 | wake_up(&sem->wait); | ||
| 166 | |||
| 167 | spin_unlock_irqrestore(&semaphore_lock, flags); | ||
| 168 | return 1; | ||
| 169 | } | ||
| 170 | |||
| 171 | /* | ||
| 172 | * The semaphore operations have a special calling sequence that | ||
| 173 | * allow us to do a simpler in-line version of them. These routines | ||
| 174 | * need to convert that sequence back into the C sequence when | ||
| 175 | * there is contention on the semaphore. | ||
| 176 | * | ||
| 177 | * ip contains the semaphore pointer on entry. Save the C-clobbered | ||
| 178 | * registers (r0 to r3 and lr), but not ip, as we use it as a return | ||
| 179 | * value in some cases.. | ||
| 180 | * To remain AAPCS compliant (64-bit stack align) we save r4 as well. | ||
| 181 | */ | ||
| 182 | asm(" .section .sched.text,\"ax\",%progbits \n\ | ||
| 183 | .align 5 \n\ | ||
| 184 | .globl __down_failed \n\ | ||
| 185 | __down_failed: \n\ | ||
| 186 | stmfd sp!, {r0 - r4, lr} \n\ | ||
| 187 | mov r0, ip \n\ | ||
| 188 | bl __down \n\ | ||
| 189 | ldmfd sp!, {r0 - r4, pc} \n\ | ||
| 190 | \n\ | ||
| 191 | .align 5 \n\ | ||
| 192 | .globl __down_interruptible_failed \n\ | ||
| 193 | __down_interruptible_failed: \n\ | ||
| 194 | stmfd sp!, {r0 - r4, lr} \n\ | ||
| 195 | mov r0, ip \n\ | ||
| 196 | bl __down_interruptible \n\ | ||
| 197 | mov ip, r0 \n\ | ||
| 198 | ldmfd sp!, {r0 - r4, pc} \n\ | ||
| 199 | \n\ | ||
| 200 | .align 5 \n\ | ||
| 201 | .globl __down_trylock_failed \n\ | ||
| 202 | __down_trylock_failed: \n\ | ||
| 203 | stmfd sp!, {r0 - r4, lr} \n\ | ||
| 204 | mov r0, ip \n\ | ||
| 205 | bl __down_trylock \n\ | ||
| 206 | mov ip, r0 \n\ | ||
| 207 | ldmfd sp!, {r0 - r4, pc} \n\ | ||
| 208 | \n\ | ||
| 209 | .align 5 \n\ | ||
| 210 | .globl __up_wakeup \n\ | ||
| 211 | __up_wakeup: \n\ | ||
| 212 | stmfd sp!, {r0 - r4, lr} \n\ | ||
| 213 | mov r0, ip \n\ | ||
| 214 | bl __up \n\ | ||
| 215 | ldmfd sp!, {r0 - r4, pc} \n\ | ||
| 216 | "); | ||
| 217 | |||
| 218 | EXPORT_SYMBOL(__down_failed); | ||
| 219 | EXPORT_SYMBOL(__down_interruptible_failed); | ||
| 220 | EXPORT_SYMBOL(__down_trylock_failed); | ||
| 221 | EXPORT_SYMBOL(__up_wakeup); | ||
diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c index e8b98046895b..96ab5f52949c 100644 --- a/arch/arm/kernel/sys_oabi-compat.c +++ b/arch/arm/kernel/sys_oabi-compat.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | * sys_stat64: | 25 | * sys_stat64: |
| 26 | * sys_lstat64: | 26 | * sys_lstat64: |
| 27 | * sys_fstat64: | 27 | * sys_fstat64: |
| 28 | * sys_fstatat64: | ||
| 28 | * | 29 | * |
| 29 | * struct stat64 has different sizes and some members are shifted | 30 | * struct stat64 has different sizes and some members are shifted |
| 30 | * Compatibility wrappers are needed for them and provided below. | 31 | * Compatibility wrappers are needed for them and provided below. |
| @@ -169,6 +170,29 @@ asmlinkage long sys_oabi_fstat64(unsigned long fd, | |||
| 169 | return error; | 170 | return error; |
| 170 | } | 171 | } |
| 171 | 172 | ||
| 173 | asmlinkage long sys_oabi_fstatat64(int dfd, | ||
| 174 | char __user *filename, | ||
| 175 | struct oldabi_stat64 __user *statbuf, | ||
| 176 | int flag) | ||
| 177 | { | ||
| 178 | struct kstat stat; | ||
| 179 | int error = -EINVAL; | ||
| 180 | |||
| 181 | if ((flag & ~AT_SYMLINK_NOFOLLOW) != 0) | ||
| 182 | goto out; | ||
| 183 | |||
| 184 | if (flag & AT_SYMLINK_NOFOLLOW) | ||
| 185 | error = vfs_lstat_fd(dfd, filename, &stat); | ||
| 186 | else | ||
| 187 | error = vfs_stat_fd(dfd, filename, &stat); | ||
| 188 | |||
| 189 | if (!error) | ||
| 190 | error = cp_oldabi_stat64(&stat, statbuf); | ||
| 191 | |||
| 192 | out: | ||
| 193 | return error; | ||
| 194 | } | ||
| 195 | |||
| 172 | struct oabi_flock64 { | 196 | struct oabi_flock64 { |
| 173 | short l_type; | 197 | short l_type; |
| 174 | short l_whence; | 198 | short l_whence; |
diff --git a/arch/arm/kernel/thumbee.c b/arch/arm/kernel/thumbee.c new file mode 100644 index 000000000000..df3f6b7ebcea --- /dev/null +++ b/arch/arm/kernel/thumbee.c | |||
| @@ -0,0 +1,81 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/kernel/thumbee.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #include <linux/kernel.h> | ||
| 21 | #include <linux/init.h> | ||
| 22 | |||
| 23 | #include <asm/thread_notify.h> | ||
| 24 | |||
| 25 | /* | ||
| 26 | * Access to the ThumbEE Handler Base register | ||
| 27 | */ | ||
| 28 | static inline unsigned long teehbr_read() | ||
| 29 | { | ||
| 30 | unsigned long v; | ||
| 31 | asm("mrc p14, 6, %0, c1, c0, 0\n" : "=r" (v)); | ||
| 32 | return v; | ||
| 33 | } | ||
| 34 | |||
| 35 | static inline void teehbr_write(unsigned long v) | ||
| 36 | { | ||
| 37 | asm("mcr p14, 6, %0, c1, c0, 0\n" : : "r" (v)); | ||
| 38 | } | ||
| 39 | |||
| 40 | static int thumbee_notifier(struct notifier_block *self, unsigned long cmd, void *t) | ||
| 41 | { | ||
| 42 | struct thread_info *thread = t; | ||
| 43 | |||
| 44 | switch (cmd) { | ||
| 45 | case THREAD_NOTIFY_FLUSH: | ||
| 46 | thread->thumbee_state = 0; | ||
| 47 | break; | ||
| 48 | case THREAD_NOTIFY_SWITCH: | ||
| 49 | current_thread_info()->thumbee_state = teehbr_read(); | ||
| 50 | teehbr_write(thread->thumbee_state); | ||
| 51 | break; | ||
| 52 | } | ||
| 53 | |||
| 54 | return NOTIFY_DONE; | ||
| 55 | } | ||
| 56 | |||
| 57 | static struct notifier_block thumbee_notifier_block = { | ||
| 58 | .notifier_call = thumbee_notifier, | ||
| 59 | }; | ||
| 60 | |||
| 61 | static int __init thumbee_init(void) | ||
| 62 | { | ||
| 63 | unsigned long pfr0; | ||
| 64 | unsigned int cpu_arch = cpu_architecture(); | ||
| 65 | |||
| 66 | if (cpu_arch < CPU_ARCH_ARMv7) | ||
| 67 | return 0; | ||
| 68 | |||
| 69 | /* processor feature register 0 */ | ||
| 70 | asm("mrc p15, 0, %0, c0, c1, 0\n" : "=r" (pfr0)); | ||
| 71 | if ((pfr0 & 0x0000f000) != 0x00001000) | ||
| 72 | return 0; | ||
| 73 | |||
| 74 | printk(KERN_INFO "ThumbEE CPU extension supported.\n"); | ||
| 75 | elf_hwcap |= HWCAP_THUMBEE; | ||
| 76 | thread_register_notifier(&thumbee_notifier_block); | ||
| 77 | |||
| 78 | return 0; | ||
| 79 | } | ||
| 80 | |||
| 81 | late_initcall(thumbee_init); | ||
diff --git a/arch/arm/mach-aaec2000/clock.c b/arch/arm/mach-aaec2000/clock.c index 74aa7a39bb68..e10ee158d720 100644 --- a/arch/arm/mach-aaec2000/clock.c +++ b/arch/arm/mach-aaec2000/clock.c | |||
| @@ -18,8 +18,6 @@ | |||
| 18 | #include <linux/clk.h> | 18 | #include <linux/clk.h> |
| 19 | #include <linux/mutex.h> | 19 | #include <linux/mutex.h> |
| 20 | 20 | ||
| 21 | #include <asm/semaphore.h> | ||
| 22 | |||
| 23 | #include "clock.h" | 21 | #include "clock.h" |
| 24 | 22 | ||
| 25 | static LIST_HEAD(clocks); | 23 | static LIST_HEAD(clocks); |
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 074dcd5d9a7e..0fc07b6db749 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig | |||
| @@ -12,18 +12,28 @@ config ARCH_AT91RM9200 | |||
| 12 | 12 | ||
| 13 | config ARCH_AT91SAM9260 | 13 | config ARCH_AT91SAM9260 |
| 14 | bool "AT91SAM9260 or AT91SAM9XE" | 14 | bool "AT91SAM9260 or AT91SAM9XE" |
| 15 | select GENERIC_TIME | ||
| 16 | select GENERIC_CLOCKEVENTS | ||
| 15 | 17 | ||
| 16 | config ARCH_AT91SAM9261 | 18 | config ARCH_AT91SAM9261 |
| 17 | bool "AT91SAM9261" | 19 | bool "AT91SAM9261" |
| 20 | select GENERIC_TIME | ||
| 21 | select GENERIC_CLOCKEVENTS | ||
| 18 | 22 | ||
| 19 | config ARCH_AT91SAM9263 | 23 | config ARCH_AT91SAM9263 |
| 20 | bool "AT91SAM9263" | 24 | bool "AT91SAM9263" |
| 25 | select GENERIC_TIME | ||
| 26 | select GENERIC_CLOCKEVENTS | ||
| 21 | 27 | ||
| 22 | config ARCH_AT91SAM9RL | 28 | config ARCH_AT91SAM9RL |
| 23 | bool "AT91SAM9RL" | 29 | bool "AT91SAM9RL" |
| 30 | select GENERIC_TIME | ||
| 31 | select GENERIC_CLOCKEVENTS | ||
| 24 | 32 | ||
| 25 | config ARCH_AT91CAP9 | 33 | config ARCH_AT91CAP9 |
| 26 | bool "AT91CAP9" | 34 | bool "AT91CAP9" |
| 35 | select GENERIC_TIME | ||
| 36 | select GENERIC_CLOCKEVENTS | ||
| 27 | 37 | ||
| 28 | config ARCH_AT91X40 | 38 | config ARCH_AT91X40 |
| 29 | bool "AT91x40" | 39 | bool "AT91x40" |
| @@ -109,6 +119,13 @@ config MACH_KAFA | |||
| 109 | help | 119 | help |
| 110 | Select this if you are using Sperry-Sun's KAFA board. | 120 | Select this if you are using Sperry-Sun's KAFA board. |
| 111 | 121 | ||
| 122 | config MACH_ECBAT91 | ||
| 123 | bool "emQbit ECB_AT91 SBC" | ||
| 124 | depends on ARCH_AT91RM9200 | ||
| 125 | help | ||
| 126 | Select this if you are using emQbit's ECB_AT91 board. | ||
| 127 | <http://wiki.emqbit.com/free-ecb-at91> | ||
| 128 | |||
| 112 | endif | 129 | endif |
| 113 | 130 | ||
| 114 | # ---------------------------------------------------------- | 131 | # ---------------------------------------------------------- |
| @@ -133,6 +150,20 @@ config MACH_AT91SAM9260EK | |||
| 133 | Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit | 150 | Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit |
| 134 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933> | 151 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933> |
| 135 | 152 | ||
| 153 | config MACH_CAM60 | ||
| 154 | bool "KwikByte KB9260 (CAM60) board" | ||
| 155 | depends on ARCH_AT91SAM9260 | ||
| 156 | help | ||
| 157 | Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260. | ||
| 158 | <http://www.kwikbyte.com/KB9260.html> | ||
| 159 | |||
| 160 | config MACH_SAM9_L9260 | ||
| 161 | bool "Olimex SAM9-L9260 board" | ||
| 162 | depends on ARCH_AT91SAM9260 | ||
| 163 | help | ||
| 164 | Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260. | ||
| 165 | <http://www.olimex.com/dev/sam9-L9260.html> | ||
| 166 | |||
| 136 | endif | 167 | endif |
| 137 | 168 | ||
| 138 | # ---------------------------------------------------------- | 169 | # ---------------------------------------------------------- |
| @@ -216,7 +247,7 @@ comment "AT91 Board Options" | |||
| 216 | 247 | ||
| 217 | config MTD_AT91_DATAFLASH_CARD | 248 | config MTD_AT91_DATAFLASH_CARD |
| 218 | bool "Enable DataFlash Card support" | 249 | bool "Enable DataFlash Card support" |
| 219 | depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK) | 250 | depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK || MACH_SAM9_L9260 || MACH_ECBAT91) |
| 220 | help | 251 | help |
| 221 | Enable support for the DataFlash card. | 252 | Enable support for the DataFlash card. |
| 222 | 253 | ||
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index bf5f293dccf8..8d9bc0153b18 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile | |||
| @@ -29,9 +29,12 @@ obj-$(CONFIG_MACH_KB9200) += board-kb9202.o | |||
| 29 | obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o | 29 | obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o |
| 30 | obj-$(CONFIG_MACH_KAFA) += board-kafa.o | 30 | obj-$(CONFIG_MACH_KAFA) += board-kafa.o |
| 31 | obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o | 31 | obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o |
| 32 | obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o | ||
| 32 | 33 | ||
| 33 | # AT91SAM9260 board-specific support | 34 | # AT91SAM9260 board-specific support |
| 34 | obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o | 35 | obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o |
| 36 | obj-$(CONFIG_MACH_CAM60) += board-cam60.o | ||
| 37 | obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o | ||
| 35 | 38 | ||
| 36 | # AT91SAM9261 board-specific support | 39 | # AT91SAM9261 board-specific support |
| 37 | obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o | 40 | obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o |
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c index 48d27d8000b0..933fa8f55cbc 100644 --- a/arch/arm/mach-at91/at91cap9.c +++ b/arch/arm/mach-at91/at91cap9.c | |||
| @@ -13,12 +13,14 @@ | |||
| 13 | */ | 13 | */ |
| 14 | 14 | ||
| 15 | #include <linux/module.h> | 15 | #include <linux/module.h> |
| 16 | #include <linux/pm.h> | ||
| 16 | 17 | ||
| 17 | #include <asm/mach/arch.h> | 18 | #include <asm/mach/arch.h> |
| 18 | #include <asm/mach/map.h> | 19 | #include <asm/mach/map.h> |
| 19 | #include <asm/arch/at91cap9.h> | 20 | #include <asm/arch/at91cap9.h> |
| 20 | #include <asm/arch/at91_pmc.h> | 21 | #include <asm/arch/at91_pmc.h> |
| 21 | #include <asm/arch/at91_rstc.h> | 22 | #include <asm/arch/at91_rstc.h> |
| 23 | #include <asm/arch/at91_shdwc.h> | ||
| 22 | 24 | ||
| 23 | #include "generic.h" | 25 | #include "generic.h" |
| 24 | #include "clock.h" | 26 | #include "clock.h" |
| @@ -288,6 +290,12 @@ static void at91cap9_reset(void) | |||
| 288 | at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); | 290 | at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); |
| 289 | } | 291 | } |
| 290 | 292 | ||
| 293 | static void at91cap9_poweroff(void) | ||
| 294 | { | ||
| 295 | at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); | ||
| 296 | } | ||
| 297 | |||
| 298 | |||
| 291 | /* -------------------------------------------------------------------- | 299 | /* -------------------------------------------------------------------- |
| 292 | * AT91CAP9 processor initialization | 300 | * AT91CAP9 processor initialization |
| 293 | * -------------------------------------------------------------------- */ | 301 | * -------------------------------------------------------------------- */ |
| @@ -298,6 +306,7 @@ void __init at91cap9_initialize(unsigned long main_clock) | |||
| 298 | iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc)); | 306 | iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc)); |
| 299 | 307 | ||
| 300 | at91_arch_reset = at91cap9_reset; | 308 | at91_arch_reset = at91cap9_reset; |
| 309 | pm_power_off = at91cap9_poweroff; | ||
| 301 | at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1); | 310 | at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1); |
| 302 | 311 | ||
| 303 | /* Init clock subsystem */ | 312 | /* Init clock subsystem */ |
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c index c50fad9cd143..be526746e01e 100644 --- a/arch/arm/mach-at91/at91cap9_devices.c +++ b/arch/arm/mach-at91/at91cap9_devices.c | |||
| @@ -16,15 +16,15 @@ | |||
| 16 | 16 | ||
| 17 | #include <linux/dma-mapping.h> | 17 | #include <linux/dma-mapping.h> |
| 18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/mtd/physmap.h> | 19 | #include <linux/i2c-gpio.h> |
| 20 | 20 | ||
| 21 | #include <video/atmel_lcdc.h> | 21 | #include <video/atmel_lcdc.h> |
| 22 | 22 | ||
| 23 | #include <asm/arch/board.h> | 23 | #include <asm/arch/board.h> |
| 24 | #include <asm/arch/gpio.h> | 24 | #include <asm/arch/gpio.h> |
| 25 | #include <asm/arch/at91cap9.h> | 25 | #include <asm/arch/at91cap9.h> |
| 26 | #include <asm/arch/at91sam926x_mc.h> | ||
| 27 | #include <asm/arch/at91cap9_matrix.h> | 26 | #include <asm/arch/at91cap9_matrix.h> |
| 27 | #include <asm/arch/at91sam9_smc.h> | ||
| 28 | 28 | ||
| 29 | #include "generic.h" | 29 | #include "generic.h" |
| 30 | 30 | ||
| @@ -246,7 +246,7 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) | |||
| 246 | } | 246 | } |
| 247 | 247 | ||
| 248 | mmc0_data = *data; | 248 | mmc0_data = *data; |
| 249 | at91_clock_associate("mci0_clk", &at91cap9_mmc1_device.dev, "mci_clk"); | 249 | at91_clock_associate("mci0_clk", &at91cap9_mmc0_device.dev, "mci_clk"); |
| 250 | platform_device_register(&at91cap9_mmc0_device); | 250 | platform_device_register(&at91cap9_mmc0_device); |
| 251 | } else { /* MCI1 */ | 251 | } else { /* MCI1 */ |
| 252 | /* CLK */ | 252 | /* CLK */ |
| @@ -283,10 +283,15 @@ static struct at91_nand_data nand_data; | |||
| 283 | #define NAND_BASE AT91_CHIPSELECT_3 | 283 | #define NAND_BASE AT91_CHIPSELECT_3 |
| 284 | 284 | ||
| 285 | static struct resource nand_resources[] = { | 285 | static struct resource nand_resources[] = { |
| 286 | { | 286 | [0] = { |
| 287 | .start = NAND_BASE, | 287 | .start = NAND_BASE, |
| 288 | .end = NAND_BASE + SZ_256M - 1, | 288 | .end = NAND_BASE + SZ_256M - 1, |
| 289 | .flags = IORESOURCE_MEM, | 289 | .flags = IORESOURCE_MEM, |
| 290 | }, | ||
| 291 | [1] = { | ||
| 292 | .start = AT91_BASE_SYS + AT91_ECC, | ||
| 293 | .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1, | ||
| 294 | .flags = IORESOURCE_MEM, | ||
| 290 | } | 295 | } |
| 291 | }; | 296 | }; |
| 292 | 297 | ||
| @@ -344,6 +349,7 @@ void __init at91_add_device_nand(struct at91_nand_data *data) | |||
| 344 | void __init at91_add_device_nand(struct at91_nand_data *data) {} | 349 | void __init at91_add_device_nand(struct at91_nand_data *data) {} |
| 345 | #endif | 350 | #endif |
| 346 | 351 | ||
| 352 | |||
| 347 | /* -------------------------------------------------------------------- | 353 | /* -------------------------------------------------------------------- |
| 348 | * TWI (i2c) | 354 | * TWI (i2c) |
| 349 | * -------------------------------------------------------------------- */ | 355 | * -------------------------------------------------------------------- */ |
| @@ -532,13 +538,59 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) | |||
| 532 | 538 | ||
| 533 | 539 | ||
| 534 | /* -------------------------------------------------------------------- | 540 | /* -------------------------------------------------------------------- |
| 541 | * Timer/Counter block | ||
| 542 | * -------------------------------------------------------------------- */ | ||
| 543 | |||
| 544 | #ifdef CONFIG_ATMEL_TCLIB | ||
| 545 | |||
| 546 | static struct resource tcb_resources[] = { | ||
| 547 | [0] = { | ||
| 548 | .start = AT91CAP9_BASE_TCB0, | ||
| 549 | .end = AT91CAP9_BASE_TCB0 + SZ_16K - 1, | ||
| 550 | .flags = IORESOURCE_MEM, | ||
| 551 | }, | ||
| 552 | [1] = { | ||
| 553 | .start = AT91CAP9_ID_TCB, | ||
| 554 | .end = AT91CAP9_ID_TCB, | ||
| 555 | .flags = IORESOURCE_IRQ, | ||
| 556 | }, | ||
| 557 | }; | ||
| 558 | |||
| 559 | static struct platform_device at91cap9_tcb_device = { | ||
| 560 | .name = "atmel_tcb", | ||
| 561 | .id = 0, | ||
| 562 | .resource = tcb_resources, | ||
| 563 | .num_resources = ARRAY_SIZE(tcb_resources), | ||
| 564 | }; | ||
| 565 | |||
| 566 | static void __init at91_add_device_tc(void) | ||
| 567 | { | ||
| 568 | /* this chip has one clock and irq for all three TC channels */ | ||
| 569 | at91_clock_associate("tcb_clk", &at91cap9_tcb_device.dev, "t0_clk"); | ||
| 570 | platform_device_register(&at91cap9_tcb_device); | ||
| 571 | } | ||
| 572 | #else | ||
| 573 | static void __init at91_add_device_tc(void) { } | ||
| 574 | #endif | ||
| 575 | |||
| 576 | |||
| 577 | /* -------------------------------------------------------------------- | ||
| 535 | * RTT | 578 | * RTT |
| 536 | * -------------------------------------------------------------------- */ | 579 | * -------------------------------------------------------------------- */ |
| 537 | 580 | ||
| 581 | static struct resource rtt_resources[] = { | ||
| 582 | { | ||
| 583 | .start = AT91_BASE_SYS + AT91_RTT, | ||
| 584 | .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1, | ||
| 585 | .flags = IORESOURCE_MEM, | ||
| 586 | } | ||
| 587 | }; | ||
| 588 | |||
| 538 | static struct platform_device at91cap9_rtt_device = { | 589 | static struct platform_device at91cap9_rtt_device = { |
| 539 | .name = "at91_rtt", | 590 | .name = "at91_rtt", |
| 540 | .id = -1, | 591 | .id = 0, |
| 541 | .num_resources = 0, | 592 | .resource = rtt_resources, |
| 593 | .num_resources = ARRAY_SIZE(rtt_resources), | ||
| 542 | }; | 594 | }; |
| 543 | 595 | ||
| 544 | static void __init at91_add_device_rtt(void) | 596 | static void __init at91_add_device_rtt(void) |
| @@ -990,7 +1042,7 @@ static inline void configure_usart2_pins(unsigned pins) | |||
| 990 | at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */ | 1042 | at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */ |
| 991 | } | 1043 | } |
| 992 | 1044 | ||
| 993 | static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ | 1045 | static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ |
| 994 | struct platform_device *atmel_default_console_device; /* the serial console device */ | 1046 | struct platform_device *atmel_default_console_device; /* the serial console device */ |
| 995 | 1047 | ||
| 996 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) | 1048 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) |
| @@ -1031,8 +1083,6 @@ void __init at91_set_serial_console(unsigned portnr) | |||
| 1031 | { | 1083 | { |
| 1032 | if (portnr < ATMEL_MAX_UART) | 1084 | if (portnr < ATMEL_MAX_UART) |
| 1033 | atmel_default_console_device = at91_uarts[portnr]; | 1085 | atmel_default_console_device = at91_uarts[portnr]; |
| 1034 | if (!atmel_default_console_device) | ||
| 1035 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 1036 | } | 1086 | } |
| 1037 | 1087 | ||
| 1038 | void __init at91_add_device_serial(void) | 1088 | void __init at91_add_device_serial(void) |
| @@ -1043,6 +1093,9 @@ void __init at91_add_device_serial(void) | |||
| 1043 | if (at91_uarts[i]) | 1093 | if (at91_uarts[i]) |
| 1044 | platform_device_register(at91_uarts[i]); | 1094 | platform_device_register(at91_uarts[i]); |
| 1045 | } | 1095 | } |
| 1096 | |||
| 1097 | if (!atmel_default_console_device) | ||
| 1098 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 1046 | } | 1099 | } |
| 1047 | #else | 1100 | #else |
| 1048 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} | 1101 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} |
| @@ -1060,6 +1113,7 @@ static int __init at91_add_standard_devices(void) | |||
| 1060 | { | 1113 | { |
| 1061 | at91_add_device_rtt(); | 1114 | at91_add_device_rtt(); |
| 1062 | at91_add_device_watchdog(); | 1115 | at91_add_device_watchdog(); |
| 1116 | at91_add_device_tc(); | ||
| 1063 | return 0; | 1117 | return 0; |
| 1064 | } | 1118 | } |
| 1065 | 1119 | ||
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index ef6aeb86e980..de19bee83f75 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c | |||
| @@ -577,6 +577,90 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) | |||
| 577 | 577 | ||
| 578 | 578 | ||
| 579 | /* -------------------------------------------------------------------- | 579 | /* -------------------------------------------------------------------- |
| 580 | * Timer/Counter blocks | ||
| 581 | * -------------------------------------------------------------------- */ | ||
| 582 | |||
| 583 | #ifdef CONFIG_ATMEL_TCLIB | ||
| 584 | |||
| 585 | static struct resource tcb0_resources[] = { | ||
| 586 | [0] = { | ||
| 587 | .start = AT91RM9200_BASE_TCB0, | ||
| 588 | .end = AT91RM9200_BASE_TCB0 + SZ_16K - 1, | ||
| 589 | .flags = IORESOURCE_MEM, | ||
| 590 | }, | ||
| 591 | [1] = { | ||
| 592 | .start = AT91RM9200_ID_TC0, | ||
| 593 | .end = AT91RM9200_ID_TC0, | ||
| 594 | .flags = IORESOURCE_IRQ, | ||
| 595 | }, | ||
| 596 | [2] = { | ||
| 597 | .start = AT91RM9200_ID_TC1, | ||
| 598 | .end = AT91RM9200_ID_TC1, | ||
| 599 | .flags = IORESOURCE_IRQ, | ||
| 600 | }, | ||
| 601 | [3] = { | ||
| 602 | .start = AT91RM9200_ID_TC2, | ||
| 603 | .end = AT91RM9200_ID_TC2, | ||
| 604 | .flags = IORESOURCE_IRQ, | ||
| 605 | }, | ||
| 606 | }; | ||
| 607 | |||
| 608 | static struct platform_device at91rm9200_tcb0_device = { | ||
| 609 | .name = "atmel_tcb", | ||
| 610 | .id = 0, | ||
| 611 | .resource = tcb0_resources, | ||
| 612 | .num_resources = ARRAY_SIZE(tcb0_resources), | ||
| 613 | }; | ||
| 614 | |||
| 615 | static struct resource tcb1_resources[] = { | ||
| 616 | [0] = { | ||
| 617 | .start = AT91RM9200_BASE_TCB1, | ||
| 618 | .end = AT91RM9200_BASE_TCB1 + SZ_16K - 1, | ||
| 619 | .flags = IORESOURCE_MEM, | ||
| 620 | }, | ||
| 621 | [1] = { | ||
| 622 | .start = AT91RM9200_ID_TC3, | ||
| 623 | .end = AT91RM9200_ID_TC3, | ||
| 624 | .flags = IORESOURCE_IRQ, | ||
| 625 | }, | ||
| 626 | [2] = { | ||
| 627 | .start = AT91RM9200_ID_TC4, | ||
| 628 | .end = AT91RM9200_ID_TC4, | ||
| 629 | .flags = IORESOURCE_IRQ, | ||
| 630 | }, | ||
| 631 | [3] = { | ||
| 632 | .start = AT91RM9200_ID_TC5, | ||
| 633 | .end = AT91RM9200_ID_TC5, | ||
| 634 | .flags = IORESOURCE_IRQ, | ||
| 635 | }, | ||
| 636 | }; | ||
| 637 | |||
| 638 | static struct platform_device at91rm9200_tcb1_device = { | ||
| 639 | .name = "atmel_tcb", | ||
| 640 | .id = 1, | ||
| 641 | .resource = tcb1_resources, | ||
| 642 | .num_resources = ARRAY_SIZE(tcb1_resources), | ||
| 643 | }; | ||
| 644 | |||
| 645 | static void __init at91_add_device_tc(void) | ||
| 646 | { | ||
| 647 | /* this chip has a separate clock and irq for each TC channel */ | ||
| 648 | at91_clock_associate("tc0_clk", &at91rm9200_tcb0_device.dev, "t0_clk"); | ||
| 649 | at91_clock_associate("tc1_clk", &at91rm9200_tcb0_device.dev, "t1_clk"); | ||
| 650 | at91_clock_associate("tc2_clk", &at91rm9200_tcb0_device.dev, "t2_clk"); | ||
| 651 | platform_device_register(&at91rm9200_tcb0_device); | ||
| 652 | |||
| 653 | at91_clock_associate("tc3_clk", &at91rm9200_tcb1_device.dev, "t0_clk"); | ||
| 654 | at91_clock_associate("tc4_clk", &at91rm9200_tcb1_device.dev, "t1_clk"); | ||
| 655 | at91_clock_associate("tc5_clk", &at91rm9200_tcb1_device.dev, "t2_clk"); | ||
| 656 | platform_device_register(&at91rm9200_tcb1_device); | ||
| 657 | } | ||
| 658 | #else | ||
| 659 | static void __init at91_add_device_tc(void) { } | ||
| 660 | #endif | ||
| 661 | |||
| 662 | |||
| 663 | /* -------------------------------------------------------------------- | ||
| 580 | * RTC | 664 | * RTC |
| 581 | * -------------------------------------------------------------------- */ | 665 | * -------------------------------------------------------------------- */ |
| 582 | 666 | ||
| @@ -1019,7 +1103,7 @@ static inline void configure_usart3_pins(unsigned pins) | |||
| 1019 | at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */ | 1103 | at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */ |
| 1020 | } | 1104 | } |
| 1021 | 1105 | ||
| 1022 | static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ | 1106 | static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ |
| 1023 | struct platform_device *atmel_default_console_device; /* the serial console device */ | 1107 | struct platform_device *atmel_default_console_device; /* the serial console device */ |
| 1024 | 1108 | ||
| 1025 | void __init __deprecated at91_init_serial(struct at91_uart_config *config) | 1109 | void __init __deprecated at91_init_serial(struct at91_uart_config *config) |
| @@ -1110,8 +1194,6 @@ void __init at91_set_serial_console(unsigned portnr) | |||
| 1110 | { | 1194 | { |
| 1111 | if (portnr < ATMEL_MAX_UART) | 1195 | if (portnr < ATMEL_MAX_UART) |
| 1112 | atmel_default_console_device = at91_uarts[portnr]; | 1196 | atmel_default_console_device = at91_uarts[portnr]; |
| 1113 | if (!atmel_default_console_device) | ||
| 1114 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 1115 | } | 1197 | } |
| 1116 | 1198 | ||
| 1117 | void __init at91_add_device_serial(void) | 1199 | void __init at91_add_device_serial(void) |
| @@ -1122,6 +1204,9 @@ void __init at91_add_device_serial(void) | |||
| 1122 | if (at91_uarts[i]) | 1204 | if (at91_uarts[i]) |
| 1123 | platform_device_register(at91_uarts[i]); | 1205 | platform_device_register(at91_uarts[i]); |
| 1124 | } | 1206 | } |
| 1207 | |||
| 1208 | if (!atmel_default_console_device) | ||
| 1209 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 1125 | } | 1210 | } |
| 1126 | #else | 1211 | #else |
| 1127 | void __init __deprecated at91_init_serial(struct at91_uart_config *config) {} | 1212 | void __init __deprecated at91_init_serial(struct at91_uart_config *config) {} |
| @@ -1141,6 +1226,7 @@ static int __init at91_add_standard_devices(void) | |||
| 1141 | { | 1226 | { |
| 1142 | at91_add_device_rtc(); | 1227 | at91_add_device_rtc(); |
| 1143 | at91_add_device_watchdog(); | 1228 | at91_add_device_watchdog(); |
| 1229 | at91_add_device_tc(); | ||
| 1144 | return 0; | 1230 | return 0; |
| 1145 | } | 1231 | } |
| 1146 | 1232 | ||
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 18d06612ce8a..ee26550cdc21 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
| 14 | #include <linux/pm.h> | ||
| 14 | 15 | ||
| 15 | #include <asm/mach/arch.h> | 16 | #include <asm/mach/arch.h> |
| 16 | #include <asm/mach/map.h> | 17 | #include <asm/mach/map.h> |
| @@ -18,6 +19,7 @@ | |||
| 18 | #include <asm/arch/at91sam9260.h> | 19 | #include <asm/arch/at91sam9260.h> |
| 19 | #include <asm/arch/at91_pmc.h> | 20 | #include <asm/arch/at91_pmc.h> |
| 20 | #include <asm/arch/at91_rstc.h> | 21 | #include <asm/arch/at91_rstc.h> |
| 22 | #include <asm/arch/at91_shdwc.h> | ||
| 21 | 23 | ||
| 22 | #include "generic.h" | 24 | #include "generic.h" |
| 23 | #include "clock.h" | 25 | #include "clock.h" |
| @@ -267,6 +269,11 @@ static void at91sam9260_reset(void) | |||
| 267 | at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); | 269 | at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); |
| 268 | } | 270 | } |
| 269 | 271 | ||
| 272 | static void at91sam9260_poweroff(void) | ||
| 273 | { | ||
| 274 | at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); | ||
| 275 | } | ||
| 276 | |||
| 270 | 277 | ||
| 271 | /* -------------------------------------------------------------------- | 278 | /* -------------------------------------------------------------------- |
| 272 | * AT91SAM9260 processor initialization | 279 | * AT91SAM9260 processor initialization |
| @@ -304,6 +311,7 @@ void __init at91sam9260_initialize(unsigned long main_clock) | |||
| 304 | iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc)); | 311 | iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc)); |
| 305 | 312 | ||
| 306 | at91_arch_reset = at91sam9260_reset; | 313 | at91_arch_reset = at91sam9260_reset; |
| 314 | pm_power_off = at91sam9260_poweroff; | ||
| 307 | at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) | 315 | at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) |
| 308 | | (1 << AT91SAM9260_ID_IRQ2); | 316 | | (1 << AT91SAM9260_ID_IRQ2); |
| 309 | 317 | ||
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index 105f8403860b..393a32aefce5 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c | |||
| @@ -19,8 +19,8 @@ | |||
| 19 | #include <asm/arch/board.h> | 19 | #include <asm/arch/board.h> |
| 20 | #include <asm/arch/gpio.h> | 20 | #include <asm/arch/gpio.h> |
| 21 | #include <asm/arch/at91sam9260.h> | 21 | #include <asm/arch/at91sam9260.h> |
| 22 | #include <asm/arch/at91sam926x_mc.h> | ||
| 23 | #include <asm/arch/at91sam9260_matrix.h> | 22 | #include <asm/arch/at91sam9260_matrix.h> |
| 23 | #include <asm/arch/at91sam9_smc.h> | ||
| 24 | 24 | ||
| 25 | #include "generic.h" | 25 | #include "generic.h" |
| 26 | 26 | ||
| @@ -288,10 +288,15 @@ static struct at91_nand_data nand_data; | |||
| 288 | #define NAND_BASE AT91_CHIPSELECT_3 | 288 | #define NAND_BASE AT91_CHIPSELECT_3 |
| 289 | 289 | ||
| 290 | static struct resource nand_resources[] = { | 290 | static struct resource nand_resources[] = { |
| 291 | { | 291 | [0] = { |
| 292 | .start = NAND_BASE, | 292 | .start = NAND_BASE, |
| 293 | .end = NAND_BASE + SZ_256M - 1, | 293 | .end = NAND_BASE + SZ_256M - 1, |
| 294 | .flags = IORESOURCE_MEM, | 294 | .flags = IORESOURCE_MEM, |
| 295 | }, | ||
| 296 | [1] = { | ||
| 297 | .start = AT91_BASE_SYS + AT91_ECC, | ||
| 298 | .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1, | ||
| 299 | .flags = IORESOURCE_MEM, | ||
| 295 | } | 300 | } |
| 296 | }; | 301 | }; |
| 297 | 302 | ||
| @@ -540,6 +545,90 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) | |||
| 540 | 545 | ||
| 541 | 546 | ||
| 542 | /* -------------------------------------------------------------------- | 547 | /* -------------------------------------------------------------------- |
| 548 | * Timer/Counter blocks | ||
| 549 | * -------------------------------------------------------------------- */ | ||
| 550 | |||
| 551 | #ifdef CONFIG_ATMEL_TCLIB | ||
| 552 | |||
| 553 | static struct resource tcb0_resources[] = { | ||
| 554 | [0] = { | ||
| 555 | .start = AT91SAM9260_BASE_TCB0, | ||
| 556 | .end = AT91SAM9260_BASE_TCB0 + SZ_16K - 1, | ||
| 557 | .flags = IORESOURCE_MEM, | ||
| 558 | }, | ||
| 559 | [1] = { | ||
| 560 | .start = AT91SAM9260_ID_TC0, | ||
| 561 | .end = AT91SAM9260_ID_TC0, | ||
| 562 | .flags = IORESOURCE_IRQ, | ||
| 563 | }, | ||
| 564 | [2] = { | ||
| 565 | .start = AT91SAM9260_ID_TC1, | ||
| 566 | .end = AT91SAM9260_ID_TC1, | ||
| 567 | .flags = IORESOURCE_IRQ, | ||
| 568 | }, | ||
| 569 | [3] = { | ||
| 570 | .start = AT91SAM9260_ID_TC2, | ||
| 571 | .end = AT91SAM9260_ID_TC2, | ||
| 572 | .flags = IORESOURCE_IRQ, | ||
| 573 | }, | ||
| 574 | }; | ||
| 575 | |||
| 576 | static struct platform_device at91sam9260_tcb0_device = { | ||
| 577 | .name = "atmel_tcb", | ||
| 578 | .id = 0, | ||
| 579 | .resource = tcb0_resources, | ||
| 580 | .num_resources = ARRAY_SIZE(tcb0_resources), | ||
| 581 | }; | ||
| 582 | |||
| 583 | static struct resource tcb1_resources[] = { | ||
| 584 | [0] = { | ||
| 585 | .start = AT91SAM9260_BASE_TCB1, | ||
| 586 | .end = AT91SAM9260_BASE_TCB1 + SZ_16K - 1, | ||
| 587 | .flags = IORESOURCE_MEM, | ||
| 588 | }, | ||
| 589 | [1] = { | ||
| 590 | .start = AT91SAM9260_ID_TC3, | ||
| 591 | .end = AT91SAM9260_ID_TC3, | ||
| 592 | .flags = IORESOURCE_IRQ, | ||
| 593 | }, | ||
| 594 | [2] = { | ||
| 595 | .start = AT91SAM9260_ID_TC4, | ||
| 596 | .end = AT91SAM9260_ID_TC4, | ||
| 597 | .flags = IORESOURCE_IRQ, | ||
| 598 | }, | ||
| 599 | [3] = { | ||
| 600 | .start = AT91SAM9260_ID_TC5, | ||
| 601 | .end = AT91SAM9260_ID_TC5, | ||
| 602 | .flags = IORESOURCE_IRQ, | ||
| 603 | }, | ||
| 604 | }; | ||
| 605 | |||
| 606 | static struct platform_device at91sam9260_tcb1_device = { | ||
| 607 | .name = "atmel_tcb", | ||
| 608 | .id = 1, | ||
| 609 | .resource = tcb1_resources, | ||
| 610 | .num_resources = ARRAY_SIZE(tcb1_resources), | ||
| 611 | }; | ||
| 612 | |||
| 613 | static void __init at91_add_device_tc(void) | ||
| 614 | { | ||
| 615 | /* this chip has a separate clock and irq for each TC channel */ | ||
| 616 | at91_clock_associate("tc0_clk", &at91sam9260_tcb0_device.dev, "t0_clk"); | ||
| 617 | at91_clock_associate("tc1_clk", &at91sam9260_tcb0_device.dev, "t1_clk"); | ||
| 618 | at91_clock_associate("tc2_clk", &at91sam9260_tcb0_device.dev, "t2_clk"); | ||
| 619 | platform_device_register(&at91sam9260_tcb0_device); | ||
| 620 | |||
| 621 | at91_clock_associate("tc3_clk", &at91sam9260_tcb1_device.dev, "t0_clk"); | ||
| 622 | at91_clock_associate("tc4_clk", &at91sam9260_tcb1_device.dev, "t1_clk"); | ||
| 623 | at91_clock_associate("tc5_clk", &at91sam9260_tcb1_device.dev, "t2_clk"); | ||
| 624 | platform_device_register(&at91sam9260_tcb1_device); | ||
| 625 | } | ||
| 626 | #else | ||
| 627 | static void __init at91_add_device_tc(void) { } | ||
| 628 | #endif | ||
| 629 | |||
| 630 | |||
| 631 | /* -------------------------------------------------------------------- | ||
| 543 | * RTT | 632 | * RTT |
| 544 | * -------------------------------------------------------------------- */ | 633 | * -------------------------------------------------------------------- */ |
| 545 | 634 | ||
| @@ -553,7 +642,7 @@ static struct resource rtt_resources[] = { | |||
| 553 | 642 | ||
| 554 | static struct platform_device at91sam9260_rtt_device = { | 643 | static struct platform_device at91sam9260_rtt_device = { |
| 555 | .name = "at91_rtt", | 644 | .name = "at91_rtt", |
| 556 | .id = -1, | 645 | .id = 0, |
| 557 | .resource = rtt_resources, | 646 | .resource = rtt_resources, |
| 558 | .num_resources = ARRAY_SIZE(rtt_resources), | 647 | .num_resources = ARRAY_SIZE(rtt_resources), |
| 559 | }; | 648 | }; |
| @@ -962,64 +1051,9 @@ static inline void configure_usart5_pins(void) | |||
| 962 | at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */ | 1051 | at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */ |
| 963 | } | 1052 | } |
| 964 | 1053 | ||
| 965 | static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ | 1054 | static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ |
| 966 | struct platform_device *atmel_default_console_device; /* the serial console device */ | 1055 | struct platform_device *atmel_default_console_device; /* the serial console device */ |
| 967 | 1056 | ||
| 968 | void __init __deprecated at91_init_serial(struct at91_uart_config *config) | ||
| 969 | { | ||
| 970 | int i; | ||
| 971 | |||
| 972 | /* Fill in list of supported UARTs */ | ||
| 973 | for (i = 0; i < config->nr_tty; i++) { | ||
| 974 | switch (config->tty_map[i]) { | ||
| 975 | case 0: | ||
| 976 | configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS | ATMEL_UART_DSR | ATMEL_UART_DTR | ATMEL_UART_DCD | ATMEL_UART_RI); | ||
| 977 | at91_uarts[i] = &at91sam9260_uart0_device; | ||
| 978 | at91_clock_associate("usart0_clk", &at91sam9260_uart0_device.dev, "usart"); | ||
| 979 | break; | ||
| 980 | case 1: | ||
| 981 | configure_usart1_pins(ATMEL_UART_CTS | ATMEL_UART_RTS); | ||
| 982 | at91_uarts[i] = &at91sam9260_uart1_device; | ||
| 983 | at91_clock_associate("usart1_clk", &at91sam9260_uart1_device.dev, "usart"); | ||
| 984 | break; | ||
| 985 | case 2: | ||
| 986 | configure_usart2_pins(0); | ||
| 987 | at91_uarts[i] = &at91sam9260_uart2_device; | ||
| 988 | at91_clock_associate("usart2_clk", &at91sam9260_uart2_device.dev, "usart"); | ||
| 989 | break; | ||
| 990 | case 3: | ||
| 991 | configure_usart3_pins(0); | ||
| 992 | at91_uarts[i] = &at91sam9260_uart3_device; | ||
| 993 | at91_clock_associate("usart3_clk", &at91sam9260_uart3_device.dev, "usart"); | ||
| 994 | break; | ||
| 995 | case 4: | ||
| 996 | configure_usart4_pins(); | ||
| 997 | at91_uarts[i] = &at91sam9260_uart4_device; | ||
| 998 | at91_clock_associate("usart4_clk", &at91sam9260_uart4_device.dev, "usart"); | ||
| 999 | break; | ||
| 1000 | case 5: | ||
| 1001 | configure_usart5_pins(); | ||
| 1002 | at91_uarts[i] = &at91sam9260_uart5_device; | ||
| 1003 | at91_clock_associate("usart5_clk", &at91sam9260_uart5_device.dev, "usart"); | ||
| 1004 | break; | ||
| 1005 | case 6: | ||
| 1006 | configure_dbgu_pins(); | ||
| 1007 | at91_uarts[i] = &at91sam9260_dbgu_device; | ||
| 1008 | at91_clock_associate("mck", &at91sam9260_dbgu_device.dev, "usart"); | ||
| 1009 | break; | ||
| 1010 | default: | ||
| 1011 | continue; | ||
| 1012 | } | ||
| 1013 | at91_uarts[i]->id = i; /* update ID number to mapped ID */ | ||
| 1014 | } | ||
| 1015 | |||
| 1016 | /* Set serial console device */ | ||
| 1017 | if (config->console_tty < ATMEL_MAX_UART) | ||
| 1018 | atmel_default_console_device = at91_uarts[config->console_tty]; | ||
| 1019 | if (!atmel_default_console_device) | ||
| 1020 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 1021 | } | ||
| 1022 | |||
| 1023 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) | 1057 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) |
| 1024 | { | 1058 | { |
| 1025 | struct platform_device *pdev; | 1059 | struct platform_device *pdev; |
| @@ -1073,8 +1107,6 @@ void __init at91_set_serial_console(unsigned portnr) | |||
| 1073 | { | 1107 | { |
| 1074 | if (portnr < ATMEL_MAX_UART) | 1108 | if (portnr < ATMEL_MAX_UART) |
| 1075 | atmel_default_console_device = at91_uarts[portnr]; | 1109 | atmel_default_console_device = at91_uarts[portnr]; |
| 1076 | if (!atmel_default_console_device) | ||
| 1077 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 1078 | } | 1110 | } |
| 1079 | 1111 | ||
| 1080 | void __init at91_add_device_serial(void) | 1112 | void __init at91_add_device_serial(void) |
| @@ -1085,9 +1117,11 @@ void __init at91_add_device_serial(void) | |||
| 1085 | if (at91_uarts[i]) | 1117 | if (at91_uarts[i]) |
| 1086 | platform_device_register(at91_uarts[i]); | 1118 | platform_device_register(at91_uarts[i]); |
| 1087 | } | 1119 | } |
| 1120 | |||
| 1121 | if (!atmel_default_console_device) | ||
| 1122 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 1088 | } | 1123 | } |
| 1089 | #else | 1124 | #else |
| 1090 | void __init __deprecated at91_init_serial(struct at91_uart_config *config) {} | ||
| 1091 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} | 1125 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} |
| 1092 | void __init at91_set_serial_console(unsigned portnr) {} | 1126 | void __init at91_set_serial_console(unsigned portnr) {} |
| 1093 | void __init at91_add_device_serial(void) {} | 1127 | void __init at91_add_device_serial(void) {} |
| @@ -1103,6 +1137,7 @@ static int __init at91_add_standard_devices(void) | |||
| 1103 | { | 1137 | { |
| 1104 | at91_add_device_rtt(); | 1138 | at91_add_device_rtt(); |
| 1105 | at91_add_device_watchdog(); | 1139 | at91_add_device_watchdog(); |
| 1140 | at91_add_device_tc(); | ||
| 1106 | return 0; | 1141 | return 0; |
| 1107 | } | 1142 | } |
| 1108 | 1143 | ||
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 90b87e1877d9..35bf6fd52516 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c | |||
| @@ -11,12 +11,14 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
| 14 | #include <linux/pm.h> | ||
| 14 | 15 | ||
| 15 | #include <asm/mach/arch.h> | 16 | #include <asm/mach/arch.h> |
| 16 | #include <asm/mach/map.h> | 17 | #include <asm/mach/map.h> |
| 17 | #include <asm/arch/at91sam9261.h> | 18 | #include <asm/arch/at91sam9261.h> |
| 18 | #include <asm/arch/at91_pmc.h> | 19 | #include <asm/arch/at91_pmc.h> |
| 19 | #include <asm/arch/at91_rstc.h> | 20 | #include <asm/arch/at91_rstc.h> |
| 21 | #include <asm/arch/at91_shdwc.h> | ||
| 20 | 22 | ||
| 21 | #include "generic.h" | 23 | #include "generic.h" |
| 22 | #include "clock.h" | 24 | #include "clock.h" |
| @@ -245,6 +247,11 @@ static void at91sam9261_reset(void) | |||
| 245 | at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); | 247 | at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); |
| 246 | } | 248 | } |
| 247 | 249 | ||
| 250 | static void at91sam9261_poweroff(void) | ||
| 251 | { | ||
| 252 | at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); | ||
| 253 | } | ||
| 254 | |||
| 248 | 255 | ||
| 249 | /* -------------------------------------------------------------------- | 256 | /* -------------------------------------------------------------------- |
| 250 | * AT91SAM9261 processor initialization | 257 | * AT91SAM9261 processor initialization |
| @@ -256,6 +263,7 @@ void __init at91sam9261_initialize(unsigned long main_clock) | |||
| 256 | iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc)); | 263 | iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc)); |
| 257 | 264 | ||
| 258 | at91_arch_reset = at91sam9261_reset; | 265 | at91_arch_reset = at91sam9261_reset; |
| 266 | pm_power_off = at91sam9261_poweroff; | ||
| 259 | at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) | 267 | at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) |
| 260 | | (1 << AT91SAM9261_ID_IRQ2); | 268 | | (1 << AT91SAM9261_ID_IRQ2); |
| 261 | 269 | ||
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index 245641263fce..37cd547855b1 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c | |||
| @@ -24,7 +24,7 @@ | |||
| 24 | #include <asm/arch/gpio.h> | 24 | #include <asm/arch/gpio.h> |
| 25 | #include <asm/arch/at91sam9261.h> | 25 | #include <asm/arch/at91sam9261.h> |
| 26 | #include <asm/arch/at91sam9261_matrix.h> | 26 | #include <asm/arch/at91sam9261_matrix.h> |
| 27 | #include <asm/arch/at91sam926x_mc.h> | 27 | #include <asm/arch/at91sam9_smc.h> |
| 28 | 28 | ||
| 29 | #include "generic.h" | 29 | #include "generic.h" |
| 30 | 30 | ||
| @@ -548,6 +548,55 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} | |||
| 548 | 548 | ||
| 549 | 549 | ||
| 550 | /* -------------------------------------------------------------------- | 550 | /* -------------------------------------------------------------------- |
| 551 | * Timer/Counter block | ||
| 552 | * -------------------------------------------------------------------- */ | ||
| 553 | |||
| 554 | #ifdef CONFIG_ATMEL_TCLIB | ||
| 555 | |||
| 556 | static struct resource tcb_resources[] = { | ||
| 557 | [0] = { | ||
| 558 | .start = AT91SAM9261_BASE_TCB0, | ||
| 559 | .end = AT91SAM9261_BASE_TCB0 + SZ_16K - 1, | ||
| 560 | .flags = IORESOURCE_MEM, | ||
| 561 | }, | ||
| 562 | [1] = { | ||
| 563 | .start = AT91SAM9261_ID_TC0, | ||
| 564 | .end = AT91SAM9261_ID_TC0, | ||
| 565 | .flags = IORESOURCE_IRQ, | ||
| 566 | }, | ||
| 567 | [2] = { | ||
| 568 | .start = AT91SAM9261_ID_TC1, | ||
| 569 | .end = AT91SAM9261_ID_TC1, | ||
| 570 | .flags = IORESOURCE_IRQ, | ||
| 571 | }, | ||
| 572 | [3] = { | ||
| 573 | .start = AT91SAM9261_ID_TC2, | ||
| 574 | .end = AT91SAM9261_ID_TC2, | ||
| 575 | .flags = IORESOURCE_IRQ, | ||
| 576 | }, | ||
| 577 | }; | ||
| 578 | |||
| 579 | static struct platform_device at91sam9261_tcb_device = { | ||
| 580 | .name = "atmel_tcb", | ||
| 581 | .id = 0, | ||
| 582 | .resource = tcb_resources, | ||
| 583 | .num_resources = ARRAY_SIZE(tcb_resources), | ||
| 584 | }; | ||
| 585 | |||
| 586 | static void __init at91_add_device_tc(void) | ||
| 587 | { | ||
| 588 | /* this chip has a separate clock and irq for each TC channel */ | ||
| 589 | at91_clock_associate("tc0_clk", &at91sam9261_tcb_device.dev, "t0_clk"); | ||
| 590 | at91_clock_associate("tc1_clk", &at91sam9261_tcb_device.dev, "t1_clk"); | ||
| 591 | at91_clock_associate("tc2_clk", &at91sam9261_tcb_device.dev, "t2_clk"); | ||
| 592 | platform_device_register(&at91sam9261_tcb_device); | ||
| 593 | } | ||
| 594 | #else | ||
| 595 | static void __init at91_add_device_tc(void) { } | ||
| 596 | #endif | ||
| 597 | |||
| 598 | |||
| 599 | /* -------------------------------------------------------------------- | ||
| 551 | * RTT | 600 | * RTT |
| 552 | * -------------------------------------------------------------------- */ | 601 | * -------------------------------------------------------------------- */ |
| 553 | 602 | ||
| @@ -561,7 +610,7 @@ static struct resource rtt_resources[] = { | |||
| 561 | 610 | ||
| 562 | static struct platform_device at91sam9261_rtt_device = { | 611 | static struct platform_device at91sam9261_rtt_device = { |
| 563 | .name = "at91_rtt", | 612 | .name = "at91_rtt", |
| 564 | .id = -1, | 613 | .id = 0, |
| 565 | .resource = rtt_resources, | 614 | .resource = rtt_resources, |
| 566 | .num_resources = ARRAY_SIZE(rtt_resources), | 615 | .num_resources = ARRAY_SIZE(rtt_resources), |
| 567 | }; | 616 | }; |
| @@ -938,49 +987,9 @@ static inline void configure_usart2_pins(unsigned pins) | |||
| 938 | at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */ | 987 | at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */ |
| 939 | } | 988 | } |
| 940 | 989 | ||
| 941 | static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ | 990 | static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ |
| 942 | struct platform_device *atmel_default_console_device; /* the serial console device */ | 991 | struct platform_device *atmel_default_console_device; /* the serial console device */ |
| 943 | 992 | ||
| 944 | void __init __deprecated at91_init_serial(struct at91_uart_config *config) | ||
| 945 | { | ||
| 946 | int i; | ||
| 947 | |||
| 948 | /* Fill in list of supported UARTs */ | ||
| 949 | for (i = 0; i < config->nr_tty; i++) { | ||
| 950 | switch (config->tty_map[i]) { | ||
| 951 | case 0: | ||
| 952 | configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS); | ||
| 953 | at91_uarts[i] = &at91sam9261_uart0_device; | ||
| 954 | at91_clock_associate("usart0_clk", &at91sam9261_uart0_device.dev, "usart"); | ||
| 955 | break; | ||
| 956 | case 1: | ||
| 957 | configure_usart1_pins(0); | ||
| 958 | at91_uarts[i] = &at91sam9261_uart1_device; | ||
| 959 | at91_clock_associate("usart1_clk", &at91sam9261_uart1_device.dev, "usart"); | ||
| 960 | break; | ||
| 961 | case 2: | ||
| 962 | configure_usart2_pins(0); | ||
| 963 | at91_uarts[i] = &at91sam9261_uart2_device; | ||
| 964 | at91_clock_associate("usart2_clk", &at91sam9261_uart2_device.dev, "usart"); | ||
| 965 | break; | ||
| 966 | case 3: | ||
| 967 | configure_dbgu_pins(); | ||
| 968 | at91_uarts[i] = &at91sam9261_dbgu_device; | ||
| 969 | at91_clock_associate("mck", &at91sam9261_dbgu_device.dev, "usart"); | ||
| 970 | break; | ||
| 971 | default: | ||
| 972 | continue; | ||
| 973 | } | ||
| 974 | at91_uarts[i]->id = i; /* update ID number to mapped ID */ | ||
| 975 | } | ||
| 976 | |||
| 977 | /* Set serial console device */ | ||
| 978 | if (config->console_tty < ATMEL_MAX_UART) | ||
| 979 | atmel_default_console_device = at91_uarts[config->console_tty]; | ||
| 980 | if (!atmel_default_console_device) | ||
| 981 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 982 | } | ||
| 983 | |||
| 984 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) | 993 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) |
| 985 | { | 994 | { |
| 986 | struct platform_device *pdev; | 995 | struct platform_device *pdev; |
| @@ -1019,8 +1028,6 @@ void __init at91_set_serial_console(unsigned portnr) | |||
| 1019 | { | 1028 | { |
| 1020 | if (portnr < ATMEL_MAX_UART) | 1029 | if (portnr < ATMEL_MAX_UART) |
| 1021 | atmel_default_console_device = at91_uarts[portnr]; | 1030 | atmel_default_console_device = at91_uarts[portnr]; |
| 1022 | if (!atmel_default_console_device) | ||
| 1023 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 1024 | } | 1031 | } |
| 1025 | 1032 | ||
| 1026 | void __init at91_add_device_serial(void) | 1033 | void __init at91_add_device_serial(void) |
| @@ -1031,9 +1038,11 @@ void __init at91_add_device_serial(void) | |||
| 1031 | if (at91_uarts[i]) | 1038 | if (at91_uarts[i]) |
| 1032 | platform_device_register(at91_uarts[i]); | 1039 | platform_device_register(at91_uarts[i]); |
| 1033 | } | 1040 | } |
| 1041 | |||
| 1042 | if (!atmel_default_console_device) | ||
| 1043 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 1034 | } | 1044 | } |
| 1035 | #else | 1045 | #else |
| 1036 | void __init __deprecated at91_init_serial(struct at91_uart_config *config) {} | ||
| 1037 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} | 1046 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} |
| 1038 | void __init at91_set_serial_console(unsigned portnr) {} | 1047 | void __init at91_set_serial_console(unsigned portnr) {} |
| 1039 | void __init at91_add_device_serial(void) {} | 1048 | void __init at91_add_device_serial(void) {} |
| @@ -1050,6 +1059,7 @@ static int __init at91_add_standard_devices(void) | |||
| 1050 | { | 1059 | { |
| 1051 | at91_add_device_rtt(); | 1060 | at91_add_device_rtt(); |
| 1052 | at91_add_device_watchdog(); | 1061 | at91_add_device_watchdog(); |
| 1062 | at91_add_device_tc(); | ||
| 1053 | return 0; | 1063 | return 0; |
| 1054 | } | 1064 | } |
| 1055 | 1065 | ||
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index a53ba0f74351..052074a9f2d3 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c | |||
| @@ -11,12 +11,14 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
| 14 | #include <linux/pm.h> | ||
| 14 | 15 | ||
| 15 | #include <asm/mach/arch.h> | 16 | #include <asm/mach/arch.h> |
| 16 | #include <asm/mach/map.h> | 17 | #include <asm/mach/map.h> |
| 17 | #include <asm/arch/at91sam9263.h> | 18 | #include <asm/arch/at91sam9263.h> |
| 18 | #include <asm/arch/at91_pmc.h> | 19 | #include <asm/arch/at91_pmc.h> |
| 19 | #include <asm/arch/at91_rstc.h> | 20 | #include <asm/arch/at91_rstc.h> |
| 21 | #include <asm/arch/at91_shdwc.h> | ||
| 20 | 22 | ||
| 21 | #include "generic.h" | 23 | #include "generic.h" |
| 22 | #include "clock.h" | 24 | #include "clock.h" |
| @@ -271,6 +273,11 @@ static void at91sam9263_reset(void) | |||
| 271 | at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); | 273 | at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); |
| 272 | } | 274 | } |
| 273 | 275 | ||
| 276 | static void at91sam9263_poweroff(void) | ||
| 277 | { | ||
| 278 | at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); | ||
| 279 | } | ||
| 280 | |||
| 274 | 281 | ||
| 275 | /* -------------------------------------------------------------------- | 282 | /* -------------------------------------------------------------------- |
| 276 | * AT91SAM9263 processor initialization | 283 | * AT91SAM9263 processor initialization |
| @@ -282,6 +289,7 @@ void __init at91sam9263_initialize(unsigned long main_clock) | |||
| 282 | iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc)); | 289 | iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc)); |
| 283 | 290 | ||
| 284 | at91_arch_reset = at91sam9263_reset; | 291 | at91_arch_reset = at91sam9263_reset; |
| 292 | pm_power_off = at91sam9263_poweroff; | ||
| 285 | at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1); | 293 | at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1); |
| 286 | 294 | ||
| 287 | /* Init clock subsystem */ | 295 | /* Init clock subsystem */ |
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 0b12e1adcc8e..719667e25c98 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c | |||
| @@ -22,8 +22,8 @@ | |||
| 22 | #include <asm/arch/board.h> | 22 | #include <asm/arch/board.h> |
| 23 | #include <asm/arch/gpio.h> | 23 | #include <asm/arch/gpio.h> |
| 24 | #include <asm/arch/at91sam9263.h> | 24 | #include <asm/arch/at91sam9263.h> |
| 25 | #include <asm/arch/at91sam926x_mc.h> | ||
| 26 | #include <asm/arch/at91sam9263_matrix.h> | 25 | #include <asm/arch/at91sam9263_matrix.h> |
| 26 | #include <asm/arch/at91sam9_smc.h> | ||
| 27 | 27 | ||
| 28 | #include "generic.h" | 28 | #include "generic.h" |
| 29 | 29 | ||
| @@ -308,7 +308,7 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) | |||
| 308 | } | 308 | } |
| 309 | 309 | ||
| 310 | mmc0_data = *data; | 310 | mmc0_data = *data; |
| 311 | at91_clock_associate("mci0_clk", &at91sam9263_mmc1_device.dev, "mci_clk"); | 311 | at91_clock_associate("mci0_clk", &at91sam9263_mmc0_device.dev, "mci_clk"); |
| 312 | platform_device_register(&at91sam9263_mmc0_device); | 312 | platform_device_register(&at91sam9263_mmc0_device); |
| 313 | } else { /* MCI1 */ | 313 | } else { /* MCI1 */ |
| 314 | /* CLK */ | 314 | /* CLK */ |
| @@ -358,10 +358,15 @@ static struct at91_nand_data nand_data; | |||
| 358 | #define NAND_BASE AT91_CHIPSELECT_3 | 358 | #define NAND_BASE AT91_CHIPSELECT_3 |
| 359 | 359 | ||
| 360 | static struct resource nand_resources[] = { | 360 | static struct resource nand_resources[] = { |
| 361 | { | 361 | [0] = { |
| 362 | .start = NAND_BASE, | 362 | .start = NAND_BASE, |
| 363 | .end = NAND_BASE + SZ_256M - 1, | 363 | .end = NAND_BASE + SZ_256M - 1, |
| 364 | .flags = IORESOURCE_MEM, | 364 | .flags = IORESOURCE_MEM, |
| 365 | }, | ||
| 366 | [1] = { | ||
| 367 | .start = AT91_BASE_SYS + AT91_ECC0, | ||
| 368 | .end = AT91_BASE_SYS + AT91_ECC0 + SZ_512 - 1, | ||
| 369 | .flags = IORESOURCE_MEM, | ||
| 365 | } | 370 | } |
| 366 | }; | 371 | }; |
| 367 | 372 | ||
| @@ -783,6 +788,43 @@ void __init at91_add_device_isi(void) {} | |||
| 783 | 788 | ||
| 784 | 789 | ||
| 785 | /* -------------------------------------------------------------------- | 790 | /* -------------------------------------------------------------------- |
| 791 | * Timer/Counter block | ||
| 792 | * -------------------------------------------------------------------- */ | ||
| 793 | |||
| 794 | #ifdef CONFIG_ATMEL_TCLIB | ||
| 795 | |||
| 796 | static struct resource tcb_resources[] = { | ||
| 797 | [0] = { | ||
| 798 | .start = AT91SAM9263_BASE_TCB0, | ||
| 799 | .end = AT91SAM9263_BASE_TCB0 + SZ_16K - 1, | ||
| 800 | .flags = IORESOURCE_MEM, | ||
| 801 | }, | ||
| 802 | [1] = { | ||
| 803 | .start = AT91SAM9263_ID_TCB, | ||
| 804 | .end = AT91SAM9263_ID_TCB, | ||
| 805 | .flags = IORESOURCE_IRQ, | ||
| 806 | }, | ||
| 807 | }; | ||
| 808 | |||
| 809 | static struct platform_device at91sam9263_tcb_device = { | ||
| 810 | .name = "atmel_tcb", | ||
| 811 | .id = 0, | ||
| 812 | .resource = tcb_resources, | ||
| 813 | .num_resources = ARRAY_SIZE(tcb_resources), | ||
| 814 | }; | ||
| 815 | |||
| 816 | static void __init at91_add_device_tc(void) | ||
| 817 | { | ||
| 818 | /* this chip has one clock and irq for all three TC channels */ | ||
| 819 | at91_clock_associate("tcb_clk", &at91sam9263_tcb_device.dev, "t0_clk"); | ||
| 820 | platform_device_register(&at91sam9263_tcb_device); | ||
| 821 | } | ||
| 822 | #else | ||
| 823 | static void __init at91_add_device_tc(void) { } | ||
| 824 | #endif | ||
| 825 | |||
| 826 | |||
| 827 | /* -------------------------------------------------------------------- | ||
| 786 | * RTT | 828 | * RTT |
| 787 | * -------------------------------------------------------------------- */ | 829 | * -------------------------------------------------------------------- */ |
| 788 | 830 | ||
| @@ -933,9 +975,6 @@ static inline void configure_ssc1_pins(unsigned pins) | |||
| 933 | } | 975 | } |
| 934 | 976 | ||
| 935 | /* | 977 | /* |
| 936 | * Return the device node so that board init code can use it as the | ||
| 937 | * parent for the device node reflecting how it's used on this board. | ||
| 938 | * | ||
| 939 | * SSC controllers are accessed through library code, instead of any | 978 | * SSC controllers are accessed through library code, instead of any |
| 940 | * kind of all-singing/all-dancing driver. For example one could be | 979 | * kind of all-singing/all-dancing driver. For example one could be |
| 941 | * used by a particular I2S audio codec's driver, while another one | 980 | * used by a particular I2S audio codec's driver, while another one |
| @@ -1146,49 +1185,9 @@ static inline void configure_usart2_pins(unsigned pins) | |||
| 1146 | at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */ | 1185 | at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */ |
| 1147 | } | 1186 | } |
| 1148 | 1187 | ||
| 1149 | static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ | 1188 | static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ |
| 1150 | struct platform_device *atmel_default_console_device; /* the serial console device */ | 1189 | struct platform_device *atmel_default_console_device; /* the serial console device */ |
| 1151 | 1190 | ||
| 1152 | void __init __deprecated at91_init_serial(struct at91_uart_config *config) | ||
| 1153 | { | ||
| 1154 | int i; | ||
| 1155 | |||
| 1156 | /* Fill in list of supported UARTs */ | ||
| 1157 | for (i = 0; i < config->nr_tty; i++) { | ||
| 1158 | switch (config->tty_map[i]) { | ||
| 1159 | case 0: | ||
| 1160 | configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS); | ||
| 1161 | at91_uarts[i] = &at91sam9263_uart0_device; | ||
| 1162 | at91_clock_associate("usart0_clk", &at91sam9263_uart0_device.dev, "usart"); | ||
| 1163 | break; | ||
| 1164 | case 1: | ||
| 1165 | configure_usart1_pins(ATMEL_UART_CTS | ATMEL_UART_RTS); | ||
| 1166 | at91_uarts[i] = &at91sam9263_uart1_device; | ||
| 1167 | at91_clock_associate("usart1_clk", &at91sam9263_uart1_device.dev, "usart"); | ||
| 1168 | break; | ||
| 1169 | case 2: | ||
| 1170 | configure_usart2_pins(ATMEL_UART_CTS | ATMEL_UART_RTS); | ||
| 1171 | at91_uarts[i] = &at91sam9263_uart2_device; | ||
| 1172 | at91_clock_associate("usart2_clk", &at91sam9263_uart2_device.dev, "usart"); | ||
| 1173 | break; | ||
| 1174 | case 3: | ||
| 1175 | configure_dbgu_pins(); | ||
| 1176 | at91_uarts[i] = &at91sam9263_dbgu_device; | ||
| 1177 | at91_clock_associate("mck", &at91sam9263_dbgu_device.dev, "usart"); | ||
| 1178 | break; | ||
| 1179 | default: | ||
| 1180 | continue; | ||
| 1181 | } | ||
| 1182 | at91_uarts[i]->id = i; /* update ID number to mapped ID */ | ||
| 1183 | } | ||
| 1184 | |||
| 1185 | /* Set serial console device */ | ||
| 1186 | if (config->console_tty < ATMEL_MAX_UART) | ||
| 1187 | atmel_default_console_device = at91_uarts[config->console_tty]; | ||
| 1188 | if (!atmel_default_console_device) | ||
| 1189 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 1190 | } | ||
| 1191 | |||
| 1192 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) | 1191 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) |
| 1193 | { | 1192 | { |
| 1194 | struct platform_device *pdev; | 1193 | struct platform_device *pdev; |
| @@ -1227,8 +1226,6 @@ void __init at91_set_serial_console(unsigned portnr) | |||
| 1227 | { | 1226 | { |
| 1228 | if (portnr < ATMEL_MAX_UART) | 1227 | if (portnr < ATMEL_MAX_UART) |
| 1229 | atmel_default_console_device = at91_uarts[portnr]; | 1228 | atmel_default_console_device = at91_uarts[portnr]; |
| 1230 | if (!atmel_default_console_device) | ||
| 1231 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 1232 | } | 1229 | } |
| 1233 | 1230 | ||
| 1234 | void __init at91_add_device_serial(void) | 1231 | void __init at91_add_device_serial(void) |
| @@ -1239,9 +1236,11 @@ void __init at91_add_device_serial(void) | |||
| 1239 | if (at91_uarts[i]) | 1236 | if (at91_uarts[i]) |
| 1240 | platform_device_register(at91_uarts[i]); | 1237 | platform_device_register(at91_uarts[i]); |
| 1241 | } | 1238 | } |
| 1239 | |||
| 1240 | if (!atmel_default_console_device) | ||
| 1241 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 1242 | } | 1242 | } |
| 1243 | #else | 1243 | #else |
| 1244 | void __init at91_init_serial(struct at91_uart_config *config) {} | ||
| 1245 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} | 1244 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} |
| 1246 | void __init at91_set_serial_console(unsigned portnr) {} | 1245 | void __init at91_set_serial_console(unsigned portnr) {} |
| 1247 | void __init at91_add_device_serial(void) {} | 1246 | void __init at91_add_device_serial(void) {} |
| @@ -1257,6 +1256,7 @@ static int __init at91_add_standard_devices(void) | |||
| 1257 | { | 1256 | { |
| 1258 | at91_add_device_rtt(); | 1257 | at91_add_device_rtt(); |
| 1259 | at91_add_device_watchdog(); | 1258 | at91_add_device_watchdog(); |
| 1259 | at91_add_device_tc(); | ||
| 1260 | return 0; | 1260 | return 0; |
| 1261 | } | 1261 | } |
| 1262 | 1262 | ||
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index e38d23770992..5cecbd7de6a6 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c | |||
| @@ -1,23 +1,20 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-at91/at91sam926x_time.c | 2 | * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France | 4 | * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France |
| 5 | * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France | 5 | * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France |
| 6 | * Converted to ClockSource/ClockEvents by David Brownell. | ||
| 6 | * | 7 | * |
| 7 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as | 9 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. | 10 | * published by the Free Software Foundation. |
| 10 | */ | 11 | */ |
| 11 | |||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/interrupt.h> | 12 | #include <linux/interrupt.h> |
| 14 | #include <linux/irq.h> | 13 | #include <linux/irq.h> |
| 15 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
| 16 | #include <linux/sched.h> | 15 | #include <linux/clk.h> |
| 17 | #include <linux/time.h> | 16 | #include <linux/clockchips.h> |
| 18 | 17 | ||
| 19 | #include <asm/hardware.h> | ||
| 20 | #include <asm/io.h> | ||
| 21 | #include <asm/mach/time.h> | 18 | #include <asm/mach/time.h> |
| 22 | 19 | ||
| 23 | #include <asm/arch/at91_pit.h> | 20 | #include <asm/arch/at91_pit.h> |
| @@ -26,85 +23,167 @@ | |||
| 26 | #define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) | 23 | #define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) |
| 27 | #define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) | 24 | #define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) |
| 28 | 25 | ||
| 26 | static u32 pit_cycle; /* write-once */ | ||
| 27 | static u32 pit_cnt; /* access only w/system irq blocked */ | ||
| 28 | |||
| 29 | |||
| 29 | /* | 30 | /* |
| 30 | * Returns number of microseconds since last timer interrupt. Note that interrupts | 31 | * Clocksource: just a monotonic counter of MCK/16 cycles. |
| 31 | * will have been disabled by do_gettimeofday() | 32 | * We don't care whether or not PIT irqs are enabled. |
| 32 | * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy. | ||
| 33 | */ | 33 | */ |
| 34 | static unsigned long at91sam926x_gettimeoffset(void) | 34 | static cycle_t read_pit_clk(void) |
| 35 | { | 35 | { |
| 36 | unsigned long elapsed; | 36 | unsigned long flags; |
| 37 | unsigned long t = at91_sys_read(AT91_PIT_PIIR); | 37 | u32 elapsed; |
| 38 | u32 t; | ||
| 39 | |||
| 40 | raw_local_irq_save(flags); | ||
| 41 | elapsed = pit_cnt; | ||
| 42 | t = at91_sys_read(AT91_PIT_PIIR); | ||
| 43 | raw_local_irq_restore(flags); | ||
| 44 | |||
| 45 | elapsed += PIT_PICNT(t) * pit_cycle; | ||
| 46 | elapsed += PIT_CPIV(t); | ||
| 47 | return elapsed; | ||
| 48 | } | ||
| 49 | |||
| 50 | static struct clocksource pit_clk = { | ||
| 51 | .name = "pit", | ||
| 52 | .rating = 175, | ||
| 53 | .read = read_pit_clk, | ||
| 54 | .shift = 20, | ||
| 55 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
| 56 | }; | ||
| 38 | 57 | ||
| 39 | elapsed = (PIT_PICNT(t) * LATCH) + PIT_CPIV(t); /* hardware clock cycles */ | ||
| 40 | 58 | ||
| 41 | return (unsigned long)(elapsed * jiffies_to_usecs(1)) / LATCH; | 59 | /* |
| 60 | * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16) | ||
| 61 | */ | ||
| 62 | static void | ||
| 63 | pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) | ||
| 64 | { | ||
| 65 | unsigned long flags; | ||
| 66 | |||
| 67 | switch (mode) { | ||
| 68 | case CLOCK_EVT_MODE_PERIODIC: | ||
| 69 | /* update clocksource counter, then enable the IRQ */ | ||
| 70 | raw_local_irq_save(flags); | ||
| 71 | pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); | ||
| 72 | at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN | ||
| 73 | | AT91_PIT_PITIEN); | ||
| 74 | raw_local_irq_restore(flags); | ||
| 75 | break; | ||
| 76 | case CLOCK_EVT_MODE_ONESHOT: | ||
| 77 | BUG(); | ||
| 78 | /* FALLTHROUGH */ | ||
| 79 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
| 80 | case CLOCK_EVT_MODE_UNUSED: | ||
| 81 | /* disable irq, leaving the clocksource active */ | ||
| 82 | at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); | ||
| 83 | break; | ||
| 84 | case CLOCK_EVT_MODE_RESUME: | ||
| 85 | break; | ||
| 86 | } | ||
| 42 | } | 87 | } |
| 43 | 88 | ||
| 89 | static struct clock_event_device pit_clkevt = { | ||
| 90 | .name = "pit", | ||
| 91 | .features = CLOCK_EVT_FEAT_PERIODIC, | ||
| 92 | .shift = 32, | ||
| 93 | .rating = 100, | ||
| 94 | .cpumask = CPU_MASK_CPU0, | ||
| 95 | .set_mode = pit_clkevt_mode, | ||
| 96 | }; | ||
| 97 | |||
| 98 | |||
| 44 | /* | 99 | /* |
| 45 | * IRQ handler for the timer. | 100 | * IRQ handler for the timer. |
| 46 | */ | 101 | */ |
| 47 | static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id) | 102 | static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id) |
| 48 | { | 103 | { |
| 49 | volatile long nr_ticks; | ||
| 50 | 104 | ||
| 51 | if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) { /* This is a shared interrupt */ | 105 | /* The PIT interrupt may be disabled, and is shared */ |
| 52 | /* Get number to ticks performed before interrupt and clear PIT interrupt */ | 106 | if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC) |
| 107 | && (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)) { | ||
| 108 | unsigned nr_ticks; | ||
| 109 | |||
| 110 | /* Get number of ticks performed before irq, and ack it */ | ||
| 53 | nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); | 111 | nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); |
| 54 | do { | 112 | do { |
| 55 | timer_tick(); | 113 | pit_cnt += pit_cycle; |
| 114 | pit_clkevt.event_handler(&pit_clkevt); | ||
| 56 | nr_ticks--; | 115 | nr_ticks--; |
| 57 | } while (nr_ticks); | 116 | } while (nr_ticks); |
| 58 | 117 | ||
| 59 | return IRQ_HANDLED; | 118 | return IRQ_HANDLED; |
| 60 | } else | 119 | } |
| 61 | return IRQ_NONE; /* not handled */ | 120 | |
| 121 | return IRQ_NONE; | ||
| 62 | } | 122 | } |
| 63 | 123 | ||
| 64 | static struct irqaction at91sam926x_timer_irq = { | 124 | static struct irqaction at91sam926x_pit_irq = { |
| 65 | .name = "at91_tick", | 125 | .name = "at91_tick", |
| 66 | .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | 126 | .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
| 67 | .handler = at91sam926x_timer_interrupt | 127 | .handler = at91sam926x_pit_interrupt |
| 68 | }; | 128 | }; |
| 69 | 129 | ||
| 70 | void at91sam926x_timer_reset(void) | 130 | static void at91sam926x_pit_reset(void) |
| 71 | { | 131 | { |
| 72 | /* Disable timer */ | 132 | /* Disable timer and irqs */ |
| 73 | at91_sys_write(AT91_PIT_MR, 0); | 133 | at91_sys_write(AT91_PIT_MR, 0); |
| 74 | 134 | ||
| 75 | /* Clear any pending interrupts */ | 135 | /* Clear any pending interrupts, wait for PIT to stop counting */ |
| 76 | (void) at91_sys_read(AT91_PIT_PIVR); | 136 | while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0) |
| 137 | cpu_relax(); | ||
| 77 | 138 | ||
| 78 | /* Set Period Interval timer and enable its interrupt */ | 139 | /* Start PIT but don't enable IRQ */ |
| 79 | at91_sys_write(AT91_PIT_MR, (LATCH & AT91_PIT_PIV) | AT91_PIT_PITIEN | AT91_PIT_PITEN); | 140 | at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); |
| 80 | } | 141 | } |
| 81 | 142 | ||
| 82 | /* | 143 | /* |
| 83 | * Set up timer interrupt. | 144 | * Set up both clocksource and clockevent support. |
| 84 | */ | 145 | */ |
| 85 | void __init at91sam926x_timer_init(void) | 146 | static void __init at91sam926x_pit_init(void) |
| 86 | { | 147 | { |
| 87 | /* Initialize and enable the timer */ | 148 | unsigned long pit_rate; |
| 88 | at91sam926x_timer_reset(); | 149 | unsigned bits; |
| 150 | |||
| 151 | /* | ||
| 152 | * Use our actual MCK to figure out how many MCK/16 ticks per | ||
| 153 | * 1/HZ period (instead of a compile-time constant LATCH). | ||
| 154 | */ | ||
| 155 | pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16; | ||
| 156 | pit_cycle = (pit_rate + HZ/2) / HZ; | ||
| 157 | WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0); | ||
| 89 | 158 | ||
| 90 | /* Make IRQs happen for the system timer. */ | 159 | /* Initialize and enable the timer */ |
| 91 | setup_irq(AT91_ID_SYS, &at91sam926x_timer_irq); | 160 | at91sam926x_pit_reset(); |
| 161 | |||
| 162 | /* | ||
| 163 | * Register clocksource. The high order bits of PIV are unused, | ||
| 164 | * so this isn't a 32-bit counter unless we get clockevent irqs. | ||
| 165 | */ | ||
| 166 | pit_clk.mult = clocksource_hz2mult(pit_rate, pit_clk.shift); | ||
| 167 | bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */; | ||
| 168 | pit_clk.mask = CLOCKSOURCE_MASK(bits); | ||
| 169 | clocksource_register(&pit_clk); | ||
| 170 | |||
| 171 | /* Set up irq handler */ | ||
| 172 | setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq); | ||
| 173 | |||
| 174 | /* Set up and register clockevents */ | ||
| 175 | pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift); | ||
| 176 | clockevents_register_device(&pit_clkevt); | ||
| 92 | } | 177 | } |
| 93 | 178 | ||
| 94 | #ifdef CONFIG_PM | 179 | static void at91sam926x_pit_suspend(void) |
| 95 | static void at91sam926x_timer_suspend(void) | ||
| 96 | { | 180 | { |
| 97 | /* Disable timer */ | 181 | /* Disable timer */ |
| 98 | at91_sys_write(AT91_PIT_MR, 0); | 182 | at91_sys_write(AT91_PIT_MR, 0); |
| 99 | } | 183 | } |
| 100 | #else | ||
| 101 | #define at91sam926x_timer_suspend NULL | ||
| 102 | #endif | ||
| 103 | 184 | ||
| 104 | struct sys_timer at91sam926x_timer = { | 185 | struct sys_timer at91sam926x_timer = { |
| 105 | .init = at91sam926x_timer_init, | 186 | .init = at91sam926x_pit_init, |
| 106 | .offset = at91sam926x_gettimeoffset, | 187 | .suspend = at91sam926x_pit_suspend, |
| 107 | .suspend = at91sam926x_timer_suspend, | 188 | .resume = at91sam926x_pit_reset, |
| 108 | .resume = at91sam926x_timer_reset, | ||
| 109 | }; | 189 | }; |
| 110 | |||
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index 4813a35f6cf5..902c79893ec7 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c | |||
| @@ -10,6 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include <linux/module.h> | 12 | #include <linux/module.h> |
| 13 | #include <linux/pm.h> | ||
| 13 | 14 | ||
| 14 | #include <asm/mach/arch.h> | 15 | #include <asm/mach/arch.h> |
| 15 | #include <asm/mach/map.h> | 16 | #include <asm/mach/map.h> |
| @@ -17,6 +18,7 @@ | |||
| 17 | #include <asm/arch/at91sam9rl.h> | 18 | #include <asm/arch/at91sam9rl.h> |
| 18 | #include <asm/arch/at91_pmc.h> | 19 | #include <asm/arch/at91_pmc.h> |
| 19 | #include <asm/arch/at91_rstc.h> | 20 | #include <asm/arch/at91_rstc.h> |
| 21 | #include <asm/arch/at91_shdwc.h> | ||
| 20 | 22 | ||
| 21 | #include "generic.h" | 23 | #include "generic.h" |
| 22 | #include "clock.h" | 24 | #include "clock.h" |
| @@ -244,6 +246,11 @@ static void at91sam9rl_reset(void) | |||
| 244 | at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); | 246 | at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); |
| 245 | } | 247 | } |
| 246 | 248 | ||
| 249 | static void at91sam9rl_poweroff(void) | ||
| 250 | { | ||
| 251 | at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); | ||
| 252 | } | ||
| 253 | |||
| 247 | 254 | ||
| 248 | /* -------------------------------------------------------------------- | 255 | /* -------------------------------------------------------------------- |
| 249 | * AT91SAM9RL processor initialization | 256 | * AT91SAM9RL processor initialization |
| @@ -274,6 +281,7 @@ void __init at91sam9rl_initialize(unsigned long main_clock) | |||
| 274 | iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc)); | 281 | iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc)); |
| 275 | 282 | ||
| 276 | at91_arch_reset = at91sam9rl_reset; | 283 | at91_arch_reset = at91sam9rl_reset; |
| 284 | pm_power_off = at91sam9rl_poweroff; | ||
| 277 | at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); | 285 | at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); |
| 278 | 286 | ||
| 279 | /* Init clock subsystem */ | 287 | /* Init clock subsystem */ |
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c index f43b5c33e45d..dbb9a5fc2090 100644 --- a/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/at91sam9rl_devices.c | |||
| @@ -20,7 +20,7 @@ | |||
| 20 | #include <asm/arch/gpio.h> | 20 | #include <asm/arch/gpio.h> |
| 21 | #include <asm/arch/at91sam9rl.h> | 21 | #include <asm/arch/at91sam9rl.h> |
| 22 | #include <asm/arch/at91sam9rl_matrix.h> | 22 | #include <asm/arch/at91sam9rl_matrix.h> |
| 23 | #include <asm/arch/at91sam926x_mc.h> | 23 | #include <asm/arch/at91sam9_smc.h> |
| 24 | 24 | ||
| 25 | #include "generic.h" | 25 | #include "generic.h" |
| 26 | 26 | ||
| @@ -105,10 +105,15 @@ static struct at91_nand_data nand_data; | |||
| 105 | #define NAND_BASE AT91_CHIPSELECT_3 | 105 | #define NAND_BASE AT91_CHIPSELECT_3 |
| 106 | 106 | ||
| 107 | static struct resource nand_resources[] = { | 107 | static struct resource nand_resources[] = { |
| 108 | { | 108 | [0] = { |
| 109 | .start = NAND_BASE, | 109 | .start = NAND_BASE, |
| 110 | .end = NAND_BASE + SZ_256M - 1, | 110 | .end = NAND_BASE + SZ_256M - 1, |
| 111 | .flags = IORESOURCE_MEM, | 111 | .flags = IORESOURCE_MEM, |
| 112 | }, | ||
| 113 | [1] = { | ||
| 114 | .start = AT91_BASE_SYS + AT91_ECC, | ||
| 115 | .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1, | ||
| 116 | .flags = IORESOURCE_MEM, | ||
| 112 | } | 117 | } |
| 113 | }; | 118 | }; |
| 114 | 119 | ||
| @@ -385,6 +390,55 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} | |||
| 385 | 390 | ||
| 386 | 391 | ||
| 387 | /* -------------------------------------------------------------------- | 392 | /* -------------------------------------------------------------------- |
| 393 | * Timer/Counter block | ||
| 394 | * -------------------------------------------------------------------- */ | ||
| 395 | |||
| 396 | #ifdef CONFIG_ATMEL_TCLIB | ||
| 397 | |||
| 398 | static struct resource tcb_resources[] = { | ||
| 399 | [0] = { | ||
| 400 | .start = AT91SAM9RL_BASE_TCB0, | ||
| 401 | .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1, | ||
| 402 | .flags = IORESOURCE_MEM, | ||
| 403 | }, | ||
| 404 | [1] = { | ||
| 405 | .start = AT91SAM9RL_ID_TC0, | ||
| 406 | .end = AT91SAM9RL_ID_TC0, | ||
| 407 | .flags = IORESOURCE_IRQ, | ||
| 408 | }, | ||
| 409 | [2] = { | ||
| 410 | .start = AT91SAM9RL_ID_TC1, | ||
| 411 | .end = AT91SAM9RL_ID_TC1, | ||
| 412 | .flags = IORESOURCE_IRQ, | ||
| 413 | }, | ||
| 414 | [3] = { | ||
| 415 | .start = AT91SAM9RL_ID_TC2, | ||
| 416 | .end = AT91SAM9RL_ID_TC2, | ||
| 417 | .flags = IORESOURCE_IRQ, | ||
| 418 | }, | ||
| 419 | }; | ||
| 420 | |||
| 421 | static struct platform_device at91sam9rl_tcb_device = { | ||
| 422 | .name = "atmel_tcb", | ||
| 423 | .id = 0, | ||
| 424 | .resource = tcb_resources, | ||
| 425 | .num_resources = ARRAY_SIZE(tcb_resources), | ||
| 426 | }; | ||
| 427 | |||
| 428 | static void __init at91_add_device_tc(void) | ||
| 429 | { | ||
| 430 | /* this chip has a separate clock and irq for each TC channel */ | ||
| 431 | at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk"); | ||
| 432 | at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk"); | ||
| 433 | at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk"); | ||
| 434 | platform_device_register(&at91sam9rl_tcb_device); | ||
| 435 | } | ||
| 436 | #else | ||
| 437 | static void __init at91_add_device_tc(void) { } | ||
| 438 | #endif | ||
| 439 | |||
| 440 | |||
| 441 | /* -------------------------------------------------------------------- | ||
| 388 | * RTC | 442 | * RTC |
| 389 | * -------------------------------------------------------------------- */ | 443 | * -------------------------------------------------------------------- */ |
| 390 | 444 | ||
| @@ -418,7 +472,7 @@ static struct resource rtt_resources[] = { | |||
| 418 | 472 | ||
| 419 | static struct platform_device at91sam9rl_rtt_device = { | 473 | static struct platform_device at91sam9rl_rtt_device = { |
| 420 | .name = "at91_rtt", | 474 | .name = "at91_rtt", |
| 421 | .id = -1, | 475 | .id = 0, |
| 422 | .resource = rtt_resources, | 476 | .resource = rtt_resources, |
| 423 | .num_resources = ARRAY_SIZE(rtt_resources), | 477 | .num_resources = ARRAY_SIZE(rtt_resources), |
| 424 | }; | 478 | }; |
| @@ -539,9 +593,6 @@ static inline void configure_ssc1_pins(unsigned pins) | |||
| 539 | } | 593 | } |
| 540 | 594 | ||
| 541 | /* | 595 | /* |
| 542 | * Return the device node so that board init code can use it as the | ||
| 543 | * parent for the device node reflecting how it's used on this board. | ||
| 544 | * | ||
| 545 | * SSC controllers are accessed through library code, instead of any | 596 | * SSC controllers are accessed through library code, instead of any |
| 546 | * kind of all-singing/all-dancing driver. For example one could be | 597 | * kind of all-singing/all-dancing driver. For example one could be |
| 547 | * used by a particular I2S audio codec's driver, while another one | 598 | * used by a particular I2S audio codec's driver, while another one |
| @@ -802,54 +853,9 @@ static inline void configure_usart3_pins(unsigned pins) | |||
| 802 | at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */ | 853 | at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */ |
| 803 | } | 854 | } |
| 804 | 855 | ||
| 805 | static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ | 856 | static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ |
| 806 | struct platform_device *atmel_default_console_device; /* the serial console device */ | 857 | struct platform_device *atmel_default_console_device; /* the serial console device */ |
| 807 | 858 | ||
| 808 | void __init __deprecated at91_init_serial(struct at91_uart_config *config) | ||
| 809 | { | ||
| 810 | int i; | ||
| 811 | |||
| 812 | /* Fill in list of supported UARTs */ | ||
| 813 | for (i = 0; i < config->nr_tty; i++) { | ||
| 814 | switch (config->tty_map[i]) { | ||
| 815 | case 0: | ||
| 816 | configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS); | ||
| 817 | at91_uarts[i] = &at91sam9rl_uart0_device; | ||
| 818 | at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device.dev, "usart"); | ||
| 819 | break; | ||
| 820 | case 1: | ||
| 821 | configure_usart1_pins(0); | ||
| 822 | at91_uarts[i] = &at91sam9rl_uart1_device; | ||
| 823 | at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device.dev, "usart"); | ||
| 824 | break; | ||
| 825 | case 2: | ||
| 826 | configure_usart2_pins(0); | ||
| 827 | at91_uarts[i] = &at91sam9rl_uart2_device; | ||
| 828 | at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device.dev, "usart"); | ||
| 829 | break; | ||
| 830 | case 3: | ||
| 831 | configure_usart3_pins(0); | ||
| 832 | at91_uarts[i] = &at91sam9rl_uart3_device; | ||
| 833 | at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device.dev, "usart"); | ||
| 834 | break; | ||
| 835 | case 4: | ||
| 836 | configure_dbgu_pins(); | ||
| 837 | at91_uarts[i] = &at91sam9rl_dbgu_device; | ||
| 838 | at91_clock_associate("mck", &at91sam9rl_dbgu_device.dev, "usart"); | ||
| 839 | break; | ||
| 840 | default: | ||
| 841 | continue; | ||
| 842 | } | ||
| 843 | at91_uarts[i]->id = i; /* update ID number to mapped ID */ | ||
| 844 | } | ||
| 845 | |||
| 846 | /* Set serial console device */ | ||
| 847 | if (config->console_tty < ATMEL_MAX_UART) | ||
| 848 | atmel_default_console_device = at91_uarts[config->console_tty]; | ||
| 849 | if (!atmel_default_console_device) | ||
| 850 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 851 | } | ||
| 852 | |||
| 853 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) | 859 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) |
| 854 | { | 860 | { |
| 855 | struct platform_device *pdev; | 861 | struct platform_device *pdev; |
| @@ -893,8 +899,6 @@ void __init at91_set_serial_console(unsigned portnr) | |||
| 893 | { | 899 | { |
| 894 | if (portnr < ATMEL_MAX_UART) | 900 | if (portnr < ATMEL_MAX_UART) |
| 895 | atmel_default_console_device = at91_uarts[portnr]; | 901 | atmel_default_console_device = at91_uarts[portnr]; |
| 896 | if (!atmel_default_console_device) | ||
| 897 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 898 | } | 902 | } |
| 899 | 903 | ||
| 900 | void __init at91_add_device_serial(void) | 904 | void __init at91_add_device_serial(void) |
| @@ -905,9 +909,11 @@ void __init at91_add_device_serial(void) | |||
| 905 | if (at91_uarts[i]) | 909 | if (at91_uarts[i]) |
| 906 | platform_device_register(at91_uarts[i]); | 910 | platform_device_register(at91_uarts[i]); |
| 907 | } | 911 | } |
| 912 | |||
| 913 | if (!atmel_default_console_device) | ||
| 914 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 908 | } | 915 | } |
| 909 | #else | 916 | #else |
| 910 | void __init __deprecated at91_init_serial(struct at91_uart_config *config) {} | ||
| 911 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} | 917 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} |
| 912 | void __init at91_set_serial_console(unsigned portnr) {} | 918 | void __init at91_set_serial_console(unsigned portnr) {} |
| 913 | void __init at91_add_device_serial(void) {} | 919 | void __init at91_add_device_serial(void) {} |
| @@ -925,6 +931,7 @@ static int __init at91_add_standard_devices(void) | |||
| 925 | at91_add_device_rtc(); | 931 | at91_add_device_rtc(); |
| 926 | at91_add_device_rtt(); | 932 | at91_add_device_rtt(); |
| 927 | at91_add_device_watchdog(); | 933 | at91_add_device_watchdog(); |
| 934 | at91_add_device_tc(); | ||
| 928 | return 0; | 935 | return 0; |
| 929 | } | 936 | } |
| 930 | 937 | ||
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c new file mode 100644 index 000000000000..b22a1a004055 --- /dev/null +++ b/arch/arm/mach-at91/board-cam60.c | |||
| @@ -0,0 +1,180 @@ | |||
| 1 | /* | ||
| 2 | * KwikByte CAM60 (KB9260) | ||
| 3 | * | ||
| 4 | * based on board-sam9260ek.c | ||
| 5 | * Copyright (C) 2005 SAN People | ||
| 6 | * Copyright (C) 2006 Atmel | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #include <linux/types.h> | ||
| 24 | #include <linux/init.h> | ||
| 25 | #include <linux/mm.h> | ||
| 26 | #include <linux/module.h> | ||
| 27 | #include <linux/platform_device.h> | ||
| 28 | #include <linux/spi/spi.h> | ||
| 29 | #include <linux/spi/flash.h> | ||
| 30 | |||
| 31 | #include <asm/hardware.h> | ||
| 32 | #include <asm/setup.h> | ||
| 33 | #include <asm/mach-types.h> | ||
| 34 | #include <asm/irq.h> | ||
| 35 | |||
| 36 | #include <asm/mach/arch.h> | ||
| 37 | #include <asm/mach/map.h> | ||
| 38 | #include <asm/mach/irq.h> | ||
| 39 | |||
| 40 | #include <asm/arch/board.h> | ||
| 41 | #include <asm/arch/gpio.h> | ||
| 42 | |||
| 43 | #include "generic.h" | ||
| 44 | |||
| 45 | |||
| 46 | static void __init cam60_map_io(void) | ||
| 47 | { | ||
| 48 | /* Initialize processor: 10 MHz crystal */ | ||
| 49 | at91sam9260_initialize(10000000); | ||
| 50 | |||
| 51 | /* DGBU on ttyS0. (Rx & Tx only) */ | ||
| 52 | at91_register_uart(0, 0, 0); | ||
| 53 | |||
| 54 | /* set serial console to ttyS0 (ie, DBGU) */ | ||
| 55 | at91_set_serial_console(0); | ||
| 56 | } | ||
| 57 | |||
| 58 | static void __init cam60_init_irq(void) | ||
| 59 | { | ||
| 60 | at91sam9260_init_interrupts(NULL); | ||
| 61 | } | ||
| 62 | |||
| 63 | |||
| 64 | /* | ||
| 65 | * USB Host | ||
| 66 | */ | ||
| 67 | static struct at91_usbh_data __initdata cam60_usbh_data = { | ||
| 68 | .ports = 1, | ||
| 69 | }; | ||
| 70 | |||
| 71 | |||
| 72 | /* | ||
| 73 | * SPI devices. | ||
| 74 | */ | ||
| 75 | #if defined(CONFIG_MTD_DATAFLASH) | ||
| 76 | static struct mtd_partition __initdata cam60_spi_partitions[] = { | ||
| 77 | { | ||
| 78 | .name = "BOOT1", | ||
| 79 | .offset = 0, | ||
| 80 | .size = 4 * 1056, | ||
| 81 | }, | ||
| 82 | { | ||
| 83 | .name = "BOOT2", | ||
| 84 | .offset = MTDPART_OFS_NXTBLK, | ||
| 85 | .size = 256 * 1056, | ||
| 86 | }, | ||
| 87 | { | ||
| 88 | .name = "kernel", | ||
| 89 | .offset = MTDPART_OFS_NXTBLK, | ||
| 90 | .size = 2222 * 1056, | ||
| 91 | }, | ||
| 92 | { | ||
| 93 | .name = "file system", | ||
| 94 | .offset = MTDPART_OFS_NXTBLK, | ||
| 95 | .size = MTDPART_SIZ_FULL, | ||
| 96 | }, | ||
| 97 | }; | ||
| 98 | |||
| 99 | static struct flash_platform_data __initdata cam60_spi_flash_platform_data = { | ||
| 100 | .name = "spi_flash", | ||
| 101 | .parts = cam60_spi_partitions, | ||
| 102 | .nr_parts = ARRAY_SIZE(cam60_spi_partitions) | ||
| 103 | }; | ||
| 104 | #endif | ||
| 105 | |||
| 106 | static struct spi_board_info cam60_spi_devices[] = { | ||
| 107 | #if defined(CONFIG_MTD_DATAFLASH) | ||
| 108 | { /* DataFlash chip */ | ||
| 109 | .modalias = "mtd_dataflash", | ||
| 110 | .chip_select = 0, | ||
| 111 | .max_speed_hz = 15 * 1000 * 1000, | ||
| 112 | .bus_num = 0, | ||
| 113 | .platform_data = &cam60_spi_flash_platform_data | ||
| 114 | }, | ||
| 115 | #endif | ||
| 116 | }; | ||
| 117 | |||
| 118 | |||
| 119 | /* | ||
| 120 | * MACB Ethernet device | ||
| 121 | */ | ||
| 122 | static struct __initdata at91_eth_data cam60_macb_data = { | ||
| 123 | .phy_irq_pin = AT91_PIN_PB5, | ||
| 124 | .is_rmii = 0, | ||
| 125 | }; | ||
| 126 | |||
| 127 | |||
| 128 | /* | ||
| 129 | * NAND Flash | ||
| 130 | */ | ||
| 131 | static struct mtd_partition __initdata cam60_nand_partition[] = { | ||
| 132 | { | ||
| 133 | .name = "nand_fs", | ||
| 134 | .offset = 0, | ||
| 135 | .size = MTDPART_SIZ_FULL, | ||
| 136 | }, | ||
| 137 | }; | ||
| 138 | |||
| 139 | static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) | ||
| 140 | { | ||
| 141 | *num_partitions = ARRAY_SIZE(cam60_nand_partition); | ||
| 142 | return cam60_nand_partition; | ||
| 143 | } | ||
| 144 | |||
| 145 | static struct at91_nand_data __initdata cam60_nand_data = { | ||
| 146 | .ale = 21, | ||
| 147 | .cle = 22, | ||
| 148 | // .det_pin = ... not there | ||
| 149 | .rdy_pin = AT91_PIN_PA9, | ||
| 150 | .enable_pin = AT91_PIN_PA7, | ||
| 151 | .partition_info = nand_partitions, | ||
| 152 | }; | ||
| 153 | |||
| 154 | |||
| 155 | static void __init cam60_board_init(void) | ||
| 156 | { | ||
| 157 | /* Serial */ | ||
| 158 | at91_add_device_serial(); | ||
| 159 | /* SPI */ | ||
| 160 | at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices)); | ||
| 161 | /* Ethernet */ | ||
| 162 | at91_add_device_eth(&cam60_macb_data); | ||
| 163 | /* USB Host */ | ||
| 164 | /* enable USB power supply circuit */ | ||
| 165 | at91_set_gpio_output(AT91_PIN_PB18, 1); | ||
| 166 | at91_add_device_usbh(&cam60_usbh_data); | ||
| 167 | /* NAND */ | ||
| 168 | at91_add_device_nand(&cam60_nand_data); | ||
| 169 | } | ||
| 170 | |||
| 171 | MACHINE_START(CAM60, "KwikByte CAM60") | ||
| 172 | /* Maintainer: KwikByte */ | ||
| 173 | .phys_io = AT91_BASE_SYS, | ||
| 174 | .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, | ||
| 175 | .boot_params = AT91_SDRAM_BASE + 0x100, | ||
| 176 | .timer = &at91sam926x_timer, | ||
| 177 | .map_io = cam60_map_io, | ||
| 178 | .init_irq = cam60_init_irq, | ||
| 179 | .init_machine = cam60_board_init, | ||
| 180 | MACHINE_END | ||
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c index 185437131541..e5512d1ff217 100644 --- a/arch/arm/mach-at91/board-cap9adk.c +++ b/arch/arm/mach-at91/board-cap9adk.c | |||
| @@ -45,7 +45,7 @@ | |||
| 45 | #include <asm/arch/board.h> | 45 | #include <asm/arch/board.h> |
| 46 | #include <asm/arch/gpio.h> | 46 | #include <asm/arch/gpio.h> |
| 47 | #include <asm/arch/at91cap9_matrix.h> | 47 | #include <asm/arch/at91cap9_matrix.h> |
| 48 | #include <asm/arch/at91sam926x_mc.h> | 48 | #include <asm/arch/at91sam9_smc.h> |
| 49 | 49 | ||
| 50 | #include "generic.h" | 50 | #include "generic.h" |
| 51 | 51 | ||
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c index 0e2a11fc5bbd..26fea4dcc3a0 100644 --- a/arch/arm/mach-at91/board-csb337.c +++ b/arch/arm/mach-at91/board-csb337.c | |||
| @@ -43,17 +43,6 @@ | |||
| 43 | #include "generic.h" | 43 | #include "generic.h" |
| 44 | 44 | ||
| 45 | 45 | ||
| 46 | /* | ||
| 47 | * Serial port configuration. | ||
| 48 | * 0 .. 3 = USART0 .. USART3 | ||
| 49 | * 4 = DBGU | ||
| 50 | */ | ||
| 51 | static struct at91_uart_config __initdata csb337_uart_config = { | ||
| 52 | .console_tty = 0, /* ttyS0 */ | ||
| 53 | .nr_tty = 2, | ||
| 54 | .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ | ||
| 55 | }; | ||
| 56 | |||
| 57 | static void __init csb337_map_io(void) | 46 | static void __init csb337_map_io(void) |
| 58 | { | 47 | { |
| 59 | /* Initialize processor: 3.6864 MHz crystal */ | 48 | /* Initialize processor: 3.6864 MHz crystal */ |
| @@ -62,8 +51,11 @@ static void __init csb337_map_io(void) | |||
| 62 | /* Setup the LEDs */ | 51 | /* Setup the LEDs */ |
| 63 | at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); | 52 | at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); |
| 64 | 53 | ||
| 65 | /* Setup the serial ports and console */ | 54 | /* DBGU on ttyS0 */ |
| 66 | at91_init_serial(&csb337_uart_config); | 55 | at91_register_uart(0, 0, 0); |
| 56 | |||
| 57 | /* make console=ttyS0 the default */ | ||
| 58 | at91_set_serial_console(0); | ||
| 67 | } | 59 | } |
| 68 | 60 | ||
| 69 | static void __init csb337_init_irq(void) | 61 | static void __init csb337_init_irq(void) |
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c index c5c721d27f42..419fd19b620b 100644 --- a/arch/arm/mach-at91/board-csb637.c +++ b/arch/arm/mach-at91/board-csb637.c | |||
| @@ -40,27 +40,16 @@ | |||
| 40 | #include "generic.h" | 40 | #include "generic.h" |
| 41 | 41 | ||
| 42 | 42 | ||
| 43 | /* | ||
| 44 | * Serial port configuration. | ||
| 45 | * 0 .. 3 = USART0 .. USART3 | ||
| 46 | * 4 = DBGU | ||
| 47 | */ | ||
| 48 | static struct at91_uart_config __initdata csb637_uart_config = { | ||
| 49 | .console_tty = 0, /* ttyS0 */ | ||
| 50 | .nr_tty = 2, | ||
| 51 | .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ | ||
| 52 | }; | ||
| 53 | |||
| 54 | static void __init csb637_map_io(void) | 43 | static void __init csb637_map_io(void) |
| 55 | { | 44 | { |
| 56 | /* Initialize processor: 3.6864 MHz crystal */ | 45 | /* Initialize processor: 3.6864 MHz crystal */ |
| 57 | at91rm9200_initialize(3686400, AT91RM9200_BGA); | 46 | at91rm9200_initialize(3686400, AT91RM9200_BGA); |
| 58 | 47 | ||
| 59 | /* Setup the LEDs */ | 48 | /* DBGU on ttyS0 */ |
| 60 | at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); | 49 | at91_register_uart(0, 0, 0); |
| 61 | 50 | ||
| 62 | /* Setup the serial ports and console */ | 51 | /* make console=ttyS0 the default */ |
| 63 | at91_init_serial(&csb637_uart_config); | 52 | at91_set_serial_console(0); |
| 64 | } | 53 | } |
| 65 | 54 | ||
| 66 | static void __init csb637_init_irq(void) | 55 | static void __init csb637_init_irq(void) |
| @@ -118,8 +107,19 @@ static struct platform_device csb_flash = { | |||
| 118 | .num_resources = ARRAY_SIZE(csb_flash_resources), | 107 | .num_resources = ARRAY_SIZE(csb_flash_resources), |
| 119 | }; | 108 | }; |
| 120 | 109 | ||
| 110 | static struct gpio_led csb_leds[] = { | ||
| 111 | { /* "d1", red */ | ||
| 112 | .name = "d1", | ||
| 113 | .gpio = AT91_PIN_PB2, | ||
| 114 | .active_low = 1, | ||
| 115 | .default_trigger = "heartbeat", | ||
| 116 | }, | ||
| 117 | }; | ||
| 118 | |||
| 121 | static void __init csb637_board_init(void) | 119 | static void __init csb637_board_init(void) |
| 122 | { | 120 | { |
| 121 | /* LED(s) */ | ||
| 122 | at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds)); | ||
| 123 | /* Serial */ | 123 | /* Serial */ |
| 124 | at91_add_device_serial(); | 124 | at91_add_device_serial(); |
| 125 | /* Ethernet */ | 125 | /* Ethernet */ |
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c new file mode 100644 index 000000000000..e77fad443835 --- /dev/null +++ b/arch/arm/mach-at91/board-ecbat91.c | |||
| @@ -0,0 +1,178 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-at91rm9200/board-ecbat91.c | ||
| 3 | * Copyright (C) 2007 emQbit.com. | ||
| 4 | * | ||
| 5 | * We started from board-dk.c, which is Copyright (C) 2005 SAN People. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/types.h> | ||
| 23 | #include <linux/init.h> | ||
| 24 | #include <linux/mm.h> | ||
| 25 | #include <linux/module.h> | ||
| 26 | #include <linux/platform_device.h> | ||
| 27 | #include <linux/spi/spi.h> | ||
| 28 | #include <linux/spi/flash.h> | ||
| 29 | |||
| 30 | #include <asm/hardware.h> | ||
| 31 | #include <asm/setup.h> | ||
| 32 | #include <asm/mach-types.h> | ||
| 33 | #include <asm/irq.h> | ||
| 34 | |||
| 35 | #include <asm/mach/arch.h> | ||
| 36 | #include <asm/mach/map.h> | ||
| 37 | #include <asm/mach/irq.h> | ||
| 38 | |||
| 39 | #include <asm/arch/board.h> | ||
| 40 | #include <asm/arch/gpio.h> | ||
| 41 | |||
| 42 | #include "generic.h" | ||
| 43 | |||
| 44 | |||
| 45 | static void __init ecb_at91map_io(void) | ||
| 46 | { | ||
| 47 | /* Initialize processor: 18.432 MHz crystal */ | ||
| 48 | at91rm9200_initialize(18432000, AT91RM9200_PQFP); | ||
| 49 | |||
| 50 | /* Setup the LEDs */ | ||
| 51 | at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7); | ||
| 52 | |||
| 53 | /* DBGU on ttyS0. (Rx & Tx only) */ | ||
| 54 | at91_register_uart(0, 0, 0); | ||
| 55 | |||
| 56 | /* USART0 on ttyS1. (Rx & Tx only) */ | ||
| 57 | at91_register_uart(AT91RM9200_ID_US0, 1, 0); | ||
| 58 | |||
| 59 | /* set serial console to ttyS0 (ie, DBGU) */ | ||
| 60 | at91_set_serial_console(0); | ||
| 61 | } | ||
| 62 | |||
| 63 | static void __init ecb_at91init_irq(void) | ||
| 64 | { | ||
| 65 | at91rm9200_init_interrupts(NULL); | ||
| 66 | } | ||
| 67 | |||
| 68 | static struct at91_eth_data __initdata ecb_at91eth_data = { | ||
| 69 | .phy_irq_pin = AT91_PIN_PC4, | ||
| 70 | .is_rmii = 0, | ||
| 71 | }; | ||
| 72 | |||
| 73 | static struct at91_usbh_data __initdata ecb_at91usbh_data = { | ||
| 74 | .ports = 1, | ||
| 75 | }; | ||
| 76 | |||
| 77 | static struct at91_mmc_data __initdata ecb_at91mmc_data = { | ||
| 78 | .slot_b = 0, | ||
| 79 | .wire4 = 1, | ||
| 80 | }; | ||
| 81 | |||
| 82 | |||
| 83 | #if defined(CONFIG_MTD_DATAFLASH) | ||
| 84 | static struct mtd_partition __initdata my_flash0_partitions[] = | ||
| 85 | { | ||
| 86 | { /* 0x8400 */ | ||
| 87 | .name = "Darrell-loader", | ||
| 88 | .offset = 0, | ||
| 89 | .size = 12* 1056, | ||
| 90 | }, | ||
| 91 | { | ||
| 92 | .name = "U-boot", | ||
| 93 | .offset = MTDPART_OFS_NXTBLK, | ||
| 94 | .size = 110 * 1056, | ||
| 95 | }, | ||
| 96 | { /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */ | ||
| 97 | .name = "UBoot-env", | ||
| 98 | .offset = MTDPART_OFS_NXTBLK, | ||
| 99 | .size = 8 * 1056, | ||
| 100 | }, | ||
| 101 | { /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */ | ||
| 102 | .name = "Kernel", | ||
| 103 | .offset = MTDPART_OFS_NXTBLK, | ||
| 104 | .size = 1534 * 1056, | ||
| 105 | }, | ||
| 106 | { /* 190200 - jffs2 root filesystem */ | ||
| 107 | .name = "Filesystem", | ||
| 108 | .offset = MTDPART_OFS_NXTBLK, | ||
| 109 | .size = MTDPART_SIZ_FULL, /* 26 sectors */ | ||
| 110 | } | ||
| 111 | }; | ||
| 112 | |||
| 113 | static struct flash_platform_data __initdata my_flash0_platform = { | ||
| 114 | .name = "Removable flash card", | ||
| 115 | .parts = my_flash0_partitions, | ||
| 116 | .nr_parts = ARRAY_SIZE(my_flash0_partitions) | ||
| 117 | }; | ||
| 118 | |||
| 119 | #endif | ||
| 120 | |||
| 121 | static struct spi_board_info __initdata ecb_at91spi_devices[] = { | ||
| 122 | { /* DataFlash chip */ | ||
| 123 | .modalias = "mtd_dataflash", | ||
| 124 | .chip_select = 0, | ||
| 125 | .max_speed_hz = 10 * 1000 * 1000, | ||
| 126 | .bus_num = 0, | ||
| 127 | #if defined(CONFIG_MTD_DATAFLASH) | ||
| 128 | .platform_data = &my_flash0_platform, | ||
| 129 | #endif | ||
| 130 | }, | ||
| 131 | { /* User accessable spi - cs1 (250KHz) */ | ||
| 132 | .modalias = "spi-cs1", | ||
| 133 | .chip_select = 1, | ||
| 134 | .max_speed_hz = 250 * 1000, | ||
| 135 | }, | ||
| 136 | { /* User accessable spi - cs2 (1MHz) */ | ||
| 137 | .modalias = "spi-cs2", | ||
| 138 | .chip_select = 2, | ||
| 139 | .max_speed_hz = 1 * 1000 * 1000, | ||
| 140 | }, | ||
| 141 | { /* User accessable spi - cs3 (10MHz) */ | ||
| 142 | .modalias = "spi-cs3", | ||
| 143 | .chip_select = 3, | ||
| 144 | .max_speed_hz = 10 * 1000 * 1000, | ||
| 145 | }, | ||
| 146 | }; | ||
| 147 | |||
| 148 | static void __init ecb_at91board_init(void) | ||
| 149 | { | ||
| 150 | /* Serial */ | ||
| 151 | at91_add_device_serial(); | ||
| 152 | |||
| 153 | /* Ethernet */ | ||
| 154 | at91_add_device_eth(&ecb_at91eth_data); | ||
| 155 | |||
| 156 | /* USB Host */ | ||
| 157 | at91_add_device_usbh(&ecb_at91usbh_data); | ||
| 158 | |||
| 159 | /* I2C */ | ||
| 160 | at91_add_device_i2c(NULL, 0); | ||
| 161 | |||
| 162 | /* MMC */ | ||
| 163 | at91_add_device_mmc(0, &ecb_at91mmc_data); | ||
| 164 | |||
| 165 | /* SPI */ | ||
| 166 | at91_add_device_spi(ecb_at91spi_devices, ARRAY_SIZE(ecb_at91spi_devices)); | ||
| 167 | } | ||
| 168 | |||
| 169 | MACHINE_START(ECBAT91, "emQbit's ECB_AT91") | ||
| 170 | /* Maintainer: emQbit.com */ | ||
| 171 | .phys_io = AT91_BASE_SYS, | ||
| 172 | .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, | ||
| 173 | .boot_params = AT91_SDRAM_BASE + 0x100, | ||
| 174 | .timer = &at91rm9200_timer, | ||
| 175 | .map_io = ecb_at91map_io, | ||
| 176 | .init_irq = ecb_at91init_irq, | ||
| 177 | .init_machine = ecb_at91board_init, | ||
| 178 | MACHINE_END | ||
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c new file mode 100644 index 000000000000..8f76af5e219a --- /dev/null +++ b/arch/arm/mach-at91/board-sam9-l9260.c | |||
| @@ -0,0 +1,199 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-at91/board-sam9-l9260.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 SAN People | ||
| 5 | * Copyright (C) 2006 Atmel | ||
| 6 | * Copyright (C) 2007 Olimex Ltd | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #include <linux/types.h> | ||
| 24 | #include <linux/init.h> | ||
| 25 | #include <linux/mm.h> | ||
| 26 | #include <linux/module.h> | ||
| 27 | #include <linux/platform_device.h> | ||
| 28 | #include <linux/spi/spi.h> | ||
| 29 | |||
| 30 | #include <asm/hardware.h> | ||
| 31 | #include <asm/setup.h> | ||
| 32 | #include <asm/mach-types.h> | ||
| 33 | #include <asm/irq.h> | ||
| 34 | |||
| 35 | #include <asm/mach/arch.h> | ||
| 36 | #include <asm/mach/map.h> | ||
| 37 | #include <asm/mach/irq.h> | ||
| 38 | |||
| 39 | #include <asm/arch/board.h> | ||
| 40 | #include <asm/arch/gpio.h> | ||
| 41 | |||
| 42 | #include "generic.h" | ||
| 43 | |||
| 44 | |||
| 45 | static void __init ek_map_io(void) | ||
| 46 | { | ||
| 47 | /* Initialize processor: 18.432 MHz crystal */ | ||
| 48 | at91sam9260_initialize(18432000); | ||
| 49 | |||
| 50 | /* Setup the LEDs */ | ||
| 51 | at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6); | ||
| 52 | |||
| 53 | /* DBGU on ttyS0. (Rx & Tx only) */ | ||
| 54 | at91_register_uart(0, 0, 0); | ||
| 55 | |||
| 56 | /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ | ||
| 57 | at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS | ||
| 58 | | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD | ||
| 59 | | ATMEL_UART_RI); | ||
| 60 | |||
| 61 | /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ | ||
| 62 | at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); | ||
| 63 | |||
| 64 | /* set serial console to ttyS0 (ie, DBGU) */ | ||
| 65 | at91_set_serial_console(0); | ||
| 66 | } | ||
| 67 | |||
| 68 | static void __init ek_init_irq(void) | ||
| 69 | { | ||
| 70 | at91sam9260_init_interrupts(NULL); | ||
| 71 | } | ||
| 72 | |||
| 73 | |||
| 74 | /* | ||
| 75 | * USB Host port | ||
| 76 | */ | ||
| 77 | static struct at91_usbh_data __initdata ek_usbh_data = { | ||
| 78 | .ports = 2, | ||
| 79 | }; | ||
| 80 | |||
| 81 | /* | ||
| 82 | * USB Device port | ||
| 83 | */ | ||
| 84 | static struct at91_udc_data __initdata ek_udc_data = { | ||
| 85 | .vbus_pin = AT91_PIN_PC5, | ||
| 86 | .pullup_pin = 0, /* pull-up driven by UDC */ | ||
| 87 | }; | ||
| 88 | |||
| 89 | |||
| 90 | /* | ||
| 91 | * SPI devices. | ||
| 92 | */ | ||
| 93 | static struct spi_board_info ek_spi_devices[] = { | ||
| 94 | #if !defined(CONFIG_MMC_AT91) | ||
| 95 | { /* DataFlash chip */ | ||
| 96 | .modalias = "mtd_dataflash", | ||
| 97 | .chip_select = 1, | ||
| 98 | .max_speed_hz = 15 * 1000 * 1000, | ||
| 99 | .bus_num = 0, | ||
| 100 | }, | ||
| 101 | #if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) | ||
| 102 | { /* DataFlash card */ | ||
| 103 | .modalias = "mtd_dataflash", | ||
| 104 | .chip_select = 0, | ||
| 105 | .max_speed_hz = 15 * 1000 * 1000, | ||
| 106 | .bus_num = 0, | ||
| 107 | }, | ||
| 108 | #endif | ||
| 109 | #endif | ||
| 110 | }; | ||
| 111 | |||
| 112 | |||
| 113 | /* | ||
| 114 | * MACB Ethernet device | ||
| 115 | */ | ||
| 116 | static struct at91_eth_data __initdata ek_macb_data = { | ||
| 117 | .phy_irq_pin = AT91_PIN_PA7, | ||
| 118 | .is_rmii = 0, | ||
| 119 | }; | ||
| 120 | |||
| 121 | |||
| 122 | /* | ||
| 123 | * NAND flash | ||
| 124 | */ | ||
| 125 | static struct mtd_partition __initdata ek_nand_partition[] = { | ||
| 126 | { | ||
| 127 | .name = "Bootloader Area", | ||
| 128 | .offset = 0, | ||
| 129 | .size = 10 * 1024 * 1024, | ||
| 130 | }, | ||
| 131 | { | ||
| 132 | .name = "User Area", | ||
| 133 | .offset = 10 * 1024 * 1024, | ||
| 134 | .size = MTDPART_SIZ_FULL, | ||
| 135 | }, | ||
| 136 | }; | ||
| 137 | |||
| 138 | static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) | ||
| 139 | { | ||
| 140 | *num_partitions = ARRAY_SIZE(ek_nand_partition); | ||
| 141 | return ek_nand_partition; | ||
| 142 | } | ||
| 143 | |||
| 144 | static struct at91_nand_data __initdata ek_nand_data = { | ||
| 145 | .ale = 21, | ||
| 146 | .cle = 22, | ||
| 147 | // .det_pin = ... not connected | ||
| 148 | .rdy_pin = AT91_PIN_PC13, | ||
| 149 | .enable_pin = AT91_PIN_PC14, | ||
| 150 | .partition_info = nand_partitions, | ||
| 151 | #if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16) | ||
| 152 | .bus_width_16 = 1, | ||
| 153 | #else | ||
| 154 | .bus_width_16 = 0, | ||
| 155 | #endif | ||
| 156 | }; | ||
| 157 | |||
| 158 | |||
| 159 | /* | ||
| 160 | * MCI (SD/MMC) | ||
| 161 | */ | ||
| 162 | static struct at91_mmc_data __initdata ek_mmc_data = { | ||
| 163 | .slot_b = 1, | ||
| 164 | .wire4 = 1, | ||
| 165 | .det_pin = AT91_PIN_PC8, | ||
| 166 | .wp_pin = AT91_PIN_PC4, | ||
| 167 | // .vcc_pin = ... not connected | ||
| 168 | }; | ||
| 169 | |||
| 170 | static void __init ek_board_init(void) | ||
| 171 | { | ||
| 172 | /* Serial */ | ||
| 173 | at91_add_device_serial(); | ||
| 174 | /* USB Host */ | ||
| 175 | at91_add_device_usbh(&ek_usbh_data); | ||
| 176 | /* USB Device */ | ||
| 177 | at91_add_device_udc(&ek_udc_data); | ||
| 178 | /* SPI */ | ||
| 179 | at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); | ||
| 180 | /* NAND */ | ||
| 181 | at91_add_device_nand(&ek_nand_data); | ||
| 182 | /* Ethernet */ | ||
| 183 | at91_add_device_eth(&ek_macb_data); | ||
| 184 | /* MMC */ | ||
| 185 | at91_add_device_mmc(0, &ek_mmc_data); | ||
| 186 | /* I2C */ | ||
| 187 | at91_add_device_i2c(NULL, 0); | ||
| 188 | } | ||
| 189 | |||
| 190 | MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260") | ||
| 191 | /* Maintainer: Olimex */ | ||
| 192 | .phys_io = AT91_BASE_SYS, | ||
| 193 | .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, | ||
| 194 | .boot_params = AT91_SDRAM_BASE + 0x100, | ||
| 195 | .timer = &at91sam926x_timer, | ||
| 196 | .map_io = ek_map_io, | ||
| 197 | .init_irq = ek_init_irq, | ||
| 198 | .init_machine = ek_board_init, | ||
| 199 | MACHINE_END | ||
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c index b343a6c28120..4d1d9c777084 100644 --- a/arch/arm/mach-at91/board-sam9260ek.c +++ b/arch/arm/mach-at91/board-sam9260ek.c | |||
| @@ -25,6 +25,8 @@ | |||
| 25 | #include <linux/module.h> | 25 | #include <linux/module.h> |
| 26 | #include <linux/platform_device.h> | 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/spi/spi.h> | 27 | #include <linux/spi/spi.h> |
| 28 | #include <linux/spi/at73c213.h> | ||
| 29 | #include <linux/clk.h> | ||
| 28 | 30 | ||
| 29 | #include <asm/hardware.h> | 31 | #include <asm/hardware.h> |
| 30 | #include <asm/setup.h> | 32 | #include <asm/setup.h> |
| @@ -37,29 +39,28 @@ | |||
| 37 | 39 | ||
| 38 | #include <asm/arch/board.h> | 40 | #include <asm/arch/board.h> |
| 39 | #include <asm/arch/gpio.h> | 41 | #include <asm/arch/gpio.h> |
| 40 | #include <asm/arch/at91sam926x_mc.h> | ||
| 41 | 42 | ||
| 42 | #include "generic.h" | 43 | #include "generic.h" |
| 43 | 44 | ||
| 44 | 45 | ||
| 45 | /* | ||
| 46 | * Serial port configuration. | ||
| 47 | * 0 .. 5 = USART0 .. USART5 | ||
| 48 | * 6 = DBGU | ||
| 49 | */ | ||
| 50 | static struct at91_uart_config __initdata ek_uart_config = { | ||
| 51 | .console_tty = 0, /* ttyS0 */ | ||
| 52 | .nr_tty = 3, | ||
| 53 | .tty_map = { 6, 0, 1, -1, -1, -1, -1 } /* ttyS0, ..., ttyS6 */ | ||
| 54 | }; | ||
| 55 | |||
| 56 | static void __init ek_map_io(void) | 46 | static void __init ek_map_io(void) |
| 57 | { | 47 | { |
| 58 | /* Initialize processor: 18.432 MHz crystal */ | 48 | /* Initialize processor: 18.432 MHz crystal */ |
| 59 | at91sam9260_initialize(18432000); | 49 | at91sam9260_initialize(18432000); |
| 60 | 50 | ||
| 61 | /* Setup the serial ports and console */ | 51 | /* DGBU on ttyS0. (Rx & Tx only) */ |
| 62 | at91_init_serial(&ek_uart_config); | 52 | at91_register_uart(0, 0, 0); |
| 53 | |||
| 54 | /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ | ||
| 55 | at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS | ||
| 56 | | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD | ||
| 57 | | ATMEL_UART_RI); | ||
| 58 | |||
| 59 | /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ | ||
| 60 | at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); | ||
| 61 | |||
| 62 | /* set serial console to ttyS0 (ie, DBGU) */ | ||
| 63 | at91_set_serial_console(0); | ||
| 63 | } | 64 | } |
| 64 | 65 | ||
| 65 | static void __init ek_init_irq(void) | 66 | static void __init ek_init_irq(void) |
| @@ -85,6 +86,35 @@ static struct at91_udc_data __initdata ek_udc_data = { | |||
| 85 | 86 | ||
| 86 | 87 | ||
| 87 | /* | 88 | /* |
| 89 | * Audio | ||
| 90 | */ | ||
| 91 | static struct at73c213_board_info at73c213_data = { | ||
| 92 | .ssc_id = 0, | ||
| 93 | .shortname = "AT91SAM9260-EK external DAC", | ||
| 94 | }; | ||
| 95 | |||
| 96 | #if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE) | ||
| 97 | static void __init at73c213_set_clk(struct at73c213_board_info *info) | ||
| 98 | { | ||
| 99 | struct clk *pck0; | ||
| 100 | struct clk *plla; | ||
| 101 | |||
| 102 | pck0 = clk_get(NULL, "pck0"); | ||
| 103 | plla = clk_get(NULL, "plla"); | ||
| 104 | |||
| 105 | /* AT73C213 MCK Clock */ | ||
| 106 | at91_set_B_periph(AT91_PIN_PC1, 0); /* PCK0 */ | ||
| 107 | |||
| 108 | clk_set_parent(pck0, plla); | ||
| 109 | clk_put(plla); | ||
| 110 | |||
| 111 | info->dac_clk = pck0; | ||
| 112 | } | ||
| 113 | #else | ||
| 114 | static void __init at73c213_set_clk(struct at73c213_board_info *info) {} | ||
| 115 | #endif | ||
| 116 | |||
| 117 | /* | ||
| 88 | * SPI devices. | 118 | * SPI devices. |
| 89 | */ | 119 | */ |
| 90 | static struct spi_board_info ek_spi_devices[] = { | 120 | static struct spi_board_info ek_spi_devices[] = { |
| @@ -110,6 +140,8 @@ static struct spi_board_info ek_spi_devices[] = { | |||
| 110 | .chip_select = 0, | 140 | .chip_select = 0, |
| 111 | .max_speed_hz = 10 * 1000 * 1000, | 141 | .max_speed_hz = 10 * 1000 * 1000, |
| 112 | .bus_num = 1, | 142 | .bus_num = 1, |
| 143 | .mode = SPI_MODE_1, | ||
| 144 | .platform_data = &at73c213_data, | ||
| 113 | }, | 145 | }, |
| 114 | #endif | 146 | #endif |
| 115 | }; | 147 | }; |
| @@ -172,6 +204,24 @@ static struct at91_mmc_data __initdata ek_mmc_data = { | |||
| 172 | // .vcc_pin = ... not connected | 204 | // .vcc_pin = ... not connected |
| 173 | }; | 205 | }; |
| 174 | 206 | ||
| 207 | |||
| 208 | /* | ||
| 209 | * LEDs | ||
| 210 | */ | ||
| 211 | static struct gpio_led ek_leds[] = { | ||
| 212 | { /* "bottom" led, green, userled1 to be defined */ | ||
| 213 | .name = "ds5", | ||
| 214 | .gpio = AT91_PIN_PA6, | ||
| 215 | .active_low = 1, | ||
| 216 | .default_trigger = "none", | ||
| 217 | }, | ||
| 218 | { /* "power" led, yellow */ | ||
| 219 | .name = "ds1", | ||
| 220 | .gpio = AT91_PIN_PA9, | ||
| 221 | .default_trigger = "heartbeat", | ||
| 222 | } | ||
| 223 | }; | ||
| 224 | |||
| 175 | static void __init ek_board_init(void) | 225 | static void __init ek_board_init(void) |
| 176 | { | 226 | { |
| 177 | /* Serial */ | 227 | /* Serial */ |
| @@ -190,6 +240,11 @@ static void __init ek_board_init(void) | |||
| 190 | at91_add_device_mmc(0, &ek_mmc_data); | 240 | at91_add_device_mmc(0, &ek_mmc_data); |
| 191 | /* I2C */ | 241 | /* I2C */ |
| 192 | at91_add_device_i2c(NULL, 0); | 242 | at91_add_device_i2c(NULL, 0); |
| 243 | /* SSC (to AT73C213) */ | ||
| 244 | at73c213_set_clk(&at73c213_data); | ||
| 245 | at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX); | ||
| 246 | /* LEDs */ | ||
| 247 | at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); | ||
| 193 | } | 248 | } |
| 194 | 249 | ||
| 195 | MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK") | 250 | MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK") |
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index 0ce38dfa6ebe..08382c0df221 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c | |||
| @@ -26,6 +26,8 @@ | |||
| 26 | #include <linux/platform_device.h> | 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/spi/spi.h> | 27 | #include <linux/spi/spi.h> |
| 28 | #include <linux/spi/ads7846.h> | 28 | #include <linux/spi/ads7846.h> |
| 29 | #include <linux/spi/at73c213.h> | ||
| 30 | #include <linux/clk.h> | ||
| 29 | #include <linux/dm9000.h> | 31 | #include <linux/dm9000.h> |
| 30 | #include <linux/fb.h> | 32 | #include <linux/fb.h> |
| 31 | #include <linux/gpio_keys.h> | 33 | #include <linux/gpio_keys.h> |
| @@ -44,22 +46,11 @@ | |||
| 44 | 46 | ||
| 45 | #include <asm/arch/board.h> | 47 | #include <asm/arch/board.h> |
| 46 | #include <asm/arch/gpio.h> | 48 | #include <asm/arch/gpio.h> |
| 47 | #include <asm/arch/at91sam926x_mc.h> | 49 | #include <asm/arch/at91sam9_smc.h> |
| 48 | 50 | ||
| 49 | #include "generic.h" | 51 | #include "generic.h" |
| 50 | 52 | ||
| 51 | 53 | ||
| 52 | /* | ||
| 53 | * Serial port configuration. | ||
| 54 | * 0 .. 2 = USART0 .. USART2 | ||
| 55 | * 3 = DBGU | ||
| 56 | */ | ||
| 57 | static struct at91_uart_config __initdata ek_uart_config = { | ||
| 58 | .console_tty = 0, /* ttyS0 */ | ||
| 59 | .nr_tty = 1, | ||
| 60 | .tty_map = { 3, -1, -1, -1 } /* ttyS0, ..., ttyS3 */ | ||
| 61 | }; | ||
| 62 | |||
| 63 | static void __init ek_map_io(void) | 54 | static void __init ek_map_io(void) |
| 64 | { | 55 | { |
| 65 | /* Initialize processor: 18.432 MHz crystal */ | 56 | /* Initialize processor: 18.432 MHz crystal */ |
| @@ -68,8 +59,11 @@ static void __init ek_map_io(void) | |||
| 68 | /* Setup the LEDs */ | 59 | /* Setup the LEDs */ |
| 69 | at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14); | 60 | at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14); |
| 70 | 61 | ||
| 71 | /* Setup the serial ports and console */ | 62 | /* DGBU on ttyS0. (Rx & Tx only) */ |
| 72 | at91_init_serial(&ek_uart_config); | 63 | at91_register_uart(0, 0, 0); |
| 64 | |||
| 65 | /* set serial console to ttyS0 (ie, DBGU) */ | ||
| 66 | at91_set_serial_console(0); | ||
| 73 | } | 67 | } |
| 74 | 68 | ||
| 75 | static void __init ek_init_irq(void) | 69 | static void __init ek_init_irq(void) |
| @@ -239,6 +233,35 @@ static void __init ek_add_device_ts(void) {} | |||
| 239 | #endif | 233 | #endif |
| 240 | 234 | ||
| 241 | /* | 235 | /* |
| 236 | * Audio | ||
| 237 | */ | ||
| 238 | static struct at73c213_board_info at73c213_data = { | ||
| 239 | .ssc_id = 1, | ||
| 240 | .shortname = "AT91SAM9261-EK external DAC", | ||
| 241 | }; | ||
| 242 | |||
| 243 | #if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE) | ||
| 244 | static void __init at73c213_set_clk(struct at73c213_board_info *info) | ||
| 245 | { | ||
| 246 | struct clk *pck2; | ||
| 247 | struct clk *plla; | ||
| 248 | |||
| 249 | pck2 = clk_get(NULL, "pck2"); | ||
| 250 | plla = clk_get(NULL, "plla"); | ||
| 251 | |||
| 252 | /* AT73C213 MCK Clock */ | ||
| 253 | at91_set_B_periph(AT91_PIN_PB31, 0); /* PCK2 */ | ||
| 254 | |||
| 255 | clk_set_parent(pck2, plla); | ||
| 256 | clk_put(plla); | ||
| 257 | |||
| 258 | info->dac_clk = pck2; | ||
| 259 | } | ||
| 260 | #else | ||
| 261 | static void __init at73c213_set_clk(struct at73c213_board_info *info) {} | ||
| 262 | #endif | ||
| 263 | |||
| 264 | /* | ||
| 242 | * SPI devices | 265 | * SPI devices |
| 243 | */ | 266 | */ |
| 244 | static struct spi_board_info ek_spi_devices[] = { | 267 | static struct spi_board_info ek_spi_devices[] = { |
| @@ -256,6 +279,7 @@ static struct spi_board_info ek_spi_devices[] = { | |||
| 256 | .bus_num = 0, | 279 | .bus_num = 0, |
| 257 | .platform_data = &ads_info, | 280 | .platform_data = &ads_info, |
| 258 | .irq = AT91SAM9261_ID_IRQ0, | 281 | .irq = AT91SAM9261_ID_IRQ0, |
| 282 | .controller_data = (void *) AT91_PIN_PA28, /* CS pin */ | ||
| 259 | }, | 283 | }, |
| 260 | #endif | 284 | #endif |
| 261 | #if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) | 285 | #if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) |
| @@ -271,6 +295,9 @@ static struct spi_board_info ek_spi_devices[] = { | |||
| 271 | .chip_select = 3, | 295 | .chip_select = 3, |
| 272 | .max_speed_hz = 10 * 1000 * 1000, | 296 | .max_speed_hz = 10 * 1000 * 1000, |
| 273 | .bus_num = 0, | 297 | .bus_num = 0, |
| 298 | .mode = SPI_MODE_1, | ||
| 299 | .platform_data = &at73c213_data, | ||
| 300 | .controller_data = (void*) AT91_PIN_PA29, /* default for CS3 is PA6, but it must be PA29 */ | ||
| 274 | }, | 301 | }, |
| 275 | #endif | 302 | #endif |
| 276 | }; | 303 | }; |
| @@ -460,6 +487,29 @@ static void __init ek_add_device_buttons(void) | |||
| 460 | static void __init ek_add_device_buttons(void) {} | 487 | static void __init ek_add_device_buttons(void) {} |
| 461 | #endif | 488 | #endif |
| 462 | 489 | ||
| 490 | /* | ||
| 491 | * LEDs | ||
| 492 | */ | ||
| 493 | static struct gpio_led ek_leds[] = { | ||
| 494 | { /* "bottom" led, green, userled1 to be defined */ | ||
| 495 | .name = "ds7", | ||
| 496 | .gpio = AT91_PIN_PA14, | ||
| 497 | .active_low = 1, | ||
| 498 | .default_trigger = "none", | ||
| 499 | }, | ||
| 500 | { /* "top" led, green, userled2 to be defined */ | ||
| 501 | .name = "ds8", | ||
| 502 | .gpio = AT91_PIN_PA13, | ||
| 503 | .active_low = 1, | ||
| 504 | .default_trigger = "none", | ||
| 505 | }, | ||
| 506 | { /* "power" led, yellow */ | ||
| 507 | .name = "ds1", | ||
| 508 | .gpio = AT91_PIN_PA23, | ||
| 509 | .default_trigger = "heartbeat", | ||
| 510 | } | ||
| 511 | }; | ||
| 512 | |||
| 463 | static void __init ek_board_init(void) | 513 | static void __init ek_board_init(void) |
| 464 | { | 514 | { |
| 465 | /* Serial */ | 515 | /* Serial */ |
| @@ -481,6 +531,9 @@ static void __init ek_board_init(void) | |||
| 481 | at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); | 531 | at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); |
| 482 | /* Touchscreen */ | 532 | /* Touchscreen */ |
| 483 | ek_add_device_ts(); | 533 | ek_add_device_ts(); |
| 534 | /* SSC (to AT73C213) */ | ||
| 535 | at73c213_set_clk(&at73c213_data); | ||
| 536 | at91_add_device_ssc(AT91SAM9261_ID_SSC1, ATMEL_SSC_TX); | ||
| 484 | #else | 537 | #else |
| 485 | /* MMC */ | 538 | /* MMC */ |
| 486 | at91_add_device_mmc(0, &ek_mmc_data); | 539 | at91_add_device_mmc(0, &ek_mmc_data); |
| @@ -489,6 +542,8 @@ static void __init ek_board_init(void) | |||
| 489 | at91_add_device_lcdc(&ek_lcdc_data); | 542 | at91_add_device_lcdc(&ek_lcdc_data); |
| 490 | /* Push Buttons */ | 543 | /* Push Buttons */ |
| 491 | ek_add_device_buttons(); | 544 | ek_add_device_buttons(); |
| 545 | /* LEDs */ | ||
| 546 | at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); | ||
| 492 | } | 547 | } |
| 493 | 548 | ||
| 494 | MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK") | 549 | MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK") |
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index bf103b24c937..b4cd5d0ed597 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c | |||
| @@ -43,29 +43,24 @@ | |||
| 43 | 43 | ||
| 44 | #include <asm/arch/board.h> | 44 | #include <asm/arch/board.h> |
| 45 | #include <asm/arch/gpio.h> | 45 | #include <asm/arch/gpio.h> |
| 46 | #include <asm/arch/at91sam926x_mc.h> | 46 | #include <asm/arch/at91sam9_smc.h> |
| 47 | 47 | ||
| 48 | #include "generic.h" | 48 | #include "generic.h" |
| 49 | 49 | ||
| 50 | 50 | ||
| 51 | /* | ||
| 52 | * Serial port configuration. | ||
| 53 | * 0 .. 2 = USART0 .. USART2 | ||
| 54 | * 3 = DBGU | ||
| 55 | */ | ||
| 56 | static struct at91_uart_config __initdata ek_uart_config = { | ||
| 57 | .console_tty = 0, /* ttyS0 */ | ||
| 58 | .nr_tty = 2, | ||
| 59 | .tty_map = { 3, 0, -1, -1, } /* ttyS0, ..., ttyS3 */ | ||
| 60 | }; | ||
| 61 | |||
| 62 | static void __init ek_map_io(void) | 51 | static void __init ek_map_io(void) |
| 63 | { | 52 | { |
| 64 | /* Initialize processor: 16.367 MHz crystal */ | 53 | /* Initialize processor: 16.367 MHz crystal */ |
| 65 | at91sam9263_initialize(16367660); | 54 | at91sam9263_initialize(16367660); |
| 66 | 55 | ||
| 67 | /* Setup the serial ports and console */ | 56 | /* DGBU on ttyS0. (Rx & Tx only) */ |
| 68 | at91_init_serial(&ek_uart_config); | 57 | at91_register_uart(0, 0, 0); |
| 58 | |||
| 59 | /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ | ||
| 60 | at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); | ||
| 61 | |||
| 62 | /* set serial console to ttyS0 (ie, DBGU) */ | ||
| 63 | at91_set_serial_console(0); | ||
| 69 | } | 64 | } |
| 70 | 65 | ||
| 71 | static void __init ek_init_irq(void) | 66 | static void __init ek_init_irq(void) |
| @@ -341,7 +336,7 @@ static struct gpio_led ek_leds[] = { | |||
| 341 | .name = "ds3", | 336 | .name = "ds3", |
| 342 | .gpio = AT91_PIN_PB7, | 337 | .gpio = AT91_PIN_PB7, |
| 343 | .default_trigger = "heartbeat", | 338 | .default_trigger = "heartbeat", |
| 344 | }, | 339 | } |
| 345 | }; | 340 | }; |
| 346 | 341 | ||
| 347 | 342 | ||
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c index bc0546d7245f..ffc0597aee8d 100644 --- a/arch/arm/mach-at91/board-sam9rlek.c +++ b/arch/arm/mach-at91/board-sam9rlek.c | |||
| @@ -29,29 +29,24 @@ | |||
| 29 | 29 | ||
| 30 | #include <asm/arch/board.h> | 30 | #include <asm/arch/board.h> |
| 31 | #include <asm/arch/gpio.h> | 31 | #include <asm/arch/gpio.h> |
| 32 | #include <asm/arch/at91sam926x_mc.h> | 32 | #include <asm/arch/at91sam9_smc.h> |
| 33 | 33 | ||
| 34 | #include "generic.h" | 34 | #include "generic.h" |
| 35 | 35 | ||
| 36 | 36 | ||
| 37 | /* | ||
| 38 | * Serial port configuration. | ||
| 39 | * 0 .. 3 = USART0 .. USART3 | ||
| 40 | * 4 = DBGU | ||
| 41 | */ | ||
| 42 | static struct at91_uart_config __initdata ek_uart_config = { | ||
| 43 | .console_tty = 0, /* ttyS0 */ | ||
| 44 | .nr_tty = 2, | ||
| 45 | .tty_map = { 4, 0, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ | ||
| 46 | }; | ||
| 47 | |||
| 48 | static void __init ek_map_io(void) | 37 | static void __init ek_map_io(void) |
| 49 | { | 38 | { |
| 50 | /* Initialize processor: 12.000 MHz crystal */ | 39 | /* Initialize processor: 12.000 MHz crystal */ |
| 51 | at91sam9rl_initialize(12000000); | 40 | at91sam9rl_initialize(12000000); |
| 52 | 41 | ||
| 53 | /* Setup the serial ports and console */ | 42 | /* DGBU on ttyS0. (Rx & Tx only) */ |
| 54 | at91_init_serial(&ek_uart_config); | 43 | at91_register_uart(0, 0, 0); |
| 44 | |||
| 45 | /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */ | ||
| 46 | at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); | ||
| 47 | |||
| 48 | /* set serial console to ttyS0 (ie, DBGU) */ | ||
| 49 | at91_set_serial_console(0); | ||
| 55 | } | 50 | } |
| 56 | 51 | ||
| 57 | static void __init ek_init_irq(void) | 52 | static void __init ek_init_irq(void) |
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c new file mode 100755 index 000000000000..b5717108991d --- /dev/null +++ b/arch/arm/mach-at91/board-yl-9200.c | |||
| @@ -0,0 +1,683 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-at91/board-yl-9200.c | ||
| 3 | * | ||
| 4 | * Adapted from: | ||
| 5 | *various board files in | ||
| 6 | * /arch/arm/mach-at91 | ||
| 7 | * modifications to convert to YL-9200 platform | ||
| 8 | * Copyright (C) 2007 S.Birtles | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | * | ||
| 15 | * This program is distributed in the hope that it will be useful, | ||
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 18 | * GNU General Public License for more details. | ||
| 19 | * | ||
| 20 | * You should have received a copy of the GNU General Public License | ||
| 21 | * along with this program; if not, write to the Free Software | ||
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 23 | */ | ||
| 24 | |||
| 25 | #include <linux/types.h> | ||
| 26 | #include <linux/init.h> | ||
| 27 | #include <linux/mm.h> | ||
| 28 | #include <linux/module.h> | ||
| 29 | #include <linux/platform_device.h> | ||
| 30 | #include <linux/spi/spi.h> | ||
| 31 | /*#include <linux/can_bus/candata.h>*/ | ||
| 32 | #include <linux/spi/ads7846.h> | ||
| 33 | #include <linux/mtd/physmap.h> | ||
| 34 | |||
| 35 | /*#include <sound/gpio_sounder.h>*/ | ||
| 36 | #include <asm/hardware.h> | ||
| 37 | #include <asm/setup.h> | ||
| 38 | #include <asm/mach-types.h> | ||
| 39 | #include <asm/irq.h> | ||
| 40 | |||
| 41 | #include <asm/mach/arch.h> | ||
| 42 | #include <asm/mach/map.h> | ||
| 43 | #include <asm/mach/irq.h> | ||
| 44 | |||
| 45 | #include <asm/arch/board.h> | ||
| 46 | #include <asm/arch/gpio.h> | ||
| 47 | #include <asm/arch/at91rm9200_mc.h> | ||
| 48 | #include <linux/gpio_keys.h> | ||
| 49 | #include <linux/input.h> | ||
| 50 | |||
| 51 | #include "generic.h" | ||
| 52 | #include <asm/arch/at91_pio.h> | ||
| 53 | |||
| 54 | #define YL_9200_FLASH_BASE AT91_CHIPSELECT_0 | ||
| 55 | #define YL_9200_FLASH_SIZE 0x800000 | ||
| 56 | |||
| 57 | /* | ||
| 58 | * Serial port configuration. | ||
| 59 | * 0 .. 3 = USART0 .. USART3 | ||
| 60 | * 4 = DBGU | ||
| 61 | *atmel_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a ATMEL_SERIAL | ||
| 62 | *atmel_usart.1: ttyS1 at MMIO 0xfffc0000 (irq = 6) is a ATMEL_SERIAL | ||
| 63 | *atmel_usart.2: ttyS2 at MMIO 0xfffc4000 (irq = 7) is a ATMEL_SERIAL | ||
| 64 | *atmel_usart.3: ttyS3 at MMIO 0xfffc8000 (irq = 8) is a ATMEL_SERIAL | ||
| 65 | *atmel_usart.4: ttyS4 at MMIO 0xfffcc000 (irq = 9) is a ATMEL_SERIAL | ||
| 66 | * on the YL-9200 we are sitting at the following | ||
| 67 | *ttyS0 at MMIO 0xfefff200 (irq = 1) is a AT91_SERIAL | ||
| 68 | *ttyS1 at MMIO 0xfefc4000 (irq = 7) is a AT91_SERIAL | ||
| 69 | */ | ||
| 70 | |||
| 71 | /* extern void __init yl_9200_add_device_sounder(struct gpio_sounder *sounders, int nr);*/ | ||
| 72 | |||
| 73 | static struct at91_uart_config __initdata yl_9200_uart_config = { | ||
| 74 | .console_tty = 0, /* ttyS0 */ | ||
| 75 | .nr_tty = 3, | ||
| 76 | .tty_map = { 4, 1, 0, -1, -1 } /* ttyS0, ..., ttyS4 */ | ||
| 77 | }; | ||
| 78 | |||
| 79 | static void __init yl_9200_map_io(void) | ||
| 80 | { | ||
| 81 | /* Initialize processor: 18.432 MHz crystal */ | ||
| 82 | /*Also initialises register clocks & gpio*/ | ||
| 83 | at91rm9200_initialize(18432000, AT91RM9200_PQFP); /*we have a 3 bank system*/ | ||
| 84 | |||
| 85 | /* Setup the serial ports and console */ | ||
| 86 | at91_init_serial(&yl_9200_uart_config); | ||
| 87 | |||
| 88 | /* Setup the LEDs D2=PB17,D3=PB16 */ | ||
| 89 | at91_init_leds(AT91_PIN_PB16,AT91_PIN_PB17); /*cpu-led,timer-led*/ | ||
| 90 | } | ||
| 91 | |||
| 92 | static void __init yl_9200_init_irq(void) | ||
| 93 | { | ||
| 94 | at91rm9200_init_interrupts(NULL); | ||
| 95 | } | ||
| 96 | |||
| 97 | static struct at91_eth_data __initdata yl_9200_eth_data = { | ||
| 98 | .phy_irq_pin = AT91_PIN_PB28, | ||
| 99 | .is_rmii = 1, | ||
| 100 | }; | ||
| 101 | |||
| 102 | static struct at91_usbh_data __initdata yl_9200_usbh_data = { | ||
| 103 | .ports = 1, /* this should be 1 not 2 for the Yl9200*/ | ||
| 104 | }; | ||
| 105 | |||
| 106 | static struct at91_udc_data __initdata yl_9200_udc_data = { | ||
| 107 | /*on sheet 7 Schemitic rev 1.0*/ | ||
| 108 | .pullup_pin = AT91_PIN_PC4, | ||
| 109 | .vbus_pin= AT91_PIN_PC5, | ||
| 110 | .pullup_active_low = 1, /*ACTIVE LOW!! due to PNP transistor on page 7*/ | ||
| 111 | |||
| 112 | }; | ||
| 113 | /* | ||
| 114 | static struct at91_cf_data __initdata yl_9200_cf_data = { | ||
| 115 | TODO S.BIRTLES | ||
| 116 | .det_pin = AT91_PIN_xxx, | ||
| 117 | .rst_pin = AT91_PIN_xxx, | ||
| 118 | .irq_pin = ... not connected | ||
| 119 | .vcc_pin = ... always powered | ||
| 120 | |||
| 121 | }; | ||
| 122 | */ | ||
| 123 | static struct at91_mmc_data __initdata yl_9200_mmc_data = { | ||
| 124 | .det_pin = AT91_PIN_PB9, /*THIS LOOKS CORRECT SHEET7*/ | ||
| 125 | /* .wp_pin = ... not connected SHEET7*/ | ||
| 126 | .slot_b = 0, | ||
| 127 | .wire4 = 1, | ||
| 128 | |||
| 129 | }; | ||
| 130 | |||
| 131 | /* -------------------------------------------------------------------- | ||
| 132 | * Touch screen | ||
| 133 | * -------------------------------------------------------------------- */ | ||
| 134 | #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) | ||
| 135 | static int ads7843_pendown_state(void) | ||
| 136 | { | ||
| 137 | return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */ | ||
| 138 | } | ||
| 139 | |||
| 140 | static void __init at91_init_device_ts(void) | ||
| 141 | { | ||
| 142 | /*IMPORTANT NOTE THE SPI INTERFACE IS ALREADY CONFIGURED BY XXX_DEVICES.C | ||
| 143 | THAT IS TO SAY THAT MISO,MOSI,SPCK AND CS are already configured | ||
| 144 | we only need to enable the other datapins which are: | ||
| 145 | PB10/RK1 BUSY | ||
| 146 | */ | ||
| 147 | /* Touchscreen BUSY signal , pin,use pullup ( TODO not currently used in the ADS7843/6.c driver)*/ | ||
| 148 | at91_set_gpio_input(AT91_PIN_PB10, 1); | ||
| 149 | } | ||
| 150 | |||
| 151 | #else | ||
| 152 | static void __init at91_init_device_ts(void) {} | ||
| 153 | #endif | ||
| 154 | |||
| 155 | static struct ads7846_platform_data ads_info = { | ||
| 156 | .model = 7843, | ||
| 157 | .x_min = 150, | ||
| 158 | .x_max = 3830, | ||
| 159 | .y_min = 190, | ||
| 160 | .y_max = 3830, | ||
| 161 | .vref_delay_usecs = 100, | ||
| 162 | /* for a 8" touch screen*/ | ||
| 163 | //.x_plate_ohms = 603, //= 450, S.Birtles TODO | ||
| 164 | //.y_plate_ohms = 332, //= 250, S.Birtles TODO | ||
| 165 | /*for a 10.4" touch screen*/ | ||
| 166 | //.x_plate_ohms =611, | ||
| 167 | //.y_plate_ohms =325, | ||
| 168 | |||
| 169 | .x_plate_ohms = 576, | ||
| 170 | .y_plate_ohms = 366, | ||
| 171 | // | ||
| 172 | .pressure_max = 15000, /*generally nonsense on the 7843*/ | ||
| 173 | /*number of times to send query to chip in a given run 0 equals one time (do not set to 0!! ,there is a bug in ADS 7846 code)*/ | ||
| 174 | .debounce_max = 1, | ||
| 175 | .debounce_rep = 0, | ||
| 176 | .debounce_tol = (~0), | ||
| 177 | .get_pendown_state = ads7843_pendown_state, | ||
| 178 | }; | ||
| 179 | |||
| 180 | /*static struct canbus_platform_data can_info = { | ||
| 181 | .model = 2510, | ||
| 182 | }; | ||
| 183 | */ | ||
| 184 | |||
| 185 | static struct spi_board_info yl_9200_spi_devices[] = { | ||
| 186 | /*this sticks it at: | ||
| 187 | /sys/devices/platform/atmel_spi.0/spi0.0 | ||
| 188 | /sys/bus/platform/devices/ | ||
| 189 | Documentation/spi IIRC*/ | ||
| 190 | |||
| 191 | #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) | ||
| 192 | /*(this IS correct 04-NOV-2007)*/ | ||
| 193 | { | ||
| 194 | .modalias = "ads7846", /* because the driver is called ads7846*/ | ||
| 195 | .chip_select = 0, /*THIS MUST BE AN INDEX INTO AN ARRAY OF pins */ | ||
| 196 | /*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select*/ | ||
| 197 | /*.controller_data =AT91_PIN_PA3 ,*/ | ||
| 198 | .max_speed_hz = 5000*26, /*(4700 * 26)-125000 * 26, (max sample rate @ 3V) * (cmd + data + overhead) */ | ||
| 199 | .bus_num = 0, | ||
| 200 | .platform_data = &ads_info, | ||
| 201 | .irq = AT91_PIN_PB11, | ||
| 202 | }, | ||
| 203 | #endif | ||
| 204 | /*we need to put our CAN driver data here!!*/ | ||
| 205 | /*THIS IS ALL DUMMY DATA*/ | ||
| 206 | /* { | ||
| 207 | .modalias = "mcp2510", //DUMMY for MCP2510 chip | ||
| 208 | .chip_select = 1,*/ /*THIS MUST BE AN INDEX INTO AN ARRAY OF pins */ | ||
| 209 | /*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select */ | ||
| 210 | /* .controller_data =AT91_PIN_PA4 , | ||
| 211 | .max_speed_hz = 25000 * 26, | ||
| 212 | .bus_num = 0, | ||
| 213 | .platform_data = &can_info, | ||
| 214 | .irq = AT91_PIN_PC0, | ||
| 215 | }, | ||
| 216 | */ | ||
| 217 | //max SPI chip needs to go here | ||
| 218 | }; | ||
| 219 | |||
| 220 | static struct mtd_partition __initdata yl_9200_nand_partition[] = { | ||
| 221 | { | ||
| 222 | .name = "AT91 NAND partition 1, boot", | ||
| 223 | .offset = 0, | ||
| 224 | .size = 1 * SZ_256K | ||
| 225 | }, | ||
| 226 | { | ||
| 227 | .name = "AT91 NAND partition 2, kernel", | ||
| 228 | .offset = 1 * SZ_256K, | ||
| 229 | .size = 2 * SZ_1M - 1 * SZ_256K | ||
| 230 | }, | ||
| 231 | { | ||
| 232 | .name = "AT91 NAND partition 3, filesystem", | ||
| 233 | .offset = 2 * SZ_1M, | ||
| 234 | .size = 14 * SZ_1M | ||
| 235 | }, | ||
| 236 | { | ||
| 237 | .name = "AT91 NAND partition 4, storage", | ||
| 238 | .offset = 16 * SZ_1M, | ||
| 239 | .size = 16 * SZ_1M | ||
| 240 | }, | ||
| 241 | { | ||
| 242 | .name = "AT91 NAND partition 5, ext-fs", | ||
| 243 | .offset = 32 * SZ_1M, | ||
| 244 | .size = 32 * SZ_1M | ||
| 245 | }, | ||
| 246 | }; | ||
| 247 | |||
| 248 | static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) | ||
| 249 | { | ||
| 250 | *num_partitions = ARRAY_SIZE(yl_9200_nand_partition); | ||
| 251 | return yl_9200_nand_partition; | ||
| 252 | } | ||
| 253 | |||
| 254 | static struct at91_nand_data __initdata yl_9200_nand_data = { | ||
| 255 | .ale= 6, | ||
| 256 | .cle= 7, | ||
| 257 | /*.det_pin = AT91_PIN_PCxx,*/ /*we don't have a det pin because NandFlash is fixed to board*/ | ||
| 258 | .rdy_pin = AT91_PIN_PC14, /*R/!B Sheet10*/ | ||
| 259 | .enable_pin = AT91_PIN_PC15, /*!CE Sheet10 */ | ||
| 260 | .partition_info = nand_partitions, | ||
| 261 | }; | ||
| 262 | |||
| 263 | |||
| 264 | |||
| 265 | /* | ||
| 266 | TODO S.Birtles | ||
| 267 | potentially a problem with the size above | ||
| 268 | physmap platform flash device: 00800000 at 10000000 | ||
| 269 | physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank | ||
| 270 | NOR chip too large to fit in mapping. Attempting to cope... | ||
| 271 | Intel/Sharp Extended Query Table at 0x0031 | ||
| 272 | Using buffer write method | ||
| 273 | cfi_cmdset_0001: Erase suspend on write enabled | ||
| 274 | Reducing visibility of 16384KiB chip to 8192KiB | ||
| 275 | */ | ||
| 276 | |||
| 277 | static struct mtd_partition yl_9200_flash_partitions[] = { | ||
| 278 | { | ||
| 279 | .name = "Bootloader", | ||
| 280 | .size = 0x00040000, | ||
| 281 | .offset = 0, | ||
| 282 | .mask_flags = MTD_WRITEABLE /* force read-only */ | ||
| 283 | },{ | ||
| 284 | .name = "Kernel", | ||
| 285 | .size = 0x001C0000, | ||
| 286 | .offset = 0x00040000, | ||
| 287 | },{ | ||
| 288 | .name = "Filesystem", | ||
| 289 | .size = MTDPART_SIZ_FULL, | ||
| 290 | .offset = 0x00200000 | ||
| 291 | } | ||
| 292 | |||
| 293 | }; | ||
| 294 | |||
| 295 | static struct physmap_flash_data yl_9200_flash_data = { | ||
| 296 | .width = 2, | ||
| 297 | .parts = yl_9200_flash_partitions, | ||
| 298 | .nr_parts = ARRAY_SIZE(yl_9200_flash_partitions), | ||
| 299 | }; | ||
| 300 | |||
| 301 | static struct resource yl_9200_flash_resources[] = { | ||
| 302 | { | ||
| 303 | .start = YL_9200_FLASH_BASE, | ||
| 304 | .end = YL_9200_FLASH_BASE + YL_9200_FLASH_SIZE - 1, | ||
| 305 | .flags = IORESOURCE_MEM, | ||
| 306 | } | ||
| 307 | }; | ||
| 308 | |||
| 309 | static struct platform_device yl_9200_flash = { | ||
| 310 | .name = "physmap-flash", | ||
| 311 | .id = 0, | ||
| 312 | .dev = { | ||
| 313 | .platform_data = &yl_9200_flash_data, | ||
| 314 | }, | ||
| 315 | .resource = yl_9200_flash_resources, | ||
| 316 | .num_resources = ARRAY_SIZE(yl_9200_flash_resources), | ||
| 317 | }; | ||
| 318 | |||
| 319 | |||
| 320 | static struct gpio_led yl_9200_leds[] = { | ||
| 321 | /*D2 &D3 are passed directly in via at91_init_leds*/ | ||
| 322 | { | ||
| 323 | .name = "led4", /*D4*/ | ||
| 324 | .gpio = AT91_PIN_PB15, | ||
| 325 | .active_low = 1, | ||
| 326 | .default_trigger = "heartbeat", | ||
| 327 | /*.default_trigger = "timer",*/ | ||
| 328 | }, | ||
| 329 | { | ||
| 330 | .name = "led5", /*D5*/ | ||
| 331 | .gpio = AT91_PIN_PB8, | ||
| 332 | .active_low = 1, | ||
| 333 | .default_trigger = "heartbeat", | ||
| 334 | } | ||
| 335 | }; | ||
| 336 | |||
| 337 | //static struct gpio_sounder yl_9200_sounder[] = {*/ | ||
| 338 | /*This is a simple speaker attached to a gpo line*/ | ||
| 339 | |||
| 340 | // { | ||
| 341 | // .name = "Speaker", /*LS1*/ | ||
| 342 | // .gpio = AT91_PIN_PA22, | ||
| 343 | // .active_low = 0, | ||
| 344 | // .default_trigger = "heartbeat", | ||
| 345 | /*.default_trigger = "timer",*/ | ||
| 346 | // }, | ||
| 347 | //}; | ||
| 348 | |||
| 349 | |||
| 350 | |||
| 351 | static struct i2c_board_info __initdata yl_9200_i2c_devices[] = { | ||
| 352 | { | ||
| 353 | /*TODO*/ | ||
| 354 | I2C_BOARD_INFO("CS4334", 0x00), | ||
| 355 | } | ||
| 356 | }; | ||
| 357 | |||
| 358 | |||
| 359 | /* | ||
| 360 | * GPIO Buttons | ||
| 361 | */ | ||
| 362 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | ||
| 363 | static struct gpio_keys_button yl_9200_buttons[] = { | ||
| 364 | { | ||
| 365 | .gpio = AT91_PIN_PA24, | ||
| 366 | .code = BTN_2, | ||
| 367 | .desc = "SW2", | ||
| 368 | .active_low = 1, | ||
| 369 | .wakeup = 1, | ||
| 370 | }, | ||
| 371 | { | ||
| 372 | .gpio = AT91_PIN_PB1, | ||
| 373 | .code = BTN_3, | ||
| 374 | .desc = "SW3", | ||
| 375 | .active_low = 1, | ||
| 376 | .wakeup = 1, | ||
| 377 | }, | ||
| 378 | { | ||
| 379 | .gpio = AT91_PIN_PB2, | ||
| 380 | .code = BTN_4, | ||
| 381 | .desc = "SW4", | ||
| 382 | .active_low = 1, | ||
| 383 | .wakeup = 1, | ||
| 384 | }, | ||
| 385 | { | ||
| 386 | .gpio = AT91_PIN_PB6, | ||
| 387 | .code = BTN_5, | ||
| 388 | .desc = "SW5", | ||
| 389 | .active_low = 1, | ||
| 390 | .wakeup = 1, | ||
| 391 | }, | ||
| 392 | |||
| 393 | }; | ||
| 394 | |||
| 395 | static struct gpio_keys_platform_data yl_9200_button_data = { | ||
| 396 | .buttons = yl_9200_buttons, | ||
| 397 | .nbuttons = ARRAY_SIZE(yl_9200_buttons), | ||
| 398 | }; | ||
| 399 | |||
| 400 | static struct platform_device yl_9200_button_device = { | ||
| 401 | .name = "gpio-keys", | ||
| 402 | .id = -1, | ||
| 403 | .num_resources = 0, | ||
| 404 | .dev = { | ||
| 405 | .platform_data = &yl_9200_button_data, | ||
| 406 | } | ||
| 407 | }; | ||
| 408 | |||
| 409 | static void __init yl_9200_add_device_buttons(void) | ||
| 410 | { | ||
| 411 | //SW2 | ||
| 412 | at91_set_gpio_input(AT91_PIN_PA24, 0); | ||
| 413 | at91_set_deglitch(AT91_PIN_PA24, 1); | ||
| 414 | |||
| 415 | //SW3 | ||
| 416 | at91_set_gpio_input(AT91_PIN_PB1, 0); | ||
| 417 | at91_set_deglitch(AT91_PIN_PB1, 1); | ||
| 418 | //SW4 | ||
| 419 | at91_set_gpio_input(AT91_PIN_PB2, 0); | ||
| 420 | at91_set_deglitch(AT91_PIN_PB2, 1); | ||
| 421 | |||
| 422 | //SW5 | ||
| 423 | at91_set_gpio_input(AT91_PIN_PB6, 0); | ||
| 424 | at91_set_deglitch(AT91_PIN_PB6, 1); | ||
| 425 | |||
| 426 | |||
| 427 | at91_set_gpio_output(AT91_PIN_PB7, 1); /* #TURN BUTTONS ON, SHEET 5 of schematics */ | ||
| 428 | platform_device_register(&yl_9200_button_device); | ||
| 429 | } | ||
| 430 | #else | ||
| 431 | static void __init yl_9200_add_device_buttons(void) {} | ||
| 432 | #endif | ||
| 433 | |||
| 434 | #if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE) | ||
| 435 | #include <video/s1d13xxxfb.h> | ||
| 436 | |||
| 437 | /* EPSON S1D13806 FB (discontinued chip)*/ | ||
| 438 | /* EPSON S1D13506 FB */ | ||
| 439 | |||
| 440 | #define AT91_FB_REG_BASE 0x80000000L | ||
| 441 | #define AT91_FB_REG_SIZE 0x200 | ||
| 442 | #define AT91_FB_VMEM_BASE 0x80200000L | ||
| 443 | #define AT91_FB_VMEM_SIZE 0x200000L | ||
| 444 | |||
| 445 | /*#define S1D_DISPLAY_WIDTH 640*/ | ||
| 446 | /*#define S1D_DISPLAY_HEIGHT 480*/ | ||
| 447 | |||
| 448 | |||
| 449 | static void __init yl_9200_init_video(void) | ||
| 450 | { | ||
| 451 | at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6); | ||
| 452 | at91_sys_write(AT91_PIOC + PIO_BSR,0); | ||
| 453 | at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6); | ||
| 454 | |||
| 455 | at91_sys_write( AT91_SMC_CSR(2), | ||
| 456 | AT91_SMC_NWS_(0x4) | | ||
| 457 | AT91_SMC_WSEN | | ||
| 458 | AT91_SMC_TDF_(0x100) | | ||
| 459 | AT91_SMC_DBW | ||
| 460 | ); | ||
| 461 | |||
| 462 | |||
| 463 | |||
| 464 | } | ||
| 465 | |||
| 466 | |||
| 467 | static struct s1d13xxxfb_regval yl_9200_s1dfb_initregs[] = | ||
| 468 | { | ||
| 469 | {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/ | ||
| 470 | {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/ | ||
| 471 | {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/ | ||
| 472 | {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/ | ||
| 473 | {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/ | ||
| 474 | {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/ | ||
| 475 | {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/ | ||
| 476 | {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/ | ||
| 477 | {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/ | ||
| 478 | {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/ | ||
| 479 | {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/ | ||
| 480 | {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/ | ||
| 481 | {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/ | ||
| 482 | {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/ | ||
| 483 | {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/ | ||
| 484 | {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/ | ||
| 485 | {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/ | ||
| 486 | {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/ | ||
| 487 | {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/ | ||
| 488 | {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/ | ||
| 489 | {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/ | ||
| 490 | {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/ | ||
| 491 | {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/ | ||
| 492 | {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/ | ||
| 493 | {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/ | ||
| 494 | {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/ | ||
| 495 | {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/ | ||
| 496 | {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/ | ||
| 497 | {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/ | ||
| 498 | {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/ | ||
| 499 | {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/ | ||
| 500 | {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/ | ||
| 501 | {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/ | ||
| 502 | {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/ | ||
| 503 | {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/ | ||
| 504 | {S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/ | ||
| 505 | {S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/ | ||
| 506 | {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/ | ||
| 507 | {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/ | ||
| 508 | {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/ | ||
| 509 | {S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/ | ||
| 510 | {S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/ | ||
| 511 | {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/ | ||
| 512 | {S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */ | ||
| 513 | {S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/ | ||
| 514 | {S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/ | ||
| 515 | {S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/ | ||
| 516 | {S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/ | ||
| 517 | {S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/ | ||
| 518 | {S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/ | ||
| 519 | {S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/ | ||
| 520 | {S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/ | ||
| 521 | {S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/ | ||
| 522 | {S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/ | ||
| 523 | {S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/ | ||
| 524 | {S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/ | ||
| 525 | {S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/ | ||
| 526 | {S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/ | ||
| 527 | {S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/ | ||
| 528 | {S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/ | ||
| 529 | {S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/ | ||
| 530 | {S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/ | ||
| 531 | {S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/ | ||
| 532 | {S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/ | ||
| 533 | {S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/ | ||
| 534 | {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/ | ||
| 535 | {S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/ | ||
| 536 | {S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/ | ||
| 537 | {S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/ | ||
| 538 | {S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/ | ||
| 539 | {S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/ | ||
| 540 | {S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/ | ||
| 541 | {S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/ | ||
| 542 | {S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/ | ||
| 543 | {S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/ | ||
| 544 | {S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/ | ||
| 545 | {S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/ | ||
| 546 | {S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/ | ||
| 547 | {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/ | ||
| 548 | {S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/ | ||
| 549 | {S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/ | ||
| 550 | {S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/ | ||
| 551 | {S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/ | ||
| 552 | {S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/ | ||
| 553 | {S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/ | ||
| 554 | {S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/ | ||
| 555 | {S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/ | ||
| 556 | {S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/ | ||
| 557 | {S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/ | ||
| 558 | {S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/ | ||
| 559 | {S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/ | ||
| 560 | {S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/ | ||
| 561 | {S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/ | ||
| 562 | {S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/ | ||
| 563 | {S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/ | ||
| 564 | {S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/ | ||
| 565 | {S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/ | ||
| 566 | {S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/ | ||
| 567 | {S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/ | ||
| 568 | {S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/ | ||
| 569 | {S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/ | ||
| 570 | {S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/ | ||
| 571 | {S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/ | ||
| 572 | {S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/ | ||
| 573 | {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/ | ||
| 574 | }; | ||
| 575 | |||
| 576 | static u64 s1dfb_dmamask = 0xffffffffUL; | ||
| 577 | |||
| 578 | static struct s1d13xxxfb_pdata yl_9200_s1dfb_pdata = { | ||
| 579 | .initregs = yl_9200_s1dfb_initregs, | ||
| 580 | .initregssize = ARRAY_SIZE(yl_9200_s1dfb_initregs), | ||
| 581 | .platform_init_video = yl_9200_init_video, | ||
| 582 | }; | ||
| 583 | |||
| 584 | static struct resource yl_9200_s1dfb_resource[] = { | ||
| 585 | [0] = { /* video mem */ | ||
| 586 | .name = "s1d13xxxfb memory", | ||
| 587 | /* .name = "s1d13806 memory",*/ | ||
| 588 | .start = AT91_FB_VMEM_BASE, | ||
| 589 | .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1, | ||
| 590 | .flags = IORESOURCE_MEM, | ||
| 591 | }, | ||
| 592 | [1] = { /* video registers */ | ||
| 593 | .name = "s1d13xxxfb registers", | ||
| 594 | /* .name = "s1d13806 registers",*/ | ||
| 595 | .start = AT91_FB_REG_BASE, | ||
| 596 | .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1, | ||
| 597 | .flags = IORESOURCE_MEM, | ||
| 598 | }, | ||
| 599 | }; | ||
| 600 | |||
| 601 | static struct platform_device yl_9200_s1dfb_device = { | ||
| 602 | /*TODO S.Birtles , really we need the chip revision in here as well*/ | ||
| 603 | .name = "s1d13806fb", | ||
| 604 | /* .name = "s1d13506fb",*/ | ||
| 605 | .id = -1, | ||
| 606 | .dev = { | ||
| 607 | /*TODO theres a waring here!!*/ | ||
| 608 | /*WARNING: vmlinux.o(.data+0x2dbc): Section mismatch: reference to .init.text: (between 'yl_9200_s1dfb_pdata' and 's1dfb_dmamask')*/ | ||
| 609 | .dma_mask = &s1dfb_dmamask, | ||
| 610 | .coherent_dma_mask = 0xffffffff, | ||
| 611 | .platform_data = &yl_9200_s1dfb_pdata, | ||
| 612 | }, | ||
| 613 | .resource = yl_9200_s1dfb_resource, | ||
| 614 | .num_resources = ARRAY_SIZE(yl_9200_s1dfb_resource), | ||
| 615 | }; | ||
| 616 | |||
| 617 | void __init yl_9200_add_device_video(void) | ||
| 618 | { | ||
| 619 | platform_device_register(&yl_9200_s1dfb_device); | ||
| 620 | } | ||
| 621 | #else | ||
| 622 | void __init yl_9200_add_device_video(void) {} | ||
| 623 | #endif | ||
| 624 | |||
| 625 | /*this is not called first , yl_9200_map_io is called first*/ | ||
| 626 | static void __init yl_9200_board_init(void) | ||
| 627 | { | ||
| 628 | /* Serial */ | ||
| 629 | at91_add_device_serial(); | ||
| 630 | /* Ethernet */ | ||
| 631 | at91_add_device_eth(&yl_9200_eth_data); | ||
| 632 | /* USB Host */ | ||
| 633 | at91_add_device_usbh(&yl_9200_usbh_data); | ||
| 634 | /* USB Device */ | ||
| 635 | at91_add_device_udc(&yl_9200_udc_data); | ||
| 636 | /* pullup_pin it is actually active low, but this is not needed, driver sets it up */ | ||
| 637 | /*at91_set_multi_drive(yl_9200_udc_data.pullup_pin, 0);*/ | ||
| 638 | |||
| 639 | /* Compact Flash */ | ||
| 640 | /*at91_add_device_cf(&yl_9200_cf_data);*/ | ||
| 641 | |||
| 642 | /* I2C */ | ||
| 643 | at91_add_device_i2c(yl_9200_i2c_devices, ARRAY_SIZE(yl_9200_i2c_devices)); | ||
| 644 | /* SPI */ | ||
| 645 | /*TODO YL9200 we have 2 spi interfaces touch screen & CAN*/ | ||
| 646 | /* AT91_PIN_PA5, AT91_PIN_PA6 , are used on the max 485 NOT SPI*/ | ||
| 647 | |||
| 648 | /*touch screen and CAN*/ | ||
| 649 | at91_add_device_spi(yl_9200_spi_devices, ARRAY_SIZE(yl_9200_spi_devices)); | ||
| 650 | |||
| 651 | /*Basically the TS uses PB11 & PB10 , PB11 is configured by the SPI system BP10 IS NOT USED!!*/ | ||
| 652 | /* we need this incase the board is running without a touch screen*/ | ||
| 653 | #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) | ||
| 654 | at91_init_device_ts(); /*init the touch screen device*/ | ||
| 655 | #endif | ||
| 656 | /* DataFlash card */ | ||
| 657 | at91_add_device_mmc(0, &yl_9200_mmc_data); | ||
| 658 | /* NAND */ | ||
| 659 | at91_add_device_nand(&yl_9200_nand_data); | ||
| 660 | /* NOR Flash */ | ||
| 661 | platform_device_register(&yl_9200_flash); | ||
| 662 | /* LEDs. Note!! this does not include the led's we passed for the processor status */ | ||
| 663 | at91_gpio_leds(yl_9200_leds, ARRAY_SIZE(yl_9200_leds)); | ||
| 664 | /* VGA */ | ||
| 665 | /*this is self registered by including the s1d13xxx chip in the kernel build*/ | ||
| 666 | yl_9200_add_device_video(); | ||
| 667 | /* Push Buttons */ | ||
| 668 | yl_9200_add_device_buttons(); | ||
| 669 | /*TODO fixup the Sounder */ | ||
| 670 | // yl_9200_add_device_sounder(yl_9200_sounder,ARRAY_SIZE(yl_9200_sounder)); | ||
| 671 | |||
| 672 | } | ||
| 673 | |||
| 674 | MACHINE_START(YL9200, "uCdragon YL-9200") | ||
| 675 | /* Maintainer: S.Birtles*/ | ||
| 676 | .phys_io = AT91_BASE_SYS, | ||
| 677 | .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, | ||
| 678 | .boot_params = AT91_SDRAM_BASE + 0x100, | ||
| 679 | .timer = &at91rm9200_timer, | ||
| 680 | .map_io = yl_9200_map_io, | ||
| 681 | .init_irq = yl_9200_init_irq, | ||
| 682 | .init_machine = yl_9200_board_init, | ||
| 683 | MACHINE_END | ||
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index de6424e9ac02..a33dfe450726 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c | |||
| @@ -23,7 +23,6 @@ | |||
| 23 | #include <linux/delay.h> | 23 | #include <linux/delay.h> |
| 24 | #include <linux/clk.h> | 24 | #include <linux/clk.h> |
| 25 | 25 | ||
| 26 | #include <asm/semaphore.h> | ||
| 27 | #include <asm/io.h> | 26 | #include <asm/io.h> |
| 28 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
| 29 | 28 | ||
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index a67defd50438..aa863c157708 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c | |||
| @@ -26,12 +26,139 @@ | |||
| 26 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
| 27 | 27 | ||
| 28 | #include <asm/arch/at91_pmc.h> | 28 | #include <asm/arch/at91_pmc.h> |
| 29 | #include <asm/arch/at91rm9200_mc.h> | ||
| 30 | #include <asm/arch/gpio.h> | 29 | #include <asm/arch/gpio.h> |
| 31 | #include <asm/arch/cpu.h> | 30 | #include <asm/arch/cpu.h> |
| 32 | 31 | ||
| 33 | #include "generic.h" | 32 | #include "generic.h" |
| 34 | 33 | ||
| 34 | #ifdef CONFIG_ARCH_AT91RM9200 | ||
| 35 | #include <asm/arch/at91rm9200_mc.h> | ||
| 36 | |||
| 37 | /* | ||
| 38 | * The AT91RM9200 goes into self-refresh mode with this command, and will | ||
| 39 | * terminate self-refresh automatically on the next SDRAM access. | ||
| 40 | */ | ||
| 41 | #define sdram_selfrefresh_enable() at91_sys_write(AT91_SDRAMC_SRR, 1) | ||
| 42 | #define sdram_selfrefresh_disable() do {} while (0) | ||
| 43 | |||
| 44 | #elif defined(CONFIG_ARCH_AT91CAP9) | ||
| 45 | #include <asm/arch/at91cap9_ddrsdr.h> | ||
| 46 | |||
| 47 | static u32 saved_lpr; | ||
| 48 | |||
| 49 | static inline void sdram_selfrefresh_enable(void) | ||
| 50 | { | ||
| 51 | u32 lpr; | ||
| 52 | |||
| 53 | saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR); | ||
| 54 | |||
| 55 | lpr = saved_lpr & ~AT91_DDRSDRC_LPCB; | ||
| 56 | at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH); | ||
| 57 | } | ||
| 58 | |||
| 59 | #define sdram_selfrefresh_disable() at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr) | ||
| 60 | |||
| 61 | #else | ||
| 62 | #include <asm/arch/at91sam9_sdramc.h> | ||
| 63 | |||
| 64 | #ifdef CONFIG_ARCH_AT91SAM9263 | ||
| 65 | /* | ||
| 66 | * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; | ||
| 67 | * handle those cases both here and in the Suspend-To-RAM support. | ||
| 68 | */ | ||
| 69 | #define AT91_SDRAMC AT91_SDRAMC0 | ||
| 70 | #warning Assuming EB1 SDRAM controller is *NOT* used | ||
| 71 | #endif | ||
| 72 | |||
| 73 | static u32 saved_lpr; | ||
| 74 | |||
| 75 | static inline void sdram_selfrefresh_enable(void) | ||
| 76 | { | ||
| 77 | u32 lpr; | ||
| 78 | |||
| 79 | saved_lpr = at91_sys_read(AT91_SDRAMC_LPR); | ||
| 80 | |||
| 81 | lpr = saved_lpr & ~AT91_SDRAMC_LPCB; | ||
| 82 | at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH); | ||
| 83 | } | ||
| 84 | |||
| 85 | #define sdram_selfrefresh_disable() at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) | ||
| 86 | |||
| 87 | #endif | ||
| 88 | |||
| 89 | |||
| 90 | /* | ||
| 91 | * Show the reason for the previous system reset. | ||
| 92 | */ | ||
| 93 | #if defined(AT91_SHDWC) | ||
| 94 | |||
| 95 | #include <asm/arch/at91_rstc.h> | ||
| 96 | #include <asm/arch/at91_shdwc.h> | ||
| 97 | |||
| 98 | static void __init show_reset_status(void) | ||
| 99 | { | ||
| 100 | static char reset[] __initdata = "reset"; | ||
| 101 | |||
| 102 | static char general[] __initdata = "general"; | ||
| 103 | static char wakeup[] __initdata = "wakeup"; | ||
| 104 | static char watchdog[] __initdata = "watchdog"; | ||
| 105 | static char software[] __initdata = "software"; | ||
| 106 | static char user[] __initdata = "user"; | ||
| 107 | static char unknown[] __initdata = "unknown"; | ||
| 108 | |||
| 109 | static char signal[] __initdata = "signal"; | ||
| 110 | static char rtc[] __initdata = "rtc"; | ||
| 111 | static char rtt[] __initdata = "rtt"; | ||
| 112 | static char restore[] __initdata = "power-restored"; | ||
| 113 | |||
| 114 | char *reason, *r2 = reset; | ||
| 115 | u32 reset_type, wake_type; | ||
| 116 | |||
| 117 | reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP; | ||
| 118 | wake_type = at91_sys_read(AT91_SHDW_SR); | ||
| 119 | |||
| 120 | switch (reset_type) { | ||
| 121 | case AT91_RSTC_RSTTYP_GENERAL: | ||
| 122 | reason = general; | ||
| 123 | break; | ||
| 124 | case AT91_RSTC_RSTTYP_WAKEUP: | ||
| 125 | /* board-specific code enabled the wakeup sources */ | ||
| 126 | reason = wakeup; | ||
| 127 | |||
| 128 | /* "wakeup signal" */ | ||
| 129 | if (wake_type & AT91_SHDW_WAKEUP0) | ||
| 130 | r2 = signal; | ||
| 131 | else { | ||
| 132 | r2 = reason; | ||
| 133 | if (wake_type & AT91_SHDW_RTTWK) /* rtt wakeup */ | ||
| 134 | reason = rtt; | ||
| 135 | else if (wake_type & AT91_SHDW_RTCWK) /* rtc wakeup */ | ||
| 136 | reason = rtc; | ||
| 137 | else if (wake_type == 0) /* power-restored wakeup */ | ||
| 138 | reason = restore; | ||
| 139 | else /* unknown wakeup */ | ||
| 140 | reason = unknown; | ||
| 141 | } | ||
| 142 | break; | ||
| 143 | case AT91_RSTC_RSTTYP_WATCHDOG: | ||
| 144 | reason = watchdog; | ||
| 145 | break; | ||
| 146 | case AT91_RSTC_RSTTYP_SOFTWARE: | ||
| 147 | reason = software; | ||
| 148 | break; | ||
| 149 | case AT91_RSTC_RSTTYP_USER: | ||
| 150 | reason = user; | ||
| 151 | break; | ||
| 152 | default: | ||
| 153 | reason = unknown; | ||
| 154 | break; | ||
| 155 | } | ||
| 156 | pr_info("AT91: Starting after %s %s\n", reason, r2); | ||
| 157 | } | ||
| 158 | #else | ||
| 159 | static void __init show_reset_status(void) {} | ||
| 160 | #endif | ||
| 161 | |||
| 35 | 162 | ||
| 36 | static int at91_pm_valid_state(suspend_state_t state) | 163 | static int at91_pm_valid_state(suspend_state_t state) |
| 37 | { | 164 | { |
| @@ -125,6 +252,11 @@ EXPORT_SYMBOL(at91_suspend_entering_slow_clock); | |||
| 125 | 252 | ||
| 126 | static void (*slow_clock)(void); | 253 | static void (*slow_clock)(void); |
| 127 | 254 | ||
| 255 | #ifdef CONFIG_AT91_SLOW_CLOCK | ||
| 256 | extern void at91_slow_clock(void); | ||
| 257 | extern u32 at91_slow_clock_sz; | ||
| 258 | #endif | ||
| 259 | |||
| 128 | 260 | ||
| 129 | static int at91_pm_enter(suspend_state_t state) | 261 | static int at91_pm_enter(suspend_state_t state) |
| 130 | { | 262 | { |
| @@ -158,11 +290,14 @@ static int at91_pm_enter(suspend_state_t state) | |||
| 158 | * turning off the main oscillator; reverse on wakeup. | 290 | * turning off the main oscillator; reverse on wakeup. |
| 159 | */ | 291 | */ |
| 160 | if (slow_clock) { | 292 | if (slow_clock) { |
| 293 | #ifdef CONFIG_AT91_SLOW_CLOCK | ||
| 294 | /* copy slow_clock handler to SRAM, and call it */ | ||
| 295 | memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz); | ||
| 296 | #endif | ||
| 161 | slow_clock(); | 297 | slow_clock(); |
| 162 | break; | 298 | break; |
| 163 | } else { | 299 | } else { |
| 164 | /* DEVELOPMENT ONLY */ | 300 | pr_info("AT91: PM - no slow clock mode enabled ...\n"); |
| 165 | pr_info("AT91: PM - no slow clock mode yet ...\n"); | ||
| 166 | /* FALLTHROUGH leaving master clock alone */ | 301 | /* FALLTHROUGH leaving master clock alone */ |
| 167 | } | 302 | } |
| 168 | 303 | ||
| @@ -175,13 +310,15 @@ static int at91_pm_enter(suspend_state_t state) | |||
| 175 | case PM_SUSPEND_STANDBY: | 310 | case PM_SUSPEND_STANDBY: |
| 176 | /* | 311 | /* |
| 177 | * NOTE: the Wait-for-Interrupt instruction needs to be | 312 | * NOTE: the Wait-for-Interrupt instruction needs to be |
| 178 | * in icache so the SDRAM stays in self-refresh mode until | 313 | * in icache so no SDRAM accesses are needed until the |
| 179 | * the wakeup IRQ occurs. | 314 | * wakeup IRQ occurs and self-refresh is terminated. |
| 180 | */ | 315 | */ |
| 181 | asm("b 1f; .align 5; 1:"); | 316 | asm("b 1f; .align 5; 1:"); |
| 182 | asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */ | 317 | asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */ |
| 183 | at91_sys_write(AT91_SDRAMC_SRR, 1); /* self-refresh mode */ | 318 | sdram_selfrefresh_enable(); |
| 184 | /* fall though to next state */ | 319 | asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */ |
| 320 | sdram_selfrefresh_disable(); | ||
| 321 | break; | ||
| 185 | 322 | ||
| 186 | case PM_SUSPEND_ON: | 323 | case PM_SUSPEND_ON: |
| 187 | asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */ | 324 | asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */ |
| @@ -196,6 +333,7 @@ static int at91_pm_enter(suspend_state_t state) | |||
| 196 | at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR)); | 333 | at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR)); |
| 197 | 334 | ||
| 198 | error: | 335 | error: |
| 336 | sdram_selfrefresh_disable(); | ||
| 199 | target_state = PM_SUSPEND_ON; | 337 | target_state = PM_SUSPEND_ON; |
| 200 | at91_irq_resume(); | 338 | at91_irq_resume(); |
| 201 | at91_gpio_resume(); | 339 | at91_gpio_resume(); |
| @@ -220,21 +358,20 @@ static struct platform_suspend_ops at91_pm_ops ={ | |||
| 220 | 358 | ||
| 221 | static int __init at91_pm_init(void) | 359 | static int __init at91_pm_init(void) |
| 222 | { | 360 | { |
| 223 | printk("AT91: Power Management\n"); | 361 | #ifdef CONFIG_AT91_SLOW_CLOCK |
| 224 | 362 | slow_clock = (void *) (AT91_IO_VIRT_BASE - at91_slow_clock_sz); | |
| 225 | #ifdef CONFIG_AT91_PM_SLOW_CLOCK | ||
| 226 | /* REVISIT allocations of SRAM should be dynamically managed. | ||
| 227 | * FIQ handlers and other components will want SRAM/TCM too... | ||
| 228 | */ | ||
| 229 | slow_clock = (void *) (AT91_VA_BASE_SRAM + (3 * SZ_4K)); | ||
| 230 | memcpy(slow_clock, at91rm9200_slow_clock, at91rm9200_slow_clock_sz); | ||
| 231 | #endif | 363 | #endif |
| 232 | 364 | ||
| 233 | /* Disable SDRAM low-power mode. Cannot be used with self-refresh. */ | 365 | pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : "")); |
| 366 | |||
| 367 | #ifdef CONFIG_ARCH_AT91RM9200 | ||
| 368 | /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */ | ||
| 234 | at91_sys_write(AT91_SDRAMC_LPR, 0); | 369 | at91_sys_write(AT91_SDRAMC_LPR, 0); |
| 370 | #endif | ||
| 235 | 371 | ||
| 236 | suspend_set_ops(&at91_pm_ops); | 372 | suspend_set_ops(&at91_pm_ops); |
| 237 | 373 | ||
| 374 | show_reset_status(); | ||
| 238 | return 0; | 375 | return 0; |
| 239 | } | 376 | } |
| 240 | arch_initcall(at91_pm_init); | 377 | arch_initcall(at91_pm_init); |
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index 0e2b641268ad..dbaae5f746a1 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig | |||
| @@ -31,6 +31,8 @@ config ARCH_EDB7211 | |||
| 31 | bool "EDB7211" | 31 | bool "EDB7211" |
| 32 | select ISA | 32 | select ISA |
| 33 | select ARCH_DISCONTIGMEM_ENABLE | 33 | select ARCH_DISCONTIGMEM_ENABLE |
| 34 | select ARCH_SPARSEMEM_ENABLE | ||
| 35 | select ARCH_SELECT_MEMORY_MODEL | ||
| 34 | help | 36 | help |
| 35 | Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211 | 37 | Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211 |
| 36 | evaluation board. | 38 | evaluation board. |
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile index 0ecf99761feb..c1252ca9648e 100644 --- a/arch/arm/mach-ep93xx/Makefile +++ b/arch/arm/mach-ep93xx/Makefile | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Makefile for the linux kernel. | 2 | # Makefile for the linux kernel. |
| 3 | # | 3 | # |
| 4 | obj-y := core.o clock.o | 4 | obj-y := core.o clock.o gpio.o |
| 5 | obj-m := | 5 | obj-m := |
| 6 | obj-n := | 6 | obj-n := |
| 7 | obj- := | 7 | obj- := |
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 91f6a07a51d5..8bc187240542 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c | |||
| @@ -159,7 +159,7 @@ static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 }; | |||
| 159 | static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; | 159 | static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; |
| 160 | static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x5c }; | 160 | static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x5c }; |
| 161 | 161 | ||
| 162 | static void update_gpio_int_params(unsigned port) | 162 | void ep93xx_gpio_update_int_params(unsigned port) |
| 163 | { | 163 | { |
| 164 | BUG_ON(port > 2); | 164 | BUG_ON(port > 2); |
| 165 | 165 | ||
| @@ -175,98 +175,10 @@ static void update_gpio_int_params(unsigned port) | |||
| 175 | EP93XX_GPIO_REG(int_en_register_offset[port])); | 175 | EP93XX_GPIO_REG(int_en_register_offset[port])); |
| 176 | } | 176 | } |
| 177 | 177 | ||
| 178 | /* Port ordering is: A B F D E C G H */ | 178 | void ep93xx_gpio_int_mask(unsigned line) |
| 179 | static const u8 data_register_offset[8] = { | ||
| 180 | 0x00, 0x04, 0x30, 0x0c, 0x20, 0x08, 0x38, 0x40, | ||
| 181 | }; | ||
| 182 | |||
| 183 | static const u8 data_direction_register_offset[8] = { | ||
| 184 | 0x10, 0x14, 0x34, 0x1c, 0x24, 0x18, 0x3c, 0x44, | ||
| 185 | }; | ||
| 186 | |||
| 187 | #define GPIO_IN 0 | ||
| 188 | #define GPIO_OUT 1 | ||
| 189 | |||
| 190 | static void ep93xx_gpio_set_direction(unsigned line, int direction) | ||
| 191 | { | ||
| 192 | unsigned int data_direction_register; | ||
| 193 | unsigned long flags; | ||
| 194 | unsigned char v; | ||
| 195 | |||
| 196 | data_direction_register = | ||
| 197 | EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]); | ||
| 198 | |||
| 199 | local_irq_save(flags); | ||
| 200 | if (direction == GPIO_OUT) { | ||
| 201 | if (line >= 0 && line <= EP93XX_GPIO_LINE_MAX_IRQ) { | ||
| 202 | /* Port A/B/F */ | ||
| 203 | gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7)); | ||
| 204 | update_gpio_int_params(line >> 3); | ||
| 205 | } | ||
| 206 | |||
| 207 | v = __raw_readb(data_direction_register); | ||
| 208 | v |= 1 << (line & 7); | ||
| 209 | __raw_writeb(v, data_direction_register); | ||
| 210 | } else if (direction == GPIO_IN) { | ||
| 211 | v = __raw_readb(data_direction_register); | ||
| 212 | v &= ~(1 << (line & 7)); | ||
| 213 | __raw_writeb(v, data_direction_register); | ||
| 214 | } | ||
| 215 | local_irq_restore(flags); | ||
| 216 | } | ||
| 217 | |||
| 218 | int gpio_direction_input(unsigned gpio) | ||
| 219 | { | ||
| 220 | if (gpio > EP93XX_GPIO_LINE_MAX) | ||
| 221 | return -EINVAL; | ||
| 222 | |||
| 223 | ep93xx_gpio_set_direction(gpio, GPIO_IN); | ||
| 224 | |||
| 225 | return 0; | ||
| 226 | } | ||
| 227 | EXPORT_SYMBOL(gpio_direction_input); | ||
| 228 | |||
| 229 | int gpio_direction_output(unsigned gpio, int value) | ||
| 230 | { | ||
| 231 | if (gpio > EP93XX_GPIO_LINE_MAX) | ||
| 232 | return -EINVAL; | ||
| 233 | |||
| 234 | gpio_set_value(gpio, value); | ||
| 235 | ep93xx_gpio_set_direction(gpio, GPIO_OUT); | ||
| 236 | |||
| 237 | return 0; | ||
| 238 | } | ||
| 239 | EXPORT_SYMBOL(gpio_direction_output); | ||
| 240 | |||
| 241 | int gpio_get_value(unsigned gpio) | ||
| 242 | { | ||
| 243 | unsigned int data_register; | ||
| 244 | |||
| 245 | data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]); | ||
| 246 | |||
| 247 | return !!(__raw_readb(data_register) & (1 << (gpio & 7))); | ||
| 248 | } | ||
| 249 | EXPORT_SYMBOL(gpio_get_value); | ||
| 250 | |||
| 251 | void gpio_set_value(unsigned gpio, int value) | ||
| 252 | { | 179 | { |
| 253 | unsigned int data_register; | 180 | gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7)); |
| 254 | unsigned long flags; | ||
| 255 | unsigned char v; | ||
| 256 | |||
| 257 | data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]); | ||
| 258 | |||
| 259 | local_irq_save(flags); | ||
| 260 | v = __raw_readb(data_register); | ||
| 261 | if (value) | ||
| 262 | v |= 1 << (gpio & 7); | ||
| 263 | else | ||
| 264 | v &= ~(1 << (gpio & 7)); | ||
| 265 | __raw_writeb(v, data_register); | ||
| 266 | local_irq_restore(flags); | ||
| 267 | } | 181 | } |
| 268 | EXPORT_SYMBOL(gpio_set_value); | ||
| 269 | |||
| 270 | 182 | ||
| 271 | /************************************************************************* | 183 | /************************************************************************* |
| 272 | * EP93xx IRQ handling | 184 | * EP93xx IRQ handling |
| @@ -316,7 +228,7 @@ static void ep93xx_gpio_irq_ack(unsigned int irq) | |||
| 316 | 228 | ||
| 317 | if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { | 229 | if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { |
| 318 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ | 230 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ |
| 319 | update_gpio_int_params(port); | 231 | ep93xx_gpio_update_int_params(port); |
| 320 | } | 232 | } |
| 321 | 233 | ||
| 322 | __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); | 234 | __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); |
| @@ -332,7 +244,7 @@ static void ep93xx_gpio_irq_mask_ack(unsigned int irq) | |||
| 332 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ | 244 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ |
| 333 | 245 | ||
| 334 | gpio_int_unmasked[port] &= ~port_mask; | 246 | gpio_int_unmasked[port] &= ~port_mask; |
| 335 | update_gpio_int_params(port); | 247 | ep93xx_gpio_update_int_params(port); |
| 336 | 248 | ||
| 337 | __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); | 249 | __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); |
| 338 | } | 250 | } |
| @@ -343,7 +255,7 @@ static void ep93xx_gpio_irq_mask(unsigned int irq) | |||
| 343 | int port = line >> 3; | 255 | int port = line >> 3; |
| 344 | 256 | ||
| 345 | gpio_int_unmasked[port] &= ~(1 << (line & 7)); | 257 | gpio_int_unmasked[port] &= ~(1 << (line & 7)); |
| 346 | update_gpio_int_params(port); | 258 | ep93xx_gpio_update_int_params(port); |
| 347 | } | 259 | } |
| 348 | 260 | ||
| 349 | static void ep93xx_gpio_irq_unmask(unsigned int irq) | 261 | static void ep93xx_gpio_irq_unmask(unsigned int irq) |
| @@ -352,7 +264,7 @@ static void ep93xx_gpio_irq_unmask(unsigned int irq) | |||
| 352 | int port = line >> 3; | 264 | int port = line >> 3; |
| 353 | 265 | ||
| 354 | gpio_int_unmasked[port] |= 1 << (line & 7); | 266 | gpio_int_unmasked[port] |= 1 << (line & 7); |
| 355 | update_gpio_int_params(port); | 267 | ep93xx_gpio_update_int_params(port); |
| 356 | } | 268 | } |
| 357 | 269 | ||
| 358 | 270 | ||
| @@ -368,7 +280,7 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type) | |||
| 368 | const int port = gpio >> 3; | 280 | const int port = gpio >> 3; |
| 369 | const int port_mask = 1 << (gpio & 7); | 281 | const int port_mask = 1 << (gpio & 7); |
| 370 | 282 | ||
| 371 | ep93xx_gpio_set_direction(gpio, GPIO_IN); | 283 | gpio_direction_output(gpio, gpio_get_value(gpio)); |
| 372 | 284 | ||
| 373 | switch (type) { | 285 | switch (type) { |
| 374 | case IRQT_RISING: | 286 | case IRQT_RISING: |
| @@ -411,7 +323,7 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type) | |||
| 411 | desc->status &= ~IRQ_TYPE_SENSE_MASK; | 323 | desc->status &= ~IRQ_TYPE_SENSE_MASK; |
| 412 | desc->status |= type & IRQ_TYPE_SENSE_MASK; | 324 | desc->status |= type & IRQ_TYPE_SENSE_MASK; |
| 413 | 325 | ||
| 414 | update_gpio_int_params(port); | 326 | ep93xx_gpio_update_int_params(port); |
| 415 | 327 | ||
| 416 | return 0; | 328 | return 0; |
| 417 | } | 329 | } |
| @@ -549,6 +461,7 @@ static struct platform_device ep93xx_ohci_device = { | |||
| 549 | .resource = ep93xx_ohci_resources, | 461 | .resource = ep93xx_ohci_resources, |
| 550 | }; | 462 | }; |
| 551 | 463 | ||
| 464 | extern void ep93xx_gpio_init(void); | ||
| 552 | 465 | ||
| 553 | void __init ep93xx_init_devices(void) | 466 | void __init ep93xx_init_devices(void) |
| 554 | { | 467 | { |
| @@ -562,6 +475,8 @@ void __init ep93xx_init_devices(void) | |||
| 562 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); | 475 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); |
| 563 | __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG); | 476 | __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG); |
| 564 | 477 | ||
| 478 | ep93xx_gpio_init(); | ||
| 479 | |||
| 565 | amba_device_register(&uart1_device, &iomem_resource); | 480 | amba_device_register(&uart1_device, &iomem_resource); |
| 566 | amba_device_register(&uart2_device, &iomem_resource); | 481 | amba_device_register(&uart2_device, &iomem_resource); |
| 567 | amba_device_register(&uart3_device, &iomem_resource); | 482 | amba_device_register(&uart3_device, &iomem_resource); |
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c new file mode 100644 index 000000000000..dc2e4c00d989 --- /dev/null +++ b/arch/arm/mach-ep93xx/gpio.c | |||
| @@ -0,0 +1,158 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-ep93xx/gpio.c | ||
| 3 | * | ||
| 4 | * Generic EP93xx GPIO handling | ||
| 5 | * | ||
| 6 | * Copyright (c) 2008 Ryan Mallon <ryan@bluewatersys.com> | ||
| 7 | * | ||
| 8 | * Based on code originally from: | ||
| 9 | * linux/arch/arm/mach-ep93xx/core.c | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/module.h> | ||
| 18 | #include <linux/seq_file.h> | ||
| 19 | |||
| 20 | #include <asm/arch/ep93xx-regs.h> | ||
| 21 | #include <asm/io.h> | ||
| 22 | #include <asm/gpio.h> | ||
| 23 | |||
| 24 | struct ep93xx_gpio_chip { | ||
| 25 | struct gpio_chip chip; | ||
| 26 | |||
| 27 | unsigned int data_reg; | ||
| 28 | unsigned int data_dir_reg; | ||
| 29 | }; | ||
| 30 | |||
| 31 | #define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip) | ||
| 32 | |||
| 33 | /* From core.c */ | ||
| 34 | extern void ep93xx_gpio_int_mask(unsigned line); | ||
| 35 | extern void ep93xx_gpio_update_int_params(unsigned port); | ||
| 36 | |||
| 37 | static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | ||
| 38 | { | ||
| 39 | struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); | ||
| 40 | unsigned long flags; | ||
| 41 | u8 v; | ||
| 42 | |||
| 43 | local_irq_save(flags); | ||
| 44 | v = __raw_readb(ep93xx_chip->data_dir_reg); | ||
| 45 | v &= ~(1 << offset); | ||
| 46 | __raw_writeb(v, ep93xx_chip->data_dir_reg); | ||
| 47 | local_irq_restore(flags); | ||
| 48 | |||
| 49 | return 0; | ||
| 50 | } | ||
| 51 | |||
| 52 | static int ep93xx_gpio_direction_output(struct gpio_chip *chip, | ||
| 53 | unsigned offset, int val) | ||
| 54 | { | ||
| 55 | struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); | ||
| 56 | unsigned long flags; | ||
| 57 | int line; | ||
| 58 | u8 v; | ||
| 59 | |||
| 60 | local_irq_save(flags); | ||
| 61 | |||
| 62 | /* Set the value */ | ||
| 63 | v = __raw_readb(ep93xx_chip->data_reg); | ||
| 64 | if (val) | ||
| 65 | v |= (1 << offset); | ||
| 66 | else | ||
| 67 | v &= ~(1 << offset); | ||
| 68 | __raw_writeb(v, ep93xx_chip->data_reg); | ||
| 69 | |||
| 70 | /* Drive as an output */ | ||
| 71 | line = chip->base + offset; | ||
| 72 | if (line <= EP93XX_GPIO_LINE_MAX_IRQ) { | ||
| 73 | /* Ports A/B/F */ | ||
| 74 | ep93xx_gpio_int_mask(line); | ||
| 75 | ep93xx_gpio_update_int_params(line >> 3); | ||
| 76 | } | ||
| 77 | |||
| 78 | v = __raw_readb(ep93xx_chip->data_dir_reg); | ||
| 79 | v |= (1 << offset); | ||
| 80 | __raw_writeb(v, ep93xx_chip->data_dir_reg); | ||
| 81 | |||
| 82 | local_irq_restore(flags); | ||
| 83 | |||
| 84 | return 0; | ||
| 85 | } | ||
| 86 | |||
| 87 | static int ep93xx_gpio_get(struct gpio_chip *chip, unsigned offset) | ||
| 88 | { | ||
| 89 | struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); | ||
| 90 | |||
| 91 | return !!(__raw_readb(ep93xx_chip->data_reg) & (1 << offset)); | ||
| 92 | } | ||
| 93 | |||
| 94 | static void ep93xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | ||
| 95 | { | ||
| 96 | struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); | ||
| 97 | unsigned long flags; | ||
| 98 | u8 v; | ||
| 99 | |||
| 100 | local_irq_save(flags); | ||
| 101 | v = __raw_readb(ep93xx_chip->data_reg); | ||
| 102 | if (val) | ||
| 103 | v |= (1 << offset); | ||
| 104 | else | ||
| 105 | v &= ~(1 << offset); | ||
| 106 | __raw_writeb(v, ep93xx_chip->data_reg); | ||
| 107 | local_irq_restore(flags); | ||
| 108 | } | ||
| 109 | |||
| 110 | static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | ||
| 111 | { | ||
| 112 | struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); | ||
| 113 | u8 data_reg, data_dir_reg; | ||
| 114 | int i; | ||
| 115 | |||
| 116 | data_reg = __raw_readb(ep93xx_chip->data_reg); | ||
| 117 | data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg); | ||
| 118 | |||
| 119 | for (i = 0; i < chip->ngpio; i++) | ||
| 120 | seq_printf(s, "GPIO %s%d: %s %s\n", chip->label, i, | ||
| 121 | (data_reg & (1 << i)) ? "set" : "clear", | ||
| 122 | (data_dir_reg & (1 << i)) ? "out" : "in"); | ||
| 123 | } | ||
| 124 | |||
| 125 | #define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \ | ||
| 126 | { \ | ||
| 127 | .chip = { \ | ||
| 128 | .label = name, \ | ||
| 129 | .direction_input = ep93xx_gpio_direction_input, \ | ||
| 130 | .direction_output = ep93xx_gpio_direction_output, \ | ||
| 131 | .get = ep93xx_gpio_get, \ | ||
| 132 | .set = ep93xx_gpio_set, \ | ||
| 133 | .dbg_show = ep93xx_gpio_dbg_show, \ | ||
| 134 | .base = base_gpio, \ | ||
| 135 | .ngpio = 8, \ | ||
| 136 | }, \ | ||
| 137 | .data_reg = EP93XX_GPIO_REG(dr), \ | ||
| 138 | .data_dir_reg = EP93XX_GPIO_REG(ddr), \ | ||
| 139 | } | ||
| 140 | |||
| 141 | static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = { | ||
| 142 | EP93XX_GPIO_BANK("A", 0x00, 0x10, 0), | ||
| 143 | EP93XX_GPIO_BANK("B", 0x04, 0x14, 8), | ||
| 144 | EP93XX_GPIO_BANK("C", 0x30, 0x34, 40), | ||
| 145 | EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24), | ||
| 146 | EP93XX_GPIO_BANK("E", 0x20, 0x24, 32), | ||
| 147 | EP93XX_GPIO_BANK("F", 0x08, 0x18, 16), | ||
| 148 | EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48), | ||
| 149 | EP93XX_GPIO_BANK("H", 0x40, 0x44, 56), | ||
| 150 | }; | ||
| 151 | |||
| 152 | void __init ep93xx_gpio_init(void) | ||
| 153 | { | ||
| 154 | int i; | ||
| 155 | |||
| 156 | for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) | ||
| 157 | gpiochip_add(&ep93xx_gpio_banks[i].chip); | ||
| 158 | } | ||
diff --git a/arch/arm/mach-integrator/clock.c b/arch/arm/mach-integrator/clock.c index 95a1e263f7fa..8d761fdd2ecd 100644 --- a/arch/arm/mach-integrator/clock.c +++ b/arch/arm/mach-integrator/clock.c | |||
| @@ -17,7 +17,6 @@ | |||
| 17 | #include <linux/clk.h> | 17 | #include <linux/clk.h> |
| 18 | #include <linux/mutex.h> | 18 | #include <linux/mutex.h> |
| 19 | 19 | ||
| 20 | #include <asm/semaphore.h> | ||
| 21 | #include <asm/hardware/icst525.h> | 20 | #include <asm/hardware/icst525.h> |
| 22 | 21 | ||
| 23 | #include "clock.h" | 22 | #include "clock.h" |
diff --git a/arch/arm/mach-integrator/time.c b/arch/arm/mach-integrator/time.c index 5278f589fcee..8508a0db3eaf 100644 --- a/arch/arm/mach-integrator/time.c +++ b/arch/arm/mach-integrator/time.c | |||
| @@ -124,6 +124,9 @@ static int rtc_probe(struct amba_device *dev, void *id) | |||
| 124 | 124 | ||
| 125 | xtime.tv_sec = __raw_readl(rtc_base + RTC_DR); | 125 | xtime.tv_sec = __raw_readl(rtc_base + RTC_DR); |
| 126 | 126 | ||
| 127 | /* note that 'dev' is merely used for irq disambiguation; | ||
| 128 | * it is not actually referenced in the irq handler | ||
| 129 | */ | ||
| 127 | ret = request_irq(dev->irq[0], arm_rtc_interrupt, IRQF_DISABLED, | 130 | ret = request_irq(dev->irq[0], arm_rtc_interrupt, IRQF_DISABLED, |
| 128 | "rtc-pl030", dev); | 131 | "rtc-pl030", dev); |
| 129 | if (ret) | 132 | if (ret) |
diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig index dbe07c9472ed..5e8c6f7dfabb 100644 --- a/arch/arm/mach-iop32x/Kconfig +++ b/arch/arm/mach-iop32x/Kconfig | |||
| @@ -34,14 +34,6 @@ config MACH_N2100 | |||
| 34 | Say Y here if you want to run your kernel on the Thecus n2100 | 34 | Say Y here if you want to run your kernel on the Thecus n2100 |
| 35 | NAS appliance. | 35 | NAS appliance. |
| 36 | 36 | ||
| 37 | config IOP3XX_ATU | ||
| 38 | bool "Enable the PCI Controller" | ||
| 39 | default y | ||
| 40 | help | ||
| 41 | Say Y here if you want the IOP to initialize its PCI Controller. | ||
| 42 | Say N if the IOP is an add in card, the host system owns the PCI | ||
| 43 | bus in this case. | ||
| 44 | |||
| 45 | config MACH_EM7210 | 37 | config MACH_EM7210 |
| 46 | bool "Enable support for the Lanner EM7210" | 38 | bool "Enable support for the Lanner EM7210" |
| 47 | help | 39 | help |
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index 98cfa1cd6bdb..4a89823bcebb 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c | |||
| @@ -178,10 +178,9 @@ static struct hw_pci iq31244_pci __initdata = { | |||
| 178 | 178 | ||
| 179 | static int __init iq31244_pci_init(void) | 179 | static int __init iq31244_pci_init(void) |
| 180 | { | 180 | { |
| 181 | if (is_ep80219()) { | 181 | if (is_ep80219()) |
| 182 | if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) | 182 | pci_common_init(&ep80219_pci); |
| 183 | pci_common_init(&ep80219_pci); | 183 | else if (machine_is_iq31244()) { |
| 184 | } else if (machine_is_iq31244()) { | ||
| 185 | if (is_80219()) { | 184 | if (is_80219()) { |
| 186 | printk("note: iq31244 board type has been selected\n"); | 185 | printk("note: iq31244 board type has been selected\n"); |
| 187 | printk("note: to select ep80219 operation:\n"); | 186 | printk("note: to select ep80219 operation:\n"); |
| @@ -190,9 +189,7 @@ static int __init iq31244_pci_init(void) | |||
| 190 | printk("\t2/ update boot loader to pass" | 189 | printk("\t2/ update boot loader to pass" |
| 191 | " the ep80219 id: %d\n", MACH_TYPE_EP80219); | 190 | " the ep80219 id: %d\n", MACH_TYPE_EP80219); |
| 192 | } | 191 | } |
| 193 | 192 | pci_common_init(&iq31244_pci); | |
| 194 | if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) | ||
| 195 | pci_common_init(&iq31244_pci); | ||
| 196 | } | 193 | } |
| 197 | 194 | ||
| 198 | return 0; | 195 | return 0; |
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index 18ad29f213b2..1da3c911edd3 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c | |||
| @@ -106,7 +106,7 @@ static struct hw_pci iq80321_pci __initdata = { | |||
| 106 | .swizzle = pci_std_swizzle, | 106 | .swizzle = pci_std_swizzle, |
| 107 | .nr_controllers = 1, | 107 | .nr_controllers = 1, |
| 108 | .setup = iop3xx_pci_setup, | 108 | .setup = iop3xx_pci_setup, |
| 109 | .preinit = iop3xx_pci_preinit, | 109 | .preinit = iop3xx_pci_preinit_cond, |
| 110 | .scan = iop3xx_pci_scan_bus, | 110 | .scan = iop3xx_pci_scan_bus, |
| 111 | .map_irq = iq80321_pci_map_irq, | 111 | .map_irq = iq80321_pci_map_irq, |
| 112 | }; | 112 | }; |
diff --git a/arch/arm/mach-iop33x/Kconfig b/arch/arm/mach-iop33x/Kconfig index 45598e096898..9aa016bb18f9 100644 --- a/arch/arm/mach-iop33x/Kconfig +++ b/arch/arm/mach-iop33x/Kconfig | |||
| @@ -16,14 +16,6 @@ config MACH_IQ80332 | |||
| 16 | Say Y here if you want to run your kernel on the Intel IQ80332 | 16 | Say Y here if you want to run your kernel on the Intel IQ80332 |
| 17 | evaluation kit for the IOP332 chipset. | 17 | evaluation kit for the IOP332 chipset. |
| 18 | 18 | ||
| 19 | config IOP3XX_ATU | ||
| 20 | bool "Enable the PCI Controller" | ||
| 21 | default y | ||
| 22 | help | ||
| 23 | Say Y here if you want the IOP to initialize its PCI Controller. | ||
| 24 | Say N if the IOP is an add in card, the host system owns the PCI | ||
| 25 | bus in this case. | ||
| 26 | |||
| 27 | endmenu | 19 | endmenu |
| 28 | 20 | ||
| 29 | endif | 21 | endif |
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c index 433188ebff2a..de39fd778579 100644 --- a/arch/arm/mach-iop33x/iq80331.c +++ b/arch/arm/mach-iop33x/iq80331.c | |||
| @@ -89,7 +89,7 @@ static struct hw_pci iq80331_pci __initdata = { | |||
| 89 | .swizzle = pci_std_swizzle, | 89 | .swizzle = pci_std_swizzle, |
| 90 | .nr_controllers = 1, | 90 | .nr_controllers = 1, |
| 91 | .setup = iop3xx_pci_setup, | 91 | .setup = iop3xx_pci_setup, |
| 92 | .preinit = iop3xx_pci_preinit, | 92 | .preinit = iop3xx_pci_preinit_cond, |
| 93 | .scan = iop3xx_pci_scan_bus, | 93 | .scan = iop3xx_pci_scan_bus, |
| 94 | .map_irq = iq80331_pci_map_irq, | 94 | .map_irq = iq80331_pci_map_irq, |
| 95 | }; | 95 | }; |
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c index 416c09564cc6..4904fd78445f 100644 --- a/arch/arm/mach-iop33x/iq80332.c +++ b/arch/arm/mach-iop33x/iq80332.c | |||
| @@ -89,7 +89,7 @@ static struct hw_pci iq80332_pci __initdata = { | |||
| 89 | .swizzle = pci_std_swizzle, | 89 | .swizzle = pci_std_swizzle, |
| 90 | .nr_controllers = 1, | 90 | .nr_controllers = 1, |
| 91 | .setup = iop3xx_pci_setup, | 91 | .setup = iop3xx_pci_setup, |
| 92 | .preinit = iop3xx_pci_preinit, | 92 | .preinit = iop3xx_pci_preinit_cond, |
| 93 | .scan = iop3xx_pci_scan_bus, | 93 | .scan = iop3xx_pci_scan_bus, |
| 94 | .map_irq = iq80332_pci_map_irq, | 94 | .map_irq = iq80332_pci_map_irq, |
| 95 | }; | 95 | }; |
diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile index 730a3af12c98..ade42b73afbb 100644 --- a/arch/arm/mach-ks8695/Makefile +++ b/arch/arm/mach-ks8695/Makefile | |||
| @@ -11,5 +11,8 @@ obj- := | |||
| 11 | # PCI support is optional | 11 | # PCI support is optional |
| 12 | obj-$(CONFIG_PCI) += pci.o | 12 | obj-$(CONFIG_PCI) += pci.o |
| 13 | 13 | ||
| 14 | # LEDs | ||
| 15 | obj-$(CONFIG_LEDS) += leds.o | ||
| 16 | |||
| 14 | # Board-specific support | 17 | # Board-specific support |
| 15 | obj-$(CONFIG_MACH_KS8695) += board-micrel.o | 18 | obj-$(CONFIG_MACH_KS8695) += board-micrel.o |
diff --git a/arch/arm/mach-ks8695/devices.c b/arch/arm/mach-ks8695/devices.c index 386593f8ac65..3db2ec61d06f 100644 --- a/arch/arm/mach-ks8695/devices.c +++ b/arch/arm/mach-ks8695/devices.c | |||
| @@ -176,6 +176,27 @@ static void __init ks8695_add_device_watchdog(void) {} | |||
| 176 | #endif | 176 | #endif |
| 177 | 177 | ||
| 178 | 178 | ||
| 179 | /* -------------------------------------------------------------------- | ||
| 180 | * LEDs | ||
| 181 | * -------------------------------------------------------------------- */ | ||
| 182 | |||
| 183 | #if defined(CONFIG_LEDS) | ||
| 184 | short ks8695_leds_cpu = -1; | ||
| 185 | short ks8695_leds_timer = -1; | ||
| 186 | |||
| 187 | void __init ks8695_init_leds(u8 cpu_led, u8 timer_led) | ||
| 188 | { | ||
| 189 | /* Enable GPIO to access the LEDs */ | ||
| 190 | gpio_direction_output(cpu_led, 1); | ||
| 191 | gpio_direction_output(timer_led, 1); | ||
| 192 | |||
| 193 | ks8695_leds_cpu = cpu_led; | ||
| 194 | ks8695_leds_timer = timer_led; | ||
| 195 | } | ||
| 196 | #else | ||
| 197 | void __init ks8695_init_leds(u8 cpu_led, u8 timer_led) {} | ||
| 198 | #endif | ||
| 199 | |||
| 179 | /* -------------------------------------------------------------------- */ | 200 | /* -------------------------------------------------------------------- */ |
| 180 | 201 | ||
| 181 | /* | 202 | /* |
diff --git a/arch/arm/mach-ks8695/leds.c b/arch/arm/mach-ks8695/leds.c new file mode 100644 index 000000000000..d61762ae50d8 --- /dev/null +++ b/arch/arm/mach-ks8695/leds.c | |||
| @@ -0,0 +1,94 @@ | |||
| 1 | /* | ||
| 2 | * LED driver for KS8695-based boards. | ||
| 3 | * | ||
| 4 | * Copyright (C) Andrew Victor | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/init.h> | ||
| 14 | |||
| 15 | #include <asm/mach-types.h> | ||
| 16 | #include <asm/leds.h> | ||
| 17 | #include <asm/arch/devices.h> | ||
| 18 | #include <asm/arch/gpio.h> | ||
| 19 | |||
| 20 | |||
| 21 | static inline void ks8695_led_on(unsigned int led) | ||
| 22 | { | ||
| 23 | gpio_set_value(led, 0); | ||
| 24 | } | ||
| 25 | |||
| 26 | static inline void ks8695_led_off(unsigned int led) | ||
| 27 | { | ||
| 28 | gpio_set_value(led, 1); | ||
| 29 | } | ||
| 30 | |||
| 31 | static inline void ks8695_led_toggle(unsigned int led) | ||
| 32 | { | ||
| 33 | unsigned long is_off = gpio_get_value(led); | ||
| 34 | if (is_off) | ||
| 35 | ks8695_led_on(led); | ||
| 36 | else | ||
| 37 | ks8695_led_off(led); | ||
| 38 | } | ||
| 39 | |||
| 40 | |||
| 41 | /* | ||
| 42 | * Handle LED events. | ||
| 43 | */ | ||
| 44 | static void ks8695_leds_event(led_event_t evt) | ||
| 45 | { | ||
| 46 | unsigned long flags; | ||
| 47 | |||
| 48 | local_irq_save(flags); | ||
| 49 | |||
| 50 | switch(evt) { | ||
| 51 | case led_start: /* System startup */ | ||
| 52 | ks8695_led_on(ks8695_leds_cpu); | ||
| 53 | break; | ||
| 54 | |||
| 55 | case led_stop: /* System stop / suspend */ | ||
| 56 | ks8695_led_off(ks8695_leds_cpu); | ||
| 57 | break; | ||
| 58 | |||
| 59 | #ifdef CONFIG_LEDS_TIMER | ||
| 60 | case led_timer: /* Every 50 timer ticks */ | ||
| 61 | ks8695_led_toggle(ks8695_leds_timer); | ||
| 62 | break; | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifdef CONFIG_LEDS_CPU | ||
| 66 | case led_idle_start: /* Entering idle state */ | ||
| 67 | ks8695_led_off(ks8695_leds_cpu); | ||
| 68 | break; | ||
| 69 | |||
| 70 | case led_idle_end: /* Exit idle state */ | ||
| 71 | ks8695_led_on(ks8695_leds_cpu); | ||
| 72 | break; | ||
| 73 | #endif | ||
| 74 | |||
| 75 | default: | ||
| 76 | break; | ||
| 77 | } | ||
| 78 | |||
| 79 | local_irq_restore(flags); | ||
| 80 | } | ||
| 81 | |||
| 82 | |||
| 83 | static int __init leds_init(void) | ||
| 84 | { | ||
| 85 | if ((ks8695_leds_timer == -1) || (ks8695_leds_cpu == -1)) | ||
| 86 | return -ENODEV; | ||
| 87 | |||
| 88 | leds_event = ks8695_leds_event; | ||
| 89 | |||
| 90 | leds_event(led_start); | ||
| 91 | return 0; | ||
| 92 | } | ||
| 93 | |||
| 94 | __initcall(leds_init); | ||
diff --git a/arch/arm/mach-lh7a40x/arch-kev7a400.c b/arch/arm/mach-lh7a40x/arch-kev7a400.c index 6d26661d99f6..2ef7d0097b38 100644 --- a/arch/arm/mach-lh7a40x/arch-kev7a400.c +++ b/arch/arm/mach-lh7a40x/arch-kev7a400.c | |||
| @@ -75,10 +75,9 @@ static void kev7a400_cpld_handler (unsigned int irq, struct irq_desc *desc) | |||
| 75 | { | 75 | { |
| 76 | u32 mask = CPLD_LATCHED_INTS; | 76 | u32 mask = CPLD_LATCHED_INTS; |
| 77 | irq = IRQ_KEV7A400_CPLD; | 77 | irq = IRQ_KEV7A400_CPLD; |
| 78 | for (; mask; mask >>= 1, ++irq) { | 78 | for (; mask; mask >>= 1, ++irq) |
| 79 | if (mask & 1) | 79 | if (mask & 1) |
| 80 | desc[irq].handle (irq, desc); | 80 | desc_handle_irq(irq, desc); |
| 81 | } | ||
| 82 | } | 81 | } |
| 83 | 82 | ||
| 84 | void __init lh7a40x_init_board_irq (void) | 83 | void __init lh7a40x_init_board_irq (void) |
diff --git a/arch/arm/mach-ns9xxx/Kconfig b/arch/arm/mach-ns9xxx/Kconfig index 8584ed107991..dd0cd5ac4b8b 100644 --- a/arch/arm/mach-ns9xxx/Kconfig +++ b/arch/arm/mach-ns9xxx/Kconfig | |||
| @@ -2,9 +2,26 @@ if ARCH_NS9XXX | |||
| 2 | 2 | ||
| 3 | menu "NS9xxx Implementations" | 3 | menu "NS9xxx Implementations" |
| 4 | 4 | ||
| 5 | config NS9XXX_HAVE_SERIAL8250 | ||
| 6 | bool | ||
| 7 | |||
| 8 | config PROCESSOR_NS9360 | ||
| 9 | bool | ||
| 10 | |||
| 11 | config MODULE_CC9P9360 | ||
| 12 | bool | ||
| 13 | select PROCESSOR_NS9360 | ||
| 14 | |||
| 15 | config BOARD_A9M9750DEV | ||
| 16 | select NS9XXX_HAVE_SERIAL8250 | ||
| 17 | bool | ||
| 18 | |||
| 19 | config BOARD_JSCC9P9360 | ||
| 20 | bool | ||
| 21 | |||
| 5 | config MACH_CC9P9360DEV | 22 | config MACH_CC9P9360DEV |
| 6 | bool "ConnectCore 9P 9360 on an A9M9750 Devboard" | 23 | bool "ConnectCore 9P 9360 on an A9M9750 Devboard" |
| 7 | select PROCESSOR_NS9360 | 24 | select MODULE_CC9P9360 |
| 8 | select BOARD_A9M9750DEV | 25 | select BOARD_A9M9750DEV |
| 9 | help | 26 | help |
| 10 | Say Y here if you are using the Digi ConnectCore 9P 9360 | 27 | Say Y here if you are using the Digi ConnectCore 9P 9360 |
| @@ -12,21 +29,12 @@ config MACH_CC9P9360DEV | |||
| 12 | 29 | ||
| 13 | config MACH_CC9P9360JS | 30 | config MACH_CC9P9360JS |
| 14 | bool "ConnectCore 9P 9360 on a JSCC9P9360 Devboard" | 31 | bool "ConnectCore 9P 9360 on a JSCC9P9360 Devboard" |
| 15 | select PROCESSOR_NS9360 | 32 | select MODULE_CC9P9360 |
| 16 | select BOARD_JSCC9P9360 | 33 | select BOARD_JSCC9P9360 |
| 17 | help | 34 | help |
| 18 | Say Y here if you are using the Digi ConnectCore 9P 9360 | 35 | Say Y here if you are using the Digi ConnectCore 9P 9360 |
| 19 | on an JSCC9P9360 Development Board. | 36 | on an JSCC9P9360 Development Board. |
| 20 | 37 | ||
| 21 | config PROCESSOR_NS9360 | ||
| 22 | bool | ||
| 23 | |||
| 24 | config BOARD_A9M9750DEV | ||
| 25 | bool | ||
| 26 | |||
| 27 | config BOARD_JSCC9P9360 | ||
| 28 | bool | ||
| 29 | |||
| 30 | endmenu | 38 | endmenu |
| 31 | 39 | ||
| 32 | endif | 40 | endif |
diff --git a/arch/arm/mach-ns9xxx/Makefile b/arch/arm/mach-ns9xxx/Makefile index 6fb82b855a55..41efaf9ad50b 100644 --- a/arch/arm/mach-ns9xxx/Makefile +++ b/arch/arm/mach-ns9xxx/Makefile | |||
| @@ -1,7 +1,12 @@ | |||
| 1 | obj-y := irq.o time.o generic.o gpio.o | 1 | obj-y := clock.o generic.o gpio.o irq.o |
| 2 | 2 | ||
| 3 | obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o | 3 | obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o |
| 4 | obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o | 4 | obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o |
| 5 | 5 | ||
| 6 | obj-$(CONFIG_PROCESSOR_NS9360) += gpio-ns9360.o processor-ns9360.o time-ns9360.o | ||
| 7 | |||
| 6 | obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o | 8 | obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o |
| 7 | obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o | 9 | obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o |
| 10 | |||
| 11 | # platform devices | ||
| 12 | obj-$(CONFIG_NS9XXX_HAVE_SERIAL8250) += plat-serial8250.o | ||
diff --git a/arch/arm/mach-ns9xxx/Makefile.boot b/arch/arm/mach-ns9xxx/Makefile.boot index 75ed64e90fa4..54654919229b 100644 --- a/arch/arm/mach-ns9xxx/Makefile.boot +++ b/arch/arm/mach-ns9xxx/Makefile.boot | |||
| @@ -1,2 +1,2 @@ | |||
| 1 | zreladdr-y := 0x108000 | 1 | zreladdr-y := 0x8000 |
| 2 | params_phys-y := 0x100 | 2 | params_phys-y := 0x100 |
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c index 0f65177f9e5f..a494b71c0195 100644 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c | |||
| @@ -8,15 +8,14 @@ | |||
| 8 | * under the terms of the GNU General Public License version 2 as published by | 8 | * under the terms of the GNU General Public License version 2 as published by |
| 9 | * the Free Software Foundation. | 9 | * the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | #include <linux/platform_device.h> | ||
| 12 | #include <linux/serial_8250.h> | ||
| 13 | #include <linux/irq.h> | 11 | #include <linux/irq.h> |
| 14 | 12 | ||
| 15 | #include <asm/mach/map.h> | 13 | #include <asm/mach/map.h> |
| 16 | #include <asm/gpio.h> | 14 | #include <asm/gpio.h> |
| 17 | 15 | ||
| 18 | #include <asm/arch-ns9xxx/board.h> | 16 | #include <asm/arch-ns9xxx/board.h> |
| 19 | #include <asm/arch-ns9xxx/regs-sys.h> | 17 | #include <asm/arch-ns9xxx/processor-ns9360.h> |
| 18 | #include <asm/arch-ns9xxx/regs-sys-ns9360.h> | ||
| 20 | #include <asm/arch-ns9xxx/regs-mem.h> | 19 | #include <asm/arch-ns9xxx/regs-mem.h> |
| 21 | #include <asm/arch-ns9xxx/regs-bbu.h> | 20 | #include <asm/arch-ns9xxx/regs-bbu.h> |
| 22 | #include <asm/arch-ns9xxx/regs-board-a9m9750dev.h> | 21 | #include <asm/arch-ns9xxx/regs-board-a9m9750dev.h> |
| @@ -105,9 +104,9 @@ void __init board_a9m9750dev_init_irq(void) | |||
| 105 | int i; | 104 | int i; |
| 106 | 105 | ||
| 107 | if (gpio_request(11, "board a9m9750dev extirq2") == 0) | 106 | if (gpio_request(11, "board a9m9750dev extirq2") == 0) |
| 108 | ns9xxx_gpio_configure(11, 0, 1); | 107 | ns9360_gpio_configure(11, 0, 1); |
| 109 | else | 108 | else |
| 110 | printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_EXT2\n", | 109 | printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_NS9XXX_EXT2\n", |
| 111 | __func__); | 110 | __func__); |
| 112 | 111 | ||
| 113 | for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { | 112 | for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { |
| @@ -116,69 +115,16 @@ void __init board_a9m9750dev_init_irq(void) | |||
| 116 | set_irq_flags(i, IRQF_VALID); | 115 | set_irq_flags(i, IRQF_VALID); |
| 117 | } | 116 | } |
| 118 | 117 | ||
| 119 | /* IRQ_EXT2: level sensitive + active low */ | 118 | /* IRQ_NS9XXX_EXT2: level sensitive + active low */ |
| 120 | eic = __raw_readl(SYS_EIC(2)); | 119 | eic = __raw_readl(SYS_EIC(2)); |
| 121 | REGSET(eic, SYS_EIC, PLTY, AL); | 120 | REGSET(eic, SYS_EIC, PLTY, AL); |
| 122 | REGSET(eic, SYS_EIC, LVEDG, LEVEL); | 121 | REGSET(eic, SYS_EIC, LVEDG, LEVEL); |
| 123 | __raw_writel(eic, SYS_EIC(2)); | 122 | __raw_writel(eic, SYS_EIC(2)); |
| 124 | 123 | ||
| 125 | set_irq_chained_handler(IRQ_EXT2, | 124 | set_irq_chained_handler(IRQ_NS9XXX_EXT2, |
| 126 | a9m9750dev_fpga_demux_handler); | 125 | a9m9750dev_fpga_demux_handler); |
| 127 | } | 126 | } |
| 128 | 127 | ||
| 129 | static struct plat_serial8250_port board_a9m9750dev_serial8250_port[] = { | ||
| 130 | { | ||
| 131 | .iobase = FPGA_UARTA_BASE, | ||
| 132 | .membase = (unsigned char*)FPGA_UARTA_BASE, | ||
| 133 | .mapbase = FPGA_UARTA_BASE, | ||
| 134 | .irq = IRQ_FPGA_UARTA, | ||
| 135 | .iotype = UPIO_MEM, | ||
| 136 | .uartclk = 18432000, | ||
| 137 | .regshift = 0, | ||
| 138 | .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ, | ||
| 139 | }, { | ||
| 140 | .iobase = FPGA_UARTB_BASE, | ||
| 141 | .membase = (unsigned char*)FPGA_UARTB_BASE, | ||
| 142 | .mapbase = FPGA_UARTB_BASE, | ||
| 143 | .irq = IRQ_FPGA_UARTB, | ||
| 144 | .iotype = UPIO_MEM, | ||
| 145 | .uartclk = 18432000, | ||
| 146 | .regshift = 0, | ||
| 147 | .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ, | ||
| 148 | }, { | ||
| 149 | .iobase = FPGA_UARTC_BASE, | ||
| 150 | .membase = (unsigned char*)FPGA_UARTC_BASE, | ||
| 151 | .mapbase = FPGA_UARTC_BASE, | ||
| 152 | .irq = IRQ_FPGA_UARTC, | ||
| 153 | .iotype = UPIO_MEM, | ||
| 154 | .uartclk = 18432000, | ||
| 155 | .regshift = 0, | ||
| 156 | .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ, | ||
| 157 | }, { | ||
| 158 | .iobase = FPGA_UARTD_BASE, | ||
| 159 | .membase = (unsigned char*)FPGA_UARTD_BASE, | ||
| 160 | .mapbase = FPGA_UARTD_BASE, | ||
| 161 | .irq = IRQ_FPGA_UARTD, | ||
| 162 | .iotype = UPIO_MEM, | ||
| 163 | .uartclk = 18432000, | ||
| 164 | .regshift = 0, | ||
| 165 | .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ, | ||
| 166 | }, { | ||
| 167 | /* end marker */ | ||
| 168 | }, | ||
| 169 | }; | ||
| 170 | |||
| 171 | static struct platform_device board_a9m9750dev_serial_device = { | ||
| 172 | .name = "serial8250", | ||
| 173 | .dev = { | ||
| 174 | .platform_data = board_a9m9750dev_serial8250_port, | ||
| 175 | }, | ||
| 176 | }; | ||
| 177 | |||
| 178 | static struct platform_device *board_a9m9750dev_devices[] __initdata = { | ||
| 179 | &board_a9m9750dev_serial_device, | ||
| 180 | }; | ||
| 181 | |||
| 182 | void __init board_a9m9750dev_init_machine(void) | 128 | void __init board_a9m9750dev_init_machine(void) |
| 183 | { | 129 | { |
| 184 | u32 reg; | 130 | u32 reg; |
| @@ -210,7 +156,4 @@ void __init board_a9m9750dev_init_machine(void) | |||
| 210 | __raw_writel(0x2, MEM_SMOED(0)); | 156 | __raw_writel(0x2, MEM_SMOED(0)); |
| 211 | __raw_writel(0x6, MEM_SMRD(0)); | 157 | __raw_writel(0x6, MEM_SMRD(0)); |
| 212 | __raw_writel(0x6, MEM_SMWD(0)); | 158 | __raw_writel(0x6, MEM_SMWD(0)); |
| 213 | |||
| 214 | platform_add_devices(board_a9m9750dev_devices, | ||
| 215 | ARRAY_SIZE(board_a9m9750dev_devices)); | ||
| 216 | } | 159 | } |
diff --git a/arch/arm/mach-ns9xxx/clock.c b/arch/arm/mach-ns9xxx/clock.c new file mode 100644 index 000000000000..f8639161068f --- /dev/null +++ b/arch/arm/mach-ns9xxx/clock.c | |||
| @@ -0,0 +1,215 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ns9xxx/clock.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <linux/err.h> | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/list.h> | ||
| 14 | #include <linux/clk.h> | ||
| 15 | #include <linux/string.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | |||
| 18 | #include <asm/semaphore.h> | ||
| 19 | #include "clock.h" | ||
| 20 | |||
| 21 | static LIST_HEAD(clocks); | ||
| 22 | static DEFINE_SPINLOCK(clk_lock); | ||
| 23 | |||
| 24 | struct clk *clk_get(struct device *dev, const char *id) | ||
| 25 | { | ||
| 26 | struct clk *p, *ret = NULL, *retgen = NULL; | ||
| 27 | unsigned long flags; | ||
| 28 | int idno; | ||
| 29 | |||
| 30 | if (dev == NULL || dev->bus != &platform_bus_type) | ||
| 31 | idno = -1; | ||
| 32 | else | ||
| 33 | idno = to_platform_device(dev)->id; | ||
| 34 | |||
| 35 | spin_lock_irqsave(&clk_lock, flags); | ||
| 36 | list_for_each_entry(p, &clocks, node) { | ||
| 37 | if (strcmp(id, p->name) == 0) { | ||
| 38 | if (p->id == idno) { | ||
| 39 | if (!try_module_get(p->owner)) | ||
| 40 | continue; | ||
| 41 | ret = p; | ||
| 42 | break; | ||
| 43 | } else if (p->id == -1) | ||
| 44 | /* remember match with id == -1 in case there is | ||
| 45 | * no clock for idno */ | ||
| 46 | retgen = p; | ||
| 47 | } | ||
| 48 | } | ||
| 49 | |||
| 50 | if (!ret && retgen && try_module_get(retgen->owner)) | ||
| 51 | ret = retgen; | ||
| 52 | |||
| 53 | if (ret) | ||
| 54 | ++ret->refcount; | ||
| 55 | |||
| 56 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 57 | |||
| 58 | return ret ? ret : ERR_PTR(-ENOENT); | ||
| 59 | } | ||
| 60 | EXPORT_SYMBOL(clk_get); | ||
| 61 | |||
| 62 | void clk_put(struct clk *clk) | ||
| 63 | { | ||
| 64 | module_put(clk->owner); | ||
| 65 | --clk->refcount; | ||
| 66 | } | ||
| 67 | EXPORT_SYMBOL(clk_put); | ||
| 68 | |||
| 69 | static int clk_enable_unlocked(struct clk *clk) | ||
| 70 | { | ||
| 71 | int ret = 0; | ||
| 72 | if (clk->parent) { | ||
| 73 | ret = clk_enable_unlocked(clk->parent); | ||
| 74 | if (ret) | ||
| 75 | return ret; | ||
| 76 | } | ||
| 77 | |||
| 78 | if (clk->usage++ == 0 && clk->endisable) | ||
| 79 | ret = clk->endisable(clk, 1); | ||
| 80 | |||
| 81 | return ret; | ||
| 82 | } | ||
| 83 | |||
| 84 | int clk_enable(struct clk *clk) | ||
| 85 | { | ||
| 86 | int ret; | ||
| 87 | unsigned long flags; | ||
| 88 | |||
| 89 | spin_lock_irqsave(&clk_lock, flags); | ||
| 90 | |||
| 91 | ret = clk_enable_unlocked(clk); | ||
| 92 | |||
| 93 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 94 | |||
| 95 | return ret; | ||
| 96 | } | ||
| 97 | EXPORT_SYMBOL(clk_enable); | ||
| 98 | |||
| 99 | static void clk_disable_unlocked(struct clk *clk) | ||
| 100 | { | ||
| 101 | if (--clk->usage == 0 && clk->endisable) | ||
| 102 | clk->endisable(clk, 0); | ||
| 103 | |||
| 104 | if (clk->parent) | ||
| 105 | clk_disable_unlocked(clk->parent); | ||
| 106 | } | ||
| 107 | |||
| 108 | void clk_disable(struct clk *clk) | ||
| 109 | { | ||
| 110 | unsigned long flags; | ||
| 111 | |||
| 112 | spin_lock_irqsave(&clk_lock, flags); | ||
| 113 | |||
| 114 | clk_disable_unlocked(clk); | ||
| 115 | |||
| 116 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 117 | } | ||
| 118 | EXPORT_SYMBOL(clk_disable); | ||
| 119 | |||
| 120 | unsigned long clk_get_rate(struct clk *clk) | ||
| 121 | { | ||
| 122 | if (clk->get_rate) | ||
| 123 | return clk->get_rate(clk); | ||
| 124 | |||
| 125 | if (clk->rate) | ||
| 126 | return clk->rate; | ||
| 127 | |||
| 128 | if (clk->parent) | ||
| 129 | return clk_get_rate(clk->parent); | ||
| 130 | |||
| 131 | return 0; | ||
| 132 | } | ||
| 133 | EXPORT_SYMBOL(clk_get_rate); | ||
| 134 | |||
| 135 | int clk_register(struct clk *clk) | ||
| 136 | { | ||
| 137 | unsigned long flags; | ||
| 138 | |||
| 139 | spin_lock_irqsave(&clk_lock, flags); | ||
| 140 | |||
| 141 | list_add(&clk->node, &clocks); | ||
| 142 | |||
| 143 | if (clk->parent) | ||
| 144 | ++clk->parent->refcount; | ||
| 145 | |||
| 146 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 147 | |||
| 148 | return 0; | ||
| 149 | } | ||
| 150 | |||
| 151 | int clk_unregister(struct clk *clk) | ||
| 152 | { | ||
| 153 | int ret = 0; | ||
| 154 | unsigned long flags; | ||
| 155 | |||
| 156 | spin_lock_irqsave(&clk_lock, flags); | ||
| 157 | |||
| 158 | if (clk->usage || clk->refcount) | ||
| 159 | ret = -EBUSY; | ||
| 160 | else | ||
| 161 | list_del(&clk->node); | ||
| 162 | |||
| 163 | if (clk->parent) | ||
| 164 | --clk->parent->refcount; | ||
| 165 | |||
| 166 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 167 | |||
| 168 | return ret; | ||
| 169 | } | ||
| 170 | |||
| 171 | #if defined CONFIG_DEBUG_FS | ||
| 172 | |||
| 173 | #include <linux/debugfs.h> | ||
| 174 | #include <linux/seq_file.h> | ||
| 175 | |||
| 176 | static int clk_debugfs_show(struct seq_file *s, void *null) | ||
| 177 | { | ||
| 178 | unsigned long flags; | ||
| 179 | struct clk *p; | ||
| 180 | |||
| 181 | spin_lock_irqsave(&clk_lock, flags); | ||
| 182 | |||
| 183 | list_for_each_entry(p, &clocks, node) | ||
| 184 | seq_printf(s, "%s.%d: usage=%lu refcount=%lu rate=%lu\n", | ||
| 185 | p->name, p->id, p->usage, p->refcount, | ||
| 186 | p->usage ? clk_get_rate(p) : 0); | ||
| 187 | |||
| 188 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 189 | |||
| 190 | return 0; | ||
| 191 | } | ||
| 192 | |||
| 193 | static int clk_debugfs_open(struct inode *inode, struct file *file) | ||
| 194 | { | ||
| 195 | return single_open(file, clk_debugfs_show, NULL); | ||
| 196 | } | ||
| 197 | |||
| 198 | static struct file_operations clk_debugfs_operations = { | ||
| 199 | .open = clk_debugfs_open, | ||
| 200 | .read = seq_read, | ||
| 201 | .llseek = seq_lseek, | ||
| 202 | .release = single_release, | ||
| 203 | }; | ||
| 204 | |||
| 205 | static int __init clk_debugfs_init(void) | ||
| 206 | { | ||
| 207 | struct dentry *dentry; | ||
| 208 | |||
| 209 | dentry = debugfs_create_file("clk", S_IFREG | S_IRUGO, NULL, NULL, | ||
| 210 | &clk_debugfs_operations); | ||
| 211 | return IS_ERR(dentry) ? PTR_ERR(dentry) : 0; | ||
| 212 | } | ||
| 213 | subsys_initcall(clk_debugfs_init); | ||
| 214 | |||
| 215 | #endif /* if defined CONFIG_DEBUG_FS */ | ||
diff --git a/arch/arm/mach-ns9xxx/clock.h b/arch/arm/mach-ns9xxx/clock.h new file mode 100644 index 000000000000..b86c30dd79eb --- /dev/null +++ b/arch/arm/mach-ns9xxx/clock.h | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ns9xxx/clock.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __NS9XXX_CLOCK_H | ||
| 12 | #define __NS9XXX_CLOCK_H | ||
| 13 | |||
| 14 | #include <linux/list.h> | ||
| 15 | |||
| 16 | struct clk { | ||
| 17 | struct module *owner; | ||
| 18 | const char *name; | ||
| 19 | int id; | ||
| 20 | |||
| 21 | struct clk *parent; | ||
| 22 | |||
| 23 | unsigned long rate; | ||
| 24 | int (*endisable)(struct clk *, int enable); | ||
| 25 | unsigned long (*get_rate)(struct clk *); | ||
| 26 | |||
| 27 | struct list_head node; | ||
| 28 | unsigned long refcount; | ||
| 29 | unsigned long usage; | ||
| 30 | }; | ||
| 31 | |||
| 32 | int clk_register(struct clk *clk); | ||
| 33 | int clk_unregister(struct clk *clk); | ||
| 34 | |||
| 35 | #endif /* ifndef __NS9XXX_CLOCK_H */ | ||
diff --git a/arch/arm/mach-ns9xxx/generic.c b/arch/arm/mach-ns9xxx/generic.c index d742c921e34d..1e0f467879cc 100644 --- a/arch/arm/mach-ns9xxx/generic.c +++ b/arch/arm/mach-ns9xxx/generic.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-ns9xxx/generic.c | 2 | * arch/arm/mach-ns9xxx/generic.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -11,34 +11,9 @@ | |||
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
| 13 | #include <asm/memory.h> | 13 | #include <asm/memory.h> |
| 14 | #include <asm/page.h> | ||
| 15 | #include <asm/mach-types.h> | ||
| 16 | #include <asm/mach/map.h> | ||
| 17 | #include <asm/arch-ns9xxx/regs-sys.h> | ||
| 18 | #include <asm/arch-ns9xxx/regs-mem.h> | ||
| 19 | #include <asm/arch-ns9xxx/board.h> | ||
| 20 | 14 | ||
| 21 | #include "generic.h" | 15 | #include "generic.h" |
| 22 | 16 | ||
| 23 | static struct map_desc standard_io_desc[] __initdata = { | ||
| 24 | { /* BBus */ | ||
| 25 | .virtual = io_p2v(0x90000000), | ||
| 26 | .pfn = __phys_to_pfn(0x90000000), | ||
| 27 | .length = 0x00700000, | ||
| 28 | .type = MT_DEVICE, | ||
| 29 | }, { /* AHB */ | ||
| 30 | .virtual = io_p2v(0xa0100000), | ||
| 31 | .pfn = __phys_to_pfn(0xa0100000), | ||
| 32 | .length = 0x00900000, | ||
| 33 | .type = MT_DEVICE, | ||
| 34 | }, | ||
| 35 | }; | ||
| 36 | |||
| 37 | void __init ns9xxx_map_io(void) | ||
| 38 | { | ||
| 39 | iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); | ||
| 40 | } | ||
| 41 | |||
| 42 | void __init ns9xxx_init_machine(void) | 17 | void __init ns9xxx_init_machine(void) |
| 43 | { | 18 | { |
| 44 | } | 19 | } |
diff --git a/arch/arm/mach-ns9xxx/generic.h b/arch/arm/mach-ns9xxx/generic.h index 687e291773f4..82493191aad6 100644 --- a/arch/arm/mach-ns9xxx/generic.h +++ b/arch/arm/mach-ns9xxx/generic.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-ns9xxx/generic.h | 2 | * arch/arm/mach-ns9xxx/generic.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -13,7 +13,4 @@ | |||
| 13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
| 14 | 14 | ||
| 15 | void __init ns9xxx_init_irq(void); | 15 | void __init ns9xxx_init_irq(void); |
| 16 | void __init ns9xxx_map_io(void); | ||
| 17 | void __init ns9xxx_init_machine(void); | 16 | void __init ns9xxx_init_machine(void); |
| 18 | |||
| 19 | extern struct sys_timer ns9xxx_timer; | ||
diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.c b/arch/arm/mach-ns9xxx/gpio-ns9360.c new file mode 100644 index 000000000000..cabfb879dda9 --- /dev/null +++ b/arch/arm/mach-ns9xxx/gpio-ns9360.c | |||
| @@ -0,0 +1,118 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ns9xxx/gpio-ns9360.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006,2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <linux/bug.h> | ||
| 12 | #include <linux/errno.h> | ||
| 13 | #include <linux/io.h> | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/module.h> | ||
| 16 | |||
| 17 | #include <asm/arch-ns9xxx/regs-bbu.h> | ||
| 18 | #include <asm/arch-ns9xxx/processor-ns9360.h> | ||
| 19 | |||
| 20 | #include "gpio-ns9360.h" | ||
| 21 | |||
| 22 | static inline int ns9360_valid_gpio(unsigned gpio) | ||
| 23 | { | ||
| 24 | return gpio <= 72; | ||
| 25 | } | ||
| 26 | |||
| 27 | static inline void __iomem *ns9360_gpio_get_gconfaddr(unsigned gpio) | ||
| 28 | { | ||
| 29 | if (gpio < 56) | ||
| 30 | return BBU_GCONFb1(gpio / 8); | ||
| 31 | else | ||
| 32 | /* | ||
| 33 | * this could be optimised away on | ||
| 34 | * ns9750 only builds, but it isn't ... | ||
| 35 | */ | ||
| 36 | return BBU_GCONFb2((gpio - 56) / 8); | ||
| 37 | } | ||
| 38 | |||
| 39 | static inline void __iomem *ns9360_gpio_get_gctrladdr(unsigned gpio) | ||
| 40 | { | ||
| 41 | if (gpio < 32) | ||
| 42 | return BBU_GCTRL1; | ||
| 43 | else if (gpio < 64) | ||
| 44 | return BBU_GCTRL2; | ||
| 45 | else | ||
| 46 | /* this could be optimised away on ns9750 only builds */ | ||
| 47 | return BBU_GCTRL3; | ||
| 48 | } | ||
| 49 | |||
| 50 | static inline void __iomem *ns9360_gpio_get_gstataddr(unsigned gpio) | ||
| 51 | { | ||
| 52 | if (gpio < 32) | ||
| 53 | return BBU_GSTAT1; | ||
| 54 | else if (gpio < 64) | ||
| 55 | return BBU_GSTAT2; | ||
| 56 | else | ||
| 57 | /* this could be optimised away on ns9750 only builds */ | ||
| 58 | return BBU_GSTAT3; | ||
| 59 | } | ||
| 60 | |||
| 61 | /* | ||
| 62 | * each gpio can serve for 4 different purposes [0..3]. These are called | ||
| 63 | * "functions" and passed in the parameter func. Functions 0-2 are always some | ||
| 64 | * special things, function 3 is GPIO. If func == 3 dir specifies input or | ||
| 65 | * output, and with inv you can enable an inverter (independent of func). | ||
| 66 | */ | ||
| 67 | int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func) | ||
| 68 | { | ||
| 69 | void __iomem *conf = ns9360_gpio_get_gconfaddr(gpio); | ||
| 70 | u32 confval; | ||
| 71 | |||
| 72 | confval = __raw_readl(conf); | ||
| 73 | REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir); | ||
| 74 | REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv); | ||
| 75 | REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func); | ||
| 76 | __raw_writel(confval, conf); | ||
| 77 | |||
| 78 | return 0; | ||
| 79 | } | ||
| 80 | |||
| 81 | int ns9360_gpio_configure(unsigned gpio, int inv, int func) | ||
| 82 | { | ||
| 83 | if (likely(ns9360_valid_gpio(gpio))) { | ||
| 84 | if (func == 3) { | ||
| 85 | printk(KERN_WARNING "use gpio_direction_input " | ||
| 86 | "or gpio_direction_output\n"); | ||
| 87 | return -EINVAL; | ||
| 88 | } else | ||
| 89 | return __ns9360_gpio_configure(gpio, 0, inv, func); | ||
| 90 | } else | ||
| 91 | return -EINVAL; | ||
| 92 | } | ||
| 93 | EXPORT_SYMBOL(ns9360_gpio_configure); | ||
| 94 | |||
| 95 | int ns9360_gpio_get_value(unsigned gpio) | ||
| 96 | { | ||
| 97 | void __iomem *stat = ns9360_gpio_get_gstataddr(gpio); | ||
| 98 | int ret; | ||
| 99 | |||
| 100 | ret = 1 & (__raw_readl(stat) >> (gpio & 31)); | ||
| 101 | |||
| 102 | return ret; | ||
| 103 | } | ||
| 104 | |||
| 105 | void ns9360_gpio_set_value(unsigned gpio, int value) | ||
| 106 | { | ||
| 107 | void __iomem *ctrl = ns9360_gpio_get_gctrladdr(gpio); | ||
| 108 | u32 ctrlval; | ||
| 109 | |||
| 110 | ctrlval = __raw_readl(ctrl); | ||
| 111 | |||
| 112 | if (value) | ||
| 113 | ctrlval |= 1 << (gpio & 31); | ||
| 114 | else | ||
| 115 | ctrlval &= ~(1 << (gpio & 31)); | ||
| 116 | |||
| 117 | __raw_writel(ctrlval, ctrl); | ||
| 118 | } | ||
diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.h b/arch/arm/mach-ns9xxx/gpio-ns9360.h new file mode 100644 index 000000000000..131cd1715caa --- /dev/null +++ b/arch/arm/mach-ns9xxx/gpio-ns9360.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ns9xxx/gpio-ns9360.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006,2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func); | ||
| 12 | int ns9360_gpio_get_value(unsigned gpio); | ||
| 13 | void ns9360_gpio_set_value(unsigned gpio, int value); | ||
diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c index 5286e9fc1d30..b3c963b0c8f5 100644 --- a/arch/arm/mach-ns9xxx/gpio.c +++ b/arch/arm/mach-ns9xxx/gpio.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-ns9xxx/gpio.c | 2 | * arch/arm/mach-ns9xxx/gpio.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -15,12 +15,13 @@ | |||
| 15 | 15 | ||
| 16 | #include <asm/arch-ns9xxx/gpio.h> | 16 | #include <asm/arch-ns9xxx/gpio.h> |
| 17 | #include <asm/arch-ns9xxx/processor.h> | 17 | #include <asm/arch-ns9xxx/processor.h> |
| 18 | #include <asm/arch-ns9xxx/regs-bbu.h> | 18 | #include <asm/arch-ns9xxx/processor-ns9360.h> |
| 19 | #include <asm/io.h> | ||
| 20 | #include <asm/bug.h> | 19 | #include <asm/bug.h> |
| 21 | #include <asm/types.h> | 20 | #include <asm/types.h> |
| 22 | #include <asm/bitops.h> | 21 | #include <asm/bitops.h> |
| 23 | 22 | ||
| 23 | #include "gpio-ns9360.h" | ||
| 24 | |||
| 24 | #if defined(CONFIG_PROCESSOR_NS9360) | 25 | #if defined(CONFIG_PROCESSOR_NS9360) |
| 25 | #define GPIO_MAX 72 | 26 | #define GPIO_MAX 72 |
| 26 | #elif defined(CONFIG_PROCESSOR_NS9750) | 27 | #elif defined(CONFIG_PROCESSOR_NS9750) |
| @@ -45,41 +46,10 @@ static inline int ns9xxx_valid_gpio(unsigned gpio) | |||
| 45 | return gpio <= 49; | 46 | return gpio <= 49; |
| 46 | else | 47 | else |
| 47 | #endif | 48 | #endif |
| 49 | { | ||
| 48 | BUG(); | 50 | BUG(); |
| 49 | } | 51 | return 0; |
| 50 | 52 | } | |
| 51 | static inline void __iomem *ns9xxx_gpio_get_gconfaddr(unsigned gpio) | ||
| 52 | { | ||
| 53 | if (gpio < 56) | ||
| 54 | return BBU_GCONFb1(gpio / 8); | ||
| 55 | else | ||
| 56 | /* | ||
| 57 | * this could be optimised away on | ||
| 58 | * ns9750 only builds, but it isn't ... | ||
| 59 | */ | ||
| 60 | return BBU_GCONFb2((gpio - 56) / 8); | ||
| 61 | } | ||
| 62 | |||
| 63 | static inline void __iomem *ns9xxx_gpio_get_gctrladdr(unsigned gpio) | ||
| 64 | { | ||
| 65 | if (gpio < 32) | ||
| 66 | return BBU_GCTRL1; | ||
| 67 | else if (gpio < 64) | ||
| 68 | return BBU_GCTRL2; | ||
| 69 | else | ||
| 70 | /* this could be optimised away on ns9750 only builds */ | ||
| 71 | return BBU_GCTRL3; | ||
| 72 | } | ||
| 73 | |||
| 74 | static inline void __iomem *ns9xxx_gpio_get_gstataddr(unsigned gpio) | ||
| 75 | { | ||
| 76 | if (gpio < 32) | ||
| 77 | return BBU_GSTAT1; | ||
| 78 | else if (gpio < 64) | ||
| 79 | return BBU_GSTAT2; | ||
| 80 | else | ||
| 81 | /* this could be optimised away on ns9750 only builds */ | ||
| 82 | return BBU_GSTAT3; | ||
| 83 | } | 53 | } |
| 84 | 54 | ||
| 85 | int gpio_request(unsigned gpio, const char *label) | 55 | int gpio_request(unsigned gpio, const char *label) |
| @@ -98,49 +68,24 @@ void gpio_free(unsigned gpio) | |||
| 98 | } | 68 | } |
| 99 | EXPORT_SYMBOL(gpio_free); | 69 | EXPORT_SYMBOL(gpio_free); |
| 100 | 70 | ||
| 101 | /* | 71 | int gpio_direction_input(unsigned gpio) |
| 102 | * each gpio can serve for 4 different purposes [0..3]. These are called | ||
| 103 | * "functions" and passed in the parameter func. Functions 0-2 are always some | ||
| 104 | * special things, function 3 is GPIO. If func == 3 dir specifies input or | ||
| 105 | * output, and with inv you can enable an inverter (independent of func). | ||
| 106 | */ | ||
| 107 | static int __ns9xxx_gpio_configure(unsigned gpio, int dir, int inv, int func) | ||
| 108 | { | 72 | { |
| 109 | void __iomem *conf = ns9xxx_gpio_get_gconfaddr(gpio); | 73 | if (likely(ns9xxx_valid_gpio(gpio))) { |
| 110 | u32 confval; | 74 | int ret = -EINVAL; |
| 111 | unsigned long flags; | 75 | unsigned long flags; |
| 112 | |||
| 113 | spin_lock_irqsave(&gpio_lock, flags); | ||
| 114 | |||
| 115 | confval = __raw_readl(conf); | ||
| 116 | REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir); | ||
| 117 | REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv); | ||
| 118 | REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func); | ||
| 119 | __raw_writel(confval, conf); | ||
| 120 | 76 | ||
| 121 | spin_unlock_irqrestore(&gpio_lock, flags); | 77 | spin_lock_irqsave(&gpio_lock, flags); |
| 78 | #if defined(CONFIG_PROCESSOR_NS9360) | ||
| 79 | if (processor_is_ns9360()) | ||
| 80 | ret = __ns9360_gpio_configure(gpio, 0, 0, 3); | ||
| 81 | else | ||
| 82 | #endif | ||
| 83 | BUG(); | ||
| 122 | 84 | ||
| 123 | return 0; | 85 | spin_unlock_irqrestore(&gpio_lock, flags); |
| 124 | } | ||
| 125 | 86 | ||
| 126 | int ns9xxx_gpio_configure(unsigned gpio, int inv, int func) | 87 | return ret; |
| 127 | { | ||
| 128 | if (likely(ns9xxx_valid_gpio(gpio))) { | ||
| 129 | if (func == 3) { | ||
| 130 | printk(KERN_WARNING "use gpio_direction_input " | ||
| 131 | "or gpio_direction_output\n"); | ||
| 132 | return -EINVAL; | ||
| 133 | } else | ||
| 134 | return __ns9xxx_gpio_configure(gpio, 0, inv, func); | ||
| 135 | } else | ||
| 136 | return -EINVAL; | ||
| 137 | } | ||
| 138 | EXPORT_SYMBOL(ns9xxx_gpio_configure); | ||
| 139 | 88 | ||
| 140 | int gpio_direction_input(unsigned gpio) | ||
| 141 | { | ||
| 142 | if (likely(ns9xxx_valid_gpio(gpio))) { | ||
| 143 | return __ns9xxx_gpio_configure(gpio, 0, 0, 3); | ||
| 144 | } else | 89 | } else |
| 145 | return -EINVAL; | 90 | return -EINVAL; |
| 146 | } | 91 | } |
| @@ -149,9 +94,22 @@ EXPORT_SYMBOL(gpio_direction_input); | |||
| 149 | int gpio_direction_output(unsigned gpio, int value) | 94 | int gpio_direction_output(unsigned gpio, int value) |
| 150 | { | 95 | { |
| 151 | if (likely(ns9xxx_valid_gpio(gpio))) { | 96 | if (likely(ns9xxx_valid_gpio(gpio))) { |
| 97 | int ret = -EINVAL; | ||
| 98 | unsigned long flags; | ||
| 99 | |||
| 152 | gpio_set_value(gpio, value); | 100 | gpio_set_value(gpio, value); |
| 153 | 101 | ||
| 154 | return __ns9xxx_gpio_configure(gpio, 1, 0, 3); | 102 | spin_lock_irqsave(&gpio_lock, flags); |
| 103 | #if defined(CONFIG_PROCESSOR_NS9360) | ||
| 104 | if (processor_is_ns9360()) | ||
| 105 | ret = __ns9360_gpio_configure(gpio, 1, 0, 3); | ||
| 106 | else | ||
| 107 | #endif | ||
| 108 | BUG(); | ||
| 109 | |||
| 110 | spin_unlock_irqrestore(&gpio_lock, flags); | ||
| 111 | |||
| 112 | return ret; | ||
| 155 | } else | 113 | } else |
| 156 | return -EINVAL; | 114 | return -EINVAL; |
| 157 | } | 115 | } |
| @@ -159,31 +117,28 @@ EXPORT_SYMBOL(gpio_direction_output); | |||
| 159 | 117 | ||
| 160 | int gpio_get_value(unsigned gpio) | 118 | int gpio_get_value(unsigned gpio) |
| 161 | { | 119 | { |
| 162 | void __iomem *stat = ns9xxx_gpio_get_gstataddr(gpio); | 120 | #if defined(CONFIG_PROCESSOR_NS9360) |
| 163 | int ret; | 121 | if (processor_is_ns9360()) |
| 164 | 122 | return ns9360_gpio_get_value(gpio); | |
| 165 | ret = 1 & (__raw_readl(stat) >> (gpio & 31)); | 123 | else |
| 166 | 124 | #endif | |
| 167 | return ret; | 125 | { |
| 126 | BUG(); | ||
| 127 | return -EINVAL; | ||
| 128 | } | ||
| 168 | } | 129 | } |
| 169 | EXPORT_SYMBOL(gpio_get_value); | 130 | EXPORT_SYMBOL(gpio_get_value); |
| 170 | 131 | ||
| 171 | void gpio_set_value(unsigned gpio, int value) | 132 | void gpio_set_value(unsigned gpio, int value) |
| 172 | { | 133 | { |
| 173 | void __iomem *ctrl = ns9xxx_gpio_get_gctrladdr(gpio); | ||
| 174 | u32 ctrlval; | ||
| 175 | unsigned long flags; | 134 | unsigned long flags; |
| 176 | |||
| 177 | spin_lock_irqsave(&gpio_lock, flags); | 135 | spin_lock_irqsave(&gpio_lock, flags); |
| 178 | 136 | #if defined(CONFIG_PROCESSOR_NS9360) | |
| 179 | ctrlval = __raw_readl(ctrl); | 137 | if (processor_is_ns9360()) |
| 180 | 138 | ns9360_gpio_set_value(gpio, value); | |
| 181 | if (value) | ||
| 182 | ctrlval |= 1 << (gpio & 31); | ||
| 183 | else | 139 | else |
| 184 | ctrlval &= ~(1 << (gpio & 31)); | 140 | #endif |
| 185 | 141 | BUG(); | |
| 186 | __raw_writel(ctrlval, ctrl); | ||
| 187 | 142 | ||
| 188 | spin_unlock_irqrestore(&gpio_lock, flags); | 143 | spin_unlock_irqrestore(&gpio_lock, flags); |
| 189 | } | 144 | } |
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c index 00001b874e97..36e5835e6097 100644 --- a/arch/arm/mach-ns9xxx/irq.c +++ b/arch/arm/mach-ns9xxx/irq.c | |||
| @@ -9,21 +9,27 @@ | |||
| 9 | * the Free Software Foundation. | 9 | * the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | #include <linux/interrupt.h> | 11 | #include <linux/interrupt.h> |
| 12 | #include <linux/kernel_stat.h> | ||
| 12 | #include <asm/io.h> | 13 | #include <asm/io.h> |
| 13 | #include <asm/mach/irq.h> | 14 | #include <asm/mach/irq.h> |
| 14 | #include <asm/mach-types.h> | 15 | #include <asm/mach-types.h> |
| 15 | #include <asm/arch-ns9xxx/regs-sys.h> | 16 | #include <asm/arch-ns9xxx/regs-sys-common.h> |
| 16 | #include <asm/arch-ns9xxx/irqs.h> | 17 | #include <asm/arch-ns9xxx/irqs.h> |
| 17 | #include <asm/arch-ns9xxx/board.h> | 18 | #include <asm/arch-ns9xxx/board.h> |
| 18 | 19 | ||
| 19 | #include "generic.h" | 20 | #include "generic.h" |
| 20 | 21 | ||
| 22 | /* simple interrupt prio table: prio(x) < prio(y) <=> x < y */ | ||
| 23 | #define irq2prio(i) (i) | ||
| 24 | #define prio2irq(p) (p) | ||
| 25 | |||
| 21 | static void ns9xxx_mask_irq(unsigned int irq) | 26 | static void ns9xxx_mask_irq(unsigned int irq) |
| 22 | { | 27 | { |
| 23 | /* XXX: better use cpp symbols */ | 28 | /* XXX: better use cpp symbols */ |
| 24 | u32 ic = __raw_readl(SYS_IC(irq / 4)); | 29 | int prio = irq2prio(irq); |
| 25 | ic &= ~(1 << (7 + 8 * (3 - (irq & 3)))); | 30 | u32 ic = __raw_readl(SYS_IC(prio / 4)); |
| 26 | __raw_writel(ic, SYS_IC(irq / 4)); | 31 | ic &= ~(1 << (7 + 8 * (3 - (prio & 3)))); |
| 32 | __raw_writel(ic, SYS_IC(prio / 4)); | ||
| 27 | } | 33 | } |
| 28 | 34 | ||
| 29 | static void ns9xxx_ack_irq(unsigned int irq) | 35 | static void ns9xxx_ack_irq(unsigned int irq) |
| @@ -40,9 +46,10 @@ static void ns9xxx_maskack_irq(unsigned int irq) | |||
| 40 | static void ns9xxx_unmask_irq(unsigned int irq) | 46 | static void ns9xxx_unmask_irq(unsigned int irq) |
| 41 | { | 47 | { |
| 42 | /* XXX: better use cpp symbols */ | 48 | /* XXX: better use cpp symbols */ |
| 43 | u32 ic = __raw_readl(SYS_IC(irq / 4)); | 49 | int prio = irq2prio(irq); |
| 44 | ic |= 1 << (7 + 8 * (3 - (irq & 3))); | 50 | u32 ic = __raw_readl(SYS_IC(prio / 4)); |
| 45 | __raw_writel(ic, SYS_IC(irq / 4)); | 51 | ic |= 1 << (7 + 8 * (3 - (prio & 3))); |
| 52 | __raw_writel(ic, SYS_IC(prio / 4)); | ||
| 46 | } | 53 | } |
| 47 | 54 | ||
| 48 | static struct irq_chip ns9xxx_chip = { | 55 | static struct irq_chip ns9xxx_chip = { |
| @@ -52,24 +59,61 @@ static struct irq_chip ns9xxx_chip = { | |||
| 52 | .unmask = ns9xxx_unmask_irq, | 59 | .unmask = ns9xxx_unmask_irq, |
| 53 | }; | 60 | }; |
| 54 | 61 | ||
| 62 | #if 0 | ||
| 63 | #define handle_irq handle_level_irq | ||
| 64 | #else | ||
| 65 | void handle_prio_irq(unsigned int irq, struct irq_desc *desc) | ||
| 66 | { | ||
| 67 | unsigned int cpu = smp_processor_id(); | ||
| 68 | struct irqaction *action; | ||
| 69 | irqreturn_t action_ret; | ||
| 70 | |||
| 71 | spin_lock(&desc->lock); | ||
| 72 | |||
| 73 | if (unlikely(desc->status & IRQ_INPROGRESS)) | ||
| 74 | goto out_unlock; | ||
| 75 | |||
| 76 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | ||
| 77 | kstat_cpu(cpu).irqs[irq]++; | ||
| 78 | |||
| 79 | action = desc->action; | ||
| 80 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) | ||
| 81 | goto out_unlock; | ||
| 82 | |||
| 83 | desc->status |= IRQ_INPROGRESS; | ||
| 84 | spin_unlock(&desc->lock); | ||
| 85 | |||
| 86 | action_ret = handle_IRQ_event(irq, action); | ||
| 87 | |||
| 88 | spin_lock(&desc->lock); | ||
| 89 | desc->status &= ~IRQ_INPROGRESS; | ||
| 90 | if (!(desc->status & IRQ_DISABLED) && desc->chip->ack) | ||
| 91 | desc->chip->ack(irq); | ||
| 92 | |||
| 93 | out_unlock: | ||
| 94 | spin_unlock(&desc->lock); | ||
| 95 | } | ||
| 96 | #define handle_irq handle_prio_irq | ||
| 97 | #endif | ||
| 98 | |||
| 55 | void __init ns9xxx_init_irq(void) | 99 | void __init ns9xxx_init_irq(void) |
| 56 | { | 100 | { |
| 57 | int i; | 101 | int i; |
| 58 | 102 | ||
| 59 | /* disable all IRQs */ | 103 | /* disable all IRQs */ |
| 60 | for (i = 0; i < 8; ++i) | 104 | for (i = 0; i < 8; ++i) |
| 61 | __raw_writel((4 * i) << 24 | (4 * i + 1) << 16 | | 105 | __raw_writel(prio2irq(4 * i) << 24 | |
| 62 | (4 * i + 2) << 8 | (4 * i + 3), SYS_IC(i)); | 106 | prio2irq(4 * i + 1) << 16 | |
| 107 | prio2irq(4 * i + 2) << 8 | | ||
| 108 | prio2irq(4 * i + 3), | ||
| 109 | SYS_IC(i)); | ||
| 63 | 110 | ||
| 64 | /* simple interrupt prio table: | ||
| 65 | * prio(x) < prio(y) <=> x < y | ||
| 66 | */ | ||
| 67 | for (i = 0; i < 32; ++i) | 111 | for (i = 0; i < 32; ++i) |
| 68 | __raw_writel(i, SYS_IVA(i)); | 112 | __raw_writel(prio2irq(i), SYS_IVA(i)); |
| 69 | 113 | ||
| 70 | for (i = IRQ_WATCHDOG; i <= IRQ_EXT3; ++i) { | 114 | for (i = 0; i <= 31; ++i) { |
| 71 | set_irq_chip(i, &ns9xxx_chip); | 115 | set_irq_chip(i, &ns9xxx_chip); |
| 72 | set_irq_handler(i, handle_level_irq); | 116 | set_irq_handler(i, handle_irq); |
| 73 | set_irq_flags(i, IRQF_VALID); | 117 | set_irq_flags(i, IRQF_VALID); |
| 74 | } | 118 | } |
| 75 | } | 119 | } |
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c index 760c9d0db7c3..9623fff6b3bc 100644 --- a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c +++ b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-ns9xxx/mach-cc9p9360dev.c | 2 | * arch/arm/mach-ns9xxx/mach-cc9p9360dev.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -11,12 +11,14 @@ | |||
| 11 | #include <asm/mach/arch.h> | 11 | #include <asm/mach/arch.h> |
| 12 | #include <asm/mach-types.h> | 12 | #include <asm/mach-types.h> |
| 13 | 13 | ||
| 14 | #include <asm/arch-ns9xxx/processor-ns9360.h> | ||
| 15 | |||
| 14 | #include "board-a9m9750dev.h" | 16 | #include "board-a9m9750dev.h" |
| 15 | #include "generic.h" | 17 | #include "generic.h" |
| 16 | 18 | ||
| 17 | static void __init mach_cc9p9360dev_map_io(void) | 19 | static void __init mach_cc9p9360dev_map_io(void) |
| 18 | { | 20 | { |
| 19 | ns9xxx_map_io(); | 21 | ns9360_map_io(); |
| 20 | board_a9m9750dev_map_io(); | 22 | board_a9m9750dev_map_io(); |
| 21 | } | 23 | } |
| 22 | 24 | ||
| @@ -36,6 +38,6 @@ MACHINE_START(CC9P9360DEV, "Digi ConnectCore 9P 9360 on an A9M9750 Devboard") | |||
| 36 | .map_io = mach_cc9p9360dev_map_io, | 38 | .map_io = mach_cc9p9360dev_map_io, |
| 37 | .init_irq = mach_cc9p9360dev_init_irq, | 39 | .init_irq = mach_cc9p9360dev_init_irq, |
| 38 | .init_machine = mach_cc9p9360dev_init_machine, | 40 | .init_machine = mach_cc9p9360dev_init_machine, |
| 39 | .timer = &ns9xxx_timer, | 41 | .timer = &ns9360_timer, |
| 40 | .boot_params = 0x100, | 42 | .boot_params = 0x100, |
| 41 | MACHINE_END | 43 | MACHINE_END |
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c index 85c8b41105c9..fcc815bdd291 100644 --- a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c +++ b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-ns9xxx/mach-cc9p9360js.c | 2 | * arch/arm/mach-ns9xxx/mach-cc9p9360js.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -11,6 +11,8 @@ | |||
| 11 | #include <asm/mach/arch.h> | 11 | #include <asm/mach/arch.h> |
| 12 | #include <asm/mach-types.h> | 12 | #include <asm/mach-types.h> |
| 13 | 13 | ||
| 14 | #include <asm/arch-ns9xxx/processor-ns9360.h> | ||
| 15 | |||
| 14 | #include "board-jscc9p9360.h" | 16 | #include "board-jscc9p9360.h" |
| 15 | #include "generic.h" | 17 | #include "generic.h" |
| 16 | 18 | ||
| @@ -21,9 +23,9 @@ static void __init mach_cc9p9360js_init_machine(void) | |||
| 21 | } | 23 | } |
| 22 | 24 | ||
| 23 | MACHINE_START(CC9P9360JS, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard") | 25 | MACHINE_START(CC9P9360JS, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard") |
| 24 | .map_io = ns9xxx_map_io, | 26 | .map_io = ns9360_map_io, |
| 25 | .init_irq = ns9xxx_init_irq, | 27 | .init_irq = ns9xxx_init_irq, |
| 26 | .init_machine = mach_cc9p9360js_init_machine, | 28 | .init_machine = mach_cc9p9360js_init_machine, |
| 27 | .timer = &ns9xxx_timer, | 29 | .timer = &ns9360_timer, |
| 28 | .boot_params = 0x100, | 30 | .boot_params = 0x100, |
| 29 | MACHINE_END | 31 | MACHINE_END |
diff --git a/arch/arm/mach-ns9xxx/plat-serial8250.c b/arch/arm/mach-ns9xxx/plat-serial8250.c new file mode 100644 index 000000000000..5aa5d9baf8c8 --- /dev/null +++ b/arch/arm/mach-ns9xxx/plat-serial8250.c | |||
| @@ -0,0 +1,69 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ns9xxx/plat-serial8250.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <linux/platform_device.h> | ||
| 12 | #include <linux/serial_8250.h> | ||
| 13 | |||
| 14 | #include <asm/arch-ns9xxx/regs-board-a9m9750dev.h> | ||
| 15 | #include <asm/arch-ns9xxx/board.h> | ||
| 16 | |||
| 17 | #define DRIVER_NAME "serial8250" | ||
| 18 | |||
| 19 | static int __init ns9xxx_plat_serial8250_init(void) | ||
| 20 | { | ||
| 21 | struct plat_serial8250_port *pdata; | ||
| 22 | struct platform_device *pdev; | ||
| 23 | int ret = -ENOMEM; | ||
| 24 | int i; | ||
| 25 | |||
| 26 | if (!board_is_a9m9750dev()) | ||
| 27 | return -ENODEV; | ||
| 28 | |||
| 29 | pdev = platform_device_alloc(DRIVER_NAME, 0); | ||
| 30 | if (!pdev) | ||
| 31 | goto err; | ||
| 32 | |||
| 33 | pdata = kzalloc(5 * sizeof(*pdata), GFP_KERNEL); | ||
| 34 | if (!pdata) | ||
| 35 | goto err; | ||
| 36 | |||
| 37 | pdev->dev.platform_data = pdata; | ||
| 38 | |||
| 39 | pdata[0].iobase = FPGA_UARTA_BASE; | ||
| 40 | pdata[1].iobase = FPGA_UARTB_BASE; | ||
| 41 | pdata[2].iobase = FPGA_UARTC_BASE; | ||
| 42 | pdata[3].iobase = FPGA_UARTD_BASE; | ||
| 43 | |||
| 44 | for (i = 0; i < 4; ++i) { | ||
| 45 | pdata[i].membase = (void __iomem *)pdata[i].iobase; | ||
| 46 | pdata[i].mapbase = pdata[i].iobase; | ||
| 47 | pdata[i].iotype = UPIO_MEM; | ||
| 48 | pdata[i].uartclk = 18432000; | ||
| 49 | pdata[i].flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; | ||
| 50 | } | ||
| 51 | |||
| 52 | pdata[0].irq = IRQ_FPGA_UARTA; | ||
| 53 | pdata[1].irq = IRQ_FPGA_UARTB; | ||
| 54 | pdata[2].irq = IRQ_FPGA_UARTC; | ||
| 55 | pdata[3].irq = IRQ_FPGA_UARTD; | ||
| 56 | |||
| 57 | ret = platform_device_add(pdev); | ||
| 58 | if (ret) { | ||
| 59 | err: | ||
| 60 | platform_device_put(pdev); | ||
| 61 | |||
| 62 | printk(KERN_WARNING "Could not add %s (errno=%d)\n", | ||
| 63 | DRIVER_NAME, ret); | ||
| 64 | } | ||
| 65 | |||
| 66 | return 0; | ||
| 67 | } | ||
| 68 | |||
| 69 | arch_initcall(ns9xxx_plat_serial8250_init); | ||
diff --git a/arch/arm/mach-ns9xxx/processor-ns9360.c b/arch/arm/mach-ns9xxx/processor-ns9360.c new file mode 100644 index 000000000000..2bee0b7fccbb --- /dev/null +++ b/arch/arm/mach-ns9xxx/processor-ns9360.c | |||
| @@ -0,0 +1,54 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ns9xxx/processor-ns9360.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <linux/io.h> | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/slab.h> | ||
| 14 | |||
| 15 | #include <asm/page.h> | ||
| 16 | #include <asm/mach/map.h> | ||
| 17 | #include <asm/arch-ns9xxx/processor-ns9360.h> | ||
| 18 | #include <asm/arch-ns9xxx/regs-sys-ns9360.h> | ||
| 19 | |||
| 20 | void ns9360_reset(char mode) | ||
| 21 | { | ||
| 22 | u32 reg; | ||
| 23 | |||
| 24 | reg = __raw_readl(SYS_PLL) >> 16; | ||
| 25 | REGSET(reg, SYS_PLL, SWC, YES); | ||
| 26 | __raw_writel(reg, SYS_PLL); | ||
| 27 | } | ||
| 28 | |||
| 29 | #define CRYSTAL 29491200 /* Hz */ | ||
| 30 | unsigned long ns9360_systemclock(void) | ||
| 31 | { | ||
| 32 | u32 pll = __raw_readl(SYS_PLL); | ||
| 33 | return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1) | ||
| 34 | >> REGGETIM(pll, SYS_PLL, FS); | ||
| 35 | } | ||
| 36 | |||
| 37 | static struct map_desc ns9360_io_desc[] __initdata = { | ||
| 38 | { /* BBus */ | ||
| 39 | .virtual = io_p2v(0x90000000), | ||
| 40 | .pfn = __phys_to_pfn(0x90000000), | ||
| 41 | .length = 0x00700000, | ||
| 42 | .type = MT_DEVICE, | ||
| 43 | }, { /* AHB */ | ||
| 44 | .virtual = io_p2v(0xa0100000), | ||
| 45 | .pfn = __phys_to_pfn(0xa0100000), | ||
| 46 | .length = 0x00900000, | ||
| 47 | .type = MT_DEVICE, | ||
| 48 | }, | ||
| 49 | }; | ||
| 50 | |||
| 51 | void __init ns9360_map_io(void) | ||
| 52 | { | ||
| 53 | iotable_init(ns9360_io_desc, ARRAY_SIZE(ns9360_io_desc)); | ||
| 54 | } | ||
diff --git a/arch/arm/mach-ns9xxx/time.c b/arch/arm/mach-ns9xxx/time-ns9360.c index c3dd1f4acb99..4d573c9793ed 100644 --- a/arch/arm/mach-ns9xxx/time.c +++ b/arch/arm/mach-ns9xxx/time-ns9360.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-ns9xxx/time.c | 2 | * arch/arm/mach-ns9xxx/time-ns9360.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 by Digi International Inc. | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
| 5 | * All rights reserved. | 5 | * All rights reserved. |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
| @@ -15,8 +15,8 @@ | |||
| 15 | #include <linux/clocksource.h> | 15 | #include <linux/clocksource.h> |
| 16 | #include <linux/clockchips.h> | 16 | #include <linux/clockchips.h> |
| 17 | 17 | ||
| 18 | #include <asm/arch-ns9xxx/regs-sys.h> | 18 | #include <asm/arch-ns9xxx/processor-ns9360.h> |
| 19 | #include <asm/arch-ns9xxx/clock.h> | 19 | #include <asm/arch-ns9xxx/regs-sys-ns9360.h> |
| 20 | #include <asm/arch-ns9xxx/irqs.h> | 20 | #include <asm/arch-ns9xxx/irqs.h> |
| 21 | #include <asm/arch/system.h> | 21 | #include <asm/arch/system.h> |
| 22 | #include "generic.h" | 22 | #include "generic.h" |
| @@ -25,26 +25,26 @@ | |||
| 25 | #define TIMER_CLOCKEVENT 1 | 25 | #define TIMER_CLOCKEVENT 1 |
| 26 | static u32 latch; | 26 | static u32 latch; |
| 27 | 27 | ||
| 28 | static cycle_t ns9xxx_clocksource_read(void) | 28 | static cycle_t ns9360_clocksource_read(void) |
| 29 | { | 29 | { |
| 30 | return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE)); | 30 | return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE)); |
| 31 | } | 31 | } |
| 32 | 32 | ||
| 33 | static struct clocksource ns9xxx_clocksource = { | 33 | static struct clocksource ns9360_clocksource = { |
| 34 | .name = "ns9xxx-timer" __stringify(TIMER_CLOCKSOURCE), | 34 | .name = "ns9360-timer" __stringify(TIMER_CLOCKSOURCE), |
| 35 | .rating = 300, | 35 | .rating = 300, |
| 36 | .read = ns9xxx_clocksource_read, | 36 | .read = ns9360_clocksource_read, |
| 37 | .mask = CLOCKSOURCE_MASK(32), | 37 | .mask = CLOCKSOURCE_MASK(32), |
| 38 | .shift = 20, | 38 | .shift = 20, |
| 39 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 39 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 40 | }; | 40 | }; |
| 41 | 41 | ||
| 42 | static void ns9xxx_clockevent_setmode(enum clock_event_mode mode, | 42 | static void ns9360_clockevent_setmode(enum clock_event_mode mode, |
| 43 | struct clock_event_device *clk) | 43 | struct clock_event_device *clk) |
| 44 | { | 44 | { |
| 45 | u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); | 45 | u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); |
| 46 | 46 | ||
| 47 | switch(mode) { | 47 | switch (mode) { |
| 48 | case CLOCK_EVT_MODE_PERIODIC: | 48 | case CLOCK_EVT_MODE_PERIODIC: |
| 49 | __raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT)); | 49 | __raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT)); |
| 50 | REGSET(tc, SYS_TCx, REN, EN); | 50 | REGSET(tc, SYS_TCx, REN, EN); |
| @@ -69,7 +69,7 @@ static void ns9xxx_clockevent_setmode(enum clock_event_mode mode, | |||
| 69 | __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); | 69 | __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); |
| 70 | } | 70 | } |
| 71 | 71 | ||
| 72 | static int ns9xxx_clockevent_setnextevent(unsigned long evt, | 72 | static int ns9360_clockevent_setnextevent(unsigned long evt, |
| 73 | struct clock_event_device *clk) | 73 | struct clock_event_device *clk) |
| 74 | { | 74 | { |
| 75 | u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); | 75 | u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); |
| @@ -88,20 +88,20 @@ static int ns9xxx_clockevent_setnextevent(unsigned long evt, | |||
| 88 | return 0; | 88 | return 0; |
| 89 | } | 89 | } |
| 90 | 90 | ||
| 91 | static struct clock_event_device ns9xxx_clockevent_device = { | 91 | static struct clock_event_device ns9360_clockevent_device = { |
| 92 | .name = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT), | 92 | .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT), |
| 93 | .shift = 20, | 93 | .shift = 20, |
| 94 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | 94 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
| 95 | .set_mode = ns9xxx_clockevent_setmode, | 95 | .set_mode = ns9360_clockevent_setmode, |
| 96 | .set_next_event = ns9xxx_clockevent_setnextevent, | 96 | .set_next_event = ns9360_clockevent_setnextevent, |
| 97 | }; | 97 | }; |
| 98 | 98 | ||
| 99 | static irqreturn_t ns9xxx_clockevent_handler(int irq, void *dev_id) | 99 | static irqreturn_t ns9360_clockevent_handler(int irq, void *dev_id) |
| 100 | { | 100 | { |
| 101 | int timerno = irq - IRQ_TIMER0; | 101 | int timerno = irq - IRQ_NS9360_TIMER0; |
| 102 | u32 tc; | 102 | u32 tc; |
| 103 | 103 | ||
| 104 | struct clock_event_device *evt = &ns9xxx_clockevent_device; | 104 | struct clock_event_device *evt = &ns9360_clockevent_device; |
| 105 | 105 | ||
| 106 | /* clear irq */ | 106 | /* clear irq */ |
| 107 | tc = __raw_readl(SYS_TC(timerno)); | 107 | tc = __raw_readl(SYS_TC(timerno)); |
| @@ -119,13 +119,13 @@ static irqreturn_t ns9xxx_clockevent_handler(int irq, void *dev_id) | |||
| 119 | return IRQ_HANDLED; | 119 | return IRQ_HANDLED; |
| 120 | } | 120 | } |
| 121 | 121 | ||
| 122 | static struct irqaction ns9xxx_clockevent_action = { | 122 | static struct irqaction ns9360_clockevent_action = { |
| 123 | .name = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT), | 123 | .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT), |
| 124 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | 124 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
| 125 | .handler = ns9xxx_clockevent_handler, | 125 | .handler = ns9360_clockevent_handler, |
| 126 | }; | 126 | }; |
| 127 | 127 | ||
| 128 | static void __init ns9xxx_timer_init(void) | 128 | static void __init ns9360_timer_init(void) |
| 129 | { | 129 | { |
| 130 | int tc; | 130 | int tc; |
| 131 | 131 | ||
| @@ -148,12 +148,12 @@ static void __init ns9xxx_timer_init(void) | |||
| 148 | 148 | ||
| 149 | __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); | 149 | __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); |
| 150 | 150 | ||
| 151 | ns9xxx_clocksource.mult = clocksource_hz2mult(ns9xxx_cpuclock(), | 151 | ns9360_clocksource.mult = clocksource_hz2mult(ns9360_cpuclock(), |
| 152 | ns9xxx_clocksource.shift); | 152 | ns9360_clocksource.shift); |
| 153 | 153 | ||
| 154 | clocksource_register(&ns9xxx_clocksource); | 154 | clocksource_register(&ns9360_clocksource); |
| 155 | 155 | ||
| 156 | latch = SH_DIV(ns9xxx_cpuclock(), HZ, 0); | 156 | latch = SH_DIV(ns9360_cpuclock(), HZ, 0); |
| 157 | 157 | ||
| 158 | tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); | 158 | tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); |
| 159 | REGSET(tc, SYS_TCx, TEN, DIS); | 159 | REGSET(tc, SYS_TCx, TEN, DIS); |
| @@ -166,19 +166,20 @@ static void __init ns9xxx_timer_init(void) | |||
| 166 | REGSET(tc, SYS_TCx, REN, EN); | 166 | REGSET(tc, SYS_TCx, REN, EN); |
| 167 | __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); | 167 | __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); |
| 168 | 168 | ||
| 169 | ns9xxx_clockevent_device.mult = div_sc(ns9xxx_cpuclock(), | 169 | ns9360_clockevent_device.mult = div_sc(ns9360_cpuclock(), |
| 170 | NSEC_PER_SEC, ns9xxx_clockevent_device.shift); | 170 | NSEC_PER_SEC, ns9360_clockevent_device.shift); |
| 171 | ns9xxx_clockevent_device.max_delta_ns = | 171 | ns9360_clockevent_device.max_delta_ns = |
| 172 | clockevent_delta2ns(-1, &ns9xxx_clockevent_device); | 172 | clockevent_delta2ns(-1, &ns9360_clockevent_device); |
| 173 | ns9xxx_clockevent_device.min_delta_ns = | 173 | ns9360_clockevent_device.min_delta_ns = |
| 174 | clockevent_delta2ns(1, &ns9xxx_clockevent_device); | 174 | clockevent_delta2ns(1, &ns9360_clockevent_device); |
| 175 | 175 | ||
| 176 | ns9xxx_clockevent_device.cpumask = cpumask_of_cpu(0); | 176 | ns9360_clockevent_device.cpumask = cpumask_of_cpu(0); |
| 177 | clockevents_register_device(&ns9xxx_clockevent_device); | 177 | clockevents_register_device(&ns9360_clockevent_device); |
| 178 | 178 | ||
| 179 | setup_irq(IRQ_TIMER0 + TIMER_CLOCKEVENT, &ns9xxx_clockevent_action); | 179 | setup_irq(IRQ_NS9360_TIMER0 + TIMER_CLOCKEVENT, |
| 180 | &ns9360_clockevent_action); | ||
| 180 | } | 181 | } |
| 181 | 182 | ||
| 182 | struct sys_timer ns9xxx_timer = { | 183 | struct sys_timer ns9360_timer = { |
| 183 | .init = ns9xxx_timer_init, | 184 | .init = ns9360_timer_init, |
| 184 | }; | 185 | }; |
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 015a66b3ca8e..c06f5254c0f3 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile | |||
| @@ -5,7 +5,8 @@ | |||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := io.o id.o clock.o irq.o mux.o serial.o devices.o | 6 | obj-y := io.o id.o clock.o irq.o mux.o serial.o devices.o |
| 7 | 7 | ||
| 8 | obj-$(CONFIG_OMAP_MPU_TIMER) += time.o | 8 | obj-$(CONFIG_OMAP_MPU_TIMER) += time.o |
| 9 | obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o | ||
| 9 | 10 | ||
| 10 | # Power Management | 11 | # Power Management |
| 11 | obj-$(CONFIG_PM) += pm.o sleep.o | 12 | obj-$(CONFIG_PM) += pm.o sleep.o |
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 5279e35a8aec..4f9baba7d893 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c | |||
| @@ -32,6 +32,7 @@ | |||
| 32 | #include <linux/interrupt.h> | 32 | #include <linux/interrupt.h> |
| 33 | #include <linux/irq.h> | 33 | #include <linux/irq.h> |
| 34 | #include <linux/i2c.h> | 34 | #include <linux/i2c.h> |
| 35 | #include <linux/leds.h> | ||
| 35 | 36 | ||
| 36 | #include <linux/mtd/mtd.h> | 37 | #include <linux/mtd/mtd.h> |
| 37 | #include <linux/mtd/partitions.h> | 38 | #include <linux/mtd/partitions.h> |
| @@ -183,11 +184,80 @@ static struct platform_device *osk5912_devices[] __initdata = { | |||
| 183 | &osk5912_mcbsp1_device, | 184 | &osk5912_mcbsp1_device, |
| 184 | }; | 185 | }; |
| 185 | 186 | ||
| 187 | static struct gpio_led tps_leds[] = { | ||
| 188 | /* NOTE: D9 and D2 have hardware blink support. | ||
| 189 | * Also, D9 requires non-battery power. | ||
| 190 | */ | ||
| 191 | { .gpio = OSK_TPS_GPIO_LED_D9, .name = "d9", }, | ||
| 192 | { .gpio = OSK_TPS_GPIO_LED_D2, .name = "d2", }, | ||
| 193 | { .gpio = OSK_TPS_GPIO_LED_D3, .name = "d3", .active_low = 1, | ||
| 194 | .default_trigger = "heartbeat", }, | ||
| 195 | }; | ||
| 196 | |||
| 197 | static struct gpio_led_platform_data tps_leds_data = { | ||
| 198 | .num_leds = 3, | ||
| 199 | .leds = tps_leds, | ||
| 200 | }; | ||
| 201 | |||
| 202 | static struct platform_device osk5912_tps_leds = { | ||
| 203 | .name = "leds-gpio", | ||
| 204 | .id = 0, | ||
| 205 | .dev.platform_data = &tps_leds_data, | ||
| 206 | }; | ||
| 207 | |||
| 208 | static int osk_tps_setup(struct i2c_client *client, void *context) | ||
| 209 | { | ||
| 210 | /* Set GPIO 1 HIGH to disable VBUS power supply; | ||
| 211 | * OHCI driver powers it up/down as needed. | ||
| 212 | */ | ||
| 213 | gpio_request(OSK_TPS_GPIO_USB_PWR_EN, "n_vbus_en"); | ||
| 214 | gpio_direction_output(OSK_TPS_GPIO_USB_PWR_EN, 1); | ||
| 215 | |||
| 216 | /* Set GPIO 2 high so LED D3 is off by default */ | ||
| 217 | tps65010_set_gpio_out_value(GPIO2, HIGH); | ||
| 218 | |||
| 219 | /* Set GPIO 3 low to take ethernet out of reset */ | ||
| 220 | gpio_request(OSK_TPS_GPIO_LAN_RESET, "smc_reset"); | ||
| 221 | gpio_direction_output(OSK_TPS_GPIO_LAN_RESET, 0); | ||
| 222 | |||
| 223 | /* GPIO4 is VDD_DSP */ | ||
| 224 | gpio_request(OSK_TPS_GPIO_DSP_PWR_EN, "dsp_power"); | ||
| 225 | gpio_direction_output(OSK_TPS_GPIO_DSP_PWR_EN, 1); | ||
| 226 | /* REVISIT if DSP support isn't configured, power it off ... */ | ||
| 227 | |||
| 228 | /* Let LED1 (D9) blink; leds-gpio may override it */ | ||
| 229 | tps65010_set_led(LED1, BLINK); | ||
| 230 | |||
| 231 | /* Set LED2 off by default */ | ||
| 232 | tps65010_set_led(LED2, OFF); | ||
| 233 | |||
| 234 | /* Enable LOW_PWR handshake */ | ||
| 235 | tps65010_set_low_pwr(ON); | ||
| 236 | |||
| 237 | /* Switch VLDO2 to 3.0V for AIC23 */ | ||
| 238 | tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V | ||
| 239 | | TPS_LDO1_ENABLE); | ||
| 240 | |||
| 241 | /* register these three LEDs */ | ||
| 242 | osk5912_tps_leds.dev.parent = &client->dev; | ||
| 243 | platform_device_register(&osk5912_tps_leds); | ||
| 244 | |||
| 245 | return 0; | ||
| 246 | } | ||
| 247 | |||
| 248 | static struct tps65010_board tps_board = { | ||
| 249 | .base = OSK_TPS_GPIO_BASE, | ||
| 250 | .outmask = 0x0f, | ||
| 251 | .setup = osk_tps_setup, | ||
| 252 | }; | ||
| 253 | |||
| 186 | static struct i2c_board_info __initdata osk_i2c_board_info[] = { | 254 | static struct i2c_board_info __initdata osk_i2c_board_info[] = { |
| 187 | { | 255 | { |
| 188 | I2C_BOARD_INFO("tps65010", 0x48), | 256 | I2C_BOARD_INFO("tps65010", 0x48), |
| 189 | .type = "tps65010", | 257 | .type = "tps65010", |
| 190 | .irq = OMAP_GPIO_IRQ(OMAP_MPUIO(1)), | 258 | .irq = OMAP_GPIO_IRQ(OMAP_MPUIO(1)), |
| 259 | .platform_data = &tps_board, | ||
| 260 | |||
| 191 | }, | 261 | }, |
| 192 | /* TODO when driver support is ready: | 262 | /* TODO when driver support is ready: |
| 193 | * - aic23 audio chip at 0x1a | 263 | * - aic23 audio chip at 0x1a |
| @@ -198,7 +268,7 @@ static struct i2c_board_info __initdata osk_i2c_board_info[] = { | |||
| 198 | 268 | ||
| 199 | static void __init osk_init_smc91x(void) | 269 | static void __init osk_init_smc91x(void) |
| 200 | { | 270 | { |
| 201 | if ((omap_request_gpio(0)) < 0) { | 271 | if ((gpio_request(0, "smc_irq")) < 0) { |
| 202 | printk("Error requesting gpio 0 for smc91x irq\n"); | 272 | printk("Error requesting gpio 0 for smc91x irq\n"); |
| 203 | return; | 273 | return; |
| 204 | } | 274 | } |
| @@ -210,7 +280,7 @@ static void __init osk_init_smc91x(void) | |||
| 210 | static void __init osk_init_cf(void) | 280 | static void __init osk_init_cf(void) |
| 211 | { | 281 | { |
| 212 | omap_cfg_reg(M7_1610_GPIO62); | 282 | omap_cfg_reg(M7_1610_GPIO62); |
| 213 | if ((omap_request_gpio(62)) < 0) { | 283 | if ((gpio_request(62, "cf_irq")) < 0) { |
| 214 | printk("Error requesting gpio 62 for CF irq\n"); | 284 | printk("Error requesting gpio 62 for CF irq\n"); |
| 215 | return; | 285 | return; |
| 216 | } | 286 | } |
| @@ -334,7 +404,7 @@ static struct platform_device *mistral_devices[] __initdata = { | |||
| 334 | 404 | ||
| 335 | static int mistral_get_pendown_state(void) | 405 | static int mistral_get_pendown_state(void) |
| 336 | { | 406 | { |
| 337 | return !omap_get_gpio_datain(4); | 407 | return !gpio_get_value(4); |
| 338 | } | 408 | } |
| 339 | 409 | ||
| 340 | static const struct ads7846_platform_data mistral_ts_info = { | 410 | static const struct ads7846_platform_data mistral_ts_info = { |
| @@ -396,25 +466,31 @@ static void __init osk_mistral_init(void) | |||
| 396 | omap_cfg_reg(W14_1610_CCP_DATAP); | 466 | omap_cfg_reg(W14_1610_CCP_DATAP); |
| 397 | 467 | ||
| 398 | /* CAM_PWDN */ | 468 | /* CAM_PWDN */ |
| 399 | if (omap_request_gpio(11) == 0) { | 469 | if (gpio_request(11, "cam_pwdn") == 0) { |
| 400 | omap_cfg_reg(N20_1610_GPIO11); | 470 | omap_cfg_reg(N20_1610_GPIO11); |
| 401 | omap_set_gpio_direction(11, 0 /* out */); | 471 | gpio_direction_output(11, 0); |
| 402 | omap_set_gpio_dataout(11, 0 /* off */); | ||
| 403 | } else | 472 | } else |
| 404 | pr_debug("OSK+Mistral: CAM_PWDN is awol\n"); | 473 | pr_debug("OSK+Mistral: CAM_PWDN is awol\n"); |
| 405 | 474 | ||
| 406 | 475 | ||
| 407 | /* omap_cfg_reg(P19_1610_GPIO6); */ /* BUSY */ | 476 | /* omap_cfg_reg(P19_1610_GPIO6); */ /* BUSY */ |
| 477 | gpio_request(6, "ts_busy"); | ||
| 478 | gpio_direction_input(6); | ||
| 479 | |||
| 408 | omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ | 480 | omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ |
| 481 | gpio_request(4, "ts_int"); | ||
| 482 | gpio_direction_input(4); | ||
| 409 | set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING); | 483 | set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING); |
| 484 | |||
| 410 | spi_register_board_info(mistral_boardinfo, | 485 | spi_register_board_info(mistral_boardinfo, |
| 411 | ARRAY_SIZE(mistral_boardinfo)); | 486 | ARRAY_SIZE(mistral_boardinfo)); |
| 412 | 487 | ||
| 413 | /* the sideways button (SW1) is for use as a "wakeup" button */ | 488 | /* the sideways button (SW1) is for use as a "wakeup" button */ |
| 414 | omap_cfg_reg(N15_1610_MPUIO2); | 489 | omap_cfg_reg(N15_1610_MPUIO2); |
| 415 | if (omap_request_gpio(OMAP_MPUIO(2)) == 0) { | 490 | if (gpio_request(OMAP_MPUIO(2), "wakeup") == 0) { |
| 416 | int ret = 0; | 491 | int ret = 0; |
| 417 | omap_set_gpio_direction(OMAP_MPUIO(2), 1); | 492 | |
| 493 | gpio_direction_input(OMAP_MPUIO(2)); | ||
| 418 | set_irq_type(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), IRQT_RISING); | 494 | set_irq_type(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), IRQT_RISING); |
| 419 | #ifdef CONFIG_PM | 495 | #ifdef CONFIG_PM |
| 420 | /* share the IRQ in case someone wants to use the | 496 | /* share the IRQ in case someone wants to use the |
| @@ -425,7 +501,7 @@ static void __init osk_mistral_init(void) | |||
| 425 | IRQF_SHARED, "mistral_wakeup", | 501 | IRQF_SHARED, "mistral_wakeup", |
| 426 | &osk_mistral_wake_interrupt); | 502 | &osk_mistral_wake_interrupt); |
| 427 | if (ret != 0) { | 503 | if (ret != 0) { |
| 428 | omap_free_gpio(OMAP_MPUIO(2)); | 504 | gpio_free(OMAP_MPUIO(2)); |
| 429 | printk(KERN_ERR "OSK+Mistral: no wakeup irq, %d?\n", | 505 | printk(KERN_ERR "OSK+Mistral: no wakeup irq, %d?\n", |
| 430 | ret); | 506 | ret); |
| 431 | } else | 507 | } else |
| @@ -438,10 +514,8 @@ static void __init osk_mistral_init(void) | |||
| 438 | * board, like the touchscreen, EEPROM, and wakeup (!) switch. | 514 | * board, like the touchscreen, EEPROM, and wakeup (!) switch. |
| 439 | */ | 515 | */ |
| 440 | omap_cfg_reg(PWL); | 516 | omap_cfg_reg(PWL); |
| 441 | if (omap_request_gpio(2) == 0) { | 517 | if (gpio_request(2, "lcd_pwr") == 0) |
| 442 | omap_set_gpio_direction(2, 0 /* out */); | 518 | gpio_direction_output(2, 1); |
| 443 | omap_set_gpio_dataout(2, 1 /* on */); | ||
| 444 | } | ||
| 445 | 519 | ||
| 446 | platform_add_devices(mistral_devices, ARRAY_SIZE(mistral_devices)); | 520 | platform_add_devices(mistral_devices, ARRAY_SIZE(mistral_devices)); |
| 447 | } | 521 | } |
| @@ -484,44 +558,6 @@ static void __init osk_map_io(void) | |||
| 484 | omap1_map_common_io(); | 558 | omap1_map_common_io(); |
| 485 | } | 559 | } |
| 486 | 560 | ||
| 487 | #ifdef CONFIG_TPS65010 | ||
| 488 | static int __init osk_tps_init(void) | ||
| 489 | { | ||
| 490 | if (!machine_is_omap_osk()) | ||
| 491 | return 0; | ||
| 492 | |||
| 493 | /* Let LED1 (D9) blink */ | ||
| 494 | tps65010_set_led(LED1, BLINK); | ||
| 495 | |||
| 496 | /* Disable LED 2 (D2) */ | ||
| 497 | tps65010_set_led(LED2, OFF); | ||
| 498 | |||
| 499 | /* Set GPIO 1 HIGH to disable VBUS power supply; | ||
| 500 | * OHCI driver powers it up/down as needed. | ||
| 501 | */ | ||
| 502 | tps65010_set_gpio_out_value(GPIO1, HIGH); | ||
| 503 | |||
| 504 | /* Set GPIO 2 low to turn on LED D3 */ | ||
| 505 | tps65010_set_gpio_out_value(GPIO2, HIGH); | ||
| 506 | |||
| 507 | /* Set GPIO 3 low to take ethernet out of reset */ | ||
| 508 | tps65010_set_gpio_out_value(GPIO3, LOW); | ||
| 509 | |||
| 510 | /* gpio4 for VDD_DSP */ | ||
| 511 | /* FIXME send power to DSP iff it's configured */ | ||
| 512 | |||
| 513 | /* Enable LOW_PWR */ | ||
| 514 | tps65010_set_low_pwr(ON); | ||
| 515 | |||
| 516 | /* Switch VLDO2 to 3.0V for AIC23 */ | ||
| 517 | tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V | ||
| 518 | | TPS_LDO1_ENABLE); | ||
| 519 | |||
| 520 | return 0; | ||
| 521 | } | ||
| 522 | fs_initcall(osk_tps_init); | ||
| 523 | #endif | ||
| 524 | |||
| 525 | MACHINE_START(OMAP_OSK, "TI-OSK") | 561 | MACHINE_START(OMAP_OSK, "TI-OSK") |
| 526 | /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */ | 562 | /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */ |
| 527 | .phys_io = 0xfff00000, | 563 | .phys_io = 0xfff00000, |
diff --git a/arch/arm/mach-omap1/leds-osk.c b/arch/arm/mach-omap1/leds-osk.c index 026685ed461a..754383dde807 100644 --- a/arch/arm/mach-omap1/leds-osk.c +++ b/arch/arm/mach-omap1/leds-osk.c | |||
| @@ -1,11 +1,9 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-omap1/leds-osk.c | 2 | * linux/arch/arm/mach-omap1/leds-osk.c |
| 3 | * | 3 | * |
| 4 | * LED driver for OSK, and optionally Mistral QVGA, boards | 4 | * LED driver for OSK with optional Mistral QVGA board |
| 5 | */ | 5 | */ |
| 6 | #include <linux/init.h> | 6 | #include <linux/init.h> |
| 7 | #include <linux/workqueue.h> | ||
| 8 | #include <linux/i2c/tps65010.h> | ||
| 9 | 7 | ||
| 10 | #include <asm/hardware.h> | 8 | #include <asm/hardware.h> |
| 11 | #include <asm/leds.h> | 9 | #include <asm/leds.h> |
| @@ -20,49 +18,11 @@ | |||
| 20 | #define LED_STATE_CLAIMED (1 << 1) | 18 | #define LED_STATE_CLAIMED (1 << 1) |
| 21 | static u8 led_state; | 19 | static u8 led_state; |
| 22 | 20 | ||
| 23 | #define GREEN_LED (1 << 0) /* TPS65010 LED1 */ | ||
| 24 | #define AMBER_LED (1 << 1) /* TPS65010 LED2 */ | ||
| 25 | #define RED_LED (1 << 2) /* TPS65010 GPIO2 */ | ||
| 26 | #define TIMER_LED (1 << 3) /* Mistral board */ | 21 | #define TIMER_LED (1 << 3) /* Mistral board */ |
| 27 | #define IDLE_LED (1 << 4) /* Mistral board */ | 22 | #define IDLE_LED (1 << 4) /* Mistral board */ |
| 28 | static u8 hw_led_state; | 23 | static u8 hw_led_state; |
| 29 | 24 | ||
| 30 | 25 | ||
| 31 | /* TPS65010 leds are changed using i2c -- from a task context. | ||
| 32 | * Using one of these for the "idle" LED would be impractical... | ||
| 33 | */ | ||
| 34 | #define TPS_LEDS (GREEN_LED | RED_LED | AMBER_LED) | ||
| 35 | |||
| 36 | static u8 tps_leds_change; | ||
| 37 | |||
| 38 | static void tps_work(struct work_struct *unused) | ||
| 39 | { | ||
| 40 | for (;;) { | ||
| 41 | u8 leds; | ||
| 42 | |||
| 43 | local_irq_disable(); | ||
| 44 | leds = tps_leds_change; | ||
| 45 | tps_leds_change = 0; | ||
| 46 | local_irq_enable(); | ||
| 47 | |||
| 48 | if (!leds) | ||
| 49 | break; | ||
| 50 | |||
| 51 | /* careful: the set_led() value is on/off/blink */ | ||
| 52 | if (leds & GREEN_LED) | ||
| 53 | tps65010_set_led(LED1, !!(hw_led_state & GREEN_LED)); | ||
| 54 | if (leds & AMBER_LED) | ||
| 55 | tps65010_set_led(LED2, !!(hw_led_state & AMBER_LED)); | ||
| 56 | |||
| 57 | /* the gpio led doesn't have that issue */ | ||
| 58 | if (leds & RED_LED) | ||
| 59 | tps65010_set_gpio_out_value(GPIO2, | ||
| 60 | !(hw_led_state & RED_LED)); | ||
| 61 | } | ||
| 62 | } | ||
| 63 | |||
| 64 | static DECLARE_WORK(work, tps_work); | ||
| 65 | |||
| 66 | #ifdef CONFIG_OMAP_OSK_MISTRAL | 26 | #ifdef CONFIG_OMAP_OSK_MISTRAL |
| 67 | 27 | ||
| 68 | /* For now, all system indicators require the Mistral board, since that | 28 | /* For now, all system indicators require the Mistral board, since that |
| @@ -112,7 +72,6 @@ void osk_leds_event(led_event_t evt) | |||
| 112 | case led_stop: | 72 | case led_stop: |
| 113 | led_state &= ~LED_STATE_ENABLED; | 73 | led_state &= ~LED_STATE_ENABLED; |
| 114 | hw_led_state = 0; | 74 | hw_led_state = 0; |
| 115 | /* NOTE: work may still be pending!! */ | ||
| 116 | break; | 75 | break; |
| 117 | 76 | ||
| 118 | case led_claim: | 77 | case led_claim: |
| @@ -145,48 +104,11 @@ void osk_leds_event(led_event_t evt) | |||
| 145 | 104 | ||
| 146 | #endif /* CONFIG_OMAP_OSK_MISTRAL */ | 105 | #endif /* CONFIG_OMAP_OSK_MISTRAL */ |
| 147 | 106 | ||
| 148 | /* "green" == tps LED1 (leftmost, normally power-good) | ||
| 149 | * works only with DC adapter, not on battery power! | ||
| 150 | */ | ||
| 151 | case led_green_on: | ||
| 152 | if (led_state & LED_STATE_CLAIMED) | ||
| 153 | hw_led_state |= GREEN_LED; | ||
| 154 | break; | ||
| 155 | case led_green_off: | ||
| 156 | if (led_state & LED_STATE_CLAIMED) | ||
| 157 | hw_led_state &= ~GREEN_LED; | ||
| 158 | break; | ||
| 159 | |||
| 160 | /* "amber" == tps LED2 (middle) */ | ||
| 161 | case led_amber_on: | ||
| 162 | if (led_state & LED_STATE_CLAIMED) | ||
| 163 | hw_led_state |= AMBER_LED; | ||
| 164 | break; | ||
| 165 | case led_amber_off: | ||
| 166 | if (led_state & LED_STATE_CLAIMED) | ||
| 167 | hw_led_state &= ~AMBER_LED; | ||
| 168 | break; | ||
| 169 | |||
| 170 | /* "red" == LED on tps gpio3 (rightmost) */ | ||
| 171 | case led_red_on: | ||
| 172 | if (led_state & LED_STATE_CLAIMED) | ||
| 173 | hw_led_state |= RED_LED; | ||
| 174 | break; | ||
| 175 | case led_red_off: | ||
| 176 | if (led_state & LED_STATE_CLAIMED) | ||
| 177 | hw_led_state &= ~RED_LED; | ||
| 178 | break; | ||
| 179 | |||
| 180 | default: | 107 | default: |
| 181 | break; | 108 | break; |
| 182 | } | 109 | } |
| 183 | 110 | ||
| 184 | leds ^= hw_led_state; | 111 | leds ^= hw_led_state; |
| 185 | leds &= TPS_LEDS; | ||
| 186 | if (leds && (led_state & LED_STATE_CLAIMED)) { | ||
| 187 | tps_leds_change |= leds; | ||
| 188 | schedule_work(&work); | ||
| 189 | } | ||
| 190 | 112 | ||
| 191 | done: | 113 | done: |
| 192 | local_irq_restore(flags); | 114 | local_irq_restore(flags); |
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 52c70e5fcf65..e207bf7cb853 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c | |||
| @@ -3,9 +3,9 @@ | |||
| 3 | * | 3 | * |
| 4 | * OMAP1 pin multiplexing configurations | 4 | * OMAP1 pin multiplexing configurations |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2003 - 2005 Nokia Corporation | 6 | * Copyright (C) 2003 - 2008 Nokia Corporation |
| 7 | * | 7 | * |
| 8 | * Written by Tony Lindgren <tony.lindgren@nokia.com> | 8 | * Written by Tony Lindgren |
| 9 | * | 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify | 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by | 11 | * it under the terms of the GNU General Public License as published by |
| @@ -32,8 +32,10 @@ | |||
| 32 | 32 | ||
| 33 | #ifdef CONFIG_OMAP_MUX | 33 | #ifdef CONFIG_OMAP_MUX |
| 34 | 34 | ||
| 35 | static struct omap_mux_cfg arch_mux_cfg; | ||
| 36 | |||
| 35 | #ifdef CONFIG_ARCH_OMAP730 | 37 | #ifdef CONFIG_ARCH_OMAP730 |
| 36 | struct pin_config __initdata_or_module omap730_pins[] = { | 38 | static struct pin_config __initdata_or_module omap730_pins[] = { |
| 37 | MUX_CFG_730("E2_730_KBR0", 12, 21, 0, 20, 1, 0) | 39 | MUX_CFG_730("E2_730_KBR0", 12, 21, 0, 20, 1, 0) |
| 38 | MUX_CFG_730("J7_730_KBR1", 12, 25, 0, 24, 1, 0) | 40 | MUX_CFG_730("J7_730_KBR1", 12, 25, 0, 24, 1, 0) |
| 39 | MUX_CFG_730("E1_730_KBR2", 12, 29, 0, 28, 1, 0) | 41 | MUX_CFG_730("E1_730_KBR2", 12, 29, 0, 28, 1, 0) |
| @@ -49,10 +51,14 @@ MUX_CFG_730("AA17_730_USB_DM", 2, 21, 0, 20, 0, 0) | |||
| 49 | MUX_CFG_730("W16_730_USB_PU_EN", 2, 25, 0, 24, 0, 0) | 51 | MUX_CFG_730("W16_730_USB_PU_EN", 2, 25, 0, 24, 0, 0) |
| 50 | MUX_CFG_730("W17_730_USB_VBUSI", 2, 29, 0, 28, 0, 0) | 52 | MUX_CFG_730("W17_730_USB_VBUSI", 2, 29, 0, 28, 0, 0) |
| 51 | }; | 53 | }; |
| 52 | #endif | 54 | #define OMAP730_PINS_SZ ARRAY_SIZE(omap730_pins) |
| 55 | #else | ||
| 56 | #define omap730_pins NULL | ||
| 57 | #define OMAP730_PINS_SZ 0 | ||
| 58 | #endif /* CONFIG_ARCH_OMAP730 */ | ||
| 53 | 59 | ||
| 54 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) | 60 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) |
| 55 | struct pin_config __initdata_or_module omap1xxx_pins[] = { | 61 | static struct pin_config __initdata_or_module omap1xxx_pins[] = { |
| 56 | /* | 62 | /* |
| 57 | * description mux mode mux pull pull pull pu_pd pu dbg | 63 | * description mux mode mux pull pull pull pu_pd pu dbg |
| 58 | * reg offset mode reg bit ena reg | 64 | * reg offset mode reg bit ena reg |
| @@ -306,22 +312,136 @@ MUX_CFG("Y12_1610_CCP_CLKP", 8, 18, 6, 1, 24, 1, 1, 0, 0) | |||
| 306 | MUX_CFG("W13_1610_CCP_CLKM", 9, 0, 6, 1, 28, 1, 1, 0, 0) | 312 | MUX_CFG("W13_1610_CCP_CLKM", 9, 0, 6, 1, 28, 1, 1, 0, 0) |
| 307 | MUX_CFG("W14_1610_CCP_DATAP", 9, 24, 6, 2, 4, 1, 2, 0, 0) | 313 | MUX_CFG("W14_1610_CCP_DATAP", 9, 24, 6, 2, 4, 1, 2, 0, 0) |
| 308 | MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0) | 314 | MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0) |
| 309 | |||
| 310 | }; | 315 | }; |
| 316 | #define OMAP1XXX_PINS_SZ ARRAY_SIZE(omap1xxx_pins) | ||
| 317 | #else | ||
| 318 | #define omap1xxx_pins NULL | ||
| 319 | #define OMAP1XXX_PINS_SZ 0 | ||
| 311 | #endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */ | 320 | #endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */ |
| 312 | 321 | ||
| 313 | int __init omap1_mux_init(void) | 322 | int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) |
| 314 | { | 323 | { |
| 315 | 324 | static DEFINE_SPINLOCK(mux_spin_lock); | |
| 316 | #ifdef CONFIG_ARCH_OMAP730 | 325 | unsigned long flags; |
| 317 | omap_mux_register(omap730_pins, ARRAY_SIZE(omap730_pins)); | 326 | unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0, |
| 327 | pull_orig = 0, pull = 0; | ||
| 328 | unsigned int mask, warn = 0; | ||
| 329 | |||
| 330 | /* Check the mux register in question */ | ||
| 331 | if (cfg->mux_reg) { | ||
| 332 | unsigned tmp1, tmp2; | ||
| 333 | |||
| 334 | spin_lock_irqsave(&mux_spin_lock, flags); | ||
| 335 | reg_orig = omap_readl(cfg->mux_reg); | ||
| 336 | |||
| 337 | /* The mux registers always seem to be 3 bits long */ | ||
| 338 | mask = (0x7 << cfg->mask_offset); | ||
| 339 | tmp1 = reg_orig & mask; | ||
| 340 | reg = reg_orig & ~mask; | ||
| 341 | |||
| 342 | tmp2 = (cfg->mask << cfg->mask_offset); | ||
| 343 | reg |= tmp2; | ||
| 344 | |||
| 345 | if (tmp1 != tmp2) | ||
| 346 | warn = 1; | ||
| 347 | |||
| 348 | omap_writel(reg, cfg->mux_reg); | ||
| 349 | spin_unlock_irqrestore(&mux_spin_lock, flags); | ||
| 350 | } | ||
| 351 | |||
| 352 | /* Check for pull up or pull down selection on 1610 */ | ||
| 353 | if (!cpu_is_omap15xx()) { | ||
| 354 | if (cfg->pu_pd_reg && cfg->pull_val) { | ||
| 355 | spin_lock_irqsave(&mux_spin_lock, flags); | ||
| 356 | pu_pd_orig = omap_readl(cfg->pu_pd_reg); | ||
| 357 | mask = 1 << cfg->pull_bit; | ||
| 358 | |||
| 359 | if (cfg->pu_pd_val) { | ||
| 360 | if (!(pu_pd_orig & mask)) | ||
| 361 | warn = 1; | ||
| 362 | /* Use pull up */ | ||
| 363 | pu_pd = pu_pd_orig | mask; | ||
| 364 | } else { | ||
| 365 | if (pu_pd_orig & mask) | ||
| 366 | warn = 1; | ||
| 367 | /* Use pull down */ | ||
| 368 | pu_pd = pu_pd_orig & ~mask; | ||
| 369 | } | ||
| 370 | omap_writel(pu_pd, cfg->pu_pd_reg); | ||
| 371 | spin_unlock_irqrestore(&mux_spin_lock, flags); | ||
| 372 | } | ||
| 373 | } | ||
| 374 | |||
| 375 | /* Check for an associated pull down register */ | ||
| 376 | if (cfg->pull_reg) { | ||
| 377 | spin_lock_irqsave(&mux_spin_lock, flags); | ||
| 378 | pull_orig = omap_readl(cfg->pull_reg); | ||
| 379 | mask = 1 << cfg->pull_bit; | ||
| 380 | |||
| 381 | if (cfg->pull_val) { | ||
| 382 | if (pull_orig & mask) | ||
| 383 | warn = 1; | ||
| 384 | /* Low bit = pull enabled */ | ||
| 385 | pull = pull_orig & ~mask; | ||
| 386 | } else { | ||
| 387 | if (!(pull_orig & mask)) | ||
| 388 | warn = 1; | ||
| 389 | /* High bit = pull disabled */ | ||
| 390 | pull = pull_orig | mask; | ||
| 391 | } | ||
| 392 | |||
| 393 | omap_writel(pull, cfg->pull_reg); | ||
| 394 | spin_unlock_irqrestore(&mux_spin_lock, flags); | ||
| 395 | } | ||
| 396 | |||
| 397 | if (warn) { | ||
| 398 | #ifdef CONFIG_OMAP_MUX_WARNINGS | ||
| 399 | printk(KERN_WARNING "MUX: initialized %s\n", cfg->name); | ||
| 318 | #endif | 400 | #endif |
| 319 | 401 | } | |
| 320 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) | 402 | |
| 321 | omap_mux_register(omap1xxx_pins, ARRAY_SIZE(omap1xxx_pins)); | 403 | #ifdef CONFIG_OMAP_MUX_DEBUG |
| 404 | if (cfg->debug || warn) { | ||
| 405 | printk("MUX: Setting register %s\n", cfg->name); | ||
| 406 | printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", | ||
| 407 | cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); | ||
| 408 | |||
| 409 | if (!cpu_is_omap15xx()) { | ||
| 410 | if (cfg->pu_pd_reg && cfg->pull_val) { | ||
| 411 | printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", | ||
| 412 | cfg->pu_pd_name, cfg->pu_pd_reg, | ||
| 413 | pu_pd_orig, pu_pd); | ||
| 414 | } | ||
| 415 | } | ||
| 416 | |||
| 417 | if (cfg->pull_reg) | ||
| 418 | printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", | ||
| 419 | cfg->pull_name, cfg->pull_reg, pull_orig, pull); | ||
| 420 | } | ||
| 322 | #endif | 421 | #endif |
| 323 | 422 | ||
| 423 | #ifdef CONFIG_OMAP_MUX_ERRORS | ||
| 424 | return warn ? -ETXTBSY : 0; | ||
| 425 | #else | ||
| 324 | return 0; | 426 | return 0; |
| 427 | #endif | ||
| 428 | } | ||
| 429 | |||
| 430 | int __init omap1_mux_init(void) | ||
| 431 | { | ||
| 432 | if (cpu_is_omap730()) { | ||
| 433 | arch_mux_cfg.pins = omap730_pins; | ||
| 434 | arch_mux_cfg.size = OMAP730_PINS_SZ; | ||
| 435 | arch_mux_cfg.cfg_reg = omap1_cfg_reg; | ||
| 436 | } | ||
| 437 | |||
| 438 | if (cpu_is_omap15xx() || cpu_is_omap16xx()) { | ||
| 439 | arch_mux_cfg.pins = omap1xxx_pins; | ||
| 440 | arch_mux_cfg.size = OMAP1XXX_PINS_SZ; | ||
| 441 | arch_mux_cfg.cfg_reg = omap1_cfg_reg; | ||
| 442 | } | ||
| 443 | |||
| 444 | return omap_mux_register(&arch_mux_cfg); | ||
| 325 | } | 445 | } |
| 326 | 446 | ||
| 327 | #endif | 447 | #endif |
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index a4f8b2055437..5d2b270935a2 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c | |||
| @@ -56,37 +56,6 @@ | |||
| 56 | #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE | 56 | #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE |
| 57 | #define OMAP_MPU_TIMER_OFFSET 0x100 | 57 | #define OMAP_MPU_TIMER_OFFSET 0x100 |
| 58 | 58 | ||
| 59 | /* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c, | ||
| 60 | * converted to use kHz by Kevin Hilman */ | ||
| 61 | /* convert from cycles(64bits) => nanoseconds (64bits) | ||
| 62 | * basic equation: | ||
| 63 | * ns = cycles / (freq / ns_per_sec) | ||
| 64 | * ns = cycles * (ns_per_sec / freq) | ||
| 65 | * ns = cycles * (10^9 / (cpu_khz * 10^3)) | ||
| 66 | * ns = cycles * (10^6 / cpu_khz) | ||
| 67 | * | ||
| 68 | * Then we use scaling math (suggested by george at mvista.com) to get: | ||
| 69 | * ns = cycles * (10^6 * SC / cpu_khz / SC | ||
| 70 | * ns = cycles * cyc2ns_scale / SC | ||
| 71 | * | ||
| 72 | * And since SC is a constant power of two, we can convert the div | ||
| 73 | * into a shift. | ||
| 74 | * -johnstul at us.ibm.com "math is hard, lets go shopping!" | ||
| 75 | */ | ||
| 76 | static unsigned long cyc2ns_scale; | ||
| 77 | #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ | ||
| 78 | |||
| 79 | static inline void set_cyc2ns_scale(unsigned long cpu_khz) | ||
| 80 | { | ||
| 81 | cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz; | ||
| 82 | } | ||
| 83 | |||
| 84 | static inline unsigned long long cycles_2_ns(unsigned long long cyc) | ||
| 85 | { | ||
| 86 | return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR; | ||
| 87 | } | ||
| 88 | |||
| 89 | |||
| 90 | typedef struct { | 59 | typedef struct { |
| 91 | u32 cntl; /* CNTL_TIMER, R/W */ | 60 | u32 cntl; /* CNTL_TIMER, R/W */ |
| 92 | u32 load_tim; /* LOAD_TIM, W */ | 61 | u32 load_tim; /* LOAD_TIM, W */ |
| @@ -194,8 +163,6 @@ static struct irqaction omap_mpu_timer1_irq = { | |||
| 194 | 163 | ||
| 195 | static __init void omap_init_mpu_timer(unsigned long rate) | 164 | static __init void omap_init_mpu_timer(unsigned long rate) |
| 196 | { | 165 | { |
| 197 | set_cyc2ns_scale(rate / 1000); | ||
| 198 | |||
| 199 | setup_irq(INT_TIMER1, &omap_mpu_timer1_irq); | 166 | setup_irq(INT_TIMER1, &omap_mpu_timer1_irq); |
| 200 | omap_mpu_timer_start(0, (rate / HZ) - 1, 1); | 167 | omap_mpu_timer_start(0, (rate / HZ) - 1, 1); |
| 201 | 168 | ||
| @@ -260,22 +227,6 @@ static void __init omap_init_clocksource(unsigned long rate) | |||
| 260 | printk(err, clocksource_mpu.name); | 227 | printk(err, clocksource_mpu.name); |
| 261 | } | 228 | } |
| 262 | 229 | ||
| 263 | |||
| 264 | /* | ||
| 265 | * Scheduler clock - returns current time in nanosec units. | ||
| 266 | */ | ||
| 267 | unsigned long long sched_clock(void) | ||
| 268 | { | ||
| 269 | unsigned long ticks = 0 - omap_mpu_timer_read(1); | ||
| 270 | unsigned long long ticks64; | ||
| 271 | |||
| 272 | ticks64 = omap_mpu_timer2_overflows; | ||
| 273 | ticks64 <<= 32; | ||
| 274 | ticks64 |= ticks; | ||
| 275 | |||
| 276 | return cycles_2_ns(ticks64); | ||
| 277 | } | ||
| 278 | |||
| 279 | /* | 230 | /* |
| 280 | * --------------------------------------------------------------------------- | 231 | * --------------------------------------------------------------------------- |
| 281 | * Timer initialization | 232 | * Timer initialization |
diff --git a/arch/arm/plat-omap/timer32k.c b/arch/arm/mach-omap1/timer32k.c index ea76f1979a3d..fbbdb806c95a 100644 --- a/arch/arm/plat-omap/timer32k.c +++ b/arch/arm/mach-omap1/timer32k.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/plat-omap/timer32k.c | 2 | * linux/arch/arm/mach-omap1/timer32k.c |
| 3 | * | 3 | * |
| 4 | * OMAP 32K Timer | 4 | * OMAP 32K Timer |
| 5 | * | 5 | * |
| @@ -70,8 +70,6 @@ struct sys_timer omap_timer; | |||
| 70 | 70 | ||
| 71 | #if defined(CONFIG_ARCH_OMAP16XX) | 71 | #if defined(CONFIG_ARCH_OMAP16XX) |
| 72 | #define TIMER_32K_SYNCHRONIZED 0xfffbc410 | 72 | #define TIMER_32K_SYNCHRONIZED 0xfffbc410 |
| 73 | #elif defined(CONFIG_ARCH_OMAP24XX) | ||
| 74 | #define TIMER_32K_SYNCHRONIZED (OMAP24XX_32KSYNCT_BASE + 0x10) | ||
| 75 | #else | 73 | #else |
| 76 | #error OMAP 32KHz timer does not currently work on 15XX! | 74 | #error OMAP 32KHz timer does not currently work on 15XX! |
| 77 | #endif | 75 | #endif |
| @@ -93,8 +91,6 @@ struct sys_timer omap_timer; | |||
| 93 | #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \ | 91 | #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \ |
| 94 | (((nr_jiffies) * (clock_rate)) / HZ) | 92 | (((nr_jiffies) * (clock_rate)) / HZ) |
| 95 | 93 | ||
| 96 | #if defined(CONFIG_ARCH_OMAP1) | ||
| 97 | |||
| 98 | static inline void omap_32k_timer_write(int val, int reg) | 94 | static inline void omap_32k_timer_write(int val, int reg) |
| 99 | { | 95 | { |
| 100 | omap_writew(val, OMAP1_32K_TIMER_BASE + reg); | 96 | omap_writew(val, OMAP1_32K_TIMER_BASE + reg); |
| @@ -120,30 +116,14 @@ static inline void omap_32k_timer_stop(void) | |||
| 120 | 116 | ||
| 121 | #define omap_32k_timer_ack_irq() | 117 | #define omap_32k_timer_ack_irq() |
| 122 | 118 | ||
| 123 | #elif defined(CONFIG_ARCH_OMAP2) | 119 | static int omap_32k_timer_set_next_event(unsigned long delta, |
| 124 | 120 | struct clock_event_device *dev) | |
| 125 | static struct omap_dm_timer *gptimer; | ||
| 126 | |||
| 127 | static inline void omap_32k_timer_start(unsigned long load_val) | ||
| 128 | { | ||
| 129 | omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val); | ||
| 130 | omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); | ||
| 131 | omap_dm_timer_start(gptimer); | ||
| 132 | } | ||
| 133 | |||
| 134 | static inline void omap_32k_timer_stop(void) | ||
| 135 | { | 121 | { |
| 136 | omap_dm_timer_stop(gptimer); | 122 | omap_32k_timer_start(delta); |
| 137 | } | ||
| 138 | 123 | ||
| 139 | static inline void omap_32k_timer_ack_irq(void) | 124 | return 0; |
| 140 | { | ||
| 141 | u32 status = omap_dm_timer_read_status(gptimer); | ||
| 142 | omap_dm_timer_write_status(gptimer, status); | ||
| 143 | } | 125 | } |
| 144 | 126 | ||
| 145 | #endif | ||
| 146 | |||
| 147 | static void omap_32k_timer_set_mode(enum clock_event_mode mode, | 127 | static void omap_32k_timer_set_mode(enum clock_event_mode mode, |
| 148 | struct clock_event_device *evt) | 128 | struct clock_event_device *evt) |
| 149 | { | 129 | { |
| @@ -164,8 +144,9 @@ static void omap_32k_timer_set_mode(enum clock_event_mode mode, | |||
| 164 | 144 | ||
| 165 | static struct clock_event_device clockevent_32k_timer = { | 145 | static struct clock_event_device clockevent_32k_timer = { |
| 166 | .name = "32k-timer", | 146 | .name = "32k-timer", |
| 167 | .features = CLOCK_EVT_FEAT_PERIODIC, | 147 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
| 168 | .shift = 32, | 148 | .shift = 32, |
| 149 | .set_next_event = omap_32k_timer_set_next_event, | ||
| 169 | .set_mode = omap_32k_timer_set_mode, | 150 | .set_mode = omap_32k_timer_set_mode, |
| 170 | }; | 151 | }; |
| 171 | 152 | ||
| @@ -178,32 +159,6 @@ static inline unsigned long omap_32k_sync_timer_read(void) | |||
| 178 | return omap_readl(TIMER_32K_SYNCHRONIZED); | 159 | return omap_readl(TIMER_32K_SYNCHRONIZED); |
| 179 | } | 160 | } |
| 180 | 161 | ||
| 181 | /* | ||
| 182 | * Rounds down to nearest usec. Note that this will overflow for larger values. | ||
| 183 | */ | ||
| 184 | static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k) | ||
| 185 | { | ||
| 186 | return (ticks_32k * 5*5*5*5*5*5) >> 9; | ||
| 187 | } | ||
| 188 | |||
| 189 | /* | ||
| 190 | * Rounds down to nearest nsec. | ||
| 191 | */ | ||
| 192 | static inline unsigned long long | ||
| 193 | omap_32k_ticks_to_nsecs(unsigned long ticks_32k) | ||
| 194 | { | ||
| 195 | return (unsigned long long) ticks_32k * 1000 * 5*5*5*5*5*5 >> 9; | ||
| 196 | } | ||
| 197 | |||
| 198 | /* | ||
| 199 | * Returns current time from boot in nsecs. It's OK for this to wrap | ||
| 200 | * around for now, as it's just a relative time stamp. | ||
| 201 | */ | ||
| 202 | unsigned long long sched_clock(void) | ||
| 203 | { | ||
| 204 | return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read()); | ||
| 205 | } | ||
| 206 | |||
| 207 | static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id) | 162 | static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id) |
| 208 | { | 163 | { |
| 209 | struct clock_event_device *evt = &clockevent_32k_timer; | 164 | struct clock_event_device *evt = &clockevent_32k_timer; |
| @@ -222,22 +177,7 @@ static struct irqaction omap_32k_timer_irq = { | |||
| 222 | 177 | ||
| 223 | static __init void omap_init_32k_timer(void) | 178 | static __init void omap_init_32k_timer(void) |
| 224 | { | 179 | { |
| 225 | if (cpu_class_is_omap1()) | 180 | setup_irq(INT_OS_TIMER, &omap_32k_timer_irq); |
| 226 | setup_irq(INT_OS_TIMER, &omap_32k_timer_irq); | ||
| 227 | |||
| 228 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 229 | /* REVISIT: Check 24xx TIOCP_CFG settings after idle works */ | ||
| 230 | if (cpu_is_omap24xx()) { | ||
| 231 | gptimer = omap_dm_timer_request_specific(1); | ||
| 232 | BUG_ON(gptimer == NULL); | ||
| 233 | |||
| 234 | omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ); | ||
| 235 | setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq); | ||
| 236 | omap_dm_timer_set_int_enable(gptimer, | ||
| 237 | OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW | | ||
| 238 | OMAP_TIMER_INT_MATCH); | ||
| 239 | } | ||
| 240 | #endif | ||
| 241 | 181 | ||
| 242 | clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC, | 182 | clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC, |
| 243 | NSEC_PER_SEC, | 183 | NSEC_PER_SEC, |
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index b05b738d31e6..2feb6870b735 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
| @@ -3,13 +3,15 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \ | 6 | obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o clock.o mux.o \ |
| 7 | serial.o gpmc.o | 7 | devices.o serial.o gpmc.o timer-gp.o |
| 8 | |||
| 9 | obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o | ||
| 10 | 8 | ||
| 11 | # Power Management | 9 | # Power Management |
| 12 | obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o | 10 | obj-$(CONFIG_PM) += pm.o sleep.o |
| 11 | |||
| 12 | # Clock framework | ||
| 13 | obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o | ||
| 14 | obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o | ||
| 13 | 15 | ||
| 14 | # Specific board support | 16 | # Specific board support |
| 15 | obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o | 17 | obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o |
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 64235dee5614..1c12d7c6c7fc 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c | |||
| @@ -33,7 +33,6 @@ | |||
| 33 | #include <asm/arch/board.h> | 33 | #include <asm/arch/board.h> |
| 34 | #include <asm/arch/common.h> | 34 | #include <asm/arch/common.h> |
| 35 | #include <asm/arch/gpmc.h> | 35 | #include <asm/arch/gpmc.h> |
| 36 | #include "prcm-regs.h" | ||
| 37 | 36 | ||
| 38 | #include <asm/io.h> | 37 | #include <asm/io.h> |
| 39 | 38 | ||
| @@ -125,15 +124,18 @@ static inline void __init sdp2430_init_smc91x(void) | |||
| 125 | int eth_cs; | 124 | int eth_cs; |
| 126 | unsigned long cs_mem_base; | 125 | unsigned long cs_mem_base; |
| 127 | unsigned int rate; | 126 | unsigned int rate; |
| 128 | struct clk *l3ck; | 127 | struct clk *gpmc_fck; |
| 129 | 128 | ||
| 130 | eth_cs = SDP2430_SMC91X_CS; | 129 | eth_cs = SDP2430_SMC91X_CS; |
| 131 | 130 | ||
| 132 | l3ck = clk_get(NULL, "core_l3_ck"); | 131 | gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ |
| 133 | if (IS_ERR(l3ck)) | 132 | if (IS_ERR(gpmc_fck)) { |
| 134 | rate = 100000000; | 133 | WARN_ON(1); |
| 135 | else | 134 | return; |
| 136 | rate = clk_get_rate(l3ck); | 135 | } |
| 136 | |||
| 137 | clk_enable(gpmc_fck); | ||
| 138 | rate = clk_get_rate(gpmc_fck); | ||
| 137 | 139 | ||
| 138 | /* Make sure CS1 timings are correct, for 2430 always muxed */ | 140 | /* Make sure CS1 timings are correct, for 2430 always muxed */ |
| 139 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200); | 141 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200); |
| @@ -160,7 +162,7 @@ static inline void __init sdp2430_init_smc91x(void) | |||
| 160 | 162 | ||
| 161 | if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { | 163 | if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { |
| 162 | printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); | 164 | printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); |
| 163 | return; | 165 | goto out; |
| 164 | } | 166 | } |
| 165 | 167 | ||
| 166 | sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300; | 168 | sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300; |
| @@ -171,10 +173,13 @@ static inline void __init sdp2430_init_smc91x(void) | |||
| 171 | printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", | 173 | printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", |
| 172 | OMAP24XX_ETHR_GPIO_IRQ); | 174 | OMAP24XX_ETHR_GPIO_IRQ); |
| 173 | gpmc_cs_free(eth_cs); | 175 | gpmc_cs_free(eth_cs); |
| 174 | return; | 176 | goto out; |
| 175 | } | 177 | } |
| 176 | omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1); | 178 | omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1); |
| 177 | 179 | ||
| 180 | out: | ||
| 181 | clk_disable(gpmc_fck); | ||
| 182 | clk_put(gpmc_fck); | ||
| 178 | } | 183 | } |
| 179 | 184 | ||
| 180 | static void __init omap_2430sdp_init_irq(void) | 185 | static void __init omap_2430sdp_init_irq(void) |
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 7846551f0575..a1e1e6765b5b 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c | |||
| @@ -26,6 +26,8 @@ | |||
| 26 | #include <linux/interrupt.h> | 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/delay.h> | 27 | #include <linux/delay.h> |
| 28 | #include <linux/leds.h> | 28 | #include <linux/leds.h> |
| 29 | #include <linux/err.h> | ||
| 30 | #include <linux/clk.h> | ||
| 29 | 31 | ||
| 30 | #include <asm/hardware.h> | 32 | #include <asm/hardware.h> |
| 31 | #include <asm/mach-types.h> | 33 | #include <asm/mach-types.h> |
| @@ -39,7 +41,7 @@ | |||
| 39 | #include <asm/arch/board.h> | 41 | #include <asm/arch/board.h> |
| 40 | #include <asm/arch/common.h> | 42 | #include <asm/arch/common.h> |
| 41 | #include <asm/arch/gpmc.h> | 43 | #include <asm/arch/gpmc.h> |
| 42 | #include "prcm-regs.h" | 44 | #include <asm/arch/control.h> |
| 43 | 45 | ||
| 44 | /* LED & Switch macros */ | 46 | /* LED & Switch macros */ |
| 45 | #define LED0_GPIO13 13 | 47 | #define LED0_GPIO13 13 |
| @@ -187,17 +189,47 @@ static inline void __init apollon_init_smc91x(void) | |||
| 187 | { | 189 | { |
| 188 | unsigned long base; | 190 | unsigned long base; |
| 189 | 191 | ||
| 192 | unsigned int rate; | ||
| 193 | struct clk *gpmc_fck; | ||
| 194 | int eth_cs; | ||
| 195 | |||
| 196 | gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ | ||
| 197 | if (IS_ERR(gpmc_fck)) { | ||
| 198 | WARN_ON(1); | ||
| 199 | return; | ||
| 200 | } | ||
| 201 | |||
| 202 | clk_enable(gpmc_fck); | ||
| 203 | rate = clk_get_rate(gpmc_fck); | ||
| 204 | |||
| 205 | eth_cs = APOLLON_ETH_CS; | ||
| 206 | |||
| 190 | /* Make sure CS1 timings are correct */ | 207 | /* Make sure CS1 timings are correct */ |
| 191 | GPMC_CONFIG1_1 = 0x00011203; | 208 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200); |
| 192 | GPMC_CONFIG2_1 = 0x001f1f01; | 209 | |
| 193 | GPMC_CONFIG3_1 = 0x00080803; | 210 | if (rate >= 160000000) { |
| 194 | GPMC_CONFIG4_1 = 0x1c091c09; | 211 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01); |
| 195 | GPMC_CONFIG5_1 = 0x041f1f1f; | 212 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803); |
| 196 | GPMC_CONFIG6_1 = 0x000004c4; | 213 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a); |
| 214 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); | ||
| 215 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); | ||
| 216 | } else if (rate >= 130000000) { | ||
| 217 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); | ||
| 218 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); | ||
| 219 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); | ||
| 220 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); | ||
| 221 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); | ||
| 222 | } else {/* rate = 100000000 */ | ||
| 223 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); | ||
| 224 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); | ||
| 225 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); | ||
| 226 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F); | ||
| 227 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2); | ||
| 228 | } | ||
| 197 | 229 | ||
| 198 | if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) { | 230 | if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) { |
| 199 | printk(KERN_ERR "Failed to request GPMC CS for smc91x\n"); | 231 | printk(KERN_ERR "Failed to request GPMC CS for smc91x\n"); |
| 200 | return; | 232 | goto out; |
| 201 | } | 233 | } |
| 202 | apollon_smc91x_resources[0].start = base + 0x300; | 234 | apollon_smc91x_resources[0].start = base + 0x300; |
| 203 | apollon_smc91x_resources[0].end = base + 0x30f; | 235 | apollon_smc91x_resources[0].end = base + 0x30f; |
| @@ -208,9 +240,13 @@ static inline void __init apollon_init_smc91x(void) | |||
| 208 | printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", | 240 | printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", |
| 209 | APOLLON_ETHR_GPIO_IRQ); | 241 | APOLLON_ETHR_GPIO_IRQ); |
| 210 | gpmc_cs_free(APOLLON_ETH_CS); | 242 | gpmc_cs_free(APOLLON_ETH_CS); |
| 211 | return; | 243 | goto out; |
| 212 | } | 244 | } |
| 213 | omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1); | 245 | omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1); |
| 246 | |||
| 247 | out: | ||
| 248 | clk_disable(gpmc_fck); | ||
| 249 | clk_put(gpmc_fck); | ||
| 214 | } | 250 | } |
| 215 | 251 | ||
| 216 | static void __init omap_apollon_init_irq(void) | 252 | static void __init omap_apollon_init_irq(void) |
| @@ -330,6 +366,8 @@ static void __init apollon_usb_init(void) | |||
| 330 | 366 | ||
| 331 | static void __init omap_apollon_init(void) | 367 | static void __init omap_apollon_init(void) |
| 332 | { | 368 | { |
| 369 | u32 v; | ||
| 370 | |||
| 333 | apollon_led_init(); | 371 | apollon_led_init(); |
| 334 | apollon_sw_init(); | 372 | apollon_sw_init(); |
| 335 | apollon_flash_init(); | 373 | apollon_flash_init(); |
| @@ -339,7 +377,9 @@ static void __init omap_apollon_init(void) | |||
| 339 | omap_cfg_reg(W19_24XX_SYS_NIRQ); | 377 | omap_cfg_reg(W19_24XX_SYS_NIRQ); |
| 340 | 378 | ||
| 341 | /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */ | 379 | /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */ |
| 342 | CONTROL_DEVCONF |= (1 << 24); | 380 | v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); |
| 381 | v |= (1 << 24); | ||
| 382 | omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); | ||
| 343 | 383 | ||
| 344 | /* | 384 | /* |
| 345 | * Make sure the serial ports are muxed on at this point. | 385 | * Make sure the serial ports are muxed on at this point. |
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index f125f432cc3e..d1915f99a5fa 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c | |||
| @@ -19,6 +19,8 @@ | |||
| 19 | #include <linux/delay.h> | 19 | #include <linux/delay.h> |
| 20 | #include <linux/workqueue.h> | 20 | #include <linux/workqueue.h> |
| 21 | #include <linux/input.h> | 21 | #include <linux/input.h> |
| 22 | #include <linux/err.h> | ||
| 23 | #include <linux/clk.h> | ||
| 22 | 24 | ||
| 23 | #include <asm/hardware.h> | 25 | #include <asm/hardware.h> |
| 24 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
| @@ -26,6 +28,7 @@ | |||
| 26 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
| 27 | #include <asm/mach/flash.h> | 29 | #include <asm/mach/flash.h> |
| 28 | 30 | ||
| 31 | #include <asm/arch/control.h> | ||
| 29 | #include <asm/arch/gpio.h> | 32 | #include <asm/arch/gpio.h> |
| 30 | #include <asm/arch/gpioexpander.h> | 33 | #include <asm/arch/gpioexpander.h> |
| 31 | #include <asm/arch/mux.h> | 34 | #include <asm/arch/mux.h> |
| @@ -36,10 +39,13 @@ | |||
| 36 | #include <asm/arch/keypad.h> | 39 | #include <asm/arch/keypad.h> |
| 37 | #include <asm/arch/menelaus.h> | 40 | #include <asm/arch/menelaus.h> |
| 38 | #include <asm/arch/dma.h> | 41 | #include <asm/arch/dma.h> |
| 39 | #include "prcm-regs.h" | 42 | #include <asm/arch/gpmc.h> |
| 40 | 43 | ||
| 41 | #include <asm/io.h> | 44 | #include <asm/io.h> |
| 42 | 45 | ||
| 46 | #define H4_FLASH_CS 0 | ||
| 47 | #define H4_SMC91X_CS 1 | ||
| 48 | |||
| 43 | static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 }; | 49 | static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 }; |
| 44 | static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 }; | 50 | static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 }; |
| 45 | 51 | ||
| @@ -116,8 +122,6 @@ static struct flash_platform_data h4_flash_data = { | |||
| 116 | }; | 122 | }; |
| 117 | 123 | ||
| 118 | static struct resource h4_flash_resource = { | 124 | static struct resource h4_flash_resource = { |
| 119 | .start = H4_CS0_BASE, | ||
| 120 | .end = H4_CS0_BASE + SZ_64M - 1, | ||
| 121 | .flags = IORESOURCE_MEM, | 125 | .flags = IORESOURCE_MEM, |
| 122 | }; | 126 | }; |
| 123 | 127 | ||
| @@ -253,21 +257,107 @@ static struct platform_device *h4_devices[] __initdata = { | |||
| 253 | &h4_lcd_device, | 257 | &h4_lcd_device, |
| 254 | }; | 258 | }; |
| 255 | 259 | ||
| 260 | /* 2420 Sysboot setup (2430 is different) */ | ||
| 261 | static u32 get_sysboot_value(void) | ||
| 262 | { | ||
| 263 | return (omap_ctrl_readl(OMAP24XX_CONTROL_STATUS) & | ||
| 264 | (OMAP2_SYSBOOT_5_MASK | OMAP2_SYSBOOT_4_MASK | | ||
| 265 | OMAP2_SYSBOOT_3_MASK | OMAP2_SYSBOOT_2_MASK | | ||
| 266 | OMAP2_SYSBOOT_1_MASK | OMAP2_SYSBOOT_0_MASK)); | ||
| 267 | } | ||
| 268 | |||
| 269 | /* H4-2420's always used muxed mode, H4-2422's always use non-muxed | ||
| 270 | * | ||
| 271 | * Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423 | ||
| 272 | * correctly. The macro needs to look at production_id not just hawkeye. | ||
| 273 | */ | ||
| 274 | static u32 is_gpmc_muxed(void) | ||
| 275 | { | ||
| 276 | u32 mux; | ||
| 277 | mux = get_sysboot_value(); | ||
| 278 | if ((mux & 0xF) == 0xd) | ||
| 279 | return 1; /* NAND config (could be either) */ | ||
| 280 | if (mux & 0x2) /* if mux'ed */ | ||
| 281 | return 1; | ||
| 282 | else | ||
| 283 | return 0; | ||
| 284 | } | ||
| 285 | |||
| 256 | static inline void __init h4_init_debug(void) | 286 | static inline void __init h4_init_debug(void) |
| 257 | { | 287 | { |
| 288 | int eth_cs; | ||
| 289 | unsigned long cs_mem_base; | ||
| 290 | unsigned int muxed, rate; | ||
| 291 | struct clk *gpmc_fck; | ||
| 292 | |||
| 293 | eth_cs = H4_SMC91X_CS; | ||
| 294 | |||
| 295 | gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ | ||
| 296 | if (IS_ERR(gpmc_fck)) { | ||
| 297 | WARN_ON(1); | ||
| 298 | return; | ||
| 299 | } | ||
| 300 | |||
| 301 | clk_enable(gpmc_fck); | ||
| 302 | rate = clk_get_rate(gpmc_fck); | ||
| 303 | clk_disable(gpmc_fck); | ||
| 304 | clk_put(gpmc_fck); | ||
| 305 | |||
| 306 | if (is_gpmc_muxed()) | ||
| 307 | muxed = 0x200; | ||
| 308 | else | ||
| 309 | muxed = 0; | ||
| 310 | |||
| 258 | /* Make sure CS1 timings are correct */ | 311 | /* Make sure CS1 timings are correct */ |
| 259 | GPMC_CONFIG1_1 = 0x00011200; | 312 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, |
| 260 | GPMC_CONFIG2_1 = 0x001f1f01; | 313 | 0x00011000 | muxed); |
| 261 | GPMC_CONFIG3_1 = 0x00080803; | 314 | |
| 262 | GPMC_CONFIG4_1 = 0x1c091c09; | 315 | if (rate >= 160000000) { |
| 263 | GPMC_CONFIG5_1 = 0x041f1f1f; | 316 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01); |
| 264 | GPMC_CONFIG6_1 = 0x000004c4; | 317 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803); |
| 265 | GPMC_CONFIG7_1 = 0x00000f40 | (0x08000000 >> 24); | 318 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a); |
| 319 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); | ||
| 320 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); | ||
| 321 | } else if (rate >= 130000000) { | ||
| 322 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); | ||
| 323 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); | ||
| 324 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); | ||
| 325 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); | ||
| 326 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); | ||
| 327 | } else {/* rate = 100000000 */ | ||
| 328 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); | ||
| 329 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); | ||
| 330 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); | ||
| 331 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F); | ||
| 332 | gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2); | ||
| 333 | } | ||
| 334 | |||
| 335 | if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { | ||
| 336 | printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); | ||
| 337 | goto out; | ||
| 338 | } | ||
| 339 | |||
| 266 | udelay(100); | 340 | udelay(100); |
| 267 | 341 | ||
| 268 | omap_cfg_reg(M15_24XX_GPIO92); | 342 | omap_cfg_reg(M15_24XX_GPIO92); |
| 269 | if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0) | 343 | if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0) |
| 270 | gpmc_cs_free(eth_cs); | 344 | gpmc_cs_free(eth_cs); |
| 345 | |||
| 346 | out: | ||
| 347 | clk_disable(gpmc_fck); | ||
| 348 | clk_put(gpmc_fck); | ||
| 349 | } | ||
| 350 | |||
| 351 | static void __init h4_init_flash(void) | ||
| 352 | { | ||
| 353 | unsigned long base; | ||
| 354 | |||
| 355 | if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) { | ||
| 356 | printk("Can't request GPMC CS for flash\n"); | ||
| 357 | return; | ||
| 358 | } | ||
| 359 | h4_flash_resource.start = base; | ||
| 360 | h4_flash_resource.end = base + SZ_64M - 1; | ||
| 271 | } | 361 | } |
| 272 | 362 | ||
| 273 | static void __init omap_h4_init_irq(void) | 363 | static void __init omap_h4_init_irq(void) |
| @@ -275,6 +365,7 @@ static void __init omap_h4_init_irq(void) | |||
| 275 | omap2_init_common_hw(); | 365 | omap2_init_common_hw(); |
| 276 | omap_init_irq(); | 366 | omap_init_irq(); |
| 277 | omap_gpio_init(); | 367 | omap_gpio_init(); |
| 368 | h4_init_flash(); | ||
| 278 | } | 369 | } |
| 279 | 370 | ||
| 280 | static struct omap_uart_config h4_uart_config __initdata = { | 371 | static struct omap_uart_config h4_uart_config __initdata = { |
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index e6e85b7b097b..b57ffb5a22a5 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
| @@ -1,20 +1,19 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/clock.c | 2 | * linux/arch/arm/mach-omap2/clock.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005 Texas Instruments Inc. | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
| 5 | * Richard Woodruff <r-woodruff2@ti.com> | 5 | * Copyright (C) 2004-2008 Nokia Corporation |
| 6 | * Created for OMAP2. | ||
| 7 | * | ||
| 8 | * Cleaned up and modified to use omap shared clock framework by | ||
| 9 | * Tony Lindgren <tony@atomide.com> | ||
| 10 | * | 6 | * |
| 11 | * Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation | 7 | * Contacts: |
| 12 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
| 9 | * Paul Walmsley | ||
| 13 | * | 10 | * |
| 14 | * This program is free software; you can redistribute it and/or modify | 11 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License version 2 as | 12 | * it under the terms of the GNU General Public License version 2 as |
| 16 | * published by the Free Software Foundation. | 13 | * published by the Free Software Foundation. |
| 17 | */ | 14 | */ |
| 15 | #undef DEBUG | ||
| 16 | |||
| 18 | #include <linux/module.h> | 17 | #include <linux/module.h> |
| 19 | #include <linux/kernel.h> | 18 | #include <linux/kernel.h> |
| 20 | #include <linux/device.h> | 19 | #include <linux/device.h> |
| @@ -22,176 +21,227 @@ | |||
| 22 | #include <linux/errno.h> | 21 | #include <linux/errno.h> |
| 23 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 24 | #include <linux/clk.h> | 23 | #include <linux/clk.h> |
| 24 | #include <asm/bitops.h> | ||
| 25 | 25 | ||
| 26 | #include <asm/io.h> | 26 | #include <asm/io.h> |
| 27 | 27 | ||
| 28 | #include <asm/arch/clock.h> | 28 | #include <asm/arch/clock.h> |
| 29 | #include <asm/arch/sram.h> | 29 | #include <asm/arch/sram.h> |
| 30 | #include <asm/arch/cpu.h> | ||
| 30 | #include <asm/div64.h> | 31 | #include <asm/div64.h> |
| 31 | 32 | ||
| 32 | #include "prcm-regs.h" | ||
| 33 | #include "memory.h" | 33 | #include "memory.h" |
| 34 | #include "sdrc.h" | ||
| 34 | #include "clock.h" | 35 | #include "clock.h" |
| 36 | #include "prm.h" | ||
| 37 | #include "prm-regbits-24xx.h" | ||
| 38 | #include "cm.h" | ||
| 39 | #include "cm-regbits-24xx.h" | ||
| 40 | #include "cm-regbits-34xx.h" | ||
| 35 | 41 | ||
| 36 | #undef DEBUG | 42 | #define MAX_CLOCK_ENABLE_WAIT 100000 |
| 37 | |||
| 38 | //#define DOWN_VARIABLE_DPLL 1 /* Experimental */ | ||
| 39 | 43 | ||
| 40 | static struct prcm_config *curr_prcm_set; | 44 | u8 cpu_mask; |
| 41 | static u32 curr_perf_level = PRCM_FULL_SPEED; | ||
| 42 | static struct clk *vclk; | ||
| 43 | static struct clk *sclk; | ||
| 44 | 45 | ||
| 45 | /*------------------------------------------------------------------------- | 46 | /*------------------------------------------------------------------------- |
| 46 | * Omap2 specific clock functions | 47 | * Omap2 specific clock functions |
| 47 | *-------------------------------------------------------------------------*/ | 48 | *-------------------------------------------------------------------------*/ |
| 48 | 49 | ||
| 49 | /* Recalculate SYST_CLK */ | 50 | /** |
| 50 | static void omap2_sys_clk_recalc(struct clk * clk) | 51 | * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware |
| 52 | * @clk: OMAP clock struct ptr to use | ||
| 53 | * | ||
| 54 | * Given a pointer to a source-selectable struct clk, read the hardware | ||
| 55 | * register and determine what its parent is currently set to. Update the | ||
| 56 | * clk->parent field with the appropriate clk ptr. | ||
| 57 | */ | ||
| 58 | void omap2_init_clksel_parent(struct clk *clk) | ||
| 51 | { | 59 | { |
| 52 | u32 div = PRCM_CLKSRC_CTRL; | 60 | const struct clksel *clks; |
| 53 | div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ | 61 | const struct clksel_rate *clkr; |
| 54 | div >>= clk->rate_offset; | 62 | u32 r, found = 0; |
| 55 | clk->rate = (clk->parent->rate / div); | 63 | |
| 56 | propagate_rate(clk); | 64 | if (!clk->clksel) |
| 65 | return; | ||
| 66 | |||
| 67 | r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; | ||
| 68 | r >>= __ffs(clk->clksel_mask); | ||
| 69 | |||
| 70 | for (clks = clk->clksel; clks->parent && !found; clks++) { | ||
| 71 | for (clkr = clks->rates; clkr->div && !found; clkr++) { | ||
| 72 | if ((clkr->flags & cpu_mask) && (clkr->val == r)) { | ||
| 73 | if (clk->parent != clks->parent) { | ||
| 74 | pr_debug("clock: inited %s parent " | ||
| 75 | "to %s (was %s)\n", | ||
| 76 | clk->name, clks->parent->name, | ||
| 77 | ((clk->parent) ? | ||
| 78 | clk->parent->name : "NULL")); | ||
| 79 | clk->parent = clks->parent; | ||
| 80 | }; | ||
| 81 | found = 1; | ||
| 82 | } | ||
| 83 | } | ||
| 84 | } | ||
| 85 | |||
| 86 | if (!found) | ||
| 87 | printk(KERN_ERR "clock: init parent: could not find " | ||
| 88 | "regval %0x for clock %s\n", r, clk->name); | ||
| 89 | |||
| 90 | return; | ||
| 57 | } | 91 | } |
| 58 | 92 | ||
| 59 | static u32 omap2_get_dpll_rate(struct clk * tclk) | 93 | /* Returns the DPLL rate */ |
| 94 | u32 omap2_get_dpll_rate(struct clk *clk) | ||
| 60 | { | 95 | { |
| 61 | long long dpll_clk; | 96 | long long dpll_clk; |
| 62 | int dpll_mult, dpll_div, amult; | 97 | u32 dpll_mult, dpll_div, dpll; |
| 98 | const struct dpll_data *dd; | ||
| 99 | |||
| 100 | dd = clk->dpll_data; | ||
| 101 | /* REVISIT: What do we return on error? */ | ||
| 102 | if (!dd) | ||
| 103 | return 0; | ||
| 104 | |||
| 105 | dpll = __raw_readl(dd->mult_div1_reg); | ||
| 106 | dpll_mult = dpll & dd->mult_mask; | ||
| 107 | dpll_mult >>= __ffs(dd->mult_mask); | ||
| 108 | dpll_div = dpll & dd->div1_mask; | ||
| 109 | dpll_div >>= __ffs(dd->div1_mask); | ||
| 63 | 110 | ||
| 64 | dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */ | 111 | dpll_clk = (long long)clk->parent->rate * dpll_mult; |
| 65 | dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */ | ||
| 66 | dpll_clk = (long long)tclk->parent->rate * dpll_mult; | ||
| 67 | do_div(dpll_clk, dpll_div + 1); | 112 | do_div(dpll_clk, dpll_div + 1); |
| 68 | amult = CM_CLKSEL2_PLL & 0x3; | ||
| 69 | dpll_clk *= amult; | ||
| 70 | 113 | ||
| 71 | return dpll_clk; | 114 | return dpll_clk; |
| 72 | } | 115 | } |
| 73 | 116 | ||
| 74 | static void omap2_followparent_recalc(struct clk *clk) | 117 | /* |
| 75 | { | 118 | * Used for clocks that have the same value as the parent clock, |
| 76 | followparent_recalc(clk); | 119 | * divided by some factor |
| 77 | } | 120 | */ |
| 78 | 121 | void omap2_fixed_divisor_recalc(struct clk *clk) | |
| 79 | static void omap2_propagate_rate(struct clk * clk) | ||
| 80 | { | 122 | { |
| 81 | if (!(clk->flags & RATE_FIXED)) | 123 | WARN_ON(!clk->fixed_div); |
| 82 | clk->rate = clk->parent->rate; | ||
| 83 | 124 | ||
| 84 | propagate_rate(clk); | 125 | clk->rate = clk->parent->rate / clk->fixed_div; |
| 85 | } | ||
| 86 | 126 | ||
| 87 | static void omap2_set_osc_ck(int enable) | 127 | if (clk->flags & RATE_PROPAGATES) |
| 88 | { | 128 | propagate_rate(clk); |
| 89 | if (enable) | ||
| 90 | PRCM_CLKSRC_CTRL &= ~(0x3 << 3); | ||
| 91 | else | ||
| 92 | PRCM_CLKSRC_CTRL |= 0x3 << 3; | ||
| 93 | } | 129 | } |
| 94 | 130 | ||
| 95 | /* Enable an APLL if off */ | 131 | /** |
| 96 | static void omap2_clk_fixed_enable(struct clk *clk) | 132 | * omap2_wait_clock_ready - wait for clock to enable |
| 133 | * @reg: physical address of clock IDLEST register | ||
| 134 | * @mask: value to mask against to determine if the clock is active | ||
| 135 | * @name: name of the clock (for printk) | ||
| 136 | * | ||
| 137 | * Returns 1 if the clock enabled in time, or 0 if it failed to enable | ||
| 138 | * in roughly MAX_CLOCK_ENABLE_WAIT microseconds. | ||
| 139 | */ | ||
| 140 | int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) | ||
| 97 | { | 141 | { |
| 98 | u32 cval, i=0; | 142 | int i = 0; |
| 143 | int ena = 0; | ||
| 99 | 144 | ||
| 100 | if (clk->enable_bit == 0xff) /* Parent will do it */ | 145 | /* |
| 101 | return; | 146 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. |
| 147 | * 34xx reverses this, just to keep us on our toes | ||
| 148 | */ | ||
| 149 | if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) { | ||
| 150 | ena = mask; | ||
| 151 | } else if (cpu_mask & RATE_IN_343X) { | ||
| 152 | ena = 0; | ||
| 153 | } | ||
| 102 | 154 | ||
| 103 | cval = CM_CLKEN_PLL; | 155 | /* Wait for lock */ |
| 156 | while (((__raw_readl(reg) & mask) != ena) && | ||
| 157 | (i++ < MAX_CLOCK_ENABLE_WAIT)) { | ||
| 158 | udelay(1); | ||
| 159 | } | ||
| 104 | 160 | ||
| 105 | if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit)) | 161 | if (i < MAX_CLOCK_ENABLE_WAIT) |
| 106 | return; | 162 | pr_debug("Clock %s stable after %d loops\n", name, i); |
| 163 | else | ||
| 164 | printk(KERN_ERR "Clock %s didn't enable in %d tries\n", | ||
| 165 | name, MAX_CLOCK_ENABLE_WAIT); | ||
| 107 | 166 | ||
| 108 | cval &= ~(0x3 << clk->enable_bit); | ||
| 109 | cval |= (0x3 << clk->enable_bit); | ||
| 110 | CM_CLKEN_PLL = cval; | ||
| 111 | 167 | ||
| 112 | if (clk == &apll96_ck) | 168 | return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0; |
| 113 | cval = (1 << 8); | 169 | }; |
| 114 | else if (clk == &apll54_ck) | ||
| 115 | cval = (1 << 6); | ||
| 116 | 170 | ||
| 117 | while (!(CM_IDLEST_CKGEN & cval)) { /* Wait for lock */ | ||
| 118 | ++i; | ||
| 119 | udelay(1); | ||
| 120 | if (i == 100000) { | ||
| 121 | printk(KERN_ERR "Clock %s didn't lock\n", clk->name); | ||
| 122 | break; | ||
| 123 | } | ||
| 124 | } | ||
| 125 | } | ||
| 126 | 171 | ||
| 172 | /* | ||
| 173 | * Note: We don't need special code here for INVERT_ENABLE | ||
| 174 | * for the time being since INVERT_ENABLE only applies to clocks enabled by | ||
| 175 | * CM_CLKEN_PLL | ||
| 176 | */ | ||
| 127 | static void omap2_clk_wait_ready(struct clk *clk) | 177 | static void omap2_clk_wait_ready(struct clk *clk) |
| 128 | { | 178 | { |
| 129 | unsigned long reg, other_reg, st_reg; | 179 | void __iomem *reg, *other_reg, *st_reg; |
| 130 | u32 bit; | 180 | u32 bit; |
| 131 | int i; | 181 | |
| 132 | 182 | /* | |
| 133 | reg = (unsigned long) clk->enable_reg; | 183 | * REVISIT: This code is pretty ugly. It would be nice to generalize |
| 134 | if (reg == (unsigned long) &CM_FCLKEN1_CORE || | 184 | * it and pull it into struct clk itself somehow. |
| 135 | reg == (unsigned long) &CM_FCLKEN2_CORE) | 185 | */ |
| 136 | other_reg = (reg & ~0xf0) | 0x10; | 186 | reg = clk->enable_reg; |
| 137 | else if (reg == (unsigned long) &CM_ICLKEN1_CORE || | 187 | if ((((u32)reg & 0xff) >= CM_FCLKEN1) && |
| 138 | reg == (unsigned long) &CM_ICLKEN2_CORE) | 188 | (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2)) |
| 139 | other_reg = (reg & ~0xf0) | 0x00; | 189 | other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */ |
| 190 | else if ((((u32)reg & 0xff) >= CM_ICLKEN1) && | ||
| 191 | (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4)) | ||
| 192 | other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */ | ||
| 140 | else | 193 | else |
| 141 | return; | 194 | return; |
| 142 | 195 | ||
| 196 | /* REVISIT: What are the appropriate exclusions for 34XX? */ | ||
| 143 | /* No check for DSS or cam clocks */ | 197 | /* No check for DSS or cam clocks */ |
| 144 | if ((reg & 0x0f) == 0) { | 198 | if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */ |
| 145 | if (clk->enable_bit <= 1 || clk->enable_bit == 31) | 199 | if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT || |
| 200 | clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT || | ||
| 201 | clk->enable_bit == OMAP24XX_EN_CAM_SHIFT) | ||
| 146 | return; | 202 | return; |
| 147 | } | 203 | } |
| 148 | 204 | ||
| 205 | /* REVISIT: What are the appropriate exclusions for 34XX? */ | ||
| 206 | /* OMAP3: ignore DSS-mod clocks */ | ||
| 207 | if (cpu_is_omap34xx() && | ||
| 208 | (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0))) | ||
| 209 | return; | ||
| 210 | |||
| 149 | /* Check if both functional and interface clocks | 211 | /* Check if both functional and interface clocks |
| 150 | * are running. */ | 212 | * are running. */ |
| 151 | bit = 1 << clk->enable_bit; | 213 | bit = 1 << clk->enable_bit; |
| 152 | if (!(__raw_readl(other_reg) & bit)) | 214 | if (!(__raw_readl(other_reg) & bit)) |
| 153 | return; | 215 | return; |
| 154 | st_reg = (other_reg & ~0xf0) | 0x20; | 216 | st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */ |
| 155 | i = 0; | 217 | |
| 156 | while (!(__raw_readl(st_reg) & bit)) { | 218 | omap2_wait_clock_ready(st_reg, bit, clk->name); |
| 157 | i++; | ||
| 158 | if (i == 100000) { | ||
| 159 | printk(KERN_ERR "Timeout enabling clock %s\n", clk->name); | ||
| 160 | break; | ||
| 161 | } | ||
| 162 | } | ||
| 163 | if (i) | ||
| 164 | pr_debug("Clock %s stable after %d loops\n", clk->name, i); | ||
| 165 | } | 219 | } |
| 166 | 220 | ||
| 167 | /* Enables clock without considering parent dependencies or use count | 221 | /* Enables clock without considering parent dependencies or use count |
| 168 | * REVISIT: Maybe change this to use clk->enable like on omap1? | 222 | * REVISIT: Maybe change this to use clk->enable like on omap1? |
| 169 | */ | 223 | */ |
| 170 | static int _omap2_clk_enable(struct clk * clk) | 224 | int _omap2_clk_enable(struct clk *clk) |
| 171 | { | 225 | { |
| 172 | u32 regval32; | 226 | u32 regval32; |
| 173 | 227 | ||
| 174 | if (clk->flags & ALWAYS_ENABLED) | 228 | if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) |
| 175 | return 0; | 229 | return 0; |
| 176 | 230 | ||
| 177 | if (unlikely(clk == &osc_ck)) { | 231 | if (clk->enable) |
| 178 | omap2_set_osc_ck(1); | 232 | return clk->enable(clk); |
| 179 | return 0; | ||
| 180 | } | ||
| 181 | 233 | ||
| 182 | if (unlikely(clk->enable_reg == 0)) { | 234 | if (unlikely(clk->enable_reg == 0)) { |
| 183 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", | 235 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", |
| 184 | clk->name); | 236 | clk->name); |
| 185 | return 0; | 237 | return 0; /* REVISIT: -EINVAL */ |
| 186 | } | ||
| 187 | |||
| 188 | if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) { | ||
| 189 | omap2_clk_fixed_enable(clk); | ||
| 190 | return 0; | ||
| 191 | } | 238 | } |
| 192 | 239 | ||
| 193 | regval32 = __raw_readl(clk->enable_reg); | 240 | regval32 = __raw_readl(clk->enable_reg); |
| 194 | regval32 |= (1 << clk->enable_bit); | 241 | if (clk->flags & INVERT_ENABLE) |
| 242 | regval32 &= ~(1 << clk->enable_bit); | ||
| 243 | else | ||
| 244 | regval32 |= (1 << clk->enable_bit); | ||
| 195 | __raw_writel(regval32, clk->enable_reg); | 245 | __raw_writel(regval32, clk->enable_reg); |
| 196 | wmb(); | 246 | wmb(); |
| 197 | 247 | ||
| @@ -200,44 +250,48 @@ static int _omap2_clk_enable(struct clk * clk) | |||
| 200 | return 0; | 250 | return 0; |
| 201 | } | 251 | } |
| 202 | 252 | ||
| 203 | /* Stop APLL */ | ||
| 204 | static void omap2_clk_fixed_disable(struct clk *clk) | ||
| 205 | { | ||
| 206 | u32 cval; | ||
| 207 | |||
| 208 | if(clk->enable_bit == 0xff) /* let parent off do it */ | ||
| 209 | return; | ||
| 210 | |||
| 211 | cval = CM_CLKEN_PLL; | ||
| 212 | cval &= ~(0x3 << clk->enable_bit); | ||
| 213 | CM_CLKEN_PLL = cval; | ||
| 214 | } | ||
| 215 | |||
| 216 | /* Disables clock without considering parent dependencies or use count */ | 253 | /* Disables clock without considering parent dependencies or use count */ |
| 217 | static void _omap2_clk_disable(struct clk *clk) | 254 | void _omap2_clk_disable(struct clk *clk) |
| 218 | { | 255 | { |
| 219 | u32 regval32; | 256 | u32 regval32; |
| 220 | 257 | ||
| 221 | if (unlikely(clk == &osc_ck)) { | 258 | if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) |
| 222 | omap2_set_osc_ck(0); | ||
| 223 | return; | 259 | return; |
| 224 | } | ||
| 225 | 260 | ||
| 226 | if (clk->enable_reg == 0) | 261 | if (clk->disable) { |
| 262 | clk->disable(clk); | ||
| 227 | return; | 263 | return; |
| 264 | } | ||
| 228 | 265 | ||
| 229 | if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) { | 266 | if (clk->enable_reg == 0) { |
| 230 | omap2_clk_fixed_disable(clk); | 267 | /* |
| 268 | * 'Independent' here refers to a clock which is not | ||
| 269 | * controlled by its parent. | ||
| 270 | */ | ||
| 271 | printk(KERN_ERR "clock: clk_disable called on independent " | ||
| 272 | "clock %s which has no enable_reg\n", clk->name); | ||
| 231 | return; | 273 | return; |
| 232 | } | 274 | } |
| 233 | 275 | ||
| 234 | regval32 = __raw_readl(clk->enable_reg); | 276 | regval32 = __raw_readl(clk->enable_reg); |
| 235 | regval32 &= ~(1 << clk->enable_bit); | 277 | if (clk->flags & INVERT_ENABLE) |
| 278 | regval32 |= (1 << clk->enable_bit); | ||
| 279 | else | ||
| 280 | regval32 &= ~(1 << clk->enable_bit); | ||
| 236 | __raw_writel(regval32, clk->enable_reg); | 281 | __raw_writel(regval32, clk->enable_reg); |
| 237 | wmb(); | 282 | wmb(); |
| 238 | } | 283 | } |
| 239 | 284 | ||
| 240 | static int omap2_clk_enable(struct clk *clk) | 285 | void omap2_clk_disable(struct clk *clk) |
| 286 | { | ||
| 287 | if (clk->usecount > 0 && !(--clk->usecount)) { | ||
| 288 | _omap2_clk_disable(clk); | ||
| 289 | if (likely((u32)clk->parent)) | ||
| 290 | omap2_clk_disable(clk->parent); | ||
| 291 | } | ||
| 292 | } | ||
| 293 | |||
| 294 | int omap2_clk_enable(struct clk *clk) | ||
| 241 | { | 295 | { |
| 242 | int ret = 0; | 296 | int ret = 0; |
| 243 | 297 | ||
| @@ -261,519 +315,314 @@ static int omap2_clk_enable(struct clk *clk) | |||
| 261 | return ret; | 315 | return ret; |
| 262 | } | 316 | } |
| 263 | 317 | ||
| 264 | static void omap2_clk_disable(struct clk *clk) | ||
| 265 | { | ||
| 266 | if (clk->usecount > 0 && !(--clk->usecount)) { | ||
| 267 | _omap2_clk_disable(clk); | ||
| 268 | if (likely((u32)clk->parent)) | ||
| 269 | omap2_clk_disable(clk->parent); | ||
| 270 | } | ||
| 271 | } | ||
| 272 | |||
| 273 | /* | ||
| 274 | * Uses the current prcm set to tell if a rate is valid. | ||
| 275 | * You can go slower, but not faster within a given rate set. | ||
| 276 | */ | ||
| 277 | static u32 omap2_dpll_round_rate(unsigned long target_rate) | ||
| 278 | { | ||
| 279 | u32 high, low; | ||
| 280 | |||
| 281 | if ((CM_CLKSEL2_PLL & 0x3) == 1) { /* DPLL clockout */ | ||
| 282 | high = curr_prcm_set->dpll_speed * 2; | ||
| 283 | low = curr_prcm_set->dpll_speed; | ||
| 284 | } else { /* DPLL clockout x 2 */ | ||
| 285 | high = curr_prcm_set->dpll_speed; | ||
| 286 | low = curr_prcm_set->dpll_speed / 2; | ||
| 287 | } | ||
| 288 | |||
| 289 | #ifdef DOWN_VARIABLE_DPLL | ||
| 290 | if (target_rate > high) | ||
| 291 | return high; | ||
| 292 | else | ||
| 293 | return target_rate; | ||
| 294 | #else | ||
| 295 | if (target_rate > low) | ||
| 296 | return high; | ||
| 297 | else | ||
| 298 | return low; | ||
| 299 | #endif | ||
| 300 | |||
| 301 | } | ||
| 302 | |||
| 303 | /* | 318 | /* |
| 304 | * Used for clocks that are part of CLKSEL_xyz governed clocks. | 319 | * Used for clocks that are part of CLKSEL_xyz governed clocks. |
| 305 | * REVISIT: Maybe change to use clk->enable() functions like on omap1? | 320 | * REVISIT: Maybe change to use clk->enable() functions like on omap1? |
| 306 | */ | 321 | */ |
| 307 | static void omap2_clksel_recalc(struct clk * clk) | 322 | void omap2_clksel_recalc(struct clk *clk) |
| 308 | { | 323 | { |
| 309 | u32 fixed = 0, div = 0; | 324 | u32 div = 0; |
| 310 | 325 | ||
| 311 | if (clk == &dpll_ck) { | 326 | pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); |
| 312 | clk->rate = omap2_get_dpll_rate(clk); | ||
| 313 | fixed = 1; | ||
| 314 | div = 0; | ||
| 315 | } | ||
| 316 | 327 | ||
| 317 | if (clk == &iva1_mpu_int_ifck) { | 328 | div = omap2_clksel_get_divisor(clk); |
| 318 | div = 2; | 329 | if (div == 0) |
| 319 | fixed = 1; | ||
| 320 | } | ||
| 321 | |||
| 322 | if ((clk == &dss1_fck) && ((CM_CLKSEL1_CORE & (0x1f << 8)) == 0)) { | ||
| 323 | clk->rate = sys_ck.rate; | ||
| 324 | return; | 330 | return; |
| 325 | } | ||
| 326 | 331 | ||
| 327 | if (!fixed) { | 332 | if (unlikely(clk->rate == clk->parent->rate / div)) |
| 328 | div = omap2_clksel_get_divisor(clk); | 333 | return; |
| 329 | if (div == 0) | 334 | clk->rate = clk->parent->rate / div; |
| 330 | return; | ||
| 331 | } | ||
| 332 | 335 | ||
| 333 | if (div != 0) { | 336 | pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div); |
| 334 | if (unlikely(clk->rate == clk->parent->rate / div)) | ||
| 335 | return; | ||
| 336 | clk->rate = clk->parent->rate / div; | ||
| 337 | } | ||
| 338 | 337 | ||
| 339 | if (unlikely(clk->flags & RATE_PROPAGATES)) | 338 | if (unlikely(clk->flags & RATE_PROPAGATES)) |
| 340 | propagate_rate(clk); | 339 | propagate_rate(clk); |
| 341 | } | 340 | } |
| 342 | 341 | ||
| 343 | /* | 342 | /** |
| 344 | * Finds best divider value in an array based on the source and target | 343 | * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent |
| 345 | * rates. The divider array must be sorted with smallest divider first. | 344 | * @clk: OMAP struct clk ptr to inspect |
| 345 | * @src_clk: OMAP struct clk ptr of the parent clk to search for | ||
| 346 | * | ||
| 347 | * Scan the struct clksel array associated with the clock to find | ||
| 348 | * the element associated with the supplied parent clock address. | ||
| 349 | * Returns a pointer to the struct clksel on success or NULL on error. | ||
| 346 | */ | 350 | */ |
| 347 | static inline u32 omap2_divider_from_table(u32 size, u32 *div_array, | 351 | const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, |
| 348 | u32 src_rate, u32 tgt_rate) | 352 | struct clk *src_clk) |
| 349 | { | 353 | { |
| 350 | int i, test_rate; | 354 | const struct clksel *clks; |
| 351 | 355 | ||
| 352 | if (div_array == NULL) | 356 | if (!clk->clksel) |
| 353 | return ~1; | 357 | return NULL; |
| 354 | 358 | ||
| 355 | for (i=0; i < size; i++) { | 359 | for (clks = clk->clksel; clks->parent; clks++) { |
| 356 | test_rate = src_rate / *div_array; | 360 | if (clks->parent == src_clk) |
| 357 | if (test_rate <= tgt_rate) | 361 | break; /* Found the requested parent */ |
| 358 | return *div_array; | ||
| 359 | ++div_array; | ||
| 360 | } | 362 | } |
| 361 | 363 | ||
| 362 | return ~0; /* No acceptable divider */ | 364 | if (!clks->parent) { |
| 365 | printk(KERN_ERR "clock: Could not find parent clock %s in " | ||
| 366 | "clksel array of clock %s\n", src_clk->name, | ||
| 367 | clk->name); | ||
| 368 | return NULL; | ||
| 369 | } | ||
| 370 | |||
| 371 | return clks; | ||
| 363 | } | 372 | } |
| 364 | 373 | ||
| 365 | /* | 374 | /** |
| 366 | * Find divisor for the given clock and target rate. | 375 | * omap2_clksel_round_rate_div - find divisor for the given clock and rate |
| 376 | * @clk: OMAP struct clk to use | ||
| 377 | * @target_rate: desired clock rate | ||
| 378 | * @new_div: ptr to where we should store the divisor | ||
| 367 | * | 379 | * |
| 380 | * Finds 'best' divider value in an array based on the source and target | ||
| 381 | * rates. The divider array must be sorted with smallest divider first. | ||
| 368 | * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, | 382 | * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, |
| 369 | * they are only settable as part of virtual_prcm set. | 383 | * they are only settable as part of virtual_prcm set. |
| 384 | * | ||
| 385 | * Returns the rounded clock rate or returns 0xffffffff on error. | ||
| 370 | */ | 386 | */ |
| 371 | static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate, | 387 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, |
| 372 | u32 *new_div) | 388 | u32 *new_div) |
| 373 | { | 389 | { |
| 374 | u32 gfx_div[] = {2, 3, 4}; | 390 | unsigned long test_rate; |
| 375 | u32 sysclkout_div[] = {1, 2, 4, 8, 16}; | 391 | const struct clksel *clks; |
| 376 | u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16}; | 392 | const struct clksel_rate *clkr; |
| 377 | u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18}; | 393 | u32 last_div = 0; |
| 378 | u32 best_div = ~0, asize = 0; | 394 | |
| 379 | u32 *div_array = NULL; | 395 | printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n", |
| 380 | 396 | clk->name, target_rate); | |
| 381 | switch (tclk->flags & SRC_RATE_SEL_MASK) { | 397 | |
| 382 | case CM_GFX_SEL1: | 398 | *new_div = 1; |
| 383 | asize = 3; | 399 | |
| 384 | div_array = gfx_div; | 400 | clks = omap2_get_clksel_by_parent(clk, clk->parent); |
| 385 | break; | 401 | if (clks == NULL) |
| 386 | case CM_PLL_SEL1: | 402 | return ~0; |
| 387 | return omap2_dpll_round_rate(target_rate); | 403 | |
| 388 | case CM_SYSCLKOUT_SEL1: | 404 | for (clkr = clks->rates; clkr->div; clkr++) { |
| 389 | asize = 5; | 405 | if (!(clkr->flags & cpu_mask)) |
| 390 | div_array = sysclkout_div; | 406 | continue; |
| 391 | break; | 407 | |
| 392 | case CM_CORE_SEL1: | 408 | /* Sanity check */ |
| 393 | if(tclk == &dss1_fck){ | 409 | if (clkr->div <= last_div) |
| 394 | if(tclk->parent == &core_ck){ | 410 | printk(KERN_ERR "clock: clksel_rate table not sorted " |
| 395 | asize = 10; | 411 | "for clock %s", clk->name); |
| 396 | div_array = dss1_div; | 412 | |
| 397 | } else { | 413 | last_div = clkr->div; |
| 398 | *new_div = 0; /* fixed clk */ | 414 | |
| 399 | return(tclk->parent->rate); | 415 | test_rate = clk->parent->rate / clkr->div; |
| 400 | } | 416 | |
| 401 | } else if((tclk == &vlynq_fck) && cpu_is_omap2420()){ | 417 | if (test_rate <= target_rate) |
| 402 | if(tclk->parent == &core_ck){ | 418 | break; /* found it */ |
| 403 | asize = 10; | ||
| 404 | div_array = vylnq_div; | ||
| 405 | } else { | ||
| 406 | *new_div = 0; /* fixed clk */ | ||
| 407 | return(tclk->parent->rate); | ||
| 408 | } | ||
| 409 | } | ||
| 410 | break; | ||
| 411 | } | 419 | } |
| 412 | 420 | ||
| 413 | best_div = omap2_divider_from_table(asize, div_array, | 421 | if (!clkr->div) { |
| 414 | tclk->parent->rate, target_rate); | 422 | printk(KERN_ERR "clock: Could not find divisor for target " |
| 415 | if (best_div == ~0){ | 423 | "rate %ld for clock %s parent %s\n", target_rate, |
| 416 | *new_div = 1; | 424 | clk->name, clk->parent->name); |
| 417 | return best_div; /* signal error */ | 425 | return ~0; |
| 418 | } | 426 | } |
| 419 | 427 | ||
| 420 | *new_div = best_div; | 428 | *new_div = clkr->div; |
| 421 | return (tclk->parent->rate / best_div); | 429 | |
| 430 | printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div, | ||
| 431 | (clk->parent->rate / clkr->div)); | ||
| 432 | |||
| 433 | return (clk->parent->rate / clkr->div); | ||
| 422 | } | 434 | } |
| 423 | 435 | ||
| 424 | /* Given a clock and a rate apply a clock specific rounding function */ | 436 | /** |
| 425 | static long omap2_clk_round_rate(struct clk *clk, unsigned long rate) | 437 | * omap2_clksel_round_rate - find rounded rate for the given clock and rate |
| 438 | * @clk: OMAP struct clk to use | ||
| 439 | * @target_rate: desired clock rate | ||
| 440 | * | ||
| 441 | * Compatibility wrapper for OMAP clock framework | ||
| 442 | * Finds best target rate based on the source clock and possible dividers. | ||
| 443 | * rates. The divider array must be sorted with smallest divider first. | ||
| 444 | * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, | ||
| 445 | * they are only settable as part of virtual_prcm set. | ||
| 446 | * | ||
| 447 | * Returns the rounded clock rate or returns 0xffffffff on error. | ||
| 448 | */ | ||
| 449 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) | ||
| 426 | { | 450 | { |
| 427 | u32 new_div = 0; | 451 | u32 new_div; |
| 428 | int valid_rate; | ||
| 429 | 452 | ||
| 430 | if (clk->flags & RATE_FIXED) | 453 | return omap2_clksel_round_rate_div(clk, target_rate, &new_div); |
| 431 | return clk->rate; | 454 | } |
| 432 | 455 | ||
| 433 | if (clk->flags & RATE_CKCTL) { | ||
| 434 | valid_rate = omap2_clksel_round_rate(clk, rate, &new_div); | ||
| 435 | return valid_rate; | ||
| 436 | } | ||
| 437 | 456 | ||
| 457 | /* Given a clock and a rate apply a clock specific rounding function */ | ||
| 458 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate) | ||
| 459 | { | ||
| 438 | if (clk->round_rate != 0) | 460 | if (clk->round_rate != 0) |
| 439 | return clk->round_rate(clk, rate); | 461 | return clk->round_rate(clk, rate); |
| 440 | 462 | ||
| 463 | if (clk->flags & RATE_FIXED) | ||
| 464 | printk(KERN_ERR "clock: generic omap2_clk_round_rate called " | ||
| 465 | "on fixed-rate clock %s\n", clk->name); | ||
| 466 | |||
| 441 | return clk->rate; | 467 | return clk->rate; |
| 442 | } | 468 | } |
| 443 | 469 | ||
| 444 | /* | 470 | /** |
| 445 | * Check the DLL lock state, and return tue if running in unlock mode. | 471 | * omap2_clksel_to_divisor() - turn clksel field value into integer divider |
| 446 | * This is needed to compensate for the shifted DLL value in unlock mode. | 472 | * @clk: OMAP struct clk to use |
| 473 | * @field_val: register field value to find | ||
| 474 | * | ||
| 475 | * Given a struct clk of a rate-selectable clksel clock, and a register field | ||
| 476 | * value to search for, find the corresponding clock divisor. The register | ||
| 477 | * field value should be pre-masked and shifted down so the LSB is at bit 0 | ||
| 478 | * before calling. Returns 0 on error | ||
| 447 | */ | 479 | */ |
| 448 | static u32 omap2_dll_force_needed(void) | 480 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) |
| 449 | { | 481 | { |
| 450 | u32 dll_state = SDRC_DLLA_CTRL; /* dlla and dllb are a set */ | 482 | const struct clksel *clks; |
| 483 | const struct clksel_rate *clkr; | ||
| 451 | 484 | ||
| 452 | if ((dll_state & (1 << 2)) == (1 << 2)) | 485 | clks = omap2_get_clksel_by_parent(clk, clk->parent); |
| 453 | return 1; | 486 | if (clks == NULL) |
| 454 | else | ||
| 455 | return 0; | 487 | return 0; |
| 456 | } | ||
| 457 | 488 | ||
| 458 | static u32 omap2_reprogram_sdrc(u32 level, u32 force) | 489 | for (clkr = clks->rates; clkr->div; clkr++) { |
| 459 | { | 490 | if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) |
| 460 | u32 slow_dll_ctrl, fast_dll_ctrl, m_type; | 491 | break; |
| 461 | u32 prev = curr_perf_level, flags; | ||
| 462 | |||
| 463 | if ((curr_perf_level == level) && !force) | ||
| 464 | return prev; | ||
| 465 | |||
| 466 | m_type = omap2_memory_get_type(); | ||
| 467 | slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl(); | ||
| 468 | fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl(); | ||
| 469 | |||
| 470 | if (level == PRCM_HALF_SPEED) { | ||
| 471 | local_irq_save(flags); | ||
| 472 | PRCM_VOLTSETUP = 0xffff; | ||
| 473 | omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED, | ||
| 474 | slow_dll_ctrl, m_type); | ||
| 475 | curr_perf_level = PRCM_HALF_SPEED; | ||
| 476 | local_irq_restore(flags); | ||
| 477 | } | 492 | } |
| 478 | if (level == PRCM_FULL_SPEED) { | 493 | |
| 479 | local_irq_save(flags); | 494 | if (!clkr->div) { |
| 480 | PRCM_VOLTSETUP = 0xffff; | 495 | printk(KERN_ERR "clock: Could not find fieldval %d for " |
| 481 | omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED, | 496 | "clock %s parent %s\n", field_val, clk->name, |
| 482 | fast_dll_ctrl, m_type); | 497 | clk->parent->name); |
| 483 | curr_perf_level = PRCM_FULL_SPEED; | 498 | return 0; |
| 484 | local_irq_restore(flags); | ||
| 485 | } | 499 | } |
| 486 | 500 | ||
| 487 | return prev; | 501 | return clkr->div; |
| 488 | } | 502 | } |
| 489 | 503 | ||
| 490 | static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate) | 504 | /** |
| 505 | * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value | ||
| 506 | * @clk: OMAP struct clk to use | ||
| 507 | * @div: integer divisor to search for | ||
| 508 | * | ||
| 509 | * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, | ||
| 510 | * find the corresponding register field value. The return register value is | ||
| 511 | * the value before left-shifting. Returns 0xffffffff on error | ||
| 512 | */ | ||
| 513 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) | ||
| 491 | { | 514 | { |
| 492 | u32 flags, cur_rate, low, mult, div, valid_rate, done_rate; | 515 | const struct clksel *clks; |
| 493 | u32 bypass = 0; | 516 | const struct clksel_rate *clkr; |
| 494 | struct prcm_config tmpset; | ||
| 495 | int ret = -EINVAL; | ||
| 496 | 517 | ||
| 497 | local_irq_save(flags); | 518 | /* should never happen */ |
| 498 | cur_rate = omap2_get_dpll_rate(&dpll_ck); | 519 | WARN_ON(div == 0); |
| 499 | mult = CM_CLKSEL2_PLL & 0x3; | ||
| 500 | |||
| 501 | if ((rate == (cur_rate / 2)) && (mult == 2)) { | ||
| 502 | omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1); | ||
| 503 | } else if ((rate == (cur_rate * 2)) && (mult == 1)) { | ||
| 504 | omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); | ||
| 505 | } else if (rate != cur_rate) { | ||
| 506 | valid_rate = omap2_dpll_round_rate(rate); | ||
| 507 | if (valid_rate != rate) | ||
| 508 | goto dpll_exit; | ||
| 509 | |||
| 510 | if ((CM_CLKSEL2_PLL & 0x3) == 1) | ||
| 511 | low = curr_prcm_set->dpll_speed; | ||
| 512 | else | ||
| 513 | low = curr_prcm_set->dpll_speed / 2; | ||
| 514 | |||
| 515 | tmpset.cm_clksel1_pll = CM_CLKSEL1_PLL; | ||
| 516 | tmpset.cm_clksel1_pll &= ~(0x3FFF << 8); | ||
| 517 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); | ||
| 518 | tmpset.cm_clksel2_pll = CM_CLKSEL2_PLL; | ||
| 519 | tmpset.cm_clksel2_pll &= ~0x3; | ||
| 520 | if (rate > low) { | ||
| 521 | tmpset.cm_clksel2_pll |= 0x2; | ||
| 522 | mult = ((rate / 2) / 1000000); | ||
| 523 | done_rate = PRCM_FULL_SPEED; | ||
| 524 | } else { | ||
| 525 | tmpset.cm_clksel2_pll |= 0x1; | ||
| 526 | mult = (rate / 1000000); | ||
| 527 | done_rate = PRCM_HALF_SPEED; | ||
| 528 | } | ||
| 529 | tmpset.cm_clksel1_pll |= ((div << 8) | (mult << 12)); | ||
| 530 | |||
| 531 | /* Worst case */ | ||
| 532 | tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS; | ||
| 533 | |||
| 534 | if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ | ||
| 535 | bypass = 1; | ||
| 536 | 520 | ||
| 537 | omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); /* For init_mem */ | 521 | clks = omap2_get_clksel_by_parent(clk, clk->parent); |
| 538 | 522 | if (clks == NULL) | |
| 539 | /* Force dll lock mode */ | 523 | return 0; |
| 540 | omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, | ||
| 541 | bypass); | ||
| 542 | 524 | ||
| 543 | /* Errata: ret dll entry state */ | 525 | for (clkr = clks->rates; clkr->div; clkr++) { |
| 544 | omap2_init_memory_params(omap2_dll_force_needed()); | 526 | if ((clkr->flags & cpu_mask) && (clkr->div == div)) |
| 545 | omap2_reprogram_sdrc(done_rate, 0); | 527 | break; |
| 546 | } | 528 | } |
| 547 | omap2_clksel_recalc(&dpll_ck); | ||
| 548 | ret = 0; | ||
| 549 | 529 | ||
| 550 | dpll_exit: | 530 | if (!clkr->div) { |
| 551 | local_irq_restore(flags); | 531 | printk(KERN_ERR "clock: Could not find divisor %d for " |
| 552 | return(ret); | 532 | "clock %s parent %s\n", div, clk->name, |
| 553 | } | 533 | clk->parent->name); |
| 534 | return 0; | ||
| 535 | } | ||
| 554 | 536 | ||
| 555 | /* Just return the MPU speed */ | 537 | return clkr->val; |
| 556 | static void omap2_mpu_recalc(struct clk * clk) | ||
| 557 | { | ||
| 558 | clk->rate = curr_prcm_set->mpu_speed; | ||
| 559 | } | 538 | } |
| 560 | 539 | ||
| 561 | /* | 540 | /** |
| 562 | * Look for a rate equal or less than the target rate given a configuration set. | 541 | * omap2_get_clksel - find clksel register addr & field mask for a clk |
| 542 | * @clk: struct clk to use | ||
| 543 | * @field_mask: ptr to u32 to store the register field mask | ||
| 563 | * | 544 | * |
| 564 | * What's not entirely clear is "which" field represents the key field. | 545 | * Returns the address of the clksel register upon success or NULL on error. |
| 565 | * Some might argue L3-DDR, others ARM, others IVA. This code is simple and | ||
| 566 | * just uses the ARM rates. | ||
| 567 | */ | 546 | */ |
| 568 | static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate) | 547 | void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) |
| 569 | { | 548 | { |
| 570 | struct prcm_config * ptr; | 549 | if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0))) |
| 571 | long highest_rate; | 550 | return NULL; |
| 572 | |||
| 573 | if (clk != &virt_prcm_set) | ||
| 574 | return -EINVAL; | ||
| 575 | |||
| 576 | highest_rate = -EINVAL; | ||
| 577 | |||
| 578 | for (ptr = rate_table; ptr->mpu_speed; ptr++) { | ||
| 579 | if (ptr->xtal_speed != sys_ck.rate) | ||
| 580 | continue; | ||
| 581 | 551 | ||
| 582 | highest_rate = ptr->mpu_speed; | 552 | *field_mask = clk->clksel_mask; |
| 583 | 553 | ||
| 584 | /* Can check only after xtal frequency check */ | 554 | return clk->clksel_reg; |
| 585 | if (ptr->mpu_speed <= rate) | ||
| 586 | break; | ||
| 587 | } | ||
| 588 | return highest_rate; | ||
| 589 | } | 555 | } |
| 590 | 556 | ||
| 591 | /* | 557 | /** |
| 592 | * omap2_convert_field_to_div() - turn field value into integer divider | 558 | * omap2_clksel_get_divisor - get current divider applied to parent clock. |
| 559 | * @clk: OMAP struct clk to use. | ||
| 560 | * | ||
| 561 | * Returns the integer divisor upon success or 0 on error. | ||
| 593 | */ | 562 | */ |
| 594 | static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val) | 563 | u32 omap2_clksel_get_divisor(struct clk *clk) |
| 595 | { | 564 | { |
| 596 | u32 i; | 565 | u32 field_mask, field_val; |
| 597 | u32 clkout_array[] = {1, 2, 4, 8, 16}; | 566 | void __iomem *div_addr; |
| 598 | 567 | ||
| 599 | if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) { | 568 | div_addr = omap2_get_clksel(clk, &field_mask); |
| 600 | for (i = 0; i < 5; i++) { | 569 | if (div_addr == 0) |
| 601 | if (field_val == i) | 570 | return 0; |
| 602 | return clkout_array[i]; | 571 | |
| 603 | } | 572 | field_val = __raw_readl(div_addr) & field_mask; |
| 604 | return ~0; | 573 | field_val >>= __ffs(field_mask); |
| 605 | } else | 574 | |
| 606 | return field_val; | 575 | return omap2_clksel_to_divisor(clk, field_val); |
| 607 | } | 576 | } |
| 608 | 577 | ||
| 609 | /* | 578 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) |
| 610 | * Returns the CLKSEL divider register value | ||
| 611 | * REVISIT: This should be cleaned up to work nicely with void __iomem * | ||
| 612 | */ | ||
| 613 | static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask, | ||
| 614 | struct clk *clk) | ||
| 615 | { | 579 | { |
| 616 | int ret = ~0; | 580 | u32 field_mask, field_val, reg_val, validrate, new_div = 0; |
| 617 | u32 reg_val, div_off; | 581 | void __iomem *div_addr; |
| 618 | u32 div_addr = 0; | ||
| 619 | u32 mask = ~0; | ||
| 620 | |||
| 621 | div_off = clk->rate_offset; | ||
| 622 | |||
| 623 | switch ((*div_sel & SRC_RATE_SEL_MASK)) { | ||
| 624 | case CM_MPU_SEL1: | ||
| 625 | div_addr = (u32)&CM_CLKSEL_MPU; | ||
| 626 | mask = 0x1f; | ||
| 627 | break; | ||
| 628 | case CM_DSP_SEL1: | ||
| 629 | div_addr = (u32)&CM_CLKSEL_DSP; | ||
| 630 | if (cpu_is_omap2420()) { | ||
| 631 | if ((div_off == 0) || (div_off == 8)) | ||
| 632 | mask = 0x1f; | ||
| 633 | else if (div_off == 5) | ||
| 634 | mask = 0x3; | ||
| 635 | } else if (cpu_is_omap2430()) { | ||
| 636 | if (div_off == 0) | ||
| 637 | mask = 0x1f; | ||
| 638 | else if (div_off == 5) | ||
| 639 | mask = 0x3; | ||
| 640 | } | ||
| 641 | break; | ||
| 642 | case CM_GFX_SEL1: | ||
| 643 | div_addr = (u32)&CM_CLKSEL_GFX; | ||
| 644 | if (div_off == 0) | ||
| 645 | mask = 0x7; | ||
| 646 | break; | ||
| 647 | case CM_MODEM_SEL1: | ||
| 648 | div_addr = (u32)&CM_CLKSEL_MDM; | ||
| 649 | if (div_off == 0) | ||
| 650 | mask = 0xf; | ||
| 651 | break; | ||
| 652 | case CM_SYSCLKOUT_SEL1: | ||
| 653 | div_addr = (u32)&PRCM_CLKOUT_CTRL; | ||
| 654 | if ((div_off == 3) || (div_off == 11)) | ||
| 655 | mask= 0x3; | ||
| 656 | break; | ||
| 657 | case CM_CORE_SEL1: | ||
| 658 | div_addr = (u32)&CM_CLKSEL1_CORE; | ||
| 659 | switch (div_off) { | ||
| 660 | case 0: /* l3 */ | ||
| 661 | case 8: /* dss1 */ | ||
| 662 | case 15: /* vylnc-2420 */ | ||
| 663 | case 20: /* ssi */ | ||
| 664 | mask = 0x1f; break; | ||
| 665 | case 5: /* l4 */ | ||
| 666 | mask = 0x3; break; | ||
| 667 | case 13: /* dss2 */ | ||
| 668 | mask = 0x1; break; | ||
| 669 | case 25: /* usb */ | ||
| 670 | mask = 0x7; break; | ||
| 671 | } | ||
| 672 | } | ||
| 673 | 582 | ||
| 674 | *field_mask = mask; | 583 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); |
| 584 | if (validrate != rate) | ||
| 585 | return -EINVAL; | ||
| 675 | 586 | ||
| 676 | if (unlikely(mask == ~0)) | 587 | div_addr = omap2_get_clksel(clk, &field_mask); |
| 677 | div_addr = 0; | 588 | if (div_addr == 0) |
| 589 | return -EINVAL; | ||
| 678 | 590 | ||
| 679 | *div_sel = div_addr; | 591 | field_val = omap2_divisor_to_clksel(clk, new_div); |
| 592 | if (field_val == ~0) | ||
| 593 | return -EINVAL; | ||
| 680 | 594 | ||
| 681 | if (unlikely(div_addr == 0)) | 595 | reg_val = __raw_readl(div_addr); |
| 682 | return ret; | 596 | reg_val &= ~field_mask; |
| 597 | reg_val |= (field_val << __ffs(field_mask)); | ||
| 598 | __raw_writel(reg_val, div_addr); | ||
| 599 | wmb(); | ||
| 683 | 600 | ||
| 684 | /* Isolate field */ | 601 | clk->rate = clk->parent->rate / new_div; |
| 685 | reg_val = __raw_readl((void __iomem *)div_addr) & (mask << div_off); | ||
| 686 | 602 | ||
| 687 | /* Normalize back to divider value */ | 603 | if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { |
| 688 | reg_val >>= div_off; | 604 | __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); |
| 605 | wmb(); | ||
| 606 | } | ||
| 689 | 607 | ||
| 690 | return reg_val; | 608 | return 0; |
| 691 | } | 609 | } |
| 692 | 610 | ||
| 693 | /* | ||
| 694 | * Return divider to be applied to parent clock. | ||
| 695 | * Return 0 on error. | ||
| 696 | */ | ||
| 697 | static u32 omap2_clksel_get_divisor(struct clk *clk) | ||
| 698 | { | ||
| 699 | int ret = 0; | ||
| 700 | u32 div, div_sel, div_off, field_mask, field_val; | ||
| 701 | |||
| 702 | /* isolate control register */ | ||
| 703 | div_sel = (SRC_RATE_SEL_MASK & clk->flags); | ||
| 704 | |||
| 705 | div_off = clk->rate_offset; | ||
| 706 | field_val = omap2_get_clksel(&div_sel, &field_mask, clk); | ||
| 707 | if (div_sel == 0) | ||
| 708 | return ret; | ||
| 709 | |||
| 710 | div_sel = (SRC_RATE_SEL_MASK & clk->flags); | ||
| 711 | div = omap2_clksel_to_divisor(div_sel, field_val); | ||
| 712 | |||
| 713 | return div; | ||
| 714 | } | ||
| 715 | 611 | ||
| 716 | /* Set the clock rate for a clock source */ | 612 | /* Set the clock rate for a clock source */ |
| 717 | static int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | 613 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate) |
| 718 | |||
| 719 | { | 614 | { |
| 720 | int ret = -EINVAL; | 615 | int ret = -EINVAL; |
| 721 | void __iomem * reg; | ||
| 722 | u32 div_sel, div_off, field_mask, field_val, reg_val, validrate; | ||
| 723 | u32 new_div = 0; | ||
| 724 | |||
| 725 | if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) { | ||
| 726 | if (clk == &dpll_ck) | ||
| 727 | return omap2_reprogram_dpll(clk, rate); | ||
| 728 | |||
| 729 | /* Isolate control register */ | ||
| 730 | div_sel = (SRC_RATE_SEL_MASK & clk->flags); | ||
| 731 | div_off = clk->rate_offset; | ||
| 732 | |||
| 733 | validrate = omap2_clksel_round_rate(clk, rate, &new_div); | ||
| 734 | if (validrate != rate) | ||
| 735 | return(ret); | ||
| 736 | 616 | ||
| 737 | field_val = omap2_get_clksel(&div_sel, &field_mask, clk); | 617 | pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); |
| 738 | if (div_sel == 0) | ||
| 739 | return ret; | ||
| 740 | |||
| 741 | if (clk->flags & CM_SYSCLKOUT_SEL1) { | ||
| 742 | switch (new_div) { | ||
| 743 | case 16: | ||
| 744 | field_val = 4; | ||
| 745 | break; | ||
| 746 | case 8: | ||
| 747 | field_val = 3; | ||
| 748 | break; | ||
| 749 | case 4: | ||
| 750 | field_val = 2; | ||
| 751 | break; | ||
| 752 | case 2: | ||
| 753 | field_val = 1; | ||
| 754 | break; | ||
| 755 | case 1: | ||
| 756 | field_val = 0; | ||
| 757 | break; | ||
| 758 | } | ||
| 759 | } else | ||
| 760 | field_val = new_div; | ||
| 761 | 618 | ||
| 762 | reg = (void __iomem *)div_sel; | 619 | /* CONFIG_PARTICIPANT clocks are changed only in sets via the |
| 763 | 620 | rate table mechanism, driven by mpu_speed */ | |
| 764 | reg_val = __raw_readl(reg); | 621 | if (clk->flags & CONFIG_PARTICIPANT) |
| 765 | reg_val &= ~(field_mask << div_off); | 622 | return -EINVAL; |
| 766 | reg_val |= (field_val << div_off); | ||
| 767 | __raw_writel(reg_val, reg); | ||
| 768 | wmb(); | ||
| 769 | clk->rate = clk->parent->rate / field_val; | ||
| 770 | 623 | ||
| 771 | if (clk->flags & DELAYED_APP) { | 624 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ |
| 772 | __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); | 625 | if (clk->set_rate != 0) |
| 773 | wmb(); | ||
| 774 | } | ||
| 775 | ret = 0; | ||
| 776 | } else if (clk->set_rate != 0) | ||
| 777 | ret = clk->set_rate(clk, rate); | 626 | ret = clk->set_rate(clk, rate); |
| 778 | 627 | ||
| 779 | if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) | 628 | if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) |
| @@ -782,242 +631,92 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |||
| 782 | return ret; | 631 | return ret; |
| 783 | } | 632 | } |
| 784 | 633 | ||
| 785 | /* Converts encoded control register address into a full address */ | 634 | /* |
| 786 | static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset, | 635 | * Converts encoded control register address into a full address |
| 787 | struct clk *src_clk, u32 *field_mask) | 636 | * On error, *src_addr will be returned as 0. |
| 788 | { | 637 | */ |
| 789 | u32 val = ~0, src_reg_addr = 0, mask = 0; | 638 | static u32 omap2_clksel_get_src_field(void __iomem **src_addr, |
| 790 | 639 | struct clk *src_clk, u32 *field_mask, | |
| 791 | /* Find target control register.*/ | 640 | struct clk *clk, u32 *parent_div) |
| 792 | switch ((*type_to_addr & SRC_RATE_SEL_MASK)) { | ||
| 793 | case CM_CORE_SEL1: | ||
| 794 | src_reg_addr = (u32)&CM_CLKSEL1_CORE; | ||
| 795 | if (reg_offset == 13) { /* DSS2_fclk */ | ||
| 796 | mask = 0x1; | ||
| 797 | if (src_clk == &sys_ck) | ||
| 798 | val = 0; | ||
| 799 | if (src_clk == &func_48m_ck) | ||
| 800 | val = 1; | ||
| 801 | } else if (reg_offset == 8) { /* DSS1_fclk */ | ||
| 802 | mask = 0x1f; | ||
| 803 | if (src_clk == &sys_ck) | ||
| 804 | val = 0; | ||
| 805 | else if (src_clk == &core_ck) /* divided clock */ | ||
| 806 | val = 0x10; /* rate needs fixing */ | ||
| 807 | } else if ((reg_offset == 15) && cpu_is_omap2420()){ /*vlnyq*/ | ||
| 808 | mask = 0x1F; | ||
| 809 | if(src_clk == &func_96m_ck) | ||
| 810 | val = 0; | ||
| 811 | else if (src_clk == &core_ck) | ||
| 812 | val = 0x10; | ||
| 813 | } | ||
| 814 | break; | ||
| 815 | case CM_CORE_SEL2: | ||
| 816 | src_reg_addr = (u32)&CM_CLKSEL2_CORE; | ||
| 817 | mask = 0x3; | ||
| 818 | if (src_clk == &func_32k_ck) | ||
| 819 | val = 0x0; | ||
| 820 | if (src_clk == &sys_ck) | ||
| 821 | val = 0x1; | ||
| 822 | if (src_clk == &alt_ck) | ||
| 823 | val = 0x2; | ||
| 824 | break; | ||
| 825 | case CM_WKUP_SEL1: | ||
| 826 | src_reg_addr = (u32)&CM_CLKSEL_WKUP; | ||
| 827 | mask = 0x3; | ||
| 828 | if (src_clk == &func_32k_ck) | ||
| 829 | val = 0x0; | ||
| 830 | if (src_clk == &sys_ck) | ||
| 831 | val = 0x1; | ||
| 832 | if (src_clk == &alt_ck) | ||
| 833 | val = 0x2; | ||
| 834 | break; | ||
| 835 | case CM_PLL_SEL1: | ||
| 836 | src_reg_addr = (u32)&CM_CLKSEL1_PLL; | ||
| 837 | mask = 0x1; | ||
| 838 | if (reg_offset == 0x3) { | ||
| 839 | if (src_clk == &apll96_ck) | ||
| 840 | val = 0; | ||
| 841 | if (src_clk == &alt_ck) | ||
| 842 | val = 1; | ||
| 843 | } | ||
| 844 | else if (reg_offset == 0x5) { | ||
| 845 | if (src_clk == &apll54_ck) | ||
| 846 | val = 0; | ||
| 847 | if (src_clk == &alt_ck) | ||
| 848 | val = 1; | ||
| 849 | } | ||
| 850 | break; | ||
| 851 | case CM_PLL_SEL2: | ||
| 852 | src_reg_addr = (u32)&CM_CLKSEL2_PLL; | ||
| 853 | mask = 0x3; | ||
| 854 | if (src_clk == &func_32k_ck) | ||
| 855 | val = 0x0; | ||
| 856 | if (src_clk == &dpll_ck) | ||
| 857 | val = 0x2; | ||
| 858 | break; | ||
| 859 | case CM_SYSCLKOUT_SEL1: | ||
| 860 | src_reg_addr = (u32)&PRCM_CLKOUT_CTRL; | ||
| 861 | mask = 0x3; | ||
| 862 | if (src_clk == &dpll_ck) | ||
| 863 | val = 0; | ||
| 864 | if (src_clk == &sys_ck) | ||
| 865 | val = 1; | ||
| 866 | if (src_clk == &func_96m_ck) | ||
| 867 | val = 2; | ||
| 868 | if (src_clk == &func_54m_ck) | ||
| 869 | val = 3; | ||
| 870 | break; | ||
| 871 | } | ||
| 872 | |||
| 873 | if (val == ~0) /* Catch errors in offset */ | ||
| 874 | *type_to_addr = 0; | ||
| 875 | else | ||
| 876 | *type_to_addr = src_reg_addr; | ||
| 877 | *field_mask = mask; | ||
| 878 | |||
| 879 | return val; | ||
| 880 | } | ||
| 881 | |||
| 882 | static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) | ||
| 883 | { | 641 | { |
| 884 | void __iomem * reg; | 642 | const struct clksel *clks; |
| 885 | u32 src_sel, src_off, field_val, field_mask, reg_val, rate; | 643 | const struct clksel_rate *clkr; |
| 886 | int ret = -EINVAL; | ||
| 887 | |||
| 888 | if (unlikely(clk->flags & CONFIG_PARTICIPANT)) | ||
| 889 | return ret; | ||
| 890 | |||
| 891 | if (clk->flags & SRC_SEL_MASK) { /* On-chip SEL collection */ | ||
| 892 | src_sel = (SRC_RATE_SEL_MASK & clk->flags); | ||
| 893 | src_off = clk->src_offset; | ||
| 894 | |||
| 895 | if (src_sel == 0) | ||
| 896 | goto set_parent_error; | ||
| 897 | |||
| 898 | field_val = omap2_get_src_field(&src_sel, src_off, new_parent, | ||
| 899 | &field_mask); | ||
| 900 | |||
| 901 | reg = (void __iomem *)src_sel; | ||
| 902 | |||
| 903 | if (clk->usecount > 0) | ||
| 904 | _omap2_clk_disable(clk); | ||
| 905 | |||
| 906 | /* Set new source value (previous dividers if any in effect) */ | ||
| 907 | reg_val = __raw_readl(reg) & ~(field_mask << src_off); | ||
| 908 | reg_val |= (field_val << src_off); | ||
| 909 | __raw_writel(reg_val, reg); | ||
| 910 | wmb(); | ||
| 911 | 644 | ||
| 912 | if (clk->flags & DELAYED_APP) { | 645 | *parent_div = 0; |
| 913 | __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); | 646 | *src_addr = 0; |
| 914 | wmb(); | ||
| 915 | } | ||
| 916 | if (clk->usecount > 0) | ||
| 917 | _omap2_clk_enable(clk); | ||
| 918 | |||
| 919 | clk->parent = new_parent; | ||
| 920 | 647 | ||
| 921 | /* SRC_RATE_SEL_MASK clocks follow their parents rates.*/ | 648 | clks = omap2_get_clksel_by_parent(clk, src_clk); |
| 922 | if ((new_parent == &core_ck) && (clk == &dss1_fck)) | 649 | if (clks == NULL) |
| 923 | clk->rate = new_parent->rate / 0x10; | 650 | return 0; |
| 924 | else | ||
| 925 | clk->rate = new_parent->rate; | ||
| 926 | 651 | ||
| 927 | if (unlikely(clk->flags & RATE_PROPAGATES)) | 652 | for (clkr = clks->rates; clkr->div; clkr++) { |
| 928 | propagate_rate(clk); | 653 | if (clkr->flags & (cpu_mask | DEFAULT_RATE)) |
| 654 | break; /* Found the default rate for this platform */ | ||
| 655 | } | ||
| 929 | 656 | ||
| 657 | if (!clkr->div) { | ||
| 658 | printk(KERN_ERR "clock: Could not find default rate for " | ||
| 659 | "clock %s parent %s\n", clk->name, | ||
| 660 | src_clk->parent->name); | ||
| 930 | return 0; | 661 | return 0; |
| 931 | } else { | ||
| 932 | clk->parent = new_parent; | ||
| 933 | rate = new_parent->rate; | ||
| 934 | omap2_clk_set_rate(clk, rate); | ||
| 935 | ret = 0; | ||
| 936 | } | 662 | } |
| 937 | 663 | ||
| 938 | set_parent_error: | 664 | /* Should never happen. Add a clksel mask to the struct clk. */ |
| 939 | return ret; | 665 | WARN_ON(clk->clksel_mask == 0); |
| 666 | |||
| 667 | *field_mask = clk->clksel_mask; | ||
| 668 | *src_addr = clk->clksel_reg; | ||
| 669 | *parent_div = clkr->div; | ||
| 670 | |||
| 671 | return clkr->val; | ||
| 940 | } | 672 | } |
| 941 | 673 | ||
| 942 | /* Sets basic clocks based on the specified rate */ | 674 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) |
| 943 | static int omap2_select_table_rate(struct clk * clk, unsigned long rate) | ||
| 944 | { | 675 | { |
| 945 | u32 flags, cur_rate, done_rate, bypass = 0; | 676 | void __iomem *src_addr; |
| 946 | u8 cpu_mask = 0; | 677 | u32 field_val, field_mask, reg_val, parent_div; |
| 947 | struct prcm_config *prcm; | ||
| 948 | unsigned long found_speed = 0; | ||
| 949 | 678 | ||
| 950 | if (clk != &virt_prcm_set) | 679 | if (unlikely(clk->flags & CONFIG_PARTICIPANT)) |
| 951 | return -EINVAL; | 680 | return -EINVAL; |
| 952 | 681 | ||
| 953 | /* FIXME: Change cpu_is_omap2420() to cpu_is_omap242x() */ | 682 | if (!clk->clksel) |
| 954 | if (cpu_is_omap2420()) | ||
| 955 | cpu_mask = RATE_IN_242X; | ||
| 956 | else if (cpu_is_omap2430()) | ||
| 957 | cpu_mask = RATE_IN_243X; | ||
| 958 | |||
| 959 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
| 960 | if (!(prcm->flags & cpu_mask)) | ||
| 961 | continue; | ||
| 962 | |||
| 963 | if (prcm->xtal_speed != sys_ck.rate) | ||
| 964 | continue; | ||
| 965 | |||
| 966 | if (prcm->mpu_speed <= rate) { | ||
| 967 | found_speed = prcm->mpu_speed; | ||
| 968 | break; | ||
| 969 | } | ||
| 970 | } | ||
| 971 | |||
| 972 | if (!found_speed) { | ||
| 973 | printk(KERN_INFO "Could not set MPU rate to %luMHz\n", | ||
| 974 | rate / 1000000); | ||
| 975 | return -EINVAL; | 683 | return -EINVAL; |
| 976 | } | ||
| 977 | |||
| 978 | curr_prcm_set = prcm; | ||
| 979 | cur_rate = omap2_get_dpll_rate(&dpll_ck); | ||
| 980 | |||
| 981 | if (prcm->dpll_speed == cur_rate / 2) { | ||
| 982 | omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1); | ||
| 983 | } else if (prcm->dpll_speed == cur_rate * 2) { | ||
| 984 | omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); | ||
| 985 | } else if (prcm->dpll_speed != cur_rate) { | ||
| 986 | local_irq_save(flags); | ||
| 987 | 684 | ||
| 988 | if (prcm->dpll_speed == prcm->xtal_speed) | 685 | field_val = omap2_clksel_get_src_field(&src_addr, new_parent, |
| 989 | bypass = 1; | 686 | &field_mask, clk, &parent_div); |
| 687 | if (src_addr == 0) | ||
| 688 | return -EINVAL; | ||
| 990 | 689 | ||
| 991 | if ((prcm->cm_clksel2_pll & 0x3) == 2) | 690 | if (clk->usecount > 0) |
| 992 | done_rate = PRCM_FULL_SPEED; | 691 | _omap2_clk_disable(clk); |
| 993 | else | ||
| 994 | done_rate = PRCM_HALF_SPEED; | ||
| 995 | 692 | ||
| 996 | /* MPU divider */ | 693 | /* Set new source value (previous dividers if any in effect) */ |
| 997 | CM_CLKSEL_MPU = prcm->cm_clksel_mpu; | 694 | reg_val = __raw_readl(src_addr) & ~field_mask; |
| 695 | reg_val |= (field_val << __ffs(field_mask)); | ||
| 696 | __raw_writel(reg_val, src_addr); | ||
| 697 | wmb(); | ||
| 998 | 698 | ||
| 999 | /* dsp + iva1 div(2420), iva2.1(2430) */ | 699 | if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { |
| 1000 | CM_CLKSEL_DSP = prcm->cm_clksel_dsp; | 700 | __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); |
| 701 | wmb(); | ||
| 702 | } | ||
| 1001 | 703 | ||
| 1002 | CM_CLKSEL_GFX = prcm->cm_clksel_gfx; | 704 | if (clk->usecount > 0) |
| 705 | _omap2_clk_enable(clk); | ||
| 1003 | 706 | ||
| 1004 | /* Major subsystem dividers */ | 707 | clk->parent = new_parent; |
| 1005 | CM_CLKSEL1_CORE = prcm->cm_clksel1_core; | ||
| 1006 | if (cpu_is_omap2430()) | ||
| 1007 | CM_CLKSEL_MDM = prcm->cm_clksel_mdm; | ||
| 1008 | 708 | ||
| 1009 | /* x2 to enter init_mem */ | 709 | /* CLKSEL clocks follow their parents' rates, divided by a divisor */ |
| 1010 | omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); | 710 | clk->rate = new_parent->rate; |
| 1011 | 711 | ||
| 1012 | omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, | 712 | if (parent_div > 0) |
| 1013 | bypass); | 713 | clk->rate /= parent_div; |
| 1014 | 714 | ||
| 1015 | omap2_init_memory_params(omap2_dll_force_needed()); | 715 | pr_debug("clock: set parent of %s to %s (new rate %ld)\n", |
| 1016 | omap2_reprogram_sdrc(done_rate, 0); | 716 | clk->name, clk->parent->name, clk->rate); |
| 1017 | 717 | ||
| 1018 | local_irq_restore(flags); | 718 | if (unlikely(clk->flags & RATE_PROPAGATES)) |
| 1019 | } | 719 | propagate_rate(clk); |
| 1020 | omap2_clksel_recalc(&dpll_ck); | ||
| 1021 | 720 | ||
| 1022 | return 0; | 721 | return 0; |
| 1023 | } | 722 | } |
| @@ -1027,150 +726,17 @@ static int omap2_select_table_rate(struct clk * clk, unsigned long rate) | |||
| 1027 | *-------------------------------------------------------------------------*/ | 726 | *-------------------------------------------------------------------------*/ |
| 1028 | 727 | ||
| 1029 | #ifdef CONFIG_OMAP_RESET_CLOCKS | 728 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
| 1030 | static void __init omap2_clk_disable_unused(struct clk *clk) | 729 | void omap2_clk_disable_unused(struct clk *clk) |
| 1031 | { | 730 | { |
| 1032 | u32 regval32; | 731 | u32 regval32, v; |
| 732 | |||
| 733 | v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; | ||
| 1033 | 734 | ||
| 1034 | regval32 = __raw_readl(clk->enable_reg); | 735 | regval32 = __raw_readl(clk->enable_reg); |
| 1035 | if ((regval32 & (1 << clk->enable_bit)) == 0) | 736 | if ((regval32 & (1 << clk->enable_bit)) == v) |
| 1036 | return; | 737 | return; |
| 1037 | 738 | ||
| 1038 | printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); | 739 | printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); |
| 1039 | _omap2_clk_disable(clk); | 740 | _omap2_clk_disable(clk); |
| 1040 | } | 741 | } |
| 1041 | #else | ||
| 1042 | #define omap2_clk_disable_unused NULL | ||
| 1043 | #endif | 742 | #endif |
| 1044 | |||
| 1045 | static struct clk_functions omap2_clk_functions = { | ||
| 1046 | .clk_enable = omap2_clk_enable, | ||
| 1047 | .clk_disable = omap2_clk_disable, | ||
| 1048 | .clk_round_rate = omap2_clk_round_rate, | ||
| 1049 | .clk_set_rate = omap2_clk_set_rate, | ||
| 1050 | .clk_set_parent = omap2_clk_set_parent, | ||
| 1051 | .clk_disable_unused = omap2_clk_disable_unused, | ||
| 1052 | }; | ||
| 1053 | |||
| 1054 | static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys) | ||
| 1055 | { | ||
| 1056 | u32 div, aplls, sclk = 13000000; | ||
| 1057 | |||
| 1058 | aplls = CM_CLKSEL1_PLL; | ||
| 1059 | aplls &= ((1 << 23) | (1 << 24) | (1 << 25)); | ||
| 1060 | aplls >>= 23; /* Isolate field, 0,2,3 */ | ||
| 1061 | |||
| 1062 | if (aplls == 0) | ||
| 1063 | sclk = 19200000; | ||
| 1064 | else if (aplls == 2) | ||
| 1065 | sclk = 13000000; | ||
| 1066 | else if (aplls == 3) | ||
| 1067 | sclk = 12000000; | ||
| 1068 | |||
| 1069 | div = PRCM_CLKSRC_CTRL; | ||
| 1070 | div &= ((1 << 7) | (1 << 6)); | ||
| 1071 | div >>= sys->rate_offset; | ||
| 1072 | |||
| 1073 | osc->rate = sclk * div; | ||
| 1074 | sys->rate = sclk; | ||
| 1075 | } | ||
| 1076 | |||
| 1077 | /* | ||
| 1078 | * Set clocks for bypass mode for reboot to work. | ||
| 1079 | */ | ||
| 1080 | void omap2_clk_prepare_for_reboot(void) | ||
| 1081 | { | ||
| 1082 | u32 rate; | ||
| 1083 | |||
| 1084 | if (vclk == NULL || sclk == NULL) | ||
| 1085 | return; | ||
| 1086 | |||
| 1087 | rate = clk_get_rate(sclk); | ||
| 1088 | clk_set_rate(vclk, rate); | ||
| 1089 | } | ||
| 1090 | |||
| 1091 | /* | ||
| 1092 | * Switch the MPU rate if specified on cmdline. | ||
| 1093 | * We cannot do this early until cmdline is parsed. | ||
| 1094 | */ | ||
| 1095 | static int __init omap2_clk_arch_init(void) | ||
| 1096 | { | ||
| 1097 | if (!mpurate) | ||
| 1098 | return -EINVAL; | ||
| 1099 | |||
| 1100 | if (omap2_select_table_rate(&virt_prcm_set, mpurate)) | ||
| 1101 | printk(KERN_ERR "Could not find matching MPU rate\n"); | ||
| 1102 | |||
| 1103 | propagate_rate(&osc_ck); /* update main root fast */ | ||
| 1104 | propagate_rate(&func_32k_ck); /* update main root slow */ | ||
| 1105 | |||
| 1106 | printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): " | ||
| 1107 | "%ld.%01ld/%ld/%ld MHz\n", | ||
| 1108 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | ||
| 1109 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | ||
| 1110 | |||
| 1111 | return 0; | ||
| 1112 | } | ||
| 1113 | arch_initcall(omap2_clk_arch_init); | ||
| 1114 | |||
| 1115 | int __init omap2_clk_init(void) | ||
| 1116 | { | ||
| 1117 | struct prcm_config *prcm; | ||
| 1118 | struct clk ** clkp; | ||
| 1119 | u32 clkrate; | ||
| 1120 | |||
| 1121 | clk_init(&omap2_clk_functions); | ||
| 1122 | omap2_get_crystal_rate(&osc_ck, &sys_ck); | ||
| 1123 | |||
| 1124 | for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks); | ||
| 1125 | clkp++) { | ||
| 1126 | |||
| 1127 | if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) { | ||
| 1128 | clk_register(*clkp); | ||
| 1129 | continue; | ||
| 1130 | } | ||
| 1131 | |||
| 1132 | if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) { | ||
| 1133 | clk_register(*clkp); | ||
| 1134 | continue; | ||
| 1135 | } | ||
| 1136 | } | ||
| 1137 | |||
| 1138 | /* Check the MPU rate set by bootloader */ | ||
| 1139 | clkrate = omap2_get_dpll_rate(&dpll_ck); | ||
| 1140 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
| 1141 | if (prcm->xtal_speed != sys_ck.rate) | ||
| 1142 | continue; | ||
| 1143 | if (prcm->dpll_speed <= clkrate) | ||
| 1144 | break; | ||
| 1145 | } | ||
| 1146 | curr_prcm_set = prcm; | ||
| 1147 | |||
| 1148 | propagate_rate(&osc_ck); /* update main root fast */ | ||
| 1149 | propagate_rate(&func_32k_ck); /* update main root slow */ | ||
| 1150 | |||
| 1151 | printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " | ||
| 1152 | "%ld.%01ld/%ld/%ld MHz\n", | ||
| 1153 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | ||
| 1154 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | ||
| 1155 | |||
| 1156 | /* | ||
| 1157 | * Only enable those clocks we will need, let the drivers | ||
| 1158 | * enable other clocks as necessary | ||
| 1159 | */ | ||
| 1160 | clk_enable(&sync_32k_ick); | ||
| 1161 | clk_enable(&omapctrl_ick); | ||
| 1162 | |||
| 1163 | /* Force the APLLs always active. The clocks are idled | ||
| 1164 | * automatically by hardware. */ | ||
| 1165 | clk_enable(&apll96_ck); | ||
| 1166 | clk_enable(&apll54_ck); | ||
| 1167 | |||
| 1168 | if (cpu_is_omap2430()) | ||
| 1169 | clk_enable(&sdrc_ick); | ||
| 1170 | |||
| 1171 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ | ||
| 1172 | vclk = clk_get(NULL, "virt_prcm_set"); | ||
| 1173 | sclk = clk_get(NULL, "sys_ck"); | ||
| 1174 | |||
| 1175 | return 0; | ||
| 1176 | } | ||
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 4f791866b910..d5980a9e09a4 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h | |||
| @@ -1,13 +1,12 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-omap24xx/clock.h | 2 | * linux/arch/arm/mach-omap2/clock.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005 Texas Instruments Inc. | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
| 5 | * Richard Woodruff <r-woodruff2@ti.com> | 5 | * Copyright (C) 2004-2008 Nokia Corporation |
| 6 | * Created for OMAP2. | ||
| 7 | * | 6 | * |
| 8 | * Copyright (C) 2004 Nokia corporation | 7 | * Contacts: |
| 9 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
| 10 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | 9 | * Paul Walmsley |
| 11 | * | 10 | * |
| 12 | * This program is free software; you can redistribute it and/or modify | 11 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License version 2 as | 12 | * it under the terms of the GNU General Public License version 2 as |
| @@ -17,2095 +16,53 @@ | |||
| 17 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H | 16 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H |
| 18 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_H | 17 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_H |
| 19 | 18 | ||
| 20 | static void omap2_sys_clk_recalc(struct clk * clk); | 19 | #include <asm/arch/clock.h> |
| 21 | static void omap2_clksel_recalc(struct clk * clk); | ||
| 22 | static void omap2_followparent_recalc(struct clk * clk); | ||
| 23 | static void omap2_propagate_rate(struct clk * clk); | ||
| 24 | static void omap2_mpu_recalc(struct clk * clk); | ||
| 25 | static int omap2_select_table_rate(struct clk * clk, unsigned long rate); | ||
| 26 | static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate); | ||
| 27 | static void omap2_clk_disable(struct clk *clk); | ||
| 28 | static void omap2_sys_clk_recalc(struct clk * clk); | ||
| 29 | static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val); | ||
| 30 | static u32 omap2_clksel_get_divisor(struct clk *clk); | ||
| 31 | |||
| 32 | |||
| 33 | #define RATE_IN_242X (1 << 0) | ||
| 34 | #define RATE_IN_243X (1 << 1) | ||
| 35 | |||
| 36 | /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. | ||
| 37 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP | ||
| 38 | * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM | ||
| 39 | */ | ||
| 40 | struct prcm_config { | ||
| 41 | unsigned long xtal_speed; /* crystal rate */ | ||
| 42 | unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */ | ||
| 43 | unsigned long mpu_speed; /* speed of MPU */ | ||
| 44 | unsigned long cm_clksel_mpu; /* mpu divider */ | ||
| 45 | unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */ | ||
| 46 | unsigned long cm_clksel_gfx; /* gfx dividers */ | ||
| 47 | unsigned long cm_clksel1_core; /* major subsystem dividers */ | ||
| 48 | unsigned long cm_clksel1_pll; /* m,n */ | ||
| 49 | unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ | ||
| 50 | unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ | ||
| 51 | unsigned long base_sdrc_rfr; /* base refresh timing for a set */ | ||
| 52 | unsigned char flags; | ||
| 53 | }; | ||
| 54 | |||
| 55 | /* Mask for clksel which support parent settign in set_rate */ | ||
| 56 | #define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \ | ||
| 57 | CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1) | ||
| 58 | |||
| 59 | /* Mask for clksel regs which support rate operations */ | ||
| 60 | #define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \ | ||
| 61 | CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \ | ||
| 62 | CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \ | ||
| 63 | CM_SYSCLKOUT_SEL1) | ||
| 64 | |||
| 65 | /* | ||
| 66 | * The OMAP2 processor can be run at several discrete 'PRCM configurations'. | ||
| 67 | * These configurations are characterized by voltage and speed for clocks. | ||
| 68 | * The device is only validated for certain combinations. One way to express | ||
| 69 | * these combinations is via the 'ratio's' which the clocks operate with | ||
| 70 | * respect to each other. These ratio sets are for a given voltage/DPLL | ||
| 71 | * setting. All configurations can be described by a DPLL setting and a ratio | ||
| 72 | * There are 3 ratio sets for the 2430 and X ratio sets for 2420. | ||
| 73 | * | ||
| 74 | * 2430 differs from 2420 in that there are no more phase synchronizers used. | ||
| 75 | * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs | ||
| 76 | * 2430 (iva2.1, NOdsp, mdm) | ||
| 77 | */ | ||
| 78 | |||
| 79 | /* Core fields for cm_clksel, not ratio governed */ | ||
| 80 | #define RX_CLKSEL_DSS1 (0x10 << 8) | ||
| 81 | #define RX_CLKSEL_DSS2 (0x0 << 13) | ||
| 82 | #define RX_CLKSEL_SSI (0x5 << 20) | ||
| 83 | |||
| 84 | /*------------------------------------------------------------------------- | ||
| 85 | * Voltage/DPLL ratios | ||
| 86 | *-------------------------------------------------------------------------*/ | ||
| 87 | |||
| 88 | /* 2430 Ratio's, 2430-Ratio Config 1 */ | ||
| 89 | #define R1_CLKSEL_L3 (4 << 0) | ||
| 90 | #define R1_CLKSEL_L4 (2 << 5) | ||
| 91 | #define R1_CLKSEL_USB (4 << 25) | ||
| 92 | #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \ | ||
| 93 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
| 94 | R1_CLKSEL_L4 | R1_CLKSEL_L3 | ||
| 95 | #define R1_CLKSEL_MPU (2 << 0) | ||
| 96 | #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU | ||
| 97 | #define R1_CLKSEL_DSP (2 << 0) | ||
| 98 | #define R1_CLKSEL_DSP_IF (2 << 5) | ||
| 99 | #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF | ||
| 100 | #define R1_CLKSEL_GFX (2 << 0) | ||
| 101 | #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX | ||
| 102 | #define R1_CLKSEL_MDM (4 << 0) | ||
| 103 | #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM | ||
| 104 | |||
| 105 | /* 2430-Ratio Config 2 */ | ||
| 106 | #define R2_CLKSEL_L3 (6 << 0) | ||
| 107 | #define R2_CLKSEL_L4 (2 << 5) | ||
| 108 | #define R2_CLKSEL_USB (2 << 25) | ||
| 109 | #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \ | ||
| 110 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
| 111 | R2_CLKSEL_L4 | R2_CLKSEL_L3 | ||
| 112 | #define R2_CLKSEL_MPU (2 << 0) | ||
| 113 | #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU | ||
| 114 | #define R2_CLKSEL_DSP (2 << 0) | ||
| 115 | #define R2_CLKSEL_DSP_IF (3 << 5) | ||
| 116 | #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF | ||
| 117 | #define R2_CLKSEL_GFX (2 << 0) | ||
| 118 | #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX | ||
| 119 | #define R2_CLKSEL_MDM (6 << 0) | ||
| 120 | #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM | ||
| 121 | |||
| 122 | /* 2430-Ratio Bootm (BYPASS) */ | ||
| 123 | #define RB_CLKSEL_L3 (1 << 0) | ||
| 124 | #define RB_CLKSEL_L4 (1 << 5) | ||
| 125 | #define RB_CLKSEL_USB (1 << 25) | ||
| 126 | #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \ | ||
| 127 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
| 128 | RB_CLKSEL_L4 | RB_CLKSEL_L3 | ||
| 129 | #define RB_CLKSEL_MPU (1 << 0) | ||
| 130 | #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU | ||
| 131 | #define RB_CLKSEL_DSP (1 << 0) | ||
| 132 | #define RB_CLKSEL_DSP_IF (1 << 5) | ||
| 133 | #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF | ||
| 134 | #define RB_CLKSEL_GFX (1 << 0) | ||
| 135 | #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX | ||
| 136 | #define RB_CLKSEL_MDM (1 << 0) | ||
| 137 | #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM | ||
| 138 | |||
| 139 | /* 2420 Ratio Equivalents */ | ||
| 140 | #define RXX_CLKSEL_VLYNQ (0x12 << 15) | ||
| 141 | #define RXX_CLKSEL_SSI (0x8 << 20) | ||
| 142 | |||
| 143 | /* 2420-PRCM III 532MHz core */ | ||
| 144 | #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */ | ||
| 145 | #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */ | ||
| 146 | #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */ | ||
| 147 | #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \ | ||
| 148 | RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ | ||
| 149 | RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \ | ||
| 150 | RIII_CLKSEL_L3 | ||
| 151 | #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */ | ||
| 152 | #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU | ||
| 153 | #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */ | ||
| 154 | #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */ | ||
| 155 | #define RIII_SYNC_DSP (1 << 7) /* Enable sync */ | ||
| 156 | #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */ | ||
| 157 | #define RIII_SYNC_IVA (1 << 13) /* Enable sync */ | ||
| 158 | #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \ | ||
| 159 | RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \ | ||
| 160 | RIII_CLKSEL_DSP | ||
| 161 | #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */ | ||
| 162 | #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX | ||
| 163 | |||
| 164 | /* 2420-PRCM II 600MHz core */ | ||
| 165 | #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */ | ||
| 166 | #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */ | ||
| 167 | #define RII_CLKSEL_USB (2 << 25) /* 50MHz */ | ||
| 168 | #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \ | ||
| 169 | RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ | ||
| 170 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
| 171 | RII_CLKSEL_L4 | RII_CLKSEL_L3 | ||
| 172 | #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */ | ||
| 173 | #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU | ||
| 174 | #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ | ||
| 175 | #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ | ||
| 176 | #define RII_SYNC_DSP (0 << 7) /* Bypass sync */ | ||
| 177 | #define RII_CLKSEL_IVA (6 << 8) /* iva1 - 200MHz */ | ||
| 178 | #define RII_SYNC_IVA (0 << 13) /* Bypass sync */ | ||
| 179 | #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \ | ||
| 180 | RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ | ||
| 181 | RII_CLKSEL_DSP | ||
| 182 | #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ | ||
| 183 | #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX | ||
| 184 | |||
| 185 | /* 2420-PRCM VII (boot) */ | ||
| 186 | #define RVII_CLKSEL_L3 (1 << 0) | ||
| 187 | #define RVII_CLKSEL_L4 (1 << 5) | ||
| 188 | #define RVII_CLKSEL_DSS1 (1 << 8) | ||
| 189 | #define RVII_CLKSEL_DSS2 (0 << 13) | ||
| 190 | #define RVII_CLKSEL_VLYNQ (1 << 15) | ||
| 191 | #define RVII_CLKSEL_SSI (1 << 20) | ||
| 192 | #define RVII_CLKSEL_USB (1 << 25) | ||
| 193 | |||
| 194 | #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \ | ||
| 195 | RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \ | ||
| 196 | RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3 | ||
| 197 | |||
| 198 | #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */ | ||
| 199 | #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU | ||
| 200 | 20 | ||
| 201 | #define RVII_CLKSEL_DSP (1 << 0) | 21 | int omap2_clk_enable(struct clk *clk); |
| 202 | #define RVII_CLKSEL_DSP_IF (1 << 5) | 22 | void omap2_clk_disable(struct clk *clk); |
| 203 | #define RVII_SYNC_DSP (0 << 7) | 23 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); |
| 204 | #define RVII_CLKSEL_IVA (1 << 8) | 24 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate); |
| 205 | #define RVII_SYNC_IVA (0 << 13) | 25 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); |
| 206 | #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \ | ||
| 207 | RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP | ||
| 208 | |||
| 209 | #define RVII_CLKSEL_GFX (1 << 0) | ||
| 210 | #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX | ||
| 211 | |||
| 212 | /*------------------------------------------------------------------------- | ||
| 213 | * 2430 Target modes: Along with each configuration the CPU has several | ||
| 214 | * modes which goes along with them. Modes mainly are the addition of | ||
| 215 | * describe DPLL combinations to go along with a ratio. | ||
| 216 | *-------------------------------------------------------------------------*/ | ||
| 217 | |||
| 218 | /* Hardware governed */ | ||
| 219 | #define MX_48M_SRC (0 << 3) | ||
| 220 | #define MX_54M_SRC (0 << 5) | ||
| 221 | #define MX_APLLS_CLIKIN_12 (3 << 23) | ||
| 222 | #define MX_APLLS_CLIKIN_13 (2 << 23) | ||
| 223 | #define MX_APLLS_CLIKIN_19_2 (0 << 23) | ||
| 224 | |||
| 225 | /* | ||
| 226 | * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed | ||
| 227 | * #2 (ratio1) baseport-target | ||
| 228 | * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz | ||
| 229 | */ | ||
| 230 | #define M5A_DPLL_MULT_12 (133 << 12) | ||
| 231 | #define M5A_DPLL_DIV_12 (5 << 8) | ||
| 232 | #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 233 | M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ | ||
| 234 | MX_APLLS_CLIKIN_12 | ||
| 235 | #define M5A_DPLL_MULT_13 (266 << 12) | ||
| 236 | #define M5A_DPLL_DIV_13 (12 << 8) | ||
| 237 | #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 238 | M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ | ||
| 239 | MX_APLLS_CLIKIN_13 | ||
| 240 | #define M5A_DPLL_MULT_19 (180 << 12) | ||
| 241 | #define M5A_DPLL_DIV_19 (12 << 8) | ||
| 242 | #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 243 | M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ | ||
| 244 | MX_APLLS_CLIKIN_19_2 | ||
| 245 | /* #5b (ratio1) target DPLL = 200*2 = 400MHz */ | ||
| 246 | #define M5B_DPLL_MULT_12 (50 << 12) | ||
| 247 | #define M5B_DPLL_DIV_12 (2 << 8) | ||
| 248 | #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 249 | M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \ | ||
| 250 | MX_APLLS_CLIKIN_12 | ||
| 251 | #define M5B_DPLL_MULT_13 (200 << 12) | ||
| 252 | #define M5B_DPLL_DIV_13 (12 << 8) | ||
| 253 | |||
| 254 | #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 255 | M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \ | ||
| 256 | MX_APLLS_CLIKIN_13 | ||
| 257 | #define M5B_DPLL_MULT_19 (125 << 12) | ||
| 258 | #define M5B_DPLL_DIV_19 (31 << 8) | ||
| 259 | #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 260 | M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ | ||
| 261 | MX_APLLS_CLIKIN_19_2 | ||
| 262 | /* | ||
| 263 | * #4 (ratio2) | ||
| 264 | * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz | ||
| 265 | */ | ||
| 266 | #define M3_DPLL_MULT_12 (55 << 12) | ||
| 267 | #define M3_DPLL_DIV_12 (1 << 8) | ||
| 268 | #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 269 | M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ | ||
| 270 | MX_APLLS_CLIKIN_12 | ||
| 271 | #define M3_DPLL_MULT_13 (330 << 12) | ||
| 272 | #define M3_DPLL_DIV_13 (12 << 8) | ||
| 273 | #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 274 | M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ | ||
| 275 | MX_APLLS_CLIKIN_13 | ||
| 276 | #define M3_DPLL_MULT_19 (275 << 12) | ||
| 277 | #define M3_DPLL_DIV_19 (15 << 8) | ||
| 278 | #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 279 | M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ | ||
| 280 | MX_APLLS_CLIKIN_19_2 | ||
| 281 | /* boot (boot) */ | ||
| 282 | #define MB_DPLL_MULT (1 << 12) | ||
| 283 | #define MB_DPLL_DIV (0 << 8) | ||
| 284 | #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ | ||
| 285 | MB_DPLL_MULT | MX_APLLS_CLIKIN_12 | ||
| 286 | |||
| 287 | #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ | ||
| 288 | MB_DPLL_MULT | MX_APLLS_CLIKIN_13 | ||
| 289 | |||
| 290 | #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ | ||
| 291 | MB_DPLL_MULT | MX_APLLS_CLIKIN_19 | ||
| 292 | |||
| 293 | /* | ||
| 294 | * 2430 - chassis (sedna) | ||
| 295 | * 165 (ratio1) same as above #2 | ||
| 296 | * 150 (ratio1) | ||
| 297 | * 133 (ratio2) same as above #4 | ||
| 298 | * 110 (ratio2) same as above #3 | ||
| 299 | * 104 (ratio2) | ||
| 300 | * boot (boot) | ||
| 301 | */ | ||
| 302 | |||
| 303 | /* | ||
| 304 | * 2420 Equivalent - mode registers | ||
| 305 | * PRCM II , target DPLL = 2*300MHz = 600MHz | ||
| 306 | */ | ||
| 307 | #define MII_DPLL_MULT_12 (50 << 12) | ||
| 308 | #define MII_DPLL_DIV_12 (1 << 8) | ||
| 309 | #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 310 | MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \ | ||
| 311 | MX_APLLS_CLIKIN_12 | ||
| 312 | #define MII_DPLL_MULT_13 (300 << 12) | ||
| 313 | #define MII_DPLL_DIV_13 (12 << 8) | ||
| 314 | #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 315 | MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \ | ||
| 316 | MX_APLLS_CLIKIN_13 | ||
| 317 | |||
| 318 | /* PRCM III target DPLL = 2*266 = 532MHz*/ | ||
| 319 | #define MIII_DPLL_MULT_12 (133 << 12) | ||
| 320 | #define MIII_DPLL_DIV_12 (5 << 8) | ||
| 321 | #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 322 | MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \ | ||
| 323 | MX_APLLS_CLIKIN_12 | ||
| 324 | #define MIII_DPLL_MULT_13 (266 << 12) | ||
| 325 | #define MIII_DPLL_DIV_13 (12 << 8) | ||
| 326 | #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 327 | MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \ | ||
| 328 | MX_APLLS_CLIKIN_13 | ||
| 329 | |||
| 330 | /* PRCM VII (boot bypass) */ | ||
| 331 | #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL | ||
| 332 | #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL | ||
| 333 | |||
| 334 | /* High and low operation value */ | ||
| 335 | #define MX_CLKSEL2_PLL_2x_VAL (2 << 0) | ||
| 336 | #define MX_CLKSEL2_PLL_1x_VAL (1 << 0) | ||
| 337 | |||
| 338 | /* | ||
| 339 | * These represent optimal values for common parts, it won't work for all. | ||
| 340 | * As long as you scale down, most parameters are still work, they just | ||
| 341 | * become sub-optimal. The RFR value goes in the opposite direction. If you | ||
| 342 | * don't adjust it down as your clock period increases the refresh interval | ||
| 343 | * will not be met. Setting all parameters for complete worst case may work, | ||
| 344 | * but may cut memory performance by 2x. Due to errata the DLLs need to be | ||
| 345 | * unlocked and their value needs run time calibration. A dynamic call is | ||
| 346 | * need for that as no single right value exists acorss production samples. | ||
| 347 | * | ||
| 348 | * Only the FULL speed values are given. Current code is such that rate | ||
| 349 | * changes must be made at DPLLoutx2. The actual value adjustment for low | ||
| 350 | * frequency operation will be handled by omap_set_performance() | ||
| 351 | * | ||
| 352 | * By having the boot loader boot up in the fastest L4 speed available likely | ||
| 353 | * will result in something which you can switch between. | ||
| 354 | */ | ||
| 355 | #define V24XX_SDRC_RFR_CTRL_133MHz (0x0003de00 | 1) | ||
| 356 | #define V24XX_SDRC_RFR_CTRL_100MHz (0x0002da01 | 1) | ||
| 357 | #define V24XX_SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */ | ||
| 358 | #define V24XX_SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */ | ||
| 359 | |||
| 360 | /* MPU speed defines */ | ||
| 361 | #define S12M 12000000 | ||
| 362 | #define S13M 13000000 | ||
| 363 | #define S19M 19200000 | ||
| 364 | #define S26M 26000000 | ||
| 365 | #define S100M 100000000 | ||
| 366 | #define S133M 133000000 | ||
| 367 | #define S150M 150000000 | ||
| 368 | #define S165M 165000000 | ||
| 369 | #define S200M 200000000 | ||
| 370 | #define S266M 266000000 | ||
| 371 | #define S300M 300000000 | ||
| 372 | #define S330M 330000000 | ||
| 373 | #define S400M 400000000 | ||
| 374 | #define S532M 532000000 | ||
| 375 | #define S600M 600000000 | ||
| 376 | #define S660M 660000000 | ||
| 377 | |||
| 378 | /*------------------------------------------------------------------------- | ||
| 379 | * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. | ||
| 380 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, | ||
| 381 | * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, | ||
| 382 | * CM_CLKSEL2_PLL, CM_CLKSEL_MDM | ||
| 383 | * | ||
| 384 | * Filling in table based on H4 boards and 2430-SDPs variants available. | ||
| 385 | * There are quite a few more rates combinations which could be defined. | ||
| 386 | * | ||
| 387 | * When multiple values are defined the start up will try and choose the | ||
| 388 | * fastest one. If a 'fast' value is defined, then automatically, the /2 | ||
| 389 | * one should be included as it can be used. Generally having more that | ||
| 390 | * one fast set does not make sense, as static timings need to be changed | ||
| 391 | * to change the set. The exception is the bypass setting which is | ||
| 392 | * availble for low power bypass. | ||
| 393 | * | ||
| 394 | * Note: This table needs to be sorted, fastest to slowest. | ||
| 395 | *-------------------------------------------------------------------------*/ | ||
| 396 | static struct prcm_config rate_table[] = { | ||
| 397 | /* PRCM II - FAST */ | ||
| 398 | {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ | ||
| 399 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | ||
| 400 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, | ||
| 401 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz, | ||
| 402 | RATE_IN_242X}, | ||
| 403 | |||
| 404 | {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ | ||
| 405 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | ||
| 406 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, | ||
| 407 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz, | ||
| 408 | RATE_IN_242X}, | ||
| 409 | |||
| 410 | /* PRCM III - FAST */ | ||
| 411 | {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ | ||
| 412 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | ||
| 413 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, | ||
| 414 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz, | ||
| 415 | RATE_IN_242X}, | ||
| 416 | |||
| 417 | {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ | ||
| 418 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | ||
| 419 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, | ||
| 420 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz, | ||
| 421 | RATE_IN_242X}, | ||
| 422 | |||
| 423 | /* PRCM II - SLOW */ | ||
| 424 | {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ | ||
| 425 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | ||
| 426 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, | ||
| 427 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz, | ||
| 428 | RATE_IN_242X}, | ||
| 429 | |||
| 430 | {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ | ||
| 431 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | ||
| 432 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, | ||
| 433 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz, | ||
| 434 | RATE_IN_242X}, | ||
| 435 | |||
| 436 | /* PRCM III - SLOW */ | ||
| 437 | {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ | ||
| 438 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | ||
| 439 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, | ||
| 440 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz, | ||
| 441 | RATE_IN_242X}, | ||
| 442 | |||
| 443 | {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ | ||
| 444 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | ||
| 445 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, | ||
| 446 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz, | ||
| 447 | RATE_IN_242X}, | ||
| 448 | |||
| 449 | /* PRCM-VII (boot-bypass) */ | ||
| 450 | {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/ | ||
| 451 | RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, | ||
| 452 | RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL, | ||
| 453 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS, | ||
| 454 | RATE_IN_242X}, | ||
| 455 | |||
| 456 | /* PRCM-VII (boot-bypass) */ | ||
| 457 | {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */ | ||
| 458 | RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, | ||
| 459 | RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL, | ||
| 460 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS, | ||
| 461 | RATE_IN_242X}, | ||
| 462 | |||
| 463 | /* PRCM #3 - ratio2 (ES2) - FAST */ | ||
| 464 | {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ | ||
| 465 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, | ||
| 466 | R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL, | ||
| 467 | MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL, | ||
| 468 | V24XX_SDRC_RFR_CTRL_110MHz, | ||
| 469 | RATE_IN_243X}, | ||
| 470 | |||
| 471 | /* PRCM #5a - ratio1 - FAST */ | ||
| 472 | {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ | ||
| 473 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
| 474 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, | ||
| 475 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
| 476 | V24XX_SDRC_RFR_CTRL_133MHz, | ||
| 477 | RATE_IN_243X}, | ||
| 478 | |||
| 479 | /* PRCM #5b - ratio1 - FAST */ | ||
| 480 | {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ | ||
| 481 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
| 482 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, | ||
| 483 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
| 484 | V24XX_SDRC_RFR_CTRL_100MHz, | ||
| 485 | RATE_IN_243X}, | ||
| 486 | |||
| 487 | /* PRCM #3 - ratio2 (ES2) - SLOW */ | ||
| 488 | {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ | ||
| 489 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, | ||
| 490 | R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL, | ||
| 491 | MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL, | ||
| 492 | V24XX_SDRC_RFR_CTRL_110MHz, | ||
| 493 | RATE_IN_243X}, | ||
| 494 | |||
| 495 | /* PRCM #5a - ratio1 - SLOW */ | ||
| 496 | {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ | ||
| 497 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
| 498 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, | ||
| 499 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
| 500 | V24XX_SDRC_RFR_CTRL_133MHz, | ||
| 501 | RATE_IN_243X}, | ||
| 502 | |||
| 503 | /* PRCM #5b - ratio1 - SLOW*/ | ||
| 504 | {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */ | ||
| 505 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
| 506 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, | ||
| 507 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
| 508 | V24XX_SDRC_RFR_CTRL_100MHz, | ||
| 509 | RATE_IN_243X}, | ||
| 510 | |||
| 511 | /* PRCM-boot/bypass */ | ||
| 512 | {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */ | ||
| 513 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, | ||
| 514 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, | ||
| 515 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, | ||
| 516 | V24XX_SDRC_RFR_CTRL_BYPASS, | ||
| 517 | RATE_IN_243X}, | ||
| 518 | |||
| 519 | /* PRCM-boot/bypass */ | ||
| 520 | {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */ | ||
| 521 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, | ||
| 522 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, | ||
| 523 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, | ||
| 524 | V24XX_SDRC_RFR_CTRL_BYPASS, | ||
| 525 | RATE_IN_243X}, | ||
| 526 | |||
| 527 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | ||
| 528 | }; | ||
| 529 | |||
| 530 | /*------------------------------------------------------------------------- | ||
| 531 | * 24xx clock tree. | ||
| 532 | * | ||
| 533 | * NOTE:In many cases here we are assigning a 'default' parent. In many | ||
| 534 | * cases the parent is selectable. The get/set parent calls will also | ||
| 535 | * switch sources. | ||
| 536 | * | ||
| 537 | * Many some clocks say always_enabled, but they can be auto idled for | ||
| 538 | * power savings. They will always be available upon clock request. | ||
| 539 | * | ||
| 540 | * Several sources are given initial rates which may be wrong, this will | ||
| 541 | * be fixed up in the init func. | ||
| 542 | * | ||
| 543 | * Things are broadly separated below by clock domains. It is | ||
| 544 | * noteworthy that most periferals have dependencies on multiple clock | ||
| 545 | * domains. Many get their interface clocks from the L4 domain, but get | ||
| 546 | * functional clocks from fixed sources or other core domain derived | ||
| 547 | * clocks. | ||
| 548 | *-------------------------------------------------------------------------*/ | ||
| 549 | |||
| 550 | /* Base external input clocks */ | ||
| 551 | static struct clk func_32k_ck = { | ||
| 552 | .name = "func_32k_ck", | ||
| 553 | .rate = 32000, | ||
| 554 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 555 | RATE_FIXED | ALWAYS_ENABLED, | ||
| 556 | }; | ||
| 557 | |||
| 558 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ | ||
| 559 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ | ||
| 560 | .name = "osc_ck", | ||
| 561 | .rate = 26000000, /* fixed up in clock init */ | ||
| 562 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 563 | RATE_FIXED | RATE_PROPAGATES, | ||
| 564 | }; | ||
| 565 | |||
| 566 | /* With out modem likely 12MHz, with modem likely 13MHz */ | ||
| 567 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ | ||
| 568 | .name = "sys_ck", /* ~ ref_clk also */ | ||
| 569 | .parent = &osc_ck, | ||
| 570 | .rate = 13000000, | ||
| 571 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 572 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, | ||
| 573 | .rate_offset = 6, /* sysclkdiv 1 or 2, already handled or no boot */ | ||
| 574 | .recalc = &omap2_sys_clk_recalc, | ||
| 575 | }; | ||
| 576 | |||
| 577 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ | ||
| 578 | .name = "alt_ck", | ||
| 579 | .rate = 54000000, | ||
| 580 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 581 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, | ||
| 582 | .recalc = &omap2_propagate_rate, | ||
| 583 | }; | ||
| 584 | |||
| 585 | /* | ||
| 586 | * Analog domain root source clocks | ||
| 587 | */ | ||
| 588 | |||
| 589 | /* dpll_ck, is broken out in to special cases through clksel */ | ||
| 590 | static struct clk dpll_ck = { | ||
| 591 | .name = "dpll_ck", | ||
| 592 | .parent = &sys_ck, /* Can be func_32k also */ | ||
| 593 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 594 | RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1, | ||
| 595 | .recalc = &omap2_clksel_recalc, | ||
| 596 | }; | ||
| 597 | |||
| 598 | static struct clk apll96_ck = { | ||
| 599 | .name = "apll96_ck", | ||
| 600 | .parent = &sys_ck, | ||
| 601 | .rate = 96000000, | ||
| 602 | .flags = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X | | ||
| 603 | RATE_FIXED | RATE_PROPAGATES, | ||
| 604 | .enable_reg = (void __iomem *)&CM_CLKEN_PLL, | ||
| 605 | .enable_bit = 0x2, | ||
| 606 | .recalc = &omap2_propagate_rate, | ||
| 607 | }; | ||
| 608 | |||
| 609 | static struct clk apll54_ck = { | ||
| 610 | .name = "apll54_ck", | ||
| 611 | .parent = &sys_ck, | ||
| 612 | .rate = 54000000, | ||
| 613 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 614 | RATE_FIXED | RATE_PROPAGATES, | ||
| 615 | .enable_reg = (void __iomem *)&CM_CLKEN_PLL, | ||
| 616 | .enable_bit = 0x6, | ||
| 617 | .recalc = &omap2_propagate_rate, | ||
| 618 | }; | ||
| 619 | 26 | ||
| 620 | /* | 27 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
| 621 | * PRCM digital base sources | 28 | void omap2_clk_disable_unused(struct clk *clk); |
| 622 | */ | 29 | #else |
| 623 | static struct clk func_54m_ck = { | 30 | #define omap2_clk_disable_unused NULL |
| 624 | .name = "func_54m_ck", | 31 | #endif |
| 625 | .parent = &apll54_ck, /* can also be alt_clk */ | ||
| 626 | .rate = 54000000, | ||
| 627 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 628 | RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES, | ||
| 629 | .src_offset = 5, | ||
| 630 | .enable_reg = (void __iomem *)&CM_CLKEN_PLL, | ||
| 631 | .enable_bit = 0xff, | ||
| 632 | .recalc = &omap2_propagate_rate, | ||
| 633 | }; | ||
| 634 | |||
| 635 | static struct clk core_ck = { | ||
| 636 | .name = "core_ck", | ||
| 637 | .parent = &dpll_ck, /* can also be 32k */ | ||
| 638 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 639 | ALWAYS_ENABLED | RATE_PROPAGATES, | ||
| 640 | .recalc = &omap2_propagate_rate, | ||
| 641 | }; | ||
| 642 | |||
| 643 | static struct clk sleep_ck = { /* sys_clk or 32k */ | ||
| 644 | .name = "sleep_ck", | ||
| 645 | .parent = &func_32k_ck, | ||
| 646 | .rate = 32000, | ||
| 647 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 648 | .recalc = &omap2_propagate_rate, | ||
| 649 | }; | ||
| 650 | |||
| 651 | static struct clk func_96m_ck = { | ||
| 652 | .name = "func_96m_ck", | ||
| 653 | .parent = &apll96_ck, | ||
| 654 | .rate = 96000000, | ||
| 655 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 656 | RATE_FIXED | RATE_PROPAGATES, | ||
| 657 | .enable_reg = (void __iomem *)&CM_CLKEN_PLL, | ||
| 658 | .enable_bit = 0xff, | ||
| 659 | .recalc = &omap2_propagate_rate, | ||
| 660 | }; | ||
| 661 | |||
| 662 | static struct clk func_48m_ck = { | ||
| 663 | .name = "func_48m_ck", | ||
| 664 | .parent = &apll96_ck, /* 96M or Alt */ | ||
| 665 | .rate = 48000000, | ||
| 666 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 667 | RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES, | ||
| 668 | .src_offset = 3, | ||
| 669 | .enable_reg = (void __iomem *)&CM_CLKEN_PLL, | ||
| 670 | .enable_bit = 0xff, | ||
| 671 | .recalc = &omap2_propagate_rate, | ||
| 672 | }; | ||
| 673 | |||
| 674 | static struct clk func_12m_ck = { | ||
| 675 | .name = "func_12m_ck", | ||
| 676 | .parent = &func_48m_ck, | ||
| 677 | .rate = 12000000, | ||
| 678 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 679 | RATE_FIXED | RATE_PROPAGATES, | ||
| 680 | .recalc = &omap2_propagate_rate, | ||
| 681 | .enable_reg = (void __iomem *)&CM_CLKEN_PLL, | ||
| 682 | .enable_bit = 0xff, | ||
| 683 | }; | ||
| 684 | |||
| 685 | /* Secure timer, only available in secure mode */ | ||
| 686 | static struct clk wdt1_osc_ck = { | ||
| 687 | .name = "ck_wdt1_osc", | ||
| 688 | .parent = &osc_ck, | ||
| 689 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 690 | .recalc = &omap2_followparent_recalc, | ||
| 691 | }; | ||
| 692 | |||
| 693 | static struct clk sys_clkout = { | ||
| 694 | .name = "sys_clkout", | ||
| 695 | .parent = &func_54m_ck, | ||
| 696 | .rate = 54000000, | ||
| 697 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 698 | CM_SYSCLKOUT_SEL1 | RATE_CKCTL, | ||
| 699 | .src_offset = 0, | ||
| 700 | .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL, | ||
| 701 | .enable_bit = 7, | ||
| 702 | .rate_offset = 3, | ||
| 703 | .recalc = &omap2_clksel_recalc, | ||
| 704 | }; | ||
| 705 | |||
| 706 | /* In 2430, new in 2420 ES2 */ | ||
| 707 | static struct clk sys_clkout2 = { | ||
| 708 | .name = "sys_clkout2", | ||
| 709 | .parent = &func_54m_ck, | ||
| 710 | .rate = 54000000, | ||
| 711 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 712 | CM_SYSCLKOUT_SEL1 | RATE_CKCTL, | ||
| 713 | .src_offset = 8, | ||
| 714 | .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL, | ||
| 715 | .enable_bit = 15, | ||
| 716 | .rate_offset = 11, | ||
| 717 | .recalc = &omap2_clksel_recalc, | ||
| 718 | }; | ||
| 719 | |||
| 720 | static struct clk emul_ck = { | ||
| 721 | .name = "emul_ck", | ||
| 722 | .parent = &func_54m_ck, | ||
| 723 | .flags = CLOCK_IN_OMAP242X, | ||
| 724 | .enable_reg = (void __iomem *)&PRCM_CLKEMUL_CTRL, | ||
| 725 | .enable_bit = 0, | ||
| 726 | .recalc = &omap2_propagate_rate, | ||
| 727 | |||
| 728 | }; | ||
| 729 | |||
| 730 | /* | ||
| 731 | * MPU clock domain | ||
| 732 | * Clocks: | ||
| 733 | * MPU_FCLK, MPU_ICLK | ||
| 734 | * INT_M_FCLK, INT_M_I_CLK | ||
| 735 | * | ||
| 736 | * - Individual clocks are hardware managed. | ||
| 737 | * - Base divider comes from: CM_CLKSEL_MPU | ||
| 738 | * | ||
| 739 | */ | ||
| 740 | static struct clk mpu_ck = { /* Control cpu */ | ||
| 741 | .name = "mpu_ck", | ||
| 742 | .parent = &core_ck, | ||
| 743 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL | | ||
| 744 | ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP | | ||
| 745 | CONFIG_PARTICIPANT | RATE_PROPAGATES, | ||
| 746 | .rate_offset = 0, /* bits 0-4 */ | ||
| 747 | .recalc = &omap2_clksel_recalc, | ||
| 748 | }; | ||
| 749 | |||
| 750 | /* | ||
| 751 | * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain | ||
| 752 | * Clocks: | ||
| 753 | * 2430: IVA2.1_FCLK, IVA2.1_ICLK | ||
| 754 | * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP | ||
| 755 | */ | ||
| 756 | static struct clk iva2_1_fck = { | ||
| 757 | .name = "iva2_1_fck", | ||
| 758 | .parent = &core_ck, | ||
| 759 | .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 | | ||
| 760 | DELAYED_APP | RATE_PROPAGATES | | ||
| 761 | CONFIG_PARTICIPANT, | ||
| 762 | .rate_offset = 0, | ||
| 763 | .enable_reg = (void __iomem *)&CM_FCLKEN_DSP, | ||
| 764 | .enable_bit = 0, | ||
| 765 | .recalc = &omap2_clksel_recalc, | ||
| 766 | }; | ||
| 767 | |||
| 768 | static struct clk iva2_1_ick = { | ||
| 769 | .name = "iva2_1_ick", | ||
| 770 | .parent = &iva2_1_fck, | ||
| 771 | .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 | | ||
| 772 | DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 773 | .rate_offset = 5, | ||
| 774 | .recalc = &omap2_clksel_recalc, | ||
| 775 | }; | ||
| 776 | |||
| 777 | /* | ||
| 778 | * Won't be too specific here. The core clock comes into this block | ||
| 779 | * it is divided then tee'ed. One branch goes directly to xyz enable | ||
| 780 | * controls. The other branch gets further divided by 2 then possibly | ||
| 781 | * routed into a synchronizer and out of clocks abc. | ||
| 782 | */ | ||
| 783 | static struct clk dsp_fck = { | ||
| 784 | .name = "dsp_fck", | ||
| 785 | .parent = &core_ck, | ||
| 786 | .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 | | ||
| 787 | DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, | ||
| 788 | .rate_offset = 0, | ||
| 789 | .enable_reg = (void __iomem *)&CM_FCLKEN_DSP, | ||
| 790 | .enable_bit = 0, | ||
| 791 | .recalc = &omap2_clksel_recalc, | ||
| 792 | }; | ||
| 793 | |||
| 794 | static struct clk dsp_ick = { | ||
| 795 | .name = "dsp_ick", /* apparently ipi and isp */ | ||
| 796 | .parent = &dsp_fck, | ||
| 797 | .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 | | ||
| 798 | DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 799 | .rate_offset = 5, | ||
| 800 | .enable_reg = (void __iomem *)&CM_ICLKEN_DSP, | ||
| 801 | .enable_bit = 1, /* for ipi */ | ||
| 802 | .recalc = &omap2_clksel_recalc, | ||
| 803 | }; | ||
| 804 | |||
| 805 | static struct clk iva1_ifck = { | ||
| 806 | .name = "iva1_ifck", | ||
| 807 | .parent = &core_ck, | ||
| 808 | .flags = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL | | ||
| 809 | CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP, | ||
| 810 | .rate_offset= 8, | ||
| 811 | .enable_reg = (void __iomem *)&CM_FCLKEN_DSP, | ||
| 812 | .enable_bit = 10, | ||
| 813 | .recalc = &omap2_clksel_recalc, | ||
| 814 | }; | ||
| 815 | |||
| 816 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ | ||
| 817 | static struct clk iva1_mpu_int_ifck = { | ||
| 818 | .name = "iva1_mpu_int_ifck", | ||
| 819 | .parent = &iva1_ifck, | ||
| 820 | .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1, | ||
| 821 | .enable_reg = (void __iomem *)&CM_FCLKEN_DSP, | ||
| 822 | .enable_bit = 8, | ||
| 823 | .recalc = &omap2_clksel_recalc, | ||
| 824 | }; | ||
| 825 | |||
| 826 | /* | ||
| 827 | * L3 clock domain | ||
| 828 | * L3 clocks are used for both interface and functional clocks to | ||
| 829 | * multiple entities. Some of these clocks are completely managed | ||
| 830 | * by hardware, and some others allow software control. Hardware | ||
| 831 | * managed ones general are based on directly CLK_REQ signals and | ||
| 832 | * various auto idle settings. The functional spec sets many of these | ||
| 833 | * as 'tie-high' for their enables. | ||
| 834 | * | ||
| 835 | * I-CLOCKS: | ||
| 836 | * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA | ||
| 837 | * CAM, HS-USB. | ||
| 838 | * F-CLOCK | ||
| 839 | * SSI. | ||
| 840 | * | ||
| 841 | * GPMC memories and SDRC have timing and clock sensitive registers which | ||
| 842 | * may very well need notification when the clock changes. Currently for low | ||
| 843 | * operating points, these are taken care of in sleep.S. | ||
| 844 | */ | ||
| 845 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ | ||
| 846 | .name = "core_l3_ck", | ||
| 847 | .parent = &core_ck, | ||
| 848 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 849 | RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 | | ||
| 850 | DELAYED_APP | CONFIG_PARTICIPANT | | ||
| 851 | RATE_PROPAGATES, | ||
| 852 | .rate_offset = 0, | ||
| 853 | .recalc = &omap2_clksel_recalc, | ||
| 854 | }; | ||
| 855 | |||
| 856 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ | ||
| 857 | .name = "usb_l4_ick", | ||
| 858 | .parent = &core_l3_ck, | ||
| 859 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 860 | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP | | ||
| 861 | CONFIG_PARTICIPANT, | ||
| 862 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, | ||
| 863 | .enable_bit = 0, | ||
| 864 | .rate_offset = 25, | ||
| 865 | .recalc = &omap2_clksel_recalc, | ||
| 866 | }; | ||
| 867 | |||
| 868 | /* | ||
| 869 | * SSI is in L3 management domain, its direct parent is core not l3, | ||
| 870 | * many core power domain entities are grouped into the L3 clock | ||
| 871 | * domain. | ||
| 872 | * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK | ||
| 873 | * | ||
| 874 | * ssr = core/1/2/3/4/5, sst = 1/2 ssr. | ||
| 875 | */ | ||
| 876 | static struct clk ssi_ssr_sst_fck = { | ||
| 877 | .name = "ssi_fck", | ||
| 878 | .parent = &core_ck, | ||
| 879 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 880 | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP, | ||
| 881 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, /* bit 1 */ | ||
| 882 | .enable_bit = 1, | ||
| 883 | .rate_offset = 20, | ||
| 884 | .recalc = &omap2_clksel_recalc, | ||
| 885 | }; | ||
| 886 | |||
| 887 | /* | ||
| 888 | * GFX clock domain | ||
| 889 | * Clocks: | ||
| 890 | * GFX_FCLK, GFX_ICLK | ||
| 891 | * GFX_CG1(2d), GFX_CG2(3d) | ||
| 892 | * | ||
| 893 | * GFX_FCLK runs from L3, and is divided by (1,2,3,4) | ||
| 894 | * The 2d and 3d clocks run at a hardware determined | ||
| 895 | * divided value of fclk. | ||
| 896 | * | ||
| 897 | */ | ||
| 898 | static struct clk gfx_3d_fck = { | ||
| 899 | .name = "gfx_3d_fck", | ||
| 900 | .parent = &core_l3_ck, | ||
| 901 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 902 | RATE_CKCTL | CM_GFX_SEL1, | ||
| 903 | .enable_reg = (void __iomem *)&CM_FCLKEN_GFX, | ||
| 904 | .enable_bit = 2, | ||
| 905 | .rate_offset= 0, | ||
| 906 | .recalc = &omap2_clksel_recalc, | ||
| 907 | }; | ||
| 908 | |||
| 909 | static struct clk gfx_2d_fck = { | ||
| 910 | .name = "gfx_2d_fck", | ||
| 911 | .parent = &core_l3_ck, | ||
| 912 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 913 | RATE_CKCTL | CM_GFX_SEL1, | ||
| 914 | .enable_reg = (void __iomem *)&CM_FCLKEN_GFX, | ||
| 915 | .enable_bit = 1, | ||
| 916 | .rate_offset= 0, | ||
| 917 | .recalc = &omap2_clksel_recalc, | ||
| 918 | }; | ||
| 919 | |||
| 920 | static struct clk gfx_ick = { | ||
| 921 | .name = "gfx_ick", /* From l3 */ | ||
| 922 | .parent = &core_l3_ck, | ||
| 923 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 924 | RATE_CKCTL, | ||
| 925 | .enable_reg = (void __iomem *)&CM_ICLKEN_GFX, /* bit 0 */ | ||
| 926 | .enable_bit = 0, | ||
| 927 | .recalc = &omap2_followparent_recalc, | ||
| 928 | }; | ||
| 929 | |||
| 930 | /* | ||
| 931 | * Modem clock domain (2430) | ||
| 932 | * CLOCKS: | ||
| 933 | * MDM_OSC_CLK | ||
| 934 | * MDM_ICLK | ||
| 935 | */ | ||
| 936 | static struct clk mdm_ick = { /* used both as a ick and fck */ | ||
| 937 | .name = "mdm_ick", | ||
| 938 | .parent = &core_ck, | ||
| 939 | .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 | | ||
| 940 | DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 941 | .rate_offset = 0, | ||
| 942 | .enable_reg = (void __iomem *)&CM_ICLKEN_MDM, | ||
| 943 | .enable_bit = 0, | ||
| 944 | .recalc = &omap2_clksel_recalc, | ||
| 945 | }; | ||
| 946 | |||
| 947 | static struct clk mdm_osc_ck = { | ||
| 948 | .name = "mdm_osc_ck", | ||
| 949 | .rate = 26000000, | ||
| 950 | .parent = &osc_ck, | ||
| 951 | .flags = CLOCK_IN_OMAP243X | RATE_FIXED, | ||
| 952 | .enable_reg = (void __iomem *)&CM_FCLKEN_MDM, | ||
| 953 | .enable_bit = 1, | ||
| 954 | .recalc = &omap2_followparent_recalc, | ||
| 955 | }; | ||
| 956 | |||
| 957 | /* | ||
| 958 | * L4 clock management domain | ||
| 959 | * | ||
| 960 | * This domain contains lots of interface clocks from the L4 interface, some | ||
| 961 | * functional clocks. Fixed APLL functional source clocks are managed in | ||
| 962 | * this domain. | ||
| 963 | */ | ||
| 964 | static struct clk l4_ck = { /* used both as an ick and fck */ | ||
| 965 | .name = "l4_ck", | ||
| 966 | .parent = &core_l3_ck, | ||
| 967 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 968 | RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 | | ||
| 969 | DELAYED_APP | RATE_PROPAGATES, | ||
| 970 | .rate_offset = 5, | ||
| 971 | .recalc = &omap2_clksel_recalc, | ||
| 972 | }; | ||
| 973 | |||
| 974 | static struct clk ssi_l4_ick = { | ||
| 975 | .name = "ssi_l4_ick", | ||
| 976 | .parent = &l4_ck, | ||
| 977 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL, | ||
| 978 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, /* bit 1 */ | ||
| 979 | .enable_bit = 1, | ||
| 980 | .recalc = &omap2_followparent_recalc, | ||
| 981 | }; | ||
| 982 | |||
| 983 | /* | ||
| 984 | * DSS clock domain | ||
| 985 | * CLOCKs: | ||
| 986 | * DSS_L4_ICLK, DSS_L3_ICLK, | ||
| 987 | * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK | ||
| 988 | * | ||
| 989 | * DSS is both initiator and target. | ||
| 990 | */ | ||
| 991 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ | ||
| 992 | .name = "dss_ick", | ||
| 993 | .parent = &l4_ck, /* really both l3 and l4 */ | ||
| 994 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL, | ||
| 995 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 996 | .enable_bit = 0, | ||
| 997 | .recalc = &omap2_followparent_recalc, | ||
| 998 | }; | ||
| 999 | |||
| 1000 | static struct clk dss1_fck = { | ||
| 1001 | .name = "dss1_fck", | ||
| 1002 | .parent = &core_ck, /* Core or sys */ | ||
| 1003 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1004 | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP, | ||
| 1005 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1006 | .enable_bit = 0, | ||
| 1007 | .rate_offset = 8, | ||
| 1008 | .src_offset = 8, | ||
| 1009 | .recalc = &omap2_clksel_recalc, | ||
| 1010 | }; | ||
| 1011 | |||
| 1012 | static struct clk dss2_fck = { /* Alt clk used in power management */ | ||
| 1013 | .name = "dss2_fck", | ||
| 1014 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ | ||
| 1015 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1016 | RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED | | ||
| 1017 | DELAYED_APP, | ||
| 1018 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1019 | .enable_bit = 1, | ||
| 1020 | .src_offset = 13, | ||
| 1021 | .recalc = &omap2_followparent_recalc, | ||
| 1022 | }; | ||
| 1023 | |||
| 1024 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ | ||
| 1025 | .name = "dss_54m_fck", /* 54m tv clk */ | ||
| 1026 | .parent = &func_54m_ck, | ||
| 1027 | .rate = 54000000, | ||
| 1028 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1029 | RATE_FIXED | RATE_PROPAGATES, | ||
| 1030 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1031 | .enable_bit = 2, | ||
| 1032 | .recalc = &omap2_propagate_rate, | ||
| 1033 | }; | ||
| 1034 | |||
| 1035 | /* | ||
| 1036 | * CORE power domain ICLK & FCLK defines. | ||
| 1037 | * Many of the these can have more than one possible parent. Entries | ||
| 1038 | * here will likely have an L4 interface parent, and may have multiple | ||
| 1039 | * functional clock parents. | ||
| 1040 | */ | ||
| 1041 | static struct clk gpt1_ick = { | ||
| 1042 | .name = "gpt1_ick", | ||
| 1043 | .parent = &l4_ck, | ||
| 1044 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1045 | .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, /* Bit0 */ | ||
| 1046 | .enable_bit = 0, | ||
| 1047 | .recalc = &omap2_followparent_recalc, | ||
| 1048 | }; | ||
| 1049 | |||
| 1050 | static struct clk gpt1_fck = { | ||
| 1051 | .name = "gpt1_fck", | ||
| 1052 | .parent = &func_32k_ck, | ||
| 1053 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1054 | CM_WKUP_SEL1, | ||
| 1055 | .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, /* Bit0 */ | ||
| 1056 | .enable_bit = 0, | ||
| 1057 | .src_offset = 0, | ||
| 1058 | .recalc = &omap2_followparent_recalc, | ||
| 1059 | }; | ||
| 1060 | |||
| 1061 | static struct clk gpt2_ick = { | ||
| 1062 | .name = "gpt2_ick", | ||
| 1063 | .parent = &l4_ck, | ||
| 1064 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1065 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */ | ||
| 1066 | .enable_bit = 4, | ||
| 1067 | .recalc = &omap2_followparent_recalc, | ||
| 1068 | }; | ||
| 1069 | |||
| 1070 | static struct clk gpt2_fck = { | ||
| 1071 | .name = "gpt2_fck", | ||
| 1072 | .parent = &func_32k_ck, | ||
| 1073 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1074 | CM_CORE_SEL2, | ||
| 1075 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1076 | .enable_bit = 4, | ||
| 1077 | .src_offset = 2, | ||
| 1078 | .recalc = &omap2_followparent_recalc, | ||
| 1079 | }; | ||
| 1080 | |||
| 1081 | static struct clk gpt3_ick = { | ||
| 1082 | .name = "gpt3_ick", | ||
| 1083 | .parent = &l4_ck, | ||
| 1084 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1085 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit5 */ | ||
| 1086 | .enable_bit = 5, | ||
| 1087 | .recalc = &omap2_followparent_recalc, | ||
| 1088 | }; | ||
| 1089 | |||
| 1090 | static struct clk gpt3_fck = { | ||
| 1091 | .name = "gpt3_fck", | ||
| 1092 | .parent = &func_32k_ck, | ||
| 1093 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1094 | CM_CORE_SEL2, | ||
| 1095 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1096 | .enable_bit = 5, | ||
| 1097 | .src_offset = 4, | ||
| 1098 | .recalc = &omap2_followparent_recalc, | ||
| 1099 | }; | ||
| 1100 | |||
| 1101 | static struct clk gpt4_ick = { | ||
| 1102 | .name = "gpt4_ick", | ||
| 1103 | .parent = &l4_ck, | ||
| 1104 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1105 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit6 */ | ||
| 1106 | .enable_bit = 6, | ||
| 1107 | .recalc = &omap2_followparent_recalc, | ||
| 1108 | }; | ||
| 1109 | |||
| 1110 | static struct clk gpt4_fck = { | ||
| 1111 | .name = "gpt4_fck", | ||
| 1112 | .parent = &func_32k_ck, | ||
| 1113 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1114 | CM_CORE_SEL2, | ||
| 1115 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1116 | .enable_bit = 6, | ||
| 1117 | .src_offset = 6, | ||
| 1118 | .recalc = &omap2_followparent_recalc, | ||
| 1119 | }; | ||
| 1120 | |||
| 1121 | static struct clk gpt5_ick = { | ||
| 1122 | .name = "gpt5_ick", | ||
| 1123 | .parent = &l4_ck, | ||
| 1124 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1125 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit7 */ | ||
| 1126 | .enable_bit = 7, | ||
| 1127 | .recalc = &omap2_followparent_recalc, | ||
| 1128 | }; | ||
| 1129 | |||
| 1130 | static struct clk gpt5_fck = { | ||
| 1131 | .name = "gpt5_fck", | ||
| 1132 | .parent = &func_32k_ck, | ||
| 1133 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1134 | CM_CORE_SEL2, | ||
| 1135 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1136 | .enable_bit = 7, | ||
| 1137 | .src_offset = 8, | ||
| 1138 | .recalc = &omap2_followparent_recalc, | ||
| 1139 | }; | ||
| 1140 | |||
| 1141 | static struct clk gpt6_ick = { | ||
| 1142 | .name = "gpt6_ick", | ||
| 1143 | .parent = &l4_ck, | ||
| 1144 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1145 | .enable_bit = 8, | ||
| 1146 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit8 */ | ||
| 1147 | .recalc = &omap2_followparent_recalc, | ||
| 1148 | }; | ||
| 1149 | |||
| 1150 | static struct clk gpt6_fck = { | ||
| 1151 | .name = "gpt6_fck", | ||
| 1152 | .parent = &func_32k_ck, | ||
| 1153 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1154 | CM_CORE_SEL2, | ||
| 1155 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1156 | .enable_bit = 8, | ||
| 1157 | .src_offset = 10, | ||
| 1158 | .recalc = &omap2_followparent_recalc, | ||
| 1159 | }; | ||
| 1160 | |||
| 1161 | static struct clk gpt7_ick = { | ||
| 1162 | .name = "gpt7_ick", | ||
| 1163 | .parent = &l4_ck, | ||
| 1164 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1165 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit9 */ | ||
| 1166 | .enable_bit = 9, | ||
| 1167 | .recalc = &omap2_followparent_recalc, | ||
| 1168 | }; | ||
| 1169 | |||
| 1170 | static struct clk gpt7_fck = { | ||
| 1171 | .name = "gpt7_fck", | ||
| 1172 | .parent = &func_32k_ck, | ||
| 1173 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1174 | CM_CORE_SEL2, | ||
| 1175 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1176 | .enable_bit = 9, | ||
| 1177 | .src_offset = 12, | ||
| 1178 | .recalc = &omap2_followparent_recalc, | ||
| 1179 | }; | ||
| 1180 | |||
| 1181 | static struct clk gpt8_ick = { | ||
| 1182 | .name = "gpt8_ick", | ||
| 1183 | .parent = &l4_ck, | ||
| 1184 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1185 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit10 */ | ||
| 1186 | .enable_bit = 10, | ||
| 1187 | .recalc = &omap2_followparent_recalc, | ||
| 1188 | }; | ||
| 1189 | |||
| 1190 | static struct clk gpt8_fck = { | ||
| 1191 | .name = "gpt8_fck", | ||
| 1192 | .parent = &func_32k_ck, | ||
| 1193 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1194 | CM_CORE_SEL2, | ||
| 1195 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1196 | .enable_bit = 10, | ||
| 1197 | .src_offset = 14, | ||
| 1198 | .recalc = &omap2_followparent_recalc, | ||
| 1199 | }; | ||
| 1200 | |||
| 1201 | static struct clk gpt9_ick = { | ||
| 1202 | .name = "gpt9_ick", | ||
| 1203 | .parent = &l4_ck, | ||
| 1204 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1205 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1206 | .enable_bit = 11, | ||
| 1207 | .recalc = &omap2_followparent_recalc, | ||
| 1208 | }; | ||
| 1209 | |||
| 1210 | static struct clk gpt9_fck = { | ||
| 1211 | .name = "gpt9_fck", | ||
| 1212 | .parent = &func_32k_ck, | ||
| 1213 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1214 | CM_CORE_SEL2, | ||
| 1215 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1216 | .enable_bit = 11, | ||
| 1217 | .src_offset = 16, | ||
| 1218 | .recalc = &omap2_followparent_recalc, | ||
| 1219 | }; | ||
| 1220 | |||
| 1221 | static struct clk gpt10_ick = { | ||
| 1222 | .name = "gpt10_ick", | ||
| 1223 | .parent = &l4_ck, | ||
| 1224 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1225 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1226 | .enable_bit = 12, | ||
| 1227 | .recalc = &omap2_followparent_recalc, | ||
| 1228 | }; | ||
| 1229 | |||
| 1230 | static struct clk gpt10_fck = { | ||
| 1231 | .name = "gpt10_fck", | ||
| 1232 | .parent = &func_32k_ck, | ||
| 1233 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1234 | CM_CORE_SEL2, | ||
| 1235 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1236 | .enable_bit = 12, | ||
| 1237 | .src_offset = 18, | ||
| 1238 | .recalc = &omap2_followparent_recalc, | ||
| 1239 | }; | ||
| 1240 | |||
| 1241 | static struct clk gpt11_ick = { | ||
| 1242 | .name = "gpt11_ick", | ||
| 1243 | .parent = &l4_ck, | ||
| 1244 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1245 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1246 | .enable_bit = 13, | ||
| 1247 | .recalc = &omap2_followparent_recalc, | ||
| 1248 | }; | ||
| 1249 | |||
| 1250 | static struct clk gpt11_fck = { | ||
| 1251 | .name = "gpt11_fck", | ||
| 1252 | .parent = &func_32k_ck, | ||
| 1253 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1254 | CM_CORE_SEL2, | ||
| 1255 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1256 | .enable_bit = 13, | ||
| 1257 | .src_offset = 20, | ||
| 1258 | .recalc = &omap2_followparent_recalc, | ||
| 1259 | }; | ||
| 1260 | |||
| 1261 | static struct clk gpt12_ick = { | ||
| 1262 | .name = "gpt12_ick", | ||
| 1263 | .parent = &l4_ck, | ||
| 1264 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1265 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit14 */ | ||
| 1266 | .enable_bit = 14, | ||
| 1267 | .recalc = &omap2_followparent_recalc, | ||
| 1268 | }; | ||
| 1269 | |||
| 1270 | static struct clk gpt12_fck = { | ||
| 1271 | .name = "gpt12_fck", | ||
| 1272 | .parent = &func_32k_ck, | ||
| 1273 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1274 | CM_CORE_SEL2, | ||
| 1275 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1276 | .enable_bit = 14, | ||
| 1277 | .src_offset = 22, | ||
| 1278 | .recalc = &omap2_followparent_recalc, | ||
| 1279 | }; | ||
| 1280 | |||
| 1281 | static struct clk mcbsp1_ick = { | ||
| 1282 | .name = "mcbsp1_ick", | ||
| 1283 | .parent = &l4_ck, | ||
| 1284 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1285 | .enable_bit = 15, | ||
| 1286 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit16 */ | ||
| 1287 | .recalc = &omap2_followparent_recalc, | ||
| 1288 | }; | ||
| 1289 | |||
| 1290 | static struct clk mcbsp1_fck = { | ||
| 1291 | .name = "mcbsp1_fck", | ||
| 1292 | .parent = &func_96m_ck, | ||
| 1293 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1294 | .enable_bit = 15, | ||
| 1295 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1296 | .recalc = &omap2_followparent_recalc, | ||
| 1297 | }; | ||
| 1298 | |||
| 1299 | static struct clk mcbsp2_ick = { | ||
| 1300 | .name = "mcbsp2_ick", | ||
| 1301 | .parent = &l4_ck, | ||
| 1302 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1303 | .enable_bit = 16, | ||
| 1304 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1305 | .recalc = &omap2_followparent_recalc, | ||
| 1306 | }; | ||
| 1307 | |||
| 1308 | static struct clk mcbsp2_fck = { | ||
| 1309 | .name = "mcbsp2_fck", | ||
| 1310 | .parent = &func_96m_ck, | ||
| 1311 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1312 | .enable_bit = 16, | ||
| 1313 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1314 | .recalc = &omap2_followparent_recalc, | ||
| 1315 | }; | ||
| 1316 | |||
| 1317 | static struct clk mcbsp3_ick = { | ||
| 1318 | .name = "mcbsp3_ick", | ||
| 1319 | .parent = &l4_ck, | ||
| 1320 | .flags = CLOCK_IN_OMAP243X, | ||
| 1321 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, | ||
| 1322 | .enable_bit = 3, | ||
| 1323 | .recalc = &omap2_followparent_recalc, | ||
| 1324 | }; | ||
| 1325 | |||
| 1326 | static struct clk mcbsp3_fck = { | ||
| 1327 | .name = "mcbsp3_fck", | ||
| 1328 | .parent = &func_96m_ck, | ||
| 1329 | .flags = CLOCK_IN_OMAP243X, | ||
| 1330 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, | ||
| 1331 | .enable_bit = 3, | ||
| 1332 | .recalc = &omap2_followparent_recalc, | ||
| 1333 | }; | ||
| 1334 | |||
| 1335 | static struct clk mcbsp4_ick = { | ||
| 1336 | .name = "mcbsp4_ick", | ||
| 1337 | .parent = &l4_ck, | ||
| 1338 | .flags = CLOCK_IN_OMAP243X, | ||
| 1339 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, | ||
| 1340 | .enable_bit = 4, | ||
| 1341 | .recalc = &omap2_followparent_recalc, | ||
| 1342 | }; | ||
| 1343 | |||
| 1344 | static struct clk mcbsp4_fck = { | ||
| 1345 | .name = "mcbsp4_fck", | ||
| 1346 | .parent = &func_96m_ck, | ||
| 1347 | .flags = CLOCK_IN_OMAP243X, | ||
| 1348 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, | ||
| 1349 | .enable_bit = 4, | ||
| 1350 | .recalc = &omap2_followparent_recalc, | ||
| 1351 | }; | ||
| 1352 | |||
| 1353 | static struct clk mcbsp5_ick = { | ||
| 1354 | .name = "mcbsp5_ick", | ||
| 1355 | .parent = &l4_ck, | ||
| 1356 | .flags = CLOCK_IN_OMAP243X, | ||
| 1357 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, | ||
| 1358 | .enable_bit = 5, | ||
| 1359 | .recalc = &omap2_followparent_recalc, | ||
| 1360 | }; | ||
| 1361 | |||
| 1362 | static struct clk mcbsp5_fck = { | ||
| 1363 | .name = "mcbsp5_fck", | ||
| 1364 | .parent = &func_96m_ck, | ||
| 1365 | .flags = CLOCK_IN_OMAP243X, | ||
| 1366 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, | ||
| 1367 | .enable_bit = 5, | ||
| 1368 | .recalc = &omap2_followparent_recalc, | ||
| 1369 | }; | ||
| 1370 | |||
| 1371 | static struct clk mcspi1_ick = { | ||
| 1372 | .name = "mcspi_ick", | ||
| 1373 | .id = 1, | ||
| 1374 | .parent = &l4_ck, | ||
| 1375 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1376 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1377 | .enable_bit = 17, | ||
| 1378 | .recalc = &omap2_followparent_recalc, | ||
| 1379 | }; | ||
| 1380 | |||
| 1381 | static struct clk mcspi1_fck = { | ||
| 1382 | .name = "mcspi_fck", | ||
| 1383 | .id = 1, | ||
| 1384 | .parent = &func_48m_ck, | ||
| 1385 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1386 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1387 | .enable_bit = 17, | ||
| 1388 | .recalc = &omap2_followparent_recalc, | ||
| 1389 | }; | ||
| 1390 | |||
| 1391 | static struct clk mcspi2_ick = { | ||
| 1392 | .name = "mcspi_ick", | ||
| 1393 | .id = 2, | ||
| 1394 | .parent = &l4_ck, | ||
| 1395 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1396 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1397 | .enable_bit = 18, | ||
| 1398 | .recalc = &omap2_followparent_recalc, | ||
| 1399 | }; | ||
| 1400 | |||
| 1401 | static struct clk mcspi2_fck = { | ||
| 1402 | .name = "mcspi_fck", | ||
| 1403 | .id = 2, | ||
| 1404 | .parent = &func_48m_ck, | ||
| 1405 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1406 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1407 | .enable_bit = 18, | ||
| 1408 | .recalc = &omap2_followparent_recalc, | ||
| 1409 | }; | ||
| 1410 | |||
| 1411 | static struct clk mcspi3_ick = { | ||
| 1412 | .name = "mcspi_ick", | ||
| 1413 | .id = 3, | ||
| 1414 | .parent = &l4_ck, | ||
| 1415 | .flags = CLOCK_IN_OMAP243X, | ||
| 1416 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, | ||
| 1417 | .enable_bit = 9, | ||
| 1418 | .recalc = &omap2_followparent_recalc, | ||
| 1419 | }; | ||
| 1420 | |||
| 1421 | static struct clk mcspi3_fck = { | ||
| 1422 | .name = "mcspi_fck", | ||
| 1423 | .id = 3, | ||
| 1424 | .parent = &func_48m_ck, | ||
| 1425 | .flags = CLOCK_IN_OMAP243X, | ||
| 1426 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, | ||
| 1427 | .enable_bit = 9, | ||
| 1428 | .recalc = &omap2_followparent_recalc, | ||
| 1429 | }; | ||
| 1430 | |||
| 1431 | static struct clk uart1_ick = { | ||
| 1432 | .name = "uart1_ick", | ||
| 1433 | .parent = &l4_ck, | ||
| 1434 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1435 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1436 | .enable_bit = 21, | ||
| 1437 | .recalc = &omap2_followparent_recalc, | ||
| 1438 | }; | ||
| 1439 | |||
| 1440 | static struct clk uart1_fck = { | ||
| 1441 | .name = "uart1_fck", | ||
| 1442 | .parent = &func_48m_ck, | ||
| 1443 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1444 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1445 | .enable_bit = 21, | ||
| 1446 | .recalc = &omap2_followparent_recalc, | ||
| 1447 | }; | ||
| 1448 | |||
| 1449 | static struct clk uart2_ick = { | ||
| 1450 | .name = "uart2_ick", | ||
| 1451 | .parent = &l4_ck, | ||
| 1452 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1453 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1454 | .enable_bit = 22, | ||
| 1455 | .recalc = &omap2_followparent_recalc, | ||
| 1456 | }; | ||
| 1457 | |||
| 1458 | static struct clk uart2_fck = { | ||
| 1459 | .name = "uart2_fck", | ||
| 1460 | .parent = &func_48m_ck, | ||
| 1461 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1462 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1463 | .enable_bit = 22, | ||
| 1464 | .recalc = &omap2_followparent_recalc, | ||
| 1465 | }; | ||
| 1466 | |||
| 1467 | static struct clk uart3_ick = { | ||
| 1468 | .name = "uart3_ick", | ||
| 1469 | .parent = &l4_ck, | ||
| 1470 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1471 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, | ||
| 1472 | .enable_bit = 2, | ||
| 1473 | .recalc = &omap2_followparent_recalc, | ||
| 1474 | }; | ||
| 1475 | |||
| 1476 | static struct clk uart3_fck = { | ||
| 1477 | .name = "uart3_fck", | ||
| 1478 | .parent = &func_48m_ck, | ||
| 1479 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1480 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, | ||
| 1481 | .enable_bit = 2, | ||
| 1482 | .recalc = &omap2_followparent_recalc, | ||
| 1483 | }; | ||
| 1484 | |||
| 1485 | static struct clk gpios_ick = { | ||
| 1486 | .name = "gpios_ick", | ||
| 1487 | .parent = &l4_ck, | ||
| 1488 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1489 | .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, | ||
| 1490 | .enable_bit = 2, | ||
| 1491 | .recalc = &omap2_followparent_recalc, | ||
| 1492 | }; | ||
| 1493 | |||
| 1494 | static struct clk gpios_fck = { | ||
| 1495 | .name = "gpios_fck", | ||
| 1496 | .parent = &func_32k_ck, | ||
| 1497 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1498 | .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, | ||
| 1499 | .enable_bit = 2, | ||
| 1500 | .recalc = &omap2_followparent_recalc, | ||
| 1501 | }; | ||
| 1502 | |||
| 1503 | static struct clk mpu_wdt_ick = { | ||
| 1504 | .name = "mpu_wdt_ick", | ||
| 1505 | .parent = &l4_ck, | ||
| 1506 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1507 | .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, | ||
| 1508 | .enable_bit = 3, | ||
| 1509 | .recalc = &omap2_followparent_recalc, | ||
| 1510 | }; | ||
| 1511 | |||
| 1512 | static struct clk mpu_wdt_fck = { | ||
| 1513 | .name = "mpu_wdt_fck", | ||
| 1514 | .parent = &func_32k_ck, | ||
| 1515 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1516 | .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, | ||
| 1517 | .enable_bit = 3, | ||
| 1518 | .recalc = &omap2_followparent_recalc, | ||
| 1519 | }; | ||
| 1520 | |||
| 1521 | static struct clk sync_32k_ick = { | ||
| 1522 | .name = "sync_32k_ick", | ||
| 1523 | .parent = &l4_ck, | ||
| 1524 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1525 | .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, | ||
| 1526 | .enable_bit = 1, | ||
| 1527 | .recalc = &omap2_followparent_recalc, | ||
| 1528 | }; | ||
| 1529 | static struct clk wdt1_ick = { | ||
| 1530 | .name = "wdt1_ick", | ||
| 1531 | .parent = &l4_ck, | ||
| 1532 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1533 | .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, | ||
| 1534 | .enable_bit = 4, | ||
| 1535 | .recalc = &omap2_followparent_recalc, | ||
| 1536 | }; | ||
| 1537 | static struct clk omapctrl_ick = { | ||
| 1538 | .name = "omapctrl_ick", | ||
| 1539 | .parent = &l4_ck, | ||
| 1540 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1541 | .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, | ||
| 1542 | .enable_bit = 5, | ||
| 1543 | .recalc = &omap2_followparent_recalc, | ||
| 1544 | }; | ||
| 1545 | static struct clk icr_ick = { | ||
| 1546 | .name = "icr_ick", | ||
| 1547 | .parent = &l4_ck, | ||
| 1548 | .flags = CLOCK_IN_OMAP243X, | ||
| 1549 | .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, | ||
| 1550 | .enable_bit = 6, | ||
| 1551 | .recalc = &omap2_followparent_recalc, | ||
| 1552 | }; | ||
| 1553 | |||
| 1554 | static struct clk cam_ick = { | ||
| 1555 | .name = "cam_ick", | ||
| 1556 | .parent = &l4_ck, | ||
| 1557 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1558 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1559 | .enable_bit = 31, | ||
| 1560 | .recalc = &omap2_followparent_recalc, | ||
| 1561 | }; | ||
| 1562 | |||
| 1563 | static struct clk cam_fck = { | ||
| 1564 | .name = "cam_fck", | ||
| 1565 | .parent = &func_96m_ck, | ||
| 1566 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1567 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1568 | .enable_bit = 31, | ||
| 1569 | .recalc = &omap2_followparent_recalc, | ||
| 1570 | }; | ||
| 1571 | |||
| 1572 | static struct clk mailboxes_ick = { | ||
| 1573 | .name = "mailboxes_ick", | ||
| 1574 | .parent = &l4_ck, | ||
| 1575 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1576 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1577 | .enable_bit = 30, | ||
| 1578 | .recalc = &omap2_followparent_recalc, | ||
| 1579 | }; | ||
| 1580 | |||
| 1581 | static struct clk wdt4_ick = { | ||
| 1582 | .name = "wdt4_ick", | ||
| 1583 | .parent = &l4_ck, | ||
| 1584 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1585 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1586 | .enable_bit = 29, | ||
| 1587 | .recalc = &omap2_followparent_recalc, | ||
| 1588 | }; | ||
| 1589 | |||
| 1590 | static struct clk wdt4_fck = { | ||
| 1591 | .name = "wdt4_fck", | ||
| 1592 | .parent = &func_32k_ck, | ||
| 1593 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1594 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1595 | .enable_bit = 29, | ||
| 1596 | .recalc = &omap2_followparent_recalc, | ||
| 1597 | }; | ||
| 1598 | |||
| 1599 | static struct clk wdt3_ick = { | ||
| 1600 | .name = "wdt3_ick", | ||
| 1601 | .parent = &l4_ck, | ||
| 1602 | .flags = CLOCK_IN_OMAP242X, | ||
| 1603 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1604 | .enable_bit = 28, | ||
| 1605 | .recalc = &omap2_followparent_recalc, | ||
| 1606 | }; | ||
| 1607 | |||
| 1608 | static struct clk wdt3_fck = { | ||
| 1609 | .name = "wdt3_fck", | ||
| 1610 | .parent = &func_32k_ck, | ||
| 1611 | .flags = CLOCK_IN_OMAP242X, | ||
| 1612 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1613 | .enable_bit = 28, | ||
| 1614 | .recalc = &omap2_followparent_recalc, | ||
| 1615 | }; | ||
| 1616 | |||
| 1617 | static struct clk mspro_ick = { | ||
| 1618 | .name = "mspro_ick", | ||
| 1619 | .parent = &l4_ck, | ||
| 1620 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1621 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1622 | .enable_bit = 27, | ||
| 1623 | .recalc = &omap2_followparent_recalc, | ||
| 1624 | }; | ||
| 1625 | |||
| 1626 | static struct clk mspro_fck = { | ||
| 1627 | .name = "mspro_fck", | ||
| 1628 | .parent = &func_96m_ck, | ||
| 1629 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1630 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1631 | .enable_bit = 27, | ||
| 1632 | .recalc = &omap2_followparent_recalc, | ||
| 1633 | }; | ||
| 1634 | |||
| 1635 | static struct clk mmc_ick = { | ||
| 1636 | .name = "mmc_ick", | ||
| 1637 | .parent = &l4_ck, | ||
| 1638 | .flags = CLOCK_IN_OMAP242X, | ||
| 1639 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1640 | .enable_bit = 26, | ||
| 1641 | .recalc = &omap2_followparent_recalc, | ||
| 1642 | }; | ||
| 1643 | |||
| 1644 | static struct clk mmc_fck = { | ||
| 1645 | .name = "mmc_fck", | ||
| 1646 | .parent = &func_96m_ck, | ||
| 1647 | .flags = CLOCK_IN_OMAP242X, | ||
| 1648 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1649 | .enable_bit = 26, | ||
| 1650 | .recalc = &omap2_followparent_recalc, | ||
| 1651 | }; | ||
| 1652 | |||
| 1653 | static struct clk fac_ick = { | ||
| 1654 | .name = "fac_ick", | ||
| 1655 | .parent = &l4_ck, | ||
| 1656 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1657 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1658 | .enable_bit = 25, | ||
| 1659 | .recalc = &omap2_followparent_recalc, | ||
| 1660 | }; | ||
| 1661 | |||
| 1662 | static struct clk fac_fck = { | ||
| 1663 | .name = "fac_fck", | ||
| 1664 | .parent = &func_12m_ck, | ||
| 1665 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1666 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1667 | .enable_bit = 25, | ||
| 1668 | .recalc = &omap2_followparent_recalc, | ||
| 1669 | }; | ||
| 1670 | |||
| 1671 | static struct clk eac_ick = { | ||
| 1672 | .name = "eac_ick", | ||
| 1673 | .parent = &l4_ck, | ||
| 1674 | .flags = CLOCK_IN_OMAP242X, | ||
| 1675 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1676 | .enable_bit = 24, | ||
| 1677 | .recalc = &omap2_followparent_recalc, | ||
| 1678 | }; | ||
| 1679 | |||
| 1680 | static struct clk eac_fck = { | ||
| 1681 | .name = "eac_fck", | ||
| 1682 | .parent = &func_96m_ck, | ||
| 1683 | .flags = CLOCK_IN_OMAP242X, | ||
| 1684 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1685 | .enable_bit = 24, | ||
| 1686 | .recalc = &omap2_followparent_recalc, | ||
| 1687 | }; | ||
| 1688 | |||
| 1689 | static struct clk hdq_ick = { | ||
| 1690 | .name = "hdq_ick", | ||
| 1691 | .parent = &l4_ck, | ||
| 1692 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1693 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1694 | .enable_bit = 23, | ||
| 1695 | .recalc = &omap2_followparent_recalc, | ||
| 1696 | }; | ||
| 1697 | |||
| 1698 | static struct clk hdq_fck = { | ||
| 1699 | .name = "hdq_fck", | ||
| 1700 | .parent = &func_12m_ck, | ||
| 1701 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1702 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1703 | .enable_bit = 23, | ||
| 1704 | .recalc = &omap2_followparent_recalc, | ||
| 1705 | }; | ||
| 1706 | |||
| 1707 | static struct clk i2c2_ick = { | ||
| 1708 | .name = "i2c_ick", | ||
| 1709 | .id = 2, | ||
| 1710 | .parent = &l4_ck, | ||
| 1711 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1712 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1713 | .enable_bit = 20, | ||
| 1714 | .recalc = &omap2_followparent_recalc, | ||
| 1715 | }; | ||
| 1716 | |||
| 1717 | static struct clk i2c2_fck = { | ||
| 1718 | .name = "i2c_fck", | ||
| 1719 | .id = 2, | ||
| 1720 | .parent = &func_12m_ck, | ||
| 1721 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1722 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1723 | .enable_bit = 20, | ||
| 1724 | .recalc = &omap2_followparent_recalc, | ||
| 1725 | }; | ||
| 1726 | |||
| 1727 | static struct clk i2chs2_fck = { | ||
| 1728 | .name = "i2chs2_fck", | ||
| 1729 | .parent = &func_96m_ck, | ||
| 1730 | .flags = CLOCK_IN_OMAP243X, | ||
| 1731 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, | ||
| 1732 | .enable_bit = 20, | ||
| 1733 | .recalc = &omap2_followparent_recalc, | ||
| 1734 | }; | ||
| 1735 | |||
| 1736 | static struct clk i2c1_ick = { | ||
| 1737 | .name = "i2c_ick", | ||
| 1738 | .id = 1, | ||
| 1739 | .parent = &l4_ck, | ||
| 1740 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1741 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1742 | .enable_bit = 19, | ||
| 1743 | .recalc = &omap2_followparent_recalc, | ||
| 1744 | }; | ||
| 1745 | |||
| 1746 | static struct clk i2c1_fck = { | ||
| 1747 | .name = "i2c_fck", | ||
| 1748 | .id = 1, | ||
| 1749 | .parent = &func_12m_ck, | ||
| 1750 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1751 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1752 | .enable_bit = 19, | ||
| 1753 | .recalc = &omap2_followparent_recalc, | ||
| 1754 | }; | ||
| 1755 | |||
| 1756 | static struct clk i2chs1_fck = { | ||
| 1757 | .name = "i2chs1_fck", | ||
| 1758 | .parent = &func_96m_ck, | ||
| 1759 | .flags = CLOCK_IN_OMAP243X, | ||
| 1760 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, | ||
| 1761 | .enable_bit = 19, | ||
| 1762 | .recalc = &omap2_followparent_recalc, | ||
| 1763 | }; | ||
| 1764 | |||
| 1765 | static struct clk vlynq_ick = { | ||
| 1766 | .name = "vlynq_ick", | ||
| 1767 | .parent = &core_l3_ck, | ||
| 1768 | .flags = CLOCK_IN_OMAP242X, | ||
| 1769 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, | ||
| 1770 | .enable_bit = 3, | ||
| 1771 | .recalc = &omap2_followparent_recalc, | ||
| 1772 | }; | ||
| 1773 | |||
| 1774 | static struct clk vlynq_fck = { | ||
| 1775 | .name = "vlynq_fck", | ||
| 1776 | .parent = &func_96m_ck, | ||
| 1777 | .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP, | ||
| 1778 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, | ||
| 1779 | .enable_bit = 3, | ||
| 1780 | .src_offset = 15, | ||
| 1781 | .recalc = &omap2_followparent_recalc, | ||
| 1782 | }; | ||
| 1783 | |||
| 1784 | static struct clk sdrc_ick = { | ||
| 1785 | .name = "sdrc_ick", | ||
| 1786 | .parent = &l4_ck, | ||
| 1787 | .flags = CLOCK_IN_OMAP243X, | ||
| 1788 | .enable_reg = (void __iomem *)&CM_ICLKEN3_CORE, | ||
| 1789 | .enable_bit = 2, | ||
| 1790 | .recalc = &omap2_followparent_recalc, | ||
| 1791 | }; | ||
| 1792 | |||
| 1793 | static struct clk des_ick = { | ||
| 1794 | .name = "des_ick", | ||
| 1795 | .parent = &l4_ck, | ||
| 1796 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 1797 | .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE, | ||
| 1798 | .enable_bit = 0, | ||
| 1799 | .recalc = &omap2_followparent_recalc, | ||
| 1800 | }; | ||
| 1801 | |||
| 1802 | static struct clk sha_ick = { | ||
| 1803 | .name = "sha_ick", | ||
| 1804 | .parent = &l4_ck, | ||
| 1805 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 1806 | .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE, | ||
| 1807 | .enable_bit = 1, | ||
| 1808 | .recalc = &omap2_followparent_recalc, | ||
| 1809 | }; | ||
| 1810 | |||
| 1811 | static struct clk rng_ick = { | ||
| 1812 | .name = "rng_ick", | ||
| 1813 | .parent = &l4_ck, | ||
| 1814 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 1815 | .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE, | ||
| 1816 | .enable_bit = 2, | ||
| 1817 | .recalc = &omap2_followparent_recalc, | ||
| 1818 | }; | ||
| 1819 | |||
| 1820 | static struct clk aes_ick = { | ||
| 1821 | .name = "aes_ick", | ||
| 1822 | .parent = &l4_ck, | ||
| 1823 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 1824 | .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE, | ||
| 1825 | .enable_bit = 3, | ||
| 1826 | .recalc = &omap2_followparent_recalc, | ||
| 1827 | }; | ||
| 1828 | |||
| 1829 | static struct clk pka_ick = { | ||
| 1830 | .name = "pka_ick", | ||
| 1831 | .parent = &l4_ck, | ||
| 1832 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 1833 | .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE, | ||
| 1834 | .enable_bit = 4, | ||
| 1835 | .recalc = &omap2_followparent_recalc, | ||
| 1836 | }; | ||
| 1837 | |||
| 1838 | static struct clk usb_fck = { | ||
| 1839 | .name = "usb_fck", | ||
| 1840 | .parent = &func_48m_ck, | ||
| 1841 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 1842 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, | ||
| 1843 | .enable_bit = 0, | ||
| 1844 | .recalc = &omap2_followparent_recalc, | ||
| 1845 | }; | ||
| 1846 | |||
| 1847 | static struct clk usbhs_ick = { | ||
| 1848 | .name = "usbhs_ick", | ||
| 1849 | .parent = &core_l3_ck, | ||
| 1850 | .flags = CLOCK_IN_OMAP243X, | ||
| 1851 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, | ||
| 1852 | .enable_bit = 6, | ||
| 1853 | .recalc = &omap2_followparent_recalc, | ||
| 1854 | }; | ||
| 1855 | |||
| 1856 | static struct clk mmchs1_ick = { | ||
| 1857 | .name = "mmchs1_ick", | ||
| 1858 | .parent = &l4_ck, | ||
| 1859 | .flags = CLOCK_IN_OMAP243X, | ||
| 1860 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, | ||
| 1861 | .enable_bit = 7, | ||
| 1862 | .recalc = &omap2_followparent_recalc, | ||
| 1863 | }; | ||
| 1864 | |||
| 1865 | static struct clk mmchs1_fck = { | ||
| 1866 | .name = "mmchs1_fck", | ||
| 1867 | .parent = &func_96m_ck, | ||
| 1868 | .flags = CLOCK_IN_OMAP243X, | ||
| 1869 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, | ||
| 1870 | .enable_bit = 7, | ||
| 1871 | .recalc = &omap2_followparent_recalc, | ||
| 1872 | }; | ||
| 1873 | |||
| 1874 | static struct clk mmchs2_ick = { | ||
| 1875 | .name = "mmchs2_ick", | ||
| 1876 | .parent = &l4_ck, | ||
| 1877 | .flags = CLOCK_IN_OMAP243X, | ||
| 1878 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, | ||
| 1879 | .enable_bit = 8, | ||
| 1880 | .recalc = &omap2_followparent_recalc, | ||
| 1881 | }; | ||
| 1882 | |||
| 1883 | static struct clk mmchs2_fck = { | ||
| 1884 | .name = "mmchs2_fck", | ||
| 1885 | .parent = &func_96m_ck, | ||
| 1886 | .flags = CLOCK_IN_OMAP243X, | ||
| 1887 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, | ||
| 1888 | .enable_bit = 8, | ||
| 1889 | .recalc = &omap2_followparent_recalc, | ||
| 1890 | }; | ||
| 1891 | 32 | ||
| 1892 | static struct clk gpio5_ick = { | 33 | void omap2_clksel_recalc(struct clk *clk); |
| 1893 | .name = "gpio5_ick", | 34 | void omap2_init_clksel_parent(struct clk *clk); |
| 1894 | .parent = &l4_ck, | 35 | u32 omap2_clksel_get_divisor(struct clk *clk); |
| 1895 | .flags = CLOCK_IN_OMAP243X, | 36 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, |
| 1896 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, | 37 | u32 *new_div); |
| 1897 | .enable_bit = 10, | 38 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); |
| 1898 | .recalc = &omap2_followparent_recalc, | 39 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); |
| 1899 | }; | 40 | void omap2_fixed_divisor_recalc(struct clk *clk); |
| 41 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); | ||
| 42 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); | ||
| 43 | u32 omap2_get_dpll_rate(struct clk *clk); | ||
| 44 | int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); | ||
| 1900 | 45 | ||
| 1901 | static struct clk gpio5_fck = { | 46 | extern u8 cpu_mask; |
| 1902 | .name = "gpio5_fck", | ||
| 1903 | .parent = &func_32k_ck, | ||
| 1904 | .flags = CLOCK_IN_OMAP243X, | ||
| 1905 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, | ||
| 1906 | .enable_bit = 10, | ||
| 1907 | .recalc = &omap2_followparent_recalc, | ||
| 1908 | }; | ||
| 1909 | 47 | ||
| 1910 | static struct clk mdm_intc_ick = { | 48 | /* clksel_rate data common to 24xx/343x */ |
| 1911 | .name = "mdm_intc_ick", | 49 | static const struct clksel_rate gpt_32k_rates[] = { |
| 1912 | .parent = &l4_ck, | 50 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, |
| 1913 | .flags = CLOCK_IN_OMAP243X, | 51 | { .div = 0 } |
| 1914 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, | ||
| 1915 | .enable_bit = 11, | ||
| 1916 | .recalc = &omap2_followparent_recalc, | ||
| 1917 | }; | 52 | }; |
| 1918 | 53 | ||
| 1919 | static struct clk mmchsdb1_fck = { | 54 | static const struct clksel_rate gpt_sys_rates[] = { |
| 1920 | .name = "mmchsdb1_fck", | 55 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, |
| 1921 | .parent = &func_32k_ck, | 56 | { .div = 0 } |
| 1922 | .flags = CLOCK_IN_OMAP243X, | ||
| 1923 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, | ||
| 1924 | .enable_bit = 16, | ||
| 1925 | .recalc = &omap2_followparent_recalc, | ||
| 1926 | }; | 57 | }; |
| 1927 | 58 | ||
| 1928 | static struct clk mmchsdb2_fck = { | 59 | static const struct clksel_rate gfx_l3_rates[] = { |
| 1929 | .name = "mmchsdb2_fck", | 60 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X }, |
| 1930 | .parent = &func_32k_ck, | 61 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, |
| 1931 | .flags = CLOCK_IN_OMAP243X, | 62 | { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X }, |
| 1932 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, | 63 | { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X }, |
| 1933 | .enable_bit = 17, | 64 | { .div = 0 } |
| 1934 | .recalc = &omap2_followparent_recalc, | ||
| 1935 | }; | 65 | }; |
| 1936 | 66 | ||
| 1937 | /* | ||
| 1938 | * This clock is a composite clock which does entire set changes then | ||
| 1939 | * forces a rebalance. It keys on the MPU speed, but it really could | ||
| 1940 | * be any key speed part of a set in the rate table. | ||
| 1941 | * | ||
| 1942 | * to really change a set, you need memory table sets which get changed | ||
| 1943 | * in sram, pre-notifiers & post notifiers, changing the top set, without | ||
| 1944 | * having low level display recalc's won't work... this is why dpm notifiers | ||
| 1945 | * work, isr's off, walk a list of clocks already _off_ and not messing with | ||
| 1946 | * the bus. | ||
| 1947 | * | ||
| 1948 | * This clock should have no parent. It embodies the entire upper level | ||
| 1949 | * active set. A parent will mess up some of the init also. | ||
| 1950 | */ | ||
| 1951 | static struct clk virt_prcm_set = { | ||
| 1952 | .name = "virt_prcm_set", | ||
| 1953 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1954 | VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP, | ||
| 1955 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ | ||
| 1956 | .recalc = &omap2_mpu_recalc, /* sets are keyed on mpu rate */ | ||
| 1957 | .set_rate = &omap2_select_table_rate, | ||
| 1958 | .round_rate = &omap2_round_to_table_rate, | ||
| 1959 | }; | ||
| 1960 | |||
| 1961 | static struct clk *onchip_clks[] = { | ||
| 1962 | /* external root sources */ | ||
| 1963 | &func_32k_ck, | ||
| 1964 | &osc_ck, | ||
| 1965 | &sys_ck, | ||
| 1966 | &alt_ck, | ||
| 1967 | /* internal analog sources */ | ||
| 1968 | &dpll_ck, | ||
| 1969 | &apll96_ck, | ||
| 1970 | &apll54_ck, | ||
| 1971 | /* internal prcm root sources */ | ||
| 1972 | &func_54m_ck, | ||
| 1973 | &core_ck, | ||
| 1974 | &sleep_ck, | ||
| 1975 | &func_96m_ck, | ||
| 1976 | &func_48m_ck, | ||
| 1977 | &func_12m_ck, | ||
| 1978 | &wdt1_osc_ck, | ||
| 1979 | &sys_clkout, | ||
| 1980 | &sys_clkout2, | ||
| 1981 | &emul_ck, | ||
| 1982 | /* mpu domain clocks */ | ||
| 1983 | &mpu_ck, | ||
| 1984 | /* dsp domain clocks */ | ||
| 1985 | &iva2_1_fck, /* 2430 */ | ||
| 1986 | &iva2_1_ick, | ||
| 1987 | &dsp_ick, /* 2420 */ | ||
| 1988 | &dsp_fck, | ||
| 1989 | &iva1_ifck, | ||
| 1990 | &iva1_mpu_int_ifck, | ||
| 1991 | /* GFX domain clocks */ | ||
| 1992 | &gfx_3d_fck, | ||
| 1993 | &gfx_2d_fck, | ||
| 1994 | &gfx_ick, | ||
| 1995 | /* Modem domain clocks */ | ||
| 1996 | &mdm_ick, | ||
| 1997 | &mdm_osc_ck, | ||
| 1998 | /* DSS domain clocks */ | ||
| 1999 | &dss_ick, | ||
| 2000 | &dss1_fck, | ||
| 2001 | &dss2_fck, | ||
| 2002 | &dss_54m_fck, | ||
| 2003 | /* L3 domain clocks */ | ||
| 2004 | &core_l3_ck, | ||
| 2005 | &ssi_ssr_sst_fck, | ||
| 2006 | &usb_l4_ick, | ||
| 2007 | /* L4 domain clocks */ | ||
| 2008 | &l4_ck, /* used as both core_l4 and wu_l4 */ | ||
| 2009 | &ssi_l4_ick, | ||
| 2010 | /* virtual meta-group clock */ | ||
| 2011 | &virt_prcm_set, | ||
| 2012 | /* general l4 interface ck, multi-parent functional clk */ | ||
| 2013 | &gpt1_ick, | ||
| 2014 | &gpt1_fck, | ||
| 2015 | &gpt2_ick, | ||
| 2016 | &gpt2_fck, | ||
| 2017 | &gpt3_ick, | ||
| 2018 | &gpt3_fck, | ||
| 2019 | &gpt4_ick, | ||
| 2020 | &gpt4_fck, | ||
| 2021 | &gpt5_ick, | ||
| 2022 | &gpt5_fck, | ||
| 2023 | &gpt6_ick, | ||
| 2024 | &gpt6_fck, | ||
| 2025 | &gpt7_ick, | ||
| 2026 | &gpt7_fck, | ||
| 2027 | &gpt8_ick, | ||
| 2028 | &gpt8_fck, | ||
| 2029 | &gpt9_ick, | ||
| 2030 | &gpt9_fck, | ||
| 2031 | &gpt10_ick, | ||
| 2032 | &gpt10_fck, | ||
| 2033 | &gpt11_ick, | ||
| 2034 | &gpt11_fck, | ||
| 2035 | &gpt12_ick, | ||
| 2036 | &gpt12_fck, | ||
| 2037 | &mcbsp1_ick, | ||
| 2038 | &mcbsp1_fck, | ||
| 2039 | &mcbsp2_ick, | ||
| 2040 | &mcbsp2_fck, | ||
| 2041 | &mcbsp3_ick, | ||
| 2042 | &mcbsp3_fck, | ||
| 2043 | &mcbsp4_ick, | ||
| 2044 | &mcbsp4_fck, | ||
| 2045 | &mcbsp5_ick, | ||
| 2046 | &mcbsp5_fck, | ||
| 2047 | &mcspi1_ick, | ||
| 2048 | &mcspi1_fck, | ||
| 2049 | &mcspi2_ick, | ||
| 2050 | &mcspi2_fck, | ||
| 2051 | &mcspi3_ick, | ||
| 2052 | &mcspi3_fck, | ||
| 2053 | &uart1_ick, | ||
| 2054 | &uart1_fck, | ||
| 2055 | &uart2_ick, | ||
| 2056 | &uart2_fck, | ||
| 2057 | &uart3_ick, | ||
| 2058 | &uart3_fck, | ||
| 2059 | &gpios_ick, | ||
| 2060 | &gpios_fck, | ||
| 2061 | &mpu_wdt_ick, | ||
| 2062 | &mpu_wdt_fck, | ||
| 2063 | &sync_32k_ick, | ||
| 2064 | &wdt1_ick, | ||
| 2065 | &omapctrl_ick, | ||
| 2066 | &icr_ick, | ||
| 2067 | &cam_fck, | ||
| 2068 | &cam_ick, | ||
| 2069 | &mailboxes_ick, | ||
| 2070 | &wdt4_ick, | ||
| 2071 | &wdt4_fck, | ||
| 2072 | &wdt3_ick, | ||
| 2073 | &wdt3_fck, | ||
| 2074 | &mspro_ick, | ||
| 2075 | &mspro_fck, | ||
| 2076 | &mmc_ick, | ||
| 2077 | &mmc_fck, | ||
| 2078 | &fac_ick, | ||
| 2079 | &fac_fck, | ||
| 2080 | &eac_ick, | ||
| 2081 | &eac_fck, | ||
| 2082 | &hdq_ick, | ||
| 2083 | &hdq_fck, | ||
| 2084 | &i2c1_ick, | ||
| 2085 | &i2c1_fck, | ||
| 2086 | &i2chs1_fck, | ||
| 2087 | &i2c2_ick, | ||
| 2088 | &i2c2_fck, | ||
| 2089 | &i2chs2_fck, | ||
| 2090 | &vlynq_ick, | ||
| 2091 | &vlynq_fck, | ||
| 2092 | &sdrc_ick, | ||
| 2093 | &des_ick, | ||
| 2094 | &sha_ick, | ||
| 2095 | &rng_ick, | ||
| 2096 | &aes_ick, | ||
| 2097 | &pka_ick, | ||
| 2098 | &usb_fck, | ||
| 2099 | &usbhs_ick, | ||
| 2100 | &mmchs1_ick, | ||
| 2101 | &mmchs1_fck, | ||
| 2102 | &mmchs2_ick, | ||
| 2103 | &mmchs2_fck, | ||
| 2104 | &gpio5_ick, | ||
| 2105 | &gpio5_fck, | ||
| 2106 | &mdm_intc_ick, | ||
| 2107 | &mmchsdb1_fck, | ||
| 2108 | &mmchsdb2_fck, | ||
| 2109 | }; | ||
| 2110 | 67 | ||
| 2111 | #endif | 68 | #endif |
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c new file mode 100644 index 000000000000..ece32d8acba4 --- /dev/null +++ b/arch/arm/mach-omap2/clock24xx.c | |||
| @@ -0,0 +1,539 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/clock.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2004-2008 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Contacts: | ||
| 8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 9 | * Paul Walmsley | ||
| 10 | * | ||
| 11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, | ||
| 12 | * Gordon McNutt and RidgeRun, Inc. | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | */ | ||
| 18 | #undef DEBUG | ||
| 19 | |||
| 20 | #include <linux/module.h> | ||
| 21 | #include <linux/kernel.h> | ||
| 22 | #include <linux/device.h> | ||
| 23 | #include <linux/list.h> | ||
| 24 | #include <linux/errno.h> | ||
| 25 | #include <linux/delay.h> | ||
| 26 | #include <linux/clk.h> | ||
| 27 | |||
| 28 | #include <linux/io.h> | ||
| 29 | #include <linux/cpufreq.h> | ||
| 30 | |||
| 31 | #include <asm/arch/clock.h> | ||
| 32 | #include <asm/arch/sram.h> | ||
| 33 | #include <asm/div64.h> | ||
| 34 | #include <asm/bitops.h> | ||
| 35 | |||
| 36 | #include "memory.h" | ||
| 37 | #include "clock.h" | ||
| 38 | #include "clock24xx.h" | ||
| 39 | #include "prm.h" | ||
| 40 | #include "prm-regbits-24xx.h" | ||
| 41 | #include "cm.h" | ||
| 42 | #include "cm-regbits-24xx.h" | ||
| 43 | |||
| 44 | /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ | ||
| 45 | #define EN_APLL_STOPPED 0 | ||
| 46 | #define EN_APLL_LOCKED 3 | ||
| 47 | |||
| 48 | /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */ | ||
| 49 | #define APLLS_CLKIN_19_2MHZ 0 | ||
| 50 | #define APLLS_CLKIN_13MHZ 2 | ||
| 51 | #define APLLS_CLKIN_12MHZ 3 | ||
| 52 | |||
| 53 | /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ | ||
| 54 | |||
| 55 | static struct prcm_config *curr_prcm_set; | ||
| 56 | static struct clk *vclk; | ||
| 57 | static struct clk *sclk; | ||
| 58 | |||
| 59 | /*------------------------------------------------------------------------- | ||
| 60 | * Omap24xx specific clock functions | ||
| 61 | *-------------------------------------------------------------------------*/ | ||
| 62 | |||
| 63 | /* This actually returns the rate of core_ck, not dpll_ck. */ | ||
| 64 | static u32 omap2_get_dpll_rate_24xx(struct clk *tclk) | ||
| 65 | { | ||
| 66 | long long dpll_clk; | ||
| 67 | u8 amult; | ||
| 68 | |||
| 69 | dpll_clk = omap2_get_dpll_rate(tclk); | ||
| 70 | |||
| 71 | amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
| 72 | amult &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
| 73 | dpll_clk *= amult; | ||
| 74 | |||
| 75 | return dpll_clk; | ||
| 76 | } | ||
| 77 | |||
| 78 | static int omap2_enable_osc_ck(struct clk *clk) | ||
| 79 | { | ||
| 80 | u32 pcc; | ||
| 81 | |||
| 82 | pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); | ||
| 83 | |||
| 84 | __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, | ||
| 85 | OMAP24XX_PRCM_CLKSRC_CTRL); | ||
| 86 | |||
| 87 | return 0; | ||
| 88 | } | ||
| 89 | |||
| 90 | static void omap2_disable_osc_ck(struct clk *clk) | ||
| 91 | { | ||
| 92 | u32 pcc; | ||
| 93 | |||
| 94 | pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); | ||
| 95 | |||
| 96 | __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, | ||
| 97 | OMAP24XX_PRCM_CLKSRC_CTRL); | ||
| 98 | } | ||
| 99 | |||
| 100 | #ifdef OLD_CK | ||
| 101 | /* Recalculate SYST_CLK */ | ||
| 102 | static void omap2_sys_clk_recalc(struct clk * clk) | ||
| 103 | { | ||
| 104 | u32 div = PRCM_CLKSRC_CTRL; | ||
| 105 | div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ | ||
| 106 | div >>= clk->rate_offset; | ||
| 107 | clk->rate = (clk->parent->rate / div); | ||
| 108 | propagate_rate(clk); | ||
| 109 | } | ||
| 110 | #endif /* OLD_CK */ | ||
| 111 | |||
| 112 | /* Enable an APLL if off */ | ||
| 113 | static int omap2_clk_fixed_enable(struct clk *clk) | ||
| 114 | { | ||
| 115 | u32 cval, apll_mask; | ||
| 116 | |||
| 117 | apll_mask = EN_APLL_LOCKED << clk->enable_bit; | ||
| 118 | |||
| 119 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); | ||
| 120 | |||
| 121 | if ((cval & apll_mask) == apll_mask) | ||
| 122 | return 0; /* apll already enabled */ | ||
| 123 | |||
| 124 | cval &= ~apll_mask; | ||
| 125 | cval |= apll_mask; | ||
| 126 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | ||
| 127 | |||
| 128 | if (clk == &apll96_ck) | ||
| 129 | cval = OMAP24XX_ST_96M_APLL; | ||
| 130 | else if (clk == &apll54_ck) | ||
| 131 | cval = OMAP24XX_ST_54M_APLL; | ||
| 132 | |||
| 133 | omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval, | ||
| 134 | clk->name); | ||
| 135 | |||
| 136 | /* | ||
| 137 | * REVISIT: Should we return an error code if omap2_wait_clock_ready() | ||
| 138 | * fails? | ||
| 139 | */ | ||
| 140 | return 0; | ||
| 141 | } | ||
| 142 | |||
| 143 | /* Stop APLL */ | ||
| 144 | static void omap2_clk_fixed_disable(struct clk *clk) | ||
| 145 | { | ||
| 146 | u32 cval; | ||
| 147 | |||
| 148 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); | ||
| 149 | cval &= ~(EN_APLL_LOCKED << clk->enable_bit); | ||
| 150 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | ||
| 151 | } | ||
| 152 | |||
| 153 | /* | ||
| 154 | * Uses the current prcm set to tell if a rate is valid. | ||
| 155 | * You can go slower, but not faster within a given rate set. | ||
| 156 | */ | ||
| 157 | static u32 omap2_dpll_round_rate(unsigned long target_rate) | ||
| 158 | { | ||
| 159 | u32 high, low, core_clk_src; | ||
| 160 | |||
| 161 | core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
| 162 | core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
| 163 | |||
| 164 | if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ | ||
| 165 | high = curr_prcm_set->dpll_speed * 2; | ||
| 166 | low = curr_prcm_set->dpll_speed; | ||
| 167 | } else { /* DPLL clockout x 2 */ | ||
| 168 | high = curr_prcm_set->dpll_speed; | ||
| 169 | low = curr_prcm_set->dpll_speed / 2; | ||
| 170 | } | ||
| 171 | |||
| 172 | #ifdef DOWN_VARIABLE_DPLL | ||
| 173 | if (target_rate > high) | ||
| 174 | return high; | ||
| 175 | else | ||
| 176 | return target_rate; | ||
| 177 | #else | ||
| 178 | if (target_rate > low) | ||
| 179 | return high; | ||
| 180 | else | ||
| 181 | return low; | ||
| 182 | #endif | ||
| 183 | |||
| 184 | } | ||
| 185 | |||
| 186 | static void omap2_dpll_recalc(struct clk *clk) | ||
| 187 | { | ||
| 188 | clk->rate = omap2_get_dpll_rate_24xx(clk); | ||
| 189 | |||
| 190 | propagate_rate(clk); | ||
| 191 | } | ||
| 192 | |||
| 193 | static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate) | ||
| 194 | { | ||
| 195 | u32 cur_rate, low, mult, div, valid_rate, done_rate; | ||
| 196 | u32 bypass = 0; | ||
| 197 | struct prcm_config tmpset; | ||
| 198 | const struct dpll_data *dd; | ||
| 199 | unsigned long flags; | ||
| 200 | int ret = -EINVAL; | ||
| 201 | |||
| 202 | local_irq_save(flags); | ||
| 203 | cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); | ||
| 204 | mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
| 205 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
| 206 | |||
| 207 | if ((rate == (cur_rate / 2)) && (mult == 2)) { | ||
| 208 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); | ||
| 209 | } else if ((rate == (cur_rate * 2)) && (mult == 1)) { | ||
| 210 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); | ||
| 211 | } else if (rate != cur_rate) { | ||
| 212 | valid_rate = omap2_dpll_round_rate(rate); | ||
| 213 | if (valid_rate != rate) | ||
| 214 | goto dpll_exit; | ||
| 215 | |||
| 216 | if (mult == 1) | ||
| 217 | low = curr_prcm_set->dpll_speed; | ||
| 218 | else | ||
| 219 | low = curr_prcm_set->dpll_speed / 2; | ||
| 220 | |||
| 221 | dd = clk->dpll_data; | ||
| 222 | if (!dd) | ||
| 223 | goto dpll_exit; | ||
| 224 | |||
| 225 | tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); | ||
| 226 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | | ||
| 227 | dd->div1_mask); | ||
| 228 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); | ||
| 229 | tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | ||
| 230 | tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; | ||
| 231 | if (rate > low) { | ||
| 232 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; | ||
| 233 | mult = ((rate / 2) / 1000000); | ||
| 234 | done_rate = CORE_CLK_SRC_DPLL_X2; | ||
| 235 | } else { | ||
| 236 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; | ||
| 237 | mult = (rate / 1000000); | ||
| 238 | done_rate = CORE_CLK_SRC_DPLL; | ||
| 239 | } | ||
| 240 | tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); | ||
| 241 | tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); | ||
| 242 | |||
| 243 | /* Worst case */ | ||
| 244 | tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; | ||
| 245 | |||
| 246 | if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ | ||
| 247 | bypass = 1; | ||
| 248 | |||
| 249 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */ | ||
| 250 | |||
| 251 | /* Force dll lock mode */ | ||
| 252 | omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, | ||
| 253 | bypass); | ||
| 254 | |||
| 255 | /* Errata: ret dll entry state */ | ||
| 256 | omap2_init_memory_params(omap2_dll_force_needed()); | ||
| 257 | omap2_reprogram_sdrc(done_rate, 0); | ||
| 258 | } | ||
| 259 | omap2_dpll_recalc(&dpll_ck); | ||
| 260 | ret = 0; | ||
| 261 | |||
| 262 | dpll_exit: | ||
| 263 | local_irq_restore(flags); | ||
| 264 | return(ret); | ||
| 265 | } | ||
| 266 | |||
| 267 | /** | ||
| 268 | * omap2_table_mpu_recalc - just return the MPU speed | ||
| 269 | * @clk: virt_prcm_set struct clk | ||
| 270 | * | ||
| 271 | * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. | ||
| 272 | */ | ||
| 273 | static void omap2_table_mpu_recalc(struct clk *clk) | ||
| 274 | { | ||
| 275 | clk->rate = curr_prcm_set->mpu_speed; | ||
| 276 | } | ||
| 277 | |||
| 278 | /* | ||
| 279 | * Look for a rate equal or less than the target rate given a configuration set. | ||
| 280 | * | ||
| 281 | * What's not entirely clear is "which" field represents the key field. | ||
| 282 | * Some might argue L3-DDR, others ARM, others IVA. This code is simple and | ||
| 283 | * just uses the ARM rates. | ||
| 284 | */ | ||
| 285 | static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) | ||
| 286 | { | ||
| 287 | struct prcm_config *ptr; | ||
| 288 | long highest_rate; | ||
| 289 | |||
| 290 | if (clk != &virt_prcm_set) | ||
| 291 | return -EINVAL; | ||
| 292 | |||
| 293 | highest_rate = -EINVAL; | ||
| 294 | |||
| 295 | for (ptr = rate_table; ptr->mpu_speed; ptr++) { | ||
| 296 | if (!(ptr->flags & cpu_mask)) | ||
| 297 | continue; | ||
| 298 | if (ptr->xtal_speed != sys_ck.rate) | ||
| 299 | continue; | ||
| 300 | |||
| 301 | highest_rate = ptr->mpu_speed; | ||
| 302 | |||
| 303 | /* Can check only after xtal frequency check */ | ||
| 304 | if (ptr->mpu_speed <= rate) | ||
| 305 | break; | ||
| 306 | } | ||
| 307 | return highest_rate; | ||
| 308 | } | ||
| 309 | |||
| 310 | /* Sets basic clocks based on the specified rate */ | ||
| 311 | static int omap2_select_table_rate(struct clk *clk, unsigned long rate) | ||
| 312 | { | ||
| 313 | u32 cur_rate, done_rate, bypass = 0, tmp; | ||
| 314 | struct prcm_config *prcm; | ||
| 315 | unsigned long found_speed = 0; | ||
| 316 | unsigned long flags; | ||
| 317 | |||
| 318 | if (clk != &virt_prcm_set) | ||
| 319 | return -EINVAL; | ||
| 320 | |||
| 321 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
| 322 | if (!(prcm->flags & cpu_mask)) | ||
| 323 | continue; | ||
| 324 | |||
| 325 | if (prcm->xtal_speed != sys_ck.rate) | ||
| 326 | continue; | ||
| 327 | |||
| 328 | if (prcm->mpu_speed <= rate) { | ||
| 329 | found_speed = prcm->mpu_speed; | ||
| 330 | break; | ||
| 331 | } | ||
| 332 | } | ||
| 333 | |||
| 334 | if (!found_speed) { | ||
| 335 | printk(KERN_INFO "Could not set MPU rate to %luMHz\n", | ||
| 336 | rate / 1000000); | ||
| 337 | return -EINVAL; | ||
| 338 | } | ||
| 339 | |||
| 340 | curr_prcm_set = prcm; | ||
| 341 | cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); | ||
| 342 | |||
| 343 | if (prcm->dpll_speed == cur_rate / 2) { | ||
| 344 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); | ||
| 345 | } else if (prcm->dpll_speed == cur_rate * 2) { | ||
| 346 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); | ||
| 347 | } else if (prcm->dpll_speed != cur_rate) { | ||
| 348 | local_irq_save(flags); | ||
| 349 | |||
| 350 | if (prcm->dpll_speed == prcm->xtal_speed) | ||
| 351 | bypass = 1; | ||
| 352 | |||
| 353 | if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == | ||
| 354 | CORE_CLK_SRC_DPLL_X2) | ||
| 355 | done_rate = CORE_CLK_SRC_DPLL_X2; | ||
| 356 | else | ||
| 357 | done_rate = CORE_CLK_SRC_DPLL; | ||
| 358 | |||
| 359 | /* MPU divider */ | ||
| 360 | cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); | ||
| 361 | |||
| 362 | /* dsp + iva1 div(2420), iva2.1(2430) */ | ||
| 363 | cm_write_mod_reg(prcm->cm_clksel_dsp, | ||
| 364 | OMAP24XX_DSP_MOD, CM_CLKSEL); | ||
| 365 | |||
| 366 | cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); | ||
| 367 | |||
| 368 | /* Major subsystem dividers */ | ||
| 369 | tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; | ||
| 370 | cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1); | ||
| 371 | if (cpu_is_omap2430()) | ||
| 372 | cm_write_mod_reg(prcm->cm_clksel_mdm, | ||
| 373 | OMAP2430_MDM_MOD, CM_CLKSEL); | ||
| 374 | |||
| 375 | /* x2 to enter init_mem */ | ||
| 376 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); | ||
| 377 | |||
| 378 | omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, | ||
| 379 | bypass); | ||
| 380 | |||
| 381 | omap2_init_memory_params(omap2_dll_force_needed()); | ||
| 382 | omap2_reprogram_sdrc(done_rate, 0); | ||
| 383 | |||
| 384 | local_irq_restore(flags); | ||
| 385 | } | ||
| 386 | omap2_dpll_recalc(&dpll_ck); | ||
| 387 | |||
| 388 | return 0; | ||
| 389 | } | ||
| 390 | |||
| 391 | static struct clk_functions omap2_clk_functions = { | ||
| 392 | .clk_enable = omap2_clk_enable, | ||
| 393 | .clk_disable = omap2_clk_disable, | ||
| 394 | .clk_round_rate = omap2_clk_round_rate, | ||
| 395 | .clk_set_rate = omap2_clk_set_rate, | ||
| 396 | .clk_set_parent = omap2_clk_set_parent, | ||
| 397 | .clk_disable_unused = omap2_clk_disable_unused, | ||
| 398 | }; | ||
| 399 | |||
| 400 | static u32 omap2_get_apll_clkin(void) | ||
| 401 | { | ||
| 402 | u32 aplls, sclk = 0; | ||
| 403 | |||
| 404 | aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); | ||
| 405 | aplls &= OMAP24XX_APLLS_CLKIN_MASK; | ||
| 406 | aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; | ||
| 407 | |||
| 408 | if (aplls == APLLS_CLKIN_19_2MHZ) | ||
| 409 | sclk = 19200000; | ||
| 410 | else if (aplls == APLLS_CLKIN_13MHZ) | ||
| 411 | sclk = 13000000; | ||
| 412 | else if (aplls == APLLS_CLKIN_12MHZ) | ||
| 413 | sclk = 12000000; | ||
| 414 | |||
| 415 | return sclk; | ||
| 416 | } | ||
| 417 | |||
| 418 | static u32 omap2_get_sysclkdiv(void) | ||
| 419 | { | ||
| 420 | u32 div; | ||
| 421 | |||
| 422 | div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); | ||
| 423 | div &= OMAP_SYSCLKDIV_MASK; | ||
| 424 | div >>= OMAP_SYSCLKDIV_SHIFT; | ||
| 425 | |||
| 426 | return div; | ||
| 427 | } | ||
| 428 | |||
| 429 | static void omap2_osc_clk_recalc(struct clk *clk) | ||
| 430 | { | ||
| 431 | clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv(); | ||
| 432 | propagate_rate(clk); | ||
| 433 | } | ||
| 434 | |||
| 435 | static void omap2_sys_clk_recalc(struct clk *clk) | ||
| 436 | { | ||
| 437 | clk->rate = clk->parent->rate / omap2_get_sysclkdiv(); | ||
| 438 | propagate_rate(clk); | ||
| 439 | } | ||
| 440 | |||
| 441 | /* | ||
| 442 | * Set clocks for bypass mode for reboot to work. | ||
| 443 | */ | ||
| 444 | void omap2_clk_prepare_for_reboot(void) | ||
| 445 | { | ||
| 446 | u32 rate; | ||
| 447 | |||
| 448 | if (vclk == NULL || sclk == NULL) | ||
| 449 | return; | ||
| 450 | |||
| 451 | rate = clk_get_rate(sclk); | ||
| 452 | clk_set_rate(vclk, rate); | ||
| 453 | } | ||
| 454 | |||
| 455 | /* | ||
| 456 | * Switch the MPU rate if specified on cmdline. | ||
| 457 | * We cannot do this early until cmdline is parsed. | ||
| 458 | */ | ||
| 459 | static int __init omap2_clk_arch_init(void) | ||
| 460 | { | ||
| 461 | if (!mpurate) | ||
| 462 | return -EINVAL; | ||
| 463 | |||
| 464 | if (omap2_select_table_rate(&virt_prcm_set, mpurate)) | ||
| 465 | printk(KERN_ERR "Could not find matching MPU rate\n"); | ||
| 466 | |||
| 467 | recalculate_root_clocks(); | ||
| 468 | |||
| 469 | printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): " | ||
| 470 | "%ld.%01ld/%ld/%ld MHz\n", | ||
| 471 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | ||
| 472 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | ||
| 473 | |||
| 474 | return 0; | ||
| 475 | } | ||
| 476 | arch_initcall(omap2_clk_arch_init); | ||
| 477 | |||
| 478 | int __init omap2_clk_init(void) | ||
| 479 | { | ||
| 480 | struct prcm_config *prcm; | ||
| 481 | struct clk **clkp; | ||
| 482 | u32 clkrate; | ||
| 483 | |||
| 484 | if (cpu_is_omap242x()) | ||
| 485 | cpu_mask = RATE_IN_242X; | ||
| 486 | else if (cpu_is_omap2430()) | ||
| 487 | cpu_mask = RATE_IN_243X; | ||
| 488 | |||
| 489 | clk_init(&omap2_clk_functions); | ||
| 490 | |||
| 491 | omap2_osc_clk_recalc(&osc_ck); | ||
| 492 | omap2_sys_clk_recalc(&sys_ck); | ||
| 493 | |||
| 494 | for (clkp = onchip_24xx_clks; | ||
| 495 | clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks); | ||
| 496 | clkp++) { | ||
| 497 | |||
| 498 | if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) { | ||
| 499 | clk_register(*clkp); | ||
| 500 | continue; | ||
| 501 | } | ||
| 502 | |||
| 503 | if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) { | ||
| 504 | clk_register(*clkp); | ||
| 505 | continue; | ||
| 506 | } | ||
| 507 | } | ||
| 508 | |||
| 509 | /* Check the MPU rate set by bootloader */ | ||
| 510 | clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); | ||
| 511 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
| 512 | if (!(prcm->flags & cpu_mask)) | ||
| 513 | continue; | ||
| 514 | if (prcm->xtal_speed != sys_ck.rate) | ||
| 515 | continue; | ||
| 516 | if (prcm->dpll_speed <= clkrate) | ||
| 517 | break; | ||
| 518 | } | ||
| 519 | curr_prcm_set = prcm; | ||
| 520 | |||
| 521 | recalculate_root_clocks(); | ||
| 522 | |||
| 523 | printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " | ||
| 524 | "%ld.%01ld/%ld/%ld MHz\n", | ||
| 525 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | ||
| 526 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | ||
| 527 | |||
| 528 | /* | ||
| 529 | * Only enable those clocks we will need, let the drivers | ||
| 530 | * enable other clocks as necessary | ||
| 531 | */ | ||
| 532 | clk_enable_init_clocks(); | ||
| 533 | |||
| 534 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ | ||
| 535 | vclk = clk_get(NULL, "virt_prcm_set"); | ||
| 536 | sclk = clk_get(NULL, "sys_ck"); | ||
| 537 | |||
| 538 | return 0; | ||
| 539 | } | ||
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h new file mode 100644 index 000000000000..88081ed13f96 --- /dev/null +++ b/arch/arm/mach-omap2/clock24xx.h | |||
| @@ -0,0 +1,2643 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/clock24xx.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2004-2008 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Contacts: | ||
| 8 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 9 | * Paul Walmsley | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H | ||
| 17 | #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H | ||
| 18 | |||
| 19 | #include "clock.h" | ||
| 20 | |||
| 21 | #include "prm.h" | ||
| 22 | #include "cm.h" | ||
| 23 | #include "prm-regbits-24xx.h" | ||
| 24 | #include "cm-regbits-24xx.h" | ||
| 25 | #include "sdrc.h" | ||
| 26 | |||
| 27 | static void omap2_table_mpu_recalc(struct clk *clk); | ||
| 28 | static int omap2_select_table_rate(struct clk *clk, unsigned long rate); | ||
| 29 | static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); | ||
| 30 | static void omap2_sys_clk_recalc(struct clk *clk); | ||
| 31 | static void omap2_osc_clk_recalc(struct clk *clk); | ||
| 32 | static void omap2_sys_clk_recalc(struct clk *clk); | ||
| 33 | static void omap2_dpll_recalc(struct clk *clk); | ||
| 34 | static int omap2_clk_fixed_enable(struct clk *clk); | ||
| 35 | static void omap2_clk_fixed_disable(struct clk *clk); | ||
| 36 | static int omap2_enable_osc_ck(struct clk *clk); | ||
| 37 | static void omap2_disable_osc_ck(struct clk *clk); | ||
| 38 | static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate); | ||
| 39 | |||
| 40 | /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. | ||
| 41 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP | ||
| 42 | * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM | ||
| 43 | */ | ||
| 44 | struct prcm_config { | ||
| 45 | unsigned long xtal_speed; /* crystal rate */ | ||
| 46 | unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */ | ||
| 47 | unsigned long mpu_speed; /* speed of MPU */ | ||
| 48 | unsigned long cm_clksel_mpu; /* mpu divider */ | ||
| 49 | unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */ | ||
| 50 | unsigned long cm_clksel_gfx; /* gfx dividers */ | ||
| 51 | unsigned long cm_clksel1_core; /* major subsystem dividers */ | ||
| 52 | unsigned long cm_clksel1_pll; /* m,n */ | ||
| 53 | unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ | ||
| 54 | unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ | ||
| 55 | unsigned long base_sdrc_rfr; /* base refresh timing for a set */ | ||
| 56 | unsigned char flags; | ||
| 57 | }; | ||
| 58 | |||
| 59 | /* | ||
| 60 | * The OMAP2 processor can be run at several discrete 'PRCM configurations'. | ||
| 61 | * These configurations are characterized by voltage and speed for clocks. | ||
| 62 | * The device is only validated for certain combinations. One way to express | ||
| 63 | * these combinations is via the 'ratio's' which the clocks operate with | ||
| 64 | * respect to each other. These ratio sets are for a given voltage/DPLL | ||
| 65 | * setting. All configurations can be described by a DPLL setting and a ratio | ||
| 66 | * There are 3 ratio sets for the 2430 and X ratio sets for 2420. | ||
| 67 | * | ||
| 68 | * 2430 differs from 2420 in that there are no more phase synchronizers used. | ||
| 69 | * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs | ||
| 70 | * 2430 (iva2.1, NOdsp, mdm) | ||
| 71 | */ | ||
| 72 | |||
| 73 | /* Core fields for cm_clksel, not ratio governed */ | ||
| 74 | #define RX_CLKSEL_DSS1 (0x10 << 8) | ||
| 75 | #define RX_CLKSEL_DSS2 (0x0 << 13) | ||
| 76 | #define RX_CLKSEL_SSI (0x5 << 20) | ||
| 77 | |||
| 78 | /*------------------------------------------------------------------------- | ||
| 79 | * Voltage/DPLL ratios | ||
| 80 | *-------------------------------------------------------------------------*/ | ||
| 81 | |||
| 82 | /* 2430 Ratio's, 2430-Ratio Config 1 */ | ||
| 83 | #define R1_CLKSEL_L3 (4 << 0) | ||
| 84 | #define R1_CLKSEL_L4 (2 << 5) | ||
| 85 | #define R1_CLKSEL_USB (4 << 25) | ||
| 86 | #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \ | ||
| 87 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
| 88 | R1_CLKSEL_L4 | R1_CLKSEL_L3 | ||
| 89 | #define R1_CLKSEL_MPU (2 << 0) | ||
| 90 | #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU | ||
| 91 | #define R1_CLKSEL_DSP (2 << 0) | ||
| 92 | #define R1_CLKSEL_DSP_IF (2 << 5) | ||
| 93 | #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF | ||
| 94 | #define R1_CLKSEL_GFX (2 << 0) | ||
| 95 | #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX | ||
| 96 | #define R1_CLKSEL_MDM (4 << 0) | ||
| 97 | #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM | ||
| 98 | |||
| 99 | /* 2430-Ratio Config 2 */ | ||
| 100 | #define R2_CLKSEL_L3 (6 << 0) | ||
| 101 | #define R2_CLKSEL_L4 (2 << 5) | ||
| 102 | #define R2_CLKSEL_USB (2 << 25) | ||
| 103 | #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \ | ||
| 104 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
| 105 | R2_CLKSEL_L4 | R2_CLKSEL_L3 | ||
| 106 | #define R2_CLKSEL_MPU (2 << 0) | ||
| 107 | #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU | ||
| 108 | #define R2_CLKSEL_DSP (2 << 0) | ||
| 109 | #define R2_CLKSEL_DSP_IF (3 << 5) | ||
| 110 | #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF | ||
| 111 | #define R2_CLKSEL_GFX (2 << 0) | ||
| 112 | #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX | ||
| 113 | #define R2_CLKSEL_MDM (6 << 0) | ||
| 114 | #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM | ||
| 115 | |||
| 116 | /* 2430-Ratio Bootm (BYPASS) */ | ||
| 117 | #define RB_CLKSEL_L3 (1 << 0) | ||
| 118 | #define RB_CLKSEL_L4 (1 << 5) | ||
| 119 | #define RB_CLKSEL_USB (1 << 25) | ||
| 120 | #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \ | ||
| 121 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
| 122 | RB_CLKSEL_L4 | RB_CLKSEL_L3 | ||
| 123 | #define RB_CLKSEL_MPU (1 << 0) | ||
| 124 | #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU | ||
| 125 | #define RB_CLKSEL_DSP (1 << 0) | ||
| 126 | #define RB_CLKSEL_DSP_IF (1 << 5) | ||
| 127 | #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF | ||
| 128 | #define RB_CLKSEL_GFX (1 << 0) | ||
| 129 | #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX | ||
| 130 | #define RB_CLKSEL_MDM (1 << 0) | ||
| 131 | #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM | ||
| 132 | |||
| 133 | /* 2420 Ratio Equivalents */ | ||
| 134 | #define RXX_CLKSEL_VLYNQ (0x12 << 15) | ||
| 135 | #define RXX_CLKSEL_SSI (0x8 << 20) | ||
| 136 | |||
| 137 | /* 2420-PRCM III 532MHz core */ | ||
| 138 | #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */ | ||
| 139 | #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */ | ||
| 140 | #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */ | ||
| 141 | #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \ | ||
| 142 | RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ | ||
| 143 | RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \ | ||
| 144 | RIII_CLKSEL_L3 | ||
| 145 | #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */ | ||
| 146 | #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU | ||
| 147 | #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */ | ||
| 148 | #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */ | ||
| 149 | #define RIII_SYNC_DSP (1 << 7) /* Enable sync */ | ||
| 150 | #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */ | ||
| 151 | #define RIII_SYNC_IVA (1 << 13) /* Enable sync */ | ||
| 152 | #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \ | ||
| 153 | RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \ | ||
| 154 | RIII_CLKSEL_DSP | ||
| 155 | #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */ | ||
| 156 | #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX | ||
| 157 | |||
| 158 | /* 2420-PRCM II 600MHz core */ | ||
| 159 | #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */ | ||
| 160 | #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */ | ||
| 161 | #define RII_CLKSEL_USB (2 << 25) /* 50MHz */ | ||
| 162 | #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \ | ||
| 163 | RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ | ||
| 164 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
| 165 | RII_CLKSEL_L4 | RII_CLKSEL_L3 | ||
| 166 | #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */ | ||
| 167 | #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU | ||
| 168 | #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ | ||
| 169 | #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ | ||
| 170 | #define RII_SYNC_DSP (0 << 7) /* Bypass sync */ | ||
| 171 | #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */ | ||
| 172 | #define RII_SYNC_IVA (0 << 13) /* Bypass sync */ | ||
| 173 | #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \ | ||
| 174 | RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ | ||
| 175 | RII_CLKSEL_DSP | ||
| 176 | #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ | ||
| 177 | #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX | ||
| 178 | |||
| 179 | /* 2420-PRCM I 660MHz core */ | ||
| 180 | #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */ | ||
| 181 | #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */ | ||
| 182 | #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */ | ||
| 183 | #define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \ | ||
| 184 | RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ | ||
| 185 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ | ||
| 186 | RI_CLKSEL_L4 | RI_CLKSEL_L3 | ||
| 187 | #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */ | ||
| 188 | #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU | ||
| 189 | #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */ | ||
| 190 | #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */ | ||
| 191 | #define RI_SYNC_DSP (1 << 7) /* Activate sync */ | ||
| 192 | #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */ | ||
| 193 | #define RI_SYNC_IVA (0 << 13) /* Bypass sync */ | ||
| 194 | #define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \ | ||
| 195 | RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \ | ||
| 196 | RI_CLKSEL_DSP | ||
| 197 | #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */ | ||
| 198 | #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX | ||
| 199 | |||
| 200 | /* 2420-PRCM VII (boot) */ | ||
| 201 | #define RVII_CLKSEL_L3 (1 << 0) | ||
| 202 | #define RVII_CLKSEL_L4 (1 << 5) | ||
| 203 | #define RVII_CLKSEL_DSS1 (1 << 8) | ||
| 204 | #define RVII_CLKSEL_DSS2 (0 << 13) | ||
| 205 | #define RVII_CLKSEL_VLYNQ (1 << 15) | ||
| 206 | #define RVII_CLKSEL_SSI (1 << 20) | ||
| 207 | #define RVII_CLKSEL_USB (1 << 25) | ||
| 208 | |||
| 209 | #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \ | ||
| 210 | RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \ | ||
| 211 | RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3 | ||
| 212 | |||
| 213 | #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */ | ||
| 214 | #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU | ||
| 215 | |||
| 216 | #define RVII_CLKSEL_DSP (1 << 0) | ||
| 217 | #define RVII_CLKSEL_DSP_IF (1 << 5) | ||
| 218 | #define RVII_SYNC_DSP (0 << 7) | ||
| 219 | #define RVII_CLKSEL_IVA (1 << 8) | ||
| 220 | #define RVII_SYNC_IVA (0 << 13) | ||
| 221 | #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \ | ||
| 222 | RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP | ||
| 223 | |||
| 224 | #define RVII_CLKSEL_GFX (1 << 0) | ||
| 225 | #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX | ||
| 226 | |||
| 227 | /*------------------------------------------------------------------------- | ||
| 228 | * 2430 Target modes: Along with each configuration the CPU has several | ||
| 229 | * modes which goes along with them. Modes mainly are the addition of | ||
| 230 | * describe DPLL combinations to go along with a ratio. | ||
| 231 | *-------------------------------------------------------------------------*/ | ||
| 232 | |||
| 233 | /* Hardware governed */ | ||
| 234 | #define MX_48M_SRC (0 << 3) | ||
| 235 | #define MX_54M_SRC (0 << 5) | ||
| 236 | #define MX_APLLS_CLIKIN_12 (3 << 23) | ||
| 237 | #define MX_APLLS_CLIKIN_13 (2 << 23) | ||
| 238 | #define MX_APLLS_CLIKIN_19_2 (0 << 23) | ||
| 239 | |||
| 240 | /* | ||
| 241 | * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed | ||
| 242 | * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz | ||
| 243 | */ | ||
| 244 | #define M5A_DPLL_MULT_12 (133 << 12) | ||
| 245 | #define M5A_DPLL_DIV_12 (5 << 8) | ||
| 246 | #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 247 | M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ | ||
| 248 | MX_APLLS_CLIKIN_12 | ||
| 249 | #define M5A_DPLL_MULT_13 (61 << 12) | ||
| 250 | #define M5A_DPLL_DIV_13 (2 << 8) | ||
| 251 | #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 252 | M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ | ||
| 253 | MX_APLLS_CLIKIN_13 | ||
| 254 | #define M5A_DPLL_MULT_19 (55 << 12) | ||
| 255 | #define M5A_DPLL_DIV_19 (3 << 8) | ||
| 256 | #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 257 | M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ | ||
| 258 | MX_APLLS_CLIKIN_19_2 | ||
| 259 | /* #5b (ratio1) target DPLL = 200*2 = 400MHz */ | ||
| 260 | #define M5B_DPLL_MULT_12 (50 << 12) | ||
| 261 | #define M5B_DPLL_DIV_12 (2 << 8) | ||
| 262 | #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 263 | M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \ | ||
| 264 | MX_APLLS_CLIKIN_12 | ||
| 265 | #define M5B_DPLL_MULT_13 (200 << 12) | ||
| 266 | #define M5B_DPLL_DIV_13 (12 << 8) | ||
| 267 | |||
| 268 | #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 269 | M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \ | ||
| 270 | MX_APLLS_CLIKIN_13 | ||
| 271 | #define M5B_DPLL_MULT_19 (125 << 12) | ||
| 272 | #define M5B_DPLL_DIV_19 (31 << 8) | ||
| 273 | #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 274 | M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ | ||
| 275 | MX_APLLS_CLIKIN_19_2 | ||
| 276 | /* | ||
| 277 | * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz | ||
| 278 | */ | ||
| 279 | #define M4_DPLL_MULT_12 (133 << 12) | ||
| 280 | #define M4_DPLL_DIV_12 (3 << 8) | ||
| 281 | #define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 282 | M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \ | ||
| 283 | MX_APLLS_CLIKIN_12 | ||
| 284 | |||
| 285 | #define M4_DPLL_MULT_13 (399 << 12) | ||
| 286 | #define M4_DPLL_DIV_13 (12 << 8) | ||
| 287 | #define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 288 | M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \ | ||
| 289 | MX_APLLS_CLIKIN_13 | ||
| 290 | |||
| 291 | #define M4_DPLL_MULT_19 (145 << 12) | ||
| 292 | #define M4_DPLL_DIV_19 (6 << 8) | ||
| 293 | #define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 294 | M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \ | ||
| 295 | MX_APLLS_CLIKIN_19_2 | ||
| 296 | |||
| 297 | /* | ||
| 298 | * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz | ||
| 299 | */ | ||
| 300 | #define M3_DPLL_MULT_12 (55 << 12) | ||
| 301 | #define M3_DPLL_DIV_12 (1 << 8) | ||
| 302 | #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 303 | M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ | ||
| 304 | MX_APLLS_CLIKIN_12 | ||
| 305 | #define M3_DPLL_MULT_13 (76 << 12) | ||
| 306 | #define M3_DPLL_DIV_13 (2 << 8) | ||
| 307 | #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 308 | M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ | ||
| 309 | MX_APLLS_CLIKIN_13 | ||
| 310 | #define M3_DPLL_MULT_19 (17 << 12) | ||
| 311 | #define M3_DPLL_DIV_19 (0 << 8) | ||
| 312 | #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 313 | M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ | ||
| 314 | MX_APLLS_CLIKIN_19_2 | ||
| 315 | |||
| 316 | /* | ||
| 317 | * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz | ||
| 318 | */ | ||
| 319 | #define M2_DPLL_MULT_12 (55 << 12) | ||
| 320 | #define M2_DPLL_DIV_12 (1 << 8) | ||
| 321 | #define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 322 | M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \ | ||
| 323 | MX_APLLS_CLIKIN_12 | ||
| 324 | |||
| 325 | /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, | ||
| 326 | * relock time issue */ | ||
| 327 | /* Core frequency changed from 330/165 to 329/164 MHz*/ | ||
| 328 | #define M2_DPLL_MULT_13 (76 << 12) | ||
| 329 | #define M2_DPLL_DIV_13 (2 << 8) | ||
| 330 | #define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 331 | M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \ | ||
| 332 | MX_APLLS_CLIKIN_13 | ||
| 333 | |||
| 334 | #define M2_DPLL_MULT_19 (17 << 12) | ||
| 335 | #define M2_DPLL_DIV_19 (0 << 8) | ||
| 336 | #define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 337 | M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \ | ||
| 338 | MX_APLLS_CLIKIN_19_2 | ||
| 339 | |||
| 340 | /* boot (boot) */ | ||
| 341 | #define MB_DPLL_MULT (1 << 12) | ||
| 342 | #define MB_DPLL_DIV (0 << 8) | ||
| 343 | #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ | ||
| 344 | MB_DPLL_MULT | MX_APLLS_CLIKIN_12 | ||
| 345 | |||
| 346 | #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ | ||
| 347 | MB_DPLL_MULT | MX_APLLS_CLIKIN_13 | ||
| 348 | |||
| 349 | #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ | ||
| 350 | MB_DPLL_MULT | MX_APLLS_CLIKIN_19 | ||
| 351 | |||
| 352 | /* | ||
| 353 | * 2430 - chassis (sedna) | ||
| 354 | * 165 (ratio1) same as above #2 | ||
| 355 | * 150 (ratio1) | ||
| 356 | * 133 (ratio2) same as above #4 | ||
| 357 | * 110 (ratio2) same as above #3 | ||
| 358 | * 104 (ratio2) | ||
| 359 | * boot (boot) | ||
| 360 | */ | ||
| 361 | |||
| 362 | /* PRCM I target DPLL = 2*330MHz = 660MHz */ | ||
| 363 | #define MI_DPLL_MULT_12 (55 << 12) | ||
| 364 | #define MI_DPLL_DIV_12 (1 << 8) | ||
| 365 | #define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 366 | MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \ | ||
| 367 | MX_APLLS_CLIKIN_12 | ||
| 368 | |||
| 369 | /* | ||
| 370 | * 2420 Equivalent - mode registers | ||
| 371 | * PRCM II , target DPLL = 2*300MHz = 600MHz | ||
| 372 | */ | ||
| 373 | #define MII_DPLL_MULT_12 (50 << 12) | ||
| 374 | #define MII_DPLL_DIV_12 (1 << 8) | ||
| 375 | #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 376 | MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \ | ||
| 377 | MX_APLLS_CLIKIN_12 | ||
| 378 | #define MII_DPLL_MULT_13 (300 << 12) | ||
| 379 | #define MII_DPLL_DIV_13 (12 << 8) | ||
| 380 | #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 381 | MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \ | ||
| 382 | MX_APLLS_CLIKIN_13 | ||
| 383 | |||
| 384 | /* PRCM III target DPLL = 2*266 = 532MHz*/ | ||
| 385 | #define MIII_DPLL_MULT_12 (133 << 12) | ||
| 386 | #define MIII_DPLL_DIV_12 (5 << 8) | ||
| 387 | #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 388 | MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \ | ||
| 389 | MX_APLLS_CLIKIN_12 | ||
| 390 | #define MIII_DPLL_MULT_13 (266 << 12) | ||
| 391 | #define MIII_DPLL_DIV_13 (12 << 8) | ||
| 392 | #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ | ||
| 393 | MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \ | ||
| 394 | MX_APLLS_CLIKIN_13 | ||
| 395 | |||
| 396 | /* PRCM VII (boot bypass) */ | ||
| 397 | #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL | ||
| 398 | #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL | ||
| 399 | |||
| 400 | /* High and low operation value */ | ||
| 401 | #define MX_CLKSEL2_PLL_2x_VAL (2 << 0) | ||
| 402 | #define MX_CLKSEL2_PLL_1x_VAL (1 << 0) | ||
| 403 | |||
| 404 | /* MPU speed defines */ | ||
| 405 | #define S12M 12000000 | ||
| 406 | #define S13M 13000000 | ||
| 407 | #define S19M 19200000 | ||
| 408 | #define S26M 26000000 | ||
| 409 | #define S100M 100000000 | ||
| 410 | #define S133M 133000000 | ||
| 411 | #define S150M 150000000 | ||
| 412 | #define S164M 164000000 | ||
| 413 | #define S165M 165000000 | ||
| 414 | #define S199M 199000000 | ||
| 415 | #define S200M 200000000 | ||
| 416 | #define S266M 266000000 | ||
| 417 | #define S300M 300000000 | ||
| 418 | #define S329M 329000000 | ||
| 419 | #define S330M 330000000 | ||
| 420 | #define S399M 399000000 | ||
| 421 | #define S400M 400000000 | ||
| 422 | #define S532M 532000000 | ||
| 423 | #define S600M 600000000 | ||
| 424 | #define S658M 658000000 | ||
| 425 | #define S660M 660000000 | ||
| 426 | #define S798M 798000000 | ||
| 427 | |||
| 428 | /*------------------------------------------------------------------------- | ||
| 429 | * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. | ||
| 430 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, | ||
| 431 | * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, | ||
| 432 | * CM_CLKSEL2_PLL, CM_CLKSEL_MDM | ||
| 433 | * | ||
| 434 | * Filling in table based on H4 boards and 2430-SDPs variants available. | ||
| 435 | * There are quite a few more rates combinations which could be defined. | ||
| 436 | * | ||
| 437 | * When multiple values are defined the start up will try and choose the | ||
| 438 | * fastest one. If a 'fast' value is defined, then automatically, the /2 | ||
| 439 | * one should be included as it can be used. Generally having more that | ||
| 440 | * one fast set does not make sense, as static timings need to be changed | ||
| 441 | * to change the set. The exception is the bypass setting which is | ||
| 442 | * availble for low power bypass. | ||
| 443 | * | ||
| 444 | * Note: This table needs to be sorted, fastest to slowest. | ||
| 445 | *-------------------------------------------------------------------------*/ | ||
| 446 | static struct prcm_config rate_table[] = { | ||
| 447 | /* PRCM I - FAST */ | ||
| 448 | {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ | ||
| 449 | RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL, | ||
| 450 | RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL, | ||
| 451 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz, | ||
| 452 | RATE_IN_242X}, | ||
| 453 | |||
| 454 | /* PRCM II - FAST */ | ||
| 455 | {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ | ||
| 456 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | ||
| 457 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, | ||
| 458 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, | ||
| 459 | RATE_IN_242X}, | ||
| 460 | |||
| 461 | {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ | ||
| 462 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | ||
| 463 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, | ||
| 464 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, | ||
| 465 | RATE_IN_242X}, | ||
| 466 | |||
| 467 | /* PRCM III - FAST */ | ||
| 468 | {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ | ||
| 469 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | ||
| 470 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, | ||
| 471 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, | ||
| 472 | RATE_IN_242X}, | ||
| 473 | |||
| 474 | {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ | ||
| 475 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | ||
| 476 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, | ||
| 477 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, | ||
| 478 | RATE_IN_242X}, | ||
| 479 | |||
| 480 | /* PRCM II - SLOW */ | ||
| 481 | {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ | ||
| 482 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | ||
| 483 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, | ||
| 484 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, | ||
| 485 | RATE_IN_242X}, | ||
| 486 | |||
| 487 | {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ | ||
| 488 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, | ||
| 489 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, | ||
| 490 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, | ||
| 491 | RATE_IN_242X}, | ||
| 492 | |||
| 493 | /* PRCM III - SLOW */ | ||
| 494 | {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ | ||
| 495 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | ||
| 496 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, | ||
| 497 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, | ||
| 498 | RATE_IN_242X}, | ||
| 499 | |||
| 500 | {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ | ||
| 501 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, | ||
| 502 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, | ||
| 503 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, | ||
| 504 | RATE_IN_242X}, | ||
| 505 | |||
| 506 | /* PRCM-VII (boot-bypass) */ | ||
| 507 | {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/ | ||
| 508 | RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, | ||
| 509 | RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL, | ||
| 510 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, | ||
| 511 | RATE_IN_242X}, | ||
| 512 | |||
| 513 | /* PRCM-VII (boot-bypass) */ | ||
| 514 | {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */ | ||
| 515 | RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, | ||
| 516 | RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL, | ||
| 517 | MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, | ||
| 518 | RATE_IN_242X}, | ||
| 519 | |||
| 520 | /* PRCM #4 - ratio2 (ES2.1) - FAST */ | ||
| 521 | {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */ | ||
| 522 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, | ||
| 523 | R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, | ||
| 524 | MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL, | ||
| 525 | SDRC_RFR_CTRL_133MHz, | ||
| 526 | RATE_IN_243X}, | ||
| 527 | |||
| 528 | /* PRCM #2 - ratio1 (ES2) - FAST */ | ||
| 529 | {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ | ||
| 530 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
| 531 | R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, | ||
| 532 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
| 533 | SDRC_RFR_CTRL_165MHz, | ||
| 534 | RATE_IN_243X}, | ||
| 535 | |||
| 536 | /* PRCM #5a - ratio1 - FAST */ | ||
| 537 | {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ | ||
| 538 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
| 539 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, | ||
| 540 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
| 541 | SDRC_RFR_CTRL_133MHz, | ||
| 542 | RATE_IN_243X}, | ||
| 543 | |||
| 544 | /* PRCM #5b - ratio1 - FAST */ | ||
| 545 | {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ | ||
| 546 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
| 547 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, | ||
| 548 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
| 549 | SDRC_RFR_CTRL_100MHz, | ||
| 550 | RATE_IN_243X}, | ||
| 551 | |||
| 552 | /* PRCM #4 - ratio1 (ES2.1) - SLOW */ | ||
| 553 | {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ | ||
| 554 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, | ||
| 555 | R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, | ||
| 556 | MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL, | ||
| 557 | SDRC_RFR_CTRL_133MHz, | ||
| 558 | RATE_IN_243X}, | ||
| 559 | |||
| 560 | /* PRCM #2 - ratio1 (ES2) - SLOW */ | ||
| 561 | {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ | ||
| 562 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
| 563 | R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, | ||
| 564 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
| 565 | SDRC_RFR_CTRL_165MHz, | ||
| 566 | RATE_IN_243X}, | ||
| 567 | |||
| 568 | /* PRCM #5a - ratio1 - SLOW */ | ||
| 569 | {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ | ||
| 570 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
| 571 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, | ||
| 572 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
| 573 | SDRC_RFR_CTRL_133MHz, | ||
| 574 | RATE_IN_243X}, | ||
| 575 | |||
| 576 | /* PRCM #5b - ratio1 - SLOW*/ | ||
| 577 | {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */ | ||
| 578 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, | ||
| 579 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, | ||
| 580 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, | ||
| 581 | SDRC_RFR_CTRL_100MHz, | ||
| 582 | RATE_IN_243X}, | ||
| 583 | |||
| 584 | /* PRCM-boot/bypass */ | ||
| 585 | {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */ | ||
| 586 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, | ||
| 587 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, | ||
| 588 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, | ||
| 589 | SDRC_RFR_CTRL_BYPASS, | ||
| 590 | RATE_IN_243X}, | ||
| 591 | |||
| 592 | /* PRCM-boot/bypass */ | ||
| 593 | {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */ | ||
| 594 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, | ||
| 595 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, | ||
| 596 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, | ||
| 597 | SDRC_RFR_CTRL_BYPASS, | ||
| 598 | RATE_IN_243X}, | ||
| 599 | |||
| 600 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | ||
| 601 | }; | ||
| 602 | |||
| 603 | /*------------------------------------------------------------------------- | ||
| 604 | * 24xx clock tree. | ||
| 605 | * | ||
| 606 | * NOTE:In many cases here we are assigning a 'default' parent. In many | ||
| 607 | * cases the parent is selectable. The get/set parent calls will also | ||
| 608 | * switch sources. | ||
| 609 | * | ||
| 610 | * Many some clocks say always_enabled, but they can be auto idled for | ||
| 611 | * power savings. They will always be available upon clock request. | ||
| 612 | * | ||
| 613 | * Several sources are given initial rates which may be wrong, this will | ||
| 614 | * be fixed up in the init func. | ||
| 615 | * | ||
| 616 | * Things are broadly separated below by clock domains. It is | ||
| 617 | * noteworthy that most periferals have dependencies on multiple clock | ||
| 618 | * domains. Many get their interface clocks from the L4 domain, but get | ||
| 619 | * functional clocks from fixed sources or other core domain derived | ||
| 620 | * clocks. | ||
| 621 | *-------------------------------------------------------------------------*/ | ||
| 622 | |||
| 623 | /* Base external input clocks */ | ||
| 624 | static struct clk func_32k_ck = { | ||
| 625 | .name = "func_32k_ck", | ||
| 626 | .rate = 32000, | ||
| 627 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 628 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, | ||
| 629 | .recalc = &propagate_rate, | ||
| 630 | }; | ||
| 631 | |||
| 632 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ | ||
| 633 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ | ||
| 634 | .name = "osc_ck", | ||
| 635 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 636 | RATE_PROPAGATES, | ||
| 637 | .enable = &omap2_enable_osc_ck, | ||
| 638 | .disable = &omap2_disable_osc_ck, | ||
| 639 | .recalc = &omap2_osc_clk_recalc, | ||
| 640 | }; | ||
| 641 | |||
| 642 | /* With out modem likely 12MHz, with modem likely 13MHz */ | ||
| 643 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ | ||
| 644 | .name = "sys_ck", /* ~ ref_clk also */ | ||
| 645 | .parent = &osc_ck, | ||
| 646 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 647 | ALWAYS_ENABLED | RATE_PROPAGATES, | ||
| 648 | .recalc = &omap2_sys_clk_recalc, | ||
| 649 | }; | ||
| 650 | |||
| 651 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ | ||
| 652 | .name = "alt_ck", | ||
| 653 | .rate = 54000000, | ||
| 654 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 655 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, | ||
| 656 | .recalc = &propagate_rate, | ||
| 657 | }; | ||
| 658 | |||
| 659 | /* | ||
| 660 | * Analog domain root source clocks | ||
| 661 | */ | ||
| 662 | |||
| 663 | /* dpll_ck, is broken out in to special cases through clksel */ | ||
| 664 | /* REVISIT: Rate changes on dpll_ck trigger a full set change. ... | ||
| 665 | * deal with this | ||
| 666 | */ | ||
| 667 | |||
| 668 | static const struct dpll_data dpll_dd = { | ||
| 669 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
| 670 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, | ||
| 671 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, | ||
| 672 | }; | ||
| 673 | |||
| 674 | static struct clk dpll_ck = { | ||
| 675 | .name = "dpll_ck", | ||
| 676 | .parent = &sys_ck, /* Can be func_32k also */ | ||
| 677 | .dpll_data = &dpll_dd, | ||
| 678 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 679 | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 680 | .recalc = &omap2_dpll_recalc, | ||
| 681 | .set_rate = &omap2_reprogram_dpll, | ||
| 682 | }; | ||
| 683 | |||
| 684 | static struct clk apll96_ck = { | ||
| 685 | .name = "apll96_ck", | ||
| 686 | .parent = &sys_ck, | ||
| 687 | .rate = 96000000, | ||
| 688 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 689 | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, | ||
| 690 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
| 691 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, | ||
| 692 | .enable = &omap2_clk_fixed_enable, | ||
| 693 | .disable = &omap2_clk_fixed_disable, | ||
| 694 | .recalc = &propagate_rate, | ||
| 695 | }; | ||
| 696 | |||
| 697 | static struct clk apll54_ck = { | ||
| 698 | .name = "apll54_ck", | ||
| 699 | .parent = &sys_ck, | ||
| 700 | .rate = 54000000, | ||
| 701 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 702 | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, | ||
| 703 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
| 704 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, | ||
| 705 | .enable = &omap2_clk_fixed_enable, | ||
| 706 | .disable = &omap2_clk_fixed_disable, | ||
| 707 | .recalc = &propagate_rate, | ||
| 708 | }; | ||
| 709 | |||
| 710 | /* | ||
| 711 | * PRCM digital base sources | ||
| 712 | */ | ||
| 713 | |||
| 714 | /* func_54m_ck */ | ||
| 715 | |||
| 716 | static const struct clksel_rate func_54m_apll54_rates[] = { | ||
| 717 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 718 | { .div = 0 }, | ||
| 719 | }; | ||
| 720 | |||
| 721 | static const struct clksel_rate func_54m_alt_rates[] = { | ||
| 722 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 723 | { .div = 0 }, | ||
| 724 | }; | ||
| 725 | |||
| 726 | static const struct clksel func_54m_clksel[] = { | ||
| 727 | { .parent = &apll54_ck, .rates = func_54m_apll54_rates, }, | ||
| 728 | { .parent = &alt_ck, .rates = func_54m_alt_rates, }, | ||
| 729 | { .parent = NULL }, | ||
| 730 | }; | ||
| 731 | |||
| 732 | static struct clk func_54m_ck = { | ||
| 733 | .name = "func_54m_ck", | ||
| 734 | .parent = &apll54_ck, /* can also be alt_clk */ | ||
| 735 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 736 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, | ||
| 737 | .init = &omap2_init_clksel_parent, | ||
| 738 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
| 739 | .clksel_mask = OMAP24XX_54M_SOURCE, | ||
| 740 | .clksel = func_54m_clksel, | ||
| 741 | .recalc = &omap2_clksel_recalc, | ||
| 742 | }; | ||
| 743 | |||
| 744 | static struct clk core_ck = { | ||
| 745 | .name = "core_ck", | ||
| 746 | .parent = &dpll_ck, /* can also be 32k */ | ||
| 747 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 748 | ALWAYS_ENABLED | RATE_PROPAGATES, | ||
| 749 | .recalc = &followparent_recalc, | ||
| 750 | }; | ||
| 751 | |||
| 752 | /* func_96m_ck */ | ||
| 753 | static const struct clksel_rate func_96m_apll96_rates[] = { | ||
| 754 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 755 | { .div = 0 }, | ||
| 756 | }; | ||
| 757 | |||
| 758 | static const struct clksel_rate func_96m_alt_rates[] = { | ||
| 759 | { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE }, | ||
| 760 | { .div = 0 }, | ||
| 761 | }; | ||
| 762 | |||
| 763 | static const struct clksel func_96m_clksel[] = { | ||
| 764 | { .parent = &apll96_ck, .rates = func_96m_apll96_rates }, | ||
| 765 | { .parent = &alt_ck, .rates = func_96m_alt_rates }, | ||
| 766 | { .parent = NULL } | ||
| 767 | }; | ||
| 768 | |||
| 769 | /* The parent of this clock is not selectable on 2420. */ | ||
| 770 | static struct clk func_96m_ck = { | ||
| 771 | .name = "func_96m_ck", | ||
| 772 | .parent = &apll96_ck, | ||
| 773 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 774 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, | ||
| 775 | .init = &omap2_init_clksel_parent, | ||
| 776 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
| 777 | .clksel_mask = OMAP2430_96M_SOURCE, | ||
| 778 | .clksel = func_96m_clksel, | ||
| 779 | .recalc = &omap2_clksel_recalc, | ||
| 780 | .round_rate = &omap2_clksel_round_rate, | ||
| 781 | .set_rate = &omap2_clksel_set_rate | ||
| 782 | }; | ||
| 783 | |||
| 784 | /* func_48m_ck */ | ||
| 785 | |||
| 786 | static const struct clksel_rate func_48m_apll96_rates[] = { | ||
| 787 | { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 788 | { .div = 0 }, | ||
| 789 | }; | ||
| 790 | |||
| 791 | static const struct clksel_rate func_48m_alt_rates[] = { | ||
| 792 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 793 | { .div = 0 }, | ||
| 794 | }; | ||
| 795 | |||
| 796 | static const struct clksel func_48m_clksel[] = { | ||
| 797 | { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, | ||
| 798 | { .parent = &alt_ck, .rates = func_48m_alt_rates }, | ||
| 799 | { .parent = NULL } | ||
| 800 | }; | ||
| 801 | |||
| 802 | static struct clk func_48m_ck = { | ||
| 803 | .name = "func_48m_ck", | ||
| 804 | .parent = &apll96_ck, /* 96M or Alt */ | ||
| 805 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 806 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, | ||
| 807 | .init = &omap2_init_clksel_parent, | ||
| 808 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
| 809 | .clksel_mask = OMAP24XX_48M_SOURCE, | ||
| 810 | .clksel = func_48m_clksel, | ||
| 811 | .recalc = &omap2_clksel_recalc, | ||
| 812 | .round_rate = &omap2_clksel_round_rate, | ||
| 813 | .set_rate = &omap2_clksel_set_rate | ||
| 814 | }; | ||
| 815 | |||
| 816 | static struct clk func_12m_ck = { | ||
| 817 | .name = "func_12m_ck", | ||
| 818 | .parent = &func_48m_ck, | ||
| 819 | .fixed_div = 4, | ||
| 820 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 821 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, | ||
| 822 | .recalc = &omap2_fixed_divisor_recalc, | ||
| 823 | }; | ||
| 824 | |||
| 825 | /* Secure timer, only available in secure mode */ | ||
| 826 | static struct clk wdt1_osc_ck = { | ||
| 827 | .name = "ck_wdt1_osc", | ||
| 828 | .parent = &osc_ck, | ||
| 829 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 830 | .recalc = &followparent_recalc, | ||
| 831 | }; | ||
| 832 | |||
| 833 | /* | ||
| 834 | * The common_clkout* clksel_rate structs are common to | ||
| 835 | * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src. | ||
| 836 | * sys_clkout2_* are 2420-only, so the | ||
| 837 | * clksel_rate flags fields are inaccurate for those clocks. This is | ||
| 838 | * harmless since access to those clocks are gated by the struct clk | ||
| 839 | * flags fields, which mark them as 2420-only. | ||
| 840 | */ | ||
| 841 | static const struct clksel_rate common_clkout_src_core_rates[] = { | ||
| 842 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 843 | { .div = 0 } | ||
| 844 | }; | ||
| 845 | |||
| 846 | static const struct clksel_rate common_clkout_src_sys_rates[] = { | ||
| 847 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 848 | { .div = 0 } | ||
| 849 | }; | ||
| 850 | |||
| 851 | static const struct clksel_rate common_clkout_src_96m_rates[] = { | ||
| 852 | { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 853 | { .div = 0 } | ||
| 854 | }; | ||
| 855 | |||
| 856 | static const struct clksel_rate common_clkout_src_54m_rates[] = { | ||
| 857 | { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 858 | { .div = 0 } | ||
| 859 | }; | ||
| 860 | |||
| 861 | static const struct clksel common_clkout_src_clksel[] = { | ||
| 862 | { .parent = &core_ck, .rates = common_clkout_src_core_rates }, | ||
| 863 | { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, | ||
| 864 | { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, | ||
| 865 | { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, | ||
| 866 | { .parent = NULL } | ||
| 867 | }; | ||
| 868 | |||
| 869 | static struct clk sys_clkout_src = { | ||
| 870 | .name = "sys_clkout_src", | ||
| 871 | .parent = &func_54m_ck, | ||
| 872 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 873 | RATE_PROPAGATES, | ||
| 874 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | ||
| 875 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, | ||
| 876 | .init = &omap2_init_clksel_parent, | ||
| 877 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | ||
| 878 | .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, | ||
| 879 | .clksel = common_clkout_src_clksel, | ||
| 880 | .recalc = &omap2_clksel_recalc, | ||
| 881 | .round_rate = &omap2_clksel_round_rate, | ||
| 882 | .set_rate = &omap2_clksel_set_rate | ||
| 883 | }; | ||
| 884 | |||
| 885 | static const struct clksel_rate common_clkout_rates[] = { | ||
| 886 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 887 | { .div = 2, .val = 1, .flags = RATE_IN_24XX }, | ||
| 888 | { .div = 4, .val = 2, .flags = RATE_IN_24XX }, | ||
| 889 | { .div = 8, .val = 3, .flags = RATE_IN_24XX }, | ||
| 890 | { .div = 16, .val = 4, .flags = RATE_IN_24XX }, | ||
| 891 | { .div = 0 }, | ||
| 892 | }; | ||
| 893 | |||
| 894 | static const struct clksel sys_clkout_clksel[] = { | ||
| 895 | { .parent = &sys_clkout_src, .rates = common_clkout_rates }, | ||
| 896 | { .parent = NULL } | ||
| 897 | }; | ||
| 898 | |||
| 899 | static struct clk sys_clkout = { | ||
| 900 | .name = "sys_clkout", | ||
| 901 | .parent = &sys_clkout_src, | ||
| 902 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 903 | PARENT_CONTROLS_CLOCK, | ||
| 904 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | ||
| 905 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, | ||
| 906 | .clksel = sys_clkout_clksel, | ||
| 907 | .recalc = &omap2_clksel_recalc, | ||
| 908 | .round_rate = &omap2_clksel_round_rate, | ||
| 909 | .set_rate = &omap2_clksel_set_rate | ||
| 910 | }; | ||
| 911 | |||
| 912 | /* In 2430, new in 2420 ES2 */ | ||
| 913 | static struct clk sys_clkout2_src = { | ||
| 914 | .name = "sys_clkout2_src", | ||
| 915 | .parent = &func_54m_ck, | ||
| 916 | .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES, | ||
| 917 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | ||
| 918 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, | ||
| 919 | .init = &omap2_init_clksel_parent, | ||
| 920 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | ||
| 921 | .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK, | ||
| 922 | .clksel = common_clkout_src_clksel, | ||
| 923 | .recalc = &omap2_clksel_recalc, | ||
| 924 | .round_rate = &omap2_clksel_round_rate, | ||
| 925 | .set_rate = &omap2_clksel_set_rate | ||
| 926 | }; | ||
| 927 | |||
| 928 | static const struct clksel sys_clkout2_clksel[] = { | ||
| 929 | { .parent = &sys_clkout2_src, .rates = common_clkout_rates }, | ||
| 930 | { .parent = NULL } | ||
| 931 | }; | ||
| 932 | |||
| 933 | /* In 2430, new in 2420 ES2 */ | ||
| 934 | static struct clk sys_clkout2 = { | ||
| 935 | .name = "sys_clkout2", | ||
| 936 | .parent = &sys_clkout2_src, | ||
| 937 | .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK, | ||
| 938 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | ||
| 939 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, | ||
| 940 | .clksel = sys_clkout2_clksel, | ||
| 941 | .recalc = &omap2_clksel_recalc, | ||
| 942 | .round_rate = &omap2_clksel_round_rate, | ||
| 943 | .set_rate = &omap2_clksel_set_rate | ||
| 944 | }; | ||
| 945 | |||
| 946 | static struct clk emul_ck = { | ||
| 947 | .name = "emul_ck", | ||
| 948 | .parent = &func_54m_ck, | ||
| 949 | .flags = CLOCK_IN_OMAP242X, | ||
| 950 | .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, | ||
| 951 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, | ||
| 952 | .recalc = &followparent_recalc, | ||
| 953 | |||
| 954 | }; | ||
| 955 | |||
| 956 | /* | ||
| 957 | * MPU clock domain | ||
| 958 | * Clocks: | ||
| 959 | * MPU_FCLK, MPU_ICLK | ||
| 960 | * INT_M_FCLK, INT_M_I_CLK | ||
| 961 | * | ||
| 962 | * - Individual clocks are hardware managed. | ||
| 963 | * - Base divider comes from: CM_CLKSEL_MPU | ||
| 964 | * | ||
| 965 | */ | ||
| 966 | static const struct clksel_rate mpu_core_rates[] = { | ||
| 967 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 968 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
| 969 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, | ||
| 970 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
| 971 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
| 972 | { .div = 0 }, | ||
| 973 | }; | ||
| 974 | |||
| 975 | static const struct clksel mpu_clksel[] = { | ||
| 976 | { .parent = &core_ck, .rates = mpu_core_rates }, | ||
| 977 | { .parent = NULL } | ||
| 978 | }; | ||
| 979 | |||
| 980 | static struct clk mpu_ck = { /* Control cpu */ | ||
| 981 | .name = "mpu_ck", | ||
| 982 | .parent = &core_ck, | ||
| 983 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 984 | ALWAYS_ENABLED | DELAYED_APP | | ||
| 985 | CONFIG_PARTICIPANT | RATE_PROPAGATES, | ||
| 986 | .init = &omap2_init_clksel_parent, | ||
| 987 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | ||
| 988 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, | ||
| 989 | .clksel = mpu_clksel, | ||
| 990 | .recalc = &omap2_clksel_recalc, | ||
| 991 | .round_rate = &omap2_clksel_round_rate, | ||
| 992 | .set_rate = &omap2_clksel_set_rate | ||
| 993 | }; | ||
| 994 | |||
| 995 | /* | ||
| 996 | * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain | ||
| 997 | * Clocks: | ||
| 998 | * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK | ||
| 999 | * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP | ||
| 1000 | * | ||
| 1001 | * Won't be too specific here. The core clock comes into this block | ||
| 1002 | * it is divided then tee'ed. One branch goes directly to xyz enable | ||
| 1003 | * controls. The other branch gets further divided by 2 then possibly | ||
| 1004 | * routed into a synchronizer and out of clocks abc. | ||
| 1005 | */ | ||
| 1006 | static const struct clksel_rate dsp_fck_core_rates[] = { | ||
| 1007 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 1008 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
| 1009 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | ||
| 1010 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | ||
| 1011 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
| 1012 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
| 1013 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | ||
| 1014 | { .div = 0 }, | ||
| 1015 | }; | ||
| 1016 | |||
| 1017 | static const struct clksel dsp_fck_clksel[] = { | ||
| 1018 | { .parent = &core_ck, .rates = dsp_fck_core_rates }, | ||
| 1019 | { .parent = NULL } | ||
| 1020 | }; | ||
| 1021 | |||
| 1022 | static struct clk dsp_fck = { | ||
| 1023 | .name = "dsp_fck", | ||
| 1024 | .parent = &core_ck, | ||
| 1025 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | | ||
| 1026 | CONFIG_PARTICIPANT | RATE_PROPAGATES, | ||
| 1027 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | ||
| 1028 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | ||
| 1029 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | ||
| 1030 | .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, | ||
| 1031 | .clksel = dsp_fck_clksel, | ||
| 1032 | .recalc = &omap2_clksel_recalc, | ||
| 1033 | .round_rate = &omap2_clksel_round_rate, | ||
| 1034 | .set_rate = &omap2_clksel_set_rate | ||
| 1035 | }; | ||
| 1036 | |||
| 1037 | /* DSP interface clock */ | ||
| 1038 | static const struct clksel_rate dsp_irate_ick_rates[] = { | ||
| 1039 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 1040 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
| 1041 | { .div = 3, .val = 3, .flags = RATE_IN_243X }, | ||
| 1042 | { .div = 0 }, | ||
| 1043 | }; | ||
| 1044 | |||
| 1045 | static const struct clksel dsp_irate_ick_clksel[] = { | ||
| 1046 | { .parent = &dsp_fck, .rates = dsp_irate_ick_rates }, | ||
| 1047 | { .parent = NULL } | ||
| 1048 | }; | ||
| 1049 | |||
| 1050 | /* | ||
| 1051 | * This clock does not exist as such in the TRM, but is added to | ||
| 1052 | * separate source selection from XXX | ||
| 1053 | */ | ||
| 1054 | static struct clk dsp_irate_ick = { | ||
| 1055 | .name = "dsp_irate_ick", | ||
| 1056 | .parent = &dsp_fck, | ||
| 1057 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | | ||
| 1058 | CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK, | ||
| 1059 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | ||
| 1060 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, | ||
| 1061 | .clksel = dsp_irate_ick_clksel, | ||
| 1062 | .recalc = &omap2_clksel_recalc, | ||
| 1063 | .round_rate = &omap2_clksel_round_rate, | ||
| 1064 | .set_rate = &omap2_clksel_set_rate | ||
| 1065 | }; | ||
| 1066 | |||
| 1067 | /* 2420 only */ | ||
| 1068 | static struct clk dsp_ick = { | ||
| 1069 | .name = "dsp_ick", /* apparently ipi and isp */ | ||
| 1070 | .parent = &dsp_irate_ick, | ||
| 1071 | .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 1072 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), | ||
| 1073 | .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ | ||
| 1074 | }; | ||
| 1075 | |||
| 1076 | /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ | ||
| 1077 | static struct clk iva2_1_ick = { | ||
| 1078 | .name = "iva2_1_ick", | ||
| 1079 | .parent = &dsp_irate_ick, | ||
| 1080 | .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 1081 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | ||
| 1082 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | ||
| 1083 | }; | ||
| 1084 | |||
| 1085 | static struct clk iva1_ifck = { | ||
| 1086 | .name = "iva1_ifck", | ||
| 1087 | .parent = &core_ck, | ||
| 1088 | .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | | ||
| 1089 | RATE_PROPAGATES | DELAYED_APP, | ||
| 1090 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | ||
| 1091 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, | ||
| 1092 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | ||
| 1093 | .clksel_mask = OMAP2420_CLKSEL_IVA_MASK, | ||
| 1094 | .clksel = dsp_fck_clksel, | ||
| 1095 | .recalc = &omap2_clksel_recalc, | ||
| 1096 | .round_rate = &omap2_clksel_round_rate, | ||
| 1097 | .set_rate = &omap2_clksel_set_rate | ||
| 1098 | }; | ||
| 1099 | |||
| 1100 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ | ||
| 1101 | static struct clk iva1_mpu_int_ifck = { | ||
| 1102 | .name = "iva1_mpu_int_ifck", | ||
| 1103 | .parent = &iva1_ifck, | ||
| 1104 | .flags = CLOCK_IN_OMAP242X, | ||
| 1105 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | ||
| 1106 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, | ||
| 1107 | .fixed_div = 2, | ||
| 1108 | .recalc = &omap2_fixed_divisor_recalc, | ||
| 1109 | }; | ||
| 1110 | |||
| 1111 | /* | ||
| 1112 | * L3 clock domain | ||
| 1113 | * L3 clocks are used for both interface and functional clocks to | ||
| 1114 | * multiple entities. Some of these clocks are completely managed | ||
| 1115 | * by hardware, and some others allow software control. Hardware | ||
| 1116 | * managed ones general are based on directly CLK_REQ signals and | ||
| 1117 | * various auto idle settings. The functional spec sets many of these | ||
| 1118 | * as 'tie-high' for their enables. | ||
| 1119 | * | ||
| 1120 | * I-CLOCKS: | ||
| 1121 | * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA | ||
| 1122 | * CAM, HS-USB. | ||
| 1123 | * F-CLOCK | ||
| 1124 | * SSI. | ||
| 1125 | * | ||
| 1126 | * GPMC memories and SDRC have timing and clock sensitive registers which | ||
| 1127 | * may very well need notification when the clock changes. Currently for low | ||
| 1128 | * operating points, these are taken care of in sleep.S. | ||
| 1129 | */ | ||
| 1130 | static const struct clksel_rate core_l3_core_rates[] = { | ||
| 1131 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | ||
| 1132 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, | ||
| 1133 | { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 1134 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, | ||
| 1135 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
| 1136 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | ||
| 1137 | { .div = 16, .val = 16, .flags = RATE_IN_242X }, | ||
| 1138 | { .div = 0 } | ||
| 1139 | }; | ||
| 1140 | |||
| 1141 | static const struct clksel core_l3_clksel[] = { | ||
| 1142 | { .parent = &core_ck, .rates = core_l3_core_rates }, | ||
| 1143 | { .parent = NULL } | ||
| 1144 | }; | ||
| 1145 | |||
| 1146 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ | ||
| 1147 | .name = "core_l3_ck", | ||
| 1148 | .parent = &core_ck, | ||
| 1149 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1150 | ALWAYS_ENABLED | DELAYED_APP | | ||
| 1151 | CONFIG_PARTICIPANT | RATE_PROPAGATES, | ||
| 1152 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
| 1153 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, | ||
| 1154 | .clksel = core_l3_clksel, | ||
| 1155 | .recalc = &omap2_clksel_recalc, | ||
| 1156 | .round_rate = &omap2_clksel_round_rate, | ||
| 1157 | .set_rate = &omap2_clksel_set_rate | ||
| 1158 | }; | ||
| 1159 | |||
| 1160 | /* usb_l4_ick */ | ||
| 1161 | static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { | ||
| 1162 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | ||
| 1163 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 1164 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | ||
| 1165 | { .div = 0 } | ||
| 1166 | }; | ||
| 1167 | |||
| 1168 | static const struct clksel usb_l4_ick_clksel[] = { | ||
| 1169 | { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, | ||
| 1170 | { .parent = NULL }, | ||
| 1171 | }; | ||
| 1172 | |||
| 1173 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ | ||
| 1174 | .name = "usb_l4_ick", | ||
| 1175 | .parent = &core_l3_ck, | ||
| 1176 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1177 | DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 1178 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 1179 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | ||
| 1180 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
| 1181 | .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, | ||
| 1182 | .clksel = usb_l4_ick_clksel, | ||
| 1183 | .recalc = &omap2_clksel_recalc, | ||
| 1184 | .round_rate = &omap2_clksel_round_rate, | ||
| 1185 | .set_rate = &omap2_clksel_set_rate | ||
| 1186 | }; | ||
| 1187 | |||
| 1188 | /* | ||
| 1189 | * SSI is in L3 management domain, its direct parent is core not l3, | ||
| 1190 | * many core power domain entities are grouped into the L3 clock | ||
| 1191 | * domain. | ||
| 1192 | * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK | ||
| 1193 | * | ||
| 1194 | * ssr = core/1/2/3/4/5, sst = 1/2 ssr. | ||
| 1195 | */ | ||
| 1196 | static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { | ||
| 1197 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | ||
| 1198 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 1199 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | ||
| 1200 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | ||
| 1201 | { .div = 5, .val = 5, .flags = RATE_IN_243X }, | ||
| 1202 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
| 1203 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
| 1204 | { .div = 0 } | ||
| 1205 | }; | ||
| 1206 | |||
| 1207 | static const struct clksel ssi_ssr_sst_fck_clksel[] = { | ||
| 1208 | { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, | ||
| 1209 | { .parent = NULL } | ||
| 1210 | }; | ||
| 1211 | |||
| 1212 | static struct clk ssi_ssr_sst_fck = { | ||
| 1213 | .name = "ssi_fck", | ||
| 1214 | .parent = &core_ck, | ||
| 1215 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1216 | DELAYED_APP, | ||
| 1217 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 1218 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | ||
| 1219 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
| 1220 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, | ||
| 1221 | .clksel = ssi_ssr_sst_fck_clksel, | ||
| 1222 | .recalc = &omap2_clksel_recalc, | ||
| 1223 | .round_rate = &omap2_clksel_round_rate, | ||
| 1224 | .set_rate = &omap2_clksel_set_rate | ||
| 1225 | }; | ||
| 1226 | |||
| 1227 | /* | ||
| 1228 | * GFX clock domain | ||
| 1229 | * Clocks: | ||
| 1230 | * GFX_FCLK, GFX_ICLK | ||
| 1231 | * GFX_CG1(2d), GFX_CG2(3d) | ||
| 1232 | * | ||
| 1233 | * GFX_FCLK runs from L3, and is divided by (1,2,3,4) | ||
| 1234 | * The 2d and 3d clocks run at a hardware determined | ||
| 1235 | * divided value of fclk. | ||
| 1236 | * | ||
| 1237 | */ | ||
| 1238 | /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */ | ||
| 1239 | |||
| 1240 | /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ | ||
| 1241 | static const struct clksel gfx_fck_clksel[] = { | ||
| 1242 | { .parent = &core_l3_ck, .rates = gfx_l3_rates }, | ||
| 1243 | { .parent = NULL }, | ||
| 1244 | }; | ||
| 1245 | |||
| 1246 | static struct clk gfx_3d_fck = { | ||
| 1247 | .name = "gfx_3d_fck", | ||
| 1248 | .parent = &core_l3_ck, | ||
| 1249 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1250 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | ||
| 1251 | .enable_bit = OMAP24XX_EN_3D_SHIFT, | ||
| 1252 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | ||
| 1253 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | ||
| 1254 | .clksel = gfx_fck_clksel, | ||
| 1255 | .recalc = &omap2_clksel_recalc, | ||
| 1256 | .round_rate = &omap2_clksel_round_rate, | ||
| 1257 | .set_rate = &omap2_clksel_set_rate | ||
| 1258 | }; | ||
| 1259 | |||
| 1260 | static struct clk gfx_2d_fck = { | ||
| 1261 | .name = "gfx_2d_fck", | ||
| 1262 | .parent = &core_l3_ck, | ||
| 1263 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1264 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | ||
| 1265 | .enable_bit = OMAP24XX_EN_2D_SHIFT, | ||
| 1266 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | ||
| 1267 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | ||
| 1268 | .clksel = gfx_fck_clksel, | ||
| 1269 | .recalc = &omap2_clksel_recalc, | ||
| 1270 | .round_rate = &omap2_clksel_round_rate, | ||
| 1271 | .set_rate = &omap2_clksel_set_rate | ||
| 1272 | }; | ||
| 1273 | |||
| 1274 | static struct clk gfx_ick = { | ||
| 1275 | .name = "gfx_ick", /* From l3 */ | ||
| 1276 | .parent = &core_l3_ck, | ||
| 1277 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1278 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | ||
| 1279 | .enable_bit = OMAP_EN_GFX_SHIFT, | ||
| 1280 | .recalc = &followparent_recalc, | ||
| 1281 | }; | ||
| 1282 | |||
| 1283 | /* | ||
| 1284 | * Modem clock domain (2430) | ||
| 1285 | * CLOCKS: | ||
| 1286 | * MDM_OSC_CLK | ||
| 1287 | * MDM_ICLK | ||
| 1288 | * These clocks are usable in chassis mode only. | ||
| 1289 | */ | ||
| 1290 | static const struct clksel_rate mdm_ick_core_rates[] = { | ||
| 1291 | { .div = 1, .val = 1, .flags = RATE_IN_243X }, | ||
| 1292 | { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE }, | ||
| 1293 | { .div = 6, .val = 6, .flags = RATE_IN_243X }, | ||
| 1294 | { .div = 9, .val = 9, .flags = RATE_IN_243X }, | ||
| 1295 | { .div = 0 } | ||
| 1296 | }; | ||
| 1297 | |||
| 1298 | static const struct clksel mdm_ick_clksel[] = { | ||
| 1299 | { .parent = &core_ck, .rates = mdm_ick_core_rates }, | ||
| 1300 | { .parent = NULL } | ||
| 1301 | }; | ||
| 1302 | |||
| 1303 | static struct clk mdm_ick = { /* used both as a ick and fck */ | ||
| 1304 | .name = "mdm_ick", | ||
| 1305 | .parent = &core_ck, | ||
| 1306 | .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 1307 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), | ||
| 1308 | .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, | ||
| 1309 | .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), | ||
| 1310 | .clksel_mask = OMAP2430_CLKSEL_MDM_MASK, | ||
| 1311 | .clksel = mdm_ick_clksel, | ||
| 1312 | .recalc = &omap2_clksel_recalc, | ||
| 1313 | .round_rate = &omap2_clksel_round_rate, | ||
| 1314 | .set_rate = &omap2_clksel_set_rate | ||
| 1315 | }; | ||
| 1316 | |||
| 1317 | static struct clk mdm_osc_ck = { | ||
| 1318 | .name = "mdm_osc_ck", | ||
| 1319 | .parent = &osc_ck, | ||
| 1320 | .flags = CLOCK_IN_OMAP243X, | ||
| 1321 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), | ||
| 1322 | .enable_bit = OMAP2430_EN_OSC_SHIFT, | ||
| 1323 | .recalc = &followparent_recalc, | ||
| 1324 | }; | ||
| 1325 | |||
| 1326 | /* | ||
| 1327 | * L4 clock management domain | ||
| 1328 | * | ||
| 1329 | * This domain contains lots of interface clocks from the L4 interface, some | ||
| 1330 | * functional clocks. Fixed APLL functional source clocks are managed in | ||
| 1331 | * this domain. | ||
| 1332 | */ | ||
| 1333 | static const struct clksel_rate l4_core_l3_rates[] = { | ||
| 1334 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 1335 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
| 1336 | { .div = 0 } | ||
| 1337 | }; | ||
| 1338 | |||
| 1339 | static const struct clksel l4_clksel[] = { | ||
| 1340 | { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, | ||
| 1341 | { .parent = NULL } | ||
| 1342 | }; | ||
| 1343 | |||
| 1344 | static struct clk l4_ck = { /* used both as an ick and fck */ | ||
| 1345 | .name = "l4_ck", | ||
| 1346 | .parent = &core_l3_ck, | ||
| 1347 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1348 | ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES, | ||
| 1349 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
| 1350 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, | ||
| 1351 | .clksel = l4_clksel, | ||
| 1352 | .recalc = &omap2_clksel_recalc, | ||
| 1353 | .round_rate = &omap2_clksel_round_rate, | ||
| 1354 | .set_rate = &omap2_clksel_set_rate | ||
| 1355 | }; | ||
| 1356 | |||
| 1357 | static struct clk ssi_l4_ick = { | ||
| 1358 | .name = "ssi_l4_ick", | ||
| 1359 | .parent = &l4_ck, | ||
| 1360 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1361 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 1362 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | ||
| 1363 | .recalc = &followparent_recalc, | ||
| 1364 | }; | ||
| 1365 | |||
| 1366 | /* | ||
| 1367 | * DSS clock domain | ||
| 1368 | * CLOCKs: | ||
| 1369 | * DSS_L4_ICLK, DSS_L3_ICLK, | ||
| 1370 | * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK | ||
| 1371 | * | ||
| 1372 | * DSS is both initiator and target. | ||
| 1373 | */ | ||
| 1374 | /* XXX Add RATE_NOT_VALIDATED */ | ||
| 1375 | |||
| 1376 | static const struct clksel_rate dss1_fck_sys_rates[] = { | ||
| 1377 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 1378 | { .div = 0 } | ||
| 1379 | }; | ||
| 1380 | |||
| 1381 | static const struct clksel_rate dss1_fck_core_rates[] = { | ||
| 1382 | { .div = 1, .val = 1, .flags = RATE_IN_24XX }, | ||
| 1383 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
| 1384 | { .div = 3, .val = 3, .flags = RATE_IN_24XX }, | ||
| 1385 | { .div = 4, .val = 4, .flags = RATE_IN_24XX }, | ||
| 1386 | { .div = 5, .val = 5, .flags = RATE_IN_24XX }, | ||
| 1387 | { .div = 6, .val = 6, .flags = RATE_IN_24XX }, | ||
| 1388 | { .div = 8, .val = 8, .flags = RATE_IN_24XX }, | ||
| 1389 | { .div = 9, .val = 9, .flags = RATE_IN_24XX }, | ||
| 1390 | { .div = 12, .val = 12, .flags = RATE_IN_24XX }, | ||
| 1391 | { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 1392 | { .div = 0 } | ||
| 1393 | }; | ||
| 1394 | |||
| 1395 | static const struct clksel dss1_fck_clksel[] = { | ||
| 1396 | { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, | ||
| 1397 | { .parent = &core_ck, .rates = dss1_fck_core_rates }, | ||
| 1398 | { .parent = NULL }, | ||
| 1399 | }; | ||
| 1400 | |||
| 1401 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ | ||
| 1402 | .name = "dss_ick", | ||
| 1403 | .parent = &l4_ck, /* really both l3 and l4 */ | ||
| 1404 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1405 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1406 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | ||
| 1407 | .recalc = &followparent_recalc, | ||
| 1408 | }; | ||
| 1409 | |||
| 1410 | static struct clk dss1_fck = { | ||
| 1411 | .name = "dss1_fck", | ||
| 1412 | .parent = &core_ck, /* Core or sys */ | ||
| 1413 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1414 | DELAYED_APP, | ||
| 1415 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1416 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | ||
| 1417 | .init = &omap2_init_clksel_parent, | ||
| 1418 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
| 1419 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, | ||
| 1420 | .clksel = dss1_fck_clksel, | ||
| 1421 | .recalc = &omap2_clksel_recalc, | ||
| 1422 | .round_rate = &omap2_clksel_round_rate, | ||
| 1423 | .set_rate = &omap2_clksel_set_rate | ||
| 1424 | }; | ||
| 1425 | |||
| 1426 | static const struct clksel_rate dss2_fck_sys_rates[] = { | ||
| 1427 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 1428 | { .div = 0 } | ||
| 1429 | }; | ||
| 1430 | |||
| 1431 | static const struct clksel_rate dss2_fck_48m_rates[] = { | ||
| 1432 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 1433 | { .div = 0 } | ||
| 1434 | }; | ||
| 1435 | |||
| 1436 | static const struct clksel dss2_fck_clksel[] = { | ||
| 1437 | { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, | ||
| 1438 | { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, | ||
| 1439 | { .parent = NULL } | ||
| 1440 | }; | ||
| 1441 | |||
| 1442 | static struct clk dss2_fck = { /* Alt clk used in power management */ | ||
| 1443 | .name = "dss2_fck", | ||
| 1444 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ | ||
| 1445 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 1446 | DELAYED_APP, | ||
| 1447 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1448 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, | ||
| 1449 | .init = &omap2_init_clksel_parent, | ||
| 1450 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
| 1451 | .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, | ||
| 1452 | .clksel = dss2_fck_clksel, | ||
| 1453 | .recalc = &followparent_recalc, | ||
| 1454 | }; | ||
| 1455 | |||
| 1456 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ | ||
| 1457 | .name = "dss_54m_fck", /* 54m tv clk */ | ||
| 1458 | .parent = &func_54m_ck, | ||
| 1459 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1460 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1461 | .enable_bit = OMAP24XX_EN_TV_SHIFT, | ||
| 1462 | .recalc = &followparent_recalc, | ||
| 1463 | }; | ||
| 1464 | |||
| 1465 | /* | ||
| 1466 | * CORE power domain ICLK & FCLK defines. | ||
| 1467 | * Many of the these can have more than one possible parent. Entries | ||
| 1468 | * here will likely have an L4 interface parent, and may have multiple | ||
| 1469 | * functional clock parents. | ||
| 1470 | */ | ||
| 1471 | static const struct clksel_rate gpt_alt_rates[] = { | ||
| 1472 | { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
| 1473 | { .div = 0 } | ||
| 1474 | }; | ||
| 1475 | |||
| 1476 | static const struct clksel omap24xx_gpt_clksel[] = { | ||
| 1477 | { .parent = &func_32k_ck, .rates = gpt_32k_rates }, | ||
| 1478 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | ||
| 1479 | { .parent = &alt_ck, .rates = gpt_alt_rates }, | ||
| 1480 | { .parent = NULL }, | ||
| 1481 | }; | ||
| 1482 | |||
| 1483 | static struct clk gpt1_ick = { | ||
| 1484 | .name = "gpt1_ick", | ||
| 1485 | .parent = &l4_ck, | ||
| 1486 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1487 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 1488 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | ||
| 1489 | .recalc = &followparent_recalc, | ||
| 1490 | }; | ||
| 1491 | |||
| 1492 | static struct clk gpt1_fck = { | ||
| 1493 | .name = "gpt1_fck", | ||
| 1494 | .parent = &func_32k_ck, | ||
| 1495 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1496 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
| 1497 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | ||
| 1498 | .init = &omap2_init_clksel_parent, | ||
| 1499 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), | ||
| 1500 | .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, | ||
| 1501 | .clksel = omap24xx_gpt_clksel, | ||
| 1502 | .recalc = &omap2_clksel_recalc, | ||
| 1503 | .round_rate = &omap2_clksel_round_rate, | ||
| 1504 | .set_rate = &omap2_clksel_set_rate | ||
| 1505 | }; | ||
| 1506 | |||
| 1507 | static struct clk gpt2_ick = { | ||
| 1508 | .name = "gpt2_ick", | ||
| 1509 | .parent = &l4_ck, | ||
| 1510 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1511 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1512 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | ||
| 1513 | .recalc = &followparent_recalc, | ||
| 1514 | }; | ||
| 1515 | |||
| 1516 | static struct clk gpt2_fck = { | ||
| 1517 | .name = "gpt2_fck", | ||
| 1518 | .parent = &func_32k_ck, | ||
| 1519 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1520 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1521 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | ||
| 1522 | .init = &omap2_init_clksel_parent, | ||
| 1523 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1524 | .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, | ||
| 1525 | .clksel = omap24xx_gpt_clksel, | ||
| 1526 | .recalc = &omap2_clksel_recalc, | ||
| 1527 | }; | ||
| 1528 | |||
| 1529 | static struct clk gpt3_ick = { | ||
| 1530 | .name = "gpt3_ick", | ||
| 1531 | .parent = &l4_ck, | ||
| 1532 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1533 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1534 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | ||
| 1535 | .recalc = &followparent_recalc, | ||
| 1536 | }; | ||
| 1537 | |||
| 1538 | static struct clk gpt3_fck = { | ||
| 1539 | .name = "gpt3_fck", | ||
| 1540 | .parent = &func_32k_ck, | ||
| 1541 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1542 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1543 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | ||
| 1544 | .init = &omap2_init_clksel_parent, | ||
| 1545 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1546 | .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, | ||
| 1547 | .clksel = omap24xx_gpt_clksel, | ||
| 1548 | .recalc = &omap2_clksel_recalc, | ||
| 1549 | }; | ||
| 1550 | |||
| 1551 | static struct clk gpt4_ick = { | ||
| 1552 | .name = "gpt4_ick", | ||
| 1553 | .parent = &l4_ck, | ||
| 1554 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1555 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1556 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | ||
| 1557 | .recalc = &followparent_recalc, | ||
| 1558 | }; | ||
| 1559 | |||
| 1560 | static struct clk gpt4_fck = { | ||
| 1561 | .name = "gpt4_fck", | ||
| 1562 | .parent = &func_32k_ck, | ||
| 1563 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1564 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1565 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | ||
| 1566 | .init = &omap2_init_clksel_parent, | ||
| 1567 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1568 | .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, | ||
| 1569 | .clksel = omap24xx_gpt_clksel, | ||
| 1570 | .recalc = &omap2_clksel_recalc, | ||
| 1571 | }; | ||
| 1572 | |||
| 1573 | static struct clk gpt5_ick = { | ||
| 1574 | .name = "gpt5_ick", | ||
| 1575 | .parent = &l4_ck, | ||
| 1576 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1577 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1578 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | ||
| 1579 | .recalc = &followparent_recalc, | ||
| 1580 | }; | ||
| 1581 | |||
| 1582 | static struct clk gpt5_fck = { | ||
| 1583 | .name = "gpt5_fck", | ||
| 1584 | .parent = &func_32k_ck, | ||
| 1585 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1586 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1587 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | ||
| 1588 | .init = &omap2_init_clksel_parent, | ||
| 1589 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1590 | .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, | ||
| 1591 | .clksel = omap24xx_gpt_clksel, | ||
| 1592 | .recalc = &omap2_clksel_recalc, | ||
| 1593 | }; | ||
| 1594 | |||
| 1595 | static struct clk gpt6_ick = { | ||
| 1596 | .name = "gpt6_ick", | ||
| 1597 | .parent = &l4_ck, | ||
| 1598 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1599 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1600 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | ||
| 1601 | .recalc = &followparent_recalc, | ||
| 1602 | }; | ||
| 1603 | |||
| 1604 | static struct clk gpt6_fck = { | ||
| 1605 | .name = "gpt6_fck", | ||
| 1606 | .parent = &func_32k_ck, | ||
| 1607 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1608 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1609 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | ||
| 1610 | .init = &omap2_init_clksel_parent, | ||
| 1611 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1612 | .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, | ||
| 1613 | .clksel = omap24xx_gpt_clksel, | ||
| 1614 | .recalc = &omap2_clksel_recalc, | ||
| 1615 | }; | ||
| 1616 | |||
| 1617 | static struct clk gpt7_ick = { | ||
| 1618 | .name = "gpt7_ick", | ||
| 1619 | .parent = &l4_ck, | ||
| 1620 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1621 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1622 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | ||
| 1623 | .recalc = &followparent_recalc, | ||
| 1624 | }; | ||
| 1625 | |||
| 1626 | static struct clk gpt7_fck = { | ||
| 1627 | .name = "gpt7_fck", | ||
| 1628 | .parent = &func_32k_ck, | ||
| 1629 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1630 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1631 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | ||
| 1632 | .init = &omap2_init_clksel_parent, | ||
| 1633 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1634 | .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, | ||
| 1635 | .clksel = omap24xx_gpt_clksel, | ||
| 1636 | .recalc = &omap2_clksel_recalc, | ||
| 1637 | }; | ||
| 1638 | |||
| 1639 | static struct clk gpt8_ick = { | ||
| 1640 | .name = "gpt8_ick", | ||
| 1641 | .parent = &l4_ck, | ||
| 1642 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1643 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1644 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | ||
| 1645 | .recalc = &followparent_recalc, | ||
| 1646 | }; | ||
| 1647 | |||
| 1648 | static struct clk gpt8_fck = { | ||
| 1649 | .name = "gpt8_fck", | ||
| 1650 | .parent = &func_32k_ck, | ||
| 1651 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1652 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1653 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | ||
| 1654 | .init = &omap2_init_clksel_parent, | ||
| 1655 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1656 | .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, | ||
| 1657 | .clksel = omap24xx_gpt_clksel, | ||
| 1658 | .recalc = &omap2_clksel_recalc, | ||
| 1659 | }; | ||
| 1660 | |||
| 1661 | static struct clk gpt9_ick = { | ||
| 1662 | .name = "gpt9_ick", | ||
| 1663 | .parent = &l4_ck, | ||
| 1664 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1665 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1666 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | ||
| 1667 | .recalc = &followparent_recalc, | ||
| 1668 | }; | ||
| 1669 | |||
| 1670 | static struct clk gpt9_fck = { | ||
| 1671 | .name = "gpt9_fck", | ||
| 1672 | .parent = &func_32k_ck, | ||
| 1673 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1674 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1675 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | ||
| 1676 | .init = &omap2_init_clksel_parent, | ||
| 1677 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1678 | .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, | ||
| 1679 | .clksel = omap24xx_gpt_clksel, | ||
| 1680 | .recalc = &omap2_clksel_recalc, | ||
| 1681 | }; | ||
| 1682 | |||
| 1683 | static struct clk gpt10_ick = { | ||
| 1684 | .name = "gpt10_ick", | ||
| 1685 | .parent = &l4_ck, | ||
| 1686 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1687 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1688 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | ||
| 1689 | .recalc = &followparent_recalc, | ||
| 1690 | }; | ||
| 1691 | |||
| 1692 | static struct clk gpt10_fck = { | ||
| 1693 | .name = "gpt10_fck", | ||
| 1694 | .parent = &func_32k_ck, | ||
| 1695 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1696 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1697 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | ||
| 1698 | .init = &omap2_init_clksel_parent, | ||
| 1699 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1700 | .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, | ||
| 1701 | .clksel = omap24xx_gpt_clksel, | ||
| 1702 | .recalc = &omap2_clksel_recalc, | ||
| 1703 | }; | ||
| 1704 | |||
| 1705 | static struct clk gpt11_ick = { | ||
| 1706 | .name = "gpt11_ick", | ||
| 1707 | .parent = &l4_ck, | ||
| 1708 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1709 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1710 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | ||
| 1711 | .recalc = &followparent_recalc, | ||
| 1712 | }; | ||
| 1713 | |||
| 1714 | static struct clk gpt11_fck = { | ||
| 1715 | .name = "gpt11_fck", | ||
| 1716 | .parent = &func_32k_ck, | ||
| 1717 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1718 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1719 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | ||
| 1720 | .init = &omap2_init_clksel_parent, | ||
| 1721 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1722 | .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, | ||
| 1723 | .clksel = omap24xx_gpt_clksel, | ||
| 1724 | .recalc = &omap2_clksel_recalc, | ||
| 1725 | }; | ||
| 1726 | |||
| 1727 | static struct clk gpt12_ick = { | ||
| 1728 | .name = "gpt12_ick", | ||
| 1729 | .parent = &l4_ck, | ||
| 1730 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1731 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1732 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | ||
| 1733 | .recalc = &followparent_recalc, | ||
| 1734 | }; | ||
| 1735 | |||
| 1736 | static struct clk gpt12_fck = { | ||
| 1737 | .name = "gpt12_fck", | ||
| 1738 | .parent = &func_32k_ck, | ||
| 1739 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1740 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1741 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | ||
| 1742 | .init = &omap2_init_clksel_parent, | ||
| 1743 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), | ||
| 1744 | .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, | ||
| 1745 | .clksel = omap24xx_gpt_clksel, | ||
| 1746 | .recalc = &omap2_clksel_recalc, | ||
| 1747 | }; | ||
| 1748 | |||
| 1749 | static struct clk mcbsp1_ick = { | ||
| 1750 | .name = "mcbsp1_ick", | ||
| 1751 | .parent = &l4_ck, | ||
| 1752 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1753 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1754 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | ||
| 1755 | .recalc = &followparent_recalc, | ||
| 1756 | }; | ||
| 1757 | |||
| 1758 | static struct clk mcbsp1_fck = { | ||
| 1759 | .name = "mcbsp1_fck", | ||
| 1760 | .parent = &func_96m_ck, | ||
| 1761 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1762 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1763 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | ||
| 1764 | .recalc = &followparent_recalc, | ||
| 1765 | }; | ||
| 1766 | |||
| 1767 | static struct clk mcbsp2_ick = { | ||
| 1768 | .name = "mcbsp2_ick", | ||
| 1769 | .parent = &l4_ck, | ||
| 1770 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1771 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1772 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | ||
| 1773 | .recalc = &followparent_recalc, | ||
| 1774 | }; | ||
| 1775 | |||
| 1776 | static struct clk mcbsp2_fck = { | ||
| 1777 | .name = "mcbsp2_fck", | ||
| 1778 | .parent = &func_96m_ck, | ||
| 1779 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1780 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1781 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | ||
| 1782 | .recalc = &followparent_recalc, | ||
| 1783 | }; | ||
| 1784 | |||
| 1785 | static struct clk mcbsp3_ick = { | ||
| 1786 | .name = "mcbsp3_ick", | ||
| 1787 | .parent = &l4_ck, | ||
| 1788 | .flags = CLOCK_IN_OMAP243X, | ||
| 1789 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 1790 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, | ||
| 1791 | .recalc = &followparent_recalc, | ||
| 1792 | }; | ||
| 1793 | |||
| 1794 | static struct clk mcbsp3_fck = { | ||
| 1795 | .name = "mcbsp3_fck", | ||
| 1796 | .parent = &func_96m_ck, | ||
| 1797 | .flags = CLOCK_IN_OMAP243X, | ||
| 1798 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 1799 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, | ||
| 1800 | .recalc = &followparent_recalc, | ||
| 1801 | }; | ||
| 1802 | |||
| 1803 | static struct clk mcbsp4_ick = { | ||
| 1804 | .name = "mcbsp4_ick", | ||
| 1805 | .parent = &l4_ck, | ||
| 1806 | .flags = CLOCK_IN_OMAP243X, | ||
| 1807 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 1808 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, | ||
| 1809 | .recalc = &followparent_recalc, | ||
| 1810 | }; | ||
| 1811 | |||
| 1812 | static struct clk mcbsp4_fck = { | ||
| 1813 | .name = "mcbsp4_fck", | ||
| 1814 | .parent = &func_96m_ck, | ||
| 1815 | .flags = CLOCK_IN_OMAP243X, | ||
| 1816 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 1817 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, | ||
| 1818 | .recalc = &followparent_recalc, | ||
| 1819 | }; | ||
| 1820 | |||
| 1821 | static struct clk mcbsp5_ick = { | ||
| 1822 | .name = "mcbsp5_ick", | ||
| 1823 | .parent = &l4_ck, | ||
| 1824 | .flags = CLOCK_IN_OMAP243X, | ||
| 1825 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 1826 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, | ||
| 1827 | .recalc = &followparent_recalc, | ||
| 1828 | }; | ||
| 1829 | |||
| 1830 | static struct clk mcbsp5_fck = { | ||
| 1831 | .name = "mcbsp5_fck", | ||
| 1832 | .parent = &func_96m_ck, | ||
| 1833 | .flags = CLOCK_IN_OMAP243X, | ||
| 1834 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 1835 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, | ||
| 1836 | .recalc = &followparent_recalc, | ||
| 1837 | }; | ||
| 1838 | |||
| 1839 | static struct clk mcspi1_ick = { | ||
| 1840 | .name = "mcspi_ick", | ||
| 1841 | .id = 1, | ||
| 1842 | .parent = &l4_ck, | ||
| 1843 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1844 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1845 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | ||
| 1846 | .recalc = &followparent_recalc, | ||
| 1847 | }; | ||
| 1848 | |||
| 1849 | static struct clk mcspi1_fck = { | ||
| 1850 | .name = "mcspi_fck", | ||
| 1851 | .id = 1, | ||
| 1852 | .parent = &func_48m_ck, | ||
| 1853 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1854 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1855 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | ||
| 1856 | .recalc = &followparent_recalc, | ||
| 1857 | }; | ||
| 1858 | |||
| 1859 | static struct clk mcspi2_ick = { | ||
| 1860 | .name = "mcspi_ick", | ||
| 1861 | .id = 2, | ||
| 1862 | .parent = &l4_ck, | ||
| 1863 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1864 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1865 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | ||
| 1866 | .recalc = &followparent_recalc, | ||
| 1867 | }; | ||
| 1868 | |||
| 1869 | static struct clk mcspi2_fck = { | ||
| 1870 | .name = "mcspi_fck", | ||
| 1871 | .id = 2, | ||
| 1872 | .parent = &func_48m_ck, | ||
| 1873 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1874 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1875 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | ||
| 1876 | .recalc = &followparent_recalc, | ||
| 1877 | }; | ||
| 1878 | |||
| 1879 | static struct clk mcspi3_ick = { | ||
| 1880 | .name = "mcspi_ick", | ||
| 1881 | .id = 3, | ||
| 1882 | .parent = &l4_ck, | ||
| 1883 | .flags = CLOCK_IN_OMAP243X, | ||
| 1884 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 1885 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, | ||
| 1886 | .recalc = &followparent_recalc, | ||
| 1887 | }; | ||
| 1888 | |||
| 1889 | static struct clk mcspi3_fck = { | ||
| 1890 | .name = "mcspi_fck", | ||
| 1891 | .id = 3, | ||
| 1892 | .parent = &func_48m_ck, | ||
| 1893 | .flags = CLOCK_IN_OMAP243X, | ||
| 1894 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 1895 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, | ||
| 1896 | .recalc = &followparent_recalc, | ||
| 1897 | }; | ||
| 1898 | |||
| 1899 | static struct clk uart1_ick = { | ||
| 1900 | .name = "uart1_ick", | ||
| 1901 | .parent = &l4_ck, | ||
| 1902 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1903 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1904 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | ||
| 1905 | .recalc = &followparent_recalc, | ||
| 1906 | }; | ||
| 1907 | |||
| 1908 | static struct clk uart1_fck = { | ||
| 1909 | .name = "uart1_fck", | ||
| 1910 | .parent = &func_48m_ck, | ||
| 1911 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1912 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1913 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | ||
| 1914 | .recalc = &followparent_recalc, | ||
| 1915 | }; | ||
| 1916 | |||
| 1917 | static struct clk uart2_ick = { | ||
| 1918 | .name = "uart2_ick", | ||
| 1919 | .parent = &l4_ck, | ||
| 1920 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1921 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1922 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | ||
| 1923 | .recalc = &followparent_recalc, | ||
| 1924 | }; | ||
| 1925 | |||
| 1926 | static struct clk uart2_fck = { | ||
| 1927 | .name = "uart2_fck", | ||
| 1928 | .parent = &func_48m_ck, | ||
| 1929 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1930 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1931 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | ||
| 1932 | .recalc = &followparent_recalc, | ||
| 1933 | }; | ||
| 1934 | |||
| 1935 | static struct clk uart3_ick = { | ||
| 1936 | .name = "uart3_ick", | ||
| 1937 | .parent = &l4_ck, | ||
| 1938 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1939 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 1940 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | ||
| 1941 | .recalc = &followparent_recalc, | ||
| 1942 | }; | ||
| 1943 | |||
| 1944 | static struct clk uart3_fck = { | ||
| 1945 | .name = "uart3_fck", | ||
| 1946 | .parent = &func_48m_ck, | ||
| 1947 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1948 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 1949 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | ||
| 1950 | .recalc = &followparent_recalc, | ||
| 1951 | }; | ||
| 1952 | |||
| 1953 | static struct clk gpios_ick = { | ||
| 1954 | .name = "gpios_ick", | ||
| 1955 | .parent = &l4_ck, | ||
| 1956 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1957 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 1958 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | ||
| 1959 | .recalc = &followparent_recalc, | ||
| 1960 | }; | ||
| 1961 | |||
| 1962 | static struct clk gpios_fck = { | ||
| 1963 | .name = "gpios_fck", | ||
| 1964 | .parent = &func_32k_ck, | ||
| 1965 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1966 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
| 1967 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | ||
| 1968 | .recalc = &followparent_recalc, | ||
| 1969 | }; | ||
| 1970 | |||
| 1971 | static struct clk mpu_wdt_ick = { | ||
| 1972 | .name = "mpu_wdt_ick", | ||
| 1973 | .parent = &l4_ck, | ||
| 1974 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1975 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 1976 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | ||
| 1977 | .recalc = &followparent_recalc, | ||
| 1978 | }; | ||
| 1979 | |||
| 1980 | static struct clk mpu_wdt_fck = { | ||
| 1981 | .name = "mpu_wdt_fck", | ||
| 1982 | .parent = &func_32k_ck, | ||
| 1983 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1984 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
| 1985 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | ||
| 1986 | .recalc = &followparent_recalc, | ||
| 1987 | }; | ||
| 1988 | |||
| 1989 | static struct clk sync_32k_ick = { | ||
| 1990 | .name = "sync_32k_ick", | ||
| 1991 | .parent = &l4_ck, | ||
| 1992 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, | ||
| 1993 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 1994 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, | ||
| 1995 | .recalc = &followparent_recalc, | ||
| 1996 | }; | ||
| 1997 | static struct clk wdt1_ick = { | ||
| 1998 | .name = "wdt1_ick", | ||
| 1999 | .parent = &l4_ck, | ||
| 2000 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2001 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 2002 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, | ||
| 2003 | .recalc = &followparent_recalc, | ||
| 2004 | }; | ||
| 2005 | static struct clk omapctrl_ick = { | ||
| 2006 | .name = "omapctrl_ick", | ||
| 2007 | .parent = &l4_ck, | ||
| 2008 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, | ||
| 2009 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 2010 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, | ||
| 2011 | .recalc = &followparent_recalc, | ||
| 2012 | }; | ||
| 2013 | static struct clk icr_ick = { | ||
| 2014 | .name = "icr_ick", | ||
| 2015 | .parent = &l4_ck, | ||
| 2016 | .flags = CLOCK_IN_OMAP243X, | ||
| 2017 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 2018 | .enable_bit = OMAP2430_EN_ICR_SHIFT, | ||
| 2019 | .recalc = &followparent_recalc, | ||
| 2020 | }; | ||
| 2021 | |||
| 2022 | static struct clk cam_ick = { | ||
| 2023 | .name = "cam_ick", | ||
| 2024 | .parent = &l4_ck, | ||
| 2025 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2026 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 2027 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | ||
| 2028 | .recalc = &followparent_recalc, | ||
| 2029 | }; | ||
| 2030 | |||
| 2031 | static struct clk cam_fck = { | ||
| 2032 | .name = "cam_fck", | ||
| 2033 | .parent = &func_96m_ck, | ||
| 2034 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2035 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 2036 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | ||
| 2037 | .recalc = &followparent_recalc, | ||
| 2038 | }; | ||
| 2039 | |||
| 2040 | static struct clk mailboxes_ick = { | ||
| 2041 | .name = "mailboxes_ick", | ||
| 2042 | .parent = &l4_ck, | ||
| 2043 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2044 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 2045 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | ||
| 2046 | .recalc = &followparent_recalc, | ||
| 2047 | }; | ||
| 2048 | |||
| 2049 | static struct clk wdt4_ick = { | ||
| 2050 | .name = "wdt4_ick", | ||
| 2051 | .parent = &l4_ck, | ||
| 2052 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2053 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 2054 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | ||
| 2055 | .recalc = &followparent_recalc, | ||
| 2056 | }; | ||
| 2057 | |||
| 2058 | static struct clk wdt4_fck = { | ||
| 2059 | .name = "wdt4_fck", | ||
| 2060 | .parent = &func_32k_ck, | ||
| 2061 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2062 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 2063 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | ||
| 2064 | .recalc = &followparent_recalc, | ||
| 2065 | }; | ||
| 2066 | |||
| 2067 | static struct clk wdt3_ick = { | ||
| 2068 | .name = "wdt3_ick", | ||
| 2069 | .parent = &l4_ck, | ||
| 2070 | .flags = CLOCK_IN_OMAP242X, | ||
| 2071 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 2072 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | ||
| 2073 | .recalc = &followparent_recalc, | ||
| 2074 | }; | ||
| 2075 | |||
| 2076 | static struct clk wdt3_fck = { | ||
| 2077 | .name = "wdt3_fck", | ||
| 2078 | .parent = &func_32k_ck, | ||
| 2079 | .flags = CLOCK_IN_OMAP242X, | ||
| 2080 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 2081 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | ||
| 2082 | .recalc = &followparent_recalc, | ||
| 2083 | }; | ||
| 2084 | |||
| 2085 | static struct clk mspro_ick = { | ||
| 2086 | .name = "mspro_ick", | ||
| 2087 | .parent = &l4_ck, | ||
| 2088 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2089 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 2090 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | ||
| 2091 | .recalc = &followparent_recalc, | ||
| 2092 | }; | ||
| 2093 | |||
| 2094 | static struct clk mspro_fck = { | ||
| 2095 | .name = "mspro_fck", | ||
| 2096 | .parent = &func_96m_ck, | ||
| 2097 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2098 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 2099 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | ||
| 2100 | .recalc = &followparent_recalc, | ||
| 2101 | }; | ||
| 2102 | |||
| 2103 | static struct clk mmc_ick = { | ||
| 2104 | .name = "mmc_ick", | ||
| 2105 | .parent = &l4_ck, | ||
| 2106 | .flags = CLOCK_IN_OMAP242X, | ||
| 2107 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 2108 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | ||
| 2109 | .recalc = &followparent_recalc, | ||
| 2110 | }; | ||
| 2111 | |||
| 2112 | static struct clk mmc_fck = { | ||
| 2113 | .name = "mmc_fck", | ||
| 2114 | .parent = &func_96m_ck, | ||
| 2115 | .flags = CLOCK_IN_OMAP242X, | ||
| 2116 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 2117 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | ||
| 2118 | .recalc = &followparent_recalc, | ||
| 2119 | }; | ||
| 2120 | |||
| 2121 | static struct clk fac_ick = { | ||
| 2122 | .name = "fac_ick", | ||
| 2123 | .parent = &l4_ck, | ||
| 2124 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2125 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 2126 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | ||
| 2127 | .recalc = &followparent_recalc, | ||
| 2128 | }; | ||
| 2129 | |||
| 2130 | static struct clk fac_fck = { | ||
| 2131 | .name = "fac_fck", | ||
| 2132 | .parent = &func_12m_ck, | ||
| 2133 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2134 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 2135 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | ||
| 2136 | .recalc = &followparent_recalc, | ||
| 2137 | }; | ||
| 2138 | |||
| 2139 | static struct clk eac_ick = { | ||
| 2140 | .name = "eac_ick", | ||
| 2141 | .parent = &l4_ck, | ||
| 2142 | .flags = CLOCK_IN_OMAP242X, | ||
| 2143 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 2144 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | ||
| 2145 | .recalc = &followparent_recalc, | ||
| 2146 | }; | ||
| 2147 | |||
| 2148 | static struct clk eac_fck = { | ||
| 2149 | .name = "eac_fck", | ||
| 2150 | .parent = &func_96m_ck, | ||
| 2151 | .flags = CLOCK_IN_OMAP242X, | ||
| 2152 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 2153 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | ||
| 2154 | .recalc = &followparent_recalc, | ||
| 2155 | }; | ||
| 2156 | |||
| 2157 | static struct clk hdq_ick = { | ||
| 2158 | .name = "hdq_ick", | ||
| 2159 | .parent = &l4_ck, | ||
| 2160 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2161 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 2162 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | ||
| 2163 | .recalc = &followparent_recalc, | ||
| 2164 | }; | ||
| 2165 | |||
| 2166 | static struct clk hdq_fck = { | ||
| 2167 | .name = "hdq_fck", | ||
| 2168 | .parent = &func_12m_ck, | ||
| 2169 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2170 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 2171 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | ||
| 2172 | .recalc = &followparent_recalc, | ||
| 2173 | }; | ||
| 2174 | |||
| 2175 | static struct clk i2c2_ick = { | ||
| 2176 | .name = "i2c_ick", | ||
| 2177 | .id = 2, | ||
| 2178 | .parent = &l4_ck, | ||
| 2179 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2180 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 2181 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | ||
| 2182 | .recalc = &followparent_recalc, | ||
| 2183 | }; | ||
| 2184 | |||
| 2185 | static struct clk i2c2_fck = { | ||
| 2186 | .name = "i2c_fck", | ||
| 2187 | .id = 2, | ||
| 2188 | .parent = &func_12m_ck, | ||
| 2189 | .flags = CLOCK_IN_OMAP242X, | ||
| 2190 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 2191 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | ||
| 2192 | .recalc = &followparent_recalc, | ||
| 2193 | }; | ||
| 2194 | |||
| 2195 | static struct clk i2chs2_fck = { | ||
| 2196 | .name = "i2chs_fck", | ||
| 2197 | .id = 2, | ||
| 2198 | .parent = &func_96m_ck, | ||
| 2199 | .flags = CLOCK_IN_OMAP243X, | ||
| 2200 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 2201 | .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, | ||
| 2202 | .recalc = &followparent_recalc, | ||
| 2203 | }; | ||
| 2204 | |||
| 2205 | static struct clk i2c1_ick = { | ||
| 2206 | .name = "i2c_ick", | ||
| 2207 | .id = 1, | ||
| 2208 | .parent = &l4_ck, | ||
| 2209 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2210 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 2211 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | ||
| 2212 | .recalc = &followparent_recalc, | ||
| 2213 | }; | ||
| 2214 | |||
| 2215 | static struct clk i2c1_fck = { | ||
| 2216 | .name = "i2c_fck", | ||
| 2217 | .id = 1, | ||
| 2218 | .parent = &func_12m_ck, | ||
| 2219 | .flags = CLOCK_IN_OMAP242X, | ||
| 2220 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 2221 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | ||
| 2222 | .recalc = &followparent_recalc, | ||
| 2223 | }; | ||
| 2224 | |||
| 2225 | static struct clk i2chs1_fck = { | ||
| 2226 | .name = "i2chs_fck", | ||
| 2227 | .id = 1, | ||
| 2228 | .parent = &func_96m_ck, | ||
| 2229 | .flags = CLOCK_IN_OMAP243X, | ||
| 2230 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 2231 | .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, | ||
| 2232 | .recalc = &followparent_recalc, | ||
| 2233 | }; | ||
| 2234 | |||
| 2235 | static struct clk gpmc_fck = { | ||
| 2236 | .name = "gpmc_fck", | ||
| 2237 | .parent = &core_l3_ck, | ||
| 2238 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, | ||
| 2239 | .recalc = &followparent_recalc, | ||
| 2240 | }; | ||
| 2241 | |||
| 2242 | static struct clk sdma_fck = { | ||
| 2243 | .name = "sdma_fck", | ||
| 2244 | .parent = &core_l3_ck, | ||
| 2245 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2246 | .recalc = &followparent_recalc, | ||
| 2247 | }; | ||
| 2248 | |||
| 2249 | static struct clk sdma_ick = { | ||
| 2250 | .name = "sdma_ick", | ||
| 2251 | .parent = &l4_ck, | ||
| 2252 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2253 | .recalc = &followparent_recalc, | ||
| 2254 | }; | ||
| 2255 | |||
| 2256 | static struct clk vlynq_ick = { | ||
| 2257 | .name = "vlynq_ick", | ||
| 2258 | .parent = &core_l3_ck, | ||
| 2259 | .flags = CLOCK_IN_OMAP242X, | ||
| 2260 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 2261 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | ||
| 2262 | .recalc = &followparent_recalc, | ||
| 2263 | }; | ||
| 2264 | |||
| 2265 | static const struct clksel_rate vlynq_fck_96m_rates[] = { | ||
| 2266 | { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE }, | ||
| 2267 | { .div = 0 } | ||
| 2268 | }; | ||
| 2269 | |||
| 2270 | static const struct clksel_rate vlynq_fck_core_rates[] = { | ||
| 2271 | { .div = 1, .val = 1, .flags = RATE_IN_242X }, | ||
| 2272 | { .div = 2, .val = 2, .flags = RATE_IN_242X }, | ||
| 2273 | { .div = 3, .val = 3, .flags = RATE_IN_242X }, | ||
| 2274 | { .div = 4, .val = 4, .flags = RATE_IN_242X }, | ||
| 2275 | { .div = 6, .val = 6, .flags = RATE_IN_242X }, | ||
| 2276 | { .div = 8, .val = 8, .flags = RATE_IN_242X }, | ||
| 2277 | { .div = 9, .val = 9, .flags = RATE_IN_242X }, | ||
| 2278 | { .div = 12, .val = 12, .flags = RATE_IN_242X }, | ||
| 2279 | { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE }, | ||
| 2280 | { .div = 18, .val = 18, .flags = RATE_IN_242X }, | ||
| 2281 | { .div = 0 } | ||
| 2282 | }; | ||
| 2283 | |||
| 2284 | static const struct clksel vlynq_fck_clksel[] = { | ||
| 2285 | { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, | ||
| 2286 | { .parent = &core_ck, .rates = vlynq_fck_core_rates }, | ||
| 2287 | { .parent = NULL } | ||
| 2288 | }; | ||
| 2289 | |||
| 2290 | static struct clk vlynq_fck = { | ||
| 2291 | .name = "vlynq_fck", | ||
| 2292 | .parent = &func_96m_ck, | ||
| 2293 | .flags = CLOCK_IN_OMAP242X | DELAYED_APP, | ||
| 2294 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 2295 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | ||
| 2296 | .init = &omap2_init_clksel_parent, | ||
| 2297 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
| 2298 | .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, | ||
| 2299 | .clksel = vlynq_fck_clksel, | ||
| 2300 | .recalc = &omap2_clksel_recalc, | ||
| 2301 | .round_rate = &omap2_clksel_round_rate, | ||
| 2302 | .set_rate = &omap2_clksel_set_rate | ||
| 2303 | }; | ||
| 2304 | |||
| 2305 | static struct clk sdrc_ick = { | ||
| 2306 | .name = "sdrc_ick", | ||
| 2307 | .parent = &l4_ck, | ||
| 2308 | .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, | ||
| 2309 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | ||
| 2310 | .enable_bit = OMAP2430_EN_SDRC_SHIFT, | ||
| 2311 | .recalc = &followparent_recalc, | ||
| 2312 | }; | ||
| 2313 | |||
| 2314 | static struct clk des_ick = { | ||
| 2315 | .name = "des_ick", | ||
| 2316 | .parent = &l4_ck, | ||
| 2317 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2318 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | ||
| 2319 | .enable_bit = OMAP24XX_EN_DES_SHIFT, | ||
| 2320 | .recalc = &followparent_recalc, | ||
| 2321 | }; | ||
| 2322 | |||
| 2323 | static struct clk sha_ick = { | ||
| 2324 | .name = "sha_ick", | ||
| 2325 | .parent = &l4_ck, | ||
| 2326 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2327 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | ||
| 2328 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, | ||
| 2329 | .recalc = &followparent_recalc, | ||
| 2330 | }; | ||
| 2331 | |||
| 2332 | static struct clk rng_ick = { | ||
| 2333 | .name = "rng_ick", | ||
| 2334 | .parent = &l4_ck, | ||
| 2335 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2336 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | ||
| 2337 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, | ||
| 2338 | .recalc = &followparent_recalc, | ||
| 2339 | }; | ||
| 2340 | |||
| 2341 | static struct clk aes_ick = { | ||
| 2342 | .name = "aes_ick", | ||
| 2343 | .parent = &l4_ck, | ||
| 2344 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2345 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | ||
| 2346 | .enable_bit = OMAP24XX_EN_AES_SHIFT, | ||
| 2347 | .recalc = &followparent_recalc, | ||
| 2348 | }; | ||
| 2349 | |||
| 2350 | static struct clk pka_ick = { | ||
| 2351 | .name = "pka_ick", | ||
| 2352 | .parent = &l4_ck, | ||
| 2353 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2354 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | ||
| 2355 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, | ||
| 2356 | .recalc = &followparent_recalc, | ||
| 2357 | }; | ||
| 2358 | |||
| 2359 | static struct clk usb_fck = { | ||
| 2360 | .name = "usb_fck", | ||
| 2361 | .parent = &func_48m_ck, | ||
| 2362 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2363 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 2364 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | ||
| 2365 | .recalc = &followparent_recalc, | ||
| 2366 | }; | ||
| 2367 | |||
| 2368 | static struct clk usbhs_ick = { | ||
| 2369 | .name = "usbhs_ick", | ||
| 2370 | .parent = &core_l3_ck, | ||
| 2371 | .flags = CLOCK_IN_OMAP243X, | ||
| 2372 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 2373 | .enable_bit = OMAP2430_EN_USBHS_SHIFT, | ||
| 2374 | .recalc = &followparent_recalc, | ||
| 2375 | }; | ||
| 2376 | |||
| 2377 | static struct clk mmchs1_ick = { | ||
| 2378 | .name = "mmchs_ick", | ||
| 2379 | .id = 1, | ||
| 2380 | .parent = &l4_ck, | ||
| 2381 | .flags = CLOCK_IN_OMAP243X, | ||
| 2382 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 2383 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | ||
| 2384 | .recalc = &followparent_recalc, | ||
| 2385 | }; | ||
| 2386 | |||
| 2387 | static struct clk mmchs1_fck = { | ||
| 2388 | .name = "mmchs_fck", | ||
| 2389 | .id = 1, | ||
| 2390 | .parent = &func_96m_ck, | ||
| 2391 | .flags = CLOCK_IN_OMAP243X, | ||
| 2392 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 2393 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | ||
| 2394 | .recalc = &followparent_recalc, | ||
| 2395 | }; | ||
| 2396 | |||
| 2397 | static struct clk mmchs2_ick = { | ||
| 2398 | .name = "mmchs_ick", | ||
| 2399 | .id = 2, | ||
| 2400 | .parent = &l4_ck, | ||
| 2401 | .flags = CLOCK_IN_OMAP243X, | ||
| 2402 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 2403 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | ||
| 2404 | .recalc = &followparent_recalc, | ||
| 2405 | }; | ||
| 2406 | |||
| 2407 | static struct clk mmchs2_fck = { | ||
| 2408 | .name = "mmchs_fck", | ||
| 2409 | .id = 2, | ||
| 2410 | .parent = &func_96m_ck, | ||
| 2411 | .flags = CLOCK_IN_OMAP243X, | ||
| 2412 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 2413 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | ||
| 2414 | .recalc = &followparent_recalc, | ||
| 2415 | }; | ||
| 2416 | |||
| 2417 | static struct clk gpio5_ick = { | ||
| 2418 | .name = "gpio5_ick", | ||
| 2419 | .parent = &l4_ck, | ||
| 2420 | .flags = CLOCK_IN_OMAP243X, | ||
| 2421 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 2422 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, | ||
| 2423 | .recalc = &followparent_recalc, | ||
| 2424 | }; | ||
| 2425 | |||
| 2426 | static struct clk gpio5_fck = { | ||
| 2427 | .name = "gpio5_fck", | ||
| 2428 | .parent = &func_32k_ck, | ||
| 2429 | .flags = CLOCK_IN_OMAP243X, | ||
| 2430 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 2431 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, | ||
| 2432 | .recalc = &followparent_recalc, | ||
| 2433 | }; | ||
| 2434 | |||
| 2435 | static struct clk mdm_intc_ick = { | ||
| 2436 | .name = "mdm_intc_ick", | ||
| 2437 | .parent = &l4_ck, | ||
| 2438 | .flags = CLOCK_IN_OMAP243X, | ||
| 2439 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 2440 | .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, | ||
| 2441 | .recalc = &followparent_recalc, | ||
| 2442 | }; | ||
| 2443 | |||
| 2444 | static struct clk mmchsdb1_fck = { | ||
| 2445 | .name = "mmchsdb_fck", | ||
| 2446 | .id = 1, | ||
| 2447 | .parent = &func_32k_ck, | ||
| 2448 | .flags = CLOCK_IN_OMAP243X, | ||
| 2449 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 2450 | .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, | ||
| 2451 | .recalc = &followparent_recalc, | ||
| 2452 | }; | ||
| 2453 | |||
| 2454 | static struct clk mmchsdb2_fck = { | ||
| 2455 | .name = "mmchsdb_fck", | ||
| 2456 | .id = 2, | ||
| 2457 | .parent = &func_32k_ck, | ||
| 2458 | .flags = CLOCK_IN_OMAP243X, | ||
| 2459 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | ||
| 2460 | .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, | ||
| 2461 | .recalc = &followparent_recalc, | ||
| 2462 | }; | ||
| 2463 | |||
| 2464 | /* | ||
| 2465 | * This clock is a composite clock which does entire set changes then | ||
| 2466 | * forces a rebalance. It keys on the MPU speed, but it really could | ||
| 2467 | * be any key speed part of a set in the rate table. | ||
| 2468 | * | ||
| 2469 | * to really change a set, you need memory table sets which get changed | ||
| 2470 | * in sram, pre-notifiers & post notifiers, changing the top set, without | ||
| 2471 | * having low level display recalc's won't work... this is why dpm notifiers | ||
| 2472 | * work, isr's off, walk a list of clocks already _off_ and not messing with | ||
| 2473 | * the bus. | ||
| 2474 | * | ||
| 2475 | * This clock should have no parent. It embodies the entire upper level | ||
| 2476 | * active set. A parent will mess up some of the init also. | ||
| 2477 | */ | ||
| 2478 | static struct clk virt_prcm_set = { | ||
| 2479 | .name = "virt_prcm_set", | ||
| 2480 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 2481 | VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP, | ||
| 2482 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ | ||
| 2483 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ | ||
| 2484 | .set_rate = &omap2_select_table_rate, | ||
| 2485 | .round_rate = &omap2_round_to_table_rate, | ||
| 2486 | }; | ||
| 2487 | |||
| 2488 | static struct clk *onchip_24xx_clks[] __initdata = { | ||
| 2489 | /* external root sources */ | ||
| 2490 | &func_32k_ck, | ||
| 2491 | &osc_ck, | ||
| 2492 | &sys_ck, | ||
| 2493 | &alt_ck, | ||
| 2494 | /* internal analog sources */ | ||
| 2495 | &dpll_ck, | ||
| 2496 | &apll96_ck, | ||
| 2497 | &apll54_ck, | ||
| 2498 | /* internal prcm root sources */ | ||
| 2499 | &func_54m_ck, | ||
| 2500 | &core_ck, | ||
| 2501 | &func_96m_ck, | ||
| 2502 | &func_48m_ck, | ||
| 2503 | &func_12m_ck, | ||
| 2504 | &wdt1_osc_ck, | ||
| 2505 | &sys_clkout_src, | ||
| 2506 | &sys_clkout, | ||
| 2507 | &sys_clkout2_src, | ||
| 2508 | &sys_clkout2, | ||
| 2509 | &emul_ck, | ||
| 2510 | /* mpu domain clocks */ | ||
| 2511 | &mpu_ck, | ||
| 2512 | /* dsp domain clocks */ | ||
| 2513 | &dsp_fck, | ||
| 2514 | &dsp_irate_ick, | ||
| 2515 | &dsp_ick, /* 242x */ | ||
| 2516 | &iva2_1_ick, /* 243x */ | ||
| 2517 | &iva1_ifck, /* 242x */ | ||
| 2518 | &iva1_mpu_int_ifck, /* 242x */ | ||
| 2519 | /* GFX domain clocks */ | ||
| 2520 | &gfx_3d_fck, | ||
| 2521 | &gfx_2d_fck, | ||
| 2522 | &gfx_ick, | ||
| 2523 | /* Modem domain clocks */ | ||
| 2524 | &mdm_ick, | ||
| 2525 | &mdm_osc_ck, | ||
| 2526 | /* DSS domain clocks */ | ||
| 2527 | &dss_ick, | ||
| 2528 | &dss1_fck, | ||
| 2529 | &dss2_fck, | ||
| 2530 | &dss_54m_fck, | ||
| 2531 | /* L3 domain clocks */ | ||
| 2532 | &core_l3_ck, | ||
| 2533 | &ssi_ssr_sst_fck, | ||
| 2534 | &usb_l4_ick, | ||
| 2535 | /* L4 domain clocks */ | ||
| 2536 | &l4_ck, /* used as both core_l4 and wu_l4 */ | ||
| 2537 | &ssi_l4_ick, | ||
| 2538 | /* virtual meta-group clock */ | ||
| 2539 | &virt_prcm_set, | ||
| 2540 | /* general l4 interface ck, multi-parent functional clk */ | ||
| 2541 | &gpt1_ick, | ||
| 2542 | &gpt1_fck, | ||
| 2543 | &gpt2_ick, | ||
| 2544 | &gpt2_fck, | ||
| 2545 | &gpt3_ick, | ||
| 2546 | &gpt3_fck, | ||
| 2547 | &gpt4_ick, | ||
| 2548 | &gpt4_fck, | ||
| 2549 | &gpt5_ick, | ||
| 2550 | &gpt5_fck, | ||
| 2551 | &gpt6_ick, | ||
| 2552 | &gpt6_fck, | ||
| 2553 | &gpt7_ick, | ||
| 2554 | &gpt7_fck, | ||
| 2555 | &gpt8_ick, | ||
| 2556 | &gpt8_fck, | ||
| 2557 | &gpt9_ick, | ||
| 2558 | &gpt9_fck, | ||
| 2559 | &gpt10_ick, | ||
| 2560 | &gpt10_fck, | ||
| 2561 | &gpt11_ick, | ||
| 2562 | &gpt11_fck, | ||
| 2563 | &gpt12_ick, | ||
| 2564 | &gpt12_fck, | ||
| 2565 | &mcbsp1_ick, | ||
| 2566 | &mcbsp1_fck, | ||
| 2567 | &mcbsp2_ick, | ||
| 2568 | &mcbsp2_fck, | ||
| 2569 | &mcbsp3_ick, | ||
| 2570 | &mcbsp3_fck, | ||
| 2571 | &mcbsp4_ick, | ||
| 2572 | &mcbsp4_fck, | ||
| 2573 | &mcbsp5_ick, | ||
| 2574 | &mcbsp5_fck, | ||
| 2575 | &mcspi1_ick, | ||
| 2576 | &mcspi1_fck, | ||
| 2577 | &mcspi2_ick, | ||
| 2578 | &mcspi2_fck, | ||
| 2579 | &mcspi3_ick, | ||
| 2580 | &mcspi3_fck, | ||
| 2581 | &uart1_ick, | ||
| 2582 | &uart1_fck, | ||
| 2583 | &uart2_ick, | ||
| 2584 | &uart2_fck, | ||
| 2585 | &uart3_ick, | ||
| 2586 | &uart3_fck, | ||
| 2587 | &gpios_ick, | ||
| 2588 | &gpios_fck, | ||
| 2589 | &mpu_wdt_ick, | ||
| 2590 | &mpu_wdt_fck, | ||
| 2591 | &sync_32k_ick, | ||
| 2592 | &wdt1_ick, | ||
| 2593 | &omapctrl_ick, | ||
| 2594 | &icr_ick, | ||
| 2595 | &cam_fck, | ||
| 2596 | &cam_ick, | ||
| 2597 | &mailboxes_ick, | ||
| 2598 | &wdt4_ick, | ||
| 2599 | &wdt4_fck, | ||
| 2600 | &wdt3_ick, | ||
| 2601 | &wdt3_fck, | ||
| 2602 | &mspro_ick, | ||
| 2603 | &mspro_fck, | ||
| 2604 | &mmc_ick, | ||
| 2605 | &mmc_fck, | ||
| 2606 | &fac_ick, | ||
| 2607 | &fac_fck, | ||
| 2608 | &eac_ick, | ||
| 2609 | &eac_fck, | ||
| 2610 | &hdq_ick, | ||
| 2611 | &hdq_fck, | ||
| 2612 | &i2c1_ick, | ||
| 2613 | &i2c1_fck, | ||
| 2614 | &i2chs1_fck, | ||
| 2615 | &i2c2_ick, | ||
| 2616 | &i2c2_fck, | ||
| 2617 | &i2chs2_fck, | ||
| 2618 | &gpmc_fck, | ||
| 2619 | &sdma_fck, | ||
| 2620 | &sdma_ick, | ||
| 2621 | &vlynq_ick, | ||
| 2622 | &vlynq_fck, | ||
| 2623 | &sdrc_ick, | ||
| 2624 | &des_ick, | ||
| 2625 | &sha_ick, | ||
| 2626 | &rng_ick, | ||
| 2627 | &aes_ick, | ||
| 2628 | &pka_ick, | ||
| 2629 | &usb_fck, | ||
| 2630 | &usbhs_ick, | ||
| 2631 | &mmchs1_ick, | ||
| 2632 | &mmchs1_fck, | ||
| 2633 | &mmchs2_ick, | ||
| 2634 | &mmchs2_fck, | ||
| 2635 | &gpio5_ick, | ||
| 2636 | &gpio5_fck, | ||
| 2637 | &mdm_intc_ick, | ||
| 2638 | &mmchsdb1_fck, | ||
| 2639 | &mmchsdb2_fck, | ||
| 2640 | }; | ||
| 2641 | |||
| 2642 | #endif | ||
| 2643 | |||
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c new file mode 100644 index 000000000000..b42bdd6079a5 --- /dev/null +++ b/arch/arm/mach-omap2/clock34xx.c | |||
| @@ -0,0 +1,235 @@ | |||
| 1 | /* | ||
| 2 | * OMAP3-specific clock framework functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2007 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Written by Paul Walmsley | ||
| 8 | * | ||
| 9 | * Parts of this code are based on code written by | ||
| 10 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | #undef DEBUG | ||
| 17 | |||
| 18 | #include <linux/module.h> | ||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/device.h> | ||
| 21 | #include <linux/list.h> | ||
| 22 | #include <linux/errno.h> | ||
| 23 | #include <linux/delay.h> | ||
| 24 | #include <linux/clk.h> | ||
| 25 | #include <linux/io.h> | ||
| 26 | |||
| 27 | #include <asm/arch/clock.h> | ||
| 28 | #include <asm/arch/sram.h> | ||
| 29 | #include <asm/div64.h> | ||
| 30 | #include <asm/bitops.h> | ||
| 31 | |||
| 32 | #include "memory.h" | ||
| 33 | #include "clock.h" | ||
| 34 | #include "clock34xx.h" | ||
| 35 | #include "prm.h" | ||
| 36 | #include "prm-regbits-34xx.h" | ||
| 37 | #include "cm.h" | ||
| 38 | #include "cm-regbits-34xx.h" | ||
| 39 | |||
| 40 | /* CM_CLKEN_PLL*.EN* bit values */ | ||
| 41 | #define DPLL_LOCKED 0x7 | ||
| 42 | |||
| 43 | /** | ||
| 44 | * omap3_dpll_recalc - recalculate DPLL rate | ||
| 45 | * @clk: DPLL struct clk | ||
| 46 | * | ||
| 47 | * Recalculate and propagate the DPLL rate. | ||
| 48 | */ | ||
| 49 | static void omap3_dpll_recalc(struct clk *clk) | ||
| 50 | { | ||
| 51 | clk->rate = omap2_get_dpll_rate(clk); | ||
| 52 | |||
| 53 | propagate_rate(clk); | ||
| 54 | } | ||
| 55 | |||
| 56 | /** | ||
| 57 | * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate | ||
| 58 | * @clk: DPLL output struct clk | ||
| 59 | * | ||
| 60 | * Using parent clock DPLL data, look up DPLL state. If locked, set our | ||
| 61 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. | ||
| 62 | */ | ||
| 63 | static void omap3_clkoutx2_recalc(struct clk *clk) | ||
| 64 | { | ||
| 65 | const struct dpll_data *dd; | ||
| 66 | u32 v; | ||
| 67 | struct clk *pclk; | ||
| 68 | |||
| 69 | /* Walk up the parents of clk, looking for a DPLL */ | ||
| 70 | pclk = clk->parent; | ||
| 71 | while (pclk && !pclk->dpll_data) | ||
| 72 | pclk = pclk->parent; | ||
| 73 | |||
| 74 | /* clk does not have a DPLL as a parent? */ | ||
| 75 | WARN_ON(!pclk); | ||
| 76 | |||
| 77 | dd = pclk->dpll_data; | ||
| 78 | |||
| 79 | WARN_ON(!dd->control_reg || !dd->enable_mask); | ||
| 80 | |||
| 81 | v = __raw_readl(dd->control_reg) & dd->enable_mask; | ||
| 82 | v >>= __ffs(dd->enable_mask); | ||
| 83 | if (v != DPLL_LOCKED) | ||
| 84 | clk->rate = clk->parent->rate; | ||
| 85 | else | ||
| 86 | clk->rate = clk->parent->rate * 2; | ||
| 87 | |||
| 88 | if (clk->flags & RATE_PROPAGATES) | ||
| 89 | propagate_rate(clk); | ||
| 90 | } | ||
| 91 | |||
| 92 | /* | ||
| 93 | * As it is structured now, this will prevent an OMAP2/3 multiboot | ||
| 94 | * kernel from compiling. This will need further attention. | ||
| 95 | */ | ||
| 96 | #if defined(CONFIG_ARCH_OMAP3) | ||
| 97 | |||
| 98 | static struct clk_functions omap2_clk_functions = { | ||
| 99 | .clk_enable = omap2_clk_enable, | ||
| 100 | .clk_disable = omap2_clk_disable, | ||
| 101 | .clk_round_rate = omap2_clk_round_rate, | ||
| 102 | .clk_set_rate = omap2_clk_set_rate, | ||
| 103 | .clk_set_parent = omap2_clk_set_parent, | ||
| 104 | .clk_disable_unused = omap2_clk_disable_unused, | ||
| 105 | }; | ||
| 106 | |||
| 107 | /* | ||
| 108 | * Set clocks for bypass mode for reboot to work. | ||
| 109 | */ | ||
| 110 | void omap2_clk_prepare_for_reboot(void) | ||
| 111 | { | ||
| 112 | /* REVISIT: Not ready for 343x */ | ||
| 113 | #if 0 | ||
| 114 | u32 rate; | ||
| 115 | |||
| 116 | if (vclk == NULL || sclk == NULL) | ||
| 117 | return; | ||
| 118 | |||
| 119 | rate = clk_get_rate(sclk); | ||
| 120 | clk_set_rate(vclk, rate); | ||
| 121 | #endif | ||
| 122 | } | ||
| 123 | |||
| 124 | /* REVISIT: Move this init stuff out into clock.c */ | ||
| 125 | |||
| 126 | /* | ||
| 127 | * Switch the MPU rate if specified on cmdline. | ||
| 128 | * We cannot do this early until cmdline is parsed. | ||
| 129 | */ | ||
| 130 | static int __init omap2_clk_arch_init(void) | ||
| 131 | { | ||
| 132 | if (!mpurate) | ||
| 133 | return -EINVAL; | ||
| 134 | |||
| 135 | /* REVISIT: not yet ready for 343x */ | ||
| 136 | #if 0 | ||
| 137 | if (omap2_select_table_rate(&virt_prcm_set, mpurate)) | ||
| 138 | printk(KERN_ERR "Could not find matching MPU rate\n"); | ||
| 139 | #endif | ||
| 140 | |||
| 141 | recalculate_root_clocks(); | ||
| 142 | |||
| 143 | printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): " | ||
| 144 | "%ld.%01ld/%ld/%ld MHz\n", | ||
| 145 | (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, | ||
| 146 | (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ; | ||
| 147 | |||
| 148 | return 0; | ||
| 149 | } | ||
| 150 | arch_initcall(omap2_clk_arch_init); | ||
| 151 | |||
| 152 | int __init omap2_clk_init(void) | ||
| 153 | { | ||
| 154 | /* struct prcm_config *prcm; */ | ||
| 155 | struct clk **clkp; | ||
| 156 | /* u32 clkrate; */ | ||
| 157 | u32 cpu_clkflg; | ||
| 158 | |||
| 159 | /* REVISIT: Ultimately this will be used for multiboot */ | ||
| 160 | #if 0 | ||
| 161 | if (cpu_is_omap242x()) { | ||
| 162 | cpu_mask = RATE_IN_242X; | ||
| 163 | cpu_clkflg = CLOCK_IN_OMAP242X; | ||
| 164 | clkp = onchip_24xx_clks; | ||
| 165 | } else if (cpu_is_omap2430()) { | ||
| 166 | cpu_mask = RATE_IN_243X; | ||
| 167 | cpu_clkflg = CLOCK_IN_OMAP243X; | ||
| 168 | clkp = onchip_24xx_clks; | ||
| 169 | } | ||
| 170 | #endif | ||
| 171 | if (cpu_is_omap34xx()) { | ||
| 172 | cpu_mask = RATE_IN_343X; | ||
| 173 | cpu_clkflg = CLOCK_IN_OMAP343X; | ||
| 174 | clkp = onchip_34xx_clks; | ||
| 175 | |||
| 176 | /* | ||
| 177 | * Update this if there are further clock changes between ES2 | ||
| 178 | * and production parts | ||
| 179 | */ | ||
| 180 | if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) { | ||
| 181 | /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ | ||
| 182 | cpu_clkflg |= CLOCK_IN_OMAP3430ES1; | ||
| 183 | } else { | ||
| 184 | cpu_mask |= RATE_IN_3430ES2; | ||
| 185 | cpu_clkflg |= CLOCK_IN_OMAP3430ES2; | ||
| 186 | } | ||
| 187 | } | ||
| 188 | |||
| 189 | clk_init(&omap2_clk_functions); | ||
| 190 | |||
| 191 | for (clkp = onchip_34xx_clks; | ||
| 192 | clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks); | ||
| 193 | clkp++) { | ||
| 194 | if ((*clkp)->flags & cpu_clkflg) | ||
| 195 | clk_register(*clkp); | ||
| 196 | } | ||
| 197 | |||
| 198 | /* REVISIT: Not yet ready for OMAP3 */ | ||
| 199 | #if 0 | ||
| 200 | /* Check the MPU rate set by bootloader */ | ||
| 201 | clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); | ||
| 202 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
| 203 | if (!(prcm->flags & cpu_mask)) | ||
| 204 | continue; | ||
| 205 | if (prcm->xtal_speed != sys_ck.rate) | ||
| 206 | continue; | ||
| 207 | if (prcm->dpll_speed <= clkrate) | ||
| 208 | break; | ||
| 209 | } | ||
| 210 | curr_prcm_set = prcm; | ||
| 211 | #endif | ||
| 212 | |||
| 213 | recalculate_root_clocks(); | ||
| 214 | |||
| 215 | printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): " | ||
| 216 | "%ld.%01ld/%ld/%ld MHz\n", | ||
| 217 | (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, | ||
| 218 | (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); | ||
| 219 | |||
| 220 | /* | ||
| 221 | * Only enable those clocks we will need, let the drivers | ||
| 222 | * enable other clocks as necessary | ||
| 223 | */ | ||
| 224 | clk_enable_init_clocks(); | ||
| 225 | |||
| 226 | /* Avoid sleeping during omap2_clk_prepare_for_reboot() */ | ||
| 227 | /* REVISIT: not yet ready for 343x */ | ||
| 228 | #if 0 | ||
| 229 | vclk = clk_get(NULL, "virt_prcm_set"); | ||
| 230 | sclk = clk_get(NULL, "sys_ck"); | ||
| 231 | #endif | ||
| 232 | return 0; | ||
| 233 | } | ||
| 234 | |||
| 235 | #endif | ||
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h new file mode 100644 index 000000000000..cf4644a94b9b --- /dev/null +++ b/arch/arm/mach-omap2/clock34xx.h | |||
| @@ -0,0 +1,3009 @@ | |||
| 1 | /* | ||
| 2 | * OMAP3 clock framework | ||
| 3 | * | ||
| 4 | * Virtual clocks are introduced as a convenient tools. | ||
| 5 | * They are sources for other clocks and not supposed | ||
| 6 | * to be requested from drivers directly. | ||
| 7 | * | ||
| 8 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | ||
| 9 | * Copyright (C) 2007-2008 Nokia Corporation | ||
| 10 | * | ||
| 11 | * Written by Paul Walmsley | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H | ||
| 15 | #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H | ||
| 16 | |||
| 17 | #include <asm/arch/control.h> | ||
| 18 | |||
| 19 | #include "clock.h" | ||
| 20 | #include "cm.h" | ||
| 21 | #include "cm-regbits-34xx.h" | ||
| 22 | #include "prm.h" | ||
| 23 | #include "prm-regbits-34xx.h" | ||
| 24 | |||
| 25 | static void omap3_dpll_recalc(struct clk *clk); | ||
| 26 | static void omap3_clkoutx2_recalc(struct clk *clk); | ||
| 27 | |||
| 28 | /* | ||
| 29 | * DPLL1 supplies clock to the MPU. | ||
| 30 | * DPLL2 supplies clock to the IVA2. | ||
| 31 | * DPLL3 supplies CORE domain clocks. | ||
| 32 | * DPLL4 supplies peripheral clocks. | ||
| 33 | * DPLL5 supplies other peripheral clocks (USBHOST, USIM). | ||
| 34 | */ | ||
| 35 | |||
| 36 | /* PRM CLOCKS */ | ||
| 37 | |||
| 38 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ | ||
| 39 | static struct clk omap_32k_fck = { | ||
| 40 | .name = "omap_32k_fck", | ||
| 41 | .rate = 32768, | ||
| 42 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | ||
| 43 | ALWAYS_ENABLED, | ||
| 44 | .recalc = &propagate_rate, | ||
| 45 | }; | ||
| 46 | |||
| 47 | static struct clk secure_32k_fck = { | ||
| 48 | .name = "secure_32k_fck", | ||
| 49 | .rate = 32768, | ||
| 50 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | ||
| 51 | ALWAYS_ENABLED, | ||
| 52 | .recalc = &propagate_rate, | ||
| 53 | }; | ||
| 54 | |||
| 55 | /* Virtual source clocks for osc_sys_ck */ | ||
| 56 | static struct clk virt_12m_ck = { | ||
| 57 | .name = "virt_12m_ck", | ||
| 58 | .rate = 12000000, | ||
| 59 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | ||
| 60 | ALWAYS_ENABLED, | ||
| 61 | .recalc = &propagate_rate, | ||
| 62 | }; | ||
| 63 | |||
| 64 | static struct clk virt_13m_ck = { | ||
| 65 | .name = "virt_13m_ck", | ||
| 66 | .rate = 13000000, | ||
| 67 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | ||
| 68 | ALWAYS_ENABLED, | ||
| 69 | .recalc = &propagate_rate, | ||
| 70 | }; | ||
| 71 | |||
| 72 | static struct clk virt_16_8m_ck = { | ||
| 73 | .name = "virt_16_8m_ck", | ||
| 74 | .rate = 16800000, | ||
| 75 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES | | ||
| 76 | ALWAYS_ENABLED, | ||
| 77 | .recalc = &propagate_rate, | ||
| 78 | }; | ||
| 79 | |||
| 80 | static struct clk virt_19_2m_ck = { | ||
| 81 | .name = "virt_19_2m_ck", | ||
| 82 | .rate = 19200000, | ||
| 83 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | ||
| 84 | ALWAYS_ENABLED, | ||
| 85 | .recalc = &propagate_rate, | ||
| 86 | }; | ||
| 87 | |||
| 88 | static struct clk virt_26m_ck = { | ||
| 89 | .name = "virt_26m_ck", | ||
| 90 | .rate = 26000000, | ||
| 91 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | ||
| 92 | ALWAYS_ENABLED, | ||
| 93 | .recalc = &propagate_rate, | ||
| 94 | }; | ||
| 95 | |||
| 96 | static struct clk virt_38_4m_ck = { | ||
| 97 | .name = "virt_38_4m_ck", | ||
| 98 | .rate = 38400000, | ||
| 99 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | ||
| 100 | ALWAYS_ENABLED, | ||
| 101 | .recalc = &propagate_rate, | ||
| 102 | }; | ||
| 103 | |||
| 104 | static const struct clksel_rate osc_sys_12m_rates[] = { | ||
| 105 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 106 | { .div = 0 } | ||
| 107 | }; | ||
| 108 | |||
| 109 | static const struct clksel_rate osc_sys_13m_rates[] = { | ||
| 110 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 111 | { .div = 0 } | ||
| 112 | }; | ||
| 113 | |||
| 114 | static const struct clksel_rate osc_sys_16_8m_rates[] = { | ||
| 115 | { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, | ||
| 116 | { .div = 0 } | ||
| 117 | }; | ||
| 118 | |||
| 119 | static const struct clksel_rate osc_sys_19_2m_rates[] = { | ||
| 120 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 121 | { .div = 0 } | ||
| 122 | }; | ||
| 123 | |||
| 124 | static const struct clksel_rate osc_sys_26m_rates[] = { | ||
| 125 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 126 | { .div = 0 } | ||
| 127 | }; | ||
| 128 | |||
| 129 | static const struct clksel_rate osc_sys_38_4m_rates[] = { | ||
| 130 | { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 131 | { .div = 0 } | ||
| 132 | }; | ||
| 133 | |||
| 134 | static const struct clksel osc_sys_clksel[] = { | ||
| 135 | { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, | ||
| 136 | { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, | ||
| 137 | { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, | ||
| 138 | { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, | ||
| 139 | { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, | ||
| 140 | { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, | ||
| 141 | { .parent = NULL }, | ||
| 142 | }; | ||
| 143 | |||
| 144 | /* Oscillator clock */ | ||
| 145 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ | ||
| 146 | static struct clk osc_sys_ck = { | ||
| 147 | .name = "osc_sys_ck", | ||
| 148 | .init = &omap2_init_clksel_parent, | ||
| 149 | .clksel_reg = OMAP3430_PRM_CLKSEL, | ||
| 150 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, | ||
| 151 | .clksel = osc_sys_clksel, | ||
| 152 | /* REVISIT: deal with autoextclkmode? */ | ||
| 153 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | ||
| 154 | ALWAYS_ENABLED, | ||
| 155 | .recalc = &omap2_clksel_recalc, | ||
| 156 | }; | ||
| 157 | |||
| 158 | static const struct clksel_rate div2_rates[] = { | ||
| 159 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 160 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
| 161 | { .div = 0 } | ||
| 162 | }; | ||
| 163 | |||
| 164 | static const struct clksel sys_clksel[] = { | ||
| 165 | { .parent = &osc_sys_ck, .rates = div2_rates }, | ||
| 166 | { .parent = NULL } | ||
| 167 | }; | ||
| 168 | |||
| 169 | /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ | ||
| 170 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ | ||
| 171 | static struct clk sys_ck = { | ||
| 172 | .name = "sys_ck", | ||
| 173 | .parent = &osc_sys_ck, | ||
| 174 | .init = &omap2_init_clksel_parent, | ||
| 175 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, | ||
| 176 | .clksel_mask = OMAP_SYSCLKDIV_MASK, | ||
| 177 | .clksel = sys_clksel, | ||
| 178 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 179 | .recalc = &omap2_clksel_recalc, | ||
| 180 | }; | ||
| 181 | |||
| 182 | static struct clk sys_altclk = { | ||
| 183 | .name = "sys_altclk", | ||
| 184 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 185 | .recalc = &propagate_rate, | ||
| 186 | }; | ||
| 187 | |||
| 188 | /* Optional external clock input for some McBSPs */ | ||
| 189 | static struct clk mcbsp_clks = { | ||
| 190 | .name = "mcbsp_clks", | ||
| 191 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 192 | .recalc = &propagate_rate, | ||
| 193 | }; | ||
| 194 | |||
| 195 | /* PRM EXTERNAL CLOCK OUTPUT */ | ||
| 196 | |||
| 197 | static struct clk sys_clkout1 = { | ||
| 198 | .name = "sys_clkout1", | ||
| 199 | .parent = &osc_sys_ck, | ||
| 200 | .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, | ||
| 201 | .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, | ||
| 202 | .flags = CLOCK_IN_OMAP343X, | ||
| 203 | .recalc = &followparent_recalc, | ||
| 204 | }; | ||
| 205 | |||
| 206 | /* DPLLS */ | ||
| 207 | |||
| 208 | /* CM CLOCKS */ | ||
| 209 | |||
| 210 | static const struct clksel_rate dpll_bypass_rates[] = { | ||
| 211 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 212 | { .div = 0 } | ||
| 213 | }; | ||
| 214 | |||
| 215 | static const struct clksel_rate dpll_locked_rates[] = { | ||
| 216 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 217 | { .div = 0 } | ||
| 218 | }; | ||
| 219 | |||
| 220 | static const struct clksel_rate div16_dpll_rates[] = { | ||
| 221 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 222 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
| 223 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | ||
| 224 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
| 225 | { .div = 5, .val = 5, .flags = RATE_IN_343X }, | ||
| 226 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | ||
| 227 | { .div = 7, .val = 7, .flags = RATE_IN_343X }, | ||
| 228 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | ||
| 229 | { .div = 9, .val = 9, .flags = RATE_IN_343X }, | ||
| 230 | { .div = 10, .val = 10, .flags = RATE_IN_343X }, | ||
| 231 | { .div = 11, .val = 11, .flags = RATE_IN_343X }, | ||
| 232 | { .div = 12, .val = 12, .flags = RATE_IN_343X }, | ||
| 233 | { .div = 13, .val = 13, .flags = RATE_IN_343X }, | ||
| 234 | { .div = 14, .val = 14, .flags = RATE_IN_343X }, | ||
| 235 | { .div = 15, .val = 15, .flags = RATE_IN_343X }, | ||
| 236 | { .div = 16, .val = 16, .flags = RATE_IN_343X }, | ||
| 237 | { .div = 0 } | ||
| 238 | }; | ||
| 239 | |||
| 240 | /* DPLL1 */ | ||
| 241 | /* MPU clock source */ | ||
| 242 | /* Type: DPLL */ | ||
| 243 | static const struct dpll_data dpll1_dd = { | ||
| 244 | .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | ||
| 245 | .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, | ||
| 246 | .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, | ||
| 247 | .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), | ||
| 248 | .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, | ||
| 249 | .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, | ||
| 250 | .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, | ||
| 251 | .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, | ||
| 252 | }; | ||
| 253 | |||
| 254 | static struct clk dpll1_ck = { | ||
| 255 | .name = "dpll1_ck", | ||
| 256 | .parent = &sys_ck, | ||
| 257 | .dpll_data = &dpll1_dd, | ||
| 258 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 259 | .recalc = &omap3_dpll_recalc, | ||
| 260 | }; | ||
| 261 | |||
| 262 | /* | ||
| 263 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | ||
| 264 | * DPLL isn't bypassed. | ||
| 265 | */ | ||
| 266 | static struct clk dpll1_x2_ck = { | ||
| 267 | .name = "dpll1_x2_ck", | ||
| 268 | .parent = &dpll1_ck, | ||
| 269 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 270 | PARENT_CONTROLS_CLOCK, | ||
| 271 | .recalc = &omap3_clkoutx2_recalc, | ||
| 272 | }; | ||
| 273 | |||
| 274 | /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ | ||
| 275 | static const struct clksel div16_dpll1_x2m2_clksel[] = { | ||
| 276 | { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, | ||
| 277 | { .parent = NULL } | ||
| 278 | }; | ||
| 279 | |||
| 280 | /* | ||
| 281 | * Does not exist in the TRM - needed to separate the M2 divider from | ||
| 282 | * bypass selection in mpu_ck | ||
| 283 | */ | ||
| 284 | static struct clk dpll1_x2m2_ck = { | ||
| 285 | .name = "dpll1_x2m2_ck", | ||
| 286 | .parent = &dpll1_x2_ck, | ||
| 287 | .init = &omap2_init_clksel_parent, | ||
| 288 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), | ||
| 289 | .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, | ||
| 290 | .clksel = div16_dpll1_x2m2_clksel, | ||
| 291 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 292 | PARENT_CONTROLS_CLOCK, | ||
| 293 | .recalc = &omap2_clksel_recalc, | ||
| 294 | }; | ||
| 295 | |||
| 296 | /* DPLL2 */ | ||
| 297 | /* IVA2 clock source */ | ||
| 298 | /* Type: DPLL */ | ||
| 299 | |||
| 300 | static const struct dpll_data dpll2_dd = { | ||
| 301 | .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | ||
| 302 | .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, | ||
| 303 | .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, | ||
| 304 | .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), | ||
| 305 | .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, | ||
| 306 | .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, | ||
| 307 | .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, | ||
| 308 | .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, | ||
| 309 | }; | ||
| 310 | |||
| 311 | static struct clk dpll2_ck = { | ||
| 312 | .name = "dpll2_ck", | ||
| 313 | .parent = &sys_ck, | ||
| 314 | .dpll_data = &dpll2_dd, | ||
| 315 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 316 | .recalc = &omap3_dpll_recalc, | ||
| 317 | }; | ||
| 318 | |||
| 319 | static const struct clksel div16_dpll2_m2x2_clksel[] = { | ||
| 320 | { .parent = &dpll2_ck, .rates = div16_dpll_rates }, | ||
| 321 | { .parent = NULL } | ||
| 322 | }; | ||
| 323 | |||
| 324 | /* | ||
| 325 | * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT | ||
| 326 | * or CLKOUTX2. CLKOUT seems most plausible. | ||
| 327 | */ | ||
| 328 | static struct clk dpll2_m2_ck = { | ||
| 329 | .name = "dpll2_m2_ck", | ||
| 330 | .parent = &dpll2_ck, | ||
| 331 | .init = &omap2_init_clksel_parent, | ||
| 332 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, | ||
| 333 | OMAP3430_CM_CLKSEL2_PLL), | ||
| 334 | .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, | ||
| 335 | .clksel = div16_dpll2_m2x2_clksel, | ||
| 336 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 337 | PARENT_CONTROLS_CLOCK, | ||
| 338 | .recalc = &omap2_clksel_recalc, | ||
| 339 | }; | ||
| 340 | |||
| 341 | /* DPLL3 */ | ||
| 342 | /* Source clock for all interfaces and for some device fclks */ | ||
| 343 | /* Type: DPLL */ | ||
| 344 | static const struct dpll_data dpll3_dd = { | ||
| 345 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
| 346 | .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, | ||
| 347 | .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, | ||
| 348 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
| 349 | .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, | ||
| 350 | .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, | ||
| 351 | .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, | ||
| 352 | .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, | ||
| 353 | }; | ||
| 354 | |||
| 355 | static struct clk dpll3_ck = { | ||
| 356 | .name = "dpll3_ck", | ||
| 357 | .parent = &sys_ck, | ||
| 358 | .dpll_data = &dpll3_dd, | ||
| 359 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 360 | .recalc = &omap3_dpll_recalc, | ||
| 361 | }; | ||
| 362 | |||
| 363 | /* | ||
| 364 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | ||
| 365 | * DPLL isn't bypassed | ||
| 366 | */ | ||
| 367 | static struct clk dpll3_x2_ck = { | ||
| 368 | .name = "dpll3_x2_ck", | ||
| 369 | .parent = &dpll3_ck, | ||
| 370 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 371 | PARENT_CONTROLS_CLOCK, | ||
| 372 | .recalc = &omap3_clkoutx2_recalc, | ||
| 373 | }; | ||
| 374 | |||
| 375 | static const struct clksel_rate div31_dpll3_rates[] = { | ||
| 376 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 377 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
| 378 | { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, | ||
| 379 | { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, | ||
| 380 | { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, | ||
| 381 | { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, | ||
| 382 | { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, | ||
| 383 | { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, | ||
| 384 | { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, | ||
| 385 | { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, | ||
| 386 | { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, | ||
| 387 | { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, | ||
| 388 | { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, | ||
| 389 | { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, | ||
| 390 | { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, | ||
| 391 | { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, | ||
| 392 | { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, | ||
| 393 | { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, | ||
| 394 | { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, | ||
| 395 | { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, | ||
| 396 | { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, | ||
| 397 | { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, | ||
| 398 | { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, | ||
| 399 | { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, | ||
| 400 | { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, | ||
| 401 | { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, | ||
| 402 | { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, | ||
| 403 | { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, | ||
| 404 | { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, | ||
| 405 | { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, | ||
| 406 | { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, | ||
| 407 | { .div = 0 }, | ||
| 408 | }; | ||
| 409 | |||
| 410 | static const struct clksel div31_dpll3m2_clksel[] = { | ||
| 411 | { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, | ||
| 412 | { .parent = NULL } | ||
| 413 | }; | ||
| 414 | |||
| 415 | /* | ||
| 416 | * DPLL3 output M2 | ||
| 417 | * REVISIT: This DPLL output divider must be changed in SRAM, so until | ||
| 418 | * that code is ready, this should remain a 'read-only' clksel clock. | ||
| 419 | */ | ||
| 420 | static struct clk dpll3_m2_ck = { | ||
| 421 | .name = "dpll3_m2_ck", | ||
| 422 | .parent = &dpll3_ck, | ||
| 423 | .init = &omap2_init_clksel_parent, | ||
| 424 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
| 425 | .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, | ||
| 426 | .clksel = div31_dpll3m2_clksel, | ||
| 427 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 428 | PARENT_CONTROLS_CLOCK, | ||
| 429 | .recalc = &omap2_clksel_recalc, | ||
| 430 | }; | ||
| 431 | |||
| 432 | static const struct clksel core_ck_clksel[] = { | ||
| 433 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 434 | { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, | ||
| 435 | { .parent = NULL } | ||
| 436 | }; | ||
| 437 | |||
| 438 | static struct clk core_ck = { | ||
| 439 | .name = "core_ck", | ||
| 440 | .init = &omap2_init_clksel_parent, | ||
| 441 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 442 | .clksel_mask = OMAP3430_ST_CORE_CLK, | ||
| 443 | .clksel = core_ck_clksel, | ||
| 444 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 445 | PARENT_CONTROLS_CLOCK, | ||
| 446 | .recalc = &omap2_clksel_recalc, | ||
| 447 | }; | ||
| 448 | |||
| 449 | static const struct clksel dpll3_m2x2_ck_clksel[] = { | ||
| 450 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 451 | { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, | ||
| 452 | { .parent = NULL } | ||
| 453 | }; | ||
| 454 | |||
| 455 | static struct clk dpll3_m2x2_ck = { | ||
| 456 | .name = "dpll3_m2x2_ck", | ||
| 457 | .init = &omap2_init_clksel_parent, | ||
| 458 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 459 | .clksel_mask = OMAP3430_ST_CORE_CLK, | ||
| 460 | .clksel = dpll3_m2x2_ck_clksel, | ||
| 461 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 462 | PARENT_CONTROLS_CLOCK, | ||
| 463 | .recalc = &omap2_clksel_recalc, | ||
| 464 | }; | ||
| 465 | |||
| 466 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
| 467 | static const struct clksel div16_dpll3_clksel[] = { | ||
| 468 | { .parent = &dpll3_ck, .rates = div16_dpll_rates }, | ||
| 469 | { .parent = NULL } | ||
| 470 | }; | ||
| 471 | |||
| 472 | /* This virtual clock is the source for dpll3_m3x2_ck */ | ||
| 473 | static struct clk dpll3_m3_ck = { | ||
| 474 | .name = "dpll3_m3_ck", | ||
| 475 | .parent = &dpll3_ck, | ||
| 476 | .init = &omap2_init_clksel_parent, | ||
| 477 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
| 478 | .clksel_mask = OMAP3430_DIV_DPLL3_MASK, | ||
| 479 | .clksel = div16_dpll3_clksel, | ||
| 480 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 481 | PARENT_CONTROLS_CLOCK, | ||
| 482 | .recalc = &omap2_clksel_recalc, | ||
| 483 | }; | ||
| 484 | |||
| 485 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
| 486 | static struct clk dpll3_m3x2_ck = { | ||
| 487 | .name = "dpll3_m3x2_ck", | ||
| 488 | .parent = &dpll3_m3_ck, | ||
| 489 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
| 490 | .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, | ||
| 491 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | ||
| 492 | .recalc = &omap3_clkoutx2_recalc, | ||
| 493 | }; | ||
| 494 | |||
| 495 | static const struct clksel emu_core_alwon_ck_clksel[] = { | ||
| 496 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 497 | { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, | ||
| 498 | { .parent = NULL } | ||
| 499 | }; | ||
| 500 | |||
| 501 | static struct clk emu_core_alwon_ck = { | ||
| 502 | .name = "emu_core_alwon_ck", | ||
| 503 | .parent = &dpll3_m3x2_ck, | ||
| 504 | .init = &omap2_init_clksel_parent, | ||
| 505 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 506 | .clksel_mask = OMAP3430_ST_CORE_CLK, | ||
| 507 | .clksel = emu_core_alwon_ck_clksel, | ||
| 508 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 509 | PARENT_CONTROLS_CLOCK, | ||
| 510 | .recalc = &omap2_clksel_recalc, | ||
| 511 | }; | ||
| 512 | |||
| 513 | /* DPLL4 */ | ||
| 514 | /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ | ||
| 515 | /* Type: DPLL */ | ||
| 516 | static const struct dpll_data dpll4_dd = { | ||
| 517 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), | ||
| 518 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, | ||
| 519 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, | ||
| 520 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
| 521 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, | ||
| 522 | .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, | ||
| 523 | .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, | ||
| 524 | .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, | ||
| 525 | }; | ||
| 526 | |||
| 527 | static struct clk dpll4_ck = { | ||
| 528 | .name = "dpll4_ck", | ||
| 529 | .parent = &sys_ck, | ||
| 530 | .dpll_data = &dpll4_dd, | ||
| 531 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 532 | .recalc = &omap3_dpll_recalc, | ||
| 533 | }; | ||
| 534 | |||
| 535 | /* | ||
| 536 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | ||
| 537 | * DPLL isn't bypassed -- | ||
| 538 | * XXX does this serve any downstream clocks? | ||
| 539 | */ | ||
| 540 | static struct clk dpll4_x2_ck = { | ||
| 541 | .name = "dpll4_x2_ck", | ||
| 542 | .parent = &dpll4_ck, | ||
| 543 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 544 | PARENT_CONTROLS_CLOCK, | ||
| 545 | .recalc = &omap3_clkoutx2_recalc, | ||
| 546 | }; | ||
| 547 | |||
| 548 | static const struct clksel div16_dpll4_clksel[] = { | ||
| 549 | { .parent = &dpll4_ck, .rates = div16_dpll_rates }, | ||
| 550 | { .parent = NULL } | ||
| 551 | }; | ||
| 552 | |||
| 553 | /* This virtual clock is the source for dpll4_m2x2_ck */ | ||
| 554 | static struct clk dpll4_m2_ck = { | ||
| 555 | .name = "dpll4_m2_ck", | ||
| 556 | .parent = &dpll4_ck, | ||
| 557 | .init = &omap2_init_clksel_parent, | ||
| 558 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), | ||
| 559 | .clksel_mask = OMAP3430_DIV_96M_MASK, | ||
| 560 | .clksel = div16_dpll4_clksel, | ||
| 561 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 562 | PARENT_CONTROLS_CLOCK, | ||
| 563 | .recalc = &omap2_clksel_recalc, | ||
| 564 | }; | ||
| 565 | |||
| 566 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
| 567 | static struct clk dpll4_m2x2_ck = { | ||
| 568 | .name = "dpll4_m2x2_ck", | ||
| 569 | .parent = &dpll4_m2_ck, | ||
| 570 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
| 571 | .enable_bit = OMAP3430_PWRDN_96M_SHIFT, | ||
| 572 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | ||
| 573 | .recalc = &omap3_clkoutx2_recalc, | ||
| 574 | }; | ||
| 575 | |||
| 576 | static const struct clksel omap_96m_alwon_fck_clksel[] = { | ||
| 577 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 578 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, | ||
| 579 | { .parent = NULL } | ||
| 580 | }; | ||
| 581 | |||
| 582 | static struct clk omap_96m_alwon_fck = { | ||
| 583 | .name = "omap_96m_alwon_fck", | ||
| 584 | .parent = &dpll4_m2x2_ck, | ||
| 585 | .init = &omap2_init_clksel_parent, | ||
| 586 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 587 | .clksel_mask = OMAP3430_ST_PERIPH_CLK, | ||
| 588 | .clksel = omap_96m_alwon_fck_clksel, | ||
| 589 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 590 | PARENT_CONTROLS_CLOCK, | ||
| 591 | .recalc = &omap2_clksel_recalc, | ||
| 592 | }; | ||
| 593 | |||
| 594 | static struct clk omap_96m_fck = { | ||
| 595 | .name = "omap_96m_fck", | ||
| 596 | .parent = &omap_96m_alwon_fck, | ||
| 597 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 598 | PARENT_CONTROLS_CLOCK, | ||
| 599 | .recalc = &followparent_recalc, | ||
| 600 | }; | ||
| 601 | |||
| 602 | static const struct clksel cm_96m_fck_clksel[] = { | ||
| 603 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 604 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, | ||
| 605 | { .parent = NULL } | ||
| 606 | }; | ||
| 607 | |||
| 608 | static struct clk cm_96m_fck = { | ||
| 609 | .name = "cm_96m_fck", | ||
| 610 | .parent = &dpll4_m2x2_ck, | ||
| 611 | .init = &omap2_init_clksel_parent, | ||
| 612 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 613 | .clksel_mask = OMAP3430_ST_PERIPH_CLK, | ||
| 614 | .clksel = cm_96m_fck_clksel, | ||
| 615 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 616 | PARENT_CONTROLS_CLOCK, | ||
| 617 | .recalc = &omap2_clksel_recalc, | ||
| 618 | }; | ||
| 619 | |||
| 620 | /* This virtual clock is the source for dpll4_m3x2_ck */ | ||
| 621 | static struct clk dpll4_m3_ck = { | ||
| 622 | .name = "dpll4_m3_ck", | ||
| 623 | .parent = &dpll4_ck, | ||
| 624 | .init = &omap2_init_clksel_parent, | ||
| 625 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | ||
| 626 | .clksel_mask = OMAP3430_CLKSEL_TV_MASK, | ||
| 627 | .clksel = div16_dpll4_clksel, | ||
| 628 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 629 | PARENT_CONTROLS_CLOCK, | ||
| 630 | .recalc = &omap2_clksel_recalc, | ||
| 631 | }; | ||
| 632 | |||
| 633 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
| 634 | static struct clk dpll4_m3x2_ck = { | ||
| 635 | .name = "dpll4_m3x2_ck", | ||
| 636 | .parent = &dpll4_m3_ck, | ||
| 637 | .init = &omap2_init_clksel_parent, | ||
| 638 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
| 639 | .enable_bit = OMAP3430_PWRDN_TV_SHIFT, | ||
| 640 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | ||
| 641 | .recalc = &omap3_clkoutx2_recalc, | ||
| 642 | }; | ||
| 643 | |||
| 644 | static const struct clksel virt_omap_54m_fck_clksel[] = { | ||
| 645 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 646 | { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, | ||
| 647 | { .parent = NULL } | ||
| 648 | }; | ||
| 649 | |||
| 650 | static struct clk virt_omap_54m_fck = { | ||
| 651 | .name = "virt_omap_54m_fck", | ||
| 652 | .parent = &dpll4_m3x2_ck, | ||
| 653 | .init = &omap2_init_clksel_parent, | ||
| 654 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 655 | .clksel_mask = OMAP3430_ST_PERIPH_CLK, | ||
| 656 | .clksel = virt_omap_54m_fck_clksel, | ||
| 657 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 658 | PARENT_CONTROLS_CLOCK, | ||
| 659 | .recalc = &omap2_clksel_recalc, | ||
| 660 | }; | ||
| 661 | |||
| 662 | static const struct clksel_rate omap_54m_d4m3x2_rates[] = { | ||
| 663 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 664 | { .div = 0 } | ||
| 665 | }; | ||
| 666 | |||
| 667 | static const struct clksel_rate omap_54m_alt_rates[] = { | ||
| 668 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 669 | { .div = 0 } | ||
| 670 | }; | ||
| 671 | |||
| 672 | static const struct clksel omap_54m_clksel[] = { | ||
| 673 | { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates }, | ||
| 674 | { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, | ||
| 675 | { .parent = NULL } | ||
| 676 | }; | ||
| 677 | |||
| 678 | static struct clk omap_54m_fck = { | ||
| 679 | .name = "omap_54m_fck", | ||
| 680 | .init = &omap2_init_clksel_parent, | ||
| 681 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
| 682 | .clksel_mask = OMAP3430_SOURCE_54M, | ||
| 683 | .clksel = omap_54m_clksel, | ||
| 684 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 685 | PARENT_CONTROLS_CLOCK, | ||
| 686 | .recalc = &omap2_clksel_recalc, | ||
| 687 | }; | ||
| 688 | |||
| 689 | static const struct clksel_rate omap_48m_96md2_rates[] = { | ||
| 690 | { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 691 | { .div = 0 } | ||
| 692 | }; | ||
| 693 | |||
| 694 | static const struct clksel_rate omap_48m_alt_rates[] = { | ||
| 695 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 696 | { .div = 0 } | ||
| 697 | }; | ||
| 698 | |||
| 699 | static const struct clksel omap_48m_clksel[] = { | ||
| 700 | { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates }, | ||
| 701 | { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, | ||
| 702 | { .parent = NULL } | ||
| 703 | }; | ||
| 704 | |||
| 705 | static struct clk omap_48m_fck = { | ||
| 706 | .name = "omap_48m_fck", | ||
| 707 | .init = &omap2_init_clksel_parent, | ||
| 708 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | ||
| 709 | .clksel_mask = OMAP3430_SOURCE_48M, | ||
| 710 | .clksel = omap_48m_clksel, | ||
| 711 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 712 | PARENT_CONTROLS_CLOCK, | ||
| 713 | .recalc = &omap2_clksel_recalc, | ||
| 714 | }; | ||
| 715 | |||
| 716 | static struct clk omap_12m_fck = { | ||
| 717 | .name = "omap_12m_fck", | ||
| 718 | .parent = &omap_48m_fck, | ||
| 719 | .fixed_div = 4, | ||
| 720 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 721 | PARENT_CONTROLS_CLOCK, | ||
| 722 | .recalc = &omap2_fixed_divisor_recalc, | ||
| 723 | }; | ||
| 724 | |||
| 725 | /* This virstual clock is the source for dpll4_m4x2_ck */ | ||
| 726 | static struct clk dpll4_m4_ck = { | ||
| 727 | .name = "dpll4_m4_ck", | ||
| 728 | .parent = &dpll4_ck, | ||
| 729 | .init = &omap2_init_clksel_parent, | ||
| 730 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | ||
| 731 | .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, | ||
| 732 | .clksel = div16_dpll4_clksel, | ||
| 733 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 734 | PARENT_CONTROLS_CLOCK, | ||
| 735 | .recalc = &omap2_clksel_recalc, | ||
| 736 | }; | ||
| 737 | |||
| 738 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
| 739 | static struct clk dpll4_m4x2_ck = { | ||
| 740 | .name = "dpll4_m4x2_ck", | ||
| 741 | .parent = &dpll4_m4_ck, | ||
| 742 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
| 743 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | ||
| 744 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | ||
| 745 | .recalc = &omap3_clkoutx2_recalc, | ||
| 746 | }; | ||
| 747 | |||
| 748 | /* This virtual clock is the source for dpll4_m5x2_ck */ | ||
| 749 | static struct clk dpll4_m5_ck = { | ||
| 750 | .name = "dpll4_m5_ck", | ||
| 751 | .parent = &dpll4_ck, | ||
| 752 | .init = &omap2_init_clksel_parent, | ||
| 753 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), | ||
| 754 | .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, | ||
| 755 | .clksel = div16_dpll4_clksel, | ||
| 756 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 757 | PARENT_CONTROLS_CLOCK, | ||
| 758 | .recalc = &omap2_clksel_recalc, | ||
| 759 | }; | ||
| 760 | |||
| 761 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
| 762 | static struct clk dpll4_m5x2_ck = { | ||
| 763 | .name = "dpll4_m5x2_ck", | ||
| 764 | .parent = &dpll4_m5_ck, | ||
| 765 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
| 766 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | ||
| 767 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | ||
| 768 | .recalc = &omap3_clkoutx2_recalc, | ||
| 769 | }; | ||
| 770 | |||
| 771 | /* This virtual clock is the source for dpll4_m6x2_ck */ | ||
| 772 | static struct clk dpll4_m6_ck = { | ||
| 773 | .name = "dpll4_m6_ck", | ||
| 774 | .parent = &dpll4_ck, | ||
| 775 | .init = &omap2_init_clksel_parent, | ||
| 776 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
| 777 | .clksel_mask = OMAP3430_DIV_DPLL4_MASK, | ||
| 778 | .clksel = div16_dpll4_clksel, | ||
| 779 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 780 | PARENT_CONTROLS_CLOCK, | ||
| 781 | .recalc = &omap2_clksel_recalc, | ||
| 782 | }; | ||
| 783 | |||
| 784 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | ||
| 785 | static struct clk dpll4_m6x2_ck = { | ||
| 786 | .name = "dpll4_m6x2_ck", | ||
| 787 | .parent = &dpll4_m6_ck, | ||
| 788 | .init = &omap2_init_clksel_parent, | ||
| 789 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
| 790 | .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, | ||
| 791 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | ||
| 792 | .recalc = &omap3_clkoutx2_recalc, | ||
| 793 | }; | ||
| 794 | |||
| 795 | static struct clk emu_per_alwon_ck = { | ||
| 796 | .name = "emu_per_alwon_ck", | ||
| 797 | .parent = &dpll4_m6x2_ck, | ||
| 798 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 799 | PARENT_CONTROLS_CLOCK, | ||
| 800 | .recalc = &followparent_recalc, | ||
| 801 | }; | ||
| 802 | |||
| 803 | /* DPLL5 */ | ||
| 804 | /* Supplies 120MHz clock, USIM source clock */ | ||
| 805 | /* Type: DPLL */ | ||
| 806 | /* 3430ES2 only */ | ||
| 807 | static const struct dpll_data dpll5_dd = { | ||
| 808 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), | ||
| 809 | .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, | ||
| 810 | .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, | ||
| 811 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), | ||
| 812 | .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, | ||
| 813 | .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, | ||
| 814 | .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, | ||
| 815 | .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, | ||
| 816 | }; | ||
| 817 | |||
| 818 | static struct clk dpll5_ck = { | ||
| 819 | .name = "dpll5_ck", | ||
| 820 | .parent = &sys_ck, | ||
| 821 | .dpll_data = &dpll5_dd, | ||
| 822 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | | ||
| 823 | ALWAYS_ENABLED, | ||
| 824 | .recalc = &omap3_dpll_recalc, | ||
| 825 | }; | ||
| 826 | |||
| 827 | static const struct clksel div16_dpll5_clksel[] = { | ||
| 828 | { .parent = &dpll5_ck, .rates = div16_dpll_rates }, | ||
| 829 | { .parent = NULL } | ||
| 830 | }; | ||
| 831 | |||
| 832 | static struct clk dpll5_m2_ck = { | ||
| 833 | .name = "dpll5_m2_ck", | ||
| 834 | .parent = &dpll5_ck, | ||
| 835 | .init = &omap2_init_clksel_parent, | ||
| 836 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), | ||
| 837 | .clksel_mask = OMAP3430ES2_DIV_120M_MASK, | ||
| 838 | .clksel = div16_dpll5_clksel, | ||
| 839 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, | ||
| 840 | .recalc = &omap2_clksel_recalc, | ||
| 841 | }; | ||
| 842 | |||
| 843 | static const struct clksel omap_120m_fck_clksel[] = { | ||
| 844 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 845 | { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, | ||
| 846 | { .parent = NULL } | ||
| 847 | }; | ||
| 848 | |||
| 849 | static struct clk omap_120m_fck = { | ||
| 850 | .name = "omap_120m_fck", | ||
| 851 | .parent = &dpll5_m2_ck, | ||
| 852 | .init = &omap2_init_clksel_parent, | ||
| 853 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), | ||
| 854 | .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, | ||
| 855 | .clksel = omap_120m_fck_clksel, | ||
| 856 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | | ||
| 857 | PARENT_CONTROLS_CLOCK, | ||
| 858 | .recalc = &omap2_clksel_recalc, | ||
| 859 | }; | ||
| 860 | |||
| 861 | /* CM EXTERNAL CLOCK OUTPUTS */ | ||
| 862 | |||
| 863 | static const struct clksel_rate clkout2_src_core_rates[] = { | ||
| 864 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 865 | { .div = 0 } | ||
| 866 | }; | ||
| 867 | |||
| 868 | static const struct clksel_rate clkout2_src_sys_rates[] = { | ||
| 869 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 870 | { .div = 0 } | ||
| 871 | }; | ||
| 872 | |||
| 873 | static const struct clksel_rate clkout2_src_96m_rates[] = { | ||
| 874 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 875 | { .div = 0 } | ||
| 876 | }; | ||
| 877 | |||
| 878 | static const struct clksel_rate clkout2_src_54m_rates[] = { | ||
| 879 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 880 | { .div = 0 } | ||
| 881 | }; | ||
| 882 | |||
| 883 | static const struct clksel clkout2_src_clksel[] = { | ||
| 884 | { .parent = &core_ck, .rates = clkout2_src_core_rates }, | ||
| 885 | { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, | ||
| 886 | { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates }, | ||
| 887 | { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, | ||
| 888 | { .parent = NULL } | ||
| 889 | }; | ||
| 890 | |||
| 891 | static struct clk clkout2_src_ck = { | ||
| 892 | .name = "clkout2_src_ck", | ||
| 893 | .init = &omap2_init_clksel_parent, | ||
| 894 | .enable_reg = OMAP3430_CM_CLKOUT_CTRL, | ||
| 895 | .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, | ||
| 896 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | ||
| 897 | .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, | ||
| 898 | .clksel = clkout2_src_clksel, | ||
| 899 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 900 | .recalc = &omap2_clksel_recalc, | ||
| 901 | }; | ||
| 902 | |||
| 903 | static const struct clksel_rate sys_clkout2_rates[] = { | ||
| 904 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 905 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, | ||
| 906 | { .div = 4, .val = 2, .flags = RATE_IN_343X }, | ||
| 907 | { .div = 8, .val = 3, .flags = RATE_IN_343X }, | ||
| 908 | { .div = 16, .val = 4, .flags = RATE_IN_343X }, | ||
| 909 | { .div = 0 }, | ||
| 910 | }; | ||
| 911 | |||
| 912 | static const struct clksel sys_clkout2_clksel[] = { | ||
| 913 | { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, | ||
| 914 | { .parent = NULL }, | ||
| 915 | }; | ||
| 916 | |||
| 917 | static struct clk sys_clkout2 = { | ||
| 918 | .name = "sys_clkout2", | ||
| 919 | .init = &omap2_init_clksel_parent, | ||
| 920 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | ||
| 921 | .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, | ||
| 922 | .clksel = sys_clkout2_clksel, | ||
| 923 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | ||
| 924 | .recalc = &omap2_clksel_recalc, | ||
| 925 | }; | ||
| 926 | |||
| 927 | /* CM OUTPUT CLOCKS */ | ||
| 928 | |||
| 929 | static struct clk corex2_fck = { | ||
| 930 | .name = "corex2_fck", | ||
| 931 | .parent = &dpll3_m2x2_ck, | ||
| 932 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 933 | PARENT_CONTROLS_CLOCK, | ||
| 934 | .recalc = &followparent_recalc, | ||
| 935 | }; | ||
| 936 | |||
| 937 | /* DPLL power domain clock controls */ | ||
| 938 | |||
| 939 | static const struct clksel div2_core_clksel[] = { | ||
| 940 | { .parent = &core_ck, .rates = div2_rates }, | ||
| 941 | { .parent = NULL } | ||
| 942 | }; | ||
| 943 | |||
| 944 | /* | ||
| 945 | * REVISIT: Are these in DPLL power domain or CM power domain? docs | ||
| 946 | * may be inconsistent here? | ||
| 947 | */ | ||
| 948 | static struct clk dpll1_fck = { | ||
| 949 | .name = "dpll1_fck", | ||
| 950 | .parent = &core_ck, | ||
| 951 | .init = &omap2_init_clksel_parent, | ||
| 952 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | ||
| 953 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, | ||
| 954 | .clksel = div2_core_clksel, | ||
| 955 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 956 | PARENT_CONTROLS_CLOCK, | ||
| 957 | .recalc = &omap2_clksel_recalc, | ||
| 958 | }; | ||
| 959 | |||
| 960 | /* | ||
| 961 | * MPU clksel: | ||
| 962 | * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck | ||
| 963 | * derives from the high-frequency bypass clock originating from DPLL3, | ||
| 964 | * called 'dpll1_fck' | ||
| 965 | */ | ||
| 966 | static const struct clksel mpu_clksel[] = { | ||
| 967 | { .parent = &dpll1_fck, .rates = dpll_bypass_rates }, | ||
| 968 | { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, | ||
| 969 | { .parent = NULL } | ||
| 970 | }; | ||
| 971 | |||
| 972 | static struct clk mpu_ck = { | ||
| 973 | .name = "mpu_ck", | ||
| 974 | .parent = &dpll1_x2m2_ck, | ||
| 975 | .init = &omap2_init_clksel_parent, | ||
| 976 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | ||
| 977 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, | ||
| 978 | .clksel = mpu_clksel, | ||
| 979 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 980 | PARENT_CONTROLS_CLOCK, | ||
| 981 | .recalc = &omap2_clksel_recalc, | ||
| 982 | }; | ||
| 983 | |||
| 984 | /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ | ||
| 985 | static const struct clksel_rate arm_fck_rates[] = { | ||
| 986 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 987 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, | ||
| 988 | { .div = 0 }, | ||
| 989 | }; | ||
| 990 | |||
| 991 | static const struct clksel arm_fck_clksel[] = { | ||
| 992 | { .parent = &mpu_ck, .rates = arm_fck_rates }, | ||
| 993 | { .parent = NULL } | ||
| 994 | }; | ||
| 995 | |||
| 996 | static struct clk arm_fck = { | ||
| 997 | .name = "arm_fck", | ||
| 998 | .parent = &mpu_ck, | ||
| 999 | .init = &omap2_init_clksel_parent, | ||
| 1000 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | ||
| 1001 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, | ||
| 1002 | .clksel = arm_fck_clksel, | ||
| 1003 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1004 | PARENT_CONTROLS_CLOCK, | ||
| 1005 | .recalc = &omap2_clksel_recalc, | ||
| 1006 | }; | ||
| 1007 | |||
| 1008 | /* | ||
| 1009 | * REVISIT: This clock is never specifically defined in the 3430 TRM, | ||
| 1010 | * although it is referenced - so this is a guess | ||
| 1011 | */ | ||
| 1012 | static struct clk emu_mpu_alwon_ck = { | ||
| 1013 | .name = "emu_mpu_alwon_ck", | ||
| 1014 | .parent = &mpu_ck, | ||
| 1015 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1016 | PARENT_CONTROLS_CLOCK, | ||
| 1017 | .recalc = &followparent_recalc, | ||
| 1018 | }; | ||
| 1019 | |||
| 1020 | static struct clk dpll2_fck = { | ||
| 1021 | .name = "dpll2_fck", | ||
| 1022 | .parent = &core_ck, | ||
| 1023 | .init = &omap2_init_clksel_parent, | ||
| 1024 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | ||
| 1025 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, | ||
| 1026 | .clksel = div2_core_clksel, | ||
| 1027 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1028 | PARENT_CONTROLS_CLOCK, | ||
| 1029 | .recalc = &omap2_clksel_recalc, | ||
| 1030 | }; | ||
| 1031 | |||
| 1032 | /* | ||
| 1033 | * IVA2 clksel: | ||
| 1034 | * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck | ||
| 1035 | * derives from the high-frequency bypass clock originating from DPLL3, | ||
| 1036 | * called 'dpll2_fck' | ||
| 1037 | */ | ||
| 1038 | |||
| 1039 | static const struct clksel iva2_clksel[] = { | ||
| 1040 | { .parent = &dpll2_fck, .rates = dpll_bypass_rates }, | ||
| 1041 | { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, | ||
| 1042 | { .parent = NULL } | ||
| 1043 | }; | ||
| 1044 | |||
| 1045 | static struct clk iva2_ck = { | ||
| 1046 | .name = "iva2_ck", | ||
| 1047 | .parent = &dpll2_m2_ck, | ||
| 1048 | .init = &omap2_init_clksel_parent, | ||
| 1049 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, | ||
| 1050 | OMAP3430_CM_IDLEST_PLL), | ||
| 1051 | .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, | ||
| 1052 | .clksel = iva2_clksel, | ||
| 1053 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1054 | PARENT_CONTROLS_CLOCK, | ||
| 1055 | .recalc = &omap2_clksel_recalc, | ||
| 1056 | }; | ||
| 1057 | |||
| 1058 | /* Common interface clocks */ | ||
| 1059 | |||
| 1060 | static struct clk l3_ick = { | ||
| 1061 | .name = "l3_ick", | ||
| 1062 | .parent = &core_ck, | ||
| 1063 | .init = &omap2_init_clksel_parent, | ||
| 1064 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
| 1065 | .clksel_mask = OMAP3430_CLKSEL_L3_MASK, | ||
| 1066 | .clksel = div2_core_clksel, | ||
| 1067 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1068 | PARENT_CONTROLS_CLOCK, | ||
| 1069 | .recalc = &omap2_clksel_recalc, | ||
| 1070 | }; | ||
| 1071 | |||
| 1072 | static const struct clksel div2_l3_clksel[] = { | ||
| 1073 | { .parent = &l3_ick, .rates = div2_rates }, | ||
| 1074 | { .parent = NULL } | ||
| 1075 | }; | ||
| 1076 | |||
| 1077 | static struct clk l4_ick = { | ||
| 1078 | .name = "l4_ick", | ||
| 1079 | .parent = &l3_ick, | ||
| 1080 | .init = &omap2_init_clksel_parent, | ||
| 1081 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
| 1082 | .clksel_mask = OMAP3430_CLKSEL_L4_MASK, | ||
| 1083 | .clksel = div2_l3_clksel, | ||
| 1084 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1085 | PARENT_CONTROLS_CLOCK, | ||
| 1086 | .recalc = &omap2_clksel_recalc, | ||
| 1087 | |||
| 1088 | }; | ||
| 1089 | |||
| 1090 | static const struct clksel div2_l4_clksel[] = { | ||
| 1091 | { .parent = &l4_ick, .rates = div2_rates }, | ||
| 1092 | { .parent = NULL } | ||
| 1093 | }; | ||
| 1094 | |||
| 1095 | static struct clk rm_ick = { | ||
| 1096 | .name = "rm_ick", | ||
| 1097 | .parent = &l4_ick, | ||
| 1098 | .init = &omap2_init_clksel_parent, | ||
| 1099 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | ||
| 1100 | .clksel_mask = OMAP3430_CLKSEL_RM_MASK, | ||
| 1101 | .clksel = div2_l4_clksel, | ||
| 1102 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | ||
| 1103 | .recalc = &omap2_clksel_recalc, | ||
| 1104 | }; | ||
| 1105 | |||
| 1106 | /* GFX power domain */ | ||
| 1107 | |||
| 1108 | /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ | ||
| 1109 | |||
| 1110 | static const struct clksel gfx_l3_clksel[] = { | ||
| 1111 | { .parent = &l3_ick, .rates = gfx_l3_rates }, | ||
| 1112 | { .parent = NULL } | ||
| 1113 | }; | ||
| 1114 | |||
| 1115 | static struct clk gfx_l3_fck = { | ||
| 1116 | .name = "gfx_l3_fck", | ||
| 1117 | .parent = &l3_ick, | ||
| 1118 | .init = &omap2_init_clksel_parent, | ||
| 1119 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | ||
| 1120 | .enable_bit = OMAP_EN_GFX_SHIFT, | ||
| 1121 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | ||
| 1122 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | ||
| 1123 | .clksel = gfx_l3_clksel, | ||
| 1124 | .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES, | ||
| 1125 | .recalc = &omap2_clksel_recalc, | ||
| 1126 | }; | ||
| 1127 | |||
| 1128 | static struct clk gfx_l3_ick = { | ||
| 1129 | .name = "gfx_l3_ick", | ||
| 1130 | .parent = &l3_ick, | ||
| 1131 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | ||
| 1132 | .enable_bit = OMAP_EN_GFX_SHIFT, | ||
| 1133 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1134 | .recalc = &followparent_recalc, | ||
| 1135 | }; | ||
| 1136 | |||
| 1137 | static struct clk gfx_cg1_ck = { | ||
| 1138 | .name = "gfx_cg1_ck", | ||
| 1139 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | ||
| 1140 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | ||
| 1141 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, | ||
| 1142 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1143 | .recalc = &followparent_recalc, | ||
| 1144 | }; | ||
| 1145 | |||
| 1146 | static struct clk gfx_cg2_ck = { | ||
| 1147 | .name = "gfx_cg2_ck", | ||
| 1148 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | ||
| 1149 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | ||
| 1150 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, | ||
| 1151 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1152 | .recalc = &followparent_recalc, | ||
| 1153 | }; | ||
| 1154 | |||
| 1155 | /* SGX power domain - 3430ES2 only */ | ||
| 1156 | |||
| 1157 | static const struct clksel_rate sgx_core_rates[] = { | ||
| 1158 | { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 1159 | { .div = 4, .val = 1, .flags = RATE_IN_343X }, | ||
| 1160 | { .div = 6, .val = 2, .flags = RATE_IN_343X }, | ||
| 1161 | { .div = 0 }, | ||
| 1162 | }; | ||
| 1163 | |||
| 1164 | static const struct clksel_rate sgx_96m_rates[] = { | ||
| 1165 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 1166 | { .div = 0 }, | ||
| 1167 | }; | ||
| 1168 | |||
| 1169 | static const struct clksel sgx_clksel[] = { | ||
| 1170 | { .parent = &core_ck, .rates = sgx_core_rates }, | ||
| 1171 | { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, | ||
| 1172 | { .parent = NULL }, | ||
| 1173 | }; | ||
| 1174 | |||
| 1175 | static struct clk sgx_fck = { | ||
| 1176 | .name = "sgx_fck", | ||
| 1177 | .init = &omap2_init_clksel_parent, | ||
| 1178 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), | ||
| 1179 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, | ||
| 1180 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), | ||
| 1181 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, | ||
| 1182 | .clksel = sgx_clksel, | ||
| 1183 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1184 | .recalc = &omap2_clksel_recalc, | ||
| 1185 | }; | ||
| 1186 | |||
| 1187 | static struct clk sgx_ick = { | ||
| 1188 | .name = "sgx_ick", | ||
| 1189 | .parent = &l3_ick, | ||
| 1190 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), | ||
| 1191 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, | ||
| 1192 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1193 | .recalc = &followparent_recalc, | ||
| 1194 | }; | ||
| 1195 | |||
| 1196 | /* CORE power domain */ | ||
| 1197 | |||
| 1198 | static struct clk d2d_26m_fck = { | ||
| 1199 | .name = "d2d_26m_fck", | ||
| 1200 | .parent = &sys_ck, | ||
| 1201 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1202 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, | ||
| 1203 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1204 | .recalc = &followparent_recalc, | ||
| 1205 | }; | ||
| 1206 | |||
| 1207 | static const struct clksel omap343x_gpt_clksel[] = { | ||
| 1208 | { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, | ||
| 1209 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | ||
| 1210 | { .parent = NULL} | ||
| 1211 | }; | ||
| 1212 | |||
| 1213 | static struct clk gpt10_fck = { | ||
| 1214 | .name = "gpt10_fck", | ||
| 1215 | .parent = &sys_ck, | ||
| 1216 | .init = &omap2_init_clksel_parent, | ||
| 1217 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1218 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | ||
| 1219 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
| 1220 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, | ||
| 1221 | .clksel = omap343x_gpt_clksel, | ||
| 1222 | .flags = CLOCK_IN_OMAP343X, | ||
| 1223 | .recalc = &omap2_clksel_recalc, | ||
| 1224 | }; | ||
| 1225 | |||
| 1226 | static struct clk gpt11_fck = { | ||
| 1227 | .name = "gpt11_fck", | ||
| 1228 | .parent = &sys_ck, | ||
| 1229 | .init = &omap2_init_clksel_parent, | ||
| 1230 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1231 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | ||
| 1232 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
| 1233 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, | ||
| 1234 | .clksel = omap343x_gpt_clksel, | ||
| 1235 | .flags = CLOCK_IN_OMAP343X, | ||
| 1236 | .recalc = &omap2_clksel_recalc, | ||
| 1237 | }; | ||
| 1238 | |||
| 1239 | static struct clk cpefuse_fck = { | ||
| 1240 | .name = "cpefuse_fck", | ||
| 1241 | .parent = &sys_ck, | ||
| 1242 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | ||
| 1243 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, | ||
| 1244 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1245 | .recalc = &followparent_recalc, | ||
| 1246 | }; | ||
| 1247 | |||
| 1248 | static struct clk ts_fck = { | ||
| 1249 | .name = "ts_fck", | ||
| 1250 | .parent = &omap_32k_fck, | ||
| 1251 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | ||
| 1252 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, | ||
| 1253 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1254 | .recalc = &followparent_recalc, | ||
| 1255 | }; | ||
| 1256 | |||
| 1257 | static struct clk usbtll_fck = { | ||
| 1258 | .name = "usbtll_fck", | ||
| 1259 | .parent = &omap_120m_fck, | ||
| 1260 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | ||
| 1261 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | ||
| 1262 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1263 | .recalc = &followparent_recalc, | ||
| 1264 | }; | ||
| 1265 | |||
| 1266 | /* CORE 96M FCLK-derived clocks */ | ||
| 1267 | |||
| 1268 | static struct clk core_96m_fck = { | ||
| 1269 | .name = "core_96m_fck", | ||
| 1270 | .parent = &omap_96m_fck, | ||
| 1271 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1272 | PARENT_CONTROLS_CLOCK, | ||
| 1273 | .recalc = &followparent_recalc, | ||
| 1274 | }; | ||
| 1275 | |||
| 1276 | static struct clk mmchs3_fck = { | ||
| 1277 | .name = "mmchs_fck", | ||
| 1278 | .id = 3, | ||
| 1279 | .parent = &core_96m_fck, | ||
| 1280 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1281 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | ||
| 1282 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1283 | .recalc = &followparent_recalc, | ||
| 1284 | }; | ||
| 1285 | |||
| 1286 | static struct clk mmchs2_fck = { | ||
| 1287 | .name = "mmchs_fck", | ||
| 1288 | .id = 2, | ||
| 1289 | .parent = &core_96m_fck, | ||
| 1290 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1291 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | ||
| 1292 | .flags = CLOCK_IN_OMAP343X, | ||
| 1293 | .recalc = &followparent_recalc, | ||
| 1294 | }; | ||
| 1295 | |||
| 1296 | static struct clk mspro_fck = { | ||
| 1297 | .name = "mspro_fck", | ||
| 1298 | .parent = &core_96m_fck, | ||
| 1299 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1300 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | ||
| 1301 | .flags = CLOCK_IN_OMAP343X, | ||
| 1302 | .recalc = &followparent_recalc, | ||
| 1303 | }; | ||
| 1304 | |||
| 1305 | static struct clk mmchs1_fck = { | ||
| 1306 | .name = "mmchs_fck", | ||
| 1307 | .id = 1, | ||
| 1308 | .parent = &core_96m_fck, | ||
| 1309 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1310 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | ||
| 1311 | .flags = CLOCK_IN_OMAP343X, | ||
| 1312 | .recalc = &followparent_recalc, | ||
| 1313 | }; | ||
| 1314 | |||
| 1315 | static struct clk i2c3_fck = { | ||
| 1316 | .name = "i2c_fck", | ||
| 1317 | .id = 3, | ||
| 1318 | .parent = &core_96m_fck, | ||
| 1319 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1320 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | ||
| 1321 | .flags = CLOCK_IN_OMAP343X, | ||
| 1322 | .recalc = &followparent_recalc, | ||
| 1323 | }; | ||
| 1324 | |||
| 1325 | static struct clk i2c2_fck = { | ||
| 1326 | .name = "i2c_fck", | ||
| 1327 | .id = 2, | ||
| 1328 | .parent = &core_96m_fck, | ||
| 1329 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1330 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | ||
| 1331 | .flags = CLOCK_IN_OMAP343X, | ||
| 1332 | .recalc = &followparent_recalc, | ||
| 1333 | }; | ||
| 1334 | |||
| 1335 | static struct clk i2c1_fck = { | ||
| 1336 | .name = "i2c_fck", | ||
| 1337 | .id = 1, | ||
| 1338 | .parent = &core_96m_fck, | ||
| 1339 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1340 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | ||
| 1341 | .flags = CLOCK_IN_OMAP343X, | ||
| 1342 | .recalc = &followparent_recalc, | ||
| 1343 | }; | ||
| 1344 | |||
| 1345 | /* | ||
| 1346 | * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; | ||
| 1347 | * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. | ||
| 1348 | */ | ||
| 1349 | static const struct clksel_rate common_mcbsp_96m_rates[] = { | ||
| 1350 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 1351 | { .div = 0 } | ||
| 1352 | }; | ||
| 1353 | |||
| 1354 | static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { | ||
| 1355 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 1356 | { .div = 0 } | ||
| 1357 | }; | ||
| 1358 | |||
| 1359 | static const struct clksel mcbsp_15_clksel[] = { | ||
| 1360 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, | ||
| 1361 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | ||
| 1362 | { .parent = NULL } | ||
| 1363 | }; | ||
| 1364 | |||
| 1365 | static struct clk mcbsp5_fck = { | ||
| 1366 | .name = "mcbsp5_fck", | ||
| 1367 | .init = &omap2_init_clksel_parent, | ||
| 1368 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1369 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | ||
| 1370 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | ||
| 1371 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, | ||
| 1372 | .clksel = mcbsp_15_clksel, | ||
| 1373 | .flags = CLOCK_IN_OMAP343X, | ||
| 1374 | .recalc = &omap2_clksel_recalc, | ||
| 1375 | }; | ||
| 1376 | |||
| 1377 | static struct clk mcbsp1_fck = { | ||
| 1378 | .name = "mcbsp1_fck", | ||
| 1379 | .init = &omap2_init_clksel_parent, | ||
| 1380 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1381 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | ||
| 1382 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | ||
| 1383 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, | ||
| 1384 | .clksel = mcbsp_15_clksel, | ||
| 1385 | .flags = CLOCK_IN_OMAP343X, | ||
| 1386 | .recalc = &omap2_clksel_recalc, | ||
| 1387 | }; | ||
| 1388 | |||
| 1389 | /* CORE_48M_FCK-derived clocks */ | ||
| 1390 | |||
| 1391 | static struct clk core_48m_fck = { | ||
| 1392 | .name = "core_48m_fck", | ||
| 1393 | .parent = &omap_48m_fck, | ||
| 1394 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1395 | PARENT_CONTROLS_CLOCK, | ||
| 1396 | .recalc = &followparent_recalc, | ||
| 1397 | }; | ||
| 1398 | |||
| 1399 | static struct clk mcspi4_fck = { | ||
| 1400 | .name = "mcspi_fck", | ||
| 1401 | .id = 4, | ||
| 1402 | .parent = &core_48m_fck, | ||
| 1403 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1404 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | ||
| 1405 | .flags = CLOCK_IN_OMAP343X, | ||
| 1406 | .recalc = &followparent_recalc, | ||
| 1407 | }; | ||
| 1408 | |||
| 1409 | static struct clk mcspi3_fck = { | ||
| 1410 | .name = "mcspi_fck", | ||
| 1411 | .id = 3, | ||
| 1412 | .parent = &core_48m_fck, | ||
| 1413 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1414 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | ||
| 1415 | .flags = CLOCK_IN_OMAP343X, | ||
| 1416 | .recalc = &followparent_recalc, | ||
| 1417 | }; | ||
| 1418 | |||
| 1419 | static struct clk mcspi2_fck = { | ||
| 1420 | .name = "mcspi_fck", | ||
| 1421 | .id = 2, | ||
| 1422 | .parent = &core_48m_fck, | ||
| 1423 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1424 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | ||
| 1425 | .flags = CLOCK_IN_OMAP343X, | ||
| 1426 | .recalc = &followparent_recalc, | ||
| 1427 | }; | ||
| 1428 | |||
| 1429 | static struct clk mcspi1_fck = { | ||
| 1430 | .name = "mcspi_fck", | ||
| 1431 | .id = 1, | ||
| 1432 | .parent = &core_48m_fck, | ||
| 1433 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1434 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | ||
| 1435 | .flags = CLOCK_IN_OMAP343X, | ||
| 1436 | .recalc = &followparent_recalc, | ||
| 1437 | }; | ||
| 1438 | |||
| 1439 | static struct clk uart2_fck = { | ||
| 1440 | .name = "uart2_fck", | ||
| 1441 | .parent = &core_48m_fck, | ||
| 1442 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1443 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | ||
| 1444 | .flags = CLOCK_IN_OMAP343X, | ||
| 1445 | .recalc = &followparent_recalc, | ||
| 1446 | }; | ||
| 1447 | |||
| 1448 | static struct clk uart1_fck = { | ||
| 1449 | .name = "uart1_fck", | ||
| 1450 | .parent = &core_48m_fck, | ||
| 1451 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1452 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | ||
| 1453 | .flags = CLOCK_IN_OMAP343X, | ||
| 1454 | .recalc = &followparent_recalc, | ||
| 1455 | }; | ||
| 1456 | |||
| 1457 | static struct clk fshostusb_fck = { | ||
| 1458 | .name = "fshostusb_fck", | ||
| 1459 | .parent = &core_48m_fck, | ||
| 1460 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1461 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | ||
| 1462 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1463 | .recalc = &followparent_recalc, | ||
| 1464 | }; | ||
| 1465 | |||
| 1466 | /* CORE_12M_FCK based clocks */ | ||
| 1467 | |||
| 1468 | static struct clk core_12m_fck = { | ||
| 1469 | .name = "core_12m_fck", | ||
| 1470 | .parent = &omap_12m_fck, | ||
| 1471 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1472 | PARENT_CONTROLS_CLOCK, | ||
| 1473 | .recalc = &followparent_recalc, | ||
| 1474 | }; | ||
| 1475 | |||
| 1476 | static struct clk hdq_fck = { | ||
| 1477 | .name = "hdq_fck", | ||
| 1478 | .parent = &core_12m_fck, | ||
| 1479 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1480 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | ||
| 1481 | .flags = CLOCK_IN_OMAP343X, | ||
| 1482 | .recalc = &followparent_recalc, | ||
| 1483 | }; | ||
| 1484 | |||
| 1485 | /* DPLL3-derived clock */ | ||
| 1486 | |||
| 1487 | static const struct clksel_rate ssi_ssr_corex2_rates[] = { | ||
| 1488 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 1489 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
| 1490 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | ||
| 1491 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
| 1492 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | ||
| 1493 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | ||
| 1494 | { .div = 0 } | ||
| 1495 | }; | ||
| 1496 | |||
| 1497 | static const struct clksel ssi_ssr_clksel[] = { | ||
| 1498 | { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, | ||
| 1499 | { .parent = NULL } | ||
| 1500 | }; | ||
| 1501 | |||
| 1502 | static struct clk ssi_ssr_fck = { | ||
| 1503 | .name = "ssi_ssr_fck", | ||
| 1504 | .init = &omap2_init_clksel_parent, | ||
| 1505 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | ||
| 1506 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | ||
| 1507 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
| 1508 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, | ||
| 1509 | .clksel = ssi_ssr_clksel, | ||
| 1510 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 1511 | .recalc = &omap2_clksel_recalc, | ||
| 1512 | }; | ||
| 1513 | |||
| 1514 | static struct clk ssi_sst_fck = { | ||
| 1515 | .name = "ssi_sst_fck", | ||
| 1516 | .parent = &ssi_ssr_fck, | ||
| 1517 | .fixed_div = 2, | ||
| 1518 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | ||
| 1519 | .recalc = &omap2_fixed_divisor_recalc, | ||
| 1520 | }; | ||
| 1521 | |||
| 1522 | |||
| 1523 | |||
| 1524 | /* CORE_L3_ICK based clocks */ | ||
| 1525 | |||
| 1526 | static struct clk core_l3_ick = { | ||
| 1527 | .name = "core_l3_ick", | ||
| 1528 | .parent = &l3_ick, | ||
| 1529 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1530 | PARENT_CONTROLS_CLOCK, | ||
| 1531 | .recalc = &followparent_recalc, | ||
| 1532 | }; | ||
| 1533 | |||
| 1534 | static struct clk hsotgusb_ick = { | ||
| 1535 | .name = "hsotgusb_ick", | ||
| 1536 | .parent = &core_l3_ick, | ||
| 1537 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1538 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | ||
| 1539 | .flags = CLOCK_IN_OMAP343X, | ||
| 1540 | .recalc = &followparent_recalc, | ||
| 1541 | }; | ||
| 1542 | |||
| 1543 | static struct clk sdrc_ick = { | ||
| 1544 | .name = "sdrc_ick", | ||
| 1545 | .parent = &core_l3_ick, | ||
| 1546 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1547 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, | ||
| 1548 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, | ||
| 1549 | .recalc = &followparent_recalc, | ||
| 1550 | }; | ||
| 1551 | |||
| 1552 | static struct clk gpmc_fck = { | ||
| 1553 | .name = "gpmc_fck", | ||
| 1554 | .parent = &core_l3_ick, | ||
| 1555 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | | ||
| 1556 | ENABLE_ON_INIT, | ||
| 1557 | .recalc = &followparent_recalc, | ||
| 1558 | }; | ||
| 1559 | |||
| 1560 | /* SECURITY_L3_ICK based clocks */ | ||
| 1561 | |||
| 1562 | static struct clk security_l3_ick = { | ||
| 1563 | .name = "security_l3_ick", | ||
| 1564 | .parent = &l3_ick, | ||
| 1565 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1566 | PARENT_CONTROLS_CLOCK, | ||
| 1567 | .recalc = &followparent_recalc, | ||
| 1568 | }; | ||
| 1569 | |||
| 1570 | static struct clk pka_ick = { | ||
| 1571 | .name = "pka_ick", | ||
| 1572 | .parent = &security_l3_ick, | ||
| 1573 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 1574 | .enable_bit = OMAP3430_EN_PKA_SHIFT, | ||
| 1575 | .flags = CLOCK_IN_OMAP343X, | ||
| 1576 | .recalc = &followparent_recalc, | ||
| 1577 | }; | ||
| 1578 | |||
| 1579 | /* CORE_L4_ICK based clocks */ | ||
| 1580 | |||
| 1581 | static struct clk core_l4_ick = { | ||
| 1582 | .name = "core_l4_ick", | ||
| 1583 | .parent = &l4_ick, | ||
| 1584 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1585 | PARENT_CONTROLS_CLOCK, | ||
| 1586 | .recalc = &followparent_recalc, | ||
| 1587 | }; | ||
| 1588 | |||
| 1589 | static struct clk usbtll_ick = { | ||
| 1590 | .name = "usbtll_ick", | ||
| 1591 | .parent = &core_l4_ick, | ||
| 1592 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | ||
| 1593 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | ||
| 1594 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1595 | .recalc = &followparent_recalc, | ||
| 1596 | }; | ||
| 1597 | |||
| 1598 | static struct clk mmchs3_ick = { | ||
| 1599 | .name = "mmchs_ick", | ||
| 1600 | .id = 3, | ||
| 1601 | .parent = &core_l4_ick, | ||
| 1602 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1603 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | ||
| 1604 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1605 | .recalc = &followparent_recalc, | ||
| 1606 | }; | ||
| 1607 | |||
| 1608 | /* Intersystem Communication Registers - chassis mode only */ | ||
| 1609 | static struct clk icr_ick = { | ||
| 1610 | .name = "icr_ick", | ||
| 1611 | .parent = &core_l4_ick, | ||
| 1612 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1613 | .enable_bit = OMAP3430_EN_ICR_SHIFT, | ||
| 1614 | .flags = CLOCK_IN_OMAP343X, | ||
| 1615 | .recalc = &followparent_recalc, | ||
| 1616 | }; | ||
| 1617 | |||
| 1618 | static struct clk aes2_ick = { | ||
| 1619 | .name = "aes2_ick", | ||
| 1620 | .parent = &core_l4_ick, | ||
| 1621 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1622 | .enable_bit = OMAP3430_EN_AES2_SHIFT, | ||
| 1623 | .flags = CLOCK_IN_OMAP343X, | ||
| 1624 | .recalc = &followparent_recalc, | ||
| 1625 | }; | ||
| 1626 | |||
| 1627 | static struct clk sha12_ick = { | ||
| 1628 | .name = "sha12_ick", | ||
| 1629 | .parent = &core_l4_ick, | ||
| 1630 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1631 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, | ||
| 1632 | .flags = CLOCK_IN_OMAP343X, | ||
| 1633 | .recalc = &followparent_recalc, | ||
| 1634 | }; | ||
| 1635 | |||
| 1636 | static struct clk des2_ick = { | ||
| 1637 | .name = "des2_ick", | ||
| 1638 | .parent = &core_l4_ick, | ||
| 1639 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1640 | .enable_bit = OMAP3430_EN_DES2_SHIFT, | ||
| 1641 | .flags = CLOCK_IN_OMAP343X, | ||
| 1642 | .recalc = &followparent_recalc, | ||
| 1643 | }; | ||
| 1644 | |||
| 1645 | static struct clk mmchs2_ick = { | ||
| 1646 | .name = "mmchs_ick", | ||
| 1647 | .id = 2, | ||
| 1648 | .parent = &core_l4_ick, | ||
| 1649 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1650 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | ||
| 1651 | .flags = CLOCK_IN_OMAP343X, | ||
| 1652 | .recalc = &followparent_recalc, | ||
| 1653 | }; | ||
| 1654 | |||
| 1655 | static struct clk mmchs1_ick = { | ||
| 1656 | .name = "mmchs_ick", | ||
| 1657 | .id = 1, | ||
| 1658 | .parent = &core_l4_ick, | ||
| 1659 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1660 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | ||
| 1661 | .flags = CLOCK_IN_OMAP343X, | ||
| 1662 | .recalc = &followparent_recalc, | ||
| 1663 | }; | ||
| 1664 | |||
| 1665 | static struct clk mspro_ick = { | ||
| 1666 | .name = "mspro_ick", | ||
| 1667 | .parent = &core_l4_ick, | ||
| 1668 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1669 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | ||
| 1670 | .flags = CLOCK_IN_OMAP343X, | ||
| 1671 | .recalc = &followparent_recalc, | ||
| 1672 | }; | ||
| 1673 | |||
| 1674 | static struct clk hdq_ick = { | ||
| 1675 | .name = "hdq_ick", | ||
| 1676 | .parent = &core_l4_ick, | ||
| 1677 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1678 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | ||
| 1679 | .flags = CLOCK_IN_OMAP343X, | ||
| 1680 | .recalc = &followparent_recalc, | ||
| 1681 | }; | ||
| 1682 | |||
| 1683 | static struct clk mcspi4_ick = { | ||
| 1684 | .name = "mcspi_ick", | ||
| 1685 | .id = 4, | ||
| 1686 | .parent = &core_l4_ick, | ||
| 1687 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1688 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | ||
| 1689 | .flags = CLOCK_IN_OMAP343X, | ||
| 1690 | .recalc = &followparent_recalc, | ||
| 1691 | }; | ||
| 1692 | |||
| 1693 | static struct clk mcspi3_ick = { | ||
| 1694 | .name = "mcspi_ick", | ||
| 1695 | .id = 3, | ||
| 1696 | .parent = &core_l4_ick, | ||
| 1697 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1698 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | ||
| 1699 | .flags = CLOCK_IN_OMAP343X, | ||
| 1700 | .recalc = &followparent_recalc, | ||
| 1701 | }; | ||
| 1702 | |||
| 1703 | static struct clk mcspi2_ick = { | ||
| 1704 | .name = "mcspi_ick", | ||
| 1705 | .id = 2, | ||
| 1706 | .parent = &core_l4_ick, | ||
| 1707 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1708 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | ||
| 1709 | .flags = CLOCK_IN_OMAP343X, | ||
| 1710 | .recalc = &followparent_recalc, | ||
| 1711 | }; | ||
| 1712 | |||
| 1713 | static struct clk mcspi1_ick = { | ||
| 1714 | .name = "mcspi_ick", | ||
| 1715 | .id = 1, | ||
| 1716 | .parent = &core_l4_ick, | ||
| 1717 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1718 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | ||
| 1719 | .flags = CLOCK_IN_OMAP343X, | ||
| 1720 | .recalc = &followparent_recalc, | ||
| 1721 | }; | ||
| 1722 | |||
| 1723 | static struct clk i2c3_ick = { | ||
| 1724 | .name = "i2c_ick", | ||
| 1725 | .id = 3, | ||
| 1726 | .parent = &core_l4_ick, | ||
| 1727 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1728 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | ||
| 1729 | .flags = CLOCK_IN_OMAP343X, | ||
| 1730 | .recalc = &followparent_recalc, | ||
| 1731 | }; | ||
| 1732 | |||
| 1733 | static struct clk i2c2_ick = { | ||
| 1734 | .name = "i2c_ick", | ||
| 1735 | .id = 2, | ||
| 1736 | .parent = &core_l4_ick, | ||
| 1737 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1738 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | ||
| 1739 | .flags = CLOCK_IN_OMAP343X, | ||
| 1740 | .recalc = &followparent_recalc, | ||
| 1741 | }; | ||
| 1742 | |||
| 1743 | static struct clk i2c1_ick = { | ||
| 1744 | .name = "i2c_ick", | ||
| 1745 | .id = 1, | ||
| 1746 | .parent = &core_l4_ick, | ||
| 1747 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1748 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | ||
| 1749 | .flags = CLOCK_IN_OMAP343X, | ||
| 1750 | .recalc = &followparent_recalc, | ||
| 1751 | }; | ||
| 1752 | |||
| 1753 | static struct clk uart2_ick = { | ||
| 1754 | .name = "uart2_ick", | ||
| 1755 | .parent = &core_l4_ick, | ||
| 1756 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1757 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | ||
| 1758 | .flags = CLOCK_IN_OMAP343X, | ||
| 1759 | .recalc = &followparent_recalc, | ||
| 1760 | }; | ||
| 1761 | |||
| 1762 | static struct clk uart1_ick = { | ||
| 1763 | .name = "uart1_ick", | ||
| 1764 | .parent = &core_l4_ick, | ||
| 1765 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1766 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | ||
| 1767 | .flags = CLOCK_IN_OMAP343X, | ||
| 1768 | .recalc = &followparent_recalc, | ||
| 1769 | }; | ||
| 1770 | |||
| 1771 | static struct clk gpt11_ick = { | ||
| 1772 | .name = "gpt11_ick", | ||
| 1773 | .parent = &core_l4_ick, | ||
| 1774 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1775 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | ||
| 1776 | .flags = CLOCK_IN_OMAP343X, | ||
| 1777 | .recalc = &followparent_recalc, | ||
| 1778 | }; | ||
| 1779 | |||
| 1780 | static struct clk gpt10_ick = { | ||
| 1781 | .name = "gpt10_ick", | ||
| 1782 | .parent = &core_l4_ick, | ||
| 1783 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1784 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | ||
| 1785 | .flags = CLOCK_IN_OMAP343X, | ||
| 1786 | .recalc = &followparent_recalc, | ||
| 1787 | }; | ||
| 1788 | |||
| 1789 | static struct clk mcbsp5_ick = { | ||
| 1790 | .name = "mcbsp5_ick", | ||
| 1791 | .parent = &core_l4_ick, | ||
| 1792 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1793 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | ||
| 1794 | .flags = CLOCK_IN_OMAP343X, | ||
| 1795 | .recalc = &followparent_recalc, | ||
| 1796 | }; | ||
| 1797 | |||
| 1798 | static struct clk mcbsp1_ick = { | ||
| 1799 | .name = "mcbsp1_ick", | ||
| 1800 | .parent = &core_l4_ick, | ||
| 1801 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1802 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | ||
| 1803 | .flags = CLOCK_IN_OMAP343X, | ||
| 1804 | .recalc = &followparent_recalc, | ||
| 1805 | }; | ||
| 1806 | |||
| 1807 | static struct clk fac_ick = { | ||
| 1808 | .name = "fac_ick", | ||
| 1809 | .parent = &core_l4_ick, | ||
| 1810 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1811 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, | ||
| 1812 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1813 | .recalc = &followparent_recalc, | ||
| 1814 | }; | ||
| 1815 | |||
| 1816 | static struct clk mailboxes_ick = { | ||
| 1817 | .name = "mailboxes_ick", | ||
| 1818 | .parent = &core_l4_ick, | ||
| 1819 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1820 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, | ||
| 1821 | .flags = CLOCK_IN_OMAP343X, | ||
| 1822 | .recalc = &followparent_recalc, | ||
| 1823 | }; | ||
| 1824 | |||
| 1825 | static struct clk omapctrl_ick = { | ||
| 1826 | .name = "omapctrl_ick", | ||
| 1827 | .parent = &core_l4_ick, | ||
| 1828 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1829 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, | ||
| 1830 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, | ||
| 1831 | .recalc = &followparent_recalc, | ||
| 1832 | }; | ||
| 1833 | |||
| 1834 | /* SSI_L4_ICK based clocks */ | ||
| 1835 | |||
| 1836 | static struct clk ssi_l4_ick = { | ||
| 1837 | .name = "ssi_l4_ick", | ||
| 1838 | .parent = &l4_ick, | ||
| 1839 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 1840 | .recalc = &followparent_recalc, | ||
| 1841 | }; | ||
| 1842 | |||
| 1843 | static struct clk ssi_ick = { | ||
| 1844 | .name = "ssi_ick", | ||
| 1845 | .parent = &ssi_l4_ick, | ||
| 1846 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1847 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | ||
| 1848 | .flags = CLOCK_IN_OMAP343X, | ||
| 1849 | .recalc = &followparent_recalc, | ||
| 1850 | }; | ||
| 1851 | |||
| 1852 | /* REVISIT: Technically the TRM claims that this is CORE_CLK based, | ||
| 1853 | * but l4_ick makes more sense to me */ | ||
| 1854 | |||
| 1855 | static const struct clksel usb_l4_clksel[] = { | ||
| 1856 | { .parent = &l4_ick, .rates = div2_rates }, | ||
| 1857 | { .parent = NULL }, | ||
| 1858 | }; | ||
| 1859 | |||
| 1860 | static struct clk usb_l4_ick = { | ||
| 1861 | .name = "usb_l4_ick", | ||
| 1862 | .parent = &l4_ick, | ||
| 1863 | .init = &omap2_init_clksel_parent, | ||
| 1864 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | ||
| 1865 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | ||
| 1866 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | ||
| 1867 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, | ||
| 1868 | .clksel = usb_l4_clksel, | ||
| 1869 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1870 | .recalc = &omap2_clksel_recalc, | ||
| 1871 | }; | ||
| 1872 | |||
| 1873 | /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */ | ||
| 1874 | |||
| 1875 | /* SECURITY_L4_ICK2 based clocks */ | ||
| 1876 | |||
| 1877 | static struct clk security_l4_ick2 = { | ||
| 1878 | .name = "security_l4_ick2", | ||
| 1879 | .parent = &l4_ick, | ||
| 1880 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1881 | PARENT_CONTROLS_CLOCK, | ||
| 1882 | .recalc = &followparent_recalc, | ||
| 1883 | }; | ||
| 1884 | |||
| 1885 | static struct clk aes1_ick = { | ||
| 1886 | .name = "aes1_ick", | ||
| 1887 | .parent = &security_l4_ick2, | ||
| 1888 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 1889 | .enable_bit = OMAP3430_EN_AES1_SHIFT, | ||
| 1890 | .flags = CLOCK_IN_OMAP343X, | ||
| 1891 | .recalc = &followparent_recalc, | ||
| 1892 | }; | ||
| 1893 | |||
| 1894 | static struct clk rng_ick = { | ||
| 1895 | .name = "rng_ick", | ||
| 1896 | .parent = &security_l4_ick2, | ||
| 1897 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 1898 | .enable_bit = OMAP3430_EN_RNG_SHIFT, | ||
| 1899 | .flags = CLOCK_IN_OMAP343X, | ||
| 1900 | .recalc = &followparent_recalc, | ||
| 1901 | }; | ||
| 1902 | |||
| 1903 | static struct clk sha11_ick = { | ||
| 1904 | .name = "sha11_ick", | ||
| 1905 | .parent = &security_l4_ick2, | ||
| 1906 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 1907 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, | ||
| 1908 | .flags = CLOCK_IN_OMAP343X, | ||
| 1909 | .recalc = &followparent_recalc, | ||
| 1910 | }; | ||
| 1911 | |||
| 1912 | static struct clk des1_ick = { | ||
| 1913 | .name = "des1_ick", | ||
| 1914 | .parent = &security_l4_ick2, | ||
| 1915 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 1916 | .enable_bit = OMAP3430_EN_DES1_SHIFT, | ||
| 1917 | .flags = CLOCK_IN_OMAP343X, | ||
| 1918 | .recalc = &followparent_recalc, | ||
| 1919 | }; | ||
| 1920 | |||
| 1921 | /* DSS */ | ||
| 1922 | static const struct clksel dss1_alwon_fck_clksel[] = { | ||
| 1923 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 1924 | { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, | ||
| 1925 | { .parent = NULL } | ||
| 1926 | }; | ||
| 1927 | |||
| 1928 | static struct clk dss1_alwon_fck = { | ||
| 1929 | .name = "dss1_alwon_fck", | ||
| 1930 | .parent = &dpll4_m4x2_ck, | ||
| 1931 | .init = &omap2_init_clksel_parent, | ||
| 1932 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | ||
| 1933 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, | ||
| 1934 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 1935 | .clksel_mask = OMAP3430_ST_PERIPH_CLK, | ||
| 1936 | .clksel = dss1_alwon_fck_clksel, | ||
| 1937 | .flags = CLOCK_IN_OMAP343X, | ||
| 1938 | .recalc = &omap2_clksel_recalc, | ||
| 1939 | }; | ||
| 1940 | |||
| 1941 | static struct clk dss_tv_fck = { | ||
| 1942 | .name = "dss_tv_fck", | ||
| 1943 | .parent = &omap_54m_fck, | ||
| 1944 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | ||
| 1945 | .enable_bit = OMAP3430_EN_TV_SHIFT, | ||
| 1946 | .flags = CLOCK_IN_OMAP343X, | ||
| 1947 | .recalc = &followparent_recalc, | ||
| 1948 | }; | ||
| 1949 | |||
| 1950 | static struct clk dss_96m_fck = { | ||
| 1951 | .name = "dss_96m_fck", | ||
| 1952 | .parent = &omap_96m_fck, | ||
| 1953 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | ||
| 1954 | .enable_bit = OMAP3430_EN_TV_SHIFT, | ||
| 1955 | .flags = CLOCK_IN_OMAP343X, | ||
| 1956 | .recalc = &followparent_recalc, | ||
| 1957 | }; | ||
| 1958 | |||
| 1959 | static struct clk dss2_alwon_fck = { | ||
| 1960 | .name = "dss2_alwon_fck", | ||
| 1961 | .parent = &sys_ck, | ||
| 1962 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | ||
| 1963 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, | ||
| 1964 | .flags = CLOCK_IN_OMAP343X, | ||
| 1965 | .recalc = &followparent_recalc, | ||
| 1966 | }; | ||
| 1967 | |||
| 1968 | static struct clk dss_ick = { | ||
| 1969 | /* Handles both L3 and L4 clocks */ | ||
| 1970 | .name = "dss_ick", | ||
| 1971 | .parent = &l4_ick, | ||
| 1972 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | ||
| 1973 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | ||
| 1974 | .flags = CLOCK_IN_OMAP343X, | ||
| 1975 | .recalc = &followparent_recalc, | ||
| 1976 | }; | ||
| 1977 | |||
| 1978 | /* CAM */ | ||
| 1979 | |||
| 1980 | static const struct clksel cam_mclk_clksel[] = { | ||
| 1981 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 1982 | { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, | ||
| 1983 | { .parent = NULL } | ||
| 1984 | }; | ||
| 1985 | |||
| 1986 | static struct clk cam_mclk = { | ||
| 1987 | .name = "cam_mclk", | ||
| 1988 | .parent = &dpll4_m5x2_ck, | ||
| 1989 | .init = &omap2_init_clksel_parent, | ||
| 1990 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 1991 | .clksel_mask = OMAP3430_ST_PERIPH_CLK, | ||
| 1992 | .clksel = cam_mclk_clksel, | ||
| 1993 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | ||
| 1994 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | ||
| 1995 | .flags = CLOCK_IN_OMAP343X, | ||
| 1996 | .recalc = &omap2_clksel_recalc, | ||
| 1997 | }; | ||
| 1998 | |||
| 1999 | static struct clk cam_l3_ick = { | ||
| 2000 | .name = "cam_l3_ick", | ||
| 2001 | .parent = &l3_ick, | ||
| 2002 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), | ||
| 2003 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | ||
| 2004 | .flags = CLOCK_IN_OMAP343X, | ||
| 2005 | .recalc = &followparent_recalc, | ||
| 2006 | }; | ||
| 2007 | |||
| 2008 | static struct clk cam_l4_ick = { | ||
| 2009 | .name = "cam_l4_ick", | ||
| 2010 | .parent = &l4_ick, | ||
| 2011 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), | ||
| 2012 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | ||
| 2013 | .flags = CLOCK_IN_OMAP343X, | ||
| 2014 | .recalc = &followparent_recalc, | ||
| 2015 | }; | ||
| 2016 | |||
| 2017 | /* USBHOST - 3430ES2 only */ | ||
| 2018 | |||
| 2019 | static struct clk usbhost_120m_fck = { | ||
| 2020 | .name = "usbhost_120m_fck", | ||
| 2021 | .parent = &omap_120m_fck, | ||
| 2022 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | ||
| 2023 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, | ||
| 2024 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2025 | .recalc = &followparent_recalc, | ||
| 2026 | }; | ||
| 2027 | |||
| 2028 | static struct clk usbhost_48m_fck = { | ||
| 2029 | .name = "usbhost_48m_fck", | ||
| 2030 | .parent = &omap_48m_fck, | ||
| 2031 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | ||
| 2032 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, | ||
| 2033 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2034 | .recalc = &followparent_recalc, | ||
| 2035 | }; | ||
| 2036 | |||
| 2037 | static struct clk usbhost_l3_ick = { | ||
| 2038 | .name = "usbhost_l3_ick", | ||
| 2039 | .parent = &l3_ick, | ||
| 2040 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), | ||
| 2041 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | ||
| 2042 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2043 | .recalc = &followparent_recalc, | ||
| 2044 | }; | ||
| 2045 | |||
| 2046 | static struct clk usbhost_l4_ick = { | ||
| 2047 | .name = "usbhost_l4_ick", | ||
| 2048 | .parent = &l4_ick, | ||
| 2049 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), | ||
| 2050 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | ||
| 2051 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2052 | .recalc = &followparent_recalc, | ||
| 2053 | }; | ||
| 2054 | |||
| 2055 | static struct clk usbhost_sar_fck = { | ||
| 2056 | .name = "usbhost_sar_fck", | ||
| 2057 | .parent = &osc_sys_ck, | ||
| 2058 | .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), | ||
| 2059 | .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, | ||
| 2060 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2061 | .recalc = &followparent_recalc, | ||
| 2062 | }; | ||
| 2063 | |||
| 2064 | /* WKUP */ | ||
| 2065 | |||
| 2066 | static const struct clksel_rate usim_96m_rates[] = { | ||
| 2067 | { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 2068 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
| 2069 | { .div = 8, .val = 5, .flags = RATE_IN_343X }, | ||
| 2070 | { .div = 10, .val = 6, .flags = RATE_IN_343X }, | ||
| 2071 | { .div = 0 }, | ||
| 2072 | }; | ||
| 2073 | |||
| 2074 | static const struct clksel_rate usim_120m_rates[] = { | ||
| 2075 | { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 2076 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | ||
| 2077 | { .div = 16, .val = 9, .flags = RATE_IN_343X }, | ||
| 2078 | { .div = 20, .val = 10, .flags = RATE_IN_343X }, | ||
| 2079 | { .div = 0 }, | ||
| 2080 | }; | ||
| 2081 | |||
| 2082 | static const struct clksel usim_clksel[] = { | ||
| 2083 | { .parent = &omap_96m_fck, .rates = usim_96m_rates }, | ||
| 2084 | { .parent = &omap_120m_fck, .rates = usim_120m_rates }, | ||
| 2085 | { .parent = &sys_ck, .rates = div2_rates }, | ||
| 2086 | { .parent = NULL }, | ||
| 2087 | }; | ||
| 2088 | |||
| 2089 | /* 3430ES2 only */ | ||
| 2090 | static struct clk usim_fck = { | ||
| 2091 | .name = "usim_fck", | ||
| 2092 | .init = &omap2_init_clksel_parent, | ||
| 2093 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
| 2094 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | ||
| 2095 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | ||
| 2096 | .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, | ||
| 2097 | .clksel = usim_clksel, | ||
| 2098 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2099 | .recalc = &omap2_clksel_recalc, | ||
| 2100 | }; | ||
| 2101 | |||
| 2102 | static struct clk gpt1_fck = { | ||
| 2103 | .name = "gpt1_fck", | ||
| 2104 | .init = &omap2_init_clksel_parent, | ||
| 2105 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
| 2106 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | ||
| 2107 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | ||
| 2108 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, | ||
| 2109 | .clksel = omap343x_gpt_clksel, | ||
| 2110 | .flags = CLOCK_IN_OMAP343X, | ||
| 2111 | .recalc = &omap2_clksel_recalc, | ||
| 2112 | }; | ||
| 2113 | |||
| 2114 | static struct clk wkup_32k_fck = { | ||
| 2115 | .name = "wkup_32k_fck", | ||
| 2116 | .parent = &omap_32k_fck, | ||
| 2117 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2118 | .recalc = &followparent_recalc, | ||
| 2119 | }; | ||
| 2120 | |||
| 2121 | static struct clk gpio1_fck = { | ||
| 2122 | .name = "gpio1_fck", | ||
| 2123 | .parent = &wkup_32k_fck, | ||
| 2124 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
| 2125 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | ||
| 2126 | .flags = CLOCK_IN_OMAP343X, | ||
| 2127 | .recalc = &followparent_recalc, | ||
| 2128 | }; | ||
| 2129 | |||
| 2130 | static struct clk wdt2_fck = { | ||
| 2131 | .name = "wdt2_fck", | ||
| 2132 | .parent = &wkup_32k_fck, | ||
| 2133 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
| 2134 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | ||
| 2135 | .flags = CLOCK_IN_OMAP343X, | ||
| 2136 | .recalc = &followparent_recalc, | ||
| 2137 | }; | ||
| 2138 | |||
| 2139 | static struct clk wkup_l4_ick = { | ||
| 2140 | .name = "wkup_l4_ick", | ||
| 2141 | .parent = &sys_ck, | ||
| 2142 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2143 | .recalc = &followparent_recalc, | ||
| 2144 | }; | ||
| 2145 | |||
| 2146 | /* 3430ES2 only */ | ||
| 2147 | /* Never specifically named in the TRM, so we have to infer a likely name */ | ||
| 2148 | static struct clk usim_ick = { | ||
| 2149 | .name = "usim_ick", | ||
| 2150 | .parent = &wkup_l4_ick, | ||
| 2151 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 2152 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | ||
| 2153 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2154 | .recalc = &followparent_recalc, | ||
| 2155 | }; | ||
| 2156 | |||
| 2157 | static struct clk wdt2_ick = { | ||
| 2158 | .name = "wdt2_ick", | ||
| 2159 | .parent = &wkup_l4_ick, | ||
| 2160 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 2161 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | ||
| 2162 | .flags = CLOCK_IN_OMAP343X, | ||
| 2163 | .recalc = &followparent_recalc, | ||
| 2164 | }; | ||
| 2165 | |||
| 2166 | static struct clk wdt1_ick = { | ||
| 2167 | .name = "wdt1_ick", | ||
| 2168 | .parent = &wkup_l4_ick, | ||
| 2169 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 2170 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, | ||
| 2171 | .flags = CLOCK_IN_OMAP343X, | ||
| 2172 | .recalc = &followparent_recalc, | ||
| 2173 | }; | ||
| 2174 | |||
| 2175 | static struct clk gpio1_ick = { | ||
| 2176 | .name = "gpio1_ick", | ||
| 2177 | .parent = &wkup_l4_ick, | ||
| 2178 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 2179 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | ||
| 2180 | .flags = CLOCK_IN_OMAP343X, | ||
| 2181 | .recalc = &followparent_recalc, | ||
| 2182 | }; | ||
| 2183 | |||
| 2184 | static struct clk omap_32ksync_ick = { | ||
| 2185 | .name = "omap_32ksync_ick", | ||
| 2186 | .parent = &wkup_l4_ick, | ||
| 2187 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 2188 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, | ||
| 2189 | .flags = CLOCK_IN_OMAP343X, | ||
| 2190 | .recalc = &followparent_recalc, | ||
| 2191 | }; | ||
| 2192 | |||
| 2193 | static struct clk gpt12_ick = { | ||
| 2194 | .name = "gpt12_ick", | ||
| 2195 | .parent = &wkup_l4_ick, | ||
| 2196 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 2197 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, | ||
| 2198 | .flags = CLOCK_IN_OMAP343X, | ||
| 2199 | .recalc = &followparent_recalc, | ||
| 2200 | }; | ||
| 2201 | |||
| 2202 | static struct clk gpt1_ick = { | ||
| 2203 | .name = "gpt1_ick", | ||
| 2204 | .parent = &wkup_l4_ick, | ||
| 2205 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | ||
| 2206 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | ||
| 2207 | .flags = CLOCK_IN_OMAP343X, | ||
| 2208 | .recalc = &followparent_recalc, | ||
| 2209 | }; | ||
| 2210 | |||
| 2211 | |||
| 2212 | |||
| 2213 | /* PER clock domain */ | ||
| 2214 | |||
| 2215 | static struct clk per_96m_fck = { | ||
| 2216 | .name = "per_96m_fck", | ||
| 2217 | .parent = &omap_96m_alwon_fck, | ||
| 2218 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 2219 | PARENT_CONTROLS_CLOCK, | ||
| 2220 | .recalc = &followparent_recalc, | ||
| 2221 | }; | ||
| 2222 | |||
| 2223 | static struct clk per_48m_fck = { | ||
| 2224 | .name = "per_48m_fck", | ||
| 2225 | .parent = &omap_48m_fck, | ||
| 2226 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 2227 | PARENT_CONTROLS_CLOCK, | ||
| 2228 | .recalc = &followparent_recalc, | ||
| 2229 | }; | ||
| 2230 | |||
| 2231 | static struct clk uart3_fck = { | ||
| 2232 | .name = "uart3_fck", | ||
| 2233 | .parent = &per_48m_fck, | ||
| 2234 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2235 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | ||
| 2236 | .flags = CLOCK_IN_OMAP343X, | ||
| 2237 | .recalc = &followparent_recalc, | ||
| 2238 | }; | ||
| 2239 | |||
| 2240 | static struct clk gpt2_fck = { | ||
| 2241 | .name = "gpt2_fck", | ||
| 2242 | .init = &omap2_init_clksel_parent, | ||
| 2243 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2244 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | ||
| 2245 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
| 2246 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, | ||
| 2247 | .clksel = omap343x_gpt_clksel, | ||
| 2248 | .flags = CLOCK_IN_OMAP343X, | ||
| 2249 | .recalc = &omap2_clksel_recalc, | ||
| 2250 | }; | ||
| 2251 | |||
| 2252 | static struct clk gpt3_fck = { | ||
| 2253 | .name = "gpt3_fck", | ||
| 2254 | .init = &omap2_init_clksel_parent, | ||
| 2255 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2256 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | ||
| 2257 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
| 2258 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, | ||
| 2259 | .clksel = omap343x_gpt_clksel, | ||
| 2260 | .flags = CLOCK_IN_OMAP343X, | ||
| 2261 | .recalc = &omap2_clksel_recalc, | ||
| 2262 | }; | ||
| 2263 | |||
| 2264 | static struct clk gpt4_fck = { | ||
| 2265 | .name = "gpt4_fck", | ||
| 2266 | .init = &omap2_init_clksel_parent, | ||
| 2267 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2268 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | ||
| 2269 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
| 2270 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, | ||
| 2271 | .clksel = omap343x_gpt_clksel, | ||
| 2272 | .flags = CLOCK_IN_OMAP343X, | ||
| 2273 | .recalc = &omap2_clksel_recalc, | ||
| 2274 | }; | ||
| 2275 | |||
| 2276 | static struct clk gpt5_fck = { | ||
| 2277 | .name = "gpt5_fck", | ||
| 2278 | .init = &omap2_init_clksel_parent, | ||
| 2279 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2280 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | ||
| 2281 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
| 2282 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, | ||
| 2283 | .clksel = omap343x_gpt_clksel, | ||
| 2284 | .flags = CLOCK_IN_OMAP343X, | ||
| 2285 | .recalc = &omap2_clksel_recalc, | ||
| 2286 | }; | ||
| 2287 | |||
| 2288 | static struct clk gpt6_fck = { | ||
| 2289 | .name = "gpt6_fck", | ||
| 2290 | .init = &omap2_init_clksel_parent, | ||
| 2291 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2292 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | ||
| 2293 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
| 2294 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, | ||
| 2295 | .clksel = omap343x_gpt_clksel, | ||
| 2296 | .flags = CLOCK_IN_OMAP343X, | ||
| 2297 | .recalc = &omap2_clksel_recalc, | ||
| 2298 | }; | ||
| 2299 | |||
| 2300 | static struct clk gpt7_fck = { | ||
| 2301 | .name = "gpt7_fck", | ||
| 2302 | .init = &omap2_init_clksel_parent, | ||
| 2303 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2304 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | ||
| 2305 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
| 2306 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, | ||
| 2307 | .clksel = omap343x_gpt_clksel, | ||
| 2308 | .flags = CLOCK_IN_OMAP343X, | ||
| 2309 | .recalc = &omap2_clksel_recalc, | ||
| 2310 | }; | ||
| 2311 | |||
| 2312 | static struct clk gpt8_fck = { | ||
| 2313 | .name = "gpt8_fck", | ||
| 2314 | .init = &omap2_init_clksel_parent, | ||
| 2315 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2316 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | ||
| 2317 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
| 2318 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, | ||
| 2319 | .clksel = omap343x_gpt_clksel, | ||
| 2320 | .flags = CLOCK_IN_OMAP343X, | ||
| 2321 | .recalc = &omap2_clksel_recalc, | ||
| 2322 | }; | ||
| 2323 | |||
| 2324 | static struct clk gpt9_fck = { | ||
| 2325 | .name = "gpt9_fck", | ||
| 2326 | .init = &omap2_init_clksel_parent, | ||
| 2327 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2328 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | ||
| 2329 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | ||
| 2330 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, | ||
| 2331 | .clksel = omap343x_gpt_clksel, | ||
| 2332 | .flags = CLOCK_IN_OMAP343X, | ||
| 2333 | .recalc = &omap2_clksel_recalc, | ||
| 2334 | }; | ||
| 2335 | |||
| 2336 | static struct clk per_32k_alwon_fck = { | ||
| 2337 | .name = "per_32k_alwon_fck", | ||
| 2338 | .parent = &omap_32k_fck, | ||
| 2339 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2340 | .recalc = &followparent_recalc, | ||
| 2341 | }; | ||
| 2342 | |||
| 2343 | static struct clk gpio6_fck = { | ||
| 2344 | .name = "gpio6_fck", | ||
| 2345 | .parent = &per_32k_alwon_fck, | ||
| 2346 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2347 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | ||
| 2348 | .flags = CLOCK_IN_OMAP343X, | ||
| 2349 | .recalc = &followparent_recalc, | ||
| 2350 | }; | ||
| 2351 | |||
| 2352 | static struct clk gpio5_fck = { | ||
| 2353 | .name = "gpio5_fck", | ||
| 2354 | .parent = &per_32k_alwon_fck, | ||
| 2355 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2356 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | ||
| 2357 | .flags = CLOCK_IN_OMAP343X, | ||
| 2358 | .recalc = &followparent_recalc, | ||
| 2359 | }; | ||
| 2360 | |||
| 2361 | static struct clk gpio4_fck = { | ||
| 2362 | .name = "gpio4_fck", | ||
| 2363 | .parent = &per_32k_alwon_fck, | ||
| 2364 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2365 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | ||
| 2366 | .flags = CLOCK_IN_OMAP343X, | ||
| 2367 | .recalc = &followparent_recalc, | ||
| 2368 | }; | ||
| 2369 | |||
| 2370 | static struct clk gpio3_fck = { | ||
| 2371 | .name = "gpio3_fck", | ||
| 2372 | .parent = &per_32k_alwon_fck, | ||
| 2373 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2374 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | ||
| 2375 | .flags = CLOCK_IN_OMAP343X, | ||
| 2376 | .recalc = &followparent_recalc, | ||
| 2377 | }; | ||
| 2378 | |||
| 2379 | static struct clk gpio2_fck = { | ||
| 2380 | .name = "gpio2_fck", | ||
| 2381 | .parent = &per_32k_alwon_fck, | ||
| 2382 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2383 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | ||
| 2384 | .flags = CLOCK_IN_OMAP343X, | ||
| 2385 | .recalc = &followparent_recalc, | ||
| 2386 | }; | ||
| 2387 | |||
| 2388 | static struct clk wdt3_fck = { | ||
| 2389 | .name = "wdt3_fck", | ||
| 2390 | .parent = &per_32k_alwon_fck, | ||
| 2391 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2392 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | ||
| 2393 | .flags = CLOCK_IN_OMAP343X, | ||
| 2394 | .recalc = &followparent_recalc, | ||
| 2395 | }; | ||
| 2396 | |||
| 2397 | static struct clk per_l4_ick = { | ||
| 2398 | .name = "per_l4_ick", | ||
| 2399 | .parent = &l4_ick, | ||
| 2400 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 2401 | PARENT_CONTROLS_CLOCK, | ||
| 2402 | .recalc = &followparent_recalc, | ||
| 2403 | }; | ||
| 2404 | |||
| 2405 | static struct clk gpio6_ick = { | ||
| 2406 | .name = "gpio6_ick", | ||
| 2407 | .parent = &per_l4_ick, | ||
| 2408 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2409 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | ||
| 2410 | .flags = CLOCK_IN_OMAP343X, | ||
| 2411 | .recalc = &followparent_recalc, | ||
| 2412 | }; | ||
| 2413 | |||
| 2414 | static struct clk gpio5_ick = { | ||
| 2415 | .name = "gpio5_ick", | ||
| 2416 | .parent = &per_l4_ick, | ||
| 2417 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2418 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | ||
| 2419 | .flags = CLOCK_IN_OMAP343X, | ||
| 2420 | .recalc = &followparent_recalc, | ||
| 2421 | }; | ||
| 2422 | |||
| 2423 | static struct clk gpio4_ick = { | ||
| 2424 | .name = "gpio4_ick", | ||
| 2425 | .parent = &per_l4_ick, | ||
| 2426 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2427 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | ||
| 2428 | .flags = CLOCK_IN_OMAP343X, | ||
| 2429 | .recalc = &followparent_recalc, | ||
| 2430 | }; | ||
| 2431 | |||
| 2432 | static struct clk gpio3_ick = { | ||
| 2433 | .name = "gpio3_ick", | ||
| 2434 | .parent = &per_l4_ick, | ||
| 2435 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2436 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | ||
| 2437 | .flags = CLOCK_IN_OMAP343X, | ||
| 2438 | .recalc = &followparent_recalc, | ||
| 2439 | }; | ||
| 2440 | |||
| 2441 | static struct clk gpio2_ick = { | ||
| 2442 | .name = "gpio2_ick", | ||
| 2443 | .parent = &per_l4_ick, | ||
| 2444 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2445 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | ||
| 2446 | .flags = CLOCK_IN_OMAP343X, | ||
| 2447 | .recalc = &followparent_recalc, | ||
| 2448 | }; | ||
| 2449 | |||
| 2450 | static struct clk wdt3_ick = { | ||
| 2451 | .name = "wdt3_ick", | ||
| 2452 | .parent = &per_l4_ick, | ||
| 2453 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2454 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | ||
| 2455 | .flags = CLOCK_IN_OMAP343X, | ||
| 2456 | .recalc = &followparent_recalc, | ||
| 2457 | }; | ||
| 2458 | |||
| 2459 | static struct clk uart3_ick = { | ||
| 2460 | .name = "uart3_ick", | ||
| 2461 | .parent = &per_l4_ick, | ||
| 2462 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2463 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | ||
| 2464 | .flags = CLOCK_IN_OMAP343X, | ||
| 2465 | .recalc = &followparent_recalc, | ||
| 2466 | }; | ||
| 2467 | |||
| 2468 | static struct clk gpt9_ick = { | ||
| 2469 | .name = "gpt9_ick", | ||
| 2470 | .parent = &per_l4_ick, | ||
| 2471 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2472 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | ||
| 2473 | .flags = CLOCK_IN_OMAP343X, | ||
| 2474 | .recalc = &followparent_recalc, | ||
| 2475 | }; | ||
| 2476 | |||
| 2477 | static struct clk gpt8_ick = { | ||
| 2478 | .name = "gpt8_ick", | ||
| 2479 | .parent = &per_l4_ick, | ||
| 2480 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2481 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | ||
| 2482 | .flags = CLOCK_IN_OMAP343X, | ||
| 2483 | .recalc = &followparent_recalc, | ||
| 2484 | }; | ||
| 2485 | |||
| 2486 | static struct clk gpt7_ick = { | ||
| 2487 | .name = "gpt7_ick", | ||
| 2488 | .parent = &per_l4_ick, | ||
| 2489 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2490 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | ||
| 2491 | .flags = CLOCK_IN_OMAP343X, | ||
| 2492 | .recalc = &followparent_recalc, | ||
| 2493 | }; | ||
| 2494 | |||
| 2495 | static struct clk gpt6_ick = { | ||
| 2496 | .name = "gpt6_ick", | ||
| 2497 | .parent = &per_l4_ick, | ||
| 2498 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2499 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | ||
| 2500 | .flags = CLOCK_IN_OMAP343X, | ||
| 2501 | .recalc = &followparent_recalc, | ||
| 2502 | }; | ||
| 2503 | |||
| 2504 | static struct clk gpt5_ick = { | ||
| 2505 | .name = "gpt5_ick", | ||
| 2506 | .parent = &per_l4_ick, | ||
| 2507 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2508 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | ||
| 2509 | .flags = CLOCK_IN_OMAP343X, | ||
| 2510 | .recalc = &followparent_recalc, | ||
| 2511 | }; | ||
| 2512 | |||
| 2513 | static struct clk gpt4_ick = { | ||
| 2514 | .name = "gpt4_ick", | ||
| 2515 | .parent = &per_l4_ick, | ||
| 2516 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2517 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | ||
| 2518 | .flags = CLOCK_IN_OMAP343X, | ||
| 2519 | .recalc = &followparent_recalc, | ||
| 2520 | }; | ||
| 2521 | |||
| 2522 | static struct clk gpt3_ick = { | ||
| 2523 | .name = "gpt3_ick", | ||
| 2524 | .parent = &per_l4_ick, | ||
| 2525 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2526 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | ||
| 2527 | .flags = CLOCK_IN_OMAP343X, | ||
| 2528 | .recalc = &followparent_recalc, | ||
| 2529 | }; | ||
| 2530 | |||
| 2531 | static struct clk gpt2_ick = { | ||
| 2532 | .name = "gpt2_ick", | ||
| 2533 | .parent = &per_l4_ick, | ||
| 2534 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2535 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | ||
| 2536 | .flags = CLOCK_IN_OMAP343X, | ||
| 2537 | .recalc = &followparent_recalc, | ||
| 2538 | }; | ||
| 2539 | |||
| 2540 | static struct clk mcbsp2_ick = { | ||
| 2541 | .name = "mcbsp2_ick", | ||
| 2542 | .parent = &per_l4_ick, | ||
| 2543 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2544 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | ||
| 2545 | .flags = CLOCK_IN_OMAP343X, | ||
| 2546 | .recalc = &followparent_recalc, | ||
| 2547 | }; | ||
| 2548 | |||
| 2549 | static struct clk mcbsp3_ick = { | ||
| 2550 | .name = "mcbsp3_ick", | ||
| 2551 | .parent = &per_l4_ick, | ||
| 2552 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2553 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | ||
| 2554 | .flags = CLOCK_IN_OMAP343X, | ||
| 2555 | .recalc = &followparent_recalc, | ||
| 2556 | }; | ||
| 2557 | |||
| 2558 | static struct clk mcbsp4_ick = { | ||
| 2559 | .name = "mcbsp4_ick", | ||
| 2560 | .parent = &per_l4_ick, | ||
| 2561 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | ||
| 2562 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | ||
| 2563 | .flags = CLOCK_IN_OMAP343X, | ||
| 2564 | .recalc = &followparent_recalc, | ||
| 2565 | }; | ||
| 2566 | |||
| 2567 | static const struct clksel mcbsp_234_clksel[] = { | ||
| 2568 | { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, | ||
| 2569 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | ||
| 2570 | { .parent = NULL } | ||
| 2571 | }; | ||
| 2572 | |||
| 2573 | static struct clk mcbsp2_fck = { | ||
| 2574 | .name = "mcbsp2_fck", | ||
| 2575 | .init = &omap2_init_clksel_parent, | ||
| 2576 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2577 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | ||
| 2578 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | ||
| 2579 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, | ||
| 2580 | .clksel = mcbsp_234_clksel, | ||
| 2581 | .flags = CLOCK_IN_OMAP343X, | ||
| 2582 | .recalc = &omap2_clksel_recalc, | ||
| 2583 | }; | ||
| 2584 | |||
| 2585 | static struct clk mcbsp3_fck = { | ||
| 2586 | .name = "mcbsp3_fck", | ||
| 2587 | .init = &omap2_init_clksel_parent, | ||
| 2588 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2589 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | ||
| 2590 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | ||
| 2591 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, | ||
| 2592 | .clksel = mcbsp_234_clksel, | ||
| 2593 | .flags = CLOCK_IN_OMAP343X, | ||
| 2594 | .recalc = &omap2_clksel_recalc, | ||
| 2595 | }; | ||
| 2596 | |||
| 2597 | static struct clk mcbsp4_fck = { | ||
| 2598 | .name = "mcbsp4_fck", | ||
| 2599 | .init = &omap2_init_clksel_parent, | ||
| 2600 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | ||
| 2601 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | ||
| 2602 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | ||
| 2603 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, | ||
| 2604 | .clksel = mcbsp_234_clksel, | ||
| 2605 | .flags = CLOCK_IN_OMAP343X, | ||
| 2606 | .recalc = &omap2_clksel_recalc, | ||
| 2607 | }; | ||
| 2608 | |||
| 2609 | /* EMU clocks */ | ||
| 2610 | |||
| 2611 | /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ | ||
| 2612 | |||
| 2613 | static const struct clksel_rate emu_src_sys_rates[] = { | ||
| 2614 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 2615 | { .div = 0 }, | ||
| 2616 | }; | ||
| 2617 | |||
| 2618 | static const struct clksel_rate emu_src_core_rates[] = { | ||
| 2619 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 2620 | { .div = 0 }, | ||
| 2621 | }; | ||
| 2622 | |||
| 2623 | static const struct clksel_rate emu_src_per_rates[] = { | ||
| 2624 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 2625 | { .div = 0 }, | ||
| 2626 | }; | ||
| 2627 | |||
| 2628 | static const struct clksel_rate emu_src_mpu_rates[] = { | ||
| 2629 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 2630 | { .div = 0 }, | ||
| 2631 | }; | ||
| 2632 | |||
| 2633 | static const struct clksel emu_src_clksel[] = { | ||
| 2634 | { .parent = &sys_ck, .rates = emu_src_sys_rates }, | ||
| 2635 | { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, | ||
| 2636 | { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, | ||
| 2637 | { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, | ||
| 2638 | { .parent = NULL }, | ||
| 2639 | }; | ||
| 2640 | |||
| 2641 | /* | ||
| 2642 | * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only | ||
| 2643 | * to switch the source of some of the EMU clocks. | ||
| 2644 | * XXX Are there CLKEN bits for these EMU clks? | ||
| 2645 | */ | ||
| 2646 | static struct clk emu_src_ck = { | ||
| 2647 | .name = "emu_src_ck", | ||
| 2648 | .init = &omap2_init_clksel_parent, | ||
| 2649 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
| 2650 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, | ||
| 2651 | .clksel = emu_src_clksel, | ||
| 2652 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2653 | .recalc = &omap2_clksel_recalc, | ||
| 2654 | }; | ||
| 2655 | |||
| 2656 | static const struct clksel_rate pclk_emu_rates[] = { | ||
| 2657 | { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 2658 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | ||
| 2659 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
| 2660 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | ||
| 2661 | { .div = 0 }, | ||
| 2662 | }; | ||
| 2663 | |||
| 2664 | static const struct clksel pclk_emu_clksel[] = { | ||
| 2665 | { .parent = &emu_src_ck, .rates = pclk_emu_rates }, | ||
| 2666 | { .parent = NULL }, | ||
| 2667 | }; | ||
| 2668 | |||
| 2669 | static struct clk pclk_fck = { | ||
| 2670 | .name = "pclk_fck", | ||
| 2671 | .init = &omap2_init_clksel_parent, | ||
| 2672 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
| 2673 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, | ||
| 2674 | .clksel = pclk_emu_clksel, | ||
| 2675 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2676 | .recalc = &omap2_clksel_recalc, | ||
| 2677 | }; | ||
| 2678 | |||
| 2679 | static const struct clksel_rate pclkx2_emu_rates[] = { | ||
| 2680 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 2681 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
| 2682 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | ||
| 2683 | { .div = 0 }, | ||
| 2684 | }; | ||
| 2685 | |||
| 2686 | static const struct clksel pclkx2_emu_clksel[] = { | ||
| 2687 | { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, | ||
| 2688 | { .parent = NULL }, | ||
| 2689 | }; | ||
| 2690 | |||
| 2691 | static struct clk pclkx2_fck = { | ||
| 2692 | .name = "pclkx2_fck", | ||
| 2693 | .init = &omap2_init_clksel_parent, | ||
| 2694 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
| 2695 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, | ||
| 2696 | .clksel = pclkx2_emu_clksel, | ||
| 2697 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2698 | .recalc = &omap2_clksel_recalc, | ||
| 2699 | }; | ||
| 2700 | |||
| 2701 | static const struct clksel atclk_emu_clksel[] = { | ||
| 2702 | { .parent = &emu_src_ck, .rates = div2_rates }, | ||
| 2703 | { .parent = NULL }, | ||
| 2704 | }; | ||
| 2705 | |||
| 2706 | static struct clk atclk_fck = { | ||
| 2707 | .name = "atclk_fck", | ||
| 2708 | .init = &omap2_init_clksel_parent, | ||
| 2709 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
| 2710 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, | ||
| 2711 | .clksel = atclk_emu_clksel, | ||
| 2712 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2713 | .recalc = &omap2_clksel_recalc, | ||
| 2714 | }; | ||
| 2715 | |||
| 2716 | static struct clk traceclk_src_fck = { | ||
| 2717 | .name = "traceclk_src_fck", | ||
| 2718 | .init = &omap2_init_clksel_parent, | ||
| 2719 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
| 2720 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, | ||
| 2721 | .clksel = emu_src_clksel, | ||
| 2722 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2723 | .recalc = &omap2_clksel_recalc, | ||
| 2724 | }; | ||
| 2725 | |||
| 2726 | static const struct clksel_rate traceclk_rates[] = { | ||
| 2727 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 2728 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
| 2729 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
| 2730 | { .div = 0 }, | ||
| 2731 | }; | ||
| 2732 | |||
| 2733 | static const struct clksel traceclk_clksel[] = { | ||
| 2734 | { .parent = &traceclk_src_fck, .rates = traceclk_rates }, | ||
| 2735 | { .parent = NULL }, | ||
| 2736 | }; | ||
| 2737 | |||
| 2738 | static struct clk traceclk_fck = { | ||
| 2739 | .name = "traceclk_fck", | ||
| 2740 | .init = &omap2_init_clksel_parent, | ||
| 2741 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
| 2742 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, | ||
| 2743 | .clksel = traceclk_clksel, | ||
| 2744 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | ||
| 2745 | .recalc = &omap2_clksel_recalc, | ||
| 2746 | }; | ||
| 2747 | |||
| 2748 | /* SR clocks */ | ||
| 2749 | |||
| 2750 | /* SmartReflex fclk (VDD1) */ | ||
| 2751 | static struct clk sr1_fck = { | ||
| 2752 | .name = "sr1_fck", | ||
| 2753 | .parent = &sys_ck, | ||
| 2754 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
| 2755 | .enable_bit = OMAP3430_EN_SR1_SHIFT, | ||
| 2756 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 2757 | .recalc = &followparent_recalc, | ||
| 2758 | }; | ||
| 2759 | |||
| 2760 | /* SmartReflex fclk (VDD2) */ | ||
| 2761 | static struct clk sr2_fck = { | ||
| 2762 | .name = "sr2_fck", | ||
| 2763 | .parent = &sys_ck, | ||
| 2764 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | ||
| 2765 | .enable_bit = OMAP3430_EN_SR2_SHIFT, | ||
| 2766 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 2767 | .recalc = &followparent_recalc, | ||
| 2768 | }; | ||
| 2769 | |||
| 2770 | static struct clk sr_l4_ick = { | ||
| 2771 | .name = "sr_l4_ick", | ||
| 2772 | .parent = &l4_ick, | ||
| 2773 | .flags = CLOCK_IN_OMAP343X, | ||
| 2774 | .recalc = &followparent_recalc, | ||
| 2775 | }; | ||
| 2776 | |||
| 2777 | /* SECURE_32K_FCK clocks */ | ||
| 2778 | |||
| 2779 | static struct clk gpt12_fck = { | ||
| 2780 | .name = "gpt12_fck", | ||
| 2781 | .parent = &secure_32k_fck, | ||
| 2782 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | ||
| 2783 | .recalc = &followparent_recalc, | ||
| 2784 | }; | ||
| 2785 | |||
| 2786 | static struct clk wdt1_fck = { | ||
| 2787 | .name = "wdt1_fck", | ||
| 2788 | .parent = &secure_32k_fck, | ||
| 2789 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | ||
| 2790 | .recalc = &followparent_recalc, | ||
| 2791 | }; | ||
| 2792 | |||
| 2793 | static struct clk *onchip_34xx_clks[] __initdata = { | ||
| 2794 | &omap_32k_fck, | ||
| 2795 | &virt_12m_ck, | ||
| 2796 | &virt_13m_ck, | ||
| 2797 | &virt_16_8m_ck, | ||
| 2798 | &virt_19_2m_ck, | ||
| 2799 | &virt_26m_ck, | ||
| 2800 | &virt_38_4m_ck, | ||
| 2801 | &osc_sys_ck, | ||
| 2802 | &sys_ck, | ||
| 2803 | &sys_altclk, | ||
| 2804 | &mcbsp_clks, | ||
| 2805 | &sys_clkout1, | ||
| 2806 | &dpll1_ck, | ||
| 2807 | &dpll1_x2_ck, | ||
| 2808 | &dpll1_x2m2_ck, | ||
| 2809 | &dpll2_ck, | ||
| 2810 | &dpll2_m2_ck, | ||
| 2811 | &dpll3_ck, | ||
| 2812 | &core_ck, | ||
| 2813 | &dpll3_x2_ck, | ||
| 2814 | &dpll3_m2_ck, | ||
| 2815 | &dpll3_m2x2_ck, | ||
| 2816 | &dpll3_m3_ck, | ||
| 2817 | &dpll3_m3x2_ck, | ||
| 2818 | &emu_core_alwon_ck, | ||
| 2819 | &dpll4_ck, | ||
| 2820 | &dpll4_x2_ck, | ||
| 2821 | &omap_96m_alwon_fck, | ||
| 2822 | &omap_96m_fck, | ||
| 2823 | &cm_96m_fck, | ||
| 2824 | &virt_omap_54m_fck, | ||
| 2825 | &omap_54m_fck, | ||
| 2826 | &omap_48m_fck, | ||
| 2827 | &omap_12m_fck, | ||
| 2828 | &dpll4_m2_ck, | ||
| 2829 | &dpll4_m2x2_ck, | ||
| 2830 | &dpll4_m3_ck, | ||
| 2831 | &dpll4_m3x2_ck, | ||
| 2832 | &dpll4_m4_ck, | ||
| 2833 | &dpll4_m4x2_ck, | ||
| 2834 | &dpll4_m5_ck, | ||
| 2835 | &dpll4_m5x2_ck, | ||
| 2836 | &dpll4_m6_ck, | ||
| 2837 | &dpll4_m6x2_ck, | ||
| 2838 | &emu_per_alwon_ck, | ||
| 2839 | &dpll5_ck, | ||
| 2840 | &dpll5_m2_ck, | ||
| 2841 | &omap_120m_fck, | ||
| 2842 | &clkout2_src_ck, | ||
| 2843 | &sys_clkout2, | ||
| 2844 | &corex2_fck, | ||
| 2845 | &dpll1_fck, | ||
| 2846 | &mpu_ck, | ||
| 2847 | &arm_fck, | ||
| 2848 | &emu_mpu_alwon_ck, | ||
| 2849 | &dpll2_fck, | ||
| 2850 | &iva2_ck, | ||
| 2851 | &l3_ick, | ||
| 2852 | &l4_ick, | ||
| 2853 | &rm_ick, | ||
| 2854 | &gfx_l3_fck, | ||
| 2855 | &gfx_l3_ick, | ||
| 2856 | &gfx_cg1_ck, | ||
| 2857 | &gfx_cg2_ck, | ||
| 2858 | &sgx_fck, | ||
| 2859 | &sgx_ick, | ||
| 2860 | &d2d_26m_fck, | ||
| 2861 | &gpt10_fck, | ||
| 2862 | &gpt11_fck, | ||
| 2863 | &cpefuse_fck, | ||
| 2864 | &ts_fck, | ||
| 2865 | &usbtll_fck, | ||
| 2866 | &core_96m_fck, | ||
| 2867 | &mmchs3_fck, | ||
| 2868 | &mmchs2_fck, | ||
| 2869 | &mspro_fck, | ||
| 2870 | &mmchs1_fck, | ||
| 2871 | &i2c3_fck, | ||
| 2872 | &i2c2_fck, | ||
| 2873 | &i2c1_fck, | ||
| 2874 | &mcbsp5_fck, | ||
| 2875 | &mcbsp1_fck, | ||
| 2876 | &core_48m_fck, | ||
| 2877 | &mcspi4_fck, | ||
| 2878 | &mcspi3_fck, | ||
| 2879 | &mcspi2_fck, | ||
| 2880 | &mcspi1_fck, | ||
| 2881 | &uart2_fck, | ||
| 2882 | &uart1_fck, | ||
| 2883 | &fshostusb_fck, | ||
| 2884 | &core_12m_fck, | ||
| 2885 | &hdq_fck, | ||
| 2886 | &ssi_ssr_fck, | ||
| 2887 | &ssi_sst_fck, | ||
| 2888 | &core_l3_ick, | ||
| 2889 | &hsotgusb_ick, | ||
| 2890 | &sdrc_ick, | ||
| 2891 | &gpmc_fck, | ||
| 2892 | &security_l3_ick, | ||
| 2893 | &pka_ick, | ||
| 2894 | &core_l4_ick, | ||
| 2895 | &usbtll_ick, | ||
| 2896 | &mmchs3_ick, | ||
| 2897 | &icr_ick, | ||
| 2898 | &aes2_ick, | ||
| 2899 | &sha12_ick, | ||
| 2900 | &des2_ick, | ||
| 2901 | &mmchs2_ick, | ||
| 2902 | &mmchs1_ick, | ||
| 2903 | &mspro_ick, | ||
| 2904 | &hdq_ick, | ||
| 2905 | &mcspi4_ick, | ||
| 2906 | &mcspi3_ick, | ||
| 2907 | &mcspi2_ick, | ||
| 2908 | &mcspi1_ick, | ||
| 2909 | &i2c3_ick, | ||
| 2910 | &i2c2_ick, | ||
| 2911 | &i2c1_ick, | ||
| 2912 | &uart2_ick, | ||
| 2913 | &uart1_ick, | ||
| 2914 | &gpt11_ick, | ||
| 2915 | &gpt10_ick, | ||
| 2916 | &mcbsp5_ick, | ||
| 2917 | &mcbsp1_ick, | ||
| 2918 | &fac_ick, | ||
| 2919 | &mailboxes_ick, | ||
| 2920 | &omapctrl_ick, | ||
| 2921 | &ssi_l4_ick, | ||
| 2922 | &ssi_ick, | ||
| 2923 | &usb_l4_ick, | ||
| 2924 | &security_l4_ick2, | ||
| 2925 | &aes1_ick, | ||
| 2926 | &rng_ick, | ||
| 2927 | &sha11_ick, | ||
| 2928 | &des1_ick, | ||
| 2929 | &dss1_alwon_fck, | ||
| 2930 | &dss_tv_fck, | ||
| 2931 | &dss_96m_fck, | ||
| 2932 | &dss2_alwon_fck, | ||
| 2933 | &dss_ick, | ||
| 2934 | &cam_mclk, | ||
| 2935 | &cam_l3_ick, | ||
| 2936 | &cam_l4_ick, | ||
| 2937 | &usbhost_120m_fck, | ||
| 2938 | &usbhost_48m_fck, | ||
| 2939 | &usbhost_l3_ick, | ||
| 2940 | &usbhost_l4_ick, | ||
| 2941 | &usbhost_sar_fck, | ||
| 2942 | &usim_fck, | ||
| 2943 | &gpt1_fck, | ||
| 2944 | &wkup_32k_fck, | ||
| 2945 | &gpio1_fck, | ||
| 2946 | &wdt2_fck, | ||
| 2947 | &wkup_l4_ick, | ||
| 2948 | &usim_ick, | ||
| 2949 | &wdt2_ick, | ||
| 2950 | &wdt1_ick, | ||
| 2951 | &gpio1_ick, | ||
| 2952 | &omap_32ksync_ick, | ||
| 2953 | &gpt12_ick, | ||
| 2954 | &gpt1_ick, | ||
| 2955 | &per_96m_fck, | ||
| 2956 | &per_48m_fck, | ||
| 2957 | &uart3_fck, | ||
| 2958 | &gpt2_fck, | ||
| 2959 | &gpt3_fck, | ||
| 2960 | &gpt4_fck, | ||
| 2961 | &gpt5_fck, | ||
| 2962 | &gpt6_fck, | ||
| 2963 | &gpt7_fck, | ||
| 2964 | &gpt8_fck, | ||
| 2965 | &gpt9_fck, | ||
| 2966 | &per_32k_alwon_fck, | ||
| 2967 | &gpio6_fck, | ||
| 2968 | &gpio5_fck, | ||
| 2969 | &gpio4_fck, | ||
| 2970 | &gpio3_fck, | ||
| 2971 | &gpio2_fck, | ||
| 2972 | &wdt3_fck, | ||
| 2973 | &per_l4_ick, | ||
| 2974 | &gpio6_ick, | ||
| 2975 | &gpio5_ick, | ||
| 2976 | &gpio4_ick, | ||
| 2977 | &gpio3_ick, | ||
| 2978 | &gpio2_ick, | ||
| 2979 | &wdt3_ick, | ||
| 2980 | &uart3_ick, | ||
| 2981 | &gpt9_ick, | ||
| 2982 | &gpt8_ick, | ||
| 2983 | &gpt7_ick, | ||
| 2984 | &gpt6_ick, | ||
| 2985 | &gpt5_ick, | ||
| 2986 | &gpt4_ick, | ||
| 2987 | &gpt3_ick, | ||
| 2988 | &gpt2_ick, | ||
| 2989 | &mcbsp2_ick, | ||
| 2990 | &mcbsp3_ick, | ||
| 2991 | &mcbsp4_ick, | ||
| 2992 | &mcbsp2_fck, | ||
| 2993 | &mcbsp3_fck, | ||
| 2994 | &mcbsp4_fck, | ||
| 2995 | &emu_src_ck, | ||
| 2996 | &pclk_fck, | ||
| 2997 | &pclkx2_fck, | ||
| 2998 | &atclk_fck, | ||
| 2999 | &traceclk_src_fck, | ||
| 3000 | &traceclk_fck, | ||
| 3001 | &sr1_fck, | ||
| 3002 | &sr2_fck, | ||
| 3003 | &sr_l4_ick, | ||
| 3004 | &secure_32k_fck, | ||
| 3005 | &gpt12_fck, | ||
| 3006 | &wdt1_fck, | ||
| 3007 | }; | ||
| 3008 | |||
| 3009 | #endif | ||
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h new file mode 100644 index 000000000000..20ac38100678 --- /dev/null +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h | |||
| @@ -0,0 +1,401 @@ | |||
| 1 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H | ||
| 2 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * OMAP24XX Clock Management register bits | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 8 | * Copyright (C) 2007 Nokia Corporation | ||
| 9 | * | ||
| 10 | * Written by Paul Walmsley | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include "cm.h" | ||
| 18 | |||
| 19 | /* Bits shared between registers */ | ||
| 20 | |||
| 21 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ | ||
| 22 | #define OMAP24XX_EN_CAM_SHIFT 31 | ||
| 23 | #define OMAP24XX_EN_CAM (1 << 31) | ||
| 24 | #define OMAP24XX_EN_WDT4_SHIFT 29 | ||
| 25 | #define OMAP24XX_EN_WDT4 (1 << 29) | ||
| 26 | #define OMAP2420_EN_WDT3_SHIFT 28 | ||
| 27 | #define OMAP2420_EN_WDT3 (1 << 28) | ||
| 28 | #define OMAP24XX_EN_MSPRO_SHIFT 27 | ||
| 29 | #define OMAP24XX_EN_MSPRO (1 << 27) | ||
| 30 | #define OMAP24XX_EN_FAC_SHIFT 25 | ||
| 31 | #define OMAP24XX_EN_FAC (1 << 25) | ||
| 32 | #define OMAP2420_EN_EAC_SHIFT 24 | ||
| 33 | #define OMAP2420_EN_EAC (1 << 24) | ||
| 34 | #define OMAP24XX_EN_HDQ_SHIFT 23 | ||
| 35 | #define OMAP24XX_EN_HDQ (1 << 23) | ||
| 36 | #define OMAP2420_EN_I2C2_SHIFT 20 | ||
| 37 | #define OMAP2420_EN_I2C2 (1 << 20) | ||
| 38 | #define OMAP2420_EN_I2C1_SHIFT 19 | ||
| 39 | #define OMAP2420_EN_I2C1 (1 << 19) | ||
| 40 | |||
| 41 | /* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */ | ||
| 42 | #define OMAP2430_EN_MCBSP5_SHIFT 5 | ||
| 43 | #define OMAP2430_EN_MCBSP5 (1 << 5) | ||
| 44 | #define OMAP2430_EN_MCBSP4_SHIFT 4 | ||
| 45 | #define OMAP2430_EN_MCBSP4 (1 << 4) | ||
| 46 | #define OMAP2430_EN_MCBSP3_SHIFT 3 | ||
| 47 | #define OMAP2430_EN_MCBSP3 (1 << 3) | ||
| 48 | #define OMAP24XX_EN_SSI_SHIFT 1 | ||
| 49 | #define OMAP24XX_EN_SSI (1 << 1) | ||
| 50 | |||
| 51 | /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ | ||
| 52 | #define OMAP24XX_EN_MPU_WDT_SHIFT 3 | ||
| 53 | #define OMAP24XX_EN_MPU_WDT (1 << 3) | ||
| 54 | |||
| 55 | /* Bits specific to each register */ | ||
| 56 | |||
| 57 | /* CM_IDLEST_MPU */ | ||
| 58 | /* 2430 only */ | ||
| 59 | #define OMAP2430_ST_MPU (1 << 0) | ||
| 60 | |||
| 61 | /* CM_CLKSEL_MPU */ | ||
| 62 | #define OMAP24XX_CLKSEL_MPU_SHIFT 0 | ||
| 63 | #define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) | ||
| 64 | |||
| 65 | /* CM_CLKSTCTRL_MPU */ | ||
| 66 | #define OMAP24XX_AUTOSTATE_MPU (1 << 0) | ||
| 67 | |||
| 68 | /* CM_FCLKEN1_CORE specific bits*/ | ||
| 69 | #define OMAP24XX_EN_TV_SHIFT 2 | ||
| 70 | #define OMAP24XX_EN_TV (1 << 2) | ||
| 71 | #define OMAP24XX_EN_DSS2_SHIFT 1 | ||
| 72 | #define OMAP24XX_EN_DSS2 (1 << 1) | ||
| 73 | #define OMAP24XX_EN_DSS1_SHIFT 0 | ||
| 74 | #define OMAP24XX_EN_DSS1 (1 << 0) | ||
| 75 | |||
| 76 | /* CM_FCLKEN2_CORE specific bits */ | ||
| 77 | #define OMAP2430_EN_I2CHS2_SHIFT 20 | ||
| 78 | #define OMAP2430_EN_I2CHS2 (1 << 20) | ||
| 79 | #define OMAP2430_EN_I2CHS1_SHIFT 19 | ||
| 80 | #define OMAP2430_EN_I2CHS1 (1 << 19) | ||
| 81 | #define OMAP2430_EN_MMCHSDB2_SHIFT 17 | ||
| 82 | #define OMAP2430_EN_MMCHSDB2 (1 << 17) | ||
| 83 | #define OMAP2430_EN_MMCHSDB1_SHIFT 16 | ||
| 84 | #define OMAP2430_EN_MMCHSDB1 (1 << 16) | ||
| 85 | |||
| 86 | /* CM_ICLKEN1_CORE specific bits */ | ||
| 87 | #define OMAP24XX_EN_MAILBOXES_SHIFT 30 | ||
| 88 | #define OMAP24XX_EN_MAILBOXES (1 << 30) | ||
| 89 | #define OMAP24XX_EN_DSS_SHIFT 0 | ||
| 90 | #define OMAP24XX_EN_DSS (1 << 0) | ||
| 91 | |||
| 92 | /* CM_ICLKEN2_CORE specific bits */ | ||
| 93 | |||
| 94 | /* CM_ICLKEN3_CORE */ | ||
| 95 | /* 2430 only */ | ||
| 96 | #define OMAP2430_EN_SDRC_SHIFT 2 | ||
| 97 | #define OMAP2430_EN_SDRC (1 << 2) | ||
| 98 | |||
| 99 | /* CM_ICLKEN4_CORE */ | ||
| 100 | #define OMAP24XX_EN_PKA_SHIFT 4 | ||
| 101 | #define OMAP24XX_EN_PKA (1 << 4) | ||
| 102 | #define OMAP24XX_EN_AES_SHIFT 3 | ||
| 103 | #define OMAP24XX_EN_AES (1 << 3) | ||
| 104 | #define OMAP24XX_EN_RNG_SHIFT 2 | ||
| 105 | #define OMAP24XX_EN_RNG (1 << 2) | ||
| 106 | #define OMAP24XX_EN_SHA_SHIFT 1 | ||
| 107 | #define OMAP24XX_EN_SHA (1 << 1) | ||
| 108 | #define OMAP24XX_EN_DES_SHIFT 0 | ||
| 109 | #define OMAP24XX_EN_DES (1 << 0) | ||
| 110 | |||
| 111 | /* CM_IDLEST1_CORE specific bits */ | ||
| 112 | #define OMAP24XX_ST_MAILBOXES (1 << 30) | ||
| 113 | #define OMAP24XX_ST_WDT4 (1 << 29) | ||
| 114 | #define OMAP2420_ST_WDT3 (1 << 28) | ||
| 115 | #define OMAP24XX_ST_MSPRO (1 << 27) | ||
| 116 | #define OMAP24XX_ST_FAC (1 << 25) | ||
| 117 | #define OMAP2420_ST_EAC (1 << 24) | ||
| 118 | #define OMAP24XX_ST_HDQ (1 << 23) | ||
| 119 | #define OMAP24XX_ST_I2C2 (1 << 20) | ||
| 120 | #define OMAP24XX_ST_I2C1 (1 << 19) | ||
| 121 | #define OMAP24XX_ST_MCBSP2 (1 << 16) | ||
| 122 | #define OMAP24XX_ST_MCBSP1 (1 << 15) | ||
| 123 | #define OMAP24XX_ST_DSS (1 << 0) | ||
| 124 | |||
| 125 | /* CM_IDLEST2_CORE */ | ||
| 126 | #define OMAP2430_ST_MCBSP5 (1 << 5) | ||
| 127 | #define OMAP2430_ST_MCBSP4 (1 << 4) | ||
| 128 | #define OMAP2430_ST_MCBSP3 (1 << 3) | ||
| 129 | #define OMAP24XX_ST_SSI (1 << 1) | ||
| 130 | |||
| 131 | /* CM_IDLEST3_CORE */ | ||
| 132 | /* 2430 only */ | ||
| 133 | #define OMAP2430_ST_SDRC (1 << 2) | ||
| 134 | |||
| 135 | /* CM_IDLEST4_CORE */ | ||
| 136 | #define OMAP24XX_ST_PKA (1 << 4) | ||
| 137 | #define OMAP24XX_ST_AES (1 << 3) | ||
| 138 | #define OMAP24XX_ST_RNG (1 << 2) | ||
| 139 | #define OMAP24XX_ST_SHA (1 << 1) | ||
| 140 | #define OMAP24XX_ST_DES (1 << 0) | ||
| 141 | |||
| 142 | /* CM_AUTOIDLE1_CORE */ | ||
| 143 | #define OMAP24XX_AUTO_CAM (1 << 31) | ||
| 144 | #define OMAP24XX_AUTO_MAILBOXES (1 << 30) | ||
| 145 | #define OMAP24XX_AUTO_WDT4 (1 << 29) | ||
| 146 | #define OMAP2420_AUTO_WDT3 (1 << 28) | ||
| 147 | #define OMAP24XX_AUTO_MSPRO (1 << 27) | ||
| 148 | #define OMAP2420_AUTO_MMC (1 << 26) | ||
| 149 | #define OMAP24XX_AUTO_FAC (1 << 25) | ||
| 150 | #define OMAP2420_AUTO_EAC (1 << 24) | ||
| 151 | #define OMAP24XX_AUTO_HDQ (1 << 23) | ||
| 152 | #define OMAP24XX_AUTO_UART2 (1 << 22) | ||
| 153 | #define OMAP24XX_AUTO_UART1 (1 << 21) | ||
| 154 | #define OMAP24XX_AUTO_I2C2 (1 << 20) | ||
| 155 | #define OMAP24XX_AUTO_I2C1 (1 << 19) | ||
| 156 | #define OMAP24XX_AUTO_MCSPI2 (1 << 18) | ||
| 157 | #define OMAP24XX_AUTO_MCSPI1 (1 << 17) | ||
| 158 | #define OMAP24XX_AUTO_MCBSP2 (1 << 16) | ||
| 159 | #define OMAP24XX_AUTO_MCBSP1 (1 << 15) | ||
| 160 | #define OMAP24XX_AUTO_GPT12 (1 << 14) | ||
| 161 | #define OMAP24XX_AUTO_GPT11 (1 << 13) | ||
| 162 | #define OMAP24XX_AUTO_GPT10 (1 << 12) | ||
| 163 | #define OMAP24XX_AUTO_GPT9 (1 << 11) | ||
| 164 | #define OMAP24XX_AUTO_GPT8 (1 << 10) | ||
| 165 | #define OMAP24XX_AUTO_GPT7 (1 << 9) | ||
| 166 | #define OMAP24XX_AUTO_GPT6 (1 << 8) | ||
| 167 | #define OMAP24XX_AUTO_GPT5 (1 << 7) | ||
| 168 | #define OMAP24XX_AUTO_GPT4 (1 << 6) | ||
| 169 | #define OMAP24XX_AUTO_GPT3 (1 << 5) | ||
| 170 | #define OMAP24XX_AUTO_GPT2 (1 << 4) | ||
| 171 | #define OMAP2420_AUTO_VLYNQ (1 << 3) | ||
| 172 | #define OMAP24XX_AUTO_DSS (1 << 0) | ||
| 173 | |||
| 174 | /* CM_AUTOIDLE2_CORE */ | ||
| 175 | #define OMAP2430_AUTO_MDM_INTC (1 << 11) | ||
| 176 | #define OMAP2430_AUTO_GPIO5 (1 << 10) | ||
| 177 | #define OMAP2430_AUTO_MCSPI3 (1 << 9) | ||
| 178 | #define OMAP2430_AUTO_MMCHS2 (1 << 8) | ||
| 179 | #define OMAP2430_AUTO_MMCHS1 (1 << 7) | ||
| 180 | #define OMAP2430_AUTO_USBHS (1 << 6) | ||
| 181 | #define OMAP2430_AUTO_MCBSP5 (1 << 5) | ||
| 182 | #define OMAP2430_AUTO_MCBSP4 (1 << 4) | ||
| 183 | #define OMAP2430_AUTO_MCBSP3 (1 << 3) | ||
| 184 | #define OMAP24XX_AUTO_UART3 (1 << 2) | ||
| 185 | #define OMAP24XX_AUTO_SSI (1 << 1) | ||
| 186 | #define OMAP24XX_AUTO_USB (1 << 0) | ||
| 187 | |||
| 188 | /* CM_AUTOIDLE3_CORE */ | ||
| 189 | #define OMAP24XX_AUTO_SDRC (1 << 2) | ||
| 190 | #define OMAP24XX_AUTO_GPMC (1 << 1) | ||
| 191 | #define OMAP24XX_AUTO_SDMA (1 << 0) | ||
| 192 | |||
| 193 | /* CM_AUTOIDLE4_CORE */ | ||
| 194 | #define OMAP24XX_AUTO_PKA (1 << 4) | ||
| 195 | #define OMAP24XX_AUTO_AES (1 << 3) | ||
| 196 | #define OMAP24XX_AUTO_RNG (1 << 2) | ||
| 197 | #define OMAP24XX_AUTO_SHA (1 << 1) | ||
| 198 | #define OMAP24XX_AUTO_DES (1 << 0) | ||
| 199 | |||
| 200 | /* CM_CLKSEL1_CORE */ | ||
| 201 | #define OMAP24XX_CLKSEL_USB_SHIFT 25 | ||
| 202 | #define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25) | ||
| 203 | #define OMAP24XX_CLKSEL_SSI_SHIFT 20 | ||
| 204 | #define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20) | ||
| 205 | #define OMAP2420_CLKSEL_VLYNQ_SHIFT 15 | ||
| 206 | #define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15) | ||
| 207 | #define OMAP24XX_CLKSEL_DSS2_SHIFT 13 | ||
| 208 | #define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13) | ||
| 209 | #define OMAP24XX_CLKSEL_DSS1_SHIFT 8 | ||
| 210 | #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) | ||
| 211 | #define OMAP24XX_CLKSEL_L4_SHIFT 5 | ||
| 212 | #define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5) | ||
| 213 | #define OMAP24XX_CLKSEL_L3_SHIFT 0 | ||
| 214 | #define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0) | ||
| 215 | |||
| 216 | /* CM_CLKSEL2_CORE */ | ||
| 217 | #define OMAP24XX_CLKSEL_GPT12_SHIFT 22 | ||
| 218 | #define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22) | ||
| 219 | #define OMAP24XX_CLKSEL_GPT11_SHIFT 20 | ||
| 220 | #define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20) | ||
| 221 | #define OMAP24XX_CLKSEL_GPT10_SHIFT 18 | ||
| 222 | #define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18) | ||
| 223 | #define OMAP24XX_CLKSEL_GPT9_SHIFT 16 | ||
| 224 | #define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16) | ||
| 225 | #define OMAP24XX_CLKSEL_GPT8_SHIFT 14 | ||
| 226 | #define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14) | ||
| 227 | #define OMAP24XX_CLKSEL_GPT7_SHIFT 12 | ||
| 228 | #define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12) | ||
| 229 | #define OMAP24XX_CLKSEL_GPT6_SHIFT 10 | ||
| 230 | #define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10) | ||
| 231 | #define OMAP24XX_CLKSEL_GPT5_SHIFT 8 | ||
| 232 | #define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8) | ||
| 233 | #define OMAP24XX_CLKSEL_GPT4_SHIFT 6 | ||
| 234 | #define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6) | ||
| 235 | #define OMAP24XX_CLKSEL_GPT3_SHIFT 4 | ||
| 236 | #define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4) | ||
| 237 | #define OMAP24XX_CLKSEL_GPT2_SHIFT 2 | ||
| 238 | #define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) | ||
| 239 | |||
| 240 | /* CM_CLKSTCTRL_CORE */ | ||
| 241 | #define OMAP24XX_AUTOSTATE_DSS (1 << 2) | ||
| 242 | #define OMAP24XX_AUTOSTATE_L4 (1 << 1) | ||
| 243 | #define OMAP24XX_AUTOSTATE_L3 (1 << 0) | ||
| 244 | |||
| 245 | /* CM_FCLKEN_GFX */ | ||
| 246 | #define OMAP24XX_EN_3D_SHIFT 2 | ||
| 247 | #define OMAP24XX_EN_3D (1 << 2) | ||
| 248 | #define OMAP24XX_EN_2D_SHIFT 1 | ||
| 249 | #define OMAP24XX_EN_2D (1 << 1) | ||
| 250 | |||
| 251 | /* CM_ICLKEN_GFX specific bits */ | ||
| 252 | |||
| 253 | /* CM_IDLEST_GFX specific bits */ | ||
| 254 | |||
| 255 | /* CM_CLKSEL_GFX specific bits */ | ||
| 256 | |||
| 257 | /* CM_CLKSTCTRL_GFX */ | ||
| 258 | #define OMAP24XX_AUTOSTATE_GFX (1 << 0) | ||
| 259 | |||
| 260 | /* CM_FCLKEN_WKUP specific bits */ | ||
| 261 | |||
| 262 | /* CM_ICLKEN_WKUP specific bits */ | ||
| 263 | #define OMAP2430_EN_ICR_SHIFT 6 | ||
| 264 | #define OMAP2430_EN_ICR (1 << 6) | ||
| 265 | #define OMAP24XX_EN_OMAPCTRL_SHIFT 5 | ||
| 266 | #define OMAP24XX_EN_OMAPCTRL (1 << 5) | ||
| 267 | #define OMAP24XX_EN_WDT1_SHIFT 4 | ||
| 268 | #define OMAP24XX_EN_WDT1 (1 << 4) | ||
| 269 | #define OMAP24XX_EN_32KSYNC_SHIFT 1 | ||
| 270 | #define OMAP24XX_EN_32KSYNC (1 << 1) | ||
| 271 | |||
| 272 | /* CM_IDLEST_WKUP specific bits */ | ||
| 273 | #define OMAP2430_ST_ICR (1 << 6) | ||
| 274 | #define OMAP24XX_ST_OMAPCTRL (1 << 5) | ||
| 275 | #define OMAP24XX_ST_WDT1 (1 << 4) | ||
| 276 | #define OMAP24XX_ST_MPU_WDT (1 << 3) | ||
| 277 | #define OMAP24XX_ST_32KSYNC (1 << 1) | ||
| 278 | |||
| 279 | /* CM_AUTOIDLE_WKUP */ | ||
| 280 | #define OMAP24XX_AUTO_OMAPCTRL (1 << 5) | ||
| 281 | #define OMAP24XX_AUTO_WDT1 (1 << 4) | ||
| 282 | #define OMAP24XX_AUTO_MPU_WDT (1 << 3) | ||
| 283 | #define OMAP24XX_AUTO_GPIOS (1 << 2) | ||
| 284 | #define OMAP24XX_AUTO_32KSYNC (1 << 1) | ||
| 285 | #define OMAP24XX_AUTO_GPT1 (1 << 0) | ||
| 286 | |||
| 287 | /* CM_CLKSEL_WKUP */ | ||
| 288 | #define OMAP24XX_CLKSEL_GPT1_SHIFT 0 | ||
| 289 | #define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0) | ||
| 290 | |||
| 291 | /* CM_CLKEN_PLL */ | ||
| 292 | #define OMAP24XX_EN_54M_PLL_SHIFT 6 | ||
| 293 | #define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6) | ||
| 294 | #define OMAP24XX_EN_96M_PLL_SHIFT 2 | ||
| 295 | #define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2) | ||
| 296 | #define OMAP24XX_EN_DPLL_SHIFT 0 | ||
| 297 | #define OMAP24XX_EN_DPLL_MASK (0x3 << 0) | ||
| 298 | |||
| 299 | /* CM_IDLEST_CKGEN */ | ||
| 300 | #define OMAP24XX_ST_54M_APLL (1 << 9) | ||
| 301 | #define OMAP24XX_ST_96M_APLL (1 << 8) | ||
| 302 | #define OMAP24XX_ST_54M_CLK (1 << 6) | ||
| 303 | #define OMAP24XX_ST_12M_CLK (1 << 5) | ||
| 304 | #define OMAP24XX_ST_48M_CLK (1 << 4) | ||
| 305 | #define OMAP24XX_ST_96M_CLK (1 << 2) | ||
| 306 | #define OMAP24XX_ST_CORE_CLK_SHIFT 0 | ||
| 307 | #define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0) | ||
| 308 | |||
| 309 | /* CM_AUTOIDLE_PLL */ | ||
| 310 | #define OMAP24XX_AUTO_54M_SHIFT 6 | ||
| 311 | #define OMAP24XX_AUTO_54M_MASK (0x3 << 6) | ||
| 312 | #define OMAP24XX_AUTO_96M_SHIFT 2 | ||
| 313 | #define OMAP24XX_AUTO_96M_MASK (0x3 << 2) | ||
| 314 | #define OMAP24XX_AUTO_DPLL_SHIFT 0 | ||
| 315 | #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) | ||
| 316 | |||
| 317 | /* CM_CLKSEL1_PLL */ | ||
| 318 | #define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28 | ||
| 319 | #define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28) | ||
| 320 | #define OMAP24XX_APLLS_CLKIN_SHIFT 23 | ||
| 321 | #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) | ||
| 322 | #define OMAP24XX_DPLL_MULT_SHIFT 12 | ||
| 323 | #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) | ||
| 324 | #define OMAP24XX_DPLL_DIV_SHIFT 8 | ||
| 325 | #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) | ||
| 326 | #define OMAP24XX_54M_SOURCE_SHIFT 5 | ||
| 327 | #define OMAP24XX_54M_SOURCE (1 << 5) | ||
| 328 | #define OMAP2430_96M_SOURCE_SHIFT 4 | ||
| 329 | #define OMAP2430_96M_SOURCE (1 << 4) | ||
| 330 | #define OMAP24XX_48M_SOURCE_SHIFT 3 | ||
| 331 | #define OMAP24XX_48M_SOURCE (1 << 3) | ||
| 332 | #define OMAP2430_ALTCLK_SOURCE_SHIFT 0 | ||
| 333 | #define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0) | ||
| 334 | |||
| 335 | /* CM_CLKSEL2_PLL */ | ||
| 336 | #define OMAP24XX_CORE_CLK_SRC_SHIFT 0 | ||
| 337 | #define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0) | ||
| 338 | |||
| 339 | /* CM_FCLKEN_DSP */ | ||
| 340 | #define OMAP2420_EN_IVA_COP_SHIFT 10 | ||
| 341 | #define OMAP2420_EN_IVA_COP (1 << 10) | ||
| 342 | #define OMAP2420_EN_IVA_MPU_SHIFT 8 | ||
| 343 | #define OMAP2420_EN_IVA_MPU (1 << 8) | ||
| 344 | #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 | ||
| 345 | #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP (1 << 0) | ||
| 346 | |||
| 347 | /* CM_ICLKEN_DSP */ | ||
| 348 | #define OMAP2420_EN_DSP_IPI_SHIFT 1 | ||
| 349 | #define OMAP2420_EN_DSP_IPI (1 << 1) | ||
| 350 | |||
| 351 | /* CM_IDLEST_DSP */ | ||
| 352 | #define OMAP2420_ST_IVA (1 << 8) | ||
| 353 | #define OMAP2420_ST_IPI (1 << 1) | ||
| 354 | #define OMAP24XX_ST_DSP (1 << 0) | ||
| 355 | |||
| 356 | /* CM_AUTOIDLE_DSP */ | ||
| 357 | #define OMAP2420_AUTO_DSP_IPI (1 << 1) | ||
| 358 | |||
| 359 | /* CM_CLKSEL_DSP */ | ||
| 360 | #define OMAP2420_SYNC_IVA (1 << 13) | ||
| 361 | #define OMAP2420_CLKSEL_IVA_SHIFT 8 | ||
| 362 | #define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) | ||
| 363 | #define OMAP24XX_SYNC_DSP (1 << 7) | ||
| 364 | #define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5 | ||
| 365 | #define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) | ||
| 366 | #define OMAP24XX_CLKSEL_DSP_SHIFT 0 | ||
| 367 | #define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) | ||
| 368 | |||
| 369 | /* CM_CLKSTCTRL_DSP */ | ||
| 370 | #define OMAP2420_AUTOSTATE_IVA (1 << 8) | ||
| 371 | #define OMAP24XX_AUTOSTATE_DSP (1 << 0) | ||
| 372 | |||
| 373 | /* CM_FCLKEN_MDM */ | ||
| 374 | /* 2430 only */ | ||
| 375 | #define OMAP2430_EN_OSC_SHIFT 1 | ||
| 376 | #define OMAP2430_EN_OSC (1 << 1) | ||
| 377 | |||
| 378 | /* CM_ICLKEN_MDM */ | ||
| 379 | /* 2430 only */ | ||
| 380 | #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 | ||
| 381 | #define OMAP2430_CM_ICLKEN_MDM_EN_MDM (1 << 0) | ||
| 382 | |||
| 383 | /* CM_IDLEST_MDM specific bits */ | ||
| 384 | /* 2430 only */ | ||
| 385 | |||
| 386 | /* CM_AUTOIDLE_MDM */ | ||
| 387 | /* 2430 only */ | ||
| 388 | #define OMAP2430_AUTO_OSC (1 << 1) | ||
| 389 | #define OMAP2430_AUTO_MDM (1 << 0) | ||
| 390 | |||
| 391 | /* CM_CLKSEL_MDM */ | ||
| 392 | /* 2430 only */ | ||
| 393 | #define OMAP2430_SYNC_MDM (1 << 4) | ||
| 394 | #define OMAP2430_CLKSEL_MDM_SHIFT 0 | ||
| 395 | #define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) | ||
| 396 | |||
| 397 | /* CM_CLKSTCTRL_MDM */ | ||
| 398 | /* 2430 only */ | ||
| 399 | #define OMAP2430_AUTOSTATE_MDM (1 << 0) | ||
| 400 | |||
| 401 | #endif | ||
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h new file mode 100644 index 000000000000..9249129a5f46 --- /dev/null +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
| @@ -0,0 +1,673 @@ | |||
| 1 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H | ||
| 2 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * OMAP3430 Clock Management register bits | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | ||
| 8 | * Copyright (C) 2007-2008 Nokia Corporation | ||
| 9 | * | ||
| 10 | * Written by Paul Walmsley | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include "cm.h" | ||
| 18 | |||
| 19 | /* Bits shared between registers */ | ||
| 20 | |||
| 21 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ | ||
| 22 | #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) | ||
| 23 | #define OMAP3430ES2_EN_MMC3_SHIFT 30 | ||
| 24 | #define OMAP3430_EN_MSPRO (1 << 23) | ||
| 25 | #define OMAP3430_EN_MSPRO_SHIFT 23 | ||
| 26 | #define OMAP3430_EN_HDQ (1 << 22) | ||
| 27 | #define OMAP3430_EN_HDQ_SHIFT 22 | ||
| 28 | #define OMAP3430ES1_EN_FSHOSTUSB (1 << 5) | ||
| 29 | #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 | ||
| 30 | #define OMAP3430ES1_EN_D2D (1 << 3) | ||
| 31 | #define OMAP3430ES1_EN_D2D_SHIFT 3 | ||
| 32 | #define OMAP3430_EN_SSI (1 << 0) | ||
| 33 | #define OMAP3430_EN_SSI_SHIFT 0 | ||
| 34 | |||
| 35 | /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ | ||
| 36 | #define OMAP3430ES2_EN_USBTLL_SHIFT 2 | ||
| 37 | #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) | ||
| 38 | |||
| 39 | /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ | ||
| 40 | #define OMAP3430_EN_WDT2 (1 << 5) | ||
| 41 | #define OMAP3430_EN_WDT2_SHIFT 5 | ||
| 42 | |||
| 43 | /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ | ||
| 44 | #define OMAP3430_EN_CAM (1 << 0) | ||
| 45 | #define OMAP3430_EN_CAM_SHIFT 0 | ||
| 46 | |||
| 47 | /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ | ||
| 48 | #define OMAP3430_EN_WDT3 (1 << 12) | ||
| 49 | #define OMAP3430_EN_WDT3_SHIFT 12 | ||
| 50 | |||
| 51 | /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ | ||
| 52 | #define OMAP3430_OVERRIDE_ENABLE (1 << 19) | ||
| 53 | |||
| 54 | |||
| 55 | /* Bits specific to each register */ | ||
| 56 | |||
| 57 | /* CM_FCLKEN_IVA2 */ | ||
| 58 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0) | ||
| 59 | |||
| 60 | /* CM_CLKEN_PLL_IVA2 */ | ||
| 61 | #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 | ||
| 62 | #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) | ||
| 63 | #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 | ||
| 64 | #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) | ||
| 65 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 | ||
| 66 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) | ||
| 67 | #define OMAP3430_EN_IVA2_DPLL_SHIFT 0 | ||
| 68 | #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) | ||
| 69 | |||
| 70 | /* CM_IDLEST_IVA2 */ | ||
| 71 | #define OMAP3430_ST_IVA2 (1 << 0) | ||
| 72 | |||
| 73 | /* CM_IDLEST_PLL_IVA2 */ | ||
| 74 | #define OMAP3430_ST_IVA2_CLK (1 << 0) | ||
| 75 | |||
| 76 | /* CM_AUTOIDLE_PLL_IVA2 */ | ||
| 77 | #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 | ||
| 78 | #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) | ||
| 79 | |||
| 80 | /* CM_CLKSEL1_PLL_IVA2 */ | ||
| 81 | #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 | ||
| 82 | #define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) | ||
| 83 | #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 | ||
| 84 | #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) | ||
| 85 | #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 | ||
| 86 | #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) | ||
| 87 | |||
| 88 | /* CM_CLKSEL2_PLL_IVA2 */ | ||
| 89 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 | ||
| 90 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | ||
| 91 | |||
| 92 | /* CM_CLKSTCTRL_IVA2 */ | ||
| 93 | #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 | ||
| 94 | #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) | ||
| 95 | |||
| 96 | /* CM_CLKSTST_IVA2 */ | ||
| 97 | #define OMAP3430_CLKACTIVITY_IVA2 (1 << 0) | ||
| 98 | |||
| 99 | /* CM_REVISION specific bits */ | ||
| 100 | |||
| 101 | /* CM_SYSCONFIG specific bits */ | ||
| 102 | |||
| 103 | /* CM_CLKEN_PLL_MPU */ | ||
| 104 | #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 | ||
| 105 | #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) | ||
| 106 | #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 | ||
| 107 | #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) | ||
| 108 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 | ||
| 109 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) | ||
| 110 | #define OMAP3430_EN_MPU_DPLL_SHIFT 0 | ||
| 111 | #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) | ||
| 112 | |||
| 113 | /* CM_IDLEST_MPU */ | ||
| 114 | #define OMAP3430_ST_MPU (1 << 0) | ||
| 115 | |||
| 116 | /* CM_IDLEST_PLL_MPU */ | ||
| 117 | #define OMAP3430_ST_MPU_CLK (1 << 0) | ||
| 118 | #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) | ||
| 119 | |||
| 120 | /* CM_IDLEST_PLL_MPU */ | ||
| 121 | #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) | ||
| 122 | |||
| 123 | /* CM_AUTOIDLE_PLL_MPU */ | ||
| 124 | #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 | ||
| 125 | #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) | ||
| 126 | |||
| 127 | /* CM_CLKSEL1_PLL_MPU */ | ||
| 128 | #define OMAP3430_MPU_CLK_SRC_SHIFT 19 | ||
| 129 | #define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) | ||
| 130 | #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 | ||
| 131 | #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) | ||
| 132 | #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 | ||
| 133 | #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) | ||
| 134 | |||
| 135 | /* CM_CLKSEL2_PLL_MPU */ | ||
| 136 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 | ||
| 137 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | ||
| 138 | |||
| 139 | /* CM_CLKSTCTRL_MPU */ | ||
| 140 | #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 | ||
| 141 | #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) | ||
| 142 | |||
| 143 | /* CM_CLKSTST_MPU */ | ||
| 144 | #define OMAP3430_CLKACTIVITY_MPU (1 << 0) | ||
| 145 | |||
| 146 | /* CM_FCLKEN1_CORE specific bits */ | ||
| 147 | |||
| 148 | /* CM_ICLKEN1_CORE specific bits */ | ||
| 149 | #define OMAP3430_EN_ICR (1 << 29) | ||
| 150 | #define OMAP3430_EN_ICR_SHIFT 29 | ||
| 151 | #define OMAP3430_EN_AES2 (1 << 28) | ||
| 152 | #define OMAP3430_EN_AES2_SHIFT 28 | ||
| 153 | #define OMAP3430_EN_SHA12 (1 << 27) | ||
| 154 | #define OMAP3430_EN_SHA12_SHIFT 27 | ||
| 155 | #define OMAP3430_EN_DES2 (1 << 26) | ||
| 156 | #define OMAP3430_EN_DES2_SHIFT 26 | ||
| 157 | #define OMAP3430ES1_EN_FAC (1 << 8) | ||
| 158 | #define OMAP3430ES1_EN_FAC_SHIFT 8 | ||
| 159 | #define OMAP3430_EN_MAILBOXES (1 << 7) | ||
| 160 | #define OMAP3430_EN_MAILBOXES_SHIFT 7 | ||
| 161 | #define OMAP3430_EN_OMAPCTRL (1 << 6) | ||
| 162 | #define OMAP3430_EN_OMAPCTRL_SHIFT 6 | ||
| 163 | #define OMAP3430_EN_SDRC (1 << 1) | ||
| 164 | #define OMAP3430_EN_SDRC_SHIFT 1 | ||
| 165 | |||
| 166 | /* CM_ICLKEN2_CORE */ | ||
| 167 | #define OMAP3430_EN_PKA (1 << 4) | ||
| 168 | #define OMAP3430_EN_PKA_SHIFT 4 | ||
| 169 | #define OMAP3430_EN_AES1 (1 << 3) | ||
| 170 | #define OMAP3430_EN_AES1_SHIFT 3 | ||
| 171 | #define OMAP3430_EN_RNG (1 << 2) | ||
| 172 | #define OMAP3430_EN_RNG_SHIFT 2 | ||
| 173 | #define OMAP3430_EN_SHA11 (1 << 1) | ||
| 174 | #define OMAP3430_EN_SHA11_SHIFT 1 | ||
| 175 | #define OMAP3430_EN_DES1 (1 << 0) | ||
| 176 | #define OMAP3430_EN_DES1_SHIFT 0 | ||
| 177 | |||
| 178 | /* CM_FCLKEN3_CORE specific bits */ | ||
| 179 | #define OMAP3430ES2_EN_TS_SHIFT 1 | ||
| 180 | #define OMAP3430ES2_EN_TS_MASK (1 << 1) | ||
| 181 | #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 | ||
| 182 | #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) | ||
| 183 | |||
| 184 | /* CM_IDLEST1_CORE specific bits */ | ||
| 185 | #define OMAP3430_ST_ICR (1 << 29) | ||
| 186 | #define OMAP3430_ST_AES2 (1 << 28) | ||
| 187 | #define OMAP3430_ST_SHA12 (1 << 27) | ||
| 188 | #define OMAP3430_ST_DES2 (1 << 26) | ||
| 189 | #define OMAP3430_ST_MSPRO (1 << 23) | ||
| 190 | #define OMAP3430_ST_HDQ (1 << 22) | ||
| 191 | #define OMAP3430ES1_ST_FAC (1 << 8) | ||
| 192 | #define OMAP3430ES1_ST_MAILBOXES (1 << 7) | ||
| 193 | #define OMAP3430_ST_OMAPCTRL (1 << 6) | ||
| 194 | #define OMAP3430_ST_SDMA (1 << 2) | ||
| 195 | #define OMAP3430_ST_SDRC (1 << 1) | ||
| 196 | #define OMAP3430_ST_SSI (1 << 0) | ||
| 197 | |||
| 198 | /* CM_IDLEST2_CORE */ | ||
| 199 | #define OMAP3430_ST_PKA (1 << 4) | ||
| 200 | #define OMAP3430_ST_AES1 (1 << 3) | ||
| 201 | #define OMAP3430_ST_RNG (1 << 2) | ||
| 202 | #define OMAP3430_ST_SHA11 (1 << 1) | ||
| 203 | #define OMAP3430_ST_DES1 (1 << 0) | ||
| 204 | |||
| 205 | /* CM_IDLEST3_CORE */ | ||
| 206 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 | ||
| 207 | #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) | ||
| 208 | |||
| 209 | /* CM_AUTOIDLE1_CORE */ | ||
| 210 | #define OMAP3430_AUTO_AES2 (1 << 28) | ||
| 211 | #define OMAP3430_AUTO_AES2_SHIFT 28 | ||
| 212 | #define OMAP3430_AUTO_SHA12 (1 << 27) | ||
| 213 | #define OMAP3430_AUTO_SHA12_SHIFT 27 | ||
| 214 | #define OMAP3430_AUTO_DES2 (1 << 26) | ||
| 215 | #define OMAP3430_AUTO_DES2_SHIFT 26 | ||
| 216 | #define OMAP3430_AUTO_MMC2 (1 << 25) | ||
| 217 | #define OMAP3430_AUTO_MMC2_SHIFT 25 | ||
| 218 | #define OMAP3430_AUTO_MMC1 (1 << 24) | ||
| 219 | #define OMAP3430_AUTO_MMC1_SHIFT 24 | ||
| 220 | #define OMAP3430_AUTO_MSPRO (1 << 23) | ||
| 221 | #define OMAP3430_AUTO_MSPRO_SHIFT 23 | ||
| 222 | #define OMAP3430_AUTO_HDQ (1 << 22) | ||
| 223 | #define OMAP3430_AUTO_HDQ_SHIFT 22 | ||
| 224 | #define OMAP3430_AUTO_MCSPI4 (1 << 21) | ||
| 225 | #define OMAP3430_AUTO_MCSPI4_SHIFT 21 | ||
| 226 | #define OMAP3430_AUTO_MCSPI3 (1 << 20) | ||
| 227 | #define OMAP3430_AUTO_MCSPI3_SHIFT 20 | ||
| 228 | #define OMAP3430_AUTO_MCSPI2 (1 << 19) | ||
| 229 | #define OMAP3430_AUTO_MCSPI2_SHIFT 19 | ||
| 230 | #define OMAP3430_AUTO_MCSPI1 (1 << 18) | ||
| 231 | #define OMAP3430_AUTO_MCSPI1_SHIFT 18 | ||
| 232 | #define OMAP3430_AUTO_I2C3 (1 << 17) | ||
| 233 | #define OMAP3430_AUTO_I2C3_SHIFT 17 | ||
| 234 | #define OMAP3430_AUTO_I2C2 (1 << 16) | ||
| 235 | #define OMAP3430_AUTO_I2C2_SHIFT 16 | ||
| 236 | #define OMAP3430_AUTO_I2C1 (1 << 15) | ||
| 237 | #define OMAP3430_AUTO_I2C1_SHIFT 15 | ||
| 238 | #define OMAP3430_AUTO_UART2 (1 << 14) | ||
| 239 | #define OMAP3430_AUTO_UART2_SHIFT 14 | ||
| 240 | #define OMAP3430_AUTO_UART1 (1 << 13) | ||
| 241 | #define OMAP3430_AUTO_UART1_SHIFT 13 | ||
| 242 | #define OMAP3430_AUTO_GPT11 (1 << 12) | ||
| 243 | #define OMAP3430_AUTO_GPT11_SHIFT 12 | ||
| 244 | #define OMAP3430_AUTO_GPT10 (1 << 11) | ||
| 245 | #define OMAP3430_AUTO_GPT10_SHIFT 11 | ||
| 246 | #define OMAP3430_AUTO_MCBSP5 (1 << 10) | ||
| 247 | #define OMAP3430_AUTO_MCBSP5_SHIFT 10 | ||
| 248 | #define OMAP3430_AUTO_MCBSP1 (1 << 9) | ||
| 249 | #define OMAP3430_AUTO_MCBSP1_SHIFT 9 | ||
| 250 | #define OMAP3430ES1_AUTO_FAC (1 << 8) | ||
| 251 | #define OMAP3430ES1_AUTO_FAC_SHIFT 8 | ||
| 252 | #define OMAP3430_AUTO_MAILBOXES (1 << 7) | ||
| 253 | #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 | ||
| 254 | #define OMAP3430_AUTO_OMAPCTRL (1 << 6) | ||
| 255 | #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 | ||
| 256 | #define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5) | ||
| 257 | #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 | ||
| 258 | #define OMAP3430_AUTO_HSOTGUSB (1 << 4) | ||
| 259 | #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 | ||
| 260 | #define OMAP3430ES1_AUTO_D2D (1 << 3) | ||
| 261 | #define OMAP3430ES1_AUTO_D2D_SHIFT 3 | ||
| 262 | #define OMAP3430_AUTO_SSI (1 << 0) | ||
| 263 | #define OMAP3430_AUTO_SSI_SHIFT 0 | ||
| 264 | |||
| 265 | /* CM_AUTOIDLE2_CORE */ | ||
| 266 | #define OMAP3430_AUTO_PKA (1 << 4) | ||
| 267 | #define OMAP3430_AUTO_PKA_SHIFT 4 | ||
| 268 | #define OMAP3430_AUTO_AES1 (1 << 3) | ||
| 269 | #define OMAP3430_AUTO_AES1_SHIFT 3 | ||
| 270 | #define OMAP3430_AUTO_RNG (1 << 2) | ||
| 271 | #define OMAP3430_AUTO_RNG_SHIFT 2 | ||
| 272 | #define OMAP3430_AUTO_SHA11 (1 << 1) | ||
| 273 | #define OMAP3430_AUTO_SHA11_SHIFT 1 | ||
| 274 | #define OMAP3430_AUTO_DES1 (1 << 0) | ||
| 275 | #define OMAP3430_AUTO_DES1_SHIFT 0 | ||
| 276 | |||
| 277 | /* CM_AUTOIDLE3_CORE */ | ||
| 278 | #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 | ||
| 279 | #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) | ||
| 280 | |||
| 281 | /* CM_CLKSEL_CORE */ | ||
| 282 | #define OMAP3430_CLKSEL_SSI_SHIFT 8 | ||
| 283 | #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) | ||
| 284 | #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) | ||
| 285 | #define OMAP3430_CLKSEL_GPT11_SHIFT 7 | ||
| 286 | #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) | ||
| 287 | #define OMAP3430_CLKSEL_GPT10_SHIFT 6 | ||
| 288 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 | ||
| 289 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) | ||
| 290 | #define OMAP3430_CLKSEL_L4_SHIFT 2 | ||
| 291 | #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) | ||
| 292 | #define OMAP3430_CLKSEL_L3_SHIFT 0 | ||
| 293 | #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) | ||
| 294 | |||
| 295 | /* CM_CLKSTCTRL_CORE */ | ||
| 296 | #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 | ||
| 297 | #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) | ||
| 298 | #define OMAP3430_CLKTRCTRL_L4_SHIFT 2 | ||
| 299 | #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) | ||
| 300 | #define OMAP3430_CLKTRCTRL_L3_SHIFT 0 | ||
| 301 | #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) | ||
| 302 | |||
| 303 | /* CM_CLKSTST_CORE */ | ||
| 304 | #define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2) | ||
| 305 | #define OMAP3430_CLKACTIVITY_L4 (1 << 1) | ||
| 306 | #define OMAP3430_CLKACTIVITY_L3 (1 << 0) | ||
| 307 | |||
| 308 | /* CM_FCLKEN_GFX */ | ||
| 309 | #define OMAP3430ES1_EN_3D (1 << 2) | ||
| 310 | #define OMAP3430ES1_EN_3D_SHIFT 2 | ||
| 311 | #define OMAP3430ES1_EN_2D (1 << 1) | ||
| 312 | #define OMAP3430ES1_EN_2D_SHIFT 1 | ||
| 313 | |||
| 314 | /* CM_ICLKEN_GFX specific bits */ | ||
| 315 | |||
| 316 | /* CM_IDLEST_GFX specific bits */ | ||
| 317 | |||
| 318 | /* CM_CLKSEL_GFX specific bits */ | ||
| 319 | |||
| 320 | /* CM_SLEEPDEP_GFX specific bits */ | ||
| 321 | |||
| 322 | /* CM_CLKSTCTRL_GFX */ | ||
| 323 | #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 | ||
| 324 | #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) | ||
| 325 | |||
| 326 | /* CM_CLKSTST_GFX */ | ||
| 327 | #define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0) | ||
| 328 | |||
| 329 | /* CM_FCLKEN_SGX */ | ||
| 330 | #define OMAP3430ES2_EN_SGX_SHIFT 1 | ||
| 331 | #define OMAP3430ES2_EN_SGX_MASK (1 << 1) | ||
| 332 | |||
| 333 | /* CM_CLKSEL_SGX */ | ||
| 334 | #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 | ||
| 335 | #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) | ||
| 336 | |||
| 337 | /* CM_FCLKEN_WKUP specific bits */ | ||
| 338 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 | ||
| 339 | |||
| 340 | /* CM_ICLKEN_WKUP specific bits */ | ||
| 341 | #define OMAP3430_EN_WDT1 (1 << 4) | ||
| 342 | #define OMAP3430_EN_WDT1_SHIFT 4 | ||
| 343 | #define OMAP3430_EN_32KSYNC (1 << 2) | ||
| 344 | #define OMAP3430_EN_32KSYNC_SHIFT 2 | ||
| 345 | |||
| 346 | /* CM_IDLEST_WKUP specific bits */ | ||
| 347 | #define OMAP3430_ST_WDT2 (1 << 5) | ||
| 348 | #define OMAP3430_ST_WDT1 (1 << 4) | ||
| 349 | #define OMAP3430_ST_32KSYNC (1 << 2) | ||
| 350 | |||
| 351 | /* CM_AUTOIDLE_WKUP */ | ||
| 352 | #define OMAP3430_AUTO_WDT2 (1 << 5) | ||
| 353 | #define OMAP3430_AUTO_WDT2_SHIFT 5 | ||
| 354 | #define OMAP3430_AUTO_WDT1 (1 << 4) | ||
| 355 | #define OMAP3430_AUTO_WDT1_SHIFT 4 | ||
| 356 | #define OMAP3430_AUTO_GPIO1 (1 << 3) | ||
| 357 | #define OMAP3430_AUTO_GPIO1_SHIFT 3 | ||
| 358 | #define OMAP3430_AUTO_32KSYNC (1 << 2) | ||
| 359 | #define OMAP3430_AUTO_32KSYNC_SHIFT 2 | ||
| 360 | #define OMAP3430_AUTO_GPT12 (1 << 1) | ||
| 361 | #define OMAP3430_AUTO_GPT12_SHIFT 1 | ||
| 362 | #define OMAP3430_AUTO_GPT1 (1 << 0) | ||
| 363 | #define OMAP3430_AUTO_GPT1_SHIFT 0 | ||
| 364 | |||
| 365 | /* CM_CLKSEL_WKUP */ | ||
| 366 | #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) | ||
| 367 | #define OMAP3430_CLKSEL_RM_SHIFT 1 | ||
| 368 | #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) | ||
| 369 | #define OMAP3430_CLKSEL_GPT1_SHIFT 0 | ||
| 370 | #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) | ||
| 371 | |||
| 372 | /* CM_CLKEN_PLL */ | ||
| 373 | #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 | ||
| 374 | #define OMAP3430_PWRDN_CAM_SHIFT 30 | ||
| 375 | #define OMAP3430_PWRDN_DSS1_SHIFT 29 | ||
| 376 | #define OMAP3430_PWRDN_TV_SHIFT 28 | ||
| 377 | #define OMAP3430_PWRDN_96M_SHIFT 27 | ||
| 378 | #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 | ||
| 379 | #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) | ||
| 380 | #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 | ||
| 381 | #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) | ||
| 382 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 | ||
| 383 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) | ||
| 384 | #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 | ||
| 385 | #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) | ||
| 386 | #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 | ||
| 387 | #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 | ||
| 388 | #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) | ||
| 389 | #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 | ||
| 390 | #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) | ||
| 391 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 | ||
| 392 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) | ||
| 393 | #define OMAP3430_EN_CORE_DPLL_SHIFT 0 | ||
| 394 | #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) | ||
| 395 | |||
| 396 | /* CM_CLKEN2_PLL */ | ||
| 397 | #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 | ||
| 398 | #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) | ||
| 399 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 | ||
| 400 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) | ||
| 401 | #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 | ||
| 402 | #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 | ||
| 403 | #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) | ||
| 404 | |||
| 405 | /* CM_IDLEST_CKGEN */ | ||
| 406 | #define OMAP3430_ST_54M_CLK (1 << 5) | ||
| 407 | #define OMAP3430_ST_12M_CLK (1 << 4) | ||
| 408 | #define OMAP3430_ST_48M_CLK (1 << 3) | ||
| 409 | #define OMAP3430_ST_96M_CLK (1 << 2) | ||
| 410 | #define OMAP3430_ST_PERIPH_CLK (1 << 1) | ||
| 411 | #define OMAP3430_ST_CORE_CLK (1 << 0) | ||
| 412 | |||
| 413 | /* CM_IDLEST2_CKGEN */ | ||
| 414 | #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 | ||
| 415 | #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) | ||
| 416 | #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 | ||
| 417 | #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) | ||
| 418 | |||
| 419 | /* CM_AUTOIDLE_PLL */ | ||
| 420 | #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 | ||
| 421 | #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) | ||
| 422 | #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 | ||
| 423 | #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) | ||
| 424 | |||
| 425 | /* CM_CLKSEL1_PLL */ | ||
| 426 | /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ | ||
| 427 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 | ||
| 428 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) | ||
| 429 | #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 | ||
| 430 | #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) | ||
| 431 | #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 | ||
| 432 | #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) | ||
| 433 | #define OMAP3430_SOURCE_54M (1 << 5) | ||
| 434 | #define OMAP3430_SOURCE_48M (1 << 3) | ||
| 435 | |||
| 436 | /* CM_CLKSEL2_PLL */ | ||
| 437 | #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 | ||
| 438 | #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) | ||
| 439 | #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 | ||
| 440 | #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) | ||
| 441 | |||
| 442 | /* CM_CLKSEL3_PLL */ | ||
| 443 | #define OMAP3430_DIV_96M_SHIFT 0 | ||
| 444 | #define OMAP3430_DIV_96M_MASK (0x1f << 0) | ||
| 445 | |||
| 446 | /* CM_CLKSEL4_PLL */ | ||
| 447 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 | ||
| 448 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) | ||
| 449 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 | ||
| 450 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) | ||
| 451 | |||
| 452 | /* CM_CLKSEL5_PLL */ | ||
| 453 | #define OMAP3430ES2_DIV_120M_SHIFT 0 | ||
| 454 | #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) | ||
| 455 | |||
| 456 | /* CM_CLKOUT_CTRL */ | ||
| 457 | #define OMAP3430_CLKOUT2_EN_SHIFT 7 | ||
| 458 | #define OMAP3430_CLKOUT2_EN (1 << 7) | ||
| 459 | #define OMAP3430_CLKOUT2_DIV_SHIFT 3 | ||
| 460 | #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) | ||
| 461 | #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 | ||
| 462 | #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) | ||
| 463 | |||
| 464 | /* CM_FCLKEN_DSS */ | ||
| 465 | #define OMAP3430_EN_TV (1 << 2) | ||
| 466 | #define OMAP3430_EN_TV_SHIFT 2 | ||
| 467 | #define OMAP3430_EN_DSS2 (1 << 1) | ||
| 468 | #define OMAP3430_EN_DSS2_SHIFT 1 | ||
| 469 | #define OMAP3430_EN_DSS1 (1 << 0) | ||
| 470 | #define OMAP3430_EN_DSS1_SHIFT 0 | ||
| 471 | |||
| 472 | /* CM_ICLKEN_DSS */ | ||
| 473 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0) | ||
| 474 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 | ||
| 475 | |||
| 476 | /* CM_IDLEST_DSS */ | ||
| 477 | #define OMAP3430_ST_DSS (1 << 0) | ||
| 478 | |||
| 479 | /* CM_AUTOIDLE_DSS */ | ||
| 480 | #define OMAP3430_AUTO_DSS (1 << 0) | ||
| 481 | #define OMAP3430_AUTO_DSS_SHIFT 0 | ||
| 482 | |||
| 483 | /* CM_CLKSEL_DSS */ | ||
| 484 | #define OMAP3430_CLKSEL_TV_SHIFT 8 | ||
| 485 | #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) | ||
| 486 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 | ||
| 487 | #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) | ||
| 488 | |||
| 489 | /* CM_SLEEPDEP_DSS specific bits */ | ||
| 490 | |||
| 491 | /* CM_CLKSTCTRL_DSS */ | ||
| 492 | #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 | ||
| 493 | #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) | ||
| 494 | |||
| 495 | /* CM_CLKSTST_DSS */ | ||
| 496 | #define OMAP3430_CLKACTIVITY_DSS (1 << 0) | ||
| 497 | |||
| 498 | /* CM_FCLKEN_CAM specific bits */ | ||
| 499 | |||
| 500 | /* CM_ICLKEN_CAM specific bits */ | ||
| 501 | |||
| 502 | /* CM_IDLEST_CAM */ | ||
| 503 | #define OMAP3430_ST_CAM (1 << 0) | ||
| 504 | |||
| 505 | /* CM_AUTOIDLE_CAM */ | ||
| 506 | #define OMAP3430_AUTO_CAM (1 << 0) | ||
| 507 | #define OMAP3430_AUTO_CAM_SHIFT 0 | ||
| 508 | |||
| 509 | /* CM_CLKSEL_CAM */ | ||
| 510 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 | ||
| 511 | #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) | ||
| 512 | |||
| 513 | /* CM_SLEEPDEP_CAM specific bits */ | ||
| 514 | |||
| 515 | /* CM_CLKSTCTRL_CAM */ | ||
| 516 | #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 | ||
| 517 | #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) | ||
| 518 | |||
| 519 | /* CM_CLKSTST_CAM */ | ||
| 520 | #define OMAP3430_CLKACTIVITY_CAM (1 << 0) | ||
| 521 | |||
| 522 | /* CM_FCLKEN_PER specific bits */ | ||
| 523 | |||
| 524 | /* CM_ICLKEN_PER specific bits */ | ||
| 525 | |||
| 526 | /* CM_IDLEST_PER */ | ||
| 527 | #define OMAP3430_ST_WDT3 (1 << 12) | ||
| 528 | #define OMAP3430_ST_MCBSP4 (1 << 2) | ||
| 529 | #define OMAP3430_ST_MCBSP3 (1 << 1) | ||
| 530 | #define OMAP3430_ST_MCBSP2 (1 << 0) | ||
| 531 | |||
| 532 | /* CM_AUTOIDLE_PER */ | ||
| 533 | #define OMAP3430_AUTO_GPIO6 (1 << 17) | ||
| 534 | #define OMAP3430_AUTO_GPIO6_SHIFT 17 | ||
| 535 | #define OMAP3430_AUTO_GPIO5 (1 << 16) | ||
| 536 | #define OMAP3430_AUTO_GPIO5_SHIFT 16 | ||
| 537 | #define OMAP3430_AUTO_GPIO4 (1 << 15) | ||
| 538 | #define OMAP3430_AUTO_GPIO4_SHIFT 15 | ||
| 539 | #define OMAP3430_AUTO_GPIO3 (1 << 14) | ||
| 540 | #define OMAP3430_AUTO_GPIO3_SHIFT 14 | ||
| 541 | #define OMAP3430_AUTO_GPIO2 (1 << 13) | ||
| 542 | #define OMAP3430_AUTO_GPIO2_SHIFT 13 | ||
| 543 | #define OMAP3430_AUTO_WDT3 (1 << 12) | ||
| 544 | #define OMAP3430_AUTO_WDT3_SHIFT 12 | ||
| 545 | #define OMAP3430_AUTO_UART3 (1 << 11) | ||
| 546 | #define OMAP3430_AUTO_UART3_SHIFT 11 | ||
| 547 | #define OMAP3430_AUTO_GPT9 (1 << 10) | ||
| 548 | #define OMAP3430_AUTO_GPT9_SHIFT 10 | ||
| 549 | #define OMAP3430_AUTO_GPT8 (1 << 9) | ||
| 550 | #define OMAP3430_AUTO_GPT8_SHIFT 9 | ||
| 551 | #define OMAP3430_AUTO_GPT7 (1 << 8) | ||
| 552 | #define OMAP3430_AUTO_GPT7_SHIFT 8 | ||
| 553 | #define OMAP3430_AUTO_GPT6 (1 << 7) | ||
| 554 | #define OMAP3430_AUTO_GPT6_SHIFT 7 | ||
| 555 | #define OMAP3430_AUTO_GPT5 (1 << 6) | ||
| 556 | #define OMAP3430_AUTO_GPT5_SHIFT 6 | ||
| 557 | #define OMAP3430_AUTO_GPT4 (1 << 5) | ||
| 558 | #define OMAP3430_AUTO_GPT4_SHIFT 5 | ||
| 559 | #define OMAP3430_AUTO_GPT3 (1 << 4) | ||
| 560 | #define OMAP3430_AUTO_GPT3_SHIFT 4 | ||
| 561 | #define OMAP3430_AUTO_GPT2 (1 << 3) | ||
| 562 | #define OMAP3430_AUTO_GPT2_SHIFT 3 | ||
| 563 | #define OMAP3430_AUTO_MCBSP4 (1 << 2) | ||
| 564 | #define OMAP3430_AUTO_MCBSP4_SHIFT 2 | ||
| 565 | #define OMAP3430_AUTO_MCBSP3 (1 << 1) | ||
| 566 | #define OMAP3430_AUTO_MCBSP3_SHIFT 1 | ||
| 567 | #define OMAP3430_AUTO_MCBSP2 (1 << 0) | ||
| 568 | #define OMAP3430_AUTO_MCBSP2_SHIFT 0 | ||
| 569 | |||
| 570 | /* CM_CLKSEL_PER */ | ||
| 571 | #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) | ||
| 572 | #define OMAP3430_CLKSEL_GPT9_SHIFT 7 | ||
| 573 | #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) | ||
| 574 | #define OMAP3430_CLKSEL_GPT8_SHIFT 6 | ||
| 575 | #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) | ||
| 576 | #define OMAP3430_CLKSEL_GPT7_SHIFT 5 | ||
| 577 | #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) | ||
| 578 | #define OMAP3430_CLKSEL_GPT6_SHIFT 4 | ||
| 579 | #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) | ||
| 580 | #define OMAP3430_CLKSEL_GPT5_SHIFT 3 | ||
| 581 | #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) | ||
| 582 | #define OMAP3430_CLKSEL_GPT4_SHIFT 2 | ||
| 583 | #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) | ||
| 584 | #define OMAP3430_CLKSEL_GPT3_SHIFT 1 | ||
| 585 | #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) | ||
| 586 | #define OMAP3430_CLKSEL_GPT2_SHIFT 0 | ||
| 587 | |||
| 588 | /* CM_SLEEPDEP_PER specific bits */ | ||
| 589 | #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2) | ||
| 590 | |||
| 591 | /* CM_CLKSTCTRL_PER */ | ||
| 592 | #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 | ||
| 593 | #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) | ||
| 594 | |||
| 595 | /* CM_CLKSTST_PER */ | ||
| 596 | #define OMAP3430_CLKACTIVITY_PER (1 << 0) | ||
| 597 | |||
| 598 | /* CM_CLKSEL1_EMU */ | ||
| 599 | #define OMAP3430_DIV_DPLL4_SHIFT 24 | ||
| 600 | #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) | ||
| 601 | #define OMAP3430_DIV_DPLL3_SHIFT 16 | ||
| 602 | #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) | ||
| 603 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 | ||
| 604 | #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) | ||
| 605 | #define OMAP3430_CLKSEL_PCLK_SHIFT 8 | ||
| 606 | #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) | ||
| 607 | #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 | ||
| 608 | #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) | ||
| 609 | #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 | ||
| 610 | #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) | ||
| 611 | #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 | ||
| 612 | #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) | ||
| 613 | #define OMAP3430_MUX_CTRL_SHIFT 0 | ||
| 614 | #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) | ||
| 615 | |||
| 616 | /* CM_CLKSTCTRL_EMU */ | ||
| 617 | #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 | ||
| 618 | #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) | ||
| 619 | |||
| 620 | /* CM_CLKSTST_EMU */ | ||
| 621 | #define OMAP3430_CLKACTIVITY_EMU (1 << 0) | ||
| 622 | |||
| 623 | /* CM_CLKSEL2_EMU specific bits */ | ||
| 624 | #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 | ||
| 625 | #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) | ||
| 626 | #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 | ||
| 627 | #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) | ||
| 628 | |||
| 629 | /* CM_CLKSEL3_EMU specific bits */ | ||
| 630 | #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 | ||
| 631 | #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) | ||
| 632 | #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 | ||
| 633 | #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) | ||
| 634 | |||
| 635 | /* CM_POLCTRL */ | ||
| 636 | #define OMAP3430_CLKOUT2_POL (1 << 0) | ||
| 637 | |||
| 638 | /* CM_IDLEST_NEON */ | ||
| 639 | #define OMAP3430_ST_NEON (1 << 0) | ||
| 640 | |||
| 641 | /* CM_CLKSTCTRL_NEON */ | ||
| 642 | #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 | ||
| 643 | #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) | ||
| 644 | |||
| 645 | /* CM_FCLKEN_USBHOST */ | ||
| 646 | #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 | ||
| 647 | #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) | ||
| 648 | #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 | ||
| 649 | #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) | ||
| 650 | |||
| 651 | /* CM_ICLKEN_USBHOST */ | ||
| 652 | #define OMAP3430ES2_EN_USBHOST_SHIFT 0 | ||
| 653 | #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) | ||
| 654 | |||
| 655 | /* CM_IDLEST_USBHOST */ | ||
| 656 | |||
| 657 | /* CM_AUTOIDLE_USBHOST */ | ||
| 658 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | ||
| 659 | #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) | ||
| 660 | |||
| 661 | /* CM_SLEEPDEP_USBHOST */ | ||
| 662 | #define OMAP3430ES2_EN_MPU_SHIFT 1 | ||
| 663 | #define OMAP3430ES2_EN_MPU_MASK (1 << 1) | ||
| 664 | #define OMAP3430ES2_EN_IVA2_SHIFT 2 | ||
| 665 | #define OMAP3430ES2_EN_IVA2_MASK (1 << 2) | ||
| 666 | |||
| 667 | /* CM_CLKSTCTRL_USBHOST */ | ||
| 668 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 | ||
| 669 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) | ||
| 670 | |||
| 671 | |||
| 672 | |||
| 673 | #endif | ||
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h new file mode 100644 index 000000000000..8489f3029fed --- /dev/null +++ b/arch/arm/mach-omap2/cm.h | |||
| @@ -0,0 +1,124 @@ | |||
| 1 | #ifndef __ARCH_ASM_MACH_OMAP2_CM_H | ||
| 2 | #define __ARCH_ASM_MACH_OMAP2_CM_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * OMAP2/3 Clock Management (CM) register definitions | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | ||
| 8 | * Copyright (C) 2007-2008 Nokia Corporation | ||
| 9 | * | ||
| 10 | * Written by Paul Walmsley | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include "prcm-common.h" | ||
| 18 | |||
| 19 | #ifndef __ASSEMBLER__ | ||
| 20 | #define OMAP_CM_REGADDR(module, reg) \ | ||
| 21 | (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg)) | ||
| 22 | #else | ||
| 23 | #define OMAP2420_CM_REGADDR(module, reg) \ | ||
| 24 | IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) | ||
| 25 | #define OMAP2430_CM_REGADDR(module, reg) \ | ||
| 26 | IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) | ||
| 27 | #define OMAP34XX_CM_REGADDR(module, reg) \ | ||
| 28 | IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) | ||
| 29 | #endif | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Architecture-specific global CM registers | ||
| 33 | * Use cm_{read,write}_reg() with these registers. | ||
| 34 | * These registers appear once per CM module. | ||
| 35 | */ | ||
| 36 | |||
| 37 | #define OMAP3430_CM_REVISION OMAP_CM_REGADDR(OCP_MOD, 0x0000) | ||
| 38 | #define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010) | ||
| 39 | #define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c) | ||
| 40 | |||
| 41 | #define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) | ||
| 42 | |||
| 43 | /* | ||
| 44 | * Module specific CM registers from CM_BASE + domain offset | ||
| 45 | * Use cm_{read,write}_mod_reg() with these registers. | ||
| 46 | * These register offsets generally appear in more than one PRCM submodule. | ||
| 47 | */ | ||
| 48 | |||
| 49 | /* Common between 24xx and 34xx */ | ||
| 50 | |||
| 51 | #define CM_FCLKEN 0x0000 | ||
| 52 | #define CM_FCLKEN1 CM_FCLKEN | ||
| 53 | #define CM_CLKEN CM_FCLKEN | ||
| 54 | #define CM_ICLKEN 0x0010 | ||
| 55 | #define CM_ICLKEN1 CM_ICLKEN | ||
| 56 | #define CM_ICLKEN2 0x0014 | ||
| 57 | #define CM_ICLKEN3 0x0018 | ||
| 58 | #define CM_IDLEST 0x0020 | ||
| 59 | #define CM_IDLEST1 CM_IDLEST | ||
| 60 | #define CM_IDLEST2 0x0024 | ||
| 61 | #define CM_AUTOIDLE 0x0030 | ||
| 62 | #define CM_AUTOIDLE1 CM_AUTOIDLE | ||
| 63 | #define CM_AUTOIDLE2 0x0034 | ||
| 64 | #define CM_AUTOIDLE3 0x0038 | ||
| 65 | #define CM_CLKSEL 0x0040 | ||
| 66 | #define CM_CLKSEL1 CM_CLKSEL | ||
| 67 | #define CM_CLKSEL2 0x0044 | ||
| 68 | #define CM_CLKSTCTRL 0x0048 | ||
| 69 | |||
| 70 | |||
| 71 | /* Architecture-specific registers */ | ||
| 72 | |||
| 73 | #define OMAP24XX_CM_FCLKEN2 0x0004 | ||
| 74 | #define OMAP24XX_CM_ICLKEN4 0x001c | ||
| 75 | #define OMAP24XX_CM_AUTOIDLE4 0x003c | ||
| 76 | |||
| 77 | #define OMAP2430_CM_IDLEST3 0x0028 | ||
| 78 | |||
| 79 | #define OMAP3430_CM_CLKEN_PLL 0x0004 | ||
| 80 | #define OMAP3430ES2_CM_CLKEN2 0x0004 | ||
| 81 | #define OMAP3430ES2_CM_FCLKEN3 0x0008 | ||
| 82 | #define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 | ||
| 83 | #define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 | ||
| 84 | #define OMAP3430_CM_CLKSEL1 CM_CLKSEL | ||
| 85 | #define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL | ||
| 86 | #define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 | ||
| 87 | #define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 | ||
| 88 | #define OMAP3430_CM_CLKSEL3 CM_CLKSTCTRL | ||
| 89 | #define OMAP3430_CM_CLKSTST 0x004c | ||
| 90 | #define OMAP3430ES2_CM_CLKSEL4 0x004c | ||
| 91 | #define OMAP3430ES2_CM_CLKSEL5 0x0050 | ||
| 92 | #define OMAP3430_CM_CLKSEL2_EMU 0x0050 | ||
| 93 | #define OMAP3430_CM_CLKSEL3_EMU 0x0054 | ||
| 94 | |||
| 95 | |||
| 96 | /* Clock management domain register get/set */ | ||
| 97 | |||
| 98 | #ifndef __ASSEMBLER__ | ||
| 99 | static inline void cm_write_mod_reg(u32 val, s16 module, s16 idx) | ||
| 100 | { | ||
| 101 | __raw_writel(val, OMAP_CM_REGADDR(module, idx)); | ||
| 102 | } | ||
| 103 | |||
| 104 | static inline u32 cm_read_mod_reg(s16 module, s16 idx) | ||
| 105 | { | ||
| 106 | return __raw_readl(OMAP_CM_REGADDR(module, idx)); | ||
| 107 | } | ||
| 108 | #endif | ||
| 109 | |||
| 110 | /* CM register bits shared between 24XX and 3430 */ | ||
| 111 | |||
| 112 | /* CM_CLKSEL_GFX */ | ||
| 113 | #define OMAP_CLKSEL_GFX_SHIFT 0 | ||
| 114 | #define OMAP_CLKSEL_GFX_MASK (0x7 << 0) | ||
| 115 | |||
| 116 | /* CM_ICLKEN_GFX */ | ||
| 117 | #define OMAP_EN_GFX_SHIFT 0 | ||
| 118 | #define OMAP_EN_GFX (1 << 0) | ||
| 119 | |||
| 120 | /* CM_IDLEST_GFX */ | ||
| 121 | #define OMAP_ST_GFX (1 << 0) | ||
| 122 | |||
| 123 | |||
| 124 | #endif | ||
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c new file mode 100644 index 000000000000..a5d86a49c213 --- /dev/null +++ b/arch/arm/mach-omap2/control.c | |||
| @@ -0,0 +1,74 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2/3 System Control Module register access | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2007 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Written by Paul Walmsley | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | #undef DEBUG | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | |||
| 17 | #include <asm/io.h> | ||
| 18 | |||
| 19 | #include <asm/arch/control.h> | ||
| 20 | |||
| 21 | static u32 omap2_ctrl_base; | ||
| 22 | |||
| 23 | #define OMAP_CTRL_REGADDR(reg) (void __iomem *)IO_ADDRESS(omap2_ctrl_base \ | ||
| 24 | + (reg)) | ||
| 25 | |||
| 26 | void omap_ctrl_base_set(u32 base) | ||
| 27 | { | ||
| 28 | omap2_ctrl_base = base; | ||
| 29 | } | ||
| 30 | |||
| 31 | u32 omap_ctrl_base_get(void) | ||
| 32 | { | ||
| 33 | return omap2_ctrl_base; | ||
| 34 | } | ||
| 35 | |||
| 36 | u8 omap_ctrl_readb(u16 offset) | ||
| 37 | { | ||
| 38 | return __raw_readb(OMAP_CTRL_REGADDR(offset)); | ||
| 39 | } | ||
| 40 | |||
| 41 | u16 omap_ctrl_readw(u16 offset) | ||
| 42 | { | ||
| 43 | return __raw_readw(OMAP_CTRL_REGADDR(offset)); | ||
| 44 | } | ||
| 45 | |||
| 46 | u32 omap_ctrl_readl(u16 offset) | ||
| 47 | { | ||
| 48 | return __raw_readl(OMAP_CTRL_REGADDR(offset)); | ||
| 49 | } | ||
| 50 | |||
| 51 | void omap_ctrl_writeb(u8 val, u16 offset) | ||
| 52 | { | ||
| 53 | pr_debug("omap_ctrl_writeb: writing 0x%0x to 0x%0x\n", val, | ||
| 54 | (u32)OMAP_CTRL_REGADDR(offset)); | ||
| 55 | |||
| 56 | __raw_writeb(val, OMAP_CTRL_REGADDR(offset)); | ||
| 57 | } | ||
| 58 | |||
| 59 | void omap_ctrl_writew(u16 val, u16 offset) | ||
| 60 | { | ||
| 61 | pr_debug("omap_ctrl_writew: writing 0x%0x to 0x%0x\n", val, | ||
| 62 | (u32)OMAP_CTRL_REGADDR(offset)); | ||
| 63 | |||
| 64 | __raw_writew(val, OMAP_CTRL_REGADDR(offset)); | ||
| 65 | } | ||
| 66 | |||
| 67 | void omap_ctrl_writel(u32 val, u16 offset) | ||
| 68 | { | ||
| 69 | pr_debug("omap_ctrl_writel: writing 0x%0x to 0x%0x\n", val, | ||
| 70 | (u32)OMAP_CTRL_REGADDR(offset)); | ||
| 71 | |||
| 72 | __raw_writel(val, OMAP_CTRL_REGADDR(offset)); | ||
| 73 | } | ||
| 74 | |||
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 5a4cc2076a7d..02cede295e89 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c | |||
| @@ -69,7 +69,7 @@ static void __iomem *gpmc_base = | |||
| 69 | static void __iomem *gpmc_cs_base = | 69 | static void __iomem *gpmc_cs_base = |
| 70 | (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0; | 70 | (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0; |
| 71 | 71 | ||
| 72 | static struct clk *gpmc_l3_clk; | 72 | static struct clk *gpmc_fck; |
| 73 | 73 | ||
| 74 | static void gpmc_write_reg(int idx, u32 val) | 74 | static void gpmc_write_reg(int idx, u32 val) |
| 75 | { | 75 | { |
| @@ -94,11 +94,10 @@ u32 gpmc_cs_read_reg(int cs, int idx) | |||
| 94 | return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx); | 94 | return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx); |
| 95 | } | 95 | } |
| 96 | 96 | ||
| 97 | /* TODO: Add support for gpmc_fck to clock framework and use it */ | ||
| 98 | unsigned long gpmc_get_fclk_period(void) | 97 | unsigned long gpmc_get_fclk_period(void) |
| 99 | { | 98 | { |
| 100 | /* In picoseconds */ | 99 | /* In picoseconds */ |
| 101 | return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000); | 100 | return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000); |
| 102 | } | 101 | } |
| 103 | 102 | ||
| 104 | unsigned int gpmc_ns_to_ticks(unsigned int time_ns) | 103 | unsigned int gpmc_ns_to_ticks(unsigned int time_ns) |
| @@ -398,8 +397,11 @@ void __init gpmc_init(void) | |||
| 398 | { | 397 | { |
| 399 | u32 l; | 398 | u32 l; |
| 400 | 399 | ||
| 401 | gpmc_l3_clk = clk_get(NULL, "core_l3_ck"); | 400 | gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ |
| 402 | BUG_ON(IS_ERR(gpmc_l3_clk)); | 401 | if (IS_ERR(gpmc_fck)) |
| 402 | WARN_ON(1); | ||
| 403 | else | ||
| 404 | clk_enable(gpmc_fck); | ||
| 403 | 405 | ||
| 404 | l = gpmc_read_reg(GPMC_REVISION); | 406 | l = gpmc_read_reg(GPMC_REVISION); |
| 405 | printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); | 407 | printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); |
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c index 3e5d8cd4ea4f..12479081881a 100644 --- a/arch/arm/mach-omap2/memory.c +++ b/arch/arm/mach-omap2/memory.c | |||
| @@ -27,11 +27,16 @@ | |||
| 27 | #include <asm/arch/clock.h> | 27 | #include <asm/arch/clock.h> |
| 28 | #include <asm/arch/sram.h> | 28 | #include <asm/arch/sram.h> |
| 29 | 29 | ||
| 30 | #include "prcm-regs.h" | 30 | #include "prm.h" |
| 31 | |||
| 31 | #include "memory.h" | 32 | #include "memory.h" |
| 33 | #include "sdrc.h" | ||
| 32 | 34 | ||
| 35 | unsigned long omap2_sdrc_base; | ||
| 36 | unsigned long omap2_sms_base; | ||
| 33 | 37 | ||
| 34 | static struct memory_timings mem_timings; | 38 | static struct memory_timings mem_timings; |
| 39 | static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2; | ||
| 35 | 40 | ||
| 36 | u32 omap2_memory_get_slow_dll_ctrl(void) | 41 | u32 omap2_memory_get_slow_dll_ctrl(void) |
| 37 | { | 42 | { |
| @@ -48,12 +53,60 @@ u32 omap2_memory_get_type(void) | |||
| 48 | return mem_timings.m_type; | 53 | return mem_timings.m_type; |
| 49 | } | 54 | } |
| 50 | 55 | ||
| 56 | /* | ||
| 57 | * Check the DLL lock state, and return tue if running in unlock mode. | ||
| 58 | * This is needed to compensate for the shifted DLL value in unlock mode. | ||
| 59 | */ | ||
| 60 | u32 omap2_dll_force_needed(void) | ||
| 61 | { | ||
| 62 | /* dlla and dllb are a set */ | ||
| 63 | u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL); | ||
| 64 | |||
| 65 | if ((dll_state & (1 << 2)) == (1 << 2)) | ||
| 66 | return 1; | ||
| 67 | else | ||
| 68 | return 0; | ||
| 69 | } | ||
| 70 | |||
| 71 | /* | ||
| 72 | * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC. | ||
| 73 | * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or | ||
| 74 | * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2) | ||
| 75 | */ | ||
| 76 | u32 omap2_reprogram_sdrc(u32 level, u32 force) | ||
| 77 | { | ||
| 78 | u32 dll_ctrl, m_type; | ||
| 79 | u32 prev = curr_perf_level; | ||
| 80 | unsigned long flags; | ||
| 81 | |||
| 82 | if ((curr_perf_level == level) && !force) | ||
| 83 | return prev; | ||
| 84 | |||
| 85 | if (level == CORE_CLK_SRC_DPLL) { | ||
| 86 | dll_ctrl = omap2_memory_get_slow_dll_ctrl(); | ||
| 87 | } else if (level == CORE_CLK_SRC_DPLL_X2) { | ||
| 88 | dll_ctrl = omap2_memory_get_fast_dll_ctrl(); | ||
| 89 | } else { | ||
| 90 | return prev; | ||
| 91 | } | ||
| 92 | |||
| 93 | m_type = omap2_memory_get_type(); | ||
| 94 | |||
| 95 | local_irq_save(flags); | ||
| 96 | __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); | ||
| 97 | omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); | ||
| 98 | curr_perf_level = level; | ||
| 99 | local_irq_restore(flags); | ||
| 100 | |||
| 101 | return prev; | ||
| 102 | } | ||
| 103 | |||
| 51 | void omap2_init_memory_params(u32 force_lock_to_unlock_mode) | 104 | void omap2_init_memory_params(u32 force_lock_to_unlock_mode) |
| 52 | { | 105 | { |
| 53 | unsigned long dll_cnt; | 106 | unsigned long dll_cnt; |
| 54 | u32 fast_dll = 0; | 107 | u32 fast_dll = 0; |
| 55 | 108 | ||
| 56 | mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */ | 109 | mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */ |
| 57 | 110 | ||
| 58 | /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. | 111 | /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. |
| 59 | * In the case of 2422, its ok to use CS1 instead of CS0. | 112 | * In the case of 2422, its ok to use CS1 instead of CS0. |
| @@ -73,11 +126,11 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode) | |||
| 73 | mem_timings.dll_mode = M_LOCK; | 126 | mem_timings.dll_mode = M_LOCK; |
| 74 | 127 | ||
| 75 | if (mem_timings.base_cs == 0) { | 128 | if (mem_timings.base_cs == 0) { |
| 76 | fast_dll = SDRC_DLLA_CTRL; | 129 | fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL); |
| 77 | dll_cnt = SDRC_DLLA_STATUS & 0xff00; | 130 | dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00; |
| 78 | } else { | 131 | } else { |
| 79 | fast_dll = SDRC_DLLB_CTRL; | 132 | fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL); |
| 80 | dll_cnt = SDRC_DLLB_STATUS & 0xff00; | 133 | dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00; |
| 81 | } | 134 | } |
| 82 | if (force_lock_to_unlock_mode) { | 135 | if (force_lock_to_unlock_mode) { |
| 83 | fast_dll &= ~0xff00; | 136 | fast_dll &= ~0xff00; |
| @@ -106,14 +159,13 @@ void __init omap2_init_memory(void) | |||
| 106 | { | 159 | { |
| 107 | u32 l; | 160 | u32 l; |
| 108 | 161 | ||
| 109 | l = SMS_SYSCONFIG; | 162 | l = sms_read_reg(SMS_SYSCONFIG); |
| 110 | l &= ~(0x3 << 3); | 163 | l &= ~(0x3 << 3); |
| 111 | l |= (0x2 << 3); | 164 | l |= (0x2 << 3); |
| 112 | SMS_SYSCONFIG = l; | 165 | sms_write_reg(l, SMS_SYSCONFIG); |
| 113 | 166 | ||
| 114 | l = SDRC_SYSCONFIG; | 167 | l = sdrc_read_reg(SDRC_SYSCONFIG); |
| 115 | l &= ~(0x3 << 3); | 168 | l &= ~(0x3 << 3); |
| 116 | l |= (0x2 << 3); | 169 | l |= (0x2 << 3); |
| 117 | SDRC_SYSCONFIG = l; | 170 | sdrc_write_reg(l, SDRC_SYSCONFIG); |
| 118 | |||
| 119 | } | 171 | } |
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h index d212eea83a05..9a280b50a893 100644 --- a/arch/arm/mach-omap2/memory.h +++ b/arch/arm/mach-omap2/memory.h | |||
| @@ -32,3 +32,5 @@ extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode); | |||
| 32 | extern u32 omap2_memory_get_slow_dll_ctrl(void); | 32 | extern u32 omap2_memory_get_slow_dll_ctrl(void); |
| 33 | extern u32 omap2_memory_get_fast_dll_ctrl(void); | 33 | extern u32 omap2_memory_get_fast_dll_ctrl(void); |
| 34 | extern u32 omap2_memory_get_type(void); | 34 | extern u32 omap2_memory_get_type(void); |
| 35 | u32 omap2_dll_force_needed(void); | ||
| 36 | u32 omap2_reprogram_sdrc(u32 level, u32 force); | ||
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 05750975d746..930770012a75 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c | |||
| @@ -1,11 +1,12 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/mux.c | 2 | * linux/arch/arm/mach-omap2/mux.c |
| 3 | * | 3 | * |
| 4 | * OMAP1 pin multiplexing configurations | 4 | * OMAP2 pin multiplexing configurations |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2003 - 2005 Nokia Corporation | 6 | * Copyright (C) 2004 - 2008 Texas Instruments Inc. |
| 7 | * Copyright (C) 2003 - 2008 Nokia Corporation | ||
| 7 | * | 8 | * |
| 8 | * Written by Tony Lindgren <tony.lindgren@nokia.com> | 9 | * Written by Tony Lindgren |
| 9 | * | 10 | * |
| 10 | * This program is free software; you can redistribute it and/or modify | 11 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by | 12 | * it under the terms of the GNU General Public License as published by |
| @@ -28,13 +29,17 @@ | |||
| 28 | #include <asm/io.h> | 29 | #include <asm/io.h> |
| 29 | #include <linux/spinlock.h> | 30 | #include <linux/spinlock.h> |
| 30 | 31 | ||
| 32 | #include <asm/arch/control.h> | ||
| 31 | #include <asm/arch/mux.h> | 33 | #include <asm/arch/mux.h> |
| 32 | 34 | ||
| 33 | #ifdef CONFIG_OMAP_MUX | 35 | #ifdef CONFIG_OMAP_MUX |
| 34 | 36 | ||
| 37 | static struct omap_mux_cfg arch_mux_cfg; | ||
| 38 | |||
| 35 | /* NOTE: See mux.h for the enumeration */ | 39 | /* NOTE: See mux.h for the enumeration */ |
| 36 | 40 | ||
| 37 | struct pin_config __initdata_or_module omap24xx_pins[] = { | 41 | #ifdef CONFIG_ARCH_OMAP24XX |
| 42 | static struct pin_config __initdata_or_module omap24xx_pins[] = { | ||
| 38 | /* | 43 | /* |
| 39 | * description mux mux pull pull debug | 44 | * description mux mux pull pull debug |
| 40 | * offset mode ena type | 45 | * offset mode ena type |
| @@ -77,7 +82,12 @@ MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1) | |||
| 77 | MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1) | 82 | MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1) |
| 78 | MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1) | 83 | MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1) |
| 79 | MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1) | 84 | MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1) |
| 85 | MUX_CFG_24XX("N15_24XX_GPIO85", 0x103, 3, 0, 0, 1) | ||
| 80 | MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1) | 86 | MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1) |
| 87 | MUX_CFG_24XX("P20_24XX_GPIO93", 0x10b, 3, 0, 0, 1) | ||
| 88 | MUX_CFG_24XX("P18_24XX_GPIO95", 0x10d, 3, 0, 0, 1) | ||
| 89 | MUX_CFG_24XX("M18_24XX_GPIO96", 0x10e, 3, 0, 0, 1) | ||
| 90 | MUX_CFG_24XX("L14_24XX_GPIO97", 0x10f, 3, 0, 0, 1) | ||
| 81 | MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1) | 91 | MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1) |
| 82 | MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1) | 92 | MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1) |
| 83 | MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1) | 93 | MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1) |
| @@ -102,9 +112,6 @@ MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1) | |||
| 102 | MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1) | 112 | MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1) |
| 103 | MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1) | 113 | MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1) |
| 104 | 114 | ||
| 105 | /* TSC IRQ */ | ||
| 106 | MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1) | ||
| 107 | |||
| 108 | /* UART3 */ | 115 | /* UART3 */ |
| 109 | MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1) | 116 | MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1) |
| 110 | MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1) | 117 | MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1) |
| @@ -167,12 +174,108 @@ MUX_CFG_24XX("B3__24XX_KBR5", 0x30, 3, 1, 1, 1) | |||
| 167 | MUX_CFG_24XX("AA4_24XX_KBC2", 0xe7, 3, 0, 0, 1) | 174 | MUX_CFG_24XX("AA4_24XX_KBC2", 0xe7, 3, 0, 0, 1) |
| 168 | MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1) | 175 | MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1) |
| 169 | 176 | ||
| 177 | /* 2430 USB */ | ||
| 178 | MUX_CFG_24XX("AD9_2430_USB0_PUEN", 0x133, 4, 0, 0, 1) | ||
| 179 | MUX_CFG_24XX("Y11_2430_USB0_VP", 0x134, 4, 0, 0, 1) | ||
| 180 | MUX_CFG_24XX("AD7_2430_USB0_VM", 0x135, 4, 0, 0, 1) | ||
| 181 | MUX_CFG_24XX("AE7_2430_USB0_RCV", 0x136, 4, 0, 0, 1) | ||
| 182 | MUX_CFG_24XX("AD4_2430_USB0_TXEN", 0x137, 4, 0, 0, 1) | ||
| 183 | MUX_CFG_24XX("AF9_2430_USB0_SE0", 0x138, 4, 0, 0, 1) | ||
| 184 | MUX_CFG_24XX("AE6_2430_USB0_DAT", 0x139, 4, 0, 0, 1) | ||
| 185 | MUX_CFG_24XX("AD24_2430_USB1_SE0", 0x107, 2, 0, 0, 1) | ||
| 186 | MUX_CFG_24XX("AB24_2430_USB1_RCV", 0x108, 2, 0, 0, 1) | ||
| 187 | MUX_CFG_24XX("Y25_2430_USB1_TXEN", 0x109, 2, 0, 0, 1) | ||
| 188 | MUX_CFG_24XX("AA26_2430_USB1_DAT", 0x10A, 2, 0, 0, 1) | ||
| 189 | |||
| 190 | /* 2430 HS-USB */ | ||
| 191 | MUX_CFG_24XX("AD9_2430_USB0HS_DATA3", 0x133, 0, 0, 0, 1) | ||
| 192 | MUX_CFG_24XX("Y11_2430_USB0HS_DATA4", 0x134, 0, 0, 0, 1) | ||
| 193 | MUX_CFG_24XX("AD7_2430_USB0HS_DATA5", 0x135, 0, 0, 0, 1) | ||
| 194 | MUX_CFG_24XX("AE7_2430_USB0HS_DATA6", 0x136, 0, 0, 0, 1) | ||
| 195 | MUX_CFG_24XX("AD4_2430_USB0HS_DATA2", 0x137, 0, 0, 0, 1) | ||
| 196 | MUX_CFG_24XX("AF9_2430_USB0HS_DATA0", 0x138, 0, 0, 0, 1) | ||
| 197 | MUX_CFG_24XX("AE6_2430_USB0HS_DATA1", 0x139, 0, 0, 0, 1) | ||
| 198 | MUX_CFG_24XX("AE8_2430_USB0HS_CLK", 0x13A, 0, 0, 0, 1) | ||
| 199 | MUX_CFG_24XX("AD8_2430_USB0HS_DIR", 0x13B, 0, 0, 0, 1) | ||
| 200 | MUX_CFG_24XX("AE5_2430_USB0HS_STP", 0x13c, 0, 1, 1, 1) | ||
| 201 | MUX_CFG_24XX("AE9_2430_USB0HS_NXT", 0x13D, 0, 0, 0, 1) | ||
| 202 | MUX_CFG_24XX("AC7_2430_USB0HS_DATA7", 0x13E, 0, 0, 0, 1) | ||
| 203 | |||
| 204 | /* 2430 McBSP */ | ||
| 205 | MUX_CFG_24XX("AC10_2430_MCBSP2_FSX", 0x012E, 1, 0, 0, 1) | ||
| 206 | MUX_CFG_24XX("AD16_2430_MCBSP2_CLX", 0x012F, 1, 0, 0, 1) | ||
| 207 | MUX_CFG_24XX("AE13_2430_MCBSP2_DX", 0x0130, 1, 0, 0, 1) | ||
| 208 | MUX_CFG_24XX("AD13_2430_MCBSP2_DR", 0x0131, 1, 0, 0, 1) | ||
| 209 | MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0, 0, 0, 1) | ||
| 210 | MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1) | ||
| 211 | MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1) | ||
| 212 | MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1) | ||
| 170 | }; | 213 | }; |
| 171 | 214 | ||
| 172 | int __init omap2_mux_init(void) | 215 | #define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins) |
| 216 | |||
| 217 | #else | ||
| 218 | #define omap24xx_pins NULL | ||
| 219 | #define OMAP24XX_PINS_SZ 0 | ||
| 220 | #endif /* CONFIG_ARCH_OMAP24XX */ | ||
| 221 | |||
| 222 | #define OMAP24XX_PULL_ENA (1 << 3) | ||
| 223 | #define OMAP24XX_PULL_UP (1 << 4) | ||
| 224 | |||
| 225 | #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) | ||
| 226 | void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg) | ||
| 173 | { | 227 | { |
| 174 | omap_mux_register(omap24xx_pins, ARRAY_SIZE(omap24xx_pins)); | 228 | u16 orig; |
| 229 | u8 warn = 0, debug = 0; | ||
| 230 | |||
| 231 | orig = omap_ctrl_readb(cfg->mux_reg); | ||
| 232 | |||
| 233 | #ifdef CONFIG_OMAP_MUX_DEBUG | ||
| 234 | debug = cfg->debug; | ||
| 235 | #endif | ||
| 236 | warn = (orig != reg); | ||
| 237 | if (debug || warn) | ||
| 238 | printk(KERN_WARNING | ||
| 239 | "MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n", | ||
| 240 | cfg->name, omap_ctrl_base_get() + cfg->mux_reg, | ||
| 241 | orig, reg); | ||
| 242 | } | ||
| 243 | #else | ||
| 244 | #define omap2_cfg_debug(x, y) do {} while (0) | ||
| 245 | #endif | ||
| 246 | |||
| 247 | #ifdef CONFIG_ARCH_OMAP24XX | ||
| 248 | int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) | ||
| 249 | { | ||
| 250 | static DEFINE_SPINLOCK(mux_spin_lock); | ||
| 251 | unsigned long flags; | ||
| 252 | u8 reg = 0; | ||
| 253 | |||
| 254 | spin_lock_irqsave(&mux_spin_lock, flags); | ||
| 255 | reg |= cfg->mask & 0x7; | ||
| 256 | if (cfg->pull_val) | ||
| 257 | reg |= OMAP24XX_PULL_ENA; | ||
| 258 | if (cfg->pu_pd_val) | ||
| 259 | reg |= OMAP24XX_PULL_UP; | ||
| 260 | omap2_cfg_debug(cfg, reg); | ||
| 261 | omap_ctrl_writeb(reg, cfg->mux_reg); | ||
| 262 | spin_unlock_irqrestore(&mux_spin_lock, flags); | ||
| 263 | |||
| 175 | return 0; | 264 | return 0; |
| 176 | } | 265 | } |
| 266 | #else | ||
| 267 | #define omap24xx_cfg_reg 0 | ||
| 268 | #endif | ||
| 269 | |||
| 270 | int __init omap2_mux_init(void) | ||
| 271 | { | ||
| 272 | if (cpu_is_omap24xx()) { | ||
| 273 | arch_mux_cfg.pins = omap24xx_pins; | ||
| 274 | arch_mux_cfg.size = OMAP24XX_PINS_SZ; | ||
| 275 | arch_mux_cfg.cfg_reg = omap24xx_cfg_reg; | ||
| 276 | } | ||
| 277 | |||
| 278 | return omap_mux_register(&arch_mux_cfg); | ||
| 279 | } | ||
| 177 | 280 | ||
| 178 | #endif | 281 | #endif |
diff --git a/arch/arm/mach-omap2/pm-domain.c b/arch/arm/mach-omap2/pm-domain.c deleted file mode 100644 index 2494091a078b..000000000000 --- a/arch/arm/mach-omap2/pm-domain.c +++ /dev/null | |||
| @@ -1,299 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/pm-domain.c | ||
| 3 | * | ||
| 4 | * Power domain functions for OMAP2 | ||
| 5 | * | ||
| 6 | * Copyright (C) 2006 Nokia Corporation | ||
| 7 | * Tony Lindgren <tony@atomide.com> | ||
| 8 | * | ||
| 9 | * Some code based on earlier OMAP2 sample PM code | ||
| 10 | * Copyright (C) 2005 Texas Instruments, Inc. | ||
| 11 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 12 | * | ||
| 13 | * This program is free software; you can redistribute it and/or modify | ||
| 14 | * it under the terms of the GNU General Public License version 2 as | ||
| 15 | * published by the Free Software Foundation. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include <linux/module.h> | ||
| 19 | #include <linux/init.h> | ||
| 20 | #include <linux/clk.h> | ||
| 21 | |||
| 22 | #include <asm/io.h> | ||
| 23 | |||
| 24 | #include "prcm-regs.h" | ||
| 25 | |||
| 26 | /* Power domain offsets */ | ||
| 27 | #define PM_MPU_OFFSET 0x100 | ||
| 28 | #define PM_CORE_OFFSET 0x200 | ||
| 29 | #define PM_GFX_OFFSET 0x300 | ||
| 30 | #define PM_WKUP_OFFSET 0x400 /* Autoidle only */ | ||
| 31 | #define PM_PLL_OFFSET 0x500 /* Autoidle only */ | ||
| 32 | #define PM_DSP_OFFSET 0x800 | ||
| 33 | #define PM_MDM_OFFSET 0xc00 | ||
| 34 | |||
| 35 | /* Power domain wake-up dependency control register */ | ||
| 36 | #define PM_WKDEP_OFFSET 0xc8 | ||
| 37 | #define EN_MDM (1 << 5) | ||
| 38 | #define EN_WKUP (1 << 4) | ||
| 39 | #define EN_GFX (1 << 3) | ||
| 40 | #define EN_DSP (1 << 2) | ||
| 41 | #define EN_MPU (1 << 1) | ||
| 42 | #define EN_CORE (1 << 0) | ||
| 43 | |||
| 44 | /* Core power domain state transition control register */ | ||
| 45 | #define PM_PWSTCTRL_OFFSET 0xe0 | ||
| 46 | #define FORCESTATE (1 << 18) /* Only for DSP & GFX */ | ||
| 47 | #define MEM4RETSTATE (1 << 6) | ||
| 48 | #define MEM3RETSTATE (1 << 5) | ||
| 49 | #define MEM2RETSTATE (1 << 4) | ||
| 50 | #define MEM1RETSTATE (1 << 3) | ||
| 51 | #define LOGICRETSTATE (1 << 2) /* Logic is retained */ | ||
| 52 | #define POWERSTATE_OFF 0x3 | ||
| 53 | #define POWERSTATE_RETENTION 0x1 | ||
| 54 | #define POWERSTATE_ON 0x0 | ||
| 55 | |||
| 56 | /* Power domain state register */ | ||
| 57 | #define PM_PWSTST_OFFSET 0xe4 | ||
| 58 | |||
| 59 | /* Hardware supervised state transition control register */ | ||
| 60 | #define CM_CLKSTCTRL_OFFSET 0x48 | ||
| 61 | #define AUTOSTAT_MPU (1 << 0) /* MPU */ | ||
| 62 | #define AUTOSTAT_DSS (1 << 2) /* Core */ | ||
| 63 | #define AUTOSTAT_L4 (1 << 1) /* Core */ | ||
| 64 | #define AUTOSTAT_L3 (1 << 0) /* Core */ | ||
| 65 | #define AUTOSTAT_GFX (1 << 0) /* GFX */ | ||
| 66 | #define AUTOSTAT_IVA (1 << 8) /* 2420 IVA in DSP domain */ | ||
| 67 | #define AUTOSTAT_DSP (1 << 0) /* DSP */ | ||
| 68 | #define AUTOSTAT_MDM (1 << 0) /* MDM */ | ||
| 69 | |||
| 70 | /* Automatic control of interface clock idling */ | ||
| 71 | #define CM_AUTOIDLE1_OFFSET 0x30 | ||
| 72 | #define CM_AUTOIDLE2_OFFSET 0x34 /* Core only */ | ||
| 73 | #define CM_AUTOIDLE3_OFFSET 0x38 /* Core only */ | ||
| 74 | #define CM_AUTOIDLE4_OFFSET 0x3c /* Core only */ | ||
| 75 | #define AUTO_54M(x) (((x) & 0x3) << 6) | ||
| 76 | #define AUTO_96M(x) (((x) & 0x3) << 2) | ||
| 77 | #define AUTO_DPLL(x) (((x) & 0x3) << 0) | ||
| 78 | #define AUTO_STOPPED 0x3 | ||
| 79 | #define AUTO_BYPASS_FAST 0x2 /* DPLL only */ | ||
| 80 | #define AUTO_BYPASS_LOW_POWER 0x1 /* DPLL only */ | ||
| 81 | #define AUTO_DISABLED 0x0 | ||
| 82 | |||
| 83 | /* Voltage control PRCM_VOLTCTRL bits */ | ||
| 84 | #define AUTO_EXTVOLT (1 << 15) | ||
| 85 | #define FORCE_EXTVOLT (1 << 14) | ||
| 86 | #define SETOFF_LEVEL(x) (((x) & 0x3) << 12) | ||
| 87 | #define MEMRETCTRL (1 << 8) | ||
| 88 | #define SETRET_LEVEL(x) (((x) & 0x3) << 6) | ||
| 89 | #define VOLT_LEVEL(x) (((x) & 0x3) << 0) | ||
| 90 | |||
| 91 | #define OMAP24XX_PRCM_VBASE IO_ADDRESS(OMAP24XX_PRCM_BASE) | ||
| 92 | #define prcm_readl(r) __raw_readl(OMAP24XX_PRCM_VBASE + (r)) | ||
| 93 | #define prcm_writel(v, r) __raw_writel((v), OMAP24XX_PRCM_VBASE + (r)) | ||
| 94 | |||
| 95 | static u32 pmdomain_get_wakeup_dependencies(int domain_offset) | ||
| 96 | { | ||
| 97 | return prcm_readl(domain_offset + PM_WKDEP_OFFSET); | ||
| 98 | } | ||
| 99 | |||
| 100 | static void pmdomain_set_wakeup_dependencies(u32 state, int domain_offset) | ||
| 101 | { | ||
| 102 | prcm_writel(state, domain_offset + PM_WKDEP_OFFSET); | ||
| 103 | } | ||
| 104 | |||
| 105 | static u32 pmdomain_get_powerstate(int domain_offset) | ||
| 106 | { | ||
| 107 | return prcm_readl(domain_offset + PM_PWSTCTRL_OFFSET); | ||
| 108 | } | ||
| 109 | |||
| 110 | static void pmdomain_set_powerstate(u32 state, int domain_offset) | ||
| 111 | { | ||
| 112 | prcm_writel(state, domain_offset + PM_PWSTCTRL_OFFSET); | ||
| 113 | } | ||
| 114 | |||
| 115 | static u32 pmdomain_get_clock_autocontrol(int domain_offset) | ||
| 116 | { | ||
| 117 | return prcm_readl(domain_offset + CM_CLKSTCTRL_OFFSET); | ||
| 118 | } | ||
| 119 | |||
| 120 | static void pmdomain_set_clock_autocontrol(u32 state, int domain_offset) | ||
| 121 | { | ||
| 122 | prcm_writel(state, domain_offset + CM_CLKSTCTRL_OFFSET); | ||
| 123 | } | ||
| 124 | |||
| 125 | static u32 pmdomain_get_clock_autoidle1(int domain_offset) | ||
| 126 | { | ||
| 127 | return prcm_readl(domain_offset + CM_AUTOIDLE1_OFFSET); | ||
| 128 | } | ||
| 129 | |||
| 130 | /* Core domain only */ | ||
| 131 | static u32 pmdomain_get_clock_autoidle2(int domain_offset) | ||
| 132 | { | ||
| 133 | return prcm_readl(domain_offset + CM_AUTOIDLE2_OFFSET); | ||
| 134 | } | ||
| 135 | |||
| 136 | /* Core domain only */ | ||
| 137 | static u32 pmdomain_get_clock_autoidle3(int domain_offset) | ||
| 138 | { | ||
| 139 | return prcm_readl(domain_offset + CM_AUTOIDLE3_OFFSET); | ||
| 140 | } | ||
| 141 | |||
| 142 | /* Core domain only */ | ||
| 143 | static u32 pmdomain_get_clock_autoidle4(int domain_offset) | ||
| 144 | { | ||
| 145 | return prcm_readl(domain_offset + CM_AUTOIDLE4_OFFSET); | ||
| 146 | } | ||
| 147 | |||
| 148 | static void pmdomain_set_clock_autoidle1(u32 state, int domain_offset) | ||
| 149 | { | ||
| 150 | prcm_writel(state, CM_AUTOIDLE1_OFFSET + domain_offset); | ||
| 151 | } | ||
| 152 | |||
| 153 | /* Core domain only */ | ||
| 154 | static void pmdomain_set_clock_autoidle2(u32 state, int domain_offset) | ||
| 155 | { | ||
| 156 | prcm_writel(state, CM_AUTOIDLE2_OFFSET + domain_offset); | ||
| 157 | } | ||
| 158 | |||
| 159 | /* Core domain only */ | ||
| 160 | static void pmdomain_set_clock_autoidle3(u32 state, int domain_offset) | ||
| 161 | { | ||
| 162 | prcm_writel(state, CM_AUTOIDLE3_OFFSET + domain_offset); | ||
| 163 | } | ||
| 164 | |||
| 165 | /* Core domain only */ | ||
| 166 | static void pmdomain_set_clock_autoidle4(u32 state, int domain_offset) | ||
| 167 | { | ||
| 168 | prcm_writel(state, CM_AUTOIDLE4_OFFSET + domain_offset); | ||
| 169 | } | ||
| 170 | |||
| 171 | /* | ||
| 172 | * Configures power management domains to idle clocks automatically. | ||
| 173 | */ | ||
| 174 | void pmdomain_set_autoidle(void) | ||
| 175 | { | ||
| 176 | u32 val; | ||
| 177 | |||
| 178 | /* Set PLL auto stop for 54M, 96M & DPLL */ | ||
| 179 | pmdomain_set_clock_autoidle1(AUTO_54M(AUTO_STOPPED) | | ||
| 180 | AUTO_96M(AUTO_STOPPED) | | ||
| 181 | AUTO_DPLL(AUTO_STOPPED), PM_PLL_OFFSET); | ||
| 182 | |||
| 183 | /* External clock input control | ||
| 184 | * REVISIT: Should this be in clock framework? | ||
| 185 | */ | ||
| 186 | PRCM_CLKSRC_CTRL |= (0x3 << 3); | ||
| 187 | |||
| 188 | /* Configure number of 32KHz clock cycles for sys_clk */ | ||
| 189 | PRCM_CLKSSETUP = 0x00ff; | ||
| 190 | |||
| 191 | /* Configure automatic voltage transition */ | ||
| 192 | PRCM_VOLTSETUP = 0; | ||
| 193 | val = PRCM_VOLTCTRL; | ||
| 194 | val &= ~(SETOFF_LEVEL(0x3) | VOLT_LEVEL(0x3)); | ||
| 195 | val |= SETOFF_LEVEL(1) | VOLT_LEVEL(1) | AUTO_EXTVOLT; | ||
| 196 | PRCM_VOLTCTRL = val; | ||
| 197 | |||
| 198 | /* Disable emulation tools functional clock */ | ||
| 199 | PRCM_CLKEMUL_CTRL = 0x0; | ||
| 200 | |||
| 201 | /* Set core memory retention state */ | ||
| 202 | val = pmdomain_get_powerstate(PM_CORE_OFFSET); | ||
| 203 | if (cpu_is_omap2420()) { | ||
| 204 | val &= ~(0x7 << 3); | ||
| 205 | val |= (MEM3RETSTATE | MEM2RETSTATE | MEM1RETSTATE); | ||
| 206 | } else { | ||
| 207 | val &= ~(0xf << 3); | ||
| 208 | val |= (MEM4RETSTATE | MEM3RETSTATE | MEM2RETSTATE | | ||
| 209 | MEM1RETSTATE); | ||
| 210 | } | ||
| 211 | pmdomain_set_powerstate(val, PM_CORE_OFFSET); | ||
| 212 | |||
| 213 | /* OCP interface smart idle. REVISIT: Enable autoidle bit0 ? */ | ||
| 214 | val = SMS_SYSCONFIG; | ||
| 215 | val &= ~(0x3 << 3); | ||
| 216 | val |= (0x2 << 3) | (1 << 0); | ||
| 217 | SMS_SYSCONFIG |= val; | ||
| 218 | |||
| 219 | val = SDRC_SYSCONFIG; | ||
| 220 | val &= ~(0x3 << 3); | ||
| 221 | val |= (0x2 << 3); | ||
| 222 | SDRC_SYSCONFIG = val; | ||
| 223 | |||
| 224 | /* Configure L3 interface for smart idle. | ||
| 225 | * REVISIT: Enable autoidle bit0 ? | ||
| 226 | */ | ||
| 227 | val = GPMC_SYSCONFIG; | ||
| 228 | val &= ~(0x3 << 3); | ||
| 229 | val |= (0x2 << 3) | (1 << 0); | ||
| 230 | GPMC_SYSCONFIG = val; | ||
| 231 | |||
| 232 | pmdomain_set_powerstate(LOGICRETSTATE | POWERSTATE_RETENTION, | ||
| 233 | PM_MPU_OFFSET); | ||
| 234 | pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_CORE_OFFSET); | ||
| 235 | if (!cpu_is_omap2420()) | ||
| 236 | pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_MDM_OFFSET); | ||
| 237 | |||
| 238 | /* Assume suspend function has saved the state for DSP and GFX */ | ||
| 239 | pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_DSP_OFFSET); | ||
| 240 | pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_GFX_OFFSET); | ||
| 241 | |||
| 242 | #if 0 | ||
| 243 | /* REVISIT: Internal USB needs special handling */ | ||
| 244 | force_standby_usb(); | ||
| 245 | if (cpu_is_omap2430()) | ||
| 246 | force_hsmmc(); | ||
| 247 | sdram_self_refresh_on_idle_req(1); | ||
| 248 | #endif | ||
| 249 | |||
| 250 | /* Enable clock auto control for all domains. | ||
| 251 | * Note that CORE domain includes also DSS, L4 & L3. | ||
| 252 | */ | ||
| 253 | pmdomain_set_clock_autocontrol(AUTOSTAT_MPU, PM_MPU_OFFSET); | ||
| 254 | pmdomain_set_clock_autocontrol(AUTOSTAT_GFX, PM_GFX_OFFSET); | ||
| 255 | pmdomain_set_clock_autocontrol(AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3, | ||
| 256 | PM_CORE_OFFSET); | ||
| 257 | if (cpu_is_omap2420()) | ||
| 258 | pmdomain_set_clock_autocontrol(AUTOSTAT_IVA | AUTOSTAT_DSP, | ||
| 259 | PM_DSP_OFFSET); | ||
| 260 | else { | ||
| 261 | pmdomain_set_clock_autocontrol(AUTOSTAT_DSP, PM_DSP_OFFSET); | ||
| 262 | pmdomain_set_clock_autocontrol(AUTOSTAT_MDM, PM_MDM_OFFSET); | ||
| 263 | } | ||
| 264 | |||
| 265 | /* Enable clock autoidle for all domains */ | ||
| 266 | pmdomain_set_clock_autoidle1(0x2, PM_DSP_OFFSET); | ||
| 267 | if (cpu_is_omap2420()) { | ||
| 268 | pmdomain_set_clock_autoidle1(0xfffffff9, PM_CORE_OFFSET); | ||
| 269 | pmdomain_set_clock_autoidle2(0x7, PM_CORE_OFFSET); | ||
| 270 | pmdomain_set_clock_autoidle1(0x3f, PM_WKUP_OFFSET); | ||
| 271 | } else { | ||
| 272 | pmdomain_set_clock_autoidle1(0xeafffff1, PM_CORE_OFFSET); | ||
| 273 | pmdomain_set_clock_autoidle2(0xfff, PM_CORE_OFFSET); | ||
| 274 | pmdomain_set_clock_autoidle1(0x7f, PM_WKUP_OFFSET); | ||
| 275 | pmdomain_set_clock_autoidle1(0x3, PM_MDM_OFFSET); | ||
| 276 | } | ||
| 277 | pmdomain_set_clock_autoidle3(0x7, PM_CORE_OFFSET); | ||
| 278 | pmdomain_set_clock_autoidle4(0x1f, PM_CORE_OFFSET); | ||
| 279 | } | ||
| 280 | |||
| 281 | /* | ||
| 282 | * Initializes power domains by removing wake-up dependencies and powering | ||
| 283 | * down DSP and GFX. Gets called from PM init. Note that DSP and IVA code | ||
| 284 | * must re-enable DSP and GFX when used. | ||
| 285 | */ | ||
| 286 | void __init pmdomain_init(void) | ||
| 287 | { | ||
| 288 | /* Remove all domain wakeup dependencies */ | ||
| 289 | pmdomain_set_wakeup_dependencies(EN_WKUP | EN_CORE, PM_MPU_OFFSET); | ||
| 290 | pmdomain_set_wakeup_dependencies(0, PM_DSP_OFFSET); | ||
| 291 | pmdomain_set_wakeup_dependencies(0, PM_GFX_OFFSET); | ||
| 292 | pmdomain_set_wakeup_dependencies(EN_WKUP | EN_MPU, PM_CORE_OFFSET); | ||
| 293 | if (cpu_is_omap2430()) | ||
| 294 | pmdomain_set_wakeup_dependencies(0, PM_MDM_OFFSET); | ||
| 295 | |||
| 296 | /* Power down DSP and GFX */ | ||
| 297 | pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_DSP_OFFSET); | ||
| 298 | pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_GFX_OFFSET); | ||
| 299 | } | ||
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index baf7d82b458b..aad781dcf1b1 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/sysfs.h> | 23 | #include <linux/sysfs.h> |
| 24 | #include <linux/module.h> | 24 | #include <linux/module.h> |
| 25 | #include <linux/delay.h> | 25 | #include <linux/delay.h> |
| 26 | #include <linux/clk.h> | ||
| 26 | 27 | ||
| 27 | #include <asm/io.h> | 28 | #include <asm/io.h> |
| 28 | #include <asm/irq.h> | 29 | #include <asm/irq.h> |
| @@ -36,8 +37,6 @@ | |||
| 36 | #include <asm/arch/sram.h> | 37 | #include <asm/arch/sram.h> |
| 37 | #include <asm/arch/pm.h> | 38 | #include <asm/arch/pm.h> |
| 38 | 39 | ||
| 39 | #include "prcm-regs.h" | ||
| 40 | |||
| 41 | static struct clk *vclk; | 40 | static struct clk *vclk; |
| 42 | static void (*omap2_sram_idle)(void); | 41 | static void (*omap2_sram_idle)(void); |
| 43 | static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev); | 42 | static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev); |
| @@ -78,251 +77,8 @@ static int omap2_pm_prepare(void) | |||
| 78 | return 0; | 77 | return 0; |
| 79 | } | 78 | } |
| 80 | 79 | ||
| 81 | #define INT0_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK1) | \ | ||
| 82 | OMAP_IRQ_BIT(INT_24XX_GPIO_BANK2) | \ | ||
| 83 | OMAP_IRQ_BIT(INT_24XX_GPIO_BANK3)) | ||
| 84 | |||
| 85 | #define INT1_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK4)) | ||
| 86 | |||
| 87 | #define INT2_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_UART1_IRQ) | \ | ||
| 88 | OMAP_IRQ_BIT(INT_24XX_UART2_IRQ) | \ | ||
| 89 | OMAP_IRQ_BIT(INT_24XX_UART3_IRQ)) | ||
| 90 | |||
| 91 | #define preg(reg) printk("%s\t(0x%p):\t0x%08x\n", #reg, ®, reg); | ||
| 92 | |||
| 93 | static void omap2_pm_debug(char * desc) | ||
| 94 | { | ||
| 95 | printk("%s:\n", desc); | ||
| 96 | |||
| 97 | preg(CM_CLKSTCTRL_MPU); | ||
| 98 | preg(CM_CLKSTCTRL_CORE); | ||
| 99 | preg(CM_CLKSTCTRL_GFX); | ||
| 100 | preg(CM_CLKSTCTRL_DSP); | ||
| 101 | preg(CM_CLKSTCTRL_MDM); | ||
| 102 | |||
| 103 | preg(PM_PWSTCTRL_MPU); | ||
| 104 | preg(PM_PWSTCTRL_CORE); | ||
| 105 | preg(PM_PWSTCTRL_GFX); | ||
| 106 | preg(PM_PWSTCTRL_DSP); | ||
| 107 | preg(PM_PWSTCTRL_MDM); | ||
| 108 | |||
| 109 | preg(PM_PWSTST_MPU); | ||
| 110 | preg(PM_PWSTST_CORE); | ||
| 111 | preg(PM_PWSTST_GFX); | ||
| 112 | preg(PM_PWSTST_DSP); | ||
| 113 | preg(PM_PWSTST_MDM); | ||
| 114 | |||
| 115 | preg(CM_AUTOIDLE1_CORE); | ||
| 116 | preg(CM_AUTOIDLE2_CORE); | ||
| 117 | preg(CM_AUTOIDLE3_CORE); | ||
| 118 | preg(CM_AUTOIDLE4_CORE); | ||
| 119 | preg(CM_AUTOIDLE_WKUP); | ||
| 120 | preg(CM_AUTOIDLE_PLL); | ||
| 121 | preg(CM_AUTOIDLE_DSP); | ||
| 122 | preg(CM_AUTOIDLE_MDM); | ||
| 123 | |||
| 124 | preg(CM_ICLKEN1_CORE); | ||
| 125 | preg(CM_ICLKEN2_CORE); | ||
| 126 | preg(CM_ICLKEN3_CORE); | ||
| 127 | preg(CM_ICLKEN4_CORE); | ||
| 128 | preg(CM_ICLKEN_GFX); | ||
| 129 | preg(CM_ICLKEN_WKUP); | ||
| 130 | preg(CM_ICLKEN_DSP); | ||
| 131 | preg(CM_ICLKEN_MDM); | ||
| 132 | |||
| 133 | preg(CM_IDLEST1_CORE); | ||
| 134 | preg(CM_IDLEST2_CORE); | ||
| 135 | preg(CM_IDLEST3_CORE); | ||
| 136 | preg(CM_IDLEST4_CORE); | ||
| 137 | preg(CM_IDLEST_GFX); | ||
| 138 | preg(CM_IDLEST_WKUP); | ||
| 139 | preg(CM_IDLEST_CKGEN); | ||
| 140 | preg(CM_IDLEST_DSP); | ||
| 141 | preg(CM_IDLEST_MDM); | ||
| 142 | |||
| 143 | preg(RM_RSTST_MPU); | ||
| 144 | preg(RM_RSTST_GFX); | ||
| 145 | preg(RM_RSTST_WKUP); | ||
| 146 | preg(RM_RSTST_DSP); | ||
| 147 | preg(RM_RSTST_MDM); | ||
| 148 | |||
| 149 | preg(PM_WKDEP_MPU); | ||
| 150 | preg(PM_WKDEP_CORE); | ||
| 151 | preg(PM_WKDEP_GFX); | ||
| 152 | preg(PM_WKDEP_DSP); | ||
| 153 | preg(PM_WKDEP_MDM); | ||
| 154 | |||
| 155 | preg(CM_FCLKEN_WKUP); | ||
| 156 | preg(CM_ICLKEN_WKUP); | ||
| 157 | preg(CM_IDLEST_WKUP); | ||
| 158 | preg(CM_AUTOIDLE_WKUP); | ||
| 159 | preg(CM_CLKSEL_WKUP); | ||
| 160 | |||
| 161 | preg(PM_WKEN_WKUP); | ||
| 162 | preg(PM_WKST_WKUP); | ||
| 163 | } | ||
| 164 | |||
| 165 | static inline void omap2_pm_save_registers(void) | ||
| 166 | { | ||
| 167 | /* Save interrupt registers */ | ||
| 168 | OMAP24XX_SAVE(INTC_MIR0); | ||
| 169 | OMAP24XX_SAVE(INTC_MIR1); | ||
| 170 | OMAP24XX_SAVE(INTC_MIR2); | ||
| 171 | |||
| 172 | /* Save power control registers */ | ||
| 173 | OMAP24XX_SAVE(CM_CLKSTCTRL_MPU); | ||
| 174 | OMAP24XX_SAVE(CM_CLKSTCTRL_CORE); | ||
| 175 | OMAP24XX_SAVE(CM_CLKSTCTRL_GFX); | ||
| 176 | OMAP24XX_SAVE(CM_CLKSTCTRL_DSP); | ||
| 177 | OMAP24XX_SAVE(CM_CLKSTCTRL_MDM); | ||
| 178 | |||
| 179 | /* Save power state registers */ | ||
| 180 | OMAP24XX_SAVE(PM_PWSTCTRL_MPU); | ||
| 181 | OMAP24XX_SAVE(PM_PWSTCTRL_CORE); | ||
| 182 | OMAP24XX_SAVE(PM_PWSTCTRL_GFX); | ||
| 183 | OMAP24XX_SAVE(PM_PWSTCTRL_DSP); | ||
| 184 | OMAP24XX_SAVE(PM_PWSTCTRL_MDM); | ||
| 185 | |||
| 186 | /* Save autoidle registers */ | ||
| 187 | OMAP24XX_SAVE(CM_AUTOIDLE1_CORE); | ||
| 188 | OMAP24XX_SAVE(CM_AUTOIDLE2_CORE); | ||
| 189 | OMAP24XX_SAVE(CM_AUTOIDLE3_CORE); | ||
| 190 | OMAP24XX_SAVE(CM_AUTOIDLE4_CORE); | ||
| 191 | OMAP24XX_SAVE(CM_AUTOIDLE_WKUP); | ||
| 192 | OMAP24XX_SAVE(CM_AUTOIDLE_PLL); | ||
| 193 | OMAP24XX_SAVE(CM_AUTOIDLE_DSP); | ||
| 194 | OMAP24XX_SAVE(CM_AUTOIDLE_MDM); | ||
| 195 | |||
| 196 | /* Save idle state registers */ | ||
| 197 | OMAP24XX_SAVE(CM_IDLEST1_CORE); | ||
| 198 | OMAP24XX_SAVE(CM_IDLEST2_CORE); | ||
| 199 | OMAP24XX_SAVE(CM_IDLEST3_CORE); | ||
| 200 | OMAP24XX_SAVE(CM_IDLEST4_CORE); | ||
| 201 | OMAP24XX_SAVE(CM_IDLEST_GFX); | ||
| 202 | OMAP24XX_SAVE(CM_IDLEST_WKUP); | ||
| 203 | OMAP24XX_SAVE(CM_IDLEST_CKGEN); | ||
| 204 | OMAP24XX_SAVE(CM_IDLEST_DSP); | ||
| 205 | OMAP24XX_SAVE(CM_IDLEST_MDM); | ||
| 206 | |||
| 207 | /* Save clock registers */ | ||
| 208 | OMAP24XX_SAVE(CM_FCLKEN1_CORE); | ||
| 209 | OMAP24XX_SAVE(CM_FCLKEN2_CORE); | ||
| 210 | OMAP24XX_SAVE(CM_ICLKEN1_CORE); | ||
| 211 | OMAP24XX_SAVE(CM_ICLKEN2_CORE); | ||
| 212 | OMAP24XX_SAVE(CM_ICLKEN3_CORE); | ||
| 213 | OMAP24XX_SAVE(CM_ICLKEN4_CORE); | ||
| 214 | } | ||
| 215 | |||
| 216 | static inline void omap2_pm_restore_registers(void) | ||
| 217 | { | ||
| 218 | /* Restore clock state registers */ | ||
| 219 | OMAP24XX_RESTORE(CM_CLKSTCTRL_MPU); | ||
| 220 | OMAP24XX_RESTORE(CM_CLKSTCTRL_CORE); | ||
| 221 | OMAP24XX_RESTORE(CM_CLKSTCTRL_GFX); | ||
| 222 | OMAP24XX_RESTORE(CM_CLKSTCTRL_DSP); | ||
| 223 | OMAP24XX_RESTORE(CM_CLKSTCTRL_MDM); | ||
| 224 | |||
| 225 | /* Restore power state registers */ | ||
| 226 | OMAP24XX_RESTORE(PM_PWSTCTRL_MPU); | ||
| 227 | OMAP24XX_RESTORE(PM_PWSTCTRL_CORE); | ||
| 228 | OMAP24XX_RESTORE(PM_PWSTCTRL_GFX); | ||
| 229 | OMAP24XX_RESTORE(PM_PWSTCTRL_DSP); | ||
| 230 | OMAP24XX_RESTORE(PM_PWSTCTRL_MDM); | ||
| 231 | |||
| 232 | /* Restore idle state registers */ | ||
| 233 | OMAP24XX_RESTORE(CM_IDLEST1_CORE); | ||
| 234 | OMAP24XX_RESTORE(CM_IDLEST2_CORE); | ||
| 235 | OMAP24XX_RESTORE(CM_IDLEST3_CORE); | ||
| 236 | OMAP24XX_RESTORE(CM_IDLEST4_CORE); | ||
| 237 | OMAP24XX_RESTORE(CM_IDLEST_GFX); | ||
| 238 | OMAP24XX_RESTORE(CM_IDLEST_WKUP); | ||
| 239 | OMAP24XX_RESTORE(CM_IDLEST_CKGEN); | ||
| 240 | OMAP24XX_RESTORE(CM_IDLEST_DSP); | ||
| 241 | OMAP24XX_RESTORE(CM_IDLEST_MDM); | ||
| 242 | |||
| 243 | /* Restore autoidle registers */ | ||
| 244 | OMAP24XX_RESTORE(CM_AUTOIDLE1_CORE); | ||
| 245 | OMAP24XX_RESTORE(CM_AUTOIDLE2_CORE); | ||
| 246 | OMAP24XX_RESTORE(CM_AUTOIDLE3_CORE); | ||
| 247 | OMAP24XX_RESTORE(CM_AUTOIDLE4_CORE); | ||
| 248 | OMAP24XX_RESTORE(CM_AUTOIDLE_WKUP); | ||
| 249 | OMAP24XX_RESTORE(CM_AUTOIDLE_PLL); | ||
| 250 | OMAP24XX_RESTORE(CM_AUTOIDLE_DSP); | ||
| 251 | OMAP24XX_RESTORE(CM_AUTOIDLE_MDM); | ||
| 252 | |||
| 253 | /* Restore clock registers */ | ||
| 254 | OMAP24XX_RESTORE(CM_FCLKEN1_CORE); | ||
| 255 | OMAP24XX_RESTORE(CM_FCLKEN2_CORE); | ||
| 256 | OMAP24XX_RESTORE(CM_ICLKEN1_CORE); | ||
| 257 | OMAP24XX_RESTORE(CM_ICLKEN2_CORE); | ||
| 258 | OMAP24XX_RESTORE(CM_ICLKEN3_CORE); | ||
| 259 | OMAP24XX_RESTORE(CM_ICLKEN4_CORE); | ||
| 260 | |||
| 261 | /* REVISIT: Clear interrupts here */ | ||
| 262 | |||
| 263 | /* Restore interrupt registers */ | ||
| 264 | OMAP24XX_RESTORE(INTC_MIR0); | ||
| 265 | OMAP24XX_RESTORE(INTC_MIR1); | ||
| 266 | OMAP24XX_RESTORE(INTC_MIR2); | ||
| 267 | } | ||
| 268 | |||
| 269 | static int omap2_pm_suspend(void) | 80 | static int omap2_pm_suspend(void) |
| 270 | { | 81 | { |
| 271 | int processor_type = 0; | ||
| 272 | |||
| 273 | /* REVISIT: 0x21 or 0x26? */ | ||
| 274 | if (cpu_is_omap2420()) | ||
| 275 | processor_type = 0x21; | ||
| 276 | |||
| 277 | if (!processor_type) | ||
| 278 | return -ENOTSUPP; | ||
| 279 | |||
| 280 | local_irq_disable(); | ||
| 281 | local_fiq_disable(); | ||
| 282 | |||
| 283 | omap2_pm_save_registers(); | ||
| 284 | |||
| 285 | /* Disable interrupts except for the wake events */ | ||
| 286 | INTC_MIR_SET0 = 0xffffffff & ~INT0_WAKE_MASK; | ||
| 287 | INTC_MIR_SET1 = 0xffffffff & ~INT1_WAKE_MASK; | ||
| 288 | INTC_MIR_SET2 = 0xffffffff & ~INT2_WAKE_MASK; | ||
| 289 | |||
| 290 | pmdomain_set_autoidle(); | ||
| 291 | |||
| 292 | /* Clear old wake-up events */ | ||
| 293 | PM_WKST1_CORE = 0; | ||
| 294 | PM_WKST2_CORE = 0; | ||
| 295 | PM_WKST_WKUP = 0; | ||
| 296 | |||
| 297 | /* Enable wake-up events */ | ||
| 298 | PM_WKEN1_CORE = (1 << 22) | (1 << 21); /* UART1 & 2 */ | ||
| 299 | PM_WKEN2_CORE = (1 << 2); /* UART3 */ | ||
| 300 | PM_WKEN_WKUP = (1 << 2) | (1 << 0); /* GPIO & GPT1 */ | ||
| 301 | |||
| 302 | /* Disable clocks except for CM_ICLKEN2_CORE. It gets disabled | ||
| 303 | * in the SRAM suspend code */ | ||
| 304 | CM_FCLKEN1_CORE = 0; | ||
| 305 | CM_FCLKEN2_CORE = 0; | ||
| 306 | CM_ICLKEN1_CORE = 0; | ||
| 307 | CM_ICLKEN3_CORE = 0; | ||
| 308 | CM_ICLKEN4_CORE = 0; | ||
| 309 | |||
| 310 | omap2_pm_debug("Status before suspend"); | ||
| 311 | |||
| 312 | /* Must wait for serial buffers to clear */ | ||
| 313 | mdelay(200); | ||
| 314 | |||
| 315 | /* Jump to SRAM suspend code | ||
| 316 | * REVISIT: When is this SDRC_DLLB_CTRL? | ||
| 317 | */ | ||
| 318 | omap2_sram_suspend(SDRC_DLLA_CTRL, processor_type); | ||
| 319 | |||
| 320 | /* Back from sleep */ | ||
| 321 | omap2_pm_restore_registers(); | ||
| 322 | |||
| 323 | local_fiq_enable(); | ||
| 324 | local_irq_enable(); | ||
| 325 | |||
| 326 | return 0; | 82 | return 0; |
| 327 | } | 83 | } |
| 328 | 84 | ||
| @@ -357,30 +113,6 @@ static struct platform_suspend_ops omap_pm_ops = { | |||
| 357 | 113 | ||
| 358 | int __init omap2_pm_init(void) | 114 | int __init omap2_pm_init(void) |
| 359 | { | 115 | { |
| 360 | printk("Power Management for TI OMAP.\n"); | ||
| 361 | |||
| 362 | vclk = clk_get(NULL, "virt_prcm_set"); | ||
| 363 | if (IS_ERR(vclk)) { | ||
| 364 | printk(KERN_ERR "Could not get PM vclk\n"); | ||
| 365 | return -ENODEV; | ||
| 366 | } | ||
| 367 | |||
| 368 | /* | ||
| 369 | * We copy the assembler sleep/wakeup routines to SRAM. | ||
| 370 | * These routines need to be in SRAM as that's the only | ||
| 371 | * memory the MPU can see when it wakes up. | ||
| 372 | */ | ||
| 373 | omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend, | ||
| 374 | omap24xx_idle_loop_suspend_sz); | ||
| 375 | |||
| 376 | omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend, | ||
| 377 | omap24xx_cpu_suspend_sz); | ||
| 378 | |||
| 379 | suspend_set_ops(&omap_pm_ops); | ||
| 380 | pm_idle = omap2_pm_idle; | ||
| 381 | |||
| 382 | pmdomain_init(); | ||
| 383 | |||
| 384 | return 0; | 116 | return 0; |
| 385 | } | 117 | } |
| 386 | 118 | ||
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h new file mode 100644 index 000000000000..cacb34086e35 --- /dev/null +++ b/arch/arm/mach-omap2/prcm-common.h | |||
| @@ -0,0 +1,317 @@ | |||
| 1 | #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H | ||
| 2 | #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * OMAP2/3 PRCM base and module definitions | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | ||
| 8 | * Copyright (C) 2007-2008 Nokia Corporation | ||
| 9 | * | ||
| 10 | * Written by Paul Walmsley | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | |||
| 18 | /* Module offsets from both CM_BASE & PRM_BASE */ | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Offsets that are the same on 24xx and 34xx | ||
| 22 | * | ||
| 23 | * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is | ||
| 24 | * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2. | ||
| 25 | */ | ||
| 26 | #define OCP_MOD 0x000 | ||
| 27 | #define MPU_MOD 0x100 | ||
| 28 | #define CORE_MOD 0x200 | ||
| 29 | #define GFX_MOD 0x300 | ||
| 30 | #define WKUP_MOD 0x400 | ||
| 31 | #define PLL_MOD 0x500 | ||
| 32 | |||
| 33 | |||
| 34 | /* Chip-specific module offsets */ | ||
| 35 | #define OMAP24XX_DSP_MOD 0x800 | ||
| 36 | |||
| 37 | #define OMAP2430_MDM_MOD 0xc00 | ||
| 38 | |||
| 39 | /* IVA2 module is < base on 3430 */ | ||
| 40 | #define OMAP3430_IVA2_MOD -0x800 | ||
| 41 | #define OMAP3430ES2_SGX_MOD GFX_MOD | ||
| 42 | #define OMAP3430_CCR_MOD PLL_MOD | ||
| 43 | #define OMAP3430_DSS_MOD 0x600 | ||
| 44 | #define OMAP3430_CAM_MOD 0x700 | ||
| 45 | #define OMAP3430_PER_MOD 0x800 | ||
| 46 | #define OMAP3430_EMU_MOD 0x900 | ||
| 47 | #define OMAP3430_GR_MOD 0xa00 | ||
| 48 | #define OMAP3430_NEON_MOD 0xb00 | ||
| 49 | #define OMAP3430ES2_USBHOST_MOD 0xc00 | ||
| 50 | |||
| 51 | |||
| 52 | /* 24XX register bits shared between CM & PRM registers */ | ||
| 53 | |||
| 54 | /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | ||
| 55 | #define OMAP2420_EN_MMC_SHIFT 26 | ||
| 56 | #define OMAP2420_EN_MMC (1 << 26) | ||
| 57 | #define OMAP24XX_EN_UART2_SHIFT 22 | ||
| 58 | #define OMAP24XX_EN_UART2 (1 << 22) | ||
| 59 | #define OMAP24XX_EN_UART1_SHIFT 21 | ||
| 60 | #define OMAP24XX_EN_UART1 (1 << 21) | ||
| 61 | #define OMAP24XX_EN_MCSPI2_SHIFT 18 | ||
| 62 | #define OMAP24XX_EN_MCSPI2 (1 << 18) | ||
| 63 | #define OMAP24XX_EN_MCSPI1_SHIFT 17 | ||
| 64 | #define OMAP24XX_EN_MCSPI1 (1 << 17) | ||
| 65 | #define OMAP24XX_EN_MCBSP2_SHIFT 16 | ||
| 66 | #define OMAP24XX_EN_MCBSP2 (1 << 16) | ||
| 67 | #define OMAP24XX_EN_MCBSP1_SHIFT 15 | ||
| 68 | #define OMAP24XX_EN_MCBSP1 (1 << 15) | ||
| 69 | #define OMAP24XX_EN_GPT12_SHIFT 14 | ||
| 70 | #define OMAP24XX_EN_GPT12 (1 << 14) | ||
| 71 | #define OMAP24XX_EN_GPT11_SHIFT 13 | ||
| 72 | #define OMAP24XX_EN_GPT11 (1 << 13) | ||
| 73 | #define OMAP24XX_EN_GPT10_SHIFT 12 | ||
| 74 | #define OMAP24XX_EN_GPT10 (1 << 12) | ||
| 75 | #define OMAP24XX_EN_GPT9_SHIFT 11 | ||
| 76 | #define OMAP24XX_EN_GPT9 (1 << 11) | ||
| 77 | #define OMAP24XX_EN_GPT8_SHIFT 10 | ||
| 78 | #define OMAP24XX_EN_GPT8 (1 << 10) | ||
| 79 | #define OMAP24XX_EN_GPT7_SHIFT 9 | ||
| 80 | #define OMAP24XX_EN_GPT7 (1 << 9) | ||
| 81 | #define OMAP24XX_EN_GPT6_SHIFT 8 | ||
| 82 | #define OMAP24XX_EN_GPT6 (1 << 8) | ||
| 83 | #define OMAP24XX_EN_GPT5_SHIFT 7 | ||
| 84 | #define OMAP24XX_EN_GPT5 (1 << 7) | ||
| 85 | #define OMAP24XX_EN_GPT4_SHIFT 6 | ||
| 86 | #define OMAP24XX_EN_GPT4 (1 << 6) | ||
| 87 | #define OMAP24XX_EN_GPT3_SHIFT 5 | ||
| 88 | #define OMAP24XX_EN_GPT3 (1 << 5) | ||
| 89 | #define OMAP24XX_EN_GPT2_SHIFT 4 | ||
| 90 | #define OMAP24XX_EN_GPT2 (1 << 4) | ||
| 91 | #define OMAP2420_EN_VLYNQ_SHIFT 3 | ||
| 92 | #define OMAP2420_EN_VLYNQ (1 << 3) | ||
| 93 | |||
| 94 | /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ | ||
| 95 | #define OMAP2430_EN_GPIO5_SHIFT 10 | ||
| 96 | #define OMAP2430_EN_GPIO5 (1 << 10) | ||
| 97 | #define OMAP2430_EN_MCSPI3_SHIFT 9 | ||
| 98 | #define OMAP2430_EN_MCSPI3 (1 << 9) | ||
| 99 | #define OMAP2430_EN_MMCHS2_SHIFT 8 | ||
| 100 | #define OMAP2430_EN_MMCHS2 (1 << 8) | ||
| 101 | #define OMAP2430_EN_MMCHS1_SHIFT 7 | ||
| 102 | #define OMAP2430_EN_MMCHS1 (1 << 7) | ||
| 103 | #define OMAP24XX_EN_UART3_SHIFT 2 | ||
| 104 | #define OMAP24XX_EN_UART3 (1 << 2) | ||
| 105 | #define OMAP24XX_EN_USB_SHIFT 0 | ||
| 106 | #define OMAP24XX_EN_USB (1 << 0) | ||
| 107 | |||
| 108 | /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ | ||
| 109 | #define OMAP2430_EN_MDM_INTC_SHIFT 11 | ||
| 110 | #define OMAP2430_EN_MDM_INTC (1 << 11) | ||
| 111 | #define OMAP2430_EN_USBHS_SHIFT 6 | ||
| 112 | #define OMAP2430_EN_USBHS (1 << 6) | ||
| 113 | |||
| 114 | /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ | ||
| 115 | #define OMAP2420_ST_MMC (1 << 26) | ||
| 116 | #define OMAP24XX_ST_UART2 (1 << 22) | ||
| 117 | #define OMAP24XX_ST_UART1 (1 << 21) | ||
| 118 | #define OMAP24XX_ST_MCSPI2 (1 << 18) | ||
| 119 | #define OMAP24XX_ST_MCSPI1 (1 << 17) | ||
| 120 | #define OMAP24XX_ST_GPT12 (1 << 14) | ||
| 121 | #define OMAP24XX_ST_GPT11 (1 << 13) | ||
| 122 | #define OMAP24XX_ST_GPT10 (1 << 12) | ||
| 123 | #define OMAP24XX_ST_GPT9 (1 << 11) | ||
| 124 | #define OMAP24XX_ST_GPT8 (1 << 10) | ||
| 125 | #define OMAP24XX_ST_GPT7 (1 << 9) | ||
| 126 | #define OMAP24XX_ST_GPT6 (1 << 8) | ||
| 127 | #define OMAP24XX_ST_GPT5 (1 << 7) | ||
| 128 | #define OMAP24XX_ST_GPT4 (1 << 6) | ||
| 129 | #define OMAP24XX_ST_GPT3 (1 << 5) | ||
| 130 | #define OMAP24XX_ST_GPT2 (1 << 4) | ||
| 131 | #define OMAP2420_ST_VLYNQ (1 << 3) | ||
| 132 | |||
| 133 | /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ | ||
| 134 | #define OMAP2430_ST_MDM_INTC (1 << 11) | ||
| 135 | #define OMAP2430_ST_GPIO5 (1 << 10) | ||
| 136 | #define OMAP2430_ST_MCSPI3 (1 << 9) | ||
| 137 | #define OMAP2430_ST_MMCHS2 (1 << 8) | ||
| 138 | #define OMAP2430_ST_MMCHS1 (1 << 7) | ||
| 139 | #define OMAP2430_ST_USBHS (1 << 6) | ||
| 140 | #define OMAP24XX_ST_UART3 (1 << 2) | ||
| 141 | #define OMAP24XX_ST_USB (1 << 0) | ||
| 142 | |||
| 143 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | ||
| 144 | #define OMAP24XX_EN_GPIOS_SHIFT 2 | ||
| 145 | #define OMAP24XX_EN_GPIOS (1 << 2) | ||
| 146 | #define OMAP24XX_EN_GPT1_SHIFT 0 | ||
| 147 | #define OMAP24XX_EN_GPT1 (1 << 0) | ||
| 148 | |||
| 149 | /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ | ||
| 150 | #define OMAP24XX_ST_GPIOS (1 << 2) | ||
| 151 | #define OMAP24XX_ST_GPT1 (1 << 0) | ||
| 152 | |||
| 153 | /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ | ||
| 154 | #define OMAP2430_ST_MDM (1 << 0) | ||
| 155 | |||
| 156 | |||
| 157 | /* 3430 register bits shared between CM & PRM registers */ | ||
| 158 | |||
| 159 | /* CM_REVISION, PRM_REVISION shared bits */ | ||
| 160 | #define OMAP3430_REV_SHIFT 0 | ||
| 161 | #define OMAP3430_REV_MASK (0xff << 0) | ||
| 162 | |||
| 163 | /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */ | ||
| 164 | #define OMAP3430_AUTOIDLE (1 << 0) | ||
| 165 | |||
| 166 | /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | ||
| 167 | #define OMAP3430_EN_MMC2 (1 << 25) | ||
| 168 | #define OMAP3430_EN_MMC2_SHIFT 25 | ||
| 169 | #define OMAP3430_EN_MMC1 (1 << 24) | ||
| 170 | #define OMAP3430_EN_MMC1_SHIFT 24 | ||
| 171 | #define OMAP3430_EN_MCSPI4 (1 << 21) | ||
| 172 | #define OMAP3430_EN_MCSPI4_SHIFT 21 | ||
| 173 | #define OMAP3430_EN_MCSPI3 (1 << 20) | ||
| 174 | #define OMAP3430_EN_MCSPI3_SHIFT 20 | ||
| 175 | #define OMAP3430_EN_MCSPI2 (1 << 19) | ||
| 176 | #define OMAP3430_EN_MCSPI2_SHIFT 19 | ||
| 177 | #define OMAP3430_EN_MCSPI1 (1 << 18) | ||
| 178 | #define OMAP3430_EN_MCSPI1_SHIFT 18 | ||
| 179 | #define OMAP3430_EN_I2C3 (1 << 17) | ||
| 180 | #define OMAP3430_EN_I2C3_SHIFT 17 | ||
| 181 | #define OMAP3430_EN_I2C2 (1 << 16) | ||
| 182 | #define OMAP3430_EN_I2C2_SHIFT 16 | ||
| 183 | #define OMAP3430_EN_I2C1 (1 << 15) | ||
| 184 | #define OMAP3430_EN_I2C1_SHIFT 15 | ||
| 185 | #define OMAP3430_EN_UART2 (1 << 14) | ||
| 186 | #define OMAP3430_EN_UART2_SHIFT 14 | ||
| 187 | #define OMAP3430_EN_UART1 (1 << 13) | ||
| 188 | #define OMAP3430_EN_UART1_SHIFT 13 | ||
| 189 | #define OMAP3430_EN_GPT11 (1 << 12) | ||
| 190 | #define OMAP3430_EN_GPT11_SHIFT 12 | ||
| 191 | #define OMAP3430_EN_GPT10 (1 << 11) | ||
| 192 | #define OMAP3430_EN_GPT10_SHIFT 11 | ||
| 193 | #define OMAP3430_EN_MCBSP5 (1 << 10) | ||
| 194 | #define OMAP3430_EN_MCBSP5_SHIFT 10 | ||
| 195 | #define OMAP3430_EN_MCBSP1 (1 << 9) | ||
| 196 | #define OMAP3430_EN_MCBSP1_SHIFT 9 | ||
| 197 | #define OMAP3430_EN_FSHOSTUSB (1 << 5) | ||
| 198 | #define OMAP3430_EN_FSHOSTUSB_SHIFT 5 | ||
| 199 | #define OMAP3430_EN_D2D (1 << 3) | ||
| 200 | #define OMAP3430_EN_D2D_SHIFT 3 | ||
| 201 | |||
| 202 | /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | ||
| 203 | #define OMAP3430_EN_HSOTGUSB (1 << 4) | ||
| 204 | #define OMAP3430_EN_HSOTGUSB_SHIFT 4 | ||
| 205 | |||
| 206 | /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ | ||
| 207 | #define OMAP3430_ST_MMC2 (1 << 25) | ||
| 208 | #define OMAP3430_ST_MMC1 (1 << 24) | ||
| 209 | #define OMAP3430_ST_MCSPI4 (1 << 21) | ||
| 210 | #define OMAP3430_ST_MCSPI3 (1 << 20) | ||
| 211 | #define OMAP3430_ST_MCSPI2 (1 << 19) | ||
| 212 | #define OMAP3430_ST_MCSPI1 (1 << 18) | ||
| 213 | #define OMAP3430_ST_I2C3 (1 << 17) | ||
| 214 | #define OMAP3430_ST_I2C2 (1 << 16) | ||
| 215 | #define OMAP3430_ST_I2C1 (1 << 15) | ||
| 216 | #define OMAP3430_ST_UART2 (1 << 14) | ||
| 217 | #define OMAP3430_ST_UART1 (1 << 13) | ||
| 218 | #define OMAP3430_ST_GPT11 (1 << 12) | ||
| 219 | #define OMAP3430_ST_GPT10 (1 << 11) | ||
| 220 | #define OMAP3430_ST_MCBSP5 (1 << 10) | ||
| 221 | #define OMAP3430_ST_MCBSP1 (1 << 9) | ||
| 222 | #define OMAP3430_ST_FSHOSTUSB (1 << 5) | ||
| 223 | #define OMAP3430_ST_HSOTGUSB (1 << 4) | ||
| 224 | #define OMAP3430_ST_D2D (1 << 3) | ||
| 225 | |||
| 226 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | ||
| 227 | #define OMAP3430_EN_GPIO1 (1 << 3) | ||
| 228 | #define OMAP3430_EN_GPIO1_SHIFT 3 | ||
| 229 | #define OMAP3430_EN_GPT1 (1 << 0) | ||
| 230 | #define OMAP3430_EN_GPT1_SHIFT 0 | ||
| 231 | |||
| 232 | /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */ | ||
| 233 | #define OMAP3430_EN_SR2 (1 << 7) | ||
| 234 | #define OMAP3430_EN_SR2_SHIFT 7 | ||
| 235 | #define OMAP3430_EN_SR1 (1 << 6) | ||
| 236 | #define OMAP3430_EN_SR1_SHIFT 6 | ||
| 237 | |||
| 238 | /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | ||
| 239 | #define OMAP3430_EN_GPT12 (1 << 1) | ||
| 240 | #define OMAP3430_EN_GPT12_SHIFT 1 | ||
| 241 | |||
| 242 | /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ | ||
| 243 | #define OMAP3430_ST_SR2 (1 << 7) | ||
| 244 | #define OMAP3430_ST_SR1 (1 << 6) | ||
| 245 | #define OMAP3430_ST_GPIO1 (1 << 3) | ||
| 246 | #define OMAP3430_ST_GPT12 (1 << 1) | ||
| 247 | #define OMAP3430_ST_GPT1 (1 << 0) | ||
| 248 | |||
| 249 | /* | ||
| 250 | * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, | ||
| 251 | * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX, | ||
| 252 | * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits | ||
| 253 | */ | ||
| 254 | #define OMAP3430_EN_MPU (1 << 1) | ||
| 255 | #define OMAP3430_EN_MPU_SHIFT 1 | ||
| 256 | |||
| 257 | /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ | ||
| 258 | #define OMAP3430_EN_GPIO6 (1 << 17) | ||
| 259 | #define OMAP3430_EN_GPIO6_SHIFT 17 | ||
| 260 | #define OMAP3430_EN_GPIO5 (1 << 16) | ||
| 261 | #define OMAP3430_EN_GPIO5_SHIFT 16 | ||
| 262 | #define OMAP3430_EN_GPIO4 (1 << 15) | ||
| 263 | #define OMAP3430_EN_GPIO4_SHIFT 15 | ||
| 264 | #define OMAP3430_EN_GPIO3 (1 << 14) | ||
| 265 | #define OMAP3430_EN_GPIO3_SHIFT 14 | ||
| 266 | #define OMAP3430_EN_GPIO2 (1 << 13) | ||
| 267 | #define OMAP3430_EN_GPIO2_SHIFT 13 | ||
| 268 | #define OMAP3430_EN_UART3 (1 << 11) | ||
| 269 | #define OMAP3430_EN_UART3_SHIFT 11 | ||
| 270 | #define OMAP3430_EN_GPT9 (1 << 10) | ||
| 271 | #define OMAP3430_EN_GPT9_SHIFT 10 | ||
| 272 | #define OMAP3430_EN_GPT8 (1 << 9) | ||
| 273 | #define OMAP3430_EN_GPT8_SHIFT 9 | ||
| 274 | #define OMAP3430_EN_GPT7 (1 << 8) | ||
| 275 | #define OMAP3430_EN_GPT7_SHIFT 8 | ||
| 276 | #define OMAP3430_EN_GPT6 (1 << 7) | ||
| 277 | #define OMAP3430_EN_GPT6_SHIFT 7 | ||
| 278 | #define OMAP3430_EN_GPT5 (1 << 6) | ||
| 279 | #define OMAP3430_EN_GPT5_SHIFT 6 | ||
| 280 | #define OMAP3430_EN_GPT4 (1 << 5) | ||
| 281 | #define OMAP3430_EN_GPT4_SHIFT 5 | ||
| 282 | #define OMAP3430_EN_GPT3 (1 << 4) | ||
| 283 | #define OMAP3430_EN_GPT3_SHIFT 4 | ||
| 284 | #define OMAP3430_EN_GPT2 (1 << 3) | ||
| 285 | #define OMAP3430_EN_GPT2_SHIFT 3 | ||
| 286 | |||
| 287 | /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */ | ||
| 288 | /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits | ||
| 289 | * be ST_* bits instead? */ | ||
| 290 | #define OMAP3430_EN_MCBSP4 (1 << 2) | ||
| 291 | #define OMAP3430_EN_MCBSP4_SHIFT 2 | ||
| 292 | #define OMAP3430_EN_MCBSP3 (1 << 1) | ||
| 293 | #define OMAP3430_EN_MCBSP3_SHIFT 1 | ||
| 294 | #define OMAP3430_EN_MCBSP2 (1 << 0) | ||
| 295 | #define OMAP3430_EN_MCBSP2_SHIFT 0 | ||
| 296 | |||
| 297 | /* CM_IDLEST_PER, PM_WKST_PER shared bits */ | ||
| 298 | #define OMAP3430_ST_GPIO6 (1 << 17) | ||
| 299 | #define OMAP3430_ST_GPIO5 (1 << 16) | ||
| 300 | #define OMAP3430_ST_GPIO4 (1 << 15) | ||
| 301 | #define OMAP3430_ST_GPIO3 (1 << 14) | ||
| 302 | #define OMAP3430_ST_GPIO2 (1 << 13) | ||
| 303 | #define OMAP3430_ST_UART3 (1 << 11) | ||
| 304 | #define OMAP3430_ST_GPT9 (1 << 10) | ||
| 305 | #define OMAP3430_ST_GPT8 (1 << 9) | ||
| 306 | #define OMAP3430_ST_GPT7 (1 << 8) | ||
| 307 | #define OMAP3430_ST_GPT6 (1 << 7) | ||
| 308 | #define OMAP3430_ST_GPT5 (1 << 6) | ||
| 309 | #define OMAP3430_ST_GPT4 (1 << 5) | ||
| 310 | #define OMAP3430_ST_GPT3 (1 << 4) | ||
| 311 | #define OMAP3430_ST_GPT2 (1 << 3) | ||
| 312 | |||
| 313 | /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ | ||
| 314 | #define OMAP3430_EN_CORE (1 << 0) | ||
| 315 | |||
| 316 | #endif | ||
| 317 | |||
diff --git a/arch/arm/mach-omap2/prcm-regs.h b/arch/arm/mach-omap2/prcm-regs.h deleted file mode 100644 index 5e1c4b53ee9d..000000000000 --- a/arch/arm/mach-omap2/prcm-regs.h +++ /dev/null | |||
| @@ -1,483 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/prcm-regs.h | ||
| 3 | * | ||
| 4 | * OMAP24XX Power Reset and Clock Management (PRCM) registers | ||
| 5 | * | ||
| 6 | * Copyright (C) 2005 Texas Instruments, Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_H | ||
| 24 | #define __ARCH_ARM_MACH_OMAP2_PRCM_H | ||
| 25 | |||
| 26 | /* SET_PERFORMANCE_LEVEL PARAMETERS */ | ||
| 27 | #define PRCM_HALF_SPEED 1 | ||
| 28 | #define PRCM_FULL_SPEED 2 | ||
| 29 | |||
| 30 | #ifndef __ASSEMBLER__ | ||
| 31 | |||
| 32 | #define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset)) | ||
| 33 | |||
| 34 | #define PRCM_REVISION PRCM_REG32(0x000) | ||
| 35 | #define PRCM_SYSCONFIG PRCM_REG32(0x010) | ||
| 36 | #define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018) | ||
| 37 | #define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C) | ||
| 38 | #define PRCM_VOLTCTRL PRCM_REG32(0x050) | ||
| 39 | #define PRCM_VOLTST PRCM_REG32(0x054) | ||
| 40 | #define PRCM_CLKSRC_CTRL PRCM_REG32(0x060) | ||
| 41 | #define PRCM_CLKOUT_CTRL PRCM_REG32(0x070) | ||
| 42 | #define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078) | ||
| 43 | #define PRCM_CLKCFG_CTRL PRCM_REG32(0x080) | ||
| 44 | #define PRCM_CLKCFG_STATUS PRCM_REG32(0x084) | ||
| 45 | #define PRCM_VOLTSETUP PRCM_REG32(0x090) | ||
| 46 | #define PRCM_CLKSSETUP PRCM_REG32(0x094) | ||
| 47 | #define PRCM_POLCTRL PRCM_REG32(0x098) | ||
| 48 | |||
| 49 | /* GENERAL PURPOSE */ | ||
| 50 | #define GENERAL_PURPOSE1 PRCM_REG32(0x0B0) | ||
| 51 | #define GENERAL_PURPOSE2 PRCM_REG32(0x0B4) | ||
| 52 | #define GENERAL_PURPOSE3 PRCM_REG32(0x0B8) | ||
| 53 | #define GENERAL_PURPOSE4 PRCM_REG32(0x0BC) | ||
| 54 | #define GENERAL_PURPOSE5 PRCM_REG32(0x0C0) | ||
| 55 | #define GENERAL_PURPOSE6 PRCM_REG32(0x0C4) | ||
| 56 | #define GENERAL_PURPOSE7 PRCM_REG32(0x0C8) | ||
| 57 | #define GENERAL_PURPOSE8 PRCM_REG32(0x0CC) | ||
| 58 | #define GENERAL_PURPOSE9 PRCM_REG32(0x0D0) | ||
| 59 | #define GENERAL_PURPOSE10 PRCM_REG32(0x0D4) | ||
| 60 | #define GENERAL_PURPOSE11 PRCM_REG32(0x0D8) | ||
| 61 | #define GENERAL_PURPOSE12 PRCM_REG32(0x0DC) | ||
| 62 | #define GENERAL_PURPOSE13 PRCM_REG32(0x0E0) | ||
| 63 | #define GENERAL_PURPOSE14 PRCM_REG32(0x0E4) | ||
| 64 | #define GENERAL_PURPOSE15 PRCM_REG32(0x0E8) | ||
| 65 | #define GENERAL_PURPOSE16 PRCM_REG32(0x0EC) | ||
| 66 | #define GENERAL_PURPOSE17 PRCM_REG32(0x0F0) | ||
| 67 | #define GENERAL_PURPOSE18 PRCM_REG32(0x0F4) | ||
| 68 | #define GENERAL_PURPOSE19 PRCM_REG32(0x0F8) | ||
| 69 | #define GENERAL_PURPOSE20 PRCM_REG32(0x0FC) | ||
| 70 | |||
| 71 | /* MPU */ | ||
| 72 | #define CM_CLKSEL_MPU PRCM_REG32(0x140) | ||
| 73 | #define CM_CLKSTCTRL_MPU PRCM_REG32(0x148) | ||
| 74 | #define RM_RSTST_MPU PRCM_REG32(0x158) | ||
| 75 | #define PM_WKDEP_MPU PRCM_REG32(0x1C8) | ||
| 76 | #define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4) | ||
| 77 | #define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8) | ||
| 78 | #define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC) | ||
| 79 | #define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0) | ||
| 80 | #define PM_PWSTST_MPU PRCM_REG32(0x1E4) | ||
| 81 | |||
| 82 | /* CORE */ | ||
| 83 | #define CM_FCLKEN1_CORE PRCM_REG32(0x200) | ||
| 84 | #define CM_FCLKEN2_CORE PRCM_REG32(0x204) | ||
| 85 | #define CM_FCLKEN3_CORE PRCM_REG32(0x208) | ||
| 86 | #define CM_ICLKEN1_CORE PRCM_REG32(0x210) | ||
| 87 | #define CM_ICLKEN2_CORE PRCM_REG32(0x214) | ||
| 88 | #define CM_ICLKEN3_CORE PRCM_REG32(0x218) | ||
| 89 | #define CM_ICLKEN4_CORE PRCM_REG32(0x21C) | ||
| 90 | #define CM_IDLEST1_CORE PRCM_REG32(0x220) | ||
| 91 | #define CM_IDLEST2_CORE PRCM_REG32(0x224) | ||
| 92 | #define CM_IDLEST3_CORE PRCM_REG32(0x228) | ||
| 93 | #define CM_IDLEST4_CORE PRCM_REG32(0x22C) | ||
| 94 | #define CM_AUTOIDLE1_CORE PRCM_REG32(0x230) | ||
| 95 | #define CM_AUTOIDLE2_CORE PRCM_REG32(0x234) | ||
| 96 | #define CM_AUTOIDLE3_CORE PRCM_REG32(0x238) | ||
| 97 | #define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C) | ||
| 98 | #define CM_CLKSEL1_CORE PRCM_REG32(0x240) | ||
| 99 | #define CM_CLKSEL2_CORE PRCM_REG32(0x244) | ||
| 100 | #define CM_CLKSTCTRL_CORE PRCM_REG32(0x248) | ||
| 101 | #define PM_WKEN1_CORE PRCM_REG32(0x2A0) | ||
| 102 | #define PM_WKEN2_CORE PRCM_REG32(0x2A4) | ||
| 103 | #define PM_WKST1_CORE PRCM_REG32(0x2B0) | ||
| 104 | #define PM_WKST2_CORE PRCM_REG32(0x2B4) | ||
| 105 | #define PM_WKDEP_CORE PRCM_REG32(0x2C8) | ||
| 106 | #define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0) | ||
| 107 | #define PM_PWSTST_CORE PRCM_REG32(0x2E4) | ||
| 108 | |||
| 109 | /* GFX */ | ||
| 110 | #define CM_FCLKEN_GFX PRCM_REG32(0x300) | ||
| 111 | #define CM_ICLKEN_GFX PRCM_REG32(0x310) | ||
| 112 | #define CM_IDLEST_GFX PRCM_REG32(0x320) | ||
| 113 | #define CM_CLKSEL_GFX PRCM_REG32(0x340) | ||
| 114 | #define CM_CLKSTCTRL_GFX PRCM_REG32(0x348) | ||
| 115 | #define RM_RSTCTRL_GFX PRCM_REG32(0x350) | ||
| 116 | #define RM_RSTST_GFX PRCM_REG32(0x358) | ||
| 117 | #define PM_WKDEP_GFX PRCM_REG32(0x3C8) | ||
| 118 | #define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0) | ||
| 119 | #define PM_PWSTST_GFX PRCM_REG32(0x3E4) | ||
| 120 | |||
| 121 | /* WAKE-UP */ | ||
| 122 | #define CM_FCLKEN_WKUP PRCM_REG32(0x400) | ||
| 123 | #define CM_ICLKEN_WKUP PRCM_REG32(0x410) | ||
| 124 | #define CM_IDLEST_WKUP PRCM_REG32(0x420) | ||
| 125 | #define CM_AUTOIDLE_WKUP PRCM_REG32(0x430) | ||
| 126 | #define CM_CLKSEL_WKUP PRCM_REG32(0x440) | ||
| 127 | #define RM_RSTCTRL_WKUP PRCM_REG32(0x450) | ||
| 128 | #define RM_RSTTIME_WKUP PRCM_REG32(0x454) | ||
| 129 | #define RM_RSTST_WKUP PRCM_REG32(0x458) | ||
| 130 | #define PM_WKEN_WKUP PRCM_REG32(0x4A0) | ||
| 131 | #define PM_WKST_WKUP PRCM_REG32(0x4B0) | ||
| 132 | |||
| 133 | /* CLOCKS */ | ||
| 134 | #define CM_CLKEN_PLL PRCM_REG32(0x500) | ||
| 135 | #define CM_IDLEST_CKGEN PRCM_REG32(0x520) | ||
| 136 | #define CM_AUTOIDLE_PLL PRCM_REG32(0x530) | ||
| 137 | #define CM_CLKSEL1_PLL PRCM_REG32(0x540) | ||
| 138 | #define CM_CLKSEL2_PLL PRCM_REG32(0x544) | ||
| 139 | |||
| 140 | /* DSP */ | ||
| 141 | #define CM_FCLKEN_DSP PRCM_REG32(0x800) | ||
| 142 | #define CM_ICLKEN_DSP PRCM_REG32(0x810) | ||
| 143 | #define CM_IDLEST_DSP PRCM_REG32(0x820) | ||
| 144 | #define CM_AUTOIDLE_DSP PRCM_REG32(0x830) | ||
| 145 | #define CM_CLKSEL_DSP PRCM_REG32(0x840) | ||
| 146 | #define CM_CLKSTCTRL_DSP PRCM_REG32(0x848) | ||
| 147 | #define RM_RSTCTRL_DSP PRCM_REG32(0x850) | ||
| 148 | #define RM_RSTST_DSP PRCM_REG32(0x858) | ||
| 149 | #define PM_WKEN_DSP PRCM_REG32(0x8A0) | ||
| 150 | #define PM_WKDEP_DSP PRCM_REG32(0x8C8) | ||
| 151 | #define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0) | ||
| 152 | #define PM_PWSTST_DSP PRCM_REG32(0x8E4) | ||
| 153 | #define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0) | ||
| 154 | #define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4) | ||
| 155 | |||
| 156 | /* IVA */ | ||
| 157 | #define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8) | ||
| 158 | #define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC) | ||
| 159 | |||
| 160 | /* Modem on 2430 */ | ||
| 161 | #define CM_FCLKEN_MDM PRCM_REG32(0xC00) | ||
| 162 | #define CM_ICLKEN_MDM PRCM_REG32(0xC10) | ||
| 163 | #define CM_IDLEST_MDM PRCM_REG32(0xC20) | ||
| 164 | #define CM_AUTOIDLE_MDM PRCM_REG32(0xC30) | ||
| 165 | #define CM_CLKSEL_MDM PRCM_REG32(0xC40) | ||
| 166 | #define CM_CLKSTCTRL_MDM PRCM_REG32(0xC48) | ||
| 167 | #define RM_RSTCTRL_MDM PRCM_REG32(0xC50) | ||
| 168 | #define RM_RSTST_MDM PRCM_REG32(0xC58) | ||
| 169 | #define PM_WKEN_MDM PRCM_REG32(0xCA0) | ||
| 170 | #define PM_WKST_MDM PRCM_REG32(0xCB0) | ||
| 171 | #define PM_WKDEP_MDM PRCM_REG32(0xCC8) | ||
| 172 | #define PM_PWSTCTRL_MDM PRCM_REG32(0xCE0) | ||
| 173 | #define PM_PWSTST_MDM PRCM_REG32(0xCE4) | ||
| 174 | |||
| 175 | #define OMAP24XX_L4_IO_BASE 0x48000000 | ||
| 176 | |||
| 177 | #define DISP_BASE (OMAP24XX_L4_IO_BASE + 0x50000) | ||
| 178 | #define DISP_REG32(offset) __REG32(DISP_BASE + (offset)) | ||
| 179 | |||
| 180 | #define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000) | ||
| 181 | #define GPMC_REG32(offset) __REG32(OMAP24XX_GPMC_BASE + (offset)) | ||
| 182 | |||
| 183 | /* FIXME: Move these to timer code */ | ||
| 184 | #define GPT1_BASE (0x48028000) | ||
| 185 | #define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset)) | ||
| 186 | |||
| 187 | /* Misc sysconfig */ | ||
| 188 | #define DISPC_SYSCONFIG DISP_REG32(0x410) | ||
| 189 | #define SPI_BASE (OMAP24XX_L4_IO_BASE + 0x98000) | ||
| 190 | #define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10) | ||
| 191 | #define MCSPI2_SYSCONFIG __REG32(SPI_BASE + 0x2000 + 0x10) | ||
| 192 | #define MCSPI3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0xb8010) | ||
| 193 | |||
| 194 | #define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE + 0x2C10) | ||
| 195 | #define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE + 0x282C) | ||
| 196 | #define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE + 0x602C) | ||
| 197 | #define GPMC_SYSCONFIG GPMC_REG32(0x010) | ||
| 198 | #define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x94010) | ||
| 199 | #define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6A054) | ||
| 200 | #define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6C054) | ||
| 201 | #define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6E054) | ||
| 202 | #define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE + 0x10) | ||
| 203 | #define OMAP24XX_SMS_BASE (L3_24XX_BASE + 0x8000) | ||
| 204 | #define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE + 0x10) | ||
| 205 | #define SSI_SYSCONFIG __REG32(DISP_BASE + 0x8010) | ||
| 206 | |||
| 207 | /* rkw - good cannidates for PM_ to start what nm was trying */ | ||
| 208 | #define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE + 0x2A000) | ||
| 209 | #define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE + 0x78000) | ||
| 210 | #define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE + 0x7A000) | ||
| 211 | #define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE + 0x7C000) | ||
| 212 | #define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE + 0x7E000) | ||
| 213 | #define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE + 0x80000) | ||
| 214 | #define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE + 0x82000) | ||
| 215 | #define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE + 0x84000) | ||
| 216 | #define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE + 0x86000) | ||
| 217 | #define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE + 0x88000) | ||
| 218 | #define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE + 0x8A000) | ||
| 219 | |||
| 220 | /* FIXME: Move these to timer code */ | ||
| 221 | #define GPTIMER1_SYSCONFIG GPT1_REG32(0x010) | ||
| 222 | #define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10) | ||
| 223 | #define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10) | ||
| 224 | #define GPTIMER4_SYSCONFIG __REG32(OMAP24XX_GPT4 + 0x10) | ||
| 225 | #define GPTIMER5_SYSCONFIG __REG32(OMAP24XX_GPT5 + 0x10) | ||
| 226 | #define GPTIMER6_SYSCONFIG __REG32(OMAP24XX_GPT6 + 0x10) | ||
| 227 | #define GPTIMER7_SYSCONFIG __REG32(OMAP24XX_GPT7 + 0x10) | ||
| 228 | #define GPTIMER8_SYSCONFIG __REG32(OMAP24XX_GPT8 + 0x10) | ||
| 229 | #define GPTIMER9_SYSCONFIG __REG32(OMAP24XX_GPT9 + 0x10) | ||
| 230 | #define GPTIMER10_SYSCONFIG __REG32(OMAP24XX_GPT10 + 0x10) | ||
| 231 | #define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10) | ||
| 232 | #define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10) | ||
| 233 | |||
| 234 | /* FIXME: Move these to gpio code */ | ||
| 235 | #define OMAP24XX_GPIO_BASE 0x48018000 | ||
| 236 | #define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE + (0x2000 * ((X) - 1))) | ||
| 237 | |||
| 238 | #define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1) + 0x10)) | ||
| 239 | #define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2) + 0x10)) | ||
| 240 | #define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3) + 0x10)) | ||
| 241 | #define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4) + 0x10)) | ||
| 242 | |||
| 243 | #if defined(CONFIG_ARCH_OMAP243X) | ||
| 244 | #define GPIO5_SYSCONFIG __REG32((OMAP24XX_GPIO5_BASE + 0x10)) | ||
| 245 | #endif | ||
| 246 | |||
| 247 | /* GP TIMER 1 */ | ||
| 248 | #define GPTIMER1_TISTAT GPT1_REG32(0x014) | ||
| 249 | #define GPTIMER1_TISR GPT1_REG32(0x018) | ||
| 250 | #define GPTIMER1_TIER GPT1_REG32(0x01C) | ||
| 251 | #define GPTIMER1_TWER GPT1_REG32(0x020) | ||
| 252 | #define GPTIMER1_TCLR GPT1_REG32(0x024) | ||
| 253 | #define GPTIMER1_TCRR GPT1_REG32(0x028) | ||
| 254 | #define GPTIMER1_TLDR GPT1_REG32(0x02C) | ||
| 255 | #define GPTIMER1_TTGR GPT1_REG32(0x030) | ||
| 256 | #define GPTIMER1_TWPS GPT1_REG32(0x034) | ||
| 257 | #define GPTIMER1_TMAR GPT1_REG32(0x038) | ||
| 258 | #define GPTIMER1_TCAR1 GPT1_REG32(0x03C) | ||
| 259 | #define GPTIMER1_TSICR GPT1_REG32(0x040) | ||
| 260 | #define GPTIMER1_TCAR2 GPT1_REG32(0x044) | ||
| 261 | |||
| 262 | /* rkw -- base fix up please... */ | ||
| 263 | #define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE + 0x78018) | ||
| 264 | |||
| 265 | /* SDRC */ | ||
| 266 | #define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x060) | ||
| 267 | #define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x064) | ||
| 268 | #define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x068) | ||
| 269 | #define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x06C) | ||
| 270 | #define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE + 0x070) | ||
| 271 | #define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE + 0x084) | ||
| 272 | |||
| 273 | /* GPIO 1 */ | ||
| 274 | #define GPIO1_BASE GPIOX_BASE(1) | ||
| 275 | #define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset)) | ||
| 276 | #define GPIO1_IRQENABLE1 GPIO1_REG32(0x01C) | ||
| 277 | #define GPIO1_IRQSTATUS1 GPIO1_REG32(0x018) | ||
| 278 | #define GPIO1_IRQENABLE2 GPIO1_REG32(0x02C) | ||
| 279 | #define GPIO1_IRQSTATUS2 GPIO1_REG32(0x028) | ||
| 280 | #define GPIO1_WAKEUPENABLE GPIO1_REG32(0x020) | ||
| 281 | #define GPIO1_RISINGDETECT GPIO1_REG32(0x048) | ||
| 282 | #define GPIO1_DATAIN GPIO1_REG32(0x038) | ||
| 283 | #define GPIO1_OE GPIO1_REG32(0x034) | ||
| 284 | #define GPIO1_DATAOUT GPIO1_REG32(0x03C) | ||
| 285 | |||
| 286 | /* GPIO2 */ | ||
| 287 | #define GPIO2_BASE GPIOX_BASE(2) | ||
| 288 | #define GPIO2_REG32(offset) __REG32(GPIO2_BASE + (offset)) | ||
| 289 | #define GPIO2_IRQENABLE1 GPIO2_REG32(0x01C) | ||
| 290 | #define GPIO2_IRQSTATUS1 GPIO2_REG32(0x018) | ||
| 291 | #define GPIO2_IRQENABLE2 GPIO2_REG32(0x02C) | ||
| 292 | #define GPIO2_IRQSTATUS2 GPIO2_REG32(0x028) | ||
| 293 | #define GPIO2_WAKEUPENABLE GPIO2_REG32(0x020) | ||
| 294 | #define GPIO2_RISINGDETECT GPIO2_REG32(0x048) | ||
| 295 | #define GPIO2_DATAIN GPIO2_REG32(0x038) | ||
| 296 | #define GPIO2_OE GPIO2_REG32(0x034) | ||
| 297 | #define GPIO2_DATAOUT GPIO2_REG32(0x03C) | ||
| 298 | #define GPIO2_DEBOUNCENABLE GPIO2_REG32(0x050) | ||
| 299 | #define GPIO2_DEBOUNCINGTIME GPIO2_REG32(0x054) | ||
| 300 | |||
| 301 | /* GPIO 3 */ | ||
| 302 | #define GPIO3_BASE GPIOX_BASE(3) | ||
| 303 | #define GPIO3_REG32(offset) __REG32(GPIO3_BASE + (offset)) | ||
| 304 | #define GPIO3_IRQENABLE1 GPIO3_REG32(0x01C) | ||
| 305 | #define GPIO3_IRQSTATUS1 GPIO3_REG32(0x018) | ||
| 306 | #define GPIO3_IRQENABLE2 GPIO3_REG32(0x02C) | ||
| 307 | #define GPIO3_IRQSTATUS2 GPIO3_REG32(0x028) | ||
| 308 | #define GPIO3_WAKEUPENABLE GPIO3_REG32(0x020) | ||
| 309 | #define GPIO3_RISINGDETECT GPIO3_REG32(0x048) | ||
| 310 | #define GPIO3_FALLINGDETECT GPIO3_REG32(0x04C) | ||
| 311 | #define GPIO3_DATAIN GPIO3_REG32(0x038) | ||
| 312 | #define GPIO3_OE GPIO3_REG32(0x034) | ||
| 313 | #define GPIO3_DATAOUT GPIO3_REG32(0x03C) | ||
| 314 | #define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050) | ||
| 315 | #define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054) | ||
| 316 | #define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050) | ||
| 317 | #define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054) | ||
| 318 | |||
| 319 | /* GPIO 4 */ | ||
| 320 | #define GPIO4_BASE GPIOX_BASE(4) | ||
| 321 | #define GPIO4_REG32(offset) __REG32(GPIO4_BASE + (offset)) | ||
| 322 | #define GPIO4_IRQENABLE1 GPIO4_REG32(0x01C) | ||
| 323 | #define GPIO4_IRQSTATUS1 GPIO4_REG32(0x018) | ||
| 324 | #define GPIO4_IRQENABLE2 GPIO4_REG32(0x02C) | ||
| 325 | #define GPIO4_IRQSTATUS2 GPIO4_REG32(0x028) | ||
| 326 | #define GPIO4_WAKEUPENABLE GPIO4_REG32(0x020) | ||
| 327 | #define GPIO4_RISINGDETECT GPIO4_REG32(0x048) | ||
| 328 | #define GPIO4_FALLINGDETECT GPIO4_REG32(0x04C) | ||
| 329 | #define GPIO4_DATAIN GPIO4_REG32(0x038) | ||
| 330 | #define GPIO4_OE GPIO4_REG32(0x034) | ||
| 331 | #define GPIO4_DATAOUT GPIO4_REG32(0x03C) | ||
| 332 | #define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050) | ||
| 333 | #define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054) | ||
| 334 | |||
| 335 | #if defined(CONFIG_ARCH_OMAP243X) | ||
| 336 | /* GPIO 5 */ | ||
| 337 | #define GPIO5_REG32(offset) __REG32((OMAP24XX_GPIO5_BASE + (offset))) | ||
| 338 | #define GPIO5_IRQENABLE1 GPIO5_REG32(0x01C) | ||
| 339 | #define GPIO5_IRQSTATUS1 GPIO5_REG32(0x018) | ||
| 340 | #define GPIO5_IRQENABLE2 GPIO5_REG32(0x02C) | ||
| 341 | #define GPIO5_IRQSTATUS2 GPIO5_REG32(0x028) | ||
| 342 | #define GPIO5_WAKEUPENABLE GPIO5_REG32(0x020) | ||
| 343 | #define GPIO5_RISINGDETECT GPIO5_REG32(0x048) | ||
| 344 | #define GPIO5_FALLINGDETECT GPIO5_REG32(0x04C) | ||
| 345 | #define GPIO5_DATAIN GPIO5_REG32(0x038) | ||
| 346 | #define GPIO5_OE GPIO5_REG32(0x034) | ||
| 347 | #define GPIO5_DATAOUT GPIO5_REG32(0x03C) | ||
| 348 | #define GPIO5_DEBOUNCENABLE GPIO5_REG32(0x050) | ||
| 349 | #define GPIO5_DEBOUNCINGTIME GPIO5_REG32(0x054) | ||
| 350 | #endif | ||
| 351 | |||
| 352 | /* IO CONFIG */ | ||
| 353 | #define OMAP24XX_CTRL_BASE (L4_24XX_BASE) | ||
| 354 | #define CONTROL_REG32(offset) __REG32(OMAP24XX_CTRL_BASE + (offset)) | ||
| 355 | |||
| 356 | #define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104) | ||
| 357 | #define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134) | ||
| 358 | #define CONTROL_PADCONF_UART1_RX CONTROL_REG32(0x0C8) | ||
| 359 | #define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C) | ||
| 360 | #define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090) | ||
| 361 | #define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8) | ||
| 362 | #define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC) /* 2420 */ | ||
| 363 | #define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0) | ||
| 364 | #define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC) | ||
| 365 | #define CONTROL_PADCONF_SYS_NIRQW0 CONTROL_REG32(0x0BC) /* 2430 */ | ||
| 366 | #define CONTROL_PADCONF_SSI1_FLAG_TX CONTROL_REG32(0x108) /* 2430 */ | ||
| 367 | |||
| 368 | /* CONTROL */ | ||
| 369 | #define CONTROL_DEVCONF CONTROL_REG32(0x274) | ||
| 370 | #define CONTROL_DEVCONF1 CONTROL_REG32(0x2E8) | ||
| 371 | |||
| 372 | /* INTERRUPT CONTROLLER */ | ||
| 373 | #define INTC_BASE ((L4_24XX_BASE) + 0xfe000) | ||
| 374 | #define INTC_REG32(offset) __REG32(INTC_BASE + (offset)) | ||
| 375 | |||
| 376 | #define INTC1_U_BASE INTC_REG32(0x000) | ||
| 377 | #define INTC_MIR0 INTC_REG32(0x084) | ||
| 378 | #define INTC_MIR_SET0 INTC_REG32(0x08C) | ||
| 379 | #define INTC_MIR_CLEAR0 INTC_REG32(0x088) | ||
| 380 | #define INTC_ISR_CLEAR0 INTC_REG32(0x094) | ||
| 381 | #define INTC_MIR1 INTC_REG32(0x0A4) | ||
| 382 | #define INTC_MIR_SET1 INTC_REG32(0x0AC) | ||
| 383 | #define INTC_MIR_CLEAR1 INTC_REG32(0x0A8) | ||
| 384 | #define INTC_ISR_CLEAR1 INTC_REG32(0x0B4) | ||
| 385 | #define INTC_MIR2 INTC_REG32(0x0C4) | ||
| 386 | #define INTC_MIR_SET2 INTC_REG32(0x0CC) | ||
| 387 | #define INTC_MIR_CLEAR2 INTC_REG32(0x0C8) | ||
| 388 | #define INTC_ISR_CLEAR2 INTC_REG32(0x0D4) | ||
| 389 | #define INTC_SIR_IRQ INTC_REG32(0x040) | ||
| 390 | #define INTC_CONTROL INTC_REG32(0x048) | ||
| 391 | #define INTC_ILR11 INTC_REG32(0x12C) /* PRCM on MPU PIC */ | ||
| 392 | #define INTC_ILR30 INTC_REG32(0x178) | ||
| 393 | #define INTC_ILR31 INTC_REG32(0x17C) | ||
| 394 | #define INTC_ILR32 INTC_REG32(0x180) | ||
| 395 | #define INTC_ILR37 INTC_REG32(0x194) /* GPIO4 on MPU PIC */ | ||
| 396 | #define INTC_SYSCONFIG INTC_REG32(0x010) /* GPT1 on MPU PIC */ | ||
| 397 | |||
| 398 | /* RAM FIREWALL */ | ||
| 399 | #define RAMFW_BASE (0x68005000) | ||
| 400 | #define RAMFW_REG32(offset) __REG32(RAMFW_BASE + (offset)) | ||
| 401 | |||
| 402 | #define RAMFW_REQINFOPERM0 RAMFW_REG32(0x048) | ||
| 403 | #define RAMFW_READPERM0 RAMFW_REG32(0x050) | ||
| 404 | #define RAMFW_WRITEPERM0 RAMFW_REG32(0x058) | ||
| 405 | |||
| 406 | /* GPMC CS1 FPGA ON USER INTERFACE MODULE */ | ||
| 407 | //#define DEBUG_BOARD_LED_REGISTER 0x04000014 | ||
| 408 | |||
| 409 | /* GPMC CS0 */ | ||
| 410 | #define GPMC_CONFIG1_0 GPMC_REG32(0x060) | ||
| 411 | #define GPMC_CONFIG2_0 GPMC_REG32(0x064) | ||
| 412 | #define GPMC_CONFIG3_0 GPMC_REG32(0x068) | ||
| 413 | #define GPMC_CONFIG4_0 GPMC_REG32(0x06C) | ||
| 414 | #define GPMC_CONFIG5_0 GPMC_REG32(0x070) | ||
| 415 | #define GPMC_CONFIG6_0 GPMC_REG32(0x074) | ||
| 416 | #define GPMC_CONFIG7_0 GPMC_REG32(0x078) | ||
| 417 | |||
| 418 | /* GPMC CS1 */ | ||
| 419 | #define GPMC_CONFIG1_1 GPMC_REG32(0x090) | ||
| 420 | #define GPMC_CONFIG2_1 GPMC_REG32(0x094) | ||
| 421 | #define GPMC_CONFIG3_1 GPMC_REG32(0x098) | ||
| 422 | #define GPMC_CONFIG4_1 GPMC_REG32(0x09C) | ||
| 423 | #define GPMC_CONFIG5_1 GPMC_REG32(0x0a0) | ||
| 424 | #define GPMC_CONFIG6_1 GPMC_REG32(0x0a4) | ||
| 425 | #define GPMC_CONFIG7_1 GPMC_REG32(0x0a8) | ||
| 426 | |||
| 427 | /* GPMC CS3 */ | ||
| 428 | #define GPMC_CONFIG1_3 GPMC_REG32(0x0F0) | ||
| 429 | #define GPMC_CONFIG2_3 GPMC_REG32(0x0F4) | ||
| 430 | #define GPMC_CONFIG3_3 GPMC_REG32(0x0F8) | ||
| 431 | #define GPMC_CONFIG4_3 GPMC_REG32(0x0FC) | ||
| 432 | #define GPMC_CONFIG5_3 GPMC_REG32(0x100) | ||
| 433 | #define GPMC_CONFIG6_3 GPMC_REG32(0x104) | ||
| 434 | #define GPMC_CONFIG7_3 GPMC_REG32(0x108) | ||
| 435 | |||
| 436 | /* DSS */ | ||
| 437 | #define DSS_CONTROL DISP_REG32(0x040) | ||
| 438 | #define DISPC_CONTROL DISP_REG32(0x440) | ||
| 439 | #define DISPC_SYSSTATUS DISP_REG32(0x414) | ||
| 440 | #define DISPC_IRQSTATUS DISP_REG32(0x418) | ||
| 441 | #define DISPC_IRQENABLE DISP_REG32(0x41C) | ||
| 442 | #define DISPC_CONFIG DISP_REG32(0x444) | ||
| 443 | #define DISPC_DEFAULT_COLOR0 DISP_REG32(0x44C) | ||
| 444 | #define DISPC_DEFAULT_COLOR1 DISP_REG32(0x450) | ||
| 445 | #define DISPC_TRANS_COLOR0 DISP_REG32(0x454) | ||
| 446 | #define DISPC_TRANS_COLOR1 DISP_REG32(0x458) | ||
| 447 | #define DISPC_LINE_NUMBER DISP_REG32(0x460) | ||
| 448 | #define DISPC_TIMING_H DISP_REG32(0x464) | ||
| 449 | #define DISPC_TIMING_V DISP_REG32(0x468) | ||
| 450 | #define DISPC_POL_FREQ DISP_REG32(0x46C) | ||
| 451 | #define DISPC_DIVISOR DISP_REG32(0x470) | ||
| 452 | #define DISPC_SIZE_DIG DISP_REG32(0x478) | ||
| 453 | #define DISPC_SIZE_LCD DISP_REG32(0x47C) | ||
| 454 | #define DISPC_GFX_BA0 DISP_REG32(0x480) | ||
| 455 | #define DISPC_GFX_BA1 DISP_REG32(0x484) | ||
| 456 | #define DISPC_GFX_POSITION DISP_REG32(0x488) | ||
| 457 | #define DISPC_GFX_SIZE DISP_REG32(0x48C) | ||
| 458 | #define DISPC_GFX_ATTRIBUTES DISP_REG32(0x4A0) | ||
| 459 | #define DISPC_GFX_FIFO_THRESHOLD DISP_REG32(0x4A4) | ||
| 460 | #define DISPC_GFX_ROW_INC DISP_REG32(0x4AC) | ||
| 461 | #define DISPC_GFX_PIXEL_INC DISP_REG32(0x4B0) | ||
| 462 | #define DISPC_GFX_WINDOW_SKIP DISP_REG32(0x4B4) | ||
| 463 | #define DISPC_GFX_TABLE_BA DISP_REG32(0x4B8) | ||
| 464 | #define DISPC_DATA_CYCLE1 DISP_REG32(0x5D4) | ||
| 465 | #define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8) | ||
| 466 | #define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC) | ||
| 467 | |||
| 468 | /* HSUSB Suspend */ | ||
| 469 | #define HSUSB_CTRL __REG8(0x480AC001) | ||
| 470 | #define USBOTG_POWER __REG32(0x480AC000) | ||
| 471 | |||
| 472 | /* HS MMC */ | ||
| 473 | #define MMCHS1_SYSCONFIG __REG32(0x4809C010) | ||
| 474 | #define MMCHS2_SYSCONFIG __REG32(0x480b4010) | ||
| 475 | |||
| 476 | #endif /* __ASSEMBLER__ */ | ||
| 477 | |||
| 478 | #endif | ||
| 479 | |||
| 480 | |||
| 481 | |||
| 482 | |||
| 483 | |||
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 90f530540c65..b12f423b8595 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c | |||
| @@ -17,19 +17,27 @@ | |||
| 17 | #include <linux/init.h> | 17 | #include <linux/init.h> |
| 18 | #include <linux/clk.h> | 18 | #include <linux/clk.h> |
| 19 | 19 | ||
| 20 | #include "prcm-regs.h" | 20 | #include <asm/io.h> |
| 21 | |||
| 22 | #include "prm.h" | ||
| 23 | #include "prm-regbits-24xx.h" | ||
| 21 | 24 | ||
| 22 | extern void omap2_clk_prepare_for_reboot(void); | 25 | extern void omap2_clk_prepare_for_reboot(void); |
| 23 | 26 | ||
| 24 | u32 omap_prcm_get_reset_sources(void) | 27 | u32 omap_prcm_get_reset_sources(void) |
| 25 | { | 28 | { |
| 26 | return RM_RSTST_WKUP & 0x7f; | 29 | return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f; |
| 27 | } | 30 | } |
| 28 | EXPORT_SYMBOL(omap_prcm_get_reset_sources); | 31 | EXPORT_SYMBOL(omap_prcm_get_reset_sources); |
| 29 | 32 | ||
| 30 | /* Resets clock rates and reboots the system. Only called from system.h */ | 33 | /* Resets clock rates and reboots the system. Only called from system.h */ |
| 31 | void omap_prcm_arch_reset(char mode) | 34 | void omap_prcm_arch_reset(char mode) |
| 32 | { | 35 | { |
| 36 | u32 wkup; | ||
| 33 | omap2_clk_prepare_for_reboot(); | 37 | omap2_clk_prepare_for_reboot(); |
| 34 | RM_RSTCTRL_WKUP |= 2; | 38 | |
| 39 | if (cpu_is_omap24xx()) { | ||
| 40 | wkup = prm_read_mod_reg(WKUP_MOD, RM_RSTCTRL) | OMAP_RST_DPLL3; | ||
| 41 | prm_write_mod_reg(wkup, WKUP_MOD, RM_RSTCTRL); | ||
| 42 | } | ||
| 35 | } | 43 | } |
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h new file mode 100644 index 000000000000..c6d17a3378ec --- /dev/null +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h | |||
| @@ -0,0 +1,279 @@ | |||
| 1 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H | ||
| 2 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * OMAP24XX Power/Reset Management register bits | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 8 | * Copyright (C) 2007 Nokia Corporation | ||
| 9 | * | ||
| 10 | * Written by Paul Walmsley | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include "prm.h" | ||
| 18 | |||
| 19 | /* Bits shared between registers */ | ||
| 20 | |||
| 21 | /* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */ | ||
| 22 | #define OMAP24XX_VOLTTRANS_ST (1 << 2) | ||
| 23 | #define OMAP24XX_WKUP2_ST (1 << 1) | ||
| 24 | #define OMAP24XX_WKUP1_ST (1 << 0) | ||
| 25 | |||
| 26 | /* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */ | ||
| 27 | #define OMAP24XX_VOLTTRANS_EN (1 << 2) | ||
| 28 | #define OMAP24XX_WKUP2_EN (1 << 1) | ||
| 29 | #define OMAP24XX_WKUP1_EN (1 << 0) | ||
| 30 | |||
| 31 | /* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */ | ||
| 32 | #define OMAP24XX_EN_MPU (1 << 1) | ||
| 33 | #define OMAP24XX_EN_CORE (1 << 0) | ||
| 34 | |||
| 35 | /* | ||
| 36 | * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM | ||
| 37 | * shared bits | ||
| 38 | */ | ||
| 39 | #define OMAP24XX_MEMONSTATE_SHIFT 10 | ||
| 40 | #define OMAP24XX_MEMONSTATE_MASK (0x3 << 10) | ||
| 41 | #define OMAP24XX_MEMRETSTATE (1 << 3) | ||
| 42 | |||
| 43 | /* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */ | ||
| 44 | #define OMAP24XX_FORCESTATE (1 << 18) | ||
| 45 | |||
| 46 | /* | ||
| 47 | * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP, | ||
| 48 | * PM_PWSTST_MDM shared bits | ||
| 49 | */ | ||
| 50 | #define OMAP24XX_CLKACTIVITY (1 << 19) | ||
| 51 | |||
| 52 | /* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */ | ||
| 53 | #define OMAP24XX_LASTSTATEENTERED_SHIFT 4 | ||
| 54 | #define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4) | ||
| 55 | |||
| 56 | /* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */ | ||
| 57 | #define OMAP2430_MEMSTATEST_SHIFT 10 | ||
| 58 | #define OMAP2430_MEMSTATEST_MASK (0x3 << 10) | ||
| 59 | |||
| 60 | /* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */ | ||
| 61 | #define OMAP24XX_POWERSTATEST_SHIFT 0 | ||
| 62 | #define OMAP24XX_POWERSTATEST_MASK (0x3 << 0) | ||
| 63 | |||
| 64 | |||
| 65 | /* Bits specific to each register */ | ||
| 66 | |||
| 67 | /* PRCM_REVISION */ | ||
| 68 | #define OMAP24XX_REV_SHIFT 0 | ||
| 69 | #define OMAP24XX_REV_MASK (0xff << 0) | ||
| 70 | |||
| 71 | /* PRCM_SYSCONFIG */ | ||
| 72 | #define OMAP24XX_AUTOIDLE (1 << 0) | ||
| 73 | |||
| 74 | /* PRCM_IRQSTATUS_MPU specific bits */ | ||
| 75 | #define OMAP2430_DPLL_RECAL_ST (1 << 6) | ||
| 76 | #define OMAP24XX_TRANSITION_ST (1 << 5) | ||
| 77 | #define OMAP24XX_EVGENOFF_ST (1 << 4) | ||
| 78 | #define OMAP24XX_EVGENON_ST (1 << 3) | ||
| 79 | |||
| 80 | /* PRCM_IRQENABLE_MPU specific bits */ | ||
| 81 | #define OMAP2430_DPLL_RECAL_EN (1 << 6) | ||
| 82 | #define OMAP24XX_TRANSITION_EN (1 << 5) | ||
| 83 | #define OMAP24XX_EVGENOFF_EN (1 << 4) | ||
| 84 | #define OMAP24XX_EVGENON_EN (1 << 3) | ||
| 85 | |||
| 86 | /* PRCM_VOLTCTRL */ | ||
| 87 | #define OMAP24XX_AUTO_EXTVOLT (1 << 15) | ||
| 88 | #define OMAP24XX_FORCE_EXTVOLT (1 << 14) | ||
| 89 | #define OMAP24XX_SETOFF_LEVEL_SHIFT 12 | ||
| 90 | #define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12) | ||
| 91 | #define OMAP24XX_MEMRETCTRL (1 << 8) | ||
| 92 | #define OMAP24XX_SETRET_LEVEL_SHIFT 6 | ||
| 93 | #define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6) | ||
| 94 | #define OMAP24XX_VOLT_LEVEL_SHIFT 0 | ||
| 95 | #define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0) | ||
| 96 | |||
| 97 | /* PRCM_VOLTST */ | ||
| 98 | #define OMAP24XX_ST_VOLTLEVEL_SHIFT 0 | ||
| 99 | #define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0) | ||
| 100 | |||
| 101 | /* PRCM_CLKSRC_CTRL specific bits */ | ||
| 102 | |||
| 103 | /* PRCM_CLKOUT_CTRL */ | ||
| 104 | #define OMAP2420_CLKOUT2_EN_SHIFT 15 | ||
| 105 | #define OMAP2420_CLKOUT2_EN (1 << 15) | ||
| 106 | #define OMAP2420_CLKOUT2_DIV_SHIFT 11 | ||
| 107 | #define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) | ||
| 108 | #define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 | ||
| 109 | #define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) | ||
| 110 | #define OMAP24XX_CLKOUT_EN_SHIFT 7 | ||
| 111 | #define OMAP24XX_CLKOUT_EN (1 << 7) | ||
| 112 | #define OMAP24XX_CLKOUT_DIV_SHIFT 3 | ||
| 113 | #define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) | ||
| 114 | #define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 | ||
| 115 | #define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) | ||
| 116 | |||
| 117 | /* PRCM_CLKEMUL_CTRL */ | ||
| 118 | #define OMAP24XX_EMULATION_EN_SHIFT 0 | ||
| 119 | #define OMAP24XX_EMULATION_EN (1 << 0) | ||
| 120 | |||
| 121 | /* PRCM_CLKCFG_CTRL */ | ||
| 122 | #define OMAP24XX_VALID_CONFIG (1 << 0) | ||
| 123 | |||
| 124 | /* PRCM_CLKCFG_STATUS */ | ||
| 125 | #define OMAP24XX_CONFIG_STATUS (1 << 0) | ||
| 126 | |||
| 127 | /* PRCM_VOLTSETUP specific bits */ | ||
| 128 | |||
| 129 | /* PRCM_CLKSSETUP specific bits */ | ||
| 130 | |||
| 131 | /* PRCM_POLCTRL */ | ||
| 132 | #define OMAP2420_CLKOUT2_POL (1 << 10) | ||
| 133 | #define OMAP24XX_CLKOUT_POL (1 << 9) | ||
| 134 | #define OMAP24XX_CLKREQ_POL (1 << 8) | ||
| 135 | #define OMAP2430_USE_POWEROK (1 << 2) | ||
| 136 | #define OMAP2430_POWEROK_POL (1 << 1) | ||
| 137 | #define OMAP24XX_EXTVOL_POL (1 << 0) | ||
| 138 | |||
| 139 | /* RM_RSTST_MPU specific bits */ | ||
| 140 | /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */ | ||
| 141 | |||
| 142 | /* PM_WKDEP_MPU specific bits */ | ||
| 143 | #define OMAP2430_PM_WKDEP_MPU_EN_MDM (1 << 5) | ||
| 144 | #define OMAP24XX_PM_WKDEP_MPU_EN_DSP (1 << 2) | ||
| 145 | |||
| 146 | /* PM_EVGENCTRL_MPU specific bits */ | ||
| 147 | |||
| 148 | /* PM_EVEGENONTIM_MPU specific bits */ | ||
| 149 | |||
| 150 | /* PM_EVEGENOFFTIM_MPU specific bits */ | ||
| 151 | |||
| 152 | /* PM_PWSTCTRL_MPU specific bits */ | ||
| 153 | #define OMAP2430_FORCESTATE (1 << 18) | ||
| 154 | |||
| 155 | /* PM_PWSTST_MPU specific bits */ | ||
| 156 | /* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */ | ||
| 157 | |||
| 158 | /* PM_WKEN1_CORE specific bits */ | ||
| 159 | |||
| 160 | /* PM_WKEN2_CORE specific bits */ | ||
| 161 | |||
| 162 | /* PM_WKST1_CORE specific bits*/ | ||
| 163 | |||
| 164 | /* PM_WKST2_CORE specific bits */ | ||
| 165 | |||
| 166 | /* PM_WKDEP_CORE specific bits*/ | ||
| 167 | #define OMAP2430_PM_WKDEP_CORE_EN_MDM (1 << 5) | ||
| 168 | #define OMAP24XX_PM_WKDEP_CORE_EN_GFX (1 << 3) | ||
| 169 | #define OMAP24XX_PM_WKDEP_CORE_EN_DSP (1 << 2) | ||
| 170 | |||
| 171 | /* PM_PWSTCTRL_CORE specific bits */ | ||
| 172 | #define OMAP24XX_MEMORYCHANGE (1 << 20) | ||
| 173 | #define OMAP24XX_MEM3ONSTATE_SHIFT 14 | ||
| 174 | #define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14) | ||
| 175 | #define OMAP24XX_MEM2ONSTATE_SHIFT 12 | ||
| 176 | #define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12) | ||
| 177 | #define OMAP24XX_MEM1ONSTATE_SHIFT 10 | ||
| 178 | #define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10) | ||
| 179 | #define OMAP24XX_MEM3RETSTATE (1 << 5) | ||
| 180 | #define OMAP24XX_MEM2RETSTATE (1 << 4) | ||
| 181 | #define OMAP24XX_MEM1RETSTATE (1 << 3) | ||
| 182 | |||
| 183 | /* PM_PWSTST_CORE specific bits */ | ||
| 184 | #define OMAP24XX_MEM3STATEST_SHIFT 14 | ||
| 185 | #define OMAP24XX_MEM3STATEST_MASK (0x3 << 14) | ||
| 186 | #define OMAP24XX_MEM2STATEST_SHIFT 12 | ||
| 187 | #define OMAP24XX_MEM2STATEST_MASK (0x3 << 12) | ||
| 188 | #define OMAP24XX_MEM1STATEST_SHIFT 10 | ||
| 189 | #define OMAP24XX_MEM1STATEST_MASK (0x3 << 10) | ||
| 190 | |||
| 191 | /* RM_RSTCTRL_GFX */ | ||
| 192 | #define OMAP24XX_GFX_RST (1 << 0) | ||
| 193 | |||
| 194 | /* RM_RSTST_GFX specific bits */ | ||
| 195 | #define OMAP24XX_GFX_SW_RST (1 << 4) | ||
| 196 | |||
| 197 | /* PM_PWSTCTRL_GFX specific bits */ | ||
| 198 | |||
| 199 | /* PM_WKDEP_GFX specific bits */ | ||
| 200 | /* 2430 often calls EN_WAKEUP "EN_WKUP" */ | ||
| 201 | |||
| 202 | /* RM_RSTCTRL_WKUP specific bits */ | ||
| 203 | |||
| 204 | /* RM_RSTTIME_WKUP specific bits */ | ||
| 205 | |||
| 206 | /* RM_RSTST_WKUP specific bits */ | ||
| 207 | /* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */ | ||
| 208 | #define OMAP24XX_EXTWMPU_RST (1 << 6) | ||
| 209 | #define OMAP24XX_SECU_WD_RST (1 << 5) | ||
| 210 | #define OMAP24XX_MPU_WD_RST (1 << 4) | ||
| 211 | #define OMAP24XX_SECU_VIOL_RST (1 << 3) | ||
| 212 | |||
| 213 | /* PM_WKEN_WKUP specific bits */ | ||
| 214 | |||
| 215 | /* PM_WKST_WKUP specific bits */ | ||
| 216 | |||
| 217 | /* RM_RSTCTRL_DSP */ | ||
| 218 | #define OMAP2420_RST_IVA (1 << 8) | ||
| 219 | #define OMAP24XX_RST2_DSP (1 << 1) | ||
| 220 | #define OMAP24XX_RST1_DSP (1 << 0) | ||
| 221 | |||
| 222 | /* RM_RSTST_DSP specific bits */ | ||
| 223 | /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */ | ||
| 224 | #define OMAP2420_IVA_SW_RST (1 << 8) | ||
| 225 | #define OMAP24XX_DSP_SW_RST2 (1 << 5) | ||
| 226 | #define OMAP24XX_DSP_SW_RST1 (1 << 4) | ||
| 227 | |||
| 228 | /* PM_WKDEP_DSP specific bits */ | ||
| 229 | |||
| 230 | /* PM_PWSTCTRL_DSP specific bits */ | ||
| 231 | /* 2430 only: MEMONSTATE, MEMRETSTATE */ | ||
| 232 | #define OMAP2420_MEMIONSTATE_SHIFT 12 | ||
| 233 | #define OMAP2420_MEMIONSTATE_MASK (0x3 << 12) | ||
| 234 | #define OMAP2420_MEMIRETSTATE (1 << 4) | ||
| 235 | |||
| 236 | /* PM_PWSTST_DSP specific bits */ | ||
| 237 | /* MEMSTATEST is 2430 only */ | ||
| 238 | #define OMAP2420_MEMISTATEST_SHIFT 12 | ||
| 239 | #define OMAP2420_MEMISTATEST_MASK (0x3 << 12) | ||
| 240 | |||
| 241 | /* PRCM_IRQSTATUS_DSP specific bits */ | ||
| 242 | |||
| 243 | /* PRCM_IRQENABLE_DSP specific bits */ | ||
| 244 | |||
| 245 | /* RM_RSTCTRL_MDM */ | ||
| 246 | /* 2430 only */ | ||
| 247 | #define OMAP2430_PWRON1_MDM (1 << 1) | ||
| 248 | #define OMAP2430_RST1_MDM (1 << 0) | ||
| 249 | |||
| 250 | /* RM_RSTST_MDM specific bits */ | ||
| 251 | /* 2430 only */ | ||
| 252 | #define OMAP2430_MDM_SECU_VIOL (1 << 6) | ||
| 253 | #define OMAP2430_MDM_SW_PWRON1 (1 << 5) | ||
| 254 | #define OMAP2430_MDM_SW_RST1 (1 << 4) | ||
| 255 | |||
| 256 | /* PM_WKEN_MDM */ | ||
| 257 | /* 2430 only */ | ||
| 258 | #define OMAP2430_PM_WKEN_MDM_EN_MDM (1 << 0) | ||
| 259 | |||
| 260 | /* PM_WKST_MDM specific bits */ | ||
| 261 | /* 2430 only */ | ||
| 262 | |||
| 263 | /* PM_WKDEP_MDM specific bits */ | ||
| 264 | /* 2430 only */ | ||
| 265 | |||
| 266 | /* PM_PWSTCTRL_MDM specific bits */ | ||
| 267 | /* 2430 only */ | ||
| 268 | #define OMAP2430_KILLDOMAINWKUP (1 << 19) | ||
| 269 | |||
| 270 | /* PM_PWSTST_MDM specific bits */ | ||
| 271 | /* 2430 only */ | ||
| 272 | |||
| 273 | /* PRCM_IRQSTATUS_IVA */ | ||
| 274 | /* 2420 only */ | ||
| 275 | |||
| 276 | /* PRCM_IRQENABLE_IVA */ | ||
| 277 | /* 2420 only */ | ||
| 278 | |||
| 279 | #endif | ||
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h new file mode 100644 index 000000000000..b4686bc345ca --- /dev/null +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h | |||
| @@ -0,0 +1,582 @@ | |||
| 1 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H | ||
| 2 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * OMAP3430 Power/Reset Management register bits | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | ||
| 8 | * Copyright (C) 2007-2008 Nokia Corporation | ||
| 9 | * | ||
| 10 | * Written by Paul Walmsley | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include "prm.h" | ||
| 18 | |||
| 19 | /* Shared register bits */ | ||
| 20 | |||
| 21 | /* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */ | ||
| 22 | #define OMAP3430_ON_SHIFT 24 | ||
| 23 | #define OMAP3430_ON_MASK (0xff << 24) | ||
| 24 | #define OMAP3430_ONLP_SHIFT 16 | ||
| 25 | #define OMAP3430_ONLP_MASK (0xff << 16) | ||
| 26 | #define OMAP3430_RET_SHIFT 8 | ||
| 27 | #define OMAP3430_RET_MASK (0xff << 8) | ||
| 28 | #define OMAP3430_OFF_SHIFT 0 | ||
| 29 | #define OMAP3430_OFF_MASK (0xff << 0) | ||
| 30 | |||
| 31 | /* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */ | ||
| 32 | #define OMAP3430_ERROROFFSET_SHIFT 24 | ||
| 33 | #define OMAP3430_ERROROFFSET_MASK (0xff << 24) | ||
| 34 | #define OMAP3430_ERRORGAIN_SHIFT 16 | ||
| 35 | #define OMAP3430_ERRORGAIN_MASK (0xff << 16) | ||
| 36 | #define OMAP3430_INITVOLTAGE_SHIFT 8 | ||
| 37 | #define OMAP3430_INITVOLTAGE_MASK (0xff << 8) | ||
| 38 | #define OMAP3430_TIMEOUTEN (1 << 3) | ||
| 39 | #define OMAP3430_INITVDD (1 << 2) | ||
| 40 | #define OMAP3430_FORCEUPDATE (1 << 1) | ||
| 41 | #define OMAP3430_VPENABLE (1 << 0) | ||
| 42 | |||
| 43 | /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */ | ||
| 44 | #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8 | ||
| 45 | #define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8) | ||
| 46 | #define OMAP3430_VSTEPMIN_SHIFT 0 | ||
| 47 | #define OMAP3430_VSTEPMIN_MASK (0xff << 0) | ||
| 48 | |||
| 49 | /* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */ | ||
| 50 | #define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8 | ||
| 51 | #define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8) | ||
| 52 | #define OMAP3430_VSTEPMAX_SHIFT 0 | ||
| 53 | #define OMAP3430_VSTEPMAX_MASK (0xff << 0) | ||
| 54 | |||
| 55 | /* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */ | ||
| 56 | #define OMAP3430_VDDMAX_SHIFT 24 | ||
| 57 | #define OMAP3430_VDDMAX_MASK (0xff << 24) | ||
| 58 | #define OMAP3430_VDDMIN_SHIFT 16 | ||
| 59 | #define OMAP3430_VDDMIN_MASK (0xff << 16) | ||
| 60 | #define OMAP3430_TIMEOUT_SHIFT 0 | ||
| 61 | #define OMAP3430_TIMEOUT_MASK (0xffff << 0) | ||
| 62 | |||
| 63 | /* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */ | ||
| 64 | #define OMAP3430_VPVOLTAGE_SHIFT 0 | ||
| 65 | #define OMAP3430_VPVOLTAGE_MASK (0xff << 0) | ||
| 66 | |||
| 67 | /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */ | ||
| 68 | #define OMAP3430_VPINIDLE (1 << 0) | ||
| 69 | |||
| 70 | /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ | ||
| 71 | #define OMAP3430_EN_PER (1 << 7) | ||
| 72 | |||
| 73 | /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ | ||
| 74 | #define OMAP3430_MEMORYCHANGE (1 << 3) | ||
| 75 | |||
| 76 | /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */ | ||
| 77 | #define OMAP3430_LOGICSTATEST (1 << 2) | ||
| 78 | |||
| 79 | /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ | ||
| 80 | #define OMAP3430_LASTLOGICSTATEENTERED (1 << 2) | ||
| 81 | |||
| 82 | /* | ||
| 83 | * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, | ||
| 84 | * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM, | ||
| 85 | * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits | ||
| 86 | */ | ||
| 87 | #define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0 | ||
| 88 | #define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) | ||
| 89 | |||
| 90 | /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */ | ||
| 91 | #define OMAP3430_WKUP_ST (1 << 0) | ||
| 92 | |||
| 93 | /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */ | ||
| 94 | #define OMAP3430_WKUP_EN (1 << 0) | ||
| 95 | |||
| 96 | /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */ | ||
| 97 | #define OMAP3430_GRPSEL_MMC2 (1 << 25) | ||
| 98 | #define OMAP3430_GRPSEL_MMC1 (1 << 24) | ||
| 99 | #define OMAP3430_GRPSEL_MCSPI4 (1 << 21) | ||
| 100 | #define OMAP3430_GRPSEL_MCSPI3 (1 << 20) | ||
| 101 | #define OMAP3430_GRPSEL_MCSPI2 (1 << 19) | ||
| 102 | #define OMAP3430_GRPSEL_MCSPI1 (1 << 18) | ||
| 103 | #define OMAP3430_GRPSEL_I2C3 (1 << 17) | ||
| 104 | #define OMAP3430_GRPSEL_I2C2 (1 << 16) | ||
| 105 | #define OMAP3430_GRPSEL_I2C1 (1 << 15) | ||
| 106 | #define OMAP3430_GRPSEL_UART2 (1 << 14) | ||
| 107 | #define OMAP3430_GRPSEL_UART1 (1 << 13) | ||
| 108 | #define OMAP3430_GRPSEL_GPT11 (1 << 12) | ||
| 109 | #define OMAP3430_GRPSEL_GPT10 (1 << 11) | ||
| 110 | #define OMAP3430_GRPSEL_MCBSP5 (1 << 10) | ||
| 111 | #define OMAP3430_GRPSEL_MCBSP1 (1 << 9) | ||
| 112 | #define OMAP3430_GRPSEL_HSOTGUSB (1 << 4) | ||
| 113 | #define OMAP3430_GRPSEL_D2D (1 << 3) | ||
| 114 | |||
| 115 | /* | ||
| 116 | * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, | ||
| 117 | * PM_PWSTCTRL_PER shared bits | ||
| 118 | */ | ||
| 119 | #define OMAP3430_MEMONSTATE_SHIFT 16 | ||
| 120 | #define OMAP3430_MEMONSTATE_MASK (0x3 << 16) | ||
| 121 | #define OMAP3430_MEMRETSTATE (1 << 8) | ||
| 122 | |||
| 123 | /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */ | ||
| 124 | #define OMAP3430_GRPSEL_GPIO6 (1 << 17) | ||
| 125 | #define OMAP3430_GRPSEL_GPIO5 (1 << 16) | ||
| 126 | #define OMAP3430_GRPSEL_GPIO4 (1 << 15) | ||
| 127 | #define OMAP3430_GRPSEL_GPIO3 (1 << 14) | ||
| 128 | #define OMAP3430_GRPSEL_GPIO2 (1 << 13) | ||
| 129 | #define OMAP3430_GRPSEL_UART3 (1 << 11) | ||
| 130 | #define OMAP3430_GRPSEL_GPT9 (1 << 10) | ||
| 131 | #define OMAP3430_GRPSEL_GPT8 (1 << 9) | ||
| 132 | #define OMAP3430_GRPSEL_GPT7 (1 << 8) | ||
| 133 | #define OMAP3430_GRPSEL_GPT6 (1 << 7) | ||
| 134 | #define OMAP3430_GRPSEL_GPT5 (1 << 6) | ||
| 135 | #define OMAP3430_GRPSEL_GPT4 (1 << 5) | ||
| 136 | #define OMAP3430_GRPSEL_GPT3 (1 << 4) | ||
| 137 | #define OMAP3430_GRPSEL_GPT2 (1 << 3) | ||
| 138 | #define OMAP3430_GRPSEL_MCBSP4 (1 << 2) | ||
| 139 | #define OMAP3430_GRPSEL_MCBSP3 (1 << 1) | ||
| 140 | #define OMAP3430_GRPSEL_MCBSP2 (1 << 0) | ||
| 141 | |||
| 142 | /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */ | ||
| 143 | #define OMAP3430_GRPSEL_IO (1 << 8) | ||
| 144 | #define OMAP3430_GRPSEL_SR2 (1 << 7) | ||
| 145 | #define OMAP3430_GRPSEL_SR1 (1 << 6) | ||
| 146 | #define OMAP3430_GRPSEL_GPIO1 (1 << 3) | ||
| 147 | #define OMAP3430_GRPSEL_GPT12 (1 << 1) | ||
| 148 | #define OMAP3430_GRPSEL_GPT1 (1 << 0) | ||
| 149 | |||
| 150 | /* Bits specific to each register */ | ||
| 151 | |||
| 152 | /* RM_RSTCTRL_IVA2 */ | ||
| 153 | #define OMAP3430_RST3_IVA2 (1 << 2) | ||
| 154 | #define OMAP3430_RST2_IVA2 (1 << 1) | ||
| 155 | #define OMAP3430_RST1_IVA2 (1 << 0) | ||
| 156 | |||
| 157 | /* RM_RSTST_IVA2 specific bits */ | ||
| 158 | #define OMAP3430_EMULATION_VSEQ_RST (1 << 13) | ||
| 159 | #define OMAP3430_EMULATION_VHWA_RST (1 << 12) | ||
| 160 | #define OMAP3430_EMULATION_IVA2_RST (1 << 11) | ||
| 161 | #define OMAP3430_IVA2_SW_RST3 (1 << 10) | ||
| 162 | #define OMAP3430_IVA2_SW_RST2 (1 << 9) | ||
| 163 | #define OMAP3430_IVA2_SW_RST1 (1 << 8) | ||
| 164 | |||
| 165 | /* PM_WKDEP_IVA2 specific bits */ | ||
| 166 | |||
| 167 | /* PM_PWSTCTRL_IVA2 specific bits */ | ||
| 168 | #define OMAP3430_L2FLATMEMONSTATE_SHIFT 22 | ||
| 169 | #define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22) | ||
| 170 | #define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20 | ||
| 171 | #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20) | ||
| 172 | #define OMAP3430_L1FLATMEMONSTATE_SHIFT 18 | ||
| 173 | #define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18) | ||
| 174 | #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16 | ||
| 175 | #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16) | ||
| 176 | #define OMAP3430_L2FLATMEMRETSTATE (1 << 11) | ||
| 177 | #define OMAP3430_SHAREDL2CACHEFLATRETSTATE (1 << 10) | ||
| 178 | #define OMAP3430_L1FLATMEMRETSTATE (1 << 9) | ||
| 179 | #define OMAP3430_SHAREDL1CACHEFLATRETSTATE (1 << 8) | ||
| 180 | |||
| 181 | /* PM_PWSTST_IVA2 specific bits */ | ||
| 182 | #define OMAP3430_L2FLATMEMSTATEST_SHIFT 10 | ||
| 183 | #define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10) | ||
| 184 | #define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8 | ||
| 185 | #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8) | ||
| 186 | #define OMAP3430_L1FLATMEMSTATEST_SHIFT 6 | ||
| 187 | #define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6) | ||
| 188 | #define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4 | ||
| 189 | #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4) | ||
| 190 | |||
| 191 | /* PM_PREPWSTST_IVA2 specific bits */ | ||
| 192 | #define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10 | ||
| 193 | #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10) | ||
| 194 | #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8 | ||
| 195 | #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8) | ||
| 196 | #define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6 | ||
| 197 | #define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6) | ||
| 198 | #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4 | ||
| 199 | #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4) | ||
| 200 | |||
| 201 | /* PRM_IRQSTATUS_IVA2 specific bits */ | ||
| 202 | #define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST (1 << 2) | ||
| 203 | #define OMAP3430_FORCEWKUP_ST (1 << 1) | ||
| 204 | |||
| 205 | /* PRM_IRQENABLE_IVA2 specific bits */ | ||
| 206 | #define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN (1 << 2) | ||
| 207 | #define OMAP3430_FORCEWKUP_EN (1 << 1) | ||
| 208 | |||
| 209 | /* PRM_REVISION specific bits */ | ||
| 210 | |||
| 211 | /* PRM_SYSCONFIG specific bits */ | ||
| 212 | |||
| 213 | /* PRM_IRQSTATUS_MPU specific bits */ | ||
| 214 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 | ||
| 215 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST (1 << 25) | ||
| 216 | #define OMAP3430_VC_TIMEOUTERR_ST (1 << 24) | ||
| 217 | #define OMAP3430_VC_RAERR_ST (1 << 23) | ||
| 218 | #define OMAP3430_VC_SAERR_ST (1 << 22) | ||
| 219 | #define OMAP3430_VP2_TRANXDONE_ST (1 << 21) | ||
| 220 | #define OMAP3430_VP2_EQVALUE_ST (1 << 20) | ||
| 221 | #define OMAP3430_VP2_NOSMPSACK_ST (1 << 19) | ||
| 222 | #define OMAP3430_VP2_MAXVDD_ST (1 << 18) | ||
| 223 | #define OMAP3430_VP2_MINVDD_ST (1 << 17) | ||
| 224 | #define OMAP3430_VP2_OPPCHANGEDONE_ST (1 << 16) | ||
| 225 | #define OMAP3430_VP1_TRANXDONE_ST (1 << 15) | ||
| 226 | #define OMAP3430_VP1_EQVALUE_ST (1 << 14) | ||
| 227 | #define OMAP3430_VP1_NOSMPSACK_ST (1 << 13) | ||
| 228 | #define OMAP3430_VP1_MAXVDD_ST (1 << 12) | ||
| 229 | #define OMAP3430_VP1_MINVDD_ST (1 << 11) | ||
| 230 | #define OMAP3430_VP1_OPPCHANGEDONE_ST (1 << 10) | ||
| 231 | #define OMAP3430_IO_ST (1 << 9) | ||
| 232 | #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST (1 << 8) | ||
| 233 | #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8 | ||
| 234 | #define OMAP3430_MPU_DPLL_ST (1 << 7) | ||
| 235 | #define OMAP3430_MPU_DPLL_ST_SHIFT 7 | ||
| 236 | #define OMAP3430_PERIPH_DPLL_ST (1 << 6) | ||
| 237 | #define OMAP3430_PERIPH_DPLL_ST_SHIFT 6 | ||
| 238 | #define OMAP3430_CORE_DPLL_ST (1 << 5) | ||
| 239 | #define OMAP3430_CORE_DPLL_ST_SHIFT 5 | ||
| 240 | #define OMAP3430_TRANSITION_ST (1 << 4) | ||
| 241 | #define OMAP3430_EVGENOFF_ST (1 << 3) | ||
| 242 | #define OMAP3430_EVGENON_ST (1 << 2) | ||
| 243 | #define OMAP3430_FS_USB_WKUP_ST (1 << 1) | ||
| 244 | |||
| 245 | /* PRM_IRQENABLE_MPU specific bits */ | ||
| 246 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 | ||
| 247 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN (1 << 25) | ||
| 248 | #define OMAP3430_VC_TIMEOUTERR_EN (1 << 24) | ||
| 249 | #define OMAP3430_VC_RAERR_EN (1 << 23) | ||
| 250 | #define OMAP3430_VC_SAERR_EN (1 << 22) | ||
| 251 | #define OMAP3430_VP2_TRANXDONE_EN (1 << 21) | ||
| 252 | #define OMAP3430_VP2_EQVALUE_EN (1 << 20) | ||
| 253 | #define OMAP3430_VP2_NOSMPSACK_EN (1 << 19) | ||
| 254 | #define OMAP3430_VP2_MAXVDD_EN (1 << 18) | ||
| 255 | #define OMAP3430_VP2_MINVDD_EN (1 << 17) | ||
| 256 | #define OMAP3430_VP2_OPPCHANGEDONE_EN (1 << 16) | ||
| 257 | #define OMAP3430_VP1_TRANXDONE_EN (1 << 15) | ||
| 258 | #define OMAP3430_VP1_EQVALUE_EN (1 << 14) | ||
| 259 | #define OMAP3430_VP1_NOSMPSACK_EN (1 << 13) | ||
| 260 | #define OMAP3430_VP1_MAXVDD_EN (1 << 12) | ||
| 261 | #define OMAP3430_VP1_MINVDD_EN (1 << 11) | ||
| 262 | #define OMAP3430_VP1_OPPCHANGEDONE_EN (1 << 10) | ||
| 263 | #define OMAP3430_IO_EN (1 << 9) | ||
| 264 | #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN (1 << 8) | ||
| 265 | #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8 | ||
| 266 | #define OMAP3430_MPU_DPLL_RECAL_EN (1 << 7) | ||
| 267 | #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7 | ||
| 268 | #define OMAP3430_PERIPH_DPLL_RECAL_EN (1 << 6) | ||
| 269 | #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6 | ||
| 270 | #define OMAP3430_CORE_DPLL_RECAL_EN (1 << 5) | ||
| 271 | #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5 | ||
| 272 | #define OMAP3430_TRANSITION_EN (1 << 4) | ||
| 273 | #define OMAP3430_EVGENOFF_EN (1 << 3) | ||
| 274 | #define OMAP3430_EVGENON_EN (1 << 2) | ||
| 275 | #define OMAP3430_FS_USB_WKUP_EN (1 << 1) | ||
| 276 | |||
| 277 | /* RM_RSTST_MPU specific bits */ | ||
| 278 | #define OMAP3430_EMULATION_MPU_RST (1 << 11) | ||
| 279 | |||
| 280 | /* PM_WKDEP_MPU specific bits */ | ||
| 281 | #define OMAP3430_PM_WKDEP_MPU_EN_DSS (1 << 5) | ||
| 282 | #define OMAP3430_PM_WKDEP_MPU_EN_IVA2 (1 << 2) | ||
| 283 | |||
| 284 | /* PM_EVGENCTRL_MPU */ | ||
| 285 | #define OMAP3430_OFFLOADMODE_SHIFT 3 | ||
| 286 | #define OMAP3430_OFFLOADMODE_MASK (0x3 << 3) | ||
| 287 | #define OMAP3430_ONLOADMODE_SHIFT 1 | ||
| 288 | #define OMAP3430_ONLOADMODE_MASK (0x3 << 1) | ||
| 289 | #define OMAP3430_ENABLE (1 << 0) | ||
| 290 | |||
| 291 | /* PM_EVGENONTIM_MPU */ | ||
| 292 | #define OMAP3430_ONTIMEVAL_SHIFT 0 | ||
| 293 | #define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0) | ||
| 294 | |||
| 295 | /* PM_EVGENOFFTIM_MPU */ | ||
| 296 | #define OMAP3430_OFFTIMEVAL_SHIFT 0 | ||
| 297 | #define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0) | ||
| 298 | |||
| 299 | /* PM_PWSTCTRL_MPU specific bits */ | ||
| 300 | #define OMAP3430_L2CACHEONSTATE_SHIFT 16 | ||
| 301 | #define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16) | ||
| 302 | #define OMAP3430_L2CACHERETSTATE (1 << 8) | ||
| 303 | #define OMAP3430_LOGICL1CACHERETSTATE (1 << 2) | ||
| 304 | |||
| 305 | /* PM_PWSTST_MPU specific bits */ | ||
| 306 | #define OMAP3430_L2CACHESTATEST_SHIFT 6 | ||
| 307 | #define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6) | ||
| 308 | #define OMAP3430_LOGICL1CACHESTATEST (1 << 2) | ||
| 309 | |||
| 310 | /* PM_PREPWSTST_MPU specific bits */ | ||
| 311 | #define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6 | ||
| 312 | #define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6) | ||
| 313 | #define OMAP3430_LASTLOGICL1CACHESTATEENTERED (1 << 2) | ||
| 314 | |||
| 315 | /* RM_RSTCTRL_CORE */ | ||
| 316 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON (1 << 1) | ||
| 317 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST (1 << 0) | ||
| 318 | |||
| 319 | /* RM_RSTST_CORE specific bits */ | ||
| 320 | #define OMAP3430_MODEM_SECURITY_VIOL_RST (1 << 10) | ||
| 321 | #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON (1 << 9) | ||
| 322 | #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST (1 << 8) | ||
| 323 | |||
| 324 | /* PM_WKEN1_CORE specific bits */ | ||
| 325 | |||
| 326 | /* PM_MPUGRPSEL1_CORE specific bits */ | ||
| 327 | #define OMAP3430_GRPSEL_FSHOSTUSB (1 << 5) | ||
| 328 | |||
| 329 | /* PM_IVA2GRPSEL1_CORE specific bits */ | ||
| 330 | |||
| 331 | /* PM_WKST1_CORE specific bits */ | ||
| 332 | |||
| 333 | /* PM_PWSTCTRL_CORE specific bits */ | ||
| 334 | #define OMAP3430_MEM2ONSTATE_SHIFT 18 | ||
| 335 | #define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18) | ||
| 336 | #define OMAP3430_MEM1ONSTATE_SHIFT 16 | ||
| 337 | #define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16) | ||
| 338 | #define OMAP3430_MEM2RETSTATE (1 << 9) | ||
| 339 | #define OMAP3430_MEM1RETSTATE (1 << 8) | ||
| 340 | |||
| 341 | /* PM_PWSTST_CORE specific bits */ | ||
| 342 | #define OMAP3430_MEM2STATEST_SHIFT 6 | ||
| 343 | #define OMAP3430_MEM2STATEST_MASK (0x3 << 6) | ||
| 344 | #define OMAP3430_MEM1STATEST_SHIFT 4 | ||
| 345 | #define OMAP3430_MEM1STATEST_MASK (0x3 << 4) | ||
| 346 | |||
| 347 | /* PM_PREPWSTST_CORE specific bits */ | ||
| 348 | #define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6 | ||
| 349 | #define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6) | ||
| 350 | #define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4 | ||
| 351 | #define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4) | ||
| 352 | |||
| 353 | /* RM_RSTST_GFX specific bits */ | ||
| 354 | |||
| 355 | /* PM_WKDEP_GFX specific bits */ | ||
| 356 | #define OMAP3430_PM_WKDEP_GFX_EN_IVA2 (1 << 2) | ||
| 357 | |||
| 358 | /* PM_PWSTCTRL_GFX specific bits */ | ||
| 359 | |||
| 360 | /* PM_PWSTST_GFX specific bits */ | ||
| 361 | |||
| 362 | /* PM_PREPWSTST_GFX specific bits */ | ||
| 363 | |||
| 364 | /* PM_WKEN_WKUP specific bits */ | ||
| 365 | #define OMAP3430_EN_IO (1 << 8) | ||
| 366 | |||
| 367 | /* PM_MPUGRPSEL_WKUP specific bits */ | ||
| 368 | |||
| 369 | /* PM_IVA2GRPSEL_WKUP specific bits */ | ||
| 370 | |||
| 371 | /* PM_WKST_WKUP specific bits */ | ||
| 372 | #define OMAP3430_ST_IO (1 << 8) | ||
| 373 | |||
| 374 | /* PRM_CLKSEL */ | ||
| 375 | #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 | ||
| 376 | #define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0) | ||
| 377 | |||
| 378 | /* PRM_CLKOUT_CTRL */ | ||
| 379 | #define OMAP3430_CLKOUT_EN (1 << 7) | ||
| 380 | #define OMAP3430_CLKOUT_EN_SHIFT 7 | ||
| 381 | |||
| 382 | /* RM_RSTST_DSS specific bits */ | ||
| 383 | |||
| 384 | /* PM_WKEN_DSS */ | ||
| 385 | #define OMAP3430_PM_WKEN_DSS_EN_DSS (1 << 0) | ||
| 386 | |||
| 387 | /* PM_WKDEP_DSS specific bits */ | ||
| 388 | #define OMAP3430_PM_WKDEP_DSS_EN_IVA2 (1 << 2) | ||
| 389 | |||
| 390 | /* PM_PWSTCTRL_DSS specific bits */ | ||
| 391 | |||
| 392 | /* PM_PWSTST_DSS specific bits */ | ||
| 393 | |||
| 394 | /* PM_PREPWSTST_DSS specific bits */ | ||
| 395 | |||
| 396 | /* RM_RSTST_CAM specific bits */ | ||
| 397 | |||
| 398 | /* PM_WKDEP_CAM specific bits */ | ||
| 399 | #define OMAP3430_PM_WKDEP_CAM_EN_IVA2 (1 << 2) | ||
| 400 | |||
| 401 | /* PM_PWSTCTRL_CAM specific bits */ | ||
| 402 | |||
| 403 | /* PM_PWSTST_CAM specific bits */ | ||
| 404 | |||
| 405 | /* PM_PREPWSTST_CAM specific bits */ | ||
| 406 | |||
| 407 | /* PM_PWSTCTRL_USBHOST specific bits */ | ||
| 408 | #define OMAP3430ES2_SAVEANDRESTORE_SHIFT (1 << 4) | ||
| 409 | |||
| 410 | /* RM_RSTST_PER specific bits */ | ||
| 411 | |||
| 412 | /* PM_WKEN_PER specific bits */ | ||
| 413 | |||
| 414 | /* PM_MPUGRPSEL_PER specific bits */ | ||
| 415 | |||
| 416 | /* PM_IVA2GRPSEL_PER specific bits */ | ||
| 417 | |||
| 418 | /* PM_WKST_PER specific bits */ | ||
| 419 | |||
| 420 | /* PM_WKDEP_PER specific bits */ | ||
| 421 | #define OMAP3430_PM_WKDEP_PER_EN_IVA2 (1 << 2) | ||
| 422 | |||
| 423 | /* PM_PWSTCTRL_PER specific bits */ | ||
| 424 | |||
| 425 | /* PM_PWSTST_PER specific bits */ | ||
| 426 | |||
| 427 | /* PM_PREPWSTST_PER specific bits */ | ||
| 428 | |||
| 429 | /* RM_RSTST_EMU specific bits */ | ||
| 430 | |||
| 431 | /* PM_PWSTST_EMU specific bits */ | ||
| 432 | |||
| 433 | /* PRM_VC_SMPS_SA */ | ||
| 434 | #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16 | ||
| 435 | #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) | ||
| 436 | #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0 | ||
| 437 | #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) | ||
| 438 | |||
| 439 | /* PRM_VC_SMPS_VOL_RA */ | ||
| 440 | #define OMAP3430_VOLRA1_SHIFT 16 | ||
| 441 | #define OMAP3430_VOLRA1_MASK (0xff << 16) | ||
| 442 | #define OMAP3430_VOLRA0_SHIFT 0 | ||
| 443 | #define OMAP3430_VOLRA0_MASK (0xff << 0) | ||
| 444 | |||
| 445 | /* PRM_VC_SMPS_CMD_RA */ | ||
| 446 | #define OMAP3430_CMDRA1_SHIFT 16 | ||
| 447 | #define OMAP3430_CMDRA1_MASK (0xff << 16) | ||
| 448 | #define OMAP3430_CMDRA0_SHIFT 0 | ||
| 449 | #define OMAP3430_CMDRA0_MASK (0xff << 0) | ||
| 450 | |||
| 451 | /* PRM_VC_CMD_VAL_0 specific bits */ | ||
| 452 | |||
| 453 | /* PRM_VC_CMD_VAL_1 specific bits */ | ||
| 454 | |||
| 455 | /* PRM_VC_CH_CONF */ | ||
| 456 | #define OMAP3430_CMD1 (1 << 20) | ||
| 457 | #define OMAP3430_RACEN1 (1 << 19) | ||
| 458 | #define OMAP3430_RAC1 (1 << 18) | ||
| 459 | #define OMAP3430_RAV1 (1 << 17) | ||
| 460 | #define OMAP3430_PRM_VC_CH_CONF_SA1 (1 << 16) | ||
| 461 | #define OMAP3430_CMD0 (1 << 4) | ||
| 462 | #define OMAP3430_RACEN0 (1 << 3) | ||
| 463 | #define OMAP3430_RAC0 (1 << 2) | ||
| 464 | #define OMAP3430_RAV0 (1 << 1) | ||
| 465 | #define OMAP3430_PRM_VC_CH_CONF_SA0 (1 << 0) | ||
| 466 | |||
| 467 | /* PRM_VC_I2C_CFG */ | ||
| 468 | #define OMAP3430_HSMASTER (1 << 5) | ||
| 469 | #define OMAP3430_SREN (1 << 4) | ||
| 470 | #define OMAP3430_HSEN (1 << 3) | ||
| 471 | #define OMAP3430_MCODE_SHIFT 0 | ||
| 472 | #define OMAP3430_MCODE_MASK (0x7 << 0) | ||
| 473 | |||
| 474 | /* PRM_VC_BYPASS_VAL */ | ||
| 475 | #define OMAP3430_VALID (1 << 24) | ||
| 476 | #define OMAP3430_DATA_SHIFT 16 | ||
| 477 | #define OMAP3430_DATA_MASK (0xff << 16) | ||
| 478 | #define OMAP3430_REGADDR_SHIFT 8 | ||
| 479 | #define OMAP3430_REGADDR_MASK (0xff << 8) | ||
| 480 | #define OMAP3430_SLAVEADDR_SHIFT 0 | ||
| 481 | #define OMAP3430_SLAVEADDR_MASK (0x7f << 0) | ||
| 482 | |||
| 483 | /* PRM_RSTCTRL */ | ||
| 484 | #define OMAP3430_RST_DPLL3 (1 << 2) | ||
| 485 | #define OMAP3430_RST_GS (1 << 1) | ||
| 486 | |||
| 487 | /* PRM_RSTTIME */ | ||
| 488 | #define OMAP3430_RSTTIME2_SHIFT 8 | ||
| 489 | #define OMAP3430_RSTTIME2_MASK (0x1f << 8) | ||
| 490 | #define OMAP3430_RSTTIME1_SHIFT 0 | ||
| 491 | #define OMAP3430_RSTTIME1_MASK (0xff << 0) | ||
| 492 | |||
| 493 | /* PRM_RSTST */ | ||
| 494 | #define OMAP3430_ICECRUSHER_RST (1 << 10) | ||
| 495 | #define OMAP3430_ICEPICK_RST (1 << 9) | ||
| 496 | #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST (1 << 8) | ||
| 497 | #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST (1 << 7) | ||
| 498 | #define OMAP3430_EXTERNAL_WARM_RST (1 << 6) | ||
| 499 | #define OMAP3430_SECURE_WD_RST (1 << 5) | ||
| 500 | #define OMAP3430_MPU_WD_RST (1 << 4) | ||
| 501 | #define OMAP3430_SECURITY_VIOL_RST (1 << 3) | ||
| 502 | #define OMAP3430_GLOBAL_SW_RST (1 << 1) | ||
| 503 | #define OMAP3430_GLOBAL_COLD_RST (1 << 0) | ||
| 504 | |||
| 505 | /* PRM_VOLTCTRL */ | ||
| 506 | #define OMAP3430_SEL_VMODE (1 << 4) | ||
| 507 | #define OMAP3430_SEL_OFF (1 << 3) | ||
| 508 | #define OMAP3430_AUTO_OFF (1 << 2) | ||
| 509 | #define OMAP3430_AUTO_RET (1 << 1) | ||
| 510 | #define OMAP3430_AUTO_SLEEP (1 << 0) | ||
| 511 | |||
| 512 | /* PRM_SRAM_PCHARGE */ | ||
| 513 | #define OMAP3430_PCHARGE_TIME_SHIFT 0 | ||
| 514 | #define OMAP3430_PCHARGE_TIME_MASK (0xff << 0) | ||
| 515 | |||
| 516 | /* PRM_CLKSRC_CTRL */ | ||
| 517 | #define OMAP3430_SYSCLKDIV_SHIFT 6 | ||
| 518 | #define OMAP3430_SYSCLKDIV_MASK (0x3 << 6) | ||
| 519 | #define OMAP3430_AUTOEXTCLKMODE_SHIFT 3 | ||
| 520 | #define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3) | ||
| 521 | #define OMAP3430_SYSCLKSEL_SHIFT 0 | ||
| 522 | #define OMAP3430_SYSCLKSEL_MASK (0x3 << 0) | ||
| 523 | |||
| 524 | /* PRM_VOLTSETUP1 */ | ||
| 525 | #define OMAP3430_SETUP_TIME2_SHIFT 16 | ||
| 526 | #define OMAP3430_SETUP_TIME2_MASK (0xffff << 16) | ||
| 527 | #define OMAP3430_SETUP_TIME1_SHIFT 0 | ||
| 528 | #define OMAP3430_SETUP_TIME1_MASK (0xffff << 0) | ||
| 529 | |||
| 530 | /* PRM_VOLTOFFSET */ | ||
| 531 | #define OMAP3430_OFFSET_TIME_SHIFT 0 | ||
| 532 | #define OMAP3430_OFFSET_TIME_MASK (0xffff << 0) | ||
| 533 | |||
| 534 | /* PRM_CLKSETUP */ | ||
| 535 | #define OMAP3430_SETUP_TIME_SHIFT 0 | ||
| 536 | #define OMAP3430_SETUP_TIME_MASK (0xffff << 0) | ||
| 537 | |||
| 538 | /* PRM_POLCTRL */ | ||
| 539 | #define OMAP3430_OFFMODE_POL (1 << 3) | ||
| 540 | #define OMAP3430_CLKOUT_POL (1 << 2) | ||
| 541 | #define OMAP3430_CLKREQ_POL (1 << 1) | ||
| 542 | #define OMAP3430_EXTVOL_POL (1 << 0) | ||
| 543 | |||
| 544 | /* PRM_VOLTSETUP2 */ | ||
| 545 | #define OMAP3430_OFFMODESETUPTIME_SHIFT 0 | ||
| 546 | #define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0) | ||
| 547 | |||
| 548 | /* PRM_VP1_CONFIG specific bits */ | ||
| 549 | |||
| 550 | /* PRM_VP1_VSTEPMIN specific bits */ | ||
| 551 | |||
| 552 | /* PRM_VP1_VSTEPMAX specific bits */ | ||
| 553 | |||
| 554 | /* PRM_VP1_VLIMITTO specific bits */ | ||
| 555 | |||
| 556 | /* PRM_VP1_VOLTAGE specific bits */ | ||
| 557 | |||
| 558 | /* PRM_VP1_STATUS specific bits */ | ||
| 559 | |||
| 560 | /* PRM_VP2_CONFIG specific bits */ | ||
| 561 | |||
| 562 | /* PRM_VP2_VSTEPMIN specific bits */ | ||
| 563 | |||
| 564 | /* PRM_VP2_VSTEPMAX specific bits */ | ||
| 565 | |||
| 566 | /* PRM_VP2_VLIMITTO specific bits */ | ||
| 567 | |||
| 568 | /* PRM_VP2_VOLTAGE specific bits */ | ||
| 569 | |||
| 570 | /* PRM_VP2_STATUS specific bits */ | ||
| 571 | |||
| 572 | /* RM_RSTST_NEON specific bits */ | ||
| 573 | |||
| 574 | /* PM_WKDEP_NEON specific bits */ | ||
| 575 | |||
| 576 | /* PM_PWSTCTRL_NEON specific bits */ | ||
| 577 | |||
| 578 | /* PM_PWSTST_NEON specific bits */ | ||
| 579 | |||
| 580 | /* PM_PREPWSTST_NEON specific bits */ | ||
| 581 | |||
| 582 | #endif | ||
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h new file mode 100644 index 000000000000..ab7649afd891 --- /dev/null +++ b/arch/arm/mach-omap2/prm.h | |||
| @@ -0,0 +1,316 @@ | |||
| 1 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H | ||
| 2 | #define __ARCH_ARM_MACH_OMAP2_PRM_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * OMAP2/3 Power/Reset Management (PRM) register definitions | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 8 | * Copyright (C) 2007 Nokia Corporation | ||
| 9 | * | ||
| 10 | * Written by Paul Walmsley | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include "prcm-common.h" | ||
| 18 | |||
| 19 | #ifndef __ASSEMBLER__ | ||
| 20 | #define OMAP_PRM_REGADDR(module, reg) \ | ||
| 21 | (void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg)) | ||
| 22 | #else | ||
| 23 | #define OMAP2420_PRM_REGADDR(module, reg) \ | ||
| 24 | IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) | ||
| 25 | #define OMAP2430_PRM_REGADDR(module, reg) \ | ||
| 26 | IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) | ||
| 27 | #define OMAP34XX_PRM_REGADDR(module, reg) \ | ||
| 28 | IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) | ||
| 29 | #endif | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Architecture-specific global PRM registers | ||
| 33 | * Use prm_{read,write}_reg() with these registers. | ||
| 34 | * | ||
| 35 | * With a few exceptions, these are the register names beginning with | ||
| 36 | * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the | ||
| 37 | * IRQSTATUS and IRQENABLE bits.) | ||
| 38 | * | ||
| 39 | */ | ||
| 40 | |||
| 41 | #define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000) | ||
| 42 | #define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010) | ||
| 43 | |||
| 44 | #define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) | ||
| 45 | #define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) | ||
| 46 | |||
| 47 | #define OMAP24XX_PRCM_VOLTCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0050) | ||
| 48 | #define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054) | ||
| 49 | #define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060) | ||
| 50 | #define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070) | ||
| 51 | #define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0078) | ||
| 52 | #define OMAP24XX_PRCM_CLKCFG_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0080) | ||
| 53 | #define OMAP24XX_PRCM_CLKCFG_STATUS OMAP_PRM_REGADDR(OCP_MOD, 0x0084) | ||
| 54 | #define OMAP24XX_PRCM_VOLTSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0090) | ||
| 55 | #define OMAP24XX_PRCM_CLKSSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0094) | ||
| 56 | #define OMAP24XX_PRCM_POLCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0098) | ||
| 57 | |||
| 58 | #define OMAP3430_PRM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0004) | ||
| 59 | #define OMAP3430_PRM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0014) | ||
| 60 | |||
| 61 | #define OMAP3430_PRM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) | ||
| 62 | #define OMAP3430_PRM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) | ||
| 63 | |||
| 64 | |||
| 65 | #define OMAP3430_PRM_VC_SMPS_SA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) | ||
| 66 | #define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) | ||
| 67 | #define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) | ||
| 68 | #define OMAP3430_PRM_VC_CMD_VAL_0 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) | ||
| 69 | #define OMAP3430_PRM_VC_CMD_VAL_1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) | ||
| 70 | #define OMAP3430_PRM_VC_CH_CONF OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) | ||
| 71 | #define OMAP3430_PRM_VC_I2C_CFG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) | ||
| 72 | #define OMAP3430_PRM_VC_BYPASS_VAL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) | ||
| 73 | #define OMAP3430_PRM_RSTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) | ||
| 74 | #define OMAP3430_PRM_RSTTIME OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) | ||
| 75 | #define OMAP3430_PRM_RSTST OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) | ||
| 76 | #define OMAP3430_PRM_VOLTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) | ||
| 77 | #define OMAP3430_PRM_SRAM_PCHARGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) | ||
| 78 | #define OMAP3430_PRM_CLKSRC_CTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) | ||
| 79 | #define OMAP3430_PRM_VOLTSETUP1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) | ||
| 80 | #define OMAP3430_PRM_VOLTOFFSET OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) | ||
| 81 | #define OMAP3430_PRM_CLKSETUP OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) | ||
| 82 | #define OMAP3430_PRM_POLCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) | ||
| 83 | #define OMAP3430_PRM_VOLTSETUP2 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) | ||
| 84 | #define OMAP3430_PRM_VP1_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) | ||
| 85 | #define OMAP3430_PRM_VP1_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) | ||
| 86 | #define OMAP3430_PRM_VP1_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) | ||
| 87 | #define OMAP3430_PRM_VP1_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) | ||
| 88 | #define OMAP3430_PRM_VP1_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) | ||
| 89 | #define OMAP3430_PRM_VP1_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) | ||
| 90 | #define OMAP3430_PRM_VP2_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) | ||
| 91 | #define OMAP3430_PRM_VP2_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) | ||
| 92 | #define OMAP3430_PRM_VP2_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) | ||
| 93 | #define OMAP3430_PRM_VP2_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) | ||
| 94 | #define OMAP3430_PRM_VP2_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) | ||
| 95 | #define OMAP3430_PRM_VP2_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) | ||
| 96 | |||
| 97 | #define OMAP3430_PRM_CLKSEL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) | ||
| 98 | #define OMAP3430_PRM_CLKOUT_CTRL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) | ||
| 99 | |||
| 100 | /* | ||
| 101 | * Module specific PRM registers from PRM_BASE + domain offset | ||
| 102 | * | ||
| 103 | * Use prm_{read,write}_mod_reg() with these registers. | ||
| 104 | * | ||
| 105 | * With a few exceptions, these are the register names beginning with | ||
| 106 | * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS | ||
| 107 | * and IRQENABLE bits.) | ||
| 108 | * | ||
| 109 | */ | ||
| 110 | |||
| 111 | /* Registers appearing on both 24xx and 34xx */ | ||
| 112 | |||
| 113 | #define RM_RSTCTRL 0x0050 | ||
| 114 | #define RM_RSTTIME 0x0054 | ||
| 115 | #define RM_RSTST 0x0058 | ||
| 116 | |||
| 117 | #define PM_WKEN 0x00a0 | ||
| 118 | #define PM_WKEN1 PM_WKEN | ||
| 119 | #define PM_WKST 0x00b0 | ||
| 120 | #define PM_WKST1 PM_WKST | ||
| 121 | #define PM_WKDEP 0x00c8 | ||
| 122 | #define PM_EVGENCTRL 0x00d4 | ||
| 123 | #define PM_EVGENONTIM 0x00d8 | ||
| 124 | #define PM_EVGENOFFTIM 0x00dc | ||
| 125 | #define PM_PWSTCTRL 0x00e0 | ||
| 126 | #define PM_PWSTST 0x00e4 | ||
| 127 | |||
| 128 | #define OMAP3430_PM_MPUGRPSEL 0x00a4 | ||
| 129 | #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL | ||
| 130 | |||
| 131 | #define OMAP3430_PM_IVAGRPSEL 0x00a8 | ||
| 132 | #define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL | ||
| 133 | |||
| 134 | #define OMAP3430_PM_PREPWSTST 0x00e8 | ||
| 135 | |||
| 136 | #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 | ||
| 137 | #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc | ||
| 138 | |||
| 139 | |||
| 140 | /* Architecture-specific registers */ | ||
| 141 | |||
| 142 | #define OMAP24XX_PM_WKEN2 0x00a4 | ||
| 143 | #define OMAP24XX_PM_WKST2 0x00b4 | ||
| 144 | |||
| 145 | #define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ | ||
| 146 | #define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ | ||
| 147 | #define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 | ||
| 148 | #define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc | ||
| 149 | |||
| 150 | #ifndef __ASSEMBLER__ | ||
| 151 | |||
| 152 | /* Power/reset management domain register get/set */ | ||
| 153 | |||
| 154 | static inline void prm_write_mod_reg(u32 val, s16 module, s16 idx) | ||
| 155 | { | ||
| 156 | __raw_writel(val, OMAP_PRM_REGADDR(module, idx)); | ||
| 157 | } | ||
| 158 | |||
| 159 | static inline u32 prm_read_mod_reg(s16 module, s16 idx) | ||
| 160 | { | ||
| 161 | return __raw_readl(OMAP_PRM_REGADDR(module, idx)); | ||
| 162 | } | ||
| 163 | |||
| 164 | #endif | ||
| 165 | |||
| 166 | /* | ||
| 167 | * Bits common to specific registers | ||
| 168 | * | ||
| 169 | * The 3430 register and bit names are generally used, | ||
| 170 | * since they tend to make more sense | ||
| 171 | */ | ||
| 172 | |||
| 173 | /* PM_EVGENONTIM_MPU */ | ||
| 174 | /* Named PM_EVEGENONTIM_MPU on the 24XX */ | ||
| 175 | #define OMAP_ONTIMEVAL_SHIFT 0 | ||
| 176 | #define OMAP_ONTIMEVAL_MASK (0xffffffff << 0) | ||
| 177 | |||
| 178 | /* PM_EVGENOFFTIM_MPU */ | ||
| 179 | /* Named PM_EVEGENOFFTIM_MPU on the 24XX */ | ||
| 180 | #define OMAP_OFFTIMEVAL_SHIFT 0 | ||
| 181 | #define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0) | ||
| 182 | |||
| 183 | /* PRM_CLKSETUP and PRCM_VOLTSETUP */ | ||
| 184 | /* Named PRCM_CLKSSETUP on the 24XX */ | ||
| 185 | #define OMAP_SETUP_TIME_SHIFT 0 | ||
| 186 | #define OMAP_SETUP_TIME_MASK (0xffff << 0) | ||
| 187 | |||
| 188 | /* PRM_CLKSRC_CTRL */ | ||
| 189 | /* Named PRCM_CLKSRC_CTRL on the 24XX */ | ||
| 190 | #define OMAP_SYSCLKDIV_SHIFT 6 | ||
| 191 | #define OMAP_SYSCLKDIV_MASK (0x3 << 6) | ||
| 192 | #define OMAP_AUTOEXTCLKMODE_SHIFT 3 | ||
| 193 | #define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3) | ||
| 194 | #define OMAP_SYSCLKSEL_SHIFT 0 | ||
| 195 | #define OMAP_SYSCLKSEL_MASK (0x3 << 0) | ||
| 196 | |||
| 197 | /* PM_EVGENCTRL_MPU */ | ||
| 198 | #define OMAP_OFFLOADMODE_SHIFT 3 | ||
| 199 | #define OMAP_OFFLOADMODE_MASK (0x3 << 3) | ||
| 200 | #define OMAP_ONLOADMODE_SHIFT 1 | ||
| 201 | #define OMAP_ONLOADMODE_MASK (0x3 << 1) | ||
| 202 | #define OMAP_ENABLE (1 << 0) | ||
| 203 | |||
| 204 | /* PRM_RSTTIME */ | ||
| 205 | /* Named RM_RSTTIME_WKUP on the 24xx */ | ||
| 206 | #define OMAP_RSTTIME2_SHIFT 8 | ||
| 207 | #define OMAP_RSTTIME2_MASK (0x1f << 8) | ||
| 208 | #define OMAP_RSTTIME1_SHIFT 0 | ||
| 209 | #define OMAP_RSTTIME1_MASK (0xff << 0) | ||
| 210 | |||
| 211 | |||
| 212 | /* PRM_RSTCTRL */ | ||
| 213 | /* Named RM_RSTCTRL_WKUP on the 24xx */ | ||
| 214 | /* 2420 calls RST_DPLL3 'RST_DPLL' */ | ||
| 215 | #define OMAP_RST_DPLL3 (1 << 2) | ||
| 216 | #define OMAP_RST_GS (1 << 1) | ||
| 217 | |||
| 218 | |||
| 219 | /* | ||
| 220 | * Bits common to module-shared registers | ||
| 221 | * | ||
| 222 | * Not all registers of a particular type support all of these bits - | ||
| 223 | * check TRM if you are unsure | ||
| 224 | */ | ||
| 225 | |||
| 226 | /* | ||
| 227 | * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP | ||
| 228 | * | ||
| 229 | * 2430: PM_PWSTST_MDM | ||
| 230 | * | ||
| 231 | * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, | ||
| 232 | * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, | ||
| 233 | * PM_PWSTST_NEON | ||
| 234 | */ | ||
| 235 | #define OMAP_INTRANSITION (1 << 20) | ||
| 236 | |||
| 237 | |||
| 238 | /* | ||
| 239 | * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP | ||
| 240 | * | ||
| 241 | * 2430: PM_PWSTST_MDM | ||
| 242 | * | ||
| 243 | * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, | ||
| 244 | * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, | ||
| 245 | * PM_PWSTST_NEON | ||
| 246 | */ | ||
| 247 | #define OMAP_POWERSTATEST_SHIFT 0 | ||
| 248 | #define OMAP_POWERSTATEST_MASK (0x3 << 0) | ||
| 249 | |||
| 250 | /* | ||
| 251 | * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is | ||
| 252 | * called 'COREWKUP_RST' | ||
| 253 | * | ||
| 254 | * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS, | ||
| 255 | * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON | ||
| 256 | */ | ||
| 257 | #define OMAP_COREDOMAINWKUP_RST (1 << 3) | ||
| 258 | |||
| 259 | /* | ||
| 260 | * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP | ||
| 261 | * | ||
| 262 | * 2430: RM_RSTST_MDM | ||
| 263 | * | ||
| 264 | * 3430: RM_RSTST_CORE, RM_RSTST_EMU | ||
| 265 | */ | ||
| 266 | #define OMAP_DOMAINWKUP_RST (1 << 2) | ||
| 267 | |||
| 268 | /* | ||
| 269 | * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP | ||
| 270 | * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'. | ||
| 271 | * | ||
| 272 | * 2430: RM_RSTST_MDM | ||
| 273 | * | ||
| 274 | * 3430: RM_RSTST_CORE, RM_RSTST_EMU | ||
| 275 | */ | ||
| 276 | #define OMAP_GLOBALWARM_RST (1 << 1) | ||
| 277 | #define OMAP_GLOBALCOLD_RST (1 << 0) | ||
| 278 | |||
| 279 | /* | ||
| 280 | * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP | ||
| 281 | * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP" | ||
| 282 | * | ||
| 283 | * 2430: PM_WKDEP_MDM | ||
| 284 | * | ||
| 285 | * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, | ||
| 286 | * PM_WKDEP_PER | ||
| 287 | */ | ||
| 288 | #define OMAP_EN_WKUP (1 << 4) | ||
| 289 | |||
| 290 | /* | ||
| 291 | * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, | ||
| 292 | * PM_PWSTCTRL_DSP | ||
| 293 | * | ||
| 294 | * 2430: PM_PWSTCTRL_MDM | ||
| 295 | * | ||
| 296 | * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, | ||
| 297 | * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, | ||
| 298 | * PM_PWSTCTRL_NEON | ||
| 299 | */ | ||
| 300 | #define OMAP_LOGICRETSTATE (1 << 2) | ||
| 301 | |||
| 302 | /* | ||
| 303 | * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, | ||
| 304 | * PM_PWSTCTRL_DSP, PM_PWSTST_MPU | ||
| 305 | * | ||
| 306 | * 2430: PM_PWSTCTRL_MDM shared bits | ||
| 307 | * | ||
| 308 | * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, | ||
| 309 | * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, | ||
| 310 | * PM_PWSTCTRL_NEON shared bits | ||
| 311 | */ | ||
| 312 | #define OMAP_POWERSTATE_SHIFT 0 | ||
| 313 | #define OMAP_POWERSTATE_MASK (0x3 << 0) | ||
| 314 | |||
| 315 | |||
| 316 | #endif | ||
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h new file mode 100644 index 000000000000..d7f23bc9550a --- /dev/null +++ b/arch/arm/mach-omap2/sdrc.h | |||
| @@ -0,0 +1,58 @@ | |||
| 1 | #ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H | ||
| 2 | #define __ARCH_ARM_MACH_OMAP2_SDRC_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * OMAP2 SDRC register definitions | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 8 | * Copyright (C) 2007 Nokia Corporation | ||
| 9 | * | ||
| 10 | * Written by Paul Walmsley | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | #undef DEBUG | ||
| 17 | |||
| 18 | #include <asm/arch/sdrc.h> | ||
| 19 | |||
| 20 | #ifndef __ASSEMBLER__ | ||
| 21 | extern unsigned long omap2_sdrc_base; | ||
| 22 | extern unsigned long omap2_sms_base; | ||
| 23 | |||
| 24 | #define OMAP_SDRC_REGADDR(reg) \ | ||
| 25 | (void __iomem *)IO_ADDRESS(omap2_sdrc_base + (reg)) | ||
| 26 | #define OMAP_SMS_REGADDR(reg) \ | ||
| 27 | (void __iomem *)IO_ADDRESS(omap2_sms_base + (reg)) | ||
| 28 | |||
| 29 | /* SDRC global register get/set */ | ||
| 30 | |||
| 31 | static inline void sdrc_write_reg(u32 val, u16 reg) | ||
| 32 | { | ||
| 33 | __raw_writel(val, OMAP_SDRC_REGADDR(reg)); | ||
| 34 | } | ||
| 35 | |||
| 36 | static inline u32 sdrc_read_reg(u16 reg) | ||
| 37 | { | ||
| 38 | return __raw_readl(OMAP_SDRC_REGADDR(reg)); | ||
| 39 | } | ||
| 40 | |||
| 41 | /* SMS global register get/set */ | ||
| 42 | |||
| 43 | static inline void sms_write_reg(u32 val, u16 reg) | ||
| 44 | { | ||
| 45 | __raw_writel(val, OMAP_SMS_REGADDR(reg)); | ||
| 46 | } | ||
| 47 | |||
| 48 | static inline u32 sms_read_reg(u16 reg) | ||
| 49 | { | ||
| 50 | return __raw_readl(OMAP_SMS_REGADDR(reg)); | ||
| 51 | } | ||
| 52 | #else | ||
| 53 | #define OMAP242X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP2420_SDRC_BASE + (reg)) | ||
| 54 | #define OMAP243X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP243X_SDRC_BASE + (reg)) | ||
| 55 | #define OMAP34XX_SDRC_REGADDR(reg) IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) | ||
| 56 | #endif /* __ASSEMBLER__ */ | ||
| 57 | |||
| 58 | #endif | ||
diff --git a/arch/arm/mach-omap2/sleep.S b/arch/arm/mach-omap2/sleep.S index 16247d557853..46ccb9b8b583 100644 --- a/arch/arm/mach-omap2/sleep.S +++ b/arch/arm/mach-omap2/sleep.S | |||
| @@ -26,19 +26,10 @@ | |||
| 26 | #include <asm/arch/io.h> | 26 | #include <asm/arch/io.h> |
| 27 | #include <asm/arch/pm.h> | 27 | #include <asm/arch/pm.h> |
| 28 | 28 | ||
| 29 | #define A_32KSYNC_CR_V IO_ADDRESS(OMAP_TIMER32K_BASE+0x10) | 29 | #include "sdrc.h" |
| 30 | #define A_PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x50) | ||
| 31 | #define A_PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x80) | ||
| 32 | #define A_CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x500) | ||
| 33 | #define A_CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x520) | ||
| 34 | #define A_CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x540) | ||
| 35 | #define A_CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x544) | ||
| 36 | 30 | ||
| 37 | #define A_SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0x60) | 31 | /* First address of reserved address space? apparently valid for OMAP2 & 3 */ |
| 38 | #define A_SDRC_POWER_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0x70) | ||
| 39 | #define A_SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA4) | ||
| 40 | #define A_SDRC0_V (0xC0000000) | 32 | #define A_SDRC0_V (0xC0000000) |
| 41 | #define A_SDRC_MANUAL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA8) | ||
| 42 | 33 | ||
| 43 | .text | 34 | .text |
| 44 | 35 | ||
| @@ -126,17 +117,11 @@ loop2: | |||
| 126 | ldmfd sp!, {r0 - r12, pc} @ restore regs and return | 117 | ldmfd sp!, {r0 - r12, pc} @ restore regs and return |
| 127 | 118 | ||
| 128 | A_SDRC_POWER: | 119 | A_SDRC_POWER: |
| 129 | .word A_SDRC_POWER_V | 120 | .word OMAP242X_SDRC_REGADDR(SDRC_POWER) |
| 130 | A_SDRC0: | 121 | A_SDRC0: |
| 131 | .word A_SDRC0_V | 122 | .word A_SDRC0_V |
| 132 | A_CM_CLKSEL2_PLL_S: | ||
| 133 | .word A_CM_CLKSEL2_PLL_V | ||
| 134 | A_CM_CLKEN_PLL: | ||
| 135 | .word A_CM_CLKEN_PLL_V | ||
| 136 | A_SDRC_DLLA_CTRL_S: | 123 | A_SDRC_DLLA_CTRL_S: |
| 137 | .word A_SDRC_DLLA_CTRL_V | 124 | .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) |
| 138 | A_SDRC_MANUAL_S: | ||
| 139 | .word A_SDRC_MANUAL_V | ||
| 140 | 125 | ||
| 141 | ENTRY(omap24xx_cpu_suspend_sz) | 126 | ENTRY(omap24xx_cpu_suspend_sz) |
| 142 | .word . - omap24xx_cpu_suspend | 127 | .word . - omap24xx_cpu_suspend |
diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram-fn.S index b27576690f8d..4a9e49140716 100644 --- a/arch/arm/mach-omap2/sram-fn.S +++ b/arch/arm/mach-omap2/sram-fn.S | |||
| @@ -27,19 +27,11 @@ | |||
| 27 | #include <asm/arch/io.h> | 27 | #include <asm/arch/io.h> |
| 28 | #include <asm/hardware.h> | 28 | #include <asm/hardware.h> |
| 29 | 29 | ||
| 30 | #include "prcm-regs.h" | 30 | #include "sdrc.h" |
| 31 | #include "prm.h" | ||
| 32 | #include "cm.h" | ||
| 31 | 33 | ||
| 32 | #define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010) | 34 | #define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) |
| 33 | |||
| 34 | #define CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x544) | ||
| 35 | #define PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x050) | ||
| 36 | #define PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x080) | ||
| 37 | #define CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x500) | ||
| 38 | #define CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x520) | ||
| 39 | #define CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x540) | ||
| 40 | |||
| 41 | #define SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x060) | ||
| 42 | #define SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x0a4) | ||
| 43 | 35 | ||
| 44 | .text | 36 | .text |
| 45 | 37 | ||
| @@ -131,11 +123,11 @@ volt_delay: | |||
| 131 | 123 | ||
| 132 | /* relative load constants */ | 124 | /* relative load constants */ |
| 133 | cm_clksel2_pll: | 125 | cm_clksel2_pll: |
| 134 | .word CM_CLKSEL2_PLL_V | 126 | .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2) |
| 135 | sdrc_dlla_ctrl: | 127 | sdrc_dlla_ctrl: |
| 136 | .word SDRC_DLLA_CTRL_V | 128 | .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) |
| 137 | prcm_voltctrl: | 129 | prcm_voltctrl: |
| 138 | .word PRCM_VOLTCTRL_V | 130 | .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50) |
| 139 | prcm_mask_val: | 131 | prcm_mask_val: |
| 140 | .word 0xFFFF3FFC | 132 | .word 0xFFFF3FFC |
| 141 | timer_32ksynct_cr: | 133 | timer_32ksynct_cr: |
| @@ -225,13 +217,13 @@ volt_delay_c: | |||
| 225 | mov pc, lr @ back to caller | 217 | mov pc, lr @ back to caller |
| 226 | 218 | ||
| 227 | ddr_cm_clksel2_pll: | 219 | ddr_cm_clksel2_pll: |
| 228 | .word CM_CLKSEL2_PLL_V | 220 | .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2) |
| 229 | ddr_sdrc_dlla_ctrl: | 221 | ddr_sdrc_dlla_ctrl: |
| 230 | .word SDRC_DLLA_CTRL_V | 222 | .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) |
| 231 | ddr_sdrc_rfr_ctrl: | 223 | ddr_sdrc_rfr_ctrl: |
| 232 | .word SDRC_RFR_CTRL_V | 224 | .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0) |
| 233 | ddr_prcm_voltctrl: | 225 | ddr_prcm_voltctrl: |
| 234 | .word PRCM_VOLTCTRL_V | 226 | .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50) |
| 235 | ddr_prcm_mask_val: | 227 | ddr_prcm_mask_val: |
| 236 | .word 0xFFFF3FFC | 228 | .word 0xFFFF3FFC |
| 237 | ddr_timer_32ksynct: | 229 | ddr_timer_32ksynct: |
| @@ -316,17 +308,17 @@ wait_dll_lock: | |||
| 316 | ldmfd sp!, {r0-r12, pc} @ restore regs and return | 308 | ldmfd sp!, {r0-r12, pc} @ restore regs and return |
| 317 | 309 | ||
| 318 | set_config: | 310 | set_config: |
| 319 | .word PRCM_CLKCFG_CTRL_V | 311 | .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x80) |
| 320 | pll_ctl: | 312 | pll_ctl: |
| 321 | .word CM_CLKEN_PLL_V | 313 | .word OMAP2420_CM_REGADDR(PLL_MOD, CM_FCLKEN1) |
| 322 | pll_stat: | 314 | pll_stat: |
| 323 | .word CM_IDLEST_CKGEN_V | 315 | .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST1) |
| 324 | pll_div: | 316 | pll_div: |
| 325 | .word CM_CLKSEL1_PLL_V | 317 | .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL) |
| 326 | sdrc_rfr: | 318 | sdrc_rfr: |
| 327 | .word SDRC_RFR_CTRL_V | 319 | .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0) |
| 328 | dlla_ctrl: | 320 | dlla_ctrl: |
| 329 | .word SDRC_DLLA_CTRL_V | 321 | .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) |
| 330 | 322 | ||
| 331 | ENTRY(sram_set_prcm_sz) | 323 | ENTRY(sram_set_prcm_sz) |
| 332 | .word . - sram_set_prcm | 324 | .word . - sram_set_prcm |
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index 3234deedb946..78d05f203fff 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c | |||
| @@ -3,6 +3,11 @@ | |||
| 3 | * | 3 | * |
| 4 | * OMAP2 GP timer support. | 4 | * OMAP2 GP timer support. |
| 5 | * | 5 | * |
| 6 | * Update to use new clocksource/clockevent layers | ||
| 7 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
| 8 | * Copyright (C) 2007 MontaVista Software, Inc. | ||
| 9 | * | ||
| 10 | * Original driver: | ||
| 6 | * Copyright (C) 2005 Nokia Corporation | 11 | * Copyright (C) 2005 Nokia Corporation |
| 7 | * Author: Paul Mundt <paul.mundt@nokia.com> | 12 | * Author: Paul Mundt <paul.mundt@nokia.com> |
| 8 | * Juha Yrjölä <juha.yrjola@nokia.com> | 13 | * Juha Yrjölä <juha.yrjola@nokia.com> |
| @@ -25,24 +30,23 @@ | |||
| 25 | #include <linux/clk.h> | 30 | #include <linux/clk.h> |
| 26 | #include <linux/delay.h> | 31 | #include <linux/delay.h> |
| 27 | #include <linux/irq.h> | 32 | #include <linux/irq.h> |
| 33 | #include <linux/clocksource.h> | ||
| 34 | #include <linux/clockchips.h> | ||
| 28 | 35 | ||
| 29 | #include <asm/mach/time.h> | 36 | #include <asm/mach/time.h> |
| 30 | #include <asm/arch/dmtimer.h> | 37 | #include <asm/arch/dmtimer.h> |
| 31 | 38 | ||
| 32 | static struct omap_dm_timer *gptimer; | 39 | static struct omap_dm_timer *gptimer; |
| 33 | 40 | static struct clock_event_device clockevent_gpt; | |
| 34 | static inline void omap2_gp_timer_start(unsigned long load_val) | ||
| 35 | { | ||
| 36 | omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val); | ||
| 37 | omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); | ||
| 38 | omap_dm_timer_start(gptimer); | ||
| 39 | } | ||
| 40 | 41 | ||
| 41 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) | 42 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
| 42 | { | 43 | { |
| 43 | omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW); | 44 | struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id; |
| 44 | timer_tick(); | 45 | struct clock_event_device *evt = &clockevent_gpt; |
| 46 | |||
| 47 | omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW); | ||
| 45 | 48 | ||
| 49 | evt->event_handler(evt); | ||
| 46 | return IRQ_HANDLED; | 50 | return IRQ_HANDLED; |
| 47 | } | 51 | } |
| 48 | 52 | ||
| @@ -52,20 +56,138 @@ static struct irqaction omap2_gp_timer_irq = { | |||
| 52 | .handler = omap2_gp_timer_interrupt, | 56 | .handler = omap2_gp_timer_interrupt, |
| 53 | }; | 57 | }; |
| 54 | 58 | ||
| 55 | static void __init omap2_gp_timer_init(void) | 59 | static int omap2_gp_timer_set_next_event(unsigned long cycles, |
| 60 | struct clock_event_device *evt) | ||
| 56 | { | 61 | { |
| 57 | u32 tick_period; | 62 | omap_dm_timer_set_load(gptimer, 0, 0xffffffff - cycles); |
| 63 | omap_dm_timer_start(gptimer); | ||
| 64 | |||
| 65 | return 0; | ||
| 66 | } | ||
| 67 | |||
| 68 | static void omap2_gp_timer_set_mode(enum clock_event_mode mode, | ||
| 69 | struct clock_event_device *evt) | ||
| 70 | { | ||
| 71 | u32 period; | ||
| 72 | |||
| 73 | omap_dm_timer_stop(gptimer); | ||
| 74 | |||
| 75 | switch (mode) { | ||
| 76 | case CLOCK_EVT_MODE_PERIODIC: | ||
| 77 | period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ; | ||
| 78 | period -= 1; | ||
| 79 | |||
| 80 | omap_dm_timer_set_load(gptimer, 1, 0xffffffff - period); | ||
| 81 | omap_dm_timer_start(gptimer); | ||
| 82 | break; | ||
| 83 | case CLOCK_EVT_MODE_ONESHOT: | ||
| 84 | break; | ||
| 85 | case CLOCK_EVT_MODE_UNUSED: | ||
| 86 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
| 87 | case CLOCK_EVT_MODE_RESUME: | ||
| 88 | break; | ||
| 89 | } | ||
| 90 | } | ||
| 91 | |||
| 92 | static struct clock_event_device clockevent_gpt = { | ||
| 93 | .name = "gp timer", | ||
| 94 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | ||
| 95 | .shift = 32, | ||
| 96 | .set_next_event = omap2_gp_timer_set_next_event, | ||
| 97 | .set_mode = omap2_gp_timer_set_mode, | ||
| 98 | }; | ||
| 99 | |||
| 100 | static void __init omap2_gp_clockevent_init(void) | ||
| 101 | { | ||
| 102 | u32 tick_rate; | ||
| 58 | 103 | ||
| 59 | omap_dm_timer_init(); | ||
| 60 | gptimer = omap_dm_timer_request_specific(1); | 104 | gptimer = omap_dm_timer_request_specific(1); |
| 61 | BUG_ON(gptimer == NULL); | 105 | BUG_ON(gptimer == NULL); |
| 62 | 106 | ||
| 107 | #if defined(CONFIG_OMAP_32K_TIMER) | ||
| 108 | omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ); | ||
| 109 | #else | ||
| 63 | omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK); | 110 | omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK); |
| 64 | tick_period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ; | 111 | #endif |
| 65 | tick_period -= 1; | 112 | tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); |
| 66 | 113 | ||
| 114 | omap2_gp_timer_irq.dev_id = (void *)gptimer; | ||
| 67 | setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); | 115 | setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); |
| 68 | omap2_gp_timer_start(tick_period); | 116 | omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); |
| 117 | |||
| 118 | clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC, | ||
| 119 | clockevent_gpt.shift); | ||
| 120 | clockevent_gpt.max_delta_ns = | ||
| 121 | clockevent_delta2ns(0xffffffff, &clockevent_gpt); | ||
| 122 | clockevent_gpt.min_delta_ns = | ||
| 123 | clockevent_delta2ns(1, &clockevent_gpt); | ||
| 124 | |||
| 125 | clockevent_gpt.cpumask = cpumask_of_cpu(0); | ||
| 126 | clockevents_register_device(&clockevent_gpt); | ||
| 127 | } | ||
| 128 | |||
| 129 | #ifdef CONFIG_OMAP_32K_TIMER | ||
| 130 | /* | ||
| 131 | * When 32k-timer is enabled, don't use GPTimer for clocksource | ||
| 132 | * instead, just leave default clocksource which uses the 32k | ||
| 133 | * sync counter. See clocksource setup in see plat-omap/common.c. | ||
| 134 | */ | ||
| 135 | |||
| 136 | static inline void __init omap2_gp_clocksource_init(void) {} | ||
| 137 | #else | ||
| 138 | /* | ||
| 139 | * clocksource | ||
| 140 | */ | ||
| 141 | static struct omap_dm_timer *gpt_clocksource; | ||
| 142 | static cycle_t clocksource_read_cycles(void) | ||
| 143 | { | ||
| 144 | return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource); | ||
| 145 | } | ||
| 146 | |||
| 147 | static struct clocksource clocksource_gpt = { | ||
| 148 | .name = "gp timer", | ||
| 149 | .rating = 300, | ||
| 150 | .read = clocksource_read_cycles, | ||
| 151 | .mask = CLOCKSOURCE_MASK(32), | ||
| 152 | .shift = 24, | ||
| 153 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
| 154 | }; | ||
| 155 | |||
| 156 | /* Setup free-running counter for clocksource */ | ||
| 157 | static void __init omap2_gp_clocksource_init(void) | ||
| 158 | { | ||
| 159 | static struct omap_dm_timer *gpt; | ||
| 160 | u32 tick_rate, tick_period; | ||
| 161 | static char err1[] __initdata = KERN_ERR | ||
| 162 | "%s: failed to request dm-timer\n"; | ||
| 163 | static char err2[] __initdata = KERN_ERR | ||
| 164 | "%s: can't register clocksource!\n"; | ||
| 165 | |||
| 166 | gpt = omap_dm_timer_request(); | ||
| 167 | if (!gpt) | ||
| 168 | printk(err1, clocksource_gpt.name); | ||
| 169 | gpt_clocksource = gpt; | ||
| 170 | |||
| 171 | omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK); | ||
| 172 | tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt)); | ||
| 173 | tick_period = (tick_rate / HZ) - 1; | ||
| 174 | |||
| 175 | omap_dm_timer_set_load(gpt, 1, 0); | ||
| 176 | omap_dm_timer_start(gpt); | ||
| 177 | |||
| 178 | clocksource_gpt.mult = | ||
| 179 | clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift); | ||
| 180 | if (clocksource_register(&clocksource_gpt)) | ||
| 181 | printk(err2, clocksource_gpt.name); | ||
| 182 | } | ||
| 183 | #endif | ||
| 184 | |||
| 185 | static void __init omap2_gp_timer_init(void) | ||
| 186 | { | ||
| 187 | omap_dm_timer_init(); | ||
| 188 | |||
| 189 | omap2_gp_clockevent_init(); | ||
| 190 | omap2_gp_clocksource_init(); | ||
| 69 | } | 191 | } |
| 70 | 192 | ||
| 71 | struct sys_timer omap_timer = { | 193 | struct sys_timer omap_timer = { |
diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c deleted file mode 100644 index 58cc3c0333b6..000000000000 --- a/arch/arm/mach-orion/addr-map.c +++ /dev/null | |||
| @@ -1,490 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-orion/addr-map.c | ||
| 3 | * | ||
| 4 | * Address map functions for Marvell Orion System On Chip | ||
| 5 | * | ||
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/init.h> | ||
| 15 | #include <asm/hardware.h> | ||
| 16 | #include "common.h" | ||
| 17 | |||
| 18 | /* | ||
| 19 | * The Orion has fully programable address map. There's a separate address | ||
| 20 | * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB, | ||
| 21 | * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own | ||
| 22 | * address decode windows that allow it to access any of the Orion resources. | ||
| 23 | * | ||
| 24 | * CPU address decoding -- | ||
| 25 | * Linux assumes that it is the boot loader that already setup the access to | ||
| 26 | * DDR and internal registers. | ||
| 27 | * Setup access to PCI and PCI-E IO/MEM space is issued by core.c. | ||
| 28 | * Setup access to various devices located on the device bus interface (e.g. | ||
| 29 | * flashes, RTC, etc) should be issued by machine-setup.c according to | ||
| 30 | * specific board population (by using orion_setup_cpu_win()). | ||
| 31 | * | ||
| 32 | * Non-CPU Masters address decoding -- | ||
| 33 | * Unlike the CPU, we setup the access from Orion's master interfaces to DDR | ||
| 34 | * banks only (the typical use case). | ||
| 35 | * Setup access for each master to DDR is issued by common.c. | ||
| 36 | * | ||
| 37 | * Note: although orion_setbits() and orion_clrbits() are not atomic | ||
| 38 | * no locking is necessary here since code in this file is only called | ||
| 39 | * at boot time when there is no concurrency issues. | ||
| 40 | */ | ||
| 41 | |||
| 42 | /* | ||
| 43 | * Generic Address Decode Windows bit settings | ||
| 44 | */ | ||
| 45 | #define TARGET_DDR 0 | ||
| 46 | #define TARGET_PCI 3 | ||
| 47 | #define TARGET_PCIE 4 | ||
| 48 | #define TARGET_DEV_BUS 1 | ||
| 49 | #define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \ | ||
| 50 | ((n) == 1) ? 0xd : \ | ||
| 51 | ((n) == 2) ? 0xb : \ | ||
| 52 | ((n) == 3) ? 0x7 : 0xf) | ||
| 53 | #define ATTR_PCIE_MEM 0x59 | ||
| 54 | #define ATTR_PCIE_IO 0x51 | ||
| 55 | #define ATTR_PCI_MEM 0x59 | ||
| 56 | #define ATTR_PCI_IO 0x51 | ||
| 57 | #define ATTR_DEV_CS0 0x1e | ||
| 58 | #define ATTR_DEV_CS1 0x1d | ||
| 59 | #define ATTR_DEV_CS2 0x1b | ||
| 60 | #define ATTR_DEV_BOOT 0xf | ||
| 61 | #define WIN_EN 1 | ||
| 62 | |||
| 63 | /* | ||
| 64 | * Helpers to get DDR banks info | ||
| 65 | */ | ||
| 66 | #define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8)) | ||
| 67 | #define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8)) | ||
| 68 | #define DDR_MAX_CS 4 | ||
| 69 | #define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1) | ||
| 70 | #define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000) | ||
| 71 | #define DDR_BANK_EN 1 | ||
| 72 | |||
| 73 | /* | ||
| 74 | * CPU Address Decode Windows registers | ||
| 75 | */ | ||
| 76 | #define CPU_WIN_CTRL(n) ORION_BRIDGE_REG(0x000 | ((n) << 4)) | ||
| 77 | #define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4)) | ||
| 78 | #define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4)) | ||
| 79 | #define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4)) | ||
| 80 | #define CPU_MAX_WIN 8 | ||
| 81 | |||
| 82 | /* | ||
| 83 | * Use this CPU address decode windows allocation | ||
| 84 | */ | ||
| 85 | #define CPU_WIN_PCIE_IO 0 | ||
| 86 | #define CPU_WIN_PCI_IO 1 | ||
| 87 | #define CPU_WIN_PCIE_MEM 2 | ||
| 88 | #define CPU_WIN_PCI_MEM 3 | ||
| 89 | #define CPU_WIN_DEV_BOOT 4 | ||
| 90 | #define CPU_WIN_DEV_CS0 5 | ||
| 91 | #define CPU_WIN_DEV_CS1 6 | ||
| 92 | #define CPU_WIN_DEV_CS2 7 | ||
| 93 | |||
| 94 | /* | ||
| 95 | * PCIE Address Decode Windows registers | ||
| 96 | */ | ||
| 97 | #define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4)) | ||
| 98 | #define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8)) | ||
| 99 | #define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8)) | ||
| 100 | #define PCIE_WIN_CTRL(n) (((n) < 5) ? \ | ||
| 101 | ORION_PCIE_REG(0x1820 + ((n) << 4)) : \ | ||
| 102 | ORION_PCIE_REG(0x1880)) | ||
| 103 | #define PCIE_WIN_BASE(n) (((n) < 5) ? \ | ||
| 104 | ORION_PCIE_REG(0x1824 + ((n) << 4)) : \ | ||
| 105 | ORION_PCIE_REG(0x1884)) | ||
| 106 | #define PCIE_WIN_REMAP(n) (((n) < 5) ? \ | ||
| 107 | ORION_PCIE_REG(0x182c + ((n) << 4)) : \ | ||
| 108 | ORION_PCIE_REG(0x188c)) | ||
| 109 | #define PCIE_DEFWIN_CTRL ORION_PCIE_REG(0x18b0) | ||
| 110 | #define PCIE_EXPROM_WIN_CTRL ORION_PCIE_REG(0x18c0) | ||
| 111 | #define PCIE_EXPROM_WIN_REMP ORION_PCIE_REG(0x18c4) | ||
| 112 | #define PCIE_MAX_BARS 3 | ||
| 113 | #define PCIE_MAX_WINS 6 | ||
| 114 | |||
| 115 | /* | ||
| 116 | * Use PCIE BAR '1' for all DDR banks | ||
| 117 | */ | ||
| 118 | #define PCIE_DRAM_BAR 1 | ||
| 119 | |||
| 120 | /* | ||
| 121 | * PCI Address Decode Windows registers | ||
| 122 | */ | ||
| 123 | #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \ | ||
| 124 | ((n) == 1) ? ORION_PCI_REG(0xd08) : \ | ||
| 125 | ((n) == 2) ? ORION_PCI_REG(0xc0c) : \ | ||
| 126 | ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0) | ||
| 127 | #define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \ | ||
| 128 | ((n) == 1) ? ORION_PCI_REG(0xd48) : \ | ||
| 129 | ((n) == 2) ? ORION_PCI_REG(0xc4c) : \ | ||
| 130 | ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0) | ||
| 131 | #define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c) | ||
| 132 | #define PCI_CTRL_BASE_LO(n) ORION_PCI_REG(0x1e00 | ((n) << 4)) | ||
| 133 | #define PCI_CTRL_BASE_HI(n) ORION_PCI_REG(0x1e04 | ((n) << 4)) | ||
| 134 | #define PCI_CTRL_SIZE(n) ORION_PCI_REG(0x1e08 | ((n) << 4)) | ||
| 135 | #define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c) | ||
| 136 | |||
| 137 | /* | ||
| 138 | * PCI configuration heleprs for BAR settings | ||
| 139 | */ | ||
| 140 | #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) | ||
| 141 | #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) | ||
| 142 | #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) | ||
| 143 | |||
| 144 | /* | ||
| 145 | * Gigabit Ethernet Address Decode Windows registers | ||
| 146 | */ | ||
| 147 | #define ETH_WIN_BASE(win) ORION_ETH_REG(0x200 + ((win) * 8)) | ||
| 148 | #define ETH_WIN_SIZE(win) ORION_ETH_REG(0x204 + ((win) * 8)) | ||
| 149 | #define ETH_WIN_REMAP(win) ORION_ETH_REG(0x280 + ((win) * 4)) | ||
| 150 | #define ETH_WIN_EN ORION_ETH_REG(0x290) | ||
| 151 | #define ETH_WIN_PROT ORION_ETH_REG(0x294) | ||
| 152 | #define ETH_MAX_WIN 6 | ||
| 153 | #define ETH_MAX_REMAP_WIN 4 | ||
| 154 | |||
| 155 | /* | ||
| 156 | * USB Address Decode Windows registers | ||
| 157 | */ | ||
| 158 | #define USB_WIN_CTRL(i, w) ((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \ | ||
| 159 | : ORION_USB1_REG(0x320 + ((w) << 4))) | ||
| 160 | #define USB_WIN_BASE(i, w) ((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \ | ||
| 161 | : ORION_USB1_REG(0x324 + ((w) << 4))) | ||
| 162 | #define USB_MAX_WIN 4 | ||
| 163 | |||
| 164 | /* | ||
| 165 | * SATA Address Decode Windows registers | ||
| 166 | */ | ||
| 167 | #define SATA_WIN_CTRL(win) ORION_SATA_REG(0x30 + ((win) * 0x10)) | ||
| 168 | #define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10)) | ||
| 169 | #define SATA_MAX_WIN 4 | ||
| 170 | |||
| 171 | static int __init orion_cpu_win_can_remap(u32 win) | ||
| 172 | { | ||
| 173 | u32 dev, rev; | ||
| 174 | |||
| 175 | orion_pcie_id(&dev, &rev); | ||
| 176 | if ((dev == MV88F5281_DEV_ID && win < 4) | ||
| 177 | || (dev == MV88F5182_DEV_ID && win < 2) | ||
| 178 | || (dev == MV88F5181_DEV_ID && win < 2)) | ||
| 179 | return 1; | ||
| 180 | |||
| 181 | return 0; | ||
| 182 | } | ||
| 183 | |||
| 184 | void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap) | ||
| 185 | { | ||
| 186 | u32 win, attr, ctrl; | ||
| 187 | |||
| 188 | switch (target) { | ||
| 189 | case ORION_PCIE_IO: | ||
| 190 | target = TARGET_PCIE; | ||
| 191 | attr = ATTR_PCIE_IO; | ||
| 192 | win = CPU_WIN_PCIE_IO; | ||
| 193 | break; | ||
| 194 | case ORION_PCI_IO: | ||
| 195 | target = TARGET_PCI; | ||
| 196 | attr = ATTR_PCI_IO; | ||
| 197 | win = CPU_WIN_PCI_IO; | ||
| 198 | break; | ||
| 199 | case ORION_PCIE_MEM: | ||
| 200 | target = TARGET_PCIE; | ||
| 201 | attr = ATTR_PCIE_MEM; | ||
| 202 | win = CPU_WIN_PCIE_MEM; | ||
| 203 | break; | ||
| 204 | case ORION_PCI_MEM: | ||
| 205 | target = TARGET_PCI; | ||
| 206 | attr = ATTR_PCI_MEM; | ||
| 207 | win = CPU_WIN_PCI_MEM; | ||
| 208 | break; | ||
| 209 | case ORION_DEV_BOOT: | ||
| 210 | target = TARGET_DEV_BUS; | ||
| 211 | attr = ATTR_DEV_BOOT; | ||
| 212 | win = CPU_WIN_DEV_BOOT; | ||
| 213 | break; | ||
| 214 | case ORION_DEV0: | ||
| 215 | target = TARGET_DEV_BUS; | ||
| 216 | attr = ATTR_DEV_CS0; | ||
| 217 | win = CPU_WIN_DEV_CS0; | ||
| 218 | break; | ||
| 219 | case ORION_DEV1: | ||
| 220 | target = TARGET_DEV_BUS; | ||
| 221 | attr = ATTR_DEV_CS1; | ||
| 222 | win = CPU_WIN_DEV_CS1; | ||
| 223 | break; | ||
| 224 | case ORION_DEV2: | ||
| 225 | target = TARGET_DEV_BUS; | ||
| 226 | attr = ATTR_DEV_CS2; | ||
| 227 | win = CPU_WIN_DEV_CS2; | ||
| 228 | break; | ||
| 229 | case ORION_DDR: | ||
| 230 | case ORION_REGS: | ||
| 231 | /* | ||
| 232 | * Must be mapped by bootloader. | ||
| 233 | */ | ||
| 234 | default: | ||
| 235 | target = attr = win = -1; | ||
| 236 | BUG(); | ||
| 237 | } | ||
| 238 | |||
| 239 | base &= 0xffff0000; | ||
| 240 | ctrl = (((size - 1) & 0xffff0000) | (attr << 8) | | ||
| 241 | (target << 4) | WIN_EN); | ||
| 242 | |||
| 243 | orion_write(CPU_WIN_BASE(win), base); | ||
| 244 | orion_write(CPU_WIN_CTRL(win), ctrl); | ||
| 245 | |||
| 246 | if (orion_cpu_win_can_remap(win)) { | ||
| 247 | if (remap >= 0) { | ||
| 248 | orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); | ||
| 249 | orion_write(CPU_WIN_REMAP_HI(win), 0); | ||
| 250 | } else { | ||
| 251 | orion_write(CPU_WIN_REMAP_LO(win), base); | ||
| 252 | orion_write(CPU_WIN_REMAP_HI(win), 0); | ||
| 253 | } | ||
| 254 | } | ||
| 255 | } | ||
| 256 | |||
| 257 | void __init orion_setup_cpu_wins(void) | ||
| 258 | { | ||
| 259 | int i; | ||
| 260 | |||
| 261 | /* | ||
| 262 | * First, disable and clear windows | ||
| 263 | */ | ||
| 264 | for (i = 0; i < CPU_MAX_WIN; i++) { | ||
| 265 | orion_write(CPU_WIN_BASE(i), 0); | ||
| 266 | orion_write(CPU_WIN_CTRL(i), 0); | ||
| 267 | if (orion_cpu_win_can_remap(i)) { | ||
| 268 | orion_write(CPU_WIN_REMAP_LO(i), 0); | ||
| 269 | orion_write(CPU_WIN_REMAP_HI(i), 0); | ||
| 270 | } | ||
| 271 | } | ||
| 272 | |||
| 273 | /* | ||
| 274 | * Setup windows for PCI+PCIe IO+MEM space. | ||
| 275 | */ | ||
| 276 | orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE, | ||
| 277 | ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE); | ||
| 278 | orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE, | ||
| 279 | ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE); | ||
| 280 | orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE, | ||
| 281 | ORION_PCIE_MEM_SIZE, -1); | ||
| 282 | orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE, | ||
| 283 | ORION_PCI_MEM_SIZE, -1); | ||
| 284 | } | ||
| 285 | |||
| 286 | /* | ||
| 287 | * Setup PCIE BARs and Address Decode Wins: | ||
| 288 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks | ||
| 289 | * WIN[0-3] -> DRAM bank[0-3] | ||
| 290 | */ | ||
| 291 | void __init orion_setup_pcie_wins(void) | ||
| 292 | { | ||
| 293 | u32 base, size, i; | ||
| 294 | |||
| 295 | /* | ||
| 296 | * First, disable and clear BARs and windows | ||
| 297 | */ | ||
| 298 | for (i = 1; i < PCIE_MAX_BARS; i++) { | ||
| 299 | orion_write(PCIE_BAR_CTRL(i), 0); | ||
| 300 | orion_write(PCIE_BAR_LO(i), 0); | ||
| 301 | orion_write(PCIE_BAR_HI(i), 0); | ||
| 302 | } | ||
| 303 | |||
| 304 | for (i = 0; i < PCIE_MAX_WINS; i++) { | ||
| 305 | orion_write(PCIE_WIN_CTRL(i), 0); | ||
| 306 | orion_write(PCIE_WIN_BASE(i), 0); | ||
| 307 | orion_write(PCIE_WIN_REMAP(i), 0); | ||
| 308 | } | ||
| 309 | |||
| 310 | /* | ||
| 311 | * Setup windows for DDR banks. Count total DDR size on the fly. | ||
| 312 | */ | ||
| 313 | base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0))); | ||
| 314 | size = 0; | ||
| 315 | for (i = 0; i < DDR_MAX_CS; i++) { | ||
| 316 | u32 bank_base, bank_size; | ||
| 317 | bank_size = orion_read(DDR_SIZE_CS(i)); | ||
| 318 | bank_base = orion_read(DDR_BASE_CS(i)); | ||
| 319 | if (bank_size & DDR_BANK_EN) { | ||
| 320 | bank_size = DDR_REG_TO_SIZE(bank_size); | ||
| 321 | bank_base = DDR_REG_TO_BASE(bank_base); | ||
| 322 | orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000); | ||
| 323 | orion_write(PCIE_WIN_REMAP(i), 0); | ||
| 324 | orion_write(PCIE_WIN_CTRL(i), | ||
| 325 | ((bank_size-1) & 0xffff0000) | | ||
| 326 | (ATTR_DDR_CS(i) << 8) | | ||
| 327 | (TARGET_DDR << 4) | | ||
| 328 | (PCIE_DRAM_BAR << 1) | WIN_EN); | ||
| 329 | size += bank_size; | ||
| 330 | } | ||
| 331 | } | ||
| 332 | |||
| 333 | /* | ||
| 334 | * Setup BAR[1] to all DRAM banks | ||
| 335 | */ | ||
| 336 | orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000); | ||
| 337 | orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0); | ||
| 338 | orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR), | ||
| 339 | ((size - 1) & 0xffff0000) | WIN_EN); | ||
| 340 | } | ||
| 341 | |||
| 342 | void __init orion_setup_pci_wins(void) | ||
| 343 | { | ||
| 344 | u32 base, size, i; | ||
| 345 | |||
| 346 | /* | ||
| 347 | * First, disable windows | ||
| 348 | */ | ||
| 349 | orion_write(PCI_BAR_ENABLE, 0xffffffff); | ||
| 350 | |||
| 351 | /* | ||
| 352 | * Setup windows for DDR banks. | ||
| 353 | */ | ||
| 354 | for (i = 0; i < DDR_MAX_CS; i++) { | ||
| 355 | base = orion_read(DDR_BASE_CS(i)); | ||
| 356 | size = orion_read(DDR_SIZE_CS(i)); | ||
| 357 | if (size & DDR_BANK_EN) { | ||
| 358 | u32 bus, dev, func, reg, val; | ||
| 359 | size = DDR_REG_TO_SIZE(size); | ||
| 360 | base = DDR_REG_TO_BASE(base); | ||
| 361 | bus = orion_pci_local_bus_nr(); | ||
| 362 | dev = orion_pci_local_dev_nr(); | ||
| 363 | func = PCI_CONF_FUNC_BAR_CS(i); | ||
| 364 | reg = PCI_CONF_REG_BAR_LO_CS(i); | ||
| 365 | orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val); | ||
| 366 | orion_pci_hw_wr_conf(bus, dev, func, reg, 4, | ||
| 367 | (base & 0xfffff000) | (val & 0xfff)); | ||
| 368 | reg = PCI_CONF_REG_BAR_HI_CS(i); | ||
| 369 | orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0); | ||
| 370 | orion_write(PCI_BAR_SIZE_DDR_CS(i), | ||
| 371 | (size - 1) & 0xfffff000); | ||
| 372 | orion_write(PCI_BAR_REMAP_DDR_CS(i), | ||
| 373 | base & 0xfffff000); | ||
| 374 | orion_clrbits(PCI_BAR_ENABLE, (1 << i)); | ||
| 375 | } | ||
| 376 | } | ||
| 377 | |||
| 378 | /* | ||
| 379 | * Disable automatic update of address remaping when writing to BARs | ||
| 380 | */ | ||
| 381 | orion_setbits(PCI_ADDR_DECODE_CTRL, 1); | ||
| 382 | } | ||
| 383 | |||
| 384 | void __init orion_setup_usb_wins(void) | ||
| 385 | { | ||
| 386 | int i; | ||
| 387 | u32 usb_if, dev, rev; | ||
| 388 | u32 max_usb_if = 1; | ||
| 389 | |||
| 390 | orion_pcie_id(&dev, &rev); | ||
| 391 | if (dev == MV88F5182_DEV_ID) | ||
| 392 | max_usb_if = 2; | ||
| 393 | |||
| 394 | for (usb_if = 0; usb_if < max_usb_if; usb_if++) { | ||
| 395 | /* | ||
| 396 | * First, disable and clear windows | ||
| 397 | */ | ||
| 398 | for (i = 0; i < USB_MAX_WIN; i++) { | ||
| 399 | orion_write(USB_WIN_BASE(usb_if, i), 0); | ||
| 400 | orion_write(USB_WIN_CTRL(usb_if, i), 0); | ||
| 401 | } | ||
| 402 | |||
| 403 | /* | ||
| 404 | * Setup windows for DDR banks. | ||
| 405 | */ | ||
| 406 | for (i = 0; i < DDR_MAX_CS; i++) { | ||
| 407 | u32 base, size; | ||
| 408 | size = orion_read(DDR_SIZE_CS(i)); | ||
| 409 | base = orion_read(DDR_BASE_CS(i)); | ||
| 410 | if (size & DDR_BANK_EN) { | ||
| 411 | base = DDR_REG_TO_BASE(base); | ||
| 412 | size = DDR_REG_TO_SIZE(size); | ||
| 413 | orion_write(USB_WIN_CTRL(usb_if, i), | ||
| 414 | ((size-1) & 0xffff0000) | | ||
| 415 | (ATTR_DDR_CS(i) << 8) | | ||
| 416 | (TARGET_DDR << 4) | WIN_EN); | ||
| 417 | orion_write(USB_WIN_BASE(usb_if, i), | ||
| 418 | base & 0xffff0000); | ||
| 419 | } | ||
| 420 | } | ||
| 421 | } | ||
| 422 | } | ||
| 423 | |||
| 424 | void __init orion_setup_eth_wins(void) | ||
| 425 | { | ||
| 426 | int i; | ||
| 427 | |||
| 428 | /* | ||
| 429 | * First, disable and clear windows | ||
| 430 | */ | ||
| 431 | for (i = 0; i < ETH_MAX_WIN; i++) { | ||
| 432 | orion_write(ETH_WIN_BASE(i), 0); | ||
| 433 | orion_write(ETH_WIN_SIZE(i), 0); | ||
| 434 | orion_setbits(ETH_WIN_EN, 1 << i); | ||
| 435 | orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2)); | ||
| 436 | if (i < ETH_MAX_REMAP_WIN) | ||
| 437 | orion_write(ETH_WIN_REMAP(i), 0); | ||
| 438 | } | ||
| 439 | |||
| 440 | /* | ||
| 441 | * Setup windows for DDR banks. | ||
| 442 | */ | ||
| 443 | for (i = 0; i < DDR_MAX_CS; i++) { | ||
| 444 | u32 base, size; | ||
| 445 | size = orion_read(DDR_SIZE_CS(i)); | ||
| 446 | base = orion_read(DDR_BASE_CS(i)); | ||
| 447 | if (size & DDR_BANK_EN) { | ||
| 448 | base = DDR_REG_TO_BASE(base); | ||
| 449 | size = DDR_REG_TO_SIZE(size); | ||
| 450 | orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000); | ||
| 451 | orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) | | ||
| 452 | (ATTR_DDR_CS(i) << 8) | | ||
| 453 | TARGET_DDR); | ||
| 454 | orion_clrbits(ETH_WIN_EN, 1 << i); | ||
| 455 | orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2)); | ||
| 456 | } | ||
| 457 | } | ||
| 458 | } | ||
| 459 | |||
| 460 | void __init orion_setup_sata_wins(void) | ||
| 461 | { | ||
| 462 | int i; | ||
| 463 | |||
| 464 | /* | ||
| 465 | * First, disable and clear windows | ||
| 466 | */ | ||
| 467 | for (i = 0; i < SATA_MAX_WIN; i++) { | ||
| 468 | orion_write(SATA_WIN_BASE(i), 0); | ||
| 469 | orion_write(SATA_WIN_CTRL(i), 0); | ||
| 470 | } | ||
| 471 | |||
| 472 | /* | ||
| 473 | * Setup windows for DDR banks. | ||
| 474 | */ | ||
| 475 | for (i = 0; i < DDR_MAX_CS; i++) { | ||
| 476 | u32 base, size; | ||
| 477 | size = orion_read(DDR_SIZE_CS(i)); | ||
| 478 | base = orion_read(DDR_BASE_CS(i)); | ||
| 479 | if (size & DDR_BANK_EN) { | ||
| 480 | base = DDR_REG_TO_BASE(base); | ||
| 481 | size = DDR_REG_TO_SIZE(size); | ||
| 482 | orion_write(SATA_WIN_CTRL(i), | ||
| 483 | ((size-1) & 0xffff0000) | | ||
| 484 | (ATTR_DDR_CS(i) << 8) | | ||
| 485 | (TARGET_DDR << 4) | WIN_EN); | ||
| 486 | orion_write(SATA_WIN_BASE(i), | ||
| 487 | base & 0xffff0000); | ||
| 488 | } | ||
| 489 | } | ||
| 490 | } | ||
diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h deleted file mode 100644 index 501497cc2c4d..000000000000 --- a/arch/arm/mach-orion/common.h +++ /dev/null | |||
| @@ -1,92 +0,0 @@ | |||
| 1 | #ifndef __ARCH_ORION_COMMON_H__ | ||
| 2 | #define __ARCH_ORION_COMMON_H__ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Basic Orion init functions used early by machine-setup. | ||
| 6 | */ | ||
| 7 | |||
| 8 | void __init orion_map_io(void); | ||
| 9 | void __init orion_init_irq(void); | ||
| 10 | void __init orion_init(void); | ||
| 11 | |||
| 12 | /* | ||
| 13 | * Enumerations and functions for Orion windows mapping. Used by Orion core | ||
| 14 | * functions to map its interfaces and by the machine-setup to map its on- | ||
| 15 | * board devices. Details in /mach-orion/addr-map.c | ||
| 16 | */ | ||
| 17 | |||
| 18 | enum orion_target { | ||
| 19 | ORION_DEV_BOOT = 0, | ||
| 20 | ORION_DEV0, | ||
| 21 | ORION_DEV1, | ||
| 22 | ORION_DEV2, | ||
| 23 | ORION_PCIE_MEM, | ||
| 24 | ORION_PCIE_IO, | ||
| 25 | ORION_PCI_MEM, | ||
| 26 | ORION_PCI_IO, | ||
| 27 | ORION_DDR, | ||
| 28 | ORION_REGS, | ||
| 29 | ORION_MAX_TARGETS | ||
| 30 | }; | ||
| 31 | |||
| 32 | void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap); | ||
| 33 | void orion_setup_cpu_wins(void); | ||
| 34 | void orion_setup_eth_wins(void); | ||
| 35 | void orion_setup_usb_wins(void); | ||
| 36 | void orion_setup_pci_wins(void); | ||
| 37 | void orion_setup_pcie_wins(void); | ||
| 38 | void orion_setup_sata_wins(void); | ||
| 39 | |||
| 40 | /* | ||
| 41 | * Shared code used internally by other Orion core functions. | ||
| 42 | * (/mach-orion/pci.c) | ||
| 43 | */ | ||
| 44 | |||
| 45 | struct pci_sys_data; | ||
| 46 | struct pci_bus; | ||
| 47 | |||
| 48 | void orion_pcie_id(u32 *dev, u32 *rev); | ||
| 49 | u32 orion_pcie_local_bus_nr(void); | ||
| 50 | u32 orion_pci_local_bus_nr(void); | ||
| 51 | u32 orion_pci_local_dev_nr(void); | ||
| 52 | int orion_pci_sys_setup(int nr, struct pci_sys_data *sys); | ||
| 53 | struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); | ||
| 54 | int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val); | ||
| 55 | int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val); | ||
| 56 | |||
| 57 | /* | ||
| 58 | * Valid GPIO pins according to MPP setup, used by machine-setup. | ||
| 59 | * (/mach-orion/gpio.c). | ||
| 60 | */ | ||
| 61 | |||
| 62 | void __init orion_gpio_set_valid_pins(u32 pins); | ||
| 63 | void gpio_display(void); /* debug */ | ||
| 64 | |||
| 65 | /* | ||
| 66 | * Orion system timer (clocksource + clockevnt, /mach-orion/time.c) | ||
| 67 | */ | ||
| 68 | extern struct sys_timer orion_timer; | ||
| 69 | |||
| 70 | /* | ||
| 71 | * Pull in Orion Ethernet platform_data, used by machine-setup | ||
| 72 | */ | ||
| 73 | |||
| 74 | struct mv643xx_eth_platform_data; | ||
| 75 | |||
| 76 | void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data); | ||
| 77 | |||
| 78 | /* | ||
| 79 | * Orion Sata platform_data, used by machine-setup | ||
| 80 | */ | ||
| 81 | |||
| 82 | struct mv_sata_platform_data; | ||
| 83 | |||
| 84 | void __init orion_sata_init(struct mv_sata_platform_data *sata_data); | ||
| 85 | |||
| 86 | struct machine_desc; | ||
| 87 | struct meminfo; | ||
| 88 | struct tag; | ||
| 89 | extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, | ||
| 90 | char **, struct meminfo *); | ||
| 91 | |||
| 92 | #endif /* __ARCH_ORION_COMMON_H__ */ | ||
diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c deleted file mode 100644 index b109bb46681e..000000000000 --- a/arch/arm/mach-orion/pci.c +++ /dev/null | |||
| @@ -1,557 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-orion/pci.c | ||
| 3 | * | ||
| 4 | * PCI and PCIE functions for Marvell Orion System On Chip | ||
| 5 | * | ||
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/pci.h> | ||
| 15 | #include <asm/mach/pci.h> | ||
| 16 | #include "common.h" | ||
| 17 | |||
| 18 | /***************************************************************************** | ||
| 19 | * Orion has one PCIE controller and one PCI controller. | ||
| 20 | * | ||
| 21 | * Note1: The local PCIE bus number is '0'. The local PCI bus number | ||
| 22 | * follows the scanned PCIE bridged busses, if any. | ||
| 23 | * | ||
| 24 | * Note2: It is possible for PCI/PCIE agents to access many subsystem's | ||
| 25 | * space, by configuring BARs and Address Decode Windows, e.g. flashes on | ||
| 26 | * device bus, Orion registers, etc. However this code only enable the | ||
| 27 | * access to DDR banks. | ||
| 28 | ****************************************************************************/ | ||
| 29 | |||
| 30 | |||
| 31 | /***************************************************************************** | ||
| 32 | * PCIE controller | ||
| 33 | ****************************************************************************/ | ||
| 34 | #define PCIE_CTRL ORION_PCIE_REG(0x1a00) | ||
| 35 | #define PCIE_STAT ORION_PCIE_REG(0x1a04) | ||
| 36 | #define PCIE_DEV_ID ORION_PCIE_REG(0x0000) | ||
| 37 | #define PCIE_CMD_STAT ORION_PCIE_REG(0x0004) | ||
| 38 | #define PCIE_DEV_REV ORION_PCIE_REG(0x0008) | ||
| 39 | #define PCIE_MASK ORION_PCIE_REG(0x1910) | ||
| 40 | #define PCIE_CONF_ADDR ORION_PCIE_REG(0x18f8) | ||
| 41 | #define PCIE_CONF_DATA ORION_PCIE_REG(0x18fc) | ||
| 42 | |||
| 43 | /* | ||
| 44 | * PCIE_STAT bits | ||
| 45 | */ | ||
| 46 | #define PCIE_STAT_LINK_DOWN 1 | ||
| 47 | #define PCIE_STAT_BUS_OFFS 8 | ||
| 48 | #define PCIE_STAT_BUS_MASK (0xff << PCIE_STAT_BUS_OFFS) | ||
| 49 | #define PCIE_STAT_DEV_OFFS 20 | ||
| 50 | #define PCIE_STAT_DEV_MASK (0x1f << PCIE_STAT_DEV_OFFS) | ||
| 51 | |||
| 52 | /* | ||
| 53 | * PCIE_CONF_ADDR bits | ||
| 54 | */ | ||
| 55 | #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 24) | ((r) & 0xfc)) | ||
| 56 | #define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8) | ||
| 57 | #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) | ||
| 58 | #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) | ||
| 59 | #define PCIE_CONF_ADDR_EN (1 << 31) | ||
| 60 | |||
| 61 | /* | ||
| 62 | * PCIE config cycles are done by programming the PCIE_CONF_ADDR register | ||
| 63 | * and then reading the PCIE_CONF_DATA register. Need to make sure these | ||
| 64 | * transactions are atomic. | ||
| 65 | */ | ||
| 66 | static DEFINE_SPINLOCK(orion_pcie_lock); | ||
| 67 | |||
| 68 | void orion_pcie_id(u32 *dev, u32 *rev) | ||
| 69 | { | ||
| 70 | *dev = orion_read(PCIE_DEV_ID) >> 16; | ||
| 71 | *rev = orion_read(PCIE_DEV_REV) & 0xff; | ||
| 72 | } | ||
| 73 | |||
| 74 | u32 orion_pcie_local_bus_nr(void) | ||
| 75 | { | ||
| 76 | u32 stat = orion_read(PCIE_STAT); | ||
| 77 | return((stat & PCIE_STAT_BUS_MASK) >> PCIE_STAT_BUS_OFFS); | ||
| 78 | } | ||
| 79 | |||
| 80 | static u32 orion_pcie_local_dev_nr(void) | ||
| 81 | { | ||
| 82 | u32 stat = orion_read(PCIE_STAT); | ||
| 83 | return((stat & PCIE_STAT_DEV_MASK) >> PCIE_STAT_DEV_OFFS); | ||
| 84 | } | ||
| 85 | |||
| 86 | static u32 orion_pcie_no_link(void) | ||
| 87 | { | ||
| 88 | u32 stat = orion_read(PCIE_STAT); | ||
| 89 | return(stat & PCIE_STAT_LINK_DOWN); | ||
| 90 | } | ||
| 91 | |||
| 92 | static void orion_pcie_set_bus_nr(int nr) | ||
| 93 | { | ||
| 94 | orion_clrbits(PCIE_STAT, PCIE_STAT_BUS_MASK); | ||
| 95 | orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS); | ||
| 96 | } | ||
| 97 | |||
| 98 | static void orion_pcie_master_slave_enable(void) | ||
| 99 | { | ||
| 100 | orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER | | ||
| 101 | PCI_COMMAND_IO | | ||
| 102 | PCI_COMMAND_MEMORY); | ||
| 103 | } | ||
| 104 | |||
| 105 | static void orion_pcie_enable_interrupts(void) | ||
| 106 | { | ||
| 107 | /* | ||
| 108 | * Enable interrupts lines | ||
| 109 | * INTA[24] INTB[25] INTC[26] INTD[27] | ||
| 110 | */ | ||
| 111 | orion_setbits(PCIE_MASK, 0xf<<24); | ||
| 112 | } | ||
| 113 | |||
| 114 | static int orion_pcie_valid_config(u32 bus, u32 dev) | ||
| 115 | { | ||
| 116 | /* | ||
| 117 | * Don't go out when trying to access -- | ||
| 118 | * 1. our own device | ||
| 119 | * 2. where there's no device connected (no link) | ||
| 120 | * 3. nonexisting devices on local bus | ||
| 121 | */ | ||
| 122 | |||
| 123 | if ((orion_pcie_local_bus_nr() == bus) && | ||
| 124 | (orion_pcie_local_dev_nr() == dev)) | ||
| 125 | return 0; | ||
| 126 | |||
| 127 | if (orion_pcie_no_link()) | ||
| 128 | return 0; | ||
| 129 | |||
| 130 | if (bus == orion_pcie_local_bus_nr()) | ||
| 131 | if (((orion_pcie_local_dev_nr() == 0) && (dev != 1)) || | ||
| 132 | ((orion_pcie_local_dev_nr() != 0) && (dev != 0))) | ||
| 133 | return 0; | ||
| 134 | |||
| 135 | return 1; | ||
| 136 | } | ||
| 137 | |||
| 138 | static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | ||
| 139 | int size, u32 *val) | ||
| 140 | { | ||
| 141 | unsigned long flags; | ||
| 142 | unsigned int dev, rev, pcie_addr; | ||
| 143 | |||
| 144 | if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { | ||
| 145 | *val = 0xffffffff; | ||
| 146 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 147 | } | ||
| 148 | |||
| 149 | spin_lock_irqsave(&orion_pcie_lock, flags); | ||
| 150 | |||
| 151 | orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) | | ||
| 152 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | ||
| 153 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | ||
| 154 | PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN); | ||
| 155 | |||
| 156 | orion_pcie_id(&dev, &rev); | ||
| 157 | if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { | ||
| 158 | /* extended register space */ | ||
| 159 | pcie_addr = ORION_PCIE_WA_VIRT_BASE; | ||
| 160 | pcie_addr |= PCIE_CONF_BUS(bus->number) | | ||
| 161 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | ||
| 162 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | ||
| 163 | PCIE_CONF_REG(where); | ||
| 164 | *val = orion_read(pcie_addr); | ||
| 165 | } else | ||
| 166 | *val = orion_read(PCIE_CONF_DATA); | ||
| 167 | |||
| 168 | if (size == 1) | ||
| 169 | *val = (*val >> (8*(where & 0x3))) & 0xff; | ||
| 170 | else if (size == 2) | ||
| 171 | *val = (*val >> (8*(where & 0x3))) & 0xffff; | ||
| 172 | |||
| 173 | spin_unlock_irqrestore(&orion_pcie_lock, flags); | ||
| 174 | |||
| 175 | return PCIBIOS_SUCCESSFUL; | ||
| 176 | } | ||
| 177 | |||
| 178 | |||
| 179 | static int orion_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, | ||
| 180 | int size, u32 val) | ||
| 181 | { | ||
| 182 | unsigned long flags; | ||
| 183 | int ret; | ||
| 184 | |||
| 185 | if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) | ||
| 186 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 187 | |||
| 188 | spin_lock_irqsave(&orion_pcie_lock, flags); | ||
| 189 | |||
| 190 | ret = PCIBIOS_SUCCESSFUL; | ||
| 191 | |||
| 192 | orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) | | ||
| 193 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | ||
| 194 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | ||
| 195 | PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN); | ||
| 196 | |||
| 197 | if (size == 4) { | ||
| 198 | __raw_writel(val, PCIE_CONF_DATA); | ||
| 199 | } else if (size == 2) { | ||
| 200 | __raw_writew(val, PCIE_CONF_DATA + (where & 0x3)); | ||
| 201 | } else if (size == 1) { | ||
| 202 | __raw_writeb(val, PCIE_CONF_DATA + (where & 0x3)); | ||
| 203 | } else { | ||
| 204 | ret = PCIBIOS_BAD_REGISTER_NUMBER; | ||
| 205 | } | ||
| 206 | |||
| 207 | spin_unlock_irqrestore(&orion_pcie_lock, flags); | ||
| 208 | |||
| 209 | return ret; | ||
| 210 | } | ||
| 211 | |||
| 212 | struct pci_ops orion_pcie_ops = { | ||
| 213 | .read = orion_pcie_rd_conf, | ||
| 214 | .write = orion_pcie_wr_conf, | ||
| 215 | }; | ||
| 216 | |||
| 217 | |||
| 218 | static int orion_pcie_setup(struct pci_sys_data *sys) | ||
| 219 | { | ||
| 220 | struct resource *res; | ||
| 221 | |||
| 222 | /* | ||
| 223 | * Master + Slave enable | ||
| 224 | */ | ||
| 225 | orion_pcie_master_slave_enable(); | ||
| 226 | |||
| 227 | /* | ||
| 228 | * Enable interrupts lines A-D | ||
| 229 | */ | ||
| 230 | orion_pcie_enable_interrupts(); | ||
| 231 | |||
| 232 | /* | ||
| 233 | * Request resource | ||
| 234 | */ | ||
| 235 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); | ||
| 236 | if (!res) | ||
| 237 | panic("orion_pci_setup unable to alloc resources"); | ||
| 238 | |||
| 239 | /* | ||
| 240 | * IORESOURCE_IO | ||
| 241 | */ | ||
| 242 | res[0].name = "PCI-EX I/O Space"; | ||
| 243 | res[0].flags = IORESOURCE_IO; | ||
| 244 | res[0].start = ORION_PCIE_IO_BUS_BASE; | ||
| 245 | res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1; | ||
| 246 | if (request_resource(&ioport_resource, &res[0])) | ||
| 247 | panic("Request PCIE IO resource failed\n"); | ||
| 248 | sys->resource[0] = &res[0]; | ||
| 249 | |||
| 250 | /* | ||
| 251 | * IORESOURCE_MEM | ||
| 252 | */ | ||
| 253 | res[1].name = "PCI-EX Memory Space"; | ||
| 254 | res[1].flags = IORESOURCE_MEM; | ||
| 255 | res[1].start = ORION_PCIE_MEM_PHYS_BASE; | ||
| 256 | res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1; | ||
| 257 | if (request_resource(&iomem_resource, &res[1])) | ||
| 258 | panic("Request PCIE Memory resource failed\n"); | ||
| 259 | sys->resource[1] = &res[1]; | ||
| 260 | |||
| 261 | sys->resource[2] = NULL; | ||
| 262 | sys->io_offset = 0; | ||
| 263 | |||
| 264 | return 1; | ||
| 265 | } | ||
| 266 | |||
| 267 | /***************************************************************************** | ||
| 268 | * PCI controller | ||
| 269 | ****************************************************************************/ | ||
| 270 | #define PCI_MODE ORION_PCI_REG(0xd00) | ||
| 271 | #define PCI_CMD ORION_PCI_REG(0xc00) | ||
| 272 | #define PCI_P2P_CONF ORION_PCI_REG(0x1d14) | ||
| 273 | #define PCI_CONF_ADDR ORION_PCI_REG(0xc78) | ||
| 274 | #define PCI_CONF_DATA ORION_PCI_REG(0xc7c) | ||
| 275 | |||
| 276 | /* | ||
| 277 | * PCI_MODE bits | ||
| 278 | */ | ||
| 279 | #define PCI_MODE_64BIT (1 << 2) | ||
| 280 | #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) | ||
| 281 | |||
| 282 | /* | ||
| 283 | * PCI_CMD bits | ||
| 284 | */ | ||
| 285 | #define PCI_CMD_HOST_REORDER (1 << 29) | ||
| 286 | |||
| 287 | /* | ||
| 288 | * PCI_P2P_CONF bits | ||
| 289 | */ | ||
| 290 | #define PCI_P2P_BUS_OFFS 16 | ||
| 291 | #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) | ||
| 292 | #define PCI_P2P_DEV_OFFS 24 | ||
| 293 | #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) | ||
| 294 | |||
| 295 | /* | ||
| 296 | * PCI_CONF_ADDR bits | ||
| 297 | */ | ||
| 298 | #define PCI_CONF_REG(reg) ((reg) & 0xfc) | ||
| 299 | #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) | ||
| 300 | #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) | ||
| 301 | #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) | ||
| 302 | #define PCI_CONF_ADDR_EN (1 << 31) | ||
| 303 | |||
| 304 | /* | ||
| 305 | * Internal configuration space | ||
| 306 | */ | ||
| 307 | #define PCI_CONF_FUNC_STAT_CMD 0 | ||
| 308 | #define PCI_CONF_REG_STAT_CMD 4 | ||
| 309 | #define PCIX_STAT 0x64 | ||
| 310 | #define PCIX_STAT_BUS_OFFS 8 | ||
| 311 | #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) | ||
| 312 | |||
| 313 | /* | ||
| 314 | * PCI config cycles are done by programming the PCI_CONF_ADDR register | ||
| 315 | * and then reading the PCI_CONF_DATA register. Need to make sure these | ||
| 316 | * transactions are atomic. | ||
| 317 | */ | ||
| 318 | static DEFINE_SPINLOCK(orion_pci_lock); | ||
| 319 | |||
| 320 | u32 orion_pci_local_bus_nr(void) | ||
| 321 | { | ||
| 322 | u32 conf = orion_read(PCI_P2P_CONF); | ||
| 323 | return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); | ||
| 324 | } | ||
| 325 | |||
| 326 | u32 orion_pci_local_dev_nr(void) | ||
| 327 | { | ||
| 328 | u32 conf = orion_read(PCI_P2P_CONF); | ||
| 329 | return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS); | ||
| 330 | } | ||
| 331 | |||
| 332 | int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, | ||
| 333 | u32 where, u32 size, u32 *val) | ||
| 334 | { | ||
| 335 | unsigned long flags; | ||
| 336 | spin_lock_irqsave(&orion_pci_lock, flags); | ||
| 337 | |||
| 338 | orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | | ||
| 339 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | ||
| 340 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); | ||
| 341 | |||
| 342 | *val = orion_read(PCI_CONF_DATA); | ||
| 343 | |||
| 344 | if (size == 1) | ||
| 345 | *val = (*val >> (8*(where & 0x3))) & 0xff; | ||
| 346 | else if (size == 2) | ||
| 347 | *val = (*val >> (8*(where & 0x3))) & 0xffff; | ||
| 348 | |||
| 349 | spin_unlock_irqrestore(&orion_pci_lock, flags); | ||
| 350 | |||
| 351 | return PCIBIOS_SUCCESSFUL; | ||
| 352 | } | ||
| 353 | |||
| 354 | int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, | ||
| 355 | u32 where, u32 size, u32 val) | ||
| 356 | { | ||
| 357 | unsigned long flags; | ||
| 358 | int ret = PCIBIOS_SUCCESSFUL; | ||
| 359 | |||
| 360 | spin_lock_irqsave(&orion_pci_lock, flags); | ||
| 361 | |||
| 362 | orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | | ||
| 363 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | ||
| 364 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); | ||
| 365 | |||
| 366 | if (size == 4) { | ||
| 367 | __raw_writel(val, PCI_CONF_DATA); | ||
| 368 | } else if (size == 2) { | ||
| 369 | __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); | ||
| 370 | } else if (size == 1) { | ||
| 371 | __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); | ||
| 372 | } else { | ||
| 373 | ret = PCIBIOS_BAD_REGISTER_NUMBER; | ||
| 374 | } | ||
| 375 | |||
| 376 | spin_unlock_irqrestore(&orion_pci_lock, flags); | ||
| 377 | |||
| 378 | return ret; | ||
| 379 | } | ||
| 380 | |||
| 381 | static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn, | ||
| 382 | int where, int size, u32 *val) | ||
| 383 | { | ||
| 384 | /* | ||
| 385 | * Don't go out for local device | ||
| 386 | */ | ||
| 387 | if ((orion_pci_local_bus_nr() == bus->number) && | ||
| 388 | (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) { | ||
| 389 | *val = 0xffffffff; | ||
| 390 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 391 | } | ||
| 392 | |||
| 393 | return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), | ||
| 394 | PCI_FUNC(devfn), where, size, val); | ||
| 395 | } | ||
| 396 | |||
| 397 | static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn, | ||
| 398 | int where, int size, u32 val) | ||
| 399 | { | ||
| 400 | /* | ||
| 401 | * Don't go out for local device | ||
| 402 | */ | ||
| 403 | if ((orion_pci_local_bus_nr() == bus->number) && | ||
| 404 | (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) | ||
| 405 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 406 | |||
| 407 | return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), | ||
| 408 | PCI_FUNC(devfn), where, size, val); | ||
| 409 | } | ||
| 410 | |||
| 411 | struct pci_ops orion_pci_ops = { | ||
| 412 | .read = orion_pci_rd_conf, | ||
| 413 | .write = orion_pci_wr_conf, | ||
| 414 | }; | ||
| 415 | |||
| 416 | static void orion_pci_set_bus_nr(int nr) | ||
| 417 | { | ||
| 418 | u32 p2p = orion_read(PCI_P2P_CONF); | ||
| 419 | |||
| 420 | if (orion_read(PCI_MODE) & PCI_MODE_PCIX) { | ||
| 421 | /* | ||
| 422 | * PCI-X mode | ||
| 423 | */ | ||
| 424 | u32 pcix_status, bus, dev; | ||
| 425 | bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; | ||
| 426 | dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; | ||
| 427 | orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); | ||
| 428 | pcix_status &= ~PCIX_STAT_BUS_MASK; | ||
| 429 | pcix_status |= (nr << PCIX_STAT_BUS_OFFS); | ||
| 430 | orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); | ||
| 431 | } else { | ||
| 432 | /* | ||
| 433 | * PCI Conventional mode | ||
| 434 | */ | ||
| 435 | p2p &= ~PCI_P2P_BUS_MASK; | ||
| 436 | p2p |= (nr << PCI_P2P_BUS_OFFS); | ||
| 437 | orion_write(PCI_P2P_CONF, p2p); | ||
| 438 | } | ||
| 439 | } | ||
| 440 | |||
| 441 | static void orion_pci_master_slave_enable(void) | ||
| 442 | { | ||
| 443 | u32 bus_nr, dev_nr, func, reg, val; | ||
| 444 | |||
| 445 | bus_nr = orion_pci_local_bus_nr(); | ||
| 446 | dev_nr = orion_pci_local_dev_nr(); | ||
| 447 | func = PCI_CONF_FUNC_STAT_CMD; | ||
| 448 | reg = PCI_CONF_REG_STAT_CMD; | ||
| 449 | orion_pci_hw_rd_conf(bus_nr, dev_nr, func, reg, 4, &val); | ||
| 450 | val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | ||
| 451 | orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7); | ||
| 452 | } | ||
| 453 | |||
| 454 | static int orion_pci_setup(struct pci_sys_data *sys) | ||
| 455 | { | ||
| 456 | struct resource *res; | ||
| 457 | |||
| 458 | /* | ||
| 459 | * Master + Slave enable | ||
| 460 | */ | ||
| 461 | orion_pci_master_slave_enable(); | ||
| 462 | |||
| 463 | /* | ||
| 464 | * Force ordering | ||
| 465 | */ | ||
| 466 | orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); | ||
| 467 | |||
| 468 | /* | ||
| 469 | * Request resources | ||
| 470 | */ | ||
| 471 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); | ||
| 472 | if (!res) | ||
| 473 | panic("orion_pci_setup unable to alloc resources"); | ||
| 474 | |||
| 475 | /* | ||
| 476 | * IORESOURCE_IO | ||
| 477 | */ | ||
| 478 | res[0].name = "PCI I/O Space"; | ||
| 479 | res[0].flags = IORESOURCE_IO; | ||
| 480 | res[0].start = ORION_PCI_IO_BUS_BASE; | ||
| 481 | res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1; | ||
| 482 | if (request_resource(&ioport_resource, &res[0])) | ||
| 483 | panic("Request PCI IO resource failed\n"); | ||
| 484 | sys->resource[0] = &res[0]; | ||
| 485 | |||
| 486 | /* | ||
| 487 | * IORESOURCE_MEM | ||
| 488 | */ | ||
| 489 | res[1].name = "PCI Memory Space"; | ||
| 490 | res[1].flags = IORESOURCE_MEM; | ||
| 491 | res[1].start = ORION_PCI_MEM_PHYS_BASE; | ||
| 492 | res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1; | ||
| 493 | if (request_resource(&iomem_resource, &res[1])) | ||
| 494 | panic("Request PCI Memory resource failed\n"); | ||
| 495 | sys->resource[1] = &res[1]; | ||
| 496 | |||
| 497 | sys->resource[2] = NULL; | ||
| 498 | sys->io_offset = 0; | ||
| 499 | |||
| 500 | return 1; | ||
| 501 | } | ||
| 502 | |||
| 503 | |||
| 504 | /***************************************************************************** | ||
| 505 | * General PCIE + PCI | ||
| 506 | ****************************************************************************/ | ||
| 507 | int orion_pci_sys_setup(int nr, struct pci_sys_data *sys) | ||
| 508 | { | ||
| 509 | int ret = 0; | ||
| 510 | |||
| 511 | if (nr == 0) { | ||
| 512 | /* | ||
| 513 | * PCIE setup | ||
| 514 | */ | ||
| 515 | orion_pcie_set_bus_nr(0); | ||
| 516 | ret = orion_pcie_setup(sys); | ||
| 517 | } else if (nr == 1) { | ||
| 518 | /* | ||
| 519 | * PCI setup | ||
| 520 | */ | ||
| 521 | ret = orion_pci_setup(sys); | ||
| 522 | } | ||
| 523 | |||
| 524 | return ret; | ||
| 525 | } | ||
| 526 | |||
| 527 | struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) | ||
| 528 | { | ||
| 529 | struct pci_ops *ops; | ||
| 530 | struct pci_bus *bus; | ||
| 531 | |||
| 532 | |||
| 533 | if (nr == 0) { | ||
| 534 | u32 pci_bus; | ||
| 535 | /* | ||
| 536 | * PCIE scan | ||
| 537 | */ | ||
| 538 | ops = &orion_pcie_ops; | ||
| 539 | bus = pci_scan_bus(sys->busnr, ops, sys); | ||
| 540 | /* | ||
| 541 | * Set local PCI bus number to follow PCIE bridges (if any) | ||
| 542 | */ | ||
| 543 | pci_bus = bus->number + bus->subordinate - bus->secondary + 1; | ||
| 544 | orion_pci_set_bus_nr(pci_bus); | ||
| 545 | } else if (nr == 1) { | ||
| 546 | /* | ||
| 547 | * PCI scan | ||
| 548 | */ | ||
| 549 | ops = &orion_pci_ops; | ||
| 550 | bus = pci_scan_bus(sys->busnr, ops, sys); | ||
| 551 | } else { | ||
| 552 | BUG(); | ||
| 553 | bus = NULL; | ||
| 554 | } | ||
| 555 | |||
| 556 | return bus; | ||
| 557 | } | ||
diff --git a/arch/arm/mach-orion/time.c b/arch/arm/mach-orion/time.c deleted file mode 100644 index bd4262da4f40..000000000000 --- a/arch/arm/mach-orion/time.c +++ /dev/null | |||
| @@ -1,181 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-orion/time.c | ||
| 3 | * | ||
| 4 | * Core time functions for Marvell Orion System On Chip | ||
| 5 | * | ||
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/clockchips.h> | ||
| 15 | #include <linux/interrupt.h> | ||
| 16 | #include <linux/irq.h> | ||
| 17 | #include <asm/mach/time.h> | ||
| 18 | #include <asm/arch/orion.h> | ||
| 19 | #include "common.h" | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Timer0: clock_event_device, Tick. | ||
| 23 | * Timer1: clocksource, Free running. | ||
| 24 | * WatchDog: Not used. | ||
| 25 | * | ||
| 26 | * Timers are counting down. | ||
| 27 | */ | ||
| 28 | #define CLOCKEVENT 0 | ||
| 29 | #define CLOCKSOURCE 1 | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Timers bits | ||
| 33 | */ | ||
| 34 | #define BRIDGE_INT_TIMER(x) (1 << ((x) + 1)) | ||
| 35 | #define TIMER_EN(x) (1 << ((x) * 2)) | ||
| 36 | #define TIMER_RELOAD_EN(x) (1 << (((x) * 2) + 1)) | ||
| 37 | #define BRIDGE_INT_TIMER_WD (1 << 3) | ||
| 38 | #define TIMER_WD_EN (1 << 4) | ||
| 39 | #define TIMER_WD_RELOAD_EN (1 << 5) | ||
| 40 | |||
| 41 | static cycle_t orion_clksrc_read(void) | ||
| 42 | { | ||
| 43 | return (0xffffffff - orion_read(TIMER_VAL(CLOCKSOURCE))); | ||
| 44 | } | ||
| 45 | |||
| 46 | static struct clocksource orion_clksrc = { | ||
| 47 | .name = "orion_clocksource", | ||
| 48 | .shift = 20, | ||
| 49 | .rating = 300, | ||
| 50 | .read = orion_clksrc_read, | ||
| 51 | .mask = CLOCKSOURCE_MASK(32), | ||
| 52 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
| 53 | }; | ||
| 54 | |||
| 55 | static int | ||
| 56 | orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) | ||
| 57 | { | ||
| 58 | unsigned long flags; | ||
| 59 | |||
| 60 | if (delta == 0) | ||
| 61 | return -ETIME; | ||
| 62 | |||
| 63 | local_irq_save(flags); | ||
| 64 | |||
| 65 | /* | ||
| 66 | * Clear and enable timer interrupt bit | ||
| 67 | */ | ||
| 68 | orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); | ||
| 69 | orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); | ||
| 70 | |||
| 71 | /* | ||
| 72 | * Setup new timer value | ||
| 73 | */ | ||
| 74 | orion_write(TIMER_VAL(CLOCKEVENT), delta); | ||
| 75 | |||
| 76 | /* | ||
| 77 | * Disable auto reload and kickoff the timer | ||
| 78 | */ | ||
| 79 | orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT)); | ||
| 80 | orion_setbits(TIMER_CTRL, TIMER_EN(CLOCKEVENT)); | ||
| 81 | |||
| 82 | local_irq_restore(flags); | ||
| 83 | |||
| 84 | return 0; | ||
| 85 | } | ||
| 86 | |||
| 87 | static void | ||
| 88 | orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) | ||
| 89 | { | ||
| 90 | unsigned long flags; | ||
| 91 | |||
| 92 | local_irq_save(flags); | ||
| 93 | |||
| 94 | if (mode == CLOCK_EVT_MODE_PERIODIC) { | ||
| 95 | /* | ||
| 96 | * Setup latch cycles in timer and enable reload interrupt. | ||
| 97 | */ | ||
| 98 | orion_write(TIMER_VAL_RELOAD(CLOCKEVENT), LATCH); | ||
| 99 | orion_write(TIMER_VAL(CLOCKEVENT), LATCH); | ||
| 100 | orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); | ||
| 101 | orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) | | ||
| 102 | TIMER_EN(CLOCKEVENT)); | ||
| 103 | } else { | ||
| 104 | /* | ||
| 105 | * Disable timer and interrupt | ||
| 106 | */ | ||
| 107 | orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); | ||
| 108 | orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); | ||
| 109 | orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) | | ||
| 110 | TIMER_EN(CLOCKEVENT)); | ||
| 111 | } | ||
| 112 | |||
| 113 | local_irq_restore(flags); | ||
| 114 | } | ||
| 115 | |||
| 116 | static struct clock_event_device orion_clkevt = { | ||
| 117 | .name = "orion_tick", | ||
| 118 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | ||
| 119 | .shift = 32, | ||
| 120 | .rating = 300, | ||
| 121 | .cpumask = CPU_MASK_CPU0, | ||
| 122 | .set_next_event = orion_clkevt_next_event, | ||
| 123 | .set_mode = orion_clkevt_mode, | ||
| 124 | }; | ||
| 125 | |||
| 126 | static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) | ||
| 127 | { | ||
| 128 | /* | ||
| 129 | * Clear cause bit and do event | ||
| 130 | */ | ||
| 131 | orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); | ||
| 132 | orion_clkevt.event_handler(&orion_clkevt); | ||
| 133 | return IRQ_HANDLED; | ||
| 134 | } | ||
| 135 | |||
| 136 | static struct irqaction orion_timer_irq = { | ||
| 137 | .name = "orion_tick", | ||
| 138 | .flags = IRQF_DISABLED | IRQF_TIMER, | ||
| 139 | .handler = orion_timer_interrupt | ||
| 140 | }; | ||
| 141 | |||
| 142 | static void orion_timer_init(void) | ||
| 143 | { | ||
| 144 | /* | ||
| 145 | * Setup clocksource free running timer (no interrupt on reload) | ||
| 146 | */ | ||
| 147 | orion_write(TIMER_VAL(CLOCKSOURCE), 0xffffffff); | ||
| 148 | orion_write(TIMER_VAL_RELOAD(CLOCKSOURCE), 0xffffffff); | ||
| 149 | orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKSOURCE)); | ||
| 150 | orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKSOURCE) | | ||
| 151 | TIMER_EN(CLOCKSOURCE)); | ||
| 152 | |||
| 153 | /* | ||
| 154 | * Register clocksource | ||
| 155 | */ | ||
| 156 | orion_clksrc.mult = | ||
| 157 | clocksource_hz2mult(CLOCK_TICK_RATE, orion_clksrc.shift); | ||
| 158 | |||
| 159 | clocksource_register(&orion_clksrc); | ||
| 160 | |||
| 161 | /* | ||
| 162 | * Connect and enable tick handler | ||
| 163 | */ | ||
| 164 | setup_irq(IRQ_ORION_BRIDGE, &orion_timer_irq); | ||
| 165 | |||
| 166 | /* | ||
| 167 | * Register clockevent | ||
| 168 | */ | ||
| 169 | orion_clkevt.mult = | ||
| 170 | div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, orion_clkevt.shift); | ||
| 171 | orion_clkevt.max_delta_ns = | ||
| 172 | clockevent_delta2ns(0xfffffffe, &orion_clkevt); | ||
| 173 | orion_clkevt.min_delta_ns = | ||
| 174 | clockevent_delta2ns(1, &orion_clkevt); | ||
| 175 | |||
| 176 | clockevents_register_device(&orion_clkevt); | ||
| 177 | } | ||
| 178 | |||
| 179 | struct sys_timer orion_timer = { | ||
| 180 | .init = orion_timer_init, | ||
| 181 | }; | ||
diff --git a/arch/arm/mach-orion/Kconfig b/arch/arm/mach-orion5x/Kconfig index 1dcbb6ac5a30..93debf336155 100644 --- a/arch/arm/mach-orion/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | if ARCH_ORION | 1 | if ARCH_ORION5X |
| 2 | 2 | ||
| 3 | menu "Orion Implementations" | 3 | menu "Orion Implementations" |
| 4 | 4 | ||
| @@ -36,6 +36,14 @@ config MACH_TS209 | |||
| 36 | Say 'Y' here if you want your kernel to support the | 36 | Say 'Y' here if you want your kernel to support the |
| 37 | QNAP TS-109/TS-209 platform. | 37 | QNAP TS-109/TS-209 platform. |
| 38 | 38 | ||
| 39 | config MACH_LINKSTATION_PRO | ||
| 40 | bool "Buffalo Linkstation Pro/Live" | ||
| 41 | select I2C_BOARDINFO | ||
| 42 | help | ||
| 43 | Say 'Y' here if you want your kernel to support the | ||
| 44 | Buffalo Linkstation Pro/Live platform. Both v1 and | ||
| 45 | v2 devices are supported. | ||
| 46 | |||
| 39 | endmenu | 47 | endmenu |
| 40 | 48 | ||
| 41 | endif | 49 | endif |
diff --git a/arch/arm/mach-orion/Makefile b/arch/arm/mach-orion5x/Makefile index f91d937a73e8..9301bf55910b 100644 --- a/arch/arm/mach-orion/Makefile +++ b/arch/arm/mach-orion5x/Makefile | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | obj-y += common.o addr-map.o pci.o gpio.o irq.o time.o | 1 | obj-y += common.o addr-map.o pci.o gpio.o irq.o |
| 2 | obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o | 2 | obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o |
| 3 | obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o | 3 | obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o |
| 4 | obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o | 4 | obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o |
| 5 | obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o | ||
| 5 | obj-$(CONFIG_MACH_DNS323) += dns323-setup.o | 6 | obj-$(CONFIG_MACH_DNS323) += dns323-setup.o |
| 6 | obj-$(CONFIG_MACH_TS209) += ts209-setup.o | 7 | obj-$(CONFIG_MACH_TS209) += ts209-setup.o |
diff --git a/arch/arm/mach-orion/Makefile.boot b/arch/arm/mach-orion5x/Makefile.boot index 67039c3e0c48..67039c3e0c48 100644 --- a/arch/arm/mach-orion/Makefile.boot +++ b/arch/arm/mach-orion5x/Makefile.boot | |||
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c new file mode 100644 index 000000000000..9608503d67f5 --- /dev/null +++ b/arch/arm/mach-orion5x/addr-map.c | |||
| @@ -0,0 +1,240 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-orion5x/addr-map.c | ||
| 3 | * | ||
| 4 | * Address map functions for Marvell Orion 5x SoCs | ||
| 5 | * | ||
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/mbus.h> | ||
| 16 | #include <asm/hardware.h> | ||
| 17 | #include <asm/io.h> | ||
| 18 | #include "common.h" | ||
| 19 | |||
| 20 | /* | ||
| 21 | * The Orion has fully programable address map. There's a separate address | ||
| 22 | * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB, | ||
| 23 | * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own | ||
| 24 | * address decode windows that allow it to access any of the Orion resources. | ||
| 25 | * | ||
| 26 | * CPU address decoding -- | ||
| 27 | * Linux assumes that it is the boot loader that already setup the access to | ||
| 28 | * DDR and internal registers. | ||
| 29 | * Setup access to PCI and PCIe IO/MEM space is issued by this file. | ||
| 30 | * Setup access to various devices located on the device bus interface (e.g. | ||
| 31 | * flashes, RTC, etc) should be issued by machine-setup.c according to | ||
| 32 | * specific board population (by using orion5x_setup_*_win()). | ||
| 33 | * | ||
| 34 | * Non-CPU Masters address decoding -- | ||
| 35 | * Unlike the CPU, we setup the access from Orion's master interfaces to DDR | ||
| 36 | * banks only (the typical use case). | ||
| 37 | * Setup access for each master to DDR is issued by common.c. | ||
| 38 | * | ||
| 39 | * Note: although orion_setbits() and orion_clrbits() are not atomic | ||
| 40 | * no locking is necessary here since code in this file is only called | ||
| 41 | * at boot time when there is no concurrency issues. | ||
| 42 | */ | ||
| 43 | |||
| 44 | /* | ||
| 45 | * Generic Address Decode Windows bit settings | ||
| 46 | */ | ||
| 47 | #define TARGET_DDR 0 | ||
| 48 | #define TARGET_DEV_BUS 1 | ||
| 49 | #define TARGET_PCI 3 | ||
| 50 | #define TARGET_PCIE 4 | ||
| 51 | #define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \ | ||
| 52 | ((n) == 1) ? 0xd : \ | ||
| 53 | ((n) == 2) ? 0xb : \ | ||
| 54 | ((n) == 3) ? 0x7 : 0xf) | ||
| 55 | #define ATTR_PCIE_MEM 0x59 | ||
| 56 | #define ATTR_PCIE_IO 0x51 | ||
| 57 | #define ATTR_PCIE_WA 0x79 | ||
| 58 | #define ATTR_PCI_MEM 0x59 | ||
| 59 | #define ATTR_PCI_IO 0x51 | ||
| 60 | #define ATTR_DEV_CS0 0x1e | ||
| 61 | #define ATTR_DEV_CS1 0x1d | ||
| 62 | #define ATTR_DEV_CS2 0x1b | ||
| 63 | #define ATTR_DEV_BOOT 0xf | ||
| 64 | #define WIN_EN 1 | ||
| 65 | |||
| 66 | /* | ||
| 67 | * Helpers to get DDR bank info | ||
| 68 | */ | ||
| 69 | #define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) * 8)) | ||
| 70 | #define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) * 8)) | ||
| 71 | #define DDR_MAX_CS 4 | ||
| 72 | #define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1) | ||
| 73 | #define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000) | ||
| 74 | #define DDR_BANK_EN 1 | ||
| 75 | |||
| 76 | /* | ||
| 77 | * CPU Address Decode Windows registers | ||
| 78 | */ | ||
| 79 | #define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4)) | ||
| 80 | #define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4)) | ||
| 81 | #define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) | ||
| 82 | #define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4)) | ||
| 83 | |||
| 84 | /* | ||
| 85 | * Gigabit Ethernet Address Decode Windows registers | ||
| 86 | */ | ||
| 87 | #define ETH_WIN_BASE(win) ORION5X_ETH_REG(0x200 + ((win) * 8)) | ||
| 88 | #define ETH_WIN_SIZE(win) ORION5X_ETH_REG(0x204 + ((win) * 8)) | ||
| 89 | #define ETH_WIN_REMAP(win) ORION5X_ETH_REG(0x280 + ((win) * 4)) | ||
| 90 | #define ETH_WIN_EN ORION5X_ETH_REG(0x290) | ||
| 91 | #define ETH_WIN_PROT ORION5X_ETH_REG(0x294) | ||
| 92 | #define ETH_MAX_WIN 6 | ||
| 93 | #define ETH_MAX_REMAP_WIN 4 | ||
| 94 | |||
| 95 | |||
| 96 | struct mbus_dram_target_info orion5x_mbus_dram_info; | ||
| 97 | |||
| 98 | static int __init orion5x_cpu_win_can_remap(int win) | ||
| 99 | { | ||
| 100 | u32 dev, rev; | ||
| 101 | |||
| 102 | orion5x_pcie_id(&dev, &rev); | ||
| 103 | if ((dev == MV88F5281_DEV_ID && win < 4) | ||
| 104 | || (dev == MV88F5182_DEV_ID && win < 2) | ||
| 105 | || (dev == MV88F5181_DEV_ID && win < 2)) | ||
| 106 | return 1; | ||
| 107 | |||
| 108 | return 0; | ||
| 109 | } | ||
| 110 | |||
| 111 | static void __init setup_cpu_win(int win, u32 base, u32 size, | ||
| 112 | u8 target, u8 attr, int remap) | ||
| 113 | { | ||
| 114 | orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000); | ||
| 115 | orion5x_write(CPU_WIN_CTRL(win), | ||
| 116 | ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); | ||
| 117 | |||
| 118 | if (orion5x_cpu_win_can_remap(win)) { | ||
| 119 | if (remap < 0) | ||
| 120 | remap = base; | ||
| 121 | |||
| 122 | orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); | ||
| 123 | orion5x_write(CPU_WIN_REMAP_HI(win), 0); | ||
| 124 | } | ||
| 125 | } | ||
| 126 | |||
| 127 | void __init orion5x_setup_cpu_mbus_bridge(void) | ||
| 128 | { | ||
| 129 | int i; | ||
| 130 | int cs; | ||
| 131 | |||
| 132 | /* | ||
| 133 | * First, disable and clear windows. | ||
| 134 | */ | ||
| 135 | for (i = 0; i < 8; i++) { | ||
| 136 | orion5x_write(CPU_WIN_BASE(i), 0); | ||
| 137 | orion5x_write(CPU_WIN_CTRL(i), 0); | ||
| 138 | if (orion5x_cpu_win_can_remap(i)) { | ||
| 139 | orion5x_write(CPU_WIN_REMAP_LO(i), 0); | ||
| 140 | orion5x_write(CPU_WIN_REMAP_HI(i), 0); | ||
| 141 | } | ||
| 142 | } | ||
| 143 | |||
| 144 | /* | ||
| 145 | * Setup windows for PCI+PCIe IO+MEM space. | ||
| 146 | */ | ||
| 147 | setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, | ||
| 148 | TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE); | ||
| 149 | setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, | ||
| 150 | TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE); | ||
| 151 | setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, | ||
| 152 | TARGET_PCIE, ATTR_PCIE_MEM, -1); | ||
| 153 | setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, | ||
| 154 | TARGET_PCI, ATTR_PCI_MEM, -1); | ||
| 155 | |||
| 156 | /* | ||
| 157 | * Setup MBUS dram target info. | ||
| 158 | */ | ||
| 159 | orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; | ||
| 160 | |||
| 161 | for (i = 0, cs = 0; i < 4; i++) { | ||
| 162 | u32 base = readl(DDR_BASE_CS(i)); | ||
| 163 | u32 size = readl(DDR_SIZE_CS(i)); | ||
| 164 | |||
| 165 | /* | ||
| 166 | * Chip select enabled? | ||
| 167 | */ | ||
| 168 | if (size & 1) { | ||
| 169 | struct mbus_dram_window *w; | ||
| 170 | |||
| 171 | w = &orion5x_mbus_dram_info.cs[cs++]; | ||
| 172 | w->cs_index = i; | ||
| 173 | w->mbus_attr = 0xf & ~(1 << i); | ||
| 174 | w->base = base & 0xff000000; | ||
| 175 | w->size = (size | 0x00ffffff) + 1; | ||
| 176 | } | ||
| 177 | } | ||
| 178 | orion5x_mbus_dram_info.num_cs = cs; | ||
| 179 | } | ||
| 180 | |||
| 181 | void __init orion5x_setup_dev_boot_win(u32 base, u32 size) | ||
| 182 | { | ||
| 183 | setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); | ||
| 184 | } | ||
| 185 | |||
| 186 | void __init orion5x_setup_dev0_win(u32 base, u32 size) | ||
| 187 | { | ||
| 188 | setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); | ||
| 189 | } | ||
| 190 | |||
| 191 | void __init orion5x_setup_dev1_win(u32 base, u32 size) | ||
| 192 | { | ||
| 193 | setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); | ||
| 194 | } | ||
| 195 | |||
| 196 | void __init orion5x_setup_dev2_win(u32 base, u32 size) | ||
| 197 | { | ||
| 198 | setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); | ||
| 199 | } | ||
| 200 | |||
| 201 | void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) | ||
| 202 | { | ||
| 203 | setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); | ||
| 204 | } | ||
| 205 | |||
| 206 | void __init orion5x_setup_eth_wins(void) | ||
| 207 | { | ||
| 208 | int i; | ||
| 209 | |||
| 210 | /* | ||
| 211 | * First, disable and clear windows | ||
| 212 | */ | ||
| 213 | for (i = 0; i < ETH_MAX_WIN; i++) { | ||
| 214 | orion5x_write(ETH_WIN_BASE(i), 0); | ||
| 215 | orion5x_write(ETH_WIN_SIZE(i), 0); | ||
| 216 | orion5x_setbits(ETH_WIN_EN, 1 << i); | ||
| 217 | orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2)); | ||
| 218 | if (i < ETH_MAX_REMAP_WIN) | ||
| 219 | orion5x_write(ETH_WIN_REMAP(i), 0); | ||
| 220 | } | ||
| 221 | |||
| 222 | /* | ||
| 223 | * Setup windows for DDR banks. | ||
| 224 | */ | ||
| 225 | for (i = 0; i < DDR_MAX_CS; i++) { | ||
| 226 | u32 base, size; | ||
| 227 | size = orion5x_read(DDR_SIZE_CS(i)); | ||
| 228 | base = orion5x_read(DDR_BASE_CS(i)); | ||
| 229 | if (size & DDR_BANK_EN) { | ||
| 230 | base = DDR_REG_TO_BASE(base); | ||
| 231 | size = DDR_REG_TO_SIZE(size); | ||
| 232 | orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000); | ||
| 233 | orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) | | ||
| 234 | (ATTR_DDR_CS(i) << 8) | | ||
| 235 | TARGET_DDR); | ||
| 236 | orion5x_clrbits(ETH_WIN_EN, 1 << i); | ||
| 237 | orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2)); | ||
| 238 | } | ||
| 239 | } | ||
| 240 | } | ||
diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion5x/common.c index bbc2b4ec932c..968deb58be01 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion5x/common.c | |||
| @@ -1,12 +1,12 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-orion/common.c | 2 | * arch/arm/mach-orion5x/common.c |
| 3 | * | 3 | * |
| 4 | * Core functions for Marvell Orion System On Chip | 4 | * Core functions for Marvell Orion 5x SoCs |
| 5 | * | 5 | * |
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> |
| 7 | * | 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public | 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any | 9 | * License version 2. This program is licensed "as is" without any |
| 10 | * warranty of any kind, whether express or implied. | 10 | * warranty of any kind, whether express or implied. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| @@ -14,64 +14,71 @@ | |||
| 14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
| 15 | #include <linux/platform_device.h> | 15 | #include <linux/platform_device.h> |
| 16 | #include <linux/serial_8250.h> | 16 | #include <linux/serial_8250.h> |
| 17 | #include <linux/mbus.h> | ||
| 17 | #include <linux/mv643xx_eth.h> | 18 | #include <linux/mv643xx_eth.h> |
| 18 | #include <linux/mv643xx_i2c.h> | 19 | #include <linux/mv643xx_i2c.h> |
| 20 | #include <linux/ata_platform.h> | ||
| 19 | #include <asm/page.h> | 21 | #include <asm/page.h> |
| 20 | #include <asm/setup.h> | 22 | #include <asm/setup.h> |
| 21 | #include <asm/timex.h> | 23 | #include <asm/timex.h> |
| 22 | #include <asm/mach/arch.h> | 24 | #include <asm/mach/arch.h> |
| 23 | #include <asm/mach/map.h> | 25 | #include <asm/mach/map.h> |
| 26 | #include <asm/mach/time.h> | ||
| 24 | #include <asm/arch/hardware.h> | 27 | #include <asm/arch/hardware.h> |
| 28 | #include <asm/arch/orion5x.h> | ||
| 29 | #include <asm/plat-orion/ehci-orion.h> | ||
| 30 | #include <asm/plat-orion/orion_nand.h> | ||
| 31 | #include <asm/plat-orion/time.h> | ||
| 25 | #include "common.h" | 32 | #include "common.h" |
| 26 | 33 | ||
| 27 | /***************************************************************************** | 34 | /***************************************************************************** |
| 28 | * I/O Address Mapping | 35 | * I/O Address Mapping |
| 29 | ****************************************************************************/ | 36 | ****************************************************************************/ |
| 30 | static struct map_desc orion_io_desc[] __initdata = { | 37 | static struct map_desc orion5x_io_desc[] __initdata = { |
| 31 | { | 38 | { |
| 32 | .virtual = ORION_REGS_VIRT_BASE, | 39 | .virtual = ORION5X_REGS_VIRT_BASE, |
| 33 | .pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE), | 40 | .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), |
| 34 | .length = ORION_REGS_SIZE, | 41 | .length = ORION5X_REGS_SIZE, |
| 35 | .type = MT_DEVICE | 42 | .type = MT_DEVICE |
| 36 | }, | 43 | }, |
| 37 | { | 44 | { |
| 38 | .virtual = ORION_PCIE_IO_VIRT_BASE, | 45 | .virtual = ORION5X_PCIE_IO_VIRT_BASE, |
| 39 | .pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE), | 46 | .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), |
| 40 | .length = ORION_PCIE_IO_SIZE, | 47 | .length = ORION5X_PCIE_IO_SIZE, |
| 41 | .type = MT_DEVICE | 48 | .type = MT_DEVICE |
| 42 | }, | 49 | }, |
| 43 | { | 50 | { |
| 44 | .virtual = ORION_PCI_IO_VIRT_BASE, | 51 | .virtual = ORION5X_PCI_IO_VIRT_BASE, |
| 45 | .pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE), | 52 | .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), |
| 46 | .length = ORION_PCI_IO_SIZE, | 53 | .length = ORION5X_PCI_IO_SIZE, |
| 47 | .type = MT_DEVICE | 54 | .type = MT_DEVICE |
| 48 | }, | 55 | }, |
| 49 | { | 56 | { |
| 50 | .virtual = ORION_PCIE_WA_VIRT_BASE, | 57 | .virtual = ORION5X_PCIE_WA_VIRT_BASE, |
| 51 | .pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE), | 58 | .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), |
| 52 | .length = ORION_PCIE_WA_SIZE, | 59 | .length = ORION5X_PCIE_WA_SIZE, |
| 53 | .type = MT_DEVICE | 60 | .type = MT_DEVICE |
| 54 | }, | 61 | }, |
| 55 | }; | 62 | }; |
| 56 | 63 | ||
| 57 | void __init orion_map_io(void) | 64 | void __init orion5x_map_io(void) |
| 58 | { | 65 | { |
| 59 | iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc)); | 66 | iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); |
| 60 | } | 67 | } |
| 61 | 68 | ||
| 62 | /***************************************************************************** | 69 | /***************************************************************************** |
| 63 | * UART | 70 | * UART |
| 64 | ****************************************************************************/ | 71 | ****************************************************************************/ |
| 65 | 72 | ||
| 66 | static struct resource orion_uart_resources[] = { | 73 | static struct resource orion5x_uart_resources[] = { |
| 67 | { | 74 | { |
| 68 | .start = UART0_PHYS_BASE, | 75 | .start = UART0_PHYS_BASE, |
| 69 | .end = UART0_PHYS_BASE + 0xff, | 76 | .end = UART0_PHYS_BASE + 0xff, |
| 70 | .flags = IORESOURCE_MEM, | 77 | .flags = IORESOURCE_MEM, |
| 71 | }, | 78 | }, |
| 72 | { | 79 | { |
| 73 | .start = IRQ_ORION_UART0, | 80 | .start = IRQ_ORION5X_UART0, |
| 74 | .end = IRQ_ORION_UART0, | 81 | .end = IRQ_ORION5X_UART0, |
| 75 | .flags = IORESOURCE_IRQ, | 82 | .flags = IORESOURCE_IRQ, |
| 76 | }, | 83 | }, |
| 77 | { | 84 | { |
| @@ -80,96 +87,102 @@ static struct resource orion_uart_resources[] = { | |||
| 80 | .flags = IORESOURCE_MEM, | 87 | .flags = IORESOURCE_MEM, |
| 81 | }, | 88 | }, |
| 82 | { | 89 | { |
| 83 | .start = IRQ_ORION_UART1, | 90 | .start = IRQ_ORION5X_UART1, |
| 84 | .end = IRQ_ORION_UART1, | 91 | .end = IRQ_ORION5X_UART1, |
| 85 | .flags = IORESOURCE_IRQ, | 92 | .flags = IORESOURCE_IRQ, |
| 86 | }, | 93 | }, |
| 87 | }; | 94 | }; |
| 88 | 95 | ||
| 89 | static struct plat_serial8250_port orion_uart_data[] = { | 96 | static struct plat_serial8250_port orion5x_uart_data[] = { |
| 90 | { | 97 | { |
| 91 | .mapbase = UART0_PHYS_BASE, | 98 | .mapbase = UART0_PHYS_BASE, |
| 92 | .membase = (char *)UART0_VIRT_BASE, | 99 | .membase = (char *)UART0_VIRT_BASE, |
| 93 | .irq = IRQ_ORION_UART0, | 100 | .irq = IRQ_ORION5X_UART0, |
| 94 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, | 101 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, |
| 95 | .iotype = UPIO_MEM, | 102 | .iotype = UPIO_MEM, |
| 96 | .regshift = 2, | 103 | .regshift = 2, |
| 97 | .uartclk = ORION_TCLK, | 104 | .uartclk = ORION5X_TCLK, |
| 98 | }, | 105 | }, |
| 99 | { | 106 | { |
| 100 | .mapbase = UART1_PHYS_BASE, | 107 | .mapbase = UART1_PHYS_BASE, |
| 101 | .membase = (char *)UART1_VIRT_BASE, | 108 | .membase = (char *)UART1_VIRT_BASE, |
| 102 | .irq = IRQ_ORION_UART1, | 109 | .irq = IRQ_ORION5X_UART1, |
| 103 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, | 110 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, |
| 104 | .iotype = UPIO_MEM, | 111 | .iotype = UPIO_MEM, |
| 105 | .regshift = 2, | 112 | .regshift = 2, |
| 106 | .uartclk = ORION_TCLK, | 113 | .uartclk = ORION5X_TCLK, |
| 107 | }, | 114 | }, |
| 108 | { }, | 115 | { }, |
| 109 | }; | 116 | }; |
| 110 | 117 | ||
| 111 | static struct platform_device orion_uart = { | 118 | static struct platform_device orion5x_uart = { |
| 112 | .name = "serial8250", | 119 | .name = "serial8250", |
| 113 | .id = PLAT8250_DEV_PLATFORM, | 120 | .id = PLAT8250_DEV_PLATFORM, |
| 114 | .dev = { | 121 | .dev = { |
| 115 | .platform_data = orion_uart_data, | 122 | .platform_data = orion5x_uart_data, |
| 116 | }, | 123 | }, |
| 117 | .resource = orion_uart_resources, | 124 | .resource = orion5x_uart_resources, |
| 118 | .num_resources = ARRAY_SIZE(orion_uart_resources), | 125 | .num_resources = ARRAY_SIZE(orion5x_uart_resources), |
| 119 | }; | 126 | }; |
| 120 | 127 | ||
| 121 | /******************************************************************************* | 128 | /******************************************************************************* |
| 122 | * USB Controller - 2 interfaces | 129 | * USB Controller - 2 interfaces |
| 123 | ******************************************************************************/ | 130 | ******************************************************************************/ |
| 124 | 131 | ||
| 125 | static struct resource orion_ehci0_resources[] = { | 132 | static struct resource orion5x_ehci0_resources[] = { |
| 126 | { | 133 | { |
| 127 | .start = ORION_USB0_PHYS_BASE, | 134 | .start = ORION5X_USB0_PHYS_BASE, |
| 128 | .end = ORION_USB0_PHYS_BASE + SZ_4K, | 135 | .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1, |
| 129 | .flags = IORESOURCE_MEM, | 136 | .flags = IORESOURCE_MEM, |
| 130 | }, | 137 | }, |
| 131 | { | 138 | { |
| 132 | .start = IRQ_ORION_USB0_CTRL, | 139 | .start = IRQ_ORION5X_USB0_CTRL, |
| 133 | .end = IRQ_ORION_USB0_CTRL, | 140 | .end = IRQ_ORION5X_USB0_CTRL, |
| 134 | .flags = IORESOURCE_IRQ, | 141 | .flags = IORESOURCE_IRQ, |
| 135 | }, | 142 | }, |
| 136 | }; | 143 | }; |
| 137 | 144 | ||
| 138 | static struct resource orion_ehci1_resources[] = { | 145 | static struct resource orion5x_ehci1_resources[] = { |
| 139 | { | 146 | { |
| 140 | .start = ORION_USB1_PHYS_BASE, | 147 | .start = ORION5X_USB1_PHYS_BASE, |
| 141 | .end = ORION_USB1_PHYS_BASE + SZ_4K, | 148 | .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1, |
| 142 | .flags = IORESOURCE_MEM, | 149 | .flags = IORESOURCE_MEM, |
| 143 | }, | 150 | }, |
| 144 | { | 151 | { |
| 145 | .start = IRQ_ORION_USB1_CTRL, | 152 | .start = IRQ_ORION5X_USB1_CTRL, |
| 146 | .end = IRQ_ORION_USB1_CTRL, | 153 | .end = IRQ_ORION5X_USB1_CTRL, |
| 147 | .flags = IORESOURCE_IRQ, | 154 | .flags = IORESOURCE_IRQ, |
| 148 | }, | 155 | }, |
| 149 | }; | 156 | }; |
| 150 | 157 | ||
| 158 | static struct orion_ehci_data orion5x_ehci_data = { | ||
| 159 | .dram = &orion5x_mbus_dram_info, | ||
| 160 | }; | ||
| 161 | |||
| 151 | static u64 ehci_dmamask = 0xffffffffUL; | 162 | static u64 ehci_dmamask = 0xffffffffUL; |
| 152 | 163 | ||
| 153 | static struct platform_device orion_ehci0 = { | 164 | static struct platform_device orion5x_ehci0 = { |
| 154 | .name = "orion-ehci", | 165 | .name = "orion-ehci", |
| 155 | .id = 0, | 166 | .id = 0, |
| 156 | .dev = { | 167 | .dev = { |
| 157 | .dma_mask = &ehci_dmamask, | 168 | .dma_mask = &ehci_dmamask, |
| 158 | .coherent_dma_mask = 0xffffffff, | 169 | .coherent_dma_mask = 0xffffffff, |
| 170 | .platform_data = &orion5x_ehci_data, | ||
| 159 | }, | 171 | }, |
| 160 | .resource = orion_ehci0_resources, | 172 | .resource = orion5x_ehci0_resources, |
| 161 | .num_resources = ARRAY_SIZE(orion_ehci0_resources), | 173 | .num_resources = ARRAY_SIZE(orion5x_ehci0_resources), |
| 162 | }; | 174 | }; |
| 163 | 175 | ||
| 164 | static struct platform_device orion_ehci1 = { | 176 | static struct platform_device orion5x_ehci1 = { |
| 165 | .name = "orion-ehci", | 177 | .name = "orion-ehci", |
| 166 | .id = 1, | 178 | .id = 1, |
| 167 | .dev = { | 179 | .dev = { |
| 168 | .dma_mask = &ehci_dmamask, | 180 | .dma_mask = &ehci_dmamask, |
| 169 | .coherent_dma_mask = 0xffffffff, | 181 | .coherent_dma_mask = 0xffffffff, |
| 182 | .platform_data = &orion5x_ehci_data, | ||
| 170 | }, | 183 | }, |
| 171 | .resource = orion_ehci1_resources, | 184 | .resource = orion5x_ehci1_resources, |
| 172 | .num_resources = ARRAY_SIZE(orion_ehci1_resources), | 185 | .num_resources = ARRAY_SIZE(orion5x_ehci1_resources), |
| 173 | }; | 186 | }; |
| 174 | 187 | ||
| 175 | /***************************************************************************** | 188 | /***************************************************************************** |
| @@ -177,42 +190,42 @@ static struct platform_device orion_ehci1 = { | |||
| 177 | * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) | 190 | * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) |
| 178 | ****************************************************************************/ | 191 | ****************************************************************************/ |
| 179 | 192 | ||
| 180 | static struct resource orion_eth_shared_resources[] = { | 193 | static struct resource orion5x_eth_shared_resources[] = { |
| 181 | { | 194 | { |
| 182 | .start = ORION_ETH_PHYS_BASE + 0x2000, | 195 | .start = ORION5X_ETH_PHYS_BASE + 0x2000, |
| 183 | .end = ORION_ETH_PHYS_BASE + 0x3fff, | 196 | .end = ORION5X_ETH_PHYS_BASE + 0x3fff, |
| 184 | .flags = IORESOURCE_MEM, | 197 | .flags = IORESOURCE_MEM, |
| 185 | }, | 198 | }, |
| 186 | }; | 199 | }; |
| 187 | 200 | ||
| 188 | static struct platform_device orion_eth_shared = { | 201 | static struct platform_device orion5x_eth_shared = { |
| 189 | .name = MV643XX_ETH_SHARED_NAME, | 202 | .name = MV643XX_ETH_SHARED_NAME, |
| 190 | .id = 0, | 203 | .id = 0, |
| 191 | .num_resources = 1, | 204 | .num_resources = 1, |
| 192 | .resource = orion_eth_shared_resources, | 205 | .resource = orion5x_eth_shared_resources, |
| 193 | }; | 206 | }; |
| 194 | 207 | ||
| 195 | static struct resource orion_eth_resources[] = { | 208 | static struct resource orion5x_eth_resources[] = { |
| 196 | { | 209 | { |
| 197 | .name = "eth irq", | 210 | .name = "eth irq", |
| 198 | .start = IRQ_ORION_ETH_SUM, | 211 | .start = IRQ_ORION5X_ETH_SUM, |
| 199 | .end = IRQ_ORION_ETH_SUM, | 212 | .end = IRQ_ORION5X_ETH_SUM, |
| 200 | .flags = IORESOURCE_IRQ, | 213 | .flags = IORESOURCE_IRQ, |
| 201 | } | 214 | } |
| 202 | }; | 215 | }; |
| 203 | 216 | ||
| 204 | static struct platform_device orion_eth = { | 217 | static struct platform_device orion5x_eth = { |
| 205 | .name = MV643XX_ETH_NAME, | 218 | .name = MV643XX_ETH_NAME, |
| 206 | .id = 0, | 219 | .id = 0, |
| 207 | .num_resources = 1, | 220 | .num_resources = 1, |
| 208 | .resource = orion_eth_resources, | 221 | .resource = orion5x_eth_resources, |
| 209 | }; | 222 | }; |
| 210 | 223 | ||
| 211 | void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data) | 224 | void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) |
| 212 | { | 225 | { |
| 213 | orion_eth.dev.platform_data = eth_data; | 226 | orion5x_eth.dev.platform_data = eth_data; |
| 214 | platform_device_register(&orion_eth_shared); | 227 | platform_device_register(&orion5x_eth_shared); |
| 215 | platform_device_register(&orion_eth); | 228 | platform_device_register(&orion5x_eth); |
| 216 | } | 229 | } |
| 217 | 230 | ||
| 218 | /***************************************************************************** | 231 | /***************************************************************************** |
| @@ -220,13 +233,13 @@ void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data) | |||
| 220 | * (The Orion and Discovery (MV643xx) families share the same I2C controller) | 233 | * (The Orion and Discovery (MV643xx) families share the same I2C controller) |
| 221 | ****************************************************************************/ | 234 | ****************************************************************************/ |
| 222 | 235 | ||
| 223 | static struct mv64xxx_i2c_pdata orion_i2c_pdata = { | 236 | static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { |
| 224 | .freq_m = 8, /* assumes 166 MHz TCLK */ | 237 | .freq_m = 8, /* assumes 166 MHz TCLK */ |
| 225 | .freq_n = 3, | 238 | .freq_n = 3, |
| 226 | .timeout = 1000, /* Default timeout of 1 second */ | 239 | .timeout = 1000, /* Default timeout of 1 second */ |
| 227 | }; | 240 | }; |
| 228 | 241 | ||
| 229 | static struct resource orion_i2c_resources[] = { | 242 | static struct resource orion5x_i2c_resources[] = { |
| 230 | { | 243 | { |
| 231 | .name = "i2c base", | 244 | .name = "i2c base", |
| 232 | .start = I2C_PHYS_BASE, | 245 | .start = I2C_PHYS_BASE, |
| @@ -235,66 +248,80 @@ static struct resource orion_i2c_resources[] = { | |||
| 235 | }, | 248 | }, |
| 236 | { | 249 | { |
| 237 | .name = "i2c irq", | 250 | .name = "i2c irq", |
| 238 | .start = IRQ_ORION_I2C, | 251 | .start = IRQ_ORION5X_I2C, |
| 239 | .end = IRQ_ORION_I2C, | 252 | .end = IRQ_ORION5X_I2C, |
| 240 | .flags = IORESOURCE_IRQ, | 253 | .flags = IORESOURCE_IRQ, |
| 241 | }, | 254 | }, |
| 242 | }; | 255 | }; |
| 243 | 256 | ||
| 244 | static struct platform_device orion_i2c = { | 257 | static struct platform_device orion5x_i2c = { |
| 245 | .name = MV64XXX_I2C_CTLR_NAME, | 258 | .name = MV64XXX_I2C_CTLR_NAME, |
| 246 | .id = 0, | 259 | .id = 0, |
| 247 | .num_resources = ARRAY_SIZE(orion_i2c_resources), | 260 | .num_resources = ARRAY_SIZE(orion5x_i2c_resources), |
| 248 | .resource = orion_i2c_resources, | 261 | .resource = orion5x_i2c_resources, |
| 249 | .dev = { | 262 | .dev = { |
| 250 | .platform_data = &orion_i2c_pdata, | 263 | .platform_data = &orion5x_i2c_pdata, |
| 251 | }, | 264 | }, |
| 252 | }; | 265 | }; |
| 253 | 266 | ||
| 254 | /***************************************************************************** | 267 | /***************************************************************************** |
| 255 | * Sata port | 268 | * Sata port |
| 256 | ****************************************************************************/ | 269 | ****************************************************************************/ |
| 257 | static struct resource orion_sata_resources[] = { | 270 | static struct resource orion5x_sata_resources[] = { |
| 258 | { | 271 | { |
| 259 | .name = "sata base", | 272 | .name = "sata base", |
| 260 | .start = ORION_SATA_PHYS_BASE, | 273 | .start = ORION5X_SATA_PHYS_BASE, |
| 261 | .end = ORION_SATA_PHYS_BASE + 0x5000 - 1, | 274 | .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, |
| 262 | .flags = IORESOURCE_MEM, | 275 | .flags = IORESOURCE_MEM, |
| 263 | }, | 276 | }, |
| 264 | { | 277 | { |
| 265 | .name = "sata irq", | 278 | .name = "sata irq", |
| 266 | .start = IRQ_ORION_SATA, | 279 | .start = IRQ_ORION5X_SATA, |
| 267 | .end = IRQ_ORION_SATA, | 280 | .end = IRQ_ORION5X_SATA, |
| 268 | .flags = IORESOURCE_IRQ, | 281 | .flags = IORESOURCE_IRQ, |
| 269 | }, | 282 | }, |
| 270 | }; | 283 | }; |
| 271 | 284 | ||
| 272 | static struct platform_device orion_sata = { | 285 | static struct platform_device orion5x_sata = { |
| 273 | .name = "sata_mv", | 286 | .name = "sata_mv", |
| 274 | .id = 0, | 287 | .id = 0, |
| 275 | .dev = { | 288 | .dev = { |
| 276 | .coherent_dma_mask = 0xffffffff, | 289 | .coherent_dma_mask = 0xffffffff, |
| 277 | }, | 290 | }, |
| 278 | .num_resources = ARRAY_SIZE(orion_sata_resources), | 291 | .num_resources = ARRAY_SIZE(orion5x_sata_resources), |
| 279 | .resource = orion_sata_resources, | 292 | .resource = orion5x_sata_resources, |
| 280 | }; | 293 | }; |
| 281 | 294 | ||
| 282 | void __init orion_sata_init(struct mv_sata_platform_data *sata_data) | 295 | void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) |
| 283 | { | 296 | { |
| 284 | orion_sata.dev.platform_data = sata_data; | 297 | sata_data->dram = &orion5x_mbus_dram_info; |
| 285 | platform_device_register(&orion_sata); | 298 | orion5x_sata.dev.platform_data = sata_data; |
| 299 | platform_device_register(&orion5x_sata); | ||
| 286 | } | 300 | } |
| 287 | 301 | ||
| 288 | /***************************************************************************** | 302 | /***************************************************************************** |
| 303 | * Time handling | ||
| 304 | ****************************************************************************/ | ||
| 305 | |||
| 306 | static void orion5x_timer_init(void) | ||
| 307 | { | ||
| 308 | orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK); | ||
| 309 | } | ||
| 310 | |||
| 311 | struct sys_timer orion5x_timer = { | ||
| 312 | .init = orion5x_timer_init, | ||
| 313 | }; | ||
| 314 | |||
| 315 | /***************************************************************************** | ||
| 289 | * General | 316 | * General |
| 290 | ****************************************************************************/ | 317 | ****************************************************************************/ |
| 291 | 318 | ||
| 292 | /* | 319 | /* |
| 293 | * Identify device ID and rev from PCIE configuration header space '0'. | 320 | * Identify device ID and rev from PCIe configuration header space '0'. |
| 294 | */ | 321 | */ |
| 295 | static void orion_id(u32 *dev, u32 *rev, char **dev_name) | 322 | static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) |
| 296 | { | 323 | { |
| 297 | orion_pcie_id(dev, rev); | 324 | orion5x_pcie_id(dev, rev); |
| 298 | 325 | ||
| 299 | if (*dev == MV88F5281_DEV_ID) { | 326 | if (*dev == MV88F5281_DEV_ID) { |
| 300 | if (*rev == MV88F5281_REV_D2) { | 327 | if (*rev == MV88F5281_REV_D2) { |
| @@ -321,33 +348,28 @@ static void orion_id(u32 *dev, u32 *rev, char **dev_name) | |||
| 321 | } | 348 | } |
| 322 | } | 349 | } |
| 323 | 350 | ||
| 324 | void __init orion_init(void) | 351 | void __init orion5x_init(void) |
| 325 | { | 352 | { |
| 326 | char *dev_name; | 353 | char *dev_name; |
| 327 | u32 dev, rev; | 354 | u32 dev, rev; |
| 328 | 355 | ||
| 329 | orion_id(&dev, &rev, &dev_name); | 356 | orion5x_id(&dev, &rev, &dev_name); |
| 330 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION_TCLK); | 357 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK); |
| 331 | 358 | ||
| 332 | /* | 359 | /* |
| 333 | * Setup Orion address map | 360 | * Setup Orion address map |
| 334 | */ | 361 | */ |
| 335 | orion_setup_cpu_wins(); | 362 | orion5x_setup_cpu_mbus_bridge(); |
| 336 | orion_setup_usb_wins(); | 363 | orion5x_setup_eth_wins(); |
| 337 | orion_setup_eth_wins(); | ||
| 338 | orion_setup_pci_wins(); | ||
| 339 | orion_setup_pcie_wins(); | ||
| 340 | if (dev == MV88F5182_DEV_ID) | ||
| 341 | orion_setup_sata_wins(); | ||
| 342 | 364 | ||
| 343 | /* | 365 | /* |
| 344 | * REgister devices | 366 | * Register devices. |
| 345 | */ | 367 | */ |
| 346 | platform_device_register(&orion_uart); | 368 | platform_device_register(&orion5x_uart); |
| 347 | platform_device_register(&orion_ehci0); | 369 | platform_device_register(&orion5x_ehci0); |
| 348 | if (dev == MV88F5182_DEV_ID) | 370 | if (dev == MV88F5182_DEV_ID) |
| 349 | platform_device_register(&orion_ehci1); | 371 | platform_device_register(&orion5x_ehci1); |
| 350 | platform_device_register(&orion_i2c); | 372 | platform_device_register(&orion5x_i2c); |
| 351 | } | 373 | } |
| 352 | 374 | ||
| 353 | /* | 375 | /* |
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h new file mode 100644 index 000000000000..14adf8d1a54a --- /dev/null +++ b/arch/arm/mach-orion5x/common.h | |||
| @@ -0,0 +1,71 @@ | |||
| 1 | #ifndef __ARCH_ORION5X_COMMON_H | ||
| 2 | #define __ARCH_ORION5X_COMMON_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Basic Orion init functions used early by machine-setup. | ||
| 6 | */ | ||
| 7 | |||
| 8 | void orion5x_map_io(void); | ||
| 9 | void orion5x_init_irq(void); | ||
| 10 | void orion5x_init(void); | ||
| 11 | extern struct sys_timer orion5x_timer; | ||
| 12 | |||
| 13 | /* | ||
| 14 | * Enumerations and functions for Orion windows mapping. Used by Orion core | ||
| 15 | * functions to map its interfaces and by the machine-setup to map its on- | ||
| 16 | * board devices. Details in /mach-orion/addr-map.c | ||
| 17 | */ | ||
| 18 | extern struct mbus_dram_target_info orion5x_mbus_dram_info; | ||
| 19 | void orion5x_setup_cpu_mbus_bridge(void); | ||
| 20 | void orion5x_setup_dev_boot_win(u32 base, u32 size); | ||
| 21 | void orion5x_setup_dev0_win(u32 base, u32 size); | ||
| 22 | void orion5x_setup_dev1_win(u32 base, u32 size); | ||
| 23 | void orion5x_setup_dev2_win(u32 base, u32 size); | ||
| 24 | void orion5x_setup_pcie_wa_win(u32 base, u32 size); | ||
| 25 | void orion5x_setup_eth_wins(void); | ||
| 26 | |||
| 27 | /* | ||
| 28 | * Shared code used internally by other Orion core functions. | ||
| 29 | * (/mach-orion/pci.c) | ||
| 30 | */ | ||
| 31 | |||
| 32 | struct pci_sys_data; | ||
| 33 | struct pci_bus; | ||
| 34 | |||
| 35 | void orion5x_pcie_id(u32 *dev, u32 *rev); | ||
| 36 | int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); | ||
| 37 | struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); | ||
| 38 | int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); | ||
| 39 | |||
| 40 | /* | ||
| 41 | * Valid GPIO pins according to MPP setup, used by machine-setup. | ||
| 42 | * (/mach-orion/gpio.c). | ||
| 43 | */ | ||
| 44 | |||
| 45 | void orion5x_gpio_set_valid_pins(u32 pins); | ||
| 46 | void gpio_display(void); /* debug */ | ||
| 47 | |||
| 48 | /* | ||
| 49 | * Pull in Orion Ethernet platform_data, used by machine-setup | ||
| 50 | */ | ||
| 51 | |||
| 52 | struct mv643xx_eth_platform_data; | ||
| 53 | |||
| 54 | void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data); | ||
| 55 | |||
| 56 | /* | ||
| 57 | * Orion Sata platform_data, used by machine-setup | ||
| 58 | */ | ||
| 59 | |||
| 60 | struct mv_sata_platform_data; | ||
| 61 | |||
| 62 | void orion5x_sata_init(struct mv_sata_platform_data *sata_data); | ||
| 63 | |||
| 64 | struct machine_desc; | ||
| 65 | struct meminfo; | ||
| 66 | struct tag; | ||
| 67 | extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, | ||
| 68 | char **, struct meminfo *); | ||
| 69 | |||
| 70 | |||
| 71 | #endif | ||
diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index 5ef44e1a2d36..83e9ad4cf190 100644 --- a/arch/arm/mach-orion/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c | |||
| @@ -1,12 +1,12 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-orion/db88f5281-setup.c | 2 | * arch/arm/mach-orion5x/db88f5281-setup.c |
| 3 | * | 3 | * |
| 4 | * Marvell Orion-2 Development Board Setup | 4 | * Marvell Orion-2 Development Board Setup |
| 5 | * | 5 | * |
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> |
| 7 | * | 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public | 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any | 9 | * License version 2. This program is licensed "as is" without any |
| 10 | * warranty of any kind, whether express or implied. | 10 | * warranty of any kind, whether express or implied. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| @@ -24,8 +24,8 @@ | |||
| 24 | #include <asm/gpio.h> | 24 | #include <asm/gpio.h> |
| 25 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
| 26 | #include <asm/mach/pci.h> | 26 | #include <asm/mach/pci.h> |
| 27 | #include <asm/arch/orion.h> | 27 | #include <asm/arch/orion5x.h> |
| 28 | #include <asm/arch/platform.h> | 28 | #include <asm/plat-orion/orion_nand.h> |
| 29 | #include "common.h" | 29 | #include "common.h" |
| 30 | 30 | ||
| 31 | /***************************************************************************** | 31 | /***************************************************************************** |
| @@ -241,14 +241,17 @@ void __init db88f5281_pci_preinit(void) | |||
| 241 | 241 | ||
| 242 | static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 242 | static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
| 243 | { | 243 | { |
| 244 | int irq; | ||
| 245 | |||
| 244 | /* | 246 | /* |
| 245 | * PCIE IRQ is connected internally (not GPIO) | 247 | * Check for devices with hard-wired IRQs. |
| 246 | */ | 248 | */ |
| 247 | if (dev->bus->number == orion_pcie_local_bus_nr()) | 249 | irq = orion5x_pci_map_irq(dev, slot, pin); |
| 248 | return IRQ_ORION_PCIE0_INT; | 250 | if (irq != -1) |
| 251 | return irq; | ||
| 249 | 252 | ||
| 250 | /* | 253 | /* |
| 251 | * PCI IRQs are connected via GPIOs | 254 | * PCI IRQs are connected via GPIOs. |
| 252 | */ | 255 | */ |
| 253 | switch (slot - DB88F5281_PCI_SLOT0_OFFS) { | 256 | switch (slot - DB88F5281_PCI_SLOT0_OFFS) { |
| 254 | case 0: | 257 | case 0: |
| @@ -265,8 +268,8 @@ static struct hw_pci db88f5281_pci __initdata = { | |||
| 265 | .nr_controllers = 2, | 268 | .nr_controllers = 2, |
| 266 | .preinit = db88f5281_pci_preinit, | 269 | .preinit = db88f5281_pci_preinit, |
| 267 | .swizzle = pci_std_swizzle, | 270 | .swizzle = pci_std_swizzle, |
| 268 | .setup = orion_pci_sys_setup, | 271 | .setup = orion5x_pci_sys_setup, |
| 269 | .scan = orion_pci_sys_scan_bus, | 272 | .scan = orion5x_pci_sys_scan_bus, |
| 270 | .map_irq = db88f5281_pci_map_irq, | 273 | .map_irq = db88f5281_pci_map_irq, |
| 271 | }; | 274 | }; |
| 272 | 275 | ||
| @@ -312,19 +315,16 @@ static void __init db88f5281_init(void) | |||
| 312 | /* | 315 | /* |
| 313 | * Basic Orion setup. Need to be called early. | 316 | * Basic Orion setup. Need to be called early. |
| 314 | */ | 317 | */ |
| 315 | orion_init(); | 318 | orion5x_init(); |
| 316 | 319 | ||
| 317 | /* | 320 | /* |
| 318 | * Setup the CPU address decode windows for our on-board devices | 321 | * Setup the CPU address decode windows for our on-board devices |
| 319 | */ | 322 | */ |
| 320 | orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE, | 323 | orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, |
| 321 | DB88F5281_NOR_BOOT_SIZE, -1); | 324 | DB88F5281_NOR_BOOT_SIZE); |
| 322 | orion_setup_cpu_win(ORION_DEV0, DB88F5281_7SEG_BASE, | 325 | orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); |
| 323 | DB88F5281_7SEG_SIZE, -1); | 326 | orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); |
| 324 | orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE, | 327 | orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); |
| 325 | DB88F5281_NOR_SIZE, -1); | ||
| 326 | orion_setup_cpu_win(ORION_DEV2, DB88F5281_NAND_BASE, | ||
| 327 | DB88F5281_NAND_SIZE, -1); | ||
| 328 | 328 | ||
| 329 | /* | 329 | /* |
| 330 | * Setup Multiplexing Pins: | 330 | * Setup Multiplexing Pins: |
| @@ -340,25 +340,25 @@ static void __init db88f5281_init(void) | |||
| 340 | * MPP18: UART1_CTS MPP19: UART1_RTS | 340 | * MPP18: UART1_CTS MPP19: UART1_RTS |
| 341 | * MPP-DEV: DEV_D[16:31] | 341 | * MPP-DEV: DEV_D[16:31] |
| 342 | */ | 342 | */ |
| 343 | orion_write(MPP_0_7_CTRL, 0x00222203); | 343 | orion5x_write(MPP_0_7_CTRL, 0x00222203); |
| 344 | orion_write(MPP_8_15_CTRL, 0x44000000); | 344 | orion5x_write(MPP_8_15_CTRL, 0x44000000); |
| 345 | orion_write(MPP_16_19_CTRL, 0); | 345 | orion5x_write(MPP_16_19_CTRL, 0); |
| 346 | orion_write(MPP_DEV_CTRL, 0); | 346 | orion5x_write(MPP_DEV_CTRL, 0); |
| 347 | 347 | ||
| 348 | orion_gpio_set_valid_pins(0x00003fc3); | 348 | orion5x_gpio_set_valid_pins(0x00003fc3); |
| 349 | 349 | ||
| 350 | platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs)); | 350 | platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs)); |
| 351 | i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); | 351 | i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); |
| 352 | orion_eth_init(&db88f5281_eth_data); | 352 | orion5x_eth_init(&db88f5281_eth_data); |
| 353 | } | 353 | } |
| 354 | 354 | ||
| 355 | MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") | 355 | MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") |
| 356 | /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */ | 356 | /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */ |
| 357 | .phys_io = ORION_REGS_PHYS_BASE, | 357 | .phys_io = ORION5X_REGS_PHYS_BASE, |
| 358 | .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc, | 358 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc, |
| 359 | .boot_params = 0x00000100, | 359 | .boot_params = 0x00000100, |
| 360 | .init_machine = db88f5281_init, | 360 | .init_machine = db88f5281_init, |
| 361 | .map_io = orion_map_io, | 361 | .map_io = orion5x_map_io, |
| 362 | .init_irq = orion_init_irq, | 362 | .init_irq = orion5x_init_irq, |
| 363 | .timer = &orion_timer, | 363 | .timer = &orion5x_timer, |
| 364 | MACHINE_END | 364 | MACHINE_END |
diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 076e155ad510..5bc064b8bb44 100644 --- a/arch/arm/mach-orion/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-orion/dns323-setup.c | 2 | * arch/arm/mach-orion5x/dns323-setup.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> | 4 | * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> |
| 5 | * | 5 | * |
| @@ -25,8 +25,7 @@ | |||
| 25 | #include <asm/gpio.h> | 25 | #include <asm/gpio.h> |
| 26 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
| 27 | #include <asm/mach/pci.h> | 27 | #include <asm/mach/pci.h> |
| 28 | #include <asm/arch/orion.h> | 28 | #include <asm/arch/orion5x.h> |
| 29 | #include <asm/arch/platform.h> | ||
| 30 | #include "common.h" | 29 | #include "common.h" |
| 31 | 30 | ||
| 32 | #define DNS323_GPIO_LED_RIGHT_AMBER 1 | 31 | #define DNS323_GPIO_LED_RIGHT_AMBER 1 |
| @@ -44,11 +43,16 @@ | |||
| 44 | 43 | ||
| 45 | static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 44 | static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
| 46 | { | 45 | { |
| 47 | /* PCI-E */ | 46 | int irq; |
| 48 | if (dev->bus->number == orion_pcie_local_bus_nr()) | ||
| 49 | return IRQ_ORION_PCIE0_INT; | ||
| 50 | 47 | ||
| 51 | pr_err("%s: requested mapping for unknown bus\n", __func__); | 48 | /* |
| 49 | * Check for devices with hard-wired IRQs. | ||
| 50 | */ | ||
| 51 | irq = orion5x_pci_map_irq(dev, slot, pin); | ||
| 52 | if (irq != -1) | ||
| 53 | return irq; | ||
| 54 | |||
| 55 | pr_err("%s: requested mapping for unknown device\n", __func__); | ||
| 52 | 56 | ||
| 53 | return -1; | 57 | return -1; |
| 54 | } | 58 | } |
| @@ -56,8 +60,8 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |||
| 56 | static struct hw_pci dns323_pci __initdata = { | 60 | static struct hw_pci dns323_pci __initdata = { |
| 57 | .nr_controllers = 1, | 61 | .nr_controllers = 1, |
| 58 | .swizzle = pci_std_swizzle, | 62 | .swizzle = pci_std_swizzle, |
| 59 | .setup = orion_pci_sys_setup, | 63 | .setup = orion5x_pci_sys_setup, |
| 60 | .scan = orion_pci_sys_scan_bus, | 64 | .scan = orion5x_pci_sys_scan_bus, |
| 61 | .map_irq = dns323_pci_map_irq, | 65 | .map_irq = dns323_pci_map_irq, |
| 62 | }; | 66 | }; |
| 63 | 67 | ||
| @@ -247,27 +251,25 @@ static void dns323_power_off(void) | |||
| 247 | static void __init dns323_init(void) | 251 | static void __init dns323_init(void) |
| 248 | { | 252 | { |
| 249 | /* Setup basic Orion functions. Need to be called early. */ | 253 | /* Setup basic Orion functions. Need to be called early. */ |
| 250 | orion_init(); | 254 | orion5x_init(); |
| 251 | 255 | ||
| 252 | /* setup flash mapping | 256 | /* setup flash mapping |
| 253 | * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 | 257 | * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 |
| 254 | */ | 258 | */ |
| 255 | orion_setup_cpu_win(ORION_DEV_BOOT, DNS323_NOR_BOOT_BASE, | 259 | orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); |
| 256 | DNS323_NOR_BOOT_SIZE, -1); | ||
| 257 | 260 | ||
| 258 | /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE | 261 | /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIe |
| 259 | * | 262 | * |
| 260 | * Open a special address decode windows for the PCIE WA. | 263 | * Open a special address decode windows for the PCIe WA. |
| 261 | */ | 264 | */ |
| 262 | orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); | 265 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
| 263 | orion_write(ORION_REGS_VIRT_BASE | 0x20070, | 266 | ORION5X_PCIE_WA_SIZE); |
| 264 | (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); | ||
| 265 | 267 | ||
| 266 | /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ | 268 | /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ |
| 267 | orion_write(MPP_0_7_CTRL, 0); | 269 | orion5x_write(MPP_0_7_CTRL, 0); |
| 268 | orion_write(MPP_8_15_CTRL, 0); | 270 | orion5x_write(MPP_8_15_CTRL, 0); |
| 269 | orion_write(MPP_16_19_CTRL, 0); | 271 | orion5x_write(MPP_16_19_CTRL, 0); |
| 270 | orion_write(MPP_DEV_CTRL, 0); | 272 | orion5x_write(MPP_DEV_CTRL, 0); |
| 271 | 273 | ||
| 272 | /* Define used GPIO pins | 274 | /* Define used GPIO pins |
| 273 | 275 | ||
| @@ -290,7 +292,7 @@ static void __init dns323_init(void) | |||
| 290 | | 14 | Out | //unknown// | 292 | | 14 | Out | //unknown// |
| 291 | | 15 | Out | //unknown// | 293 | | 15 | Out | //unknown// |
| 292 | */ | 294 | */ |
| 293 | orion_gpio_set_valid_pins(0x07f6); | 295 | orion5x_gpio_set_valid_pins(0x07f6); |
| 294 | 296 | ||
| 295 | /* register dns323 specific power-off method */ | 297 | /* register dns323 specific power-off method */ |
| 296 | if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0) | 298 | if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0) |
| @@ -306,18 +308,18 @@ static void __init dns323_init(void) | |||
| 306 | i2c_register_board_info(0, dns323_i2c_devices, | 308 | i2c_register_board_info(0, dns323_i2c_devices, |
| 307 | ARRAY_SIZE(dns323_i2c_devices)); | 309 | ARRAY_SIZE(dns323_i2c_devices)); |
| 308 | 310 | ||
| 309 | orion_eth_init(&dns323_eth_data); | 311 | orion5x_eth_init(&dns323_eth_data); |
| 310 | } | 312 | } |
| 311 | 313 | ||
| 312 | /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ | 314 | /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ |
| 313 | MACHINE_START(DNS323, "D-Link DNS-323") | 315 | MACHINE_START(DNS323, "D-Link DNS-323") |
| 314 | /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ | 316 | /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ |
| 315 | .phys_io = ORION_REGS_PHYS_BASE, | 317 | .phys_io = ORION5X_REGS_PHYS_BASE, |
| 316 | .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, | 318 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, |
| 317 | .boot_params = 0x00000100, | 319 | .boot_params = 0x00000100, |
| 318 | .init_machine = dns323_init, | 320 | .init_machine = dns323_init, |
| 319 | .map_io = orion_map_io, | 321 | .map_io = orion5x_map_io, |
| 320 | .init_irq = orion_init_irq, | 322 | .init_irq = orion5x_init_irq, |
| 321 | .timer = &orion_timer, | 323 | .timer = &orion5x_timer, |
| 322 | .fixup = tag_fixup_mem32, | 324 | .fixup = tag_fixup_mem32, |
| 323 | MACHINE_END | 325 | MACHINE_END |
diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion5x/gpio.c index f713818c66a3..8108c316c426 100644 --- a/arch/arm/mach-orion/gpio.c +++ b/arch/arm/mach-orion5x/gpio.c | |||
| @@ -1,12 +1,12 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-orion/gpio.c | 2 | * arch/arm/mach-orion5x/gpio.c |
| 3 | * | 3 | * |
| 4 | * GPIO functions for Marvell Orion System On Chip | 4 | * GPIO functions for Marvell Orion System On Chip |
| 5 | * | 5 | * |
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> |
| 7 | * | 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public | 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any | 9 | * License version 2. This program is licensed "as is" without any |
| 10 | * warranty of any kind, whether express or implied. | 10 | * warranty of any kind, whether express or implied. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| @@ -16,14 +16,15 @@ | |||
| 16 | #include <linux/spinlock.h> | 16 | #include <linux/spinlock.h> |
| 17 | #include <linux/bitops.h> | 17 | #include <linux/bitops.h> |
| 18 | #include <asm/gpio.h> | 18 | #include <asm/gpio.h> |
| 19 | #include <asm/arch/orion.h> | 19 | #include <asm/io.h> |
| 20 | #include <asm/arch/orion5x.h> | ||
| 20 | #include "common.h" | 21 | #include "common.h" |
| 21 | 22 | ||
| 22 | static DEFINE_SPINLOCK(gpio_lock); | 23 | static DEFINE_SPINLOCK(gpio_lock); |
| 23 | static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; | 24 | static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; |
| 24 | static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ | 25 | static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ |
| 25 | 26 | ||
| 26 | void __init orion_gpio_set_valid_pins(u32 pins) | 27 | void __init orion5x_gpio_set_valid_pins(u32 pins) |
| 27 | { | 28 | { |
| 28 | gpio_valid[0] = pins; | 29 | gpio_valid[0] = pins; |
| 29 | } | 30 | } |
| @@ -49,7 +50,7 @@ int gpio_direction_input(unsigned pin) | |||
| 49 | if (!gpio_label[pin]) | 50 | if (!gpio_label[pin]) |
| 50 | gpio_label[pin] = "?"; | 51 | gpio_label[pin] = "?"; |
| 51 | 52 | ||
| 52 | orion_setbits(GPIO_IO_CONF, 1 << pin); | 53 | orion5x_setbits(GPIO_IO_CONF, 1 << pin); |
| 53 | 54 | ||
| 54 | spin_unlock_irqrestore(&gpio_lock, flags); | 55 | spin_unlock_irqrestore(&gpio_lock, flags); |
| 55 | return 0; | 56 | return 0; |
| @@ -76,12 +77,12 @@ int gpio_direction_output(unsigned pin, int value) | |||
| 76 | gpio_label[pin] = "?"; | 77 | gpio_label[pin] = "?"; |
| 77 | 78 | ||
| 78 | mask = 1 << pin; | 79 | mask = 1 << pin; |
| 79 | orion_clrbits(GPIO_BLINK_EN, mask); | 80 | orion5x_clrbits(GPIO_BLINK_EN, mask); |
| 80 | if (value) | 81 | if (value) |
| 81 | orion_setbits(GPIO_OUT, mask); | 82 | orion5x_setbits(GPIO_OUT, mask); |
| 82 | else | 83 | else |
| 83 | orion_clrbits(GPIO_OUT, mask); | 84 | orion5x_clrbits(GPIO_OUT, mask); |
| 84 | orion_clrbits(GPIO_IO_CONF, mask); | 85 | orion5x_clrbits(GPIO_IO_CONF, mask); |
| 85 | 86 | ||
| 86 | spin_unlock_irqrestore(&gpio_lock, flags); | 87 | spin_unlock_irqrestore(&gpio_lock, flags); |
| 87 | return 0; | 88 | return 0; |
| @@ -92,10 +93,10 @@ int gpio_get_value(unsigned pin) | |||
| 92 | { | 93 | { |
| 93 | int val, mask = 1 << pin; | 94 | int val, mask = 1 << pin; |
| 94 | 95 | ||
| 95 | if (orion_read(GPIO_IO_CONF) & mask) | 96 | if (orion5x_read(GPIO_IO_CONF) & mask) |
| 96 | val = orion_read(GPIO_DATA_IN) ^ orion_read(GPIO_IN_POL); | 97 | val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL); |
| 97 | else | 98 | else |
| 98 | val = orion_read(GPIO_OUT); | 99 | val = orion5x_read(GPIO_OUT); |
| 99 | 100 | ||
| 100 | return val & mask; | 101 | return val & mask; |
| 101 | } | 102 | } |
| @@ -108,32 +109,32 @@ void gpio_set_value(unsigned pin, int value) | |||
| 108 | 109 | ||
| 109 | spin_lock_irqsave(&gpio_lock, flags); | 110 | spin_lock_irqsave(&gpio_lock, flags); |
| 110 | 111 | ||
| 111 | orion_clrbits(GPIO_BLINK_EN, mask); | 112 | orion5x_clrbits(GPIO_BLINK_EN, mask); |
| 112 | if (value) | 113 | if (value) |
| 113 | orion_setbits(GPIO_OUT, mask); | 114 | orion5x_setbits(GPIO_OUT, mask); |
| 114 | else | 115 | else |
| 115 | orion_clrbits(GPIO_OUT, mask); | 116 | orion5x_clrbits(GPIO_OUT, mask); |
| 116 | 117 | ||
| 117 | spin_unlock_irqrestore(&gpio_lock, flags); | 118 | spin_unlock_irqrestore(&gpio_lock, flags); |
| 118 | } | 119 | } |
| 119 | EXPORT_SYMBOL(gpio_set_value); | 120 | EXPORT_SYMBOL(gpio_set_value); |
| 120 | 121 | ||
| 121 | void orion_gpio_set_blink(unsigned pin, int blink) | 122 | void orion5x_gpio_set_blink(unsigned pin, int blink) |
| 122 | { | 123 | { |
| 123 | unsigned long flags; | 124 | unsigned long flags; |
| 124 | int mask = 1 << pin; | 125 | int mask = 1 << pin; |
| 125 | 126 | ||
| 126 | spin_lock_irqsave(&gpio_lock, flags); | 127 | spin_lock_irqsave(&gpio_lock, flags); |
| 127 | 128 | ||
| 128 | orion_clrbits(GPIO_OUT, mask); | 129 | orion5x_clrbits(GPIO_OUT, mask); |
| 129 | if (blink) | 130 | if (blink) |
| 130 | orion_setbits(GPIO_BLINK_EN, mask); | 131 | orion5x_setbits(GPIO_BLINK_EN, mask); |
| 131 | else | 132 | else |
| 132 | orion_clrbits(GPIO_BLINK_EN, mask); | 133 | orion5x_clrbits(GPIO_BLINK_EN, mask); |
| 133 | 134 | ||
| 134 | spin_unlock_irqrestore(&gpio_lock, flags); | 135 | spin_unlock_irqrestore(&gpio_lock, flags); |
| 135 | } | 136 | } |
| 136 | EXPORT_SYMBOL(orion_gpio_set_blink); | 137 | EXPORT_SYMBOL(orion5x_gpio_set_blink); |
| 137 | 138 | ||
| 138 | int gpio_request(unsigned pin, const char *label) | 139 | int gpio_request(unsigned pin, const char *label) |
| 139 | { | 140 | { |
| @@ -187,39 +188,39 @@ void gpio_display(void) | |||
| 187 | printk("GPIO, free\n"); | 188 | printk("GPIO, free\n"); |
| 188 | } else { | 189 | } else { |
| 189 | printk("GPIO, used by %s, ", gpio_label[i]); | 190 | printk("GPIO, used by %s, ", gpio_label[i]); |
| 190 | if (orion_read(GPIO_IO_CONF) & (1 << i)) { | 191 | if (orion5x_read(GPIO_IO_CONF) & (1 << i)) { |
| 191 | printk("input, active %s, level %s, edge %s\n", | 192 | printk("input, active %s, level %s, edge %s\n", |
| 192 | ((orion_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", | 193 | ((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", |
| 193 | ((orion_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", | 194 | ((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", |
| 194 | ((orion_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); | 195 | ((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); |
| 195 | } else { | 196 | } else { |
| 196 | printk("output, val=%d\n", (orion_read(GPIO_OUT) >> i) & 1); | 197 | printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1); |
| 197 | } | 198 | } |
| 198 | } | 199 | } |
| 199 | } | 200 | } |
| 200 | 201 | ||
| 201 | printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", | 202 | printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", |
| 202 | MPP_0_7_CTRL, orion_read(MPP_0_7_CTRL)); | 203 | MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL)); |
| 203 | printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", | 204 | printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", |
| 204 | MPP_8_15_CTRL, orion_read(MPP_8_15_CTRL)); | 205 | MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL)); |
| 205 | printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", | 206 | printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", |
| 206 | MPP_16_19_CTRL, orion_read(MPP_16_19_CTRL)); | 207 | MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL)); |
| 207 | printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", | 208 | printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", |
| 208 | MPP_DEV_CTRL, orion_read(MPP_DEV_CTRL)); | 209 | MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL)); |
| 209 | printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", | 210 | printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", |
| 210 | GPIO_OUT, orion_read(GPIO_OUT)); | 211 | GPIO_OUT, orion5x_read(GPIO_OUT)); |
| 211 | printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", | 212 | printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", |
| 212 | GPIO_IO_CONF, orion_read(GPIO_IO_CONF)); | 213 | GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF)); |
| 213 | printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", | 214 | printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", |
| 214 | GPIO_BLINK_EN, orion_read(GPIO_BLINK_EN)); | 215 | GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN)); |
| 215 | printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", | 216 | printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", |
| 216 | GPIO_IN_POL, orion_read(GPIO_IN_POL)); | 217 | GPIO_IN_POL, orion5x_read(GPIO_IN_POL)); |
| 217 | printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", | 218 | printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", |
| 218 | GPIO_DATA_IN, orion_read(GPIO_DATA_IN)); | 219 | GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN)); |
| 219 | printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", | 220 | printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", |
| 220 | GPIO_LEVEL_MASK, orion_read(GPIO_LEVEL_MASK)); | 221 | GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK)); |
| 221 | printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", | 222 | printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", |
| 222 | GPIO_EDGE_CAUSE, orion_read(GPIO_EDGE_CAUSE)); | 223 | GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE)); |
| 223 | printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", | 224 | printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", |
| 224 | GPIO_EDGE_MASK, orion_read(GPIO_EDGE_MASK)); | 225 | GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK)); |
| 225 | } | 226 | } |
diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion5x/irq.c index df7e12ad378b..dd21f38c5d37 100644 --- a/arch/arm/mach-orion/irq.c +++ b/arch/arm/mach-orion5x/irq.c | |||
| @@ -1,12 +1,12 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-orion/irq.c | 2 | * arch/arm/mach-orion5x/irq.c |
| 3 | * | 3 | * |
| 4 | * Core IRQ functions for Marvell Orion System On Chip | 4 | * Core IRQ functions for Marvell Orion System On Chip |
| 5 | * | 5 | * |
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> |
| 7 | * | 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public | 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any | 9 | * License version 2. This program is licensed "as is" without any |
| 10 | * warranty of any kind, whether express or implied. | 10 | * warranty of any kind, whether express or implied. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| @@ -14,7 +14,9 @@ | |||
| 14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
| 15 | #include <linux/irq.h> | 15 | #include <linux/irq.h> |
| 16 | #include <asm/gpio.h> | 16 | #include <asm/gpio.h> |
| 17 | #include <asm/arch/orion.h> | 17 | #include <asm/io.h> |
| 18 | #include <asm/arch/orion5x.h> | ||
| 19 | #include <asm/plat-orion/irq.h> | ||
| 18 | #include "common.h" | 20 | #include "common.h" |
| 19 | 21 | ||
| 20 | /***************************************************************************** | 22 | /***************************************************************************** |
| @@ -42,46 +44,46 @@ | |||
| 42 | * polarity LEVEL mask | 44 | * polarity LEVEL mask |
| 43 | * | 45 | * |
| 44 | ****************************************************************************/ | 46 | ****************************************************************************/ |
| 45 | static void orion_gpio_irq_ack(u32 irq) | 47 | static void orion5x_gpio_irq_ack(u32 irq) |
| 46 | { | 48 | { |
| 47 | int pin = irq_to_gpio(irq); | 49 | int pin = irq_to_gpio(irq); |
| 48 | if (irq_desc[irq].status & IRQ_LEVEL) | 50 | if (irq_desc[irq].status & IRQ_LEVEL) |
| 49 | /* | 51 | /* |
| 50 | * Mask bit for level interrupt | 52 | * Mask bit for level interrupt |
| 51 | */ | 53 | */ |
| 52 | orion_clrbits(GPIO_LEVEL_MASK, 1 << pin); | 54 | orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin); |
| 53 | else | 55 | else |
| 54 | /* | 56 | /* |
| 55 | * Clear casue bit for egde interrupt | 57 | * Clear casue bit for egde interrupt |
| 56 | */ | 58 | */ |
| 57 | orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin); | 59 | orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin); |
| 58 | } | 60 | } |
| 59 | 61 | ||
| 60 | static void orion_gpio_irq_mask(u32 irq) | 62 | static void orion5x_gpio_irq_mask(u32 irq) |
| 61 | { | 63 | { |
| 62 | int pin = irq_to_gpio(irq); | 64 | int pin = irq_to_gpio(irq); |
| 63 | if (irq_desc[irq].status & IRQ_LEVEL) | 65 | if (irq_desc[irq].status & IRQ_LEVEL) |
| 64 | orion_clrbits(GPIO_LEVEL_MASK, 1 << pin); | 66 | orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin); |
| 65 | else | 67 | else |
| 66 | orion_clrbits(GPIO_EDGE_MASK, 1 << pin); | 68 | orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin); |
| 67 | } | 69 | } |
| 68 | 70 | ||
| 69 | static void orion_gpio_irq_unmask(u32 irq) | 71 | static void orion5x_gpio_irq_unmask(u32 irq) |
| 70 | { | 72 | { |
| 71 | int pin = irq_to_gpio(irq); | 73 | int pin = irq_to_gpio(irq); |
| 72 | if (irq_desc[irq].status & IRQ_LEVEL) | 74 | if (irq_desc[irq].status & IRQ_LEVEL) |
| 73 | orion_setbits(GPIO_LEVEL_MASK, 1 << pin); | 75 | orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin); |
| 74 | else | 76 | else |
| 75 | orion_setbits(GPIO_EDGE_MASK, 1 << pin); | 77 | orion5x_setbits(GPIO_EDGE_MASK, 1 << pin); |
| 76 | } | 78 | } |
| 77 | 79 | ||
| 78 | static int orion_gpio_set_irq_type(u32 irq, u32 type) | 80 | static int orion5x_gpio_set_irq_type(u32 irq, u32 type) |
| 79 | { | 81 | { |
| 80 | int pin = irq_to_gpio(irq); | 82 | int pin = irq_to_gpio(irq); |
| 81 | struct irq_desc *desc; | 83 | struct irq_desc *desc; |
| 82 | 84 | ||
| 83 | if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) { | 85 | if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) { |
| 84 | printk(KERN_ERR "orion_gpio_set_irq_type failed " | 86 | printk(KERN_ERR "orion5x_gpio_set_irq_type failed " |
| 85 | "(irq %d, pin %d).\n", irq, pin); | 87 | "(irq %d, pin %d).\n", irq, pin); |
| 86 | return -EINVAL; | 88 | return -EINVAL; |
| 87 | } | 89 | } |
| @@ -92,22 +94,22 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type) | |||
| 92 | case IRQT_HIGH: | 94 | case IRQT_HIGH: |
| 93 | desc->handle_irq = handle_level_irq; | 95 | desc->handle_irq = handle_level_irq; |
| 94 | desc->status |= IRQ_LEVEL; | 96 | desc->status |= IRQ_LEVEL; |
| 95 | orion_clrbits(GPIO_IN_POL, (1 << pin)); | 97 | orion5x_clrbits(GPIO_IN_POL, (1 << pin)); |
| 96 | break; | 98 | break; |
| 97 | case IRQT_LOW: | 99 | case IRQT_LOW: |
| 98 | desc->handle_irq = handle_level_irq; | 100 | desc->handle_irq = handle_level_irq; |
| 99 | desc->status |= IRQ_LEVEL; | 101 | desc->status |= IRQ_LEVEL; |
| 100 | orion_setbits(GPIO_IN_POL, (1 << pin)); | 102 | orion5x_setbits(GPIO_IN_POL, (1 << pin)); |
| 101 | break; | 103 | break; |
| 102 | case IRQT_RISING: | 104 | case IRQT_RISING: |
| 103 | desc->handle_irq = handle_edge_irq; | 105 | desc->handle_irq = handle_edge_irq; |
| 104 | desc->status &= ~IRQ_LEVEL; | 106 | desc->status &= ~IRQ_LEVEL; |
| 105 | orion_clrbits(GPIO_IN_POL, (1 << pin)); | 107 | orion5x_clrbits(GPIO_IN_POL, (1 << pin)); |
| 106 | break; | 108 | break; |
| 107 | case IRQT_FALLING: | 109 | case IRQT_FALLING: |
| 108 | desc->handle_irq = handle_edge_irq; | 110 | desc->handle_irq = handle_edge_irq; |
| 109 | desc->status &= ~IRQ_LEVEL; | 111 | desc->status &= ~IRQ_LEVEL; |
| 110 | orion_setbits(GPIO_IN_POL, (1 << pin)); | 112 | orion5x_setbits(GPIO_IN_POL, (1 << pin)); |
| 111 | break; | 113 | break; |
| 112 | case IRQT_BOTHEDGE: | 114 | case IRQT_BOTHEDGE: |
| 113 | desc->handle_irq = handle_edge_irq; | 115 | desc->handle_irq = handle_edge_irq; |
| @@ -115,11 +117,11 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type) | |||
| 115 | /* | 117 | /* |
| 116 | * set initial polarity based on current input level | 118 | * set initial polarity based on current input level |
| 117 | */ | 119 | */ |
| 118 | if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN)) | 120 | if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN)) |
| 119 | & (1 << pin)) | 121 | & (1 << pin)) |
| 120 | orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ | 122 | orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ |
| 121 | else | 123 | else |
| 122 | orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ | 124 | orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ |
| 123 | 125 | ||
| 124 | break; | 126 | break; |
| 125 | default: | 127 | default: |
| @@ -133,22 +135,22 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type) | |||
| 133 | return 0; | 135 | return 0; |
| 134 | } | 136 | } |
| 135 | 137 | ||
| 136 | static struct irq_chip orion_gpio_irq_chip = { | 138 | static struct irq_chip orion5x_gpio_irq_chip = { |
| 137 | .name = "Orion-IRQ-GPIO", | 139 | .name = "Orion-IRQ-GPIO", |
| 138 | .ack = orion_gpio_irq_ack, | 140 | .ack = orion5x_gpio_irq_ack, |
| 139 | .mask = orion_gpio_irq_mask, | 141 | .mask = orion5x_gpio_irq_mask, |
| 140 | .unmask = orion_gpio_irq_unmask, | 142 | .unmask = orion5x_gpio_irq_unmask, |
| 141 | .set_type = orion_gpio_set_irq_type, | 143 | .set_type = orion5x_gpio_set_irq_type, |
| 142 | }; | 144 | }; |
| 143 | 145 | ||
| 144 | static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | 146 | static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
| 145 | { | 147 | { |
| 146 | u32 cause, offs, pin; | 148 | u32 cause, offs, pin; |
| 147 | 149 | ||
| 148 | BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31); | 150 | BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); |
| 149 | offs = (irq - IRQ_ORION_GPIO_0_7) * 8; | 151 | offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8; |
| 150 | cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) | | 152 | cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) | |
| 151 | (orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK)); | 153 | (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK)); |
| 152 | 154 | ||
| 153 | for (pin = offs; pin < offs + 8; pin++) { | 155 | for (pin = offs; pin < offs + 8; pin++) { |
| 154 | if (cause & (1 << pin)) { | 156 | if (cause & (1 << pin)) { |
| @@ -156,16 +158,16 @@ static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
| 156 | desc = irq_desc + irq; | 158 | desc = irq_desc + irq; |
| 157 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { | 159 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { |
| 158 | /* Swap polarity (race with GPIO line) */ | 160 | /* Swap polarity (race with GPIO line) */ |
| 159 | u32 polarity = orion_read(GPIO_IN_POL); | 161 | u32 polarity = orion5x_read(GPIO_IN_POL); |
| 160 | polarity ^= 1 << pin; | 162 | polarity ^= 1 << pin; |
| 161 | orion_write(GPIO_IN_POL, polarity); | 163 | orion5x_write(GPIO_IN_POL, polarity); |
| 162 | } | 164 | } |
| 163 | desc_handle_irq(irq, desc); | 165 | desc_handle_irq(irq, desc); |
| 164 | } | 166 | } |
| 165 | } | 167 | } |
| 166 | } | 168 | } |
| 167 | 169 | ||
| 168 | static void __init orion_init_gpio_irq(void) | 170 | static void __init orion5x_init_gpio_irq(void) |
| 169 | { | 171 | { |
| 170 | int i; | 172 | int i; |
| 171 | struct irq_desc *desc; | 173 | struct irq_desc *desc; |
| @@ -173,69 +175,37 @@ static void __init orion_init_gpio_irq(void) | |||
| 173 | /* | 175 | /* |
| 174 | * Mask and clear GPIO IRQ interrupts | 176 | * Mask and clear GPIO IRQ interrupts |
| 175 | */ | 177 | */ |
| 176 | orion_write(GPIO_LEVEL_MASK, 0x0); | 178 | orion5x_write(GPIO_LEVEL_MASK, 0x0); |
| 177 | orion_write(GPIO_EDGE_MASK, 0x0); | 179 | orion5x_write(GPIO_EDGE_MASK, 0x0); |
| 178 | orion_write(GPIO_EDGE_CAUSE, 0x0); | 180 | orion5x_write(GPIO_EDGE_CAUSE, 0x0); |
| 179 | 181 | ||
| 180 | /* | 182 | /* |
| 181 | * Register chained level handlers for GPIO IRQs by default. | 183 | * Register chained level handlers for GPIO IRQs by default. |
| 182 | * User can use set_type() if he wants to use edge types handlers. | 184 | * User can use set_type() if he wants to use edge types handlers. |
| 183 | */ | 185 | */ |
| 184 | for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) { | 186 | for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) { |
| 185 | set_irq_chip(i, &orion_gpio_irq_chip); | 187 | set_irq_chip(i, &orion5x_gpio_irq_chip); |
| 186 | set_irq_handler(i, handle_level_irq); | 188 | set_irq_handler(i, handle_level_irq); |
| 187 | desc = irq_desc + i; | 189 | desc = irq_desc + i; |
| 188 | desc->status |= IRQ_LEVEL; | 190 | desc->status |= IRQ_LEVEL; |
| 189 | set_irq_flags(i, IRQF_VALID); | 191 | set_irq_flags(i, IRQF_VALID); |
| 190 | } | 192 | } |
| 191 | set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler); | 193 | set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler); |
| 192 | set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler); | 194 | set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler); |
| 193 | set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler); | 195 | set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler); |
| 194 | set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler); | 196 | set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler); |
| 195 | } | 197 | } |
| 196 | 198 | ||
| 197 | /***************************************************************************** | 199 | /***************************************************************************** |
| 198 | * Orion Main IRQ | 200 | * Orion Main IRQ |
| 199 | ****************************************************************************/ | 201 | ****************************************************************************/ |
| 200 | static void orion_main_irq_mask(u32 irq) | 202 | static void __init orion5x_init_main_irq(void) |
| 201 | { | 203 | { |
| 202 | orion_clrbits(MAIN_IRQ_MASK, 1 << irq); | 204 | orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); |
| 203 | } | 205 | } |
| 204 | 206 | ||
| 205 | static void orion_main_irq_unmask(u32 irq) | 207 | void __init orion5x_init_irq(void) |
| 206 | { | 208 | { |
| 207 | orion_setbits(MAIN_IRQ_MASK, 1 << irq); | 209 | orion5x_init_main_irq(); |
| 208 | } | 210 | orion5x_init_gpio_irq(); |
| 209 | |||
| 210 | static struct irq_chip orion_main_irq_chip = { | ||
| 211 | .name = "Orion-IRQ-Main", | ||
| 212 | .ack = orion_main_irq_mask, | ||
| 213 | .mask = orion_main_irq_mask, | ||
| 214 | .unmask = orion_main_irq_unmask, | ||
| 215 | }; | ||
| 216 | |||
| 217 | static void __init orion_init_main_irq(void) | ||
| 218 | { | ||
| 219 | int i; | ||
| 220 | |||
| 221 | /* | ||
| 222 | * Mask and clear Main IRQ interrupts | ||
| 223 | */ | ||
| 224 | orion_write(MAIN_IRQ_MASK, 0x0); | ||
| 225 | orion_write(MAIN_IRQ_CAUSE, 0x0); | ||
| 226 | |||
| 227 | /* | ||
| 228 | * Register level handler for Main IRQs | ||
| 229 | */ | ||
| 230 | for (i = 0; i < IRQ_ORION_GPIO_START; i++) { | ||
| 231 | set_irq_chip(i, &orion_main_irq_chip); | ||
| 232 | set_irq_handler(i, handle_level_irq); | ||
| 233 | set_irq_flags(i, IRQF_VALID); | ||
| 234 | } | ||
| 235 | } | ||
| 236 | |||
| 237 | void __init orion_init_irq(void) | ||
| 238 | { | ||
| 239 | orion_init_main_irq(); | ||
| 240 | orion_init_gpio_irq(); | ||
| 241 | } | 211 | } |
diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index 785a07bdf1e2..36760c6e54c0 100644 --- a/arch/arm/mach-orion/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c | |||
| @@ -1,10 +1,10 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-orion/kurobox_pro-setup.c | 2 | * arch/arm/mach-orion5x/kurobox_pro-setup.c |
| 3 | * | 3 | * |
| 4 | * Maintainer: Ronen Shitrit <rshitrit@marvell.com> | 4 | * Maintainer: Ronen Shitrit <rshitrit@marvell.com> |
| 5 | * | 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public | 6 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without any | 7 | * License version 2. This program is licensed "as is" without any |
| 8 | * warranty of any kind, whether express or implied. | 8 | * warranty of any kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| @@ -22,8 +22,8 @@ | |||
| 22 | #include <asm/gpio.h> | 22 | #include <asm/gpio.h> |
| 23 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 24 | #include <asm/mach/pci.h> | 24 | #include <asm/mach/pci.h> |
| 25 | #include <asm/arch/orion.h> | 25 | #include <asm/arch/orion5x.h> |
| 26 | #include <asm/arch/platform.h> | 26 | #include <asm/plat-orion/orion_nand.h> |
| 27 | #include "common.h" | 27 | #include "common.h" |
| 28 | 28 | ||
| 29 | /***************************************************************************** | 29 | /***************************************************************************** |
| @@ -120,13 +120,19 @@ static struct platform_device kurobox_pro_nor_flash = { | |||
| 120 | 120 | ||
| 121 | static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 121 | static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
| 122 | { | 122 | { |
| 123 | int irq; | ||
| 124 | |||
| 125 | /* | ||
| 126 | * Check for devices with hard-wired IRQs. | ||
| 127 | */ | ||
| 128 | irq = orion5x_pci_map_irq(dev, slot, pin); | ||
| 129 | if (irq != -1) | ||
| 130 | return irq; | ||
| 131 | |||
| 123 | /* | 132 | /* |
| 124 | * PCI isn't used on the Kuro | 133 | * PCI isn't used on the Kuro |
| 125 | */ | 134 | */ |
| 126 | if (dev->bus->number == orion_pcie_local_bus_nr()) | 135 | printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n"); |
| 127 | return IRQ_ORION_PCIE0_INT; | ||
| 128 | else | ||
| 129 | printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n"); | ||
| 130 | 136 | ||
| 131 | return -1; | 137 | return -1; |
| 132 | } | 138 | } |
| @@ -134,8 +140,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |||
| 134 | static struct hw_pci kurobox_pro_pci __initdata = { | 140 | static struct hw_pci kurobox_pro_pci __initdata = { |
| 135 | .nr_controllers = 1, | 141 | .nr_controllers = 1, |
| 136 | .swizzle = pci_std_swizzle, | 142 | .swizzle = pci_std_swizzle, |
| 137 | .setup = orion_pci_sys_setup, | 143 | .setup = orion5x_pci_sys_setup, |
| 138 | .scan = orion_pci_sys_scan_bus, | 144 | .scan = orion5x_pci_sys_scan_bus, |
| 139 | .map_irq = kurobox_pro_pci_map_irq, | 145 | .map_irq = kurobox_pro_pci_map_irq, |
| 140 | }; | 146 | }; |
| 141 | 147 | ||
| @@ -178,31 +184,25 @@ static struct mv_sata_platform_data kurobox_pro_sata_data = { | |||
| 178 | * General Setup | 184 | * General Setup |
| 179 | ****************************************************************************/ | 185 | ****************************************************************************/ |
| 180 | 186 | ||
| 181 | static struct platform_device *kurobox_pro_devices[] __initdata = { | ||
| 182 | &kurobox_pro_nor_flash, | ||
| 183 | &kurobox_pro_nand_flash, | ||
| 184 | }; | ||
| 185 | |||
| 186 | static void __init kurobox_pro_init(void) | 187 | static void __init kurobox_pro_init(void) |
| 187 | { | 188 | { |
| 188 | /* | 189 | /* |
| 189 | * Setup basic Orion functions. Need to be called early. | 190 | * Setup basic Orion functions. Need to be called early. |
| 190 | */ | 191 | */ |
| 191 | orion_init(); | 192 | orion5x_init(); |
| 192 | 193 | ||
| 193 | /* | 194 | /* |
| 194 | * Setup the CPU address decode windows for our devices | 195 | * Setup the CPU address decode windows for our devices |
| 195 | */ | 196 | */ |
| 196 | orion_setup_cpu_win(ORION_DEV_BOOT, KUROBOX_PRO_NOR_BOOT_BASE, | 197 | orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, |
| 197 | KUROBOX_PRO_NOR_BOOT_SIZE, -1); | 198 | KUROBOX_PRO_NOR_BOOT_SIZE); |
| 198 | orion_setup_cpu_win(ORION_DEV0, KUROBOX_PRO_NAND_BASE, | 199 | orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); |
| 199 | KUROBOX_PRO_NAND_SIZE, -1); | 200 | |
| 200 | /* | 201 | /* |
| 201 | * Open a special address decode windows for the PCIE WA. | 202 | * Open a special address decode windows for the PCIe WA. |
| 202 | */ | 203 | */ |
| 203 | orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); | 204 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
| 204 | orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | | 205 | ORION5X_PCIE_WA_SIZE); |
| 205 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); | ||
| 206 | 206 | ||
| 207 | /* | 207 | /* |
| 208 | * Setup Multiplexing Pins -- | 208 | * Setup Multiplexing Pins -- |
| @@ -219,26 +219,44 @@ static void __init kurobox_pro_init(void) | |||
| 219 | * MPP[15] SATA 1 active indication | 219 | * MPP[15] SATA 1 active indication |
| 220 | * MPP[16-19] Not used | 220 | * MPP[16-19] Not used |
| 221 | */ | 221 | */ |
| 222 | orion_write(MPP_0_7_CTRL, 0x44220003); | 222 | orion5x_write(MPP_0_7_CTRL, 0x44220003); |
| 223 | orion_write(MPP_8_15_CTRL, 0x55550000); | 223 | orion5x_write(MPP_8_15_CTRL, 0x55550000); |
| 224 | orion_write(MPP_16_19_CTRL, 0x0); | 224 | orion5x_write(MPP_16_19_CTRL, 0x0); |
| 225 | 225 | ||
| 226 | orion_gpio_set_valid_pins(0x0000000c); | 226 | orion5x_gpio_set_valid_pins(0x0000000c); |
| 227 | 227 | ||
| 228 | platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices)); | 228 | platform_device_register(&kurobox_pro_nor_flash); |
| 229 | if (machine_is_kurobox_pro()) | ||
| 230 | platform_device_register(&kurobox_pro_nand_flash); | ||
| 229 | i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); | 231 | i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); |
| 230 | orion_eth_init(&kurobox_pro_eth_data); | 232 | orion5x_eth_init(&kurobox_pro_eth_data); |
| 231 | orion_sata_init(&kurobox_pro_sata_data); | 233 | orion5x_sata_init(&kurobox_pro_sata_data); |
| 232 | } | 234 | } |
| 233 | 235 | ||
| 236 | #ifdef CONFIG_MACH_KUROBOX_PRO | ||
| 234 | MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") | 237 | MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") |
| 235 | /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ | 238 | /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ |
| 236 | .phys_io = ORION_REGS_PHYS_BASE, | 239 | .phys_io = ORION5X_REGS_PHYS_BASE, |
| 237 | .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, | 240 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, |
| 241 | .boot_params = 0x00000100, | ||
| 242 | .init_machine = kurobox_pro_init, | ||
| 243 | .map_io = orion5x_map_io, | ||
| 244 | .init_irq = orion5x_init_irq, | ||
| 245 | .timer = &orion5x_timer, | ||
| 246 | .fixup = tag_fixup_mem32, | ||
| 247 | MACHINE_END | ||
| 248 | #endif | ||
| 249 | |||
| 250 | #ifdef CONFIG_MACH_LINKSTATION_PRO | ||
| 251 | MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live") | ||
| 252 | /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ | ||
| 253 | .phys_io = ORION5X_REGS_PHYS_BASE, | ||
| 254 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, | ||
| 238 | .boot_params = 0x00000100, | 255 | .boot_params = 0x00000100, |
| 239 | .init_machine = kurobox_pro_init, | 256 | .init_machine = kurobox_pro_init, |
| 240 | .map_io = orion_map_io, | 257 | .map_io = orion5x_map_io, |
| 241 | .init_irq = orion_init_irq, | 258 | .init_irq = orion5x_init_irq, |
| 242 | .timer = &orion_timer, | 259 | .timer = &orion5x_timer, |
| 243 | .fixup = tag_fixup_mem32, | 260 | .fixup = tag_fixup_mem32, |
| 244 | MACHINE_END | 261 | MACHINE_END |
| 262 | #endif | ||
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c new file mode 100644 index 000000000000..9d5d39fa19c3 --- /dev/null +++ b/arch/arm/mach-orion5x/pci.c | |||
| @@ -0,0 +1,567 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-orion5x/pci.c | ||
| 3 | * | ||
| 4 | * PCI and PCIe functions for Marvell Orion System On Chip | ||
| 5 | * | ||
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/pci.h> | ||
| 15 | #include <linux/mbus.h> | ||
| 16 | #include <asm/mach/pci.h> | ||
| 17 | #include <asm/plat-orion/pcie.h> | ||
| 18 | #include "common.h" | ||
| 19 | |||
| 20 | /***************************************************************************** | ||
| 21 | * Orion has one PCIe controller and one PCI controller. | ||
| 22 | * | ||
| 23 | * Note1: The local PCIe bus number is '0'. The local PCI bus number | ||
| 24 | * follows the scanned PCIe bridged busses, if any. | ||
| 25 | * | ||
| 26 | * Note2: It is possible for PCI/PCIe agents to access many subsystem's | ||
| 27 | * space, by configuring BARs and Address Decode Windows, e.g. flashes on | ||
| 28 | * device bus, Orion registers, etc. However this code only enable the | ||
| 29 | * access to DDR banks. | ||
| 30 | ****************************************************************************/ | ||
| 31 | |||
| 32 | |||
| 33 | /***************************************************************************** | ||
| 34 | * PCIe controller | ||
| 35 | ****************************************************************************/ | ||
| 36 | #define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) | ||
| 37 | |||
| 38 | void __init orion5x_pcie_id(u32 *dev, u32 *rev) | ||
| 39 | { | ||
| 40 | *dev = orion_pcie_dev_id(PCIE_BASE); | ||
| 41 | *rev = orion_pcie_rev(PCIE_BASE); | ||
| 42 | } | ||
| 43 | |||
| 44 | static int pcie_valid_config(int bus, int dev) | ||
| 45 | { | ||
| 46 | /* | ||
| 47 | * Don't go out when trying to access -- | ||
| 48 | * 1. nonexisting device on local bus | ||
| 49 | * 2. where there's no device connected (no link) | ||
| 50 | */ | ||
| 51 | if (bus == 0 && dev == 0) | ||
| 52 | return 1; | ||
| 53 | |||
| 54 | if (!orion_pcie_link_up(PCIE_BASE)) | ||
| 55 | return 0; | ||
| 56 | |||
| 57 | if (bus == 0 && dev != 1) | ||
| 58 | return 0; | ||
| 59 | |||
| 60 | return 1; | ||
| 61 | } | ||
| 62 | |||
| 63 | |||
| 64 | /* | ||
| 65 | * PCIe config cycles are done by programming the PCIE_CONF_ADDR register | ||
| 66 | * and then reading the PCIE_CONF_DATA register. Need to make sure these | ||
| 67 | * transactions are atomic. | ||
| 68 | */ | ||
| 69 | static DEFINE_SPINLOCK(orion5x_pcie_lock); | ||
| 70 | |||
| 71 | static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | ||
| 72 | int size, u32 *val) | ||
| 73 | { | ||
| 74 | unsigned long flags; | ||
| 75 | int ret; | ||
| 76 | |||
| 77 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { | ||
| 78 | *val = 0xffffffff; | ||
| 79 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 80 | } | ||
| 81 | |||
| 82 | spin_lock_irqsave(&orion5x_pcie_lock, flags); | ||
| 83 | ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); | ||
| 84 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); | ||
| 85 | |||
| 86 | return ret; | ||
| 87 | } | ||
| 88 | |||
| 89 | static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, | ||
| 90 | int where, int size, u32 *val) | ||
| 91 | { | ||
| 92 | int ret; | ||
| 93 | |||
| 94 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { | ||
| 95 | *val = 0xffffffff; | ||
| 96 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 97 | } | ||
| 98 | |||
| 99 | /* | ||
| 100 | * We only support access to the non-extended configuration | ||
| 101 | * space when using the WA access method (or we would have to | ||
| 102 | * sacrifice 256M of CPU virtual address space.) | ||
| 103 | */ | ||
| 104 | if (where >= 0x100) { | ||
| 105 | *val = 0xffffffff; | ||
| 106 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 107 | } | ||
| 108 | |||
| 109 | ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, | ||
| 110 | bus, devfn, where, size, val); | ||
| 111 | |||
| 112 | return ret; | ||
| 113 | } | ||
| 114 | |||
| 115 | static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, | ||
| 116 | int where, int size, u32 val) | ||
| 117 | { | ||
| 118 | unsigned long flags; | ||
| 119 | int ret; | ||
| 120 | |||
| 121 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) | ||
| 122 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 123 | |||
| 124 | spin_lock_irqsave(&orion5x_pcie_lock, flags); | ||
| 125 | ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); | ||
| 126 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); | ||
| 127 | |||
| 128 | return ret; | ||
| 129 | } | ||
| 130 | |||
| 131 | static struct pci_ops pcie_ops = { | ||
| 132 | .read = pcie_rd_conf, | ||
| 133 | .write = pcie_wr_conf, | ||
| 134 | }; | ||
| 135 | |||
| 136 | |||
| 137 | static int __init pcie_setup(struct pci_sys_data *sys) | ||
| 138 | { | ||
| 139 | struct resource *res; | ||
| 140 | int dev; | ||
| 141 | |||
| 142 | /* | ||
| 143 | * Generic PCIe unit setup. | ||
| 144 | */ | ||
| 145 | orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); | ||
| 146 | |||
| 147 | /* | ||
| 148 | * Check whether to apply Orion-1/Orion-NAS PCIe config | ||
| 149 | * read transaction workaround. | ||
| 150 | */ | ||
| 151 | dev = orion_pcie_dev_id(PCIE_BASE); | ||
| 152 | if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { | ||
| 153 | printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " | ||
| 154 | "read transaction workaround\n"); | ||
| 155 | pcie_ops.read = pcie_rd_conf_wa; | ||
| 156 | } | ||
| 157 | |||
| 158 | /* | ||
| 159 | * Request resources. | ||
| 160 | */ | ||
| 161 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); | ||
| 162 | if (!res) | ||
| 163 | panic("pcie_setup unable to alloc resources"); | ||
| 164 | |||
| 165 | /* | ||
| 166 | * IORESOURCE_IO | ||
| 167 | */ | ||
| 168 | res[0].name = "PCIe I/O Space"; | ||
| 169 | res[0].flags = IORESOURCE_IO; | ||
| 170 | res[0].start = ORION5X_PCIE_IO_BUS_BASE; | ||
| 171 | res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; | ||
| 172 | if (request_resource(&ioport_resource, &res[0])) | ||
| 173 | panic("Request PCIe IO resource failed\n"); | ||
| 174 | sys->resource[0] = &res[0]; | ||
| 175 | |||
| 176 | /* | ||
| 177 | * IORESOURCE_MEM | ||
| 178 | */ | ||
| 179 | res[1].name = "PCIe Memory Space"; | ||
| 180 | res[1].flags = IORESOURCE_MEM; | ||
| 181 | res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; | ||
| 182 | res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; | ||
| 183 | if (request_resource(&iomem_resource, &res[1])) | ||
| 184 | panic("Request PCIe Memory resource failed\n"); | ||
| 185 | sys->resource[1] = &res[1]; | ||
| 186 | |||
| 187 | sys->resource[2] = NULL; | ||
| 188 | sys->io_offset = 0; | ||
| 189 | |||
| 190 | return 1; | ||
| 191 | } | ||
| 192 | |||
| 193 | /***************************************************************************** | ||
| 194 | * PCI controller | ||
| 195 | ****************************************************************************/ | ||
| 196 | #define PCI_MODE ORION5X_PCI_REG(0xd00) | ||
| 197 | #define PCI_CMD ORION5X_PCI_REG(0xc00) | ||
| 198 | #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) | ||
| 199 | #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) | ||
| 200 | #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) | ||
| 201 | |||
| 202 | /* | ||
| 203 | * PCI_MODE bits | ||
| 204 | */ | ||
| 205 | #define PCI_MODE_64BIT (1 << 2) | ||
| 206 | #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) | ||
| 207 | |||
| 208 | /* | ||
| 209 | * PCI_CMD bits | ||
| 210 | */ | ||
| 211 | #define PCI_CMD_HOST_REORDER (1 << 29) | ||
| 212 | |||
| 213 | /* | ||
| 214 | * PCI_P2P_CONF bits | ||
| 215 | */ | ||
| 216 | #define PCI_P2P_BUS_OFFS 16 | ||
| 217 | #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) | ||
| 218 | #define PCI_P2P_DEV_OFFS 24 | ||
| 219 | #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) | ||
| 220 | |||
| 221 | /* | ||
| 222 | * PCI_CONF_ADDR bits | ||
| 223 | */ | ||
| 224 | #define PCI_CONF_REG(reg) ((reg) & 0xfc) | ||
| 225 | #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) | ||
| 226 | #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) | ||
| 227 | #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) | ||
| 228 | #define PCI_CONF_ADDR_EN (1 << 31) | ||
| 229 | |||
| 230 | /* | ||
| 231 | * Internal configuration space | ||
| 232 | */ | ||
| 233 | #define PCI_CONF_FUNC_STAT_CMD 0 | ||
| 234 | #define PCI_CONF_REG_STAT_CMD 4 | ||
| 235 | #define PCIX_STAT 0x64 | ||
| 236 | #define PCIX_STAT_BUS_OFFS 8 | ||
| 237 | #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) | ||
| 238 | |||
| 239 | /* | ||
| 240 | * PCI Address Decode Windows registers | ||
| 241 | */ | ||
| 242 | #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ | ||
| 243 | ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ | ||
| 244 | ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ | ||
| 245 | ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) | ||
| 246 | #define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) : \ | ||
| 247 | ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ | ||
| 248 | ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ | ||
| 249 | ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) | ||
| 250 | #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) | ||
| 251 | #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) | ||
| 252 | |||
| 253 | /* | ||
| 254 | * PCI configuration helpers for BAR settings | ||
| 255 | */ | ||
| 256 | #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) | ||
| 257 | #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) | ||
| 258 | #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) | ||
| 259 | |||
| 260 | /* | ||
| 261 | * PCI config cycles are done by programming the PCI_CONF_ADDR register | ||
| 262 | * and then reading the PCI_CONF_DATA register. Need to make sure these | ||
| 263 | * transactions are atomic. | ||
| 264 | */ | ||
| 265 | static DEFINE_SPINLOCK(orion5x_pci_lock); | ||
| 266 | |||
| 267 | static int orion5x_pci_local_bus_nr(void) | ||
| 268 | { | ||
| 269 | u32 conf = orion5x_read(PCI_P2P_CONF); | ||
| 270 | return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); | ||
| 271 | } | ||
| 272 | |||
| 273 | static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, | ||
| 274 | u32 where, u32 size, u32 *val) | ||
| 275 | { | ||
| 276 | unsigned long flags; | ||
| 277 | spin_lock_irqsave(&orion5x_pci_lock, flags); | ||
| 278 | |||
| 279 | orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | | ||
| 280 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | ||
| 281 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); | ||
| 282 | |||
| 283 | *val = orion5x_read(PCI_CONF_DATA); | ||
| 284 | |||
| 285 | if (size == 1) | ||
| 286 | *val = (*val >> (8*(where & 0x3))) & 0xff; | ||
| 287 | else if (size == 2) | ||
| 288 | *val = (*val >> (8*(where & 0x3))) & 0xffff; | ||
| 289 | |||
| 290 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); | ||
| 291 | |||
| 292 | return PCIBIOS_SUCCESSFUL; | ||
| 293 | } | ||
| 294 | |||
| 295 | static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, | ||
| 296 | u32 where, u32 size, u32 val) | ||
| 297 | { | ||
| 298 | unsigned long flags; | ||
| 299 | int ret = PCIBIOS_SUCCESSFUL; | ||
| 300 | |||
| 301 | spin_lock_irqsave(&orion5x_pci_lock, flags); | ||
| 302 | |||
| 303 | orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | | ||
| 304 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | ||
| 305 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); | ||
| 306 | |||
| 307 | if (size == 4) { | ||
| 308 | __raw_writel(val, PCI_CONF_DATA); | ||
| 309 | } else if (size == 2) { | ||
| 310 | __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); | ||
| 311 | } else if (size == 1) { | ||
| 312 | __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); | ||
| 313 | } else { | ||
| 314 | ret = PCIBIOS_BAD_REGISTER_NUMBER; | ||
| 315 | } | ||
| 316 | |||
| 317 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); | ||
| 318 | |||
| 319 | return ret; | ||
| 320 | } | ||
| 321 | |||
| 322 | static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, | ||
| 323 | int where, int size, u32 *val) | ||
| 324 | { | ||
| 325 | /* | ||
| 326 | * Don't go out for local device | ||
| 327 | */ | ||
| 328 | if (bus->number == orion5x_pci_local_bus_nr() && | ||
| 329 | PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) { | ||
| 330 | *val = 0xffffffff; | ||
| 331 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 332 | } | ||
| 333 | |||
| 334 | return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), | ||
| 335 | PCI_FUNC(devfn), where, size, val); | ||
| 336 | } | ||
| 337 | |||
| 338 | static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, | ||
| 339 | int where, int size, u32 val) | ||
| 340 | { | ||
| 341 | if (bus->number == orion5x_pci_local_bus_nr() && | ||
| 342 | PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) | ||
| 343 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 344 | |||
| 345 | return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), | ||
| 346 | PCI_FUNC(devfn), where, size, val); | ||
| 347 | } | ||
| 348 | |||
| 349 | static struct pci_ops pci_ops = { | ||
| 350 | .read = orion5x_pci_rd_conf, | ||
| 351 | .write = orion5x_pci_wr_conf, | ||
| 352 | }; | ||
| 353 | |||
| 354 | static void __init orion5x_pci_set_bus_nr(int nr) | ||
| 355 | { | ||
| 356 | u32 p2p = orion5x_read(PCI_P2P_CONF); | ||
| 357 | |||
| 358 | if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) { | ||
| 359 | /* | ||
| 360 | * PCI-X mode | ||
| 361 | */ | ||
| 362 | u32 pcix_status, bus, dev; | ||
| 363 | bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; | ||
| 364 | dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; | ||
| 365 | orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); | ||
| 366 | pcix_status &= ~PCIX_STAT_BUS_MASK; | ||
| 367 | pcix_status |= (nr << PCIX_STAT_BUS_OFFS); | ||
| 368 | orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); | ||
| 369 | } else { | ||
| 370 | /* | ||
| 371 | * PCI Conventional mode | ||
| 372 | */ | ||
| 373 | p2p &= ~PCI_P2P_BUS_MASK; | ||
| 374 | p2p |= (nr << PCI_P2P_BUS_OFFS); | ||
| 375 | orion5x_write(PCI_P2P_CONF, p2p); | ||
| 376 | } | ||
| 377 | } | ||
| 378 | |||
| 379 | static void __init orion5x_pci_master_slave_enable(void) | ||
| 380 | { | ||
| 381 | int bus_nr, func, reg; | ||
| 382 | u32 val; | ||
| 383 | |||
| 384 | bus_nr = orion5x_pci_local_bus_nr(); | ||
| 385 | func = PCI_CONF_FUNC_STAT_CMD; | ||
| 386 | reg = PCI_CONF_REG_STAT_CMD; | ||
| 387 | orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); | ||
| 388 | val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | ||
| 389 | orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); | ||
| 390 | } | ||
| 391 | |||
| 392 | static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) | ||
| 393 | { | ||
| 394 | u32 win_enable; | ||
| 395 | int bus; | ||
| 396 | int i; | ||
| 397 | |||
| 398 | /* | ||
| 399 | * First, disable windows. | ||
| 400 | */ | ||
| 401 | win_enable = 0xffffffff; | ||
| 402 | orion5x_write(PCI_BAR_ENABLE, win_enable); | ||
| 403 | |||
| 404 | /* | ||
| 405 | * Setup windows for DDR banks. | ||
| 406 | */ | ||
| 407 | bus = orion5x_pci_local_bus_nr(); | ||
| 408 | |||
| 409 | for (i = 0; i < dram->num_cs; i++) { | ||
| 410 | struct mbus_dram_window *cs = dram->cs + i; | ||
| 411 | u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); | ||
| 412 | u32 reg; | ||
| 413 | u32 val; | ||
| 414 | |||
| 415 | /* | ||
| 416 | * Write DRAM bank base address register. | ||
| 417 | */ | ||
| 418 | reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); | ||
| 419 | orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); | ||
| 420 | val = (cs->base & 0xfffff000) | (val & 0xfff); | ||
| 421 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); | ||
| 422 | |||
| 423 | /* | ||
| 424 | * Write DRAM bank size register. | ||
| 425 | */ | ||
| 426 | reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); | ||
| 427 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); | ||
| 428 | orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), | ||
| 429 | (cs->size - 1) & 0xfffff000); | ||
| 430 | orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), | ||
| 431 | cs->base & 0xfffff000); | ||
| 432 | |||
| 433 | /* | ||
| 434 | * Enable decode window for this chip select. | ||
| 435 | */ | ||
| 436 | win_enable &= ~(1 << cs->cs_index); | ||
| 437 | } | ||
| 438 | |||
| 439 | /* | ||
| 440 | * Re-enable decode windows. | ||
| 441 | */ | ||
| 442 | orion5x_write(PCI_BAR_ENABLE, win_enable); | ||
| 443 | |||
| 444 | /* | ||
| 445 | * Disable automatic update of address remaping when writing to BARs. | ||
| 446 | */ | ||
| 447 | orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); | ||
| 448 | } | ||
| 449 | |||
| 450 | static int __init pci_setup(struct pci_sys_data *sys) | ||
| 451 | { | ||
| 452 | struct resource *res; | ||
| 453 | |||
| 454 | /* | ||
| 455 | * Point PCI unit MBUS decode windows to DRAM space. | ||
| 456 | */ | ||
| 457 | orion5x_setup_pci_wins(&orion5x_mbus_dram_info); | ||
| 458 | |||
| 459 | /* | ||
| 460 | * Master + Slave enable | ||
| 461 | */ | ||
| 462 | orion5x_pci_master_slave_enable(); | ||
| 463 | |||
| 464 | /* | ||
| 465 | * Force ordering | ||
| 466 | */ | ||
| 467 | orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); | ||
| 468 | |||
| 469 | /* | ||
| 470 | * Request resources | ||
| 471 | */ | ||
| 472 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); | ||
| 473 | if (!res) | ||
| 474 | panic("pci_setup unable to alloc resources"); | ||
| 475 | |||
| 476 | /* | ||
| 477 | * IORESOURCE_IO | ||
| 478 | */ | ||
| 479 | res[0].name = "PCI I/O Space"; | ||
| 480 | res[0].flags = IORESOURCE_IO; | ||
| 481 | res[0].start = ORION5X_PCI_IO_BUS_BASE; | ||
| 482 | res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; | ||
| 483 | if (request_resource(&ioport_resource, &res[0])) | ||
| 484 | panic("Request PCI IO resource failed\n"); | ||
| 485 | sys->resource[0] = &res[0]; | ||
| 486 | |||
| 487 | /* | ||
| 488 | * IORESOURCE_MEM | ||
| 489 | */ | ||
| 490 | res[1].name = "PCI Memory Space"; | ||
| 491 | res[1].flags = IORESOURCE_MEM; | ||
| 492 | res[1].start = ORION5X_PCI_MEM_PHYS_BASE; | ||
| 493 | res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; | ||
| 494 | if (request_resource(&iomem_resource, &res[1])) | ||
| 495 | panic("Request PCI Memory resource failed\n"); | ||
| 496 | sys->resource[1] = &res[1]; | ||
| 497 | |||
| 498 | sys->resource[2] = NULL; | ||
| 499 | sys->io_offset = 0; | ||
| 500 | |||
| 501 | return 1; | ||
| 502 | } | ||
| 503 | |||
| 504 | |||
| 505 | /***************************************************************************** | ||
| 506 | * General PCIe + PCI | ||
| 507 | ****************************************************************************/ | ||
| 508 | static void __devinit rc_pci_fixup(struct pci_dev *dev) | ||
| 509 | { | ||
| 510 | /* | ||
| 511 | * Prevent enumeration of root complex. | ||
| 512 | */ | ||
| 513 | if (dev->bus->parent == NULL && dev->devfn == 0) { | ||
| 514 | int i; | ||
| 515 | |||
| 516 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | ||
| 517 | dev->resource[i].start = 0; | ||
| 518 | dev->resource[i].end = 0; | ||
| 519 | dev->resource[i].flags = 0; | ||
| 520 | } | ||
| 521 | } | ||
| 522 | } | ||
| 523 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); | ||
| 524 | |||
| 525 | int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) | ||
| 526 | { | ||
| 527 | int ret = 0; | ||
| 528 | |||
| 529 | if (nr == 0) { | ||
| 530 | orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); | ||
| 531 | ret = pcie_setup(sys); | ||
| 532 | } else if (nr == 1) { | ||
| 533 | orion5x_pci_set_bus_nr(sys->busnr); | ||
| 534 | ret = pci_setup(sys); | ||
| 535 | } | ||
| 536 | |||
| 537 | return ret; | ||
| 538 | } | ||
| 539 | |||
| 540 | struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) | ||
| 541 | { | ||
| 542 | struct pci_bus *bus; | ||
| 543 | |||
| 544 | if (nr == 0) { | ||
| 545 | bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); | ||
| 546 | } else if (nr == 1) { | ||
| 547 | bus = pci_scan_bus(sys->busnr, &pci_ops, sys); | ||
| 548 | } else { | ||
| 549 | bus = NULL; | ||
| 550 | BUG(); | ||
| 551 | } | ||
| 552 | |||
| 553 | return bus; | ||
| 554 | } | ||
| 555 | |||
| 556 | int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | ||
| 557 | { | ||
| 558 | int bus = dev->bus->number; | ||
| 559 | |||
| 560 | /* | ||
| 561 | * PCIe endpoint? | ||
| 562 | */ | ||
| 563 | if (bus < orion5x_pci_local_bus_nr()) | ||
| 564 | return IRQ_ORION5X_PCIE0_INT; | ||
| 565 | |||
| 566 | return -1; | ||
| 567 | } | ||
diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index e851b8ca5ac6..aebe6b8e5059 100644 --- a/arch/arm/mach-orion/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c | |||
| @@ -1,12 +1,12 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-orion/rd88f5182-setup.c | 2 | * arch/arm/mach-orion5x/rd88f5182-setup.c |
| 3 | * | 3 | * |
| 4 | * Marvell Orion-NAS Reference Design Setup | 4 | * Marvell Orion-NAS Reference Design Setup |
| 5 | * | 5 | * |
| 6 | * Maintainer: Ronen Shitrit <rshitrit@marvell.com> | 6 | * Maintainer: Ronen Shitrit <rshitrit@marvell.com> |
| 7 | * | 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public | 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any | 9 | * License version 2. This program is licensed "as is" without any |
| 10 | * warranty of any kind, whether express or implied. | 10 | * warranty of any kind, whether express or implied. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| @@ -24,8 +24,7 @@ | |||
| 24 | #include <asm/leds.h> | 24 | #include <asm/leds.h> |
| 25 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
| 26 | #include <asm/mach/pci.h> | 26 | #include <asm/mach/pci.h> |
| 27 | #include <asm/arch/orion.h> | 27 | #include <asm/arch/orion5x.h> |
| 28 | #include <asm/arch/platform.h> | ||
| 29 | #include "common.h" | 28 | #include "common.h" |
| 30 | 29 | ||
| 31 | /***************************************************************************** | 30 | /***************************************************************************** |
| @@ -173,11 +172,14 @@ void __init rd88f5182_pci_preinit(void) | |||
| 173 | 172 | ||
| 174 | static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 173 | static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
| 175 | { | 174 | { |
| 175 | int irq; | ||
| 176 | |||
| 176 | /* | 177 | /* |
| 177 | * PCI-E isn't used on the RD2 | 178 | * Check for devices with hard-wired IRQs. |
| 178 | */ | 179 | */ |
| 179 | if (dev->bus->number == orion_pcie_local_bus_nr()) | 180 | irq = orion5x_pci_map_irq(dev, slot, pin); |
| 180 | return IRQ_ORION_PCIE0_INT; | 181 | if (irq != -1) |
| 182 | return irq; | ||
| 181 | 183 | ||
| 182 | /* | 184 | /* |
| 183 | * PCI IRQs are connected via GPIOs | 185 | * PCI IRQs are connected via GPIOs |
| @@ -197,8 +199,8 @@ static struct hw_pci rd88f5182_pci __initdata = { | |||
| 197 | .nr_controllers = 2, | 199 | .nr_controllers = 2, |
| 198 | .preinit = rd88f5182_pci_preinit, | 200 | .preinit = rd88f5182_pci_preinit, |
| 199 | .swizzle = pci_std_swizzle, | 201 | .swizzle = pci_std_swizzle, |
| 200 | .setup = orion_pci_sys_setup, | 202 | .setup = orion5x_pci_sys_setup, |
| 201 | .scan = orion_pci_sys_scan_bus, | 203 | .scan = orion5x_pci_sys_scan_bus, |
| 202 | .map_irq = rd88f5182_pci_map_irq, | 204 | .map_irq = rd88f5182_pci_map_irq, |
| 203 | }; | 205 | }; |
| 204 | 206 | ||
| @@ -250,22 +252,20 @@ static void __init rd88f5182_init(void) | |||
| 250 | /* | 252 | /* |
| 251 | * Setup basic Orion functions. Need to be called early. | 253 | * Setup basic Orion functions. Need to be called early. |
| 252 | */ | 254 | */ |
| 253 | orion_init(); | 255 | orion5x_init(); |
| 254 | 256 | ||
| 255 | /* | 257 | /* |
| 256 | * Setup the CPU address decode windows for our devices | 258 | * Setup the CPU address decode windows for our devices |
| 257 | */ | 259 | */ |
| 258 | orion_setup_cpu_win(ORION_DEV_BOOT, RD88F5182_NOR_BOOT_BASE, | 260 | orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, |
| 259 | RD88F5182_NOR_BOOT_SIZE, -1); | 261 | RD88F5182_NOR_BOOT_SIZE); |
| 260 | orion_setup_cpu_win(ORION_DEV1, RD88F5182_NOR_BASE, | 262 | orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); |
| 261 | RD88F5182_NOR_SIZE, -1); | ||
| 262 | 263 | ||
| 263 | /* | 264 | /* |
| 264 | * Open a special address decode windows for the PCIE WA. | 265 | * Open a special address decode windows for the PCIe WA. |
| 265 | */ | 266 | */ |
| 266 | orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); | 267 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
| 267 | orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | | 268 | ORION5X_PCIE_WA_SIZE); |
| 268 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); | ||
| 269 | 269 | ||
| 270 | /* | 270 | /* |
| 271 | * Setup Multiplexing Pins -- | 271 | * Setup Multiplexing Pins -- |
| @@ -291,25 +291,25 @@ static void __init rd88f5182_init(void) | |||
| 291 | * MPP[25] USB 0 over current enable | 291 | * MPP[25] USB 0 over current enable |
| 292 | */ | 292 | */ |
| 293 | 293 | ||
| 294 | orion_write(MPP_0_7_CTRL, 0x00000003); | 294 | orion5x_write(MPP_0_7_CTRL, 0x00000003); |
| 295 | orion_write(MPP_8_15_CTRL, 0x55550000); | 295 | orion5x_write(MPP_8_15_CTRL, 0x55550000); |
| 296 | orion_write(MPP_16_19_CTRL, 0x5555); | 296 | orion5x_write(MPP_16_19_CTRL, 0x5555); |
| 297 | 297 | ||
| 298 | orion_gpio_set_valid_pins(0x000000fb); | 298 | orion5x_gpio_set_valid_pins(0x000000fb); |
| 299 | 299 | ||
| 300 | platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices)); | 300 | platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices)); |
| 301 | i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); | 301 | i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); |
| 302 | orion_eth_init(&rd88f5182_eth_data); | 302 | orion5x_eth_init(&rd88f5182_eth_data); |
| 303 | orion_sata_init(&rd88f5182_sata_data); | 303 | orion5x_sata_init(&rd88f5182_sata_data); |
| 304 | } | 304 | } |
| 305 | 305 | ||
| 306 | MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") | 306 | MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") |
| 307 | /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ | 307 | /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ |
| 308 | .phys_io = ORION_REGS_PHYS_BASE, | 308 | .phys_io = ORION5X_REGS_PHYS_BASE, |
| 309 | .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, | 309 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, |
| 310 | .boot_params = 0x00000100, | 310 | .boot_params = 0x00000100, |
| 311 | .init_machine = rd88f5182_init, | 311 | .init_machine = rd88f5182_init, |
| 312 | .map_io = orion_map_io, | 312 | .map_io = orion5x_map_io, |
| 313 | .init_irq = orion_init_irq, | 313 | .init_irq = orion5x_init_irq, |
| 314 | .timer = &orion_timer, | 314 | .timer = &orion5x_timer, |
| 315 | MACHINE_END | 315 | MACHINE_END |
diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 45764dad16d0..161c965f3906 100644 --- a/arch/arm/mach-orion/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c | |||
| @@ -26,8 +26,7 @@ | |||
| 26 | #include <asm/gpio.h> | 26 | #include <asm/gpio.h> |
| 27 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| 28 | #include <asm/mach/pci.h> | 28 | #include <asm/mach/pci.h> |
| 29 | #include <asm/arch/orion.h> | 29 | #include <asm/arch/orion5x.h> |
| 30 | #include <asm/arch/platform.h> | ||
| 31 | #include "common.h" | 30 | #include "common.h" |
| 32 | 31 | ||
| 33 | #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 | 32 | #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 |
| @@ -142,14 +141,17 @@ void __init qnap_ts209_pci_preinit(void) | |||
| 142 | 141 | ||
| 143 | static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 142 | static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
| 144 | { | 143 | { |
| 144 | int irq; | ||
| 145 | |||
| 145 | /* | 146 | /* |
| 146 | * PCIE IRQ is connected internally (not GPIO) | 147 | * Check for devices with hard-wired IRQs. |
| 147 | */ | 148 | */ |
| 148 | if (dev->bus->number == orion_pcie_local_bus_nr()) | 149 | irq = orion5x_pci_map_irq(dev, slot, pin); |
| 149 | return IRQ_ORION_PCIE0_INT; | 150 | if (irq != -1) |
| 151 | return irq; | ||
| 150 | 152 | ||
| 151 | /* | 153 | /* |
| 152 | * PCI IRQs are connected via GPIOs | 154 | * PCI IRQs are connected via GPIOs. |
| 153 | */ | 155 | */ |
| 154 | switch (slot - QNAP_TS209_PCI_SLOT0_OFFS) { | 156 | switch (slot - QNAP_TS209_PCI_SLOT0_OFFS) { |
| 155 | case 0: | 157 | case 0: |
| @@ -165,8 +167,8 @@ static struct hw_pci qnap_ts209_pci __initdata = { | |||
| 165 | .nr_controllers = 2, | 167 | .nr_controllers = 2, |
| 166 | .preinit = qnap_ts209_pci_preinit, | 168 | .preinit = qnap_ts209_pci_preinit, |
| 167 | .swizzle = pci_std_swizzle, | 169 | .swizzle = pci_std_swizzle, |
| 168 | .setup = orion_pci_sys_setup, | 170 | .setup = orion5x_pci_sys_setup, |
| 169 | .scan = orion_pci_sys_scan_bus, | 171 | .scan = orion5x_pci_sys_scan_bus, |
| 170 | .map_irq = qnap_ts209_pci_map_irq, | 172 | .map_irq = qnap_ts209_pci_map_irq, |
| 171 | }; | 173 | }; |
| 172 | 174 | ||
| @@ -189,6 +191,87 @@ static struct mv643xx_eth_platform_data qnap_ts209_eth_data = { | |||
| 189 | .force_phy_addr = 1, | 191 | .force_phy_addr = 1, |
| 190 | }; | 192 | }; |
| 191 | 193 | ||
| 194 | static int __init parse_hex_nibble(char n) | ||
| 195 | { | ||
| 196 | if (n >= '0' && n <= '9') | ||
| 197 | return n - '0'; | ||
| 198 | |||
| 199 | if (n >= 'A' && n <= 'F') | ||
| 200 | return n - 'A' + 10; | ||
| 201 | |||
| 202 | if (n >= 'a' && n <= 'f') | ||
| 203 | return n - 'a' + 10; | ||
| 204 | |||
| 205 | return -1; | ||
| 206 | } | ||
| 207 | |||
| 208 | static int __init parse_hex_byte(const char *b) | ||
| 209 | { | ||
| 210 | int hi; | ||
| 211 | int lo; | ||
| 212 | |||
| 213 | hi = parse_hex_nibble(b[0]); | ||
| 214 | lo = parse_hex_nibble(b[1]); | ||
| 215 | |||
| 216 | if (hi < 0 || lo < 0) | ||
| 217 | return -1; | ||
| 218 | |||
| 219 | return (hi << 4) | lo; | ||
| 220 | } | ||
| 221 | |||
| 222 | static int __init check_mac_addr(const char *addr_str) | ||
| 223 | { | ||
| 224 | u_int8_t addr[6]; | ||
| 225 | int i; | ||
| 226 | |||
| 227 | for (i = 0; i < 6; i++) { | ||
| 228 | int byte; | ||
| 229 | |||
| 230 | /* | ||
| 231 | * Enforce "xx:xx:xx:xx:xx:xx\n" format. | ||
| 232 | */ | ||
| 233 | if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n')) | ||
| 234 | return -1; | ||
| 235 | |||
| 236 | byte = parse_hex_byte(addr_str + (i * 3)); | ||
| 237 | if (byte < 0) | ||
| 238 | return -1; | ||
| 239 | addr[i] = byte; | ||
| 240 | } | ||
| 241 | |||
| 242 | printk(KERN_INFO "ts209: found ethernet mac address "); | ||
| 243 | for (i = 0; i < 6; i++) | ||
| 244 | printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n"); | ||
| 245 | |||
| 246 | memcpy(qnap_ts209_eth_data.mac_addr, addr, 6); | ||
| 247 | |||
| 248 | return 0; | ||
| 249 | } | ||
| 250 | |||
| 251 | /* | ||
| 252 | * The 'NAS Config' flash partition has an ext2 filesystem which | ||
| 253 | * contains a file that has the ethernet MAC address in plain text | ||
| 254 | * (format "xx:xx:xx:xx:xx:xx\n".) | ||
| 255 | */ | ||
| 256 | static void __init ts209_find_mac_addr(void) | ||
| 257 | { | ||
| 258 | unsigned long addr; | ||
| 259 | |||
| 260 | for (addr = 0x00700000; addr < 0x00760000; addr += 1024) { | ||
| 261 | char *nor_page; | ||
| 262 | int ret = 0; | ||
| 263 | |||
| 264 | nor_page = ioremap(QNAP_TS209_NOR_BOOT_BASE + addr, 1024); | ||
| 265 | if (nor_page != NULL) { | ||
| 266 | ret = check_mac_addr(nor_page); | ||
| 267 | iounmap(nor_page); | ||
| 268 | } | ||
| 269 | |||
| 270 | if (ret == 0) | ||
| 271 | break; | ||
| 272 | } | ||
| 273 | } | ||
| 274 | |||
| 192 | /***************************************************************************** | 275 | /***************************************************************************** |
| 193 | * RTC S35390A on I2C bus | 276 | * RTC S35390A on I2C bus |
| 194 | ****************************************************************************/ | 277 | ****************************************************************************/ |
| @@ -262,21 +345,21 @@ static struct platform_device *qnap_ts209_devices[] __initdata = { | |||
| 262 | static void qnap_ts209_power_off(void) | 345 | static void qnap_ts209_power_off(void) |
| 263 | { | 346 | { |
| 264 | /* 19200 baud divisor */ | 347 | /* 19200 baud divisor */ |
| 265 | const unsigned divisor = ((ORION_TCLK + (8 * 19200)) / (16 * 19200)); | 348 | const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200)); |
| 266 | 349 | ||
| 267 | pr_info("%s: triggering power-off...\n", __func__); | 350 | pr_info("%s: triggering power-off...\n", __func__); |
| 268 | 351 | ||
| 269 | /* hijack uart1 and reset into sane state (19200,8n1) */ | 352 | /* hijack uart1 and reset into sane state (19200,8n1) */ |
| 270 | orion_write(UART1_REG(LCR), 0x83); | 353 | orion5x_write(UART1_REG(LCR), 0x83); |
| 271 | orion_write(UART1_REG(DLL), divisor & 0xff); | 354 | orion5x_write(UART1_REG(DLL), divisor & 0xff); |
| 272 | orion_write(UART1_REG(DLM), (divisor >> 8) & 0xff); | 355 | orion5x_write(UART1_REG(DLM), (divisor >> 8) & 0xff); |
| 273 | orion_write(UART1_REG(LCR), 0x03); | 356 | orion5x_write(UART1_REG(LCR), 0x03); |
| 274 | orion_write(UART1_REG(IER), 0x00); | 357 | orion5x_write(UART1_REG(IER), 0x00); |
| 275 | orion_write(UART1_REG(FCR), 0x00); | 358 | orion5x_write(UART1_REG(FCR), 0x00); |
| 276 | orion_write(UART1_REG(MCR), 0x00); | 359 | orion5x_write(UART1_REG(MCR), 0x00); |
| 277 | 360 | ||
| 278 | /* send the power-off command 'A' to PIC */ | 361 | /* send the power-off command 'A' to PIC */ |
| 279 | orion_write(UART1_REG(TX), 'A'); | 362 | orion5x_write(UART1_REG(TX), 'A'); |
| 280 | } | 363 | } |
| 281 | 364 | ||
| 282 | static void __init qnap_ts209_init(void) | 365 | static void __init qnap_ts209_init(void) |
| @@ -284,20 +367,19 @@ static void __init qnap_ts209_init(void) | |||
| 284 | /* | 367 | /* |
| 285 | * Setup basic Orion functions. Need to be called early. | 368 | * Setup basic Orion functions. Need to be called early. |
| 286 | */ | 369 | */ |
| 287 | orion_init(); | 370 | orion5x_init(); |
| 288 | 371 | ||
| 289 | /* | 372 | /* |
| 290 | * Setup flash mapping | 373 | * Setup flash mapping |
| 291 | */ | 374 | */ |
| 292 | orion_setup_cpu_win(ORION_DEV_BOOT, QNAP_TS209_NOR_BOOT_BASE, | 375 | orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, |
| 293 | QNAP_TS209_NOR_BOOT_SIZE, -1); | 376 | QNAP_TS209_NOR_BOOT_SIZE); |
| 294 | 377 | ||
| 295 | /* | 378 | /* |
| 296 | * Open a special address decode windows for the PCIE WA. | 379 | * Open a special address decode windows for the PCIe WA. |
| 297 | */ | 380 | */ |
| 298 | orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); | 381 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
| 299 | orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | | 382 | ORION5X_PCIE_WA_SIZE); |
| 300 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); | ||
| 301 | 383 | ||
| 302 | /* | 384 | /* |
| 303 | * Setup Multiplexing Pins -- | 385 | * Setup Multiplexing Pins -- |
| @@ -322,10 +404,10 @@ static void __init qnap_ts209_init(void) | |||
| 322 | * MPP[22] USB 0 over current | 404 | * MPP[22] USB 0 over current |
| 323 | * MPP[23-25] Reserved | 405 | * MPP[23-25] Reserved |
| 324 | */ | 406 | */ |
| 325 | orion_write(MPP_0_7_CTRL, 0x3); | 407 | orion5x_write(MPP_0_7_CTRL, 0x3); |
| 326 | orion_write(MPP_8_15_CTRL, 0x55550000); | 408 | orion5x_write(MPP_8_15_CTRL, 0x55550000); |
| 327 | orion_write(MPP_16_19_CTRL, 0x5500); | 409 | orion5x_write(MPP_16_19_CTRL, 0x5500); |
| 328 | orion_gpio_set_valid_pins(0x3cc0fff); | 410 | orion5x_gpio_set_valid_pins(0x3cc0fff); |
| 329 | 411 | ||
| 330 | /* register ts209 specific power-off method */ | 412 | /* register ts209 specific power-off method */ |
| 331 | pm_power_off = qnap_ts209_power_off; | 413 | pm_power_off = qnap_ts209_power_off; |
| @@ -344,18 +426,20 @@ static void __init qnap_ts209_init(void) | |||
| 344 | pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); | 426 | pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); |
| 345 | i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); | 427 | i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); |
| 346 | 428 | ||
| 347 | orion_eth_init(&qnap_ts209_eth_data); | 429 | ts209_find_mac_addr(); |
| 348 | orion_sata_init(&qnap_ts209_sata_data); | 430 | orion5x_eth_init(&qnap_ts209_eth_data); |
| 431 | |||
| 432 | orion5x_sata_init(&qnap_ts209_sata_data); | ||
| 349 | } | 433 | } |
| 350 | 434 | ||
| 351 | MACHINE_START(TS209, "QNAP TS-109/TS-209") | 435 | MACHINE_START(TS209, "QNAP TS-109/TS-209") |
| 352 | /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ | 436 | /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ |
| 353 | .phys_io = ORION_REGS_PHYS_BASE, | 437 | .phys_io = ORION5X_REGS_PHYS_BASE, |
| 354 | .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, | 438 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, |
| 355 | .boot_params = 0x00000100, | 439 | .boot_params = 0x00000100, |
| 356 | .init_machine = qnap_ts209_init, | 440 | .init_machine = qnap_ts209_init, |
| 357 | .map_io = orion_map_io, | 441 | .map_io = orion5x_map_io, |
| 358 | .init_irq = orion_init_irq, | 442 | .init_irq = orion5x_init_irq, |
| 359 | .timer = &orion_timer, | 443 | .timer = &orion5x_timer, |
| 360 | .fixup = tag_fixup_mem32, | 444 | .fixup = tag_fixup_mem32, |
| 361 | MACHINE_END | 445 | MACHINE_END |
diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c index 8e00ed43fb95..a5268c3ac5a7 100644 --- a/arch/arm/mach-pnx4008/clock.c +++ b/arch/arm/mach-pnx4008/clock.c | |||
| @@ -21,7 +21,6 @@ | |||
| 21 | #include <linux/err.h> | 21 | #include <linux/err.h> |
| 22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 23 | 23 | ||
| 24 | #include <asm/semaphore.h> | ||
| 25 | #include <asm/hardware.h> | 24 | #include <asm/hardware.h> |
| 26 | #include <asm/io.h> | 25 | #include <asm/io.h> |
| 27 | 26 | ||
diff --git a/arch/arm/mach-pnx4008/gpio.c b/arch/arm/mach-pnx4008/gpio.c index 1ab84ced7b5a..ef179cab80e2 100644 --- a/arch/arm/mach-pnx4008/gpio.c +++ b/arch/arm/mach-pnx4008/gpio.c | |||
| @@ -17,7 +17,6 @@ | |||
| 17 | #include <linux/types.h> | 17 | #include <linux/types.h> |
| 18 | #include <linux/kernel.h> | 18 | #include <linux/kernel.h> |
| 19 | #include <linux/module.h> | 19 | #include <linux/module.h> |
| 20 | #include <asm/semaphore.h> | ||
| 21 | #include <asm/io.h> | 20 | #include <asm/io.h> |
| 22 | #include <asm/arch/platform.h> | 21 | #include <asm/arch/platform.h> |
| 23 | #include <asm/arch/gpio.h> | 22 | #include <asm/arch/gpio.h> |
diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c index b84c3ba7a8d6..3a5b0fcbaf1f 100644 --- a/arch/arm/mach-pxa/mfp-pxa3xx.c +++ b/arch/arm/mach-pxa/mfp-pxa3xx.c | |||
| @@ -42,7 +42,7 @@ struct pxa3xx_mfp_pin { | |||
| 42 | static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX]; | 42 | static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX]; |
| 43 | 43 | ||
| 44 | /* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */ | 44 | /* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */ |
| 45 | const static unsigned long mfpr_lpm[] = { | 45 | static const unsigned long mfpr_lpm[] = { |
| 46 | MFPR_LPM_INPUT, | 46 | MFPR_LPM_INPUT, |
| 47 | MFPR_LPM_DRIVE_LOW, | 47 | MFPR_LPM_DRIVE_LOW, |
| 48 | MFPR_LPM_DRIVE_HIGH, | 48 | MFPR_LPM_DRIVE_HIGH, |
| @@ -52,7 +52,7 @@ const static unsigned long mfpr_lpm[] = { | |||
| 52 | }; | 52 | }; |
| 53 | 53 | ||
| 54 | /* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */ | 54 | /* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */ |
| 55 | const static unsigned long mfpr_pull[] = { | 55 | static const unsigned long mfpr_pull[] = { |
| 56 | MFPR_PULL_NONE, | 56 | MFPR_PULL_NONE, |
| 57 | MFPR_PULL_LOW, | 57 | MFPR_PULL_LOW, |
| 58 | MFPR_PULL_HIGH, | 58 | MFPR_PULL_HIGH, |
| @@ -60,7 +60,7 @@ const static unsigned long mfpr_pull[] = { | |||
| 60 | }; | 60 | }; |
| 61 | 61 | ||
| 62 | /* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */ | 62 | /* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */ |
| 63 | const static unsigned long mfpr_edge[] = { | 63 | static const unsigned long mfpr_edge[] = { |
| 64 | MFPR_EDGE_NONE, | 64 | MFPR_EDGE_NONE, |
| 65 | MFPR_EDGE_RISE, | 65 | MFPR_EDGE_RISE, |
| 66 | MFPR_EDGE_FALL, | 66 | MFPR_EDGE_FALL, |
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index 39b3bb7f1020..5ccde7cf39e8 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig | |||
| @@ -10,7 +10,6 @@ config MACH_REALVIEW_EB | |||
| 10 | config REALVIEW_EB_ARM11MP | 10 | config REALVIEW_EB_ARM11MP |
| 11 | bool "Support ARM11MPCore tile" | 11 | bool "Support ARM11MPCore tile" |
| 12 | depends on MACH_REALVIEW_EB | 12 | depends on MACH_REALVIEW_EB |
| 13 | select CACHE_L2X0 | ||
| 14 | help | 13 | help |
| 15 | Enable support for the ARM11MPCore tile on the Realview platform. | 14 | Enable support for the ARM11MPCore tile on the Realview platform. |
| 16 | 15 | ||
| @@ -24,4 +23,18 @@ config REALVIEW_EB_ARM11MP_REVB | |||
| 24 | kernel built with this option enabled is not compatible with | 23 | kernel built with this option enabled is not compatible with |
| 25 | other revisions of the ARM11MPCore tile. | 24 | other revisions of the ARM11MPCore tile. |
| 26 | 25 | ||
| 26 | config MACH_REALVIEW_PB11MP | ||
| 27 | bool "Support RealView/PB11MPCore platform" | ||
| 28 | select ARM_GIC | ||
| 29 | help | ||
| 30 | Include support for the ARM(R) RealView MPCore Platform Baseboard. | ||
| 31 | PB11MPCore is a platform with an on-board ARM11MPCore and has | ||
| 32 | support for PCI-E and Compact Flash. | ||
| 33 | |||
| 34 | config MACH_REALVIEW_PB1176 | ||
| 35 | bool "Support RealView/PB1176 platform" | ||
| 36 | select ARM_GIC | ||
| 37 | help | ||
| 38 | Include support for the ARM(R) RealView ARM1176 Platform Baseboard. | ||
| 39 | |||
| 27 | endmenu | 40 | endmenu |
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile index ca1e390c3c28..d2ae077431dd 100644 --- a/arch/arm/mach-realview/Makefile +++ b/arch/arm/mach-realview/Makefile | |||
| @@ -4,5 +4,7 @@ | |||
| 4 | 4 | ||
| 5 | obj-y := core.o clock.o | 5 | obj-y := core.o clock.o |
| 6 | obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o | 6 | obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o |
| 7 | obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o | ||
| 8 | obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o | ||
| 7 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o | 9 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o |
| 8 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 10 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
diff --git a/arch/arm/mach-realview/clock.c b/arch/arm/mach-realview/clock.c index 21325a4da9da..3e706c57833a 100644 --- a/arch/arm/mach-realview/clock.c +++ b/arch/arm/mach-realview/clock.c | |||
| @@ -16,7 +16,6 @@ | |||
| 16 | #include <linux/clk.h> | 16 | #include <linux/clk.h> |
| 17 | #include <linux/mutex.h> | 17 | #include <linux/mutex.h> |
| 18 | 18 | ||
| 19 | #include <asm/semaphore.h> | ||
| 20 | #include <asm/hardware/icst307.h> | 19 | #include <asm/hardware/icst307.h> |
| 21 | 20 | ||
| 22 | #include "clock.h" | 21 | #include "clock.h" |
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 98aefc9f4df3..131990d196f5 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c | |||
| @@ -109,22 +109,21 @@ static struct flash_platform_data realview_flash_data = { | |||
| 109 | .set_vpp = realview_flash_set_vpp, | 109 | .set_vpp = realview_flash_set_vpp, |
| 110 | }; | 110 | }; |
| 111 | 111 | ||
| 112 | static struct resource realview_flash_resource = { | ||
| 113 | .start = REALVIEW_FLASH_BASE, | ||
| 114 | .end = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE, | ||
| 115 | .flags = IORESOURCE_MEM, | ||
| 116 | }; | ||
| 117 | |||
| 118 | struct platform_device realview_flash_device = { | 112 | struct platform_device realview_flash_device = { |
| 119 | .name = "armflash", | 113 | .name = "armflash", |
| 120 | .id = 0, | 114 | .id = 0, |
| 121 | .dev = { | 115 | .dev = { |
| 122 | .platform_data = &realview_flash_data, | 116 | .platform_data = &realview_flash_data, |
| 123 | }, | 117 | }, |
| 124 | .num_resources = 1, | ||
| 125 | .resource = &realview_flash_resource, | ||
| 126 | }; | 118 | }; |
| 127 | 119 | ||
| 120 | int realview_flash_register(struct resource *res, u32 num) | ||
| 121 | { | ||
| 122 | realview_flash_device.resource = res; | ||
| 123 | realview_flash_device.num_resources = num; | ||
| 124 | return platform_device_register(&realview_flash_device); | ||
| 125 | } | ||
| 126 | |||
| 128 | static struct resource realview_i2c_resource = { | 127 | static struct resource realview_i2c_resource = { |
| 129 | .start = REALVIEW_I2C_BASE, | 128 | .start = REALVIEW_I2C_BASE, |
| 130 | .end = REALVIEW_I2C_BASE + SZ_4K - 1, | 129 | .end = REALVIEW_I2C_BASE + SZ_4K - 1, |
| @@ -445,10 +444,10 @@ void realview_leds_event(led_event_t ledevt) | |||
| 445 | /* | 444 | /* |
| 446 | * Where is the timer (VA)? | 445 | * Where is the timer (VA)? |
| 447 | */ | 446 | */ |
| 448 | #define TIMER0_VA_BASE __io_address(REALVIEW_TIMER0_1_BASE) | 447 | void __iomem *timer0_va_base; |
| 449 | #define TIMER1_VA_BASE (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20) | 448 | void __iomem *timer1_va_base; |
| 450 | #define TIMER2_VA_BASE __io_address(REALVIEW_TIMER2_3_BASE) | 449 | void __iomem *timer2_va_base; |
| 451 | #define TIMER3_VA_BASE (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20) | 450 | void __iomem *timer3_va_base; |
| 452 | 451 | ||
| 453 | /* | 452 | /* |
| 454 | * How long is the timer interval? | 453 | * How long is the timer interval? |
| @@ -475,7 +474,7 @@ static void timer_set_mode(enum clock_event_mode mode, | |||
| 475 | 474 | ||
| 476 | switch(mode) { | 475 | switch(mode) { |
| 477 | case CLOCK_EVT_MODE_PERIODIC: | 476 | case CLOCK_EVT_MODE_PERIODIC: |
| 478 | writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD); | 477 | writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD); |
| 479 | 478 | ||
| 480 | ctrl = TIMER_CTRL_PERIODIC; | 479 | ctrl = TIMER_CTRL_PERIODIC; |
| 481 | ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE; | 480 | ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE; |
| @@ -491,16 +490,16 @@ static void timer_set_mode(enum clock_event_mode mode, | |||
| 491 | ctrl = 0; | 490 | ctrl = 0; |
| 492 | } | 491 | } |
| 493 | 492 | ||
| 494 | writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL); | 493 | writel(ctrl, timer0_va_base + TIMER_CTRL); |
| 495 | } | 494 | } |
| 496 | 495 | ||
| 497 | static int timer_set_next_event(unsigned long evt, | 496 | static int timer_set_next_event(unsigned long evt, |
| 498 | struct clock_event_device *unused) | 497 | struct clock_event_device *unused) |
| 499 | { | 498 | { |
| 500 | unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL); | 499 | unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL); |
| 501 | 500 | ||
| 502 | writel(evt, TIMER0_VA_BASE + TIMER_LOAD); | 501 | writel(evt, timer0_va_base + TIMER_LOAD); |
| 503 | writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL); | 502 | writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL); |
| 504 | 503 | ||
| 505 | return 0; | 504 | return 0; |
| 506 | } | 505 | } |
| @@ -536,7 +535,7 @@ static irqreturn_t realview_timer_interrupt(int irq, void *dev_id) | |||
| 536 | struct clock_event_device *evt = &timer0_clockevent; | 535 | struct clock_event_device *evt = &timer0_clockevent; |
| 537 | 536 | ||
| 538 | /* clear the interrupt */ | 537 | /* clear the interrupt */ |
| 539 | writel(1, TIMER0_VA_BASE + TIMER_INTCLR); | 538 | writel(1, timer0_va_base + TIMER_INTCLR); |
| 540 | 539 | ||
| 541 | evt->event_handler(evt); | 540 | evt->event_handler(evt); |
| 542 | 541 | ||
| @@ -551,7 +550,7 @@ static struct irqaction realview_timer_irq = { | |||
| 551 | 550 | ||
| 552 | static cycle_t realview_get_cycles(void) | 551 | static cycle_t realview_get_cycles(void) |
| 553 | { | 552 | { |
| 554 | return ~readl(TIMER3_VA_BASE + TIMER_VALUE); | 553 | return ~readl(timer3_va_base + TIMER_VALUE); |
| 555 | } | 554 | } |
| 556 | 555 | ||
| 557 | static struct clocksource clocksource_realview = { | 556 | static struct clocksource clocksource_realview = { |
| @@ -566,11 +565,11 @@ static struct clocksource clocksource_realview = { | |||
| 566 | static void __init realview_clocksource_init(void) | 565 | static void __init realview_clocksource_init(void) |
| 567 | { | 566 | { |
| 568 | /* setup timer 0 as free-running clocksource */ | 567 | /* setup timer 0 as free-running clocksource */ |
| 569 | writel(0, TIMER3_VA_BASE + TIMER_CTRL); | 568 | writel(0, timer3_va_base + TIMER_CTRL); |
| 570 | writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD); | 569 | writel(0xffffffff, timer3_va_base + TIMER_LOAD); |
| 571 | writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE); | 570 | writel(0xffffffff, timer3_va_base + TIMER_VALUE); |
| 572 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, | 571 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, |
| 573 | TIMER3_VA_BASE + TIMER_CTRL); | 572 | timer3_va_base + TIMER_CTRL); |
| 574 | 573 | ||
| 575 | clocksource_realview.mult = | 574 | clocksource_realview.mult = |
| 576 | clocksource_khz2mult(1000, clocksource_realview.shift); | 575 | clocksource_khz2mult(1000, clocksource_realview.shift); |
| @@ -607,10 +606,10 @@ void __init realview_timer_init(unsigned int timer_irq) | |||
| 607 | /* | 606 | /* |
| 608 | * Initialise to a known state (all timers off) | 607 | * Initialise to a known state (all timers off) |
| 609 | */ | 608 | */ |
| 610 | writel(0, TIMER0_VA_BASE + TIMER_CTRL); | 609 | writel(0, timer0_va_base + TIMER_CTRL); |
| 611 | writel(0, TIMER1_VA_BASE + TIMER_CTRL); | 610 | writel(0, timer1_va_base + TIMER_CTRL); |
| 612 | writel(0, TIMER2_VA_BASE + TIMER_CTRL); | 611 | writel(0, timer2_va_base + TIMER_CTRL); |
| 613 | writel(0, TIMER3_VA_BASE + TIMER_CTRL); | 612 | writel(0, timer3_va_base + TIMER_CTRL); |
| 614 | 613 | ||
| 615 | /* | 614 | /* |
| 616 | * Make irqs happen for the system timer | 615 | * Make irqs happen for the system timer |
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 492a14c0d604..33dbbb41a663 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h | |||
| @@ -55,8 +55,13 @@ extern void __iomem *gic_cpu_base_addr; | |||
| 55 | extern void __iomem *twd_base_addr; | 55 | extern void __iomem *twd_base_addr; |
| 56 | extern unsigned int twd_size; | 56 | extern unsigned int twd_size; |
| 57 | #endif | 57 | #endif |
| 58 | extern void __iomem *timer0_va_base; | ||
| 59 | extern void __iomem *timer1_va_base; | ||
| 60 | extern void __iomem *timer2_va_base; | ||
| 61 | extern void __iomem *timer3_va_base; | ||
| 58 | 62 | ||
| 59 | extern void realview_leds_event(led_event_t ledevt); | 63 | extern void realview_leds_event(led_event_t ledevt); |
| 60 | extern void realview_timer_init(unsigned int timer_irq); | 64 | extern void realview_timer_init(unsigned int timer_irq); |
| 65 | extern int realview_flash_register(struct resource *res, u32 num); | ||
| 61 | 66 | ||
| 62 | #endif | 67 | #endif |
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index de2b7159557d..3e57428affee 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c | |||
| @@ -15,11 +15,14 @@ | |||
| 15 | #include <linux/smp.h> | 15 | #include <linux/smp.h> |
| 16 | 16 | ||
| 17 | #include <asm/cacheflush.h> | 17 | #include <asm/cacheflush.h> |
| 18 | #include <asm/hardware/arm_scu.h> | ||
| 19 | #include <asm/hardware.h> | 18 | #include <asm/hardware.h> |
| 20 | #include <asm/io.h> | 19 | #include <asm/io.h> |
| 21 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
| 22 | 21 | ||
| 22 | #include <asm/arch/board-eb.h> | ||
| 23 | #include <asm/arch/board-pb11mp.h> | ||
| 24 | #include <asm/arch/scu.h> | ||
| 25 | |||
| 23 | extern void realview_secondary_startup(void); | 26 | extern void realview_secondary_startup(void); |
| 24 | 27 | ||
| 25 | /* | 28 | /* |
| @@ -31,9 +34,15 @@ volatile int __cpuinitdata pen_release = -1; | |||
| 31 | static unsigned int __init get_core_count(void) | 34 | static unsigned int __init get_core_count(void) |
| 32 | { | 35 | { |
| 33 | unsigned int ncores; | 36 | unsigned int ncores; |
| 37 | void __iomem *scu_base = 0; | ||
| 38 | |||
| 39 | if (machine_is_realview_eb() && core_tile_eb11mp()) | ||
| 40 | scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); | ||
| 41 | else if (machine_is_realview_pb11mp()) | ||
| 42 | scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); | ||
| 34 | 43 | ||
| 35 | if (machine_is_realview_eb() && core_tile_eb11mp()) { | 44 | if (scu_base) { |
| 36 | ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG); | 45 | ncores = __raw_readl(scu_base + SCU_CONFIG); |
| 37 | ncores = (ncores & 0x03) + 1; | 46 | ncores = (ncores & 0x03) + 1; |
| 38 | } else | 47 | } else |
| 39 | ncores = 1; | 48 | ncores = 1; |
| @@ -41,6 +50,26 @@ static unsigned int __init get_core_count(void) | |||
| 41 | return ncores; | 50 | return ncores; |
| 42 | } | 51 | } |
| 43 | 52 | ||
| 53 | /* | ||
| 54 | * Setup the SCU | ||
| 55 | */ | ||
| 56 | static void scu_enable(void) | ||
| 57 | { | ||
| 58 | u32 scu_ctrl; | ||
| 59 | void __iomem *scu_base; | ||
| 60 | |||
| 61 | if (machine_is_realview_eb() && core_tile_eb11mp()) | ||
| 62 | scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); | ||
| 63 | else if (machine_is_realview_pb11mp()) | ||
| 64 | scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); | ||
| 65 | else | ||
| 66 | BUG(); | ||
| 67 | |||
| 68 | scu_ctrl = __raw_readl(scu_base + SCU_CTRL); | ||
| 69 | scu_ctrl |= 1; | ||
| 70 | __raw_writel(scu_ctrl, scu_base + SCU_CTRL); | ||
| 71 | } | ||
| 72 | |||
| 44 | static DEFINE_SPINLOCK(boot_lock); | 73 | static DEFINE_SPINLOCK(boot_lock); |
| 45 | 74 | ||
| 46 | void __cpuinit platform_secondary_init(unsigned int cpu) | 75 | void __cpuinit platform_secondary_init(unsigned int cpu) |
| @@ -57,7 +86,10 @@ void __cpuinit platform_secondary_init(unsigned int cpu) | |||
| 57 | * core (e.g. timer irq), then they will not have been enabled | 86 | * core (e.g. timer irq), then they will not have been enabled |
| 58 | * for us: do so | 87 | * for us: do so |
| 59 | */ | 88 | */ |
| 60 | gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); | 89 | if (machine_is_realview_eb() && core_tile_eb11mp()) |
| 90 | gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); | ||
| 91 | else if (machine_is_realview_pb11mp()) | ||
| 92 | gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE)); | ||
| 61 | 93 | ||
| 62 | /* | 94 | /* |
| 63 | * let the primary processor know we're out of the | 95 | * let the primary processor know we're out of the |
| @@ -198,7 +230,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
| 198 | * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in | 230 | * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in |
| 199 | * realview_timer_init | 231 | * realview_timer_init |
| 200 | */ | 232 | */ |
| 201 | if (machine_is_realview_eb() && core_tile_eb11mp()) | 233 | if ((machine_is_realview_eb() && core_tile_eb11mp()) || |
| 234 | machine_is_realview_pb11mp()) | ||
| 202 | local_timer_setup(cpu); | 235 | local_timer_setup(cpu); |
| 203 | #endif | 236 | #endif |
| 204 | 237 | ||
| @@ -210,11 +243,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
| 210 | cpu_set(i, cpu_present_map); | 243 | cpu_set(i, cpu_present_map); |
| 211 | 244 | ||
| 212 | /* | 245 | /* |
| 213 | * Do we need any more CPUs? If so, then let them know where | 246 | * Initialise the SCU if there are more than one CPU and let |
| 214 | * to start. Note that, on modern versions of MILO, the "poke" | 247 | * them know where to start. Note that, on modern versions of |
| 215 | * doesn't actually do anything until each individual core is | 248 | * MILO, the "poke" doesn't actually do anything until each |
| 216 | * sent a soft interrupt to get it out of WFI | 249 | * individual core is sent a soft interrupt to get it out of |
| 250 | * WFI | ||
| 217 | */ | 251 | */ |
| 218 | if (max_cpus > 1) | 252 | if (max_cpus > 1) { |
| 253 | scu_enable(); | ||
| 219 | poke_milo(); | 254 | poke_milo(); |
| 255 | } | ||
| 220 | } | 256 | } |
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 60d9eb810246..5782d83fd886 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c | |||
| @@ -51,13 +51,13 @@ static struct map_desc realview_eb_io_desc[] __initdata = { | |||
| 51 | .length = SZ_4K, | 51 | .length = SZ_4K, |
| 52 | .type = MT_DEVICE, | 52 | .type = MT_DEVICE, |
| 53 | }, { | 53 | }, { |
| 54 | .virtual = IO_ADDRESS(REALVIEW_GIC_CPU_BASE), | 54 | .virtual = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE), |
| 55 | .pfn = __phys_to_pfn(REALVIEW_GIC_CPU_BASE), | 55 | .pfn = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE), |
| 56 | .length = SZ_4K, | 56 | .length = SZ_4K, |
| 57 | .type = MT_DEVICE, | 57 | .type = MT_DEVICE, |
| 58 | }, { | 58 | }, { |
| 59 | .virtual = IO_ADDRESS(REALVIEW_GIC_DIST_BASE), | 59 | .virtual = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE), |
| 60 | .pfn = __phys_to_pfn(REALVIEW_GIC_DIST_BASE), | 60 | .pfn = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE), |
| 61 | .length = SZ_4K, | 61 | .length = SZ_4K, |
| 62 | .type = MT_DEVICE, | 62 | .type = MT_DEVICE, |
| 63 | }, { | 63 | }, { |
| @@ -66,20 +66,20 @@ static struct map_desc realview_eb_io_desc[] __initdata = { | |||
| 66 | .length = SZ_4K, | 66 | .length = SZ_4K, |
| 67 | .type = MT_DEVICE, | 67 | .type = MT_DEVICE, |
| 68 | }, { | 68 | }, { |
| 69 | .virtual = IO_ADDRESS(REALVIEW_TIMER0_1_BASE), | 69 | .virtual = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE), |
| 70 | .pfn = __phys_to_pfn(REALVIEW_TIMER0_1_BASE), | 70 | .pfn = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE), |
| 71 | .length = SZ_4K, | 71 | .length = SZ_4K, |
| 72 | .type = MT_DEVICE, | 72 | .type = MT_DEVICE, |
| 73 | }, { | 73 | }, { |
| 74 | .virtual = IO_ADDRESS(REALVIEW_TIMER2_3_BASE), | 74 | .virtual = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE), |
| 75 | .pfn = __phys_to_pfn(REALVIEW_TIMER2_3_BASE), | 75 | .pfn = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE), |
| 76 | .length = SZ_4K, | 76 | .length = SZ_4K, |
| 77 | .type = MT_DEVICE, | 77 | .type = MT_DEVICE, |
| 78 | }, | 78 | }, |
| 79 | #ifdef CONFIG_DEBUG_LL | 79 | #ifdef CONFIG_DEBUG_LL |
| 80 | { | 80 | { |
| 81 | .virtual = IO_ADDRESS(REALVIEW_UART0_BASE), | 81 | .virtual = IO_ADDRESS(REALVIEW_EB_UART0_BASE), |
| 82 | .pfn = __phys_to_pfn(REALVIEW_UART0_BASE), | 82 | .pfn = __phys_to_pfn(REALVIEW_EB_UART0_BASE), |
| 83 | .length = SZ_4K, | 83 | .length = SZ_4K, |
| 84 | .type = MT_DEVICE, | 84 | .type = MT_DEVICE, |
| 85 | } | 85 | } |
| @@ -136,12 +136,12 @@ static void __init realview_eb_map_io(void) | |||
| 136 | /* | 136 | /* |
| 137 | * These devices are connected directly to the multi-layer AHB switch | 137 | * These devices are connected directly to the multi-layer AHB switch |
| 138 | */ | 138 | */ |
| 139 | #define SMC_IRQ { NO_IRQ, NO_IRQ } | 139 | #define EB_SMC_IRQ { NO_IRQ, NO_IRQ } |
| 140 | #define SMC_DMA { 0, 0 } | 140 | #define EB_SMC_DMA { 0, 0 } |
| 141 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } | 141 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } |
| 142 | #define MPMC_DMA { 0, 0 } | 142 | #define MPMC_DMA { 0, 0 } |
| 143 | #define CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ } | 143 | #define EB_CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ } |
| 144 | #define CLCD_DMA { 0, 0 } | 144 | #define EB_CLCD_DMA { 0, 0 } |
| 145 | #define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ } | 145 | #define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ } |
| 146 | #define DMAC_DMA { 0, 0 } | 146 | #define DMAC_DMA { 0, 0 } |
| 147 | 147 | ||
| @@ -150,53 +150,53 @@ static void __init realview_eb_map_io(void) | |||
| 150 | */ | 150 | */ |
| 151 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } | 151 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } |
| 152 | #define SCTL_DMA { 0, 0 } | 152 | #define SCTL_DMA { 0, 0 } |
| 153 | #define WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ } | 153 | #define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ } |
| 154 | #define WATCHDOG_DMA { 0, 0 } | 154 | #define EB_WATCHDOG_DMA { 0, 0 } |
| 155 | #define GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ } | 155 | #define EB_GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ } |
| 156 | #define GPIO0_DMA { 0, 0 } | 156 | #define EB_GPIO0_DMA { 0, 0 } |
| 157 | #define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ } | 157 | #define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ } |
| 158 | #define GPIO1_DMA { 0, 0 } | 158 | #define GPIO1_DMA { 0, 0 } |
| 159 | #define RTC_IRQ { IRQ_EB_RTC, NO_IRQ } | 159 | #define EB_RTC_IRQ { IRQ_EB_RTC, NO_IRQ } |
| 160 | #define RTC_DMA { 0, 0 } | 160 | #define EB_RTC_DMA { 0, 0 } |
| 161 | 161 | ||
| 162 | /* | 162 | /* |
| 163 | * These devices are connected via the DMA APB bridge | 163 | * These devices are connected via the DMA APB bridge |
| 164 | */ | 164 | */ |
| 165 | #define SCI_IRQ { IRQ_EB_SCI, NO_IRQ } | 165 | #define SCI_IRQ { IRQ_EB_SCI, NO_IRQ } |
| 166 | #define SCI_DMA { 7, 6 } | 166 | #define SCI_DMA { 7, 6 } |
| 167 | #define UART0_IRQ { IRQ_EB_UART0, NO_IRQ } | 167 | #define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ } |
| 168 | #define UART0_DMA { 15, 14 } | 168 | #define EB_UART0_DMA { 15, 14 } |
| 169 | #define UART1_IRQ { IRQ_EB_UART1, NO_IRQ } | 169 | #define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ } |
| 170 | #define UART1_DMA { 13, 12 } | 170 | #define EB_UART1_DMA { 13, 12 } |
| 171 | #define UART2_IRQ { IRQ_EB_UART2, NO_IRQ } | 171 | #define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ } |
| 172 | #define UART2_DMA { 11, 10 } | 172 | #define EB_UART2_DMA { 11, 10 } |
| 173 | #define UART3_IRQ { IRQ_EB_UART3, NO_IRQ } | 173 | #define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ } |
| 174 | #define UART3_DMA { 0x86, 0x87 } | 174 | #define EB_UART3_DMA { 0x86, 0x87 } |
| 175 | #define SSP_IRQ { IRQ_EB_SSP, NO_IRQ } | 175 | #define EB_SSP_IRQ { IRQ_EB_SSP, NO_IRQ } |
| 176 | #define SSP_DMA { 9, 8 } | 176 | #define EB_SSP_DMA { 9, 8 } |
| 177 | 177 | ||
| 178 | /* FPGA Primecells */ | 178 | /* FPGA Primecells */ |
| 179 | AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); | 179 | AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); |
| 180 | AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); | 180 | AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); |
| 181 | AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); | 181 | AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); |
| 182 | AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); | 182 | AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); |
| 183 | AMBA_DEVICE(uart3, "fpga:09", UART3, NULL); | 183 | AMBA_DEVICE(uart3, "fpga:09", EB_UART3, NULL); |
| 184 | 184 | ||
| 185 | /* DevChip Primecells */ | 185 | /* DevChip Primecells */ |
| 186 | AMBA_DEVICE(smc, "dev:00", SMC, NULL); | 186 | AMBA_DEVICE(smc, "dev:00", EB_SMC, NULL); |
| 187 | AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data); | 187 | AMBA_DEVICE(clcd, "dev:20", EB_CLCD, &clcd_plat_data); |
| 188 | AMBA_DEVICE(dmac, "dev:30", DMAC, NULL); | 188 | AMBA_DEVICE(dmac, "dev:30", DMAC, NULL); |
| 189 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); | 189 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); |
| 190 | AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL); | 190 | AMBA_DEVICE(wdog, "dev:e1", EB_WATCHDOG, NULL); |
| 191 | AMBA_DEVICE(gpio0, "dev:e4", GPIO0, NULL); | 191 | AMBA_DEVICE(gpio0, "dev:e4", EB_GPIO0, NULL); |
| 192 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); | 192 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); |
| 193 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); | 193 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); |
| 194 | AMBA_DEVICE(rtc, "dev:e8", RTC, NULL); | 194 | AMBA_DEVICE(rtc, "dev:e8", EB_RTC, NULL); |
| 195 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); | 195 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); |
| 196 | AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); | 196 | AMBA_DEVICE(uart0, "dev:f1", EB_UART0, NULL); |
| 197 | AMBA_DEVICE(uart1, "dev:f2", UART1, NULL); | 197 | AMBA_DEVICE(uart1, "dev:f2", EB_UART1, NULL); |
| 198 | AMBA_DEVICE(uart2, "dev:f3", UART2, NULL); | 198 | AMBA_DEVICE(uart2, "dev:f3", EB_UART2, NULL); |
| 199 | AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL); | 199 | AMBA_DEVICE(ssp0, "dev:f4", EB_SSP, NULL); |
| 200 | 200 | ||
| 201 | static struct amba_device *amba_devs[] __initdata = { | 201 | static struct amba_device *amba_devs[] __initdata = { |
| 202 | &dmac_device, | 202 | &dmac_device, |
| @@ -223,11 +223,16 @@ static struct amba_device *amba_devs[] __initdata = { | |||
| 223 | /* | 223 | /* |
| 224 | * RealView EB platform devices | 224 | * RealView EB platform devices |
| 225 | */ | 225 | */ |
| 226 | static struct resource realview_eb_flash_resource = { | ||
| 227 | .start = REALVIEW_EB_FLASH_BASE, | ||
| 228 | .end = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1, | ||
| 229 | .flags = IORESOURCE_MEM, | ||
| 230 | }; | ||
| 226 | 231 | ||
| 227 | static struct resource realview_eb_smc91x_resources[] = { | 232 | static struct resource realview_eb_eth_resources[] = { |
| 228 | [0] = { | 233 | [0] = { |
| 229 | .start = REALVIEW_ETH_BASE, | 234 | .start = REALVIEW_EB_ETH_BASE, |
| 230 | .end = REALVIEW_ETH_BASE + SZ_64K - 1, | 235 | .end = REALVIEW_EB_ETH_BASE + SZ_64K - 1, |
| 231 | .flags = IORESOURCE_MEM, | 236 | .flags = IORESOURCE_MEM, |
| 232 | }, | 237 | }, |
| 233 | [1] = { | 238 | [1] = { |
| @@ -237,13 +242,36 @@ static struct resource realview_eb_smc91x_resources[] = { | |||
| 237 | }, | 242 | }, |
| 238 | }; | 243 | }; |
| 239 | 244 | ||
| 240 | static struct platform_device realview_eb_smc91x_device = { | 245 | static struct platform_device realview_eb_eth_device = { |
| 241 | .name = "smc91x", | ||
| 242 | .id = 0, | 246 | .id = 0, |
| 243 | .num_resources = ARRAY_SIZE(realview_eb_smc91x_resources), | 247 | .num_resources = ARRAY_SIZE(realview_eb_eth_resources), |
| 244 | .resource = realview_eb_smc91x_resources, | 248 | .resource = realview_eb_eth_resources, |
| 245 | }; | 249 | }; |
| 246 | 250 | ||
| 251 | /* | ||
| 252 | * Detect and register the correct Ethernet device. RealView/EB rev D | ||
| 253 | * platforms use the newer SMSC LAN9118 Ethernet chip | ||
| 254 | */ | ||
| 255 | static int eth_device_register(void) | ||
| 256 | { | ||
| 257 | void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K); | ||
| 258 | u32 idrev; | ||
| 259 | |||
| 260 | if (!eth_addr) | ||
| 261 | return -ENOMEM; | ||
| 262 | |||
| 263 | idrev = readl(eth_addr + 0x50); | ||
| 264 | if ((idrev & 0xFFFF0000) == 0x01180000) | ||
| 265 | /* SMSC LAN9118 chip present */ | ||
| 266 | realview_eb_eth_device.name = "smc911x"; | ||
| 267 | else | ||
| 268 | /* SMSC 91C111 chip present */ | ||
| 269 | realview_eb_eth_device.name = "smc91x"; | ||
| 270 | |||
| 271 | iounmap(eth_addr); | ||
| 272 | return platform_device_register(&realview_eb_eth_device); | ||
| 273 | } | ||
| 274 | |||
| 247 | static void __init gic_init_irq(void) | 275 | static void __init gic_init_irq(void) |
| 248 | { | 276 | { |
| 249 | if (core_tile_eb11mp()) { | 277 | if (core_tile_eb11mp()) { |
| @@ -263,14 +291,14 @@ static void __init gic_init_irq(void) | |||
| 263 | 291 | ||
| 264 | #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB | 292 | #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB |
| 265 | /* board GIC, secondary */ | 293 | /* board GIC, secondary */ |
| 266 | gic_dist_init(1, __io_address(REALVIEW_GIC_DIST_BASE), 64); | 294 | gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64); |
| 267 | gic_cpu_init(1, __io_address(REALVIEW_GIC_CPU_BASE)); | 295 | gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE)); |
| 268 | gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); | 296 | gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); |
| 269 | #endif | 297 | #endif |
| 270 | } else { | 298 | } else { |
| 271 | /* board GIC, primary */ | 299 | /* board GIC, primary */ |
| 272 | gic_cpu_base_addr = __io_address(REALVIEW_GIC_CPU_BASE); | 300 | gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE); |
| 273 | gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29); | 301 | gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29); |
| 274 | gic_cpu_init(0, gic_cpu_base_addr); | 302 | gic_cpu_init(0, gic_cpu_base_addr); |
| 275 | } | 303 | } |
| 276 | } | 304 | } |
| @@ -301,14 +329,19 @@ static void realview_eb11mp_fixup(void) | |||
| 301 | kmi1_device.irq[0] = IRQ_EB11MP_KMI1; | 329 | kmi1_device.irq[0] = IRQ_EB11MP_KMI1; |
| 302 | 330 | ||
| 303 | /* platform devices */ | 331 | /* platform devices */ |
| 304 | realview_eb_smc91x_resources[1].start = IRQ_EB11MP_ETH; | 332 | realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH; |
| 305 | realview_eb_smc91x_resources[1].end = IRQ_EB11MP_ETH; | 333 | realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH; |
| 306 | } | 334 | } |
| 307 | 335 | ||
| 308 | static void __init realview_eb_timer_init(void) | 336 | static void __init realview_eb_timer_init(void) |
| 309 | { | 337 | { |
| 310 | unsigned int timer_irq; | 338 | unsigned int timer_irq; |
| 311 | 339 | ||
| 340 | timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE); | ||
| 341 | timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20; | ||
| 342 | timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE); | ||
| 343 | timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20; | ||
| 344 | |||
| 312 | if (core_tile_eb11mp()) { | 345 | if (core_tile_eb11mp()) { |
| 313 | #ifdef CONFIG_LOCAL_TIMERS | 346 | #ifdef CONFIG_LOCAL_TIMERS |
| 314 | twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE); | 347 | twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE); |
| @@ -332,16 +365,18 @@ static void __init realview_eb_init(void) | |||
| 332 | if (core_tile_eb11mp()) { | 365 | if (core_tile_eb11mp()) { |
| 333 | realview_eb11mp_fixup(); | 366 | realview_eb11mp_fixup(); |
| 334 | 367 | ||
| 368 | #ifdef CONFIG_CACHE_L2X0 | ||
| 335 | /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled | 369 | /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled |
| 336 | * Bits: .... ...0 0111 1001 0000 .... .... .... */ | 370 | * Bits: .... ...0 0111 1001 0000 .... .... .... */ |
| 337 | l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff); | 371 | l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff); |
| 372 | #endif | ||
| 338 | } | 373 | } |
| 339 | 374 | ||
| 340 | clk_register(&realview_clcd_clk); | 375 | clk_register(&realview_clcd_clk); |
| 341 | 376 | ||
| 342 | platform_device_register(&realview_flash_device); | 377 | realview_flash_register(&realview_eb_flash_resource, 1); |
| 343 | platform_device_register(&realview_eb_smc91x_device); | ||
| 344 | platform_device_register(&realview_i2c_device); | 378 | platform_device_register(&realview_i2c_device); |
| 379 | eth_device_register(); | ||
| 345 | 380 | ||
| 346 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | 381 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { |
| 347 | struct amba_device *d = amba_devs[i]; | 382 | struct amba_device *d = amba_devs[i]; |
| @@ -355,8 +390,8 @@ static void __init realview_eb_init(void) | |||
| 355 | 390 | ||
| 356 | MACHINE_START(REALVIEW_EB, "ARM-RealView EB") | 391 | MACHINE_START(REALVIEW_EB, "ARM-RealView EB") |
| 357 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | 392 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ |
| 358 | .phys_io = REALVIEW_UART0_BASE, | 393 | .phys_io = REALVIEW_EB_UART0_BASE, |
| 359 | .io_pg_offst = (IO_ADDRESS(REALVIEW_UART0_BASE) >> 18) & 0xfffc, | 394 | .io_pg_offst = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc, |
| 360 | .boot_params = 0x00000100, | 395 | .boot_params = 0x00000100, |
| 361 | .map_io = realview_eb_map_io, | 396 | .map_io = realview_eb_map_io, |
| 362 | .init_irq = gic_init_irq, | 397 | .init_irq = gic_init_irq, |
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c new file mode 100644 index 000000000000..cf7f576a5860 --- /dev/null +++ b/arch/arm/mach-realview/realview_pb1176.c | |||
| @@ -0,0 +1,292 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-realview/realview_pb1176.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 ARM Limited | ||
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/init.h> | ||
| 23 | #include <linux/platform_device.h> | ||
| 24 | #include <linux/sysdev.h> | ||
| 25 | #include <linux/amba/bus.h> | ||
| 26 | |||
| 27 | #include <asm/hardware.h> | ||
| 28 | #include <asm/io.h> | ||
| 29 | #include <asm/irq.h> | ||
| 30 | #include <asm/leds.h> | ||
| 31 | #include <asm/mach-types.h> | ||
| 32 | #include <asm/hardware/gic.h> | ||
| 33 | #include <asm/hardware/icst307.h> | ||
| 34 | #include <asm/hardware/cache-l2x0.h> | ||
| 35 | |||
| 36 | #include <asm/mach/arch.h> | ||
| 37 | #include <asm/mach/flash.h> | ||
| 38 | #include <asm/mach/map.h> | ||
| 39 | #include <asm/mach/mmc.h> | ||
| 40 | #include <asm/mach/time.h> | ||
| 41 | |||
| 42 | #include <asm/arch/board-pb1176.h> | ||
| 43 | #include <asm/arch/irqs.h> | ||
| 44 | |||
| 45 | #include "core.h" | ||
| 46 | #include "clock.h" | ||
| 47 | |||
| 48 | static struct map_desc realview_pb1176_io_desc[] __initdata = { | ||
| 49 | { | ||
| 50 | .virtual = IO_ADDRESS(REALVIEW_SYS_BASE), | ||
| 51 | .pfn = __phys_to_pfn(REALVIEW_SYS_BASE), | ||
| 52 | .length = SZ_4K, | ||
| 53 | .type = MT_DEVICE, | ||
| 54 | }, { | ||
| 55 | .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_CPU_BASE), | ||
| 56 | .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_CPU_BASE), | ||
| 57 | .length = SZ_4K, | ||
| 58 | .type = MT_DEVICE, | ||
| 59 | }, { | ||
| 60 | .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_DIST_BASE), | ||
| 61 | .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_DIST_BASE), | ||
| 62 | .length = SZ_4K, | ||
| 63 | .type = MT_DEVICE, | ||
| 64 | }, { | ||
| 65 | .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_CPU_BASE), | ||
| 66 | .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_CPU_BASE), | ||
| 67 | .length = SZ_4K, | ||
| 68 | .type = MT_DEVICE, | ||
| 69 | }, { | ||
| 70 | .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_DIST_BASE), | ||
| 71 | .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_DIST_BASE), | ||
| 72 | .length = SZ_4K, | ||
| 73 | .type = MT_DEVICE, | ||
| 74 | }, { | ||
| 75 | .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), | ||
| 76 | .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), | ||
| 77 | .length = SZ_4K, | ||
| 78 | .type = MT_DEVICE, | ||
| 79 | }, { | ||
| 80 | .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER0_1_BASE), | ||
| 81 | .pfn = __phys_to_pfn(REALVIEW_PB1176_TIMER0_1_BASE), | ||
| 82 | .length = SZ_4K, | ||
| 83 | .type = MT_DEVICE, | ||
| 84 | }, { | ||
| 85 | .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER2_3_BASE), | ||
| 86 | .pfn = __phys_to_pfn(REALVIEW_PB1176_TIMER2_3_BASE), | ||
| 87 | .length = SZ_4K, | ||
| 88 | .type = MT_DEVICE, | ||
| 89 | }, { | ||
| 90 | .virtual = IO_ADDRESS(REALVIEW_PB1176_L220_BASE), | ||
| 91 | .pfn = __phys_to_pfn(REALVIEW_PB1176_L220_BASE), | ||
| 92 | .length = SZ_8K, | ||
| 93 | .type = MT_DEVICE, | ||
| 94 | }, | ||
| 95 | #ifdef CONFIG_DEBUG_LL | ||
| 96 | { | ||
| 97 | .virtual = IO_ADDRESS(REALVIEW_PB1176_UART0_BASE), | ||
| 98 | .pfn = __phys_to_pfn(REALVIEW_PB1176_UART0_BASE), | ||
| 99 | .length = SZ_4K, | ||
| 100 | .type = MT_DEVICE, | ||
| 101 | }, | ||
| 102 | #endif | ||
| 103 | }; | ||
| 104 | |||
| 105 | static void __init realview_pb1176_map_io(void) | ||
| 106 | { | ||
| 107 | iotable_init(realview_pb1176_io_desc, ARRAY_SIZE(realview_pb1176_io_desc)); | ||
| 108 | } | ||
| 109 | |||
| 110 | /* | ||
| 111 | * RealView PB1176 AMBA devices | ||
| 112 | */ | ||
| 113 | #define GPIO2_IRQ { IRQ_PB1176_GPIO2, NO_IRQ } | ||
| 114 | #define GPIO2_DMA { 0, 0 } | ||
| 115 | #define GPIO3_IRQ { IRQ_PB1176_GPIO3, NO_IRQ } | ||
| 116 | #define GPIO3_DMA { 0, 0 } | ||
| 117 | #define AACI_IRQ { IRQ_PB1176_AACI, NO_IRQ } | ||
| 118 | #define AACI_DMA { 0x80, 0x81 } | ||
| 119 | #define MMCI0_IRQ { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B } | ||
| 120 | #define MMCI0_DMA { 0x84, 0 } | ||
| 121 | #define KMI0_IRQ { IRQ_PB1176_KMI0, NO_IRQ } | ||
| 122 | #define KMI0_DMA { 0, 0 } | ||
| 123 | #define KMI1_IRQ { IRQ_PB1176_KMI1, NO_IRQ } | ||
| 124 | #define KMI1_DMA { 0, 0 } | ||
| 125 | #define PB1176_SMC_IRQ { NO_IRQ, NO_IRQ } | ||
| 126 | #define PB1176_SMC_DMA { 0, 0 } | ||
| 127 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } | ||
| 128 | #define MPMC_DMA { 0, 0 } | ||
| 129 | #define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ } | ||
| 130 | #define PB1176_CLCD_DMA { 0, 0 } | ||
| 131 | #define DMAC_IRQ { IRQ_PB1176_DMAC, NO_IRQ } | ||
| 132 | #define DMAC_DMA { 0, 0 } | ||
| 133 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } | ||
| 134 | #define SCTL_DMA { 0, 0 } | ||
| 135 | #define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG, NO_IRQ } | ||
| 136 | #define PB1176_WATCHDOG_DMA { 0, 0 } | ||
| 137 | #define PB1176_GPIO0_IRQ { IRQ_PB1176_GPIO0, NO_IRQ } | ||
| 138 | #define PB1176_GPIO0_DMA { 0, 0 } | ||
| 139 | #define GPIO1_IRQ { IRQ_PB1176_GPIO1, NO_IRQ } | ||
| 140 | #define GPIO1_DMA { 0, 0 } | ||
| 141 | #define PB1176_RTC_IRQ { IRQ_DC1176_RTC, NO_IRQ } | ||
| 142 | #define PB1176_RTC_DMA { 0, 0 } | ||
| 143 | #define SCI_IRQ { IRQ_PB1176_SCI, NO_IRQ } | ||
| 144 | #define SCI_DMA { 7, 6 } | ||
| 145 | #define PB1176_UART0_IRQ { IRQ_DC1176_UART0, NO_IRQ } | ||
| 146 | #define PB1176_UART0_DMA { 15, 14 } | ||
| 147 | #define PB1176_UART1_IRQ { IRQ_DC1176_UART1, NO_IRQ } | ||
| 148 | #define PB1176_UART1_DMA { 13, 12 } | ||
| 149 | #define PB1176_UART2_IRQ { IRQ_DC1176_UART2, NO_IRQ } | ||
| 150 | #define PB1176_UART2_DMA { 11, 10 } | ||
| 151 | #define PB1176_UART3_IRQ { IRQ_DC1176_UART3, NO_IRQ } | ||
| 152 | #define PB1176_UART3_DMA { 0x86, 0x87 } | ||
| 153 | #define PB1176_SSP_IRQ { IRQ_PB1176_SSP, NO_IRQ } | ||
| 154 | #define PB1176_SSP_DMA { 9, 8 } | ||
| 155 | |||
| 156 | /* FPGA Primecells */ | ||
| 157 | AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); | ||
| 158 | AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); | ||
| 159 | AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); | ||
| 160 | AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); | ||
| 161 | AMBA_DEVICE(uart3, "fpga:09", PB1176_UART3, NULL); | ||
| 162 | |||
| 163 | /* DevChip Primecells */ | ||
| 164 | AMBA_DEVICE(smc, "dev:00", PB1176_SMC, NULL); | ||
| 165 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); | ||
| 166 | AMBA_DEVICE(wdog, "dev:e1", PB1176_WATCHDOG, NULL); | ||
| 167 | AMBA_DEVICE(gpio0, "dev:e4", PB1176_GPIO0, NULL); | ||
| 168 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); | ||
| 169 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); | ||
| 170 | AMBA_DEVICE(rtc, "dev:e8", PB1176_RTC, NULL); | ||
| 171 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); | ||
| 172 | AMBA_DEVICE(uart0, "dev:f1", PB1176_UART0, NULL); | ||
| 173 | AMBA_DEVICE(uart1, "dev:f2", PB1176_UART1, NULL); | ||
| 174 | AMBA_DEVICE(uart2, "dev:f3", PB1176_UART2, NULL); | ||
| 175 | AMBA_DEVICE(ssp0, "dev:f4", PB1176_SSP, NULL); | ||
| 176 | |||
| 177 | /* Primecells on the NEC ISSP chip */ | ||
| 178 | AMBA_DEVICE(clcd, "issp:20", PB1176_CLCD, &clcd_plat_data); | ||
| 179 | //AMBA_DEVICE(dmac, "issp:30", PB1176_DMAC, NULL); | ||
| 180 | |||
| 181 | static struct amba_device *amba_devs[] __initdata = { | ||
| 182 | // &dmac_device, | ||
| 183 | &uart0_device, | ||
| 184 | &uart1_device, | ||
| 185 | &uart2_device, | ||
| 186 | &uart3_device, | ||
| 187 | &smc_device, | ||
| 188 | &clcd_device, | ||
| 189 | &sctl_device, | ||
| 190 | &wdog_device, | ||
| 191 | &gpio0_device, | ||
| 192 | &gpio1_device, | ||
| 193 | &gpio2_device, | ||
| 194 | &rtc_device, | ||
| 195 | &sci0_device, | ||
| 196 | &ssp0_device, | ||
| 197 | &aaci_device, | ||
| 198 | &mmc0_device, | ||
| 199 | &kmi0_device, | ||
| 200 | &kmi1_device, | ||
| 201 | }; | ||
| 202 | |||
| 203 | /* | ||
| 204 | * RealView PB1176 platform devices | ||
| 205 | */ | ||
| 206 | static struct resource realview_pb1176_flash_resource = { | ||
| 207 | .start = REALVIEW_PB1176_FLASH_BASE, | ||
| 208 | .end = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1, | ||
| 209 | .flags = IORESOURCE_MEM, | ||
| 210 | }; | ||
| 211 | |||
| 212 | static struct resource realview_pb1176_smsc911x_resources[] = { | ||
| 213 | [0] = { | ||
| 214 | .start = REALVIEW_PB1176_ETH_BASE, | ||
| 215 | .end = REALVIEW_PB1176_ETH_BASE + SZ_64K - 1, | ||
| 216 | .flags = IORESOURCE_MEM, | ||
| 217 | }, | ||
| 218 | [1] = { | ||
| 219 | .start = IRQ_PB1176_ETH, | ||
| 220 | .end = IRQ_PB1176_ETH, | ||
| 221 | .flags = IORESOURCE_IRQ, | ||
| 222 | }, | ||
| 223 | }; | ||
| 224 | |||
| 225 | static struct platform_device realview_pb1176_smsc911x_device = { | ||
| 226 | .name = "smc911x", | ||
| 227 | .id = 0, | ||
| 228 | .num_resources = ARRAY_SIZE(realview_pb1176_smsc911x_resources), | ||
| 229 | .resource = realview_pb1176_smsc911x_resources, | ||
| 230 | }; | ||
| 231 | |||
| 232 | static void __init gic_init_irq(void) | ||
| 233 | { | ||
| 234 | /* ARM1176 DevChip GIC, primary */ | ||
| 235 | gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE); | ||
| 236 | gic_dist_init(0, __io_address(REALVIEW_DC1176_GIC_DIST_BASE), IRQ_DC1176_GIC_START); | ||
| 237 | gic_cpu_init(0, gic_cpu_base_addr); | ||
| 238 | |||
| 239 | /* board GIC, secondary */ | ||
| 240 | gic_dist_init(1, __io_address(REALVIEW_PB1176_GIC_DIST_BASE), IRQ_PB1176_GIC_START); | ||
| 241 | gic_cpu_init(1, __io_address(REALVIEW_PB1176_GIC_CPU_BASE)); | ||
| 242 | gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1); | ||
| 243 | } | ||
| 244 | |||
| 245 | static void __init realview_pb1176_timer_init(void) | ||
| 246 | { | ||
| 247 | timer0_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE); | ||
| 248 | timer1_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE) + 0x20; | ||
| 249 | timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE); | ||
| 250 | timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20; | ||
| 251 | |||
| 252 | realview_timer_init(IRQ_DC1176_TIMER0); | ||
| 253 | } | ||
| 254 | |||
| 255 | static struct sys_timer realview_pb1176_timer = { | ||
| 256 | .init = realview_pb1176_timer_init, | ||
| 257 | }; | ||
| 258 | |||
| 259 | static void __init realview_pb1176_init(void) | ||
| 260 | { | ||
| 261 | int i; | ||
| 262 | |||
| 263 | #ifdef CONFIG_CACHE_L2X0 | ||
| 264 | /* 128Kb (16Kb/way) 8-way associativity. evmon/parity/share enabled. */ | ||
| 265 | l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff); | ||
| 266 | #endif | ||
| 267 | |||
| 268 | clk_register(&realview_clcd_clk); | ||
| 269 | |||
| 270 | realview_flash_register(&realview_pb1176_flash_resource, 1); | ||
| 271 | platform_device_register(&realview_pb1176_smsc911x_device); | ||
| 272 | |||
| 273 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | ||
| 274 | struct amba_device *d = amba_devs[i]; | ||
| 275 | amba_device_register(d, &iomem_resource); | ||
| 276 | } | ||
| 277 | |||
| 278 | #ifdef CONFIG_LEDS | ||
| 279 | leds_event = realview_leds_event; | ||
| 280 | #endif | ||
| 281 | } | ||
| 282 | |||
| 283 | MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176") | ||
| 284 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | ||
| 285 | .phys_io = REALVIEW_PB1176_UART0_BASE, | ||
| 286 | .io_pg_offst = (IO_ADDRESS(REALVIEW_PB1176_UART0_BASE) >> 18) & 0xfffc, | ||
| 287 | .boot_params = 0x00000100, | ||
| 288 | .map_io = realview_pb1176_map_io, | ||
| 289 | .init_irq = gic_init_irq, | ||
| 290 | .timer = &realview_pb1176_timer, | ||
| 291 | .init_machine = realview_pb1176_init, | ||
| 292 | MACHINE_END | ||
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c new file mode 100644 index 000000000000..f7ce1c5a178a --- /dev/null +++ b/arch/arm/mach-realview/realview_pb11mp.c | |||
| @@ -0,0 +1,342 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-realview/realview_pb11mp.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 ARM Limited | ||
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/init.h> | ||
| 23 | #include <linux/platform_device.h> | ||
| 24 | #include <linux/sysdev.h> | ||
| 25 | #include <linux/amba/bus.h> | ||
| 26 | |||
| 27 | #include <asm/hardware.h> | ||
| 28 | #include <asm/io.h> | ||
| 29 | #include <asm/irq.h> | ||
| 30 | #include <asm/leds.h> | ||
| 31 | #include <asm/mach-types.h> | ||
| 32 | #include <asm/hardware/gic.h> | ||
| 33 | #include <asm/hardware/icst307.h> | ||
| 34 | #include <asm/hardware/cache-l2x0.h> | ||
| 35 | |||
| 36 | #include <asm/mach/arch.h> | ||
| 37 | #include <asm/mach/flash.h> | ||
| 38 | #include <asm/mach/map.h> | ||
| 39 | #include <asm/mach/mmc.h> | ||
| 40 | #include <asm/mach/time.h> | ||
| 41 | |||
| 42 | #include <asm/arch/board-pb11mp.h> | ||
| 43 | #include <asm/arch/irqs.h> | ||
| 44 | |||
| 45 | #include "core.h" | ||
| 46 | #include "clock.h" | ||
| 47 | |||
| 48 | static struct map_desc realview_pb11mp_io_desc[] __initdata = { | ||
| 49 | { | ||
| 50 | .virtual = IO_ADDRESS(REALVIEW_SYS_BASE), | ||
| 51 | .pfn = __phys_to_pfn(REALVIEW_SYS_BASE), | ||
| 52 | .length = SZ_4K, | ||
| 53 | .type = MT_DEVICE, | ||
| 54 | }, { | ||
| 55 | .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE), | ||
| 56 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_CPU_BASE), | ||
| 57 | .length = SZ_4K, | ||
| 58 | .type = MT_DEVICE, | ||
| 59 | }, { | ||
| 60 | .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE), | ||
| 61 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE), | ||
| 62 | .length = SZ_4K, | ||
| 63 | .type = MT_DEVICE, | ||
| 64 | }, { | ||
| 65 | .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_CPU_BASE), | ||
| 66 | .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_CPU_BASE), | ||
| 67 | .length = SZ_4K, | ||
| 68 | .type = MT_DEVICE, | ||
| 69 | }, { | ||
| 70 | .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_DIST_BASE), | ||
| 71 | .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_DIST_BASE), | ||
| 72 | .length = SZ_4K, | ||
| 73 | .type = MT_DEVICE, | ||
| 74 | }, { | ||
| 75 | .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), | ||
| 76 | .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), | ||
| 77 | .length = SZ_4K, | ||
| 78 | .type = MT_DEVICE, | ||
| 79 | }, { | ||
| 80 | .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE), | ||
| 81 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER0_1_BASE), | ||
| 82 | .length = SZ_4K, | ||
| 83 | .type = MT_DEVICE, | ||
| 84 | }, { | ||
| 85 | .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE), | ||
| 86 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER2_3_BASE), | ||
| 87 | .length = SZ_4K, | ||
| 88 | .type = MT_DEVICE, | ||
| 89 | }, { | ||
| 90 | .virtual = IO_ADDRESS(REALVIEW_TC11MP_L220_BASE), | ||
| 91 | .pfn = __phys_to_pfn(REALVIEW_TC11MP_L220_BASE), | ||
| 92 | .length = SZ_8K, | ||
| 93 | .type = MT_DEVICE, | ||
| 94 | }, | ||
| 95 | #ifdef CONFIG_DEBUG_LL | ||
| 96 | { | ||
| 97 | .virtual = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE), | ||
| 98 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_UART0_BASE), | ||
| 99 | .length = SZ_4K, | ||
| 100 | .type = MT_DEVICE, | ||
| 101 | }, | ||
| 102 | #endif | ||
| 103 | }; | ||
| 104 | |||
| 105 | static void __init realview_pb11mp_map_io(void) | ||
| 106 | { | ||
| 107 | iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc)); | ||
| 108 | } | ||
| 109 | |||
| 110 | /* | ||
| 111 | * RealView PB11MPCore AMBA devices | ||
| 112 | */ | ||
| 113 | |||
| 114 | #define GPIO2_IRQ { IRQ_PB11MP_GPIO2, NO_IRQ } | ||
| 115 | #define GPIO2_DMA { 0, 0 } | ||
| 116 | #define GPIO3_IRQ { IRQ_PB11MP_GPIO3, NO_IRQ } | ||
| 117 | #define GPIO3_DMA { 0, 0 } | ||
| 118 | #define AACI_IRQ { IRQ_TC11MP_AACI, NO_IRQ } | ||
| 119 | #define AACI_DMA { 0x80, 0x81 } | ||
| 120 | #define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B } | ||
| 121 | #define MMCI0_DMA { 0x84, 0 } | ||
| 122 | #define KMI0_IRQ { IRQ_TC11MP_KMI0, NO_IRQ } | ||
| 123 | #define KMI0_DMA { 0, 0 } | ||
| 124 | #define KMI1_IRQ { IRQ_TC11MP_KMI1, NO_IRQ } | ||
| 125 | #define KMI1_DMA { 0, 0 } | ||
| 126 | #define PB11MP_SMC_IRQ { NO_IRQ, NO_IRQ } | ||
| 127 | #define PB11MP_SMC_DMA { 0, 0 } | ||
| 128 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } | ||
| 129 | #define MPMC_DMA { 0, 0 } | ||
| 130 | #define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD, NO_IRQ } | ||
| 131 | #define PB11MP_CLCD_DMA { 0, 0 } | ||
| 132 | #define DMAC_IRQ { IRQ_PB11MP_DMAC, NO_IRQ } | ||
| 133 | #define DMAC_DMA { 0, 0 } | ||
| 134 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } | ||
| 135 | #define SCTL_DMA { 0, 0 } | ||
| 136 | #define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG, NO_IRQ } | ||
| 137 | #define PB11MP_WATCHDOG_DMA { 0, 0 } | ||
| 138 | #define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0, NO_IRQ } | ||
| 139 | #define PB11MP_GPIO0_DMA { 0, 0 } | ||
| 140 | #define GPIO1_IRQ { IRQ_PB11MP_GPIO1, NO_IRQ } | ||
| 141 | #define GPIO1_DMA { 0, 0 } | ||
| 142 | #define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC, NO_IRQ } | ||
| 143 | #define PB11MP_RTC_DMA { 0, 0 } | ||
| 144 | #define SCI_IRQ { IRQ_PB11MP_SCI, NO_IRQ } | ||
| 145 | #define SCI_DMA { 7, 6 } | ||
| 146 | #define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0, NO_IRQ } | ||
| 147 | #define PB11MP_UART0_DMA { 15, 14 } | ||
| 148 | #define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1, NO_IRQ } | ||
| 149 | #define PB11MP_UART1_DMA { 13, 12 } | ||
| 150 | #define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2, NO_IRQ } | ||
| 151 | #define PB11MP_UART2_DMA { 11, 10 } | ||
| 152 | #define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3, NO_IRQ } | ||
| 153 | #define PB11MP_UART3_DMA { 0x86, 0x87 } | ||
| 154 | #define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP, NO_IRQ } | ||
| 155 | #define PB11MP_SSP_DMA { 9, 8 } | ||
| 156 | |||
| 157 | /* FPGA Primecells */ | ||
| 158 | AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); | ||
| 159 | AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); | ||
| 160 | AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); | ||
| 161 | AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); | ||
| 162 | AMBA_DEVICE(uart3, "fpga:09", PB11MP_UART3, NULL); | ||
| 163 | |||
| 164 | /* DevChip Primecells */ | ||
| 165 | AMBA_DEVICE(smc, "dev:00", PB11MP_SMC, NULL); | ||
| 166 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); | ||
| 167 | AMBA_DEVICE(wdog, "dev:e1", PB11MP_WATCHDOG, NULL); | ||
| 168 | AMBA_DEVICE(gpio0, "dev:e4", PB11MP_GPIO0, NULL); | ||
| 169 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); | ||
| 170 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); | ||
| 171 | AMBA_DEVICE(rtc, "dev:e8", PB11MP_RTC, NULL); | ||
| 172 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); | ||
| 173 | AMBA_DEVICE(uart0, "dev:f1", PB11MP_UART0, NULL); | ||
| 174 | AMBA_DEVICE(uart1, "dev:f2", PB11MP_UART1, NULL); | ||
| 175 | AMBA_DEVICE(uart2, "dev:f3", PB11MP_UART2, NULL); | ||
| 176 | AMBA_DEVICE(ssp0, "dev:f4", PB11MP_SSP, NULL); | ||
| 177 | |||
| 178 | /* Primecells on the NEC ISSP chip */ | ||
| 179 | AMBA_DEVICE(clcd, "issp:20", PB11MP_CLCD, &clcd_plat_data); | ||
| 180 | AMBA_DEVICE(dmac, "issp:30", DMAC, NULL); | ||
| 181 | |||
| 182 | static struct amba_device *amba_devs[] __initdata = { | ||
| 183 | &dmac_device, | ||
| 184 | &uart0_device, | ||
| 185 | &uart1_device, | ||
| 186 | &uart2_device, | ||
| 187 | &uart3_device, | ||
| 188 | &smc_device, | ||
| 189 | &clcd_device, | ||
| 190 | &sctl_device, | ||
| 191 | &wdog_device, | ||
| 192 | &gpio0_device, | ||
| 193 | &gpio1_device, | ||
| 194 | &gpio2_device, | ||
| 195 | &rtc_device, | ||
| 196 | &sci0_device, | ||
| 197 | &ssp0_device, | ||
| 198 | &aaci_device, | ||
| 199 | &mmc0_device, | ||
| 200 | &kmi0_device, | ||
| 201 | &kmi1_device, | ||
| 202 | }; | ||
| 203 | |||
| 204 | /* | ||
| 205 | * RealView PB11MPCore platform devices | ||
| 206 | */ | ||
| 207 | static struct resource realview_pb11mp_flash_resource[] = { | ||
| 208 | [0] = { | ||
| 209 | .start = REALVIEW_PB11MP_FLASH0_BASE, | ||
| 210 | .end = REALVIEW_PB11MP_FLASH0_BASE + REALVIEW_PB11MP_FLASH0_SIZE - 1, | ||
| 211 | .flags = IORESOURCE_MEM, | ||
| 212 | }, | ||
| 213 | [1] = { | ||
| 214 | .start = REALVIEW_PB11MP_FLASH1_BASE, | ||
| 215 | .end = REALVIEW_PB11MP_FLASH1_BASE + REALVIEW_PB11MP_FLASH1_SIZE - 1, | ||
| 216 | .flags = IORESOURCE_MEM, | ||
| 217 | }, | ||
| 218 | }; | ||
| 219 | |||
| 220 | static struct resource realview_pb11mp_smsc911x_resources[] = { | ||
| 221 | [0] = { | ||
| 222 | .start = REALVIEW_PB11MP_ETH_BASE, | ||
| 223 | .end = REALVIEW_PB11MP_ETH_BASE + SZ_64K - 1, | ||
| 224 | .flags = IORESOURCE_MEM, | ||
| 225 | }, | ||
| 226 | [1] = { | ||
| 227 | .start = IRQ_TC11MP_ETH, | ||
| 228 | .end = IRQ_TC11MP_ETH, | ||
| 229 | .flags = IORESOURCE_IRQ, | ||
| 230 | }, | ||
| 231 | }; | ||
| 232 | |||
| 233 | static struct platform_device realview_pb11mp_smsc911x_device = { | ||
| 234 | .name = "smc911x", | ||
| 235 | .id = 0, | ||
| 236 | .num_resources = ARRAY_SIZE(realview_pb11mp_smsc911x_resources), | ||
| 237 | .resource = realview_pb11mp_smsc911x_resources, | ||
| 238 | }; | ||
| 239 | |||
| 240 | struct resource realview_pb11mp_cf_resources[] = { | ||
| 241 | [0] = { | ||
| 242 | .start = REALVIEW_PB11MP_CF_BASE, | ||
| 243 | .end = REALVIEW_PB11MP_CF_BASE + SZ_4K - 1, | ||
| 244 | .flags = IORESOURCE_MEM, | ||
| 245 | }, | ||
| 246 | [1] = { | ||
| 247 | .start = REALVIEW_PB11MP_CF_MEM_BASE, | ||
| 248 | .end = REALVIEW_PB11MP_CF_MEM_BASE + SZ_4K - 1, | ||
| 249 | .flags = IORESOURCE_MEM, | ||
| 250 | }, | ||
| 251 | [2] = { | ||
| 252 | .start = -1, /* FIXME: Find correct irq */ | ||
| 253 | .end = -1, | ||
| 254 | .flags = IORESOURCE_IRQ, | ||
| 255 | }, | ||
| 256 | }; | ||
| 257 | |||
| 258 | struct platform_device realview_pb11mp_cf_device = { | ||
| 259 | .name = "compactflash", | ||
| 260 | .id = 0, | ||
| 261 | .num_resources = ARRAY_SIZE(realview_pb11mp_cf_resources), | ||
| 262 | .resource = realview_pb11mp_cf_resources, | ||
| 263 | }; | ||
| 264 | |||
| 265 | static void __init gic_init_irq(void) | ||
| 266 | { | ||
| 267 | unsigned int pldctrl; | ||
| 268 | |||
| 269 | /* new irq mode with no DCC */ | ||
| 270 | writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK)); | ||
| 271 | pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1); | ||
| 272 | pldctrl |= 2 << 22; | ||
| 273 | writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1); | ||
| 274 | writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); | ||
| 275 | |||
| 276 | /* ARM11MPCore test chip GIC, primary */ | ||
| 277 | gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE); | ||
| 278 | gic_dist_init(0, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), 29); | ||
| 279 | gic_cpu_init(0, gic_cpu_base_addr); | ||
| 280 | |||
| 281 | /* board GIC, secondary */ | ||
| 282 | gic_dist_init(1, __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), IRQ_PB11MP_GIC_START); | ||
| 283 | gic_cpu_init(1, __io_address(REALVIEW_PB11MP_GIC_CPU_BASE)); | ||
| 284 | gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1); | ||
| 285 | } | ||
| 286 | |||
| 287 | static void __init realview_pb11mp_timer_init(void) | ||
| 288 | { | ||
| 289 | timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE); | ||
| 290 | timer1_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE) + 0x20; | ||
| 291 | timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE); | ||
| 292 | timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20; | ||
| 293 | |||
| 294 | #ifdef CONFIG_LOCAL_TIMERS | ||
| 295 | twd_base_addr = __io_address(REALVIEW_TC11MP_TWD_BASE); | ||
| 296 | twd_size = REALVIEW_TC11MP_TWD_SIZE; | ||
| 297 | #endif | ||
| 298 | realview_timer_init(IRQ_TC11MP_TIMER0_1); | ||
| 299 | } | ||
| 300 | |||
| 301 | static struct sys_timer realview_pb11mp_timer = { | ||
| 302 | .init = realview_pb11mp_timer_init, | ||
| 303 | }; | ||
| 304 | |||
| 305 | static void __init realview_pb11mp_init(void) | ||
| 306 | { | ||
| 307 | int i; | ||
| 308 | |||
| 309 | #ifdef CONFIG_CACHE_L2X0 | ||
| 310 | /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled | ||
| 311 | * Bits: .... ...0 0111 1001 0000 .... .... .... */ | ||
| 312 | l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff); | ||
| 313 | #endif | ||
| 314 | |||
| 315 | clk_register(&realview_clcd_clk); | ||
| 316 | |||
| 317 | realview_flash_register(realview_pb11mp_flash_resource, | ||
| 318 | ARRAY_SIZE(realview_pb11mp_flash_resource)); | ||
| 319 | platform_device_register(&realview_pb11mp_smsc911x_device); | ||
| 320 | platform_device_register(&realview_i2c_device); | ||
| 321 | platform_device_register(&realview_pb11mp_cf_device); | ||
| 322 | |||
| 323 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | ||
| 324 | struct amba_device *d = amba_devs[i]; | ||
| 325 | amba_device_register(d, &iomem_resource); | ||
| 326 | } | ||
| 327 | |||
| 328 | #ifdef CONFIG_LEDS | ||
| 329 | leds_event = realview_leds_event; | ||
| 330 | #endif | ||
| 331 | } | ||
| 332 | |||
| 333 | MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore") | ||
| 334 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | ||
| 335 | .phys_io = REALVIEW_PB11MP_UART0_BASE, | ||
| 336 | .io_pg_offst = (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc, | ||
| 337 | .boot_params = 0x00000100, | ||
| 338 | .map_io = realview_pb11mp_map_io, | ||
| 339 | .init_irq = gic_init_irq, | ||
| 340 | .timer = &realview_pb11mp_timer, | ||
| 341 | .init_machine = realview_pb11mp_init, | ||
| 342 | MACHINE_END | ||
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index e2079cf9266f..cd3dc0834b3b 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig | |||
| @@ -97,6 +97,13 @@ config BAST_PC104_IRQ | |||
| 97 | Say Y here to enable the PC104 IRQ routing on the | 97 | Say Y here to enable the PC104 IRQ routing on the |
| 98 | Simtec BAST (EB2410ITX) | 98 | Simtec BAST (EB2410ITX) |
| 99 | 99 | ||
| 100 | config MACH_TCT_HAMMER | ||
| 101 | bool "TCT Hammer Board" | ||
| 102 | select CPU_S3C2410 | ||
| 103 | help | ||
| 104 | Say Y here if you are using the TinCanTools Hammer Board | ||
| 105 | <http://www.tincantools.com> | ||
| 106 | |||
| 100 | config MACH_VR1000 | 107 | config MACH_VR1000 |
| 101 | bool "Thorcom VR1000" | 108 | bool "Thorcom VR1000" |
| 102 | select PM_SIMTEC if PM | 109 | select PM_SIMTEC if PM |
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 3e7a85594d9c..cabc13ce09e4 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile | |||
| @@ -27,5 +27,6 @@ obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o | |||
| 27 | obj-$(CONFIG_MACH_OTOM) += mach-otom.o | 27 | obj-$(CONFIG_MACH_OTOM) += mach-otom.o |
| 28 | obj-$(CONFIG_MACH_AML_M5900) += mach-amlm5900.o | 28 | obj-$(CONFIG_MACH_AML_M5900) += mach-amlm5900.o |
| 29 | obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o | 29 | obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o |
| 30 | obj-$(CONFIG_MACH_TCT_HAMMER) += mach-tct_hammer.o | ||
| 30 | obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o usb-simtec.o | 31 | obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o usb-simtec.o |
| 31 | obj-$(CONFIG_MACH_QT2410) += mach-qt2410.o | 32 | obj-$(CONFIG_MACH_QT2410) += mach-qt2410.o |
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index 66175471fff3..661a2358ac22 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | #include <linux/list.h> | 16 | #include <linux/list.h> |
| 17 | #include <linux/timer.h> | 17 | #include <linux/timer.h> |
| 18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
| 19 | #include <linux/sysdev.h> | ||
| 19 | #include <linux/serial_core.h> | 20 | #include <linux/serial_core.h> |
| 20 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
| 21 | #include <linux/dm9000.h> | 22 | #include <linux/dm9000.h> |
| @@ -236,6 +237,36 @@ static struct platform_device bast_device_nor = { | |||
| 236 | 237 | ||
| 237 | /* NAND Flash on BAST board */ | 238 | /* NAND Flash on BAST board */ |
| 238 | 239 | ||
| 240 | #ifdef CONFIG_PM | ||
| 241 | static int bast_pm_suspend(struct sys_device *sd, pm_message_t state) | ||
| 242 | { | ||
| 243 | /* ensure that an nRESET is not generated on resume. */ | ||
| 244 | s3c2410_gpio_setpin(S3C2410_GPA21, 1); | ||
| 245 | s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT); | ||
| 246 | |||
| 247 | return 0; | ||
| 248 | } | ||
| 249 | |||
| 250 | static int bast_pm_resume(struct sys_device *sd) | ||
| 251 | { | ||
| 252 | s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT); | ||
| 253 | return 0; | ||
| 254 | } | ||
| 255 | |||
| 256 | #else | ||
| 257 | #define bast_pm_suspend NULL | ||
| 258 | #define bast_pm_resume NULL | ||
| 259 | #endif | ||
| 260 | |||
| 261 | static struct sysdev_class bast_pm_sysclass = { | ||
| 262 | .name = "mach-bast", | ||
| 263 | .suspend = bast_pm_suspend, | ||
| 264 | .resume = bast_pm_resume, | ||
| 265 | }; | ||
| 266 | |||
| 267 | static struct sys_device bast_pm_sysdev = { | ||
| 268 | .cls = &bast_pm_sysclass, | ||
| 269 | }; | ||
| 239 | 270 | ||
| 240 | static int smartmedia_map[] = { 0 }; | 271 | static int smartmedia_map[] = { 0 }; |
| 241 | static int chip0_map[] = { 1 }; | 272 | static int chip0_map[] = { 1 }; |
| @@ -561,10 +592,10 @@ static void __init bast_map_io(void) | |||
| 561 | { | 592 | { |
| 562 | /* initialise the clocks */ | 593 | /* initialise the clocks */ |
| 563 | 594 | ||
| 564 | s3c24xx_dclk0.parent = NULL; | 595 | s3c24xx_dclk0.parent = &clk_upll; |
| 565 | s3c24xx_dclk0.rate = 12*1000*1000; | 596 | s3c24xx_dclk0.rate = 12*1000*1000; |
| 566 | 597 | ||
| 567 | s3c24xx_dclk1.parent = NULL; | 598 | s3c24xx_dclk1.parent = &clk_upll; |
| 568 | s3c24xx_dclk1.rate = 24*1000*1000; | 599 | s3c24xx_dclk1.rate = 24*1000*1000; |
| 569 | 600 | ||
| 570 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; | 601 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; |
| @@ -586,6 +617,9 @@ static void __init bast_map_io(void) | |||
| 586 | 617 | ||
| 587 | static void __init bast_init(void) | 618 | static void __init bast_init(void) |
| 588 | { | 619 | { |
| 620 | sysdev_class_register(&bast_pm_sysclass); | ||
| 621 | sysdev_register(&bast_pm_sysdev); | ||
| 622 | |||
| 589 | s3c24xx_fb_set_platdata(&bast_fb_info); | 623 | s3c24xx_fb_set_platdata(&bast_fb_info); |
| 590 | platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices)); | 624 | platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices)); |
| 591 | } | 625 | } |
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c new file mode 100644 index 000000000000..d90d445ccfb4 --- /dev/null +++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c | |||
| @@ -0,0 +1,160 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c2410/mach-tct_hammer.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2007 TinCanTools | ||
| 4 | * David Anders <danders@amltd.com> | ||
| 5 | |||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License as | ||
| 8 | * published by the Free Software Foundation; either version 2 of | ||
| 9 | * the License, or (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 19 | * MA 02111-1307 USA | ||
| 20 | * | ||
| 21 | * @History: | ||
| 22 | * derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by | ||
| 23 | * Ben Dooks <ben@simtec.co.uk> | ||
| 24 | * | ||
| 25 | ***********************************************************************/ | ||
| 26 | |||
| 27 | #include <linux/kernel.h> | ||
| 28 | #include <linux/types.h> | ||
| 29 | #include <linux/interrupt.h> | ||
| 30 | #include <linux/list.h> | ||
| 31 | #include <linux/timer.h> | ||
| 32 | #include <linux/init.h> | ||
| 33 | #include <linux/device.h> | ||
| 34 | #include <linux/platform_device.h> | ||
| 35 | #include <linux/serial_core.h> | ||
| 36 | |||
| 37 | #include <asm/mach/arch.h> | ||
| 38 | #include <asm/mach/map.h> | ||
| 39 | #include <asm/mach/irq.h> | ||
| 40 | #include <asm/mach/flash.h> | ||
| 41 | |||
| 42 | #include <asm/hardware.h> | ||
| 43 | #include <asm/io.h> | ||
| 44 | #include <asm/irq.h> | ||
| 45 | #include <asm/mach-types.h> | ||
| 46 | |||
| 47 | #include <asm/plat-s3c/regs-serial.h> | ||
| 48 | #include <asm/plat-s3c24xx/devs.h> | ||
| 49 | #include <asm/plat-s3c24xx/cpu.h> | ||
| 50 | |||
| 51 | #ifdef CONFIG_MTD_PARTITIONS | ||
| 52 | |||
| 53 | #include <linux/mtd/mtd.h> | ||
| 54 | #include <linux/mtd/partitions.h> | ||
| 55 | #include <linux/mtd/map.h> | ||
| 56 | #include <linux/mtd/physmap.h> | ||
| 57 | |||
| 58 | static struct resource tct_hammer_nor_resource = { | ||
| 59 | .start = 0x00000000, | ||
| 60 | .end = 0x01000000 - 1, | ||
| 61 | .flags = IORESOURCE_MEM, | ||
| 62 | }; | ||
| 63 | |||
| 64 | static struct mtd_partition tct_hammer_mtd_partitions[] = { | ||
| 65 | { | ||
| 66 | .name = "System", | ||
| 67 | .size = 0x240000, | ||
| 68 | .offset = 0, | ||
| 69 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 70 | }, { | ||
| 71 | .name = "JFFS2", | ||
| 72 | .size = MTDPART_SIZ_FULL, | ||
| 73 | .offset = MTDPART_OFS_APPEND, | ||
| 74 | } | ||
| 75 | }; | ||
| 76 | |||
| 77 | static struct physmap_flash_data tct_hammer_flash_data = { | ||
| 78 | .width = 2, | ||
| 79 | .parts = tct_hammer_mtd_partitions, | ||
| 80 | .nr_parts = ARRAY_SIZE(tct_hammer_mtd_partitions), | ||
| 81 | }; | ||
| 82 | |||
| 83 | static struct platform_device tct_hammer_device_nor = { | ||
| 84 | .name = "physmap-flash", | ||
| 85 | .id = 0, | ||
| 86 | .dev = { | ||
| 87 | .platform_data = &tct_hammer_flash_data, | ||
| 88 | }, | ||
| 89 | .num_resources = 1, | ||
| 90 | .resource = &tct_hammer_nor_resource, | ||
| 91 | }; | ||
| 92 | |||
| 93 | #endif | ||
| 94 | |||
| 95 | static struct map_desc tct_hammer_iodesc[] __initdata = { | ||
| 96 | }; | ||
| 97 | |||
| 98 | #define UCON S3C2410_UCON_DEFAULT | ||
| 99 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB | ||
| 100 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE | ||
| 101 | |||
| 102 | static struct s3c2410_uartcfg tct_hammer_uartcfgs[] = { | ||
| 103 | [0] = { | ||
| 104 | .hwport = 0, | ||
| 105 | .flags = 0, | ||
| 106 | .ucon = UCON, | ||
| 107 | .ulcon = ULCON, | ||
| 108 | .ufcon = UFCON, | ||
| 109 | }, | ||
| 110 | [1] = { | ||
| 111 | .hwport = 1, | ||
| 112 | .flags = 0, | ||
| 113 | .ucon = UCON, | ||
| 114 | .ulcon = ULCON, | ||
| 115 | .ufcon = UFCON, | ||
| 116 | }, | ||
| 117 | [2] = { | ||
| 118 | .hwport = 2, | ||
| 119 | .flags = 0, | ||
| 120 | .ucon = UCON, | ||
| 121 | .ulcon = ULCON, | ||
| 122 | .ufcon = UFCON, | ||
| 123 | } | ||
| 124 | }; | ||
| 125 | |||
| 126 | |||
| 127 | static struct platform_device *tct_hammer_devices[] __initdata = { | ||
| 128 | &s3c_device_adc, | ||
| 129 | &s3c_device_wdt, | ||
| 130 | &s3c_device_i2c, | ||
| 131 | &s3c_device_usb, | ||
| 132 | &s3c_device_rtc, | ||
| 133 | &s3c_device_usbgadget, | ||
| 134 | &s3c_device_sdi, | ||
| 135 | #ifdef CONFIG_MTD_PARTITIONS | ||
| 136 | &tct_hammer_device_nor, | ||
| 137 | #endif | ||
| 138 | }; | ||
| 139 | |||
| 140 | static void __init tct_hammer_map_io(void) | ||
| 141 | { | ||
| 142 | s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc)); | ||
| 143 | s3c24xx_init_clocks(0); | ||
| 144 | s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs)); | ||
| 145 | } | ||
| 146 | |||
| 147 | static void __init tct_hammer_init(void) | ||
| 148 | { | ||
| 149 | platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices)); | ||
| 150 | } | ||
| 151 | |||
| 152 | MACHINE_START(TCT_HAMMER, "TCT_HAMMER") | ||
| 153 | .phys_io = S3C2410_PA_UART, | ||
| 154 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | ||
| 155 | .boot_params = S3C2410_SDRAM_PA + 0x100, | ||
| 156 | .map_io = tct_hammer_map_io, | ||
| 157 | .init_irq = s3c24xx_init_irq, | ||
| 158 | .init_machine = tct_hammer_init, | ||
| 159 | .timer = &s3c24xx_timer, | ||
| 160 | MACHINE_END | ||
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index 3aade7b78fe5..c56423373ff3 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c | |||
| @@ -393,7 +393,7 @@ static void __init vr1000_map_io(void) | |||
| 393 | { | 393 | { |
| 394 | /* initialise clock sources */ | 394 | /* initialise clock sources */ |
| 395 | 395 | ||
| 396 | s3c24xx_dclk0.parent = NULL; | 396 | s3c24xx_dclk0.parent = &clk_upll; |
| 397 | s3c24xx_dclk0.rate = 12*1000*1000; | 397 | s3c24xx_dclk0.rate = 12*1000*1000; |
| 398 | 398 | ||
| 399 | s3c24xx_dclk1.parent = NULL; | 399 | s3c24xx_dclk1.parent = NULL; |
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index abf1599c9f97..98a0de924c22 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c | |||
| @@ -175,7 +175,7 @@ void __init s3c2412_init_clocks(int xtal) | |||
| 175 | /* work out clock scalings */ | 175 | /* work out clock scalings */ |
| 176 | 176 | ||
| 177 | hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1); | 177 | hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1); |
| 178 | hclk /= ((tmp & S3C2421_CLKDIVN_ARMDIVN) ? 2 : 1); | 178 | hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1); |
| 179 | pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1); | 179 | pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1); |
| 180 | 180 | ||
| 181 | /* print brieft summary of clocks, etc */ | 181 | /* print brieft summary of clocks, etc */ |
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c index 3d3dfa95db8e..47258915a2f9 100644 --- a/arch/arm/mach-s3c2440/mach-anubis.c +++ b/arch/arm/mach-s3c2440/mach-anubis.c | |||
| @@ -413,10 +413,10 @@ static void __init anubis_map_io(void) | |||
| 413 | { | 413 | { |
| 414 | /* initialise the clocks */ | 414 | /* initialise the clocks */ |
| 415 | 415 | ||
| 416 | s3c24xx_dclk0.parent = NULL; | 416 | s3c24xx_dclk0.parent = &clk_upll; |
| 417 | s3c24xx_dclk0.rate = 12*1000*1000; | 417 | s3c24xx_dclk0.rate = 12*1000*1000; |
| 418 | 418 | ||
| 419 | s3c24xx_dclk1.parent = NULL; | 419 | s3c24xx_dclk1.parent = &clk_upll; |
| 420 | s3c24xx_dclk1.rate = 24*1000*1000; | 420 | s3c24xx_dclk1.rate = 24*1000*1000; |
| 421 | 421 | ||
| 422 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; | 422 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; |
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index 78af7664988b..8a8acdbd072d 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | #include <linux/device.h> | 18 | #include <linux/device.h> |
| 19 | #include <linux/sysdev.h> | 19 | #include <linux/sysdev.h> |
| 20 | #include <linux/serial_core.h> | 20 | #include <linux/serial_core.h> |
| 21 | #include <linux/clk.h> | ||
| 21 | 22 | ||
| 22 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 23 | #include <asm/mach/map.h> | 24 | #include <asm/mach/map.h> |
| @@ -344,10 +345,10 @@ static void __init osiris_map_io(void) | |||
| 344 | 345 | ||
| 345 | /* initialise the clocks */ | 346 | /* initialise the clocks */ |
| 346 | 347 | ||
| 347 | s3c24xx_dclk0.parent = NULL; | 348 | s3c24xx_dclk0.parent = &clk_upll; |
| 348 | s3c24xx_dclk0.rate = 12*1000*1000; | 349 | s3c24xx_dclk0.rate = 12*1000*1000; |
| 349 | 350 | ||
| 350 | s3c24xx_dclk1.parent = NULL; | 351 | s3c24xx_dclk1.parent = &clk_upll; |
| 351 | s3c24xx_dclk1.rate = 24*1000*1000; | 352 | s3c24xx_dclk1.rate = 24*1000*1000; |
| 352 | 353 | ||
| 353 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; | 354 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; |
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile index 7a61e8d33ab7..8e0244631d65 100644 --- a/arch/arm/mach-sa1100/Makefile +++ b/arch/arm/mach-sa1100/Makefile | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := clock.o generic.o irq.o dma.o time.o #nmi-oopser.o | 6 | obj-y := clock.o generic.o gpio.o irq.o dma.o time.o #nmi-oopser.o |
| 7 | obj-m := | 7 | obj-m := |
| 8 | obj-n := | 8 | obj-n := |
| 9 | obj- := | 9 | obj- := |
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 5c84c604ed86..0c2fa1c4fb4c 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c | |||
| @@ -139,37 +139,6 @@ unsigned long long sched_clock(void) | |||
| 139 | return v; | 139 | return v; |
| 140 | } | 140 | } |
| 141 | 141 | ||
| 142 | int gpio_direction_input(unsigned gpio) | ||
| 143 | { | ||
| 144 | unsigned long flags; | ||
| 145 | |||
| 146 | if (gpio > GPIO_MAX) | ||
| 147 | return -EINVAL; | ||
| 148 | |||
| 149 | local_irq_save(flags); | ||
| 150 | GPDR &= ~GPIO_GPIO(gpio); | ||
| 151 | local_irq_restore(flags); | ||
| 152 | return 0; | ||
| 153 | } | ||
| 154 | |||
| 155 | EXPORT_SYMBOL(gpio_direction_input); | ||
| 156 | |||
| 157 | int gpio_direction_output(unsigned gpio, int value) | ||
| 158 | { | ||
| 159 | unsigned long flags; | ||
| 160 | |||
| 161 | if (gpio > GPIO_MAX) | ||
| 162 | return -EINVAL; | ||
| 163 | |||
| 164 | local_irq_save(flags); | ||
| 165 | gpio_set_value(gpio, value); | ||
| 166 | GPDR |= GPIO_GPIO(gpio); | ||
| 167 | local_irq_restore(flags); | ||
| 168 | return 0; | ||
| 169 | } | ||
| 170 | |||
| 171 | EXPORT_SYMBOL(gpio_direction_output); | ||
| 172 | |||
| 173 | /* | 142 | /* |
| 174 | * Default power-off for SA1100 | 143 | * Default power-off for SA1100 |
| 175 | */ | 144 | */ |
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h index f085d68e568e..793c2e6c991f 100644 --- a/arch/arm/mach-sa1100/generic.h +++ b/arch/arm/mach-sa1100/generic.h | |||
| @@ -9,6 +9,7 @@ struct sys_timer; | |||
| 9 | extern struct sys_timer sa1100_timer; | 9 | extern struct sys_timer sa1100_timer; |
| 10 | extern void __init sa1100_map_io(void); | 10 | extern void __init sa1100_map_io(void); |
| 11 | extern void __init sa1100_init_irq(void); | 11 | extern void __init sa1100_init_irq(void); |
| 12 | extern void __init sa1100_init_gpio(void); | ||
| 12 | 13 | ||
| 13 | #define SET_BANK(__nr,__start,__size) \ | 14 | #define SET_BANK(__nr,__start,__size) \ |
| 14 | mi->bank[__nr].start = (__start), \ | 15 | mi->bank[__nr].start = (__start), \ |
diff --git a/arch/arm/mach-sa1100/gpio.c b/arch/arm/mach-sa1100/gpio.c new file mode 100644 index 000000000000..372f1f4f54a1 --- /dev/null +++ b/arch/arm/mach-sa1100/gpio.c | |||
| @@ -0,0 +1,65 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-sa1100/gpio.c | ||
| 3 | * | ||
| 4 | * Generic SA-1100 GPIO handling | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/module.h> | ||
| 13 | |||
| 14 | #include <asm/gpio.h> | ||
| 15 | #include <asm/hardware.h> | ||
| 16 | #include "generic.h" | ||
| 17 | |||
| 18 | static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset) | ||
| 19 | { | ||
| 20 | return GPLR & GPIO_GPIO(offset); | ||
| 21 | } | ||
| 22 | |||
| 23 | static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | ||
| 24 | { | ||
| 25 | if (value) | ||
| 26 | GPSR = GPIO_GPIO(offset); | ||
| 27 | else | ||
| 28 | GPCR = GPIO_GPIO(offset); | ||
| 29 | } | ||
| 30 | |||
| 31 | static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset) | ||
| 32 | { | ||
| 33 | unsigned long flags; | ||
| 34 | |||
| 35 | local_irq_save(flags); | ||
| 36 | GPDR &= ~GPIO_GPIO(offset); | ||
| 37 | local_irq_restore(flags); | ||
| 38 | return 0; | ||
| 39 | } | ||
| 40 | |||
| 41 | static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value) | ||
| 42 | { | ||
| 43 | unsigned long flags; | ||
| 44 | |||
| 45 | local_irq_save(flags); | ||
| 46 | sa1100_gpio_set(chip, offset, value); | ||
| 47 | GPDR |= GPIO_GPIO(offset); | ||
| 48 | local_irq_restore(flags); | ||
| 49 | return 0; | ||
| 50 | } | ||
| 51 | |||
| 52 | static struct gpio_chip sa1100_gpio_chip = { | ||
| 53 | .label = "gpio", | ||
| 54 | .direction_input = sa1100_direction_input, | ||
| 55 | .direction_output = sa1100_direction_output, | ||
| 56 | .set = sa1100_gpio_set, | ||
| 57 | .get = sa1100_gpio_get, | ||
| 58 | .base = 0, | ||
| 59 | .ngpio = GPIO_MAX + 1, | ||
| 60 | }; | ||
| 61 | |||
| 62 | void __init sa1100_init_gpio(void) | ||
| 63 | { | ||
| 64 | gpiochip_add(&sa1100_gpio_chip); | ||
| 65 | } | ||
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index 3dc17d7bf38e..fa0403af7eec 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c | |||
| @@ -347,4 +347,6 @@ void __init sa1100_init_irq(void) | |||
| 347 | */ | 347 | */ |
| 348 | set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip); | 348 | set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip); |
| 349 | set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); | 349 | set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); |
| 350 | |||
| 351 | sa1100_init_gpio(); | ||
| 350 | } | 352 | } |
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index c2677368d6af..a9799cb35b74 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c | |||
| @@ -13,67 +13,69 @@ | |||
| 13 | #include <linux/interrupt.h> | 13 | #include <linux/interrupt.h> |
| 14 | #include <linux/irq.h> | 14 | #include <linux/irq.h> |
| 15 | #include <linux/timex.h> | 15 | #include <linux/timex.h> |
| 16 | #include <linux/signal.h> | 16 | #include <linux/clockchips.h> |
| 17 | #include <linux/clocksource.h> | ||
| 18 | 17 | ||
| 19 | #include <asm/mach/time.h> | 18 | #include <asm/mach/time.h> |
| 20 | #include <asm/hardware.h> | 19 | #include <asm/hardware.h> |
| 21 | 20 | ||
| 22 | #define RTC_DEF_DIVIDER (32768 - 1) | 21 | #define MIN_OSCR_DELTA 2 |
| 23 | #define RTC_DEF_TRIM 0 | ||
| 24 | 22 | ||
| 25 | static int sa1100_set_rtc(void) | 23 | static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id) |
| 26 | { | 24 | { |
| 27 | unsigned long current_time = xtime.tv_sec; | 25 | struct clock_event_device *c = dev_id; |
| 28 | 26 | ||
| 29 | if (RTSR & RTSR_ALE) { | 27 | /* Disarm the compare/match, signal the event. */ |
| 30 | /* make sure not to forward the clock over an alarm */ | 28 | OIER &= ~OIER_E0; |
| 31 | unsigned long alarm = RTAR; | 29 | OSSR = OSSR_M0; |
| 32 | if (current_time >= alarm && alarm >= RCNR) | 30 | c->event_handler(c); |
| 33 | return -ERESTARTSYS; | ||
| 34 | } | ||
| 35 | RCNR = current_time; | ||
| 36 | return 0; | ||
| 37 | } | ||
| 38 | 31 | ||
| 39 | #ifdef CONFIG_NO_IDLE_HZ | 32 | return IRQ_HANDLED; |
| 40 | static unsigned long initial_match; | 33 | } |
| 41 | static int match_posponed; | ||
| 42 | #endif | ||
| 43 | 34 | ||
| 44 | static irqreturn_t | 35 | static int |
| 45 | sa1100_timer_interrupt(int irq, void *dev_id) | 36 | sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c) |
| 46 | { | 37 | { |
| 47 | unsigned int next_match; | 38 | unsigned long flags, next, oscr; |
| 48 | 39 | ||
| 49 | #ifdef CONFIG_NO_IDLE_HZ | 40 | raw_local_irq_save(flags); |
| 50 | if (match_posponed) { | 41 | OIER |= OIER_E0; |
| 51 | match_posponed = 0; | 42 | next = OSCR + delta; |
| 52 | OSMR0 = initial_match; | 43 | OSMR0 = next; |
| 53 | } | 44 | oscr = OSCR; |
| 54 | #endif | 45 | raw_local_irq_restore(flags); |
| 55 | 46 | ||
| 56 | /* | 47 | return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0; |
| 57 | * Loop until we get ahead of the free running timer. | 48 | } |
| 58 | * This ensures an exact clock tick count and time accuracy. | ||
| 59 | * Since IRQs are disabled at this point, coherence between | ||
| 60 | * lost_ticks(updated in do_timer()) and the match reg value is | ||
| 61 | * ensured, hence we can use do_gettimeofday() from interrupt | ||
| 62 | * handlers. | ||
| 63 | */ | ||
| 64 | do { | ||
| 65 | timer_tick(); | ||
| 66 | OSSR = OSSR_M0; /* Clear match on timer 0 */ | ||
| 67 | next_match = (OSMR0 += LATCH); | ||
| 68 | } while ((signed long)(next_match - OSCR) <= 0); | ||
| 69 | 49 | ||
| 70 | return IRQ_HANDLED; | 50 | static void |
| 51 | sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c) | ||
| 52 | { | ||
| 53 | unsigned long flags; | ||
| 54 | |||
| 55 | switch (mode) { | ||
| 56 | case CLOCK_EVT_MODE_ONESHOT: | ||
| 57 | case CLOCK_EVT_MODE_UNUSED: | ||
| 58 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
| 59 | raw_local_irq_save(flags); | ||
| 60 | OIER &= ~OIER_E0; | ||
| 61 | OSSR = OSSR_M0; | ||
| 62 | raw_local_irq_restore(flags); | ||
| 63 | break; | ||
| 64 | |||
| 65 | case CLOCK_EVT_MODE_RESUME: | ||
| 66 | case CLOCK_EVT_MODE_PERIODIC: | ||
| 67 | break; | ||
| 68 | } | ||
| 71 | } | 69 | } |
| 72 | 70 | ||
| 73 | static struct irqaction sa1100_timer_irq = { | 71 | static struct clock_event_device ckevt_sa1100_osmr0 = { |
| 74 | .name = "SA11xx Timer Tick", | 72 | .name = "osmr0", |
| 75 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | 73 | .features = CLOCK_EVT_FEAT_ONESHOT, |
| 76 | .handler = sa1100_timer_interrupt, | 74 | .shift = 32, |
| 75 | .rating = 200, | ||
| 76 | .cpumask = CPU_MASK_CPU0, | ||
| 77 | .set_next_event = sa1100_osmr0_set_next_event, | ||
| 78 | .set_mode = sa1100_osmr0_set_mode, | ||
| 77 | }; | 79 | }; |
| 78 | 80 | ||
| 79 | static cycle_t sa1100_read_oscr(void) | 81 | static cycle_t sa1100_read_oscr(void) |
| @@ -90,62 +92,34 @@ static struct clocksource cksrc_sa1100_oscr = { | |||
| 90 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 92 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 91 | }; | 93 | }; |
| 92 | 94 | ||
| 95 | static struct irqaction sa1100_timer_irq = { | ||
| 96 | .name = "ost0", | ||
| 97 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
| 98 | .handler = sa1100_ost0_interrupt, | ||
| 99 | .dev_id = &ckevt_sa1100_osmr0, | ||
| 100 | }; | ||
| 101 | |||
| 93 | static void __init sa1100_timer_init(void) | 102 | static void __init sa1100_timer_init(void) |
| 94 | { | 103 | { |
| 95 | unsigned long flags; | ||
| 96 | |||
| 97 | set_rtc = sa1100_set_rtc; | ||
| 98 | |||
| 99 | OIER = 0; /* disable any timer interrupts */ | 104 | OIER = 0; /* disable any timer interrupts */ |
| 100 | OSSR = 0xf; /* clear status on all timers */ | 105 | OSSR = 0xf; /* clear status on all timers */ |
| 101 | setup_irq(IRQ_OST0, &sa1100_timer_irq); | 106 | |
| 102 | local_irq_save(flags); | 107 | ckevt_sa1100_osmr0.mult = |
| 103 | OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */ | 108 | div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift); |
| 104 | OSMR0 = OSCR + LATCH; /* set initial match */ | 109 | ckevt_sa1100_osmr0.max_delta_ns = |
| 105 | local_irq_restore(flags); | 110 | clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0); |
| 111 | ckevt_sa1100_osmr0.min_delta_ns = | ||
| 112 | clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1; | ||
| 106 | 113 | ||
| 107 | cksrc_sa1100_oscr.mult = | 114 | cksrc_sa1100_oscr.mult = |
| 108 | clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_sa1100_oscr.shift); | 115 | clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_sa1100_oscr.shift); |
| 109 | 116 | ||
| 110 | clocksource_register(&cksrc_sa1100_oscr); | 117 | setup_irq(IRQ_OST0, &sa1100_timer_irq); |
| 111 | } | ||
| 112 | |||
| 113 | #ifdef CONFIG_NO_IDLE_HZ | ||
| 114 | static int sa1100_dyn_tick_enable_disable(void) | ||
| 115 | { | ||
| 116 | /* nothing to do */ | ||
| 117 | return 0; | ||
| 118 | } | ||
| 119 | |||
| 120 | static void sa1100_dyn_tick_reprogram(unsigned long ticks) | ||
| 121 | { | ||
| 122 | if (ticks > 1) { | ||
| 123 | initial_match = OSMR0; | ||
| 124 | OSMR0 = initial_match + ticks * LATCH; | ||
| 125 | match_posponed = 1; | ||
| 126 | } | ||
| 127 | } | ||
| 128 | 118 | ||
| 129 | static irqreturn_t | 119 | clocksource_register(&cksrc_sa1100_oscr); |
| 130 | sa1100_dyn_tick_handler(int irq, void *dev_id) | 120 | clockevents_register_device(&ckevt_sa1100_osmr0); |
| 131 | { | ||
| 132 | if (match_posponed) { | ||
| 133 | match_posponed = 0; | ||
| 134 | OSMR0 = initial_match; | ||
| 135 | if ((signed long)(initial_match - OSCR) <= 0) | ||
| 136 | return sa1100_timer_interrupt(irq, dev_id); | ||
| 137 | } | ||
| 138 | return IRQ_NONE; | ||
| 139 | } | 121 | } |
| 140 | 122 | ||
| 141 | static struct dyn_tick_timer sa1100_dyn_tick = { | ||
| 142 | .enable = sa1100_dyn_tick_enable_disable, | ||
| 143 | .disable = sa1100_dyn_tick_enable_disable, | ||
| 144 | .reprogram = sa1100_dyn_tick_reprogram, | ||
| 145 | .handler = sa1100_dyn_tick_handler, | ||
| 146 | }; | ||
| 147 | #endif | ||
| 148 | |||
| 149 | #ifdef CONFIG_PM | 123 | #ifdef CONFIG_PM |
| 150 | unsigned long osmr[4], oier; | 124 | unsigned long osmr[4], oier; |
| 151 | 125 | ||
| @@ -181,7 +155,4 @@ struct sys_timer sa1100_timer = { | |||
| 181 | .init = sa1100_timer_init, | 155 | .init = sa1100_timer_init, |
| 182 | .suspend = sa1100_timer_suspend, | 156 | .suspend = sa1100_timer_suspend, |
| 183 | .resume = sa1100_timer_resume, | 157 | .resume = sa1100_timer_resume, |
| 184 | #ifdef CONFIG_NO_IDLE_HZ | ||
| 185 | .dyn_tick = &sa1100_dyn_tick, | ||
| 186 | #endif | ||
| 187 | }; | 158 | }; |
diff --git a/arch/arm/mach-versatile/clock.c b/arch/arm/mach-versatile/clock.c index 9858c96560e2..9336508ec0b2 100644 --- a/arch/arm/mach-versatile/clock.c +++ b/arch/arm/mach-versatile/clock.c | |||
| @@ -17,7 +17,6 @@ | |||
| 17 | #include <linux/clk.h> | 17 | #include <linux/clk.h> |
| 18 | #include <linux/mutex.h> | 18 | #include <linux/mutex.h> |
| 19 | 19 | ||
| 20 | #include <asm/semaphore.h> | ||
| 21 | #include <asm/hardware/icst307.h> | 20 | #include <asm/hardware/icst307.h> |
| 22 | 21 | ||
| 23 | #include "clock.h" | 22 | #include "clock.h" |
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 76348f060f27..a92a577c1b65 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig | |||
| @@ -18,6 +18,7 @@ config CPU_ARM610 | |||
| 18 | select CPU_CP15_MMU | 18 | select CPU_CP15_MMU |
| 19 | select CPU_COPY_V3 if MMU | 19 | select CPU_COPY_V3 if MMU |
| 20 | select CPU_TLB_V3 if MMU | 20 | select CPU_TLB_V3 if MMU |
| 21 | select CPU_PABRT_NOIFAR | ||
| 21 | help | 22 | help |
| 22 | The ARM610 is the successor to the ARM3 processor | 23 | The ARM610 is the successor to the ARM3 processor |
| 23 | and was produced by VLSI Technology Inc. | 24 | and was produced by VLSI Technology Inc. |
| @@ -31,6 +32,7 @@ config CPU_ARM7TDMI | |||
| 31 | depends on !MMU | 32 | depends on !MMU |
| 32 | select CPU_32v4T | 33 | select CPU_32v4T |
| 33 | select CPU_ABRT_LV4T | 34 | select CPU_ABRT_LV4T |
| 35 | select CPU_PABRT_NOIFAR | ||
| 34 | select CPU_CACHE_V4 | 36 | select CPU_CACHE_V4 |
| 35 | help | 37 | help |
| 36 | A 32-bit RISC microprocessor based on the ARM7 processor core | 38 | A 32-bit RISC microprocessor based on the ARM7 processor core |
| @@ -49,6 +51,7 @@ config CPU_ARM710 | |||
| 49 | select CPU_CP15_MMU | 51 | select CPU_CP15_MMU |
| 50 | select CPU_COPY_V3 if MMU | 52 | select CPU_COPY_V3 if MMU |
| 51 | select CPU_TLB_V3 if MMU | 53 | select CPU_TLB_V3 if MMU |
| 54 | select CPU_PABRT_NOIFAR | ||
| 52 | help | 55 | help |
| 53 | A 32-bit RISC microprocessor based on the ARM7 processor core | 56 | A 32-bit RISC microprocessor based on the ARM7 processor core |
| 54 | designed by Advanced RISC Machines Ltd. The ARM710 is the | 57 | designed by Advanced RISC Machines Ltd. The ARM710 is the |
| @@ -64,6 +67,7 @@ config CPU_ARM720T | |||
| 64 | default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X | 67 | default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X |
| 65 | select CPU_32v4T | 68 | select CPU_32v4T |
| 66 | select CPU_ABRT_LV4T | 69 | select CPU_ABRT_LV4T |
| 70 | select CPU_PABRT_NOIFAR | ||
| 67 | select CPU_CACHE_V4 | 71 | select CPU_CACHE_V4 |
| 68 | select CPU_CACHE_VIVT | 72 | select CPU_CACHE_VIVT |
| 69 | select CPU_CP15_MMU | 73 | select CPU_CP15_MMU |
| @@ -82,6 +86,7 @@ config CPU_ARM740T | |||
| 82 | depends on !MMU | 86 | depends on !MMU |
| 83 | select CPU_32v4T | 87 | select CPU_32v4T |
| 84 | select CPU_ABRT_LV4T | 88 | select CPU_ABRT_LV4T |
| 89 | select CPU_PABRT_NOIFAR | ||
| 85 | select CPU_CACHE_V3 # although the core is v4t | 90 | select CPU_CACHE_V3 # although the core is v4t |
| 86 | select CPU_CP15_MPU | 91 | select CPU_CP15_MPU |
| 87 | help | 92 | help |
| @@ -98,6 +103,7 @@ config CPU_ARM9TDMI | |||
| 98 | depends on !MMU | 103 | depends on !MMU |
| 99 | select CPU_32v4T | 104 | select CPU_32v4T |
| 100 | select CPU_ABRT_NOMMU | 105 | select CPU_ABRT_NOMMU |
| 106 | select CPU_PABRT_NOIFAR | ||
| 101 | select CPU_CACHE_V4 | 107 | select CPU_CACHE_V4 |
| 102 | help | 108 | help |
| 103 | A 32-bit RISC microprocessor based on the ARM9 processor core | 109 | A 32-bit RISC microprocessor based on the ARM9 processor core |
| @@ -113,6 +119,7 @@ config CPU_ARM920T | |||
| 113 | default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200 | 119 | default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200 |
| 114 | select CPU_32v4T | 120 | select CPU_32v4T |
| 115 | select CPU_ABRT_EV4T | 121 | select CPU_ABRT_EV4T |
| 122 | select CPU_PABRT_NOIFAR | ||
| 116 | select CPU_CACHE_V4WT | 123 | select CPU_CACHE_V4WT |
| 117 | select CPU_CACHE_VIVT | 124 | select CPU_CACHE_VIVT |
| 118 | select CPU_CP15_MMU | 125 | select CPU_CP15_MMU |
| @@ -135,6 +142,7 @@ config CPU_ARM922T | |||
| 135 | default y if ARCH_LH7A40X || ARCH_KS8695 | 142 | default y if ARCH_LH7A40X || ARCH_KS8695 |
| 136 | select CPU_32v4T | 143 | select CPU_32v4T |
| 137 | select CPU_ABRT_EV4T | 144 | select CPU_ABRT_EV4T |
| 145 | select CPU_PABRT_NOIFAR | ||
| 138 | select CPU_CACHE_V4WT | 146 | select CPU_CACHE_V4WT |
| 139 | select CPU_CACHE_VIVT | 147 | select CPU_CACHE_VIVT |
| 140 | select CPU_CP15_MMU | 148 | select CPU_CP15_MMU |
| @@ -155,6 +163,7 @@ config CPU_ARM925T | |||
| 155 | default y if ARCH_OMAP15XX | 163 | default y if ARCH_OMAP15XX |
| 156 | select CPU_32v4T | 164 | select CPU_32v4T |
| 157 | select CPU_ABRT_EV4T | 165 | select CPU_ABRT_EV4T |
| 166 | select CPU_PABRT_NOIFAR | ||
| 158 | select CPU_CACHE_V4WT | 167 | select CPU_CACHE_V4WT |
| 159 | select CPU_CACHE_VIVT | 168 | select CPU_CACHE_VIVT |
| 160 | select CPU_CP15_MMU | 169 | select CPU_CP15_MMU |
| @@ -175,6 +184,7 @@ config CPU_ARM926T | |||
| 175 | default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI | 184 | default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI |
| 176 | select CPU_32v5 | 185 | select CPU_32v5 |
| 177 | select CPU_ABRT_EV5TJ | 186 | select CPU_ABRT_EV5TJ |
| 187 | select CPU_PABRT_NOIFAR | ||
| 178 | select CPU_CACHE_VIVT | 188 | select CPU_CACHE_VIVT |
| 179 | select CPU_CP15_MMU | 189 | select CPU_CP15_MMU |
| 180 | select CPU_COPY_V4WB if MMU | 190 | select CPU_COPY_V4WB if MMU |
| @@ -193,6 +203,7 @@ config CPU_ARM940T | |||
| 193 | depends on !MMU | 203 | depends on !MMU |
| 194 | select CPU_32v4T | 204 | select CPU_32v4T |
| 195 | select CPU_ABRT_NOMMU | 205 | select CPU_ABRT_NOMMU |
| 206 | select CPU_PABRT_NOIFAR | ||
| 196 | select CPU_CACHE_VIVT | 207 | select CPU_CACHE_VIVT |
| 197 | select CPU_CP15_MPU | 208 | select CPU_CP15_MPU |
| 198 | help | 209 | help |
| @@ -210,6 +221,7 @@ config CPU_ARM946E | |||
| 210 | depends on !MMU | 221 | depends on !MMU |
| 211 | select CPU_32v5 | 222 | select CPU_32v5 |
| 212 | select CPU_ABRT_NOMMU | 223 | select CPU_ABRT_NOMMU |
| 224 | select CPU_PABRT_NOIFAR | ||
| 213 | select CPU_CACHE_VIVT | 225 | select CPU_CACHE_VIVT |
| 214 | select CPU_CP15_MPU | 226 | select CPU_CP15_MPU |
| 215 | help | 227 | help |
| @@ -226,6 +238,7 @@ config CPU_ARM1020 | |||
| 226 | depends on ARCH_INTEGRATOR | 238 | depends on ARCH_INTEGRATOR |
| 227 | select CPU_32v5 | 239 | select CPU_32v5 |
| 228 | select CPU_ABRT_EV4T | 240 | select CPU_ABRT_EV4T |
| 241 | select CPU_PABRT_NOIFAR | ||
| 229 | select CPU_CACHE_V4WT | 242 | select CPU_CACHE_V4WT |
| 230 | select CPU_CACHE_VIVT | 243 | select CPU_CACHE_VIVT |
| 231 | select CPU_CP15_MMU | 244 | select CPU_CP15_MMU |
| @@ -244,6 +257,7 @@ config CPU_ARM1020E | |||
| 244 | depends on ARCH_INTEGRATOR | 257 | depends on ARCH_INTEGRATOR |
| 245 | select CPU_32v5 | 258 | select CPU_32v5 |
| 246 | select CPU_ABRT_EV4T | 259 | select CPU_ABRT_EV4T |
| 260 | select CPU_PABRT_NOIFAR | ||
| 247 | select CPU_CACHE_V4WT | 261 | select CPU_CACHE_V4WT |
| 248 | select CPU_CACHE_VIVT | 262 | select CPU_CACHE_VIVT |
| 249 | select CPU_CP15_MMU | 263 | select CPU_CP15_MMU |
| @@ -257,6 +271,7 @@ config CPU_ARM1022 | |||
| 257 | depends on ARCH_INTEGRATOR | 271 | depends on ARCH_INTEGRATOR |
| 258 | select CPU_32v5 | 272 | select CPU_32v5 |
| 259 | select CPU_ABRT_EV4T | 273 | select CPU_ABRT_EV4T |
| 274 | select CPU_PABRT_NOIFAR | ||
| 260 | select CPU_CACHE_VIVT | 275 | select CPU_CACHE_VIVT |
| 261 | select CPU_CP15_MMU | 276 | select CPU_CP15_MMU |
| 262 | select CPU_COPY_V4WB if MMU # can probably do better | 277 | select CPU_COPY_V4WB if MMU # can probably do better |
| @@ -275,6 +290,7 @@ config CPU_ARM1026 | |||
| 275 | depends on ARCH_INTEGRATOR | 290 | depends on ARCH_INTEGRATOR |
| 276 | select CPU_32v5 | 291 | select CPU_32v5 |
| 277 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 | 292 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 |
| 293 | select CPU_PABRT_NOIFAR | ||
| 278 | select CPU_CACHE_VIVT | 294 | select CPU_CACHE_VIVT |
| 279 | select CPU_CP15_MMU | 295 | select CPU_CP15_MMU |
| 280 | select CPU_COPY_V4WB if MMU # can probably do better | 296 | select CPU_COPY_V4WB if MMU # can probably do better |
| @@ -293,6 +309,7 @@ config CPU_SA110 | |||
| 293 | select CPU_32v3 if ARCH_RPC | 309 | select CPU_32v3 if ARCH_RPC |
| 294 | select CPU_32v4 if !ARCH_RPC | 310 | select CPU_32v4 if !ARCH_RPC |
| 295 | select CPU_ABRT_EV4 | 311 | select CPU_ABRT_EV4 |
| 312 | select CPU_PABRT_NOIFAR | ||
| 296 | select CPU_CACHE_V4WB | 313 | select CPU_CACHE_V4WB |
| 297 | select CPU_CACHE_VIVT | 314 | select CPU_CACHE_VIVT |
| 298 | select CPU_CP15_MMU | 315 | select CPU_CP15_MMU |
| @@ -314,6 +331,7 @@ config CPU_SA1100 | |||
| 314 | default y | 331 | default y |
| 315 | select CPU_32v4 | 332 | select CPU_32v4 |
| 316 | select CPU_ABRT_EV4 | 333 | select CPU_ABRT_EV4 |
| 334 | select CPU_PABRT_NOIFAR | ||
| 317 | select CPU_CACHE_V4WB | 335 | select CPU_CACHE_V4WB |
| 318 | select CPU_CACHE_VIVT | 336 | select CPU_CACHE_VIVT |
| 319 | select CPU_CP15_MMU | 337 | select CPU_CP15_MMU |
| @@ -326,6 +344,7 @@ config CPU_XSCALE | |||
| 326 | default y | 344 | default y |
| 327 | select CPU_32v5 | 345 | select CPU_32v5 |
| 328 | select CPU_ABRT_EV5T | 346 | select CPU_ABRT_EV5T |
| 347 | select CPU_PABRT_NOIFAR | ||
| 329 | select CPU_CACHE_VIVT | 348 | select CPU_CACHE_VIVT |
| 330 | select CPU_CP15_MMU | 349 | select CPU_CP15_MMU |
| 331 | select CPU_TLB_V4WBI if MMU | 350 | select CPU_TLB_V4WBI if MMU |
| @@ -337,6 +356,7 @@ config CPU_XSC3 | |||
| 337 | default y | 356 | default y |
| 338 | select CPU_32v5 | 357 | select CPU_32v5 |
| 339 | select CPU_ABRT_EV5T | 358 | select CPU_ABRT_EV5T |
| 359 | select CPU_PABRT_NOIFAR | ||
| 340 | select CPU_CACHE_VIVT | 360 | select CPU_CACHE_VIVT |
| 341 | select CPU_CP15_MMU | 361 | select CPU_CP15_MMU |
| 342 | select CPU_TLB_V4WBI if MMU | 362 | select CPU_TLB_V4WBI if MMU |
| @@ -345,10 +365,11 @@ config CPU_XSC3 | |||
| 345 | # Feroceon | 365 | # Feroceon |
| 346 | config CPU_FEROCEON | 366 | config CPU_FEROCEON |
| 347 | bool | 367 | bool |
| 348 | depends on ARCH_ORION | 368 | depends on ARCH_ORION5X |
| 349 | default y | 369 | default y |
| 350 | select CPU_32v5 | 370 | select CPU_32v5 |
| 351 | select CPU_ABRT_EV5T | 371 | select CPU_ABRT_EV5T |
| 372 | select CPU_PABRT_NOIFAR | ||
| 352 | select CPU_CACHE_VIVT | 373 | select CPU_CACHE_VIVT |
| 353 | select CPU_CP15_MMU | 374 | select CPU_CP15_MMU |
| 354 | select CPU_COPY_V4WB if MMU | 375 | select CPU_COPY_V4WB if MMU |
| @@ -366,11 +387,12 @@ config CPU_FEROCEON_OLD_ID | |||
| 366 | # ARMv6 | 387 | # ARMv6 |
| 367 | config CPU_V6 | 388 | config CPU_V6 |
| 368 | bool "Support ARM V6 processor" | 389 | bool "Support ARM V6 processor" |
| 369 | depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A | 390 | depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 |
| 370 | default y if ARCH_MX3 | 391 | default y if ARCH_MX3 |
| 371 | default y if ARCH_MSM7X00A | 392 | default y if ARCH_MSM7X00A |
| 372 | select CPU_32v6 | 393 | select CPU_32v6 |
| 373 | select CPU_ABRT_EV6 | 394 | select CPU_ABRT_EV6 |
| 395 | select CPU_PABRT_NOIFAR | ||
| 374 | select CPU_CACHE_V6 | 396 | select CPU_CACHE_V6 |
| 375 | select CPU_CACHE_VIPT | 397 | select CPU_CACHE_VIPT |
| 376 | select CPU_CP15_MMU | 398 | select CPU_CP15_MMU |
| @@ -393,10 +415,11 @@ config CPU_32v6K | |||
| 393 | # ARMv7 | 415 | # ARMv7 |
| 394 | config CPU_V7 | 416 | config CPU_V7 |
| 395 | bool "Support ARM V7 processor" | 417 | bool "Support ARM V7 processor" |
| 396 | depends on ARCH_INTEGRATOR | 418 | depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB |
| 397 | select CPU_32v6K | 419 | select CPU_32v6K |
| 398 | select CPU_32v7 | 420 | select CPU_32v7 |
| 399 | select CPU_ABRT_EV7 | 421 | select CPU_ABRT_EV7 |
| 422 | select CPU_PABRT_IFAR | ||
| 400 | select CPU_CACHE_V7 | 423 | select CPU_CACHE_V7 |
| 401 | select CPU_CACHE_VIPT | 424 | select CPU_CACHE_VIPT |
| 402 | select CPU_CP15_MMU | 425 | select CPU_CP15_MMU |
| @@ -458,6 +481,12 @@ config CPU_ABRT_EV6 | |||
| 458 | config CPU_ABRT_EV7 | 481 | config CPU_ABRT_EV7 |
| 459 | bool | 482 | bool |
| 460 | 483 | ||
| 484 | config CPU_PABRT_IFAR | ||
| 485 | bool | ||
| 486 | |||
| 487 | config CPU_PABRT_NOIFAR | ||
| 488 | bool | ||
| 489 | |||
| 461 | # The cache model | 490 | # The cache model |
| 462 | config CPU_CACHE_V3 | 491 | config CPU_CACHE_V3 |
| 463 | bool | 492 | bool |
| @@ -572,6 +601,13 @@ config ARM_THUMB | |||
| 572 | 601 | ||
| 573 | If you don't know what this all is, saying Y is a safe choice. | 602 | If you don't know what this all is, saying Y is a safe choice. |
| 574 | 603 | ||
| 604 | config ARM_THUMBEE | ||
| 605 | bool "Enable ThumbEE CPU extension" | ||
| 606 | depends on CPU_V7 | ||
| 607 | help | ||
| 608 | Say Y here if you have a CPU with the ThumbEE extension and code to | ||
| 609 | make use of it. Say N for code that can run on CPUs without ThumbEE. | ||
| 610 | |||
| 575 | config CPU_BIG_ENDIAN | 611 | config CPU_BIG_ENDIAN |
| 576 | bool "Build big-endian kernel" | 612 | bool "Build big-endian kernel" |
| 577 | depends on ARCH_SUPPORTS_BIG_ENDIAN | 613 | depends on ARCH_SUPPORTS_BIG_ENDIAN |
| @@ -622,7 +658,7 @@ config CPU_DCACHE_SIZE | |||
| 622 | 658 | ||
| 623 | config CPU_DCACHE_WRITETHROUGH | 659 | config CPU_DCACHE_WRITETHROUGH |
| 624 | bool "Force write through D-cache" | 660 | bool "Force write through D-cache" |
| 625 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FEROCEON) && !CPU_DCACHE_DISABLE | 661 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE |
| 626 | default y if CPU_ARM925T | 662 | default y if CPU_ARM925T |
| 627 | help | 663 | help |
| 628 | Say Y here to use the data cache in writethrough mode. Unless you | 664 | Say Y here to use the data cache in writethrough mode. Unless you |
| @@ -671,5 +707,9 @@ config OUTER_CACHE | |||
| 671 | default n | 707 | default n |
| 672 | 708 | ||
| 673 | config CACHE_L2X0 | 709 | config CACHE_L2X0 |
| 674 | bool | 710 | bool "Enable the L2x0 outer cache controller" |
| 711 | depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 | ||
| 712 | default y | ||
| 675 | select OUTER_CACHE | 713 | select OUTER_CACHE |
| 714 | help | ||
| 715 | This option enables the L2x0 PrimeCell. | ||
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index ec00f26bffa4..b657f1719af0 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c | |||
| @@ -48,8 +48,6 @@ void show_mem(void) | |||
| 48 | 48 | ||
| 49 | printk("Mem-info:\n"); | 49 | printk("Mem-info:\n"); |
| 50 | show_free_areas(); | 50 | show_free_areas(); |
| 51 | printk("Free swap: %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10)); | ||
| 52 | |||
| 53 | for_each_online_node(node) { | 51 | for_each_online_node(node) { |
| 54 | pg_data_t *n = NODE_DATA(node); | 52 | pg_data_t *n = NODE_DATA(node); |
| 55 | struct page *map = n->node_mem_map - n->node_start_pfn; | 53 | struct page *map = n->node_mem_map - n->node_start_pfn; |
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 700c04d6996e..5673f4d6113b 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S | |||
| @@ -471,6 +471,7 @@ arm1020_crval: | |||
| 471 | .type arm1020_processor_functions, #object | 471 | .type arm1020_processor_functions, #object |
| 472 | arm1020_processor_functions: | 472 | arm1020_processor_functions: |
| 473 | .word v4t_early_abort | 473 | .word v4t_early_abort |
| 474 | .word pabort_noifar | ||
| 474 | .word cpu_arm1020_proc_init | 475 | .word cpu_arm1020_proc_init |
| 475 | .word cpu_arm1020_proc_fin | 476 | .word cpu_arm1020_proc_fin |
| 476 | .word cpu_arm1020_reset | 477 | .word cpu_arm1020_reset |
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index 1cc206ab5eae..4343fdb0e9e5 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S | |||
| @@ -452,6 +452,7 @@ arm1020e_crval: | |||
| 452 | .type arm1020e_processor_functions, #object | 452 | .type arm1020e_processor_functions, #object |
| 453 | arm1020e_processor_functions: | 453 | arm1020e_processor_functions: |
| 454 | .word v4t_early_abort | 454 | .word v4t_early_abort |
| 455 | .word pabort_noifar | ||
| 455 | .word cpu_arm1020e_proc_init | 456 | .word cpu_arm1020e_proc_init |
| 456 | .word cpu_arm1020e_proc_fin | 457 | .word cpu_arm1020e_proc_fin |
| 457 | .word cpu_arm1020e_reset | 458 | .word cpu_arm1020e_reset |
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index aff0ea08e2f8..2a4ea1659e96 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S | |||
| @@ -435,6 +435,7 @@ arm1022_crval: | |||
| 435 | .type arm1022_processor_functions, #object | 435 | .type arm1022_processor_functions, #object |
| 436 | arm1022_processor_functions: | 436 | arm1022_processor_functions: |
| 437 | .word v4t_early_abort | 437 | .word v4t_early_abort |
| 438 | .word pabort_noifar | ||
| 438 | .word cpu_arm1022_proc_init | 439 | .word cpu_arm1022_proc_init |
| 439 | .word cpu_arm1022_proc_fin | 440 | .word cpu_arm1022_proc_fin |
| 440 | .word cpu_arm1022_reset | 441 | .word cpu_arm1022_reset |
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 65e43a109085..77a1babd421c 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S | |||
| @@ -430,6 +430,7 @@ arm1026_crval: | |||
| 430 | .type arm1026_processor_functions, #object | 430 | .type arm1026_processor_functions, #object |
| 431 | arm1026_processor_functions: | 431 | arm1026_processor_functions: |
| 432 | .word v5t_early_abort | 432 | .word v5t_early_abort |
| 433 | .word pabort_noifar | ||
| 433 | .word cpu_arm1026_proc_init | 434 | .word cpu_arm1026_proc_init |
| 434 | .word cpu_arm1026_proc_fin | 435 | .word cpu_arm1026_proc_fin |
| 435 | .word cpu_arm1026_reset | 436 | .word cpu_arm1026_reset |
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S index 123a7dc7a433..c371fc87776e 100644 --- a/arch/arm/mm/proc-arm6_7.S +++ b/arch/arm/mm/proc-arm6_7.S | |||
| @@ -293,6 +293,7 @@ __arm7_setup: mov r0, #0 | |||
| 293 | .type arm6_processor_functions, #object | 293 | .type arm6_processor_functions, #object |
| 294 | ENTRY(arm6_processor_functions) | 294 | ENTRY(arm6_processor_functions) |
| 295 | .word cpu_arm6_data_abort | 295 | .word cpu_arm6_data_abort |
| 296 | .word pabort_noifar | ||
| 296 | .word cpu_arm6_proc_init | 297 | .word cpu_arm6_proc_init |
| 297 | .word cpu_arm6_proc_fin | 298 | .word cpu_arm6_proc_fin |
| 298 | .word cpu_arm6_reset | 299 | .word cpu_arm6_reset |
| @@ -309,6 +310,7 @@ ENTRY(arm6_processor_functions) | |||
| 309 | .type arm7_processor_functions, #object | 310 | .type arm7_processor_functions, #object |
| 310 | ENTRY(arm7_processor_functions) | 311 | ENTRY(arm7_processor_functions) |
| 311 | .word cpu_arm7_data_abort | 312 | .word cpu_arm7_data_abort |
| 313 | .word pabort_noifar | ||
| 312 | .word cpu_arm7_proc_init | 314 | .word cpu_arm7_proc_init |
| 313 | .word cpu_arm7_proc_fin | 315 | .word cpu_arm7_proc_fin |
| 314 | .word cpu_arm7_reset | 316 | .word cpu_arm7_reset |
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index dc763be43362..d64f8e6f75ab 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S | |||
| @@ -198,6 +198,7 @@ arm720_crval: | |||
| 198 | .type arm720_processor_functions, #object | 198 | .type arm720_processor_functions, #object |
| 199 | ENTRY(arm720_processor_functions) | 199 | ENTRY(arm720_processor_functions) |
| 200 | .word v4t_late_abort | 200 | .word v4t_late_abort |
| 201 | .word pabort_noifar | ||
| 201 | .word cpu_arm720_proc_init | 202 | .word cpu_arm720_proc_init |
| 202 | .word cpu_arm720_proc_fin | 203 | .word cpu_arm720_proc_fin |
| 203 | .word cpu_arm720_reset | 204 | .word cpu_arm720_reset |
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S index 7069f495cf9b..3a57376c8bc9 100644 --- a/arch/arm/mm/proc-arm740.S +++ b/arch/arm/mm/proc-arm740.S | |||
| @@ -126,6 +126,7 @@ __arm740_setup: | |||
| 126 | .type arm740_processor_functions, #object | 126 | .type arm740_processor_functions, #object |
| 127 | ENTRY(arm740_processor_functions) | 127 | ENTRY(arm740_processor_functions) |
| 128 | .word v4t_late_abort | 128 | .word v4t_late_abort |
| 129 | .word pabort_noifar | ||
| 129 | .word cpu_arm740_proc_init | 130 | .word cpu_arm740_proc_init |
| 130 | .word cpu_arm740_proc_fin | 131 | .word cpu_arm740_proc_fin |
| 131 | .word cpu_arm740_reset | 132 | .word cpu_arm740_reset |
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S index d091c2571823..7b3ecdeb5370 100644 --- a/arch/arm/mm/proc-arm7tdmi.S +++ b/arch/arm/mm/proc-arm7tdmi.S | |||
| @@ -64,6 +64,7 @@ __arm7tdmi_setup: | |||
| 64 | .type arm7tdmi_processor_functions, #object | 64 | .type arm7tdmi_processor_functions, #object |
| 65 | ENTRY(arm7tdmi_processor_functions) | 65 | ENTRY(arm7tdmi_processor_functions) |
| 66 | .word v4t_late_abort | 66 | .word v4t_late_abort |
| 67 | .word pabort_noifar | ||
| 67 | .word cpu_arm7tdmi_proc_init | 68 | .word cpu_arm7tdmi_proc_init |
| 68 | .word cpu_arm7tdmi_proc_fin | 69 | .word cpu_arm7tdmi_proc_fin |
| 69 | .word cpu_arm7tdmi_reset | 70 | .word cpu_arm7tdmi_reset |
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 75c945ed6c4d..28cdb060df45 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S | |||
| @@ -417,6 +417,7 @@ arm920_crval: | |||
| 417 | .type arm920_processor_functions, #object | 417 | .type arm920_processor_functions, #object |
| 418 | arm920_processor_functions: | 418 | arm920_processor_functions: |
| 419 | .word v4t_early_abort | 419 | .word v4t_early_abort |
| 420 | .word pabort_noifar | ||
| 420 | .word cpu_arm920_proc_init | 421 | .word cpu_arm920_proc_init |
| 421 | .word cpu_arm920_proc_fin | 422 | .word cpu_arm920_proc_fin |
| 422 | .word cpu_arm920_reset | 423 | .word cpu_arm920_reset |
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index ffb751b877ff..94ddcb4a4b76 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S | |||
| @@ -421,6 +421,7 @@ arm922_crval: | |||
| 421 | .type arm922_processor_functions, #object | 421 | .type arm922_processor_functions, #object |
| 422 | arm922_processor_functions: | 422 | arm922_processor_functions: |
| 423 | .word v4t_early_abort | 423 | .word v4t_early_abort |
| 424 | .word pabort_noifar | ||
| 424 | .word cpu_arm922_proc_init | 425 | .word cpu_arm922_proc_init |
| 425 | .word cpu_arm922_proc_fin | 426 | .word cpu_arm922_proc_fin |
| 426 | .word cpu_arm922_reset | 427 | .word cpu_arm922_reset |
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 44c2c997819f..065087afb772 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S | |||
| @@ -484,6 +484,7 @@ arm925_crval: | |||
| 484 | .type arm925_processor_functions, #object | 484 | .type arm925_processor_functions, #object |
| 485 | arm925_processor_functions: | 485 | arm925_processor_functions: |
| 486 | .word v4t_early_abort | 486 | .word v4t_early_abort |
| 487 | .word pabort_noifar | ||
| 487 | .word cpu_arm925_proc_init | 488 | .word cpu_arm925_proc_init |
| 488 | .word cpu_arm925_proc_fin | 489 | .word cpu_arm925_proc_fin |
| 489 | .word cpu_arm925_reset | 490 | .word cpu_arm925_reset |
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 194ef48968e6..997db8472b5c 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S | |||
| @@ -437,6 +437,7 @@ arm926_crval: | |||
| 437 | .type arm926_processor_functions, #object | 437 | .type arm926_processor_functions, #object |
| 438 | arm926_processor_functions: | 438 | arm926_processor_functions: |
| 439 | .word v5tj_early_abort | 439 | .word v5tj_early_abort |
| 440 | .word pabort_noifar | ||
| 440 | .word cpu_arm926_proc_init | 441 | .word cpu_arm926_proc_init |
| 441 | .word cpu_arm926_proc_fin | 442 | .word cpu_arm926_proc_fin |
| 442 | .word cpu_arm926_reset | 443 | .word cpu_arm926_reset |
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S index 786c593778f0..44ead902bd54 100644 --- a/arch/arm/mm/proc-arm940.S +++ b/arch/arm/mm/proc-arm940.S | |||
| @@ -321,6 +321,7 @@ __arm940_setup: | |||
| 321 | .type arm940_processor_functions, #object | 321 | .type arm940_processor_functions, #object |
| 322 | ENTRY(arm940_processor_functions) | 322 | ENTRY(arm940_processor_functions) |
| 323 | .word nommu_early_abort | 323 | .word nommu_early_abort |
| 324 | .word pabort_noifar | ||
| 324 | .word cpu_arm940_proc_init | 325 | .word cpu_arm940_proc_init |
| 325 | .word cpu_arm940_proc_fin | 326 | .word cpu_arm940_proc_fin |
| 326 | .word cpu_arm940_reset | 327 | .word cpu_arm940_reset |
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S index a60c1421d450..2218b0c01330 100644 --- a/arch/arm/mm/proc-arm946.S +++ b/arch/arm/mm/proc-arm946.S | |||
| @@ -376,6 +376,7 @@ __arm946_setup: | |||
| 376 | .type arm946_processor_functions, #object | 376 | .type arm946_processor_functions, #object |
| 377 | ENTRY(arm946_processor_functions) | 377 | ENTRY(arm946_processor_functions) |
| 378 | .word nommu_early_abort | 378 | .word nommu_early_abort |
| 379 | .word pabort_noifar | ||
| 379 | .word cpu_arm946_proc_init | 380 | .word cpu_arm946_proc_init |
| 380 | .word cpu_arm946_proc_fin | 381 | .word cpu_arm946_proc_fin |
| 381 | .word cpu_arm946_reset | 382 | .word cpu_arm946_reset |
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S index 4848eeac86b6..c85c1f50e396 100644 --- a/arch/arm/mm/proc-arm9tdmi.S +++ b/arch/arm/mm/proc-arm9tdmi.S | |||
| @@ -64,6 +64,7 @@ __arm9tdmi_setup: | |||
| 64 | .type arm9tdmi_processor_functions, #object | 64 | .type arm9tdmi_processor_functions, #object |
| 65 | ENTRY(arm9tdmi_processor_functions) | 65 | ENTRY(arm9tdmi_processor_functions) |
| 66 | .word nommu_early_abort | 66 | .word nommu_early_abort |
| 67 | .word pabort_noifar | ||
| 67 | .word cpu_arm9tdmi_proc_init | 68 | .word cpu_arm9tdmi_proc_init |
| 68 | .word cpu_arm9tdmi_proc_fin | 69 | .word cpu_arm9tdmi_proc_fin |
| 69 | .word cpu_arm9tdmi_reset | 70 | .word cpu_arm9tdmi_reset |
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index fa0dc7e6f0ea..3ceb6785a345 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S | |||
| @@ -118,12 +118,8 @@ ENTRY(feroceon_flush_kern_cache_all) | |||
| 118 | mov r2, #VM_EXEC | 118 | mov r2, #VM_EXEC |
| 119 | mov ip, #0 | 119 | mov ip, #0 |
| 120 | __flush_whole_cache: | 120 | __flush_whole_cache: |
| 121 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
| 122 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | ||
| 123 | #else | ||
| 124 | 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate | 121 | 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate |
| 125 | bne 1b | 122 | bne 1b |
| 126 | #endif | ||
| 127 | tst r2, #VM_EXEC | 123 | tst r2, #VM_EXEC |
| 128 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | 124 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache |
| 129 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | 125 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB |
| @@ -145,21 +141,12 @@ ENTRY(feroceon_flush_user_cache_range) | |||
| 145 | cmp r3, #CACHE_DLIMIT | 141 | cmp r3, #CACHE_DLIMIT |
| 146 | bgt __flush_whole_cache | 142 | bgt __flush_whole_cache |
| 147 | 1: tst r2, #VM_EXEC | 143 | 1: tst r2, #VM_EXEC |
| 148 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
| 149 | mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | ||
| 150 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | ||
| 151 | add r0, r0, #CACHE_DLINESIZE | ||
| 152 | mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | ||
| 153 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | ||
| 154 | add r0, r0, #CACHE_DLINESIZE | ||
| 155 | #else | ||
| 156 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry | 144 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry |
| 157 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | 145 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry |
| 158 | add r0, r0, #CACHE_DLINESIZE | 146 | add r0, r0, #CACHE_DLINESIZE |
| 159 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry | 147 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry |
| 160 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | 148 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry |
| 161 | add r0, r0, #CACHE_DLINESIZE | 149 | add r0, r0, #CACHE_DLINESIZE |
| 162 | #endif | ||
| 163 | cmp r0, r1 | 150 | cmp r0, r1 |
| 164 | blo 1b | 151 | blo 1b |
| 165 | tst r2, #VM_EXEC | 152 | tst r2, #VM_EXEC |
| @@ -232,12 +219,10 @@ ENTRY(feroceon_flush_kern_dcache_page) | |||
| 232 | * (same as v4wb) | 219 | * (same as v4wb) |
| 233 | */ | 220 | */ |
| 234 | ENTRY(feroceon_dma_inv_range) | 221 | ENTRY(feroceon_dma_inv_range) |
| 235 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
| 236 | tst r0, #CACHE_DLINESIZE - 1 | 222 | tst r0, #CACHE_DLINESIZE - 1 |
| 237 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | 223 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
| 238 | tst r1, #CACHE_DLINESIZE - 1 | 224 | tst r1, #CACHE_DLINESIZE - 1 |
| 239 | mcrne p15, 0, r1, c7, c10, 1 @ clean D entry | 225 | mcrne p15, 0, r1, c7, c10, 1 @ clean D entry |
| 240 | #endif | ||
| 241 | bic r0, r0, #CACHE_DLINESIZE - 1 | 226 | bic r0, r0, #CACHE_DLINESIZE - 1 |
| 242 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | 227 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry |
| 243 | add r0, r0, #CACHE_DLINESIZE | 228 | add r0, r0, #CACHE_DLINESIZE |
| @@ -257,13 +242,11 @@ ENTRY(feroceon_dma_inv_range) | |||
| 257 | * (same as v4wb) | 242 | * (same as v4wb) |
| 258 | */ | 243 | */ |
| 259 | ENTRY(feroceon_dma_clean_range) | 244 | ENTRY(feroceon_dma_clean_range) |
| 260 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
| 261 | bic r0, r0, #CACHE_DLINESIZE - 1 | 245 | bic r0, r0, #CACHE_DLINESIZE - 1 |
| 262 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 246 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
| 263 | add r0, r0, #CACHE_DLINESIZE | 247 | add r0, r0, #CACHE_DLINESIZE |
| 264 | cmp r0, r1 | 248 | cmp r0, r1 |
| 265 | blo 1b | 249 | blo 1b |
| 266 | #endif | ||
| 267 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | 250 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
| 268 | mov pc, lr | 251 | mov pc, lr |
| 269 | 252 | ||
| @@ -278,11 +261,7 @@ ENTRY(feroceon_dma_clean_range) | |||
| 278 | ENTRY(feroceon_dma_flush_range) | 261 | ENTRY(feroceon_dma_flush_range) |
| 279 | bic r0, r0, #CACHE_DLINESIZE - 1 | 262 | bic r0, r0, #CACHE_DLINESIZE - 1 |
| 280 | 1: | 263 | 1: |
| 281 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
| 282 | mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | 264 | mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |
| 283 | #else | ||
| 284 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | ||
| 285 | #endif | ||
| 286 | add r0, r0, #CACHE_DLINESIZE | 265 | add r0, r0, #CACHE_DLINESIZE |
| 287 | cmp r0, r1 | 266 | cmp r0, r1 |
| 288 | blo 1b | 267 | blo 1b |
| @@ -301,12 +280,10 @@ ENTRY(feroceon_cache_fns) | |||
| 301 | .long feroceon_dma_flush_range | 280 | .long feroceon_dma_flush_range |
| 302 | 281 | ||
| 303 | ENTRY(cpu_feroceon_dcache_clean_area) | 282 | ENTRY(cpu_feroceon_dcache_clean_area) |
| 304 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
| 305 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 283 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
| 306 | add r0, r0, #CACHE_DLINESIZE | 284 | add r0, r0, #CACHE_DLINESIZE |
| 307 | subs r1, r1, #CACHE_DLINESIZE | 285 | subs r1, r1, #CACHE_DLINESIZE |
| 308 | bhi 1b | 286 | bhi 1b |
| 309 | #endif | ||
| 310 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | 287 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
| 311 | mov pc, lr | 288 | mov pc, lr |
| 312 | 289 | ||
| @@ -323,13 +300,9 @@ ENTRY(cpu_feroceon_dcache_clean_area) | |||
| 323 | ENTRY(cpu_feroceon_switch_mm) | 300 | ENTRY(cpu_feroceon_switch_mm) |
| 324 | #ifdef CONFIG_MMU | 301 | #ifdef CONFIG_MMU |
| 325 | mov ip, #0 | 302 | mov ip, #0 |
| 326 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
| 327 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | ||
| 328 | #else | ||
| 329 | @ && 'Clean & Invalidate whole DCache' | 303 | @ && 'Clean & Invalidate whole DCache' |
| 330 | 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate | 304 | 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate |
| 331 | bne 1b | 305 | bne 1b |
| 332 | #endif | ||
| 333 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache | 306 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache |
| 334 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | 307 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
| 335 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer | 308 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer |
| @@ -362,16 +335,9 @@ ENTRY(cpu_feroceon_set_pte_ext) | |||
| 362 | tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? | 335 | tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? |
| 363 | movne r2, #0 | 336 | movne r2, #0 |
| 364 | 337 | ||
| 365 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
| 366 | eor r3, r2, #0x0a @ C & small page? | ||
| 367 | tst r3, #0x0b | ||
| 368 | biceq r2, r2, #4 | ||
| 369 | #endif | ||
| 370 | str r2, [r0] @ hardware version | 338 | str r2, [r0] @ hardware version |
| 371 | mov r0, r0 | 339 | mov r0, r0 |
| 372 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
| 373 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 340 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
| 374 | #endif | ||
| 375 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | 341 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
| 376 | #endif | 342 | #endif |
| 377 | mov pc, lr | 343 | mov pc, lr |
| @@ -387,20 +353,11 @@ __feroceon_setup: | |||
| 387 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 | 353 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 |
| 388 | #endif | 354 | #endif |
| 389 | 355 | ||
| 390 | |||
| 391 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
| 392 | mov r0, #4 @ disable write-back on caches explicitly | ||
| 393 | mcr p15, 7, r0, c15, c0, 0 | ||
| 394 | #endif | ||
| 395 | |||
| 396 | adr r5, feroceon_crval | 356 | adr r5, feroceon_crval |
| 397 | ldmia r5, {r5, r6} | 357 | ldmia r5, {r5, r6} |
| 398 | mrc p15, 0, r0, c1, c0 @ get control register v4 | 358 | mrc p15, 0, r0, c1, c0 @ get control register v4 |
| 399 | bic r0, r0, r5 | 359 | bic r0, r0, r5 |
| 400 | orr r0, r0, r6 | 360 | orr r0, r0, r6 |
| 401 | #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN | ||
| 402 | orr r0, r0, #0x4000 @ .1.. .... .... .... | ||
| 403 | #endif | ||
| 404 | mov pc, lr | 361 | mov pc, lr |
| 405 | .size __feroceon_setup, . - __feroceon_setup | 362 | .size __feroceon_setup, . - __feroceon_setup |
| 406 | 363 | ||
| @@ -423,6 +380,7 @@ feroceon_crval: | |||
| 423 | .type feroceon_processor_functions, #object | 380 | .type feroceon_processor_functions, #object |
| 424 | feroceon_processor_functions: | 381 | feroceon_processor_functions: |
| 425 | .word v5t_early_abort | 382 | .word v5t_early_abort |
| 383 | .word pabort_noifar | ||
| 426 | .word cpu_feroceon_proc_init | 384 | .word cpu_feroceon_proc_init |
| 427 | .word cpu_feroceon_proc_fin | 385 | .word cpu_feroceon_proc_fin |
| 428 | .word cpu_feroceon_reset | 386 | .word cpu_feroceon_reset |
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S index 6e226e12989f..9818195dbf11 100644 --- a/arch/arm/mm/proc-sa110.S +++ b/arch/arm/mm/proc-sa110.S | |||
| @@ -216,6 +216,7 @@ sa110_crval: | |||
| 216 | .type sa110_processor_functions, #object | 216 | .type sa110_processor_functions, #object |
| 217 | ENTRY(sa110_processor_functions) | 217 | ENTRY(sa110_processor_functions) |
| 218 | .word v4_early_abort | 218 | .word v4_early_abort |
| 219 | .word pabort_noifar | ||
| 219 | .word cpu_sa110_proc_init | 220 | .word cpu_sa110_proc_init |
| 220 | .word cpu_sa110_proc_fin | 221 | .word cpu_sa110_proc_fin |
| 221 | .word cpu_sa110_reset | 222 | .word cpu_sa110_reset |
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 9afb11d089fe..c5fe27ad2892 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S | |||
| @@ -231,6 +231,7 @@ sa1100_crval: | |||
| 231 | .type sa1100_processor_functions, #object | 231 | .type sa1100_processor_functions, #object |
| 232 | ENTRY(sa1100_processor_functions) | 232 | ENTRY(sa1100_processor_functions) |
| 233 | .word v4_early_abort | 233 | .word v4_early_abort |
| 234 | .word pabort_noifar | ||
| 234 | .word cpu_sa1100_proc_init | 235 | .word cpu_sa1100_proc_init |
| 235 | .word cpu_sa1100_proc_fin | 236 | .word cpu_sa1100_proc_fin |
| 236 | .word cpu_sa1100_reset | 237 | .word cpu_sa1100_reset |
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index eb42e5b94863..5702ec58b2a2 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S | |||
| @@ -17,10 +17,6 @@ | |||
| 17 | #include <asm/pgtable-hwdef.h> | 17 | #include <asm/pgtable-hwdef.h> |
| 18 | #include <asm/pgtable.h> | 18 | #include <asm/pgtable.h> |
| 19 | 19 | ||
| 20 | #ifdef CONFIG_SMP | ||
| 21 | #include <asm/hardware/arm_scu.h> | ||
| 22 | #endif | ||
| 23 | |||
| 24 | #include "proc-macros.S" | 20 | #include "proc-macros.S" |
| 25 | 21 | ||
| 26 | #define D_CACHE_LINE_SIZE 32 | 22 | #define D_CACHE_LINE_SIZE 32 |
| @@ -187,20 +183,10 @@ cpu_v6_name: | |||
| 187 | */ | 183 | */ |
| 188 | __v6_setup: | 184 | __v6_setup: |
| 189 | #ifdef CONFIG_SMP | 185 | #ifdef CONFIG_SMP |
| 190 | /* Set up the SCU on core 0 only */ | ||
| 191 | mrc p15, 0, r0, c0, c0, 5 @ CPU core number | ||
| 192 | ands r0, r0, #15 | ||
| 193 | ldreq r0, =SCU_BASE | ||
| 194 | ldreq r5, [r0, #SCU_CTRL] | ||
| 195 | orreq r5, r5, #1 | ||
| 196 | streq r5, [r0, #SCU_CTRL] | ||
| 197 | |||
| 198 | #ifndef CONFIG_CPU_DCACHE_DISABLE | ||
| 199 | mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode | 186 | mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode |
| 200 | orr r0, r0, #0x20 | 187 | orr r0, r0, #0x20 |
| 201 | mcr p15, 0, r0, c1, c0, 1 | 188 | mcr p15, 0, r0, c1, c0, 1 |
| 202 | #endif | 189 | #endif |
| 203 | #endif | ||
| 204 | 190 | ||
| 205 | mov r0, #0 | 191 | mov r0, #0 |
| 206 | mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache | 192 | mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache |
| @@ -233,6 +219,7 @@ v6_crval: | |||
| 233 | .type v6_processor_functions, #object | 219 | .type v6_processor_functions, #object |
| 234 | ENTRY(v6_processor_functions) | 220 | ENTRY(v6_processor_functions) |
| 235 | .word v6_early_abort | 221 | .word v6_early_abort |
| 222 | .word pabort_noifar | ||
| 236 | .word cpu_v6_proc_init | 223 | .word cpu_v6_proc_init |
| 237 | .word cpu_v6_proc_fin | 224 | .word cpu_v6_proc_fin |
| 238 | .word cpu_v6_reset | 225 | .word cpu_v6_reset |
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index e0acc5ae6f6f..b49f9a4c82c8 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
| @@ -205,6 +205,7 @@ __v7_setup_stack: | |||
| 205 | .type v7_processor_functions, #object | 205 | .type v7_processor_functions, #object |
| 206 | ENTRY(v7_processor_functions) | 206 | ENTRY(v7_processor_functions) |
| 207 | .word v7_early_abort | 207 | .word v7_early_abort |
| 208 | .word pabort_ifar | ||
| 208 | .word cpu_v7_proc_init | 209 | .word cpu_v7_proc_init |
| 209 | .word cpu_v7_proc_fin | 210 | .word cpu_v7_proc_fin |
| 210 | .word cpu_v7_reset | 211 | .word cpu_v7_reset |
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index d95921a2ab99..3533741a76f6 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S | |||
| @@ -450,6 +450,7 @@ xsc3_crval: | |||
| 450 | .type xsc3_processor_functions, #object | 450 | .type xsc3_processor_functions, #object |
| 451 | ENTRY(xsc3_processor_functions) | 451 | ENTRY(xsc3_processor_functions) |
| 452 | .word v5t_early_abort | 452 | .word v5t_early_abort |
| 453 | .word pabort_noifar | ||
| 453 | .word cpu_xsc3_proc_init | 454 | .word cpu_xsc3_proc_init |
| 454 | .word cpu_xsc3_proc_fin | 455 | .word cpu_xsc3_proc_fin |
| 455 | .word cpu_xsc3_reset | 456 | .word cpu_xsc3_reset |
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 016690b9d564..2dd85273976f 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S | |||
| @@ -527,6 +527,7 @@ xscale_crval: | |||
| 527 | .type xscale_processor_functions, #object | 527 | .type xscale_processor_functions, #object |
| 528 | ENTRY(xscale_processor_functions) | 528 | ENTRY(xscale_processor_functions) |
| 529 | .word v5t_early_abort | 529 | .word v5t_early_abort |
| 530 | .word pabort_noifar | ||
| 530 | .word cpu_xscale_proc_init | 531 | .word cpu_xscale_proc_init |
| 531 | .word cpu_xscale_proc_fin | 532 | .word cpu_xscale_proc_fin |
| 532 | .word cpu_xscale_reset | 533 | .word cpu_xscale_reset |
diff --git a/arch/arm/oprofile/op_model_mpcore.c b/arch/arm/oprofile/op_model_mpcore.c index 75bae067922d..74fae6045650 100644 --- a/arch/arm/oprofile/op_model_mpcore.c +++ b/arch/arm/oprofile/op_model_mpcore.c | |||
| @@ -51,7 +51,7 @@ | |||
| 51 | /* | 51 | /* |
| 52 | * MPCore SCU event monitor support | 52 | * MPCore SCU event monitor support |
| 53 | */ | 53 | */ |
| 54 | #define SCU_EVENTMONITORS_VA_BASE __io_address(REALVIEW_MPCORE_SCU_BASE + 0x10) | 54 | #define SCU_EVENTMONITORS_VA_BASE __io_address(REALVIEW_EB11MP_SCU_BASE + 0x10) |
| 55 | 55 | ||
| 56 | /* | 56 | /* |
| 57 | * Bitmask of used SCU counters | 57 | * Bitmask of used SCU counters |
| @@ -80,7 +80,7 @@ static irqreturn_t scu_em_interrupt(int irq, void *arg) | |||
| 80 | struct eventmonitor __iomem *emc = SCU_EVENTMONITORS_VA_BASE; | 80 | struct eventmonitor __iomem *emc = SCU_EVENTMONITORS_VA_BASE; |
| 81 | unsigned int cnt; | 81 | unsigned int cnt; |
| 82 | 82 | ||
| 83 | cnt = irq - IRQ_PMU_SCU0; | 83 | cnt = irq - IRQ_EB11MP_PMU_SCU0; |
| 84 | oprofile_add_sample(get_irq_regs(), SCU_COUNTER(cnt)); | 84 | oprofile_add_sample(get_irq_regs(), SCU_COUNTER(cnt)); |
| 85 | scu_reset_counter(emc, cnt); | 85 | scu_reset_counter(emc, cnt); |
| 86 | 86 | ||
| @@ -119,10 +119,10 @@ static int scu_start(void) | |||
| 119 | */ | 119 | */ |
| 120 | for (i = 0; i < NUM_SCU_COUNTERS; i++) { | 120 | for (i = 0; i < NUM_SCU_COUNTERS; i++) { |
| 121 | if (scu_em_used & (1 << i)) { | 121 | if (scu_em_used & (1 << i)) { |
| 122 | ret = request_irq(IRQ_PMU_SCU0 + i, scu_em_interrupt, IRQF_DISABLED, "SCU PMU", NULL); | 122 | ret = request_irq(IRQ_EB11MP_PMU_SCU0 + i, scu_em_interrupt, IRQF_DISABLED, "SCU PMU", NULL); |
| 123 | if (ret) { | 123 | if (ret) { |
| 124 | printk(KERN_ERR "oprofile: unable to request IRQ%u for SCU Event Monitor\n", | 124 | printk(KERN_ERR "oprofile: unable to request IRQ%u for SCU Event Monitor\n", |
| 125 | IRQ_PMU_SCU0 + i); | 125 | IRQ_EB11MP_PMU_SCU0 + i); |
| 126 | goto err_free_scu; | 126 | goto err_free_scu; |
| 127 | } | 127 | } |
| 128 | } | 128 | } |
| @@ -153,7 +153,7 @@ static int scu_start(void) | |||
| 153 | 153 | ||
| 154 | err_free_scu: | 154 | err_free_scu: |
| 155 | while (i--) | 155 | while (i--) |
| 156 | free_irq(IRQ_PMU_SCU0 + i, NULL); | 156 | free_irq(IRQ_EB11MP_PMU_SCU0 + i, NULL); |
| 157 | return ret; | 157 | return ret; |
| 158 | } | 158 | } |
| 159 | 159 | ||
| @@ -175,7 +175,7 @@ static void scu_stop(void) | |||
| 175 | for (i = 0; i < NUM_SCU_COUNTERS; i++) { | 175 | for (i = 0; i < NUM_SCU_COUNTERS; i++) { |
| 176 | if (scu_em_used & (1 << i)) { | 176 | if (scu_em_used & (1 << i)) { |
| 177 | scu_reset_counter(emc, i); | 177 | scu_reset_counter(emc, i); |
| 178 | free_irq(IRQ_PMU_SCU0 + i, NULL); | 178 | free_irq(IRQ_EB11MP_PMU_SCU0 + i, NULL); |
| 179 | } | 179 | } |
| 180 | } | 180 | } |
| 181 | } | 181 | } |
| @@ -225,10 +225,10 @@ static int em_setup_ctrs(void) | |||
| 225 | } | 225 | } |
| 226 | 226 | ||
| 227 | static int arm11_irqs[] = { | 227 | static int arm11_irqs[] = { |
| 228 | [0] = IRQ_PMU_CPU0, | 228 | [0] = IRQ_EB11MP_PMU_CPU0, |
| 229 | [1] = IRQ_PMU_CPU1, | 229 | [1] = IRQ_EB11MP_PMU_CPU1, |
| 230 | [2] = IRQ_PMU_CPU2, | 230 | [2] = IRQ_EB11MP_PMU_CPU2, |
| 231 | [3] = IRQ_PMU_CPU3 | 231 | [3] = IRQ_EB11MP_PMU_CPU3 |
| 232 | }; | 232 | }; |
| 233 | 233 | ||
| 234 | static int em_start(void) | 234 | static int em_start(void) |
| @@ -273,22 +273,22 @@ static int em_setup(void) | |||
| 273 | /* | 273 | /* |
| 274 | * Send SCU PMU interrupts to the "owner" CPU. | 274 | * Send SCU PMU interrupts to the "owner" CPU. |
| 275 | */ | 275 | */ |
| 276 | em_route_irq(IRQ_PMU_SCU0, 0); | 276 | em_route_irq(IRQ_EB11MP_PMU_SCU0, 0); |
| 277 | em_route_irq(IRQ_PMU_SCU1, 0); | 277 | em_route_irq(IRQ_EB11MP_PMU_SCU1, 0); |
| 278 | em_route_irq(IRQ_PMU_SCU2, 1); | 278 | em_route_irq(IRQ_EB11MP_PMU_SCU2, 1); |
| 279 | em_route_irq(IRQ_PMU_SCU3, 1); | 279 | em_route_irq(IRQ_EB11MP_PMU_SCU3, 1); |
| 280 | em_route_irq(IRQ_PMU_SCU4, 2); | 280 | em_route_irq(IRQ_EB11MP_PMU_SCU4, 2); |
| 281 | em_route_irq(IRQ_PMU_SCU5, 2); | 281 | em_route_irq(IRQ_EB11MP_PMU_SCU5, 2); |
| 282 | em_route_irq(IRQ_PMU_SCU6, 3); | 282 | em_route_irq(IRQ_EB11MP_PMU_SCU6, 3); |
| 283 | em_route_irq(IRQ_PMU_SCU7, 3); | 283 | em_route_irq(IRQ_EB11MP_PMU_SCU7, 3); |
| 284 | 284 | ||
| 285 | /* | 285 | /* |
| 286 | * Send CP15 PMU interrupts to the owner CPU. | 286 | * Send CP15 PMU interrupts to the owner CPU. |
| 287 | */ | 287 | */ |
| 288 | em_route_irq(IRQ_PMU_CPU0, 0); | 288 | em_route_irq(IRQ_EB11MP_PMU_CPU0, 0); |
| 289 | em_route_irq(IRQ_PMU_CPU1, 1); | 289 | em_route_irq(IRQ_EB11MP_PMU_CPU1, 1); |
| 290 | em_route_irq(IRQ_PMU_CPU2, 2); | 290 | em_route_irq(IRQ_EB11MP_PMU_CPU2, 2); |
| 291 | em_route_irq(IRQ_PMU_CPU3, 3); | 291 | em_route_irq(IRQ_EB11MP_PMU_CPU3, 3); |
| 292 | 292 | ||
| 293 | return 0; | 293 | return 0; |
| 294 | } | 294 | } |
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index 98d01517b563..d9bc15a69e5d 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | #include <asm/hardware.h> | 24 | #include <asm/hardware.h> |
| 25 | #include <asm/mach/pci.h> | 25 | #include <asm/mach/pci.h> |
| 26 | #include <asm/hardware/iop3xx.h> | 26 | #include <asm/hardware/iop3xx.h> |
| 27 | #include <asm/mach-types.h> | ||
| 27 | 28 | ||
| 28 | // #define DEBUG | 29 | // #define DEBUG |
| 29 | 30 | ||
| @@ -209,8 +210,11 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) | |||
| 209 | res[1].flags = IORESOURCE_MEM; | 210 | res[1].flags = IORESOURCE_MEM; |
| 210 | request_resource(&iomem_resource, &res[1]); | 211 | request_resource(&iomem_resource, &res[1]); |
| 211 | 212 | ||
| 212 | sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA; | 213 | /* |
| 213 | sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - IOP3XX_PCI_LOWER_IO_BA; | 214 | * Use whatever translation is already setup. |
| 215 | */ | ||
| 216 | sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0; | ||
| 217 | sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR; | ||
| 214 | 218 | ||
| 215 | sys->resource[0] = &res[0]; | 219 | sys->resource[0] = &res[0]; |
| 216 | sys->resource[1] = &res[1]; | 220 | sys->resource[1] = &res[1]; |
| @@ -250,11 +254,11 @@ void __init iop3xx_atu_setup(void) | |||
| 250 | *IOP3XX_IATVR2 = PHYS_OFFSET; | 254 | *IOP3XX_IATVR2 = PHYS_OFFSET; |
| 251 | 255 | ||
| 252 | /* Outbound window 0 */ | 256 | /* Outbound window 0 */ |
| 253 | *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_PA; | 257 | *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA; |
| 254 | *IOP3XX_OUMWTVR0 = 0; | 258 | *IOP3XX_OUMWTVR0 = 0; |
| 255 | 259 | ||
| 256 | /* Outbound window 1 */ | 260 | /* Outbound window 1 */ |
| 257 | *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE; | 261 | *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA + IOP3XX_PCI_MEM_WINDOW_SIZE; |
| 258 | *IOP3XX_OUMWTVR1 = 0; | 262 | *IOP3XX_OUMWTVR1 = 0; |
| 259 | 263 | ||
| 260 | /* BAR 3 ( Disabled ) */ | 264 | /* BAR 3 ( Disabled ) */ |
| @@ -265,7 +269,7 @@ void __init iop3xx_atu_setup(void) | |||
| 265 | 269 | ||
| 266 | /* Setup the I/O Bar | 270 | /* Setup the I/O Bar |
| 267 | */ | 271 | */ |
| 268 | *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_PA;; | 272 | *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA; |
| 269 | 273 | ||
| 270 | /* Enable inbound and outbound cycles | 274 | /* Enable inbound and outbound cycles |
| 271 | */ | 275 | */ |
| @@ -322,34 +326,59 @@ void __init iop3xx_atu_disable(void) | |||
| 322 | /* Flag to determine whether the ATU is initialized and the PCI bus scanned */ | 326 | /* Flag to determine whether the ATU is initialized and the PCI bus scanned */ |
| 323 | int init_atu; | 327 | int init_atu; |
| 324 | 328 | ||
| 325 | void __init iop3xx_pci_preinit(void) | 329 | int iop3xx_get_init_atu(void) { |
| 330 | /* check if default has been overridden */ | ||
| 331 | if (init_atu != IOP3XX_INIT_ATU_DEFAULT) | ||
| 332 | return init_atu; | ||
| 333 | else | ||
| 334 | return IOP3XX_INIT_ATU_DISABLE; | ||
| 335 | } | ||
| 336 | |||
| 337 | static void __init iop3xx_atu_debug(void) | ||
| 326 | { | 338 | { |
| 327 | if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { | 339 | DBG("PCI: Intel IOP3xx PCI init.\n"); |
| 328 | iop3xx_atu_disable(); | 340 | DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n", |
| 329 | iop3xx_atu_setup(); | 341 | *IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0); |
| 330 | } | 342 | DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n", |
| 343 | *IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1); | ||
| 344 | DBG("PCI: Outbound IO window: PCI 0x%08x\n", | ||
| 345 | *IOP3XX_OIOWTVR); | ||
| 346 | |||
| 347 | DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", | ||
| 348 | *IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0); | ||
| 349 | DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n", | ||
| 350 | *IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1); | ||
| 351 | DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", | ||
| 352 | *IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2); | ||
| 353 | DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", | ||
| 354 | *IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3); | ||
| 355 | |||
| 356 | DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", | ||
| 357 | 0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR); | ||
| 331 | 358 | ||
| 332 | DBG("PCI: Intel 803xx PCI init code.\n"); | ||
| 333 | DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); | 359 | DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); |
| 334 | DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n", | ||
| 335 | *IOP3XX_OMWTVR0, | ||
| 336 | *IOP3XX_OIOWTVR); | ||
| 337 | DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR); | 360 | DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR); |
| 338 | DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n", | ||
| 339 | *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0); | ||
| 340 | DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0); | ||
| 341 | DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n", | ||
| 342 | *IOP3XX_IABAR1, *IOP3XX_IALR1); | ||
| 343 | DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n", | ||
| 344 | *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR); | ||
| 345 | DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n", | ||
| 346 | *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2); | ||
| 347 | DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n", | ||
| 348 | *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3); | ||
| 349 | 361 | ||
| 350 | hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort"); | 362 | hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort"); |
| 351 | } | 363 | } |
| 352 | 364 | ||
| 365 | /* for platforms that might be host-bus-adapters */ | ||
| 366 | void __init iop3xx_pci_preinit_cond(void) | ||
| 367 | { | ||
| 368 | if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { | ||
| 369 | iop3xx_atu_disable(); | ||
| 370 | iop3xx_atu_setup(); | ||
| 371 | iop3xx_atu_debug(); | ||
| 372 | } | ||
| 373 | } | ||
| 374 | |||
| 375 | void __init iop3xx_pci_preinit(void) | ||
| 376 | { | ||
| 377 | iop3xx_atu_disable(); | ||
| 378 | iop3xx_atu_setup(); | ||
| 379 | iop3xx_atu_debug(); | ||
| 380 | } | ||
| 381 | |||
| 353 | /* allow init_atu to be user overridden */ | 382 | /* allow init_atu to be user overridden */ |
| 354 | static int __init iop3xx_init_atu_setup(char *str) | 383 | static int __init iop3xx_init_atu_setup(char *str) |
| 355 | { | 384 | { |
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 03a65c0dfb60..bb6e12738fb3 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig | |||
| @@ -4,7 +4,7 @@ menu "Freescale MXC Implementations" | |||
| 4 | 4 | ||
| 5 | choice | 5 | choice |
| 6 | prompt "MXC/iMX System Type" | 6 | prompt "MXC/iMX System Type" |
| 7 | default 0 | 7 | default ARCH_MX3 |
| 8 | 8 | ||
| 9 | config ARCH_MX3 | 9 | config ARCH_MX3 |
| 10 | bool "MX3-based" | 10 | bool "MX3-based" |
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 66ad9c2b6d64..f96dc0362068 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile | |||
| @@ -4,7 +4,3 @@ | |||
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := irq.o | 6 | obj-y := irq.o |
| 7 | |||
| 8 | obj-m := | ||
| 9 | obj-n := | ||
| 10 | obj- := | ||
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c index 87d253bc3d3c..2ad5a6917b3f 100644 --- a/arch/arm/plat-mxc/irq.c +++ b/arch/arm/plat-mxc/irq.c | |||
| @@ -19,21 +19,13 @@ | |||
| 19 | #include <asm/mach/irq.h> | 19 | #include <asm/mach/irq.h> |
| 20 | #include <asm/arch/common.h> | 20 | #include <asm/arch/common.h> |
| 21 | 21 | ||
| 22 | /*! | 22 | /* Disable interrupt number "irq" in the AVIC */ |
| 23 | * Disable interrupt number "irq" in the AVIC | ||
| 24 | * | ||
| 25 | * @param irq interrupt source number | ||
| 26 | */ | ||
| 27 | static void mxc_mask_irq(unsigned int irq) | 23 | static void mxc_mask_irq(unsigned int irq) |
| 28 | { | 24 | { |
| 29 | __raw_writel(irq, AVIC_INTDISNUM); | 25 | __raw_writel(irq, AVIC_INTDISNUM); |
| 30 | } | 26 | } |
| 31 | 27 | ||
| 32 | /*! | 28 | /* Enable interrupt number "irq" in the AVIC */ |
| 33 | * Enable interrupt number "irq" in the AVIC | ||
| 34 | * | ||
| 35 | * @param irq interrupt source number | ||
| 36 | */ | ||
| 37 | static void mxc_unmask_irq(unsigned int irq) | 29 | static void mxc_unmask_irq(unsigned int irq) |
| 38 | { | 30 | { |
| 39 | __raw_writel(irq, AVIC_INTENNUM); | 31 | __raw_writel(irq, AVIC_INTENNUM); |
| @@ -45,7 +37,7 @@ static struct irq_chip mxc_avic_chip = { | |||
| 45 | .unmask = mxc_unmask_irq, | 37 | .unmask = mxc_unmask_irq, |
| 46 | }; | 38 | }; |
| 47 | 39 | ||
| 48 | /*! | 40 | /* |
| 49 | * This function initializes the AVIC hardware and disables all the | 41 | * This function initializes the AVIC hardware and disables all the |
| 50 | * interrupts. It registers the interrupt enable and disable functions | 42 | * interrupts. It registers the interrupt enable and disable functions |
| 51 | * to the kernel for each interrupt source. | 43 | * to the kernel for each interrupt source. |
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 8f56c255d1ee..bc639a30d6d1 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile | |||
| @@ -9,8 +9,6 @@ obj-m := | |||
| 9 | obj-n := | 9 | obj-n := |
| 10 | obj- := | 10 | obj- := |
| 11 | 11 | ||
| 12 | obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o | ||
| 13 | |||
| 14 | # OCPI interconnect support for 1710, 1610 and 5912 | 12 | # OCPI interconnect support for 1710, 1610 and 5912 |
| 15 | obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o | 13 | obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o |
| 16 | 14 | ||
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 0a603242f367..72d34a23a2ec 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c | |||
| @@ -23,7 +23,6 @@ | |||
| 23 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
| 24 | 24 | ||
| 25 | #include <asm/io.h> | 25 | #include <asm/io.h> |
| 26 | #include <asm/semaphore.h> | ||
| 27 | 26 | ||
| 28 | #include <asm/arch/clock.h> | 27 | #include <asm/arch/clock.h> |
| 29 | 28 | ||
| @@ -304,6 +303,23 @@ void propagate_rate(struct clk * tclk) | |||
| 304 | } | 303 | } |
| 305 | } | 304 | } |
| 306 | 305 | ||
| 306 | /** | ||
| 307 | * recalculate_root_clocks - recalculate and propagate all root clocks | ||
| 308 | * | ||
| 309 | * Recalculates all root clocks (clocks with no parent), which if the | ||
| 310 | * clock's .recalc is set correctly, should also propagate their rates. | ||
| 311 | * Called at init. | ||
| 312 | */ | ||
| 313 | void recalculate_root_clocks(void) | ||
| 314 | { | ||
| 315 | struct clk *clkp; | ||
| 316 | |||
| 317 | list_for_each_entry(clkp, &clocks, node) { | ||
| 318 | if (unlikely(!clkp->parent) && likely((u32)clkp->recalc)) | ||
| 319 | clkp->recalc(clkp); | ||
| 320 | } | ||
| 321 | } | ||
| 322 | |||
| 307 | int clk_register(struct clk *clk) | 323 | int clk_register(struct clk *clk) |
| 308 | { | 324 | { |
| 309 | if (clk == NULL || IS_ERR(clk)) | 325 | if (clk == NULL || IS_ERR(clk)) |
| @@ -358,6 +374,30 @@ void clk_allow_idle(struct clk *clk) | |||
| 358 | } | 374 | } |
| 359 | EXPORT_SYMBOL(clk_allow_idle); | 375 | EXPORT_SYMBOL(clk_allow_idle); |
| 360 | 376 | ||
| 377 | void clk_enable_init_clocks(void) | ||
| 378 | { | ||
| 379 | struct clk *clkp; | ||
| 380 | |||
| 381 | list_for_each_entry(clkp, &clocks, node) { | ||
| 382 | if (clkp->flags & ENABLE_ON_INIT) | ||
| 383 | clk_enable(clkp); | ||
| 384 | } | ||
| 385 | } | ||
| 386 | EXPORT_SYMBOL(clk_enable_init_clocks); | ||
| 387 | |||
| 388 | #ifdef CONFIG_CPU_FREQ | ||
| 389 | void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) | ||
| 390 | { | ||
| 391 | unsigned long flags; | ||
| 392 | |||
| 393 | spin_lock_irqsave(&clockfw_lock, flags); | ||
| 394 | if (arch_clock->clk_init_cpufreq_table) | ||
| 395 | arch_clock->clk_init_cpufreq_table(table); | ||
| 396 | spin_unlock_irqrestore(&clockfw_lock, flags); | ||
| 397 | } | ||
| 398 | EXPORT_SYMBOL(clk_init_cpufreq_table); | ||
| 399 | #endif | ||
| 400 | |||
| 361 | /*-------------------------------------------------------------------------*/ | 401 | /*-------------------------------------------------------------------------*/ |
| 362 | 402 | ||
| 363 | #ifdef CONFIG_OMAP_RESET_CLOCKS | 403 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
| @@ -396,3 +436,4 @@ int __init clk_init(struct clk_functions * custom_clocks) | |||
| 396 | 436 | ||
| 397 | return 0; | 437 | return 0; |
| 398 | } | 438 | } |
| 439 | |||
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 4f0f9c4e938e..bd1cef2c3c14 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c | |||
| @@ -27,11 +27,16 @@ | |||
| 27 | #include <asm/setup.h> | 27 | #include <asm/setup.h> |
| 28 | 28 | ||
| 29 | #include <asm/arch/board.h> | 29 | #include <asm/arch/board.h> |
| 30 | #include <asm/arch/control.h> | ||
| 30 | #include <asm/arch/mux.h> | 31 | #include <asm/arch/mux.h> |
| 31 | #include <asm/arch/fpga.h> | 32 | #include <asm/arch/fpga.h> |
| 32 | 33 | ||
| 33 | #include <asm/arch/clock.h> | 34 | #include <asm/arch/clock.h> |
| 34 | 35 | ||
| 36 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | ||
| 37 | # include "../mach-omap2/sdrc.h" | ||
| 38 | #endif | ||
| 39 | |||
| 35 | #define NO_LENGTH_CHECK 0xffffffff | 40 | #define NO_LENGTH_CHECK 0xffffffff |
| 36 | 41 | ||
| 37 | unsigned char omap_bootloader_tag[512]; | 42 | unsigned char omap_bootloader_tag[512]; |
| @@ -171,8 +176,8 @@ console_initcall(omap_add_serial_console); | |||
| 171 | 176 | ||
| 172 | #if defined(CONFIG_ARCH_OMAP16XX) | 177 | #if defined(CONFIG_ARCH_OMAP16XX) |
| 173 | #define TIMER_32K_SYNCHRONIZED 0xfffbc410 | 178 | #define TIMER_32K_SYNCHRONIZED 0xfffbc410 |
| 174 | #elif defined(CONFIG_ARCH_OMAP24XX) | 179 | #elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 175 | #define TIMER_32K_SYNCHRONIZED (OMAP24XX_32KSYNCT_BASE + 0x10) | 180 | #define TIMER_32K_SYNCHRONIZED (OMAP2_32KSYNCT_BASE + 0x10) |
| 176 | #endif | 181 | #endif |
| 177 | 182 | ||
| 178 | #ifdef TIMER_32K_SYNCHRONIZED | 183 | #ifdef TIMER_32K_SYNCHRONIZED |
| @@ -193,12 +198,35 @@ static struct clocksource clocksource_32k = { | |||
| 193 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 198 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 194 | }; | 199 | }; |
| 195 | 200 | ||
| 201 | /* | ||
| 202 | * Rounds down to nearest nsec. | ||
| 203 | */ | ||
| 204 | unsigned long long omap_32k_ticks_to_nsecs(unsigned long ticks_32k) | ||
| 205 | { | ||
| 206 | return cyc2ns(&clocksource_32k, ticks_32k); | ||
| 207 | } | ||
| 208 | |||
| 209 | /* | ||
| 210 | * Returns current time from boot in nsecs. It's OK for this to wrap | ||
| 211 | * around for now, as it's just a relative time stamp. | ||
| 212 | */ | ||
| 213 | unsigned long long sched_clock(void) | ||
| 214 | { | ||
| 215 | return omap_32k_ticks_to_nsecs(omap_32k_read()); | ||
| 216 | } | ||
| 217 | |||
| 196 | static int __init omap_init_clocksource_32k(void) | 218 | static int __init omap_init_clocksource_32k(void) |
| 197 | { | 219 | { |
| 198 | static char err[] __initdata = KERN_ERR | 220 | static char err[] __initdata = KERN_ERR |
| 199 | "%s: can't register clocksource!\n"; | 221 | "%s: can't register clocksource!\n"; |
| 200 | 222 | ||
| 201 | if (cpu_is_omap16xx() || cpu_is_omap24xx()) { | 223 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { |
| 224 | struct clk *sync_32k_ick; | ||
| 225 | |||
| 226 | sync_32k_ick = clk_get(NULL, "omap_32ksync_ick"); | ||
| 227 | if (sync_32k_ick) | ||
| 228 | clk_enable(sync_32k_ick); | ||
| 229 | |||
| 202 | clocksource_32k.mult = clocksource_hz2mult(32768, | 230 | clocksource_32k.mult = clocksource_hz2mult(32768, |
| 203 | clocksource_32k.shift); | 231 | clocksource_32k.shift); |
| 204 | 232 | ||
| @@ -210,3 +238,33 @@ static int __init omap_init_clocksource_32k(void) | |||
| 210 | arch_initcall(omap_init_clocksource_32k); | 238 | arch_initcall(omap_init_clocksource_32k); |
| 211 | 239 | ||
| 212 | #endif /* TIMER_32K_SYNCHRONIZED */ | 240 | #endif /* TIMER_32K_SYNCHRONIZED */ |
| 241 | |||
| 242 | /* Global address base setup code */ | ||
| 243 | |||
| 244 | #if defined(CONFIG_ARCH_OMAP2420) | ||
| 245 | void __init omap2_set_globals_242x(void) | ||
| 246 | { | ||
| 247 | omap2_sdrc_base = OMAP2420_SDRC_BASE; | ||
| 248 | omap2_sms_base = OMAP2420_SMS_BASE; | ||
| 249 | omap_ctrl_base_set(OMAP2420_CTRL_BASE); | ||
| 250 | } | ||
| 251 | #endif | ||
| 252 | |||
| 253 | #if defined(CONFIG_ARCH_OMAP2430) | ||
| 254 | void __init omap2_set_globals_243x(void) | ||
| 255 | { | ||
| 256 | omap2_sdrc_base = OMAP243X_SDRC_BASE; | ||
| 257 | omap2_sms_base = OMAP243X_SMS_BASE; | ||
| 258 | omap_ctrl_base_set(OMAP243X_CTRL_BASE); | ||
| 259 | } | ||
| 260 | #endif | ||
| 261 | |||
| 262 | #if defined(CONFIG_ARCH_OMAP3430) | ||
| 263 | void __init omap2_set_globals_343x(void) | ||
| 264 | { | ||
| 265 | omap2_sdrc_base = OMAP343X_SDRC_BASE; | ||
| 266 | omap2_sms_base = OMAP343X_SMS_BASE; | ||
| 267 | omap_ctrl_base_set(OMAP343X_CTRL_BASE); | ||
| 268 | } | ||
| 269 | #endif | ||
| 270 | |||
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 8c78e4e57b5c..1903a3491ee9 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c | |||
| @@ -136,7 +136,6 @@ struct gpio_bank { | |||
| 136 | u16 irq; | 136 | u16 irq; |
| 137 | u16 virtual_irq_start; | 137 | u16 virtual_irq_start; |
| 138 | int method; | 138 | int method; |
| 139 | u32 reserved_map; | ||
| 140 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 139 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 141 | u32 suspend_wakeup; | 140 | u32 suspend_wakeup; |
| 142 | u32 saved_wakeup; | 141 | u32 saved_wakeup; |
| @@ -149,7 +148,9 @@ struct gpio_bank { | |||
| 149 | u32 saved_fallingdetect; | 148 | u32 saved_fallingdetect; |
| 150 | u32 saved_risingdetect; | 149 | u32 saved_risingdetect; |
| 151 | #endif | 150 | #endif |
| 151 | u32 level_mask; | ||
| 152 | spinlock_t lock; | 152 | spinlock_t lock; |
| 153 | struct gpio_chip chip; | ||
| 153 | }; | 154 | }; |
| 154 | 155 | ||
| 155 | #define METHOD_MPUIO 0 | 156 | #define METHOD_MPUIO 0 |
| @@ -538,10 +539,9 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, | |||
| 538 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | 539 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; |
| 539 | } | 540 | } |
| 540 | 541 | ||
| 541 | /* | 542 | bank->level_mask = |
| 542 | * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only | 543 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | |
| 543 | * level triggering requested. | 544 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); |
| 544 | */ | ||
| 545 | } | 545 | } |
| 546 | #endif | 546 | #endif |
| 547 | 547 | ||
| @@ -652,6 +652,12 @@ static int gpio_irq_type(unsigned irq, unsigned type) | |||
| 652 | irq_desc[irq].status |= type; | 652 | irq_desc[irq].status |= type; |
| 653 | } | 653 | } |
| 654 | spin_unlock_irqrestore(&bank->lock, flags); | 654 | spin_unlock_irqrestore(&bank->lock, flags); |
| 655 | |||
| 656 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | ||
| 657 | __set_irq_handler_unlocked(irq, handle_level_irq); | ||
| 658 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | ||
| 659 | __set_irq_handler_unlocked(irq, handle_edge_irq); | ||
| 660 | |||
| 655 | return retval; | 661 | return retval; |
| 656 | } | 662 | } |
| 657 | 663 | ||
| @@ -903,19 +909,17 @@ int omap_request_gpio(int gpio) | |||
| 903 | { | 909 | { |
| 904 | struct gpio_bank *bank; | 910 | struct gpio_bank *bank; |
| 905 | unsigned long flags; | 911 | unsigned long flags; |
| 912 | int status; | ||
| 906 | 913 | ||
| 907 | if (check_gpio(gpio) < 0) | 914 | if (check_gpio(gpio) < 0) |
| 908 | return -EINVAL; | 915 | return -EINVAL; |
| 909 | 916 | ||
| 917 | status = gpio_request(gpio, NULL); | ||
| 918 | if (status < 0) | ||
| 919 | return status; | ||
| 920 | |||
| 910 | bank = get_gpio_bank(gpio); | 921 | bank = get_gpio_bank(gpio); |
| 911 | spin_lock_irqsave(&bank->lock, flags); | 922 | spin_lock_irqsave(&bank->lock, flags); |
| 912 | if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) { | ||
| 913 | printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio); | ||
| 914 | dump_stack(); | ||
| 915 | spin_unlock_irqrestore(&bank->lock, flags); | ||
| 916 | return -1; | ||
| 917 | } | ||
| 918 | bank->reserved_map |= (1 << get_gpio_index(gpio)); | ||
| 919 | 923 | ||
| 920 | /* Set trigger to none. You need to enable the desired trigger with | 924 | /* Set trigger to none. You need to enable the desired trigger with |
| 921 | * request_irq() or set_irq_type(). | 925 | * request_irq() or set_irq_type(). |
| @@ -945,10 +949,11 @@ void omap_free_gpio(int gpio) | |||
| 945 | return; | 949 | return; |
| 946 | bank = get_gpio_bank(gpio); | 950 | bank = get_gpio_bank(gpio); |
| 947 | spin_lock_irqsave(&bank->lock, flags); | 951 | spin_lock_irqsave(&bank->lock, flags); |
| 948 | if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) { | 952 | if (unlikely(!gpiochip_is_requested(&bank->chip, |
| 953 | get_gpio_index(gpio)))) { | ||
| 954 | spin_unlock_irqrestore(&bank->lock, flags); | ||
| 949 | printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio); | 955 | printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio); |
| 950 | dump_stack(); | 956 | dump_stack(); |
| 951 | spin_unlock_irqrestore(&bank->lock, flags); | ||
| 952 | return; | 957 | return; |
| 953 | } | 958 | } |
| 954 | #ifdef CONFIG_ARCH_OMAP16XX | 959 | #ifdef CONFIG_ARCH_OMAP16XX |
| @@ -965,9 +970,9 @@ void omap_free_gpio(int gpio) | |||
| 965 | __raw_writel(1 << get_gpio_index(gpio), reg); | 970 | __raw_writel(1 << get_gpio_index(gpio), reg); |
| 966 | } | 971 | } |
| 967 | #endif | 972 | #endif |
| 968 | bank->reserved_map &= ~(1 << get_gpio_index(gpio)); | ||
| 969 | _reset_gpio(bank, gpio); | 973 | _reset_gpio(bank, gpio); |
| 970 | spin_unlock_irqrestore(&bank->lock, flags); | 974 | spin_unlock_irqrestore(&bank->lock, flags); |
| 975 | gpio_free(gpio); | ||
| 971 | } | 976 | } |
| 972 | 977 | ||
| 973 | /* | 978 | /* |
| @@ -1022,12 +1027,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
| 1022 | isr &= 0x0000ffff; | 1027 | isr &= 0x0000ffff; |
| 1023 | 1028 | ||
| 1024 | if (cpu_class_is_omap2()) { | 1029 | if (cpu_class_is_omap2()) { |
| 1025 | level_mask = | 1030 | level_mask = bank->level_mask & enabled; |
| 1026 | __raw_readl(bank->base + | ||
| 1027 | OMAP24XX_GPIO_LEVELDETECT0) | | ||
| 1028 | __raw_readl(bank->base + | ||
| 1029 | OMAP24XX_GPIO_LEVELDETECT1); | ||
| 1030 | level_mask &= enabled; | ||
| 1031 | } | 1031 | } |
| 1032 | 1032 | ||
| 1033 | /* clear edge sensitive interrupts before handler(s) are | 1033 | /* clear edge sensitive interrupts before handler(s) are |
| @@ -1052,51 +1052,13 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
| 1052 | gpio_irq = bank->virtual_irq_start; | 1052 | gpio_irq = bank->virtual_irq_start; |
| 1053 | for (; isr != 0; isr >>= 1, gpio_irq++) { | 1053 | for (; isr != 0; isr >>= 1, gpio_irq++) { |
| 1054 | struct irq_desc *d; | 1054 | struct irq_desc *d; |
| 1055 | int irq_mask; | 1055 | |
| 1056 | if (!(isr & 1)) | 1056 | if (!(isr & 1)) |
| 1057 | continue; | 1057 | continue; |
| 1058 | d = irq_desc + gpio_irq; | 1058 | d = irq_desc + gpio_irq; |
| 1059 | /* Don't run the handler if it's already running | ||
| 1060 | * or was disabled lazely. | ||
| 1061 | */ | ||
| 1062 | if (unlikely((d->depth || | ||
| 1063 | (d->status & IRQ_INPROGRESS)))) { | ||
| 1064 | irq_mask = 1 << | ||
| 1065 | (gpio_irq - bank->virtual_irq_start); | ||
| 1066 | /* The unmasking will be done by | ||
| 1067 | * enable_irq in case it is disabled or | ||
| 1068 | * after returning from the handler if | ||
| 1069 | * it's already running. | ||
| 1070 | */ | ||
| 1071 | _enable_gpio_irqbank(bank, irq_mask, 0); | ||
| 1072 | if (!d->depth) { | ||
| 1073 | /* Level triggered interrupts | ||
| 1074 | * won't ever be reentered | ||
| 1075 | */ | ||
| 1076 | BUG_ON(level_mask & irq_mask); | ||
| 1077 | d->status |= IRQ_PENDING; | ||
| 1078 | } | ||
| 1079 | continue; | ||
| 1080 | } | ||
| 1081 | 1059 | ||
| 1082 | desc_handle_irq(gpio_irq, d); | 1060 | desc_handle_irq(gpio_irq, d); |
| 1083 | |||
| 1084 | if (unlikely((d->status & IRQ_PENDING) && !d->depth)) { | ||
| 1085 | irq_mask = 1 << | ||
| 1086 | (gpio_irq - bank->virtual_irq_start); | ||
| 1087 | d->status &= ~IRQ_PENDING; | ||
| 1088 | _enable_gpio_irqbank(bank, irq_mask, 1); | ||
| 1089 | retrigger |= irq_mask; | ||
| 1090 | } | ||
| 1091 | } | 1061 | } |
| 1092 | |||
| 1093 | if (cpu_class_is_omap2()) { | ||
| 1094 | /* clear level sensitive interrupts after handler(s) */ | ||
| 1095 | _enable_gpio_irqbank(bank, isr_saved & level_mask, 0); | ||
| 1096 | _clear_gpio_irqbank(bank, isr_saved & level_mask); | ||
| 1097 | _enable_gpio_irqbank(bank, isr_saved & level_mask, 1); | ||
| 1098 | } | ||
| 1099 | |||
| 1100 | } | 1062 | } |
| 1101 | /* if bank has any level sensitive GPIO pin interrupt | 1063 | /* if bank has any level sensitive GPIO pin interrupt |
| 1102 | configured, we must unmask the bank interrupt only after | 1064 | configured, we must unmask the bank interrupt only after |
| @@ -1135,6 +1097,14 @@ static void gpio_unmask_irq(unsigned int irq) | |||
| 1135 | { | 1097 | { |
| 1136 | unsigned int gpio = irq - IH_GPIO_BASE; | 1098 | unsigned int gpio = irq - IH_GPIO_BASE; |
| 1137 | struct gpio_bank *bank = get_irq_chip_data(irq); | 1099 | struct gpio_bank *bank = get_irq_chip_data(irq); |
| 1100 | unsigned int irq_mask = 1 << get_gpio_index(gpio); | ||
| 1101 | |||
| 1102 | /* For level-triggered GPIOs, the clearing must be done after | ||
| 1103 | * the HW source is cleared, thus after the handler has run */ | ||
| 1104 | if (bank->level_mask & irq_mask) { | ||
| 1105 | _set_gpio_irqenable(bank, gpio, 0); | ||
| 1106 | _clear_gpio_irqstatus(bank, gpio); | ||
| 1107 | } | ||
| 1138 | 1108 | ||
| 1139 | _set_gpio_irqenable(bank, gpio, 1); | 1109 | _set_gpio_irqenable(bank, gpio, 1); |
| 1140 | } | 1110 | } |
| @@ -1266,6 +1236,53 @@ static inline void mpuio_init(void) {} | |||
| 1266 | 1236 | ||
| 1267 | /*---------------------------------------------------------------------*/ | 1237 | /*---------------------------------------------------------------------*/ |
| 1268 | 1238 | ||
| 1239 | /* REVISIT these are stupid implementations! replace by ones that | ||
| 1240 | * don't switch on METHOD_* and which mostly avoid spinlocks | ||
| 1241 | */ | ||
| 1242 | |||
| 1243 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | ||
| 1244 | { | ||
| 1245 | struct gpio_bank *bank; | ||
| 1246 | unsigned long flags; | ||
| 1247 | |||
| 1248 | bank = container_of(chip, struct gpio_bank, chip); | ||
| 1249 | spin_lock_irqsave(&bank->lock, flags); | ||
| 1250 | _set_gpio_direction(bank, offset, 1); | ||
| 1251 | spin_unlock_irqrestore(&bank->lock, flags); | ||
| 1252 | return 0; | ||
| 1253 | } | ||
| 1254 | |||
| 1255 | static int gpio_get(struct gpio_chip *chip, unsigned offset) | ||
| 1256 | { | ||
| 1257 | return omap_get_gpio_datain(chip->base + offset); | ||
| 1258 | } | ||
| 1259 | |||
| 1260 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | ||
| 1261 | { | ||
| 1262 | struct gpio_bank *bank; | ||
| 1263 | unsigned long flags; | ||
| 1264 | |||
| 1265 | bank = container_of(chip, struct gpio_bank, chip); | ||
| 1266 | spin_lock_irqsave(&bank->lock, flags); | ||
| 1267 | _set_gpio_dataout(bank, offset, value); | ||
| 1268 | _set_gpio_direction(bank, offset, 0); | ||
| 1269 | spin_unlock_irqrestore(&bank->lock, flags); | ||
| 1270 | return 0; | ||
| 1271 | } | ||
| 1272 | |||
| 1273 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) | ||
| 1274 | { | ||
| 1275 | struct gpio_bank *bank; | ||
| 1276 | unsigned long flags; | ||
| 1277 | |||
| 1278 | bank = container_of(chip, struct gpio_bank, chip); | ||
| 1279 | spin_lock_irqsave(&bank->lock, flags); | ||
| 1280 | _set_gpio_dataout(bank, offset, value); | ||
| 1281 | spin_unlock_irqrestore(&bank->lock, flags); | ||
| 1282 | } | ||
| 1283 | |||
| 1284 | /*---------------------------------------------------------------------*/ | ||
| 1285 | |||
| 1269 | static int initialized; | 1286 | static int initialized; |
| 1270 | #if !defined(CONFIG_ARCH_OMAP3) | 1287 | #if !defined(CONFIG_ARCH_OMAP3) |
| 1271 | static struct clk * gpio_ick; | 1288 | static struct clk * gpio_ick; |
| @@ -1293,6 +1310,7 @@ static struct lock_class_key gpio_lock_class; | |||
| 1293 | static int __init _omap_gpio_init(void) | 1310 | static int __init _omap_gpio_init(void) |
| 1294 | { | 1311 | { |
| 1295 | int i; | 1312 | int i; |
| 1313 | int gpio = 0; | ||
| 1296 | struct gpio_bank *bank; | 1314 | struct gpio_bank *bank; |
| 1297 | #if defined(CONFIG_ARCH_OMAP3) | 1315 | #if defined(CONFIG_ARCH_OMAP3) |
| 1298 | char clk_name[11]; | 1316 | char clk_name[11]; |
| @@ -1423,7 +1441,6 @@ static int __init _omap_gpio_init(void) | |||
| 1423 | int j, gpio_count = 16; | 1441 | int j, gpio_count = 16; |
| 1424 | 1442 | ||
| 1425 | bank = &gpio_bank[i]; | 1443 | bank = &gpio_bank[i]; |
| 1426 | bank->reserved_map = 0; | ||
| 1427 | bank->base = IO_ADDRESS(bank->base); | 1444 | bank->base = IO_ADDRESS(bank->base); |
| 1428 | spin_lock_init(&bank->lock); | 1445 | spin_lock_init(&bank->lock); |
| 1429 | if (bank_is_mpuio(bank)) | 1446 | if (bank_is_mpuio(bank)) |
| @@ -1461,6 +1478,26 @@ static int __init _omap_gpio_init(void) | |||
| 1461 | gpio_count = 32; | 1478 | gpio_count = 32; |
| 1462 | } | 1479 | } |
| 1463 | #endif | 1480 | #endif |
| 1481 | |||
| 1482 | /* REVISIT eventually switch from OMAP-specific gpio structs | ||
| 1483 | * over to the generic ones | ||
| 1484 | */ | ||
| 1485 | bank->chip.direction_input = gpio_input; | ||
| 1486 | bank->chip.get = gpio_get; | ||
| 1487 | bank->chip.direction_output = gpio_output; | ||
| 1488 | bank->chip.set = gpio_set; | ||
| 1489 | if (bank_is_mpuio(bank)) { | ||
| 1490 | bank->chip.label = "mpuio"; | ||
| 1491 | bank->chip.base = OMAP_MPUIO(0); | ||
| 1492 | } else { | ||
| 1493 | bank->chip.label = "gpio"; | ||
| 1494 | bank->chip.base = gpio; | ||
| 1495 | gpio += gpio_count; | ||
| 1496 | } | ||
| 1497 | bank->chip.ngpio = gpio_count; | ||
| 1498 | |||
| 1499 | gpiochip_add(&bank->chip); | ||
| 1500 | |||
| 1464 | for (j = bank->virtual_irq_start; | 1501 | for (j = bank->virtual_irq_start; |
| 1465 | j < bank->virtual_irq_start + gpio_count; j++) { | 1502 | j < bank->virtual_irq_start + gpio_count; j++) { |
| 1466 | lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); | 1503 | lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); |
| @@ -1757,8 +1794,10 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) | |||
| 1757 | 1794 | ||
| 1758 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { | 1795 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { |
| 1759 | unsigned irq, value, is_in, irqstat; | 1796 | unsigned irq, value, is_in, irqstat; |
| 1797 | const char *label; | ||
| 1760 | 1798 | ||
| 1761 | if (!(bank->reserved_map & mask)) | 1799 | label = gpiochip_is_requested(&bank->chip, j); |
| 1800 | if (!label) | ||
| 1762 | continue; | 1801 | continue; |
| 1763 | 1802 | ||
| 1764 | irq = bank->virtual_irq_start + j; | 1803 | irq = bank->virtual_irq_start + j; |
| @@ -1766,13 +1805,16 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) | |||
| 1766 | is_in = gpio_is_input(bank, mask); | 1805 | is_in = gpio_is_input(bank, mask); |
| 1767 | 1806 | ||
| 1768 | if (bank_is_mpuio(bank)) | 1807 | if (bank_is_mpuio(bank)) |
| 1769 | seq_printf(s, "MPUIO %2d: ", j); | 1808 | seq_printf(s, "MPUIO %2d ", j); |
| 1770 | else | 1809 | else |
| 1771 | seq_printf(s, "GPIO %3d: ", gpio); | 1810 | seq_printf(s, "GPIO %3d ", gpio); |
| 1772 | seq_printf(s, "%s %s", | 1811 | seq_printf(s, "(%10s): %s %s", |
| 1812 | label, | ||
| 1773 | is_in ? "in " : "out", | 1813 | is_in ? "in " : "out", |
| 1774 | value ? "hi" : "lo"); | 1814 | value ? "hi" : "lo"); |
| 1775 | 1815 | ||
| 1816 | /* FIXME for at least omap2, show pullup/pulldown state */ | ||
| 1817 | |||
| 1776 | irqstat = irq_desc[irq].status; | 1818 | irqstat = irq_desc[irq].status; |
| 1777 | if (is_in && ((bank->suspend_wakeup & mask) | 1819 | if (is_in && ((bank->suspend_wakeup & mask) |
| 1778 | || irqstat & IRQ_TYPE_SENSE_MASK)) { | 1820 | || irqstat & IRQ_TYPE_SENSE_MASK)) { |
| @@ -1795,10 +1837,10 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) | |||
| 1795 | trigger = "high"; | 1837 | trigger = "high"; |
| 1796 | break; | 1838 | break; |
| 1797 | case IRQ_TYPE_NONE: | 1839 | case IRQ_TYPE_NONE: |
| 1798 | trigger = "(unspecified)"; | 1840 | trigger = "(?)"; |
| 1799 | break; | 1841 | break; |
| 1800 | } | 1842 | } |
| 1801 | seq_printf(s, ", irq-%d %s%s", | 1843 | seq_printf(s, ", irq-%d %-8s%s", |
| 1802 | irq, trigger, | 1844 | irq, trigger, |
| 1803 | (bank->suspend_wakeup & mask) | 1845 | (bank->suspend_wakeup & mask) |
| 1804 | ? " wakeup" : ""); | 1846 | ? " wakeup" : ""); |
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c index 75211f20ccb3..6f3f459731c8 100644 --- a/arch/arm/plat-omap/mux.c +++ b/arch/arm/plat-omap/mux.c | |||
| @@ -3,9 +3,9 @@ | |||
| 3 | * | 3 | * |
| 4 | * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h | 4 | * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2003 - 2005 Nokia Corporation | 6 | * Copyright (C) 2003 - 2008 Nokia Corporation |
| 7 | * | 7 | * |
| 8 | * Written by Tony Lindgren <tony.lindgren@nokia.com> | 8 | * Written by Tony Lindgren |
| 9 | * | 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify | 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by | 11 | * it under the terms of the GNU General Public License as published by |
| @@ -32,21 +32,17 @@ | |||
| 32 | 32 | ||
| 33 | #ifdef CONFIG_OMAP_MUX | 33 | #ifdef CONFIG_OMAP_MUX |
| 34 | 34 | ||
| 35 | #define OMAP24XX_L4_BASE 0x48000000 | 35 | static struct omap_mux_cfg *mux_cfg; |
| 36 | #define OMAP24XX_PULL_ENA (1 << 3) | ||
| 37 | #define OMAP24XX_PULL_UP (1 << 4) | ||
| 38 | 36 | ||
| 39 | static struct pin_config * pin_table; | 37 | int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg) |
| 40 | static unsigned long pin_table_sz; | ||
| 41 | |||
| 42 | extern struct pin_config * omap730_pins; | ||
| 43 | extern struct pin_config * omap1xxx_pins; | ||
| 44 | extern struct pin_config * omap24xx_pins; | ||
| 45 | |||
| 46 | int __init omap_mux_register(struct pin_config * pins, unsigned long size) | ||
| 47 | { | 38 | { |
| 48 | pin_table = pins; | 39 | if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0 |
| 49 | pin_table_sz = size; | 40 | || !arch_mux_cfg->cfg_reg) { |
| 41 | printk(KERN_ERR "Invalid pin table\n"); | ||
| 42 | return -EINVAL; | ||
| 43 | } | ||
| 44 | |||
| 45 | mux_cfg = arch_mux_cfg; | ||
| 50 | 46 | ||
| 51 | return 0; | 47 | return 0; |
| 52 | } | 48 | } |
| @@ -56,152 +52,26 @@ int __init omap_mux_register(struct pin_config * pins, unsigned long size) | |||
| 56 | */ | 52 | */ |
| 57 | int __init_or_module omap_cfg_reg(const unsigned long index) | 53 | int __init_or_module omap_cfg_reg(const unsigned long index) |
| 58 | { | 54 | { |
| 59 | static DEFINE_SPINLOCK(mux_spin_lock); | 55 | struct pin_config *reg; |
| 60 | |||
| 61 | unsigned long flags; | ||
| 62 | struct pin_config *cfg; | ||
| 63 | unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0, | ||
| 64 | pull_orig = 0, pull = 0; | ||
| 65 | unsigned int mask, warn = 0; | ||
| 66 | 56 | ||
| 67 | if (!pin_table) | 57 | if (mux_cfg == NULL) { |
| 68 | BUG(); | 58 | printk(KERN_ERR "Pin mux table not initialized\n"); |
| 59 | return -ENODEV; | ||
| 60 | } | ||
| 69 | 61 | ||
| 70 | if (index >= pin_table_sz) { | 62 | if (index >= mux_cfg->size) { |
| 71 | printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", | 63 | printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", |
| 72 | index, pin_table_sz); | 64 | index, mux_cfg->size); |
| 73 | dump_stack(); | 65 | dump_stack(); |
| 74 | return -ENODEV; | 66 | return -ENODEV; |
| 75 | } | 67 | } |
| 76 | 68 | ||
| 77 | cfg = (struct pin_config *)&pin_table[index]; | 69 | reg = (struct pin_config *)&mux_cfg->pins[index]; |
| 78 | if (cpu_is_omap24xx()) { | ||
| 79 | u8 reg = 0; | ||
| 80 | |||
| 81 | reg |= cfg->mask & 0x7; | ||
| 82 | if (cfg->pull_val) | ||
| 83 | reg |= OMAP24XX_PULL_ENA; | ||
| 84 | if(cfg->pu_pd_val) | ||
| 85 | reg |= OMAP24XX_PULL_UP; | ||
| 86 | #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) | ||
| 87 | { | ||
| 88 | u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg); | ||
| 89 | u8 debug = 0; | ||
| 90 | |||
| 91 | #ifdef CONFIG_OMAP_MUX_DEBUG | ||
| 92 | debug = cfg->debug; | ||
| 93 | #endif | ||
| 94 | warn = (orig != reg); | ||
| 95 | if (debug || warn) | ||
| 96 | printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n", | ||
| 97 | cfg->name, | ||
| 98 | OMAP24XX_L4_BASE + cfg->mux_reg, | ||
| 99 | orig, reg); | ||
| 100 | } | ||
| 101 | #endif | ||
| 102 | omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg); | ||
| 103 | 70 | ||
| 104 | return 0; | 71 | if (!mux_cfg->cfg_reg) |
| 105 | } | 72 | return -ENODEV; |
| 106 | |||
| 107 | /* Check the mux register in question */ | ||
| 108 | if (cfg->mux_reg) { | ||
| 109 | unsigned tmp1, tmp2; | ||
| 110 | |||
| 111 | spin_lock_irqsave(&mux_spin_lock, flags); | ||
| 112 | reg_orig = omap_readl(cfg->mux_reg); | ||
| 113 | |||
| 114 | /* The mux registers always seem to be 3 bits long */ | ||
| 115 | mask = (0x7 << cfg->mask_offset); | ||
| 116 | tmp1 = reg_orig & mask; | ||
| 117 | reg = reg_orig & ~mask; | ||
| 118 | |||
| 119 | tmp2 = (cfg->mask << cfg->mask_offset); | ||
| 120 | reg |= tmp2; | ||
| 121 | |||
| 122 | if (tmp1 != tmp2) | ||
| 123 | warn = 1; | ||
| 124 | |||
| 125 | omap_writel(reg, cfg->mux_reg); | ||
| 126 | spin_unlock_irqrestore(&mux_spin_lock, flags); | ||
| 127 | } | ||
| 128 | |||
| 129 | /* Check for pull up or pull down selection on 1610 */ | ||
| 130 | if (!cpu_is_omap15xx()) { | ||
| 131 | if (cfg->pu_pd_reg && cfg->pull_val) { | ||
| 132 | spin_lock_irqsave(&mux_spin_lock, flags); | ||
| 133 | pu_pd_orig = omap_readl(cfg->pu_pd_reg); | ||
| 134 | mask = 1 << cfg->pull_bit; | ||
| 135 | |||
| 136 | if (cfg->pu_pd_val) { | ||
| 137 | if (!(pu_pd_orig & mask)) | ||
| 138 | warn = 1; | ||
| 139 | /* Use pull up */ | ||
| 140 | pu_pd = pu_pd_orig | mask; | ||
| 141 | } else { | ||
| 142 | if (pu_pd_orig & mask) | ||
| 143 | warn = 1; | ||
| 144 | /* Use pull down */ | ||
| 145 | pu_pd = pu_pd_orig & ~mask; | ||
| 146 | } | ||
| 147 | omap_writel(pu_pd, cfg->pu_pd_reg); | ||
| 148 | spin_unlock_irqrestore(&mux_spin_lock, flags); | ||
| 149 | } | ||
| 150 | } | ||
| 151 | |||
| 152 | /* Check for an associated pull down register */ | ||
| 153 | if (cfg->pull_reg) { | ||
| 154 | spin_lock_irqsave(&mux_spin_lock, flags); | ||
| 155 | pull_orig = omap_readl(cfg->pull_reg); | ||
| 156 | mask = 1 << cfg->pull_bit; | ||
| 157 | |||
| 158 | if (cfg->pull_val) { | ||
| 159 | if (pull_orig & mask) | ||
| 160 | warn = 1; | ||
| 161 | /* Low bit = pull enabled */ | ||
| 162 | pull = pull_orig & ~mask; | ||
| 163 | } else { | ||
| 164 | if (!(pull_orig & mask)) | ||
| 165 | warn = 1; | ||
| 166 | /* High bit = pull disabled */ | ||
| 167 | pull = pull_orig | mask; | ||
| 168 | } | ||
| 169 | |||
| 170 | omap_writel(pull, cfg->pull_reg); | ||
| 171 | spin_unlock_irqrestore(&mux_spin_lock, flags); | ||
| 172 | } | ||
| 173 | |||
| 174 | if (warn) { | ||
| 175 | #ifdef CONFIG_OMAP_MUX_WARNINGS | ||
| 176 | printk(KERN_WARNING "MUX: initialized %s\n", cfg->name); | ||
| 177 | #endif | ||
| 178 | } | ||
| 179 | |||
| 180 | #ifdef CONFIG_OMAP_MUX_DEBUG | ||
| 181 | if (cfg->debug || warn) { | ||
| 182 | printk("MUX: Setting register %s\n", cfg->name); | ||
| 183 | printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", | ||
| 184 | cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); | ||
| 185 | |||
| 186 | if (!cpu_is_omap15xx()) { | ||
| 187 | if (cfg->pu_pd_reg && cfg->pull_val) { | ||
| 188 | printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", | ||
| 189 | cfg->pu_pd_name, cfg->pu_pd_reg, | ||
| 190 | pu_pd_orig, pu_pd); | ||
| 191 | } | ||
| 192 | } | ||
| 193 | |||
| 194 | if (cfg->pull_reg) | ||
| 195 | printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", | ||
| 196 | cfg->pull_name, cfg->pull_reg, pull_orig, pull); | ||
| 197 | } | ||
| 198 | #endif | ||
| 199 | 73 | ||
| 200 | #ifdef CONFIG_OMAP_MUX_ERRORS | 74 | return mux_cfg->cfg_reg(reg); |
| 201 | return warn ? -ETXTBSY : 0; | ||
| 202 | #else | ||
| 203 | return 0; | ||
| 204 | #endif | ||
| 205 | } | 75 | } |
| 206 | EXPORT_SYMBOL(omap_cfg_reg); | 76 | EXPORT_SYMBOL(omap_cfg_reg); |
| 207 | #else | 77 | #else |
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c index a5aedf964b88..a619475c4b76 100644 --- a/arch/arm/plat-omap/usb.c +++ b/arch/arm/plat-omap/usb.c | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | #include <asm/system.h> | 33 | #include <asm/system.h> |
| 34 | #include <asm/hardware.h> | 34 | #include <asm/hardware.h> |
| 35 | 35 | ||
| 36 | #include <asm/arch/control.h> | ||
| 36 | #include <asm/arch/mux.h> | 37 | #include <asm/arch/mux.h> |
| 37 | #include <asm/arch/usb.h> | 38 | #include <asm/arch/usb.h> |
| 38 | #include <asm/arch/board.h> | 39 | #include <asm/arch/board.h> |
| @@ -76,7 +77,7 @@ | |||
| 76 | 77 | ||
| 77 | /*-------------------------------------------------------------------------*/ | 78 | /*-------------------------------------------------------------------------*/ |
| 78 | 79 | ||
| 79 | #ifdef CONFIG_ARCH_OMAP_OTG | 80 | #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_USB_MUSB_OTG) |
| 80 | 81 | ||
| 81 | static struct otg_transceiver *xceiv; | 82 | static struct otg_transceiver *xceiv; |
| 82 | 83 | ||
| @@ -110,12 +111,48 @@ EXPORT_SYMBOL(otg_set_transceiver); | |||
| 110 | 111 | ||
| 111 | #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX) | 112 | #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX) |
| 112 | 113 | ||
| 114 | static void omap2_usb_devconf_clear(u8 port, u32 mask) | ||
| 115 | { | ||
| 116 | u32 r; | ||
| 117 | |||
| 118 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 119 | r &= ~USBTXWRMODEI(port, mask); | ||
| 120 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
| 121 | } | ||
| 122 | |||
| 123 | static void omap2_usb_devconf_set(u8 port, u32 mask) | ||
| 124 | { | ||
| 125 | u32 r; | ||
| 126 | |||
| 127 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 128 | r |= USBTXWRMODEI(port, mask); | ||
| 129 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
| 130 | } | ||
| 131 | |||
| 132 | static void omap2_usb2_disable_5pinbitll(void) | ||
| 133 | { | ||
| 134 | u32 r; | ||
| 135 | |||
| 136 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 137 | r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI); | ||
| 138 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
| 139 | } | ||
| 140 | |||
| 141 | static void omap2_usb2_enable_5pinunitll(void) | ||
| 142 | { | ||
| 143 | u32 r; | ||
| 144 | |||
| 145 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 146 | r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI; | ||
| 147 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
| 148 | } | ||
| 149 | |||
| 113 | static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) | 150 | static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) |
| 114 | { | 151 | { |
| 115 | u32 syscon1 = 0; | 152 | u32 syscon1 = 0; |
| 116 | 153 | ||
| 117 | if (cpu_is_omap24xx()) | 154 | if (cpu_is_omap24xx()) |
| 118 | CONTROL_DEVCONF_REG &= ~USBT0WRMODEI(USB_BIDIR_TLL); | 155 | omap2_usb_devconf_clear(0, USB_BIDIR_TLL); |
| 119 | 156 | ||
| 120 | if (nwires == 0) { | 157 | if (nwires == 0) { |
| 121 | if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { | 158 | if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { |
| @@ -187,19 +224,19 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) | |||
| 187 | case 3: | 224 | case 3: |
| 188 | syscon1 = 2; | 225 | syscon1 = 2; |
| 189 | if (cpu_is_omap24xx()) | 226 | if (cpu_is_omap24xx()) |
| 190 | CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_BIDIR); | 227 | omap2_usb_devconf_set(0, USB_BIDIR); |
| 191 | break; | 228 | break; |
| 192 | case 4: | 229 | case 4: |
| 193 | syscon1 = 1; | 230 | syscon1 = 1; |
| 194 | if (cpu_is_omap24xx()) | 231 | if (cpu_is_omap24xx()) |
| 195 | CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_BIDIR); | 232 | omap2_usb_devconf_set(0, USB_BIDIR); |
| 196 | break; | 233 | break; |
| 197 | case 6: | 234 | case 6: |
| 198 | syscon1 = 3; | 235 | syscon1 = 3; |
| 199 | if (cpu_is_omap24xx()) { | 236 | if (cpu_is_omap24xx()) { |
| 200 | omap_cfg_reg(J19_24XX_USB0_VP); | 237 | omap_cfg_reg(J19_24XX_USB0_VP); |
| 201 | omap_cfg_reg(K20_24XX_USB0_VM); | 238 | omap_cfg_reg(K20_24XX_USB0_VM); |
| 202 | CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_UNIDIR); | 239 | omap2_usb_devconf_set(0, USB_UNIDIR); |
| 203 | } else { | 240 | } else { |
| 204 | omap_cfg_reg(AA9_USB0_VP); | 241 | omap_cfg_reg(AA9_USB0_VP); |
| 205 | omap_cfg_reg(R9_USB0_VM); | 242 | omap_cfg_reg(R9_USB0_VM); |
| @@ -220,7 +257,7 @@ static u32 __init omap_usb1_init(unsigned nwires) | |||
| 220 | if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) | 257 | if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) |
| 221 | USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R; | 258 | USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R; |
| 222 | if (cpu_is_omap24xx()) | 259 | if (cpu_is_omap24xx()) |
| 223 | CONTROL_DEVCONF_REG &= ~USBT1WRMODEI(USB_BIDIR_TLL); | 260 | omap2_usb_devconf_clear(1, USB_BIDIR_TLL); |
| 224 | 261 | ||
| 225 | if (nwires == 0) | 262 | if (nwires == 0) |
| 226 | return 0; | 263 | return 0; |
| @@ -261,17 +298,17 @@ static u32 __init omap_usb1_init(unsigned nwires) | |||
| 261 | * this TLL link is not using DP/DM | 298 | * this TLL link is not using DP/DM |
| 262 | */ | 299 | */ |
| 263 | syscon1 = 1; | 300 | syscon1 = 1; |
| 264 | CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR_TLL); | 301 | omap2_usb_devconf_set(1, USB_BIDIR_TLL); |
| 265 | break; | 302 | break; |
| 266 | case 3: | 303 | case 3: |
| 267 | syscon1 = 2; | 304 | syscon1 = 2; |
| 268 | if (cpu_is_omap24xx()) | 305 | if (cpu_is_omap24xx()) |
| 269 | CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR); | 306 | omap2_usb_devconf_set(1, USB_BIDIR); |
| 270 | break; | 307 | break; |
| 271 | case 4: | 308 | case 4: |
| 272 | syscon1 = 1; | 309 | syscon1 = 1; |
| 273 | if (cpu_is_omap24xx()) | 310 | if (cpu_is_omap24xx()) |
| 274 | CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR); | 311 | omap2_usb_devconf_set(1, USB_BIDIR); |
| 275 | break; | 312 | break; |
| 276 | case 6: | 313 | case 6: |
| 277 | if (cpu_is_omap24xx()) | 314 | if (cpu_is_omap24xx()) |
| @@ -295,8 +332,7 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup) | |||
| 295 | u32 syscon1 = 0; | 332 | u32 syscon1 = 0; |
| 296 | 333 | ||
| 297 | if (cpu_is_omap24xx()) { | 334 | if (cpu_is_omap24xx()) { |
| 298 | CONTROL_DEVCONF_REG &= ~(USBT2WRMODEI(USB_BIDIR_TLL) | 335 | omap2_usb2_disable_5pinbitll(); |
| 299 | | USBT2TLL5PI); | ||
| 300 | alt_pingroup = 0; | 336 | alt_pingroup = 0; |
| 301 | } | 337 | } |
| 302 | 338 | ||
| @@ -343,17 +379,17 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup) | |||
| 343 | * this TLL link is not using DP/DM | 379 | * this TLL link is not using DP/DM |
| 344 | */ | 380 | */ |
| 345 | syscon1 = 1; | 381 | syscon1 = 1; |
| 346 | CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR_TLL); | 382 | omap2_usb_devconf_set(2, USB_BIDIR_TLL); |
| 347 | break; | 383 | break; |
| 348 | case 3: | 384 | case 3: |
| 349 | syscon1 = 2; | 385 | syscon1 = 2; |
| 350 | if (cpu_is_omap24xx()) | 386 | if (cpu_is_omap24xx()) |
| 351 | CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR); | 387 | omap2_usb_devconf_set(2, USB_BIDIR); |
| 352 | break; | 388 | break; |
| 353 | case 4: | 389 | case 4: |
| 354 | syscon1 = 1; | 390 | syscon1 = 1; |
| 355 | if (cpu_is_omap24xx()) | 391 | if (cpu_is_omap24xx()) |
| 356 | CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR); | 392 | omap2_usb_devconf_set(2, USB_BIDIR); |
| 357 | break; | 393 | break; |
| 358 | case 5: | 394 | case 5: |
| 359 | if (!cpu_is_omap24xx()) | 395 | if (!cpu_is_omap24xx()) |
| @@ -364,8 +400,7 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup) | |||
| 364 | * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED} | 400 | * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED} |
| 365 | */ | 401 | */ |
| 366 | syscon1 = 3; | 402 | syscon1 = 3; |
| 367 | CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_UNIDIR_TLL) | 403 | omap2_usb2_enable_5pinunitll(); |
| 368 | | USBT2TLL5PI; | ||
| 369 | break; | 404 | break; |
| 370 | case 6: | 405 | case 6: |
| 371 | if (cpu_is_omap24xx()) | 406 | if (cpu_is_omap24xx()) |
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile new file mode 100644 index 000000000000..198f3dde2be3 --- /dev/null +++ b/arch/arm/plat-orion/Makefile | |||
| @@ -0,0 +1,8 @@ | |||
| 1 | # | ||
| 2 | # Makefile for the linux kernel. | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-y := irq.o pcie.o time.o | ||
| 6 | obj-m := | ||
| 7 | obj-n := | ||
| 8 | obj- := | ||
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c new file mode 100644 index 000000000000..c5b669d234bc --- /dev/null +++ b/arch/arm/plat-orion/irq.c | |||
| @@ -0,0 +1,64 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-orion/irq.c | ||
| 3 | * | ||
| 4 | * Marvell Orion SoC IRQ handling. | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/irq.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | #include <asm/plat-orion/irq.h> | ||
| 16 | |||
| 17 | static void orion_irq_mask(u32 irq) | ||
| 18 | { | ||
| 19 | void __iomem *maskaddr = get_irq_chip_data(irq); | ||
| 20 | u32 mask; | ||
| 21 | |||
| 22 | mask = readl(maskaddr); | ||
| 23 | mask &= ~(1 << (irq & 31)); | ||
| 24 | writel(mask, maskaddr); | ||
| 25 | } | ||
| 26 | |||
| 27 | static void orion_irq_unmask(u32 irq) | ||
| 28 | { | ||
| 29 | void __iomem *maskaddr = get_irq_chip_data(irq); | ||
| 30 | u32 mask; | ||
| 31 | |||
| 32 | mask = readl(maskaddr); | ||
| 33 | mask |= 1 << (irq & 31); | ||
| 34 | writel(mask, maskaddr); | ||
| 35 | } | ||
| 36 | |||
| 37 | static struct irq_chip orion_irq_chip = { | ||
| 38 | .name = "orion_irq", | ||
| 39 | .ack = orion_irq_mask, | ||
| 40 | .mask = orion_irq_mask, | ||
| 41 | .unmask = orion_irq_unmask, | ||
| 42 | }; | ||
| 43 | |||
| 44 | void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) | ||
| 45 | { | ||
| 46 | unsigned int i; | ||
| 47 | |||
| 48 | /* | ||
| 49 | * Mask all interrupts initially. | ||
| 50 | */ | ||
| 51 | writel(0, maskaddr); | ||
| 52 | |||
| 53 | /* | ||
| 54 | * Register IRQ sources. | ||
| 55 | */ | ||
| 56 | for (i = 0; i < 32; i++) { | ||
| 57 | unsigned int irq = irq_start + i; | ||
| 58 | |||
| 59 | set_irq_chip(irq, &orion_irq_chip); | ||
| 60 | set_irq_chip_data(irq, maskaddr); | ||
| 61 | set_irq_handler(irq, handle_level_irq); | ||
| 62 | set_irq_flags(irq, IRQF_VALID); | ||
| 63 | } | ||
| 64 | } | ||
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c new file mode 100644 index 000000000000..abfda53f1800 --- /dev/null +++ b/arch/arm/plat-orion/pcie.c | |||
| @@ -0,0 +1,245 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-orion/pcie.c | ||
| 3 | * | ||
| 4 | * Marvell Orion SoC PCIe handling. | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/pci.h> | ||
| 13 | #include <linux/mbus.h> | ||
| 14 | #include <asm/mach/pci.h> | ||
| 15 | #include <asm/plat-orion/pcie.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * PCIe unit register offsets. | ||
| 19 | */ | ||
| 20 | #define PCIE_DEV_ID_OFF 0x0000 | ||
| 21 | #define PCIE_CMD_OFF 0x0004 | ||
| 22 | #define PCIE_DEV_REV_OFF 0x0008 | ||
| 23 | #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) | ||
| 24 | #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) | ||
| 25 | #define PCIE_HEADER_LOG_4_OFF 0x0128 | ||
| 26 | #define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4)) | ||
| 27 | #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) | ||
| 28 | #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) | ||
| 29 | #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) | ||
| 30 | #define PCIE_WIN5_CTRL_OFF 0x1880 | ||
| 31 | #define PCIE_WIN5_BASE_OFF 0x1884 | ||
| 32 | #define PCIE_WIN5_REMAP_OFF 0x188c | ||
| 33 | #define PCIE_CONF_ADDR_OFF 0x18f8 | ||
| 34 | #define PCIE_CONF_ADDR_EN 0x80000000 | ||
| 35 | #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) | ||
| 36 | #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) | ||
| 37 | #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) | ||
| 38 | #define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8) | ||
| 39 | #define PCIE_CONF_DATA_OFF 0x18fc | ||
| 40 | #define PCIE_MASK_OFF 0x1910 | ||
| 41 | #define PCIE_CTRL_OFF 0x1a00 | ||
| 42 | #define PCIE_STAT_OFF 0x1a04 | ||
| 43 | #define PCIE_STAT_DEV_OFFS 20 | ||
| 44 | #define PCIE_STAT_DEV_MASK 0x1f | ||
| 45 | #define PCIE_STAT_BUS_OFFS 8 | ||
| 46 | #define PCIE_STAT_BUS_MASK 0xff | ||
| 47 | #define PCIE_STAT_LINK_DOWN 1 | ||
| 48 | |||
| 49 | |||
| 50 | u32 __init orion_pcie_dev_id(void __iomem *base) | ||
| 51 | { | ||
| 52 | return readl(base + PCIE_DEV_ID_OFF) >> 16; | ||
| 53 | } | ||
| 54 | |||
| 55 | u32 __init orion_pcie_rev(void __iomem *base) | ||
| 56 | { | ||
| 57 | return readl(base + PCIE_DEV_REV_OFF) & 0xff; | ||
| 58 | } | ||
| 59 | |||
| 60 | int orion_pcie_link_up(void __iomem *base) | ||
| 61 | { | ||
| 62 | return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); | ||
| 63 | } | ||
| 64 | |||
| 65 | int orion_pcie_get_local_bus_nr(void __iomem *base) | ||
| 66 | { | ||
| 67 | u32 stat = readl(base + PCIE_STAT_OFF); | ||
| 68 | |||
| 69 | return (stat >> PCIE_STAT_BUS_OFFS) & PCIE_STAT_BUS_MASK; | ||
| 70 | } | ||
| 71 | |||
| 72 | void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr) | ||
| 73 | { | ||
| 74 | u32 stat; | ||
| 75 | |||
| 76 | stat = readl(base + PCIE_STAT_OFF); | ||
| 77 | stat &= ~(PCIE_STAT_BUS_MASK << PCIE_STAT_BUS_OFFS); | ||
| 78 | stat |= nr << PCIE_STAT_BUS_OFFS; | ||
| 79 | writel(stat, base + PCIE_STAT_OFF); | ||
| 80 | } | ||
| 81 | |||
| 82 | /* | ||
| 83 | * Setup PCIE BARs and Address Decode Wins: | ||
| 84 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks | ||
| 85 | * WIN[0-3] -> DRAM bank[0-3] | ||
| 86 | */ | ||
| 87 | static void __init orion_pcie_setup_wins(void __iomem *base, | ||
| 88 | struct mbus_dram_target_info *dram) | ||
| 89 | { | ||
| 90 | u32 size; | ||
| 91 | int i; | ||
| 92 | |||
| 93 | /* | ||
| 94 | * First, disable and clear BARs and windows. | ||
| 95 | */ | ||
| 96 | for (i = 1; i <= 2; i++) { | ||
| 97 | writel(0, base + PCIE_BAR_CTRL_OFF(i)); | ||
| 98 | writel(0, base + PCIE_BAR_LO_OFF(i)); | ||
| 99 | writel(0, base + PCIE_BAR_HI_OFF(i)); | ||
| 100 | } | ||
| 101 | |||
| 102 | for (i = 0; i < 5; i++) { | ||
| 103 | writel(0, base + PCIE_WIN04_CTRL_OFF(i)); | ||
| 104 | writel(0, base + PCIE_WIN04_BASE_OFF(i)); | ||
| 105 | writel(0, base + PCIE_WIN04_REMAP_OFF(i)); | ||
| 106 | } | ||
| 107 | |||
| 108 | writel(0, base + PCIE_WIN5_CTRL_OFF); | ||
| 109 | writel(0, base + PCIE_WIN5_BASE_OFF); | ||
| 110 | writel(0, base + PCIE_WIN5_REMAP_OFF); | ||
| 111 | |||
| 112 | /* | ||
| 113 | * Setup windows for DDR banks. Count total DDR size on the fly. | ||
| 114 | */ | ||
| 115 | size = 0; | ||
| 116 | for (i = 0; i < dram->num_cs; i++) { | ||
| 117 | struct mbus_dram_window *cs = dram->cs + i; | ||
| 118 | |||
| 119 | writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); | ||
| 120 | writel(0, base + PCIE_WIN04_REMAP_OFF(i)); | ||
| 121 | writel(((cs->size - 1) & 0xffff0000) | | ||
| 122 | (cs->mbus_attr << 8) | | ||
| 123 | (dram->mbus_dram_target_id << 4) | 1, | ||
| 124 | base + PCIE_WIN04_CTRL_OFF(i)); | ||
| 125 | |||
| 126 | size += cs->size; | ||
| 127 | } | ||
| 128 | |||
| 129 | /* | ||
| 130 | * Setup BAR[1] to all DRAM banks. | ||
| 131 | */ | ||
| 132 | writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1)); | ||
| 133 | writel(0, base + PCIE_BAR_HI_OFF(1)); | ||
| 134 | writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1)); | ||
| 135 | } | ||
| 136 | |||
| 137 | void __init orion_pcie_setup(void __iomem *base, | ||
| 138 | struct mbus_dram_target_info *dram) | ||
| 139 | { | ||
| 140 | u16 cmd; | ||
| 141 | u32 mask; | ||
| 142 | |||
| 143 | /* | ||
| 144 | * Point PCIe unit MBUS decode windows to DRAM space. | ||
| 145 | */ | ||
| 146 | orion_pcie_setup_wins(base, dram); | ||
| 147 | |||
| 148 | /* | ||
| 149 | * Master + slave enable. | ||
| 150 | */ | ||
| 151 | cmd = readw(base + PCIE_CMD_OFF); | ||
| 152 | cmd |= PCI_COMMAND_IO; | ||
| 153 | cmd |= PCI_COMMAND_MEMORY; | ||
| 154 | cmd |= PCI_COMMAND_MASTER; | ||
| 155 | writew(cmd, base + PCIE_CMD_OFF); | ||
| 156 | |||
| 157 | /* | ||
| 158 | * Enable interrupt lines A-D. | ||
| 159 | */ | ||
| 160 | mask = readl(base + PCIE_MASK_OFF); | ||
| 161 | mask |= 0x0f000000; | ||
| 162 | writel(mask, base + PCIE_MASK_OFF); | ||
| 163 | } | ||
| 164 | |||
| 165 | int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, | ||
| 166 | u32 devfn, int where, int size, u32 *val) | ||
| 167 | { | ||
| 168 | writel(PCIE_CONF_BUS(bus->number) | | ||
| 169 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | ||
| 170 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | ||
| 171 | PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, | ||
| 172 | base + PCIE_CONF_ADDR_OFF); | ||
| 173 | |||
| 174 | *val = readl(base + PCIE_CONF_DATA_OFF); | ||
| 175 | |||
| 176 | if (size == 1) | ||
| 177 | *val = (*val >> (8 * (where & 3))) & 0xff; | ||
| 178 | else if (size == 2) | ||
| 179 | *val = (*val >> (8 * (where & 3))) & 0xffff; | ||
| 180 | |||
| 181 | return PCIBIOS_SUCCESSFUL; | ||
| 182 | } | ||
| 183 | |||
| 184 | int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, | ||
| 185 | u32 devfn, int where, int size, u32 *val) | ||
| 186 | { | ||
| 187 | writel(PCIE_CONF_BUS(bus->number) | | ||
| 188 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | ||
| 189 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | ||
| 190 | PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, | ||
| 191 | base + PCIE_CONF_ADDR_OFF); | ||
| 192 | |||
| 193 | *val = readl(base + PCIE_CONF_DATA_OFF); | ||
| 194 | |||
| 195 | if (bus->number != orion_pcie_get_local_bus_nr(base) || | ||
| 196 | PCI_FUNC(devfn) != 0) | ||
| 197 | *val = readl(base + PCIE_HEADER_LOG_4_OFF); | ||
| 198 | |||
| 199 | if (size == 1) | ||
| 200 | *val = (*val >> (8 * (where & 3))) & 0xff; | ||
| 201 | else if (size == 2) | ||
| 202 | *val = (*val >> (8 * (where & 3))) & 0xffff; | ||
| 203 | |||
| 204 | return PCIBIOS_SUCCESSFUL; | ||
| 205 | } | ||
| 206 | |||
| 207 | int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus, | ||
| 208 | u32 devfn, int where, int size, u32 *val) | ||
| 209 | { | ||
| 210 | *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) | | ||
| 211 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | ||
| 212 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | ||
| 213 | PCIE_CONF_REG(where))); | ||
| 214 | |||
| 215 | if (size == 1) | ||
| 216 | *val = (*val >> (8 * (where & 3))) & 0xff; | ||
| 217 | else if (size == 2) | ||
| 218 | *val = (*val >> (8 * (where & 3))) & 0xffff; | ||
| 219 | |||
| 220 | return PCIBIOS_SUCCESSFUL; | ||
| 221 | } | ||
| 222 | |||
| 223 | int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus, | ||
| 224 | u32 devfn, int where, int size, u32 val) | ||
| 225 | { | ||
| 226 | int ret = PCIBIOS_SUCCESSFUL; | ||
| 227 | |||
| 228 | writel(PCIE_CONF_BUS(bus->number) | | ||
| 229 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | ||
| 230 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | ||
| 231 | PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, | ||
| 232 | base + PCIE_CONF_ADDR_OFF); | ||
| 233 | |||
| 234 | if (size == 4) { | ||
| 235 | writel(val, base + PCIE_CONF_DATA_OFF); | ||
| 236 | } else if (size == 2) { | ||
| 237 | writew(val, base + PCIE_CONF_DATA_OFF + (where & 3)); | ||
| 238 | } else if (size == 1) { | ||
| 239 | writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3)); | ||
| 240 | } else { | ||
| 241 | ret = PCIBIOS_BAD_REGISTER_NUMBER; | ||
| 242 | } | ||
| 243 | |||
| 244 | return ret; | ||
| 245 | } | ||
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c new file mode 100644 index 000000000000..28b5285446e8 --- /dev/null +++ b/arch/arm/plat-orion/time.c | |||
| @@ -0,0 +1,203 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-orion/time.c | ||
| 3 | * | ||
| 4 | * Marvell Orion SoC timer handling. | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | * | ||
| 10 | * Timer 0 is used as free-running clocksource, while timer 1 is | ||
| 11 | * used as clock_event_device. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/clockchips.h> | ||
| 16 | #include <linux/interrupt.h> | ||
| 17 | #include <linux/irq.h> | ||
| 18 | #include <asm/mach/time.h> | ||
| 19 | #include <asm/arch/hardware.h> | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Number of timer ticks per jiffy. | ||
| 23 | */ | ||
| 24 | static u32 ticks_per_jiffy; | ||
| 25 | |||
| 26 | |||
| 27 | /* | ||
| 28 | * Timer block registers. | ||
| 29 | */ | ||
| 30 | #define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000) | ||
| 31 | #define TIMER0_EN 0x0001 | ||
| 32 | #define TIMER0_RELOAD_EN 0x0002 | ||
| 33 | #define TIMER1_EN 0x0004 | ||
| 34 | #define TIMER1_RELOAD_EN 0x0008 | ||
| 35 | #define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010) | ||
| 36 | #define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014) | ||
| 37 | #define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018) | ||
| 38 | #define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c) | ||
| 39 | |||
| 40 | |||
| 41 | /* | ||
| 42 | * Clocksource handling. | ||
| 43 | */ | ||
| 44 | static cycle_t orion_clksrc_read(void) | ||
| 45 | { | ||
| 46 | return 0xffffffff - readl(TIMER0_VAL); | ||
| 47 | } | ||
| 48 | |||
| 49 | static struct clocksource orion_clksrc = { | ||
| 50 | .name = "orion_clocksource", | ||
| 51 | .shift = 20, | ||
| 52 | .rating = 300, | ||
| 53 | .read = orion_clksrc_read, | ||
| 54 | .mask = CLOCKSOURCE_MASK(32), | ||
| 55 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
| 56 | }; | ||
| 57 | |||
| 58 | |||
| 59 | |||
| 60 | /* | ||
| 61 | * Clockevent handling. | ||
| 62 | */ | ||
| 63 | static int | ||
| 64 | orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) | ||
| 65 | { | ||
| 66 | unsigned long flags; | ||
| 67 | u32 u; | ||
| 68 | |||
| 69 | if (delta == 0) | ||
| 70 | return -ETIME; | ||
| 71 | |||
| 72 | local_irq_save(flags); | ||
| 73 | |||
| 74 | /* | ||
| 75 | * Clear and enable clockevent timer interrupt. | ||
| 76 | */ | ||
| 77 | writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); | ||
| 78 | |||
| 79 | u = readl(BRIDGE_MASK); | ||
| 80 | u |= BRIDGE_INT_TIMER1; | ||
| 81 | writel(u, BRIDGE_MASK); | ||
| 82 | |||
| 83 | /* | ||
| 84 | * Setup new clockevent timer value. | ||
| 85 | */ | ||
| 86 | writel(delta, TIMER1_VAL); | ||
| 87 | |||
| 88 | /* | ||
| 89 | * Enable the timer. | ||
| 90 | */ | ||
| 91 | u = readl(TIMER_CTRL); | ||
| 92 | u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN; | ||
| 93 | writel(u, TIMER_CTRL); | ||
| 94 | |||
| 95 | local_irq_restore(flags); | ||
| 96 | |||
| 97 | return 0; | ||
| 98 | } | ||
| 99 | |||
| 100 | static void | ||
| 101 | orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) | ||
| 102 | { | ||
| 103 | unsigned long flags; | ||
| 104 | u32 u; | ||
| 105 | |||
| 106 | local_irq_save(flags); | ||
| 107 | if (mode == CLOCK_EVT_MODE_PERIODIC) { | ||
| 108 | /* | ||
| 109 | * Setup timer to fire at 1/HZ intervals. | ||
| 110 | */ | ||
| 111 | writel(ticks_per_jiffy - 1, TIMER1_RELOAD); | ||
| 112 | writel(ticks_per_jiffy - 1, TIMER1_VAL); | ||
| 113 | |||
| 114 | /* | ||
| 115 | * Enable timer interrupt. | ||
| 116 | */ | ||
| 117 | u = readl(BRIDGE_MASK); | ||
| 118 | writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK); | ||
| 119 | |||
| 120 | /* | ||
| 121 | * Enable timer. | ||
| 122 | */ | ||
| 123 | u = readl(TIMER_CTRL); | ||
| 124 | writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL); | ||
| 125 | } else { | ||
| 126 | /* | ||
| 127 | * Disable timer. | ||
| 128 | */ | ||
| 129 | u = readl(TIMER_CTRL); | ||
| 130 | writel(u & ~TIMER1_EN, TIMER_CTRL); | ||
| 131 | |||
| 132 | /* | ||
| 133 | * Disable timer interrupt. | ||
| 134 | */ | ||
| 135 | u = readl(BRIDGE_MASK); | ||
| 136 | writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK); | ||
| 137 | |||
| 138 | /* | ||
| 139 | * ACK pending timer interrupt. | ||
| 140 | */ | ||
| 141 | writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); | ||
| 142 | |||
| 143 | } | ||
| 144 | local_irq_restore(flags); | ||
| 145 | } | ||
| 146 | |||
| 147 | static struct clock_event_device orion_clkevt = { | ||
| 148 | .name = "orion_tick", | ||
| 149 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, | ||
| 150 | .shift = 32, | ||
| 151 | .rating = 300, | ||
| 152 | .cpumask = CPU_MASK_CPU0, | ||
| 153 | .set_next_event = orion_clkevt_next_event, | ||
| 154 | .set_mode = orion_clkevt_mode, | ||
| 155 | }; | ||
| 156 | |||
| 157 | static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) | ||
| 158 | { | ||
| 159 | /* | ||
| 160 | * ACK timer interrupt and call event handler. | ||
| 161 | */ | ||
| 162 | writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); | ||
| 163 | orion_clkevt.event_handler(&orion_clkevt); | ||
| 164 | |||
| 165 | return IRQ_HANDLED; | ||
| 166 | } | ||
| 167 | |||
| 168 | static struct irqaction orion_timer_irq = { | ||
| 169 | .name = "orion_tick", | ||
| 170 | .flags = IRQF_DISABLED | IRQF_TIMER, | ||
| 171 | .handler = orion_timer_interrupt | ||
| 172 | }; | ||
| 173 | |||
| 174 | void __init orion_time_init(unsigned int irq, unsigned int tclk) | ||
| 175 | { | ||
| 176 | u32 u; | ||
| 177 | |||
| 178 | ticks_per_jiffy = (tclk + HZ/2) / HZ; | ||
| 179 | |||
| 180 | |||
| 181 | /* | ||
| 182 | * Setup free-running clocksource timer (interrupts | ||
| 183 | * disabled.) | ||
| 184 | */ | ||
| 185 | writel(0xffffffff, TIMER0_VAL); | ||
| 186 | writel(0xffffffff, TIMER0_RELOAD); | ||
| 187 | u = readl(BRIDGE_MASK); | ||
| 188 | writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK); | ||
| 189 | u = readl(TIMER_CTRL); | ||
| 190 | writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL); | ||
| 191 | orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift); | ||
| 192 | clocksource_register(&orion_clksrc); | ||
| 193 | |||
| 194 | |||
| 195 | /* | ||
| 196 | * Setup clockevent timer (interrupt-driven.) | ||
| 197 | */ | ||
| 198 | setup_irq(irq, &orion_timer_irq); | ||
| 199 | orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift); | ||
| 200 | orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt); | ||
| 201 | orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt); | ||
| 202 | clockevents_register_device(&orion_clkevt); | ||
| 203 | } | ||
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c index 99a44746f8f2..d84167fb33b1 100644 --- a/arch/arm/plat-s3c24xx/clock.c +++ b/arch/arm/plat-s3c24xx/clock.c | |||
| @@ -332,6 +332,58 @@ static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent) | |||
| 332 | return 0; | 332 | return 0; |
| 333 | } | 333 | } |
| 334 | 334 | ||
| 335 | static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate) | ||
| 336 | { | ||
| 337 | unsigned long div; | ||
| 338 | |||
| 339 | if ((rate == 0) || !clk->parent) | ||
| 340 | return 0; | ||
| 341 | |||
| 342 | div = clk_get_rate(clk->parent) / rate; | ||
| 343 | if (div < 2) | ||
| 344 | div = 2; | ||
| 345 | else if (div > 16) | ||
| 346 | div = 16; | ||
| 347 | |||
| 348 | return div; | ||
| 349 | } | ||
| 350 | |||
| 351 | static unsigned long s3c24xx_round_dclk_rate(struct clk *clk, | ||
| 352 | unsigned long rate) | ||
| 353 | { | ||
| 354 | unsigned long div = s3c24xx_calc_div(clk, rate); | ||
| 355 | |||
| 356 | if (div == 0) | ||
| 357 | return 0; | ||
| 358 | |||
| 359 | return clk_get_rate(clk->parent) / div; | ||
| 360 | } | ||
| 361 | |||
| 362 | static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate) | ||
| 363 | { | ||
| 364 | unsigned long mask, data, div = s3c24xx_calc_div(clk, rate); | ||
| 365 | |||
| 366 | if (div == 0) | ||
| 367 | return -EINVAL; | ||
| 368 | |||
| 369 | if (clk == &s3c24xx_dclk0) { | ||
| 370 | mask = S3C2410_DCLKCON_DCLK0_DIV_MASK | | ||
| 371 | S3C2410_DCLKCON_DCLK0_CMP_MASK; | ||
| 372 | data = S3C2410_DCLKCON_DCLK0_DIV(div) | | ||
| 373 | S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2); | ||
| 374 | } else if (clk == &s3c24xx_dclk1) { | ||
| 375 | mask = S3C2410_DCLKCON_DCLK1_DIV_MASK | | ||
| 376 | S3C2410_DCLKCON_DCLK1_CMP_MASK; | ||
| 377 | data = S3C2410_DCLKCON_DCLK1_DIV(div) | | ||
| 378 | S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2); | ||
| 379 | } else | ||
| 380 | return -EINVAL; | ||
| 381 | |||
| 382 | clk->rate = clk_get_rate(clk->parent) / div; | ||
| 383 | __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data), | ||
| 384 | S3C24XX_DCLKCON); | ||
| 385 | return clk->rate; | ||
| 386 | } | ||
| 335 | 387 | ||
| 336 | static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) | 388 | static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) |
| 337 | { | 389 | { |
| @@ -378,6 +430,8 @@ struct clk s3c24xx_dclk0 = { | |||
| 378 | .ctrlbit = S3C2410_DCLKCON_DCLK0EN, | 430 | .ctrlbit = S3C2410_DCLKCON_DCLK0EN, |
| 379 | .enable = s3c24xx_dclk_enable, | 431 | .enable = s3c24xx_dclk_enable, |
| 380 | .set_parent = s3c24xx_dclk_setparent, | 432 | .set_parent = s3c24xx_dclk_setparent, |
| 433 | .set_rate = s3c24xx_set_dclk_rate, | ||
| 434 | .round_rate = s3c24xx_round_dclk_rate, | ||
| 381 | }; | 435 | }; |
| 382 | 436 | ||
| 383 | struct clk s3c24xx_dclk1 = { | 437 | struct clk s3c24xx_dclk1 = { |
| @@ -386,6 +440,8 @@ struct clk s3c24xx_dclk1 = { | |||
| 386 | .ctrlbit = S3C2410_DCLKCON_DCLK0EN, | 440 | .ctrlbit = S3C2410_DCLKCON_DCLK0EN, |
| 387 | .enable = s3c24xx_dclk_enable, | 441 | .enable = s3c24xx_dclk_enable, |
| 388 | .set_parent = s3c24xx_dclk_setparent, | 442 | .set_parent = s3c24xx_dclk_setparent, |
| 443 | .set_rate = s3c24xx_set_dclk_rate, | ||
| 444 | .round_rate = s3c24xx_round_dclk_rate, | ||
| 389 | }; | 445 | }; |
| 390 | 446 | ||
| 391 | struct clk s3c24xx_clkout0 = { | 447 | struct clk s3c24xx_clkout0 = { |
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index f513ab083b8f..f5699cadb0c3 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c | |||
| @@ -28,15 +28,19 @@ | |||
| 28 | #include <linux/ioport.h> | 28 | #include <linux/ioport.h> |
| 29 | #include <linux/serial_core.h> | 29 | #include <linux/serial_core.h> |
| 30 | #include <linux/platform_device.h> | 30 | #include <linux/platform_device.h> |
| 31 | #include <linux/delay.h> | ||
| 31 | 32 | ||
| 32 | #include <asm/hardware.h> | 33 | #include <asm/hardware.h> |
| 33 | #include <asm/irq.h> | 34 | #include <asm/irq.h> |
| 34 | #include <asm/io.h> | 35 | #include <asm/io.h> |
| 35 | #include <asm/delay.h> | 36 | #include <asm/delay.h> |
| 37 | #include <asm/cacheflush.h> | ||
| 36 | 38 | ||
| 37 | #include <asm/mach/arch.h> | 39 | #include <asm/mach/arch.h> |
| 38 | #include <asm/mach/map.h> | 40 | #include <asm/mach/map.h> |
| 39 | 41 | ||
| 42 | #include <asm/arch/system-reset.h> | ||
| 43 | |||
| 40 | #include <asm/arch/regs-gpio.h> | 44 | #include <asm/arch/regs-gpio.h> |
| 41 | #include <asm/plat-s3c/regs-serial.h> | 45 | #include <asm/plat-s3c/regs-serial.h> |
| 42 | 46 | ||
| @@ -203,6 +207,27 @@ static unsigned long s3c24xx_read_idcode_v4(void) | |||
| 203 | #endif | 207 | #endif |
| 204 | } | 208 | } |
| 205 | 209 | ||
| 210 | /* Hook for arm_pm_restart to ensure we execute the reset code | ||
| 211 | * with the caches enabled. It seems at least the S3C2440 has a problem | ||
| 212 | * resetting if there is bus activity interrupted by the reset. | ||
| 213 | */ | ||
| 214 | static void s3c24xx_pm_restart(char mode) | ||
| 215 | { | ||
| 216 | if (mode != 's') { | ||
| 217 | unsigned long flags; | ||
| 218 | |||
| 219 | local_irq_save(flags); | ||
| 220 | __cpuc_flush_kern_all(); | ||
| 221 | __cpuc_flush_user_all(); | ||
| 222 | |||
| 223 | arch_reset(mode); | ||
| 224 | local_irq_restore(flags); | ||
| 225 | } | ||
| 226 | |||
| 227 | /* fallback, or unhandled */ | ||
| 228 | arm_machine_restart(mode); | ||
| 229 | } | ||
| 230 | |||
| 206 | void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) | 231 | void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) |
| 207 | { | 232 | { |
| 208 | unsigned long idcode = 0x0; | 233 | unsigned long idcode = 0x0; |
| @@ -230,6 +255,8 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) | |||
| 230 | panic("Unsupported S3C24XX CPU"); | 255 | panic("Unsupported S3C24XX CPU"); |
| 231 | } | 256 | } |
| 232 | 257 | ||
| 258 | arm_pm_restart = s3c24xx_pm_restart; | ||
| 259 | |||
| 233 | (cpu->map_io)(mach_desc, size); | 260 | (cpu->map_io)(mach_desc, size); |
| 234 | } | 261 | } |
| 235 | 262 | ||