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-rw-r--r--arch/arm/Kconfig36
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/compressed/Makefile4
-rw-r--r--arch/arm/boot/compressed/head-clps7500.S86
-rw-r--r--arch/arm/boot/compressed/head.S14
-rw-r--r--arch/arm/boot/compressed/misc.c2
-rw-r--r--arch/arm/include/asm/cacheflush.h37
-rw-r--r--arch/arm/include/asm/dma.h24
-rw-r--r--arch/arm/include/asm/hardware/iomd.h41
-rw-r--r--arch/arm/include/asm/hwcap.h1
-rw-r--r--arch/arm/include/asm/io.h8
-rw-r--r--arch/arm/include/asm/irq.h4
-rw-r--r--arch/arm/include/asm/memory.h7
-rw-r--r--arch/arm/include/asm/mmu_context.h1
-rw-r--r--arch/arm/include/asm/page.h32
-rw-r--r--arch/arm/include/asm/processor.h2
-rw-r--r--arch/arm/include/asm/setup.h6
-rw-r--r--arch/arm/include/asm/string.h9
-rw-r--r--arch/arm/include/asm/system.h2
-rw-r--r--arch/arm/include/asm/uaccess.h5
-rw-r--r--arch/arm/kernel/armksyms.c1
-rw-r--r--arch/arm/kernel/setup.c39
-rw-r--r--arch/arm/kernel/thumbee.c2
-rw-r--r--arch/arm/lib/Makefile1
-rw-r--r--arch/arm/lib/memset.S2
-rw-r--r--arch/arm/mach-aaec2000/include/mach/dma.h9
-rw-r--r--arch/arm/mach-aaec2000/include/mach/io.h6
-rw-r--r--arch/arm/mach-aaec2000/include/mach/memory.h3
-rw-r--r--arch/arm/mach-at91/Kconfig7
-rw-r--r--arch/arm/mach-at91/include/mach/dma.h19
-rw-r--r--arch/arm/mach-at91/include/mach/io.h4
-rw-r--r--arch/arm/mach-at91/include/mach/memory.h11
-rw-r--r--arch/arm/mach-clps711x/include/mach/dma.h19
-rw-r--r--arch/arm/mach-clps711x/include/mach/io.h6
-rw-r--r--arch/arm/mach-clps711x/include/mach/memory.h20
-rw-r--r--arch/arm/mach-clps7500/Makefile11
-rw-r--r--arch/arm/mach-clps7500/Makefile.boot2
-rw-r--r--arch/arm/mach-clps7500/core.c395
-rw-r--r--arch/arm/mach-clps7500/include/mach/acornfb.h33
-rw-r--r--arch/arm/mach-clps7500/include/mach/debug-macro.S21
-rw-r--r--arch/arm/mach-clps7500/include/mach/dma.h21
-rw-r--r--arch/arm/mach-clps7500/include/mach/entry-macro.S16
-rw-r--r--arch/arm/mach-clps7500/include/mach/hardware.h67
-rw-r--r--arch/arm/mach-clps7500/include/mach/io.h255
-rw-r--r--arch/arm/mach-clps7500/include/mach/irq.h32
-rw-r--r--arch/arm/mach-clps7500/include/mach/irqs.h66
-rw-r--r--arch/arm/mach-clps7500/include/mach/memory.h43
-rw-r--r--arch/arm/mach-clps7500/include/mach/system.h23
-rw-r--r--arch/arm/mach-clps7500/include/mach/timex.h13
-rw-r--r--arch/arm/mach-clps7500/include/mach/uncompress.h35
-rw-r--r--arch/arm/mach-clps7500/include/mach/vmalloc.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/dma.h16
-rw-r--r--arch/arm/mach-davinci/include/mach/io.h3
-rw-r--r--arch/arm/mach-davinci/include/mach/memory.h7
-rw-r--r--arch/arm/mach-davinci/include/mach/vmalloc.h1
-rw-r--r--arch/arm/mach-ebsa110/include/mach/dma.h11
-rw-r--r--arch/arm/mach-ebsa110/include/mach/memory.h7
-rw-r--r--arch/arm/mach-ep93xx/include/mach/dma.h3
-rw-r--r--arch/arm/mach-ep93xx/include/mach/io.h4
-rw-r--r--arch/arm/mach-ep93xx/include/mach/memory.h4
-rw-r--r--arch/arm/mach-footbridge/include/mach/hardware.h5
-rw-r--r--arch/arm/mach-footbridge/include/mach/io.h3
-rw-r--r--arch/arm/mach-footbridge/include/mach/isa-dma.h (renamed from arch/arm/mach-footbridge/include/mach/dma.h)2
-rw-r--r--arch/arm/mach-footbridge/include/mach/memory.h9
-rw-r--r--arch/arm/mach-h720x/include/mach/io.h4
-rw-r--r--arch/arm/mach-h720x/include/mach/isa-dma.h (renamed from arch/arm/mach-h720x/include/mach/dma.h)9
-rw-r--r--arch/arm/mach-h720x/include/mach/memory.h20
-rw-r--r--arch/arm/mach-imx/dma.c7
-rw-r--r--arch/arm/mach-imx/include/mach/imx-dma.h12
-rw-r--r--arch/arm/mach-imx/include/mach/io.h4
-rw-r--r--arch/arm/mach-imx/include/mach/memory.h10
-rw-r--r--arch/arm/mach-integrator/include/mach/dma.h19
-rw-r--r--arch/arm/mach-integrator/include/mach/memory.h13
-rw-r--r--arch/arm/mach-iop13xx/include/mach/dma.h3
-rw-r--r--arch/arm/mach-iop13xx/include/mach/memory.h16
-rw-r--r--arch/arm/mach-iop13xx/include/mach/timex.h2
-rw-r--r--arch/arm/mach-iop32x/include/mach/dma.h9
-rw-r--r--arch/arm/mach-iop32x/include/mach/io.h2
-rw-r--r--arch/arm/mach-iop32x/include/mach/memory.h13
-rw-r--r--arch/arm/mach-iop32x/include/mach/system.h3
-rw-r--r--arch/arm/mach-iop32x/include/mach/timex.h3
-rw-r--r--arch/arm/mach-iop33x/include/mach/dma.h9
-rw-r--r--arch/arm/mach-iop33x/include/mach/io.h2
-rw-r--r--arch/arm/mach-iop33x/include/mach/memory.h13
-rw-r--r--arch/arm/mach-iop33x/include/mach/timex.h3
-rw-r--r--arch/arm/mach-ixp2000/include/mach/dma.h9
-rw-r--r--arch/arm/mach-ixp2000/include/mach/memory.h7
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/dma.h3
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/io.h2
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/memory.h13
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/dma.h21
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/io.h4
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/memory.h13
-rw-r--r--arch/arm/mach-kirkwood/include/mach/dma.h1
-rw-r--r--arch/arm/mach-kirkwood/include/mach/memory.h4
-rw-r--r--arch/arm/mach-ks8695/include/mach/dma.h17
-rw-r--r--arch/arm/mach-ks8695/include/mach/io.h4
-rw-r--r--arch/arm/mach-ks8695/include/mach/memory.h5
-rw-r--r--arch/arm/mach-l7200/include/mach/dma.h23
-rw-r--r--arch/arm/mach-l7200/include/mach/io.h10
-rw-r--r--arch/arm/mach-l7200/include/mach/memory.h3
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/io.h6
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/memory.h10
-rw-r--r--arch/arm/mach-loki/include/mach/dma.h1
-rw-r--r--arch/arm/mach-loki/include/mach/memory.h4
-rw-r--r--arch/arm/mach-msm/include/mach/io.h6
-rw-r--r--arch/arm/mach-msm/include/mach/memory.h4
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/dma.h1
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/memory.h4
-rw-r--r--arch/arm/mach-netx/include/mach/dma.h21
-rw-r--r--arch/arm/mach-netx/include/mach/io.h2
-rw-r--r--arch/arm/mach-netx/include/mach/memory.h10
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/dma.h14
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/io.h2
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/memory.h3
-rw-r--r--arch/arm/mach-omap1/Kconfig3
-rw-r--r--arch/arm/mach-orion5x/include/mach/dma.h1
-rw-r--r--arch/arm/mach-orion5x/include/mach/io.h7
-rw-r--r--arch/arm/mach-orion5x/include/mach/memory.h4
-rw-r--r--arch/arm/mach-pnx4008/dma.c3
-rw-r--r--arch/arm/mach-pnx4008/include/mach/dma.h2
-rw-r--r--arch/arm/mach-pnx4008/include/mach/io.h4
-rw-r--r--arch/arm/mach-pnx4008/include/mach/memory.h5
-rw-r--r--arch/arm/mach-pxa/Kconfig3
-rw-r--r--arch/arm/mach-pxa/dma.c2
-rw-r--r--arch/arm/mach-pxa/ezx.c1
-rw-r--r--arch/arm/mach-pxa/include/mach/io.h6
-rw-r--r--arch/arm/mach-pxa/include/mach/memory.h11
-rw-r--r--arch/arm/mach-pxa/mioa701.c2
-rw-r--r--arch/arm/mach-pxa/mioa701_bootresume.S1
-rw-r--r--arch/arm/mach-pxa/smemc.c2
-rw-r--r--arch/arm/mach-pxa/time.c1
-rw-r--r--arch/arm/mach-realview/Kconfig2
-rw-r--r--arch/arm/mach-realview/include/mach/dma.h20
-rw-r--r--arch/arm/mach-realview/include/mach/io.h9
-rw-r--r--arch/arm/mach-realview/include/mach/memory.h10
-rw-r--r--arch/arm/mach-rpc/include/mach/io.h47
-rw-r--r--arch/arm/mach-rpc/include/mach/irqs.h1
-rw-r--r--arch/arm/mach-rpc/include/mach/isa-dma.h (renamed from arch/arm/mach-rpc/include/mach/dma.h)8
-rw-r--r--arch/arm/mach-rpc/include/mach/memory.h7
-rw-r--r--arch/arm/mach-s3c2400/include/mach/memory.h3
-rw-r--r--arch/arm/mach-s3c2410/Kconfig1
-rw-r--r--arch/arm/mach-s3c2410/dma.c5
-rw-r--r--arch/arm/mach-s3c2410/include/mach/dma.h23
-rw-r--r--arch/arm/mach-s3c2410/include/mach/memory.h3
-rw-r--r--arch/arm/mach-s3c2410/include/mach/system-reset.h2
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c4
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c2
-rw-r--r--arch/arm/mach-s3c2410/mach-n30.c4
-rw-r--r--arch/arm/mach-s3c2410/mach-qt2410.c4
-rw-r--r--arch/arm/mach-s3c2412/Kconfig1
-rw-r--r--arch/arm/mach-s3c2412/dma.c5
-rw-r--r--arch/arm/mach-s3c2412/mach-jive.c6
-rw-r--r--arch/arm/mach-s3c2412/mach-smdk2413.c2
-rw-r--r--arch/arm/mach-s3c2412/mach-vstms.c2
-rw-r--r--arch/arm/mach-s3c2412/s3c2412.c2
-rw-r--r--arch/arm/mach-s3c2440/Kconfig1
-rw-r--r--arch/arm/mach-s3c2440/dma.c5
-rw-r--r--arch/arm/mach-s3c2440/mach-anubis.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-at2440evb.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-osiris.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-rx3715.c2
-rw-r--r--arch/arm/mach-s3c2442/Kconfig1
-rw-r--r--arch/arm/mach-s3c2443/dma.c5
-rw-r--r--arch/arm/mach-sa1100/collie_pm.c2
-rw-r--r--arch/arm/mach-sa1100/dma.c2
-rw-r--r--arch/arm/mach-sa1100/include/mach/io.h8
-rw-r--r--arch/arm/mach-sa1100/include/mach/memory.h13
-rw-r--r--arch/arm/mach-shark/core.c2
-rw-r--r--arch/arm/mach-shark/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-shark/include/mach/io.h44
-rw-r--r--arch/arm/mach-shark/include/mach/isa-dma.h (renamed from arch/arm/mach-shark/include/mach/dma.h)3
-rw-r--r--arch/arm/mach-shark/include/mach/memory.h4
-rw-r--r--arch/arm/mach-versatile/Kconfig2
-rw-r--r--arch/arm/mach-versatile/include/mach/dma.h20
-rw-r--r--arch/arm/mach-versatile/include/mach/io.h8
-rw-r--r--arch/arm/mach-versatile/include/mach/irqs.h86
-rw-r--r--arch/arm/mach-versatile/include/mach/memory.h10
-rw-r--r--arch/arm/mach-versatile/include/mach/platform.h58
-rw-r--r--arch/arm/mm/Kconfig65
-rw-r--r--arch/arm/mm/alignment.c1
-rw-r--r--arch/arm/mm/cache-v3.S1
-rw-r--r--arch/arm/mm/cache-v4.S1
-rw-r--r--arch/arm/mm/cache-v4wt.S1
-rw-r--r--arch/arm/mm/cache-v7.S2
-rw-r--r--arch/arm/mm/copypage-feroceon.S95
-rw-r--r--arch/arm/mm/copypage-feroceon.c111
-rw-r--r--arch/arm/mm/copypage-v3.S67
-rw-r--r--arch/arm/mm/copypage-v3.c81
-rw-r--r--arch/arm/mm/copypage-v4mc.c53
-rw-r--r--arch/arm/mm/copypage-v4wb.S79
-rw-r--r--arch/arm/mm/copypage-v4wb.c94
-rw-r--r--arch/arm/mm/copypage-v4wt.S73
-rw-r--r--arch/arm/mm/copypage-v4wt.c88
-rw-r--r--arch/arm/mm/copypage-v6.c84
-rw-r--r--arch/arm/mm/copypage-xsc3.S97
-rw-r--r--arch/arm/mm/copypage-xsc3.c113
-rw-r--r--arch/arm/mm/copypage-xscale.c47
-rw-r--r--arch/arm/mm/fault.c6
-rw-r--r--arch/arm/mm/init.c57
-rw-r--r--arch/arm/mm/mm.h2
-rw-r--r--arch/arm/mm/mmu.c116
-rw-r--r--arch/arm/mm/nommu.c18
-rw-r--r--arch/arm/mm/pgd.c2
-rw-r--r--arch/arm/mm/proc-syms.c4
-rw-r--r--arch/arm/mm/proc-v6.S2
-rw-r--r--arch/arm/mm/proc-v7.S19
-rw-r--r--arch/arm/plat-mxc/Kconfig2
-rw-r--r--arch/arm/plat-mxc/dma-mx1-mx2.c2
-rw-r--r--arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/dma.h14
-rw-r--r--arch/arm/plat-mxc/include/mach/io.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h13
-rw-r--r--arch/arm/plat-omap/Kconfig2
-rw-r--r--arch/arm/plat-omap/dma.c2
-rw-r--r--arch/arm/plat-omap/gpio.c5
-rw-r--r--arch/arm/plat-omap/include/mach/io.h6
-rw-r--r--arch/arm/plat-omap/include/mach/memory.h17
-rw-r--r--arch/arm/plat-omap/include/mach/pm.h2
-rw-r--r--arch/arm/plat-s3c/include/plat/iic.h33
-rw-r--r--arch/arm/plat-s3c/include/plat/nand.h50
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-ac97.h67
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-iic.h56
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-nand.h123
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-rtc.h61
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-watchdog.h41
-rw-r--r--arch/arm/plat-s3c/include/plat/uncompress.h2
-rw-r--r--arch/arm/plat-s3c24xx/common-smdk.c2
-rw-r--r--arch/arm/plat-s3c24xx/devs.c4
-rw-r--r--arch/arm/plat-s3c24xx/dma.c17
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/mci.h15
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-spi.h82
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-udc.h153
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/udc.h36
-rw-r--r--arch/arm/tools/mach-types101
-rw-r--r--arch/arm/vfp/vfphw.S27
-rw-r--r--arch/arm/vfp/vfpmodule.c9
238 files changed, 1903 insertions, 2929 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 995a1bfe3ae4..131b7120995e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -201,6 +201,7 @@ choice
201 201
202config ARCH_AAEC2000 202config ARCH_AAEC2000
203 bool "Agilent AAEC-2000 based" 203 bool "Agilent AAEC-2000 based"
204 select CPU_ARM920T
204 select ARM_AMBA 205 select ARM_AMBA
205 select HAVE_CLK 206 select HAVE_CLK
206 help 207 help
@@ -246,22 +247,15 @@ config ARCH_AT91
246 This enables support for systems based on the Atmel AT91RM9200, 247 This enables support for systems based on the Atmel AT91RM9200,
247 AT91SAM9 and AT91CAP9 processors. 248 AT91SAM9 and AT91CAP9 processors.
248 249
249config ARCH_CLPS7500
250 bool "Cirrus CL-PS7500FE"
251 select TIMER_ACORN
252 select ISA
253 select NO_IOPORT
254 select ARCH_SPARSEMEM_ENABLE
255 help
256 Support for the Cirrus Logic PS7500FE system-on-a-chip.
257
258config ARCH_CLPS711X 250config ARCH_CLPS711X
259 bool "Cirrus Logic CLPS711x/EP721x-based" 251 bool "Cirrus Logic CLPS711x/EP721x-based"
252 select CPU_ARM720T
260 help 253 help
261 Support for Cirrus Logic 711x/721x based boards. 254 Support for Cirrus Logic 711x/721x based boards.
262 255
263config ARCH_EBSA110 256config ARCH_EBSA110
264 bool "EBSA-110" 257 bool "EBSA-110"
258 select CPU_SA110
265 select ISA 259 select ISA
266 select NO_IOPORT 260 select NO_IOPORT
267 help 261 help
@@ -272,6 +266,7 @@ config ARCH_EBSA110
272 266
273config ARCH_EP93XX 267config ARCH_EP93XX
274 bool "EP93xx-based" 268 bool "EP93xx-based"
269 select CPU_ARM920T
275 select ARM_AMBA 270 select ARM_AMBA
276 select ARM_VIC 271 select ARM_VIC
277 select GENERIC_GPIO 272 select GENERIC_GPIO
@@ -283,6 +278,7 @@ config ARCH_EP93XX
283 278
284config ARCH_FOOTBRIDGE 279config ARCH_FOOTBRIDGE
285 bool "FootBridge" 280 bool "FootBridge"
281 select CPU_SA110
286 select FOOTBRIDGE 282 select FOOTBRIDGE
287 help 283 help
288 Support for systems based on the DC21285 companion chip 284 Support for systems based on the DC21285 companion chip
@@ -290,18 +286,21 @@ config ARCH_FOOTBRIDGE
290 286
291config ARCH_NETX 287config ARCH_NETX
292 bool "Hilscher NetX based" 288 bool "Hilscher NetX based"
289 select CPU_ARM926T
293 select ARM_VIC 290 select ARM_VIC
294 help 291 help
295 This enables support for systems based on the Hilscher NetX Soc 292 This enables support for systems based on the Hilscher NetX Soc
296 293
297config ARCH_H720X 294config ARCH_H720X
298 bool "Hynix HMS720x-based" 295 bool "Hynix HMS720x-based"
296 select CPU_ARM720T
299 select ISA_DMA_API 297 select ISA_DMA_API
300 help 298 help
301 This enables support for systems based on the Hynix HMS720x 299 This enables support for systems based on the Hynix HMS720x
302 300
303config ARCH_IMX 301config ARCH_IMX
304 bool "IMX" 302 bool "IMX"
303 select CPU_ARM920T
305 select GENERIC_GPIO 304 select GENERIC_GPIO
306 select GENERIC_TIME 305 select GENERIC_TIME
307 select GENERIC_CLOCKEVENTS 306 select GENERIC_CLOCKEVENTS
@@ -311,6 +310,7 @@ config ARCH_IMX
311config ARCH_IOP13XX 310config ARCH_IOP13XX
312 bool "IOP13xx-based" 311 bool "IOP13xx-based"
313 depends on MMU 312 depends on MMU
313 select CPU_XSC3
314 select PLAT_IOP 314 select PLAT_IOP
315 select PCI 315 select PCI
316 select ARCH_SUPPORTS_MSI 316 select ARCH_SUPPORTS_MSI
@@ -321,6 +321,7 @@ config ARCH_IOP13XX
321config ARCH_IOP32X 321config ARCH_IOP32X
322 bool "IOP32x-based" 322 bool "IOP32x-based"
323 depends on MMU 323 depends on MMU
324 select CPU_XSCALE
324 select PLAT_IOP 325 select PLAT_IOP
325 select PCI 326 select PCI
326 select GENERIC_GPIO 327 select GENERIC_GPIO
@@ -332,6 +333,7 @@ config ARCH_IOP32X
332config ARCH_IOP33X 333config ARCH_IOP33X
333 bool "IOP33x-based" 334 bool "IOP33x-based"
334 depends on MMU 335 depends on MMU
336 select CPU_XSCALE
335 select PLAT_IOP 337 select PLAT_IOP
336 select PCI 338 select PCI
337 select GENERIC_GPIO 339 select GENERIC_GPIO
@@ -342,6 +344,7 @@ config ARCH_IOP33X
342config ARCH_IXP23XX 344config ARCH_IXP23XX
343 bool "IXP23XX-based" 345 bool "IXP23XX-based"
344 depends on MMU 346 depends on MMU
347 select CPU_XSC3
345 select PCI 348 select PCI
346 help 349 help
347 Support for Intel's IXP23xx (XScale) family of processors. 350 Support for Intel's IXP23xx (XScale) family of processors.
@@ -349,6 +352,7 @@ config ARCH_IXP23XX
349config ARCH_IXP2000 352config ARCH_IXP2000
350 bool "IXP2400/2800-based" 353 bool "IXP2400/2800-based"
351 depends on MMU 354 depends on MMU
355 select CPU_XSCALE
352 select PCI 356 select PCI
353 help 357 help
354 Support for Intel's IXP2400/2800 (XScale) family of processors. 358 Support for Intel's IXP2400/2800 (XScale) family of processors.
@@ -356,6 +360,7 @@ config ARCH_IXP2000
356config ARCH_IXP4XX 360config ARCH_IXP4XX
357 bool "IXP4xx-based" 361 bool "IXP4xx-based"
358 depends on MMU 362 depends on MMU
363 select CPU_XSCALE
359 select GENERIC_GPIO 364 select GENERIC_GPIO
360 select GENERIC_TIME 365 select GENERIC_TIME
361 select GENERIC_CLOCKEVENTS 366 select GENERIC_CLOCKEVENTS
@@ -365,6 +370,7 @@ config ARCH_IXP4XX
365 370
366config ARCH_L7200 371config ARCH_L7200
367 bool "LinkUp-L7200" 372 bool "LinkUp-L7200"
373 select CPU_ARM720T
368 select FIQ 374 select FIQ
369 help 375 help
370 Say Y here if you intend to run this kernel on a LinkUp Systems 376 Say Y here if you intend to run this kernel on a LinkUp Systems
@@ -378,6 +384,7 @@ config ARCH_L7200
378 384
379config ARCH_KIRKWOOD 385config ARCH_KIRKWOOD
380 bool "Marvell Kirkwood" 386 bool "Marvell Kirkwood"
387 select CPU_FEROCEON
381 select PCI 388 select PCI
382 select GENERIC_TIME 389 select GENERIC_TIME
383 select GENERIC_CLOCKEVENTS 390 select GENERIC_CLOCKEVENTS
@@ -388,6 +395,7 @@ config ARCH_KIRKWOOD
388 395
389config ARCH_KS8695 396config ARCH_KS8695
390 bool "Micrel/Kendin KS8695" 397 bool "Micrel/Kendin KS8695"
398 select CPU_ARM922T
391 select GENERIC_GPIO 399 select GENERIC_GPIO
392 help 400 help
393 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 401 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
@@ -395,6 +403,7 @@ config ARCH_KS8695
395 403
396config ARCH_NS9XXX 404config ARCH_NS9XXX
397 bool "NetSilicon NS9xxx" 405 bool "NetSilicon NS9xxx"
406 select CPU_ARM926T
398 select GENERIC_GPIO 407 select GENERIC_GPIO
399 select GENERIC_TIME 408 select GENERIC_TIME
400 select GENERIC_CLOCKEVENTS 409 select GENERIC_CLOCKEVENTS
@@ -407,6 +416,7 @@ config ARCH_NS9XXX
407 416
408config ARCH_LOKI 417config ARCH_LOKI
409 bool "Marvell Loki (88RC8480)" 418 bool "Marvell Loki (88RC8480)"
419 select CPU_FEROCEON
410 select GENERIC_TIME 420 select GENERIC_TIME
411 select GENERIC_CLOCKEVENTS 421 select GENERIC_CLOCKEVENTS
412 select PLAT_ORION 422 select PLAT_ORION
@@ -415,6 +425,7 @@ config ARCH_LOKI
415 425
416config ARCH_MV78XX0 426config ARCH_MV78XX0
417 bool "Marvell MV78xx0" 427 bool "Marvell MV78xx0"
428 select CPU_FEROCEON
418 select PCI 429 select PCI
419 select GENERIC_TIME 430 select GENERIC_TIME
420 select GENERIC_CLOCKEVENTS 431 select GENERIC_CLOCKEVENTS
@@ -436,6 +447,7 @@ config ARCH_MXC
436config ARCH_ORION5X 447config ARCH_ORION5X
437 bool "Marvell Orion" 448 bool "Marvell Orion"
438 depends on MMU 449 depends on MMU
450 select CPU_FEROCEON
439 select PCI 451 select PCI
440 select GENERIC_GPIO 452 select GENERIC_GPIO
441 select GENERIC_TIME 453 select GENERIC_TIME
@@ -448,6 +460,7 @@ config ARCH_ORION5X
448 460
449config ARCH_PNX4008 461config ARCH_PNX4008
450 bool "Philips Nexperia PNX4008 Mobile" 462 bool "Philips Nexperia PNX4008 Mobile"
463 select CPU_ARM926T
451 select HAVE_CLK 464 select HAVE_CLK
452 help 465 help
453 This enables support for Philips PNX4008 mobile platform. 466 This enables support for Philips PNX4008 mobile platform.
@@ -482,6 +495,7 @@ config ARCH_RPC
482 495
483config ARCH_SA1100 496config ARCH_SA1100
484 bool "SA1100-based" 497 bool "SA1100-based"
498 select CPU_SA1100
485 select ISA 499 select ISA
486 select ARCH_SPARSEMEM_ENABLE 500 select ARCH_SPARSEMEM_ENABLE
487 select ARCH_MTD_XIP 501 select ARCH_MTD_XIP
@@ -505,6 +519,7 @@ config ARCH_S3C2410
505 519
506config ARCH_SHARK 520config ARCH_SHARK
507 bool "Shark" 521 bool "Shark"
522 select CPU_SA110
508 select ISA 523 select ISA
509 select ISA_DMA 524 select ISA_DMA
510 select ZONE_DMA 525 select ZONE_DMA
@@ -515,6 +530,7 @@ config ARCH_SHARK
515 530
516config ARCH_LH7A40X 531config ARCH_LH7A40X
517 bool "Sharp LH7A40X" 532 bool "Sharp LH7A40X"
533 select CPU_ARM922T
518 select ARCH_DISCONTIGMEM_ENABLE if !LH7A40X_CONTIGMEM 534 select ARCH_DISCONTIGMEM_ENABLE if !LH7A40X_CONTIGMEM
519 select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM 535 select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
520 help 536 help
@@ -525,6 +541,7 @@ config ARCH_LH7A40X
525 541
526config ARCH_DAVINCI 542config ARCH_DAVINCI
527 bool "TI DaVinci" 543 bool "TI DaVinci"
544 select CPU_ARM926T
528 select GENERIC_TIME 545 select GENERIC_TIME
529 select GENERIC_CLOCKEVENTS 546 select GENERIC_CLOCKEVENTS
530 select GENERIC_GPIO 547 select GENERIC_GPIO
@@ -546,6 +563,7 @@ config ARCH_OMAP
546 563
547config ARCH_MSM 564config ARCH_MSM
548 bool "Qualcomm MSM" 565 bool "Qualcomm MSM"
566 select CPU_V6
549 select GENERIC_TIME 567 select GENERIC_TIME
550 select GENERIC_CLOCKEVENTS 568 select GENERIC_CLOCKEVENTS
551 help 569 help
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index bd6e28115ebb..2eca2998f93e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -96,7 +96,6 @@ textofs-y := 0x00008000
96 96
97 machine-$(CONFIG_ARCH_RPC) := rpc 97 machine-$(CONFIG_ARCH_RPC) := rpc
98 machine-$(CONFIG_ARCH_EBSA110) := ebsa110 98 machine-$(CONFIG_ARCH_EBSA110) := ebsa110
99 machine-$(CONFIG_ARCH_CLPS7500) := clps7500
100 machine-$(CONFIG_FOOTBRIDGE) := footbridge 99 machine-$(CONFIG_FOOTBRIDGE) := footbridge
101 machine-$(CONFIG_ARCH_SHARK) := shark 100 machine-$(CONFIG_ARCH_SHARK) := shark
102 machine-$(CONFIG_ARCH_SA1100) := sa1100 101 machine-$(CONFIG_ARCH_SA1100) := sa1100
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index c47f2a3f8f8f..fbe5eef1f6c9 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -23,10 +23,6 @@ ifeq ($(CONFIG_ARCH_L7200),y)
23OBJS += head-l7200.o 23OBJS += head-l7200.o
24endif 24endif
25 25
26ifeq ($(CONFIG_ARCH_CLPS7500),y)
27HEAD = head-clps7500.o
28endif
29
30ifeq ($(CONFIG_ARCH_P720T),y) 26ifeq ($(CONFIG_ARCH_P720T),y)
31# Borrow this code from SA1100 27# Borrow this code from SA1100
32OBJS += head-sa1100.o 28OBJS += head-sa1100.o
diff --git a/arch/arm/boot/compressed/head-clps7500.S b/arch/arm/boot/compressed/head-clps7500.S
deleted file mode 100644
index 4f3c78ac30a0..000000000000
--- a/arch/arm/boot/compressed/head-clps7500.S
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 * linux/arch/arm/boot/compressed/head-clps7500.S
3 *
4 * Copyright (C) 1999, 2000, 2001 Nexus Electronics Ltd
5 */
6
7
8 /* There are three different ways the kernel can be
9 booted on a 7500 system: from Angel (loaded in RAM), from
10 16-bit ROM or from 32-bit Flash. Luckily, a single kernel
11 image does for them all. */
12 /* This branch is taken if the CPU memory width matches the
13 actual device in use. The default at power on is 16 bits
14 so we must be prepared for a mismatch. */
15 .section ".start", "ax"
162:
17 b 1f
18 .word 0xffff
19 .word 0xb632 @ mov r11, #0x03200000
20 .word 0xe3a0
21 .word 0x0000 @ mov r0, #0
22 .word 0xe3a0
23 .word 0x0080 @ strb r0, [r11, #0x80]
24 .word 0xe5cb
25 .word 0xf000 @ mov pc, #0
26 .word 0xe3a0
271:
28 adr r1, 2b
29 teq r1, #0
30 bne .Langel
31 /* This is a direct-from-ROM boot. Copy the kernel into
32 RAM and run it there. */
33 mov r0, #0x30
34 mcr p15, 0, r0, c1, c0, 0
35 mov r0, #0x13
36 msr cpsr_cxsf, r0
37 mov r12, #0x03000000 @ point to LEDs
38 orr r12, r12, #0x00020000
39 orr r12, r12, #0xba00
40 mov r0, #0x5500
41 str r0, [r12]
42 mov r0, #0x10000000
43 orr r0, r0, #0x8000
44 mov r4, r0
45 ldr r2, =_end
462:
47 ldr r3, [r1], #4
48 str r3, [r0], #4
49 teq r0, r2
50 bne 2b
51 mov r0, #0xff00
52 str r0, [r12]
531:
54 mov r12, #0x03000000 @ point to LEDs
55 orr r12, r12, #0x00020000
56 orr r12, r12, #0xba00
57 mov r0, #0xfe00
58 str r0, [r12]
59
60 adr lr, 1f
61 mov r0, #0
62 mov r1, #14 /* MACH_TYPE_CLPS7500 */
63 mov pc, lr
64.Langel:
65#ifdef CONFIG_ANGELBOOT
66 /* Call Angel to switch into SVC mode. */
67 mov r0, #0x17
68 swi 0x123456
69#endif
70 /* Ensure all interrupts are off and MMU disabled */
71 mrs r0, cpsr
72 orr r0, r0, #0xc0
73 msr cpsr_cxsf, r0
74
75 adr lr, 1b
76 orr lr, lr, #0x10000000
77 mov r0, #0x30 @ MMU off
78 mcr p15, 0, r0, c1, c0, 0
79 mov r0, r0
80 mov pc, lr
81
82 .ltorg
83
841:
85/* And the rest */
86#include "head.S"
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 84a1e0496a3c..7b1f31295a0a 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -717,6 +717,9 @@ __armv7_mmu_cache_off:
717 bl __armv7_mmu_cache_flush 717 bl __armv7_mmu_cache_flush
718 mov r0, #0 718 mov r0, #0
719 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB 719 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
720 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
721 mcr p15, 0, r0, c7, c10, 4 @ DSB
722 mcr p15, 0, r0, c7, c5, 4 @ ISB
720 mov pc, r12 723 mov pc, r12
721 724
722__arm6_mmu_cache_off: 725__arm6_mmu_cache_off:
@@ -778,12 +781,13 @@ __armv6_mmu_cache_flush:
778__armv7_mmu_cache_flush: 781__armv7_mmu_cache_flush:
779 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 782 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
780 tst r10, #0xf << 16 @ hierarchical cache (ARMv7) 783 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
781 beq hierarchical
782 mov r10, #0 784 mov r10, #0
785 beq hierarchical
783 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D 786 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
784 b iflush 787 b iflush
785hierarchical: 788hierarchical:
786 stmfd sp!, {r0-r5, r7, r9-r11} 789 mcr p15, 0, r10, c7, c10, 5 @ DMB
790 stmfd sp!, {r0-r5, r7, r9, r11}
787 mrc p15, 1, r0, c0, c0, 1 @ read clidr 791 mrc p15, 1, r0, c0, c0, 1 @ read clidr
788 ands r3, r0, #0x7000000 @ extract loc from clidr 792 ands r3, r0, #0x7000000 @ extract loc from clidr
789 mov r3, r3, lsr #23 @ left align loc bit field 793 mov r3, r3, lsr #23 @ left align loc bit field
@@ -820,12 +824,14 @@ skip:
820 cmp r3, r10 824 cmp r3, r10
821 bgt loop1 825 bgt loop1
822finished: 826finished:
827 ldmfd sp!, {r0-r5, r7, r9, r11}
823 mov r10, #0 @ swith back to cache level 0 828 mov r10, #0 @ swith back to cache level 0
824 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 829 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
825 ldmfd sp!, {r0-r5, r7, r9-r11}
826iflush: 830iflush:
831 mcr p15, 0, r10, c7, c10, 4 @ DSB
827 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB 832 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
828 mcr p15, 0, r10, c7, c10, 4 @ drain WB 833 mcr p15, 0, r10, c7, c10, 4 @ DSB
834 mcr p15, 0, r10, c7, c5, 4 @ ISB
829 mov pc, lr 835 mov pc, lr
830 836
831__armv5tej_mmu_cache_flush: 837__armv5tej_mmu_cache_flush:
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 65ce8fff29db..3fc08413fff0 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -86,6 +86,8 @@ static void putstr(const char *ptr)
86 86
87#define __ptr_t void * 87#define __ptr_t void *
88 88
89#define memzero(s,n) __memzero(s,n)
90
89/* 91/*
90 * Optimised C version of memzero for the ARM. 92 * Optimised C version of memzero for the ARM.
91 */ 93 */
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index de6c59f814a1..6cbd8fdc9f1f 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -10,11 +10,11 @@
10#ifndef _ASMARM_CACHEFLUSH_H 10#ifndef _ASMARM_CACHEFLUSH_H
11#define _ASMARM_CACHEFLUSH_H 11#define _ASMARM_CACHEFLUSH_H
12 12
13#include <linux/sched.h>
14#include <linux/mm.h> 13#include <linux/mm.h>
15 14
16#include <asm/glue.h> 15#include <asm/glue.h>
17#include <asm/shmparam.h> 16#include <asm/shmparam.h>
17#include <asm/cachetype.h>
18 18
19#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) 19#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
20 20
@@ -296,16 +296,6 @@ static inline void outer_flush_range(unsigned long start, unsigned long end)
296#endif 296#endif
297 297
298/* 298/*
299 * flush_cache_vmap() is used when creating mappings (eg, via vmap,
300 * vmalloc, ioremap etc) in kernel space for pages. Since the
301 * direct-mappings of these pages may contain cached data, we need
302 * to do a full cache flush to ensure that writebacks don't corrupt
303 * data placed into these pages via the new mappings.
304 */
305#define flush_cache_vmap(start, end) flush_cache_all()
306#define flush_cache_vunmap(start, end) flush_cache_all()
307
308/*
309 * Copy user data from/to a page which is mapped into a different 299 * Copy user data from/to a page which is mapped into a different
310 * processes address space. Really, we want to allow our "user 300 * processes address space. Really, we want to allow our "user
311 * space" model to handle this. 301 * space" model to handle this.
@@ -444,4 +434,29 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
444 dmac_inv_range(start, start + size); 434 dmac_inv_range(start, start + size);
445} 435}
446 436
437/*
438 * flush_cache_vmap() is used when creating mappings (eg, via vmap,
439 * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT
440 * caches, since the direct-mappings of these pages may contain cached
441 * data, we need to do a full cache flush to ensure that writebacks
442 * don't corrupt data placed into these pages via the new mappings.
443 */
444static inline void flush_cache_vmap(unsigned long start, unsigned long end)
445{
446 if (!cache_is_vipt_nonaliasing())
447 flush_cache_all();
448 else
449 /*
450 * set_pte_at() called from vmap_pte_range() does not
451 * have a DSB after cleaning the cache line.
452 */
453 dsb();
454}
455
456static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
457{
458 if (!cache_is_vipt_nonaliasing())
459 flush_cache_all();
460}
461
447#endif 462#endif
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 75154b193117..df5638f3643a 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -1,12 +1,7 @@
1#ifndef __ASM_ARM_DMA_H 1#ifndef __ASM_ARM_DMA_H
2#define __ASM_ARM_DMA_H 2#define __ASM_ARM_DMA_H
3 3
4typedef unsigned int dmach_t; 4#include <asm/memory.h>
5
6#include <linux/spinlock.h>
7#include <asm/system.h>
8#include <asm/scatterlist.h>
9#include <mach/dma.h>
10 5
11/* 6/*
12 * This is the maximum virtual address which can be DMA'd from. 7 * This is the maximum virtual address which can be DMA'd from.
@@ -15,6 +10,19 @@ typedef unsigned int dmach_t;
15#define MAX_DMA_ADDRESS 0xffffffff 10#define MAX_DMA_ADDRESS 0xffffffff
16#endif 11#endif
17 12
13#ifdef CONFIG_ISA_DMA_API
14/*
15 * This is used to support drivers written for the x86 ISA DMA API.
16 * It should not be re-used except for that purpose.
17 */
18#include <linux/spinlock.h>
19#include <asm/system.h>
20#include <asm/scatterlist.h>
21
22typedef unsigned int dmach_t;
23
24#include <mach/isa-dma.h>
25
18/* 26/*
19 * DMA modes 27 * DMA modes
20 */ 28 */
@@ -140,4 +148,6 @@ extern int isa_dma_bridge_buggy;
140#define isa_dma_bridge_buggy (0) 148#define isa_dma_bridge_buggy (0)
141#endif 149#endif
142 150
143#endif /* _ARM_DMA_H */ 151#endif /* CONFIG_ISA_DMA_API */
152
153#endif /* __ASM_ARM_DMA_H */
diff --git a/arch/arm/include/asm/hardware/iomd.h b/arch/arm/include/asm/hardware/iomd.h
index 9c5afbd71a69..f9ee69e4f53e 100644
--- a/arch/arm/include/asm/hardware/iomd.h
+++ b/arch/arm/include/asm/hardware/iomd.h
@@ -32,19 +32,11 @@
32#define IOMD_KARTRX (0x004) 32#define IOMD_KARTRX (0x004)
33#define IOMD_KCTRL (0x008) 33#define IOMD_KCTRL (0x008)
34 34
35#ifdef CONFIG_ARCH_CLPS7500
36#define IOMD_IOLINES (0x00C)
37#endif
38
39#define IOMD_IRQSTATA (0x010) 35#define IOMD_IRQSTATA (0x010)
40#define IOMD_IRQREQA (0x014) 36#define IOMD_IRQREQA (0x014)
41#define IOMD_IRQCLRA (0x014) 37#define IOMD_IRQCLRA (0x014)
42#define IOMD_IRQMASKA (0x018) 38#define IOMD_IRQMASKA (0x018)
43 39
44#ifdef CONFIG_ARCH_CLPS7500
45#define IOMD_SUSMODE (0x01C)
46#endif
47
48#define IOMD_IRQSTATB (0x020) 40#define IOMD_IRQSTATB (0x020)
49#define IOMD_IRQREQB (0x024) 41#define IOMD_IRQREQB (0x024)
50#define IOMD_IRQMASKB (0x028) 42#define IOMD_IRQMASKB (0x028)
@@ -53,10 +45,6 @@
53#define IOMD_FIQREQ (0x034) 45#define IOMD_FIQREQ (0x034)
54#define IOMD_FIQMASK (0x038) 46#define IOMD_FIQMASK (0x038)
55 47
56#ifdef CONFIG_ARCH_CLPS7500
57#define IOMD_CLKCTL (0x03C)
58#endif
59
60#define IOMD_T0CNTL (0x040) 48#define IOMD_T0CNTL (0x040)
61#define IOMD_T0LTCHL (0x040) 49#define IOMD_T0LTCHL (0x040)
62#define IOMD_T0CNTH (0x044) 50#define IOMD_T0CNTH (0x044)
@@ -71,18 +59,6 @@
71#define IOMD_T1GO (0x058) 59#define IOMD_T1GO (0x058)
72#define IOMD_T1LATCH (0x05c) 60#define IOMD_T1LATCH (0x05c)
73 61
74#ifdef CONFIG_ARCH_CLPS7500
75#define IOMD_IRQSTATC (0x060)
76#define IOMD_IRQREQC (0x064)
77#define IOMD_IRQMASKC (0x068)
78
79#define IOMD_VIDMUX (0x06c)
80
81#define IOMD_IRQSTATD (0x070)
82#define IOMD_IRQREQD (0x074)
83#define IOMD_IRQMASKD (0x078)
84#endif
85
86#define IOMD_ROMCR0 (0x080) 62#define IOMD_ROMCR0 (0x080)
87#define IOMD_ROMCR1 (0x084) 63#define IOMD_ROMCR1 (0x084)
88#ifdef CONFIG_ARCH_RPC 64#ifdef CONFIG_ARCH_RPC
@@ -100,11 +76,6 @@
100#define IOMD_MOUSEY (0x0A4) 76#define IOMD_MOUSEY (0x0A4)
101#endif 77#endif
102 78
103#ifdef CONFIG_ARCH_CLPS7500
104#define IOMD_MSEDAT (0x0A8)
105#define IOMD_MSECTL (0x0Ac)
106#endif
107
108#ifdef CONFIG_ARCH_RPC 79#ifdef CONFIG_ARCH_RPC
109#define IOMD_DMATCR (0x0C0) 80#define IOMD_DMATCR (0x0C0)
110#endif 81#endif
@@ -113,18 +84,6 @@
113#ifdef CONFIG_ARCH_RPC 84#ifdef CONFIG_ARCH_RPC
114#define IOMD_DMAEXT (0x0CC) 85#define IOMD_DMAEXT (0x0CC)
115#endif 86#endif
116#ifdef CONFIG_ARCH_CLPS7500
117#define IOMD_ASTCR (0x0CC)
118#define IOMD_DRAMCR (0x0D0)
119#define IOMD_SELFREF (0x0D4)
120#define IOMD_ATODICR (0x0E0)
121#define IOMD_ATODSR (0x0E4)
122#define IOMD_ATODCC (0x0E8)
123#define IOMD_ATODCNT1 (0x0EC)
124#define IOMD_ATODCNT2 (0x0F0)
125#define IOMD_ATODCNT3 (0x0F4)
126#define IOMD_ATODCNT4 (0x0F8)
127#endif
128 87
129#ifdef CONFIG_ARCH_RPC 88#ifdef CONFIG_ARCH_RPC
130#define DMA_EXT_IO0 1 89#define DMA_EXT_IO0 1
diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index 81f4c899a555..bda489f9f017 100644
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -16,6 +16,7 @@
16#define HWCAP_IWMMXT 512 16#define HWCAP_IWMMXT 512
17#define HWCAP_CRUNCH 1024 17#define HWCAP_CRUNCH 1024
18#define HWCAP_THUMBEE 2048 18#define HWCAP_THUMBEE 2048
19#define HWCAP_NEON 4096
19 20
20#if defined(__KERNEL__) && !defined(__ASSEMBLY__) 21#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
21/* 22/*
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index a8094451be57..d2a59cfc30ce 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -80,6 +80,14 @@ extern void __iounmap(volatile void __iomem *addr);
80extern void __readwrite_bug(const char *fn); 80extern void __readwrite_bug(const char *fn);
81 81
82/* 82/*
83 * A typesafe __io() helper
84 */
85static inline void __iomem *__typesafe_io(unsigned long addr)
86{
87 return (void __iomem *)addr;
88}
89
90/*
83 * Now, pick up the machine-defined IO definitions 91 * Now, pick up the machine-defined IO definitions
84 */ 92 */
85#include <mach/io.h> 93#include <mach/io.h>
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index a0009aa5d157..328f14a8b790 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -7,10 +7,6 @@
7#define irq_canonicalize(i) (i) 7#define irq_canonicalize(i) (i)
8#endif 8#endif
9 9
10#ifndef NR_IRQS
11#define NR_IRQS 128
12#endif
13
14/* 10/*
15 * Use this value to indicate lack of interrupt 11 * Use this value to indicate lack of interrupt
16 * capability 12 * capability
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 77764301844b..0202a7c20e62 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -112,10 +112,8 @@
112 * private definitions which should NOT be used outside memory.h 112 * private definitions which should NOT be used outside memory.h
113 * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. 113 * files. Use virt_to_phys/phys_to_virt/__pa/__va instead.
114 */ 114 */
115#ifndef __virt_to_phys
116#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) 115#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET)
117#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) 116#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET)
118#endif
119 117
120/* 118/*
121 * Convert a physical address to a Page Frame Number and back 119 * Convert a physical address to a Page Frame Number and back
@@ -180,6 +178,11 @@ static inline void *phys_to_virt(unsigned long x)
180 * memory. Use of these is *deprecated* (and that doesn't mean 178 * memory. Use of these is *deprecated* (and that doesn't mean
181 * use the __ prefixed forms instead.) See dma-mapping.h. 179 * use the __ prefixed forms instead.) See dma-mapping.h.
182 */ 180 */
181#ifndef __virt_to_bus
182#define __virt_to_bus __virt_to_phys
183#define __bus_to_virt __phys_to_virt
184#endif
185
183static inline __deprecated unsigned long virt_to_bus(void *x) 186static inline __deprecated unsigned long virt_to_bus(void *x)
184{ 187{
185 return __virt_to_bus((unsigned long)x); 188 return __virt_to_bus((unsigned long)x);
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index 0559f37c2a27..263fed05ea33 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -14,6 +14,7 @@
14#define __ASM_ARM_MMU_CONTEXT_H 14#define __ASM_ARM_MMU_CONTEXT_H
15 15
16#include <linux/compiler.h> 16#include <linux/compiler.h>
17#include <linux/sched.h>
17#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
18#include <asm/cachetype.h> 19#include <asm/cachetype.h>
19#include <asm/proc-fns.h> 20#include <asm/proc-fns.h>
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index bed1c0a00368..f341c9dbd662 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -108,32 +108,38 @@
108#error Unknown user operations model 108#error Unknown user operations model
109#endif 109#endif
110 110
111struct page;
112
111struct cpu_user_fns { 113struct cpu_user_fns {
112 void (*cpu_clear_user_page)(void *p, unsigned long user); 114 void (*cpu_clear_user_highpage)(struct page *page, unsigned long vaddr);
113 void (*cpu_copy_user_page)(void *to, const void *from, 115 void (*cpu_copy_user_highpage)(struct page *to, struct page *from,
114 unsigned long user); 116 unsigned long vaddr);
115}; 117};
116 118
117#ifdef MULTI_USER 119#ifdef MULTI_USER
118extern struct cpu_user_fns cpu_user; 120extern struct cpu_user_fns cpu_user;
119 121
120#define __cpu_clear_user_page cpu_user.cpu_clear_user_page 122#define __cpu_clear_user_highpage cpu_user.cpu_clear_user_highpage
121#define __cpu_copy_user_page cpu_user.cpu_copy_user_page 123#define __cpu_copy_user_highpage cpu_user.cpu_copy_user_highpage
122 124
123#else 125#else
124 126
125#define __cpu_clear_user_page __glue(_USER,_clear_user_page) 127#define __cpu_clear_user_highpage __glue(_USER,_clear_user_highpage)
126#define __cpu_copy_user_page __glue(_USER,_copy_user_page) 128#define __cpu_copy_user_highpage __glue(_USER,_copy_user_highpage)
127 129
128extern void __cpu_clear_user_page(void *p, unsigned long user); 130extern void __cpu_clear_user_highpage(struct page *page, unsigned long vaddr);
129extern void __cpu_copy_user_page(void *to, const void *from, 131extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
130 unsigned long user); 132 unsigned long vaddr);
131#endif 133#endif
132 134
133#define clear_user_page(addr,vaddr,pg) __cpu_clear_user_page(addr, vaddr) 135#define clear_user_highpage(page,vaddr) \
134#define copy_user_page(to,from,vaddr,pg) __cpu_copy_user_page(to, from, vaddr) 136 __cpu_clear_user_highpage(page, vaddr)
137
138#define __HAVE_ARCH_COPY_USER_HIGHPAGE
139#define copy_user_highpage(to,from,vaddr,vma) \
140 __cpu_copy_user_highpage(to, from, vaddr)
135 141
136#define clear_page(page) memzero((void *)(page), PAGE_SIZE) 142#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
137extern void copy_page(void *to, const void *from); 143extern void copy_page(void *to, const void *from);
138 144
139#undef STRICT_MM_TYPECHECKS 145#undef STRICT_MM_TYPECHECKS
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 517a4d6ffc74..2320508443a5 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -64,7 +64,7 @@ struct thread_struct {
64({ \ 64({ \
65 unsigned long *stack = (unsigned long *)sp; \ 65 unsigned long *stack = (unsigned long *)sp; \
66 set_fs(USER_DS); \ 66 set_fs(USER_DS); \
67 memzero(regs->uregs, sizeof(regs->uregs)); \ 67 memset(regs->uregs, 0, sizeof(regs->uregs)); \
68 if (current->personality & ADDR_LIMIT_32BIT) \ 68 if (current->personality & ADDR_LIMIT_32BIT) \
69 regs->ARM_cpsr = USR_MODE; \ 69 regs->ARM_cpsr = USR_MODE; \
70 else \ 70 else \
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index a65413ba121d..f2cd18a0932b 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -209,9 +209,11 @@ struct meminfo {
209 struct membank bank[NR_BANKS]; 209 struct membank bank[NR_BANKS];
210}; 210};
211 211
212extern struct meminfo meminfo;
213
212#define for_each_nodebank(iter,mi,no) \ 214#define for_each_nodebank(iter,mi,no) \
213 for (iter = 0; iter < mi->nr_banks; iter++) \ 215 for (iter = 0; iter < (mi)->nr_banks; iter++) \
214 if (mi->bank[iter].node == no) 216 if ((mi)->bank[iter].node == no)
215 217
216#define bank_pfn_start(bank) __phys_to_pfn((bank)->start) 218#define bank_pfn_start(bank) __phys_to_pfn((bank)->start)
217#define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size) 219#define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size)
diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h
index e50c4a39b699..cf4f3aad0fc1 100644
--- a/arch/arm/include/asm/string.h
+++ b/arch/arm/include/asm/string.h
@@ -21,7 +21,6 @@ extern void * memmove(void *, const void *, __kernel_size_t);
21#define __HAVE_ARCH_MEMCHR 21#define __HAVE_ARCH_MEMCHR
22extern void * memchr(const void *, int, __kernel_size_t); 22extern void * memchr(const void *, int, __kernel_size_t);
23 23
24#define __HAVE_ARCH_MEMZERO
25#define __HAVE_ARCH_MEMSET 24#define __HAVE_ARCH_MEMSET
26extern void * memset(void *, int, __kernel_size_t); 25extern void * memset(void *, int, __kernel_size_t);
27 26
@@ -39,12 +38,4 @@ extern void __memzero(void *ptr, __kernel_size_t n);
39 (__p); \ 38 (__p); \
40 }) 39 })
41 40
42#define memzero(p,n) \
43 ({ \
44 void *__p = (p); size_t __n = n; \
45 if ((__n) != 0) \
46 __memzero((__p),(__n)); \
47 (__p); \
48 })
49
50#endif 41#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 568020b34e3e..811be55f338e 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -3,8 +3,6 @@
3 3
4#ifdef __KERNEL__ 4#ifdef __KERNEL__
5 5
6#include <asm/memory.h>
7
8#define CPU_ARCH_UNKNOWN 0 6#define CPU_ARCH_UNKNOWN 0
9#define CPU_ARCH_ARMv3 1 7#define CPU_ARCH_ARMv3 1
10#define CPU_ARCH_ARMv4 2 8#define CPU_ARCH_ARMv4 2
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index e98ec60b3400..7897464e0c24 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -11,7 +11,8 @@
11/* 11/*
12 * User space memory access functions 12 * User space memory access functions
13 */ 13 */
14#include <linux/sched.h> 14#include <linux/string.h>
15#include <linux/thread_info.h>
15#include <asm/errno.h> 16#include <asm/errno.h>
16#include <asm/memory.h> 17#include <asm/memory.h>
17#include <asm/domain.h> 18#include <asm/domain.h>
@@ -400,7 +401,7 @@ static inline unsigned long __must_check copy_from_user(void *to, const void __u
400 if (access_ok(VERIFY_READ, from, n)) 401 if (access_ok(VERIFY_READ, from, n))
401 n = __copy_from_user(to, from, n); 402 n = __copy_from_user(to, from, n);
402 else /* security hole - plug it */ 403 else /* security hole - plug it */
403 memzero(to, n); 404 memset(to, 0, n);
404 return n; 405 return n;
405} 406}
406 407
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index c74f766ffc12..53d0037a1e9d 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -8,6 +8,7 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10#include <linux/module.h> 10#include <linux/module.h>
11#include <linux/sched.h>
11#include <linux/string.h> 12#include <linux/string.h>
12#include <linux/cryptohash.h> 13#include <linux/cryptohash.h>
13#include <linux/delay.h> 14#include <linux/delay.h>
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 1f1eecca7f55..4f6ae06d0855 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -59,7 +59,7 @@ static int __init fpe_setup(char *line)
59__setup("fpe=", fpe_setup); 59__setup("fpe=", fpe_setup);
60#endif 60#endif
61 61
62extern void paging_init(struct meminfo *, struct machine_desc *desc); 62extern void paging_init(struct machine_desc *desc);
63extern void reboot_setup(char *str); 63extern void reboot_setup(char *str);
64extern void _text, _etext, __data_start, _edata, _end; 64extern void _text, _etext, __data_start, _edata, _end;
65 65
@@ -112,7 +112,6 @@ static struct stack stacks[NR_CPUS];
112char elf_platform[ELF_PLATFORM_SIZE]; 112char elf_platform[ELF_PLATFORM_SIZE];
113EXPORT_SYMBOL(elf_platform); 113EXPORT_SYMBOL(elf_platform);
114 114
115static struct meminfo meminfo __initdata = { 0, };
116static const char *cpu_name; 115static const char *cpu_name;
117static const char *machine_name; 116static const char *machine_name;
118static char __initdata command_line[COMMAND_LINE_SIZE]; 117static char __initdata command_line[COMMAND_LINE_SIZE];
@@ -367,21 +366,34 @@ static struct machine_desc * __init setup_machine(unsigned int nr)
367 return list; 366 return list;
368} 367}
369 368
370static void __init arm_add_memory(unsigned long start, unsigned long size) 369static int __init arm_add_memory(unsigned long start, unsigned long size)
371{ 370{
372 struct membank *bank; 371 struct membank *bank = &meminfo.bank[meminfo.nr_banks];
372
373 if (meminfo.nr_banks >= NR_BANKS) {
374 printk(KERN_CRIT "NR_BANKS too low, "
375 "ignoring memory at %#lx\n", start);
376 return -EINVAL;
377 }
373 378
374 /* 379 /*
375 * Ensure that start/size are aligned to a page boundary. 380 * Ensure that start/size are aligned to a page boundary.
376 * Size is appropriately rounded down, start is rounded up. 381 * Size is appropriately rounded down, start is rounded up.
377 */ 382 */
378 size -= start & ~PAGE_MASK; 383 size -= start & ~PAGE_MASK;
379
380 bank = &meminfo.bank[meminfo.nr_banks++];
381
382 bank->start = PAGE_ALIGN(start); 384 bank->start = PAGE_ALIGN(start);
383 bank->size = size & PAGE_MASK; 385 bank->size = size & PAGE_MASK;
384 bank->node = PHYS_TO_NID(start); 386 bank->node = PHYS_TO_NID(start);
387
388 /*
389 * Check whether this memory region has non-zero size or
390 * invalid node number.
391 */
392 if (bank->size == 0 || bank->node >= MAX_NUMNODES)
393 return -EINVAL;
394
395 meminfo.nr_banks++;
396 return 0;
385} 397}
386 398
387/* 399/*
@@ -539,14 +551,7 @@ __tagtable(ATAG_CORE, parse_tag_core);
539 551
540static int __init parse_tag_mem32(const struct tag *tag) 552static int __init parse_tag_mem32(const struct tag *tag)
541{ 553{
542 if (meminfo.nr_banks >= NR_BANKS) { 554 return arm_add_memory(tag->u.mem.start, tag->u.mem.size);
543 printk(KERN_WARNING
544 "Ignoring memory bank 0x%08x size %dKB\n",
545 tag->u.mem.start, tag->u.mem.size / 1024);
546 return -EINVAL;
547 }
548 arm_add_memory(tag->u.mem.start, tag->u.mem.size);
549 return 0;
550} 555}
551 556
552__tagtable(ATAG_MEM, parse_tag_mem32); 557__tagtable(ATAG_MEM, parse_tag_mem32);
@@ -718,7 +723,7 @@ void __init setup_arch(char **cmdline_p)
718 memcpy(boot_command_line, from, COMMAND_LINE_SIZE); 723 memcpy(boot_command_line, from, COMMAND_LINE_SIZE);
719 boot_command_line[COMMAND_LINE_SIZE-1] = '\0'; 724 boot_command_line[COMMAND_LINE_SIZE-1] = '\0';
720 parse_cmdline(cmdline_p, from); 725 parse_cmdline(cmdline_p, from);
721 paging_init(&meminfo, mdesc); 726 paging_init(mdesc);
722 request_standard_resources(&meminfo, mdesc); 727 request_standard_resources(&meminfo, mdesc);
723 728
724#ifdef CONFIG_SMP 729#ifdef CONFIG_SMP
@@ -772,6 +777,8 @@ static const char *hwcap_str[] = {
772 "java", 777 "java",
773 "iwmmxt", 778 "iwmmxt",
774 "crunch", 779 "crunch",
780 "thumbee",
781 "neon",
775 NULL 782 NULL
776}; 783};
777 784
diff --git a/arch/arm/kernel/thumbee.c b/arch/arm/kernel/thumbee.c
index df3f6b7ebcea..9cb7aaca159f 100644
--- a/arch/arm/kernel/thumbee.c
+++ b/arch/arm/kernel/thumbee.c
@@ -25,7 +25,7 @@
25/* 25/*
26 * Access to the ThumbEE Handler Base register 26 * Access to the ThumbEE Handler Base register
27 */ 27 */
28static inline unsigned long teehbr_read() 28static inline unsigned long teehbr_read(void)
29{ 29{
30 unsigned long v; 30 unsigned long v;
31 asm("mrc p14, 6, %0, c1, c0, 0\n" : "=r" (v)); 31 asm("mrc p14, 6, %0, c1, c0, 0\n" : "=r" (v));
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 30351cd4560d..866f84a586ff 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -38,7 +38,6 @@ else
38endif 38endif
39 39
40lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o 40lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o
41lib-$(CONFIG_ARCH_CLPS7500) += io-acorn.o
42lib-$(CONFIG_ARCH_L7200) += io-acorn.o 41lib-$(CONFIG_ARCH_L7200) += io-acorn.o
43lib-$(CONFIG_ARCH_SHARK) += io-shark.o 42lib-$(CONFIG_ARCH_SHARK) += io-shark.o
44 43
diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S
index 761eefa76243..650d5923ab83 100644
--- a/arch/arm/lib/memset.S
+++ b/arch/arm/lib/memset.S
@@ -25,7 +25,7 @@
25 add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) 25 add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
26/* 26/*
27 * The pointer is now aligned and the length is adjusted. Try doing the 27 * The pointer is now aligned and the length is adjusted. Try doing the
28 * memzero again. 28 * memset again.
29 */ 29 */
30 30
31ENTRY(memset) 31ENTRY(memset)
diff --git a/arch/arm/mach-aaec2000/include/mach/dma.h b/arch/arm/mach-aaec2000/include/mach/dma.h
deleted file mode 100644
index 2da846c72fe7..000000000000
--- a/arch/arm/mach-aaec2000/include/mach/dma.h
+++ /dev/null
@@ -1,9 +0,0 @@
1/*
2 * arch/arm/mach-aaec2000/include/mach/dma.h
3 *
4 * Copyright (c) 2005 Nicolas Bellido Y Ortega
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
diff --git a/arch/arm/mach-aaec2000/include/mach/io.h b/arch/arm/mach-aaec2000/include/mach/io.h
index c87c24de1110..ab4fe5d20eaf 100644
--- a/arch/arm/mach-aaec2000/include/mach/io.h
+++ b/arch/arm/mach-aaec2000/include/mach/io.h
@@ -6,15 +6,13 @@
6#ifndef __ASM_ARM_ARCH_IO_H 6#ifndef __ASM_ARM_ARCH_IO_H
7#define __ASM_ARM_ARCH_IO_H 7#define __ASM_ARM_ARCH_IO_H
8 8
9#include <mach/hardware.h>
10
11#define IO_SPACE_LIMIT 0xffffffff 9#define IO_SPACE_LIMIT 0xffffffff
12 10
13/* 11/*
14 * We don't actually have real ISA nor PCI buses, but there is so many 12 * We don't actually have real ISA nor PCI buses, but there is so many
15 * drivers out there that might just work if we fake them... 13 * drivers out there that might just work if we fake them...
16 */ 14 */
17#define __io(a) ((void __iomem *)(a)) 15#define __io(a) __typesafe_io(a)
18#define __mem_pci(a) (a) 16#define __mem_pci(a) (a)
19 17
20#endif 18#endif
diff --git a/arch/arm/mach-aaec2000/include/mach/memory.h b/arch/arm/mach-aaec2000/include/mach/memory.h
index 56ae900a482e..c00822543d9f 100644
--- a/arch/arm/mach-aaec2000/include/mach/memory.h
+++ b/arch/arm/mach-aaec2000/include/mach/memory.h
@@ -14,9 +14,6 @@
14 14
15#define PHYS_OFFSET UL(0xf0000000) 15#define PHYS_OFFSET UL(0xf0000000)
16 16
17#define __virt_to_bus(x) __virt_to_phys(x)
18#define __bus_to_virt(x) __phys_to_virt(x)
19
20/* 17/*
21 * The nodes are the followings: 18 * The nodes are the followings:
22 * 19 *
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 5aafb2e2ca7a..95dc71aaa668 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -7,36 +7,43 @@ choice
7 7
8config ARCH_AT91RM9200 8config ARCH_AT91RM9200
9 bool "AT91RM9200" 9 bool "AT91RM9200"
10 select CPU_ARM920T
10 select GENERIC_TIME 11 select GENERIC_TIME
11 select GENERIC_CLOCKEVENTS 12 select GENERIC_CLOCKEVENTS
12 13
13config ARCH_AT91SAM9260 14config ARCH_AT91SAM9260
14 bool "AT91SAM9260 or AT91SAM9XE" 15 bool "AT91SAM9260 or AT91SAM9XE"
16 select CPU_ARM926T
15 select GENERIC_TIME 17 select GENERIC_TIME
16 select GENERIC_CLOCKEVENTS 18 select GENERIC_CLOCKEVENTS
17 19
18config ARCH_AT91SAM9261 20config ARCH_AT91SAM9261
19 bool "AT91SAM9261" 21 bool "AT91SAM9261"
22 select CPU_ARM926T
20 select GENERIC_TIME 23 select GENERIC_TIME
21 select GENERIC_CLOCKEVENTS 24 select GENERIC_CLOCKEVENTS
22 25
23config ARCH_AT91SAM9263 26config ARCH_AT91SAM9263
24 bool "AT91SAM9263" 27 bool "AT91SAM9263"
28 select CPU_ARM926T
25 select GENERIC_TIME 29 select GENERIC_TIME
26 select GENERIC_CLOCKEVENTS 30 select GENERIC_CLOCKEVENTS
27 31
28config ARCH_AT91SAM9RL 32config ARCH_AT91SAM9RL
29 bool "AT91SAM9RL" 33 bool "AT91SAM9RL"
34 select CPU_ARM926T
30 select GENERIC_TIME 35 select GENERIC_TIME
31 select GENERIC_CLOCKEVENTS 36 select GENERIC_CLOCKEVENTS
32 37
33config ARCH_AT91SAM9G20 38config ARCH_AT91SAM9G20
34 bool "AT91SAM9G20" 39 bool "AT91SAM9G20"
40 select CPU_ARM926T
35 select GENERIC_TIME 41 select GENERIC_TIME
36 select GENERIC_CLOCKEVENTS 42 select GENERIC_CLOCKEVENTS
37 43
38config ARCH_AT91CAP9 44config ARCH_AT91CAP9
39 bool "AT91CAP9" 45 bool "AT91CAP9"
46 select CPU_ARM926T
40 select GENERIC_TIME 47 select GENERIC_TIME
41 select GENERIC_CLOCKEVENTS 48 select GENERIC_CLOCKEVENTS
42 49
diff --git a/arch/arm/mach-at91/include/mach/dma.h b/arch/arm/mach-at91/include/mach/dma.h
deleted file mode 100644
index e4f90c177616..000000000000
--- a/arch/arm/mach-at91/include/mach/dma.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/dma.h
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
index 1611bd03f528..0b0cccc46e68 100644
--- a/arch/arm/mach-at91/include/mach/io.h
+++ b/arch/arm/mach-at91/include/mach/io.h
@@ -23,8 +23,8 @@
23 23
24#define IO_SPACE_LIMIT 0xFFFFFFFF 24#define IO_SPACE_LIMIT 0xFFFFFFFF
25 25
26#define __io(a) ((void __iomem *)(a)) 26#define __io(a) __typesafe_io(a)
27#define __mem_pci(a) (a) 27#define __mem_pci(a) (a)
28 28
29 29
30#ifndef __ASSEMBLY__ 30#ifndef __ASSEMBLY__
diff --git a/arch/arm/mach-at91/include/mach/memory.h b/arch/arm/mach-at91/include/mach/memory.h
index 9dd1b8c79b08..14f4ef4b6a9e 100644
--- a/arch/arm/mach-at91/include/mach/memory.h
+++ b/arch/arm/mach-at91/include/mach/memory.h
@@ -25,15 +25,4 @@
25 25
26#define PHYS_OFFSET (AT91_SDRAM_BASE) 26#define PHYS_OFFSET (AT91_SDRAM_BASE)
27 27
28
29/*
30 * Virtual view <-> DMA view memory address translations
31 * virt_to_bus: Used to translate the virtual address to an
32 * address suitable to be passed to set_dma_addr
33 * bus_to_virt: Used to convert an address for DMA operations
34 * to an address that the kernel can use.
35 */
36#define __virt_to_bus(x) __virt_to_phys(x)
37#define __bus_to_virt(x) __phys_to_virt(x)
38
39#endif 28#endif
diff --git a/arch/arm/mach-clps711x/include/mach/dma.h b/arch/arm/mach-clps711x/include/mach/dma.h
deleted file mode 100644
index 0d620e869536..000000000000
--- a/arch/arm/mach-clps711x/include/mach/dma.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-clps711x/include/mach/dma.h
3 *
4 * Copyright (C) 1997,1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
diff --git a/arch/arm/mach-clps711x/include/mach/io.h b/arch/arm/mach-clps711x/include/mach/io.h
index 4c8440087679..2e0b3ced8f07 100644
--- a/arch/arm/mach-clps711x/include/mach/io.h
+++ b/arch/arm/mach-clps711x/include/mach/io.h
@@ -20,12 +20,10 @@
20#ifndef __ASM_ARM_ARCH_IO_H 20#ifndef __ASM_ARM_ARCH_IO_H
21#define __ASM_ARM_ARCH_IO_H 21#define __ASM_ARM_ARCH_IO_H
22 22
23#include <mach/hardware.h>
24
25#define IO_SPACE_LIMIT 0xffffffff 23#define IO_SPACE_LIMIT 0xffffffff
26 24
27#define __io(a) ((void __iomem *)(a)) 25#define __io(a) __typesafe_io(a)
28#define __mem_pci(a) (a) 26#define __mem_pci(a) (a)
29 27
30/* 28/*
31 * We don't support ins[lb]/outs[lb]. Make them fault. 29 * We don't support ins[lb]/outs[lb]. Make them fault.
diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h
index 98ec30c97bbe..e522b20bcbc2 100644
--- a/arch/arm/mach-clps711x/include/mach/memory.h
+++ b/arch/arm/mach-clps711x/include/mach/memory.h
@@ -26,25 +26,7 @@
26 */ 26 */
27#define PHYS_OFFSET UL(0xc0000000) 27#define PHYS_OFFSET UL(0xc0000000)
28 28
29/* 29#if !defined(CONFIG_ARCH_CDB89712) && !defined (CONFIG_ARCH_AUTCPU12)
30 * Virtual view <-> DMA view memory address translations
31 * virt_to_bus: Used to translate the virtual address to an
32 * address suitable to be passed to set_dma_addr
33 * bus_to_virt: Used to convert an address for DMA operations
34 * to an address that the kernel can use.
35 */
36
37#if defined(CONFIG_ARCH_CDB89712)
38
39#define __virt_to_bus(x) (x)
40#define __bus_to_virt(x) (x)
41
42#elif defined (CONFIG_ARCH_AUTCPU12)
43
44#define __virt_to_bus(x) (x)
45#define __bus_to_virt(x) (x)
46
47#else
48 30
49#define __virt_to_bus(x) ((x) - PAGE_OFFSET) 31#define __virt_to_bus(x) ((x) - PAGE_OFFSET)
50#define __bus_to_virt(x) ((x) + PAGE_OFFSET) 32#define __bus_to_virt(x) ((x) + PAGE_OFFSET)
diff --git a/arch/arm/mach-clps7500/Makefile b/arch/arm/mach-clps7500/Makefile
deleted file mode 100644
index 4bd8ebd70e7b..000000000000
--- a/arch/arm/mach-clps7500/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7obj-y := core.o
8obj-m :=
9obj-n :=
10obj- :=
11
diff --git a/arch/arm/mach-clps7500/Makefile.boot b/arch/arm/mach-clps7500/Makefile.boot
deleted file mode 100644
index fe16506c1540..000000000000
--- a/arch/arm/mach-clps7500/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y := 0x10008000
2
diff --git a/arch/arm/mach-clps7500/core.c b/arch/arm/mach-clps7500/core.c
deleted file mode 100644
index 7e247c04d41c..000000000000
--- a/arch/arm/mach-clps7500/core.c
+++ /dev/null
@@ -1,395 +0,0 @@
1/*
2 * linux/arch/arm/mach-clps7500/core.c
3 *
4 * Copyright (C) 1998 Russell King
5 * Copyright (C) 1999 Nexus Electronics Ltd
6 *
7 * Extra MM routines for CL7500 architecture
8 */
9#include <linux/kernel.h>
10#include <linux/types.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/list.h>
14#include <linux/sched.h>
15#include <linux/init.h>
16#include <linux/device.h>
17#include <linux/serial_8250.h>
18#include <linux/io.h>
19
20#include <asm/mach/arch.h>
21#include <asm/mach/map.h>
22#include <asm/mach/irq.h>
23#include <asm/mach/time.h>
24
25#include <mach/hardware.h>
26#include <asm/hardware/iomd.h>
27#include <asm/irq.h>
28#include <asm/mach-types.h>
29
30unsigned int vram_size;
31
32static void cl7500_ack_irq_a(unsigned int irq)
33{
34 unsigned int val, mask;
35
36 mask = 1 << irq;
37 val = iomd_readb(IOMD_IRQMASKA);
38 iomd_writeb(val & ~mask, IOMD_IRQMASKA);
39 iomd_writeb(mask, IOMD_IRQCLRA);
40}
41
42static void cl7500_mask_irq_a(unsigned int irq)
43{
44 unsigned int val, mask;
45
46 mask = 1 << irq;
47 val = iomd_readb(IOMD_IRQMASKA);
48 iomd_writeb(val & ~mask, IOMD_IRQMASKA);
49}
50
51static void cl7500_unmask_irq_a(unsigned int irq)
52{
53 unsigned int val, mask;
54
55 mask = 1 << irq;
56 val = iomd_readb(IOMD_IRQMASKA);
57 iomd_writeb(val | mask, IOMD_IRQMASKA);
58}
59
60static struct irq_chip clps7500_a_chip = {
61 .ack = cl7500_ack_irq_a,
62 .mask = cl7500_mask_irq_a,
63 .unmask = cl7500_unmask_irq_a,
64};
65
66static void cl7500_mask_irq_b(unsigned int irq)
67{
68 unsigned int val, mask;
69
70 mask = 1 << (irq & 7);
71 val = iomd_readb(IOMD_IRQMASKB);
72 iomd_writeb(val & ~mask, IOMD_IRQMASKB);
73}
74
75static void cl7500_unmask_irq_b(unsigned int irq)
76{
77 unsigned int val, mask;
78
79 mask = 1 << (irq & 7);
80 val = iomd_readb(IOMD_IRQMASKB);
81 iomd_writeb(val | mask, IOMD_IRQMASKB);
82}
83
84static struct irq_chip clps7500_b_chip = {
85 .ack = cl7500_mask_irq_b,
86 .mask = cl7500_mask_irq_b,
87 .unmask = cl7500_unmask_irq_b,
88};
89
90static void cl7500_mask_irq_c(unsigned int irq)
91{
92 unsigned int val, mask;
93
94 mask = 1 << (irq & 7);
95 val = iomd_readb(IOMD_IRQMASKC);
96 iomd_writeb(val & ~mask, IOMD_IRQMASKC);
97}
98
99static void cl7500_unmask_irq_c(unsigned int irq)
100{
101 unsigned int val, mask;
102
103 mask = 1 << (irq & 7);
104 val = iomd_readb(IOMD_IRQMASKC);
105 iomd_writeb(val | mask, IOMD_IRQMASKC);
106}
107
108static struct irq_chip clps7500_c_chip = {
109 .ack = cl7500_mask_irq_c,
110 .mask = cl7500_mask_irq_c,
111 .unmask = cl7500_unmask_irq_c,
112};
113
114static void cl7500_mask_irq_d(unsigned int irq)
115{
116 unsigned int val, mask;
117
118 mask = 1 << (irq & 7);
119 val = iomd_readb(IOMD_IRQMASKD);
120 iomd_writeb(val & ~mask, IOMD_IRQMASKD);
121}
122
123static void cl7500_unmask_irq_d(unsigned int irq)
124{
125 unsigned int val, mask;
126
127 mask = 1 << (irq & 7);
128 val = iomd_readb(IOMD_IRQMASKD);
129 iomd_writeb(val | mask, IOMD_IRQMASKD);
130}
131
132static struct irq_chip clps7500_d_chip = {
133 .ack = cl7500_mask_irq_d,
134 .mask = cl7500_mask_irq_d,
135 .unmask = cl7500_unmask_irq_d,
136};
137
138static void cl7500_mask_irq_dma(unsigned int irq)
139{
140 unsigned int val, mask;
141
142 mask = 1 << (irq & 7);
143 val = iomd_readb(IOMD_DMAMASK);
144 iomd_writeb(val & ~mask, IOMD_DMAMASK);
145}
146
147static void cl7500_unmask_irq_dma(unsigned int irq)
148{
149 unsigned int val, mask;
150
151 mask = 1 << (irq & 7);
152 val = iomd_readb(IOMD_DMAMASK);
153 iomd_writeb(val | mask, IOMD_DMAMASK);
154}
155
156static struct irq_chip clps7500_dma_chip = {
157 .ack = cl7500_mask_irq_dma,
158 .mask = cl7500_mask_irq_dma,
159 .unmask = cl7500_unmask_irq_dma,
160};
161
162static void cl7500_mask_irq_fiq(unsigned int irq)
163{
164 unsigned int val, mask;
165
166 mask = 1 << (irq & 7);
167 val = iomd_readb(IOMD_FIQMASK);
168 iomd_writeb(val & ~mask, IOMD_FIQMASK);
169}
170
171static void cl7500_unmask_irq_fiq(unsigned int irq)
172{
173 unsigned int val, mask;
174
175 mask = 1 << (irq & 7);
176 val = iomd_readb(IOMD_FIQMASK);
177 iomd_writeb(val | mask, IOMD_FIQMASK);
178}
179
180static struct irq_chip clps7500_fiq_chip = {
181 .ack = cl7500_mask_irq_fiq,
182 .mask = cl7500_mask_irq_fiq,
183 .unmask = cl7500_unmask_irq_fiq,
184};
185
186static void cl7500_no_action(unsigned int irq)
187{
188}
189
190static struct irq_chip clps7500_no_chip = {
191 .ack = cl7500_no_action,
192 .mask = cl7500_no_action,
193 .unmask = cl7500_no_action,
194};
195
196static struct irqaction irq_isa = {
197 .handler = no_action,
198 .mask = CPU_MASK_NONE,
199 .name = "isa",
200};
201
202static void __init clps7500_init_irq(void)
203{
204 unsigned int irq, flags;
205
206 iomd_writeb(0, IOMD_IRQMASKA);
207 iomd_writeb(0, IOMD_IRQMASKB);
208 iomd_writeb(0, IOMD_FIQMASK);
209 iomd_writeb(0, IOMD_DMAMASK);
210
211 for (irq = 0; irq < NR_IRQS; irq++) {
212 flags = IRQF_VALID;
213
214 if (irq <= 6 || (irq >= 9 && irq <= 15) ||
215 (irq >= 48 && irq <= 55))
216 flags |= IRQF_PROBE;
217
218 switch (irq) {
219 case 0 ... 7:
220 set_irq_chip(irq, &clps7500_a_chip);
221 set_irq_handler(irq, handle_level_irq);
222 set_irq_flags(irq, flags);
223 break;
224
225 case 8 ... 15:
226 set_irq_chip(irq, &clps7500_b_chip);
227 set_irq_handler(irq, handle_level_irq);
228 set_irq_flags(irq, flags);
229 break;
230
231 case 16 ... 22:
232 set_irq_chip(irq, &clps7500_dma_chip);
233 set_irq_handler(irq, handle_level_irq);
234 set_irq_flags(irq, flags);
235 break;
236
237 case 24 ... 31:
238 set_irq_chip(irq, &clps7500_c_chip);
239 set_irq_handler(irq, handle_level_irq);
240 set_irq_flags(irq, flags);
241 break;
242
243 case 40 ... 47:
244 set_irq_chip(irq, &clps7500_d_chip);
245 set_irq_handler(irq, handle_level_irq);
246 set_irq_flags(irq, flags);
247 break;
248
249 case 48 ... 55:
250 set_irq_chip(irq, &clps7500_no_chip);
251 set_irq_handler(irq, handle_level_irq);
252 set_irq_flags(irq, flags);
253 break;
254
255 case 64 ... 72:
256 set_irq_chip(irq, &clps7500_fiq_chip);
257 set_irq_handler(irq, handle_level_irq);
258 set_irq_flags(irq, flags);
259 break;
260 }
261 }
262
263 setup_irq(IRQ_ISA, &irq_isa);
264}
265
266static struct map_desc cl7500_io_desc[] __initdata = {
267 { /* IO space */
268 .virtual = (unsigned long)IO_BASE,
269 .pfn = __phys_to_pfn(IO_START),
270 .length = IO_SIZE,
271 .type = MT_DEVICE
272 }, { /* ISA space */
273 .virtual = ISA_BASE,
274 .pfn = __phys_to_pfn(ISA_START),
275 .length = ISA_SIZE,
276 .type = MT_DEVICE
277 }, { /* Flash */
278 .virtual = CLPS7500_FLASH_BASE,
279 .pfn = __phys_to_pfn(CLPS7500_FLASH_START),
280 .length = CLPS7500_FLASH_SIZE,
281 .type = MT_DEVICE
282 }, { /* LED */
283 .virtual = LED_BASE,
284 .pfn = __phys_to_pfn(LED_START),
285 .length = LED_SIZE,
286 .type = MT_DEVICE
287 }
288};
289
290static void __init clps7500_map_io(void)
291{
292 iotable_init(cl7500_io_desc, ARRAY_SIZE(cl7500_io_desc));
293}
294
295extern void ioctime_init(void);
296extern unsigned long ioc_timer_gettimeoffset(void);
297
298static irqreturn_t
299clps7500_timer_interrupt(int irq, void *dev_id)
300{
301 timer_tick();
302
303 /* Why not using do_leds interface?? */
304 {
305 /* Twinkle the lights. */
306 static int count, state = 0xff00;
307 if (count-- == 0) {
308 state ^= 0x100;
309 count = 25;
310 *((volatile unsigned int *)LED_ADDRESS) = state;
311 }
312 }
313
314 return IRQ_HANDLED;
315}
316
317static struct irqaction clps7500_timer_irq = {
318 .name = "CLPS7500 Timer Tick",
319 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
320 .handler = clps7500_timer_interrupt,
321};
322
323/*
324 * Set up timer interrupt.
325 */
326static void __init clps7500_timer_init(void)
327{
328 ioctime_init();
329 setup_irq(IRQ_TIMER, &clps7500_timer_irq);
330}
331
332static struct sys_timer clps7500_timer = {
333 .init = clps7500_timer_init,
334 .offset = ioc_timer_gettimeoffset,
335};
336
337static struct plat_serial8250_port serial_platform_data[] = {
338 {
339 .mapbase = 0x03010fe0,
340 .irq = 10,
341 .uartclk = 1843200,
342 .regshift = 2,
343 .iotype = UPIO_MEM,
344 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
345 },
346 {
347 .mapbase = 0x03010be0,
348 .irq = 0,
349 .uartclk = 1843200,
350 .regshift = 2,
351 .iotype = UPIO_MEM,
352 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
353 },
354 {
355 .iobase = ISASLOT_IO + 0x2e8,
356 .irq = 41,
357 .uartclk = 1843200,
358 .regshift = 0,
359 .iotype = UPIO_PORT,
360 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
361 },
362 {
363 .iobase = ISASLOT_IO + 0x3e8,
364 .irq = 40,
365 .uartclk = 1843200,
366 .regshift = 0,
367 .iotype = UPIO_PORT,
368 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
369 },
370 { },
371};
372
373static struct platform_device serial_device = {
374 .name = "serial8250",
375 .id = PLAT8250_DEV_PLATFORM,
376 .dev = {
377 .platform_data = serial_platform_data,
378 },
379};
380
381static void __init clps7500_init(void)
382{
383 platform_device_register(&serial_device);
384}
385
386MACHINE_START(CLPS7500, "CL-PS7500")
387 /* Maintainer: Philip Blundell */
388 .phys_io = 0x03000000,
389 .io_pg_offst = ((0xe0000000) >> 18) & 0xfffc,
390 .map_io = clps7500_map_io,
391 .init_irq = clps7500_init_irq,
392 .init_machine = clps7500_init,
393 .timer = &clps7500_timer,
394MACHINE_END
395
diff --git a/arch/arm/mach-clps7500/include/mach/acornfb.h b/arch/arm/mach-clps7500/include/mach/acornfb.h
deleted file mode 100644
index aea6330c9745..000000000000
--- a/arch/arm/mach-clps7500/include/mach/acornfb.h
+++ /dev/null
@@ -1,33 +0,0 @@
1#define acornfb_valid_pixrate(var) (var->pixclock >= 39325 && var->pixclock <= 40119)
2
3static inline void
4acornfb_vidc20_find_rates(struct vidc_timing *vidc,
5 struct fb_var_screeninfo *var)
6{
7 u_int bandwidth;
8
9 vidc->control |= VIDC20_CTRL_PIX_CK;
10
11 /* Calculate bandwidth */
12 bandwidth = var->pixclock * 8 / var->bits_per_pixel;
13
14 /* Encode bandwidth as VIDC20 setting */
15 if (bandwidth > 16667*2)
16 vidc->control |= VIDC20_CTRL_FIFO_16;
17 else if (bandwidth > 13333*2)
18 vidc->control |= VIDC20_CTRL_FIFO_20;
19 else if (bandwidth > 11111*2)
20 vidc->control |= VIDC20_CTRL_FIFO_24;
21 else
22 vidc->control |= VIDC20_CTRL_FIFO_28;
23
24 vidc->pll_ctl = 0x2020;
25}
26
27#ifdef CONFIG_CHRONTEL_7003
28#define acornfb_default_control() VIDC20_CTRL_PIX_HCLK
29#else
30#define acornfb_default_control() VIDC20_CTRL_PIX_VCLK
31#endif
32
33#define acornfb_default_econtrol() VIDC20_ECTL_DAC | VIDC20_ECTL_REG(3) | VIDC20_ECTL_ECK
diff --git a/arch/arm/mach-clps7500/include/mach/debug-macro.S b/arch/arm/mach-clps7500/include/mach/debug-macro.S
deleted file mode 100644
index af4104e7e84a..000000000000
--- a/arch/arm/mach-clps7500/include/mach/debug-macro.S
+++ /dev/null
@@ -1,21 +0,0 @@
1/* arch/arm/mach-clps7500/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart,rx
15 mov \rx, #0xe0000000
16 orr \rx, \rx, #0x00010000
17 orr \rx, \rx, #0x00000be0
18 .endm
19
20#define UART_SHIFT 2
21#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-clps7500/include/mach/dma.h b/arch/arm/mach-clps7500/include/mach/dma.h
deleted file mode 100644
index 63fcde505498..000000000000
--- a/arch/arm/mach-clps7500/include/mach/dma.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/dma.h
3 *
4 * Copyright (C) 1999 Nexus Electronics Ltd.
5 */
6
7#ifndef __ASM_ARCH_DMA_H
8#define __ASM_ARCH_DMA_H
9
10/* DMA is not yet implemented! It should be the same as acorn, copy over.. */
11
12/*
13 * This is the maximum DMA address that can be DMAd to.
14 * There should not be more than (0xd0000000 - 0xc0000000)
15 * bytes of RAM.
16 */
17#define MAX_DMA_ADDRESS 0xd0000000
18
19#define DMA_S0 0
20
21#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-clps7500/include/mach/entry-macro.S b/arch/arm/mach-clps7500/include/mach/entry-macro.S
deleted file mode 100644
index 4e7e54144093..000000000000
--- a/arch/arm/mach-clps7500/include/mach/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
1#include <mach/hardware.h>
2#include <asm/hardware/entry-macro-iomd.S>
3
4 .equ ioc_base_high, IOC_BASE & 0xff000000
5 .equ ioc_base_low, IOC_BASE & 0x00ff0000
6
7 .macro get_irqnr_preamble, base, tmp
8 mov \base, #ioc_base_high @ point at IOC
9 .if ioc_base_low
10 orr \base, \base, #ioc_base_low
11 .endif
12 .endm
13
14 .macro arch_ret_to_user, tmp1, tmp2
15 .endm
16
diff --git a/arch/arm/mach-clps7500/include/mach/hardware.h b/arch/arm/mach-clps7500/include/mach/hardware.h
deleted file mode 100644
index a6ad1d44badf..000000000000
--- a/arch/arm/mach-clps7500/include/mach/hardware.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/hardware.h
3 *
4 * Copyright (C) 1996-1999 Russell King.
5 * Copyright (C) 1999 Nexus Electronics Ltd.
6 *
7 * This file contains the hardware definitions of the
8 * CL7500 evaluation board.
9 */
10#ifndef __ASM_ARCH_HARDWARE_H
11#define __ASM_ARCH_HARDWARE_H
12
13#include <mach/memory.h>
14#include <asm/hardware/iomd.h>
15
16#ifdef __ASSEMBLY__
17#define IOMEM(x) x
18#else
19#define IOMEM(x) ((void __iomem *)(x))
20#endif
21
22/*
23 * What hardware must be present
24 */
25#define HAS_IOMD
26#define HAS_VIDC20
27
28/* Hardware addresses of major areas.
29 * *_START is the physical address
30 * *_SIZE is the size of the region
31 * *_BASE is the virtual address
32 */
33
34#define IO_START 0x03000000 /* I/O */
35#define IO_SIZE 0x01000000
36#define IO_BASE IOMEM(0xe0000000)
37
38#define ISA_START 0x0c000000 /* ISA */
39#define ISA_SIZE 0x00010000
40#define ISA_BASE 0xe1000000
41
42#define CLPS7500_FLASH_START 0x01000000 /* XXX */
43#define CLPS7500_FLASH_SIZE 0x01000000
44#define CLPS7500_FLASH_BASE 0xe2000000
45
46#define LED_START 0x0302B000
47#define LED_SIZE 0x00001000
48#define LED_BASE 0xe3000000
49#define LED_ADDRESS (LED_BASE + 0xa00)
50
51/* Let's define SCREEN_START for CL7500, even though it's a lie. */
52#define SCREEN_START 0x02000000 /* VRAM */
53#define SCREEN_END 0xdfc00000
54#define SCREEN_BASE 0xdf800000
55
56#define VIDC_BASE (void __iomem *)0xe0400000
57#define IOMD_BASE IOMEM(0xe0200000)
58#define IOC_BASE IOMEM(0xe0200000)
59#define FLOPPYDMA_BASE IOMEM(0xe002a000)
60#define PCIO_BASE IOMEM(0xe0010000)
61
62#define vidc_writel(val) __raw_writel(val, VIDC_BASE)
63
64/* in/out bias for the ISA slot region */
65#define ISASLOT_IO 0x80400000
66
67#endif
diff --git a/arch/arm/mach-clps7500/include/mach/io.h b/arch/arm/mach-clps7500/include/mach/io.h
deleted file mode 100644
index 2ff2860889ed..000000000000
--- a/arch/arm/mach-clps7500/include/mach/io.h
+++ /dev/null
@@ -1,255 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/io.h
3 * from arch/arm/mach-rpc/include/mach/io.h
4 *
5 * Copyright (C) 1997 Russell King
6 *
7 * Modifications:
8 * 06-Dec-1997 RMK Created.
9 */
10#ifndef __ASM_ARM_ARCH_IO_H
11#define __ASM_ARM_ARCH_IO_H
12
13#include <mach/hardware.h>
14
15#define IO_SPACE_LIMIT 0xffffffff
16
17/*
18 * GCC is totally crap at loading/storing data. We try to persuade it
19 * to do the right thing by using these whereever possible instead of
20 * the above.
21 */
22#define __arch_base_getb(b,o) \
23 ({ \
24 unsigned int v, r = (b); \
25 __asm__ __volatile__( \
26 "ldrb %0, [%1, %2]" \
27 : "=r" (v) \
28 : "r" (r), "Ir" (o)); \
29 v; \
30 })
31
32#define __arch_base_getl(b,o) \
33 ({ \
34 unsigned int v, r = (b); \
35 __asm__ __volatile__( \
36 "ldr %0, [%1, %2]" \
37 : "=r" (v) \
38 : "r" (r), "Ir" (o)); \
39 v; \
40 })
41
42#define __arch_base_putb(v,b,o) \
43 ({ \
44 unsigned int r = (b); \
45 __asm__ __volatile__( \
46 "strb %0, [%1, %2]" \
47 : \
48 : "r" (v), "r" (r), "Ir" (o)); \
49 })
50
51#define __arch_base_putl(v,b,o) \
52 ({ \
53 unsigned int r = (b); \
54 __asm__ __volatile__( \
55 "str %0, [%1, %2]" \
56 : \
57 : "r" (v), "r" (r), "Ir" (o)); \
58 })
59
60/*
61 * We use two different types of addressing - PC style addresses, and ARM
62 * addresses. PC style accesses the PC hardware with the normal PC IO
63 * addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+
64 * and are translated to the start of IO. Note that all addresses are
65 * shifted left!
66 */
67#define __PORT_PCIO(x) (!((x) & 0x80000000))
68
69/*
70 * Dynamic IO functions - let the compiler
71 * optimize the expressions
72 */
73static inline void __outb (unsigned int value, unsigned int port)
74{
75 unsigned long temp;
76 __asm__ __volatile__(
77 "tst %2, #0x80000000\n\t"
78 "mov %0, %4\n\t"
79 "addeq %0, %0, %3\n\t"
80 "strb %1, [%0, %2, lsl #2] @ outb"
81 : "=&r" (temp)
82 : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
83 : "cc");
84}
85
86static inline void __outw (unsigned int value, unsigned int port)
87{
88 unsigned long temp;
89 __asm__ __volatile__(
90 "tst %2, #0x80000000\n\t"
91 "mov %0, %4\n\t"
92 "addeq %0, %0, %3\n\t"
93 "str %1, [%0, %2, lsl #2] @ outw"
94 : "=&r" (temp)
95 : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
96 : "cc");
97}
98
99static inline void __outl (unsigned int value, unsigned int port)
100{
101 unsigned long temp;
102 __asm__ __volatile__(
103 "tst %2, #0x80000000\n\t"
104 "mov %0, %4\n\t"
105 "addeq %0, %0, %3\n\t"
106 "str %1, [%0, %2, lsl #2] @ outl"
107 : "=&r" (temp)
108 : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
109 : "cc");
110}
111
112#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
113static inline unsigned sz __in##fnsuffix (unsigned int port) \
114{ \
115 unsigned long temp, value; \
116 __asm__ __volatile__( \
117 "tst %2, #0x80000000\n\t" \
118 "mov %0, %4\n\t" \
119 "addeq %0, %0, %3\n\t" \
120 "ldr" instr " %1, [%0, %2, lsl #2] @ in" #fnsuffix \
121 : "=&r" (temp), "=r" (value) \
122 : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \
123 : "cc"); \
124 return (unsigned sz)value; \
125}
126
127static inline unsigned int __ioaddr (unsigned int port) \
128{ \
129 if (__PORT_PCIO(port)) \
130 return (unsigned int)(PCIO_BASE + (port << 2)); \
131 else \
132 return (unsigned int)(IO_BASE + (port << 2)); \
133}
134
135#define DECLARE_IO(sz,fnsuffix,instr) \
136 DECLARE_DYN_IN(sz,fnsuffix,instr)
137
138DECLARE_IO(char,b,"b")
139DECLARE_IO(short,w,"")
140DECLARE_IO(int,l,"")
141
142#undef DECLARE_IO
143#undef DECLARE_DYN_IN
144
145/*
146 * Constant address IO functions
147 *
148 * These have to be macros for the 'J' constraint to work -
149 * +/-4096 immediate operand.
150 */
151#define __outbc(value,port) \
152({ \
153 if (__PORT_PCIO((port))) \
154 __asm__ __volatile__( \
155 "strb %0, [%1, %2] @ outbc" \
156 : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
157 else \
158 __asm__ __volatile__( \
159 "strb %0, [%1, %2] @ outbc" \
160 : : "r" (value), "r" (IO_BASE), "r" ((port) << 2)); \
161})
162
163#define __inbc(port) \
164({ \
165 unsigned char result; \
166 if (__PORT_PCIO((port))) \
167 __asm__ __volatile__( \
168 "ldrb %0, [%1, %2] @ inbc" \
169 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
170 else \
171 __asm__ __volatile__( \
172 "ldrb %0, [%1, %2] @ inbc" \
173 : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
174 result; \
175})
176
177#define __outwc(value,port) \
178({ \
179 unsigned long v = value; \
180 if (__PORT_PCIO((port))) \
181 __asm__ __volatile__( \
182 "str %0, [%1, %2] @ outwc" \
183 : : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
184 else \
185 __asm__ __volatile__( \
186 "str %0, [%1, %2] @ outwc" \
187 : : "r" (v|v<<16), "r" (IO_BASE), "r" ((port) << 2)); \
188})
189
190#define __inwc(port) \
191({ \
192 unsigned short result; \
193 if (__PORT_PCIO((port))) \
194 __asm__ __volatile__( \
195 "ldr %0, [%1, %2] @ inwc" \
196 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
197 else \
198 __asm__ __volatile__( \
199 "ldr %0, [%1, %2] @ inwc" \
200 : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
201 result & 0xffff; \
202})
203
204#define __outlc(value,port) \
205({ \
206 unsigned long v = value; \
207 if (__PORT_PCIO((port))) \
208 __asm__ __volatile__( \
209 "str %0, [%1, %2] @ outlc" \
210 : : "r" (v), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
211 else \
212 __asm__ __volatile__( \
213 "str %0, [%1, %2] @ outlc" \
214 : : "r" (v), "r" (IO_BASE), "r" ((port) << 2)); \
215})
216
217#define __inlc(port) \
218({ \
219 unsigned long result; \
220 if (__PORT_PCIO((port))) \
221 __asm__ __volatile__( \
222 "ldr %0, [%1, %2] @ inlc" \
223 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
224 else \
225 __asm__ __volatile__( \
226 "ldr %0, [%1, %2] @ inlc" \
227 : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
228 result; \
229})
230
231#define __ioaddrc(port) \
232 (__PORT_PCIO((port)) ? PCIO_BASE + ((port) << 2) : IO_BASE + ((port) << 2))
233
234#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
235#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
236#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p))
237#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
238#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
239#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
240#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p))
241/* the following macro is deprecated */
242#define ioaddr(port) __ioaddr((port))
243
244#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l)
245#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l)
246
247#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l)
248#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
249
250/*
251 * 1:1 mapping for ioremapped regions.
252 */
253#define __mem_pci(x) (x)
254
255#endif
diff --git a/arch/arm/mach-clps7500/include/mach/irq.h b/arch/arm/mach-clps7500/include/mach/irq.h
deleted file mode 100644
index d02fcf28ee05..000000000000
--- a/arch/arm/mach-clps7500/include/mach/irq.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/irq.h
3 *
4 * Copyright (C) 1996 Russell King
5 * Copyright (C) 1999, 2001 Nexus Electronics Ltd.
6 *
7 * Changelog:
8 * 10-10-1996 RMK Brought up to date with arch-sa110eval
9 * 22-08-1998 RMK Restructured IRQ routines
10 * 11-08-1999 PJB Created ARM7500 version, derived from RiscPC code
11 */
12
13#include <linux/io.h>
14#include <asm/hardware/iomd.h>
15
16static inline int fixup_irq(unsigned int irq)
17{
18 if (irq == IRQ_ISA) {
19 int isabits = *((volatile unsigned int *)0xe002b700);
20 if (isabits == 0) {
21 printk("Spurious ISA IRQ!\n");
22 return irq;
23 }
24 irq = IRQ_ISA_BASE;
25 while (!(isabits & 1)) {
26 irq++;
27 isabits >>= 1;
28 }
29 }
30
31 return irq;
32}
diff --git a/arch/arm/mach-clps7500/include/mach/irqs.h b/arch/arm/mach-clps7500/include/mach/irqs.h
deleted file mode 100644
index bee66b487f59..000000000000
--- a/arch/arm/mach-clps7500/include/mach/irqs.h
+++ /dev/null
@@ -1,66 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/irqs.h
3 *
4 * Copyright (C) 1999 Nexus Electronics Ltd
5 */
6
7#define IRQ_INT2 0
8#define IRQ_INT1 2
9#define IRQ_VSYNCPULSE 3
10#define IRQ_POWERON 4
11#define IRQ_TIMER0 5
12#define IRQ_TIMER1 6
13#define IRQ_FORCE 7
14#define IRQ_INT8 8
15#define IRQ_ISA 9
16#define IRQ_INT6 10
17#define IRQ_INT5 11
18#define IRQ_INT4 12
19#define IRQ_INT3 13
20#define IRQ_KEYBOARDTX 14
21#define IRQ_KEYBOARDRX 15
22
23#define IRQ_DMA0 16
24#define IRQ_DMA1 17
25#define IRQ_DMA2 18
26#define IRQ_DMA3 19
27#define IRQ_DMAS0 20
28#define IRQ_DMAS1 21
29
30#define IRQ_IOP0 24
31#define IRQ_IOP1 25
32#define IRQ_IOP2 26
33#define IRQ_IOP3 27
34#define IRQ_IOP4 28
35#define IRQ_IOP5 29
36#define IRQ_IOP6 30
37#define IRQ_IOP7 31
38
39#define IRQ_MOUSERX 40
40#define IRQ_MOUSETX 41
41#define IRQ_ADC 42
42#define IRQ_EVENT1 43
43#define IRQ_EVENT2 44
44
45#define IRQ_ISA_BASE 48
46#define IRQ_ISA_3 48
47#define IRQ_ISA_4 49
48#define IRQ_ISA_5 50
49#define IRQ_ISA_7 51
50#define IRQ_ISA_9 52
51#define IRQ_ISA_10 53
52#define IRQ_ISA_11 54
53#define IRQ_ISA_14 55
54
55#define FIQ_INT9 0
56#define FIQ_INT5 1
57#define FIQ_INT6 4
58#define FIQ_INT8 6
59#define FIQ_FORCE 7
60
61/*
62 * This is the offset of the FIQ "IRQ" numbers
63 */
64#define FIQ_START 64
65
66#define IRQ_TIMER IRQ_TIMER0
diff --git a/arch/arm/mach-clps7500/include/mach/memory.h b/arch/arm/mach-clps7500/include/mach/memory.h
deleted file mode 100644
index 87b32db470c8..000000000000
--- a/arch/arm/mach-clps7500/include/mach/memory.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/memory.h
3 *
4 * Copyright (c) 1996,1997,1998 Russell King.
5 *
6 * Changelog:
7 * 20-Oct-1996 RMK Created
8 * 31-Dec-1997 RMK Fixed definitions to reduce warnings
9 * 11-Jan-1998 RMK Uninlined to reduce hits on cache
10 * 08-Feb-1998 RMK Added __virt_to_bus and __bus_to_virt
11 * 21-Mar-1999 RMK Renamed to memory.h
12 * RMK Added TASK_SIZE and PAGE_OFFSET
13 */
14#ifndef __ASM_ARCH_MEMORY_H
15#define __ASM_ARCH_MEMORY_H
16
17/*
18 * Physical DRAM offset.
19 */
20#define PHYS_OFFSET UL(0x10000000)
21
22/*
23 * These are exactly the same on the RiscPC as the
24 * physical memory view.
25 */
26#define __virt_to_bus(x) __virt_to_phys(x)
27#define __bus_to_virt(x) __phys_to_virt(x)
28
29/*
30 * Cache flushing area - ROM
31 */
32#define FLUSH_BASE_PHYS 0x00000000
33#define FLUSH_BASE 0xdf000000
34
35/*
36 * Sparsemem support. Each section is a maximum of 64MB. The sections
37 * are offset by 128MB and can cover 128MB, so that gives us a maximum
38 * of 29 physmem bits.
39 */
40#define MAX_PHYSMEM_BITS 29
41#define SECTION_SIZE_BITS 26
42
43#endif
diff --git a/arch/arm/mach-clps7500/include/mach/system.h b/arch/arm/mach-clps7500/include/mach/system.h
deleted file mode 100644
index 6d325fbe8b08..000000000000
--- a/arch/arm/mach-clps7500/include/mach/system.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/system.h
3 *
4 * Copyright (c) 1999 Nexus Electronics Ltd.
5 */
6#ifndef __ASM_ARCH_SYSTEM_H
7#define __ASM_ARCH_SYSTEM_H
8
9#include <linux/io.h>
10#include <asm/hardware/iomd.h>
11
12static inline void arch_idle(void)
13{
14 iomd_writeb(0, IOMD_SUSMODE);
15}
16
17#define arch_reset(mode) \
18 do { \
19 iomd_writeb(0, IOMD_ROMCR0); \
20 cpu_reset(0); \
21 } while (0)
22
23#endif
diff --git a/arch/arm/mach-clps7500/include/mach/timex.h b/arch/arm/mach-clps7500/include/mach/timex.h
deleted file mode 100644
index dfaa9b425757..000000000000
--- a/arch/arm/mach-clps7500/include/mach/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/timex.h
3 *
4 * CL7500 architecture timex specifications
5 *
6 * Copyright (C) 1999 Nexus Electronics Ltd
7 */
8
9/*
10 * On the ARM7500, the clock ticks at 2MHz.
11 */
12#define CLOCK_TICK_RATE 2000000
13
diff --git a/arch/arm/mach-clps7500/include/mach/uncompress.h b/arch/arm/mach-clps7500/include/mach/uncompress.h
deleted file mode 100644
index d7d0af4b49fc..000000000000
--- a/arch/arm/mach-clps7500/include/mach/uncompress.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/uncompress.h
3 *
4 * Copyright (C) 1999, 2000 Nexus Electronics Ltd.
5 */
6#define BASE 0x03010000
7#define SERBASE (BASE + (0x2f8 << 2))
8
9static inline void putc(char c)
10{
11 while (!(*((volatile unsigned int *)(SERBASE + 0x14)) & 0x20))
12 barrier();
13
14 *((volatile unsigned int *)(SERBASE)) = c;
15}
16
17static inline void flush(void)
18{
19}
20
21static __inline__ void arch_decomp_setup(void)
22{
23 int baud = 3686400 / (9600 * 32);
24
25 *((volatile unsigned int *)(SERBASE + 0xC)) = 0x80;
26 *((volatile unsigned int *)(SERBASE + 0x0)) = baud & 0xff;
27 *((volatile unsigned int *)(SERBASE + 0x4)) = (baud & 0xff00) >> 8;
28 *((volatile unsigned int *)(SERBASE + 0xC)) = 3; /* 8 bits */
29 *((volatile unsigned int *)(SERBASE + 0x10)) = 3; /* DTR, RTS */
30}
31
32/*
33 * nothing to do
34 */
35#define arch_decomp_wdog()
diff --git a/arch/arm/mach-clps7500/include/mach/vmalloc.h b/arch/arm/mach-clps7500/include/mach/vmalloc.h
deleted file mode 100644
index 8fc5406d1b6d..000000000000
--- a/arch/arm/mach-clps7500/include/mach/vmalloc.h
+++ /dev/null
@@ -1,4 +0,0 @@
1/*
2 * arch/arm/mach-clps7500/include/mach/vmalloc.h
3 */
4#define VMALLOC_END (PAGE_OFFSET + 0x1c000000)
diff --git a/arch/arm/mach-davinci/include/mach/dma.h b/arch/arm/mach-davinci/include/mach/dma.h
deleted file mode 100644
index 8e2f2d0ba667..000000000000
--- a/arch/arm/mach-davinci/include/mach/dma.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * DaVinci DMA definitions
3 *
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef __ASM_ARCH_DMA_H
12#define __ASM_ARCH_DMA_H
13
14#define MAX_DMA_ADDRESS 0xffffffff
15
16#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index b78ee9140496..a48795fd2417 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -29,8 +29,7 @@
29 * We don't actually have real ISA nor PCI buses, but there is so many 29 * We don't actually have real ISA nor PCI buses, but there is so many
30 * drivers out there that might just work if we fake them... 30 * drivers out there that might just work if we fake them...
31 */ 31 */
32#define PCIO_BASE 0 32#define __io(a) __typesafe_io(a)
33#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
34#define __mem_pci(a) (a) 33#define __mem_pci(a) (a)
35#define __mem_isa(a) (a) 34#define __mem_isa(a) (a)
36 35
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index dd1625c23cf4..86c25c7f3ce3 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -52,13 +52,8 @@ __arch_adjust_zones(int node, unsigned long *size, unsigned long *holes)
52 if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes) 52 if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes)
53 53
54#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1) 54#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1)
55#define MAX_DMA_ADDRESS (PAGE_OFFSET + (128<<20))
55 56
56#endif 57#endif
57 58
58/*
59 * Bus address is physical address
60 */
61#define __virt_to_bus(x) __virt_to_phys(x)
62#define __bus_to_virt(x) __phys_to_virt(x)
63
64#endif /* __ASM_ARCH_MEMORY_H */ 59#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-davinci/include/mach/vmalloc.h b/arch/arm/mach-davinci/include/mach/vmalloc.h
index b98bd9e92fd6..ad51625b6609 100644
--- a/arch/arm/mach-davinci/include/mach/vmalloc.h
+++ b/arch/arm/mach-davinci/include/mach/vmalloc.h
@@ -8,7 +8,6 @@
8 * is licensed "as is" without any warranty of any kind, whether express 8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 9 * or implied.
10 */ 10 */
11#include <asm/memory.h>
12#include <mach/io.h> 11#include <mach/io.h>
13 12
14/* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ 13/* Allow vmalloc range until the IO virtual range minus a 2M "hole" */
diff --git a/arch/arm/mach-ebsa110/include/mach/dma.h b/arch/arm/mach-ebsa110/include/mach/dma.h
deleted file mode 100644
index 780a04c8bbe9..000000000000
--- a/arch/arm/mach-ebsa110/include/mach/dma.h
+++ /dev/null
@@ -1,11 +0,0 @@
1/*
2 * arch/arm/mach-ebsa110/include/mach/dma.h
3 *
4 * Copyright (C) 1997,1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * EBSA110 DMA definitions
11 */
diff --git a/arch/arm/mach-ebsa110/include/mach/memory.h b/arch/arm/mach-ebsa110/include/mach/memory.h
index eea4b75b657b..0ca66d080c69 100644
--- a/arch/arm/mach-ebsa110/include/mach/memory.h
+++ b/arch/arm/mach-ebsa110/include/mach/memory.h
@@ -22,13 +22,6 @@
22#define PHYS_OFFSET UL(0x00000000) 22#define PHYS_OFFSET UL(0x00000000)
23 23
24/* 24/*
25 * We keep this 1:1 so that we don't interfere
26 * with the PCMCIA memory regions
27 */
28#define __virt_to_bus(x) (x)
29#define __bus_to_virt(x) (x)
30
31/*
32 * Cache flushing area - SRAM 25 * Cache flushing area - SRAM
33 */ 26 */
34#define FLUSH_BASE_PHYS 0x40000000 27#define FLUSH_BASE_PHYS 0x40000000
diff --git a/arch/arm/mach-ep93xx/include/mach/dma.h b/arch/arm/mach-ep93xx/include/mach/dma.h
deleted file mode 100644
index d0fa9656e92f..000000000000
--- a/arch/arm/mach-ep93xx/include/mach/dma.h
+++ /dev/null
@@ -1,3 +0,0 @@
1/*
2 * arch/arm/mach-ep93xx/include/mach/dma.h
3 */
diff --git a/arch/arm/mach-ep93xx/include/mach/io.h b/arch/arm/mach-ep93xx/include/mach/io.h
index 1ab9a90ad339..fd5f081cc8b7 100644
--- a/arch/arm/mach-ep93xx/include/mach/io.h
+++ b/arch/arm/mach-ep93xx/include/mach/io.h
@@ -4,5 +4,5 @@
4 4
5#define IO_SPACE_LIMIT 0xffffffff 5#define IO_SPACE_LIMIT 0xffffffff
6 6
7#define __io(p) ((void __iomem *)(p)) 7#define __io(p) __typesafe_io(p)
8#define __mem_pci(p) (p) 8#define __mem_pci(p) (p)
diff --git a/arch/arm/mach-ep93xx/include/mach/memory.h b/arch/arm/mach-ep93xx/include/mach/memory.h
index f1b633590752..5c80c3c8158d 100644
--- a/arch/arm/mach-ep93xx/include/mach/memory.h
+++ b/arch/arm/mach-ep93xx/include/mach/memory.h
@@ -7,8 +7,4 @@
7 7
8#define PHYS_OFFSET UL(0x00000000) 8#define PHYS_OFFSET UL(0x00000000)
9 9
10#define __bus_to_virt(x) __phys_to_virt(x)
11#define __virt_to_bus(x) __virt_to_phys(x)
12
13
14#endif 10#endif
diff --git a/arch/arm/mach-footbridge/include/mach/hardware.h b/arch/arm/mach-footbridge/include/mach/hardware.h
index ffaea90486f9..ff44e0ce2e14 100644
--- a/arch/arm/mach-footbridge/include/mach/hardware.h
+++ b/arch/arm/mach-footbridge/include/mach/hardware.h
@@ -12,8 +12,6 @@
12#ifndef __ASM_ARCH_HARDWARE_H 12#ifndef __ASM_ARCH_HARDWARE_H
13#define __ASM_ARCH_HARDWARE_H 13#define __ASM_ARCH_HARDWARE_H
14 14
15#include <mach/memory.h>
16
17/* Virtual Physical Size 15/* Virtual Physical Size
18 * 0xff800000 0x40000000 1MB X-Bus 16 * 0xff800000 0x40000000 1MB X-Bus
19 * 0xff000000 0x7c000000 1MB PCI I/O space 17 * 0xff000000 0x7c000000 1MB PCI I/O space
@@ -28,9 +26,6 @@
28#define XBUS_SIZE 0x00100000 26#define XBUS_SIZE 0x00100000
29#define XBUS_BASE 0xff800000 27#define XBUS_BASE 0xff800000
30 28
31#define PCIO_SIZE 0x00100000
32#define PCIO_BASE 0xff000000
33
34#define ARMCSR_SIZE 0x00100000 29#define ARMCSR_SIZE 0x00100000
35#define ARMCSR_BASE 0xfe000000 30#define ARMCSR_BASE 0xfe000000
36 31
diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h
index a7b066239996..101a4fe90bde 100644
--- a/arch/arm/mach-footbridge/include/mach/io.h
+++ b/arch/arm/mach-footbridge/include/mach/io.h
@@ -14,7 +14,8 @@
14#ifndef __ASM_ARM_ARCH_IO_H 14#ifndef __ASM_ARM_ARCH_IO_H
15#define __ASM_ARM_ARCH_IO_H 15#define __ASM_ARM_ARCH_IO_H
16 16
17#include <mach/hardware.h> 17#define PCIO_SIZE 0x00100000
18#define PCIO_BASE 0xff000000
18 19
19#define IO_SPACE_LIMIT 0xffff 20#define IO_SPACE_LIMIT 0xffff
20 21
diff --git a/arch/arm/mach-footbridge/include/mach/dma.h b/arch/arm/mach-footbridge/include/mach/isa-dma.h
index 62afd213effb..5bd4a0d338a8 100644
--- a/arch/arm/mach-footbridge/include/mach/dma.h
+++ b/arch/arm/mach-footbridge/include/mach/isa-dma.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-footbridge/include/mach/dma.h 2 * arch/arm/mach-footbridge/include/mach/isa-dma.h
3 * 3 *
4 * Architecture DMA routines 4 * Architecture DMA routines
5 * 5 *
diff --git a/arch/arm/mach-footbridge/include/mach/memory.h b/arch/arm/mach-footbridge/include/mach/memory.h
index 6ae2f1a07ab9..cb16e59d87b6 100644
--- a/arch/arm/mach-footbridge/include/mach/memory.h
+++ b/arch/arm/mach-footbridge/include/mach/memory.h
@@ -30,9 +30,18 @@
30extern unsigned long __virt_to_bus(unsigned long); 30extern unsigned long __virt_to_bus(unsigned long);
31extern unsigned long __bus_to_virt(unsigned long); 31extern unsigned long __bus_to_virt(unsigned long);
32#endif 32#endif
33#define __virt_to_bus __virt_to_bus
34#define __bus_to_virt __bus_to_virt
33 35
34#elif defined(CONFIG_FOOTBRIDGE_HOST) 36#elif defined(CONFIG_FOOTBRIDGE_HOST)
35 37
38/*
39 * The footbridge is programmed to expose the system RAM at the corresponding
40 * address. So, if PAGE_OFFSET is 0xc0000000, RAM appears at 0xe0000000.
41 * If 0x80000000, then its exposed at 0xa0000000 on the bus. etc.
42 * The only requirement is that the RAM isn't placed at bus address 0 which
43 * would clash with VGA cards.
44 */
36#define __virt_to_bus(x) ((x) - 0xe0000000) 45#define __virt_to_bus(x) ((x) - 0xe0000000)
37#define __bus_to_virt(x) ((x) + 0xe0000000) 46#define __bus_to_virt(x) ((x) + 0xe0000000)
38 47
diff --git a/arch/arm/mach-h720x/include/mach/io.h b/arch/arm/mach-h720x/include/mach/io.h
index 1dab74ce88c6..2c8659c21a93 100644
--- a/arch/arm/mach-h720x/include/mach/io.h
+++ b/arch/arm/mach-h720x/include/mach/io.h
@@ -14,11 +14,9 @@
14#ifndef __ASM_ARM_ARCH_IO_H 14#ifndef __ASM_ARM_ARCH_IO_H
15#define __ASM_ARM_ARCH_IO_H 15#define __ASM_ARM_ARCH_IO_H
16 16
17#include <mach/hardware.h>
18
19#define IO_SPACE_LIMIT 0xffffffff 17#define IO_SPACE_LIMIT 0xffffffff
20 18
21#define __io(a) ((void __iomem *)(a)) 19#define __io(a) __typesafe_io(a)
22#define __mem_pci(a) (a) 20#define __mem_pci(a) (a)
23 21
24#endif 22#endif
diff --git a/arch/arm/mach-h720x/include/mach/dma.h b/arch/arm/mach-h720x/include/mach/isa-dma.h
index 0a9d86ee84fe..3eafb3f163c0 100644
--- a/arch/arm/mach-h720x/include/mach/dma.h
+++ b/arch/arm/mach-h720x/include/mach/isa-dma.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-h720x/include/mach/dma.h 2 * arch/arm/mach-h720x/include/mach/isa-dma.h
3 * 3 *
4 * Architecture DMA routes 4 * Architecture DMA routes
5 * 5 *
@@ -8,13 +8,6 @@
8#ifndef __ASM_ARCH_DMA_H 8#ifndef __ASM_ARCH_DMA_H
9#define __ASM_ARCH_DMA_H 9#define __ASM_ARCH_DMA_H
10 10
11/*
12 * This is the maximum DMA address that can be DMAd to.
13 * There should not be more than (0xd0000000 - 0xc0000000)
14 * bytes of RAM.
15 */
16#define MAX_DMA_ADDRESS 0xd0000000
17
18#if defined (CONFIG_CPU_H7201) 11#if defined (CONFIG_CPU_H7201)
19#define MAX_DMA_CHANNELS 3 12#define MAX_DMA_CHANNELS 3
20#elif defined (CONFIG_CPU_H7202) 13#elif defined (CONFIG_CPU_H7202)
diff --git a/arch/arm/mach-h720x/include/mach/memory.h b/arch/arm/mach-h720x/include/mach/memory.h
index cb26f49cc4e1..ef4c1e26f18e 100644
--- a/arch/arm/mach-h720x/include/mach/memory.h
+++ b/arch/arm/mach-h720x/include/mach/memory.h
@@ -7,23 +7,13 @@
7#ifndef __ASM_ARCH_MEMORY_H 7#ifndef __ASM_ARCH_MEMORY_H
8#define __ASM_ARCH_MEMORY_H 8#define __ASM_ARCH_MEMORY_H
9 9
10/*
11 * Page offset:
12 * ( 0xc0000000UL )
13 */
14#define PHYS_OFFSET UL(0x40000000) 10#define PHYS_OFFSET UL(0x40000000)
15
16/* 11/*
17 * Virtual view <-> DMA view memory address translations 12 * This is the maximum DMA address that can be DMAd to.
18 * virt_to_bus: Used to translate the virtual address to an 13 * There should not be more than (0xd0000000 - 0xc0000000)
19 * address suitable to be passed to set_dma_addr 14 * bytes of RAM.
20 * bus_to_virt: Used to convert an address for DMA operations
21 * to an address that the kernel can use.
22 *
23 * There is something to do here later !, Mar 2000, Jungjun Kim
24 */ 15 */
25 16#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1)
26#define __virt_to_bus(x) __virt_to_phys(x) 17#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M)
27#define __bus_to_virt(x) __phys_to_virt(x)
28 18
29#endif 19#endif
diff --git a/arch/arm/mach-imx/dma.c b/arch/arm/mach-imx/dma.c
index c10810c936b3..1536583eece0 100644
--- a/arch/arm/mach-imx/dma.c
+++ b/arch/arm/mach-imx/dma.c
@@ -28,10 +28,11 @@
28#include <linux/interrupt.h> 28#include <linux/interrupt.h>
29#include <linux/errno.h> 29#include <linux/errno.h>
30 30
31#include <asm/scatterlist.h>
31#include <asm/system.h> 32#include <asm/system.h>
32#include <asm/irq.h> 33#include <asm/irq.h>
33#include <mach/hardware.h> 34#include <mach/hardware.h>
34#include <asm/dma.h> 35#include <mach/dma.h>
35#include <mach/imx-dma.h> 36#include <mach/imx-dma.h>
36 37
37struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; 38struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
@@ -138,7 +139,7 @@ imx_dma_setup_sg_base(imx_dmach_t dma_ch,
138int 139int
139imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, 140imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
140 unsigned int dma_length, unsigned int dev_addr, 141 unsigned int dma_length, unsigned int dev_addr,
141 dmamode_t dmamode) 142 unsigned int dmamode)
142{ 143{
143 struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; 144 struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
144 145
@@ -223,7 +224,7 @@ imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
223int 224int
224imx_dma_setup_sg(imx_dmach_t dma_ch, 225imx_dma_setup_sg(imx_dmach_t dma_ch,
225 struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, 226 struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length,
226 unsigned int dev_addr, dmamode_t dmamode) 227 unsigned int dev_addr, unsigned int dmamode)
227{ 228{
228 int res; 229 int res;
229 struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; 230 struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
diff --git a/arch/arm/mach-imx/include/mach/imx-dma.h b/arch/arm/mach-imx/include/mach/imx-dma.h
index 44d89c35539a..bbe54df7f0de 100644
--- a/arch/arm/mach-imx/include/mach/imx-dma.h
+++ b/arch/arm/mach-imx/include/mach/imx-dma.h
@@ -18,7 +18,7 @@
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20 20
21#include <asm/dma.h> 21#include <mach/dma.h>
22 22
23#ifndef __ASM_ARCH_IMX_DMA_H 23#ifndef __ASM_ARCH_IMX_DMA_H
24#define __ASM_ARCH_IMX_DMA_H 24#define __ASM_ARCH_IMX_DMA_H
@@ -48,7 +48,7 @@ struct imx_dma_channel {
48 void (*irq_handler) (int, void *); 48 void (*irq_handler) (int, void *);
49 void (*err_handler) (int, void *, int errcode); 49 void (*err_handler) (int, void *, int errcode);
50 void *data; 50 void *data;
51 dmamode_t dma_mode; 51 unsigned int dma_mode;
52 struct scatterlist *sg; 52 struct scatterlist *sg;
53 unsigned int sgbc; 53 unsigned int sgbc;
54 unsigned int sgcount; 54 unsigned int sgcount;
@@ -66,14 +66,18 @@ extern struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
66/* The type to distinguish channel numbers parameter from ordinal int type */ 66/* The type to distinguish channel numbers parameter from ordinal int type */
67typedef int imx_dmach_t; 67typedef int imx_dmach_t;
68 68
69#define DMA_MODE_READ 0
70#define DMA_MODE_WRITE 1
71#define DMA_MODE_MASK 1
72
69int 73int
70imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, 74imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
71 unsigned int dma_length, unsigned int dev_addr, dmamode_t dmamode); 75 unsigned int dma_length, unsigned int dev_addr, unsigned int dmamode);
72 76
73int 77int
74imx_dma_setup_sg(imx_dmach_t dma_ch, 78imx_dma_setup_sg(imx_dmach_t dma_ch,
75 struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, 79 struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length,
76 unsigned int dev_addr, dmamode_t dmamode); 80 unsigned int dev_addr, unsigned int dmamode);
77 81
78int 82int
79imx_dma_setup_handlers(imx_dmach_t dma_ch, 83imx_dma_setup_handlers(imx_dmach_t dma_ch,
diff --git a/arch/arm/mach-imx/include/mach/io.h b/arch/arm/mach-imx/include/mach/io.h
index c50c5fa6fb81..9e197ae4590f 100644
--- a/arch/arm/mach-imx/include/mach/io.h
+++ b/arch/arm/mach-imx/include/mach/io.h
@@ -20,11 +20,9 @@
20#ifndef __ASM_ARM_ARCH_IO_H 20#ifndef __ASM_ARM_ARCH_IO_H
21#define __ASM_ARM_ARCH_IO_H 21#define __ASM_ARM_ARCH_IO_H
22 22
23#include <mach/hardware.h>
24
25#define IO_SPACE_LIMIT 0xffffffff 23#define IO_SPACE_LIMIT 0xffffffff
26 24
27#define __io(a) ((void __iomem *)(a)) 25#define __io(a) __typesafe_io(a)
28#define __mem_pci(a) (a) 26#define __mem_pci(a) (a)
29 27
30#endif 28#endif
diff --git a/arch/arm/mach-imx/include/mach/memory.h b/arch/arm/mach-imx/include/mach/memory.h
index 5c453063c0ed..a93df7cba694 100644
--- a/arch/arm/mach-imx/include/mach/memory.h
+++ b/arch/arm/mach-imx/include/mach/memory.h
@@ -23,14 +23,4 @@
23 23
24#define PHYS_OFFSET UL(0x08000000) 24#define PHYS_OFFSET UL(0x08000000)
25 25
26/*
27 * Virtual view <-> DMA view memory address translations
28 * virt_to_bus: Used to translate the virtual address to an
29 * address suitable to be passed to set_dma_addr
30 * bus_to_virt: Used to convert an address for DMA operations
31 * to an address that the kernel can use.
32 */
33#define __virt_to_bus(x) (x - PAGE_OFFSET + PHYS_OFFSET)
34#define __bus_to_virt(x) (x - PHYS_OFFSET + PAGE_OFFSET)
35
36#endif 26#endif
diff --git a/arch/arm/mach-integrator/include/mach/dma.h b/arch/arm/mach-integrator/include/mach/dma.h
deleted file mode 100644
index fbebe85a2db7..000000000000
--- a/arch/arm/mach-integrator/include/mach/dma.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-integrator/include/mach/dma.h
3 *
4 * Copyright (C) 1997,1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
diff --git a/arch/arm/mach-integrator/include/mach/memory.h b/arch/arm/mach-integrator/include/mach/memory.h
index be7e63c21d25..2b2e7a110724 100644
--- a/arch/arm/mach-integrator/include/mach/memory.h
+++ b/arch/arm/mach-integrator/include/mach/memory.h
@@ -24,16 +24,9 @@
24 * Physical DRAM offset. 24 * Physical DRAM offset.
25 */ 25 */
26#define PHYS_OFFSET UL(0x00000000) 26#define PHYS_OFFSET UL(0x00000000)
27#define BUS_OFFSET UL(0x80000000)
28 27
29/* 28#define BUS_OFFSET UL(0x80000000)
30 * Virtual view <-> DMA view memory address translations 29#define __virt_to_bus(x) ((x) - PAGE_OFFSET + BUS_OFFSET)
31 * virt_to_bus: Used to translate the virtual address to an 30#define __bus_to_virt(x) ((x) - BUS_OFFSET + PAGE_OFFSET)
32 * address suitable to be passed to set_dma_addr
33 * bus_to_virt: Used to convert an address for DMA operations
34 * to an address that the kernel can use.
35 */
36#define __virt_to_bus(x) (x - PAGE_OFFSET + BUS_OFFSET)
37#define __bus_to_virt(x) (x - BUS_OFFSET + PAGE_OFFSET)
38 31
39#endif 32#endif
diff --git a/arch/arm/mach-iop13xx/include/mach/dma.h b/arch/arm/mach-iop13xx/include/mach/dma.h
deleted file mode 100644
index d79846fbb394..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/dma.h
+++ /dev/null
@@ -1,3 +0,0 @@
1#ifndef _IOP13XX_DMA_H
2#define _IOP13XX_DMA_H
3#endif
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h
index b82602d529bf..e012bf13c955 100644
--- a/arch/arm/mach-iop13xx/include/mach/memory.h
+++ b/arch/arm/mach-iop13xx/include/mach/memory.h
@@ -16,18 +16,6 @@
16#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE) 16#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
17#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE) 17#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
18 18
19/*
20 * Virtual view <-> PCI DMA view memory address translations
21 * virt_to_bus: Used to translate the virtual address to an
22 * address suitable to be passed to set_dma_addr
23 * bus_to_virt: Used to convert an address for DMA operations
24 * to an address that the kernel can use.
25 */
26
27/* RAM has 1:1 mapping on the PCIe/x Busses */
28#define __virt_to_bus(x) (__virt_to_phys(x))
29#define __bus_to_virt(x) (__phys_to_virt(x))
30
31static inline dma_addr_t __virt_to_lbus(unsigned long x) 19static inline dma_addr_t __virt_to_lbus(unsigned long x)
32{ 20{
33 return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE; 21 return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE;
@@ -55,7 +43,7 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x)
55 if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \ 43 if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \
56 __virt = __lbus_to_virt(__dma); \ 44 __virt = __lbus_to_virt(__dma); \
57 else \ 45 else \
58 __virt = __bus_to_virt(__dma); \ 46 __virt = __phys_to_virt(__dma); \
59 (void *)__virt; \ 47 (void *)__virt; \
60 }) 48 })
61 49
@@ -66,7 +54,7 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x)
66 if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \ 54 if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \
67 __dma = __virt_to_lbus(__virt); \ 55 __dma = __virt_to_lbus(__virt); \
68 else \ 56 else \
69 __dma = __virt_to_bus(__virt); \ 57 __dma = __virt_to_phys(__virt); \
70 __dma; \ 58 __dma; \
71 }) 59 })
72 60
diff --git a/arch/arm/mach-iop13xx/include/mach/timex.h b/arch/arm/mach-iop13xx/include/mach/timex.h
index 5b1f1c8a8270..45fb2745bb54 100644
--- a/arch/arm/mach-iop13xx/include/mach/timex.h
+++ b/arch/arm/mach-iop13xx/include/mach/timex.h
@@ -1,3 +1 @@
1#include <mach/hardware.h>
2
3#define CLOCK_TICK_RATE (100 * HZ) #define CLOCK_TICK_RATE (100 * HZ)
diff --git a/arch/arm/mach-iop32x/include/mach/dma.h b/arch/arm/mach-iop32x/include/mach/dma.h
deleted file mode 100644
index f8bd817f205d..000000000000
--- a/arch/arm/mach-iop32x/include/mach/dma.h
+++ /dev/null
@@ -1,9 +0,0 @@
1/*
2 * arch/arm/mach-iop32x/include/mach/dma.h
3 *
4 * Copyright (C) 2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h
index ce54705ba3d4..339e5854728b 100644
--- a/arch/arm/mach-iop32x/include/mach/io.h
+++ b/arch/arm/mach-iop32x/include/mach/io.h
@@ -11,7 +11,7 @@
11#ifndef __IO_H 11#ifndef __IO_H
12#define __IO_H 12#define __IO_H
13 13
14#include <mach/hardware.h> 14#include <asm/hardware/iop3xx.h>
15 15
16extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, 16extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
17 unsigned int mtype); 17 unsigned int mtype);
diff --git a/arch/arm/mach-iop32x/include/mach/memory.h b/arch/arm/mach-iop32x/include/mach/memory.h
index 42cd4bf3148c..c30f6450ad50 100644
--- a/arch/arm/mach-iop32x/include/mach/memory.h
+++ b/arch/arm/mach-iop32x/include/mach/memory.h
@@ -5,22 +5,9 @@
5#ifndef __MEMORY_H 5#ifndef __MEMORY_H
6#define __MEMORY_H 6#define __MEMORY_H
7 7
8#include <mach/hardware.h>
9
10/* 8/*
11 * Physical DRAM offset. 9 * Physical DRAM offset.
12 */ 10 */
13#define PHYS_OFFSET UL(0xa0000000) 11#define PHYS_OFFSET UL(0xa0000000)
14 12
15/*
16 * Virtual view <-> PCI DMA view memory address translations
17 * virt_to_bus: Used to translate the virtual address to an
18 * address suitable to be passed to set_dma_addr
19 * bus_to_virt: Used to convert an address for DMA operations
20 * to an address that the kernel can use.
21 */
22#define __virt_to_bus(x) (__virt_to_phys(x))
23#define __bus_to_virt(x) (__phys_to_virt(x))
24
25
26#endif 13#endif
diff --git a/arch/arm/mach-iop32x/include/mach/system.h b/arch/arm/mach-iop32x/include/mach/system.h
index 20f923e54f46..32d9e5b0a28d 100644
--- a/arch/arm/mach-iop32x/include/mach/system.h
+++ b/arch/arm/mach-iop32x/include/mach/system.h
@@ -7,8 +7,9 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10
11#include <asm/mach-types.h> 10#include <asm/mach-types.h>
11#include <asm/hardware/iop3xx.h>
12#include <mach/n2100.h>
12 13
13static inline void arch_idle(void) 14static inline void arch_idle(void)
14{ 15{
diff --git a/arch/arm/mach-iop32x/include/mach/timex.h b/arch/arm/mach-iop32x/include/mach/timex.h
index a541afced3cb..7262ab81419d 100644
--- a/arch/arm/mach-iop32x/include/mach/timex.h
+++ b/arch/arm/mach-iop32x/include/mach/timex.h
@@ -3,7 +3,4 @@
3 * 3 *
4 * IOP32x architecture timex specifications 4 * IOP32x architecture timex specifications
5 */ 5 */
6
7#include <mach/hardware.h>
8
9#define CLOCK_TICK_RATE (100 * HZ) 6#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/arch/arm/mach-iop33x/include/mach/dma.h b/arch/arm/mach-iop33x/include/mach/dma.h
deleted file mode 100644
index d8b42232931d..000000000000
--- a/arch/arm/mach-iop33x/include/mach/dma.h
+++ /dev/null
@@ -1,9 +0,0 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/dma.h
3 *
4 * Copyright (C) 2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h
index 158874631217..e99a7ed6d050 100644
--- a/arch/arm/mach-iop33x/include/mach/io.h
+++ b/arch/arm/mach-iop33x/include/mach/io.h
@@ -11,7 +11,7 @@
11#ifndef __IO_H 11#ifndef __IO_H
12#define __IO_H 12#define __IO_H
13 13
14#include <mach/hardware.h> 14#include <asm/hardware/iop3xx.h>
15 15
16extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, 16extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
17 unsigned int mtype); 17 unsigned int mtype);
diff --git a/arch/arm/mach-iop33x/include/mach/memory.h b/arch/arm/mach-iop33x/include/mach/memory.h
index 2cef0bbb354f..a30a96aa6d2d 100644
--- a/arch/arm/mach-iop33x/include/mach/memory.h
+++ b/arch/arm/mach-iop33x/include/mach/memory.h
@@ -5,22 +5,9 @@
5#ifndef __MEMORY_H 5#ifndef __MEMORY_H
6#define __MEMORY_H 6#define __MEMORY_H
7 7
8#include <mach/hardware.h>
9
10/* 8/*
11 * Physical DRAM offset. 9 * Physical DRAM offset.
12 */ 10 */
13#define PHYS_OFFSET UL(0x00000000) 11#define PHYS_OFFSET UL(0x00000000)
14 12
15/*
16 * Virtual view <-> PCI DMA view memory address translations
17 * virt_to_bus: Used to translate the virtual address to an
18 * address suitable to be passed to set_dma_addr
19 * bus_to_virt: Used to convert an address for DMA operations
20 * to an address that the kernel can use.
21 */
22#define __virt_to_bus(x) (__virt_to_phys(x))
23#define __bus_to_virt(x) (__phys_to_virt(x))
24
25
26#endif 13#endif
diff --git a/arch/arm/mach-iop33x/include/mach/timex.h b/arch/arm/mach-iop33x/include/mach/timex.h
index c75760844d49..54c589091d6e 100644
--- a/arch/arm/mach-iop33x/include/mach/timex.h
+++ b/arch/arm/mach-iop33x/include/mach/timex.h
@@ -3,7 +3,4 @@
3 * 3 *
4 * IOP3xx architecture timex specifications 4 * IOP3xx architecture timex specifications
5 */ 5 */
6
7#include <mach/hardware.h>
8
9#define CLOCK_TICK_RATE (100 * HZ) 6#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/arch/arm/mach-ixp2000/include/mach/dma.h b/arch/arm/mach-ixp2000/include/mach/dma.h
deleted file mode 100644
index 26063d60f622..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/dma.h
+++ /dev/null
@@ -1,9 +0,0 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/dma.h
3 *
4 * Copyright (C) 2002 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
diff --git a/arch/arm/mach-ixp2000/include/mach/memory.h b/arch/arm/mach-ixp2000/include/mach/memory.h
index 241529a7c52d..aee7eb8a71b2 100644
--- a/arch/arm/mach-ixp2000/include/mach/memory.h
+++ b/arch/arm/mach-ixp2000/include/mach/memory.h
@@ -15,13 +15,6 @@
15 15
16#define PHYS_OFFSET UL(0x00000000) 16#define PHYS_OFFSET UL(0x00000000)
17 17
18/*
19 * Virtual view <-> DMA view memory address translations
20 * virt_to_bus: Used to translate the virtual address to an
21 * address suitable to be passed to set_dma_addr
22 * bus_to_virt: Used to convert an address for DMA operations
23 * to an address that the kernel can use.
24 */
25#include <mach/ixp2000-regs.h> 18#include <mach/ixp2000-regs.h>
26 19
27#define __virt_to_bus(v) \ 20#define __virt_to_bus(v) \
diff --git a/arch/arm/mach-ixp23xx/include/mach/dma.h b/arch/arm/mach-ixp23xx/include/mach/dma.h
deleted file mode 100644
index 8886544b93f7..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/dma.h
+++ /dev/null
@@ -1,3 +0,0 @@
1/*
2 * arch/arm/mach-ixp23xx/include/mach/dma.h
3 */
diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h
index 305ea1808c71..fd9ef8e519f7 100644
--- a/arch/arm/mach-ixp23xx/include/mach/io.h
+++ b/arch/arm/mach-ixp23xx/include/mach/io.h
@@ -20,8 +20,6 @@
20#define __io(p) ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT)) 20#define __io(p) ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
21#define __mem_pci(a) (a) 21#define __mem_pci(a) (a)
22 22
23#include <linux/kernel.h> /* For BUG */
24
25static inline void __iomem * 23static inline void __iomem *
26ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned int mtype) 24ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned int mtype)
27{ 25{
diff --git a/arch/arm/mach-ixp23xx/include/mach/memory.h b/arch/arm/mach-ixp23xx/include/mach/memory.h
index 9d40115f7ebe..fdd138706c70 100644
--- a/arch/arm/mach-ixp23xx/include/mach/memory.h
+++ b/arch/arm/mach-ixp23xx/include/mach/memory.h
@@ -19,16 +19,6 @@
19 */ 19 */
20#define PHYS_OFFSET (0x00000000) 20#define PHYS_OFFSET (0x00000000)
21 21
22
23/*
24 * Virtual view <-> DMA view memory address translations
25 * virt_to_bus: Used to translate the virtual address to an
26 * address suitable to be passed to set_dma_addr
27 * bus_to_virt: Used to convert an address for DMA operations
28 * to an address that the kernel can use.
29 */
30#ifndef __ASSEMBLY__
31
32#define __virt_to_bus(v) \ 22#define __virt_to_bus(v) \
33 ({ unsigned int ret; \ 23 ({ unsigned int ret; \
34 ret = ((__virt_to_phys(v) - 0x00000000) + \ 24 ret = ((__virt_to_phys(v) - 0x00000000) + \
@@ -43,6 +33,3 @@
43#define arch_is_coherent() 1 33#define arch_is_coherent() 1
44 34
45#endif 35#endif
46
47
48#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/dma.h b/arch/arm/mach-ixp4xx/include/mach/dma.h
deleted file mode 100644
index 00c5070c0201..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/dma.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/dma.h
3 *
4 * Copyright (C) 2001-2004 MontaVista Software, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11#ifndef __ASM_ARCH_DMA_H
12#define __ASM_ARCH_DMA_H
13
14#include <linux/device.h>
15#include <asm/page.h>
16#include <asm/sizes.h>
17#include <mach/hardware.h>
18
19#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
20
21#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index 319948e31bec..ce63048d45eb 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -49,8 +49,6 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
49 49
50#else 50#else
51 51
52#include <linux/mm.h>
53
54/* 52/*
55 * In the case of using indirect PCI, we simply return the actual PCI 53 * In the case of using indirect PCI, we simply return the actual PCI
56 * address and our read/write implementation use that to drive the 54 * address and our read/write implementation use that to drive the
@@ -241,7 +239,7 @@ __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
241 239
242#ifndef CONFIG_PCI 240#ifndef CONFIG_PCI
243 241
244#define __io(v) v 242#define __io(v) __typesafe_io(v)
245 243
246#else 244#else
247 245
diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h
index c4d2830ac987..98f5e5e20980 100644
--- a/arch/arm/mach-ixp4xx/include/mach/memory.h
+++ b/arch/arm/mach-ixp4xx/include/mach/memory.h
@@ -22,19 +22,8 @@ void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes);
22 ixp4xx_adjust_zones(node, size, holes) 22 ixp4xx_adjust_zones(node, size, holes)
23 23
24#define ISA_DMA_THRESHOLD (SZ_64M - 1) 24#define ISA_DMA_THRESHOLD (SZ_64M - 1)
25#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
25 26
26#endif 27#endif
27 28
28/*
29 * Virtual view <-> DMA view memory address translations
30 * virt_to_bus: Used to translate the virtual address to an
31 * address suitable to be passed to set_dma_addr
32 * bus_to_virt: Used to convert an address for DMA operations
33 * to an address that the kernel can use.
34 *
35 * These are dummies for now.
36 */
37#define __virt_to_bus(x) __virt_to_phys(x)
38#define __bus_to_virt(x) __phys_to_virt(x)
39
40#endif 29#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/dma.h b/arch/arm/mach-kirkwood/include/mach/dma.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/dma.h
+++ /dev/null
@@ -1 +0,0 @@
1/* empty */
diff --git a/arch/arm/mach-kirkwood/include/mach/memory.h b/arch/arm/mach-kirkwood/include/mach/memory.h
index b5fb34bdccd5..45431e131465 100644
--- a/arch/arm/mach-kirkwood/include/mach/memory.h
+++ b/arch/arm/mach-kirkwood/include/mach/memory.h
@@ -7,8 +7,4 @@
7 7
8#define PHYS_OFFSET UL(0x00000000) 8#define PHYS_OFFSET UL(0x00000000)
9 9
10#define __virt_to_bus(x) __virt_to_phys(x)
11#define __bus_to_virt(x) __phys_to_virt(x)
12
13
14#endif 10#endif
diff --git a/arch/arm/mach-ks8695/include/mach/dma.h b/arch/arm/mach-ks8695/include/mach/dma.h
deleted file mode 100644
index 561206280089..000000000000
--- a/arch/arm/mach-ks8695/include/mach/dma.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * arch/arm/mach-ks8695/include/mach/dma.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
diff --git a/arch/arm/mach-ks8695/include/mach/io.h b/arch/arm/mach-ks8695/include/mach/io.h
index f364f24ffe1e..a7a63ac3ba4e 100644
--- a/arch/arm/mach-ks8695/include/mach/io.h
+++ b/arch/arm/mach-ks8695/include/mach/io.h
@@ -13,7 +13,7 @@
13 13
14#define IO_SPACE_LIMIT 0xffffffff 14#define IO_SPACE_LIMIT 0xffffffff
15 15
16#define __io(a) ((void __iomem *)(a)) 16#define __io(a) __typesafe_io(a)
17#define __mem_pci(a) (a) 17#define __mem_pci(a) (a)
18 18
19#endif 19#endif
diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h
index 8fbc4c76c38b..6d5887cf5742 100644
--- a/arch/arm/mach-ks8695/include/mach/memory.h
+++ b/arch/arm/mach-ks8695/include/mach/memory.h
@@ -37,11 +37,6 @@ extern struct bus_type platform_bus_type;
37 (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); }) 37 (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); })
38#define __arch_page_to_dma(dev, x) __arch_virt_to_dma(dev, page_address(x)) 38#define __arch_page_to_dma(dev, x) __arch_virt_to_dma(dev, page_address(x))
39 39
40#else
41
42#define __virt_to_bus(x) __virt_to_phys(x)
43#define __bus_to_virt(x) __phys_to_virt(x)
44
45#endif 40#endif
46 41
47#endif 42#endif
diff --git a/arch/arm/mach-l7200/include/mach/dma.h b/arch/arm/mach-l7200/include/mach/dma.h
deleted file mode 100644
index c7e48bd4590c..000000000000
--- a/arch/arm/mach-l7200/include/mach/dma.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * arch/arm/mach-l7200/include/mach/dma.h
3 *
4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
5 *
6 * Changelog:
7 * 08-29-2000 SJH Created
8 */
9#ifndef __ASM_ARCH_DMA_H
10#define __ASM_ARCH_DMA_H
11
12/* DMA is not yet implemented! It should be the same as acorn, copy over.. */
13
14/*
15 * This is the maximum DMA address that can be DMAd to.
16 * There should not be more than (0xd0000000 - 0xc0000000)
17 * bytes of RAM.
18 */
19#define MAX_DMA_ADDRESS 0xd0000000
20
21#define DMA_S0 0
22
23#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-l7200/include/mach/io.h b/arch/arm/mach-l7200/include/mach/io.h
index d432ba9e5dff..a770a89fb708 100644
--- a/arch/arm/mach-l7200/include/mach/io.h
+++ b/arch/arm/mach-l7200/include/mach/io.h
@@ -10,18 +10,12 @@
10#ifndef __ASM_ARM_ARCH_IO_H 10#ifndef __ASM_ARM_ARCH_IO_H
11#define __ASM_ARM_ARCH_IO_H 11#define __ASM_ARM_ARCH_IO_H
12 12
13#include <mach/hardware.h>
14
15#define IO_SPACE_LIMIT 0xffffffff 13#define IO_SPACE_LIMIT 0xffffffff
16 14
17/* 15/*
18 * There are not real ISA nor PCI buses, so we fake it. 16 * There are not real ISA nor PCI buses, so we fake it.
19 */ 17 */
20static inline void __iomem *__io(unsigned long addr) 18#define __io(a) __typesafe_io(a)
21{ 19#define __mem_pci(a) (a)
22 return (void __iomem *)addr;
23}
24#define __io(a) __io(a)
25#define __mem_pci(a) (a)
26 20
27#endif 21#endif
diff --git a/arch/arm/mach-l7200/include/mach/memory.h b/arch/arm/mach-l7200/include/mach/memory.h
index f338cf3ffd93..9fb40ed2f03b 100644
--- a/arch/arm/mach-l7200/include/mach/memory.h
+++ b/arch/arm/mach-l7200/include/mach/memory.h
@@ -17,9 +17,6 @@
17 */ 17 */
18#define PHYS_OFFSET UL(0xf0000000) 18#define PHYS_OFFSET UL(0xf0000000)
19 19
20#define __virt_to_bus(x) __virt_to_phys(x)
21#define __bus_to_virt(x) __phys_to_virt(x)
22
23/* 20/*
24 * Cache flushing area - ROM 21 * Cache flushing area - ROM
25 */ 22 */
diff --git a/arch/arm/mach-lh7a40x/include/mach/io.h b/arch/arm/mach-lh7a40x/include/mach/io.h
index 031d26f9163c..6ece45911cbc 100644
--- a/arch/arm/mach-lh7a40x/include/mach/io.h
+++ b/arch/arm/mach-lh7a40x/include/mach/io.h
@@ -11,12 +11,10 @@
11#ifndef __ASM_ARCH_IO_H 11#ifndef __ASM_ARCH_IO_H
12#define __ASM_ARCH_IO_H 12#define __ASM_ARCH_IO_H
13 13
14#include <mach/hardware.h>
15
16#define IO_SPACE_LIMIT 0xffffffff 14#define IO_SPACE_LIMIT 0xffffffff
17 15
18/* No ISA or PCI bus on this machine. */ 16/* No ISA or PCI bus on this machine. */
19#define __io(a) ((void __iomem *)(a)) 17#define __io(a) __typesafe_io(a)
20#define __mem_pci(a) (a) 18#define __mem_pci(a) (a)
21 19
22#endif /* __ASM_ARCH_IO_H */ 20#endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-lh7a40x/include/mach/memory.h b/arch/arm/mach-lh7a40x/include/mach/memory.h
index 1da14ff66c93..189d20e543e7 100644
--- a/arch/arm/mach-lh7a40x/include/mach/memory.h
+++ b/arch/arm/mach-lh7a40x/include/mach/memory.h
@@ -19,16 +19,6 @@
19 */ 19 */
20#define PHYS_OFFSET UL(0xc0000000) 20#define PHYS_OFFSET UL(0xc0000000)
21 21
22/*
23 * Virtual view <-> DMA view memory address translations
24 * virt_to_bus: Used to translate the virtual address to an
25 * address suitable to be passed to set_dma_addr
26 * bus_to_virt: Used to convert an address for DMA operations
27 * to an address that the kernel can use.
28 */
29#define __virt_to_bus(x) __virt_to_phys(x)
30#define __bus_to_virt(x) __phys_to_virt(x)
31
32#ifdef CONFIG_DISCONTIGMEM 22#ifdef CONFIG_DISCONTIGMEM
33 23
34/* 24/*
diff --git a/arch/arm/mach-loki/include/mach/dma.h b/arch/arm/mach-loki/include/mach/dma.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-loki/include/mach/dma.h
+++ /dev/null
@@ -1 +0,0 @@
1/* empty */
diff --git a/arch/arm/mach-loki/include/mach/memory.h b/arch/arm/mach-loki/include/mach/memory.h
index a39533ab489d..2ed7e6e732c2 100644
--- a/arch/arm/mach-loki/include/mach/memory.h
+++ b/arch/arm/mach-loki/include/mach/memory.h
@@ -7,8 +7,4 @@
7 7
8#define PHYS_OFFSET UL(0x00000000) 8#define PHYS_OFFSET UL(0x00000000)
9 9
10#define __virt_to_bus(x) __virt_to_phys(x)
11#define __bus_to_virt(x) __phys_to_virt(x)
12
13
14#endif 10#endif
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index c6a2feb268b0..aab964591db4 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -23,11 +23,7 @@
23 23
24void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype); 24void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype);
25 25
26static inline void __iomem *__io(unsigned long addr) 26#define __io(a) __typesafe_io(a)
27{
28 return (void __iomem *)addr;
29}
30#define __io(a) __io(a)
31#define __mem_pci(a) (a) 27#define __mem_pci(a) (a)
32 28
33#endif 29#endif
diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
index 63fd47f2e62e..f4698baec976 100644
--- a/arch/arm/mach-msm/include/mach/memory.h
+++ b/arch/arm/mach-msm/include/mach/memory.h
@@ -19,9 +19,5 @@
19/* physical offset of RAM */ 19/* physical offset of RAM */
20#define PHYS_OFFSET UL(0x10000000) 20#define PHYS_OFFSET UL(0x10000000)
21 21
22/* bus address and physical addresses are identical */
23#define __virt_to_bus(x) __virt_to_phys(x)
24#define __bus_to_virt(x) __phys_to_virt(x)
25
26#endif 22#endif
27 23
diff --git a/arch/arm/mach-mv78xx0/include/mach/dma.h b/arch/arm/mach-mv78xx0/include/mach/dma.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-mv78xx0/include/mach/dma.h
+++ /dev/null
@@ -1 +0,0 @@
1/* empty */
diff --git a/arch/arm/mach-mv78xx0/include/mach/memory.h b/arch/arm/mach-mv78xx0/include/mach/memory.h
index 9e47a140ff7a..e663042d307f 100644
--- a/arch/arm/mach-mv78xx0/include/mach/memory.h
+++ b/arch/arm/mach-mv78xx0/include/mach/memory.h
@@ -7,8 +7,4 @@
7 7
8#define PHYS_OFFSET UL(0x00000000) 8#define PHYS_OFFSET UL(0x00000000)
9 9
10#define __virt_to_bus(x) __virt_to_phys(x)
11#define __bus_to_virt(x) __phys_to_virt(x)
12
13
14#endif 10#endif
diff --git a/arch/arm/mach-netx/include/mach/dma.h b/arch/arm/mach-netx/include/mach/dma.h
deleted file mode 100644
index 690b3ebc43ac..000000000000
--- a/arch/arm/mach-netx/include/mach/dma.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * arch/arm/mach-netx/include/mach/dma.h
3 *
4 * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#define MAX_DMA_CHANNELS 0
21#define MAX_DMA_ADDRESS ~0
diff --git a/arch/arm/mach-netx/include/mach/io.h b/arch/arm/mach-netx/include/mach/io.h
index 468b92a82585..c3921cb3b6a6 100644
--- a/arch/arm/mach-netx/include/mach/io.h
+++ b/arch/arm/mach-netx/include/mach/io.h
@@ -22,7 +22,7 @@
22 22
23#define IO_SPACE_LIMIT 0xffffffff 23#define IO_SPACE_LIMIT 0xffffffff
24 24
25#define __io(a) ((void __iomem *)(a)) 25#define __io(a) __typesafe_io(a)
26#define __mem_pci(a) (a) 26#define __mem_pci(a) (a)
27 27
28#endif 28#endif
diff --git a/arch/arm/mach-netx/include/mach/memory.h b/arch/arm/mach-netx/include/mach/memory.h
index 53745a1378de..9a363f297f90 100644
--- a/arch/arm/mach-netx/include/mach/memory.h
+++ b/arch/arm/mach-netx/include/mach/memory.h
@@ -22,15 +22,5 @@
22 22
23#define PHYS_OFFSET UL(0x80000000) 23#define PHYS_OFFSET UL(0x80000000)
24 24
25/*
26 * Virtual view <-> DMA view memory address translations
27 * virt_to_bus: Used to translate the virtual address to an
28 * address suitable to be passed to set_dma_addr
29 * bus_to_virt: Used to convert an address for DMA operations
30 * to an address that the kernel can use.
31 */
32#define __virt_to_bus(x) __virt_to_phys(x)
33#define __bus_to_virt(x) __phys_to_virt(x)
34
35#endif 25#endif
36 26
diff --git a/arch/arm/mach-ns9xxx/include/mach/dma.h b/arch/arm/mach-ns9xxx/include/mach/dma.h
deleted file mode 100644
index 3f50d8c9e5c7..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/dma.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/dma.h
3 *
4 * Copyright (C) 2006 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __ASM_ARCH_DMA_H
12#define __ASM_ARCH_DMA_H
13
14#endif /* ifndef __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/hardware.h b/arch/arm/mach-ns9xxx/include/mach/hardware.h
index 6dbb2030f563..76631128e11c 100644
--- a/arch/arm/mach-ns9xxx/include/mach/hardware.h
+++ b/arch/arm/mach-ns9xxx/include/mach/hardware.h
@@ -11,8 +11,6 @@
11#ifndef __ASM_ARCH_HARDWARE_H 11#ifndef __ASM_ARCH_HARDWARE_H
12#define __ASM_ARCH_HARDWARE_H 12#define __ASM_ARCH_HARDWARE_H
13 13
14#include <asm/memory.h>
15
16/* 14/*
17 * NetSilicon NS9xxx internal mapping: 15 * NetSilicon NS9xxx internal mapping:
18 * 16 *
diff --git a/arch/arm/mach-ns9xxx/include/mach/io.h b/arch/arm/mach-ns9xxx/include/mach/io.h
index 027bf649645a..f08451d2e1bc 100644
--- a/arch/arm/mach-ns9xxx/include/mach/io.h
+++ b/arch/arm/mach-ns9xxx/include/mach/io.h
@@ -13,7 +13,7 @@
13 13
14#define IO_SPACE_LIMIT 0xffffffff /* XXX */ 14#define IO_SPACE_LIMIT 0xffffffff /* XXX */
15 15
16#define __io(a) ((void __iomem *)(a)) 16#define __io(a) __typesafe_io(a)
17#define __mem_pci(a) (a) 17#define __mem_pci(a) (a)
18#define __mem_isa(a) (IO_BASE + (a)) 18#define __mem_isa(a) (IO_BASE + (a))
19 19
diff --git a/arch/arm/mach-ns9xxx/include/mach/memory.h b/arch/arm/mach-ns9xxx/include/mach/memory.h
index 649ee6235b94..6107193adbfe 100644
--- a/arch/arm/mach-ns9xxx/include/mach/memory.h
+++ b/arch/arm/mach-ns9xxx/include/mach/memory.h
@@ -21,7 +21,4 @@
21 21
22#define PHYS_OFFSET UL(0x00000000) 22#define PHYS_OFFSET UL(0x00000000)
23 23
24#define __virt_to_bus(x) __virt_to_phys(x)
25#define __bus_to_virt(x) __phys_to_virt(x)
26
27#endif 24#endif
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 79f0b1f8497b..10a301e32434 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -4,16 +4,19 @@ comment "OMAP Core Type"
4config ARCH_OMAP730 4config ARCH_OMAP730
5 depends on ARCH_OMAP1 5 depends on ARCH_OMAP1
6 bool "OMAP730 Based System" 6 bool "OMAP730 Based System"
7 select CPU_ARM926T
7 select ARCH_OMAP_OTG 8 select ARCH_OMAP_OTG
8 9
9config ARCH_OMAP15XX 10config ARCH_OMAP15XX
10 depends on ARCH_OMAP1 11 depends on ARCH_OMAP1
11 default y 12 default y
12 bool "OMAP15xx Based System" 13 bool "OMAP15xx Based System"
14 select CPU_ARM925T
13 15
14config ARCH_OMAP16XX 16config ARCH_OMAP16XX
15 depends on ARCH_OMAP1 17 depends on ARCH_OMAP1
16 bool "OMAP16xx Based System" 18 bool "OMAP16xx Based System"
19 select CPU_ARM926T
17 select ARCH_OMAP_OTG 20 select ARCH_OMAP_OTG
18 21
19comment "OMAP Board Type" 22comment "OMAP Board Type"
diff --git a/arch/arm/mach-orion5x/include/mach/dma.h b/arch/arm/mach-orion5x/include/mach/dma.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-orion5x/include/mach/dma.h
+++ /dev/null
@@ -1 +0,0 @@
1/* empty */
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
index f24b2513f7f3..c47b033bd999 100644
--- a/arch/arm/mach-orion5x/include/mach/io.h
+++ b/arch/arm/mach-orion5x/include/mach/io.h
@@ -38,14 +38,9 @@ __arch_iounmap(void __iomem *addr)
38 __iounmap(addr); 38 __iounmap(addr);
39} 39}
40 40
41static inline void __iomem *__io(unsigned long addr)
42{
43 return (void __iomem *)addr;
44}
45
46#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m) 41#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m)
47#define __arch_iounmap(a) __arch_iounmap(a) 42#define __arch_iounmap(a) __arch_iounmap(a)
48#define __io(a) __io(a) 43#define __io(a) __typesafe_io(a)
49#define __mem_pci(a) (a) 44#define __mem_pci(a) (a)
50 45
51 46
diff --git a/arch/arm/mach-orion5x/include/mach/memory.h b/arch/arm/mach-orion5x/include/mach/memory.h
index 54dd76b013f2..52a2955d0f87 100644
--- a/arch/arm/mach-orion5x/include/mach/memory.h
+++ b/arch/arm/mach-orion5x/include/mach/memory.h
@@ -9,8 +9,4 @@
9 9
10#define PHYS_OFFSET UL(0x00000000) 10#define PHYS_OFFSET UL(0x00000000)
11 11
12#define __virt_to_bus(x) __virt_to_phys(x)
13#define __bus_to_virt(x) __phys_to_virt(x)
14
15
16#endif 12#endif
diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c
index ac2f70eddb9e..425f7188505e 100644
--- a/arch/arm/mach-pnx4008/dma.c
+++ b/arch/arm/mach-pnx4008/dma.c
@@ -25,9 +25,8 @@
25 25
26#include <asm/system.h> 26#include <asm/system.h>
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <asm/dma.h> 28#include <mach/dma.h>
29#include <asm/dma-mapping.h> 29#include <asm/dma-mapping.h>
30#include <asm/mach/dma.h>
31#include <mach/clock.h> 30#include <mach/clock.h>
32 31
33static struct dma_channel { 32static struct dma_channel {
diff --git a/arch/arm/mach-pnx4008/include/mach/dma.h b/arch/arm/mach-pnx4008/include/mach/dma.h
index 5442d04fc575..f094bf8bfb18 100644
--- a/arch/arm/mach-pnx4008/include/mach/dma.h
+++ b/arch/arm/mach-pnx4008/include/mach/dma.h
@@ -16,8 +16,6 @@
16 16
17#include "platform.h" 17#include "platform.h"
18 18
19#define MAX_DMA_ADDRESS 0xffffffff
20
21#define MAX_DMA_CHANNELS 8 19#define MAX_DMA_CHANNELS 8
22 20
23#define DMAC_BASE IO_ADDRESS(PNX4008_DMA_CONFIG_BASE) 21#define DMAC_BASE IO_ADDRESS(PNX4008_DMA_CONFIG_BASE)
diff --git a/arch/arm/mach-pnx4008/include/mach/io.h b/arch/arm/mach-pnx4008/include/mach/io.h
index c6206f25839d..cbf0904540ea 100644
--- a/arch/arm/mach-pnx4008/include/mach/io.h
+++ b/arch/arm/mach-pnx4008/include/mach/io.h
@@ -15,7 +15,7 @@
15 15
16#define IO_SPACE_LIMIT 0xffffffff 16#define IO_SPACE_LIMIT 0xffffffff
17 17
18#define __io(a) ((void __iomem *)(a)) 18#define __io(a) __typesafe_io(a)
19#define __mem_pci(a) (a) 19#define __mem_pci(a) (a)
20 20
21#endif 21#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/memory.h b/arch/arm/mach-pnx4008/include/mach/memory.h
index 5789a2d16f5a..0e8770081058 100644
--- a/arch/arm/mach-pnx4008/include/mach/memory.h
+++ b/arch/arm/mach-pnx4008/include/mach/memory.h
@@ -16,9 +16,6 @@
16/* 16/*
17 * Physical DRAM offset. 17 * Physical DRAM offset.
18 */ 18 */
19#define PHYS_OFFSET (0x80000000) 19#define PHYS_OFFSET UL(0x80000000)
20
21#define __virt_to_bus(x) ((x) - PAGE_OFFSET + PHYS_OFFSET)
22#define __bus_to_virt(x) ((x) + PAGE_OFFSET - PHYS_OFFSET)
23 20
24#endif 21#endif
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index a062235e83a8..740f0a382bac 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -386,16 +386,19 @@ endmenu
386 386
387config PXA25x 387config PXA25x
388 bool 388 bool
389 select CPU_XSCALE
389 help 390 help
390 Select code specific to PXA21x/25x/26x variants 391 Select code specific to PXA21x/25x/26x variants
391 392
392config PXA27x 393config PXA27x
393 bool 394 bool
395 select CPU_XSCALE
394 help 396 help
395 Select code specific to PXA27x variants 397 Select code specific to PXA27x variants
396 398
397config PXA3xx 399config PXA3xx
398 bool 400 bool
401 select CPU_XSC3
399 help 402 help
400 Select code specific to PXA3xx variants 403 Select code specific to PXA3xx variants
401 404
diff --git a/arch/arm/mach-pxa/dma.c b/arch/arm/mach-pxa/dma.c
index c0be17e0ab82..b1514fb20d3a 100644
--- a/arch/arm/mach-pxa/dma.c
+++ b/arch/arm/mach-pxa/dma.c
@@ -21,7 +21,7 @@
21#include <asm/system.h> 21#include <asm/system.h>
22#include <asm/irq.h> 22#include <asm/irq.h>
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24#include <asm/dma.h> 24#include <mach/dma.h>
25 25
26#include <mach/pxa-regs.h> 26#include <mach/pxa-regs.h>
27 27
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index cc3d850cc0b6..83c56d3abacb 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -21,6 +21,7 @@
21#include <mach/pxafb.h> 21#include <mach/pxafb.h>
22#include <mach/ohci.h> 22#include <mach/ohci.h>
23#include <mach/i2c.h> 23#include <mach/i2c.h>
24#include <mach/hardware.h>
24 25
25#include <mach/mfp-pxa27x.h> 26#include <mach/mfp-pxa27x.h>
26#include <mach/pxa-regs.h> 27#include <mach/pxa-regs.h>
diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h
index 600fd4f76603..262691fb97d8 100644
--- a/arch/arm/mach-pxa/include/mach/io.h
+++ b/arch/arm/mach-pxa/include/mach/io.h
@@ -6,15 +6,13 @@
6#ifndef __ASM_ARM_ARCH_IO_H 6#ifndef __ASM_ARM_ARCH_IO_H
7#define __ASM_ARM_ARCH_IO_H 7#define __ASM_ARM_ARCH_IO_H
8 8
9#include <mach/hardware.h>
10
11#define IO_SPACE_LIMIT 0xffffffff 9#define IO_SPACE_LIMIT 0xffffffff
12 10
13/* 11/*
14 * We don't actually have real ISA nor PCI buses, but there is so many 12 * We don't actually have real ISA nor PCI buses, but there is so many
15 * drivers out there that might just work if we fake them... 13 * drivers out there that might just work if we fake them...
16 */ 14 */
17#define __io(a) ((void __iomem *)(a)) 15#define __io(a) __typesafe_io(a)
18#define __mem_pci(a) (a) 16#define __mem_pci(a) (a)
19 17
20#endif 18#endif
diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
index 59aef89808d6..f626730ee42e 100644
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -18,16 +18,6 @@
18#define PHYS_OFFSET UL(0xa0000000) 18#define PHYS_OFFSET UL(0xa0000000)
19 19
20/* 20/*
21 * Virtual view <-> DMA view memory address translations
22 * virt_to_bus: Used to translate the virtual address to an
23 * address suitable to be passed to set_dma_addr
24 * bus_to_virt: Used to convert an address for DMA operations
25 * to an address that the kernel can use.
26 */
27#define __virt_to_bus(x) __virt_to_phys(x)
28#define __bus_to_virt(x) __phys_to_virt(x)
29
30/*
31 * The nodes are matched with the physical SDRAM banks as follows: 21 * The nodes are matched with the physical SDRAM banks as follows:
32 * 22 *
33 * node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff 23 * node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff
@@ -47,6 +37,7 @@ void cmx2xx_pci_adjust_zones(int node, unsigned long *size,
47 cmx2xx_pci_adjust_zones(node, size, holes) 37 cmx2xx_pci_adjust_zones(node, size, holes)
48 38
49#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) 39#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1)
40#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
50#endif 41#endif
51 42
52#endif 43#endif
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 0842c531ee4d..782903fe9c6c 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -565,7 +565,7 @@ static int mioa701_sys_suspend(struct sys_device *sysdev, pm_message_t state)
565 u32 *mem_resume_unknown = phys_to_virt(RESUME_UNKNOWN_ADDR); 565 u32 *mem_resume_unknown = phys_to_virt(RESUME_UNKNOWN_ADDR);
566 566
567 /* Devices prepare suspend */ 567 /* Devices prepare suspend */
568 is_bt_on = gpio_get_value(GPIO83_BT_ON); 568 is_bt_on = !!gpio_get_value(GPIO83_BT_ON);
569 pxa2xx_mfp_set_lpm(GPIO83_BT_ON, 569 pxa2xx_mfp_set_lpm(GPIO83_BT_ON,
570 is_bt_on ? MFP_LPM_DRIVE_HIGH : MFP_LPM_DRIVE_LOW); 570 is_bt_on ? MFP_LPM_DRIVE_HIGH : MFP_LPM_DRIVE_LOW);
571 571
diff --git a/arch/arm/mach-pxa/mioa701_bootresume.S b/arch/arm/mach-pxa/mioa701_bootresume.S
index a647693d9856..324d25a48c85 100644
--- a/arch/arm/mach-pxa/mioa701_bootresume.S
+++ b/arch/arm/mach-pxa/mioa701_bootresume.S
@@ -24,6 +24,7 @@ ENTRY(mioa701_jumpaddr)
241: 241:
25 mov r0, #0xa0000000 @ Don't suppose memory access works 25 mov r0, #0xa0000000 @ Don't suppose memory access works
26 orr r0, r0, #0x00200000 @ even if it's supposed to 26 orr r0, r0, #0x00200000 @ even if it's supposed to
27 orr r0, r0, #0x0000b000
27 mov r1, #0 28 mov r1, #0
28 str r1, [r0] @ Early disable resume for next boot 29 str r1, [r0] @ Early disable resume for next boot
29 ldr r0, mioa701_jumpaddr @ (Murphy's Law) 30 ldr r0, mioa701_jumpaddr @ (Murphy's Law)
diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c
index ad346addc028..d6f6904132a6 100644
--- a/arch/arm/mach-pxa/smemc.c
+++ b/arch/arm/mach-pxa/smemc.c
@@ -8,6 +8,8 @@
8#include <linux/io.h> 8#include <linux/io.h>
9#include <linux/sysdev.h> 9#include <linux/sysdev.h>
10 10
11#include <mach/hardware.h>
12
11#define SMEMC_PHYS_BASE (0x4A000000) 13#define SMEMC_PHYS_BASE (0x4A000000)
12#define SMEMC_PHYS_SIZE (0x90) 14#define SMEMC_PHYS_SIZE (0x90)
13 15
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index f8a9a62959e5..ef4ddf9d5040 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -22,6 +22,7 @@
22#include <asm/div64.h> 22#include <asm/div64.h>
23#include <asm/mach/irq.h> 23#include <asm/mach/irq.h>
24#include <asm/mach/time.h> 24#include <asm/mach/time.h>
25#include <mach/hardware.h>
25#include <mach/pxa-regs.h> 26#include <mach/pxa-regs.h>
26#include <asm/mach-types.h> 27#include <asm/mach-types.h>
27 28
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index 5ccde7cf39e8..603d1db9baf0 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -10,6 +10,7 @@ config MACH_REALVIEW_EB
10config REALVIEW_EB_ARM11MP 10config REALVIEW_EB_ARM11MP
11 bool "Support ARM11MPCore tile" 11 bool "Support ARM11MPCore tile"
12 depends on MACH_REALVIEW_EB 12 depends on MACH_REALVIEW_EB
13 select CPU_V6
13 help 14 help
14 Enable support for the ARM11MPCore tile on the Realview platform. 15 Enable support for the ARM11MPCore tile on the Realview platform.
15 16
@@ -33,6 +34,7 @@ config MACH_REALVIEW_PB11MP
33 34
34config MACH_REALVIEW_PB1176 35config MACH_REALVIEW_PB1176
35 bool "Support RealView/PB1176 platform" 36 bool "Support RealView/PB1176 platform"
37 select CPU_V6
36 select ARM_GIC 38 select ARM_GIC
37 help 39 help
38 Include support for the ARM(R) RealView ARM1176 Platform Baseboard. 40 Include support for the ARM(R) RealView ARM1176 Platform Baseboard.
diff --git a/arch/arm/mach-realview/include/mach/dma.h b/arch/arm/mach-realview/include/mach/dma.h
deleted file mode 100644
index f1a5a1a10952..000000000000
--- a/arch/arm/mach-realview/include/mach/dma.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * arch/arm/mach-realview/include/mach/dma.h
3 *
4 * Copyright (C) 2003 ARM Limited.
5 * Copyright (C) 1997,1998 Russell King
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
diff --git a/arch/arm/mach-realview/include/mach/io.h b/arch/arm/mach-realview/include/mach/io.h
index aa069424d310..f05bcdf605d8 100644
--- a/arch/arm/mach-realview/include/mach/io.h
+++ b/arch/arm/mach-realview/include/mach/io.h
@@ -22,12 +22,7 @@
22 22
23#define IO_SPACE_LIMIT 0xffffffff 23#define IO_SPACE_LIMIT 0xffffffff
24 24
25static inline void __iomem *__io(unsigned long addr) 25#define __io(a) __typesafe_io(a)
26{ 26#define __mem_pci(a) (a)
27 return (void __iomem *)addr;
28}
29
30#define __io(a) __io(a)
31#define __mem_pci(a) (a)
32 27
33#endif 28#endif
diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h
index 0e673483a141..65a0742094f7 100644
--- a/arch/arm/mach-realview/include/mach/memory.h
+++ b/arch/arm/mach-realview/include/mach/memory.h
@@ -25,14 +25,4 @@
25 */ 25 */
26#define PHYS_OFFSET UL(0x00000000) 26#define PHYS_OFFSET UL(0x00000000)
27 27
28/*
29 * Virtual view <-> DMA view memory address translations
30 * virt_to_bus: Used to translate the virtual address to an
31 * address suitable to be passed to set_dma_addr
32 * bus_to_virt: Used to convert an address for DMA operations
33 * to an address that the kernel can use.
34 */
35#define __virt_to_bus(x) ((x) - PAGE_OFFSET)
36#define __bus_to_virt(x) ((x) + PAGE_OFFSET)
37
38#endif 28#endif
diff --git a/arch/arm/mach-rpc/include/mach/io.h b/arch/arm/mach-rpc/include/mach/io.h
index 9f0553b7ec28..20da7f486e51 100644
--- a/arch/arm/mach-rpc/include/mach/io.h
+++ b/arch/arm/mach-rpc/include/mach/io.h
@@ -18,49 +18,6 @@
18#define IO_SPACE_LIMIT 0xffffffff 18#define IO_SPACE_LIMIT 0xffffffff
19 19
20/* 20/*
21 * GCC is totally crap at loading/storing data. We try to persuade it
22 * to do the right thing by using these whereever possible instead of
23 * the above.
24 */
25#define __arch_base_getb(b,o) \
26 ({ \
27 unsigned int __v, __r = (b); \
28 __asm__ __volatile__( \
29 "ldrb %0, [%1, %2]" \
30 : "=r" (__v) \
31 : "r" (__r), "Ir" (o)); \
32 __v; \
33 })
34
35#define __arch_base_getl(b,o) \
36 ({ \
37 unsigned int __v, __r = (b); \
38 __asm__ __volatile__( \
39 "ldr %0, [%1, %2]" \
40 : "=r" (__v) \
41 : "r" (__r), "Ir" (o)); \
42 __v; \
43 })
44
45#define __arch_base_putb(v,b,o) \
46 ({ \
47 unsigned int __r = (b); \
48 __asm__ __volatile__( \
49 "strb %0, [%1, %2]" \
50 : \
51 : "r" (v), "r" (__r), "Ir" (o));\
52 })
53
54#define __arch_base_putl(v,b,o) \
55 ({ \
56 unsigned int __r = (b); \
57 __asm__ __volatile__( \
58 "str %0, [%1, %2]" \
59 : \
60 : "r" (v), "r" (__r), "Ir" (o));\
61 })
62
63/*
64 * We use two different types of addressing - PC style addresses, and ARM 21 * We use two different types of addressing - PC style addresses, and ARM
65 * addresses. PC style accesses the PC hardware with the normal PC IO 22 * addresses. PC style accesses the PC hardware with the normal PC IO
66 * addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+ 23 * addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+
@@ -232,15 +189,13 @@ DECLARE_IO(int,l,"")
232 result; \ 189 result; \
233}) 190})
234 191
235#define __ioaddrc(port) __ioaddr(port)
236
237#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) 192#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
238#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) 193#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
239#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p)) 194#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p))
240#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p)) 195#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
241#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) 196#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
242#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) 197#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
243#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p)) 198
244/* the following macro is deprecated */ 199/* the following macro is deprecated */
245#define ioaddr(port) ((unsigned long)__ioaddr((port))) 200#define ioaddr(port) ((unsigned long)__ioaddr((port)))
246 201
diff --git a/arch/arm/mach-rpc/include/mach/irqs.h b/arch/arm/mach-rpc/include/mach/irqs.h
index 4ce6ca97f669..3d2037496e38 100644
--- a/arch/arm/mach-rpc/include/mach/irqs.h
+++ b/arch/arm/mach-rpc/include/mach/irqs.h
@@ -44,3 +44,4 @@
44 44
45#define IRQ_TIMER IRQ_TIMER0 45#define IRQ_TIMER IRQ_TIMER0
46 46
47#define NR_IRQS 128
diff --git a/arch/arm/mach-rpc/include/mach/dma.h b/arch/arm/mach-rpc/include/mach/isa-dma.h
index 360b56f8f29f..bad720548587 100644
--- a/arch/arm/mach-rpc/include/mach/dma.h
+++ b/arch/arm/mach-rpc/include/mach/isa-dma.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-rpc/include/mach/dma.h 2 * arch/arm/mach-rpc/include/mach/isa-dma.h
3 * 3 *
4 * Copyright (C) 1997 Russell King 4 * Copyright (C) 1997 Russell King
5 * 5 *
@@ -10,12 +10,6 @@
10#ifndef __ASM_ARCH_DMA_H 10#ifndef __ASM_ARCH_DMA_H
11#define __ASM_ARCH_DMA_H 11#define __ASM_ARCH_DMA_H
12 12
13/*
14 * This is the maximum DMA address that can be DMAd to.
15 * There should not be more than (0xd0000000 - 0xc0000000)
16 * bytes of RAM.
17 */
18#define MAX_DMA_ADDRESS 0xd0000000
19#define MAX_DMA_CHANNELS 8 13#define MAX_DMA_CHANNELS 8
20 14
21#define DMA_0 0 15#define DMA_0 0
diff --git a/arch/arm/mach-rpc/include/mach/memory.h b/arch/arm/mach-rpc/include/mach/memory.h
index 9bf7e43e2863..78191bf25192 100644
--- a/arch/arm/mach-rpc/include/mach/memory.h
+++ b/arch/arm/mach-rpc/include/mach/memory.h
@@ -24,13 +24,6 @@
24#define PHYS_OFFSET UL(0x10000000) 24#define PHYS_OFFSET UL(0x10000000)
25 25
26/* 26/*
27 * These are exactly the same on the RiscPC as the
28 * physical memory view.
29 */
30#define __virt_to_bus(x) __virt_to_phys(x)
31#define __bus_to_virt(x) __phys_to_virt(x)
32
33/*
34 * Cache flushing area - ROM 27 * Cache flushing area - ROM
35 */ 28 */
36#define FLUSH_BASE_PHYS 0x00000000 29#define FLUSH_BASE_PHYS 0x00000000
diff --git a/arch/arm/mach-s3c2400/include/mach/memory.h b/arch/arm/mach-s3c2400/include/mach/memory.h
index 8f4878e4f591..cf5901ffd385 100644
--- a/arch/arm/mach-s3c2400/include/mach/memory.h
+++ b/arch/arm/mach-s3c2400/include/mach/memory.h
@@ -17,7 +17,4 @@
17 17
18#define PHYS_OFFSET UL(0x0C000000) 18#define PHYS_OFFSET UL(0x0C000000)
19 19
20#define __virt_to_bus(x) __virt_to_phys(x)
21#define __bus_to_virt(x) __phys_to_virt(x)
22
23#endif 20#endif
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 99fdc736698c..7315569fbfd7 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -7,6 +7,7 @@
7config CPU_S3C2410 7config CPU_S3C2410
8 bool 8 bool
9 depends on ARCH_S3C2410 9 depends on ARCH_S3C2410
10 select CPU_ARM920T
10 select S3C2410_CLOCK 11 select S3C2410_CLOCK
11 select S3C2410_GPIO 12 select S3C2410_GPIO
12 select CPU_LLSERIAL_S3C2410 13 select CPU_LLSERIAL_S3C2410
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 7d914a470b6c..552b4c778fdc 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -17,7 +17,6 @@
17#include <linux/sysdev.h> 17#include <linux/sysdev.h>
18#include <linux/serial_core.h> 18#include <linux/serial_core.h>
19 19
20#include <asm/dma.h>
21#include <mach/dma.h> 20#include <mach/dma.h>
22 21
23#include <plat/cpu.h> 22#include <plat/cpu.h>
@@ -25,12 +24,12 @@
25 24
26#include <plat/regs-serial.h> 25#include <plat/regs-serial.h>
27#include <mach/regs-gpio.h> 26#include <mach/regs-gpio.h>
28#include <asm/plat-s3c/regs-ac97.h> 27#include <plat/regs-ac97.h>
29#include <mach/regs-mem.h> 28#include <mach/regs-mem.h>
30#include <mach/regs-lcd.h> 29#include <mach/regs-lcd.h>
31#include <mach/regs-sdi.h> 30#include <mach/regs-sdi.h>
32#include <asm/plat-s3c24xx/regs-iis.h> 31#include <asm/plat-s3c24xx/regs-iis.h>
33#include <asm/plat-s3c24xx/regs-spi.h> 32#include <plat/regs-spi.h>
34 33
35static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = { 34static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
36 [DMACH_XD0] = { 35 [DMACH_XD0] = {
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index 891b53cd69b8..13358ce2128c 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -16,11 +16,6 @@
16#include <linux/sysdev.h> 16#include <linux/sysdev.h>
17#include <mach/hardware.h> 17#include <mach/hardware.h>
18 18
19/*
20 * This is the maximum DMA address(physical address) that can be DMAd to.
21 *
22 */
23#define MAX_DMA_ADDRESS 0x40000000
24#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ 19#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
25 20
26/* We use `virtual` dma channels to hide the fact we have only a limited 21/* We use `virtual` dma channels to hide the fact we have only a limited
@@ -254,7 +249,7 @@ typedef unsigned long dma_device_t;
254 * request a dma channel exclusivley 249 * request a dma channel exclusivley
255*/ 250*/
256 251
257extern int s3c2410_dma_request(dmach_t channel, 252extern int s3c2410_dma_request(unsigned int channel,
258 struct s3c2410_dma_client *, void *dev); 253 struct s3c2410_dma_client *, void *dev);
259 254
260 255
@@ -263,14 +258,14 @@ extern int s3c2410_dma_request(dmach_t channel,
263 * change the state of the dma channel 258 * change the state of the dma channel
264*/ 259*/
265 260
266extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op); 261extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
267 262
268/* s3c2410_dma_setflags 263/* s3c2410_dma_setflags
269 * 264 *
270 * set the channel's flags to a given state 265 * set the channel's flags to a given state
271*/ 266*/
272 267
273extern int s3c2410_dma_setflags(dmach_t channel, 268extern int s3c2410_dma_setflags(unsigned int channel,
274 unsigned int flags); 269 unsigned int flags);
275 270
276/* s3c2410_dma_free 271/* s3c2410_dma_free
@@ -278,7 +273,7 @@ extern int s3c2410_dma_setflags(dmach_t channel,
278 * free the dma channel (will also abort any outstanding operations) 273 * free the dma channel (will also abort any outstanding operations)
279*/ 274*/
280 275
281extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *); 276extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
282 277
283/* s3c2410_dma_enqueue 278/* s3c2410_dma_enqueue
284 * 279 *
@@ -287,7 +282,7 @@ extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *);
287 * drained before the buffer is given to the DMA system. 282 * drained before the buffer is given to the DMA system.
288*/ 283*/
289 284
290extern int s3c2410_dma_enqueue(dmach_t channel, void *id, 285extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
291 dma_addr_t data, int size); 286 dma_addr_t data, int size);
292 287
293/* s3c2410_dma_config 288/* s3c2410_dma_config
@@ -295,7 +290,7 @@ extern int s3c2410_dma_enqueue(dmach_t channel, void *id,
295 * configure the dma channel 290 * configure the dma channel
296*/ 291*/
297 292
298extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon); 293extern int s3c2410_dma_config(unsigned int channel, int xferunit, int dcon);
299 294
300/* s3c2410_dma_devconfig 295/* s3c2410_dma_devconfig
301 * 296 *
@@ -310,11 +305,11 @@ extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
310 * get the position that the dma transfer is currently at 305 * get the position that the dma transfer is currently at
311*/ 306*/
312 307
313extern int s3c2410_dma_getposition(dmach_t channel, 308extern int s3c2410_dma_getposition(unsigned int channel,
314 dma_addr_t *src, dma_addr_t *dest); 309 dma_addr_t *src, dma_addr_t *dest);
315 310
316extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn); 311extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
317extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn); 312extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
318 313
319/* DMA Register definitions */ 314/* DMA Register definitions */
320 315
diff --git a/arch/arm/mach-s3c2410/include/mach/memory.h b/arch/arm/mach-s3c2410/include/mach/memory.h
index 93782628a786..6f1e5871ae4b 100644
--- a/arch/arm/mach-s3c2410/include/mach/memory.h
+++ b/arch/arm/mach-s3c2410/include/mach/memory.h
@@ -13,7 +13,4 @@
13 13
14#define PHYS_OFFSET UL(0x30000000) 14#define PHYS_OFFSET UL(0x30000000)
15 15
16#define __virt_to_bus(x) __virt_to_phys(x)
17#define __bus_to_virt(x) __phys_to_virt(x)
18
19#endif 16#endif
diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h
index 43535a0e7186..7613d0a384ba 100644
--- a/arch/arm/mach-s3c2410/include/mach/system-reset.h
+++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h
@@ -13,7 +13,7 @@
13#include <mach/hardware.h> 13#include <mach/hardware.h>
14#include <linux/io.h> 14#include <linux/io.h>
15 15
16#include <asm/plat-s3c/regs-watchdog.h> 16#include <plat/regs-watchdog.h>
17#include <mach/regs-clock.h> 17#include <mach/regs-clock.h>
18 18
19#include <linux/clk.h> 19#include <linux/clk.h>
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 8db9c700e3c2..c04c24444e0d 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -44,8 +44,8 @@
44#include <mach/regs-mem.h> 44#include <mach/regs-mem.h>
45#include <mach/regs-lcd.h> 45#include <mach/regs-lcd.h>
46 46
47#include <asm/plat-s3c/nand.h> 47#include <plat/nand.h>
48#include <asm/plat-s3c/iic.h> 48#include <plat/iic.h>
49#include <mach/fb.h> 49#include <mach/fb.h>
50 50
51#include <linux/mtd/mtd.h> 51#include <linux/mtd/mtd.h>
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 98716d0108e9..32d550fcff4d 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -38,7 +38,7 @@
38#include <mach/h1940.h> 38#include <mach/h1940.h>
39#include <mach/h1940-latch.h> 39#include <mach/h1940-latch.h>
40#include <mach/fb.h> 40#include <mach/fb.h>
41#include <asm/plat-s3c24xx/udc.h> 41#include <plat/udc.h>
42 42
43#include <plat/clock.h> 43#include <plat/clock.h>
44#include <plat/devs.h> 44#include <plat/devs.h>
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 82505517846c..7a7c45d28fe7 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -40,14 +40,14 @@
40#include <asm/mach/irq.h> 40#include <asm/mach/irq.h>
41#include <asm/mach/map.h> 41#include <asm/mach/map.h>
42 42
43#include <asm/plat-s3c/iic.h> 43#include <plat/iic.h>
44#include <plat/regs-serial.h> 44#include <plat/regs-serial.h>
45 45
46#include <plat/clock.h> 46#include <plat/clock.h>
47#include <plat/cpu.h> 47#include <plat/cpu.h>
48#include <plat/devs.h> 48#include <plat/devs.h>
49#include <plat/s3c2410.h> 49#include <plat/s3c2410.h>
50#include <asm/plat-s3c24xx/udc.h> 50#include <plat/udc.h>
51 51
52static struct map_desc n30_iodesc[] __initdata = { 52static struct map_desc n30_iodesc[] __initdata = {
53 /* nothing here yet */ 53 /* nothing here yet */
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 661807e14e8a..ef868472f6a4 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -50,8 +50,8 @@
50#include <mach/leds-gpio.h> 50#include <mach/leds-gpio.h>
51#include <plat/regs-serial.h> 51#include <plat/regs-serial.h>
52#include <mach/fb.h> 52#include <mach/fb.h>
53#include <asm/plat-s3c/nand.h> 53#include <plat/nand.h>
54#include <asm/plat-s3c24xx/udc.h> 54#include <plat/udc.h>
55#include <mach/spi.h> 55#include <mach/spi.h>
56#include <mach/spi-gpio.h> 56#include <mach/spi-gpio.h>
57 57
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index c59a9d2ee9a6..ca99564ae4b5 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -7,6 +7,7 @@
7config CPU_S3C2412 7config CPU_S3C2412
8 bool 8 bool
9 depends on ARCH_S3C2410 9 depends on ARCH_S3C2410
10 select CPU_ARM926T
10 select CPU_LLSERIAL_S3C2440 11 select CPU_LLSERIAL_S3C2440
11 select S3C2412_PM if PM 12 select S3C2412_PM if PM
12 select S3C2412_DMA if S3C2410_DMA 13 select S3C2412_DMA if S3C2410_DMA
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index ba0591e71f32..919856c9433f 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -18,7 +18,6 @@
18#include <linux/serial_core.h> 18#include <linux/serial_core.h>
19#include <linux/io.h> 19#include <linux/io.h>
20 20
21#include <asm/dma.h>
22#include <mach/dma.h> 21#include <mach/dma.h>
23 22
24#include <plat/dma.h> 23#include <plat/dma.h>
@@ -26,13 +25,13 @@
26 25
27#include <plat/regs-serial.h> 26#include <plat/regs-serial.h>
28#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
29#include <asm/plat-s3c/regs-ac97.h> 28#include <plat/regs-ac97.h>
30#include <mach/regs-mem.h> 29#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h> 30#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h> 31#include <mach/regs-sdi.h>
33#include <asm/plat-s3c24xx/regs-s3c2412-iis.h> 32#include <asm/plat-s3c24xx/regs-s3c2412-iis.h>
34#include <asm/plat-s3c24xx/regs-iis.h> 33#include <asm/plat-s3c24xx/regs-iis.h>
35#include <asm/plat-s3c24xx/regs-spi.h> 34#include <plat/regs-spi.h>
36 35
37#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID } 36#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
38 37
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index b08f18c8c47a..25ff1ec9f8ad 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -31,8 +31,8 @@
31#include <asm/mach/irq.h> 31#include <asm/mach/irq.h>
32 32
33#include <plat/regs-serial.h> 33#include <plat/regs-serial.h>
34#include <asm/plat-s3c/nand.h> 34#include <plat/nand.h>
35#include <asm/plat-s3c/iic.h> 35#include <plat/iic.h>
36 36
37#include <mach/regs-power.h> 37#include <mach/regs-power.h>
38#include <mach/regs-gpio.h> 38#include <mach/regs-gpio.h>
@@ -52,7 +52,7 @@
52#include <plat/devs.h> 52#include <plat/devs.h>
53#include <plat/cpu.h> 53#include <plat/cpu.h>
54#include <plat/pm.h> 54#include <plat/pm.h>
55#include <asm/plat-s3c24xx/udc.h> 55#include <plat/udc.h>
56 56
57static struct map_desc jive_iodesc[] __initdata = { 57static struct map_desc jive_iodesc[] __initdata = {
58}; 58};
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index c719b5a740a9..8fd17b8d5679 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -37,7 +37,7 @@
37#include <mach/regs-lcd.h> 37#include <mach/regs-lcd.h>
38 38
39#include <mach/idle.h> 39#include <mach/idle.h>
40#include <asm/plat-s3c24xx/udc.h> 40#include <plat/udc.h>
41#include <mach/fb.h> 41#include <mach/fb.h>
42 42
43#include <plat/s3c2410.h> 43#include <plat/s3c2410.h>
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index 4cfa19ad9be0..da32a6cb17ae 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -39,7 +39,7 @@
39#include <mach/idle.h> 39#include <mach/idle.h>
40#include <mach/fb.h> 40#include <mach/fb.h>
41 41
42#include <asm/plat-s3c/nand.h> 42#include <plat/nand.h>
43 43
44#include <plat/s3c2410.h> 44#include <plat/s3c2410.h>
45#include <plat/s3c2412.h> 45#include <plat/s3c2412.h>
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index 313759c3da69..a086818e117e 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -39,7 +39,7 @@
39#include <mach/regs-gpio.h> 39#include <mach/regs-gpio.h>
40#include <mach/regs-gpioj.h> 40#include <mach/regs-gpioj.h>
41#include <mach/regs-dsc.h> 41#include <mach/regs-dsc.h>
42#include <asm/plat-s3c24xx/regs-spi.h> 42#include <plat/regs-spi.h>
43#include <mach/regs-s3c2412.h> 43#include <mach/regs-s3c2412.h>
44 44
45#include <plat/s3c2412.h> 45#include <plat/s3c2412.h>
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index 25de042ab996..0429d255b0d8 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -7,6 +7,7 @@
7config CPU_S3C2440 7config CPU_S3C2440
8 bool 8 bool
9 depends on ARCH_S3C2410 9 depends on ARCH_S3C2410
10 select CPU_ARM920T
10 select S3C2410_CLOCK 11 select S3C2410_CLOCK
11 select S3C2410_PM if PM 12 select S3C2410_PM if PM
12 select S3C2410_GPIO 13 select S3C2410_GPIO
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index 32303f6a8321..5b5ee0b8f4e0 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -17,7 +17,6 @@
17#include <linux/sysdev.h> 17#include <linux/sysdev.h>
18#include <linux/serial_core.h> 18#include <linux/serial_core.h>
19 19
20#include <asm/dma.h>
21#include <mach/dma.h> 20#include <mach/dma.h>
22 21
23#include <plat/dma.h> 22#include <plat/dma.h>
@@ -25,12 +24,12 @@
25 24
26#include <plat/regs-serial.h> 25#include <plat/regs-serial.h>
27#include <mach/regs-gpio.h> 26#include <mach/regs-gpio.h>
28#include <asm/plat-s3c/regs-ac97.h> 27#include <plat/regs-ac97.h>
29#include <mach/regs-mem.h> 28#include <mach/regs-mem.h>
30#include <mach/regs-lcd.h> 29#include <mach/regs-lcd.h>
31#include <mach/regs-sdi.h> 30#include <mach/regs-sdi.h>
32#include <asm/plat-s3c24xx/regs-iis.h> 31#include <asm/plat-s3c24xx/regs-iis.h>
33#include <asm/plat-s3c24xx/regs-spi.h> 32#include <plat/regs-spi.h>
34 33
35static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = { 34static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
36 [DMACH_XD0] = { 35 [DMACH_XD0] = {
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index e2beca470484..334379bdfc6e 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -39,7 +39,7 @@
39#include <mach/regs-gpio.h> 39#include <mach/regs-gpio.h>
40#include <mach/regs-mem.h> 40#include <mach/regs-mem.h>
41#include <mach/regs-lcd.h> 41#include <mach/regs-lcd.h>
42#include <asm/plat-s3c/nand.h> 42#include <plat/nand.h>
43 43
44#include <linux/mtd/mtd.h> 44#include <linux/mtd/mtd.h>
45#include <linux/mtd/nand.h> 45#include <linux/mtd/nand.h>
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 66876c6f2f1c..07b42a0207d1 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -35,7 +35,7 @@
35#include <mach/regs-gpio.h> 35#include <mach/regs-gpio.h>
36#include <mach/regs-mem.h> 36#include <mach/regs-mem.h>
37#include <mach/regs-lcd.h> 37#include <mach/regs-lcd.h>
38#include <asm/plat-s3c/nand.h> 38#include <plat/nand.h>
39 39
40#include <linux/mtd/mtd.h> 40#include <linux/mtd/mtd.h>
41#include <linux/mtd/nand.h> 41#include <linux/mtd/nand.h>
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 2361d606abc5..884a3c7ae75f 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -37,7 +37,7 @@
37#include <mach/regs-gpio.h> 37#include <mach/regs-gpio.h>
38#include <mach/regs-mem.h> 38#include <mach/regs-mem.h>
39#include <mach/regs-lcd.h> 39#include <mach/regs-lcd.h>
40#include <asm/plat-s3c/nand.h> 40#include <plat/nand.h>
41 41
42#include <linux/mtd/mtd.h> 42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h> 43#include <linux/mtd/nand.h>
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index 4d14c7cff892..fbd081de592f 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -42,7 +42,7 @@
42#include <mach/regs-lcd.h> 42#include <mach/regs-lcd.h>
43 43
44#include <mach/h1940.h> 44#include <mach/h1940.h>
45#include <asm/plat-s3c/nand.h> 45#include <plat/nand.h>
46#include <mach/fb.h> 46#include <mach/fb.h>
47 47
48#include <plat/clock.h> 48#include <plat/clock.h>
diff --git a/arch/arm/mach-s3c2442/Kconfig b/arch/arm/mach-s3c2442/Kconfig
index 26d131a77074..b289d198020e 100644
--- a/arch/arm/mach-s3c2442/Kconfig
+++ b/arch/arm/mach-s3c2442/Kconfig
@@ -7,6 +7,7 @@
7config CPU_S3C2442 7config CPU_S3C2442
8 bool 8 bool
9 depends on ARCH_S3C2410 9 depends on ARCH_S3C2410
10 select CPU_ARM920T
10 select S3C2410_CLOCK 11 select S3C2410_CLOCK
11 select S3C2410_GPIO 12 select S3C2410_GPIO
12 select S3C2410_PM if PM 13 select S3C2410_PM if PM
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index f73ccb25ff94..2a58a4d5aa5a 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -18,7 +18,6 @@
18#include <linux/serial_core.h> 18#include <linux/serial_core.h>
19#include <linux/io.h> 19#include <linux/io.h>
20 20
21#include <asm/dma.h>
22#include <mach/dma.h> 21#include <mach/dma.h>
23 22
24#include <plat/dma.h> 23#include <plat/dma.h>
@@ -26,12 +25,12 @@
26 25
27#include <plat/regs-serial.h> 26#include <plat/regs-serial.h>
28#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
29#include <asm/plat-s3c/regs-ac97.h> 28#include <plat/regs-ac97.h>
30#include <mach/regs-mem.h> 29#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h> 30#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h> 31#include <mach/regs-sdi.h>
33#include <asm/plat-s3c24xx/regs-iis.h> 32#include <asm/plat-s3c24xx/regs-iis.h>
34#include <asm/plat-s3c24xx/regs-spi.h> 33#include <plat/regs-spi.h>
35 34
36#define MAP(x) { \ 35#define MAP(x) { \
37 [0] = (x) | DMA_CH_VALID, \ 36 [0] = (x) | DMA_CH_VALID, \
diff --git a/arch/arm/mach-sa1100/collie_pm.c b/arch/arm/mach-sa1100/collie_pm.c
index b1161fc80602..947883a483df 100644
--- a/arch/arm/mach-sa1100/collie_pm.c
+++ b/arch/arm/mach-sa1100/collie_pm.c
@@ -26,7 +26,7 @@
26#include <asm/irq.h> 26#include <asm/irq.h>
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <asm/hardware/scoop.h> 28#include <asm/hardware/scoop.h>
29#include <asm/dma.h> 29#include <mach/dma.h>
30#include <mach/collie.h> 30#include <mach/collie.h>
31#include <asm/mach/sharpsl_param.h> 31#include <asm/mach/sharpsl_param.h>
32#include <asm/hardware/sharpsl_pm.h> 32#include <asm/hardware/sharpsl_pm.h>
diff --git a/arch/arm/mach-sa1100/dma.c b/arch/arm/mach-sa1100/dma.c
index f990a3e85846..3f445ffd99f8 100644
--- a/arch/arm/mach-sa1100/dma.c
+++ b/arch/arm/mach-sa1100/dma.c
@@ -19,7 +19,7 @@
19#include <asm/system.h> 19#include <asm/system.h>
20#include <asm/irq.h> 20#include <asm/irq.h>
21#include <mach/hardware.h> 21#include <mach/hardware.h>
22#include <asm/dma.h> 22#include <mach/dma.h>
23 23
24 24
25#undef DEBUG 25#undef DEBUG
diff --git a/arch/arm/mach-sa1100/include/mach/io.h b/arch/arm/mach-sa1100/include/mach/io.h
index 0c070a6149bc..d8b43f3dcd2d 100644
--- a/arch/arm/mach-sa1100/include/mach/io.h
+++ b/arch/arm/mach-sa1100/include/mach/io.h
@@ -16,11 +16,7 @@
16 * We don't actually have real ISA nor PCI buses, but there is so many 16 * We don't actually have real ISA nor PCI buses, but there is so many
17 * drivers out there that might just work if we fake them... 17 * drivers out there that might just work if we fake them...
18 */ 18 */
19static inline void __iomem *__io(unsigned long addr) 19#define __io(a) __typesafe_io(a)
20{ 20#define __mem_pci(a) (a)
21 return (void __iomem *)addr;
22}
23#define __io(a) __io(a)
24#define __mem_pci(a) (a)
25 21
26#endif 22#endif
diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h
index 1c127b68581d..e9f8eed900f5 100644
--- a/arch/arm/mach-sa1100/include/mach/memory.h
+++ b/arch/arm/mach-sa1100/include/mach/memory.h
@@ -23,23 +23,12 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
23 sa1111_adjust_zones(node, size, holes) 23 sa1111_adjust_zones(node, size, holes)
24 24
25#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1) 25#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1)
26#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_1M)
26 27
27#endif 28#endif
28#endif 29#endif
29 30
30/* 31/*
31 * Virtual view <-> DMA view memory address translations
32 * virt_to_bus: Used to translate the virtual address to an
33 * address suitable to be passed to set_dma_addr
34 * bus_to_virt: Used to convert an address for DMA operations
35 * to an address that the kernel can use.
36 *
37 * On the SA1100, bus addresses are equivalent to physical addresses.
38 */
39#define __virt_to_bus(x) __virt_to_phys(x)
40#define __bus_to_virt(x) __phys_to_virt(x)
41
42/*
43 * Because of the wide memory address space between physical RAM banks on the 32 * Because of the wide memory address space between physical RAM banks on the
44 * SA1100, it's much convenient to use Linux's SparseMEM support to implement 33 * SA1100, it's much convenient to use Linux's SparseMEM support to implement
45 * our memory map representation. Assuming all memory nodes have equal access 34 * our memory map representation. Assuming all memory nodes have equal access
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index a9400d984451..a23fd3d0163a 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -16,6 +16,8 @@
16#include <asm/leds.h> 16#include <asm/leds.h>
17#include <asm/param.h> 17#include <asm/param.h>
18 18
19#include <mach/hardware.h>
20
19#include <asm/mach/map.h> 21#include <asm/mach/map.h>
20#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
21#include <asm/mach/time.h> 23#include <asm/mach/time.h>
diff --git a/arch/arm/mach-shark/include/mach/hardware.h b/arch/arm/mach-shark/include/mach/hardware.h
index cb0ee2943c1a..01bf76099ce5 100644
--- a/arch/arm/mach-shark/include/mach/hardware.h
+++ b/arch/arm/mach-shark/include/mach/hardware.h
@@ -28,8 +28,6 @@
28#define ROMCARD_SIZE 0x08000000 28#define ROMCARD_SIZE 0x08000000
29#define ROMCARD_START 0x10000000 29#define ROMCARD_START 0x10000000
30 30
31#define PCIO_BASE 0xe0000000
32
33 31
34/* defines for the Framebuffer */ 32/* defines for the Framebuffer */
35#define FB_START 0x06000000 33#define FB_START 0x06000000
diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h
index 92475922c068..c5cee829fc87 100644
--- a/arch/arm/mach-shark/include/mach/io.h
+++ b/arch/arm/mach-shark/include/mach/io.h
@@ -11,46 +11,10 @@
11#ifndef __ASM_ARM_ARCH_IO_H 11#ifndef __ASM_ARM_ARCH_IO_H
12#define __ASM_ARM_ARCH_IO_H 12#define __ASM_ARM_ARCH_IO_H
13 13
14#include <mach/hardware.h> 14#define PCIO_BASE 0xe0000000
15#define IO_SPACE_LIMIT 0xffffffff
15 16
16#define IO_SPACE_LIMIT 0xffffffff 17#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
17 18#define __mem_pci(addr) (addr)
18/*
19 * We use two different types of addressing - PC style addresses, and ARM
20 * addresses. PC style accesses the PC hardware with the normal PC IO
21 * addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+
22 * and are translated to the start of IO.
23 */
24#define __PORT_PCIO(x) (!((x) & 0x80000000))
25
26#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
27
28
29static inline unsigned int __ioaddr (unsigned int port) \
30{ \
31 if (__PORT_PCIO(port)) \
32 return (unsigned int)(PCIO_BASE + (port)); \
33 else \
34 return (unsigned int)(IO_BASE + (port)); \
35}
36
37#define __mem_pci(addr) (addr)
38
39/*
40 * Translated address IO functions
41 *
42 * IO address has already been translated to a virtual address
43 */
44#define outb_t(v,p) \
45 (*(volatile unsigned char *)(p) = (v))
46
47#define inb_t(p) \
48 (*(volatile unsigned char *)(p))
49
50#define outl_t(v,p) \
51 (*(volatile unsigned long *)(p) = (v))
52
53#define inl_t(p) \
54 (*(volatile unsigned long *)(p))
55 19
56#endif 20#endif
diff --git a/arch/arm/mach-shark/include/mach/dma.h b/arch/arm/mach-shark/include/mach/isa-dma.h
index c0a29bd2a74f..864298ff3927 100644
--- a/arch/arm/mach-shark/include/mach/dma.h
+++ b/arch/arm/mach-shark/include/mach/isa-dma.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-shark/include/mach/dma.h 2 * arch/arm/mach-shark/include/mach/isa-dma.h
3 * 3 *
4 * by Alexander Schulz 4 * by Alexander Schulz
5 */ 5 */
@@ -10,7 +10,6 @@
10 * The rest is not DMAable. See dev / .properties 10 * The rest is not DMAable. See dev / .properties
11 * in OpenFirmware. 11 * in OpenFirmware.
12 */ 12 */
13#define MAX_DMA_ADDRESS 0xC0400000
14#define MAX_DMA_CHANNELS 8 13#define MAX_DMA_CHANNELS 8
15#define DMA_ISA_CASCADE 4 14#define DMA_ISA_CASCADE 4
16 15
diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h
index b7874ad9f9f6..c5ab038925d6 100644
--- a/arch/arm/mach-shark/include/mach/memory.h
+++ b/arch/arm/mach-shark/include/mach/memory.h
@@ -33,12 +33,10 @@ static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsig
33 __arch_adjust_zones(node, size, holes) 33 __arch_adjust_zones(node, size, holes)
34 34
35#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_4M - 1) 35#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_4M - 1)
36#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_4M)
36 37
37#endif 38#endif
38 39
39#define __virt_to_bus(x) __virt_to_phys(x)
40#define __bus_to_virt(x) __phys_to_virt(x)
41
42/* 40/*
43 * Cache flushing area 41 * Cache flushing area
44 */ 42 */
diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig
index 95096afd5271..c781f30c8368 100644
--- a/arch/arm/mach-versatile/Kconfig
+++ b/arch/arm/mach-versatile/Kconfig
@@ -3,12 +3,14 @@ menu "Versatile platform type"
3 3
4config ARCH_VERSATILE_PB 4config ARCH_VERSATILE_PB
5 bool "Support Versatile/PB platform" 5 bool "Support Versatile/PB platform"
6 select CPU_ARM926T
6 default y 7 default y
7 help 8 help
8 Include support for the ARM(R) Versatile/PB platform. 9 Include support for the ARM(R) Versatile/PB platform.
9 10
10config MACH_VERSATILE_AB 11config MACH_VERSATILE_AB
11 bool "Support Versatile/AB platform" 12 bool "Support Versatile/AB platform"
13 select CPU_ARM926T
12 help 14 help
13 Include support for the ARM(R) Versatile/AP platform. 15 Include support for the ARM(R) Versatile/AP platform.
14 16
diff --git a/arch/arm/mach-versatile/include/mach/dma.h b/arch/arm/mach-versatile/include/mach/dma.h
deleted file mode 100644
index 0aabf12c8834..000000000000
--- a/arch/arm/mach-versatile/include/mach/dma.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * arch/arm/mach-versatile/include/mach/dma.h
3 *
4 * Copyright (C) 2003 ARM Limited.
5 * Copyright (C) 1997,1998 Russell King
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-versatile/include/mach/io.h
index c0b9dd1d0257..f067c14c7182 100644
--- a/arch/arm/mach-versatile/include/mach/io.h
+++ b/arch/arm/mach-versatile/include/mach/io.h
@@ -22,11 +22,7 @@
22 22
23#define IO_SPACE_LIMIT 0xffffffff 23#define IO_SPACE_LIMIT 0xffffffff
24 24
25static inline void __iomem *__io(unsigned long addr) 25#define __io(a) __typesafe_io(a)
26{ 26#define __mem_pci(a) (a)
27 return (void __iomem *)addr;
28}
29#define __io(a) __io(a)
30#define __mem_pci(a) (a)
31 27
32#endif 28#endif
diff --git a/arch/arm/mach-versatile/include/mach/irqs.h b/arch/arm/mach-versatile/include/mach/irqs.h
index 216a1312e62e..9bfdb30e1f3f 100644
--- a/arch/arm/mach-versatile/include/mach/irqs.h
+++ b/arch/arm/mach-versatile/include/mach/irqs.h
@@ -60,39 +60,6 @@
60#define IRQ_VICSOURCE31 (IRQ_VIC_START + INT_VICSOURCE31) 60#define IRQ_VICSOURCE31 (IRQ_VIC_START + INT_VICSOURCE31)
61#define IRQ_VIC_END (IRQ_VIC_START + 31) 61#define IRQ_VIC_END (IRQ_VIC_START + 31)
62 62
63#define IRQMASK_WDOGINT INTMASK_WDOGINT
64#define IRQMASK_SOFTINT INTMASK_SOFTINT
65#define IRQMASK_COMMRx INTMASK_COMMRx
66#define IRQMASK_COMMTx INTMASK_COMMTx
67#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
68#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
69#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0
70#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1
71#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2
72#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3
73#define IRQMASK_RTCINT INTMASK_RTCINT
74#define IRQMASK_SSPINT INTMASK_SSPINT
75#define IRQMASK_UARTINT0 INTMASK_UARTINT0
76#define IRQMASK_UARTINT1 INTMASK_UARTINT1
77#define IRQMASK_UARTINT2 INTMASK_UARTINT2
78#define IRQMASK_SCIINT INTMASK_SCIINT
79#define IRQMASK_CLCDINT INTMASK_CLCDINT
80#define IRQMASK_DMAINT INTMASK_DMAINT
81#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT
82#define IRQMASK_MBXINT INTMASK_MBXINT
83#define IRQMASK_GNDINT INTMASK_GNDINT
84#define IRQMASK_VICSOURCE21 INTMASK_VICSOURCE21
85#define IRQMASK_VICSOURCE22 INTMASK_VICSOURCE22
86#define IRQMASK_VICSOURCE23 INTMASK_VICSOURCE23
87#define IRQMASK_VICSOURCE24 INTMASK_VICSOURCE24
88#define IRQMASK_VICSOURCE25 INTMASK_VICSOURCE25
89#define IRQMASK_VICSOURCE26 INTMASK_VICSOURCE26
90#define IRQMASK_VICSOURCE27 INTMASK_VICSOURCE27
91#define IRQMASK_VICSOURCE28 INTMASK_VICSOURCE28
92#define IRQMASK_VICSOURCE29 INTMASK_VICSOURCE29
93#define IRQMASK_VICSOURCE30 INTMASK_VICSOURCE30
94#define IRQMASK_VICSOURCE31 INTMASK_VICSOURCE31
95
96/* 63/*
97 * FIQ interrupts definitions are the same as the INT definitions. 64 * FIQ interrupts definitions are the same as the INT definitions.
98 */ 65 */
@@ -130,39 +97,6 @@
130#define FIQ_VICSOURCE31 INT_VICSOURCE31 97#define FIQ_VICSOURCE31 INT_VICSOURCE31
131 98
132 99
133#define FIQMASK_WDOGINT INTMASK_WDOGINT
134#define FIQMASK_SOFTINT INTMASK_SOFTINT
135#define FIQMASK_COMMRx INTMASK_COMMRx
136#define FIQMASK_COMMTx INTMASK_COMMTx
137#define FIQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
138#define FIQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
139#define FIQMASK_GPIOINT0 INTMASK_GPIOINT0
140#define FIQMASK_GPIOINT1 INTMASK_GPIOINT1
141#define FIQMASK_GPIOINT2 INTMASK_GPIOINT2
142#define FIQMASK_GPIOINT3 INTMASK_GPIOINT3
143#define FIQMASK_RTCINT INTMASK_RTCINT
144#define FIQMASK_SSPINT INTMASK_SSPINT
145#define FIQMASK_UARTINT0 INTMASK_UARTINT0
146#define FIQMASK_UARTINT1 INTMASK_UARTINT1
147#define FIQMASK_UARTINT2 INTMASK_UARTINT2
148#define FIQMASK_SCIINT INTMASK_SCIINT
149#define FIQMASK_CLCDINT INTMASK_CLCDINT
150#define FIQMASK_DMAINT INTMASK_DMAINT
151#define FIQMASK_PWRFAILINT INTMASK_PWRFAILINT
152#define FIQMASK_MBXINT INTMASK_MBXINT
153#define FIQMASK_GNDINT INTMASK_GNDINT
154#define FIQMASK_VICSOURCE21 INTMASK_VICSOURCE21
155#define FIQMASK_VICSOURCE22 INTMASK_VICSOURCE22
156#define FIQMASK_VICSOURCE23 INTMASK_VICSOURCE23
157#define FIQMASK_VICSOURCE24 INTMASK_VICSOURCE24
158#define FIQMASK_VICSOURCE25 INTMASK_VICSOURCE25
159#define FIQMASK_VICSOURCE26 INTMASK_VICSOURCE26
160#define FIQMASK_VICSOURCE27 INTMASK_VICSOURCE27
161#define FIQMASK_VICSOURCE28 INTMASK_VICSOURCE28
162#define FIQMASK_VICSOURCE29 INTMASK_VICSOURCE29
163#define FIQMASK_VICSOURCE30 INTMASK_VICSOURCE30
164#define FIQMASK_VICSOURCE31 INTMASK_VICSOURCE31
165
166/* 100/*
167 * Secondary interrupt controller 101 * Secondary interrupt controller
168 */ 102 */
@@ -188,24 +122,4 @@
188#define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3) 122#define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3)
189#define IRQ_SIC_END 63 123#define IRQ_SIC_END 63
190 124
191#define SIC_IRQMASK_MMCI0B SIC_INTMASK_MMCI0B
192#define SIC_IRQMASK_MMCI1B SIC_INTMASK_MMCI1B
193#define SIC_IRQMASK_KMI0 SIC_INTMASK_KMI0
194#define SIC_IRQMASK_KMI1 SIC_INTMASK_KMI1
195#define SIC_IRQMASK_SCI3 SIC_INTMASK_SCI3
196#define SIC_IRQMASK_UART3 SIC_INTMASK_UART3
197#define SIC_IRQMASK_CLCD SIC_INTMASK_CLCD
198#define SIC_IRQMASK_TOUCH SIC_INTMASK_TOUCH
199#define SIC_IRQMASK_KEYPAD SIC_INTMASK_KEYPAD
200#define SIC_IRQMASK_DoC SIC_INTMASK_DoC
201#define SIC_IRQMASK_MMCI0A SIC_INTMASK_MMCI0A
202#define SIC_IRQMASK_MMCI1A SIC_INTMASK_MMCI1A
203#define SIC_IRQMASK_AACI SIC_INTMASK_AACI
204#define SIC_IRQMASK_ETH SIC_INTMASK_ETH
205#define SIC_IRQMASK_USB SIC_INTMASK_USB
206#define SIC_IRQMASK_PCI0 SIC_INTMASK_PCI0
207#define SIC_IRQMASK_PCI1 SIC_INTMASK_PCI1
208#define SIC_IRQMASK_PCI2 SIC_INTMASK_PCI2
209#define SIC_IRQMASK_PCI3 SIC_INTMASK_PCI3
210
211#define NR_IRQS 64 125#define NR_IRQS 64
diff --git a/arch/arm/mach-versatile/include/mach/memory.h b/arch/arm/mach-versatile/include/mach/memory.h
index b6315c0602ac..79aeab86b903 100644
--- a/arch/arm/mach-versatile/include/mach/memory.h
+++ b/arch/arm/mach-versatile/include/mach/memory.h
@@ -25,14 +25,4 @@
25 */ 25 */
26#define PHYS_OFFSET UL(0x00000000) 26#define PHYS_OFFSET UL(0x00000000)
27 27
28/*
29 * Virtual view <-> DMA view memory address translations
30 * virt_to_bus: Used to translate the virtual address to an
31 * address suitable to be passed to set_dma_addr
32 * bus_to_virt: Used to convert an address for DMA operations
33 * to an address that the kernel can use.
34 */
35#define __virt_to_bus(x) ((x) - PAGE_OFFSET)
36#define __bus_to_virt(x) ((x) + PAGE_OFFSET)
37
38#endif 28#endif
diff --git a/arch/arm/mach-versatile/include/mach/platform.h b/arch/arm/mach-versatile/include/mach/platform.h
index f91ba930ca8a..83207395191a 100644
--- a/arch/arm/mach-versatile/include/mach/platform.h
+++ b/arch/arm/mach-versatile/include/mach/platform.h
@@ -347,44 +347,6 @@
347#define INT_VICSOURCE30 30 /* PCI 3 */ 347#define INT_VICSOURCE30 30 /* PCI 3 */
348#define INT_VICSOURCE31 31 /* SIC source */ 348#define INT_VICSOURCE31 31 /* SIC source */
349 349
350/*
351 * Interrupt bit positions
352 *
353 */
354#define INTMASK_WDOGINT (1 << INT_WDOGINT)
355#define INTMASK_SOFTINT (1 << INT_SOFTINT)
356#define INTMASK_COMMRx (1 << INT_COMMRx)
357#define INTMASK_COMMTx (1 << INT_COMMTx)
358#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1)
359#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3)
360#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0)
361#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1)
362#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2)
363#define INTMASK_GPIOINT3 (1 << INT_GPIOINT3)
364#define INTMASK_RTCINT (1 << INT_RTCINT)
365#define INTMASK_SSPINT (1 << INT_SSPINT)
366#define INTMASK_UARTINT0 (1 << INT_UARTINT0)
367#define INTMASK_UARTINT1 (1 << INT_UARTINT1)
368#define INTMASK_UARTINT2 (1 << INT_UARTINT2)
369#define INTMASK_SCIINT (1 << INT_SCIINT)
370#define INTMASK_CLCDINT (1 << INT_CLCDINT)
371#define INTMASK_DMAINT (1 << INT_DMAINT)
372#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT)
373#define INTMASK_MBXINT (1 << INT_MBXINT)
374#define INTMASK_GNDINT (1 << INT_GNDINT)
375#define INTMASK_VICSOURCE21 (1 << INT_VICSOURCE21)
376#define INTMASK_VICSOURCE22 (1 << INT_VICSOURCE22)
377#define INTMASK_VICSOURCE23 (1 << INT_VICSOURCE23)
378#define INTMASK_VICSOURCE24 (1 << INT_VICSOURCE24)
379#define INTMASK_VICSOURCE25 (1 << INT_VICSOURCE25)
380#define INTMASK_VICSOURCE26 (1 << INT_VICSOURCE26)
381#define INTMASK_VICSOURCE27 (1 << INT_VICSOURCE27)
382#define INTMASK_VICSOURCE28 (1 << INT_VICSOURCE28)
383#define INTMASK_VICSOURCE29 (1 << INT_VICSOURCE29)
384#define INTMASK_VICSOURCE30 (1 << INT_VICSOURCE30)
385#define INTMASK_VICSOURCE31 (1 << INT_VICSOURCE31)
386
387
388#define VERSATILE_SC_VALID_INT 0x003FFFFF 350#define VERSATILE_SC_VALID_INT 0x003FFFFF
389 351
390#define MAXIRQNUM 31 352#define MAXIRQNUM 31
@@ -417,26 +379,6 @@
417#define SIC_INT_PCI3 30 379#define SIC_INT_PCI3 30
418 380
419 381
420#define SIC_INTMASK_MMCI0B (1 << SIC_INT_MMCI0B)
421#define SIC_INTMASK_MMCI1B (1 << SIC_INT_MMCI1B)
422#define SIC_INTMASK_KMI0 (1 << SIC_INT_KMI0)
423#define SIC_INTMASK_KMI1 (1 << SIC_INT_KMI1)
424#define SIC_INTMASK_SCI3 (1 << SIC_INT_SCI3)
425#define SIC_INTMASK_UART3 (1 << SIC_INT_UART3)
426#define SIC_INTMASK_CLCD (1 << SIC_INT_CLCD)
427#define SIC_INTMASK_TOUCH (1 << SIC_INT_TOUCH)
428#define SIC_INTMASK_KEYPAD (1 << SIC_INT_KEYPAD)
429#define SIC_INTMASK_DoC (1 << SIC_INT_DoC)
430#define SIC_INTMASK_MMCI0A (1 << SIC_INT_MMCI0A)
431#define SIC_INTMASK_MMCI1A (1 << SIC_INT_MMCI1A)
432#define SIC_INTMASK_AACI (1 << SIC_INT_AACI)
433#define SIC_INTMASK_ETH (1 << SIC_INT_ETH)
434#define SIC_INTMASK_USB (1 << SIC_INT_USB)
435#define SIC_INTMASK_PCI0 (1 << SIC_INT_PCI0)
436#define SIC_INTMASK_PCI1 (1 << SIC_INT_PCI1)
437#define SIC_INTMASK_PCI2 (1 << SIC_INT_PCI2)
438#define SIC_INTMASK_PCI3 (1 << SIC_INT_PCI3)
439
440/* 382/*
441 * Clean base - dummy 383 * Clean base - dummy
442 * 384 *
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index ab5f7a21350b..cf44de512830 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -10,8 +10,7 @@ config CPU_32
10 10
11# ARM610 11# ARM610
12config CPU_ARM610 12config CPU_ARM610
13 bool "Support ARM610 processor" 13 bool "Support ARM610 processor" if ARCH_RPC
14 depends on ARCH_RPC
15 select CPU_32v3 14 select CPU_32v3
16 select CPU_CACHE_V3 15 select CPU_CACHE_V3
17 select CPU_CACHE_VIVT 16 select CPU_CACHE_VIVT
@@ -43,8 +42,7 @@ config CPU_ARM7TDMI
43 42
44# ARM710 43# ARM710
45config CPU_ARM710 44config CPU_ARM710
46 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC 45 bool "Support ARM710 processor" if ARCH_RPC
47 default y if ARCH_CLPS7500
48 select CPU_32v3 46 select CPU_32v3
49 select CPU_CACHE_V3 47 select CPU_CACHE_V3
50 select CPU_CACHE_VIVT 48 select CPU_CACHE_VIVT
@@ -63,8 +61,7 @@ config CPU_ARM710
63 61
64# ARM720T 62# ARM720T
65config CPU_ARM720T 63config CPU_ARM720T
66 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR 64 bool "Support ARM720T processor" if ARCH_INTEGRATOR
67 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
68 select CPU_32v4T 65 select CPU_32v4T
69 select CPU_ABRT_LV4T 66 select CPU_ABRT_LV4T
70 select CPU_PABRT_NOIFAR 67 select CPU_PABRT_NOIFAR
@@ -114,9 +111,7 @@ config CPU_ARM9TDMI
114 111
115# ARM920T 112# ARM920T
116config CPU_ARM920T 113config CPU_ARM920T
117 bool "Support ARM920T processor" 114 bool "Support ARM920T processor" if ARCH_INTEGRATOR
118 depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
119 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
120 select CPU_32v4T 115 select CPU_32v4T
121 select CPU_ABRT_EV4T 116 select CPU_ABRT_EV4T
122 select CPU_PABRT_NOIFAR 117 select CPU_PABRT_NOIFAR
@@ -138,8 +133,6 @@ config CPU_ARM920T
138# ARM922T 133# ARM922T
139config CPU_ARM922T 134config CPU_ARM922T
140 bool "Support ARM922T processor" if ARCH_INTEGRATOR 135 bool "Support ARM922T processor" if ARCH_INTEGRATOR
141 depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695
142 default y if ARCH_LH7A40X || ARCH_KS8695
143 select CPU_32v4T 136 select CPU_32v4T
144 select CPU_ABRT_EV4T 137 select CPU_ABRT_EV4T
145 select CPU_PABRT_NOIFAR 138 select CPU_PABRT_NOIFAR
@@ -159,8 +152,6 @@ config CPU_ARM922T
159# ARM925T 152# ARM925T
160config CPU_ARM925T 153config CPU_ARM925T
161 bool "Support ARM925T processor" if ARCH_OMAP1 154 bool "Support ARM925T processor" if ARCH_OMAP1
162 depends on ARCH_OMAP15XX
163 default y if ARCH_OMAP15XX
164 select CPU_32v4T 155 select CPU_32v4T
165 select CPU_ABRT_EV4T 156 select CPU_ABRT_EV4T
166 select CPU_PABRT_NOIFAR 157 select CPU_PABRT_NOIFAR
@@ -179,22 +170,7 @@ config CPU_ARM925T
179 170
180# ARM926T 171# ARM926T
181config CPU_ARM926T 172config CPU_ARM926T
182 bool "Support ARM926T processor" 173 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
183 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || \
184 MACH_VERSATILE_AB || ARCH_OMAP730 || \
185 ARCH_OMAP16XX || MACH_REALVIEW_EB || \
186 ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
187 ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
188 ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
189 ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
190 ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2
191 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || \
192 ARCH_OMAP730 || ARCH_OMAP16XX || \
193 ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
194 ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
195 ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
196 ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
197 ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2
198 select CPU_32v5 174 select CPU_32v5
199 select CPU_ABRT_EV5TJ 175 select CPU_ABRT_EV5TJ
200 select CPU_PABRT_NOIFAR 176 select CPU_PABRT_NOIFAR
@@ -247,8 +223,7 @@ config CPU_ARM946E
247 223
248# ARM1020 - needs validating 224# ARM1020 - needs validating
249config CPU_ARM1020 225config CPU_ARM1020
250 bool "Support ARM1020T (rev 0) processor" 226 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
251 depends on ARCH_INTEGRATOR
252 select CPU_32v5 227 select CPU_32v5
253 select CPU_ABRT_EV4T 228 select CPU_ABRT_EV4T
254 select CPU_PABRT_NOIFAR 229 select CPU_PABRT_NOIFAR
@@ -266,8 +241,7 @@ config CPU_ARM1020
266 241
267# ARM1020E - needs validating 242# ARM1020E - needs validating
268config CPU_ARM1020E 243config CPU_ARM1020E
269 bool "Support ARM1020E processor" 244 bool "Support ARM1020E processor" if ARCH_INTEGRATOR
270 depends on ARCH_INTEGRATOR
271 select CPU_32v5 245 select CPU_32v5
272 select CPU_ABRT_EV4T 246 select CPU_ABRT_EV4T
273 select CPU_PABRT_NOIFAR 247 select CPU_PABRT_NOIFAR
@@ -280,8 +254,7 @@ config CPU_ARM1020E
280 254
281# ARM1022E 255# ARM1022E
282config CPU_ARM1022 256config CPU_ARM1022
283 bool "Support ARM1022E processor" 257 bool "Support ARM1022E processor" if ARCH_INTEGRATOR
284 depends on ARCH_INTEGRATOR
285 select CPU_32v5 258 select CPU_32v5
286 select CPU_ABRT_EV4T 259 select CPU_ABRT_EV4T
287 select CPU_PABRT_NOIFAR 260 select CPU_PABRT_NOIFAR
@@ -299,8 +272,7 @@ config CPU_ARM1022
299 272
300# ARM1026EJ-S 273# ARM1026EJ-S
301config CPU_ARM1026 274config CPU_ARM1026
302 bool "Support ARM1026EJ-S processor" 275 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
303 depends on ARCH_INTEGRATOR
304 select CPU_32v5 276 select CPU_32v5
305 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 277 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
306 select CPU_PABRT_NOIFAR 278 select CPU_PABRT_NOIFAR
@@ -317,8 +289,7 @@ config CPU_ARM1026
317 289
318# SA110 290# SA110
319config CPU_SA110 291config CPU_SA110
320 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC 292 bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
321 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
322 select CPU_32v3 if ARCH_RPC 293 select CPU_32v3 if ARCH_RPC
323 select CPU_32v4 if !ARCH_RPC 294 select CPU_32v4 if !ARCH_RPC
324 select CPU_ABRT_EV4 295 select CPU_ABRT_EV4
@@ -340,8 +311,6 @@ config CPU_SA110
340# SA1100 311# SA1100
341config CPU_SA1100 312config CPU_SA1100
342 bool 313 bool
343 depends on ARCH_SA1100
344 default y
345 select CPU_32v4 314 select CPU_32v4
346 select CPU_ABRT_EV4 315 select CPU_ABRT_EV4
347 select CPU_PABRT_NOIFAR 316 select CPU_PABRT_NOIFAR
@@ -353,8 +322,6 @@ config CPU_SA1100
353# XScale 322# XScale
354config CPU_XSCALE 323config CPU_XSCALE
355 bool 324 bool
356 depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000
357 default y
358 select CPU_32v5 325 select CPU_32v5
359 select CPU_ABRT_EV5T 326 select CPU_ABRT_EV5T
360 select CPU_PABRT_NOIFAR 327 select CPU_PABRT_NOIFAR
@@ -365,8 +332,6 @@ config CPU_XSCALE
365# XScale Core Version 3 332# XScale Core Version 3
366config CPU_XSC3 333config CPU_XSC3
367 bool 334 bool
368 depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx
369 default y
370 select CPU_32v5 335 select CPU_32v5
371 select CPU_ABRT_EV5T 336 select CPU_ABRT_EV5T
372 select CPU_PABRT_NOIFAR 337 select CPU_PABRT_NOIFAR
@@ -378,8 +343,6 @@ config CPU_XSC3
378# Feroceon 343# Feroceon
379config CPU_FEROCEON 344config CPU_FEROCEON
380 bool 345 bool
381 depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD || ARCH_MV78XX0
382 default y
383 select CPU_32v5 346 select CPU_32v5
384 select CPU_ABRT_EV5T 347 select CPU_ABRT_EV5T
385 select CPU_PABRT_NOIFAR 348 select CPU_PABRT_NOIFAR
@@ -399,10 +362,7 @@ config CPU_FEROCEON_OLD_ID
399 362
400# ARMv6 363# ARMv6
401config CPU_V6 364config CPU_V6
402 bool "Support ARM V6 processor" 365 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
403 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
404 default y if ARCH_MX3
405 default y if ARCH_MSM
406 select CPU_32v6 366 select CPU_32v6
407 select CPU_ABRT_EV6 367 select CPU_ABRT_EV6
408 select CPU_PABRT_NOIFAR 368 select CPU_PABRT_NOIFAR
@@ -427,8 +387,7 @@ config CPU_32v6K
427 387
428# ARMv7 388# ARMv7
429config CPU_V7 389config CPU_V7
430 bool "Support ARM V7 processor" 390 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
431 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP3
432 select CPU_32v6K 391 select CPU_32v6K
433 select CPU_32v7 392 select CPU_32v7
434 select CPU_ABRT_EV7 393 select CPU_ABRT_EV7
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 133e65d166b3..c5a57fbf095d 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -17,6 +17,7 @@
17#include <linux/string.h> 17#include <linux/string.h>
18#include <linux/proc_fs.h> 18#include <linux/proc_fs.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/sched.h>
20#include <linux/uaccess.h> 21#include <linux/uaccess.h>
21 22
22#include <asm/unaligned.h> 23#include <asm/unaligned.h>
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index 3b3639eb7ca5..8a4abebc478a 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -9,7 +9,6 @@
9 */ 9 */
10#include <linux/linkage.h> 10#include <linux/linkage.h>
11#include <linux/init.h> 11#include <linux/init.h>
12#include <mach/hardware.h>
13#include <asm/page.h> 12#include <asm/page.h>
14#include "proc-macros.S" 13#include "proc-macros.S"
15 14
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index 5786adf10040..3668611cb400 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -9,7 +9,6 @@
9 */ 9 */
10#include <linux/linkage.h> 10#include <linux/linkage.h>
11#include <linux/init.h> 11#include <linux/init.h>
12#include <mach/hardware.h>
13#include <asm/page.h> 12#include <asm/page.h>
14#include "proc-macros.S" 13#include "proc-macros.S"
15 14
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index 51a9b0b273b6..c54fa2cc40e6 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -13,7 +13,6 @@
13 */ 13 */
14#include <linux/linkage.h> 14#include <linux/linkage.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <mach/hardware.h>
17#include <asm/page.h> 16#include <asm/page.h>
18#include "proc-macros.S" 17#include "proc-macros.S"
19 18
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index d19c2bec2b1f..be93ff02a98d 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -26,6 +26,7 @@
26 * - mm - mm_struct describing address space 26 * - mm - mm_struct describing address space
27 */ 27 */
28ENTRY(v7_flush_dcache_all) 28ENTRY(v7_flush_dcache_all)
29 dmb @ ensure ordering with previous memory accesses
29 mrc p15, 1, r0, c0, c0, 1 @ read clidr 30 mrc p15, 1, r0, c0, c0, 1 @ read clidr
30 ands r3, r0, #0x7000000 @ extract loc from clidr 31 ands r3, r0, #0x7000000 @ extract loc from clidr
31 mov r3, r3, lsr #23 @ left align loc bit field 32 mov r3, r3, lsr #23 @ left align loc bit field
@@ -64,6 +65,7 @@ skip:
64finished: 65finished:
65 mov r10, #0 @ swith back to cache level 0 66 mov r10, #0 @ swith back to cache level 0
66 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 67 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
68 dsb
67 isb 69 isb
68 mov pc, lr 70 mov pc, lr
69ENDPROC(v7_flush_dcache_all) 71ENDPROC(v7_flush_dcache_all)
diff --git a/arch/arm/mm/copypage-feroceon.S b/arch/arm/mm/copypage-feroceon.S
deleted file mode 100644
index 7eb0d320d240..000000000000
--- a/arch/arm/mm/copypage-feroceon.S
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * linux/arch/arm/lib/copypage-feroceon.S
3 *
4 * Copyright (C) 2008 Marvell Semiconductors
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This handles copy_user_page and clear_user_page on Feroceon
11 * more optimally than the generic implementations.
12 */
13#include <linux/linkage.h>
14#include <linux/init.h>
15#include <asm/asm-offsets.h>
16
17 .text
18 .align 5
19
20ENTRY(feroceon_copy_user_page)
21 stmfd sp!, {r4-r9, lr}
22 mov ip, #PAGE_SZ
231: mov lr, r1
24 ldmia r1!, {r2 - r9}
25 pld [lr, #32]
26 pld [lr, #64]
27 pld [lr, #96]
28 pld [lr, #128]
29 pld [lr, #160]
30 pld [lr, #192]
31 pld [lr, #224]
32 stmia r0, {r2 - r9}
33 ldmia r1!, {r2 - r9}
34 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line
35 add r0, r0, #32
36 stmia r0, {r2 - r9}
37 ldmia r1!, {r2 - r9}
38 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line
39 add r0, r0, #32
40 stmia r0, {r2 - r9}
41 ldmia r1!, {r2 - r9}
42 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line
43 add r0, r0, #32
44 stmia r0, {r2 - r9}
45 ldmia r1!, {r2 - r9}
46 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line
47 add r0, r0, #32
48 stmia r0, {r2 - r9}
49 ldmia r1!, {r2 - r9}
50 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line
51 add r0, r0, #32
52 stmia r0, {r2 - r9}
53 ldmia r1!, {r2 - r9}
54 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line
55 add r0, r0, #32
56 stmia r0, {r2 - r9}
57 ldmia r1!, {r2 - r9}
58 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line
59 add r0, r0, #32
60 stmia r0, {r2 - r9}
61 subs ip, ip, #(32 * 8)
62 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line
63 add r0, r0, #32
64 bne 1b
65 mcr p15, 0, ip, c7, c10, 4 @ drain WB
66 ldmfd sp!, {r4-r9, pc}
67
68 .align 5
69
70ENTRY(feroceon_clear_user_page)
71 stmfd sp!, {r4-r7, lr}
72 mov r1, #PAGE_SZ/32
73 mov r2, #0
74 mov r3, #0
75 mov r4, #0
76 mov r5, #0
77 mov r6, #0
78 mov r7, #0
79 mov ip, #0
80 mov lr, #0
811: stmia r0, {r2-r7, ip, lr}
82 subs r1, r1, #1
83 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line
84 add r0, r0, #32
85 bne 1b
86 mcr p15, 0, r1, c7, c10, 4 @ drain WB
87 ldmfd sp!, {r4-r7, pc}
88
89 __INITDATA
90
91 .type feroceon_user_fns, #object
92ENTRY(feroceon_user_fns)
93 .long feroceon_clear_user_page
94 .long feroceon_copy_user_page
95 .size feroceon_user_fns, . - feroceon_user_fns
diff --git a/arch/arm/mm/copypage-feroceon.c b/arch/arm/mm/copypage-feroceon.c
new file mode 100644
index 000000000000..c3ba6a94da0c
--- /dev/null
+++ b/arch/arm/mm/copypage-feroceon.c
@@ -0,0 +1,111 @@
1/*
2 * linux/arch/arm/mm/copypage-feroceon.S
3 *
4 * Copyright (C) 2008 Marvell Semiconductors
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This handles copy_user_highpage and clear_user_page on Feroceon
11 * more optimally than the generic implementations.
12 */
13#include <linux/init.h>
14#include <linux/highmem.h>
15
16static void __attribute__((naked))
17feroceon_copy_user_page(void *kto, const void *kfrom)
18{
19 asm("\
20 stmfd sp!, {r4-r9, lr} \n\
21 mov ip, %0 \n\
221: mov lr, r1 \n\
23 ldmia r1!, {r2 - r9} \n\
24 pld [lr, #32] \n\
25 pld [lr, #64] \n\
26 pld [lr, #96] \n\
27 pld [lr, #128] \n\
28 pld [lr, #160] \n\
29 pld [lr, #192] \n\
30 pld [lr, #224] \n\
31 stmia r0, {r2 - r9} \n\
32 ldmia r1!, {r2 - r9} \n\
33 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\
34 add r0, r0, #32 \n\
35 stmia r0, {r2 - r9} \n\
36 ldmia r1!, {r2 - r9} \n\
37 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\
38 add r0, r0, #32 \n\
39 stmia r0, {r2 - r9} \n\
40 ldmia r1!, {r2 - r9} \n\
41 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\
42 add r0, r0, #32 \n\
43 stmia r0, {r2 - r9} \n\
44 ldmia r1!, {r2 - r9} \n\
45 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\
46 add r0, r0, #32 \n\
47 stmia r0, {r2 - r9} \n\
48 ldmia r1!, {r2 - r9} \n\
49 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\
50 add r0, r0, #32 \n\
51 stmia r0, {r2 - r9} \n\
52 ldmia r1!, {r2 - r9} \n\
53 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\
54 add r0, r0, #32 \n\
55 stmia r0, {r2 - r9} \n\
56 ldmia r1!, {r2 - r9} \n\
57 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\
58 add r0, r0, #32 \n\
59 stmia r0, {r2 - r9} \n\
60 subs ip, ip, #(32 * 8) \n\
61 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\
62 add r0, r0, #32 \n\
63 bne 1b \n\
64 mcr p15, 0, ip, c7, c10, 4 @ drain WB\n\
65 ldmfd sp!, {r4-r9, pc}"
66 :
67 : "I" (PAGE_SIZE));
68}
69
70void feroceon_copy_user_highpage(struct page *to, struct page *from,
71 unsigned long vaddr)
72{
73 void *kto, *kfrom;
74
75 kto = kmap_atomic(to, KM_USER0);
76 kfrom = kmap_atomic(from, KM_USER1);
77 feroceon_copy_user_page(kto, kfrom);
78 kunmap_atomic(kfrom, KM_USER1);
79 kunmap_atomic(kto, KM_USER0);
80}
81
82void feroceon_clear_user_highpage(struct page *page, unsigned long vaddr)
83{
84 void *ptr, *kaddr = kmap_atomic(page, KM_USER0);
85 asm volatile ("\
86 mov r1, %2 \n\
87 mov r2, #0 \n\
88 mov r3, #0 \n\
89 mov r4, #0 \n\
90 mov r5, #0 \n\
91 mov r6, #0 \n\
92 mov r7, #0 \n\
93 mov ip, #0 \n\
94 mov lr, #0 \n\
951: stmia %0, {r2-r7, ip, lr} \n\
96 subs r1, r1, #1 \n\
97 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\
98 add %0, %0, #32 \n\
99 bne 1b \n\
100 mcr p15, 0, r1, c7, c10, 4 @ drain WB"
101 : "=r" (ptr)
102 : "0" (kaddr), "I" (PAGE_SIZE / 32)
103 : "r1", "r2", "r3", "r4", "r5", "r6", "r7", "ip", "lr");
104 kunmap_atomic(kaddr, KM_USER0);
105}
106
107struct cpu_user_fns feroceon_user_fns __initdata = {
108 .cpu_clear_user_highpage = feroceon_clear_user_highpage,
109 .cpu_copy_user_highpage = feroceon_copy_user_highpage,
110};
111
diff --git a/arch/arm/mm/copypage-v3.S b/arch/arm/mm/copypage-v3.S
deleted file mode 100644
index 2ee394b11bcb..000000000000
--- a/arch/arm/mm/copypage-v3.S
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * linux/arch/arm/lib/copypage.S
3 *
4 * Copyright (C) 1995-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * ASM optimised string functions
11 */
12#include <linux/linkage.h>
13#include <linux/init.h>
14#include <asm/assembler.h>
15#include <asm/asm-offsets.h>
16
17 .text
18 .align 5
19/*
20 * ARMv3 optimised copy_user_page
21 *
22 * FIXME: do we need to handle cache stuff...
23 */
24ENTRY(v3_copy_user_page)
25 stmfd sp!, {r4, lr} @ 2
26 mov r2, #PAGE_SZ/64 @ 1
27 ldmia r1!, {r3, r4, ip, lr} @ 4+1
281: stmia r0!, {r3, r4, ip, lr} @ 4
29 ldmia r1!, {r3, r4, ip, lr} @ 4+1
30 stmia r0!, {r3, r4, ip, lr} @ 4
31 ldmia r1!, {r3, r4, ip, lr} @ 4+1
32 stmia r0!, {r3, r4, ip, lr} @ 4
33 ldmia r1!, {r3, r4, ip, lr} @ 4
34 subs r2, r2, #1 @ 1
35 stmia r0!, {r3, r4, ip, lr} @ 4
36 ldmneia r1!, {r3, r4, ip, lr} @ 4
37 bne 1b @ 1
38 ldmfd sp!, {r4, pc} @ 3
39
40 .align 5
41/*
42 * ARMv3 optimised clear_user_page
43 *
44 * FIXME: do we need to handle cache stuff...
45 */
46ENTRY(v3_clear_user_page)
47 str lr, [sp, #-4]!
48 mov r1, #PAGE_SZ/64 @ 1
49 mov r2, #0 @ 1
50 mov r3, #0 @ 1
51 mov ip, #0 @ 1
52 mov lr, #0 @ 1
531: stmia r0!, {r2, r3, ip, lr} @ 4
54 stmia r0!, {r2, r3, ip, lr} @ 4
55 stmia r0!, {r2, r3, ip, lr} @ 4
56 stmia r0!, {r2, r3, ip, lr} @ 4
57 subs r1, r1, #1 @ 1
58 bne 1b @ 1
59 ldr pc, [sp], #4
60
61 __INITDATA
62
63 .type v3_user_fns, #object
64ENTRY(v3_user_fns)
65 .long v3_clear_user_page
66 .long v3_copy_user_page
67 .size v3_user_fns, . - v3_user_fns
diff --git a/arch/arm/mm/copypage-v3.c b/arch/arm/mm/copypage-v3.c
new file mode 100644
index 000000000000..70ed96c8af8e
--- /dev/null
+++ b/arch/arm/mm/copypage-v3.c
@@ -0,0 +1,81 @@
1/*
2 * linux/arch/arm/mm/copypage-v3.c
3 *
4 * Copyright (C) 1995-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/init.h>
11#include <linux/highmem.h>
12
13/*
14 * ARMv3 optimised copy_user_highpage
15 *
16 * FIXME: do we need to handle cache stuff...
17 */
18static void __attribute__((naked))
19v3_copy_user_page(void *kto, const void *kfrom)
20{
21 asm("\n\
22 stmfd sp!, {r4, lr} @ 2\n\
23 mov r2, %2 @ 1\n\
24 ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\
251: stmia %1!, {r3, r4, ip, lr} @ 4\n\
26 ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\
27 stmia %1!, {r3, r4, ip, lr} @ 4\n\
28 ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\
29 stmia %1!, {r3, r4, ip, lr} @ 4\n\
30 ldmia %0!, {r3, r4, ip, lr} @ 4\n\
31 subs r2, r2, #1 @ 1\n\
32 stmia %1!, {r3, r4, ip, lr} @ 4\n\
33 ldmneia %0!, {r3, r4, ip, lr} @ 4\n\
34 bne 1b @ 1\n\
35 ldmfd sp!, {r4, pc} @ 3"
36 :
37 : "r" (kfrom), "r" (kto), "I" (PAGE_SIZE / 64));
38}
39
40void v3_copy_user_highpage(struct page *to, struct page *from,
41 unsigned long vaddr)
42{
43 void *kto, *kfrom;
44
45 kto = kmap_atomic(to, KM_USER0);
46 kfrom = kmap_atomic(from, KM_USER1);
47 v3_copy_user_page(kto, kfrom);
48 kunmap_atomic(kfrom, KM_USER1);
49 kunmap_atomic(kto, KM_USER0);
50}
51
52/*
53 * ARMv3 optimised clear_user_page
54 *
55 * FIXME: do we need to handle cache stuff...
56 */
57void v3_clear_user_highpage(struct page *page, unsigned long vaddr)
58{
59 void *ptr, *kaddr = kmap_atomic(page, KM_USER0);
60 asm volatile("\n\
61 mov r1, %2 @ 1\n\
62 mov r2, #0 @ 1\n\
63 mov r3, #0 @ 1\n\
64 mov ip, #0 @ 1\n\
65 mov lr, #0 @ 1\n\
661: stmia %0!, {r2, r3, ip, lr} @ 4\n\
67 stmia %0!, {r2, r3, ip, lr} @ 4\n\
68 stmia %0!, {r2, r3, ip, lr} @ 4\n\
69 stmia %0!, {r2, r3, ip, lr} @ 4\n\
70 subs r1, r1, #1 @ 1\n\
71 bne 1b @ 1"
72 : "=r" (ptr)
73 : "0" (kaddr), "I" (PAGE_SIZE / 64)
74 : "r1", "r2", "r3", "ip", "lr");
75 kunmap_atomic(kaddr, KM_USER0);
76}
77
78struct cpu_user_fns v3_user_fns __initdata = {
79 .cpu_clear_user_highpage = v3_clear_user_highpage,
80 .cpu_copy_user_highpage = v3_copy_user_highpage,
81};
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index 8d33e2549344..bdb5fd983b15 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -15,8 +15,8 @@
15 */ 15 */
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/mm.h> 17#include <linux/mm.h>
18#include <linux/highmem.h>
18 19
19#include <asm/page.h>
20#include <asm/pgtable.h> 20#include <asm/pgtable.h>
21#include <asm/tlbflush.h> 21#include <asm/tlbflush.h>
22#include <asm/cacheflush.h> 22#include <asm/cacheflush.h>
@@ -33,7 +33,7 @@
33static DEFINE_SPINLOCK(minicache_lock); 33static DEFINE_SPINLOCK(minicache_lock);
34 34
35/* 35/*
36 * ARMv4 mini-dcache optimised copy_user_page 36 * ARMv4 mini-dcache optimised copy_user_highpage
37 * 37 *
38 * We flush the destination cache lines just before we write the data into the 38 * We flush the destination cache lines just before we write the data into the
39 * corresponding address. Since the Dcache is read-allocate, this removes the 39 * corresponding address. Since the Dcache is read-allocate, this removes the
@@ -42,7 +42,7 @@ static DEFINE_SPINLOCK(minicache_lock);
42 * 42 *
43 * Note: We rely on all ARMv4 processors implementing the "invalidate D line" 43 * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
44 * instruction. If your processor does not supply this, you have to write your 44 * instruction. If your processor does not supply this, you have to write your
45 * own copy_user_page that does the right thing. 45 * own copy_user_highpage that does the right thing.
46 */ 46 */
47static void __attribute__((naked)) 47static void __attribute__((naked))
48mc_copy_user_page(void *from, void *to) 48mc_copy_user_page(void *from, void *to)
@@ -68,50 +68,53 @@ mc_copy_user_page(void *from, void *to)
68 : "r" (from), "r" (to), "I" (PAGE_SIZE / 64)); 68 : "r" (from), "r" (to), "I" (PAGE_SIZE / 64));
69} 69}
70 70
71void v4_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr) 71void v4_mc_copy_user_highpage(struct page *from, struct page *to,
72 unsigned long vaddr)
72{ 73{
73 struct page *page = virt_to_page(kfrom); 74 void *kto = kmap_atomic(to, KM_USER1);
74 75
75 if (test_and_clear_bit(PG_dcache_dirty, &page->flags)) 76 if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
76 __flush_dcache_page(page_mapping(page), page); 77 __flush_dcache_page(page_mapping(from), from);
77 78
78 spin_lock(&minicache_lock); 79 spin_lock(&minicache_lock);
79 80
80 set_pte_ext(TOP_PTE(0xffff8000), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot), 0); 81 set_pte_ext(TOP_PTE(0xffff8000), pfn_pte(page_to_pfn(from), minicache_pgprot), 0);
81 flush_tlb_kernel_page(0xffff8000); 82 flush_tlb_kernel_page(0xffff8000);
82 83
83 mc_copy_user_page((void *)0xffff8000, kto); 84 mc_copy_user_page((void *)0xffff8000, kto);
84 85
85 spin_unlock(&minicache_lock); 86 spin_unlock(&minicache_lock);
87
88 kunmap_atomic(kto, KM_USER1);
86} 89}
87 90
88/* 91/*
89 * ARMv4 optimised clear_user_page 92 * ARMv4 optimised clear_user_page
90 */ 93 */
91void __attribute__((naked)) 94void v4_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
92v4_mc_clear_user_page(void *kaddr, unsigned long vaddr)
93{ 95{
94 asm volatile( 96 void *ptr, *kaddr = kmap_atomic(page, KM_USER0);
95 "str lr, [sp, #-4]!\n\ 97 asm volatile("\
96 mov r1, %0 @ 1\n\ 98 mov r1, %2 @ 1\n\
97 mov r2, #0 @ 1\n\ 99 mov r2, #0 @ 1\n\
98 mov r3, #0 @ 1\n\ 100 mov r3, #0 @ 1\n\
99 mov ip, #0 @ 1\n\ 101 mov ip, #0 @ 1\n\
100 mov lr, #0 @ 1\n\ 102 mov lr, #0 @ 1\n\
1011: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ 1031: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
102 stmia r0!, {r2, r3, ip, lr} @ 4\n\ 104 stmia %0!, {r2, r3, ip, lr} @ 4\n\
103 stmia r0!, {r2, r3, ip, lr} @ 4\n\ 105 stmia %0!, {r2, r3, ip, lr} @ 4\n\
104 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ 106 mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
105 stmia r0!, {r2, r3, ip, lr} @ 4\n\ 107 stmia %0!, {r2, r3, ip, lr} @ 4\n\
106 stmia r0!, {r2, r3, ip, lr} @ 4\n\ 108 stmia %0!, {r2, r3, ip, lr} @ 4\n\
107 subs r1, r1, #1 @ 1\n\ 109 subs r1, r1, #1 @ 1\n\
108 bne 1b @ 1\n\ 110 bne 1b @ 1"
109 ldr pc, [sp], #4" 111 : "=r" (ptr)
110 : 112 : "0" (kaddr), "I" (PAGE_SIZE / 64)
111 : "I" (PAGE_SIZE / 64)); 113 : "r1", "r2", "r3", "ip", "lr");
114 kunmap_atomic(kaddr, KM_USER0);
112} 115}
113 116
114struct cpu_user_fns v4_mc_user_fns __initdata = { 117struct cpu_user_fns v4_mc_user_fns __initdata = {
115 .cpu_clear_user_page = v4_mc_clear_user_page, 118 .cpu_clear_user_highpage = v4_mc_clear_user_highpage,
116 .cpu_copy_user_page = v4_mc_copy_user_page, 119 .cpu_copy_user_highpage = v4_mc_copy_user_highpage,
117}; 120};
diff --git a/arch/arm/mm/copypage-v4wb.S b/arch/arm/mm/copypage-v4wb.S
deleted file mode 100644
index 83117354b1cd..000000000000
--- a/arch/arm/mm/copypage-v4wb.S
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * linux/arch/arm/lib/copypage.S
3 *
4 * Copyright (C) 1995-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * ASM optimised string functions
11 */
12#include <linux/linkage.h>
13#include <linux/init.h>
14#include <asm/asm-offsets.h>
15
16 .text
17 .align 5
18/*
19 * ARMv4 optimised copy_user_page
20 *
21 * We flush the destination cache lines just before we write the data into the
22 * corresponding address. Since the Dcache is read-allocate, this removes the
23 * Dcache aliasing issue. The writes will be forwarded to the write buffer,
24 * and merged as appropriate.
25 *
26 * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
27 * instruction. If your processor does not supply this, you have to write your
28 * own copy_user_page that does the right thing.
29 */
30ENTRY(v4wb_copy_user_page)
31 stmfd sp!, {r4, lr} @ 2
32 mov r2, #PAGE_SZ/64 @ 1
33 ldmia r1!, {r3, r4, ip, lr} @ 4
341: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
35 stmia r0!, {r3, r4, ip, lr} @ 4
36 ldmia r1!, {r3, r4, ip, lr} @ 4+1
37 stmia r0!, {r3, r4, ip, lr} @ 4
38 ldmia r1!, {r3, r4, ip, lr} @ 4
39 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
40 stmia r0!, {r3, r4, ip, lr} @ 4
41 ldmia r1!, {r3, r4, ip, lr} @ 4
42 subs r2, r2, #1 @ 1
43 stmia r0!, {r3, r4, ip, lr} @ 4
44 ldmneia r1!, {r3, r4, ip, lr} @ 4
45 bne 1b @ 1
46 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB
47 ldmfd sp!, {r4, pc} @ 3
48
49 .align 5
50/*
51 * ARMv4 optimised clear_user_page
52 *
53 * Same story as above.
54 */
55ENTRY(v4wb_clear_user_page)
56 str lr, [sp, #-4]!
57 mov r1, #PAGE_SZ/64 @ 1
58 mov r2, #0 @ 1
59 mov r3, #0 @ 1
60 mov ip, #0 @ 1
61 mov lr, #0 @ 1
621: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
63 stmia r0!, {r2, r3, ip, lr} @ 4
64 stmia r0!, {r2, r3, ip, lr} @ 4
65 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
66 stmia r0!, {r2, r3, ip, lr} @ 4
67 stmia r0!, {r2, r3, ip, lr} @ 4
68 subs r1, r1, #1 @ 1
69 bne 1b @ 1
70 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB
71 ldr pc, [sp], #4
72
73 __INITDATA
74
75 .type v4wb_user_fns, #object
76ENTRY(v4wb_user_fns)
77 .long v4wb_clear_user_page
78 .long v4wb_copy_user_page
79 .size v4wb_user_fns, . - v4wb_user_fns
diff --git a/arch/arm/mm/copypage-v4wb.c b/arch/arm/mm/copypage-v4wb.c
new file mode 100644
index 000000000000..3ec93dab7656
--- /dev/null
+++ b/arch/arm/mm/copypage-v4wb.c
@@ -0,0 +1,94 @@
1/*
2 * linux/arch/arm/mm/copypage-v4wb.c
3 *
4 * Copyright (C) 1995-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/init.h>
11#include <linux/highmem.h>
12
13/*
14 * ARMv4 optimised copy_user_highpage
15 *
16 * We flush the destination cache lines just before we write the data into the
17 * corresponding address. Since the Dcache is read-allocate, this removes the
18 * Dcache aliasing issue. The writes will be forwarded to the write buffer,
19 * and merged as appropriate.
20 *
21 * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
22 * instruction. If your processor does not supply this, you have to write your
23 * own copy_user_highpage that does the right thing.
24 */
25static void __attribute__((naked))
26v4wb_copy_user_page(void *kto, const void *kfrom)
27{
28 asm("\
29 stmfd sp!, {r4, lr} @ 2\n\
30 mov r2, %0 @ 1\n\
31 ldmia r1!, {r3, r4, ip, lr} @ 4\n\
321: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
33 stmia r0!, {r3, r4, ip, lr} @ 4\n\
34 ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\
35 stmia r0!, {r3, r4, ip, lr} @ 4\n\
36 ldmia r1!, {r3, r4, ip, lr} @ 4\n\
37 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
38 stmia r0!, {r3, r4, ip, lr} @ 4\n\
39 ldmia r1!, {r3, r4, ip, lr} @ 4\n\
40 subs r2, r2, #1 @ 1\n\
41 stmia r0!, {r3, r4, ip, lr} @ 4\n\
42 ldmneia r1!, {r3, r4, ip, lr} @ 4\n\
43 bne 1b @ 1\n\
44 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB\n\
45 ldmfd sp!, {r4, pc} @ 3"
46 :
47 : "I" (PAGE_SIZE / 64));
48}
49
50void v4wb_copy_user_highpage(struct page *to, struct page *from,
51 unsigned long vaddr)
52{
53 void *kto, *kfrom;
54
55 kto = kmap_atomic(to, KM_USER0);
56 kfrom = kmap_atomic(from, KM_USER1);
57 v4wb_copy_user_page(kto, kfrom);
58 kunmap_atomic(kfrom, KM_USER1);
59 kunmap_atomic(kto, KM_USER0);
60}
61
62/*
63 * ARMv4 optimised clear_user_page
64 *
65 * Same story as above.
66 */
67void v4wb_clear_user_highpage(struct page *page, unsigned long vaddr)
68{
69 void *ptr, *kaddr = kmap_atomic(page, KM_USER0);
70 asm volatile("\
71 mov r1, %2 @ 1\n\
72 mov r2, #0 @ 1\n\
73 mov r3, #0 @ 1\n\
74 mov ip, #0 @ 1\n\
75 mov lr, #0 @ 1\n\
761: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
77 stmia %0!, {r2, r3, ip, lr} @ 4\n\
78 stmia %0!, {r2, r3, ip, lr} @ 4\n\
79 mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
80 stmia %0!, {r2, r3, ip, lr} @ 4\n\
81 stmia %0!, {r2, r3, ip, lr} @ 4\n\
82 subs r1, r1, #1 @ 1\n\
83 bne 1b @ 1\n\
84 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB"
85 : "=r" (ptr)
86 : "0" (kaddr), "I" (PAGE_SIZE / 64)
87 : "r1", "r2", "r3", "ip", "lr");
88 kunmap_atomic(kaddr, KM_USER0);
89}
90
91struct cpu_user_fns v4wb_user_fns __initdata = {
92 .cpu_clear_user_highpage = v4wb_clear_user_highpage,
93 .cpu_copy_user_highpage = v4wb_copy_user_highpage,
94};
diff --git a/arch/arm/mm/copypage-v4wt.S b/arch/arm/mm/copypage-v4wt.S
deleted file mode 100644
index e1f2af28d549..000000000000
--- a/arch/arm/mm/copypage-v4wt.S
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * linux/arch/arm/lib/copypage-v4.S
3 *
4 * Copyright (C) 1995-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * ASM optimised string functions
11 *
12 * This is for CPUs with a writethrough cache and 'flush ID cache' is
13 * the only supported cache operation.
14 */
15#include <linux/linkage.h>
16#include <linux/init.h>
17#include <asm/asm-offsets.h>
18
19 .text
20 .align 5
21/*
22 * ARMv4 optimised copy_user_page
23 *
24 * Since we have writethrough caches, we don't have to worry about
25 * dirty data in the cache. However, we do have to ensure that
26 * subsequent reads are up to date.
27 */
28ENTRY(v4wt_copy_user_page)
29 stmfd sp!, {r4, lr} @ 2
30 mov r2, #PAGE_SZ/64 @ 1
31 ldmia r1!, {r3, r4, ip, lr} @ 4
321: stmia r0!, {r3, r4, ip, lr} @ 4
33 ldmia r1!, {r3, r4, ip, lr} @ 4+1
34 stmia r0!, {r3, r4, ip, lr} @ 4
35 ldmia r1!, {r3, r4, ip, lr} @ 4
36 stmia r0!, {r3, r4, ip, lr} @ 4
37 ldmia r1!, {r3, r4, ip, lr} @ 4
38 subs r2, r2, #1 @ 1
39 stmia r0!, {r3, r4, ip, lr} @ 4
40 ldmneia r1!, {r3, r4, ip, lr} @ 4
41 bne 1b @ 1
42 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache
43 ldmfd sp!, {r4, pc} @ 3
44
45 .align 5
46/*
47 * ARMv4 optimised clear_user_page
48 *
49 * Same story as above.
50 */
51ENTRY(v4wt_clear_user_page)
52 str lr, [sp, #-4]!
53 mov r1, #PAGE_SZ/64 @ 1
54 mov r2, #0 @ 1
55 mov r3, #0 @ 1
56 mov ip, #0 @ 1
57 mov lr, #0 @ 1
581: stmia r0!, {r2, r3, ip, lr} @ 4
59 stmia r0!, {r2, r3, ip, lr} @ 4
60 stmia r0!, {r2, r3, ip, lr} @ 4
61 stmia r0!, {r2, r3, ip, lr} @ 4
62 subs r1, r1, #1 @ 1
63 bne 1b @ 1
64 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache
65 ldr pc, [sp], #4
66
67 __INITDATA
68
69 .type v4wt_user_fns, #object
70ENTRY(v4wt_user_fns)
71 .long v4wt_clear_user_page
72 .long v4wt_copy_user_page
73 .size v4wt_user_fns, . - v4wt_user_fns
diff --git a/arch/arm/mm/copypage-v4wt.c b/arch/arm/mm/copypage-v4wt.c
new file mode 100644
index 000000000000..0f1188efae45
--- /dev/null
+++ b/arch/arm/mm/copypage-v4wt.c
@@ -0,0 +1,88 @@
1/*
2 * linux/arch/arm/mm/copypage-v4wt.S
3 *
4 * Copyright (C) 1995-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is for CPUs with a writethrough cache and 'flush ID cache' is
11 * the only supported cache operation.
12 */
13#include <linux/init.h>
14#include <linux/highmem.h>
15
16/*
17 * ARMv4 optimised copy_user_highpage
18 *
19 * Since we have writethrough caches, we don't have to worry about
20 * dirty data in the cache. However, we do have to ensure that
21 * subsequent reads are up to date.
22 */
23static void __attribute__((naked))
24v4wt_copy_user_page(void *kto, const void *kfrom)
25{
26 asm("\
27 stmfd sp!, {r4, lr} @ 2\n\
28 mov r2, %0 @ 1\n\
29 ldmia r1!, {r3, r4, ip, lr} @ 4\n\
301: stmia r0!, {r3, r4, ip, lr} @ 4\n\
31 ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\
32 stmia r0!, {r3, r4, ip, lr} @ 4\n\
33 ldmia r1!, {r3, r4, ip, lr} @ 4\n\
34 stmia r0!, {r3, r4, ip, lr} @ 4\n\
35 ldmia r1!, {r3, r4, ip, lr} @ 4\n\
36 subs r2, r2, #1 @ 1\n\
37 stmia r0!, {r3, r4, ip, lr} @ 4\n\
38 ldmneia r1!, {r3, r4, ip, lr} @ 4\n\
39 bne 1b @ 1\n\
40 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache\n\
41 ldmfd sp!, {r4, pc} @ 3"
42 :
43 : "I" (PAGE_SIZE / 64));
44}
45
46void v4wt_copy_user_highpage(struct page *to, struct page *from,
47 unsigned long vaddr)
48{
49 void *kto, *kfrom;
50
51 kto = kmap_atomic(to, KM_USER0);
52 kfrom = kmap_atomic(from, KM_USER1);
53 v4wt_copy_user_page(kto, kfrom);
54 kunmap_atomic(kfrom, KM_USER1);
55 kunmap_atomic(kto, KM_USER0);
56}
57
58/*
59 * ARMv4 optimised clear_user_page
60 *
61 * Same story as above.
62 */
63void v4wt_clear_user_highpage(struct page *page, unsigned long vaddr)
64{
65 void *ptr, *kaddr = kmap_atomic(page, KM_USER0);
66 asm volatile("\
67 mov r1, %2 @ 1\n\
68 mov r2, #0 @ 1\n\
69 mov r3, #0 @ 1\n\
70 mov ip, #0 @ 1\n\
71 mov lr, #0 @ 1\n\
721: stmia %0!, {r2, r3, ip, lr} @ 4\n\
73 stmia %0!, {r2, r3, ip, lr} @ 4\n\
74 stmia %0!, {r2, r3, ip, lr} @ 4\n\
75 stmia %0!, {r2, r3, ip, lr} @ 4\n\
76 subs r1, r1, #1 @ 1\n\
77 bne 1b @ 1\n\
78 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache"
79 : "=r" (ptr)
80 : "0" (kaddr), "I" (PAGE_SIZE / 64)
81 : "r1", "r2", "r3", "ip", "lr");
82 kunmap_atomic(kaddr, KM_USER0);
83}
84
85struct cpu_user_fns v4wt_user_fns __initdata = {
86 .cpu_clear_user_highpage = v4wt_clear_user_highpage,
87 .cpu_copy_user_highpage = v4wt_copy_user_highpage,
88};
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 0e21c0767580..4127a7bddfe5 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -10,8 +10,8 @@
10#include <linux/init.h> 10#include <linux/init.h>
11#include <linux/spinlock.h> 11#include <linux/spinlock.h>
12#include <linux/mm.h> 12#include <linux/mm.h>
13#include <linux/highmem.h>
13 14
14#include <asm/page.h>
15#include <asm/pgtable.h> 15#include <asm/pgtable.h>
16#include <asm/shmparam.h> 16#include <asm/shmparam.h>
17#include <asm/tlbflush.h> 17#include <asm/tlbflush.h>
@@ -33,41 +33,56 @@ static DEFINE_SPINLOCK(v6_lock);
33 * Copy the user page. No aliasing to deal with so we can just 33 * Copy the user page. No aliasing to deal with so we can just
34 * attack the kernel's existing mapping of these pages. 34 * attack the kernel's existing mapping of these pages.
35 */ 35 */
36static void v6_copy_user_page_nonaliasing(void *kto, const void *kfrom, unsigned long vaddr) 36static void v6_copy_user_highpage_nonaliasing(struct page *to,
37 struct page *from, unsigned long vaddr)
37{ 38{
39 void *kto, *kfrom;
40
41 kfrom = kmap_atomic(from, KM_USER0);
42 kto = kmap_atomic(to, KM_USER1);
38 copy_page(kto, kfrom); 43 copy_page(kto, kfrom);
44 kunmap_atomic(kto, KM_USER1);
45 kunmap_atomic(kfrom, KM_USER0);
39} 46}
40 47
41/* 48/*
42 * Clear the user page. No aliasing to deal with so we can just 49 * Clear the user page. No aliasing to deal with so we can just
43 * attack the kernel's existing mapping of this page. 50 * attack the kernel's existing mapping of this page.
44 */ 51 */
45static void v6_clear_user_page_nonaliasing(void *kaddr, unsigned long vaddr) 52static void v6_clear_user_highpage_nonaliasing(struct page *page, unsigned long vaddr)
46{ 53{
54 void *kaddr = kmap_atomic(page, KM_USER0);
47 clear_page(kaddr); 55 clear_page(kaddr);
56 kunmap_atomic(kaddr, KM_USER0);
48} 57}
49 58
50/* 59/*
51 * Copy the page, taking account of the cache colour. 60 * Discard data in the kernel mapping for the new page.
61 * FIXME: needs this MCRR to be supported.
52 */ 62 */
53static void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned long vaddr) 63static void discard_old_kernel_data(void *kto)
54{ 64{
55 unsigned int offset = CACHE_COLOUR(vaddr);
56 unsigned long from, to;
57 struct page *page = virt_to_page(kfrom);
58
59 if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
60 __flush_dcache_page(page_mapping(page), page);
61
62 /*
63 * Discard data in the kernel mapping for the new page.
64 * FIXME: needs this MCRR to be supported.
65 */
66 __asm__("mcrr p15, 0, %1, %0, c6 @ 0xec401f06" 65 __asm__("mcrr p15, 0, %1, %0, c6 @ 0xec401f06"
67 : 66 :
68 : "r" (kto), 67 : "r" (kto),
69 "r" ((unsigned long)kto + PAGE_SIZE - L1_CACHE_BYTES) 68 "r" ((unsigned long)kto + PAGE_SIZE - L1_CACHE_BYTES)
70 : "cc"); 69 : "cc");
70}
71
72/*
73 * Copy the page, taking account of the cache colour.
74 */
75static void v6_copy_user_highpage_aliasing(struct page *to,
76 struct page *from, unsigned long vaddr)
77{
78 unsigned int offset = CACHE_COLOUR(vaddr);
79 unsigned long kfrom, kto;
80
81 if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
82 __flush_dcache_page(page_mapping(from), from);
83
84 /* FIXME: not highmem safe */
85 discard_old_kernel_data(page_address(to));
71 86
72 /* 87 /*
73 * Now copy the page using the same cache colour as the 88 * Now copy the page using the same cache colour as the
@@ -75,16 +90,16 @@ static void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned lo
75 */ 90 */
76 spin_lock(&v6_lock); 91 spin_lock(&v6_lock);
77 92
78 set_pte_ext(TOP_PTE(from_address) + offset, pfn_pte(__pa(kfrom) >> PAGE_SHIFT, PAGE_KERNEL), 0); 93 set_pte_ext(TOP_PTE(from_address) + offset, pfn_pte(page_to_pfn(from), PAGE_KERNEL), 0);
79 set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(__pa(kto) >> PAGE_SHIFT, PAGE_KERNEL), 0); 94 set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(page_to_pfn(to), PAGE_KERNEL), 0);
80 95
81 from = from_address + (offset << PAGE_SHIFT); 96 kfrom = from_address + (offset << PAGE_SHIFT);
82 to = to_address + (offset << PAGE_SHIFT); 97 kto = to_address + (offset << PAGE_SHIFT);
83 98
84 flush_tlb_kernel_page(from); 99 flush_tlb_kernel_page(kfrom);
85 flush_tlb_kernel_page(to); 100 flush_tlb_kernel_page(kto);
86 101
87 copy_page((void *)to, (void *)from); 102 copy_page((void *)kto, (void *)kfrom);
88 103
89 spin_unlock(&v6_lock); 104 spin_unlock(&v6_lock);
90} 105}
@@ -94,20 +109,13 @@ static void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned lo
94 * so remap the kernel page into the same cache colour as the user 109 * so remap the kernel page into the same cache colour as the user
95 * page. 110 * page.
96 */ 111 */
97static void v6_clear_user_page_aliasing(void *kaddr, unsigned long vaddr) 112static void v6_clear_user_highpage_aliasing(struct page *page, unsigned long vaddr)
98{ 113{
99 unsigned int offset = CACHE_COLOUR(vaddr); 114 unsigned int offset = CACHE_COLOUR(vaddr);
100 unsigned long to = to_address + (offset << PAGE_SHIFT); 115 unsigned long to = to_address + (offset << PAGE_SHIFT);
101 116
102 /* 117 /* FIXME: not highmem safe */
103 * Discard data in the kernel mapping for the new page 118 discard_old_kernel_data(page_address(page));
104 * FIXME: needs this MCRR to be supported.
105 */
106 __asm__("mcrr p15, 0, %1, %0, c6 @ 0xec401f06"
107 :
108 : "r" (kaddr),
109 "r" ((unsigned long)kaddr + PAGE_SIZE - L1_CACHE_BYTES)
110 : "cc");
111 119
112 /* 120 /*
113 * Now clear the page using the same cache colour as 121 * Now clear the page using the same cache colour as
@@ -115,7 +123,7 @@ static void v6_clear_user_page_aliasing(void *kaddr, unsigned long vaddr)
115 */ 123 */
116 spin_lock(&v6_lock); 124 spin_lock(&v6_lock);
117 125
118 set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(__pa(kaddr) >> PAGE_SHIFT, PAGE_KERNEL), 0); 126 set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(page_to_pfn(page), PAGE_KERNEL), 0);
119 flush_tlb_kernel_page(to); 127 flush_tlb_kernel_page(to);
120 clear_page((void *)to); 128 clear_page((void *)to);
121 129
@@ -123,15 +131,15 @@ static void v6_clear_user_page_aliasing(void *kaddr, unsigned long vaddr)
123} 131}
124 132
125struct cpu_user_fns v6_user_fns __initdata = { 133struct cpu_user_fns v6_user_fns __initdata = {
126 .cpu_clear_user_page = v6_clear_user_page_nonaliasing, 134 .cpu_clear_user_highpage = v6_clear_user_highpage_nonaliasing,
127 .cpu_copy_user_page = v6_copy_user_page_nonaliasing, 135 .cpu_copy_user_highpage = v6_copy_user_highpage_nonaliasing,
128}; 136};
129 137
130static int __init v6_userpage_init(void) 138static int __init v6_userpage_init(void)
131{ 139{
132 if (cache_is_vipt_aliasing()) { 140 if (cache_is_vipt_aliasing()) {
133 cpu_user.cpu_clear_user_page = v6_clear_user_page_aliasing; 141 cpu_user.cpu_clear_user_highpage = v6_clear_user_highpage_aliasing;
134 cpu_user.cpu_copy_user_page = v6_copy_user_page_aliasing; 142 cpu_user.cpu_copy_user_highpage = v6_copy_user_highpage_aliasing;
135 } 143 }
136 144
137 return 0; 145 return 0;
diff --git a/arch/arm/mm/copypage-xsc3.S b/arch/arm/mm/copypage-xsc3.S
deleted file mode 100644
index 9a2cb4332b4c..000000000000
--- a/arch/arm/mm/copypage-xsc3.S
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * linux/arch/arm/lib/copypage-xsc3.S
3 *
4 * Copyright (C) 2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Adapted for 3rd gen XScale core, no more mini-dcache
11 * Author: Matt Gilbert (matthew.m.gilbert@intel.com)
12 */
13
14#include <linux/linkage.h>
15#include <linux/init.h>
16#include <asm/asm-offsets.h>
17
18/*
19 * General note:
20 * We don't really want write-allocate cache behaviour for these functions
21 * since that will just eat through 8K of the cache.
22 */
23
24 .text
25 .align 5
26/*
27 * XSC3 optimised copy_user_page
28 * r0 = destination
29 * r1 = source
30 * r2 = virtual user address of ultimate destination page
31 *
32 * The source page may have some clean entries in the cache already, but we
33 * can safely ignore them - break_cow() will flush them out of the cache
34 * if we eventually end up using our copied page.
35 *
36 */
37ENTRY(xsc3_mc_copy_user_page)
38 stmfd sp!, {r4, r5, lr}
39 mov lr, #PAGE_SZ/64-1
40
41 pld [r1, #0]
42 pld [r1, #32]
431: pld [r1, #64]
44 pld [r1, #96]
45
462: ldrd r2, [r1], #8
47 mov ip, r0
48 ldrd r4, [r1], #8
49 mcr p15, 0, ip, c7, c6, 1 @ invalidate
50 strd r2, [r0], #8
51 ldrd r2, [r1], #8
52 strd r4, [r0], #8
53 ldrd r4, [r1], #8
54 strd r2, [r0], #8
55 strd r4, [r0], #8
56 ldrd r2, [r1], #8
57 mov ip, r0
58 ldrd r4, [r1], #8
59 mcr p15, 0, ip, c7, c6, 1 @ invalidate
60 strd r2, [r0], #8
61 ldrd r2, [r1], #8
62 subs lr, lr, #1
63 strd r4, [r0], #8
64 ldrd r4, [r1], #8
65 strd r2, [r0], #8
66 strd r4, [r0], #8
67 bgt 1b
68 beq 2b
69
70 ldmfd sp!, {r4, r5, pc}
71
72 .align 5
73/*
74 * XScale optimised clear_user_page
75 * r0 = destination
76 * r1 = virtual user address of ultimate destination page
77 */
78ENTRY(xsc3_mc_clear_user_page)
79 mov r1, #PAGE_SZ/32
80 mov r2, #0
81 mov r3, #0
821: mcr p15, 0, r0, c7, c6, 1 @ invalidate line
83 strd r2, [r0], #8
84 strd r2, [r0], #8
85 strd r2, [r0], #8
86 strd r2, [r0], #8
87 subs r1, r1, #1
88 bne 1b
89 mov pc, lr
90
91 __INITDATA
92
93 .type xsc3_mc_user_fns, #object
94ENTRY(xsc3_mc_user_fns)
95 .long xsc3_mc_clear_user_page
96 .long xsc3_mc_copy_user_page
97 .size xsc3_mc_user_fns, . - xsc3_mc_user_fns
diff --git a/arch/arm/mm/copypage-xsc3.c b/arch/arm/mm/copypage-xsc3.c
new file mode 100644
index 000000000000..39a994542cad
--- /dev/null
+++ b/arch/arm/mm/copypage-xsc3.c
@@ -0,0 +1,113 @@
1/*
2 * linux/arch/arm/mm/copypage-xsc3.S
3 *
4 * Copyright (C) 2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Adapted for 3rd gen XScale core, no more mini-dcache
11 * Author: Matt Gilbert (matthew.m.gilbert@intel.com)
12 */
13#include <linux/init.h>
14#include <linux/highmem.h>
15
16/*
17 * General note:
18 * We don't really want write-allocate cache behaviour for these functions
19 * since that will just eat through 8K of the cache.
20 */
21
22/*
23 * XSC3 optimised copy_user_highpage
24 * r0 = destination
25 * r1 = source
26 *
27 * The source page may have some clean entries in the cache already, but we
28 * can safely ignore them - break_cow() will flush them out of the cache
29 * if we eventually end up using our copied page.
30 *
31 */
32static void __attribute__((naked))
33xsc3_mc_copy_user_page(void *kto, const void *kfrom)
34{
35 asm("\
36 stmfd sp!, {r4, r5, lr} \n\
37 mov lr, %0 \n\
38 \n\
39 pld [r1, #0] \n\
40 pld [r1, #32] \n\
411: pld [r1, #64] \n\
42 pld [r1, #96] \n\
43 \n\
442: ldrd r2, [r1], #8 \n\
45 mov ip, r0 \n\
46 ldrd r4, [r1], #8 \n\
47 mcr p15, 0, ip, c7, c6, 1 @ invalidate\n\
48 strd r2, [r0], #8 \n\
49 ldrd r2, [r1], #8 \n\
50 strd r4, [r0], #8 \n\
51 ldrd r4, [r1], #8 \n\
52 strd r2, [r0], #8 \n\
53 strd r4, [r0], #8 \n\
54 ldrd r2, [r1], #8 \n\
55 mov ip, r0 \n\
56 ldrd r4, [r1], #8 \n\
57 mcr p15, 0, ip, c7, c6, 1 @ invalidate\n\
58 strd r2, [r0], #8 \n\
59 ldrd r2, [r1], #8 \n\
60 subs lr, lr, #1 \n\
61 strd r4, [r0], #8 \n\
62 ldrd r4, [r1], #8 \n\
63 strd r2, [r0], #8 \n\
64 strd r4, [r0], #8 \n\
65 bgt 1b \n\
66 beq 2b \n\
67 \n\
68 ldmfd sp!, {r4, r5, pc}"
69 :
70 : "I" (PAGE_SIZE / 64 - 1));
71}
72
73void xsc3_mc_copy_user_highpage(struct page *to, struct page *from,
74 unsigned long vaddr)
75{
76 void *kto, *kfrom;
77
78 kto = kmap_atomic(to, KM_USER0);
79 kfrom = kmap_atomic(from, KM_USER1);
80 xsc3_mc_copy_user_page(kto, kfrom);
81 kunmap_atomic(kfrom, KM_USER1);
82 kunmap_atomic(kto, KM_USER0);
83}
84
85/*
86 * XScale optimised clear_user_page
87 * r0 = destination
88 * r1 = virtual user address of ultimate destination page
89 */
90void xsc3_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
91{
92 void *ptr, *kaddr = kmap_atomic(page, KM_USER0);
93 asm volatile ("\
94 mov r1, %2 \n\
95 mov r2, #0 \n\
96 mov r3, #0 \n\
971: mcr p15, 0, %0, c7, c6, 1 @ invalidate line\n\
98 strd r2, [%0], #8 \n\
99 strd r2, [%0], #8 \n\
100 strd r2, [%0], #8 \n\
101 strd r2, [%0], #8 \n\
102 subs r1, r1, #1 \n\
103 bne 1b"
104 : "=r" (ptr)
105 : "0" (kaddr), "I" (PAGE_SIZE / 32)
106 : "r1", "r2", "r3");
107 kunmap_atomic(kaddr, KM_USER0);
108}
109
110struct cpu_user_fns xsc3_mc_user_fns __initdata = {
111 .cpu_clear_user_highpage = xsc3_mc_clear_user_highpage,
112 .cpu_copy_user_highpage = xsc3_mc_copy_user_highpage,
113};
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index bad49331bbf9..d18f2397ee2d 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -15,8 +15,8 @@
15 */ 15 */
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/mm.h> 17#include <linux/mm.h>
18#include <linux/highmem.h>
18 19
19#include <asm/page.h>
20#include <asm/pgtable.h> 20#include <asm/pgtable.h>
21#include <asm/tlbflush.h> 21#include <asm/tlbflush.h>
22#include <asm/cacheflush.h> 22#include <asm/cacheflush.h>
@@ -35,7 +35,7 @@
35static DEFINE_SPINLOCK(minicache_lock); 35static DEFINE_SPINLOCK(minicache_lock);
36 36
37/* 37/*
38 * XScale mini-dcache optimised copy_user_page 38 * XScale mini-dcache optimised copy_user_highpage
39 * 39 *
40 * We flush the destination cache lines just before we write the data into the 40 * We flush the destination cache lines just before we write the data into the
41 * corresponding address. Since the Dcache is read-allocate, this removes the 41 * corresponding address. Since the Dcache is read-allocate, this removes the
@@ -90,48 +90,53 @@ mc_copy_user_page(void *from, void *to)
90 : "r" (from), "r" (to), "I" (PAGE_SIZE / 64 - 1)); 90 : "r" (from), "r" (to), "I" (PAGE_SIZE / 64 - 1));
91} 91}
92 92
93void xscale_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr) 93void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
94 unsigned long vaddr)
94{ 95{
95 struct page *page = virt_to_page(kfrom); 96 void *kto = kmap_atomic(to, KM_USER1);
96 97
97 if (test_and_clear_bit(PG_dcache_dirty, &page->flags)) 98 if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
98 __flush_dcache_page(page_mapping(page), page); 99 __flush_dcache_page(page_mapping(from), from);
99 100
100 spin_lock(&minicache_lock); 101 spin_lock(&minicache_lock);
101 102
102 set_pte_ext(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot), 0); 103 set_pte_ext(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(page_to_pfn(from), minicache_pgprot), 0);
103 flush_tlb_kernel_page(COPYPAGE_MINICACHE); 104 flush_tlb_kernel_page(COPYPAGE_MINICACHE);
104 105
105 mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto); 106 mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto);
106 107
107 spin_unlock(&minicache_lock); 108 spin_unlock(&minicache_lock);
109
110 kunmap_atomic(kto, KM_USER1);
108} 111}
109 112
110/* 113/*
111 * XScale optimised clear_user_page 114 * XScale optimised clear_user_page
112 */ 115 */
113void __attribute__((naked)) 116void
114xscale_mc_clear_user_page(void *kaddr, unsigned long vaddr) 117xscale_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
115{ 118{
119 void *ptr, *kaddr = kmap_atomic(page, KM_USER0);
116 asm volatile( 120 asm volatile(
117 "mov r1, %0 \n\ 121 "mov r1, %2 \n\
118 mov r2, #0 \n\ 122 mov r2, #0 \n\
119 mov r3, #0 \n\ 123 mov r3, #0 \n\
1201: mov ip, r0 \n\ 1241: mov ip, %0 \n\
121 strd r2, [r0], #8 \n\ 125 strd r2, [%0], #8 \n\
122 strd r2, [r0], #8 \n\ 126 strd r2, [%0], #8 \n\
123 strd r2, [r0], #8 \n\ 127 strd r2, [%0], #8 \n\
124 strd r2, [r0], #8 \n\ 128 strd r2, [%0], #8 \n\
125 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\ 129 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
126 subs r1, r1, #1 \n\ 130 subs r1, r1, #1 \n\
127 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\ 131 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
128 bne 1b \n\ 132 bne 1b"
129 mov pc, lr" 133 : "=r" (ptr)
130 : 134 : "0" (kaddr), "I" (PAGE_SIZE / 32)
131 : "I" (PAGE_SIZE / 32)); 135 : "r1", "r2", "r3", "ip");
136 kunmap_atomic(kaddr, KM_USER0);
132} 137}
133 138
134struct cpu_user_fns xscale_mc_user_fns __initdata = { 139struct cpu_user_fns xscale_mc_user_fns __initdata = {
135 .cpu_clear_user_page = xscale_mc_clear_user_page, 140 .cpu_clear_user_highpage = xscale_mc_clear_user_highpage,
136 .cpu_copy_user_page = xscale_mc_copy_user_page, 141 .cpu_copy_user_highpage = xscale_mc_copy_user_highpage,
137}; 142};
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 2df8d9facf57..ffd8b228a139 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -14,6 +14,7 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/kprobes.h> 15#include <linux/kprobes.h>
16#include <linux/uaccess.h> 16#include <linux/uaccess.h>
17#include <linux/page-flags.h>
17 18
18#include <asm/system.h> 19#include <asm/system.h>
19#include <asm/pgtable.h> 20#include <asm/pgtable.h>
@@ -83,13 +84,14 @@ void show_pte(struct mm_struct *mm, unsigned long addr)
83 break; 84 break;
84 } 85 }
85 86
86#ifndef CONFIG_HIGHMEM
87 /* We must not map this if we have highmem enabled */ 87 /* We must not map this if we have highmem enabled */
88 if (PageHighMem(pfn_to_page(pmd_val(*pmd) >> PAGE_SHIFT)))
89 break;
90
88 pte = pte_offset_map(pmd, addr); 91 pte = pte_offset_map(pmd, addr);
89 printk(", *pte=%08lx", pte_val(*pte)); 92 printk(", *pte=%08lx", pte_val(*pte));
90 printk(", *ppte=%08lx", pte_val(pte[-PTRS_PER_PTE])); 93 printk(", *ppte=%08lx", pte_val(pte[-PTRS_PER_PTE]));
91 pte_unmap(pte); 94 pte_unmap(pte);
92#endif
93 } while(0); 95 } while(0);
94 96
95 printk("\n"); 97 printk("\n");
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 82c4b4217989..ab5c9abd5c34 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -64,10 +64,11 @@ static int __init parse_tag_initrd2(const struct tag *tag)
64__tagtable(ATAG_INITRD2, parse_tag_initrd2); 64__tagtable(ATAG_INITRD2, parse_tag_initrd2);
65 65
66/* 66/*
67 * This is used to pass memory configuration data from paging_init 67 * This keeps memory configuration data used by a couple memory
68 * to mem_init, and by show_mem() to skip holes in the memory map. 68 * initialization functions, as well as show_mem() for the skipping
69 * of holes in the memory map. It is populated by arm_add_memory().
69 */ 70 */
70static struct meminfo meminfo = { 0, }; 71struct meminfo meminfo;
71 72
72void show_mem(void) 73void show_mem(void)
73{ 74{
@@ -331,13 +332,12 @@ static void __init bootmem_free_node(int node, struct meminfo *mi)
331 free_area_init_node(node, zone_size, start_pfn, zhole_size); 332 free_area_init_node(node, zone_size, start_pfn, zhole_size);
332} 333}
333 334
334void __init bootmem_init(struct meminfo *mi) 335void __init bootmem_init(void)
335{ 336{
337 struct meminfo *mi = &meminfo;
336 unsigned long memend_pfn = 0; 338 unsigned long memend_pfn = 0;
337 int node, initrd_node; 339 int node, initrd_node;
338 340
339 memcpy(&meminfo, mi, sizeof(meminfo));
340
341 /* 341 /*
342 * Locate which node contains the ramdisk image, if any. 342 * Locate which node contains the ramdisk image, if any.
343 */ 343 */
@@ -394,20 +394,22 @@ void __init bootmem_init(struct meminfo *mi)
394 max_pfn = max_low_pfn = memend_pfn - PHYS_PFN_OFFSET; 394 max_pfn = max_low_pfn = memend_pfn - PHYS_PFN_OFFSET;
395} 395}
396 396
397static inline void free_area(unsigned long addr, unsigned long end, char *s) 397static inline int free_area(unsigned long pfn, unsigned long end, char *s)
398{ 398{
399 unsigned int size = (end - addr) >> 10; 399 unsigned int pages = 0, size = (end - pfn) << (PAGE_SHIFT - 10);
400 400
401 for (; addr < end; addr += PAGE_SIZE) { 401 for (; pfn < end; pfn++) {
402 struct page *page = virt_to_page(addr); 402 struct page *page = pfn_to_page(pfn);
403 ClearPageReserved(page); 403 ClearPageReserved(page);
404 init_page_count(page); 404 init_page_count(page);
405 free_page(addr); 405 __free_page(page);
406 totalram_pages++; 406 pages++;
407 } 407 }
408 408
409 if (size && s) 409 if (size && s)
410 printk(KERN_INFO "Freeing %s memory: %dK\n", s, size); 410 printk(KERN_INFO "Freeing %s memory: %dK\n", s, size);
411
412 return pages;
411} 413}
412 414
413static inline void 415static inline void
@@ -478,13 +480,9 @@ static void __init free_unused_memmap_node(int node, struct meminfo *mi)
478 */ 480 */
479void __init mem_init(void) 481void __init mem_init(void)
480{ 482{
481 unsigned int codepages, datapages, initpages; 483 unsigned int codesize, datasize, initsize;
482 int i, node; 484 int i, node;
483 485
484 codepages = &_etext - &_text;
485 datapages = &_end - &__data_start;
486 initpages = &__init_end - &__init_begin;
487
488#ifndef CONFIG_DISCONTIGMEM 486#ifndef CONFIG_DISCONTIGMEM
489 max_mapnr = virt_to_page(high_memory) - mem_map; 487 max_mapnr = virt_to_page(high_memory) - mem_map;
490#endif 488#endif
@@ -501,7 +499,8 @@ void __init mem_init(void)
501 499
502#ifdef CONFIG_SA1111 500#ifdef CONFIG_SA1111
503 /* now that our DMA memory is actually so designated, we can free it */ 501 /* now that our DMA memory is actually so designated, we can free it */
504 free_area(PAGE_OFFSET, (unsigned long)swapper_pg_dir, NULL); 502 totalram_pages += free_area(PHYS_PFN_OFFSET,
503 __phys_to_pfn(__pa(swapper_pg_dir)), NULL);
505#endif 504#endif
506 505
507 /* 506 /*
@@ -509,18 +508,21 @@ void __init mem_init(void)
509 * real number of pages we have in this system 508 * real number of pages we have in this system
510 */ 509 */
511 printk(KERN_INFO "Memory:"); 510 printk(KERN_INFO "Memory:");
512
513 num_physpages = 0; 511 num_physpages = 0;
514 for (i = 0; i < meminfo.nr_banks; i++) { 512 for (i = 0; i < meminfo.nr_banks; i++) {
515 num_physpages += bank_pfn_size(&meminfo.bank[i]); 513 num_physpages += bank_pfn_size(&meminfo.bank[i]);
516 printk(" %ldMB", bank_phys_size(&meminfo.bank[i]) >> 20); 514 printk(" %ldMB", bank_phys_size(&meminfo.bank[i]) >> 20);
517 } 515 }
518
519 printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT)); 516 printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
517
518 codesize = &_etext - &_text;
519 datasize = &_end - &__data_start;
520 initsize = &__init_end - &__init_begin;
521
520 printk(KERN_NOTICE "Memory: %luKB available (%dK code, " 522 printk(KERN_NOTICE "Memory: %luKB available (%dK code, "
521 "%dK data, %dK init)\n", 523 "%dK data, %dK init)\n",
522 (unsigned long) nr_free_pages() << (PAGE_SHIFT-10), 524 (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
523 codepages >> 10, datapages >> 10, initpages >> 10); 525 codesize >> 10, datasize >> 10, initsize >> 10);
524 526
525 if (PAGE_SIZE >= 16384 && num_physpages <= 128) { 527 if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
526 extern int sysctl_overcommit_memory; 528 extern int sysctl_overcommit_memory;
@@ -535,11 +537,10 @@ void __init mem_init(void)
535 537
536void free_initmem(void) 538void free_initmem(void)
537{ 539{
538 if (!machine_is_integrator() && !machine_is_cintegrator()) { 540 if (!machine_is_integrator() && !machine_is_cintegrator())
539 free_area((unsigned long)(&__init_begin), 541 totalram_pages += free_area(__phys_to_pfn(__pa(&__init_begin)),
540 (unsigned long)(&__init_end), 542 __phys_to_pfn(__pa(&__init_end)),
541 "init"); 543 "init");
542 }
543} 544}
544 545
545#ifdef CONFIG_BLK_DEV_INITRD 546#ifdef CONFIG_BLK_DEV_INITRD
@@ -549,7 +550,9 @@ static int keep_initrd;
549void free_initrd_mem(unsigned long start, unsigned long end) 550void free_initrd_mem(unsigned long start, unsigned long end)
550{ 551{
551 if (!keep_initrd) 552 if (!keep_initrd)
552 free_area(start, end, "initrd"); 553 totalram_pages += free_area(__phys_to_pfn(__pa(start)),
554 __phys_to_pfn(__pa(end)),
555 "initrd");
553} 556}
554 557
555static int __init keepinitrd_setup(char *__unused) 558static int __init keepinitrd_setup(char *__unused)
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 5d9f53907b4e..94367bdbb5a8 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -32,7 +32,7 @@ struct meminfo;
32struct pglist_data; 32struct pglist_data;
33 33
34void __init create_mapping(struct map_desc *md); 34void __init create_mapping(struct map_desc *md);
35void __init bootmem_init(struct meminfo *mi); 35void __init bootmem_init(void);
36void reserve_node_zero(struct pglist_data *pgdat); 36void reserve_node_zero(struct pglist_data *pgdat);
37 37
38extern void _text, _stext, _etext, __data_start, _end, __init_begin, __init_end; 38extern void _text, _stext, _etext, __data_start, _end, __init_begin, __init_end;
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 7f36c825718d..c0b9a78d7b87 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -646,61 +646,79 @@ static void __init early_vmalloc(char **arg)
646 "vmalloc area too small, limiting to %luMB\n", 646 "vmalloc area too small, limiting to %luMB\n",
647 vmalloc_reserve >> 20); 647 vmalloc_reserve >> 20);
648 } 648 }
649
650 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
651 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
652 printk(KERN_WARNING
653 "vmalloc area is too big, limiting to %luMB\n",
654 vmalloc_reserve >> 20);
655 }
649} 656}
650__early_param("vmalloc=", early_vmalloc); 657__early_param("vmalloc=", early_vmalloc);
651 658
652#define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve) 659#define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve)
653 660
654static int __init check_membank_valid(struct membank *mb) 661static void __init sanity_check_meminfo(void)
655{ 662{
656 /* 663 int i, j;
657 * Check whether this memory region has non-zero size or
658 * invalid node number.
659 */
660 if (mb->size == 0 || mb->node >= MAX_NUMNODES)
661 return 0;
662
663 /*
664 * Check whether this memory region would entirely overlap
665 * the vmalloc area.
666 */
667 if (phys_to_virt(mb->start) >= VMALLOC_MIN) {
668 printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
669 "(vmalloc region overlap).\n",
670 mb->start, mb->start + mb->size - 1);
671 return 0;
672 }
673
674 /*
675 * Check whether this memory region would partially overlap
676 * the vmalloc area.
677 */
678 if (phys_to_virt(mb->start + mb->size) < phys_to_virt(mb->start) ||
679 phys_to_virt(mb->start + mb->size) > VMALLOC_MIN) {
680 unsigned long newsize = VMALLOC_MIN - phys_to_virt(mb->start);
681
682 printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
683 "to -%.8lx (vmalloc region overlap).\n",
684 mb->start, mb->start + mb->size - 1,
685 mb->start + newsize - 1);
686 mb->size = newsize;
687 }
688 664
689 return 1; 665 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
690} 666 struct membank *bank = &meminfo.bank[j];
667 *bank = meminfo.bank[i];
691 668
692static void __init sanity_check_meminfo(struct meminfo *mi) 669#ifdef CONFIG_HIGHMEM
693{ 670 /*
694 int i, j; 671 * Split those memory banks which are partially overlapping
672 * the vmalloc area greatly simplifying things later.
673 */
674 if (__va(bank->start) < VMALLOC_MIN &&
675 bank->size > VMALLOC_MIN - __va(bank->start)) {
676 if (meminfo.nr_banks >= NR_BANKS) {
677 printk(KERN_CRIT "NR_BANKS too low, "
678 "ignoring high memory\n");
679 } else {
680 memmove(bank + 1, bank,
681 (meminfo.nr_banks - i) * sizeof(*bank));
682 meminfo.nr_banks++;
683 i++;
684 bank[1].size -= VMALLOC_MIN - __va(bank->start);
685 bank[1].start = __pa(VMALLOC_MIN - 1) + 1;
686 j++;
687 }
688 bank->size = VMALLOC_MIN - __va(bank->start);
689 }
690#else
691 /*
692 * Check whether this memory bank would entirely overlap
693 * the vmalloc area.
694 */
695 if (__va(bank->start) >= VMALLOC_MIN) {
696 printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
697 "(vmalloc region overlap).\n",
698 bank->start, bank->start + bank->size - 1);
699 continue;
700 }
695 701
696 for (i = 0, j = 0; i < mi->nr_banks; i++) { 702 /*
697 if (check_membank_valid(&mi->bank[i])) 703 * Check whether this memory bank would partially overlap
698 mi->bank[j++] = mi->bank[i]; 704 * the vmalloc area.
705 */
706 if (__va(bank->start + bank->size) > VMALLOC_MIN ||
707 __va(bank->start + bank->size) < __va(bank->start)) {
708 unsigned long newsize = VMALLOC_MIN - __va(bank->start);
709 printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
710 "to -%.8lx (vmalloc region overlap).\n",
711 bank->start, bank->start + bank->size - 1,
712 bank->start + newsize - 1);
713 bank->size = newsize;
714 }
715#endif
716 j++;
699 } 717 }
700 mi->nr_banks = j; 718 meminfo.nr_banks = j;
701} 719}
702 720
703static inline void prepare_page_table(struct meminfo *mi) 721static inline void prepare_page_table(void)
704{ 722{
705 unsigned long addr; 723 unsigned long addr;
706 724
@@ -721,7 +739,7 @@ static inline void prepare_page_table(struct meminfo *mi)
721 * Clear out all the kernel space mappings, except for the first 739 * Clear out all the kernel space mappings, except for the first
722 * memory bank, up to the end of the vmalloc region. 740 * memory bank, up to the end of the vmalloc region.
723 */ 741 */
724 for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size); 742 for (addr = __phys_to_virt(bank_phys_end(&meminfo.bank[0]));
725 addr < VMALLOC_END; addr += PGDIR_SIZE) 743 addr < VMALLOC_END; addr += PGDIR_SIZE)
726 pmd_clear(pmd_off_k(addr)); 744 pmd_clear(pmd_off_k(addr));
727} 745}
@@ -880,14 +898,14 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
880 * paging_init() sets up the page tables, initialises the zone memory 898 * paging_init() sets up the page tables, initialises the zone memory
881 * maps, and sets up the zero page, bad page and bad page tables. 899 * maps, and sets up the zero page, bad page and bad page tables.
882 */ 900 */
883void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc) 901void __init paging_init(struct machine_desc *mdesc)
884{ 902{
885 void *zero_page; 903 void *zero_page;
886 904
887 build_mem_type_table(); 905 build_mem_type_table();
888 sanity_check_meminfo(mi); 906 sanity_check_meminfo();
889 prepare_page_table(mi); 907 prepare_page_table();
890 bootmem_init(mi); 908 bootmem_init();
891 devicemaps_init(mdesc); 909 devicemaps_init(mdesc);
892 910
893 top_pmd = pmd_off_k(0xffff0000); 911 top_pmd = pmd_off_k(0xffff0000);
@@ -896,7 +914,7 @@ void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
896 * allocate the zero page. Note that we count on this going ok. 914 * allocate the zero page. Note that we count on this going ok.
897 */ 915 */
898 zero_page = alloc_bootmem_low_pages(PAGE_SIZE); 916 zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
899 memzero(zero_page, PAGE_SIZE); 917 memset(zero_page, 0, PAGE_SIZE);
900 empty_zero_page = virt_to_page(zero_page); 918 empty_zero_page = virt_to_page(zero_page);
901 flush_dcache_page(empty_zero_page); 919 flush_dcache_page(empty_zero_page);
902} 920}
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 07b62b238979..c085f4e8248b 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -41,27 +41,13 @@ void __init reserve_node_zero(pg_data_t *pgdat)
41 BOOTMEM_DEFAULT); 41 BOOTMEM_DEFAULT);
42} 42}
43 43
44static void __init sanity_check_meminfo(struct meminfo *mi)
45{
46 int i, j;
47
48 for (i = 0, j = 0; i < mi->nr_banks; i++) {
49 struct membank *mb = &mi->bank[i];
50
51 if (mb->size != 0 && mb->node < MAX_NUMNODES)
52 mi->bank[j++] = mi->bank[i];
53 }
54 mi->nr_banks = j;
55}
56
57/* 44/*
58 * paging_init() sets up the page tables, initialises the zone memory 45 * paging_init() sets up the page tables, initialises the zone memory
59 * maps, and sets up the zero page, bad page and bad page tables. 46 * maps, and sets up the zero page, bad page and bad page tables.
60 */ 47 */
61void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc) 48void __init paging_init(struct machine_desc *mdesc)
62{ 49{
63 sanity_check_meminfo(mi); 50 bootmem_init();
64 bootmem_init(mi);
65} 51}
66 52
67/* 53/*
diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c
index e0f19ab91163..2690146161ba 100644
--- a/arch/arm/mm/pgd.c
+++ b/arch/arm/mm/pgd.c
@@ -31,7 +31,7 @@ pgd_t *get_pgd_slow(struct mm_struct *mm)
31 if (!new_pgd) 31 if (!new_pgd)
32 goto no_pgd; 32 goto no_pgd;
33 33
34 memzero(new_pgd, FIRST_KERNEL_PGD_NR * sizeof(pgd_t)); 34 memset(new_pgd, 0, FIRST_KERNEL_PGD_NR * sizeof(pgd_t));
35 35
36 /* 36 /*
37 * Copy over the kernel and IO PGD entries 37 * Copy over the kernel and IO PGD entries
diff --git a/arch/arm/mm/proc-syms.c b/arch/arm/mm/proc-syms.c
index 2b5ba396e3a6..4ad3bf291ad3 100644
--- a/arch/arm/mm/proc-syms.c
+++ b/arch/arm/mm/proc-syms.c
@@ -33,8 +33,8 @@ EXPORT_SYMBOL(cpu_cache);
33 33
34#ifdef CONFIG_MMU 34#ifdef CONFIG_MMU
35#ifndef MULTI_USER 35#ifndef MULTI_USER
36EXPORT_SYMBOL(__cpu_clear_user_page); 36EXPORT_SYMBOL(__cpu_clear_user_highpage);
37EXPORT_SYMBOL(__cpu_copy_user_page); 37EXPORT_SYMBOL(__cpu_copy_user_highpage);
38#else 38#else
39EXPORT_SYMBOL(cpu_user); 39EXPORT_SYMBOL(cpu_user);
40#endif 40#endif
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 294943b85973..f0cc599facb7 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -71,6 +71,8 @@ ENTRY(cpu_v6_reset)
71 * IRQs are already disabled. 71 * IRQs are already disabled.
72 */ 72 */
73ENTRY(cpu_v6_do_idle) 73ENTRY(cpu_v6_do_idle)
74 mov r1, #0
75 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
74 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 76 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
75 mov pc, lr 77 mov pc, lr
76 78
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 4d3c0a73e7fb..d1ebec42521d 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -20,9 +20,17 @@
20 20
21#define TTB_C (1 << 0) 21#define TTB_C (1 << 0)
22#define TTB_S (1 << 1) 22#define TTB_S (1 << 1)
23#define TTB_RGN_NC (0 << 3)
24#define TTB_RGN_OC_WBWA (1 << 3)
23#define TTB_RGN_OC_WT (2 << 3) 25#define TTB_RGN_OC_WT (2 << 3)
24#define TTB_RGN_OC_WB (3 << 3) 26#define TTB_RGN_OC_WB (3 << 3)
25 27
28#ifndef CONFIG_SMP
29#define TTB_FLAGS TTB_C|TTB_RGN_OC_WB @ mark PTWs cacheable, outer WB
30#else
31#define TTB_FLAGS TTB_C|TTB_S|TTB_RGN_OC_WBWA @ mark PTWs cacheable and shared, outer WBWA
32#endif
33
26ENTRY(cpu_v7_proc_init) 34ENTRY(cpu_v7_proc_init)
27 mov pc, lr 35 mov pc, lr
28ENDPROC(cpu_v7_proc_init) 36ENDPROC(cpu_v7_proc_init)
@@ -55,6 +63,7 @@ ENDPROC(cpu_v7_reset)
55 * IRQs are already disabled. 63 * IRQs are already disabled.
56 */ 64 */
57ENTRY(cpu_v7_do_idle) 65ENTRY(cpu_v7_do_idle)
66 dsb @ WFI may enter a low-power mode
58 wfi 67 wfi
59 mov pc, lr 68 mov pc, lr
60ENDPROC(cpu_v7_do_idle) 69ENDPROC(cpu_v7_do_idle)
@@ -85,7 +94,7 @@ ENTRY(cpu_v7_switch_mm)
85#ifdef CONFIG_MMU 94#ifdef CONFIG_MMU
86 mov r2, #0 95 mov r2, #0
87 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 96 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
88 orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB 97 orr r0, r0, #TTB_FLAGS
89 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID 98 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
90 isb 99 isb
911: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 1001: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
@@ -162,6 +171,11 @@ cpu_v7_name:
162 * - cache type register is implemented 171 * - cache type register is implemented
163 */ 172 */
164__v7_setup: 173__v7_setup:
174#ifdef CONFIG_SMP
175 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
176 orr r0, r0, #(0x1 << 6)
177 mcr p15, 0, r0, c1, c0, 1
178#endif
165 adr r12, __v7_setup_stack @ the local stack 179 adr r12, __v7_setup_stack @ the local stack
166 stmia r12, {r0-r5, r7, r9, r11, lr} 180 stmia r12, {r0-r5, r7, r9, r11, lr}
167 bl v7_flush_dcache_all 181 bl v7_flush_dcache_all
@@ -174,8 +188,7 @@ __v7_setup:
174#ifdef CONFIG_MMU 188#ifdef CONFIG_MMU
175 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 189 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
176 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 190 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
177 orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB 191 orr r4, r4, #TTB_FLAGS
178 mcr p15, 0, r4, c2, c0, 0 @ load TTB0
179 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 192 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
180 mov r10, #0x1f @ domains 0, 1 = manager 193 mov r10, #0x1f @ domains 0, 1 = manager
181 mcr p15, 0, r10, c3, c0, 0 @ load domain access register 194 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index b2a7e3fad117..a1612958a59e 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -8,11 +8,13 @@ choice
8 8
9config ARCH_MX2 9config ARCH_MX2
10 bool "MX2-based" 10 bool "MX2-based"
11 select CPU_ARM926T
11 help 12 help
12 This enables support for systems based on the Freescale i.MX2 family 13 This enables support for systems based on the Freescale i.MX2 family
13 14
14config ARCH_MX3 15config ARCH_MX3
15 bool "MX3-based" 16 bool "MX3-based"
17 select CPU_V6
16 help 18 help
17 This enables support for systems based on the Freescale i.MX3 family 19 This enables support for systems based on the Freescale i.MX3 family
18 20
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
index b296f19fd89a..214274344442 100644
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ b/arch/arm/plat-mxc/dma-mx1-mx2.c
@@ -34,7 +34,7 @@
34#include <asm/system.h> 34#include <asm/system.h>
35#include <asm/irq.h> 35#include <asm/irq.h>
36#include <mach/hardware.h> 36#include <mach/hardware.h>
37#include <asm/dma.h> 37#include <mach/dma.h>
38#include <mach/dma-mx1-mx2.h> 38#include <mach/dma-mx1-mx2.h>
39 39
40#define DMA_DCR 0x00 /* Control Register */ 40#define DMA_DCR 0x00 /* Control Register */
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
index e85fd946116c..6cc6f0c8cb25 100644
--- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
@@ -22,7 +22,7 @@
22 * MA 02110-1301, USA. 22 * MA 02110-1301, USA.
23 */ 23 */
24 24
25#include <asm/dma.h> 25#include <mach/dma.h>
26 26
27#ifndef __ASM_ARCH_MXC_DMA_H 27#ifndef __ASM_ARCH_MXC_DMA_H
28#define __ASM_ARCH_MXC_DMA_H 28#define __ASM_ARCH_MXC_DMA_H
diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h
deleted file mode 100644
index c822d569a05e..000000000000
--- a/arch/arm/plat-mxc/include/mach/dma.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_DMA_H__
12#define __ASM_ARCH_MXC_DMA_H__
13
14#endif
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
index 5d4cb1196441..c0cb267e7403 100644
--- a/arch/arm/plat-mxc/include/mach/io.h
+++ b/arch/arm/plat-mxc/include/mach/io.h
@@ -35,8 +35,8 @@ __mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
35#endif 35#endif
36 36
37/* io address mapping macro */ 37/* io address mapping macro */
38#define __io(a) ((void __iomem *)(a)) 38#define __io(a) __typesafe_io(a)
39 39
40#define __mem_pci(a) (a) 40#define __mem_pci(a) (a)
41 41
42#endif 42#endif
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index d7a8d3ebed57..203688e6164e 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -13,17 +13,4 @@
13 13
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15 15
16/*
17 * Virtual view <-> DMA view memory address translations
18 * This macro is used to translate the virtual address to an address
19 * suitable to be passed to set_dma_addr()
20 */
21#define __virt_to_bus(a) __virt_to_phys(a)
22
23/*
24 * Used to convert an address for DMA operations to an address that the
25 * kernel can use.
26 */
27#define __bus_to_virt(a) __phys_to_virt(a)
28
29#endif /* __ASM_ARCH_MXC_MEMORY_H__ */ 16#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index a94f0c44ebc8..46d3b0b9ce69 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -14,9 +14,11 @@ config ARCH_OMAP1
14 14
15config ARCH_OMAP2 15config ARCH_OMAP2
16 bool "TI OMAP2" 16 bool "TI OMAP2"
17 select CPU_V6
17 18
18config ARCH_OMAP3 19config ARCH_OMAP3
19 bool "TI OMAP3" 20 bool "TI OMAP3"
21 select CPU_V7
20 22
21endchoice 23endchoice
22 24
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 50f8b4ad9a09..7686b9fa53f2 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -29,7 +29,7 @@
29 29
30#include <asm/system.h> 30#include <asm/system.h>
31#include <mach/hardware.h> 31#include <mach/hardware.h>
32#include <asm/dma.h> 32#include <mach/dma.h>
33 33
34#include <mach/tc.h> 34#include <mach/tc.h>
35 35
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 8679fbca6bbe..424049d83fbe 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -101,6 +101,7 @@
101#define OMAP24XX_GPIO_IRQSTATUS2 0x0028 101#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
102#define OMAP24XX_GPIO_IRQENABLE2 0x002c 102#define OMAP24XX_GPIO_IRQENABLE2 0x002c
103#define OMAP24XX_GPIO_IRQENABLE1 0x001c 103#define OMAP24XX_GPIO_IRQENABLE1 0x001c
104#define OMAP24XX_GPIO_WAKE_EN 0x0020
104#define OMAP24XX_GPIO_CTRL 0x0030 105#define OMAP24XX_GPIO_CTRL 0x0030
105#define OMAP24XX_GPIO_OE 0x0034 106#define OMAP24XX_GPIO_OE 0x0034
106#define OMAP24XX_GPIO_DATAIN 0x0038 107#define OMAP24XX_GPIO_DATAIN 0x0038
@@ -1551,7 +1552,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1551#endif 1552#endif
1552#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1553#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1553 case METHOD_GPIO_24XX: 1554 case METHOD_GPIO_24XX:
1554 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA; 1555 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1555 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1556 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1556 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1557 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1557 break; 1558 break;
@@ -1574,7 +1575,7 @@ static int omap_gpio_resume(struct sys_device *dev)
1574{ 1575{
1575 int i; 1576 int i;
1576 1577
1577 if (!cpu_is_omap24xx() && !cpu_is_omap16xx()) 1578 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1578 return 0; 1579 return 0;
1579 1580
1580 for (i = 0; i < gpio_bank_count; i++) { 1581 for (i = 0; i < gpio_bank_count; i++) {
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index adc83b7b8205..d92bf7964481 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -42,8 +42,8 @@
42 * We don't actually have real ISA nor PCI buses, but there is so many 42 * We don't actually have real ISA nor PCI buses, but there is so many
43 * drivers out there that might just work if we fake them... 43 * drivers out there that might just work if we fake them...
44 */ 44 */
45#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) 45#define __io(a) __typesafe_io(a)
46#define __mem_pci(a) (a) 46#define __mem_pci(a) (a)
47 47
48/* 48/*
49 * ---------------------------------------------------------------------------- 49 * ----------------------------------------------------------------------------
@@ -51,8 +51,6 @@
51 * ---------------------------------------------------------------------------- 51 * ----------------------------------------------------------------------------
52 */ 52 */
53 53
54#define PCIO_BASE 0
55
56#if defined(CONFIG_ARCH_OMAP1) 54#if defined(CONFIG_ARCH_OMAP1)
57 55
58#define IO_PHYS 0xFFFB0000 56#define IO_PHYS 0xFFFB0000
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h
index d40cac60b959..211c9f6619e9 100644
--- a/arch/arm/plat-omap/include/mach/memory.h
+++ b/arch/arm/plat-omap/include/mach/memory.h
@@ -43,18 +43,7 @@
43#endif 43#endif
44 44
45/* 45/*
46 * Conversion between SDRAM and fake PCI bus, used by USB
47 * NOTE: Physical address must be converted to Local Bus address
48 * on OMAP-1510 only
49 */
50
51/*
52 * Bus address is physical address, except for OMAP-1510 Local Bus. 46 * Bus address is physical address, except for OMAP-1510 Local Bus.
53 */
54#define __virt_to_bus(x) __virt_to_phys(x)
55#define __bus_to_virt(x) __phys_to_virt(x)
56
57/*
58 * OMAP-1510 bus address is translated into a Local Bus address if the 47 * OMAP-1510 bus address is translated into a Local Bus address if the
59 * OMAP bus type is lbus. We do the address translation based on the 48 * OMAP bus type is lbus. We do the address translation based on the
60 * device overriding the defaults used in the dma-mapping API. 49 * device overriding the defaults used in the dma-mapping API.
@@ -74,16 +63,16 @@
74 63
75#define __arch_page_to_dma(dev, page) ({is_lbus_device(dev) ? \ 64#define __arch_page_to_dma(dev, page) ({is_lbus_device(dev) ? \
76 (dma_addr_t)virt_to_lbus(page_address(page)) : \ 65 (dma_addr_t)virt_to_lbus(page_address(page)) : \
77 (dma_addr_t)__virt_to_bus(page_address(page));}) 66 (dma_addr_t)__virt_to_phys(page_address(page));})
78 67
79#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \ 68#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \
80 lbus_to_virt(addr) : \ 69 lbus_to_virt(addr) : \
81 __bus_to_virt(addr)); }) 70 __phys_to_virt(addr)); })
82 71
83#define __arch_virt_to_dma(dev, addr) ({ unsigned long __addr = (unsigned long)(addr); \ 72#define __arch_virt_to_dma(dev, addr) ({ unsigned long __addr = (unsigned long)(addr); \
84 (dma_addr_t) (is_lbus_device(dev) ? \ 73 (dma_addr_t) (is_lbus_device(dev) ? \
85 virt_to_lbus(__addr) : \ 74 virt_to_lbus(__addr) : \
86 __virt_to_bus(__addr)); }) 75 __virt_to_phys(__addr)); })
87 76
88#endif /* CONFIG_ARCH_OMAP15XX */ 77#endif /* CONFIG_ARCH_OMAP15XX */
89 78
diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h
index 768eb6e7abcf..2a9c27ad4c37 100644
--- a/arch/arm/plat-omap/include/mach/pm.h
+++ b/arch/arm/plat-omap/include/mach/pm.h
@@ -128,7 +128,7 @@ void clk_deny_idle(struct clk *clk);
128 * clk_allow_idle - Counters previous clk_deny_idle 128 * clk_allow_idle - Counters previous clk_deny_idle
129 * @clk: clock signal handle 129 * @clk: clock signal handle
130 */ 130 */
131void clk_deny_idle(struct clk *clk); 131void clk_allow_idle(struct clk *clk);
132 132
133extern void omap_pm_idle(void); 133extern void omap_pm_idle(void);
134extern void omap_pm_suspend(void); 134extern void omap_pm_suspend(void);
diff --git a/arch/arm/plat-s3c/include/plat/iic.h b/arch/arm/plat-s3c/include/plat/iic.h
new file mode 100644
index 000000000000..5106acaa1d0e
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/iic.h
@@ -0,0 +1,33 @@
1/* arch/arm/mach-s3c2410/include/mach/iic.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - I2C Controller platfrom_device info
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_IIC_H
14#define __ASM_ARCH_IIC_H __FILE__
15
16#define S3C_IICFLG_FILTER (1<<0) /* enable s3c2440 filter */
17
18/* Notes:
19 * 1) All frequencies are expressed in Hz
20 * 2) A value of zero is `do not care`
21*/
22
23struct s3c2410_platform_i2c {
24 int bus_num; /* bus number to use */
25 unsigned int flags;
26 unsigned int slave_addr; /* slave address for controller */
27 unsigned long bus_freq; /* standard bus frequency */
28 unsigned long max_freq; /* max frequency for the bus */
29 unsigned long min_freq; /* min frequency for the bus */
30 unsigned int sda_delay; /* pclks (s3c2440 only) */
31};
32
33#endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h
new file mode 100644
index 000000000000..f4dcd14af059
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/nand.h
@@ -0,0 +1,50 @@
1/* arch/arm/mach-s3c2410/include/mach/nand.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - NAND device controller platfrom_device info
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* struct s3c2410_nand_set
14 *
15 * define an set of one or more nand chips registered with an unique mtd
16 *
17 * nr_chips = number of chips in this set
18 * nr_partitions = number of partitions pointed to be partitoons (or zero)
19 * name = name of set (optional)
20 * nr_map = map for low-layer logical to physical chip numbers (option)
21 * partitions = mtd partition list
22*/
23
24struct s3c2410_nand_set {
25 unsigned int disable_ecc : 1;
26
27 int nr_chips;
28 int nr_partitions;
29 char *name;
30 int *nr_map;
31 struct mtd_partition *partitions;
32 struct nand_ecclayout *ecc_layout;
33};
34
35struct s3c2410_platform_nand {
36 /* timing information for controller, all times in nanoseconds */
37
38 int tacls; /* time for active CLE/ALE to nWE/nOE */
39 int twrph0; /* active time for nWE/nOE */
40 int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
41
42 unsigned int ignore_unset_ecc : 1;
43
44 int nr_sets;
45 struct s3c2410_nand_set *sets;
46
47 void (*select_chip)(struct s3c2410_nand_set *,
48 int chip);
49};
50
diff --git a/arch/arm/plat-s3c/include/plat/regs-ac97.h b/arch/arm/plat-s3c/include/plat/regs-ac97.h
new file mode 100644
index 000000000000..c3878f7acb83
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-ac97.h
@@ -0,0 +1,67 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-ac97.h
2 *
3 * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2440 AC97 Controller
11*/
12
13#ifndef __ASM_ARCH_REGS_AC97_H
14#define __ASM_ARCH_REGS_AC97_H __FILE__
15
16#define S3C_AC97_GLBCTRL (0x00)
17
18#define S3C_AC97_GLBCTRL_CODECREADYIE (1<<22)
19#define S3C_AC97_GLBCTRL_PCMOUTURIE (1<<21)
20#define S3C_AC97_GLBCTRL_PCMINORIE (1<<20)
21#define S3C_AC97_GLBCTRL_MICINORIE (1<<19)
22#define S3C_AC97_GLBCTRL_PCMOUTTIE (1<<18)
23#define S3C_AC97_GLBCTRL_PCMINTIE (1<<17)
24#define S3C_AC97_GLBCTRL_MICINTIE (1<<16)
25#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF (0<<12)
26#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO (1<<12)
27#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA (2<<12)
28#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK (3<<12)
29#define S3C_AC97_GLBCTRL_PCMINTM_OFF (0<<10)
30#define S3C_AC97_GLBCTRL_PCMINTM_PIO (1<<10)
31#define S3C_AC97_GLBCTRL_PCMINTM_DMA (2<<10)
32#define S3C_AC97_GLBCTRL_PCMINTM_MASK (3<<10)
33#define S3C_AC97_GLBCTRL_MICINTM_OFF (0<<8)
34#define S3C_AC97_GLBCTRL_MICINTM_PIO (1<<8)
35#define S3C_AC97_GLBCTRL_MICINTM_DMA (2<<8)
36#define S3C_AC97_GLBCTRL_MICINTM_MASK (3<<8)
37#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE (1<<3)
38#define S3C_AC97_GLBCTRL_ACLINKON (1<<2)
39#define S3C_AC97_GLBCTRL_WARMRESET (1<<1)
40#define S3C_AC97_GLBCTRL_COLDRESET (1<<0)
41
42#define S3C_AC97_GLBSTAT (0x04)
43
44#define S3C_AC97_GLBSTAT_CODECREADY (1<<22)
45#define S3C_AC97_GLBSTAT_PCMOUTUR (1<<21)
46#define S3C_AC97_GLBSTAT_PCMINORI (1<<20)
47#define S3C_AC97_GLBSTAT_MICINORI (1<<19)
48#define S3C_AC97_GLBSTAT_PCMOUTTI (1<<18)
49#define S3C_AC97_GLBSTAT_PCMINTI (1<<17)
50#define S3C_AC97_GLBSTAT_MICINTI (1<<16)
51#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE (0<<0)
52#define S3C_AC97_GLBSTAT_MAINSTATE_INIT (1<<0)
53#define S3C_AC97_GLBSTAT_MAINSTATE_READY (2<<0)
54#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE (3<<0)
55#define S3C_AC97_GLBSTAT_MAINSTATE_LP (4<<0)
56#define S3C_AC97_GLBSTAT_MAINSTATE_WARM (5<<0)
57
58#define S3C_AC97_CODEC_CMD (0x08)
59
60#define S3C_AC97_CODEC_CMD_READ (1<<23)
61
62#define S3C_AC97_STAT (0x0c)
63#define S3C_AC97_PCM_ADDR (0x10)
64#define S3C_AC97_PCM_DATA (0x18)
65#define S3C_AC97_MIC_DATA (0x1C)
66
67#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/arch/arm/plat-s3c/include/plat/regs-iic.h b/arch/arm/plat-s3c/include/plat/regs-iic.h
new file mode 100644
index 000000000000..2f7c17de8ac8
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-iic.h
@@ -0,0 +1,56 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-iic.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 I2C Controller
11*/
12
13#ifndef __ASM_ARCH_REGS_IIC_H
14#define __ASM_ARCH_REGS_IIC_H __FILE__
15
16/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
17
18#define S3C2410_IICREG(x) (x)
19
20#define S3C2410_IICCON S3C2410_IICREG(0x00)
21#define S3C2410_IICSTAT S3C2410_IICREG(0x04)
22#define S3C2410_IICADD S3C2410_IICREG(0x08)
23#define S3C2410_IICDS S3C2410_IICREG(0x0C)
24#define S3C2440_IICLC S3C2410_IICREG(0x10)
25
26#define S3C2410_IICCON_ACKEN (1<<7)
27#define S3C2410_IICCON_TXDIV_16 (0<<6)
28#define S3C2410_IICCON_TXDIV_512 (1<<6)
29#define S3C2410_IICCON_IRQEN (1<<5)
30#define S3C2410_IICCON_IRQPEND (1<<4)
31#define S3C2410_IICCON_SCALE(x) ((x)&15)
32#define S3C2410_IICCON_SCALEMASK (0xf)
33
34#define S3C2410_IICSTAT_MASTER_RX (2<<6)
35#define S3C2410_IICSTAT_MASTER_TX (3<<6)
36#define S3C2410_IICSTAT_SLAVE_RX (0<<6)
37#define S3C2410_IICSTAT_SLAVE_TX (1<<6)
38#define S3C2410_IICSTAT_MODEMASK (3<<6)
39
40#define S3C2410_IICSTAT_START (1<<5)
41#define S3C2410_IICSTAT_BUSBUSY (1<<5)
42#define S3C2410_IICSTAT_TXRXEN (1<<4)
43#define S3C2410_IICSTAT_ARBITR (1<<3)
44#define S3C2410_IICSTAT_ASSLAVE (1<<2)
45#define S3C2410_IICSTAT_ADDR0 (1<<1)
46#define S3C2410_IICSTAT_LASTBIT (1<<0)
47
48#define S3C2410_IICLC_SDA_DELAY0 (0 << 0)
49#define S3C2410_IICLC_SDA_DELAY5 (1 << 0)
50#define S3C2410_IICLC_SDA_DELAY10 (2 << 0)
51#define S3C2410_IICLC_SDA_DELAY15 (3 << 0)
52#define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)
53
54#define S3C2410_IICLC_FILTER_ON (1<<2)
55
56#endif /* __ASM_ARCH_REGS_IIC_H */
diff --git a/arch/arm/plat-s3c/include/plat/regs-nand.h b/arch/arm/plat-s3c/include/plat/regs-nand.h
new file mode 100644
index 000000000000..b2caa4bca270
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-nand.h
@@ -0,0 +1,123 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-nand.h
2 *
3 * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 NAND register definitions
11*/
12
13#ifndef __ASM_ARM_REGS_NAND
14#define __ASM_ARM_REGS_NAND
15
16
17#define S3C2410_NFREG(x) (x)
18
19#define S3C2410_NFCONF S3C2410_NFREG(0x00)
20#define S3C2410_NFCMD S3C2410_NFREG(0x04)
21#define S3C2410_NFADDR S3C2410_NFREG(0x08)
22#define S3C2410_NFDATA S3C2410_NFREG(0x0C)
23#define S3C2410_NFSTAT S3C2410_NFREG(0x10)
24#define S3C2410_NFECC S3C2410_NFREG(0x14)
25
26#define S3C2440_NFCONT S3C2410_NFREG(0x04)
27#define S3C2440_NFCMD S3C2410_NFREG(0x08)
28#define S3C2440_NFADDR S3C2410_NFREG(0x0C)
29#define S3C2440_NFDATA S3C2410_NFREG(0x10)
30#define S3C2440_NFECCD0 S3C2410_NFREG(0x14)
31#define S3C2440_NFECCD1 S3C2410_NFREG(0x18)
32#define S3C2440_NFECCD S3C2410_NFREG(0x1C)
33#define S3C2440_NFSTAT S3C2410_NFREG(0x20)
34#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
35#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
36#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
37#define S3C2440_NFMECC1 S3C2410_NFREG(0x30)
38#define S3C2440_NFSECC S3C2410_NFREG(0x34)
39#define S3C2440_NFSBLK S3C2410_NFREG(0x38)
40#define S3C2440_NFEBLK S3C2410_NFREG(0x3C)
41
42#define S3C2412_NFSBLK S3C2410_NFREG(0x20)
43#define S3C2412_NFEBLK S3C2410_NFREG(0x24)
44#define S3C2412_NFSTAT S3C2410_NFREG(0x28)
45#define S3C2412_NFMECC_ERR0 S3C2410_NFREG(0x2C)
46#define S3C2412_NFMECC_ERR1 S3C2410_NFREG(0x30)
47#define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
48#define S3C2412_NFMECC1 S3C2410_NFREG(0x38)
49#define S3C2412_NFSECC S3C2410_NFREG(0x3C)
50
51#define S3C2410_NFCONF_EN (1<<15)
52#define S3C2410_NFCONF_512BYTE (1<<14)
53#define S3C2410_NFCONF_4STEP (1<<13)
54#define S3C2410_NFCONF_INITECC (1<<12)
55#define S3C2410_NFCONF_nFCE (1<<11)
56#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
57#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
58#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
59
60#define S3C2410_NFSTAT_BUSY (1<<0)
61
62#define S3C2440_NFCONF_BUSWIDTH_8 (0<<0)
63#define S3C2440_NFCONF_BUSWIDTH_16 (1<<0)
64#define S3C2440_NFCONF_ADVFLASH (1<<3)
65#define S3C2440_NFCONF_TACLS(x) ((x)<<12)
66#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
67#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
68
69#define S3C2440_NFCONT_LOCKTIGHT (1<<13)
70#define S3C2440_NFCONT_SOFTLOCK (1<<12)
71#define S3C2440_NFCONT_ILLEGALACC_EN (1<<10)
72#define S3C2440_NFCONT_RNBINT_EN (1<<9)
73#define S3C2440_NFCONT_RN_FALLING (1<<8)
74#define S3C2440_NFCONT_SPARE_ECCLOCK (1<<6)
75#define S3C2440_NFCONT_MAIN_ECCLOCK (1<<5)
76#define S3C2440_NFCONT_INITECC (1<<4)
77#define S3C2440_NFCONT_nFCE (1<<1)
78#define S3C2440_NFCONT_ENABLE (1<<0)
79
80#define S3C2440_NFSTAT_READY (1<<0)
81#define S3C2440_NFSTAT_nCE (1<<1)
82#define S3C2440_NFSTAT_RnB_CHANGE (1<<2)
83#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3)
84
85#define S3C2412_NFCONF_NANDBOOT (1<<31)
86#define S3C2412_NFCONF_ECCCLKCON (1<<30)
87#define S3C2412_NFCONF_ECC_MLC (1<<24)
88#define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */
89
90#define S3C2412_NFCONT_ECC4_DIRWR (1<<18)
91#define S3C2412_NFCONT_LOCKTIGHT (1<<17)
92#define S3C2412_NFCONT_SOFTLOCK (1<<16)
93#define S3C2412_NFCONT_ECC4_ENCINT (1<<13)
94#define S3C2412_NFCONT_ECC4_DECINT (1<<12)
95#define S3C2412_NFCONT_MAIN_ECC_LOCK (1<<7)
96#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
97#define S3C2412_NFCONT_nFCE1 (1<<2)
98#define S3C2412_NFCONT_nFCE0 (1<<1)
99
100#define S3C2412_NFSTAT_ECC_ENCDONE (1<<7)
101#define S3C2412_NFSTAT_ECC_DECDONE (1<<6)
102#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1<<5)
103#define S3C2412_NFSTAT_RnB_CHANGE (1<<4)
104#define S3C2412_NFSTAT_nFCE1 (1<<3)
105#define S3C2412_NFSTAT_nFCE0 (1<<2)
106#define S3C2412_NFSTAT_Res1 (1<<1)
107#define S3C2412_NFSTAT_READY (1<<0)
108
109#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)
110#define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7)
111#define S3C2412_NFECCERR_MERRDATA(x) (((x) >> 7) & 0x3ff)
112#define S3C2412_NFECCERR_MERRBIT(x) (((x) >> 4) & 0x7)
113#define S3C2412_NFECCERR_SPARE_ERR(x) (((x) >> 2) & 0x3)
114#define S3C2412_NFECCERR_MAIN_ERR(x) (((x) >> 2) & 0x3)
115#define S3C2412_NFECCERR_NONE (0)
116#define S3C2412_NFECCERR_1BIT (1)
117#define S3C2412_NFECCERR_MULTIBIT (2)
118#define S3C2412_NFECCERR_ECCAREA (3)
119
120
121
122#endif /* __ASM_ARM_REGS_NAND */
123
diff --git a/arch/arm/plat-s3c/include/plat/regs-rtc.h b/arch/arm/plat-s3c/include/plat/regs-rtc.h
new file mode 100644
index 000000000000..d5837cf8e402
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-rtc.h
@@ -0,0 +1,61 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Internal RTC register definition
11*/
12
13#ifndef __ASM_ARCH_REGS_RTC_H
14#define __ASM_ARCH_REGS_RTC_H __FILE__
15
16#define S3C2410_RTCREG(x) (x)
17
18#define S3C2410_RTCCON S3C2410_RTCREG(0x40)
19#define S3C2410_RTCCON_RTCEN (1<<0)
20#define S3C2410_RTCCON_CLKSEL (1<<1)
21#define S3C2410_RTCCON_CNTSEL (1<<2)
22#define S3C2410_RTCCON_CLKRST (1<<3)
23
24#define S3C2410_TICNT S3C2410_RTCREG(0x44)
25#define S3C2410_TICNT_ENABLE (1<<7)
26
27#define S3C2410_RTCALM S3C2410_RTCREG(0x50)
28#define S3C2410_RTCALM_ALMEN (1<<6)
29#define S3C2410_RTCALM_YEAREN (1<<5)
30#define S3C2410_RTCALM_MONEN (1<<4)
31#define S3C2410_RTCALM_DAYEN (1<<3)
32#define S3C2410_RTCALM_HOUREN (1<<2)
33#define S3C2410_RTCALM_MINEN (1<<1)
34#define S3C2410_RTCALM_SECEN (1<<0)
35
36#define S3C2410_RTCALM_ALL \
37 S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
38 S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
39 S3C2410_RTCALM_SECEN
40
41
42#define S3C2410_ALMSEC S3C2410_RTCREG(0x54)
43#define S3C2410_ALMMIN S3C2410_RTCREG(0x58)
44#define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c)
45
46#define S3C2410_ALMDATE S3C2410_RTCREG(0x60)
47#define S3C2410_ALMMON S3C2410_RTCREG(0x64)
48#define S3C2410_ALMYEAR S3C2410_RTCREG(0x68)
49
50#define S3C2410_RTCRST S3C2410_RTCREG(0x6c)
51
52#define S3C2410_RTCSEC S3C2410_RTCREG(0x70)
53#define S3C2410_RTCMIN S3C2410_RTCREG(0x74)
54#define S3C2410_RTCHOUR S3C2410_RTCREG(0x78)
55#define S3C2410_RTCDATE S3C2410_RTCREG(0x7c)
56#define S3C2410_RTCDAY S3C2410_RTCREG(0x80)
57#define S3C2410_RTCMON S3C2410_RTCREG(0x84)
58#define S3C2410_RTCYEAR S3C2410_RTCREG(0x88)
59
60
61#endif /* __ASM_ARCH_REGS_RTC_H */
diff --git a/arch/arm/plat-s3c/include/plat/regs-watchdog.h b/arch/arm/plat-s3c/include/plat/regs-watchdog.h
new file mode 100644
index 000000000000..4938492470f7
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-watchdog.h
@@ -0,0 +1,41 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Watchdog timer control
11*/
12
13
14#ifndef __ASM_ARCH_REGS_WATCHDOG_H
15#define __ASM_ARCH_REGS_WATCHDOG_H
16
17#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
18
19#define S3C2410_WTCON S3C_WDOGREG(0x00)
20#define S3C2410_WTDAT S3C_WDOGREG(0x04)
21#define S3C2410_WTCNT S3C_WDOGREG(0x08)
22
23/* the watchdog can either generate a reset pulse, or an
24 * interrupt.
25 */
26
27#define S3C2410_WTCON_RSTEN (0x01)
28#define S3C2410_WTCON_INTEN (1<<2)
29#define S3C2410_WTCON_ENABLE (1<<5)
30
31#define S3C2410_WTCON_DIV16 (0<<3)
32#define S3C2410_WTCON_DIV32 (1<<3)
33#define S3C2410_WTCON_DIV64 (2<<3)
34#define S3C2410_WTCON_DIV128 (3<<3)
35
36#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
37#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
38
39#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
40
41
diff --git a/arch/arm/plat-s3c/include/plat/uncompress.h b/arch/arm/plat-s3c/include/plat/uncompress.h
index 4df006b9cc10..8a8a927292e0 100644
--- a/arch/arm/plat-s3c/include/plat/uncompress.h
+++ b/arch/arm/plat-s3c/include/plat/uncompress.h
@@ -28,7 +28,7 @@ static void arch_detect_cpu(void);
28/* defines for UART registers */ 28/* defines for UART registers */
29 29
30#include <plat/regs-serial.h> 30#include <plat/regs-serial.h>
31#include <asm/plat-s3c/regs-watchdog.h> 31#include <plat/regs-watchdog.h>
32 32
33/* working in physical space... */ 33/* working in physical space... */
34#undef S3C2410_WDOGREG 34#undef S3C2410_WDOGREG
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 3098736c65d9..3d4837021ac7 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -38,7 +38,7 @@
38#include <mach/regs-gpio.h> 38#include <mach/regs-gpio.h>
39#include <mach/leds-gpio.h> 39#include <mach/leds-gpio.h>
40 40
41#include <asm/plat-s3c/nand.h> 41#include <plat/nand.h>
42 42
43#include <plat/common-smdk.h> 43#include <plat/common-smdk.h>
44#include <plat/devs.h> 44#include <plat/devs.h>
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index e93f8bf6d338..adf535aaf43a 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -29,11 +29,11 @@
29#include <asm/irq.h> 29#include <asm/irq.h>
30 30
31#include <plat/regs-serial.h> 31#include <plat/regs-serial.h>
32#include <asm/plat-s3c24xx/udc.h> 32#include <plat/udc.h>
33 33
34#include <plat/devs.h> 34#include <plat/devs.h>
35#include <plat/cpu.h> 35#include <plat/cpu.h>
36#include <asm/plat-s3c24xx/regs-spi.h> 36#include <plat/regs-spi.h>
37 37
38/* Serial port registrations */ 38/* Serial port registrations */
39 39
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 1baf941d1930..63bb22b973e3 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -31,9 +31,8 @@
31#include <asm/system.h> 31#include <asm/system.h>
32#include <asm/irq.h> 32#include <asm/irq.h>
33#include <mach/hardware.h> 33#include <mach/hardware.h>
34#include <asm/dma.h> 34#include <mach/dma.h>
35 35
36#include <asm/mach/dma.h>
37#include <mach/map.h> 36#include <mach/map.h>
38 37
39#include <plat/dma.h> 38#include <plat/dma.h>
@@ -804,7 +803,7 @@ EXPORT_SYMBOL(s3c2410_dma_request);
804 * allowed to go through. 803 * allowed to go through.
805*/ 804*/
806 805
807int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client) 806int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
808{ 807{
809 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 808 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
810 unsigned long flags; 809 unsigned long flags;
@@ -995,7 +994,7 @@ static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
995} 994}
996 995
997int 996int
998s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op) 997s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
999{ 998{
1000 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 999 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1001 1000
@@ -1043,7 +1042,7 @@ EXPORT_SYMBOL(s3c2410_dma_ctrl);
1043 * dcon: base value of the DCONx register 1042 * dcon: base value of the DCONx register
1044*/ 1043*/
1045 1044
1046int s3c2410_dma_config(dmach_t channel, 1045int s3c2410_dma_config(unsigned int channel,
1047 int xferunit, 1046 int xferunit,
1048 int dcon) 1047 int dcon)
1049{ 1048{
@@ -1092,7 +1091,7 @@ int s3c2410_dma_config(dmach_t channel,
1092 1091
1093EXPORT_SYMBOL(s3c2410_dma_config); 1092EXPORT_SYMBOL(s3c2410_dma_config);
1094 1093
1095int s3c2410_dma_setflags(dmach_t channel, unsigned int flags) 1094int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
1096{ 1095{
1097 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 1096 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1098 1097
@@ -1113,7 +1112,7 @@ EXPORT_SYMBOL(s3c2410_dma_setflags);
1113 * irq? 1112 * irq?
1114*/ 1113*/
1115 1114
1116int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn) 1115int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
1117{ 1116{
1118 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 1117 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1119 1118
@@ -1129,7 +1128,7 @@ int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn)
1129 1128
1130EXPORT_SYMBOL(s3c2410_dma_set_opfn); 1129EXPORT_SYMBOL(s3c2410_dma_set_opfn);
1131 1130
1132int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn) 1131int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
1133{ 1132{
1134 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 1133 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1135 1134
@@ -1219,7 +1218,7 @@ EXPORT_SYMBOL(s3c2410_dma_devconfig);
1219 * returns the current transfer points for the dma source and destination 1218 * returns the current transfer points for the dma source and destination
1220*/ 1219*/
1221 1220
1222int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst) 1221int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dst)
1223{ 1222{
1224 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 1223 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1225 1224
diff --git a/arch/arm/plat-s3c24xx/include/plat/mci.h b/arch/arm/plat-s3c24xx/include/plat/mci.h
new file mode 100644
index 000000000000..2d0852ac3b27
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/mci.h
@@ -0,0 +1,15 @@
1#ifndef _ARCH_MCI_H
2#define _ARCH_MCI_H
3
4struct s3c24xx_mci_pdata {
5 unsigned int wprotect_invert : 1;
6 unsigned int detect_invert : 1; /* set => detect active high. */
7
8 unsigned int gpio_detect;
9 unsigned int gpio_wprotect;
10 unsigned long ocr_avail;
11 void (*set_power)(unsigned char power_mode,
12 unsigned short vdd);
13};
14
15#endif /* _ARCH_NCI_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
new file mode 100644
index 000000000000..2b35479ee35c
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
@@ -0,0 +1,82 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-spi.h
2 *
3 * Copyright (c) 2004 Fetron GmbH
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S3C2410 SPI register definition
10*/
11
12#ifndef __ASM_ARCH_REGS_SPI_H
13#define __ASM_ARCH_REGS_SPI_H
14
15#define S3C2410_SPI1 (0x20)
16#define S3C2412_SPI1 (0x100)
17
18#define S3C2410_SPCON (0x00)
19
20#define S3C2412_SPCON_RXFIFO_RB2 (0<<14)
21#define S3C2412_SPCON_RXFIFO_RB4 (1<<14)
22#define S3C2412_SPCON_RXFIFO_RB12 (2<<14)
23#define S3C2412_SPCON_RXFIFO_RB14 (3<<14)
24#define S3C2412_SPCON_TXFIFO_RB2 (0<<12)
25#define S3C2412_SPCON_TXFIFO_RB4 (1<<12)
26#define S3C2412_SPCON_TXFIFO_RB12 (2<<12)
27#define S3C2412_SPCON_TXFIFO_RB14 (3<<12)
28#define S3C2412_SPCON_RXFIFO_RESET (1<<11) /* RxFIFO reset */
29#define S3C2412_SPCON_TXFIFO_RESET (1<<10) /* TxFIFO reset */
30#define S3C2412_SPCON_RXFIFO_EN (1<<9) /* RxFIFO Enable */
31#define S3C2412_SPCON_TXFIFO_EN (1<<8) /* TxFIFO Enable */
32
33#define S3C2412_SPCON_DIRC_RX (1<<7)
34
35#define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */
36#define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */
37#define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */
38#define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */
39#define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select
40 0: slave, 1: master */
41#define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */
42#define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */
43
44#define S3C2410_SPCON_CPHA_FMTB (1<<1) /* Clock Phase Select */
45#define S3C2410_SPCON_CPHA_FMTA (0<<1) /* Clock Phase Select */
46
47#define S3C2410_SPCON_TAGD (1<<0) /* Tx auto garbage data mode */
48
49
50#define S3C2410_SPSTA (0x04)
51
52#define S3C2412_SPSTA_RXFIFO_AE (1<<11)
53#define S3C2412_SPSTA_TXFIFO_AE (1<<10)
54#define S3C2412_SPSTA_RXFIFO_ERROR (1<<9)
55#define S3C2412_SPSTA_TXFIFO_ERROR (1<<8)
56#define S3C2412_SPSTA_RXFIFO_FIFO (1<<7)
57#define S3C2412_SPSTA_RXFIFO_EMPTY (1<<6)
58#define S3C2412_SPSTA_TXFIFO_NFULL (1<<5)
59#define S3C2412_SPSTA_TXFIFO_EMPTY (1<<4)
60
61#define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */
62#define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */
63#define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */
64#define S3C2412_SPSTA_READY_ORG (1<<3)
65
66#define S3C2410_SPPIN (0x08)
67
68#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */
69#define S3C2410_SPPIN_RESERVED (1<<1)
70#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */
71#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
72
73#define S3C2410_SPPRE (0x0C)
74#define S3C2410_SPTDAT (0x10)
75#define S3C2410_SPRDAT (0x14)
76
77#define S3C2412_TXFIFO (0x18)
78#define S3C2412_RXFIFO (0x18)
79#define S3C2412_SPFIC (0x24)
80
81
82#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-udc.h b/arch/arm/plat-s3c24xx/include/plat/regs-udc.h
new file mode 100644
index 000000000000..f0dd4a41b37b
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-udc.h
@@ -0,0 +1,153 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-udc.h
2 *
3 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
4 *
5 * This include file is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9*/
10
11#ifndef __ASM_ARCH_REGS_UDC_H
12#define __ASM_ARCH_REGS_UDC_H
13
14#define S3C2410_USBDREG(x) (x)
15
16#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
17#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
18#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)
19
20#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)
21#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)
22
23#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)
24
25#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)
26#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)
27
28#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)
29#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)
30#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)
31#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)
32#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)
33
34#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)
35#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)
36#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)
37#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)
38#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)
39#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)
40
41#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)
42#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)
43#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)
44#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)
45#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)
46#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)
47
48#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)
49#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)
50#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)
51#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)
52#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)
53#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)
54
55#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)
56#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)
57#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)
58#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)
59#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)
60#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)
61
62#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)
63
64/* indexed registers */
65
66#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)
67
68#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)
69
70#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)
71#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)
72
73#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)
74#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)
75#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
76#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
77
78#define S3C2410_UDC_FUNCADDR_UPDATE (1<<7)
79
80#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W
81#define S3C2410_UDC_PWR_RESET (1<<3) // R
82#define S3C2410_UDC_PWR_RESUME (1<<2) // R/W
83#define S3C2410_UDC_PWR_SUSPEND (1<<1) // R
84#define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W
85
86#define S3C2410_UDC_PWR_DEFAULT 0x00
87
88#define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only)
89#define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only)
90#define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only)
91#define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only)
92#define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only)
93
94#define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only)
95#define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only)
96#define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only)
97
98#define S3C2410_UDC_INTE_EP4 (1<<4) // R/W
99#define S3C2410_UDC_INTE_EP3 (1<<3) // R/W
100#define S3C2410_UDC_INTE_EP2 (1<<2) // R/W
101#define S3C2410_UDC_INTE_EP1 (1<<1) // R/W
102#define S3C2410_UDC_INTE_EP0 (1<<0) // R/W
103
104#define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W
105#define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W
106
107
108#define S3C2410_UDC_INDEX_EP0 (0x00)
109#define S3C2410_UDC_INDEX_EP1 (0x01) // ??
110#define S3C2410_UDC_INDEX_EP2 (0x02) // ??
111#define S3C2410_UDC_INDEX_EP3 (0x03) // ??
112#define S3C2410_UDC_INDEX_EP4 (0x04) // ??
113
114#define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W
115#define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only)
116#define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W
117#define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only)
118#define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only)
119#define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only)
120
121#define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W
122#define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W
123#define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W
124#define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W
125
126#define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W
127#define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only)
128#define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W
129#define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W
130#define S3C2410_UDC_OCSR1_DERROR (1<<3) // R
131#define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only)
132#define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only)
133
134#define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W
135#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W
136#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W
137
138#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0)
139#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1)
140#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2)
141#define S3C2410_UDC_EP0_CSR_DE (1<<3)
142#define S3C2410_UDC_EP0_CSR_SE (1<<4)
143#define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5)
144#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6)
145#define S3C2410_UDC_EP0_CSR_SSE (1<<7)
146
147#define S3C2410_UDC_MAXP_8 (1<<0)
148#define S3C2410_UDC_MAXP_16 (1<<1)
149#define S3C2410_UDC_MAXP_32 (1<<2)
150#define S3C2410_UDC_MAXP_64 (1<<3)
151
152
153#endif
diff --git a/arch/arm/plat-s3c24xx/include/plat/udc.h b/arch/arm/plat-s3c24xx/include/plat/udc.h
new file mode 100644
index 000000000000..546bb4008f49
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/udc.h
@@ -0,0 +1,36 @@
1/* arch/arm/mach-s3c2410/include/mach/udc.h
2 *
3 * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *
11 * Changelog:
12 * 14-Mar-2005 RTP Created file
13 * 02-Aug-2005 RTP File rename
14 * 07-Sep-2005 BJD Minor cleanups, changed cmd to enum
15 * 18-Jan-2007 HMW Add per-platform vbus_draw function
16*/
17
18#ifndef __ASM_ARM_ARCH_UDC_H
19#define __ASM_ARM_ARCH_UDC_H
20
21enum s3c2410_udc_cmd_e {
22 S3C2410_UDC_P_ENABLE = 1, /* Pull-up enable */
23 S3C2410_UDC_P_DISABLE = 2, /* Pull-up disable */
24 S3C2410_UDC_P_RESET = 3, /* UDC reset, in case of */
25};
26
27struct s3c2410_udc_mach_info {
28 void (*udc_command)(enum s3c2410_udc_cmd_e);
29 void (*vbus_draw)(unsigned int ma);
30 unsigned int vbus_pin;
31 unsigned char vbus_pin_inverted;
32};
33
34extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
35
36#endif /* __ASM_ARM_ARCH_UDC_H */
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 43aa2020f85c..fd23c0e9e698 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
12# 12#
13# http://www.arm.linux.org.uk/developer/machines/?action=new 13# http://www.arm.linux.org.uk/developer/machines/?action=new
14# 14#
15# Last update: Thu Sep 25 10:10:50 2008 15# Last update: Sun Nov 30 16:39:36 2008
16# 16#
17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number 17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
18# 18#
@@ -1380,7 +1380,7 @@ holon MACH_HOLON HOLON 1377
1380olip8 MACH_OLIP8 OLIP8 1378 1380olip8 MACH_OLIP8 OLIP8 1378
1381ghi270hg MACH_GHI270HG GHI270HG 1379 1381ghi270hg MACH_GHI270HG GHI270HG 1379
1382davinci_dm6467_evm MACH_DAVINCI_DM6467_EVM DAVINCI_DM6467_EVM 1380 1382davinci_dm6467_evm MACH_DAVINCI_DM6467_EVM DAVINCI_DM6467_EVM 1380
1383davinci_dm355_evm MACH_DAVINCI_DM350_EVM DAVINCI_DM350_EVM 1381 1383davinci_dm355_evm MACH_DAVINCI_DM355_EVM DAVINCI_DM355_EVM 1381
1384blackriver MACH_BLACKRIVER BLACKRIVER 1383 1384blackriver MACH_BLACKRIVER BLACKRIVER 1383
1385sandgate_wp MACH_SANDGATEWP SANDGATEWP 1384 1385sandgate_wp MACH_SANDGATEWP SANDGATEWP 1384
1386cdotbwsg MACH_CDOTBWSG CDOTBWSG 1385 1386cdotbwsg MACH_CDOTBWSG CDOTBWSG 1385
@@ -1771,7 +1771,7 @@ axs_ultrax MACH_AXS_ULTRAX AXS_ULTRAX 1779
1771at572d940deb MACH_AT572D940DEB AT572D940DEB 1780 1771at572d940deb MACH_AT572D940DEB AT572D940DEB 1780
1772davinci_da8xx_evm MACH_DAVINCI_DA8XX_EVM DAVINCI_DA8XX_EVM 1781 1772davinci_da8xx_evm MACH_DAVINCI_DA8XX_EVM DAVINCI_DA8XX_EVM 1781
1773ep9302 MACH_EP9302 EP9302 1782 1773ep9302 MACH_EP9302 EP9302 1782
1774at572d940hfeb MACH_AT572D940HFEB AT572D940HFEB 1783 1774at572d940hfek MACH_AT572D940HFEB AT572D940HFEB 1783
1775cybook3 MACH_CYBOOK3 CYBOOK3 1784 1775cybook3 MACH_CYBOOK3 CYBOOK3 1784
1776wdg002 MACH_WDG002 WDG002 1785 1776wdg002 MACH_WDG002 WDG002 1785
1777sg560adsl MACH_SG560ADSL SG560ADSL 1786 1777sg560adsl MACH_SG560ADSL SG560ADSL 1786
@@ -1899,3 +1899,98 @@ rut100 MACH_RUT100 RUT100 1908
1899asusp535 MACH_ASUSP535 ASUSP535 1909 1899asusp535 MACH_ASUSP535 ASUSP535 1909
1900htcraphael MACH_HTCRAPHAEL HTCRAPHAEL 1910 1900htcraphael MACH_HTCRAPHAEL HTCRAPHAEL 1910
1901sygdg1 MACH_SYGDG1 SYGDG1 1911 1901sygdg1 MACH_SYGDG1 SYGDG1 1911
1902sygdg2 MACH_SYGDG2 SYGDG2 1912
1903seoul MACH_SEOUL SEOUL 1913
1904salerno MACH_SALERNO SALERNO 1914
1905ucn_s3c64xx MACH_UCN_S3C64XX UCN_S3C64XX 1915
1906msm7201a MACH_MSM7201A MSM7201A 1916
1907lpr1 MACH_LPR1 LPR1 1917
1908armadillo500fx MACH_ARMADILLO500FX ARMADILLO500FX 1918
1909g3evm MACH_G3EVM G3EVM 1919
1910z3_dm355 MACH_Z3_DM355 Z3_DM355 1920
1911w90p910evb MACH_W90P910EVB W90P910EVB 1921
1912w90p920evb MACH_W90P920EVB W90P920EVB 1922
1913w90p950evb MACH_W90P950EVB W90P950EVB 1923
1914w90n960evb MACH_W90N960EVB W90N960EVB 1924
1915camhd MACH_CAMHD CAMHD 1925
1916mvc100 MACH_MVC100 MVC100 1926
1917electrum_200 MACH_ELECTRUM_200 ELECTRUM_200 1927
1918htcjade MACH_HTCJADE HTCJADE 1928
1919memphis MACH_MEMPHIS MEMPHIS 1929
1920imx27sbc MACH_IMX27SBC IMX27SBC 1930
1921lextar MACH_LEXTAR LEXTAR 1931
1922mv88f6281gtw_ge MACH_MV88F6281GTW_GE MV88F6281GTW_GE 1932
1923ncp MACH_NCP NCP 1933
1924z32an_series MACH_Z32AN Z32AN 1934
1925tmq_capd MACH_TMQ_CAPD TMQ_CAPD 1935
1926omap3_wl MACH_OMAP3_WL OMAP3_WL 1936
1927chumby MACH_CHUMBY CHUMBY 1937
1928atsarm9 MACH_ATSARM9 ATSARM9 1938
1929davinci_dm365_evm MACH_DAVINCI_DM365_EVM DAVINCI_DM365_EVM 1939
1930bahamas MACH_BAHAMAS BAHAMAS 1940
1931das MACH_DAS DAS 1941
1932minidas MACH_MINIDAS MINIDAS 1942
1933vk1000 MACH_VK1000 VK1000 1943
1934centro MACH_CENTRO CENTRO 1944
1935ctera_2bay MACH_CTERA_2BAY CTERA_2BAY 1945
1936edgeconnect MACH_EDGECONNECT EDGECONNECT 1946
1937nd27000 MACH_ND27000 ND27000 1947
1938cobra MACH_GEMALTO_COBRA GEMALTO_COBRA 1948
1939ingelabs_comet MACH_INGELABS_COMET INGELABS_COMET 1949
1940pollux_wiz MACH_POLLUX_WIZ POLLUX_WIZ 1950
1941blackstone MACH_BLACKSTONE BLACKSTONE 1951
1942topaz MACH_TOPAZ TOPAZ 1952
1943aixle MACH_AIXLE AIXLE 1953
1944mw998 MACH_MW998 MW998 1954
1945nokia_rx51 MACH_NOKIA_RX51 NOKIA_RX51 1955
1946vsc5605ev MACH_VSC5605EV VSC5605EV 1956
1947nt98700dk MACH_NT98700DK NT98700DK 1957
1948icontact MACH_ICONTACT ICONTACT 1958
1949swarco_frcpu MACH_SWARCO_FRCPU SWARCO_FRCPU 1959
1950swarco_scpu MACH_SWARCO_SCPU SWARCO_SCPU 1960
1951bbox_p16 MACH_BBOX_P16 BBOX_P16 1961
1952bstd MACH_BSTD BSTD 1962
1953sbc2440ii MACH_SBC2440II SBC2440II 1963
1954pcm034 MACH_PCM034 PCM034 1964
1955neso MACH_NESO NESO 1965
1956wlnx_9g20 MACH_WLNX_9G20 WLNX_9G20 1966
1957omap_zoom2 MACH_OMAP_ZOOM2 OMAP_ZOOM2 1967
1958totemnova MACH_TOTEMNOVA TOTEMNOVA 1968
1959c5000 MACH_C5000 C5000 1969
1960unipo_at91sam9263 MACH_UNIPO_AT91SAM9263 UNIPO_AT91SAM9263 1970
1961ethernut5 MACH_ETHERNUT5 ETHERNUT5 1971
1962arm11 MACH_ARM11 ARM11 1972
1963cpuat9260 MACH_CPUAT9260 CPUAT9260 1973
1964cpupxa255 MACH_CPUPXA255 CPUPXA255 1974
1965cpuimx27 MACH_CPUIMX27 CPUIMX27 1975
1966cheflux MACH_CHEFLUX CHEFLUX 1976
1967eb_cpux9k2 MACH_EB_CPUX9K2 EB_CPUX9K2 1977
1968opcotec MACH_OPCOTEC OPCOTEC 1978
1969yt MACH_YT YT 1979
1970motoq MACH_MOTOQ MOTOQ 1980
1971bsb1 MACH_BSB1 BSB1 1981
1972acs5k MACH_ACS5K ACS5K 1982
1973milan MACH_MILAN MILAN 1983
1974quartzv2 MACH_QUARTZV2 QUARTZV2 1984
1975rsvp MACH_RSVP RSVP 1985
1976rmp200 MACH_RMP200 RMP200 1986
1977snapper_9260 MACH_SNAPPER_9260 SNAPPER_9260 1987
1978dsm320 MACH_DSM320 DSM320 1988
1979adsgcm MACH_ADSGCM ADSGCM 1989
1980ase2_400 MACH_ASE2_400 ASE2_400 1990
1981pizza MACH_PIZZA PIZZA 1991
1982spot_ngpl MACH_SPOT_NGPL SPOT_NGPL 1992
1983armata MACH_ARMATA ARMATA 1993
1984exeda MACH_EXEDA EXEDA 1994
1985mx31sf005 MACH_MX31SF005 MX31SF005 1995
1986f5d8231_4_v2 MACH_F5D8231_4_V2 F5D8231_4_V2 1996
1987q2440 MACH_Q2440 Q2440 1997
1988qq2440 MACH_QQ2440 QQ2440 1998
1989mini2440 MACH_MINI2440 MINI2440 1999
1990colibri300 MACH_COLIBRI300 COLIBRI300 2000
1991jades MACH_JADES JADES 2001
1992spark MACH_SPARK SPARK 2002
1993benzina MACH_BENZINA BENZINA 2003
1994blaze MACH_BLAZE BLAZE 2004
1995linkstation_ls_hgl MACH_LINKSTATION_LS_HGL LINKSTATION_LS_HGL 2005
1996htcvenus MACH_HTCVENUS HTCVENUS 2006
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index a62dcf7098ba..3c73aafe3e01 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -101,9 +101,12 @@ ENTRY(vfp_support_entry)
101 VFPFSTMIA r4, r5 @ save the working registers 101 VFPFSTMIA r4, r5 @ save the working registers
102 VFPFMRX r5, FPSCR @ current status 102 VFPFMRX r5, FPSCR @ current status
103 tst r1, #FPEXC_EX @ is there additional state to save? 103 tst r1, #FPEXC_EX @ is there additional state to save?
104 VFPFMRX r6, FPINST, NE @ FPINST (only if FPEXC.EX is set) 104 beq 1f
105 tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read? 105 VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set)
106 VFPFMRX r8, FPINST2, NE @ FPINST2 if needed (and present) 106 tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
107 beq 1f
108 VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present)
1091:
107 stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 110 stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
108 @ and point r4 at the word at the 111 @ and point r4 at the word at the
109 @ start of the register dump 112 @ start of the register dump
@@ -117,9 +120,12 @@ no_old_VFP_process:
117 @ FPEXC is in a safe state 120 @ FPEXC is in a safe state
118 ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 121 ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
119 tst r1, #FPEXC_EX @ is there additional state to restore? 122 tst r1, #FPEXC_EX @ is there additional state to restore?
120 VFPFMXR FPINST, r6, NE @ restore FPINST (only if FPEXC.EX is set) 123 beq 1f
121 tstne r1, #FPEXC_FP2V @ is there an FPINST2 to write? 124 VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set)
122 VFPFMXR FPINST2, r8, NE @ FPINST2 if needed (and present) 125 tst r1, #FPEXC_FP2V @ is there an FPINST2 to write?
126 beq 1f
127 VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present)
1281:
123 VFPFMXR FPSCR, r5 @ restore status 129 VFPFMXR FPSCR, r5 @ restore status
124 130
125check_for_exception: 131check_for_exception:
@@ -175,9 +181,12 @@ ENTRY(vfp_save_state)
175 VFPFSTMIA r0, r2 @ save the working registers 181 VFPFSTMIA r0, r2 @ save the working registers
176 VFPFMRX r2, FPSCR @ current status 182 VFPFMRX r2, FPSCR @ current status
177 tst r1, #FPEXC_EX @ is there additional state to save? 183 tst r1, #FPEXC_EX @ is there additional state to save?
178 VFPFMRX r3, FPINST, NE @ FPINST (only if FPEXC.EX is set) 184 beq 1f
179 tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read? 185 VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set)
180 VFPFMRX r12, FPINST2, NE @ FPINST2 if needed (and present) 186 tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
187 beq 1f
188 VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present)
1891:
181 stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2 190 stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
182 mov pc, lr 191 mov pc, lr
183ENDPROC(vfp_save_state) 192ENDPROC(vfp_save_state)
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index c0d2c9bb952b..67ca340a7c85 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -371,6 +371,15 @@ static int __init vfp_init(void)
371 * in place; report VFP support to userspace. 371 * in place; report VFP support to userspace.
372 */ 372 */
373 elf_hwcap |= HWCAP_VFP; 373 elf_hwcap |= HWCAP_VFP;
374#ifdef CONFIG_NEON
375 /*
376 * Check for the presence of the Advanced SIMD
377 * load/store instructions, integer and single
378 * precision floating point operations.
379 */
380 if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
381 elf_hwcap |= HWCAP_NEON;
382#endif
374 } 383 }
375 return 0; 384 return 0;
376} 385}