aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig12
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/boot/compressed/head.S7
-rw-r--r--arch/arm/configs/at91rm9200dk_defconfig1
-rw-r--r--arch/arm/configs/at91rm9200ek_defconfig1
-rw-r--r--arch/arm/configs/ateb9200_defconfig1
-rw-r--r--arch/arm/configs/carmeva_defconfig1
-rw-r--r--arch/arm/configs/csb337_defconfig1
-rw-r--r--arch/arm/configs/csb637_defconfig1
-rw-r--r--arch/arm/configs/kafa_defconfig1
-rw-r--r--arch/arm/configs/kb9202_defconfig1
-rw-r--r--arch/arm/configs/omap_h2_1610_defconfig129
-rw-r--r--arch/arm/configs/onearm_defconfig1
-rw-r--r--arch/arm/configs/trizeps4_defconfig1579
-rw-r--r--arch/arm/kernel/Makefile2
-rw-r--r--arch/arm/kernel/asm-offsets.c3
-rw-r--r--arch/arm/kernel/entry-armv.S4
-rw-r--r--arch/arm/kernel/head.S5
-rw-r--r--arch/arm/kernel/iwmmxt-notifier.c64
-rw-r--r--arch/arm/kernel/iwmmxt.S27
-rw-r--r--arch/arm/kernel/process.c6
-rw-r--r--arch/arm/kernel/setup.c4
-rw-r--r--arch/arm/mach-at91rm9200/Kconfig82
-rw-r--r--arch/arm/mach-at91rm9200/Makefile13
-rw-r--r--arch/arm/mach-at91rm9200/at91rm9200.c (renamed from arch/arm/mach-at91rm9200/common.c)2
-rw-r--r--arch/arm/mach-at91rm9200/at91rm9200_time.c (renamed from arch/arm/mach-at91rm9200/time.c)2
-rw-r--r--arch/arm/mach-ep93xx/Kconfig12
-rw-r--r--arch/arm/mach-ep93xx/Makefile2
-rw-r--r--arch/arm/mach-ep93xx/edb9302.c62
-rw-r--r--arch/arm/mach-ep93xx/edb9315a.c62
-rw-r--r--arch/arm/mach-iop3xx/Kconfig15
-rw-r--r--arch/arm/mach-omap1/Kconfig7
-rw-r--r--arch/arm/mach-omap1/Makefile1
-rw-r--r--arch/arm/mach-omap1/board-ams-delta.c7
-rw-r--r--arch/arm/mach-omap1/board-fsample.c319
-rw-r--r--arch/arm/mach-omap1/board-innovator.c75
-rw-r--r--arch/arm/mach-omap1/board-osk.c147
-rw-r--r--arch/arm/mach-omap1/clock.c18
-rw-r--r--arch/arm/mach-omap1/pm.c7
-rw-r--r--arch/arm/mach-omap1/time.c2
-rw-r--r--arch/arm/mach-omap2/Kconfig1
-rw-r--r--arch/arm/mach-omap2/Makefile5
-rw-r--r--arch/arm/mach-omap2/clock.c37
-rw-r--r--arch/arm/mach-omap2/clock.h2
-rw-r--r--arch/arm/mach-omap2/devices.c46
-rw-r--r--arch/arm/mach-omap2/gpmc.c209
-rw-r--r--arch/arm/mach-omap2/io.c2
-rw-r--r--arch/arm/mach-omap2/mux.c38
-rw-r--r--arch/arm/mach-omap2/pm-domain.c300
-rw-r--r--arch/arm/mach-omap2/pm.c271
-rw-r--r--arch/arm/mach-omap2/timer-gp.c86
-rw-r--r--arch/arm/mach-pxa/Kconfig19
-rw-r--r--arch/arm/mach-pxa/Makefile2
-rw-r--r--arch/arm/mach-pxa/leds-trizeps4.c134
-rw-r--r--arch/arm/mach-pxa/leds.c2
-rw-r--r--arch/arm/mach-pxa/leds.h1
-rw-r--r--arch/arm/mach-pxa/lpd270.c126
-rw-r--r--arch/arm/mach-pxa/trizeps4.c471
-rw-r--r--arch/arm/mach-sa1100/cpu-sa1110.c131
-rw-r--r--arch/arm/mm/Kconfig4
-rw-r--r--arch/arm/mm/ioremap.c227
-rw-r--r--arch/arm/mm/mm-armv.c37
-rw-r--r--arch/arm/mm/proc-arm1020.S19
-rw-r--r--arch/arm/mm/proc-arm1020e.S39
-rw-r--r--arch/arm/mm/proc-arm1022.S39
-rw-r--r--arch/arm/mm/proc-arm1026.S39
-rw-r--r--arch/arm/mm/proc-arm6_7.S16
-rw-r--r--arch/arm/mm/proc-arm720.S23
-rw-r--r--arch/arm/mm/proc-arm920.S33
-rw-r--r--arch/arm/mm/proc-arm922.S33
-rw-r--r--arch/arm/mm/proc-arm925.S39
-rw-r--r--arch/arm/mm/proc-arm926.S36
-rw-r--r--arch/arm/mm/proc-macros.S10
-rw-r--r--arch/arm/mm/proc-sa110.S19
-rw-r--r--arch/arm/mm/proc-sa1100.S21
-rw-r--r--arch/arm/mm/proc-v6.S19
-rw-r--r--arch/arm/mm/proc-xsc3.S28
-rw-r--r--arch/arm/mm/proc-xscale.S63
-rw-r--r--arch/arm/plat-omap/Kconfig2
-rw-r--r--arch/arm/plat-omap/clock.c4
-rw-r--r--arch/arm/plat-omap/cpu-omap.c18
-rw-r--r--arch/arm/plat-omap/devices.c10
-rw-r--r--arch/arm/plat-omap/dma.c84
-rw-r--r--arch/arm/plat-omap/dmtimer.c428
-rw-r--r--arch/arm/plat-omap/gpio.c103
-rw-r--r--arch/arm/plat-omap/sram.c9
-rw-r--r--arch/arm/plat-omap/timer32k.c122
87 files changed, 5254 insertions, 841 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f123c7c9fc98..919d8b92aaa4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -121,11 +121,11 @@ config ARCH_VERSATILE
121 help 121 help
122 This enables support for ARM Ltd Versatile board. 122 This enables support for ARM Ltd Versatile board.
123 123
124config ARCH_AT91RM9200 124config ARCH_AT91
125 bool "Atmel AT91RM9200" 125 bool "Atmel AT91"
126 help 126 help
127 Say Y here if you intend to run this kernel on an Atmel 127 This enables support for systems based on the Atmel AT91RM9200
128 AT91RM9200-based board. 128 and AT91SAM9xxx processors.
129 129
130config ARCH_CLPS7500 130config ARCH_CLPS7500
131 bool "Cirrus CL-PS7500FE" 131 bool "Cirrus CL-PS7500FE"
@@ -547,7 +547,7 @@ config LEDS
547 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 547 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
548 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 548 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
549 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 549 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
550 ARCH_AT91RM9200 550 ARCH_AT91RM9200 || MACH_TRIZEPS4
551 help 551 help
552 If you say Y here, the LEDs on your machine will be used 552 If you say Y here, the LEDs on your machine will be used
553 to provide useful information about your current system status. 553 to provide useful information about your current system status.
@@ -678,7 +678,7 @@ config XIP_PHYS_ADDR
678 678
679endmenu 679endmenu
680 680
681if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP1) 681if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP)
682 682
683menu "CPU Frequency scaling" 683menu "CPU Frequency scaling"
684 684
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index a3bbaaf480b9..3345c6d0fd1e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -114,7 +114,7 @@ endif
114 machine-$(CONFIG_ARCH_H720X) := h720x 114 machine-$(CONFIG_ARCH_H720X) := h720x
115 machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 115 machine-$(CONFIG_ARCH_AAEC2000) := aaec2000
116 machine-$(CONFIG_ARCH_REALVIEW) := realview 116 machine-$(CONFIG_ARCH_REALVIEW) := realview
117 machine-$(CONFIG_ARCH_AT91RM9200) := at91rm9200 117 machine-$(CONFIG_ARCH_AT91) := at91rm9200
118 machine-$(CONFIG_ARCH_EP93XX) := ep93xx 118 machine-$(CONFIG_ARCH_EP93XX) := ep93xx
119 machine-$(CONFIG_ARCH_PNX4008) := pnx4008 119 machine-$(CONFIG_ARCH_PNX4008) := pnx4008
120 machine-$(CONFIG_ARCH_NETX) := netx 120 machine-$(CONFIG_ARCH_NETX) := netx
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index f7b5c6db30f5..14a9ff9c68df 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -447,8 +447,11 @@ __common_mmu_cache_on:
447 mov r1, #-1 447 mov r1, #-1
448 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer 448 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
449 mcr p15, 0, r1, c3, c0, 0 @ load domain access control 449 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
450 mcr p15, 0, r0, c1, c0, 0 @ load control register 450 b 1f
451 mov pc, lr 451 .align 5 @ cache line aligned
4521: mcr p15, 0, r0, c1, c0, 0 @ load control register
453 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
454 sub pc, lr, r0, lsr #32 @ properly flush pipeline
452 455
453/* 456/*
454 * All code following this line is relocatable. It is relocated by 457 * All code following this line is relocatable. It is relocated by
diff --git a/arch/arm/configs/at91rm9200dk_defconfig b/arch/arm/configs/at91rm9200dk_defconfig
index 9e1c1cceb735..4f3d8d37741e 100644
--- a/arch/arm/configs/at91rm9200dk_defconfig
+++ b/arch/arm/configs/at91rm9200dk_defconfig
@@ -103,6 +103,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
103# CONFIG_ARCH_IMX is not set 103# CONFIG_ARCH_IMX is not set
104# CONFIG_ARCH_H720X is not set 104# CONFIG_ARCH_H720X is not set
105# CONFIG_ARCH_AAEC2000 is not set 105# CONFIG_ARCH_AAEC2000 is not set
106CONFIG_ARCH_AT91=y
106CONFIG_ARCH_AT91RM9200=y 107CONFIG_ARCH_AT91RM9200=y
107 108
108# 109#
diff --git a/arch/arm/configs/at91rm9200ek_defconfig b/arch/arm/configs/at91rm9200ek_defconfig
index 6e0805a971d7..08b5dc38876f 100644
--- a/arch/arm/configs/at91rm9200ek_defconfig
+++ b/arch/arm/configs/at91rm9200ek_defconfig
@@ -103,6 +103,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
103# CONFIG_ARCH_IMX is not set 103# CONFIG_ARCH_IMX is not set
104# CONFIG_ARCH_H720X is not set 104# CONFIG_ARCH_H720X is not set
105# CONFIG_ARCH_AAEC2000 is not set 105# CONFIG_ARCH_AAEC2000 is not set
106CONFIG_ARCH_AT91=y
106CONFIG_ARCH_AT91RM9200=y 107CONFIG_ARCH_AT91RM9200=y
107 108
108# 109#
diff --git a/arch/arm/configs/ateb9200_defconfig b/arch/arm/configs/ateb9200_defconfig
index 69c39e098743..bee7813d040e 100644
--- a/arch/arm/configs/ateb9200_defconfig
+++ b/arch/arm/configs/ateb9200_defconfig
@@ -105,6 +105,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
105# CONFIG_ARCH_IMX is not set 105# CONFIG_ARCH_IMX is not set
106# CONFIG_ARCH_H720X is not set 106# CONFIG_ARCH_H720X is not set
107# CONFIG_ARCH_AAEC2000 is not set 107# CONFIG_ARCH_AAEC2000 is not set
108CONFIG_ARCH_AT91=y
108CONFIG_ARCH_AT91RM9200=y 109CONFIG_ARCH_AT91RM9200=y
109 110
110# 111#
diff --git a/arch/arm/configs/carmeva_defconfig b/arch/arm/configs/carmeva_defconfig
index 5ccd29a7c1fb..8a075c8ecc63 100644
--- a/arch/arm/configs/carmeva_defconfig
+++ b/arch/arm/configs/carmeva_defconfig
@@ -82,6 +82,7 @@ CONFIG_OBSOLETE_MODPARM=y
82# CONFIG_ARCH_VERSATILE is not set 82# CONFIG_ARCH_VERSATILE is not set
83# CONFIG_ARCH_IMX is not set 83# CONFIG_ARCH_IMX is not set
84# CONFIG_ARCH_H720X is not set 84# CONFIG_ARCH_H720X is not set
85CONFIG_ARCH_AT91=y
85CONFIG_ARCH_AT91RM9200=y 86CONFIG_ARCH_AT91RM9200=y
86 87
87# 88#
diff --git a/arch/arm/configs/csb337_defconfig b/arch/arm/configs/csb337_defconfig
index 94bd9932a402..3594155a8137 100644
--- a/arch/arm/configs/csb337_defconfig
+++ b/arch/arm/configs/csb337_defconfig
@@ -103,6 +103,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
103# CONFIG_ARCH_IMX is not set 103# CONFIG_ARCH_IMX is not set
104# CONFIG_ARCH_H720X is not set 104# CONFIG_ARCH_H720X is not set
105# CONFIG_ARCH_AAEC2000 is not set 105# CONFIG_ARCH_AAEC2000 is not set
106CONFIG_ARCH_AT91=y
106CONFIG_ARCH_AT91RM9200=y 107CONFIG_ARCH_AT91RM9200=y
107 108
108# 109#
diff --git a/arch/arm/configs/csb637_defconfig b/arch/arm/configs/csb637_defconfig
index 1519124c5501..640d70c1f066 100644
--- a/arch/arm/configs/csb637_defconfig
+++ b/arch/arm/configs/csb637_defconfig
@@ -103,6 +103,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
103# CONFIG_ARCH_IMX is not set 103# CONFIG_ARCH_IMX is not set
104# CONFIG_ARCH_H720X is not set 104# CONFIG_ARCH_H720X is not set
105# CONFIG_ARCH_AAEC2000 is not set 105# CONFIG_ARCH_AAEC2000 is not set
106CONFIG_ARCH_AT91=y
106CONFIG_ARCH_AT91RM9200=y 107CONFIG_ARCH_AT91RM9200=y
107 108
108# 109#
diff --git a/arch/arm/configs/kafa_defconfig b/arch/arm/configs/kafa_defconfig
index 51ded20e3f64..1db633e2c940 100644
--- a/arch/arm/configs/kafa_defconfig
+++ b/arch/arm/configs/kafa_defconfig
@@ -105,6 +105,7 @@ CONFIG_DEFAULT_IOSCHED="deadline"
105# CONFIG_ARCH_IMX is not set 105# CONFIG_ARCH_IMX is not set
106# CONFIG_ARCH_H720X is not set 106# CONFIG_ARCH_H720X is not set
107# CONFIG_ARCH_AAEC2000 is not set 107# CONFIG_ARCH_AAEC2000 is not set
108CONFIG_ARCH_AT91=y
108CONFIG_ARCH_AT91RM9200=y 109CONFIG_ARCH_AT91RM9200=y
109 110
110# 111#
diff --git a/arch/arm/configs/kb9202_defconfig b/arch/arm/configs/kb9202_defconfig
index fee4f566452e..45396e087196 100644
--- a/arch/arm/configs/kb9202_defconfig
+++ b/arch/arm/configs/kb9202_defconfig
@@ -80,6 +80,7 @@ CONFIG_KMOD=y
80# CONFIG_ARCH_IMX is not set 80# CONFIG_ARCH_IMX is not set
81# CONFIG_ARCH_H720X is not set 81# CONFIG_ARCH_H720X is not set
82# CONFIG_ARCH_AAEC2000 is not set 82# CONFIG_ARCH_AAEC2000 is not set
83CONFIG_ARCH_AT91=y
83CONFIG_ARCH_AT91RM9200=y 84CONFIG_ARCH_AT91RM9200=y
84 85
85# 86#
diff --git a/arch/arm/configs/omap_h2_1610_defconfig b/arch/arm/configs/omap_h2_1610_defconfig
index ee3ecbd9002d..05adb0b34e72 100644
--- a/arch/arm/configs/omap_h2_1610_defconfig
+++ b/arch/arm/configs/omap_h2_1610_defconfig
@@ -1,19 +1,20 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.14 3# Linux kernel version: 2.6.17
4# Wed Nov 9 18:53:40 2005 4# Thu Jun 29 15:25:18 2006
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_MMU=y 7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 10CONFIG_GENERIC_CALIBRATE_DELAY=y
11CONFIG_VECTORS_BASE=0xffff0000
12CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
11 13
12# 14#
13# Code maturity level options 15# Code maturity level options
14# 16#
15CONFIG_EXPERIMENTAL=y 17CONFIG_EXPERIMENTAL=y
16CONFIG_CLEAN_COMPILE=y
17CONFIG_BROKEN_ON_SMP=y 18CONFIG_BROKEN_ON_SMP=y
18CONFIG_LOCK_KERNEL=y 19CONFIG_LOCK_KERNEL=y
19CONFIG_INIT_ENV_ARG_LIMIT=32 20CONFIG_INIT_ENV_ARG_LIMIT=32
@@ -29,26 +30,26 @@ CONFIG_SYSVIPC=y
29# CONFIG_BSD_PROCESS_ACCT is not set 30# CONFIG_BSD_PROCESS_ACCT is not set
30CONFIG_SYSCTL=y 31CONFIG_SYSCTL=y
31# CONFIG_AUDIT is not set 32# CONFIG_AUDIT is not set
32# CONFIG_HOTPLUG is not set
33CONFIG_KOBJECT_UEVENT=y
34# CONFIG_IKCONFIG is not set 33# CONFIG_IKCONFIG is not set
34# CONFIG_RELAY is not set
35CONFIG_INITRAMFS_SOURCE="" 35CONFIG_INITRAMFS_SOURCE=""
36CONFIG_UID16=y
37CONFIG_CC_OPTIMIZE_FOR_SIZE=y
36# CONFIG_EMBEDDED is not set 38# CONFIG_EMBEDDED is not set
37CONFIG_KALLSYMS=y 39CONFIG_KALLSYMS=y
38# CONFIG_KALLSYMS_EXTRA_PASS is not set 40# CONFIG_KALLSYMS_EXTRA_PASS is not set
41CONFIG_HOTPLUG=y
39CONFIG_PRINTK=y 42CONFIG_PRINTK=y
40CONFIG_BUG=y 43CONFIG_BUG=y
44CONFIG_ELF_CORE=y
41CONFIG_BASE_FULL=y 45CONFIG_BASE_FULL=y
42CONFIG_FUTEX=y 46CONFIG_FUTEX=y
43CONFIG_EPOLL=y 47CONFIG_EPOLL=y
44CONFIG_CC_OPTIMIZE_FOR_SIZE=y
45CONFIG_SHMEM=y 48CONFIG_SHMEM=y
46CONFIG_CC_ALIGN_FUNCTIONS=0 49CONFIG_SLAB=y
47CONFIG_CC_ALIGN_LABELS=0
48CONFIG_CC_ALIGN_LOOPS=0
49CONFIG_CC_ALIGN_JUMPS=0
50# CONFIG_TINY_SHMEM is not set 50# CONFIG_TINY_SHMEM is not set
51CONFIG_BASE_SMALL=0 51CONFIG_BASE_SMALL=0
52# CONFIG_SLOB is not set
52 53
53# 54#
54# Loadable module support 55# Loadable module support
@@ -56,7 +57,6 @@ CONFIG_BASE_SMALL=0
56CONFIG_MODULES=y 57CONFIG_MODULES=y
57CONFIG_MODULE_UNLOAD=y 58CONFIG_MODULE_UNLOAD=y
58# CONFIG_MODULE_FORCE_UNLOAD is not set 59# CONFIG_MODULE_FORCE_UNLOAD is not set
59CONFIG_OBSOLETE_MODPARM=y
60# CONFIG_MODVERSIONS is not set 60# CONFIG_MODVERSIONS is not set
61# CONFIG_MODULE_SRCVERSION_ALL is not set 61# CONFIG_MODULE_SRCVERSION_ALL is not set
62# CONFIG_KMOD is not set 62# CONFIG_KMOD is not set
@@ -64,6 +64,7 @@ CONFIG_OBSOLETE_MODPARM=y
64# 64#
65# Block layer 65# Block layer
66# 66#
67# CONFIG_BLK_DEV_IO_TRACE is not set
67 68
68# 69#
69# IO Schedulers 70# IO Schedulers
@@ -81,16 +82,26 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
81# 82#
82# System Type 83# System Type
83# 84#
85# CONFIG_ARCH_AAEC2000 is not set
86# CONFIG_ARCH_INTEGRATOR is not set
87# CONFIG_ARCH_REALVIEW is not set
88# CONFIG_ARCH_VERSATILE is not set
89# CONFIG_ARCH_AT91RM9200 is not set
84# CONFIG_ARCH_CLPS7500 is not set 90# CONFIG_ARCH_CLPS7500 is not set
85# CONFIG_ARCH_CLPS711X is not set 91# CONFIG_ARCH_CLPS711X is not set
86# CONFIG_ARCH_CO285 is not set 92# CONFIG_ARCH_CO285 is not set
87# CONFIG_ARCH_EBSA110 is not set 93# CONFIG_ARCH_EBSA110 is not set
94# CONFIG_ARCH_EP93XX is not set
88# CONFIG_ARCH_FOOTBRIDGE is not set 95# CONFIG_ARCH_FOOTBRIDGE is not set
89# CONFIG_ARCH_INTEGRATOR is not set 96# CONFIG_ARCH_NETX is not set
97# CONFIG_ARCH_H720X is not set
98# CONFIG_ARCH_IMX is not set
90# CONFIG_ARCH_IOP3XX is not set 99# CONFIG_ARCH_IOP3XX is not set
91# CONFIG_ARCH_IXP4XX is not set 100# CONFIG_ARCH_IXP4XX is not set
92# CONFIG_ARCH_IXP2000 is not set 101# CONFIG_ARCH_IXP2000 is not set
102# CONFIG_ARCH_IXP23XX is not set
93# CONFIG_ARCH_L7200 is not set 103# CONFIG_ARCH_L7200 is not set
104# CONFIG_ARCH_PNX4008 is not set
94# CONFIG_ARCH_PXA is not set 105# CONFIG_ARCH_PXA is not set
95# CONFIG_ARCH_RPC is not set 106# CONFIG_ARCH_RPC is not set
96# CONFIG_ARCH_SA1100 is not set 107# CONFIG_ARCH_SA1100 is not set
@@ -98,11 +109,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
98# CONFIG_ARCH_SHARK is not set 109# CONFIG_ARCH_SHARK is not set
99# CONFIG_ARCH_LH7A40X is not set 110# CONFIG_ARCH_LH7A40X is not set
100CONFIG_ARCH_OMAP=y 111CONFIG_ARCH_OMAP=y
101# CONFIG_ARCH_VERSATILE is not set
102# CONFIG_ARCH_REALVIEW is not set
103# CONFIG_ARCH_IMX is not set
104# CONFIG_ARCH_H720X is not set
105# CONFIG_ARCH_AAEC2000 is not set
106 112
107# 113#
108# TI OMAP Implementations 114# TI OMAP Implementations
@@ -141,6 +147,7 @@ CONFIG_ARCH_OMAP16XX=y
141CONFIG_MACH_OMAP_H2=y 147CONFIG_MACH_OMAP_H2=y
142# CONFIG_MACH_OMAP_H3 is not set 148# CONFIG_MACH_OMAP_H3 is not set
143# CONFIG_MACH_OMAP_OSK is not set 149# CONFIG_MACH_OMAP_OSK is not set
150# CONFIG_MACH_NOKIA770 is not set
144# CONFIG_MACH_OMAP_GENERIC is not set 151# CONFIG_MACH_OMAP_GENERIC is not set
145 152
146# 153#
@@ -177,7 +184,6 @@ CONFIG_ARM_THUMB=y
177# 184#
178# Bus support 185# Bus support
179# 186#
180CONFIG_ISA_DMA_API=y
181 187
182# 188#
183# PCCARD (PCMCIA/CardBus) support 189# PCCARD (PCMCIA/CardBus) support
@@ -189,6 +195,8 @@ CONFIG_ISA_DMA_API=y
189# 195#
190CONFIG_PREEMPT=y 196CONFIG_PREEMPT=y
191CONFIG_NO_IDLE_HZ=y 197CONFIG_NO_IDLE_HZ=y
198CONFIG_HZ=128
199# CONFIG_AEABI is not set
192# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 200# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
193CONFIG_SELECT_MEMORY_MODEL=y 201CONFIG_SELECT_MEMORY_MODEL=y
194CONFIG_FLATMEM_MANUAL=y 202CONFIG_FLATMEM_MANUAL=y
@@ -249,6 +257,8 @@ CONFIG_BINFMT_AOUT=y
249# Power management options 257# Power management options
250# 258#
251CONFIG_PM=y 259CONFIG_PM=y
260CONFIG_PM_LEGACY=y
261# CONFIG_PM_DEBUG is not set
252# CONFIG_APM is not set 262# CONFIG_APM is not set
253 263
254# 264#
@@ -259,9 +269,12 @@ CONFIG_NET=y
259# 269#
260# Networking options 270# Networking options
261# 271#
272# CONFIG_NETDEBUG is not set
262CONFIG_PACKET=y 273CONFIG_PACKET=y
263# CONFIG_PACKET_MMAP is not set 274# CONFIG_PACKET_MMAP is not set
264CONFIG_UNIX=y 275CONFIG_UNIX=y
276CONFIG_XFRM=y
277# CONFIG_XFRM_USER is not set
265# CONFIG_NET_KEY is not set 278# CONFIG_NET_KEY is not set
266CONFIG_INET=y 279CONFIG_INET=y
267# CONFIG_IP_MULTICAST is not set 280# CONFIG_IP_MULTICAST is not set
@@ -278,12 +291,18 @@ CONFIG_IP_PNP_BOOTP=y
278# CONFIG_INET_AH is not set 291# CONFIG_INET_AH is not set
279# CONFIG_INET_ESP is not set 292# CONFIG_INET_ESP is not set
280# CONFIG_INET_IPCOMP is not set 293# CONFIG_INET_IPCOMP is not set
294# CONFIG_INET_XFRM_TUNNEL is not set
281# CONFIG_INET_TUNNEL is not set 295# CONFIG_INET_TUNNEL is not set
296CONFIG_INET_XFRM_MODE_TRANSPORT=y
297CONFIG_INET_XFRM_MODE_TUNNEL=y
282CONFIG_INET_DIAG=y 298CONFIG_INET_DIAG=y
283CONFIG_INET_TCP_DIAG=y 299CONFIG_INET_TCP_DIAG=y
284# CONFIG_TCP_CONG_ADVANCED is not set 300# CONFIG_TCP_CONG_ADVANCED is not set
285CONFIG_TCP_CONG_BIC=y 301CONFIG_TCP_CONG_BIC=y
286# CONFIG_IPV6 is not set 302# CONFIG_IPV6 is not set
303# CONFIG_INET6_XFRM_TUNNEL is not set
304# CONFIG_INET6_TUNNEL is not set
305# CONFIG_NETWORK_SECMARK is not set
287# CONFIG_NETFILTER is not set 306# CONFIG_NETFILTER is not set
288 307
289# 308#
@@ -295,6 +314,11 @@ CONFIG_TCP_CONG_BIC=y
295# SCTP Configuration (EXPERIMENTAL) 314# SCTP Configuration (EXPERIMENTAL)
296# 315#
297# CONFIG_IP_SCTP is not set 316# CONFIG_IP_SCTP is not set
317
318#
319# TIPC Configuration (EXPERIMENTAL)
320#
321# CONFIG_TIPC is not set
298# CONFIG_ATM is not set 322# CONFIG_ATM is not set
299# CONFIG_BRIDGE is not set 323# CONFIG_BRIDGE is not set
300# CONFIG_VLAN_8021Q is not set 324# CONFIG_VLAN_8021Q is not set
@@ -312,7 +336,6 @@ CONFIG_TCP_CONG_BIC=y
312# QoS and/or fair queueing 336# QoS and/or fair queueing
313# 337#
314# CONFIG_NET_SCHED is not set 338# CONFIG_NET_SCHED is not set
315# CONFIG_NET_CLS_ROUTE is not set
316 339
317# 340#
318# Network testing 341# Network testing
@@ -333,6 +356,12 @@ CONFIG_TCP_CONG_BIC=y
333CONFIG_STANDALONE=y 356CONFIG_STANDALONE=y
334CONFIG_PREVENT_FIRMWARE_BUILD=y 357CONFIG_PREVENT_FIRMWARE_BUILD=y
335# CONFIG_FW_LOADER is not set 358# CONFIG_FW_LOADER is not set
359# CONFIG_SYS_HYPERVISOR is not set
360
361#
362# Connector - unified userspace <-> kernelspace linker
363#
364# CONFIG_CONNECTOR is not set
336 365
337# 366#
338# Memory Technology Devices (MTD) 367# Memory Technology Devices (MTD)
@@ -526,6 +555,7 @@ CONFIG_SERIO_SERPORT=y
526CONFIG_VT=y 555CONFIG_VT=y
527CONFIG_VT_CONSOLE=y 556CONFIG_VT_CONSOLE=y
528CONFIG_HW_CONSOLE=y 557CONFIG_HW_CONSOLE=y
558# CONFIG_VT_HW_CONSOLE_BINDING is not set
529# CONFIG_SERIAL_NONSTANDARD is not set 559# CONFIG_SERIAL_NONSTANDARD is not set
530 560
531# 561#
@@ -534,6 +564,7 @@ CONFIG_HW_CONSOLE=y
534CONFIG_SERIAL_8250=y 564CONFIG_SERIAL_8250=y
535CONFIG_SERIAL_8250_CONSOLE=y 565CONFIG_SERIAL_8250_CONSOLE=y
536CONFIG_SERIAL_8250_NR_UARTS=4 566CONFIG_SERIAL_8250_NR_UARTS=4
567CONFIG_SERIAL_8250_RUNTIME_UARTS=4
537# CONFIG_SERIAL_8250_EXTENDED is not set 568# CONFIG_SERIAL_8250_EXTENDED is not set
538 569
539# 570#
@@ -559,8 +590,8 @@ CONFIG_WATCHDOG_NOWAYOUT=y
559# Watchdog Device Drivers 590# Watchdog Device Drivers
560# 591#
561# CONFIG_SOFT_WATCHDOG is not set 592# CONFIG_SOFT_WATCHDOG is not set
593# CONFIG_HW_RANDOM is not set
562# CONFIG_NVRAM is not set 594# CONFIG_NVRAM is not set
563# CONFIG_RTC is not set
564# CONFIG_DTLK is not set 595# CONFIG_DTLK is not set
565# CONFIG_R3964 is not set 596# CONFIG_R3964 is not set
566 597
@@ -572,6 +603,7 @@ CONFIG_WATCHDOG_NOWAYOUT=y
572# 603#
573# TPM devices 604# TPM devices
574# 605#
606# CONFIG_TCG_TPM is not set
575# CONFIG_TELCLOCK is not set 607# CONFIG_TELCLOCK is not set
576 608
577# 609#
@@ -580,10 +612,22 @@ CONFIG_WATCHDOG_NOWAYOUT=y
580# CONFIG_I2C is not set 612# CONFIG_I2C is not set
581 613
582# 614#
615# SPI support
616#
617# CONFIG_SPI is not set
618# CONFIG_SPI_MASTER is not set
619
620#
621# Dallas's 1-wire bus
622#
623
624#
583# Hardware Monitoring support 625# Hardware Monitoring support
584# 626#
585CONFIG_HWMON=y 627CONFIG_HWMON=y
586# CONFIG_HWMON_VID is not set 628# CONFIG_HWMON_VID is not set
629# CONFIG_SENSORS_ABITUGURU is not set
630# CONFIG_SENSORS_F71805F is not set
587# CONFIG_HWMON_DEBUG_CHIP is not set 631# CONFIG_HWMON_DEBUG_CHIP is not set
588 632
589# 633#
@@ -591,13 +635,23 @@ CONFIG_HWMON=y
591# 635#
592 636
593# 637#
594# Multimedia Capabilities Port drivers 638# LED devices
639#
640# CONFIG_NEW_LEDS is not set
641
642#
643# LED drivers
644#
645
646#
647# LED Triggers
595# 648#
596 649
597# 650#
598# Multimedia devices 651# Multimedia devices
599# 652#
600# CONFIG_VIDEO_DEV is not set 653# CONFIG_VIDEO_DEV is not set
654CONFIG_VIDEO_V4L2=y
601 655
602# 656#
603# Digital Video Broadcasting Devices 657# Digital Video Broadcasting Devices
@@ -607,11 +661,13 @@ CONFIG_HWMON=y
607# 661#
608# Graphics support 662# Graphics support
609# 663#
664CONFIG_FIRMWARE_EDID=y
610CONFIG_FB=y 665CONFIG_FB=y
611# CONFIG_FB_CFB_FILLRECT is not set 666# CONFIG_FB_CFB_FILLRECT is not set
612# CONFIG_FB_CFB_COPYAREA is not set 667# CONFIG_FB_CFB_COPYAREA is not set
613# CONFIG_FB_CFB_IMAGEBLIT is not set 668# CONFIG_FB_CFB_IMAGEBLIT is not set
614# CONFIG_FB_MACMODES is not set 669# CONFIG_FB_MACMODES is not set
670# CONFIG_FB_BACKLIGHT is not set
615CONFIG_FB_MODE_HELPERS=y 671CONFIG_FB_MODE_HELPERS=y
616# CONFIG_FB_TILEBLITTING is not set 672# CONFIG_FB_TILEBLITTING is not set
617# CONFIG_FB_S1D13XXX is not set 673# CONFIG_FB_S1D13XXX is not set
@@ -635,7 +691,6 @@ CONFIG_FONT_8x16=y
635# CONFIG_FONT_SUN8x16 is not set 691# CONFIG_FONT_SUN8x16 is not set
636# CONFIG_FONT_SUN12x22 is not set 692# CONFIG_FONT_SUN12x22 is not set
637# CONFIG_FONT_10x18 is not set 693# CONFIG_FONT_10x18 is not set
638# CONFIG_FONT_RL is not set
639 694
640# 695#
641# Logo configuration 696# Logo configuration
@@ -660,16 +715,15 @@ CONFIG_SOUND=y
660# Open Sound System 715# Open Sound System
661# 716#
662CONFIG_SOUND_PRIME=y 717CONFIG_SOUND_PRIME=y
663# CONFIG_OBSOLETE_OSS_DRIVER is not set
664# CONFIG_SOUND_MSNDCLAS is not set 718# CONFIG_SOUND_MSNDCLAS is not set
665# CONFIG_SOUND_MSNDPIN is not set 719# CONFIG_SOUND_MSNDPIN is not set
666# CONFIG_SOUND_OSS is not set
667 720
668# 721#
669# USB support 722# USB support
670# 723#
671CONFIG_USB_ARCH_HAS_HCD=y 724CONFIG_USB_ARCH_HAS_HCD=y
672CONFIG_USB_ARCH_HAS_OHCI=y 725CONFIG_USB_ARCH_HAS_OHCI=y
726# CONFIG_USB_ARCH_HAS_EHCI is not set
673# CONFIG_USB is not set 727# CONFIG_USB is not set
674 728
675# 729#
@@ -680,17 +734,6 @@ CONFIG_USB_ARCH_HAS_OHCI=y
680# USB Gadget Support 734# USB Gadget Support
681# 735#
682# CONFIG_USB_GADGET is not set 736# CONFIG_USB_GADGET is not set
683# CONFIG_USB_GADGET_NET2280 is not set
684# CONFIG_USB_GADGET_PXA2XX is not set
685# CONFIG_USB_GADGET_GOKU is not set
686# CONFIG_USB_GADGET_LH7A40X is not set
687# CONFIG_USB_GADGET_OMAP is not set
688# CONFIG_USB_GADGET_DUMMY_HCD is not set
689# CONFIG_USB_ZERO is not set
690# CONFIG_USB_ETH is not set
691# CONFIG_USB_GADGETFS is not set
692# CONFIG_USB_FILE_STORAGE is not set
693# CONFIG_USB_G_SERIAL is not set
694 737
695# 738#
696# MMC/SD Card support 739# MMC/SD Card support
@@ -698,20 +741,27 @@ CONFIG_USB_ARCH_HAS_OHCI=y
698# CONFIG_MMC is not set 741# CONFIG_MMC is not set
699 742
700# 743#
744# Real Time Clock
745#
746CONFIG_RTC_LIB=y
747# CONFIG_RTC_CLASS is not set
748
749#
701# File systems 750# File systems
702# 751#
703CONFIG_EXT2_FS=y 752CONFIG_EXT2_FS=y
704# CONFIG_EXT2_FS_XATTR is not set 753# CONFIG_EXT2_FS_XATTR is not set
705# CONFIG_EXT2_FS_XIP is not set 754# CONFIG_EXT2_FS_XIP is not set
706# CONFIG_EXT3_FS is not set 755# CONFIG_EXT3_FS is not set
707# CONFIG_JBD is not set
708# CONFIG_REISERFS_FS is not set 756# CONFIG_REISERFS_FS is not set
709# CONFIG_JFS_FS is not set 757# CONFIG_JFS_FS is not set
710# CONFIG_FS_POSIX_ACL is not set 758# CONFIG_FS_POSIX_ACL is not set
711# CONFIG_XFS_FS is not set 759# CONFIG_XFS_FS is not set
760# CONFIG_OCFS2_FS is not set
712# CONFIG_MINIX_FS is not set 761# CONFIG_MINIX_FS is not set
713CONFIG_ROMFS_FS=y 762CONFIG_ROMFS_FS=y
714CONFIG_INOTIFY=y 763CONFIG_INOTIFY=y
764CONFIG_INOTIFY_USER=y
715# CONFIG_QUOTA is not set 765# CONFIG_QUOTA is not set
716CONFIG_DNOTIFY=y 766CONFIG_DNOTIFY=y
717# CONFIG_AUTOFS_FS is not set 767# CONFIG_AUTOFS_FS is not set
@@ -741,7 +791,7 @@ CONFIG_SYSFS=y
741# CONFIG_TMPFS is not set 791# CONFIG_TMPFS is not set
742# CONFIG_HUGETLB_PAGE is not set 792# CONFIG_HUGETLB_PAGE is not set
743CONFIG_RAMFS=y 793CONFIG_RAMFS=y
744# CONFIG_RELAYFS_FS is not set 794# CONFIG_CONFIGFS_FS is not set
745 795
746# 796#
747# Miscellaneous filesystems 797# Miscellaneous filesystems
@@ -843,10 +893,13 @@ CONFIG_NLS_DEFAULT="iso8859-1"
843# Kernel hacking 893# Kernel hacking
844# 894#
845# CONFIG_PRINTK_TIME is not set 895# CONFIG_PRINTK_TIME is not set
896# CONFIG_MAGIC_SYSRQ is not set
846# CONFIG_DEBUG_KERNEL is not set 897# CONFIG_DEBUG_KERNEL is not set
847CONFIG_LOG_BUF_SHIFT=14 898CONFIG_LOG_BUF_SHIFT=14
848CONFIG_DEBUG_BUGVERBOSE=y 899CONFIG_DEBUG_BUGVERBOSE=y
900# CONFIG_DEBUG_FS is not set
849CONFIG_FRAME_POINTER=y 901CONFIG_FRAME_POINTER=y
902# CONFIG_UNWIND_INFO is not set
850# CONFIG_DEBUG_USER is not set 903# CONFIG_DEBUG_USER is not set
851 904
852# 905#
diff --git a/arch/arm/configs/onearm_defconfig b/arch/arm/configs/onearm_defconfig
index 5401c01caefe..2b4a63be03f7 100644
--- a/arch/arm/configs/onearm_defconfig
+++ b/arch/arm/configs/onearm_defconfig
@@ -85,6 +85,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
85# CONFIG_ARCH_INTEGRATOR is not set 85# CONFIG_ARCH_INTEGRATOR is not set
86# CONFIG_ARCH_REALVIEW is not set 86# CONFIG_ARCH_REALVIEW is not set
87# CONFIG_ARCH_VERSATILE is not set 87# CONFIG_ARCH_VERSATILE is not set
88CONFIG_ARCH_AT91=y
88CONFIG_ARCH_AT91RM9200=y 89CONFIG_ARCH_AT91RM9200=y
89# CONFIG_ARCH_CLPS7500 is not set 90# CONFIG_ARCH_CLPS7500 is not set
90# CONFIG_ARCH_CLPS711X is not set 91# CONFIG_ARCH_CLPS711X is not set
diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig
new file mode 100644
index 000000000000..a6698dc4f6b9
--- /dev/null
+++ b/arch/arm/configs/trizeps4_defconfig
@@ -0,0 +1,1579 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.17
4# Sat Jun 24 22:45:14 2006
5#
6CONFIG_ARM=y
7CONFIG_MMU=y
8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y
11CONFIG_ARCH_MTD_XIP=y
12CONFIG_VECTORS_BASE=0xffff0000
13
14#
15# Code maturity level options
16#
17CONFIG_EXPERIMENTAL=y
18CONFIG_BROKEN_ON_SMP=y
19CONFIG_LOCK_KERNEL=y
20CONFIG_INIT_ENV_ARG_LIMIT=32
21
22#
23# General setup
24#
25CONFIG_LOCALVERSION=""
26CONFIG_LOCALVERSION_AUTO=y
27CONFIG_SWAP=y
28CONFIG_SYSVIPC=y
29CONFIG_POSIX_MQUEUE=y
30CONFIG_BSD_PROCESS_ACCT=y
31CONFIG_BSD_PROCESS_ACCT_V3=y
32CONFIG_SYSCTL=y
33CONFIG_AUDIT=y
34CONFIG_IKCONFIG=y
35CONFIG_IKCONFIG_PROC=y
36# CONFIG_RELAY is not set
37CONFIG_INITRAMFS_SOURCE=""
38CONFIG_UID16=y
39CONFIG_CC_OPTIMIZE_FOR_SIZE=y
40CONFIG_EMBEDDED=y
41CONFIG_KALLSYMS=y
42CONFIG_KALLSYMS_EXTRA_PASS=y
43CONFIG_HOTPLUG=y
44CONFIG_PRINTK=y
45CONFIG_BUG=y
46CONFIG_ELF_CORE=y
47CONFIG_BASE_FULL=y
48CONFIG_FUTEX=y
49CONFIG_EPOLL=y
50CONFIG_SHMEM=y
51CONFIG_SLAB=y
52# CONFIG_TINY_SHMEM is not set
53CONFIG_BASE_SMALL=0
54# CONFIG_SLOB is not set
55CONFIG_OBSOLETE_INTERMODULE=y
56
57#
58# Loadable module support
59#
60CONFIG_MODULES=y
61CONFIG_MODULE_UNLOAD=y
62CONFIG_MODULE_FORCE_UNLOAD=y
63# CONFIG_MODVERSIONS is not set
64CONFIG_MODULE_SRCVERSION_ALL=y
65CONFIG_KMOD=y
66
67#
68# Block layer
69#
70# CONFIG_BLK_DEV_IO_TRACE is not set
71
72#
73# IO Schedulers
74#
75CONFIG_IOSCHED_NOOP=y
76CONFIG_IOSCHED_AS=y
77CONFIG_IOSCHED_DEADLINE=y
78CONFIG_IOSCHED_CFQ=y
79CONFIG_DEFAULT_AS=y
80# CONFIG_DEFAULT_DEADLINE is not set
81# CONFIG_DEFAULT_CFQ is not set
82# CONFIG_DEFAULT_NOOP is not set
83CONFIG_DEFAULT_IOSCHED="anticipatory"
84
85#
86# System Type
87#
88# CONFIG_ARCH_CLPS7500 is not set
89# CONFIG_ARCH_CLPS711X is not set
90# CONFIG_ARCH_CO285 is not set
91# CONFIG_ARCH_EBSA110 is not set
92# CONFIG_ARCH_EP93XX is not set
93# CONFIG_ARCH_FOOTBRIDGE is not set
94# CONFIG_ARCH_INTEGRATOR is not set
95# CONFIG_ARCH_IOP3XX is not set
96# CONFIG_ARCH_IXP4XX is not set
97# CONFIG_ARCH_IXP2000 is not set
98# CONFIG_ARCH_IXP23XX is not set
99# CONFIG_ARCH_L7200 is not set
100CONFIG_ARCH_PXA=y
101# CONFIG_ARCH_RPC is not set
102# CONFIG_ARCH_SA1100 is not set
103# CONFIG_ARCH_S3C2410 is not set
104# CONFIG_ARCH_SHARK is not set
105# CONFIG_ARCH_LH7A40X is not set
106# CONFIG_ARCH_OMAP is not set
107# CONFIG_ARCH_VERSATILE is not set
108# CONFIG_ARCH_REALVIEW is not set
109# CONFIG_ARCH_IMX is not set
110# CONFIG_ARCH_H720X is not set
111# CONFIG_ARCH_AAEC2000 is not set
112# CONFIG_ARCH_AT91RM9200 is not set
113
114#
115# Intel PXA2xx Implementations
116#
117# CONFIG_ARCH_LUBBOCK is not set
118# CONFIG_MACH_LOGICPD_PXA270 is not set
119# CONFIG_MACH_MAINSTONE is not set
120# CONFIG_ARCH_PXA_IDP is not set
121# CONFIG_PXA_SHARPSL is not set
122CONFIG_MACH_TRIZEPS4=y
123CONFIG_MACH_TRIZEPS4_CONXS=y
124# CONFIG_MACH_TRIZEPS4_ANY is not set
125CONFIG_PXA27x=y
126
127#
128# Processor Type
129#
130CONFIG_CPU_32=y
131CONFIG_CPU_XSCALE=y
132CONFIG_CPU_32v5=y
133CONFIG_CPU_ABRT_EV5T=y
134CONFIG_CPU_CACHE_VIVT=y
135CONFIG_CPU_TLB_V4WBI=y
136
137#
138# Processor Features
139#
140CONFIG_ARM_THUMB=y
141CONFIG_XSCALE_PMU=y
142
143#
144# Bus support
145#
146
147#
148# PCCARD (PCMCIA/CardBus) support
149#
150CONFIG_PCCARD=m
151# CONFIG_PCMCIA_DEBUG is not set
152CONFIG_PCMCIA=m
153CONFIG_PCMCIA_LOAD_CIS=y
154CONFIG_PCMCIA_IOCTL=y
155
156#
157# PC-card bridges
158#
159CONFIG_PCMCIA_PXA2XX=m
160
161#
162# Kernel Features
163#
164CONFIG_PREEMPT=y
165# CONFIG_NO_IDLE_HZ is not set
166CONFIG_HZ=100
167# CONFIG_AEABI is not set
168# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
169CONFIG_SELECT_MEMORY_MODEL=y
170CONFIG_FLATMEM_MANUAL=y
171# CONFIG_DISCONTIGMEM_MANUAL is not set
172# CONFIG_SPARSEMEM_MANUAL is not set
173CONFIG_FLATMEM=y
174CONFIG_FLAT_NODE_MEM_MAP=y
175# CONFIG_SPARSEMEM_STATIC is not set
176CONFIG_SPLIT_PTLOCK_CPUS=4096
177CONFIG_LEDS=y
178CONFIG_LEDS_TIMER=y
179CONFIG_LEDS_CPU=y
180CONFIG_ALIGNMENT_TRAP=y
181
182#
183# Boot options
184#
185CONFIG_ZBOOT_ROM_TEXT=0
186CONFIG_ZBOOT_ROM_BSS=0
187CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200n8"
188# CONFIG_XIP_KERNEL is not set
189
190#
191# Floating point emulation
192#
193
194#
195# At least one emulation must be selected
196#
197CONFIG_FPE_NWFPE=y
198CONFIG_FPE_NWFPE_XP=y
199# CONFIG_FPE_FASTFPE is not set
200
201#
202# Userspace binary formats
203#
204CONFIG_BINFMT_ELF=y
205# CONFIG_BINFMT_AOUT is not set
206CONFIG_BINFMT_MISC=m
207# CONFIG_ARTHUR is not set
208
209#
210# Power management options
211#
212CONFIG_PM=y
213CONFIG_PM_LEGACY=y
214# CONFIG_PM_DEBUG is not set
215CONFIG_APM=y
216
217#
218# Networking
219#
220CONFIG_NET=y
221
222#
223# Networking options
224#
225# CONFIG_NETDEBUG is not set
226CONFIG_PACKET=y
227CONFIG_PACKET_MMAP=y
228CONFIG_UNIX=y
229CONFIG_XFRM=y
230CONFIG_XFRM_USER=m
231CONFIG_NET_KEY=y
232CONFIG_INET=y
233# CONFIG_IP_MULTICAST is not set
234# CONFIG_IP_ADVANCED_ROUTER is not set
235CONFIG_IP_FIB_HASH=y
236CONFIG_IP_PNP=y
237CONFIG_IP_PNP_DHCP=y
238CONFIG_IP_PNP_BOOTP=y
239# CONFIG_IP_PNP_RARP is not set
240# CONFIG_NET_IPIP is not set
241# CONFIG_NET_IPGRE is not set
242# CONFIG_ARPD is not set
243# CONFIG_SYN_COOKIES is not set
244# CONFIG_INET_AH is not set
245# CONFIG_INET_ESP is not set
246# CONFIG_INET_IPCOMP is not set
247# CONFIG_INET_XFRM_TUNNEL is not set
248# CONFIG_INET_TUNNEL is not set
249CONFIG_INET_DIAG=y
250CONFIG_INET_TCP_DIAG=y
251# CONFIG_TCP_CONG_ADVANCED is not set
252CONFIG_TCP_CONG_BIC=y
253
254#
255# IP: Virtual Server Configuration
256#
257# CONFIG_IP_VS is not set
258CONFIG_IPV6=m
259# CONFIG_IPV6_PRIVACY is not set
260# CONFIG_IPV6_ROUTER_PREF is not set
261# CONFIG_INET6_AH is not set
262# CONFIG_INET6_ESP is not set
263# CONFIG_INET6_IPCOMP is not set
264# CONFIG_INET6_XFRM_TUNNEL is not set
265# CONFIG_INET6_TUNNEL is not set
266# CONFIG_IPV6_TUNNEL is not set
267CONFIG_NETFILTER=y
268# CONFIG_NETFILTER_DEBUG is not set
269
270#
271# Core Netfilter Configuration
272#
273# CONFIG_NETFILTER_NETLINK is not set
274# CONFIG_NETFILTER_XTABLES is not set
275
276#
277# IP: Netfilter Configuration
278#
279CONFIG_IP_NF_CONNTRACK=m
280CONFIG_IP_NF_CT_ACCT=y
281CONFIG_IP_NF_CONNTRACK_MARK=y
282# CONFIG_IP_NF_CONNTRACK_EVENTS is not set
283# CONFIG_IP_NF_CT_PROTO_SCTP is not set
284CONFIG_IP_NF_FTP=m
285CONFIG_IP_NF_IRC=m
286# CONFIG_IP_NF_NETBIOS_NS is not set
287CONFIG_IP_NF_TFTP=m
288CONFIG_IP_NF_AMANDA=m
289# CONFIG_IP_NF_PPTP is not set
290# CONFIG_IP_NF_H323 is not set
291CONFIG_IP_NF_QUEUE=m
292
293#
294# IPv6: Netfilter Configuration (EXPERIMENTAL)
295#
296# CONFIG_IP6_NF_QUEUE is not set
297
298#
299# DCCP Configuration (EXPERIMENTAL)
300#
301# CONFIG_IP_DCCP is not set
302
303#
304# SCTP Configuration (EXPERIMENTAL)
305#
306# CONFIG_IP_SCTP is not set
307
308#
309# TIPC Configuration (EXPERIMENTAL)
310#
311# CONFIG_TIPC is not set
312# CONFIG_ATM is not set
313# CONFIG_BRIDGE is not set
314CONFIG_VLAN_8021Q=m
315# CONFIG_DECNET is not set
316# CONFIG_LLC2 is not set
317# CONFIG_IPX is not set
318# CONFIG_ATALK is not set
319# CONFIG_X25 is not set
320# CONFIG_LAPB is not set
321# CONFIG_NET_DIVERT is not set
322# CONFIG_ECONET is not set
323# CONFIG_WAN_ROUTER is not set
324
325#
326# QoS and/or fair queueing
327#
328# CONFIG_NET_SCHED is not set
329
330#
331# Network testing
332#
333# CONFIG_NET_PKTGEN is not set
334# CONFIG_HAMRADIO is not set
335CONFIG_IRDA=m
336
337#
338# IrDA protocols
339#
340CONFIG_IRLAN=m
341CONFIG_IRNET=m
342CONFIG_IRCOMM=m
343CONFIG_IRDA_ULTRA=y
344
345#
346# IrDA options
347#
348CONFIG_IRDA_CACHE_LAST_LSAP=y
349CONFIG_IRDA_FAST_RR=y
350# CONFIG_IRDA_DEBUG is not set
351
352#
353# Infrared-port device drivers
354#
355
356#
357# SIR device drivers
358#
359CONFIG_IRTTY_SIR=m
360
361#
362# Dongle support
363#
364# CONFIG_DONGLE is not set
365
366#
367# Old SIR device drivers
368#
369# CONFIG_IRPORT_SIR is not set
370
371#
372# Old Serial dongle support
373#
374
375#
376# FIR device drivers
377#
378# CONFIG_USB_IRDA is not set
379# CONFIG_SIGMATEL_FIR is not set
380# CONFIG_PXA_FICP is not set
381CONFIG_BT=m
382CONFIG_BT_L2CAP=m
383CONFIG_BT_SCO=m
384CONFIG_BT_RFCOMM=m
385CONFIG_BT_RFCOMM_TTY=y
386CONFIG_BT_BNEP=m
387CONFIG_BT_BNEP_MC_FILTER=y
388CONFIG_BT_BNEP_PROTO_FILTER=y
389CONFIG_BT_HIDP=m
390
391#
392# Bluetooth device drivers
393#
394# CONFIG_BT_HCIUSB is not set
395# CONFIG_BT_HCIUART is not set
396# CONFIG_BT_HCIBCM203X is not set
397# CONFIG_BT_HCIBPA10X is not set
398# CONFIG_BT_HCIBFUSB is not set
399# CONFIG_BT_HCIDTL1 is not set
400# CONFIG_BT_HCIBT3C is not set
401# CONFIG_BT_HCIBLUECARD is not set
402# CONFIG_BT_HCIBTUART is not set
403# CONFIG_BT_HCIVHCI is not set
404CONFIG_IEEE80211=m
405# CONFIG_IEEE80211_DEBUG is not set
406CONFIG_IEEE80211_CRYPT_WEP=m
407CONFIG_IEEE80211_CRYPT_CCMP=m
408CONFIG_IEEE80211_CRYPT_TKIP=m
409CONFIG_IEEE80211_SOFTMAC=m
410# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
411CONFIG_WIRELESS_EXT=y
412
413#
414# Device Drivers
415#
416
417#
418# Generic Driver Options
419#
420CONFIG_STANDALONE=y
421CONFIG_PREVENT_FIRMWARE_BUILD=y
422CONFIG_FW_LOADER=y
423
424#
425# Connector - unified userspace <-> kernelspace linker
426#
427CONFIG_CONNECTOR=y
428CONFIG_PROC_EVENTS=y
429
430#
431# Memory Technology Devices (MTD)
432#
433CONFIG_MTD=y
434# CONFIG_MTD_DEBUG is not set
435CONFIG_MTD_CONCAT=y
436CONFIG_MTD_PARTITIONS=y
437CONFIG_MTD_REDBOOT_PARTS=y
438CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
439CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
440CONFIG_MTD_REDBOOT_PARTS_READONLY=y
441# CONFIG_MTD_CMDLINE_PARTS is not set
442# CONFIG_MTD_AFS_PARTS is not set
443
444#
445# User Modules And Translation Layers
446#
447CONFIG_MTD_CHAR=y
448CONFIG_MTD_BLOCK=y
449# CONFIG_FTL is not set
450CONFIG_NFTL=y
451CONFIG_NFTL_RW=y
452CONFIG_INFTL=y
453# CONFIG_RFD_FTL is not set
454
455#
456# RAM/ROM/Flash chip drivers
457#
458CONFIG_MTD_CFI=y
459CONFIG_MTD_JEDECPROBE=y
460CONFIG_MTD_GEN_PROBE=y
461CONFIG_MTD_CFI_ADV_OPTIONS=y
462# CONFIG_MTD_CFI_NOSWAP is not set
463# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
464CONFIG_MTD_CFI_LE_BYTE_SWAP=y
465CONFIG_MTD_CFI_GEOMETRY=y
466CONFIG_MTD_MAP_BANK_WIDTH_1=y
467CONFIG_MTD_MAP_BANK_WIDTH_2=y
468CONFIG_MTD_MAP_BANK_WIDTH_4=y
469# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
470# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
471# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
472CONFIG_MTD_CFI_I1=y
473CONFIG_MTD_CFI_I2=y
474# CONFIG_MTD_CFI_I4 is not set
475# CONFIG_MTD_CFI_I8 is not set
476# CONFIG_MTD_OTP is not set
477CONFIG_MTD_CFI_INTELEXT=y
478CONFIG_MTD_CFI_AMDSTD=y
479# CONFIG_MTD_CFI_STAA is not set
480CONFIG_MTD_CFI_UTIL=y
481# CONFIG_MTD_RAM is not set
482# CONFIG_MTD_ROM is not set
483# CONFIG_MTD_ABSENT is not set
484# CONFIG_MTD_OBSOLETE_CHIPS is not set
485# CONFIG_MTD_XIP is not set
486
487#
488# Mapping drivers for chip access
489#
490CONFIG_MTD_COMPLEX_MAPPINGS=y
491CONFIG_MTD_PHYSMAP=y
492CONFIG_MTD_PHYSMAP_START=0x0
493CONFIG_MTD_PHYSMAP_LEN=0x4000000
494CONFIG_MTD_PHYSMAP_BANKWIDTH=2
495# CONFIG_MTD_TRIZEPS4 is not set
496# CONFIG_MTD_ARM_INTEGRATOR is not set
497# CONFIG_MTD_IMPA7 is not set
498# CONFIG_MTD_SHARP_SL is not set
499# CONFIG_MTD_PLATRAM is not set
500
501#
502# Self-contained MTD device drivers
503#
504# CONFIG_MTD_DATAFLASH is not set
505# CONFIG_MTD_M25P80 is not set
506# CONFIG_MTD_SLRAM is not set
507# CONFIG_MTD_PHRAM is not set
508# CONFIG_MTD_MTDRAM is not set
509# CONFIG_MTD_BLOCK2MTD is not set
510
511#
512# Disk-On-Chip Device Drivers
513#
514# CONFIG_MTD_DOC2000 is not set
515# CONFIG_MTD_DOC2001 is not set
516CONFIG_MTD_DOC2001PLUS=y
517CONFIG_MTD_DOCPROBE=y
518CONFIG_MTD_DOCECC=y
519# CONFIG_MTD_DOCPROBE_ADVANCED is not set
520CONFIG_MTD_DOCPROBE_ADDRESS=0
521
522#
523# NAND Flash Device Drivers
524#
525CONFIG_MTD_NAND=y
526# CONFIG_MTD_NAND_VERIFY_WRITE is not set
527# CONFIG_MTD_NAND_H1900 is not set
528CONFIG_MTD_NAND_IDS=y
529CONFIG_MTD_NAND_DISKONCHIP=y
530# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set
531CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
532# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set
533# CONFIG_MTD_NAND_SHARPSL is not set
534# CONFIG_MTD_NAND_NANDSIM is not set
535
536#
537# OneNAND Flash Device Drivers
538#
539# CONFIG_MTD_ONENAND is not set
540
541#
542# Parallel port support
543#
544# CONFIG_PARPORT is not set
545
546#
547# Plug and Play support
548#
549
550#
551# Block devices
552#
553# CONFIG_BLK_DEV_COW_COMMON is not set
554CONFIG_BLK_DEV_LOOP=y
555CONFIG_BLK_DEV_CRYPTOLOOP=m
556CONFIG_BLK_DEV_NBD=y
557# CONFIG_BLK_DEV_UB is not set
558CONFIG_BLK_DEV_RAM=y
559CONFIG_BLK_DEV_RAM_COUNT=4
560CONFIG_BLK_DEV_RAM_SIZE=4096
561CONFIG_BLK_DEV_INITRD=y
562# CONFIG_CDROM_PKTCDVD is not set
563# CONFIG_ATA_OVER_ETH is not set
564
565#
566# ATA/ATAPI/MFM/RLL support
567#
568CONFIG_IDE=y
569CONFIG_BLK_DEV_IDE=y
570
571#
572# Please see Documentation/ide.txt for help/info on IDE drives
573#
574# CONFIG_BLK_DEV_IDE_SATA is not set
575CONFIG_BLK_DEV_IDEDISK=y
576CONFIG_IDEDISK_MULTI_MODE=y
577CONFIG_BLK_DEV_IDECS=m
578# CONFIG_BLK_DEV_IDECD is not set
579# CONFIG_BLK_DEV_IDETAPE is not set
580# CONFIG_BLK_DEV_IDEFLOPPY is not set
581# CONFIG_BLK_DEV_IDESCSI is not set
582# CONFIG_IDE_TASK_IOCTL is not set
583
584#
585# IDE chipset support/bugfixes
586#
587CONFIG_IDE_GENERIC=y
588CONFIG_IDE_PXA_CF=y
589CONFIG_IDE_ARM=y
590# CONFIG_BLK_DEV_IDEDMA is not set
591# CONFIG_IDEDMA_AUTO is not set
592# CONFIG_BLK_DEV_HD is not set
593
594#
595# SCSI device support
596#
597# CONFIG_RAID_ATTRS is not set
598CONFIG_SCSI=m
599CONFIG_SCSI_PROC_FS=y
600
601#
602# SCSI support type (disk, tape, CD-ROM)
603#
604CONFIG_BLK_DEV_SD=m
605# CONFIG_CHR_DEV_ST is not set
606# CONFIG_CHR_DEV_OSST is not set
607# CONFIG_BLK_DEV_SR is not set
608CONFIG_CHR_DEV_SG=m
609# CONFIG_CHR_DEV_SCH is not set
610
611#
612# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
613#
614CONFIG_SCSI_MULTI_LUN=y
615# CONFIG_SCSI_CONSTANTS is not set
616# CONFIG_SCSI_LOGGING is not set
617
618#
619# SCSI Transport Attributes
620#
621# CONFIG_SCSI_SPI_ATTRS is not set
622# CONFIG_SCSI_FC_ATTRS is not set
623# CONFIG_SCSI_ISCSI_ATTRS is not set
624# CONFIG_SCSI_SAS_ATTRS is not set
625
626#
627# SCSI low-level drivers
628#
629# CONFIG_ISCSI_TCP is not set
630# CONFIG_SCSI_SATA is not set
631# CONFIG_SCSI_DEBUG is not set
632
633#
634# PCMCIA SCSI adapter support
635#
636# CONFIG_PCMCIA_AHA152X is not set
637# CONFIG_PCMCIA_FDOMAIN is not set
638# CONFIG_PCMCIA_NINJA_SCSI is not set
639# CONFIG_PCMCIA_QLOGIC is not set
640# CONFIG_PCMCIA_SYM53C500 is not set
641
642#
643# Multi-device support (RAID and LVM)
644#
645# CONFIG_MD is not set
646
647#
648# Fusion MPT device support
649#
650# CONFIG_FUSION is not set
651
652#
653# IEEE 1394 (FireWire) support
654#
655
656#
657# I2O device support
658#
659
660#
661# Network device support
662#
663CONFIG_NETDEVICES=y
664# CONFIG_DUMMY is not set
665# CONFIG_BONDING is not set
666# CONFIG_EQUALIZER is not set
667# CONFIG_TUN is not set
668
669#
670# PHY device support
671#
672CONFIG_PHYLIB=y
673
674#
675# MII PHY device drivers
676#
677# CONFIG_MARVELL_PHY is not set
678CONFIG_DAVICOM_PHY=y
679# CONFIG_QSEMI_PHY is not set
680# CONFIG_LXT_PHY is not set
681# CONFIG_CICADA_PHY is not set
682
683#
684# Ethernet (10 or 100Mbit)
685#
686CONFIG_NET_ETHERNET=y
687CONFIG_MII=y
688# CONFIG_SMC91X is not set
689CONFIG_DM9000=y
690
691#
692# Ethernet (1000 Mbit)
693#
694
695#
696# Ethernet (10000 Mbit)
697#
698
699#
700# Token Ring devices
701#
702
703#
704# Wireless LAN (non-hamradio)
705#
706CONFIG_NET_RADIO=y
707# CONFIG_NET_WIRELESS_RTNETLINK is not set
708
709#
710# Obsolete Wireless cards support (pre-802.11)
711#
712# CONFIG_STRIP is not set
713# CONFIG_PCMCIA_WAVELAN is not set
714# CONFIG_PCMCIA_NETWAVE is not set
715
716#
717# Wireless 802.11 Frequency Hopping cards support
718#
719# CONFIG_PCMCIA_RAYCS is not set
720
721#
722# Wireless 802.11b ISA/PCI cards support
723#
724CONFIG_HERMES=m
725# CONFIG_ATMEL is not set
726
727#
728# Wireless 802.11b Pcmcia/Cardbus cards support
729#
730CONFIG_PCMCIA_HERMES=m
731# CONFIG_PCMCIA_SPECTRUM is not set
732CONFIG_AIRO_CS=m
733# CONFIG_PCMCIA_WL3501 is not set
734CONFIG_HOSTAP=m
735CONFIG_HOSTAP_FIRMWARE=y
736CONFIG_HOSTAP_FIRMWARE_NVRAM=y
737CONFIG_HOSTAP_CS=m
738CONFIG_NET_WIRELESS=y
739
740#
741# PCMCIA network device support
742#
743# CONFIG_NET_PCMCIA is not set
744
745#
746# Wan interfaces
747#
748# CONFIG_WAN is not set
749CONFIG_PPP=m
750CONFIG_PPP_MULTILINK=y
751CONFIG_PPP_FILTER=y
752CONFIG_PPP_ASYNC=m
753CONFIG_PPP_SYNC_TTY=m
754CONFIG_PPP_DEFLATE=m
755CONFIG_PPP_BSDCOMP=m
756CONFIG_PPP_MPPE=m
757# CONFIG_PPPOE is not set
758# CONFIG_SLIP is not set
759# CONFIG_SHAPER is not set
760# CONFIG_NETCONSOLE is not set
761# CONFIG_NETPOLL is not set
762# CONFIG_NET_POLL_CONTROLLER is not set
763
764#
765# ISDN subsystem
766#
767# CONFIG_ISDN is not set
768
769#
770# Input device support
771#
772CONFIG_INPUT=y
773
774#
775# Userland interfaces
776#
777CONFIG_INPUT_MOUSEDEV=y
778CONFIG_INPUT_MOUSEDEV_PSAUX=y
779CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
780CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
781# CONFIG_INPUT_JOYDEV is not set
782CONFIG_INPUT_TSDEV=y
783CONFIG_INPUT_TSDEV_SCREEN_X=640
784CONFIG_INPUT_TSDEV_SCREEN_Y=480
785CONFIG_INPUT_EVDEV=y
786# CONFIG_INPUT_EVBUG is not set
787
788#
789# Input Device Drivers
790#
791CONFIG_INPUT_KEYBOARD=y
792CONFIG_KEYBOARD_ATKBD=y
793# CONFIG_KEYBOARD_SUNKBD is not set
794# CONFIG_KEYBOARD_LKKBD is not set
795# CONFIG_KEYBOARD_XTKBD is not set
796# CONFIG_KEYBOARD_NEWTON is not set
797CONFIG_INPUT_MOUSE=y
798# CONFIG_MOUSE_PS2 is not set
799CONFIG_MOUSE_SERIAL=y
800# CONFIG_MOUSE_VSXXXAA is not set
801# CONFIG_INPUT_JOYSTICK is not set
802CONFIG_INPUT_TOUCHSCREEN=y
803# CONFIG_TOUCHSCREEN_ADS7846 is not set
804# CONFIG_TOUCHSCREEN_GUNZE is not set
805# CONFIG_TOUCHSCREEN_ELO is not set
806# CONFIG_TOUCHSCREEN_MTOUCH is not set
807# CONFIG_TOUCHSCREEN_MK712 is not set
808CONFIG_INPUT_MISC=y
809CONFIG_INPUT_UINPUT=m
810
811#
812# Hardware I/O ports
813#
814CONFIG_SERIO=y
815CONFIG_SERIO_SERPORT=y
816CONFIG_SERIO_LIBPS2=y
817# CONFIG_SERIO_RAW is not set
818# CONFIG_GAMEPORT is not set
819
820#
821# Character devices
822#
823CONFIG_VT=y
824CONFIG_VT_CONSOLE=y
825CONFIG_HW_CONSOLE=y
826# CONFIG_SERIAL_NONSTANDARD is not set
827
828#
829# Serial drivers
830#
831# CONFIG_SERIAL_8250 is not set
832
833#
834# Non-8250 serial port support
835#
836CONFIG_SERIAL_PXA=y
837CONFIG_SERIAL_PXA_CONSOLE=y
838CONFIG_SERIAL_CORE=y
839CONFIG_SERIAL_CORE_CONSOLE=y
840CONFIG_UNIX98_PTYS=y
841CONFIG_LEGACY_PTYS=y
842CONFIG_LEGACY_PTY_COUNT=256
843
844#
845# IPMI
846#
847# CONFIG_IPMI_HANDLER is not set
848
849#
850# Watchdog Cards
851#
852CONFIG_WATCHDOG=y
853# CONFIG_WATCHDOG_NOWAYOUT is not set
854
855#
856# Watchdog Device Drivers
857#
858# CONFIG_SOFT_WATCHDOG is not set
859CONFIG_SA1100_WATCHDOG=y
860
861#
862# USB-based Watchdog Cards
863#
864# CONFIG_USBPCWATCHDOG is not set
865# CONFIG_NVRAM is not set
866# CONFIG_DTLK is not set
867# CONFIG_R3964 is not set
868
869#
870# Ftape, the floppy tape device driver
871#
872
873#
874# PCMCIA character devices
875#
876# CONFIG_SYNCLINK_CS is not set
877# CONFIG_CARDMAN_4000 is not set
878# CONFIG_CARDMAN_4040 is not set
879# CONFIG_RAW_DRIVER is not set
880
881#
882# TPM devices
883#
884# CONFIG_TCG_TPM is not set
885# CONFIG_TELCLOCK is not set
886
887#
888# I2C support
889#
890CONFIG_I2C=y
891CONFIG_I2C_CHARDEV=y
892
893#
894# I2C Algorithms
895#
896# CONFIG_I2C_ALGOBIT is not set
897# CONFIG_I2C_ALGOPCF is not set
898# CONFIG_I2C_ALGOPCA is not set
899
900#
901# I2C Hardware Bus support
902#
903CONFIG_I2C_PXA=y
904CONFIG_I2C_PXA_SLAVE=y
905# CONFIG_I2C_PARPORT_LIGHT is not set
906# CONFIG_I2C_STUB is not set
907# CONFIG_I2C_PCA_ISA is not set
908
909#
910# Miscellaneous I2C Chip support
911#
912# CONFIG_SENSORS_DS1337 is not set
913# CONFIG_SENSORS_DS1374 is not set
914CONFIG_SENSORS_EEPROM=m
915# CONFIG_SENSORS_PCF8574 is not set
916# CONFIG_SENSORS_PCA9539 is not set
917# CONFIG_SENSORS_PCF8591 is not set
918# CONFIG_SENSORS_MAX6875 is not set
919# CONFIG_I2C_DEBUG_CORE is not set
920# CONFIG_I2C_DEBUG_ALGO is not set
921# CONFIG_I2C_DEBUG_BUS is not set
922# CONFIG_I2C_DEBUG_CHIP is not set
923
924#
925# SPI support
926#
927CONFIG_SPI=y
928CONFIG_SPI_MASTER=y
929
930#
931# SPI Master Controller Drivers
932#
933# CONFIG_SPI_BITBANG is not set
934CONFIG_SPI_PXA2XX=m
935
936#
937# SPI Protocol Masters
938#
939
940#
941# Dallas's 1-wire bus
942#
943# CONFIG_W1 is not set
944
945#
946# Hardware Monitoring support
947#
948CONFIG_HWMON=y
949# CONFIG_HWMON_VID is not set
950# CONFIG_SENSORS_ADM1021 is not set
951# CONFIG_SENSORS_ADM1025 is not set
952# CONFIG_SENSORS_ADM1026 is not set
953# CONFIG_SENSORS_ADM1031 is not set
954# CONFIG_SENSORS_ADM9240 is not set
955# CONFIG_SENSORS_ASB100 is not set
956# CONFIG_SENSORS_ATXP1 is not set
957# CONFIG_SENSORS_DS1621 is not set
958# CONFIG_SENSORS_F71805F is not set
959# CONFIG_SENSORS_FSCHER is not set
960# CONFIG_SENSORS_FSCPOS is not set
961# CONFIG_SENSORS_GL518SM is not set
962# CONFIG_SENSORS_GL520SM is not set
963# CONFIG_SENSORS_IT87 is not set
964# CONFIG_SENSORS_LM63 is not set
965# CONFIG_SENSORS_LM75 is not set
966# CONFIG_SENSORS_LM77 is not set
967# CONFIG_SENSORS_LM78 is not set
968# CONFIG_SENSORS_LM80 is not set
969# CONFIG_SENSORS_LM83 is not set
970# CONFIG_SENSORS_LM85 is not set
971# CONFIG_SENSORS_LM87 is not set
972# CONFIG_SENSORS_LM90 is not set
973# CONFIG_SENSORS_LM92 is not set
974# CONFIG_SENSORS_MAX1619 is not set
975# CONFIG_SENSORS_PC87360 is not set
976# CONFIG_SENSORS_SMSC47M1 is not set
977# CONFIG_SENSORS_SMSC47B397 is not set
978# CONFIG_SENSORS_W83781D is not set
979# CONFIG_SENSORS_W83792D is not set
980# CONFIG_SENSORS_W83L785TS is not set
981# CONFIG_SENSORS_W83627HF is not set
982# CONFIG_SENSORS_W83627EHF is not set
983# CONFIG_HWMON_DEBUG_CHIP is not set
984
985#
986# Misc devices
987#
988
989#
990# Multimedia Capabilities Port drivers
991#
992CONFIG_UCB1400=y
993CONFIG_UCB1400_TS=y
994
995#
996# LED devices
997#
998CONFIG_NEW_LEDS=y
999CONFIG_LEDS_CLASS=y
1000
1001#
1002# LED drivers
1003#
1004
1005#
1006# LED Triggers
1007#
1008CONFIG_LEDS_TRIGGERS=y
1009CONFIG_LEDS_TRIGGER_TIMER=y
1010CONFIG_LEDS_TRIGGER_IDE_DISK=y
1011
1012#
1013# Multimedia devices
1014#
1015# CONFIG_VIDEO_DEV is not set
1016CONFIG_VIDEO_V4L2=y
1017
1018#
1019# Digital Video Broadcasting Devices
1020#
1021# CONFIG_DVB is not set
1022# CONFIG_USB_DABUSB is not set
1023
1024#
1025# Graphics support
1026#
1027CONFIG_FB=y
1028CONFIG_FB_CFB_FILLRECT=y
1029CONFIG_FB_CFB_COPYAREA=y
1030CONFIG_FB_CFB_IMAGEBLIT=y
1031# CONFIG_FB_MACMODES is not set
1032CONFIG_FB_FIRMWARE_EDID=y
1033# CONFIG_FB_MODE_HELPERS is not set
1034# CONFIG_FB_TILEBLITTING is not set
1035# CONFIG_FB_S1D13XXX is not set
1036CONFIG_FB_PXA=y
1037# CONFIG_FB_PXA_PARAMETERS is not set
1038# CONFIG_FB_VIRTUAL is not set
1039
1040#
1041# Console display driver support
1042#
1043# CONFIG_VGA_CONSOLE is not set
1044CONFIG_DUMMY_CONSOLE=y
1045CONFIG_FRAMEBUFFER_CONSOLE=y
1046CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
1047CONFIG_FONTS=y
1048CONFIG_FONT_8x8=y
1049CONFIG_FONT_8x16=y
1050# CONFIG_FONT_6x11 is not set
1051# CONFIG_FONT_7x14 is not set
1052# CONFIG_FONT_PEARL_8x8 is not set
1053# CONFIG_FONT_ACORN_8x8 is not set
1054# CONFIG_FONT_MINI_4x6 is not set
1055# CONFIG_FONT_SUN8x16 is not set
1056# CONFIG_FONT_SUN12x22 is not set
1057# CONFIG_FONT_10x18 is not set
1058
1059#
1060# Logo configuration
1061#
1062CONFIG_LOGO=y
1063CONFIG_LOGO_LINUX_MONO=y
1064CONFIG_LOGO_LINUX_VGA16=y
1065CONFIG_LOGO_LINUX_CLUT224=y
1066CONFIG_BACKLIGHT_LCD_SUPPORT=y
1067CONFIG_BACKLIGHT_CLASS_DEVICE=y
1068CONFIG_BACKLIGHT_DEVICE=y
1069CONFIG_LCD_CLASS_DEVICE=y
1070CONFIG_LCD_DEVICE=y
1071
1072#
1073# Sound
1074#
1075CONFIG_SOUND=y
1076
1077#
1078# Advanced Linux Sound Architecture
1079#
1080CONFIG_SND=y
1081CONFIG_SND_TIMER=y
1082CONFIG_SND_PCM=y
1083CONFIG_SND_HWDEP=m
1084CONFIG_SND_RAWMIDI=m
1085CONFIG_SND_SEQUENCER=m
1086# CONFIG_SND_SEQ_DUMMY is not set
1087CONFIG_SND_OSSEMUL=y
1088CONFIG_SND_MIXER_OSS=y
1089CONFIG_SND_PCM_OSS=y
1090CONFIG_SND_PCM_OSS_PLUGINS=y
1091# CONFIG_SND_SEQUENCER_OSS is not set
1092# CONFIG_SND_DYNAMIC_MINORS is not set
1093CONFIG_SND_SUPPORT_OLD_API=y
1094CONFIG_SND_VERBOSE_PROCFS=y
1095CONFIG_SND_VERBOSE_PRINTK=y
1096# CONFIG_SND_DEBUG is not set
1097
1098#
1099# Generic devices
1100#
1101CONFIG_SND_AC97_CODEC=y
1102CONFIG_SND_AC97_BUS=y
1103# CONFIG_SND_DUMMY is not set
1104# CONFIG_SND_VIRMIDI is not set
1105# CONFIG_SND_MTPAV is not set
1106# CONFIG_SND_SERIAL_U16550 is not set
1107# CONFIG_SND_MPU401 is not set
1108
1109#
1110# ALSA ARM devices
1111#
1112CONFIG_SND_PXA2XX_PCM=y
1113CONFIG_SND_PXA2XX_AC97=y
1114
1115#
1116# USB devices
1117#
1118CONFIG_SND_USB_AUDIO=m
1119
1120#
1121# PCMCIA devices
1122#
1123# CONFIG_SND_VXPOCKET is not set
1124# CONFIG_SND_PDAUDIOCF is not set
1125
1126#
1127# Open Sound System
1128#
1129# CONFIG_SOUND_PRIME is not set
1130
1131#
1132# USB support
1133#
1134CONFIG_USB_ARCH_HAS_HCD=y
1135CONFIG_USB_ARCH_HAS_OHCI=y
1136# CONFIG_USB_ARCH_HAS_EHCI is not set
1137CONFIG_USB=y
1138# CONFIG_USB_DEBUG is not set
1139
1140#
1141# Miscellaneous USB options
1142#
1143CONFIG_USB_DEVICEFS=y
1144# CONFIG_USB_BANDWIDTH is not set
1145# CONFIG_USB_DYNAMIC_MINORS is not set
1146# CONFIG_USB_SUSPEND is not set
1147# CONFIG_USB_OTG is not set
1148
1149#
1150# USB Host Controller Drivers
1151#
1152# CONFIG_USB_ISP116X_HCD is not set
1153CONFIG_USB_OHCI_HCD=y
1154# CONFIG_USB_OHCI_BIG_ENDIAN is not set
1155CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1156# CONFIG_USB_SL811_HCD is not set
1157
1158#
1159# USB Device Class drivers
1160#
1161# CONFIG_USB_ACM is not set
1162# CONFIG_USB_PRINTER is not set
1163
1164#
1165# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1166#
1167
1168#
1169# may also be needed; see USB_STORAGE Help for more information
1170#
1171CONFIG_USB_STORAGE=m
1172# CONFIG_USB_STORAGE_DEBUG is not set
1173# CONFIG_USB_STORAGE_DATAFAB is not set
1174# CONFIG_USB_STORAGE_FREECOM is not set
1175# CONFIG_USB_STORAGE_ISD200 is not set
1176# CONFIG_USB_STORAGE_DPCM is not set
1177# CONFIG_USB_STORAGE_USBAT is not set
1178# CONFIG_USB_STORAGE_SDDR09 is not set
1179# CONFIG_USB_STORAGE_SDDR55 is not set
1180# CONFIG_USB_STORAGE_JUMPSHOT is not set
1181# CONFIG_USB_STORAGE_ALAUDA is not set
1182# CONFIG_USB_LIBUSUAL is not set
1183
1184#
1185# USB Input Devices
1186#
1187CONFIG_USB_HID=m
1188CONFIG_USB_HIDINPUT=y
1189# CONFIG_USB_HIDINPUT_POWERBOOK is not set
1190# CONFIG_HID_FF is not set
1191# CONFIG_USB_HIDDEV is not set
1192
1193#
1194# USB HID Boot Protocol drivers
1195#
1196# CONFIG_USB_KBD is not set
1197# CONFIG_USB_MOUSE is not set
1198# CONFIG_USB_AIPTEK is not set
1199# CONFIG_USB_WACOM is not set
1200# CONFIG_USB_ACECAD is not set
1201# CONFIG_USB_KBTAB is not set
1202# CONFIG_USB_POWERMATE is not set
1203CONFIG_USB_TOUCHSCREEN=m
1204# CONFIG_USB_TOUCHSCREEN_EGALAX is not set
1205# CONFIG_USB_TOUCHSCREEN_PANJIT is not set
1206# CONFIG_USB_TOUCHSCREEN_3M is not set
1207# CONFIG_USB_TOUCHSCREEN_ITM is not set
1208# CONFIG_USB_YEALINK is not set
1209# CONFIG_USB_XPAD is not set
1210# CONFIG_USB_ATI_REMOTE is not set
1211# CONFIG_USB_ATI_REMOTE2 is not set
1212# CONFIG_USB_KEYSPAN_REMOTE is not set
1213# CONFIG_USB_APPLETOUCH is not set
1214
1215#
1216# USB Imaging devices
1217#
1218# CONFIG_USB_MDC800 is not set
1219# CONFIG_USB_MICROTEK is not set
1220
1221#
1222# USB Network Adapters
1223#
1224# CONFIG_USB_CATC is not set
1225# CONFIG_USB_KAWETH is not set
1226# CONFIG_USB_PEGASUS is not set
1227# CONFIG_USB_RTL8150 is not set
1228# CONFIG_USB_USBNET is not set
1229# CONFIG_USB_ZD1201 is not set
1230CONFIG_USB_MON=y
1231
1232#
1233# USB port drivers
1234#
1235
1236#
1237# USB Serial Converter support
1238#
1239# CONFIG_USB_SERIAL is not set
1240
1241#
1242# USB Miscellaneous drivers
1243#
1244# CONFIG_USB_EMI62 is not set
1245# CONFIG_USB_EMI26 is not set
1246# CONFIG_USB_AUERSWALD is not set
1247# CONFIG_USB_RIO500 is not set
1248# CONFIG_USB_LEGOTOWER is not set
1249# CONFIG_USB_LCD is not set
1250# CONFIG_USB_LED is not set
1251# CONFIG_USB_CYTHERM is not set
1252# CONFIG_USB_PHIDGETKIT is not set
1253# CONFIG_USB_PHIDGETSERVO is not set
1254# CONFIG_USB_IDMOUSE is not set
1255# CONFIG_USB_LD is not set
1256# CONFIG_USB_TEST is not set
1257
1258#
1259# USB DSL modem support
1260#
1261
1262#
1263# USB Gadget Support
1264#
1265CONFIG_USB_GADGET=y
1266# CONFIG_USB_GADGET_DEBUG_FILES is not set
1267CONFIG_USB_GADGET_SELECTED=y
1268# CONFIG_USB_GADGET_NET2280 is not set
1269# CONFIG_USB_GADGET_PXA2XX is not set
1270# CONFIG_USB_GADGET_GOKU is not set
1271# CONFIG_USB_GADGET_LH7A40X is not set
1272# CONFIG_USB_GADGET_OMAP is not set
1273# CONFIG_USB_GADGET_AT91 is not set
1274CONFIG_USB_GADGET_DUMMY_HCD=y
1275CONFIG_USB_DUMMY_HCD=y
1276CONFIG_USB_GADGET_DUALSPEED=y
1277# CONFIG_USB_ZERO is not set
1278CONFIG_USB_ETH=m
1279CONFIG_USB_ETH_RNDIS=y
1280CONFIG_USB_GADGETFS=m
1281CONFIG_USB_FILE_STORAGE=m
1282# CONFIG_USB_FILE_STORAGE_TEST is not set
1283CONFIG_USB_G_SERIAL=m
1284
1285#
1286# MMC/SD Card support
1287#
1288CONFIG_MMC=y
1289# CONFIG_MMC_DEBUG is not set
1290CONFIG_MMC_BLOCK=y
1291CONFIG_MMC_PXA=y
1292
1293#
1294# Real Time Clock
1295#
1296CONFIG_RTC_LIB=y
1297CONFIG_RTC_CLASS=y
1298CONFIG_RTC_HCTOSYS=y
1299CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1300
1301#
1302# RTC interfaces
1303#
1304CONFIG_RTC_INTF_SYSFS=y
1305CONFIG_RTC_INTF_PROC=y
1306CONFIG_RTC_INTF_DEV=y
1307
1308#
1309# RTC drivers
1310#
1311# CONFIG_RTC_DRV_X1205 is not set
1312# CONFIG_RTC_DRV_DS1672 is not set
1313# CONFIG_RTC_DRV_PCF8563 is not set
1314# CONFIG_RTC_DRV_RS5C372 is not set
1315# CONFIG_RTC_DRV_M48T86 is not set
1316CONFIG_RTC_DRV_SA1100=y
1317# CONFIG_RTC_DRV_TEST is not set
1318
1319#
1320# File systems
1321#
1322CONFIG_EXT2_FS=y
1323CONFIG_EXT2_FS_XATTR=y
1324CONFIG_EXT2_FS_POSIX_ACL=y
1325CONFIG_EXT2_FS_SECURITY=y
1326# CONFIG_EXT2_FS_XIP is not set
1327CONFIG_EXT3_FS=y
1328CONFIG_EXT3_FS_XATTR=y
1329CONFIG_EXT3_FS_POSIX_ACL=y
1330CONFIG_EXT3_FS_SECURITY=y
1331CONFIG_JBD=y
1332# CONFIG_JBD_DEBUG is not set
1333CONFIG_FS_MBCACHE=y
1334# CONFIG_REISERFS_FS is not set
1335# CONFIG_JFS_FS is not set
1336CONFIG_FS_POSIX_ACL=y
1337# CONFIG_XFS_FS is not set
1338# CONFIG_OCFS2_FS is not set
1339# CONFIG_MINIX_FS is not set
1340# CONFIG_ROMFS_FS is not set
1341CONFIG_INOTIFY=y
1342# CONFIG_QUOTA is not set
1343CONFIG_DNOTIFY=y
1344# CONFIG_AUTOFS_FS is not set
1345CONFIG_AUTOFS4_FS=y
1346# CONFIG_FUSE_FS is not set
1347
1348#
1349# CD-ROM/DVD Filesystems
1350#
1351# CONFIG_ISO9660_FS is not set
1352# CONFIG_UDF_FS is not set
1353
1354#
1355# DOS/FAT/NT Filesystems
1356#
1357CONFIG_FAT_FS=m
1358CONFIG_MSDOS_FS=m
1359CONFIG_VFAT_FS=m
1360CONFIG_FAT_DEFAULT_CODEPAGE=437
1361CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15"
1362# CONFIG_NTFS_FS is not set
1363
1364#
1365# Pseudo filesystems
1366#
1367CONFIG_PROC_FS=y
1368CONFIG_SYSFS=y
1369CONFIG_TMPFS=y
1370# CONFIG_HUGETLB_PAGE is not set
1371CONFIG_RAMFS=y
1372# CONFIG_CONFIGFS_FS is not set
1373
1374#
1375# Miscellaneous filesystems
1376#
1377# CONFIG_ADFS_FS is not set
1378# CONFIG_AFFS_FS is not set
1379# CONFIG_HFS_FS is not set
1380# CONFIG_HFSPLUS_FS is not set
1381# CONFIG_BEFS_FS is not set
1382# CONFIG_BFS_FS is not set
1383# CONFIG_EFS_FS is not set
1384CONFIG_JFFS_FS=y
1385CONFIG_JFFS_FS_VERBOSE=0
1386CONFIG_JFFS_PROC_FS=y
1387CONFIG_JFFS2_FS=y
1388CONFIG_JFFS2_FS_DEBUG=0
1389CONFIG_JFFS2_FS_WRITEBUFFER=y
1390# CONFIG_JFFS2_SUMMARY is not set
1391CONFIG_JFFS2_COMPRESSION_OPTIONS=y
1392CONFIG_JFFS2_ZLIB=y
1393CONFIG_JFFS2_RTIME=y
1394# CONFIG_JFFS2_RUBIN is not set
1395# CONFIG_JFFS2_CMODE_NONE is not set
1396CONFIG_JFFS2_CMODE_PRIORITY=y
1397# CONFIG_JFFS2_CMODE_SIZE is not set
1398# CONFIG_CRAMFS is not set
1399# CONFIG_VXFS_FS is not set
1400# CONFIG_HPFS_FS is not set
1401# CONFIG_QNX4FS_FS is not set
1402# CONFIG_SYSV_FS is not set
1403# CONFIG_UFS_FS is not set
1404
1405#
1406# Network File Systems
1407#
1408CONFIG_NFS_FS=y
1409CONFIG_NFS_V3=y
1410CONFIG_NFS_V3_ACL=y
1411CONFIG_NFS_V4=y
1412# CONFIG_NFS_DIRECTIO is not set
1413CONFIG_NFSD=y
1414CONFIG_NFSD_V2_ACL=y
1415CONFIG_NFSD_V3=y
1416CONFIG_NFSD_V3_ACL=y
1417CONFIG_NFSD_V4=y
1418CONFIG_NFSD_TCP=y
1419CONFIG_ROOT_NFS=y
1420CONFIG_LOCKD=y
1421CONFIG_LOCKD_V4=y
1422CONFIG_EXPORTFS=y
1423CONFIG_NFS_ACL_SUPPORT=y
1424CONFIG_NFS_COMMON=y
1425CONFIG_SUNRPC=y
1426CONFIG_SUNRPC_GSS=y
1427CONFIG_RPCSEC_GSS_KRB5=y
1428# CONFIG_RPCSEC_GSS_SPKM3 is not set
1429CONFIG_SMB_FS=m
1430# CONFIG_SMB_NLS_DEFAULT is not set
1431CONFIG_CIFS=m
1432# CONFIG_CIFS_STATS is not set
1433# CONFIG_CIFS_XATTR is not set
1434# CONFIG_CIFS_EXPERIMENTAL is not set
1435# CONFIG_NCP_FS is not set
1436# CONFIG_CODA_FS is not set
1437# CONFIG_AFS_FS is not set
1438# CONFIG_9P_FS is not set
1439
1440#
1441# Partition Types
1442#
1443CONFIG_PARTITION_ADVANCED=y
1444# CONFIG_ACORN_PARTITION is not set
1445# CONFIG_OSF_PARTITION is not set
1446# CONFIG_AMIGA_PARTITION is not set
1447# CONFIG_ATARI_PARTITION is not set
1448# CONFIG_MAC_PARTITION is not set
1449CONFIG_MSDOS_PARTITION=y
1450# CONFIG_BSD_DISKLABEL is not set
1451# CONFIG_MINIX_SUBPARTITION is not set
1452# CONFIG_SOLARIS_X86_PARTITION is not set
1453# CONFIG_UNIXWARE_DISKLABEL is not set
1454CONFIG_LDM_PARTITION=y
1455# CONFIG_LDM_DEBUG is not set
1456# CONFIG_SGI_PARTITION is not set
1457# CONFIG_ULTRIX_PARTITION is not set
1458# CONFIG_SUN_PARTITION is not set
1459# CONFIG_KARMA_PARTITION is not set
1460# CONFIG_EFI_PARTITION is not set
1461
1462#
1463# Native Language Support
1464#
1465CONFIG_NLS=y
1466CONFIG_NLS_DEFAULT="iso8859-15"
1467CONFIG_NLS_CODEPAGE_437=y
1468# CONFIG_NLS_CODEPAGE_737 is not set
1469# CONFIG_NLS_CODEPAGE_775 is not set
1470CONFIG_NLS_CODEPAGE_850=y
1471# CONFIG_NLS_CODEPAGE_852 is not set
1472# CONFIG_NLS_CODEPAGE_855 is not set
1473# CONFIG_NLS_CODEPAGE_857 is not set
1474# CONFIG_NLS_CODEPAGE_860 is not set
1475# CONFIG_NLS_CODEPAGE_861 is not set
1476# CONFIG_NLS_CODEPAGE_862 is not set
1477# CONFIG_NLS_CODEPAGE_863 is not set
1478# CONFIG_NLS_CODEPAGE_864 is not set
1479# CONFIG_NLS_CODEPAGE_865 is not set
1480# CONFIG_NLS_CODEPAGE_866 is not set
1481# CONFIG_NLS_CODEPAGE_869 is not set
1482# CONFIG_NLS_CODEPAGE_936 is not set
1483# CONFIG_NLS_CODEPAGE_950 is not set
1484# CONFIG_NLS_CODEPAGE_932 is not set
1485# CONFIG_NLS_CODEPAGE_949 is not set
1486# CONFIG_NLS_CODEPAGE_874 is not set
1487# CONFIG_NLS_ISO8859_8 is not set
1488# CONFIG_NLS_CODEPAGE_1250 is not set
1489# CONFIG_NLS_CODEPAGE_1251 is not set
1490CONFIG_NLS_ASCII=y
1491CONFIG_NLS_ISO8859_1=m
1492# CONFIG_NLS_ISO8859_2 is not set
1493# CONFIG_NLS_ISO8859_3 is not set
1494# CONFIG_NLS_ISO8859_4 is not set
1495# CONFIG_NLS_ISO8859_5 is not set
1496# CONFIG_NLS_ISO8859_6 is not set
1497# CONFIG_NLS_ISO8859_7 is not set
1498# CONFIG_NLS_ISO8859_9 is not set
1499# CONFIG_NLS_ISO8859_13 is not set
1500# CONFIG_NLS_ISO8859_14 is not set
1501CONFIG_NLS_ISO8859_15=m
1502# CONFIG_NLS_KOI8_R is not set
1503# CONFIG_NLS_KOI8_U is not set
1504CONFIG_NLS_UTF8=m
1505
1506#
1507# Profiling support
1508#
1509CONFIG_PROFILING=y
1510CONFIG_OPROFILE=y
1511
1512#
1513# Kernel hacking
1514#
1515# CONFIG_PRINTK_TIME is not set
1516CONFIG_MAGIC_SYSRQ=y
1517# CONFIG_DEBUG_KERNEL is not set
1518CONFIG_LOG_BUF_SHIFT=14
1519# CONFIG_DEBUG_BUGVERBOSE is not set
1520# CONFIG_DEBUG_FS is not set
1521CONFIG_FRAME_POINTER=y
1522# CONFIG_UNWIND_INFO is not set
1523CONFIG_DEBUG_USER=y
1524
1525#
1526# Security options
1527#
1528CONFIG_KEYS=y
1529CONFIG_KEYS_DEBUG_PROC_KEYS=y
1530CONFIG_SECURITY=y
1531# CONFIG_SECURITY_NETWORK is not set
1532CONFIG_SECURITY_CAPABILITIES=y
1533# CONFIG_SECURITY_ROOTPLUG is not set
1534# CONFIG_SECURITY_SECLVL is not set
1535
1536#
1537# Cryptographic options
1538#
1539CONFIG_CRYPTO=y
1540# CONFIG_CRYPTO_HMAC is not set
1541# CONFIG_CRYPTO_NULL is not set
1542CONFIG_CRYPTO_MD4=y
1543CONFIG_CRYPTO_MD5=y
1544CONFIG_CRYPTO_SHA1=m
1545CONFIG_CRYPTO_SHA256=m
1546CONFIG_CRYPTO_SHA512=m
1547# CONFIG_CRYPTO_WP512 is not set
1548# CONFIG_CRYPTO_TGR192 is not set
1549CONFIG_CRYPTO_DES=y
1550# CONFIG_CRYPTO_BLOWFISH is not set
1551# CONFIG_CRYPTO_TWOFISH is not set
1552# CONFIG_CRYPTO_SERPENT is not set
1553CONFIG_CRYPTO_AES=m
1554# CONFIG_CRYPTO_CAST5 is not set
1555# CONFIG_CRYPTO_CAST6 is not set
1556# CONFIG_CRYPTO_TEA is not set
1557CONFIG_CRYPTO_ARC4=m
1558# CONFIG_CRYPTO_KHAZAD is not set
1559# CONFIG_CRYPTO_ANUBIS is not set
1560CONFIG_CRYPTO_DEFLATE=m
1561CONFIG_CRYPTO_MICHAEL_MIC=m
1562CONFIG_CRYPTO_CRC32C=y
1563# CONFIG_CRYPTO_TEST is not set
1564
1565#
1566# Hardware crypto devices
1567#
1568
1569#
1570# Library routines
1571#
1572CONFIG_CRC_CCITT=y
1573CONFIG_CRC16=y
1574CONFIG_CRC32=y
1575CONFIG_LIBCRC32C=y
1576CONFIG_ZLIB_INFLATE=y
1577CONFIG_ZLIB_DEFLATE=y
1578CONFIG_REED_SOLOMON=y
1579CONFIG_REED_SOLOMON_DEC16=y
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 7cffbaef064b..f0c0cdb1c183 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -25,7 +25,7 @@ obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o
25obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o 25obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o
26AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 26AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
27 27
28obj-$(CONFIG_IWMMXT) += iwmmxt.o 28obj-$(CONFIG_IWMMXT) += iwmmxt.o iwmmxt-notifier.o
29AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt 29AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt
30 30
31ifneq ($(CONFIG_ARCH_EBSA110),y) 31ifneq ($(CONFIG_ARCH_EBSA110),y)
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 447ede5143a8..cc2d58d028e1 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -105,6 +105,7 @@ int main(void)
105 BLANK(); 105 BLANK();
106 DEFINE(PROC_INFO_SZ, sizeof(struct proc_info_list)); 106 DEFINE(PROC_INFO_SZ, sizeof(struct proc_info_list));
107 DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush)); 107 DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush));
108 DEFINE(PROCINFO_MMUFLAGS, offsetof(struct proc_info_list, __cpu_mmu_flags)); 108 DEFINE(PROCINFO_MM_MMUFLAGS, offsetof(struct proc_info_list, __cpu_mm_mmu_flags));
109 DEFINE(PROCINFO_IO_MMUFLAGS, offsetof(struct proc_info_list, __cpu_io_mmu_flags));
109 return 0; 110 return 0;
110} 111}
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 26f197afd204..7ea5f01dfc7b 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -589,9 +589,7 @@ ENTRY(__switch_to)
589#ifdef CONFIG_MMU 589#ifdef CONFIG_MMU
590 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 590 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
591#endif 591#endif
592#if defined(CONFIG_IWMMXT) 592#if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
593 bl iwmmxt_task_switch
594#elif defined(CONFIG_CPU_XSCALE)
595 add r4, r2, #TI_CPU_DOMAIN + 40 @ cpu_context_save->extra 593 add r4, r2, #TI_CPU_DOMAIN + 40 @ cpu_context_save->extra
596 ldmib r4, {r4, r5} 594 ldmib r4, {r4, r5}
597 mar acc0, r4, r5 595 mar acc0, r4, r5
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 518b80cd87de..2242f5f7cb7d 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -220,7 +220,7 @@ __create_page_tables:
220 teq r0, r6 220 teq r0, r6
221 bne 1b 221 bne 1b
222 222
223 ldr r7, [r10, #PROCINFO_MMUFLAGS] @ mmuflags 223 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
224 224
225 /* 225 /*
226 * Create identity mapping for first MB of kernel to 226 * Create identity mapping for first MB of kernel to
@@ -271,8 +271,7 @@ __create_page_tables:
271#endif 271#endif
272 272
273#ifdef CONFIG_DEBUG_LL 273#ifdef CONFIG_DEBUG_LL
274 bic r7, r7, #0x0c @ turn off cacheable 274 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
275 @ and bufferable bits
276 /* 275 /*
277 * Map in IO space for serial debugging. 276 * Map in IO space for serial debugging.
278 * This allows debug messages to be output 277 * This allows debug messages to be output
diff --git a/arch/arm/kernel/iwmmxt-notifier.c b/arch/arm/kernel/iwmmxt-notifier.c
new file mode 100644
index 000000000000..44a86c33796e
--- /dev/null
+++ b/arch/arm/kernel/iwmmxt-notifier.c
@@ -0,0 +1,64 @@
1/*
2 * linux/arch/arm/kernel/iwmmxt-notifier.c
3 *
4 * XScale iWMMXt (Concan) context switching and handling
5 *
6 * Initial code:
7 * Copyright (c) 2003, Intel Corporation
8 *
9 * Full lazy switching support, optimizations and more, by Nicolas Pitre
10 * Copyright (c) 2003-2004, MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/module.h>
18#include <linux/config.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/signal.h>
22#include <linux/sched.h>
23#include <linux/init.h>
24#include <asm/thread_notify.h>
25#include <asm/io.h>
26
27static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
28{
29 struct thread_info *thread = t;
30
31 switch (cmd) {
32 case THREAD_NOTIFY_FLUSH:
33 /*
34 * flush_thread() zeroes thread->fpstate, so no need
35 * to do anything here.
36 *
37 * FALLTHROUGH: Ensure we don't try to overwrite our newly
38 * initialised state information on the first fault.
39 */
40
41 case THREAD_NOTIFY_RELEASE:
42 iwmmxt_task_release(thread);
43 break;
44
45 case THREAD_NOTIFY_SWITCH:
46 iwmmxt_task_switch(thread);
47 break;
48 }
49
50 return NOTIFY_DONE;
51}
52
53static struct notifier_block iwmmxt_notifier_block = {
54 .notifier_call = iwmmxt_do,
55};
56
57static int __init iwmmxt_init(void)
58{
59 thread_register_notifier(&iwmmxt_notifier_block);
60
61 return 0;
62}
63
64late_initcall(iwmmxt_init);
diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S
index a3bae95e536c..b63b528f22a6 100644
--- a/arch/arm/kernel/iwmmxt.S
+++ b/arch/arm/kernel/iwmmxt.S
@@ -271,30 +271,27 @@ ENTRY(iwmmxt_task_restore)
271/* 271/*
272 * Concan handling on task switch 272 * Concan handling on task switch
273 * 273 *
274 * r0 = previous task_struct pointer (must be preserved) 274 * r0 = next thread_info pointer
275 * r1 = previous thread_info pointer
276 * r2 = next thread_info pointer (must be preserved)
277 * 275 *
278 * Called only from __switch_to with task preemption disabled. 276 * Called only from the iwmmxt notifier with task preemption disabled.
279 * No need to care about preserving r4 and above.
280 */ 277 */
281ENTRY(iwmmxt_task_switch) 278ENTRY(iwmmxt_task_switch)
282 279
283 mrc p15, 0, r4, c15, c1, 0 280 mrc p15, 0, r1, c15, c1, 0
284 tst r4, #0x3 @ CP0 and CP1 accessible? 281 tst r1, #0x3 @ CP0 and CP1 accessible?
285 bne 1f @ yes: block them for next task 282 bne 1f @ yes: block them for next task
286 283
287 ldr r5, =concan_owner 284 ldr r2, =concan_owner
288 add r6, r2, #TI_IWMMXT_STATE @ get next task Concan save area 285 add r3, r0, #TI_IWMMXT_STATE @ get next task Concan save area
289 ldr r5, [r5] @ get current Concan owner 286 ldr r2, [r2] @ get current Concan owner
290 teq r5, r6 @ next task owns it? 287 teq r2, r3 @ next task owns it?
291 movne pc, lr @ no: leave Concan disabled 288 movne pc, lr @ no: leave Concan disabled
292 289
2931: eor r4, r4, #3 @ flip Concan access 2901: eor r1, r1, #3 @ flip Concan access
294 mcr p15, 0, r4, c15, c1, 0 291 mcr p15, 0, r1, c15, c1, 0
295 292
296 mrc p15, 0, r4, c2, c0, 0 293 mrc p15, 0, r1, c2, c0, 0
297 sub pc, lr, r4, lsr #32 @ cpwait and return 294 sub pc, lr, r1, lsr #32 @ cpwait and return
298 295
299/* 296/*
300 * Remove Concan ownership of given task 297 * Remove Concan ownership of given task
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index c3258b763c5d..3079535afccd 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -352,9 +352,6 @@ void flush_thread(void)
352 memset(&thread->fpstate, 0, sizeof(union fp_state)); 352 memset(&thread->fpstate, 0, sizeof(union fp_state));
353 353
354 thread_notify(THREAD_NOTIFY_FLUSH, thread); 354 thread_notify(THREAD_NOTIFY_FLUSH, thread);
355#if defined(CONFIG_IWMMXT)
356 iwmmxt_task_release(thread);
357#endif
358} 355}
359 356
360void release_thread(struct task_struct *dead_task) 357void release_thread(struct task_struct *dead_task)
@@ -362,9 +359,6 @@ void release_thread(struct task_struct *dead_task)
362 struct thread_info *thread = task_thread_info(dead_task); 359 struct thread_info *thread = task_thread_info(dead_task);
363 360
364 thread_notify(THREAD_NOTIFY_RELEASE, thread); 361 thread_notify(THREAD_NOTIFY_RELEASE, thread);
365#if defined(CONFIG_IWMMXT)
366 iwmmxt_task_release(thread);
367#endif
368} 362}
369 363
370asmlinkage void ret_from_fork(void) __asm__("ret_from_fork"); 364asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 7447a1987322..7d6a516c0b9f 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -344,9 +344,9 @@ static void __init setup_processor(void)
344 cpu_cache = *list->cache; 344 cpu_cache = *list->cache;
345#endif 345#endif
346 346
347 printk("CPU: %s [%08x] revision %d (ARMv%s)\n", 347 printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08x\n",
348 cpu_name, processor_id, (int)processor_id & 15, 348 cpu_name, processor_id, (int)processor_id & 15,
349 proc_arch[cpu_architecture()]); 349 proc_arch[cpu_architecture()], cr_alignment);
350 350
351 sprintf(system_utsname.machine, "%s%c", list->arch_name, ENDIANNESS); 351 sprintf(system_utsname.machine, "%s%c", list->arch_name, ENDIANNESS);
352 sprintf(elf_platform, "%s%c", list->elf_name, ENDIANNESS); 352 sprintf(elf_platform, "%s%c", list->elf_name, ENDIANNESS);
diff --git a/arch/arm/mach-at91rm9200/Kconfig b/arch/arm/mach-at91rm9200/Kconfig
index 70d402f76ce5..2f85e8693b1b 100644
--- a/arch/arm/mach-at91rm9200/Kconfig
+++ b/arch/arm/mach-at91rm9200/Kconfig
@@ -1,6 +1,21 @@
1if ARCH_AT91RM9200 1if ARCH_AT91
2
3menu "Atmel AT91 System-on-Chip"
4
5comment "Atmel AT91 Processors"
6
7config ARCH_AT91RM9200
8 bool "AT91RM9200"
2 9
3menu "AT91RM9200 Implementations" 10config ARCH_AT91SAM9260
11 bool "AT91SAM9260"
12
13config ARCH_AT91SAM9261
14 bool "AT91SAM9261"
15
16# ----------------------------------------------------------
17
18if ARCH_AT91RM9200
4 19
5comment "AT91RM9200 Board Type" 20comment "AT91RM9200 Board Type"
6 21
@@ -8,58 +23,87 @@ config MACH_ONEARM
8 bool "Ajeco 1ARM Single Board Computer" 23 bool "Ajeco 1ARM Single Board Computer"
9 depends on ARCH_AT91RM9200 24 depends on ARCH_AT91RM9200
10 help 25 help
11 Select this if you are using Ajeco's 1ARM Single Board Computer 26 Select this if you are using Ajeco's 1ARM Single Board Computer.
27 <http://www.ajeco.fi/products.htm>
12 28
13config ARCH_AT91RM9200DK 29config ARCH_AT91RM9200DK
14 bool "Atmel AT91RM9200-DK Development board" 30 bool "Atmel AT91RM9200-DK Development board"
15 depends on ARCH_AT91RM9200 31 depends on ARCH_AT91RM9200
16 help 32 help
17 Select this if you are using Atmel's AT91RM9200-DK Development board 33 Select this if you are using Atmel's AT91RM9200-DK Development board.
34 (Discontinued)
35
18 36
19config MACH_AT91RM9200EK 37config MACH_AT91RM9200EK
20 bool "Atmel AT91RM9200-EK Evaluation Kit" 38 bool "Atmel AT91RM9200-EK Evaluation Kit"
21 depends on ARCH_AT91RM9200 39 depends on ARCH_AT91RM9200
22 help 40 help
23 Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit 41 Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit.
42 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507>
24 43
25config MACH_CSB337 44config MACH_CSB337
26 bool "Cogent CSB337 board" 45 bool "Cogent CSB337"
27 depends on ARCH_AT91RM9200 46 depends on ARCH_AT91RM9200
28 help 47 help
29 Select this if you are using Cogent's CSB337 board 48 Select this if you are using Cogent's CSB337 board.
49 <http://www.cogcomp.com/csb_csb337.htm>
30 50
31config MACH_CSB637 51config MACH_CSB637
32 bool "Cogent CSB637 board" 52 bool "Cogent CSB637"
33 depends on ARCH_AT91RM9200 53 depends on ARCH_AT91RM9200
34 help 54 help
35 Select this if you are using Cogent's CSB637 board 55 Select this if you are using Cogent's CSB637 board.
56 <http://www.cogcomp.com/csb_csb637.htm>
36 57
37config MACH_CARMEVA 58config MACH_CARMEVA
38 bool "Conitec's ARM&EVA" 59 bool "Conitec ARM&EVA"
39 depends on ARCH_AT91RM9200 60 depends on ARCH_AT91RM9200
40 help 61 help
41 Select this if you are using Conitec's AT91RM9200-MCU-Module 62 Select this if you are using Conitec's AT91RM9200-MCU-Module.
63 <http://www.conitec.net/english/linuxboard.htm>
42 64
43config MACH_KB9200 65config MACH_ATEB9200
44 bool "KwikByte's KB920x" 66 bool "Embest ATEB9200"
45 depends on ARCH_AT91RM9200 67 depends on ARCH_AT91RM9200
46 help 68 help
47 Select this if you are using KwikByte's KB920x board 69 Select this if you are using Embest's ATEB9200 board.
70 <http://www.embedinfo.com/english/product/ATEB9200.asp>
48 71
49config MACH_ATEB9200 72config MACH_KB9200
50 bool "Embest's ATEB9200" 73 bool "KwikByte KB920x"
51 depends on ARCH_AT91RM9200 74 depends on ARCH_AT91RM9200
52 help 75 help
53 Select this if you are using Embest's ATEB9200 board 76 Select this if you are using KwikByte's KB920x board.
77 <http://kwikbyte.com/KB9202_description_new.htm>
54 78
55config MACH_KAFA 79config MACH_KAFA
56 bool "Sperry-Sun KAFA board" 80 bool "Sperry-Sun KAFA board"
57 depends on ARCH_AT91RM9200 81 depends on ARCH_AT91RM9200
58 help 82 help
59 Select this if you are using Sperry-Sun's KAFA board 83 Select this if you are using Sperry-Sun's KAFA board.
84
85endif
86
87# ----------------------------------------------------------
88
89if ARCH_AT91SAM9260
90
91comment "AT91SAM9260 Board Type"
92
93endif
94
95# ----------------------------------------------------------
96
97if ARCH_AT91SAM9261
98
99comment "AT91SAM9261 Board Type"
100
101endif
102
60 103
104# ----------------------------------------------------------
61 105
62comment "AT91RM9200 Feature Selections" 106comment "AT91 Feature Selections"
63 107
64config AT91_PROGRAMMABLE_CLOCKS 108config AT91_PROGRAMMABLE_CLOCKS
65 bool "Programmable Clocks" 109 bool "Programmable Clocks"
diff --git a/arch/arm/mach-at91rm9200/Makefile b/arch/arm/mach-at91rm9200/Makefile
index 82db957322df..c174805c24e5 100644
--- a/arch/arm/mach-at91rm9200/Makefile
+++ b/arch/arm/mach-at91rm9200/Makefile
@@ -2,14 +2,19 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := clock.o irq.o time.o gpio.o common.o devices.o 5obj-y := clock.o irq.o gpio.o devices.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
9 9
10obj-$(CONFIG_PM) += pm.o 10obj-$(CONFIG_PM) += pm.o
11 11
12# Board-specific support 12# CPU-specific support
13obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o
14obj-$(CONFIG_ARCH_AT91SAM9260) +=
15obj-$(CONFIG_ARCH_AT91SAM9261) +=
16
17# AT91RM9200 Board-specific support
13obj-$(CONFIG_MACH_ONEARM) += board-1arm.o 18obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
14obj-$(CONFIG_ARCH_AT91RM9200DK) += board-dk.o 19obj-$(CONFIG_ARCH_AT91RM9200DK) += board-dk.o
15obj-$(CONFIG_MACH_AT91RM9200EK) += board-ek.o 20obj-$(CONFIG_MACH_AT91RM9200EK) += board-ek.o
@@ -20,6 +25,10 @@ obj-$(CONFIG_MACH_KB9200) += board-kb9202.o
20obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o 25obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o
21obj-$(CONFIG_MACH_KAFA) += board-kafa.o 26obj-$(CONFIG_MACH_KAFA) += board-kafa.o
22 27
28# AT91SAM9260 board-specific support
29
30# AT91SAM9261 board-specific support
31
23# LEDs support 32# LEDs support
24led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o 33led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o
25led-$(CONFIG_MACH_AT91RM9200EK) += leds.o 34led-$(CONFIG_MACH_AT91RM9200EK) += leds.o
diff --git a/arch/arm/mach-at91rm9200/common.c b/arch/arm/mach-at91rm9200/at91rm9200.c
index cc55f4c28d95..7e1d072bdd80 100644
--- a/arch/arm/mach-at91rm9200/common.c
+++ b/arch/arm/mach-at91rm9200/at91rm9200.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-at91rm9200/common.c 2 * arch/arm/mach-at91rm9200/at91rm9200.c
3 * 3 *
4 * Copyright (C) 2005 SAN People 4 * Copyright (C) 2005 SAN People
5 * 5 *
diff --git a/arch/arm/mach-at91rm9200/time.c b/arch/arm/mach-at91rm9200/at91rm9200_time.c
index f2f080350ccb..dc38e06ada63 100644
--- a/arch/arm/mach-at91rm9200/time.c
+++ b/arch/arm/mach-at91rm9200/at91rm9200_time.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-at91rm9200/time.c 2 * linux/arch/arm/mach-at91rm9200/at91rm9200_time.c
3 * 3 *
4 * Copyright (C) 2003 SAN People 4 * Copyright (C) 2003 SAN People
5 * Copyright (C) 2003 ATMEL 5 * Copyright (C) 2003 ATMEL
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index e15e4c54a253..f1b740083aee 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -9,12 +9,24 @@ config CRUNCH
9 9
10comment "EP93xx Platforms" 10comment "EP93xx Platforms"
11 11
12config MACH_EDB9302
13 bool "Support Cirrus Logic EDB9302"
14 help
15 Say 'Y' here if you want your kernel to support the Cirrus
16 Logic EDB9302 Evaluation Board.
17
12config MACH_EDB9315 18config MACH_EDB9315
13 bool "Support Cirrus Logic EDB9315" 19 bool "Support Cirrus Logic EDB9315"
14 help 20 help
15 Say 'Y' here if you want your kernel to support the Cirrus 21 Say 'Y' here if you want your kernel to support the Cirrus
16 Logic EDB9315 Evaluation Board. 22 Logic EDB9315 Evaluation Board.
17 23
24config MACH_EDB9315A
25 bool "Support Cirrus Logic EDB9315A"
26 help
27 Say 'Y' here if you want your kernel to support the Cirrus
28 Logic EDB9315A Evaluation Board.
29
18config MACH_GESBC9312 30config MACH_GESBC9312
19 bool "Support Glomation GESBC-9312-sx" 31 bool "Support Glomation GESBC-9312-sx"
20 help 32 help
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index dfa7e2e8a18b..1f5a6b0487ee 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -6,6 +6,8 @@ obj-m :=
6obj-n := 6obj-n :=
7obj- := 7obj- :=
8 8
9obj-$(CONFIG_MACH_EDB9302) += edb9302.o
9obj-$(CONFIG_MACH_EDB9315) += edb9315.o 10obj-$(CONFIG_MACH_EDB9315) += edb9315.o
11obj-$(CONFIG_MACH_EDB9315A) += edb9315a.o
10obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o 12obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o
11obj-$(CONFIG_MACH_TS72XX) += ts72xx.o 13obj-$(CONFIG_MACH_TS72XX) += ts72xx.o
diff --git a/arch/arm/mach-ep93xx/edb9302.c b/arch/arm/mach-ep93xx/edb9302.c
new file mode 100644
index 000000000000..62a8efd23256
--- /dev/null
+++ b/arch/arm/mach-ep93xx/edb9302.c
@@ -0,0 +1,62 @@
1/*
2 * arch/arm/mach-ep93xx/edb9302.c
3 * Cirrus Logic EDB9302 support.
4 *
5 * Copyright (C) 2006 George Kashperko <george@chas.com.ua>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or (at
10 * your option) any later version.
11 */
12
13#include <linux/config.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/mm.h>
17#include <linux/sched.h>
18#include <linux/interrupt.h>
19#include <linux/ioport.h>
20#include <linux/mtd/physmap.h>
21#include <linux/platform_device.h>
22#include <asm/io.h>
23#include <asm/hardware.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26
27static struct physmap_flash_data edb9302_flash_data = {
28 .width = 2,
29};
30
31static struct resource edb9302_flash_resource = {
32 .start = 0x60000000,
33 .end = 0x60ffffff,
34 .flags = IORESOURCE_MEM,
35};
36
37static struct platform_device edb9302_flash = {
38 .name = "physmap-flash",
39 .id = 0,
40 .dev = {
41 .platform_data = &edb9302_flash_data,
42 },
43 .num_resources = 1,
44 .resource = &edb9302_flash_resource,
45};
46
47static void __init edb9302_init_machine(void)
48{
49 ep93xx_init_devices();
50 platform_device_register(&edb9302_flash);
51}
52
53MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
54 /* Maintainer: George Kashperko <george@chas.com.ua> */
55 .phys_io = EP93XX_APB_PHYS_BASE,
56 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
57 .boot_params = 0x00000100,
58 .map_io = ep93xx_map_io,
59 .init_irq = ep93xx_init_irq,
60 .timer = &ep93xx_timer,
61 .init_machine = edb9302_init_machine,
62MACHINE_END
diff --git a/arch/arm/mach-ep93xx/edb9315a.c b/arch/arm/mach-ep93xx/edb9315a.c
new file mode 100644
index 000000000000..bfefdaa8f794
--- /dev/null
+++ b/arch/arm/mach-ep93xx/edb9315a.c
@@ -0,0 +1,62 @@
1/*
2 * arch/arm/mach-ep93xx/edb9315a.c
3 * Cirrus Logic EDB9315A support.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or (at
10 * your option) any later version.
11 */
12
13#include <linux/config.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/mm.h>
17#include <linux/sched.h>
18#include <linux/interrupt.h>
19#include <linux/ioport.h>
20#include <linux/mtd/physmap.h>
21#include <linux/platform_device.h>
22#include <asm/io.h>
23#include <asm/hardware.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26
27static struct physmap_flash_data edb9315a_flash_data = {
28 .width = 2,
29};
30
31static struct resource edb9315a_flash_resource = {
32 .start = 0x60000000,
33 .end = 0x60ffffff,
34 .flags = IORESOURCE_MEM,
35};
36
37static struct platform_device edb9315a_flash = {
38 .name = "physmap-flash",
39 .id = 0,
40 .dev = {
41 .platform_data = &edb9315a_flash_data,
42 },
43 .num_resources = 1,
44 .resource = &edb9315a_flash_resource,
45};
46
47static void __init edb9315a_init_machine(void)
48{
49 ep93xx_init_devices();
50 platform_device_register(&edb9315a_flash);
51}
52
53MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
54 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
55 .phys_io = EP93XX_APB_PHYS_BASE,
56 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
57 .boot_params = 0xc0000100,
58 .map_io = ep93xx_map_io,
59 .init_irq = ep93xx_init_irq,
60 .timer = &ep93xx_timer,
61 .init_machine = edb9315a_init_machine,
62MACHINE_END
diff --git a/arch/arm/mach-iop3xx/Kconfig b/arch/arm/mach-iop3xx/Kconfig
index 2bfe8c729f9f..4422f2388607 100644
--- a/arch/arm/mach-iop3xx/Kconfig
+++ b/arch/arm/mach-iop3xx/Kconfig
@@ -30,12 +30,15 @@ config MACH_IQ80332
30 select ARCH_IOP331 30 select ARCH_IOP331
31 help 31 help
32 Say Y here if you want to run your kernel on the Intel IQ80332 32 Say Y here if you want to run your kernel on the Intel IQ80332
33 evaluation kit for the IOP332 chipset 33 evaluation kit for the IOP332 chipset.
34 34
35config ARCH_EP80219 35config ARCH_EP80219
36 bool "Enable support for EP80219" 36 bool "Enable support for EP80219"
37 select ARCH_IOP321 37 select ARCH_IOP321
38 select ARCH_IQ31244 38 select ARCH_IQ31244
39 help
40 Say Y here if you want to run your kernel on the Intel EP80219
41 evaluation kit for the Intel 80219 chipset (a IOP321 variant).
39 42
40# Which IOP variant are we running? 43# Which IOP variant are we running?
41config ARCH_IOP321 44config ARCH_IOP321
@@ -56,8 +59,8 @@ config IOP331_STEPD
56 bool "Chip stepping D of the IOP80331 processor or IOP80333" 59 bool "Chip stepping D of the IOP80331 processor or IOP80333"
57 depends on (ARCH_IOP331) 60 depends on (ARCH_IOP331)
58 help 61 help
59 Say Y here if you have StepD of the IOP80331 or IOP8033 62 Say Y here if you have StepD of the IOP80331 or IOP8033
60 based platforms. 63 based platforms.
61 64
62endmenu 65endmenu
63endif 66endif
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index f8d716ccc1df..d135568dc9e7 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -62,6 +62,13 @@ config MACH_OMAP_PERSEUS2
62 Support for TI OMAP 730 Perseus2 board. Say Y here if you have such 62 Support for TI OMAP 730 Perseus2 board. Say Y here if you have such
63 a board. 63 a board.
64 64
65config MACH_OMAP_FSAMPLE
66 bool "TI F-Sample"
67 depends on ARCH_OMAP1 && ARCH_OMAP730
68 help
69 Support for TI OMAP 850 F-Sample board. Say Y here if you have such
70 a board.
71
65config MACH_VOICEBLUE 72config MACH_VOICEBLUE
66 bool "Voiceblue" 73 bool "Voiceblue"
67 depends on ARCH_OMAP1 && ARCH_OMAP15XX 74 depends on ARCH_OMAP1 && ARCH_OMAP15XX
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 9ea719550ad3..7165f74f78da 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o
17obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o 17obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o
18obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o 18obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
19obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o 19obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o
20obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o
20obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o 21obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o
21obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o 22obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o
22obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o 23obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 73df32aac4c4..8437d065ada5 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -80,8 +80,15 @@ static struct omap_uart_config ams_delta_uart_config __initdata = {
80 .enabled_uarts = 1, 80 .enabled_uarts = 1,
81}; 81};
82 82
83static struct omap_usb_config ams_delta_usb_config __initdata = {
84 .register_host = 1,
85 .hmc_mode = 16,
86 .pins[0] = 2,
87};
88
83static struct omap_board_config_kernel ams_delta_config[] = { 89static struct omap_board_config_kernel ams_delta_config[] = {
84 { OMAP_TAG_UART, &ams_delta_uart_config }, 90 { OMAP_TAG_UART, &ams_delta_uart_config },
91 { OMAP_TAG_USB, &ams_delta_usb_config },
85}; 92};
86 93
87static struct platform_device ams_delta_led_device = { 94static struct platform_device ams_delta_led_device = {
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
new file mode 100644
index 000000000000..c753a3c5aadd
--- /dev/null
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -0,0 +1,319 @@
1/*
2 * linux/arch/arm/mach-omap1/board-fsample.c
3 *
4 * Modified from board-perseus2.c
5 *
6 * Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
7 * Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/delay.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h>
21#include <linux/input.h>
22
23#include <asm/hardware.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/flash.h>
27#include <asm/mach/map.h>
28
29#include <asm/arch/tc.h>
30#include <asm/arch/gpio.h>
31#include <asm/arch/mux.h>
32#include <asm/arch/fpga.h>
33#include <asm/arch/keypad.h>
34#include <asm/arch/common.h>
35#include <asm/arch/board.h>
36#include <asm/arch/board-fsample.h>
37
38static int fsample_keymap[] = {
39 KEY(0,0,KEY_UP),
40 KEY(0,1,KEY_RIGHT),
41 KEY(0,2,KEY_LEFT),
42 KEY(0,3,KEY_DOWN),
43 KEY(0,4,KEY_CENTER),
44 KEY(0,5,KEY_0_5),
45 KEY(1,0,KEY_SOFT2),
46 KEY(1,1,KEY_SEND),
47 KEY(1,2,KEY_END),
48 KEY(1,3,KEY_VOLUMEDOWN),
49 KEY(1,4,KEY_VOLUMEUP),
50 KEY(1,5,KEY_RECORD),
51 KEY(2,0,KEY_SOFT1),
52 KEY(2,1,KEY_3),
53 KEY(2,2,KEY_6),
54 KEY(2,3,KEY_9),
55 KEY(2,4,KEY_SHARP),
56 KEY(2,5,KEY_2_5),
57 KEY(3,0,KEY_BACK),
58 KEY(3,1,KEY_2),
59 KEY(3,2,KEY_5),
60 KEY(3,3,KEY_8),
61 KEY(3,4,KEY_0),
62 KEY(3,5,KEY_HEADSETHOOK),
63 KEY(4,0,KEY_HOME),
64 KEY(4,1,KEY_1),
65 KEY(4,2,KEY_4),
66 KEY(4,3,KEY_7),
67 KEY(4,4,KEY_STAR),
68 KEY(4,5,KEY_POWER),
69 0
70};
71
72static struct resource smc91x_resources[] = {
73 [0] = {
74 .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
75 .end = H2P2_DBG_FPGA_ETHR_START + 0xf,
76 .flags = IORESOURCE_MEM,
77 },
78 [1] = {
79 .start = INT_730_MPU_EXT_NIRQ,
80 .end = 0,
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85static struct mtd_partition nor_partitions[] = {
86 /* bootloader (U-Boot, etc) in first sector */
87 {
88 .name = "bootloader",
89 .offset = 0,
90 .size = SZ_128K,
91 .mask_flags = MTD_WRITEABLE, /* force read-only */
92 },
93 /* bootloader params in the next sector */
94 {
95 .name = "params",
96 .offset = MTDPART_OFS_APPEND,
97 .size = SZ_128K,
98 .mask_flags = 0,
99 },
100 /* kernel */
101 {
102 .name = "kernel",
103 .offset = MTDPART_OFS_APPEND,
104 .size = SZ_2M,
105 .mask_flags = 0
106 },
107 /* rest of flash is a file system */
108 {
109 .name = "rootfs",
110 .offset = MTDPART_OFS_APPEND,
111 .size = MTDPART_SIZ_FULL,
112 .mask_flags = 0
113 },
114};
115
116static struct flash_platform_data nor_data = {
117 .map_name = "cfi_probe",
118 .width = 2,
119 .parts = nor_partitions,
120 .nr_parts = ARRAY_SIZE(nor_partitions),
121};
122
123static struct resource nor_resource = {
124 .start = OMAP_CS0_PHYS,
125 .end = OMAP_CS0_PHYS + SZ_32M - 1,
126 .flags = IORESOURCE_MEM,
127};
128
129static struct platform_device nor_device = {
130 .name = "omapflash",
131 .id = 0,
132 .dev = {
133 .platform_data = &nor_data,
134 },
135 .num_resources = 1,
136 .resource = &nor_resource,
137};
138
139static struct nand_platform_data nand_data = {
140 .options = NAND_SAMSUNG_LP_OPTIONS,
141};
142
143static struct resource nand_resource = {
144 .start = OMAP_CS3_PHYS,
145 .end = OMAP_CS3_PHYS + SZ_4K - 1,
146 .flags = IORESOURCE_MEM,
147};
148
149static struct platform_device nand_device = {
150 .name = "omapnand",
151 .id = 0,
152 .dev = {
153 .platform_data = &nand_data,
154 },
155 .num_resources = 1,
156 .resource = &nand_resource,
157};
158
159static struct platform_device smc91x_device = {
160 .name = "smc91x",
161 .id = 0,
162 .num_resources = ARRAY_SIZE(smc91x_resources),
163 .resource = smc91x_resources,
164};
165
166static struct resource kp_resources[] = {
167 [0] = {
168 .start = INT_730_MPUIO_KEYPAD,
169 .end = INT_730_MPUIO_KEYPAD,
170 .flags = IORESOURCE_IRQ,
171 },
172};
173
174static struct omap_kp_platform_data kp_data = {
175 .rows = 8,
176 .cols = 8,
177 .keymap = fsample_keymap,
178};
179
180static struct platform_device kp_device = {
181 .name = "omap-keypad",
182 .id = -1,
183 .dev = {
184 .platform_data = &kp_data,
185 },
186 .num_resources = ARRAY_SIZE(kp_resources),
187 .resource = kp_resources,
188};
189
190static struct platform_device lcd_device = {
191 .name = "lcd_p2",
192 .id = -1,
193};
194
195static struct platform_device *devices[] __initdata = {
196 &nor_device,
197 &nand_device,
198 &smc91x_device,
199 &kp_device,
200 &lcd_device,
201};
202
203#define P2_NAND_RB_GPIO_PIN 62
204
205static int nand_dev_ready(struct nand_platform_data *data)
206{
207 return omap_get_gpio_datain(P2_NAND_RB_GPIO_PIN);
208}
209
210static struct omap_uart_config fsample_uart_config __initdata = {
211 .enabled_uarts = ((1 << 0) | (1 << 1)),
212};
213
214static struct omap_lcd_config fsample_lcd_config __initdata = {
215 .ctrl_name = "internal",
216};
217
218static struct omap_board_config_kernel fsample_config[] = {
219 { OMAP_TAG_UART, &fsample_uart_config },
220 { OMAP_TAG_LCD, &fsample_lcd_config },
221};
222
223static void __init omap_fsample_init(void)
224{
225 if (!(omap_request_gpio(P2_NAND_RB_GPIO_PIN)))
226 nand_data.dev_ready = nand_dev_ready;
227
228 omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
229 omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
230
231 platform_add_devices(devices, ARRAY_SIZE(devices));
232
233 omap_board_config = fsample_config;
234 omap_board_config_size = ARRAY_SIZE(fsample_config);
235 omap_serial_init();
236}
237
238static void __init fsample_init_smc91x(void)
239{
240 fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
241 mdelay(50);
242 fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
243 H2P2_DBG_FPGA_LAN_RESET);
244 mdelay(50);
245}
246
247void omap_fsample_init_irq(void)
248{
249 omap1_init_common_hw();
250 omap_init_irq();
251 omap_gpio_init();
252 fsample_init_smc91x();
253}
254
255/* Only FPGA needs to be mapped here. All others are done with ioremap */
256static struct map_desc omap_fsample_io_desc[] __initdata = {
257 {
258 .virtual = H2P2_DBG_FPGA_BASE,
259 .pfn = __phys_to_pfn(H2P2_DBG_FPGA_START),
260 .length = H2P2_DBG_FPGA_SIZE,
261 .type = MT_DEVICE
262 },
263 {
264 .virtual = FSAMPLE_CPLD_BASE,
265 .pfn = __phys_to_pfn(FSAMPLE_CPLD_START),
266 .length = FSAMPLE_CPLD_SIZE,
267 .type = MT_DEVICE
268 }
269};
270
271static void __init omap_fsample_map_io(void)
272{
273 omap1_map_common_io();
274 iotable_init(omap_fsample_io_desc,
275 ARRAY_SIZE(omap_fsample_io_desc));
276
277 /* Early, board-dependent init */
278
279 /*
280 * Hold GSM Reset until needed
281 */
282 omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);
283
284 /*
285 * UARTs -> done automagically by 8250 driver
286 */
287
288 /*
289 * CSx timings, GPIO Mux ... setup
290 */
291
292 /* Flash: CS0 timings setup */
293 omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0);
294 omap_writel(0x00000088, OMAP730_FLASH_ACFG_0);
295
296 /*
297 * Ethernet support through the debug board
298 * CS1 timings setup
299 */
300 omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1);
301 omap_writel(0x00000000, OMAP730_FLASH_ACFG_1);
302
303 /*
304 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
305 * It is used as the Ethernet controller interrupt
306 */
307 omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9);
308}
309
310MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
311/* Maintainer: Brian Swetland <swetland@google.com> */
312 .phys_io = 0xfff00000,
313 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
314 .boot_params = 0x10000100,
315 .map_io = omap_fsample_map_io,
316 .init_irq = omap_fsample_init_irq,
317 .init_machine = omap_fsample_init,
318 .timer = &omap_timer,
319MACHINE_END
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index e90c137a4cf3..4cbc62db5b5d 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -37,6 +37,8 @@
37#include <asm/arch/usb.h> 37#include <asm/arch/usb.h>
38#include <asm/arch/keypad.h> 38#include <asm/arch/keypad.h>
39#include <asm/arch/common.h> 39#include <asm/arch/common.h>
40#include <asm/arch/mcbsp.h>
41#include <asm/arch/omap-alsa.h>
40 42
41static int innovator_keymap[] = { 43static int innovator_keymap[] = {
42 KEY(0, 0, KEY_F1), 44 KEY(0, 0, KEY_F1),
@@ -112,6 +114,42 @@ static struct platform_device innovator_flash_device = {
112 .resource = &innovator_flash_resource, 114 .resource = &innovator_flash_resource,
113}; 115};
114 116
117#define DEFAULT_BITPERSAMPLE 16
118
119static struct omap_mcbsp_reg_cfg mcbsp_regs = {
120 .spcr2 = FREE | FRST | GRST | XRST | XINTM(3),
121 .spcr1 = RINTM(3) | RRST,
122 .rcr2 = RPHASE | RFRLEN2(OMAP_MCBSP_WORD_8) |
123 RWDLEN2(OMAP_MCBSP_WORD_16) | RDATDLY(0),
124 .rcr1 = RFRLEN1(OMAP_MCBSP_WORD_8) | RWDLEN1(OMAP_MCBSP_WORD_16),
125 .xcr2 = XPHASE | XFRLEN2(OMAP_MCBSP_WORD_8) |
126 XWDLEN2(OMAP_MCBSP_WORD_16) | XDATDLY(0) | XFIG,
127 .xcr1 = XFRLEN1(OMAP_MCBSP_WORD_8) | XWDLEN1(OMAP_MCBSP_WORD_16),
128 .srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1),
129 .srgr2 = GSYNC | CLKSP | FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1),
130 /*.pcr0 = FSXM | FSRM | CLKXM | CLKRM | CLKXP | CLKRP,*/ /* mcbsp: master */
131 .pcr0 = CLKXP | CLKRP, /* mcbsp: slave */
132};
133
134static struct omap_alsa_codec_config alsa_config = {
135 .name = "OMAP Innovator AIC23",
136 .mcbsp_regs_alsa = &mcbsp_regs,
137 .codec_configure_dev = NULL, // aic23_configure,
138 .codec_set_samplerate = NULL, // aic23_set_samplerate,
139 .codec_clock_setup = NULL, // aic23_clock_setup,
140 .codec_clock_on = NULL, // aic23_clock_on,
141 .codec_clock_off = NULL, // aic23_clock_off,
142 .get_default_samplerate = NULL, // aic23_get_default_samplerate,
143};
144
145static struct platform_device innovator_mcbsp1_device = {
146 .name = "omap_alsa_mcbsp",
147 .id = 1,
148 .dev = {
149 .platform_data = &alsa_config,
150 },
151};
152
115static struct resource innovator_kp_resources[] = { 153static struct resource innovator_kp_resources[] = {
116 [0] = { 154 [0] = {
117 .start = INT_KEYBOARD, 155 .start = INT_KEYBOARD,
@@ -139,6 +177,10 @@ static struct platform_device innovator_kp_device = {
139 177
140#ifdef CONFIG_ARCH_OMAP15XX 178#ifdef CONFIG_ARCH_OMAP15XX
141 179
180#include <linux/spi/spi.h>
181#include <linux/spi/ads7846.h>
182
183
142/* Only FPGA needs to be mapped here. All others are done with ioremap */ 184/* Only FPGA needs to be mapped here. All others are done with ioremap */
143static struct map_desc innovator1510_io_desc[] __initdata = { 185static struct map_desc innovator1510_io_desc[] __initdata = {
144 { 186 {
@@ -174,13 +216,44 @@ static struct platform_device innovator1510_lcd_device = {
174 .id = -1, 216 .id = -1,
175}; 217};
176 218
219static struct platform_device innovator1510_spi_device = {
220 .name = "spi_inn1510",
221 .id = -1,
222};
223
177static struct platform_device *innovator1510_devices[] __initdata = { 224static struct platform_device *innovator1510_devices[] __initdata = {
178 &innovator_flash_device, 225 &innovator_flash_device,
179 &innovator1510_smc91x_device, 226 &innovator1510_smc91x_device,
227 &innovator_mcbsp1_device,
180 &innovator_kp_device, 228 &innovator_kp_device,
181 &innovator1510_lcd_device, 229 &innovator1510_lcd_device,
230 &innovator1510_spi_device,
182}; 231};
183 232
233static int innovator_get_pendown_state(void)
234{
235 return !(fpga_read(OMAP1510_FPGA_TOUCHSCREEN) & (1 << 5));
236}
237
238static const struct ads7846_platform_data innovator1510_ts_info = {
239 .model = 7846,
240 .vref_delay_usecs = 100, /* internal, no capacitor */
241 .x_plate_ohms = 419,
242 .y_plate_ohms = 486,
243 .get_pendown_state = innovator_get_pendown_state,
244};
245
246static struct spi_board_info __initdata innovator1510_boardinfo[] = { {
247 /* FPGA (bus "10") CS0 has an ads7846e */
248 .modalias = "ads7846",
249 .platform_data = &innovator1510_ts_info,
250 .irq = OMAP1510_INT_FPGA_TS,
251 .max_speed_hz = 120000 /* max sample rate at 3V */
252 * 26 /* command + data + overhead */,
253 .bus_num = 10,
254 .chip_select = 0,
255} };
256
184#endif /* CONFIG_ARCH_OMAP15XX */ 257#endif /* CONFIG_ARCH_OMAP15XX */
185 258
186#ifdef CONFIG_ARCH_OMAP16XX 259#ifdef CONFIG_ARCH_OMAP16XX
@@ -311,6 +384,8 @@ static void __init innovator_init(void)
311#ifdef CONFIG_ARCH_OMAP15XX 384#ifdef CONFIG_ARCH_OMAP15XX
312 if (cpu_is_omap1510()) { 385 if (cpu_is_omap1510()) {
313 platform_add_devices(innovator1510_devices, ARRAY_SIZE(innovator1510_devices)); 386 platform_add_devices(innovator1510_devices, ARRAY_SIZE(innovator1510_devices));
387 spi_register_board_info(innovator1510_boardinfo,
388 ARRAY_SIZE(innovator1510_boardinfo));
314 } 389 }
315#endif 390#endif
316#ifdef CONFIG_ARCH_OMAP16XX 391#ifdef CONFIG_ARCH_OMAP16XX
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 1160093e8ef6..e0711d23a6b0 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -33,7 +33,6 @@
33 33
34#include <linux/mtd/mtd.h> 34#include <linux/mtd/mtd.h>
35#include <linux/mtd/partitions.h> 35#include <linux/mtd/partitions.h>
36#include <linux/input.h>
37 36
38#include <asm/hardware.h> 37#include <asm/hardware.h>
39#include <asm/mach-types.h> 38#include <asm/mach-types.h>
@@ -45,25 +44,10 @@
45#include <asm/arch/usb.h> 44#include <asm/arch/usb.h>
46#include <asm/arch/mux.h> 45#include <asm/arch/mux.h>
47#include <asm/arch/tc.h> 46#include <asm/arch/tc.h>
48#include <asm/arch/keypad.h>
49#include <asm/arch/common.h> 47#include <asm/arch/common.h>
50#include <asm/arch/mcbsp.h> 48#include <asm/arch/mcbsp.h>
51#include <asm/arch/omap-alsa.h> 49#include <asm/arch/omap-alsa.h>
52 50
53static int osk_keymap[] = {
54 KEY(0, 0, KEY_F1),
55 KEY(0, 3, KEY_UP),
56 KEY(1, 1, KEY_LEFTCTRL),
57 KEY(1, 2, KEY_LEFT),
58 KEY(2, 0, KEY_SPACE),
59 KEY(2, 1, KEY_ESC),
60 KEY(2, 2, KEY_DOWN),
61 KEY(3, 2, KEY_ENTER),
62 KEY(3, 3, KEY_RIGHT),
63 0
64};
65
66
67static struct mtd_partition osk_partitions[] = { 51static struct mtd_partition osk_partitions[] = {
68 /* bootloader (U-Boot, etc) in first sector */ 52 /* bootloader (U-Boot, etc) in first sector */
69 { 53 {
@@ -181,48 +165,17 @@ static struct omap_alsa_codec_config alsa_config = {
181 165
182static struct platform_device osk5912_mcbsp1_device = { 166static struct platform_device osk5912_mcbsp1_device = {
183 .name = "omap_alsa_mcbsp", 167 .name = "omap_alsa_mcbsp",
184 .id = 1, 168 .id = 1,
185 .dev = { 169 .dev = {
186 .platform_data = &alsa_config, 170 .platform_data = &alsa_config,
187 }, 171 },
188}; 172};
189 173
190static struct resource osk5912_kp_resources[] = {
191 [0] = {
192 .start = INT_KEYBOARD,
193 .end = INT_KEYBOARD,
194 .flags = IORESOURCE_IRQ,
195 },
196};
197
198static struct omap_kp_platform_data osk_kp_data = {
199 .rows = 8,
200 .cols = 8,
201 .keymap = osk_keymap,
202};
203
204static struct platform_device osk5912_kp_device = {
205 .name = "omap-keypad",
206 .id = -1,
207 .dev = {
208 .platform_data = &osk_kp_data,
209 },
210 .num_resources = ARRAY_SIZE(osk5912_kp_resources),
211 .resource = osk5912_kp_resources,
212};
213
214static struct platform_device osk5912_lcd_device = {
215 .name = "lcd_osk",
216 .id = -1,
217};
218
219static struct platform_device *osk5912_devices[] __initdata = { 174static struct platform_device *osk5912_devices[] __initdata = {
220 &osk5912_flash_device, 175 &osk5912_flash_device,
221 &osk5912_smc91x_device, 176 &osk5912_smc91x_device,
222 &osk5912_cf_device, 177 &osk5912_cf_device,
223 &osk5912_mcbsp1_device, 178 &osk5912_mcbsp1_device,
224 &osk5912_kp_device,
225 &osk5912_lcd_device,
226}; 179};
227 180
228static void __init osk_init_smc91x(void) 181static void __init osk_init_smc91x(void)
@@ -276,18 +229,100 @@ static struct omap_uart_config osk_uart_config __initdata = {
276 .enabled_uarts = (1 << 0), 229 .enabled_uarts = (1 << 0),
277}; 230};
278 231
232#ifdef CONFIG_OMAP_OSK_MISTRAL
279static struct omap_lcd_config osk_lcd_config __initdata = { 233static struct omap_lcd_config osk_lcd_config __initdata = {
280 .ctrl_name = "internal", 234 .ctrl_name = "internal",
281}; 235};
236#endif
282 237
283static struct omap_board_config_kernel osk_config[] = { 238static struct omap_board_config_kernel osk_config[] = {
284 { OMAP_TAG_USB, &osk_usb_config }, 239 { OMAP_TAG_USB, &osk_usb_config },
285 { OMAP_TAG_UART, &osk_uart_config }, 240 { OMAP_TAG_UART, &osk_uart_config },
241#ifdef CONFIG_OMAP_OSK_MISTRAL
286 { OMAP_TAG_LCD, &osk_lcd_config }, 242 { OMAP_TAG_LCD, &osk_lcd_config },
243#endif
287}; 244};
288 245
289#ifdef CONFIG_OMAP_OSK_MISTRAL 246#ifdef CONFIG_OMAP_OSK_MISTRAL
290 247
248#include <linux/input.h>
249#include <linux/spi/spi.h>
250#include <linux/spi/ads7846.h>
251
252#include <asm/arch/keypad.h>
253
254static const int osk_keymap[] = {
255 /* KEY(col, row, code) */
256 KEY(0, 0, KEY_F1), /* SW4 */
257 KEY(0, 3, KEY_UP), /* (sw2/up) */
258 KEY(1, 1, KEY_LEFTCTRL), /* SW5 */
259 KEY(1, 2, KEY_LEFT), /* (sw2/left) */
260 KEY(2, 0, KEY_SPACE), /* SW3 */
261 KEY(2, 1, KEY_ESC), /* SW6 */
262 KEY(2, 2, KEY_DOWN), /* (sw2/down) */
263 KEY(3, 2, KEY_ENTER), /* (sw2/select) */
264 KEY(3, 3, KEY_RIGHT), /* (sw2/right) */
265 0
266};
267
268static struct omap_kp_platform_data osk_kp_data = {
269 .rows = 8,
270 .cols = 8,
271 .keymap = (int *) osk_keymap,
272};
273
274static struct resource osk5912_kp_resources[] = {
275 [0] = {
276 .start = INT_KEYBOARD,
277 .end = INT_KEYBOARD,
278 .flags = IORESOURCE_IRQ,
279 },
280};
281
282static struct platform_device osk5912_kp_device = {
283 .name = "omap-keypad",
284 .id = -1,
285 .dev = {
286 .platform_data = &osk_kp_data,
287 },
288 .num_resources = ARRAY_SIZE(osk5912_kp_resources),
289 .resource = osk5912_kp_resources,
290};
291
292static struct platform_device osk5912_lcd_device = {
293 .name = "lcd_osk",
294 .id = -1,
295};
296
297static struct platform_device *mistral_devices[] __initdata = {
298 &osk5912_kp_device,
299 &osk5912_lcd_device,
300};
301
302static int mistral_get_pendown_state(void)
303{
304 return !omap_get_gpio_datain(4);
305}
306
307static const struct ads7846_platform_data mistral_ts_info = {
308 .model = 7846,
309 .vref_delay_usecs = 100, /* internal, no capacitor */
310 .x_plate_ohms = 419,
311 .y_plate_ohms = 486,
312 .get_pendown_state = mistral_get_pendown_state,
313};
314
315static struct spi_board_info __initdata mistral_boardinfo[] = { {
316 /* MicroWire (bus 2) CS0 has an ads7846e */
317 .modalias = "ads7846",
318 .platform_data = &mistral_ts_info,
319 .irq = OMAP_GPIO_IRQ(4),
320 .max_speed_hz = 120000 /* max sample rate at 3V */
321 * 26 /* command + data + overhead */,
322 .bus_num = 2,
323 .chip_select = 0,
324} };
325
291#ifdef CONFIG_PM 326#ifdef CONFIG_PM
292static irqreturn_t 327static irqreturn_t
293osk_mistral_wake_interrupt(int irq, void *ignored, struct pt_regs *regs) 328osk_mistral_wake_interrupt(int irq, void *ignored, struct pt_regs *regs)
@@ -298,14 +333,18 @@ osk_mistral_wake_interrupt(int irq, void *ignored, struct pt_regs *regs)
298 333
299static void __init osk_mistral_init(void) 334static void __init osk_mistral_init(void)
300{ 335{
301 /* FIXME here's where to feed in framebuffer, touchpad, and 336 /* NOTE: we could actually tell if there's a Mistral board
302 * keyboard setup ... not in the drivers for those devices!
303 *
304 * NOTE: we could actually tell if there's a Mistral board
305 * attached, e.g. by trying to read something from the ads7846. 337 * attached, e.g. by trying to read something from the ads7846.
306 * But this is too early for that... 338 * But this arch_init() code is too early for that, since we
339 * can't talk to the ads or even the i2c eeprom.
307 */ 340 */
308 341
342 // omap_cfg_reg(P19_1610_GPIO6); // BUSY
343 omap_cfg_reg(P20_1610_GPIO4); // PENIRQ
344 set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING);
345 spi_register_board_info(mistral_boardinfo,
346 ARRAY_SIZE(mistral_boardinfo));
347
309 /* the sideways button (SW1) is for use as a "wakeup" button */ 348 /* the sideways button (SW1) is for use as a "wakeup" button */
310 omap_cfg_reg(N15_1610_MPUIO2); 349 omap_cfg_reg(N15_1610_MPUIO2);
311 if (omap_request_gpio(OMAP_MPUIO(2)) == 0) { 350 if (omap_request_gpio(OMAP_MPUIO(2)) == 0) {
@@ -329,6 +368,8 @@ static void __init osk_mistral_init(void)
329#endif 368#endif
330 } else 369 } else
331 printk(KERN_ERR "OSK+Mistral: wakeup button is awol\n"); 370 printk(KERN_ERR "OSK+Mistral: wakeup button is awol\n");
371
372 platform_add_devices(mistral_devices, ARRAY_SIZE(mistral_devices));
332} 373}
333#else 374#else
334static void __init osk_mistral_init(void) { } 375static void __init osk_mistral_init(void) { }
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 619db18144ea..f1958e882e86 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -1,3 +1,4 @@
1//kernel/linux-omap-fsample/arch/arm/mach-omap1/clock.c#2 - edit change 3808 (text)
1/* 2/*
2 * linux/arch/arm/mach-omap1/clock.c 3 * linux/arch/arm/mach-omap1/clock.c
3 * 4 *
@@ -20,6 +21,7 @@
20 21
21#include <asm/io.h> 22#include <asm/io.h>
22 23
24#include <asm/arch/cpu.h>
23#include <asm/arch/usb.h> 25#include <asm/arch/usb.h>
24#include <asm/arch/clock.h> 26#include <asm/arch/clock.h>
25#include <asm/arch/sram.h> 27#include <asm/arch/sram.h>
@@ -270,8 +272,12 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
270 /* 272 /*
271 * In most cases we should not need to reprogram DPLL. 273 * In most cases we should not need to reprogram DPLL.
272 * Reprogramming the DPLL is tricky, it must be done from SRAM. 274 * Reprogramming the DPLL is tricky, it must be done from SRAM.
275 * (on 730, bit 13 must always be 1)
273 */ 276 */
274 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); 277 if (cpu_is_omap730())
278 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
279 else
280 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
275 281
276 ck_dpll1.rate = ptr->pll_rate; 282 ck_dpll1.rate = ptr->pll_rate;
277 propagate_rate(&ck_dpll1); 283 propagate_rate(&ck_dpll1);
@@ -748,7 +754,7 @@ int __init omap1_clk_init(void)
748 printk(KERN_ERR "System frequencies not set. Check your config.\n"); 754 printk(KERN_ERR "System frequencies not set. Check your config.\n");
749 /* Guess sane values (60MHz) */ 755 /* Guess sane values (60MHz) */
750 omap_writew(0x2290, DPLL_CTL); 756 omap_writew(0x2290, DPLL_CTL);
751 omap_writew(0x1005, ARM_CKCTL); 757 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
752 ck_dpll1.rate = 60000000; 758 ck_dpll1.rate = 60000000;
753 propagate_rate(&ck_dpll1); 759 propagate_rate(&ck_dpll1);
754 } 760 }
@@ -761,13 +767,17 @@ int __init omap1_clk_init(void)
761 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, 767 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
762 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); 768 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
763 769
764#ifdef CONFIG_MACH_OMAP_PERSEUS2 770#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
765 /* Select slicer output as OMAP input clock */ 771 /* Select slicer output as OMAP input clock */
766 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL); 772 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
767#endif 773#endif
768 774
769 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ 775 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
770 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); 776 /* (on 730, bit 13 must not be cleared) */
777 if (cpu_is_omap730())
778 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
779 else
780 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
771 781
772 /* Put DSP/MPUI into reset until needed */ 782 /* Put DSP/MPUI into reset until needed */
773 omap_writew(0, ARM_RSTCT1); 783 omap_writew(0, ARM_RSTCT1);
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index ddf6b07dc9c7..1b4e1d57afb1 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -1,3 +1,4 @@
1//kernel/linux-omap-fsample/arch/arm/mach-omap1/pm.c#3 - integrate change 4545 (text)
1/* 2/*
2 * linux/arch/arm/mach-omap1/pm.c 3 * linux/arch/arm/mach-omap1/pm.c
3 * 4 *
@@ -50,6 +51,7 @@
50#include <asm/mach/irq.h> 51#include <asm/mach/irq.h>
51#include <asm/mach-types.h> 52#include <asm/mach-types.h>
52 53
54#include <asm/arch/cpu.h>
53#include <asm/arch/irqs.h> 55#include <asm/arch/irqs.h>
54#include <asm/arch/clock.h> 56#include <asm/arch/clock.h>
55#include <asm/arch/sram.h> 57#include <asm/arch/sram.h>
@@ -326,8 +328,9 @@ void omap_pm_suspend(void)
326 /* stop DSP */ 328 /* stop DSP */
327 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1); 329 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
328 330
329 /* shut down dsp_ck */ 331 /* shut down dsp_ck */
330 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); 332 if (!cpu_is_omap730())
333 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
331 334
332 /* temporarily enabling api_ck to access DSP registers */ 335 /* temporarily enabling api_ck to access DSP registers */
333 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); 336 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index c2d3205bc592..a01f0efdae14 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -93,7 +93,7 @@ static inline unsigned long long cycles_2_ns(unsigned long long cyc)
93 * will break. On P2, the timer count rate is 6.5 MHz after programming PTV 93 * will break. On P2, the timer count rate is 6.5 MHz after programming PTV
94 * with 0. This divides the 13MHz input by 2, and is undocumented. 94 * with 0. This divides the 13MHz input by 2, and is undocumented.
95 */ 95 */
96#ifdef CONFIG_MACH_OMAP_PERSEUS2 96#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
97/* REVISIT: This ifdef construct should be replaced by a query to clock 97/* REVISIT: This ifdef construct should be replaced by a query to clock
98 * framework to see if timer base frequency is 12.0, 13.0 or 19.2 MHz. 98 * framework to see if timer base frequency is 12.0, 13.0 or 19.2 MHz.
99 */ 99 */
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 537dd2e6d380..aab97ccf1e63 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -8,6 +8,7 @@ config ARCH_OMAP24XX
8config ARCH_OMAP2420 8config ARCH_OMAP2420
9 bool "OMAP2420 support" 9 bool "OMAP2420 support"
10 depends on ARCH_OMAP24XX 10 depends on ARCH_OMAP24XX
11 select OMAP_DM_TIMER
11 12
12comment "OMAP Board Type" 13comment "OMAP Board Type"
13 depends on ARCH_OMAP2 14 depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 111eaa64258f..266d88e77bdc 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,12 +3,13 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o serial.o 6obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \
7 serial.o gpmc.o
7 8
8obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o 9obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o
9 10
10# Power Management 11# Power Management
11obj-$(CONFIG_PM) += pm.o sleep.o 12obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o
12 13
13# Specific board support 14# Specific board support
14obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o 15obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 7edf0f69da1e..d1b648a4efbf 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -659,26 +659,35 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
659 659
660 /* Isolate control register */ 660 /* Isolate control register */
661 div_sel = (SRC_RATE_SEL_MASK & clk->flags); 661 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
662 div_off = clk->src_offset; 662 div_off = clk->rate_offset;
663 663
664 validrate = omap2_clksel_round_rate(clk, rate, &new_div); 664 validrate = omap2_clksel_round_rate(clk, rate, &new_div);
665 if(validrate != rate) 665 if (validrate != rate)
666 return(ret); 666 return(ret);
667 667
668 field_val = omap2_get_clksel(&div_sel, &field_mask, clk); 668 field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
669 if (div_sel == 0) 669 if (div_sel == 0)
670 return ret; 670 return ret;
671 671
672 if(clk->flags & CM_SYSCLKOUT_SEL1){ 672 if (clk->flags & CM_SYSCLKOUT_SEL1) {
673 switch(new_div){ 673 switch (new_div) {
674 case 16: field_val = 4; break; 674 case 16:
675 case 8: field_val = 3; break; 675 field_val = 4;
676 case 4: field_val = 2; break; 676 break;
677 case 2: field_val = 1; break; 677 case 8:
678 case 1: field_val = 0; break; 678 field_val = 3;
679 break;
680 case 4:
681 field_val = 2;
682 break;
683 case 2:
684 field_val = 1;
685 break;
686 case 1:
687 field_val = 0;
688 break;
679 } 689 }
680 } 690 } else
681 else
682 field_val = new_div; 691 field_val = new_div;
683 692
684 reg = (void __iomem *)div_sel; 693 reg = (void __iomem *)div_sel;
@@ -743,7 +752,7 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
743 val = 0x2; 752 val = 0x2;
744 break; 753 break;
745 case CM_WKUP_SEL1: 754 case CM_WKUP_SEL1:
746 src_reg_addr = (u32)&CM_CLKSEL2_CORE; 755 src_reg_addr = (u32)&CM_CLKSEL_WKUP;
747 mask = 0x3; 756 mask = 0x3;
748 if (src_clk == &func_32k_ck) 757 if (src_clk == &func_32k_ck)
749 val = 0x0; 758 val = 0x0;
@@ -783,9 +792,9 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
783 val = 0; 792 val = 0;
784 if (src_clk == &sys_ck) 793 if (src_clk == &sys_ck)
785 val = 1; 794 val = 1;
786 if (src_clk == &func_54m_ck)
787 val = 2;
788 if (src_clk == &func_96m_ck) 795 if (src_clk == &func_96m_ck)
796 val = 2;
797 if (src_clk == &func_54m_ck)
789 val = 3; 798 val = 3;
790 break; 799 break;
791 } 800 }
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 6c78d471fab7..2781dfbc5164 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -1062,7 +1062,7 @@ static struct clk gpt2_ick = {
1062 .parent = &l4_ck, 1062 .parent = &l4_ck,
1063 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1063 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1064 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */ 1064 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */
1065 .enable_bit = 0, 1065 .enable_bit = 4,
1066 .recalc = &omap2_followparent_recalc, 1066 .recalc = &omap2_followparent_recalc,
1067}; 1067};
1068 1068
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 4842ffe26705..aa4322451e8b 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -104,6 +104,51 @@ static inline void omap_init_sti(void)
104static inline void omap_init_sti(void) {} 104static inline void omap_init_sti(void) {}
105#endif 105#endif
106 106
107#if defined(CONFIG_SPI_OMAP24XX)
108
109#include <asm/arch/mcspi.h>
110
111#define OMAP2_MCSPI1_BASE 0x48098000
112#define OMAP2_MCSPI2_BASE 0x4809a000
113
114/* FIXME: use resources instead */
115
116static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
117 .base = io_p2v(OMAP2_MCSPI1_BASE),
118 .num_cs = 4,
119};
120
121struct platform_device omap2_mcspi1 = {
122 .name = "omap2_mcspi",
123 .id = 1,
124 .dev = {
125 .platform_data = &omap2_mcspi1_config,
126 },
127};
128
129static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
130 .base = io_p2v(OMAP2_MCSPI2_BASE),
131 .num_cs = 2,
132};
133
134struct platform_device omap2_mcspi2 = {
135 .name = "omap2_mcspi",
136 .id = 2,
137 .dev = {
138 .platform_data = &omap2_mcspi2_config,
139 },
140};
141
142static void omap_init_mcspi(void)
143{
144 platform_device_register(&omap2_mcspi1);
145 platform_device_register(&omap2_mcspi2);
146}
147
148#else
149static inline void omap_init_mcspi(void) {}
150#endif
151
107/*-------------------------------------------------------------------------*/ 152/*-------------------------------------------------------------------------*/
108 153
109static int __init omap2_init_devices(void) 154static int __init omap2_init_devices(void)
@@ -112,6 +157,7 @@ static int __init omap2_init_devices(void)
112 * in alphabetical order so they're easier to sort through. 157 * in alphabetical order so they're easier to sort through.
113 */ 158 */
114 omap_init_i2c(); 159 omap_init_i2c();
160 omap_init_mcspi();
115 omap_init_sti(); 161 omap_init_sti();
116 162
117 return 0; 163 return 0;
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
new file mode 100644
index 000000000000..c7a48f921fef
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -0,0 +1,209 @@
1/*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/err.h>
15#include <linux/clk.h>
16
17#include <asm/io.h>
18#include <asm/arch/gpmc.h>
19
20#undef DEBUG
21
22#define GPMC_BASE 0x6800a000
23#define GPMC_REVISION 0x00
24#define GPMC_SYSCONFIG 0x10
25#define GPMC_SYSSTATUS 0x14
26#define GPMC_IRQSTATUS 0x18
27#define GPMC_IRQENABLE 0x1c
28#define GPMC_TIMEOUT_CONTROL 0x40
29#define GPMC_ERR_ADDRESS 0x44
30#define GPMC_ERR_TYPE 0x48
31#define GPMC_CONFIG 0x50
32#define GPMC_STATUS 0x54
33#define GPMC_PREFETCH_CONFIG1 0x1e0
34#define GPMC_PREFETCH_CONFIG2 0x1e4
35#define GPMC_PREFETCH_CONTROL 0x1e8
36#define GPMC_PREFETCH_STATUS 0x1f0
37#define GPMC_ECC_CONFIG 0x1f4
38#define GPMC_ECC_CONTROL 0x1f8
39#define GPMC_ECC_SIZE_CONFIG 0x1fc
40
41#define GPMC_CS0 0x60
42#define GPMC_CS_SIZE 0x30
43
44static void __iomem *gpmc_base =
45 (void __iomem *) IO_ADDRESS(GPMC_BASE);
46static void __iomem *gpmc_cs_base =
47 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
48
49static struct clk *gpmc_l3_clk;
50
51static void gpmc_write_reg(int idx, u32 val)
52{
53 __raw_writel(val, gpmc_base + idx);
54}
55
56static u32 gpmc_read_reg(int idx)
57{
58 return __raw_readl(gpmc_base + idx);
59}
60
61void gpmc_cs_write_reg(int cs, int idx, u32 val)
62{
63 void __iomem *reg_addr;
64
65 reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
66 __raw_writel(val, reg_addr);
67}
68
69u32 gpmc_cs_read_reg(int cs, int idx)
70{
71 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
72}
73
74/* TODO: Add support for gpmc_fck to clock framework and use it */
75static unsigned long gpmc_get_fclk_period(void)
76{
77 /* In picoseconds */
78 return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
79}
80
81unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
82{
83 unsigned long tick_ps;
84
85 /* Calculate in picosecs to yield more exact results */
86 tick_ps = gpmc_get_fclk_period();
87
88 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
89}
90
91#ifdef DEBUG
92static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
93 int time, const char *name)
94#else
95static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
96 int time)
97#endif
98{
99 u32 l;
100 int ticks, mask, nr_bits;
101
102 if (time == 0)
103 ticks = 0;
104 else
105 ticks = gpmc_ns_to_ticks(time);
106 nr_bits = end_bit - st_bit + 1;
107 if (ticks >= 1 << nr_bits)
108 return -1;
109
110 mask = (1 << nr_bits) - 1;
111 l = gpmc_cs_read_reg(cs, reg);
112#ifdef DEBUG
113 printk(KERN_INFO "GPMC CS%d: %-10s: %d ticks, %3lu ns (was %i ticks)\n",
114 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
115 (l >> st_bit) & mask);
116#endif
117 l &= ~(mask << st_bit);
118 l |= ticks << st_bit;
119 gpmc_cs_write_reg(cs, reg, l);
120
121 return 0;
122}
123
124#ifdef DEBUG
125#define GPMC_SET_ONE(reg, st, end, field) \
126 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
127 t->field, #field) < 0) \
128 return -1
129#else
130#define GPMC_SET_ONE(reg, st, end, field) \
131 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
132 return -1
133#endif
134
135int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
136{
137 int div;
138 u32 l;
139
140 l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
141 div = l / gpmc_get_fclk_period();
142 if (div > 4)
143 return -1;
144 if (div < 0)
145 div = 1;
146
147 return div;
148}
149
150int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
151{
152 int div;
153 u32 l;
154
155 div = gpmc_cs_calc_divider(cs, t->sync_clk);
156 if (div < 0)
157 return -1;
158
159 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
160 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
161 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
162
163 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
164 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
165 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
166
167 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
168 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
169 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
170 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
171
172 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
173 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
174 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
175
176 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
177
178#ifdef DEBUG
179 printk(KERN_INFO "GPMC CS%d CLK period is %lu (div %d)\n",
180 cs, gpmc_get_fclk_period(), div);
181#endif
182
183 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
184 l &= ~0x03;
185 l |= (div - 1);
186
187 return 0;
188}
189
190unsigned long gpmc_cs_get_base_addr(int cs)
191{
192 return (gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7) & 0x1f) << 24;
193}
194
195void __init gpmc_init(void)
196{
197 u32 l;
198
199 gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
200 BUG_ON(IS_ERR(gpmc_l3_clk));
201
202 l = gpmc_read_reg(GPMC_REVISION);
203 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
204 /* Set smart idle mode and automatic L3 clock gating */
205 l = gpmc_read_reg(GPMC_SYSCONFIG);
206 l &= 0x03 << 3;
207 l |= (0x02 << 3) | (1 << 0);
208 gpmc_write_reg(GPMC_SYSCONFIG, l);
209}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 20dd6e74e91d..a0728c33e5d9 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -26,6 +26,7 @@
26extern void omap_sram_init(void); 26extern void omap_sram_init(void);
27extern int omap2_clk_init(void); 27extern int omap2_clk_init(void);
28extern void omap2_check_revision(void); 28extern void omap2_check_revision(void);
29extern void gpmc_init(void);
29 30
30/* 31/*
31 * The machine specific code may provide the extra mapping besides the 32 * The machine specific code may provide the extra mapping besides the
@@ -66,4 +67,5 @@ void __init omap2_init_common_hw(void)
66{ 67{
67 omap2_mux_init(); 68 omap2_mux_init();
68 omap2_clk_init(); 69 omap2_clk_init();
70 gpmc_init();
69} 71}
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 4c5f2c04883e..60ef084faffd 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -52,6 +52,12 @@ MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1)
52/* 24xx clocks */ 52/* 24xx clocks */
53MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1) 53MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1)
54 54
55/* 24xx GPMC wait pin monitoring */
56MUX_CFG_24XX("L3_GPMC_WAIT0", 0x09a, 0, 1, 1, 1)
57MUX_CFG_24XX("N7_GPMC_WAIT1", 0x09b, 0, 1, 1, 1)
58MUX_CFG_24XX("M1_GPMC_WAIT2", 0x09c, 0, 1, 1, 1)
59MUX_CFG_24XX("P1_GPMC_WAIT3", 0x09d, 0, 1, 1, 1)
60
55/* 24xx McBSP */ 61/* 24xx McBSP */
56MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX", 0x124, 1, 1, 0, 1) 62MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX", 0x124, 1, 1, 0, 1)
57MUX_CFG_24XX("R14_24XX_MCBSP2_FSX", 0x125, 1, 1, 0, 1) 63MUX_CFG_24XX("R14_24XX_MCBSP2_FSX", 0x125, 1, 1, 0, 1)
@@ -59,18 +65,38 @@ MUX_CFG_24XX("W15_24XX_MCBSP2_DR", 0x126, 1, 1, 0, 1)
59MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1) 65MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1)
60 66
61/* 24xx GPIO */ 67/* 24xx GPIO */
62MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1) 68MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1)
63MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1) 69MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1)
64MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1) 70MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1)
65MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1) 71MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1)
66MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1) 72MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1)
67MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1) 73MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1)
68MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1) 74MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1)
69MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1) 75MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1)
70MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1) 76MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1)
71MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1) 77MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1)
72MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1) 78MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1)
73 79
80/* 242x DBG GPIO */
81MUX_CFG_24XX("V4_242X_GPIO49", 0xd3, 3, 0, 0, 1)
82MUX_CFG_24XX("W2_242X_GPIO50", 0xd4, 3, 0, 0, 1)
83MUX_CFG_24XX("U4_242X_GPIO51", 0xd5, 3, 0, 0, 1)
84MUX_CFG_24XX("V3_242X_GPIO52", 0xd6, 3, 0, 0, 1)
85MUX_CFG_24XX("V2_242X_GPIO53", 0xd7, 3, 0, 0, 1)
86MUX_CFG_24XX("V6_242X_GPIO53", 0xcf, 3, 0, 0, 1)
87MUX_CFG_24XX("T4_242X_GPIO54", 0xd8, 3, 0, 0, 1)
88MUX_CFG_24XX("Y4_242X_GPIO54", 0xd0, 3, 0, 0, 1)
89MUX_CFG_24XX("T3_242X_GPIO55", 0xd9, 3, 0, 0, 1)
90MUX_CFG_24XX("U2_242X_GPIO56", 0xda, 3, 0, 0, 1)
91
92/* 24xx external DMA requests */
93MUX_CFG_24XX("AA10_242X_DMAREQ0", 0x0e5, 2, 0, 0, 1)
94MUX_CFG_24XX("AA6_242X_DMAREQ1", 0x0e6, 2, 0, 0, 1)
95MUX_CFG_24XX("E4_242X_DMAREQ2", 0x074, 2, 0, 0, 1)
96MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1)
97MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1)
98MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1)
99
74/* TSC IRQ */ 100/* TSC IRQ */
75MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1) 101MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1)
76 102
diff --git a/arch/arm/mach-omap2/pm-domain.c b/arch/arm/mach-omap2/pm-domain.c
new file mode 100644
index 000000000000..5e20e740cde5
--- /dev/null
+++ b/arch/arm/mach-omap2/pm-domain.c
@@ -0,0 +1,300 @@
1/*
2 * linux/arch/arm/mach-omap2/pm-domain.c
3 *
4 * Power domain functions for OMAP2
5 *
6 * Copyright (C) 2006 Nokia Corporation
7 * Tony Lindgren <tony@atomide.com>
8 *
9 * Some code based on earlier OMAP2 sample PM code
10 * Copyright (C) 2005 Texas Instruments, Inc.
11 * Richard Woodruff <r-woodruff2@ti.com>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/config.h>
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/clk.h>
22
23#include <asm/io.h>
24
25#include "prcm-regs.h"
26
27/* Power domain offsets */
28#define PM_MPU_OFFSET 0x100
29#define PM_CORE_OFFSET 0x200
30#define PM_GFX_OFFSET 0x300
31#define PM_WKUP_OFFSET 0x400 /* Autoidle only */
32#define PM_PLL_OFFSET 0x500 /* Autoidle only */
33#define PM_DSP_OFFSET 0x800
34#define PM_MDM_OFFSET 0xc00
35
36/* Power domain wake-up dependency control register */
37#define PM_WKDEP_OFFSET 0xc8
38#define EN_MDM (1 << 5)
39#define EN_WKUP (1 << 4)
40#define EN_GFX (1 << 3)
41#define EN_DSP (1 << 2)
42#define EN_MPU (1 << 1)
43#define EN_CORE (1 << 0)
44
45/* Core power domain state transition control register */
46#define PM_PWSTCTRL_OFFSET 0xe0
47#define FORCESTATE (1 << 18) /* Only for DSP & GFX */
48#define MEM4RETSTATE (1 << 6)
49#define MEM3RETSTATE (1 << 5)
50#define MEM2RETSTATE (1 << 4)
51#define MEM1RETSTATE (1 << 3)
52#define LOGICRETSTATE (1 << 2) /* Logic is retained */
53#define POWERSTATE_OFF 0x3
54#define POWERSTATE_RETENTION 0x1
55#define POWERSTATE_ON 0x0
56
57/* Power domain state register */
58#define PM_PWSTST_OFFSET 0xe4
59
60/* Hardware supervised state transition control register */
61#define CM_CLKSTCTRL_OFFSET 0x48
62#define AUTOSTAT_MPU (1 << 0) /* MPU */
63#define AUTOSTAT_DSS (1 << 2) /* Core */
64#define AUTOSTAT_L4 (1 << 1) /* Core */
65#define AUTOSTAT_L3 (1 << 0) /* Core */
66#define AUTOSTAT_GFX (1 << 0) /* GFX */
67#define AUTOSTAT_IVA (1 << 8) /* 2420 IVA in DSP domain */
68#define AUTOSTAT_DSP (1 << 0) /* DSP */
69#define AUTOSTAT_MDM (1 << 0) /* MDM */
70
71/* Automatic control of interface clock idling */
72#define CM_AUTOIDLE1_OFFSET 0x30
73#define CM_AUTOIDLE2_OFFSET 0x34 /* Core only */
74#define CM_AUTOIDLE3_OFFSET 0x38 /* Core only */
75#define CM_AUTOIDLE4_OFFSET 0x3c /* Core only */
76#define AUTO_54M(x) (((x) & 0x3) << 6)
77#define AUTO_96M(x) (((x) & 0x3) << 2)
78#define AUTO_DPLL(x) (((x) & 0x3) << 0)
79#define AUTO_STOPPED 0x3
80#define AUTO_BYPASS_FAST 0x2 /* DPLL only */
81#define AUTO_BYPASS_LOW_POWER 0x1 /* DPLL only */
82#define AUTO_DISABLED 0x0
83
84/* Voltage control PRCM_VOLTCTRL bits */
85#define AUTO_EXTVOLT (1 << 15)
86#define FORCE_EXTVOLT (1 << 14)
87#define SETOFF_LEVEL(x) (((x) & 0x3) << 12)
88#define MEMRETCTRL (1 << 8)
89#define SETRET_LEVEL(x) (((x) & 0x3) << 6)
90#define VOLT_LEVEL(x) (((x) & 0x3) << 0)
91
92#define OMAP24XX_PRCM_VBASE IO_ADDRESS(OMAP24XX_PRCM_BASE)
93#define prcm_readl(r) __raw_readl(OMAP24XX_PRCM_VBASE + (r))
94#define prcm_writel(v, r) __raw_writel((v), OMAP24XX_PRCM_VBASE + (r))
95
96static u32 pmdomain_get_wakeup_dependencies(int domain_offset)
97{
98 return prcm_readl(domain_offset + PM_WKDEP_OFFSET);
99}
100
101static void pmdomain_set_wakeup_dependencies(u32 state, int domain_offset)
102{
103 prcm_writel(state, domain_offset + PM_WKDEP_OFFSET);
104}
105
106static u32 pmdomain_get_powerstate(int domain_offset)
107{
108 return prcm_readl(domain_offset + PM_PWSTCTRL_OFFSET);
109}
110
111static void pmdomain_set_powerstate(u32 state, int domain_offset)
112{
113 prcm_writel(state, domain_offset + PM_PWSTCTRL_OFFSET);
114}
115
116static u32 pmdomain_get_clock_autocontrol(int domain_offset)
117{
118 return prcm_readl(domain_offset + CM_CLKSTCTRL_OFFSET);
119}
120
121static void pmdomain_set_clock_autocontrol(u32 state, int domain_offset)
122{
123 prcm_writel(state, domain_offset + CM_CLKSTCTRL_OFFSET);
124}
125
126static u32 pmdomain_get_clock_autoidle1(int domain_offset)
127{
128 return prcm_readl(domain_offset + CM_AUTOIDLE1_OFFSET);
129}
130
131/* Core domain only */
132static u32 pmdomain_get_clock_autoidle2(int domain_offset)
133{
134 return prcm_readl(domain_offset + CM_AUTOIDLE2_OFFSET);
135}
136
137/* Core domain only */
138static u32 pmdomain_get_clock_autoidle3(int domain_offset)
139{
140 return prcm_readl(domain_offset + CM_AUTOIDLE3_OFFSET);
141}
142
143/* Core domain only */
144static u32 pmdomain_get_clock_autoidle4(int domain_offset)
145{
146 return prcm_readl(domain_offset + CM_AUTOIDLE4_OFFSET);
147}
148
149static void pmdomain_set_clock_autoidle1(u32 state, int domain_offset)
150{
151 prcm_writel(state, CM_AUTOIDLE1_OFFSET + domain_offset);
152}
153
154/* Core domain only */
155static void pmdomain_set_clock_autoidle2(u32 state, int domain_offset)
156{
157 prcm_writel(state, CM_AUTOIDLE2_OFFSET + domain_offset);
158}
159
160/* Core domain only */
161static void pmdomain_set_clock_autoidle3(u32 state, int domain_offset)
162{
163 prcm_writel(state, CM_AUTOIDLE3_OFFSET + domain_offset);
164}
165
166/* Core domain only */
167static void pmdomain_set_clock_autoidle4(u32 state, int domain_offset)
168{
169 prcm_writel(state, CM_AUTOIDLE4_OFFSET + domain_offset);
170}
171
172/*
173 * Configures power management domains to idle clocks automatically.
174 */
175void pmdomain_set_autoidle(void)
176{
177 u32 val;
178
179 /* Set PLL auto stop for 54M, 96M & DPLL */
180 pmdomain_set_clock_autoidle1(AUTO_54M(AUTO_STOPPED) |
181 AUTO_96M(AUTO_STOPPED) |
182 AUTO_DPLL(AUTO_STOPPED), PM_PLL_OFFSET);
183
184 /* External clock input control
185 * REVISIT: Should this be in clock framework?
186 */
187 PRCM_CLKSRC_CTRL |= (0x3 << 3);
188
189 /* Configure number of 32KHz clock cycles for sys_clk */
190 PRCM_CLKSSETUP = 0x00ff;
191
192 /* Configure automatic voltage transition */
193 PRCM_VOLTSETUP = 0;
194 val = PRCM_VOLTCTRL;
195 val &= ~(SETOFF_LEVEL(0x3) | VOLT_LEVEL(0x3));
196 val |= SETOFF_LEVEL(1) | VOLT_LEVEL(1) | AUTO_EXTVOLT;
197 PRCM_VOLTCTRL = val;
198
199 /* Disable emulation tools functional clock */
200 PRCM_CLKEMUL_CTRL = 0x0;
201
202 /* Set core memory retention state */
203 val = pmdomain_get_powerstate(PM_CORE_OFFSET);
204 if (cpu_is_omap2420()) {
205 val &= ~(0x7 << 3);
206 val |= (MEM3RETSTATE | MEM2RETSTATE | MEM1RETSTATE);
207 } else {
208 val &= ~(0xf << 3);
209 val |= (MEM4RETSTATE | MEM3RETSTATE | MEM2RETSTATE |
210 MEM1RETSTATE);
211 }
212 pmdomain_set_powerstate(val, PM_CORE_OFFSET);
213
214 /* OCP interface smart idle. REVISIT: Enable autoidle bit0 ? */
215 val = SMS_SYSCONFIG;
216 val &= ~(0x3 << 3);
217 val |= (0x2 << 3) | (1 << 0);
218 SMS_SYSCONFIG |= val;
219
220 val = SDRC_SYSCONFIG;
221 val &= ~(0x3 << 3);
222 val |= (0x2 << 3);
223 SDRC_SYSCONFIG = val;
224
225 /* Configure L3 interface for smart idle.
226 * REVISIT: Enable autoidle bit0 ?
227 */
228 val = GPMC_SYSCONFIG;
229 val &= ~(0x3 << 3);
230 val |= (0x2 << 3) | (1 << 0);
231 GPMC_SYSCONFIG = val;
232
233 pmdomain_set_powerstate(LOGICRETSTATE | POWERSTATE_RETENTION,
234 PM_MPU_OFFSET);
235 pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_CORE_OFFSET);
236 if (!cpu_is_omap2420())
237 pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_MDM_OFFSET);
238
239 /* Assume suspend function has saved the state for DSP and GFX */
240 pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_DSP_OFFSET);
241 pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_GFX_OFFSET);
242
243#if 0
244 /* REVISIT: Internal USB needs special handling */
245 force_standby_usb();
246 if (cpu_is_omap2430())
247 force_hsmmc();
248 sdram_self_refresh_on_idle_req(1);
249#endif
250
251 /* Enable clock auto control for all domains.
252 * Note that CORE domain includes also DSS, L4 & L3.
253 */
254 pmdomain_set_clock_autocontrol(AUTOSTAT_MPU, PM_MPU_OFFSET);
255 pmdomain_set_clock_autocontrol(AUTOSTAT_GFX, PM_GFX_OFFSET);
256 pmdomain_set_clock_autocontrol(AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3,
257 PM_CORE_OFFSET);
258 if (cpu_is_omap2420())
259 pmdomain_set_clock_autocontrol(AUTOSTAT_IVA | AUTOSTAT_DSP,
260 PM_DSP_OFFSET);
261 else {
262 pmdomain_set_clock_autocontrol(AUTOSTAT_DSP, PM_DSP_OFFSET);
263 pmdomain_set_clock_autocontrol(AUTOSTAT_MDM, PM_MDM_OFFSET);
264 }
265
266 /* Enable clock autoidle for all domains */
267 pmdomain_set_clock_autoidle1(0x2, PM_DSP_OFFSET);
268 if (cpu_is_omap2420()) {
269 pmdomain_set_clock_autoidle1(0xfffffff9, PM_CORE_OFFSET);
270 pmdomain_set_clock_autoidle2(0x7, PM_CORE_OFFSET);
271 pmdomain_set_clock_autoidle1(0x3f, PM_WKUP_OFFSET);
272 } else {
273 pmdomain_set_clock_autoidle1(0xeafffff1, PM_CORE_OFFSET);
274 pmdomain_set_clock_autoidle2(0xfff, PM_CORE_OFFSET);
275 pmdomain_set_clock_autoidle1(0x7f, PM_WKUP_OFFSET);
276 pmdomain_set_clock_autoidle1(0x3, PM_MDM_OFFSET);
277 }
278 pmdomain_set_clock_autoidle3(0x7, PM_CORE_OFFSET);
279 pmdomain_set_clock_autoidle4(0x1f, PM_CORE_OFFSET);
280}
281
282/*
283 * Initializes power domains by removing wake-up dependencies and powering
284 * down DSP and GFX. Gets called from PM init. Note that DSP and IVA code
285 * must re-enable DSP and GFX when used.
286 */
287void __init pmdomain_init(void)
288{
289 /* Remove all domain wakeup dependencies */
290 pmdomain_set_wakeup_dependencies(EN_WKUP | EN_CORE, PM_MPU_OFFSET);
291 pmdomain_set_wakeup_dependencies(0, PM_DSP_OFFSET);
292 pmdomain_set_wakeup_dependencies(0, PM_GFX_OFFSET);
293 pmdomain_set_wakeup_dependencies(EN_WKUP | EN_MPU, PM_CORE_OFFSET);
294 if (cpu_is_omap2430())
295 pmdomain_set_wakeup_dependencies(0, PM_MDM_OFFSET);
296
297 /* Power down DSP and GFX */
298 pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_DSP_OFFSET);
299 pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_GFX_OFFSET);
300}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 562168fa2b16..d7eee99b7e3f 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -23,6 +23,7 @@
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/sysfs.h> 24#include <linux/sysfs.h>
25#include <linux/module.h> 25#include <linux/module.h>
26#include <linux/delay.h>
26 27
27#include <asm/io.h> 28#include <asm/io.h>
28#include <asm/irq.h> 29#include <asm/irq.h>
@@ -36,11 +37,18 @@
36#include <asm/arch/sram.h> 37#include <asm/arch/sram.h>
37#include <asm/arch/pm.h> 38#include <asm/arch/pm.h>
38 39
40#include "prcm-regs.h"
41
39static struct clk *vclk; 42static struct clk *vclk;
40static void (*omap2_sram_idle)(void); 43static void (*omap2_sram_idle)(void);
41static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev); 44static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev);
42static void (*saved_idle)(void); 45static void (*saved_idle)(void);
43 46
47extern void __init pmdomain_init(void);
48extern void pmdomain_set_autoidle(void);
49
50static unsigned int omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_SIZE];
51
44void omap2_pm_idle(void) 52void omap2_pm_idle(void)
45{ 53{
46 local_irq_disable(); 54 local_irq_disable();
@@ -87,23 +95,272 @@ static int omap2_pm_prepare(suspend_state_t state)
87 return error; 95 return error;
88} 96}
89 97
98#define INT0_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK1) | \
99 OMAP_IRQ_BIT(INT_24XX_GPIO_BANK2) | \
100 OMAP_IRQ_BIT(INT_24XX_GPIO_BANK3))
101
102#define INT1_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK4))
103
104#define INT2_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_UART1_IRQ) | \
105 OMAP_IRQ_BIT(INT_24XX_UART2_IRQ) | \
106 OMAP_IRQ_BIT(INT_24XX_UART3_IRQ))
107
108#define preg(reg) printk("%s\t(0x%p):\t0x%08x\n", #reg, &reg, reg);
109
110static void omap2_pm_debug(char * desc)
111{
112 printk("%s:\n", desc);
113
114 preg(CM_CLKSTCTRL_MPU);
115 preg(CM_CLKSTCTRL_CORE);
116 preg(CM_CLKSTCTRL_GFX);
117 preg(CM_CLKSTCTRL_DSP);
118 preg(CM_CLKSTCTRL_MDM);
119
120 preg(PM_PWSTCTRL_MPU);
121 preg(PM_PWSTCTRL_CORE);
122 preg(PM_PWSTCTRL_GFX);
123 preg(PM_PWSTCTRL_DSP);
124 preg(PM_PWSTCTRL_MDM);
125
126 preg(PM_PWSTST_MPU);
127 preg(PM_PWSTST_CORE);
128 preg(PM_PWSTST_GFX);
129 preg(PM_PWSTST_DSP);
130 preg(PM_PWSTST_MDM);
131
132 preg(CM_AUTOIDLE1_CORE);
133 preg(CM_AUTOIDLE2_CORE);
134 preg(CM_AUTOIDLE3_CORE);
135 preg(CM_AUTOIDLE4_CORE);
136 preg(CM_AUTOIDLE_WKUP);
137 preg(CM_AUTOIDLE_PLL);
138 preg(CM_AUTOIDLE_DSP);
139 preg(CM_AUTOIDLE_MDM);
140
141 preg(CM_ICLKEN1_CORE);
142 preg(CM_ICLKEN2_CORE);
143 preg(CM_ICLKEN3_CORE);
144 preg(CM_ICLKEN4_CORE);
145 preg(CM_ICLKEN_GFX);
146 preg(CM_ICLKEN_WKUP);
147 preg(CM_ICLKEN_DSP);
148 preg(CM_ICLKEN_MDM);
149
150 preg(CM_IDLEST1_CORE);
151 preg(CM_IDLEST2_CORE);
152 preg(CM_IDLEST3_CORE);
153 preg(CM_IDLEST4_CORE);
154 preg(CM_IDLEST_GFX);
155 preg(CM_IDLEST_WKUP);
156 preg(CM_IDLEST_CKGEN);
157 preg(CM_IDLEST_DSP);
158 preg(CM_IDLEST_MDM);
159
160 preg(RM_RSTST_MPU);
161 preg(RM_RSTST_GFX);
162 preg(RM_RSTST_WKUP);
163 preg(RM_RSTST_DSP);
164 preg(RM_RSTST_MDM);
165
166 preg(PM_WKDEP_MPU);
167 preg(PM_WKDEP_CORE);
168 preg(PM_WKDEP_GFX);
169 preg(PM_WKDEP_DSP);
170 preg(PM_WKDEP_MDM);
171
172 preg(CM_FCLKEN_WKUP);
173 preg(CM_ICLKEN_WKUP);
174 preg(CM_IDLEST_WKUP);
175 preg(CM_AUTOIDLE_WKUP);
176 preg(CM_CLKSEL_WKUP);
177
178 preg(PM_WKEN_WKUP);
179 preg(PM_WKST_WKUP);
180}
181
182static inline void omap2_pm_save_registers(void)
183{
184 /* Save interrupt registers */
185 OMAP24XX_SAVE(INTC_MIR0);
186 OMAP24XX_SAVE(INTC_MIR1);
187 OMAP24XX_SAVE(INTC_MIR2);
188
189 /* Save power control registers */
190 OMAP24XX_SAVE(CM_CLKSTCTRL_MPU);
191 OMAP24XX_SAVE(CM_CLKSTCTRL_CORE);
192 OMAP24XX_SAVE(CM_CLKSTCTRL_GFX);
193 OMAP24XX_SAVE(CM_CLKSTCTRL_DSP);
194 OMAP24XX_SAVE(CM_CLKSTCTRL_MDM);
195
196 /* Save power state registers */
197 OMAP24XX_SAVE(PM_PWSTCTRL_MPU);
198 OMAP24XX_SAVE(PM_PWSTCTRL_CORE);
199 OMAP24XX_SAVE(PM_PWSTCTRL_GFX);
200 OMAP24XX_SAVE(PM_PWSTCTRL_DSP);
201 OMAP24XX_SAVE(PM_PWSTCTRL_MDM);
202
203 /* Save autoidle registers */
204 OMAP24XX_SAVE(CM_AUTOIDLE1_CORE);
205 OMAP24XX_SAVE(CM_AUTOIDLE2_CORE);
206 OMAP24XX_SAVE(CM_AUTOIDLE3_CORE);
207 OMAP24XX_SAVE(CM_AUTOIDLE4_CORE);
208 OMAP24XX_SAVE(CM_AUTOIDLE_WKUP);
209 OMAP24XX_SAVE(CM_AUTOIDLE_PLL);
210 OMAP24XX_SAVE(CM_AUTOIDLE_DSP);
211 OMAP24XX_SAVE(CM_AUTOIDLE_MDM);
212
213 /* Save idle state registers */
214 OMAP24XX_SAVE(CM_IDLEST1_CORE);
215 OMAP24XX_SAVE(CM_IDLEST2_CORE);
216 OMAP24XX_SAVE(CM_IDLEST3_CORE);
217 OMAP24XX_SAVE(CM_IDLEST4_CORE);
218 OMAP24XX_SAVE(CM_IDLEST_GFX);
219 OMAP24XX_SAVE(CM_IDLEST_WKUP);
220 OMAP24XX_SAVE(CM_IDLEST_CKGEN);
221 OMAP24XX_SAVE(CM_IDLEST_DSP);
222 OMAP24XX_SAVE(CM_IDLEST_MDM);
223
224 /* Save clock registers */
225 OMAP24XX_SAVE(CM_FCLKEN1_CORE);
226 OMAP24XX_SAVE(CM_FCLKEN2_CORE);
227 OMAP24XX_SAVE(CM_ICLKEN1_CORE);
228 OMAP24XX_SAVE(CM_ICLKEN2_CORE);
229 OMAP24XX_SAVE(CM_ICLKEN3_CORE);
230 OMAP24XX_SAVE(CM_ICLKEN4_CORE);
231}
232
233static inline void omap2_pm_restore_registers(void)
234{
235 /* Restore clock state registers */
236 OMAP24XX_RESTORE(CM_CLKSTCTRL_MPU);
237 OMAP24XX_RESTORE(CM_CLKSTCTRL_CORE);
238 OMAP24XX_RESTORE(CM_CLKSTCTRL_GFX);
239 OMAP24XX_RESTORE(CM_CLKSTCTRL_DSP);
240 OMAP24XX_RESTORE(CM_CLKSTCTRL_MDM);
241
242 /* Restore power state registers */
243 OMAP24XX_RESTORE(PM_PWSTCTRL_MPU);
244 OMAP24XX_RESTORE(PM_PWSTCTRL_CORE);
245 OMAP24XX_RESTORE(PM_PWSTCTRL_GFX);
246 OMAP24XX_RESTORE(PM_PWSTCTRL_DSP);
247 OMAP24XX_RESTORE(PM_PWSTCTRL_MDM);
248
249 /* Restore idle state registers */
250 OMAP24XX_RESTORE(CM_IDLEST1_CORE);
251 OMAP24XX_RESTORE(CM_IDLEST2_CORE);
252 OMAP24XX_RESTORE(CM_IDLEST3_CORE);
253 OMAP24XX_RESTORE(CM_IDLEST4_CORE);
254 OMAP24XX_RESTORE(CM_IDLEST_GFX);
255 OMAP24XX_RESTORE(CM_IDLEST_WKUP);
256 OMAP24XX_RESTORE(CM_IDLEST_CKGEN);
257 OMAP24XX_RESTORE(CM_IDLEST_DSP);
258 OMAP24XX_RESTORE(CM_IDLEST_MDM);
259
260 /* Restore autoidle registers */
261 OMAP24XX_RESTORE(CM_AUTOIDLE1_CORE);
262 OMAP24XX_RESTORE(CM_AUTOIDLE2_CORE);
263 OMAP24XX_RESTORE(CM_AUTOIDLE3_CORE);
264 OMAP24XX_RESTORE(CM_AUTOIDLE4_CORE);
265 OMAP24XX_RESTORE(CM_AUTOIDLE_WKUP);
266 OMAP24XX_RESTORE(CM_AUTOIDLE_PLL);
267 OMAP24XX_RESTORE(CM_AUTOIDLE_DSP);
268 OMAP24XX_RESTORE(CM_AUTOIDLE_MDM);
269
270 /* Restore clock registers */
271 OMAP24XX_RESTORE(CM_FCLKEN1_CORE);
272 OMAP24XX_RESTORE(CM_FCLKEN2_CORE);
273 OMAP24XX_RESTORE(CM_ICLKEN1_CORE);
274 OMAP24XX_RESTORE(CM_ICLKEN2_CORE);
275 OMAP24XX_RESTORE(CM_ICLKEN3_CORE);
276 OMAP24XX_RESTORE(CM_ICLKEN4_CORE);
277
278 /* REVISIT: Clear interrupts here */
279
280 /* Restore interrupt registers */
281 OMAP24XX_RESTORE(INTC_MIR0);
282 OMAP24XX_RESTORE(INTC_MIR1);
283 OMAP24XX_RESTORE(INTC_MIR2);
284}
285
286static int omap2_pm_suspend(void)
287{
288 int processor_type = 0;
289
290 /* REVISIT: 0x21 or 0x26? */
291 if (cpu_is_omap2420())
292 processor_type = 0x21;
293
294 if (!processor_type)
295 return -ENOTSUPP;
296
297 local_irq_disable();
298 local_fiq_disable();
299
300 omap2_pm_save_registers();
301
302 /* Disable interrupts except for the wake events */
303 INTC_MIR_SET0 = 0xffffffff & ~INT0_WAKE_MASK;
304 INTC_MIR_SET1 = 0xffffffff & ~INT1_WAKE_MASK;
305 INTC_MIR_SET2 = 0xffffffff & ~INT2_WAKE_MASK;
306
307 pmdomain_set_autoidle();
308
309 /* Clear old wake-up events */
310 PM_WKST1_CORE = 0;
311 PM_WKST2_CORE = 0;
312 PM_WKST_WKUP = 0;
313
314 /* Enable wake-up events */
315 PM_WKEN1_CORE = (1 << 22) | (1 << 21); /* UART1 & 2 */
316 PM_WKEN2_CORE = (1 << 2); /* UART3 */
317 PM_WKEN_WKUP = (1 << 2) | (1 << 0); /* GPIO & GPT1 */
318
319 /* Disable clocks except for CM_ICLKEN2_CORE. It gets disabled
320 * in the SRAM suspend code */
321 CM_FCLKEN1_CORE = 0;
322 CM_FCLKEN2_CORE = 0;
323 CM_ICLKEN1_CORE = 0;
324 CM_ICLKEN3_CORE = 0;
325 CM_ICLKEN4_CORE = 0;
326
327 omap2_pm_debug("Status before suspend");
328
329 /* Must wait for serial buffers to clear */
330 mdelay(200);
331
332 /* Jump to SRAM suspend code
333 * REVISIT: When is this SDRC_DLLB_CTRL?
334 */
335 omap2_sram_suspend(SDRC_DLLA_CTRL, processor_type);
336
337 /* Back from sleep */
338 omap2_pm_restore_registers();
339
340 local_fiq_enable();
341 local_irq_enable();
342
343 return 0;
344}
345
90static int omap2_pm_enter(suspend_state_t state) 346static int omap2_pm_enter(suspend_state_t state)
91{ 347{
348 int ret = 0;
349
92 switch (state) 350 switch (state)
93 { 351 {
94 case PM_SUSPEND_STANDBY: 352 case PM_SUSPEND_STANDBY:
95 case PM_SUSPEND_MEM: 353 case PM_SUSPEND_MEM:
96 /* FIXME: Add suspend */ 354 ret = omap2_pm_suspend();
97 break; 355 break;
98
99 case PM_SUSPEND_DISK: 356 case PM_SUSPEND_DISK:
100 return -ENOTSUPP; 357 ret = -ENOTSUPP;
101 358 break;
102 default: 359 default:
103 return -EINVAL; 360 ret = -EINVAL;
104 } 361 }
105 362
106 return 0; 363 return ret;
107} 364}
108 365
109static int omap2_pm_finish(suspend_state_t state) 366static int omap2_pm_finish(suspend_state_t state)
@@ -143,6 +400,8 @@ int __init omap2_pm_init(void)
143 pm_set_ops(&omap_pm_ops); 400 pm_set_ops(&omap_pm_ops);
144 pm_idle = omap2_pm_idle; 401 pm_idle = omap2_pm_idle;
145 402
403 pmdomain_init();
404
146 return 0; 405 return 0;
147} 406}
148 407
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 1d2f5ac2f69b..cf78e6c5a277 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -6,6 +6,7 @@
6 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com> 7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 * Juha Yrjölä <juha.yrjola@nokia.com> 8 * Juha Yrjölä <juha.yrjola@nokia.com>
9 * OMAP Dual-mode timer framework support by Timo Teras
9 * 10 *
10 * Some parts based off of TI's 24xx code: 11 * Some parts based off of TI's 24xx code:
11 * 12 *
@@ -22,54 +23,18 @@
22#include <linux/interrupt.h> 23#include <linux/interrupt.h>
23#include <linux/err.h> 24#include <linux/err.h>
24#include <linux/clk.h> 25#include <linux/clk.h>
26#include <linux/delay.h>
25 27
26#include <asm/mach/time.h> 28#include <asm/mach/time.h>
27#include <asm/delay.h> 29#include <asm/arch/dmtimer.h>
28#include <asm/io.h>
29 30
30#define OMAP2_GP_TIMER1_BASE 0x48028000 31static struct omap_dm_timer *gptimer;
31#define OMAP2_GP_TIMER2_BASE 0x4802a000
32#define OMAP2_GP_TIMER3_BASE 0x48078000
33#define OMAP2_GP_TIMER4_BASE 0x4807a000
34 32
35#define GP_TIMER_TIDR 0x00 33static inline void omap2_gp_timer_start(unsigned long load_val)
36#define GP_TIMER_TISR 0x18
37#define GP_TIMER_TIER 0x1c
38#define GP_TIMER_TCLR 0x24
39#define GP_TIMER_TCRR 0x28
40#define GP_TIMER_TLDR 0x2c
41#define GP_TIMER_TSICR 0x40
42
43#define OS_TIMER_NR 1 /* GP timer 2 */
44
45static unsigned long timer_base[] = {
46 IO_ADDRESS(OMAP2_GP_TIMER1_BASE),
47 IO_ADDRESS(OMAP2_GP_TIMER2_BASE),
48 IO_ADDRESS(OMAP2_GP_TIMER3_BASE),
49 IO_ADDRESS(OMAP2_GP_TIMER4_BASE),
50};
51
52static inline unsigned int timer_read_reg(int nr, unsigned int reg)
53{
54 return __raw_readl(timer_base[nr] + reg);
55}
56
57static inline void timer_write_reg(int nr, unsigned int reg, unsigned int val)
58{
59 __raw_writel(val, timer_base[nr] + reg);
60}
61
62/* Note that we always enable the clock prescale divider bit */
63static inline void omap2_gp_timer_start(int nr, unsigned long load_val)
64{ 34{
65 unsigned int tmp; 35 omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
66 36 omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
67 tmp = 0xffffffff - load_val; 37 omap_dm_timer_start(gptimer);
68
69 timer_write_reg(nr, GP_TIMER_TLDR, tmp);
70 timer_write_reg(nr, GP_TIMER_TCRR, tmp);
71 timer_write_reg(nr, GP_TIMER_TIER, 1 << 1);
72 timer_write_reg(nr, GP_TIMER_TCLR, (1 << 5) | (1 << 1) | 1);
73} 38}
74 39
75static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id, 40static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id,
@@ -77,7 +42,7 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id,
77{ 42{
78 write_seqlock(&xtime_lock); 43 write_seqlock(&xtime_lock);
79 44
80 timer_write_reg(OS_TIMER_NR, GP_TIMER_TISR, 1 << 1); 45 omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW);
81 timer_tick(regs); 46 timer_tick(regs);
82 47
83 write_sequnlock(&xtime_lock); 48 write_sequnlock(&xtime_lock);
@@ -87,41 +52,26 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id,
87 52
88static struct irqaction omap2_gp_timer_irq = { 53static struct irqaction omap2_gp_timer_irq = {
89 .name = "gp timer", 54 .name = "gp timer",
90 .flags = SA_INTERRUPT, 55 .flags = SA_INTERRUPT | SA_TIMER,
91 .handler = omap2_gp_timer_interrupt, 56 .handler = omap2_gp_timer_interrupt,
92}; 57};
93 58
94static void __init omap2_gp_timer_init(void) 59static void __init omap2_gp_timer_init(void)
95{ 60{
96 struct clk * sys_ck; 61 u32 tick_period;
97 u32 tick_period = 120000;
98 u32 l;
99 62
100 /* Reset clock and prescale value */ 63 omap_dm_timer_init();
101 timer_write_reg(OS_TIMER_NR, GP_TIMER_TCLR, 0); 64 gptimer = omap_dm_timer_request_specific(1);
65 BUG_ON(gptimer == NULL);
102 66
103 sys_ck = clk_get(NULL, "sys_ck"); 67 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
104 if (IS_ERR(sys_ck)) 68 tick_period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / 100;
105 printk(KERN_ERR "Could not get sys_ck\n");
106 else {
107 clk_enable(sys_ck);
108 tick_period = clk_get_rate(sys_ck) / 100;
109 clk_put(sys_ck);
110 }
111
112 tick_period /= 2; /* Minimum prescale divider is 2 */
113 tick_period -= 1; 69 tick_period -= 1;
114 70
115 l = timer_read_reg(OS_TIMER_NR, GP_TIMER_TIDR); 71 setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
116 printk(KERN_INFO "OMAP2 GP timer (HW version %d.%d)\n", 72 omap2_gp_timer_start(tick_period);
117 (l >> 4) & 0x0f, l & 0x0f);
118
119 setup_irq(38, &omap2_gp_timer_irq);
120
121 omap2_gp_timer_start(OS_TIMER_NR, tick_period);
122} 73}
123 74
124struct sys_timer omap_timer = { 75struct sys_timer omap_timer = {
125 .init = omap2_gp_timer_init, 76 .init = omap2_gp_timer_init,
126}; 77};
127
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index ea5137f319c4..03d07cae26c8 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -35,6 +35,10 @@ config PXA_SHARPSL
35 SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa) 35 SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa)
36 handheld computer. 36 handheld computer.
37 37
38config MACH_TRIZEPS4
39 bool "Keith und Koep Trizeps4 DIMM-Module"
40 select PXA27x
41
38endchoice 42endchoice
39 43
40if PXA_SHARPSL 44if PXA_SHARPSL
@@ -55,6 +59,21 @@ endchoice
55 59
56endif 60endif
57 61
62if MACH_TRIZEPS4
63
64choice
65 prompt "Select base board for Trizeps 4 module"
66
67config MACH_TRIZEPS4_CONXS
68 bool "ConXS Eval Board"
69
70config MACH_TRIZEPS4_ANY
71 bool "another Board"
72
73endchoice
74
75endif
76
58endmenu 77endmenu
59 78
60config MACH_POODLE 79config MACH_POODLE
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 1610690be419..9093eb1c94eb 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
12obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o 12obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
13obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o 13obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
14obj-$(CONFIG_ARCH_PXA_IDP) += idp.o 14obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
15obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o
15obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o 16obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o
16obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o 17obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o
17obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o 18obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o
@@ -23,6 +24,7 @@ led-y := leds.o
23led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o 24led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o
24led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o 25led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o
25led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o 26led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o
27led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o
26 28
27obj-$(CONFIG_LEDS) += $(led-y) 29obj-$(CONFIG_LEDS) += $(led-y)
28 30
diff --git a/arch/arm/mach-pxa/leds-trizeps4.c b/arch/arm/mach-pxa/leds-trizeps4.c
new file mode 100644
index 000000000000..14cfc85e44b5
--- /dev/null
+++ b/arch/arm/mach-pxa/leds-trizeps4.c
@@ -0,0 +1,134 @@
1/*
2 * linux/arch/arm/mach-pxa/leds-trizeps4.c
3 *
4 * Author: Jürgen Schindele
5 * Created: 20 02, 2006
6 * Copyright: Jürgen Schindele
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/config.h>
14#include <linux/init.h>
15
16#include <asm/hardware.h>
17#include <asm/system.h>
18#include <asm/types.h>
19#include <asm/leds.h>
20
21#include <asm/arch/pxa-regs.h>
22#include <asm/arch/trizeps4.h>
23
24#include "leds.h"
25
26#define LED_STATE_ENABLED 1
27#define LED_STATE_CLAIMED 2
28
29#define SYS_BUSY 0x01
30#define HEARTBEAT 0x02
31#define BLINK 0x04
32
33static unsigned int led_state;
34static unsigned int hw_led_state;
35
36void trizeps4_leds_event(led_event_t evt)
37{
38 unsigned long flags;
39
40 local_irq_save(flags);
41
42 switch (evt) {
43 case led_start:
44 hw_led_state = 0;
45 pxa_gpio_mode( GPIO_SYS_BUSY_LED | GPIO_OUT); /* LED1 */
46 pxa_gpio_mode( GPIO_HEARTBEAT_LED | GPIO_OUT); /* LED2 */
47 led_state = LED_STATE_ENABLED;
48 break;
49
50 case led_stop:
51 led_state &= ~LED_STATE_ENABLED;
52 break;
53
54 case led_claim:
55 led_state |= LED_STATE_CLAIMED;
56 hw_led_state = 0;
57 break;
58
59 case led_release:
60 led_state &= ~LED_STATE_CLAIMED;
61 hw_led_state = 0;
62 break;
63
64#ifdef CONFIG_LEDS_TIMER
65 case led_timer:
66 hw_led_state ^= HEARTBEAT;
67 break;
68#endif
69
70#ifdef CONFIG_LEDS_CPU
71 case led_idle_start:
72 hw_led_state &= ~SYS_BUSY;
73 break;
74
75 case led_idle_end:
76 hw_led_state |= SYS_BUSY;
77 break;
78#endif
79
80 case led_halted:
81 break;
82
83 case led_green_on:
84 hw_led_state |= BLINK;
85 break;
86
87 case led_green_off:
88 hw_led_state &= ~BLINK;
89 break;
90
91 case led_amber_on:
92 break;
93
94 case led_amber_off:
95 break;
96
97 case led_red_on:
98 break;
99
100 case led_red_off:
101 break;
102
103 default:
104 break;
105 }
106
107 if (led_state & LED_STATE_ENABLED) {
108 switch (hw_led_state) {
109 case 0:
110 GPSR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
111 GPSR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
112 break;
113 case 1:
114 GPCR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
115 GPSR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
116 break;
117 case 2:
118 GPSR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
119 GPCR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
120 break;
121 case 3:
122 GPCR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
123 GPCR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
124 break;
125 }
126 }
127 else {
128 /* turn all off */
129 GPSR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
130 GPSR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
131 }
132
133 local_irq_restore(flags);
134}
diff --git a/arch/arm/mach-pxa/leds.c b/arch/arm/mach-pxa/leds.c
index bbe4d5f6afaa..e13eb841e48d 100644
--- a/arch/arm/mach-pxa/leds.c
+++ b/arch/arm/mach-pxa/leds.c
@@ -24,6 +24,8 @@ pxa_leds_init(void)
24 leds_event = mainstone_leds_event; 24 leds_event = mainstone_leds_event;
25 if (machine_is_pxa_idp()) 25 if (machine_is_pxa_idp())
26 leds_event = idp_leds_event; 26 leds_event = idp_leds_event;
27 if (machine_is_trizeps4())
28 leds_event = trizeps4_leds_event;
27 29
28 leds_event(led_start); 30 leds_event(led_start);
29 return 0; 31 return 0;
diff --git a/arch/arm/mach-pxa/leds.h b/arch/arm/mach-pxa/leds.h
index d98f6e93c12b..4f829b8c39dd 100644
--- a/arch/arm/mach-pxa/leds.h
+++ b/arch/arm/mach-pxa/leds.h
@@ -10,3 +10,4 @@
10extern void idp_leds_event(led_event_t evt); 10extern void idp_leds_event(led_event_t evt);
11extern void lubbock_leds_event(led_event_t evt); 11extern void lubbock_leds_event(led_event_t evt);
12extern void mainstone_leds_event(led_event_t evt); 12extern void mainstone_leds_event(led_event_t evt);
13extern void trizeps4_leds_event(led_event_t evt);
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index ec0f43a102c7..1a5f5c21481e 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -248,58 +248,137 @@ static void lpd270_backlight_power(int on)
248 248
249/* 5.7" TFT QVGA (LoLo display number 1) */ 249/* 5.7" TFT QVGA (LoLo display number 1) */
250static struct pxafb_mach_info sharp_lq057q3dc02 __initdata = { 250static struct pxafb_mach_info sharp_lq057q3dc02 __initdata = {
251 .pixclock = 100000, 251 .pixclock = 150000,
252 .xres = 240, 252 .xres = 320,
253 .yres = 320, 253 .yres = 240,
254 .bpp = 16, 254 .bpp = 16,
255 .hsync_len = 64, 255 .hsync_len = 0x14,
256 .left_margin = 0x27, 256 .left_margin = 0x28,
257 .right_margin = 0x09, 257 .right_margin = 0x0a,
258 .vsync_len = 0x04, 258 .vsync_len = 0x02,
259 .upper_margin = 0x08, 259 .upper_margin = 0x08,
260 .lower_margin = 0x14, 260 .lower_margin = 0x14,
261 .sync = 0, 261 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
262 .lccr0 = 0x07800080, 262 .lccr0 = 0x07800080,
263 .lccr3 = 0x04400007, 263 .lccr3 = 0x00400000,
264 .pxafb_backlight_power = lpd270_backlight_power,
265};
266
267/* 12.1" TFT SVGA (LoLo display number 2) */
268static struct pxafb_mach_info sharp_lq121s1dg31 __initdata = {
269 .pixclock = 50000,
270 .xres = 800,
271 .yres = 600,
272 .bpp = 16,
273 .hsync_len = 0x05,
274 .left_margin = 0x52,
275 .right_margin = 0x05,
276 .vsync_len = 0x04,
277 .upper_margin = 0x14,
278 .lower_margin = 0x0a,
279 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
280 .lccr0 = 0x07800080,
281 .lccr3 = 0x00400000,
282 .pxafb_backlight_power = lpd270_backlight_power,
283};
284
285/* 3.6" TFT QVGA (LoLo display number 3) */
286static struct pxafb_mach_info sharp_lq036q1da01 __initdata = {
287 .pixclock = 150000,
288 .xres = 320,
289 .yres = 240,
290 .bpp = 16,
291 .hsync_len = 0x0e,
292 .left_margin = 0x04,
293 .right_margin = 0x0a,
294 .vsync_len = 0x03,
295 .upper_margin = 0x03,
296 .lower_margin = 0x03,
297 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
298 .lccr0 = 0x07800080,
299 .lccr3 = 0x00400000,
264 .pxafb_backlight_power = lpd270_backlight_power, 300 .pxafb_backlight_power = lpd270_backlight_power,
265}; 301};
266 302
267/* 6.4" TFT VGA (LoLo display number 5) */ 303/* 6.4" TFT VGA (LoLo display number 5) */
268static struct pxafb_mach_info sharp_lq64d343 __initdata = { 304static struct pxafb_mach_info sharp_lq64d343 __initdata = {
269 .pixclock = 20000, 305 .pixclock = 25000,
270 .xres = 640, 306 .xres = 640,
271 .yres = 480, 307 .yres = 480,
272 .bpp = 16, 308 .bpp = 16,
273 .hsync_len = 49, 309 .hsync_len = 0x31,
274 .left_margin = 0x89, 310 .left_margin = 0x89,
275 .right_margin = 0x19, 311 .right_margin = 0x19,
276 .vsync_len = 18, 312 .vsync_len = 0x12,
277 .upper_margin = 0x22, 313 .upper_margin = 0x22,
278 .lower_margin = 0, 314 .lower_margin = 0x00,
279 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 315 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
280 .lccr0 = 0x07800080, 316 .lccr0 = 0x07800080,
281 .lccr3 = 0x04400001, 317 .lccr3 = 0x00400000,
318 .pxafb_backlight_power = lpd270_backlight_power,
319};
320
321/* 10.4" TFT VGA (LoLo display number 7) */
322static struct pxafb_mach_info sharp_lq10d368 __initdata = {
323 .pixclock = 25000,
324 .xres = 640,
325 .yres = 480,
326 .bpp = 16,
327 .hsync_len = 0x31,
328 .left_margin = 0x89,
329 .right_margin = 0x19,
330 .vsync_len = 0x12,
331 .upper_margin = 0x22,
332 .lower_margin = 0x00,
333 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
334 .lccr0 = 0x07800080,
335 .lccr3 = 0x00400000,
282 .pxafb_backlight_power = lpd270_backlight_power, 336 .pxafb_backlight_power = lpd270_backlight_power,
283}; 337};
284 338
285/* 3.5" TFT QVGA (LoLo display number 8) */ 339/* 3.5" TFT QVGA (LoLo display number 8) */
286static struct pxafb_mach_info sharp_lq035q7db02_20 __initdata = { 340static struct pxafb_mach_info sharp_lq035q7db02_20 __initdata = {
287 .pixclock = 100000, 341 .pixclock = 150000,
288 .xres = 240, 342 .xres = 240,
289 .yres = 320, 343 .yres = 320,
290 .bpp = 16, 344 .bpp = 16,
291 .hsync_len = 0x34, 345 .hsync_len = 0x0e,
292 .left_margin = 0x09, 346 .left_margin = 0x0a,
293 .right_margin = 0x09, 347 .right_margin = 0x0a,
294 .vsync_len = 0x08, 348 .vsync_len = 0x03,
295 .upper_margin = 0x05, 349 .upper_margin = 0x05,
296 .lower_margin = 0x14, 350 .lower_margin = 0x14,
297 .sync = 0, 351 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
298 .lccr0 = 0x07800080, 352 .lccr0 = 0x07800080,
299 .lccr3 = 0x04400007, 353 .lccr3 = 0x00400000,
300 .pxafb_backlight_power = lpd270_backlight_power, 354 .pxafb_backlight_power = lpd270_backlight_power,
301}; 355};
302 356
357static struct pxafb_mach_info *lpd270_lcd_to_use;
358
359static int __init lpd270_set_lcd(char *str)
360{
361 if (!strnicmp(str, "lq057q3dc02", 11)) {
362 lpd270_lcd_to_use = &sharp_lq057q3dc02;
363 } else if (!strnicmp(str, "lq121s1dg31", 11)) {
364 lpd270_lcd_to_use = &sharp_lq121s1dg31;
365 } else if (!strnicmp(str, "lq036q1da01", 11)) {
366 lpd270_lcd_to_use = &sharp_lq036q1da01;
367 } else if (!strnicmp(str, "lq64d343", 8)) {
368 lpd270_lcd_to_use = &sharp_lq64d343;
369 } else if (!strnicmp(str, "lq10d368", 8)) {
370 lpd270_lcd_to_use = &sharp_lq10d368;
371 } else if (!strnicmp(str, "lq035q7db02-20", 14)) {
372 lpd270_lcd_to_use = &sharp_lq035q7db02_20;
373 } else {
374 printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
375 }
376
377 return 1;
378}
379
380__setup("lcd=", lpd270_set_lcd);
381
303static struct platform_device *platform_devices[] __initdata = { 382static struct platform_device *platform_devices[] __initdata = {
304 &smc91x_device, 383 &smc91x_device,
305 &lpd270_audio_device, 384 &lpd270_audio_device,
@@ -345,9 +424,8 @@ static void __init lpd270_init(void)
345 424
346 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 425 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
347 426
348 // set_pxa_fb_info(&sharp_lq057q3dc02); 427 if (lpd270_lcd_to_use != NULL)
349 set_pxa_fb_info(&sharp_lq64d343); 428 set_pxa_fb_info(lpd270_lcd_to_use);
350 // set_pxa_fb_info(&sharp_lq035q7db02_20);
351 429
352 pxa_set_ohci_info(&lpd270_ohci_platform_data); 430 pxa_set_ohci_info(&lpd270_ohci_platform_data);
353} 431}
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
new file mode 100644
index 000000000000..4ffff9e95eca
--- /dev/null
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -0,0 +1,471 @@
1/*
2 * linux/arch/arm/mach-pxa/trizeps4.c
3 *
4 * Support for the Keith und Koep Trizeps4 Module Platform.
5 *
6 * Author: Jürgen Schindele
7 * Created: 20 02, 2006
8 * Copyright: Jürgen Schindele
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <linux/platform_device.h>
18#include <linux/sysdev.h>
19#include <linux/interrupt.h>
20#include <linux/sched.h>
21#include <linux/bitops.h>
22#include <linux/fb.h>
23#include <linux/ioport.h>
24#include <linux/delay.h>
25#include <linux/serial_8250.h>
26#include <linux/mtd/mtd.h>
27#include <linux/mtd/partitions.h>
28
29#include <asm/types.h>
30#include <asm/setup.h>
31#include <asm/memory.h>
32#include <asm/mach-types.h>
33#include <asm/hardware.h>
34#include <asm/irq.h>
35#include <asm/sizes.h>
36
37#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39#include <asm/mach/irq.h>
40#include <asm/mach/flash.h>
41
42#include <asm/arch/pxa-regs.h>
43#include <asm/arch/trizeps4.h>
44#include <asm/arch/audio.h>
45#include <asm/arch/pxafb.h>
46#include <asm/arch/mmc.h>
47#include <asm/arch/irda.h>
48#include <asm/arch/ohci.h>
49
50#include "generic.h"
51
52/********************************************************************************************
53 * ONBOARD FLASH
54 ********************************************************************************************/
55static struct mtd_partition trizeps4_partitions[] = {
56 {
57 .name = "Bootloader",
58 .size = 0x00040000,
59 .offset = 0,
60 .mask_flags = MTD_WRITEABLE /* force read-only */
61 },{
62 .name = "Kernel",
63 .size = 0x00400000,
64 .offset = 0x00040000
65 },{
66 .name = "Filesystem",
67 .size = MTDPART_SIZ_FULL,
68 .offset = 0x00440000
69 }
70};
71
72static struct flash_platform_data trizeps4_flash_data[] = {
73 {
74 .map_name = "cfi_probe",
75 .parts = trizeps4_partitions,
76 .nr_parts = ARRAY_SIZE(trizeps4_partitions)
77 }
78};
79
80static struct resource flash_resource = {
81 .start = PXA_CS0_PHYS,
82 .end = PXA_CS0_PHYS + SZ_64M - 1,
83 .flags = IORESOURCE_MEM,
84};
85
86static struct platform_device flash_device = {
87 .name = "pxa2xx-flash",
88 .id = 0,
89 .dev = {
90 .platform_data = &trizeps4_flash_data,
91 },
92 .resource = &flash_resource,
93 .num_resources = 1,
94};
95
96/********************************************************************************************
97 * DAVICOM DM9000 Ethernet
98 ********************************************************************************************/
99static struct resource dm9000_resources[] = {
100 [0] = {
101 .start = TRIZEPS4_ETH_PHYS+0x300,
102 .end = TRIZEPS4_ETH_PHYS+0x400-1,
103 .flags = IORESOURCE_MEM,
104 },
105 [1] = {
106 .start = TRIZEPS4_ETH_PHYS+0x8300,
107 .end = TRIZEPS4_ETH_PHYS+0x8400-1,
108 .flags = IORESOURCE_MEM,
109 },
110 [2] = {
111 .start = TRIZEPS4_ETH_IRQ,
112 .end = TRIZEPS4_ETH_IRQ,
113 .flags = (IORESOURCE_IRQ | IRQT_RISING),
114 },
115};
116
117static struct platform_device dm9000_device = {
118 .name = "dm9000",
119 .id = -1,
120 .num_resources = ARRAY_SIZE(dm9000_resources),
121 .resource = dm9000_resources,
122};
123
124/********************************************************************************************
125 * PXA270 serial ports
126 ********************************************************************************************/
127static struct plat_serial8250_port tri_serial_ports[] = {
128#ifdef CONFIG_SERIAL_PXA
129 /* this uses the own PXA driver */
130 {
131 0,
132 },
133#else
134 /* this uses the generic 8520 driver */
135 [0] = {
136 .membase = (void *)&FFUART,
137 .irq = IRQ_FFUART,
138 .flags = UPF_BOOT_AUTOCONF,
139 .iotype = UPIO_MEM32,
140 .regshift = 2,
141 .uartclk = (921600*16),
142 },
143 [1] = {
144 .membase = (void *)&BTUART,
145 .irq = IRQ_BTUART,
146 .flags = UPF_BOOT_AUTOCONF,
147 .iotype = UPIO_MEM32,
148 .regshift = 2,
149 .uartclk = (921600*16),
150 },
151 {
152 0,
153 },
154#endif
155};
156
157static struct platform_device uart_devices = {
158 .name = "serial8250",
159 .id = 0,
160 .dev = {
161 .platform_data = tri_serial_ports,
162 },
163 .num_resources = 0,
164 .resource = NULL,
165};
166
167/********************************************************************************************
168 * PXA270 ac97 sound codec
169 ********************************************************************************************/
170static struct platform_device ac97_audio_device = {
171 .name = "pxa2xx-ac97",
172 .id = -1,
173};
174
175static struct platform_device * trizeps4_devices[] __initdata = {
176 &flash_device,
177 &uart_devices,
178 &dm9000_device,
179 &ac97_audio_device,
180};
181
182#ifdef CONFIG_MACH_TRIZEPS4_CONXS
183static short trizeps_conxs_bcr;
184
185/* PCCARD power switching supports only 3,3V */
186void board_pcmcia_power(int power)
187{
188 if (power) {
189 /* switch power on, put in reset and enable buffers */
190 trizeps_conxs_bcr |= power;
191 trizeps_conxs_bcr |= ConXS_BCR_CF_RESET;
192 trizeps_conxs_bcr &= ~(ConXS_BCR_CF_BUF_EN);
193 ConXS_BCR = trizeps_conxs_bcr;
194 /* wait a little */
195 udelay(2000);
196 /* take reset away */
197 trizeps_conxs_bcr &= ~(ConXS_BCR_CF_RESET);
198 ConXS_BCR = trizeps_conxs_bcr;
199 udelay(2000);
200 } else {
201 /* put in reset */
202 trizeps_conxs_bcr |= ConXS_BCR_CF_RESET;
203 ConXS_BCR = trizeps_conxs_bcr;
204 udelay(1000);
205 /* switch power off */
206 trizeps_conxs_bcr &= ~(0xf);
207 ConXS_BCR = trizeps_conxs_bcr;
208
209 }
210 pr_debug("%s: o%s 0x%x\n", __FUNCTION__, power ? "n": "ff", trizeps_conxs_bcr);
211}
212
213/* backlight power switching for LCD panel */
214static void board_backlight_power(int on)
215{
216 if (on) {
217 trizeps_conxs_bcr |= ConXS_BCR_L_DISP;
218 } else {
219 trizeps_conxs_bcr &= ~ConXS_BCR_L_DISP;
220 }
221 pr_debug("%s: o%s 0x%x\n", __FUNCTION__, on ? "n" : "ff", trizeps_conxs_bcr);
222 ConXS_BCR = trizeps_conxs_bcr;
223}
224
225/* Powersupply for MMC/SD cardslot */
226static void board_mci_power(struct device *dev, unsigned int vdd)
227{
228 struct pxamci_platform_data* p_d = dev->platform_data;
229
230 if (( 1 << vdd) & p_d->ocr_mask) {
231 pr_debug("%s: on\n", __FUNCTION__);
232 /* FIXME fill in values here */
233 } else {
234 pr_debug("%s: off\n", __FUNCTION__);
235 /* FIXME fill in values here */
236 }
237}
238
239static short trizeps_conxs_ircr;
240
241/* Switch modes and Power for IRDA receiver */
242static void board_irda_mode(struct device *dev, int mode)
243{
244 unsigned long flags;
245
246 local_irq_save(flags);
247 if (mode & IR_SIRMODE) {
248 /* Slow mode */
249 trizeps_conxs_ircr &= ~ConXS_IRCR_MODE;
250 } else if (mode & IR_FIRMODE) {
251 /* Fast mode */
252 trizeps_conxs_ircr |= ConXS_IRCR_MODE;
253 }
254 if (mode & IR_OFF) {
255 trizeps_conxs_ircr |= ConXS_IRCR_SD;
256 } else {
257 trizeps_conxs_ircr &= ~ConXS_IRCR_SD;
258 }
259 /* FIXME write values to register */
260 local_irq_restore(flags);
261}
262
263#else
264/* for other baseboards define dummies */
265void board_pcmcia_power(int power) {;}
266#define board_backlight_power NULL
267#define board_mci_power NULL
268#define board_irda_mode NULL
269
270#endif /* CONFIG_MACH_TRIZEPS4_CONXS */
271EXPORT_SYMBOL(board_pcmcia_power);
272
273static int trizeps4_mci_init(struct device *dev, irqreturn_t (*mci_detect_int)(int, void *, struct pt_regs *), void *data)
274{
275 int err;
276 /* setup GPIO for PXA27x MMC controller */
277 pxa_gpio_mode(GPIO32_MMCCLK_MD);
278 pxa_gpio_mode(GPIO112_MMCCMD_MD);
279 pxa_gpio_mode(GPIO92_MMCDAT0_MD);
280 pxa_gpio_mode(GPIO109_MMCDAT1_MD);
281 pxa_gpio_mode(GPIO110_MMCDAT2_MD);
282 pxa_gpio_mode(GPIO111_MMCDAT3_MD);
283
284 pxa_gpio_mode(GPIO_MMC_DET | GPIO_IN);
285
286 err = request_irq(TRIZEPS4_MMC_IRQ, mci_detect_int, SA_INTERRUPT | SA_TRIGGER_RISING, "MMC card detect", data);
287 if (err) {
288 printk(KERN_ERR "trizeps4_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
289 return -1;
290 }
291 return 0;
292}
293
294static void trizeps4_mci_exit(struct device *dev, void *data)
295{
296 free_irq(TRIZEPS4_MMC_IRQ, data);
297}
298
299static struct pxamci_platform_data trizeps4_mci_platform_data = {
300 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
301 .init = trizeps4_mci_init,
302 .exit = trizeps4_mci_exit,
303 .setpower = board_mci_power,
304};
305
306static struct pxaficp_platform_data trizeps4_ficp_platform_data = {
307 .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF,
308 .transceiver_mode = board_irda_mode,
309};
310
311static int trizeps4_ohci_init(struct device *dev)
312{
313 /* setup Port1 GPIO pin. */
314 pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */
315 pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
316
317 /* Set the Power Control Polarity Low and Power Sense
318 Polarity Low to active low. */
319 UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
320 ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
321
322 return 0;
323}
324
325static void trizeps4_ohci_exit(struct device *dev)
326{
327 ;
328}
329
330static struct pxaohci_platform_data trizeps4_ohci_platform_data = {
331 .port_mode = PMM_PERPORT_MODE,
332 .init = trizeps4_ohci_init,
333 .exit = trizeps4_ohci_exit,
334};
335
336static struct map_desc trizeps4_io_desc[] __initdata = {
337 { /* ConXS CFSR */
338 .virtual = TRIZEPS4_CFSR_VIRT,
339 .pfn = __phys_to_pfn(TRIZEPS4_CFSR_PHYS),
340 .length = 0x00001000,
341 .type = MT_DEVICE
342 },
343 { /* ConXS BCR */
344 .virtual = TRIZEPS4_BOCR_VIRT,
345 .pfn = __phys_to_pfn(TRIZEPS4_BOCR_PHYS),
346 .length = 0x00001000,
347 .type = MT_DEVICE
348 },
349 { /* ConXS IRCR */
350 .virtual = TRIZEPS4_IRCR_VIRT,
351 .pfn = __phys_to_pfn(TRIZEPS4_IRCR_PHYS),
352 .length = 0x00001000,
353 .type = MT_DEVICE
354 },
355 { /* ConXS DCR */
356 .virtual = TRIZEPS4_DICR_VIRT,
357 .pfn = __phys_to_pfn(TRIZEPS4_DICR_PHYS),
358 .length = 0x00001000,
359 .type = MT_DEVICE
360 },
361 { /* ConXS UPSR */
362 .virtual = TRIZEPS4_UPSR_VIRT,
363 .pfn = __phys_to_pfn(TRIZEPS4_UPSR_PHYS),
364 .length = 0x00001000,
365 .type = MT_DEVICE
366 }
367};
368
369static struct pxafb_mach_info sharp_lcd __initdata = {
370 .pixclock = 78000,
371 .xres = 640,
372 .yres = 480,
373 .bpp = 8,
374 .hsync_len = 4,
375 .left_margin = 4,
376 .right_margin = 4,
377 .vsync_len = 2,
378 .upper_margin = 0,
379 .lower_margin = 0,
380 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
381 .cmap_greyscale = 0,
382 .cmap_inverse = 0,
383 .cmap_static = 0,
384 .lccr0 = LCCR0_Color | LCCR0_Pas | LCCR0_Dual,
385 .lccr3 = 0x0340ff02,
386 .pxafb_backlight_power = board_backlight_power,
387};
388
389static void __init trizeps4_fixup(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi)
390{
391}
392
393static void __init trizeps4_init(void)
394{
395 platform_add_devices(trizeps4_devices, ARRAY_SIZE(trizeps4_devices));
396
397 set_pxa_fb_info(&sharp_lcd);
398
399 pxa_set_mci_info(&trizeps4_mci_platform_data);
400 pxa_set_ficp_info(&trizeps4_ficp_platform_data);
401 pxa_set_ohci_info(&trizeps4_ohci_platform_data);
402}
403
404static void __init trizeps4_map_io(void)
405{
406 pxa_map_io();
407 iotable_init(trizeps4_io_desc, ARRAY_SIZE(trizeps4_io_desc));
408
409 /* for DiskOnChip */
410 pxa_gpio_mode(GPIO15_nCS_1_MD);
411
412 /* for off-module PIC on ConXS board */
413 pxa_gpio_mode(GPIO_PIC | GPIO_IN);
414
415 /* UCB1400 irq */
416 pxa_gpio_mode(GPIO_UCB1400 | GPIO_IN);
417
418 /* for DM9000 LAN */
419 pxa_gpio_mode(GPIO78_nCS_2_MD);
420 pxa_gpio_mode(GPIO_DM9000 | GPIO_IN);
421
422 /* for PCMCIA device */
423 pxa_gpio_mode(GPIO_PCD | GPIO_IN);
424 pxa_gpio_mode(GPIO_PRDY | GPIO_IN);
425
426 /* for I2C adapter */
427 pxa_gpio_mode(GPIO117_I2CSCL_MD);
428 pxa_gpio_mode(GPIO118_I2CSDA_MD);
429
430 /* MMC_DET s.o. */
431 pxa_gpio_mode(GPIO_MMC_DET | GPIO_IN);
432
433 /* whats that for ??? */
434 pxa_gpio_mode(GPIO79_nCS_3_MD);
435
436 pxa_gpio_mode( GPIO_SYS_BUSY_LED | GPIO_OUT); /* LED1 */
437 pxa_gpio_mode( GPIO_HEARTBEAT_LED | GPIO_OUT); /* LED2 */
438
439#ifdef CONFIG_MACH_TRIZEPS4_CONXS
440#ifdef CONFIG_IDE_PXA_CF
441 /* if boot direct from compact flash dont disable power */
442 trizeps_conxs_bcr = 0x0009;
443#else
444 /* this is the reset value */
445 trizeps_conxs_bcr = 0x00A0;
446#endif
447 ConXS_BCR = trizeps_conxs_bcr;
448#endif
449
450 PWER = 0x00000002;
451 PFER = 0x00000000;
452 PRER = 0x00000002;
453 PGSR0 = 0x0158C000;
454 PGSR1 = 0x00FF0080;
455 PGSR2 = 0x0001C004;
456 /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
457 PCFR |= PCFR_OPDE;
458}
459
460MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
461 /* MAINTAINER("Jürgen Schindele") */
462 .phys_io = 0x40000000,
463 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
464 .boot_params = TRIZEPS4_SDRAM_BASE + 0x100,
465 .fixup = trizeps4_fixup,
466 .init_machine = trizeps4_init,
467 .map_io = trizeps4_map_io,
468 .init_irq = pxa_init_irq,
469 .timer = &pxa_timer,
470MACHINE_END
471
diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c
index 04c94ab6c18b..639597729932 100644
--- a/arch/arm/mach-sa1100/cpu-sa1110.c
+++ b/arch/arm/mach-sa1100/cpu-sa1110.c
@@ -15,7 +15,10 @@
15 * SDRAM reads (rev A0, B0, B1) 15 * SDRAM reads (rev A0, B0, B1)
16 * 16 *
17 * We ignore rev. A0 and B0 devices; I don't think they're worth supporting. 17 * We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
18 *
19 * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
18 */ 20 */
21#include <linux/moduleparam.h>
19#include <linux/types.h> 22#include <linux/types.h>
20#include <linux/kernel.h> 23#include <linux/kernel.h>
21#include <linux/sched.h> 24#include <linux/sched.h>
@@ -35,6 +38,7 @@
35static struct cpufreq_driver sa1110_driver; 38static struct cpufreq_driver sa1110_driver;
36 39
37struct sdram_params { 40struct sdram_params {
41 const char name[16];
38 u_char rows; /* bits */ 42 u_char rows; /* bits */
39 u_char cas_latency; /* cycles */ 43 u_char cas_latency; /* cycles */
40 u_char tck; /* clock cycle time (ns) */ 44 u_char tck; /* clock cycle time (ns) */
@@ -50,54 +54,53 @@ struct sdram_info {
50 u_int mdcas[3]; 54 u_int mdcas[3];
51}; 55};
52 56
53static struct sdram_params tc59sm716_cl2_params __initdata = { 57static struct sdram_params sdram_tbl[] __initdata = {
54 .rows = 12, 58 { /* Toshiba TC59SM716 CL2 */
55 .tck = 10, 59 .name = "TC59SM716-CL2",
56 .trcd = 20, 60 .rows = 12,
57 .trp = 20, 61 .tck = 10,
58 .twr = 10, 62 .trcd = 20,
59 .refresh = 64000, 63 .trp = 20,
60 .cas_latency = 2, 64 .twr = 10,
61}; 65 .refresh = 64000,
62 66 .cas_latency = 2,
63static struct sdram_params tc59sm716_cl3_params __initdata = { 67 }, { /* Toshiba TC59SM716 CL3 */
64 .rows = 12, 68 .name = "TC59SM716-CL3",
65 .tck = 8, 69 .rows = 12,
66 .trcd = 20, 70 .tck = 8,
67 .trp = 20, 71 .trcd = 20,
68 .twr = 8, 72 .trp = 20,
69 .refresh = 64000, 73 .twr = 8,
70 .cas_latency = 3, 74 .refresh = 64000,
71}; 75 .cas_latency = 3,
72 76 }, { /* Samsung K4S641632D TC75 */
73static struct sdram_params samsung_k4s641632d_tc75 __initdata = { 77 .name = "K4S641632D",
74 .rows = 14, 78 .rows = 14,
75 .tck = 9, 79 .tck = 9,
76 .trcd = 27, 80 .trcd = 27,
77 .trp = 20, 81 .trp = 20,
78 .twr = 9, 82 .twr = 9,
79 .refresh = 64000, 83 .refresh = 64000,
80 .cas_latency = 3, 84 .cas_latency = 3,
81}; 85 }, { /* Samsung KM416S4030CT */
82 86 .name = "KM416S4030CT",
83static struct sdram_params samsung_km416s4030ct __initdata = { 87 .rows = 13,
84 .rows = 13, 88 .tck = 8,
85 .tck = 8, 89 .trcd = 24, /* 3 CLKs */
86 .trcd = 24, /* 3 CLKs */ 90 .trp = 24, /* 3 CLKs */
87 .trp = 24, /* 3 CLKs */ 91 .twr = 16, /* Trdl: 2 CLKs */
88 .twr = 16, /* Trdl: 2 CLKs */ 92 .refresh = 64000,
89 .refresh = 64000, 93 .cas_latency = 3,
90 .cas_latency = 3, 94 }, { /* Winbond W982516AH75L CL3 */
91}; 95 .name = "W982516AH75L",
92 96 .rows = 16,
93static struct sdram_params wbond_w982516ah75l_cl3_params __initdata = { 97 .tck = 8,
94 .rows = 16, 98 .trcd = 20,
95 .tck = 8, 99 .trp = 20,
96 .trcd = 20, 100 .twr = 8,
97 .trp = 20, 101 .refresh = 64000,
98 .twr = 8, 102 .cas_latency = 3,
99 .refresh = 64000, 103 },
100 .cas_latency = 3,
101}; 104};
102 105
103static struct sdram_params sdram_params; 106static struct sdram_params sdram_params;
@@ -336,19 +339,36 @@ static struct cpufreq_driver sa1110_driver = {
336 .name = "sa1110", 339 .name = "sa1110",
337}; 340};
338 341
342static struct sdram_params *sa1110_find_sdram(const char *name)
343{
344 struct sdram_params *sdram;
345
346 for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl); sdram++)
347 if (strcmp(name, sdram->name) == 0)
348 return sdram;
349
350 return NULL;
351}
352
353static char sdram_name[16];
354
339static int __init sa1110_clk_init(void) 355static int __init sa1110_clk_init(void)
340{ 356{
341 struct sdram_params *sdram = NULL; 357 struct sdram_params *sdram;
358 const char *name = sdram_name;
342 359
343 if (machine_is_assabet()) 360 if (!name[0]) {
344 sdram = &tc59sm716_cl3_params; 361 if (machine_is_assabet())
362 name = "TC59SM716-CL3";
345 363
346 if (machine_is_pt_system3()) 364 if (machine_is_pt_system3())
347 sdram = &samsung_k4s641632d_tc75; 365 name = "K4S641632D";
348 366
349 if (machine_is_h3100()) 367 if (machine_is_h3100())
350 sdram = &samsung_km416s4030ct; 368 name = "KM416S4030CT";
369 }
351 370
371 sdram = sa1110_find_sdram(name);
352 if (sdram) { 372 if (sdram) {
353 printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d" 373 printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
354 " twr: %d refresh: %d cas_latency: %d\n", 374 " twr: %d refresh: %d cas_latency: %d\n",
@@ -363,4 +383,5 @@ static int __init sa1110_clk_init(void)
363 return 0; 383 return 0;
364} 384}
365 385
386module_param_string(sdram, sdram_name, sizeof(sdram_name), 0);
366arch_initcall(sa1110_clk_init); 387arch_initcall(sa1110_clk_init);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c4bca753165b..5f80f184cd32 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -121,8 +121,8 @@ config CPU_ARM925T
121# ARM926T 121# ARM926T
122config CPU_ARM926T 122config CPU_ARM926T
123 bool "Support ARM926T processor" 123 bool "Support ARM926T processor"
124 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 124 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
125 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 125 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
126 select CPU_32v5 126 select CPU_32v5
127 select CPU_ABRT_EV5TJ 127 select CPU_ABRT_EV5TJ
128 select CPU_CACHE_VIVT 128 select CPU_CACHE_VIVT
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 7691cfdba567..7eac87f05180 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -27,7 +27,16 @@
27 27
28#include <asm/cacheflush.h> 28#include <asm/cacheflush.h>
29#include <asm/io.h> 29#include <asm/io.h>
30#include <asm/mmu_context.h>
31#include <asm/pgalloc.h>
30#include <asm/tlbflush.h> 32#include <asm/tlbflush.h>
33#include <asm/sizes.h>
34
35/*
36 * Used by ioremap() and iounmap() code to mark (super)section-mapped
37 * I/O regions in vm_struct->flags field.
38 */
39#define VM_ARM_SECTION_MAPPING 0x80000000
31 40
32static inline void 41static inline void
33remap_area_pte(pte_t * pte, unsigned long address, unsigned long size, 42remap_area_pte(pte_t * pte, unsigned long address, unsigned long size,
@@ -113,10 +122,168 @@ remap_area_pages(unsigned long start, unsigned long pfn,
113 dir++; 122 dir++;
114 } while (address && (address < end)); 123 } while (address && (address < end));
115 124
116 flush_cache_vmap(start, end);
117 return err; 125 return err;
118} 126}
119 127
128
129void __check_kvm_seq(struct mm_struct *mm)
130{
131 unsigned int seq;
132
133 do {
134 seq = init_mm.context.kvm_seq;
135 memcpy(pgd_offset(mm, VMALLOC_START),
136 pgd_offset_k(VMALLOC_START),
137 sizeof(pgd_t) * (pgd_index(VMALLOC_END) -
138 pgd_index(VMALLOC_START)));
139 mm->context.kvm_seq = seq;
140 } while (seq != init_mm.context.kvm_seq);
141}
142
143#ifndef CONFIG_SMP
144/*
145 * Section support is unsafe on SMP - If you iounmap and ioremap a region,
146 * the other CPUs will not see this change until their next context switch.
147 * Meanwhile, (eg) if an interrupt comes in on one of those other CPUs
148 * which requires the new ioremap'd region to be referenced, the CPU will
149 * reference the _old_ region.
150 *
151 * Note that get_vm_area() allocates a guard 4K page, so we need to mask
152 * the size back to 1MB aligned or we will overflow in the loop below.
153 */
154static void unmap_area_sections(unsigned long virt, unsigned long size)
155{
156 unsigned long addr = virt, end = virt + (size & ~SZ_1M);
157 pgd_t *pgd;
158
159 flush_cache_vunmap(addr, end);
160 pgd = pgd_offset_k(addr);
161 do {
162 pmd_t pmd, *pmdp = pmd_offset(pgd, addr);
163
164 pmd = *pmdp;
165 if (!pmd_none(pmd)) {
166 /*
167 * Clear the PMD from the page table, and
168 * increment the kvm sequence so others
169 * notice this change.
170 *
171 * Note: this is still racy on SMP machines.
172 */
173 pmd_clear(pmdp);
174 init_mm.context.kvm_seq++;
175
176 /*
177 * Free the page table, if there was one.
178 */
179 if ((pmd_val(pmd) & PMD_TYPE_MASK) == PMD_TYPE_TABLE)
180 pte_free_kernel(pmd_page_kernel(pmd));
181 }
182
183 addr += PGDIR_SIZE;
184 pgd++;
185 } while (addr < end);
186
187 /*
188 * Ensure that the active_mm is up to date - we want to
189 * catch any use-after-iounmap cases.
190 */
191 if (current->active_mm->context.kvm_seq != init_mm.context.kvm_seq)
192 __check_kvm_seq(current->active_mm);
193
194 flush_tlb_kernel_range(virt, end);
195}
196
197static int
198remap_area_sections(unsigned long virt, unsigned long pfn,
199 unsigned long size, unsigned long flags)
200{
201 unsigned long prot, addr = virt, end = virt + size;
202 pgd_t *pgd;
203
204 /*
205 * Remove and free any PTE-based mapping, and
206 * sync the current kernel mapping.
207 */
208 unmap_area_sections(virt, size);
209
210 prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO) |
211 (flags & (L_PTE_CACHEABLE | L_PTE_BUFFERABLE));
212
213 /*
214 * ARMv6 and above need XN set to prevent speculative prefetches
215 * hitting IO.
216 */
217 if (cpu_architecture() >= CPU_ARCH_ARMv6)
218 prot |= PMD_SECT_XN;
219
220 pgd = pgd_offset_k(addr);
221 do {
222 pmd_t *pmd = pmd_offset(pgd, addr);
223
224 pmd[0] = __pmd(__pfn_to_phys(pfn) | prot);
225 pfn += SZ_1M >> PAGE_SHIFT;
226 pmd[1] = __pmd(__pfn_to_phys(pfn) | prot);
227 pfn += SZ_1M >> PAGE_SHIFT;
228 flush_pmd_entry(pmd);
229
230 addr += PGDIR_SIZE;
231 pgd++;
232 } while (addr < end);
233
234 return 0;
235}
236
237static int
238remap_area_supersections(unsigned long virt, unsigned long pfn,
239 unsigned long size, unsigned long flags)
240{
241 unsigned long prot, addr = virt, end = virt + size;
242 pgd_t *pgd;
243
244 /*
245 * Remove and free any PTE-based mapping, and
246 * sync the current kernel mapping.
247 */
248 unmap_area_sections(virt, size);
249
250 prot = PMD_TYPE_SECT | PMD_SECT_SUPER | PMD_SECT_AP_WRITE |
251 PMD_DOMAIN(DOMAIN_IO) |
252 (flags & (L_PTE_CACHEABLE | L_PTE_BUFFERABLE));
253
254 /*
255 * ARMv6 and above need XN set to prevent speculative prefetches
256 * hitting IO.
257 */
258 if (cpu_architecture() >= CPU_ARCH_ARMv6)
259 prot |= PMD_SECT_XN;
260
261 pgd = pgd_offset_k(virt);
262 do {
263 unsigned long super_pmd_val, i;
264
265 super_pmd_val = __pfn_to_phys(pfn) | prot;
266 super_pmd_val |= ((pfn >> (32 - PAGE_SHIFT)) & 0xf) << 20;
267
268 for (i = 0; i < 8; i++) {
269 pmd_t *pmd = pmd_offset(pgd, addr);
270
271 pmd[0] = __pmd(super_pmd_val);
272 pmd[1] = __pmd(super_pmd_val);
273 flush_pmd_entry(pmd);
274
275 addr += PGDIR_SIZE;
276 pgd++;
277 }
278
279 pfn += SUPERSECTION_SIZE >> PAGE_SHIFT;
280 } while (addr < end);
281
282 return 0;
283}
284#endif
285
286
120/* 287/*
121 * Remap an arbitrary physical address space into the kernel virtual 288 * Remap an arbitrary physical address space into the kernel virtual
122 * address space. Needed when the kernel wants to access high addresses 289 * address space. Needed when the kernel wants to access high addresses
@@ -133,18 +300,42 @@ void __iomem *
133__ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size, 300__ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
134 unsigned long flags) 301 unsigned long flags)
135{ 302{
303 int err;
136 unsigned long addr; 304 unsigned long addr;
137 struct vm_struct * area; 305 struct vm_struct * area;
306 unsigned int cr = get_cr();
307
308 /*
309 * High mappings must be supersection aligned
310 */
311 if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK))
312 return NULL;
138 313
139 area = get_vm_area(size, VM_IOREMAP); 314 area = get_vm_area(size, VM_IOREMAP);
140 if (!area) 315 if (!area)
141 return NULL; 316 return NULL;
142 addr = (unsigned long)area->addr; 317 addr = (unsigned long)area->addr;
143 if (remap_area_pages(addr, pfn, size, flags)) { 318
319#ifndef CONFIG_SMP
320 if ((((cpu_architecture() >= CPU_ARCH_ARMv6) && (cr & CR_XP)) ||
321 cpu_is_xsc3()) &&
322 !((__pfn_to_phys(pfn) | size | addr) & ~SUPERSECTION_MASK)) {
323 area->flags |= VM_ARM_SECTION_MAPPING;
324 err = remap_area_supersections(addr, pfn, size, flags);
325 } else if (!((__pfn_to_phys(pfn) | size | addr) & ~PMD_MASK)) {
326 area->flags |= VM_ARM_SECTION_MAPPING;
327 err = remap_area_sections(addr, pfn, size, flags);
328 } else
329#endif
330 err = remap_area_pages(addr, pfn, size, flags);
331
332 if (err) {
144 vunmap((void *)addr); 333 vunmap((void *)addr);
145 return NULL; 334 return NULL;
146 } 335 }
147 return (void __iomem *) (offset + (char *)addr); 336
337 flush_cache_vmap(addr, addr + size);
338 return (void __iomem *) (offset + addr);
148} 339}
149EXPORT_SYMBOL(__ioremap_pfn); 340EXPORT_SYMBOL(__ioremap_pfn);
150 341
@@ -173,6 +364,34 @@ EXPORT_SYMBOL(__ioremap);
173 364
174void __iounmap(void __iomem *addr) 365void __iounmap(void __iomem *addr)
175{ 366{
176 vunmap((void *)(PAGE_MASK & (unsigned long)addr)); 367 struct vm_struct **p, *tmp;
368 unsigned int section_mapping = 0;
369
370 addr = (void __iomem *)(PAGE_MASK & (unsigned long)addr);
371
372 /*
373 * If this is a section based mapping we need to handle it
374 * specially as the VM subysystem does not know how to handle
375 * such a beast. We need the lock here b/c we need to clear
376 * all the mappings before the area can be reclaimed
377 * by someone else.
378 */
379 write_lock(&vmlist_lock);
380 for (p = &vmlist ; (tmp = *p) ; p = &tmp->next) {
381 if((tmp->flags & VM_IOREMAP) && (tmp->addr == addr)) {
382 if (tmp->flags & VM_ARM_SECTION_MAPPING) {
383 *p = tmp->next;
384 unmap_area_sections((unsigned long)tmp->addr,
385 tmp->size);
386 kfree(tmp);
387 section_mapping = 1;
388 }
389 break;
390 }
391 }
392 write_unlock(&vmlist_lock);
393
394 if (!section_mapping)
395 vunmap(addr);
177} 396}
178EXPORT_SYMBOL(__iounmap); 397EXPORT_SYMBOL(__iounmap);
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index b0242c6ea066..38769f5862bc 100644
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -302,16 +302,16 @@ static struct mem_types mem_types[] __initdata = {
302 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 302 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
303 L_PTE_WRITE, 303 L_PTE_WRITE,
304 .prot_l1 = PMD_TYPE_TABLE, 304 .prot_l1 = PMD_TYPE_TABLE,
305 .prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED | 305 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
306 PMD_SECT_AP_WRITE, 306 PMD_SECT_AP_WRITE,
307 .domain = DOMAIN_IO, 307 .domain = DOMAIN_IO,
308 }, 308 },
309 [MT_CACHECLEAN] = { 309 [MT_CACHECLEAN] = {
310 .prot_sect = PMD_TYPE_SECT, 310 .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
311 .domain = DOMAIN_KERNEL, 311 .domain = DOMAIN_KERNEL,
312 }, 312 },
313 [MT_MINICLEAN] = { 313 [MT_MINICLEAN] = {
314 .prot_sect = PMD_TYPE_SECT | PMD_SECT_MINICACHE, 314 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_MINICACHE,
315 .domain = DOMAIN_KERNEL, 315 .domain = DOMAIN_KERNEL,
316 }, 316 },
317 [MT_LOW_VECTORS] = { 317 [MT_LOW_VECTORS] = {
@@ -327,25 +327,25 @@ static struct mem_types mem_types[] __initdata = {
327 .domain = DOMAIN_USER, 327 .domain = DOMAIN_USER,
328 }, 328 },
329 [MT_MEMORY] = { 329 [MT_MEMORY] = {
330 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 330 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_AP_WRITE,
331 .domain = DOMAIN_KERNEL, 331 .domain = DOMAIN_KERNEL,
332 }, 332 },
333 [MT_ROM] = { 333 [MT_ROM] = {
334 .prot_sect = PMD_TYPE_SECT, 334 .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
335 .domain = DOMAIN_KERNEL, 335 .domain = DOMAIN_KERNEL,
336 }, 336 },
337 [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */ 337 [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
338 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 338 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
339 L_PTE_WRITE, 339 L_PTE_WRITE,
340 .prot_l1 = PMD_TYPE_TABLE, 340 .prot_l1 = PMD_TYPE_TABLE,
341 .prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED | 341 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
342 PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE | 342 PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
343 PMD_SECT_TEX(1), 343 PMD_SECT_TEX(1),
344 .domain = DOMAIN_IO, 344 .domain = DOMAIN_IO,
345 }, 345 },
346 [MT_NONSHARED_DEVICE] = { 346 [MT_NONSHARED_DEVICE] = {
347 .prot_l1 = PMD_TYPE_TABLE, 347 .prot_l1 = PMD_TYPE_TABLE,
348 .prot_sect = PMD_TYPE_SECT | PMD_SECT_NONSHARED_DEV | 348 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_NONSHARED_DEV |
349 PMD_SECT_AP_WRITE, 349 PMD_SECT_AP_WRITE,
350 .domain = DOMAIN_IO, 350 .domain = DOMAIN_IO,
351 } 351 }
@@ -375,14 +375,21 @@ void __init build_mem_type_table(void)
375 ecc_mask = 0; 375 ecc_mask = 0;
376 } 376 }
377 377
378 if (cpu_arch <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) { 378 /*
379 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 379 * Xscale must not have PMD bit 4 set for section mappings.
380 */
381 if (cpu_is_xscale())
382 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
383 mem_types[i].prot_sect &= ~PMD_BIT4;
384
385 /*
386 * ARMv5 and lower, excluding Xscale, bit 4 must be set for
387 * page tables.
388 */
389 if (cpu_arch < CPU_ARCH_ARMv6 && !cpu_is_xscale())
390 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
380 if (mem_types[i].prot_l1) 391 if (mem_types[i].prot_l1)
381 mem_types[i].prot_l1 |= PMD_BIT4; 392 mem_types[i].prot_l1 |= PMD_BIT4;
382 if (mem_types[i].prot_sect)
383 mem_types[i].prot_sect |= PMD_BIT4;
384 }
385 }
386 393
387 cp = &cache_policies[cachepolicy]; 394 cp = &cache_policies[cachepolicy];
388 kern_pgprot = user_pgprot = cp->pte; 395 kern_pgprot = user_pgprot = cp->pte;
@@ -406,8 +413,8 @@ void __init build_mem_type_table(void)
406 * bit 4 becomes XN which we must clear for the 413 * bit 4 becomes XN which we must clear for the
407 * kernel memory mapping. 414 * kernel memory mapping.
408 */ 415 */
409 mem_types[MT_MEMORY].prot_sect &= ~PMD_BIT4; 416 mem_types[MT_MEMORY].prot_sect &= ~PMD_SECT_XN;
410 mem_types[MT_ROM].prot_sect &= ~PMD_BIT4; 417 mem_types[MT_ROM].prot_sect &= ~PMD_SECT_XN;
411 418
412 /* 419 /*
413 * Mark cache clean areas and XIP ROM read only 420 * Mark cache clean areas and XIP ROM read only
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index cc609666df05..700297ae4a55 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -439,11 +439,12 @@ __arm1020_setup:
439#ifdef CONFIG_MMU 439#ifdef CONFIG_MMU
440 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 440 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
441#endif 441#endif
442
443 adr r5, arm1020_crval
444 ldmia r5, {r5, r6}
442 mrc p15, 0, r0, c1, c0 @ get control register v4 445 mrc p15, 0, r0, c1, c0 @ get control register v4
443 ldr r5, arm1020_cr1_clear
444 bic r0, r0, r5 446 bic r0, r0, r5
445 ldr r5, arm1020_cr1_set 447 orr r0, r0, r6
446 orr r0, r0, r5
447#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 448#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
448 orr r0, r0, #0x4000 @ .R.. .... .... .... 449 orr r0, r0, #0x4000 @ .R.. .... .... ....
449#endif 450#endif
@@ -455,12 +456,9 @@ __arm1020_setup:
455 * .RVI ZFRS BLDP WCAM 456 * .RVI ZFRS BLDP WCAM
456 * .011 1001 ..11 0101 457 * .011 1001 ..11 0101
457 */ 458 */
458 .type arm1020_cr1_clear, #object 459 .type arm1020_crval, #object
459 .type arm1020_cr1_set, #object 460arm1020_crval:
460arm1020_cr1_clear: 461 crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
461 .word 0x593f
462arm1020_cr1_set:
463 .word 0x3935
464 462
465 __INITDATA 463 __INITDATA
466 464
@@ -526,6 +524,9 @@ __arm1020_proc_info:
526 .long PMD_TYPE_SECT | \ 524 .long PMD_TYPE_SECT | \
527 PMD_SECT_AP_WRITE | \ 525 PMD_SECT_AP_WRITE | \
528 PMD_SECT_AP_READ 526 PMD_SECT_AP_READ
527 .long PMD_TYPE_SECT | \
528 PMD_SECT_AP_WRITE | \
529 PMD_SECT_AP_READ
529 b __arm1020_setup 530 b __arm1020_setup
530 .long cpu_arch_name 531 .long cpu_arch_name
531 .long cpu_elf_name 532 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 117a946c28c8..0c33a5ed5a61 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -421,11 +421,11 @@ __arm1020e_setup:
421#ifdef CONFIG_MMU 421#ifdef CONFIG_MMU
422 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 422 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
423#endif 423#endif
424 adr r5, arm1020e_crval
425 ldmia r5, {r5, r6}
424 mrc p15, 0, r0, c1, c0 @ get control register v4 426 mrc p15, 0, r0, c1, c0 @ get control register v4
425 ldr r5, arm1020e_cr1_clear
426 bic r0, r0, r5 427 bic r0, r0, r5
427 ldr r5, arm1020e_cr1_set 428 orr r0, r0, r6
428 orr r0, r0, r5
429#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 429#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
430 orr r0, r0, #0x4000 @ .R.. .... .... .... 430 orr r0, r0, #0x4000 @ .R.. .... .... ....
431#endif 431#endif
@@ -437,12 +437,9 @@ __arm1020e_setup:
437 * .RVI ZFRS BLDP WCAM 437 * .RVI ZFRS BLDP WCAM
438 * .011 1001 ..11 0101 438 * .011 1001 ..11 0101
439 */ 439 */
440 .type arm1020e_cr1_clear, #object 440 .type arm1020e_crval, #object
441 .type arm1020e_cr1_set, #object 441arm1020e_crval:
442arm1020e_cr1_clear: 442 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
443 .word 0x5f3f
444arm1020e_cr1_set:
445 .word 0x3935
446 443
447 __INITDATA 444 __INITDATA
448 445
@@ -476,25 +473,7 @@ cpu_elf_name:
476 473
477 .type cpu_arm1020e_name, #object 474 .type cpu_arm1020e_name, #object
478cpu_arm1020e_name: 475cpu_arm1020e_name:
479 .ascii "ARM1020E" 476 .asciz "ARM1020E"
480#ifndef CONFIG_CPU_ICACHE_DISABLE
481 .ascii "i"
482#endif
483#ifndef CONFIG_CPU_DCACHE_DISABLE
484 .ascii "d"
485#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
486 .ascii "(wt)"
487#else
488 .ascii "(wb)"
489#endif
490#endif
491#ifndef CONFIG_CPU_BPREDICT_DISABLE
492 .ascii "B"
493#endif
494#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
495 .ascii "RR"
496#endif
497 .ascii "\0"
498 .size cpu_arm1020e_name, . - cpu_arm1020e_name 477 .size cpu_arm1020e_name, . - cpu_arm1020e_name
499 478
500 .align 479 .align
@@ -509,6 +488,10 @@ __arm1020e_proc_info:
509 PMD_BIT4 | \ 488 PMD_BIT4 | \
510 PMD_SECT_AP_WRITE | \ 489 PMD_SECT_AP_WRITE | \
511 PMD_SECT_AP_READ 490 PMD_SECT_AP_READ
491 .long PMD_TYPE_SECT | \
492 PMD_BIT4 | \
493 PMD_SECT_AP_WRITE | \
494 PMD_SECT_AP_READ
512 b __arm1020e_setup 495 b __arm1020e_setup
513 .long cpu_arch_name 496 .long cpu_arch_name
514 .long cpu_elf_name 497 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 39b7c102180a..566a55653072 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -403,11 +403,11 @@ __arm1022_setup:
403#ifdef CONFIG_MMU 403#ifdef CONFIG_MMU
404 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 404 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
405#endif 405#endif
406 adr r5, arm1022_crval
407 ldmia r5, {r5, r6}
406 mrc p15, 0, r0, c1, c0 @ get control register v4 408 mrc p15, 0, r0, c1, c0 @ get control register v4
407 ldr r5, arm1022_cr1_clear
408 bic r0, r0, r5 409 bic r0, r0, r5
409 ldr r5, arm1022_cr1_set 410 orr r0, r0, r6
410 orr r0, r0, r5
411#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 411#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
412 orr r0, r0, #0x4000 @ .R.............. 412 orr r0, r0, #0x4000 @ .R..............
413#endif 413#endif
@@ -420,12 +420,9 @@ __arm1022_setup:
420 * .011 1001 ..11 0101 420 * .011 1001 ..11 0101
421 * 421 *
422 */ 422 */
423 .type arm1022_cr1_clear, #object 423 .type arm1022_crval, #object
424 .type arm1022_cr1_set, #object 424arm1022_crval:
425arm1022_cr1_clear: 425 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
426 .word 0x7f3f
427arm1022_cr1_set:
428 .word 0x3935
429 426
430 __INITDATA 427 __INITDATA
431 428
@@ -459,25 +456,7 @@ cpu_elf_name:
459 456
460 .type cpu_arm1022_name, #object 457 .type cpu_arm1022_name, #object
461cpu_arm1022_name: 458cpu_arm1022_name:
462 .ascii "arm1022" 459 .asciz "ARM1022"
463#ifndef CONFIG_CPU_ICACHE_DISABLE
464 .ascii "i"
465#endif
466#ifndef CONFIG_CPU_DCACHE_DISABLE
467 .ascii "d"
468#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
469 .ascii "(wt)"
470#else
471 .ascii "(wb)"
472#endif
473#endif
474#ifndef CONFIG_CPU_BPREDICT_DISABLE
475 .ascii "B"
476#endif
477#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
478 .ascii "RR"
479#endif
480 .ascii "\0"
481 .size cpu_arm1022_name, . - cpu_arm1022_name 460 .size cpu_arm1022_name, . - cpu_arm1022_name
482 461
483 .align 462 .align
@@ -492,6 +471,10 @@ __arm1022_proc_info:
492 PMD_BIT4 | \ 471 PMD_BIT4 | \
493 PMD_SECT_AP_WRITE | \ 472 PMD_SECT_AP_WRITE | \
494 PMD_SECT_AP_READ 473 PMD_SECT_AP_READ
474 .long PMD_TYPE_SECT | \
475 PMD_BIT4 | \
476 PMD_SECT_AP_WRITE | \
477 PMD_SECT_AP_READ
495 b __arm1022_setup 478 b __arm1022_setup
496 .long cpu_arch_name 479 .long cpu_arch_name
497 .long cpu_elf_name 480 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 33e1ab8eb1d6..6ea76321d0df 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -398,11 +398,11 @@ __arm1026_setup:
398 mov r0, #4 @ explicitly disable writeback 398 mov r0, #4 @ explicitly disable writeback
399 mcr p15, 7, r0, c15, c0, 0 399 mcr p15, 7, r0, c15, c0, 0
400#endif 400#endif
401 adr r5, arm1026_crval
402 ldmia r5, {r5, r6}
401 mrc p15, 0, r0, c1, c0 @ get control register v4 403 mrc p15, 0, r0, c1, c0 @ get control register v4
402 ldr r5, arm1026_cr1_clear
403 bic r0, r0, r5 404 bic r0, r0, r5
404 ldr r5, arm1026_cr1_set 405 orr r0, r0, r6
405 orr r0, r0, r5
406#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 406#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
407 orr r0, r0, #0x4000 @ .R.. .... .... .... 407 orr r0, r0, #0x4000 @ .R.. .... .... ....
408#endif 408#endif
@@ -415,12 +415,9 @@ __arm1026_setup:
415 * .011 1001 ..11 0101 415 * .011 1001 ..11 0101
416 * 416 *
417 */ 417 */
418 .type arm1026_cr1_clear, #object 418 .type arm1026_crval, #object
419 .type arm1026_cr1_set, #object 419arm1026_crval:
420arm1026_cr1_clear: 420 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
421 .word 0x7f3f
422arm1026_cr1_set:
423 .word 0x3935
424 421
425 __INITDATA 422 __INITDATA
426 423
@@ -455,25 +452,7 @@ cpu_elf_name:
455 452
456 .type cpu_arm1026_name, #object 453 .type cpu_arm1026_name, #object
457cpu_arm1026_name: 454cpu_arm1026_name:
458 .ascii "ARM1026EJ-S" 455 .asciz "ARM1026EJ-S"
459#ifndef CONFIG_CPU_ICACHE_DISABLE
460 .ascii "i"
461#endif
462#ifndef CONFIG_CPU_DCACHE_DISABLE
463 .ascii "d"
464#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
465 .ascii "(wt)"
466#else
467 .ascii "(wb)"
468#endif
469#endif
470#ifndef CONFIG_CPU_BPREDICT_DISABLE
471 .ascii "B"
472#endif
473#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
474 .ascii "RR"
475#endif
476 .ascii "\0"
477 .size cpu_arm1026_name, . - cpu_arm1026_name 456 .size cpu_arm1026_name, . - cpu_arm1026_name
478 457
479 .align 458 .align
@@ -488,6 +467,10 @@ __arm1026_proc_info:
488 PMD_BIT4 | \ 467 PMD_BIT4 | \
489 PMD_SECT_AP_WRITE | \ 468 PMD_SECT_AP_WRITE | \
490 PMD_SECT_AP_READ 469 PMD_SECT_AP_READ
470 .long PMD_TYPE_SECT | \
471 PMD_BIT4 | \
472 PMD_SECT_AP_WRITE | \
473 PMD_SECT_AP_READ
491 b __arm1026_setup 474 b __arm1026_setup
492 .long cpu_arch_name 475 .long cpu_arch_name
493 .long cpu_elf_name 476 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 7a705edfa4b2..0432e4806888 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -355,6 +355,10 @@ __arm6_proc_info:
355 .long 0x41560600 355 .long 0x41560600
356 .long 0xfffffff0 356 .long 0xfffffff0
357 .long 0x00000c1e 357 .long 0x00000c1e
358 .long PMD_TYPE_SECT | \
359 PMD_BIT4 | \
360 PMD_SECT_AP_WRITE | \
361 PMD_SECT_AP_READ
358 b __arm6_setup 362 b __arm6_setup
359 .long cpu_arch_name 363 .long cpu_arch_name
360 .long cpu_elf_name 364 .long cpu_elf_name
@@ -371,6 +375,10 @@ __arm610_proc_info:
371 .long 0x41560610 375 .long 0x41560610
372 .long 0xfffffff0 376 .long 0xfffffff0
373 .long 0x00000c1e 377 .long 0x00000c1e
378 .long PMD_TYPE_SECT | \
379 PMD_BIT4 | \
380 PMD_SECT_AP_WRITE | \
381 PMD_SECT_AP_READ
374 b __arm6_setup 382 b __arm6_setup
375 .long cpu_arch_name 383 .long cpu_arch_name
376 .long cpu_elf_name 384 .long cpu_elf_name
@@ -387,6 +395,10 @@ __arm7_proc_info:
387 .long 0x41007000 395 .long 0x41007000
388 .long 0xffffff00 396 .long 0xffffff00
389 .long 0x00000c1e 397 .long 0x00000c1e
398 .long PMD_TYPE_SECT | \
399 PMD_BIT4 | \
400 PMD_SECT_AP_WRITE | \
401 PMD_SECT_AP_READ
390 b __arm7_setup 402 b __arm7_setup
391 .long cpu_arch_name 403 .long cpu_arch_name
392 .long cpu_elf_name 404 .long cpu_elf_name
@@ -408,6 +420,10 @@ __arm710_proc_info:
408 PMD_BIT4 | \ 420 PMD_BIT4 | \
409 PMD_SECT_AP_WRITE | \ 421 PMD_SECT_AP_WRITE | \
410 PMD_SECT_AP_READ 422 PMD_SECT_AP_READ
423 .long PMD_TYPE_SECT | \
424 PMD_BIT4 | \
425 PMD_SECT_AP_WRITE | \
426 PMD_SECT_AP_READ
411 b __arm7_setup 427 b __arm7_setup
412 .long cpu_arch_name 428 .long cpu_arch_name
413 .long cpu_elf_name 429 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 86102467d37f..0e6946ab6e5b 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -169,11 +169,11 @@ __arm720_setup:
169#ifdef CONFIG_MMU 169#ifdef CONFIG_MMU
170 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) 170 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
171#endif 171#endif
172 adr r5, arm720_crval
173 ldmia r5, {r5, r6}
172 mrc p15, 0, r0, c1, c0 @ get control register 174 mrc p15, 0, r0, c1, c0 @ get control register
173 ldr r5, arm720_cr1_clear
174 bic r0, r0, r5 175 bic r0, r0, r5
175 ldr r5, arm720_cr1_set 176 orr r0, r0, r6
176 orr r0, r0, r5
177 mov pc, lr @ __ret (head.S) 177 mov pc, lr @ __ret (head.S)
178 .size __arm720_setup, . - __arm720_setup 178 .size __arm720_setup, . - __arm720_setup
179 179
@@ -183,12 +183,9 @@ __arm720_setup:
183 * ..1. 1001 ..11 1101 183 * ..1. 1001 ..11 1101
184 * 184 *
185 */ 185 */
186 .type arm720_cr1_clear, #object 186 .type arm720_crval, #object
187 .type arm720_cr1_set, #object 187arm720_crval:
188arm720_cr1_clear: 188 crval clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
189 .word 0x2f3f
190arm720_cr1_set:
191 .word 0x213d
192 189
193 __INITDATA 190 __INITDATA
194 191
@@ -246,6 +243,10 @@ __arm710_proc_info:
246 PMD_BIT4 | \ 243 PMD_BIT4 | \
247 PMD_SECT_AP_WRITE | \ 244 PMD_SECT_AP_WRITE | \
248 PMD_SECT_AP_READ 245 PMD_SECT_AP_READ
246 .long PMD_TYPE_SECT | \
247 PMD_BIT4 | \
248 PMD_SECT_AP_WRITE | \
249 PMD_SECT_AP_READ
249 b __arm710_setup @ cpu_flush 250 b __arm710_setup @ cpu_flush
250 .long cpu_arch_name @ arch_name 251 .long cpu_arch_name @ arch_name
251 .long cpu_elf_name @ elf_name 252 .long cpu_elf_name @ elf_name
@@ -267,6 +268,10 @@ __arm720_proc_info:
267 PMD_BIT4 | \ 268 PMD_BIT4 | \
268 PMD_SECT_AP_WRITE | \ 269 PMD_SECT_AP_WRITE | \
269 PMD_SECT_AP_READ 270 PMD_SECT_AP_READ
271 .long PMD_TYPE_SECT | \
272 PMD_BIT4 | \
273 PMD_SECT_AP_WRITE | \
274 PMD_SECT_AP_READ
270 b __arm720_setup @ cpu_flush 275 b __arm720_setup @ cpu_flush
271 .long cpu_arch_name @ arch_name 276 .long cpu_arch_name @ arch_name
272 .long cpu_elf_name @ elf_name 277 .long cpu_elf_name @ elf_name
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 6f0db29ab842..4adb46b3a4e0 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -390,11 +390,11 @@ __arm920_setup:
390#ifdef CONFIG_MMU 390#ifdef CONFIG_MMU
391 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 391 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
392#endif 392#endif
393 adr r5, arm920_crval
394 ldmia r5, {r5, r6}
393 mrc p15, 0, r0, c1, c0 @ get control register v4 395 mrc p15, 0, r0, c1, c0 @ get control register v4
394 ldr r5, arm920_cr1_clear
395 bic r0, r0, r5 396 bic r0, r0, r5
396 ldr r5, arm920_cr1_set 397 orr r0, r0, r6
397 orr r0, r0, r5
398 mov pc, lr 398 mov pc, lr
399 .size __arm920_setup, . - __arm920_setup 399 .size __arm920_setup, . - __arm920_setup
400 400
@@ -404,12 +404,9 @@ __arm920_setup:
404 * ..11 0001 ..11 0101 404 * ..11 0001 ..11 0101
405 * 405 *
406 */ 406 */
407 .type arm920_cr1_clear, #object 407 .type arm920_crval, #object
408 .type arm920_cr1_set, #object 408arm920_crval:
409arm920_cr1_clear: 409 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
410 .word 0x3f3f
411arm920_cr1_set:
412 .word 0x3135
413 410
414 __INITDATA 411 __INITDATA
415 412
@@ -443,19 +440,7 @@ cpu_elf_name:
443 440
444 .type cpu_arm920_name, #object 441 .type cpu_arm920_name, #object
445cpu_arm920_name: 442cpu_arm920_name:
446 .ascii "ARM920T" 443 .asciz "ARM920T"
447#ifndef CONFIG_CPU_ICACHE_DISABLE
448 .ascii "i"
449#endif
450#ifndef CONFIG_CPU_DCACHE_DISABLE
451 .ascii "d"
452#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
453 .ascii "(wt)"
454#else
455 .ascii "(wb)"
456#endif
457#endif
458 .ascii "\0"
459 .size cpu_arm920_name, . - cpu_arm920_name 444 .size cpu_arm920_name, . - cpu_arm920_name
460 445
461 .align 446 .align
@@ -472,6 +457,10 @@ __arm920_proc_info:
472 PMD_BIT4 | \ 457 PMD_BIT4 | \
473 PMD_SECT_AP_WRITE | \ 458 PMD_SECT_AP_WRITE | \
474 PMD_SECT_AP_READ 459 PMD_SECT_AP_READ
460 .long PMD_TYPE_SECT | \
461 PMD_BIT4 | \
462 PMD_SECT_AP_WRITE | \
463 PMD_SECT_AP_READ
475 b __arm920_setup 464 b __arm920_setup
476 .long cpu_arch_name 465 .long cpu_arch_name
477 .long cpu_elf_name 466 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 1ad464cc7bcb..571f082f0247 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -394,11 +394,11 @@ __arm922_setup:
394#ifdef CONFIG_MMU 394#ifdef CONFIG_MMU
395 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 395 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
396#endif 396#endif
397 adr r5, arm922_crval
398 ldmia r5, {r5, r6}
397 mrc p15, 0, r0, c1, c0 @ get control register v4 399 mrc p15, 0, r0, c1, c0 @ get control register v4
398 ldr r5, arm922_cr1_clear
399 bic r0, r0, r5 400 bic r0, r0, r5
400 ldr r5, arm922_cr1_set 401 orr r0, r0, r6
401 orr r0, r0, r5
402 mov pc, lr 402 mov pc, lr
403 .size __arm922_setup, . - __arm922_setup 403 .size __arm922_setup, . - __arm922_setup
404 404
@@ -408,12 +408,9 @@ __arm922_setup:
408 * ..11 0001 ..11 0101 408 * ..11 0001 ..11 0101
409 * 409 *
410 */ 410 */
411 .type arm922_cr1_clear, #object 411 .type arm922_crval, #object
412 .type arm922_cr1_set, #object 412arm922_crval:
413arm922_cr1_clear: 413 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
414 .word 0x3f3f
415arm922_cr1_set:
416 .word 0x3135
417 414
418 __INITDATA 415 __INITDATA
419 416
@@ -447,19 +444,7 @@ cpu_elf_name:
447 444
448 .type cpu_arm922_name, #object 445 .type cpu_arm922_name, #object
449cpu_arm922_name: 446cpu_arm922_name:
450 .ascii "ARM922T" 447 .asciz "ARM922T"
451#ifndef CONFIG_CPU_ICACHE_DISABLE
452 .ascii "i"
453#endif
454#ifndef CONFIG_CPU_DCACHE_DISABLE
455 .ascii "d"
456#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
457 .ascii "(wt)"
458#else
459 .ascii "(wb)"
460#endif
461#endif
462 .ascii "\0"
463 .size cpu_arm922_name, . - cpu_arm922_name 448 .size cpu_arm922_name, . - cpu_arm922_name
464 449
465 .align 450 .align
@@ -476,6 +461,10 @@ __arm922_proc_info:
476 PMD_BIT4 | \ 461 PMD_BIT4 | \
477 PMD_SECT_AP_WRITE | \ 462 PMD_SECT_AP_WRITE | \
478 PMD_SECT_AP_READ 463 PMD_SECT_AP_READ
464 .long PMD_TYPE_SECT | \
465 PMD_BIT4 | \
466 PMD_SECT_AP_WRITE | \
467 PMD_SECT_AP_READ
479 b __arm922_setup 468 b __arm922_setup
480 .long cpu_arch_name 469 .long cpu_arch_name
481 .long cpu_elf_name 470 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index a55d56ce2264..ad15f8503d51 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -454,11 +454,10 @@ __arm925_setup:
454 mcr p15, 7, r0, c15, c0, 0 454 mcr p15, 7, r0, c15, c0, 0
455#endif 455#endif
456 456
457 adr r5, {r5, r6}
457 mrc p15, 0, r0, c1, c0 @ get control register v4 458 mrc p15, 0, r0, c1, c0 @ get control register v4
458 ldr r5, arm925_cr1_clear
459 bic r0, r0, r5 459 bic r0, r0, r5
460 ldr r5, arm925_cr1_set 460 orr r0, r0, r6
461 orr r0, r0, r5
462#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 461#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
463 orr r0, r0, #0x4000 @ .1.. .... .... .... 462 orr r0, r0, #0x4000 @ .1.. .... .... ....
464#endif 463#endif
@@ -471,12 +470,9 @@ __arm925_setup:
471 * .011 0001 ..11 1101 470 * .011 0001 ..11 1101
472 * 471 *
473 */ 472 */
474 .type arm925_cr1_clear, #object 473 .type arm925_crval, #object
475 .type arm925_cr1_set, #object 474arm925_crval:
476arm925_cr1_clear: 475 crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
477 .word 0x7f3f
478arm925_cr1_set:
479 .word 0x313d
480 476
481 __INITDATA 477 __INITDATA
482 478
@@ -510,22 +506,7 @@ cpu_elf_name:
510 506
511 .type cpu_arm925_name, #object 507 .type cpu_arm925_name, #object
512cpu_arm925_name: 508cpu_arm925_name:
513 .ascii "ARM925T" 509 .asciz "ARM925T"
514#ifndef CONFIG_CPU_ICACHE_DISABLE
515 .ascii "i"
516#endif
517#ifndef CONFIG_CPU_DCACHE_DISABLE
518 .ascii "d"
519#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
520 .ascii "(wt)"
521#else
522 .ascii "(wb)"
523#endif
524#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
525 .ascii "RR"
526#endif
527#endif
528 .ascii "\0"
529 .size cpu_arm925_name, . - cpu_arm925_name 510 .size cpu_arm925_name, . - cpu_arm925_name
530 511
531 .align 512 .align
@@ -540,6 +521,10 @@ __arm925_proc_info:
540 PMD_BIT4 | \ 521 PMD_BIT4 | \
541 PMD_SECT_AP_WRITE | \ 522 PMD_SECT_AP_WRITE | \
542 PMD_SECT_AP_READ 523 PMD_SECT_AP_READ
524 .long PMD_TYPE_SECT | \
525 PMD_BIT4 | \
526 PMD_SECT_AP_WRITE | \
527 PMD_SECT_AP_READ
543 b __arm925_setup 528 b __arm925_setup
544 .long cpu_arch_name 529 .long cpu_arch_name
545 .long cpu_elf_name 530 .long cpu_elf_name
@@ -559,6 +544,10 @@ __arm915_proc_info:
559 PMD_BIT4 | \ 544 PMD_BIT4 | \
560 PMD_SECT_AP_WRITE | \ 545 PMD_SECT_AP_WRITE | \
561 PMD_SECT_AP_READ 546 PMD_SECT_AP_READ
547 .long PMD_TYPE_SECT | \
548 PMD_BIT4 | \
549 PMD_SECT_AP_WRITE | \
550 PMD_SECT_AP_READ
562 b __arm925_setup 551 b __arm925_setup
563 .long cpu_arch_name 552 .long cpu_arch_name
564 .long cpu_elf_name 553 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 20275967663d..1e89d4080474 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -403,11 +403,11 @@ __arm926_setup:
403 mcr p15, 7, r0, c15, c0, 0 403 mcr p15, 7, r0, c15, c0, 0
404#endif 404#endif
405 405
406 adr r5, arm926_crval
407 ldmia r5, {r5, r6}
406 mrc p15, 0, r0, c1, c0 @ get control register v4 408 mrc p15, 0, r0, c1, c0 @ get control register v4
407 ldr r5, arm926_cr1_clear
408 bic r0, r0, r5 409 bic r0, r0, r5
409 ldr r5, arm926_cr1_set 410 orr r0, r0, r6
410 orr r0, r0, r5
411#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 411#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
412 orr r0, r0, #0x4000 @ .1.. .... .... .... 412 orr r0, r0, #0x4000 @ .1.. .... .... ....
413#endif 413#endif
@@ -420,12 +420,9 @@ __arm926_setup:
420 * .011 0001 ..11 0101 420 * .011 0001 ..11 0101
421 * 421 *
422 */ 422 */
423 .type arm926_cr1_clear, #object 423 .type arm926_crval, #object
424 .type arm926_cr1_set, #object 424arm926_crval:
425arm926_cr1_clear: 425 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
426 .word 0x7f3f
427arm926_cr1_set:
428 .word 0x3135
429 426
430 __INITDATA 427 __INITDATA
431 428
@@ -459,22 +456,7 @@ cpu_elf_name:
459 456
460 .type cpu_arm926_name, #object 457 .type cpu_arm926_name, #object
461cpu_arm926_name: 458cpu_arm926_name:
462 .ascii "ARM926EJ-S" 459 .asciz "ARM926EJ-S"
463#ifndef CONFIG_CPU_ICACHE_DISABLE
464 .ascii "i"
465#endif
466#ifndef CONFIG_CPU_DCACHE_DISABLE
467 .ascii "d"
468#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
469 .ascii "(wt)"
470#else
471 .ascii "(wb)"
472#endif
473#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
474 .ascii "RR"
475#endif
476#endif
477 .ascii "\0"
478 .size cpu_arm926_name, . - cpu_arm926_name 460 .size cpu_arm926_name, . - cpu_arm926_name
479 461
480 .align 462 .align
@@ -491,6 +473,10 @@ __arm926_proc_info:
491 PMD_BIT4 | \ 473 PMD_BIT4 | \
492 PMD_SECT_AP_WRITE | \ 474 PMD_SECT_AP_WRITE | \
493 PMD_SECT_AP_READ 475 PMD_SECT_AP_READ
476 .long PMD_TYPE_SECT | \
477 PMD_BIT4 | \
478 PMD_SECT_AP_WRITE | \
479 PMD_SECT_AP_READ
494 b __arm926_setup 480 b __arm926_setup
495 .long cpu_arch_name 481 .long cpu_arch_name
496 .long cpu_elf_name 482 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 7cfc2604a1ee..9e2c89eb2115 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -49,3 +49,13 @@
49 .macro asid, rd, rn 49 .macro asid, rd, rn
50 and \rd, \rn, #255 50 and \rd, \rn, #255
51 .endm 51 .endm
52
53 .macro crval, clear, mmuset, ucset
54#ifdef CONFIG_MMU
55 .word \clear
56 .word \mmuset
57#else
58 .word \clear
59 .word \ucset
60#endif
61 .endm
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 5a760a2c629c..e812246277cf 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -185,11 +185,12 @@ __sa110_setup:
185#ifdef CONFIG_MMU 185#ifdef CONFIG_MMU
186 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4 186 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
187#endif 187#endif
188
189 adr r5, sa110_crval
190 ldmia r5, {r5, r6}
188 mrc p15, 0, r0, c1, c0 @ get control register v4 191 mrc p15, 0, r0, c1, c0 @ get control register v4
189 ldr r5, sa110_cr1_clear
190 bic r0, r0, r5 192 bic r0, r0, r5
191 ldr r5, sa110_cr1_set 193 orr r0, r0, r6
192 orr r0, r0, r5
193 mov pc, lr 194 mov pc, lr
194 .size __sa110_setup, . - __sa110_setup 195 .size __sa110_setup, . - __sa110_setup
195 196
@@ -199,12 +200,9 @@ __sa110_setup:
199 * ..01 0001 ..11 1101 200 * ..01 0001 ..11 1101
200 * 201 *
201 */ 202 */
202 .type sa110_cr1_clear, #object 203 .type sa110_crval, #object
203 .type sa110_cr1_set, #object 204sa110_crval:
204sa110_cr1_clear: 205 crval clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
205 .word 0x3f3f
206sa110_cr1_set:
207 .word 0x113d
208 206
209 __INITDATA 207 __INITDATA
210 208
@@ -255,6 +253,9 @@ __sa110_proc_info:
255 PMD_SECT_CACHEABLE | \ 253 PMD_SECT_CACHEABLE | \
256 PMD_SECT_AP_WRITE | \ 254 PMD_SECT_AP_WRITE | \
257 PMD_SECT_AP_READ 255 PMD_SECT_AP_READ
256 .long PMD_TYPE_SECT | \
257 PMD_SECT_AP_WRITE | \
258 PMD_SECT_AP_READ
258 b __sa110_setup 259 b __sa110_setup
259 .long cpu_arch_name 260 .long cpu_arch_name
260 .long cpu_elf_name 261 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 0a2107ad4c32..ba32cc6296a0 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -198,11 +198,11 @@ __sa1100_setup:
198#ifdef CONFIG_MMU 198#ifdef CONFIG_MMU
199 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 199 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
200#endif 200#endif
201 adr r5, sa1100_crval
202 ldmia r5, {r5, r6}
201 mrc p15, 0, r0, c1, c0 @ get control register v4 203 mrc p15, 0, r0, c1, c0 @ get control register v4
202 ldr r5, sa1100_cr1_clear
203 bic r0, r0, r5 204 bic r0, r0, r5
204 ldr r5, sa1100_cr1_set 205 orr r0, r0, r6
205 orr r0, r0, r5
206 mov pc, lr 206 mov pc, lr
207 .size __sa1100_setup, . - __sa1100_setup 207 .size __sa1100_setup, . - __sa1100_setup
208 208
@@ -212,12 +212,9 @@ __sa1100_setup:
212 * ..11 0001 ..11 1101 212 * ..11 0001 ..11 1101
213 * 213 *
214 */ 214 */
215 .type sa1100_cr1_clear, #object 215 .type sa1100_crval, #object
216 .type sa1100_cr1_set, #object 216sa1100_crval:
217sa1100_cr1_clear: 217 crval clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
218 .word 0x3f3f
219sa1100_cr1_set:
220 .word 0x313d
221 218
222 __INITDATA 219 __INITDATA
223 220
@@ -276,6 +273,9 @@ __sa1100_proc_info:
276 PMD_SECT_CACHEABLE | \ 273 PMD_SECT_CACHEABLE | \
277 PMD_SECT_AP_WRITE | \ 274 PMD_SECT_AP_WRITE | \
278 PMD_SECT_AP_READ 275 PMD_SECT_AP_READ
276 .long PMD_TYPE_SECT | \
277 PMD_SECT_AP_WRITE | \
278 PMD_SECT_AP_READ
279 b __sa1100_setup 279 b __sa1100_setup
280 .long cpu_arch_name 280 .long cpu_arch_name
281 .long cpu_elf_name 281 .long cpu_elf_name
@@ -296,6 +296,9 @@ __sa1110_proc_info:
296 PMD_SECT_CACHEABLE | \ 296 PMD_SECT_CACHEABLE | \
297 PMD_SECT_AP_WRITE | \ 297 PMD_SECT_AP_WRITE | \
298 PMD_SECT_AP_READ 298 PMD_SECT_AP_READ
299 .long PMD_TYPE_SECT | \
300 PMD_SECT_AP_WRITE | \
301 PMD_SECT_AP_READ
299 b __sa1100_setup 302 b __sa1100_setup
300 .long cpu_arch_name 303 .long cpu_arch_name
301 .long cpu_elf_name 304 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index ca13d4d05f65..6f72549f8843 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -212,11 +212,11 @@ __v6_setup:
212 orr r0, r0, #(0xf << 20) 212 orr r0, r0, #(0xf << 20)
213 mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP 213 mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP
214#endif 214#endif
215 adr r5, v6_crval
216 ldmia r5, {r5, r6}
215 mrc p15, 0, r0, c1, c0, 0 @ read control register 217 mrc p15, 0, r0, c1, c0, 0 @ read control register
216 ldr r5, v6_cr1_clear @ get mask for bits to clear
217 bic r0, r0, r5 @ clear bits them 218 bic r0, r0, r5 @ clear bits them
218 ldr r5, v6_cr1_set @ get mask for bits to set 219 orr r0, r0, r6 @ set them
219 orr r0, r0, r5 @ set them
220 mov pc, lr @ return to head.S:__ret 220 mov pc, lr @ return to head.S:__ret
221 221
222 /* 222 /*
@@ -225,12 +225,9 @@ __v6_setup:
225 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced 225 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
226 * 0 110 0011 1.00 .111 1101 < we want 226 * 0 110 0011 1.00 .111 1101 < we want
227 */ 227 */
228 .type v6_cr1_clear, #object 228 .type v6_crval, #object
229 .type v6_cr1_set, #object 229v6_crval:
230v6_cr1_clear: 230 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
231 .word 0x01e0fb7f
232v6_cr1_set:
233 .word 0x00c0387d
234 231
235 .type v6_processor_functions, #object 232 .type v6_processor_functions, #object
236ENTRY(v6_processor_functions) 233ENTRY(v6_processor_functions)
@@ -269,6 +266,10 @@ __v6_proc_info:
269 PMD_SECT_CACHEABLE | \ 266 PMD_SECT_CACHEABLE | \
270 PMD_SECT_AP_WRITE | \ 267 PMD_SECT_AP_WRITE | \
271 PMD_SECT_AP_READ 268 PMD_SECT_AP_READ
269 .long PMD_TYPE_SECT | \
270 PMD_SECT_XN | \
271 PMD_SECT_AP_WRITE | \
272 PMD_SECT_AP_READ
272 b __v6_setup 273 b __v6_setup
273 .long cpu_arch_name 274 .long cpu_arch_name
274 .long cpu_elf_name 275 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 8d32e21fe151..4ace2d8090c7 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -426,23 +426,26 @@ __xsc3_setup:
426 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache 426 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
427#endif 427#endif
428 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg 428 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
429
430 adr r5, xsc3_crval
431 ldmia r5, {r5, r6}
429 mrc p15, 0, r0, c1, c0, 0 @ get control register 432 mrc p15, 0, r0, c1, c0, 0 @ get control register
430 bic r0, r0, #0x0002 @ .... .... .... ..A. 433 bic r0, r0, r5 @ .... .... .... ..A.
431 orr r0, r0, #0x0005 @ .... .... .... .C.M 434 orr r0, r0, r6 @ .... .... .... .C.M
432#if BTB_ENABLE 435#if BTB_ENABLE
433 bic r0, r0, #0x0200 @ .... ..R. .... .... 436 orr r0, r0, #0x00000800 @ ..VI Z..S .... ....
434 orr r0, r0, #0x3900 @ ..VI Z..S .... ....
435#else
436 bic r0, r0, #0x0a00 @ .... Z.R. .... ....
437 orr r0, r0, #0x3100 @ ..VI ...S .... ....
438#endif 437#endif
439#if L2_CACHE_ENABLE 438#if L2_CACHE_ENABLE
440 orr r0, r0, #0x4000000 @ L2 enable 439 orr r0, r0, #0x04000000 @ L2 enable
441#endif 440#endif
442 mov pc, lr 441 mov pc, lr
443 442
444 .size __xsc3_setup, . - __xsc3_setup 443 .size __xsc3_setup, . - __xsc3_setup
445 444
445 .type xsc3_crval, #object
446xsc3_crval:
447 crval clear=0x04003b02, mmuset=0x00003105, ucset=0x00001100
448
446 __INITDATA 449 __INITDATA
447 450
448/* 451/*
@@ -487,7 +490,14 @@ cpu_xsc3_name:
487__xsc3_proc_info: 490__xsc3_proc_info:
488 .long 0x69056000 491 .long 0x69056000
489 .long 0xffffe000 492 .long 0xffffe000
490 .long 0x00000c0e 493 .long PMD_TYPE_SECT | \
494 PMD_SECT_BUFFERABLE | \
495 PMD_SECT_CACHEABLE | \
496 PMD_SECT_AP_WRITE | \
497 PMD_SECT_AP_READ
498 .long PMD_TYPE_SECT | \
499 PMD_SECT_AP_WRITE | \
500 PMD_SECT_AP_READ
491 b __xsc3_setup 501 b __xsc3_setup
492 .long cpu_arch_name 502 .long cpu_arch_name
493 .long cpu_elf_name 503 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 29bcc4dd6517..521538671f4c 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -138,17 +138,23 @@ ENTRY(cpu_xscale_proc_fin)
138 * to what would be the reset vector. 138 * to what would be the reset vector.
139 * 139 *
140 * loc: location to jump to for soft reset 140 * loc: location to jump to for soft reset
141 *
142 * Beware PXA270 erratum E7.
141 */ 143 */
142 .align 5 144 .align 5
143ENTRY(cpu_xscale_reset) 145ENTRY(cpu_xscale_reset)
144 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE 146 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
145 msr cpsr_c, r1 @ reset CPSR 147 msr cpsr_c, r1 @ reset CPSR
148 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
149 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
146 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 150 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
147 bic r1, r1, #0x0086 @ ........B....CA. 151 bic r1, r1, #0x0086 @ ........B....CA.
148 bic r1, r1, #0x3900 @ ..VIZ..S........ 152 bic r1, r1, #0x3900 @ ..VIZ..S........
153 sub pc, pc, #4 @ flush pipeline
154 @ *** cache line aligned ***
149 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 155 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
150 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
151 bic r1, r1, #0x0001 @ ...............M 156 bic r1, r1, #0x0001 @ ...............M
157 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
152 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 158 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
153 @ CAUTION: MMU turned off from this point. We count on the pipeline 159 @ CAUTION: MMU turned off from this point. We count on the pipeline
154 @ already containing those two last instructions to survive. 160 @ already containing those two last instructions to survive.
@@ -475,11 +481,12 @@ __xscale_setup:
475 orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde 481 orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
476 orr r0, r0, #1 << 13 @ Its undefined whether this 482 orr r0, r0, #1 << 13 @ Its undefined whether this
477 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes 483 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
484
485 adr r5, xscale_crval
486 ldmia r5, {r5, r6}
478 mrc p15, 0, r0, c1, c0, 0 @ get control register 487 mrc p15, 0, r0, c1, c0, 0 @ get control register
479 ldr r5, xscale_cr1_clear
480 bic r0, r0, r5 488 bic r0, r0, r5
481 ldr r5, xscale_cr1_set 489 orr r0, r0, r6
482 orr r0, r0, r5
483 mov pc, lr 490 mov pc, lr
484 .size __xscale_setup, . - __xscale_setup 491 .size __xscale_setup, . - __xscale_setup
485 492
@@ -489,12 +496,9 @@ __xscale_setup:
489 * ..11 1.01 .... .101 496 * ..11 1.01 .... .101
490 * 497 *
491 */ 498 */
492 .type xscale_cr1_clear, #object 499 .type xscale_crval, #object
493 .type xscale_cr1_set, #object 500xscale_crval:
494xscale_cr1_clear: 501 crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
495 .word 0x3b07
496xscale_cr1_set:
497 .word 0x3905
498 502
499 __INITDATA 503 __INITDATA
500 504
@@ -595,6 +599,9 @@ __80200_proc_info:
595 PMD_SECT_CACHEABLE | \ 599 PMD_SECT_CACHEABLE | \
596 PMD_SECT_AP_WRITE | \ 600 PMD_SECT_AP_WRITE | \
597 PMD_SECT_AP_READ 601 PMD_SECT_AP_READ
602 .long PMD_TYPE_SECT | \
603 PMD_SECT_AP_WRITE | \
604 PMD_SECT_AP_READ
598 b __xscale_setup 605 b __xscale_setup
599 .long cpu_arch_name 606 .long cpu_arch_name
600 .long cpu_elf_name 607 .long cpu_elf_name
@@ -615,6 +622,9 @@ __8032x_proc_info:
615 PMD_SECT_CACHEABLE | \ 622 PMD_SECT_CACHEABLE | \
616 PMD_SECT_AP_WRITE | \ 623 PMD_SECT_AP_WRITE | \
617 PMD_SECT_AP_READ 624 PMD_SECT_AP_READ
625 .long PMD_TYPE_SECT | \
626 PMD_SECT_AP_WRITE | \
627 PMD_SECT_AP_READ
618 b __xscale_setup 628 b __xscale_setup
619 .long cpu_arch_name 629 .long cpu_arch_name
620 .long cpu_elf_name 630 .long cpu_elf_name
@@ -635,6 +645,9 @@ __8033x_proc_info:
635 PMD_SECT_CACHEABLE | \ 645 PMD_SECT_CACHEABLE | \
636 PMD_SECT_AP_WRITE | \ 646 PMD_SECT_AP_WRITE | \
637 PMD_SECT_AP_READ 647 PMD_SECT_AP_READ
648 .long PMD_TYPE_SECT | \
649 PMD_SECT_AP_WRITE | \
650 PMD_SECT_AP_READ
638 b __xscale_setup 651 b __xscale_setup
639 .long cpu_arch_name 652 .long cpu_arch_name
640 .long cpu_elf_name 653 .long cpu_elf_name
@@ -655,6 +668,9 @@ __pxa250_proc_info:
655 PMD_SECT_CACHEABLE | \ 668 PMD_SECT_CACHEABLE | \
656 PMD_SECT_AP_WRITE | \ 669 PMD_SECT_AP_WRITE | \
657 PMD_SECT_AP_READ 670 PMD_SECT_AP_READ
671 .long PMD_TYPE_SECT | \
672 PMD_SECT_AP_WRITE | \
673 PMD_SECT_AP_READ
658 b __xscale_setup 674 b __xscale_setup
659 .long cpu_arch_name 675 .long cpu_arch_name
660 .long cpu_elf_name 676 .long cpu_elf_name
@@ -675,6 +691,9 @@ __pxa210_proc_info:
675 PMD_SECT_CACHEABLE | \ 691 PMD_SECT_CACHEABLE | \
676 PMD_SECT_AP_WRITE | \ 692 PMD_SECT_AP_WRITE | \
677 PMD_SECT_AP_READ 693 PMD_SECT_AP_READ
694 .long PMD_TYPE_SECT | \
695 PMD_SECT_AP_WRITE | \
696 PMD_SECT_AP_READ
678 b __xscale_setup 697 b __xscale_setup
679 .long cpu_arch_name 698 .long cpu_arch_name
680 .long cpu_elf_name 699 .long cpu_elf_name
@@ -695,6 +714,9 @@ __ixp2400_proc_info:
695 PMD_SECT_CACHEABLE | \ 714 PMD_SECT_CACHEABLE | \
696 PMD_SECT_AP_WRITE | \ 715 PMD_SECT_AP_WRITE | \
697 PMD_SECT_AP_READ 716 PMD_SECT_AP_READ
717 .long PMD_TYPE_SECT | \
718 PMD_SECT_AP_WRITE | \
719 PMD_SECT_AP_READ
698 b __xscale_setup 720 b __xscale_setup
699 .long cpu_arch_name 721 .long cpu_arch_name
700 .long cpu_elf_name 722 .long cpu_elf_name
@@ -715,6 +737,9 @@ __ixp2800_proc_info:
715 PMD_SECT_CACHEABLE | \ 737 PMD_SECT_CACHEABLE | \
716 PMD_SECT_AP_WRITE | \ 738 PMD_SECT_AP_WRITE | \
717 PMD_SECT_AP_READ 739 PMD_SECT_AP_READ
740 .long PMD_TYPE_SECT | \
741 PMD_SECT_AP_WRITE | \
742 PMD_SECT_AP_READ
718 b __xscale_setup 743 b __xscale_setup
719 .long cpu_arch_name 744 .long cpu_arch_name
720 .long cpu_elf_name 745 .long cpu_elf_name
@@ -735,6 +760,9 @@ __ixp42x_proc_info:
735 PMD_SECT_CACHEABLE | \ 760 PMD_SECT_CACHEABLE | \
736 PMD_SECT_AP_WRITE | \ 761 PMD_SECT_AP_WRITE | \
737 PMD_SECT_AP_READ 762 PMD_SECT_AP_READ
763 .long PMD_TYPE_SECT | \
764 PMD_SECT_AP_WRITE | \
765 PMD_SECT_AP_READ
738 b __xscale_setup 766 b __xscale_setup
739 .long cpu_arch_name 767 .long cpu_arch_name
740 .long cpu_elf_name 768 .long cpu_elf_name
@@ -750,7 +778,14 @@ __ixp42x_proc_info:
750__ixp46x_proc_info: 778__ixp46x_proc_info:
751 .long 0x69054200 779 .long 0x69054200
752 .long 0xffffff00 780 .long 0xffffff00
753 .long 0x00000c0e 781 .long PMD_TYPE_SECT | \
782 PMD_SECT_BUFFERABLE | \
783 PMD_SECT_CACHEABLE | \
784 PMD_SECT_AP_WRITE | \
785 PMD_SECT_AP_READ
786 .long PMD_TYPE_SECT | \
787 PMD_SECT_AP_WRITE | \
788 PMD_SECT_AP_READ
754 b __xscale_setup 789 b __xscale_setup
755 .long cpu_arch_name 790 .long cpu_arch_name
756 .long cpu_elf_name 791 .long cpu_elf_name
@@ -771,6 +806,9 @@ __pxa255_proc_info:
771 PMD_SECT_CACHEABLE | \ 806 PMD_SECT_CACHEABLE | \
772 PMD_SECT_AP_WRITE | \ 807 PMD_SECT_AP_WRITE | \
773 PMD_SECT_AP_READ 808 PMD_SECT_AP_READ
809 .long PMD_TYPE_SECT | \
810 PMD_SECT_AP_WRITE | \
811 PMD_SECT_AP_READ
774 b __xscale_setup 812 b __xscale_setup
775 .long cpu_arch_name 813 .long cpu_arch_name
776 .long cpu_elf_name 814 .long cpu_elf_name
@@ -791,6 +829,9 @@ __pxa270_proc_info:
791 PMD_SECT_CACHEABLE | \ 829 PMD_SECT_CACHEABLE | \
792 PMD_SECT_AP_WRITE | \ 830 PMD_SECT_AP_WRITE | \
793 PMD_SECT_AP_READ 831 PMD_SECT_AP_READ
832 .long PMD_TYPE_SECT | \
833 PMD_SECT_AP_WRITE | \
834 PMD_SECT_AP_READ
794 b __xscale_setup 835 b __xscale_setup
795 .long cpu_arch_name 836 .long cpu_arch_name
796 .long cpu_elf_name 837 .long cpu_elf_name
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index ec49495e651e..ec752e16d618 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -91,7 +91,7 @@ config OMAP_32K_TIMER_HZ
91 91
92config OMAP_DM_TIMER 92config OMAP_DM_TIMER
93 bool "Use dual-mode timer" 93 bool "Use dual-mode timer"
94 depends on ARCH_OMAP16XX 94 depends on ARCH_OMAP16XX || ARCH_OMAP24XX
95 help 95 help
96 Select this option if you want to use OMAP Dual-Mode timers. 96 Select this option if you want to use OMAP Dual-Mode timers.
97 97
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index c520e9dcdd8a..7f45c7c3e673 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -27,9 +27,9 @@
27 27
28#include <asm/arch/clock.h> 28#include <asm/arch/clock.h>
29 29
30LIST_HEAD(clocks); 30static LIST_HEAD(clocks);
31static DEFINE_MUTEX(clocks_mutex); 31static DEFINE_MUTEX(clocks_mutex);
32DEFINE_SPINLOCK(clockfw_lock); 32static DEFINE_SPINLOCK(clockfw_lock);
33 33
34static struct clk_functions *arch_clock; 34static struct clk_functions *arch_clock;
35 35
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index 98edc9fdd6d1..a0c71dca2373 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -25,6 +25,14 @@
25#include <asm/io.h> 25#include <asm/io.h>
26#include <asm/system.h> 26#include <asm/system.h>
27 27
28#define VERY_HI_RATE 900000000
29
30#ifdef CONFIG_ARCH_OMAP1
31#define MPU_CLK "mpu"
32#else
33#define MPU_CLK "virt_prcm_set"
34#endif
35
28/* TODO: Add support for SDRAM timing changes */ 36/* TODO: Add support for SDRAM timing changes */
29 37
30int omap_verify_speed(struct cpufreq_policy *policy) 38int omap_verify_speed(struct cpufreq_policy *policy)
@@ -36,7 +44,7 @@ int omap_verify_speed(struct cpufreq_policy *policy)
36 44
37 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, 45 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
38 policy->cpuinfo.max_freq); 46 policy->cpuinfo.max_freq);
39 mpu_clk = clk_get(NULL, "mpu"); 47 mpu_clk = clk_get(NULL, MPU_CLK);
40 if (IS_ERR(mpu_clk)) 48 if (IS_ERR(mpu_clk))
41 return PTR_ERR(mpu_clk); 49 return PTR_ERR(mpu_clk);
42 policy->min = clk_round_rate(mpu_clk, policy->min * 1000) / 1000; 50 policy->min = clk_round_rate(mpu_clk, policy->min * 1000) / 1000;
@@ -56,7 +64,7 @@ unsigned int omap_getspeed(unsigned int cpu)
56 if (cpu) 64 if (cpu)
57 return 0; 65 return 0;
58 66
59 mpu_clk = clk_get(NULL, "mpu"); 67 mpu_clk = clk_get(NULL, MPU_CLK);
60 if (IS_ERR(mpu_clk)) 68 if (IS_ERR(mpu_clk))
61 return 0; 69 return 0;
62 rate = clk_get_rate(mpu_clk) / 1000; 70 rate = clk_get_rate(mpu_clk) / 1000;
@@ -73,7 +81,7 @@ static int omap_target(struct cpufreq_policy *policy,
73 struct cpufreq_freqs freqs; 81 struct cpufreq_freqs freqs;
74 int ret = 0; 82 int ret = 0;
75 83
76 mpu_clk = clk_get(NULL, "mpu"); 84 mpu_clk = clk_get(NULL, MPU_CLK);
77 if (IS_ERR(mpu_clk)) 85 if (IS_ERR(mpu_clk))
78 return PTR_ERR(mpu_clk); 86 return PTR_ERR(mpu_clk);
79 87
@@ -93,7 +101,7 @@ static int __init omap_cpu_init(struct cpufreq_policy *policy)
93{ 101{
94 struct clk * mpu_clk; 102 struct clk * mpu_clk;
95 103
96 mpu_clk = clk_get(NULL, "mpu"); 104 mpu_clk = clk_get(NULL, MPU_CLK);
97 if (IS_ERR(mpu_clk)) 105 if (IS_ERR(mpu_clk))
98 return PTR_ERR(mpu_clk); 106 return PTR_ERR(mpu_clk);
99 107
@@ -102,7 +110,7 @@ static int __init omap_cpu_init(struct cpufreq_policy *policy)
102 policy->cur = policy->min = policy->max = omap_getspeed(0); 110 policy->cur = policy->min = policy->max = omap_getspeed(0);
103 policy->governor = CPUFREQ_DEFAULT_GOVERNOR; 111 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
104 policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000; 112 policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000;
105 policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, 216000000) / 1000; 113 policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, VERY_HI_RATE) / 1000;
106 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; 114 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
107 clk_put(mpu_clk); 115 clk_put(mpu_clk);
108 116
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index ca486c9f36b5..1812f237d12f 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -104,7 +104,7 @@ static void omap_init_kp(void)
104 omap_cfg_reg(E20_1610_KBR3); 104 omap_cfg_reg(E20_1610_KBR3);
105 omap_cfg_reg(E19_1610_KBR4); 105 omap_cfg_reg(E19_1610_KBR4);
106 omap_cfg_reg(N19_1610_KBR5); 106 omap_cfg_reg(N19_1610_KBR5);
107 } else if (machine_is_omap_perseus2()) { 107 } else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
108 omap_cfg_reg(E2_730_KBR0); 108 omap_cfg_reg(E2_730_KBR0);
109 omap_cfg_reg(J7_730_KBR1); 109 omap_cfg_reg(J7_730_KBR1);
110 omap_cfg_reg(E1_730_KBR2); 110 omap_cfg_reg(E1_730_KBR2);
@@ -161,8 +161,8 @@ static u64 mmc1_dmamask = 0xffffffff;
161 161
162static struct resource mmc1_resources[] = { 162static struct resource mmc1_resources[] = {
163 { 163 {
164 .start = IO_ADDRESS(OMAP_MMC1_BASE), 164 .start = OMAP_MMC1_BASE,
165 .end = IO_ADDRESS(OMAP_MMC1_BASE) + 0x7f, 165 .end = OMAP_MMC1_BASE + 0x7f,
166 .flags = IORESOURCE_MEM, 166 .flags = IORESOURCE_MEM,
167 }, 167 },
168 { 168 {
@@ -190,8 +190,8 @@ static u64 mmc2_dmamask = 0xffffffff;
190 190
191static struct resource mmc2_resources[] = { 191static struct resource mmc2_resources[] = {
192 { 192 {
193 .start = IO_ADDRESS(OMAP_MMC2_BASE), 193 .start = OMAP_MMC2_BASE,
194 .end = IO_ADDRESS(OMAP_MMC2_BASE) + 0x7f, 194 .end = OMAP_MMC2_BASE + 0x7f,
195 .flags = IORESOURCE_MEM, 195 .flags = IORESOURCE_MEM,
196 }, 196 },
197 { 197 {
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 5dac4230360d..c5d0214ef191 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -43,6 +43,7 @@
43 43
44#define OMAP_DMA_ACTIVE 0x01 44#define OMAP_DMA_ACTIVE 0x01
45#define OMAP_DMA_CCR_EN (1 << 7) 45#define OMAP_DMA_CCR_EN (1 << 7)
46#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
46 47
47#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) 48#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
48 49
@@ -166,18 +167,24 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
166 if (cpu_is_omap24xx() && dma_trigger) { 167 if (cpu_is_omap24xx() && dma_trigger) {
167 u32 val = OMAP_DMA_CCR_REG(lch); 168 u32 val = OMAP_DMA_CCR_REG(lch);
168 169
170 val &= ~(3 << 19);
169 if (dma_trigger > 63) 171 if (dma_trigger > 63)
170 val |= 1 << 20; 172 val |= 1 << 20;
171 if (dma_trigger > 31) 173 if (dma_trigger > 31)
172 val |= 1 << 19; 174 val |= 1 << 19;
173 175
176 val &= ~(0x1f);
174 val |= (dma_trigger & 0x1f); 177 val |= (dma_trigger & 0x1f);
175 178
176 if (sync_mode & OMAP_DMA_SYNC_FRAME) 179 if (sync_mode & OMAP_DMA_SYNC_FRAME)
177 val |= 1 << 5; 180 val |= 1 << 5;
181 else
182 val &= ~(1 << 5);
178 183
179 if (sync_mode & OMAP_DMA_SYNC_BLOCK) 184 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
180 val |= 1 << 18; 185 val |= 1 << 18;
186 else
187 val &= ~(1 << 18);
181 188
182 if (src_or_dst_synch) 189 if (src_or_dst_synch)
183 val |= 1 << 24; /* source synch */ 190 val |= 1 << 24; /* source synch */
@@ -286,22 +293,39 @@ void omap_set_dma_src_data_pack(int lch, int enable)
286 293
287void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) 294void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
288{ 295{
296 unsigned int burst = 0;
289 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7); 297 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
290 298
291 switch (burst_mode) { 299 switch (burst_mode) {
292 case OMAP_DMA_DATA_BURST_DIS: 300 case OMAP_DMA_DATA_BURST_DIS:
293 break; 301 break;
294 case OMAP_DMA_DATA_BURST_4: 302 case OMAP_DMA_DATA_BURST_4:
295 OMAP_DMA_CSDP_REG(lch) |= (0x02 << 7); 303 if (cpu_is_omap24xx())
304 burst = 0x1;
305 else
306 burst = 0x2;
296 break; 307 break;
297 case OMAP_DMA_DATA_BURST_8: 308 case OMAP_DMA_DATA_BURST_8:
298 /* not supported by current hardware 309 if (cpu_is_omap24xx()) {
310 burst = 0x2;
311 break;
312 }
313 /* not supported by current hardware on OMAP1
299 * w |= (0x03 << 7); 314 * w |= (0x03 << 7);
300 * fall through 315 * fall through
301 */ 316 */
317 case OMAP_DMA_DATA_BURST_16:
318 if (cpu_is_omap24xx()) {
319 burst = 0x3;
320 break;
321 }
322 /* OMAP1 don't support burst 16
323 * fall through
324 */
302 default: 325 default:
303 BUG(); 326 BUG();
304 } 327 }
328 OMAP_DMA_CSDP_REG(lch) |= (burst << 7);
305} 329}
306 330
307/* Note that dest_port is only for OMAP1 */ 331/* Note that dest_port is only for OMAP1 */
@@ -348,30 +372,49 @@ void omap_set_dma_dest_data_pack(int lch, int enable)
348 372
349void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) 373void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
350{ 374{
375 unsigned int burst = 0;
351 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14); 376 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
352 377
353 switch (burst_mode) { 378 switch (burst_mode) {
354 case OMAP_DMA_DATA_BURST_DIS: 379 case OMAP_DMA_DATA_BURST_DIS:
355 break; 380 break;
356 case OMAP_DMA_DATA_BURST_4: 381 case OMAP_DMA_DATA_BURST_4:
357 OMAP_DMA_CSDP_REG(lch) |= (0x02 << 14); 382 if (cpu_is_omap24xx())
383 burst = 0x1;
384 else
385 burst = 0x2;
358 break; 386 break;
359 case OMAP_DMA_DATA_BURST_8: 387 case OMAP_DMA_DATA_BURST_8:
360 OMAP_DMA_CSDP_REG(lch) |= (0x03 << 14); 388 if (cpu_is_omap24xx())
389 burst = 0x2;
390 else
391 burst = 0x3;
361 break; 392 break;
393 case OMAP_DMA_DATA_BURST_16:
394 if (cpu_is_omap24xx()) {
395 burst = 0x3;
396 break;
397 }
398 /* OMAP1 don't support burst 16
399 * fall through
400 */
362 default: 401 default:
363 printk(KERN_ERR "Invalid DMA burst mode\n"); 402 printk(KERN_ERR "Invalid DMA burst mode\n");
364 BUG(); 403 BUG();
365 return; 404 return;
366 } 405 }
406 OMAP_DMA_CSDP_REG(lch) |= (burst << 14);
367} 407}
368 408
369static inline void omap_enable_channel_irq(int lch) 409static inline void omap_enable_channel_irq(int lch)
370{ 410{
371 u32 status; 411 u32 status;
372 412
373 /* Read CSR to make sure it's cleared. */ 413 /* Clear CSR */
374 status = OMAP_DMA_CSR_REG(lch); 414 if (cpu_class_is_omap1())
415 status = OMAP_DMA_CSR_REG(lch);
416 else if (cpu_is_omap24xx())
417 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
375 418
376 /* Enable some nice interrupts. */ 419 /* Enable some nice interrupts. */
377 OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs; 420 OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
@@ -470,11 +513,13 @@ int omap_request_dma(int dev_id, const char *dev_name,
470 chan->dev_name = dev_name; 513 chan->dev_name = dev_name;
471 chan->callback = callback; 514 chan->callback = callback;
472 chan->data = data; 515 chan->data = data;
473 chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ | 516 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
474 OMAP_DMA_BLOCK_IRQ;
475 517
476 if (cpu_is_omap24xx()) 518 if (cpu_class_is_omap1())
477 chan->enabled_irqs |= OMAP2_DMA_TRANS_ERR_IRQ; 519 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
520 else if (cpu_is_omap24xx())
521 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
522 OMAP2_DMA_TRANS_ERR_IRQ;
478 523
479 if (cpu_is_omap16xx()) { 524 if (cpu_is_omap16xx()) {
480 /* If the sync device is set, configure it dynamically. */ 525 /* If the sync device is set, configure it dynamically. */
@@ -494,7 +539,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
494 539
495 omap_enable_channel_irq(free_ch); 540 omap_enable_channel_irq(free_ch);
496 /* Clear the CSR register and IRQ status register */ 541 /* Clear the CSR register and IRQ status register */
497 OMAP_DMA_CSR_REG(free_ch) = 0x0; 542 OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK;
498 omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0); 543 omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0);
499 } 544 }
500 545
@@ -534,7 +579,7 @@ void omap_free_dma(int lch)
534 omap_writel(val, OMAP_DMA4_IRQENABLE_L0); 579 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
535 580
536 /* Clear the CSR register and IRQ status register */ 581 /* Clear the CSR register and IRQ status register */
537 OMAP_DMA_CSR_REG(lch) = 0x0; 582 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
538 583
539 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0); 584 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
540 val |= 1 << lch; 585 val |= 1 << lch;
@@ -798,7 +843,7 @@ static int omap1_dma_handle_ch(int ch)
798 "%d (CSR %04x)\n", ch, csr); 843 "%d (CSR %04x)\n", ch, csr);
799 return 0; 844 return 0;
800 } 845 }
801 if (unlikely(csr & OMAP_DMA_TOUT_IRQ)) 846 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
802 printk(KERN_WARNING "DMA timeout with device %d\n", 847 printk(KERN_WARNING "DMA timeout with device %d\n",
803 dma_chan[ch].dev_id); 848 dma_chan[ch].dev_id);
804 if (unlikely(csr & OMAP_DMA_DROP_IRQ)) 849 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
@@ -846,20 +891,21 @@ static int omap2_dma_handle_ch(int ch)
846 return 0; 891 return 0;
847 if (unlikely(dma_chan[ch].dev_id == -1)) 892 if (unlikely(dma_chan[ch].dev_id == -1))
848 return 0; 893 return 0;
849 /* REVISIT: According to 24xx TRM, there's no TOUT_IE */
850 if (unlikely(status & OMAP_DMA_TOUT_IRQ))
851 printk(KERN_INFO "DMA timeout with device %d\n",
852 dma_chan[ch].dev_id);
853 if (unlikely(status & OMAP_DMA_DROP_IRQ)) 894 if (unlikely(status & OMAP_DMA_DROP_IRQ))
854 printk(KERN_INFO 895 printk(KERN_INFO
855 "DMA synchronization event drop occurred with device " 896 "DMA synchronization event drop occurred with device "
856 "%d\n", dma_chan[ch].dev_id); 897 "%d\n", dma_chan[ch].dev_id);
857
858 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) 898 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
859 printk(KERN_INFO "DMA transaction error with device %d\n", 899 printk(KERN_INFO "DMA transaction error with device %d\n",
860 dma_chan[ch].dev_id); 900 dma_chan[ch].dev_id);
901 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
902 printk(KERN_INFO "DMA secure error with device %d\n",
903 dma_chan[ch].dev_id);
904 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
905 printk(KERN_INFO "DMA misaligned error with device %d\n",
906 dma_chan[ch].dev_id);
861 907
862 OMAP_DMA_CSR_REG(ch) = 0x20; 908 OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
863 909
864 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0); 910 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
865 /* ch in this function is from 0-31 while in register it is 1-32 */ 911 /* ch in this function is from 0-31 while in register it is 1-32 */
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index eba3cb52ad87..50524436de63 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -4,7 +4,8 @@
4 * OMAP Dual-Mode Timers 4 * OMAP Dual-Mode Timers
5 * 5 *
6 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com> 7 * OMAP2 support by Juha Yrjola
8 * API improvements and OMAP2 clock framework support by Timo Teras
8 * 9 *
9 * This program is free software; you can redistribute it and/or modify it 10 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the 11 * under the terms of the GNU General Public License as published by the
@@ -26,15 +27,17 @@
26 */ 27 */
27 28
28#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/spinlock.h>
31#include <linux/errno.h>
32#include <linux/list.h>
33#include <linux/clk.h>
34#include <linux/delay.h>
29#include <asm/hardware.h> 35#include <asm/hardware.h>
30#include <asm/arch/dmtimer.h> 36#include <asm/arch/dmtimer.h>
31#include <asm/io.h> 37#include <asm/io.h>
32#include <asm/arch/irqs.h> 38#include <asm/arch/irqs.h>
33#include <linux/spinlock.h>
34#include <linux/list.h>
35
36#define OMAP_TIMER_COUNT 8
37 39
40/* register offsets */
38#define OMAP_TIMER_ID_REG 0x00 41#define OMAP_TIMER_ID_REG 0x00
39#define OMAP_TIMER_OCP_CFG_REG 0x10 42#define OMAP_TIMER_OCP_CFG_REG 0x10
40#define OMAP_TIMER_SYS_STAT_REG 0x14 43#define OMAP_TIMER_SYS_STAT_REG 0x14
@@ -50,52 +53,196 @@
50#define OMAP_TIMER_CAPTURE_REG 0x3c 53#define OMAP_TIMER_CAPTURE_REG 0x3c
51#define OMAP_TIMER_IF_CTRL_REG 0x40 54#define OMAP_TIMER_IF_CTRL_REG 0x40
52 55
56/* timer control reg bits */
57#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
58#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
59#define OMAP_TIMER_CTRL_PT (1 << 12)
60#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
61#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
62#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
63#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
64#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
65#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
66#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* how much to shift the prescaler value */
67#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
68#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
69
70struct omap_dm_timer {
71 unsigned long phys_base;
72 int irq;
73#ifdef CONFIG_ARCH_OMAP2
74 struct clk *iclk, *fclk;
75#endif
76 void __iomem *io_base;
77 unsigned reserved:1;
78};
53 79
54static struct dmtimer_info_struct { 80#ifdef CONFIG_ARCH_OMAP1
55 struct list_head unused_timers;
56 struct list_head reserved_timers;
57} dm_timer_info;
58 81
59static struct omap_dm_timer dm_timers[] = { 82static struct omap_dm_timer dm_timers[] = {
60 { .base=0xfffb1400, .irq=INT_1610_GPTIMER1 }, 83 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
61 { .base=0xfffb1c00, .irq=INT_1610_GPTIMER2 }, 84 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
62 { .base=0xfffb2400, .irq=INT_1610_GPTIMER3 }, 85 { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
63 { .base=0xfffb2c00, .irq=INT_1610_GPTIMER4 }, 86 { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
64 { .base=0xfffb3400, .irq=INT_1610_GPTIMER5 }, 87 { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
65 { .base=0xfffb3c00, .irq=INT_1610_GPTIMER6 }, 88 { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
66 { .base=0xfffb4400, .irq=INT_1610_GPTIMER7 }, 89 { .phys_base = 0xfffb4400, .irq = INT_1610_GPTIMER7 },
67 { .base=0xfffb4c00, .irq=INT_1610_GPTIMER8 }, 90 { .phys_base = 0xfffb4c00, .irq = INT_1610_GPTIMER8 },
68 { .base=0x0 },
69}; 91};
70 92
93#elif defined(CONFIG_ARCH_OMAP2)
94
95static struct omap_dm_timer dm_timers[] = {
96 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
97 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
98 { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
99 { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
100 { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
101 { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
102 { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
103 { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
104 { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
105 { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
106 { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
107 { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
108};
109
110static const char *dm_source_names[] = {
111 "sys_ck",
112 "func_32k_ck",
113 "alt_ck"
114};
71 115
116static struct clk *dm_source_clocks[3];
117
118#else
119
120#error OMAP architecture not supported!
121
122#endif
123
124static const int dm_timer_count = ARRAY_SIZE(dm_timers);
72static spinlock_t dm_timer_lock; 125static spinlock_t dm_timer_lock;
73 126
127static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
128{
129 return readl(timer->io_base + reg);
130}
74 131
75inline void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value) 132static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
76{ 133{
77 omap_writel(value, timer->base + reg); 134 writel(value, timer->io_base + reg);
78 while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG)) 135 while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
79 ; 136 ;
80} 137}
81 138
82u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg) 139static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
83{ 140{
84 return omap_readl(timer->base + reg); 141 int c;
142
143 c = 0;
144 while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
145 c++;
146 if (c > 100000) {
147 printk(KERN_ERR "Timer failed to reset\n");
148 return;
149 }
150 }
85} 151}
86 152
87int omap_dm_timers_active(void) 153static void omap_dm_timer_reset(struct omap_dm_timer *timer)
154{
155 u32 l;
156
157 if (timer != &dm_timers[0]) {
158 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
159 omap_dm_timer_wait_for_reset(timer);
160 }
161 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_SYS_CLK);
162
163 /* Set to smart-idle mode */
164 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
165 l |= 0x02 << 3;
166 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
167}
168
169static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
170{
171#ifdef CONFIG_ARCH_OMAP2
172 clk_enable(timer->iclk);
173 clk_enable(timer->fclk);
174#endif
175 omap_dm_timer_reset(timer);
176}
177
178struct omap_dm_timer *omap_dm_timer_request(void)
179{
180 struct omap_dm_timer *timer = NULL;
181 unsigned long flags;
182 int i;
183
184 spin_lock_irqsave(&dm_timer_lock, flags);
185 for (i = 0; i < dm_timer_count; i++) {
186 if (dm_timers[i].reserved)
187 continue;
188
189 timer = &dm_timers[i];
190 timer->reserved = 1;
191 break;
192 }
193 spin_unlock_irqrestore(&dm_timer_lock, flags);
194
195 if (timer != NULL)
196 omap_dm_timer_prepare(timer);
197
198 return timer;
199}
200
201struct omap_dm_timer *omap_dm_timer_request_specific(int id)
88{ 202{
89 struct omap_dm_timer *timer; 203 struct omap_dm_timer *timer;
204 unsigned long flags;
90 205
91 for (timer = &dm_timers[0]; timer->base; ++timer) 206 spin_lock_irqsave(&dm_timer_lock, flags);
92 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & 207 if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
93 OMAP_TIMER_CTRL_ST) 208 spin_unlock_irqrestore(&dm_timer_lock, flags);
94 return 1; 209 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
210 __FILE__, __LINE__, __FUNCTION__, id);
211 dump_stack();
212 return NULL;
213 }
95 214
96 return 0; 215 timer = &dm_timers[id-1];
216 timer->reserved = 1;
217 spin_unlock_irqrestore(&dm_timer_lock, flags);
218
219 omap_dm_timer_prepare(timer);
220
221 return timer;
97} 222}
98 223
224void omap_dm_timer_free(struct omap_dm_timer *timer)
225{
226 omap_dm_timer_reset(timer);
227#ifdef CONFIG_ARCH_OMAP2
228 clk_disable(timer->iclk);
229 clk_disable(timer->fclk);
230#endif
231 WARN_ON(!timer->reserved);
232 timer->reserved = 0;
233}
234
235int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
236{
237 return timer->irq;
238}
239
240#if defined(CONFIG_ARCH_OMAP1)
241
242struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
243{
244 BUG();
245}
99 246
100/** 247/**
101 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR 248 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
@@ -103,184 +250,229 @@ int omap_dm_timers_active(void)
103 */ 250 */
104__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) 251__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
105{ 252{
106 int n; 253 int i;
107 254
108 /* If ARMXOR cannot be idled this function call is unnecessary */ 255 /* If ARMXOR cannot be idled this function call is unnecessary */
109 if (!(inputmask & (1 << 1))) 256 if (!(inputmask & (1 << 1)))
110 return inputmask; 257 return inputmask;
111 258
112 /* If any active timer is using ARMXOR return modified mask */ 259 /* If any active timer is using ARMXOR return modified mask */
113 for (n = 0; dm_timers[n].base; ++n) 260 for (i = 0; i < dm_timer_count; i++) {
114 if (omap_dm_timer_read_reg(&dm_timers[n], OMAP_TIMER_CTRL_REG)& 261 u32 l;
115 OMAP_TIMER_CTRL_ST) { 262
116 if (((omap_readl(MOD_CONF_CTRL_1)>>(n*2)) & 0x03) == 0) 263 l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
264 if (l & OMAP_TIMER_CTRL_ST) {
265 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
117 inputmask &= ~(1 << 1); 266 inputmask &= ~(1 << 1);
118 else 267 else
119 inputmask &= ~(1 << 2); 268 inputmask &= ~(1 << 2);
120 } 269 }
270 }
121 271
122 return inputmask; 272 return inputmask;
123} 273}
124 274
275#elif defined(CONFIG_ARCH_OMAP2)
125 276
126void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) 277struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
127{ 278{
128 int n = (timer - dm_timers) << 1; 279 return timer->fclk;
129 u32 l; 280}
130 281
131 l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); 282__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
132 l |= source << n; 283{
133 omap_writel(l, MOD_CONF_CTRL_1); 284 BUG();
134} 285}
135 286
287#endif
136 288
137static void omap_dm_timer_reset(struct omap_dm_timer *timer) 289void omap_dm_timer_trigger(struct omap_dm_timer *timer)
138{ 290{
139 /* Reset and set posted mode */ 291 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
140 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
141 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, 0x02);
142
143 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_ARMXOR);
144} 292}
145 293
294void omap_dm_timer_start(struct omap_dm_timer *timer)
295{
296 u32 l;
146 297
298 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
299 if (!(l & OMAP_TIMER_CTRL_ST)) {
300 l |= OMAP_TIMER_CTRL_ST;
301 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
302 }
303}
147 304
148struct omap_dm_timer * omap_dm_timer_request(void) 305void omap_dm_timer_stop(struct omap_dm_timer *timer)
149{ 306{
150 struct omap_dm_timer *timer = NULL; 307 u32 l;
151 unsigned long flags;
152 308
153 spin_lock_irqsave(&dm_timer_lock, flags); 309 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
154 if (!list_empty(&dm_timer_info.unused_timers)) { 310 if (l & OMAP_TIMER_CTRL_ST) {
155 timer = (struct omap_dm_timer *) 311 l &= ~0x1;
156 dm_timer_info.unused_timers.next; 312 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
157 list_move_tail((struct list_head *)timer,
158 &dm_timer_info.reserved_timers);
159 } 313 }
160 spin_unlock_irqrestore(&dm_timer_lock, flags);
161
162 return timer;
163} 314}
164 315
316#ifdef CONFIG_ARCH_OMAP1
165 317
166void omap_dm_timer_free(struct omap_dm_timer *timer) 318void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
167{ 319{
168 unsigned long flags; 320 int n = (timer - dm_timers) << 1;
169 321 u32 l;
170 omap_dm_timer_reset(timer);
171 322
172 spin_lock_irqsave(&dm_timer_lock, flags); 323 l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
173 list_move_tail((struct list_head *)timer, &dm_timer_info.unused_timers); 324 l |= source << n;
174 spin_unlock_irqrestore(&dm_timer_lock, flags); 325 omap_writel(l, MOD_CONF_CTRL_1);
175} 326}
176 327
177void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, 328#else
178 unsigned int value)
179{
180 omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
181}
182 329
183unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) 330void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
184{ 331{
185 return omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG); 332 if (source < 0 || source >= 3)
186} 333 return;
187 334
188void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) 335 clk_disable(timer->fclk);
189{ 336 clk_set_parent(timer->fclk, dm_source_clocks[source]);
190 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value); 337 clk_enable(timer->fclk);
338
339 /* When the functional clock disappears, too quick writes seem to
340 * cause an abort. */
341 __delay(15000);
191} 342}
192 343
193void omap_dm_timer_enable_autoreload(struct omap_dm_timer *timer) 344#endif
345
346void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
347 unsigned int load)
194{ 348{
195 u32 l; 349 u32 l;
350
196 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 351 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
197 l |= OMAP_TIMER_CTRL_AR; 352 if (autoreload)
353 l |= OMAP_TIMER_CTRL_AR;
354 else
355 l &= ~OMAP_TIMER_CTRL_AR;
198 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 356 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
357 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
358 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
199} 359}
200 360
201void omap_dm_timer_trigger(struct omap_dm_timer *timer) 361void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
202{ 362 unsigned int match)
203 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 1);
204}
205
206void omap_dm_timer_set_trigger(struct omap_dm_timer *timer, unsigned int value)
207{ 363{
208 u32 l; 364 u32 l;
209 365
210 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 366 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
211 l |= value & 0x3; 367 if (enable)
368 l |= OMAP_TIMER_CTRL_CE;
369 else
370 l &= ~OMAP_TIMER_CTRL_CE;
212 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 371 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
372 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
213} 373}
214 374
215void omap_dm_timer_start(struct omap_dm_timer *timer) 375
376void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
377 int toggle, int trigger)
216{ 378{
217 u32 l; 379 u32 l;
218 380
219 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 381 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
220 l |= OMAP_TIMER_CTRL_ST; 382 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
383 OMAP_TIMER_CTRL_PT | (0x03 << 10));
384 if (def_on)
385 l |= OMAP_TIMER_CTRL_SCPWM;
386 if (toggle)
387 l |= OMAP_TIMER_CTRL_PT;
388 l |= trigger << 10;
221 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 389 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
222} 390}
223 391
224void omap_dm_timer_stop(struct omap_dm_timer *timer) 392void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
225{ 393{
226 u32 l; 394 u32 l;
227 395
228 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 396 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
229 l &= ~0x1; 397 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
398 if (prescaler >= 0x00 && prescaler <= 0x07) {
399 l |= OMAP_TIMER_CTRL_PRE;
400 l |= prescaler << 2;
401 }
230 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 402 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
231} 403}
232 404
233unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) 405void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
406 unsigned int value)
234{ 407{
235 return omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG); 408 omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
236} 409}
237 410
238void omap_dm_timer_reset_counter(struct omap_dm_timer *timer) 411unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
239{ 412{
240 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, 0); 413 return omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
241} 414}
242 415
243void omap_dm_timer_set_load(struct omap_dm_timer *timer, unsigned int load) 416void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
244{ 417{
245 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); 418 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
246} 419}
247 420
248void omap_dm_timer_set_match(struct omap_dm_timer *timer, unsigned int match) 421unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
249{ 422{
250 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); 423 return omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
251} 424}
252 425
253void omap_dm_timer_enable_compare(struct omap_dm_timer *timer) 426void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
254{ 427{
255 u32 l; 428 return omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
256
257 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
258 l |= OMAP_TIMER_CTRL_CE;
259 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
260} 429}
261 430
431int omap_dm_timers_active(void)
432{
433 int i;
434
435 for (i = 0; i < dm_timer_count; i++) {
436 struct omap_dm_timer *timer;
437
438 timer = &dm_timers[i];
439 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
440 OMAP_TIMER_CTRL_ST)
441 return 1;
442 }
443 return 0;
444}
262 445
263static inline void __dm_timer_init(void) 446int omap_dm_timer_init(void)
264{ 447{
265 struct omap_dm_timer *timer; 448 struct omap_dm_timer *timer;
449 int i;
450
451 if (!(cpu_is_omap16xx() || cpu_is_omap24xx()))
452 return -ENODEV;
266 453
267 spin_lock_init(&dm_timer_lock); 454 spin_lock_init(&dm_timer_lock);
268 INIT_LIST_HEAD(&dm_timer_info.unused_timers); 455#ifdef CONFIG_ARCH_OMAP2
269 INIT_LIST_HEAD(&dm_timer_info.reserved_timers); 456 for (i = 0; i < ARRAY_SIZE(dm_source_names); i++) {
270 457 dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
271 timer = &dm_timers[0]; 458 BUG_ON(dm_source_clocks[i] == NULL);
272 while (timer->base) { 459 }
273 list_add_tail((struct list_head *)timer, &dm_timer_info.unused_timers); 460#endif
274 omap_dm_timer_reset(timer); 461
275 timer++; 462 for (i = 0; i < dm_timer_count; i++) {
463#ifdef CONFIG_ARCH_OMAP2
464 char clk_name[16];
465#endif
466
467 timer = &dm_timers[i];
468 timer->io_base = (void __iomem *) io_p2v(timer->phys_base);
469#ifdef CONFIG_ARCH_OMAP2
470 sprintf(clk_name, "gpt%d_ick", i + 1);
471 timer->iclk = clk_get(NULL, clk_name);
472 sprintf(clk_name, "gpt%d_fck", i + 1);
473 timer->fclk = clk_get(NULL, clk_name);
474#endif
276 } 475 }
277}
278 476
279static int __init omap_dm_timer_init(void)
280{
281 if (cpu_is_omap16xx())
282 __dm_timer_init();
283 return 0; 477 return 0;
284} 478}
285
286arch_initcall(omap_dm_timer_init);
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 418b88fbea8e..ae08eeec7aad 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -536,6 +536,49 @@ static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
536 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); 536 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
537} 537}
538 538
539static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
540{
541 void __iomem *reg = bank->base;
542 int inv = 0;
543 u32 l;
544 u32 mask;
545
546 switch (bank->method) {
547 case METHOD_MPUIO:
548 reg += OMAP_MPUIO_GPIO_MASKIT;
549 mask = 0xffff;
550 inv = 1;
551 break;
552 case METHOD_GPIO_1510:
553 reg += OMAP1510_GPIO_INT_MASK;
554 mask = 0xffff;
555 inv = 1;
556 break;
557 case METHOD_GPIO_1610:
558 reg += OMAP1610_GPIO_IRQENABLE1;
559 mask = 0xffff;
560 break;
561 case METHOD_GPIO_730:
562 reg += OMAP730_GPIO_INT_MASK;
563 mask = 0xffffffff;
564 inv = 1;
565 break;
566 case METHOD_GPIO_24XX:
567 reg += OMAP24XX_GPIO_IRQENABLE1;
568 mask = 0xffffffff;
569 break;
570 default:
571 BUG();
572 return 0;
573 }
574
575 l = __raw_readl(reg);
576 if (inv)
577 l = ~l;
578 l &= mask;
579 return l;
580}
581
539static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) 582static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
540{ 583{
541 void __iomem *reg = bank->base; 584 void __iomem *reg = bank->base;
@@ -735,6 +778,8 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
735 u32 isr; 778 u32 isr;
736 unsigned int gpio_irq; 779 unsigned int gpio_irq;
737 struct gpio_bank *bank; 780 struct gpio_bank *bank;
781 u32 retrigger = 0;
782 int unmasked = 0;
738 783
739 desc->chip->ack(irq); 784 desc->chip->ack(irq);
740 785
@@ -759,18 +804,22 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
759#endif 804#endif
760 while(1) { 805 while(1) {
761 u32 isr_saved, level_mask = 0; 806 u32 isr_saved, level_mask = 0;
807 u32 enabled;
762 808
763 isr_saved = isr = __raw_readl(isr_reg); 809 enabled = _get_gpio_irqbank_mask(bank);
810 isr_saved = isr = __raw_readl(isr_reg) & enabled;
764 811
765 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) 812 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
766 isr &= 0x0000ffff; 813 isr &= 0x0000ffff;
767 814
768 if (cpu_is_omap24xx()) 815 if (cpu_is_omap24xx()) {
769 level_mask = 816 level_mask =
770 __raw_readl(bank->base + 817 __raw_readl(bank->base +
771 OMAP24XX_GPIO_LEVELDETECT0) | 818 OMAP24XX_GPIO_LEVELDETECT0) |
772 __raw_readl(bank->base + 819 __raw_readl(bank->base +
773 OMAP24XX_GPIO_LEVELDETECT1); 820 OMAP24XX_GPIO_LEVELDETECT1);
821 level_mask &= enabled;
822 }
774 823
775 /* clear edge sensitive interrupts before handler(s) are 824 /* clear edge sensitive interrupts before handler(s) are
776 called so that we don't miss any interrupt occurred while 825 called so that we don't miss any interrupt occurred while
@@ -781,19 +830,54 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
781 830
782 /* if there is only edge sensitive GPIO pin interrupts 831 /* if there is only edge sensitive GPIO pin interrupts
783 configured, we could unmask GPIO bank interrupt immediately */ 832 configured, we could unmask GPIO bank interrupt immediately */
784 if (!level_mask) 833 if (!level_mask && !unmasked) {
834 unmasked = 1;
785 desc->chip->unmask(irq); 835 desc->chip->unmask(irq);
836 }
786 837
838 isr |= retrigger;
839 retrigger = 0;
787 if (!isr) 840 if (!isr)
788 break; 841 break;
789 842
790 gpio_irq = bank->virtual_irq_start; 843 gpio_irq = bank->virtual_irq_start;
791 for (; isr != 0; isr >>= 1, gpio_irq++) { 844 for (; isr != 0; isr >>= 1, gpio_irq++) {
792 struct irqdesc *d; 845 struct irqdesc *d;
846 int irq_mask;
793 if (!(isr & 1)) 847 if (!(isr & 1))
794 continue; 848 continue;
795 d = irq_desc + gpio_irq; 849 d = irq_desc + gpio_irq;
850 /* Don't run the handler if it's already running
851 * or was disabled lazely.
852 */
853 if (unlikely((d->disable_depth || d->running))) {
854 irq_mask = 1 <<
855 (gpio_irq - bank->virtual_irq_start);
856 /* The unmasking will be done by
857 * enable_irq in case it is disabled or
858 * after returning from the handler if
859 * it's already running.
860 */
861 _enable_gpio_irqbank(bank, irq_mask, 0);
862 if (!d->disable_depth) {
863 /* Level triggered interrupts
864 * won't ever be reentered
865 */
866 BUG_ON(level_mask & irq_mask);
867 d->pending = 1;
868 }
869 continue;
870 }
871 d->running = 1;
796 desc_handle_irq(gpio_irq, d, regs); 872 desc_handle_irq(gpio_irq, d, regs);
873 d->running = 0;
874 if (unlikely(d->pending && !d->disable_depth)) {
875 irq_mask = 1 <<
876 (gpio_irq - bank->virtual_irq_start);
877 d->pending = 0;
878 _enable_gpio_irqbank(bank, irq_mask, 1);
879 retrigger |= irq_mask;
880 }
797 } 881 }
798 882
799 if (cpu_is_omap24xx()) { 883 if (cpu_is_omap24xx()) {
@@ -803,13 +887,14 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
803 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1); 887 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
804 } 888 }
805 889
806 /* if bank has any level sensitive GPIO pin interrupt
807 configured, we must unmask the bank interrupt only after
808 handler(s) are executed in order to avoid spurious bank
809 interrupt */
810 if (level_mask)
811 desc->chip->unmask(irq);
812 } 890 }
891 /* if bank has any level sensitive GPIO pin interrupt
892 configured, we must unmask the bank interrupt only after
893 handler(s) are executed in order to avoid spurious bank
894 interrupt */
895 if (!unmasked)
896 desc->chip->unmask(irq);
897
813} 898}
814 899
815static void gpio_ack_irq(unsigned int irq) 900static void gpio_ack_irq(unsigned int irq)
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 72ce52ce815b..e75718301b0f 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -157,14 +157,12 @@ static struct map_desc omap_sram_io_desc[] __initdata = {
157 { /* .length gets filled in at runtime */ 157 { /* .length gets filled in at runtime */
158 .virtual = OMAP1_SRAM_VA, 158 .virtual = OMAP1_SRAM_VA,
159 .pfn = __phys_to_pfn(OMAP1_SRAM_PA), 159 .pfn = __phys_to_pfn(OMAP1_SRAM_PA),
160 .type = MT_DEVICE 160 .type = MT_MEMORY
161 } 161 }
162}; 162};
163 163
164/* 164/*
165 * In order to use last 2kB of SRAM on 1611b, we must round the size 165 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
166 * up to multiple of PAGE_SIZE. We cannot use ioremap for SRAM, as
167 * clock init needs SRAM early.
168 */ 166 */
169void __init omap_map_sram(void) 167void __init omap_map_sram(void)
170{ 168{
@@ -184,8 +182,7 @@ void __init omap_map_sram(void)
184 omap_sram_io_desc[0].pfn = __phys_to_pfn(base); 182 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
185 } 183 }
186 184
187 omap_sram_io_desc[0].length = (omap_sram_size + PAGE_SIZE-1)/PAGE_SIZE; 185 omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
188 omap_sram_io_desc[0].length *= PAGE_SIZE;
189 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); 186 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
190 187
191 printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n", 188 printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
diff --git a/arch/arm/plat-omap/timer32k.c b/arch/arm/plat-omap/timer32k.c
index 053c18132ef4..ddf4360dea72 100644
--- a/arch/arm/plat-omap/timer32k.c
+++ b/arch/arm/plat-omap/timer32k.c
@@ -7,6 +7,7 @@
7 * Partial timer rewrite and additional dynamic tick timer support by 7 * Partial timer rewrite and additional dynamic tick timer support by
8 * Tony Lindgen <tony@atomide.com> and 8 * Tony Lindgen <tony@atomide.com> and
9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10 * OMAP Dual-mode timer framework support by Timo Teras
10 * 11 *
11 * MPU timer code based on the older MPU timer code for OMAP 12 * MPU timer code based on the older MPU timer code for OMAP
12 * Copyright (C) 2000 RidgeRun, Inc. 13 * Copyright (C) 2000 RidgeRun, Inc.
@@ -49,6 +50,7 @@
49#include <asm/irq.h> 50#include <asm/irq.h>
50#include <asm/mach/irq.h> 51#include <asm/mach/irq.h>
51#include <asm/mach/time.h> 52#include <asm/mach/time.h>
53#include <asm/arch/dmtimer.h>
52 54
53struct sys_timer omap_timer; 55struct sys_timer omap_timer;
54 56
@@ -78,18 +80,6 @@ struct sys_timer omap_timer;
78#define OMAP1_32K_TIMER_TVR 0x00 80#define OMAP1_32K_TIMER_TVR 0x00
79#define OMAP1_32K_TIMER_TCR 0x04 81#define OMAP1_32K_TIMER_TCR 0x04
80 82
81/* 24xx specific defines */
82#define OMAP2_GP_TIMER_BASE 0x48028000
83#define CM_CLKSEL_WKUP 0x48008440
84#define GP_TIMER_TIDR 0x00
85#define GP_TIMER_TISR 0x18
86#define GP_TIMER_TIER 0x1c
87#define GP_TIMER_TCLR 0x24
88#define GP_TIMER_TCRR 0x28
89#define GP_TIMER_TLDR 0x2c
90#define GP_TIMER_TTGR 0x30
91#define GP_TIMER_TSICR 0x40
92
93#define OMAP_32K_TICKS_PER_HZ (32768 / HZ) 83#define OMAP_32K_TICKS_PER_HZ (32768 / HZ)
94 84
95/* 85/*
@@ -101,54 +91,62 @@ struct sys_timer omap_timer;
101#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \ 91#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
102 (((nr_jiffies) * (clock_rate)) / HZ) 92 (((nr_jiffies) * (clock_rate)) / HZ)
103 93
94#if defined(CONFIG_ARCH_OMAP1)
95
104static inline void omap_32k_timer_write(int val, int reg) 96static inline void omap_32k_timer_write(int val, int reg)
105{ 97{
106 if (cpu_class_is_omap1()) 98 omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
107 omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
108
109 if (cpu_is_omap24xx())
110 omap_writel(val, OMAP2_GP_TIMER_BASE + reg);
111} 99}
112 100
113static inline unsigned long omap_32k_timer_read(int reg) 101static inline unsigned long omap_32k_timer_read(int reg)
114{ 102{
115 if (cpu_class_is_omap1()) 103 return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
116 return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff; 104}
117 105
118 if (cpu_is_omap24xx()) 106static inline void omap_32k_timer_start(unsigned long load_val)
119 return omap_readl(OMAP2_GP_TIMER_BASE + reg); 107{
108 omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
109 omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
120} 110}
121 111
122/* 112static inline void omap_32k_timer_stop(void)
123 * The 32KHz synchronized timer is an additional timer on 16xx.
124 * It is always running.
125 */
126static inline unsigned long omap_32k_sync_timer_read(void)
127{ 113{
128 return omap_readl(TIMER_32K_SYNCHRONIZED); 114 omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
129} 115}
130 116
117#define omap_32k_timer_ack_irq()
118
119#elif defined(CONFIG_ARCH_OMAP2)
120
121static struct omap_dm_timer *gptimer;
122
131static inline void omap_32k_timer_start(unsigned long load_val) 123static inline void omap_32k_timer_start(unsigned long load_val)
132{ 124{
133 if (cpu_class_is_omap1()) { 125 omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
134 omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR); 126 omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
135 omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR); 127 omap_dm_timer_start(gptimer);
136 }
137
138 if (cpu_is_omap24xx()) {
139 omap_32k_timer_write(0xffffffff - load_val, GP_TIMER_TCRR);
140 omap_32k_timer_write((1 << 1), GP_TIMER_TIER);
141 omap_32k_timer_write((1 << 1) | 1, GP_TIMER_TCLR);
142 }
143} 128}
144 129
145static inline void omap_32k_timer_stop(void) 130static inline void omap_32k_timer_stop(void)
146{ 131{
147 if (cpu_class_is_omap1()) 132 omap_dm_timer_stop(gptimer);
148 omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR); 133}
149 134
150 if (cpu_is_omap24xx()) 135static inline void omap_32k_timer_ack_irq(void)
151 omap_32k_timer_write(0x0, GP_TIMER_TCLR); 136{
137 u32 status = omap_dm_timer_read_status(gptimer);
138 omap_dm_timer_write_status(gptimer, status);
139}
140
141#endif
142
143/*
144 * The 32KHz synchronized timer is an additional timer on 16xx.
145 * It is always running.
146 */
147static inline unsigned long omap_32k_sync_timer_read(void)
148{
149 return omap_readl(TIMER_32K_SYNCHRONIZED);
152} 150}
153 151
154/* 152/*
@@ -202,11 +200,7 @@ static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
202 200
203 write_seqlock_irqsave(&xtime_lock, flags); 201 write_seqlock_irqsave(&xtime_lock, flags);
204 202
205 if (cpu_is_omap24xx()) { 203 omap_32k_timer_ack_irq();
206 u32 status = omap_32k_timer_read(GP_TIMER_TISR);
207 omap_32k_timer_write(status, GP_TIMER_TISR);
208 }
209
210 now = omap_32k_sync_timer_read(); 204 now = omap_32k_sync_timer_read();
211 205
212 while ((signed long)(now - omap_32k_last_tick) 206 while ((signed long)(now - omap_32k_last_tick)
@@ -268,9 +262,6 @@ static struct irqaction omap_32k_timer_irq = {
268 .handler = omap_32k_timer_interrupt, 262 .handler = omap_32k_timer_interrupt,
269}; 263};
270 264
271static struct clk * gpt1_ick;
272static struct clk * gpt1_fck;
273
274static __init void omap_init_32k_timer(void) 265static __init void omap_init_32k_timer(void)
275{ 266{
276#ifdef CONFIG_NO_IDLE_HZ 267#ifdef CONFIG_NO_IDLE_HZ
@@ -279,32 +270,22 @@ static __init void omap_init_32k_timer(void)
279 270
280 if (cpu_class_is_omap1()) 271 if (cpu_class_is_omap1())
281 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq); 272 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
282 if (cpu_is_omap24xx())
283 setup_irq(37, &omap_32k_timer_irq);
284 omap_timer.offset = omap_32k_timer_gettimeoffset; 273 omap_timer.offset = omap_32k_timer_gettimeoffset;
285 omap_32k_last_tick = omap_32k_sync_timer_read(); 274 omap_32k_last_tick = omap_32k_sync_timer_read();
286 275
276#ifdef CONFIG_ARCH_OMAP2
287 /* REVISIT: Check 24xx TIOCP_CFG settings after idle works */ 277 /* REVISIT: Check 24xx TIOCP_CFG settings after idle works */
288 if (cpu_is_omap24xx()) { 278 if (cpu_is_omap24xx()) {
289 omap_32k_timer_write(0, GP_TIMER_TCLR); 279 gptimer = omap_dm_timer_request_specific(1);
290 omap_writel(0, CM_CLKSEL_WKUP); /* 32KHz clock source */ 280 BUG_ON(gptimer == NULL);
291 281
292 gpt1_ick = clk_get(NULL, "gpt1_ick"); 282 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
293 if (IS_ERR(gpt1_ick)) 283 setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq);
294 printk(KERN_ERR "Could not get gpt1_ick\n"); 284 omap_dm_timer_set_int_enable(gptimer,
295 else 285 OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW |
296 clk_enable(gpt1_ick); 286 OMAP_TIMER_INT_MATCH);
297
298 gpt1_fck = clk_get(NULL, "gpt1_fck");
299 if (IS_ERR(gpt1_fck))
300 printk(KERN_ERR "Could not get gpt1_fck\n");
301 else
302 clk_enable(gpt1_fck);
303
304 mdelay(100); /* Wait for clocks to stabilize */
305
306 omap_32k_timer_write(0x7, GP_TIMER_TISR);
307 } 287 }
288#endif
308 289
309 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD); 290 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
310} 291}
@@ -316,6 +297,9 @@ static __init void omap_init_32k_timer(void)
316 */ 297 */
317static void __init omap_timer_init(void) 298static void __init omap_timer_init(void)
318{ 299{
300#ifdef CONFIG_OMAP_DM_TIMER
301 omap_dm_timer_init();
302#endif
319 omap_init_32k_timer(); 303 omap_init_32k_timer();
320} 304}
321 305
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 00:27:05 -0500