139 files changed, 3082 insertions, 1813 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 36c8b5e12590..4047f5724da3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -25,6 +25,7 @@ config ARM
         select HAVE_KERNEL_LZMA
         select HAVE_PERF_EVENTS
         select PERF_USE_VMALLOC
+        select HAVE_REGS_AND_STACK_ACCESS_API
         help
           The ARM series is a line of low-power-consumption RISC chip designs
           licensed by ARM Ltd and targeted at embedded applications and
@@ -440,21 +441,6 @@ config ARCH_IXP4XX
         help
           Support for Intel's IXP4XX (XScale) family of processors.
 
-config ARCH_L7200
-        bool "LinkUp-L7200"
-        select CPU_ARM720T
-        select FIQ
-        select ARCH_USES_GETTIMEOFFSET
-        help
-          Say Y here if you intend to run this kernel on a LinkUp Systems
-          L7200 Software Development Board which uses an ARM720T processor.
-          Information on this board can be obtained at:
-
-          <http://www.linkupsys.com/>
-
-          If you have any questions or comments about the Linux kernel port
-          to this board, send e-mail to <sjhill@cotw.com>.
-
 config ARCH_DOVE
         bool "Marvell Dove"
         select PCI
@@ -1031,11 +1017,6 @@ endmenu
 
 source "arch/arm/common/Kconfig"
 
-config FORCE_MAX_ZONEORDER
-        int
-        depends on SA1111
-        default "9"
-
 menu "Bus support"
 
 config ARM_AMBA
@@ -1172,9 +1153,10 @@ config HOTPLUG_CPU
 config LOCAL_TIMERS
         bool "Use local timer interrupts"
         depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
-                REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500)
+                REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
+                ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
         default y
-        select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500)
+        select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_VEXPRESS || ARCH_OMAP4 || ARCH_U8500)
         help
           Enable support for local timers on SMP platforms, rather then the
           legacy IPI broadcast method.  Local timers allows the system
@@ -1185,10 +1167,10 @@ source kernel/Kconfig.preempt
 
 config HZ
         int
-        default 128 if ARCH_L7200
         default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210
         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
         default AT91_TIMER_HZ if ARCH_AT91
+        default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
         default 100
 
 config THUMB2_KERNEL
@@ -1280,8 +1262,36 @@ config HW_PERF_EVENTS
           Enable hardware performance counter support for perf events. If
           disabled, perf events will use software events only.
 
+config SPARSE_IRQ
+        bool "Support sparse irq numbering"
+        depends on EXPERIMENTAL
+        help
+          This enables support for sparse irqs. This is useful in general
+          as most CPUs have a fairly sparse array of IRQ vectors, which
+          the irq_desc then maps directly on to. Systems with a high
+          number of off-chip IRQs will want to treat this as
+          experimental until they have been independently verified.
+
+          If you don't know what to do here, say N.
+
 source "mm/Kconfig"
 
+config FORCE_MAX_ZONEORDER
+        int "Maximum zone order" if ARCH_SHMOBILE
+        range 11 64 if ARCH_SHMOBILE
+        default "9" if SA1111
+        default "11"
+        help
+          The kernel memory allocator divides physically contiguous memory
+          blocks into "zones", where each zone is a power of two number of
+          pages.  This option selects the largest power of two that the kernel
+          keeps in the memory allocator.  If you need to allocate very large
+          blocks of physically contiguous memory, then you may need to
+          increase this value.
+
+          This config option is actually maximum order plus one. For example,
+          a value of 11 means that the largest free memory block is 2^10 pages.
+
 config LEDS
         bool "Timer and CPU usage LEDs"
         depends on ARCH_CDB89712 || ARCH_EBSA110 || \
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 64ba313724d2..bea37a2512e7 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -139,7 +139,6 @@ machine-$(CONFIG_ARCH_IXP23XX)		:= ixp23xx
 machine-$(CONFIG_ARCH_IXP4XX)           := ixp4xx
 machine-$(CONFIG_ARCH_KIRKWOOD)         := kirkwood
 machine-$(CONFIG_ARCH_KS8695)           := ks8695
-machine-$(CONFIG_ARCH_L7200)            := l7200
 machine-$(CONFIG_ARCH_LH7A40X)          := lh7a40x
 machine-$(CONFIG_ARCH_LOKI)             := loki
 machine-$(CONFIG_ARCH_MMP)              := mmp
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 53faa9063a03..7a29301d516b 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -19,10 +19,6 @@ ifeq ($(CONFIG_ARCH_SHARK),y)
 OBJS            += head-shark.o ofw-shark.o
 endif
 
-ifeq ($(CONFIG_ARCH_L7200),y)
-OBJS            += head-l7200.o
-endif
-
 ifeq ($(CONFIG_ARCH_P720T),y)
 # Borrow this code from SA1100
 OBJS            += head-sa1100.o
diff --git a/arch/arm/boot/compressed/head-l7200.S b/arch/arm/boot/compressed/head-l7200.S
deleted file mode 100644
index d0e3b20856cd..000000000000
--- a/arch/arm/boot/compressed/head-l7200.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/* 
- * linux/arch/arm/boot/compressed/head-l7200.S
- * 
- * Copyright (C) 2000 Steve Hill <sjhill@cotw.com>
- * 
- * Some code borrowed from Nicolas Pitre's 'head-sa1100.S' file. This
- * is merged with head.S by the linker.
- */
-
-#include <asm/mach-types.h>
-
-#ifndef CONFIG_ARCH_L7200
-#error What am I doing here...
-#endif
-
-                .section        ".start", "ax"
-
-__L7200_start:
-                mov     r0, #0x00100000         @ FLASH address of initrd
-                mov     r2, #0xf1000000         @ RAM address of initrd
-                add     r3, r2, #0x00700000     @ Size of initrd 
-1:
-                ldmia   r0!, {r4, r5, r6, r7}
-                stmia   r2!, {r4, r5, r6, r7}
-                cmp     r2, r3
-                ble     1b
-
-                mov     r8, #0                  @ Zero it out
-                mov     r7, #MACH_TYPE_L7200    @ Set architecture ID
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 337741f734ac..7dfa9a85bc0c 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -108,6 +108,51 @@ static void gic_unmask_irq(unsigned int irq)
         spin_unlock(&irq_controller_lock);
 }
 
+static int gic_set_type(unsigned int irq, unsigned int type)
+{
+        void __iomem *base = gic_dist_base(irq);
+        unsigned int gicirq = gic_irq(irq);
+        u32 enablemask = 1 << (gicirq % 32);
+        u32 enableoff = (gicirq / 32) * 4;
+        u32 confmask = 0x2 << ((gicirq % 16) * 2);
+        u32 confoff = (gicirq / 16) * 4;
+        bool enabled = false;
+        u32 val;
+
+        /* Interrupt configuration for SGIs can't be changed */
+        if (gicirq < 16)
+                return -EINVAL;
+
+        if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
+                return -EINVAL;
+
+        spin_lock(&irq_controller_lock);
+
+        val = readl(base + GIC_DIST_CONFIG + confoff);
+        if (type == IRQ_TYPE_LEVEL_HIGH)
+                val &= ~confmask;
+        else if (type == IRQ_TYPE_EDGE_RISING)
+                val |= confmask;
+
+        /*
+         * As recommended by the spec, disable the interrupt before changing
+         * the configuration
+         */
+        if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
+                writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
+                enabled = true;
+        }
+
+        writel(val, base + GIC_DIST_CONFIG + confoff);
+
+        if (enabled)
+                writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
+
+        spin_unlock(&irq_controller_lock);
+
+        return 0;
+}
+
 #ifdef CONFIG_SMP
 static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
 {
@@ -161,6 +206,7 @@ static struct irq_chip gic_chip = {
         .ack            = gic_ack_irq,
         .mask           = gic_mask_irq,
         .unmask         = gic_unmask_irq,
+        .set_type       = gic_set_type,
 #ifdef CONFIG_SMP
         .set_affinity   = gic_set_cpu,
 #endif
diff --git a/arch/arm/configs/lusl7200_defconfig b/arch/arm/configs/lusl7200_defconfig
deleted file mode 100644
index 816fc42884c9..000000000000
--- a/arch/arm/configs/lusl7200_defconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_HOTPLUG is not set
-CONFIG_MODULES=y
-CONFIG_ARCH_L7200=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x00010000
-CONFIG_ZBOOT_ROM_BSS=0xf03e0000
-CONFIG_ZBOOT_ROM=y
-CONFIG_CMDLINE="console=tty0 console=ttyLU1,115200 root=/dev/ram initrd=0xf1000000,0x005dac7b mem=32M"
-CONFIG_BINFMT_AOUT=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_EXT2_FS=y
-CONFIG_DEBUG_USER=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index f7bd52b1c365..c1062c317103 100644
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -19,6 +19,7 @@
 #define HWCAP_NEON      4096
 #define HWCAP_VFPv3     8192
 #define HWCAP_VFPv3D16  16384
+#define HWCAP_TLS       32768
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 /*
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 237282f7c762..2721a5814cb9 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -7,6 +7,8 @@
 #define irq_canonicalize(i)     (i)
 #endif
 
+#define NR_IRQS_LEGACY  16
+
 /*
  * Use this value to indicate lack of interrupt
  * capability
diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h
index df15a0dc228e..8ec9ef5c3c7b 100644
--- a/arch/arm/include/asm/kexec.h
+++ b/arch/arm/include/asm/kexec.h
@@ -19,10 +19,26 @@
 
 #ifndef __ASSEMBLY__
 
-struct kimage;
-/* Provide a dummy definition to avoid build failures. */
+/**
+ * crash_setup_regs() - save registers for the panic kernel
+ * @newregs: registers are saved here
+ * @oldregs: registers to be saved (may be %NULL)
+ *
+ * Function copies machine registers from @oldregs to @newregs. If @oldregs is
+ * %NULL then current registers are stored there.
+ */
 static inline void crash_setup_regs(struct pt_regs *newregs,
-                                        struct pt_regs *oldregs) { }
+                                    struct pt_regs *oldregs)
+{
+        if (oldregs) {
+                memcpy(newregs, oldregs, sizeof(*newregs));
+        } else {
+                __asm__ __volatile__ ("stmia %0, {r0 - r15}"
+                                      : : "r" (&newregs->ARM_r0));
+                __asm__ __volatile__ ("mrs %0, cpsr"
+                                      : "=r" (newregs->ARM_cpsr));
+        }
+}
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index d425f2b6efeb..8a0dd18ba642 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -20,6 +20,7 @@ struct machine_desc {
          * by assembler code in head.S, head-common.S
          */
         unsigned int            nr;             /* architecture number  */
+        unsigned int            nr_irqs;        /* number of IRQs */
         unsigned int            phys_io;        /* start of physical io */
         unsigned int            io_pg_offst;    /* byte offset for io 
                                                  * page tabe entry      */
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index 8920b2d6e3b8..ce3eee9fe26c 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -17,6 +17,7 @@ struct seq_file;
 /*
  * This is internal.  Do not use it.
  */
+extern unsigned int arch_nr_irqs;
 extern void (*init_arch_irq)(void);
 extern void init_FIQ(void);
 extern int show_fiq_list(struct seq_file *, void *);
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 9dcb11e59026..c974be8913a7 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -184,6 +184,42 @@ extern unsigned long profile_pc(struct pt_regs *regs);
 #define predicate(x)            ((x) & 0xf0000000)
 #define PREDICATE_ALWAYS        0xe0000000
 
+/*
+ * kprobe-based event tracer support
+ */
+#include <linux/stddef.h>
+#include <linux/types.h>
+#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))
+
+extern int regs_query_register_offset(const char *name);
+extern const char *regs_query_register_name(unsigned int offset);
+extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
+extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
+                                               unsigned int n);
+
+/**
+ * regs_get_register() - get register value from its offset
+ * @regs:          pt_regs from which register value is gotten
+ * @offset:    offset number of the register.
+ *
+ * regs_get_register returns the value of a register whose offset from @regs.
+ * The @offset is the offset of the register in struct pt_regs.
+ * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
+ */
+static inline unsigned long regs_get_register(struct pt_regs *regs,
+                                              unsigned int offset)
+{
+        if (unlikely(offset > MAX_REG_OFFSET))
+                return 0;
+        return *(unsigned long *)((unsigned long)regs + offset);
+}
+
+/* Valid only for Kernel mode traps. */
+static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
+{
+        return regs->ARM_sp;
+}
+
 #endif /* __KERNEL__ */
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
new file mode 100644
index 000000000000..e71d6ff8d104
--- /dev/null
+++ b/arch/arm/include/asm/tls.h
@@ -0,0 +1,46 @@
+#ifndef __ASMARM_TLS_H
+#define __ASMARM_TLS_H
+
+#ifdef __ASSEMBLY__
+        .macro set_tls_none, tp, tmp1, tmp2
+        .endm
+
+        .macro set_tls_v6k, tp, tmp1, tmp2
+        mcr     p15, 0, \tp, c13, c0, 3         @ set TLS register
+        .endm
+
+        .macro set_tls_v6, tp, tmp1, tmp2
+        ldr     \tmp1, =elf_hwcap
+        ldr     \tmp1, [\tmp1, #0]
+        mov     \tmp2, #0xffff0fff
+        tst     \tmp1, #HWCAP_TLS               @ hardware TLS available?
+        mcrne   p15, 0, \tp, c13, c0, 3         @ yes, set TLS register
+        streq   \tp, [\tmp2, #-15]              @ set TLS value at 0xffff0ff0
+        .endm
+
+        .macro set_tls_software, tp, tmp1, tmp2
+        mov     \tmp1, #0xffff0fff
+        str     \tp, [\tmp1, #-15]              @ set TLS value at 0xffff0ff0
+        .endm
+#endif
+
+#ifdef CONFIG_TLS_REG_EMUL
+#define tls_emu         1
+#define has_tls_reg             1
+#define set_tls         set_tls_none
+#elif __LINUX_ARM_ARCH__ >= 7 ||                                        \
+        (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
+#define tls_emu         0
+#define has_tls_reg             1
+#define set_tls         set_tls_v6k
+#elif __LINUX_ARM_ARCH__ == 6
+#define tls_emu         0
+#define has_tls_reg             (elf_hwcap & HWCAP_TLS)
+#define set_tls         set_tls_v6
+#else
+#define tls_emu         0
+#define has_tls_reg             0
+#define set_tls         set_tls_software
+#endif
+
+#endif  /* __ASMARM_TLS_H */
diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h
index 422f3cc204a2..3d5fc41ae8d3 100644
--- a/arch/arm/include/asm/vfpmacros.h
+++ b/arch/arm/include/asm/vfpmacros.h
@@ -3,6 +3,8 @@
  *
  * Assembler-only file containing VFP macros and register definitions.
  */
+#include <asm/hwcap.h>
+
 #include "vfp.h"
 
 @ Macros to allow building with old toolkits (with no VFP support)
@@ -22,12 +24,20 @@
         LDC     p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d0-d15}
 #endif
 #ifdef CONFIG_VFPv3
+#if __LINUX_ARM_ARCH__ <= 6
+        ldr     \tmp, =elf_hwcap                    @ may not have MVFR regs
+        ldr     \tmp, [\tmp, #0]
+        tst     \tmp, #HWCAP_VFPv3D16
+        ldceq   p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
+        addne   \base, \base, #32*4                 @ step over unused register space
+#else
         VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
         and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
         cmp     \tmp, #2                            @ 32 x 64bit registers?
         ldceql  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
         addne   \base, \base, #32*4                 @ step over unused register space
 #endif
+#endif
         .endm
 
         @ write all the working registers out of the VFP
@@ -38,10 +48,18 @@
         STC     p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d0-d15}
 #endif
 #ifdef CONFIG_VFPv3
+#if __LINUX_ARM_ARCH__ <= 6
+        ldr     \tmp, =elf_hwcap                    @ may not have MVFR regs
+        ldr     \tmp, [\tmp, #0]
+        tst     \tmp, #HWCAP_VFPv3D16
+        stceq   p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
+        addne   \base, \base, #32*4                 @ step over unused register space
+#else
         VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
         and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
         cmp     \tmp, #2                            @ 32 x 64bit registers?
         stceql  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
         addne   \base, \base, #32*4                 @ step over unused register space
 #endif
+#endif
         .endm
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 26d302c28e13..ea023c6aa31e 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_ARM_THUMBEE)	+= thumbee.o
 obj-$(CONFIG_KGDB)              += kgdb.o
 obj-$(CONFIG_ARM_UNWIND)        += unwind.o
 obj-$(CONFIG_HAVE_TCM)          += tcm.o
+obj-$(CONFIG_CRASH_DUMP)        += crash_dump.o
 
 obj-$(CONFIG_CRUNCH)            += crunch.o crunch-bits.o
 AFLAGS_crunch-bits.o            := -Wa,-mcpu=ep9312
diff --git a/arch/arm/kernel/crash_dump.c b/arch/arm/kernel/crash_dump.c
new file mode 100644
index 000000000000..cd3b853a8a6d
--- /dev/null
+++ b/arch/arm/kernel/crash_dump.c
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/kernel/crash_dump.c
+ *
+ * Copyright (C) 2010 Nokia Corporation.
+ * Author: Mika Westerberg
+ *
+ * This code is taken from arch/x86/kernel/crash_dump_64.c
+ *   Created by: Hariprasad Nellitheertha (hari@in.ibm.com)
+ *   Copyright (C) IBM Corporation, 2004. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/errno.h>
+#include <linux/crash_dump.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+
+/* stores the physical address of elf header of crash image */
+unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX;
+
+/**
+ * copy_oldmem_page() - copy one page from old kernel memory
+ * @pfn: page frame number to be copied
+ * @buf: buffer where the copied page is placed
+ * @csize: number of bytes to copy
+ * @offset: offset in bytes into the page
+ * @userbuf: if set, @buf is int he user address space
+ *
+ * This function copies one page from old kernel memory into buffer pointed by
+ * @buf. If @buf is in userspace, set @userbuf to %1. Returns number of bytes
+ * copied or negative error in case of failure.
+ */
+ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
+                         size_t csize, unsigned long offset,
+                         int userbuf)
+{
+        void *vaddr;
+
+        if (!csize)
+                return 0;
+
+        vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
+        if (!vaddr)
+                return -ENOMEM;
+
+        if (userbuf) {
+                if (copy_to_user(buf, vaddr + offset, csize)) {
+                        iounmap(vaddr);
+                        return -EFAULT;
+                }
+        } else {
+                memcpy(buf, vaddr + offset, csize);
+        }
+
+        iounmap(vaddr);
+        return csize;
+}
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 3fd7861de4d1..e864e482118a 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -22,6 +22,7 @@
 #include <asm/thread_notify.h>
 #include <asm/unwind.h>
 #include <asm/unistd.h>
+#include <asm/tls.h>
 
 #include "entry-header.S"
 
@@ -735,12 +736,7 @@ ENTRY(__switch_to)
 #ifdef CONFIG_MMU
         ldr     r6, [r2, #TI_CPU_DOMAIN]
 #endif
-#if defined(CONFIG_HAS_TLS_REG)
-        mcr     p15, 0, r3, c13, c0, 3          @ set TLS register
-#elif !defined(CONFIG_TLS_REG_EMUL)
-        mov     r4, #0xffff0fff
-        str     r3, [r4, #-15]                  @ TLS val at 0xffff0ff0
-#endif
+        set_tls r3, r4, r5
 #ifdef CONFIG_MMU
         mcr     p15, 0, r6, c3, c0, 0           @ Set domain register
 #endif
@@ -1005,17 +1001,12 @@ kuser_cmpxchg_fixup:
  */
 
 __kuser_get_tls:                                @ 0xffff0fe0
-
-#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
-        ldr     r0, [pc, #(16 - 8)]             @ TLS stored at 0xffff0ff0
-#else
-        mrc     p15, 0, r0, c13, c0, 3          @ read TLS register
-#endif
+        ldr     r0, [pc, #(16 - 8)]     @ read TLS, set in kuser_get_tls_init
         usr_ret lr
-
-        .rep    5
-        .word   0                       @ pad up to __kuser_helper_version
-        .endr
+        mrc     p15, 0, r0, c13, c0, 3  @ 0xffff0fe8 hardware TLS code
+        .rep    4
+        .word   0                       @ 0xffff0ff0 software TLS value, then
+        .endr                           @ pad up to __kuser_helper_version
 
 /*
  * Reference declaration:
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 3b3d2c80509c..c0d5c3b3a760 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -47,12 +47,14 @@
 #define irq_finish(irq) do { } while (0)
 #endif
 
+unsigned int arch_nr_irqs;
 void (*init_arch_irq)(void) __initdata = NULL;
 unsigned long irq_err_count;
 
 int show_interrupts(struct seq_file *p, void *v)
 {
         int i = *(loff_t *) v, cpu;
+        struct irq_desc *desc;
         struct irqaction * action;
         unsigned long flags;
 
@@ -67,24 +69,25 @@ int show_interrupts(struct seq_file *p, void *v)
                 seq_putc(p, '\n');
         }
 
-        if (i < NR_IRQS) {
-                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
-                action = irq_desc[i].action;
+        if (i < nr_irqs) {
+                desc = irq_to_desc(i);
+                raw_spin_lock_irqsave(&desc->lock, flags);
+                action = desc->action;
                 if (!action)
                         goto unlock;
 
                 seq_printf(p, "%3d: ", i);
                 for_each_present_cpu(cpu)
                         seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
-                seq_printf(p, " %10s", irq_desc[i].chip->name ? : "-");
+                seq_printf(p, " %10s", desc->chip->name ? : "-");
                 seq_printf(p, "  %s", action->name);
                 for (action = action->next; action; action = action->next)
                         seq_printf(p, ", %s", action->name);
 
                 seq_putc(p, '\n');
 unlock:
-                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
-        } else if (i == NR_IRQS) {
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
+        } else if (i == nr_irqs) {
 #ifdef CONFIG_FIQ
                 show_fiq_list(p, v);
 #endif
@@ -112,7 +115,7 @@ asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
          * Some hardware gives randomly wrong interrupts.  Rather
          * than crashing, do something sensible.
          */
-        if (unlikely(irq >= NR_IRQS)) {
+        if (unlikely(irq >= nr_irqs)) {
                 if (printk_ratelimit())
                         printk(KERN_WARNING "Bad IRQ%u\n", irq);
                 ack_bad_irq(irq);
@@ -132,12 +135,12 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
         struct irq_desc *desc;
         unsigned long flags;
 
-        if (irq >= NR_IRQS) {
+        if (irq >= nr_irqs) {
                 printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq);
                 return;
         }
 
-        desc = irq_desc + irq;
+        desc = irq_to_desc(irq);
         raw_spin_lock_irqsave(&desc->lock, flags);
         desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
         if (iflags & IRQF_VALID)
@@ -151,14 +154,25 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
 
 void __init init_IRQ(void)
 {
+        struct irq_desc *desc;
         int irq;
 
-        for (irq = 0; irq < NR_IRQS; irq++)
-                irq_desc[irq].status |= IRQ_NOREQUEST | IRQ_NOPROBE;
+        for (irq = 0; irq < nr_irqs; irq++) {
+                desc = irq_to_desc_alloc_node(irq, 0);
+                desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE;
+        }
 
         init_arch_irq();
 }
 
+#ifdef CONFIG_SPARSE_IRQ
+int __init arch_probe_nr_irqs(void)
+{
+        nr_irqs = arch_nr_irqs ? arch_nr_irqs : NR_IRQS;
+        return 0;
+}
+#endif
+
 #ifdef CONFIG_HOTPLUG_CPU
 
 static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
@@ -178,10 +192,9 @@ static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
 void migrate_irqs(void)
 {
         unsigned int i, cpu = smp_processor_id();
+        struct irq_desc *desc;
 
-        for (i = 0; i < NR_IRQS; i++) {
-                struct irq_desc *desc = irq_desc + i;
-
+        for_each_irq_desc(i, desc) {
                 if (desc->node == cpu) {
                         unsigned int newcpu = cpumask_any_and(desc->affinity,
                                                               cpu_online_mask);
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 598ca61e7bca..81e989858d42 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -43,6 +43,10 @@ void machine_shutdown(void)
 
 void machine_crash_shutdown(struct pt_regs *regs)
 {
+        local_irq_disable();
+        crash_save_cpu(regs, smp_processor_id());
+
+        printk(KERN_INFO "Loading crashdump kernel...\n");
 }
 
 void machine_kexec(struct kimage *image)
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 3f562a7c0a99..f99d489822d5 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -52,6 +52,102 @@
 #define BREAKINST_THUMB 0xde01
 #endif
 
+struct pt_regs_offset {
+        const char *name;
+        int offset;
+};
+
+#define REG_OFFSET_NAME(r) \
+        {.name = #r, .offset = offsetof(struct pt_regs, ARM_##r)}
+#define REG_OFFSET_END {.name = NULL, .offset = 0}
+
+static const struct pt_regs_offset regoffset_table[] = {
+        REG_OFFSET_NAME(r0),
+        REG_OFFSET_NAME(r1),
+        REG_OFFSET_NAME(r2),
+        REG_OFFSET_NAME(r3),
+        REG_OFFSET_NAME(r4),
+        REG_OFFSET_NAME(r5),
+        REG_OFFSET_NAME(r6),
+        REG_OFFSET_NAME(r7),
+        REG_OFFSET_NAME(r8),
+        REG_OFFSET_NAME(r9),
+        REG_OFFSET_NAME(r10),
+        REG_OFFSET_NAME(fp),
+        REG_OFFSET_NAME(ip),
+        REG_OFFSET_NAME(sp),
+        REG_OFFSET_NAME(lr),
+        REG_OFFSET_NAME(pc),
+        REG_OFFSET_NAME(cpsr),
+        REG_OFFSET_NAME(ORIG_r0),
+        REG_OFFSET_END,
+};
+
+/**
+ * regs_query_register_offset() - query register offset from its name
+ * @name:       the name of a register
+ *
+ * regs_query_register_offset() returns the offset of a register in struct
+ * pt_regs from its name. If the name is invalid, this returns -EINVAL;
+ */
+int regs_query_register_offset(const char *name)
+{
+        const struct pt_regs_offset *roff;
+        for (roff = regoffset_table; roff->name != NULL; roff++)
+                if (!strcmp(roff->name, name))
+                        return roff->offset;
+        return -EINVAL;
+}
+
+/**
+ * regs_query_register_name() - query register name from its offset
+ * @offset:     the offset of a register in struct pt_regs.
+ *
+ * regs_query_register_name() returns the name of a register from its
+ * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
+ */
+const char *regs_query_register_name(unsigned int offset)
+{
+        const struct pt_regs_offset *roff;
+        for (roff = regoffset_table; roff->name != NULL; roff++)
+                if (roff->offset == offset)
+                        return roff->name;
+        return NULL;
+}
+
+/**
+ * regs_within_kernel_stack() - check the address in the stack
+ * @regs:      pt_regs which contains kernel stack pointer.
+ * @addr:      address which is checked.
+ *
+ * regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
+ * If @addr is within the kernel stack, it returns true. If not, returns false.
+ */
+bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr)
+{
+        return ((addr & ~(THREAD_SIZE - 1))  ==
+                (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
+}
+
+/**
+ * regs_get_kernel_stack_nth() - get Nth entry of the stack
+ * @regs:       pt_regs which contains kernel stack pointer.
+ * @n:          stack entry number.
+ *
+ * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
+ * is specified by @regs. If the @n th entry is NOT in the kernel stack,
+ * this returns 0.
+ */
+unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n)
+{
+        unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
+        addr += n;
+        if (regs_within_kernel_stack(regs, (unsigned long)addr))
+                return *addr;
+        else
+                return 0;
+}
+
 /*
  * this routine will get a word off of the processes privileged stack.
  * the offset is how far from the base addr as stored in the THREAD.
diff --git a/arch/arm/kernel/relocate_kernel.S b/arch/arm/kernel/relocate_kernel.S
index 61930eb09029..fd26f8d65151 100644
--- a/arch/arm/kernel/relocate_kernel.S
+++ b/arch/arm/kernel/relocate_kernel.S
@@ -10,6 +10,12 @@ relocate_new_kernel:
         ldr     r0,kexec_indirection_page
         ldr     r1,kexec_start_address
 
+        /*
+         * If there is no indirection page (we are doing crashdumps)
+         * skip any relocation.
+         */
+        cmp     r0, #0
+        beq     2f
 
 0:      /* top, read another word for the indirection page */
         ldr     r3, [r0],#4
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 31b2643bb0c6..776ea1aa974b 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -19,6 +19,8 @@
 #include <linux/seq_file.h>
 #include <linux/screen_info.h>
 #include <linux/init.h>
+#include <linux/kexec.h>
+#include <linux/crash_dump.h>
 #include <linux/root_dev.h>
 #include <linux/cpu.h>
 #include <linux/interrupt.h>
@@ -270,6 +272,21 @@ static void __init cacheid_init(void)
 extern struct proc_info_list *lookup_processor_type(unsigned int);
 extern struct machine_desc *lookup_machine_type(unsigned int);
 
+static void __init feat_v6_fixup(void)
+{
+        int id = read_cpuid_id();
+
+        if ((id & 0xff0f0000) != 0x41070000)
+                return;
+
+        /*
+         * HWCAP_TLS is available only on 1136 r1p0 and later,
+         * see also kuser_get_tls_init.
+         */
+        if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0))
+                elf_hwcap &= ~HWCAP_TLS;
+}
+
 static void __init setup_processor(void)
 {
         struct proc_info_list *list;
@@ -312,6 +329,8 @@ static void __init setup_processor(void)
         elf_hwcap &= ~HWCAP_THUMB;
 #endif
 
+        feat_v6_fixup();
+
         cacheid_init();
         cpu_proc_init();
 }
@@ -663,6 +682,79 @@ static int __init customize_machine(void)
 }
 arch_initcall(customize_machine);
 
+#ifdef CONFIG_KEXEC
+static inline unsigned long long get_total_mem(void)
+{
+        unsigned long total;
+
+        total = max_low_pfn - min_low_pfn;
+        return total << PAGE_SHIFT;
+}
+
+/**
+ * reserve_crashkernel() - reserves memory are for crash kernel
+ *
+ * This function reserves memory area given in "crashkernel=" kernel command
+ * line parameter. The memory reserved is used by a dump capture kernel when
+ * primary kernel is crashing.
+ */
+static void __init reserve_crashkernel(void)
+{
+        unsigned long long crash_size, crash_base;
+        unsigned long long total_mem;
+        int ret;
+
+        total_mem = get_total_mem();
+        ret = parse_crashkernel(boot_command_line, total_mem,
+                                &crash_size, &crash_base);
+        if (ret)
+                return;
+
+        ret = reserve_bootmem(crash_base, crash_size, BOOTMEM_EXCLUSIVE);
+        if (ret < 0) {
+                printk(KERN_WARNING "crashkernel reservation failed - "
+                       "memory is in use (0x%lx)\n", (unsigned long)crash_base);
+                return;
+        }
+
+        printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
+               "for crashkernel (System RAM: %ldMB)\n",
+               (unsigned long)(crash_size >> 20),
+               (unsigned long)(crash_base >> 20),
+               (unsigned long)(total_mem >> 20));
+
+        crashk_res.start = crash_base;
+        crashk_res.end = crash_base + crash_size - 1;
+        insert_resource(&iomem_resource, &crashk_res);
+}
+#else
+static inline void reserve_crashkernel(void) {}
+#endif /* CONFIG_KEXEC */
+
+/*
+ * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by
+ * is_kdump_kernel() to determine if we are booting after a panic. Hence
+ * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE.
+ */
+
+#ifdef CONFIG_CRASH_DUMP
+/*
+ * elfcorehdr= specifies the location of elf core header stored by the crashed
+ * kernel. This option will be passed by kexec loader to the capture kernel.
+ */
+static int __init setup_elfcorehdr(char *arg)
+{
+        char *end;
+
+        if (!arg)
+                return -EINVAL;
+
+        elfcorehdr_addr = memparse(arg, &end);
+        return end > arg ? 0 : -EINVAL;
+}
+early_param("elfcorehdr", setup_elfcorehdr);
+#endif /* CONFIG_CRASH_DUMP */
+
 void __init setup_arch(char **cmdline_p)
 {
         struct tag *tags = (struct tag *)&init_tags;
@@ -724,6 +816,7 @@ void __init setup_arch(char **cmdline_p)
 #ifdef CONFIG_SMP
         smp_init_cpus();
 #endif
+        reserve_crashkernel();
 
         cpu_init();
         tcm_init();
@@ -731,6 +824,7 @@ void __init setup_arch(char **cmdline_p)
         /*
          * Set up various architecture-specific pointers
          */
+        arch_nr_irqs = mdesc->nr_irqs;
         init_arch_irq = mdesc->init_irq;
         system_timer = mdesc->timer;
         init_machine = mdesc->init_machine;
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 1621e5327b2a..cda78d59aa31 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -30,6 +30,7 @@
 #include <asm/unistd.h>
 #include <asm/traps.h>
 #include <asm/unwind.h>
+#include <asm/tls.h>
 
 #include "ptrace.h"
 #include "signal.h"
@@ -518,17 +519,20 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 
         case NR(set_tls):
                 thread->tp_value = regs->ARM_r0;
-#if defined(CONFIG_HAS_TLS_REG)
-                asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) );
-#elif !defined(CONFIG_TLS_REG_EMUL)
-                /*
-                 * User space must never try to access this directly.
-                 * Expect your app to break eventually if you do so.
-                 * The user helper at 0xffff0fe0 must be used instead.
-                 * (see entry-armv.S for details)
-                 */
-                *((unsigned int *)0xffff0ff0) = regs->ARM_r0;
-#endif
+                if (tls_emu)
+                        return 0;
+                if (has_tls_reg) {
+                        asm ("mcr p15, 0, %0, c13, c0, 3"
+                                : : "r" (regs->ARM_r0));
+                } else {
+                        /*
+                         * User space must never try to access this directly.
+                         * Expect your app to break eventually if you do so.
+                         * The user helper at 0xffff0fe0 must be used instead.
+                         * (see entry-armv.S for details)
+                         */
+                        *((unsigned int *)0xffff0ff0) = regs->ARM_r0;
+                }
                 return 0;
 
 #ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG
@@ -743,6 +747,16 @@ void __init trap_init(void)
         return;
 }
 
+static void __init kuser_get_tls_init(unsigned long vectors)
+{
+        /*
+         * vectors + 0xfe0 = __kuser_get_tls
+         * vectors + 0xfe8 = hardware TLS instruction at 0xffff0fe8
+         */
+        if (tls_emu || has_tls_reg)
+                memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4);
+}
+
 void __init early_trap_init(void)
 {
         unsigned long vectors = CONFIG_VECTORS_BASE;
@@ -761,6 +775,11 @@ void __init early_trap_init(void)
         memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);
 
         /*
+         * Do processor specific fixups for the kuser helpers
+         */
+        kuser_get_tls_init(vectors);
+
+        /*
          * Copy signal return handlers into the vector page, and
          * set sigreturn to be a pointer to these.
          */
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 030ba7219f48..59ff42ddf0ae 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -41,7 +41,6 @@ else
 endif
 
 lib-$(CONFIG_ARCH_RPC)          += ecard.o io-acorn.o floppydma.o
-lib-$(CONFIG_ARCH_L7200)        += io-acorn.o
 lib-$(CONFIG_ARCH_SHARK)        += io-shark.o
 
 $(obj)/csumpartialcopy.o:       $(obj)/csumpartialcopygeneric.S
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 841eaf8f27e2..939bccd70569 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -366,6 +366,17 @@ config MACH_STAMP9G20
 
 endif
 
+if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
+comment "AT91SAM9260/AT91SAM9G20 boards"
+
+config MACH_SNAPPER_9260
+        bool "Bluewater Systems Snapper 9260/9G20 module"
+        help
+          Select this if you are using the Bluewater Systems Snapper 9260 or
+          Snapper 9G20 modules.
+          <http://www.bluewatersys.com/>
+endif
+
 # ----------------------------------------------------------
 
 if ARCH_AT91SAM9G45
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c1f821e58222..ca2ac003f41f 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -66,6 +66,9 @@ obj-$(CONFIG_MACH_CPU9G20)	+= board-cpu9krea.o
 obj-$(CONFIG_MACH_STAMP9G20)    += board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)    += board-stamp9g20.o
 
+# AT91SAM9260/AT91SAM9G20 board-specific support
+obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
+
 # AT91SAM9G45 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
 
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 85166b7e69a1..753c0d31a3d3 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -20,6 +20,7 @@
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
 #include <mach/at91_shdwc.h>
+#include <mach/cpu.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -176,6 +177,13 @@ static struct clk mmc1_clk = {
         .type           = CLK_TYPE_PERIPHERAL,
 };
 
+/* Video decoder clock - Only for sam9m10/sam9m11 */
+static struct clk vdec_clk = {
+        .name           = "vdec_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_VDEC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+
 /* One additional fake clock for ohci */
 static struct clk ohci_clk = {
         .name           = "ohci_clk",
@@ -239,6 +247,9 @@ static void __init at91sam9g45_register_clocks(void)
         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
                 clk_register(periph_clocks[i]);
 
+        if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
+                clk_register(&vdec_clk);
+
         clk_register(&pck0);
         clk_register(&pck1);
 }
diff --git a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
index a4102d72cc9b..c49f5c003ee1 100644
--- a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
+++ b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
@@ -26,6 +26,9 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/at73c213.h>
 #include <linux/clk.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/consumer.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -235,6 +238,46 @@ static struct gpio_led ek_leds[] = {
         }
 };
 
+#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
+static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
+        REGULATOR_SUPPLY("AVDD", "0-001b"),
+        REGULATOR_SUPPLY("HPVDD", "0-001b"),
+        REGULATOR_SUPPLY("DBVDD", "0-001b"),
+        REGULATOR_SUPPLY("DCVDD", "0-001b"),
+};
+
+static struct regulator_init_data ek_avdd_reg_init_data = {
+        .constraints    = {
+                .name   = "3V3",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .consumer_supplies = ek_audio_consumer_supplies,
+        .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
+};
+
+static struct fixed_voltage_config ek_vdd_pdata = {
+        .supply_name    = "board-3V3",
+        .microvolts     = 3300000,
+        .gpio           = -EINVAL,
+        .enabled_at_boot = 0,
+        .init_data      = &ek_avdd_reg_init_data,
+};
+static struct platform_device ek_voltage_regulator = {
+        .name           = "reg-fixed-voltage",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ek_vdd_pdata,
+        },
+};
+static void __init ek_add_regulators(void)
+{
+        platform_device_register(&ek_voltage_regulator);
+}
+#else
+static void __init ek_add_regulators(void) {}
+#endif
+
 static struct i2c_board_info __initdata ek_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("24c512", 0x50),
@@ -256,6 +299,8 @@ static void __init ek_board_init(void)
         ek_add_device_nand();
         /* Ethernet */
         at91_add_device_eth(&ek_macb_data);
+        /* Regulators */
+        ek_add_regulators();
         /* MMC */
 #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
         at91_add_device_mci(0, &ek_mmc_data);
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index c11fd47aec5d..6ea9808b8868 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -27,6 +27,9 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/clk.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/consumer.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -269,6 +272,46 @@ static void __init ek_add_device_buttons(void)
 static void __init ek_add_device_buttons(void) {}
 #endif
 
+#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
+static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
+        REGULATOR_SUPPLY("AVDD", "0-001b"),
+        REGULATOR_SUPPLY("HPVDD", "0-001b"),
+        REGULATOR_SUPPLY("DBVDD", "0-001b"),
+        REGULATOR_SUPPLY("DCVDD", "0-001b"),
+};
+
+static struct regulator_init_data ek_avdd_reg_init_data = {
+        .constraints    = {
+                .name   = "3V3",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .consumer_supplies = ek_audio_consumer_supplies,
+        .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
+};
+
+static struct fixed_voltage_config ek_vdd_pdata = {
+        .supply_name    = "board-3V3",
+        .microvolts     = 3300000,
+        .gpio           = -EINVAL,
+        .enabled_at_boot = 0,
+        .init_data      = &ek_avdd_reg_init_data,
+};
+static struct platform_device ek_voltage_regulator = {
+        .name           = "reg-fixed-voltage",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ek_vdd_pdata,
+        },
+};
+static void __init ek_add_regulators(void)
+{
+        platform_device_register(&ek_voltage_regulator);
+}
+#else
+static void __init ek_add_regulators(void) {}
+#endif
+
 
 static struct i2c_board_info __initdata ek_i2c_devices[] = {
         {
@@ -294,6 +337,8 @@ static void __init ek_board_init(void)
         ek_add_device_nand();
         /* Ethernet */
         at91_add_device_eth(&ek_macb_data);
+        /* Regulators */
+        ek_add_regulators();
         /* MMC */
         at91_add_device_mmc(0, &ek_mmc_data);
         /* I2C */
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
new file mode 100644
index 000000000000..2c08ae4ad3a1
--- /dev/null
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -0,0 +1,189 @@
+/*
+ * linux/arch/arm/mach-at91/board-snapper9260.c
+ *
+ *  Copyright (C) 2010 Bluewater System Ltd
+ *
+ * Author: Andre Renaud <andre@bluewatersys.com>
+ * Author: Ryan Mallon  <ryan@bluewatersys.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/i2c/pca953x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/hardware.h>
+#include <mach/board.h>
+#include <mach/at91sam9_smc.h>
+
+#include "sam9_smc.h"
+#include "generic.h"
+
+#define SNAPPER9260_IO_EXP_GPIO(x)      (NR_BUILTIN_GPIO + (x))
+
+static void __init snapper9260_map_io(void)
+{
+        at91sam9260_initialize(18432000);
+
+        /* Debug on ttyS0 */
+        at91_register_uart(0, 0, 0);
+        at91_set_serial_console(0);
+
+        at91_register_uart(AT91SAM9260_ID_US0, 1,
+                           ATMEL_UART_CTS | ATMEL_UART_RTS);
+        at91_register_uart(AT91SAM9260_ID_US1, 2,
+                           ATMEL_UART_CTS | ATMEL_UART_RTS);
+        at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
+}
+
+static void __init snapper9260_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+static struct at91_usbh_data __initdata snapper9260_usbh_data = {
+        .ports          = 2,
+};
+
+static struct at91_udc_data __initdata snapper9260_udc_data = {
+        .vbus_pin               = SNAPPER9260_IO_EXP_GPIO(5),
+        .vbus_active_low        = 1,
+        .vbus_polled            = 1,
+};
+
+static struct at91_eth_data snapper9260_macb_data = {
+        .is_rmii        = 1,
+};
+
+static struct mtd_partition __initdata snapper9260_nand_partitions[] = {
+        {
+                .name   = "Preboot",
+                .offset = 0,
+                .size   = SZ_128K,
+        },
+        {
+                .name   = "Bootloader",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = SZ_256K,
+        },
+        {
+                .name   = "Environment",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = SZ_128K,
+        },
+        {
+                .name   = "Kernel",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = SZ_4M,
+        },
+        {
+                .name   = "Filesystem",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct mtd_partition * __init
+snapper9260_nand_partition_info(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(snapper9260_nand_partitions);
+        return snapper9260_nand_partitions;
+}
+
+static struct atmel_nand_data __initdata snapper9260_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+        .rdy_pin        = AT91_PIN_PC13,
+        .partition_info = snapper9260_nand_partition_info,
+        .bus_width_16   = 0,
+};
+
+static struct sam9_smc_config __initdata snapper9260_nand_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 0,
+        .ncs_write_setup        = 0,
+        .nwe_setup              = 0,
+
+        .ncs_read_pulse         = 5,
+        .nrd_pulse              = 2,
+        .ncs_write_pulse        = 5,
+        .nwe_pulse              = 2,
+
+        .read_cycle             = 7,
+        .write_cycle            = 7,
+
+        .mode                   = (AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+                                   AT91_SMC_EXNWMODE_DISABLE),
+        .tdf_cycles             = 1,
+};
+
+static struct pca953x_platform_data snapper9260_io_expander_data = {
+        .gpio_base              = SNAPPER9260_IO_EXP_GPIO(0),
+};
+
+static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
+        {
+                /* IO expander */
+                I2C_BOARD_INFO("max7312", 0x28),
+                .platform_data = &snapper9260_io_expander_data,
+        },
+        {
+                /* Audio codec */
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        },
+        {
+                /* RTC */
+                I2C_BOARD_INFO("isl1208", 0x6f),
+        },
+};
+
+static void __init snapper9260_add_device_nand(void)
+{
+        at91_set_A_periph(AT91_PIN_PC14, 0);
+        sam9_smc_configure(3, &snapper9260_nand_smc_config);
+        at91_add_device_nand(&snapper9260_nand_data);
+}
+
+static void __init snapper9260_board_init(void)
+{
+        at91_add_device_i2c(snapper9260_i2c_devices,
+                            ARRAY_SIZE(snapper9260_i2c_devices));
+        at91_add_device_serial();
+        at91_add_device_usbh(&snapper9260_usbh_data);
+        at91_add_device_udc(&snapper9260_udc_data);
+        at91_add_device_eth(&snapper9260_macb_data);
+        at91_add_device_ssc(AT91SAM9260_ID_SSC, (ATMEL_SSC_TF | ATMEL_SSC_TK |
+                                                 ATMEL_SSC_TD | ATMEL_SSC_RD));
+        snapper9260_add_device_nand();
+}
+
+MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = snapper9260_map_io,
+        .init_irq       = snapper9260_init_irq,
+        .init_machine   = snapper9260_board_init,
+MACHINE_END
+
+
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index d8c1ededaa75..9c6af9737485 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -84,7 +84,7 @@
  */
 #define AT91_ECC        (0xffffe200 - AT91_BASE_SYS)
 #define AT91_BCRAMC     (0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC    (0xffffe600 - AT91_BASE_SYS)
+#define AT91_DDRSDRC0   (0xffffe600 - AT91_BASE_SYS)
 #define AT91_SMC        (0xffffe800 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
 #define AT91_CCFG       (0xffffeb10 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
index 1499b1cbffdd..976f4a6c3353 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
@@ -15,7 +15,7 @@
 #ifndef AT91CAP9_DDRSDR_H
 #define AT91CAP9_DDRSDR_H
 
-#define AT91_DDRSDRC_MR         (AT91_DDRSDRC + 0x00)   /* Mode Register */
+#define AT91_DDRSDRC_MR         0x00    /* Mode Register */
 #define         AT91_DDRSDRC_MODE       (0xf << 0)              /* Command Mode */
 #define                 AT91_DDRSDRC_MODE_NORMAL                0
 #define                 AT91_DDRSDRC_MODE_NOP           1
@@ -25,10 +25,10 @@
 #define                 AT91_DDRSDRC_MODE_EXT_LMR       5
 #define                 AT91_DDRSDRC_MODE_DEEP          6
 
-#define AT91_DDRSDRC_RTR        (AT91_DDRSDRC + 0x04)   /* Refresh Timer Register */
+#define AT91_DDRSDRC_RTR        0x04    /* Refresh Timer Register */
 #define         AT91_DDRSDRC_COUNT      (0xfff << 0)            /* Refresh Timer Counter */
 
-#define AT91_DDRSDRC_CR         (AT91_DDRSDRC + 0x08)   /* Configuration Register */
+#define AT91_DDRSDRC_CR         0x08    /* Configuration Register */
 #define         AT91_DDRSDRC_NC         (3 << 0)                /* Number of Column Bits */
 #define                 AT91_DDRSDRC_NC_SDR8    (0 << 0)
 #define                 AT91_DDRSDRC_NC_SDR9    (1 << 0)
@@ -49,7 +49,7 @@
 #define         AT91_DDRSDRC_DLL        (1 << 7)                /* Reset DLL */
 #define         AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
 
-#define AT91_DDRSDRC_T0PR       (AT91_DDRSDRC + 0x0C)   /* Timing 0 Register */
+#define AT91_DDRSDRC_T0PR       0x0C    /* Timing 0 Register */
 #define         AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
 #define         AT91_DDRSDRC_TRCD       (0xf <<  4)             /* Row to Column delay */
 #define         AT91_DDRSDRC_TWR        (0xf <<  8)             /* Write recovery delay */
@@ -59,13 +59,13 @@
 #define         AT91_DDRSDRC_TWTR       (1   << 24)             /* Internal Write to Read delay */
 #define         AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
 
-#define AT91_DDRSDRC_T1PR       (AT91_DDRSDRC + 0x10)   /* Timing 1 Register */
+#define AT91_DDRSDRC_T1PR       0x10    /* Timing 1 Register */
 #define         AT91_DDRSDRC_TRFC       (0x1f << 0)             /* Row Cycle Delay */
 #define         AT91_DDRSDRC_TXSNR      (0xff << 8)             /* Exit self-refresh to non-read */
 #define         AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
 #define         AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
 
-#define AT91_DDRSDRC_LPR        (AT91_DDRSDRC + 0x18)   /* Low Power Register */
+#define AT91_DDRSDRC_LPR        0x18    /* Low Power Register */
 #define         AT91_DDRSDRC_LPCB               (3 << 0)        /* Low-power Configurations */
 #define                 AT91_DDRSDRC_LPCB_DISABLE               0
 #define                 AT91_DDRSDRC_LPCB_SELF_REFRESH          1
@@ -80,14 +80,14 @@
 #define                 AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES      (1 << 12)
 #define                 AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES     (2 << 12)
 
-#define AT91_DDRSDRC_MDR        (AT91_DDRSDRC + 0x1C)   /* Memory Device Register */
+#define AT91_DDRSDRC_MDR        0x1C    /* Memory Device Register */
 #define         AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
 #define                 AT91_DDRSDRC_MD_SDR             0
 #define                 AT91_DDRSDRC_MD_LOW_POWER_SDR   1
 #define                 AT91_DDRSDRC_MD_DDR             2
 #define                 AT91_DDRSDRC_MD_LOW_POWER_DDR   3
 
-#define AT91_DDRSDRC_DLLR       (AT91_DDRSDRC + 0x20)   /* DLL Information Register */
+#define AT91_DDRSDRC_DLLR       0x20    /* DLL Information Register */
 #define         AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
 #define         AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
 #define         AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
@@ -98,5 +98,11 @@
 #define         AT91_DDRSDRC_SDVAL      (0xff << 16)            /* Slave Delay value */
 #define         AT91_DDRSDRC_SDCVAL     (0xff << 24)            /* Slave Delay Correction value */
 
+/* Register access macros */
+#define at91_ramc_read(num, reg) \
+        at91_sys_read(AT91_DDRSDRC##num + reg)
+#define at91_ramc_write(num, reg, value) \
+        at91_sys_write(AT91_DDRSDRC##num + reg, value)
+
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 43c396b9b4cb..4e79036d3b80 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -84,7 +84,7 @@
  * System Peripherals (offset from AT91_BASE_SYS)
  */
 #define AT91_ECC        (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
 #define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
 #define AT91_CCFG       (0xffffef10 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 87de8be17484..2b5618518129 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -68,7 +68,7 @@
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
-#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
 #define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
 #define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
new file mode 100644
index 000000000000..d27b15ba8ebf
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -0,0 +1,130 @@
+/*
+ * Header file for the Atmel DDR/SDR SDRAM Controller
+ *
+ * Copyright (C) 2010 Atmel Corporation
+ *      Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91SAM9_DDRSDR_H
+#define AT91SAM9_DDRSDR_H
+
+#define AT91_DDRSDRC_MR         0x00    /* Mode Register */
+#define         AT91_DDRSDRC_MODE       (0x7 << 0)              /* Command Mode */
+#define                 AT91_DDRSDRC_MODE_NORMAL        0
+#define                 AT91_DDRSDRC_MODE_NOP           1
+#define                 AT91_DDRSDRC_MODE_PRECHARGE     2
+#define                 AT91_DDRSDRC_MODE_LMR           3
+#define                 AT91_DDRSDRC_MODE_REFRESH       4
+#define                 AT91_DDRSDRC_MODE_EXT_LMR       5
+#define                 AT91_DDRSDRC_MODE_DEEP          6
+
+#define AT91_DDRSDRC_RTR        0x04    /* Refresh Timer Register */
+#define         AT91_DDRSDRC_COUNT      (0xfff << 0)            /* Refresh Timer Counter */
+
+#define AT91_DDRSDRC_CR         0x08    /* Configuration Register */
+#define         AT91_DDRSDRC_NC         (3 << 0)                /* Number of Column Bits */
+#define                 AT91_DDRSDRC_NC_SDR8    (0 << 0)
+#define                 AT91_DDRSDRC_NC_SDR9    (1 << 0)
+#define                 AT91_DDRSDRC_NC_SDR10   (2 << 0)
+#define                 AT91_DDRSDRC_NC_SDR11   (3 << 0)
+#define                 AT91_DDRSDRC_NC_DDR9    (0 << 0)
+#define                 AT91_DDRSDRC_NC_DDR10   (1 << 0)
+#define                 AT91_DDRSDRC_NC_DDR11   (2 << 0)
+#define                 AT91_DDRSDRC_NC_DDR12   (3 << 0)
+#define         AT91_DDRSDRC_NR         (3 << 2)                /* Number of Row Bits */
+#define                 AT91_DDRSDRC_NR_11      (0 << 2)
+#define                 AT91_DDRSDRC_NR_12      (1 << 2)
+#define                 AT91_DDRSDRC_NR_13      (2 << 2)
+#define                 AT91_DDRSDRC_NR_14      (3 << 2)
+#define         AT91_DDRSDRC_CAS        (7 << 4)                /* CAS Latency */
+#define                 AT91_DDRSDRC_CAS_2      (2 << 4)
+#define                 AT91_DDRSDRC_CAS_3      (3 << 4)
+#define                 AT91_DDRSDRC_CAS_25     (6 << 4)
+#define         AT91_DDRSDRC_RST_DLL    (1 << 7)                /* Reset DLL */
+#define         AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
+#define         AT91_DDRSDRC_DIS_DLL    (1 << 9)                /* Disable DLL */
+#define         AT91_DDRSDRC_OCD        (1 << 12)               /* Off-Chip Driver */
+#define         AT91_DDRSDRC_DQMS       (1 << 16)               /* Mask Data is Shared */
+#define         AT91_DDRSDRC_ACTBST     (1 << 18)               /* Active Bank X to Burst Stop Read Access Bank Y */
+
+#define AT91_DDRSDRC_T0PR       0x0C    /* Timing 0 Register */
+#define         AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
+#define         AT91_DDRSDRC_TRCD       (0xf <<  4)             /* Row to Column delay */
+#define         AT91_DDRSDRC_TWR        (0xf <<  8)             /* Write recovery delay */
+#define         AT91_DDRSDRC_TRC        (0xf << 12)             /* Row cycle delay */
+#define         AT91_DDRSDRC_TRP        (0xf << 16)             /* Row precharge delay */
+#define         AT91_DDRSDRC_TRRD       (0xf << 20)             /* Active BankA to BankB */
+#define         AT91_DDRSDRC_TWTR       (0x7 << 24)             /* Internal Write to Read delay */
+#define         AT91_DDRSDRC_RED_WRRD   (0x1 << 27)             /* Reduce Write to Read Delay */
+#define         AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
+
+#define AT91_DDRSDRC_T1PR       0x10    /* Timing 1 Register */
+#define         AT91_DDRSDRC_TRFC       (0x1f << 0)             /* Row Cycle Delay */
+#define         AT91_DDRSDRC_TXSNR      (0xff << 8)             /* Exit self-refresh to non-read */
+#define         AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
+#define         AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
+
+#define AT91_DDRSDRC_T2PR       0x14    /* Timing 2 Register */
+#define         AT91_DDRSDRC_TXARD      (0xf  << 0)             /* Exit active power down delay to read command in mode "Fast Exit" */
+#define         AT91_DDRSDRC_TXARDS     (0xf  << 4)             /* Exit active power down delay to read command in mode "Slow Exit" */
+#define         AT91_DDRSDRC_TRPA       (0xf  << 8)             /* Row Precharge All delay */
+#define         AT91_DDRSDRC_TRTP       (0x7  << 12)            /* Read to Precharge delay */
+
+#define AT91_DDRSDRC_LPR        0x1C    /* Low Power Register */
+#define         AT91_DDRSDRC_LPCB       (3 << 0)                /* Low-power Configurations */
+#define                 AT91_DDRSDRC_LPCB_DISABLE               0
+#define                 AT91_DDRSDRC_LPCB_SELF_REFRESH          1
+#define                 AT91_DDRSDRC_LPCB_POWER_DOWN            2
+#define                 AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN       3
+#define         AT91_DDRSDRC_CLKFR      (1 << 2)        /* Clock Frozen */
+#define         AT91_DDRSDRC_PASR       (7 << 4)        /* Partial Array Self Refresh */
+#define         AT91_DDRSDRC_TCSR       (3 << 8)        /* Temperature Compensated Self Refresh */
+#define         AT91_DDRSDRC_DS         (3 << 10)       /* Drive Strength */
+#define         AT91_DDRSDRC_TIMEOUT    (3 << 12)       /* Time to define when Low Power Mode is enabled */
+#define                 AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES       (0 << 12)
+#define                 AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES      (1 << 12)
+#define                 AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES     (2 << 12)
+#define         AT91_DDRSDRC_APDE       (1 << 16)        /* Active power down exit time */
+#define         AT91_DDRSDRC_UPD_MR     (3 << 20)        /* Update load mode register and extended mode register */
+
+#define AT91_DDRSDRC_MDR        0x20    /* Memory Device Register */
+#define         AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
+#define                 AT91_DDRSDRC_MD_SDR             0
+#define                 AT91_DDRSDRC_MD_LOW_POWER_SDR   1
+#define                 AT91_DDRSDRC_MD_LOW_POWER_DDR   3
+#define                 AT91_DDRSDRC_MD_DDR2            6
+#define         AT91_DDRSDRC_DBW        (1 << 4)                /* Data Bus Width */
+#define                 AT91_DDRSDRC_DBW_32BITS         (0 <<  4)
+#define                 AT91_DDRSDRC_DBW_16BITS         (1 <<  4)
+
+#define AT91_DDRSDRC_DLL        0x24    /* DLL Information Register */
+#define         AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
+#define         AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
+#define         AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
+#define         AT91_DDRSDRC_MDVAL      (0xff <<  8)            /* Master Delay value */
+
+#define AT91_DDRSDRC_HS         0x2C    /* High Speed Register */
+#define         AT91_DDRSDRC_DIS_ATCP_RD        (1 << 2)        /* Anticip read access is disabled */
+
+#define AT91_DDRSDRC_DELAY(n)   (0x30 + (0x4 * (n)))    /* Delay I/O Register n */
+
+#define AT91_DDRSDRC_WPMR       0xE4    /* Write Protect Mode Register */
+#define         AT91_DDRSDRC_WP         (1 << 0)                /* Write protect enable */
+#define         AT91_DDRSDRC_WPKEY      (0xffffff << 8)         /* Write protect key */
+#define         AT91_DDRSDRC_KEY        (0x444452 << 8)         /* Write protect key = "DDR" */
+
+#define AT91_DDRSDRC_WPSR       0xE8    /* Write Protect Status Register */
+#define         AT91_DDRSDRC_WPVS       (1 << 0)                /* Write protect violation status */
+#define         AT91_DDRSDRC_WPVSRC     (0xffff << 8)           /* Write protect violation source */
+
+/* Register access macros */
+#define at91_ramc_read(num, reg) \
+        at91_sys_read(AT91_DDRSDRC##num + reg)
+#define at91_ramc_write(num, reg, value) \
+        at91_sys_write(AT91_DDRSDRC##num + reg, value)
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index b7260389f7ca..100f5a592926 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -17,7 +17,7 @@
 #define AT91SAM9_SDRAMC_H
 
 /* SDRAM Controller (SDRAMC) registers */
-#define AT91_SDRAMC_MR          (AT91_SDRAMC + 0x00)    /* SDRAM Controller Mode Register */
+#define AT91_SDRAMC_MR          0x00    /* SDRAM Controller Mode Register */
 #define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
 #define                 AT91_SDRAMC_MODE_NORMAL         0
 #define                 AT91_SDRAMC_MODE_NOP            1
@@ -27,10 +27,10 @@
 #define                 AT91_SDRAMC_MODE_EXT_LMR        5
 #define                 AT91_SDRAMC_MODE_DEEP           6
 
-#define AT91_SDRAMC_TR          (AT91_SDRAMC + 0x04)    /* SDRAM Controller Refresh Timer Register */
+#define AT91_SDRAMC_TR          0x04    /* SDRAM Controller Refresh Timer Register */
 #define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Counter */
 
-#define AT91_SDRAMC_CR          (AT91_SDRAMC + 0x08)    /* SDRAM Controller Configuration Register */
+#define AT91_SDRAMC_CR          0x08    /* SDRAM Controller Configuration Register */
 #define         AT91_SDRAMC_NC          (3 << 0)                /* Number of Column Bits */
 #define                 AT91_SDRAMC_NC_8        (0 << 0)
 #define                 AT91_SDRAMC_NC_9        (1 << 0)
@@ -57,7 +57,7 @@
 #define         AT91_SDRAMC_TRAS        (0xf << 24)             /* Active to Precharge Delay */
 #define         AT91_SDRAMC_TXSR        (0xf << 28)             /* Exit Self Refresh to Active Delay */
 
-#define AT91_SDRAMC_LPR         (AT91_SDRAMC + 0x10)    /* SDRAM Controller Low Power Register */
+#define AT91_SDRAMC_LPR         0x10    /* SDRAM Controller Low Power Register */
 #define         AT91_SDRAMC_LPCB                (3 << 0)        /* Low-power Configurations */
 #define                 AT91_SDRAMC_LPCB_DISABLE                0
 #define                 AT91_SDRAMC_LPCB_SELF_REFRESH           1
@@ -71,16 +71,21 @@
 #define                 AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
 #define                 AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES      (2 << 12)
 
-#define AT91_SDRAMC_IER         (AT91_SDRAMC + 0x14)    /* SDRAM Controller Interrupt Enable Register */
-#define AT91_SDRAMC_IDR         (AT91_SDRAMC + 0x18)    /* SDRAM Controller Interrupt Disable Register */
-#define AT91_SDRAMC_IMR         (AT91_SDRAMC + 0x1C)    /* SDRAM Controller Interrupt Mask Register */
-#define AT91_SDRAMC_ISR         (AT91_SDRAMC + 0x20)    /* SDRAM Controller Interrupt Status Register */
+#define AT91_SDRAMC_IER         0x14    /* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR         0x18    /* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR         0x1C    /* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR         0x20    /* SDRAM Controller Interrupt Status Register */
 #define         AT91_SDRAMC_RES         (1 << 0)                /* Refresh Error Status */
 
-#define AT91_SDRAMC_MDR         (AT91_SDRAMC + 0x24)    /* SDRAM Memory Device Register */
+#define AT91_SDRAMC_MDR         0x24    /* SDRAM Memory Device Register */
 #define         AT91_SDRAMC_MD          (3 << 0)                /* Memory Device Type */
 #define                 AT91_SDRAMC_MD_SDRAM            0
 #define                 AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
 
+/* Register access macros */
+#define at91_ramc_read(num, reg) \
+        at91_sys_read(AT91_SDRAMC##num + reg)
+#define at91_ramc_write(num, reg, value) \
+        at91_sys_write(AT91_SDRAMC##num + reg, value)
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index fc2de6c09c86..87ba8517ad98 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -74,7 +74,7 @@
  */
 #define AT91_DMA        (0xffffe600 - AT91_BASE_SYS)
 #define AT91_ECC        (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
 #define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
 #define AT91_CCFG       (0xffffef10 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index df2ed848c9f8..58528aa9c8a8 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -44,6 +44,8 @@
  /* USB Device */
 struct at91_udc_data {
         u8      vbus_pin;               /* high == host powering us */
+        u8      vbus_active_low;        /* vbus polarity */
+        u8      vbus_polled;            /* Use polling, not interrupt */
         u8      pullup_pin;             /* active == D+ pulled up */
         u8      pullup_active_low;      /* true == pullup_pin is active low */
 };
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 833659d1200a..3bef931d0b1c 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -52,6 +52,7 @@ static inline unsigned long at91_cpu_fully_identify(void)
 
 #define ARCH_EXID_AT91SAM9M11   0x00000001
 #define ARCH_EXID_AT91SAM9M10   0x00000002
+#define ARCH_EXID_AT91SAM9G46   0x00000003
 #define ARCH_EXID_AT91SAM9G45   0x00000004
 
 static inline unsigned long at91_exid_identify(void)
@@ -128,9 +129,18 @@ static inline unsigned long at91cap9_rev_identify(void)
 #ifdef CONFIG_ARCH_AT91SAM9G45
 #define cpu_is_at91sam9g45()    (at91_cpu_identify() == ARCH_ID_AT91SAM9G45)
 #define cpu_is_at91sam9g45es()  (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES)
+#define cpu_is_at91sam9m10()    (cpu_is_at91sam9g45() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9M10))
+#define cpu_is_at91sam9m46()    (cpu_is_at91sam9g45() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9G46))
+#define cpu_is_at91sam9m11()    (cpu_is_at91sam9g45() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9M11))
 #else
 #define cpu_is_at91sam9g45()    (0)
 #define cpu_is_at91sam9g45es()  (0)
+#define cpu_is_at91sam9m10()    (0)
+#define cpu_is_at91sam9g46()    (0)
+#define cpu_is_at91sam9m11()    (0)
 #endif
 
 #ifdef CONFIG_ARCH_AT91CAP9
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index 04c91e31c9c5..bfdd8ab26dc8 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -19,6 +19,7 @@
 #define PIN_BASE                NR_AIC_IRQS
 
 #define MAX_GPIO_BANKS          5
+#define NR_BUILTIN_GPIO         (PIN_BASE + (MAX_GPIO_BANKS * 32))
 
 /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
 
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 08322c44df1a..8c87d0c1b8f8 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -30,14 +30,50 @@ static inline u32 sdram_selfrefresh_enable(void)
 {
         u32 saved_lpr, lpr;
 
-        saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
+        saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
 
         lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
-        at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
+        at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
         return saved_lpr;
 }
 
-#define sdram_selfrefresh_disable(saved_lpr)    at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
+#define sdram_selfrefresh_disable(saved_lpr)    at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
+
+#elif defined(CONFIG_ARCH_AT91SAM9G45)
+#include <mach/at91sam9_ddrsdr.h>
+
+/* We manage both DDRAM/SDRAM controllers, we need more than one value to
+ * remember.
+ */
+static u32 saved_lpr1;
+
+static inline u32 sdram_selfrefresh_enable(void)
+{
+        /* Those tow values allow us to delay self-refresh activation
+         * to the maximum. */
+        u32 lpr0, lpr1;
+        u32 saved_lpr0;
+
+        saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
+        lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
+        lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
+
+        saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
+        lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
+        lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
+
+        /* self-refresh mode now */
+        at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
+        at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
+
+        return saved_lpr0;
+}
+
+#define sdram_selfrefresh_disable(saved_lpr0)   \
+        do { \
+                at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
+                at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
+        } while (0)
 
 #else
 #include <mach/at91sam9_sdramc.h>
@@ -47,7 +83,6 @@ static inline u32 sdram_selfrefresh_enable(void)
  * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
  * handle those cases both here and in the Suspend-To-RAM support.
  */
-#define AT91_SDRAMC     AT91_SDRAMC0
 #warning Assuming EB1 SDRAM controller is *NOT* used
 #endif
 
@@ -55,13 +90,13 @@ static inline u32 sdram_selfrefresh_enable(void)
 {
         u32 saved_lpr, lpr;
 
-        saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
+        saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
 
         lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
-        at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
+        at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
         return saved_lpr;
 }
 
-#define sdram_selfrefresh_disable(saved_lpr)    at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
+#define sdram_selfrefresh_disable(saved_lpr)    at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
 
 #endif
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 9c5b48e68a71..b6b00a1f6125 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -16,10 +16,12 @@
 #include <mach/hardware.h>
 #include <mach/at91_pmc.h>
 
-#ifdef CONFIG_ARCH_AT91RM9200
+#if defined(CONFIG_ARCH_AT91RM9200)
 #include <mach/at91rm9200_mc.h>
 #elif defined(CONFIG_ARCH_AT91CAP9)
 #include <mach/at91cap9_ddrsdr.h>
+#elif defined(CONFIG_ARCH_AT91SAM9G45)
+#include <mach/at91sam9_ddrsdr.h>
 #else
 #include <mach/at91sam9_sdramc.h>
 #endif
@@ -30,7 +32,6 @@
  * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
  * handle those cases both here and in the Suspend-To-RAM support.
  */
-#define AT91_SDRAMC     AT91_SDRAMC0
 #warning Assuming EB1 SDRAM controller is *NOT* used
 #endif
 
@@ -113,12 +114,14 @@ ENTRY(at91_slow_clock)
         /*
          * Register usage:
          *  R1 = Base address of AT91_PMC
-         *  R2 = Base address of AT91_SDRAMC (or AT91_SYS on AT91RM9200)
+         *  R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
          *  R3 = temporary register
          *  R4 = temporary register
+         *  R5 = Base address of second RAM Controller or 0 if not present
          */
         ldr     r1, .at91_va_base_pmc
         ldr     r2, .at91_va_base_sdramc
+        ldr     r5, .at91_va_base_ramc1
 
         /* Drain write buffer */
         mcr     p15, 0, r0, c7, c10, 4
@@ -127,20 +130,33 @@ ENTRY(at91_slow_clock)
         /* Put SDRAM in self-refresh mode */
         mov     r3, #1
         str     r3, [r2, #AT91_SDRAMC_SRR]
-#elif defined(CONFIG_ARCH_AT91CAP9)
-        /* Enable SDRAM self-refresh mode */
-        ldr     r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
-        str     r3, .saved_sam9_lpr
+#elif defined(CONFIG_ARCH_AT91CAP9) \
+        || defined(CONFIG_ARCH_AT91SAM9G45)
 
-        mov     r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
-        str     r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
+        /* prepare for DDRAM self-refresh mode */
+        ldr     r3, [r2, #AT91_DDRSDRC_LPR]
+        str     r3, .saved_sam9_lpr
+        bic     r3, #AT91_DDRSDRC_LPCB
+        orr     r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+
+        /* figure out if we use the second ram controller */
+        cmp     r5, #0
+        ldrne   r4, [r5, #AT91_DDRSDRC_LPR]
+        strne   r4, .saved_sam9_lpr1
+        bicne   r4, #AT91_DDRSDRC_LPCB
+        orrne   r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+
+        /* Enable DDRAM self-refresh mode */
+        str     r3, [r2, #AT91_DDRSDRC_LPR]
+        strne   r4, [r5, #AT91_DDRSDRC_LPR]
 #else
         /* Enable SDRAM self-refresh mode */
-        ldr     r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
+        ldr     r3, [r2, #AT91_SDRAMC_LPR]
         str     r3, .saved_sam9_lpr
 
-        mov     r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
-        str     r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
+        bic     r3, #AT91_SDRAMC_LPCB
+        orr     r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
+        str     r3, [r2, #AT91_SDRAMC_LPR]
 #endif
 
         /* Save Master clock setting */
@@ -247,14 +263,21 @@ ENTRY(at91_slow_clock)
 
 #ifdef CONFIG_ARCH_AT91RM9200
         /* Do nothing - self-refresh is automatically disabled. */
-#elif defined(CONFIG_ARCH_AT91CAP9)
-        /* Restore LPR on AT91CAP9 */
+#elif defined(CONFIG_ARCH_AT91CAP9) \
+        || defined(CONFIG_ARCH_AT91SAM9G45)
+        /* Restore LPR on AT91 with DDRAM */
         ldr     r3, .saved_sam9_lpr
-        str     r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
+        str     r3, [r2, #AT91_DDRSDRC_LPR]
+
+        /* if we use the second ram controller */
+        cmp     r5, #0
+        ldrne   r4, .saved_sam9_lpr1
+        strne   r4, [r5, #AT91_DDRSDRC_LPR]
+
 #else
-        /* Restore LPR on AT91SAM9 */
+        /* Restore LPR on AT91 with SDRAM */
         ldr     r3, .saved_sam9_lpr
-        str     r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
+        str     r3, [r2, #AT91_SDRAMC_LPR]
 #endif
 
         /* Restore registers, and return */
@@ -273,18 +296,29 @@ ENTRY(at91_slow_clock)
 .saved_sam9_lpr:
         .word 0
 
+.saved_sam9_lpr1:
+        .word 0
+
 .at91_va_base_pmc:
         .word AT91_VA_BASE_SYS + AT91_PMC
 
 #ifdef CONFIG_ARCH_AT91RM9200
 .at91_va_base_sdramc:
         .word AT91_VA_BASE_SYS
-#elif defined(CONFIG_ARCH_AT91CAP9)
+#elif defined(CONFIG_ARCH_AT91CAP9) \
+        || defined(CONFIG_ARCH_AT91SAM9G45)
 .at91_va_base_sdramc:
-        .word AT91_VA_BASE_SYS + AT91_DDRSDRC
+        .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
 #else
 .at91_va_base_sdramc:
-        .word AT91_VA_BASE_SYS + AT91_SDRAMC
+        .word AT91_VA_BASE_SYS + AT91_SDRAMC0
+#endif
+
+.at91_va_base_ramc1:
+#if defined(CONFIG_ARCH_AT91SAM9G45)
+        .word AT91_VA_BASE_SYS + AT91_DDRSDRC1
+#else
+        .word 0
 #endif
 
 ENTRY(at91_slow_clock_sz)
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index 72e405df0fb0..d3f959e92b2d 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -91,14 +91,23 @@ static struct clk uart_clk = {
         .parent = &pll1_clk,
 };
 
+static struct clk dummy_apb_pclk = {
+        .name = "BUSCLK",
+        .type = CLK_TYPE_PRIMARY,
+        .mode = CLK_MODE_XTAL,
+};
+
 static struct clk_lookup lookups[] = {
-        {                       /* UART0 */
-         .dev_id = "uarta",
-         .clk = &uart_clk,
-         }, {                   /* UART1 */
-             .dev_id = "uartb",
-             .clk = &uart_clk,
-             }
+        {                       /* Bus clock */
+                .con_id = "apb_pclk",
+                .clk = &dummy_apb_pclk,
+        }, {                    /* UART0 */
+                .dev_id = "uarta",
+                .clk = &uart_clk,
+        }, {                    /* UART1 */
+                .dev_id = "uartb",
+                .clk = &uart_clk,
+        }
 };
 
 static struct amba_device *amba_devs[] __initdata = {
diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S
index fedd8076a689..072cc6b61ba3 100644
--- a/arch/arm/mach-clps711x/include/mach/debug-macro.S
+++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S
@@ -11,6 +11,7 @@
  *
 */
 
+#include <mach/hardware.h>
 #include <asm/hardware/clps7111.h>
 
                 .macro  addruart, rx, tmp
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 2ec3095ffb7b..b280efb1fa12 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -25,6 +25,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/regulator/machine.h>
+#include <linux/regulator/tps6507x.h>
 #include <linux/mfd/tps6507x.h>
 #include <linux/input/tps6507x-ts.h>
 
@@ -469,6 +470,11 @@ struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
         },
 };
 
+/* We take advantage of the fact that both defdcdc{2,3} are tied high */
+static struct tps6507x_reg_platform_data tps6507x_platform_data = {
+        .defdcdc_default = true,
+};
+
 struct regulator_init_data tps65070_regulator_data[] = {
         /* dcdc1 */
         {
@@ -494,6 +500,7 @@ struct regulator_init_data tps65070_regulator_data[] = {
                 },
                 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers),
                 .consumer_supplies = tps65070_dcdc2_consumers,
+                .driver_data = &tps6507x_platform_data,
         },
 
         /* dcdc3 */
@@ -507,6 +514,7 @@ struct regulator_init_data tps65070_regulator_data[] = {
                 },
                 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers),
                 .consumer_supplies = tps65070_dcdc3_consumers,
+                .driver_data = &tps6507x_platform_data,
         },
 
         /* ldo1 */
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 3a1a855bfdca..f744f676783f 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -13,7 +13,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 
 #include <mach/hardware.h>
 
@@ -21,26 +20,6 @@
 #include <asm/mach/arch.h>
 
 
-static struct physmap_flash_data adssphere_flash_data = {
-        .width          = 4,
-};
-
-static struct resource adssphere_flash_resource = {
-        .start          = EP93XX_CS6_PHYS_BASE,
-        .end            = EP93XX_CS6_PHYS_BASE + SZ_32M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device adssphere_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &adssphere_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &adssphere_flash_resource,
-};
-
 static struct ep93xx_eth_data __initdata adssphere_eth_data = {
         .phy_id         = 1,
 };
@@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata adssphere_eth_data = {
 static void __init adssphere_init_machine(void)
 {
         ep93xx_init_devices();
-        platform_device_register(&adssphere_flash);
-
+        ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
         ep93xx_register_eth(&adssphere_eth_data, 1);
 }
 
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index e29bdef9b2e2..7f3039761d91 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -185,7 +185,7 @@ static struct clk_lookup clocks[] = {
         INIT_CK(NULL,                   "pll1",         &clk_pll1),
         INIT_CK(NULL,                   "fclk",         &clk_f),
         INIT_CK(NULL,                   "hclk",         &clk_h),
-        INIT_CK(NULL,                   "pclk",         &clk_p),
+        INIT_CK(NULL,                   "apb_pclk",     &clk_p),
         INIT_CK(NULL,                   "pll2",         &clk_pll2),
         INIT_CK("ep93xx-ohci",          NULL,           &clk_usb_host),
         INIT_CK("ep93xx-keypad",        NULL,           &clk_keypad),
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 9092677f63eb..8e37a045188c 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -29,6 +29,7 @@
 #include <linux/termios.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
+#include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 #include <linux/spi/spi.h>
@@ -215,8 +216,8 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
         spin_lock_irqsave(&syscon_swlock, flags);
 
         val = __raw_readl(EP93XX_SYSCON_DEVCFG);
-        val |= set_bits;
         val &= ~clear_bits;
+        val |= set_bits;
         __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
         __raw_writel(val, EP93XX_SYSCON_DEVCFG);
 
@@ -348,6 +349,43 @@ static struct platform_device ep93xx_ohci_device = {
 
 
 /*************************************************************************
+ * EP93xx physmap'ed flash
+ *************************************************************************/
+static struct physmap_flash_data ep93xx_flash_data;
+
+static struct resource ep93xx_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device ep93xx_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &ep93xx_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &ep93xx_flash_resource,
+};
+
+/**
+ * ep93xx_register_flash() - Register the external flash device.
+ * @width:      bank width in octets
+ * @start:      resource start address
+ * @size:       resource size
+ */
+void __init ep93xx_register_flash(unsigned int width,
+                                  resource_size_t start, resource_size_t size)
+{
+        ep93xx_flash_data.width         = width;
+
+        ep93xx_flash_resource.start     = start;
+        ep93xx_flash_resource.end       = start + size - 1;
+
+        platform_device_register(&ep93xx_flash);
+}
+
+
+/*************************************************************************
  * EP93xx ethernet peripheral handling
  *************************************************************************/
 static struct ep93xx_eth_data ep93xx_eth_data;
@@ -620,6 +658,11 @@ static struct platform_device ep93xx_fb_device = {
         .resource               = ep93xx_fb_resource,
 };
 
+static struct platform_device ep93xx_bl_device = {
+        .name           = "ep93xx-bl",
+        .id             = -1,
+};
+
 /**
  * ep93xx_register_fb - Register the framebuffer platform device.
  * @data:       platform specific framebuffer configuration (__initdata)
@@ -628,6 +671,7 @@ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
 {
         ep93xxfb_data = *data;
         platform_device_register(&ep93xx_fb_device);
+        platform_device_register(&ep93xx_bl_device);
 }
 
 
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 3884182cd362..c2ce9034ba87 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -27,7 +27,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 #include <linux/gpio.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
@@ -38,39 +37,13 @@
 #include <asm/mach/arch.h>
 
 
-static struct physmap_flash_data edb93xx_flash_data;
-
-static struct resource edb93xx_flash_resource = {
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device edb93xx_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &edb93xx_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &edb93xx_flash_resource,
-};
-
-static void __init __edb93xx_register_flash(unsigned int width,
-                        resource_size_t start, resource_size_t size)
-{
-        edb93xx_flash_data.width        = width;
-        edb93xx_flash_resource.start    = start;
-        edb93xx_flash_resource.end      = start + size - 1;
-
-        platform_device_register(&edb93xx_flash);
-}
-
 static void __init edb93xx_register_flash(void)
 {
         if (machine_is_edb9307() || machine_is_edb9312() ||
             machine_is_edb9315()) {
-                __edb93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
+                ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
         } else {
-                __edb93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
+                ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
         }
 }
 
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index a809618e9f05..d97168c0ba33 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -13,7 +13,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 
 #include <mach/hardware.h>
 
@@ -21,26 +20,6 @@
 #include <asm/mach/arch.h>
 
 
-static struct physmap_flash_data gesbc9312_flash_data = {
-        .width          = 4,
-};
-
-static struct resource gesbc9312_flash_resource = {
-        .start          = EP93XX_CS6_PHYS_BASE,
-        .end            = EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device gesbc9312_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &gesbc9312_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &gesbc9312_flash_resource,
-};
-
 static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
         .phy_id         = 1,
 };
@@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
 static void __init gesbc9312_init_machine(void)
 {
         ep93xx_init_devices();
-        platform_device_register(&gesbc9312_flash);
-
+        ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_8M);
         ep93xx_register_eth(&gesbc9312_eth_data, 0);
 }
 
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index 9a4413dd44bb..a6c09176334c 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -43,6 +43,9 @@ static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
 
 unsigned int ep93xx_chip_revision(void);
 
+void ep93xx_register_flash(unsigned int width,
+                           resource_size_t start, resource_size_t size);
+
 void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr);
 void ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
                          struct i2c_board_info *devices, int num);
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 1cc911b4efa6..2ba776320a82 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -14,7 +14,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -31,31 +30,6 @@
  * Micro9-Lite uses a separate MTD map driver for flash support
  * Micro9-Slim has up to 64MB of either 32-bit or 16-bit flash on CS1
  *************************************************************************/
-static struct physmap_flash_data micro9_flash_data;
-
-static struct resource micro9_flash_resource = {
-        .start          = EP93XX_CS1_PHYS_BASE,
-        .end            = EP93XX_CS1_PHYS_BASE + SZ_64M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device micro9_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &micro9_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &micro9_flash_resource,
-};
-
-static void __init __micro9_register_flash(unsigned int width)
-{
-        micro9_flash_data.width = width;
-
-        platform_device_register(&micro9_flash);
-}
-
 static unsigned int __init micro9_detect_bootwidth(void)
 {
         u32 v;
@@ -70,10 +44,17 @@ static unsigned int __init micro9_detect_bootwidth(void)
 
 static void __init micro9_register_flash(void)
 {
+        unsigned int width;
+
         if (machine_is_micro9())
-                __micro9_register_flash(4);
+                width = 4;
         else if (machine_is_micro9m() || machine_is_micro9s())
-                __micro9_register_flash(micro9_detect_bootwidth());
+                width = micro9_detect_bootwidth();
+        else
+                width = 0;
+
+        if (width)
+                ep93xx_register_flash(width, EP93XX_CS1_PHYS_BASE, SZ_64M);
 }
 
 
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index 388aec95f60e..5dded5884133 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -18,7 +18,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 #include <linux/gpio.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
@@ -29,26 +28,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-static struct physmap_flash_data simone_flash_data = {
-        .width          = 2,
-};
-
-static struct resource simone_flash_resource = {
-        .start          = EP93XX_CS6_PHYS_BASE,
-        .end            = EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device simone_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = &simone_flash_resource,
-        .dev = {
-                .platform_data  = &simone_flash_data,
-        },
-};
-
 static struct ep93xx_eth_data __initdata simone_eth_data = {
         .phy_id         = 1,
 };
@@ -77,8 +56,7 @@ static struct i2c_board_info __initdata simone_i2c_board_info[] = {
 static void __init simone_init_machine(void)
 {
         ep93xx_init_devices();
-
-        platform_device_register(&simone_flash);
+        ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_8M);
         ep93xx_register_eth(&simone_eth_data, 1);
         ep93xx_register_fb(&simone_fb_info);
         ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info,
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index ae7319e588c7..93aeab8af705 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -17,7 +17,6 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/m48t86.h>
-#include <linux/mtd/physmap.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 
@@ -173,31 +172,13 @@ static struct platform_device ts72xx_nand_flash = {
 };
 
 
-/*************************************************************************
- * NOR flash (TS-7200 only)
- *************************************************************************/
-static struct physmap_flash_data ts72xx_nor_data = {
-        .width          = 2,
-};
-
-static struct resource ts72xx_nor_resource = {
-        .start          = EP93XX_CS6_PHYS_BASE,
-        .end            = EP93XX_CS6_PHYS_BASE + SZ_16M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device ts72xx_nor_flash = {
-        .name                   = "physmap-flash",
-        .id                     = 0,
-        .dev.platform_data      = &ts72xx_nor_data,
-        .resource               = &ts72xx_nor_resource,
-        .num_resources          = 1,
-};
-
 static void __init ts72xx_register_flash(void)
 {
+        /*
+         * TS7200 has NOR flash all other TS72xx board have NAND flash.
+         */
         if (board_is_ts7200()) {
-                platform_device_register(&ts72xx_nor_flash);
+                ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
         } else {
                 resource_size_t start;
 
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index e3bc3f6f6b10..88b3dd89be89 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -232,7 +232,7 @@ EXPORT_SYMBOL(__bus_to_virt);
 
 unsigned long __pfn_to_bus(unsigned long pfn)
 {
-        return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET));
+        return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET);
 }
 EXPORT_SYMBOL(__pfn_to_bus);
 
diff --git a/arch/arm/mach-h720x/include/mach/debug-macro.S b/arch/arm/mach-h720x/include/mach/debug-macro.S
index a9ee8f0d48b7..27cafd12f033 100644
--- a/arch/arm/mach-h720x/include/mach/debug-macro.S
+++ b/arch/arm/mach-h720x/include/mach/debug-macro.S
@@ -11,8 +11,10 @@
  *
 */
 
-                .equ    io_virt, IO_BASE
-                .equ    io_phys, IO_START
+#include <mach/hardware.h>
+
+                .equ    io_virt, IO_VIRT
+                .equ    io_phys, IO_PHYS
 
                 .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index bcb26f01b26c..8f4fb6d638f7 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -121,8 +121,13 @@ static struct clk uartclk = {
         .rate   = 14745600,
 };
 
+static struct clk dummy_apb_pclk;
+
 static struct clk_lookup lookups[] = {
-        {       /* UART0 */
+        {       /* Bus clock */
+                .con_id         = "apb_pclk",
+                .clk            = &dummy_apb_pclk,
+        }, {    /* UART0 */
                 .dev_id         = "mb:16",
                 .clk            = &uartclk,
         }, {    /* UART1 */
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.c b/arch/arm/mach-kirkwood/tsx1x-common.c
index 7221c20b2afa..f781164e623f 100644
--- a/arch/arm/mach-kirkwood/tsx1x-common.c
+++ b/arch/arm/mach-kirkwood/tsx1x-common.c
@@ -77,7 +77,7 @@ struct spi_board_info __initdata qnap_tsx1x_spi_slave_info[] = {
         },
 };
 
-void qnap_tsx1x_register_flash(void)
+void __init qnap_tsx1x_register_flash(void)
 {
         spi_register_board_info(qnap_tsx1x_spi_slave_info,
                                 ARRAY_SIZE(qnap_tsx1x_spi_slave_info));
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.h b/arch/arm/mach-kirkwood/tsx1x-common.h
index 9a592962a6ea..7fa037361b55 100644
--- a/arch/arm/mach-kirkwood/tsx1x-common.h
+++ b/arch/arm/mach-kirkwood/tsx1x-common.h
@@ -1,7 +1,7 @@
 #ifndef __ARCH_KIRKWOOD_TSX1X_COMMON_H
 #define __ARCH_KIRKWOOD_TSX1X_COMMON_H
 
-extern void qnap_tsx1x_register_flash(void);
+extern void __init qnap_tsx1x_register_flash(void);
 extern void qnap_tsx1x_power_off(void);
 
 #endif
diff --git a/arch/arm/mach-l7200/Makefile b/arch/arm/mach-l7200/Makefile
deleted file mode 100644
index 4bd8ebd70e7b..000000000000
--- a/arch/arm/mach-l7200/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-obj-y                   := core.o
-obj-m                   :=
-obj-n                   :=
-obj-                    :=
-
diff --git a/arch/arm/mach-l7200/Makefile.boot b/arch/arm/mach-l7200/Makefile.boot
deleted file mode 100644
index 6c72ecbe6b64..000000000000
--- a/arch/arm/mach-l7200/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
-   zreladdr-y   := 0xf0008000
-
diff --git a/arch/arm/mach-l7200/core.c b/arch/arm/mach-l7200/core.c
deleted file mode 100644
index 50d23246d4f0..000000000000
--- a/arch/arm/mach-l7200/core.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- *  linux/arch/arm/mm/mm-lusl7200.c
- *
- *  Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- *  Extra MM routines for L7200 architecture
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/device.h>
-
-#include <asm/types.h>
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <asm/page.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-/*
- * IRQ base register
- */
-#define IRQ_BASE        (IO_BASE_2 + 0x1000)
-
-/* 
- * Normal IRQ registers
- */
-#define IRQ_STATUS      (*(volatile unsigned long *) (IRQ_BASE + 0x000))
-#define IRQ_RAWSTATUS   (*(volatile unsigned long *) (IRQ_BASE + 0x004))
-#define IRQ_ENABLE      (*(volatile unsigned long *) (IRQ_BASE + 0x008))
-#define IRQ_ENABLECLEAR (*(volatile unsigned long *) (IRQ_BASE + 0x00c))
-#define IRQ_SOFT        (*(volatile unsigned long *) (IRQ_BASE + 0x010))
-#define IRQ_SOURCESEL   (*(volatile unsigned long *) (IRQ_BASE + 0x018))
-
-/* 
- * Fast IRQ registers
- */
-#define FIQ_STATUS      (*(volatile unsigned long *) (IRQ_BASE + 0x100))
-#define FIQ_RAWSTATUS   (*(volatile unsigned long *) (IRQ_BASE + 0x104))
-#define FIQ_ENABLE      (*(volatile unsigned long *) (IRQ_BASE + 0x108))
-#define FIQ_ENABLECLEAR (*(volatile unsigned long *) (IRQ_BASE + 0x10c))
-#define FIQ_SOFT        (*(volatile unsigned long *) (IRQ_BASE + 0x110))
-#define FIQ_SOURCESEL   (*(volatile unsigned long *) (IRQ_BASE + 0x118))
-
-static void l7200_mask_irq(unsigned int irq)
-{
-        IRQ_ENABLECLEAR = 1 << irq;
-}
-
-static void l7200_unmask_irq(unsigned int irq)
-{
-        IRQ_ENABLE = 1 << irq;
-}
-
-static struct irq_chip l7200_irq_chip = {
-        .ack            = l7200_mask_irq,
-        .mask           = l7200_mask_irq,
-        .unmask         = l7200_unmask_irq
-};
- 
-static void __init l7200_init_irq(void)
-{
-        int irq;
-
-        IRQ_ENABLECLEAR = 0xffffffff;   /* clear all interrupt enables */
-        FIQ_ENABLECLEAR = 0xffffffff;   /* clear all fast interrupt enables */
-
-        for (irq = 0; irq < NR_IRQS; irq++) {
-                set_irq_chip(irq, &l7200_irq_chip);
-                set_irq_flags(irq, IRQF_VALID);
-                set_irq_handler(irq, handle_level_irq);
-        }
-
-        init_FIQ();
-}
-
-static struct map_desc l7200_io_desc[] __initdata = {
-        { IO_BASE,      IO_START,       IO_SIZE,        MT_DEVICE },
-        { IO_BASE_2,    IO_START_2,     IO_SIZE_2,      MT_DEVICE },
-        { AUX_BASE,     AUX_START,      AUX_SIZE,       MT_DEVICE },
-        { FLASH1_BASE,  FLASH1_START,   FLASH1_SIZE,    MT_DEVICE },
-        { FLASH2_BASE,  FLASH2_START,   FLASH2_SIZE,    MT_DEVICE }
-};
-
-static void __init l7200_map_io(void)
-{
-        iotable_init(l7200_io_desc, ARRAY_SIZE(l7200_io_desc));
-}
-
-MACHINE_START(L7200, "LinkUp Systems L7200")
-        /* Maintainer: Steve Hill / Scott McConnell */
-        .phys_io        = 0x80040000,
-        .io_pg_offst    = ((0xd0000000) >> 18) & 0xfffc,
-        .map_io         = l7200_map_io,
-        .init_irq       = l7200_init_irq,
-MACHINE_END
-
diff --git a/arch/arm/mach-l7200/include/mach/aux_reg.h b/arch/arm/mach-l7200/include/mach/aux_reg.h
deleted file mode 100644
index 4671558cdd51..000000000000
--- a/arch/arm/mach-l7200/include/mach/aux_reg.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/aux_reg.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   08-02-2000 SJH     Created file
- */
-#ifndef _ASM_ARCH_AUXREG_H
-#define _ASM_ARCH_AUXREG_H
-
-#include <mach/hardware.h>
-
-#define l7200aux_reg    *((volatile unsigned int *) (AUX_BASE))
-
-/*
- * Auxillary register values
- */
-#define AUX_CLEAR               0x00000000
-#define AUX_DIAG_LED_ON         0x00000002
-#define AUX_RTS_UART1           0x00000004
-#define AUX_DTR_UART1           0x00000008
-#define AUX_KBD_COLUMN_12_HIGH  0x00000010
-#define AUX_KBD_COLUMN_12_OFF   0x00000020
-#define AUX_KBD_COLUMN_13_HIGH  0x00000040
-#define AUX_KBD_COLUMN_13_OFF   0x00000080
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/debug-macro.S b/arch/arm/mach-l7200/include/mach/debug-macro.S
deleted file mode 100644
index b69ed344c7c9..000000000000
--- a/arch/arm/mach-l7200/include/mach/debug-macro.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* arch/arm/mach-l7200/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .equ    io_virt, IO_BASE
-                .equ    io_phys, IO_START
-
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #io_phys           @ physical base address
-                movne   \rx, #io_virt           @ virtual address
-                add     \rx, \rx, #0x00044000   @ UART1
-@               add     \rx, \rx, #0x00045000   @ UART2
-                .endm
-
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0x0]        @ UARTDR
-                .endm
-
-                .macro  waituart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
-                tst     \rd, #1 << 5            @ UARTFLGUTXFF - 1 when full
-                bne     1001b
-                .endm
-
-                .macro  busyuart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
-                tst     \rd, #1 << 3            @ UARTFLGUBUSY - 1 when busy
-                bne     1001b
-                .endm
diff --git a/arch/arm/mach-l7200/include/mach/entry-macro.S b/arch/arm/mach-l7200/include/mach/entry-macro.S
deleted file mode 100644
index 1726d91fc1d3..000000000000
--- a/arch/arm/mach-l7200/include/mach/entry-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for L7200-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <mach/hardware.h>
-
-                .equ    irq_base_addr,  IO_BASE_2
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mov     \irqstat, #irq_base_addr                @ Virt addr IRQ regs
-                add     \irqstat, \irqstat, #0x00001000         @ Status reg
-                ldr     \irqstat, [\irqstat, #0]                @ get interrupts
-                mov     \irqnr, #0
-1001:           tst     \irqstat, #1
-                addeq   \irqnr, \irqnr, #1
-                moveq   \irqstat, \irqstat, lsr #1
-                tsteq   \irqnr, #32
-                beq     1001b
-                teq     \irqnr, #32
-                .endm
-
diff --git a/arch/arm/mach-l7200/include/mach/gp_timers.h b/arch/arm/mach-l7200/include/mach/gp_timers.h
deleted file mode 100644
index 2b7086a26b81..000000000000
--- a/arch/arm/mach-l7200/include/mach/gp_timers.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/gp_timers.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   07-28-2000 SJH     Created file
- *   08-02-2000 SJH     Used structure for registers
- */
-#ifndef _ASM_ARCH_GPTIMERS_H
-#define _ASM_ARCH_GPTIMERS_H
-
-#include <mach/hardware.h>
-
-/*
- * Layout of L7200 general purpose timer registers
- */
-struct GPT_Regs {
-        unsigned int TIMERLOAD;
-        unsigned int TIMERVALUE;
-        unsigned int TIMERCONTROL;
-        unsigned int TIMERCLEAR;
-};
-
-#define GPT_BASE                (IO_BASE_2 + 0x3000)
-#define l7200_timer1_regs       ((volatile struct GPT_Regs *) (GPT_BASE))
-#define l7200_timer2_regs       ((volatile struct GPT_Regs *) (GPT_BASE + 0x20))
-
-/*
- * General register values
- */
-#define GPT_PRESCALE_1          0x00000000
-#define GPT_PRESCALE_16         0x00000004
-#define GPT_PRESCALE_256        0x00000008
-#define GPT_MODE_FREERUN        0x00000000
-#define GPT_MODE_PERIODIC       0x00000040
-#define GPT_ENABLE              0x00000080
-#define GPT_BZTOG               0x00000100
-#define GPT_BZMOD               0x00000200
-#define GPT_LOAD_MASK           0x0000ffff
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/gpio.h b/arch/arm/mach-l7200/include/mach/gpio.h
deleted file mode 100644
index c7b0a5d7b8bb..000000000000
--- a/arch/arm/mach-l7200/include/mach/gpio.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/****************************************************************************/
-/*
- *      arch/arm/mach-l7200/include/mach/gpio.h
- *
- *      Registers and  helper functions for the L7200 Link-Up Systems
- *      GPIO.
- *
- *      (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define GPIO_OFF   0x00005000  /* Offset from IO_START to the GPIO reg's. */
-
-/* IO_START and IO_BASE are defined in hardware.h */
-
-#define GPIO_START (IO_START_2 + GPIO_OFF) /* Physical addr of the GPIO reg. */
-#define GPIO_BASE  (IO_BASE_2  + GPIO_OFF) /* Virtual addr of the GPIO reg. */
-
-/* Offsets from the start of the GPIO for all the registers. */
-#define PADR_OFF     0x000
-#define PADDR_OFF    0x004
-#define PASBSR_OFF   0x008
-#define PAEENR_OFF   0x00c
-#define PAESNR_OFF   0x010
-#define PAESTR_OFF   0x014
-#define PAIMR_OFF    0x018
-#define PAINT_OFF    0x01c
-
-#define PBDR_OFF     0x020
-#define PBDDR_OFF    0x024
-#define PBSBSR_OFF   0x028
-#define PBIMR_OFF    0x038
-#define PBINT_OFF    0x03c
-
-#define PCDR_OFF     0x040
-#define PCDDR_OFF    0x044
-#define PCSBSR_OFF   0x048
-#define PCIMR_OFF    0x058
-#define PCINT_OFF    0x05c
-
-#define PDDR_OFF     0x060
-#define PDDDR_OFF    0x064
-#define PDSBSR_OFF   0x068
-#define PDEENR_OFF   0x06c
-#define PDESNR_OFF   0x070
-#define PDESTR_OFF   0x074
-#define PDIMR_OFF    0x078
-#define PDINT_OFF    0x07c
-
-#define PEDR_OFF     0x080
-#define PEDDR_OFF    0x084
-#define PESBSR_OFF   0x088
-#define PEEENR_OFF   0x08c
-#define PEESNR_OFF   0x090
-#define PEESTR_OFF   0x094
-#define PEIMR_OFF    0x098
-#define PEINT_OFF    0x09c
-
-/* Define the GPIO registers for use by device drivers and the kernel. */
-#define PADR   (*(volatile unsigned long *)(GPIO_BASE+PADR_OFF))
-#define PADDR  (*(volatile unsigned long *)(GPIO_BASE+PADDR_OFF))
-#define PASBSR (*(volatile unsigned long *)(GPIO_BASE+PASBSR_OFF))
-#define PAEENR (*(volatile unsigned long *)(GPIO_BASE+PAEENR_OFF))
-#define PAESNR (*(volatile unsigned long *)(GPIO_BASE+PAESNR_OFF))
-#define PAESTR (*(volatile unsigned long *)(GPIO_BASE+PAESTR_OFF))
-#define PAIMR  (*(volatile unsigned long *)(GPIO_BASE+PAIMR_OFF))
-#define PAINT  (*(volatile unsigned long *)(GPIO_BASE+PAINT_OFF))
-
-#define PBDR   (*(volatile unsigned long *)(GPIO_BASE+PBDR_OFF))
-#define PBDDR  (*(volatile unsigned long *)(GPIO_BASE+PBDDR_OFF))
-#define PBSBSR (*(volatile unsigned long *)(GPIO_BASE+PBSBSR_OFF))
-#define PBIMR  (*(volatile unsigned long *)(GPIO_BASE+PBIMR_OFF))
-#define PBINT  (*(volatile unsigned long *)(GPIO_BASE+PBINT_OFF))
-
-#define PCDR   (*(volatile unsigned long *)(GPIO_BASE+PCDR_OFF))
-#define PCDDR  (*(volatile unsigned long *)(GPIO_BASE+PCDDR_OFF))
-#define PCSBSR (*(volatile unsigned long *)(GPIO_BASE+PCSBSR_OFF))
-#define PCIMR  (*(volatile unsigned long *)(GPIO_BASE+PCIMR_OFF))
-#define PCINT  (*(volatile unsigned long *)(GPIO_BASE+PCINT_OFF))
-
-#define PDDR   (*(volatile unsigned long *)(GPIO_BASE+PDDR_OFF))
-#define PDDDR  (*(volatile unsigned long *)(GPIO_BASE+PDDDR_OFF))
-#define PDSBSR (*(volatile unsigned long *)(GPIO_BASE+PDSBSR_OFF))
-#define PDEENR (*(volatile unsigned long *)(GPIO_BASE+PDEENR_OFF))
-#define PDESNR (*(volatile unsigned long *)(GPIO_BASE+PDESNR_OFF))
-#define PDESTR (*(volatile unsigned long *)(GPIO_BASE+PDESTR_OFF))
-#define PDIMR  (*(volatile unsigned long *)(GPIO_BASE+PDIMR_OFF))
-#define PDINT  (*(volatile unsigned long *)(GPIO_BASE+PDINT_OFF))
-
-#define PEDR   (*(volatile unsigned long *)(GPIO_BASE+PEDR_OFF))
-#define PEDDR  (*(volatile unsigned long *)(GPIO_BASE+PEDDR_OFF))
-#define PESBSR (*(volatile unsigned long *)(GPIO_BASE+PESBSR_OFF))
-#define PEEENR (*(volatile unsigned long *)(GPIO_BASE+PEEENR_OFF))
-#define PEESNR (*(volatile unsigned long *)(GPIO_BASE+PEESNR_OFF))
-#define PEESTR (*(volatile unsigned long *)(GPIO_BASE+PEESTR_OFF))
-#define PEIMR  (*(volatile unsigned long *)(GPIO_BASE+PEIMR_OFF))
-#define PEINT  (*(volatile unsigned long *)(GPIO_BASE+PEINT_OFF))
-
-#define VEE_EN         0x02
-#define BACKLIGHT_EN   0x04
diff --git a/arch/arm/mach-l7200/include/mach/hardware.h b/arch/arm/mach-l7200/include/mach/hardware.h
deleted file mode 100644
index c31909cfc254..000000000000
--- a/arch/arm/mach-l7200/include/mach/hardware.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/hardware.h
- *
- * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * This file contains the hardware definitions for the 
- * LinkUp Systems L7200 SOC development board.
- *
- * Changelog:
- *   02-01-2000  RS     Created L7200 version, derived from rpc code
- *   03-21-2000 SJH     Cleaned up file
- *   04-21-2000  RS     Changed mapping of I/O in virtual space
- *   04-25-2000 SJH     Removed unused symbols and such
- *   05-05-2000 SJH     Complete rewrite
- *   07-31-2000 SJH     Added undocumented debug auxillary port to
- *                      get at last two columns for keyboard driver
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/* Hardware addresses of major areas.
- *  *_START is the physical address
- *  *_SIZE  is the size of the region
- *  *_BASE  is the virtual address
- */
-#define RAM_START               0xf0000000
-#define RAM_SIZE                0x02000000
-#define RAM_BASE                0xc0000000
-
-#define IO_START                0x80000000      /* I/O */
-#define IO_SIZE                 0x01000000
-#define IO_BASE                 0xd0000000
-
-#define IO_START_2              0x90000000      /* I/O */
-#define IO_SIZE_2               0x01000000
-#define IO_BASE_2               0xd1000000
-
-#define AUX_START               0x1a000000      /* AUX PORT */
-#define AUX_SIZE                0x01000000
-#define AUX_BASE                0xd2000000
-
-#define FLASH1_START            0x00000000      /* FLASH BANK 1 */
-#define FLASH1_SIZE             0x01000000
-#define FLASH1_BASE             0xd3000000
-
-#define FLASH2_START            0x10000000      /* FLASH BANK 2 */
-#define FLASH2_SIZE             0x01000000
-#define FLASH2_BASE             0xd4000000
-
-#define ISA_START               0x20000000      /* ISA */
-#define ISA_SIZE                0x20000000
-#define ISA_BASE                0xe0000000
-
-#define PCIO_BASE               IO_BASE
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/io.h b/arch/arm/mach-l7200/include/mach/io.h
deleted file mode 100644
index a770a89fb708..000000000000
--- a/arch/arm/mach-l7200/include/mach/io.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/io.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  03-21-2000  SJH     Created from arch/arm/mach-nexuspci/include/mach/io.h
- *  08-31-2000  SJH     Added in IO functions necessary for new drivers
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * There are not real ISA nor PCI buses, so we fake it.
- */
-#define __io(a)         __typesafe_io(a)
-#define __mem_pci(a)    (a)
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/irqs.h b/arch/arm/mach-l7200/include/mach/irqs.h
deleted file mode 100644
index 7edffd713c5b..000000000000
--- a/arch/arm/mach-l7200/include/mach/irqs.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/irqs.h
- *
- * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   01-02-2000 RS      Create l7200 version
- *   03-28-2000 SJH     Removed unused interrupt
- *   07-28-2000 SJH     Added pseudo-keyboard interrupt
- */
-
-/*
- * NOTE: The second timer (Timer 2) is used as the keyboard
- *       interrupt when the keyboard driver is enabled.
- */
-
-#define NR_IRQS          32
-
-#define IRQ_STWDOG        0   /* Watchdog timer */
-#define IRQ_PROG          1   /* Programmable interrupt */
-#define IRQ_DEBUG_RX      2   /* Comm Rx debug */
-#define IRQ_DEBUG_TX      3   /* Comm Tx debug */
-#define IRQ_GCTC1         4   /* Timer 1 */
-#define IRQ_GCTC2         5   /* Timer 2 / Keyboard */
-#define IRQ_DMA           6   /* DMA controller */
-#define IRQ_CLCD          7   /* Color LCD controller */
-#define IRQ_SM_RX         8   /* Smart card */
-#define IRQ_SM_TX         9   /* Smart cart */
-#define IRQ_SM_RST       10   /* Smart card */
-#define IRQ_SIB          11   /* Serial Interface Bus */
-#define IRQ_MMC          12   /* MultiMediaCard */
-#define IRQ_SSP1         13   /* Synchronous Serial Port 1 */
-#define IRQ_SSP2         14   /* Synchronous Serial Port 1 */
-#define IRQ_SPI          15   /* SPI slave */
-#define IRQ_UART_1       16   /* UART 1 */
-#define IRQ_UART_2       17   /* UART 2 */
-#define IRQ_IRDA         18   /* IRDA */
-#define IRQ_RTC_TICK     19   /* Real Time Clock tick */
-#define IRQ_RTC_ALARM    20   /* Real Time Clock alarm */
-#define IRQ_GPIO         21   /* General Purpose IO */
-#define IRQ_GPIO_DMA     22   /* General Purpose IO, DMA */
-#define IRQ_M2M          23   /* Memory to memory DMA  */
-#define IRQ_RESERVED     24   /* RESERVED, don't use */
-#define IRQ_INTF         25   /* External active low interrupt */
-#define IRQ_INT0         26   /* External active low interrupt */
-#define IRQ_INT1         27   /* External active low interrupt */
-#define IRQ_INT2         28   /* External active low interrupt */
-#define IRQ_UCB1200      29   /* Interrupt generated by UCB1200*/
-#define IRQ_BAT_LO       30   /* Low batery or external power */
-#define IRQ_MEDIA_CHG    31   /* Media change interrupt */
-
-/*
- * This is the offset of the FIQ "IRQ" numbers
- */
-#define FIQ_START       64
diff --git a/arch/arm/mach-l7200/include/mach/memory.h b/arch/arm/mach-l7200/include/mach/memory.h
deleted file mode 100644
index 9fb40ed2f03b..000000000000
--- a/arch/arm/mach-l7200/include/mach/memory.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/memory.h
- *
- * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
- * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *
- * Changelog:
- *  03-13-2000  SJH     Created
- *  04-13-2000  RS      Changed bus macros for new addr
- *  05-03-2000  SJH     Removed bus macros and fixed virt_to_phys macro
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset on the L7200 SDB.
- */
-#define PHYS_OFFSET     UL(0xf0000000)
-
-/*
- * Cache flushing area - ROM
- */
-#define FLUSH_BASE_PHYS         0x40000000
-#define FLUSH_BASE              0xdf000000
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/pmpcon.h b/arch/arm/mach-l7200/include/mach/pmpcon.h
deleted file mode 100644
index 3959871e8361..000000000000
--- a/arch/arm/mach-l7200/include/mach/pmpcon.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/****************************************************************************/
-/*
- *  arch/arm/mach-l7200/include/mach/pmpcon.h
- *
- *   Registers and  helper functions for the L7200 Link-Up Systems
- *   DC/DC converter register.
- *
- *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define PMPCON_OFF 0x00006000  /* Offset from IO_START_2. */
-
-/* IO_START_2 and IO_BASE_2 are defined in hardware.h */
-
-#define PMPCON_START (IO_START_2 + PMPCON_OFF)  /* Physical address of reg. */
-#define PMPCON_BASE  (IO_BASE_2  + PMPCON_OFF)  /* Virtual address of reg. */
-
-
-#define PMPCON (*(volatile unsigned int *)(PMPCON_BASE))
-
-#define PWM2_50CYCLE 0x800
-#define CONTRAST     0x9
-
-#define PWM1H (CONTRAST)
-#define PWM1L (CONTRAST << 4)
-
-#define PMPCON_VALUE  (PWM2_50CYCLE | PWM1L | PWM1H) 
-        
-/* PMPCON = 0x811;   // too light and fuzzy
- * PMPCON = 0x844;   
- * PMPCON = 0x866;   // better color poor depth
- * PMPCON = 0x888;   // Darker but better depth 
- * PMPCON = 0x899;   // Darker even better depth
- * PMPCON = 0x8aa;   // too dark even better depth
- * PMPCON = 0X8cc;   // Way too dark
- */
-
-/* As CONTRAST value increases the greater the depth perception and
- * the darker the colors.
- */
diff --git a/arch/arm/mach-l7200/include/mach/pmu.h b/arch/arm/mach-l7200/include/mach/pmu.h
deleted file mode 100644
index a2da7aedf208..000000000000
--- a/arch/arm/mach-l7200/include/mach/pmu.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/****************************************************************************/
-/*
- *  arch/arm/mach-l7200/include/mach/pmu.h
- *
- *   Registers and  helper functions for the L7200 Link-Up Systems
- *   Power Management Unit (PMU).
- *
- *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define PMU_OFF   0x00050000  /* Offset from IO_START to the PMU registers. */
-
-/* IO_START and IO_BASE are defined in hardware.h */
-
-#define PMU_START (IO_START + PMU_OFF)  /* Physical addr. of the PMU reg. */
-#define PMU_BASE  (IO_BASE  + PMU_OFF)  /* Virtual addr. of the PMU reg. */
-
-
-/* Define the PMU registers for use by device drivers and the kernel. */
-
-typedef struct {
-     unsigned int CURRENT;  /* Current configuration register */
-     unsigned int NEXT;     /* Next configuration register */
-     unsigned int reserved;
-     unsigned int RUN;      /* Run configuration register */
-     unsigned int COMM;     /* Configuration command register */
-     unsigned int SDRAM;    /* SDRAM configuration bypass register */
-} pmu_interface;
-
-#define PMU ((volatile pmu_interface *)(PMU_BASE))
-
-
-/* Macro's for reading the common register fields. */
-
-#define GET_TRANSOP(reg)  ((reg >> 25) & 0x03) /* Bits 26-25 */
-#define GET_OSCEN(reg)    ((reg >> 16) & 0x01)
-#define GET_OSCMUX(reg)   ((reg >> 15) & 0x01)
-#define GET_PLLMUL(reg)   ((reg >>  9) & 0x3f) /* Bits 14-9 */
-#define GET_PLLEN(reg)    ((reg >>  8) & 0x01)
-#define GET_PLLMUX(reg)   ((reg >>  7) & 0x01)
-#define GET_BCLK_DIV(reg) ((reg >>  3) & 0x03) /* Bits 4-3 */
-#define GET_SDRB_SEL(reg) ((reg >>  2) & 0x01)
-#define GET_SDRF_SEL(reg) ((reg >>  1) & 0x01)
-#define GET_FASTBUS(reg)  (reg & 0x1)
-
-/* CFG_NEXT register */
-
-#define CFG_NEXT_CLOCKRECOVERY ((PMU->NEXT >> 18) & 0x7f)   /* Bits 24-18 */
-#define CFG_NEXT_INTRET        ((PMU->NEXT >> 17) & 0x01)
-#define CFG_NEXT_SDR_STOP      ((PMU->NEXT >>  6) & 0x01)
-#define CFG_NEXT_SYSCLKEN      ((PMU->NEXT >>  5) & 0x01)
-
-/* Useful field values that can be used to construct the
- * CFG_NEXT and CFG_RUN registers.
- */
-
-#define TRANSOP_NOP      0<<25  /* NOCHANGE_NOSTALL */
-#define NOCHANGE_STALL   1<<25
-#define CHANGE_NOSTALL   2<<25
-#define CHANGE_STALL     3<<25
-
-#define INTRET           1<<17
-#define OSCEN            1<<16
-#define OSCMUX           1<<15
-
-/* PLL frequencies */
-
-#define PLLMUL_0         0<<9         /*  3.6864 MHz */
-#define PLLMUL_1         1<<9         /*  ?????? MHz */
-#define PLLMUL_5         5<<9         /*  18.432 MHz */
-#define PLLMUL_10       10<<9         /*  36.864 MHz */
-#define PLLMUL_18       18<<9         /*  ?????? MHz */
-#define PLLMUL_20       20<<9         /*  73.728 MHz */
-#define PLLMUL_32       32<<9         /*  ?????? MHz */
-#define PLLMUL_35       35<<9         /* 129.024 MHz */
-#define PLLMUL_36       36<<9         /*  ?????? MHz */
-#define PLLMUL_39       39<<9         /*  ?????? MHz */
-#define PLLMUL_40       40<<9         /* 147.456 MHz */
-
-/* Clock recovery times */
-
-#define CRCLOCK_1        1<<18
-#define CRCLOCK_2        2<<18
-#define CRCLOCK_4        4<<18
-#define CRCLOCK_8        8<<18
-#define CRCLOCK_16      16<<18
-#define CRCLOCK_32      32<<18
-#define CRCLOCK_63      63<<18
-#define CRCLOCK_127    127<<18
-
-#define PLLEN            1<<8
-#define PLLMUX           1<<7
-#define SDR_STOP         1<<6
-#define SYSCLKEN         1<<5
-
-#define BCLK_DIV_4       2<<3
-#define BCLK_DIV_2       1<<3
-#define BCLK_DIV_1       0<<3
-
-#define SDRB_SEL         1<<2
-#define SDRF_SEL         1<<1
-#define FASTBUS          1<<0
-
-
-/* CFG_SDRAM */
-
-#define SDRREFFQ         1<<0  /* Only if SDRSTOPRQ is not set. */
-#define SDRREFACK        1<<1  /* Read-only */
-#define SDRSTOPRQ        1<<2  /* Only if SDRREFFQ is not set. */
-#define SDRSTOPACK       1<<3  /* Read-only */
-#define PICEN            1<<4  /* Enable Co-procesor */
-#define PICTEST          1<<5
-
-#define GET_SDRREFFQ    ((PMU->SDRAM >> 0) & 0x01)
-#define GET_SDRREFACK   ((PMU->SDRAM >> 1) & 0x01) /* Read-only */
-#define GET_SDRSTOPRQ   ((PMU->SDRAM >> 2) & 0x01)
-#define GET_SDRSTOPACK  ((PMU->SDRAM >> 3) & 0x01) /* Read-only */
-#define GET_PICEN       ((PMU->SDRAM >> 4) & 0x01)
-#define GET_PICTEST     ((PMU->SDRAM >> 5) & 0x01)
diff --git a/arch/arm/mach-l7200/include/mach/serial.h b/arch/arm/mach-l7200/include/mach/serial.h
deleted file mode 100644
index adc05e5f8378..000000000000
--- a/arch/arm/mach-l7200/include/mach/serial.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/serial.h
- *
- * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  03-20-2000  SJH     Created
- *  03-26-2000  SJH     Added flags for serial ports
- *  03-27-2000  SJH     Corrected BASE_BAUD value
- *  04-14-2000  RS      Made register addr dependent on IO_BASE
- *  05-03-2000  SJH     Complete rewrite
- *  05-09-2000  SJH     Stripped out architecture specific serial stuff
- *                      and placed it in a separate file
- *  07-28-2000  SJH     Moved base baud rate variable
- */
-#ifndef __ASM_ARCH_SERIAL_H
-#define __ASM_ARCH_SERIAL_H
-
-/*
- * This assumes you have a 3.6864 MHz clock for your UART.
- */
-#define BASE_BAUD       3686400
-
-/*
- * Standard COM flags
- */
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
-
-#define STD_SERIAL_PORT_DEFNS           \
-        /* MAGIC UART CLK   PORT       IRQ     FLAGS */                 \
-        { 0, BASE_BAUD, UART1_BASE, IRQ_UART_1, STD_COM_FLAGS },  /* ttyLU0 */ \
-        { 0, BASE_BAUD, UART2_BASE, IRQ_UART_2, STD_COM_FLAGS },  /* ttyLU1 */ \
-
-#define EXTRA_SERIAL_PORT_DEFNS
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/serial_l7200.h b/arch/arm/mach-l7200/include/mach/serial_l7200.h
deleted file mode 100644
index 645f1c5e568d..000000000000
--- a/arch/arm/mach-l7200/include/mach/serial_l7200.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/serial_l7200.h
- *
- * Copyright (c) 2000 Steven Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  05-09-2000  SJH     Created
- */
-#ifndef __ASM_ARCH_SERIAL_L7200_H
-#define __ASM_ARCH_SERIAL_L7200_H
-
-#include <mach/memory.h>
-
-/*
- * This assumes you have a 3.6864 MHz clock for your UART.
- */
-#define BASE_BAUD 3686400
-
-/*
- * UART base register addresses
- */
-#define UART1_BASE      (IO_BASE + 0x00044000)
-#define UART2_BASE      (IO_BASE + 0x00045000)
-
-/*
- * UART register offsets
- */
-#define UARTDR                  0x00    /* Tx/Rx data */
-#define RXSTAT                  0x04    /* Rx status */
-#define H_UBRLCR                0x08    /* mode register high */
-#define M_UBRLCR                0x0C    /* mode reg mid (MSB of baud)*/
-#define L_UBRLCR                0x10    /* mode reg low (LSB of baud)*/
-#define UARTCON                 0x14    /* control register */
-#define UARTFLG                 0x18    /* flag register */
-#define UARTINTSTAT             0x1C    /* FIFO IRQ status register */
-#define UARTINTMASK             0x20    /* FIFO IRQ mask register */
-
-/*
- * UART baud rate register values
- */
-#define BR_110                  0x827
-#define BR_1200                 0x06e
-#define BR_2400                 0x05f
-#define BR_4800                 0x02f
-#define BR_9600                 0x017
-#define BR_14400                0x00f
-#define BR_19200                0x00b
-#define BR_38400                0x005
-#define BR_57600                0x003
-#define BR_76800                0x002
-#define BR_115200               0x001
-
-/*
- * Receiver status register (RXSTAT) mask values
- */
-#define RXSTAT_NO_ERR           0x00    /* No error */
-#define RXSTAT_FRM_ERR          0x01    /* Framing error */
-#define RXSTAT_PAR_ERR          0x02    /* Parity error */
-#define RXSTAT_OVR_ERR          0x04    /* Overrun error */
-
-/*
- * High byte of UART bit rate and line control register (H_UBRLCR) values
- */
-#define UBRLCR_BRK              0x01    /* generate break on tx */
-#define UBRLCR_PEN              0x02    /* enable parity */
-#define UBRLCR_PDIS             0x00    /* disable parity */
-#define UBRLCR_EVEN             0x04    /* 1= even parity,0 = odd parity */
-#define UBRLCR_STP2             0x08    /* transmit 2 stop bits */
-#define UBRLCR_FIFO             0x10    /* enable FIFO */
-#define UBRLCR_LEN5             0x60    /* word length5 */
-#define UBRLCR_LEN6             0x40    /* word length6 */
-#define UBRLCR_LEN7             0x20    /* word length7 */
-#define UBRLCR_LEN8             0x00    /* word length8 */
-
-/*
- * UART control register (UARTCON) values
- */
-#define UARTCON_UARTEN          0x01    /* Enable UART */
-#define UARTCON_DMAONERR        0x08    /* Mask RxDmaRq when errors occur */
-
-/*
- * UART flag register (UARTFLG) mask values
- */
-#define UARTFLG_UTXFF           0x20    /* Transmit FIFO full */
-#define UARTFLG_URXFE           0x10    /* Receiver FIFO empty */
-#define UARTFLG_UBUSY           0x08    /* Transmitter busy */
-#define UARTFLG_DCD             0x04    /* Data carrier detect */
-#define UARTFLG_DSR             0x02    /* Data set ready */
-#define UARTFLG_CTS             0x01    /* Clear to send */
-
-/*
- * UART interrupt status/clear registers (UARTINTSTAT/CLR) values
- */
-#define UART_TXINT              0x01    /* TX interrupt */
-#define UART_RXINT              0x02    /* RX interrupt */
-#define UART_RXERRINT           0x04    /* RX error interrupt */
-#define UART_MSINT              0x08    /* Modem Status interrupt */
-#define UART_UDINT              0x10    /* UART Disabled interrupt */
-#define UART_ALLIRQS            0x1f    /* All interrupts */
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/sib.h b/arch/arm/mach-l7200/include/mach/sib.h
deleted file mode 100644
index 965728712cf3..000000000000
--- a/arch/arm/mach-l7200/include/mach/sib.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/****************************************************************************/
-/*
- *  arch/arm/mach-l7200/include/mach/sib.h
- *
- *  Registers and helper functions for the Serial Interface Bus.
- *
- *  (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define SIB_OFF   0x00040000  /* Offset from IO_START to the SIB reg's. */
-
-/* IO_START and IO_BASE are defined in hardware.h */
-
-#define SIB_START (IO_START + SIB_OFF) /* Physical addr of the SIB reg. */
-#define SIB_BASE  (IO_BASE  + SIB_OFF) /* Virtual addr of the SIB reg.  */
-
-/* Offsets from the start of the SIB for all the registers. */
-
-/* Define the SIB registers for use by device drivers and the kernel. */
-
-typedef struct
-{
-     unsigned int MCCR;    /* SIB Control Register           Offset: 0x00 */
-     unsigned int RES1;    /* Reserved                       Offset: 0x04 */
-     unsigned int MCDR0;   /* SIB Data Register 0            Offset: 0x08 */
-     unsigned int MCDR1;   /* SIB Data Register 1            Offset: 0x0c */
-     unsigned int MCDR2;   /* SIB Data Register 2 (UCB1x00)  Offset: 0x10 */
-     unsigned int RES2;    /* Reserved                       Offset: 0x14 */
-     unsigned int MCSR;    /* SIB Status Register            Offset: 0x18 */
-} SIB_Interface;
-
-#define SIB ((volatile SIB_Interface *) (SIB_BASE))
-
-/* MCCR */
-
-#define INTERNAL_FREQ   9216000  /* Hertz */
-#define AUDIO_FREQ         5000  /* Hertz */
-#define TELECOM_FREQ       5000  /* Hertz */
-
-#define AUDIO_DIVIDE    (INTERNAL_FREQ / (32 * AUDIO_FREQ))
-#define TELECOM_DIVIDE  (INTERNAL_FREQ / (32 * TELECOM_FREQ))
-
-#define MCCR_ASD57      AUDIO_DIVIDE
-#define MCCR_TSD57      (TELECOM_DIVIDE << 8)
-#define MCCR_MCE        (1 << 16)             /* SIB enable */
-#define MCCR_ECS        (1 << 17)             /* External Clock Select */
-#define MCCR_ADM        (1 << 18)             /* A/D Data Sampling */
-#define MCCR_PMC        (1 << 26)             /* PIN Multiplexer Control */
-
-
-#define GET_ASD ((SIB->MCCR >>  0) & 0x3f) /* Audio Sample Rate Div. */
-#define GET_TSD ((SIB->MCCR >>  8) & 0x3f) /* Telcom Sample Rate Div. */
-#define GET_MCE ((SIB->MCCR >> 16) & 0x01) /* SIB Enable */
-#define GET_ECS ((SIB->MCCR >> 17) & 0x01) /* External Clock Select */
-#define GET_ADM ((SIB->MCCR >> 18) & 0x01) /* A/D Data Sampling Mode */
-#define GET_TTM ((SIB->MCCR >> 19) & 0x01) /* Telco Trans. FIFO I mask */ 
-#define GET_TRM ((SIB->MCCR >> 20) & 0x01) /* Telco Recv. FIFO I mask */
-#define GET_ATM ((SIB->MCCR >> 21) & 0x01) /* Audio Trans. FIFO I mask */ 
-#define GET_ARM ((SIB->MCCR >> 22) & 0x01) /* Audio Recv. FIFO I mask */
-#define GET_LBM ((SIB->MCCR >> 23) & 0x01) /* Loop Back Mode */
-#define GET_ECP ((SIB->MCCR >> 24) & 0x03) /* Extern. Clck Prescale sel */
-#define GET_PMC ((SIB->MCCR >> 26) & 0x01) /* PIN Multiplexer Control */
-#define GET_ERI ((SIB->MCCR >> 27) & 0x01) /* External Read Interrupt */
-#define GET_EWI ((SIB->MCCR >> 28) & 0x01) /* External Write Interrupt */
-
-/* MCDR0 */
-
-#define AUDIO_RECV     ((SIB->MCDR0 >> 4) & 0xfff)
-#define AUDIO_WRITE(v) ((SIB->MCDR0 = (v & 0xfff) << 4))
-
-/* MCDR1 */
-
-#define TELECOM_RECV     ((SIB->MCDR1 >> 2) & 032fff)
-#define TELECOM_WRITE(v) ((SIB->MCDR1 = (v & 0x3fff) << 2))
-
-
-/* MCSR */
-
-#define MCSR_ATU (1 << 4)  /* Audio Transmit FIFO Underrun */
-#define MCSR_ARO (1 << 5)  /* Audio Receive  FIFO Underrun */
-#define MCSR_TTU (1 << 6)  /* TELECOM Transmit FIFO Underrun */
-#define MCSR_TRO (1 << 7)  /* TELECOM Receive  FIFO Underrun */
-
-#define MCSR_CLEAR_UNDERUN_BITS (MCSR_ATU | MCSR_ARO | MCSR_TTU | MCSR_TRO)
-
-
-#define GET_ATS ((SIB->MCSR >>  0) & 0x01) /* Audio Transmit FIFO Service Req*/
-#define GET_ARS ((SIB->MCSR >>  1) & 0x01) /* Audio Recv FIFO Service Request*/
-#define GET_TTS ((SIB->MCSR >>  2) & 0x01) /* TELECOM Transmit FIFO  Flag */
-#define GET_TRS ((SIB->MCSR >>  3) & 0x01) /* TELECOM Recv FIFO Service Req. */
-#define GET_ATU ((SIB->MCSR >>  4) & 0x01) /* Audio Transmit FIFO Underrun */
-#define GET_ARO ((SIB->MCSR >>  5) & 0x01) /* Audio Receive  FIFO Underrun */
-#define GET_TTU ((SIB->MCSR >>  6) & 0x01) /* TELECOM Transmit FIFO Underrun */
-#define GET_TRO ((SIB->MCSR >>  7) & 0x01) /* TELECOM Receive  FIFO Underrun */
-#define GET_ANF ((SIB->MCSR >>  8) & 0x01) /* Audio Transmit FIFO not full */
-#define GET_ANE ((SIB->MCSR >>  9) & 0x01) /* Audio Receive FIFO not empty */
-#define GET_TNF ((SIB->MCSR >> 10) & 0x01) /* Telecom Transmit FIFO not full */
-#define GET_TNE ((SIB->MCSR >> 11) & 0x01) /* Telecom Receive FIFO not empty */
-#define GET_CWC ((SIB->MCSR >> 12) & 0x01) /* Codec Write Complete */
-#define GET_CRC ((SIB->MCSR >> 13) & 0x01) /* Codec Read Complete */
-#define GET_ACE ((SIB->MCSR >> 14) & 0x01) /* Audio Codec Enabled */
-#define GET_TCE ((SIB->MCSR >> 15) & 0x01) /* Telecom Codec Enabled */
-
-/* MCDR2 */
-
-#define MCDR2_rW               (1 << 16)
-
-#define WRITE_MCDR2(reg, data) (SIB->MCDR2 =((reg<<17)|MCDR2_rW|(data&0xffff)))
-#define MCDR2_WRITE_COMPLETE   GET_CWC
-
-#define INITIATE_MCDR2_READ(reg) (SIB->MCDR2 = (reg << 17))
-#define MCDR2_READ_COMPLETE      GET_CRC
-#define MCDR2_READ               (SIB->MCDR2 & 0xffff)
diff --git a/arch/arm/mach-l7200/include/mach/sys-clock.h b/arch/arm/mach-l7200/include/mach/sys-clock.h
deleted file mode 100644
index e9729a35751d..000000000000
--- a/arch/arm/mach-l7200/include/mach/sys-clock.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/****************************************************************************/
-/*
- *  arch/arm/mach-l7200/include/mach/sys-clock.h
- *
- *   Registers and  helper functions for the L7200 Link-Up Systems
- *   System clocks.
- *
- *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define SYS_CLOCK_OFF   0x00050030  /* Offset from IO_START. */
-
-/* IO_START and IO_BASE are defined in hardware.h */
-
-#define SYS_CLOCK_START (IO_START + SYS_CLOCK_OFF)  /* Physical address */
-#define SYS_CLOCK_BASE  (IO_BASE  + SYS_CLOCK_OFF)  /* Virtual address  */
-
-/* Define the interface to the SYS_CLOCK */
-
-typedef struct
-{
-     unsigned int ENABLE;
-     unsigned int ESYNC;
-     unsigned int SELECT;
-} sys_clock_interface;
-
-#define SYS_CLOCK   ((volatile sys_clock_interface *)(SYS_CLOCK_BASE))
-
-//#define CLOCK_EN    (*(volatile unsigned long *)(PMU_BASE+CLOCK_EN_OFF))
-//#define CLOCK_ESYNC (*(volatile unsigned long *)(PMU_BASE+CLOCK_ESYNC_OFF))
-//#define CLOCK_SEL   (*(volatile unsigned long *)(PMU_BASE+CLOCK_SEL_OFF))
-
-/* SYS_CLOCK -> ENABLE */
-
-#define SYN_EN          1<<0
-#define B18M_EN         1<<1
-#define CLK3M6_EN       1<<2
-#define BUART_EN        1<<3
-#define CLK18MU_EN      1<<4
-#define FIR_EN          1<<5
-#define MIRN_EN         1<<6
-#define UARTM_EN        1<<7
-#define SIBADC_EN       1<<8
-#define ALTD_EN         1<<9
-#define CLCLK_EN        1<<10
-
-/* SYS_CLOCK -> SELECT */
-
-#define CLK18M_DIV      1<<0
-#define MIR_SEL         1<<1
-#define SSP_SEL         1<<4
-#define MM_DIV          1<<5
-#define MM_SEL          1<<6
-#define ADC_SEL_2       0<<7
-#define ADC_SEL_4       1<<7
-#define ADC_SEL_8       3<<7
-#define ADC_SEL_16      7<<7
-#define ADC_SEL_32      0x0f<<7
-#define ADC_SEL_64      0x1f<<7
-#define ADC_SEL_128     0x3f<<7
-#define ALTD_SEL        1<<13
diff --git a/arch/arm/mach-l7200/include/mach/system.h b/arch/arm/mach-l7200/include/mach/system.h
deleted file mode 100644
index e0dd3b6ae4aa..000000000000
--- a/arch/arm/mach-l7200/include/mach/system.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/system.h
- *
- * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog
- *  03-21-2000  SJH     Created
- *  04-26-2000  SJH     Fixed functions
- *  05-03-2000  SJH     Removed usage of obsolete 'iomd.h'
- *  05-31-2000  SJH     Properly implemented 'arch_idle'
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <mach/hardware.h>
-
-static inline void arch_idle(void)
-{
-        *(unsigned long *)(IO_BASE + 0x50004) = 1;      /* idle mode */
-}
-
-static inline void arch_reset(char mode, const char *cmd)
-{
-        if (mode == 's') {
-                cpu_reset(0);
-        }
-}
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/time.h b/arch/arm/mach-l7200/include/mach/time.h
deleted file mode 100644
index 061771c2c2bd..000000000000
--- a/arch/arm/mach-l7200/include/mach/time.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/time.h
- *
- * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   01-02-2000 RS      Created l7200 version, derived from rpc code
- *   05-03-2000 SJH     Complete rewrite
- */
-#ifndef _ASM_ARCH_TIME_H
-#define _ASM_ARCH_TIME_H
-
-#include <mach/irqs.h>
-
-/*
- * RTC base register address
- */
-#define RTC_BASE        (IO_BASE_2 + 0x2000)
-
-/*
- * RTC registers
- */
-#define RTC_RTCDR       (*(volatile unsigned char *) (RTC_BASE + 0x000))
-#define RTC_RTCMR       (*(volatile unsigned char *) (RTC_BASE + 0x004))
-#define RTC_RTCS        (*(volatile unsigned char *) (RTC_BASE + 0x008))
-#define RTC_RTCC        (*(volatile unsigned char *) (RTC_BASE + 0x008))
-#define RTC_RTCDV       (*(volatile unsigned char *) (RTC_BASE + 0x00c))
-#define RTC_RTCCR       (*(volatile unsigned char *) (RTC_BASE + 0x010))
-
-/*
- * RTCCR register values
- */
-#define RTC_RATE_32     0x00      /* 32 Hz tick */
-#define RTC_RATE_64     0x10      /* 64 Hz tick */
-#define RTC_RATE_128    0x20      /* 128 Hz tick */
-#define RTC_RATE_256    0x30      /* 256 Hz tick */
-#define RTC_EN_ALARM    0x01      /* Enable alarm */
-#define RTC_EN_TIC      0x04      /* Enable counter */
-#define RTC_EN_STWDOG   0x08      /* Enable watchdog */
-
-/*
- * Handler for RTC timer interrupt
- */
-static irqreturn_t
-timer_interrupt(int irq, void *dev_id)
-{
-        struct pt_regs *regs = get_irq_regs();
-        do_timer(1);
-#ifndef CONFIG_SMP
-        update_process_times(user_mode(regs));
-#endif
-        do_profile(regs);
-        RTC_RTCC = 0;                           /* Clear interrupt */
-
-        return IRQ_HANDLED;
-}
-
-/*
- * Set up RTC timer interrupt, and return the current time in seconds.
- */
-void __init time_init(void)
-{
-        RTC_RTCC = 0;                           /* Clear interrupt */
-
-        timer_irq.handler = timer_interrupt;
-
-        setup_irq(IRQ_RTC_TICK, &timer_irq);
-
-        RTC_RTCCR = RTC_RATE_128 | RTC_EN_TIC;  /* Set rate and enable timer */
-}
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/timex.h b/arch/arm/mach-l7200/include/mach/timex.h
deleted file mode 100644
index ffc96a63b5a2..000000000000
--- a/arch/arm/mach-l7200/include/mach/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/timex.h
- *
- * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * 04-21-2000  RS Created file
- * 05-03-2000 SJH Tick rate was wrong
- *
- */
-
-/*
- * On the ARM720T, clock ticks are set to 128 Hz.
- *
- * NOTE: The actual RTC value is set in 'time.h' which
- *       must be changed when choosing a different tick
- *       rate. The value of HZ in 'param.h' must also
- *       be changed to match below.
- */
-#define CLOCK_TICK_RATE         128
diff --git a/arch/arm/mach-l7200/include/mach/uncompress.h b/arch/arm/mach-l7200/include/mach/uncompress.h
deleted file mode 100644
index 591c962bb315..000000000000
--- a/arch/arm/mach-l7200/include/mach/uncompress.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/uncompress.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  05-01-2000  SJH     Created
- *  05-13-2000  SJH     Filled in function bodies
- *  07-26-2000  SJH     Removed hard coded baud rate
- */
-
-#include <mach/hardware.h>
-
-#define IO_UART  IO_START + 0x00044000
-
-#define __raw_writeb(v,p)       (*(volatile unsigned char *)(p) = (v))
-#define __raw_readb(p)          (*(volatile unsigned char *)(p))
-
-static inline void putc(int c)
-{
-        while(__raw_readb(IO_UART + 0x18) & 0x20 ||
-              __raw_readb(IO_UART + 0x18) & 0x08)
-                barrier();
-
-        __raw_writeb(c, IO_UART + 0x00);
-}
-
-static inline void flush(void)
-{
-}
-
-static __inline__ void arch_decomp_setup(void)
-{
-        __raw_writeb(0x00, IO_UART + 0x08);     /* Set HSB */
-        __raw_writeb(0x00, IO_UART + 0x20);     /* Disable IRQs */
-        __raw_writeb(0x01, IO_UART + 0x14);     /* Enable UART */
-}
-
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-l7200/include/mach/vmalloc.h b/arch/arm/mach-l7200/include/mach/vmalloc.h
deleted file mode 100644
index 85f0abbf15f1..000000000000
--- a/arch/arm/mach-l7200/include/mach/vmalloc.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/vmalloc.h
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/arch/arm/mach-nomadik/clock.c b/arch/arm/mach-nomadik/clock.c
index f035f4185274..89f793adf776 100644
--- a/arch/arm/mach-nomadik/clock.c
+++ b/arch/arm/mach-nomadik/clock.c
@@ -53,6 +53,10 @@ static struct clk clk_default;
         }
 
 static struct clk_lookup lookups[] = {
+        {
+                .con_id         = "apb_pclk",
+                .clk            = &clk_default,
+        },
         CLK(&clk_24, "mtu0"),
         CLK(&clk_24, "mtu1"),
         CLK(&clk_48, "uart0"),
diff --git a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
index 0859336a8e6d..5c934bdb7158 100644
--- a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
@@ -8,6 +8,7 @@
  * the Free Software Foundation.
  */
 #include <mach/hardware.h>
+#include <asm/memory.h>
 
 #include <mach/regs-board-a9m9750dev.h>
 
diff --git a/arch/arm/mach-ns9xxx/include/mach/uncompress.h b/arch/arm/mach-ns9xxx/include/mach/uncompress.h
index 1b12d324b087..770a68c46e81 100644
--- a/arch/arm/mach-ns9xxx/include/mach/uncompress.h
+++ b/arch/arm/mach-ns9xxx/include/mach/uncompress.h
@@ -20,50 +20,49 @@ static void putc_dummy(char c, void __iomem *base)
         /* nothing */
 }
 
+static int timeout;
+
 static void putc_ns9360(char c, void __iomem *base)
 {
-        static int t = 0x10000;
         do {
-                if (t)
-                        --t;
+                if (timeout)
+                        --timeout;
 
                 if (__raw_readl(base + 8) & (1 << 3)) {
                         __raw_writeb(c, base + 16);
-                        t = 0x10000;
+                        timeout = 0x10000;
                         break;
                 }
-        } while (t);
+        } while (timeout);
 }
 
 static void putc_a9m9750dev(char c, void __iomem *base)
 {
-        static int t = 0x10000;
         do {
-                if (t)
-                        --t;
+                if (timeout)
+                        --timeout;
 
                 if (__raw_readb(base + 5) & (1 << 5)) {
                         __raw_writeb(c, base);
-                        t = 0x10000;
+                        timeout = 0x10000;
                         break;
                 }
-        } while (t);
+        } while (timeout);
 
 }
 
 static void putc_ns921x(char c, void __iomem *base)
 {
-        static int t = 0x10000;
         do {
-                if (t)
-                        --t;
+                if (timeout)
+                        --timeout;
 
                 if (!(__raw_readl(base) & (1 << 11))) {
                         __raw_writeb(c, base + 0x0028);
-                        t = 0x10000;
+                        timeout = 0x10000;
                         break;
                 }
-        } while (t);
+        } while (timeout);
 }
 
 #define MSCS __REG(0xA0900184)
@@ -89,6 +88,7 @@ static void putc_ns921x(char c, void __iomem *base)
 
 static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base)
 {
+        timeout = 0x10000;
         if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) {
                 /* ns9360 or ns9750 */
                 if (NS9360_UART_ENABLED(NS9360_UARTA)) {
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index abdf321c2d41..03483920ed6e 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -175,6 +175,10 @@ static void __init rx51_add_gpio_keys(void)
 #endif /* CONFIG_KEYBOARD_GPIO || CONFIG_KEYBOARD_GPIO_MODULE */
 
 static int board_keymap[] = {
+        /*
+         * Note that KEY(x, 8, KEY_XXX) entries represent "entrire row
+         * connected to the ground" matrix state.
+         */
         KEY(0, 0, KEY_Q),
         KEY(0, 1, KEY_O),
         KEY(0, 2, KEY_P),
@@ -182,6 +186,7 @@ static int board_keymap[] = {
         KEY(0, 4, KEY_BACKSPACE),
         KEY(0, 6, KEY_A),
         KEY(0, 7, KEY_S),
+
         KEY(1, 0, KEY_W),
         KEY(1, 1, KEY_D),
         KEY(1, 2, KEY_F),
@@ -190,6 +195,7 @@ static int board_keymap[] = {
         KEY(1, 5, KEY_J),
         KEY(1, 6, KEY_K),
         KEY(1, 7, KEY_L),
+
         KEY(2, 0, KEY_E),
         KEY(2, 1, KEY_DOT),
         KEY(2, 2, KEY_UP),
@@ -197,6 +203,8 @@ static int board_keymap[] = {
         KEY(2, 5, KEY_Z),
         KEY(2, 6, KEY_X),
         KEY(2, 7, KEY_C),
+        KEY(2, 8, KEY_F9),
+
         KEY(3, 0, KEY_R),
         KEY(3, 1, KEY_V),
         KEY(3, 2, KEY_B),
@@ -205,20 +213,23 @@ static int board_keymap[] = {
         KEY(3, 5, KEY_SPACE),
         KEY(3, 6, KEY_SPACE),
         KEY(3, 7, KEY_LEFT),
+
         KEY(4, 0, KEY_T),
         KEY(4, 1, KEY_DOWN),
         KEY(4, 2, KEY_RIGHT),
         KEY(4, 4, KEY_LEFTCTRL),
         KEY(4, 5, KEY_RIGHTALT),
         KEY(4, 6, KEY_LEFTSHIFT),
+        KEY(4, 8, KEY_F10),
+
         KEY(5, 0, KEY_Y),
+        KEY(5, 8, KEY_F11),
+
         KEY(6, 0, KEY_U),
+
         KEY(7, 0, KEY_I),
         KEY(7, 1, KEY_F7),
         KEY(7, 2, KEY_F8),
-        KEY(0xff, 2, KEY_F9),
-        KEY(0xff, 4, KEY_F10),
-        KEY(0xff, 5, KEY_F11),
 };
 
 static struct matrix_keymap_data board_map_data = {
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 41b155acfca7..d33744117ce2 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3166,6 +3166,10 @@ static struct clk uart4_ick_am35xx = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk dummy_apb_pclk = {
+        .name           = "apb_pclk",
+        .ops            = &clkops_null,
+};
 
 /*
  * clkdev
@@ -3173,6 +3177,7 @@ static struct clk uart4_ick_am35xx = {
 
 /* XXX At some point we should rename this file to clock3xxx_data.c */
 static struct omap_clk omap3xxx_clks[] = {
+        CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index 45c23fd6df31..40b6ac2de876 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -26,6 +26,7 @@
 #include <mach/colibri.h>
 #include <mach/ohci.h>
 #include <mach/pxafb.h>
+#include <mach/audio.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -145,7 +146,7 @@ static void __init colibri_pxa300_init_lcd(void)
 static inline void colibri_pxa300_init_lcd(void) {}
 #endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */
 
-#if defined(SND_AC97_CODEC) || defined(SND_AC97_CODEC_MODULE)
+#if defined(CONFIG_SND_AC97_CODEC) || defined(CONFIG_SND_AC97_CODEC_MODULE)
 static mfp_cfg_t colibri_pxa310_ac97_pin_config[] __initdata = {
         GPIO24_AC97_SYSCLK,
         GPIO23_AC97_nACRESET,
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 95234fb4fcf8..461ba4080155 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -446,7 +446,7 @@ static struct platform_device corgiled_device = {
 static struct pxamci_platform_data corgi_mci_platform_data = {
         .detect_delay_ms        = 250,
         .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
-        .gpio_card_detect       = -1,
+        .gpio_card_detect       = CORGI_GPIO_nSD_DETECT,
         .gpio_card_ro           = CORGI_GPIO_nSD_WP,
         .gpio_power             = CORGI_GPIO_SD_PWR,
 };
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 9e4d9816726a..268a9bc6be8a 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -256,13 +256,9 @@ static void init_sdram_rows(void)
 
 static u32 mdrefr_dri(unsigned int freq)
 {
-        u32 dri = 0;
+        u32 interval = freq * SDRAM_TREF / sdram_rows;
 
-        if (cpu_is_pxa25x())
-                dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
-        if (cpu_is_pxa27x())
-                dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
-        return dri;
+        return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32;
 }
 
 /* find a valid frequency point */
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 0af36177ff08..c059dac02b61 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -41,10 +41,10 @@ void pxa27x_clear_otgph(void)
 EXPORT_SYMBOL(pxa27x_clear_otgph);
 
 static unsigned long ac97_reset_config[] = {
-        GPIO95_AC97_nRESET,
-        GPIO95_GPIO,
-        GPIO113_AC97_nRESET,
         GPIO113_GPIO,
+        GPIO113_AC97_nRESET,
+        GPIO95_GPIO,
+        GPIO95_AC97_nRESET,
 };
 
 void pxa27x_assert_ac97reset(int reset_gpio, int on)
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 1195e07c5483..a54fbda77e45 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -231,6 +231,21 @@ static unsigned int realview_mmc_status(struct device *dev)
         struct amba_device *adev = container_of(dev, struct amba_device, dev);
         u32 mask;
 
+        if (machine_is_realview_pb1176()) {
+                static bool inserted = false;
+
+                /*
+                 * The PB1176 does not have the status register,
+                 * assume it is inserted at startup, then invert
+                 * for each call so card insertion/removal will
+                 * be detected anyway. This will not be called if
+                 * GPIO on PL061 is active, which is the proper
+                 * way to do this on the PB1176.
+                 */
+                inserted = !inserted;
+                return inserted ? 0 : 1;
+        }
+
         if (adev->res.start == REALVIEW_MMCI0_BASE)
                 mask = 1;
         else
@@ -299,8 +314,13 @@ static struct clk ref24_clk = {
         .rate   = 24000000,
 };
 
+static struct clk dummy_apb_pclk;
+
 static struct clk_lookup lookups[] = {
-        {       /* UART0 */
+        {       /* Bus clock */
+                .con_id         = "apb_pclk",
+                .clk            = &dummy_apb_pclk,
+        }, {    /* UART0 */
                 .dev_id         = "dev:uart0",
                 .clk            = &ref24_clk,
         }, {    /* UART1 */
@@ -312,6 +332,12 @@ static struct clk_lookup lookups[] = {
         }, {    /* UART3 */
                 .dev_id         = "fpga:uart3",
                 .clk            = &ref24_clk,
+        }, {    /* UART3 is on the dev chip in PB1176 */
+                .dev_id         = "dev:uart3",
+                .clk            = &ref24_clk,
+        }, {    /* UART4 only exists in PB1176 */
+                .dev_id         = "fpga:uart4",
+                .clk            = &ref24_clk,
         }, {    /* KMI0 */
                 .dev_id         = "fpga:kmi0",
                 .clk            = &ref24_clk,
@@ -321,12 +347,15 @@ static struct clk_lookup lookups[] = {
         }, {    /* MMC0 */
                 .dev_id         = "fpga:mmc0",
                 .clk            = &ref24_clk,
-        }, {    /* EB:CLCD */
+        }, {    /* CLCD is in the PB1176 and EB DevChip */
                 .dev_id         = "dev:clcd",
                 .clk            = &oscvco_clk,
         }, {    /* PB:CLCD */
                 .dev_id         = "issp:clcd",
                 .clk            = &oscvco_clk,
+        }, {    /* SSP */
+                .dev_id         = "dev:ssp0",
+                .clk            = &ref24_clk,
         }
 };
 
@@ -341,7 +370,7 @@ static int __init clk_init(void)
 
         return 0;
 }
-arch_initcall(clk_init);
+core_initcall(clk_init);
 
 /*
  * CLCD support.
diff --git a/arch/arm/mach-realview/include/mach/board-pb1176.h b/arch/arm/mach-realview/include/mach/board-pb1176.h
index 2f5ccb298858..002ab5d8c11c 100644
--- a/arch/arm/mach-realview/include/mach/board-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/board-pb1176.h
@@ -26,6 +26,7 @@
 /*
  * Peripheral addresses
  */
+#define REALVIEW_PB1176_UART4_BASE              0x10009000 /* UART 4 */
 #define REALVIEW_PB1176_SCTL_BASE               0x10100000 /* System controller */
 #define REALVIEW_PB1176_SMC_BASE                0x10111000 /* SMC */
 #define REALVIEW_PB1176_DMC_BASE                0x10109000 /* DMC configuration */
diff --git a/arch/arm/mach-realview/include/mach/irqs-pb1176.h b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
index 830055bb8628..5c3c625e3e04 100644
--- a/arch/arm/mach-realview/include/mach/irqs-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
@@ -40,6 +40,7 @@
 #define IRQ_DC1176_L2CC         (IRQ_DC1176_GIC_START + 13)
 #define IRQ_DC1176_RTC          (IRQ_DC1176_GIC_START + 14)
 #define IRQ_DC1176_CLCD         (IRQ_DC1176_GIC_START + 15)     /* CLCD controller */
+#define IRQ_DC1176_SSP          (IRQ_DC1176_GIC_START + 17)     /* SSP port */
 #define IRQ_DC1176_UART0        (IRQ_DC1176_GIC_START + 18)     /* UART 0 on development chip */
 #define IRQ_DC1176_UART1        (IRQ_DC1176_GIC_START + 19)     /* UART 1 on development chip */
 #define IRQ_DC1176_UART2        (IRQ_DC1176_GIC_START + 20)     /* UART 2 on development chip */
@@ -73,7 +74,6 @@
 #define IRQ_PB1176_RTC          (IRQ_PB1176_GIC_START + 25)     /* Real Time Clock */
 
 #define IRQ_PB1176_GPIO0        -1
-#define IRQ_PB1176_SSP          -1
 #define IRQ_PB1176_SCTL         -1
 
 #define NR_GIC_PB1176           2
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 4425018fab82..991c1f8390e2 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -25,6 +25,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -129,6 +130,12 @@ static struct pl061_platform_data gpio2_plat_data = {
         .irq_base       = -1,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 0,
+        .num_chipselect = 1,
+};
+
 /*
  * RealView EB AMBA devices
  */
@@ -213,7 +220,7 @@ AMBA_DEVICE(sci0,  "dev:sci0",  SCI,      NULL);
 AMBA_DEVICE(uart0, "dev:uart0", EB_UART0, NULL);
 AMBA_DEVICE(uart1, "dev:uart1", EB_UART1, NULL);
 AMBA_DEVICE(uart2, "dev:uart2", EB_UART2, NULL);
-AMBA_DEVICE(ssp0,  "dev:ssp0",  EB_SSP,   NULL);
+AMBA_DEVICE(ssp0,  "dev:ssp0",  EB_SSP,   &ssp0_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
         &dmac_device,
@@ -324,6 +331,26 @@ static struct platform_device pmu_device = {
         .resource               = pmu_resources,
 };
 
+static struct resource char_lcd_resources[] = {
+        {
+                .start = REALVIEW_CHAR_LCD_BASE,
+                .end   = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1),
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_EB_CHARLCD,
+                .end    = IRQ_EB_CHARLCD,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device char_lcd_device = {
+        .name           =       "arm-charlcd",
+        .id             =       -1,
+        .num_resources  =       ARRAY_SIZE(char_lcd_resources),
+        .resource       =       char_lcd_resources,
+};
+
 static void __init gic_init_irq(void)
 {
         if (core_tile_eb11mp() || core_tile_a9mp()) {
@@ -442,6 +469,7 @@ static void __init realview_eb_init(void)
 
         realview_flash_register(&realview_eb_flash_resource, 1);
         platform_device_register(&realview_i2c_device);
+        platform_device_register(&char_lcd_device);
         eth_device_register();
         realview_usb_register(realview_eb_isp1761_resources);
 
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 099a1f125cf8..d2be12eb829e 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -25,6 +25,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -123,6 +124,12 @@ static struct pl061_platform_data gpio2_plat_data = {
         .irq_base       = -1,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 0,
+        .num_chipselect = 1,
+};
+
 /*
  * RealView PB1176 AMBA devices
  */
@@ -144,8 +151,6 @@ static struct pl061_platform_data gpio2_plat_data = {
 #define MPMC_DMA        { 0, 0 }
 #define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ }
 #define PB1176_CLCD_DMA { 0, 0 }
-#define DMAC_IRQ        { IRQ_PB1176_DMAC, NO_IRQ }
-#define DMAC_DMA        { 0, 0 }
 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 #define SCTL_DMA        { 0, 0 }
 #define PB1176_WATCHDOG_IRQ     { IRQ_DC1176_WATCHDOG, NO_IRQ }
@@ -166,7 +171,9 @@ static struct pl061_platform_data gpio2_plat_data = {
 #define PB1176_UART2_DMA        { 11, 10 }
 #define PB1176_UART3_IRQ        { IRQ_DC1176_UART3, NO_IRQ }
 #define PB1176_UART3_DMA        { 0x86, 0x87 }
-#define PB1176_SSP_IRQ          { IRQ_PB1176_SSP, NO_IRQ }
+#define PB1176_UART4_IRQ        { IRQ_PB1176_UART4, NO_IRQ }
+#define PB1176_UART4_DMA        { 0, 0 }
+#define PB1176_SSP_IRQ          { IRQ_DC1176_SSP, NO_IRQ }
 #define PB1176_SSP_DMA          { 9, 8 }
 
 /* FPGA Primecells */
@@ -174,7 +181,7 @@ AMBA_DEVICE(aaci,	"fpga:aaci",	AACI,		NULL);
 AMBA_DEVICE(mmc0,       "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
 AMBA_DEVICE(kmi0,       "fpga:kmi0",    KMI0,           NULL);
 AMBA_DEVICE(kmi1,       "fpga:kmi1",    KMI1,           NULL);
-AMBA_DEVICE(uart3,      "fpga:uart3",   PB1176_UART3,   NULL);
+AMBA_DEVICE(uart4,      "fpga:uart4",   PB1176_UART4,   NULL);
 
 /* DevChip Primecells */
 AMBA_DEVICE(smc,        "dev:smc",      PB1176_SMC,     NULL);
@@ -188,18 +195,16 @@ AMBA_DEVICE(sci0,	"dev:sci0",	SCI,		NULL);
 AMBA_DEVICE(uart0,      "dev:uart0",    PB1176_UART0,   NULL);
 AMBA_DEVICE(uart1,      "dev:uart1",    PB1176_UART1,   NULL);
 AMBA_DEVICE(uart2,      "dev:uart2",    PB1176_UART2,   NULL);
-AMBA_DEVICE(ssp0,       "dev:ssp0",     PB1176_SSP,     NULL);
-
-/* Primecells on the NEC ISSP chip */
-AMBA_DEVICE(clcd,       "issp:clcd",    PB1176_CLCD,    &clcd_plat_data);
-//AMBA_DEVICE(dmac,     "issp:dmac",    PB1176_DMAC,    NULL);
+AMBA_DEVICE(uart3,      "dev:uart3",    PB1176_UART3,   NULL);
+AMBA_DEVICE(ssp0,       "dev:ssp0",     PB1176_SSP,     &ssp0_plat_data);
+AMBA_DEVICE(clcd,       "dev:clcd",     PB1176_CLCD,    &clcd_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
-//      &dmac_device,
         &uart0_device,
         &uart1_device,
         &uart2_device,
         &uart3_device,
+        &uart4_device,
         &smc_device,
         &clcd_device,
         &sctl_device,
@@ -276,6 +281,26 @@ static struct platform_device pmu_device = {
         .resource               = &pmu_resource,
 };
 
+static struct resource char_lcd_resources[] = {
+        {
+                .start = REALVIEW_CHAR_LCD_BASE,
+                .end   = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1),
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_PB1176_CHARLCD,
+                .end    = IRQ_PB1176_CHARLCD,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device char_lcd_device = {
+        .name           =       "arm-charlcd",
+        .id             =       -1,
+        .num_resources  =       ARRAY_SIZE(char_lcd_resources),
+        .resource       =       char_lcd_resources,
+};
+
 static void __init gic_init_irq(void)
 {
         /* ARM1176 DevChip GIC, primary */
@@ -338,6 +363,7 @@ static void __init realview_pb1176_init(void)
         platform_device_register(&realview_i2c_device);
         realview_usb_register(realview_pb1176_isp1761_resources);
         platform_device_register(&pmu_device);
+        platform_device_register(&char_lcd_device);
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 0e07a5ccb75f..d591bc00b86e 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -25,6 +25,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -124,6 +125,12 @@ static struct pl061_platform_data gpio2_plat_data = {
         .irq_base       = -1,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 0,
+        .num_chipselect = 1,
+};
+
 /*
  * RealView PB11MPCore AMBA devices
  */
@@ -190,7 +197,7 @@ AMBA_DEVICE(sci0,	"dev:sci0",	SCI,		NULL);
 AMBA_DEVICE(uart0,      "dev:uart0",    PB11MP_UART0,   NULL);
 AMBA_DEVICE(uart1,      "dev:uart1",    PB11MP_UART1,   NULL);
 AMBA_DEVICE(uart2,      "dev:uart2",    PB11MP_UART2,   NULL);
-AMBA_DEVICE(ssp0,       "dev:ssp0",     PB11MP_SSP,     NULL);
+AMBA_DEVICE(ssp0,       "dev:ssp0",     PB11MP_SSP,     &ssp0_plat_data);
 
 /* Primecells on the NEC ISSP chip */
 AMBA_DEVICE(clcd,       "issp:clcd",    PB11MP_CLCD,    &clcd_plat_data);
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index ac2f06f1ca50..6c37621217bc 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -25,6 +25,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 
 #include <asm/irq.h>
@@ -114,6 +115,12 @@ static struct pl061_platform_data gpio2_plat_data = {
         .irq_base       = -1,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 0,
+        .num_chipselect = 1,
+};
+
 /*
  * RealView PBA8Core AMBA devices
  */
@@ -180,7 +187,7 @@ AMBA_DEVICE(sci0,	"dev:sci0",	SCI,		NULL);
 AMBA_DEVICE(uart0,      "dev:uart0",    PBA8_UART0,     NULL);
 AMBA_DEVICE(uart1,      "dev:uart1",    PBA8_UART1,     NULL);
 AMBA_DEVICE(uart2,      "dev:uart2",    PBA8_UART2,     NULL);
-AMBA_DEVICE(ssp0,       "dev:ssp0",     PBA8_SSP,       NULL);
+AMBA_DEVICE(ssp0,       "dev:ssp0",     PBA8_SSP,       &ssp0_plat_data);
 
 /* Primecells on the NEC ISSP chip */
 AMBA_DEVICE(clcd,       "issp:clcd",    PBA8_CLCD,      &clcd_plat_data);
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 08fd683adc4c..9428eff0b116 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -24,6 +24,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 
 #include <asm/irq.h>
@@ -136,6 +137,12 @@ static struct pl061_platform_data gpio2_plat_data = {
         .irq_base       = -1,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 0,
+        .num_chipselect = 1,
+};
+
 /*
  * RealView PBXCore AMBA devices
  */
@@ -202,7 +209,7 @@ AMBA_DEVICE(sci0,	"dev:sci0",	SCI,		NULL);
 AMBA_DEVICE(uart0,      "dev:uart0",    PBX_UART0,      NULL);
 AMBA_DEVICE(uart1,      "dev:uart1",    PBX_UART1,      NULL);
 AMBA_DEVICE(uart2,      "dev:uart2",    PBX_UART2,      NULL);
-AMBA_DEVICE(ssp0,       "dev:ssp0",     PBX_SSP,        NULL);
+AMBA_DEVICE(ssp0,       "dev:ssp0",     PBX_SSP,        &ssp0_plat_data);
 
 /* Primecells on the NEC ISSP chip */
 AMBA_DEVICE(clcd,       "issp:clcd",    PBX_CLCD,       &clcd_plat_data);
diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S
index 50f071c5bf4d..5ea24d4d1ba6 100644
--- a/arch/arm/mach-shark/include/mach/debug-macro.S
+++ b/arch/arm/mach-shark/include/mach/debug-macro.S
@@ -20,6 +20,9 @@
                 strb    \rd, [\rx]
                 .endm
 
+                .macro waituart,rd,rx
+                .endm
+
                 .macro  busyuart,rd,rx
                 mov     \rd, #0
 1001:           add     \rd, \rd, #1
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index f2b88c5fe142..4c704b4e8b34 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -70,6 +70,18 @@ endmenu
 
 menu "Timer and clock configuration"
 
+config SHMOBILE_TIMER_HZ
+        int "Kernel HZ (jiffies per second)"
+        range 32 1024
+        default "128"
+        help
+          Allows the configuration of the timer frequency. It is customary
+          to have the timer interrupt run at 1000 Hz or 100 Hz, but in the
+          case of low timer frequencies other values may be more suitable.
+          SH-Mobile systems using a 32768 Hz RCLK for clock events may want
+          to select a HZ value such as 128 that can evenly divide RCLK.
+          A HZ value that does not divide evenly may cause timer drift.
+
 config SH_TIMER_CMT
         bool "CMT timer driver"
         default y
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index 5179b72e1ee3..132256bb8c81 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -2,7 +2,6 @@
 #define __ASM_MACH_IRQS_H
 
 #define NR_IRQS         512
-#define NR_IRQS_LEGACY  8
 
 #define evt2irq(evt)            (((evt) >> 5) - 16)
 #define irq2evt(irq)            (((irq) + 16) << 5)
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 39f6ccf22294..18febf92f20a 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -341,8 +341,11 @@ static struct clk gpio_clk = {
         .recalc = &follow_parent,
 };
 
+static struct clk dummy_apb_pclk;
+
 /* array of all spear 3xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
+        { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
         /* root clks */
         { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
         { .con_id = "osc_24m_clk",      .clk = &osc_24m_clk},
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index 13e27c769685..36ff056b7321 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -428,8 +428,11 @@ static struct clk gpio2_clk = {
         .recalc = &follow_parent,
 };
 
+static struct clk dummy_apb_pclk;
+
 /* array of all spear 6xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
+        { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
         /* root clks */
         { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
         { .con_id = "osc_30m_clk",      .clk = &osc_30m_clk},
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
index 5af71d5ba665..5d12d547789e 100644
--- a/arch/arm/mach-u300/clock.c
+++ b/arch/arm/mach-u300/clock.c
@@ -1212,6 +1212,8 @@ static struct clk ppm_clk = {
 };
 #endif
 
+static struct clk dummy_apb_pclk;
+
 #define DEF_LOOKUP(devid, clkref)               \
         {                                       \
         .dev_id = devid,                        \
@@ -1223,6 +1225,10 @@ static struct clk ppm_clk = {
  * look up through clockdevice.
  */
 static struct clk_lookup lookups[] = {
+        {
+                .con_id = "apb_pclk",
+                .clk = &dummy_apb_pclk,
+        },
         /* Connected directly to the AMBA bus */
         DEF_LOOKUP("amba",      &amba_clk),
         DEF_LOOKUP("cpu",       &cpu_clk),
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index bb8d7b771817..0e8fd135a57d 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -13,19 +13,42 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl022.h>
 #include <linux/spi/spi.h>
+#include <linux/mfd/ab8500.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include <plat/pincfg.h>
 #include <plat/i2c.h>
 
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
 
+#include "pins-db8500.h"
+
+static pin_cfg_t mop500_pins[] = {
+        /* SSP0 */
+        GPIO143_SSP0_CLK,
+        GPIO144_SSP0_FRM,
+        GPIO145_SSP0_RXD,
+        GPIO146_SSP0_TXD,
+
+        /* I2C */
+        GPIO147_I2C0_SCL,
+        GPIO148_I2C0_SDA,
+        GPIO16_I2C1_SCL,
+        GPIO17_I2C1_SDA,
+        GPIO10_I2C2_SDA,
+        GPIO11_I2C2_SCL,
+        GPIO229_I2C3_SDA,
+        GPIO230_I2C3_SCL,
+};
+
 static void ab4500_spi_cs_control(u32 command)
 {
         /* set the FRM signal, which is CS  - TODO */
@@ -48,15 +71,20 @@ struct pl022_config_chip ab4500_chip_info = {
         .cs_control = ab4500_spi_cs_control,
 };
 
+static struct ab8500_platform_data ab8500_platdata = {
+        .irq_base       = MOP500_AB8500_IRQ_BASE,
+};
+
 static struct spi_board_info u8500_spi_devices[] = {
         {
                 .modalias = "ab8500",
                 .controller_data = &ab4500_chip_info,
+                .platform_data = &ab8500_platdata,
                 .max_speed_hz = 12000000,
                 .bus_num = 0,
                 .chip_select = 0,
                 .mode = SPI_MODE_0,
-                .irq = IRQ_AB4500,
+                .irq = IRQ_DB8500_AB8500,
         },
 };
 
@@ -118,6 +146,10 @@ static void __init u8500_init_machine(void)
 {
         int i;
 
+        u8500_init_devices();
+
+        nmk_config_pins(mop500_pins, ARRAY_SIZE(mop500_pins));
+
         u8500_i2c0_device.dev.platform_data = &u8500_i2c0_data;
         ux500_i2c1_device.dev.platform_data = &u8500_i2c1_data;
         ux500_i2c2_device.dev.platform_data = &u8500_i2c2_data;
@@ -133,8 +165,6 @@ static void __init u8500_init_machine(void)
 
         spi_register_board_info(u8500_spi_devices,
                         ARRAY_SIZE(u8500_spi_devices));
-
-        u8500_init_devices();
 }
 
 MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 0a1318fc8e2b..d8ab7f184fe4 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -453,7 +453,11 @@ static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
 static DEFINE_PRCC_CLK(7, wdg_ed,       1, -1, NULL);
 static DEFINE_PRCC_CLK(7, cfgreg_ed,    0, -1, NULL);
 
+static struct clk clk_dummy_apb_pclk;
+
 static struct clk_lookup u8500_common_clks[] = {
+        CLK(dummy_apb_pclk, NULL,       "apb_pclk"),
+
         /* Peripheral Cluster #1 */
         CLK(gpio0,      "gpio.0",       NULL),
         CLK(gpio0,      "gpio.1",       NULL),
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 822903421943..654fca944e65 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -65,7 +65,7 @@ struct amba_device u8500_ssp0_device = {
                 .end   = U8500_SSP0_BASE + SZ_4K - 1,
                 .flags = IORESOURCE_MEM,
         },
-        .irq = {IRQ_SSP0, NO_IRQ },
+        .irq = {IRQ_DB8500_SSP0, NO_IRQ },
         /* ST-Ericsson modified id */
         .periphid = SSP_PER_ID,
 };
@@ -77,8 +77,8 @@ static struct resource u8500_i2c0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ_I2C0,
-                .end    = IRQ_I2C0,
+                .start  = IRQ_DB8500_I2C0,
+                .end    = IRQ_DB8500_I2C0,
                 .flags  = IORESOURCE_IRQ,
         }
 };
@@ -97,8 +97,8 @@ static struct resource u8500_i2c4_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ_I2C4,
-                .end    = IRQ_I2C4,
+                .start  = IRQ_DB8500_I2C4,
+                .end    = IRQ_DB8500_I2C4,
                 .flags  = IORESOURCE_IRQ,
         }
 };
@@ -130,8 +130,8 @@ static struct resource dma40_resources[] = {
                 .name = "lcla",
         },
         [3] = {
-                .start = IRQ_DMA,
-                .end = IRQ_DMA,
+                .start = IRQ_DB8500_DMA,
+                .end   = IRQ_DB8500_DMA,
                 .flags = IORESOURCE_IRQ}
 };
 
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
new file mode 100644
index 000000000000..cca4f705601e
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __MACH_IRQS_BOARD_MOP500_H
+#define __MACH_IRQS_BOARD_MOP500_H
+
+#define AB8500_NR_IRQS                  104
+
+#define MOP500_AB8500_IRQ_BASE          IRQ_BOARD_START
+#define MOP500_AB8500_IRQ_END           (MOP500_AB8500_IRQ_BASE \
+                                         + AB8500_NR_IRQS)
+#define MOP500_IRQ_END                  MOP500_AB8500_IRQ_END
+
+#if MOP500_IRQ_END > IRQ_BOARD_END
+#undef IRQ_BOARD_END
+#define IRQ_BOARD_END   MOP500_IRQ_END
+#endif
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
new file mode 100644
index 000000000000..6fbfe5e2065a
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __MACH_IRQS_DB5500_H
+#define __MACH_IRQS_DB5500_H
+
+#define IRQ_DB5500_MTU0                 (IRQ_SHPI_START + 4)
+#define IRQ_DB5500_SPI2                 (IRQ_SHPI_START + 6)
+#define IRQ_DB5500_PMU0                 (IRQ_SHPI_START + 7)
+#define IRQ_DB5500_SPI0                 (IRQ_SHPI_START + 8)
+#define IRQ_DB5500_RTT                  (IRQ_SHPI_START + 9)
+#define IRQ_DB5500_PKA                  (IRQ_SHPI_START + 10)
+#define IRQ_DB5500_UART0                (IRQ_SHPI_START + 11)
+#define IRQ_DB5500_I2C3                 (IRQ_SHPI_START + 12)
+#define IRQ_DB5500_L2CC                 (IRQ_SHPI_START + 13)
+#define IRQ_DB5500_MSP0                 (IRQ_SHPI_START + 14)
+#define IRQ_DB5500_CRYP1                (IRQ_SHPI_START + 15)
+#define IRQ_DB5500_PMU1                 (IRQ_SHPI_START + 16)
+#define IRQ_DB5500_MTU1                 (IRQ_SHPI_START + 17)
+#define IRQ_DB5500_RTC                  (IRQ_SHPI_START + 18)
+#define IRQ_DB5500_UART1                (IRQ_SHPI_START + 19)
+#define IRQ_DB5500_USB_WAKEUP           (IRQ_SHPI_START + 20)
+#define IRQ_DB5500_I2C0                 (IRQ_SHPI_START + 21)
+#define IRQ_DB5500_I2C1                 (IRQ_SHPI_START + 22)
+#define IRQ_DB5500_USBOTG               (IRQ_SHPI_START + 23)
+#define IRQ_DB5500_DMA_SECURE           (IRQ_SHPI_START + 24)
+#define IRQ_DB5500_DMA                  (IRQ_SHPI_START + 25)
+#define IRQ_DB5500_UART2                (IRQ_SHPI_START + 26)
+#define IRQ_DB5500_ICN_PMU1             (IRQ_SHPI_START + 27)
+#define IRQ_DB5500_ICN_PMU2             (IRQ_SHPI_START + 28)
+#define IRQ_DB5500_UART3                (IRQ_SHPI_START + 29)
+#define IRQ_DB5500_SPI3                 (IRQ_SHPI_START + 30)
+#define IRQ_DB5500_SDMMC4               (IRQ_SHPI_START + 31)
+#define IRQ_DB5500_IRRC                 (IRQ_SHPI_START + 33)
+#define IRQ_DB5500_IRDA_FT              (IRQ_SHPI_START + 34)
+#define IRQ_DB5500_IRDA_SD              (IRQ_SHPI_START + 35)
+#define IRQ_DB5500_IRDA_FI              (IRQ_SHPI_START + 36)
+#define IRQ_DB5500_IRDA_FD              (IRQ_SHPI_START + 37)
+#define IRQ_DB5500_FSMC_CODEREADY       (IRQ_SHPI_START + 38)
+#define IRQ_DB5500_FSMC_NANDWAIT        (IRQ_SHPI_START + 39)
+#define IRQ_DB5500_AB5500               (IRQ_SHPI_START + 40)
+#define IRQ_DB5500_SDMMC2               (IRQ_SHPI_START + 41)
+#define IRQ_DB5500_SIA                  (IRQ_SHPI_START + 42)
+#define IRQ_DB5500_SIA2                 (IRQ_SHPI_START + 43)
+#define IRQ_DB5500_HVA                  (IRQ_SHPI_START + 44)
+#define IRQ_DB5500_HVA2                 (IRQ_SHPI_START + 45)
+#define IRQ_DB5500_PRCMU0               (IRQ_SHPI_START + 46)
+#define IRQ_DB5500_PRCMU1               (IRQ_SHPI_START + 47)
+#define IRQ_DB5500_DISP                 (IRQ_SHPI_START + 48)
+#define IRQ_DB5500_SDMMC1               (IRQ_SHPI_START + 50)
+#define IRQ_DB5500_MSP1                 (IRQ_SHPI_START + 52)
+#define IRQ_DB5500_KBD                  (IRQ_SHPI_START + 53)
+#define IRQ_DB5500_I2C2                 (IRQ_SHPI_START + 55)
+#define IRQ_DB5500_B2R2                 (IRQ_SHPI_START + 56)
+#define IRQ_DB5500_CRYP0                (IRQ_SHPI_START + 57)
+#define IRQ_DB5500_SDMMC3               (IRQ_SHPI_START + 59)
+#define IRQ_DB5500_SDMMC0               (IRQ_SHPI_START + 60)
+#define IRQ_DB5500_HSEM                 (IRQ_SHPI_START + 61)
+#define IRQ_DB5500_SBAG                 (IRQ_SHPI_START + 63)
+#define IRQ_DB5500_SPI1                 (IRQ_SHPI_START + 96)
+#define IRQ_DB5500_MSP2                 (IRQ_SHPI_START + 98)
+#define IRQ_DB5500_SRPTIMER             (IRQ_SHPI_START + 101)
+#define IRQ_DB5500_CTI0                 (IRQ_SHPI_START + 108)
+#define IRQ_DB5500_CTI1                 (IRQ_SHPI_START + 109)
+#define IRQ_DB5500_ICN_ERR              (IRQ_SHPI_START + 110)
+#define IRQ_DB5500_MALI_PPMMU           (IRQ_SHPI_START + 112)
+#define IRQ_DB5500_MALI_PP              (IRQ_SHPI_START + 113)
+#define IRQ_DB5500_MALI_GPMMU           (IRQ_SHPI_START + 114)
+#define IRQ_DB5500_MALI_GP              (IRQ_SHPI_START + 115)
+#define IRQ_DB5500_MALI                 (IRQ_SHPI_START + 116)
+#define IRQ_DB5500_PRCMU_SEM            (IRQ_SHPI_START + 118)
+#define IRQ_DB5500_GPIO0                (IRQ_SHPI_START + 119)
+#define IRQ_DB5500_GPIO1                (IRQ_SHPI_START + 120)
+#define IRQ_DB5500_GPIO2                (IRQ_SHPI_START + 121)
+#define IRQ_DB5500_GPIO3                (IRQ_SHPI_START + 122)
+#define IRQ_DB5500_GPIO4                (IRQ_SHPI_START + 123)
+#define IRQ_DB5500_GPIO5                (IRQ_SHPI_START + 124)
+#define IRQ_DB5500_GPIO6                (IRQ_SHPI_START + 125)
+#define IRQ_DB5500_GPIO7                (IRQ_SHPI_START + 126)
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
new file mode 100644
index 000000000000..8b5d9f0a1633
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __MACH_IRQS_DB8500_H
+#define __MACH_IRQS_DB8500_H
+
+#define IRQ_DB8500_MTU0                 (IRQ_SHPI_START + 4)
+#define IRQ_DB8500_SPI2                 (IRQ_SHPI_START + 6)
+#define IRQ_DB8500_PMU                  (IRQ_SHPI_START + 7)
+#define IRQ_DB8500_SPI0                 (IRQ_SHPI_START + 8)
+#define IRQ_DB8500_RTT                  (IRQ_SHPI_START + 9)
+#define IRQ_DB8500_PKA                  (IRQ_SHPI_START + 10)
+#define IRQ_DB8500_UART0                (IRQ_SHPI_START + 11)
+#define IRQ_DB8500_I2C3                 (IRQ_SHPI_START + 12)
+#define IRQ_DB8500_L2CC                 (IRQ_SHPI_START + 13)
+#define IRQ_DB8500_SSP0                 (IRQ_SHPI_START + 14)
+#define IRQ_DB8500_CRYP1                (IRQ_SHPI_START + 15)
+#define IRQ_DB8500_MSP1_RX              (IRQ_SHPI_START + 16)
+#define IRQ_DB8500_MTU1                 (IRQ_SHPI_START + 17)
+#define IRQ_DB8500_RTC                  (IRQ_SHPI_START + 18)
+#define IRQ_DB8500_UART1                (IRQ_SHPI_START + 19)
+#define IRQ_DB8500_USB_WAKEUP           (IRQ_SHPI_START + 20)
+#define IRQ_DB8500_I2C0                 (IRQ_SHPI_START + 21)
+#define IRQ_DB8500_I2C1                 (IRQ_SHPI_START + 22)
+#define IRQ_DB8500_USBOTG               (IRQ_SHPI_START + 23)
+#define IRQ_DB8500_DMA_SECURE           (IRQ_SHPI_START + 24)
+#define IRQ_DB8500_DMA                  (IRQ_SHPI_START + 25)
+#define IRQ_DB8500_UART2                (IRQ_SHPI_START + 26)
+#define IRQ_DB8500_ICN_PMU1             (IRQ_SHPI_START + 27)
+#define IRQ_DB8500_ICN_PMU2             (IRQ_SHPI_START + 28)
+#define IRQ_DB8500_HSIR_EXCEP           (IRQ_SHPI_START + 29)
+#define IRQ_DB8500_MSP0                 (IRQ_SHPI_START + 31)
+#define IRQ_DB8500_HSIR_CH0_OVRRUN      (IRQ_SHPI_START + 32)
+#define IRQ_DB8500_HSIR_CH1_OVRRUN      (IRQ_SHPI_START + 33)
+#define IRQ_DB8500_HSIR_CH2_OVRRUN      (IRQ_SHPI_START + 34)
+#define IRQ_DB8500_HSIR_CH3_OVRRUN      (IRQ_SHPI_START + 35)
+#define IRQ_DB8500_HSIR_CH4_OVRRUN      (IRQ_SHPI_START + 36)
+#define IRQ_DB8500_HSIR_CH5_OVRRUN      (IRQ_SHPI_START + 37)
+#define IRQ_DB8500_HSIR_CH6_OVRRUN      (IRQ_SHPI_START + 38)
+#define IRQ_DB8500_HSIR_CH7_OVRRUN      (IRQ_SHPI_START + 39)
+#define IRQ_DB8500_AB8500               (IRQ_SHPI_START + 40)
+#define IRQ_DB8500_SDMMC2               (IRQ_SHPI_START + 41)
+#define IRQ_DB8500_SIA                  (IRQ_SHPI_START + 42)
+#define IRQ_DB8500_SIA2                 (IRQ_SHPI_START + 43)
+#define IRQ_DB8500_SVA                  (IRQ_SHPI_START + 44)
+#define IRQ_DB8500_SVA2                 (IRQ_SHPI_START + 45)
+#define IRQ_DB8500_PRCMU0               (IRQ_SHPI_START + 46)
+#define IRQ_DB8500_PRCMU1               (IRQ_SHPI_START + 47)
+#define IRQ_DB8500_DISP                 (IRQ_SHPI_START + 48)
+#define IRQ_DB8500_SPI3                 (IRQ_SHPI_START + 49)
+#define IRQ_DB8500_SDMMC1               (IRQ_SHPI_START + 50)
+#define IRQ_DB8500_I2C4                 (IRQ_SHPI_START + 51)
+#define IRQ_DB8500_SSP1                 (IRQ_SHPI_START + 52)
+#define IRQ_DB8500_SKE                  (IRQ_SHPI_START + 53)
+#define IRQ_DB8500_KB                   (IRQ_SHPI_START + 54)
+#define IRQ_DB8500_I2C2                 (IRQ_SHPI_START + 55)
+#define IRQ_DB8500_B2R2                 (IRQ_SHPI_START + 56)
+#define IRQ_DB8500_CRYP0                (IRQ_SHPI_START + 57)
+#define IRQ_DB8500_SDMMC3               (IRQ_SHPI_START + 59)
+#define IRQ_DB8500_SDMMC0               (IRQ_SHPI_START + 60)
+#define IRQ_DB8500_HSEM                 (IRQ_SHPI_START + 61)
+#define IRQ_DB8500_MSP1                 (IRQ_SHPI_START + 62)
+#define IRQ_DB8500_SBAG                 (IRQ_SHPI_START + 63)
+#define IRQ_DB8500_SPI1                 (IRQ_SHPI_START + 96)
+#define IRQ_DB8500_SRPTIMER             (IRQ_SHPI_START + 97)
+#define IRQ_DB8500_MSP2                 (IRQ_SHPI_START + 98)
+#define IRQ_DB8500_SDMMC4               (IRQ_SHPI_START + 99)
+#define IRQ_DB8500_SDMMC5               (IRQ_SHPI_START + 100)
+#define IRQ_DB8500_HSIRD0               (IRQ_SHPI_START + 104)
+#define IRQ_DB8500_HSIRD1               (IRQ_SHPI_START + 105)
+#define IRQ_DB8500_HSITD0               (IRQ_SHPI_START + 106)
+#define IRQ_DB8500_HSITD1               (IRQ_SHPI_START + 107)
+#define IRQ_DB8500_CTI0                 (IRQ_SHPI_START + 108)
+#define IRQ_DB8500_CTI1                 (IRQ_SHPI_START + 109)
+#define IRQ_DB8500_ICN_ERR              (IRQ_SHPI_START + 110)
+#define IRQ_DB8500_MALI_PPMMU           (IRQ_SHPI_START + 112)
+#define IRQ_DB8500_MALI_PP              (IRQ_SHPI_START + 113)
+#define IRQ_DB8500_MALI_GPMMU           (IRQ_SHPI_START + 114)
+#define IRQ_DB8500_MALI_GP              (IRQ_SHPI_START + 115)
+#define IRQ_DB8500_MALI                 (IRQ_SHPI_START + 116)
+#define IRQ_DB8500_PRCMU_SEM            (IRQ_SHPI_START + 118)
+#define IRQ_DB8500_GPIO0                (IRQ_SHPI_START + 119)
+#define IRQ_DB8500_GPIO1                (IRQ_SHPI_START + 120)
+#define IRQ_DB8500_GPIO2                (IRQ_SHPI_START + 121)
+#define IRQ_DB8500_GPIO3                (IRQ_SHPI_START + 122)
+#define IRQ_DB8500_GPIO4                (IRQ_SHPI_START + 123)
+#define IRQ_DB8500_GPIO5                (IRQ_SHPI_START + 124)
+#define IRQ_DB8500_GPIO6                (IRQ_SHPI_START + 125)
+#define IRQ_DB8500_GPIO7                (IRQ_SHPI_START + 126)
+#define IRQ_DB8500_GPIO8                (IRQ_SHPI_START + 127)
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 7970684b1d09..10385bdc2b77 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -10,7 +10,8 @@
 #ifndef ASM_ARCH_IRQS_H
 #define ASM_ARCH_IRQS_H
 
-#include <mach/hardware.h>
+#include <mach/irqs-db5500.h>
+#include <mach/irqs-db8500.h>
 
 #define IRQ_LOCALTIMER                  29
 #define IRQ_LOCALWDOG                   30
@@ -67,12 +68,21 @@
 /* There are 128 shared peripheral interrupts assigned to
  * INTID[160:32]. The first 32 interrupts are reserved.
  */
-#define U8500_SOC_NR_IRQS               161
+#define DBX500_NR_INTERNAL_IRQS         161
 
 /* After chip-specific IRQ numbers we have the GPIO ones */
 #define NOMADIK_NR_GPIO                 288
-#define NOMADIK_GPIO_TO_IRQ(gpio)       ((gpio) + U8500_SOC_NR_IRQS)
-#define NOMADIK_IRQ_TO_GPIO(irq)        ((irq) - U8500_SOC_NR_IRQS)
-#define NR_IRQS                         NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
+#define NOMADIK_GPIO_TO_IRQ(gpio)       ((gpio) + DBX500_NR_INTERNAL_IRQS)
+#define NOMADIK_IRQ_TO_GPIO(irq)        ((irq) - DBX500_NR_INTERNAL_IRQS)
+#define IRQ_BOARD_START                 NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
 
-#endif /*ASM_ARCH_IRQS_H*/
+/* This will be overridden by board-specific irq headers */
+#define IRQ_BOARD_END                   IRQ_BOARD_START
+
+#ifdef CONFIG_MACH_U8500_MOP
+#include <mach/irqs-board-mop500.h>
+#endif
+
+#define NR_IRQS                         IRQ_BOARD_END
+
+#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h
new file mode 100644
index 000000000000..9055d5d3233c
--- /dev/null
+++ b/arch/arm/mach-ux500/pins-db8500.h
@@ -0,0 +1,742 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License, version 2
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com>
+ */
+
+#ifndef __MACH_PINS_DB8500_H
+#define __MACH_PINS_DB8500_H
+
+/*
+ * TODO: Eventually encode all non-board specific pull up/down configuration
+ * here.
+ */
+
+#define GPIO0_GPIO              PIN_CFG(0, GPIO)
+#define GPIO0_U0_CTSn           PIN_CFG(0, ALT_A)
+#define GPIO0_TRIG_OUT          PIN_CFG(0, ALT_B)
+#define GPIO0_IP_TDO            PIN_CFG(0, ALT_C)
+
+#define GPIO1_GPIO              PIN_CFG(1, GPIO)
+#define GPIO1_U0_RTSn           PIN_CFG(1, ALT_A)
+#define GPIO1_TRIG_IN           PIN_CFG(1, ALT_B)
+#define GPIO1_IP_TDI            PIN_CFG(1, ALT_C)
+
+#define GPIO2_GPIO              PIN_CFG(2, GPIO)
+#define GPIO2_U0_RXD            PIN_CFG(2, ALT_A)
+#define GPIO2_NONE              PIN_CFG(2, ALT_B)
+#define GPIO2_IP_TMS            PIN_CFG(2, ALT_C)
+
+#define GPIO3_GPIO              PIN_CFG(3, GPIO)
+#define GPIO3_U0_TXD            PIN_CFG(3, ALT_A)
+#define GPIO3_NONE              PIN_CFG(3, ALT_B)
+#define GPIO3_IP_TCK            PIN_CFG(3, ALT_C)
+
+#define GPIO4_GPIO              PIN_CFG(4, GPIO)
+#define GPIO4_U1_RXD            PIN_CFG(4, ALT_A)
+#define GPIO4_I2C4_SCL          PIN_CFG_PULL(4, ALT_B, UP)
+#define GPIO4_IP_TRSTn          PIN_CFG(4, ALT_C)
+
+#define GPIO5_GPIO              PIN_CFG(5, GPIO)
+#define GPIO5_U1_TXD            PIN_CFG(5, ALT_A)
+#define GPIO5_I2C4_SDA          PIN_CFG_PULL(5, ALT_B, UP)
+#define GPIO5_IP_GPIO6          PIN_CFG(5, ALT_C)
+
+#define GPIO6_GPIO              PIN_CFG(6, GPIO)
+#define GPIO6_U1_CTSn           PIN_CFG(6, ALT_A)
+#define GPIO6_I2C1_SCL          PIN_CFG_PULL(6, ALT_B, UP)
+#define GPIO6_IP_GPIO0          PIN_CFG(6, ALT_C)
+
+#define GPIO7_GPIO              PIN_CFG(7, GPIO)
+#define GPIO7_U1_RTSn           PIN_CFG(7, ALT_A)
+#define GPIO7_I2C1_SDA          PIN_CFG_PULL(7, ALT_B, UP)
+#define GPIO7_IP_GPIO1          PIN_CFG(7, ALT_C)
+
+#define GPIO8_GPIO              PIN_CFG(8, GPIO)
+#define GPIO8_IPI2C_SDA         PIN_CFG_PULL(8, ALT_A, UP)
+#define GPIO8_I2C2_SDA          PIN_CFG_PULL(8, ALT_B, UP)
+
+#define GPIO9_GPIO              PIN_CFG(9, GPIO)
+#define GPIO9_IPI2C_SCL         PIN_CFG_PULL(9, ALT_A, UP)
+#define GPIO9_I2C2_SCL          PIN_CFG_PULL(9, ALT_B, UP)
+
+#define GPIO10_GPIO             PIN_CFG(10, GPIO)
+#define GPIO10_IPI2C_SDA        PIN_CFG_PULL(10, ALT_A, UP)
+#define GPIO10_I2C2_SDA         PIN_CFG_PULL(10, ALT_B, UP)
+#define GPIO10_IP_GPIO3         PIN_CFG(10, ALT_C)
+
+#define GPIO11_GPIO             PIN_CFG(11, GPIO)
+#define GPIO11_IPI2C_SCL        PIN_CFG_PULL(11, ALT_A, UP)
+#define GPIO11_I2C2_SCL         PIN_CFG_PULL(11, ALT_B, UP)
+#define GPIO11_IP_GPIO2         PIN_CFG(11, ALT_C)
+
+#define GPIO12_GPIO             PIN_CFG(12, GPIO)
+#define GPIO12_MSP0_TXD         PIN_CFG(12, ALT_A)
+#define GPIO12_MSP0_RXD         PIN_CFG(12, ALT_B)
+
+#define GPIO13_GPIO             PIN_CFG(13, GPIO)
+#define GPIO13_MSP0_TFS         PIN_CFG(13, ALT_A)
+
+#define GPIO14_GPIO             PIN_CFG(14, GPIO)
+#define GPIO14_MSP0_TCK         PIN_CFG(14, ALT_A)
+
+#define GPIO15_GPIO             PIN_CFG(15, GPIO)
+#define GPIO15_MSP0_RXD         PIN_CFG(15, ALT_A)
+#define GPIO15_MSP0_TXD         PIN_CFG(15, ALT_B)
+
+#define GPIO16_GPIO             PIN_CFG(16, GPIO)
+#define GPIO16_MSP0_RFS         PIN_CFG(16, ALT_A)
+#define GPIO16_I2C1_SCL         PIN_CFG_PULL(16, ALT_B, UP)
+#define GPIO16_SLIM0_DAT        PIN_CFG(16, ALT_C)
+
+#define GPIO17_GPIO             PIN_CFG(17, GPIO)
+#define GPIO17_MSP0_RCK         PIN_CFG(17, ALT_A)
+#define GPIO17_I2C1_SDA         PIN_CFG_PULL(17, ALT_B, UP)
+#define GPIO17_SLIM0_CLK        PIN_CFG(17, ALT_C)
+
+#define GPIO18_GPIO             PIN_CFG(18, GPIO)
+#define GPIO18_MC0_CMDDIR       PIN_CFG(18, ALT_A)
+#define GPIO18_U2_RXD           PIN_CFG(18, ALT_B)
+#define GPIO18_MS_IEP           PIN_CFG(18, ALT_C)
+
+#define GPIO19_GPIO             PIN_CFG(19, GPIO)
+#define GPIO19_MC0_DAT0DIR      PIN_CFG(19, ALT_A)
+#define GPIO19_U2_TXD           PIN_CFG(19, ALT_B)
+#define GPIO19_MS_DAT0DIR       PIN_CFG(19, ALT_C)
+
+#define GPIO20_GPIO             PIN_CFG(20, GPIO)
+#define GPIO20_MC0_DAT2DIR      PIN_CFG(20, ALT_A)
+#define GPIO20_UARTMOD_TXD      PIN_CFG(20, ALT_B)
+#define GPIO20_IP_TRIGOUT       PIN_CFG(20, ALT_C)
+
+#define GPIO21_GPIO             PIN_CFG(21, GPIO)
+#define GPIO21_MC0_DAT31DIR     PIN_CFG(21, ALT_A)
+#define GPIO21_MSP0_SCK         PIN_CFG(21, ALT_B)
+#define GPIO21_MS_DAT31DIR      PIN_CFG(21, ALT_C)
+
+#define GPIO22_GPIO             PIN_CFG(22, GPIO)
+#define GPIO22_MC0_FBCLK        PIN_CFG(22, ALT_A)
+#define GPIO22_UARTMOD_RXD      PIN_CFG(22, ALT_B)
+#define GPIO22_MS_FBCLK         PIN_CFG(22, ALT_C)
+
+#define GPIO23_GPIO             PIN_CFG(23, GPIO)
+#define GPIO23_MC0_CLK          PIN_CFG(23, ALT_A)
+#define GPIO23_STMMOD_CLK       PIN_CFG(23, ALT_B)
+#define GPIO23_MS_CLK           PIN_CFG(23, ALT_C)
+
+#define GPIO24_GPIO             PIN_CFG(24, GPIO)
+#define GPIO24_MC0_CMD          PIN_CFG(24, ALT_A)
+#define GPIO24_UARTMOD_RXD      PIN_CFG(24, ALT_B)
+#define GPIO24_MS_BS            PIN_CFG(24, ALT_C)
+
+#define GPIO25_GPIO             PIN_CFG(25, GPIO)
+#define GPIO25_MC0_DAT0         PIN_CFG(25, ALT_A)
+#define GPIO25_STMMOD_DAT0      PIN_CFG(25, ALT_B)
+#define GPIO25_MS_DAT0          PIN_CFG(25, ALT_C)
+
+#define GPIO26_GPIO             PIN_CFG(26, GPIO)
+#define GPIO26_MC0_DAT1         PIN_CFG(26, ALT_A)
+#define GPIO26_STMMOD_DAT1      PIN_CFG(26, ALT_B)
+#define GPIO26_MS_DAT1          PIN_CFG(26, ALT_C)
+
+#define GPIO27_GPIO             PIN_CFG(27, GPIO)
+#define GPIO27_MC0_DAT2         PIN_CFG(27, ALT_A)
+#define GPIO27_STMMOD_DAT2      PIN_CFG(27, ALT_B)
+#define GPIO27_MS_DAT2          PIN_CFG(27, ALT_C)
+
+#define GPIO28_GPIO             PIN_CFG(28, GPIO)
+#define GPIO28_MC0_DAT3         PIN_CFG(28, ALT_A)
+#define GPIO28_STMMOD_DAT3      PIN_CFG(28, ALT_B)
+#define GPIO28_MS_DAT3          PIN_CFG(28, ALT_C)
+
+#define GPIO29_GPIO             PIN_CFG(29, GPIO)
+#define GPIO29_MC0_DAT4         PIN_CFG(29, ALT_A)
+#define GPIO29_SPI3_CLK         PIN_CFG(29, ALT_B)
+#define GPIO29_U2_RXD           PIN_CFG(29, ALT_C)
+
+#define GPIO30_GPIO             PIN_CFG(30, GPIO)
+#define GPIO30_MC0_DAT5         PIN_CFG(30, ALT_A)
+#define GPIO30_SPI3_RXD         PIN_CFG(30, ALT_B)
+#define GPIO30_U2_TXD           PIN_CFG(30, ALT_C)
+
+#define GPIO31_GPIO             PIN_CFG(31, GPIO)
+#define GPIO31_MC0_DAT6         PIN_CFG(31, ALT_A)
+#define GPIO31_SPI3_FRM         PIN_CFG(31, ALT_B)
+#define GPIO31_U2_CTSn          PIN_CFG(31, ALT_C)
+
+#define GPIO32_GPIO             PIN_CFG(32, GPIO)
+#define GPIO32_MC0_DAT7         PIN_CFG(32, ALT_A)
+#define GPIO32_SPI3_TXD         PIN_CFG(32, ALT_B)
+#define GPIO32_U2_RTSn          PIN_CFG(32, ALT_C)
+
+#define GPIO33_GPIO             PIN_CFG(33, GPIO)
+#define GPIO33_MSP1_TXD         PIN_CFG(33, ALT_A)
+#define GPIO33_MSP1_RXD         PIN_CFG(33, ALT_B)
+#define GPIO33_U0_DTRn          PIN_CFG(33, ALT_C)
+
+#define GPIO34_GPIO             PIN_CFG(34, GPIO)
+#define GPIO34_MSP1_TFS         PIN_CFG(34, ALT_A)
+#define GPIO34_NONE             PIN_CFG(34, ALT_B)
+#define GPIO34_U0_DCDn          PIN_CFG(34, ALT_C)
+
+#define GPIO35_GPIO             PIN_CFG(35, GPIO)
+#define GPIO35_MSP1_TCK         PIN_CFG(35, ALT_A)
+#define GPIO35_NONE             PIN_CFG(35, ALT_B)
+#define GPIO35_U0_DSRn          PIN_CFG(35, ALT_C)
+
+#define GPIO36_GPIO             PIN_CFG(36, GPIO)
+#define GPIO36_MSP1_RXD         PIN_CFG(36, ALT_A)
+#define GPIO36_MSP1_TXD         PIN_CFG(36, ALT_B)
+#define GPIO36_U0_RIn           PIN_CFG(36, ALT_C)
+
+#define GPIO64_GPIO             PIN_CFG(64, GPIO)
+#define GPIO64_LCDB_DE          PIN_CFG(64, ALT_A)
+#define GPIO64_KP_O1            PIN_CFG(64, ALT_B)
+#define GPIO64_IP_GPIO4         PIN_CFG(64, ALT_C)
+
+#define GPIO65_GPIO             PIN_CFG(65, GPIO)
+#define GPIO65_LCDB_HSO         PIN_CFG(65, ALT_A)
+#define GPIO65_KP_O0            PIN_CFG(65, ALT_B)
+#define GPIO65_IP_GPIO5         PIN_CFG(65, ALT_C)
+
+#define GPIO66_GPIO             PIN_CFG(66, GPIO)
+#define GPIO66_LCDB_VSO         PIN_CFG(66, ALT_A)
+#define GPIO66_KP_I1            PIN_CFG(66, ALT_B)
+#define GPIO66_IP_GPIO6         PIN_CFG(66, ALT_C)
+
+#define GPIO67_GPIO             PIN_CFG(67, GPIO)
+#define GPIO67_LCDB_CLK         PIN_CFG(67, ALT_A)
+#define GPIO67_KP_I0            PIN_CFG(67, ALT_B)
+#define GPIO67_IP_GPIO7         PIN_CFG(67, ALT_C)
+
+#define GPIO68_GPIO             PIN_CFG(68, GPIO)
+#define GPIO68_LCD_VSI0         PIN_CFG(68, ALT_A)
+#define GPIO68_KP_O7            PIN_CFG(68, ALT_B)
+#define GPIO68_SM_CLE           PIN_CFG(68, ALT_C)
+
+#define GPIO69_GPIO             PIN_CFG(69, GPIO)
+#define GPIO69_LCD_VSI1         PIN_CFG(69, ALT_A)
+#define GPIO69_KP_I7            PIN_CFG(69, ALT_B)
+#define GPIO69_SM_ALE           PIN_CFG(69, ALT_C)
+
+#define GPIO70_GPIO             PIN_CFG(70, GPIO)
+#define GPIO70_LCD_D0           PIN_CFG(70, ALT_A)
+#define GPIO70_KP_O5            PIN_CFG(70, ALT_B)
+#define GPIO70_STMAPE_CLK       PIN_CFG(70, ALT_C)
+
+#define GPIO71_GPIO             PIN_CFG(71, GPIO)
+#define GPIO71_LCD_D1           PIN_CFG(71, ALT_A)
+#define GPIO71_KP_O4            PIN_CFG(71, ALT_B)
+#define GPIO71_STMAPE_DAT3      PIN_CFG(71, ALT_C)
+
+#define GPIO72_GPIO             PIN_CFG(72, GPIO)
+#define GPIO72_LCD_D2           PIN_CFG(72, ALT_A)
+#define GPIO72_KP_O3            PIN_CFG(72, ALT_B)
+#define GPIO72_STMAPE_DAT2      PIN_CFG(72, ALT_C)
+
+#define GPIO73_GPIO             PIN_CFG(73, GPIO)
+#define GPIO73_LCD_D3           PIN_CFG(73, ALT_A)
+#define GPIO73_KP_O2            PIN_CFG(73, ALT_B)
+#define GPIO73_STMAPE_DAT1      PIN_CFG(73, ALT_C)
+
+#define GPIO74_GPIO             PIN_CFG(74, GPIO)
+#define GPIO74_LCD_D4           PIN_CFG(74, ALT_A)
+#define GPIO74_KP_I5            PIN_CFG(74, ALT_B)
+#define GPIO74_STMAPE_DAT0      PIN_CFG(74, ALT_C)
+
+#define GPIO75_GPIO             PIN_CFG(75, GPIO)
+#define GPIO75_LCD_D5           PIN_CFG(75, ALT_A)
+#define GPIO75_KP_I4            PIN_CFG(75, ALT_B)
+#define GPIO75_U2_RXD           PIN_CFG(75, ALT_C)
+
+#define GPIO76_GPIO             PIN_CFG(76, GPIO)
+#define GPIO76_LCD_D6           PIN_CFG(76, ALT_A)
+#define GPIO76_KP_I3            PIN_CFG(76, ALT_B)
+#define GPIO76_U2_TXD           PIN_CFG(76, ALT_C)
+
+#define GPIO77_GPIO             PIN_CFG(77, GPIO)
+#define GPIO77_LCD_D7           PIN_CFG(77, ALT_A)
+#define GPIO77_KP_I2            PIN_CFG(77, ALT_B)
+#define GPIO77_NONE             PIN_CFG(77, ALT_C)
+
+#define GPIO78_GPIO             PIN_CFG(78, GPIO)
+#define GPIO78_LCD_D8           PIN_CFG(78, ALT_A)
+#define GPIO78_KP_O6            PIN_CFG(78, ALT_B)
+#define GPIO78_IP_GPIO2         PIN_CFG(78, ALT_C)
+
+#define GPIO79_GPIO             PIN_CFG(79, GPIO)
+#define GPIO79_LCD_D9           PIN_CFG(79, ALT_A)
+#define GPIO79_KP_I6            PIN_CFG(79, ALT_B)
+#define GPIO79_IP_GPIO3         PIN_CFG(79, ALT_C)
+
+#define GPIO80_GPIO             PIN_CFG(80, GPIO)
+#define GPIO80_LCD_D10          PIN_CFG(80, ALT_A)
+#define GPIO80_KP_SKA0          PIN_CFG(80, ALT_B)
+#define GPIO80_IP_GPIO4         PIN_CFG(80, ALT_C)
+
+#define GPIO81_GPIO             PIN_CFG(81, GPIO)
+#define GPIO81_LCD_D11          PIN_CFG(81, ALT_A)
+#define GPIO81_KP_SKB0          PIN_CFG(81, ALT_B)
+#define GPIO81_IP_GPIO5         PIN_CFG(81, ALT_C)
+
+#define GPIO82_GPIO             PIN_CFG(82, GPIO)
+#define GPIO82_LCD_D12          PIN_CFG(82, ALT_A)
+#define GPIO82_KP_O5            PIN_CFG(82, ALT_B)
+
+#define GPIO83_GPIO             PIN_CFG(83, GPIO)
+#define GPIO83_LCD_D13          PIN_CFG(83, ALT_A)
+#define GPIO83_KP_O4            PIN_CFG(83, ALT_B)
+
+#define GPIO84_GPIO             PIN_CFG(84, GPIO)
+#define GPIO84_LCD_D14          PIN_CFG(84, ALT_A)
+#define GPIO84_KP_I5            PIN_CFG(84, ALT_B)
+
+#define GPIO85_GPIO             PIN_CFG(85, GPIO)
+#define GPIO85_LCD_D15          PIN_CFG(85, ALT_A)
+#define GPIO85_KP_I4            PIN_CFG(85, ALT_B)
+
+#define GPIO86_GPIO             PIN_CFG(86, GPIO)
+#define GPIO86_LCD_D16          PIN_CFG(86, ALT_A)
+#define GPIO86_SM_ADQ0          PIN_CFG(86, ALT_B)
+#define GPIO86_MC5_DAT0         PIN_CFG(86, ALT_C)
+
+#define GPIO87_GPIO             PIN_CFG(87, GPIO)
+#define GPIO87_LCD_D17          PIN_CFG(87, ALT_A)
+#define GPIO87_SM_ADQ1          PIN_CFG(87, ALT_B)
+#define GPIO87_MC5_DAT1         PIN_CFG(87, ALT_C)
+
+#define GPIO88_GPIO             PIN_CFG(88, GPIO)
+#define GPIO88_LCD_D18          PIN_CFG(88, ALT_A)
+#define GPIO88_SM_ADQ2          PIN_CFG(88, ALT_B)
+#define GPIO88_MC5_DAT2         PIN_CFG(88, ALT_C)
+
+#define GPIO89_GPIO             PIN_CFG(89, GPIO)
+#define GPIO89_LCD_D19          PIN_CFG(89, ALT_A)
+#define GPIO89_SM_ADQ3          PIN_CFG(89, ALT_B)
+#define GPIO89_MC5_DAT3         PIN_CFG(89, ALT_C)
+
+#define GPIO90_GPIO             PIN_CFG(90, GPIO)
+#define GPIO90_LCD_D20          PIN_CFG(90, ALT_A)
+#define GPIO90_SM_ADQ4          PIN_CFG(90, ALT_B)
+#define GPIO90_MC5_CMD          PIN_CFG(90, ALT_C)
+
+#define GPIO91_GPIO             PIN_CFG(91, GPIO)
+#define GPIO91_LCD_D21          PIN_CFG(91, ALT_A)
+#define GPIO91_SM_ADQ5          PIN_CFG(91, ALT_B)
+#define GPIO91_MC5_FBCLK        PIN_CFG(91, ALT_C)
+
+#define GPIO92_GPIO             PIN_CFG(92, GPIO)
+#define GPIO92_LCD_D22          PIN_CFG(92, ALT_A)
+#define GPIO92_SM_ADQ6          PIN_CFG(92, ALT_B)
+#define GPIO92_MC5_CLK          PIN_CFG(92, ALT_C)
+
+#define GPIO93_GPIO             PIN_CFG(93, GPIO)
+#define GPIO93_LCD_D23          PIN_CFG(93, ALT_A)
+#define GPIO93_SM_ADQ7          PIN_CFG(93, ALT_B)
+#define GPIO93_MC5_DAT4         PIN_CFG(93, ALT_C)
+
+#define GPIO94_GPIO             PIN_CFG(94, GPIO)
+#define GPIO94_KP_O7            PIN_CFG(94, ALT_A)
+#define GPIO94_SM_ADVn          PIN_CFG(94, ALT_B)
+#define GPIO94_MC5_DAT5         PIN_CFG(94, ALT_C)
+
+#define GPIO95_GPIO             PIN_CFG(95, GPIO)
+#define GPIO95_KP_I7            PIN_CFG(95, ALT_A)
+#define GPIO95_SM_CS0n          PIN_CFG(95, ALT_B)
+#define GPIO95_SM_PS0n          PIN_CFG(95, ALT_C)
+
+#define GPIO96_GPIO             PIN_CFG(96, GPIO)
+#define GPIO96_KP_O6            PIN_CFG(96, ALT_A)
+#define GPIO96_SM_OEn           PIN_CFG(96, ALT_B)
+#define GPIO96_MC5_DAT6         PIN_CFG(96, ALT_C)
+
+#define GPIO97_GPIO             PIN_CFG(97, GPIO)
+#define GPIO97_KP_I6            PIN_CFG(97, ALT_A)
+#define GPIO97_SM_WEn           PIN_CFG(97, ALT_B)
+#define GPIO97_MC5_DAT7         PIN_CFG(97, ALT_C)
+
+#define GPIO128_GPIO            PIN_CFG(128, GPIO)
+#define GPIO128_MC2_CLK         PIN_CFG(128, ALT_A)
+#define GPIO128_SM_CKO          PIN_CFG(128, ALT_B)
+
+#define GPIO129_GPIO            PIN_CFG(129, GPIO)
+#define GPIO129_MC2_CMD         PIN_CFG(129, ALT_A)
+#define GPIO129_SM_WAIT0n       PIN_CFG(129, ALT_B)
+
+#define GPIO130_GPIO            PIN_CFG(130, GPIO)
+#define GPIO130_MC2_FBCLK       PIN_CFG(130, ALT_A)
+#define GPIO130_SM_FBCLK        PIN_CFG(130, ALT_B)
+#define GPIO130_MC2_RSTN        PIN_CFG(130, ALT_C)
+
+#define GPIO131_GPIO            PIN_CFG(131, GPIO)
+#define GPIO131_MC2_DAT0        PIN_CFG(131, ALT_A)
+#define GPIO131_SM_ADQ8         PIN_CFG(131, ALT_B)
+
+#define GPIO132_GPIO            PIN_CFG(132, GPIO)
+#define GPIO132_MC2_DAT1        PIN_CFG(132, ALT_A)
+#define GPIO132_SM_ADQ9         PIN_CFG(132, ALT_B)
+
+#define GPIO133_GPIO            PIN_CFG(133, GPIO)
+#define GPIO133_MC2_DAT2        PIN_CFG(133, ALT_A)
+#define GPIO133_SM_ADQ10        PIN_CFG(133, ALT_B)
+
+#define GPIO134_GPIO            PIN_CFG(134, GPIO)
+#define GPIO134_MC2_DAT3        PIN_CFG(134, ALT_A)
+#define GPIO134_SM_ADQ11        PIN_CFG(134, ALT_B)
+
+#define GPIO135_GPIO            PIN_CFG(135, GPIO)
+#define GPIO135_MC2_DAT4        PIN_CFG(135, ALT_A)
+#define GPIO135_SM_ADQ12        PIN_CFG(135, ALT_B)
+
+#define GPIO136_GPIO            PIN_CFG(136, GPIO)
+#define GPIO136_MC2_DAT5        PIN_CFG(136, ALT_A)
+#define GPIO136_SM_ADQ13        PIN_CFG(136, ALT_B)
+
+#define GPIO137_GPIO            PIN_CFG(137, GPIO)
+#define GPIO137_MC2_DAT6        PIN_CFG(137, ALT_A)
+#define GPIO137_SM_ADQ14        PIN_CFG(137, ALT_B)
+
+#define GPIO138_GPIO            PIN_CFG(138, GPIO)
+#define GPIO138_MC2_DAT7        PIN_CFG(138, ALT_A)
+#define GPIO138_SM_ADQ15        PIN_CFG(138, ALT_B)
+
+#define GPIO139_GPIO            PIN_CFG(139, GPIO)
+#define GPIO139_SSP1_RXD        PIN_CFG(139, ALT_A)
+#define GPIO139_SM_WAIT1n       PIN_CFG(139, ALT_B)
+#define GPIO139_KP_O8           PIN_CFG(139, ALT_C)
+
+#define GPIO140_GPIO            PIN_CFG(140, GPIO)
+#define GPIO140_SSP1_TXD        PIN_CFG(140, ALT_A)
+#define GPIO140_IP_GPIO7        PIN_CFG(140, ALT_B)
+#define GPIO140_KP_SKA1         PIN_CFG(140, ALT_C)
+
+#define GPIO141_GPIO            PIN_CFG(141, GPIO)
+#define GPIO141_SSP1_CLK        PIN_CFG(141, ALT_A)
+#define GPIO141_IP_GPIO2        PIN_CFG(141, ALT_B)
+#define GPIO141_KP_O9           PIN_CFG(141, ALT_C)
+
+#define GPIO142_GPIO            PIN_CFG(142, GPIO)
+#define GPIO142_SSP1_FRM        PIN_CFG(142, ALT_A)
+#define GPIO142_IP_GPIO3        PIN_CFG(142, ALT_B)
+#define GPIO142_KP_SKB1         PIN_CFG(142, ALT_C)
+
+#define GPIO143_GPIO            PIN_CFG(143, GPIO)
+#define GPIO143_SSP0_CLK        PIN_CFG(143, ALT_A)
+
+#define GPIO144_GPIO            PIN_CFG(144, GPIO)
+#define GPIO144_SSP0_FRM        PIN_CFG(144, ALT_A)
+
+#define GPIO145_GPIO            PIN_CFG(145, GPIO)
+#define GPIO145_SSP0_RXD        PIN_CFG(145, ALT_A)
+
+#define GPIO146_GPIO            PIN_CFG(146, GPIO)
+#define GPIO146_SSP0_TXD        PIN_CFG(146, ALT_A)
+
+#define GPIO147_GPIO            PIN_CFG(147, GPIO)
+#define GPIO147_I2C0_SCL        PIN_CFG_PULL(147, ALT_A, UP)
+
+#define GPIO148_GPIO            PIN_CFG(148, GPIO)
+#define GPIO148_I2C0_SDA        PIN_CFG_PULL(148, ALT_A, UP)
+
+#define GPIO149_GPIO            PIN_CFG(149, GPIO)
+#define GPIO149_IP_GPIO0        PIN_CFG(149, ALT_A)
+#define GPIO149_SM_CS1n         PIN_CFG(149, ALT_B)
+#define GPIO149_SM_PS1n         PIN_CFG(149, ALT_C)
+
+#define GPIO150_GPIO            PIN_CFG(150, GPIO)
+#define GPIO150_IP_GPIO1        PIN_CFG(150, ALT_A)
+#define GPIO150_LCDA_CLK        PIN_CFG(150, ALT_B)
+
+#define GPIO151_GPIO            PIN_CFG(151, GPIO)
+#define GPIO151_KP_SKA0         PIN_CFG(151, ALT_A)
+#define GPIO151_LCD_VSI0        PIN_CFG(151, ALT_B)
+#define GPIO151_KP_O8           PIN_CFG(151, ALT_C)
+
+#define GPIO152_GPIO            PIN_CFG(152, GPIO)
+#define GPIO152_KP_SKB0         PIN_CFG(152, ALT_A)
+#define GPIO152_LCD_VSI1        PIN_CFG(152, ALT_B)
+#define GPIO152_KP_O9           PIN_CFG(152, ALT_C)
+
+#define GPIO153_GPIO            PIN_CFG(153, GPIO)
+#define GPIO153_KP_I7           PIN_CFG(153, ALT_A)
+#define GPIO153_LCD_D24         PIN_CFG(153, ALT_B)
+#define GPIO153_U2_RXD          PIN_CFG(153, ALT_C)
+
+#define GPIO154_GPIO            PIN_CFG(154, GPIO)
+#define GPIO154_KP_I6           PIN_CFG(154, ALT_A)
+#define GPIO154_LCD_D25         PIN_CFG(154, ALT_B)
+#define GPIO154_U2_TXD          PIN_CFG(154, ALT_C)
+
+#define GPIO155_GPIO            PIN_CFG(155, GPIO)
+#define GPIO155_KP_I5           PIN_CFG(155, ALT_A)
+#define GPIO155_LCD_D26         PIN_CFG(155, ALT_B)
+#define GPIO155_STMAPE_CLK      PIN_CFG(155, ALT_C)
+
+#define GPIO156_GPIO            PIN_CFG(156, GPIO)
+#define GPIO156_KP_I4           PIN_CFG(156, ALT_A)
+#define GPIO156_LCD_D27         PIN_CFG(156, ALT_B)
+#define GPIO156_STMAPE_DAT3     PIN_CFG(156, ALT_C)
+
+#define GPIO157_GPIO            PIN_CFG(157, GPIO)
+#define GPIO157_KP_O7           PIN_CFG(157, ALT_A)
+#define GPIO157_LCD_D28         PIN_CFG(157, ALT_B)
+#define GPIO157_STMAPE_DAT2     PIN_CFG(157, ALT_C)
+
+#define GPIO158_GPIO            PIN_CFG(158, GPIO)
+#define GPIO158_KP_O6           PIN_CFG(158, ALT_A)
+#define GPIO158_LCD_D29         PIN_CFG(158, ALT_B)
+#define GPIO158_STMAPE_DAT1     PIN_CFG(158, ALT_C)
+
+#define GPIO159_GPIO            PIN_CFG(159, GPIO)
+#define GPIO159_KP_O5           PIN_CFG(159, ALT_A)
+#define GPIO159_LCD_D30         PIN_CFG(159, ALT_B)
+#define GPIO159_STMAPE_DAT0     PIN_CFG(159, ALT_C)
+
+#define GPIO160_GPIO            PIN_CFG(160, GPIO)
+#define GPIO160_KP_O4           PIN_CFG(160, ALT_A)
+#define GPIO160_LCD_D31         PIN_CFG(160, ALT_B)
+#define GPIO160_NONE            PIN_CFG(160, ALT_C)
+
+#define GPIO161_GPIO            PIN_CFG(161, GPIO)
+#define GPIO161_KP_I3           PIN_CFG(161, ALT_A)
+#define GPIO161_LCD_D32         PIN_CFG(161, ALT_B)
+#define GPIO161_UARTMOD_RXD     PIN_CFG(161, ALT_C)
+
+#define GPIO162_GPIO            PIN_CFG(162, GPIO)
+#define GPIO162_KP_I2           PIN_CFG(162, ALT_A)
+#define GPIO162_LCD_D33         PIN_CFG(162, ALT_B)
+#define GPIO162_UARTMOD_TXD     PIN_CFG(162, ALT_C)
+
+#define GPIO163_GPIO            PIN_CFG(163, GPIO)
+#define GPIO163_KP_I1           PIN_CFG(163, ALT_A)
+#define GPIO163_LCD_D34         PIN_CFG(163, ALT_B)
+#define GPIO163_STMMOD_CLK      PIN_CFG(163, ALT_C)
+
+#define GPIO164_GPIO            PIN_CFG(164, GPIO)
+#define GPIO164_KP_I0           PIN_CFG(164, ALT_A)
+#define GPIO164_LCD_D35         PIN_CFG(164, ALT_B)
+#define GPIO164_STMMOD_DAT3     PIN_CFG(164, ALT_C)
+
+#define GPIO165_GPIO            PIN_CFG(165, GPIO)
+#define GPIO165_KP_O3           PIN_CFG(165, ALT_A)
+#define GPIO165_LCD_D36         PIN_CFG(165, ALT_B)
+#define GPIO165_STMMOD_DAT2     PIN_CFG(165, ALT_C)
+
+#define GPIO166_GPIO            PIN_CFG(166, GPIO)
+#define GPIO166_KP_O2           PIN_CFG(166, ALT_A)
+#define GPIO166_LCD_D37         PIN_CFG(166, ALT_B)
+#define GPIO166_STMMOD_DAT1     PIN_CFG(166, ALT_C)
+
+#define GPIO167_GPIO            PIN_CFG(167, GPIO)
+#define GPIO167_KP_O1           PIN_CFG(167, ALT_A)
+#define GPIO167_LCD_D38         PIN_CFG(167, ALT_B)
+#define GPIO167_STMMOD_DAT0     PIN_CFG(167, ALT_C)
+
+#define GPIO168_GPIO            PIN_CFG(168, GPIO)
+#define GPIO168_KP_O0           PIN_CFG(168, ALT_A)
+#define GPIO168_LCD_D39         PIN_CFG(168, ALT_B)
+#define GPIO168_NONE            PIN_CFG(168, ALT_C)
+
+#define GPIO169_GPIO            PIN_CFG(169, GPIO)
+#define GPIO169_RF_PURn         PIN_CFG(169, ALT_A)
+#define GPIO169_LCDA_DE         PIN_CFG(169, ALT_B)
+#define GPIO169_USBSIM_PDC      PIN_CFG(169, ALT_C)
+
+#define GPIO170_GPIO            PIN_CFG(170, GPIO)
+#define GPIO170_MODEM_STATE     PIN_CFG(170, ALT_A)
+#define GPIO170_LCDA_VSO        PIN_CFG(170, ALT_B)
+#define GPIO170_KP_SKA1         PIN_CFG(170, ALT_C)
+
+#define GPIO171_GPIO            PIN_CFG(171, GPIO)
+#define GPIO171_MODEM_PWREN     PIN_CFG(171, ALT_A)
+#define GPIO171_LCDA_HSO        PIN_CFG(171, ALT_B)
+#define GPIO171_KP_SKB1         PIN_CFG(171, ALT_C)
+
+#define GPIO192_GPIO            PIN_CFG(192, GPIO)
+#define GPIO192_MSP2_SCK        PIN_CFG(192, ALT_A)
+
+#define GPIO193_GPIO            PIN_CFG(193, GPIO)
+#define GPIO193_MSP2_TXD        PIN_CFG(193, ALT_A)
+
+#define GPIO194_GPIO            PIN_CFG(194, GPIO)
+#define GPIO194_MSP2_TCK        PIN_CFG(194, ALT_A)
+
+#define GPIO195_GPIO            PIN_CFG(195, GPIO)
+#define GPIO195_MSP2_TFS        PIN_CFG(195, ALT_A)
+
+#define GPIO196_GPIO            PIN_CFG(196, GPIO)
+#define GPIO196_MSP2_RXD        PIN_CFG(196, ALT_A)
+
+#define GPIO197_GPIO            PIN_CFG(197, GPIO)
+#define GPIO197_MC4_DAT3        PIN_CFG(197, ALT_A)
+
+#define GPIO198_GPIO            PIN_CFG(198, GPIO)
+#define GPIO198_MC4_DAT2        PIN_CFG(198, ALT_A)
+
+#define GPIO199_GPIO            PIN_CFG(199, GPIO)
+#define GPIO199_MC4_DAT1        PIN_CFG(199, ALT_A)
+
+#define GPIO200_GPIO            PIN_CFG(200, GPIO)
+#define GPIO200_MC4_DAT0        PIN_CFG(200, ALT_A)
+
+#define GPIO201_GPIO            PIN_CFG(201, GPIO)
+#define GPIO201_MC4_CMD         PIN_CFG(201, ALT_A)
+
+#define GPIO202_GPIO            PIN_CFG(202, GPIO)
+#define GPIO202_MC4_FBCLK       PIN_CFG(202, ALT_A)
+#define GPIO202_PWL             PIN_CFG(202, ALT_B)
+#define GPIO202_MC4_RSTN        PIN_CFG(202, ALT_C)
+
+#define GPIO203_GPIO            PIN_CFG(203, GPIO)
+#define GPIO203_MC4_CLK         PIN_CFG(203, ALT_A)
+
+#define GPIO204_GPIO            PIN_CFG(204, GPIO)
+#define GPIO204_MC4_DAT7        PIN_CFG(204, ALT_A)
+
+#define GPIO205_GPIO            PIN_CFG(205, GPIO)
+#define GPIO205_MC4_DAT6        PIN_CFG(205, ALT_A)
+
+#define GPIO206_GPIO            PIN_CFG(206, GPIO)
+#define GPIO206_MC4_DAT5        PIN_CFG(206, ALT_A)
+
+#define GPIO207_GPIO            PIN_CFG(207, GPIO)
+#define GPIO207_MC4_DAT4        PIN_CFG(207, ALT_A)
+
+#define GPIO208_GPIO            PIN_CFG(208, GPIO)
+#define GPIO208_MC1_CLK         PIN_CFG(208, ALT_A)
+
+#define GPIO209_GPIO            PIN_CFG(209, GPIO)
+#define GPIO209_MC1_FBCLK       PIN_CFG(209, ALT_A)
+#define GPIO209_SPI1_CLK        PIN_CFG(209, ALT_B)
+
+#define GPIO210_GPIO            PIN_CFG(210, GPIO)
+#define GPIO210_MC1_CMD         PIN_CFG(210, ALT_A)
+
+#define GPIO211_GPIO            PIN_CFG(211, GPIO)
+#define GPIO211_MC1_DAT0        PIN_CFG(211, ALT_A)
+
+#define GPIO212_GPIO            PIN_CFG(212, GPIO)
+#define GPIO212_MC1_DAT1        PIN_CFG(212, ALT_A)
+#define GPIO212_SPI1_FRM        PIN_CFG(212, ALT_B)
+
+#define GPIO213_GPIO            PIN_CFG(213, GPIO)
+#define GPIO213_MC1_DAT2        PIN_CFG(213, ALT_A)
+#define GPIO213_SPI1_TXD        PIN_CFG(213, ALT_B)
+
+#define GPIO214_GPIO            PIN_CFG(214, GPIO)
+#define GPIO214_MC1_DAT3        PIN_CFG(214, ALT_A)
+#define GPIO214_SPI1_RXD        PIN_CFG(214, ALT_B)
+
+#define GPIO215_GPIO            PIN_CFG(215, GPIO)
+#define GPIO215_MC1_CMDDIR      PIN_CFG(215, ALT_A)
+#define GPIO215_MC3_DAT2DIR     PIN_CFG(215, ALT_B)
+#define GPIO215_CLKOUT1         PIN_CFG(215, ALT_C)
+
+#define GPIO216_GPIO            PIN_CFG(216, GPIO)
+#define GPIO216_MC1_DAT2DIR     PIN_CFG(216, ALT_A)
+#define GPIO216_MC3_CMDDIR      PIN_CFG(216, ALT_B)
+#define GPIO216_I2C3_SDA        PIN_CFG_PULL(216, ALT_C, UP)
+
+#define GPIO217_GPIO            PIN_CFG(217, GPIO)
+#define GPIO217_MC1_DAT0DIR     PIN_CFG(217, ALT_A)
+#define GPIO217_MC3_DAT31DIR    PIN_CFG(217, ALT_B)
+#define GPIO217_CLKOUT2         PIN_CFG(217, ALT_C)
+
+#define GPIO218_GPIO            PIN_CFG(218, GPIO)
+#define GPIO218_MC1_DAT31DIR    PIN_CFG(218, ALT_A)
+#define GPIO218_MC3_DAT0DIR     PIN_CFG(218, ALT_B)
+#define GPIO218_I2C3_SCL        PIN_CFG_PULL(218, ALT_C, UP)
+
+#define GPIO219_GPIO            PIN_CFG(219, GPIO)
+#define GPIO219_HSIR_FLA0       PIN_CFG(219, ALT_A)
+#define GPIO219_MC3_CLK         PIN_CFG(219, ALT_B)
+
+#define GPIO220_GPIO            PIN_CFG(220, GPIO)
+#define GPIO220_HSIR_DAT0       PIN_CFG(220, ALT_A)
+#define GPIO220_MC3_FBCLK       PIN_CFG(220, ALT_B)
+#define GPIO220_SPI0_CLK        PIN_CFG(220, ALT_C)
+
+#define GPIO221_GPIO            PIN_CFG(221, GPIO)
+#define GPIO221_HSIR_RDY0       PIN_CFG(221, ALT_A)
+#define GPIO221_MC3_CMD         PIN_CFG(221, ALT_B)
+
+#define GPIO222_GPIO            PIN_CFG(222, GPIO)
+#define GPIO222_HSIT_FLA0       PIN_CFG(222, ALT_A)
+#define GPIO222_MC3_DAT0        PIN_CFG(222, ALT_B)
+
+#define GPIO223_GPIO            PIN_CFG(223, GPIO)
+#define GPIO223_HSIT_DAT0       PIN_CFG(223, ALT_A)
+#define GPIO223_MC3_DAT1        PIN_CFG(223, ALT_B)
+#define GPIO223_SPI0_FRM        PIN_CFG(223, ALT_C)
+
+#define GPIO224_GPIO            PIN_CFG(224, GPIO)
+#define GPIO224_HSIT_RDY0       PIN_CFG(224, ALT_A)
+#define GPIO224_MC3_DAT2        PIN_CFG(224, ALT_B)
+#define GPIO224_SPI0_TXD        PIN_CFG(224, ALT_C)
+
+#define GPIO225_GPIO            PIN_CFG(225, GPIO)
+#define GPIO225_HSIT_CAWAKE0    PIN_CFG(225, ALT_A)
+#define GPIO225_MC3_DAT3        PIN_CFG(225, ALT_B)
+#define GPIO225_SPI0_RXD        PIN_CFG(225, ALT_C)
+
+#define GPIO226_GPIO            PIN_CFG(226, GPIO)
+#define GPIO226_HSIT_ACWAKE0    PIN_CFG(226, ALT_A)
+#define GPIO226_PWL             PIN_CFG(226, ALT_B)
+#define GPIO226_USBSIM_PDC      PIN_CFG(226, ALT_C)
+
+#define GPIO227_GPIO            PIN_CFG(227, GPIO)
+#define GPIO227_CLKOUT1         PIN_CFG(227, ALT_A)
+
+#define GPIO228_GPIO            PIN_CFG(228, GPIO)
+#define GPIO228_CLKOUT2         PIN_CFG(228, ALT_A)
+
+#define GPIO229_GPIO            PIN_CFG(229, GPIO)
+#define GPIO229_CLKOUT1         PIN_CFG(229, ALT_A)
+#define GPIO229_PWL             PIN_CFG(229, ALT_B)
+#define GPIO229_I2C3_SDA        PIN_CFG_PULL(229, ALT_C, UP)
+
+#define GPIO230_GPIO            PIN_CFG(230, GPIO)
+#define GPIO230_CLKOUT2         PIN_CFG(230, ALT_A)
+#define GPIO230_PWL             PIN_CFG(230, ALT_B)
+#define GPIO230_I2C3_SCL        PIN_CFG_PULL(230, ALT_C, UP)
+
+#define GPIO256_GPIO            PIN_CFG(256, GPIO)
+#define GPIO256_USB_NXT         PIN_CFG(256, ALT_A)
+
+#define GPIO257_GPIO            PIN_CFG(257, GPIO)
+#define GPIO257_USB_STP         PIN_CFG(257, ALT_A)
+
+#define GPIO258_GPIO            PIN_CFG(258, GPIO)
+#define GPIO258_USB_XCLK        PIN_CFG(258, ALT_A)
+#define GPIO258_NONE            PIN_CFG(258, ALT_B)
+#define GPIO258_DDR_TRIG        PIN_CFG(258, ALT_C)
+
+#define GPIO259_GPIO            PIN_CFG(259, GPIO)
+#define GPIO259_USB_DIR         PIN_CFG(259, ALT_A)
+
+#define GPIO260_GPIO            PIN_CFG(260, GPIO)
+#define GPIO260_USB_DAT7        PIN_CFG(260, ALT_A)
+
+#define GPIO261_GPIO            PIN_CFG(261, GPIO)
+#define GPIO261_USB_DAT6        PIN_CFG(261, ALT_A)
+
+#define GPIO262_GPIO            PIN_CFG(262, GPIO)
+#define GPIO262_USB_DAT5        PIN_CFG(262, ALT_A)
+
+#define GPIO263_GPIO            PIN_CFG(263, GPIO)
+#define GPIO263_USB_DAT4        PIN_CFG(263, ALT_A)
+
+#define GPIO264_GPIO            PIN_CFG(264, GPIO)
+#define GPIO264_USB_DAT3        PIN_CFG(264, ALT_A)
+
+#define GPIO265_GPIO            PIN_CFG(265, GPIO)
+#define GPIO265_USB_DAT2        PIN_CFG(265, ALT_A)
+
+#define GPIO266_GPIO            PIN_CFG(266, GPIO)
+#define GPIO266_USB_DAT1        PIN_CFG(266, ALT_A)
+
+#define GPIO267_GPIO            PIN_CFG(267, GPIO)
+#define GPIO267_USB_DAT0        PIN_CFG(267, ALT_A)
+
+#endif
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 3dff8641b03f..e38acb0f89c8 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -28,6 +28,7 @@
 #include <linux/amba/clcd.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 #include <linux/gfp.h>
 
@@ -354,6 +355,21 @@ static struct mmci_platform_data mmc0_plat_data = {
         .gpio_cd        = -1,
 };
 
+static struct resource char_lcd_resources[] = {
+        {
+                .start = VERSATILE_CHAR_LCD_BASE,
+                .end   = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device char_lcd_device = {
+        .name           =       "arm-charlcd",
+        .id             =       -1,
+        .num_resources  =       ARRAY_SIZE(char_lcd_resources),
+        .resource       =       char_lcd_resources,
+};
+
 /*
  * Clock handling
  */
@@ -400,8 +416,13 @@ static struct clk ref24_clk = {
         .rate   = 24000000,
 };
 
+static struct clk dummy_apb_pclk;
+
 static struct clk_lookup lookups[] = {
-        {       /* UART0 */
+        {       /* AMBA bus clock */
+                .con_id         = "apb_pclk",
+                .clk            = &dummy_apb_pclk,
+        }, {    /* UART0 */
                 .dev_id         = "dev:f1",
                 .clk            = &ref24_clk,
         }, {    /* UART1 */
@@ -425,6 +446,9 @@ static struct clk_lookup lookups[] = {
         }, {    /* MMC1 */
                 .dev_id         = "fpga:0b",
                 .clk            = &ref24_clk,
+        }, {    /* SSP */
+                .dev_id         = "dev:f4",
+                .clk            = &ref24_clk,
         }, {    /* CLCD */
                 .dev_id         = "dev:20",
                 .clk            = &osc4_clk,
@@ -703,6 +727,12 @@ static struct pl061_platform_data gpio1_plat_data = {
         .irq_base       = IRQ_GPIO1_START,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 0,
+        .num_chipselect = 1,
+};
+
 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 #define AACI_DMA        { 0x80, 0x81 }
 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
@@ -772,7 +802,7 @@ AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
-AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
+AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      &ssp0_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
         &dmac_device,
@@ -843,6 +873,7 @@ void __init versatile_init(void)
         platform_device_register(&versatile_flash_device);
         platform_device_register(&versatile_i2c_device);
         platform_device_register(&smc91x_device);
+        platform_device_register(&char_lcd_device);
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 334f0df4e948..13c7e5f90a82 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -304,7 +304,7 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 }
 
 
-struct pci_bus *pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
+struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
 {
         return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys);
 }
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 6353459bb567..577df6cccb08 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -16,6 +16,7 @@
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
+#include <asm/smp_twd.h>
 
 #include <mach/clkdev.h>
 #include <mach/ct-ca9x4.h>
@@ -53,6 +54,7 @@ static struct map_desc ct_ca9x4_io_desc[] __initdata = {
 
 static void __init ct_ca9x4_map_io(void)
 {
+        twd_base = MMIO_P2V(A9_MPCORE_TWD);
         v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
 }
 
diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
index 8650f04136ef..f9e2f8d22962 100644
--- a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
+++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
@@ -28,6 +28,7 @@
 #define A9_MPCORE_SCU           (CT_CA9X4_MPIC + 0x0000)
 #define A9_MPCORE_GIC_CPU       (CT_CA9X4_MPIC + 0x0100)
 #define A9_MPCORE_GIT           (CT_CA9X4_MPIC + 0x0200)
+#define A9_MPCORE_TWD           (CT_CA9X4_MPIC + 0x0600)
 #define A9_MPCORE_GIC_DIST      (CT_CA9X4_MPIC + 0x1000)
 
 /*
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index d250711b8c7a..d6db3453908b 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -298,8 +298,13 @@ static struct clk osc2_clk = {
         .rate   = 24000000,
 };
 
+static struct clk dummy_apb_pclk;
+
 static struct clk_lookup v2m_lookups[] = {
-        {       /* UART0 */
+        {       /* AMBA bus clock */
+                .con_id         = "apb_pclk",
+                .clk            = &dummy_apb_pclk,
+        }, {    /* UART0 */
                 .dev_id         = "mb:uart0",
                 .clk            = &osc2_clk,
         }, {    /* UART1 */
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 642207e18198..83c56324a472 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -93,7 +93,7 @@ static struct clk_lookup nuc900_clkregs[] = {
         DEF_CLKLOOK(&clk_kpi, "nuc900-kpi", NULL),
         DEF_CLKLOOK(&clk_wdt, "nuc900-wdt", NULL),
         DEF_CLKLOOK(&clk_gdma, "nuc900-gdma", NULL),
-        DEF_CLKLOOK(&clk_adc, "nuc900-adc", NULL),
+        DEF_CLKLOOK(&clk_adc, "nuc900-ts", NULL),
         DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL),
         DEF_CLKLOOK(&clk_ext, NULL, "ext"),
         DEF_CLKLOOK(&clk_timer0, NULL, "timer0"),
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
index b2eda4dc1c34..7a1fa6adb7c3 100644
--- a/arch/arm/mach-w90x900/dev.c
+++ b/arch/arm/mach-w90x900/dev.c
@@ -36,6 +36,8 @@
 #include <mach/nuc900_spi.h>
 #include <mach/map.h>
 #include <mach/fb.h>
+#include <mach/regs-ldm.h>
+#include <mach/w90p910_keypad.h>
 
 #include "cpu.h"
 
@@ -207,7 +209,7 @@ static struct nuc900_spi_info nuc900_spiflash_data = {
         .divider        = 24,
         .sleep          = 0,
         .txnum          = 0,
-        .txbitlen       = 1,
+        .txbitlen       = 8,
         .bus_num        = 0,
 };
 
@@ -256,7 +258,7 @@ static struct spi_board_info nuc900_spi_board_info[] __initdata = {
                 .modalias = "m25p80",
                 .max_speed_hz = 20000000,
                 .bus_num = 0,
-                .chip_select = 1,
+                .chip_select = 0,
                 .platform_data = &nuc900_spi_flash_data,
                 .mode = SPI_MODE_0,
         },
@@ -361,6 +363,39 @@ struct platform_device nuc900_device_fmi = {
 
 /* KPI controller*/
 
+static int nuc900_keymap[] = {
+        KEY(0, 0, KEY_A),
+        KEY(0, 1, KEY_B),
+        KEY(0, 2, KEY_C),
+        KEY(0, 3, KEY_D),
+
+        KEY(1, 0, KEY_E),
+        KEY(1, 1, KEY_F),
+        KEY(1, 2, KEY_G),
+        KEY(1, 3, KEY_H),
+
+        KEY(2, 0, KEY_I),
+        KEY(2, 1, KEY_J),
+        KEY(2, 2, KEY_K),
+        KEY(2, 3, KEY_L),
+
+        KEY(3, 0, KEY_M),
+        KEY(3, 1, KEY_N),
+        KEY(3, 2, KEY_O),
+        KEY(3, 3, KEY_P),
+};
+
+static struct matrix_keymap_data nuc900_map_data = {
+        .keymap                 = nuc900_keymap,
+        .keymap_size            = ARRAY_SIZE(nuc900_keymap),
+};
+
+struct w90p910_keypad_platform_data nuc900_keypad_info = {
+        .keymap_data    = &nuc900_map_data,
+        .prescale       = 0xfa,
+        .debounce       = 0x50,
+};
+
 static struct resource nuc900_kpi_resource[] = {
         [0] = {
                 .start = W90X900_PA_KPI,
@@ -380,9 +415,49 @@ struct platform_device nuc900_device_kpi = {
         .id             = -1,
         .num_resources  = ARRAY_SIZE(nuc900_kpi_resource),
         .resource       = nuc900_kpi_resource,
+        .dev            = {
+                                .platform_data = &nuc900_keypad_info,
+                        }
 };
 
-#ifdef CONFIG_FB_NUC900
+/* LCD controller*/
+
+static struct nuc900fb_display __initdata nuc900_lcd_info[] = {
+        /* Giantplus Technology GPM1040A0 320x240 Color TFT LCD */
+        [0] = {
+                .type           = LCM_DCCS_VA_SRC_RGB565,
+                .width          = 320,
+                .height         = 240,
+                .xres           = 320,
+                .yres           = 240,
+                .bpp            = 16,
+                .pixclock       = 200000,
+                .left_margin    = 34,
+                .right_margin   = 54,
+                .hsync_len      = 10,
+                .upper_margin   = 18,
+                .lower_margin   = 4,
+                .vsync_len      = 1,
+                .dccs           = 0x8e00041a,
+                .devctl         = 0x060800c0,
+                .fbctrl         = 0x00a000a0,
+                .scale          = 0x04000400,
+        },
+};
+
+static struct nuc900fb_mach_info nuc900_fb_info __initdata = {
+#if defined(CONFIG_GPM1040A0_320X240)
+        .displays               = &nuc900_lcd_info[0],
+#else
+        .displays               = nuc900_lcd_info,
+#endif
+        .num_displays           = ARRAY_SIZE(nuc900_lcd_info),
+        .default_display        = 0,
+        .gpio_dir               = 0x00000004,
+        .gpio_dir_mask          = 0xFFFFFFFD,
+        .gpio_data              = 0x00000004,
+        .gpio_data_mask         = 0xFFFFFFFD,
+};
 
 static struct resource nuc900_lcd_resource[] = {
         [0] = {
@@ -406,23 +481,10 @@ struct platform_device nuc900_device_lcd = {
         .dev              = {
                 .dma_mask               = &nuc900_device_lcd_dmamask,
                 .coherent_dma_mask      = -1,
+                .platform_data = &nuc900_fb_info,
         }
 };
 
-void  nuc900_fb_set_platdata(struct nuc900fb_mach_info *pd)
-{
-        struct nuc900fb_mach_info *npd;
-
-        npd = kmalloc(sizeof(*npd), GFP_KERNEL);
-        if (npd) {
-                memcpy(npd, pd, sizeof(*npd));
-                nuc900_device_lcd.dev.platform_data = npd;
-        } else {
-                printk(KERN_ERR "no memory for LCD platform data\n");
-        }
-}
-#endif
-
 /* AUDIO controller*/
 static u64 nuc900_device_audio_dmamask = -1;
 static struct resource nuc900_ac97_resource[] = {
diff --git a/arch/arm/mach-w90x900/include/mach/regs-gcr.h b/arch/arm/mach-w90x900/include/mach/regs-gcr.h
new file mode 100644
index 000000000000..6087abd93ef5
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/regs-gcr.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-w90x900/include/mach/regs-gcr.h
+ *
+ * Copyright (c) 2010 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_REGS_GCR_H
+#define __ASM_ARCH_REGS_GCR_H
+
+/* Global control registers */
+
+#define GCR_BA          W90X900_VA_GCR
+#define REG_PDID        (GCR_BA+0x000)
+#define REG_PWRON       (GCR_BA+0x004)
+#define REG_ARBCON      (GCR_BA+0x008)
+#define REG_MFSEL       (GCR_BA+0x00C)
+#define REG_EBIDPE      (GCR_BA+0x010)
+#define REG_LCDDPE      (GCR_BA+0x014)
+#define REG_GPIOCPE     (GCR_BA+0x018)
+#define REG_GPIODPE     (GCR_BA+0x01C)
+#define REG_GPIOEPE     (GCR_BA+0x020)
+#define REG_GPIOFPE     (GCR_BA+0x024)
+#define REG_GPIOGPE     (GCR_BA+0x028)
+#define REG_GPIOHPE     (GCR_BA+0x02C)
+#define REG_GPIOIPE     (GCR_BA+0x030)
+#define REG_GTMP1       (GCR_BA+0x034)
+#define REG_GTMP2       (GCR_BA+0x038)
+#define REG_GTMP3       (GCR_BA+0x03C)
+
+#endif /*  __ASM_ARCH_REGS_GCR_H */
diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c
index b3edc3cccf52..04d295f89eb0 100644
--- a/arch/arm/mach-w90x900/mach-nuc950evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc950evb.c
@@ -20,51 +20,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach-types.h>
 #include <mach/map.h>
-#include <mach/regs-ldm.h>
 #include <mach/fb.h>
 
 #include "nuc950.h"
 
-#ifdef CONFIG_FB_NUC900
-/* LCD Controller */
-static struct nuc900fb_display __initdata nuc950_lcd_info[] = {
-        /* Giantplus Technology GPM1040A0 320x240 Color TFT LCD */
-        [0] = {
-                .type           = LCM_DCCS_VA_SRC_RGB565,
-                .width          = 320,
-                .height         = 240,
-                .xres           = 320,
-                .yres           = 240,
-                .bpp            = 16,
-                .pixclock       = 200000,
-                .left_margin    = 34,
-                .right_margin   = 54,
-                .hsync_len      = 10,
-                .upper_margin   = 18,
-                .lower_margin   = 4,
-                .vsync_len      = 1,
-                .dccs           = 0x8e00041a,
-                .devctl         = 0x060800c0,
-                .fbctrl         = 0x00a000a0,
-                .scale          = 0x04000400,
-        },
-};
-
-static struct nuc900fb_mach_info nuc950_fb_info __initdata = {
-#if defined(CONFIG_GPM1040A0_320X240)
-        .displays               = &nuc950_lcd_info[0],
-#else
-        .displays               = nuc950_lcd_info,
-#endif
-        .num_displays           = ARRAY_SIZE(nuc950_lcd_info),
-        .default_display        = 0,
-        .gpio_dir               = 0x00000004,
-        .gpio_dir_mask          = 0xFFFFFFFD,
-        .gpio_data              = 0x00000004,
-        .gpio_data_mask         = 0xFFFFFFFD,
-};
-#endif
-
 static void __init nuc950evb_map_io(void)
 {
         nuc950_map_io();
@@ -74,9 +33,6 @@ static void __init nuc950evb_map_io(void)
 static void __init nuc950evb_init(void)
 {
         nuc950_board_init();
-#ifdef CONFIG_FB_NUC900
-        nuc900_fb_set_platdata(&nuc950_fb_info);
-#endif
 }
 
 MACHINE_START(W90P950EVB, "W90P950EVB")
diff --git a/arch/arm/mach-w90x900/nuc910.c b/arch/arm/mach-w90x900/nuc910.c
index 656f03b3b629..1523f4136985 100644
--- a/arch/arm/mach-w90x900/nuc910.c
+++ b/arch/arm/mach-w90x900/nuc910.c
@@ -26,6 +26,8 @@
 static struct platform_device *nuc910_dev[] __initdata = {
         &nuc900_device_ts,
         &nuc900_device_rtc,
+        &nuc900_device_lcd,
+        &nuc900_device_kpi,
 };
 
 /* define specific CPU platform io map */
diff --git a/arch/arm/mach-w90x900/nuc950.c b/arch/arm/mach-w90x900/nuc950.c
index 4d1f1ab044c4..5704f74a50ee 100644
--- a/arch/arm/mach-w90x900/nuc950.c
+++ b/arch/arm/mach-w90x900/nuc950.c
@@ -26,9 +26,7 @@
 static struct platform_device *nuc950_dev[] __initdata = {
         &nuc900_device_kpi,
         &nuc900_device_fmi,
-#ifdef CONFIG_FB_NUC900
         &nuc900_device_lcd,
-#endif
 };
 
 /* define specific CPU platform io map */
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 101105e52610..87ec141fcaa6 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -717,17 +717,6 @@ config TLS_REG_EMUL
           a few prototypes like that in existence) and therefore access to
           that required register must be emulated.
 
-config HAS_TLS_REG
-        bool
-        depends on !TLS_REG_EMUL
-        default y if SMP || CPU_32v7
-        help
-          This selects support for the CP15 thread register.
-          It is defined to be available on some ARMv6 processors (including
-          all SMP capable ARMv6's) or later processors.  User space may
-          assume directly accessing that register and always obtain the
-          expected value only on ARMv7 and above.
-
 config NEEDS_SYSCALL_FOR_CMPXCHG
         bool
         help
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 28c8b950ef04..03f11935ed08 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -268,6 +268,12 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
         if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK))
                 return NULL;
 
+        /*
+         * Don't allow RAM to be mapped - this causes problems with ARMv6+
+         */
+        if (WARN_ON(pfn_valid(pfn)))
+                return NULL;
+
         type = get_mem_type(mtype);
         if (!type)
                 return NULL;
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 7a5337ed7d68..2f5a3c23a0fe 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -239,7 +239,8 @@ __v6_proc_info:
         b       __v6_setup
         .long   cpu_arch_name
         .long   cpu_elf_name
-        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
+        /* See also feat_v6_fixup() for HWCAP_TLS */
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
         .long   cpu_v6_name
         .long   v6_processor_functions
         .long   v6wbi_tlb_fns
@@ -262,7 +263,7 @@ __pj4_v6_proc_info:
         b       __v6_setup
         .long   cpu_arch_name
         .long   cpu_elf_name
-        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
         .long   cpu_pj4_name
         .long   v6_processor_functions
         .long   v6wbi_tlb_fns
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7aaf88a3b7aa..8071bcd4c995 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -344,7 +344,7 @@ __v7_proc_info:
         b       __v7_setup
         .long   cpu_arch_name
         .long   cpu_elf_name
-        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
         .long   cpu_v7_name
         .long   v7_processor_functions
         .long   v7wbi_tlb_fns
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 6c8a02ad98e3..85d3e55ca4a9 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -29,6 +29,11 @@
 #include <mach/time.h>
 
 /*
+ * Minimum clocksource/clockevent timer range in seconds
+ */
+#define IOP_MIN_RANGE 4
+
+/*
  * IOP clocksource (free-running timer 1).
  */
 static cycle_t iop_clocksource_read(struct clocksource *unused)
@@ -44,27 +49,6 @@ static struct clocksource iop_clocksource = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int hz)
-{
-        u64 temp;
-        u32 shift;
-
-        /* Find shift and mult values for hz. */
-        shift = 32;
-        do {
-                temp = (u64) NSEC_PER_SEC << shift;
-                do_div(temp, hz);
-                if ((temp >> 32) == 0)
-                        break;
-        } while (--shift != 0);
-
-        cs->shift = shift;
-        cs->mult = (u32) temp;
-
-        printk(KERN_INFO "clocksource: %s uses shift %u mult %#x\n",
-               cs->name, cs->shift, cs->mult);
-}
-
 /*
  * IOP sched_clock() implementation via its clocksource.
  */
@@ -130,27 +114,6 @@ static struct clock_event_device iop_clockevent = {
         .set_mode       = iop_set_mode,
 };
 
-static void __init iop_clockevent_set_hz(struct clock_event_device *ce, unsigned int hz)
-{
-        u64 temp;
-        u32 shift;
-
-        /* Find shift and mult values for hz. */
-        shift = 32;
-        do {
-                temp = (u64) hz << shift;
-                do_div(temp, NSEC_PER_SEC);
-                if ((temp >> 32) == 0)
-                        break;
-        } while (--shift != 0);
-
-        ce->shift = shift;
-        ce->mult = (u32) temp;
-
-        printk(KERN_INFO "clockevent: %s uses shift %u mult %#lx\n",
-               ce->name, ce->shift, ce->mult);
-}
-
 static irqreturn_t
 iop_timer_interrupt(int irq, void *dev_id)
 {
@@ -190,7 +153,8 @@ void __init iop_init_time(unsigned long tick_rate)
          */
         write_tmr0(timer_ctl & ~IOP_TMR_EN);
         setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
-        iop_clockevent_set_hz(&iop_clockevent, tick_rate);
+        clockevents_calc_mult_shift(&iop_clockevent,
+                                    tick_rate, IOP_MIN_RANGE);
         iop_clockevent.max_delta_ns =
                 clockevent_delta2ns(0xfffffffe, &iop_clockevent);
         iop_clockevent.min_delta_ns =
@@ -207,6 +171,7 @@ void __init iop_init_time(unsigned long tick_rate)
         write_trr1(0xffffffff);
         write_tcr1(0xffffffff);
         write_tmr1(timer_ctl);
-        iop_clocksource_set_hz(&iop_clocksource, tick_rate);
+        clocksource_calc_mult_shift(&iop_clocksource, tick_rate,
+                                    IOP_MIN_RANGE);
         clocksource_register(&iop_clocksource);
 }
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 5a6ef252c38b..977c8f9a07a2 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -23,6 +23,7 @@
 #include <linux/irq.h>
 #include <linux/slab.h>
 
+#include <plat/pincfg.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
 
@@ -46,28 +47,217 @@ struct nmk_gpio_chip {
         u32 edge_falling;
 };
 
+static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
+                                unsigned offset, int gpio_mode)
+{
+        u32 bit = 1 << offset;
+        u32 afunc, bfunc;
+
+        afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
+        bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
+        if (gpio_mode & NMK_GPIO_ALT_A)
+                afunc |= bit;
+        if (gpio_mode & NMK_GPIO_ALT_B)
+                bfunc |= bit;
+        writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
+        writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
+}
+
+static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
+                                unsigned offset, enum nmk_gpio_slpm mode)
+{
+        u32 bit = 1 << offset;
+        u32 slpm;
+
+        slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
+        if (mode == NMK_GPIO_SLPM_NOCHANGE)
+                slpm |= bit;
+        else
+                slpm &= ~bit;
+        writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
+}
+
+static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
+                                unsigned offset, enum nmk_gpio_pull pull)
+{
+        u32 bit = 1 << offset;
+        u32 pdis;
+
+        pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
+        if (pull == NMK_GPIO_PULL_NONE)
+                pdis |= bit;
+        else
+                pdis &= ~bit;
+        writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
+
+        if (pull == NMK_GPIO_PULL_UP)
+                writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
+        else if (pull == NMK_GPIO_PULL_DOWN)
+                writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
+}
+
+static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
+                                  unsigned offset)
+{
+        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
+}
+
+static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
+                             pin_cfg_t cfg)
+{
+        static const char *afnames[] = {
+                [NMK_GPIO_ALT_GPIO]     = "GPIO",
+                [NMK_GPIO_ALT_A]        = "A",
+                [NMK_GPIO_ALT_B]        = "B",
+                [NMK_GPIO_ALT_C]        = "C"
+        };
+        static const char *pullnames[] = {
+                [NMK_GPIO_PULL_NONE]    = "none",
+                [NMK_GPIO_PULL_UP]      = "up",
+                [NMK_GPIO_PULL_DOWN]    = "down",
+                [3] /* illegal */       = "??"
+        };
+        static const char *slpmnames[] = {
+                [NMK_GPIO_SLPM_INPUT]           = "input",
+                [NMK_GPIO_SLPM_NOCHANGE]        = "no-change",
+        };
+
+        int pin = PIN_NUM(cfg);
+        int pull = PIN_PULL(cfg);
+        int af = PIN_ALT(cfg);
+        int slpm = PIN_SLPM(cfg);
+
+        dev_dbg(nmk_chip->chip.dev, "pin %d: af %s, pull %s, slpm %s\n",
+                pin, afnames[af], pullnames[pull], slpmnames[slpm]);
+
+        __nmk_gpio_make_input(nmk_chip, offset);
+        __nmk_gpio_set_pull(nmk_chip, offset, pull);
+        __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
+        __nmk_gpio_set_mode(nmk_chip, offset, af);
+}
+
+/**
+ * nmk_config_pin - configure a pin's mux attributes
+ * @cfg: pin confguration
+ *
+ * Configures a pin's mode (alternate function or GPIO), its pull up status,
+ * and its sleep mode based on the specified configuration.  The @cfg is
+ * usually one of the SoC specific macros defined in mach/<soc>-pins.h.  These
+ * are constructed using, and can be further enhanced with, the macros in
+ * plat/pincfg.h.
+ *
+ * If a pin's mode is set to GPIO, it is configured as an input to avoid
+ * side-effects.  The gpio can be manipulated later using standard GPIO API
+ * calls.
+ */
+int nmk_config_pin(pin_cfg_t cfg)
+{
+        struct nmk_gpio_chip *nmk_chip;
+        int gpio = PIN_NUM(cfg);
+        unsigned long flags;
+
+        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        if (!nmk_chip)
+                return -EINVAL;
+
+        spin_lock_irqsave(&nmk_chip->lock, flags);
+        __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg);
+        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(nmk_config_pin);
+
+/**
+ * nmk_config_pins - configure several pins at once
+ * @cfgs: array of pin configurations
+ * @num: number of elments in the array
+ *
+ * Configures several pins using nmk_config_pin().  Refer to that function for
+ * further information.
+ */
+int nmk_config_pins(pin_cfg_t *cfgs, int num)
+{
+        int ret = 0;
+        int i;
+
+        for (i = 0; i < num; i++) {
+                int ret = nmk_config_pin(cfgs[i]);
+                if (ret)
+                        break;
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL(nmk_config_pins);
+
+/**
+ * nmk_gpio_set_slpm() - configure the sleep mode of a pin
+ * @gpio: pin number
+ * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
+ *
+ * Sets the sleep mode of a pin.  If @mode is NMK_GPIO_SLPM_INPUT, the pin is
+ * changed to an input (with pullup/down enabled) in sleep and deep sleep.  If
+ * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was
+ * configured even when in sleep and deep sleep.
+ */
+int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
+{
+        struct nmk_gpio_chip *nmk_chip;
+        unsigned long flags;
+
+        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        if (!nmk_chip)
+                return -EINVAL;
+
+        spin_lock_irqsave(&nmk_chip->lock, flags);
+        __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
+        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+        return 0;
+}
+
+/**
+ * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
+ * @gpio: pin number
+ * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
+ *
+ * Enables/disables pull up/down on a specified pin.  This only takes effect if
+ * the pin is configured as an input (either explicitly or by the alternate
+ * function).
+ *
+ * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
+ * configured as an input.  Otherwise, due to the way the controller registers
+ * work, this function will change the value output on the pin.
+ */
+int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
+{
+        struct nmk_gpio_chip *nmk_chip;
+        unsigned long flags;
+
+        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        if (!nmk_chip)
+                return -EINVAL;
+
+        spin_lock_irqsave(&nmk_chip->lock, flags);
+        __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull);
+        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+        return 0;
+}
+
 /* Mode functions */
 int nmk_gpio_set_mode(int gpio, int gpio_mode)
 {
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
-        u32 afunc, bfunc, bit;
 
         nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
         if (!nmk_chip)
                 return -EINVAL;
 
-        bit = 1 << (gpio - nmk_chip->chip.base);
-
         spin_lock_irqsave(&nmk_chip->lock, flags);
-        afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
-        bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
-        if (gpio_mode & NMK_GPIO_ALT_A)
-                afunc |= bit;
-        if (gpio_mode & NMK_GPIO_ALT_B)
-                bfunc |= bit;
-        writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
-        writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
+        __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode);
         spin_unlock_irqrestore(&nmk_chip->lock, flags);
 
         return 0;
@@ -111,32 +301,41 @@ static void nmk_gpio_irq_ack(unsigned int irq)
         writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
 }
 
+enum nmk_gpio_irq_type {
+        NORMAL,
+        WAKE,
+};
+
 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
-                                  int gpio, bool enable)
+                                  int gpio, enum nmk_gpio_irq_type which,
+                                  bool enable)
 {
+        u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC;
+        u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC;
         u32 bitmask = nmk_gpio_get_bitmask(gpio);
         u32 reg;
 
         /* we must individually set/clear the two edges */
         if (nmk_chip->edge_rising & bitmask) {
-                reg = readl(nmk_chip->addr + NMK_GPIO_RIMSC);
+                reg = readl(nmk_chip->addr + rimsc);
                 if (enable)
                         reg |= bitmask;
                 else
                         reg &= ~bitmask;
-                writel(reg, nmk_chip->addr + NMK_GPIO_RIMSC);
+                writel(reg, nmk_chip->addr + rimsc);
         }
         if (nmk_chip->edge_falling & bitmask) {
-                reg = readl(nmk_chip->addr + NMK_GPIO_FIMSC);
+                reg = readl(nmk_chip->addr + fimsc);
                 if (enable)
                         reg |= bitmask;
                 else
                         reg &= ~bitmask;
-                writel(reg, nmk_chip->addr + NMK_GPIO_FIMSC);
+                writel(reg, nmk_chip->addr + fimsc);
         }
 }
 
-static void nmk_gpio_irq_modify(unsigned int irq, bool enable)
+static int nmk_gpio_irq_modify(unsigned int irq, enum nmk_gpio_irq_type which,
+                               bool enable)
 {
         int gpio;
         struct nmk_gpio_chip *nmk_chip;
@@ -147,26 +346,35 @@ static void nmk_gpio_irq_modify(unsigned int irq, bool enable)
         nmk_chip = get_irq_chip_data(irq);
         bitmask = nmk_gpio_get_bitmask(gpio);
         if (!nmk_chip)
-                return;
+                return -EINVAL;
 
         spin_lock_irqsave(&nmk_chip->lock, flags);
-        __nmk_gpio_irq_modify(nmk_chip, gpio, enable);
+        __nmk_gpio_irq_modify(nmk_chip, gpio, which, enable);
         spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+        return 0;
 }
 
 static void nmk_gpio_irq_mask(unsigned int irq)
 {
-        nmk_gpio_irq_modify(irq, false);
-};
+        nmk_gpio_irq_modify(irq, NORMAL, false);
+}
 
 static void nmk_gpio_irq_unmask(unsigned int irq)
 {
-        nmk_gpio_irq_modify(irq, true);
+        nmk_gpio_irq_modify(irq, NORMAL, true);
+}
+
+static int nmk_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+{
+        return nmk_gpio_irq_modify(irq, WAKE, on);
 }
 
 static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
 {
-        bool enabled = !(irq_to_desc(irq)->status & IRQ_DISABLED);
+        struct irq_desc *desc = irq_to_desc(irq);
+        bool enabled = !(desc->status & IRQ_DISABLED);
+        bool wake = desc->wake_depth;
         int gpio;
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
@@ -186,7 +394,10 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
         spin_lock_irqsave(&nmk_chip->lock, flags);
 
         if (enabled)
-                __nmk_gpio_irq_modify(nmk_chip, gpio, false);
+                __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
+
+        if (wake)
+                __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
 
         nmk_chip->edge_rising &= ~bitmask;
         if (type & IRQ_TYPE_EDGE_RISING)
@@ -197,7 +408,10 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
                 nmk_chip->edge_falling |= bitmask;
 
         if (enabled)
-                __nmk_gpio_irq_modify(nmk_chip, gpio, true);
+                __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
+
+        if (wake)
+                __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
 
         spin_unlock_irqrestore(&nmk_chip->lock, flags);
 
@@ -210,6 +424,7 @@ static struct irq_chip nmk_gpio_irq_chip = {
         .mask           = nmk_gpio_irq_mask,
         .unmask         = nmk_gpio_irq_unmask,
         .set_type       = nmk_gpio_irq_set_type,
+        .set_wake       = nmk_gpio_irq_set_wake,
 };
 
 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
@@ -266,16 +481,6 @@ static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
         return 0;
 }
 
-static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
-                                int val)
-{
-        struct nmk_gpio_chip *nmk_chip =
-                container_of(chip, struct nmk_gpio_chip, chip);
-
-        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
-        return 0;
-}
-
 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
 {
         struct nmk_gpio_chip *nmk_chip =
@@ -298,12 +503,33 @@ static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
                 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
 }
 
+static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
+                                int val)
+{
+        struct nmk_gpio_chip *nmk_chip =
+                container_of(chip, struct nmk_gpio_chip, chip);
+
+        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
+        nmk_gpio_set_output(chip, offset, val);
+
+        return 0;
+}
+
+static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        struct nmk_gpio_chip *nmk_chip =
+                container_of(chip, struct nmk_gpio_chip, chip);
+
+        return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
+}
+
 /* This structure is replicated for each GPIO block allocated at probe time */
 static struct gpio_chip nmk_gpio_template = {
         .direction_input        = nmk_gpio_make_input,
         .get                    = nmk_gpio_get_input,
         .direction_output       = nmk_gpio_make_output,
         .set                    = nmk_gpio_set_output,
+        .to_irq                 = nmk_gpio_to_irq,
         .ngpio                  = NMK_GPIO_PER_CHIP,
         .can_sleep              = 0,
 };
@@ -393,30 +619,12 @@ out:
         return ret;
 }
 
-static int __exit nmk_gpio_remove(struct platform_device *dev)
-{
-        struct nmk_gpio_chip *nmk_chip;
-        struct resource *res;
-
-        res = platform_get_resource(dev, IORESOURCE_MEM, 0);
-
-        nmk_chip = platform_get_drvdata(dev);
-        gpiochip_remove(&nmk_chip->chip);
-        clk_disable(nmk_chip->clk);
-        clk_put(nmk_chip->clk);
-        kfree(nmk_chip);
-        release_mem_region(res->start, resource_size(res));
-        return 0;
-}
-
-
 static struct platform_driver nmk_gpio_driver = {
         .driver = {
                 .owner = THIS_MODULE,
                 .name = "gpio",
                 },
         .probe = nmk_gpio_probe,
-        .remove = __exit_p(nmk_gpio_remove),
         .suspend = NULL, /* to be done */
         .resume = NULL,
 };
@@ -426,7 +634,7 @@ static int __init nmk_gpio_init(void)
         return platform_driver_register(&nmk_gpio_driver);
 }
 
-arch_initcall(nmk_gpio_init);
+core_initcall(nmk_gpio_init);
 
 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
 MODULE_DESCRIPTION("Nomadik GPIO Driver");
diff --git a/arch/arm/plat-nomadik/include/plat/gpio.h b/arch/arm/plat-nomadik/include/plat/gpio.h
index 4200811249ca..aba355101f49 100644
--- a/arch/arm/plat-nomadik/include/plat/gpio.h
+++ b/arch/arm/plat-nomadik/include/plat/gpio.h
@@ -55,6 +55,21 @@
 #define NMK_GPIO_ALT_B  2
 #define NMK_GPIO_ALT_C  (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
 
+/* Pull up/down values */
+enum nmk_gpio_pull {
+        NMK_GPIO_PULL_NONE,
+        NMK_GPIO_PULL_UP,
+        NMK_GPIO_PULL_DOWN,
+};
+
+/* Sleep mode */
+enum nmk_gpio_slpm {
+        NMK_GPIO_SLPM_INPUT,
+        NMK_GPIO_SLPM_NOCHANGE,
+};
+
+extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode);
+extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull);
 extern int nmk_gpio_set_mode(int gpio, int gpio_mode);
 extern int nmk_gpio_get_mode(int gpio);
 
diff --git a/arch/arm/plat-nomadik/include/plat/mtu.h b/arch/arm/plat-nomadik/include/plat/mtu.h
index 42c907258b14..65704a3d4241 100644
--- a/arch/arm/plat-nomadik/include/plat/mtu.h
+++ b/arch/arm/plat-nomadik/include/plat/mtu.h
@@ -1,6 +1,12 @@
 #ifndef __PLAT_MTU_H
 #define __PLAT_MTU_H
 
+/*
+ * Guaranteed runtime conversion range in seconds for
+ * the clocksource and clockevent.
+ */
+#define MTU_MIN_RANGE 4
+
 /* should be set by the platform code */
 extern void __iomem *mtu_base;
 
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
new file mode 100644
index 000000000000..7eed11c1038d
--- /dev/null
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License, version 2
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ *
+ * Based on arch/arm/mach-pxa/include/mach/mfp.h:
+ *   Copyright (C) 2007 Marvell International Ltd.
+ *   eric miao <eric.miao@marvell.com>
+ */
+
+#ifndef __PLAT_PINCFG_H
+#define __PLAT_PINCFG_H
+
+/*
+ * pin configurations are represented by 32-bit integers:
+ *
+ *      bit  0.. 8 - Pin Number (512 Pins Maximum)
+ *      bit  9..10 - Alternate Function Selection
+ *      bit 11..12 - Pull up/down state
+ *      bit     13 - Sleep mode behaviour
+ *
+ * to facilitate the definition, the following macros are provided
+ *
+ * PIN_CFG_DEFAULT - default config (0):
+ *                   pull up/down = disabled
+ *                   sleep mode = input
+ *
+ * PIN_CFG         - default config with alternate function
+ * PIN_CFG_PULL    - default config with alternate function and pull up/down
+ */
+
+typedef unsigned long pin_cfg_t;
+
+#define PIN_NUM_MASK            0x1ff
+#define PIN_NUM(x)              ((x) & PIN_NUM_MASK)
+
+#define PIN_ALT_SHIFT           9
+#define PIN_ALT_MASK            (0x3 << PIN_ALT_SHIFT)
+#define PIN_ALT(x)              (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
+#define PIN_GPIO                (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
+#define PIN_ALT_A               (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
+#define PIN_ALT_B               (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
+#define PIN_ALT_C               (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
+
+#define PIN_PULL_SHIFT          11
+#define PIN_PULL_MASK           (0x3 << PIN_PULL_SHIFT)
+#define PIN_PULL(x)             (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
+#define PIN_PULL_NONE           (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
+#define PIN_PULL_UP             (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
+#define PIN_PULL_DOWN           (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
+
+#define PIN_SLPM_SHIFT          13
+#define PIN_SLPM_MASK           (0x1 << PIN_SLPM_SHIFT)
+#define PIN_SLPM(x)             (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
+#define PIN_SLPM_INPUT          (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
+#define PIN_SLPM_NOCHANGE       (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
+
+#define PIN_CFG_DEFAULT         (PIN_PULL_NONE | PIN_SLPM_INPUT)
+
+#define PIN_CFG(num, alt)               \
+        (PIN_CFG_DEFAULT |\
+         (PIN_NUM(num) | PIN_##alt))
+
+#define PIN_CFG_PULL(num, alt, pull)    \
+        ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\
+         (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull))
+
+extern int nmk_config_pin(pin_cfg_t cfg);
+extern int nmk_config_pins(pin_cfg_t *cfgs, int num);
+
+#endif
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index 08aaa4a7f65f..ea3ca86c5283 100644
--- a/arch/arm/plat-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -42,7 +42,6 @@ static struct clocksource nmdk_clksrc = {
         .rating         = 200,
         .read           = nmdk_read_timer_dummy,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 20,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -82,6 +81,12 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
         case CLOCK_EVT_MODE_UNUSED:
                 /* disable irq */
                 writel(0, mtu_base + MTU_IMSC);
+                /* disable timer */
+                cr = readl(mtu_base + MTU_CR(1));
+                cr &= ~MTU_CRn_ENA;
+                writel(cr, mtu_base + MTU_CR(1));
+                /* load some high default value */
+                writel(0xffffffff, mtu_base + MTU_LR(1));
                 break;
         case CLOCK_EVT_MODE_RESUME:
                 break;
@@ -98,7 +103,6 @@ static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
 static struct clock_event_device nmdk_clkevt = {
         .name           = "mtu_1",
         .features       = CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
         .rating         = 200,
         .set_mode       = nmdk_clkevt_mode,
         .set_next_event = nmdk_clkevt_next,
@@ -151,6 +155,7 @@ void __init nmdk_timer_init(void)
         } else {
                 cr |= MTU_CRn_PRESCALE_1;
         }
+        clocksource_calc_mult_shift(&nmdk_clksrc, rate, MTU_MIN_RANGE);
 
         /* Timer 0 is the free running clocksource */
         writel(cr, mtu_base + MTU_CR(0));
@@ -158,7 +163,6 @@ void __init nmdk_timer_init(void)
         writel(0, mtu_base + MTU_BGLR(0));
         writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
 
-        nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift);
         /* Now the scheduling clock is ready */
         nmdk_clksrc.read = nmdk_read_timer;
 
@@ -175,8 +179,10 @@ void __init nmdk_timer_init(void)
         } else {
                 cr |= MTU_CRn_PRESCALE_1;
         }
+        clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
+
         writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
-        nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift);
+
         nmdk_clkevt.max_delta_ns =
                 clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
         nmdk_clkevt.min_delta_ns =
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S
index 1670734b7e51..37fa593884ee 100644
--- a/arch/arm/plat-spear/include/plat/debug-macro.S
+++ b/arch/arm/plat-spear/include/plat/debug-macro.S
@@ -17,8 +17,8 @@
                 .macro  addruart, rx
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                                 @ MMU enabled?
-                moveq   \rx, =SPEAR_DBG_UART_BASE               @ Physical base
-                movne   \rx, =VA_SPEAR_DBG_UART_BASE            @ Virtual base
+                moveq   \rx, #SPEAR_DBG_UART_BASE               @ Physical base
+                movne   \rx, #VA_SPEAR_DBG_UART_BASE            @ Virtual base
                 .endm
 
                 .macro  senduart, rd, rx
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index a1025d38f383..ab211652e4ca 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -58,6 +58,11 @@
 
 #define INT_STATUS              0x1
 
+/*
+ * Minimum clocksource/clockevent timer range in seconds
+ */
+#define SPEAR_MIN_RANGE 4
+
 static __iomem void *gpt_base;
 static struct clk *gpt_clk;
 
@@ -66,44 +71,6 @@ static void clockevent_set_mode(enum clock_event_mode mode,
 static int clockevent_next_event(unsigned long evt,
                                  struct clock_event_device *clk_event_dev);
 
-/*
- * Following clocksource_set_clock and clockevent_set_clock picked
- * from arch/mips/kernel/time.c
- */
-
-void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock)
-{
-        u64 temp;
-        u32 shift;
-
-        /* Find a shift value */
-        for (shift = 32; shift > 0; shift--) {
-                temp = (u64) NSEC_PER_SEC << shift;
-                do_div(temp, clock);
-                if ((temp >> 32) == 0)
-                        break;
-        }
-        cs->shift = shift;
-        cs->mult = (u32) temp;
-}
-
-void __init clockevent_set_clock(struct clock_event_device *cd,
-        unsigned int clock)
-{
-        u64 temp;
-        u32 shift;
-
-        /* Find a shift value */
-        for (shift = 32; shift > 0; shift--) {
-                temp = (u64) clock << shift;
-                do_div(temp, NSEC_PER_SEC);
-                if ((temp >> 32) == 0)
-                        break;
-        }
-        cd->shift = shift;
-        cd->mult = (u32) temp;
-}
-
 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 {
         return (cycle_t) readw(gpt_base + COUNT(CLKSRC));
@@ -138,7 +105,7 @@ static void spear_clocksource_init(void)
         val |= CTRL_ENABLE ;
         writew(val, gpt_base + CR(CLKSRC));
 
-        clocksource_set_clock(&clksrc, tick_rate);
+        clocksource_calc_mult_shift(&clksrc, tick_rate, SPEAR_MIN_RANGE);
 
         /* register the clocksource */
         clocksource_register(&clksrc);
@@ -233,7 +200,7 @@ static void __init spear_clockevent_init(void)
         tick_rate = clk_get_rate(gpt_clk);
         tick_rate >>= CTRL_PRESCALER16;
 
-        clockevent_set_clock(&clkevt, tick_rate);
+        clockevents_calc_mult_shift(&clkevt, tick_rate, SPEAR_MIN_RANGE);
 
         clkevt.max_delta_ns = clockevent_delta2ns(0xfff0,
                         &clkevt);
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 9b1a66816aa6..5cf88e8427b1 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -2,3 +2,7 @@ obj-y	:= clock.o
 obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
 obj-$(CONFIG_ARCH_REALVIEW) += sched-clock.o
 obj-$(CONFIG_ARCH_VERSATILE) += sched-clock.o
+ifeq ($(CONFIG_LEDS_CLASS),y)
+obj-$(CONFIG_ARCH_REALVIEW) += leds.o
+obj-$(CONFIG_ARCH_VERSATILE) += leds.o
+endif
diff --git a/arch/arm/plat-versatile/leds.c b/arch/arm/plat-versatile/leds.c
new file mode 100644
index 000000000000..3169fa555ea6
--- /dev/null
+++ b/arch/arm/plat-versatile/leds.c
@@ -0,0 +1,103 @@
+/*
+ * Driver for the 8 user LEDs found on the RealViews and Versatiles
+ * Based on DaVinci's DM365 board code
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ * Author: Linus Walleij <triad@df.lth.se>
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+
+#ifdef VERSATILE_SYS_BASE
+#define LEDREG  (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
+#endif
+
+#ifdef REALVIEW_SYS_BASE
+#define LEDREG  (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
+#endif
+
+struct versatile_led {
+        struct led_classdev     cdev;
+        u8                      mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} versatile_leds[] = {
+        { "versatile:0", "heartbeat", },
+        { "versatile:1", "mmc0", },
+        { "versatile:2", },
+        { "versatile:3", },
+        { "versatile:4", },
+        { "versatile:5", },
+        { "versatile:6", },
+        { "versatile:7", },
+};
+
+static void versatile_led_set(struct led_classdev *cdev,
+                              enum led_brightness b)
+{
+        struct versatile_led *led = container_of(cdev,
+                                                 struct versatile_led, cdev);
+        u32 reg = readl(LEDREG);
+
+        if (b != LED_OFF)
+                reg |= led->mask;
+        else
+                reg &= ~led->mask;
+        writel(reg, LEDREG);
+}
+
+static enum led_brightness versatile_led_get(struct led_classdev *cdev)
+{
+        struct versatile_led *led = container_of(cdev,
+                                                 struct versatile_led, cdev);
+        u32 reg = readl(LEDREG);
+
+        return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
+
+static int __init versatile_leds_init(void)
+{
+        int i;
+
+        /* All ON */
+        writel(0xff, LEDREG);
+        for (i = 0; i < ARRAY_SIZE(versatile_leds); i++) {
+                struct versatile_led *led;
+
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+
+                led->cdev.name = versatile_leds[i].name;
+                led->cdev.brightness_set = versatile_led_set;
+                led->cdev.brightness_get = versatile_led_get;
+                led->cdev.default_trigger = versatile_leds[i].trigger;
+                led->mask = BIT(i);
+
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
+
+        return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(versatile_leds_init);
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 315a540c7ce5..8063a322c790 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -15,6 +15,7 @@
 #include <linux/sched.h>
 #include <linux/init.h>
 
+#include <asm/cputype.h>
 #include <asm/thread_notify.h>
 #include <asm/vfp.h>
 
@@ -549,10 +550,13 @@ static int __init vfp_init(void)
                 /*
                  * Check for the presence of the Advanced SIMD
                  * load/store instructions, integer and single
-                 * precision floating point operations.
+                 * precision floating point operations. Only check
+                 * for NEON if the hardware has the MVFR registers.
                  */
-                if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
-                        elf_hwcap |= HWCAP_NEON;
+                if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
+                        if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
+                                elf_hwcap |= HWCAP_NEON;
+                }
 #endif
         }
         return 0;