diff options
Diffstat (limited to 'arch/arm')
57 files changed, 1641 insertions, 961 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 48a0628d93e8..169db59f6bcb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -635,6 +635,7 @@ config ARCH_MSM | |||
635 | select HAVE_CLK | 635 | select HAVE_CLK |
636 | select GENERIC_CLOCKEVENTS | 636 | select GENERIC_CLOCKEVENTS |
637 | select ARCH_REQUIRE_GPIOLIB | 637 | select ARCH_REQUIRE_GPIOLIB |
638 | select CLKDEV_LOOKUP | ||
638 | help | 639 | help |
639 | Support for Qualcomm MSM/QSD based systems. This runs on the | 640 | Support for Qualcomm MSM/QSD based systems. This runs on the |
640 | apps processor of the MSM/QSD and depends on a shared memory | 641 | apps processor of the MSM/QSD and depends on a shared memory |
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 5d3d9ade12fb..1516896e8d17 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig | |||
@@ -45,7 +45,16 @@ config ARCH_MSM8X60 | |||
45 | select CPU_V7 | 45 | select CPU_V7 |
46 | select MSM_V2_TLMM | 46 | select MSM_V2_TLMM |
47 | select MSM_GPIOMUX | 47 | select MSM_GPIOMUX |
48 | select IOMMU_API | 48 | select MSM_SCM if SMP |
49 | |||
50 | config ARCH_MSM8960 | ||
51 | bool "MSM8960" | ||
52 | select ARCH_MSM_SCORPIONMP | ||
53 | select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3) | ||
54 | select ARM_GIC | ||
55 | select CPU_V7 | ||
56 | select MSM_V2_TLMM | ||
57 | select MSM_GPIOMUX | ||
49 | select MSM_SCM if SMP | 58 | select MSM_SCM if SMP |
50 | 59 | ||
51 | endchoice | 60 | endchoice |
@@ -125,11 +134,35 @@ config MACH_MSM8X60_FFA | |||
125 | help | 134 | help |
126 | Support for the Qualcomm MSM8x60 FFA eval board. | 135 | Support for the Qualcomm MSM8x60 FFA eval board. |
127 | 136 | ||
137 | config MACH_MSM8960_SIM | ||
138 | depends on ARCH_MSM8960 | ||
139 | bool "MSM8960 Simulator" | ||
140 | help | ||
141 | Support for the Qualcomm MSM8960 simulator. | ||
142 | |||
143 | config MACH_MSM8960_RUMI3 | ||
144 | depends on ARCH_MSM8960 | ||
145 | bool "MSM8960 RUMI3" | ||
146 | help | ||
147 | Support for the Qualcomm MSM8960 RUMI3 emulator. | ||
148 | |||
128 | endmenu | 149 | endmenu |
129 | 150 | ||
151 | config MSM_IOMMU | ||
152 | bool "MSM IOMMU Support" | ||
153 | depends on ARCH_MSM8X60 || ARCH_MSM8960 | ||
154 | select IOMMU_API | ||
155 | default n | ||
156 | help | ||
157 | Support for the IOMMUs found on certain Qualcomm SOCs. | ||
158 | These IOMMUs allow virtualization of the address space used by most | ||
159 | cores within the multimedia subsystem. | ||
160 | |||
161 | If unsure, say N here. | ||
162 | |||
130 | config IOMMU_PGTABLES_L2 | 163 | config IOMMU_PGTABLES_L2 |
131 | def_bool y | 164 | def_bool y |
132 | depends on ARCH_MSM8X60 && MMU && SMP && CPU_DCACHE_DISABLE=n | 165 | depends on MSM_IOMMU && MMU && SMP && CPU_DCACHE_DISABLE=n |
133 | 166 | ||
134 | config MSM_DEBUG_UART | 167 | config MSM_DEBUG_UART |
135 | int | 168 | int |
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 94195c190e13..9519fd28a025 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile | |||
@@ -1,21 +1,16 @@ | |||
1 | obj-y += io.o idle.o timer.o | 1 | obj-y += io.o idle.o timer.o |
2 | ifndef CONFIG_ARCH_MSM8X60 | 2 | obj-y += clock.o |
3 | obj-y += acpuclock-arm11.o | 3 | obj-$(CONFIG_DEBUG_FS) += clock-debug.o |
4 | obj-y += dma.o | ||
5 | endif | ||
6 | 4 | ||
7 | ifdef CONFIG_MSM_VIC | 5 | obj-$(CONFIG_MSM_VIC) += irq-vic.o |
8 | obj-y += irq-vic.o | 6 | obj-$(CONFIG_MSM_IOMMU) += iommu.o iommu_dev.o devices-iommu.o |
9 | else | 7 | |
10 | ifndef CONFIG_ARCH_MSM8X60 | 8 | obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o |
11 | obj-y += irq.o | 9 | obj-$(CONFIG_ARCH_MSM7X30) += dma.o |
12 | endif | 10 | obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o |
13 | endif | ||
14 | 11 | ||
15 | obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o | ||
16 | obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o | 12 | obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o |
17 | obj-$(CONFIG_MSM_PROC_COMM) += clock.o | 13 | |
18 | obj-$(CONFIG_ARCH_QSD8X50) += sirc.o | ||
19 | obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o | 14 | obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o |
20 | obj-$(CONFIG_MSM_SMD) += last_radio_log.o | 15 | obj-$(CONFIG_MSM_SMD) += last_radio_log.o |
21 | obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o | 16 | obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o |
@@ -29,12 +24,16 @@ obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o | |||
29 | obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o | 24 | obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o |
30 | obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o | 25 | obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o |
31 | obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o | 26 | obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o |
27 | obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o | ||
32 | 28 | ||
33 | obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o | 29 | obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o |
34 | obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o | 30 | obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o |
35 | obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o | 31 | obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o |
36 | ifdef CONFIG_MSM_V2_TLMM | 32 | ifdef CONFIG_MSM_V2_TLMM |
33 | ifndef CONFIG_ARCH_MSM8960 | ||
34 | # TODO: TLMM Mapping issues need to be resolved | ||
37 | obj-y += gpio-v2.o | 35 | obj-y += gpio-v2.o |
36 | endif | ||
38 | else | 37 | else |
39 | obj-y += gpio.o | 38 | obj-y += gpio.o |
40 | endif | 39 | endif |
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c index 75dabb16c802..18a3c97bc863 100644 --- a/arch/arm/mach-msm/board-halibut.c +++ b/arch/arm/mach-msm/board-halibut.c | |||
@@ -93,8 +93,6 @@ static void __init halibut_map_io(void) | |||
93 | } | 93 | } |
94 | 94 | ||
95 | MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)") | 95 | MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)") |
96 | #ifdef CONFIG_MSM_DEBUG_UART | ||
97 | #endif | ||
98 | .boot_params = 0x10000100, | 96 | .boot_params = 0x10000100, |
99 | .fixup = halibut_fixup, | 97 | .fixup = halibut_fixup, |
100 | .map_io = halibut_map_io, | 98 | .map_io = halibut_map_io, |
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c index ef3ebf2f763b..7a9a03eb189c 100644 --- a/arch/arm/mach-msm/board-mahimahi.c +++ b/arch/arm/mach-msm/board-mahimahi.c | |||
@@ -74,8 +74,6 @@ static void __init mahimahi_map_io(void) | |||
74 | extern struct sys_timer msm_timer; | 74 | extern struct sys_timer msm_timer; |
75 | 75 | ||
76 | MACHINE_START(MAHIMAHI, "mahimahi") | 76 | MACHINE_START(MAHIMAHI, "mahimahi") |
77 | #ifdef CONFIG_MSM_DEBUG_UART | ||
78 | #endif | ||
79 | .boot_params = 0x20000100, | 77 | .boot_params = 0x20000100, |
80 | .fixup = mahimahi_fixup, | 78 | .fixup = mahimahi_fixup, |
81 | .map_io = mahimahi_map_io, | 79 | .map_io = mahimahi_map_io, |
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c index 08fcd40a8cbd..c03f269e2e4b 100644 --- a/arch/arm/mach-msm/board-msm7x27.c +++ b/arch/arm/mach-msm/board-msm7x27.c | |||
@@ -130,8 +130,6 @@ static void __init msm7x2x_map_io(void) | |||
130 | } | 130 | } |
131 | 131 | ||
132 | MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF") | 132 | MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF") |
133 | #ifdef CONFIG_MSM_DEBUG_UART | ||
134 | #endif | ||
135 | .boot_params = PLAT_PHYS_OFFSET + 0x100, | 133 | .boot_params = PLAT_PHYS_OFFSET + 0x100, |
136 | .map_io = msm7x2x_map_io, | 134 | .map_io = msm7x2x_map_io, |
137 | .init_irq = msm7x2x_init_irq, | 135 | .init_irq = msm7x2x_init_irq, |
@@ -140,8 +138,6 @@ MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF") | |||
140 | MACHINE_END | 138 | MACHINE_END |
141 | 139 | ||
142 | MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA") | 140 | MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA") |
143 | #ifdef CONFIG_MSM_DEBUG_UART | ||
144 | #endif | ||
145 | .boot_params = PLAT_PHYS_OFFSET + 0x100, | 141 | .boot_params = PLAT_PHYS_OFFSET + 0x100, |
146 | .map_io = msm7x2x_map_io, | 142 | .map_io = msm7x2x_map_io, |
147 | .init_irq = msm7x2x_init_irq, | 143 | .init_irq = msm7x2x_init_irq, |
@@ -150,8 +146,6 @@ MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA") | |||
150 | MACHINE_END | 146 | MACHINE_END |
151 | 147 | ||
152 | MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF") | 148 | MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF") |
153 | #ifdef CONFIG_MSM_DEBUG_UART | ||
154 | #endif | ||
155 | .boot_params = PLAT_PHYS_OFFSET + 0x100, | 149 | .boot_params = PLAT_PHYS_OFFSET + 0x100, |
156 | .map_io = msm7x2x_map_io, | 150 | .map_io = msm7x2x_map_io, |
157 | .init_irq = msm7x2x_init_irq, | 151 | .init_irq = msm7x2x_init_irq, |
@@ -160,8 +154,6 @@ MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF") | |||
160 | MACHINE_END | 154 | MACHINE_END |
161 | 155 | ||
162 | MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA") | 156 | MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA") |
163 | #ifdef CONFIG_MSM_DEBUG_UART | ||
164 | #endif | ||
165 | .boot_params = PLAT_PHYS_OFFSET + 0x100, | 157 | .boot_params = PLAT_PHYS_OFFSET + 0x100, |
166 | .map_io = msm7x2x_map_io, | 158 | .map_io = msm7x2x_map_io, |
167 | .init_irq = msm7x2x_init_irq, | 159 | .init_irq = msm7x2x_init_irq, |
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index 25db8fd71a70..b7a84966b711 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | #include <linux/smsc911x.h> | 24 | #include <linux/smsc911x.h> |
25 | #include <linux/usb/msm_hsusb.h> | 25 | #include <linux/usb/msm_hsusb.h> |
26 | #include <linux/clkdev.h> | ||
26 | 27 | ||
27 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
28 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
@@ -36,6 +37,7 @@ | |||
36 | 37 | ||
37 | #include <mach/vreg.h> | 38 | #include <mach/vreg.h> |
38 | #include "devices.h" | 39 | #include "devices.h" |
40 | #include "gpiomux.h" | ||
39 | #include "proc_comm.h" | 41 | #include "proc_comm.h" |
40 | 42 | ||
41 | extern struct sys_timer msm_timer; | 43 | extern struct sys_timer msm_timer; |
@@ -52,6 +54,27 @@ static struct msm_otg_platform_data msm_otg_pdata = { | |||
52 | .otg_control = OTG_PHY_CONTROL, | 54 | .otg_control = OTG_PHY_CONTROL, |
53 | }; | 55 | }; |
54 | 56 | ||
57 | struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { | ||
58 | #ifdef CONFIG_SERIAL_MSM_CONSOLE | ||
59 | [49] = { /* UART2 RFR */ | ||
60 | .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | | ||
61 | GPIOMUX_FUNC_2 | GPIOMUX_VALID, | ||
62 | }, | ||
63 | [50] = { /* UART2 CTS */ | ||
64 | .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | | ||
65 | GPIOMUX_FUNC_2 | GPIOMUX_VALID, | ||
66 | }, | ||
67 | [51] = { /* UART2 RX */ | ||
68 | .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | | ||
69 | GPIOMUX_FUNC_2 | GPIOMUX_VALID, | ||
70 | }, | ||
71 | [52] = { /* UART2 TX */ | ||
72 | .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | | ||
73 | GPIOMUX_FUNC_2 | GPIOMUX_VALID, | ||
74 | }, | ||
75 | #endif | ||
76 | }; | ||
77 | |||
55 | static struct platform_device *devices[] __initdata = { | 78 | static struct platform_device *devices[] __initdata = { |
56 | #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER) | 79 | #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER) |
57 | &msm_device_uart2, | 80 | &msm_device_uart2, |
@@ -83,8 +106,6 @@ static void __init msm7x30_map_io(void) | |||
83 | } | 106 | } |
84 | 107 | ||
85 | MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") | 108 | MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") |
86 | #ifdef CONFIG_MSM_DEBUG_UART | ||
87 | #endif | ||
88 | .boot_params = PLAT_PHYS_OFFSET + 0x100, | 109 | .boot_params = PLAT_PHYS_OFFSET + 0x100, |
89 | .map_io = msm7x30_map_io, | 110 | .map_io = msm7x30_map_io, |
90 | .init_irq = msm7x30_init_irq, | 111 | .init_irq = msm7x30_init_irq, |
@@ -93,8 +114,6 @@ MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") | |||
93 | MACHINE_END | 114 | MACHINE_END |
94 | 115 | ||
95 | MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") | 116 | MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") |
96 | #ifdef CONFIG_MSM_DEBUG_UART | ||
97 | #endif | ||
98 | .boot_params = PLAT_PHYS_OFFSET + 0x100, | 117 | .boot_params = PLAT_PHYS_OFFSET + 0x100, |
99 | .map_io = msm7x30_map_io, | 118 | .map_io = msm7x30_map_io, |
100 | .init_irq = msm7x30_init_irq, | 119 | .init_irq = msm7x30_init_irq, |
@@ -103,8 +122,6 @@ MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") | |||
103 | MACHINE_END | 122 | MACHINE_END |
104 | 123 | ||
105 | MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") | 124 | MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") |
106 | #ifdef CONFIG_MSM_DEBUG_UART | ||
107 | #endif | ||
108 | .boot_params = PLAT_PHYS_OFFSET + 0x100, | 125 | .boot_params = PLAT_PHYS_OFFSET + 0x100, |
109 | .map_io = msm7x30_map_io, | 126 | .map_io = msm7x30_map_io, |
110 | .init_irq = msm7x30_init_irq, | 127 | .init_irq = msm7x30_init_irq, |
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c new file mode 100644 index 000000000000..1993721d472e --- /dev/null +++ b/arch/arm/mach-msm/board-msm8960.c | |||
@@ -0,0 +1,91 @@ | |||
1 | /* Copyright (c) 2011, Code Aurora Forum. All rights reserved. | ||
2 | * | ||
3 | * This program is free software; you can redistribute it and/or modify | ||
4 | * it under the terms of the GNU General Public License version 2 and | ||
5 | * only version 2 as published by the Free Software Foundation. | ||
6 | * | ||
7 | * This program is distributed in the hope that it will be useful, | ||
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | * GNU General Public License for more details. | ||
11 | * | ||
12 | * You should have received a copy of the GNU General Public License | ||
13 | * along with this program; if not, write to the Free Software | ||
14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
15 | * 02110-1301, USA. | ||
16 | * | ||
17 | */ | ||
18 | #include <linux/kernel.h> | ||
19 | #include <linux/platform_device.h> | ||
20 | #include <linux/io.h> | ||
21 | #include <linux/irq.h> | ||
22 | #include <linux/clkdev.h> | ||
23 | |||
24 | #include <asm/mach-types.h> | ||
25 | #include <asm/mach/arch.h> | ||
26 | #include <asm/hardware/gic.h> | ||
27 | |||
28 | #include <mach/board.h> | ||
29 | #include <mach/msm_iomap.h> | ||
30 | |||
31 | #include "devices.h" | ||
32 | |||
33 | static void __init msm8960_map_io(void) | ||
34 | { | ||
35 | msm_map_msm8960_io(); | ||
36 | } | ||
37 | |||
38 | static void __init msm8960_init_irq(void) | ||
39 | { | ||
40 | unsigned int i; | ||
41 | gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, | ||
42 | (void *)MSM_QGIC_CPU_BASE); | ||
43 | |||
44 | /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ | ||
45 | writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); | ||
46 | |||
47 | if (machine_is_msm8960_rumi3()) | ||
48 | writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); | ||
49 | |||
50 | /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet | ||
51 | * as they are configured as level, which does not play nice with | ||
52 | * handle_percpu_irq. | ||
53 | */ | ||
54 | for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { | ||
55 | if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) | ||
56 | set_irq_handler(i, handle_percpu_irq); | ||
57 | } | ||
58 | } | ||
59 | |||
60 | static struct platform_device *sim_devices[] __initdata = { | ||
61 | &msm8960_device_uart_gsbi2, | ||
62 | }; | ||
63 | |||
64 | static struct platform_device *rumi3_devices[] __initdata = { | ||
65 | &msm8960_device_uart_gsbi5, | ||
66 | }; | ||
67 | |||
68 | static void __init msm8960_sim_init(void) | ||
69 | { | ||
70 | platform_add_devices(sim_devices, ARRAY_SIZE(sim_devices)); | ||
71 | } | ||
72 | |||
73 | static void __init msm8960_rumi3_init(void) | ||
74 | { | ||
75 | platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices)); | ||
76 | } | ||
77 | |||
78 | MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR") | ||
79 | .map_io = msm8960_map_io, | ||
80 | .init_irq = msm8960_init_irq, | ||
81 | .timer = &msm_timer, | ||
82 | .init_machine = msm8960_sim_init, | ||
83 | MACHINE_END | ||
84 | |||
85 | MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3") | ||
86 | .map_io = msm8960_map_io, | ||
87 | .init_irq = msm8960_init_irq, | ||
88 | .timer = &msm_timer, | ||
89 | .init_machine = msm8960_rumi3_init, | ||
90 | MACHINE_END | ||
91 | |||
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index 9b5eb2b4ae1b..b3c55f138fce 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c | |||
@@ -28,10 +28,6 @@ | |||
28 | #include <mach/board.h> | 28 | #include <mach/board.h> |
29 | #include <mach/msm_iomap.h> | 29 | #include <mach/msm_iomap.h> |
30 | 30 | ||
31 | unsigned long clk_get_max_axi_khz(void) | ||
32 | { | ||
33 | return 0; | ||
34 | } | ||
35 | 31 | ||
36 | static void __init msm8x60_map_io(void) | 32 | static void __init msm8x60_map_io(void) |
37 | { | 33 | { |
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index 15c2bbd2ef81..7f568611547e 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c | |||
@@ -1,4 +1,4 @@ | |||
1 | /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. | 1 | /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. |
2 | * | 2 | * |
3 | * This program is free software; you can redistribute it and/or modify | 3 | * This program is free software; you can redistribute it and/or modify |
4 | * it under the terms of the GNU General Public License version 2 and | 4 | * it under the terms of the GNU General Public License version 2 and |
@@ -21,6 +21,8 @@ | |||
21 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
23 | #include <linux/usb/msm_hsusb.h> | 23 | #include <linux/usb/msm_hsusb.h> |
24 | #include <linux/err.h> | ||
25 | #include <linux/clkdev.h> | ||
24 | 26 | ||
25 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
26 | #include <asm/mach/arch.h> | 28 | #include <asm/mach/arch.h> |
@@ -31,6 +33,8 @@ | |||
31 | #include <mach/irqs.h> | 33 | #include <mach/irqs.h> |
32 | #include <mach/sirc.h> | 34 | #include <mach/sirc.h> |
33 | #include <mach/gpio.h> | 35 | #include <mach/gpio.h> |
36 | #include <mach/vreg.h> | ||
37 | #include <mach/mmc.h> | ||
34 | 38 | ||
35 | #include "devices.h" | 39 | #include "devices.h" |
36 | 40 | ||
@@ -95,6 +99,81 @@ static struct platform_device *devices[] __initdata = { | |||
95 | &msm_device_hsusb_host, | 99 | &msm_device_hsusb_host, |
96 | }; | 100 | }; |
97 | 101 | ||
102 | static struct msm_mmc_gpio sdc1_gpio_cfg[] = { | ||
103 | {51, "sdc1_dat_3"}, | ||
104 | {52, "sdc1_dat_2"}, | ||
105 | {53, "sdc1_dat_1"}, | ||
106 | {54, "sdc1_dat_0"}, | ||
107 | {55, "sdc1_cmd"}, | ||
108 | {56, "sdc1_clk"} | ||
109 | }; | ||
110 | |||
111 | static struct vreg *vreg_mmc; | ||
112 | static unsigned long vreg_sts; | ||
113 | |||
114 | static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd) | ||
115 | { | ||
116 | int rc = 0; | ||
117 | struct platform_device *pdev; | ||
118 | |||
119 | pdev = container_of(dv, struct platform_device, dev); | ||
120 | |||
121 | if (vdd == 0) { | ||
122 | if (!vreg_sts) | ||
123 | return 0; | ||
124 | |||
125 | clear_bit(pdev->id, &vreg_sts); | ||
126 | |||
127 | if (!vreg_sts) { | ||
128 | rc = vreg_disable(vreg_mmc); | ||
129 | if (rc) | ||
130 | pr_err("vreg_mmc disable failed for slot " | ||
131 | "%d: %d\n", pdev->id, rc); | ||
132 | } | ||
133 | return 0; | ||
134 | } | ||
135 | |||
136 | if (!vreg_sts) { | ||
137 | rc = vreg_set_level(vreg_mmc, 2900); | ||
138 | if (rc) | ||
139 | pr_err("vreg_mmc set level failed for slot %d: %d\n", | ||
140 | pdev->id, rc); | ||
141 | rc = vreg_enable(vreg_mmc); | ||
142 | if (rc) | ||
143 | pr_err("vreg_mmc enable failed for slot %d: %d\n", | ||
144 | pdev->id, rc); | ||
145 | } | ||
146 | set_bit(pdev->id, &vreg_sts); | ||
147 | return 0; | ||
148 | } | ||
149 | |||
150 | static struct msm_mmc_gpio_data sdc1_gpio = { | ||
151 | .gpio = sdc1_gpio_cfg, | ||
152 | .size = ARRAY_SIZE(sdc1_gpio_cfg), | ||
153 | }; | ||
154 | |||
155 | static struct msm_mmc_platform_data qsd8x50_sdc1_data = { | ||
156 | .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, | ||
157 | .translate_vdd = msm_sdcc_setup_power, | ||
158 | .gpio_data = &sdc1_gpio, | ||
159 | }; | ||
160 | |||
161 | static void __init qsd8x50_init_mmc(void) | ||
162 | { | ||
163 | if (machine_is_qsd8x50_ffa() || machine_is_qsd8x50a_ffa()) | ||
164 | vreg_mmc = vreg_get(NULL, "gp6"); | ||
165 | else | ||
166 | vreg_mmc = vreg_get(NULL, "gp5"); | ||
167 | |||
168 | if (IS_ERR(vreg_mmc)) { | ||
169 | pr_err("vreg get for vreg_mmc failed (%ld)\n", | ||
170 | PTR_ERR(vreg_mmc)); | ||
171 | return; | ||
172 | } | ||
173 | |||
174 | msm_add_sdcc(1, &qsd8x50_sdc1_data, 0, 0); | ||
175 | } | ||
176 | |||
98 | static void __init qsd8x50_map_io(void) | 177 | static void __init qsd8x50_map_io(void) |
99 | { | 178 | { |
100 | msm_map_qsd8x50_io(); | 179 | msm_map_qsd8x50_io(); |
@@ -113,11 +192,10 @@ static void __init qsd8x50_init(void) | |||
113 | msm_device_hsusb.dev.parent = &msm_device_otg.dev; | 192 | msm_device_hsusb.dev.parent = &msm_device_otg.dev; |
114 | msm_device_hsusb_host.dev.parent = &msm_device_otg.dev; | 193 | msm_device_hsusb_host.dev.parent = &msm_device_otg.dev; |
115 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 194 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
195 | qsd8x50_init_mmc(); | ||
116 | } | 196 | } |
117 | 197 | ||
118 | MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") | 198 | MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") |
119 | #ifdef CONFIG_MSM_DEBUG_UART | ||
120 | #endif | ||
121 | .boot_params = PLAT_PHYS_OFFSET + 0x100, | 199 | .boot_params = PLAT_PHYS_OFFSET + 0x100, |
122 | .map_io = qsd8x50_map_io, | 200 | .map_io = qsd8x50_map_io, |
123 | .init_irq = qsd8x50_init_irq, | 201 | .init_irq = qsd8x50_init_irq, |
@@ -126,8 +204,6 @@ MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") | |||
126 | MACHINE_END | 204 | MACHINE_END |
127 | 205 | ||
128 | MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") | 206 | MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") |
129 | #ifdef CONFIG_MSM_DEBUG_UART | ||
130 | #endif | ||
131 | .boot_params = PLAT_PHYS_OFFSET + 0x100, | 207 | .boot_params = PLAT_PHYS_OFFSET + 0x100, |
132 | .map_io = qsd8x50_map_io, | 208 | .map_io = qsd8x50_map_io, |
133 | .init_irq = qsd8x50_init_irq, | 209 | .init_irq = qsd8x50_init_irq, |
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c index 83604f526f0f..68f930f07d77 100644 --- a/arch/arm/mach-msm/board-sapphire.c +++ b/arch/arm/mach-msm/board-sapphire.c | |||
@@ -105,8 +105,6 @@ static void __init sapphire_map_io(void) | |||
105 | 105 | ||
106 | MACHINE_START(SAPPHIRE, "sapphire") | 106 | MACHINE_START(SAPPHIRE, "sapphire") |
107 | /* Maintainer: Brian Swetland <swetland@google.com> */ | 107 | /* Maintainer: Brian Swetland <swetland@google.com> */ |
108 | #ifdef CONFIG_MSM_DEBUG_UART | ||
109 | #endif | ||
110 | .boot_params = PLAT_PHYS_OFFSET + 0x100, | 108 | .boot_params = PLAT_PHYS_OFFSET + 0x100, |
111 | .fixup = sapphire_fixup, | 109 | .fixup = sapphire_fixup, |
112 | .map_io = sapphire_map_io, | 110 | .map_io = sapphire_map_io, |
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c index a604ec1e44bf..31117a4499c4 100644 --- a/arch/arm/mach-msm/board-trout-gpio.c +++ b/arch/arm/mach-msm/board-trout-gpio.c | |||
@@ -74,8 +74,6 @@ static int msm_gpiolib_direction_output(struct gpio_chip *chip, | |||
74 | 74 | ||
75 | static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | 75 | static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
76 | { | 76 | { |
77 | struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip); | ||
78 | |||
79 | return TROUT_GPIO_TO_INT(offset + chip->base); | 77 | return TROUT_GPIO_TO_INT(offset + chip->base); |
80 | } | 78 | } |
81 | 79 | ||
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c index 73f146066542..814386772c66 100644 --- a/arch/arm/mach-msm/board-trout.c +++ b/arch/arm/mach-msm/board-trout.c | |||
@@ -17,6 +17,7 @@ | |||
17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
19 | #include <linux/platform_device.h> | 19 | #include <linux/platform_device.h> |
20 | #include <linux/clkdev.h> | ||
20 | 21 | ||
21 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
22 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
@@ -92,8 +93,6 @@ static void __init trout_map_io(void) | |||
92 | } | 93 | } |
93 | 94 | ||
94 | MACHINE_START(TROUT, "HTC Dream") | 95 | MACHINE_START(TROUT, "HTC Dream") |
95 | #ifdef CONFIG_MSM_DEBUG_UART | ||
96 | #endif | ||
97 | .boot_params = 0x10000100, | 96 | .boot_params = 0x10000100, |
98 | .fixup = trout_fixup, | 97 | .fixup = trout_fixup, |
99 | .map_io = trout_map_io, | 98 | .map_io = trout_map_io, |
diff --git a/arch/arm/mach-msm/clock-7x30.h b/arch/arm/mach-msm/clock-7x30.h index e16f72f32829..14104453688b 100644 --- a/arch/arm/mach-msm/clock-7x30.h +++ b/arch/arm/mach-msm/clock-7x30.h | |||
@@ -1,30 +1,13 @@ | |||
1 | /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. | 1 | /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. |
2 | * | 2 | * |
3 | * Redistribution and use in source and binary forms, with or without | 3 | * This program is free software; you can redistribute it and/or modify |
4 | * modification, are permitted provided that the following conditions are | 4 | * it under the terms of the GNU General Public License version 2 and |
5 | * met: | 5 | * only version 2 as published by the Free Software Foundation. |
6 | * * Redistributions of source code must retain the above copyright | ||
7 | * notice, this list of conditions and the following disclaimer. | ||
8 | * * Redistributions in binary form must reproduce the above | ||
9 | * copyright notice, this list of conditions and the following | ||
10 | * disclaimer in the documentation and/or other materials provided | ||
11 | * with the distribution. | ||
12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its | ||
13 | * contributors may be used to endorse or promote products derived | ||
14 | * from this software without specific prior written permission. | ||
15 | * | ||
16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | ||
17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT | ||
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS | ||
20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
27 | * | 6 | * |
7 | * This program is distributed in the hope that it will be useful, | ||
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | * GNU General Public License for more details. | ||
28 | */ | 11 | */ |
29 | 12 | ||
30 | #ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H | 13 | #ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H |
@@ -147,22 +130,26 @@ void pll_disable(uint32_t pll); | |||
147 | extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable); | 130 | extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable); |
148 | 131 | ||
149 | #define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) { \ | 132 | #define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) { \ |
150 | .name = clk_name, \ | 133 | .con_id = clk_name, \ |
151 | .id = L_7X30_##clk_id, \ | 134 | .dev_id = clk_dev, \ |
152 | .remote_id = P_##clk_id, \ | 135 | .clk = &(struct clk){ \ |
153 | .flags = clk_flags, \ | 136 | .id = L_7X30_##clk_id, \ |
154 | .dev = clk_dev, \ | 137 | .remote_id = P_##clk_id, \ |
155 | .dbg_name = #clk_id, \ | 138 | .flags = clk_flags, \ |
139 | .dbg_name = #clk_id, \ | ||
140 | }, \ | ||
156 | } | 141 | } |
157 | 142 | ||
158 | #define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) { \ | 143 | #define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) { \ |
159 | .name = clk_name, \ | 144 | .con_id = clk_name, \ |
160 | .id = L_7X30_##l_id, \ | 145 | .dev_id = clk_dev, \ |
161 | .remote_id = P_##r_id, \ | 146 | .clk = &(struct clk){ \ |
162 | .flags = clk_flags, \ | 147 | .id = L_7X30_##l_id, \ |
163 | .dev = clk_dev, \ | 148 | .remote_id = P_##r_id, \ |
164 | .dbg_name = #l_id, \ | 149 | .flags = clk_flags, \ |
150 | .dbg_name = #l_id, \ | ||
151 | .ops = &clk_ops_pcom, \ | ||
152 | }, \ | ||
165 | } | 153 | } |
166 | 154 | ||
167 | #endif | 155 | #endif |
168 | |||
diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c new file mode 100644 index 000000000000..4886404d42f5 --- /dev/null +++ b/arch/arm/mach-msm/clock-debug.c | |||
@@ -0,0 +1,130 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2007 Google, Inc. | ||
3 | * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved. | ||
4 | * | ||
5 | * This software is licensed under the terms of the GNU General Public | ||
6 | * License version 2, as published by the Free Software Foundation, and | ||
7 | * may be copied, distributed, and modified under those terms. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/module.h> | ||
18 | #include <linux/ctype.h> | ||
19 | #include <linux/debugfs.h> | ||
20 | #include <linux/clk.h> | ||
21 | #include "clock.h" | ||
22 | |||
23 | static int clock_debug_rate_set(void *data, u64 val) | ||
24 | { | ||
25 | struct clk *clock = data; | ||
26 | int ret; | ||
27 | |||
28 | /* Only increases to max rate will succeed, but that's actually good | ||
29 | * for debugging purposes so we don't check for error. */ | ||
30 | if (clock->flags & CLK_MAX) | ||
31 | clk_set_max_rate(clock, val); | ||
32 | if (clock->flags & CLK_MIN) | ||
33 | ret = clk_set_min_rate(clock, val); | ||
34 | else | ||
35 | ret = clk_set_rate(clock, val); | ||
36 | if (ret != 0) | ||
37 | printk(KERN_ERR "clk_set%s_rate failed (%d)\n", | ||
38 | (clock->flags & CLK_MIN) ? "_min" : "", ret); | ||
39 | return ret; | ||
40 | } | ||
41 | |||
42 | static int clock_debug_rate_get(void *data, u64 *val) | ||
43 | { | ||
44 | struct clk *clock = data; | ||
45 | *val = clk_get_rate(clock); | ||
46 | return 0; | ||
47 | } | ||
48 | |||
49 | DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get, | ||
50 | clock_debug_rate_set, "%llu\n"); | ||
51 | |||
52 | static int clock_debug_enable_set(void *data, u64 val) | ||
53 | { | ||
54 | struct clk *clock = data; | ||
55 | int rc = 0; | ||
56 | |||
57 | if (val) | ||
58 | rc = clock->ops->enable(clock->id); | ||
59 | else | ||
60 | clock->ops->disable(clock->id); | ||
61 | |||
62 | return rc; | ||
63 | } | ||
64 | |||
65 | static int clock_debug_enable_get(void *data, u64 *val) | ||
66 | { | ||
67 | struct clk *clock = data; | ||
68 | |||
69 | *val = clock->ops->is_enabled(clock->id); | ||
70 | |||
71 | return 0; | ||
72 | } | ||
73 | |||
74 | DEFINE_SIMPLE_ATTRIBUTE(clock_enable_fops, clock_debug_enable_get, | ||
75 | clock_debug_enable_set, "%llu\n"); | ||
76 | |||
77 | static int clock_debug_local_get(void *data, u64 *val) | ||
78 | { | ||
79 | struct clk *clock = data; | ||
80 | |||
81 | *val = clock->ops->is_local(clock->id); | ||
82 | |||
83 | return 0; | ||
84 | } | ||
85 | |||
86 | DEFINE_SIMPLE_ATTRIBUTE(clock_local_fops, clock_debug_local_get, | ||
87 | NULL, "%llu\n"); | ||
88 | |||
89 | static struct dentry *debugfs_base; | ||
90 | |||
91 | int __init clock_debug_init(void) | ||
92 | { | ||
93 | debugfs_base = debugfs_create_dir("clk", NULL); | ||
94 | if (!debugfs_base) | ||
95 | return -ENOMEM; | ||
96 | return 0; | ||
97 | } | ||
98 | |||
99 | int __init clock_debug_add(struct clk *clock) | ||
100 | { | ||
101 | char temp[50], *ptr; | ||
102 | struct dentry *clk_dir; | ||
103 | |||
104 | if (!debugfs_base) | ||
105 | return -ENOMEM; | ||
106 | |||
107 | strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1); | ||
108 | for (ptr = temp; *ptr; ptr++) | ||
109 | *ptr = tolower(*ptr); | ||
110 | |||
111 | clk_dir = debugfs_create_dir(temp, debugfs_base); | ||
112 | if (!clk_dir) | ||
113 | return -ENOMEM; | ||
114 | |||
115 | if (!debugfs_create_file("rate", S_IRUGO | S_IWUSR, clk_dir, | ||
116 | clock, &clock_rate_fops)) | ||
117 | goto error; | ||
118 | |||
119 | if (!debugfs_create_file("enable", S_IRUGO | S_IWUSR, clk_dir, | ||
120 | clock, &clock_enable_fops)) | ||
121 | goto error; | ||
122 | |||
123 | if (!debugfs_create_file("is_local", S_IRUGO, clk_dir, clock, | ||
124 | &clock_local_fops)) | ||
125 | goto error; | ||
126 | return 0; | ||
127 | error: | ||
128 | debugfs_remove_recursive(clk_dir); | ||
129 | return -ENOMEM; | ||
130 | } | ||
diff --git a/arch/arm/mach-msm/clock-dummy.c b/arch/arm/mach-msm/clock-dummy.c deleted file mode 100644 index 1250d22082ee..000000000000 --- a/arch/arm/mach-msm/clock-dummy.c +++ /dev/null | |||
@@ -1,54 +0,0 @@ | |||
1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | ||
2 | * | ||
3 | * This program is free software; you can redistribute it and/or modify | ||
4 | * it under the terms of the GNU General Public License version 2 and | ||
5 | * only version 2 as published by the Free Software Foundation. | ||
6 | * | ||
7 | * This program is distributed in the hope that it will be useful, | ||
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | * GNU General Public License for more details. | ||
11 | * | ||
12 | * You should have received a copy of the GNU General Public License | ||
13 | * along with this program; if not, write to the Free Software | ||
14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
15 | * 02110-1301, USA. | ||
16 | * | ||
17 | */ | ||
18 | #include <linux/clk.h> | ||
19 | #include <linux/err.h> | ||
20 | #include <linux/module.h> | ||
21 | |||
22 | struct clk *clk_get(struct device *dev, const char *id) | ||
23 | { | ||
24 | return ERR_PTR(-ENOENT); | ||
25 | } | ||
26 | EXPORT_SYMBOL(clk_get); | ||
27 | |||
28 | int clk_enable(struct clk *clk) | ||
29 | { | ||
30 | return -ENOENT; | ||
31 | } | ||
32 | EXPORT_SYMBOL(clk_enable); | ||
33 | |||
34 | void clk_disable(struct clk *clk) | ||
35 | { | ||
36 | } | ||
37 | EXPORT_SYMBOL(clk_disable); | ||
38 | |||
39 | unsigned long clk_get_rate(struct clk *clk) | ||
40 | { | ||
41 | return 0; | ||
42 | } | ||
43 | EXPORT_SYMBOL(clk_get_rate); | ||
44 | |||
45 | int clk_set_rate(struct clk *clk, unsigned long rate) | ||
46 | { | ||
47 | return -ENOENT; | ||
48 | } | ||
49 | EXPORT_SYMBOL(clk_set_rate); | ||
50 | |||
51 | void clk_put(struct clk *clk) | ||
52 | { | ||
53 | } | ||
54 | EXPORT_SYMBOL(clk_put); | ||
diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c index a3b45627eb4a..63b711311086 100644 --- a/arch/arm/mach-msm/clock-pcom.c +++ b/arch/arm/mach-msm/clock-pcom.c | |||
@@ -20,6 +20,7 @@ | |||
20 | 20 | ||
21 | #include "proc_comm.h" | 21 | #include "proc_comm.h" |
22 | #include "clock.h" | 22 | #include "clock.h" |
23 | #include "clock-pcom.h" | ||
23 | 24 | ||
24 | /* | 25 | /* |
25 | * glue for the proc_comm interface | 26 | * glue for the proc_comm interface |
@@ -116,6 +117,11 @@ long pc_clk_round_rate(unsigned id, unsigned rate) | |||
116 | return rate; | 117 | return rate; |
117 | } | 118 | } |
118 | 119 | ||
120 | static bool pc_clk_is_local(unsigned id) | ||
121 | { | ||
122 | return false; | ||
123 | } | ||
124 | |||
119 | struct clk_ops clk_ops_pcom = { | 125 | struct clk_ops clk_ops_pcom = { |
120 | .enable = pc_clk_enable, | 126 | .enable = pc_clk_enable, |
121 | .disable = pc_clk_disable, | 127 | .disable = pc_clk_disable, |
@@ -128,4 +134,5 @@ struct clk_ops clk_ops_pcom = { | |||
128 | .get_rate = pc_clk_get_rate, | 134 | .get_rate = pc_clk_get_rate, |
129 | .is_enabled = pc_clk_is_enabled, | 135 | .is_enabled = pc_clk_is_enabled, |
130 | .round_rate = pc_clk_round_rate, | 136 | .round_rate = pc_clk_round_rate, |
137 | .is_local = pc_clk_is_local, | ||
131 | }; | 138 | }; |
diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h index 17d027b23501..974d0032f3a3 100644 --- a/arch/arm/mach-msm/clock-pcom.h +++ b/arch/arm/mach-msm/clock-pcom.h | |||
@@ -1,30 +1,13 @@ | |||
1 | /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. | 1 | /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. |
2 | * | 2 | * |
3 | * Redistribution and use in source and binary forms, with or without | 3 | * This program is free software; you can redistribute it and/or modify |
4 | * modification, are permitted provided that the following conditions are | 4 | * it under the terms of the GNU General Public License version 2 and |
5 | * met: | 5 | * only version 2 as published by the Free Software Foundation. |
6 | * * Redistributions of source code must retain the above copyright | ||
7 | * notice, this list of conditions and the following disclaimer. | ||
8 | * * Redistributions in binary form must reproduce the above | ||
9 | * copyright notice, this list of conditions and the following | ||
10 | * disclaimer in the documentation and/or other materials provided | ||
11 | * with the distribution. | ||
12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its | ||
13 | * contributors may be used to endorse or promote products derived | ||
14 | * from this software without specific prior written permission. | ||
15 | * | ||
16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | ||
17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT | ||
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS | ||
20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
27 | * | 6 | * |
7 | * This program is distributed in the hope that it will be useful, | ||
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | * GNU General Public License for more details. | ||
28 | */ | 11 | */ |
29 | 12 | ||
30 | #ifndef __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H | 13 | #ifndef __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H |
@@ -132,8 +115,10 @@ | |||
132 | #define P_CSI1_P_CLK 97 | 115 | #define P_CSI1_P_CLK 97 |
133 | #define P_GSBI_CLK 98 | 116 | #define P_GSBI_CLK 98 |
134 | #define P_GSBI_P_CLK 99 | 117 | #define P_GSBI_P_CLK 99 |
118 | #define P_CE_CLK 100 /* Crypto engine */ | ||
119 | #define P_CODEC_SSBI_CLK 101 | ||
135 | 120 | ||
136 | #define P_NR_CLKS 100 | 121 | #define P_NR_CLKS 102 |
137 | 122 | ||
138 | struct clk_ops; | 123 | struct clk_ops; |
139 | extern struct clk_ops clk_ops_pcom; | 124 | extern struct clk_ops clk_ops_pcom; |
@@ -141,13 +126,15 @@ extern struct clk_ops clk_ops_pcom; | |||
141 | int pc_clk_reset(unsigned id, enum clk_reset_action action); | 126 | int pc_clk_reset(unsigned id, enum clk_reset_action action); |
142 | 127 | ||
143 | #define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) { \ | 128 | #define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) { \ |
144 | .name = clk_name, \ | 129 | .con_id = clk_name, \ |
145 | .id = P_##clk_id, \ | 130 | .dev_id = clk_dev, \ |
146 | .remote_id = P_##clk_id, \ | 131 | .clk = &(struct clk){ \ |
147 | .ops = &clk_ops_pcom, \ | 132 | .id = P_##clk_id, \ |
148 | .flags = clk_flags, \ | 133 | .remote_id = P_##clk_id, \ |
149 | .dev = clk_dev, \ | 134 | .ops = &clk_ops_pcom, \ |
150 | .dbg_name = #clk_id, \ | 135 | .flags = clk_flags, \ |
136 | .dbg_name = #clk_id, \ | ||
137 | }, \ | ||
151 | } | 138 | } |
152 | 139 | ||
153 | #endif | 140 | #endif |
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c index 2069bfaa3a26..22a537669624 100644 --- a/arch/arm/mach-msm/clock.c +++ b/arch/arm/mach-msm/clock.c | |||
@@ -15,74 +15,32 @@ | |||
15 | */ | 15 | */ |
16 | 16 | ||
17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
18 | #include <linux/init.h> | ||
19 | #include <linux/module.h> | ||
20 | #include <linux/list.h> | 18 | #include <linux/list.h> |
21 | #include <linux/err.h> | 19 | #include <linux/err.h> |
22 | #include <linux/clk.h> | ||
23 | #include <linux/spinlock.h> | 20 | #include <linux/spinlock.h> |
24 | #include <linux/debugfs.h> | ||
25 | #include <linux/ctype.h> | ||
26 | #include <linux/pm_qos_params.h> | 21 | #include <linux/pm_qos_params.h> |
27 | #include <mach/clk.h> | 22 | #include <linux/mutex.h> |
23 | #include <linux/clk.h> | ||
24 | #include <linux/string.h> | ||
25 | #include <linux/module.h> | ||
26 | #include <linux/clkdev.h> | ||
28 | 27 | ||
29 | #include "clock.h" | 28 | #include "clock.h" |
30 | #include "proc_comm.h" | ||
31 | #include "clock-7x30.h" | ||
32 | 29 | ||
33 | static DEFINE_MUTEX(clocks_mutex); | 30 | static DEFINE_MUTEX(clocks_mutex); |
34 | static DEFINE_SPINLOCK(clocks_lock); | 31 | static DEFINE_SPINLOCK(clocks_lock); |
35 | static LIST_HEAD(clocks); | 32 | static LIST_HEAD(clocks); |
36 | struct clk *msm_clocks; | ||
37 | unsigned msm_num_clocks; | ||
38 | |||
39 | /* | ||
40 | * Bitmap of enabled clocks, excluding ACPU which is always | ||
41 | * enabled | ||
42 | */ | ||
43 | static DECLARE_BITMAP(clock_map_enabled, NR_CLKS); | ||
44 | static DEFINE_SPINLOCK(clock_map_lock); | ||
45 | 33 | ||
46 | /* | 34 | /* |
47 | * Standard clock functions defined in include/linux/clk.h | 35 | * Standard clock functions defined in include/linux/clk.h |
48 | */ | 36 | */ |
49 | struct clk *clk_get(struct device *dev, const char *id) | ||
50 | { | ||
51 | struct clk *clk; | ||
52 | |||
53 | mutex_lock(&clocks_mutex); | ||
54 | |||
55 | list_for_each_entry(clk, &clocks, list) | ||
56 | if (!strcmp(id, clk->name) && clk->dev == dev) | ||
57 | goto found_it; | ||
58 | |||
59 | list_for_each_entry(clk, &clocks, list) | ||
60 | if (!strcmp(id, clk->name) && clk->dev == NULL) | ||
61 | goto found_it; | ||
62 | |||
63 | clk = ERR_PTR(-ENOENT); | ||
64 | found_it: | ||
65 | mutex_unlock(&clocks_mutex); | ||
66 | return clk; | ||
67 | } | ||
68 | EXPORT_SYMBOL(clk_get); | ||
69 | |||
70 | void clk_put(struct clk *clk) | ||
71 | { | ||
72 | } | ||
73 | EXPORT_SYMBOL(clk_put); | ||
74 | |||
75 | int clk_enable(struct clk *clk) | 37 | int clk_enable(struct clk *clk) |
76 | { | 38 | { |
77 | unsigned long flags; | 39 | unsigned long flags; |
78 | spin_lock_irqsave(&clocks_lock, flags); | 40 | spin_lock_irqsave(&clocks_lock, flags); |
79 | clk->count++; | 41 | clk->count++; |
80 | if (clk->count == 1) { | 42 | if (clk->count == 1) |
81 | clk->ops->enable(clk->id); | 43 | clk->ops->enable(clk->id); |
82 | spin_lock(&clock_map_lock); | ||
83 | clock_map_enabled[BIT_WORD(clk->id)] |= BIT_MASK(clk->id); | ||
84 | spin_unlock(&clock_map_lock); | ||
85 | } | ||
86 | spin_unlock_irqrestore(&clocks_lock, flags); | 44 | spin_unlock_irqrestore(&clocks_lock, flags); |
87 | return 0; | 45 | return 0; |
88 | } | 46 | } |
@@ -94,20 +52,14 @@ void clk_disable(struct clk *clk) | |||
94 | spin_lock_irqsave(&clocks_lock, flags); | 52 | spin_lock_irqsave(&clocks_lock, flags); |
95 | BUG_ON(clk->count == 0); | 53 | BUG_ON(clk->count == 0); |
96 | clk->count--; | 54 | clk->count--; |
97 | if (clk->count == 0) { | 55 | if (clk->count == 0) |
98 | clk->ops->disable(clk->id); | 56 | clk->ops->disable(clk->id); |
99 | spin_lock(&clock_map_lock); | ||
100 | clock_map_enabled[BIT_WORD(clk->id)] &= ~BIT_MASK(clk->id); | ||
101 | spin_unlock(&clock_map_lock); | ||
102 | } | ||
103 | spin_unlock_irqrestore(&clocks_lock, flags); | 57 | spin_unlock_irqrestore(&clocks_lock, flags); |
104 | } | 58 | } |
105 | EXPORT_SYMBOL(clk_disable); | 59 | EXPORT_SYMBOL(clk_disable); |
106 | 60 | ||
107 | int clk_reset(struct clk *clk, enum clk_reset_action action) | 61 | int clk_reset(struct clk *clk, enum clk_reset_action action) |
108 | { | 62 | { |
109 | if (!clk->ops->reset) | ||
110 | clk->ops->reset = &pc_clk_reset; | ||
111 | return clk->ops->reset(clk->remote_id, action); | 63 | return clk->ops->reset(clk->remote_id, action); |
112 | } | 64 | } |
113 | EXPORT_SYMBOL(clk_reset); | 65 | EXPORT_SYMBOL(clk_reset); |
@@ -184,25 +136,14 @@ EXPORT_SYMBOL(clk_set_flags); | |||
184 | */ | 136 | */ |
185 | static struct clk *ebi1_clk; | 137 | static struct clk *ebi1_clk; |
186 | 138 | ||
187 | static void __init set_clock_ops(struct clk *clk) | 139 | void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks) |
188 | { | ||
189 | if (!clk->ops) { | ||
190 | clk->ops = &clk_ops_pcom; | ||
191 | clk->id = clk->remote_id; | ||
192 | } | ||
193 | } | ||
194 | |||
195 | void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks) | ||
196 | { | 140 | { |
197 | unsigned n; | 141 | unsigned n; |
198 | 142 | ||
199 | spin_lock_init(&clocks_lock); | ||
200 | mutex_lock(&clocks_mutex); | 143 | mutex_lock(&clocks_mutex); |
201 | msm_clocks = clock_tbl; | 144 | for (n = 0; n < num_clocks; n++) { |
202 | msm_num_clocks = num_clocks; | 145 | clkdev_add(&clock_tbl[n]); |
203 | for (n = 0; n < msm_num_clocks; n++) { | 146 | list_add_tail(&clock_tbl[n].clk->list, &clocks); |
204 | set_clock_ops(&msm_clocks[n]); | ||
205 | list_add_tail(&msm_clocks[n].list, &clocks); | ||
206 | } | 147 | } |
207 | mutex_unlock(&clocks_mutex); | 148 | mutex_unlock(&clocks_mutex); |
208 | 149 | ||
@@ -211,115 +152,6 @@ void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks) | |||
211 | 152 | ||
212 | } | 153 | } |
213 | 154 | ||
214 | #if defined(CONFIG_DEBUG_FS) | ||
215 | static struct clk *msm_clock_get_nth(unsigned index) | ||
216 | { | ||
217 | if (index < msm_num_clocks) | ||
218 | return msm_clocks + index; | ||
219 | else | ||
220 | return 0; | ||
221 | } | ||
222 | |||
223 | static int clock_debug_rate_set(void *data, u64 val) | ||
224 | { | ||
225 | struct clk *clock = data; | ||
226 | int ret; | ||
227 | |||
228 | /* Only increases to max rate will succeed, but that's actually good | ||
229 | * for debugging purposes. So we don't check for error. */ | ||
230 | if (clock->flags & CLK_MAX) | ||
231 | clk_set_max_rate(clock, val); | ||
232 | if (clock->flags & CLK_MIN) | ||
233 | ret = clk_set_min_rate(clock, val); | ||
234 | else | ||
235 | ret = clk_set_rate(clock, val); | ||
236 | if (ret != 0) | ||
237 | printk(KERN_ERR "clk_set%s_rate failed (%d)\n", | ||
238 | (clock->flags & CLK_MIN) ? "_min" : "", ret); | ||
239 | return ret; | ||
240 | } | ||
241 | |||
242 | static int clock_debug_rate_get(void *data, u64 *val) | ||
243 | { | ||
244 | struct clk *clock = data; | ||
245 | *val = clk_get_rate(clock); | ||
246 | return 0; | ||
247 | } | ||
248 | |||
249 | static int clock_debug_enable_set(void *data, u64 val) | ||
250 | { | ||
251 | struct clk *clock = data; | ||
252 | int rc = 0; | ||
253 | |||
254 | if (val) | ||
255 | rc = clock->ops->enable(clock->id); | ||
256 | else | ||
257 | clock->ops->disable(clock->id); | ||
258 | |||
259 | return rc; | ||
260 | } | ||
261 | |||
262 | static int clock_debug_enable_get(void *data, u64 *val) | ||
263 | { | ||
264 | struct clk *clock = data; | ||
265 | |||
266 | *val = clock->ops->is_enabled(clock->id); | ||
267 | |||
268 | return 0; | ||
269 | } | ||
270 | |||
271 | static int clock_debug_local_get(void *data, u64 *val) | ||
272 | { | ||
273 | struct clk *clock = data; | ||
274 | |||
275 | *val = clock->ops != &clk_ops_pcom; | ||
276 | |||
277 | return 0; | ||
278 | } | ||
279 | |||
280 | DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get, | ||
281 | clock_debug_rate_set, "%llu\n"); | ||
282 | DEFINE_SIMPLE_ATTRIBUTE(clock_enable_fops, clock_debug_enable_get, | ||
283 | clock_debug_enable_set, "%llu\n"); | ||
284 | DEFINE_SIMPLE_ATTRIBUTE(clock_local_fops, clock_debug_local_get, | ||
285 | NULL, "%llu\n"); | ||
286 | |||
287 | static int __init clock_debug_init(void) | ||
288 | { | ||
289 | struct dentry *dent_rate, *dent_enable, *dent_local; | ||
290 | struct clk *clock; | ||
291 | unsigned n = 0; | ||
292 | char temp[50], *ptr; | ||
293 | |||
294 | dent_rate = debugfs_create_dir("clk_rate", 0); | ||
295 | if (IS_ERR(dent_rate)) | ||
296 | return PTR_ERR(dent_rate); | ||
297 | |||
298 | dent_enable = debugfs_create_dir("clk_enable", 0); | ||
299 | if (IS_ERR(dent_enable)) | ||
300 | return PTR_ERR(dent_enable); | ||
301 | |||
302 | dent_local = debugfs_create_dir("clk_local", NULL); | ||
303 | if (IS_ERR(dent_local)) | ||
304 | return PTR_ERR(dent_local); | ||
305 | |||
306 | while ((clock = msm_clock_get_nth(n++)) != 0) { | ||
307 | strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1); | ||
308 | for (ptr = temp; *ptr; ptr++) | ||
309 | *ptr = tolower(*ptr); | ||
310 | debugfs_create_file(temp, 0644, dent_rate, | ||
311 | clock, &clock_rate_fops); | ||
312 | debugfs_create_file(temp, 0644, dent_enable, | ||
313 | clock, &clock_enable_fops); | ||
314 | debugfs_create_file(temp, S_IRUGO, dent_local, | ||
315 | clock, &clock_local_fops); | ||
316 | } | ||
317 | return 0; | ||
318 | } | ||
319 | |||
320 | device_initcall(clock_debug_init); | ||
321 | #endif | ||
322 | |||
323 | /* The bootloader and/or AMSS may have left various clocks enabled. | 155 | /* The bootloader and/or AMSS may have left various clocks enabled. |
324 | * Disable any clocks that belong to us (CLKFLAG_AUTO_OFF) but have | 156 | * Disable any clocks that belong to us (CLKFLAG_AUTO_OFF) but have |
325 | * not been explicitly enabled by a clk_enable() call. | 157 | * not been explicitly enabled by a clk_enable() call. |
@@ -330,8 +162,10 @@ static int __init clock_late_init(void) | |||
330 | struct clk *clk; | 162 | struct clk *clk; |
331 | unsigned count = 0; | 163 | unsigned count = 0; |
332 | 164 | ||
165 | clock_debug_init(); | ||
333 | mutex_lock(&clocks_mutex); | 166 | mutex_lock(&clocks_mutex); |
334 | list_for_each_entry(clk, &clocks, list) { | 167 | list_for_each_entry(clk, &clocks, list) { |
168 | clock_debug_add(clk); | ||
335 | if (clk->flags & CLKFLAG_AUTO_OFF) { | 169 | if (clk->flags & CLKFLAG_AUTO_OFF) { |
336 | spin_lock_irqsave(&clocks_lock, flags); | 170 | spin_lock_irqsave(&clocks_lock, flags); |
337 | if (!clk->count) { | 171 | if (!clk->count) { |
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h index c270b552ed13..2c007f606d29 100644 --- a/arch/arm/mach-msm/clock.h +++ b/arch/arm/mach-msm/clock.h | |||
@@ -17,12 +17,10 @@ | |||
17 | #ifndef __ARCH_ARM_MACH_MSM_CLOCK_H | 17 | #ifndef __ARCH_ARM_MACH_MSM_CLOCK_H |
18 | #define __ARCH_ARM_MACH_MSM_CLOCK_H | 18 | #define __ARCH_ARM_MACH_MSM_CLOCK_H |
19 | 19 | ||
20 | #include <linux/init.h> | ||
20 | #include <linux/list.h> | 21 | #include <linux/list.h> |
21 | #include <mach/clk.h> | 22 | #include <mach/clk.h> |
22 | 23 | ||
23 | #include "clock-pcom.h" | ||
24 | #include "clock-7x30.h" | ||
25 | |||
26 | #define CLKFLAG_INVERT 0x00000001 | 24 | #define CLKFLAG_INVERT 0x00000001 |
27 | #define CLKFLAG_NOINVERT 0x00000002 | 25 | #define CLKFLAG_NOINVERT 0x00000002 |
28 | #define CLKFLAG_NONEST 0x00000004 | 26 | #define CLKFLAG_NONEST 0x00000004 |
@@ -45,6 +43,7 @@ struct clk_ops { | |||
45 | unsigned (*get_rate)(unsigned id); | 43 | unsigned (*get_rate)(unsigned id); |
46 | unsigned (*is_enabled)(unsigned id); | 44 | unsigned (*is_enabled)(unsigned id); |
47 | long (*round_rate)(unsigned id, unsigned rate); | 45 | long (*round_rate)(unsigned id, unsigned rate); |
46 | bool (*is_local)(unsigned id); | ||
48 | }; | 47 | }; |
49 | 48 | ||
50 | struct clk { | 49 | struct clk { |
@@ -52,58 +51,22 @@ struct clk { | |||
52 | uint32_t remote_id; | 51 | uint32_t remote_id; |
53 | uint32_t count; | 52 | uint32_t count; |
54 | uint32_t flags; | 53 | uint32_t flags; |
55 | const char *name; | ||
56 | struct clk_ops *ops; | 54 | struct clk_ops *ops; |
57 | const char *dbg_name; | 55 | const char *dbg_name; |
58 | struct list_head list; | 56 | struct list_head list; |
59 | struct device *dev; | ||
60 | }; | 57 | }; |
61 | 58 | ||
62 | #define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100) | ||
63 | #define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104) | ||
64 | #define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124) | ||
65 | |||
66 | #ifdef CONFIG_DEBUG_FS | ||
67 | #define CLOCK_DBG_NAME(x) .dbg_name = x, | ||
68 | #else | ||
69 | #define CLOCK_DBG_NAME(x) | ||
70 | #endif | ||
71 | |||
72 | #define CLOCK(clk_name, clk_id, clk_dev, clk_flags) { \ | ||
73 | .name = clk_name, \ | ||
74 | .id = clk_id, \ | ||
75 | .flags = clk_flags, \ | ||
76 | .dev = clk_dev, \ | ||
77 | CLOCK_DBG_NAME(#clk_id) \ | ||
78 | } | ||
79 | |||
80 | #define OFF CLKFLAG_AUTO_OFF | 59 | #define OFF CLKFLAG_AUTO_OFF |
81 | #define CLK_MIN CLKFLAG_MIN | 60 | #define CLK_MIN CLKFLAG_MIN |
82 | #define CLK_MAX CLKFLAG_MAX | 61 | #define CLK_MAX CLKFLAG_MAX |
83 | #define CLK_MINMAX (CLK_MIN | CLK_MAX) | 62 | #define CLK_MINMAX (CLK_MIN | CLK_MAX) |
84 | #define NR_CLKS P_NR_CLKS | ||
85 | |||
86 | enum { | ||
87 | PLL_0 = 0, | ||
88 | PLL_1, | ||
89 | PLL_2, | ||
90 | PLL_3, | ||
91 | PLL_4, | ||
92 | PLL_5, | ||
93 | PLL_6, | ||
94 | NUM_PLL | ||
95 | }; | ||
96 | |||
97 | enum clkvote_client { | ||
98 | CLKVOTE_ACPUCLK = 0, | ||
99 | CLKVOTE_PMQOS, | ||
100 | CLKVOTE_MAX, | ||
101 | }; | ||
102 | |||
103 | int msm_clock_require_tcxo(unsigned long *reason, int nbits); | ||
104 | int msm_clock_get_name(uint32_t id, char *name, uint32_t size); | ||
105 | int ebi1_clk_set_min_rate(enum clkvote_client client, unsigned long rate); | ||
106 | unsigned long clk_get_max_axi_khz(void); | ||
107 | 63 | ||
64 | #ifdef CONFIG_DEBUG_FS | ||
65 | int __init clock_debug_init(void); | ||
66 | int __init clock_debug_add(struct clk *clock); | ||
67 | #else | ||
68 | static inline int __init clock_debug_init(void) { return 0; } | ||
69 | static inline int __init clock_debug_add(struct clk *clock) { return 0; } | ||
108 | #endif | 70 | #endif |
109 | 71 | ||
72 | #endif | ||
diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-iommu.c index f9e7bd34ec59..24030d0da6e3 100644 --- a/arch/arm/mach-msm/devices-msm8x60-iommu.c +++ b/arch/arm/mach-msm/devices-iommu.c | |||
@@ -1,4 +1,4 @@ | |||
1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | 1 | /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. |
2 | * | 2 | * |
3 | * This program is free software; you can redistribute it and/or modify | 3 | * This program is free software; you can redistribute it and/or modify |
4 | * it under the terms of the GNU General Public License version 2 and | 4 | * it under the terms of the GNU General Public License version 2 and |
@@ -18,15 +18,13 @@ | |||
18 | #include <linux/kernel.h> | 18 | #include <linux/kernel.h> |
19 | #include <linux/platform_device.h> | 19 | #include <linux/platform_device.h> |
20 | #include <linux/bootmem.h> | 20 | #include <linux/bootmem.h> |
21 | 21 | #include <mach/irqs.h> | |
22 | #include <mach/msm_iomap-8x60.h> | ||
23 | #include <mach/irqs-8x60.h> | ||
24 | #include <mach/iommu.h> | 22 | #include <mach/iommu.h> |
25 | 23 | ||
26 | static struct resource msm_iommu_jpegd_resources[] = { | 24 | static struct resource msm_iommu_jpegd_resources[] = { |
27 | { | 25 | { |
28 | .start = MSM_IOMMU_JPEGD_PHYS, | 26 | .start = 0x07300000, |
29 | .end = MSM_IOMMU_JPEGD_PHYS + MSM_IOMMU_JPEGD_SIZE - 1, | 27 | .end = 0x07300000 + SZ_1M - 1, |
30 | .name = "physbase", | 28 | .name = "physbase", |
31 | .flags = IORESOURCE_MEM, | 29 | .flags = IORESOURCE_MEM, |
32 | }, | 30 | }, |
@@ -46,8 +44,8 @@ static struct resource msm_iommu_jpegd_resources[] = { | |||
46 | 44 | ||
47 | static struct resource msm_iommu_vpe_resources[] = { | 45 | static struct resource msm_iommu_vpe_resources[] = { |
48 | { | 46 | { |
49 | .start = MSM_IOMMU_VPE_PHYS, | 47 | .start = 0x07400000, |
50 | .end = MSM_IOMMU_VPE_PHYS + MSM_IOMMU_VPE_SIZE - 1, | 48 | .end = 0x07400000 + SZ_1M - 1, |
51 | .name = "physbase", | 49 | .name = "physbase", |
52 | .flags = IORESOURCE_MEM, | 50 | .flags = IORESOURCE_MEM, |
53 | }, | 51 | }, |
@@ -67,8 +65,8 @@ static struct resource msm_iommu_vpe_resources[] = { | |||
67 | 65 | ||
68 | static struct resource msm_iommu_mdp0_resources[] = { | 66 | static struct resource msm_iommu_mdp0_resources[] = { |
69 | { | 67 | { |
70 | .start = MSM_IOMMU_MDP0_PHYS, | 68 | .start = 0x07500000, |
71 | .end = MSM_IOMMU_MDP0_PHYS + MSM_IOMMU_MDP0_SIZE - 1, | 69 | .end = 0x07500000 + SZ_1M - 1, |
72 | .name = "physbase", | 70 | .name = "physbase", |
73 | .flags = IORESOURCE_MEM, | 71 | .flags = IORESOURCE_MEM, |
74 | }, | 72 | }, |
@@ -88,8 +86,8 @@ static struct resource msm_iommu_mdp0_resources[] = { | |||
88 | 86 | ||
89 | static struct resource msm_iommu_mdp1_resources[] = { | 87 | static struct resource msm_iommu_mdp1_resources[] = { |
90 | { | 88 | { |
91 | .start = MSM_IOMMU_MDP1_PHYS, | 89 | .start = 0x07600000, |
92 | .end = MSM_IOMMU_MDP1_PHYS + MSM_IOMMU_MDP1_SIZE - 1, | 90 | .end = 0x07600000 + SZ_1M - 1, |
93 | .name = "physbase", | 91 | .name = "physbase", |
94 | .flags = IORESOURCE_MEM, | 92 | .flags = IORESOURCE_MEM, |
95 | }, | 93 | }, |
@@ -109,8 +107,8 @@ static struct resource msm_iommu_mdp1_resources[] = { | |||
109 | 107 | ||
110 | static struct resource msm_iommu_rot_resources[] = { | 108 | static struct resource msm_iommu_rot_resources[] = { |
111 | { | 109 | { |
112 | .start = MSM_IOMMU_ROT_PHYS, | 110 | .start = 0x07700000, |
113 | .end = MSM_IOMMU_ROT_PHYS + MSM_IOMMU_ROT_SIZE - 1, | 111 | .end = 0x07700000 + SZ_1M - 1, |
114 | .name = "physbase", | 112 | .name = "physbase", |
115 | .flags = IORESOURCE_MEM, | 113 | .flags = IORESOURCE_MEM, |
116 | }, | 114 | }, |
@@ -130,8 +128,8 @@ static struct resource msm_iommu_rot_resources[] = { | |||
130 | 128 | ||
131 | static struct resource msm_iommu_ijpeg_resources[] = { | 129 | static struct resource msm_iommu_ijpeg_resources[] = { |
132 | { | 130 | { |
133 | .start = MSM_IOMMU_IJPEG_PHYS, | 131 | .start = 0x07800000, |
134 | .end = MSM_IOMMU_IJPEG_PHYS + MSM_IOMMU_IJPEG_SIZE - 1, | 132 | .end = 0x07800000 + SZ_1M - 1, |
135 | .name = "physbase", | 133 | .name = "physbase", |
136 | .flags = IORESOURCE_MEM, | 134 | .flags = IORESOURCE_MEM, |
137 | }, | 135 | }, |
@@ -151,8 +149,8 @@ static struct resource msm_iommu_ijpeg_resources[] = { | |||
151 | 149 | ||
152 | static struct resource msm_iommu_vfe_resources[] = { | 150 | static struct resource msm_iommu_vfe_resources[] = { |
153 | { | 151 | { |
154 | .start = MSM_IOMMU_VFE_PHYS, | 152 | .start = 0x07900000, |
155 | .end = MSM_IOMMU_VFE_PHYS + MSM_IOMMU_VFE_SIZE - 1, | 153 | .end = 0x07900000 + SZ_1M - 1, |
156 | .name = "physbase", | 154 | .name = "physbase", |
157 | .flags = IORESOURCE_MEM, | 155 | .flags = IORESOURCE_MEM, |
158 | }, | 156 | }, |
@@ -172,8 +170,8 @@ static struct resource msm_iommu_vfe_resources[] = { | |||
172 | 170 | ||
173 | static struct resource msm_iommu_vcodec_a_resources[] = { | 171 | static struct resource msm_iommu_vcodec_a_resources[] = { |
174 | { | 172 | { |
175 | .start = MSM_IOMMU_VCODEC_A_PHYS, | 173 | .start = 0x07A00000, |
176 | .end = MSM_IOMMU_VCODEC_A_PHYS + MSM_IOMMU_VCODEC_A_SIZE - 1, | 174 | .end = 0x07A00000 + SZ_1M - 1, |
177 | .name = "physbase", | 175 | .name = "physbase", |
178 | .flags = IORESOURCE_MEM, | 176 | .flags = IORESOURCE_MEM, |
179 | }, | 177 | }, |
@@ -193,8 +191,8 @@ static struct resource msm_iommu_vcodec_a_resources[] = { | |||
193 | 191 | ||
194 | static struct resource msm_iommu_vcodec_b_resources[] = { | 192 | static struct resource msm_iommu_vcodec_b_resources[] = { |
195 | { | 193 | { |
196 | .start = MSM_IOMMU_VCODEC_B_PHYS, | 194 | .start = 0x07B00000, |
197 | .end = MSM_IOMMU_VCODEC_B_PHYS + MSM_IOMMU_VCODEC_B_SIZE - 1, | 195 | .end = 0x07B00000 + SZ_1M - 1, |
198 | .name = "physbase", | 196 | .name = "physbase", |
199 | .flags = IORESOURCE_MEM, | 197 | .flags = IORESOURCE_MEM, |
200 | }, | 198 | }, |
@@ -214,8 +212,8 @@ static struct resource msm_iommu_vcodec_b_resources[] = { | |||
214 | 212 | ||
215 | static struct resource msm_iommu_gfx3d_resources[] = { | 213 | static struct resource msm_iommu_gfx3d_resources[] = { |
216 | { | 214 | { |
217 | .start = MSM_IOMMU_GFX3D_PHYS, | 215 | .start = 0x07C00000, |
218 | .end = MSM_IOMMU_GFX3D_PHYS + MSM_IOMMU_GFX3D_SIZE - 1, | 216 | .end = 0x07C00000 + SZ_1M - 1, |
219 | .name = "physbase", | 217 | .name = "physbase", |
220 | .flags = IORESOURCE_MEM, | 218 | .flags = IORESOURCE_MEM, |
221 | }, | 219 | }, |
@@ -235,8 +233,8 @@ static struct resource msm_iommu_gfx3d_resources[] = { | |||
235 | 233 | ||
236 | static struct resource msm_iommu_gfx2d0_resources[] = { | 234 | static struct resource msm_iommu_gfx2d0_resources[] = { |
237 | { | 235 | { |
238 | .start = MSM_IOMMU_GFX2D0_PHYS, | 236 | .start = 0x07D00000, |
239 | .end = MSM_IOMMU_GFX2D0_PHYS + MSM_IOMMU_GFX2D0_SIZE - 1, | 237 | .end = 0x07D00000 + SZ_1M - 1, |
240 | .name = "physbase", | 238 | .name = "physbase", |
241 | .flags = IORESOURCE_MEM, | 239 | .flags = IORESOURCE_MEM, |
242 | }, | 240 | }, |
@@ -256,8 +254,8 @@ static struct resource msm_iommu_gfx2d0_resources[] = { | |||
256 | 254 | ||
257 | static struct resource msm_iommu_gfx2d1_resources[] = { | 255 | static struct resource msm_iommu_gfx2d1_resources[] = { |
258 | { | 256 | { |
259 | .start = MSM_IOMMU_GFX2D1_PHYS, | 257 | .start = 0x07E00000, |
260 | .end = MSM_IOMMU_GFX2D1_PHYS + MSM_IOMMU_GFX2D1_SIZE - 1, | 258 | .end = 0x07E00000 + SZ_1M - 1, |
261 | .name = "physbase", | 259 | .name = "physbase", |
262 | .flags = IORESOURCE_MEM, | 260 | .flags = IORESOURCE_MEM, |
263 | }, | 261 | }, |
@@ -282,55 +280,62 @@ static struct platform_device msm_root_iommu_dev = { | |||
282 | 280 | ||
283 | static struct msm_iommu_dev jpegd_iommu = { | 281 | static struct msm_iommu_dev jpegd_iommu = { |
284 | .name = "jpegd", | 282 | .name = "jpegd", |
285 | .clk_rate = -1 | 283 | .ncb = 2, |
286 | }; | 284 | }; |
287 | 285 | ||
288 | static struct msm_iommu_dev vpe_iommu = { | 286 | static struct msm_iommu_dev vpe_iommu = { |
289 | .name = "vpe" | 287 | .name = "vpe", |
288 | .ncb = 2, | ||
290 | }; | 289 | }; |
291 | 290 | ||
292 | static struct msm_iommu_dev mdp0_iommu = { | 291 | static struct msm_iommu_dev mdp0_iommu = { |
293 | .name = "mdp0" | 292 | .name = "mdp0", |
293 | .ncb = 2, | ||
294 | }; | 294 | }; |
295 | 295 | ||
296 | static struct msm_iommu_dev mdp1_iommu = { | 296 | static struct msm_iommu_dev mdp1_iommu = { |
297 | .name = "mdp1" | 297 | .name = "mdp1", |
298 | .ncb = 2, | ||
298 | }; | 299 | }; |
299 | 300 | ||
300 | static struct msm_iommu_dev rot_iommu = { | 301 | static struct msm_iommu_dev rot_iommu = { |
301 | .name = "rot" | 302 | .name = "rot", |
303 | .ncb = 2, | ||
302 | }; | 304 | }; |
303 | 305 | ||
304 | static struct msm_iommu_dev ijpeg_iommu = { | 306 | static struct msm_iommu_dev ijpeg_iommu = { |
305 | .name = "ijpeg" | 307 | .name = "ijpeg", |
308 | .ncb = 2, | ||
306 | }; | 309 | }; |
307 | 310 | ||
308 | static struct msm_iommu_dev vfe_iommu = { | 311 | static struct msm_iommu_dev vfe_iommu = { |
309 | .name = "vfe", | 312 | .name = "vfe", |
310 | .clk_rate = -1 | 313 | .ncb = 2, |
311 | }; | 314 | }; |
312 | 315 | ||
313 | static struct msm_iommu_dev vcodec_a_iommu = { | 316 | static struct msm_iommu_dev vcodec_a_iommu = { |
314 | .name = "vcodec_a" | 317 | .name = "vcodec_a", |
318 | .ncb = 2, | ||
315 | }; | 319 | }; |
316 | 320 | ||
317 | static struct msm_iommu_dev vcodec_b_iommu = { | 321 | static struct msm_iommu_dev vcodec_b_iommu = { |
318 | .name = "vcodec_b" | 322 | .name = "vcodec_b", |
323 | .ncb = 2, | ||
319 | }; | 324 | }; |
320 | 325 | ||
321 | static struct msm_iommu_dev gfx3d_iommu = { | 326 | static struct msm_iommu_dev gfx3d_iommu = { |
322 | .name = "gfx3d", | 327 | .name = "gfx3d", |
323 | .clk_rate = 27000000 | 328 | .ncb = 3, |
324 | }; | 329 | }; |
325 | 330 | ||
326 | static struct msm_iommu_dev gfx2d0_iommu = { | 331 | static struct msm_iommu_dev gfx2d0_iommu = { |
327 | .name = "gfx2d0", | 332 | .name = "gfx2d0", |
328 | .clk_rate = 27000000 | 333 | .ncb = 2, |
329 | }; | 334 | }; |
330 | 335 | ||
331 | static struct msm_iommu_dev gfx2d1_iommu = { | 336 | static struct msm_iommu_dev gfx2d1_iommu = { |
332 | .name = "gfx2d1", | 337 | .name = "gfx2d1", |
333 | .clk_rate = 27000000 | 338 | .ncb = 2, |
334 | }; | 339 | }; |
335 | 340 | ||
336 | static struct platform_device msm_device_iommu_jpegd = { | 341 | static struct platform_device msm_device_iommu_jpegd = { |
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c index fb548a8a21db..c4f5e26feb4d 100644 --- a/arch/arm/mach-msm/devices-msm7x00.c +++ b/arch/arm/mach-msm/devices-msm7x00.c | |||
@@ -15,6 +15,7 @@ | |||
15 | 15 | ||
16 | #include <linux/kernel.h> | 16 | #include <linux/kernel.h> |
17 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
18 | #include <linux/clkdev.h> | ||
18 | 19 | ||
19 | #include <mach/irqs.h> | 20 | #include <mach/irqs.h> |
20 | #include <mach/msm_iomap.h> | 21 | #include <mach/msm_iomap.h> |
@@ -24,8 +25,8 @@ | |||
24 | #include <linux/mtd/nand.h> | 25 | #include <linux/mtd/nand.h> |
25 | #include <linux/mtd/partitions.h> | 26 | #include <linux/mtd/partitions.h> |
26 | 27 | ||
27 | |||
28 | #include "clock.h" | 28 | #include "clock.h" |
29 | #include "clock-pcom.h" | ||
29 | #include <mach/mmc.h> | 30 | #include <mach/mmc.h> |
30 | 31 | ||
31 | static struct resource resources_uart1[] = { | 32 | static struct resource resources_uart1[] = { |
@@ -38,6 +39,7 @@ static struct resource resources_uart1[] = { | |||
38 | .start = MSM_UART1_PHYS, | 39 | .start = MSM_UART1_PHYS, |
39 | .end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1, | 40 | .end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1, |
40 | .flags = IORESOURCE_MEM, | 41 | .flags = IORESOURCE_MEM, |
42 | .name = "uart_resource" | ||
41 | }, | 43 | }, |
42 | }; | 44 | }; |
43 | 45 | ||
@@ -51,6 +53,7 @@ static struct resource resources_uart2[] = { | |||
51 | .start = MSM_UART2_PHYS, | 53 | .start = MSM_UART2_PHYS, |
52 | .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1, | 54 | .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1, |
53 | .flags = IORESOURCE_MEM, | 55 | .flags = IORESOURCE_MEM, |
56 | .name = "uart_resource" | ||
54 | }, | 57 | }, |
55 | }; | 58 | }; |
56 | 59 | ||
@@ -64,6 +67,7 @@ static struct resource resources_uart3[] = { | |||
64 | .start = MSM_UART3_PHYS, | 67 | .start = MSM_UART3_PHYS, |
65 | .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1, | 68 | .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1, |
66 | .flags = IORESOURCE_MEM, | 69 | .flags = IORESOURCE_MEM, |
70 | .name = "uart_resource" | ||
67 | }, | 71 | }, |
68 | }; | 72 | }; |
69 | 73 | ||
@@ -414,7 +418,7 @@ struct platform_device msm_device_mdp = { | |||
414 | .resource = resources_mdp, | 418 | .resource = resources_mdp, |
415 | }; | 419 | }; |
416 | 420 | ||
417 | struct clk msm_clocks_7x01a[] = { | 421 | struct clk_lookup msm_clocks_7x01a[] = { |
418 | CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), | 422 | CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), |
419 | CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), | 423 | CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), |
420 | CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, 0), | 424 | CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, 0), |
@@ -423,7 +427,7 @@ struct clk msm_clocks_7x01a[] = { | |||
423 | CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF), | 427 | CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF), |
424 | CLK_PCOM("gp_clk", GP_CLK, NULL, 0), | 428 | CLK_PCOM("gp_clk", GP_CLK, NULL, 0), |
425 | CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, OFF), | 429 | CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, OFF), |
426 | CLK_PCOM("i2c_clk", I2C_CLK, &msm_device_i2c.dev, 0), | 430 | CLK_PCOM("i2c_clk", I2C_CLK, "msm_i2c.0", 0), |
427 | CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0), | 431 | CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0), |
428 | CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0), | 432 | CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0), |
429 | CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF), | 433 | CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF), |
@@ -433,25 +437,25 @@ struct clk msm_clocks_7x01a[] = { | |||
433 | CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), | 437 | CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), |
434 | CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX), | 438 | CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX), |
435 | CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), | 439 | CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), |
436 | CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF), | 440 | CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF), |
437 | CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF), | 441 | CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF), |
438 | CLK_PCOM("sdc_clk", SDC2_CLK, &msm_device_sdc2.dev, OFF), | 442 | CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF), |
439 | CLK_PCOM("sdc_pclk", SDC2_P_CLK, &msm_device_sdc2.dev, OFF), | 443 | CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF), |
440 | CLK_PCOM("sdc_clk", SDC3_CLK, &msm_device_sdc3.dev, OFF), | 444 | CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF), |
441 | CLK_PCOM("sdc_pclk", SDC3_P_CLK, &msm_device_sdc3.dev, OFF), | 445 | CLK_PCOM("sdc_pclk", SDC3_P_CLK, "msm_sdcc.3", OFF), |
442 | CLK_PCOM("sdc_clk", SDC4_CLK, &msm_device_sdc4.dev, OFF), | 446 | CLK_PCOM("sdc_clk", SDC4_CLK, "msm_sdcc.4", OFF), |
443 | CLK_PCOM("sdc_pclk", SDC4_P_CLK, &msm_device_sdc4.dev, OFF), | 447 | CLK_PCOM("sdc_pclk", SDC4_P_CLK, "msm_sdcc.4", OFF), |
444 | CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), | 448 | CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), |
445 | CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), | 449 | CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), |
446 | CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), | 450 | CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), |
447 | CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), | 451 | CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), |
448 | CLK_PCOM("uart_clk", UART1_CLK, &msm_device_uart1.dev, OFF), | 452 | CLK_PCOM("uart_clk", UART1_CLK, "msm_serial.0", OFF), |
449 | CLK_PCOM("uart_clk", UART2_CLK, &msm_device_uart2.dev, 0), | 453 | CLK_PCOM("uart_clk", UART2_CLK, "msm_serial.1", 0), |
450 | CLK_PCOM("uart_clk", UART3_CLK, &msm_device_uart3.dev, OFF), | 454 | CLK_PCOM("uart_clk", UART3_CLK, "msm_serial.2", OFF), |
451 | CLK_PCOM("uart1dm_clk", UART1DM_CLK, NULL, OFF), | 455 | CLK_PCOM("uart1dm_clk", UART1DM_CLK, NULL, OFF), |
452 | CLK_PCOM("uart2dm_clk", UART2DM_CLK, NULL, 0), | 456 | CLK_PCOM("uart2dm_clk", UART2DM_CLK, NULL, 0), |
453 | CLK_PCOM("usb_hs_clk", USB_HS_CLK, &msm_device_hsusb.dev, OFF), | 457 | CLK_PCOM("usb_hs_clk", USB_HS_CLK, "msm_hsusb", OFF), |
454 | CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, &msm_device_hsusb.dev, OFF), | 458 | CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, "msm_hsusb", OFF), |
455 | CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0), | 459 | CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0), |
456 | CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF ), | 460 | CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF ), |
457 | CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF), | 461 | CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF), |
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c index 4e9a0ab3e937..09b4f1403824 100644 --- a/arch/arm/mach-msm/devices-msm7x30.c +++ b/arch/arm/mach-msm/devices-msm7x30.c | |||
@@ -1,6 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2008 Google, Inc. | 2 | * Copyright (C) 2008 Google, Inc. |
3 | * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. | 3 | * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. |
4 | * | 4 | * |
5 | * This software is licensed under the terms of the GNU General Public | 5 | * This software is licensed under the terms of the GNU General Public |
6 | * License version 2, as published by the Free Software Foundation, and | 6 | * License version 2, as published by the Free Software Foundation, and |
@@ -17,6 +17,7 @@ | |||
17 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
18 | 18 | ||
19 | #include <linux/dma-mapping.h> | 19 | #include <linux/dma-mapping.h> |
20 | #include <linux/clkdev.h> | ||
20 | #include <mach/irqs.h> | 21 | #include <mach/irqs.h> |
21 | #include <mach/msm_iomap.h> | 22 | #include <mach/msm_iomap.h> |
22 | #include <mach/dma.h> | 23 | #include <mach/dma.h> |
@@ -28,6 +29,7 @@ | |||
28 | #include <asm/mach/flash.h> | 29 | #include <asm/mach/flash.h> |
29 | 30 | ||
30 | #include "clock-pcom.h" | 31 | #include "clock-pcom.h" |
32 | #include "clock-7x30.h" | ||
31 | 33 | ||
32 | #include <mach/mmc.h> | 34 | #include <mach/mmc.h> |
33 | 35 | ||
@@ -41,6 +43,7 @@ static struct resource resources_uart2[] = { | |||
41 | .start = MSM_UART2_PHYS, | 43 | .start = MSM_UART2_PHYS, |
42 | .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1, | 44 | .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1, |
43 | .flags = IORESOURCE_MEM, | 45 | .flags = IORESOURCE_MEM, |
46 | .name = "uart_resource" | ||
44 | }, | 47 | }, |
45 | }; | 48 | }; |
46 | 49 | ||
@@ -127,11 +130,13 @@ struct platform_device msm_device_hsusb_host = { | |||
127 | }, | 130 | }, |
128 | }; | 131 | }; |
129 | 132 | ||
130 | struct clk msm_clocks_7x30[] = { | 133 | struct clk_lookup msm_clocks_7x30[] = { |
131 | CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), | 134 | CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), |
132 | CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), | 135 | CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), |
133 | CLK_PCOM("cam_m_clk", CAM_M_CLK, NULL, 0), | 136 | CLK_PCOM("cam_m_clk", CAM_M_CLK, NULL, 0), |
134 | CLK_PCOM("camif_pad_pclk", CAMIF_PAD_P_CLK, NULL, OFF), | 137 | CLK_PCOM("camif_pad_pclk", CAMIF_PAD_P_CLK, NULL, OFF), |
138 | CLK_PCOM("ce_clk", CE_CLK, NULL, 0), | ||
139 | CLK_PCOM("codec_ssbi_clk", CODEC_SSBI_CLK, NULL, 0), | ||
135 | CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), | 140 | CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), |
136 | CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0), | 141 | CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0), |
137 | CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX), | 142 | CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX), |
@@ -177,7 +182,7 @@ struct clk msm_clocks_7x30[] = { | |||
177 | CLK_7X30S("tv_src_clk", TV_CLK, TV_ENC_CLK, NULL, 0), | 182 | CLK_7X30S("tv_src_clk", TV_CLK, TV_ENC_CLK, NULL, 0), |
178 | CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), | 183 | CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), |
179 | CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), | 184 | CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), |
180 | CLK_PCOM("uart_clk", UART2_CLK, &msm_device_uart2.dev, 0), | 185 | CLK_PCOM("uart_clk", UART2_CLK, "msm_serial.1", 0), |
181 | CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0), | 186 | CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0), |
182 | CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), | 187 | CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), |
183 | CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF), | 188 | CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF), |
diff --git a/arch/arm/mach-msm/devices-msm8960.c b/arch/arm/mach-msm/devices-msm8960.c new file mode 100644 index 000000000000..d9e1f26475de --- /dev/null +++ b/arch/arm/mach-msm/devices-msm8960.c | |||
@@ -0,0 +1,85 @@ | |||
1 | /* Copyright (c) 2011, Code Aurora Forum. All rights reserved. | ||
2 | * | ||
3 | * This program is free software; you can redistribute it and/or modify | ||
4 | * it under the terms of the GNU General Public License version 2 and | ||
5 | * only version 2 as published by the Free Software Foundation. | ||
6 | * | ||
7 | * This program is distributed in the hope that it will be useful, | ||
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | * GNU General Public License for more details. | ||
11 | * | ||
12 | * You should have received a copy of the GNU General Public License | ||
13 | * along with this program; if not, write to the Free Software | ||
14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
15 | * 02110-1301, USA. | ||
16 | */ | ||
17 | |||
18 | #include <linux/kernel.h> | ||
19 | #include <linux/platform_device.h> | ||
20 | |||
21 | #include <linux/dma-mapping.h> | ||
22 | #include <mach/irqs-8960.h> | ||
23 | #include <mach/board.h> | ||
24 | |||
25 | #include "devices.h" | ||
26 | |||
27 | #define MSM_GSBI2_PHYS 0x16100000 | ||
28 | #define MSM_UART2DM_PHYS (MSM_GSBI2_PHYS + 0x40000) | ||
29 | |||
30 | #define MSM_GSBI5_PHYS 0x16400000 | ||
31 | #define MSM_UART5DM_PHYS (MSM_GSBI5_PHYS + 0x40000) | ||
32 | |||
33 | static struct resource resources_uart_gsbi2[] = { | ||
34 | { | ||
35 | .start = GSBI2_UARTDM_IRQ, | ||
36 | .end = GSBI2_UARTDM_IRQ, | ||
37 | .flags = IORESOURCE_IRQ, | ||
38 | }, | ||
39 | { | ||
40 | .start = MSM_UART2DM_PHYS, | ||
41 | .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1, | ||
42 | .name = "uart_resource", | ||
43 | .flags = IORESOURCE_MEM, | ||
44 | }, | ||
45 | { | ||
46 | .start = MSM_GSBI2_PHYS, | ||
47 | .end = MSM_GSBI2_PHYS + PAGE_SIZE - 1, | ||
48 | .name = "gsbi_resource", | ||
49 | .flags = IORESOURCE_MEM, | ||
50 | }, | ||
51 | }; | ||
52 | |||
53 | struct platform_device msm8960_device_uart_gsbi2 = { | ||
54 | .name = "msm_serial", | ||
55 | .id = 0, | ||
56 | .num_resources = ARRAY_SIZE(resources_uart_gsbi2), | ||
57 | .resource = resources_uart_gsbi2, | ||
58 | }; | ||
59 | |||
60 | static struct resource resources_uart_gsbi5[] = { | ||
61 | { | ||
62 | .start = GSBI5_UARTDM_IRQ, | ||
63 | .end = GSBI5_UARTDM_IRQ, | ||
64 | .flags = IORESOURCE_IRQ, | ||
65 | }, | ||
66 | { | ||
67 | .start = MSM_UART5DM_PHYS, | ||
68 | .end = MSM_UART5DM_PHYS + PAGE_SIZE - 1, | ||
69 | .name = "uart_resource", | ||
70 | .flags = IORESOURCE_MEM, | ||
71 | }, | ||
72 | { | ||
73 | .start = MSM_GSBI5_PHYS, | ||
74 | .end = MSM_GSBI5_PHYS + PAGE_SIZE - 1, | ||
75 | .name = "gsbi_resource", | ||
76 | .flags = IORESOURCE_MEM, | ||
77 | }, | ||
78 | }; | ||
79 | |||
80 | struct platform_device msm8960_device_uart_gsbi5 = { | ||
81 | .name = "msm_serial", | ||
82 | .id = 0, | ||
83 | .num_resources = ARRAY_SIZE(resources_uart_gsbi5), | ||
84 | .resource = resources_uart_gsbi5, | ||
85 | }; | ||
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c index a4b798f20ccb..12d8deb78d9c 100644 --- a/arch/arm/mach-msm/devices-qsd8x50.c +++ b/arch/arm/mach-msm/devices-qsd8x50.c | |||
@@ -1,6 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2008 Google, Inc. | 2 | * Copyright (C) 2008 Google, Inc. |
3 | * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. | 3 | * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. |
4 | * | 4 | * |
5 | * This software is licensed under the terms of the GNU General Public | 5 | * This software is licensed under the terms of the GNU General Public |
6 | * License version 2, as published by the Free Software Foundation, and | 6 | * License version 2, as published by the Free Software Foundation, and |
@@ -15,8 +15,9 @@ | |||
15 | 15 | ||
16 | #include <linux/kernel.h> | 16 | #include <linux/kernel.h> |
17 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
18 | 18 | #include <linux/clkdev.h> | |
19 | #include <linux/dma-mapping.h> | 19 | #include <linux/dma-mapping.h> |
20 | |||
20 | #include <mach/irqs.h> | 21 | #include <mach/irqs.h> |
21 | #include <mach/msm_iomap.h> | 22 | #include <mach/msm_iomap.h> |
22 | #include <mach/dma.h> | 23 | #include <mach/dma.h> |
@@ -27,6 +28,7 @@ | |||
27 | #include <asm/mach/flash.h> | 28 | #include <asm/mach/flash.h> |
28 | 29 | ||
29 | #include <mach/mmc.h> | 30 | #include <mach/mmc.h> |
31 | #include "clock-pcom.h" | ||
30 | 32 | ||
31 | static struct resource resources_uart3[] = { | 33 | static struct resource resources_uart3[] = { |
32 | { | 34 | { |
@@ -38,6 +40,7 @@ static struct resource resources_uart3[] = { | |||
38 | .start = MSM_UART3_PHYS, | 40 | .start = MSM_UART3_PHYS, |
39 | .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1, | 41 | .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1, |
40 | .flags = IORESOURCE_MEM, | 42 | .flags = IORESOURCE_MEM, |
43 | .name = "uart_resource" | ||
41 | }, | 44 | }, |
42 | }; | 45 | }; |
43 | 46 | ||
@@ -124,14 +127,204 @@ struct platform_device msm_device_hsusb_host = { | |||
124 | }, | 127 | }, |
125 | }; | 128 | }; |
126 | 129 | ||
127 | struct clk msm_clocks_8x50[] = { | 130 | static struct resource resources_sdc1[] = { |
131 | { | ||
132 | .start = MSM_SDC1_PHYS, | ||
133 | .end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1, | ||
134 | .flags = IORESOURCE_MEM, | ||
135 | }, | ||
136 | { | ||
137 | .start = INT_SDC1_0, | ||
138 | .end = INT_SDC1_0, | ||
139 | .flags = IORESOURCE_IRQ, | ||
140 | .name = "cmd_irq", | ||
141 | }, | ||
142 | { | ||
143 | .start = INT_SDC1_1, | ||
144 | .end = INT_SDC1_1, | ||
145 | .flags = IORESOURCE_IRQ, | ||
146 | .name = "pio_irq", | ||
147 | }, | ||
148 | { | ||
149 | .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, | ||
150 | .name = "status_irq" | ||
151 | }, | ||
152 | { | ||
153 | .start = 8, | ||
154 | .end = 8, | ||
155 | .flags = IORESOURCE_DMA, | ||
156 | }, | ||
157 | }; | ||
158 | |||
159 | static struct resource resources_sdc2[] = { | ||
160 | { | ||
161 | .start = MSM_SDC2_PHYS, | ||
162 | .end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1, | ||
163 | .flags = IORESOURCE_MEM, | ||
164 | }, | ||
165 | { | ||
166 | .start = INT_SDC2_0, | ||
167 | .end = INT_SDC2_0, | ||
168 | .flags = IORESOURCE_IRQ, | ||
169 | .name = "cmd_irq", | ||
170 | }, | ||
171 | { | ||
172 | .start = INT_SDC2_1, | ||
173 | .end = INT_SDC2_1, | ||
174 | .flags = IORESOURCE_IRQ, | ||
175 | .name = "pio_irq", | ||
176 | }, | ||
177 | { | ||
178 | .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, | ||
179 | .name = "status_irq" | ||
180 | }, | ||
181 | { | ||
182 | .start = 8, | ||
183 | .end = 8, | ||
184 | .flags = IORESOURCE_DMA, | ||
185 | }, | ||
186 | }; | ||
187 | |||
188 | static struct resource resources_sdc3[] = { | ||
189 | { | ||
190 | .start = MSM_SDC3_PHYS, | ||
191 | .end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1, | ||
192 | .flags = IORESOURCE_MEM, | ||
193 | }, | ||
194 | { | ||
195 | .start = INT_SDC3_0, | ||
196 | .end = INT_SDC3_0, | ||
197 | .flags = IORESOURCE_IRQ, | ||
198 | .name = "cmd_irq", | ||
199 | }, | ||
200 | { | ||
201 | .start = INT_SDC3_1, | ||
202 | .end = INT_SDC3_1, | ||
203 | .flags = IORESOURCE_IRQ, | ||
204 | .name = "pio_irq", | ||
205 | }, | ||
206 | { | ||
207 | .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, | ||
208 | .name = "status_irq" | ||
209 | }, | ||
210 | { | ||
211 | .start = 8, | ||
212 | .end = 8, | ||
213 | .flags = IORESOURCE_DMA, | ||
214 | }, | ||
215 | }; | ||
216 | |||
217 | static struct resource resources_sdc4[] = { | ||
218 | { | ||
219 | .start = MSM_SDC4_PHYS, | ||
220 | .end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1, | ||
221 | .flags = IORESOURCE_MEM, | ||
222 | }, | ||
223 | { | ||
224 | .start = INT_SDC4_0, | ||
225 | .end = INT_SDC4_0, | ||
226 | .flags = IORESOURCE_IRQ, | ||
227 | .name = "cmd_irq", | ||
228 | }, | ||
229 | { | ||
230 | .start = INT_SDC4_1, | ||
231 | .end = INT_SDC4_1, | ||
232 | .flags = IORESOURCE_IRQ, | ||
233 | .name = "pio_irq", | ||
234 | }, | ||
235 | { | ||
236 | .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, | ||
237 | .name = "status_irq" | ||
238 | }, | ||
239 | { | ||
240 | .start = 8, | ||
241 | .end = 8, | ||
242 | .flags = IORESOURCE_DMA, | ||
243 | }, | ||
244 | }; | ||
245 | |||
246 | struct platform_device msm_device_sdc1 = { | ||
247 | .name = "msm_sdcc", | ||
248 | .id = 1, | ||
249 | .num_resources = ARRAY_SIZE(resources_sdc1), | ||
250 | .resource = resources_sdc1, | ||
251 | .dev = { | ||
252 | .coherent_dma_mask = 0xffffffff, | ||
253 | }, | ||
254 | }; | ||
255 | |||
256 | struct platform_device msm_device_sdc2 = { | ||
257 | .name = "msm_sdcc", | ||
258 | .id = 2, | ||
259 | .num_resources = ARRAY_SIZE(resources_sdc2), | ||
260 | .resource = resources_sdc2, | ||
261 | .dev = { | ||
262 | .coherent_dma_mask = 0xffffffff, | ||
263 | }, | ||
264 | }; | ||
265 | |||
266 | struct platform_device msm_device_sdc3 = { | ||
267 | .name = "msm_sdcc", | ||
268 | .id = 3, | ||
269 | .num_resources = ARRAY_SIZE(resources_sdc3), | ||
270 | .resource = resources_sdc3, | ||
271 | .dev = { | ||
272 | .coherent_dma_mask = 0xffffffff, | ||
273 | }, | ||
274 | }; | ||
275 | |||
276 | struct platform_device msm_device_sdc4 = { | ||
277 | .name = "msm_sdcc", | ||
278 | .id = 4, | ||
279 | .num_resources = ARRAY_SIZE(resources_sdc4), | ||
280 | .resource = resources_sdc4, | ||
281 | .dev = { | ||
282 | .coherent_dma_mask = 0xffffffff, | ||
283 | }, | ||
284 | }; | ||
285 | |||
286 | static struct platform_device *msm_sdcc_devices[] __initdata = { | ||
287 | &msm_device_sdc1, | ||
288 | &msm_device_sdc2, | ||
289 | &msm_device_sdc3, | ||
290 | &msm_device_sdc4, | ||
291 | }; | ||
292 | |||
293 | int __init msm_add_sdcc(unsigned int controller, | ||
294 | struct msm_mmc_platform_data *plat, | ||
295 | unsigned int stat_irq, unsigned long stat_irq_flags) | ||
296 | { | ||
297 | struct platform_device *pdev; | ||
298 | struct resource *res; | ||
299 | |||
300 | if (controller < 1 || controller > 4) | ||
301 | return -EINVAL; | ||
302 | |||
303 | pdev = msm_sdcc_devices[controller-1]; | ||
304 | pdev->dev.platform_data = plat; | ||
305 | |||
306 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq"); | ||
307 | if (!res) | ||
308 | return -EINVAL; | ||
309 | else if (stat_irq) { | ||
310 | res->start = res->end = stat_irq; | ||
311 | res->flags &= ~IORESOURCE_DISABLED; | ||
312 | res->flags |= stat_irq_flags; | ||
313 | } | ||
314 | |||
315 | return platform_device_register(pdev); | ||
316 | } | ||
317 | |||
318 | struct clk_lookup msm_clocks_8x50[] = { | ||
128 | CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), | 319 | CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), |
320 | CLK_PCOM("ce_clk", CE_CLK, NULL, 0), | ||
129 | CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), | 321 | CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), |
130 | CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0), | 322 | CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0), |
131 | CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0), | 323 | CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0), |
132 | CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX), | 324 | CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX), |
133 | CLK_PCOM("gp_clk", GP_CLK, NULL, 0), | 325 | CLK_PCOM("gp_clk", GP_CLK, NULL, 0), |
134 | CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0), | 326 | CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0), |
327 | CLK_PCOM("i2c_clk", I2C_CLK, NULL, 0), | ||
135 | CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0), | 328 | CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0), |
136 | CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0), | 329 | CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0), |
137 | CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF), | 330 | CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF), |
@@ -144,12 +337,24 @@ struct clk msm_clocks_8x50[] = { | |||
144 | CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN), | 337 | CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN), |
145 | CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), | 338 | CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), |
146 | CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), | 339 | CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), |
340 | CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF), | ||
341 | CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF), | ||
342 | CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF), | ||
343 | CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF), | ||
344 | CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF), | ||
345 | CLK_PCOM("sdc_pclk", SDC3_P_CLK, "msm_sdcc.3", OFF), | ||
346 | CLK_PCOM("sdc_clk", SDC4_CLK, "msm_sdcc.4", OFF), | ||
347 | CLK_PCOM("sdc_pclk", SDC4_P_CLK, "msm_sdcc.4", OFF), | ||
147 | CLK_PCOM("spi_clk", SPI_CLK, NULL, 0), | 348 | CLK_PCOM("spi_clk", SPI_CLK, NULL, 0), |
148 | CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), | 349 | CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), |
149 | CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), | 350 | CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), |
150 | CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), | 351 | CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), |
151 | CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), | 352 | CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), |
152 | CLK_PCOM("uart_clk", UART3_CLK, &msm_device_uart3.dev, OFF), | 353 | CLK_PCOM("uart_clk", UART1_CLK, NULL, OFF), |
354 | CLK_PCOM("uart_clk", UART2_CLK, NULL, 0), | ||
355 | CLK_PCOM("uart_clk", UART3_CLK, "msm_serial.2", OFF), | ||
356 | CLK_PCOM("uartdm_clk", UART1DM_CLK, NULL, OFF), | ||
357 | CLK_PCOM("uartdm_clk", UART2DM_CLK, NULL, 0), | ||
153 | CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), | 358 | CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), |
154 | CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF), | 359 | CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF), |
155 | CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0), | 360 | CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0), |
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h index 87c70bfce2bd..9545c196c6e8 100644 --- a/arch/arm/mach-msm/devices.h +++ b/arch/arm/mach-msm/devices.h | |||
@@ -16,12 +16,17 @@ | |||
16 | #ifndef __ARCH_ARM_MACH_MSM_DEVICES_H | 16 | #ifndef __ARCH_ARM_MACH_MSM_DEVICES_H |
17 | #define __ARCH_ARM_MACH_MSM_DEVICES_H | 17 | #define __ARCH_ARM_MACH_MSM_DEVICES_H |
18 | 18 | ||
19 | #include <linux/clkdev.h> | ||
20 | |||
19 | #include "clock.h" | 21 | #include "clock.h" |
20 | 22 | ||
21 | extern struct platform_device msm_device_uart1; | 23 | extern struct platform_device msm_device_uart1; |
22 | extern struct platform_device msm_device_uart2; | 24 | extern struct platform_device msm_device_uart2; |
23 | extern struct platform_device msm_device_uart3; | 25 | extern struct platform_device msm_device_uart3; |
24 | 26 | ||
27 | extern struct platform_device msm8960_device_uart_gsbi2; | ||
28 | extern struct platform_device msm8960_device_uart_gsbi5; | ||
29 | |||
25 | extern struct platform_device msm_device_sdc1; | 30 | extern struct platform_device msm_device_sdc1; |
26 | extern struct platform_device msm_device_sdc2; | 31 | extern struct platform_device msm_device_sdc2; |
27 | extern struct platform_device msm_device_sdc3; | 32 | extern struct platform_device msm_device_sdc3; |
@@ -41,13 +46,13 @@ extern struct platform_device msm_device_mddi0; | |||
41 | extern struct platform_device msm_device_mddi1; | 46 | extern struct platform_device msm_device_mddi1; |
42 | extern struct platform_device msm_device_mdp; | 47 | extern struct platform_device msm_device_mdp; |
43 | 48 | ||
44 | extern struct clk msm_clocks_7x01a[]; | 49 | extern struct clk_lookup msm_clocks_7x01a[]; |
45 | extern unsigned msm_num_clocks_7x01a; | 50 | extern unsigned msm_num_clocks_7x01a; |
46 | 51 | ||
47 | extern struct clk msm_clocks_7x30[]; | 52 | extern struct clk_lookup msm_clocks_7x30[]; |
48 | extern unsigned msm_num_clocks_7x30; | 53 | extern unsigned msm_num_clocks_7x30; |
49 | 54 | ||
50 | extern struct clk msm_clocks_8x50[]; | 55 | extern struct clk_lookup msm_clocks_8x50[]; |
51 | extern unsigned msm_num_clocks_8x50; | 56 | extern unsigned msm_num_clocks_8x50; |
52 | 57 | ||
53 | #endif | 58 | #endif |
diff --git a/arch/arm/mach-msm/gpiomux-7x30.c b/arch/arm/mach-msm/gpiomux-7x30.c deleted file mode 100644 index 6ce41c5241a5..000000000000 --- a/arch/arm/mach-msm/gpiomux-7x30.c +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | ||
2 | * | ||
3 | * This program is free software; you can redistribute it and/or modify | ||
4 | * it under the terms of the GNU General Public License version 2 and | ||
5 | * only version 2 as published by the Free Software Foundation. | ||
6 | * | ||
7 | * This program is distributed in the hope that it will be useful, | ||
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | * GNU General Public License for more details. | ||
11 | * | ||
12 | * You should have received a copy of the GNU General Public License | ||
13 | * along with this program; if not, write to the Free Software | ||
14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
15 | * 02110-1301, USA. | ||
16 | */ | ||
17 | #include "gpiomux.h" | ||
18 | |||
19 | struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { | ||
20 | #ifdef CONFIG_SERIAL_MSM_CONSOLE | ||
21 | [49] = { /* UART2 RFR */ | ||
22 | .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | | ||
23 | GPIOMUX_FUNC_2 | GPIOMUX_VALID, | ||
24 | }, | ||
25 | [50] = { /* UART2 CTS */ | ||
26 | .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | | ||
27 | GPIOMUX_FUNC_2 | GPIOMUX_VALID, | ||
28 | }, | ||
29 | [51] = { /* UART2 RX */ | ||
30 | .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | | ||
31 | GPIOMUX_FUNC_2 | GPIOMUX_VALID, | ||
32 | }, | ||
33 | [52] = { /* UART2 TX */ | ||
34 | .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | | ||
35 | GPIOMUX_FUNC_2 | GPIOMUX_VALID, | ||
36 | }, | ||
37 | #endif | ||
38 | }; | ||
diff --git a/arch/arm/mach-msm/gpiomux-8x50.c b/arch/arm/mach-msm/gpiomux-8x50.c index 4406e0f4ae95..f7a4ea593c95 100644 --- a/arch/arm/mach-msm/gpiomux-8x50.c +++ b/arch/arm/mach-msm/gpiomux-8x50.c | |||
@@ -16,6 +16,19 @@ | |||
16 | */ | 16 | */ |
17 | #include "gpiomux.h" | 17 | #include "gpiomux.h" |
18 | 18 | ||
19 | #if defined(CONFIG_MMC_MSM) || defined(CONFIG_MMC_MSM_MODULE) | ||
20 | #define SDCC_DAT_0_3_CMD_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_UP\ | ||
21 | | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA) | ||
22 | #define SDCC_CLK_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_NONE\ | ||
23 | | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA) | ||
24 | #else | ||
25 | #define SDCC_DAT_0_3_CMD_ACTV_CFG 0 | ||
26 | #define SDCC_CLK_ACTV_CFG 0 | ||
27 | #endif | ||
28 | |||
29 | #define SDC1_SUSPEND_CONFIG (GPIOMUX_VALID | GPIOMUX_PULL_DOWN\ | ||
30 | | GPIOMUX_FUNC_GPIO | GPIOMUX_DRV_2MA) | ||
31 | |||
19 | struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { | 32 | struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { |
20 | [86] = { /* UART3 RX */ | 33 | [86] = { /* UART3 RX */ |
21 | .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | | 34 | .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | |
@@ -25,4 +38,14 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { | |||
25 | .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | | 38 | .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | |
26 | GPIOMUX_FUNC_1 | GPIOMUX_VALID, | 39 | GPIOMUX_FUNC_1 | GPIOMUX_VALID, |
27 | }, | 40 | }, |
41 | /* SDC1 data[3:0] & CMD */ | ||
42 | [51 ... 55] = { | ||
43 | .active = SDCC_DAT_0_3_CMD_ACTV_CFG, | ||
44 | .suspended = SDC1_SUSPEND_CONFIG | ||
45 | }, | ||
46 | /* SDC1 CLK */ | ||
47 | [56] = { | ||
48 | .active = SDCC_CLK_ACTV_CFG, | ||
49 | .suspended = SDC1_SUSPEND_CONFIG | ||
50 | }, | ||
28 | }; | 51 | }; |
diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S index d0c214338df9..0c631a9f8647 100644 --- a/arch/arm/mach-msm/headsmp.S +++ b/arch/arm/mach-msm/headsmp.S | |||
@@ -11,7 +11,7 @@ | |||
11 | #include <linux/linkage.h> | 11 | #include <linux/linkage.h> |
12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
13 | 13 | ||
14 | __INIT | 14 | __CPUINIT |
15 | 15 | ||
16 | /* | 16 | /* |
17 | * MSM specific entry point for secondary CPUs. This provides | 17 | * MSM specific entry point for secondary CPUs. This provides |
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h index 6abf4a6eadc1..2ce8f1f2fc4d 100644 --- a/arch/arm/mach-msm/include/mach/board.h +++ b/arch/arm/mach-msm/include/mach/board.h | |||
@@ -31,7 +31,7 @@ struct msm_acpu_clock_platform_data | |||
31 | unsigned long wait_for_irq_khz; | 31 | unsigned long wait_for_irq_khz; |
32 | }; | 32 | }; |
33 | 33 | ||
34 | struct clk; | 34 | struct clk_lookup; |
35 | 35 | ||
36 | extern struct sys_timer msm_timer; | 36 | extern struct sys_timer msm_timer; |
37 | 37 | ||
@@ -41,7 +41,7 @@ void __init msm_add_devices(void); | |||
41 | void __init msm_map_common_io(void); | 41 | void __init msm_map_common_io(void); |
42 | void __init msm_init_irq(void); | 42 | void __init msm_init_irq(void); |
43 | void __init msm_init_gpio(void); | 43 | void __init msm_init_gpio(void); |
44 | void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks); | 44 | void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks); |
45 | void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *); | 45 | void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *); |
46 | int __init msm_add_sdcc(unsigned int controller, | 46 | int __init msm_add_sdcc(unsigned int controller, |
47 | struct msm_mmc_platform_data *plat, | 47 | struct msm_mmc_platform_data *plat, |
diff --git a/arch/arm/mach-msm/include/mach/clk.h b/arch/arm/mach-msm/include/mach/clk.h index c05ca40478c7..e8d38428d813 100644 --- a/arch/arm/mach-msm/include/mach/clk.h +++ b/arch/arm/mach-msm/include/mach/clk.h | |||
@@ -1,30 +1,13 @@ | |||
1 | /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. | 1 | /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. |
2 | * | 2 | * |
3 | * Redistribution and use in source and binary forms, with or without | 3 | * This program is free software; you can redistribute it and/or modify |
4 | * modification, are permitted provided that the following conditions are | 4 | * it under the terms of the GNU General Public License version 2 and |
5 | * met: | 5 | * only version 2 as published by the Free Software Foundation. |
6 | * * Redistributions of source code must retain the above copyright | ||
7 | * notice, this list of conditions and the following disclaimer. | ||
8 | * * Redistributions in binary form must reproduce the above | ||
9 | * copyright notice, this list of conditions and the following | ||
10 | * disclaimer in the documentation and/or other materials provided | ||
11 | * with the distribution. | ||
12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its | ||
13 | * contributors may be used to endorse or promote products derived | ||
14 | * from this software without specific prior written permission. | ||
15 | * | ||
16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | ||
17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT | ||
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS | ||
20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
27 | * | 6 | * |
7 | * This program is distributed in the hope that it will be useful, | ||
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | * GNU General Public License for more details. | ||
28 | */ | 11 | */ |
29 | #ifndef __MACH_CLK_H | 12 | #ifndef __MACH_CLK_H |
30 | #define __MACH_CLK_H | 13 | #define __MACH_CLK_H |
diff --git a/arch/arm/mach-msm/include/mach/clkdev.h b/arch/arm/mach-msm/include/mach/clkdev.h new file mode 100644 index 000000000000..f87a57b59534 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/clkdev.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* Copyright (c) 2011, Code Aurora Forum. All rights reserved. | ||
2 | * | ||
3 | * This program is free software; you can redistribute it and/or modify | ||
4 | * it under the terms of the GNU General Public License version 2 and | ||
5 | * only version 2 as published by the Free Software Foundation. | ||
6 | * | ||
7 | * This program is distributed in the hope that it will be useful, | ||
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | * GNU General Public License for more details. | ||
11 | */ | ||
12 | #ifndef __ASM_ARCH_MSM_CLKDEV_H | ||
13 | #define __ASM_ARCH_MSM_CLKDEV_H | ||
14 | |||
15 | struct clk; | ||
16 | |||
17 | static inline int __clk_get(struct clk *clk) { return 1; } | ||
18 | static inline void __clk_put(struct clk *clk) { } | ||
19 | #endif | ||
diff --git a/arch/arm/mach-msm/include/mach/cpu.h b/arch/arm/mach-msm/include/mach/cpu.h new file mode 100644 index 000000000000..a9481b08d5c7 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/cpu.h | |||
@@ -0,0 +1,54 @@ | |||
1 | /* Copyright (c) 2011, Code Aurora Forum. All rights reserved. | ||
2 | * | ||
3 | * This program is free software; you can redistribute it and/or modify | ||
4 | * it under the terms of the GNU General Public License version 2 and | ||
5 | * only version 2 as published by the Free Software Foundation. | ||
6 | * | ||
7 | * This program is distributed in the hope that it will be useful, | ||
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | * GNU General Public License for more details. | ||
11 | * | ||
12 | * You should have received a copy of the GNU General Public License | ||
13 | * along with this program; if not, write to the Free Software | ||
14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
15 | * 02110-1301, USA. | ||
16 | */ | ||
17 | |||
18 | #ifndef __ARCH_ARM_MACH_MSM_CPU_H__ | ||
19 | #define __ARCH_ARM_MACH_MSM_CPU_H__ | ||
20 | |||
21 | /* TODO: For now, only one CPU can be compiled at a time. */ | ||
22 | |||
23 | #define cpu_is_msm7x01() 0 | ||
24 | #define cpu_is_msm7x30() 0 | ||
25 | #define cpu_is_qsd8x50() 0 | ||
26 | #define cpu_is_msm8x60() 0 | ||
27 | #define cpu_is_msm8960() 0 | ||
28 | |||
29 | #ifdef CONFIG_ARCH_MSM7X00A | ||
30 | # undef cpu_is_msm7x01 | ||
31 | # define cpu_is_msm7x01() 1 | ||
32 | #endif | ||
33 | |||
34 | #ifdef CONFIG_ARCH_MSM7X30 | ||
35 | # undef cpu_is_msm7x30 | ||
36 | # define cpu_is_msm7x30() 1 | ||
37 | #endif | ||
38 | |||
39 | #ifdef CONFIG_ARCH_QSD8X50 | ||
40 | # undef cpu_is_qsd8x50 | ||
41 | # define cpu_is_qsd8x50() 1 | ||
42 | #endif | ||
43 | |||
44 | #ifdef CONFIG_ARCH_MSM8X60 | ||
45 | # undef cpu_is_msm8x60 | ||
46 | # define cpu_is_msm8x60() 1 | ||
47 | #endif | ||
48 | |||
49 | #ifdef CONFIG_ARCH_MSM8960 | ||
50 | # undef cpu_is_msm8960 | ||
51 | # define cpu_is_msm8960() 1 | ||
52 | #endif | ||
53 | |||
54 | #endif | ||
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h index 7386e732baad..dc1b928745e9 100644 --- a/arch/arm/mach-msm/include/mach/io.h +++ b/arch/arm/mach-msm/include/mach/io.h | |||
@@ -29,6 +29,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m | |||
29 | void msm_map_qsd8x50_io(void); | 29 | void msm_map_qsd8x50_io(void); |
30 | void msm_map_msm7x30_io(void); | 30 | void msm_map_msm7x30_io(void); |
31 | void msm_map_msm8x60_io(void); | 31 | void msm_map_msm8x60_io(void); |
32 | void msm_map_msm8960_io(void); | ||
32 | 33 | ||
33 | extern unsigned int msm_shared_ram_phys; | 34 | extern unsigned int msm_shared_ram_phys; |
34 | 35 | ||
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h index 296c0f10f230..5c7c955e6d25 100644 --- a/arch/arm/mach-msm/include/mach/iommu.h +++ b/arch/arm/mach-msm/include/mach/iommu.h | |||
@@ -1,4 +1,4 @@ | |||
1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | 1 | /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. |
2 | * | 2 | * |
3 | * This program is free software; you can redistribute it and/or modify | 3 | * This program is free software; you can redistribute it and/or modify |
4 | * it under the terms of the GNU General Public License version 2 and | 4 | * it under the terms of the GNU General Public License version 2 and |
@@ -19,6 +19,7 @@ | |||
19 | #define MSM_IOMMU_H | 19 | #define MSM_IOMMU_H |
20 | 20 | ||
21 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
22 | #include <linux/clk.h> | ||
22 | 23 | ||
23 | /* Sharability attributes of MSM IOMMU mappings */ | 24 | /* Sharability attributes of MSM IOMMU mappings */ |
24 | #define MSM_IOMMU_ATTR_NON_SH 0x0 | 25 | #define MSM_IOMMU_ATTR_NON_SH 0x0 |
@@ -44,14 +45,11 @@ | |||
44 | /** | 45 | /** |
45 | * struct msm_iommu_dev - a single IOMMU hardware instance | 46 | * struct msm_iommu_dev - a single IOMMU hardware instance |
46 | * name Human-readable name given to this IOMMU HW instance | 47 | * name Human-readable name given to this IOMMU HW instance |
47 | * clk_rate Rate to set for this IOMMU's clock, if applicable to this | 48 | * ncb Number of context banks present on this IOMMU HW instance |
48 | * particular IOMMU. 0 means don't set a rate. | ||
49 | * -1 means it is an AXI clock with no valid rate | ||
50 | * | ||
51 | */ | 49 | */ |
52 | struct msm_iommu_dev { | 50 | struct msm_iommu_dev { |
53 | const char *name; | 51 | const char *name; |
54 | int clk_rate; | 52 | int ncb; |
55 | }; | 53 | }; |
56 | 54 | ||
57 | /** | 55 | /** |
@@ -73,14 +71,20 @@ struct msm_iommu_ctx_dev { | |||
73 | /** | 71 | /** |
74 | * struct msm_iommu_drvdata - A single IOMMU hardware instance | 72 | * struct msm_iommu_drvdata - A single IOMMU hardware instance |
75 | * @base: IOMMU config port base address (VA) | 73 | * @base: IOMMU config port base address (VA) |
74 | * @ncb The number of contexts on this IOMMU | ||
76 | * @irq: Interrupt number | 75 | * @irq: Interrupt number |
77 | * | 76 | * @clk: The bus clock for this IOMMU hardware instance |
77 | * @pclk: The clock for the IOMMU bus interconnect | ||
78 | * | ||
78 | * A msm_iommu_drvdata holds the global driver data about a single piece | 79 | * A msm_iommu_drvdata holds the global driver data about a single piece |
79 | * of an IOMMU hardware instance. | 80 | * of an IOMMU hardware instance. |
80 | */ | 81 | */ |
81 | struct msm_iommu_drvdata { | 82 | struct msm_iommu_drvdata { |
82 | void __iomem *base; | 83 | void __iomem *base; |
83 | int irq; | 84 | int irq; |
85 | int ncb; | ||
86 | struct clk *clk; | ||
87 | struct clk *pclk; | ||
84 | }; | 88 | }; |
85 | 89 | ||
86 | /** | 90 | /** |
diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h index c2c3da9444f4..fc160101dead 100644 --- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h +++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h | |||
@@ -1,4 +1,4 @@ | |||
1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | 1 | /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. |
2 | * | 2 | * |
3 | * This program is free software; you can redistribute it and/or modify | 3 | * This program is free software; you can redistribute it and/or modify |
4 | * it under the terms of the GNU General Public License version 2 and | 4 | * it under the terms of the GNU General Public License version 2 and |
@@ -68,6 +68,7 @@ do { \ | |||
68 | #define FL_CACHEABLE (1 << 3) | 68 | #define FL_CACHEABLE (1 << 3) |
69 | #define FL_TEX0 (1 << 12) | 69 | #define FL_TEX0 (1 << 12) |
70 | #define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20) | 70 | #define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20) |
71 | #define FL_NG (1 << 17) | ||
71 | 72 | ||
72 | /* Second-level page table bits */ | 73 | /* Second-level page table bits */ |
73 | #define SL_BASE_MASK_LARGE 0xFFFF0000 | 74 | #define SL_BASE_MASK_LARGE 0xFFFF0000 |
@@ -81,6 +82,7 @@ do { \ | |||
81 | #define SL_CACHEABLE (1 << 3) | 82 | #define SL_CACHEABLE (1 << 3) |
82 | #define SL_TEX0 (1 << 6) | 83 | #define SL_TEX0 (1 << 6) |
83 | #define SL_OFFSET(va) (((va) & 0xFF000) >> 12) | 84 | #define SL_OFFSET(va) (((va) & 0xFF000) >> 12) |
85 | #define SL_NG (1 << 11) | ||
84 | 86 | ||
85 | /* Memory type and cache policy attributes */ | 87 | /* Memory type and cache policy attributes */ |
86 | #define MT_SO 0 | 88 | #define MT_SO 0 |
@@ -623,20 +625,6 @@ do { \ | |||
623 | #define SET_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v) | 625 | #define SET_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v) |
624 | 626 | ||
625 | 627 | ||
626 | /* V2Pxx UW UR PW PR */ | ||
627 | #define SET_V2PUW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX, v) | ||
628 | #define SET_V2PUW_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA, v) | ||
629 | |||
630 | #define SET_V2PUR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX, v) | ||
631 | #define SET_V2PUR_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA, v) | ||
632 | |||
633 | #define SET_V2PPW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX, v) | ||
634 | #define SET_V2PPW_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA, v) | ||
635 | |||
636 | #define SET_V2PPR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX, v) | ||
637 | #define SET_V2PPR_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA, v) | ||
638 | |||
639 | |||
640 | /* Context Register getters */ | 628 | /* Context Register getters */ |
641 | /* ACTLR */ | 629 | /* ACTLR */ |
642 | #define GET_CFERE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFERE) | 630 | #define GET_CFERE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFERE) |
@@ -824,20 +812,6 @@ do { \ | |||
824 | #define GET_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, INDEX) | 812 | #define GET_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, INDEX) |
825 | 813 | ||
826 | 814 | ||
827 | /* V2Pxx UW UR PW PR */ | ||
828 | #define GET_V2PUW_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX) | ||
829 | #define GET_V2PUW_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA) | ||
830 | |||
831 | #define GET_V2PUR_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX) | ||
832 | #define GET_V2PUR_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA) | ||
833 | |||
834 | #define GET_V2PPW_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX) | ||
835 | #define GET_V2PPW_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA) | ||
836 | |||
837 | #define GET_V2PPR_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX) | ||
838 | #define GET_V2PPR_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA) | ||
839 | |||
840 | |||
841 | /* Global Registers */ | 815 | /* Global Registers */ |
842 | #define M2VCBR_N (0xFF000) | 816 | #define M2VCBR_N (0xFF000) |
843 | #define CBACR_N (0xFF800) | 817 | #define CBACR_N (0xFF800) |
diff --git a/arch/arm/mach-msm/include/mach/irqs-7x30.h b/arch/arm/mach-msm/include/mach/irqs-7x30.h index 67c5396514fe..1f15902655fd 100644 --- a/arch/arm/mach-msm/include/mach/irqs-7x30.h +++ b/arch/arm/mach-msm/include/mach/irqs-7x30.h | |||
@@ -1,30 +1,13 @@ | |||
1 | /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. | 1 | /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. |
2 | * | 2 | * |
3 | * Redistribution and use in source and binary forms, with or without | 3 | * This program is free software; you can redistribute it and/or modify |
4 | * modification, are permitted provided that the following conditions are | 4 | * it under the terms of the GNU General Public License version 2 and |
5 | * met: | 5 | * only version 2 as published by the Free Software Foundation. |
6 | * * Redistributions of source code must retain the above copyright | ||
7 | * notice, this list of conditions and the following disclaimer. | ||
8 | * * Redistributions in binary form must reproduce the above | ||
9 | * copyright notice, this list of conditions and the following | ||
10 | * disclaimer in the documentation and/or other materials provided | ||
11 | * with the distribution. | ||
12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its | ||
13 | * contributors may be used to endorse or promote products derived | ||
14 | * from this software without specific prior written permission. | ||
15 | * | ||
16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | ||
17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT | ||
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS | ||
20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
27 | * | 6 | * |
7 | * This program is distributed in the hope that it will be useful, | ||
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | * GNU General Public License for more details. | ||
28 | */ | 11 | */ |
29 | 12 | ||
30 | #ifndef __ASM_ARCH_MSM_IRQS_7X30_H | 13 | #ifndef __ASM_ARCH_MSM_IRQS_7X30_H |
diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h new file mode 100644 index 000000000000..81ab2a6792bd --- /dev/null +++ b/arch/arm/mach-msm/include/mach/irqs-8960.h | |||
@@ -0,0 +1,277 @@ | |||
1 | /* Copyright (c) 2011 Code Aurora Forum. All rights reserved. | ||
2 | * | ||
3 | * This program is free software; you can redistribute it and/or modify | ||
4 | * it under the terms of the GNU General Public License version 2 and | ||
5 | * only version 2 as published by the Free Software Foundation. | ||
6 | * | ||
7 | * This program is distributed in the hope that it will be useful, | ||
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | * GNU General Public License for more details. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_MSM_IRQS_8960_H | ||
14 | #define __ASM_ARCH_MSM_IRQS_8960_H | ||
15 | |||
16 | /* MSM ACPU Interrupt Numbers */ | ||
17 | |||
18 | /* 0-15: STI/SGI (software triggered/generated interrupts) | ||
19 | 16-31: PPI (private peripheral interrupts) | ||
20 | 32+: SPI (shared peripheral interrupts) */ | ||
21 | |||
22 | #define GIC_PPI_START 16 | ||
23 | #define GIC_SPI_START 32 | ||
24 | |||
25 | #define INT_VGIC (GIC_PPI_START + 0) | ||
26 | #define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1) | ||
27 | #define INT_GP_TIMER_EXP (GIC_PPI_START + 2) | ||
28 | #define INT_GP_TIMER2_EXP (GIC_PPI_START + 3) | ||
29 | #define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 4) | ||
30 | #define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 5) | ||
31 | #define AVS_SVICINT (GIC_PPI_START + 6) | ||
32 | #define AVS_SVICINTSWDONE (GIC_PPI_START + 7) | ||
33 | #define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 8) | ||
34 | #define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 9) | ||
35 | #define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 10) | ||
36 | #define SC_AVSCPUXDOWN (GIC_PPI_START + 11) | ||
37 | #define SC_AVSCPUXUP (GIC_PPI_START + 12) | ||
38 | #define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 13) | ||
39 | #define SC_SICCPUXEXTFAULTIRPTREQ (GIC_PPI_START + 14) | ||
40 | /* PPI 15 is unused */ | ||
41 | |||
42 | #define SC_SICMPUIRPTREQ (GIC_SPI_START + 0) | ||
43 | #define SC_SICL2IRPTREQ (GIC_SPI_START + 1) | ||
44 | #define SC_SICL2PERFMONIRPTREQ (GIC_SPI_START + 2) | ||
45 | #define SC_SICAGCIRPTREQ (GIC_SPI_START + 3) | ||
46 | #define TLMM_APCC_DIR_CONN_IRQ_0 (GIC_SPI_START + 4) | ||
47 | #define TLMM_APCC_DIR_CONN_IRQ_1 (GIC_SPI_START + 5) | ||
48 | #define TLMM_APCC_DIR_CONN_IRQ_2 (GIC_SPI_START + 6) | ||
49 | #define TLMM_APCC_DIR_CONN_IRQ_3 (GIC_SPI_START + 7) | ||
50 | #define TLMM_APCC_DIR_CONN_IRQ_4 (GIC_SPI_START + 8) | ||
51 | #define TLMM_APCC_DIR_CONN_IRQ_5 (GIC_SPI_START + 9) | ||
52 | #define TLMM_APCC_DIR_CONN_IRQ_6 (GIC_SPI_START + 10) | ||
53 | #define TLMM_APCC_DIR_CONN_IRQ_7 (GIC_SPI_START + 11) | ||
54 | #define TLMM_APCC_DIR_CONN_IRQ_8 (GIC_SPI_START + 12) | ||
55 | #define TLMM_APCC_DIR_CONN_IRQ_9 (GIC_SPI_START + 13) | ||
56 | #define PM8921_SEC_IRQ_103 (GIC_SPI_START + 14) | ||
57 | #define PM8018_SEC_IRQ_106 (GIC_SPI_START + 15) | ||
58 | #define TLMM_APCC_SUMMARY_IRQ (GIC_SPI_START + 16) | ||
59 | #define SPDM_RT_1_IRQ (GIC_SPI_START + 17) | ||
60 | #define SPDM_DIAG_IRQ (GIC_SPI_START + 18) | ||
61 | #define RPM_APCC_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19) | ||
62 | #define RPM_APCC_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20) | ||
63 | #define RPM_APCC_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21) | ||
64 | #define RPM_APCC_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22) | ||
65 | #define RPM_APCC_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23) | ||
66 | #define RPM_APCC_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24) | ||
67 | #define RPM_APCC_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25) | ||
68 | #define RPM_APCC_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26) | ||
69 | #define SSBI2_2_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 27) | ||
70 | #define SSBI2_2_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 28) | ||
71 | #define SSBI2_1_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 29) | ||
72 | #define SSBI2_1_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 30) | ||
73 | #define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31) | ||
74 | #define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32) | ||
75 | #define SLIMBUS0_CORE_EE1_IRQ (GIC_SPI_START + 33) | ||
76 | #define SLIMBUS0_BAM_EE1_IRQ (GIC_SPI_START + 34) | ||
77 | #define Q6FW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 35) | ||
78 | #define Q6SW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 36) | ||
79 | #define MSS_TO_APPS_IRQ_0 (GIC_SPI_START + 37) | ||
80 | #define MSS_TO_APPS_IRQ_1 (GIC_SPI_START + 38) | ||
81 | #define MSS_TO_APPS_IRQ_2 (GIC_SPI_START + 39) | ||
82 | #define MSS_TO_APPS_IRQ_3 (GIC_SPI_START + 40) | ||
83 | #define MSS_TO_APPS_IRQ_4 (GIC_SPI_START + 41) | ||
84 | #define MSS_TO_APPS_IRQ_5 (GIC_SPI_START + 42) | ||
85 | #define MSS_TO_APPS_IRQ_6 (GIC_SPI_START + 43) | ||
86 | #define MSS_TO_APPS_IRQ_7 (GIC_SPI_START + 44) | ||
87 | #define MSS_TO_APPS_IRQ_8 (GIC_SPI_START + 45) | ||
88 | #define MSS_TO_APPS_IRQ_9 (GIC_SPI_START + 46) | ||
89 | #define VPE_IRQ (GIC_SPI_START + 47) | ||
90 | #define VFE_IRQ (GIC_SPI_START + 48) | ||
91 | #define VCODEC_IRQ (GIC_SPI_START + 49) | ||
92 | #define TV_ENC_IRQ (GIC_SPI_START + 50) | ||
93 | #define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51) | ||
94 | #define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52) | ||
95 | #define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53) | ||
96 | #define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54) | ||
97 | #define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55) | ||
98 | #define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56) | ||
99 | #define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57) | ||
100 | #define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58) | ||
101 | #define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59) | ||
102 | #define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60) | ||
103 | #define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61) | ||
104 | #define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62) | ||
105 | #define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63) | ||
106 | #define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64) | ||
107 | #define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65) | ||
108 | #define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66) | ||
109 | #define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67) | ||
110 | #define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68) | ||
111 | #define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69) | ||
112 | #define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70) | ||
113 | #define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71) | ||
114 | #define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72) | ||
115 | #define ROT_IRQ (GIC_SPI_START + 73) | ||
116 | #define MMSS_FABRIC_IRQ (GIC_SPI_START + 74) | ||
117 | #define MDP_IRQ (GIC_SPI_START + 75) | ||
118 | #define JPEGD_IRQ (GIC_SPI_START + 76) | ||
119 | #define JPEG_IRQ (GIC_SPI_START + 77) | ||
120 | #define MMSS_IMEM_IRQ (GIC_SPI_START + 78) | ||
121 | #define HDMI_IRQ (GIC_SPI_START + 79) | ||
122 | #define GFX3D_IRQ (GIC_SPI_START + 80) | ||
123 | #define GFX2D0_IRQ (GIC_SPI_START + 81) | ||
124 | #define DSI1_IRQ (GIC_SPI_START + 82) | ||
125 | #define CSI_1_IRQ (GIC_SPI_START + 83) | ||
126 | #define CSI_0_IRQ (GIC_SPI_START + 84) | ||
127 | #define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85) | ||
128 | #define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86) | ||
129 | #define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87) | ||
130 | #define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88) | ||
131 | #define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89) | ||
132 | #define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90) | ||
133 | #define TOP_IMEM_IRQ (GIC_SPI_START + 91) | ||
134 | #define FABRIC_SYS_IRQ (GIC_SPI_START + 92) | ||
135 | #define FABRIC_APPS_IRQ (GIC_SPI_START + 93) | ||
136 | #define USB1_HS_BAM_IRQ (GIC_SPI_START + 94) | ||
137 | #define SDC4_BAM_IRQ (GIC_SPI_START + 95) | ||
138 | #define SDC3_BAM_IRQ (GIC_SPI_START + 96) | ||
139 | #define SDC2_BAM_IRQ (GIC_SPI_START + 97) | ||
140 | #define SDC1_BAM_IRQ (GIC_SPI_START + 98) | ||
141 | #define FABRIC_SPS_IRQ (GIC_SPI_START + 99) | ||
142 | #define USB1_HS_IRQ (GIC_SPI_START + 100) | ||
143 | #define SDC4_IRQ_0 (GIC_SPI_START + 101) | ||
144 | #define SDC3_IRQ_0 (GIC_SPI_START + 102) | ||
145 | #define SDC2_IRQ_0 (GIC_SPI_START + 103) | ||
146 | #define SDC1_IRQ_0 (GIC_SPI_START + 104) | ||
147 | #define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105) | ||
148 | #define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106) | ||
149 | #define SPS_MTI_0 (GIC_SPI_START + 107) | ||
150 | #define SPS_MTI_1 (GIC_SPI_START + 108) | ||
151 | #define SPS_MTI_2 (GIC_SPI_START + 109) | ||
152 | #define SPS_MTI_3 (GIC_SPI_START + 110) | ||
153 | #define SPS_MTI_4 (GIC_SPI_START + 111) | ||
154 | #define SPS_MTI_5 (GIC_SPI_START + 112) | ||
155 | #define SPS_MTI_6 (GIC_SPI_START + 113) | ||
156 | #define SPS_MTI_7 (GIC_SPI_START + 114) | ||
157 | #define SPS_MTI_8 (GIC_SPI_START + 115) | ||
158 | #define SPS_MTI_9 (GIC_SPI_START + 116) | ||
159 | #define SPS_MTI_10 (GIC_SPI_START + 117) | ||
160 | #define SPS_MTI_11 (GIC_SPI_START + 118) | ||
161 | #define SPS_MTI_12 (GIC_SPI_START + 119) | ||
162 | #define SPS_MTI_13 (GIC_SPI_START + 120) | ||
163 | #define SPS_MTI_14 (GIC_SPI_START + 121) | ||
164 | #define SPS_MTI_15 (GIC_SPI_START + 122) | ||
165 | #define SPS_MTI_16 (GIC_SPI_START + 123) | ||
166 | #define SPS_MTI_17 (GIC_SPI_START + 124) | ||
167 | #define SPS_MTI_18 (GIC_SPI_START + 125) | ||
168 | #define SPS_MTI_19 (GIC_SPI_START + 126) | ||
169 | #define SPS_MTI_20 (GIC_SPI_START + 127) | ||
170 | #define SPS_MTI_21 (GIC_SPI_START + 128) | ||
171 | #define SPS_MTI_22 (GIC_SPI_START + 129) | ||
172 | #define SPS_MTI_23 (GIC_SPI_START + 130) | ||
173 | #define SPS_MTI_24 (GIC_SPI_START + 131) | ||
174 | #define SPS_MTI_25 (GIC_SPI_START + 132) | ||
175 | #define SPS_MTI_26 (GIC_SPI_START + 133) | ||
176 | #define SPS_MTI_27 (GIC_SPI_START + 134) | ||
177 | #define SPS_MTI_28 (GIC_SPI_START + 135) | ||
178 | #define SPS_MTI_29 (GIC_SPI_START + 136) | ||
179 | #define SPS_MTI_30 (GIC_SPI_START + 137) | ||
180 | #define SPS_MTI_31 (GIC_SPI_START + 138) | ||
181 | #define CSIPHY_4LN_IRQ (GIC_SPI_START + 139) | ||
182 | #define CSIPHY_2LN_IRQ (GIC_SPI_START + 140) | ||
183 | #define USB2_IRQ (GIC_SPI_START + 141) | ||
184 | #define USB1_IRQ (GIC_SPI_START + 142) | ||
185 | #define TSSC_SSBI_IRQ (GIC_SPI_START + 143) | ||
186 | #define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144) | ||
187 | #define TSSC_PENUP_IRQ (GIC_SPI_START + 145) | ||
188 | #define GSBI1_UARTDM_IRQ (GIC_SPI_START + 146) | ||
189 | #define GSBI1_QUP_IRQ (GIC_SPI_START + 147) | ||
190 | #define GSBI2_UARTDM_IRQ (GIC_SPI_START + 148) | ||
191 | #define GSBI2_QUP_IRQ (GIC_SPI_START + 149) | ||
192 | #define GSBI3_UARTDM_IRQ (GIC_SPI_START + 150) | ||
193 | #define GSBI3_QUP_IRQ (GIC_SPI_START + 151) | ||
194 | #define GSBI4_UARTDM_IRQ (GIC_SPI_START + 152) | ||
195 | #define GSBI4_QUP_IRQ (GIC_SPI_START + 153) | ||
196 | #define GSBI5_UARTDM_IRQ (GIC_SPI_START + 154) | ||
197 | #define GSBI5_QUP_IRQ (GIC_SPI_START + 155) | ||
198 | #define GSBI6_UARTDM_IRQ (GIC_SPI_START + 156) | ||
199 | #define GSBI6_QUP_IRQ (GIC_SPI_START + 157) | ||
200 | #define GSBI7_UARTDM_IRQ (GIC_SPI_START + 158) | ||
201 | #define GSBI7_QUP_IRQ (GIC_SPI_START + 159) | ||
202 | #define GSBI8_UARTDM_IRQ (GIC_SPI_START + 160) | ||
203 | #define GSBI8_QUP_IRQ (GIC_SPI_START + 161) | ||
204 | #define TSIF_TSPP_IRQ (GIC_SPI_START + 162) | ||
205 | #define TSIF_BAM_IRQ (GIC_SPI_START + 163) | ||
206 | #define TSIF2_IRQ (GIC_SPI_START + 164) | ||
207 | #define TSIF1_IRQ (GIC_SPI_START + 165) | ||
208 | #define DSI2_IRQ (GIC_SPI_START + 166) | ||
209 | #define ISPIF_IRQ (GIC_SPI_START + 167) | ||
210 | #define MSMC_SC_SEC_TMR_IRQ (GIC_SPI_START + 168) | ||
211 | #define MSMC_SC_SEC_WDOG_BARK_IRQ (GIC_SPI_START + 169) | ||
212 | #define INT_ADM0_SCSS_0_IRQ (GIC_SPI_START + 170) | ||
213 | #define INT_ADM0_SCSS_1_IRQ (GIC_SPI_START + 171) | ||
214 | #define INT_ADM0_SCSS_2_IRQ (GIC_SPI_START + 172) | ||
215 | #define INT_ADM0_SCSS_3_IRQ (GIC_SPI_START + 173) | ||
216 | #define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174) | ||
217 | #define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175) | ||
218 | #define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176) | ||
219 | #define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177) | ||
220 | #define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178) | ||
221 | #define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179) | ||
222 | #define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180) | ||
223 | #define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181) | ||
224 | #define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182) | ||
225 | #define XPU_SUMMARY_IRQ (GIC_SPI_START + 183) | ||
226 | #define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184) | ||
227 | #define HSDDRX_EBI1CH0_IRQ (GIC_SPI_START + 185) | ||
228 | #define HSDDRX_EBI1CH1_IRQ (GIC_SPI_START + 186) | ||
229 | #define SDC5_BAM_IRQ (GIC_SPI_START + 187) | ||
230 | #define SDC5_IRQ_0 (GIC_SPI_START + 188) | ||
231 | #define GSBI9_UARTDM_IRQ (GIC_SPI_START + 189) | ||
232 | #define GSBI9_QUP_IRQ (GIC_SPI_START + 190) | ||
233 | #define GSBI10_UARTDM_IRQ (GIC_SPI_START + 191) | ||
234 | #define GSBI10_QUP_IRQ (GIC_SPI_START + 192) | ||
235 | #define GSBI11_UARTDM_IRQ (GIC_SPI_START + 193) | ||
236 | #define GSBI11_QUP_IRQ (GIC_SPI_START + 194) | ||
237 | #define GSBI12_UARTDM_IRQ (GIC_SPI_START + 195) | ||
238 | #define GSBI12_QUP_IRQ (GIC_SPI_START + 196) | ||
239 | #define RIVA_APSS_LTECOEX_IRQ (GIC_SPI_START + 197) | ||
240 | #define RIVA_APSS_SPARE_IRQ (GIC_SPI_START + 198) | ||
241 | #define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ (GIC_SPI_START + 199) | ||
242 | #define RIVA_ASS_RESET_DONE_IRQ (GIC_SPI_START + 200) | ||
243 | #define RIVA_APSS_ASIC_IRQ (GIC_SPI_START + 201) | ||
244 | #define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ (GIC_SPI_START + 202) | ||
245 | #define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ (GIC_SPI_START + 203) | ||
246 | #define RIVA_APPS_WLAM_SMSM_IRQ (GIC_SPI_START + 204) | ||
247 | #define RIVA_APPS_LOG_CTRL_IRQ (GIC_SPI_START + 205) | ||
248 | #define RIVA_APPS_FM_CTRL_IRQ (GIC_SPI_START + 206) | ||
249 | #define RIVA_APPS_HCI_IRQ (GIC_SPI_START + 207) | ||
250 | #define RIVA_APPS_WLAN_CTRL_IRQ (GIC_SPI_START + 208) | ||
251 | #define A2_BAM_IRQ (GIC_SPI_START + 209) | ||
252 | #define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210) | ||
253 | #define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211) | ||
254 | #define GFX2D1_IRQ (GIC_SPI_START + 212) | ||
255 | #define PPSS_WDOG_TIMER_IRQ (GIC_SPI_START + 213) | ||
256 | #define SPS_SLIMBUS_CORE_EE0_IRQ (GIC_SPI_START + 214) | ||
257 | #define SPS_SLIMBUS_BAM_EE0_IRQ (GIC_SPI_START + 215) | ||
258 | #define QDSS_ETB_IRQ (GIC_SPI_START + 216) | ||
259 | #define QDSS_CTI2KPSS_CPU1_IRQ (GIC_SPI_START + 217) | ||
260 | #define QDSS_CTI2KPSS_CPU0_IRQ (GIC_SPI_START + 218) | ||
261 | #define TLMM_APCC_DIR_CONN_IRQ_16 (GIC_SPI_START + 219) | ||
262 | #define TLMM_APCC_DIR_CONN_IRQ_17 (GIC_SPI_START + 220) | ||
263 | #define TLMM_APCC_DIR_CONN_IRQ_18 (GIC_SPI_START + 221) | ||
264 | #define TLMM_APCC_DIR_CONN_IRQ_19 (GIC_SPI_START + 222) | ||
265 | #define TLMM_APCC_DIR_CONN_IRQ_20 (GIC_SPI_START + 223) | ||
266 | #define TLMM_APCC_DIR_CONN_IRQ_21 (GIC_SPI_START + 224) | ||
267 | #define PM8921_SEC_IRQ_104 (GIC_SPI_START + 225) | ||
268 | #define PM8018_SEC_IRQ_107 (GIC_SPI_START + 226) | ||
269 | |||
270 | /* For now, use the maximum number of interrupts until a pending GIC issue | ||
271 | * is sorted out */ | ||
272 | #define NR_MSM_IRQS 1020 | ||
273 | #define NR_BOARD_IRQS 0 | ||
274 | #define NR_GPIO_IRQS 0 | ||
275 | |||
276 | #endif | ||
277 | |||
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x50.h b/arch/arm/mach-msm/include/mach/irqs-8x50.h index de3d8fe24e4e..26adbe0e9406 100644 --- a/arch/arm/mach-msm/include/mach/irqs-8x50.h +++ b/arch/arm/mach-msm/include/mach/irqs-8x50.h | |||
@@ -1,30 +1,13 @@ | |||
1 | /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. | 1 | /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. |
2 | * | 2 | * |
3 | * Redistribution and use in source and binary forms, with or without | 3 | * This program is free software; you can redistribute it and/or modify |
4 | * modification, are permitted provided that the following conditions are | 4 | * it under the terms of the GNU General Public License version 2 and |
5 | * met: | 5 | * only version 2 as published by the Free Software Foundation. |
6 | * * Redistributions of source code must retain the above copyright | ||
7 | * notice, this list of conditions and the following disclaimer. | ||
8 | * * Redistributions in binary form must reproduce the above | ||
9 | * copyright notice, this list of conditions and the following | ||
10 | * disclaimer in the documentation and/or other materials provided | ||
11 | * with the distribution. | ||
12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its | ||
13 | * contributors may be used to endorse or promote products derived | ||
14 | * from this software without specific prior written permission. | ||
15 | * | ||
16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | ||
17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT | ||
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS | ||
20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
27 | * | 6 | * |
7 | * This program is distributed in the hope that it will be useful, | ||
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | * GNU General Public License for more details. | ||
28 | */ | 11 | */ |
29 | 12 | ||
30 | #ifndef __ASM_ARCH_MSM_IRQS_8XXX_H | 13 | #ifndef __ASM_ARCH_MSM_IRQS_8XXX_H |
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h index 8679a4564744..3cd78b165abb 100644 --- a/arch/arm/mach-msm/include/mach/irqs.h +++ b/arch/arm/mach-msm/include/mach/irqs.h | |||
@@ -26,6 +26,9 @@ | |||
26 | #include "sirc.h" | 26 | #include "sirc.h" |
27 | #elif defined(CONFIG_ARCH_MSM8X60) | 27 | #elif defined(CONFIG_ARCH_MSM8X60) |
28 | #include "irqs-8x60.h" | 28 | #include "irqs-8x60.h" |
29 | #elif defined(CONFIG_ARCH_MSM8960) | ||
30 | /* TODO: Make these not generic. */ | ||
31 | #include "irqs-8960.h" | ||
29 | #elif defined(CONFIG_ARCH_MSM_ARM11) | 32 | #elif defined(CONFIG_ARCH_MSM_ARM11) |
30 | #include "irqs-7x00.h" | 33 | #include "irqs-7x00.h" |
31 | #else | 34 | #else |
diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h index 176875df241f..f2f8d299ba95 100644 --- a/arch/arm/mach-msm/include/mach/memory.h +++ b/arch/arm/mach-msm/include/mach/memory.h | |||
@@ -25,6 +25,8 @@ | |||
25 | #define PLAT_PHYS_OFFSET UL(0x00200000) | 25 | #define PLAT_PHYS_OFFSET UL(0x00200000) |
26 | #elif defined(CONFIG_ARCH_MSM8X60) | 26 | #elif defined(CONFIG_ARCH_MSM8X60) |
27 | #define PLAT_PHYS_OFFSET UL(0x40200000) | 27 | #define PLAT_PHYS_OFFSET UL(0x40200000) |
28 | #elif defined(CONFIG_ARCH_MSM8960) | ||
29 | #define PLAT_PHYS_OFFSET UL(0x40200000) | ||
28 | #else | 30 | #else |
29 | #define PLAT_PHYS_OFFSET UL(0x10000000) | 31 | #define PLAT_PHYS_OFFSET UL(0x10000000) |
30 | #endif | 32 | #endif |
diff --git a/arch/arm/mach-msm/include/mach/mmc.h b/arch/arm/mach-msm/include/mach/mmc.h index d54b6b086cff..5631b51cec46 100644 --- a/arch/arm/mach-msm/include/mach/mmc.h +++ b/arch/arm/mach-msm/include/mach/mmc.h | |||
@@ -15,12 +15,23 @@ struct embedded_sdio_data { | |||
15 | int num_funcs; | 15 | int num_funcs; |
16 | }; | 16 | }; |
17 | 17 | ||
18 | struct msm_mmc_gpio { | ||
19 | unsigned no; | ||
20 | const char *name; | ||
21 | }; | ||
22 | |||
23 | struct msm_mmc_gpio_data { | ||
24 | struct msm_mmc_gpio *gpio; | ||
25 | u8 size; | ||
26 | }; | ||
27 | |||
18 | struct msm_mmc_platform_data { | 28 | struct msm_mmc_platform_data { |
19 | unsigned int ocr_mask; /* available voltages */ | 29 | unsigned int ocr_mask; /* available voltages */ |
20 | u32 (*translate_vdd)(struct device *, unsigned int); | 30 | u32 (*translate_vdd)(struct device *, unsigned int); |
21 | unsigned int (*status)(struct device *); | 31 | unsigned int (*status)(struct device *); |
22 | struct embedded_sdio_data *embedded_sdio; | 32 | struct embedded_sdio_data *embedded_sdio; |
23 | int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id); | 33 | int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id); |
34 | struct msm_mmc_gpio_data *gpio_data; | ||
24 | }; | 35 | }; |
25 | 36 | ||
26 | #endif | 37 | #endif |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h index cfff0e74f128..8f99d97615a0 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h | |||
@@ -1,6 +1,7 @@ | |||
1 | /* arch/arm/mach-msm/include/mach/msm_iomap.h | 1 | /* arch/arm/mach-msm/include/mach/msm_iomap.h |
2 | * | 2 | * |
3 | * Copyright (C) 2007 Google, Inc. | 3 | * Copyright (C) 2007 Google, Inc. |
4 | * Copyright (c) 2011, Code Aurora Forum. All rights reserved. | ||
4 | * Author: Brian Swetland <swetland@google.com> | 5 | * Author: Brian Swetland <swetland@google.com> |
5 | * | 6 | * |
6 | * This software is licensed under the terms of the GNU General Public | 7 | * This software is licensed under the terms of the GNU General Public |
@@ -47,13 +48,8 @@ | |||
47 | #define MSM_VIC_PHYS 0xC0000000 | 48 | #define MSM_VIC_PHYS 0xC0000000 |
48 | #define MSM_VIC_SIZE SZ_4K | 49 | #define MSM_VIC_SIZE SZ_4K |
49 | 50 | ||
50 | #define MSM_CSR_BASE IOMEM(0xE0001000) | 51 | #define MSM7X00_CSR_PHYS 0xC0100000 |
51 | #define MSM_CSR_PHYS 0xC0100000 | 52 | #define MSM7X00_CSR_SIZE SZ_4K |
52 | #define MSM_CSR_SIZE SZ_4K | ||
53 | |||
54 | #define MSM_GPT_PHYS MSM_CSR_PHYS | ||
55 | #define MSM_GPT_BASE MSM_CSR_BASE | ||
56 | #define MSM_GPT_SIZE SZ_4K | ||
57 | 53 | ||
58 | #define MSM_DMOV_BASE IOMEM(0xE0002000) | 54 | #define MSM_DMOV_BASE IOMEM(0xE0002000) |
59 | #define MSM_DMOV_PHYS 0xA9700000 | 55 | #define MSM_DMOV_PHYS 0xA9700000 |
@@ -130,10 +126,4 @@ | |||
130 | #define MSM_AD5_SIZE (SZ_1M*13) | 126 | #define MSM_AD5_SIZE (SZ_1M*13) |
131 | 127 | ||
132 | 128 | ||
133 | #if defined(CONFIG_ARCH_MSM7X30) | ||
134 | #define MSM_GCC_BASE IOMEM(0xF8009000) | ||
135 | #define MSM_GCC_PHYS 0xC0182000 | ||
136 | #define MSM_GCC_SIZE SZ_4K | ||
137 | #endif | ||
138 | |||
139 | #endif | 129 | #endif |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h index 0fd7b68ca114..4d84be15955e 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h | |||
@@ -1,6 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2007 Google, Inc. | 2 | * Copyright (C) 2007 Google, Inc. |
3 | * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. | 3 | * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved. |
4 | * Author: Brian Swetland <swetland@google.com> | 4 | * Author: Brian Swetland <swetland@google.com> |
5 | * | 5 | * |
6 | * This software is licensed under the terms of the GNU General Public | 6 | * This software is licensed under the terms of the GNU General Public |
@@ -39,16 +39,8 @@ | |||
39 | #define MSM_VIC_PHYS 0xC0080000 | 39 | #define MSM_VIC_PHYS 0xC0080000 |
40 | #define MSM_VIC_SIZE SZ_4K | 40 | #define MSM_VIC_SIZE SZ_4K |
41 | 41 | ||
42 | #define MSM_CSR_BASE IOMEM(0xE0001000) | 42 | #define MSM7X30_CSR_PHYS 0xC0100000 |
43 | #define MSM_CSR_PHYS 0xC0100000 | 43 | #define MSM7X30_CSR_SIZE SZ_4K |
44 | #define MSM_CSR_SIZE SZ_4K | ||
45 | |||
46 | #define MSM_TMR_PHYS MSM_CSR_PHYS | ||
47 | #define MSM_TMR_BASE MSM_CSR_BASE | ||
48 | #define MSM_TMR_SIZE SZ_4K | ||
49 | |||
50 | #define MSM_GPT_BASE (MSM_TMR_BASE + 0x4) | ||
51 | #define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) | ||
52 | 44 | ||
53 | #define MSM_DMOV_BASE IOMEM(0xE0002000) | 45 | #define MSM_DMOV_BASE IOMEM(0xE0002000) |
54 | #define MSM_DMOV_PHYS 0xAC400000 | 46 | #define MSM_DMOV_PHYS 0xAC400000 |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h new file mode 100644 index 000000000000..3c9d9602a318 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h | |||
@@ -0,0 +1,48 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2007 Google, Inc. | ||
3 | * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. | ||
4 | * Author: Brian Swetland <swetland@google.com> | ||
5 | * | ||
6 | * This software is licensed under the terms of the GNU General Public | ||
7 | * License version 2, as published by the Free Software Foundation, and | ||
8 | * may be copied, distributed, and modified under those terms. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * | ||
16 | * The MSM peripherals are spread all over across 768MB of physical | ||
17 | * space, which makes just having a simple IO_ADDRESS macro to slide | ||
18 | * them into the right virtual location rough. Instead, we will | ||
19 | * provide a master phys->virt mapping for peripherals here. | ||
20 | * | ||
21 | */ | ||
22 | |||
23 | #ifndef __ASM_ARCH_MSM_IOMAP_8960_H | ||
24 | #define __ASM_ARCH_MSM_IOMAP_8960_H | ||
25 | |||
26 | /* Physical base address and size of peripherals. | ||
27 | * Ordered by the virtual base addresses they will be mapped at. | ||
28 | * | ||
29 | * If you add or remove entries here, you'll want to edit the | ||
30 | * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your | ||
31 | * changes. | ||
32 | * | ||
33 | */ | ||
34 | |||
35 | |||
36 | #define MSM8960_QGIC_DIST_PHYS 0x02000000 | ||
37 | #define MSM8960_QGIC_DIST_SIZE SZ_4K | ||
38 | |||
39 | #define MSM8960_QGIC_CPU_PHYS 0x02002000 | ||
40 | #define MSM8960_QGIC_CPU_SIZE SZ_4K | ||
41 | |||
42 | #define MSM8960_TMR_PHYS 0x0200A000 | ||
43 | #define MSM8960_TMR_SIZE SZ_4K | ||
44 | |||
45 | #define MSM8960_TMR0_PHYS 0x0208A000 | ||
46 | #define MSM8960_TMR0_SIZE SZ_4K | ||
47 | |||
48 | #endif | ||
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h index acc819eb76e5..d4143201999f 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h | |||
@@ -1,6 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2007 Google, Inc. | 2 | * Copyright (C) 2007 Google, Inc. |
3 | * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. | 3 | * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved. |
4 | * Author: Brian Swetland <swetland@google.com> | 4 | * Author: Brian Swetland <swetland@google.com> |
5 | * | 5 | * |
6 | * This software is licensed under the terms of the GNU General Public | 6 | * This software is licensed under the terms of the GNU General Public |
@@ -39,16 +39,8 @@ | |||
39 | #define MSM_VIC_PHYS 0xAC000000 | 39 | #define MSM_VIC_PHYS 0xAC000000 |
40 | #define MSM_VIC_SIZE SZ_4K | 40 | #define MSM_VIC_SIZE SZ_4K |
41 | 41 | ||
42 | #define MSM_CSR_BASE IOMEM(0xE0001000) | 42 | #define QSD8X50_CSR_PHYS 0xAC100000 |
43 | #define MSM_CSR_PHYS 0xAC100000 | 43 | #define QSD8X50_CSR_SIZE SZ_4K |
44 | #define MSM_CSR_SIZE SZ_4K | ||
45 | |||
46 | #define MSM_TMR_PHYS MSM_CSR_PHYS | ||
47 | #define MSM_TMR_BASE MSM_CSR_BASE | ||
48 | #define MSM_TMR_SIZE SZ_4K | ||
49 | |||
50 | #define MSM_GPT_BASE MSM_TMR_BASE | ||
51 | #define MSM_DGT_BASE (MSM_TMR_BASE + 0x10) | ||
52 | 44 | ||
53 | #define MSM_DMOV_BASE IOMEM(0xE0002000) | 45 | #define MSM_DMOV_BASE IOMEM(0xE0002000) |
54 | #define MSM_DMOV_PHYS 0xA9700000 | 46 | #define MSM_DMOV_PHYS 0xA9700000 |
@@ -132,16 +124,16 @@ | |||
132 | #define MSM_UART2DM_PHYS 0xA0900000 | 124 | #define MSM_UART2DM_PHYS 0xA0900000 |
133 | 125 | ||
134 | 126 | ||
135 | #define MSM_SDC1_PHYS 0xA0400000 | 127 | #define MSM_SDC1_PHYS 0xA0300000 |
136 | #define MSM_SDC1_SIZE SZ_4K | 128 | #define MSM_SDC1_SIZE SZ_4K |
137 | 129 | ||
138 | #define MSM_SDC2_PHYS 0xA0500000 | 130 | #define MSM_SDC2_PHYS 0xA0400000 |
139 | #define MSM_SDC2_SIZE SZ_4K | 131 | #define MSM_SDC2_SIZE SZ_4K |
140 | 132 | ||
141 | #define MSM_SDC3_PHYS 0xA0600000 | 133 | #define MSM_SDC3_PHYS 0xA0500000 |
142 | #define MSM_SDC3_SIZE SZ_4K | 134 | #define MSM_SDC3_SIZE SZ_4K |
143 | 135 | ||
144 | #define MSM_SDC4_PHYS 0xA0700000 | 136 | #define MSM_SDC4_PHYS 0xA0600000 |
145 | #define MSM_SDC4_SIZE SZ_4K | 137 | #define MSM_SDC4_SIZE SZ_4K |
146 | 138 | ||
147 | #endif | 139 | #endif |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index a54e33b0882e..3b19b8f244b8 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | |||
@@ -1,6 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2007 Google, Inc. | 2 | * Copyright (C) 2007 Google, Inc. |
3 | * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. | 3 | * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. |
4 | * Author: Brian Swetland <swetland@google.com> | 4 | * Author: Brian Swetland <swetland@google.com> |
5 | * | 5 | * |
6 | * This software is licensed under the terms of the GNU General Public | 6 | * This software is licensed under the terms of the GNU General Public |
@@ -35,13 +35,11 @@ | |||
35 | * | 35 | * |
36 | */ | 36 | */ |
37 | 37 | ||
38 | #define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) | 38 | #define MSM8X60_QGIC_DIST_PHYS 0x02080000 |
39 | #define MSM_QGIC_DIST_PHYS 0x02080000 | 39 | #define MSM8X60_QGIC_DIST_SIZE SZ_4K |
40 | #define MSM_QGIC_DIST_SIZE SZ_4K | ||
41 | 40 | ||
42 | #define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) | 41 | #define MSM8X60_QGIC_CPU_PHYS 0x02081000 |
43 | #define MSM_QGIC_CPU_PHYS 0x02081000 | 42 | #define MSM8X60_QGIC_CPU_SIZE SZ_4K |
44 | #define MSM_QGIC_CPU_SIZE SZ_4K | ||
45 | 43 | ||
46 | #define MSM_ACC_BASE IOMEM(0xF0002000) | 44 | #define MSM_ACC_BASE IOMEM(0xF0002000) |
47 | #define MSM_ACC_PHYS 0x02001000 | 45 | #define MSM_ACC_PHYS 0x02001000 |
@@ -58,51 +56,10 @@ | |||
58 | #define MSM_SHARED_RAM_BASE IOMEM(0xF0100000) | 56 | #define MSM_SHARED_RAM_BASE IOMEM(0xF0100000) |
59 | #define MSM_SHARED_RAM_SIZE SZ_1M | 57 | #define MSM_SHARED_RAM_SIZE SZ_1M |
60 | 58 | ||
61 | #define MSM_TMR_BASE IOMEM(0xF0200000) | 59 | #define MSM8X60_TMR_PHYS 0x02000000 |
62 | #define MSM_TMR_PHYS 0x02000000 | 60 | #define MSM8X60_TMR_SIZE SZ_4K |
63 | #define MSM_TMR_SIZE SZ_4K | ||
64 | 61 | ||
65 | #define MSM_TMR0_BASE IOMEM(0xF0201000) | 62 | #define MSM8X60_TMR0_PHYS 0x02040000 |
66 | #define MSM_TMR0_PHYS 0x02040000 | 63 | #define MSM8X60_TMR0_SIZE SZ_4K |
67 | #define MSM_TMR0_SIZE SZ_4K | ||
68 | |||
69 | #define MSM_GPT_BASE (MSM_TMR_BASE + 0x4) | ||
70 | #define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) | ||
71 | |||
72 | #define MSM_IOMMU_JPEGD_PHYS 0x07300000 | ||
73 | #define MSM_IOMMU_JPEGD_SIZE SZ_1M | ||
74 | |||
75 | #define MSM_IOMMU_VPE_PHYS 0x07400000 | ||
76 | #define MSM_IOMMU_VPE_SIZE SZ_1M | ||
77 | |||
78 | #define MSM_IOMMU_MDP0_PHYS 0x07500000 | ||
79 | #define MSM_IOMMU_MDP0_SIZE SZ_1M | ||
80 | |||
81 | #define MSM_IOMMU_MDP1_PHYS 0x07600000 | ||
82 | #define MSM_IOMMU_MDP1_SIZE SZ_1M | ||
83 | |||
84 | #define MSM_IOMMU_ROT_PHYS 0x07700000 | ||
85 | #define MSM_IOMMU_ROT_SIZE SZ_1M | ||
86 | |||
87 | #define MSM_IOMMU_IJPEG_PHYS 0x07800000 | ||
88 | #define MSM_IOMMU_IJPEG_SIZE SZ_1M | ||
89 | |||
90 | #define MSM_IOMMU_VFE_PHYS 0x07900000 | ||
91 | #define MSM_IOMMU_VFE_SIZE SZ_1M | ||
92 | |||
93 | #define MSM_IOMMU_VCODEC_A_PHYS 0x07A00000 | ||
94 | #define MSM_IOMMU_VCODEC_A_SIZE SZ_1M | ||
95 | |||
96 | #define MSM_IOMMU_VCODEC_B_PHYS 0x07B00000 | ||
97 | #define MSM_IOMMU_VCODEC_B_SIZE SZ_1M | ||
98 | |||
99 | #define MSM_IOMMU_GFX3D_PHYS 0x07C00000 | ||
100 | #define MSM_IOMMU_GFX3D_SIZE SZ_1M | ||
101 | |||
102 | #define MSM_IOMMU_GFX2D0_PHYS 0x07D00000 | ||
103 | #define MSM_IOMMU_GFX2D0_SIZE SZ_1M | ||
104 | |||
105 | #define MSM_IOMMU_GFX2D1_PHYS 0x07E00000 | ||
106 | #define MSM_IOMMU_GFX2D1_SIZE SZ_1M | ||
107 | 64 | ||
108 | #endif | 65 | #endif |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index 8e24dd812139..c98c7591f3b8 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h | |||
@@ -1,6 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2007 Google, Inc. | 2 | * Copyright (C) 2007 Google, Inc. |
3 | * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. | 3 | * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. |
4 | * Author: Brian Swetland <swetland@google.com> | 4 | * Author: Brian Swetland <swetland@google.com> |
5 | * | 5 | * |
6 | * This software is licensed under the terms of the GNU General Public | 6 | * This software is licensed under the terms of the GNU General Public |
@@ -53,6 +53,13 @@ | |||
53 | #include "msm_iomap-7x00.h" | 53 | #include "msm_iomap-7x00.h" |
54 | #endif | 54 | #endif |
55 | 55 | ||
56 | #include "msm_iomap-8960.h" | ||
56 | 57 | ||
58 | /* Virtual addressses shared across all MSM targets. */ | ||
59 | #define MSM_CSR_BASE IOMEM(0xE0001000) | ||
60 | #define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) | ||
61 | #define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) | ||
62 | #define MSM_TMR_BASE IOMEM(0xF0200000) | ||
63 | #define MSM_TMR0_BASE IOMEM(0xF0201000) | ||
57 | 64 | ||
58 | #endif | 65 | #endif |
diff --git a/arch/arm/mach-msm/include/mach/sirc.h b/arch/arm/mach-msm/include/mach/sirc.h index 7281337ee28d..ef55868a5b8a 100644 --- a/arch/arm/mach-msm/include/mach/sirc.h +++ b/arch/arm/mach-msm/include/mach/sirc.h | |||
@@ -1,30 +1,13 @@ | |||
1 | /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. | 1 | /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. |
2 | * | 2 | * |
3 | * Redistribution and use in source and binary forms, with or without | 3 | * This program is free software; you can redistribute it and/or modify |
4 | * modification, are permitted provided that the following conditions are | 4 | * it under the terms of the GNU General Public License version 2 and |
5 | * met: | 5 | * only version 2 as published by the Free Software Foundation. |
6 | * * Redistributions of source code must retain the above copyright | ||
7 | * notice, this list of conditions and the following disclaimer. | ||
8 | * * Redistributions in binary form must reproduce the above | ||
9 | * copyright notice, this list of conditions and the following | ||
10 | * disclaimer in the documentation and/or other materials provided | ||
11 | * with the distribution. | ||
12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its | ||
13 | * contributors may be used to endorse or promote products derived | ||
14 | * from this software without specific prior written permission. | ||
15 | * | ||
16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | ||
17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT | ||
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS | ||
20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
27 | * | 6 | * |
7 | * This program is distributed in the hope that it will be useful, | ||
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | * GNU General Public License for more details. | ||
28 | */ | 11 | */ |
29 | 12 | ||
30 | #ifndef __ASM_ARCH_MSM_SIRC_H | 13 | #ifndef __ASM_ARCH_MSM_SIRC_H |
diff --git a/arch/arm/mach-msm/include/mach/smp.h b/arch/arm/mach-msm/include/mach/smp.h index a95f7b9efe31..3c01000ecc80 100644 --- a/arch/arm/mach-msm/include/mach/smp.h +++ b/arch/arm/mach-msm/include/mach/smp.h | |||
@@ -1,29 +1,13 @@ | |||
1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | 1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. |
2 | * | 2 | * |
3 | * Redistribution and use in source and binary forms, with or without | 3 | * This program is free software; you can redistribute it and/or modify |
4 | * modification, are permitted provided that the following conditions are met: | 4 | * it under the terms of the GNU General Public License version 2 and |
5 | * * Redistributions of source code must retain the above copyright | 5 | * only version 2 as published by the Free Software Foundation. |
6 | * notice, this list of conditions and the following disclaimer. | ||
7 | * * Redistributions in binary form must reproduce the above copyright | ||
8 | * notice, this list of conditions and the following disclaimer in the | ||
9 | * documentation and/or other materials provided with the distribution. | ||
10 | * * Neither the name of Code Aurora nor | ||
11 | * the names of its contributors may be used to endorse or promote | ||
12 | * products derived from this software without specific prior written | ||
13 | * permission. | ||
14 | * | ||
15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||
16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||
17 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | ||
18 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | ||
19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | ||
20 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | ||
21 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; | ||
22 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
23 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR | ||
24 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF | ||
25 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
26 | * | 6 | * |
7 | * This program is distributed in the hope that it will be useful, | ||
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | * GNU General Public License for more details. | ||
27 | */ | 11 | */ |
28 | 12 | ||
29 | #ifndef __ASM_ARCH_MSM_SMP_H | 13 | #ifndef __ASM_ARCH_MSM_SMP_H |
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index 1260007a9dd1..cec6ed1c91d3 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * MSM7K, QSD io support | 3 | * MSM7K, QSD io support |
4 | * | 4 | * |
5 | * Copyright (C) 2007 Google, Inc. | 5 | * Copyright (C) 2007 Google, Inc. |
6 | * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. | 6 | * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. |
7 | * Author: Brian Swetland <swetland@google.com> | 7 | * Author: Brian Swetland <swetland@google.com> |
8 | * | 8 | * |
9 | * This software is licensed under the terms of the GNU General Public | 9 | * This software is licensed under the terms of the GNU General Public |
@@ -28,19 +28,20 @@ | |||
28 | 28 | ||
29 | #include <mach/board.h> | 29 | #include <mach/board.h> |
30 | 30 | ||
31 | #define MSM_DEVICE(name) { \ | 31 | #define MSM_CHIP_DEVICE(name, chip) { \ |
32 | .virtual = (unsigned long) MSM_##name##_BASE, \ | 32 | .virtual = (unsigned long) MSM_##name##_BASE, \ |
33 | .pfn = __phys_to_pfn(MSM_##name##_PHYS), \ | 33 | .pfn = __phys_to_pfn(chip##_##name##_PHYS), \ |
34 | .length = MSM_##name##_SIZE, \ | 34 | .length = chip##_##name##_SIZE, \ |
35 | .type = MT_DEVICE_NONSHARED, \ | 35 | .type = MT_DEVICE_NONSHARED, \ |
36 | } | 36 | } |
37 | 37 | ||
38 | #define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM) | ||
39 | |||
38 | #if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \ | 40 | #if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \ |
39 | || defined(CONFIG_ARCH_MSM7X25) | 41 | || defined(CONFIG_ARCH_MSM7X25) |
40 | static struct map_desc msm_io_desc[] __initdata = { | 42 | static struct map_desc msm_io_desc[] __initdata = { |
41 | MSM_DEVICE(VIC), | 43 | MSM_DEVICE(VIC), |
42 | MSM_DEVICE(CSR), | 44 | MSM_CHIP_DEVICE(CSR, MSM7X00), |
43 | MSM_DEVICE(GPT), | ||
44 | MSM_DEVICE(DMOV), | 45 | MSM_DEVICE(DMOV), |
45 | MSM_DEVICE(GPIO1), | 46 | MSM_DEVICE(GPIO1), |
46 | MSM_DEVICE(GPIO2), | 47 | MSM_DEVICE(GPIO2), |
@@ -73,8 +74,7 @@ void __init msm_map_common_io(void) | |||
73 | #ifdef CONFIG_ARCH_QSD8X50 | 74 | #ifdef CONFIG_ARCH_QSD8X50 |
74 | static struct map_desc qsd8x50_io_desc[] __initdata = { | 75 | static struct map_desc qsd8x50_io_desc[] __initdata = { |
75 | MSM_DEVICE(VIC), | 76 | MSM_DEVICE(VIC), |
76 | MSM_DEVICE(CSR), | 77 | MSM_CHIP_DEVICE(CSR, QSD8X50), |
77 | MSM_DEVICE(TMR), | ||
78 | MSM_DEVICE(DMOV), | 78 | MSM_DEVICE(DMOV), |
79 | MSM_DEVICE(GPIO1), | 79 | MSM_DEVICE(GPIO1), |
80 | MSM_DEVICE(GPIO2), | 80 | MSM_DEVICE(GPIO2), |
@@ -102,10 +102,10 @@ void __init msm_map_qsd8x50_io(void) | |||
102 | 102 | ||
103 | #ifdef CONFIG_ARCH_MSM8X60 | 103 | #ifdef CONFIG_ARCH_MSM8X60 |
104 | static struct map_desc msm8x60_io_desc[] __initdata = { | 104 | static struct map_desc msm8x60_io_desc[] __initdata = { |
105 | MSM_DEVICE(QGIC_DIST), | 105 | MSM_CHIP_DEVICE(QGIC_DIST, MSM8X60), |
106 | MSM_DEVICE(QGIC_CPU), | 106 | MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60), |
107 | MSM_DEVICE(TMR), | 107 | MSM_CHIP_DEVICE(TMR, MSM8X60), |
108 | MSM_DEVICE(TMR0), | 108 | MSM_CHIP_DEVICE(TMR0, MSM8X60), |
109 | MSM_DEVICE(ACC), | 109 | MSM_DEVICE(ACC), |
110 | MSM_DEVICE(GCC), | 110 | MSM_DEVICE(GCC), |
111 | }; | 111 | }; |
@@ -116,11 +116,24 @@ void __init msm_map_msm8x60_io(void) | |||
116 | } | 116 | } |
117 | #endif /* CONFIG_ARCH_MSM8X60 */ | 117 | #endif /* CONFIG_ARCH_MSM8X60 */ |
118 | 118 | ||
119 | #ifdef CONFIG_ARCH_MSM8960 | ||
120 | static struct map_desc msm8960_io_desc[] __initdata = { | ||
121 | MSM_CHIP_DEVICE(QGIC_DIST, MSM8960), | ||
122 | MSM_CHIP_DEVICE(QGIC_CPU, MSM8960), | ||
123 | MSM_CHIP_DEVICE(TMR, MSM8960), | ||
124 | MSM_CHIP_DEVICE(TMR0, MSM8960), | ||
125 | }; | ||
126 | |||
127 | void __init msm_map_msm8960_io(void) | ||
128 | { | ||
129 | iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc)); | ||
130 | } | ||
131 | #endif /* CONFIG_ARCH_MSM8960 */ | ||
132 | |||
119 | #ifdef CONFIG_ARCH_MSM7X30 | 133 | #ifdef CONFIG_ARCH_MSM7X30 |
120 | static struct map_desc msm7x30_io_desc[] __initdata = { | 134 | static struct map_desc msm7x30_io_desc[] __initdata = { |
121 | MSM_DEVICE(VIC), | 135 | MSM_DEVICE(VIC), |
122 | MSM_DEVICE(CSR), | 136 | MSM_CHIP_DEVICE(CSR, MSM7X30), |
123 | MSM_DEVICE(TMR), | ||
124 | MSM_DEVICE(DMOV), | 137 | MSM_DEVICE(DMOV), |
125 | MSM_DEVICE(GPIO1), | 138 | MSM_DEVICE(GPIO1), |
126 | MSM_DEVICE(GPIO2), | 139 | MSM_DEVICE(GPIO2), |
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index e2d58e4cb0d7..1a584e077c61 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c | |||
@@ -1,4 +1,4 @@ | |||
1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | 1 | /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. |
2 | * | 2 | * |
3 | * This program is free software; you can redistribute it and/or modify | 3 | * This program is free software; you can redistribute it and/or modify |
4 | * it under the terms of the GNU General Public License version 2 and | 4 | * it under the terms of the GNU General Public License version 2 and |
@@ -26,6 +26,7 @@ | |||
26 | #include <linux/spinlock.h> | 26 | #include <linux/spinlock.h> |
27 | #include <linux/slab.h> | 27 | #include <linux/slab.h> |
28 | #include <linux/iommu.h> | 28 | #include <linux/iommu.h> |
29 | #include <linux/clk.h> | ||
29 | 30 | ||
30 | #include <asm/cacheflush.h> | 31 | #include <asm/cacheflush.h> |
31 | #include <asm/sizes.h> | 32 | #include <asm/sizes.h> |
@@ -50,6 +51,30 @@ struct msm_priv { | |||
50 | struct list_head list_attached; | 51 | struct list_head list_attached; |
51 | }; | 52 | }; |
52 | 53 | ||
54 | static int __enable_clocks(struct msm_iommu_drvdata *drvdata) | ||
55 | { | ||
56 | int ret; | ||
57 | |||
58 | ret = clk_enable(drvdata->pclk); | ||
59 | if (ret) | ||
60 | goto fail; | ||
61 | |||
62 | if (drvdata->clk) { | ||
63 | ret = clk_enable(drvdata->clk); | ||
64 | if (ret) | ||
65 | clk_disable(drvdata->pclk); | ||
66 | } | ||
67 | fail: | ||
68 | return ret; | ||
69 | } | ||
70 | |||
71 | static void __disable_clocks(struct msm_iommu_drvdata *drvdata) | ||
72 | { | ||
73 | if (drvdata->clk) | ||
74 | clk_disable(drvdata->clk); | ||
75 | clk_disable(drvdata->pclk); | ||
76 | } | ||
77 | |||
53 | static int __flush_iotlb(struct iommu_domain *domain) | 78 | static int __flush_iotlb(struct iommu_domain *domain) |
54 | { | 79 | { |
55 | struct msm_priv *priv = domain->priv; | 80 | struct msm_priv *priv = domain->priv; |
@@ -77,9 +102,16 @@ static int __flush_iotlb(struct iommu_domain *domain) | |||
77 | BUG(); | 102 | BUG(); |
78 | 103 | ||
79 | iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent); | 104 | iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent); |
105 | BUG_ON(!iommu_drvdata); | ||
106 | |||
107 | ret = __enable_clocks(iommu_drvdata); | ||
108 | if (ret) | ||
109 | goto fail; | ||
110 | |||
80 | SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0); | 111 | SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0); |
112 | __disable_clocks(iommu_drvdata); | ||
81 | } | 113 | } |
82 | 114 | fail: | |
83 | return ret; | 115 | return ret; |
84 | } | 116 | } |
85 | 117 | ||
@@ -105,7 +137,6 @@ static void __reset_context(void __iomem *base, int ctx) | |||
105 | SET_TLBLKCR(base, ctx, 0); | 137 | SET_TLBLKCR(base, ctx, 0); |
106 | SET_PRRR(base, ctx, 0); | 138 | SET_PRRR(base, ctx, 0); |
107 | SET_NMRR(base, ctx, 0); | 139 | SET_NMRR(base, ctx, 0); |
108 | SET_CONTEXTIDR(base, ctx, 0); | ||
109 | } | 140 | } |
110 | 141 | ||
111 | static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable) | 142 | static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable) |
@@ -265,9 +296,14 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |||
265 | goto fail; | 296 | goto fail; |
266 | } | 297 | } |
267 | 298 | ||
299 | ret = __enable_clocks(iommu_drvdata); | ||
300 | if (ret) | ||
301 | goto fail; | ||
302 | |||
268 | __program_context(iommu_drvdata->base, ctx_dev->num, | 303 | __program_context(iommu_drvdata->base, ctx_dev->num, |
269 | __pa(priv->pgtable)); | 304 | __pa(priv->pgtable)); |
270 | 305 | ||
306 | __disable_clocks(iommu_drvdata); | ||
271 | list_add(&(ctx_drvdata->attached_elm), &priv->list_attached); | 307 | list_add(&(ctx_drvdata->attached_elm), &priv->list_attached); |
272 | ret = __flush_iotlb(domain); | 308 | ret = __flush_iotlb(domain); |
273 | 309 | ||
@@ -303,7 +339,12 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain, | |||
303 | if (ret) | 339 | if (ret) |
304 | goto fail; | 340 | goto fail; |
305 | 341 | ||
342 | ret = __enable_clocks(iommu_drvdata); | ||
343 | if (ret) | ||
344 | goto fail; | ||
345 | |||
306 | __reset_context(iommu_drvdata->base, ctx_dev->num); | 346 | __reset_context(iommu_drvdata->base, ctx_dev->num); |
347 | __disable_clocks(iommu_drvdata); | ||
307 | list_del_init(&ctx_drvdata->attached_elm); | 348 | list_del_init(&ctx_drvdata->attached_elm); |
308 | 349 | ||
309 | fail: | 350 | fail: |
@@ -376,11 +417,11 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, | |||
376 | for (i = 0; i < 16; i++) | 417 | for (i = 0; i < 16; i++) |
377 | *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION | | 418 | *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION | |
378 | FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT | | 419 | FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT | |
379 | FL_SHARED | pgprot; | 420 | FL_SHARED | FL_NG | pgprot; |
380 | } | 421 | } |
381 | 422 | ||
382 | if (len == SZ_1M) | 423 | if (len == SZ_1M) |
383 | *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE | | 424 | *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE | FL_NG | |
384 | FL_TYPE_SECT | FL_SHARED | pgprot; | 425 | FL_TYPE_SECT | FL_SHARED | pgprot; |
385 | 426 | ||
386 | /* Need a 2nd level table */ | 427 | /* Need a 2nd level table */ |
@@ -405,7 +446,7 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, | |||
405 | 446 | ||
406 | 447 | ||
407 | if (len == SZ_4K) | 448 | if (len == SZ_4K) |
408 | *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 | | 449 | *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 | SL_NG | |
409 | SL_SHARED | SL_TYPE_SMALL | pgprot; | 450 | SL_SHARED | SL_TYPE_SMALL | pgprot; |
410 | 451 | ||
411 | if (len == SZ_64K) { | 452 | if (len == SZ_64K) { |
@@ -413,7 +454,7 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, | |||
413 | 454 | ||
414 | for (i = 0; i < 16; i++) | 455 | for (i = 0; i < 16; i++) |
415 | *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 | | 456 | *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 | |
416 | SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot; | 457 | SL_NG | SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot; |
417 | } | 458 | } |
418 | 459 | ||
419 | ret = __flush_iotlb(domain); | 460 | ret = __flush_iotlb(domain); |
@@ -532,9 +573,13 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, | |||
532 | base = iommu_drvdata->base; | 573 | base = iommu_drvdata->base; |
533 | ctx = ctx_drvdata->num; | 574 | ctx = ctx_drvdata->num; |
534 | 575 | ||
576 | ret = __enable_clocks(iommu_drvdata); | ||
577 | if (ret) | ||
578 | goto fail; | ||
579 | |||
535 | /* Invalidate context TLB */ | 580 | /* Invalidate context TLB */ |
536 | SET_CTX_TLBIALL(base, ctx, 0); | 581 | SET_CTX_TLBIALL(base, ctx, 0); |
537 | SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT); | 582 | SET_V2PPR(base, ctx, va & V2Pxx_VA); |
538 | 583 | ||
539 | par = GET_PAR(base, ctx); | 584 | par = GET_PAR(base, ctx); |
540 | 585 | ||
@@ -547,6 +592,7 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, | |||
547 | if (GET_FAULT(base, ctx)) | 592 | if (GET_FAULT(base, ctx)) |
548 | ret = 0; | 593 | ret = 0; |
549 | 594 | ||
595 | __disable_clocks(iommu_drvdata); | ||
550 | fail: | 596 | fail: |
551 | spin_unlock_irqrestore(&msm_iommu_lock, flags); | 597 | spin_unlock_irqrestore(&msm_iommu_lock, flags); |
552 | return ret; | 598 | return ret; |
@@ -590,7 +636,7 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) | |||
590 | struct msm_iommu_drvdata *drvdata = dev_id; | 636 | struct msm_iommu_drvdata *drvdata = dev_id; |
591 | void __iomem *base; | 637 | void __iomem *base; |
592 | unsigned int fsr; | 638 | unsigned int fsr; |
593 | int ncb, i; | 639 | int i, ret; |
594 | 640 | ||
595 | spin_lock(&msm_iommu_lock); | 641 | spin_lock(&msm_iommu_lock); |
596 | 642 | ||
@@ -604,8 +650,11 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) | |||
604 | pr_err("Unexpected IOMMU page fault!\n"); | 650 | pr_err("Unexpected IOMMU page fault!\n"); |
605 | pr_err("base = %08x\n", (unsigned int) base); | 651 | pr_err("base = %08x\n", (unsigned int) base); |
606 | 652 | ||
607 | ncb = GET_NCB(base)+1; | 653 | ret = __enable_clocks(drvdata); |
608 | for (i = 0; i < ncb; i++) { | 654 | if (ret) |
655 | goto fail; | ||
656 | |||
657 | for (i = 0; i < drvdata->ncb; i++) { | ||
609 | fsr = GET_FSR(base, i); | 658 | fsr = GET_FSR(base, i); |
610 | if (fsr) { | 659 | if (fsr) { |
611 | pr_err("Fault occurred in context %d.\n", i); | 660 | pr_err("Fault occurred in context %d.\n", i); |
@@ -614,6 +663,7 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) | |||
614 | SET_FSR(base, i, 0x4000000F); | 663 | SET_FSR(base, i, 0x4000000F); |
615 | } | 664 | } |
616 | } | 665 | } |
666 | __disable_clocks(drvdata); | ||
617 | fail: | 667 | fail: |
618 | spin_unlock(&msm_iommu_lock); | 668 | spin_unlock(&msm_iommu_lock); |
619 | return 0; | 669 | return 0; |
diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c index b83c73b41fd1..8e8fb079852d 100644 --- a/arch/arm/mach-msm/iommu_dev.c +++ b/arch/arm/mach-msm/iommu_dev.c | |||
@@ -1,4 +1,4 @@ | |||
1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | 1 | /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. |
2 | * | 2 | * |
3 | * This program is free software; you can redistribute it and/or modify | 3 | * This program is free software; you can redistribute it and/or modify |
4 | * it under the terms of the GNU General Public License version 2 and | 4 | * it under the terms of the GNU General Public License version 2 and |
@@ -29,6 +29,7 @@ | |||
29 | 29 | ||
30 | #include <mach/iommu_hw-8xxx.h> | 30 | #include <mach/iommu_hw-8xxx.h> |
31 | #include <mach/iommu.h> | 31 | #include <mach/iommu.h> |
32 | #include <mach/clk.h> | ||
32 | 33 | ||
33 | struct iommu_ctx_iter_data { | 34 | struct iommu_ctx_iter_data { |
34 | /* input */ | 35 | /* input */ |
@@ -84,9 +85,9 @@ fail: | |||
84 | } | 85 | } |
85 | EXPORT_SYMBOL(msm_iommu_get_ctx); | 86 | EXPORT_SYMBOL(msm_iommu_get_ctx); |
86 | 87 | ||
87 | static void msm_iommu_reset(void __iomem *base) | 88 | static void msm_iommu_reset(void __iomem *base, int ncb) |
88 | { | 89 | { |
89 | int ctx, ncb; | 90 | int ctx; |
90 | 91 | ||
91 | SET_RPUE(base, 0); | 92 | SET_RPUE(base, 0); |
92 | SET_RPUEIE(base, 0); | 93 | SET_RPUEIE(base, 0); |
@@ -99,7 +100,6 @@ static void msm_iommu_reset(void __iomem *base) | |||
99 | SET_GLOBAL_TLBIALL(base, 0); | 100 | SET_GLOBAL_TLBIALL(base, 0); |
100 | SET_RPU_ACR(base, 0); | 101 | SET_RPU_ACR(base, 0); |
101 | SET_TLBLKCRWE(base, 1); | 102 | SET_TLBLKCRWE(base, 1); |
102 | ncb = GET_NCB(base)+1; | ||
103 | 103 | ||
104 | for (ctx = 0; ctx < ncb; ctx++) { | 104 | for (ctx = 0; ctx < ncb; ctx++) { |
105 | SET_BPRCOSH(base, ctx, 0); | 105 | SET_BPRCOSH(base, ctx, 0); |
@@ -130,117 +130,140 @@ static int msm_iommu_probe(struct platform_device *pdev) | |||
130 | { | 130 | { |
131 | struct resource *r, *r2; | 131 | struct resource *r, *r2; |
132 | struct clk *iommu_clk; | 132 | struct clk *iommu_clk; |
133 | struct clk *iommu_pclk; | ||
133 | struct msm_iommu_drvdata *drvdata; | 134 | struct msm_iommu_drvdata *drvdata; |
134 | struct msm_iommu_dev *iommu_dev = pdev->dev.platform_data; | 135 | struct msm_iommu_dev *iommu_dev = pdev->dev.platform_data; |
135 | void __iomem *regs_base; | 136 | void __iomem *regs_base; |
136 | resource_size_t len; | 137 | resource_size_t len; |
137 | int ret = 0, ncb, nm2v, irq; | 138 | int ret, irq, par; |
138 | 139 | ||
139 | if (pdev->id != -1) { | 140 | if (pdev->id == -1) { |
140 | drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL); | 141 | msm_iommu_root_dev = pdev; |
142 | return 0; | ||
143 | } | ||
141 | 144 | ||
142 | if (!drvdata) { | 145 | drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL); |
143 | ret = -ENOMEM; | ||
144 | goto fail; | ||
145 | } | ||
146 | 146 | ||
147 | if (!iommu_dev) { | 147 | if (!drvdata) { |
148 | ret = -ENODEV; | 148 | ret = -ENOMEM; |
149 | goto fail; | 149 | goto fail; |
150 | } | 150 | } |
151 | 151 | ||
152 | if (iommu_dev->clk_rate != 0) { | 152 | if (!iommu_dev) { |
153 | iommu_clk = clk_get(&pdev->dev, "iommu_clk"); | 153 | ret = -ENODEV; |
154 | 154 | goto fail; | |
155 | if (IS_ERR(iommu_clk)) { | 155 | } |
156 | ret = -ENODEV; | 156 | |
157 | goto fail; | 157 | iommu_pclk = clk_get(NULL, "smmu_pclk"); |
158 | } | 158 | if (IS_ERR(iommu_pclk)) { |
159 | 159 | ret = -ENODEV; | |
160 | if (iommu_dev->clk_rate > 0) { | 160 | goto fail; |
161 | ret = clk_set_rate(iommu_clk, | 161 | } |
162 | iommu_dev->clk_rate); | 162 | |
163 | if (ret) { | 163 | ret = clk_enable(iommu_pclk); |
164 | clk_put(iommu_clk); | 164 | if (ret) |
165 | goto fail; | 165 | goto fail_enable; |
166 | } | 166 | |
167 | } | 167 | iommu_clk = clk_get(&pdev->dev, "iommu_clk"); |
168 | 168 | ||
169 | ret = clk_enable(iommu_clk); | 169 | if (!IS_ERR(iommu_clk)) { |
170 | if (ret) { | 170 | if (clk_get_rate(iommu_clk) == 0) |
171 | clk_put(iommu_clk); | 171 | clk_set_min_rate(iommu_clk, 1); |
172 | goto fail; | 172 | |
173 | } | 173 | ret = clk_enable(iommu_clk); |
174 | if (ret) { | ||
174 | clk_put(iommu_clk); | 175 | clk_put(iommu_clk); |
176 | goto fail_pclk; | ||
175 | } | 177 | } |
178 | } else | ||
179 | iommu_clk = NULL; | ||
176 | 180 | ||
177 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, | 181 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "physbase"); |
178 | "physbase"); | ||
179 | if (!r) { | ||
180 | ret = -ENODEV; | ||
181 | goto fail; | ||
182 | } | ||
183 | 182 | ||
184 | len = r->end - r->start + 1; | 183 | if (!r) { |
184 | ret = -ENODEV; | ||
185 | goto fail_clk; | ||
186 | } | ||
185 | 187 | ||
186 | r2 = request_mem_region(r->start, len, r->name); | 188 | len = resource_size(r); |
187 | if (!r2) { | ||
188 | pr_err("Could not request memory region: " | ||
189 | "start=%p, len=%d\n", (void *) r->start, len); | ||
190 | ret = -EBUSY; | ||
191 | goto fail; | ||
192 | } | ||
193 | 189 | ||
194 | regs_base = ioremap(r2->start, len); | 190 | r2 = request_mem_region(r->start, len, r->name); |
191 | if (!r2) { | ||
192 | pr_err("Could not request memory region: start=%p, len=%d\n", | ||
193 | (void *) r->start, len); | ||
194 | ret = -EBUSY; | ||
195 | goto fail_clk; | ||
196 | } | ||
195 | 197 | ||
196 | if (!regs_base) { | 198 | regs_base = ioremap(r2->start, len); |
197 | pr_err("Could not ioremap: start=%p, len=%d\n", | ||
198 | (void *) r2->start, len); | ||
199 | ret = -EBUSY; | ||
200 | goto fail_mem; | ||
201 | } | ||
202 | 199 | ||
203 | irq = platform_get_irq_byname(pdev, "secure_irq"); | 200 | if (!regs_base) { |
204 | if (irq < 0) { | 201 | pr_err("Could not ioremap: start=%p, len=%d\n", |
205 | ret = -ENODEV; | 202 | (void *) r2->start, len); |
206 | goto fail_io; | 203 | ret = -EBUSY; |
207 | } | 204 | goto fail_mem; |
205 | } | ||
208 | 206 | ||
209 | mb(); | 207 | irq = platform_get_irq_byname(pdev, "secure_irq"); |
208 | if (irq < 0) { | ||
209 | ret = -ENODEV; | ||
210 | goto fail_io; | ||
211 | } | ||
210 | 212 | ||
211 | if (GET_IDR(regs_base) == 0) { | 213 | msm_iommu_reset(regs_base, iommu_dev->ncb); |
212 | pr_err("Invalid IDR value detected\n"); | ||
213 | ret = -ENODEV; | ||
214 | goto fail_io; | ||
215 | } | ||
216 | 214 | ||
217 | ret = request_irq(irq, msm_iommu_fault_handler, 0, | 215 | SET_M(regs_base, 0, 1); |
218 | "msm_iommu_secure_irpt_handler", drvdata); | 216 | SET_PAR(regs_base, 0, 0); |
219 | if (ret) { | 217 | SET_V2PCFG(regs_base, 0, 1); |
220 | pr_err("Request IRQ %d failed with ret=%d\n", irq, ret); | 218 | SET_V2PPR(regs_base, 0, 0); |
221 | goto fail_io; | 219 | par = GET_PAR(regs_base, 0); |
222 | } | 220 | SET_V2PCFG(regs_base, 0, 0); |
221 | SET_M(regs_base, 0, 0); | ||
223 | 222 | ||
224 | msm_iommu_reset(regs_base); | 223 | if (!par) { |
225 | drvdata->base = regs_base; | 224 | pr_err("%s: Invalid PAR value detected\n", iommu_dev->name); |
226 | drvdata->irq = irq; | 225 | ret = -ENODEV; |
226 | goto fail_io; | ||
227 | } | ||
227 | 228 | ||
228 | nm2v = GET_NM2VCBMT((unsigned long) regs_base); | 229 | ret = request_irq(irq, msm_iommu_fault_handler, 0, |
229 | ncb = GET_NCB((unsigned long) regs_base); | 230 | "msm_iommu_secure_irpt_handler", drvdata); |
231 | if (ret) { | ||
232 | pr_err("Request IRQ %d failed with ret=%d\n", irq, ret); | ||
233 | goto fail_io; | ||
234 | } | ||
230 | 235 | ||
231 | pr_info("device %s mapped at %p, irq %d with %d ctx banks\n", | ||
232 | iommu_dev->name, regs_base, irq, ncb+1); | ||
233 | 236 | ||
234 | platform_set_drvdata(pdev, drvdata); | 237 | drvdata->pclk = iommu_pclk; |
235 | } else | 238 | drvdata->clk = iommu_clk; |
236 | msm_iommu_root_dev = pdev; | 239 | drvdata->base = regs_base; |
240 | drvdata->irq = irq; | ||
241 | drvdata->ncb = iommu_dev->ncb; | ||
237 | 242 | ||
238 | return 0; | 243 | pr_info("device %s mapped at %p, irq %d with %d ctx banks\n", |
244 | iommu_dev->name, regs_base, irq, iommu_dev->ncb); | ||
245 | |||
246 | platform_set_drvdata(pdev, drvdata); | ||
247 | |||
248 | if (iommu_clk) | ||
249 | clk_disable(iommu_clk); | ||
250 | |||
251 | clk_disable(iommu_pclk); | ||
239 | 252 | ||
253 | return 0; | ||
240 | fail_io: | 254 | fail_io: |
241 | iounmap(regs_base); | 255 | iounmap(regs_base); |
242 | fail_mem: | 256 | fail_mem: |
243 | release_mem_region(r->start, len); | 257 | release_mem_region(r->start, len); |
258 | fail_clk: | ||
259 | if (iommu_clk) { | ||
260 | clk_disable(iommu_clk); | ||
261 | clk_put(iommu_clk); | ||
262 | } | ||
263 | fail_pclk: | ||
264 | clk_disable(iommu_pclk); | ||
265 | fail_enable: | ||
266 | clk_put(iommu_pclk); | ||
244 | fail: | 267 | fail: |
245 | kfree(drvdata); | 268 | kfree(drvdata); |
246 | return ret; | 269 | return ret; |
@@ -252,7 +275,10 @@ static int msm_iommu_remove(struct platform_device *pdev) | |||
252 | 275 | ||
253 | drv = platform_get_drvdata(pdev); | 276 | drv = platform_get_drvdata(pdev); |
254 | if (drv) { | 277 | if (drv) { |
255 | memset(drv, 0, sizeof(struct msm_iommu_drvdata)); | 278 | if (drv->clk) |
279 | clk_put(drv->clk); | ||
280 | clk_put(drv->pclk); | ||
281 | memset(drv, 0, sizeof(*drv)); | ||
256 | kfree(drv); | 282 | kfree(drv); |
257 | platform_set_drvdata(pdev, NULL); | 283 | platform_set_drvdata(pdev, NULL); |
258 | } | 284 | } |
@@ -264,7 +290,7 @@ static int msm_iommu_ctx_probe(struct platform_device *pdev) | |||
264 | struct msm_iommu_ctx_dev *c = pdev->dev.platform_data; | 290 | struct msm_iommu_ctx_dev *c = pdev->dev.platform_data; |
265 | struct msm_iommu_drvdata *drvdata; | 291 | struct msm_iommu_drvdata *drvdata; |
266 | struct msm_iommu_ctx_drvdata *ctx_drvdata = NULL; | 292 | struct msm_iommu_ctx_drvdata *ctx_drvdata = NULL; |
267 | int i, ret = 0; | 293 | int i, ret; |
268 | if (!c || !pdev->dev.parent) { | 294 | if (!c || !pdev->dev.parent) { |
269 | ret = -EINVAL; | 295 | ret = -EINVAL; |
270 | goto fail; | 296 | goto fail; |
@@ -288,6 +314,18 @@ static int msm_iommu_ctx_probe(struct platform_device *pdev) | |||
288 | INIT_LIST_HEAD(&ctx_drvdata->attached_elm); | 314 | INIT_LIST_HEAD(&ctx_drvdata->attached_elm); |
289 | platform_set_drvdata(pdev, ctx_drvdata); | 315 | platform_set_drvdata(pdev, ctx_drvdata); |
290 | 316 | ||
317 | ret = clk_enable(drvdata->pclk); | ||
318 | if (ret) | ||
319 | goto fail; | ||
320 | |||
321 | if (drvdata->clk) { | ||
322 | ret = clk_enable(drvdata->clk); | ||
323 | if (ret) { | ||
324 | clk_disable(drvdata->pclk); | ||
325 | goto fail; | ||
326 | } | ||
327 | } | ||
328 | |||
291 | /* Program the M2V tables for this context */ | 329 | /* Program the M2V tables for this context */ |
292 | for (i = 0; i < MAX_NUM_MIDS; i++) { | 330 | for (i = 0; i < MAX_NUM_MIDS; i++) { |
293 | int mid = c->mids[i]; | 331 | int mid = c->mids[i]; |
@@ -297,21 +335,27 @@ static int msm_iommu_ctx_probe(struct platform_device *pdev) | |||
297 | SET_M2VCBR_N(drvdata->base, mid, 0); | 335 | SET_M2VCBR_N(drvdata->base, mid, 0); |
298 | SET_CBACR_N(drvdata->base, c->num, 0); | 336 | SET_CBACR_N(drvdata->base, c->num, 0); |
299 | 337 | ||
300 | /* Set VMID = MID */ | 338 | /* Set VMID = 0 */ |
301 | SET_VMID(drvdata->base, mid, mid); | 339 | SET_VMID(drvdata->base, mid, 0); |
302 | 340 | ||
303 | /* Set the context number for that MID to this context */ | 341 | /* Set the context number for that MID to this context */ |
304 | SET_CBNDX(drvdata->base, mid, c->num); | 342 | SET_CBNDX(drvdata->base, mid, c->num); |
305 | 343 | ||
306 | /* Set MID associated with this context bank */ | 344 | /* Set MID associated with this context bank to 0*/ |
307 | SET_CBVMID(drvdata->base, c->num, mid); | 345 | SET_CBVMID(drvdata->base, c->num, 0); |
346 | |||
347 | /* Set the ASID for TLB tagging for this context */ | ||
348 | SET_CONTEXTIDR_ASID(drvdata->base, c->num, c->num); | ||
308 | 349 | ||
309 | /* Set security bit override to be Non-secure */ | 350 | /* Set security bit override to be Non-secure */ |
310 | SET_NSCFG(drvdata->base, mid, 3); | 351 | SET_NSCFG(drvdata->base, mid, 3); |
311 | } | 352 | } |
312 | 353 | ||
313 | pr_info("context device %s with bank index %d\n", c->name, c->num); | 354 | if (drvdata->clk) |
355 | clk_disable(drvdata->clk); | ||
356 | clk_disable(drvdata->pclk); | ||
314 | 357 | ||
358 | dev_info(&pdev->dev, "context %s using bank %d\n", c->name, c->num); | ||
315 | return 0; | 359 | return 0; |
316 | fail: | 360 | fail: |
317 | kfree(ctx_drvdata); | 361 | kfree(ctx_drvdata); |
diff --git a/arch/arm/mach-msm/scm-boot.h b/arch/arm/mach-msm/scm-boot.h index 68f9b6153d74..7be32ff5d687 100644 --- a/arch/arm/mach-msm/scm-boot.h +++ b/arch/arm/mach-msm/scm-boot.h | |||
@@ -1,29 +1,13 @@ | |||
1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | 1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. |
2 | * | 2 | * |
3 | * Redistribution and use in source and binary forms, with or without | 3 | * This program is free software; you can redistribute it and/or modify |
4 | * modification, are permitted provided that the following conditions are | 4 | * it under the terms of the GNU General Public License version 2 and |
5 | * met: | 5 | * only version 2 as published by the Free Software Foundation. |
6 | * * Redistributions of source code must retain the above copyright | ||
7 | * notice, this list of conditions and the following disclaimer. | ||
8 | * * Redistributions in binary form must reproduce the above | ||
9 | * copyright notice, this list of conditions and the following | ||
10 | * disclaimer in the documentation and/or other materials provided | ||
11 | * with the distribution. | ||
12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its | ||
13 | * contributors may be used to endorse or promote products derived | ||
14 | * from this software without specific prior written permission. | ||
15 | * | 6 | * |
16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | 7 | * This program is distributed in the hope that it will be useful, |
17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT | 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS | 10 | * GNU General Public License for more details. |
20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
27 | */ | 11 | */ |
28 | #ifndef __MACH_SCM_BOOT_H | 12 | #ifndef __MACH_SCM_BOOT_H |
29 | #define __MACH_SCM_BOOT_H | 13 | #define __MACH_SCM_BOOT_H |
diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c index f4b9bc90d6a7..cfa808dd4897 100644 --- a/arch/arm/mach-msm/scm.c +++ b/arch/arm/mach-msm/scm.c | |||
@@ -174,15 +174,18 @@ static u32 smc(u32 cmd_addr) | |||
174 | register u32 r0 asm("r0") = 1; | 174 | register u32 r0 asm("r0") = 1; |
175 | register u32 r1 asm("r1") = (u32)&context_id; | 175 | register u32 r1 asm("r1") = (u32)&context_id; |
176 | register u32 r2 asm("r2") = cmd_addr; | 176 | register u32 r2 asm("r2") = cmd_addr; |
177 | asm( | 177 | do { |
178 | __asmeq("%0", "r0") | 178 | asm volatile( |
179 | __asmeq("%1", "r0") | 179 | __asmeq("%0", "r0") |
180 | __asmeq("%2", "r1") | 180 | __asmeq("%1", "r0") |
181 | __asmeq("%3", "r2") | 181 | __asmeq("%2", "r1") |
182 | "smc #0 @ switch to secure world\n" | 182 | __asmeq("%3", "r2") |
183 | : "=r" (r0) | 183 | "smc #0 @ switch to secure world\n" |
184 | : "r" (r0), "r" (r1), "r" (r2) | 184 | : "=r" (r0) |
185 | : "r3"); | 185 | : "r" (r0), "r" (r1), "r" (r2) |
186 | : "r3"); | ||
187 | } while (r0 == SCM_INTERRUPTED); | ||
188 | |||
186 | return r0; | 189 | return r0; |
187 | } | 190 | } |
188 | 191 | ||
@@ -197,13 +200,9 @@ static int __scm_call(const struct scm_command *cmd) | |||
197 | * side in the buffer. | 200 | * side in the buffer. |
198 | */ | 201 | */ |
199 | flush_cache_all(); | 202 | flush_cache_all(); |
200 | do { | 203 | ret = smc(cmd_addr); |
201 | ret = smc(cmd_addr); | 204 | if (ret < 0) |
202 | if (ret < 0) { | 205 | ret = scm_remap_error(ret); |
203 | ret = scm_remap_error(ret); | ||
204 | break; | ||
205 | } | ||
206 | } while (ret == SCM_INTERRUPTED); | ||
207 | 206 | ||
208 | return ret; | 207 | return ret; |
209 | } | 208 | } |
@@ -264,21 +263,28 @@ u32 scm_get_version(void) | |||
264 | { | 263 | { |
265 | int context_id; | 264 | int context_id; |
266 | static u32 version = -1; | 265 | static u32 version = -1; |
267 | register u32 r0 asm("r0") = 0x1 << 8; | 266 | register u32 r0 asm("r0"); |
268 | register u32 r1 asm("r1") = (u32)&context_id; | 267 | register u32 r1 asm("r1"); |
269 | 268 | ||
270 | if (version != -1) | 269 | if (version != -1) |
271 | return version; | 270 | return version; |
272 | 271 | ||
273 | mutex_lock(&scm_lock); | 272 | mutex_lock(&scm_lock); |
274 | asm( | 273 | |
275 | __asmeq("%0", "r1") | 274 | r0 = 0x1 << 8; |
276 | __asmeq("%1", "r0") | 275 | r1 = (u32)&context_id; |
277 | __asmeq("%2", "r1") | 276 | do { |
278 | "smc #0 @ switch to secure world\n" | 277 | asm volatile( |
279 | : "=r" (r1) | 278 | __asmeq("%0", "r0") |
280 | : "r" (r0), "r" (r1) | 279 | __asmeq("%1", "r1") |
281 | : "r2", "r3"); | 280 | __asmeq("%2", "r0") |
281 | __asmeq("%3", "r1") | ||
282 | "smc #0 @ switch to secure world\n" | ||
283 | : "=r" (r0), "=r" (r1) | ||
284 | : "r" (r0), "r" (r1) | ||
285 | : "r2", "r3"); | ||
286 | } while (r0 == SCM_INTERRUPTED); | ||
287 | |||
282 | version = r1; | 288 | version = r1; |
283 | mutex_unlock(&scm_lock); | 289 | mutex_unlock(&scm_lock); |
284 | 290 | ||
diff --git a/arch/arm/mach-msm/scm.h b/arch/arm/mach-msm/scm.h index 261786be11c5..00b31ea58f29 100644 --- a/arch/arm/mach-msm/scm.h +++ b/arch/arm/mach-msm/scm.h | |||
@@ -1,29 +1,13 @@ | |||
1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | 1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. |
2 | * | 2 | * |
3 | * Redistribution and use in source and binary forms, with or without | 3 | * This program is free software; you can redistribute it and/or modify |
4 | * modification, are permitted provided that the following conditions are | 4 | * it under the terms of the GNU General Public License version 2 and |
5 | * met: | 5 | * only version 2 as published by the Free Software Foundation. |
6 | * * Redistributions of source code must retain the above copyright | ||
7 | * notice, this list of conditions and the following disclaimer. | ||
8 | * * Redistributions in binary form must reproduce the above | ||
9 | * copyright notice, this list of conditions and the following | ||
10 | * disclaimer in the documentation and/or other materials provided | ||
11 | * with the distribution. | ||
12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its | ||
13 | * contributors may be used to endorse or promote products derived | ||
14 | * from this software without specific prior written permission. | ||
15 | * | 6 | * |
16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | 7 | * This program is distributed in the hope that it will be useful, |
17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT | 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS | 10 | * GNU General Public License for more details. |
20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
27 | */ | 11 | */ |
28 | #ifndef __MACH_SCM_H | 12 | #ifndef __MACH_SCM_H |
29 | #define __MACH_SCM_H | 13 | #define __MACH_SCM_H |
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index c105d28b53e3..e7f8e5a4d48f 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c | |||
@@ -24,10 +24,7 @@ | |||
24 | 24 | ||
25 | #include <asm/mach/time.h> | 25 | #include <asm/mach/time.h> |
26 | #include <mach/msm_iomap.h> | 26 | #include <mach/msm_iomap.h> |
27 | 27 | #include <mach/cpu.h> | |
28 | #ifndef MSM_DGT_BASE | ||
29 | #define MSM_DGT_BASE (MSM_GPT_BASE + 0x10) | ||
30 | #endif | ||
31 | 28 | ||
32 | #define TIMER_MATCH_VAL 0x0000 | 29 | #define TIMER_MATCH_VAL 0x0000 |
33 | #define TIMER_COUNT_VAL 0x0004 | 30 | #define TIMER_COUNT_VAL 0x0004 |
@@ -52,18 +49,14 @@ enum timer_location { | |||
52 | GLOBAL_TIMER = 1, | 49 | GLOBAL_TIMER = 1, |
53 | }; | 50 | }; |
54 | 51 | ||
55 | #ifdef MSM_TMR0_BASE | ||
56 | #define MSM_TMR_GLOBAL (MSM_TMR0_BASE - MSM_TMR_BASE) | ||
57 | #else | ||
58 | #define MSM_TMR_GLOBAL 0 | ||
59 | #endif | ||
60 | |||
61 | #define MSM_GLOBAL_TIMER MSM_CLOCK_DGT | 52 | #define MSM_GLOBAL_TIMER MSM_CLOCK_DGT |
62 | 53 | ||
54 | /* TODO: Remove these ifdefs */ | ||
63 | #if defined(CONFIG_ARCH_QSD8X50) | 55 | #if defined(CONFIG_ARCH_QSD8X50) |
64 | #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */ | 56 | #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */ |
65 | #define MSM_DGT_SHIFT (0) | 57 | #define MSM_DGT_SHIFT (0) |
66 | #elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) | 58 | #elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \ |
59 | defined(CONFIG_ARCH_MSM8960) | ||
67 | #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */ | 60 | #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */ |
68 | #define MSM_DGT_SHIFT (0) | 61 | #define MSM_DGT_SHIFT (0) |
69 | #else | 62 | #else |
@@ -177,11 +170,7 @@ static struct msm_clock msm_clocks[] = { | |||
177 | .dev_id = &msm_clocks[0].clockevent, | 170 | .dev_id = &msm_clocks[0].clockevent, |
178 | .irq = INT_GP_TIMER_EXP | 171 | .irq = INT_GP_TIMER_EXP |
179 | }, | 172 | }, |
180 | .regbase = MSM_GPT_BASE, | ||
181 | .freq = GPT_HZ, | 173 | .freq = GPT_HZ, |
182 | .local_counter = MSM_GPT_BASE + TIMER_COUNT_VAL, | ||
183 | .global_counter = MSM_GPT_BASE + TIMER_COUNT_VAL + | ||
184 | MSM_TMR_GLOBAL, | ||
185 | }, | 174 | }, |
186 | [MSM_CLOCK_DGT] = { | 175 | [MSM_CLOCK_DGT] = { |
187 | .clockevent = { | 176 | .clockevent = { |
@@ -206,12 +195,8 @@ static struct msm_clock msm_clocks[] = { | |||
206 | .dev_id = &msm_clocks[1].clockevent, | 195 | .dev_id = &msm_clocks[1].clockevent, |
207 | .irq = INT_DEBUG_TIMER_EXP | 196 | .irq = INT_DEBUG_TIMER_EXP |
208 | }, | 197 | }, |
209 | .regbase = MSM_DGT_BASE, | ||
210 | .freq = DGT_HZ >> MSM_DGT_SHIFT, | 198 | .freq = DGT_HZ >> MSM_DGT_SHIFT, |
211 | .shift = MSM_DGT_SHIFT, | 199 | .shift = MSM_DGT_SHIFT, |
212 | .local_counter = MSM_DGT_BASE + TIMER_COUNT_VAL, | ||
213 | .global_counter = MSM_DGT_BASE + TIMER_COUNT_VAL + | ||
214 | MSM_TMR_GLOBAL, | ||
215 | } | 200 | } |
216 | }; | 201 | }; |
217 | 202 | ||
@@ -219,6 +204,25 @@ static void __init msm_timer_init(void) | |||
219 | { | 204 | { |
220 | int i; | 205 | int i; |
221 | int res; | 206 | int res; |
207 | int global_offset = 0; | ||
208 | |||
209 | if (cpu_is_msm7x01()) { | ||
210 | msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; | ||
211 | msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; | ||
212 | } else if (cpu_is_msm7x30()) { | ||
213 | msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04; | ||
214 | msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24; | ||
215 | } else if (cpu_is_qsd8x50()) { | ||
216 | msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; | ||
217 | msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; | ||
218 | } else if (cpu_is_msm8x60() || cpu_is_msm8960()) { | ||
219 | msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04; | ||
220 | msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24; | ||
221 | |||
222 | /* Use CPU0's timer as the global timer. */ | ||
223 | global_offset = MSM_TMR0_BASE - MSM_TMR_BASE; | ||
224 | } else | ||
225 | BUG(); | ||
222 | 226 | ||
223 | #ifdef CONFIG_ARCH_MSM_SCORPIONMP | 227 | #ifdef CONFIG_ARCH_MSM_SCORPIONMP |
224 | writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); | 228 | writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); |
@@ -228,6 +232,10 @@ static void __init msm_timer_init(void) | |||
228 | struct msm_clock *clock = &msm_clocks[i]; | 232 | struct msm_clock *clock = &msm_clocks[i]; |
229 | struct clock_event_device *ce = &clock->clockevent; | 233 | struct clock_event_device *ce = &clock->clockevent; |
230 | struct clocksource *cs = &clock->clocksource; | 234 | struct clocksource *cs = &clock->clocksource; |
235 | |||
236 | clock->local_counter = clock->regbase + TIMER_COUNT_VAL; | ||
237 | clock->global_counter = clock->local_counter + global_offset; | ||
238 | |||
231 | writel(0, clock->regbase + TIMER_ENABLE); | 239 | writel(0, clock->regbase + TIMER_ENABLE); |
232 | writel(0, clock->regbase + TIMER_CLEAR); | 240 | writel(0, clock->regbase + TIMER_CLEAR); |
233 | writel(~0, clock->regbase + TIMER_MATCH_VAL); | 241 | writel(~0, clock->regbase + TIMER_MATCH_VAL); |