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-rw-r--r--arch/arm/mach-msm/Makefile4
-rw-r--r--arch/arm/mach-msm/acpuclock-arm11.c525
-rw-r--r--arch/arm/mach-msm/acpuclock.h32
-rw-r--r--arch/arm/mach-msm/board-mahimahi.c1
-rw-r--r--arch/arm/mach-msm/board-msm7x27.c170
-rw-r--r--arch/arm/mach-msm/board-msm8x60.c5
-rw-r--r--arch/arm/mach-msm/board-sapphire.c1
-rw-r--r--arch/arm/mach-msm/clock-pcom.c18
-rw-r--r--arch/arm/mach-msm/dma.c3
-rw-r--r--arch/arm/mach-msm/idle.c49
-rw-r--r--arch/arm/mach-msm/include/mach/board.h10
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8960.h2
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x60.h2
-rw-r--r--arch/arm/mach-msm/include/mach/system.h19
-rw-r--r--arch/arm/mach-msm/io.c28
-rw-r--r--arch/arm/mach-msm/proc_comm.c1
-rw-r--r--arch/arm/mach-msm/smd.c7
-rw-r--r--arch/arm/mach-msm/timer.c2
18 files changed, 29 insertions, 850 deletions
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 4ad3969b9881..6a6c197212eb 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,11 +1,11 @@
1obj-y += io.o idle.o timer.o 1obj-y += io.o timer.o
2obj-y += clock.o 2obj-y += clock.o
3obj-$(CONFIG_DEBUG_FS) += clock-debug.o 3obj-$(CONFIG_DEBUG_FS) += clock-debug.o
4 4
5obj-$(CONFIG_MSM_VIC) += irq-vic.o 5obj-$(CONFIG_MSM_VIC) += irq-vic.o
6obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o 6obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
7 7
8obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o 8obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o
9obj-$(CONFIG_ARCH_MSM7X30) += dma.o 9obj-$(CONFIG_ARCH_MSM7X30) += dma.o
10obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o 10obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
11 11
diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c
deleted file mode 100644
index 805d4ee53f7e..000000000000
--- a/arch/arm/mach-msm/acpuclock-arm11.c
+++ /dev/null
@@ -1,525 +0,0 @@
1/* arch/arm/mach-msm/acpuclock.c
2 *
3 * MSM architecture clock driver
4 *
5 * Copyright (C) 2007 Google, Inc.
6 * Copyright (c) 2007 QUALCOMM Incorporated
7 * Author: San Mehat <san@android.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/list.h>
23#include <linux/errno.h>
24#include <linux/string.h>
25#include <linux/delay.h>
26#include <linux/clk.h>
27#include <linux/cpufreq.h>
28#include <linux/mutex.h>
29#include <linux/io.h>
30#include <mach/board.h>
31#include <mach/msm_iomap.h>
32
33#include "proc_comm.h"
34#include "acpuclock.h"
35
36
37#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
38#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
39#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
40
41/*
42 * ARM11 clock configuration for specific ACPU speeds
43 */
44
45#define ACPU_PLL_TCXO -1
46#define ACPU_PLL_0 0
47#define ACPU_PLL_1 1
48#define ACPU_PLL_2 2
49#define ACPU_PLL_3 3
50
51#define PERF_SWITCH_DEBUG 0
52#define PERF_SWITCH_STEP_DEBUG 0
53
54struct clock_state
55{
56 struct clkctl_acpu_speed *current_speed;
57 struct mutex lock;
58 uint32_t acpu_switch_time_us;
59 uint32_t max_speed_delta_khz;
60 uint32_t vdd_switch_time_us;
61 unsigned long power_collapse_khz;
62 unsigned long wait_for_irq_khz;
63};
64
65static struct clk *ebi1_clk;
66static struct clock_state drv_state = { 0 };
67
68static void __init acpuclk_init(void);
69
70/* MSM7201A Levels 3-6 all correspond to 1.2V, level 7 corresponds to 1.325V. */
71enum {
72 VDD_0 = 0,
73 VDD_1 = 1,
74 VDD_2 = 2,
75 VDD_3 = 3,
76 VDD_4 = 3,
77 VDD_5 = 3,
78 VDD_6 = 3,
79 VDD_7 = 7,
80 VDD_END
81};
82
83struct clkctl_acpu_speed {
84 unsigned int a11clk_khz;
85 int pll;
86 unsigned int a11clk_src_sel;
87 unsigned int a11clk_src_div;
88 unsigned int ahbclk_khz;
89 unsigned int ahbclk_div;
90 int vdd;
91 unsigned int axiclk_khz;
92 unsigned long lpj; /* loops_per_jiffy */
93/* Index in acpu_freq_tbl[] for steppings. */
94 short down;
95 short up;
96};
97
98/*
99 * ACPU speed table. Complete table is shown but certain speeds are commented
100 * out to optimized speed switching. Initialize loops_per_jiffy to 0.
101 *
102 * Table stepping up/down is optimized for 256mhz jumps while staying on the
103 * same PLL.
104 */
105#if (0)
106static struct clkctl_acpu_speed acpu_freq_tbl[] = {
107 { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 8 },
108 { 61440, ACPU_PLL_0, 4, 3, 61440, 0, VDD_0, 30720, 0, 0, 8 },
109 { 81920, ACPU_PLL_0, 4, 2, 40960, 1, VDD_0, 61440, 0, 0, 8 },
110 { 96000, ACPU_PLL_1, 1, 7, 48000, 1, VDD_0, 61440, 0, 0, 9 },
111 { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 8 },
112 { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 12 },
113 { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 11 },
114 { 192000, ACPU_PLL_1, 1, 3, 64000, 2, VDD_3, 61440, 0, 0, 12 },
115 { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 12 },
116 { 256000, ACPU_PLL_1, 1, 2, 128000, 2, VDD_5, 128000, 0, 0, 12 },
117 { 264000, ACPU_PLL_2, 2, 3, 88000, 2, VDD_5, 128000, 0, 6, 13 },
118 { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 6, 13 },
119 { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 5, -1 },
120 { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 11, -1 },
121 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
122};
123#else /* Table of freq we currently use. */
124static struct clkctl_acpu_speed acpu_freq_tbl[] = {
125 { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 4 },
126 { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 4 },
127 { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 6 },
128 { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 5 },
129 { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 5 },
130 { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 3, 7 },
131 { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, -1 },
132 { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 5, -1 },
133 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
134};
135#endif
136
137
138#ifdef CONFIG_CPU_FREQ_TABLE
139static struct cpufreq_frequency_table freq_table[] = {
140 { 0, 122880 },
141 { 1, 128000 },
142 { 2, 245760 },
143 { 3, 384000 },
144 { 4, 528000 },
145 { 5, CPUFREQ_TABLE_END },
146};
147#endif
148
149static int pc_pll_request(unsigned id, unsigned on)
150{
151 int res;
152 on = !!on;
153
154#if PERF_SWITCH_DEBUG
155 if (on)
156 printk(KERN_DEBUG "Enabling PLL %d\n", id);
157 else
158 printk(KERN_DEBUG "Disabling PLL %d\n", id);
159#endif
160
161 res = msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on);
162 if (res < 0)
163 return res;
164
165#if PERF_SWITCH_DEBUG
166 if (on)
167 printk(KERN_DEBUG "PLL %d enabled\n", id);
168 else
169 printk(KERN_DEBUG "PLL %d disabled\n", id);
170#endif
171 return res;
172}
173
174
175/*----------------------------------------------------------------------------
176 * ARM11 'owned' clock control
177 *---------------------------------------------------------------------------*/
178
179unsigned long acpuclk_power_collapse(void) {
180 int ret = acpuclk_get_rate();
181 ret *= 1000;
182 if (ret > drv_state.power_collapse_khz)
183 acpuclk_set_rate(drv_state.power_collapse_khz, 1);
184 return ret;
185}
186
187unsigned long acpuclk_get_wfi_rate(void)
188{
189 return drv_state.wait_for_irq_khz;
190}
191
192unsigned long acpuclk_wait_for_irq(void) {
193 int ret = acpuclk_get_rate();
194 ret *= 1000;
195 if (ret > drv_state.wait_for_irq_khz)
196 acpuclk_set_rate(drv_state.wait_for_irq_khz, 1);
197 return ret;
198}
199
200static int acpuclk_set_vdd_level(int vdd)
201{
202 uint32_t current_vdd;
203
204 current_vdd = readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07;
205
206#if PERF_SWITCH_DEBUG
207 printk(KERN_DEBUG "acpuclock: Switching VDD from %u -> %d\n",
208 current_vdd, vdd);
209#endif
210 writel((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR);
211 udelay(drv_state.vdd_switch_time_us);
212 if ((readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) {
213#if PERF_SWITCH_DEBUG
214 printk(KERN_ERR "acpuclock: VDD set failed\n");
215#endif
216 return -EIO;
217 }
218
219#if PERF_SWITCH_DEBUG
220 printk(KERN_DEBUG "acpuclock: VDD switched\n");
221#endif
222 return 0;
223}
224
225/* Set proper dividers for the given clock speed. */
226static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) {
227 uint32_t reg_clkctl, reg_clksel, clk_div;
228
229 /* AHB_CLK_DIV */
230 clk_div = (readl(A11S_CLK_SEL_ADDR) >> 1) & 0x03;
231 /*
232 * If the new clock divider is higher than the previous, then
233 * program the divider before switching the clock
234 */
235 if (hunt_s->ahbclk_div > clk_div) {
236 reg_clksel = readl(A11S_CLK_SEL_ADDR);
237 reg_clksel &= ~(0x3 << 1);
238 reg_clksel |= (hunt_s->ahbclk_div << 1);
239 writel(reg_clksel, A11S_CLK_SEL_ADDR);
240 }
241 if ((readl(A11S_CLK_SEL_ADDR) & 0x01) == 0) {
242 /* SRC0 */
243
244 /* Program clock source */
245 reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
246 reg_clkctl &= ~(0x07 << 4);
247 reg_clkctl |= (hunt_s->a11clk_src_sel << 4);
248 writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
249
250 /* Program clock divider */
251 reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
252 reg_clkctl &= ~0xf;
253 reg_clkctl |= hunt_s->a11clk_src_div;
254 writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
255
256 /* Program clock source selection */
257 reg_clksel = readl(A11S_CLK_SEL_ADDR);
258 reg_clksel |= 1; /* CLK_SEL_SRC1NO == SRC1 */
259 writel(reg_clksel, A11S_CLK_SEL_ADDR);
260 } else {
261 /* SRC1 */
262
263 /* Program clock source */
264 reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
265 reg_clkctl &= ~(0x07 << 12);
266 reg_clkctl |= (hunt_s->a11clk_src_sel << 12);
267 writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
268
269 /* Program clock divider */
270 reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
271 reg_clkctl &= ~(0xf << 8);
272 reg_clkctl |= (hunt_s->a11clk_src_div << 8);
273 writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
274
275 /* Program clock source selection */
276 reg_clksel = readl(A11S_CLK_SEL_ADDR);
277 reg_clksel &= ~1; /* CLK_SEL_SRC1NO == SRC0 */
278 writel(reg_clksel, A11S_CLK_SEL_ADDR);
279 }
280
281 /*
282 * If the new clock divider is lower than the previous, then
283 * program the divider after switching the clock
284 */
285 if (hunt_s->ahbclk_div < clk_div) {
286 reg_clksel = readl(A11S_CLK_SEL_ADDR);
287 reg_clksel &= ~(0x3 << 1);
288 reg_clksel |= (hunt_s->ahbclk_div << 1);
289 writel(reg_clksel, A11S_CLK_SEL_ADDR);
290 }
291}
292
293int acpuclk_set_rate(unsigned long rate, int for_power_collapse)
294{
295 uint32_t reg_clkctl;
296 struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s;
297 int rc = 0;
298 unsigned int plls_enabled = 0, pll;
299
300 strt_s = cur_s = drv_state.current_speed;
301
302 WARN_ONCE(cur_s == NULL, "acpuclk_set_rate: not initialized\n");
303 if (cur_s == NULL)
304 return -ENOENT;
305
306 if (rate == (cur_s->a11clk_khz * 1000))
307 return 0;
308
309 for (tgt_s = acpu_freq_tbl; tgt_s->a11clk_khz != 0; tgt_s++) {
310 if (tgt_s->a11clk_khz == (rate / 1000))
311 break;
312 }
313
314 if (tgt_s->a11clk_khz == 0)
315 return -EINVAL;
316
317 /* Choose the highest speed speed at or below 'rate' with same PLL. */
318 if (for_power_collapse && tgt_s->a11clk_khz < cur_s->a11clk_khz) {
319 while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll)
320 tgt_s--;
321 }
322
323 if (strt_s->pll != ACPU_PLL_TCXO)
324 plls_enabled |= 1 << strt_s->pll;
325
326 if (!for_power_collapse) {
327 mutex_lock(&drv_state.lock);
328 if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) {
329 rc = pc_pll_request(tgt_s->pll, 1);
330 if (rc < 0) {
331 pr_err("PLL%d enable failed (%d)\n",
332 tgt_s->pll, rc);
333 goto out;
334 }
335 plls_enabled |= 1 << tgt_s->pll;
336 }
337 /* Increase VDD if needed. */
338 if (tgt_s->vdd > cur_s->vdd) {
339 if ((rc = acpuclk_set_vdd_level(tgt_s->vdd)) < 0) {
340 printk(KERN_ERR "Unable to switch ACPU vdd\n");
341 goto out;
342 }
343 }
344 }
345
346 /* Set wait states for CPU between frequency changes */
347 reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
348 reg_clkctl |= (100 << 16); /* set WT_ST_CNT */
349 writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
350
351#if PERF_SWITCH_DEBUG
352 printk(KERN_INFO "acpuclock: Switching from ACPU rate %u -> %u\n",
353 strt_s->a11clk_khz * 1000, tgt_s->a11clk_khz * 1000);
354#endif
355
356 while (cur_s != tgt_s) {
357 /*
358 * Always jump to target freq if within 256mhz, regulardless of
359 * PLL. If differnece is greater, use the predefinied
360 * steppings in the table.
361 */
362 int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz));
363 if (d > drv_state.max_speed_delta_khz) {
364 /* Step up or down depending on target vs current. */
365 int clk_index = tgt_s->a11clk_khz > cur_s->a11clk_khz ?
366 cur_s->up : cur_s->down;
367 if (clk_index < 0) { /* This should not happen. */
368 printk(KERN_ERR "cur:%u target: %u\n",
369 cur_s->a11clk_khz, tgt_s->a11clk_khz);
370 rc = -EINVAL;
371 goto out;
372 }
373 cur_s = &acpu_freq_tbl[clk_index];
374 } else {
375 cur_s = tgt_s;
376 }
377#if PERF_SWITCH_STEP_DEBUG
378 printk(KERN_DEBUG "%s: STEP khz = %u, pll = %d\n",
379 __FUNCTION__, cur_s->a11clk_khz, cur_s->pll);
380#endif
381 if (!for_power_collapse&& cur_s->pll != ACPU_PLL_TCXO
382 && !(plls_enabled & (1 << cur_s->pll))) {
383 rc = pc_pll_request(cur_s->pll, 1);
384 if (rc < 0) {
385 pr_err("PLL%d enable failed (%d)\n",
386 cur_s->pll, rc);
387 goto out;
388 }
389 plls_enabled |= 1 << cur_s->pll;
390 }
391
392 acpuclk_set_div(cur_s);
393 drv_state.current_speed = cur_s;
394 /* Re-adjust lpj for the new clock speed. */
395 loops_per_jiffy = cur_s->lpj;
396 udelay(drv_state.acpu_switch_time_us);
397 }
398
399 /* Nothing else to do for power collapse. */
400 if (for_power_collapse)
401 return 0;
402
403 /* Disable PLLs we are not using anymore. */
404 plls_enabled &= ~(1 << tgt_s->pll);
405 for (pll = ACPU_PLL_0; pll <= ACPU_PLL_2; pll++)
406 if (plls_enabled & (1 << pll)) {
407 rc = pc_pll_request(pll, 0);
408 if (rc < 0) {
409 pr_err("PLL%d disable failed (%d)\n", pll, rc);
410 goto out;
411 }
412 }
413
414 /* Change the AXI bus frequency if we can. */
415 if (strt_s->axiclk_khz != tgt_s->axiclk_khz) {
416 rc = clk_set_rate(ebi1_clk, tgt_s->axiclk_khz * 1000);
417 if (rc < 0)
418 pr_err("Setting AXI min rate failed!\n");
419 }
420
421 /* Drop VDD level if we can. */
422 if (tgt_s->vdd < strt_s->vdd) {
423 if (acpuclk_set_vdd_level(tgt_s->vdd) < 0)
424 printk(KERN_ERR "acpuclock: Unable to drop ACPU vdd\n");
425 }
426
427#if PERF_SWITCH_DEBUG
428 printk(KERN_DEBUG "%s: ACPU speed change complete\n", __FUNCTION__);
429#endif
430out:
431 if (!for_power_collapse)
432 mutex_unlock(&drv_state.lock);
433 return rc;
434}
435
436static void __init acpuclk_init(void)
437{
438 struct clkctl_acpu_speed *speed;
439 uint32_t div, sel;
440 int rc;
441
442 /*
443 * Determine the rate of ACPU clock
444 */
445
446 if (!(readl(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */
447 /* CLK_SRC0_SEL */
448 sel = (readl(A11S_CLK_CNTL_ADDR) >> 12) & 0x7;
449 /* CLK_SRC0_DIV */
450 div = (readl(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f;
451 } else {
452 /* CLK_SRC1_SEL */
453 sel = (readl(A11S_CLK_CNTL_ADDR) >> 4) & 0x07;
454 /* CLK_SRC1_DIV */
455 div = readl(A11S_CLK_CNTL_ADDR) & 0x0f;
456 }
457
458 for (speed = acpu_freq_tbl; speed->a11clk_khz != 0; speed++) {
459 if (speed->a11clk_src_sel == sel
460 && (speed->a11clk_src_div == div))
461 break;
462 }
463 if (speed->a11clk_khz == 0) {
464 printk(KERN_WARNING "Warning - ACPU clock reports invalid speed\n");
465 return;
466 }
467
468 drv_state.current_speed = speed;
469
470 rc = clk_set_rate(ebi1_clk, speed->axiclk_khz * 1000);
471 if (rc < 0)
472 pr_err("Setting AXI min rate failed!\n");
473
474 printk(KERN_INFO "ACPU running at %d KHz\n", speed->a11clk_khz);
475}
476
477unsigned long acpuclk_get_rate(void)
478{
479 WARN_ONCE(drv_state.current_speed == NULL,
480 "acpuclk_get_rate: not initialized\n");
481 if (drv_state.current_speed)
482 return drv_state.current_speed->a11clk_khz;
483 else
484 return 0;
485}
486
487uint32_t acpuclk_get_switch_time(void)
488{
489 return drv_state.acpu_switch_time_us;
490}
491
492/*----------------------------------------------------------------------------
493 * Clock driver initialization
494 *---------------------------------------------------------------------------*/
495
496/* Initialize the lpj field in the acpu_freq_tbl. */
497static void __init lpj_init(void)
498{
499 int i;
500 const struct clkctl_acpu_speed *base_clk = drv_state.current_speed;
501 for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) {
502 acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy,
503 base_clk->a11clk_khz,
504 acpu_freq_tbl[i].a11clk_khz);
505 }
506}
507
508void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata)
509{
510 pr_info("acpu_clock_init()\n");
511
512 ebi1_clk = clk_get(NULL, "ebi1_clk");
513
514 mutex_init(&drv_state.lock);
515 drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us;
516 drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz;
517 drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
518 drv_state.power_collapse_khz = clkdata->power_collapse_khz;
519 drv_state.wait_for_irq_khz = clkdata->wait_for_irq_khz;
520 acpuclk_init();
521 lpj_init();
522#ifdef CONFIG_CPU_FREQ_TABLE
523 cpufreq_frequency_table_get_attr(freq_table, smp_processor_id());
524#endif
525}
diff --git a/arch/arm/mach-msm/acpuclock.h b/arch/arm/mach-msm/acpuclock.h
deleted file mode 100644
index 415de2eb9a5e..000000000000
--- a/arch/arm/mach-msm/acpuclock.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/* arch/arm/mach-msm/acpuclock.h
2 *
3 * MSM architecture clock driver header
4 *
5 * Copyright (C) 2007 Google, Inc.
6 * Copyright (c) 2007 QUALCOMM Incorporated
7 * Author: San Mehat <san@android.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
21#define __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
22
23int acpuclk_set_rate(unsigned long rate, int for_power_collapse);
24unsigned long acpuclk_get_rate(void);
25uint32_t acpuclk_get_switch_time(void);
26unsigned long acpuclk_wait_for_irq(void);
27unsigned long acpuclk_power_collapse(void);
28unsigned long acpuclk_get_wfi_rate(void);
29
30
31#endif
32
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index cf1f89a5dc62..df00bc03ce74 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -30,7 +30,6 @@
30 30
31#include <mach/board.h> 31#include <mach/board.h>
32#include <mach/hardware.h> 32#include <mach/hardware.h>
33#include <mach/system.h>
34 33
35#include "board-mahimahi.h" 34#include "board-mahimahi.h"
36#include "devices.h" 35#include "devices.h"
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c
deleted file mode 100644
index 451ab1d43c92..000000000000
--- a/arch/arm/mach-msm/board-msm7x27.c
+++ /dev/null
@@ -1,170 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16#include <linux/gpio.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/platform_device.h>
20#include <linux/input.h>
21#include <linux/io.h>
22#include <linux/delay.h>
23#include <linux/power_supply.h>
24
25#include <mach/hardware.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/flash.h>
30#include <asm/setup.h>
31#ifdef CONFIG_CACHE_L2X0
32#include <asm/hardware/cache-l2x0.h>
33#endif
34
35#include <mach/vreg.h>
36#include <mach/mpp.h>
37#include <mach/board.h>
38#include <mach/msm_iomap.h>
39
40#include <linux/mtd/nand.h>
41#include <linux/mtd/partitions.h>
42
43#include "devices.h"
44#include "socinfo.h"
45#include "clock.h"
46
47static struct resource smc91x_resources[] = {
48 [0] = {
49 .start = 0x9C004300,
50 .end = 0x9C0043ff,
51 .flags = IORESOURCE_MEM,
52 },
53 [1] = {
54 .start = MSM_GPIO_TO_INT(132),
55 .end = MSM_GPIO_TO_INT(132),
56 .flags = IORESOURCE_IRQ,
57 },
58};
59
60static struct platform_device smc91x_device = {
61 .name = "smc91x",
62 .id = 0,
63 .num_resources = ARRAY_SIZE(smc91x_resources),
64 .resource = smc91x_resources,
65};
66
67static struct platform_device *devices[] __initdata = {
68 &msm_device_uart3,
69 &msm_device_smd,
70 &msm_device_dmov,
71 &msm_device_nand,
72 &smc91x_device,
73};
74
75extern struct sys_timer msm_timer;
76
77static void __init msm7x2x_init_irq(void)
78{
79 msm_init_irq();
80}
81
82static void __init msm7x2x_init(void)
83{
84 if (socinfo_init() < 0)
85 BUG();
86
87 if (machine_is_msm7x25_ffa() || machine_is_msm7x27_ffa()) {
88 smc91x_resources[0].start = 0x98000300;
89 smc91x_resources[0].end = 0x980003ff;
90 smc91x_resources[1].start = MSM_GPIO_TO_INT(85);
91 smc91x_resources[1].end = MSM_GPIO_TO_INT(85);
92 if (gpio_tlmm_config(GPIO_CFG(85, 0,
93 GPIO_INPUT,
94 GPIO_PULL_DOWN,
95 GPIO_2MA),
96 GPIO_ENABLE)) {
97 printk(KERN_ERR
98 "%s: Err: Config GPIO-85 INT\n",
99 __func__);
100 }
101 }
102
103 platform_add_devices(devices, ARRAY_SIZE(devices));
104}
105
106static void __init msm7x2x_map_io(void)
107{
108 msm_map_common_io();
109 /* Technically dependent on the SoC but using machine_is
110 * macros since socinfo is not available this early and there
111 * are plans to restructure the code which will eliminate the
112 * need for socinfo.
113 */
114 if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa())
115 msm_clock_init(msm_clocks_7x27, msm_num_clocks_7x27);
116
117 if (machine_is_msm7x25_surf() || machine_is_msm7x25_ffa())
118 msm_clock_init(msm_clocks_7x25, msm_num_clocks_7x25);
119
120#ifdef CONFIG_CACHE_L2X0
121 if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) {
122 /* 7x27 has 256KB L2 cache:
123 64Kb/Way and 4-Way Associativity;
124 R/W latency: 3 cycles;
125 evmon/parity/share disabled. */
126 l2x0_init(MSM_L2CC_BASE, 0x00068012, 0xfe000000);
127 }
128#endif
129}
130
131static void __init msm7x2x_init_late(void)
132{
133 smd_debugfs_init();
134}
135
136MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
137 .atag_offset = 0x100,
138 .map_io = msm7x2x_map_io,
139 .init_irq = msm7x2x_init_irq,
140 .init_machine = msm7x2x_init,
141 .init_late = msm7x2x_init_late,
142 .timer = &msm_timer,
143MACHINE_END
144
145MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
146 .atag_offset = 0x100,
147 .map_io = msm7x2x_map_io,
148 .init_irq = msm7x2x_init_irq,
149 .init_machine = msm7x2x_init,
150 .init_late = msm7x2x_init_late,
151 .timer = &msm_timer,
152MACHINE_END
153
154MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
155 .atag_offset = 0x100,
156 .map_io = msm7x2x_map_io,
157 .init_irq = msm7x2x_init_irq,
158 .init_machine = msm7x2x_init,
159 .init_late = msm7x2x_init_late,
160 .timer = &msm_timer,
161MACHINE_END
162
163MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA")
164 .atag_offset = 0x100,
165 .map_io = msm7x2x_map_io,
166 .init_irq = msm7x2x_init_irq,
167 .init_machine = msm7x2x_init,
168 .init_late = msm7x2x_init_late,
169 .timer = &msm_timer,
170MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index e37a724cd1eb..06003b4ccb10 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -93,11 +93,6 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
93 93
94static void __init msm8x60_dt_init(void) 94static void __init msm8x60_dt_init(void)
95{ 95{
96 if (of_machine_is_compatible("qcom,msm8660-surf")) {
97 printk(KERN_INFO "Init surf UART registers\n");
98 msm8x60_init_uart12dm();
99 }
100
101 of_platform_populate(NULL, of_default_bus_match_table, 96 of_platform_populate(NULL, of_default_bus_match_table,
102 msm_auxdata_lookup, NULL); 97 msm_auxdata_lookup, NULL);
103} 98}
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 2e569ab10eef..b7b0fc7e3278 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -27,7 +27,6 @@
27#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
28#include <asm/mach/map.h> 28#include <asm/mach/map.h>
29#include <asm/mach/flash.h> 29#include <asm/mach/flash.h>
30#include <mach/system.h>
31#include <mach/vreg.h> 30#include <mach/vreg.h>
32#include <mach/board.h> 31#include <mach/board.h>
33 32
diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
index 63b711311086..a52c970df157 100644
--- a/arch/arm/mach-msm/clock-pcom.c
+++ b/arch/arm/mach-msm/clock-pcom.c
@@ -25,7 +25,7 @@
25/* 25/*
26 * glue for the proc_comm interface 26 * glue for the proc_comm interface
27 */ 27 */
28int pc_clk_enable(unsigned id) 28static int pc_clk_enable(unsigned id)
29{ 29{
30 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL); 30 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
31 if (rc < 0) 31 if (rc < 0)
@@ -34,7 +34,7 @@ int pc_clk_enable(unsigned id)
34 return (int)id < 0 ? -EINVAL : 0; 34 return (int)id < 0 ? -EINVAL : 0;
35} 35}
36 36
37void pc_clk_disable(unsigned id) 37static void pc_clk_disable(unsigned id)
38{ 38{
39 msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL); 39 msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
40} 40}
@@ -54,7 +54,7 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action)
54 return (int)id < 0 ? -EINVAL : 0; 54 return (int)id < 0 ? -EINVAL : 0;
55} 55}
56 56
57int pc_clk_set_rate(unsigned id, unsigned rate) 57static int pc_clk_set_rate(unsigned id, unsigned rate)
58{ 58{
59 /* The rate _might_ be rounded off to the nearest KHz value by the 59 /* The rate _might_ be rounded off to the nearest KHz value by the
60 * remote function. So a return value of 0 doesn't necessarily mean 60 * remote function. So a return value of 0 doesn't necessarily mean
@@ -67,7 +67,7 @@ int pc_clk_set_rate(unsigned id, unsigned rate)
67 return (int)id < 0 ? -EINVAL : 0; 67 return (int)id < 0 ? -EINVAL : 0;
68} 68}
69 69
70int pc_clk_set_min_rate(unsigned id, unsigned rate) 70static int pc_clk_set_min_rate(unsigned id, unsigned rate)
71{ 71{
72 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate); 72 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
73 if (rc < 0) 73 if (rc < 0)
@@ -76,7 +76,7 @@ int pc_clk_set_min_rate(unsigned id, unsigned rate)
76 return (int)id < 0 ? -EINVAL : 0; 76 return (int)id < 0 ? -EINVAL : 0;
77} 77}
78 78
79int pc_clk_set_max_rate(unsigned id, unsigned rate) 79static int pc_clk_set_max_rate(unsigned id, unsigned rate)
80{ 80{
81 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate); 81 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
82 if (rc < 0) 82 if (rc < 0)
@@ -85,7 +85,7 @@ int pc_clk_set_max_rate(unsigned id, unsigned rate)
85 return (int)id < 0 ? -EINVAL : 0; 85 return (int)id < 0 ? -EINVAL : 0;
86} 86}
87 87
88int pc_clk_set_flags(unsigned id, unsigned flags) 88static int pc_clk_set_flags(unsigned id, unsigned flags)
89{ 89{
90 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags); 90 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags);
91 if (rc < 0) 91 if (rc < 0)
@@ -94,7 +94,7 @@ int pc_clk_set_flags(unsigned id, unsigned flags)
94 return (int)id < 0 ? -EINVAL : 0; 94 return (int)id < 0 ? -EINVAL : 0;
95} 95}
96 96
97unsigned pc_clk_get_rate(unsigned id) 97static unsigned pc_clk_get_rate(unsigned id)
98{ 98{
99 if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL)) 99 if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
100 return 0; 100 return 0;
@@ -102,7 +102,7 @@ unsigned pc_clk_get_rate(unsigned id)
102 return id; 102 return id;
103} 103}
104 104
105unsigned pc_clk_is_enabled(unsigned id) 105static unsigned pc_clk_is_enabled(unsigned id)
106{ 106{
107 if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL)) 107 if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
108 return 0; 108 return 0;
@@ -110,7 +110,7 @@ unsigned pc_clk_is_enabled(unsigned id)
110 return id; 110 return id;
111} 111}
112 112
113long pc_clk_round_rate(unsigned id, unsigned rate) 113static long pc_clk_round_rate(unsigned id, unsigned rate)
114{ 114{
115 115
116 /* Not really supported; pc_clk_set_rate() does rounding on it's own. */ 116 /* Not really supported; pc_clk_set_rate() does rounding on it's own. */
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index 02cae5e2951c..354b91d4c3ac 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -223,8 +223,7 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id)
223 PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); 223 PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
224 if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) { 224 if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) {
225 cmd = list_entry(ready_commands[id].next, typeof(*cmd), list); 225 cmd = list_entry(ready_commands[id].next, typeof(*cmd), list);
226 list_del(&cmd->list); 226 list_move_tail(&cmd->list, &active_commands[id]);
227 list_add_tail(&cmd->list, &active_commands[id]);
228 if (cmd->execute_func) 227 if (cmd->execute_func)
229 cmd->execute_func(cmd); 228 cmd->execute_func(cmd);
230 PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id); 229 PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id);
diff --git a/arch/arm/mach-msm/idle.c b/arch/arm/mach-msm/idle.c
deleted file mode 100644
index 0c9e13c65743..000000000000
--- a/arch/arm/mach-msm/idle.c
+++ /dev/null
@@ -1,49 +0,0 @@
1/* arch/arm/mach-msm/idle.c
2 *
3 * Idle processing for MSM7K - work around bugs with SWFI.
4 *
5 * Copyright (c) 2007 QUALCOMM Incorporated.
6 * Copyright (C) 2007 Google, Inc.
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#include <linux/init.h>
20#include <asm/system.h>
21
22static void msm_idle(void)
23{
24#ifdef CONFIG_MSM7X00A_IDLE
25 asm volatile (
26
27 "mrc p15, 0, r1, c1, c0, 0 /* read current CR */ \n\t"
28 "bic r0, r1, #(1 << 2) /* clear dcache bit */ \n\t"
29 "bic r0, r0, #(1 << 12) /* clear icache bit */ \n\t"
30 "mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */ \n\t"
31
32 "mov r0, #0 /* prepare wfi value */ \n\t"
33 "mcr p15, 0, r0, c7, c10, 0 /* flush the cache */ \n\t"
34 "mcr p15, 0, r0, c7, c10, 4 /* memory barrier */ \n\t"
35 "mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */ \n\t"
36
37 "mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */ \n\t"
38
39 : : : "r0","r1" );
40#endif
41}
42
43static int __init msm_idle_init(void)
44{
45 arm_pm_idle = msm_idle;
46 return 0;
47}
48
49arch_initcall(msm_idle_init);
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 435f8edfafd1..5a0811a4c851 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -22,15 +22,6 @@
22 22
23/* platform device data structures */ 23/* platform device data structures */
24 24
25struct msm_acpu_clock_platform_data
26{
27 uint32_t acpu_switch_time_us;
28 uint32_t max_speed_delta_khz;
29 uint32_t vdd_switch_time_us;
30 unsigned long power_collapse_khz;
31 unsigned long wait_for_irq_khz;
32};
33
34struct clk_lookup; 25struct clk_lookup;
35 26
36extern struct sys_timer msm_timer; 27extern struct sys_timer msm_timer;
@@ -42,7 +33,6 @@ void __init msm_map_common_io(void);
42void __init msm_init_irq(void); 33void __init msm_init_irq(void);
43void __init msm_init_gpio(void); 34void __init msm_init_gpio(void);
44void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks); 35void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks);
45void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *);
46int __init msm_add_sdcc(unsigned int controller, 36int __init msm_add_sdcc(unsigned int controller,
47 struct msm_mmc_platform_data *plat, 37 struct msm_mmc_platform_data *plat,
48 unsigned int stat_irq, unsigned long stat_irq_flags); 38 unsigned int stat_irq, unsigned long stat_irq_flags);
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
index a1752c0284fc..facf434d09be 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -46,7 +46,7 @@
46#define MSM8960_TMR0_SIZE SZ_4K 46#define MSM8960_TMR0_SIZE SZ_4K
47 47
48#ifdef CONFIG_DEBUG_MSM8960_UART 48#ifdef CONFIG_DEBUG_MSM8960_UART
49#define MSM_DEBUG_UART_BASE 0xE1040000 49#define MSM_DEBUG_UART_BASE 0xF0040000
50#define MSM_DEBUG_UART_PHYS 0x16440000 50#define MSM_DEBUG_UART_PHYS 0x16440000
51#endif 51#endif
52 52
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 5aed57dc808c..21a2a8859a9a 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -63,7 +63,7 @@
63#define MSM8X60_TMR0_SIZE SZ_4K 63#define MSM8X60_TMR0_SIZE SZ_4K
64 64
65#ifdef CONFIG_DEBUG_MSM8660_UART 65#ifdef CONFIG_DEBUG_MSM8660_UART
66#define MSM_DEBUG_UART_BASE 0xE1040000 66#define MSM_DEBUG_UART_BASE 0xF0040000
67#define MSM_DEBUG_UART_PHYS 0x19C40000 67#define MSM_DEBUG_UART_PHYS 0x19C40000
68#endif 68#endif
69 69
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h
deleted file mode 100644
index f5fb2ec87ffe..000000000000
--- a/arch/arm/mach-msm/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* arch/arm/mach-msm/include/mach/system.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16/* low level hardware reset hook -- for example, hitting the
17 * PSHOLD line on the PMIC to hard reset the system
18 */
19extern void (*msm_hw_reset_hook)(void);
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index a1e7b1168850..3cb4f4c35710 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -29,30 +29,30 @@
29 29
30#include <mach/board.h> 30#include <mach/board.h>
31 31
32#define MSM_CHIP_DEVICE(name, chip) { \ 32#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \
33 .virtual = (unsigned long) MSM_##name##_BASE, \ 33 .virtual = (unsigned long) MSM_##name##_BASE, \
34 .pfn = __phys_to_pfn(chip##_##name##_PHYS), \ 34 .pfn = __phys_to_pfn(chip##_##name##_PHYS), \
35 .length = chip##_##name##_SIZE, \ 35 .length = chip##_##name##_SIZE, \
36 .type = MT_DEVICE_NONSHARED, \ 36 .type = mem_type, \
37 } 37 }
38 38
39#define MSM_DEVICE_TYPE(name, mem_type) \
40 MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type)
41#define MSM_CHIP_DEVICE(name, chip) \
42 MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE)
39#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM) 43#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
40 44
41#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \ 45#if defined(CONFIG_ARCH_MSM7X00A)
42 || defined(CONFIG_ARCH_MSM7X25)
43static struct map_desc msm_io_desc[] __initdata = { 46static struct map_desc msm_io_desc[] __initdata = {
44 MSM_DEVICE(VIC), 47 MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED),
45 MSM_CHIP_DEVICE(CSR, MSM7X00), 48 MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED),
46 MSM_DEVICE(DMOV), 49 MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED),
47 MSM_CHIP_DEVICE(GPIO1, MSM7X00), 50 MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED),
48 MSM_CHIP_DEVICE(GPIO2, MSM7X00), 51 MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED),
49 MSM_DEVICE(CLK_CTL), 52 MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED),
50#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ 53#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
51 defined(CONFIG_DEBUG_MSM_UART3) 54 defined(CONFIG_DEBUG_MSM_UART3)
52 MSM_DEVICE(DEBUG_UART), 55 MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED),
53#endif
54#ifdef CONFIG_ARCH_MSM7X30
55 MSM_DEVICE(GCC),
56#endif 56#endif
57 { 57 {
58 .virtual = (unsigned long) MSM_SHARED_RAM_BASE, 58 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
diff --git a/arch/arm/mach-msm/proc_comm.c b/arch/arm/mach-msm/proc_comm.c
index 9980dc736e7b..8f1eecd88186 100644
--- a/arch/arm/mach-msm/proc_comm.c
+++ b/arch/arm/mach-msm/proc_comm.c
@@ -19,7 +19,6 @@
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/spinlock.h> 20#include <linux/spinlock.h>
21#include <mach/msm_iomap.h> 21#include <mach/msm_iomap.h>
22#include <mach/system.h>
23 22
24#include "proc_comm.h" 23#include "proc_comm.h"
25 24
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index 657be73297db..84183ed2ef79 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -30,7 +30,6 @@
30#include <linux/delay.h> 30#include <linux/delay.h>
31 31
32#include <mach/msm_smd.h> 32#include <mach/msm_smd.h>
33#include <mach/system.h>
34 33
35#include "smd_private.h" 34#include "smd_private.h"
36#include "proc_comm.h" 35#include "proc_comm.h"
@@ -39,8 +38,6 @@
39#define CONFIG_QDSP6 1 38#define CONFIG_QDSP6 1
40#endif 39#endif
41 40
42void (*msm_hw_reset_hook)(void);
43
44#define MODULE_NAME "msm_smd" 41#define MODULE_NAME "msm_smd"
45 42
46enum { 43enum {
@@ -101,10 +98,6 @@ static void handle_modem_crash(void)
101 pr_err("ARM9 has CRASHED\n"); 98 pr_err("ARM9 has CRASHED\n");
102 smd_diag(); 99 smd_diag();
103 100
104 /* hard reboot if possible */
105 if (msm_hw_reset_hook)
106 msm_hw_reset_hook();
107
108 /* in this case the modem or watchdog should reboot us */ 101 /* in this case the modem or watchdog should reboot us */
109 for (;;) 102 for (;;)
110 ; 103 ;
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 812808254936..004f93515a4e 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -101,7 +101,7 @@ static struct clock_event_device msm_clockevent = {
101 101
102static union { 102static union {
103 struct clock_event_device *evt; 103 struct clock_event_device *evt;
104 struct clock_event_device __percpu **percpu_evt; 104 struct clock_event_device * __percpu *percpu_evt;
105} msm_evt; 105} msm_evt;
106 106
107static void __iomem *source_base; 107static void __iomem *source_base;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-30 22:06:45 -0500