124 files changed, 4581 insertions, 904 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 346f62aedbd4..d7c0984d4a86 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -29,6 +29,10 @@ config GENERIC_TIME
        bool
        default n
+config GENERIC_CLOCKEVENTS
+        bool
+        default n
 config MMU
        bool
        default y
@@ -67,6 +71,14 @@ config GENERIC_HARDIRQS
        bool
        default y
+config STACKTRACE_SUPPORT
+        bool
+        default y
+config LOCKDEP_SUPPORT
+        bool
+        default y
 config TRACE_IRQFLAGS_SUPPORT
        bool
        default y
@@ -162,6 +174,8 @@ config ARCH_VERSATILE
        select ARM_AMBA
        select ARM_VIC
        select ICST307
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
        help
          This enables support for ARM Ltd Versatile board.
@@ -255,6 +269,7 @@ config ARCH_IOP13XX
        depends on MMU
        select PLAT_IOP
        select PCI
+        select ARCH_SUPPORTS_MSI
        help
          Support for Intel's IOP13XX (XScale) family of processors.
@@ -262,6 +277,7 @@ config ARCH_IXP4XX
        bool "IXP4xx-based"
        depends on MMU
        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
        help
          Support for Intel's IXP4XX (XScale) family of processors.
@@ -364,6 +380,7 @@ config ARCH_LH7A40X
 config ARCH_OMAP
        bool "TI OMAP"
        select GENERIC_GPIO
+        select GENERIC_TIME
        help
          Support for TI's OMAP platform (OMAP1 and OMAP2).
@@ -514,6 +531,8 @@ endmenu
 menu "Kernel Features"
+source "kernel/time/Kconfig"
 config SMP
        bool "Symmetric Multi-Processing (EXPERIMENTAL)"
        depends on EXPERIMENTAL && REALVIEW_MPCORE
@@ -573,6 +592,7 @@ config PREEMPT
 config NO_IDLE_HZ
        bool "Dynamic tick timer"
+        depends on !GENERIC_CLOCKEVENTS
        help
          Select this option if you want to disable continuous timer ticks
          and have them programmed to occur as required. This option saves
@@ -670,6 +690,7 @@ config LEDS_TIMER
        bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
                            MACH_OMAP_H2 || MACH_OMAP_PERSEUS2
        depends on LEDS
+        depends on !GENERIC_CLOCKEVENTS
        default y if ARCH_EBSA110
        help
          If you say Y here, one of the system LEDs (the green one on the
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ab9f2d4bd04e..00ea4305ad5d 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -47,8 +47,13 @@ comma = ,
 # Note that GCC does not numerically define an architecture version
 # macro, but instead defines a whole series of macros which makes
 # testing for a specific architecture or later rather impossible.
+arch-$(CONFIG_CPU_32v7)         :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7a,-march=armv5t -Wa$(comma)-march=armv7a)
 arch-$(CONFIG_CPU_32v6)         :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
+# Only override the compiler option if ARMv6. The ARMv6K extensions are
+# always available in ARMv7
+ifeq ($(CONFIG_CPU_32v6),y)
 arch-$(CONFIG_CPU_32v6K)        :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)
+endif
 arch-$(CONFIG_CPU_32v5)         :=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)
 arch-$(CONFIG_CPU_32v4T)        :=-D__LINUX_ARM_ARCH__=4 -march=armv4t
 arch-$(CONFIG_CPU_32v4)         :=-D__LINUX_ARM_ARCH__=4 -march=armv4
diff --git a/arch/arm/boot/compressed/head-at91rm9200.S b/arch/arm/boot/compressed/head-at91rm9200.S
index d68b9acd826e..11782ccd93a1 100644
--- a/arch/arm/boot/compressed/head-at91rm9200.S
+++ b/arch/arm/boot/compressed/head-at91rm9200.S
@@ -61,6 +61,12 @@
                cmp     r7, r3
                beq     99f
+                @ picotux 200 : 963
+                mov     r3,     #(MACH_TYPE_PICOTUX2XX & 0xff)
+                orr     r3, r3, #(MACH_TYPE_PICOTUX2XX & 0xff00)
+                cmp     r7, r3
+                beq     99f
                @ Ajeco 1ARM : 1075
                mov     r3,     #(MACH_TYPE_ONEARM & 0xff)
                orr     r3, r3, #(MACH_TYPE_ONEARM & 0xff00)
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 283891c736c4..9b444022cb9b 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -239,7 +239,7 @@ extern int end;
 static ulg free_mem_ptr;
 static ulg free_mem_ptr_end;
-#define HEAP_SIZE 0x2000
+#define HEAP_SIZE 0x3000
 #include "../../../../lib/inflate.c"
diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c
index a9bc5b52218f..5972df2b9af4 100644
--- a/arch/arm/common/sharpsl_pm.c
+++ b/arch/arm/common/sharpsl_pm.c
@@ -766,10 +766,10 @@ static void sharpsl_apm_get_power_status(struct apm_power_info *info)
 }
 static struct pm_ops sharpsl_pm_ops = {
-        .pm_disk_mode   = PM_DISK_FIRMWARE,
        .prepare        = pxa_pm_prepare,
        .enter          = corgi_pxa_pm_enter,
        .finish         = pxa_pm_finish,
+        .valid          = pm_valid_only_mem,
 };
 static int __init sharpsl_pm_probe(struct platform_device *pdev)
diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig
index fabf74c51a88..db850a5689eb 100644
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -117,11 +117,13 @@ CONFIG_ARCH_ADI_COYOTE=y
 CONFIG_ARCH_IXDP425=y
 CONFIG_MACH_IXDPG425=y
 CONFIG_MACH_IXDP465=y
+CONFIG_MACH_KIXRP435=y
 CONFIG_ARCH_IXCDP1100=y
 CONFIG_ARCH_PRPMC1100=y
 CONFIG_MACH_NAS100D=y
 CONFIG_ARCH_IXDP4XX=y
 CONFIG_CPU_IXP46X=y
+CONFIG_CPU_IXP43X=y
 # CONFIG_MACH_GTWX5715 is not set
 #
diff --git a/arch/arm/configs/picotux200_defconfig b/arch/arm/configs/picotux200_defconfig
new file mode 100644
index 000000000000..339c48953a62
--- /dev/null
+++ b/arch/arm/configs/picotux200_defconfig
@@ -0,0 +1,1386 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.21-rc4
+# Wed Mar 28 16:19:50 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_UTS_NS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=m
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_KALLSYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SHMEM=y
+CONFIG_SLAB=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_SLOB is not set
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+#
+# Block layer
+#
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_OMAP is not set
+#
+# Atmel AT91 System-on-Chip
+#
+CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+#
+# AT91RM9200 Board Type
+#
+# CONFIG_MACH_ONEARM is not set
+# CONFIG_ARCH_AT91RM9200DK is not set
+# CONFIG_MACH_AT91RM9200EK is not set
+# CONFIG_MACH_CSB337 is not set
+# CONFIG_MACH_CSB637 is not set
+# CONFIG_MACH_CARMEVA is not set
+# CONFIG_MACH_ATEB9200 is not set
+# CONFIG_MACH_KB9200 is not set
+CONFIG_MACH_PICOTUX2XX=y
+# CONFIG_MACH_KAFA is not set
+#
+# AT91 Board Options
+#
+#
+# AT91 Feature Selections
+#
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
+#
+# Bus support
+#
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+# CONFIG_PREEMPT is not set
+CONFIG_NO_IDLE_HZ=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=m
+#
+# Power management options
+#
+# CONFIG_PM is not set
+#
+# Networking
+#
+CONFIG_NET=y
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=m
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=y
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_BRIDGE=m
+CONFIG_VLAN_8021Q=m
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIUSB=m
+CONFIG_BT_HCIUSB_SCO=y
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_IEEE80211 is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x8000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+#
+# OneNAND Flash Device Drivers
+#
+# CONFIG_MTD_ONENAND is not set
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+#
+# Plug and Play support
+#
+# CONFIG_PNPACPI is not set
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+#
+# SCSI low-level drivers
+#
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+#
+# Serial ATA (prod) and Parallel ATA (experimental) drivers
+#
+# CONFIG_ATA is not set
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+#
+# IEEE 1394 (FireWire) support
+#
+#
+# I2O device support
+#
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+#
+# PHY device support
+#
+# CONFIG_PHYLIB is not set
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_ARM_AT91_ETHER=y
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+#
+# Ethernet (1000 Mbit)
+#
+#
+# Ethernet (10000 Mbit)
+#
+#
+# Token Ring devices
+#
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_SLIP=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
+CONFIG_SLIP_SMART=y
+CONFIG_SLIP_MODE_SLIP6=y
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91RM9200_WATCHDOG=m
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_NVRAM is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+#
+# I2C support
+#
+CONFIG_I2C=m
+CONFIG_I2C_CHARDEV=m
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+#
+# I2C Hardware Bus support
+#
+CONFIG_I2C_AT91=m
+CONFIG_I2C_ISA=m
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_PCA_ISA is not set
+#
+# Miscellaneous I2C Chip support
+#
+CONFIG_SENSORS_DS1337=m
+CONFIG_SENSORS_DS1374=m
+CONFIG_SENSORS_EEPROM=m
+CONFIG_SENSORS_PCF8574=m
+CONFIG_SENSORS_PCA9539=m
+CONFIG_SENSORS_PCF8591=m
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+#
+# Hardware Monitoring support
+#
+CONFIG_HWMON=m
+CONFIG_HWMON_VID=m
+# CONFIG_SENSORS_ABITUGURU is not set
+CONFIG_SENSORS_ADM1021=m
+CONFIG_SENSORS_ADM1025=m
+CONFIG_SENSORS_ADM1026=m
+CONFIG_SENSORS_ADM1029=m
+CONFIG_SENSORS_ADM1031=m
+CONFIG_SENSORS_ADM9240=m
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+CONFIG_SENSORS_DS1621=m
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+CONFIG_SENSORS_GL518SM=m
+CONFIG_SENSORS_GL520SM=m
+CONFIG_SENSORS_IT87=m
+CONFIG_SENSORS_LM63=m
+CONFIG_SENSORS_LM75=m
+CONFIG_SENSORS_LM77=m
+CONFIG_SENSORS_LM78=m
+CONFIG_SENSORS_LM80=m
+CONFIG_SENSORS_LM83=m
+CONFIG_SENSORS_LM85=m
+CONFIG_SENSORS_LM87=m
+CONFIG_SENSORS_LM90=m
+CONFIG_SENSORS_LM92=m
+CONFIG_SENSORS_MAX1619=m
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+CONFIG_SENSORS_SMSC47B397=m
+# CONFIG_SENSORS_VT1211 is not set
+CONFIG_SENSORS_W83781D=m
+CONFIG_SENSORS_W83791D=m
+CONFIG_SENSORS_W83792D=m
+CONFIG_SENSORS_W83793=m
+CONFIG_SENSORS_W83L785TS=m
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+#
+# Misc devices
+#
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+#
+# LED drivers
+#
+#
+# LED Triggers
+#
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+# CONFIG_USB_DABUSB is not set
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_FB is not set
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+#
+# HID Devices
+#
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=m
+# CONFIG_USB_DEBUG is not set
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=m
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_AIPTEK is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_ACECAD is not set
+# CONFIG_USB_KBTAB is not set
+# CONFIG_USB_POWERMATE is not set
+# CONFIG_USB_TOUCHSCREEN is not set
+# CONFIG_USB_YEALINK is not set
+# CONFIG_USB_XPAD is not set
+# CONFIG_USB_ATI_REMOTE is not set
+# CONFIG_USB_ATI_REMOTE2 is not set
+# CONFIG_USB_KEYSPAN_REMOTE is not set
+# CONFIG_USB_APPLETOUCH is not set
+# CONFIG_USB_GTCO is not set
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET_MII=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_USB_MON is not set
+#
+# USB port drivers
+#
+#
+# USB Serial Converter support
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_AIRPRIME is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP2101 is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+CONFIG_USB_SERIAL_PL2303=m
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+#
+# USB DSL modem support
+#
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+#
+# MMC/SD Card support
+#
+CONFIG_MMC=m
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_BLOCK=m
+CONFIG_MMC_AT91=m
+#
+# Real Time Clock
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=m
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=m
+CONFIG_RTC_INTF_PROC=m
+CONFIG_RTC_INTF_DEV=m
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+#
+# RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+CONFIG_RTC_DRV_AT91RM9200=m
+# CONFIG_RTC_DRV_TEST is not set
+# CONFIG_RTC_DRV_V3020 is not set
+#
+# File systems
+#
+CONFIG_EXT2_FS=m
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=m
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=m
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=m
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+CONFIG_AMIGA_PARTITION=y
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+#
+# Native Language Support
+#
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="utf-8"
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_FORCED_INLINING is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_MANAGER=m
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_TEST=m
+#
+# Hardware crypto devices
+#
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+CONFIG_CRC32=y
+CONFIG_LIBCRC32C=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index bb28087bf818..593b56509f4f 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -7,8 +7,8 @@ AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET)
 # Object file lists.
 obj-y           := compat.o entry-armv.o entry-common.o irq.o \
-                   process.o ptrace.o semaphore.o setup.o signal.o sys_arm.o \
+                   process.o ptrace.o semaphore.o setup.o signal.o \
-                   time.o traps.o
+                   sys_arm.o stacktrace.o time.o traps.o
 obj-$(CONFIG_ISA_DMA_API)       += dma.o
 obj-$(CONFIG_ARCH_ACORN)        += ecard.o 
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index f1c0fb974177..bdbd7da99286 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -40,6 +40,7 @@
 #include <linux/device.h>
 #include <linux/init.h>
 #include <linux/mutex.h>
+#include <linux/kthread.h>
 #include <asm/dma.h>
 #include <asm/ecard.h>
@@ -50,6 +51,8 @@
 #include <asm/mach/irq.h>
 #include <asm/tlbflush.h>
+#include "ecard.h"
 #ifndef CONFIG_ARCH_RPC
 #define HAVE_EXPMASK
 #endif
@@ -123,7 +126,7 @@ static void ecard_task_reset(struct ecard_request *req)
        res = ec->slot_no == 8
                ? &ec->resource[ECARD_RES_MEMC]
-                : ec->type == ECARD_EASI
+                : ec->easi
                  ? &ec->resource[ECARD_RES_EASI]
                  : &ec->resource[ECARD_RES_IOCSYNC];
@@ -178,7 +181,7 @@ static void ecard_task_readbytes(struct ecard_request *req)
                        index += 1;
                }
        } else {
-                unsigned long base = (ec->type == ECARD_EASI
+                unsigned long base = (ec->easi
                         ? &ec->resource[ECARD_RES_EASI]
                         : &ec->resource[ECARD_RES_IOCSYNC])->start;
                void __iomem *pbase = (void __iomem *)base;
@@ -263,8 +266,6 @@ static int ecard_init_mm(void)
 static int
 ecard_task(void * unused)
 {
-        daemonize("kecardd");
        /*
         * Allocate a mm.  We're not a lazy-TLB kernel task since we need
         * to set page table entries where the user space would be.  Note
@@ -727,7 +728,7 @@ static int ecard_prints(char *buffer, ecard_t *ec)
        char *start = buffer;
        buffer += sprintf(buffer, "  %d: %s ", ec->slot_no,
-                          ec->type == ECARD_EASI ? "EASI" : "    ");
+                          ec->easi ? "EASI" : "    ");
        if (ec->cid.id == 0) {
                struct in_chunk_dir incd;
@@ -814,7 +815,7 @@ static struct expansion_card *__init ecard_alloc_card(int type, int slot)
        }
        ec->slot_no = slot;
-        ec->type = type;
+        ec->easi = type == ECARD_EASI;
        ec->irq = NO_IRQ;
        ec->fiq = NO_IRQ;
        ec->dma = NO_DMA;
@@ -825,6 +826,7 @@ static struct expansion_card *__init ecard_alloc_card(int type, int slot)
        ec->dev.bus = &ecard_bus_type;
        ec->dev.dma_mask = &ec->dma_mask;
        ec->dma_mask = (u64)0xffffffff;
+        ec->dev.coherent_dma_mask = ec->dma_mask;
        if (slot < 4) {
                ec_set_resource(ec, ECARD_RES_MEMC,
@@ -907,7 +909,7 @@ static ssize_t ecard_show_device(struct device *dev, struct device_attribute *at
 static ssize_t ecard_show_type(struct device *dev, struct device_attribute *attr, char *buf)
 {
        struct expansion_card *ec = ECARD_DEV(dev);
-        return sprintf(buf, "%s\n", ec->type == ECARD_EASI ? "EASI" : "IOC");
+        return sprintf(buf, "%s\n", ec->easi ? "EASI" : "IOC");
 }
 static struct device_attribute ecard_dev_attrs[] = {
@@ -1058,13 +1060,14 @@ ecard_probe(int slot, card_type_t type)
 */
 static int __init ecard_init(void)
 {
-        int slot, irqhw, ret;
+        struct task_struct *task;
+        int slot, irqhw;
-        ret = kernel_thread(ecard_task, NULL, CLONE_KERNEL);
-        if (ret < 0) {
+        task = kthread_run(ecard_task, NULL, "kecardd");
-                printk(KERN_ERR "Ecard: unable to create kernel thread: %d\n",
+        if (IS_ERR(task)) {
-                       ret);
+                printk(KERN_ERR "Ecard: unable to create kernel thread: %ld\n",
-                return ret;
+                       PTR_ERR(task));
+                return PTR_ERR(task);
        }
        printk("Probing expansion cards\n");
diff --git a/arch/arm/kernel/ecard.h b/arch/arm/kernel/ecard.h
new file mode 100644
index 000000000000..d7c2dacf935d
--- /dev/null
+++ b/arch/arm/kernel/ecard.h
@@ -0,0 +1,56 @@
+/*
+ *  ecard.h
+ *
+ *  Copyright 2007 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/* Definitions internal to ecard.c - for it's use only!!
+ *
+ * External expansion card header as read from the card
+ */
+struct ex_ecid {
+        unsigned char   r_irq:1;
+        unsigned char   r_zero:1;
+        unsigned char   r_fiq:1;
+        unsigned char   r_id:4;
+        unsigned char   r_a:1;
+        unsigned char   r_cd:1;
+        unsigned char   r_is:1;
+        unsigned char   r_w:2;
+        unsigned char   r_r1:4;
+        unsigned char   r_r2:8;
+        unsigned char   r_prod[2];
+        unsigned char   r_manu[2];
+        unsigned char   r_country;
+        unsigned char   r_fiqmask;
+        unsigned char   r_fiqoff[3];
+        unsigned char   r_irqmask;
+        unsigned char   r_irqoff[3];
+};
+/*
+ * Chunk directory entry as read from the card
+ */
+struct ex_chunk_dir {
+        unsigned char r_id;
+        unsigned char r_len[3];
+        unsigned long r_start;
+        union {
+                char string[256];
+                char data[1];
+        } d;
+#define c_id(x)         ((x)->r_id)
+#define c_len(x)        ((x)->r_len[0]|((x)->r_len[1]<<8)|((x)->r_len[2]<<16))
+#define c_start(x)      ((x)->r_start)
+};
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 0119c0d5f978..5d78ffb8a9a7 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -33,7 +33,7 @@
 * numbers for r1.
 *
 */
-        __INIT
+        .section ".text.head", "ax"
        .type   stext, %function
 ENTRY(stext)
        msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 66db0a9bf0bc..41f98b4ba2ee 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -73,7 +73,7 @@
 * crap here - that's what the boot loader (or in extreme, well justified
 * circumstances, zImage) is for.
 */
-        __INIT
+        .section ".text.head", "ax"
        .type   stext, %function
 ENTRY(stext)
        msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
@@ -257,7 +257,9 @@ __create_page_tables:
         * Map some ram to cover our .data and .bss areas.
         */
        orr     r3, r7, #(KERNEL_RAM_PADDR & 0xff000000)
+        .if     (KERNEL_RAM_PADDR & 0x00f00000)
        orr     r3, r3, #(KERNEL_RAM_PADDR & 0x00f00000)
+        .endif
        add     r0, r4,  #(KERNEL_RAM_VADDR & 0xff000000) >> 18
        str     r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]!
        ldr     r6, =(_end - 1)
@@ -274,7 +276,9 @@ __create_page_tables:
         */
        add     r0, r4, #PAGE_OFFSET >> 18
        orr     r6, r7, #(PHYS_OFFSET & 0xff000000)
-        orr     r6, r6, #(PHYS_OFFSET & 0x00e00000)
+        .if     (PHYS_OFFSET & 0x00f00000)
+        orr     r6, r6, #(PHYS_OFFSET & 0x00f00000)
+        .endif
        str     r6, [r0]
 #ifdef CONFIG_DEBUG_LL
diff --git a/arch/arm/kernel/init_task.c b/arch/arm/kernel/init_task.c
index a00cca0000bd..bd4ef53bc6b9 100644
--- a/arch/arm/kernel/init_task.c
+++ b/arch/arm/kernel/init_task.c
@@ -31,7 +31,7 @@ EXPORT_SYMBOL(init_mm);
 * The things we do for performance..
 */
 union thread_union init_thread_union
-        __attribute__((__section__(".init.task"))) =
+        __attribute__((__section__(".data.init_task"))) =
                { INIT_THREAD_INFO(init_task) };
 /*
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 1b061583408e..79b7e5cf5416 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -116,8 +116,8 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
                        offset += sym->st_value - loc;
                        if (offset & 3 ||
-                            offset <= (s32)0xfc000000 ||
+                            offset <= (s32)0xfe000000 ||
-                            offset >= (s32)0x04000000) {
+                            offset >= (s32)0x02000000) {
                                printk(KERN_ERR
                                       "%s: relocation out of range, section "
                                       "%d reloc %d sym '%s'\n", module->name,
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 8afd83d0cbdd..5d6e6523598b 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -27,6 +27,7 @@
 #include <linux/cpu.h>
 #include <linux/elfcore.h>
 #include <linux/pm.h>
+#include <linux/tick.h>
 #include <asm/leds.h>
 #include <asm/processor.h>
@@ -159,9 +160,11 @@ void cpu_idle(void)
                if (!idle)
                        idle = default_idle;
                leds_event(led_idle_start);
+                tick_nohz_stop_sched_tick();
                while (!need_resched())
                        idle();
                leds_event(led_idle_end);
+                tick_nohz_restart_sched_tick();
                preempt_enable_no_resched();
                schedule();
                preempt_disable();
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index e594b84cca83..13af4006a40f 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -779,8 +779,8 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                        break;
                case PTRACE_SET_SYSCALL:
+                        task_thread_info(child)->syscall = data;
                        ret = 0;
-                        child->ptrace_message = data;
                        break;
 #ifdef CONFIG_CRUNCH
@@ -817,7 +817,7 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
        ip = regs->ARM_ip;
        regs->ARM_ip = why;
-        current->ptrace_message = scno;
+        current_thread_info()->syscall = scno;
        /* the 0x80 provides a way for the tracing parent to distinguish
           between a syscall stop and SIGTRAP delivery */
@@ -834,5 +834,5 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
        }
        regs->ARM_ip = ip;
-        return current->ptrace_message;
+        return current_thread_info()->syscall;
 }
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 070bcb7a6306..1b76d87fa335 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -486,7 +486,7 @@ static void ipi_timer(void)
 }
 #ifdef CONFIG_LOCAL_TIMERS
-asmlinkage void do_local_timer(struct pt_regs *regs)
+asmlinkage void __exception do_local_timer(struct pt_regs *regs)
 {
        struct pt_regs *old_regs = set_irq_regs(regs);
        int cpu = smp_processor_id();
@@ -551,7 +551,7 @@ static void ipi_cpu_stop(unsigned int cpu)
 *
 *  Bit 0 - Inter-processor function call
 */
-asmlinkage void do_IPI(struct pt_regs *regs)
+asmlinkage void __exception do_IPI(struct pt_regs *regs)
 {
        unsigned int cpu = smp_processor_id();
        struct ipi_data *ipi = &per_cpu(ipi_data, cpu);
diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c
new file mode 100644
index 000000000000..77ef35efaa8d
--- /dev/null
+++ b/arch/arm/kernel/stacktrace.c
@@ -0,0 +1,73 @@
+#include <linux/sched.h>
+#include <linux/stacktrace.h>
+#include "stacktrace.h"
+int walk_stackframe(unsigned long fp, unsigned long low, unsigned long high,
+                    int (*fn)(struct stackframe *, void *), void *data)
+{
+        struct stackframe *frame;
+        do {
+                /*
+                 * Check current frame pointer is within bounds
+                 */
+                if ((fp - 12) < low || fp + 4 >= high)
+                        break;
+                frame = (struct stackframe *)(fp - 12);
+                if (fn(frame, data))
+                        break;
+                /*
+                 * Update the low bound - the next frame must always
+                 * be at a higher address than the current frame.
+                 */
+                low = fp + 4;
+                fp = frame->fp;
+        } while (fp);
+        return 0;
+}
+#ifdef CONFIG_STACKTRACE
+struct stack_trace_data {
+        struct stack_trace *trace;
+        unsigned int skip;
+};
+static int save_trace(struct stackframe *frame, void *d)
+{
+        struct stack_trace_data *data = d;
+        struct stack_trace *trace = data->trace;
+        if (data->skip) {
+                data->skip--;
+                return 0;
+        }
+        trace->entries[trace->nr_entries++] = frame->lr;
+        return trace->nr_entries >= trace->max_entries;
+}
+void save_stack_trace(struct stack_trace *trace, struct task_struct *task)
+{
+        struct stack_trace_data data;
+        unsigned long fp, base;
+        data.trace = trace;
+        data.skip = trace->skip;
+        if (task) {
+                base = (unsigned long)task_stack_page(task);
+                fp = 0; /* FIXME */
+        } else {
+                base = (unsigned long)task_stack_page(current);
+                asm("mov %0, fp" : "=r" (fp));
+        }
+        walk_stackframe(fp, base, base + THREAD_SIZE, save_trace, &data);
+}
+#endif
diff --git a/arch/arm/kernel/stacktrace.h b/arch/arm/kernel/stacktrace.h
new file mode 100644
index 000000000000..e9fd20cb5662
--- /dev/null
+++ b/arch/arm/kernel/stacktrace.h
@@ -0,0 +1,9 @@
+struct stackframe {
+        unsigned long fp;
+        unsigned long sp;
+        unsigned long lr;
+        unsigned long pc;
+};
+int walk_stackframe(unsigned long fp, unsigned long low, unsigned long high,
+                    int (*fn)(struct stackframe *, void *), void *data);
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index f61decb89ba2..d0540e4eaf5b 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -327,6 +327,7 @@ void restore_time_delta(struct timespec *delta, struct timespec *rtc)
 }
 EXPORT_SYMBOL(restore_time_delta);
+#ifndef CONFIG_GENERIC_CLOCKEVENTS
 /*
 * Kernel system timer support.
 */
@@ -340,8 +341,9 @@ void timer_tick(void)
        update_process_times(user_mode(get_irq_regs()));
 #endif
 }
+#endif
-#ifdef CONFIG_PM
+#if defined(CONFIG_PM) && !defined(CONFIG_GENERIC_CLOCKEVENTS)
 static int timer_suspend(struct sys_device *dev, pm_message_t state)
 {
        struct sys_timer *timer = container_of(dev, struct sys_timer, dev);
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 6055ab4b58d9..f05e66b0f868 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -286,6 +286,7 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
        struct undef_hook *hook;
        siginfo_t info;
        void __user *pc;
+        unsigned long flags;
        /*
         * According to the ARM ARM, PC is 2 or 4 bytes ahead,
@@ -304,7 +305,7 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
                get_user(instr, (u32 __user *)pc);
        }
-        spin_lock_irq(&undef_lock);
+        spin_lock_irqsave(&undef_lock, flags);
        list_for_each_entry(hook, &undef_hook, node) {
                if ((instr & hook->instr_mask) == hook->instr_val &&
                    (regs->ARM_cpsr & hook->cpsr_mask) == hook->cpsr_val) {
@@ -314,7 +315,7 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
                        }
                }
        }
-        spin_unlock_irq(&undef_lock);
+        spin_unlock_irqrestore(&undef_lock, flags);
 #ifdef CONFIG_DEBUG_USER
        if (user_debug & UDBG_UNDEFINED) {
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b295f6a85cf1..e4156e7868ce 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -23,11 +23,15 @@ SECTIONS
 #else
        . = PAGE_OFFSET + TEXT_OFFSET;
 #endif
-        .init : {                       /* Init code and data           */
+        .text.head : {
                _stext = .;
-                        _sinittext = .;
+                _sinittext = .;
+                *(.text.head)
+        }
+        .init : {                       /* Init code and data           */
                        *(.init.text)
-                        _einittext = .;
+                _einittext = .;
                __proc_info_begin = .;
                        *(.proc.info.init)
                __proc_info_end = .;
@@ -59,7 +63,7 @@ SECTIONS
                        usr/built-in.o(.init.ramfs)
                __initramfs_end = .;
 #endif
-                . = ALIGN(64);
+                . = ALIGN(4096);
                __per_cpu_start = .;
                        *(.data.percpu)
                __per_cpu_end = .;
@@ -119,7 +123,7 @@ SECTIONS
                 * first, the init task union, aligned
                 * to an 8192 byte boundary.
                 */
-                *(.init.task)
+                *(.data.init_task)
 #ifdef CONFIG_XIP_KERNEL
                . = ALIGN(4096);
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index bf0d96272e3a..e238ad8cfd8f 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -81,6 +81,13 @@ config MACH_KB9200
          Select this if you are using KwikByte's KB920x board.
          <http://kwikbyte.com/KB9202_description_new.htm>
+config MACH_PICOTUX2XX
+        bool "picotux 200"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using a picotux 200.
+          <http://www.picotux.com/>
 config MACH_KAFA
        bool "Sperry-Sun KAFA board"
        depends on ARCH_AT91RM9200
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 05de6cdc88f1..a412ae18a421 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_MACH_CARMEVA)	+= board-carmeva.o
 obj-$(CONFIG_MACH_KB9200)       += board-kb9202.o
 obj-$(CONFIG_MACH_ATEB9200)     += board-eb9200.o
 obj-$(CONFIG_MACH_KAFA)         += board-kafa.o
+obj-$(CONFIG_MACH_PICOTUX2XX)   += board-picotux200.o
 # AT91SAM9260 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 2ddcdd69df7d..2cad2bf864be 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -117,6 +117,21 @@ static struct clk pioD_clk = {
        .pmc_mask       = 1 << AT91RM9200_ID_PIOD,
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk ssc0_clk = {
+        .name           = "ssc0_clk",
+        .pmc_mask       = 1 << AT91RM9200_ID_SSC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc1_clk = {
+        .name           = "ssc1_clk",
+        .pmc_mask       = 1 << AT91RM9200_ID_SSC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc2_clk = {
+        .name           = "ssc2_clk",
+        .pmc_mask       = 1 << AT91RM9200_ID_SSC2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
 static struct clk tc0_clk = {
        .name           = "tc0_clk",
        .pmc_mask       = 1 << AT91RM9200_ID_TC0,
@@ -161,7 +176,9 @@ static struct clk *periph_clocks[] __initdata = {
        &udc_clk,
        &twi_clk,
        &spi_clk,
-        // ssc 0 .. ssc2
+        &ssc0_clk,
+        &ssc1_clk,
+        &ssc2_clk,
        &tc0_clk,
        &tc1_clk,
        &tc2_clk,
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 6ea41d8266cb..e47381e8aaba 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -119,6 +119,11 @@ static struct clk spi1_clk = {
        .pmc_mask       = 1 << AT91SAM9260_ID_SPI1,
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk ssc_clk = {
+        .name           = "ssc_clk",
+        .pmc_mask       = 1 << AT91SAM9260_ID_SSC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
 static struct clk tc0_clk = {
        .name           = "tc0_clk",
        .pmc_mask       = 1 << AT91SAM9260_ID_TC0,
@@ -193,7 +198,7 @@ static struct clk *periph_clocks[] __initdata = {
        &twi_clk,
        &spi0_clk,
        &spi1_clk,
-        // ssc
+        &ssc_clk,
        &tc0_clk,
        &tc1_clk,
        &tc2_clk,
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 784d1e682d6d..dfe8c39c9fb9 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -97,6 +97,21 @@ static struct clk spi1_clk = {
        .pmc_mask       = 1 << AT91SAM9261_ID_SPI1,
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk ssc0_clk = {
+        .name           = "ssc0_clk",
+        .pmc_mask       = 1 << AT91SAM9261_ID_SSC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc1_clk = {
+        .name           = "ssc1_clk",
+        .pmc_mask       = 1 << AT91SAM9261_ID_SSC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc2_clk = {
+        .name           = "ssc2_clk",
+        .pmc_mask       = 1 << AT91SAM9261_ID_SSC2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
 static struct clk tc0_clk = {
        .name           = "tc0_clk",
        .pmc_mask       = 1 << AT91SAM9261_ID_TC0,
@@ -135,7 +150,9 @@ static struct clk *periph_clocks[] __initdata = {
        &twi_clk,
        &spi0_clk,
        &spi1_clk,
-        // ssc 0 .. ssc2
+        &ssc0_clk,
+        &ssc1_clk,
+        &ssc2_clk,
        &tc0_clk,
        &tc1_clk,
        &tc2_clk,
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index e1504766fd64..8e781997716a 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -430,9 +430,9 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 *  LCD Controller
 * -------------------------------------------------------------------- */
-#if defined(CONFIG_FB_AT91) || defined(CONFIG_FB_AT91_MODULE)
+#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
 static u64 lcdc_dmamask = 0xffffffffUL;
-static struct at91fb_info lcdc_data;
+static struct atmel_lcdfb_info lcdc_data;
 static struct resource lcdc_resources[] = {
        [0] = {
@@ -455,7 +455,7 @@ static struct resource lcdc_resources[] = {
 };
 static struct platform_device at91_lcdc_device = {
-        .name           = "at91-fb",
+        .name           = "atmel_lcdfb",
        .id             = 0,
        .dev            = {
                                .dma_mask               = &lcdc_dmamask,
@@ -466,7 +466,7 @@ static struct platform_device at91_lcdc_device = {
        .num_resources  = ARRAY_SIZE(lcdc_resources),
 };
-void __init at91_add_device_lcdc(struct at91fb_info *data)
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
 {
        if (!data) {
                return;
@@ -499,7 +499,7 @@ void __init at91_add_device_lcdc(struct at91fb_info *data)
        platform_device_register(&at91_lcdc_device);
 }
 #else
-void __init at91_add_device_lcdc(struct at91fb_info *data) {}
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 #endif
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 0e89a7fca3fa..00e27b177857 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -87,6 +87,11 @@ static struct clk mmc1_clk = {
        .pmc_mask       = 1 << AT91SAM9263_ID_MCI1,
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk can_clk = {
+        .name           = "can_clk",
+        .pmc_mask       = 1 << AT91SAM9263_ID_CAN,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
 static struct clk twi_clk = {
        .name           = "twi_clk",
        .pmc_mask       = 1 << AT91SAM9263_ID_TWI,
@@ -102,16 +107,46 @@ static struct clk spi1_clk = {
        .pmc_mask       = 1 << AT91SAM9263_ID_SPI1,
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk ssc0_clk = {
+        .name           = "ssc0_clk",
+        .pmc_mask       = 1 << AT91SAM9263_ID_SSC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc1_clk = {
+        .name           = "ssc1_clk",
+        .pmc_mask       = 1 << AT91SAM9263_ID_SSC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ac97_clk = {
+        .name           = "ac97_clk",
+        .pmc_mask       = 1 << AT91SAM9263_ID_AC97C,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
 static struct clk tcb_clk = {
        .name           = "tcb_clk",
        .pmc_mask       = 1 << AT91SAM9263_ID_TCB,
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk pwmc_clk = {
+        .name           = "pwmc_clk",
+        .pmc_mask       = 1 << AT91SAM9263_ID_PWMC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
 static struct clk macb_clk = {
        .name           = "macb_clk",
        .pmc_mask       = 1 << AT91SAM9263_ID_EMAC,
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk dma_clk = {
+        .name           = "dma_clk",
+        .pmc_mask       = 1 << AT91SAM9263_ID_DMA,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twodge_clk = {
+        .name           = "2dge_clk",
+        .pmc_mask       = 1 << AT91SAM9263_ID_2DGE,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
 static struct clk udc_clk = {
        .name           = "udc_clk",
        .pmc_mask       = 1 << AT91SAM9263_ID_UDP,
@@ -142,20 +177,21 @@ static struct clk *periph_clocks[] __initdata = {
        &usart2_clk,
        &mmc0_clk,
        &mmc1_clk,
-        // can
+        &can_clk,
        &twi_clk,
        &spi0_clk,
        &spi1_clk,
-        // ssc0 .. ssc1
+        &ssc0_clk,
-        // ac97
+        &ssc1_clk,
+        &ac97_clk,
        &tcb_clk,
-        // pwmc
+        &pwmc_clk,
        &macb_clk,
-        // 2dge
+        &twodge_clk,
        &udc_clk,
        &isi_clk,
        &lcdc_clk,
-        // dma
+        &dma_clk,
        &ohci_clk,
        // irq0 .. irq1
 };
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index b77121f27f34..2b2e18a67128 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -573,6 +573,130 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 /* --------------------------------------------------------------------
+ *  AC97
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_SND_AT91_AC97) || defined(CONFIG_SND_AT91_AC97_MODULE)
+static u64 ac97_dmamask = 0xffffffffUL;
+static struct atmel_ac97_data ac97_data;
+static struct resource ac97_resources[] = {
+        [0] = {
+                .start  = AT91SAM9263_BASE_AC97C,
+                .end    = AT91SAM9263_BASE_AC97C + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9263_ID_AC97C,
+                .end    = AT91SAM9263_ID_AC97C,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91sam9263_ac97_device = {
+        .name           = "ac97c",
+        .id             = 1,
+        .dev            = {
+                                .dma_mask               = &ac97_dmamask,
+                                .coherent_dma_mask      = 0xffffffff,
+                                .platform_data          = &ac97_data,
+        },
+        .resource       = ac97_resources,
+        .num_resources  = ARRAY_SIZE(ac97_resources),
+};
+void __init at91_add_device_ac97(struct atmel_ac97_data *data)
+{
+        if (!data)
+                return;
+        at91_set_A_periph(AT91_PIN_PB0, 0);     /* AC97FS */
+        at91_set_A_periph(AT91_PIN_PB1, 0);     /* AC97CK */
+        at91_set_A_periph(AT91_PIN_PB2, 0);     /* AC97TX */
+        at91_set_A_periph(AT91_PIN_PB3, 0);     /* AC97RX */
+        /* reset */
+        if (data->reset_pin)
+                at91_set_gpio_output(data->reset_pin, 0);
+        ac97_data = *ek_data;
+        platform_device_register(&at91sam9263_ac97_device);
+}
+#else
+void __init at91_add_device_ac97(struct atmel_ac97_data *data) {}
+#endif
+/* --------------------------------------------------------------------
+ *  LCD Controller
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
+static u64 lcdc_dmamask = 0xffffffffUL;
+static struct atmel_lcdfb_info lcdc_data;
+static struct resource lcdc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9263_LCDC_BASE,
+                .end    = AT91SAM9263_LCDC_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9263_ID_LCDC,
+                .end    = AT91SAM9263_ID_LCDC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91_lcdc_device = {
+        .name           = "atmel_lcdfb",
+        .id             = 0,
+        .dev            = {
+                                .dma_mask               = &lcdc_dmamask,
+                                .coherent_dma_mask      = 0xffffffff,
+                                .platform_data          = &lcdc_data,
+        },
+        .resource       = lcdc_resources,
+        .num_resources  = ARRAY_SIZE(lcdc_resources),
+};
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
+{
+        if (!data)
+                return;
+        at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
+        at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
+        at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
+        at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
+        at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
+        at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
+        at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
+        at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
+        at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
+        at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
+        at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
+        at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
+        at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
+        at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD13 */
+        at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
+        at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
+        at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
+        at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
+        at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
+        at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD21 */
+        at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
+        at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
+        lcdc_data = *data;
+        platform_device_register(&at91_lcdc_device);
+}
+#else
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
+#endif
+/* --------------------------------------------------------------------
 *  LEDs
 * -------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
new file mode 100644
index 000000000000..49cfe7ab4a85
--- /dev/null
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -0,0 +1,166 @@
+/*
+ * linux/arch/arm/mach-at91/board-picotux200.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2007 Kleinhenz Elektronik GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/mtd/physmap.h>
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91rm9200_mc.h>
+#include "generic.h"
+/*
+ * Serial port configuration.
+ *    0 .. 3 = USART0 .. USART3
+ *    4      = DBGU
+ */
+static struct at91_uart_config __initdata picotux200_uart_config = {
+        .console_tty    = 0,                            /* ttyS0 */
+        .nr_tty         = 2,
+        .tty_map        = { 4, 1, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
+};
+static void __init picotux200_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91rm9200_initialize(18432000, AT91RM9200_BGA);
+        /* Setup the serial ports and console */
+        at91_init_serial(&picotux200_uart_config);
+}
+static void __init picotux200_init_irq(void)
+{
+        at91rm9200_init_interrupts(NULL);
+}
+static struct at91_eth_data __initdata picotux200_eth_data = {
+        .phy_irq_pin    = AT91_PIN_PC4,
+        .is_rmii        = 1,
+};
+static struct at91_usbh_data __initdata picotux200_usbh_data = {
+        .ports          = 1,
+};
+// static struct at91_udc_data __initdata picotux200_udc_data = {
+//      .vbus_pin       = AT91_PIN_PD4,
+//      .pullup_pin     = AT91_PIN_PD5,
+// };
+static struct at91_mmc_data __initdata picotux200_mmc_data = {
+        .det_pin        = AT91_PIN_PB27,
+        .slot_b         = 0,
+        .wire4          = 1,
+        .wp_pin         = AT91_PIN_PA17,
+};
+// static struct spi_board_info picotux200_spi_devices[] = {
+//      {       /* DataFlash chip */
+//              .modalias       = "mtd_dataflash",
+//              .chip_select    = 0,
+//              .max_speed_hz   = 15 * 1000 * 1000,
+//      },
+// #ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
+//      {       /* DataFlash card */
+//              .modalias       = "mtd_dataflash",
+//              .chip_select    = 3,
+//              .max_speed_hz   = 15 * 1000 * 1000,
+//      },
+// #endif
+// };
+#define PICOTUX200_FLASH_BASE   AT91_CHIPSELECT_0
+#define PICOTUX200_FLASH_SIZE   0x400000
+static struct physmap_flash_data picotux200_flash_data = {
+        .width  = 2,
+};
+static struct resource picotux200_flash_resource = {
+        .start          = PICOTUX200_FLASH_BASE,
+        .end            = PICOTUX200_FLASH_BASE + PICOTUX200_FLASH_SIZE - 1,
+        .flags          = IORESOURCE_MEM,
+};
+static struct platform_device picotux200_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                                .platform_data  = &picotux200_flash_data,
+                        },
+        .resource       = &picotux200_flash_resource,
+        .num_resources  = 1,
+};
+static void __init picotux200_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* Ethernet */
+        at91_add_device_eth(&picotux200_eth_data);
+        /* USB Host */
+        at91_add_device_usbh(&picotux200_usbh_data);
+        /* USB Device */
+        // at91_add_device_udc(&picotux200_udc_data);
+        // at91_set_multi_drive(picotux200_udc_data.pullup_pin, 1);     /* pullup_pin is connected to reset */
+        /* I2C */
+        at91_add_device_i2c();
+        /* SPI */
+        // at91_add_device_spi(picotux200_spi_devices, ARRAY_SIZE(picotux200_spi_devices));
+#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
+        /* DataFlash card */
+        at91_set_gpio_output(AT91_PIN_PB22, 0);
+#else
+        /* MMC */
+        at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
+        at91_add_device_mmc(0, &picotux200_mmc_data);
+#endif
+        /* NOR Flash */
+        platform_device_register(&picotux200_flash);
+}
+MACHINE_START(PICOTUX2XX, "picotux 200")
+        /* Maintainer: Kleinhenz Elektronik GmbH */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91rm9200_timer,
+        .map_io         = picotux200_map_io,
+        .init_irq       = picotux200_init_irq,
+        .init_machine   = picotux200_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 57fb4499d969..65fa532bb4ac 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -104,9 +104,9 @@ static struct spi_board_info ek_spi_devices[] = {
        },
 #endif
 #endif
-#if defined(CONFIG_SND_AT73C213)
+#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
        {       /* AT73C213 DAC */
-                .modalias       = "snd_at73c213",
+                .modalias       = "at73c213",
                .chip_select    = 0,
                .max_speed_hz   = 10 * 1000 * 1000,
                .bus_num        = 1,
@@ -118,7 +118,7 @@ static struct spi_board_info ek_spi_devices[] = {
 /*
 * MACB Ethernet device
 */
-static struct __initdata at91_eth_data ek_macb_data = {
+static struct at91_eth_data __initdata ek_macb_data = {
        .phy_irq_pin    = AT91_PIN_PA7,
        .is_rmii        = 1,
 };
@@ -140,7 +140,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
        },
 };
-static struct mtd_partition *nand_partitions(int size, int *num_partitions)
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
 {
        *num_partitions = ARRAY_SIZE(ek_nand_partition);
        return ek_nand_partition;
@@ -188,6 +188,8 @@ static void __init ek_board_init(void)
        at91_add_device_eth(&ek_macb_data);
        /* MMC */
        at91_add_device_mmc(0, &ek_mmc_data);
+        /* I2C */
+        at91_add_device_i2c();
 }
 MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index b7e772467cf6..bcf71536cc6d 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -25,6 +25,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
 #include <linux/dm9000.h>
 #include <asm/hardware.h>
@@ -195,6 +196,41 @@ static struct at91_nand_data __initdata ek_nand_data = {
 };
 /*
+ * ADS7846 Touchscreen
+ */
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+static int ads7843_pendown_state(void)
+{
+        return !at91_get_gpio_value(AT91_PIN_PC2);      /* Touchscreen PENIRQ */
+}
+static struct ads7846_platform_data ads_info = {
+        .model                  = 7843,
+        .x_min                  = 150,
+        .x_max                  = 3830,
+        .y_min                  = 190,
+        .y_max                  = 3830,
+        .vref_delay_usecs       = 100,
+        .x_plate_ohms           = 450,
+        .y_plate_ohms           = 250,
+        .pressure_max           = 15000,
+        .debounce_max           = 1,
+        .debounce_rep           = 0,
+        .debounce_tol           = (~0),
+        .get_pendown_state      = ads7843_pendown_state,
+};
+static void __init ek_add_device_ts(void)
+{
+        at91_set_B_periph(AT91_PIN_PC2, 1);     /* External IRQ0, with pullup */
+        at91_set_gpio_input(AT91_PIN_PA11, 1);  /* Touchscreen BUSY signal */
+}
+#else
+static void __init ek_add_device_ts(void) {}
+#endif
+/*
 * SPI devices
 */
 static struct spi_board_info ek_spi_devices[] = {
@@ -204,6 +240,16 @@ static struct spi_board_info ek_spi_devices[] = {
                .max_speed_hz   = 15 * 1000 * 1000,
                .bus_num        = 0,
        },
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+        {
+                .modalias       = "ads7846",
+                .chip_select    = 2,
+                .max_speed_hz   = 125000 * 26,  /* (max sample rate @ 3V) * (cmd + data + overhead) */
+                .bus_num        = 0,
+                .platform_data  = &ads_info,
+                .irq            = AT91SAM9261_ID_IRQ0,
+        },
+#endif
 #if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
        {       /* DataFlash card - jumper (J12) configurable to CS3 or CS0 */
                .modalias       = "mtd_dataflash",
@@ -211,9 +257,9 @@ static struct spi_board_info ek_spi_devices[] = {
                .max_speed_hz   = 15 * 1000 * 1000,
                .bus_num        = 0,
        },
-#elif defined(CONFIG_SND_AT73C213)
+#elif defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
        {       /* AT73C213 DAC */
-                .modalias       = "snd_at73c213",
+                .modalias       = "at73c213",
                .chip_select    = 3,
                .max_speed_hz   = 10 * 1000 * 1000,
                .bus_num        = 0,
@@ -241,6 +287,8 @@ static void __init ek_board_init(void)
 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
        /* SPI */
        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+        /* Touchscreen */
+        ek_add_device_ts();
 #else
        /* MMC */
        at91_add_device_mmc(0, &ek_mmc_data);
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 8fdce11a880c..f57458559fb6 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -25,6 +25,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
 #include <asm/hardware.h>
 #include <asm/setup.h>
@@ -86,6 +87,40 @@ static struct at91_udc_data __initdata ek_udc_data = {
 /*
+ * ADS7846 Touchscreen
+ */
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+static int ads7843_pendown_state(void)
+{
+        return !at91_get_gpio_value(AT91_PIN_PA15);     /* Touchscreen PENIRQ */
+}
+static struct ads7846_platform_data ads_info = {
+        .model                  = 7843,
+        .x_min                  = 150,
+        .x_max                  = 3830,
+        .y_min                  = 190,
+        .y_max                  = 3830,
+        .vref_delay_usecs       = 100,
+        .x_plate_ohms           = 450,
+        .y_plate_ohms           = 250,
+        .pressure_max           = 15000,
+        .debounce_max           = 1,
+        .debounce_rep           = 0,
+        .debounce_tol           = (~0),
+        .get_pendown_state      = ads7843_pendown_state,
+};
+static void __init ek_add_device_ts(void)
+{
+        at91_set_B_periph(AT91_PIN_PA15, 1);    /* External IRQ1, with pullup */
+        at91_set_gpio_input(AT91_PIN_PA31, 1);  /* Touchscreen BUSY signal */
+}
+#else
+static void __init ek_add_device_ts(void) {}
+#endif
+/*
 * SPI devices.
 */
 static struct spi_board_info ek_spi_devices[] = {
@@ -97,6 +132,16 @@ static struct spi_board_info ek_spi_devices[] = {
                .bus_num        = 0,
        },
 #endif
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+        {
+                .modalias       = "ads7846",
+                .chip_select    = 3,
+                .max_speed_hz   = 125000 * 26,  /* (max sample rate @ 3V) * (cmd + data + overhead) */
+                .bus_num        = 0,
+                .platform_data  = &ads_info,
+                .irq            = AT91SAM9263_ID_IRQ1,
+        },
+#endif
 };
@@ -112,6 +157,14 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
 /*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata ek_macb_data = {
+        .is_rmii        = 1,
+};
+/*
 * NAND flash
 */
 static struct mtd_partition __initdata ek_nand_partition[] = {
@@ -148,6 +201,14 @@ static struct at91_nand_data __initdata ek_nand_data = {
 };
+/*
+ * AC97
+ */
+static struct atmel_ac97_data ek_ac97_data = {
+        .reset_pin      = AT91_PIN_PA13,
+};
 static void __init ek_board_init(void)
 {
        /* Serial */
@@ -157,11 +218,20 @@ static void __init ek_board_init(void)
        /* USB Device */
        at91_add_device_udc(&ek_udc_data);
        /* SPI */
+        at91_set_gpio_output(AT91_PIN_PE20, 1);         /* select spi0 clock */
        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+        /* Touchscreen */
+        ek_add_device_ts();
        /* MMC */
        at91_add_device_mmc(1, &ek_mmc_data);
+        /* Ethernet */
+        at91_add_device_eth(&ek_macb_data);
        /* NAND */
        at91_add_device_nand(&ek_nand_data);
+        /* I2C */
+        at91_add_device_i2c();
+        /* AC97 */
+        at91_add_device_ac97(&ek_ac97_data);
 }
 MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index b49bfda53d7f..ff8db29e989e 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -201,7 +201,6 @@ error:
 static struct pm_ops at91_pm_ops ={
-        .pm_disk_mode   = 0,
        .valid          = at91_pm_valid_state,
        .prepare        = at91_pm_prepare,
        .enter          = at91_pm_enter,
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index f174d1a3b11c..9d7515c36bff 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -27,6 +27,10 @@ struct clk {
        u32             enable_mask;
 };
+static struct clk clk_uart = {
+        .name           = "UARTCLK",
+        .rate           = 14745600,
+};
 static struct clk clk_pll1 = {
        .name           = "pll1",
 };
@@ -50,6 +54,7 @@ static struct clk clk_usb_host = {
 static struct clk *clocks[] = {
+        &clk_uart,
        &clk_pll1,
        &clk_f,
        &clk_h,
diff --git a/arch/arm/mach-iop13xx/Makefile b/arch/arm/mach-iop13xx/Makefile
index 4185e0586c33..da1609dc0dee 100644
--- a/arch/arm/mach-iop13xx/Makefile
+++ b/arch/arm/mach-iop13xx/Makefile
@@ -7,5 +7,6 @@ obj-$(CONFIG_ARCH_IOP13XX) += setup.o
 obj-$(CONFIG_ARCH_IOP13XX) += irq.o
 obj-$(CONFIG_ARCH_IOP13XX) += pci.o
 obj-$(CONFIG_ARCH_IOP13XX) += io.o
+obj-$(CONFIG_ARCH_IOP13XX) += tpmi.o
 obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o
 obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index e79a1b62600f..5b22fdeca52c 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -41,7 +41,7 @@ void * __iomem __iop13xx_io(unsigned long io_addr)
 EXPORT_SYMBOL(__iop13xx_io);
 void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
-        unsigned long flags)
+        unsigned int mtype)
 {
        void __iomem * retval;
@@ -61,9 +61,9 @@ void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
                                 (cookie - IOP13XX_PCIE_LOWER_MEM_RA));
                break;
        case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
-                retval = __ioremap(IOP13XX_PBI_LOWER_MEM_PA +
+                retval = __arm_ioremap(IOP13XX_PBI_LOWER_MEM_PA +
-                                  (cookie - IOP13XX_PBI_LOWER_MEM_RA),
+                                       (cookie - IOP13XX_PBI_LOWER_MEM_RA),
-                                  size, flags);
+                                       size, mtype);
                break;
        case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
                retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
@@ -75,7 +75,7 @@ void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
                retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
                break;
        default:
-                retval = __ioremap(cookie, size, flags);
+                retval = __arm_ioremap(cookie, size, mtype);
        }
        return retval;
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index a519d707571c..268a8d84999c 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -75,11 +75,14 @@ static void __init iq81340mc_init(void)
 {
        iop13xx_platform_init();
        iq81340mc_pci_init();
+        iop13xx_add_tpmi_devices();
 }
 static void __init iq81340mc_timer_init(void)
 {
-        iop_init_time(400000000);
+        unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio();
+        printk(KERN_DEBUG "%s: bus frequency: %lu\n", __FUNCTION__, bus_freq);
+        iop_init_time(bus_freq);
 }
 static struct sys_timer iq81340mc_timer = {
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index 0e71fbcabe00..a51ffd2683e5 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -77,11 +77,14 @@ static void __init iq81340sc_init(void)
 {
        iop13xx_platform_init();
        iq81340sc_pci_init();
+        iop13xx_add_tpmi_devices();
 }
 static void __init iq81340sc_timer_init(void)
 {
-        iop_init_time(400000000);
+        unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio();
+        printk(KERN_DEBUG "%s: bus frequency: %lu\n", __FUNCTION__, bus_freq);
+        iop_init_time(bus_freq);
 }
 static struct sys_timer iq81340sc_timer = {
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 89ec70ea3187..d1d0d32ca77c 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -88,9 +88,9 @@ void iop13xx_map_pci_memory(void)
                                if (end) {
                                        iop13xx_atux_mem_base =
-                                        (u32) __ioremap_pfn(
+                                        (u32) __arm_ioremap_pfn(
                                        __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
-                                        , 0, iop13xx_atux_mem_size, 0);
+                                        , 0, iop13xx_atux_mem_size, MT_DEVICE);
                                        if (!iop13xx_atux_mem_base) {
                                                printk("%s: atux allocation "
                                                       "failed\n", __FUNCTION__);
@@ -114,9 +114,9 @@ void iop13xx_map_pci_memory(void)
                                if (end) {
                                        iop13xx_atue_mem_base =
-                                        (u32) __ioremap_pfn(
+                                        (u32) __arm_ioremap_pfn(
                                        __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
-                                        , 0, iop13xx_atue_mem_size, 0);
+                                        , 0, iop13xx_atue_mem_size, MT_DEVICE);
                                        if (!iop13xx_atue_mem_base) {
                                                printk("%s: atue allocation "
                                                       "failed\n", __FUNCTION__);
@@ -1023,7 +1023,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
                                  << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
                __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
-                res[0].start = IOP13XX_PCIX_LOWER_IO_PA;
+                res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET;
                res[0].end   = IOP13XX_PCIX_UPPER_IO_PA;
                res[0].name  = "IQ81340 ATUX PCI I/O Space";
                res[0].flags = IORESOURCE_IO;
@@ -1033,7 +1033,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
                res[1].name  = "IQ81340 ATUX PCI Memory Space";
                res[1].flags = IORESOURCE_MEM;
                sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
-                sys->io_offset = IOP13XX_PCIX_IO_OFFSET;
+                sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA;
                break;
        case IOP13XX_INIT_ATU_ATUE:
                /* Note: the function number field in the PCSR is ro */
@@ -1044,7 +1044,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
                __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
-                res[0].start = IOP13XX_PCIE_LOWER_IO_PA;
+                res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET;
                res[0].end   = IOP13XX_PCIE_UPPER_IO_PA;
                res[0].name  = "IQ81340 ATUE PCI I/O Space";
                res[0].flags = IORESOURCE_IO;
@@ -1054,7 +1054,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
                res[1].name  = "IQ81340 ATUE PCI Memory Space";
                res[1].flags = IORESOURCE_MEM;
                sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
-                sys->io_offset = IOP13XX_PCIE_IO_OFFSET;
+                sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA;
                sys->map_irq = iop13xx_pcie_map_irq;
                break;
        default:
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index 9a46bcd5f18e..bc4871553f6a 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -258,15 +258,11 @@ void __init iop13xx_platform_init(void)
        if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
                switch (iop13xx_dev_id()) {
-                /* enable both uarts on iop341 and iop342 */
+                /* enable both uarts on iop341 */
                case 0x3380:
                case 0x3384:
                case 0x3388:
                case 0x338c:
-                case 0x3382:
-                case 0x3386:
-                case 0x338a:
-                case 0x338e:
                        init_uart |= IOP13XX_INIT_UART_0;
                        init_uart |= IOP13XX_INIT_UART_1;
                        break;
diff --git a/arch/arm/mach-iop13xx/tpmi.c b/arch/arm/mach-iop13xx/tpmi.c
new file mode 100644
index 000000000000..d3dc278213da
--- /dev/null
+++ b/arch/arm/mach-iop13xx/tpmi.c
@@ -0,0 +1,234 @@
+/*
+ * iop13xx tpmi device resources
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/sizes.h>
+/* assumes CONTROLLER_ONLY# is never asserted in the ESSR register */
+#define IOP13XX_TPMI_MMR(dev)   IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12))
+#define IOP13XX_TPMI_MEM(dev)   IOP13XX_REG_ADDR32_PHYS(0x60000 + (dev << 13))
+#define IOP13XX_TPMI_CTRL(dev)  IOP13XX_REG_ADDR32_PHYS(0x50000 + (dev << 10))
+#define IOP13XX_TPMI_MMR_SIZE       (SZ_4K - 1)
+#define IOP13XX_TPMI_MEM_SIZE       (255)
+#define IOP13XX_TPMI_MEM_CTRL       (SZ_1K - 1)
+#define IOP13XX_TPMI_RESOURCE_MMR  0
+#define IOP13XX_TPMI_RESOURCE_MEM  1
+#define IOP13XX_TPMI_RESOURCE_CTRL 2
+#define IOP13XX_TPMI_RESOURCE_IRQ  3
+static struct resource iop13xx_tpmi_0_resources[] = {
+        [IOP13XX_TPMI_RESOURCE_MMR] = {
+                .start = IOP13XX_TPMI_MMR(4), /* tpmi0 starts at dev == 4 */
+                .end = IOP13XX_TPMI_MMR(4) + IOP13XX_TPMI_MMR_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_MEM] = {
+                .start = IOP13XX_TPMI_MEM(0),
+                .end = IOP13XX_TPMI_MEM(0) + IOP13XX_TPMI_MEM_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_CTRL] = {
+                .start = IOP13XX_TPMI_CTRL(0),
+                .end = IOP13XX_TPMI_CTRL(0) + IOP13XX_TPMI_MEM_CTRL,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_IRQ] = {
+                .start = IRQ_IOP13XX_TPMI0_OUT,
+                .end = IRQ_IOP13XX_TPMI0_OUT,
+                .flags = IORESOURCE_IRQ
+        }
+};
+static struct resource iop13xx_tpmi_1_resources[] = {
+        [IOP13XX_TPMI_RESOURCE_MMR] = {
+                .start = IOP13XX_TPMI_MMR(1),
+                .end = IOP13XX_TPMI_MMR(1) + IOP13XX_TPMI_MMR_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_MEM] = {
+                .start = IOP13XX_TPMI_MEM(1),
+                .end = IOP13XX_TPMI_MEM(1) + IOP13XX_TPMI_MEM_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_CTRL] = {
+                .start = IOP13XX_TPMI_CTRL(1),
+                .end = IOP13XX_TPMI_CTRL(1) + IOP13XX_TPMI_MEM_CTRL,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_IRQ] = {
+                .start = IRQ_IOP13XX_TPMI1_OUT,
+                .end = IRQ_IOP13XX_TPMI1_OUT,
+                .flags = IORESOURCE_IRQ
+        }
+};
+static struct resource iop13xx_tpmi_2_resources[] = {
+        [IOP13XX_TPMI_RESOURCE_MMR] = {
+                .start = IOP13XX_TPMI_MMR(2),
+                .end = IOP13XX_TPMI_MMR(2) + IOP13XX_TPMI_MMR_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_MEM] = {
+                .start = IOP13XX_TPMI_MEM(2),
+                .end = IOP13XX_TPMI_MEM(2) + IOP13XX_TPMI_MEM_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_CTRL] = {
+                .start = IOP13XX_TPMI_CTRL(2),
+                .end = IOP13XX_TPMI_CTRL(2) + IOP13XX_TPMI_MEM_CTRL,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_IRQ] = {
+                .start = IRQ_IOP13XX_TPMI2_OUT,
+                .end = IRQ_IOP13XX_TPMI2_OUT,
+                .flags = IORESOURCE_IRQ
+        }
+};
+static struct resource iop13xx_tpmi_3_resources[] = {
+        [IOP13XX_TPMI_RESOURCE_MMR] = {
+                .start = IOP13XX_TPMI_MMR(3),
+                .end = IOP13XX_TPMI_MMR(3) + IOP13XX_TPMI_MMR_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_MEM] = {
+                .start = IOP13XX_TPMI_MEM(3),
+                .end = IOP13XX_TPMI_MEM(3) + IOP13XX_TPMI_MEM_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_CTRL] = {
+                .start = IOP13XX_TPMI_CTRL(3),
+                .end = IOP13XX_TPMI_CTRL(3) + IOP13XX_TPMI_MEM_CTRL,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_IRQ] = {
+                .start = IRQ_IOP13XX_TPMI3_OUT,
+                .end = IRQ_IOP13XX_TPMI3_OUT,
+                .flags = IORESOURCE_IRQ
+        }
+};
+u64 iop13xx_tpmi_mask = DMA_64BIT_MASK;
+static struct platform_device iop13xx_tpmi_0_device = {
+        .name = "iop-tpmi",
+        .id = 0,
+        .num_resources = 4,
+        .resource = iop13xx_tpmi_0_resources,
+        .dev = {
+                .dma_mask          = &iop13xx_tpmi_mask,
+                .coherent_dma_mask = DMA_64BIT_MASK,
+        },
+};
+static struct platform_device iop13xx_tpmi_1_device = {
+        .name = "iop-tpmi",
+        .id = 1,
+        .num_resources = 4,
+        .resource = iop13xx_tpmi_1_resources,
+        .dev = {
+                .dma_mask          = &iop13xx_tpmi_mask,
+                .coherent_dma_mask = DMA_64BIT_MASK,
+        },
+};
+static struct platform_device iop13xx_tpmi_2_device = {
+        .name = "iop-tpmi",
+        .id = 2,
+        .num_resources = 4,
+        .resource = iop13xx_tpmi_2_resources,
+        .dev = {
+                .dma_mask          = &iop13xx_tpmi_mask,
+                .coherent_dma_mask = DMA_64BIT_MASK,
+        },
+};
+static struct platform_device iop13xx_tpmi_3_device = {
+        .name = "iop-tpmi",
+        .id = 3,
+        .num_resources = 4,
+        .resource = iop13xx_tpmi_3_resources,
+        .dev = {
+                .dma_mask          = &iop13xx_tpmi_mask,
+                .coherent_dma_mask = DMA_64BIT_MASK,
+        },
+};
+__init void iop13xx_add_tpmi_devices(void)
+{
+        unsigned short device_id;
+        /* tpmi's not present on iop341 or iop342 */
+        if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
+                /* ATUE must be present */
+                device_id = __raw_readw(IOP13XX_ATUE_DID);
+        else
+                /* ATUX must be present */
+                device_id = __raw_readw(IOP13XX_ATUX_DID);
+        switch (device_id) {
+        /* iop34[1|2] 0-tpmi */
+        case 0x3380:
+        case 0x3384:
+        case 0x3388:
+        case 0x338c:
+        case 0x3382:
+        case 0x3386:
+        case 0x338a:
+        case 0x338e:
+                return;
+        /* iop348 1-tpmi */
+        case 0x3310:
+        case 0x3312:
+        case 0x3314:
+        case 0x3318:
+        case 0x331a:
+        case 0x331c:
+        case 0x33c0:
+        case 0x33c2:
+        case 0x33c4:
+        case 0x33c8:
+        case 0x33ca:
+        case 0x33cc:
+        case 0x33b0:
+        case 0x33b2:
+        case 0x33b4:
+        case 0x33b8:
+        case 0x33ba:
+        case 0x33bc:
+        case 0x3320:
+        case 0x3322:
+        case 0x3324:
+        case 0x3328:
+        case 0x332a:
+        case 0x332c:
+                platform_device_register(&iop13xx_tpmi_0_device);
+                return;
+        default:
+                platform_device_register(&iop13xx_tpmi_0_device);
+                platform_device_register(&iop13xx_tpmi_1_device);
+                platform_device_register(&iop13xx_tpmi_2_device);
+                platform_device_register(&iop13xx_tpmi_3_device);
+                return;
+        }
+}
diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig
index 9dd49cff21ff..9bb02b6d7ae1 100644
--- a/arch/arm/mach-iop32x/Kconfig
+++ b/arch/arm/mach-iop32x/Kconfig
@@ -34,6 +34,14 @@ config MACH_N2100
          Say Y here if you want to run your kernel on the Thecus n2100
          NAS appliance.
+config IOP3XX_ATU
+        bool "Enable the PCI Controller"
+        default y
+        help
+          Say Y here if you want the IOP to initialize its PCI Controller.
+          Say N if the IOP is an add in card, the host system owns the PCI
+          bus in this case.
 endmenu
 endif
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 60e74309a458..7b21c6e13e59 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -178,9 +178,10 @@ static struct hw_pci iq31244_pci __initdata = {
 static int __init iq31244_pci_init(void)
 {
-        if (is_ep80219())
+        if (is_ep80219()) {
-                pci_common_init(&ep80219_pci);
+                if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE)
-        else if (machine_is_iq31244()) {
+                        pci_common_init(&ep80219_pci);
+        } else if (machine_is_iq31244()) {
                if (is_80219()) {
                        printk("note: iq31244 board type has been selected\n");
                        printk("note: to select ep80219 operation:\n");
@@ -189,7 +190,9 @@ static int __init iq31244_pci_init(void)
                        printk("\t2/ update boot loader to pass"
                                " the ep80219 id: %d\n", MACH_TYPE_EP80219);
                }
-                pci_common_init(&iq31244_pci);
+                if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE)
+                        pci_common_init(&iq31244_pci);
        }
        return 0;
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index 361c70c0f64c..bc25fb91e7b9 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -113,7 +113,8 @@ static struct hw_pci iq80321_pci __initdata = {
 static int __init iq80321_pci_init(void)
 {
-        if (machine_is_iq80321())
+        if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) &&
+                machine_is_iq80321())
                pci_common_init(&iq80321_pci);
        return 0;
diff --git a/arch/arm/mach-iop33x/Kconfig b/arch/arm/mach-iop33x/Kconfig
index 9aa016bb18f9..45598e096898 100644
--- a/arch/arm/mach-iop33x/Kconfig
+++ b/arch/arm/mach-iop33x/Kconfig
@@ -16,6 +16,14 @@ config MACH_IQ80332
          Say Y here if you want to run your kernel on the Intel IQ80332
          evaluation kit for the IOP332 chipset.
+config IOP3XX_ATU
+        bool "Enable the PCI Controller"
+        default y
+        help
+          Say Y here if you want the IOP to initialize its PCI Controller.
+          Say N if the IOP is an add in card, the host system owns the PCI
+          bus in this case.
 endmenu
 endif
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index 1a9e36138d80..376c932830be 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -96,7 +96,8 @@ static struct hw_pci iq80331_pci __initdata = {
 static int __init iq80331_pci_init(void)
 {
-        if (machine_is_iq80331())
+        if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) &&
+                machine_is_iq80331())
                pci_common_init(&iq80331_pci);
        return 0;
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 96d6f0f3cd21..58c81496c6f6 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -96,7 +96,8 @@ static struct hw_pci iq80332_pci __initdata = {
 static int __init iq80332_pci_init(void)
 {
-        if (machine_is_iq80332())
+        if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) &&
+                machine_is_iq80332())
                pci_common_init(&iq80332_pci);
        return 0;
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 27b7480f4afe..9cf2498dc99e 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -84,59 +84,59 @@ static struct map_desc ixp2000_io_desc[] __initdata = {
                .virtual        = IXP2000_CAP_VIRT_BASE,
                .pfn            = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
                .length         = IXP2000_CAP_SIZE,
-                .type           = MT_IXP2000_DEVICE,
+                .type           = MT_DEVICE_IXP2000,
        }, {
                .virtual        = IXP2000_INTCTL_VIRT_BASE,
                .pfn            = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
                .length         = IXP2000_INTCTL_SIZE,
-                .type           = MT_IXP2000_DEVICE,
+                .type           = MT_DEVICE_IXP2000,
        }, {
                .virtual        = IXP2000_PCI_CREG_VIRT_BASE,
                .pfn            = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
                .length         = IXP2000_PCI_CREG_SIZE,
-                .type           = MT_IXP2000_DEVICE,
+                .type           = MT_DEVICE_IXP2000,
        }, {
                .virtual        = IXP2000_PCI_CSR_VIRT_BASE,
                .pfn            = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
                .length         = IXP2000_PCI_CSR_SIZE,
-                .type           = MT_IXP2000_DEVICE,
+                .type           = MT_DEVICE_IXP2000,
        }, {
                .virtual        = IXP2000_MSF_VIRT_BASE,
                .pfn            = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
                .length         = IXP2000_MSF_SIZE,
-                .type           = MT_IXP2000_DEVICE,
+                .type           = MT_DEVICE_IXP2000,
        }, {
                .virtual        = IXP2000_SCRATCH_RING_VIRT_BASE,
                .pfn            = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
                .length         = IXP2000_SCRATCH_RING_SIZE,
-                .type           = MT_IXP2000_DEVICE,
+                .type           = MT_DEVICE_IXP2000,
        }, {
                .virtual        = IXP2000_SRAM0_VIRT_BASE,
                .pfn            = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
                .length         = IXP2000_SRAM0_SIZE,
-                .type           = MT_IXP2000_DEVICE,
+                .type           = MT_DEVICE_IXP2000,
        }, {
                .virtual        = IXP2000_PCI_IO_VIRT_BASE,
                .pfn            = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
                .length         = IXP2000_PCI_IO_SIZE,
-                .type           = MT_IXP2000_DEVICE,
+                .type           = MT_DEVICE_IXP2000,
        }, {
                .virtual        = IXP2000_PCI_CFG0_VIRT_BASE,
                .pfn            = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
                .length         = IXP2000_PCI_CFG0_SIZE,
-                .type           = MT_IXP2000_DEVICE,
+                .type           = MT_DEVICE_IXP2000,
        }, {
                .virtual        = IXP2000_PCI_CFG1_VIRT_BASE,
                .pfn            = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
                .length         = IXP2000_PCI_CFG1_SIZE,
-                .type           = MT_IXP2000_DEVICE,
+                .type           = MT_DEVICE_IXP2000,
        }
 };
 void __init ixp2000_map_io(void)
 {
        /*
-         * On IXP2400 CPUs we need to use MT_IXP2000_DEVICE so that
+         * On IXP2400 CPUs we need to use MT_DEVICE_IXP2000 so that
         * XCB=101 (to avoid triggering erratum #66), and given that
         * this mode speeds up I/O accesses and we have write buffer
         * flushes in the right places anyway, it doesn't hurt to use
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index ac29298c5d3f..500e997ba7a4 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -70,17 +70,17 @@ static struct map_desc enp2611_io_desc[] __initdata = {
                .virtual        = ENP2611_CALEB_VIRT_BASE,
                .pfn            = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE),
                .length         = ENP2611_CALEB_SIZE,
-                .type           = MT_IXP2000_DEVICE,
+                .type           = MT_DEVICE_IXP2000,
        }, {
                .virtual        = ENP2611_PM3386_0_VIRT_BASE,
                .pfn            = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE),
                .length         = ENP2611_PM3386_0_SIZE,
-                .type           = MT_IXP2000_DEVICE,
+                .type           = MT_DEVICE_IXP2000,
        }, {
                .virtual        = ENP2611_PM3386_1_VIRT_BASE,
                .pfn            = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE),
                .length         = ENP2611_PM3386_1_SIZE,
-                .type           = MT_IXP2000_DEVICE,
+                .type           = MT_DEVICE_IXP2000,
        }
 };
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 8a339cdfe222..9715ef506c24 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -62,6 +62,12 @@ config MACH_IXDP465
          IXDP465 Development Platform (Also known as BMP).
          For more information on this platform, see <file:Documentation/arm/IXP4xx>.
+config MACH_KIXRP435
+        bool "KIXRP435"
+        help
+          Say 'Y' here if you want your kernel to support Intel's
+          KIXRP435 Reference Platform.
+          For more information on this platform, see <file:Documentation/arm/IXP4xx>.
 #
 # IXCDP1100 is the exact same HW as IXDP425, but with a different machine 
@@ -89,12 +95,21 @@ config MACH_NAS100D
          NAS 100d device. For more information on this platform,
          see http://www.nslu2-linux.org/wiki/NAS100d/HomePage
+config MACH_DSMG600
+        bool
+        prompt "D-Link DSM-G600 RevA"
+        select PCI
+        help
+          Say 'Y' here if you want your kernel to support D-Link's
+          DSM-G600 RevA device. For more information on this platform,
+          see http://www.nslu2-linux.org/wiki/DSMG600/HomePage
 #
 # Avila and IXDP share the same source for now. Will change in future
 #
 config  ARCH_IXDP4XX
        bool
-        depends on ARCH_IXDP425 || MACH_IXDP465
+        depends on ARCH_IXDP425 || MACH_IXDP465 || MACH_KIXRP435
        default y
 #
@@ -105,6 +120,11 @@ config CPU_IXP46X
        depends on MACH_IXDP465
        default y
+config CPU_IXP43X
+        bool
+        depends on MACH_KIXRP435
+        default y
 config MACH_GTWX5715
        bool "Gemtek WX5715 (Linksys WRV54G)"
        depends on ARCH_IXP4XX
diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
index 746e297284ed..3b87c47e06cf 100644
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -12,6 +12,7 @@ obj-pci-$(CONFIG_ARCH_ADI_COYOTE)	+= coyote-pci.o
 obj-pci-$(CONFIG_MACH_GTWX5715)         += gtwx5715-pci.o
 obj-pci-$(CONFIG_MACH_NSLU2)            += nslu2-pci.o
 obj-pci-$(CONFIG_MACH_NAS100D)          += nas100d-pci.o
+obj-pci-$(CONFIG_MACH_DSMG600)          += dsmg600-pci.o
 obj-y   += common.o
@@ -22,5 +23,6 @@ obj-$(CONFIG_ARCH_ADI_COYOTE)	+= coyote-setup.o
 obj-$(CONFIG_MACH_GTWX5715)     += gtwx5715-setup.o
 obj-$(CONFIG_MACH_NSLU2)        += nslu2-setup.o nslu2-power.o
 obj-$(CONFIG_MACH_NAS100D)      += nas100d-setup.o nas100d-power.o
+obj-$(CONFIG_MACH_DSMG600)      += dsmg600-setup.o dsmg600-power.o
 obj-$(CONFIG_PCI)               += $(obj-pci-$(CONFIG_PCI)) common-pci.o
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 9562177b5fe1..bf04121d1a31 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -374,7 +374,7 @@ void __init ixp4xx_pci_preinit(void)
         * Determine which PCI read method to use.
         * Rev 0 IXP425 requires workaround.
         */
-        if (!(processor_id & 0xf) && !cpu_is_ixp46x()) {
+        if (!(processor_id & 0xf) && cpu_is_ixp42x()) {
                printk("PCI: IXP42x A0 silicon detected - "
                        "PCI Non-Prefetch Workaround Enabled\n");
                ixp4xx_pci_read = ixp4xx_pci_read_errata;
@@ -480,7 +480,7 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
        res[0].flags = IORESOURCE_IO;
        res[1].name = "PCI Memory Space";
-        res[1].start = 0x48000000;
+        res[1].start = PCIBIOS_MIN_MEM;
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
        res[1].end = 0x4bffffff;
 #else
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 45068c3d8dcc..f5cae1e46b7e 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -27,6 +27,7 @@
 #include <linux/time.h>
 #include <linux/timex.h>
 #include <linux/clocksource.h>
+#include <linux/clockchips.h>
 #include <asm/arch/udc.h>
 #include <asm/hardware.h>
@@ -41,6 +42,8 @@
 #include <asm/mach/time.h>
 static int __init ixp4xx_clocksource_init(void);
+static int __init ixp4xx_clockevent_init(void);
+static struct clock_event_device clockevent_ixp4xx;
 /*************************************************************************
 * IXP4xx chipset I/O mapping
@@ -102,6 +105,29 @@ static signed char irq2gpio[32] = {
         7,  8,  9, 10, 11, 12, -1, -1,
 };
+int gpio_to_irq(int gpio)
+{
+        int irq;
+        for (irq = 0; irq < 32; irq++) {
+                if (irq2gpio[irq] == gpio)
+                        return irq;
+        }
+        return -EINVAL;
+}
+EXPORT_SYMBOL(gpio_to_irq);
+int irq_to_gpio(int irq)
+{
+        int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
+        if (gpio == -1)
+                return -EINVAL;
+        return gpio;
+}
+EXPORT_SYMBOL(irq_to_gpio);
 static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
 {
        int line = irq2gpio[irq];
@@ -169,7 +195,7 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
 static void ixp4xx_irq_mask(unsigned int irq)
 {
-        if (cpu_is_ixp46x() && irq >= 32)
+        if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
                *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
        else
                *IXP4XX_ICMR &= ~(1 << irq);
@@ -192,7 +218,7 @@ static void ixp4xx_irq_unmask(unsigned int irq)
        if (!(ixp4xx_irq_edge & (1 << irq)))
                ixp4xx_irq_ack(irq);
-        if (cpu_is_ixp46x() && irq >= 32)
+        if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
                *IXP4XX_ICMR2 |= (1 << (irq - 32));
        else
                *IXP4XX_ICMR |= (1 << irq);
@@ -216,7 +242,7 @@ void __init ixp4xx_init_irq(void)
        /* Disable all interrupt */
        *IXP4XX_ICMR = 0x0; 
-        if (cpu_is_ixp46x()) {
+        if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
                /* Route upper 32 sources to IRQ instead of FIQ */
                *IXP4XX_ICLR2 = 0x00;
@@ -239,52 +265,40 @@ void __init ixp4xx_init_irq(void)
 * counter as a source of real clock ticks to account for missed jiffies.
 *************************************************************************/
-static unsigned volatile last_jiffy_time;
-#define CLOCK_TICKS_PER_USEC    ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
 {
-        write_seqlock(&xtime_lock);
+        struct clock_event_device *evt = &clockevent_ixp4xx;
        /* Clear Pending Interrupt by writing '1' to it */
        *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
-        /*
+        evt->event_handler(evt);
-         * Catch up with the real idea of time
-         */
-        while ((signed long)(*IXP4XX_OSTS - last_jiffy_time) >= LATCH) {
-                timer_tick();
-                last_jiffy_time += LATCH;
-        }
-        write_sequnlock(&xtime_lock);
        return IRQ_HANDLED;
 }
 static struct irqaction ixp4xx_timer_irq = {
-        .name           = "IXP4xx Timer Tick",
+        .name           = "timer1",
        .flags          = IRQF_DISABLED | IRQF_TIMER,
        .handler        = ixp4xx_timer_interrupt,
 };
 static void __init ixp4xx_timer_init(void)
 {
+        /* Reset/disable counter */
+        *IXP4XX_OSRT1 = 0;
        /* Clear Pending Interrupt by writing '1' to it */
        *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
-        /* Setup the Timer counter value */
-        *IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
        /* Reset time-stamp counter */
        *IXP4XX_OSTS = 0;
-        last_jiffy_time = 0;
        /* Connect the interrupt handler and enable the interrupt */
        setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
        ixp4xx_clocksource_init();
+        ixp4xx_clockevent_init();
 }
 struct sys_timer ixp4xx_timer = {
@@ -384,6 +398,9 @@ void __init ixp4xx_sys_init(void)
                        ixp4xx_exp_bus_size >> 20);
 }
+/*
+ * clocksource
+ */
 cycle_t ixp4xx_get_cycles(void)
 {
        return *IXP4XX_OSTS;
@@ -408,3 +425,64 @@ static int __init ixp4xx_clocksource_init(void)
        return 0;
 }
+/*
+ * clockevents
+ */
+static int ixp4xx_set_next_event(unsigned long evt,
+                                 struct clock_event_device *unused)
+{
+        unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
+        *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
+        return 0;
+}
+static void ixp4xx_set_mode(enum clock_event_mode mode,
+                            struct clock_event_device *evt)
+{
+        unsigned long opts, osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
+                opts = IXP4XX_OST_ENABLE;
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* period set by 'set next_event' */
+                osrt = 0;
+                opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
+                break;
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+        default:
+                osrt = opts = 0;
+                break;
+        }
+        *IXP4XX_OSRT1 = osrt | opts;
+}
+static struct clock_event_device clockevent_ixp4xx = {
+        .name           = "ixp4xx timer1",
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .rating         = 200,
+        .shift          = 24,
+        .set_mode       = ixp4xx_set_mode,
+        .set_next_event = ixp4xx_set_next_event,
+};
+static int __init ixp4xx_clockevent_init(void)
+{
+        clockevent_ixp4xx.mult = div_sc(FREQ, NSEC_PER_SEC,
+                                        clockevent_ixp4xx.shift);
+        clockevent_ixp4xx.max_delta_ns =
+                clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
+        clockevent_ixp4xx.min_delta_ns =
+                clockevent_delta2ns(0xf, &clockevent_ixp4xx);
+        clockevent_ixp4xx.cpumask = cpumask_of_cpu(0);
+        clockevents_register_device(&clockevent_ixp4xx);
+        return 0;
+}
diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c
new file mode 100644
index 000000000000..9db7e1f42011
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c
@@ -0,0 +1,74 @@
+/*
+ * DSM-G600 board-level PCI initialization
+ *
+ * Copyright (C) 2006 Tower Technologies
+ * Author: Alessandro Zummo <a.zummo@towertech.it>
+ *
+ * based on ixdp425-pci.c:
+ *      Copyright (C) 2002 Intel Corporation.
+ *      Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * Maintainer: http://www.nslu2-linux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <asm/mach/pci.h>
+#include <asm/mach-types.h>
+void __init dsmg600_pci_preinit(void)
+{
+        set_irq_type(IRQ_DSMG600_PCI_INTA, IRQT_LOW);
+        set_irq_type(IRQ_DSMG600_PCI_INTB, IRQT_LOW);
+        set_irq_type(IRQ_DSMG600_PCI_INTC, IRQT_LOW);
+        set_irq_type(IRQ_DSMG600_PCI_INTD, IRQT_LOW);
+        set_irq_type(IRQ_DSMG600_PCI_INTE, IRQT_LOW);
+        set_irq_type(IRQ_DSMG600_PCI_INTF, IRQT_LOW);
+        ixp4xx_pci_preinit();
+}
+static int __init dsmg600_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        static int pci_irq_table[DSMG600_PCI_MAX_DEV][DSMG600_PCI_IRQ_LINES] =
+        {
+                { IRQ_DSMG600_PCI_INTE, -1, -1 },
+                { IRQ_DSMG600_PCI_INTA, -1, -1 },
+                { IRQ_DSMG600_PCI_INTB, IRQ_DSMG600_PCI_INTC, IRQ_DSMG600_PCI_INTD },
+                { IRQ_DSMG600_PCI_INTF, -1, -1 },
+        };
+        int irq = -1;
+        if (slot >= 1 && slot <= DSMG600_PCI_MAX_DEV &&
+                pin >= 1 && pin <= DSMG600_PCI_IRQ_LINES)
+                irq = pci_irq_table[slot-1][pin-1];
+        return irq;
+}
+struct hw_pci __initdata dsmg600_pci = {
+        .nr_controllers = 1,
+        .preinit        = dsmg600_pci_preinit,
+        .swizzle        = pci_std_swizzle,
+        .setup          = ixp4xx_setup,
+        .scan           = ixp4xx_scan_bus,
+        .map_irq        = dsmg600_map_irq,
+};
+int __init dsmg600_pci_init(void)
+{
+        if (machine_is_dsmg600())
+                pci_common_init(&dsmg600_pci);
+        return 0;
+}
+subsys_initcall(dsmg600_pci_init);
diff --git a/arch/arm/mach-ixp4xx/dsmg600-power.c b/arch/arm/mach-ixp4xx/dsmg600-power.c
new file mode 100644
index 000000000000..34717872d076
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/dsmg600-power.c
@@ -0,0 +1,125 @@
+/*
+ * arch/arm/mach-ixp4xx/dsmg600-power.c
+ *
+ * DSM-G600 Power/Reset driver
+ * Author: Michael Westerhof <mwester@dls.net>
+ *
+ * Based on nslu2-power.c
+ *  Copyright (C) 2005 Tower Technologies
+ *  Author: Alessandro Zummo <a.zummo@towertech.it>
+ *
+ * which was based on nslu2-io.c
+ *  Copyright (C) 2004 Karen Spearel
+ *
+ * Maintainers: http://www.nslu2-linux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/module.h>
+#include <linux/reboot.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/jiffies.h>
+#include <linux/timer.h>
+#include <asm/mach-types.h>
+extern void ctrl_alt_del(void);
+/* This is used to make sure the power-button pusher is serious.  The button
+ * must be held until the value of this counter reaches zero.
+ */
+static volatile int power_button_countdown;
+/* Must hold the button down for at least this many counts to be processed */
+#define PBUTTON_HOLDDOWN_COUNT 4 /* 2 secs */
+static void dsmg600_power_handler(unsigned long data);
+static DEFINE_TIMER(dsmg600_power_timer, dsmg600_power_handler, 0, 0);
+static void dsmg600_power_handler(unsigned long data)
+{
+        /* This routine is called twice per second to check the
+         * state of the power button.
+         */
+        if (*IXP4XX_GPIO_GPINR & DSMG600_PB_BM) {
+                /* IO Pin is 1 (button pushed) */
+                if (power_button_countdown == 0) {
+                        /* Signal init to do the ctrlaltdel action, this will bypass
+                         * init if it hasn't started and do a kernel_restart.
+                         */
+                        ctrl_alt_del();
+                        /* Change the state of the power LED to "blink" */
+                        gpio_line_set(DSMG600_LED_PWR_GPIO, IXP4XX_GPIO_LOW);
+                }
+                power_button_countdown--;
+        } else {
+                power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
+        }
+        mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500));
+}
+static irqreturn_t dsmg600_reset_handler(int irq, void *dev_id)
+{
+        /* This is the paper-clip reset, it shuts the machine down directly. */
+        machine_power_off();
+        return IRQ_HANDLED;
+}
+static int __init dsmg600_power_init(void)
+{
+        if (!(machine_is_dsmg600()))
+                return 0;
+        if (request_irq(DSMG600_RB_IRQ, &dsmg600_reset_handler,
+                IRQF_DISABLED | IRQF_TRIGGER_LOW, "DSM-G600 reset button",
+                NULL) < 0) {
+                printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
+                        DSMG600_RB_IRQ);
+                return -EIO;
+        }
+        /* The power button on the D-Link DSM-G600 is on GPIO 15, but
+         * it cannot handle interrupts on that GPIO line.  So we'll
+         * have to poll it with a kernel timer.
+         */
+        /* Make sure that the power button GPIO is set up as an input */
+        gpio_line_config(DSMG600_PB_GPIO, IXP4XX_GPIO_IN);
+        /* Set the initial value for the power button IRQ handler */
+        power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
+        mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500));
+        return 0;
+}
+static void __exit dsmg600_power_exit(void)
+{
+        if (!(machine_is_dsmg600()))
+                return;
+        del_timer_sync(&dsmg600_power_timer);
+        free_irq(DSMG600_RB_IRQ, NULL);
+}
+module_init(dsmg600_power_init);
+module_exit(dsmg600_power_exit);
+MODULE_AUTHOR("Michael Westerhof <mwester@dls.net>");
+MODULE_DESCRIPTION("DSM-G600 Power/Reset driver");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
new file mode 100644
index 000000000000..1caff65e22cc
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -0,0 +1,175 @@
+/*
+ * DSM-G600 board-setup
+ *
+ * Copyright (C) 2006 Tower Technologies
+ * Author: Alessandro Zummo <a.zummo@towertech.it>
+ *
+ * based ixdp425-setup.c:
+ *      Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * Author: Alessandro Zummo <a.zummo@towertech.it>
+ * Maintainers: http://www.nslu2-linux.org/
+ */
+#include <linux/kernel.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+static struct flash_platform_data dsmg600_flash_data = {
+        .map_name               = "cfi_probe",
+        .width                  = 2,
+};
+static struct resource dsmg600_flash_resource = {
+        .flags                  = IORESOURCE_MEM,
+};
+static struct platform_device dsmg600_flash = {
+        .name                   = "IXP4XX-Flash",
+        .id                     = 0,
+        .dev.platform_data      = &dsmg600_flash_data,
+        .num_resources          = 1,
+        .resource               = &dsmg600_flash_resource,
+};
+static struct ixp4xx_i2c_pins dsmg600_i2c_gpio_pins = {
+        .sda_pin                = DSMG600_SDA_PIN,
+        .scl_pin                = DSMG600_SCL_PIN,
+};
+static struct platform_device dsmg600_i2c_controller = {
+        .name                   = "IXP4XX-I2C",
+        .id                     = 0,
+        .dev.platform_data      = &dsmg600_i2c_gpio_pins,
+};
+#ifdef CONFIG_LEDS_CLASS
+static struct resource dsmg600_led_resources[] = {
+        {
+                .name           = "power",
+                .start          = DSMG600_LED_PWR_GPIO,
+                .end            = DSMG600_LED_PWR_GPIO,
+                .flags          = IXP4XX_GPIO_HIGH,
+        },
+        {
+                .name           = "wlan",
+                .start          = DSMG600_LED_WLAN_GPIO,
+                .end            = DSMG600_LED_WLAN_GPIO,
+                .flags          = IXP4XX_GPIO_LOW,
+        },
+};
+static struct platform_device dsmg600_leds = {
+        .name                   = "IXP4XX-GPIO-LED",
+        .id                     = -1,
+        .num_resources          = ARRAY_SIZE(dsmg600_led_resources),
+        .resource               = dsmg600_led_resources,
+};
+#endif
+static struct resource dsmg600_uart_resources[] = {
+        {
+                .start          = IXP4XX_UART1_BASE_PHYS,
+                .end            = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = IXP4XX_UART2_BASE_PHYS,
+                .end            = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+                .flags          = IORESOURCE_MEM,
+        }
+};
+static struct plat_serial8250_port dsmg600_uart_data[] = {
+        {
+                .mapbase        = IXP4XX_UART1_BASE_PHYS,
+                .membase        = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+                .irq            = IRQ_IXP4XX_UART1,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = IXP4XX_UART_XTAL,
+        },
+        {
+                .mapbase        = IXP4XX_UART2_BASE_PHYS,
+                .membase        = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+                .irq            = IRQ_IXP4XX_UART2,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = IXP4XX_UART_XTAL,
+        },
+        { }
+};
+static struct platform_device dsmg600_uart = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev.platform_data      = dsmg600_uart_data,
+        .num_resources          = ARRAY_SIZE(dsmg600_uart_resources),
+        .resource               = dsmg600_uart_resources,
+};
+static struct platform_device *dsmg600_devices[] __initdata = {
+        &dsmg600_i2c_controller,
+        &dsmg600_flash,
+};
+static void dsmg600_power_off(void)
+{
+        /* enable the pwr cntl gpio */
+        gpio_line_config(DSMG600_PO_GPIO, IXP4XX_GPIO_OUT);
+        /* poweroff */
+        gpio_line_set(DSMG600_PO_GPIO, IXP4XX_GPIO_HIGH);
+}
+static void __init dsmg600_init(void)
+{
+        ixp4xx_sys_init();
+        /* Make sure that GPIO14 and GPIO15 are not used as clocks */
+        *IXP4XX_GPIO_GPCLKR = 0;
+        dsmg600_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+        dsmg600_flash_resource.end =
+                IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+        pm_power_off = dsmg600_power_off;
+        /* The UART is required on the DSM-G600 (Redboot cannot use the
+         * NIC) -- do it here so that it does *not* get removed if
+         * platform_add_devices fails!
+         */
+        (void)platform_device_register(&dsmg600_uart);
+        platform_add_devices(dsmg600_devices, ARRAY_SIZE(dsmg600_devices));
+#ifdef CONFIG_LEDS_CLASS
+        /* We don't care whether or not this works. */
+        (void)platform_device_register(&dsmg600_leds);
+#endif
+}
+static void __init dsmg600_fixup(struct machine_desc *desc,
+                struct tag *tags, char **cmdline, struct meminfo *mi)
+{
+       /* The xtal on this machine is non-standard. */
+        ixp4xx_timer_freq = DSMG600_FREQ;
+}
+MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
+        /* Maintainer: www.nslu2-linux.org */
+        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
+        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .fixup          = dsmg600_fixup,
+        .map_io         = ixp4xx_map_io,
+        .init_irq       = ixp4xx_init_irq,
+        .timer          = &ixp4xx_timer,
+        .init_machine   = dsmg600_init,
+MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c
index 99c1dc8033c8..408796004812 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
@@ -66,7 +66,7 @@ struct hw_pci ixdp425_pci __initdata = {
 int __init ixdp425_pci_init(void)
 {
        if (machine_is_ixdp425() || machine_is_ixcdp1100() ||
-                        machine_is_ixdp465())
+                        machine_is_ixdp465() || machine_is_kixrp435())
                pci_common_init(&ixdp425_pci);
        return 0;
 }
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index 04b1d56396a0..ec4f07950ec6 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -115,6 +115,11 @@ static void __init ixdp425_init(void)
        ixdp425_flash_resource.end =
                IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+        if (cpu_is_ixp43x()) {
+                ixdp425_uart.num_resources = 1;
+                ixdp425_uart_data[1].flags = 0;
+        }
        platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
 }
@@ -156,3 +161,16 @@ MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
        .init_machine   = ixdp425_init,
 MACHINE_END
 #endif
+#ifdef CONFIG_MACH_KIXRP435
+MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
+        /* Maintainer: MontaVista Software, Inc. */
+        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
+        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
+        .map_io         = ixp4xx_map_io,
+        .init_irq       = ixp4xx_init_irq,
+        .timer          = &ixp4xx_timer,
+        .boot_params    = 0x0100,
+        .init_machine   = ixdp425_init,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-ns9xxx/Kconfig b/arch/arm/mach-ns9xxx/Kconfig
index 8175ba92a2fa..8584ed107991 100644
--- a/arch/arm/mach-ns9xxx/Kconfig
+++ b/arch/arm/mach-ns9xxx/Kconfig
@@ -3,19 +3,30 @@ if ARCH_NS9XXX
 menu "NS9xxx Implementations"
 config MACH_CC9P9360DEV
-        bool "Connect Core 9P 9360 on an A9M9750 Devboard"
+        bool "ConnectCore 9P 9360 on an A9M9750 Devboard"
        select PROCESSOR_NS9360
        select BOARD_A9M9750DEV
        help
-          Say Y here if you are using the Digi Connect Core 9P 9360
+          Say Y here if you are using the Digi ConnectCore 9P 9360
          on an A9M9750 Development Board.
+config MACH_CC9P9360JS
+        bool "ConnectCore 9P 9360 on a JSCC9P9360 Devboard"
+        select PROCESSOR_NS9360
+        select BOARD_JSCC9P9360
+        help
+          Say Y here if you are using the Digi ConnectCore 9P 9360
+          on an JSCC9P9360 Development Board.
 config PROCESSOR_NS9360
        bool
 config BOARD_A9M9750DEV
        bool
+config BOARD_JSCC9P9360
+        bool
 endmenu
 endif
diff --git a/arch/arm/mach-ns9xxx/Makefile b/arch/arm/mach-ns9xxx/Makefile
index 91e945f5e16d..53213a69f601 100644
--- a/arch/arm/mach-ns9xxx/Makefile
+++ b/arch/arm/mach-ns9xxx/Makefile
@@ -3,3 +3,4 @@ obj-y := irq.o time.o generic.o
 obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o
 obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o
+obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o
diff --git a/arch/arm/mach-ns9xxx/board-jscc9p9360.c b/arch/arm/mach-ns9xxx/board-jscc9p9360.c
new file mode 100644
index 000000000000..4bd3eec04bfe
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/board-jscc9p9360.c
@@ -0,0 +1,17 @@
+/*
+ * arch/arm/mach-ns9xxx/board-jscc9p9360.c
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include "board-jscc9p9360.h"
+void __init board_jscc9p9360_init_machine(void)
+{
+        /* TODO: reserve GPIOs for push buttons, etc pp */
+}
diff --git a/arch/arm/mach-ns9xxx/board-jscc9p9360.h b/arch/arm/mach-ns9xxx/board-jscc9p9360.h
new file mode 100644
index 000000000000..1a81a074df45
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/board-jscc9p9360.h
@@ -0,0 +1,13 @@
+/*
+ * arch/arm/mach-ns9xxx/board-jscc9p9360.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/init.h>
+void __init board_jscc9p9360_init_machine(void);
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
new file mode 100644
index 000000000000..d09d5fa5620a
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/mach-ns9xxx/mach-cc9p9360js.c
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include "board-jscc9p9360.h"
+#include "generic.h"
+static void __init mach_cc9p9360js_init_machine(void)
+{
+        ns9xxx_init_machine();
+        board_jscc9p9360_init_machine();
+}
+MACHINE_START(CC9P9360DEV, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard")
+        .map_io = ns9xxx_map_io,
+        .init_irq = ns9xxx_init_irq,
+        .init_machine = mach_cc9p9360js_init_machine,
+        .timer = &ns9xxx_timer,
+        .boot_params = 0x100,
+MACHINE_END
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 49efe903dacd..6f4ea4bda5e0 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -72,12 +72,12 @@ static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
 static unsigned short enable_dyn_sleep = 1;
-static ssize_t omap_pm_sleep_while_idle_show(struct subsystem * subsys, char *buf)
+static ssize_t omap_pm_sleep_while_idle_show(struct kset *kset, char *buf)
 {
        return sprintf(buf, "%hu\n", enable_dyn_sleep);
 }
-static ssize_t omap_pm_sleep_while_idle_store(struct subsystem * subsys,
+static ssize_t omap_pm_sleep_while_idle_store(struct kset *kset,
                                              const char * buf,
                                              size_t n)
 {
@@ -100,7 +100,7 @@ static struct subsys_attribute sleep_while_idle_attr = {
        .store  = omap_pm_sleep_while_idle_store,
 };
-extern struct subsystem power_subsys;
+extern struct kset power_subsys;
 static void (*omap_sram_idle)(void) = NULL;
 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
@@ -698,10 +698,10 @@ static struct irqaction omap_wakeup_irq = {
 static struct pm_ops omap_pm_ops ={
-        .pm_disk_mode   = 0,
        .prepare        = omap_pm_prepare,
        .enter          = omap_pm_enter,
        .finish         = omap_pm_finish,
+        .valid          = pm_valid_only_mem,
 };
 static int __init omap_pm_init(void)
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 1b7e4a506c26..85e048b259f5 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -39,6 +39,10 @@
 #include <linux/interrupt.h>
 #include <linux/sched.h>
 #include <linux/spinlock.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 #include <asm/system.h>
 #include <asm/hardware.h>
@@ -48,13 +52,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
-struct sys_timer omap_timer;
-/*
- * ---------------------------------------------------------------------------
- * MPU timer
- * ---------------------------------------------------------------------------
- */
 #define OMAP_MPU_TIMER_BASE             OMAP_MPU_TIMER1_BASE
 #define OMAP_MPU_TIMER_OFFSET           0x100
@@ -88,21 +86,6 @@ static inline unsigned long long cycles_2_ns(unsigned long long cyc)
        return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
 }
-/*
- * MPU_TICKS_PER_SEC must be an even number, otherwise machinecycles_to_usecs
- * will break. On P2, the timer count rate is 6.5 MHz after programming PTV
- * with 0. This divides the 13MHz input by 2, and is undocumented.
- */
-#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
-/* REVISIT: This ifdef construct should be replaced by a query to clock
- * framework to see if timer base frequency is 12.0, 13.0 or 19.2 MHz.
- */
-#define MPU_TICKS_PER_SEC               (13000000 / 2)
-#else
-#define MPU_TICKS_PER_SEC               (12000000 / 2)
-#endif
-#define MPU_TIMER_TICK_PERIOD           ((MPU_TICKS_PER_SEC / HZ) - 1)
 typedef struct {
        u32 cntl;                       /* CNTL_TIMER, R/W */
@@ -120,98 +103,164 @@ static inline unsigned long omap_mpu_timer_read(int nr)
        return timer->read_tim;
 }
-static inline void omap_mpu_timer_start(int nr, unsigned long load_val)
+static inline void omap_mpu_set_autoreset(int nr)
 {
        volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
-        timer->cntl = MPU_TIMER_CLOCK_ENABLE;
+        timer->cntl = timer->cntl | MPU_TIMER_AR;
-        udelay(1);
-        timer->load_tim = load_val;
-        udelay(1);
-        timer->cntl = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_AR | MPU_TIMER_ST);
 }
-unsigned long omap_mpu_timer_ticks_to_usecs(unsigned long nr_ticks)
+static inline void omap_mpu_remove_autoreset(int nr)
 {
-        unsigned long long nsec;
+        volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
-        nsec = cycles_2_ns((unsigned long long)nr_ticks);
+        timer->cntl = timer->cntl & ~MPU_TIMER_AR;
-        return (unsigned long)nsec / 1000;
 }
-/*
+static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
- * Last processed system timer interrupt
+                                        int autoreset)
- */
+{
-static unsigned long omap_mpu_timer_last = 0;
+        volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
+        unsigned int timerflags = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST);
+        if (autoreset) timerflags |= MPU_TIMER_AR;
+        timer->cntl = MPU_TIMER_CLOCK_ENABLE;
+        udelay(1);
+        timer->load_tim = load_val;
+        udelay(1);
+        timer->cntl = timerflags;
+}
 /*
- * Returns elapsed usecs since last system timer interrupt
+ * ---------------------------------------------------------------------------
+ * MPU timer 1 ... count down to zero, interrupt, reload
+ * ---------------------------------------------------------------------------
 */
-static unsigned long omap_mpu_timer_gettimeoffset(void)
+static int omap_mpu_set_next_event(unsigned long cycles,
+                                    struct clock_event_device *evt)
 {
-        unsigned long now = 0 - omap_mpu_timer_read(0);
+        omap_mpu_timer_start(0, cycles, 0);
-        unsigned long elapsed = now - omap_mpu_timer_last;
+        return 0;
+}
-        return omap_mpu_timer_ticks_to_usecs(elapsed);
+static void omap_mpu_set_mode(enum clock_event_mode mode,
+                              struct clock_event_device *evt)
+{
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                omap_mpu_set_autoreset(0);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                omap_mpu_remove_autoreset(0);
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                break;
+        }
 }
-/*
+static struct clock_event_device clockevent_mpu_timer1 = {
- * Elapsed time between interrupts is calculated using timer0.
+        .name           = "mpu_timer1",
- * Latency during the interrupt is calculated using timer1.
+        .features       = CLOCK_EVT_FEAT_PERIODIC, CLOCK_EVT_FEAT_ONESHOT,
- * Both timer0 and timer1 are counting at 6MHz (P2 6.5MHz).
+        .shift          = 32,
- */
+        .set_next_event = omap_mpu_set_next_event,
-static irqreturn_t omap_mpu_timer_interrupt(int irq, void *dev_id)
+        .set_mode       = omap_mpu_set_mode,
+};
+static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
 {
-        unsigned long now, latency;
+        struct clock_event_device *evt = &clockevent_mpu_timer1;
-        write_seqlock(&xtime_lock);
+        evt->event_handler(evt);
-        now = 0 - omap_mpu_timer_read(0);
-        latency = MPU_TICKS_PER_SEC / HZ - omap_mpu_timer_read(1);
-        omap_mpu_timer_last = now - latency;
-        timer_tick();
-        write_sequnlock(&xtime_lock);
        return IRQ_HANDLED;
 }
-static struct irqaction omap_mpu_timer_irq = {
+static struct irqaction omap_mpu_timer1_irq = {
-        .name           = "mpu timer",
+        .name           = "mpu_timer1",
        .flags          = IRQF_DISABLED | IRQF_TIMER,
-        .handler        = omap_mpu_timer_interrupt,
+        .handler        = omap_mpu_timer1_interrupt,
 };
-static unsigned long omap_mpu_timer1_overflows;
+static __init void omap_init_mpu_timer(unsigned long rate)
-static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
+{
+        set_cyc2ns_scale(rate / 1000);
+        setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
+        omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
+        clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC,
+                                            clockevent_mpu_timer1.shift);
+        clockevent_mpu_timer1.max_delta_ns =
+                clockevent_delta2ns(-1, &clockevent_mpu_timer1);
+        clockevent_mpu_timer1.min_delta_ns =
+                clockevent_delta2ns(1, &clockevent_mpu_timer1);
+        clockevent_mpu_timer1.cpumask = cpumask_of_cpu(0);
+        clockevents_register_device(&clockevent_mpu_timer1);
+}
+/*
+ * ---------------------------------------------------------------------------
+ * MPU timer 2 ... free running 32-bit clock source and scheduler clock
+ * ---------------------------------------------------------------------------
+ */
+static unsigned long omap_mpu_timer2_overflows;
+static irqreturn_t omap_mpu_timer2_interrupt(int irq, void *dev_id)
 {
-        omap_mpu_timer1_overflows++;
+        omap_mpu_timer2_overflows++;
        return IRQ_HANDLED;
 }
-static struct irqaction omap_mpu_timer1_irq = {
+static struct irqaction omap_mpu_timer2_irq = {
-        .name           = "mpu timer1 overflow",
+        .name           = "mpu_timer2",
        .flags          = IRQF_DISABLED,
-        .handler        = omap_mpu_timer1_interrupt,
+        .handler        = omap_mpu_timer2_interrupt,
 };
-static __init void omap_init_mpu_timer(void)
+static cycle_t mpu_read(void)
 {
-        set_cyc2ns_scale(MPU_TICKS_PER_SEC / 1000);
+        return ~omap_mpu_timer_read(1);
-        omap_timer.offset = omap_mpu_timer_gettimeoffset;
+}
-        setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
-        setup_irq(INT_TIMER2, &omap_mpu_timer_irq);
+static struct clocksource clocksource_mpu = {
-        omap_mpu_timer_start(0, 0xffffffff);
+        .name           = "mpu_timer2",
-        omap_mpu_timer_start(1, MPU_TIMER_TICK_PERIOD);
+        .rating         = 300,
+        .read           = mpu_read,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .shift          = 24,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+static void __init omap_init_clocksource(unsigned long rate)
+{
+        static char err[] __initdata = KERN_ERR
+                        "%s: can't register clocksource!\n";
+        clocksource_mpu.mult
+                = clocksource_khz2mult(rate/1000, clocksource_mpu.shift);
+        setup_irq(INT_TIMER2, &omap_mpu_timer2_irq);
+        omap_mpu_timer_start(1, ~0, 1);
+        if (clocksource_register(&clocksource_mpu))
+                printk(err, clocksource_mpu.name);
 }
 /*
 * Scheduler clock - returns current time in nanosec units.
 */
 unsigned long long sched_clock(void)
 {
-        unsigned long ticks = 0 - omap_mpu_timer_read(0);
+        unsigned long ticks = 0 - omap_mpu_timer_read(1);
        unsigned long long ticks64;
-        ticks64 = omap_mpu_timer1_overflows;
+        ticks64 = omap_mpu_timer2_overflows;
        ticks64 <<= 32;
        ticks64 |= ticks;
@@ -225,10 +274,21 @@ unsigned long long sched_clock(void)
 */
 static void __init omap_timer_init(void)
 {
-        omap_init_mpu_timer();
+        struct clk      *ck_ref = clk_get(NULL, "ck_ref");
+        unsigned long   rate;
+        BUG_ON(IS_ERR(ck_ref));
+        rate = clk_get_rate(ck_ref);
+        clk_put(ck_ref);
+        /* PTV = 0 */
+        rate /= 2;
+        omap_init_mpu_timer(rate);
+        omap_init_clocksource(rate);
 }
 struct sys_timer omap_timer = {
        .init           = omap_timer_init,
-        .offset         = NULL,         /* Initialized later */
 };
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index d7eee99b7e3f..6f4a5436d0ce 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -370,10 +370,10 @@ static int omap2_pm_finish(suspend_state_t state)
 }
 static struct pm_ops omap_pm_ops = {
-        .pm_disk_mode   = 0,
        .prepare        = omap2_pm_prepare,
        .enter          = omap2_pm_enter,
        .finish         = omap2_pm_finish,
+        .valid          = pm_valid_only_mem,
 };
 int __init omap2_pm_init(void)
diff --git a/arch/arm/mach-pnx4008/pm.c b/arch/arm/mach-pnx4008/pm.c
index 3649cd3dfc9a..2a137f33f752 100644
--- a/arch/arm/mach-pnx4008/pm.c
+++ b/arch/arm/mach-pnx4008/pm.c
@@ -107,50 +107,19 @@ static int pnx4008_pm_enter(suspend_state_t state)
        case PM_SUSPEND_MEM:
                pnx4008_suspend();
                break;
-        case PM_SUSPEND_DISK:
-                return -ENOTSUPP;
-        default:
-                return -EINVAL;
        }
        return 0;
 }
-/*
+static int pnx4008_pm_valid(suspend_state_t state)
- * Called after processes are frozen, but before we shut down devices.
- */
-static int pnx4008_pm_prepare(suspend_state_t state)
-{
-        switch (state) {
-        case PM_SUSPEND_STANDBY:
-        case PM_SUSPEND_MEM:
-                break;
-        case PM_SUSPEND_DISK:
-                return -ENOTSUPP;
-                break;
-        default:
-                return -EINVAL;
-                break;
-        }
-        return 0;
-}
-/*
- * Called after devices are re-setup, but before processes are thawed.
- */
-static int pnx4008_pm_finish(suspend_state_t state)
 {
-        return 0;
+        return (state == PM_SUSPEND_STANDBY) ||
+               (state == PM_SUSPEND_MEM);
 }
-/*
- * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
- */
 static struct pm_ops pnx4008_pm_ops = {
-        .prepare = pnx4008_pm_prepare,
        .enter = pnx4008_pm_enter,
-        .finish = pnx4008_pm_finish,
+        .valid = pnx4008_pm_valid,
 };
 static int __init pnx4008_pm_init(void)
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index b8cb79f899d5..64b08b744f9f 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -164,9 +164,9 @@ void pxa_set_cken(int clock, int enable)
        local_irq_save(flags);
        if (enable)
-                CKEN |= clock;
+                CKEN |= (1 << clock);
        else
-                CKEN &= ~clock;
+                CKEN &= ~(1 << clock);
        local_irq_restore(flags);
 }
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 9f7499b6d435..4619d5fe606c 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -38,11 +38,33 @@ static void pxa_unmask_low_irq(unsigned int irq)
        ICMR |= (1 << (irq + PXA_IRQ_SKIP));
 }
+static int pxa_set_wake(unsigned int irq, unsigned int on)
+{
+        u32     mask;
+        switch (irq) {
+        case IRQ_RTCAlrm:
+                mask = PWER_RTC;
+                break;
+#ifdef CONFIG_PXA27x
+        /* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */
+#endif
+        default:
+                return -EINVAL;
+        }
+        if (on)
+                PWER |= mask;
+        else
+                PWER &= ~mask;
+        return 0;
+}
 static struct irq_chip pxa_internal_chip_low = {
        .name           = "SC",
        .ack            = pxa_mask_low_irq,
        .mask           = pxa_mask_low_irq,
        .unmask         = pxa_unmask_low_irq,
+        .set_wake       = pxa_set_wake,
 };
 #if PXA_INTERNAL_IRQS > 32
@@ -70,6 +92,26 @@ static struct irq_chip pxa_internal_chip_high = {
 #endif
+/* Note that if an input/irq line ever gets changed to an output during
+ * suspend, the relevant PWER, PRER, and PFER bits should be cleared.
+ */
+#ifdef CONFIG_PXA27x
+/* PXA27x:  Various gpios can issue wakeup events.  This logic only
+ * handles the simple cases, not the WEMUX2 and WEMUX3 options
+ */
+#define PXA27x_GPIO_NOWAKE_MASK \
+        ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
+#define WAKEMASK(gpio) \
+        (((gpio) <= 15) \
+                ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
+                : ((gpio == 35) ? (1 << 24) : 0))
+#else
+/* pxa 210, 250, 255, 26x:  gpios 0..15 can issue wakeups */
+#define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0)
+#endif
 /*
 * PXA GPIO edge detection for IRQs:
 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
@@ -83,9 +125,11 @@ static long GPIO_IRQ_mask[4];
 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
 {
        int gpio, idx;
+        u32 mask;
        gpio = IRQ_TO_GPIO(irq);
        idx = gpio >> 5;
+        mask = WAKEMASK(gpio);
        if (type == IRQT_PROBE) {
            /* Don't mess with enabled GPIOs using preconfigured edges or
@@ -105,14 +149,20 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
        if (type & __IRQT_RISEDGE) {
                /* printk("rising "); */
                __set_bit (gpio, GPIO_IRQ_rising_edge);
-        } else
+                PRER |= mask;
+        } else {
                __clear_bit (gpio, GPIO_IRQ_rising_edge);
+                PRER &= ~mask;
+        }
        if (type & __IRQT_FALEDGE) {
                /* printk("falling "); */
                __set_bit (gpio, GPIO_IRQ_falling_edge);
-        } else
+                PFER |= mask;
+        } else {
                __clear_bit (gpio, GPIO_IRQ_falling_edge);
+                PFER &= ~mask;
+        }
        /* printk("edges\n"); */
@@ -130,12 +180,29 @@ static void pxa_ack_low_gpio(unsigned int irq)
        GEDR0 = (1 << (irq - IRQ_GPIO0));
 }
+static int pxa_set_gpio_wake(unsigned int irq, unsigned int on)
+{
+        int     gpio = IRQ_TO_GPIO(irq);
+        u32     mask = WAKEMASK(gpio);
+        if (!mask)
+                return -EINVAL;
+        if (on)
+                PWER |= mask;
+        else
+                PWER &= ~mask;
+        return 0;
+}
 static struct irq_chip pxa_low_gpio_chip = {
        .name           = "GPIO-l",
        .ack            = pxa_ack_low_gpio,
        .mask           = pxa_mask_low_irq,
        .unmask         = pxa_unmask_low_irq,
        .set_type       = pxa_gpio_irq_type,
+        .set_wake       = pxa_set_gpio_wake,
 };
 /*
@@ -244,6 +311,7 @@ static struct irq_chip pxa_muxed_gpio_chip = {
        .mask           = pxa_mask_muxed_gpio,
        .unmask         = pxa_unmask_muxed_gpio,
        .set_type       = pxa_gpio_irq_type,
+        .set_wake       = pxa_set_gpio_wake,
 };
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 8e27a64fa9f4..e3097664ffe1 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -234,7 +234,7 @@ static void lpd270_backlight_power(int on)
 {
        if (on) {
                pxa_gpio_mode(GPIO16_PWM0_MD);
-                pxa_set_cken(CKEN0_PWM0, 1);
+                pxa_set_cken(CKEN_PWM0, 1);
                PWM_CTRL0 = 0;
                PWM_PWDUTY0 = 0x3ff;
                PWM_PERVAL0 = 0x3ff;
@@ -242,7 +242,7 @@ static void lpd270_backlight_power(int on)
                PWM_CTRL0 = 0;
                PWM_PWDUTY0 = 0x0;
                PWM_PERVAL0 = 0x3FF;
-                pxa_set_cken(CKEN0_PWM0, 0);
+                pxa_set_cken(CKEN_PWM0, 0);
        }
 }
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 055de7f4f00a..6377b2e29ff0 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -220,7 +220,7 @@ static struct resource pxa_ssp_resources[] = {
 static struct pxa2xx_spi_master pxa_ssp_master_info = {
        .ssp_type       = PXA25x_SSP,
-        .clock_enable   = CKEN3_SSP,
+        .clock_enable   = CKEN_SSP,
        .num_chipselect = 0,
 };
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 56d94d88d5ca..ed99a81b98f3 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -266,7 +266,7 @@ static void mainstone_backlight_power(int on)
 {
        if (on) {
                pxa_gpio_mode(GPIO16_PWM0_MD);
-                pxa_set_cken(CKEN0_PWM0, 1);
+                pxa_set_cken(CKEN_PWM0, 1);
                PWM_CTRL0 = 0;
                PWM_PWDUTY0 = 0x3ff;
                PWM_PERVAL0 = 0x3ff;
@@ -274,7 +274,7 @@ static void mainstone_backlight_power(int on)
                PWM_CTRL0 = 0;
                PWM_PWDUTY0 = 0x0;
                PWM_PERVAL0 = 0x3FF;
-                pxa_set_cken(CKEN0_PWM0, 0);
+                pxa_set_cken(CKEN_PWM0, 0);
        }
 }
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index b4d8276d6050..6bf15ae73848 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -223,14 +223,11 @@ int pxa_pm_finish(suspend_state_t state)
 EXPORT_SYMBOL_GPL(pxa_pm_finish);
-/*
- * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
- */
 static struct pm_ops pxa_pm_ops = {
-        .pm_disk_mode   = PM_DISK_FIRMWARE,
        .prepare        = pxa_pm_prepare,
        .enter          = pxa_pm_enter,
        .finish         = pxa_pm_finish,
+        .valid          = pm_valid_only_mem,
 };
 static int __init pxa_pm_init(void)
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 74eeada1e2fc..c64bab49efc4 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -140,9 +140,9 @@ void pxa_cpu_pm_enter(suspend_state_t state)
        extern void pxa_cpu_resume(void);
        if (state == PM_SUSPEND_STANDBY)
-                CKEN = CKEN22_MEMC | CKEN9_OSTIMER | CKEN16_LCD |CKEN0_PWM0;
+                CKEN = CKEN_MEMC | CKEN_OSTIMER | CKEN_LCD | CKEN_PWM0;
        else
-                CKEN = CKEN22_MEMC | CKEN9_OSTIMER;
+                CKEN = CKEN_MEMC | CKEN_OSTIMER;
        /* ensure voltage-change sequencer not initiated, which hangs */
        PCFR &= ~PCFR_FVC;
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c
index 6cc202755fb4..71766ac0328b 100644
--- a/arch/arm/mach-pxa/ssp.c
+++ b/arch/arm/mach-pxa/ssp.c
@@ -52,13 +52,13 @@ struct ssp_info_ {
 */
 static const struct ssp_info_ ssp_info[PXA_SSP_PORTS] = {
 #if defined (CONFIG_PXA27x)
-        {IRQ_SSP,       CKEN23_SSP1},
+        {IRQ_SSP,       CKEN_SSP1},
-        {IRQ_SSP2,      CKEN3_SSP2},
+        {IRQ_SSP2,      CKEN_SSP2},
-        {IRQ_SSP3,      CKEN4_SSP3},
+        {IRQ_SSP3,      CKEN_SSP3},
 #else
-        {IRQ_SSP,       CKEN3_SSP},
+        {IRQ_SSP,       CKEN_SSP},
-        {IRQ_NSSP,      CKEN9_NSSP},
+        {IRQ_NSSP,      CKEN_NSSP},
-        {IRQ_ASSP,      CKEN10_ASSP},
+        {IRQ_ASSP,      CKEN_ASSP},
 #endif
 };
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index 208a2b5dba1b..570cf937e73b 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -17,6 +17,7 @@
 #include <linux/sched.h>
 #include <linux/device.h>
 #include <linux/serial_8250.h>
+#include <linux/pata_platform.h>
 #include <asm/elf.h>
 #include <asm/io.h>
@@ -159,11 +160,45 @@ static struct platform_device serial_device = {
        },
 };
+static struct pata_platform_info pata_platform_data = {
+        .ioport_shift           = 2,
+};
+static struct resource pata_resources[] = {
+        [0] = {
+                .start          = 0x030107c0,
+                .end            = 0x030107df,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = 0x03010fd8,
+                .end            = 0x03010fdb,
+                .flags          = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start          = IRQ_HARDDISK,
+                .end            = IRQ_HARDDISK,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device pata_device = {
+        .name                   = "pata_platform",
+        .id                     = -1,
+        .num_resources          = ARRAY_SIZE(pata_resources),
+        .resource               = pata_resources,
+        .dev                    = {
+                .platform_data  = &pata_platform_data,
+                .coherent_dma_mask = ~0,        /* grumble */
+        },
+};
 static struct platform_device *devs[] __initdata = {
        &iomd_device,
        &kbd_device,
        &serial_device,
        &acornfb_device,
+        &pata_device,
 };
 static int __init rpc_init(void)
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 72f2cc4fcd03..bc308ceb91c3 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -160,17 +160,11 @@ static struct platform_device *amlm5900_devices[] __initdata = {
 #endif
 };
-static struct s3c24xx_board amlm5900_board __initdata = {
-        .devices       = amlm5900_devices,
-        .devices_count = ARRAY_SIZE(amlm5900_devices)
-};
 void __init amlm5900_map_io(void)
 {
        s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
-        s3c24xx_set_board(&amlm5900_board);
 }
 #ifdef CONFIG_FB_S3C2410
@@ -247,6 +241,7 @@ static void __init amlm5900_init(void)
 #ifdef CONFIG_FB_S3C2410
        s3c24xx_fb_set_platdata(&amlm5900_lcd_info);
 #endif
+        platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices));
 }
 MACHINE_START(AML_M5900, "AML_M5900")
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 7b81296427eb..f01de807b72f 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -464,13 +464,6 @@ static struct clk *bast_clocks[] = {
        &s3c24xx_uclk,
 };
-static struct s3c24xx_board bast_board __initdata = {
-        .devices       = bast_devices,
-        .devices_count = ARRAY_SIZE(bast_devices),
-        .clocks        = bast_clocks,
-        .clocks_count  = ARRAY_SIZE(bast_clocks),
-};
 static void __init bast_map_io(void)
 {
        /* initialise the clocks */
@@ -486,19 +479,22 @@ static void __init bast_map_io(void)
        s3c24xx_uclk.parent  = &s3c24xx_clkout1;
+        s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
        s3c_device_nand.dev.platform_data = &bast_nand_info;
        s3c_device_i2c.dev.platform_data = &bast_i2c_info;
        s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
-        s3c24xx_set_board(&bast_board);
        usb_simtec_init();
 }
 static void __init bast_init(void)
 {
        s3c24xx_fb_set_platdata(&bast_lcd_info);
+        platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
 }
 MACHINE_START(BAST, "Simtec-BAST")
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index d052ab2d9377..5d5f00e9c462 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -129,7 +129,6 @@ static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = {
 };
 /**
 * Set lcd on or off
 **/
@@ -188,17 +187,11 @@ static struct platform_device *h1940_devices[] __initdata = {
        &s3c_device_leds,
 };
-static struct s3c24xx_board h1940_board __initdata = {
-        .devices       = h1940_devices,
-        .devices_count = ARRAY_SIZE(h1940_devices)
-};
 static void __init h1940_map_io(void)
 {
        s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc));
        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
-        s3c24xx_set_board(&h1940_board);
        /* setup PM */
@@ -232,6 +225,8 @@ static void __init h1940_init(void)
              | (0x02 << S3C2410_PLLCON_PDIVSHIFT)
              | (0x03 << S3C2410_PLLCON_SDIVSHIFT);
        writel(tmp, S3C2410_UPLLCON);
+        platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
 }
 MACHINE_START(H1940, "IPAQ-H1940")
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 261aa4cc0770..412e50c3d28a 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -90,17 +90,11 @@ static struct s3c2410_platform_i2c n30_i2ccfg = {
        .max_freq       = 10*1000,
 };
-static struct s3c24xx_board n30_board __initdata = {
-        .devices       = n30_devices,
-        .devices_count = ARRAY_SIZE(n30_devices)
-};
 static void __init n30_map_io(void)
 {
        s3c24xx_init_io(n30_iodesc, ARRAY_SIZE(n30_iodesc));
        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
-        s3c24xx_set_board(&n30_board);
 }
 static void __init n30_init_irq(void)
@@ -120,6 +114,8 @@ static void __init n30_init(void)
        s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
                              S3C2410_MISCCR_USBSUSPND0 |
                              S3C2410_MISCCR_USBSUSPND1, 0x0);
+        platform_add_devices(n30_devices, ARRAY_SIZE(n30_devices));
 }
 MACHINE_START(N30, "Acer-N30")
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c
index c78ab75b44f3..1f899fa588df 100644
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c2410/mach-otom.c
@@ -100,20 +100,17 @@ static struct platform_device *otom11_devices[] __initdata = {
        &otom_device_nor,
 };
-static struct s3c24xx_board otom11_board __initdata = {
-        .devices       = otom11_devices,
-        .devices_count = ARRAY_SIZE(otom11_devices)
-};
 static void __init otom11_map_io(void)
 {
        s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc));
        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs));
-        s3c24xx_set_board(&otom11_board);
 }
+static void __init otom11_init(void)
+{
+        platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices));
+}
 MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
        /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
@@ -121,6 +118,7 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
        .boot_params    = S3C2410_SDRAM_PA + 0x100,
        .map_io         = otom11_map_io,
+        .init_machine   = otom11_init,
        .init_irq       = s3c24xx_init_irq,
        .timer          = &s3c24xx_timer,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index c6a41593de21..9cc4253d7bbc 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -29,7 +29,6 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
-#include <linux/mmc/protocol.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/spi_bitbang.h>
@@ -331,11 +330,6 @@ static struct platform_device *qt2410_devices[] __initdata = {
        &qt2410_led,
 };
-static struct s3c24xx_board qt2410_board __initdata = {
-        .devices       = qt2410_devices,
-        .devices_count = ARRAY_SIZE(qt2410_devices)
-};
 static struct mtd_partition qt2410_nand_part[] = {
        [0] = {
                .name   = "U-Boot",
@@ -405,7 +399,6 @@ static void __init qt2410_map_io(void)
        s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
        s3c24xx_init_clocks(12*1000*1000);
        s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
-        s3c24xx_set_board(&qt2410_board);
 }
 static void __init qt2410_machine_init(void)
@@ -432,6 +425,7 @@ static void __init qt2410_machine_init(void)
        s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
+        platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
        s3c2410_pm_init();
 }
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c
index 57b8a80f33d0..5852d300d52f 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
@@ -94,17 +94,17 @@ static struct platform_device *smdk2410_devices[] __initdata = {
        &s3c_device_iis,
 };
-static struct s3c24xx_board smdk2410_board __initdata = {
-        .devices       = smdk2410_devices,
-        .devices_count = ARRAY_SIZE(smdk2410_devices)
-};
 static void __init smdk2410_map_io(void)
 {
        s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc));
        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
-        s3c24xx_set_board(&smdk2410_board);
+}
+static void __init smdk2410_init(void)
+{
+        platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices));
+        smdk_machine_init();
 }
 MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switch
@@ -115,7 +115,7 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
        .boot_params    = S3C2410_SDRAM_PA + 0x100,
        .map_io         = smdk2410_map_io,
        .init_irq       = s3c24xx_init_irq,
-        .init_machine   = smdk_machine_init,
+        .init_machine   = smdk2410_init,
        .timer          = &s3c24xx_timer,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index c947c75bcbf0..7b624bb00490 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -384,13 +384,6 @@ static struct clk *vr1000_clocks[] = {
        &s3c24xx_uclk,
 };
-static struct s3c24xx_board vr1000_board __initdata = {
-        .devices       = vr1000_devices,
-        .devices_count = ARRAY_SIZE(vr1000_devices),
-        .clocks        = vr1000_clocks,
-        .clocks_count  = ARRAY_SIZE(vr1000_clocks),
-};
 static void vr1000_power_off(void)
 {
        s3c2410_gpio_cfgpin(S3C2410_GPB9, S3C2410_GPB9_OUTP);
@@ -412,15 +405,19 @@ static void __init vr1000_map_io(void)
        s3c24xx_uclk.parent  = &s3c24xx_clkout1;
+        s3c24xx_register_clocks(vr1000_clocks, ARRAY_SIZE(vr1000_clocks));
        pm_power_off = vr1000_power_off;
        s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
-        s3c24xx_set_board(&vr1000_board);
-        usb_simtec_init();
 }
+static void __init vr1000_init(void)
+{
+        platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices));
+}
 MACHINE_START(VR1000, "Thorcom-VR1000")
        /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
@@ -428,6 +425,7 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
        .boot_params    = S3C2410_SDRAM_PA + 0x100,
        .map_io         = vr1000_map_io,
+        .init_machine   = vr1000_init,
        .init_irq       = s3c24xx_init_irq,
        .timer          = &s3c24xx_timer,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index befc5fdbb613..d5be5d053264 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -47,6 +47,15 @@ config MACH_S3C2413
          machine_is_s3c2413() will work when MACH_SMDK2413 is
          selected
+config MACH_SMDK2412
+        bool "SMDK2412"
+        select MACH_SMDK2413
+        help
+          Say Y here if you are using an SMDK2412
+          Note, this shares support with SMDK2413, so will automatically
+          select MACH_SMDK2413.
 config MACH_VSTMS
        bool "VMSTMS"
        select CPU_S3C2412
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index b5befce6c8d3..063af09f899d 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -110,11 +110,6 @@ static struct platform_device *smdk2413_devices[] __initdata = {
        &s3c_device_usbgadget,
 };
-static struct s3c24xx_board smdk2413_board __initdata = {
-        .devices       = smdk2413_devices,
-        .devices_count = ARRAY_SIZE(smdk2413_devices)
-};
 static void __init smdk2413_fixup(struct machine_desc *desc,
                                  struct tag *tags, char **cmdline,
                                  struct meminfo *mi)
@@ -132,7 +127,6 @@ static void __init smdk2413_map_io(void)
        s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
-        s3c24xx_set_board(&smdk2413_board);
 }
 static void __init smdk2413_machine_init(void)
@@ -149,6 +143,7 @@ static void __init smdk2413_machine_init(void)
        s3c24xx_udc_set_platdata(&smdk2413_udc_cfg);
+        platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices));
        smdk_machine_init();
 }
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index 4231b549d797..f2fbd65956ac 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -129,11 +129,6 @@ static struct platform_device *vstms_devices[] __initdata = {
        &s3c_device_nand,
 };
-static struct s3c24xx_board vstms_board __initdata = {
-        .devices       = vstms_devices,
-        .devices_count = ARRAY_SIZE(vstms_devices)
-};
 static void __init vstms_fixup(struct machine_desc *desc,
                                  struct tag *tags, char **cmdline,
                                  struct meminfo *mi)
@@ -153,7 +148,11 @@ static void __init vstms_map_io(void)
        s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
-        s3c24xx_set_board(&vstms_board);
+}
+static void __init vstms_init(void)
+{
+        platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices));
 }
 MACHINE_START(VSTMS, "VSTMS")
@@ -163,6 +162,7 @@ MACHINE_START(VSTMS, "VSTMS")
        .fixup          = vstms_fixup,
        .init_irq       = s3c24xx_init_irq,
+        .init_machine   = vstms_init,
        .map_io         = vstms_map_io,
        .timer          = &s3c24xx_timer,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 3f0288eb1ed5..b5d387ef37e1 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -281,13 +281,6 @@ static struct clk *anubis_clocks[] = {
        &s3c24xx_uclk,
 };
-static struct s3c24xx_board anubis_board __initdata = {
-        .devices       = anubis_devices,
-        .devices_count = ARRAY_SIZE(anubis_devices),
-        .clocks        = anubis_clocks,
-        .clocks_count  = ARRAY_SIZE(anubis_clocks),
-};
 static void __init anubis_map_io(void)
 {
        /* initialise the clocks */
@@ -303,23 +296,31 @@ static void __init anubis_map_io(void)
        s3c24xx_uclk.parent  = &s3c24xx_clkout1;
+        s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
        s3c_device_nand.dev.platform_data = &anubis_nand_info;
        s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
-        s3c24xx_set_board(&anubis_board);
        /* ensure that the GPIO is setup */
        s3c2410_gpio_setpin(S3C2410_GPA0, 1);
 }
+static void __init anubis_init(void)
+{
+        platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
+}
 MACHINE_START(ANUBIS, "Simtec-Anubis")
        /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
        .phys_io        = S3C2410_PA_UART,
        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
        .boot_params    = S3C2410_SDRAM_PA + 0x100,
        .map_io         = anubis_map_io,
+        .init_machine   = anubis_init,
        .init_irq       = s3c24xx_init_irq,
        .timer          = &s3c24xx_timer,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 6d551d88330b..5e61f2166c76 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -116,12 +116,6 @@ static struct platform_device *nexcoder_devices[] __initdata = {
        &nexcoder_device_nor,
 };
-static struct s3c24xx_board nexcoder_board __initdata = {
-        .devices       = nexcoder_devices,
-        .devices_count = ARRAY_SIZE(nexcoder_devices),
-};
 static void __init nexcoder_sensorboard_init(void)
 {
        // Initialize SCCB bus
@@ -142,10 +136,14 @@ static void __init nexcoder_map_io(void)
        s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc));
        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs));
-        s3c24xx_set_board(&nexcoder_board);
        nexcoder_sensorboard_init();
 }
+static void __init nexcoder_init(void)
+{
+        platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices));
+};
 MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
        /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
@@ -153,6 +151,7 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
        .boot_params    = S3C2410_SDRAM_PA + 0x100,
        .map_io         = nexcoder_map_io,
+        .init_machine   = nexcoder_init,
        .init_irq       = s3c24xx_init_irq,
        .timer          = &s3c24xx_timer,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 2ed8e51f20c8..324f5a237921 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -251,13 +251,6 @@ static struct clk *osiris_clocks[] = {
        &s3c24xx_uclk,
 };
-static struct s3c24xx_board osiris_board __initdata = {
-        .devices       = osiris_devices,
-        .devices_count = ARRAY_SIZE(osiris_devices),
-        .clocks        = osiris_clocks,
-        .clocks_count  = ARRAY_SIZE(osiris_clocks),
-};
 static void __init osiris_map_io(void)
 {
        unsigned long flags;
@@ -275,12 +268,13 @@ static void __init osiris_map_io(void)
        s3c24xx_uclk.parent  = &s3c24xx_clkout1;
+        s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
        s3c_device_nand.dev.platform_data = &osiris_nand_info;
        s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
-        s3c24xx_set_board(&osiris_board);
        /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
@@ -292,12 +286,18 @@ static void __init osiris_map_io(void)
        s3c2410_gpio_setpin(S3C2410_GPA0, 1);
 }
+static void __init osiris_init(void)
+{
+        platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
+};
 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
        /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
        .phys_io        = S3C2410_PA_UART,
        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
        .boot_params    = S3C2410_SDRAM_PA + 0x100,
        .map_io         = osiris_map_io,
+        .init_machine   = osiris_init,
        .init_irq       = s3c24xx_init_irq,
        .timer          = &s3c24xx_timer,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index ae1d0a81fd6a..c3cc4bf158f6 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -202,11 +202,6 @@ static struct platform_device *rx3715_devices[] __initdata = {
        &s3c_device_nand,
 };
-static struct s3c24xx_board rx3715_board __initdata = {
-        .devices       = rx3715_devices,
-        .devices_count = ARRAY_SIZE(rx3715_devices)
-};
 static void __init rx3715_map_io(void)
 {
        s3c_device_nand.dev.platform_data = &rx3715_nand_info;
@@ -214,7 +209,6 @@ static void __init rx3715_map_io(void)
        s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
        s3c24xx_init_clocks(16934000);
        s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
-        s3c24xx_set_board(&rx3715_board);
 }
 static void __init rx3715_init_irq(void)
@@ -230,9 +224,9 @@ static void __init rx3715_init_machine(void)
        s3c2410_pm_init();
        s3c24xx_fb_set_platdata(&rx3715_lcdcfg);
+        platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
 }
 MACHINE_START(RX3715, "IPAQ-RX3715")
        /* Maintainer: Ben Dooks <ben@fluff.org> */
        .phys_io        = S3C2410_PA_UART,
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index c17eb5b1f6b4..e167254e232e 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -174,23 +174,18 @@ static struct platform_device *smdk2440_devices[] __initdata = {
        &s3c_device_iis,
 };
-static struct s3c24xx_board smdk2440_board __initdata = {
-        .devices       = smdk2440_devices,
-        .devices_count = ARRAY_SIZE(smdk2440_devices)
-};
 static void __init smdk2440_map_io(void)
 {
        s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc));
        s3c24xx_init_clocks(16934400);
        s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs));
-        s3c24xx_set_board(&smdk2440_board);
 }
 static void __init smdk2440_machine_init(void)
 {
        s3c24xx_fb_set_platdata(&smdk2440_lcd_cfg);
+        platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices));
        smdk_machine_init();
 }
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index e82aaff7dee4..b71ee53c2865 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -106,21 +106,16 @@ static struct platform_device *smdk2443_devices[] __initdata = {
        &s3c_device_i2c,
 };
-static struct s3c24xx_board smdk2443_board __initdata = {
-        .devices       = smdk2443_devices,
-        .devices_count = ARRAY_SIZE(smdk2443_devices)
-};
 static void __init smdk2443_map_io(void)
 {
        s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc));
        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs));
-        s3c24xx_set_board(&smdk2443_board);
 }
 static void __init smdk2443_machine_init(void)
 {
+        platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices));
        smdk_machine_init();
 }
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
index b1e8fd766c1a..fc97fe57ee6f 100644
--- a/arch/arm/mach-sa1100/clock.c
+++ b/arch/arm/mach-sa1100/clock.c
@@ -9,14 +9,17 @@
 #include <linux/string.h>
 #include <linux/clk.h>
 #include <linux/spinlock.h>
+#include <linux/mutex.h>
 #include <asm/hardware.h>
-#include <asm/semaphore.h>
+/*
+ * Very simple clock implementation - we only have one clock to
+ * deal with at the moment, so we only match using the "name".
+ */
 struct clk {
        struct list_head        node;
        unsigned long           rate;
-        struct module           *owner;
        const char              *name;
        unsigned int            enabled;
        void                    (*enable)(void);
@@ -24,21 +27,21 @@ struct clk {
 };
 static LIST_HEAD(clocks);
-static DECLARE_MUTEX(clocks_sem);
+static DEFINE_MUTEX(clocks_mutex);
 static DEFINE_SPINLOCK(clocks_lock);
 struct clk *clk_get(struct device *dev, const char *id)
 {
        struct clk *p, *clk = ERR_PTR(-ENOENT);
-        down(&clocks_sem);
+        mutex_lock(&clocks_mutex);
        list_for_each_entry(p, &clocks, node) {
-                if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
+                if (strcmp(id, p->name) == 0) {
                        clk = p;
                        break;
                }
        }
-        up(&clocks_sem);
+        mutex_unlock(&clocks_mutex);
        return clk;
 }
@@ -46,7 +49,6 @@ EXPORT_SYMBOL(clk_get);
 void clk_put(struct clk *clk)
 {
-        module_put(clk->owner);
 }
 EXPORT_SYMBOL(clk_put);
@@ -109,18 +111,18 @@ static struct clk clk_gpio27 = {
 int clk_register(struct clk *clk)
 {
-        down(&clocks_sem);
+        mutex_lock(&clocks_mutex);
        list_add(&clk->node, &clocks);
-        up(&clocks_sem);
+        mutex_unlock(&clocks_mutex);
        return 0;
 }
 EXPORT_SYMBOL(clk_register);
 void clk_unregister(struct clk *clk)
 {
-        down(&clocks_sem);
+        mutex_lock(&clocks_mutex);
        list_del(&clk->node);
-        up(&clocks_sem);
+        mutex_unlock(&clocks_mutex);
 }
 EXPORT_SYMBOL(clk_unregister);
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index 786c8534231f..d674cf343156 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -59,9 +59,6 @@ static int sa11x0_pm_enter(suspend_state_t state)
        unsigned long gpio, sleep_save[SLEEP_SAVE_SIZE];
        struct timespec delta, rtc;
-        if (state != PM_SUSPEND_MEM)
-                return -EINVAL;
        /* preserve current time */
        rtc.tv_sec = RCNR;
        rtc.tv_nsec = 0;
@@ -134,12 +131,9 @@ unsigned long sleep_phys_sp(void *sp)
        return virt_to_phys(sp);
 }
-/*
- * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
- */
 static struct pm_ops sa11x0_pm_ops = {
-        .pm_disk_mode   = PM_DISK_FIRMWARE,
        .enter          = sa11x0_pm_enter,
+        .valid          = pm_valid_only_mem,
 };
 static int __init sa11x0_pm_init(void)
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index bf71507c76fd..1275aa7d2eb1 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -26,6 +26,8 @@
 #include <linux/interrupt.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 #include <asm/cnt32_to_63.h>
 #include <asm/system.h>
@@ -828,59 +830,61 @@ void __init versatile_init(void)
 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 #endif
-/*
+static void timer_set_mode(enum clock_event_mode mode,
- * Returns number of ms since last clock interrupt.  Note that interrupts
+                           struct clock_event_device *clk)
- * will have been disabled by do_gettimeoffset()
- */
-static unsigned long versatile_gettimeoffset(void)
 {
-        unsigned long ticks1, ticks2, status;
+        unsigned long ctrl;
-        /*
+        switch(mode) {
-         * Get the current number of ticks.  Note that there is a race
+        case CLOCK_EVT_MODE_PERIODIC:
-         * condition between us reading the timer and checking for
+                writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
-         * an interrupt.  We get around this by ensuring that the
-         * counter has not reloaded between our two reads.
-         */
-        ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
-        do {
-                ticks1 = ticks2;
-                status = __raw_readl(VA_IC_BASE + VIC_RAW_STATUS);
-                ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
-        } while (ticks2 > ticks1);
-        /*
+                ctrl = TIMER_CTRL_PERIODIC;
-         * Number of ticks since last interrupt.
+                ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
-         */
+                break;
-        ticks1 = TIMER_RELOAD - ticks2;
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* period set, and timer enabled in 'next_event' hook */
+                ctrl = TIMER_CTRL_ONESHOT;
+                ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        default:
+                ctrl = 0;
+        }
-        /*
+        writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
-         * Interrupt pending?  If so, we've reloaded once already.
+}
-         *
-         * FIXME: Need to check this is effectively timer 0 that expires
-         */
-        if (status & IRQMASK_TIMERINT0_1)
-                ticks1 += TIMER_RELOAD;
-        /*
+static int timer_set_next_event(unsigned long evt,
-         * Convert the ticks to usecs
+                                struct clock_event_device *unused)
-         */
+{
-        return TICKS2USECS(ticks1);
+        unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
+        writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
+        writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
+        return 0;
 }
+static struct clock_event_device timer0_clockevent =     {
+        .name           = "timer0",
+        .shift          = 32,
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .set_mode       = timer_set_mode,
+        .set_next_event = timer_set_next_event,
+};
 /*
 * IRQ handler for the timer
 */
 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id)
 {
-        write_seqlock(&xtime_lock);
+        struct clock_event_device *evt = &timer0_clockevent;
-        // ...clear the interrupt
        writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
-        timer_tick();
+        evt->event_handler(evt);
-        write_sequnlock(&xtime_lock);
        return IRQ_HANDLED;
 }
@@ -891,6 +895,36 @@ static struct irqaction versatile_timer_irq = {
        .handler        = versatile_timer_interrupt,
 };
+static cycle_t versatile_get_cycles(void)
+{
+        return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
+}
+static struct clocksource clocksource_versatile = {
+        .name           = "timer3",
+        .rating         = 200,
+        .read           = versatile_get_cycles,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .shift          = 20,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+static int __init versatile_clocksource_init(void)
+{
+        /* setup timer3 as free-running clocksource */
+        writel(0, TIMER3_VA_BASE + TIMER_CTRL);
+        writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
+        writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
+        writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
+               TIMER3_VA_BASE + TIMER_CTRL);
+        clocksource_versatile.mult =
+                clocksource_khz2mult(1000, clocksource_versatile.shift);
+        clocksource_register(&clocksource_versatile);
+        return 0;
+}
 /*
 * Set up timer interrupt, and return the current time in seconds.
 */
@@ -918,18 +952,25 @@ static void __init versatile_timer_init(void)
        writel(0, TIMER2_VA_BASE + TIMER_CTRL);
        writel(0, TIMER3_VA_BASE + TIMER_CTRL);
-        writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
-        writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
-        writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
-               TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
        /* 
         * Make irqs happen for the system timer
         */
        setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
+        versatile_clocksource_init();
+        timer0_clockevent.mult =
+                div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
+        timer0_clockevent.max_delta_ns =
+                clockevent_delta2ns(0xffffffff, &timer0_clockevent);
+        timer0_clockevent.min_delta_ns =
+                clockevent_delta2ns(0xf, &timer0_clockevent);
+        timer0_clockevent.cpumask = cpumask_of_cpu(0);
+        clockevents_register_device(&timer0_clockevent);
 }
 struct sys_timer versatile_timer = {
        .init           = versatile_timer_init,
-        .offset         = versatile_gettimeoffset,
 };
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e684e9b38216..b81391a4e374 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -366,6 +366,19 @@ config CPU_32v6K
          enabled will not boot on processors with do not support these
          instructions.
+# ARMv7
+config CPU_V7
+        bool "Support ARM V7 processor"
+        depends on ARCH_INTEGRATOR
+        select CPU_32v6K
+        select CPU_32v7
+        select CPU_ABRT_EV7
+        select CPU_CACHE_V7
+        select CPU_CACHE_VIPT
+        select CPU_CP15_MMU
+        select CPU_COPY_V6 if MMU
+        select CPU_TLB_V6 if MMU
 # Figure out what processor architecture version we should be using.
 # This defines the compiler instruction set which depends on the machine type.
 config CPU_32v3
@@ -391,6 +404,9 @@ config CPU_32v5
 config CPU_32v6
        bool
+config CPU_32v7
+        bool
 # The abort model
 config CPU_ABRT_NOMMU
        bool
@@ -413,6 +429,9 @@ config CPU_ABRT_EV5TJ
 config CPU_ABRT_EV6
        bool
+config CPU_ABRT_EV7
+        bool
 # The cache model
 config CPU_CACHE_V3
        bool
@@ -429,6 +448,9 @@ config CPU_CACHE_V4WB
 config CPU_CACHE_V6
        bool
+config CPU_CACHE_V7
+        bool
 config CPU_CACHE_VIVT
        bool
@@ -503,7 +525,7 @@ comment "Processor Features"
 config ARM_THUMB
        bool "Support Thumb user binaries"
-        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
+        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7
        default y
        help
          Say Y if you want to include kernel support for running user space
@@ -578,9 +600,15 @@ config CPU_CACHE_ROUND_ROBIN
          Say Y here to use the predictable round-robin cache replacement
          policy.  Unless you specifically require this or are unsure, say N.
+config CPU_L2CACHE_DISABLE
+        bool "Disable level 2 cache"
+        depends on CPU_V7
+        help
+          Say Y here to disable the level 2 cache.  If unsure, say N.
 config CPU_BPREDICT_DISABLE
        bool "Disable branch prediction"
-        depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3
+        depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
        help
          Say Y here to disable branch prediction.  If unsure, say N.
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 2f8b95947774..b5bd335ff14a 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -24,12 +24,14 @@ obj-$(CONFIG_CPU_ABRT_LV4T)	+= abort-lv4t.o
 obj-$(CONFIG_CPU_ABRT_EV5T)     += abort-ev5t.o
 obj-$(CONFIG_CPU_ABRT_EV5TJ)    += abort-ev5tj.o
 obj-$(CONFIG_CPU_ABRT_EV6)      += abort-ev6.o
+obj-$(CONFIG_CPU_ABRT_EV7)      += abort-ev7.o
 obj-$(CONFIG_CPU_CACHE_V3)      += cache-v3.o
 obj-$(CONFIG_CPU_CACHE_V4)      += cache-v4.o
 obj-$(CONFIG_CPU_CACHE_V4WT)    += cache-v4wt.o
 obj-$(CONFIG_CPU_CACHE_V4WB)    += cache-v4wb.o
 obj-$(CONFIG_CPU_CACHE_V6)      += cache-v6.o
+obj-$(CONFIG_CPU_CACHE_V7)      += cache-v7.o
 obj-$(CONFIG_CPU_COPY_V3)       += copypage-v3.o
 obj-$(CONFIG_CPU_COPY_V4WT)     += copypage-v4wt.o
@@ -66,5 +68,6 @@ obj-$(CONFIG_CPU_SA1100)	+= proc-sa1100.o
 obj-$(CONFIG_CPU_XSCALE)        += proc-xscale.o
 obj-$(CONFIG_CPU_XSC3)          += proc-xsc3.o
 obj-$(CONFIG_CPU_V6)            += proc-v6.o
+obj-$(CONFIG_CPU_V7)            += proc-v7.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
diff --git a/arch/arm/mm/abort-ev7.S b/arch/arm/mm/abort-ev7.S
new file mode 100644
index 000000000000..eb90bce38e14
--- /dev/null
+++ b/arch/arm/mm/abort-ev7.S
@@ -0,0 +1,32 @@
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+/*
+ * Function: v7_early_abort
+ *
+ * Params  : r2 = address of aborted instruction
+ *         : r3 = saved SPSR
+ *
+ * Returns : r0 = address of abort
+ *         : r1 = FSR, bit 11 = write
+ *         : r2-r8 = corrupted
+ *         : r9 = preserved
+ *         : sp = pointer to registers
+ *
+ * Purpose : obtain information about current aborted instruction.
+ */
+        .align  5
+ENTRY(v7_early_abort)
+        /*
+         * The effect of data aborts on on the exclusive access monitor are
+         * UNPREDICTABLE. Do a CLREX to clear the state
+         */
+        clrex
+        mrc     p15, 0, r1, c5, c0, 0           @ get FSR
+        mrc     p15, 0, r0, c6, c0, 0           @ get FAR
+        /*
+         * V6 code adjusts the returned DFSR.
+         * New designs should not need to patch up faults.
+         */
+        mov     pc, lr
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
new file mode 100644
index 000000000000..35ffc4d95997
--- /dev/null
+++ b/arch/arm/mm/cache-v7.S
@@ -0,0 +1,253 @@
+/*
+ *  linux/arch/arm/mm/cache-v7.S
+ *
+ *  Copyright (C) 2001 Deep Blue Solutions Ltd.
+ *  Copyright (C) 2005 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This is the "shell" of the ARMv7 processor support.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/assembler.h>
+#include "proc-macros.S"
+/*
+ *      v7_flush_dcache_all()
+ *
+ *      Flush the whole D-cache.
+ *
+ *      Corrupted registers: r0-r5, r7, r9-r11
+ *
+ *      - mm    - mm_struct describing address space
+ */
+ENTRY(v7_flush_dcache_all)
+        mrc     p15, 1, r0, c0, c0, 1           @ read clidr
+        ands    r3, r0, #0x7000000              @ extract loc from clidr
+        mov     r3, r3, lsr #23                 @ left align loc bit field
+        beq     finished                        @ if loc is 0, then no need to clean
+        mov     r10, #0                         @ start clean at cache level 0
+loop1:
+        add     r2, r10, r10, lsr #1            @ work out 3x current cache level
+        mov     r1, r0, lsr r2                  @ extract cache type bits from clidr
+        and     r1, r1, #7                      @ mask of the bits for current cache only
+        cmp     r1, #2                          @ see what cache we have at this level
+        blt     skip                            @ skip if no cache, or just i-cache
+        mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
+        isb                                     @ isb to sych the new cssr&csidr
+        mrc     p15, 1, r1, c0, c0, 0           @ read the new csidr
+        and     r2, r1, #7                      @ extract the length of the cache lines
+        add     r2, r2, #4                      @ add 4 (line length offset)
+        ldr     r4, =0x3ff
+        ands    r4, r4, r1, lsr #3              @ find maximum number on the way size
+        clz     r5, r4                          @ find bit position of way size increment
+        ldr     r7, =0x7fff
+        ands    r7, r7, r1, lsr #13             @ extract max number of the index size
+loop2:
+        mov     r9, r4                          @ create working copy of max way size
+loop3:
+        orr     r11, r10, r9, lsl r5            @ factor way and cache number into r11
+        orr     r11, r11, r7, lsl r2            @ factor index number into r11
+        mcr     p15, 0, r11, c7, c14, 2         @ clean & invalidate by set/way
+        subs    r9, r9, #1                      @ decrement the way
+        bge     loop3
+        subs    r7, r7, #1                      @ decrement the index
+        bge     loop2
+skip:
+        add     r10, r10, #2                    @ increment cache number
+        cmp     r3, r10
+        bgt     loop1
+finished:
+        mov     r10, #0                         @ swith back to cache level 0
+        mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
+        isb
+        mov     pc, lr
+/*
+ *      v7_flush_cache_all()
+ *
+ *      Flush the entire cache system.
+ *  The data cache flush is now achieved using atomic clean / invalidates
+ *  working outwards from L1 cache. This is done using Set/Way based cache
+ *  maintainance instructions.
+ *  The instruction cache can still be invalidated back to the point of
+ *  unification in a single instruction.
+ *
+ */
+ENTRY(v7_flush_kern_cache_all)
+        stmfd   sp!, {r4-r5, r7, r9-r11, lr}
+        bl      v7_flush_dcache_all
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
+        ldmfd   sp!, {r4-r5, r7, r9-r11, lr}
+        mov     pc, lr
+/*
+ *      v7_flush_cache_all()
+ *
+ *      Flush all TLB entries in a particular address space
+ *
+ *      - mm    - mm_struct describing address space
+ */
+ENTRY(v7_flush_user_cache_all)
+        /*FALLTHROUGH*/
+/*
+ *      v7_flush_cache_range(start, end, flags)
+ *
+ *      Flush a range of TLB entries in the specified address space.
+ *
+ *      - start - start address (may not be aligned)
+ *      - end   - end address (exclusive, may not be aligned)
+ *      - flags - vm_area_struct flags describing address space
+ *
+ *      It is assumed that:
+ *      - we have a VIPT cache.
+ */
+ENTRY(v7_flush_user_cache_range)
+        mov     pc, lr
+/*
+ *      v7_coherent_kern_range(start,end)
+ *
+ *      Ensure that the I and D caches are coherent within specified
+ *      region.  This is typically used when code has been written to
+ *      a memory region, and will be executed.
+ *
+ *      - start   - virtual start address of region
+ *      - end     - virtual end address of region
+ *
+ *      It is assumed that:
+ *      - the Icache does not read data from the write buffer
+ */
+ENTRY(v7_coherent_kern_range)
+        /* FALLTHROUGH */
+/*
+ *      v7_coherent_user_range(start,end)
+ *
+ *      Ensure that the I and D caches are coherent within specified
+ *      region.  This is typically used when code has been written to
+ *      a memory region, and will be executed.
+ *
+ *      - start   - virtual start address of region
+ *      - end     - virtual end address of region
+ *
+ *      It is assumed that:
+ *      - the Icache does not read data from the write buffer
+ */
+ENTRY(v7_coherent_user_range)
+        dcache_line_size r2, r3
+        sub     r3, r2, #1
+        bic     r0, r0, r3
+1:      mcr     p15, 0, r0, c7, c11, 1          @ clean D line to the point of unification
+        dsb
+        mcr     p15, 0, r0, c7, c5, 1           @ invalidate I line
+        add     r0, r0, r2
+        cmp     r0, r1
+        blo     1b
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB
+        dsb
+        isb
+        mov     pc, lr
+/*
+ *      v7_flush_kern_dcache_page(kaddr)
+ *
+ *      Ensure that the data held in the page kaddr is written back
+ *      to the page in question.
+ *
+ *      - kaddr   - kernel address (guaranteed to be page aligned)
+ */
+ENTRY(v7_flush_kern_dcache_page)
+        dcache_line_size r2, r3
+        add     r1, r0, #PAGE_SZ
+1:
+        mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line / unified line
+        add     r0, r0, r2
+        cmp     r0, r1
+        blo     1b
+        dsb
+        mov     pc, lr
+/*
+ *      v7_dma_inv_range(start,end)
+ *
+ *      Invalidate the data cache within the specified region; we will
+ *      be performing a DMA operation in this region and we want to
+ *      purge old data in the cache.
+ *
+ *      - start   - virtual start address of region
+ *      - end     - virtual end address of region
+ */
+ENTRY(v7_dma_inv_range)
+        dcache_line_size r2, r3
+        sub     r3, r2, #1
+        tst     r0, r3
+        bic     r0, r0, r3
+        mcrne   p15, 0, r0, c7, c14, 1          @ clean & invalidate D / U line
+        tst     r1, r3
+        bic     r1, r1, r3
+        mcrne   p15, 0, r1, c7, c14, 1          @ clean & invalidate D / U line
+1:
+        mcr     p15, 0, r0, c7, c6, 1           @ invalidate D / U line
+        add     r0, r0, r2
+        cmp     r0, r1
+        blo     1b
+        dsb
+        mov     pc, lr
+/*
+ *      v7_dma_clean_range(start,end)
+ *      - start   - virtual start address of region
+ *      - end     - virtual end address of region
+ */
+ENTRY(v7_dma_clean_range)
+        dcache_line_size r2, r3
+        sub     r3, r2, #1
+        bic     r0, r0, r3
+1:
+        mcr     p15, 0, r0, c7, c10, 1          @ clean D / U line
+        add     r0, r0, r2
+        cmp     r0, r1
+        blo     1b
+        dsb
+        mov     pc, lr
+/*
+ *      v7_dma_flush_range(start,end)
+ *      - start   - virtual start address of region
+ *      - end     - virtual end address of region
+ */
+ENTRY(v7_dma_flush_range)
+        dcache_line_size r2, r3
+        sub     r3, r2, #1
+        bic     r0, r0, r3
+1:
+        mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D / U line
+        add     r0, r0, r2
+        cmp     r0, r1
+        blo     1b
+        dsb
+        mov     pc, lr
+        __INITDATA
+        .type   v7_cache_fns, #object
+ENTRY(v7_cache_fns)
+        .long   v7_flush_kern_cache_all
+        .long   v7_flush_user_cache_all
+        .long   v7_flush_user_cache_range
+        .long   v7_coherent_kern_range
+        .long   v7_coherent_user_range
+        .long   v7_flush_kern_dcache_page
+        .long   v7_dma_inv_range
+        .long   v7_dma_clean_range
+        .long   v7_dma_flush_range
+        .size   v7_cache_fns, . - v7_cache_fns
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 9da43a0fdcdf..fc84fcc74380 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -14,7 +14,8 @@
 #include <asm/mmu_context.h>
 #include <asm/tlbflush.h>
-unsigned int cpu_last_asid = { 1 << ASID_BITS };
+static DEFINE_SPINLOCK(cpu_asid_lock);
+unsigned int cpu_last_asid = ASID_FIRST_VERSION;
 /*
 * We fork()ed a process, and we need a new context for the child
@@ -31,15 +32,16 @@ void __new_context(struct mm_struct *mm)
 {
        unsigned int asid;
+        spin_lock(&cpu_asid_lock);
        asid = ++cpu_last_asid;
        if (asid == 0)
-                asid = cpu_last_asid = 1 << ASID_BITS;
+                asid = cpu_last_asid = ASID_FIRST_VERSION;
        /*
         * If we've used up all our ASIDs, we need
         * to start a new version and flush the TLB.
         */
-        if ((asid & ~ASID_MASK) == 0) {
+        if (unlikely((asid & ~ASID_MASK) == 0)) {
                asid = ++cpu_last_asid;
                /* set the reserved ASID before flushing the TLB */
                asm("mcr        p15, 0, %0, c13, c0, 1  @ set reserved context ID\n"
@@ -47,7 +49,16 @@ void __new_context(struct mm_struct *mm)
                    : "r" (0));
                isb();
                flush_tlb_all();
+                if (icache_is_vivt_asid_tagged()) {
+                        asm("mcr        p15, 0, %0, c7, c5, 0   @ invalidate I-cache\n"
+                            "mcr        p15, 0, %0, c7, c5, 6   @ flush BTAC/BTB\n"
+                            :
+                            : "r" (0));
+                        dsb();
+                }
        }
+        spin_unlock(&cpu_asid_lock);
+        mm->cpu_vm_mask = cpumask_of_cpu(smp_processor_id());
        mm->context.id = asid;
 }
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 0ac615c0f798..d6167ad4e011 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -32,6 +32,9 @@
 #include <asm/tlbflush.h>
 #include <asm/sizes.h>
+#include <asm/mach/map.h>
+#include "mm.h"
 /*
 * Used by ioremap() and iounmap() code to mark (super)section-mapped
 * I/O regions in vm_struct->flags field.
@@ -39,8 +42,9 @@
 #define VM_ARM_SECTION_MAPPING  0x80000000
 static int remap_area_pte(pmd_t *pmd, unsigned long addr, unsigned long end,
-                          unsigned long phys_addr, pgprot_t prot)
+                          unsigned long phys_addr, const struct mem_type *type)
 {
+        pgprot_t prot = __pgprot(type->prot_pte);
        pte_t *pte;
        pte = pte_alloc_kernel(pmd, addr);
@@ -51,7 +55,8 @@ static int remap_area_pte(pmd_t *pmd, unsigned long addr, unsigned long end,
                if (!pte_none(*pte))
                        goto bad;
-                set_pte_ext(pte, pfn_pte(phys_addr >> PAGE_SHIFT, prot), 0);
+                set_pte_ext(pte, pfn_pte(phys_addr >> PAGE_SHIFT, prot),
+                            type->prot_pte_ext);
                phys_addr += PAGE_SIZE;
        } while (pte++, addr += PAGE_SIZE, addr != end);
        return 0;
@@ -63,7 +68,7 @@ static int remap_area_pte(pmd_t *pmd, unsigned long addr, unsigned long end,
 static inline int remap_area_pmd(pgd_t *pgd, unsigned long addr,
                                 unsigned long end, unsigned long phys_addr,
-                                 pgprot_t prot)
+                                 const struct mem_type *type)
 {
        unsigned long next;
        pmd_t *pmd;
@@ -75,7 +80,7 @@ static inline int remap_area_pmd(pgd_t *pgd, unsigned long addr,
        do {
                next = pmd_addr_end(addr, end);
-                ret = remap_area_pte(pmd, addr, next, phys_addr, prot);
+                ret = remap_area_pte(pmd, addr, next, phys_addr, type);
                if (ret)
                        return ret;
                phys_addr += next - addr;
@@ -84,13 +89,11 @@ static inline int remap_area_pmd(pgd_t *pgd, unsigned long addr,
 }
 static int remap_area_pages(unsigned long start, unsigned long pfn,
-                            unsigned long size, unsigned long flags)
+                            size_t size, const struct mem_type *type)
 {
        unsigned long addr = start;
        unsigned long next, end = start + size;
        unsigned long phys_addr = __pfn_to_phys(pfn);
-        pgprot_t prot = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
-                                 L_PTE_DIRTY | L_PTE_WRITE | flags);
        pgd_t *pgd;
        int err = 0;
@@ -98,7 +101,7 @@ static int remap_area_pages(unsigned long start, unsigned long pfn,
        pgd = pgd_offset_k(addr);
        do {
                next = pgd_addr_end(addr, end);
-                err = remap_area_pmd(pgd, addr, next, phys_addr, prot);
+                err = remap_area_pmd(pgd, addr, next, phys_addr, type);
                if (err)
                        break;
                phys_addr += next - addr;
@@ -178,9 +181,9 @@ static void unmap_area_sections(unsigned long virt, unsigned long size)
 static int
 remap_area_sections(unsigned long virt, unsigned long pfn,
-                    unsigned long size, unsigned long flags)
+                    size_t size, const struct mem_type *type)
 {
-        unsigned long prot, addr = virt, end = virt + size;
+        unsigned long addr = virt, end = virt + size;
        pgd_t *pgd;
        /*
@@ -189,23 +192,13 @@ remap_area_sections(unsigned long virt, unsigned long pfn,
         */
        unmap_area_sections(virt, size);
-        prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO) |
-               (flags & (L_PTE_CACHEABLE | L_PTE_BUFFERABLE));
-        /*
-         * ARMv6 and above need XN set to prevent speculative prefetches
-         * hitting IO.
-         */
-        if (cpu_architecture() >= CPU_ARCH_ARMv6)
-                prot |= PMD_SECT_XN;
        pgd = pgd_offset_k(addr);
        do {
                pmd_t *pmd = pmd_offset(pgd, addr);
-                pmd[0] = __pmd(__pfn_to_phys(pfn) | prot);
+                pmd[0] = __pmd(__pfn_to_phys(pfn) | type->prot_sect);
                pfn += SZ_1M >> PAGE_SHIFT;
-                pmd[1] = __pmd(__pfn_to_phys(pfn) | prot);
+                pmd[1] = __pmd(__pfn_to_phys(pfn) | type->prot_sect);
                pfn += SZ_1M >> PAGE_SHIFT;
                flush_pmd_entry(pmd);
@@ -218,9 +211,9 @@ remap_area_sections(unsigned long virt, unsigned long pfn,
 static int
 remap_area_supersections(unsigned long virt, unsigned long pfn,
-                         unsigned long size, unsigned long flags)
+                         size_t size, const struct mem_type *type)
 {
-        unsigned long prot, addr = virt, end = virt + size;
+        unsigned long addr = virt, end = virt + size;
        pgd_t *pgd;
        /*
@@ -229,22 +222,12 @@ remap_area_supersections(unsigned long virt, unsigned long pfn,
         */
        unmap_area_sections(virt, size);
-        prot = PMD_TYPE_SECT | PMD_SECT_SUPER | PMD_SECT_AP_WRITE |
-                        PMD_DOMAIN(DOMAIN_IO) |
-                        (flags & (L_PTE_CACHEABLE | L_PTE_BUFFERABLE));
-        /*
-         * ARMv6 and above need XN set to prevent speculative prefetches
-         * hitting IO.
-         */
-        if (cpu_architecture() >= CPU_ARCH_ARMv6)
-                prot |= PMD_SECT_XN;
        pgd = pgd_offset_k(virt);
        do {
                unsigned long super_pmd_val, i;
-                super_pmd_val = __pfn_to_phys(pfn) | prot;
+                super_pmd_val = __pfn_to_phys(pfn) | type->prot_sect |
+                                PMD_SECT_SUPER;
                super_pmd_val |= ((pfn >> (32 - PAGE_SHIFT)) & 0xf) << 20;
                for (i = 0; i < 8; i++) {
@@ -279,9 +262,10 @@ remap_area_supersections(unsigned long virt, unsigned long pfn,
 * mapping.  See include/asm-arm/proc-armv/pgtable.h for more information.
 */
 void __iomem *
-__ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
+__arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
-              unsigned long flags)
+                  unsigned int mtype)
 {
+        const struct mem_type *type;
        int err;
        unsigned long addr;
        struct vm_struct * area;
@@ -292,6 +276,10 @@ __ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
        if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK))
                return NULL;
+        type = get_mem_type(mtype);
+        if (!type)
+                return NULL;
        size = PAGE_ALIGN(size);
        area = get_vm_area(size, VM_IOREMAP);
@@ -302,16 +290,16 @@ __ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
 #ifndef CONFIG_SMP
        if (DOMAIN_IO == 0 &&
            (((cpu_architecture() >= CPU_ARCH_ARMv6) && (get_cr() & CR_XP)) ||
-               cpu_is_xsc3()) &&
+               cpu_is_xsc3()) && pfn >= 0x100000 &&
               !((__pfn_to_phys(pfn) | size | addr) & ~SUPERSECTION_MASK)) {
                area->flags |= VM_ARM_SECTION_MAPPING;
-                err = remap_area_supersections(addr, pfn, size, flags);
+                err = remap_area_supersections(addr, pfn, size, type);
        } else if (!((__pfn_to_phys(pfn) | size | addr) & ~PMD_MASK)) {
                area->flags |= VM_ARM_SECTION_MAPPING;
-                err = remap_area_sections(addr, pfn, size, flags);
+                err = remap_area_sections(addr, pfn, size, type);
        } else
 #endif
-                err = remap_area_pages(addr, pfn, size, flags);
+                err = remap_area_pages(addr, pfn, size, type);
        if (err) {
                vunmap((void *)addr);
@@ -321,10 +309,10 @@ __ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
        flush_cache_vmap(addr, addr + size);
        return (void __iomem *) (offset + addr);
 }
-EXPORT_SYMBOL(__ioremap_pfn);
+EXPORT_SYMBOL(__arm_ioremap_pfn);
 void __iomem *
-__ioremap(unsigned long phys_addr, size_t size, unsigned long flags)
+__arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
 {
        unsigned long last_addr;
        unsigned long offset = phys_addr & ~PAGE_MASK;
@@ -342,9 +330,9 @@ __ioremap(unsigned long phys_addr, size_t size, unsigned long flags)
         */
        size = PAGE_ALIGN(last_addr + 1) - phys_addr;
-        return __ioremap_pfn(pfn, offset, size, flags);
+        return __arm_ioremap_pfn(pfn, offset, size, mtype);
 }
-EXPORT_SYMBOL(__ioremap);
+EXPORT_SYMBOL(__arm_ioremap);
 void __iounmap(volatile void __iomem *addr)
 {
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index a44e30970635..7647c597fc59 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -16,6 +16,16 @@ static inline pmd_t *pmd_off_k(unsigned long virt)
        return pmd_off(pgd_offset_k(virt), virt);
 }
+struct mem_type {
+        unsigned int prot_pte;
+        unsigned int prot_pte_ext;
+        unsigned int prot_l1;
+        unsigned int prot_sect;
+        unsigned int domain;
+};
+const struct mem_type *get_mem_type(unsigned int type);
 #endif
 struct map_desc;
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index b0b5f4694070..2c4c2422cd1e 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -49,8 +49,7 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
 #endif
        /*
-         * We should enforce the MAP_FIXED case.  However, currently
+         * We enforce the MAP_FIXED case.
-         * the generic kernel code doesn't allow us to handle this.
         */
        if (flags & MAP_FIXED) {
                if (aliasing && flags & MAP_SHARED && addr & (SHMLBA - 1))
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 94fd4bf5cb9e..2ba1530d1ce1 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -176,28 +176,42 @@ void adjust_cr(unsigned long mask, unsigned long set)
 }
 #endif
-struct mem_types {
+#define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
-        unsigned int    prot_pte;
+#define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_XN|PMD_SECT_AP_WRITE
-        unsigned int    prot_l1;
-        unsigned int    prot_sect;
+static struct mem_type mem_types[] = {
-        unsigned int    domain;
+        [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
-};
+                .prot_pte       = PROT_PTE_DEVICE,
+                .prot_l1        = PMD_TYPE_TABLE,
-static struct mem_types mem_types[] __initdata = {
+                .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_UNCACHED,
-        [MT_DEVICE] = {
+                .domain         = DOMAIN_IO,
-                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+        },
-                                L_PTE_WRITE,
+        [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
-                .prot_l1   = PMD_TYPE_TABLE,
+                .prot_pte       = PROT_PTE_DEVICE,
-                .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
+                .prot_pte_ext   = PTE_EXT_TEX(2),
-                                PMD_SECT_AP_WRITE,
+                .prot_l1        = PMD_TYPE_TABLE,
-                .domain    = DOMAIN_IO,
+                .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_TEX(2),
+                .domain         = DOMAIN_IO,
+        },
+        [MT_DEVICE_CACHED] = {    /* ioremap_cached */
+                .prot_pte       = PROT_PTE_DEVICE | L_PTE_CACHEABLE | L_PTE_BUFFERABLE,
+                .prot_l1        = PMD_TYPE_TABLE,
+                .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
+                .domain         = DOMAIN_IO,
+        },      
+        [MT_DEVICE_IXP2000] = {   /* IXP2400 requires XCB=101 for on-chip I/O */
+                .prot_pte       = PROT_PTE_DEVICE,
+                .prot_l1        = PMD_TYPE_TABLE,
+                .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE |
+                                  PMD_SECT_TEX(1),
+                .domain         = DOMAIN_IO,
        },
        [MT_CACHECLEAN] = {
-                .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
+                .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
                .domain    = DOMAIN_KERNEL,
        },
        [MT_MINICLEAN] = {
-                .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_MINICACHE,
+                .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
                .domain    = DOMAIN_KERNEL,
        },
        [MT_LOW_VECTORS] = {
@@ -213,30 +227,20 @@ static struct mem_types mem_types[] __initdata = {
                .domain    = DOMAIN_USER,
        },
        [MT_MEMORY] = {
-                .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_AP_WRITE,
+                .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
                .domain    = DOMAIN_KERNEL,
        },
        [MT_ROM] = {
-                .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
+                .prot_sect = PMD_TYPE_SECT,
                .domain    = DOMAIN_KERNEL,
        },
-        [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
-                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
-                                L_PTE_WRITE,
-                .prot_l1   = PMD_TYPE_TABLE,
-                .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
-                                PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
-                                PMD_SECT_TEX(1),
-                .domain    = DOMAIN_IO,
-        },
-        [MT_NONSHARED_DEVICE] = {
-                .prot_l1   = PMD_TYPE_TABLE,
-                .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_NONSHARED_DEV |
-                                PMD_SECT_AP_WRITE,
-                .domain    = DOMAIN_IO,
-        }
 };
+const struct mem_type *get_mem_type(unsigned int type)
+{
+        return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
+}
 /*
 * Adjust the PMD section entries according to the CPU in use.
 */
@@ -262,20 +266,23 @@ static void __init build_mem_type_table(void)
        }
        /*
-         * Xscale must not have PMD bit 4 set for section mappings.
+         * ARMv5 and lower, bit 4 must be set for page tables.
+         * (was: cache "update-able on write" bit on ARM610)
+         * However, Xscale cores require this bit to be cleared.
         */
-        if (cpu_is_xscale())
+        if (cpu_is_xscale()) {
-                for (i = 0; i < ARRAY_SIZE(mem_types); i++)
+                for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
                        mem_types[i].prot_sect &= ~PMD_BIT4;
+                        mem_types[i].prot_l1 &= ~PMD_BIT4;
-        /*
+                }
-         * ARMv5 and lower, excluding Xscale, bit 4 must be set for
+        } else if (cpu_arch < CPU_ARCH_ARMv6) {
-         * page tables.
+                for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
-         */
-        if (cpu_arch < CPU_ARCH_ARMv6 && !cpu_is_xscale())
-                for (i = 0; i < ARRAY_SIZE(mem_types); i++)
                        if (mem_types[i].prot_l1)
                                mem_types[i].prot_l1 |= PMD_BIT4;
+                        if (mem_types[i].prot_sect)
+                                mem_types[i].prot_sect |= PMD_BIT4;
+                }
+        }
        cp = &cache_policies[cachepolicy];
        kern_pgprot = user_pgprot = cp->pte;
@@ -296,13 +303,6 @@ static void __init build_mem_type_table(void)
         */
        if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
                /*
-                 * bit 4 becomes XN which we must clear for the
-                 * kernel memory mapping.
-                 */
-                mem_types[MT_MEMORY].prot_sect &= ~PMD_SECT_XN;
-                mem_types[MT_ROM].prot_sect &= ~PMD_SECT_XN;
-                /*
                 * Mark cache clean areas and XIP ROM read only
                 * from SVC mode and no access from userspace.
                 */
@@ -368,64 +368,126 @@ static void __init build_mem_type_table(void)
        }
        printk("Memory policy: ECC %sabled, Data cache %s\n",
                ecc_mask ? "en" : "dis", cp->policy);
+        for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
+                struct mem_type *t = &mem_types[i];
+                if (t->prot_l1)
+                        t->prot_l1 |= PMD_DOMAIN(t->domain);
+                if (t->prot_sect)
+                        t->prot_sect |= PMD_DOMAIN(t->domain);
+        }
 }
 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
-/*
+static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
- * Create a SECTION PGD between VIRT and PHYS in domain
+                                  unsigned long end, unsigned long pfn,
- * DOMAIN with protection PROT.  This operates on half-
+                                  const struct mem_type *type)
- * pgdir entry increments.
- */
-static inline void
-alloc_init_section(unsigned long virt, unsigned long phys, int prot)
 {
-        pmd_t *pmdp = pmd_off_k(virt);
+        pte_t *pte;
-        if (virt & (1 << 20))
+        if (pmd_none(*pmd)) {
-                pmdp++;
+                pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
+                __pmd_populate(pmd, __pa(pte) | type->prot_l1);
+        }
-        *pmdp = __pmd(phys | prot);
+        pte = pte_offset_kernel(pmd, addr);
-        flush_pmd_entry(pmdp);
+        do {
+                set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
+                            type->prot_pte_ext);
+                pfn++;
+        } while (pte++, addr += PAGE_SIZE, addr != end);
 }
-/*
+static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
- * Create a SUPER SECTION PGD between VIRT and PHYS with protection PROT
+                                      unsigned long end, unsigned long phys,
- */
+                                      const struct mem_type *type)
-static inline void
-alloc_init_supersection(unsigned long virt, unsigned long phys, int prot)
 {
-        int i;
+        pmd_t *pmd = pmd_offset(pgd, addr);
+        /*
+         * Try a section mapping - end, addr and phys must all be aligned
+         * to a section boundary.  Note that PMDs refer to the individual
+         * L1 entries, whereas PGDs refer to a group of L1 entries making
+         * up one logical pointer to an L2 table.
+         */
+        if (((addr | end | phys) & ~SECTION_MASK) == 0) {
+                pmd_t *p = pmd;
+                if (addr & SECTION_SIZE)
+                        pmd++;
-        for (i = 0; i < 16; i += 1) {
+                do {
-                alloc_init_section(virt, phys, prot | PMD_SECT_SUPER);
+                        *pmd = __pmd(phys | type->prot_sect);
+                        phys += SECTION_SIZE;
+                } while (pmd++, addr += SECTION_SIZE, addr != end);
-                virt += (PGDIR_SIZE / 2);
+                flush_pmd_entry(p);
+        } else {
+                /*
+                 * No need to loop; pte's aren't interested in the
+                 * individual L1 entries.
+                 */
+                alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
        }
 }
-/*
+static void __init create_36bit_mapping(struct map_desc *md,
- * Add a PAGE mapping between VIRT and PHYS in domain
+                                        const struct mem_type *type)
- * DOMAIN with protection PROT.  Note that due to the
- * way we map the PTEs, we must allocate two PTE_SIZE'd
- * blocks - one for the Linux pte table, and one for
- * the hardware pte table.
- */
-static inline void
-alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pgprot_t prot)
 {
-        pmd_t *pmdp = pmd_off_k(virt);
+        unsigned long phys, addr, length, end;
-        pte_t *ptep;
+        pgd_t *pgd;
+        addr = md->virtual;
+        phys = (unsigned long)__pfn_to_phys(md->pfn);
+        length = PAGE_ALIGN(md->length);
+        if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
+                printk(KERN_ERR "MM: CPU does not support supersection "
+                       "mapping for 0x%08llx at 0x%08lx\n",
+                       __pfn_to_phys((u64)md->pfn), addr);
+                return;
+        }
-        if (pmd_none(*pmdp)) {
+        /* N.B. ARMv6 supersections are only defined to work with domain 0.
-                ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
+         *      Since domain assignments can in fact be arbitrary, the
-                                               sizeof(pte_t));
+         *      'domain == 0' check below is required to insure that ARMv6
+         *      supersections are only allocated for domain 0 regardless
+         *      of the actual domain assignments in use.
+         */
+        if (type->domain) {
+                printk(KERN_ERR "MM: invalid domain in supersection "
+                       "mapping for 0x%08llx at 0x%08lx\n",
+                       __pfn_to_phys((u64)md->pfn), addr);
+                return;
+        }
-                __pmd_populate(pmdp, __pa(ptep) | prot_l1);
+        if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
+                printk(KERN_ERR "MM: cannot create mapping for "
+                       "0x%08llx at 0x%08lx invalid alignment\n",
+                       __pfn_to_phys((u64)md->pfn), addr);
+                return;
        }
-        ptep = pte_offset_kernel(pmdp, virt);
-        set_pte_ext(ptep, pfn_pte(phys >> PAGE_SHIFT, prot), 0);
+        /*
+         * Shift bits [35:32] of address into bits [23:20] of PMD
+         * (See ARMv6 spec).
+         */
+        phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
+        pgd = pgd_offset_k(addr);
+        end = addr + length;
+        do {
+                pmd_t *pmd = pmd_offset(pgd, addr);
+                int i;
+                for (i = 0; i < 16; i++)
+                        *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
+                addr += SUPERSECTION_SIZE;
+                phys += SUPERSECTION_SIZE;
+                pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
+        } while (addr != end);
 }
 /*
@@ -437,10 +499,9 @@ alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pg
 */
 void __init create_mapping(struct map_desc *md)
 {
-        unsigned long virt, length;
+        unsigned long phys, addr, length, end;
-        int prot_sect, prot_l1, domain;
+        const struct mem_type *type;
-        pgprot_t prot_pte;
+        pgd_t *pgd;
-        unsigned long off = (u32)__pfn_to_phys(md->pfn);
        if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
                printk(KERN_WARNING "BUG: not creating mapping for "
@@ -456,105 +517,37 @@ void __init create_mapping(struct map_desc *md)
                       __pfn_to_phys((u64)md->pfn), md->virtual);
        }
-        domain    = mem_types[md->type].domain;
+        type = &mem_types[md->type];
-        prot_pte  = __pgprot(mem_types[md->type].prot_pte);
-        prot_l1   = mem_types[md->type].prot_l1 | PMD_DOMAIN(domain);
-        prot_sect = mem_types[md->type].prot_sect | PMD_DOMAIN(domain);
        /*
         * Catch 36-bit addresses
         */
-        if(md->pfn >= 0x100000) {
+        if (md->pfn >= 0x100000) {
-                if(domain) {
+                create_36bit_mapping(md, type);
-                        printk(KERN_ERR "MM: invalid domain in supersection "
+                return;
-                                "mapping for 0x%08llx at 0x%08lx\n",
-                                __pfn_to_phys((u64)md->pfn), md->virtual);
-                        return;
-                }
-                if((md->virtual | md->length | __pfn_to_phys(md->pfn))
-                        & ~SUPERSECTION_MASK) {
-                        printk(KERN_ERR "MM: cannot create mapping for "
-                                "0x%08llx at 0x%08lx invalid alignment\n",
-                                __pfn_to_phys((u64)md->pfn), md->virtual);
-                        return;
-                }
-                /*
-                 * Shift bits [35:32] of address into bits [23:20] of PMD
-                 * (See ARMv6 spec).
-                 */
-                off |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
        }
-        virt   = md->virtual;
+        addr = md->virtual;
-        off   -= virt;
+        phys = (unsigned long)__pfn_to_phys(md->pfn);
-        length = md->length;
+        length = PAGE_ALIGN(md->length);
-        if (mem_types[md->type].prot_l1 == 0 &&
+        if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
-            (virt & 0xfffff || (virt + off) & 0xfffff || (virt + length) & 0xfffff)) {
                printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
                       "be mapped using pages, ignoring.\n",
-                       __pfn_to_phys(md->pfn), md->virtual);
+                       __pfn_to_phys(md->pfn), addr);
                return;
        }
-        while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) {
+        pgd = pgd_offset_k(addr);
-                alloc_init_page(virt, virt + off, prot_l1, prot_pte);
+        end = addr + length;
+        do {
+                unsigned long next = pgd_addr_end(addr, end);
-                virt   += PAGE_SIZE;
+                alloc_init_section(pgd, addr, next, phys, type);
-                length -= PAGE_SIZE;
-        }
-        /* N.B. ARMv6 supersections are only defined to work with domain 0.
-         *      Since domain assignments can in fact be arbitrary, the
-         *      'domain == 0' check below is required to insure that ARMv6
-         *      supersections are only allocated for domain 0 regardless
-         *      of the actual domain assignments in use.
-         */
-        if ((cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())
-                && domain == 0) {
-                /*
-                 * Align to supersection boundary if !high pages.
-                 * High pages have already been checked for proper
-                 * alignment above and they will fail the SUPSERSECTION_MASK
-                 * check because of the way the address is encoded into
-                 * offset.
-                 */
-                if (md->pfn <= 0x100000) {
-                        while ((virt & ~SUPERSECTION_MASK ||
-                                (virt + off) & ~SUPERSECTION_MASK) &&
-                                length >= (PGDIR_SIZE / 2)) {
-                                alloc_init_section(virt, virt + off, prot_sect);
-                                virt   += (PGDIR_SIZE / 2);
-                                length -= (PGDIR_SIZE / 2);
-                        }
-                }
-                while (length >= SUPERSECTION_SIZE) {
+                phys += next - addr;
-                        alloc_init_supersection(virt, virt + off, prot_sect);
+                addr = next;
+        } while (pgd++, addr != end);
-                        virt   += SUPERSECTION_SIZE;
-                        length -= SUPERSECTION_SIZE;
-                }
-        }
-        /*
-         * A section mapping covers half a "pgdir" entry.
-         */
-        while (length >= (PGDIR_SIZE / 2)) {
-                alloc_init_section(virt, virt + off, prot_sect);
-                virt   += (PGDIR_SIZE / 2);
-                length -= (PGDIR_SIZE / 2);
-        }
-        while (length >= PAGE_SIZE) {
-                alloc_init_page(virt, virt + off, prot_l1, prot_pte);
-                virt   += PAGE_SIZE;
-                length -= PAGE_SIZE;
-        }
 }
 /*
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 05818fc0c705..8cd3a60954f0 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -62,21 +62,21 @@ void flush_dcache_page(struct page *page)
 }
 EXPORT_SYMBOL(flush_dcache_page);
-void __iomem *__ioremap_pfn(unsigned long pfn, unsigned long offset,
+void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
-                            size_t size, unsigned long flags)
+                                size_t size, unsigned int mtype)
 {
        if (pfn >= (0x100000000ULL >> PAGE_SHIFT))
                return NULL;
        return (void __iomem *) (offset + (pfn << PAGE_SHIFT));
 }
-EXPORT_SYMBOL(__ioremap_pfn);
+EXPORT_SYMBOL(__arm_ioremap_pfn);
-void __iomem *__ioremap(unsigned long phys_addr, size_t size,
+void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
-                        unsigned long flags)
+                            unsigned int mtype)
 {
        return (void __iomem *)phys_addr;
 }
-EXPORT_SYMBOL(__ioremap);
+EXPORT_SYMBOL(__arm_ioremap);
 void __iounmap(volatile void __iomem *addr)
 {
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 9e2c89eb2115..b13150052a76 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -59,3 +59,15 @@
        .word   \ucset
 #endif
        .endm
+/*
+ * cache_line_size - get the cache line size from the CSIDR register
+ * (available on ARMv7+). It assumes that the CSSR register was configured
+ * to access the L1 data cache CSIDR.
+ */
+        .macro  dcache_line_size, reg, tmp
+        mrc     p15, 1, \tmp, c0, c0, 0         @ read CSIDR
+        and     \tmp, \tmp, #7                  @ cache line size encoding
+        mov     \reg, #16                       @ size offset
+        mov     \reg, \reg, lsl \tmp            @ actual cache line size
+        .endm
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
new file mode 100644
index 000000000000..dd823dd4a374
--- /dev/null
+++ b/arch/arm/mm/proc-v7.S
@@ -0,0 +1,262 @@
+/*
+ *  linux/arch/arm/mm/proc-v7.S
+ *
+ *  Copyright (C) 2001 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This is the "shell" of the ARMv7 processor support.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
+#include <asm/elf.h>
+#include <asm/pgtable-hwdef.h>
+#include <asm/pgtable.h>
+#include "proc-macros.S"
+#define TTB_C           (1 << 0)
+#define TTB_S           (1 << 1)
+#define TTB_RGN_OC_WT   (2 << 3)
+#define TTB_RGN_OC_WB   (3 << 3)
+ENTRY(cpu_v7_proc_init)
+        mov     pc, lr
+ENTRY(cpu_v7_proc_fin)
+        mov     pc, lr
+/*
+ *      cpu_v7_reset(loc)
+ *
+ *      Perform a soft reset of the system.  Put the CPU into the
+ *      same state as it would be if it had been reset, and branch
+ *      to what would be the reset vector.
+ *
+ *      - loc   - location to jump to for soft reset
+ *
+ *      It is assumed that:
+ */
+        .align  5
+ENTRY(cpu_v7_reset)
+        mov     pc, r0
+/*
+ *      cpu_v7_do_idle()
+ *
+ *      Idle the processor (eg, wait for interrupt).
+ *
+ *      IRQs are already disabled.
+ */
+ENTRY(cpu_v7_do_idle)
+        .long   0xe320f003                      @ ARM V7 WFI instruction
+        mov     pc, lr
+ENTRY(cpu_v7_dcache_clean_area)
+#ifndef TLB_CAN_READ_FROM_L1_CACHE
+        dcache_line_size r2, r3
+1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+        add     r0, r0, r2
+        subs    r1, r1, r2
+        bhi     1b
+        dsb
+#endif
+        mov     pc, lr
+/*
+ *      cpu_v7_switch_mm(pgd_phys, tsk)
+ *
+ *      Set the translation table base pointer to be pgd_phys
+ *
+ *      - pgd_phys - physical address of new TTB
+ *
+ *      It is assumed that:
+ *      - we are not using split page tables
+ */
+ENTRY(cpu_v7_switch_mm)
+        mov     r2, #0
+        ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
+        orr     r0, r0, #TTB_RGN_OC_WB          @ mark PTWs outer cacheable, WB
+        mcr     p15, 0, r2, c13, c0, 1          @ set reserved context ID
+        isb
+1:      mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
+        isb
+        mcr     p15, 0, r1, c13, c0, 1          @ set context ID
+        isb
+        mov     pc, lr
+/*
+ *      cpu_v7_set_pte_ext(ptep, pte)
+ *
+ *      Set a level 2 translation table entry.
+ *
+ *      - ptep  - pointer to level 2 translation table entry
+ *                (hardware version is stored at -1024 bytes)
+ *      - pte   - PTE value to store
+ *      - ext   - value for extended PTE bits
+ *
+ *      Permissions:
+ *        YUWD  APX AP1 AP0     SVC     User
+ *        0xxx   0   0   0      no acc  no acc
+ *        100x   1   0   1      r/o     no acc
+ *        10x0   1   0   1      r/o     no acc
+ *        1011   0   0   1      r/w     no acc
+ *        110x   0   1   0      r/w     r/o
+ *        11x0   0   1   0      r/w     r/o
+ *        1111   0   1   1      r/w     r/w
+ */
+ENTRY(cpu_v7_set_pte_ext)
+        str     r1, [r0], #-2048                @ linux version
+        bic     r3, r1, #0x000003f0
+        bic     r3, r3, #0x00000003
+        orr     r3, r3, r2
+        orr     r3, r3, #PTE_EXT_AP0 | 2
+        tst     r1, #L_PTE_WRITE
+        tstne   r1, #L_PTE_DIRTY
+        orreq   r3, r3, #PTE_EXT_APX
+        tst     r1, #L_PTE_USER
+        orrne   r3, r3, #PTE_EXT_AP1
+        tstne   r3, #PTE_EXT_APX
+        bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
+        tst     r1, #L_PTE_YOUNG
+        biceq   r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
+        tst     r1, #L_PTE_EXEC
+        orreq   r3, r3, #PTE_EXT_XN
+        tst     r1, #L_PTE_PRESENT
+        moveq   r3, #0
+        str     r3, [r0]
+        mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
+        mov     pc, lr
+cpu_v7_name:
+        .ascii  "ARMv7 Processor"
+        .align
+        .section ".text.init", #alloc, #execinstr
+/*
+ *      __v7_setup
+ *
+ *      Initialise TLB, Caches, and MMU state ready to switch the MMU
+ *      on.  Return in r0 the new CP15 C1 control register setting.
+ *
+ *      We automatically detect if we have a Harvard cache, and use the
+ *      Harvard cache control instructions insead of the unified cache
+ *      control instructions.
+ *
+ *      This should be able to cover all ARMv7 cores.
+ *
+ *      It is assumed that:
+ *      - cache type register is implemented
+ */
+__v7_setup:
+        adr     r12, __v7_setup_stack           @ the local stack
+        stmia   r12, {r0-r5, r7, r9, r11, lr}
+        bl      v7_flush_dcache_all
+        ldmia   r12, {r0-r5, r7, r9, r11, lr}
+        mov     r10, #0
+#ifdef HARVARD_CACHE
+        mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
+#endif
+        dsb
+        mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
+        mcr     p15, 0, r10, c2, c0, 2          @ TTB control register
+        orr     r4, r4, #TTB_RGN_OC_WB          @ mark PTWs outer cacheable, WB
+        mcr     p15, 0, r4, c2, c0, 0           @ load TTB0
+        mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
+        mov     r10, #0x1f                      @ domains 0, 1 = manager
+        mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
+#ifndef CONFIG_CPU_L2CACHE_DISABLE
+        @ L2 cache configuration in the L2 aux control register
+        mrc     p15, 1, r10, c9, c0, 2
+        bic     r10, r10, #(1 << 16)            @ L2 outer cache
+        mcr     p15, 1, r10, c9, c0, 2
+        @ L2 cache is enabled in the aux control register
+        mrc     p15, 0, r10, c1, c0, 1
+        orr     r10, r10, #2
+        mcr     p15, 0, r10, c1, c0, 1
+#endif
+        mrc     p15, 0, r0, c1, c0, 0           @ read control register
+        ldr     r10, cr1_clear                  @ get mask for bits to clear
+        bic     r0, r0, r10                     @ clear bits them
+        ldr     r10, cr1_set                    @ get mask for bits to set
+        orr     r0, r0, r10                     @ set them
+        mov     pc, lr                          @ return to head.S:__ret
+        /*
+         *         V X F   I D LR
+         * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
+         * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
+         *         0 110       0011 1.00 .111 1101 < we want
+         */
+        .type   cr1_clear, #object
+        .type   cr1_set, #object
+cr1_clear:
+        .word   0x0120c302
+cr1_set:
+        .word   0x00c0387d
+__v7_setup_stack:
+        .space  4 * 11                          @ 11 registers
+        .type   v7_processor_functions, #object
+ENTRY(v7_processor_functions)
+        .word   v7_early_abort
+        .word   cpu_v7_proc_init
+        .word   cpu_v7_proc_fin
+        .word   cpu_v7_reset
+        .word   cpu_v7_do_idle
+        .word   cpu_v7_dcache_clean_area
+        .word   cpu_v7_switch_mm
+        .word   cpu_v7_set_pte_ext
+        .size   v7_processor_functions, . - v7_processor_functions
+        .type   cpu_arch_name, #object
+cpu_arch_name:
+        .asciz  "armv7"
+        .size   cpu_arch_name, . - cpu_arch_name
+        .type   cpu_elf_name, #object
+cpu_elf_name:
+        .asciz  "v7"
+        .size   cpu_elf_name, . - cpu_elf_name
+        .align
+        .section ".proc.info.init", #alloc, #execinstr
+        /*
+         * Match any ARMv7 processor core.
+         */
+        .type   __v7_proc_info, #object
+__v7_proc_info:
+        .long   0x000f0000              @ Required ID value
+        .long   0x000f0000              @ Mask for ID
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_BUFFERABLE | \
+                PMD_SECT_CACHEABLE | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_XN | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        b       __v7_setup
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   cpu_v7_name
+        .long   v7_processor_functions
+        .long   v6wbi_tlb_fns
+        .long   v6_user_fns
+        .long   v7_cache_fns
+        .size   __v7_proc_info, . - __v7_proc_info
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index d29fe927ee9e..c156ddab9a2d 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -584,6 +584,11 @@ cpu_ixp42x_name:
        .asciz  "XScale-IXP42x Family"
        .size   cpu_ixp42x_name, . - cpu_ixp42x_name
+        .type   cpu_ixp43x_name, #object
+cpu_ixp43x_name:
+        .asciz  "XScale-IXP43x Family"
+        .size   cpu_ixp43x_name, . - cpu_ixp43x_name
        .type   cpu_ixp46x_name, #object
 cpu_ixp46x_name:
        .asciz  "XScale-IXP46x Family"
@@ -843,6 +848,29 @@ __ixp42x_proc_info:
        .long   xscale_cache_fns
        .size   __ixp42x_proc_info, . - __ixp42x_proc_info                
+        .type   __ixp43x_proc_info, #object
+__ixp43x_proc_info:
+        .long   0x69054040
+        .long   0xfffffff0
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_BUFFERABLE | \
+                PMD_SECT_CACHEABLE | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        b       __xscale_setup
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   cpu_ixp43x_name
+        .long   xscale_processor_functions
+        .long   v4wbi_tlb_fns
+        .long   xscale_mc_user_fns
+        .long   xscale_cache_fns
+        .size   __ixp43x_proc_info, . - __ixp43x_proc_info
        .type   __ixp46x_proc_info, #object
 __ixp46x_proc_info:
        .long   0x69054200
diff --git a/arch/arm/oprofile/backtrace.c b/arch/arm/oprofile/backtrace.c
index 7c22c12618cc..f5ebf30151fa 100644
--- a/arch/arm/oprofile/backtrace.c
+++ b/arch/arm/oprofile/backtrace.c
@@ -19,6 +19,19 @@
 #include <asm/ptrace.h>
 #include <asm/uaccess.h>
+#include "../kernel/stacktrace.h"
+static int report_trace(struct stackframe *frame, void *d)
+{
+        unsigned int *depth = d;
+        if (*depth) {
+                oprofile_add_trace(frame->lr);
+                (*depth)--;
+        }
+        return *depth == 0;
+}
 /*
 * The registers we're interested in are at the end of the variable
@@ -32,21 +45,6 @@ struct frame_tail {
        unsigned long lr;
 } __attribute__((packed));
-#ifdef CONFIG_FRAME_POINTER
-static struct frame_tail* kernel_backtrace(struct frame_tail *tail)
-{
-        oprofile_add_trace(tail->lr);
-        /* frame pointers should strictly progress back up the stack
-         * (towards higher addresses) */
-        if (tail >= tail->fp)
-                return NULL;
-        return tail->fp-1;
-}
-#endif
 static struct frame_tail* user_backtrace(struct frame_tail *tail)
 {
        struct frame_tail buftail[2];
@@ -67,47 +65,14 @@ static struct frame_tail* user_backtrace(struct frame_tail *tail)
        return buftail[0].fp-1;
 }
-/*
- * |             | /\ Higher addresses
- * |             |
- * --------------- stack base (address of current_thread_info)
- * | thread info |
- * .             .
- * |    stack    |
- * --------------- saved regs->ARM_fp value if valid (frame_tail address)
- * .             .
- * --------------- struct pt_regs stored on stack (struct pt_regs *)
- * |             |
- * .             .
- * |             |
- * --------------- %esp
- * |             |
- * |             | \/ Lower addresses
- *
- * Thus, &pt_regs <-> stack base restricts the valid(ish) fp values
- */
-static int valid_kernel_stack(struct frame_tail *tail, struct pt_regs *regs)
-{
-        unsigned long tailaddr = (unsigned long)tail;
-        unsigned long stack = (unsigned long)regs;
-        unsigned long stack_base = (stack & ~(THREAD_SIZE - 1)) + THREAD_SIZE;
-        return (tailaddr > stack) && (tailaddr < stack_base);
-}
 void arm_backtrace(struct pt_regs * const regs, unsigned int depth)
 {
-        struct frame_tail *tail;
+        struct frame_tail *tail = ((struct frame_tail *) regs->ARM_fp) - 1;
-        tail = ((struct frame_tail *) regs->ARM_fp) - 1;
        if (!user_mode(regs)) {
+                unsigned long base = ((unsigned long)regs) & ~(THREAD_SIZE - 1);
-#ifdef CONFIG_FRAME_POINTER
+                walk_stackframe(regs->ARM_fp, base, base + THREAD_SIZE,
-                while (depth-- && tail && valid_kernel_stack(tail, regs)) {
+                                report_trace, &depth);
-                        tail = kernel_backtrace(tail);
-                }
-#endif
                return;
        }
diff --git a/arch/arm/plat-iop/io.c b/arch/arm/plat-iop/io.c
index f7eccecf2e47..498675d028d0 100644
--- a/arch/arm/plat-iop/io.c
+++ b/arch/arm/plat-iop/io.c
@@ -22,7 +22,7 @@
 #include <asm/io.h>
 void * __iomem __iop3xx_ioremap(unsigned long cookie, size_t size,
-        unsigned long flags)
+        unsigned int mtype)
 {
        void __iomem * retval;
@@ -34,7 +34,7 @@ void * __iomem __iop3xx_ioremap(unsigned long cookie, size_t size,
                retval = (void *) IOP3XX_PMMR_PHYS_TO_VIRT(cookie);
                break;
        default:
-                retval = __ioremap(cookie, size, flags);
+                retval = __arm_ioremap(cookie, size, mtype);
        }
        return retval;
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index b5f6ec35aafb..e2744b7227c5 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -55,7 +55,7 @@ static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where)
 * This routine checks the status of the last configuration cycle.  If an error
 * was detected it returns a 1, else it returns a 0.  The errors being checked
 * are parity, master abort, target abort (master and target).  These types of
- * errors occure during a config cycle where there is no device, like during
+ * errors occur during a config cycle where there is no device, like during
 * the discovery stage.
 */
 static int iop3xx_pci_status(void)
@@ -223,8 +223,111 @@ struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys)
        return pci_scan_bus(sys->busnr, &iop3xx_ops, sys);
 }
+void __init iop3xx_atu_setup(void)
+{
+        /* BAR 0 ( Disabled ) */
+        *IOP3XX_IAUBAR0 = 0x0;
+        *IOP3XX_IABAR0  = 0x0;
+        *IOP3XX_IATVR0  = 0x0;
+        *IOP3XX_IALR0   = 0x0;
+        /* BAR 1 ( Disabled ) */
+        *IOP3XX_IAUBAR1 = 0x0;
+        *IOP3XX_IABAR1  = 0x0;
+        *IOP3XX_IALR1   = 0x0;
+        /* BAR 2 (1:1 mapping with Physical RAM) */
+        /* Set limit and enable */
+        *IOP3XX_IALR2 = ~((u32)IOP3XX_MAX_RAM_SIZE - 1) & ~0x1;
+        *IOP3XX_IAUBAR2 = 0x0;
+        /* Align the inbound bar with the base of memory */
+        *IOP3XX_IABAR2 = PHYS_OFFSET |
+                               PCI_BASE_ADDRESS_MEM_TYPE_64 |
+                               PCI_BASE_ADDRESS_MEM_PREFETCH;
+        *IOP3XX_IATVR2 = PHYS_OFFSET;
+        /* Outbound window 0 */
+        *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_PA;
+        *IOP3XX_OUMWTVR0 = 0;
+        /* Outbound window 1 */
+        *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE;
+        *IOP3XX_OUMWTVR1 = 0;
+        /* BAR 3 ( Disabled ) */
+        *IOP3XX_IAUBAR3 = 0x0;
+        *IOP3XX_IABAR3  = 0x0;
+        *IOP3XX_IATVR3  = 0x0;
+        *IOP3XX_IALR3   = 0x0;
+        /* Setup the I/O Bar
+         */
+        *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_PA;;
+        /* Enable inbound and outbound cycles
+         */
+        *IOP3XX_ATUCMD |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+                               PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
+        *IOP3XX_ATUCR |= IOP3XX_ATUCR_OUT_EN;
+}
+void __init iop3xx_atu_disable(void)
+{
+        *IOP3XX_ATUCMD = 0;
+        *IOP3XX_ATUCR = 0;
+        /* wait for cycles to quiesce */
+        while (*IOP3XX_PCSR & (IOP3XX_PCSR_OUT_Q_BUSY |
+                                     IOP3XX_PCSR_IN_Q_BUSY))
+                cpu_relax();
+        /* BAR 0 ( Disabled ) */
+        *IOP3XX_IAUBAR0 = 0x0;
+        *IOP3XX_IABAR0  = 0x0;
+        *IOP3XX_IATVR0  = 0x0;
+        *IOP3XX_IALR0   = 0x0;
+        /* BAR 1 ( Disabled ) */
+        *IOP3XX_IAUBAR1 = 0x0;
+        *IOP3XX_IABAR1  = 0x0;
+        *IOP3XX_IALR1   = 0x0;
+        /* BAR 2 ( Disabled ) */
+        *IOP3XX_IAUBAR2 = 0x0;
+        *IOP3XX_IABAR2  = 0x0;
+        *IOP3XX_IATVR2  = 0x0;
+        *IOP3XX_IALR2   = 0x0;
+        /* BAR 3 ( Disabled ) */
+        *IOP3XX_IAUBAR3 = 0x0;
+        *IOP3XX_IABAR3  = 0x0;
+        *IOP3XX_IATVR3  = 0x0;
+        *IOP3XX_IALR3   = 0x0;
+        /* Clear the outbound windows */
+        *IOP3XX_OIOWTVR  = 0;
+        /* Outbound window 0 */
+        *IOP3XX_OMWTVR0 = 0;
+        *IOP3XX_OUMWTVR0 = 0;
+        /* Outbound window 1 */
+        *IOP3XX_OMWTVR1 = 0;
+        *IOP3XX_OUMWTVR1 = 0;
+}
+/* Flag to determine whether the ATU is initialized and the PCI bus scanned */
+int init_atu;
 void iop3xx_pci_preinit(void)
 {
+        if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
+                iop3xx_atu_disable();
+                iop3xx_atu_setup();
+        }
        DBG("PCI:  Intel 803xx PCI init code.\n");
        DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
        DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n",
@@ -245,3 +348,38 @@ void iop3xx_pci_preinit(void)
        hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");
 }
+/* allow init_atu to be user overridden */
+static int __init iop3xx_init_atu_setup(char *str)
+{
+        init_atu = IOP3XX_INIT_ATU_DEFAULT;
+        if (str) {
+                while (*str != '\0') {
+                        switch (*str) {
+                        case 'y':
+                        case 'Y':
+                                init_atu = IOP3XX_INIT_ATU_ENABLE;
+                                break;
+                        case 'n':
+                        case 'N':
+                                init_atu = IOP3XX_INIT_ATU_DISABLE;
+                                break;
+                        case ',':
+                        case '=':
+                                break;
+                        default:
+                                printk(KERN_DEBUG "\"%s\" malformed at "
+                                            "character: \'%c\'",
+                                            __FUNCTION__,
+                                            *str);
+                                *(str + 1) = '\0';
+                        }
+                        str++;
+                }
+        }
+        return 1;
+}
+__setup("iop3xx_init_atu", iop3xx_init_atu_setup);
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 16300adfb4de..0cc26da034a1 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -32,22 +32,22 @@ static unsigned long next_jiffy_time;
 unsigned long iop_gettimeoffset(void)
 {
-        unsigned long offset, temp1, temp2;
+        unsigned long offset, temp;
        /* enable cp6, if necessary, to avoid taking the overhead of an
         * undefined instruction trap
         */
        asm volatile (
        "mrc    p15, 0, %0, c15, c1, 0\n\t"
-        "ands   %1, %0, #(1 << 6)\n\t"
+        "tst    %0, #(1 << 6)\n\t"
        "orreq  %0, %0, #(1 << 6)\n\t"
        "mcreq  p15, 0, %0, c15, c1, 0\n\t"
-#ifdef CONFIG_XSCALE
+#ifdef CONFIG_CPU_XSCALE
        "mrceq  p15, 0, %0, c15, c1, 0\n\t"
        "moveq  %0, %0\n\t"
        "subeq  pc, pc, #4\n\t"
 #endif
-        : "=r"(temp1), "=r"(temp2) : : "cc");
+        : "=r"(temp) : : "cc");
        offset = next_jiffy_time - read_tcr1();
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index a347fb5946c7..cfc69f3842fd 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -11,6 +11,7 @@ choice
 config ARCH_OMAP1
        bool "TI OMAP1"
+        select GENERIC_CLOCKEVENTS
 config ARCH_OMAP2
        bool "TI OMAP2"
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index ffb94aa164ad..dd8708ad0a71 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -160,3 +160,53 @@ static int __init omap_add_serial_console(void)
        return add_preferred_console("ttyS", line, opt);
 }
 console_initcall(omap_add_serial_console);
+/*
+ * 32KHz clocksource ... always available, on pretty most chips except
+ * OMAP 730 and 1510.  Other timers could be used as clocksources, with
+ * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
+ * but systems won't necessarily want to spend resources that way.
+ */
+#if defined(CONFIG_ARCH_OMAP16XX)
+#define TIMER_32K_SYNCHRONIZED          0xfffbc410
+#elif defined(CONFIG_ARCH_OMAP24XX)
+#define TIMER_32K_SYNCHRONIZED          0x48004010
+#endif
+#ifdef  TIMER_32K_SYNCHRONIZED
+#include <linux/clocksource.h>
+static cycle_t omap_32k_read(void)
+{
+        return omap_readl(TIMER_32K_SYNCHRONIZED);
+}
+static struct clocksource clocksource_32k = {
+        .name           = "32k_counter",
+        .rating         = 250,
+        .read           = omap_32k_read,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .shift          = 10,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+static int __init omap_init_clocksource_32k(void)
+{
+        static char err[] __initdata = KERN_ERR
+                        "%s: can't register clocksource!\n";
+        if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
+                clocksource_32k.mult = clocksource_hz2mult(32768,
+                                            clocksource_32k.shift);
+                if (clocksource_register(&clocksource_32k))
+                        printk(err, clocksource_32k.name);
+        }
+        return 0;
+}
+arch_initcall(omap_init_clocksource_32k);
+#endif  /* TIMER_32K_SYNCHRONIZED */
diff --git a/arch/arm/plat-omap/timer32k.c b/arch/arm/plat-omap/timer32k.c
index 265310601161..114f87151d60 100644
--- a/arch/arm/plat-omap/timer32k.c
+++ b/arch/arm/plat-omap/timer32k.c
@@ -42,6 +42,8 @@
 #include <linux/spinlock.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 #include <asm/system.h>
 #include <asm/hardware.h>
@@ -80,13 +82,13 @@ struct sys_timer omap_timer;
 #define OMAP1_32K_TIMER_TVR             0x00
 #define OMAP1_32K_TIMER_TCR             0x04
-#define OMAP_32K_TICKS_PER_HZ           (32768 / HZ)
+#define OMAP_32K_TICKS_PER_SEC          (32768)
 /*
 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
 * so with HZ = 128, TVR = 255.
 */
-#define OMAP_32K_TIMER_TICK_PERIOD      ((32768 / HZ) - 1)
+#define OMAP_32K_TIMER_TICK_PERIOD      ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
 #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate)                     \
                                (((nr_jiffies) * (clock_rate)) / HZ)
@@ -142,6 +144,28 @@ static inline void omap_32k_timer_ack_irq(void)
 #endif
+static void omap_32k_timer_set_mode(enum clock_event_mode mode,
+                                    struct clock_event_device *evt)
+{
+        switch (mode) {
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_PERIODIC:
+                omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                omap_32k_timer_stop();
+                break;
+        }
+}
+static struct clock_event_device clockevent_32k_timer = {
+        .name           = "32k-timer",
+        .features       = CLOCK_EVT_FEAT_PERIODIC,
+        .shift          = 32,
+        .set_mode       = omap_32k_timer_set_mode,
+};
 /*
 * The 32KHz synchronized timer is an additional timer on 16xx.
 * It is always running.
@@ -171,15 +195,6 @@ omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
 static unsigned long omap_32k_last_tick = 0;
 /*
- * Returns elapsed usecs since last 32k timer interrupt
- */
-static unsigned long omap_32k_timer_gettimeoffset(void)
-{
-        unsigned long now = omap_32k_sync_timer_read();
-        return omap_32k_ticks_to_usecs(now - omap_32k_last_tick);
-}
-/*
 * Returns current time from boot in nsecs. It's OK for this to wrap
 * around for now, as it's just a relative time stamp.
 */
@@ -188,95 +203,16 @@ unsigned long long sched_clock(void)
        return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read());
 }
-/*
- * Timer interrupt for 32KHz timer. When dynamic tick is enabled, this
- * function is also called from other interrupts to remove latency
- * issues with dynamic tick. In the dynamic tick case, we need to lock
- * with irqsave.
- */
-static inline irqreturn_t _omap_32k_timer_interrupt(int irq, void *dev_id)
-{
-        unsigned long now;
-        omap_32k_timer_ack_irq();
-        now = omap_32k_sync_timer_read();
-        while ((signed long)(now - omap_32k_last_tick)
-                                                >= OMAP_32K_TICKS_PER_HZ) {
-                omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ;
-                timer_tick();
-        }
-        /* Restart timer so we don't drift off due to modulo or dynamic tick.
-         * By default we program the next timer to be continuous to avoid
-         * latencies during high system load. During dynamic tick operation the
-         * continuous timer can be overridden from pm_idle to be longer.
-         */
-        omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now);
-        return IRQ_HANDLED;
-}
-static irqreturn_t omap_32k_timer_handler(int irq, void *dev_id)
-{
-        return _omap_32k_timer_interrupt(irq, dev_id);
-}
 static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
 {
-        unsigned long flags;
+        struct clock_event_device *evt = &clockevent_32k_timer;
+        omap_32k_timer_ack_irq();
-        write_seqlock_irqsave(&xtime_lock, flags);
+        evt->event_handler(evt);
-        _omap_32k_timer_interrupt(irq, dev_id);
-        write_sequnlock_irqrestore(&xtime_lock, flags);
        return IRQ_HANDLED;
 }
-#ifdef CONFIG_NO_IDLE_HZ
-/*
- * Programs the next timer interrupt needed. Called when dynamic tick is
- * enabled, and to reprogram the ticks to skip from pm_idle. Note that
- * we can keep the timer continuous, and don't need to set it to run in
- * one-shot mode. This is because the timer will get reprogrammed again
- * after next interrupt.
- */
-void omap_32k_timer_reprogram(unsigned long next_tick)
-{
-        unsigned long ticks = JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1;
-        unsigned long now = omap_32k_sync_timer_read();
-        unsigned long idled = now - omap_32k_last_tick;
-        if (idled + 1 < ticks)
-                ticks -= idled;
-        else
-                ticks = 1;
-        omap_32k_timer_start(ticks);
-}
-static struct irqaction omap_32k_timer_irq;
-extern struct timer_update_handler timer_update;
-static int omap_32k_timer_enable_dyn_tick(void)
-{
-        /* No need to reprogram timer, just use the next interrupt */
-        return 0;
-}
-static int omap_32k_timer_disable_dyn_tick(void)
-{
-        omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
-        return 0;
-}
-static struct dyn_tick_timer omap_dyn_tick_timer = {
-        .enable         = omap_32k_timer_enable_dyn_tick,
-        .disable        = omap_32k_timer_disable_dyn_tick,
-        .reprogram      = omap_32k_timer_reprogram,
-        .handler        = omap_32k_timer_handler,
-};
-#endif  /* CONFIG_NO_IDLE_HZ */
 static struct irqaction omap_32k_timer_irq = {
        .name           = "32KHz timer",
        .flags          = IRQF_DISABLED | IRQF_TIMER,
@@ -285,13 +221,8 @@ static struct irqaction omap_32k_timer_irq = {
 static __init void omap_init_32k_timer(void)
 {
-#ifdef CONFIG_NO_IDLE_HZ
-        omap_timer.dyn_tick = &omap_dyn_tick_timer;
-#endif
        if (cpu_class_is_omap1())
                setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
-        omap_timer.offset  = omap_32k_timer_gettimeoffset;
        omap_32k_last_tick = omap_32k_sync_timer_read();
 #ifdef CONFIG_ARCH_OMAP2
@@ -308,7 +239,16 @@ static __init void omap_init_32k_timer(void)
        }
 #endif
-        omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
+        clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
+                                           NSEC_PER_SEC,
+                                           clockevent_32k_timer.shift);
+        clockevent_32k_timer.max_delta_ns =
+                clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer);
+        clockevent_32k_timer.min_delta_ns =
+                clockevent_delta2ns(1, &clockevent_32k_timer);
+        clockevent_32k_timer.cpumask = cpumask_of_cpu(0);
+        clockevents_register_device(&clockevent_32k_timer);
 }
 /*
@@ -326,5 +266,4 @@ static void __init omap_timer_init(void)
 struct sys_timer omap_timer = {
        .init           = omap_timer_init,
-        .offset         = NULL,         /* Initialized later */
 };
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c
index d3dc03a7383a..79cda0faec86 100644
--- a/arch/arm/plat-s3c24xx/clock.c
+++ b/arch/arm/plat-s3c24xx/clock.c
@@ -404,6 +404,18 @@ int s3c24xx_register_clock(struct clk *clk)
        return 0;
 }
+int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
+{
+        int fails = 0;
+        for (; nr_clks > 0; nr_clks--, clks++) {
+                if (s3c24xx_register_clock(*clks) < 0)
+                        fails++;
+        }
+        return fails;
+}
 /* initalise all the clocks */
 int __init s3c24xx_setup_clocks(unsigned long xtal,
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 6a2d1070e5a0..8ce4904d3131 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -181,24 +181,6 @@ s3c_lookup_cpu(unsigned long idcode)
        return NULL;
 }
-/* board information */
-static struct s3c24xx_board *board;
-void s3c24xx_set_board(struct s3c24xx_board *b)
-{
-        int i;
-        board = b;
-        if (b->clocks_count != 0) {
-                struct clk **ptr = b->clocks;
-                for (i = b->clocks_count; i > 0; i--, ptr++)
-                        s3c24xx_register_clock(*ptr);
-        }
-}
 /* cpu information */
 static struct cpu_table *cpu;
@@ -342,26 +324,6 @@ static int __init s3c_arch_init(void)
                return ret;
        ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
-        if (ret != 0)
-                return ret;
-        if (board != NULL) {
-                struct platform_device **ptr = board->devices;
-                int i;
-                for (i = 0; i < board->devices_count; i++, ptr++) {
-                        ret = platform_device_register(*ptr);
-                        if (ret) {
-                                printk(KERN_ERR "s3c24xx: failed to add board device %s (%d) @%p\n", (*ptr)->name, ret, *ptr);
-                        }
-                }
-                /* mask any error, we may not need all these board
-                 * devices */
-                ret = 0;
-        }
        return ret;
 }
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 4540a806f522..6f03c9370979 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -44,7 +44,7 @@ static struct kmem_cache *dma_kmem;
 static int dma_channels;
-struct s3c24xx_dma_selection dma_sel;
+static struct s3c24xx_dma_selection dma_sel;
 /* dma channel state information */
 struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
@@ -880,7 +880,7 @@ static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan)
        return 0;
 }
-void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan)
+static void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan)
 {
        unsigned long tmp;
        unsigned int timeout = 0x10000;
@@ -957,8 +957,7 @@ static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan)
        return 0;
 }
-int
+static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
-s3c2410_dma_started(struct s3c2410_dma_chan *chan)
 {
        unsigned long flags;
@@ -1280,7 +1279,7 @@ static void s3c2410_dma_cache_ctor(void *p, struct kmem_cache *c, unsigned long
 /* initialisation code */
-int __init s3c24xx_dma_sysclass_init(void)
+static int __init s3c24xx_dma_sysclass_init(void)
 {
        int ret = sysdev_class_register(&dma_sysclass);
@@ -1292,7 +1291,7 @@ int __init s3c24xx_dma_sysclass_init(void)
 core_initcall(s3c24xx_dma_sysclass_init);
-int __init s3c24xx_dma_sysdev_register(void)
+static int __init s3c24xx_dma_sysdev_register(void)
 {
        struct s3c2410_dma_chan *cp = s3c2410_chans;
        int channel, ret;
@@ -1396,7 +1395,7 @@ static struct s3c24xx_dma_order *dma_order;
 * channel
 */
-struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
+static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
 {
        struct s3c24xx_dma_order_ch *ord = NULL;
        struct s3c24xx_dma_map *ch_map;
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index ecf68d611904..c6b03f8ab260 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -511,11 +511,6 @@ static int s3c2410_pm_enter(suspend_state_t state)
                return -EINVAL;
        }
-        if (state != PM_SUSPEND_MEM) {
-                printk(KERN_ERR PFX "error: only PM_SUSPEND_MEM supported\n");
-                return -EINVAL;
-        }
        /* check if we have anything to wake-up with... bad things seem
         * to happen if you suspend with no wakeup (system will often
         * require a full power-cycle)
@@ -617,30 +612,9 @@ static int s3c2410_pm_enter(suspend_state_t state)
        return 0;
 }
-/*
- * Called after processes are frozen, but before we shut down devices.
- */
-static int s3c2410_pm_prepare(suspend_state_t state)
-{
-        return 0;
-}
-/*
- * Called after devices are re-setup, but before processes are thawed.
- */
-static int s3c2410_pm_finish(suspend_state_t state)
-{
-        return 0;
-}
-/*
- * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
- */
 static struct pm_ops s3c2410_pm_ops = {
-        .pm_disk_mode   = PM_DISK_FIRMWARE,
-        .prepare        = s3c2410_pm_prepare,
        .enter          = s3c2410_pm_enter,
-        .finish         = s3c2410_pm_finish,
+        .valid          = pm_valid_only_mem,
 };
 /* s3c2410_pm_init
diff --git a/arch/arm/vfp/vfpdouble.c b/arch/arm/vfp/vfpdouble.c
index e44b9ed0f81f..74e89f8fb3ab 100644
--- a/arch/arm/vfp/vfpdouble.c
+++ b/arch/arm/vfp/vfpdouble.c
@@ -34,7 +34,6 @@
 #include <linux/bitops.h>
 #include <asm/div64.h>
-#include <asm/ptrace.h>
 #include <asm/vfp.h>
 #include "vfpinstr.h"
diff --git a/arch/arm/vfp/vfpsingle.c b/arch/arm/vfp/vfpsingle.c
index 0221ba3bc799..b252631b406b 100644
--- a/arch/arm/vfp/vfpsingle.c
+++ b/arch/arm/vfp/vfpsingle.c
@@ -34,7 +34,6 @@
 #include <linux/bitops.h>
 #include <asm/div64.h>
-#include <asm/ptrace.h>
 #include <asm/vfp.h>
 #include "vfpinstr.h"