diff options
Diffstat (limited to 'arch/arm')
169 files changed, 9385 insertions, 2199 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 184a6bd54825..83127311a522 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -633,6 +633,14 @@ config ARCH_S3C64XX | |||
| 633 | help | 633 | help |
| 634 | Samsung S3C64XX series based systems | 634 | Samsung S3C64XX series based systems |
| 635 | 635 | ||
| 636 | config ARCH_S5P6440 | ||
| 637 | bool "Samsung S5P6440" | ||
| 638 | select CPU_V6 | ||
| 639 | select GENERIC_GPIO | ||
| 640 | select HAVE_CLK | ||
| 641 | help | ||
| 642 | Samsung S5P6440 CPU based systems | ||
| 643 | |||
| 636 | config ARCH_S5PC1XX | 644 | config ARCH_S5PC1XX |
| 637 | bool "Samsung S5PC1XX" | 645 | bool "Samsung S5PC1XX" |
| 638 | select GENERIC_GPIO | 646 | select GENERIC_GPIO |
| @@ -806,6 +814,7 @@ source "arch/arm/plat-samsung/Kconfig" | |||
| 806 | source "arch/arm/plat-s3c24xx/Kconfig" | 814 | source "arch/arm/plat-s3c24xx/Kconfig" |
| 807 | source "arch/arm/plat-s3c64xx/Kconfig" | 815 | source "arch/arm/plat-s3c64xx/Kconfig" |
| 808 | source "arch/arm/plat-s3c/Kconfig" | 816 | source "arch/arm/plat-s3c/Kconfig" |
| 817 | source "arch/arm/plat-s5p/Kconfig" | ||
| 809 | source "arch/arm/plat-s5pc1xx/Kconfig" | 818 | source "arch/arm/plat-s5pc1xx/Kconfig" |
| 810 | 819 | ||
| 811 | if ARCH_S3C2410 | 820 | if ARCH_S3C2410 |
| @@ -822,6 +831,8 @@ source "arch/arm/mach-s3c6400/Kconfig" | |||
| 822 | source "arch/arm/mach-s3c6410/Kconfig" | 831 | source "arch/arm/mach-s3c6410/Kconfig" |
| 823 | endif | 832 | endif |
| 824 | 833 | ||
| 834 | source "arch/arm/mach-s5p6440/Kconfig" | ||
| 835 | |||
| 825 | source "arch/arm/plat-stmp3xxx/Kconfig" | 836 | source "arch/arm/plat-stmp3xxx/Kconfig" |
| 826 | 837 | ||
| 827 | if ARCH_S5PC1XX | 838 | if ARCH_S5PC1XX |
| @@ -1075,7 +1086,7 @@ source kernel/Kconfig.preempt | |||
| 1075 | config HZ | 1086 | config HZ |
| 1076 | int | 1087 | int |
| 1077 | default 128 if ARCH_L7200 | 1088 | default 128 if ARCH_L7200 |
| 1078 | default 200 if ARCH_EBSA110 || ARCH_S3C2410 | 1089 | default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 |
| 1079 | default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER | 1090 | default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER |
| 1080 | default AT91_TIMER_HZ if ARCH_AT91 | 1091 | default AT91_TIMER_HZ if ARCH_AT91 |
| 1081 | default 100 | 1092 | default 100 |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 356d702c0808..215a5cdd3d7f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
| @@ -162,6 +162,7 @@ machine-$(CONFIG_ARCH_RPC) := rpc | |||
| 162 | machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 | 162 | machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 |
| 163 | machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 | 163 | machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 |
| 164 | machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 | 164 | machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 |
| 165 | machine-$(CONFIG_ARCH_S5P6440) := s5p6440 | ||
| 165 | machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100 | 166 | machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100 |
| 166 | machine-$(CONFIG_ARCH_SA1100) := sa1100 | 167 | machine-$(CONFIG_ARCH_SA1100) := sa1100 |
| 167 | machine-$(CONFIG_ARCH_SHARK) := shark | 168 | machine-$(CONFIG_ARCH_SHARK) := shark |
| @@ -185,6 +186,7 @@ plat-$(CONFIG_PLAT_PXA) := pxa | |||
| 185 | plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c samsung | 186 | plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c samsung |
| 186 | plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c samsung | 187 | plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c samsung |
| 187 | plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c samsung | 188 | plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c samsung |
| 189 | plat-$(CONFIG_PLAT_S5P) := s5p samsung s3c | ||
| 188 | 190 | ||
| 189 | ifeq ($(CONFIG_ARCH_EBSA110),y) | 191 | ifeq ($(CONFIG_ARCH_EBSA110),y) |
| 190 | # This is what happens if you forget the IOCS16 line. | 192 | # This is what happens if you forget the IOCS16 line. |
diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index d2a90eb844a9..ff44bd1615c0 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig | |||
| @@ -184,7 +184,7 @@ CONFIG_S3C24XX_PWM=y | |||
| 184 | CONFIG_S3C24XX_GPIO_EXTRA=0 | 184 | CONFIG_S3C24XX_GPIO_EXTRA=0 |
| 185 | CONFIG_S3C2410_DMA=y | 185 | CONFIG_S3C2410_DMA=y |
| 186 | # CONFIG_S3C2410_DMA_DEBUG is not set | 186 | # CONFIG_S3C2410_DMA_DEBUG is not set |
| 187 | CONFIG_S3C24XX_ADC=y | 187 | CONFIG_S3C_ADC=y |
| 188 | CONFIG_PLAT_S3C=y | 188 | CONFIG_PLAT_S3C=y |
| 189 | CONFIG_CPU_LLSERIAL_S3C2440_ONLY=y | 189 | CONFIG_CPU_LLSERIAL_S3C2440_ONLY=y |
| 190 | CONFIG_CPU_LLSERIAL_S3C2440=y | 190 | CONFIG_CPU_LLSERIAL_S3C2440=y |
| @@ -199,8 +199,8 @@ CONFIG_S3C_BOOT_UART_FORCE_FIFO=y | |||
| 199 | # | 199 | # |
| 200 | # Power management | 200 | # Power management |
| 201 | # | 201 | # |
| 202 | # CONFIG_S3C2410_PM_DEBUG is not set | 202 | # CONFIG_SAMSUNG_PM_DEBUG is not set |
| 203 | # CONFIG_S3C2410_PM_CHECK is not set | 203 | # CONFIG_SAMSUNG_PM_CHECK is not set |
| 204 | CONFIG_S3C_LOWLEVEL_UART_PORT=0 | 204 | CONFIG_S3C_LOWLEVEL_UART_PORT=0 |
| 205 | CONFIG_S3C_GPIO_SPACE=0 | 205 | CONFIG_S3C_GPIO_SPACE=0 |
| 206 | 206 | ||
diff --git a/arch/arm/configs/raumfeld_defconfig b/arch/arm/configs/raumfeld_defconfig new file mode 100644 index 000000000000..acb1a8f30e31 --- /dev/null +++ b/arch/arm/configs/raumfeld_defconfig | |||
| @@ -0,0 +1,1898 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.32-rc5 | ||
| 4 | # Sun Nov 1 21:57:32 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_HAVE_PWM=y | ||
| 8 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 9 | CONFIG_GENERIC_GPIO=y | ||
| 10 | CONFIG_GENERIC_TIME=y | ||
| 11 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 12 | CONFIG_GENERIC_HARDIRQS=y | ||
| 13 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 14 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 18 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 20 | CONFIG_ARCH_HAS_CPUFREQ=y | ||
| 21 | CONFIG_GENERIC_HWEIGHT=y | ||
| 22 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 23 | CONFIG_ARCH_MTD_XIP=y | ||
| 24 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 25 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 26 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 27 | CONFIG_CONSTRUCTORS=y | ||
| 28 | |||
| 29 | # | ||
| 30 | # General setup | ||
| 31 | # | ||
| 32 | CONFIG_EXPERIMENTAL=y | ||
| 33 | CONFIG_BROKEN_ON_SMP=y | ||
| 34 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 35 | CONFIG_LOCALVERSION="" | ||
| 36 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 37 | # CONFIG_SWAP is not set | ||
| 38 | # CONFIG_SYSVIPC is not set | ||
| 39 | # CONFIG_POSIX_MQUEUE is not set | ||
| 40 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 41 | # CONFIG_TASKSTATS is not set | ||
| 42 | # CONFIG_AUDIT is not set | ||
| 43 | |||
| 44 | # | ||
| 45 | # RCU Subsystem | ||
| 46 | # | ||
| 47 | CONFIG_TREE_RCU=y | ||
| 48 | # CONFIG_TREE_PREEMPT_RCU is not set | ||
| 49 | # CONFIG_RCU_TRACE is not set | ||
| 50 | CONFIG_RCU_FANOUT=32 | ||
| 51 | # CONFIG_RCU_FANOUT_EXACT is not set | ||
| 52 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 53 | # CONFIG_IKCONFIG is not set | ||
| 54 | CONFIG_LOG_BUF_SHIFT=17 | ||
| 55 | # CONFIG_GROUP_SCHED is not set | ||
| 56 | # CONFIG_CGROUPS is not set | ||
| 57 | # CONFIG_SYSFS_DEPRECATED_V2 is not set | ||
| 58 | # CONFIG_RELAY is not set | ||
| 59 | CONFIG_NAMESPACES=y | ||
| 60 | # CONFIG_UTS_NS is not set | ||
| 61 | # CONFIG_USER_NS is not set | ||
| 62 | # CONFIG_PID_NS is not set | ||
| 63 | # CONFIG_NET_NS is not set | ||
| 64 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 65 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 66 | CONFIG_SYSCTL=y | ||
| 67 | CONFIG_ANON_INODES=y | ||
| 68 | # CONFIG_EMBEDDED is not set | ||
| 69 | CONFIG_UID16=y | ||
| 70 | CONFIG_SYSCTL_SYSCALL=y | ||
| 71 | CONFIG_KALLSYMS=y | ||
| 72 | # CONFIG_KALLSYMS_ALL is not set | ||
| 73 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 74 | CONFIG_HOTPLUG=y | ||
| 75 | CONFIG_PRINTK=y | ||
| 76 | CONFIG_BUG=y | ||
| 77 | CONFIG_ELF_CORE=y | ||
| 78 | CONFIG_BASE_FULL=y | ||
| 79 | CONFIG_FUTEX=y | ||
| 80 | CONFIG_EPOLL=y | ||
| 81 | CONFIG_SIGNALFD=y | ||
| 82 | CONFIG_TIMERFD=y | ||
| 83 | CONFIG_EVENTFD=y | ||
| 84 | CONFIG_SHMEM=y | ||
| 85 | CONFIG_AIO=y | ||
| 86 | |||
| 87 | # | ||
| 88 | # Kernel Performance Events And Counters | ||
| 89 | # | ||
| 90 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 91 | CONFIG_SLUB_DEBUG=y | ||
| 92 | CONFIG_COMPAT_BRK=y | ||
| 93 | # CONFIG_SLAB is not set | ||
| 94 | CONFIG_SLUB=y | ||
| 95 | # CONFIG_SLOB is not set | ||
| 96 | # CONFIG_PROFILING is not set | ||
| 97 | CONFIG_HAVE_OPROFILE=y | ||
| 98 | # CONFIG_KPROBES is not set | ||
| 99 | CONFIG_HAVE_KPROBES=y | ||
| 100 | CONFIG_HAVE_KRETPROBES=y | ||
| 101 | CONFIG_HAVE_CLK=y | ||
| 102 | |||
| 103 | # | ||
| 104 | # GCOV-based kernel profiling | ||
| 105 | # | ||
| 106 | CONFIG_SLOW_WORK=y | ||
| 107 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 108 | CONFIG_SLABINFO=y | ||
| 109 | CONFIG_RT_MUTEXES=y | ||
| 110 | CONFIG_BASE_SMALL=0 | ||
| 111 | CONFIG_MODULES=y | ||
| 112 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 113 | CONFIG_MODULE_UNLOAD=y | ||
| 114 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 115 | # CONFIG_MODVERSIONS is not set | ||
| 116 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 117 | CONFIG_BLOCK=y | ||
| 118 | # CONFIG_LBDAF is not set | ||
| 119 | # CONFIG_BLK_DEV_BSG is not set | ||
| 120 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 121 | |||
| 122 | # | ||
| 123 | # IO Schedulers | ||
| 124 | # | ||
| 125 | CONFIG_IOSCHED_NOOP=y | ||
| 126 | CONFIG_IOSCHED_AS=y | ||
| 127 | CONFIG_IOSCHED_DEADLINE=y | ||
| 128 | CONFIG_IOSCHED_CFQ=y | ||
| 129 | # CONFIG_DEFAULT_AS is not set | ||
| 130 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 131 | CONFIG_DEFAULT_CFQ=y | ||
| 132 | # CONFIG_DEFAULT_NOOP is not set | ||
| 133 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 134 | CONFIG_FREEZER=y | ||
| 135 | |||
| 136 | # | ||
| 137 | # System Type | ||
| 138 | # | ||
| 139 | CONFIG_MMU=y | ||
| 140 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 141 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 142 | # CONFIG_ARCH_REALVIEW is not set | ||
| 143 | # CONFIG_ARCH_VERSATILE is not set | ||
| 144 | # CONFIG_ARCH_AT91 is not set | ||
| 145 | # CONFIG_ARCH_CLPS711X is not set | ||
| 146 | # CONFIG_ARCH_GEMINI is not set | ||
| 147 | # CONFIG_ARCH_EBSA110 is not set | ||
| 148 | # CONFIG_ARCH_EP93XX is not set | ||
| 149 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 150 | # CONFIG_ARCH_MXC is not set | ||
| 151 | # CONFIG_ARCH_STMP3XXX is not set | ||
| 152 | # CONFIG_ARCH_NETX is not set | ||
| 153 | # CONFIG_ARCH_H720X is not set | ||
| 154 | # CONFIG_ARCH_NOMADIK is not set | ||
| 155 | # CONFIG_ARCH_IOP13XX is not set | ||
| 156 | # CONFIG_ARCH_IOP32X is not set | ||
| 157 | # CONFIG_ARCH_IOP33X is not set | ||
| 158 | # CONFIG_ARCH_IXP23XX is not set | ||
| 159 | # CONFIG_ARCH_IXP2000 is not set | ||
| 160 | # CONFIG_ARCH_IXP4XX is not set | ||
| 161 | # CONFIG_ARCH_L7200 is not set | ||
| 162 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 163 | # CONFIG_ARCH_LOKI is not set | ||
| 164 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 165 | # CONFIG_ARCH_ORION5X is not set | ||
| 166 | # CONFIG_ARCH_MMP is not set | ||
| 167 | # CONFIG_ARCH_KS8695 is not set | ||
| 168 | # CONFIG_ARCH_NS9XXX is not set | ||
| 169 | # CONFIG_ARCH_W90X900 is not set | ||
| 170 | # CONFIG_ARCH_PNX4008 is not set | ||
| 171 | CONFIG_ARCH_PXA=y | ||
| 172 | # CONFIG_ARCH_MSM is not set | ||
| 173 | # CONFIG_ARCH_RPC is not set | ||
| 174 | # CONFIG_ARCH_SA1100 is not set | ||
| 175 | # CONFIG_ARCH_S3C2410 is not set | ||
| 176 | # CONFIG_ARCH_S3C64XX is not set | ||
| 177 | # CONFIG_ARCH_S5PC1XX is not set | ||
| 178 | # CONFIG_ARCH_SHARK is not set | ||
| 179 | # CONFIG_ARCH_LH7A40X is not set | ||
| 180 | # CONFIG_ARCH_U300 is not set | ||
| 181 | # CONFIG_ARCH_DAVINCI is not set | ||
| 182 | # CONFIG_ARCH_OMAP is not set | ||
| 183 | # CONFIG_ARCH_BCMRING is not set | ||
| 184 | |||
| 185 | # | ||
| 186 | # Intel PXA2xx/PXA3xx Implementations | ||
| 187 | # | ||
| 188 | |||
| 189 | # | ||
| 190 | # Supported PXA3xx Processor Variants | ||
| 191 | # | ||
| 192 | CONFIG_CPU_PXA300=y | ||
| 193 | # CONFIG_CPU_PXA310 is not set | ||
| 194 | CONFIG_CPU_PXA320=y | ||
| 195 | # CONFIG_CPU_PXA930 is not set | ||
| 196 | # CONFIG_CPU_PXA935 is not set | ||
| 197 | # CONFIG_CPU_PXA950 is not set | ||
| 198 | |||
| 199 | # | ||
| 200 | # Intel/Marvell Dev Platforms (sorted by hardware release time) | ||
| 201 | # | ||
| 202 | # CONFIG_ARCH_LUBBOCK is not set | ||
| 203 | # CONFIG_MACH_MAINSTONE is not set | ||
| 204 | # CONFIG_MACH_ZYLONITE is not set | ||
| 205 | # CONFIG_MACH_LITTLETON is not set | ||
| 206 | # CONFIG_MACH_TAVOREVB is not set | ||
| 207 | # CONFIG_MACH_SAAR is not set | ||
| 208 | |||
| 209 | # | ||
| 210 | # Third Party Dev Platforms (sorted by vendor name) | ||
| 211 | # | ||
| 212 | # CONFIG_ARCH_PXA_IDP is not set | ||
| 213 | # CONFIG_ARCH_VIPER is not set | ||
| 214 | # CONFIG_MACH_BALLOON3 is not set | ||
| 215 | # CONFIG_MACH_CSB726 is not set | ||
| 216 | # CONFIG_MACH_ARMCORE is not set | ||
| 217 | # CONFIG_MACH_EM_X270 is not set | ||
| 218 | # CONFIG_MACH_EXEDA is not set | ||
| 219 | # CONFIG_MACH_CM_X300 is not set | ||
| 220 | # CONFIG_ARCH_GUMSTIX is not set | ||
| 221 | # CONFIG_MACH_INTELMOTE2 is not set | ||
| 222 | # CONFIG_MACH_STARGATE2 is not set | ||
| 223 | # CONFIG_MACH_XCEP is not set | ||
| 224 | # CONFIG_TRIZEPS_PXA is not set | ||
| 225 | # CONFIG_MACH_LOGICPD_PXA270 is not set | ||
| 226 | # CONFIG_MACH_PCM027 is not set | ||
| 227 | # CONFIG_MACH_COLIBRI is not set | ||
| 228 | # CONFIG_MACH_COLIBRI300 is not set | ||
| 229 | # CONFIG_MACH_COLIBRI320 is not set | ||
| 230 | |||
| 231 | # | ||
| 232 | # End-user Products (sorted by vendor name) | ||
| 233 | # | ||
| 234 | # CONFIG_MACH_H4700 is not set | ||
| 235 | # CONFIG_MACH_H5000 is not set | ||
| 236 | # CONFIG_MACH_HIMALAYA is not set | ||
| 237 | # CONFIG_MACH_MAGICIAN is not set | ||
| 238 | # CONFIG_MACH_MIOA701 is not set | ||
| 239 | # CONFIG_PXA_EZX is not set | ||
| 240 | # CONFIG_MACH_MP900C is not set | ||
| 241 | # CONFIG_ARCH_PXA_PALM is not set | ||
| 242 | CONFIG_MACH_RAUMFELD_RC=y | ||
| 243 | CONFIG_MACH_RAUMFELD_CONNECTOR=y | ||
| 244 | CONFIG_MACH_RAUMFELD_PROTO=y | ||
| 245 | CONFIG_MACH_RAUMFELD_SPEAKER=y | ||
| 246 | # CONFIG_PXA_SHARPSL is not set | ||
| 247 | # CONFIG_ARCH_PXA_ESERIES is not set | ||
| 248 | CONFIG_PXA3xx=y | ||
| 249 | CONFIG_PXA_SSP=y | ||
| 250 | CONFIG_PLAT_PXA=y | ||
| 251 | |||
| 252 | # | ||
| 253 | # Processor Type | ||
| 254 | # | ||
| 255 | CONFIG_CPU_32=y | ||
| 256 | CONFIG_CPU_XSC3=y | ||
| 257 | CONFIG_CPU_32v5=y | ||
| 258 | CONFIG_CPU_ABRT_EV5T=y | ||
| 259 | CONFIG_CPU_PABRT_LEGACY=y | ||
| 260 | CONFIG_CPU_CACHE_VIVT=y | ||
| 261 | CONFIG_CPU_TLB_V4WBI=y | ||
| 262 | CONFIG_CPU_CP15=y | ||
| 263 | CONFIG_CPU_CP15_MMU=y | ||
| 264 | CONFIG_IO_36=y | ||
| 265 | |||
| 266 | # | ||
| 267 | # Processor Features | ||
| 268 | # | ||
| 269 | CONFIG_ARM_THUMB=y | ||
| 270 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 271 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
| 272 | CONFIG_OUTER_CACHE=y | ||
| 273 | CONFIG_CACHE_XSC3L2=y | ||
| 274 | CONFIG_ARM_L1_CACHE_SHIFT=5 | ||
| 275 | CONFIG_IWMMXT=y | ||
| 276 | CONFIG_COMMON_CLKDEV=y | ||
| 277 | |||
| 278 | # | ||
| 279 | # Bus support | ||
| 280 | # | ||
| 281 | # CONFIG_PCI_SYSCALL is not set | ||
| 282 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 283 | # CONFIG_PCCARD is not set | ||
| 284 | |||
| 285 | # | ||
| 286 | # Kernel Features | ||
| 287 | # | ||
| 288 | CONFIG_TICK_ONESHOT=y | ||
| 289 | CONFIG_NO_HZ=y | ||
| 290 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 291 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 292 | CONFIG_VMSPLIT_3G=y | ||
| 293 | # CONFIG_VMSPLIT_2G is not set | ||
| 294 | # CONFIG_VMSPLIT_1G is not set | ||
| 295 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 296 | CONFIG_PREEMPT_NONE=y | ||
| 297 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
| 298 | # CONFIG_PREEMPT is not set | ||
| 299 | CONFIG_HZ=100 | ||
| 300 | CONFIG_AEABI=y | ||
| 301 | # CONFIG_OABI_COMPAT is not set | ||
| 302 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 303 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 304 | # CONFIG_HIGHMEM is not set | ||
| 305 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 306 | CONFIG_FLATMEM_MANUAL=y | ||
| 307 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 308 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 309 | CONFIG_FLATMEM=y | ||
| 310 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 311 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 312 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 313 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 314 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 315 | CONFIG_VIRT_TO_BUS=y | ||
| 316 | CONFIG_HAVE_MLOCK=y | ||
| 317 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 318 | # CONFIG_KSM is not set | ||
| 319 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
| 320 | CONFIG_ALIGNMENT_TRAP=y | ||
| 321 | # CONFIG_UACCESS_WITH_MEMCPY is not set | ||
| 322 | |||
| 323 | # | ||
| 324 | # Boot options | ||
| 325 | # | ||
| 326 | CONFIG_ZBOOT_ROM_TEXT=0 | ||
| 327 | CONFIG_ZBOOT_ROM_BSS=0 | ||
| 328 | CONFIG_CMDLINE="console=ttyS0,115200 rw" | ||
| 329 | # CONFIG_XIP_KERNEL is not set | ||
| 330 | # CONFIG_KEXEC is not set | ||
| 331 | |||
| 332 | # | ||
| 333 | # CPU Power Management | ||
| 334 | # | ||
| 335 | CONFIG_CPU_FREQ=y | ||
| 336 | CONFIG_CPU_FREQ_TABLE=y | ||
| 337 | # CONFIG_CPU_FREQ_DEBUG is not set | ||
| 338 | CONFIG_CPU_FREQ_STAT=y | ||
| 339 | # CONFIG_CPU_FREQ_STAT_DETAILS is not set | ||
| 340 | CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y | ||
| 341 | # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set | ||
| 342 | # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set | ||
| 343 | # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set | ||
| 344 | # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set | ||
| 345 | CONFIG_CPU_FREQ_GOV_PERFORMANCE=y | ||
| 346 | # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set | ||
| 347 | # CONFIG_CPU_FREQ_GOV_USERSPACE is not set | ||
| 348 | # CONFIG_CPU_FREQ_GOV_ONDEMAND is not set | ||
| 349 | # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set | ||
| 350 | CONFIG_CPU_IDLE=y | ||
| 351 | CONFIG_CPU_IDLE_GOV_LADDER=y | ||
| 352 | CONFIG_CPU_IDLE_GOV_MENU=y | ||
| 353 | |||
| 354 | # | ||
| 355 | # Floating point emulation | ||
| 356 | # | ||
| 357 | |||
| 358 | # | ||
| 359 | # At least one emulation must be selected | ||
| 360 | # | ||
| 361 | |||
| 362 | # | ||
| 363 | # Userspace binary formats | ||
| 364 | # | ||
| 365 | CONFIG_BINFMT_ELF=y | ||
| 366 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 367 | CONFIG_HAVE_AOUT=y | ||
| 368 | # CONFIG_BINFMT_AOUT is not set | ||
| 369 | # CONFIG_BINFMT_MISC is not set | ||
| 370 | |||
| 371 | # | ||
| 372 | # Power management options | ||
| 373 | # | ||
| 374 | CONFIG_PM=y | ||
| 375 | # CONFIG_PM_DEBUG is not set | ||
| 376 | CONFIG_PM_SLEEP=y | ||
| 377 | CONFIG_SUSPEND=y | ||
| 378 | CONFIG_SUSPEND_FREEZER=y | ||
| 379 | CONFIG_APM_EMULATION=y | ||
| 380 | # CONFIG_PM_RUNTIME is not set | ||
| 381 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 382 | CONFIG_NET=y | ||
| 383 | |||
| 384 | # | ||
| 385 | # Networking options | ||
| 386 | # | ||
| 387 | CONFIG_PACKET=y | ||
| 388 | CONFIG_PACKET_MMAP=y | ||
| 389 | CONFIG_UNIX=y | ||
| 390 | CONFIG_XFRM=y | ||
| 391 | # CONFIG_XFRM_USER is not set | ||
| 392 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 393 | # CONFIG_XFRM_MIGRATE is not set | ||
| 394 | # CONFIG_XFRM_STATISTICS is not set | ||
| 395 | # CONFIG_NET_KEY is not set | ||
| 396 | CONFIG_INET=y | ||
| 397 | CONFIG_IP_MULTICAST=y | ||
| 398 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 399 | CONFIG_IP_FIB_HASH=y | ||
| 400 | CONFIG_IP_PNP=y | ||
| 401 | # CONFIG_IP_PNP_DHCP is not set | ||
| 402 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 403 | # CONFIG_IP_PNP_RARP is not set | ||
| 404 | # CONFIG_NET_IPIP is not set | ||
| 405 | # CONFIG_NET_IPGRE is not set | ||
| 406 | # CONFIG_IP_MROUTE is not set | ||
| 407 | # CONFIG_ARPD is not set | ||
| 408 | CONFIG_SYN_COOKIES=y | ||
| 409 | # CONFIG_INET_AH is not set | ||
| 410 | # CONFIG_INET_ESP is not set | ||
| 411 | # CONFIG_INET_IPCOMP is not set | ||
| 412 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 413 | CONFIG_INET_TUNNEL=y | ||
| 414 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 415 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 416 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 417 | # CONFIG_INET_LRO is not set | ||
| 418 | CONFIG_INET_DIAG=y | ||
| 419 | CONFIG_INET_TCP_DIAG=y | ||
| 420 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 421 | CONFIG_TCP_CONG_CUBIC=y | ||
| 422 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 423 | # CONFIG_TCP_MD5SIG is not set | ||
| 424 | CONFIG_IPV6=y | ||
| 425 | # CONFIG_IPV6_PRIVACY is not set | ||
| 426 | # CONFIG_IPV6_ROUTER_PREF is not set | ||
| 427 | # CONFIG_IPV6_OPTIMISTIC_DAD is not set | ||
| 428 | # CONFIG_INET6_AH is not set | ||
| 429 | # CONFIG_INET6_ESP is not set | ||
| 430 | # CONFIG_INET6_IPCOMP is not set | ||
| 431 | # CONFIG_IPV6_MIP6 is not set | ||
| 432 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 433 | # CONFIG_INET6_TUNNEL is not set | ||
| 434 | CONFIG_INET6_XFRM_MODE_TRANSPORT=y | ||
| 435 | CONFIG_INET6_XFRM_MODE_TUNNEL=y | ||
| 436 | CONFIG_INET6_XFRM_MODE_BEET=y | ||
| 437 | # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set | ||
| 438 | CONFIG_IPV6_SIT=y | ||
| 439 | CONFIG_IPV6_NDISC_NODETYPE=y | ||
| 440 | # CONFIG_IPV6_TUNNEL is not set | ||
| 441 | # CONFIG_IPV6_MULTIPLE_TABLES is not set | ||
| 442 | # CONFIG_IPV6_MROUTE is not set | ||
| 443 | # CONFIG_NETWORK_SECMARK is not set | ||
| 444 | # CONFIG_NETFILTER is not set | ||
| 445 | # CONFIG_IP_DCCP is not set | ||
| 446 | # CONFIG_IP_SCTP is not set | ||
| 447 | # CONFIG_RDS is not set | ||
| 448 | # CONFIG_TIPC is not set | ||
| 449 | # CONFIG_ATM is not set | ||
| 450 | # CONFIG_BRIDGE is not set | ||
| 451 | # CONFIG_NET_DSA is not set | ||
| 452 | # CONFIG_VLAN_8021Q is not set | ||
| 453 | # CONFIG_DECNET is not set | ||
| 454 | # CONFIG_LLC2 is not set | ||
| 455 | # CONFIG_IPX is not set | ||
| 456 | # CONFIG_ATALK is not set | ||
| 457 | # CONFIG_X25 is not set | ||
| 458 | # CONFIG_LAPB is not set | ||
| 459 | # CONFIG_ECONET is not set | ||
| 460 | # CONFIG_WAN_ROUTER is not set | ||
| 461 | # CONFIG_PHONET is not set | ||
| 462 | # CONFIG_IEEE802154 is not set | ||
| 463 | # CONFIG_NET_SCHED is not set | ||
| 464 | # CONFIG_DCB is not set | ||
| 465 | |||
| 466 | # | ||
| 467 | # Network testing | ||
| 468 | # | ||
| 469 | # CONFIG_NET_PKTGEN is not set | ||
| 470 | # CONFIG_HAMRADIO is not set | ||
| 471 | # CONFIG_CAN is not set | ||
| 472 | # CONFIG_IRDA is not set | ||
| 473 | # CONFIG_BT is not set | ||
| 474 | # CONFIG_AF_RXRPC is not set | ||
| 475 | CONFIG_WIRELESS=y | ||
| 476 | CONFIG_CFG80211=y | ||
| 477 | # CONFIG_NL80211_TESTMODE is not set | ||
| 478 | # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set | ||
| 479 | CONFIG_CFG80211_REG_DEBUG=y | ||
| 480 | CONFIG_CFG80211_DEFAULT_PS=y | ||
| 481 | CONFIG_CFG80211_DEFAULT_PS_VALUE=1 | ||
| 482 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 483 | CONFIG_WIRELESS_EXT=y | ||
| 484 | CONFIG_WIRELESS_EXT_SYSFS=y | ||
| 485 | CONFIG_LIB80211=y | ||
| 486 | # CONFIG_LIB80211_DEBUG is not set | ||
| 487 | CONFIG_MAC80211=y | ||
| 488 | CONFIG_MAC80211_RC_MINSTREL=y | ||
| 489 | # CONFIG_MAC80211_RC_DEFAULT_PID is not set | ||
| 490 | CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y | ||
| 491 | CONFIG_MAC80211_RC_DEFAULT="minstrel" | ||
| 492 | # CONFIG_MAC80211_MESH is not set | ||
| 493 | # CONFIG_MAC80211_LEDS is not set | ||
| 494 | # CONFIG_MAC80211_DEBUG_MENU is not set | ||
| 495 | # CONFIG_WIMAX is not set | ||
| 496 | # CONFIG_RFKILL is not set | ||
| 497 | # CONFIG_NET_9P is not set | ||
| 498 | |||
| 499 | # | ||
| 500 | # Device Drivers | ||
| 501 | # | ||
| 502 | |||
| 503 | # | ||
| 504 | # Generic Driver Options | ||
| 505 | # | ||
| 506 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 507 | # CONFIG_DEVTMPFS is not set | ||
| 508 | CONFIG_STANDALONE=y | ||
| 509 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 510 | CONFIG_FW_LOADER=y | ||
| 511 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 512 | CONFIG_EXTRA_FIRMWARE="" | ||
| 513 | # CONFIG_DEBUG_DRIVER is not set | ||
| 514 | # CONFIG_DEBUG_DEVRES is not set | ||
| 515 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 516 | # CONFIG_CONNECTOR is not set | ||
| 517 | CONFIG_MTD=y | ||
| 518 | # CONFIG_MTD_DEBUG is not set | ||
| 519 | # CONFIG_MTD_TESTS is not set | ||
| 520 | CONFIG_MTD_CONCAT=y | ||
| 521 | CONFIG_MTD_PARTITIONS=y | ||
| 522 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 523 | # CONFIG_MTD_CMDLINE_PARTS is not set | ||
| 524 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 525 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 526 | |||
| 527 | # | ||
| 528 | # User Modules And Translation Layers | ||
| 529 | # | ||
| 530 | CONFIG_MTD_CHAR=y | ||
| 531 | CONFIG_MTD_BLKDEVS=y | ||
| 532 | CONFIG_MTD_BLOCK=y | ||
| 533 | # CONFIG_FTL is not set | ||
| 534 | CONFIG_NFTL=y | ||
| 535 | CONFIG_NFTL_RW=y | ||
| 536 | # CONFIG_INFTL is not set | ||
| 537 | # CONFIG_RFD_FTL is not set | ||
| 538 | # CONFIG_SSFDC is not set | ||
| 539 | # CONFIG_MTD_OOPS is not set | ||
| 540 | |||
| 541 | # | ||
| 542 | # RAM/ROM/Flash chip drivers | ||
| 543 | # | ||
| 544 | # CONFIG_MTD_CFI is not set | ||
| 545 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 546 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 547 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 548 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 549 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 550 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 551 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 552 | CONFIG_MTD_CFI_I1=y | ||
| 553 | CONFIG_MTD_CFI_I2=y | ||
| 554 | # CONFIG_MTD_CFI_I4 is not set | ||
| 555 | # CONFIG_MTD_CFI_I8 is not set | ||
| 556 | # CONFIG_MTD_RAM is not set | ||
| 557 | # CONFIG_MTD_ROM is not set | ||
| 558 | # CONFIG_MTD_ABSENT is not set | ||
| 559 | |||
| 560 | # | ||
| 561 | # Mapping drivers for chip access | ||
| 562 | # | ||
| 563 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 564 | # CONFIG_MTD_PLATRAM is not set | ||
| 565 | |||
| 566 | # | ||
| 567 | # Self-contained MTD device drivers | ||
| 568 | # | ||
| 569 | # CONFIG_MTD_DATAFLASH is not set | ||
| 570 | # CONFIG_MTD_M25P80 is not set | ||
| 571 | # CONFIG_MTD_SST25L is not set | ||
| 572 | # CONFIG_MTD_SLRAM is not set | ||
| 573 | # CONFIG_MTD_PHRAM is not set | ||
| 574 | # CONFIG_MTD_MTDRAM is not set | ||
| 575 | CONFIG_MTD_BLOCK2MTD=y | ||
| 576 | |||
| 577 | # | ||
| 578 | # Disk-On-Chip Device Drivers | ||
| 579 | # | ||
| 580 | # CONFIG_MTD_DOC2000 is not set | ||
| 581 | # CONFIG_MTD_DOC2001 is not set | ||
| 582 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 583 | CONFIG_MTD_NAND=y | ||
| 584 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
| 585 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 586 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 587 | # CONFIG_MTD_NAND_H1900 is not set | ||
| 588 | # CONFIG_MTD_NAND_GPIO is not set | ||
| 589 | CONFIG_MTD_NAND_IDS=y | ||
| 590 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 591 | # CONFIG_MTD_NAND_SHARPSL is not set | ||
| 592 | CONFIG_MTD_NAND_PXA3xx=y | ||
| 593 | # CONFIG_MTD_NAND_PXA3xx_BUILTIN is not set | ||
| 594 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 595 | # CONFIG_MTD_NAND_PLATFORM is not set | ||
| 596 | # CONFIG_MTD_ALAUDA is not set | ||
| 597 | # CONFIG_MTD_ONENAND is not set | ||
| 598 | |||
| 599 | # | ||
| 600 | # LPDDR flash memory drivers | ||
| 601 | # | ||
| 602 | # CONFIG_MTD_LPDDR is not set | ||
| 603 | |||
| 604 | # | ||
| 605 | # UBI - Unsorted block images | ||
| 606 | # | ||
| 607 | CONFIG_MTD_UBI=y | ||
| 608 | CONFIG_MTD_UBI_WL_THRESHOLD=4096 | ||
| 609 | CONFIG_MTD_UBI_BEB_RESERVE=1 | ||
| 610 | # CONFIG_MTD_UBI_GLUEBI is not set | ||
| 611 | |||
| 612 | # | ||
| 613 | # UBI debugging options | ||
| 614 | # | ||
| 615 | # CONFIG_MTD_UBI_DEBUG is not set | ||
| 616 | # CONFIG_PARPORT is not set | ||
| 617 | CONFIG_BLK_DEV=y | ||
| 618 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 619 | CONFIG_BLK_DEV_LOOP=y | ||
| 620 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 621 | # CONFIG_BLK_DEV_NBD is not set | ||
| 622 | # CONFIG_BLK_DEV_UB is not set | ||
| 623 | # CONFIG_BLK_DEV_RAM is not set | ||
| 624 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 625 | # CONFIG_ATA_OVER_ETH is not set | ||
| 626 | # CONFIG_MG_DISK is not set | ||
| 627 | CONFIG_MISC_DEVICES=y | ||
| 628 | # CONFIG_ICS932S401 is not set | ||
| 629 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 630 | CONFIG_ISL29003=y | ||
| 631 | CONFIG_TI_DAC7512=y | ||
| 632 | # CONFIG_C2PORT is not set | ||
| 633 | |||
| 634 | # | ||
| 635 | # EEPROM support | ||
| 636 | # | ||
| 637 | # CONFIG_EEPROM_AT24 is not set | ||
| 638 | # CONFIG_EEPROM_AT25 is not set | ||
| 639 | # CONFIG_EEPROM_LEGACY is not set | ||
| 640 | # CONFIG_EEPROM_MAX6875 is not set | ||
| 641 | # CONFIG_EEPROM_93CX6 is not set | ||
| 642 | CONFIG_HAVE_IDE=y | ||
| 643 | # CONFIG_IDE is not set | ||
| 644 | |||
| 645 | # | ||
| 646 | # SCSI device support | ||
| 647 | # | ||
| 648 | # CONFIG_RAID_ATTRS is not set | ||
| 649 | CONFIG_SCSI=y | ||
| 650 | CONFIG_SCSI_DMA=y | ||
| 651 | # CONFIG_SCSI_TGT is not set | ||
| 652 | # CONFIG_SCSI_NETLINK is not set | ||
| 653 | CONFIG_SCSI_PROC_FS=y | ||
| 654 | |||
| 655 | # | ||
| 656 | # SCSI support type (disk, tape, CD-ROM) | ||
| 657 | # | ||
| 658 | CONFIG_BLK_DEV_SD=y | ||
| 659 | # CONFIG_CHR_DEV_ST is not set | ||
| 660 | # CONFIG_CHR_DEV_OSST is not set | ||
| 661 | # CONFIG_BLK_DEV_SR is not set | ||
| 662 | CONFIG_CHR_DEV_SG=y | ||
| 663 | # CONFIG_CHR_DEV_SCH is not set | ||
| 664 | # CONFIG_SCSI_MULTI_LUN is not set | ||
| 665 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 666 | # CONFIG_SCSI_LOGGING is not set | ||
| 667 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 668 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 669 | |||
| 670 | # | ||
| 671 | # SCSI Transports | ||
| 672 | # | ||
| 673 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 674 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 675 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 676 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 677 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 678 | CONFIG_SCSI_LOWLEVEL=y | ||
| 679 | # CONFIG_ISCSI_TCP is not set | ||
| 680 | # CONFIG_LIBFC is not set | ||
| 681 | # CONFIG_LIBFCOE is not set | ||
| 682 | # CONFIG_SCSI_DEBUG is not set | ||
| 683 | # CONFIG_SCSI_DH is not set | ||
| 684 | # CONFIG_SCSI_OSD_INITIATOR is not set | ||
| 685 | # CONFIG_ATA is not set | ||
| 686 | # CONFIG_MD is not set | ||
| 687 | CONFIG_NETDEVICES=y | ||
| 688 | # CONFIG_DUMMY is not set | ||
| 689 | # CONFIG_BONDING is not set | ||
| 690 | # CONFIG_MACVLAN is not set | ||
| 691 | # CONFIG_EQUALIZER is not set | ||
| 692 | # CONFIG_TUN is not set | ||
| 693 | # CONFIG_VETH is not set | ||
| 694 | CONFIG_PHYLIB=y | ||
| 695 | |||
| 696 | # | ||
| 697 | # MII PHY device drivers | ||
| 698 | # | ||
| 699 | # CONFIG_MARVELL_PHY is not set | ||
| 700 | # CONFIG_DAVICOM_PHY is not set | ||
| 701 | # CONFIG_QSEMI_PHY is not set | ||
| 702 | # CONFIG_LXT_PHY is not set | ||
| 703 | # CONFIG_CICADA_PHY is not set | ||
| 704 | # CONFIG_VITESSE_PHY is not set | ||
| 705 | # CONFIG_SMSC_PHY is not set | ||
| 706 | # CONFIG_BROADCOM_PHY is not set | ||
| 707 | # CONFIG_ICPLUS_PHY is not set | ||
| 708 | # CONFIG_REALTEK_PHY is not set | ||
| 709 | # CONFIG_NATIONAL_PHY is not set | ||
| 710 | # CONFIG_STE10XP is not set | ||
| 711 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 712 | # CONFIG_FIXED_PHY is not set | ||
| 713 | # CONFIG_MDIO_BITBANG is not set | ||
| 714 | CONFIG_NET_ETHERNET=y | ||
| 715 | CONFIG_MII=y | ||
| 716 | # CONFIG_AX88796 is not set | ||
| 717 | # CONFIG_SMC91X is not set | ||
| 718 | # CONFIG_DM9000 is not set | ||
| 719 | # CONFIG_ENC28J60 is not set | ||
| 720 | # CONFIG_ETHOC is not set | ||
| 721 | # CONFIG_SMC911X is not set | ||
| 722 | CONFIG_SMSC911X=y | ||
| 723 | # CONFIG_DNET is not set | ||
| 724 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 725 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 726 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 727 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 728 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 729 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 730 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 731 | # CONFIG_B44 is not set | ||
| 732 | # CONFIG_KS8842 is not set | ||
| 733 | # CONFIG_KS8851 is not set | ||
| 734 | # CONFIG_KS8851_MLL is not set | ||
| 735 | # CONFIG_NETDEV_1000 is not set | ||
| 736 | # CONFIG_NETDEV_10000 is not set | ||
| 737 | CONFIG_WLAN=y | ||
| 738 | # CONFIG_WLAN_PRE80211 is not set | ||
| 739 | CONFIG_WLAN_80211=y | ||
| 740 | CONFIG_LIBERTAS=y | ||
| 741 | # CONFIG_LIBERTAS_USB is not set | ||
| 742 | CONFIG_LIBERTAS_SDIO=m | ||
| 743 | # CONFIG_LIBERTAS_SPI is not set | ||
| 744 | # CONFIG_LIBERTAS_DEBUG is not set | ||
| 745 | # CONFIG_LIBERTAS_THINFIRM is not set | ||
| 746 | # CONFIG_AT76C50X_USB is not set | ||
| 747 | # CONFIG_USB_ZD1201 is not set | ||
| 748 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
| 749 | # CONFIG_RTL8187 is not set | ||
| 750 | # CONFIG_MAC80211_HWSIM is not set | ||
| 751 | # CONFIG_P54_COMMON is not set | ||
| 752 | # CONFIG_ATH_COMMON is not set | ||
| 753 | # CONFIG_HOSTAP is not set | ||
| 754 | # CONFIG_B43 is not set | ||
| 755 | # CONFIG_B43LEGACY is not set | ||
| 756 | # CONFIG_ZD1211RW is not set | ||
| 757 | # CONFIG_RT2X00 is not set | ||
| 758 | # CONFIG_WL12XX is not set | ||
| 759 | # CONFIG_IWM is not set | ||
| 760 | |||
| 761 | # | ||
| 762 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 763 | # | ||
| 764 | |||
| 765 | # | ||
| 766 | # USB Network Adapters | ||
| 767 | # | ||
| 768 | # CONFIG_USB_CATC is not set | ||
| 769 | # CONFIG_USB_KAWETH is not set | ||
| 770 | # CONFIG_USB_PEGASUS is not set | ||
| 771 | # CONFIG_USB_RTL8150 is not set | ||
| 772 | CONFIG_USB_USBNET=y | ||
| 773 | # CONFIG_USB_NET_AX8817X is not set | ||
| 774 | CONFIG_USB_NET_CDCETHER=y | ||
| 775 | # CONFIG_USB_NET_CDC_EEM is not set | ||
| 776 | # CONFIG_USB_NET_DM9601 is not set | ||
| 777 | # CONFIG_USB_NET_SMSC95XX is not set | ||
| 778 | # CONFIG_USB_NET_GL620A is not set | ||
| 779 | # CONFIG_USB_NET_NET1080 is not set | ||
| 780 | # CONFIG_USB_NET_PLUSB is not set | ||
| 781 | CONFIG_USB_NET_MCS7830=y | ||
| 782 | # CONFIG_USB_NET_RNDIS_HOST is not set | ||
| 783 | # CONFIG_USB_NET_CDC_SUBSET is not set | ||
| 784 | # CONFIG_USB_NET_ZAURUS is not set | ||
| 785 | # CONFIG_USB_NET_INT51X1 is not set | ||
| 786 | # CONFIG_WAN is not set | ||
| 787 | # CONFIG_PPP is not set | ||
| 788 | # CONFIG_SLIP is not set | ||
| 789 | # CONFIG_NETCONSOLE is not set | ||
| 790 | # CONFIG_NETPOLL is not set | ||
| 791 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 792 | # CONFIG_ISDN is not set | ||
| 793 | # CONFIG_PHONE is not set | ||
| 794 | |||
| 795 | # | ||
| 796 | # Input device support | ||
| 797 | # | ||
| 798 | CONFIG_INPUT=y | ||
| 799 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 800 | CONFIG_INPUT_POLLDEV=y | ||
| 801 | |||
| 802 | # | ||
| 803 | # Userland interfaces | ||
| 804 | # | ||
| 805 | CONFIG_INPUT_MOUSEDEV=y | ||
| 806 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
| 807 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 808 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 809 | # CONFIG_INPUT_JOYDEV is not set | ||
| 810 | CONFIG_INPUT_EVDEV=y | ||
| 811 | # CONFIG_INPUT_EVBUG is not set | ||
| 812 | |||
| 813 | # | ||
| 814 | # Input Device Drivers | ||
| 815 | # | ||
| 816 | CONFIG_INPUT_KEYBOARD=y | ||
| 817 | # CONFIG_KEYBOARD_ADP5588 is not set | ||
| 818 | CONFIG_KEYBOARD_ATKBD=y | ||
| 819 | # CONFIG_QT2160 is not set | ||
| 820 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 821 | CONFIG_KEYBOARD_GPIO=y | ||
| 822 | # CONFIG_KEYBOARD_MATRIX is not set | ||
| 823 | # CONFIG_KEYBOARD_LM8323 is not set | ||
| 824 | # CONFIG_KEYBOARD_MAX7359 is not set | ||
| 825 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 826 | # CONFIG_KEYBOARD_OPENCORES is not set | ||
| 827 | # CONFIG_KEYBOARD_PXA27x is not set | ||
| 828 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 829 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 830 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 831 | # CONFIG_INPUT_MOUSE is not set | ||
| 832 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 833 | # CONFIG_INPUT_TABLET is not set | ||
| 834 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 835 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
| 836 | # CONFIG_TOUCHSCREEN_AD7877 is not set | ||
| 837 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | ||
| 838 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set | ||
| 839 | # CONFIG_TOUCHSCREEN_AD7879 is not set | ||
| 840 | CONFIG_TOUCHSCREEN_EETI=m | ||
| 841 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 842 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
| 843 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
| 844 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 845 | # CONFIG_TOUCHSCREEN_MCS5000 is not set | ||
| 846 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
| 847 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 848 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
| 849 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
| 850 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
| 851 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
| 852 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
| 853 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 854 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 855 | # CONFIG_TOUCHSCREEN_W90X900 is not set | ||
| 856 | CONFIG_INPUT_MISC=y | ||
| 857 | # CONFIG_INPUT_ATI_REMOTE is not set | ||
| 858 | # CONFIG_INPUT_ATI_REMOTE2 is not set | ||
| 859 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | ||
| 860 | # CONFIG_INPUT_POWERMATE is not set | ||
| 861 | # CONFIG_INPUT_YEALINK is not set | ||
| 862 | # CONFIG_INPUT_CM109 is not set | ||
| 863 | # CONFIG_INPUT_UINPUT is not set | ||
| 864 | CONFIG_INPUT_GPIO_ROTARY_ENCODER=y | ||
| 865 | |||
| 866 | # | ||
| 867 | # Hardware I/O ports | ||
| 868 | # | ||
| 869 | CONFIG_SERIO=y | ||
| 870 | CONFIG_SERIO_SERPORT=y | ||
| 871 | CONFIG_SERIO_LIBPS2=y | ||
| 872 | # CONFIG_SERIO_RAW is not set | ||
| 873 | # CONFIG_GAMEPORT is not set | ||
| 874 | |||
| 875 | # | ||
| 876 | # Character devices | ||
| 877 | # | ||
| 878 | CONFIG_VT=y | ||
| 879 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 880 | CONFIG_VT_CONSOLE=y | ||
| 881 | CONFIG_HW_CONSOLE=y | ||
| 882 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 883 | CONFIG_DEVKMEM=y | ||
| 884 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 885 | |||
| 886 | # | ||
| 887 | # Serial drivers | ||
| 888 | # | ||
| 889 | # CONFIG_SERIAL_8250 is not set | ||
| 890 | |||
| 891 | # | ||
| 892 | # Non-8250 serial port support | ||
| 893 | # | ||
| 894 | # CONFIG_SERIAL_MAX3100 is not set | ||
| 895 | CONFIG_SERIAL_PXA=y | ||
| 896 | CONFIG_SERIAL_PXA_CONSOLE=y | ||
| 897 | CONFIG_SERIAL_CORE=y | ||
| 898 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 899 | CONFIG_UNIX98_PTYS=y | ||
| 900 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 901 | CONFIG_LEGACY_PTYS=y | ||
| 902 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 903 | # CONFIG_IPMI_HANDLER is not set | ||
| 904 | CONFIG_HW_RANDOM=y | ||
| 905 | # CONFIG_HW_RANDOM_TIMERIOMEM is not set | ||
| 906 | # CONFIG_R3964 is not set | ||
| 907 | # CONFIG_RAW_DRIVER is not set | ||
| 908 | # CONFIG_TCG_TPM is not set | ||
| 909 | CONFIG_I2C=y | ||
| 910 | CONFIG_I2C_BOARDINFO=y | ||
| 911 | CONFIG_I2C_COMPAT=y | ||
| 912 | CONFIG_I2C_CHARDEV=y | ||
| 913 | CONFIG_I2C_HELPER_AUTO=y | ||
| 914 | |||
| 915 | # | ||
| 916 | # I2C Hardware Bus support | ||
| 917 | # | ||
| 918 | |||
| 919 | # | ||
| 920 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 921 | # | ||
| 922 | # CONFIG_I2C_DESIGNWARE is not set | ||
| 923 | # CONFIG_I2C_GPIO is not set | ||
| 924 | # CONFIG_I2C_OCORES is not set | ||
| 925 | CONFIG_I2C_PXA=y | ||
| 926 | # CONFIG_I2C_PXA_SLAVE is not set | ||
| 927 | # CONFIG_I2C_SIMTEC is not set | ||
| 928 | |||
| 929 | # | ||
| 930 | # External I2C/SMBus adapter drivers | ||
| 931 | # | ||
| 932 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 933 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 934 | # CONFIG_I2C_TINY_USB is not set | ||
| 935 | |||
| 936 | # | ||
| 937 | # Other I2C/SMBus bus drivers | ||
| 938 | # | ||
| 939 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 940 | # CONFIG_I2C_STUB is not set | ||
| 941 | |||
| 942 | # | ||
| 943 | # Miscellaneous I2C Chip support | ||
| 944 | # | ||
| 945 | # CONFIG_DS1682 is not set | ||
| 946 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 947 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 948 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 949 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 950 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 951 | CONFIG_SPI=y | ||
| 952 | CONFIG_SPI_DEBUG=y | ||
| 953 | CONFIG_SPI_MASTER=y | ||
| 954 | |||
| 955 | # | ||
| 956 | # SPI Master Controller Drivers | ||
| 957 | # | ||
| 958 | CONFIG_SPI_BITBANG=y | ||
| 959 | CONFIG_SPI_GPIO=y | ||
| 960 | # CONFIG_SPI_PXA2XX is not set | ||
| 961 | |||
| 962 | # | ||
| 963 | # SPI Protocol Masters | ||
| 964 | # | ||
| 965 | CONFIG_SPI_SPIDEV=y | ||
| 966 | # CONFIG_SPI_TLE62X0 is not set | ||
| 967 | |||
| 968 | # | ||
| 969 | # PPS support | ||
| 970 | # | ||
| 971 | # CONFIG_PPS is not set | ||
| 972 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 973 | CONFIG_GPIOLIB=y | ||
| 974 | CONFIG_DEBUG_GPIO=y | ||
| 975 | # CONFIG_GPIO_SYSFS is not set | ||
| 976 | |||
| 977 | # | ||
| 978 | # Memory mapped GPIO expanders: | ||
| 979 | # | ||
| 980 | |||
| 981 | # | ||
| 982 | # I2C GPIO expanders: | ||
| 983 | # | ||
| 984 | # CONFIG_GPIO_MAX732X is not set | ||
| 985 | # CONFIG_GPIO_PCA953X is not set | ||
| 986 | # CONFIG_GPIO_PCF857X is not set | ||
| 987 | |||
| 988 | # | ||
| 989 | # PCI GPIO expanders: | ||
| 990 | # | ||
| 991 | |||
| 992 | # | ||
| 993 | # SPI GPIO expanders: | ||
| 994 | # | ||
| 995 | # CONFIG_GPIO_MAX7301 is not set | ||
| 996 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 997 | # CONFIG_GPIO_MC33880 is not set | ||
| 998 | |||
| 999 | # | ||
| 1000 | # AC97 GPIO expanders: | ||
| 1001 | # | ||
| 1002 | CONFIG_W1=m | ||
| 1003 | |||
| 1004 | # | ||
| 1005 | # 1-wire Bus Masters | ||
| 1006 | # | ||
| 1007 | # CONFIG_W1_MASTER_DS2490 is not set | ||
| 1008 | # CONFIG_W1_MASTER_DS2482 is not set | ||
| 1009 | # CONFIG_W1_MASTER_DS1WM is not set | ||
| 1010 | CONFIG_W1_MASTER_GPIO=m | ||
| 1011 | |||
| 1012 | # | ||
| 1013 | # 1-wire Slaves | ||
| 1014 | # | ||
| 1015 | # CONFIG_W1_SLAVE_THERM is not set | ||
| 1016 | # CONFIG_W1_SLAVE_SMEM is not set | ||
| 1017 | # CONFIG_W1_SLAVE_DS2431 is not set | ||
| 1018 | # CONFIG_W1_SLAVE_DS2433 is not set | ||
| 1019 | CONFIG_W1_SLAVE_DS2760=m | ||
| 1020 | # CONFIG_W1_SLAVE_BQ27000 is not set | ||
| 1021 | CONFIG_POWER_SUPPLY=y | ||
| 1022 | # CONFIG_POWER_SUPPLY_DEBUG is not set | ||
| 1023 | CONFIG_PDA_POWER=y | ||
| 1024 | # CONFIG_APM_POWER is not set | ||
| 1025 | CONFIG_BATTERY_DS2760=m | ||
| 1026 | # CONFIG_BATTERY_DS2782 is not set | ||
| 1027 | # CONFIG_BATTERY_BQ27x00 is not set | ||
| 1028 | # CONFIG_BATTERY_MAX17040 is not set | ||
| 1029 | CONFIG_HWMON=y | ||
| 1030 | # CONFIG_HWMON_VID is not set | ||
| 1031 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
| 1032 | |||
| 1033 | # | ||
| 1034 | # Native drivers | ||
| 1035 | # | ||
| 1036 | # CONFIG_SENSORS_AD7414 is not set | ||
| 1037 | # CONFIG_SENSORS_AD7418 is not set | ||
| 1038 | # CONFIG_SENSORS_ADCXX is not set | ||
| 1039 | # CONFIG_SENSORS_ADM1021 is not set | ||
| 1040 | # CONFIG_SENSORS_ADM1025 is not set | ||
| 1041 | # CONFIG_SENSORS_ADM1026 is not set | ||
| 1042 | # CONFIG_SENSORS_ADM1029 is not set | ||
| 1043 | # CONFIG_SENSORS_ADM1031 is not set | ||
| 1044 | # CONFIG_SENSORS_ADM9240 is not set | ||
| 1045 | # CONFIG_SENSORS_ADT7462 is not set | ||
| 1046 | # CONFIG_SENSORS_ADT7470 is not set | ||
| 1047 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 1048 | # CONFIG_SENSORS_ADT7475 is not set | ||
| 1049 | # CONFIG_SENSORS_ATXP1 is not set | ||
| 1050 | # CONFIG_SENSORS_DS1621 is not set | ||
| 1051 | # CONFIG_SENSORS_F71805F is not set | ||
| 1052 | # CONFIG_SENSORS_F71882FG is not set | ||
| 1053 | # CONFIG_SENSORS_F75375S is not set | ||
| 1054 | # CONFIG_SENSORS_G760A is not set | ||
| 1055 | # CONFIG_SENSORS_GL518SM is not set | ||
| 1056 | # CONFIG_SENSORS_GL520SM is not set | ||
| 1057 | # CONFIG_SENSORS_IT87 is not set | ||
| 1058 | # CONFIG_SENSORS_LM63 is not set | ||
| 1059 | # CONFIG_SENSORS_LM70 is not set | ||
| 1060 | # CONFIG_SENSORS_LM75 is not set | ||
| 1061 | # CONFIG_SENSORS_LM77 is not set | ||
| 1062 | # CONFIG_SENSORS_LM78 is not set | ||
| 1063 | # CONFIG_SENSORS_LM80 is not set | ||
| 1064 | # CONFIG_SENSORS_LM83 is not set | ||
| 1065 | # CONFIG_SENSORS_LM85 is not set | ||
| 1066 | # CONFIG_SENSORS_LM87 is not set | ||
| 1067 | # CONFIG_SENSORS_LM90 is not set | ||
| 1068 | # CONFIG_SENSORS_LM92 is not set | ||
| 1069 | # CONFIG_SENSORS_LM93 is not set | ||
| 1070 | # CONFIG_SENSORS_LTC4215 is not set | ||
| 1071 | # CONFIG_SENSORS_LTC4245 is not set | ||
| 1072 | # CONFIG_SENSORS_LM95241 is not set | ||
| 1073 | # CONFIG_SENSORS_MAX1111 is not set | ||
| 1074 | # CONFIG_SENSORS_MAX1619 is not set | ||
| 1075 | # CONFIG_SENSORS_MAX6650 is not set | ||
| 1076 | # CONFIG_SENSORS_PC87360 is not set | ||
| 1077 | # CONFIG_SENSORS_PC87427 is not set | ||
| 1078 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 1079 | # CONFIG_SENSORS_SHT15 is not set | ||
| 1080 | # CONFIG_SENSORS_DME1737 is not set | ||
| 1081 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
| 1082 | # CONFIG_SENSORS_SMSC47M192 is not set | ||
| 1083 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
| 1084 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 1085 | # CONFIG_SENSORS_THMC50 is not set | ||
| 1086 | # CONFIG_SENSORS_TMP401 is not set | ||
| 1087 | # CONFIG_SENSORS_TMP421 is not set | ||
| 1088 | # CONFIG_SENSORS_VT1211 is not set | ||
| 1089 | # CONFIG_SENSORS_W83781D is not set | ||
| 1090 | # CONFIG_SENSORS_W83791D is not set | ||
| 1091 | # CONFIG_SENSORS_W83792D is not set | ||
| 1092 | # CONFIG_SENSORS_W83793 is not set | ||
| 1093 | # CONFIG_SENSORS_W83L785TS is not set | ||
| 1094 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 1095 | # CONFIG_SENSORS_W83627HF is not set | ||
| 1096 | # CONFIG_SENSORS_W83627EHF is not set | ||
| 1097 | CONFIG_SENSORS_LIS3_SPI=y | ||
| 1098 | # CONFIG_THERMAL is not set | ||
| 1099 | # CONFIG_WATCHDOG is not set | ||
| 1100 | CONFIG_SSB_POSSIBLE=y | ||
| 1101 | |||
| 1102 | # | ||
| 1103 | # Sonics Silicon Backplane | ||
| 1104 | # | ||
| 1105 | # CONFIG_SSB is not set | ||
| 1106 | |||
| 1107 | # | ||
| 1108 | # Multifunction device drivers | ||
| 1109 | # | ||
| 1110 | # CONFIG_MFD_CORE is not set | ||
| 1111 | # CONFIG_MFD_SM501 is not set | ||
| 1112 | # CONFIG_MFD_ASIC3 is not set | ||
| 1113 | # CONFIG_HTC_EGPIO is not set | ||
| 1114 | # CONFIG_HTC_PASIC3 is not set | ||
| 1115 | # CONFIG_TPS65010 is not set | ||
| 1116 | # CONFIG_TWL4030_CORE is not set | ||
| 1117 | # CONFIG_MFD_TMIO is not set | ||
| 1118 | # CONFIG_MFD_T7L66XB is not set | ||
| 1119 | # CONFIG_MFD_TC6387XB is not set | ||
| 1120 | # CONFIG_MFD_TC6393XB is not set | ||
| 1121 | # CONFIG_PMIC_DA903X is not set | ||
| 1122 | # CONFIG_MFD_WM8400 is not set | ||
| 1123 | # CONFIG_MFD_WM831X is not set | ||
| 1124 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 1125 | # CONFIG_MFD_PCF50633 is not set | ||
| 1126 | # CONFIG_MFD_MC13783 is not set | ||
| 1127 | # CONFIG_AB3100_CORE is not set | ||
| 1128 | # CONFIG_EZX_PCAP is not set | ||
| 1129 | CONFIG_REGULATOR=y | ||
| 1130 | CONFIG_REGULATOR_DEBUG=y | ||
| 1131 | CONFIG_REGULATOR_FIXED_VOLTAGE=y | ||
| 1132 | # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set | ||
| 1133 | # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set | ||
| 1134 | # CONFIG_REGULATOR_BQ24022 is not set | ||
| 1135 | # CONFIG_REGULATOR_MAX1586 is not set | ||
| 1136 | CONFIG_REGULATOR_MAX8660=y | ||
| 1137 | # CONFIG_REGULATOR_LP3971 is not set | ||
| 1138 | # CONFIG_REGULATOR_TPS65023 is not set | ||
| 1139 | # CONFIG_REGULATOR_TPS6507X is not set | ||
| 1140 | # CONFIG_MEDIA_SUPPORT is not set | ||
| 1141 | |||
| 1142 | # | ||
| 1143 | # Graphics support | ||
| 1144 | # | ||
| 1145 | # CONFIG_VGASTATE is not set | ||
| 1146 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 1147 | CONFIG_FB=y | ||
| 1148 | # CONFIG_FIRMWARE_EDID is not set | ||
| 1149 | # CONFIG_FB_DDC is not set | ||
| 1150 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 1151 | CONFIG_FB_CFB_FILLRECT=y | ||
| 1152 | CONFIG_FB_CFB_COPYAREA=y | ||
| 1153 | CONFIG_FB_CFB_IMAGEBLIT=y | ||
| 1154 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 1155 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 1156 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 1157 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 1158 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 1159 | # CONFIG_FB_SYS_FOPS is not set | ||
| 1160 | # CONFIG_FB_SVGALIB is not set | ||
| 1161 | # CONFIG_FB_MACMODES is not set | ||
| 1162 | # CONFIG_FB_BACKLIGHT is not set | ||
| 1163 | # CONFIG_FB_MODE_HELPERS is not set | ||
| 1164 | # CONFIG_FB_TILEBLITTING is not set | ||
| 1165 | |||
| 1166 | # | ||
| 1167 | # Frame buffer hardware drivers | ||
| 1168 | # | ||
| 1169 | # CONFIG_FB_S1D13XXX is not set | ||
| 1170 | CONFIG_FB_PXA=y | ||
| 1171 | # CONFIG_FB_PXA_OVERLAY is not set | ||
| 1172 | # CONFIG_FB_PXA_SMARTPANEL is not set | ||
| 1173 | # CONFIG_FB_PXA_PARAMETERS is not set | ||
| 1174 | CONFIG_PXA3XX_GCU=y | ||
| 1175 | # CONFIG_FB_MBX is not set | ||
| 1176 | # CONFIG_FB_W100 is not set | ||
| 1177 | # CONFIG_FB_VIRTUAL is not set | ||
| 1178 | # CONFIG_FB_METRONOME is not set | ||
| 1179 | # CONFIG_FB_MB862XX is not set | ||
| 1180 | # CONFIG_FB_BROADSHEET is not set | ||
| 1181 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 1182 | # CONFIG_LCD_CLASS_DEVICE is not set | ||
| 1183 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | ||
| 1184 | # CONFIG_BACKLIGHT_GENERIC is not set | ||
| 1185 | CONFIG_BACKLIGHT_PWM=y | ||
| 1186 | |||
| 1187 | # | ||
| 1188 | # Display device support | ||
| 1189 | # | ||
| 1190 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 1191 | |||
| 1192 | # | ||
| 1193 | # Console display driver support | ||
| 1194 | # | ||
| 1195 | # CONFIG_VGA_CONSOLE is not set | ||
| 1196 | CONFIG_DUMMY_CONSOLE=y | ||
| 1197 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 1198 | # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set | ||
| 1199 | # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set | ||
| 1200 | # CONFIG_FONTS is not set | ||
| 1201 | CONFIG_FONT_8x8=y | ||
| 1202 | CONFIG_FONT_8x16=y | ||
| 1203 | CONFIG_LOGO=y | ||
| 1204 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 1205 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 1206 | # CONFIG_LOGO_LINUX_CLUT224 is not set | ||
| 1207 | CONFIG_LOGO_RAUMFELD_CLUT224=y | ||
| 1208 | CONFIG_SOUND=y | ||
| 1209 | # CONFIG_SOUND_OSS_CORE is not set | ||
| 1210 | CONFIG_SND=y | ||
| 1211 | CONFIG_SND_TIMER=y | ||
| 1212 | CONFIG_SND_PCM=y | ||
| 1213 | CONFIG_SND_JACK=y | ||
| 1214 | # CONFIG_SND_SEQUENCER is not set | ||
| 1215 | # CONFIG_SND_MIXER_OSS is not set | ||
| 1216 | # CONFIG_SND_PCM_OSS is not set | ||
| 1217 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
| 1218 | CONFIG_SND_SUPPORT_OLD_API=y | ||
| 1219 | CONFIG_SND_VERBOSE_PROCFS=y | ||
| 1220 | # CONFIG_SND_VERBOSE_PRINTK is not set | ||
| 1221 | # CONFIG_SND_DEBUG is not set | ||
| 1222 | # CONFIG_SND_RAWMIDI_SEQ is not set | ||
| 1223 | # CONFIG_SND_OPL3_LIB_SEQ is not set | ||
| 1224 | # CONFIG_SND_OPL4_LIB_SEQ is not set | ||
| 1225 | # CONFIG_SND_SBAWE_SEQ is not set | ||
| 1226 | # CONFIG_SND_EMU10K1_SEQ is not set | ||
| 1227 | # CONFIG_SND_DRIVERS is not set | ||
| 1228 | CONFIG_SND_ARM=y | ||
| 1229 | CONFIG_SND_PXA2XX_LIB=y | ||
| 1230 | # CONFIG_SND_PXA2XX_AC97 is not set | ||
| 1231 | CONFIG_SND_SPI=y | ||
| 1232 | # CONFIG_SND_USB is not set | ||
| 1233 | CONFIG_SND_SOC=y | ||
| 1234 | CONFIG_SND_PXA2XX_SOC=y | ||
| 1235 | CONFIG_SND_PXA_SOC_SSP=y | ||
| 1236 | CONFIG_SND_SOC_RAUMFELD=y | ||
| 1237 | CONFIG_SND_SOC_I2C_AND_SPI=y | ||
| 1238 | # CONFIG_SND_SOC_ALL_CODECS is not set | ||
| 1239 | CONFIG_SND_SOC_AK4104=y | ||
| 1240 | CONFIG_SND_SOC_CS4270=y | ||
| 1241 | # CONFIG_SOUND_PRIME is not set | ||
| 1242 | CONFIG_HID_SUPPORT=y | ||
| 1243 | CONFIG_HID=y | ||
| 1244 | # CONFIG_HIDRAW is not set | ||
| 1245 | |||
| 1246 | # | ||
| 1247 | # USB Input Devices | ||
| 1248 | # | ||
| 1249 | CONFIG_USB_HID=y | ||
| 1250 | # CONFIG_HID_PID is not set | ||
| 1251 | # CONFIG_USB_HIDDEV is not set | ||
| 1252 | |||
| 1253 | # | ||
| 1254 | # Special HID drivers | ||
| 1255 | # | ||
| 1256 | CONFIG_HID_A4TECH=y | ||
| 1257 | CONFIG_HID_APPLE=y | ||
| 1258 | CONFIG_HID_BELKIN=y | ||
| 1259 | CONFIG_HID_CHERRY=y | ||
| 1260 | CONFIG_HID_CHICONY=y | ||
| 1261 | CONFIG_HID_CYPRESS=y | ||
| 1262 | CONFIG_HID_DRAGONRISE=y | ||
| 1263 | # CONFIG_DRAGONRISE_FF is not set | ||
| 1264 | CONFIG_HID_EZKEY=y | ||
| 1265 | CONFIG_HID_KYE=y | ||
| 1266 | CONFIG_HID_GYRATION=y | ||
| 1267 | CONFIG_HID_TWINHAN=y | ||
| 1268 | CONFIG_HID_KENSINGTON=y | ||
| 1269 | CONFIG_HID_LOGITECH=y | ||
| 1270 | # CONFIG_LOGITECH_FF is not set | ||
| 1271 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | ||
| 1272 | CONFIG_HID_MICROSOFT=y | ||
| 1273 | CONFIG_HID_MONTEREY=y | ||
| 1274 | CONFIG_HID_NTRIG=y | ||
| 1275 | CONFIG_HID_PANTHERLORD=y | ||
| 1276 | # CONFIG_PANTHERLORD_FF is not set | ||
| 1277 | CONFIG_HID_PETALYNX=y | ||
| 1278 | CONFIG_HID_SAMSUNG=y | ||
| 1279 | CONFIG_HID_SONY=y | ||
| 1280 | CONFIG_HID_SUNPLUS=y | ||
| 1281 | CONFIG_HID_GREENASIA=y | ||
| 1282 | # CONFIG_GREENASIA_FF is not set | ||
| 1283 | CONFIG_HID_SMARTJOYPLUS=y | ||
| 1284 | # CONFIG_SMARTJOYPLUS_FF is not set | ||
| 1285 | CONFIG_HID_TOPSEED=y | ||
| 1286 | CONFIG_HID_THRUSTMASTER=y | ||
| 1287 | # CONFIG_THRUSTMASTER_FF is not set | ||
| 1288 | CONFIG_HID_ZEROPLUS=y | ||
| 1289 | # CONFIG_ZEROPLUS_FF is not set | ||
| 1290 | CONFIG_USB_SUPPORT=y | ||
| 1291 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 1292 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 1293 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 1294 | CONFIG_USB=y | ||
| 1295 | CONFIG_USB_DEBUG=y | ||
| 1296 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 1297 | |||
| 1298 | # | ||
| 1299 | # Miscellaneous USB options | ||
| 1300 | # | ||
| 1301 | # CONFIG_USB_DEVICEFS is not set | ||
| 1302 | CONFIG_USB_DEVICE_CLASS=y | ||
| 1303 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 1304 | # CONFIG_USB_SUSPEND is not set | ||
| 1305 | # CONFIG_USB_OTG is not set | ||
| 1306 | CONFIG_USB_MON=y | ||
| 1307 | # CONFIG_USB_WUSB is not set | ||
| 1308 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1309 | |||
| 1310 | # | ||
| 1311 | # USB Host Controller Drivers | ||
| 1312 | # | ||
| 1313 | # CONFIG_USB_C67X00_HCD is not set | ||
| 1314 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1315 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 1316 | # CONFIG_USB_ISP1760_HCD is not set | ||
| 1317 | # CONFIG_USB_ISP1362_HCD is not set | ||
| 1318 | CONFIG_USB_OHCI_HCD=y | ||
| 1319 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
| 1320 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 1321 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
| 1322 | # CONFIG_USB_SL811_HCD is not set | ||
| 1323 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 1324 | # CONFIG_USB_HWA_HCD is not set | ||
| 1325 | # CONFIG_USB_MUSB_HDRC is not set | ||
| 1326 | |||
| 1327 | # | ||
| 1328 | # USB Device Class drivers | ||
| 1329 | # | ||
| 1330 | # CONFIG_USB_ACM is not set | ||
| 1331 | # CONFIG_USB_PRINTER is not set | ||
| 1332 | # CONFIG_USB_WDM is not set | ||
| 1333 | # CONFIG_USB_TMC is not set | ||
| 1334 | |||
| 1335 | # | ||
| 1336 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may | ||
| 1337 | # | ||
| 1338 | |||
| 1339 | # | ||
| 1340 | # also be needed; see USB_STORAGE Help for more info | ||
| 1341 | # | ||
| 1342 | CONFIG_USB_STORAGE=y | ||
| 1343 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 1344 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 1345 | CONFIG_USB_STORAGE_FREECOM=y | ||
| 1346 | CONFIG_USB_STORAGE_ISD200=y | ||
| 1347 | CONFIG_USB_STORAGE_USBAT=y | ||
| 1348 | CONFIG_USB_STORAGE_SDDR09=y | ||
| 1349 | CONFIG_USB_STORAGE_SDDR55=y | ||
| 1350 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 1351 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 1352 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 1353 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 1354 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 1355 | # CONFIG_USB_LIBUSUAL is not set | ||
| 1356 | |||
| 1357 | # | ||
| 1358 | # USB Imaging devices | ||
| 1359 | # | ||
| 1360 | # CONFIG_USB_MDC800 is not set | ||
| 1361 | # CONFIG_USB_MICROTEK is not set | ||
| 1362 | |||
| 1363 | # | ||
| 1364 | # USB port drivers | ||
| 1365 | # | ||
| 1366 | # CONFIG_USB_SERIAL is not set | ||
| 1367 | |||
| 1368 | # | ||
| 1369 | # USB Miscellaneous drivers | ||
| 1370 | # | ||
| 1371 | # CONFIG_USB_EMI62 is not set | ||
| 1372 | # CONFIG_USB_EMI26 is not set | ||
| 1373 | # CONFIG_USB_ADUTUX is not set | ||
| 1374 | # CONFIG_USB_SEVSEG is not set | ||
| 1375 | # CONFIG_USB_RIO500 is not set | ||
| 1376 | # CONFIG_USB_LEGOTOWER is not set | ||
| 1377 | # CONFIG_USB_LCD is not set | ||
| 1378 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 1379 | # CONFIG_USB_LED is not set | ||
| 1380 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 1381 | # CONFIG_USB_CYTHERM is not set | ||
| 1382 | # CONFIG_USB_IDMOUSE is not set | ||
| 1383 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 1384 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 1385 | # CONFIG_USB_LD is not set | ||
| 1386 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 1387 | # CONFIG_USB_IOWARRIOR is not set | ||
| 1388 | # CONFIG_USB_TEST is not set | ||
| 1389 | # CONFIG_USB_ISIGHTFW is not set | ||
| 1390 | # CONFIG_USB_VST is not set | ||
| 1391 | # CONFIG_USB_GADGET is not set | ||
| 1392 | |||
| 1393 | # | ||
| 1394 | # OTG and related infrastructure | ||
| 1395 | # | ||
| 1396 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1397 | # CONFIG_NOP_USB_XCEIV is not set | ||
| 1398 | CONFIG_MMC=y | ||
| 1399 | # CONFIG_MMC_DEBUG is not set | ||
| 1400 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 1401 | |||
| 1402 | # | ||
| 1403 | # MMC/SD/SDIO Card Drivers | ||
| 1404 | # | ||
| 1405 | CONFIG_MMC_BLOCK=y | ||
| 1406 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 1407 | # CONFIG_SDIO_UART is not set | ||
| 1408 | # CONFIG_MMC_TEST is not set | ||
| 1409 | |||
| 1410 | # | ||
| 1411 | # MMC/SD/SDIO Host Controller Drivers | ||
| 1412 | # | ||
| 1413 | CONFIG_MMC_PXA=m | ||
| 1414 | # CONFIG_MMC_SDHCI is not set | ||
| 1415 | # CONFIG_MMC_AT91 is not set | ||
| 1416 | # CONFIG_MMC_ATMELMCI is not set | ||
| 1417 | # CONFIG_MMC_SPI is not set | ||
| 1418 | # CONFIG_MEMSTICK is not set | ||
| 1419 | CONFIG_NEW_LEDS=y | ||
| 1420 | CONFIG_LEDS_CLASS=y | ||
| 1421 | |||
| 1422 | # | ||
| 1423 | # LED drivers | ||
| 1424 | # | ||
| 1425 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1426 | CONFIG_LEDS_GPIO=y | ||
| 1427 | CONFIG_LEDS_GPIO_PLATFORM=y | ||
| 1428 | # CONFIG_LEDS_LP3944 is not set | ||
| 1429 | # CONFIG_LEDS_PCA955X is not set | ||
| 1430 | # CONFIG_LEDS_DAC124S085 is not set | ||
| 1431 | # CONFIG_LEDS_PWM is not set | ||
| 1432 | # CONFIG_LEDS_BD2802 is not set | ||
| 1433 | CONFIG_LEDS_LT3593=y | ||
| 1434 | |||
| 1435 | # | ||
| 1436 | # LED Triggers | ||
| 1437 | # | ||
| 1438 | CONFIG_LEDS_TRIGGERS=y | ||
| 1439 | # CONFIG_LEDS_TRIGGER_TIMER is not set | ||
| 1440 | # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set | ||
| 1441 | CONFIG_LEDS_TRIGGER_BACKLIGHT=y | ||
| 1442 | # CONFIG_LEDS_TRIGGER_GPIO is not set | ||
| 1443 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | ||
| 1444 | |||
| 1445 | # | ||
| 1446 | # iptables trigger is under Netfilter config (LED target) | ||
| 1447 | # | ||
| 1448 | # CONFIG_ACCESSIBILITY is not set | ||
| 1449 | CONFIG_RTC_LIB=y | ||
| 1450 | CONFIG_RTC_CLASS=y | ||
| 1451 | CONFIG_RTC_HCTOSYS=y | ||
| 1452 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 1453 | # CONFIG_RTC_DEBUG is not set | ||
| 1454 | |||
| 1455 | # | ||
| 1456 | # RTC interfaces | ||
| 1457 | # | ||
| 1458 | CONFIG_RTC_INTF_SYSFS=y | ||
| 1459 | CONFIG_RTC_INTF_PROC=y | ||
| 1460 | CONFIG_RTC_INTF_DEV=y | ||
| 1461 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 1462 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1463 | |||
| 1464 | # | ||
| 1465 | # I2C RTC drivers | ||
| 1466 | # | ||
| 1467 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 1468 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 1469 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 1470 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 1471 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 1472 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 1473 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 1474 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 1475 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 1476 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 1477 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1478 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1479 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1480 | # CONFIG_RTC_DRV_RX8025 is not set | ||
| 1481 | |||
| 1482 | # | ||
| 1483 | # SPI RTC drivers | ||
| 1484 | # | ||
| 1485 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 1486 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1487 | # CONFIG_RTC_DRV_DS1390 is not set | ||
| 1488 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 1489 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1490 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1491 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1492 | # CONFIG_RTC_DRV_PCF2123 is not set | ||
| 1493 | |||
| 1494 | # | ||
| 1495 | # Platform RTC drivers | ||
| 1496 | # | ||
| 1497 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 1498 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1499 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1500 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1501 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1502 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1503 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1504 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1505 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1506 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1507 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 1508 | |||
| 1509 | # | ||
| 1510 | # on-CPU RTC drivers | ||
| 1511 | # | ||
| 1512 | # CONFIG_RTC_DRV_SA1100 is not set | ||
| 1513 | CONFIG_RTC_DRV_PXA=y | ||
| 1514 | CONFIG_DMADEVICES=y | ||
| 1515 | |||
| 1516 | # | ||
| 1517 | # DMA Devices | ||
| 1518 | # | ||
| 1519 | # CONFIG_AUXDISPLAY is not set | ||
| 1520 | CONFIG_UIO=y | ||
| 1521 | # CONFIG_UIO_PDRV is not set | ||
| 1522 | # CONFIG_UIO_PDRV_GENIRQ is not set | ||
| 1523 | # CONFIG_UIO_SMX is not set | ||
| 1524 | # CONFIG_UIO_SERCOS3 is not set | ||
| 1525 | |||
| 1526 | # | ||
| 1527 | # TI VLYNQ | ||
| 1528 | # | ||
| 1529 | # CONFIG_STAGING is not set | ||
| 1530 | |||
| 1531 | # | ||
| 1532 | # File systems | ||
| 1533 | # | ||
| 1534 | CONFIG_EXT2_FS=y | ||
| 1535 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 1536 | CONFIG_EXT2_FS_XIP=y | ||
| 1537 | CONFIG_EXT3_FS=y | ||
| 1538 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
| 1539 | CONFIG_EXT3_FS_XATTR=y | ||
| 1540 | # CONFIG_EXT3_FS_POSIX_ACL is not set | ||
| 1541 | # CONFIG_EXT3_FS_SECURITY is not set | ||
| 1542 | # CONFIG_EXT4_FS is not set | ||
| 1543 | CONFIG_FS_XIP=y | ||
| 1544 | CONFIG_JBD=y | ||
| 1545 | CONFIG_FS_MBCACHE=y | ||
| 1546 | # CONFIG_REISERFS_FS is not set | ||
| 1547 | # CONFIG_JFS_FS is not set | ||
| 1548 | # CONFIG_FS_POSIX_ACL is not set | ||
| 1549 | # CONFIG_XFS_FS is not set | ||
| 1550 | # CONFIG_OCFS2_FS is not set | ||
| 1551 | # CONFIG_BTRFS_FS is not set | ||
| 1552 | # CONFIG_NILFS2_FS is not set | ||
| 1553 | CONFIG_FILE_LOCKING=y | ||
| 1554 | CONFIG_FSNOTIFY=y | ||
| 1555 | CONFIG_DNOTIFY=y | ||
| 1556 | CONFIG_INOTIFY=y | ||
| 1557 | CONFIG_INOTIFY_USER=y | ||
| 1558 | # CONFIG_QUOTA is not set | ||
| 1559 | # CONFIG_AUTOFS_FS is not set | ||
| 1560 | # CONFIG_AUTOFS4_FS is not set | ||
| 1561 | # CONFIG_FUSE_FS is not set | ||
| 1562 | |||
| 1563 | # | ||
| 1564 | # Caches | ||
| 1565 | # | ||
| 1566 | CONFIG_FSCACHE=y | ||
| 1567 | CONFIG_FSCACHE_STATS=y | ||
| 1568 | # CONFIG_FSCACHE_HISTOGRAM is not set | ||
| 1569 | # CONFIG_FSCACHE_DEBUG is not set | ||
| 1570 | CONFIG_CACHEFILES=y | ||
| 1571 | # CONFIG_CACHEFILES_DEBUG is not set | ||
| 1572 | # CONFIG_CACHEFILES_HISTOGRAM is not set | ||
| 1573 | |||
| 1574 | # | ||
| 1575 | # CD-ROM/DVD Filesystems | ||
| 1576 | # | ||
| 1577 | # CONFIG_ISO9660_FS is not set | ||
| 1578 | # CONFIG_UDF_FS is not set | ||
| 1579 | |||
| 1580 | # | ||
| 1581 | # DOS/FAT/NT Filesystems | ||
| 1582 | # | ||
| 1583 | CONFIG_FAT_FS=y | ||
| 1584 | CONFIG_MSDOS_FS=y | ||
| 1585 | CONFIG_VFAT_FS=y | ||
| 1586 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1587 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1588 | # CONFIG_NTFS_FS is not set | ||
| 1589 | |||
| 1590 | # | ||
| 1591 | # Pseudo filesystems | ||
| 1592 | # | ||
| 1593 | CONFIG_PROC_FS=y | ||
| 1594 | CONFIG_PROC_SYSCTL=y | ||
| 1595 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1596 | CONFIG_SYSFS=y | ||
| 1597 | CONFIG_TMPFS=y | ||
| 1598 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1599 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1600 | # CONFIG_CONFIGFS_FS is not set | ||
| 1601 | CONFIG_MISC_FILESYSTEMS=y | ||
| 1602 | # CONFIG_ADFS_FS is not set | ||
| 1603 | # CONFIG_AFFS_FS is not set | ||
| 1604 | # CONFIG_HFS_FS is not set | ||
| 1605 | # CONFIG_HFSPLUS_FS is not set | ||
| 1606 | # CONFIG_BEFS_FS is not set | ||
| 1607 | # CONFIG_BFS_FS is not set | ||
| 1608 | # CONFIG_EFS_FS is not set | ||
| 1609 | # CONFIG_JFFS2_FS is not set | ||
| 1610 | CONFIG_UBIFS_FS=y | ||
| 1611 | # CONFIG_UBIFS_FS_XATTR is not set | ||
| 1612 | # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set | ||
| 1613 | CONFIG_UBIFS_FS_LZO=y | ||
| 1614 | CONFIG_UBIFS_FS_ZLIB=y | ||
| 1615 | # CONFIG_UBIFS_FS_DEBUG is not set | ||
| 1616 | # CONFIG_CRAMFS is not set | ||
| 1617 | # CONFIG_SQUASHFS is not set | ||
| 1618 | # CONFIG_VXFS_FS is not set | ||
| 1619 | # CONFIG_MINIX_FS is not set | ||
| 1620 | # CONFIG_OMFS_FS is not set | ||
| 1621 | # CONFIG_HPFS_FS is not set | ||
| 1622 | # CONFIG_QNX4FS_FS is not set | ||
| 1623 | # CONFIG_ROMFS_FS is not set | ||
| 1624 | # CONFIG_SYSV_FS is not set | ||
| 1625 | # CONFIG_UFS_FS is not set | ||
| 1626 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1627 | CONFIG_NFS_FS=y | ||
| 1628 | CONFIG_NFS_V3=y | ||
| 1629 | # CONFIG_NFS_V3_ACL is not set | ||
| 1630 | # CONFIG_NFS_V4 is not set | ||
| 1631 | CONFIG_ROOT_NFS=y | ||
| 1632 | CONFIG_NFS_FSCACHE=y | ||
| 1633 | # CONFIG_NFSD is not set | ||
| 1634 | CONFIG_LOCKD=y | ||
| 1635 | CONFIG_LOCKD_V4=y | ||
| 1636 | CONFIG_NFS_COMMON=y | ||
| 1637 | CONFIG_SUNRPC=y | ||
| 1638 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 1639 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1640 | # CONFIG_SMB_FS is not set | ||
| 1641 | # CONFIG_CIFS is not set | ||
| 1642 | # CONFIG_NCP_FS is not set | ||
| 1643 | # CONFIG_CODA_FS is not set | ||
| 1644 | # CONFIG_AFS_FS is not set | ||
| 1645 | |||
| 1646 | # | ||
| 1647 | # Partition Types | ||
| 1648 | # | ||
| 1649 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 1650 | CONFIG_MSDOS_PARTITION=y | ||
| 1651 | CONFIG_NLS=y | ||
| 1652 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1653 | CONFIG_NLS_CODEPAGE_437=y | ||
| 1654 | CONFIG_NLS_CODEPAGE_737=y | ||
| 1655 | CONFIG_NLS_CODEPAGE_775=y | ||
| 1656 | CONFIG_NLS_CODEPAGE_850=y | ||
| 1657 | CONFIG_NLS_CODEPAGE_852=y | ||
| 1658 | CONFIG_NLS_CODEPAGE_855=y | ||
| 1659 | CONFIG_NLS_CODEPAGE_857=y | ||
| 1660 | CONFIG_NLS_CODEPAGE_860=y | ||
| 1661 | CONFIG_NLS_CODEPAGE_861=y | ||
| 1662 | CONFIG_NLS_CODEPAGE_862=y | ||
| 1663 | CONFIG_NLS_CODEPAGE_863=y | ||
| 1664 | CONFIG_NLS_CODEPAGE_864=y | ||
| 1665 | CONFIG_NLS_CODEPAGE_865=y | ||
| 1666 | CONFIG_NLS_CODEPAGE_866=y | ||
| 1667 | CONFIG_NLS_CODEPAGE_869=y | ||
| 1668 | CONFIG_NLS_CODEPAGE_936=y | ||
| 1669 | CONFIG_NLS_CODEPAGE_950=y | ||
| 1670 | CONFIG_NLS_CODEPAGE_932=y | ||
| 1671 | CONFIG_NLS_CODEPAGE_949=y | ||
| 1672 | CONFIG_NLS_CODEPAGE_874=y | ||
| 1673 | CONFIG_NLS_ISO8859_8=y | ||
| 1674 | CONFIG_NLS_CODEPAGE_1250=y | ||
| 1675 | CONFIG_NLS_CODEPAGE_1251=y | ||
| 1676 | CONFIG_NLS_ASCII=y | ||
| 1677 | CONFIG_NLS_ISO8859_1=y | ||
| 1678 | CONFIG_NLS_ISO8859_2=y | ||
| 1679 | CONFIG_NLS_ISO8859_3=y | ||
| 1680 | CONFIG_NLS_ISO8859_4=y | ||
| 1681 | CONFIG_NLS_ISO8859_5=y | ||
| 1682 | CONFIG_NLS_ISO8859_6=y | ||
| 1683 | CONFIG_NLS_ISO8859_7=y | ||
| 1684 | CONFIG_NLS_ISO8859_9=y | ||
| 1685 | CONFIG_NLS_ISO8859_13=y | ||
| 1686 | CONFIG_NLS_ISO8859_14=y | ||
| 1687 | CONFIG_NLS_ISO8859_15=y | ||
| 1688 | CONFIG_NLS_KOI8_R=y | ||
| 1689 | CONFIG_NLS_KOI8_U=y | ||
| 1690 | CONFIG_NLS_UTF8=y | ||
| 1691 | # CONFIG_DLM is not set | ||
| 1692 | |||
| 1693 | # | ||
| 1694 | # Kernel hacking | ||
| 1695 | # | ||
| 1696 | CONFIG_PRINTK_TIME=y | ||
| 1697 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1698 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1699 | CONFIG_FRAME_WARN=1024 | ||
| 1700 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1701 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 1702 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1703 | # CONFIG_DEBUG_FS is not set | ||
| 1704 | # CONFIG_HEADERS_CHECK is not set | ||
| 1705 | CONFIG_DEBUG_KERNEL=y | ||
| 1706 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1707 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1708 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1709 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1710 | CONFIG_DETECT_HUNG_TASK=y | ||
| 1711 | # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set | ||
| 1712 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 | ||
| 1713 | CONFIG_SCHED_DEBUG=y | ||
| 1714 | # CONFIG_SCHEDSTATS is not set | ||
| 1715 | # CONFIG_TIMER_STATS is not set | ||
| 1716 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1717 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 1718 | # CONFIG_SLUB_STATS is not set | ||
| 1719 | # CONFIG_DEBUG_KMEMLEAK is not set | ||
| 1720 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1721 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1722 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1723 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1724 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1725 | # CONFIG_PROVE_LOCKING is not set | ||
| 1726 | # CONFIG_LOCK_STAT is not set | ||
| 1727 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1728 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1729 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1730 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1731 | CONFIG_DEBUG_INFO=y | ||
| 1732 | # CONFIG_DEBUG_VM is not set | ||
| 1733 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1734 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 1735 | # CONFIG_DEBUG_LIST is not set | ||
| 1736 | # CONFIG_DEBUG_SG is not set | ||
| 1737 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1738 | # CONFIG_DEBUG_CREDENTIALS is not set | ||
| 1739 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1740 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1741 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1742 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1743 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1744 | # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set | ||
| 1745 | # CONFIG_FAULT_INJECTION is not set | ||
| 1746 | # CONFIG_LATENCYTOP is not set | ||
| 1747 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1748 | # CONFIG_PAGE_POISONING is not set | ||
| 1749 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1750 | CONFIG_TRACING_SUPPORT=y | ||
| 1751 | CONFIG_FTRACE=y | ||
| 1752 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1753 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1754 | # CONFIG_SCHED_TRACER is not set | ||
| 1755 | # CONFIG_ENABLE_DEFAULT_TRACERS is not set | ||
| 1756 | # CONFIG_BOOT_TRACER is not set | ||
| 1757 | CONFIG_BRANCH_PROFILE_NONE=y | ||
| 1758 | # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set | ||
| 1759 | # CONFIG_PROFILE_ALL_BRANCHES is not set | ||
| 1760 | # CONFIG_STACK_TRACER is not set | ||
| 1761 | # CONFIG_KMEMTRACE is not set | ||
| 1762 | # CONFIG_WORKQUEUE_TRACER is not set | ||
| 1763 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 1764 | # CONFIG_SAMPLES is not set | ||
| 1765 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1766 | # CONFIG_KGDB is not set | ||
| 1767 | CONFIG_ARM_UNWIND=y | ||
| 1768 | CONFIG_DEBUG_USER=y | ||
| 1769 | CONFIG_DEBUG_ERRORS=y | ||
| 1770 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1771 | CONFIG_DEBUG_LL=y | ||
| 1772 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 1773 | |||
| 1774 | # | ||
| 1775 | # Security options | ||
| 1776 | # | ||
| 1777 | # CONFIG_KEYS is not set | ||
| 1778 | # CONFIG_SECURITY is not set | ||
| 1779 | # CONFIG_SECURITYFS is not set | ||
| 1780 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1781 | CONFIG_CRYPTO=y | ||
| 1782 | |||
| 1783 | # | ||
| 1784 | # Crypto core or helper | ||
| 1785 | # | ||
| 1786 | CONFIG_CRYPTO_ALGAPI=y | ||
| 1787 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1788 | CONFIG_CRYPTO_AEAD2=y | ||
| 1789 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 1790 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1791 | CONFIG_CRYPTO_HASH2=y | ||
| 1792 | CONFIG_CRYPTO_RNG2=y | ||
| 1793 | CONFIG_CRYPTO_PCOMP=y | ||
| 1794 | CONFIG_CRYPTO_MANAGER=y | ||
| 1795 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1796 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1797 | # CONFIG_CRYPTO_NULL is not set | ||
| 1798 | CONFIG_CRYPTO_WORKQUEUE=y | ||
| 1799 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1800 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1801 | # CONFIG_CRYPTO_TEST is not set | ||
| 1802 | |||
| 1803 | # | ||
| 1804 | # Authenticated Encryption with Associated Data | ||
| 1805 | # | ||
| 1806 | # CONFIG_CRYPTO_CCM is not set | ||
| 1807 | # CONFIG_CRYPTO_GCM is not set | ||
| 1808 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1809 | |||
| 1810 | # | ||
| 1811 | # Block modes | ||
| 1812 | # | ||
| 1813 | # CONFIG_CRYPTO_CBC is not set | ||
| 1814 | # CONFIG_CRYPTO_CTR is not set | ||
| 1815 | # CONFIG_CRYPTO_CTS is not set | ||
| 1816 | CONFIG_CRYPTO_ECB=y | ||
| 1817 | # CONFIG_CRYPTO_LRW is not set | ||
| 1818 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1819 | # CONFIG_CRYPTO_XTS is not set | ||
| 1820 | |||
| 1821 | # | ||
| 1822 | # Hash modes | ||
| 1823 | # | ||
| 1824 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1825 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1826 | # CONFIG_CRYPTO_VMAC is not set | ||
| 1827 | |||
| 1828 | # | ||
| 1829 | # Digest | ||
| 1830 | # | ||
| 1831 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1832 | # CONFIG_CRYPTO_GHASH is not set | ||
| 1833 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1834 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1835 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1836 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1837 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1838 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1839 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1840 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1841 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1842 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1843 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1844 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1845 | |||
| 1846 | # | ||
| 1847 | # Ciphers | ||
| 1848 | # | ||
| 1849 | CONFIG_CRYPTO_AES=y | ||
| 1850 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1851 | CONFIG_CRYPTO_ARC4=y | ||
| 1852 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1853 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1854 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1855 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1856 | # CONFIG_CRYPTO_DES is not set | ||
| 1857 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1858 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1859 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1860 | # CONFIG_CRYPTO_SEED is not set | ||
| 1861 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1862 | # CONFIG_CRYPTO_TEA is not set | ||
| 1863 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1864 | |||
| 1865 | # | ||
| 1866 | # Compression | ||
| 1867 | # | ||
| 1868 | CONFIG_CRYPTO_DEFLATE=y | ||
| 1869 | # CONFIG_CRYPTO_ZLIB is not set | ||
| 1870 | CONFIG_CRYPTO_LZO=y | ||
| 1871 | |||
| 1872 | # | ||
| 1873 | # Random Number Generation | ||
| 1874 | # | ||
| 1875 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1876 | # CONFIG_CRYPTO_HW is not set | ||
| 1877 | # CONFIG_BINARY_PRINTF is not set | ||
| 1878 | |||
| 1879 | # | ||
| 1880 | # Library routines | ||
| 1881 | # | ||
| 1882 | CONFIG_BITREVERSE=y | ||
| 1883 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1884 | # CONFIG_CRC_CCITT is not set | ||
| 1885 | CONFIG_CRC16=y | ||
| 1886 | # CONFIG_CRC_T10DIF is not set | ||
| 1887 | # CONFIG_CRC_ITU_T is not set | ||
| 1888 | CONFIG_CRC32=y | ||
| 1889 | # CONFIG_CRC7 is not set | ||
| 1890 | # CONFIG_LIBCRC32C is not set | ||
| 1891 | CONFIG_ZLIB_INFLATE=y | ||
| 1892 | CONFIG_ZLIB_DEFLATE=y | ||
| 1893 | CONFIG_LZO_COMPRESS=y | ||
| 1894 | CONFIG_LZO_DECOMPRESS=y | ||
| 1895 | CONFIG_HAS_IOMEM=y | ||
| 1896 | CONFIG_HAS_IOPORT=y | ||
| 1897 | CONFIG_HAS_DMA=y | ||
| 1898 | CONFIG_NLATTR=y | ||
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index 2f10dae02796..8e94c3caeb8c 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig | |||
| @@ -187,7 +187,7 @@ CONFIG_S3C24XX_GPIO_EXTRA128=y | |||
| 187 | CONFIG_PM_SIMTEC=y | 187 | CONFIG_PM_SIMTEC=y |
| 188 | CONFIG_S3C2410_DMA=y | 188 | CONFIG_S3C2410_DMA=y |
| 189 | # CONFIG_S3C2410_DMA_DEBUG is not set | 189 | # CONFIG_S3C2410_DMA_DEBUG is not set |
| 190 | CONFIG_S3C24XX_ADC=y | 190 | CONFIG_S3C_ADC=y |
| 191 | CONFIG_MACH_SMDK=y | 191 | CONFIG_MACH_SMDK=y |
| 192 | CONFIG_PLAT_S3C=y | 192 | CONFIG_PLAT_S3C=y |
| 193 | CONFIG_CPU_LLSERIAL_S3C2410=y | 193 | CONFIG_CPU_LLSERIAL_S3C2410=y |
| @@ -203,8 +203,8 @@ CONFIG_S3C_BOOT_UART_FORCE_FIFO=y | |||
| 203 | # | 203 | # |
| 204 | # Power management | 204 | # Power management |
| 205 | # | 205 | # |
| 206 | # CONFIG_S3C2410_PM_DEBUG is not set | 206 | # CONFIG_SAMSUNG_PM_DEBUG is not set |
| 207 | # CONFIG_S3C2410_PM_CHECK is not set | 207 | # CONFIG_SAMSUNG_PM_CHECK is not set |
| 208 | CONFIG_S3C_LOWLEVEL_UART_PORT=0 | 208 | CONFIG_S3C_LOWLEVEL_UART_PORT=0 |
| 209 | CONFIG_S3C_GPIO_SPACE=0 | 209 | CONFIG_S3C_GPIO_SPACE=0 |
| 210 | CONFIG_S3C_DEV_HSMMC=y | 210 | CONFIG_S3C_DEV_HSMMC=y |
diff --git a/arch/arm/configs/s5p6440_defconfig b/arch/arm/configs/s5p6440_defconfig new file mode 100644 index 000000000000..279a15e53114 --- /dev/null +++ b/arch/arm/configs/s5p6440_defconfig | |||
| @@ -0,0 +1,969 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.33-rc2 | ||
| 4 | # Sat Jan 9 16:33:55 2010 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_NO_IOPORT=y | ||
| 10 | CONFIG_GENERIC_HARDIRQS=y | ||
| 11 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 12 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 13 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 14 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 15 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 16 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 17 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 18 | CONFIG_GENERIC_HWEIGHT=y | ||
| 19 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 20 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 21 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 22 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 23 | CONFIG_CONSTRUCTORS=y | ||
| 24 | |||
| 25 | # | ||
| 26 | # General setup | ||
| 27 | # | ||
| 28 | CONFIG_EXPERIMENTAL=y | ||
| 29 | CONFIG_BROKEN_ON_SMP=y | ||
| 30 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 31 | CONFIG_LOCALVERSION="" | ||
| 32 | CONFIG_LOCALVERSION_AUTO=y | ||
| 33 | CONFIG_SWAP=y | ||
| 34 | # CONFIG_SYSVIPC is not set | ||
| 35 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 36 | |||
| 37 | # | ||
| 38 | # RCU Subsystem | ||
| 39 | # | ||
| 40 | CONFIG_TREE_RCU=y | ||
| 41 | # CONFIG_TREE_PREEMPT_RCU is not set | ||
| 42 | # CONFIG_TINY_RCU is not set | ||
| 43 | # CONFIG_RCU_TRACE is not set | ||
| 44 | CONFIG_RCU_FANOUT=32 | ||
| 45 | # CONFIG_RCU_FANOUT_EXACT is not set | ||
| 46 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 47 | # CONFIG_IKCONFIG is not set | ||
| 48 | CONFIG_LOG_BUF_SHIFT=17 | ||
| 49 | # CONFIG_GROUP_SCHED is not set | ||
| 50 | # CONFIG_CGROUPS is not set | ||
| 51 | CONFIG_SYSFS_DEPRECATED=y | ||
| 52 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 53 | # CONFIG_RELAY is not set | ||
| 54 | CONFIG_NAMESPACES=y | ||
| 55 | # CONFIG_UTS_NS is not set | ||
| 56 | # CONFIG_USER_NS is not set | ||
| 57 | # CONFIG_PID_NS is not set | ||
| 58 | CONFIG_BLK_DEV_INITRD=y | ||
| 59 | CONFIG_INITRAMFS_SOURCE="" | ||
| 60 | CONFIG_RD_GZIP=y | ||
| 61 | CONFIG_RD_BZIP2=y | ||
| 62 | CONFIG_RD_LZMA=y | ||
| 63 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 64 | CONFIG_SYSCTL=y | ||
| 65 | CONFIG_ANON_INODES=y | ||
| 66 | # CONFIG_EMBEDDED is not set | ||
| 67 | CONFIG_UID16=y | ||
| 68 | CONFIG_SYSCTL_SYSCALL=y | ||
| 69 | CONFIG_KALLSYMS=y | ||
| 70 | CONFIG_KALLSYMS_ALL=y | ||
| 71 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 72 | CONFIG_HOTPLUG=y | ||
| 73 | CONFIG_PRINTK=y | ||
| 74 | CONFIG_BUG=y | ||
| 75 | CONFIG_ELF_CORE=y | ||
| 76 | CONFIG_BASE_FULL=y | ||
| 77 | CONFIG_FUTEX=y | ||
| 78 | CONFIG_EPOLL=y | ||
| 79 | CONFIG_SIGNALFD=y | ||
| 80 | CONFIG_TIMERFD=y | ||
| 81 | CONFIG_EVENTFD=y | ||
| 82 | CONFIG_SHMEM=y | ||
| 83 | CONFIG_AIO=y | ||
| 84 | |||
| 85 | # | ||
| 86 | # Kernel Performance Events And Counters | ||
| 87 | # | ||
| 88 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 89 | CONFIG_SLUB_DEBUG=y | ||
| 90 | CONFIG_COMPAT_BRK=y | ||
| 91 | # CONFIG_SLAB is not set | ||
| 92 | CONFIG_SLUB=y | ||
| 93 | # CONFIG_SLOB is not set | ||
| 94 | # CONFIG_PROFILING is not set | ||
| 95 | CONFIG_HAVE_OPROFILE=y | ||
| 96 | # CONFIG_KPROBES is not set | ||
| 97 | CONFIG_HAVE_KPROBES=y | ||
| 98 | CONFIG_HAVE_KRETPROBES=y | ||
| 99 | CONFIG_HAVE_CLK=y | ||
| 100 | |||
| 101 | # | ||
| 102 | # GCOV-based kernel profiling | ||
| 103 | # | ||
| 104 | # CONFIG_SLOW_WORK is not set | ||
| 105 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 106 | CONFIG_SLABINFO=y | ||
| 107 | CONFIG_RT_MUTEXES=y | ||
| 108 | CONFIG_BASE_SMALL=0 | ||
| 109 | CONFIG_MODULES=y | ||
| 110 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 111 | CONFIG_MODULE_UNLOAD=y | ||
| 112 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 113 | # CONFIG_MODVERSIONS is not set | ||
| 114 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 115 | CONFIG_BLOCK=y | ||
| 116 | CONFIG_LBDAF=y | ||
| 117 | # CONFIG_BLK_DEV_BSG is not set | ||
| 118 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 119 | |||
| 120 | # | ||
| 121 | # IO Schedulers | ||
| 122 | # | ||
| 123 | CONFIG_IOSCHED_NOOP=y | ||
| 124 | CONFIG_IOSCHED_DEADLINE=y | ||
| 125 | CONFIG_IOSCHED_CFQ=y | ||
| 126 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 127 | CONFIG_DEFAULT_CFQ=y | ||
| 128 | # CONFIG_DEFAULT_NOOP is not set | ||
| 129 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 130 | # CONFIG_INLINE_SPIN_TRYLOCK is not set | ||
| 131 | # CONFIG_INLINE_SPIN_TRYLOCK_BH is not set | ||
| 132 | # CONFIG_INLINE_SPIN_LOCK is not set | ||
| 133 | # CONFIG_INLINE_SPIN_LOCK_BH is not set | ||
| 134 | # CONFIG_INLINE_SPIN_LOCK_IRQ is not set | ||
| 135 | # CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set | ||
| 136 | # CONFIG_INLINE_SPIN_UNLOCK is not set | ||
| 137 | # CONFIG_INLINE_SPIN_UNLOCK_BH is not set | ||
| 138 | # CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set | ||
| 139 | # CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set | ||
| 140 | # CONFIG_INLINE_READ_TRYLOCK is not set | ||
| 141 | # CONFIG_INLINE_READ_LOCK is not set | ||
| 142 | # CONFIG_INLINE_READ_LOCK_BH is not set | ||
| 143 | # CONFIG_INLINE_READ_LOCK_IRQ is not set | ||
| 144 | # CONFIG_INLINE_READ_LOCK_IRQSAVE is not set | ||
| 145 | # CONFIG_INLINE_READ_UNLOCK is not set | ||
| 146 | # CONFIG_INLINE_READ_UNLOCK_BH is not set | ||
| 147 | # CONFIG_INLINE_READ_UNLOCK_IRQ is not set | ||
| 148 | # CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set | ||
| 149 | # CONFIG_INLINE_WRITE_TRYLOCK is not set | ||
| 150 | # CONFIG_INLINE_WRITE_LOCK is not set | ||
| 151 | # CONFIG_INLINE_WRITE_LOCK_BH is not set | ||
| 152 | # CONFIG_INLINE_WRITE_LOCK_IRQ is not set | ||
| 153 | # CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set | ||
| 154 | # CONFIG_INLINE_WRITE_UNLOCK is not set | ||
| 155 | # CONFIG_INLINE_WRITE_UNLOCK_BH is not set | ||
| 156 | # CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set | ||
| 157 | # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set | ||
| 158 | # CONFIG_MUTEX_SPIN_ON_OWNER is not set | ||
| 159 | # CONFIG_FREEZER is not set | ||
| 160 | |||
| 161 | # | ||
| 162 | # System Type | ||
| 163 | # | ||
| 164 | CONFIG_MMU=y | ||
| 165 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 166 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 167 | # CONFIG_ARCH_REALVIEW is not set | ||
| 168 | # CONFIG_ARCH_VERSATILE is not set | ||
| 169 | # CONFIG_ARCH_AT91 is not set | ||
| 170 | # CONFIG_ARCH_CLPS711X is not set | ||
| 171 | # CONFIG_ARCH_GEMINI is not set | ||
| 172 | # CONFIG_ARCH_EBSA110 is not set | ||
| 173 | # CONFIG_ARCH_EP93XX is not set | ||
| 174 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 175 | # CONFIG_ARCH_MXC is not set | ||
| 176 | # CONFIG_ARCH_STMP3XXX is not set | ||
| 177 | # CONFIG_ARCH_NETX is not set | ||
| 178 | # CONFIG_ARCH_H720X is not set | ||
| 179 | # CONFIG_ARCH_NOMADIK is not set | ||
| 180 | # CONFIG_ARCH_IOP13XX is not set | ||
| 181 | # CONFIG_ARCH_IOP32X is not set | ||
| 182 | # CONFIG_ARCH_IOP33X is not set | ||
| 183 | # CONFIG_ARCH_IXP23XX is not set | ||
| 184 | # CONFIG_ARCH_IXP2000 is not set | ||
| 185 | # CONFIG_ARCH_IXP4XX is not set | ||
| 186 | # CONFIG_ARCH_L7200 is not set | ||
| 187 | # CONFIG_ARCH_DOVE is not set | ||
| 188 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 189 | # CONFIG_ARCH_LOKI is not set | ||
| 190 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 191 | # CONFIG_ARCH_ORION5X is not set | ||
| 192 | # CONFIG_ARCH_MMP is not set | ||
| 193 | # CONFIG_ARCH_KS8695 is not set | ||
| 194 | # CONFIG_ARCH_NS9XXX is not set | ||
| 195 | # CONFIG_ARCH_W90X900 is not set | ||
| 196 | # CONFIG_ARCH_PNX4008 is not set | ||
| 197 | # CONFIG_ARCH_PXA is not set | ||
| 198 | # CONFIG_ARCH_MSM is not set | ||
| 199 | # CONFIG_ARCH_RPC is not set | ||
| 200 | # CONFIG_ARCH_SA1100 is not set | ||
| 201 | # CONFIG_ARCH_S3C2410 is not set | ||
| 202 | # CONFIG_ARCH_S3C64XX is not set | ||
| 203 | CONFIG_ARCH_S5P6440=y | ||
| 204 | # CONFIG_ARCH_S5PC1XX is not set | ||
| 205 | # CONFIG_ARCH_SHARK is not set | ||
| 206 | # CONFIG_ARCH_LH7A40X is not set | ||
| 207 | # CONFIG_ARCH_U300 is not set | ||
| 208 | # CONFIG_ARCH_DAVINCI is not set | ||
| 209 | # CONFIG_ARCH_OMAP is not set | ||
| 210 | # CONFIG_ARCH_BCMRING is not set | ||
| 211 | # CONFIG_ARCH_U8500 is not set | ||
| 212 | CONFIG_PLAT_SAMSUNG=y | ||
| 213 | CONFIG_SAMSUNG_CLKSRC=y | ||
| 214 | CONFIG_SAMSUNG_IRQ_VIC_TIMER=y | ||
| 215 | CONFIG_SAMSUNG_IRQ_UART=y | ||
| 216 | CONFIG_SAMSUNG_GPIO_EXTRA=0 | ||
| 217 | CONFIG_PLAT_S3C=y | ||
| 218 | |||
| 219 | # | ||
| 220 | # Boot options | ||
| 221 | # | ||
| 222 | CONFIG_S3C_BOOT_ERROR_RESET=y | ||
| 223 | CONFIG_S3C_BOOT_UART_FORCE_FIFO=y | ||
| 224 | |||
| 225 | # | ||
| 226 | # Power management | ||
| 227 | # | ||
| 228 | CONFIG_S3C_LOWLEVEL_UART_PORT=1 | ||
| 229 | CONFIG_S3C_GPIO_SPACE=0 | ||
| 230 | CONFIG_S3C_GPIO_TRACK=y | ||
| 231 | CONFIG_PLAT_S5P=y | ||
| 232 | CONFIG_CPU_S5P6440_INIT=y | ||
| 233 | CONFIG_CPU_S5P6440_CLOCK=y | ||
| 234 | CONFIG_CPU_S5P6440=y | ||
| 235 | CONFIG_MACH_SMDK6440=y | ||
| 236 | |||
| 237 | # | ||
| 238 | # Processor Type | ||
| 239 | # | ||
| 240 | CONFIG_CPU_V6=y | ||
| 241 | CONFIG_CPU_32v6K=y | ||
| 242 | CONFIG_CPU_32v6=y | ||
| 243 | CONFIG_CPU_ABRT_EV6=y | ||
| 244 | CONFIG_CPU_PABRT_V6=y | ||
| 245 | CONFIG_CPU_CACHE_V6=y | ||
| 246 | CONFIG_CPU_CACHE_VIPT=y | ||
| 247 | CONFIG_CPU_COPY_V6=y | ||
| 248 | CONFIG_CPU_TLB_V6=y | ||
| 249 | CONFIG_CPU_HAS_ASID=y | ||
| 250 | CONFIG_CPU_CP15=y | ||
| 251 | CONFIG_CPU_CP15_MMU=y | ||
| 252 | |||
| 253 | # | ||
| 254 | # Processor Features | ||
| 255 | # | ||
| 256 | CONFIG_ARM_THUMB=y | ||
| 257 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 258 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 259 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
| 260 | CONFIG_ARM_L1_CACHE_SHIFT=5 | ||
| 261 | # CONFIG_ARM_ERRATA_411920 is not set | ||
| 262 | CONFIG_ARM_VIC=y | ||
| 263 | CONFIG_ARM_VIC_NR=2 | ||
| 264 | |||
| 265 | # | ||
| 266 | # Bus support | ||
| 267 | # | ||
| 268 | # CONFIG_PCI_SYSCALL is not set | ||
| 269 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 270 | # CONFIG_PCCARD is not set | ||
| 271 | |||
| 272 | # | ||
| 273 | # Kernel Features | ||
| 274 | # | ||
| 275 | CONFIG_VMSPLIT_3G=y | ||
| 276 | # CONFIG_VMSPLIT_2G is not set | ||
| 277 | # CONFIG_VMSPLIT_1G is not set | ||
| 278 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 279 | CONFIG_PREEMPT_NONE=y | ||
| 280 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
| 281 | # CONFIG_PREEMPT is not set | ||
| 282 | CONFIG_HZ=200 | ||
| 283 | CONFIG_AEABI=y | ||
| 284 | CONFIG_OABI_COMPAT=y | ||
| 285 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 286 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 287 | # CONFIG_HIGHMEM is not set | ||
| 288 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 289 | CONFIG_FLATMEM_MANUAL=y | ||
| 290 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 291 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 292 | CONFIG_FLATMEM=y | ||
| 293 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 294 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 295 | CONFIG_SPLIT_PTLOCK_CPUS=999999 | ||
| 296 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 297 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 298 | CONFIG_VIRT_TO_BUS=y | ||
| 299 | # CONFIG_KSM is not set | ||
| 300 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
| 301 | CONFIG_ALIGNMENT_TRAP=y | ||
| 302 | # CONFIG_UACCESS_WITH_MEMCPY is not set | ||
| 303 | |||
| 304 | # | ||
| 305 | # Boot options | ||
| 306 | # | ||
| 307 | CONFIG_ZBOOT_ROM_TEXT=0 | ||
| 308 | CONFIG_ZBOOT_ROM_BSS=0 | ||
| 309 | CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc" | ||
| 310 | # CONFIG_XIP_KERNEL is not set | ||
| 311 | # CONFIG_KEXEC is not set | ||
| 312 | |||
| 313 | # | ||
| 314 | # CPU Power Management | ||
| 315 | # | ||
| 316 | # CONFIG_CPU_IDLE is not set | ||
| 317 | |||
| 318 | # | ||
| 319 | # Floating point emulation | ||
| 320 | # | ||
| 321 | |||
| 322 | # | ||
| 323 | # At least one emulation must be selected | ||
| 324 | # | ||
| 325 | CONFIG_FPE_NWFPE=y | ||
| 326 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 327 | # CONFIG_FPE_FASTFPE is not set | ||
| 328 | # CONFIG_VFP is not set | ||
| 329 | |||
| 330 | # | ||
| 331 | # Userspace binary formats | ||
| 332 | # | ||
| 333 | CONFIG_BINFMT_ELF=y | ||
| 334 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 335 | CONFIG_HAVE_AOUT=y | ||
| 336 | # CONFIG_BINFMT_AOUT is not set | ||
| 337 | # CONFIG_BINFMT_MISC is not set | ||
| 338 | |||
| 339 | # | ||
| 340 | # Power management options | ||
| 341 | # | ||
| 342 | # CONFIG_PM is not set | ||
| 343 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 344 | # CONFIG_NET is not set | ||
| 345 | |||
| 346 | # | ||
| 347 | # Device Drivers | ||
| 348 | # | ||
| 349 | |||
| 350 | # | ||
| 351 | # Generic Driver Options | ||
| 352 | # | ||
| 353 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 354 | # CONFIG_DEVTMPFS is not set | ||
| 355 | CONFIG_STANDALONE=y | ||
| 356 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | ||
| 357 | CONFIG_FW_LOADER=y | ||
| 358 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 359 | CONFIG_EXTRA_FIRMWARE="" | ||
| 360 | # CONFIG_DEBUG_DRIVER is not set | ||
| 361 | # CONFIG_DEBUG_DEVRES is not set | ||
| 362 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 363 | # CONFIG_MTD is not set | ||
| 364 | # CONFIG_PARPORT is not set | ||
| 365 | CONFIG_BLK_DEV=y | ||
| 366 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 367 | # CONFIG_BLK_DEV_LOOP is not set | ||
| 368 | |||
| 369 | # | ||
| 370 | # DRBD disabled because PROC_FS, INET or CONNECTOR not selected | ||
| 371 | # | ||
| 372 | CONFIG_BLK_DEV_RAM=y | ||
| 373 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 374 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 375 | # CONFIG_BLK_DEV_XIP is not set | ||
| 376 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 377 | # CONFIG_MG_DISK is not set | ||
| 378 | # CONFIG_MISC_DEVICES is not set | ||
| 379 | CONFIG_HAVE_IDE=y | ||
| 380 | # CONFIG_IDE is not set | ||
| 381 | |||
| 382 | # | ||
| 383 | # SCSI device support | ||
| 384 | # | ||
| 385 | # CONFIG_RAID_ATTRS is not set | ||
| 386 | CONFIG_SCSI=y | ||
| 387 | CONFIG_SCSI_DMA=y | ||
| 388 | # CONFIG_SCSI_TGT is not set | ||
| 389 | # CONFIG_SCSI_NETLINK is not set | ||
| 390 | CONFIG_SCSI_PROC_FS=y | ||
| 391 | |||
| 392 | # | ||
| 393 | # SCSI support type (disk, tape, CD-ROM) | ||
| 394 | # | ||
| 395 | CONFIG_BLK_DEV_SD=y | ||
| 396 | # CONFIG_CHR_DEV_ST is not set | ||
| 397 | # CONFIG_CHR_DEV_OSST is not set | ||
| 398 | # CONFIG_BLK_DEV_SR is not set | ||
| 399 | CONFIG_CHR_DEV_SG=y | ||
| 400 | # CONFIG_CHR_DEV_SCH is not set | ||
| 401 | # CONFIG_SCSI_MULTI_LUN is not set | ||
| 402 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 403 | # CONFIG_SCSI_LOGGING is not set | ||
| 404 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 405 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 406 | |||
| 407 | # | ||
| 408 | # SCSI Transports | ||
| 409 | # | ||
| 410 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 411 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 412 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 413 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 414 | CONFIG_SCSI_LOWLEVEL=y | ||
| 415 | # CONFIG_LIBFC is not set | ||
| 416 | # CONFIG_LIBFCOE is not set | ||
| 417 | # CONFIG_SCSI_DEBUG is not set | ||
| 418 | # CONFIG_SCSI_DH is not set | ||
| 419 | # CONFIG_SCSI_OSD_INITIATOR is not set | ||
| 420 | # CONFIG_ATA is not set | ||
| 421 | # CONFIG_MD is not set | ||
| 422 | # CONFIG_PHONE is not set | ||
| 423 | |||
| 424 | # | ||
| 425 | # Input device support | ||
| 426 | # | ||
| 427 | CONFIG_INPUT=y | ||
| 428 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 429 | # CONFIG_INPUT_POLLDEV is not set | ||
| 430 | # CONFIG_INPUT_SPARSEKMAP is not set | ||
| 431 | |||
| 432 | # | ||
| 433 | # Userland interfaces | ||
| 434 | # | ||
| 435 | CONFIG_INPUT_MOUSEDEV=y | ||
| 436 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
| 437 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 438 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 439 | # CONFIG_INPUT_JOYDEV is not set | ||
| 440 | CONFIG_INPUT_EVDEV=y | ||
| 441 | # CONFIG_INPUT_EVBUG is not set | ||
| 442 | |||
| 443 | # | ||
| 444 | # Input Device Drivers | ||
| 445 | # | ||
| 446 | CONFIG_INPUT_KEYBOARD=y | ||
| 447 | CONFIG_KEYBOARD_ATKBD=y | ||
| 448 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 449 | # CONFIG_KEYBOARD_GPIO is not set | ||
| 450 | # CONFIG_KEYBOARD_MATRIX is not set | ||
| 451 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 452 | # CONFIG_KEYBOARD_OPENCORES is not set | ||
| 453 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 454 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 455 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 456 | CONFIG_INPUT_MOUSE=y | ||
| 457 | CONFIG_MOUSE_PS2=y | ||
| 458 | CONFIG_MOUSE_PS2_ALPS=y | ||
| 459 | CONFIG_MOUSE_PS2_LOGIPS2PP=y | ||
| 460 | CONFIG_MOUSE_PS2_SYNAPTICS=y | ||
| 461 | CONFIG_MOUSE_PS2_TRACKPOINT=y | ||
| 462 | # CONFIG_MOUSE_PS2_ELANTECH is not set | ||
| 463 | # CONFIG_MOUSE_PS2_SENTELIC is not set | ||
| 464 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | ||
| 465 | # CONFIG_MOUSE_SERIAL is not set | ||
| 466 | # CONFIG_MOUSE_VSXXXAA is not set | ||
| 467 | # CONFIG_MOUSE_GPIO is not set | ||
| 468 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 469 | # CONFIG_INPUT_TABLET is not set | ||
| 470 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 471 | # CONFIG_TOUCHSCREEN_AD7879 is not set | ||
| 472 | # CONFIG_TOUCHSCREEN_DYNAPRO is not set | ||
| 473 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 474 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
| 475 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
| 476 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 477 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
| 478 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 479 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
| 480 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
| 481 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
| 482 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
| 483 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 484 | # CONFIG_TOUCHSCREEN_W90X900 is not set | ||
| 485 | # CONFIG_INPUT_MISC is not set | ||
| 486 | |||
| 487 | # | ||
| 488 | # Hardware I/O ports | ||
| 489 | # | ||
| 490 | CONFIG_SERIO=y | ||
| 491 | CONFIG_SERIO_SERPORT=y | ||
| 492 | CONFIG_SERIO_LIBPS2=y | ||
| 493 | # CONFIG_SERIO_RAW is not set | ||
| 494 | # CONFIG_SERIO_ALTERA_PS2 is not set | ||
| 495 | # CONFIG_GAMEPORT is not set | ||
| 496 | |||
| 497 | # | ||
| 498 | # Character devices | ||
| 499 | # | ||
| 500 | CONFIG_VT=y | ||
| 501 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 502 | CONFIG_VT_CONSOLE=y | ||
| 503 | CONFIG_HW_CONSOLE=y | ||
| 504 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 505 | CONFIG_DEVKMEM=y | ||
| 506 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 507 | |||
| 508 | # | ||
| 509 | # Serial drivers | ||
| 510 | # | ||
| 511 | CONFIG_SERIAL_8250=y | ||
| 512 | # CONFIG_SERIAL_8250_CONSOLE is not set | ||
| 513 | CONFIG_SERIAL_8250_NR_UARTS=3 | ||
| 514 | CONFIG_SERIAL_8250_RUNTIME_UARTS=3 | ||
| 515 | # CONFIG_SERIAL_8250_EXTENDED is not set | ||
| 516 | |||
| 517 | # | ||
| 518 | # Non-8250 serial port support | ||
| 519 | # | ||
| 520 | CONFIG_SERIAL_SAMSUNG=y | ||
| 521 | CONFIG_SERIAL_SAMSUNG_UARTS=4 | ||
| 522 | # CONFIG_SERIAL_SAMSUNG_DEBUG is not set | ||
| 523 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y | ||
| 524 | CONFIG_SERIAL_S5P6440=y | ||
| 525 | CONFIG_SERIAL_CORE=y | ||
| 526 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 527 | CONFIG_UNIX98_PTYS=y | ||
| 528 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 529 | CONFIG_LEGACY_PTYS=y | ||
| 530 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 531 | # CONFIG_IPMI_HANDLER is not set | ||
| 532 | CONFIG_HW_RANDOM=y | ||
| 533 | # CONFIG_HW_RANDOM_TIMERIOMEM is not set | ||
| 534 | # CONFIG_R3964 is not set | ||
| 535 | # CONFIG_RAW_DRIVER is not set | ||
| 536 | # CONFIG_TCG_TPM is not set | ||
| 537 | # CONFIG_I2C is not set | ||
| 538 | # CONFIG_SPI is not set | ||
| 539 | |||
| 540 | # | ||
| 541 | # PPS support | ||
| 542 | # | ||
| 543 | # CONFIG_PPS is not set | ||
| 544 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 545 | CONFIG_GPIOLIB=y | ||
| 546 | # CONFIG_DEBUG_GPIO is not set | ||
| 547 | # CONFIG_GPIO_SYSFS is not set | ||
| 548 | |||
| 549 | # | ||
| 550 | # Memory mapped GPIO expanders: | ||
| 551 | # | ||
| 552 | |||
| 553 | # | ||
| 554 | # I2C GPIO expanders: | ||
| 555 | # | ||
| 556 | |||
| 557 | # | ||
| 558 | # PCI GPIO expanders: | ||
| 559 | # | ||
| 560 | |||
| 561 | # | ||
| 562 | # SPI GPIO expanders: | ||
| 563 | # | ||
| 564 | |||
| 565 | # | ||
| 566 | # AC97 GPIO expanders: | ||
| 567 | # | ||
| 568 | # CONFIG_W1 is not set | ||
| 569 | # CONFIG_POWER_SUPPLY is not set | ||
| 570 | # CONFIG_HWMON is not set | ||
| 571 | # CONFIG_THERMAL is not set | ||
| 572 | # CONFIG_WATCHDOG is not set | ||
| 573 | CONFIG_SSB_POSSIBLE=y | ||
| 574 | |||
| 575 | # | ||
| 576 | # Sonics Silicon Backplane | ||
| 577 | # | ||
| 578 | # CONFIG_SSB is not set | ||
| 579 | |||
| 580 | # | ||
| 581 | # Multifunction device drivers | ||
| 582 | # | ||
| 583 | # CONFIG_MFD_CORE is not set | ||
| 584 | # CONFIG_MFD_SM501 is not set | ||
| 585 | # CONFIG_MFD_ASIC3 is not set | ||
| 586 | # CONFIG_HTC_EGPIO is not set | ||
| 587 | # CONFIG_HTC_PASIC3 is not set | ||
| 588 | # CONFIG_MFD_TMIO is not set | ||
| 589 | # CONFIG_MFD_T7L66XB is not set | ||
| 590 | # CONFIG_MFD_TC6387XB is not set | ||
| 591 | # CONFIG_MFD_TC6393XB is not set | ||
| 592 | # CONFIG_REGULATOR is not set | ||
| 593 | # CONFIG_MEDIA_SUPPORT is not set | ||
| 594 | |||
| 595 | # | ||
| 596 | # Graphics support | ||
| 597 | # | ||
| 598 | # CONFIG_VGASTATE is not set | ||
| 599 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 600 | # CONFIG_FB is not set | ||
| 601 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 602 | |||
| 603 | # | ||
| 604 | # Display device support | ||
| 605 | # | ||
| 606 | CONFIG_DISPLAY_SUPPORT=y | ||
| 607 | |||
| 608 | # | ||
| 609 | # Display hardware drivers | ||
| 610 | # | ||
| 611 | |||
| 612 | # | ||
| 613 | # Console display driver support | ||
| 614 | # | ||
| 615 | # CONFIG_VGA_CONSOLE is not set | ||
| 616 | CONFIG_DUMMY_CONSOLE=y | ||
| 617 | # CONFIG_SOUND is not set | ||
| 618 | # CONFIG_HID_SUPPORT is not set | ||
| 619 | # CONFIG_USB_SUPPORT is not set | ||
| 620 | # CONFIG_MMC is not set | ||
| 621 | # CONFIG_MEMSTICK is not set | ||
| 622 | # CONFIG_NEW_LEDS is not set | ||
| 623 | # CONFIG_ACCESSIBILITY is not set | ||
| 624 | CONFIG_RTC_LIB=y | ||
| 625 | # CONFIG_RTC_CLASS is not set | ||
| 626 | # CONFIG_DMADEVICES is not set | ||
| 627 | # CONFIG_AUXDISPLAY is not set | ||
| 628 | # CONFIG_UIO is not set | ||
| 629 | |||
| 630 | # | ||
| 631 | # TI VLYNQ | ||
| 632 | # | ||
| 633 | # CONFIG_STAGING is not set | ||
| 634 | |||
| 635 | # | ||
| 636 | # File systems | ||
| 637 | # | ||
| 638 | CONFIG_EXT2_FS=y | ||
| 639 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 640 | # CONFIG_EXT2_FS_XIP is not set | ||
| 641 | CONFIG_EXT3_FS=y | ||
| 642 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
| 643 | CONFIG_EXT3_FS_XATTR=y | ||
| 644 | CONFIG_EXT3_FS_POSIX_ACL=y | ||
| 645 | CONFIG_EXT3_FS_SECURITY=y | ||
| 646 | # CONFIG_EXT4_FS is not set | ||
| 647 | CONFIG_JBD=y | ||
| 648 | CONFIG_FS_MBCACHE=y | ||
| 649 | # CONFIG_REISERFS_FS is not set | ||
| 650 | # CONFIG_JFS_FS is not set | ||
| 651 | CONFIG_FS_POSIX_ACL=y | ||
| 652 | # CONFIG_XFS_FS is not set | ||
| 653 | # CONFIG_GFS2_FS is not set | ||
| 654 | # CONFIG_BTRFS_FS is not set | ||
| 655 | # CONFIG_NILFS2_FS is not set | ||
| 656 | CONFIG_FILE_LOCKING=y | ||
| 657 | CONFIG_FSNOTIFY=y | ||
| 658 | CONFIG_DNOTIFY=y | ||
| 659 | CONFIG_INOTIFY=y | ||
| 660 | CONFIG_INOTIFY_USER=y | ||
| 661 | # CONFIG_QUOTA is not set | ||
| 662 | # CONFIG_AUTOFS_FS is not set | ||
| 663 | # CONFIG_AUTOFS4_FS is not set | ||
| 664 | # CONFIG_FUSE_FS is not set | ||
| 665 | CONFIG_GENERIC_ACL=y | ||
| 666 | |||
| 667 | # | ||
| 668 | # Caches | ||
| 669 | # | ||
| 670 | # CONFIG_FSCACHE is not set | ||
| 671 | |||
| 672 | # | ||
| 673 | # CD-ROM/DVD Filesystems | ||
| 674 | # | ||
| 675 | # CONFIG_ISO9660_FS is not set | ||
| 676 | # CONFIG_UDF_FS is not set | ||
| 677 | |||
| 678 | # | ||
| 679 | # DOS/FAT/NT Filesystems | ||
| 680 | # | ||
| 681 | CONFIG_FAT_FS=y | ||
| 682 | CONFIG_MSDOS_FS=y | ||
| 683 | CONFIG_VFAT_FS=y | ||
| 684 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 685 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 686 | # CONFIG_NTFS_FS is not set | ||
| 687 | |||
| 688 | # | ||
| 689 | # Pseudo filesystems | ||
| 690 | # | ||
| 691 | CONFIG_PROC_FS=y | ||
| 692 | CONFIG_PROC_SYSCTL=y | ||
| 693 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 694 | CONFIG_SYSFS=y | ||
| 695 | CONFIG_TMPFS=y | ||
| 696 | CONFIG_TMPFS_POSIX_ACL=y | ||
| 697 | # CONFIG_HUGETLB_PAGE is not set | ||
| 698 | # CONFIG_CONFIGFS_FS is not set | ||
| 699 | CONFIG_MISC_FILESYSTEMS=y | ||
| 700 | # CONFIG_ADFS_FS is not set | ||
| 701 | # CONFIG_AFFS_FS is not set | ||
| 702 | # CONFIG_HFS_FS is not set | ||
| 703 | # CONFIG_HFSPLUS_FS is not set | ||
| 704 | # CONFIG_BEFS_FS is not set | ||
| 705 | # CONFIG_BFS_FS is not set | ||
| 706 | # CONFIG_EFS_FS is not set | ||
| 707 | CONFIG_CRAMFS=y | ||
| 708 | # CONFIG_SQUASHFS is not set | ||
| 709 | # CONFIG_VXFS_FS is not set | ||
| 710 | # CONFIG_MINIX_FS is not set | ||
| 711 | # CONFIG_OMFS_FS is not set | ||
| 712 | # CONFIG_HPFS_FS is not set | ||
| 713 | # CONFIG_QNX4FS_FS is not set | ||
| 714 | CONFIG_ROMFS_FS=y | ||
| 715 | CONFIG_ROMFS_BACKED_BY_BLOCK=y | ||
| 716 | # CONFIG_ROMFS_BACKED_BY_MTD is not set | ||
| 717 | # CONFIG_ROMFS_BACKED_BY_BOTH is not set | ||
| 718 | CONFIG_ROMFS_ON_BLOCK=y | ||
| 719 | # CONFIG_SYSV_FS is not set | ||
| 720 | # CONFIG_UFS_FS is not set | ||
| 721 | |||
| 722 | # | ||
| 723 | # Partition Types | ||
| 724 | # | ||
| 725 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 726 | CONFIG_MSDOS_PARTITION=y | ||
| 727 | CONFIG_NLS=y | ||
| 728 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 729 | CONFIG_NLS_CODEPAGE_437=y | ||
| 730 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 731 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 732 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 733 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 734 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 735 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 736 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 737 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 738 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 739 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 740 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 741 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 742 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 743 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 744 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 745 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 746 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 747 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 748 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 749 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 750 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 751 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 752 | CONFIG_NLS_ASCII=y | ||
| 753 | CONFIG_NLS_ISO8859_1=y | ||
| 754 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 755 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 756 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 757 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 758 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 759 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 760 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 761 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 762 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 763 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 764 | # CONFIG_NLS_KOI8_R is not set | ||
| 765 | # CONFIG_NLS_KOI8_U is not set | ||
| 766 | # CONFIG_NLS_UTF8 is not set | ||
| 767 | |||
| 768 | # | ||
| 769 | # Kernel hacking | ||
| 770 | # | ||
| 771 | # CONFIG_PRINTK_TIME is not set | ||
| 772 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 773 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 774 | CONFIG_FRAME_WARN=1024 | ||
| 775 | CONFIG_MAGIC_SYSRQ=y | ||
| 776 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 777 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 778 | # CONFIG_DEBUG_FS is not set | ||
| 779 | # CONFIG_HEADERS_CHECK is not set | ||
| 780 | CONFIG_DEBUG_KERNEL=y | ||
| 781 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 782 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 783 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 784 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 785 | CONFIG_DETECT_HUNG_TASK=y | ||
| 786 | # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set | ||
| 787 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 | ||
| 788 | CONFIG_SCHED_DEBUG=y | ||
| 789 | # CONFIG_SCHEDSTATS is not set | ||
| 790 | # CONFIG_TIMER_STATS is not set | ||
| 791 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 792 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 793 | # CONFIG_SLUB_STATS is not set | ||
| 794 | # CONFIG_DEBUG_KMEMLEAK is not set | ||
| 795 | CONFIG_DEBUG_RT_MUTEXES=y | ||
| 796 | CONFIG_DEBUG_PI_LIST=y | ||
| 797 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 798 | CONFIG_DEBUG_SPINLOCK=y | ||
| 799 | CONFIG_DEBUG_MUTEXES=y | ||
| 800 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 801 | # CONFIG_PROVE_LOCKING is not set | ||
| 802 | # CONFIG_LOCK_STAT is not set | ||
| 803 | CONFIG_DEBUG_SPINLOCK_SLEEP=y | ||
| 804 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 805 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 806 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 807 | CONFIG_DEBUG_INFO=y | ||
| 808 | # CONFIG_DEBUG_VM is not set | ||
| 809 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 810 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 811 | # CONFIG_DEBUG_LIST is not set | ||
| 812 | # CONFIG_DEBUG_SG is not set | ||
| 813 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 814 | # CONFIG_DEBUG_CREDENTIALS is not set | ||
| 815 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 816 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 817 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 818 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 819 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 820 | # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set | ||
| 821 | # CONFIG_FAULT_INJECTION is not set | ||
| 822 | # CONFIG_LATENCYTOP is not set | ||
| 823 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 824 | # CONFIG_PAGE_POISONING is not set | ||
| 825 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 826 | CONFIG_TRACING_SUPPORT=y | ||
| 827 | CONFIG_FTRACE=y | ||
| 828 | # CONFIG_FUNCTION_TRACER is not set | ||
| 829 | # CONFIG_SCHED_TRACER is not set | ||
| 830 | # CONFIG_ENABLE_DEFAULT_TRACERS is not set | ||
| 831 | # CONFIG_BOOT_TRACER is not set | ||
| 832 | CONFIG_BRANCH_PROFILE_NONE=y | ||
| 833 | # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set | ||
| 834 | # CONFIG_PROFILE_ALL_BRANCHES is not set | ||
| 835 | # CONFIG_STACK_TRACER is not set | ||
| 836 | # CONFIG_KMEMTRACE is not set | ||
| 837 | # CONFIG_WORKQUEUE_TRACER is not set | ||
| 838 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 839 | # CONFIG_SAMPLES is not set | ||
| 840 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 841 | # CONFIG_KGDB is not set | ||
| 842 | CONFIG_ARM_UNWIND=y | ||
| 843 | CONFIG_DEBUG_USER=y | ||
| 844 | CONFIG_DEBUG_ERRORS=y | ||
| 845 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 846 | CONFIG_DEBUG_LL=y | ||
| 847 | # CONFIG_EARLY_PRINTK is not set | ||
| 848 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 849 | # CONFIG_OC_ETM is not set | ||
| 850 | CONFIG_DEBUG_S3C_UART=1 | ||
| 851 | |||
| 852 | # | ||
| 853 | # Security options | ||
| 854 | # | ||
| 855 | # CONFIG_KEYS is not set | ||
| 856 | # CONFIG_SECURITY is not set | ||
| 857 | # CONFIG_SECURITYFS is not set | ||
| 858 | # CONFIG_DEFAULT_SECURITY_SELINUX is not set | ||
| 859 | # CONFIG_DEFAULT_SECURITY_SMACK is not set | ||
| 860 | # CONFIG_DEFAULT_SECURITY_TOMOYO is not set | ||
| 861 | CONFIG_DEFAULT_SECURITY_DAC=y | ||
| 862 | CONFIG_DEFAULT_SECURITY="" | ||
| 863 | CONFIG_CRYPTO=y | ||
| 864 | |||
| 865 | # | ||
| 866 | # Crypto core or helper | ||
| 867 | # | ||
| 868 | # CONFIG_CRYPTO_MANAGER is not set | ||
| 869 | # CONFIG_CRYPTO_MANAGER2 is not set | ||
| 870 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 871 | # CONFIG_CRYPTO_NULL is not set | ||
| 872 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 873 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 874 | # CONFIG_CRYPTO_TEST is not set | ||
| 875 | |||
| 876 | # | ||
| 877 | # Authenticated Encryption with Associated Data | ||
| 878 | # | ||
| 879 | # CONFIG_CRYPTO_CCM is not set | ||
| 880 | # CONFIG_CRYPTO_GCM is not set | ||
| 881 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 882 | |||
| 883 | # | ||
| 884 | # Block modes | ||
| 885 | # | ||
| 886 | # CONFIG_CRYPTO_CBC is not set | ||
| 887 | # CONFIG_CRYPTO_CTR is not set | ||
| 888 | # CONFIG_CRYPTO_CTS is not set | ||
| 889 | # CONFIG_CRYPTO_ECB is not set | ||
| 890 | # CONFIG_CRYPTO_LRW is not set | ||
| 891 | # CONFIG_CRYPTO_PCBC is not set | ||
| 892 | # CONFIG_CRYPTO_XTS is not set | ||
| 893 | |||
| 894 | # | ||
| 895 | # Hash modes | ||
| 896 | # | ||
| 897 | # CONFIG_CRYPTO_HMAC is not set | ||
| 898 | # CONFIG_CRYPTO_XCBC is not set | ||
| 899 | # CONFIG_CRYPTO_VMAC is not set | ||
| 900 | |||
| 901 | # | ||
| 902 | # Digest | ||
| 903 | # | ||
| 904 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 905 | # CONFIG_CRYPTO_GHASH is not set | ||
| 906 | # CONFIG_CRYPTO_MD4 is not set | ||
| 907 | # CONFIG_CRYPTO_MD5 is not set | ||
| 908 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 909 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 910 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 911 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 912 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 913 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 914 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 915 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 916 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 917 | # CONFIG_CRYPTO_WP512 is not set | ||
| 918 | |||
| 919 | # | ||
| 920 | # Ciphers | ||
| 921 | # | ||
| 922 | # CONFIG_CRYPTO_AES is not set | ||
| 923 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 924 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 925 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 926 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 927 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 928 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 929 | # CONFIG_CRYPTO_DES is not set | ||
| 930 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 931 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 932 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 933 | # CONFIG_CRYPTO_SEED is not set | ||
| 934 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 935 | # CONFIG_CRYPTO_TEA is not set | ||
| 936 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 937 | |||
| 938 | # | ||
| 939 | # Compression | ||
| 940 | # | ||
| 941 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 942 | # CONFIG_CRYPTO_ZLIB is not set | ||
| 943 | # CONFIG_CRYPTO_LZO is not set | ||
| 944 | |||
| 945 | # | ||
| 946 | # Random Number Generation | ||
| 947 | # | ||
| 948 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 949 | CONFIG_CRYPTO_HW=y | ||
| 950 | # CONFIG_BINARY_PRINTF is not set | ||
| 951 | |||
| 952 | # | ||
| 953 | # Library routines | ||
| 954 | # | ||
| 955 | CONFIG_BITREVERSE=y | ||
| 956 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 957 | CONFIG_CRC_CCITT=y | ||
| 958 | # CONFIG_CRC16 is not set | ||
| 959 | # CONFIG_CRC_T10DIF is not set | ||
| 960 | # CONFIG_CRC_ITU_T is not set | ||
| 961 | CONFIG_CRC32=y | ||
| 962 | # CONFIG_CRC7 is not set | ||
| 963 | # CONFIG_LIBCRC32C is not set | ||
| 964 | CONFIG_ZLIB_INFLATE=y | ||
| 965 | CONFIG_DECOMPRESS_GZIP=y | ||
| 966 | CONFIG_DECOMPRESS_BZIP2=y | ||
| 967 | CONFIG_DECOMPRESS_LZMA=y | ||
| 968 | CONFIG_HAS_IOMEM=y | ||
| 969 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/include/asm/entry-macro-vic2.S b/arch/arm/include/asm/entry-macro-vic2.S new file mode 100644 index 000000000000..3ceb85e43850 --- /dev/null +++ b/arch/arm/include/asm/entry-macro-vic2.S | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | /* arch/arm/include/asm/entry-macro-vic2.S | ||
| 2 | * | ||
| 3 | * Originally arch/arm/mach-s3c6400/include/mach/entry-macro.S | ||
| 4 | * | ||
| 5 | * Copyright 2008 Openmoko, Inc. | ||
| 6 | * Copyright 2008 Simtec Electronics | ||
| 7 | * http://armlinux.simtec.co.uk/ | ||
| 8 | * Ben Dooks <ben@simtec.co.uk> | ||
| 9 | * | ||
| 10 | * Low-level IRQ helper macros for a device with two VICs | ||
| 11 | * | ||
| 12 | * This file is licensed under the terms of the GNU General Public | ||
| 13 | * License version 2. This program is licensed "as is" without any | ||
| 14 | * warranty of any kind, whether express or implied. | ||
| 15 | */ | ||
| 16 | |||
| 17 | /* This should be included from <mach/entry-macro.S> with the necessary | ||
| 18 | * defines for virtual addresses and IRQ bases for the two vics. | ||
| 19 | * | ||
| 20 | * The code needs the following defined: | ||
| 21 | * IRQ_VIC0_BASE IRQ number of VIC0's first IRQ | ||
| 22 | * IRQ_VIC1_BASE IRQ number of VIC1's first IRQ | ||
| 23 | * VA_VIC0 Virtual address of VIC0 | ||
| 24 | * VA_VIC1 Virtual address of VIC1 | ||
| 25 | * | ||
| 26 | * Note, code assumes VIC0's virtual address is an ARM immediate constant | ||
| 27 | * away from VIC1. | ||
| 28 | */ | ||
| 29 | |||
| 30 | #include <asm/hardware/vic.h> | ||
| 31 | |||
| 32 | .macro disable_fiq | ||
| 33 | .endm | ||
| 34 | |||
| 35 | .macro get_irqnr_preamble, base, tmp | ||
| 36 | ldr \base, =VA_VIC0 | ||
| 37 | .endm | ||
| 38 | |||
| 39 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 40 | .endm | ||
| 41 | |||
| 42 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 43 | |||
| 44 | @ check the vic0 | ||
| 45 | mov \irqnr, #IRQ_VIC0_BASE + 31 | ||
| 46 | ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] | ||
| 47 | teq \irqstat, #0 | ||
| 48 | |||
| 49 | @ otherwise try vic1 | ||
| 50 | addeq \tmp, \base, #(VA_VIC1 - VA_VIC0) | ||
| 51 | addeq \irqnr, \irqnr, #(IRQ_VIC1_BASE - IRQ_VIC0_BASE) | ||
| 52 | ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] | ||
| 53 | teqeq \irqstat, #0 | ||
| 54 | |||
| 55 | clzne \irqstat, \irqstat | ||
| 56 | subne \irqnr, \irqnr, \irqstat | ||
| 57 | .endm | ||
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index dee92182749b..385c30ee3f23 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig | |||
| @@ -417,6 +417,24 @@ config MACH_TREO680 | |||
| 417 | Say Y here if you intend to run this kernel on Palm Treo 680 | 417 | Say Y here if you intend to run this kernel on Palm Treo 680 |
| 418 | smartphone. | 418 | smartphone. |
| 419 | 419 | ||
| 420 | config MACH_RAUMFELD_RC | ||
| 421 | bool "Raumfeld Controller" | ||
| 422 | select PXA3xx | ||
| 423 | select CPU_PXA300 | ||
| 424 | select HAVE_PWM | ||
| 425 | |||
| 426 | config MACH_RAUMFELD_CONNECTOR | ||
| 427 | bool "Raumfeld Connector" | ||
| 428 | select PXA3xx | ||
| 429 | select CPU_PXA300 | ||
| 430 | select PXA_SSP | ||
| 431 | |||
| 432 | config MACH_RAUMFELD_SPEAKER | ||
| 433 | bool "Raumfeld Speaker" | ||
| 434 | select PXA3xx | ||
| 435 | select CPU_PXA300 | ||
| 436 | select PXA_SSP | ||
| 437 | |||
| 420 | config PXA_SHARPSL | 438 | config PXA_SHARPSL |
| 421 | bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models" | 439 | bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models" |
| 422 | select SHARP_SCOOP | 440 | select SHARP_SCOOP |
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index f64afda7e6f6..9d831939b3c5 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile | |||
| @@ -89,6 +89,9 @@ obj-$(CONFIG_MACH_E740) += e740.o | |||
| 89 | obj-$(CONFIG_MACH_E750) += e750.o | 89 | obj-$(CONFIG_MACH_E750) += e750.o |
| 90 | obj-$(CONFIG_MACH_E400) += e400.o | 90 | obj-$(CONFIG_MACH_E400) += e400.o |
| 91 | obj-$(CONFIG_MACH_E800) += e800.o | 91 | obj-$(CONFIG_MACH_E800) += e800.o |
| 92 | obj-$(CONFIG_MACH_RAUMFELD_RC) += raumfeld.o | ||
| 93 | obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR) += raumfeld.o | ||
| 94 | obj-$(CONFIG_MACH_RAUMFELD_SPEAKER) += raumfeld.o | ||
| 92 | 95 | ||
| 93 | # Support for blinky lights | 96 | # Support for blinky lights |
| 94 | led-y := leds.o | 97 | led-y := leds.o |
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c new file mode 100644 index 000000000000..06717d7995cb --- /dev/null +++ b/arch/arm/mach-pxa/raumfeld.c | |||
| @@ -0,0 +1,1100 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-pxa/raumfeld.c | ||
| 3 | * | ||
| 4 | * Support for the following Raumfeld devices: | ||
| 5 | * | ||
| 6 | * * Controller | ||
| 7 | * * Connector | ||
| 8 | * * Speaker S/M | ||
| 9 | * | ||
| 10 | * See http://www.raumfeld.com for details. | ||
| 11 | * | ||
| 12 | * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/init.h> | ||
| 20 | #include <linux/kernel.h> | ||
| 21 | #include <linux/sysdev.h> | ||
| 22 | #include <linux/platform_device.h> | ||
| 23 | #include <linux/interrupt.h> | ||
| 24 | #include <linux/gpio.h> | ||
| 25 | #include <linux/smsc911x.h> | ||
| 26 | #include <linux/input.h> | ||
| 27 | #include <linux/rotary_encoder.h> | ||
| 28 | #include <linux/gpio_keys.h> | ||
| 29 | #include <linux/input/eeti_ts.h> | ||
| 30 | #include <linux/leds.h> | ||
| 31 | #include <linux/w1-gpio.h> | ||
| 32 | #include <linux/sched.h> | ||
| 33 | #include <linux/pwm_backlight.h> | ||
| 34 | #include <linux/i2c.h> | ||
| 35 | #include <linux/spi/spi.h> | ||
| 36 | #include <linux/spi/spi_gpio.h> | ||
| 37 | #include <linux/lis3lv02d.h> | ||
| 38 | #include <linux/pda_power.h> | ||
| 39 | #include <linux/power_supply.h> | ||
| 40 | #include <linux/pda_power.h> | ||
| 41 | #include <linux/power_supply.h> | ||
| 42 | #include <linux/regulator/max8660.h> | ||
| 43 | #include <linux/regulator/machine.h> | ||
| 44 | #include <linux/regulator/fixed.h> | ||
| 45 | #include <linux/regulator/consumer.h> | ||
| 46 | #include <linux/delay.h> | ||
| 47 | |||
| 48 | #include <asm/mach-types.h> | ||
| 49 | #include <asm/mach/arch.h> | ||
| 50 | |||
| 51 | #include <mach/hardware.h> | ||
| 52 | #include <mach/pxa3xx-regs.h> | ||
| 53 | #include <mach/mfp-pxa3xx.h> | ||
| 54 | #include <mach/mfp-pxa300.h> | ||
| 55 | #include <mach/ohci.h> | ||
| 56 | #include <mach/pxafb.h> | ||
| 57 | #include <mach/mmc.h> | ||
| 58 | #include <plat/i2c.h> | ||
| 59 | #include <plat/pxa3xx_nand.h> | ||
| 60 | |||
| 61 | #include "generic.h" | ||
| 62 | #include "devices.h" | ||
| 63 | #include "clock.h" | ||
| 64 | |||
| 65 | /* common GPIO definitions */ | ||
| 66 | |||
| 67 | /* inputs */ | ||
| 68 | #define GPIO_ON_OFF (14) | ||
| 69 | #define GPIO_VOLENC_A (19) | ||
| 70 | #define GPIO_VOLENC_B (20) | ||
| 71 | #define GPIO_CHARGE_DONE (23) | ||
| 72 | #define GPIO_CHARGE_IND (27) | ||
| 73 | #define GPIO_TOUCH_IRQ (32) | ||
| 74 | #define GPIO_ETH_IRQ (40) | ||
| 75 | #define GPIO_SPI_MISO (98) | ||
| 76 | #define GPIO_ACCEL_IRQ (104) | ||
| 77 | #define GPIO_RESCUE_BOOT (115) | ||
| 78 | #define GPIO_DOCK_DETECT (116) | ||
| 79 | #define GPIO_KEY1 (117) | ||
| 80 | #define GPIO_KEY2 (118) | ||
| 81 | #define GPIO_KEY3 (119) | ||
| 82 | #define GPIO_CHARGE_USB_OK (112) | ||
| 83 | #define GPIO_CHARGE_DC_OK (101) | ||
| 84 | #define GPIO_CHARGE_USB_SUSP (102) | ||
| 85 | |||
| 86 | /* outputs */ | ||
| 87 | #define GPIO_SHUTDOWN_SUPPLY (16) | ||
| 88 | #define GPIO_SHUTDOWN_BATT (18) | ||
| 89 | #define GPIO_CHRG_PEN2 (31) | ||
| 90 | #define GPIO_TFT_VA_EN (33) | ||
| 91 | #define GPIO_SPDIF_CS (34) | ||
| 92 | #define GPIO_LED2 (35) | ||
| 93 | #define GPIO_LED1 (36) | ||
| 94 | #define GPIO_SPDIF_RESET (38) | ||
| 95 | #define GPIO_SPI_CLK (95) | ||
| 96 | #define GPIO_MCLK_DAC_CS (96) | ||
| 97 | #define GPIO_SPI_MOSI (97) | ||
| 98 | #define GPIO_W1_PULLUP_ENABLE (105) | ||
| 99 | #define GPIO_DISPLAY_ENABLE (106) | ||
| 100 | #define GPIO_MCLK_RESET (111) | ||
| 101 | #define GPIO_W2W_RESET (113) | ||
| 102 | #define GPIO_W2W_PDN (114) | ||
| 103 | #define GPIO_CODEC_RESET (120) | ||
| 104 | #define GPIO_AUDIO_VA_ENABLE (124) | ||
| 105 | #define GPIO_ACCEL_CS (125) | ||
| 106 | #define GPIO_ONE_WIRE (126) | ||
| 107 | |||
| 108 | /* | ||
| 109 | * GPIO configurations | ||
| 110 | */ | ||
| 111 | static mfp_cfg_t raumfeld_controller_pin_config[] __initdata = { | ||
| 112 | /* UART1 */ | ||
| 113 | GPIO77_UART1_RXD, | ||
| 114 | GPIO78_UART1_TXD, | ||
| 115 | GPIO79_UART1_CTS, | ||
| 116 | GPIO81_UART1_DSR, | ||
| 117 | GPIO83_UART1_DTR, | ||
| 118 | GPIO84_UART1_RTS, | ||
| 119 | |||
| 120 | /* UART3 */ | ||
| 121 | GPIO110_UART3_RXD, | ||
| 122 | |||
| 123 | /* USB Host */ | ||
| 124 | GPIO0_2_USBH_PEN, | ||
| 125 | GPIO1_2_USBH_PWR, | ||
| 126 | |||
| 127 | /* I2C */ | ||
| 128 | GPIO21_I2C_SCL | MFP_LPM_FLOAT | MFP_PULL_FLOAT, | ||
| 129 | GPIO22_I2C_SDA | MFP_LPM_FLOAT | MFP_PULL_FLOAT, | ||
| 130 | |||
| 131 | /* SPI */ | ||
| 132 | GPIO34_GPIO, /* SPDIF_CS */ | ||
| 133 | GPIO96_GPIO, /* MCLK_CS */ | ||
| 134 | GPIO125_GPIO, /* ACCEL_CS */ | ||
| 135 | |||
| 136 | /* MMC */ | ||
| 137 | GPIO3_MMC1_DAT0, | ||
| 138 | GPIO4_MMC1_DAT1, | ||
| 139 | GPIO5_MMC1_DAT2, | ||
| 140 | GPIO6_MMC1_DAT3, | ||
| 141 | GPIO7_MMC1_CLK, | ||
| 142 | GPIO8_MMC1_CMD, | ||
| 143 | |||
| 144 | /* One-wire */ | ||
| 145 | GPIO126_GPIO | MFP_LPM_FLOAT, | ||
| 146 | GPIO105_GPIO | MFP_PULL_LOW | MFP_LPM_PULL_LOW, | ||
| 147 | |||
| 148 | /* CHRG_USB_OK */ | ||
| 149 | GPIO101_GPIO | MFP_PULL_HIGH, | ||
| 150 | /* CHRG_USB_OK */ | ||
| 151 | GPIO112_GPIO | MFP_PULL_HIGH, | ||
| 152 | /* CHRG_USB_SUSP */ | ||
| 153 | GPIO102_GPIO, | ||
| 154 | /* DISPLAY_ENABLE */ | ||
| 155 | GPIO106_GPIO, | ||
| 156 | /* DOCK_DETECT */ | ||
| 157 | GPIO116_GPIO | MFP_LPM_FLOAT | MFP_PULL_FLOAT, | ||
| 158 | |||
| 159 | /* LCD */ | ||
| 160 | GPIO54_LCD_LDD_0, | ||
| 161 | GPIO55_LCD_LDD_1, | ||
| 162 | GPIO56_LCD_LDD_2, | ||
| 163 | GPIO57_LCD_LDD_3, | ||
| 164 | GPIO58_LCD_LDD_4, | ||
| 165 | GPIO59_LCD_LDD_5, | ||
| 166 | GPIO60_LCD_LDD_6, | ||
| 167 | GPIO61_LCD_LDD_7, | ||
| 168 | GPIO62_LCD_LDD_8, | ||
| 169 | GPIO63_LCD_LDD_9, | ||
| 170 | GPIO64_LCD_LDD_10, | ||
| 171 | GPIO65_LCD_LDD_11, | ||
| 172 | GPIO66_LCD_LDD_12, | ||
| 173 | GPIO67_LCD_LDD_13, | ||
| 174 | GPIO68_LCD_LDD_14, | ||
| 175 | GPIO69_LCD_LDD_15, | ||
| 176 | GPIO70_LCD_LDD_16, | ||
| 177 | GPIO71_LCD_LDD_17, | ||
| 178 | GPIO72_LCD_FCLK, | ||
| 179 | GPIO73_LCD_LCLK, | ||
| 180 | GPIO74_LCD_PCLK, | ||
| 181 | GPIO75_LCD_BIAS, | ||
| 182 | }; | ||
| 183 | |||
| 184 | static mfp_cfg_t raumfeld_connector_pin_config[] __initdata = { | ||
| 185 | /* UART1 */ | ||
| 186 | GPIO77_UART1_RXD, | ||
| 187 | GPIO78_UART1_TXD, | ||
| 188 | GPIO79_UART1_CTS, | ||
| 189 | GPIO81_UART1_DSR, | ||
| 190 | GPIO83_UART1_DTR, | ||
| 191 | GPIO84_UART1_RTS, | ||
| 192 | |||
| 193 | /* UART3 */ | ||
| 194 | GPIO110_UART3_RXD, | ||
| 195 | |||
| 196 | /* USB Host */ | ||
| 197 | GPIO0_2_USBH_PEN, | ||
| 198 | GPIO1_2_USBH_PWR, | ||
| 199 | |||
| 200 | /* I2C */ | ||
| 201 | GPIO21_I2C_SCL | MFP_LPM_FLOAT | MFP_PULL_FLOAT, | ||
| 202 | GPIO22_I2C_SDA | MFP_LPM_FLOAT | MFP_PULL_FLOAT, | ||
| 203 | |||
| 204 | /* SPI */ | ||
| 205 | GPIO34_GPIO, /* SPDIF_CS */ | ||
| 206 | GPIO96_GPIO, /* MCLK_CS */ | ||
| 207 | GPIO125_GPIO, /* ACCEL_CS */ | ||
| 208 | |||
| 209 | /* MMC */ | ||
| 210 | GPIO3_MMC1_DAT0, | ||
| 211 | GPIO4_MMC1_DAT1, | ||
| 212 | GPIO5_MMC1_DAT2, | ||
| 213 | GPIO6_MMC1_DAT3, | ||
| 214 | GPIO7_MMC1_CLK, | ||
| 215 | GPIO8_MMC1_CMD, | ||
| 216 | |||
| 217 | /* Ethernet */ | ||
| 218 | GPIO1_nCS2, /* CS */ | ||
| 219 | GPIO40_GPIO | MFP_PULL_HIGH, /* IRQ */ | ||
| 220 | |||
| 221 | /* SSP for I2S */ | ||
| 222 | GPIO85_SSP1_SCLK, | ||
| 223 | GPIO89_SSP1_EXTCLK, | ||
| 224 | GPIO86_SSP1_FRM, | ||
| 225 | GPIO87_SSP1_TXD, | ||
| 226 | GPIO88_SSP1_RXD, | ||
| 227 | GPIO90_SSP1_SYSCLK, | ||
| 228 | |||
| 229 | /* SSP2 for S/PDIF */ | ||
| 230 | GPIO25_SSP2_SCLK, | ||
| 231 | GPIO26_SSP2_FRM, | ||
| 232 | GPIO27_SSP2_TXD, | ||
| 233 | GPIO29_SSP2_EXTCLK, | ||
| 234 | }; | ||
| 235 | |||
| 236 | static mfp_cfg_t raumfeld_speaker_pin_config[] __initdata = { | ||
| 237 | /* UART1 */ | ||
| 238 | GPIO77_UART1_RXD, | ||
| 239 | GPIO78_UART1_TXD, | ||
| 240 | GPIO79_UART1_CTS, | ||
| 241 | GPIO81_UART1_DSR, | ||
| 242 | GPIO83_UART1_DTR, | ||
| 243 | GPIO84_UART1_RTS, | ||
| 244 | |||
| 245 | /* UART3 */ | ||
| 246 | GPIO110_UART3_RXD, | ||
| 247 | |||
| 248 | /* USB Host */ | ||
| 249 | GPIO0_2_USBH_PEN, | ||
| 250 | GPIO1_2_USBH_PWR, | ||
| 251 | |||
| 252 | /* I2C */ | ||
| 253 | GPIO21_I2C_SCL | MFP_LPM_FLOAT | MFP_PULL_FLOAT, | ||
| 254 | GPIO22_I2C_SDA | MFP_LPM_FLOAT | MFP_PULL_FLOAT, | ||
| 255 | |||
| 256 | /* SPI */ | ||
| 257 | GPIO34_GPIO, /* SPDIF_CS */ | ||
| 258 | GPIO96_GPIO, /* MCLK_CS */ | ||
| 259 | GPIO125_GPIO, /* ACCEL_CS */ | ||
| 260 | |||
| 261 | /* MMC */ | ||
| 262 | GPIO3_MMC1_DAT0, | ||
| 263 | GPIO4_MMC1_DAT1, | ||
| 264 | GPIO5_MMC1_DAT2, | ||
| 265 | GPIO6_MMC1_DAT3, | ||
| 266 | GPIO7_MMC1_CLK, | ||
| 267 | GPIO8_MMC1_CMD, | ||
| 268 | |||
| 269 | /* Ethernet */ | ||
| 270 | GPIO1_nCS2, /* CS */ | ||
| 271 | GPIO40_GPIO | MFP_PULL_HIGH, /* IRQ */ | ||
| 272 | |||
| 273 | /* SSP for I2S */ | ||
| 274 | GPIO85_SSP1_SCLK, | ||
| 275 | GPIO89_SSP1_EXTCLK, | ||
| 276 | GPIO86_SSP1_FRM, | ||
| 277 | GPIO87_SSP1_TXD, | ||
| 278 | GPIO88_SSP1_RXD, | ||
| 279 | GPIO90_SSP1_SYSCLK, | ||
| 280 | }; | ||
| 281 | |||
| 282 | /* | ||
| 283 | * SMSC LAN9220 Ethernet | ||
| 284 | */ | ||
| 285 | |||
| 286 | static struct resource smc91x_resources[] = { | ||
| 287 | { | ||
| 288 | .start = PXA3xx_CS2_PHYS, | ||
| 289 | .end = PXA3xx_CS2_PHYS + 0xfffff, | ||
| 290 | .flags = IORESOURCE_MEM, | ||
| 291 | }, | ||
| 292 | { | ||
| 293 | .start = gpio_to_irq(GPIO_ETH_IRQ), | ||
| 294 | .end = gpio_to_irq(GPIO_ETH_IRQ), | ||
| 295 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, | ||
| 296 | } | ||
| 297 | }; | ||
| 298 | |||
| 299 | static struct smsc911x_platform_config raumfeld_smsc911x_config = { | ||
| 300 | .phy_interface = PHY_INTERFACE_MODE_MII, | ||
| 301 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | ||
| 302 | .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, | ||
| 303 | .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, | ||
| 304 | }; | ||
| 305 | |||
| 306 | static struct platform_device smc91x_device = { | ||
| 307 | .name = "smsc911x", | ||
| 308 | .id = -1, | ||
| 309 | .num_resources = ARRAY_SIZE(smc91x_resources), | ||
| 310 | .resource = smc91x_resources, | ||
| 311 | .dev = { | ||
| 312 | .platform_data = &raumfeld_smsc911x_config, | ||
| 313 | } | ||
| 314 | }; | ||
| 315 | |||
| 316 | /** | ||
| 317 | * NAND | ||
| 318 | */ | ||
| 319 | |||
| 320 | static struct mtd_partition raumfeld_nand_partitions[] = { | ||
| 321 | { | ||
| 322 | .name = "Bootloader", | ||
| 323 | .offset = 0, | ||
| 324 | .size = 0xa0000, | ||
| 325 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 326 | }, | ||
| 327 | { | ||
| 328 | .name = "BootloaderEnvironment", | ||
| 329 | .offset = 0xa0000, | ||
| 330 | .size = 0x20000, | ||
| 331 | }, | ||
| 332 | { | ||
| 333 | .name = "BootloaderSplashScreen", | ||
| 334 | .offset = 0xc0000, | ||
| 335 | .size = 0x60000, | ||
| 336 | }, | ||
| 337 | { | ||
| 338 | .name = "UBI", | ||
| 339 | .offset = 0x120000, | ||
| 340 | .size = MTDPART_SIZ_FULL, | ||
| 341 | }, | ||
| 342 | }; | ||
| 343 | |||
| 344 | static struct pxa3xx_nand_platform_data raumfeld_nand_info = { | ||
| 345 | .enable_arbiter = 1, | ||
| 346 | .keep_config = 1, | ||
| 347 | .parts = raumfeld_nand_partitions, | ||
| 348 | .nr_parts = ARRAY_SIZE(raumfeld_nand_partitions), | ||
| 349 | }; | ||
| 350 | |||
| 351 | /** | ||
| 352 | * USB (OHCI) support | ||
| 353 | */ | ||
| 354 | |||
| 355 | static struct pxaohci_platform_data raumfeld_ohci_info = { | ||
| 356 | .port_mode = PMM_GLOBAL_MODE, | ||
| 357 | .flags = ENABLE_PORT1, | ||
| 358 | }; | ||
| 359 | |||
| 360 | /** | ||
| 361 | * Rotary encoder input device | ||
| 362 | */ | ||
| 363 | |||
| 364 | static struct rotary_encoder_platform_data raumfeld_rotary_encoder_info = { | ||
| 365 | .steps = 24, | ||
| 366 | .axis = REL_X, | ||
| 367 | .relative_axis = 1, | ||
| 368 | .gpio_a = GPIO_VOLENC_A, | ||
| 369 | .gpio_b = GPIO_VOLENC_B, | ||
| 370 | .inverted_a = 1, | ||
| 371 | .inverted_b = 0, | ||
| 372 | }; | ||
| 373 | |||
| 374 | static struct platform_device rotary_encoder_device = { | ||
| 375 | .name = "rotary-encoder", | ||
| 376 | .id = 0, | ||
| 377 | .dev = { | ||
| 378 | .platform_data = &raumfeld_rotary_encoder_info, | ||
| 379 | } | ||
| 380 | }; | ||
| 381 | |||
| 382 | /** | ||
| 383 | * GPIO buttons | ||
| 384 | */ | ||
| 385 | |||
| 386 | static struct gpio_keys_button gpio_keys_button[] = { | ||
| 387 | { | ||
| 388 | .code = KEY_F1, | ||
| 389 | .type = EV_KEY, | ||
| 390 | .gpio = GPIO_KEY1, | ||
| 391 | .active_low = 1, | ||
| 392 | .wakeup = 0, | ||
| 393 | .debounce_interval = 5, /* ms */ | ||
| 394 | .desc = "Button 1", | ||
| 395 | }, | ||
| 396 | { | ||
| 397 | .code = KEY_F2, | ||
| 398 | .type = EV_KEY, | ||
| 399 | .gpio = GPIO_KEY2, | ||
| 400 | .active_low = 1, | ||
| 401 | .wakeup = 0, | ||
| 402 | .debounce_interval = 5, /* ms */ | ||
| 403 | .desc = "Button 2", | ||
| 404 | }, | ||
| 405 | { | ||
| 406 | .code = KEY_F3, | ||
| 407 | .type = EV_KEY, | ||
| 408 | .gpio = GPIO_KEY3, | ||
| 409 | .active_low = 1, | ||
| 410 | .wakeup = 0, | ||
| 411 | .debounce_interval = 5, /* ms */ | ||
| 412 | .desc = "Button 3", | ||
| 413 | }, | ||
| 414 | { | ||
| 415 | .code = KEY_F4, | ||
| 416 | .type = EV_KEY, | ||
| 417 | .gpio = GPIO_RESCUE_BOOT, | ||
| 418 | .active_low = 0, | ||
| 419 | .wakeup = 0, | ||
| 420 | .debounce_interval = 5, /* ms */ | ||
| 421 | .desc = "rescue boot button", | ||
| 422 | }, | ||
| 423 | { | ||
| 424 | .code = KEY_F5, | ||
| 425 | .type = EV_KEY, | ||
| 426 | .gpio = GPIO_DOCK_DETECT, | ||
| 427 | .active_low = 1, | ||
| 428 | .wakeup = 0, | ||
| 429 | .debounce_interval = 5, /* ms */ | ||
| 430 | .desc = "dock detect", | ||
| 431 | }, | ||
| 432 | { | ||
| 433 | .code = KEY_F6, | ||
| 434 | .type = EV_KEY, | ||
| 435 | .gpio = GPIO_ON_OFF, | ||
| 436 | .active_low = 0, | ||
| 437 | .wakeup = 0, | ||
| 438 | .debounce_interval = 5, /* ms */ | ||
| 439 | .desc = "on/off button", | ||
| 440 | }, | ||
| 441 | }; | ||
| 442 | |||
| 443 | static struct gpio_keys_platform_data gpio_keys_platform_data = { | ||
| 444 | .buttons = gpio_keys_button, | ||
| 445 | .nbuttons = ARRAY_SIZE(gpio_keys_button), | ||
| 446 | .rep = 0, | ||
| 447 | }; | ||
| 448 | |||
| 449 | static struct platform_device raumfeld_gpio_keys_device = { | ||
| 450 | .name = "gpio-keys", | ||
| 451 | .id = -1, | ||
| 452 | .dev = { | ||
| 453 | .platform_data = &gpio_keys_platform_data, | ||
| 454 | } | ||
| 455 | }; | ||
| 456 | |||
| 457 | /** | ||
| 458 | * GPIO LEDs | ||
| 459 | */ | ||
| 460 | |||
| 461 | static struct gpio_led raumfeld_leds[] = { | ||
| 462 | { | ||
| 463 | .name = "raumfeld:1", | ||
| 464 | .gpio = GPIO_LED1, | ||
| 465 | .active_low = 1, | ||
| 466 | .default_state = LEDS_GPIO_DEFSTATE_ON, | ||
| 467 | }, | ||
| 468 | { | ||
| 469 | .name = "raumfeld:2", | ||
| 470 | .gpio = GPIO_LED2, | ||
| 471 | .active_low = 0, | ||
| 472 | .default_state = LEDS_GPIO_DEFSTATE_OFF, | ||
| 473 | } | ||
| 474 | }; | ||
| 475 | |||
| 476 | static struct gpio_led_platform_data raumfeld_led_platform_data = { | ||
| 477 | .leds = raumfeld_leds, | ||
| 478 | .num_leds = ARRAY_SIZE(raumfeld_leds), | ||
| 479 | }; | ||
| 480 | |||
| 481 | static struct platform_device raumfeld_led_device = { | ||
| 482 | .name = "leds-gpio", | ||
| 483 | .id = -1, | ||
| 484 | .dev = { | ||
| 485 | .platform_data = &raumfeld_led_platform_data, | ||
| 486 | }, | ||
| 487 | }; | ||
| 488 | |||
| 489 | /** | ||
| 490 | * One-wire (W1 bus) support | ||
| 491 | */ | ||
| 492 | |||
| 493 | static void w1_enable_external_pullup(int enable) | ||
| 494 | { | ||
| 495 | gpio_set_value(GPIO_W1_PULLUP_ENABLE, enable); | ||
| 496 | msleep(100); | ||
| 497 | } | ||
| 498 | |||
| 499 | static struct w1_gpio_platform_data w1_gpio_platform_data = { | ||
| 500 | .pin = GPIO_ONE_WIRE, | ||
| 501 | .is_open_drain = 0, | ||
| 502 | .enable_external_pullup = w1_enable_external_pullup, | ||
| 503 | }; | ||
| 504 | |||
| 505 | struct platform_device raumfeld_w1_gpio_device = { | ||
| 506 | .name = "w1-gpio", | ||
| 507 | .dev = { | ||
| 508 | .platform_data = &w1_gpio_platform_data | ||
| 509 | } | ||
| 510 | }; | ||
| 511 | |||
| 512 | static void __init raumfeld_w1_init(void) | ||
| 513 | { | ||
| 514 | int ret = gpio_request(GPIO_W1_PULLUP_ENABLE, | ||
| 515 | "W1 external pullup enable"); | ||
| 516 | |||
| 517 | if (ret < 0) | ||
| 518 | pr_warning("Unable to request GPIO_W1_PULLUP_ENABLE\n"); | ||
| 519 | else | ||
| 520 | gpio_direction_output(GPIO_W1_PULLUP_ENABLE, 0); | ||
| 521 | |||
| 522 | platform_device_register(&raumfeld_w1_gpio_device); | ||
| 523 | } | ||
| 524 | |||
| 525 | /** | ||
| 526 | * Framebuffer device | ||
| 527 | */ | ||
| 528 | |||
| 529 | /* PWM controlled backlight */ | ||
| 530 | static struct platform_pwm_backlight_data raumfeld_pwm_backlight_data = { | ||
| 531 | .pwm_id = 0, | ||
| 532 | .max_brightness = 100, | ||
| 533 | .dft_brightness = 100, | ||
| 534 | /* 10000 ns = 10 ms ^= 100 kHz */ | ||
| 535 | .pwm_period_ns = 10000, | ||
| 536 | }; | ||
| 537 | |||
| 538 | static struct platform_device raumfeld_pwm_backlight_device = { | ||
| 539 | .name = "pwm-backlight", | ||
| 540 | .dev = { | ||
| 541 | .parent = &pxa27x_device_pwm0.dev, | ||
| 542 | .platform_data = &raumfeld_pwm_backlight_data, | ||
| 543 | } | ||
| 544 | }; | ||
| 545 | |||
| 546 | /* LT3593 controlled backlight */ | ||
| 547 | static struct gpio_led raumfeld_lt3593_led = { | ||
| 548 | .name = "backlight", | ||
| 549 | .gpio = mfp_to_gpio(MFP_PIN_GPIO17), | ||
| 550 | .default_state = LEDS_GPIO_DEFSTATE_ON, | ||
| 551 | }; | ||
| 552 | |||
| 553 | static struct gpio_led_platform_data raumfeld_lt3593_platform_data = { | ||
| 554 | .leds = &raumfeld_lt3593_led, | ||
| 555 | .num_leds = 1, | ||
| 556 | }; | ||
| 557 | |||
| 558 | static struct platform_device raumfeld_lt3593_device = { | ||
| 559 | .name = "leds-lt3593", | ||
| 560 | .id = -1, | ||
| 561 | .dev = { | ||
| 562 | .platform_data = &raumfeld_lt3593_platform_data, | ||
| 563 | }, | ||
| 564 | }; | ||
| 565 | |||
| 566 | static struct pxafb_mode_info sharp_lq043t3dx02_mode = { | ||
| 567 | .pixclock = 111000, | ||
| 568 | .xres = 480, | ||
| 569 | .yres = 272, | ||
| 570 | .bpp = 16, | ||
| 571 | .hsync_len = 4, | ||
| 572 | .left_margin = 2, | ||
| 573 | .right_margin = 1, | ||
| 574 | .vsync_len = 1, | ||
| 575 | .upper_margin = 3, | ||
| 576 | .lower_margin = 1, | ||
| 577 | .sync = 0, | ||
| 578 | }; | ||
| 579 | |||
| 580 | static struct pxafb_mach_info raumfeld_sharp_lcd_info = { | ||
| 581 | .modes = &sharp_lq043t3dx02_mode, | ||
| 582 | .num_modes = 1, | ||
| 583 | .video_mem_size = 0x400000, | ||
| 584 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, | ||
| 585 | }; | ||
| 586 | |||
| 587 | static void __init raumfeld_lcd_init(void) | ||
| 588 | { | ||
| 589 | int ret; | ||
| 590 | |||
| 591 | set_pxa_fb_info(&raumfeld_sharp_lcd_info); | ||
| 592 | |||
| 593 | /* Earlier devices had the backlight regulator controlled | ||
| 594 | * via PWM, later versions use another controller for that */ | ||
| 595 | if ((system_rev & 0xff) < 2) { | ||
| 596 | mfp_cfg_t raumfeld_pwm_pin_config = GPIO17_PWM0_OUT; | ||
| 597 | pxa3xx_mfp_config(&raumfeld_pwm_pin_config, 1); | ||
| 598 | platform_device_register(&raumfeld_pwm_backlight_device); | ||
| 599 | } else | ||
| 600 | platform_device_register(&raumfeld_lt3593_device); | ||
| 601 | |||
| 602 | ret = gpio_request(GPIO_TFT_VA_EN, "display VA enable"); | ||
| 603 | if (ret < 0) | ||
| 604 | pr_warning("Unable to request GPIO_TFT_VA_EN\n"); | ||
| 605 | else | ||
| 606 | gpio_direction_output(GPIO_TFT_VA_EN, 1); | ||
| 607 | |||
| 608 | ret = gpio_request(GPIO_DISPLAY_ENABLE, "display enable"); | ||
| 609 | if (ret < 0) | ||
| 610 | pr_warning("Unable to request GPIO_DISPLAY_ENABLE\n"); | ||
| 611 | else | ||
| 612 | gpio_direction_output(GPIO_DISPLAY_ENABLE, 1); | ||
| 613 | } | ||
| 614 | |||
| 615 | /** | ||
| 616 | * SPI devices | ||
| 617 | */ | ||
| 618 | |||
| 619 | struct spi_gpio_platform_data raumfeld_spi_platform_data = { | ||
| 620 | .sck = GPIO_SPI_CLK, | ||
| 621 | .mosi = GPIO_SPI_MOSI, | ||
| 622 | .miso = GPIO_SPI_MISO, | ||
| 623 | .num_chipselect = 3, | ||
| 624 | }; | ||
| 625 | |||
| 626 | static struct platform_device raumfeld_spi_device = { | ||
| 627 | .name = "spi_gpio", | ||
| 628 | .id = 0, | ||
| 629 | .dev = { | ||
| 630 | .platform_data = &raumfeld_spi_platform_data, | ||
| 631 | } | ||
| 632 | }; | ||
| 633 | |||
| 634 | static struct lis3lv02d_platform_data lis3_pdata = { | ||
| 635 | .click_flags = LIS3_CLICK_SINGLE_X | | ||
| 636 | LIS3_CLICK_SINGLE_Y | | ||
| 637 | LIS3_CLICK_SINGLE_Z, | ||
| 638 | .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK, | ||
| 639 | .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI | | ||
| 640 | LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI | | ||
| 641 | LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI, | ||
| 642 | .wakeup_thresh = 10, | ||
| 643 | .click_thresh_x = 10, | ||
| 644 | .click_thresh_y = 10, | ||
| 645 | .click_thresh_z = 10, | ||
| 646 | }; | ||
| 647 | |||
| 648 | #define SPI_AK4104 \ | ||
| 649 | { \ | ||
| 650 | .modalias = "ak4104", \ | ||
| 651 | .max_speed_hz = 10000, \ | ||
| 652 | .bus_num = 0, \ | ||
| 653 | .chip_select = 0, \ | ||
| 654 | .controller_data = (void *) GPIO_SPDIF_CS, \ | ||
| 655 | } | ||
| 656 | |||
| 657 | #define SPI_LIS3 \ | ||
| 658 | { \ | ||
| 659 | .modalias = "lis3lv02d_spi", \ | ||
| 660 | .max_speed_hz = 1000000, \ | ||
| 661 | .bus_num = 0, \ | ||
| 662 | .chip_select = 1, \ | ||
| 663 | .controller_data = (void *) GPIO_ACCEL_CS, \ | ||
| 664 | .platform_data = &lis3_pdata, \ | ||
| 665 | .irq = gpio_to_irq(GPIO_ACCEL_IRQ), \ | ||
| 666 | } | ||
| 667 | |||
| 668 | #define SPI_DAC7512 \ | ||
| 669 | { \ | ||
| 670 | .modalias = "dac7512", \ | ||
| 671 | .max_speed_hz = 1000000, \ | ||
| 672 | .bus_num = 0, \ | ||
| 673 | .chip_select = 2, \ | ||
| 674 | .controller_data = (void *) GPIO_MCLK_DAC_CS, \ | ||
| 675 | } | ||
| 676 | |||
| 677 | static struct spi_board_info connector_spi_devices[] __initdata = { | ||
| 678 | SPI_AK4104, | ||
| 679 | SPI_DAC7512, | ||
| 680 | }; | ||
| 681 | |||
| 682 | static struct spi_board_info speaker_spi_devices[] __initdata = { | ||
| 683 | SPI_DAC7512, | ||
| 684 | }; | ||
| 685 | |||
| 686 | static struct spi_board_info controller_spi_devices[] __initdata = { | ||
| 687 | SPI_LIS3, | ||
| 688 | }; | ||
| 689 | |||
| 690 | /** | ||
| 691 | * MMC for Marvell Libertas 8688 via SDIO | ||
| 692 | */ | ||
| 693 | |||
| 694 | static int raumfeld_mci_init(struct device *dev, irq_handler_t isr, void *data) | ||
| 695 | { | ||
| 696 | gpio_set_value(GPIO_W2W_RESET, 1); | ||
| 697 | gpio_set_value(GPIO_W2W_PDN, 1); | ||
| 698 | |||
| 699 | return 0; | ||
| 700 | } | ||
| 701 | |||
| 702 | static void raumfeld_mci_exit(struct device *dev, void *data) | ||
| 703 | { | ||
| 704 | gpio_set_value(GPIO_W2W_RESET, 0); | ||
| 705 | gpio_set_value(GPIO_W2W_PDN, 0); | ||
| 706 | } | ||
| 707 | |||
| 708 | static struct pxamci_platform_data raumfeld_mci_platform_data = { | ||
| 709 | .init = raumfeld_mci_init, | ||
| 710 | .exit = raumfeld_mci_exit, | ||
| 711 | .detect_delay = 20, | ||
| 712 | .gpio_card_detect = -1, | ||
| 713 | .gpio_card_ro = -1, | ||
| 714 | .gpio_power = -1, | ||
| 715 | }; | ||
| 716 | |||
| 717 | /* | ||
| 718 | * External power / charge logic | ||
| 719 | */ | ||
| 720 | |||
| 721 | static int power_supply_init(struct device *dev) | ||
| 722 | { | ||
| 723 | return 0; | ||
| 724 | } | ||
| 725 | |||
| 726 | static void power_supply_exit(struct device *dev) | ||
| 727 | { | ||
| 728 | } | ||
| 729 | |||
| 730 | static int raumfeld_is_ac_online(void) | ||
| 731 | { | ||
| 732 | return !gpio_get_value(GPIO_CHARGE_DC_OK); | ||
| 733 | } | ||
| 734 | |||
| 735 | static int raumfeld_is_usb_online(void) | ||
| 736 | { | ||
| 737 | return 0; | ||
| 738 | } | ||
| 739 | |||
| 740 | static char *raumfeld_power_supplicants[] = { "ds2760-battery.0" }; | ||
| 741 | |||
| 742 | static struct pda_power_pdata power_supply_info = { | ||
| 743 | .init = power_supply_init, | ||
| 744 | .is_ac_online = raumfeld_is_ac_online, | ||
| 745 | .is_usb_online = raumfeld_is_usb_online, | ||
| 746 | .exit = power_supply_exit, | ||
| 747 | .supplied_to = raumfeld_power_supplicants, | ||
| 748 | .num_supplicants = ARRAY_SIZE(raumfeld_power_supplicants) | ||
| 749 | }; | ||
| 750 | |||
| 751 | static struct resource power_supply_resources[] = { | ||
| 752 | { | ||
| 753 | .name = "ac", | ||
| 754 | .flags = IORESOURCE_IRQ | | ||
| 755 | IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE, | ||
| 756 | .start = GPIO_CHARGE_DC_OK, | ||
| 757 | .end = GPIO_CHARGE_DC_OK, | ||
| 758 | }, | ||
| 759 | }; | ||
| 760 | |||
| 761 | static irqreturn_t charge_done_irq(int irq, void *dev_id) | ||
| 762 | { | ||
| 763 | struct power_supply *psy; | ||
| 764 | |||
| 765 | psy = power_supply_get_by_name("ds2760-battery.0"); | ||
| 766 | |||
| 767 | if (psy) | ||
| 768 | power_supply_set_battery_charged(psy); | ||
| 769 | |||
| 770 | return IRQ_HANDLED; | ||
| 771 | } | ||
| 772 | |||
| 773 | static struct platform_device raumfeld_power_supply = { | ||
| 774 | .name = "pda-power", | ||
| 775 | .id = -1, | ||
| 776 | .dev = { | ||
| 777 | .platform_data = &power_supply_info, | ||
| 778 | }, | ||
| 779 | .resource = power_supply_resources, | ||
| 780 | .num_resources = ARRAY_SIZE(power_supply_resources), | ||
| 781 | }; | ||
| 782 | |||
| 783 | static void __init raumfeld_power_init(void) | ||
| 784 | { | ||
| 785 | int ret; | ||
| 786 | |||
| 787 | /* Set PEN2 high to enable maximum charge current */ | ||
| 788 | ret = gpio_request(GPIO_CHRG_PEN2, "CHRG_PEN2"); | ||
| 789 | if (ret < 0) | ||
| 790 | pr_warning("Unable to request GPIO_CHRG_PEN2\n"); | ||
| 791 | else | ||
| 792 | gpio_direction_output(GPIO_CHRG_PEN2, 1); | ||
| 793 | |||
| 794 | ret = gpio_request(GPIO_CHARGE_DC_OK, "CABLE_DC_OK"); | ||
| 795 | if (ret < 0) | ||
| 796 | pr_warning("Unable to request GPIO_CHARGE_DC_OK\n"); | ||
| 797 | |||
| 798 | ret = gpio_request(GPIO_CHARGE_USB_SUSP, "CHARGE_USB_SUSP"); | ||
| 799 | if (ret < 0) | ||
| 800 | pr_warning("Unable to request GPIO_CHARGE_USB_SUSP\n"); | ||
| 801 | else | ||
| 802 | gpio_direction_output(GPIO_CHARGE_USB_SUSP, 0); | ||
| 803 | |||
| 804 | power_supply_resources[0].start = gpio_to_irq(GPIO_CHARGE_DC_OK); | ||
| 805 | power_supply_resources[0].end = gpio_to_irq(GPIO_CHARGE_DC_OK); | ||
| 806 | |||
| 807 | ret = request_irq(gpio_to_irq(GPIO_CHARGE_DONE), | ||
| 808 | &charge_done_irq, IORESOURCE_IRQ_LOWEDGE, | ||
| 809 | "charge_done", NULL); | ||
| 810 | |||
| 811 | if (ret < 0) | ||
| 812 | printk(KERN_ERR "%s: unable to register irq %d\n", __func__, | ||
| 813 | GPIO_CHARGE_DONE); | ||
| 814 | else | ||
| 815 | platform_device_register(&raumfeld_power_supply); | ||
| 816 | } | ||
| 817 | |||
| 818 | /* Fixed regulator for AUDIO_VA, 0-0048 maps to the cs4270 codec device */ | ||
| 819 | |||
| 820 | static struct regulator_consumer_supply audio_va_consumer_supply = | ||
| 821 | REGULATOR_SUPPLY("va", "0-0048"); | ||
| 822 | |||
| 823 | struct regulator_init_data audio_va_initdata = { | ||
| 824 | .consumer_supplies = &audio_va_consumer_supply, | ||
| 825 | .num_consumer_supplies = 1, | ||
| 826 | .constraints = { | ||
| 827 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
| 828 | }, | ||
| 829 | }; | ||
| 830 | |||
| 831 | static struct fixed_voltage_config audio_va_config = { | ||
| 832 | .supply_name = "audio_va", | ||
| 833 | .microvolts = 5000000, | ||
| 834 | .gpio = GPIO_AUDIO_VA_ENABLE, | ||
| 835 | .enable_high = 1, | ||
| 836 | .enabled_at_boot = 0, | ||
| 837 | .init_data = &audio_va_initdata, | ||
| 838 | }; | ||
| 839 | |||
| 840 | static struct platform_device audio_va_device = { | ||
| 841 | .name = "reg-fixed-voltage", | ||
| 842 | .id = 0, | ||
| 843 | .dev = { | ||
| 844 | .platform_data = &audio_va_config, | ||
| 845 | }, | ||
| 846 | }; | ||
| 847 | |||
| 848 | /* Dummy supplies for Codec's VD/VLC */ | ||
| 849 | |||
| 850 | static struct regulator_consumer_supply audio_dummy_supplies[] = { | ||
| 851 | REGULATOR_SUPPLY("vd", "0-0048"), | ||
| 852 | REGULATOR_SUPPLY("vlc", "0-0048"), | ||
| 853 | }; | ||
| 854 | |||
| 855 | struct regulator_init_data audio_dummy_initdata = { | ||
| 856 | .consumer_supplies = audio_dummy_supplies, | ||
| 857 | .num_consumer_supplies = ARRAY_SIZE(audio_dummy_supplies), | ||
| 858 | .constraints = { | ||
| 859 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
| 860 | }, | ||
| 861 | }; | ||
| 862 | |||
| 863 | static struct fixed_voltage_config audio_dummy_config = { | ||
| 864 | .supply_name = "audio_vd", | ||
| 865 | .microvolts = 3300000, | ||
| 866 | .gpio = -1, | ||
| 867 | .init_data = &audio_dummy_initdata, | ||
| 868 | }; | ||
| 869 | |||
| 870 | static struct platform_device audio_supply_dummy_device = { | ||
| 871 | .name = "reg-fixed-voltage", | ||
| 872 | .id = 1, | ||
| 873 | .dev = { | ||
| 874 | .platform_data = &audio_dummy_config, | ||
| 875 | }, | ||
| 876 | }; | ||
| 877 | |||
| 878 | static struct platform_device *audio_regulator_devices[] = { | ||
| 879 | &audio_va_device, | ||
| 880 | &audio_supply_dummy_device, | ||
| 881 | }; | ||
| 882 | |||
| 883 | /** | ||
| 884 | * Regulator support via MAX8660 | ||
| 885 | */ | ||
| 886 | |||
| 887 | static struct regulator_consumer_supply vcc_mmc_supply = | ||
| 888 | REGULATOR_SUPPLY("vmmc", "pxa2xx-mci.0"); | ||
| 889 | |||
| 890 | static struct regulator_init_data vcc_mmc_init_data = { | ||
| 891 | .constraints = { | ||
| 892 | .min_uV = 3300000, | ||
| 893 | .max_uV = 3300000, | ||
| 894 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 895 | .valid_ops_mask = REGULATOR_CHANGE_STATUS | | ||
| 896 | REGULATOR_CHANGE_VOLTAGE | | ||
| 897 | REGULATOR_CHANGE_MODE, | ||
| 898 | }, | ||
| 899 | .consumer_supplies = &vcc_mmc_supply, | ||
| 900 | .num_consumer_supplies = 1, | ||
| 901 | }; | ||
| 902 | |||
| 903 | struct max8660_subdev_data max8660_v6_subdev_data = { | ||
| 904 | .id = MAX8660_V6, | ||
| 905 | .name = "vmmc", | ||
| 906 | .platform_data = &vcc_mmc_init_data, | ||
| 907 | }; | ||
| 908 | |||
| 909 | static struct max8660_platform_data max8660_pdata = { | ||
| 910 | .subdevs = &max8660_v6_subdev_data, | ||
| 911 | .num_subdevs = 1, | ||
| 912 | }; | ||
| 913 | |||
| 914 | /** | ||
| 915 | * I2C devices | ||
| 916 | */ | ||
| 917 | |||
| 918 | static struct i2c_board_info raumfeld_pwri2c_board_info = { | ||
| 919 | .type = "max8660", | ||
| 920 | .addr = 0x34, | ||
| 921 | .platform_data = &max8660_pdata, | ||
| 922 | }; | ||
| 923 | |||
| 924 | static struct i2c_board_info raumfeld_connector_i2c_board_info __initdata = { | ||
| 925 | .type = "cs4270", | ||
| 926 | .addr = 0x48, | ||
| 927 | }; | ||
| 928 | |||
| 929 | static struct eeti_ts_platform_data eeti_ts_pdata = { | ||
| 930 | .irq_active_high = 1, | ||
| 931 | }; | ||
| 932 | |||
| 933 | static struct i2c_board_info raumfeld_controller_i2c_board_info __initdata = { | ||
| 934 | .type = "eeti_ts", | ||
| 935 | .addr = 0x0a, | ||
| 936 | .irq = gpio_to_irq(GPIO_TOUCH_IRQ), | ||
| 937 | .platform_data = &eeti_ts_pdata, | ||
| 938 | }; | ||
| 939 | |||
| 940 | static struct platform_device *raumfeld_common_devices[] = { | ||
| 941 | &raumfeld_gpio_keys_device, | ||
| 942 | &raumfeld_led_device, | ||
| 943 | &raumfeld_spi_device, | ||
| 944 | }; | ||
| 945 | |||
| 946 | static void __init raumfeld_audio_init(void) | ||
| 947 | { | ||
| 948 | int ret; | ||
| 949 | |||
| 950 | ret = gpio_request(GPIO_CODEC_RESET, "cs4270 reset"); | ||
| 951 | if (ret < 0) | ||
| 952 | pr_warning("unable to request GPIO_CODEC_RESET\n"); | ||
| 953 | else | ||
| 954 | gpio_direction_output(GPIO_CODEC_RESET, 1); | ||
| 955 | |||
| 956 | ret = gpio_request(GPIO_SPDIF_RESET, "ak4104 s/pdif reset"); | ||
| 957 | if (ret < 0) | ||
| 958 | pr_warning("unable to request GPIO_SPDIF_RESET\n"); | ||
| 959 | else | ||
| 960 | gpio_direction_output(GPIO_SPDIF_RESET, 1); | ||
| 961 | |||
| 962 | ret = gpio_request(GPIO_MCLK_RESET, "MCLK reset"); | ||
| 963 | if (ret < 0) | ||
| 964 | pr_warning("unable to request GPIO_MCLK_RESET\n"); | ||
| 965 | else | ||
| 966 | gpio_direction_output(GPIO_MCLK_RESET, 1); | ||
| 967 | |||
| 968 | platform_add_devices(ARRAY_AND_SIZE(audio_regulator_devices)); | ||
| 969 | } | ||
| 970 | |||
| 971 | static void __init raumfeld_common_init(void) | ||
| 972 | { | ||
| 973 | int ret; | ||
| 974 | |||
| 975 | /* The on/off button polarity has changed after revision 1 */ | ||
| 976 | if ((system_rev & 0xff) > 1) { | ||
| 977 | int i; | ||
| 978 | |||
| 979 | for (i = 0; i < ARRAY_SIZE(gpio_keys_button); i++) | ||
| 980 | if (!strcmp(gpio_keys_button[i].desc, "on/off button")) | ||
| 981 | gpio_keys_button[i].active_low = 1; | ||
| 982 | } | ||
| 983 | |||
| 984 | enable_irq_wake(IRQ_WAKEUP0); | ||
| 985 | |||
| 986 | pxa3xx_set_nand_info(&raumfeld_nand_info); | ||
| 987 | pxa3xx_set_i2c_power_info(NULL); | ||
| 988 | pxa_set_ohci_info(&raumfeld_ohci_info); | ||
| 989 | pxa_set_mci_info(&raumfeld_mci_platform_data); | ||
| 990 | pxa_set_i2c_info(NULL); | ||
| 991 | pxa_set_ffuart_info(NULL); | ||
| 992 | |||
| 993 | ret = gpio_request(GPIO_W2W_RESET, "Wi2Wi reset"); | ||
| 994 | if (ret < 0) | ||
| 995 | pr_warning("Unable to request GPIO_W2W_RESET\n"); | ||
| 996 | else | ||
| 997 | gpio_direction_output(GPIO_W2W_RESET, 0); | ||
| 998 | |||
| 999 | ret = gpio_request(GPIO_W2W_PDN, "Wi2Wi powerup"); | ||
| 1000 | if (ret < 0) | ||
| 1001 | pr_warning("Unable to request GPIO_W2W_PDN\n"); | ||
| 1002 | else | ||
| 1003 | gpio_direction_output(GPIO_W2W_PDN, 0); | ||
| 1004 | |||
| 1005 | /* this can be used to switch off the device */ | ||
| 1006 | ret = gpio_request(GPIO_SHUTDOWN_SUPPLY, | ||
| 1007 | "supply shutdown"); | ||
| 1008 | if (ret < 0) | ||
| 1009 | pr_warning("Unable to request GPIO_SHUTDOWN_SUPPLY\n"); | ||
| 1010 | else | ||
| 1011 | gpio_direction_output(GPIO_SHUTDOWN_SUPPLY, 0); | ||
| 1012 | |||
| 1013 | platform_add_devices(ARRAY_AND_SIZE(raumfeld_common_devices)); | ||
| 1014 | i2c_register_board_info(1, &raumfeld_pwri2c_board_info, 1); | ||
| 1015 | } | ||
| 1016 | |||
| 1017 | static void __init raumfeld_controller_init(void) | ||
| 1018 | { | ||
| 1019 | int ret; | ||
| 1020 | |||
| 1021 | pxa3xx_mfp_config(ARRAY_AND_SIZE(raumfeld_controller_pin_config)); | ||
| 1022 | platform_device_register(&rotary_encoder_device); | ||
| 1023 | spi_register_board_info(ARRAY_AND_SIZE(controller_spi_devices)); | ||
| 1024 | i2c_register_board_info(0, &raumfeld_controller_i2c_board_info, 1); | ||
| 1025 | |||
| 1026 | ret = gpio_request(GPIO_SHUTDOWN_BATT, "battery shutdown"); | ||
| 1027 | if (ret < 0) | ||
| 1028 | pr_warning("Unable to request GPIO_SHUTDOWN_BATT\n"); | ||
| 1029 | else | ||
| 1030 | gpio_direction_output(GPIO_SHUTDOWN_BATT, 0); | ||
| 1031 | |||
| 1032 | raumfeld_common_init(); | ||
| 1033 | raumfeld_power_init(); | ||
| 1034 | raumfeld_lcd_init(); | ||
| 1035 | raumfeld_w1_init(); | ||
| 1036 | } | ||
| 1037 | |||
| 1038 | static void __init raumfeld_connector_init(void) | ||
| 1039 | { | ||
| 1040 | pxa3xx_mfp_config(ARRAY_AND_SIZE(raumfeld_connector_pin_config)); | ||
| 1041 | spi_register_board_info(ARRAY_AND_SIZE(connector_spi_devices)); | ||
| 1042 | i2c_register_board_info(0, &raumfeld_connector_i2c_board_info, 1); | ||
| 1043 | |||
| 1044 | platform_device_register(&smc91x_device); | ||
| 1045 | |||
| 1046 | raumfeld_audio_init(); | ||
| 1047 | raumfeld_common_init(); | ||
| 1048 | } | ||
| 1049 | |||
| 1050 | static void __init raumfeld_speaker_init(void) | ||
| 1051 | { | ||
| 1052 | pxa3xx_mfp_config(ARRAY_AND_SIZE(raumfeld_speaker_pin_config)); | ||
| 1053 | spi_register_board_info(ARRAY_AND_SIZE(speaker_spi_devices)); | ||
| 1054 | i2c_register_board_info(0, &raumfeld_connector_i2c_board_info, 1); | ||
| 1055 | |||
| 1056 | platform_device_register(&smc91x_device); | ||
| 1057 | platform_device_register(&rotary_encoder_device); | ||
| 1058 | |||
| 1059 | raumfeld_audio_init(); | ||
| 1060 | raumfeld_common_init(); | ||
| 1061 | } | ||
| 1062 | |||
| 1063 | /* physical memory regions */ | ||
| 1064 | #define RAUMFELD_SDRAM_BASE 0xa0000000 /* SDRAM region */ | ||
| 1065 | |||
| 1066 | #ifdef CONFIG_MACH_RAUMFELD_RC | ||
| 1067 | MACHINE_START(RAUMFELD_RC, "Raumfeld Controller") | ||
| 1068 | .phys_io = 0x40000000, | ||
| 1069 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 1070 | .boot_params = RAUMFELD_SDRAM_BASE + 0x100, | ||
| 1071 | .init_machine = raumfeld_controller_init, | ||
| 1072 | .map_io = pxa_map_io, | ||
| 1073 | .init_irq = pxa3xx_init_irq, | ||
| 1074 | .timer = &pxa_timer, | ||
| 1075 | MACHINE_END | ||
| 1076 | #endif | ||
| 1077 | |||
| 1078 | #ifdef CONFIG_MACH_RAUMFELD_CONNECTOR | ||
| 1079 | MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector") | ||
| 1080 | .phys_io = 0x40000000, | ||
| 1081 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 1082 | .boot_params = RAUMFELD_SDRAM_BASE + 0x100, | ||
| 1083 | .init_machine = raumfeld_connector_init, | ||
| 1084 | .map_io = pxa_map_io, | ||
| 1085 | .init_irq = pxa3xx_init_irq, | ||
| 1086 | .timer = &pxa_timer, | ||
| 1087 | MACHINE_END | ||
| 1088 | #endif | ||
| 1089 | |||
| 1090 | #ifdef CONFIG_MACH_RAUMFELD_SPEAKER | ||
| 1091 | MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker") | ||
| 1092 | .phys_io = 0x40000000, | ||
| 1093 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 1094 | .boot_params = RAUMFELD_SDRAM_BASE + 0x100, | ||
| 1095 | .init_machine = raumfeld_speaker_init, | ||
| 1096 | .map_io = pxa_map_io, | ||
| 1097 | .init_irq = pxa3xx_init_irq, | ||
| 1098 | .timer = &pxa_timer, | ||
| 1099 | MACHINE_END | ||
| 1100 | #endif | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/arch/arm/mach-s3c2410/include/mach/gpio-track.h index f8b879a7973c..acb259103808 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-core.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-track.h | |||
| @@ -15,7 +15,6 @@ | |||
| 15 | #ifndef __ASM_ARCH_GPIO_CORE_H | 15 | #ifndef __ASM_ARCH_GPIO_CORE_H |
| 16 | #define __ASM_ARCH_GPIO_CORE_H __FILE__ | 16 | #define __ASM_ARCH_GPIO_CORE_H __FILE__ |
| 17 | 17 | ||
| 18 | #include <plat/gpio-core.h> | ||
| 19 | #include <mach/regs-gpio.h> | 18 | #include <mach/regs-gpio.h> |
| 20 | 19 | ||
| 21 | extern struct s3c_gpio_chip s3c24xx_gpios[]; | 20 | extern struct s3c_gpio_chip s3c24xx_gpios[]; |
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c index 06a84adfb13f..7047317ed7f4 100644 --- a/arch/arm/mach-s3c2410/mach-amlm5900.c +++ b/arch/arm/mach-s3c2410/mach-amlm5900.c | |||
| @@ -153,7 +153,7 @@ static struct platform_device *amlm5900_devices[] __initdata = { | |||
| 153 | &s3c_device_adc, | 153 | &s3c_device_adc, |
| 154 | &s3c_device_wdt, | 154 | &s3c_device_wdt, |
| 155 | &s3c_device_i2c0, | 155 | &s3c_device_i2c0, |
| 156 | &s3c_device_usb, | 156 | &s3c_device_ohci, |
| 157 | &s3c_device_rtc, | 157 | &s3c_device_rtc, |
| 158 | &s3c_device_usbgadget, | 158 | &s3c_device_usbgadget, |
| 159 | &s3c_device_sdi, | 159 | &s3c_device_sdi, |
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index 97162fdd0590..02b1b6220cba 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c | |||
| @@ -584,7 +584,7 @@ static struct s3c_hwmon_pdata bast_hwmon_info = { | |||
| 584 | // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0 | 584 | // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0 |
| 585 | 585 | ||
| 586 | static struct platform_device *bast_devices[] __initdata = { | 586 | static struct platform_device *bast_devices[] __initdata = { |
| 587 | &s3c_device_usb, | 587 | &s3c_device_ohci, |
| 588 | &s3c_device_lcd, | 588 | &s3c_device_lcd, |
| 589 | &s3c_device_wdt, | 589 | &s3c_device_wdt, |
| 590 | &s3c_device_i2c0, | 590 | &s3c_device_i2c0, |
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 1e34abe1a19e..fbedd0760941 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c | |||
| @@ -196,7 +196,7 @@ static struct platform_device h1940_device_bluetooth = { | |||
| 196 | .id = -1, | 196 | .id = -1, |
| 197 | }; | 197 | }; |
| 198 | 198 | ||
| 199 | static struct s3c24xx_mci_pdata h1940_mmc_cfg = { | 199 | static struct s3c24xx_mci_pdata h1940_mmc_cfg __initdata = { |
| 200 | .gpio_detect = S3C2410_GPF(5), | 200 | .gpio_detect = S3C2410_GPF(5), |
| 201 | .gpio_wprotect = S3C2410_GPH(8), | 201 | .gpio_wprotect = S3C2410_GPH(8), |
| 202 | .set_power = NULL, | 202 | .set_power = NULL, |
| @@ -272,7 +272,7 @@ static struct platform_device h1940_lcd_powerdev = { | |||
| 272 | 272 | ||
| 273 | static struct platform_device *h1940_devices[] __initdata = { | 273 | static struct platform_device *h1940_devices[] __initdata = { |
| 274 | &s3c_device_ts, | 274 | &s3c_device_ts, |
| 275 | &s3c_device_usb, | 275 | &s3c_device_ohci, |
| 276 | &s3c_device_lcd, | 276 | &s3c_device_lcd, |
| 277 | &s3c_device_wdt, | 277 | &s3c_device_wdt, |
| 278 | &s3c_device_i2c0, | 278 | &s3c_device_i2c0, |
| @@ -311,12 +311,11 @@ static void __init h1940_init(void) | |||
| 311 | u32 tmp; | 311 | u32 tmp; |
| 312 | 312 | ||
| 313 | s3c24xx_fb_set_platdata(&h1940_fb_info); | 313 | s3c24xx_fb_set_platdata(&h1940_fb_info); |
| 314 | s3c24xx_mci_set_platdata(&h1940_mmc_cfg); | ||
| 314 | s3c24xx_udc_set_platdata(&h1940_udc_cfg); | 315 | s3c24xx_udc_set_platdata(&h1940_udc_cfg); |
| 315 | s3c24xx_ts_set_platdata(&h1940_ts_cfg); | 316 | s3c24xx_ts_set_platdata(&h1940_ts_cfg); |
| 316 | s3c_i2c0_set_platdata(NULL); | 317 | s3c_i2c0_set_platdata(NULL); |
| 317 | 318 | ||
| 318 | s3c_device_sdi.dev.platform_data = &h1940_mmc_cfg; | ||
| 319 | |||
| 320 | /* Turn off suspend on both USB ports, and switch the | 319 | /* Turn off suspend on both USB ports, and switch the |
| 321 | * selectable USB port to USB device mode. */ | 320 | * selectable USB port to USB device mode. */ |
| 322 | 321 | ||
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c index 0405712c2263..684710f88142 100644 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ b/arch/arm/mach-s3c2410/mach-n30.c | |||
| @@ -322,7 +322,7 @@ static struct platform_device *n30_devices[] __initdata = { | |||
| 322 | &s3c_device_wdt, | 322 | &s3c_device_wdt, |
| 323 | &s3c_device_i2c0, | 323 | &s3c_device_i2c0, |
| 324 | &s3c_device_iis, | 324 | &s3c_device_iis, |
| 325 | &s3c_device_usb, | 325 | &s3c_device_ohci, |
| 326 | &s3c_device_usbgadget, | 326 | &s3c_device_usbgadget, |
| 327 | &n30_button_device, | 327 | &n30_button_device, |
| 328 | &n30_blue_led, | 328 | &n30_blue_led, |
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c index f6c7261a4a12..d8c7f2efc1a7 100644 --- a/arch/arm/mach-s3c2410/mach-otom.c +++ b/arch/arm/mach-s3c2410/mach-otom.c | |||
| @@ -92,7 +92,7 @@ static struct platform_device otom_device_nor = { | |||
| 92 | /* Standard OTOM devices */ | 92 | /* Standard OTOM devices */ |
| 93 | 93 | ||
| 94 | static struct platform_device *otom11_devices[] __initdata = { | 94 | static struct platform_device *otom11_devices[] __initdata = { |
| 95 | &s3c_device_usb, | 95 | &s3c_device_ohci, |
| 96 | &s3c_device_lcd, | 96 | &s3c_device_lcd, |
| 97 | &s3c_device_wdt, | 97 | &s3c_device_wdt, |
| 98 | &s3c_device_i2c0, | 98 | &s3c_device_i2c0, |
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index ab092bcda393..92a4ec375d82 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c | |||
| @@ -246,7 +246,7 @@ static struct platform_device qt2410_spi = { | |||
| 246 | /* Board devices */ | 246 | /* Board devices */ |
| 247 | 247 | ||
| 248 | static struct platform_device *qt2410_devices[] __initdata = { | 248 | static struct platform_device *qt2410_devices[] __initdata = { |
| 249 | &s3c_device_usb, | 249 | &s3c_device_ohci, |
| 250 | &s3c_device_lcd, | 250 | &s3c_device_lcd, |
| 251 | &s3c_device_wdt, | 251 | &s3c_device_wdt, |
| 252 | &s3c_device_i2c0, | 252 | &s3c_device_i2c0, |
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c index c49126ccb1d5..452223042201 100644 --- a/arch/arm/mach-s3c2410/mach-smdk2410.c +++ b/arch/arm/mach-s3c2410/mach-smdk2410.c | |||
| @@ -87,7 +87,7 @@ static struct s3c2410_uartcfg smdk2410_uartcfgs[] __initdata = { | |||
| 87 | }; | 87 | }; |
| 88 | 88 | ||
| 89 | static struct platform_device *smdk2410_devices[] __initdata = { | 89 | static struct platform_device *smdk2410_devices[] __initdata = { |
| 90 | &s3c_device_usb, | 90 | &s3c_device_ohci, |
| 91 | &s3c_device_lcd, | 91 | &s3c_device_lcd, |
| 92 | &s3c_device_wdt, | 92 | &s3c_device_wdt, |
| 93 | &s3c_device_i2c0, | 93 | &s3c_device_i2c0, |
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c index 8fdb0430bd48..929164a8e9b1 100644 --- a/arch/arm/mach-s3c2410/mach-tct_hammer.c +++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c | |||
| @@ -129,7 +129,7 @@ static struct platform_device *tct_hammer_devices[] __initdata = { | |||
| 129 | &s3c_device_adc, | 129 | &s3c_device_adc, |
| 130 | &s3c_device_wdt, | 130 | &s3c_device_wdt, |
| 131 | &s3c_device_i2c0, | 131 | &s3c_device_i2c0, |
| 132 | &s3c_device_usb, | 132 | &s3c_device_ohci, |
| 133 | &s3c_device_rtc, | 133 | &s3c_device_rtc, |
| 134 | &s3c_device_usbgadget, | 134 | &s3c_device_usbgadget, |
| 135 | &s3c_device_sdi, | 135 | &s3c_device_sdi, |
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index 0d61fb577170..9051f0d31123 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c | |||
| @@ -334,7 +334,7 @@ static struct i2c_board_info vr1000_i2c_devs[] __initdata = { | |||
| 334 | /* devices for this board */ | 334 | /* devices for this board */ |
| 335 | 335 | ||
| 336 | static struct platform_device *vr1000_devices[] __initdata = { | 336 | static struct platform_device *vr1000_devices[] __initdata = { |
| 337 | &s3c_device_usb, | 337 | &s3c_device_ohci, |
| 338 | &s3c_device_lcd, | 338 | &s3c_device_lcd, |
| 339 | &s3c_device_wdt, | 339 | &s3c_device_wdt, |
| 340 | &s3c_device_i2c0, | 340 | &s3c_device_i2c0, |
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c index 6b9d0d83a6f9..29bd3d987bec 100644 --- a/arch/arm/mach-s3c2410/usb-simtec.c +++ b/arch/arm/mach-s3c2410/usb-simtec.c | |||
| @@ -91,7 +91,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on) | |||
| 91 | } | 91 | } |
| 92 | } | 92 | } |
| 93 | 93 | ||
| 94 | static struct s3c2410_hcd_info usb_simtec_info = { | 94 | static struct s3c2410_hcd_info usb_simtec_info __initdata = { |
| 95 | .port[0] = { | 95 | .port[0] = { |
| 96 | .flags = S3C_HCDFLG_USED | 96 | .flags = S3C_HCDFLG_USED |
| 97 | }, | 97 | }, |
| @@ -127,6 +127,6 @@ int usb_simtec_init(void) | |||
| 127 | gpio_direction_output(S3C2410_GPB(4), 1); | 127 | gpio_direction_output(S3C2410_GPB(4), 1); |
| 128 | gpio_direction_input(S3C2410_GPG(10)); | 128 | gpio_direction_input(S3C2410_GPG(10)); |
| 129 | 129 | ||
| 130 | s3c_device_usb.dev.platform_data = &usb_simtec_info; | 130 | s3c_ohci_set_platdata(&usb_simtec_info); |
| 131 | return 0; | 131 | return 0; |
| 132 | } | 132 | } |
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c index a037df5e1c2d..0c0505b025cb 100644 --- a/arch/arm/mach-s3c2412/clock.c +++ b/arch/arm/mach-s3c2412/clock.c | |||
| @@ -124,7 +124,9 @@ static struct clk clk_usysclk = { | |||
| 124 | .name = "usysclk", | 124 | .name = "usysclk", |
| 125 | .id = -1, | 125 | .id = -1, |
| 126 | .parent = &clk_xtal, | 126 | .parent = &clk_xtal, |
| 127 | .set_parent = s3c2412_setparent_usysclk, | 127 | .ops = &(struct clk_ops) { |
| 128 | .set_parent = s3c2412_setparent_usysclk, | ||
| 129 | }, | ||
| 128 | }; | 130 | }; |
| 129 | 131 | ||
| 130 | static struct clk clk_mrefclk = { | 132 | static struct clk clk_mrefclk = { |
| @@ -199,10 +201,12 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate) | |||
| 199 | static struct clk clk_usbsrc = { | 201 | static struct clk clk_usbsrc = { |
| 200 | .name = "usbsrc", | 202 | .name = "usbsrc", |
| 201 | .id = -1, | 203 | .id = -1, |
| 202 | .get_rate = s3c2412_getrate_usbsrc, | 204 | .ops = &(struct clk_ops) { |
| 203 | .set_rate = s3c2412_setrate_usbsrc, | 205 | .get_rate = s3c2412_getrate_usbsrc, |
| 204 | .round_rate = s3c2412_roundrate_usbsrc, | 206 | .set_rate = s3c2412_setrate_usbsrc, |
| 205 | .set_parent = s3c2412_setparent_usbsrc, | 207 | .round_rate = s3c2412_roundrate_usbsrc, |
| 208 | .set_parent = s3c2412_setparent_usbsrc, | ||
| 209 | }, | ||
| 206 | }; | 210 | }; |
| 207 | 211 | ||
| 208 | static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) | 212 | static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) |
| @@ -225,7 +229,9 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) | |||
| 225 | static struct clk clk_msysclk = { | 229 | static struct clk clk_msysclk = { |
| 226 | .name = "msysclk", | 230 | .name = "msysclk", |
| 227 | .id = -1, | 231 | .id = -1, |
| 228 | .set_parent = s3c2412_setparent_msysclk, | 232 | .ops = &(struct clk_ops) { |
| 233 | .set_parent = s3c2412_setparent_msysclk, | ||
| 234 | }, | ||
| 229 | }; | 235 | }; |
| 230 | 236 | ||
| 231 | static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent) | 237 | static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent) |
| @@ -264,7 +270,9 @@ static struct clk clk_armclk = { | |||
| 264 | .name = "armclk", | 270 | .name = "armclk", |
| 265 | .id = -1, | 271 | .id = -1, |
| 266 | .parent = &clk_msysclk, | 272 | .parent = &clk_msysclk, |
| 267 | .set_parent = s3c2412_setparent_armclk, | 273 | .ops = &(struct clk_ops) { |
| 274 | .set_parent = s3c2412_setparent_armclk, | ||
| 275 | }, | ||
| 268 | }; | 276 | }; |
| 269 | 277 | ||
| 270 | /* these next clocks have an divider immediately after them, | 278 | /* these next clocks have an divider immediately after them, |
| @@ -337,10 +345,12 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate) | |||
| 337 | static struct clk clk_uart = { | 345 | static struct clk clk_uart = { |
| 338 | .name = "uartclk", | 346 | .name = "uartclk", |
| 339 | .id = -1, | 347 | .id = -1, |
| 340 | .get_rate = s3c2412_getrate_uart, | 348 | .ops = &(struct clk_ops) { |
| 341 | .set_rate = s3c2412_setrate_uart, | 349 | .get_rate = s3c2412_getrate_uart, |
| 342 | .set_parent = s3c2412_setparent_uart, | 350 | .set_rate = s3c2412_setrate_uart, |
| 343 | .round_rate = s3c2412_roundrate_clksrc, | 351 | .set_parent = s3c2412_setparent_uart, |
| 352 | .round_rate = s3c2412_roundrate_clksrc, | ||
| 353 | }, | ||
| 344 | }; | 354 | }; |
| 345 | 355 | ||
| 346 | static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent) | 356 | static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent) |
| @@ -388,10 +398,12 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate) | |||
| 388 | static struct clk clk_i2s = { | 398 | static struct clk clk_i2s = { |
| 389 | .name = "i2sclk", | 399 | .name = "i2sclk", |
| 390 | .id = -1, | 400 | .id = -1, |
| 391 | .get_rate = s3c2412_getrate_i2s, | 401 | .ops = &(struct clk_ops) { |
| 392 | .set_rate = s3c2412_setrate_i2s, | 402 | .get_rate = s3c2412_getrate_i2s, |
| 393 | .set_parent = s3c2412_setparent_i2s, | 403 | .set_rate = s3c2412_setrate_i2s, |
| 394 | .round_rate = s3c2412_roundrate_clksrc, | 404 | .set_parent = s3c2412_setparent_i2s, |
| 405 | .round_rate = s3c2412_roundrate_clksrc, | ||
| 406 | }, | ||
| 395 | }; | 407 | }; |
| 396 | 408 | ||
| 397 | static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent) | 409 | static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent) |
| @@ -438,10 +450,12 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate) | |||
| 438 | static struct clk clk_cam = { | 450 | static struct clk clk_cam = { |
| 439 | .name = "camif-upll", /* same as 2440 name */ | 451 | .name = "camif-upll", /* same as 2440 name */ |
| 440 | .id = -1, | 452 | .id = -1, |
| 441 | .get_rate = s3c2412_getrate_cam, | 453 | .ops = &(struct clk_ops) { |
| 442 | .set_rate = s3c2412_setrate_cam, | 454 | .get_rate = s3c2412_getrate_cam, |
| 443 | .set_parent = s3c2412_setparent_cam, | 455 | .set_rate = s3c2412_setrate_cam, |
| 444 | .round_rate = s3c2412_roundrate_clksrc, | 456 | .set_parent = s3c2412_setparent_cam, |
| 457 | .round_rate = s3c2412_roundrate_clksrc, | ||
| 458 | }, | ||
| 445 | }; | 459 | }; |
| 446 | 460 | ||
| 447 | /* standard clock definitions */ | 461 | /* standard clock definitions */ |
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c index c9fa3fca486c..14f4798291aa 100644 --- a/arch/arm/mach-s3c2412/mach-jive.c +++ b/arch/arm/mach-s3c2412/mach-jive.c | |||
| @@ -468,7 +468,7 @@ static struct i2c_board_info jive_i2c_devs[] __initdata = { | |||
| 468 | /* The platform devices being used. */ | 468 | /* The platform devices being used. */ |
| 469 | 469 | ||
| 470 | static struct platform_device *jive_devices[] __initdata = { | 470 | static struct platform_device *jive_devices[] __initdata = { |
| 471 | &s3c_device_usb, | 471 | &s3c_device_ohci, |
| 472 | &s3c_device_rtc, | 472 | &s3c_device_rtc, |
| 473 | &s3c_device_wdt, | 473 | &s3c_device_wdt, |
| 474 | &s3c_device_i2c0, | 474 | &s3c_device_i2c0, |
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c index 9a5e43419722..0392065af1af 100644 --- a/arch/arm/mach-s3c2412/mach-smdk2413.c +++ b/arch/arm/mach-s3c2412/mach-smdk2413.c | |||
| @@ -104,8 +104,7 @@ static struct s3c2410_udc_mach_info smdk2413_udc_cfg __initdata = { | |||
| 104 | 104 | ||
| 105 | 105 | ||
| 106 | static struct platform_device *smdk2413_devices[] __initdata = { | 106 | static struct platform_device *smdk2413_devices[] __initdata = { |
| 107 | &s3c_device_usb, | 107 | &s3c_device_ohci, |
| 108 | //&s3c_device_lcd, | ||
| 109 | &s3c_device_wdt, | 108 | &s3c_device_wdt, |
| 110 | &s3c_device_i2c0, | 109 | &s3c_device_i2c0, |
| 111 | &s3c_device_iis, | 110 | &s3c_device_iis, |
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c index a6ba591b26bb..3ca9265b6997 100644 --- a/arch/arm/mach-s3c2412/mach-vstms.c +++ b/arch/arm/mach-s3c2412/mach-vstms.c | |||
| @@ -121,7 +121,7 @@ static struct s3c2410_platform_nand __initdata vstms_nand_info = { | |||
| 121 | }; | 121 | }; |
| 122 | 122 | ||
| 123 | static struct platform_device *vstms_devices[] __initdata = { | 123 | static struct platform_device *vstms_devices[] __initdata = { |
| 124 | &s3c_device_usb, | 124 | &s3c_device_ohci, |
| 125 | &s3c_device_wdt, | 125 | &s3c_device_wdt, |
| 126 | &s3c_device_i2c0, | 126 | &s3c_device_i2c0, |
| 127 | &s3c_device_iis, | 127 | &s3c_device_iis, |
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c index d1c29b2537cd..3dc2426e2345 100644 --- a/arch/arm/mach-s3c2440/clock.c +++ b/arch/arm/mach-s3c2440/clock.c | |||
| @@ -98,8 +98,10 @@ static struct clk s3c2440_clk_cam = { | |||
| 98 | static struct clk s3c2440_clk_cam_upll = { | 98 | static struct clk s3c2440_clk_cam_upll = { |
| 99 | .name = "camif-upll", | 99 | .name = "camif-upll", |
| 100 | .id = -1, | 100 | .id = -1, |
| 101 | .set_rate = s3c2440_camif_upll_setrate, | 101 | .ops = &(struct clk_ops) { |
| 102 | .round_rate = s3c2440_camif_upll_round, | 102 | .set_rate = s3c2440_camif_upll_setrate, |
| 103 | .round_rate = s3c2440_camif_upll_round, | ||
| 104 | }, | ||
| 103 | }; | 105 | }; |
| 104 | 106 | ||
| 105 | static struct clk s3c2440_clk_ac97 = { | 107 | static struct clk s3c2440_clk_ac97 = { |
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c index 62a4c3eba97f..b73f78a9da5c 100644 --- a/arch/arm/mach-s3c2440/mach-anubis.c +++ b/arch/arm/mach-s3c2440/mach-anubis.c | |||
| @@ -409,7 +409,7 @@ static struct platform_device anubis_device_sm501 = { | |||
| 409 | /* Standard Anubis devices */ | 409 | /* Standard Anubis devices */ |
| 410 | 410 | ||
| 411 | static struct platform_device *anubis_devices[] __initdata = { | 411 | static struct platform_device *anubis_devices[] __initdata = { |
| 412 | &s3c_device_usb, | 412 | &s3c_device_ohci, |
| 413 | &s3c_device_wdt, | 413 | &s3c_device_wdt, |
| 414 | &s3c_device_adc, | 414 | &s3c_device_adc, |
| 415 | &s3c_device_i2c0, | 415 | &s3c_device_i2c0, |
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c index aa69290e04c6..84725791e6bf 100644 --- a/arch/arm/mach-s3c2440/mach-at2440evb.c +++ b/arch/arm/mach-s3c2440/mach-at2440evb.c | |||
| @@ -165,7 +165,7 @@ static struct platform_device at2440evb_device_eth = { | |||
| 165 | }, | 165 | }, |
| 166 | }; | 166 | }; |
| 167 | 167 | ||
| 168 | static struct s3c24xx_mci_pdata at2440evb_mci_pdata = { | 168 | static struct s3c24xx_mci_pdata at2440evb_mci_pdata __initdata = { |
| 169 | .gpio_detect = S3C2410_GPG(10), | 169 | .gpio_detect = S3C2410_GPG(10), |
| 170 | }; | 170 | }; |
| 171 | 171 | ||
| @@ -203,7 +203,7 @@ static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = { | |||
| 203 | }; | 203 | }; |
| 204 | 204 | ||
| 205 | static struct platform_device *at2440evb_devices[] __initdata = { | 205 | static struct platform_device *at2440evb_devices[] __initdata = { |
| 206 | &s3c_device_usb, | 206 | &s3c_device_ohci, |
| 207 | &s3c_device_wdt, | 207 | &s3c_device_wdt, |
| 208 | &s3c_device_adc, | 208 | &s3c_device_adc, |
| 209 | &s3c_device_i2c0, | 209 | &s3c_device_i2c0, |
| @@ -216,8 +216,6 @@ static struct platform_device *at2440evb_devices[] __initdata = { | |||
| 216 | 216 | ||
| 217 | static void __init at2440evb_map_io(void) | 217 | static void __init at2440evb_map_io(void) |
| 218 | { | 218 | { |
| 219 | s3c_device_sdi.dev.platform_data = &at2440evb_mci_pdata; | ||
| 220 | |||
| 221 | s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc)); | 219 | s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc)); |
| 222 | s3c24xx_init_clocks(16934400); | 220 | s3c24xx_init_clocks(16934400); |
| 223 | s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs)); | 221 | s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs)); |
| @@ -226,6 +224,7 @@ static void __init at2440evb_map_io(void) | |||
| 226 | static void __init at2440evb_init(void) | 224 | static void __init at2440evb_init(void) |
| 227 | { | 225 | { |
| 228 | s3c24xx_fb_set_platdata(&at2440evb_fb_info); | 226 | s3c24xx_fb_set_platdata(&at2440evb_fb_info); |
| 227 | s3c24xx_mci_set_platdata(&at2440evb_mci_pdata); | ||
| 229 | s3c_nand_set_platdata(&at2440evb_nand_info); | 228 | s3c_nand_set_platdata(&at2440evb_nand_info); |
| 230 | s3c_i2c0_set_platdata(NULL); | 229 | s3c_i2c0_set_platdata(NULL); |
| 231 | 230 | ||
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c index 2068e9096a43..571b17683d96 100644 --- a/arch/arm/mach-s3c2440/mach-mini2440.c +++ b/arch/arm/mach-s3c2440/mach-mini2440.c | |||
| @@ -506,9 +506,8 @@ static struct i2c_board_info mini2440_i2c_devs[] __initdata = { | |||
| 506 | }; | 506 | }; |
| 507 | 507 | ||
| 508 | static struct platform_device *mini2440_devices[] __initdata = { | 508 | static struct platform_device *mini2440_devices[] __initdata = { |
| 509 | &s3c_device_usb, | 509 | &s3c_device_ohci, |
| 510 | &s3c_device_wdt, | 510 | &s3c_device_wdt, |
| 511 | /* &s3c_device_adc,*/ /* ADC doesn't like living with touchscreen ! */ | ||
| 512 | &s3c_device_i2c0, | 511 | &s3c_device_i2c0, |
| 513 | &s3c_device_rtc, | 512 | &s3c_device_rtc, |
| 514 | &s3c_device_usbgadget, | 513 | &s3c_device_usbgadget, |
| @@ -522,8 +521,6 @@ static struct platform_device *mini2440_devices[] __initdata = { | |||
| 522 | &s3c_device_sdi, | 521 | &s3c_device_sdi, |
| 523 | &s3c_device_iis, | 522 | &s3c_device_iis, |
| 524 | &mini2440_audio, | 523 | &mini2440_audio, |
| 525 | /* &s3c_device_timer[0],*/ /* buzzer pwm, no API for it */ | ||
| 526 | /* remaining devices are optional */ | ||
| 527 | }; | 524 | }; |
| 528 | 525 | ||
| 529 | static void __init mini2440_map_io(void) | 526 | static void __init mini2440_map_io(void) |
| @@ -531,8 +528,6 @@ static void __init mini2440_map_io(void) | |||
| 531 | s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc)); | 528 | s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc)); |
| 532 | s3c24xx_init_clocks(12000000); | 529 | s3c24xx_init_clocks(12000000); |
| 533 | s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs)); | 530 | s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs)); |
| 534 | |||
| 535 | s3c_device_sdi.dev.platform_data = &mini2440_mmc_cfg; | ||
| 536 | } | 531 | } |
| 537 | 532 | ||
| 538 | /* | 533 | /* |
| @@ -678,6 +673,7 @@ static void __init mini2440_init(void) | |||
| 678 | } | 673 | } |
| 679 | 674 | ||
| 680 | s3c24xx_udc_set_platdata(&mini2440_udc_cfg); | 675 | s3c24xx_udc_set_platdata(&mini2440_udc_cfg); |
| 676 | s3c24xx_mci_set_platdata(&mini2440_mmc_cfg); | ||
| 681 | s3c_nand_set_platdata(&mini2440_nand_info); | 677 | s3c_nand_set_platdata(&mini2440_nand_info); |
| 682 | s3c_i2c0_set_platdata(NULL); | 678 | s3c_i2c0_set_platdata(NULL); |
| 683 | 679 | ||
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c index d43edede590e..86a243b3e37d 100644 --- a/arch/arm/mach-s3c2440/mach-nexcoder.c +++ b/arch/arm/mach-s3c2440/mach-nexcoder.c | |||
| @@ -106,7 +106,7 @@ static struct platform_device nexcoder_device_nor = { | |||
| 106 | /* Standard Nexcoder devices */ | 106 | /* Standard Nexcoder devices */ |
| 107 | 107 | ||
| 108 | static struct platform_device *nexcoder_devices[] __initdata = { | 108 | static struct platform_device *nexcoder_devices[] __initdata = { |
| 109 | &s3c_device_usb, | 109 | &s3c_device_ohci, |
| 110 | &s3c_device_lcd, | 110 | &s3c_device_lcd, |
| 111 | &s3c_device_wdt, | 111 | &s3c_device_wdt, |
| 112 | &s3c_device_i2c0, | 112 | &s3c_device_i2c0, |
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index a952a13afb1f..1e836e506f8b 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c | |||
| @@ -176,7 +176,7 @@ static struct s3c2410_platform_nand __initdata rx3715_nand_info = { | |||
| 176 | }; | 176 | }; |
| 177 | 177 | ||
| 178 | static struct platform_device *rx3715_devices[] __initdata = { | 178 | static struct platform_device *rx3715_devices[] __initdata = { |
| 179 | &s3c_device_usb, | 179 | &s3c_device_ohci, |
| 180 | &s3c_device_lcd, | 180 | &s3c_device_lcd, |
| 181 | &s3c_device_wdt, | 181 | &s3c_device_wdt, |
| 182 | &s3c_device_i2c0, | 182 | &s3c_device_i2c0, |
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c index ec13e748ccc5..df3e9a3be82f 100644 --- a/arch/arm/mach-s3c2440/mach-smdk2440.c +++ b/arch/arm/mach-s3c2440/mach-smdk2440.c | |||
| @@ -150,7 +150,7 @@ static struct s3c2410fb_mach_info smdk2440_fb_info __initdata = { | |||
| 150 | }; | 150 | }; |
| 151 | 151 | ||
| 152 | static struct platform_device *smdk2440_devices[] __initdata = { | 152 | static struct platform_device *smdk2440_devices[] __initdata = { |
| 153 | &s3c_device_usb, | 153 | &s3c_device_ohci, |
| 154 | &s3c_device_lcd, | 154 | &s3c_device_lcd, |
| 155 | &s3c_device_wdt, | 155 | &s3c_device_wdt, |
| 156 | &s3c_device_i2c0, | 156 | &s3c_device_i2c0, |
diff --git a/arch/arm/mach-s3c2442/clock.c b/arch/arm/mach-s3c2442/clock.c index ea1aa1f5157a..d9b692a12480 100644 --- a/arch/arm/mach-s3c2442/clock.c +++ b/arch/arm/mach-s3c2442/clock.c | |||
| @@ -109,8 +109,10 @@ static struct clk s3c2442_clk_cam = { | |||
| 109 | static struct clk s3c2442_clk_cam_upll = { | 109 | static struct clk s3c2442_clk_cam_upll = { |
| 110 | .name = "camif-upll", | 110 | .name = "camif-upll", |
| 111 | .id = -1, | 111 | .id = -1, |
| 112 | .set_rate = s3c2442_camif_upll_setrate, | 112 | .ops = &(struct clk_ops) { |
| 113 | .round_rate = s3c2442_camif_upll_round, | 113 | .set_rate = s3c2442_camif_upll_setrate, |
| 114 | .round_rate = s3c2442_camif_upll_round, | ||
| 115 | }, | ||
| 114 | }; | 116 | }; |
| 115 | 117 | ||
| 116 | static int s3c2442_clk_add(struct sys_device *sysdev) | 118 | static int s3c2442_clk_add(struct sys_device *sysdev) |
diff --git a/arch/arm/mach-s3c2442/mach-gta02.c b/arch/arm/mach-s3c2442/mach-gta02.c index 0b4a3a03071f..45799c608d8f 100644 --- a/arch/arm/mach-s3c2442/mach-gta02.c +++ b/arch/arm/mach-s3c2442/mach-gta02.c | |||
| @@ -544,7 +544,7 @@ static struct platform_device gta02_bl_dev = { | |||
| 544 | 544 | ||
| 545 | 545 | ||
| 546 | /* USB */ | 546 | /* USB */ |
| 547 | static struct s3c2410_hcd_info gta02_usb_info = { | 547 | static struct s3c2410_hcd_info gta02_usb_info __initdata = { |
| 548 | .port[0] = { | 548 | .port[0] = { |
| 549 | .flags = S3C_HCDFLG_USED, | 549 | .flags = S3C_HCDFLG_USED, |
| 550 | }, | 550 | }, |
| @@ -565,7 +565,7 @@ static void __init gta02_map_io(void) | |||
| 565 | /* These are the guys that don't need to be children of PMU. */ | 565 | /* These are the guys that don't need to be children of PMU. */ |
| 566 | 566 | ||
| 567 | static struct platform_device *gta02_devices[] __initdata = { | 567 | static struct platform_device *gta02_devices[] __initdata = { |
| 568 | &s3c_device_usb, | 568 | &s3c_device_ohci, |
| 569 | &s3c_device_wdt, | 569 | &s3c_device_wdt, |
| 570 | &s3c_device_sdi, | 570 | &s3c_device_sdi, |
| 571 | &s3c_device_usbgadget, | 571 | &s3c_device_usbgadget, |
| @@ -623,9 +623,8 @@ static void __init gta02_machine_init(void) | |||
| 623 | INIT_DELAYED_WORK(>a02_charger_work, gta02_charger_worker); | 623 | INIT_DELAYED_WORK(>a02_charger_work, gta02_charger_worker); |
| 624 | #endif | 624 | #endif |
| 625 | 625 | ||
| 626 | s3c_device_usb.dev.platform_data = >a02_usb_info; | ||
| 627 | |||
| 628 | s3c24xx_udc_set_platdata(>a02_udc_cfg); | 626 | s3c24xx_udc_set_platdata(>a02_udc_cfg); |
| 627 | s3c_ohci_set_platdata(>a02_usb_info); | ||
| 629 | s3c_nand_set_platdata(>a02_nand_info); | 628 | s3c_nand_set_platdata(>a02_nand_info); |
| 630 | s3c_i2c0_set_platdata(NULL); | 629 | s3c_i2c0_set_platdata(NULL); |
| 631 | 630 | ||
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 2785d69c95b0..3eb8b935d64c 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c | |||
| @@ -187,7 +187,9 @@ static int s3c2443_setparent_epllref(struct clk *clk, struct clk *parent) | |||
| 187 | static struct clk clk_epllref = { | 187 | static struct clk clk_epllref = { |
| 188 | .name = "epllref", | 188 | .name = "epllref", |
| 189 | .id = -1, | 189 | .id = -1, |
| 190 | .set_parent = s3c2443_setparent_epllref, | 190 | .ops = &(struct clk_ops) { |
| 191 | .set_parent = s3c2443_setparent_epllref, | ||
| 192 | }, | ||
| 191 | }; | 193 | }; |
| 192 | 194 | ||
| 193 | static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) | 195 | static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) |
| @@ -205,7 +207,9 @@ static struct clk clk_mdivclk = { | |||
| 205 | .name = "mdivclk", | 207 | .name = "mdivclk", |
| 206 | .parent = &clk_mpllref, | 208 | .parent = &clk_mpllref, |
| 207 | .id = -1, | 209 | .id = -1, |
| 208 | .get_rate = s3c2443_getrate_mdivclk, | 210 | .ops = &(struct clk_ops) { |
| 211 | .get_rate = s3c2443_getrate_mdivclk, | ||
| 212 | }, | ||
| 209 | }; | 213 | }; |
| 210 | 214 | ||
| 211 | static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent) | 215 | static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent) |
| @@ -232,7 +236,9 @@ static struct clk clk_msysclk = { | |||
| 232 | .name = "msysclk", | 236 | .name = "msysclk", |
| 233 | .parent = &clk_xtal, | 237 | .parent = &clk_xtal, |
| 234 | .id = -1, | 238 | .id = -1, |
| 235 | .set_parent = s3c2443_setparent_msysclk, | 239 | .ops = &(struct clk_ops) { |
| 240 | .set_parent = s3c2443_setparent_msysclk, | ||
| 241 | }, | ||
| 236 | }; | 242 | }; |
| 237 | 243 | ||
| 238 | /* armdiv | 244 | /* armdiv |
| @@ -273,7 +279,9 @@ static int s3c2443_setparent_armclk(struct clk *clk, struct clk *parent) | |||
| 273 | static struct clk clk_arm = { | 279 | static struct clk clk_arm = { |
| 274 | .name = "armclk", | 280 | .name = "armclk", |
| 275 | .id = -1, | 281 | .id = -1, |
| 276 | .set_parent = s3c2443_setparent_armclk, | 282 | .ops = &(struct clk_ops) { |
| 283 | .set_parent = s3c2443_setparent_armclk, | ||
| 284 | }, | ||
| 277 | }; | 285 | }; |
| 278 | 286 | ||
| 279 | /* esysclk | 287 | /* esysclk |
| @@ -302,7 +310,9 @@ static struct clk clk_esysclk = { | |||
| 302 | .name = "esysclk", | 310 | .name = "esysclk", |
| 303 | .parent = &clk_epll, | 311 | .parent = &clk_epll, |
| 304 | .id = -1, | 312 | .id = -1, |
| 305 | .set_parent = s3c2443_setparent_esysclk, | 313 | .ops = &(struct clk_ops) { |
| 314 | .set_parent = s3c2443_setparent_esysclk, | ||
| 315 | }, | ||
| 306 | }; | 316 | }; |
| 307 | 317 | ||
| 308 | /* uartclk | 318 | /* uartclk |
| @@ -341,9 +351,11 @@ static struct clk clk_uart = { | |||
| 341 | .name = "uartclk", | 351 | .name = "uartclk", |
| 342 | .id = -1, | 352 | .id = -1, |
| 343 | .parent = &clk_esysclk, | 353 | .parent = &clk_esysclk, |
| 344 | .get_rate = s3c2443_getrate_uart, | 354 | .ops = &(struct clk_ops) { |
| 345 | .set_rate = s3c2443_setrate_uart, | 355 | .get_rate = s3c2443_getrate_uart, |
| 346 | .round_rate = s3c2443_roundrate_clksrc16, | 356 | .set_rate = s3c2443_setrate_uart, |
| 357 | .round_rate = s3c2443_roundrate_clksrc16, | ||
| 358 | }, | ||
| 347 | }; | 359 | }; |
| 348 | 360 | ||
| 349 | /* hsspi | 361 | /* hsspi |
| @@ -384,9 +396,11 @@ static struct clk clk_hsspi = { | |||
| 384 | .parent = &clk_esysclk, | 396 | .parent = &clk_esysclk, |
| 385 | .ctrlbit = S3C2443_SCLKCON_HSSPICLK, | 397 | .ctrlbit = S3C2443_SCLKCON_HSSPICLK, |
| 386 | .enable = s3c2443_clkcon_enable_s, | 398 | .enable = s3c2443_clkcon_enable_s, |
| 387 | .get_rate = s3c2443_getrate_hsspi, | 399 | .ops = &(struct clk_ops) { |
| 388 | .set_rate = s3c2443_setrate_hsspi, | 400 | .get_rate = s3c2443_getrate_hsspi, |
| 389 | .round_rate = s3c2443_roundrate_clksrc4, | 401 | .set_rate = s3c2443_setrate_hsspi, |
| 402 | .round_rate = s3c2443_roundrate_clksrc4, | ||
| 403 | }, | ||
| 390 | }; | 404 | }; |
| 391 | 405 | ||
| 392 | /* usbhost | 406 | /* usbhost |
| @@ -426,9 +440,11 @@ static struct clk clk_usb_bus_host = { | |||
| 426 | .parent = &clk_esysclk, | 440 | .parent = &clk_esysclk, |
| 427 | .ctrlbit = S3C2443_SCLKCON_USBHOST, | 441 | .ctrlbit = S3C2443_SCLKCON_USBHOST, |
| 428 | .enable = s3c2443_clkcon_enable_s, | 442 | .enable = s3c2443_clkcon_enable_s, |
| 429 | .get_rate = s3c2443_getrate_usbhost, | 443 | .ops = &(struct clk_ops) { |
| 430 | .set_rate = s3c2443_setrate_usbhost, | 444 | .get_rate = s3c2443_getrate_usbhost, |
| 431 | .round_rate = s3c2443_roundrate_clksrc4, | 445 | .set_rate = s3c2443_setrate_usbhost, |
| 446 | .round_rate = s3c2443_roundrate_clksrc4, | ||
| 447 | }, | ||
| 432 | }; | 448 | }; |
| 433 | 449 | ||
| 434 | /* clk_hsmcc_div | 450 | /* clk_hsmcc_div |
| @@ -468,9 +484,11 @@ static struct clk clk_hsmmc_div = { | |||
| 468 | .name = "hsmmc-div", | 484 | .name = "hsmmc-div", |
| 469 | .id = -1, | 485 | .id = -1, |
| 470 | .parent = &clk_esysclk, | 486 | .parent = &clk_esysclk, |
| 471 | .get_rate = s3c2443_getrate_hsmmc_div, | 487 | .ops = &(struct clk_ops) { |
| 472 | .set_rate = s3c2443_setrate_hsmmc_div, | 488 | .get_rate = s3c2443_getrate_hsmmc_div, |
| 473 | .round_rate = s3c2443_roundrate_clksrc4, | 489 | .set_rate = s3c2443_setrate_hsmmc_div, |
| 490 | .round_rate = s3c2443_roundrate_clksrc4, | ||
| 491 | }, | ||
| 474 | }; | 492 | }; |
| 475 | 493 | ||
| 476 | static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent) | 494 | static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent) |
| @@ -505,7 +523,9 @@ static struct clk clk_hsmmc = { | |||
| 505 | .id = -1, | 523 | .id = -1, |
| 506 | .parent = &clk_hsmmc_div, | 524 | .parent = &clk_hsmmc_div, |
| 507 | .enable = s3c2443_enable_hsmmc, | 525 | .enable = s3c2443_enable_hsmmc, |
| 508 | .set_parent = s3c2443_setparent_hsmmc, | 526 | .ops = &(struct clk_ops) { |
| 527 | .set_parent = s3c2443_setparent_hsmmc, | ||
| 528 | }, | ||
| 509 | }; | 529 | }; |
| 510 | 530 | ||
| 511 | /* i2s_eplldiv | 531 | /* i2s_eplldiv |
| @@ -543,9 +563,11 @@ static struct clk clk_i2s_eplldiv = { | |||
| 543 | .name = "i2s-eplldiv", | 563 | .name = "i2s-eplldiv", |
| 544 | .id = -1, | 564 | .id = -1, |
| 545 | .parent = &clk_esysclk, | 565 | .parent = &clk_esysclk, |
| 546 | .get_rate = s3c2443_getrate_i2s_eplldiv, | 566 | .ops = &(struct clk_ops) { |
| 547 | .set_rate = s3c2443_setrate_i2s_eplldiv, | 567 | .get_rate = s3c2443_getrate_i2s_eplldiv, |
| 548 | .round_rate = s3c2443_roundrate_clksrc16, | 568 | .set_rate = s3c2443_setrate_i2s_eplldiv, |
| 569 | .round_rate = s3c2443_roundrate_clksrc16, | ||
| 570 | }, | ||
| 549 | }; | 571 | }; |
| 550 | 572 | ||
| 551 | /* i2s-ref | 573 | /* i2s-ref |
| @@ -578,7 +600,9 @@ static struct clk clk_i2s = { | |||
| 578 | .parent = &clk_i2s_eplldiv, | 600 | .parent = &clk_i2s_eplldiv, |
| 579 | .ctrlbit = S3C2443_SCLKCON_I2SCLK, | 601 | .ctrlbit = S3C2443_SCLKCON_I2SCLK, |
| 580 | .enable = s3c2443_clkcon_enable_s, | 602 | .enable = s3c2443_clkcon_enable_s, |
| 581 | .set_parent = s3c2443_setparent_i2s, | 603 | .ops = &(struct clk_ops) { |
| 604 | .set_parent = s3c2443_setparent_i2s, | ||
| 605 | }, | ||
| 582 | }; | 606 | }; |
| 583 | 607 | ||
| 584 | /* cam-if | 608 | /* cam-if |
| @@ -618,9 +642,11 @@ static struct clk clk_cam = { | |||
| 618 | .parent = &clk_esysclk, | 642 | .parent = &clk_esysclk, |
| 619 | .ctrlbit = S3C2443_SCLKCON_CAMCLK, | 643 | .ctrlbit = S3C2443_SCLKCON_CAMCLK, |
| 620 | .enable = s3c2443_clkcon_enable_s, | 644 | .enable = s3c2443_clkcon_enable_s, |
| 621 | .get_rate = s3c2443_getrate_cam, | 645 | .ops = &(struct clk_ops) { |
| 622 | .set_rate = s3c2443_setrate_cam, | 646 | .get_rate = s3c2443_getrate_cam, |
| 623 | .round_rate = s3c2443_roundrate_clksrc16, | 647 | .set_rate = s3c2443_setrate_cam, |
| 648 | .round_rate = s3c2443_roundrate_clksrc16, | ||
| 649 | }, | ||
| 624 | }; | 650 | }; |
| 625 | 651 | ||
| 626 | /* display-if | 652 | /* display-if |
| @@ -660,9 +686,11 @@ static struct clk clk_display = { | |||
| 660 | .parent = &clk_esysclk, | 686 | .parent = &clk_esysclk, |
| 661 | .ctrlbit = S3C2443_SCLKCON_DISPCLK, | 687 | .ctrlbit = S3C2443_SCLKCON_DISPCLK, |
| 662 | .enable = s3c2443_clkcon_enable_s, | 688 | .enable = s3c2443_clkcon_enable_s, |
| 663 | .get_rate = s3c2443_getrate_display, | 689 | .ops = &(struct clk_ops) { |
| 664 | .set_rate = s3c2443_setrate_display, | 690 | .get_rate = s3c2443_getrate_display, |
| 665 | .round_rate = s3c2443_roundrate_clksrc256, | 691 | .set_rate = s3c2443_setrate_display, |
| 692 | .round_rate = s3c2443_roundrate_clksrc256, | ||
| 693 | }, | ||
| 666 | }; | 694 | }; |
| 667 | 695 | ||
| 668 | /* prediv | 696 | /* prediv |
| @@ -685,7 +713,9 @@ static struct clk clk_prediv = { | |||
| 685 | .name = "prediv", | 713 | .name = "prediv", |
| 686 | .id = -1, | 714 | .id = -1, |
| 687 | .parent = &clk_msysclk, | 715 | .parent = &clk_msysclk, |
| 688 | .get_rate = s3c2443_prediv_getrate, | 716 | .ops = &(struct clk_ops) { |
| 717 | .get_rate = s3c2443_prediv_getrate, | ||
| 718 | }, | ||
| 689 | }; | 719 | }; |
| 690 | 720 | ||
| 691 | /* standard clock definitions */ | 721 | /* standard clock definitions */ |
| @@ -1074,14 +1104,7 @@ void __init s3c2443_init_clocks(int xtal) | |||
| 1074 | 1104 | ||
| 1075 | /* register clocks from clock array */ | 1105 | /* register clocks from clock array */ |
| 1076 | 1106 | ||
| 1077 | clkp = init_clocks; | 1107 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); |
| 1078 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { | ||
| 1079 | ret = s3c24xx_register_clock(clkp); | ||
| 1080 | if (ret < 0) { | ||
| 1081 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
| 1082 | clkp->name, ret); | ||
| 1083 | } | ||
| 1084 | } | ||
| 1085 | 1108 | ||
| 1086 | /* We must be careful disabling the clocks we are not intending to | 1109 | /* We must be careful disabling the clocks we are not intending to |
| 1087 | * be using at boot time, as subsystems such as the LCD which do | 1110 | * be using at boot time, as subsystems such as the LCD which do |
diff --git a/arch/arm/mach-s3c6400/include/mach/entry-macro.S b/arch/arm/mach-s3c6400/include/mach/entry-macro.S index fbd90d2cf355..33a8fe240882 100644 --- a/arch/arm/mach-s3c6400/include/mach/entry-macro.S +++ b/arch/arm/mach-s3c6400/include/mach/entry-macro.S | |||
| @@ -12,33 +12,7 @@ | |||
| 12 | * warranty of any kind, whether express or implied. | 12 | * warranty of any kind, whether express or implied. |
| 13 | */ | 13 | */ |
| 14 | 14 | ||
| 15 | #include <asm/hardware/vic.h> | ||
| 16 | #include <mach/map.h> | 15 | #include <mach/map.h> |
| 17 | #include <plat/irqs.h> | 16 | #include <plat/irqs.h> |
| 18 | 17 | ||
| 19 | .macro disable_fiq | 18 | #include <asm/entry-macro-vic2.S> |
| 20 | .endm | ||
| 21 | |||
| 22 | .macro get_irqnr_preamble, base, tmp | ||
| 23 | ldr \base, =S3C_VA_VIC0 | ||
| 24 | .endm | ||
| 25 | |||
| 26 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 27 | .endm | ||
| 28 | |||
| 29 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 30 | |||
| 31 | @ check the vic0 | ||
| 32 | mov \irqnr, # S3C_IRQ_OFFSET + 31 | ||
| 33 | ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] | ||
| 34 | teq \irqstat, #0 | ||
| 35 | |||
| 36 | @ otherwise try vic1 | ||
| 37 | addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0) | ||
| 38 | addeq \irqnr, \irqnr, #32 | ||
| 39 | ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] | ||
| 40 | teqeq \irqstat, #0 | ||
| 41 | |||
| 42 | clzne \irqstat, \irqstat | ||
| 43 | subne \irqnr, \irqnr, \irqstat | ||
| 44 | .endm | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/gpio-core.h b/arch/arm/mach-s3c6400/include/mach/gpio-core.h deleted file mode 100644 index d89aae68b0a5..000000000000 --- a/arch/arm/mach-s3c6400/include/mach/gpio-core.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* arch/arm/mach-s3c6400/include/mach/gpio-core.h | ||
| 2 | * | ||
| 3 | * Copyright 2008 Openmoko, Inc. | ||
| 4 | * Copyright 2008 Simtec Electronics | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * http://armlinux.simtec.co.uk/ | ||
| 7 | * | ||
| 8 | * S3C64XX - GPIO core support | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_GPIO_CORE_H | ||
| 16 | #define __ASM_ARCH_GPIO_CORE_H __FILE__ | ||
| 17 | |||
| 18 | /* currently we just include the platform support */ | ||
| 19 | #include <plat/gpio-core.h> | ||
| 20 | |||
| 21 | #endif /* __ASM_ARCH_GPIO_CORE_H */ | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h index 106ee13581e2..801c1c0f3a95 100644 --- a/arch/arm/mach-s3c6400/include/mach/map.h +++ b/arch/arm/mach-s3c6400/include/mach/map.h | |||
| @@ -17,6 +17,18 @@ | |||
| 17 | 17 | ||
| 18 | #include <plat/map-base.h> | 18 | #include <plat/map-base.h> |
| 19 | 19 | ||
| 20 | /* | ||
| 21 | * Post-mux Chip Select Regions Xm0CSn_ | ||
| 22 | * These may be used by SROM, NAND or CF depending on settings | ||
| 23 | */ | ||
| 24 | |||
| 25 | #define S3C64XX_PA_XM0CSN0 (0x10000000) | ||
| 26 | #define S3C64XX_PA_XM0CSN1 (0x18000000) | ||
| 27 | #define S3C64XX_PA_XM0CSN2 (0x20000000) | ||
| 28 | #define S3C64XX_PA_XM0CSN3 (0x28000000) | ||
| 29 | #define S3C64XX_PA_XM0CSN4 (0x30000000) | ||
| 30 | #define S3C64XX_PA_XM0CSN5 (0x38000000) | ||
| 31 | |||
| 20 | /* HSMMC units */ | 32 | /* HSMMC units */ |
| 21 | #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000)) | 33 | #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000)) |
| 22 | #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0) | 34 | #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0) |
| @@ -38,16 +50,22 @@ | |||
| 38 | #define S3C_VA_UART2 S3C_VA_UARTx(2) | 50 | #define S3C_VA_UART2 S3C_VA_UARTx(2) |
| 39 | #define S3C_VA_UART3 S3C_VA_UARTx(3) | 51 | #define S3C_VA_UART3 S3C_VA_UARTx(3) |
| 40 | 52 | ||
| 53 | #define S3C64XX_PA_SROM (0x70000000) | ||
| 54 | |||
| 41 | #define S3C64XX_PA_NAND (0x70200000) | 55 | #define S3C64XX_PA_NAND (0x70200000) |
| 42 | #define S3C64XX_PA_FB (0x77100000) | 56 | #define S3C64XX_PA_FB (0x77100000) |
| 43 | #define S3C64XX_PA_USB_HSOTG (0x7C000000) | 57 | #define S3C64XX_PA_USB_HSOTG (0x7C000000) |
| 44 | #define S3C64XX_PA_WATCHDOG (0x7E004000) | 58 | #define S3C64XX_PA_WATCHDOG (0x7E004000) |
| 59 | #define S3C64XX_PA_RTC (0x7E005000) | ||
| 60 | #define S3C64XX_PA_ADC (0x7E00B000) | ||
| 45 | #define S3C64XX_PA_SYSCON (0x7E00F000) | 61 | #define S3C64XX_PA_SYSCON (0x7E00F000) |
| 46 | #define S3C64XX_PA_AC97 (0x7F001000) | 62 | #define S3C64XX_PA_AC97 (0x7F001000) |
| 47 | #define S3C64XX_PA_IIS0 (0x7F002000) | 63 | #define S3C64XX_PA_IIS0 (0x7F002000) |
| 48 | #define S3C64XX_PA_IIS1 (0x7F003000) | 64 | #define S3C64XX_PA_IIS1 (0x7F003000) |
| 49 | #define S3C64XX_PA_TIMER (0x7F006000) | 65 | #define S3C64XX_PA_TIMER (0x7F006000) |
| 50 | #define S3C64XX_PA_IIC0 (0x7F004000) | 66 | #define S3C64XX_PA_IIC0 (0x7F004000) |
| 67 | #define S3C64XX_PA_SPI0 (0x7F00B000) | ||
| 68 | #define S3C64XX_PA_SPI1 (0x7F00C000) | ||
| 51 | #define S3C64XX_PA_PCM0 (0x7F009000) | 69 | #define S3C64XX_PA_PCM0 (0x7F009000) |
| 52 | #define S3C64XX_PA_PCM1 (0x7F00A000) | 70 | #define S3C64XX_PA_PCM1 (0x7F00A000) |
| 53 | #define S3C64XX_PA_IISV4 (0x7F00D000) | 71 | #define S3C64XX_PA_IISV4 (0x7F00D000) |
| @@ -70,8 +88,8 @@ | |||
| 70 | #define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000) | 88 | #define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000) |
| 71 | 89 | ||
| 72 | /* place VICs close together */ | 90 | /* place VICs close together */ |
| 73 | #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) | 91 | #define VA_VIC0 (S3C_VA_IRQ + 0x00) |
| 74 | #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) | 92 | #define VA_VIC1 (S3C_VA_IRQ + 0x10000) |
| 75 | 93 | ||
| 76 | /* compatibiltiy defines. */ | 94 | /* compatibiltiy defines. */ |
| 77 | #define S3C_PA_TIMER S3C64XX_PA_TIMER | 95 | #define S3C_PA_TIMER S3C64XX_PA_TIMER |
diff --git a/arch/arm/mach-s3c6400/include/mach/tick.h b/arch/arm/mach-s3c6400/include/mach/tick.h index d9c0dc7014ec..ebe18a9469b8 100644 --- a/arch/arm/mach-s3c6400/include/mach/tick.h +++ b/arch/arm/mach-s3c6400/include/mach/tick.h | |||
| @@ -20,7 +20,7 @@ | |||
| 20 | */ | 20 | */ |
| 21 | static inline u32 s3c24xx_ostimer_pending(void) | 21 | static inline u32 s3c24xx_ostimer_pending(void) |
| 22 | { | 22 | { |
| 23 | u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); | 23 | u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS); |
| 24 | return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0)); | 24 | return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0)); |
| 25 | } | 25 | } |
| 26 | 26 | ||
diff --git a/arch/arm/mach-s3c6410/mach-hmt.c b/arch/arm/mach-s3c6410/mach-hmt.c index 7619456f2ae8..f05d95784d72 100644 --- a/arch/arm/mach-s3c6410/mach-hmt.c +++ b/arch/arm/mach-s3c6410/mach-hmt.c | |||
| @@ -233,7 +233,7 @@ static struct platform_device *hmt_devices[] __initdata = { | |||
| 233 | &s3c_device_i2c0, | 233 | &s3c_device_i2c0, |
| 234 | &s3c_device_nand, | 234 | &s3c_device_nand, |
| 235 | &s3c_device_fb, | 235 | &s3c_device_fb, |
| 236 | &s3c_device_usb, | 236 | &s3c_device_ohci, |
| 237 | &s3c_device_timer[1], | 237 | &s3c_device_timer[1], |
| 238 | &hmt_backlight_device, | 238 | &hmt_backlight_device, |
| 239 | &hmt_leds_device, | 239 | &hmt_leds_device, |
diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c index 8969fe73b83f..eba345fadffe 100644 --- a/arch/arm/mach-s3c6410/mach-smdk6410.c +++ b/arch/arm/mach-s3c6410/mach-smdk6410.c | |||
| @@ -49,6 +49,7 @@ | |||
| 49 | #include <plat/regs-modem.h> | 49 | #include <plat/regs-modem.h> |
| 50 | #include <plat/regs-gpio.h> | 50 | #include <plat/regs-gpio.h> |
| 51 | #include <plat/regs-sys.h> | 51 | #include <plat/regs-sys.h> |
| 52 | #include <plat/regs-srom.h> | ||
| 52 | #include <plat/iic.h> | 53 | #include <plat/iic.h> |
| 53 | #include <plat/fb.h> | 54 | #include <plat/fb.h> |
| 54 | #include <plat/gpio-cfg.h> | 55 | #include <plat/gpio-cfg.h> |
| @@ -154,10 +155,20 @@ static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = { | |||
| 154 | .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, | 155 | .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, |
| 155 | }; | 156 | }; |
| 156 | 157 | ||
| 158 | /* | ||
| 159 | * Configuring Ethernet on SMDK6410 | ||
| 160 | * | ||
| 161 | * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6. | ||
| 162 | * The constant address below corresponds to nCS1 | ||
| 163 | * | ||
| 164 | * 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet" | ||
| 165 | * 2) CFG6 needs to be switched to "LAN9115" side | ||
| 166 | */ | ||
| 167 | |||
| 157 | static struct resource smdk6410_smsc911x_resources[] = { | 168 | static struct resource smdk6410_smsc911x_resources[] = { |
| 158 | [0] = { | 169 | [0] = { |
| 159 | .start = 0x18000000, | 170 | .start = S3C64XX_PA_XM0CSN1, |
| 160 | .end = 0x18000000 + SZ_64K - 1, | 171 | .end = S3C64XX_PA_XM0CSN1 + SZ_64K - 1, |
| 161 | .flags = IORESOURCE_MEM, | 172 | .flags = IORESOURCE_MEM, |
| 162 | }, | 173 | }, |
| 163 | [1] = { | 174 | [1] = { |
| @@ -235,7 +246,7 @@ static struct platform_device *smdk6410_devices[] __initdata = { | |||
| 235 | &s3c_device_i2c0, | 246 | &s3c_device_i2c0, |
| 236 | &s3c_device_i2c1, | 247 | &s3c_device_i2c1, |
| 237 | &s3c_device_fb, | 248 | &s3c_device_fb, |
| 238 | &s3c_device_usb, | 249 | &s3c_device_ohci, |
| 239 | &s3c_device_usb_hsotg, | 250 | &s3c_device_usb_hsotg, |
| 240 | 251 | ||
| 241 | #ifdef CONFIG_REGULATOR | 252 | #ifdef CONFIG_REGULATOR |
| @@ -388,6 +399,7 @@ static int __init smdk6410_wm8350_init(struct wm8350 *wm8350) | |||
| 388 | static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = { | 399 | static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = { |
| 389 | .init = smdk6410_wm8350_init, | 400 | .init = smdk6410_wm8350_init, |
| 390 | .irq_high = 1, | 401 | .irq_high = 1, |
| 402 | .irq_base = IRQ_BOARD_START, | ||
| 391 | }; | 403 | }; |
| 392 | #endif | 404 | #endif |
| 393 | 405 | ||
| @@ -430,10 +442,32 @@ static void __init smdk6410_map_io(void) | |||
| 430 | 442 | ||
| 431 | static void __init smdk6410_machine_init(void) | 443 | static void __init smdk6410_machine_init(void) |
| 432 | { | 444 | { |
| 445 | u32 cs1; | ||
| 446 | |||
| 433 | s3c_i2c0_set_platdata(NULL); | 447 | s3c_i2c0_set_platdata(NULL); |
| 434 | s3c_i2c1_set_platdata(NULL); | 448 | s3c_i2c1_set_platdata(NULL); |
| 435 | s3c_fb_set_platdata(&smdk6410_lcd_pdata); | 449 | s3c_fb_set_platdata(&smdk6410_lcd_pdata); |
| 436 | 450 | ||
| 451 | /* configure nCS1 width to 16 bits */ | ||
| 452 | |||
| 453 | cs1 = __raw_readl(S3C64XX_SROM_BW) & | ||
| 454 | ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT); | ||
| 455 | cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) | | ||
| 456 | (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) | | ||
| 457 | (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) << | ||
| 458 | S3C64XX_SROM_BW__NCS1__SHIFT; | ||
| 459 | __raw_writel(cs1, S3C64XX_SROM_BW); | ||
| 460 | |||
| 461 | /* set timing for nCS1 suitable for ethernet chip */ | ||
| 462 | |||
| 463 | __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) | | ||
| 464 | (6 << S3C64XX_SROM_BCX__TACP__SHIFT) | | ||
| 465 | (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) | | ||
| 466 | (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) | | ||
| 467 | (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) | | ||
| 468 | (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) | | ||
| 469 | (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1); | ||
| 470 | |||
| 437 | gpio_request(S3C64XX_GPN(5), "LCD power"); | 471 | gpio_request(S3C64XX_GPN(5), "LCD power"); |
| 438 | gpio_request(S3C64XX_GPF(13), "LCD power"); | 472 | gpio_request(S3C64XX_GPF(13), "LCD power"); |
| 439 | gpio_request(S3C64XX_GPF(15), "LCD power"); | 473 | gpio_request(S3C64XX_GPF(15), "LCD power"); |
diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig new file mode 100644 index 000000000000..3aa246244dcf --- /dev/null +++ b/arch/arm/mach-s5p6440/Kconfig | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | # arch/arm/mach-s5p6440/Kconfig | ||
| 2 | # | ||
| 3 | # Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | # http://www.samsung.com/ | ||
| 5 | # | ||
| 6 | # Licensed under GPLv2 | ||
| 7 | |||
| 8 | if ARCH_S5P6440 | ||
| 9 | |||
| 10 | config CPU_S5P6440 | ||
| 11 | bool | ||
| 12 | select CPU_S5P6440_INIT | ||
| 13 | select CPU_S5P6440_CLOCK | ||
| 14 | help | ||
| 15 | Enable S5P6440 CPU support | ||
| 16 | |||
| 17 | config MACH_SMDK6440 | ||
| 18 | bool "SMDK6440" | ||
| 19 | select CPU_S5P6440 | ||
| 20 | help | ||
| 21 | Machine support for the Samsung SMDK6440 | ||
| 22 | |||
| 23 | endif | ||
diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile new file mode 100644 index 000000000000..a79b13011edc --- /dev/null +++ b/arch/arm/mach-s5p6440/Makefile | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | # arch/arm/mach-s5p6440/Makefile | ||
| 2 | # | ||
| 3 | # Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | # http://www.samsung.com/ | ||
| 5 | # | ||
| 6 | # Licensed under GPLv2 | ||
| 7 | |||
| 8 | obj-y := | ||
| 9 | obj-m := | ||
| 10 | obj-n := | ||
| 11 | obj- := | ||
| 12 | |||
| 13 | # Core support for S5P6440 system | ||
| 14 | |||
| 15 | obj-$(CONFIG_CPU_S5P6440) += cpu.o s5p6440-gpio.o | ||
| 16 | |||
| 17 | # machine support | ||
| 18 | |||
| 19 | obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o | ||
diff --git a/arch/arm/mach-s5p6440/Makefile.boot b/arch/arm/mach-s5p6440/Makefile.boot new file mode 100644 index 000000000000..ff90aa13bd67 --- /dev/null +++ b/arch/arm/mach-s5p6440/Makefile.boot | |||
| @@ -0,0 +1,2 @@ | |||
| 1 | zreladdr-y := 0x20008000 | ||
| 2 | params_phys-y := 0x20000100 | ||
diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c new file mode 100644 index 000000000000..1794131aeacb --- /dev/null +++ b/arch/arm/mach-s5p6440/cpu.c | |||
| @@ -0,0 +1,114 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/cpu.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/types.h> | ||
| 13 | #include <linux/interrupt.h> | ||
| 14 | #include <linux/list.h> | ||
| 15 | #include <linux/timer.h> | ||
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/clk.h> | ||
| 18 | #include <linux/io.h> | ||
| 19 | #include <linux/sysdev.h> | ||
| 20 | #include <linux/serial_core.h> | ||
| 21 | #include <linux/platform_device.h> | ||
| 22 | |||
| 23 | #include <asm/mach/arch.h> | ||
| 24 | #include <asm/mach/map.h> | ||
| 25 | #include <asm/mach/irq.h> | ||
| 26 | |||
| 27 | #include <asm/proc-fns.h> | ||
| 28 | |||
| 29 | #include <mach/hardware.h> | ||
| 30 | #include <mach/map.h> | ||
| 31 | #include <asm/irq.h> | ||
| 32 | |||
| 33 | #include <plat/regs-serial.h> | ||
| 34 | #include <mach/regs-clock.h> | ||
| 35 | |||
| 36 | #include <plat/cpu.h> | ||
| 37 | #include <plat/devs.h> | ||
| 38 | #include <plat/clock.h> | ||
| 39 | #include <plat/s5p6440.h> | ||
| 40 | |||
| 41 | static void s5p6440_idle(void) | ||
| 42 | { | ||
| 43 | unsigned long val; | ||
| 44 | |||
| 45 | if (!need_resched()) { | ||
| 46 | val = __raw_readl(S5P_PWR_CFG); | ||
| 47 | val &= ~(0x3<<5); | ||
| 48 | val |= (0x1<<5); | ||
| 49 | __raw_writel(val, S5P_PWR_CFG); | ||
| 50 | |||
| 51 | cpu_do_idle(); | ||
| 52 | } | ||
| 53 | local_irq_enable(); | ||
| 54 | } | ||
| 55 | |||
| 56 | /* s5p6440_map_io | ||
| 57 | * | ||
| 58 | * register the standard cpu IO areas | ||
| 59 | */ | ||
| 60 | |||
| 61 | void __init s5p6440_map_io(void) | ||
| 62 | { | ||
| 63 | /* initialize any device information early */ | ||
| 64 | } | ||
| 65 | |||
| 66 | void __init s5p6440_init_clocks(int xtal) | ||
| 67 | { | ||
| 68 | printk(KERN_DEBUG "%s: initializing clocks\n", __func__); | ||
| 69 | |||
| 70 | s3c24xx_register_baseclocks(xtal); | ||
| 71 | s5p_register_clocks(xtal); | ||
| 72 | s5p6440_register_clocks(); | ||
| 73 | s5p6440_setup_clocks(); | ||
| 74 | } | ||
| 75 | |||
| 76 | void __init s5p6440_init_irq(void) | ||
| 77 | { | ||
| 78 | /* S5P6440 supports only 2 VIC */ | ||
| 79 | u32 vic[2]; | ||
| 80 | |||
| 81 | /* | ||
| 82 | * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)] | ||
| 83 | * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22] | ||
| 84 | */ | ||
| 85 | vic[0] = 0xff800ae7; | ||
| 86 | vic[1] = 0xffbf23e5; | ||
| 87 | |||
| 88 | s5p_init_irq(vic, ARRAY_SIZE(vic)); | ||
| 89 | } | ||
| 90 | |||
| 91 | static struct sysdev_class s5p6440_sysclass = { | ||
| 92 | .name = "s5p6440-core", | ||
| 93 | }; | ||
| 94 | |||
| 95 | static struct sys_device s5p6440_sysdev = { | ||
| 96 | .cls = &s5p6440_sysclass, | ||
| 97 | }; | ||
| 98 | |||
| 99 | static int __init s5p6440_core_init(void) | ||
| 100 | { | ||
| 101 | return sysdev_class_register(&s5p6440_sysclass); | ||
| 102 | } | ||
| 103 | |||
| 104 | core_initcall(s5p6440_core_init); | ||
| 105 | |||
| 106 | int __init s5p6440_init(void) | ||
| 107 | { | ||
| 108 | printk(KERN_INFO "S5P6440: Initializing architecture\n"); | ||
| 109 | |||
| 110 | /* set idle function */ | ||
| 111 | pm_idle = s5p6440_idle; | ||
| 112 | |||
| 113 | return sysdev_register(&s5p6440_sysdev); | ||
| 114 | } | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/debug-macro.S b/arch/arm/mach-s5p6440/include/mach/debug-macro.S new file mode 100644 index 000000000000..f3a5d1635be5 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/debug-macro.S | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/include/mach/debug-macro.S | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /* pull in the relevant register and map files. */ | ||
| 12 | |||
| 13 | #include <mach/map.h> | ||
| 14 | #include <plat/regs-serial.h> | ||
| 15 | |||
| 16 | /* note, for the boot process to work we have to keep the UART | ||
| 17 | * virtual address aligned to an 1MiB boundary for the L1 | ||
| 18 | * mapping the head code makes. We keep the UART virtual address | ||
| 19 | * aligned and add in the offset when we load the value here. | ||
| 20 | */ | ||
| 21 | |||
| 22 | .macro addruart, rx | ||
| 23 | mrc p15, 0, \rx, c1, c0 | ||
| 24 | tst \rx, #1 | ||
| 25 | ldreq \rx, = S5P_PA_UART | ||
| 26 | ldrne \rx, = (S5P_VA_UART + S5P_PA_UART & 0xfffff) | ||
| 27 | #if CONFIG_DEBUG_S3C_UART != 0 | ||
| 28 | add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) | ||
| 29 | #endif | ||
| 30 | .endm | ||
| 31 | |||
| 32 | /* include the reset of the code which will do the work, we're only | ||
| 33 | * compiling for a single cpu processor type so the default of s3c2440 | ||
| 34 | * will be fine with us. | ||
| 35 | */ | ||
| 36 | |||
| 37 | #include <plat/debug-macro.S> | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/entry-macro.S b/arch/arm/mach-s5p6440/include/mach/entry-macro.S new file mode 100644 index 000000000000..e65f1b967262 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/entry-macro.S | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/include/mach/entry-macro.S | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * Low-level IRQ helper macros for the Samsung S5P6440 | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <mach/map.h> | ||
| 14 | #include <plat/irqs.h> | ||
| 15 | |||
| 16 | #include <asm/entry-macro-vic2.S> | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/gpio.h b/arch/arm/mach-s5p6440/include/mach/gpio.h new file mode 100644 index 000000000000..21783834f2a2 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/gpio.h | |||
| @@ -0,0 +1,80 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/include/mach/gpio.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P6440 - GPIO lib support | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_GPIO_H | ||
| 14 | #define __ASM_ARCH_GPIO_H __FILE__ | ||
| 15 | |||
| 16 | #define gpio_get_value __gpio_get_value | ||
| 17 | #define gpio_set_value __gpio_set_value | ||
| 18 | #define gpio_cansleep __gpio_cansleep | ||
| 19 | #define gpio_to_irq __gpio_to_irq | ||
| 20 | |||
| 21 | /* GPIO bank sizes */ | ||
| 22 | #define S5P6440_GPIO_A_NR (6) | ||
| 23 | #define S5P6440_GPIO_B_NR (7) | ||
| 24 | #define S5P6440_GPIO_C_NR (8) | ||
| 25 | #define S5P6440_GPIO_F_NR (2) | ||
| 26 | #define S5P6440_GPIO_G_NR (7) | ||
| 27 | #define S5P6440_GPIO_H_NR (10) | ||
| 28 | #define S5P6440_GPIO_I_NR (16) | ||
| 29 | #define S5P6440_GPIO_J_NR (12) | ||
| 30 | #define S5P6440_GPIO_N_NR (16) | ||
| 31 | #define S5P6440_GPIO_P_NR (8) | ||
| 32 | #define S5P6440_GPIO_R_NR (15) | ||
| 33 | |||
| 34 | /* GPIO bank numbers */ | ||
| 35 | |||
| 36 | /* CONFIG_S3C_GPIO_SPACE allows the user to select extra | ||
| 37 | * space for debugging purposes so that any accidental | ||
| 38 | * change from one gpio bank to another can be caught. | ||
| 39 | */ | ||
| 40 | #define S5P6440_GPIO_NEXT(__gpio) \ | ||
| 41 | ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) | ||
| 42 | |||
| 43 | enum s5p_gpio_number { | ||
| 44 | S5P6440_GPIO_A_START = 0, | ||
| 45 | S5P6440_GPIO_B_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_A), | ||
| 46 | S5P6440_GPIO_C_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_B), | ||
| 47 | S5P6440_GPIO_F_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_C), | ||
| 48 | S5P6440_GPIO_G_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_F), | ||
| 49 | S5P6440_GPIO_H_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_G), | ||
| 50 | S5P6440_GPIO_I_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_H), | ||
| 51 | S5P6440_GPIO_J_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_I), | ||
| 52 | S5P6440_GPIO_N_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_J), | ||
| 53 | S5P6440_GPIO_P_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_N), | ||
| 54 | S5P6440_GPIO_R_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_P), | ||
| 55 | }; | ||
| 56 | |||
| 57 | /* S5P6440 GPIO number definitions. */ | ||
| 58 | #define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr)) | ||
| 59 | #define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr)) | ||
| 60 | #define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr)) | ||
| 61 | #define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr)) | ||
| 62 | #define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr)) | ||
| 63 | #define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr)) | ||
| 64 | #define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr)) | ||
| 65 | #define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr)) | ||
| 66 | #define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr)) | ||
| 67 | #define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr)) | ||
| 68 | #define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr)) | ||
| 69 | |||
| 70 | /* the end of the S5P6440 specific gpios */ | ||
| 71 | #define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1) | ||
| 72 | #define S3C_GPIO_END S5P6440_GPIO_END | ||
| 73 | |||
| 74 | /* define the number of gpios we need to the one after the GPR() range */ | ||
| 75 | #define ARCH_NR_GPIOS (S5P6440_GPR(S5P6440_GPIO_R_NR) + \ | ||
| 76 | CONFIG_SAMSUNG_GPIO_EXTRA + 1) | ||
| 77 | |||
| 78 | #include <asm-generic/gpio.h> | ||
| 79 | |||
| 80 | #endif /* __ASM_ARCH_GPIO_H */ | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/hardware.h b/arch/arm/mach-s5p6440/include/mach/hardware.h new file mode 100644 index 000000000000..be8b26e875db --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/hardware.h | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/include/mach/hardware.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P6440 - Hardware support | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 14 | #define __ASM_ARCH_HARDWARE_H __FILE__ | ||
| 15 | |||
| 16 | /* currently nothing here, placeholder */ | ||
| 17 | |||
| 18 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/irqs.h b/arch/arm/mach-s5p6440/include/mach/irqs.h new file mode 100644 index 000000000000..a4b9b40d18f2 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/irqs.h | |||
| @@ -0,0 +1,111 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/include/mach/irqs.h | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P6440 - IRQ definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_S5P_IRQS_H | ||
| 14 | #define __ASM_ARCH_S5P_IRQS_H __FILE__ | ||
| 15 | |||
| 16 | #include <plat/irqs.h> | ||
| 17 | |||
| 18 | /* VIC0 */ | ||
| 19 | |||
| 20 | #define IRQ_EINT0_3 S5P_IRQ_VIC0(0) | ||
| 21 | #define IRQ_EINT4_11 S5P_IRQ_VIC0(1) | ||
| 22 | #define IRQ_RTC_TIC S5P_IRQ_VIC0(2) | ||
| 23 | #define IRQ_IIC1 S5P_IRQ_VIC0(5) | ||
| 24 | #define IRQ_I2SV40 S5P_IRQ_VIC0(6) | ||
| 25 | #define IRQ_GPS S5P_IRQ_VIC0(7) | ||
| 26 | #define IRQ_POST0 S5P_IRQ_VIC0(9) | ||
| 27 | #define IRQ_2D S5P_IRQ_VIC0(11) | ||
| 28 | #define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23) | ||
| 29 | #define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24) | ||
| 30 | #define IRQ_TIMER2_VIC S5P_IRQ_VIC0(25) | ||
| 31 | #define IRQ_WDT S5P_IRQ_VIC0(26) | ||
| 32 | #define IRQ_TIMER3_VIC S5P_IRQ_VIC0(27) | ||
| 33 | #define IRQ_TIMER4_VIC S5P_IRQ_VIC0(28) | ||
| 34 | #define IRQ_DISPCON0 S5P_IRQ_VIC0(29) | ||
| 35 | #define IRQ_DISPCON1 S5P_IRQ_VIC0(30) | ||
| 36 | #define IRQ_DISPCON2 S5P_IRQ_VIC0(31) | ||
| 37 | |||
| 38 | /* VIC1 */ | ||
| 39 | |||
| 40 | #define IRQ_EINT12_15 S5P_IRQ_VIC1(0) | ||
| 41 | #define IRQ_PCM0 S5P_IRQ_VIC1(2) | ||
| 42 | #define IRQ_UART0 S5P_IRQ_VIC1(5) | ||
| 43 | #define IRQ_UART1 S5P_IRQ_VIC1(6) | ||
| 44 | #define IRQ_UART2 S5P_IRQ_VIC1(7) | ||
| 45 | #define IRQ_UART3 S5P_IRQ_VIC1(8) | ||
| 46 | #define IRQ_DMA0 S5P_IRQ_VIC1(9) | ||
| 47 | #define IRQ_NFC S5P_IRQ_VIC1(13) | ||
| 48 | #define IRQ_SPI0 S5P_IRQ_VIC1(16) | ||
| 49 | #define IRQ_SPI1 S5P_IRQ_VIC1(17) | ||
| 50 | #define IRQ_IIC S5P_IRQ_VIC1(18) | ||
| 51 | #define IRQ_DISPCON3 S5P_IRQ_VIC1(19) | ||
| 52 | #define IRQ_FIMGVG S5P_IRQ_VIC1(20) | ||
| 53 | #define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21) | ||
| 54 | #define IRQ_PMUIRQ S5P_IRQ_VIC1(23) | ||
| 55 | #define IRQ_HSMMC0 S5P_IRQ_VIC1(24) | ||
| 56 | #define IRQ_HSMMC1 S5P_IRQ_VIC1(25) | ||
| 57 | #define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ | ||
| 58 | #define IRQ_OTG S5P_IRQ_VIC1(26) | ||
| 59 | #define IRQ_DSI S5P_IRQ_VIC1(27) | ||
| 60 | #define IRQ_RTC_ALARM S5P_IRQ_VIC1(28) | ||
| 61 | #define IRQ_TSI S5P_IRQ_VIC1(29) | ||
| 62 | #define IRQ_PENDN S5P_IRQ_VIC1(30) | ||
| 63 | #define IRQ_TC IRQ_PENDN | ||
| 64 | #define IRQ_ADC S5P_IRQ_VIC1(31) | ||
| 65 | |||
| 66 | /* | ||
| 67 | * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined | ||
| 68 | * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place | ||
| 69 | * after the pair of VICs. | ||
| 70 | */ | ||
| 71 | |||
| 72 | #define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6) | ||
| 73 | |||
| 74 | #define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE) | ||
| 75 | #define IRQ_EINT(x) S5P_EINT(x) | ||
| 76 | |||
| 77 | /* | ||
| 78 | * Next the external interrupt groups. These are similar to the IRQ_EINT(x) | ||
| 79 | * that they are sourced from the GPIO pins but with a different scheme for | ||
| 80 | * priority and source indication. | ||
| 81 | * | ||
| 82 | * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO | ||
| 83 | * interrupts, but for historical reasons they are kept apart from these | ||
| 84 | * next interrupts. | ||
| 85 | * | ||
| 86 | * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the | ||
| 87 | * machine specific support files. | ||
| 88 | */ | ||
| 89 | |||
| 90 | /* Actually, #6 and #7 are missing in the EINT_GROUP1 */ | ||
| 91 | #define IRQ_EINT_GROUP1_NR (15) | ||
| 92 | #define IRQ_EINT_GROUP2_NR (8) | ||
| 93 | #define IRQ_EINT_GROUP5_NR (7) | ||
| 94 | #define IRQ_EINT_GROUP6_NR (10) | ||
| 95 | /* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */ | ||
| 96 | #define IRQ_EINT_GROUP8_NR (11) | ||
| 97 | |||
| 98 | #define IRQ_EINT_GROUP_BASE S5P_EINT(16) | ||
| 99 | #define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0) | ||
| 100 | #define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) | ||
| 101 | #define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) | ||
| 102 | #define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) | ||
| 103 | #define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) | ||
| 104 | |||
| 105 | #define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x)) | ||
| 106 | |||
| 107 | /* Set the default NR_IRQS */ | ||
| 108 | |||
| 109 | #define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1) | ||
| 110 | |||
| 111 | #endif /* __ASM_ARCH_S5P_IRQS_H */ | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h new file mode 100644 index 000000000000..4a73e73c9428 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/map.h | |||
| @@ -0,0 +1,107 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/include/mach/map.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P6440 - Memory map definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_MAP_H | ||
| 14 | #define __ASM_ARCH_MAP_H __FILE__ | ||
| 15 | |||
| 16 | #include <plat/map-base.h> | ||
| 17 | |||
| 18 | /* Chip ID */ | ||
| 19 | #define S5P6440_PA_CHIPID (0xE0000000) | ||
| 20 | #define S5P_PA_CHIPID S5P6440_PA_CHIPID | ||
| 21 | #define S5P_VA_CHIPID S3C_ADDR(0x00700000) | ||
| 22 | |||
| 23 | /* SYSCON */ | ||
| 24 | #define S5P6440_PA_SYSCON (0xE0100000) | ||
| 25 | #define S5P_PA_SYSCON S5P6440_PA_SYSCON | ||
| 26 | #define S5P_VA_SYSCON S3C_VA_SYS | ||
| 27 | |||
| 28 | #define S5P6440_PA_CLK (S5P6440_PA_SYSCON + 0x0) | ||
| 29 | #define S5P_PA_CLK S5P6440_PA_CLK | ||
| 30 | #define S5P_VA_CLK (S5P_VA_SYSCON + 0x0) | ||
| 31 | |||
| 32 | /* GPIO */ | ||
| 33 | #define S5P6440_PA_GPIO (0xE0308000) | ||
| 34 | #define S5P_PA_GPIO S5P6440_PA_GPIO | ||
| 35 | #define S5P_VA_GPIO S3C_ADDR(0x00500000) | ||
| 36 | |||
| 37 | /* VIC0 */ | ||
| 38 | #define S5P6440_PA_VIC0 (0xE4000000) | ||
| 39 | #define S5P_PA_VIC0 S5P6440_PA_VIC0 | ||
| 40 | #define S5P_VA_VIC0 (S3C_VA_IRQ + 0x0) | ||
| 41 | #define VA_VIC0 S5P_VA_VIC0 | ||
| 42 | |||
| 43 | /* VIC1 */ | ||
| 44 | #define S5P6440_PA_VIC1 (0xE4100000) | ||
| 45 | #define S5P_PA_VIC1 S5P6440_PA_VIC1 | ||
| 46 | #define S5P_VA_VIC1 (S3C_VA_IRQ + 0x10000) | ||
| 47 | #define VA_VIC1 S5P_VA_VIC1 | ||
| 48 | |||
| 49 | /* Timer */ | ||
| 50 | #define S5P6440_PA_TIMER (0xEA000000) | ||
| 51 | #define S5P_PA_TIMER S5P6440_PA_TIMER | ||
| 52 | #define S5P_VA_TIMER S3C_VA_TIMER | ||
| 53 | |||
| 54 | /* RTC */ | ||
| 55 | #define S5P6440_PA_RTC (0xEA100000) | ||
| 56 | #define S5P_PA_RTC S5P6440_PA_RTC | ||
| 57 | #define S5P_VA_RTC S3C_ADDR(0x00600000) | ||
| 58 | |||
| 59 | /* WDT */ | ||
| 60 | #define S5P6440_PA_WDT (0xEA200000) | ||
| 61 | #define S5P_PA_WDT S5P6440_PA_WDT | ||
| 62 | #define S5p_VA_WDT S3C_VA_WATCHDOG | ||
| 63 | |||
| 64 | /* UART */ | ||
| 65 | #define S5P6440_PA_UART (0xEC000000) | ||
| 66 | #define S5P_PA_UART S5P6440_PA_UART | ||
| 67 | #define S5P_VA_UART S3C_VA_UART | ||
| 68 | |||
| 69 | /* HS USB OtG */ | ||
| 70 | #define S5P6440_PA_HSOTG (0xED100000) | ||
| 71 | |||
| 72 | /* HSMMC */ | ||
| 73 | #define S5P6440_PA_HSMMC0 (0xED800000) | ||
| 74 | #define S5P6440_PA_HSMMC1 (0xED900000) | ||
| 75 | #define S5P6440_PA_HSMMC2 (0xEDA00000) | ||
| 76 | |||
| 77 | #define S5P_PA_UART0 (S5P_PA_UART + 0x0) | ||
| 78 | #define S5P_PA_UART1 (S5P_PA_UART + 0x400) | ||
| 79 | #define S5P_PA_UART2 (S5P_PA_UART + 0x800) | ||
| 80 | #define S5P_PA_UART3 (S5P_PA_UART + 0xC00) | ||
| 81 | #define S5P_UART_OFFSET (0x400) | ||
| 82 | |||
| 83 | #define S5P_VA_UARTx(x) (S5P_VA_UART + (S5P_PA_UART & 0xfffff) \ | ||
| 84 | + ((x) * S5P_UART_OFFSET)) | ||
| 85 | |||
| 86 | #define S5P_VA_UART0 S5P_VA_UARTx(0) | ||
| 87 | #define S5P_VA_UART1 S5P_VA_UARTx(1) | ||
| 88 | #define S5P_VA_UART2 S5P_VA_UARTx(2) | ||
| 89 | #define S5P_VA_UART3 S5P_VA_UARTx(3) | ||
| 90 | #define S5P_SZ_UART SZ_256 | ||
| 91 | |||
| 92 | /* I2C */ | ||
| 93 | #define S5P6440_PA_IIC0 (0xEC104000) | ||
| 94 | #define S5P_PA_IIC0 S5P6440_PA_IIC0 | ||
| 95 | #define S5p_VA_IIC0 S3C_ADDR(0x00700000) | ||
| 96 | |||
| 97 | /* SDRAM */ | ||
| 98 | #define S5P6440_PA_SDRAM (0x20000000) | ||
| 99 | #define S5P_PA_SDRAM S5P6440_PA_SDRAM | ||
| 100 | |||
| 101 | /* compatibiltiy defines. */ | ||
| 102 | #define S3C_PA_UART S5P_PA_UART | ||
| 103 | #define S3C_UART_OFFSET S5P_UART_OFFSET | ||
| 104 | #define S3C_PA_TIMER S5P_PA_TIMER | ||
| 105 | #define S3C_PA_IIC S5P_PA_IIC0 | ||
| 106 | |||
| 107 | #endif /* __ASM_ARCH_MAP_H */ | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/memory.h b/arch/arm/mach-s5p6440/include/mach/memory.h new file mode 100644 index 000000000000..d62910c71b56 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/memory.h | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/include/mach/memory.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P6440 - Memory definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 14 | #define __ASM_ARCH_MEMORY_H | ||
| 15 | |||
| 16 | #define PHYS_OFFSET UL(0x20000000) | ||
| 17 | #define CONSISTENT_DMA_SIZE SZ_8M | ||
| 18 | |||
| 19 | #endif /* __ASM_ARCH_MEMORY_H */ | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h new file mode 100644 index 000000000000..c4bb7c555477 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h | ||
| 2 | * | ||
| 3 | * Copyright 2008 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * http://armlinux.simtec.co.uk/ | ||
| 6 | * | ||
| 7 | * Copyright 2009 Samsung Electronics Co., Ltd. | ||
| 8 | * http://www.samsung.com/ | ||
| 9 | * | ||
| 10 | * S5P6440 - pwm clock and timer support | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | /** | ||
| 18 | * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk | ||
| 19 | * @cfg: The timer TCFG1 register bits shifted down to 0. | ||
| 20 | * | ||
| 21 | * Return true if the given configuration from TCFG1 is a TCLK instead | ||
| 22 | * any of the TDIV clocks. | ||
| 23 | */ | ||
| 24 | static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) | ||
| 25 | { | ||
| 26 | return tcfg == S3C2410_TCFG1_MUX_TCLK; | ||
| 27 | } | ||
| 28 | |||
| 29 | /** | ||
| 30 | * tcfg_to_divisor() - convert tcfg1 setting to a divisor | ||
| 31 | * @tcfg1: The tcfg1 setting, shifted down. | ||
| 32 | * | ||
| 33 | * Get the divisor value for the given tcfg1 setting. We assume the | ||
| 34 | * caller has already checked to see if this is not a TCLK source. | ||
| 35 | */ | ||
| 36 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | ||
| 37 | { | ||
| 38 | return 1 << (1 + tcfg1); | ||
| 39 | } | ||
| 40 | |||
| 41 | /** | ||
| 42 | * pwm_tdiv_has_div1() - does the tdiv setting have a /1 | ||
| 43 | * | ||
| 44 | * Return true if we have a /1 in the tdiv setting. | ||
| 45 | */ | ||
| 46 | static inline unsigned int pwm_tdiv_has_div1(void) | ||
| 47 | { | ||
| 48 | return 0; | ||
| 49 | } | ||
| 50 | |||
| 51 | /** | ||
| 52 | * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. | ||
| 53 | * @div: The divisor to calculate the bit information for. | ||
| 54 | * | ||
| 55 | * Turn a divisor into the necessary bit field for TCFG1. | ||
| 56 | */ | ||
| 57 | static inline unsigned long pwm_tdiv_div_bits(unsigned int div) | ||
| 58 | { | ||
| 59 | return ilog2(div) - 1; | ||
| 60 | } | ||
| 61 | |||
| 62 | #define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-clock.h b/arch/arm/mach-s5p6440/include/mach/regs-clock.h new file mode 100644 index 000000000000..b7af28342bc4 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/regs-clock.h | |||
| @@ -0,0 +1,130 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/include/mach/regs-clock.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P6440 - Clock register definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_REGS_CLOCK_H | ||
| 14 | #define __ASM_ARCH_REGS_CLOCK_H __FILE__ | ||
| 15 | |||
| 16 | #include <mach/map.h> | ||
| 17 | |||
| 18 | #define S5P_CLKREG(x) (S5P_VA_CLK + (x)) | ||
| 19 | |||
| 20 | #define S5P_APLL_LOCK S5P_CLKREG(0x00) | ||
| 21 | #define S5P_MPLL_LOCK S5P_CLKREG(0x04) | ||
| 22 | #define S5P_EPLL_LOCK S5P_CLKREG(0x08) | ||
| 23 | #define S5P_APLL_CON S5P_CLKREG(0x0C) | ||
| 24 | #define S5P_MPLL_CON S5P_CLKREG(0x10) | ||
| 25 | #define S5P_EPLL_CON S5P_CLKREG(0x14) | ||
| 26 | #define S5P_EPLL_CON_K S5P_CLKREG(0x18) | ||
| 27 | #define S5P_CLK_SRC0 S5P_CLKREG(0x1C) | ||
| 28 | #define S5P_CLK_DIV0 S5P_CLKREG(0x20) | ||
| 29 | #define S5P_CLK_DIV1 S5P_CLKREG(0x24) | ||
| 30 | #define S5P_CLK_DIV2 S5P_CLKREG(0x28) | ||
| 31 | #define S5P_CLK_OUT S5P_CLKREG(0x2C) | ||
| 32 | #define S5P_CLK_GATE_HCLK0 S5P_CLKREG(0x30) | ||
| 33 | #define S5P_CLK_GATE_PCLK S5P_CLKREG(0x34) | ||
| 34 | #define S5P_CLK_GATE_SCLK0 S5P_CLKREG(0x38) | ||
| 35 | #define S5P_CLK_GATE_MEM0 S5P_CLKREG(0x3C) | ||
| 36 | #define S5P_CLK_DIV3 S5P_CLKREG(0x40) | ||
| 37 | #define S5P_CLK_GATE_HCLK1 S5P_CLKREG(0x44) | ||
| 38 | #define S5P_CLK_GATE_SCLK1 S5P_CLKREG(0x48) | ||
| 39 | #define S5P_AHB_CON0 S5P_CLKREG(0x100) | ||
| 40 | #define S5P_CLK_SRC1 S5P_CLKREG(0x10C) | ||
| 41 | #define S5P_SWRESET S5P_CLKREG(0x114) | ||
| 42 | #define S5P_SYS_ID S5P_CLKREG(0x118) | ||
| 43 | #define S5P_SYS_OTHERS S5P_CLKREG(0x11C) | ||
| 44 | #define S5P_MEM_CFG_STAT S5P_CLKREG(0x12C) | ||
| 45 | #define S5P_PWR_CFG S5P_CLKREG(0x804) | ||
| 46 | #define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0x808) | ||
| 47 | #define S5P_NORMAL_CFG S5P_CLKREG(0x810) | ||
| 48 | #define S5P_STOP_CFG S5P_CLKREG(0x814) | ||
| 49 | #define S5P_SLEEP_CFG S5P_CLKREG(0x818) | ||
| 50 | #define S5P_OSC_FREQ S5P_CLKREG(0x820) | ||
| 51 | #define S5P_OSC_STABLE S5P_CLKREG(0x824) | ||
| 52 | #define S5P_PWR_STABLE S5P_CLKREG(0x828) | ||
| 53 | #define S5P_MTC_STABLE S5P_CLKREG(0x830) | ||
| 54 | #define S5P_OTHERS S5P_CLKREG(0x900) | ||
| 55 | #define S5P_RST_STAT S5P_CLKREG(0x904) | ||
| 56 | #define S5P_WAKEUP_STAT S5P_CLKREG(0x908) | ||
| 57 | #define S5P_SLPEN S5P_CLKREG(0x930) | ||
| 58 | #define S5P_INFORM0 S5P_CLKREG(0xA00) | ||
| 59 | #define S5P_INFORM1 S5P_CLKREG(0xA04) | ||
| 60 | #define S5P_INFORM2 S5P_CLKREG(0xA08) | ||
| 61 | #define S5P_INFORM3 S5P_CLKREG(0xA0C) | ||
| 62 | |||
| 63 | /* CLKDIV0 */ | ||
| 64 | #define S5P_CLKDIV0_PCLK_MASK (0xf << 12) | ||
| 65 | #define S5P_CLKDIV0_PCLK_SHIFT (12) | ||
| 66 | #define S5P_CLKDIV0_HCLK_MASK (0xf << 8) | ||
| 67 | #define S5P_CLKDIV0_HCLK_SHIFT (8) | ||
| 68 | #define S5P_CLKDIV0_MPLL_MASK (0x1 << 4) | ||
| 69 | #define S5P_CLKDIV0_ARM_MASK (0xf << 0) | ||
| 70 | #define S5P_CLKDIV0_ARM_SHIFT (0) | ||
| 71 | |||
| 72 | /* CLKDIV3 */ | ||
| 73 | #define S5P_CLKDIV3_PCLK_LOW_MASK (0xf << 12) | ||
| 74 | #define S5P_CLKDIV3_PCLK_LOW_SHIFT (12) | ||
| 75 | #define S5P_CLKDIV3_HCLK_LOW_MASK (0xf << 8) | ||
| 76 | #define S5P_CLKDIV3_HCLK_LOW_SHIFT (8) | ||
| 77 | |||
| 78 | /* HCLK0 GATE Registers */ | ||
| 79 | #define S5P_CLKCON_HCLK0_USB (1<<20) | ||
| 80 | #define S5P_CLKCON_HCLK0_HSMMC2 (1<<19) | ||
| 81 | #define S5P_CLKCON_HCLK0_HSMMC1 (1<<18) | ||
| 82 | #define S5P_CLKCON_HCLK0_HSMMC0 (1<<17) | ||
| 83 | #define S5P_CLKCON_HCLK0_POST0 (1<<5) | ||
| 84 | |||
| 85 | /* HCLK1 GATE Registers */ | ||
| 86 | #define S5P_CLKCON_HCLK1_DISPCON (1<<1) | ||
| 87 | |||
| 88 | /* PCLK GATE Registers */ | ||
| 89 | #define S5P_CLKCON_PCLK_IIS2 (1<<26) | ||
| 90 | #define S5P_CLKCON_PCLK_SPI1 (1<<22) | ||
| 91 | #define S5P_CLKCON_PCLK_SPI0 (1<<21) | ||
| 92 | #define S5P_CLKCON_PCLK_GPIO (1<<18) | ||
| 93 | #define S5P_CLKCON_PCLK_IIC0 (1<<17) | ||
| 94 | #define S5P_CLKCON_PCLK_TSADC (1<<12) | ||
| 95 | #define S5P_CLKCON_PCLK_PWM (1<<7) | ||
| 96 | #define S5P_CLKCON_PCLK_RTC (1<<6) | ||
| 97 | #define S5P_CLKCON_PCLK_WDT (1<<5) | ||
| 98 | #define S5P_CLKCON_PCLK_UART3 (1<<4) | ||
| 99 | #define S5P_CLKCON_PCLK_UART2 (1<<3) | ||
| 100 | #define S5P_CLKCON_PCLK_UART1 (1<<2) | ||
| 101 | #define S5P_CLKCON_PCLK_UART0 (1<<1) | ||
| 102 | |||
| 103 | /* SCLK0 GATE Registers */ | ||
| 104 | #define S5P_CLKCON_SCLK0_MMC2_48 (1<<29) | ||
| 105 | #define S5P_CLKCON_SCLK0_MMC1_48 (1<<28) | ||
| 106 | #define S5P_CLKCON_SCLK0_MMC0_48 (1<<27) | ||
| 107 | #define S5P_CLKCON_SCLK0_MMC2 (1<<26) | ||
| 108 | #define S5P_CLKCON_SCLK0_MMC1 (1<<25) | ||
| 109 | #define S5P_CLKCON_SCLK0_MMC0 (1<<24) | ||
| 110 | #define S5P_CLKCON_SCLK0_SPI1_48 (1<<23) | ||
| 111 | #define S5P_CLKCON_SCLK0_SPI0_48 (1<<22) | ||
| 112 | #define S5P_CLKCON_SCLK0_SPI1 (1<<21) | ||
| 113 | #define S5P_CLKCON_SCLK0_SPI0 (1<<20) | ||
| 114 | #define S5P_CLKCON_SCLK0_UART (1<<5) | ||
| 115 | |||
| 116 | /* SCLK1 GATE Registers */ | ||
| 117 | |||
| 118 | /* MEM0 GATE Registers */ | ||
| 119 | #define S5P_CLKCON_MEM0_HCLK_NFCON (1<<2) | ||
| 120 | |||
| 121 | /*OTHERS Resgister */ | ||
| 122 | #define S5P_OTHERS_USB_SIG_MASK (1<<16) | ||
| 123 | #define S5P_OTHERS_HCLK_LOW_SEL_MPLL (1<<6) | ||
| 124 | |||
| 125 | /* Compatibility defines */ | ||
| 126 | #define ARM_CLK_DIV S5P_CLK_DIV0 | ||
| 127 | #define ARM_DIV_RATIO_SHIFT 0 | ||
| 128 | #define ARM_DIV_MASK (0xf << ARM_DIV_RATIO_SHIFT) | ||
| 129 | |||
| 130 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-gpio.h b/arch/arm/mach-s5p6440/include/mach/regs-gpio.h new file mode 100644 index 000000000000..82ff753913da --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/regs-gpio.h | |||
| @@ -0,0 +1,54 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/include/mach/regs-gpio.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P6440 - GPIO register definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_REGS_GPIO_H | ||
| 14 | #define __ASM_ARCH_REGS_GPIO_H __FILE__ | ||
| 15 | |||
| 16 | #include <mach/map.h> | ||
| 17 | |||
| 18 | /* Base addresses for each of the banks */ | ||
| 19 | #define S5P6440_GPA_BASE (S5P_VA_GPIO + 0x0000) | ||
| 20 | #define S5P6440_GPB_BASE (S5P_VA_GPIO + 0x0020) | ||
| 21 | #define S5P6440_GPC_BASE (S5P_VA_GPIO + 0x0040) | ||
| 22 | #define S5P6440_GPF_BASE (S5P_VA_GPIO + 0x00A0) | ||
| 23 | #define S5P6440_GPG_BASE (S5P_VA_GPIO + 0x00C0) | ||
| 24 | #define S5P6440_GPH_BASE (S5P_VA_GPIO + 0x00E0) | ||
| 25 | #define S5P6440_GPI_BASE (S5P_VA_GPIO + 0x0100) | ||
| 26 | #define S5P6440_GPJ_BASE (S5P_VA_GPIO + 0x0120) | ||
| 27 | #define S5P6440_GPN_BASE (S5P_VA_GPIO + 0x0830) | ||
| 28 | #define S5P6440_GPP_BASE (S5P_VA_GPIO + 0x0160) | ||
| 29 | #define S5P6440_GPR_BASE (S5P_VA_GPIO + 0x0290) | ||
| 30 | #define S5P6440_EINT0CON0 (S5P_VA_GPIO + 0x900) | ||
| 31 | #define S5P6440_EINT0FLTCON0 (S5P_VA_GPIO + 0x910) | ||
| 32 | #define S5P6440_EINT0FLTCON1 (S5P_VA_GPIO + 0x914) | ||
| 33 | #define S5P6440_EINT0MASK (S5P_VA_GPIO + 0x920) | ||
| 34 | #define S5P6440_EINT0PEND (S5P_VA_GPIO + 0x924) | ||
| 35 | |||
| 36 | /* for LCD */ | ||
| 37 | #define S5P6440_SPCON_LCD_SEL_RGB (1 << 0) | ||
| 38 | #define S5P6440_SPCON_LCD_SEL_MASK (3 << 0) | ||
| 39 | |||
| 40 | /* These set of macros are not really useful for the | ||
| 41 | * GPF/GPI/GPJ/GPN/GPP, | ||
| 42 | * useful for others set of GPIO's (4 bit) | ||
| 43 | */ | ||
| 44 | #define S5P6440_GPIO_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | ||
| 45 | #define S5P6440_GPIO_INPUT(__gpio) (0x0 << ((__gpio) * 4)) | ||
| 46 | #define S5P6440_GPIO_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | ||
| 47 | |||
| 48 | /* Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit) | ||
| 49 | * */ | ||
| 50 | #define S5P6440_GPIO2_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
| 51 | #define S5P6440_GPIO2_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
| 52 | #define S5P6440_GPIO2_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
| 53 | |||
| 54 | #endif /* __ASM_ARCH_REGS_GPIO_H */ | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-irq.h b/arch/arm/mach-s5p6440/include/mach/regs-irq.h new file mode 100644 index 000000000000..a961f4beeb0c --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/regs-irq.h | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/include/mach/regs-irq.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P6440 - IRQ register definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_REGS_IRQ_H | ||
| 14 | #define __ASM_ARCH_REGS_IRQ_H __FILE__ | ||
| 15 | |||
| 16 | #include <asm/hardware/vic.h> | ||
| 17 | #include <mach/map.h> | ||
| 18 | |||
| 19 | #endif /* __ASM_ARCH_REGS_IRQ_H */ | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/system.h b/arch/arm/mach-s5p6440/include/mach/system.h new file mode 100644 index 000000000000..d2dd817da66a --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/system.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/include/mach/system.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P6440 - system support header | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 14 | #define __ASM_ARCH_SYSTEM_H __FILE__ | ||
| 15 | |||
| 16 | static void arch_idle(void) | ||
| 17 | { | ||
| 18 | /* nothing here yet */ | ||
| 19 | } | ||
| 20 | |||
| 21 | static void arch_reset(char mode, const char *cmd) | ||
| 22 | { | ||
| 23 | /* nothing here yet */ | ||
| 24 | } | ||
| 25 | |||
| 26 | #endif /* __ASM_ARCH_SYSTEM_H */ | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/tick.h b/arch/arm/mach-s5p6440/include/mach/tick.h new file mode 100644 index 000000000000..0815aeb4f2cf --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/tick.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/include/mach/tick.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P6440 - Timer tick support definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_TICK_H | ||
| 14 | #define __ASM_ARCH_TICK_H __FILE__ | ||
| 15 | |||
| 16 | static inline u32 s3c24xx_ostimer_pending(void) | ||
| 17 | { | ||
| 18 | u32 pend = __raw_readl(S5P_VA_VIC0 + VIC_RAW_STATUS); | ||
| 19 | return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0))); | ||
| 20 | } | ||
| 21 | |||
| 22 | #define TICK_MAX (0xffffffff) | ||
| 23 | |||
| 24 | #endif /* __ASM_ARCH_TICK_H */ | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/uncompress.h b/arch/arm/mach-s5p6440/include/mach/uncompress.h new file mode 100644 index 000000000000..7c1f600d65c0 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/uncompress.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/include/mach/uncompress.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P6440 - uncompress code | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
| 14 | #define __ASM_ARCH_UNCOMPRESS_H | ||
| 15 | |||
| 16 | #include <mach/map.h> | ||
| 17 | #include <plat/uncompress.h> | ||
| 18 | |||
| 19 | static void arch_detect_cpu(void) | ||
| 20 | { | ||
| 21 | /* we do not need to do any cpu detection here at the moment. */ | ||
| 22 | } | ||
| 23 | |||
| 24 | #endif /* __ASM_ARCH_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p6440/mach-smdk6440.c new file mode 100644 index 000000000000..760ea5424a78 --- /dev/null +++ b/arch/arm/mach-s5p6440/mach-smdk6440.c | |||
| @@ -0,0 +1,111 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/mach-smdk6440.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/types.h> | ||
| 13 | #include <linux/interrupt.h> | ||
| 14 | #include <linux/list.h> | ||
| 15 | #include <linux/timer.h> | ||
| 16 | #include <linux/delay.h> | ||
| 17 | #include <linux/init.h> | ||
| 18 | #include <linux/serial_core.h> | ||
| 19 | #include <linux/platform_device.h> | ||
| 20 | #include <linux/io.h> | ||
| 21 | #include <linux/module.h> | ||
| 22 | #include <linux/clk.h> | ||
| 23 | |||
| 24 | #include <asm/mach/arch.h> | ||
| 25 | #include <asm/mach/map.h> | ||
| 26 | |||
| 27 | #include <mach/hardware.h> | ||
| 28 | #include <mach/map.h> | ||
| 29 | |||
| 30 | #include <asm/irq.h> | ||
| 31 | #include <asm/mach-types.h> | ||
| 32 | |||
| 33 | #include <plat/regs-serial.h> | ||
| 34 | |||
| 35 | #include <plat/s5p6440.h> | ||
| 36 | #include <plat/clock.h> | ||
| 37 | #include <mach/regs-clock.h> | ||
| 38 | #include <plat/devs.h> | ||
| 39 | #include <plat/cpu.h> | ||
| 40 | #include <plat/pll.h> | ||
| 41 | |||
| 42 | #define S5P6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | ||
| 43 | S3C2410_UCON_RXILEVEL | \ | ||
| 44 | S3C2410_UCON_TXIRQMODE | \ | ||
| 45 | S3C2410_UCON_RXIRQMODE | \ | ||
| 46 | S3C2410_UCON_RXFIFO_TOI | \ | ||
| 47 | S3C2443_UCON_RXERR_IRQEN) | ||
| 48 | |||
| 49 | #define S5P6440_ULCON_DEFAULT S3C2410_LCON_CS8 | ||
| 50 | |||
| 51 | #define S5P6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | ||
| 52 | S3C2440_UFCON_TXTRIG16 | \ | ||
| 53 | S3C2410_UFCON_RXTRIG8) | ||
| 54 | |||
| 55 | static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = { | ||
| 56 | [0] = { | ||
| 57 | .hwport = 0, | ||
| 58 | .flags = 0, | ||
| 59 | .ucon = S5P6440_UCON_DEFAULT, | ||
| 60 | .ulcon = S5P6440_ULCON_DEFAULT, | ||
| 61 | .ufcon = S5P6440_UFCON_DEFAULT, | ||
| 62 | }, | ||
| 63 | [1] = { | ||
| 64 | .hwport = 1, | ||
| 65 | .flags = 0, | ||
| 66 | .ucon = S5P6440_UCON_DEFAULT, | ||
| 67 | .ulcon = S5P6440_ULCON_DEFAULT, | ||
| 68 | .ufcon = S5P6440_UFCON_DEFAULT, | ||
| 69 | }, | ||
| 70 | [2] = { | ||
| 71 | .hwport = 2, | ||
| 72 | .flags = 0, | ||
| 73 | .ucon = S5P6440_UCON_DEFAULT, | ||
| 74 | .ulcon = S5P6440_ULCON_DEFAULT, | ||
| 75 | .ufcon = S5P6440_UFCON_DEFAULT, | ||
| 76 | }, | ||
| 77 | [3] = { | ||
| 78 | .hwport = 3, | ||
| 79 | .flags = 0, | ||
| 80 | .ucon = S5P6440_UCON_DEFAULT, | ||
| 81 | .ulcon = S5P6440_ULCON_DEFAULT, | ||
| 82 | .ufcon = S5P6440_UFCON_DEFAULT, | ||
| 83 | }, | ||
| 84 | }; | ||
| 85 | |||
| 86 | static struct platform_device *smdk6440_devices[] __initdata = { | ||
| 87 | }; | ||
| 88 | |||
| 89 | static void __init smdk6440_map_io(void) | ||
| 90 | { | ||
| 91 | s5p_init_io(NULL, 0, S5P_SYS_ID); | ||
| 92 | s3c24xx_init_clocks(12000000); | ||
| 93 | s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs)); | ||
| 94 | } | ||
| 95 | |||
| 96 | static void __init smdk6440_machine_init(void) | ||
| 97 | { | ||
| 98 | platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); | ||
| 99 | } | ||
| 100 | |||
| 101 | MACHINE_START(SMDK6440, "SMDK6440") | ||
| 102 | /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ | ||
| 103 | .phys_io = S5P_PA_UART & 0xfff00000, | ||
| 104 | .io_pg_offst = (((u32)S5P_VA_UART) >> 18) & 0xfffc, | ||
| 105 | .boot_params = S5P_PA_SDRAM + 0x100, | ||
| 106 | |||
| 107 | .init_irq = s5p6440_init_irq, | ||
| 108 | .map_io = smdk6440_map_io, | ||
| 109 | .init_machine = smdk6440_machine_init, | ||
| 110 | .timer = &s3c24xx_timer, | ||
| 111 | MACHINE_END | ||
diff --git a/arch/arm/mach-s5p6440/s5p6440-gpio.c b/arch/arm/mach-s5p6440/s5p6440-gpio.c new file mode 100644 index 000000000000..742264c29f2a --- /dev/null +++ b/arch/arm/mach-s5p6440/s5p6440-gpio.c | |||
| @@ -0,0 +1,322 @@ | |||
| 1 | /* arch/arm/mach-s5p6440/s5p6440-gpio.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P6440 - GPIOlib support | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/irq.h> | ||
| 15 | #include <linux/io.h> | ||
| 16 | #include <mach/map.h> | ||
| 17 | #include <mach/gpio.h> | ||
| 18 | #include <mach/regs-gpio.h> | ||
| 19 | #include <plat/gpio-core.h> | ||
| 20 | #include <plat/gpio-cfg.h> | ||
| 21 | #include <plat/gpio-cfg-helpers.h> | ||
| 22 | |||
| 23 | /* GPIO bank summary: | ||
| 24 | * | ||
| 25 | * Bank GPIOs Style SlpCon ExtInt Group | ||
| 26 | * A 6 4Bit Yes 1 | ||
| 27 | * B 7 4Bit Yes 1 | ||
| 28 | * C 8 4Bit Yes 2 | ||
| 29 | * F 2 2Bit Yes 4 [1] | ||
| 30 | * G 7 4Bit Yes 5 | ||
| 31 | * H 10 4Bit[2] Yes 6 | ||
| 32 | * I 16 2Bit Yes None | ||
| 33 | * J 12 2Bit Yes None | ||
| 34 | * N 16 2Bit No IRQ_EINT | ||
| 35 | * P 8 2Bit Yes 8 | ||
| 36 | * R 15 4Bit[2] Yes 8 | ||
| 37 | * | ||
| 38 | * [1] BANKF pins 14,15 do not form part of the external interrupt sources | ||
| 39 | * [2] BANK has two control registers, GPxCON0 and GPxCON1 | ||
| 40 | */ | ||
| 41 | |||
| 42 | static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip, | ||
| 43 | unsigned int offset) | ||
| 44 | { | ||
| 45 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
| 46 | void __iomem *base = ourchip->base; | ||
| 47 | void __iomem *regcon = base; | ||
| 48 | unsigned long con; | ||
| 49 | |||
| 50 | switch (offset) { | ||
| 51 | case 6: | ||
| 52 | offset += 1; | ||
| 53 | case 0: | ||
| 54 | case 1: | ||
| 55 | case 2: | ||
| 56 | case 3: | ||
| 57 | case 4: | ||
| 58 | case 5: | ||
| 59 | regcon -= 4; | ||
| 60 | break; | ||
| 61 | default: | ||
| 62 | offset -= 7; | ||
| 63 | break; | ||
| 64 | } | ||
| 65 | |||
| 66 | con = __raw_readl(regcon); | ||
| 67 | con &= ~(0xf << con_4bit_shift(offset)); | ||
| 68 | __raw_writel(con, regcon); | ||
| 69 | |||
| 70 | return 0; | ||
| 71 | } | ||
| 72 | |||
| 73 | static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip, | ||
| 74 | unsigned int offset, int value) | ||
| 75 | { | ||
| 76 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
| 77 | void __iomem *base = ourchip->base; | ||
| 78 | void __iomem *regcon = base; | ||
| 79 | unsigned long con; | ||
| 80 | unsigned long dat; | ||
| 81 | unsigned con_offset = offset; | ||
| 82 | |||
| 83 | switch (con_offset) { | ||
| 84 | case 6: | ||
| 85 | con_offset += 1; | ||
| 86 | case 0: | ||
| 87 | case 1: | ||
| 88 | case 2: | ||
| 89 | case 3: | ||
| 90 | case 4: | ||
| 91 | case 5: | ||
| 92 | regcon -= 4; | ||
| 93 | break; | ||
| 94 | default: | ||
| 95 | con_offset -= 7; | ||
| 96 | break; | ||
| 97 | } | ||
| 98 | |||
| 99 | con = __raw_readl(regcon); | ||
| 100 | con &= ~(0xf << con_4bit_shift(con_offset)); | ||
| 101 | con |= 0x1 << con_4bit_shift(con_offset); | ||
| 102 | |||
| 103 | dat = __raw_readl(base + GPIODAT_OFF); | ||
| 104 | if (value) | ||
| 105 | dat |= 1 << offset; | ||
| 106 | else | ||
| 107 | dat &= ~(1 << offset); | ||
| 108 | |||
| 109 | __raw_writel(con, regcon); | ||
| 110 | __raw_writel(dat, base + GPIODAT_OFF); | ||
| 111 | |||
| 112 | return 0; | ||
| 113 | } | ||
| 114 | |||
| 115 | int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip, | ||
| 116 | unsigned int off, unsigned int cfg) | ||
| 117 | { | ||
| 118 | void __iomem *reg = chip->base; | ||
| 119 | unsigned int shift; | ||
| 120 | u32 con; | ||
| 121 | |||
| 122 | switch (off) { | ||
| 123 | case 0: | ||
| 124 | case 1: | ||
| 125 | case 2: | ||
| 126 | case 3: | ||
| 127 | case 4: | ||
| 128 | case 5: | ||
| 129 | shift = (off & 7) * 4; | ||
| 130 | reg -= 4; | ||
| 131 | break; | ||
| 132 | case 6: | ||
| 133 | shift = ((off + 1) & 7) * 4; | ||
| 134 | reg -= 4; | ||
| 135 | default: | ||
| 136 | shift = ((off + 1) & 7) * 4; | ||
| 137 | break; | ||
| 138 | } | ||
| 139 | |||
| 140 | if (s3c_gpio_is_cfg_special(cfg)) { | ||
| 141 | cfg &= 0xf; | ||
| 142 | cfg <<= shift; | ||
| 143 | } | ||
| 144 | |||
| 145 | con = __raw_readl(reg); | ||
| 146 | con &= ~(0xf << shift); | ||
| 147 | con |= cfg; | ||
| 148 | __raw_writel(con, reg); | ||
| 149 | |||
| 150 | return 0; | ||
| 151 | } | ||
| 152 | |||
| 153 | static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = { | ||
| 154 | { | ||
| 155 | .cfg_eint = 0, | ||
| 156 | }, { | ||
| 157 | .cfg_eint = 7, | ||
| 158 | }, { | ||
| 159 | .cfg_eint = 3, | ||
| 160 | .set_config = s5p6440_gpio_setcfg_4bit_rbank, | ||
| 161 | }, { | ||
| 162 | .cfg_eint = 0, | ||
| 163 | .set_config = s3c_gpio_setcfg_s3c24xx, | ||
| 164 | }, { | ||
| 165 | .cfg_eint = 2, | ||
| 166 | .set_config = s3c_gpio_setcfg_s3c24xx, | ||
| 167 | }, { | ||
| 168 | .cfg_eint = 3, | ||
| 169 | .set_config = s3c_gpio_setcfg_s3c24xx, | ||
| 170 | }, | ||
| 171 | }; | ||
| 172 | |||
| 173 | static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { | ||
| 174 | { | ||
| 175 | .base = S5P6440_GPA_BASE, | ||
| 176 | .config = &s5p6440_gpio_cfgs[1], | ||
| 177 | .chip = { | ||
| 178 | .base = S5P6440_GPA(0), | ||
| 179 | .ngpio = S5P6440_GPIO_A_NR, | ||
| 180 | .label = "GPA", | ||
| 181 | }, | ||
| 182 | }, { | ||
| 183 | .base = S5P6440_GPB_BASE, | ||
| 184 | .config = &s5p6440_gpio_cfgs[1], | ||
| 185 | .chip = { | ||
| 186 | .base = S5P6440_GPB(0), | ||
| 187 | .ngpio = S5P6440_GPIO_B_NR, | ||
| 188 | .label = "GPB", | ||
| 189 | }, | ||
| 190 | }, { | ||
| 191 | .base = S5P6440_GPC_BASE, | ||
| 192 | .config = &s5p6440_gpio_cfgs[1], | ||
| 193 | .chip = { | ||
| 194 | .base = S5P6440_GPC(0), | ||
| 195 | .ngpio = S5P6440_GPIO_C_NR, | ||
| 196 | .label = "GPC", | ||
| 197 | }, | ||
| 198 | }, { | ||
| 199 | .base = S5P6440_GPG_BASE, | ||
| 200 | .config = &s5p6440_gpio_cfgs[1], | ||
| 201 | .chip = { | ||
| 202 | .base = S5P6440_GPG(0), | ||
| 203 | .ngpio = S5P6440_GPIO_G_NR, | ||
| 204 | .label = "GPG", | ||
| 205 | }, | ||
| 206 | }, | ||
| 207 | }; | ||
| 208 | |||
| 209 | static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = { | ||
| 210 | { | ||
| 211 | .base = S5P6440_GPH_BASE + 0x4, | ||
| 212 | .config = &s5p6440_gpio_cfgs[1], | ||
| 213 | .chip = { | ||
| 214 | .base = S5P6440_GPH(0), | ||
| 215 | .ngpio = S5P6440_GPIO_H_NR, | ||
| 216 | .label = "GPH", | ||
| 217 | }, | ||
| 218 | }, | ||
| 219 | }; | ||
| 220 | |||
| 221 | static struct s3c_gpio_chip gpio_rbank_4bit2[] = { | ||
| 222 | { | ||
| 223 | .base = S5P6440_GPR_BASE + 0x4, | ||
| 224 | .config = &s5p6440_gpio_cfgs[2], | ||
| 225 | .chip = { | ||
| 226 | .base = S5P6440_GPR(0), | ||
| 227 | .ngpio = S5P6440_GPIO_R_NR, | ||
| 228 | .label = "GPR", | ||
| 229 | }, | ||
| 230 | }, | ||
| 231 | }; | ||
| 232 | |||
| 233 | static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { | ||
| 234 | { | ||
| 235 | .base = S5P6440_GPF_BASE, | ||
| 236 | .config = &s5p6440_gpio_cfgs[5], | ||
| 237 | .chip = { | ||
| 238 | .base = S5P6440_GPF(0), | ||
| 239 | .ngpio = S5P6440_GPIO_F_NR, | ||
| 240 | .label = "GPF", | ||
| 241 | }, | ||
| 242 | }, { | ||
| 243 | .base = S5P6440_GPI_BASE, | ||
| 244 | .config = &s5p6440_gpio_cfgs[3], | ||
| 245 | .chip = { | ||
| 246 | .base = S5P6440_GPI(0), | ||
| 247 | .ngpio = S5P6440_GPIO_I_NR, | ||
| 248 | .label = "GPI", | ||
| 249 | }, | ||
| 250 | }, { | ||
| 251 | .base = S5P6440_GPJ_BASE, | ||
| 252 | .config = &s5p6440_gpio_cfgs[3], | ||
| 253 | .chip = { | ||
| 254 | .base = S5P6440_GPJ(0), | ||
| 255 | .ngpio = S5P6440_GPIO_J_NR, | ||
| 256 | .label = "GPJ", | ||
| 257 | }, | ||
| 258 | }, { | ||
| 259 | .base = S5P6440_GPN_BASE, | ||
| 260 | .config = &s5p6440_gpio_cfgs[4], | ||
| 261 | .chip = { | ||
| 262 | .base = S5P6440_GPN(0), | ||
| 263 | .ngpio = S5P6440_GPIO_N_NR, | ||
| 264 | .label = "GPN", | ||
| 265 | }, | ||
| 266 | }, { | ||
| 267 | .base = S5P6440_GPP_BASE, | ||
| 268 | .config = &s5p6440_gpio_cfgs[5], | ||
| 269 | .chip = { | ||
| 270 | .base = S5P6440_GPP(0), | ||
| 271 | .ngpio = S5P6440_GPIO_P_NR, | ||
| 272 | .label = "GPP", | ||
| 273 | }, | ||
| 274 | }, | ||
| 275 | }; | ||
| 276 | |||
| 277 | void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips) | ||
| 278 | { | ||
| 279 | for (; nr_chips > 0; nr_chips--, chipcfg++) { | ||
| 280 | if (!chipcfg->set_config) | ||
| 281 | chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit; | ||
| 282 | if (!chipcfg->set_pull) | ||
| 283 | chipcfg->set_pull = s3c_gpio_setpull_updown; | ||
| 284 | if (!chipcfg->get_pull) | ||
| 285 | chipcfg->get_pull = s3c_gpio_getpull_updown; | ||
| 286 | } | ||
| 287 | } | ||
| 288 | |||
| 289 | static void __init s5p6440_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip, | ||
| 290 | int nr_chips) | ||
| 291 | { | ||
| 292 | for (; nr_chips > 0; nr_chips--, chip++) { | ||
| 293 | chip->chip.direction_input = s5p6440_gpiolib_rbank_4bit2_input; | ||
| 294 | chip->chip.direction_output = | ||
| 295 | s5p6440_gpiolib_rbank_4bit2_output; | ||
| 296 | s3c_gpiolib_add(chip); | ||
| 297 | } | ||
| 298 | } | ||
| 299 | |||
| 300 | static int __init s5p6440_gpiolib_init(void) | ||
| 301 | { | ||
| 302 | struct s3c_gpio_chip *chips = s5p6440_gpio_2bit; | ||
| 303 | int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit); | ||
| 304 | |||
| 305 | s5p6440_gpiolib_set_cfg(s5p6440_gpio_cfgs, | ||
| 306 | ARRAY_SIZE(s5p6440_gpio_cfgs)); | ||
| 307 | |||
| 308 | for (; nr_chips > 0; nr_chips--, chips++) | ||
| 309 | s3c_gpiolib_add(chips); | ||
| 310 | |||
| 311 | samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit, | ||
| 312 | ARRAY_SIZE(s5p6440_gpio_4bit)); | ||
| 313 | |||
| 314 | samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2, | ||
| 315 | ARRAY_SIZE(s5p6440_gpio_4bit2)); | ||
| 316 | |||
| 317 | s5p6440_gpio_add_rbank_4bit2(gpio_rbank_4bit2, | ||
| 318 | ARRAY_SIZE(gpio_rbank_4bit2)); | ||
| 319 | |||
| 320 | return 0; | ||
| 321 | } | ||
| 322 | arch_initcall(s5p6440_gpiolib_init); | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio-core.h b/arch/arm/mach-s5pc100/include/mach/gpio-core.h deleted file mode 100644 index ad28d8ec8a78..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/gpio-core.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* arch/arm/mach-s5pc100/include/mach/gpio-core.h | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co. | ||
| 4 | * Byungho Min <bhmin@samsung.com> | ||
| 5 | * | ||
| 6 | * S5PC100 - GPIO core support | ||
| 7 | * | ||
| 8 | * Based on mach-s3c6400/include/mach/gpio-core.h | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_GPIO_CORE_H | ||
| 16 | #define __ASM_ARCH_GPIO_CORE_H __FILE__ | ||
| 17 | |||
| 18 | /* currently we just include the platform support */ | ||
| 19 | #include <plat/gpio-core.h> | ||
| 20 | |||
| 21 | #endif /* __ASM_ARCH_GPIO_CORE_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h index d3de0f3591ae..f338c9eec717 100644 --- a/arch/arm/mach-s5pc100/include/mach/tick.h +++ b/arch/arm/mach-s5pc100/include/mach/tick.h | |||
| @@ -21,7 +21,7 @@ | |||
| 21 | static inline u32 s3c24xx_ostimer_pending(void) | 21 | static inline u32 s3c24xx_ostimer_pending(void) |
| 22 | { | 22 | { |
| 23 | u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); | 23 | u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); |
| 24 | return pend & 1 << (IRQ_TIMER4 - S5PC1XX_IRQ_VIC0(0)); | 24 | return pend & 1 << (IRQ_TIMER4_VIC - S5PC1XX_IRQ_VIC0(0)); |
| 25 | } | 25 | } |
| 26 | 26 | ||
| 27 | #define TICK_MAX (0xffffffff) | 27 | #define TICK_MAX (0xffffffff) |
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig index 9e9d0286e48f..2367908c4f62 100644 --- a/arch/arm/plat-s3c/Kconfig +++ b/arch/arm/plat-s3c/Kconfig | |||
| @@ -59,50 +59,6 @@ config S3C_BOOT_UART_FORCE_FIFO | |||
| 59 | Say Y here to force the UART FIFOs on during the kernel | 59 | Say Y here to force the UART FIFOs on during the kernel |
| 60 | uncompressor | 60 | uncompressor |
| 61 | 61 | ||
| 62 | comment "Power management" | ||
| 63 | |||
| 64 | config S3C2410_PM_DEBUG | ||
| 65 | bool "S3C2410 PM Suspend debug" | ||
| 66 | depends on PM | ||
| 67 | help | ||
| 68 | Say Y here if you want verbose debugging from the PM Suspend and | ||
| 69 | Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> | ||
| 70 | for more information. | ||
| 71 | |||
| 72 | config S3C_PM_DEBUG_LED_SMDK | ||
| 73 | bool "SMDK LED suspend/resume debugging" | ||
| 74 | depends on PM && (MACH_SMDK6410) | ||
| 75 | help | ||
| 76 | Say Y here to enable the use of the SMDK LEDs on the baseboard | ||
| 77 | for debugging of the state of the suspend and resume process. | ||
| 78 | |||
| 79 | Note, this currently only works for S3C64XX based SMDK boards. | ||
| 80 | |||
| 81 | config S3C2410_PM_CHECK | ||
| 82 | bool "S3C2410 PM Suspend Memory CRC" | ||
| 83 | depends on PM && CRC32 | ||
| 84 | help | ||
| 85 | Enable the PM code's memory area checksum over sleep. This option | ||
| 86 | will generate CRCs of all blocks of memory, and store them before | ||
| 87 | going to sleep. The blocks are then checked on resume for any | ||
| 88 | errors. | ||
| 89 | |||
| 90 | Note, this can take several seconds depending on memory size | ||
| 91 | and CPU speed. | ||
| 92 | |||
| 93 | See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> | ||
| 94 | |||
| 95 | config S3C2410_PM_CHECK_CHUNKSIZE | ||
| 96 | int "S3C2410 PM Suspend CRC Chunksize (KiB)" | ||
| 97 | depends on PM && S3C2410_PM_CHECK | ||
| 98 | default 64 | ||
| 99 | help | ||
| 100 | Set the chunksize in Kilobytes of the CRC for checking memory | ||
| 101 | corruption over suspend and resume. A smaller value will mean that | ||
| 102 | the CRC data block will take more memory, but wil identify any | ||
| 103 | faults with better precision. | ||
| 104 | |||
| 105 | See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> | ||
| 106 | 62 | ||
| 107 | config S3C_LOWLEVEL_UART_PORT | 63 | config S3C_LOWLEVEL_UART_PORT |
| 108 | int "S3C UART to use for low-level messages" | 64 | int "S3C UART to use for low-level messages" |
| @@ -130,39 +86,6 @@ config S3C_GPIO_TRACK | |||
| 130 | Internal configuration option to enable the s3c specific gpio | 86 | Internal configuration option to enable the s3c specific gpio |
| 131 | chip tracking if the platform requires it. | 87 | chip tracking if the platform requires it. |
| 132 | 88 | ||
| 133 | config S3C_GPIO_PULL_UPDOWN | ||
| 134 | bool | ||
| 135 | help | ||
| 136 | Internal configuration to enable the correct GPIO pull helper | ||
| 137 | |||
| 138 | config S3C_GPIO_PULL_DOWN | ||
| 139 | bool | ||
| 140 | help | ||
| 141 | Internal configuration to enable the correct GPIO pull helper | ||
| 142 | |||
| 143 | config S3C_GPIO_PULL_UP | ||
| 144 | bool | ||
| 145 | help | ||
| 146 | Internal configuration to enable the correct GPIO pull helper | ||
| 147 | |||
| 148 | config S3C_GPIO_CFG_S3C24XX | ||
| 149 | bool | ||
| 150 | help | ||
| 151 | Internal configuration to enable S3C24XX style GPIO configuration | ||
| 152 | functions. | ||
| 153 | |||
| 154 | config S3C_GPIO_CFG_S3C64XX | ||
| 155 | bool | ||
| 156 | help | ||
| 157 | Internal configuration to enable S3C64XX style GPIO configuration | ||
| 158 | functions. | ||
| 159 | |||
| 160 | config S5P_GPIO_CFG_S5PC1XX | ||
| 161 | bool | ||
| 162 | help | ||
| 163 | Internal configuration to enable S5PC1XX style GPIO configuration | ||
| 164 | functions. | ||
| 165 | |||
| 166 | # DMA | 89 | # DMA |
| 167 | 90 | ||
| 168 | config S3C_DMA | 91 | config S3C_DMA |
| @@ -170,46 +93,4 @@ config S3C_DMA | |||
| 170 | help | 93 | help |
| 171 | Internal configuration for S3C DMA core | 94 | Internal configuration for S3C DMA core |
| 172 | 95 | ||
| 173 | # device definitions to compile in | ||
| 174 | |||
| 175 | config S3C_DEV_HSMMC | ||
| 176 | bool | ||
| 177 | help | ||
| 178 | Compile in platform device definitions for HSMMC code | ||
| 179 | |||
| 180 | config S3C_DEV_HSMMC1 | ||
| 181 | bool | ||
| 182 | help | ||
| 183 | Compile in platform device definitions for HSMMC channel 1 | ||
| 184 | |||
| 185 | config S3C_DEV_HSMMC2 | ||
| 186 | bool | ||
| 187 | help | ||
| 188 | Compile in platform device definitions for HSMMC channel 2 | ||
| 189 | |||
| 190 | config S3C_DEV_I2C1 | ||
| 191 | bool | ||
| 192 | help | ||
| 193 | Compile in platform device definitions for I2C channel 1 | ||
| 194 | |||
| 195 | config S3C_DEV_FB | ||
| 196 | bool | ||
| 197 | help | ||
| 198 | Compile in platform device definition for framebuffer | ||
| 199 | |||
| 200 | config S3C_DEV_USB_HOST | ||
| 201 | bool | ||
| 202 | help | ||
| 203 | Compile in platform device definition for USB host. | ||
| 204 | |||
| 205 | config S3C_DEV_USB_HSOTG | ||
| 206 | bool | ||
| 207 | help | ||
| 208 | Compile in platform device definition for USB high-speed OtG | ||
| 209 | |||
| 210 | config S3C_DEV_NAND | ||
| 211 | bool | ||
| 212 | help | ||
| 213 | Compile in platform device definition for NAND controller | ||
| 214 | |||
| 215 | endif | 96 | endif |
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 50444da98425..89dbdb0adebf 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile | |||
| @@ -11,12 +11,8 @@ obj- := | |||
| 11 | 11 | ||
| 12 | # Core support for all Samsung SoCs | 12 | # Core support for all Samsung SoCs |
| 13 | 13 | ||
| 14 | obj-y += init.o | 14 | obj-y += init.o |
| 15 | obj-y += time.o | 15 | obj-y += time.o |
| 16 | obj-y += clock.o | ||
| 17 | obj-y += pwm-clock.o | ||
| 18 | obj-y += gpio.o | ||
| 19 | obj-y += gpio-config.o | ||
| 20 | 16 | ||
| 21 | # DMA support | 17 | # DMA support |
| 22 | 18 | ||
| @@ -25,21 +21,3 @@ obj-$(CONFIG_S3C_DMA) += dma.o | |||
| 25 | # PM support | 21 | # PM support |
| 26 | 22 | ||
| 27 | obj-$(CONFIG_PM) += pm.o | 23 | obj-$(CONFIG_PM) += pm.o |
| 28 | obj-$(CONFIG_PM) += pm-gpio.o | ||
| 29 | obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o | ||
| 30 | |||
| 31 | # PWM support | ||
| 32 | |||
| 33 | obj-$(CONFIG_HAVE_PWM) += pwm.o | ||
| 34 | |||
| 35 | # devices | ||
| 36 | |||
| 37 | obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o | ||
| 38 | obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o | ||
| 39 | obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o | ||
| 40 | obj-y += dev-i2c0.o | ||
| 41 | obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o | ||
| 42 | obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o | ||
| 43 | obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o | ||
| 44 | obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o | ||
| 45 | obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o | ||
diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h index d1131ca11e97..676db9465674 100644 --- a/arch/arm/plat-s3c/include/plat/cpu.h +++ b/arch/arm/plat-s3c/include/plat/cpu.h | |||
| @@ -48,9 +48,12 @@ extern void s3c_init_cpu(unsigned long idcode, | |||
| 48 | 48 | ||
| 49 | extern void s3c24xx_init_irq(void); | 49 | extern void s3c24xx_init_irq(void); |
| 50 | extern void s3c64xx_init_irq(u32 vic0, u32 vic1); | 50 | extern void s3c64xx_init_irq(u32 vic0, u32 vic1); |
| 51 | extern void s5p_init_irq(u32 *vic, u32 num_vic); | ||
| 51 | 52 | ||
| 52 | extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); | 53 | extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); |
| 53 | extern void s3c64xx_init_io(struct map_desc *mach_desc, int size); | 54 | extern void s3c64xx_init_io(struct map_desc *mach_desc, int size); |
| 55 | extern void s5p_init_io(struct map_desc *mach_desc, | ||
| 56 | int size, void __iomem *cpuid_addr); | ||
| 54 | 57 | ||
| 55 | extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); | 58 | extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); |
| 56 | 59 | ||
diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index c1c20b023917..c6f9b7310490 100644 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h | |||
| @@ -18,6 +18,7 @@ struct s3c24xx_uart_resources { | |||
| 18 | 18 | ||
| 19 | extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; | 19 | extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; |
| 20 | extern struct s3c24xx_uart_resources s3c64xx_uart_resources[]; | 20 | extern struct s3c24xx_uart_resources s3c64xx_uart_resources[]; |
| 21 | extern struct s3c24xx_uart_resources s5p_uart_resources[]; | ||
| 21 | 22 | ||
| 22 | extern struct platform_device *s3c24xx_uart_devs[]; | 23 | extern struct platform_device *s3c24xx_uart_devs[]; |
| 23 | extern struct platform_device *s3c24xx_uart_src[]; | 24 | extern struct platform_device *s3c24xx_uart_src[]; |
| @@ -28,12 +29,15 @@ extern struct platform_device s3c64xx_device_iis0; | |||
| 28 | extern struct platform_device s3c64xx_device_iis1; | 29 | extern struct platform_device s3c64xx_device_iis1; |
| 29 | extern struct platform_device s3c64xx_device_iisv4; | 30 | extern struct platform_device s3c64xx_device_iisv4; |
| 30 | 31 | ||
| 32 | extern struct platform_device s3c64xx_device_spi0; | ||
| 33 | extern struct platform_device s3c64xx_device_spi1; | ||
| 34 | |||
| 31 | extern struct platform_device s3c64xx_device_pcm0; | 35 | extern struct platform_device s3c64xx_device_pcm0; |
| 32 | extern struct platform_device s3c64xx_device_pcm1; | 36 | extern struct platform_device s3c64xx_device_pcm1; |
| 33 | 37 | ||
| 34 | extern struct platform_device s3c_device_ts; | 38 | extern struct platform_device s3c_device_ts; |
| 35 | extern struct platform_device s3c_device_fb; | 39 | extern struct platform_device s3c_device_fb; |
| 36 | extern struct platform_device s3c_device_usb; | 40 | extern struct platform_device s3c_device_ohci; |
| 37 | extern struct platform_device s3c_device_lcd; | 41 | extern struct platform_device s3c_device_lcd; |
| 38 | extern struct platform_device s3c_device_wdt; | 42 | extern struct platform_device s3c_device_wdt; |
| 39 | extern struct platform_device s3c_device_i2c0; | 43 | extern struct platform_device s3c_device_i2c0; |
diff --git a/arch/arm/plat-s3c/include/plat/pm.h b/arch/arm/plat-s3c/include/plat/pm.h index 7a797192fcf3..2543bd227f2d 100644 --- a/arch/arm/plat-s3c/include/plat/pm.h +++ b/arch/arm/plat-s3c/include/plat/pm.h | |||
| @@ -111,7 +111,7 @@ extern int s3c24xx_irq_resume(struct sys_device *dev); | |||
| 111 | 111 | ||
| 112 | /* PM debug functions */ | 112 | /* PM debug functions */ |
| 113 | 113 | ||
| 114 | #ifdef CONFIG_S3C2410_PM_DEBUG | 114 | #ifdef CONFIG_SAMSUNG_PM_DEBUG |
| 115 | /** | 115 | /** |
| 116 | * s3c_pm_dbg() - low level debug function for use in suspend/resume. | 116 | * s3c_pm_dbg() - low level debug function for use in suspend/resume. |
| 117 | * @msg: The message to print. | 117 | * @msg: The message to print. |
| @@ -141,7 +141,7 @@ static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { } | |||
| 141 | 141 | ||
| 142 | /* suspend memory checking */ | 142 | /* suspend memory checking */ |
| 143 | 143 | ||
| 144 | #ifdef CONFIG_S3C2410_PM_CHECK | 144 | #ifdef CONFIG_SAMSUNG_PM_CHECK |
| 145 | extern void s3c_pm_check_prepare(void); | 145 | extern void s3c_pm_check_prepare(void); |
| 146 | extern void s3c_pm_check_restore(void); | 146 | extern void s3c_pm_check_restore(void); |
| 147 | extern void s3c_pm_check_cleanup(void); | 147 | extern void s3c_pm_check_cleanup(void); |
diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h index 85d8904e7f24..60d6604185ea 100644 --- a/arch/arm/plat-s3c/include/plat/regs-serial.h +++ b/arch/arm/plat-s3c/include/plat/regs-serial.h | |||
| @@ -194,6 +194,36 @@ | |||
| 194 | #define S3C64XX_UINTSP 0x34 | 194 | #define S3C64XX_UINTSP 0x34 |
| 195 | #define S3C64XX_UINTM 0x38 | 195 | #define S3C64XX_UINTM 0x38 |
| 196 | 196 | ||
| 197 | /* Following are specific to S5PV210 and S5P6442 */ | ||
| 198 | #define S5PV210_UCON_CLKMASK (1<<10) | ||
| 199 | #define S5PV210_UCON_PCLK (0<<10) | ||
| 200 | #define S5PV210_UCON_UCLK (1<<10) | ||
| 201 | |||
| 202 | #define S5PV210_UFCON_TXTRIG0 (0<<8) | ||
| 203 | #define S5PV210_UFCON_TXTRIG4 (1<<8) | ||
| 204 | #define S5PV210_UFCON_TXTRIG8 (2<<8) | ||
| 205 | #define S5PV210_UFCON_TXTRIG16 (3<<8) | ||
| 206 | #define S5PV210_UFCON_TXTRIG32 (4<<8) | ||
| 207 | #define S5PV210_UFCON_TXTRIG64 (5<<8) | ||
| 208 | #define S5PV210_UFCON_TXTRIG128 (6<<8) | ||
| 209 | #define S5PV210_UFCON_TXTRIG256 (7<<8) | ||
| 210 | |||
| 211 | #define S5PV210_UFCON_RXTRIG1 (0<<4) | ||
| 212 | #define S5PV210_UFCON_RXTRIG4 (1<<4) | ||
| 213 | #define S5PV210_UFCON_RXTRIG8 (2<<4) | ||
| 214 | #define S5PV210_UFCON_RXTRIG16 (3<<4) | ||
| 215 | #define S5PV210_UFCON_RXTRIG32 (4<<4) | ||
| 216 | #define S5PV210_UFCON_RXTRIG64 (5<<4) | ||
| 217 | #define S5PV210_UFCON_RXTRIG128 (6<<4) | ||
| 218 | #define S5PV210_UFCON_RXTRIG256 (7<<4) | ||
| 219 | |||
| 220 | #define S5PV210_UFSTAT_TXFULL (1<<24) | ||
| 221 | #define S5PV210_UFSTAT_RXFULL (1<<8) | ||
| 222 | #define S5PV210_UFSTAT_TXMASK (255<<16) | ||
| 223 | #define S5PV210_UFSTAT_TXSHIFT (16) | ||
| 224 | #define S5PV210_UFSTAT_RXMASK (255<<0) | ||
| 225 | #define S5PV210_UFSTAT_RXSHIFT (0) | ||
| 226 | |||
| 197 | #ifndef __ASSEMBLY__ | 227 | #ifndef __ASSEMBLY__ |
| 198 | 228 | ||
| 199 | /* struct s3c24xx_uart_clksrc | 229 | /* struct s3c24xx_uart_clksrc |
diff --git a/arch/arm/plat-s3c/include/plat/usb-control.h b/arch/arm/plat-s3c/include/plat/usb-control.h index 822c87fe948e..a6a57bf796bd 100644 --- a/arch/arm/plat-s3c/include/plat/usb-control.h +++ b/arch/arm/plat-s3c/include/plat/usb-control.h | |||
| @@ -38,4 +38,6 @@ static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int port | |||
| 38 | } | 38 | } |
| 39 | } | 39 | } |
| 40 | 40 | ||
| 41 | extern void s3c_ohci_set_platdata(struct s3c2410_hcd_info *info); | ||
| 42 | |||
| 41 | #endif /*__ASM_ARCH_USBCONTROL_H */ | 43 | #endif /*__ASM_ARCH_USBCONTROL_H */ |
diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c index 767470601e5c..e5eef126791b 100644 --- a/arch/arm/plat-s3c/pm.c +++ b/arch/arm/plat-s3c/pm.c | |||
| @@ -41,7 +41,7 @@ unsigned long s3c_pm_flags; | |||
| 41 | * resume before the console layer is available. | 41 | * resume before the console layer is available. |
| 42 | */ | 42 | */ |
| 43 | 43 | ||
| 44 | #ifdef CONFIG_S3C2410_PM_DEBUG | 44 | #ifdef CONFIG_SAMSUNG_PM_DEBUG |
| 45 | extern void printascii(const char *); | 45 | extern void printascii(const char *); |
| 46 | 46 | ||
| 47 | void s3c_pm_dbg(const char *fmt, ...) | 47 | void s3c_pm_dbg(const char *fmt, ...) |
| @@ -65,13 +65,13 @@ static inline void s3c_pm_debug_init(void) | |||
| 65 | #else | 65 | #else |
| 66 | #define s3c_pm_debug_init() do { } while(0) | 66 | #define s3c_pm_debug_init() do { } while(0) |
| 67 | 67 | ||
| 68 | #endif /* CONFIG_S3C2410_PM_DEBUG */ | 68 | #endif /* CONFIG_SAMSUNG_PM_DEBUG */ |
| 69 | 69 | ||
| 70 | /* Save the UART configurations if we are configured for debug. */ | 70 | /* Save the UART configurations if we are configured for debug. */ |
| 71 | 71 | ||
| 72 | unsigned char pm_uart_udivslot; | 72 | unsigned char pm_uart_udivslot; |
| 73 | 73 | ||
| 74 | #ifdef CONFIG_S3C2410_PM_DEBUG | 74 | #ifdef CONFIG_SAMSUNG_PM_DEBUG |
| 75 | 75 | ||
| 76 | struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; | 76 | struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; |
| 77 | 77 | ||
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index 342647eb91d8..a806f359ceb6 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig | |||
| @@ -117,13 +117,6 @@ config S3C2410_DMA_DEBUG | |||
| 117 | Enable debugging output for the DMA code. This option sends info | 117 | Enable debugging output for the DMA code. This option sends info |
| 118 | to the kernel log, at priority KERN_DEBUG. | 118 | to the kernel log, at priority KERN_DEBUG. |
| 119 | 119 | ||
| 120 | config S3C24XX_ADC | ||
| 121 | bool "ADC common driver support" | ||
| 122 | help | ||
| 123 | Core support for the ADC block found in the S3C24XX SoC systems | ||
| 124 | for drivers such as the touchscreen and hwmon to use to share | ||
| 125 | this resource. | ||
| 126 | |||
| 127 | # SPI default pin configuration code | 120 | # SPI default pin configuration code |
| 128 | 121 | ||
| 129 | config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13 | 122 | config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13 |
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index 5dee8c12e8b4..e0100266d039 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile | |||
| @@ -38,7 +38,6 @@ obj-$(CONFIG_PM) += irq-pm.o | |||
| 38 | obj-$(CONFIG_PM) += sleep.o | 38 | obj-$(CONFIG_PM) += sleep.o |
| 39 | obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o | 39 | obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o |
| 40 | obj-$(CONFIG_S3C2410_DMA) += dma.o | 40 | obj-$(CONFIG_S3C2410_DMA) += dma.o |
| 41 | obj-$(CONFIG_S3C24XX_ADC) += adc.o | ||
| 42 | obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o | 41 | obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o |
| 43 | obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o | 42 | obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o |
| 44 | obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o | 43 | obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o |
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c index ac061a1bcb37..cf97caafe56b 100644 --- a/arch/arm/plat-s3c24xx/clock-dclk.c +++ b/arch/arm/plat-s3c24xx/clock-dclk.c | |||
| @@ -161,14 +161,18 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) | |||
| 161 | 161 | ||
| 162 | /* external clock definitions */ | 162 | /* external clock definitions */ |
| 163 | 163 | ||
| 164 | static struct clk_ops dclk_ops = { | ||
| 165 | .set_parent = s3c24xx_dclk_setparent, | ||
| 166 | .set_rate = s3c24xx_set_dclk_rate, | ||
| 167 | .round_rate = s3c24xx_round_dclk_rate, | ||
| 168 | }; | ||
| 169 | |||
| 164 | struct clk s3c24xx_dclk0 = { | 170 | struct clk s3c24xx_dclk0 = { |
| 165 | .name = "dclk0", | 171 | .name = "dclk0", |
| 166 | .id = -1, | 172 | .id = -1, |
| 167 | .ctrlbit = S3C2410_DCLKCON_DCLK0EN, | 173 | .ctrlbit = S3C2410_DCLKCON_DCLK0EN, |
| 168 | .enable = s3c24xx_dclk_enable, | 174 | .enable = s3c24xx_dclk_enable, |
| 169 | .set_parent = s3c24xx_dclk_setparent, | 175 | .ops = &dclk_ops, |
| 170 | .set_rate = s3c24xx_set_dclk_rate, | ||
| 171 | .round_rate = s3c24xx_round_dclk_rate, | ||
| 172 | }; | 176 | }; |
| 173 | 177 | ||
| 174 | struct clk s3c24xx_dclk1 = { | 178 | struct clk s3c24xx_dclk1 = { |
| @@ -176,19 +180,21 @@ struct clk s3c24xx_dclk1 = { | |||
| 176 | .id = -1, | 180 | .id = -1, |
| 177 | .ctrlbit = S3C2410_DCLKCON_DCLK1EN, | 181 | .ctrlbit = S3C2410_DCLKCON_DCLK1EN, |
| 178 | .enable = s3c24xx_dclk_enable, | 182 | .enable = s3c24xx_dclk_enable, |
| 179 | .set_parent = s3c24xx_dclk_setparent, | 183 | .ops = &dclk_ops, |
| 180 | .set_rate = s3c24xx_set_dclk_rate, | 184 | }; |
| 181 | .round_rate = s3c24xx_round_dclk_rate, | 185 | |
| 186 | static struct clk_ops clkout_ops = { | ||
| 187 | .set_parent = s3c24xx_clkout_setparent, | ||
| 182 | }; | 188 | }; |
| 183 | 189 | ||
| 184 | struct clk s3c24xx_clkout0 = { | 190 | struct clk s3c24xx_clkout0 = { |
| 185 | .name = "clkout0", | 191 | .name = "clkout0", |
| 186 | .id = -1, | 192 | .id = -1, |
| 187 | .set_parent = s3c24xx_clkout_setparent, | 193 | .ops = &clkout_ops, |
| 188 | }; | 194 | }; |
| 189 | 195 | ||
| 190 | struct clk s3c24xx_clkout1 = { | 196 | struct clk s3c24xx_clkout1 = { |
| 191 | .name = "clkout1", | 197 | .name = "clkout1", |
| 192 | .id = -1, | 198 | .id = -1, |
| 193 | .set_parent = s3c24xx_clkout_setparent, | 199 | .ops = &clkout_ops, |
| 194 | }; | 200 | }; |
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 7f686a31e672..986d4e5408f5 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c | |||
| @@ -32,6 +32,7 @@ | |||
| 32 | 32 | ||
| 33 | #include <plat/regs-serial.h> | 33 | #include <plat/regs-serial.h> |
| 34 | #include <plat/udc.h> | 34 | #include <plat/udc.h> |
| 35 | #include <plat/mci.h> | ||
| 35 | 36 | ||
| 36 | #include <plat/devs.h> | 37 | #include <plat/devs.h> |
| 37 | #include <plat/cpu.h> | 38 | #include <plat/cpu.h> |
| @@ -112,34 +113,6 @@ struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { | |||
| 112 | }, | 113 | }, |
| 113 | }; | 114 | }; |
| 114 | 115 | ||
| 115 | /* yart devices */ | ||
| 116 | |||
| 117 | static struct platform_device s3c24xx_uart_device0 = { | ||
| 118 | .id = 0, | ||
| 119 | }; | ||
| 120 | |||
| 121 | static struct platform_device s3c24xx_uart_device1 = { | ||
| 122 | .id = 1, | ||
| 123 | }; | ||
| 124 | |||
| 125 | static struct platform_device s3c24xx_uart_device2 = { | ||
| 126 | .id = 2, | ||
| 127 | }; | ||
| 128 | |||
| 129 | static struct platform_device s3c24xx_uart_device3 = { | ||
| 130 | .id = 3, | ||
| 131 | }; | ||
| 132 | |||
| 133 | struct platform_device *s3c24xx_uart_src[4] = { | ||
| 134 | &s3c24xx_uart_device0, | ||
| 135 | &s3c24xx_uart_device1, | ||
| 136 | &s3c24xx_uart_device2, | ||
| 137 | &s3c24xx_uart_device3, | ||
| 138 | }; | ||
| 139 | |||
| 140 | struct platform_device *s3c24xx_uart_devs[4] = { | ||
| 141 | }; | ||
| 142 | |||
| 143 | /* LCD Controller */ | 116 | /* LCD Controller */ |
| 144 | 117 | ||
| 145 | static struct resource s3c_lcd_resource[] = { | 118 | static struct resource s3c_lcd_resource[] = { |
| @@ -379,6 +352,18 @@ struct platform_device s3c_device_sdi = { | |||
| 379 | 352 | ||
| 380 | EXPORT_SYMBOL(s3c_device_sdi); | 353 | EXPORT_SYMBOL(s3c_device_sdi); |
| 381 | 354 | ||
| 355 | void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata) | ||
| 356 | { | ||
| 357 | struct s3c24xx_mci_pdata *npd; | ||
| 358 | |||
| 359 | npd = kmemdup(pdata, sizeof(struct s3c24xx_mci_pdata), GFP_KERNEL); | ||
| 360 | if (!npd) | ||
| 361 | printk(KERN_ERR "%s: no memory to copy pdata", __func__); | ||
| 362 | |||
| 363 | s3c_device_sdi.dev.platform_data = npd; | ||
| 364 | } | ||
| 365 | |||
| 366 | |||
| 382 | /* SPI (0) */ | 367 | /* SPI (0) */ |
| 383 | 368 | ||
| 384 | static struct resource s3c_spi0_resource[] = { | 369 | static struct resource s3c_spi0_resource[] = { |
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c index 6d7a961d3269..4f0f11a6a677 100644 --- a/arch/arm/plat-s3c24xx/gpiolib.c +++ b/arch/arm/plat-s3c24xx/gpiolib.c | |||
| @@ -20,7 +20,7 @@ | |||
| 20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
| 21 | #include <linux/gpio.h> | 21 | #include <linux/gpio.h> |
| 22 | 22 | ||
| 23 | #include <mach/gpio-core.h> | 23 | #include <plat/gpio-core.h> |
| 24 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
| 25 | #include <asm/irq.h> | 25 | #include <asm/irq.h> |
| 26 | #include <plat/pm.h> | 26 | #include <plat/pm.h> |
diff --git a/arch/arm/plat-s3c24xx/include/plat/mci.h b/arch/arm/plat-s3c24xx/include/plat/mci.h index 36aaa10fad06..2ac2b21ec490 100644 --- a/arch/arm/plat-s3c24xx/include/plat/mci.h +++ b/arch/arm/plat-s3c24xx/include/plat/mci.h | |||
| @@ -40,4 +40,13 @@ struct s3c24xx_mci_pdata { | |||
| 40 | unsigned short vdd); | 40 | unsigned short vdd); |
| 41 | }; | 41 | }; |
| 42 | 42 | ||
| 43 | /** | ||
| 44 | * s3c24xx_mci_set_platdata - set platform data for mmc/sdi device | ||
| 45 | * @pdata: The platform data | ||
| 46 | * | ||
| 47 | * Copy the platform data supplied by @pdata so that this can be marked | ||
| 48 | * __initdata. | ||
| 49 | */ | ||
| 50 | extern void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata); | ||
| 51 | |||
| 43 | #endif /* _ARCH_NCI_H */ | 52 | #endif /* _ARCH_NCI_H */ |
diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/plat-s3c24xx/s3c244x-clock.c index 79371091aa38..f8d96130d1d1 100644 --- a/arch/arm/plat-s3c24xx/s3c244x-clock.c +++ b/arch/arm/plat-s3c24xx/s3c244x-clock.c | |||
| @@ -68,7 +68,9 @@ static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent) | |||
| 68 | static struct clk clk_arm = { | 68 | static struct clk clk_arm = { |
| 69 | .name = "armclk", | 69 | .name = "armclk", |
| 70 | .id = -1, | 70 | .id = -1, |
| 71 | .set_parent = s3c2440_setparent_armclk, | 71 | .ops = &(struct clk_ops) { |
| 72 | .set_parent = s3c2440_setparent_armclk, | ||
| 73 | }, | ||
| 72 | }; | 74 | }; |
| 73 | 75 | ||
| 74 | static int s3c244x_clk_add(struct sys_device *sysdev) | 76 | static int s3c244x_clk_add(struct sys_device *sysdev) |
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig index e6da87a5885c..37b4519fb832 100644 --- a/arch/arm/plat-s3c64xx/Kconfig +++ b/arch/arm/plat-s3c64xx/Kconfig | |||
| @@ -13,12 +13,16 @@ config PLAT_S3C64XX | |||
| 13 | select ARM_VIC | 13 | select ARM_VIC |
| 14 | select NO_IOPORT | 14 | select NO_IOPORT |
| 15 | select ARCH_REQUIRE_GPIOLIB | 15 | select ARCH_REQUIRE_GPIOLIB |
| 16 | select SAMSUNG_CLKSRC | ||
| 17 | select SAMSUNG_IRQ_VIC_TIMER | ||
| 18 | select SAMSUNG_IRQ_UART | ||
| 16 | select S3C_GPIO_TRACK | 19 | select S3C_GPIO_TRACK |
| 17 | select S3C_GPIO_PULL_UPDOWN | 20 | select S3C_GPIO_PULL_UPDOWN |
| 18 | select S3C_GPIO_CFG_S3C24XX | 21 | select S3C_GPIO_CFG_S3C24XX |
| 19 | select S3C_GPIO_CFG_S3C64XX | 22 | select S3C_GPIO_CFG_S3C64XX |
| 20 | select S3C_DEV_NAND | 23 | select S3C_DEV_NAND |
| 21 | select USB_ARCH_HAS_OHCI | 24 | select USB_ARCH_HAS_OHCI |
| 25 | select SAMSUNG_GPIOLIB_4BIT | ||
| 22 | help | 26 | help |
| 23 | Base platform code for any Samsung S3C64XX device | 27 | Base platform code for any Samsung S3C64XX device |
| 24 | 28 | ||
diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index b85b4359e935..80255a5e1789 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile | |||
| @@ -13,6 +13,7 @@ obj- := | |||
| 13 | # Core files | 13 | # Core files |
| 14 | 14 | ||
| 15 | obj-y += dev-uart.o | 15 | obj-y += dev-uart.o |
| 16 | obj-y += dev-rtc.o | ||
| 16 | obj-y += cpu.o | 17 | obj-y += cpu.o |
| 17 | obj-y += irq.o | 18 | obj-y += irq.o |
| 18 | obj-y += irq-eint.o | 19 | obj-y += irq-eint.o |
| @@ -35,6 +36,10 @@ obj-$(CONFIG_PM) += irq-pm.o | |||
| 35 | 36 | ||
| 36 | obj-$(CONFIG_S3C64XX_DMA) += dma.o | 37 | obj-$(CONFIG_S3C64XX_DMA) += dma.o |
| 37 | 38 | ||
| 39 | # ADC support | ||
| 40 | |||
| 41 | obj-$(CONFIG_S3C_ADC) += dev-adc.o | ||
| 42 | |||
| 38 | # Device setup | 43 | # Device setup |
| 39 | 44 | ||
| 40 | obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o | 45 | obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o |
| @@ -42,3 +47,4 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o | |||
| 42 | obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o | 47 | obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o |
| 43 | obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o | 48 | obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o |
| 44 | obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o | 49 | obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o |
| 50 | obj-$(CONFIG_SPI_S3C64XX) += dev-spi.o | ||
diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c index 7a36e899360d..2989c3a2e94d 100644 --- a/arch/arm/plat-s3c64xx/clock.c +++ b/arch/arm/plat-s3c64xx/clock.c | |||
| @@ -141,6 +141,18 @@ static struct clk init_clocks_disable[] = { | |||
| 141 | .enable = s3c64xx_pclk_ctrl, | 141 | .enable = s3c64xx_pclk_ctrl, |
| 142 | .ctrlbit = S3C_CLKCON_PCLK_SPI1, | 142 | .ctrlbit = S3C_CLKCON_PCLK_SPI1, |
| 143 | }, { | 143 | }, { |
| 144 | .name = "spi_48m", | ||
| 145 | .id = 0, | ||
| 146 | .parent = &clk_48m, | ||
| 147 | .enable = s3c64xx_sclk_ctrl, | ||
| 148 | .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, | ||
| 149 | }, { | ||
| 150 | .name = "spi_48m", | ||
| 151 | .id = 1, | ||
| 152 | .parent = &clk_48m, | ||
| 153 | .enable = s3c64xx_sclk_ctrl, | ||
| 154 | .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, | ||
| 155 | }, { | ||
| 144 | .name = "48m", | 156 | .name = "48m", |
| 145 | .id = 0, | 157 | .id = 0, |
| 146 | .parent = &clk_48m, | 158 | .parent = &clk_48m, |
| @@ -274,15 +286,7 @@ void __init s3c64xx_register_clocks(void) | |||
| 274 | int ptr; | 286 | int ptr; |
| 275 | 287 | ||
| 276 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | 288 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); |
| 277 | 289 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | |
| 278 | clkp = init_clocks; | ||
| 279 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { | ||
| 280 | ret = s3c24xx_register_clock(clkp); | ||
| 281 | if (ret < 0) { | ||
| 282 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
| 283 | clkp->name, ret); | ||
| 284 | } | ||
| 285 | } | ||
| 286 | 290 | ||
| 287 | clkp = init_clocks_disable; | 291 | clkp = init_clocks_disable; |
| 288 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { | 292 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { |
diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c index 49796d2db86d..bc7ca1812e32 100644 --- a/arch/arm/plat-s3c64xx/cpu.c +++ b/arch/arm/plat-s3c64xx/cpu.c | |||
| @@ -73,17 +73,22 @@ static struct map_desc s3c_iodesc[] __initdata = { | |||
| 73 | .length = SZ_4K, | 73 | .length = SZ_4K, |
| 74 | .type = MT_DEVICE, | 74 | .type = MT_DEVICE, |
| 75 | }, { | 75 | }, { |
| 76 | .virtual = (unsigned long)S3C_VA_MEM, | ||
| 77 | .pfn = __phys_to_pfn(S3C64XX_PA_SROM), | ||
| 78 | .length = SZ_4K, | ||
| 79 | .type = MT_DEVICE, | ||
| 80 | }, { | ||
| 76 | .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS), | 81 | .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS), |
| 77 | .pfn = __phys_to_pfn(S3C_PA_UART), | 82 | .pfn = __phys_to_pfn(S3C_PA_UART), |
| 78 | .length = SZ_4K, | 83 | .length = SZ_4K, |
| 79 | .type = MT_DEVICE, | 84 | .type = MT_DEVICE, |
| 80 | }, { | 85 | }, { |
| 81 | .virtual = (unsigned long)S3C_VA_VIC0, | 86 | .virtual = (unsigned long)VA_VIC0, |
| 82 | .pfn = __phys_to_pfn(S3C64XX_PA_VIC0), | 87 | .pfn = __phys_to_pfn(S3C64XX_PA_VIC0), |
| 83 | .length = SZ_16K, | 88 | .length = SZ_16K, |
| 84 | .type = MT_DEVICE, | 89 | .type = MT_DEVICE, |
| 85 | }, { | 90 | }, { |
| 86 | .virtual = (unsigned long)S3C_VA_VIC1, | 91 | .virtual = (unsigned long)VA_VIC1, |
| 87 | .pfn = __phys_to_pfn(S3C64XX_PA_VIC1), | 92 | .pfn = __phys_to_pfn(S3C64XX_PA_VIC1), |
| 88 | .length = SZ_16K, | 93 | .length = SZ_16K, |
| 89 | .type = MT_DEVICE, | 94 | .type = MT_DEVICE, |
diff --git a/arch/arm/plat-s3c64xx/dev-adc.c b/arch/arm/plat-s3c64xx/dev-adc.c new file mode 100644 index 000000000000..fafef9b6bcfa --- /dev/null +++ b/arch/arm/plat-s3c64xx/dev-adc.c | |||
| @@ -0,0 +1,46 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c64xx/dev-adc.c | ||
| 2 | * | ||
| 3 | * Copyright 2010 Maurus Cuelenaere | ||
| 4 | * | ||
| 5 | * S3C64xx series device definition for ADC device | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/string.h> | ||
| 14 | #include <linux/platform_device.h> | ||
| 15 | |||
| 16 | #include <mach/irqs.h> | ||
| 17 | #include <mach/map.h> | ||
| 18 | |||
| 19 | #include <plat/adc.h> | ||
| 20 | #include <plat/devs.h> | ||
| 21 | #include <plat/cpu.h> | ||
| 22 | |||
| 23 | static struct resource s3c_adc_resource[] = { | ||
| 24 | [0] = { | ||
| 25 | .start = S3C64XX_PA_ADC, | ||
| 26 | .end = S3C64XX_PA_ADC + SZ_256 - 1, | ||
| 27 | .flags = IORESOURCE_MEM, | ||
| 28 | }, | ||
| 29 | [1] = { | ||
| 30 | .start = IRQ_TC, | ||
| 31 | .end = IRQ_TC, | ||
| 32 | .flags = IORESOURCE_IRQ, | ||
| 33 | }, | ||
| 34 | [2] = { | ||
| 35 | .start = IRQ_ADC, | ||
| 36 | .end = IRQ_ADC, | ||
| 37 | .flags = IORESOURCE_IRQ, | ||
| 38 | }, | ||
| 39 | }; | ||
| 40 | |||
| 41 | struct platform_device s3c_device_adc = { | ||
| 42 | .name = "s3c64xx-adc", | ||
| 43 | .id = -1, | ||
| 44 | .num_resources = ARRAY_SIZE(s3c_adc_resource), | ||
| 45 | .resource = s3c_adc_resource, | ||
| 46 | }; | ||
diff --git a/arch/arm/plat-s3c64xx/dev-audio.c b/arch/arm/plat-s3c64xx/dev-audio.c index a21a88fbb7e3..f6b7bfb519d7 100644 --- a/arch/arm/plat-s3c64xx/dev-audio.c +++ b/arch/arm/plat-s3c64xx/dev-audio.c | |||
| @@ -3,7 +3,6 @@ | |||
| 3 | * Copyright 2009 Wolfson Microelectronics | 3 | * Copyright 2009 Wolfson Microelectronics |
| 4 | * Mark Brown <broonie@opensource.wolfsonmicro.com> | 4 | * Mark Brown <broonie@opensource.wolfsonmicro.com> |
| 5 | * | 5 | * |
| 6 | |||
| 7 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as | 7 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
| @@ -20,16 +19,69 @@ | |||
| 20 | 19 | ||
| 21 | #include <plat/devs.h> | 20 | #include <plat/devs.h> |
| 22 | #include <plat/audio.h> | 21 | #include <plat/audio.h> |
| 22 | #include <plat/gpio-bank-c.h> | ||
| 23 | #include <plat/gpio-bank-d.h> | 23 | #include <plat/gpio-bank-d.h> |
| 24 | #include <plat/gpio-bank-e.h> | 24 | #include <plat/gpio-bank-e.h> |
| 25 | #include <plat/gpio-bank-h.h> | ||
| 25 | #include <plat/gpio-cfg.h> | 26 | #include <plat/gpio-cfg.h> |
| 26 | 27 | ||
| 28 | static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev) | ||
| 29 | { | ||
| 30 | switch (pdev->id) { | ||
| 31 | case 0: | ||
| 32 | s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK); | ||
| 33 | s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK); | ||
| 34 | s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK); | ||
| 35 | s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI); | ||
| 36 | s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_D0); | ||
| 37 | break; | ||
| 38 | case 1: | ||
| 39 | s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK); | ||
| 40 | s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK); | ||
| 41 | s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK); | ||
| 42 | s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI); | ||
| 43 | s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0); | ||
| 44 | default: | ||
| 45 | printk(KERN_DEBUG "Invalid I2S Controller number!"); | ||
| 46 | return -EINVAL; | ||
| 47 | } | ||
| 48 | |||
| 49 | return 0; | ||
| 50 | } | ||
| 51 | |||
| 52 | static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev) | ||
| 53 | { | ||
| 54 | s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0); | ||
| 55 | s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1); | ||
| 56 | s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2); | ||
| 57 | s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK); | ||
| 58 | s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK); | ||
| 59 | s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK); | ||
| 60 | s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI); | ||
| 61 | |||
| 62 | return 0; | ||
| 63 | } | ||
| 64 | |||
| 27 | static struct resource s3c64xx_iis0_resource[] = { | 65 | static struct resource s3c64xx_iis0_resource[] = { |
| 28 | [0] = { | 66 | [0] = { |
| 29 | .start = S3C64XX_PA_IIS0, | 67 | .start = S3C64XX_PA_IIS0, |
| 30 | .end = S3C64XX_PA_IIS0 + 0x100 - 1, | 68 | .end = S3C64XX_PA_IIS0 + 0x100 - 1, |
| 31 | .flags = IORESOURCE_MEM, | 69 | .flags = IORESOURCE_MEM, |
| 32 | }, | 70 | }, |
| 71 | [1] = { | ||
| 72 | .start = DMACH_I2S0_OUT, | ||
| 73 | .end = DMACH_I2S0_OUT, | ||
| 74 | .flags = IORESOURCE_DMA, | ||
| 75 | }, | ||
| 76 | [2] = { | ||
| 77 | .start = DMACH_I2S0_IN, | ||
| 78 | .end = DMACH_I2S0_IN, | ||
| 79 | .flags = IORESOURCE_DMA, | ||
| 80 | }, | ||
| 81 | }; | ||
| 82 | |||
| 83 | static struct s3c_audio_pdata s3c_i2s0_pdata = { | ||
| 84 | .cfg_gpio = s3c64xx_i2sv3_cfg_gpio, | ||
| 33 | }; | 85 | }; |
| 34 | 86 | ||
| 35 | struct platform_device s3c64xx_device_iis0 = { | 87 | struct platform_device s3c64xx_device_iis0 = { |
| @@ -37,6 +89,9 @@ struct platform_device s3c64xx_device_iis0 = { | |||
| 37 | .id = 0, | 89 | .id = 0, |
| 38 | .num_resources = ARRAY_SIZE(s3c64xx_iis0_resource), | 90 | .num_resources = ARRAY_SIZE(s3c64xx_iis0_resource), |
| 39 | .resource = s3c64xx_iis0_resource, | 91 | .resource = s3c64xx_iis0_resource, |
| 92 | .dev = { | ||
| 93 | .platform_data = &s3c_i2s0_pdata, | ||
| 94 | }, | ||
| 40 | }; | 95 | }; |
| 41 | EXPORT_SYMBOL(s3c64xx_device_iis0); | 96 | EXPORT_SYMBOL(s3c64xx_device_iis0); |
| 42 | 97 | ||
| @@ -46,6 +101,20 @@ static struct resource s3c64xx_iis1_resource[] = { | |||
| 46 | .end = S3C64XX_PA_IIS1 + 0x100 - 1, | 101 | .end = S3C64XX_PA_IIS1 + 0x100 - 1, |
| 47 | .flags = IORESOURCE_MEM, | 102 | .flags = IORESOURCE_MEM, |
| 48 | }, | 103 | }, |
| 104 | [1] = { | ||
| 105 | .start = DMACH_I2S1_OUT, | ||
| 106 | .end = DMACH_I2S1_OUT, | ||
| 107 | .flags = IORESOURCE_DMA, | ||
| 108 | }, | ||
| 109 | [2] = { | ||
| 110 | .start = DMACH_I2S1_IN, | ||
| 111 | .end = DMACH_I2S1_IN, | ||
| 112 | .flags = IORESOURCE_DMA, | ||
| 113 | }, | ||
| 114 | }; | ||
| 115 | |||
| 116 | static struct s3c_audio_pdata s3c_i2s1_pdata = { | ||
| 117 | .cfg_gpio = s3c64xx_i2sv3_cfg_gpio, | ||
| 49 | }; | 118 | }; |
| 50 | 119 | ||
| 51 | struct platform_device s3c64xx_device_iis1 = { | 120 | struct platform_device s3c64xx_device_iis1 = { |
| @@ -53,6 +122,9 @@ struct platform_device s3c64xx_device_iis1 = { | |||
| 53 | .id = 1, | 122 | .id = 1, |
| 54 | .num_resources = ARRAY_SIZE(s3c64xx_iis1_resource), | 123 | .num_resources = ARRAY_SIZE(s3c64xx_iis1_resource), |
| 55 | .resource = s3c64xx_iis1_resource, | 124 | .resource = s3c64xx_iis1_resource, |
| 125 | .dev = { | ||
| 126 | .platform_data = &s3c_i2s1_pdata, | ||
| 127 | }, | ||
| 56 | }; | 128 | }; |
| 57 | EXPORT_SYMBOL(s3c64xx_device_iis1); | 129 | EXPORT_SYMBOL(s3c64xx_device_iis1); |
| 58 | 130 | ||
| @@ -62,6 +134,20 @@ static struct resource s3c64xx_iisv4_resource[] = { | |||
| 62 | .end = S3C64XX_PA_IISV4 + 0x100 - 1, | 134 | .end = S3C64XX_PA_IISV4 + 0x100 - 1, |
| 63 | .flags = IORESOURCE_MEM, | 135 | .flags = IORESOURCE_MEM, |
| 64 | }, | 136 | }, |
| 137 | [1] = { | ||
| 138 | .start = DMACH_HSI_I2SV40_TX, | ||
| 139 | .end = DMACH_HSI_I2SV40_TX, | ||
| 140 | .flags = IORESOURCE_DMA, | ||
| 141 | }, | ||
| 142 | [2] = { | ||
| 143 | .start = DMACH_HSI_I2SV40_RX, | ||
| 144 | .end = DMACH_HSI_I2SV40_RX, | ||
| 145 | .flags = IORESOURCE_DMA, | ||
| 146 | }, | ||
| 147 | }; | ||
| 148 | |||
| 149 | static struct s3c_audio_pdata s3c_i2sv4_pdata = { | ||
| 150 | .cfg_gpio = s3c64xx_i2sv4_cfg_gpio, | ||
| 65 | }; | 151 | }; |
| 66 | 152 | ||
| 67 | struct platform_device s3c64xx_device_iisv4 = { | 153 | struct platform_device s3c64xx_device_iisv4 = { |
| @@ -69,6 +155,9 @@ struct platform_device s3c64xx_device_iisv4 = { | |||
| 69 | .id = -1, | 155 | .id = -1, |
| 70 | .num_resources = ARRAY_SIZE(s3c64xx_iisv4_resource), | 156 | .num_resources = ARRAY_SIZE(s3c64xx_iisv4_resource), |
| 71 | .resource = s3c64xx_iisv4_resource, | 157 | .resource = s3c64xx_iisv4_resource, |
| 158 | .dev = { | ||
| 159 | .platform_data = &s3c_i2sv4_pdata, | ||
| 160 | }, | ||
| 72 | }; | 161 | }; |
| 73 | EXPORT_SYMBOL(s3c64xx_device_iisv4); | 162 | EXPORT_SYMBOL(s3c64xx_device_iisv4); |
| 74 | 163 | ||
diff --git a/arch/arm/plat-s3c64xx/dev-rtc.c b/arch/arm/plat-s3c64xx/dev-rtc.c new file mode 100644 index 000000000000..b9e7a05f0129 --- /dev/null +++ b/arch/arm/plat-s3c64xx/dev-rtc.c | |||
| @@ -0,0 +1,43 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c64xx/dev-rtc.c | ||
| 2 | * | ||
| 3 | * Copyright 2009 by Maurus Cuelenaere <mcuelenaere@gmail.com> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <linux/string.h> | ||
| 12 | #include <linux/platform_device.h> | ||
| 13 | |||
| 14 | #include <mach/irqs.h> | ||
| 15 | #include <mach/map.h> | ||
| 16 | |||
| 17 | #include <plat/devs.h> | ||
| 18 | |||
| 19 | static struct resource s3c_rtc_resource[] = { | ||
| 20 | [0] = { | ||
| 21 | .start = S3C64XX_PA_RTC, | ||
| 22 | .end = S3C64XX_PA_RTC + 0xff, | ||
| 23 | .flags = IORESOURCE_MEM, | ||
| 24 | }, | ||
| 25 | [1] = { | ||
| 26 | .start = IRQ_RTC_ALARM, | ||
| 27 | .end = IRQ_RTC_ALARM, | ||
| 28 | .flags = IORESOURCE_IRQ, | ||
| 29 | }, | ||
| 30 | [2] = { | ||
| 31 | .start = IRQ_RTC_TIC, | ||
| 32 | .end = IRQ_RTC_TIC, | ||
| 33 | .flags = IORESOURCE_IRQ | ||
| 34 | } | ||
| 35 | }; | ||
| 36 | |||
| 37 | struct platform_device s3c_device_rtc = { | ||
| 38 | .name = "s3c64xx-rtc", | ||
| 39 | .id = -1, | ||
| 40 | .num_resources = ARRAY_SIZE(s3c_rtc_resource), | ||
| 41 | .resource = s3c_rtc_resource, | ||
| 42 | }; | ||
| 43 | EXPORT_SYMBOL(s3c_device_rtc); | ||
diff --git a/arch/arm/plat-s3c64xx/dev-spi.c b/arch/arm/plat-s3c64xx/dev-spi.c new file mode 100644 index 000000000000..ca10388d7ed1 --- /dev/null +++ b/arch/arm/plat-s3c64xx/dev-spi.c | |||
| @@ -0,0 +1,183 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c64xx/dev-spi.c | ||
| 2 | * | ||
| 3 | * Copyright (C) 2009 Samsung Electronics Ltd. | ||
| 4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/string.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/dma-mapping.h> | ||
| 15 | |||
| 16 | #include <mach/dma.h> | ||
| 17 | #include <mach/map.h> | ||
| 18 | #include <mach/gpio.h> | ||
| 19 | |||
| 20 | #include <plat/spi-clocks.h> | ||
| 21 | |||
| 22 | #include <plat/s3c64xx-spi.h> | ||
| 23 | #include <plat/gpio-bank-c.h> | ||
| 24 | #include <plat/gpio-cfg.h> | ||
| 25 | #include <plat/irqs.h> | ||
| 26 | |||
| 27 | static char *spi_src_clks[] = { | ||
| 28 | [S3C64XX_SPI_SRCCLK_PCLK] = "pclk", | ||
| 29 | [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus", | ||
| 30 | [S3C64XX_SPI_SRCCLK_48M] = "spi_48m", | ||
| 31 | }; | ||
| 32 | |||
| 33 | /* SPI Controller platform_devices */ | ||
| 34 | |||
| 35 | /* Since we emulate multi-cs capability, we do not touch the GPC-3,7. | ||
| 36 | * The emulated CS is toggled by board specific mechanism, as it can | ||
| 37 | * be either some immediate GPIO or some signal out of some other | ||
| 38 | * chip in between ... or some yet another way. | ||
| 39 | * We simply do not assume anything about CS. | ||
| 40 | */ | ||
| 41 | static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev) | ||
| 42 | { | ||
| 43 | switch (pdev->id) { | ||
| 44 | case 0: | ||
| 45 | s3c_gpio_cfgpin(S3C64XX_GPC(0), S3C64XX_GPC0_SPI_MISO0); | ||
| 46 | s3c_gpio_cfgpin(S3C64XX_GPC(1), S3C64XX_GPC1_SPI_CLKO); | ||
| 47 | s3c_gpio_cfgpin(S3C64XX_GPC(2), S3C64XX_GPC2_SPI_MOSIO); | ||
| 48 | s3c_gpio_setpull(S3C64XX_GPC(0), S3C_GPIO_PULL_UP); | ||
| 49 | s3c_gpio_setpull(S3C64XX_GPC(1), S3C_GPIO_PULL_UP); | ||
| 50 | s3c_gpio_setpull(S3C64XX_GPC(2), S3C_GPIO_PULL_UP); | ||
| 51 | break; | ||
| 52 | |||
| 53 | case 1: | ||
| 54 | s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_SPI_MISO1); | ||
| 55 | s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_SPI_CLK1); | ||
| 56 | s3c_gpio_cfgpin(S3C64XX_GPC(6), S3C64XX_GPC6_SPI_MOSI1); | ||
| 57 | s3c_gpio_setpull(S3C64XX_GPC(4), S3C_GPIO_PULL_UP); | ||
| 58 | s3c_gpio_setpull(S3C64XX_GPC(5), S3C_GPIO_PULL_UP); | ||
| 59 | s3c_gpio_setpull(S3C64XX_GPC(6), S3C_GPIO_PULL_UP); | ||
| 60 | break; | ||
| 61 | |||
| 62 | default: | ||
| 63 | dev_err(&pdev->dev, "Invalid SPI Controller number!"); | ||
| 64 | return -EINVAL; | ||
| 65 | } | ||
| 66 | |||
| 67 | return 0; | ||
| 68 | } | ||
| 69 | |||
| 70 | static struct resource s3c64xx_spi0_resource[] = { | ||
| 71 | [0] = { | ||
| 72 | .start = S3C64XX_PA_SPI0, | ||
| 73 | .end = S3C64XX_PA_SPI0 + 0x100 - 1, | ||
| 74 | .flags = IORESOURCE_MEM, | ||
| 75 | }, | ||
| 76 | [1] = { | ||
| 77 | .start = DMACH_SPI0_TX, | ||
| 78 | .end = DMACH_SPI0_TX, | ||
| 79 | .flags = IORESOURCE_DMA, | ||
| 80 | }, | ||
| 81 | [2] = { | ||
| 82 | .start = DMACH_SPI0_RX, | ||
| 83 | .end = DMACH_SPI0_RX, | ||
| 84 | .flags = IORESOURCE_DMA, | ||
| 85 | }, | ||
| 86 | [3] = { | ||
| 87 | .start = IRQ_SPI0, | ||
| 88 | .end = IRQ_SPI0, | ||
| 89 | .flags = IORESOURCE_IRQ, | ||
| 90 | }, | ||
| 91 | }; | ||
| 92 | |||
| 93 | static struct s3c64xx_spi_info s3c64xx_spi0_pdata = { | ||
| 94 | .cfg_gpio = s3c64xx_spi_cfg_gpio, | ||
| 95 | .fifo_lvl_mask = 0x7f, | ||
| 96 | .rx_lvl_offset = 13, | ||
| 97 | }; | ||
| 98 | |||
| 99 | static u64 spi_dmamask = DMA_BIT_MASK(32); | ||
| 100 | |||
| 101 | struct platform_device s3c64xx_device_spi0 = { | ||
| 102 | .name = "s3c64xx-spi", | ||
| 103 | .id = 0, | ||
| 104 | .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource), | ||
| 105 | .resource = s3c64xx_spi0_resource, | ||
| 106 | .dev = { | ||
| 107 | .dma_mask = &spi_dmamask, | ||
| 108 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 109 | .platform_data = &s3c64xx_spi0_pdata, | ||
| 110 | }, | ||
| 111 | }; | ||
| 112 | EXPORT_SYMBOL(s3c64xx_device_spi0); | ||
| 113 | |||
| 114 | static struct resource s3c64xx_spi1_resource[] = { | ||
| 115 | [0] = { | ||
| 116 | .start = S3C64XX_PA_SPI1, | ||
| 117 | .end = S3C64XX_PA_SPI1 + 0x100 - 1, | ||
| 118 | .flags = IORESOURCE_MEM, | ||
| 119 | }, | ||
| 120 | [1] = { | ||
| 121 | .start = DMACH_SPI1_TX, | ||
| 122 | .end = DMACH_SPI1_TX, | ||
| 123 | .flags = IORESOURCE_DMA, | ||
| 124 | }, | ||
| 125 | [2] = { | ||
| 126 | .start = DMACH_SPI1_RX, | ||
| 127 | .end = DMACH_SPI1_RX, | ||
| 128 | .flags = IORESOURCE_DMA, | ||
| 129 | }, | ||
| 130 | [3] = { | ||
| 131 | .start = IRQ_SPI1, | ||
| 132 | .end = IRQ_SPI1, | ||
| 133 | .flags = IORESOURCE_IRQ, | ||
| 134 | }, | ||
| 135 | }; | ||
| 136 | |||
| 137 | static struct s3c64xx_spi_info s3c64xx_spi1_pdata = { | ||
| 138 | .cfg_gpio = s3c64xx_spi_cfg_gpio, | ||
| 139 | .fifo_lvl_mask = 0x7f, | ||
| 140 | .rx_lvl_offset = 13, | ||
| 141 | }; | ||
| 142 | |||
| 143 | struct platform_device s3c64xx_device_spi1 = { | ||
| 144 | .name = "s3c64xx-spi", | ||
| 145 | .id = 1, | ||
| 146 | .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource), | ||
| 147 | .resource = s3c64xx_spi1_resource, | ||
| 148 | .dev = { | ||
| 149 | .dma_mask = &spi_dmamask, | ||
| 150 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 151 | .platform_data = &s3c64xx_spi1_pdata, | ||
| 152 | }, | ||
| 153 | }; | ||
| 154 | EXPORT_SYMBOL(s3c64xx_device_spi1); | ||
| 155 | |||
| 156 | void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) | ||
| 157 | { | ||
| 158 | struct s3c64xx_spi_info *pd; | ||
| 159 | |||
| 160 | /* Reject invalid configuration */ | ||
| 161 | if (!num_cs || src_clk_nr < 0 | ||
| 162 | || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) { | ||
| 163 | printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); | ||
| 164 | return; | ||
| 165 | } | ||
| 166 | |||
| 167 | switch (cntrlr) { | ||
| 168 | case 0: | ||
| 169 | pd = &s3c64xx_spi0_pdata; | ||
| 170 | break; | ||
| 171 | case 1: | ||
| 172 | pd = &s3c64xx_spi1_pdata; | ||
| 173 | break; | ||
| 174 | default: | ||
| 175 | printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", | ||
| 176 | __func__, cntrlr); | ||
| 177 | return; | ||
| 178 | } | ||
| 179 | |||
| 180 | pd->num_cs = num_cs; | ||
| 181 | pd->src_clk_nr = src_clk_nr; | ||
| 182 | pd->src_clk_name = spi_src_clks[src_clk_nr]; | ||
| 183 | } | ||
diff --git a/arch/arm/plat-s3c64xx/dev-uart.c b/arch/arm/plat-s3c64xx/dev-uart.c index 62c11a6fc7ba..f797f748b999 100644 --- a/arch/arm/plat-s3c64xx/dev-uart.c +++ b/arch/arm/plat-s3c64xx/dev-uart.c | |||
| @@ -145,32 +145,3 @@ struct s3c24xx_uart_resources s3c64xx_uart_resources[] __initdata = { | |||
| 145 | .nr_resources = ARRAY_SIZE(s3c64xx_uart3_resource), | 145 | .nr_resources = ARRAY_SIZE(s3c64xx_uart3_resource), |
| 146 | }, | 146 | }, |
| 147 | }; | 147 | }; |
| 148 | |||
| 149 | /* uart devices */ | ||
| 150 | |||
| 151 | static struct platform_device s3c24xx_uart_device0 = { | ||
| 152 | .id = 0, | ||
| 153 | }; | ||
| 154 | |||
| 155 | static struct platform_device s3c24xx_uart_device1 = { | ||
| 156 | .id = 1, | ||
| 157 | }; | ||
| 158 | |||
| 159 | static struct platform_device s3c24xx_uart_device2 = { | ||
| 160 | .id = 2, | ||
| 161 | }; | ||
| 162 | |||
| 163 | static struct platform_device s3c24xx_uart_device3 = { | ||
| 164 | .id = 3, | ||
| 165 | }; | ||
| 166 | |||
| 167 | struct platform_device *s3c24xx_uart_src[4] = { | ||
| 168 | &s3c24xx_uart_device0, | ||
| 169 | &s3c24xx_uart_device1, | ||
| 170 | &s3c24xx_uart_device2, | ||
| 171 | &s3c24xx_uart_device3, | ||
| 172 | }; | ||
| 173 | |||
| 174 | struct platform_device *s3c24xx_uart_devs[4] = { | ||
| 175 | }; | ||
| 176 | |||
diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c index 778560457277..b6e3f55321fa 100644 --- a/arch/arm/plat-s3c64xx/gpiolib.c +++ b/arch/arm/plat-s3c64xx/gpiolib.c | |||
| @@ -18,8 +18,8 @@ | |||
| 18 | 18 | ||
| 19 | #include <mach/map.h> | 19 | #include <mach/map.h> |
| 20 | #include <mach/gpio.h> | 20 | #include <mach/gpio.h> |
| 21 | #include <mach/gpio-core.h> | ||
| 22 | 21 | ||
| 22 | #include <plat/gpio-core.h> | ||
| 23 | #include <plat/gpio-cfg.h> | 23 | #include <plat/gpio-cfg.h> |
| 24 | #include <plat/gpio-cfg-helpers.h> | 24 | #include <plat/gpio-cfg-helpers.h> |
| 25 | #include <plat/regs-gpio.h> | 25 | #include <plat/regs-gpio.h> |
| @@ -49,150 +49,6 @@ | |||
| 49 | * [2] BANK has two control registers, GPxCON0 and GPxCON1 | 49 | * [2] BANK has two control registers, GPxCON0 and GPxCON1 |
| 50 | */ | 50 | */ |
| 51 | 51 | ||
| 52 | #define OFF_GPCON (0x00) | ||
| 53 | #define OFF_GPDAT (0x04) | ||
| 54 | |||
| 55 | #define con_4bit_shift(__off) ((__off) * 4) | ||
| 56 | |||
| 57 | #if 1 | ||
| 58 | #define gpio_dbg(x...) do { } while(0) | ||
| 59 | #else | ||
| 60 | #define gpio_dbg(x...) printk(KERN_DEBUG x) | ||
| 61 | #endif | ||
| 62 | |||
| 63 | /* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where | ||
| 64 | * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the | ||
| 65 | * following example: | ||
| 66 | * | ||
| 67 | * base + 0x00: Control register, 4 bits per gpio | ||
| 68 | * gpio n: 4 bits starting at (4*n) | ||
| 69 | * 0000 = input, 0001 = output, others mean special-function | ||
| 70 | * base + 0x04: Data register, 1 bit per gpio | ||
| 71 | * bit n: data bit n | ||
| 72 | * | ||
| 73 | * Note, since the data register is one bit per gpio and is at base + 0x4 | ||
| 74 | * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of | ||
| 75 | * the output. | ||
| 76 | */ | ||
| 77 | |||
| 78 | static int s3c64xx_gpiolib_4bit_input(struct gpio_chip *chip, unsigned offset) | ||
| 79 | { | ||
| 80 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
| 81 | void __iomem *base = ourchip->base; | ||
| 82 | unsigned long con; | ||
| 83 | |||
| 84 | con = __raw_readl(base + OFF_GPCON); | ||
| 85 | con &= ~(0xf << con_4bit_shift(offset)); | ||
| 86 | __raw_writel(con, base + OFF_GPCON); | ||
| 87 | |||
| 88 | gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); | ||
| 89 | |||
| 90 | return 0; | ||
| 91 | } | ||
| 92 | |||
| 93 | static int s3c64xx_gpiolib_4bit_output(struct gpio_chip *chip, | ||
| 94 | unsigned offset, int value) | ||
| 95 | { | ||
| 96 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
| 97 | void __iomem *base = ourchip->base; | ||
| 98 | unsigned long con; | ||
| 99 | unsigned long dat; | ||
| 100 | |||
| 101 | con = __raw_readl(base + OFF_GPCON); | ||
| 102 | con &= ~(0xf << con_4bit_shift(offset)); | ||
| 103 | con |= 0x1 << con_4bit_shift(offset); | ||
| 104 | |||
| 105 | dat = __raw_readl(base + OFF_GPDAT); | ||
| 106 | if (value) | ||
| 107 | dat |= 1 << offset; | ||
| 108 | else | ||
| 109 | dat &= ~(1 << offset); | ||
| 110 | |||
| 111 | __raw_writel(dat, base + OFF_GPDAT); | ||
| 112 | __raw_writel(con, base + OFF_GPCON); | ||
| 113 | __raw_writel(dat, base + OFF_GPDAT); | ||
| 114 | |||
| 115 | gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); | ||
| 116 | |||
| 117 | return 0; | ||
| 118 | } | ||
| 119 | |||
| 120 | /* The next set of routines are for the case where the GPIO configuration | ||
| 121 | * registers are 4 bits per GPIO but there is more than one register (the | ||
| 122 | * bank has more than 8 GPIOs. | ||
| 123 | * | ||
| 124 | * This case is the similar to the 4 bit case, but the registers are as | ||
| 125 | * follows: | ||
| 126 | * | ||
| 127 | * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) | ||
| 128 | * gpio n: 4 bits starting at (4*n) | ||
| 129 | * 0000 = input, 0001 = output, others mean special-function | ||
| 130 | * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) | ||
| 131 | * gpio n: 4 bits starting at (4*n) | ||
| 132 | * 0000 = input, 0001 = output, others mean special-function | ||
| 133 | * base + 0x08: Data register, 1 bit per gpio | ||
| 134 | * bit n: data bit n | ||
| 135 | * | ||
| 136 | * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we | ||
| 137 | * store the 'base + 0x4' address so that these routines see the data | ||
| 138 | * register at ourchip->base + 0x04. | ||
| 139 | */ | ||
| 140 | |||
| 141 | static int s3c64xx_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned offset) | ||
| 142 | { | ||
| 143 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
| 144 | void __iomem *base = ourchip->base; | ||
| 145 | void __iomem *regcon = base; | ||
| 146 | unsigned long con; | ||
| 147 | |||
| 148 | if (offset > 7) | ||
| 149 | offset -= 8; | ||
| 150 | else | ||
| 151 | regcon -= 4; | ||
| 152 | |||
| 153 | con = __raw_readl(regcon); | ||
| 154 | con &= ~(0xf << con_4bit_shift(offset)); | ||
| 155 | __raw_writel(con, regcon); | ||
| 156 | |||
| 157 | gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); | ||
| 158 | |||
| 159 | return 0; | ||
| 160 | |||
| 161 | } | ||
| 162 | |||
| 163 | static int s3c64xx_gpiolib_4bit2_output(struct gpio_chip *chip, | ||
| 164 | unsigned offset, int value) | ||
| 165 | { | ||
| 166 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
| 167 | void __iomem *base = ourchip->base; | ||
| 168 | void __iomem *regcon = base; | ||
| 169 | unsigned long con; | ||
| 170 | unsigned long dat; | ||
| 171 | |||
| 172 | if (offset > 7) | ||
| 173 | offset -= 8; | ||
| 174 | else | ||
| 175 | regcon -= 4; | ||
| 176 | |||
| 177 | con = __raw_readl(regcon); | ||
| 178 | con &= ~(0xf << con_4bit_shift(offset)); | ||
| 179 | con |= 0x1 << con_4bit_shift(offset); | ||
| 180 | |||
| 181 | dat = __raw_readl(base + OFF_GPDAT); | ||
| 182 | if (value) | ||
| 183 | dat |= 1 << offset; | ||
| 184 | else | ||
| 185 | dat &= ~(1 << offset); | ||
| 186 | |||
| 187 | __raw_writel(dat, base + OFF_GPDAT); | ||
| 188 | __raw_writel(con, regcon); | ||
| 189 | __raw_writel(dat, base + OFF_GPDAT); | ||
| 190 | |||
| 191 | gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); | ||
| 192 | |||
| 193 | return 0; | ||
| 194 | } | ||
| 195 | |||
| 196 | static struct s3c_gpio_cfg gpio_4bit_cfg_noint = { | 52 | static struct s3c_gpio_cfg gpio_4bit_cfg_noint = { |
| 197 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | 53 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, |
| 198 | .set_pull = s3c_gpio_setpull_updown, | 54 | .set_pull = s3c_gpio_setpull_updown, |
| @@ -399,20 +255,6 @@ static struct s3c_gpio_chip gpio_2bit[] = { | |||
| 399 | }, | 255 | }, |
| 400 | }; | 256 | }; |
| 401 | 257 | ||
| 402 | static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip) | ||
| 403 | { | ||
| 404 | chip->chip.direction_input = s3c64xx_gpiolib_4bit_input; | ||
| 405 | chip->chip.direction_output = s3c64xx_gpiolib_4bit_output; | ||
| 406 | chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); | ||
| 407 | } | ||
| 408 | |||
| 409 | static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) | ||
| 410 | { | ||
| 411 | chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input; | ||
| 412 | chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output; | ||
| 413 | chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); | ||
| 414 | } | ||
| 415 | |||
| 416 | static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip) | 258 | static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip) |
| 417 | { | 259 | { |
| 418 | chip->pm = __gpio_pm(&s3c_gpio_pm_2bit); | 260 | chip->pm = __gpio_pm(&s3c_gpio_pm_2bit); |
| @@ -432,10 +274,10 @@ static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips, | |||
| 432 | static __init int s3c64xx_gpiolib_init(void) | 274 | static __init int s3c64xx_gpiolib_init(void) |
| 433 | { | 275 | { |
| 434 | s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit), | 276 | s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit), |
| 435 | s3c64xx_gpiolib_add_4bit); | 277 | samsung_gpiolib_add_4bit); |
| 436 | 278 | ||
| 437 | s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2), | 279 | s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2), |
| 438 | s3c64xx_gpiolib_add_4bit2); | 280 | samsung_gpiolib_add_4bit2); |
| 439 | 281 | ||
| 440 | s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), | 282 | s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), |
| 441 | s3c64xx_gpiolib_add_2bit); | 283 | s3c64xx_gpiolib_add_2bit); |
diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h index 7956fd3bb194..a22758194e6d 100644 --- a/arch/arm/plat-s3c64xx/include/plat/irqs.h +++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h | |||
| @@ -24,8 +24,8 @@ | |||
| 24 | 24 | ||
| 25 | #define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) | 25 | #define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) |
| 26 | 26 | ||
| 27 | #define S3C_VIC0_BASE S3C_IRQ(0) | 27 | #define IRQ_VIC0_BASE S3C_IRQ(0) |
| 28 | #define S3C_VIC1_BASE S3C_IRQ(32) | 28 | #define IRQ_VIC1_BASE S3C_IRQ(32) |
| 29 | 29 | ||
| 30 | /* UART interrupts, each UART has 4 intterupts per channel so | 30 | /* UART interrupts, each UART has 4 intterupts per channel so |
| 31 | * use the space between the ISA and S3C main interrupts. Note, these | 31 | * use the space between the ISA and S3C main interrupts. Note, these |
| @@ -59,8 +59,8 @@ | |||
| 59 | 59 | ||
| 60 | /* VIC based IRQs */ | 60 | /* VIC based IRQs */ |
| 61 | 61 | ||
| 62 | #define S3C64XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x)) | 62 | #define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x)) |
| 63 | #define S3C64XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x)) | 63 | #define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x)) |
| 64 | 64 | ||
| 65 | /* VIC0 */ | 65 | /* VIC0 */ |
| 66 | 66 | ||
| @@ -198,7 +198,11 @@ | |||
| 198 | * interrupt controllers). */ | 198 | * interrupt controllers). */ |
| 199 | #define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) | 199 | #define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) |
| 200 | 200 | ||
| 201 | #ifdef CONFIG_SMDK6410_WM1190_EV1 | ||
| 202 | #define IRQ_BOARD_NR 64 | ||
| 203 | #else | ||
| 201 | #define IRQ_BOARD_NR 16 | 204 | #define IRQ_BOARD_NR 16 |
| 205 | #endif | ||
| 202 | 206 | ||
| 203 | #define IRQ_BOARD_END (IRQ_BOARD_START + IRQ_BOARD_NR) | 207 | #define IRQ_BOARD_END (IRQ_BOARD_START + IRQ_BOARD_NR) |
| 204 | 208 | ||
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h index ff46e7fa957a..3ef62741e5d1 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h | |||
| @@ -35,14 +35,6 @@ | |||
| 35 | #define S3C_MEM0_GATE S3C_CLKREG(0x3C) | 35 | #define S3C_MEM0_GATE S3C_CLKREG(0x3C) |
| 36 | 36 | ||
| 37 | /* CLKDIV0 */ | 37 | /* CLKDIV0 */ |
| 38 | #define S3C6400_CLKDIV0_MFC_MASK (0xf << 28) | ||
| 39 | #define S3C6400_CLKDIV0_MFC_SHIFT (28) | ||
| 40 | #define S3C6400_CLKDIV0_JPEG_MASK (0xf << 24) | ||
| 41 | #define S3C6400_CLKDIV0_JPEG_SHIFT (24) | ||
| 42 | #define S3C6400_CLKDIV0_CAM_MASK (0xf << 20) | ||
| 43 | #define S3C6400_CLKDIV0_CAM_SHIFT (20) | ||
| 44 | #define S3C6400_CLKDIV0_SECURITY_MASK (0x3 << 18) | ||
| 45 | #define S3C6400_CLKDIV0_SECURITY_SHIFT (18) | ||
| 46 | #define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) | 38 | #define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) |
| 47 | #define S3C6400_CLKDIV0_PCLK_SHIFT (12) | 39 | #define S3C6400_CLKDIV0_PCLK_SHIFT (12) |
| 48 | #define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9) | 40 | #define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9) |
| @@ -51,42 +43,11 @@ | |||
| 51 | #define S3C6400_CLKDIV0_HCLK_SHIFT (8) | 43 | #define S3C6400_CLKDIV0_HCLK_SHIFT (8) |
| 52 | #define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4) | 44 | #define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4) |
| 53 | #define S3C6400_CLKDIV0_MPLL_SHIFT (4) | 45 | #define S3C6400_CLKDIV0_MPLL_SHIFT (4) |
| 46 | |||
| 54 | #define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0) | 47 | #define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0) |
| 55 | #define S3C6410_CLKDIV0_ARM_MASK (0xf << 0) | 48 | #define S3C6410_CLKDIV0_ARM_MASK (0xf << 0) |
| 56 | #define S3C6400_CLKDIV0_ARM_SHIFT (0) | 49 | #define S3C6400_CLKDIV0_ARM_SHIFT (0) |
| 57 | 50 | ||
| 58 | /* CLKDIV1 */ | ||
| 59 | #define S3C6410_CLKDIV1_FIMC_MASK (0xf << 24) | ||
| 60 | #define S3C6410_CLKDIV1_FIMC_SHIFT (24) | ||
| 61 | #define S3C6400_CLKDIV1_UHOST_MASK (0xf << 20) | ||
| 62 | #define S3C6400_CLKDIV1_UHOST_SHIFT (20) | ||
| 63 | #define S3C6400_CLKDIV1_SCALER_MASK (0xf << 16) | ||
| 64 | #define S3C6400_CLKDIV1_SCALER_SHIFT (16) | ||
| 65 | #define S3C6400_CLKDIV1_LCD_MASK (0xf << 12) | ||
| 66 | #define S3C6400_CLKDIV1_LCD_SHIFT (12) | ||
| 67 | #define S3C6400_CLKDIV1_MMC2_MASK (0xf << 8) | ||
| 68 | #define S3C6400_CLKDIV1_MMC2_SHIFT (8) | ||
| 69 | #define S3C6400_CLKDIV1_MMC1_MASK (0xf << 4) | ||
| 70 | #define S3C6400_CLKDIV1_MMC1_SHIFT (4) | ||
| 71 | #define S3C6400_CLKDIV1_MMC0_MASK (0xf << 0) | ||
| 72 | #define S3C6400_CLKDIV1_MMC0_SHIFT (0) | ||
| 73 | |||
| 74 | /* CLKDIV2 */ | ||
| 75 | #define S3C6410_CLKDIV2_AUDIO2_MASK (0xf << 24) | ||
| 76 | #define S3C6410_CLKDIV2_AUDIO2_SHIFT (24) | ||
| 77 | #define S3C6400_CLKDIV2_IRDA_MASK (0xf << 20) | ||
| 78 | #define S3C6400_CLKDIV2_IRDA_SHIFT (20) | ||
| 79 | #define S3C6400_CLKDIV2_UART_MASK (0xf << 16) | ||
| 80 | #define S3C6400_CLKDIV2_UART_SHIFT (16) | ||
| 81 | #define S3C6400_CLKDIV2_AUDIO1_MASK (0xf << 12) | ||
| 82 | #define S3C6400_CLKDIV2_AUDIO1_SHIFT (12) | ||
| 83 | #define S3C6400_CLKDIV2_AUDIO0_MASK (0xf << 8) | ||
| 84 | #define S3C6400_CLKDIV2_AUDIO0_SHIFT (8) | ||
| 85 | #define S3C6400_CLKDIV2_SPI1_MASK (0xf << 4) | ||
| 86 | #define S3C6400_CLKDIV2_SPI1_SHIFT (4) | ||
| 87 | #define S3C6400_CLKDIV2_SPI0_MASK (0xf << 0) | ||
| 88 | #define S3C6400_CLKDIV2_SPI0_SHIFT (0) | ||
| 89 | |||
| 90 | /* HCLK GATE Registers */ | 51 | /* HCLK GATE Registers */ |
| 91 | #define S3C_CLKCON_HCLK_3DSE (1<<31) | 52 | #define S3C_CLKCON_HCLK_3DSE (1<<31) |
| 92 | #define S3C_CLKCON_HCLK_UHOST (1<<29) | 53 | #define S3C_CLKCON_HCLK_UHOST (1<<29) |
| @@ -192,34 +153,4 @@ | |||
| 192 | #define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2) | 153 | #define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2) |
| 193 | #define S3C6400_CLKSRC_MFC (1 << 4) | 154 | #define S3C6400_CLKSRC_MFC (1 << 4) |
| 194 | 155 | ||
| 195 | #define S3C6410_CLKSRC_TV27_MASK (0x1 << 31) | ||
| 196 | #define S3C6410_CLKSRC_TV27_SHIFT (31) | ||
| 197 | #define S3C6410_CLKSRC_DAC27_MASK (0x1 << 30) | ||
| 198 | #define S3C6410_CLKSRC_DAC27_SHIFT (30) | ||
| 199 | #define S3C6400_CLKSRC_SCALER_MASK (0x3 << 28) | ||
| 200 | #define S3C6400_CLKSRC_SCALER_SHIFT (28) | ||
| 201 | #define S3C6400_CLKSRC_LCD_MASK (0x3 << 26) | ||
| 202 | #define S3C6400_CLKSRC_LCD_SHIFT (26) | ||
| 203 | #define S3C6400_CLKSRC_IRDA_MASK (0x3 << 24) | ||
| 204 | #define S3C6400_CLKSRC_IRDA_SHIFT (24) | ||
| 205 | #define S3C6400_CLKSRC_MMC2_MASK (0x3 << 22) | ||
| 206 | #define S3C6400_CLKSRC_MMC2_SHIFT (22) | ||
| 207 | #define S3C6400_CLKSRC_MMC1_MASK (0x3 << 20) | ||
| 208 | #define S3C6400_CLKSRC_MMC1_SHIFT (20) | ||
| 209 | #define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18) | ||
| 210 | #define S3C6400_CLKSRC_MMC0_SHIFT (18) | ||
| 211 | #define S3C6400_CLKSRC_SPI1_MASK (0x3 << 16) | ||
| 212 | #define S3C6400_CLKSRC_SPI1_SHIFT (16) | ||
| 213 | #define S3C6400_CLKSRC_SPI0_MASK (0x3 << 14) | ||
| 214 | #define S3C6400_CLKSRC_SPI0_SHIFT (14) | ||
| 215 | #define S3C6400_CLKSRC_UART_MASK (0x1 << 13) | ||
| 216 | #define S3C6400_CLKSRC_UART_SHIFT (13) | ||
| 217 | #define S3C6400_CLKSRC_AUDIO1_MASK (0x7 << 10) | ||
| 218 | #define S3C6400_CLKSRC_AUDIO1_SHIFT (10) | ||
| 219 | #define S3C6400_CLKSRC_AUDIO0_MASK (0x7 << 7) | ||
| 220 | #define S3C6400_CLKSRC_AUDIO0_SHIFT (7) | ||
| 221 | #define S3C6400_CLKSRC_UHOST_MASK (0x3 << 5) | ||
| 222 | #define S3C6400_CLKSRC_UHOST_SHIFT (5) | ||
| 223 | |||
| 224 | |||
| 225 | #endif /* _PLAT_REGS_CLOCK_H */ | 156 | #endif /* _PLAT_REGS_CLOCK_H */ |
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-srom.h b/arch/arm/plat-s3c64xx/include/plat/regs-srom.h new file mode 100644 index 000000000000..756731b36297 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-srom.h | |||
| @@ -0,0 +1,59 @@ | |||
| 1 | /* arch/arm/plat-s3c64xx/include/plat/regs-srom.h | ||
| 2 | * | ||
| 3 | * Copyright 2009 Andy Green <andy@warmcat.com> | ||
| 4 | * | ||
| 5 | * S3C64XX SROM definitions | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __PLAT_REGS_SROM_H | ||
| 13 | #define __PLAT_REGS_SROM_H __FILE__ | ||
| 14 | |||
| 15 | #define S3C64XX_SROMREG(x) (S3C_VA_MEM + (x)) | ||
| 16 | |||
| 17 | #define S3C64XX_SROM_BW S3C64XX_SROMREG(0) | ||
| 18 | #define S3C64XX_SROM_BC0 S3C64XX_SROMREG(4) | ||
| 19 | #define S3C64XX_SROM_BC1 S3C64XX_SROMREG(8) | ||
| 20 | #define S3C64XX_SROM_BC2 S3C64XX_SROMREG(0xc) | ||
| 21 | #define S3C64XX_SROM_BC3 S3C64XX_SROMREG(0x10) | ||
| 22 | #define S3C64XX_SROM_BC4 S3C64XX_SROMREG(0x14) | ||
| 23 | #define S3C64XX_SROM_BC5 S3C64XX_SROMREG(0x18) | ||
| 24 | |||
| 25 | /* | ||
| 26 | * one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4 | ||
| 27 | */ | ||
| 28 | |||
| 29 | #define S3C64XX_SROM_BW__DATAWIDTH__SHIFT 0 | ||
| 30 | #define S3C64XX_SROM_BW__WAITENABLE__SHIFT 2 | ||
| 31 | #define S3C64XX_SROM_BW__BYTEENABLE__SHIFT 3 | ||
| 32 | #define S3C64XX_SROM_BW__CS_MASK 0xf | ||
| 33 | |||
| 34 | #define S3C64XX_SROM_BW__NCS0__SHIFT 0 | ||
| 35 | #define S3C64XX_SROM_BW__NCS1__SHIFT 4 | ||
| 36 | #define S3C64XX_SROM_BW__NCS2__SHIFT 8 | ||
| 37 | #define S3C64XX_SROM_BW__NCS3__SHIFT 0xc | ||
| 38 | #define S3C64XX_SROM_BW__NCS4__SHIFT 0x10 | ||
| 39 | |||
| 40 | /* | ||
| 41 | * applies to same to BCS0 - BCS4 | ||
| 42 | */ | ||
| 43 | |||
| 44 | #define S3C64XX_SROM_BCX__PMC__SHIFT 0 | ||
| 45 | #define S3C64XX_SROM_BCX__PMC__MASK 3 | ||
| 46 | #define S3C64XX_SROM_BCX__TACP__SHIFT 4 | ||
| 47 | #define S3C64XX_SROM_BCX__TACP__MASK 0xf | ||
| 48 | #define S3C64XX_SROM_BCX__TCAH__SHIFT 8 | ||
| 49 | #define S3C64XX_SROM_BCX__TCAH__MASK 0xf | ||
| 50 | #define S3C64XX_SROM_BCX__TCOH__SHIFT 12 | ||
| 51 | #define S3C64XX_SROM_BCX__TCOH__MASK 0xf | ||
| 52 | #define S3C64XX_SROM_BCX__TACC__SHIFT 16 | ||
| 53 | #define S3C64XX_SROM_BCX__TACC__MASK 0x1f | ||
| 54 | #define S3C64XX_SROM_BCX__TCOS__SHIFT 24 | ||
| 55 | #define S3C64XX_SROM_BCX__TCOS__MASK 0xf | ||
| 56 | #define S3C64XX_SROM_BCX__TACS__SHIFT 28 | ||
| 57 | #define S3C64XX_SROM_BCX__TACS__MASK 0xf | ||
| 58 | |||
| 59 | #endif /* _PLAT_REGS_SROM_H */ | ||
diff --git a/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h b/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h new file mode 100644 index 000000000000..524bdae3f625 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2009 Samsung Electronics Ltd. | ||
| 4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __S3C64XX_PLAT_SPI_CLKS_H | ||
| 12 | #define __S3C64XX_PLAT_SPI_CLKS_H __FILE__ | ||
| 13 | |||
| 14 | #define S3C64XX_SPI_SRCCLK_PCLK 0 | ||
| 15 | #define S3C64XX_SPI_SRCCLK_SPIBUS 1 | ||
| 16 | #define S3C64XX_SPI_SRCCLK_48M 2 | ||
| 17 | |||
| 18 | #endif /* __S3C64XX_PLAT_SPI_CLKS_H */ | ||
diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/plat-s3c64xx/irq.c index 8dc5b6da9789..67a145d440f3 100644 --- a/arch/arm/plat-s3c64xx/irq.c +++ b/arch/arm/plat-s3c64xx/irq.c | |||
| @@ -21,88 +21,11 @@ | |||
| 21 | #include <asm/hardware/vic.h> | 21 | #include <asm/hardware/vic.h> |
| 22 | 22 | ||
| 23 | #include <mach/map.h> | 23 | #include <mach/map.h> |
| 24 | #include <plat/regs-serial.h> | 24 | #include <plat/irq-vic-timer.h> |
| 25 | #include <plat/regs-timer.h> | 25 | #include <plat/irq-uart.h> |
| 26 | #include <plat/cpu.h> | 26 | #include <plat/cpu.h> |
| 27 | 27 | ||
| 28 | /* Timer interrupt handling */ | 28 | static struct s3c_uart_irq uart_irqs[] = { |
| 29 | |||
| 30 | static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq) | ||
| 31 | { | ||
| 32 | generic_handle_irq(sub_irq); | ||
| 33 | } | ||
| 34 | |||
| 35 | static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc) | ||
| 36 | { | ||
| 37 | s3c_irq_demux_timer(irq, IRQ_TIMER0); | ||
| 38 | } | ||
| 39 | |||
| 40 | static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc) | ||
| 41 | { | ||
| 42 | s3c_irq_demux_timer(irq, IRQ_TIMER1); | ||
| 43 | } | ||
| 44 | |||
| 45 | static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc) | ||
| 46 | { | ||
| 47 | s3c_irq_demux_timer(irq, IRQ_TIMER2); | ||
| 48 | } | ||
| 49 | |||
| 50 | static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc) | ||
| 51 | { | ||
| 52 | s3c_irq_demux_timer(irq, IRQ_TIMER3); | ||
| 53 | } | ||
| 54 | |||
| 55 | static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc) | ||
| 56 | { | ||
| 57 | s3c_irq_demux_timer(irq, IRQ_TIMER4); | ||
| 58 | } | ||
| 59 | |||
| 60 | /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ | ||
| 61 | |||
| 62 | static void s3c_irq_timer_mask(unsigned int irq) | ||
| 63 | { | ||
| 64 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
| 65 | |||
| 66 | reg &= 0x1f; /* mask out pending interrupts */ | ||
| 67 | reg &= ~(1 << (irq - IRQ_TIMER0)); | ||
| 68 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
| 69 | } | ||
| 70 | |||
| 71 | static void s3c_irq_timer_unmask(unsigned int irq) | ||
| 72 | { | ||
| 73 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
| 74 | |||
| 75 | reg &= 0x1f; /* mask out pending interrupts */ | ||
| 76 | reg |= 1 << (irq - IRQ_TIMER0); | ||
| 77 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
| 78 | } | ||
| 79 | |||
| 80 | static void s3c_irq_timer_ack(unsigned int irq) | ||
| 81 | { | ||
| 82 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
| 83 | |||
| 84 | reg &= 0x1f; | ||
| 85 | reg |= (1 << 5) << (irq - IRQ_TIMER0); | ||
| 86 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
| 87 | } | ||
| 88 | |||
| 89 | static struct irq_chip s3c_irq_timer = { | ||
| 90 | .name = "s3c-timer", | ||
| 91 | .mask = s3c_irq_timer_mask, | ||
| 92 | .unmask = s3c_irq_timer_unmask, | ||
| 93 | .ack = s3c_irq_timer_ack, | ||
| 94 | }; | ||
| 95 | |||
| 96 | struct uart_irq { | ||
| 97 | void __iomem *regs; | ||
| 98 | unsigned int base_irq; | ||
| 99 | unsigned int parent_irq; | ||
| 100 | }; | ||
| 101 | |||
| 102 | /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] | ||
| 103 | * are consecutive when looking up the interrupt in the demux routines. | ||
| 104 | */ | ||
| 105 | static struct uart_irq uart_irqs[] = { | ||
| 106 | [0] = { | 29 | [0] = { |
| 107 | .regs = S3C_VA_UART0, | 30 | .regs = S3C_VA_UART0, |
| 108 | .base_irq = IRQ_S3CUART_BASE0, | 31 | .base_irq = IRQ_S3CUART_BASE0, |
| @@ -125,132 +48,22 @@ static struct uart_irq uart_irqs[] = { | |||
| 125 | }, | 48 | }, |
| 126 | }; | 49 | }; |
| 127 | 50 | ||
| 128 | static inline void __iomem *s3c_irq_uart_base(unsigned int irq) | ||
| 129 | { | ||
| 130 | struct uart_irq *uirq = get_irq_chip_data(irq); | ||
| 131 | return uirq->regs; | ||
| 132 | } | ||
| 133 | |||
| 134 | static inline unsigned int s3c_irq_uart_bit(unsigned int irq) | ||
| 135 | { | ||
| 136 | return irq & 3; | ||
| 137 | } | ||
| 138 | |||
| 139 | /* UART interrupt registers, not worth adding to seperate include header */ | ||
| 140 | |||
| 141 | static void s3c_irq_uart_mask(unsigned int irq) | ||
| 142 | { | ||
| 143 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
| 144 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
| 145 | u32 reg; | ||
| 146 | |||
| 147 | reg = __raw_readl(regs + S3C64XX_UINTM); | ||
| 148 | reg |= (1 << bit); | ||
| 149 | __raw_writel(reg, regs + S3C64XX_UINTM); | ||
| 150 | } | ||
| 151 | |||
| 152 | static void s3c_irq_uart_maskack(unsigned int irq) | ||
| 153 | { | ||
| 154 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
| 155 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
| 156 | u32 reg; | ||
| 157 | |||
| 158 | reg = __raw_readl(regs + S3C64XX_UINTM); | ||
| 159 | reg |= (1 << bit); | ||
| 160 | __raw_writel(reg, regs + S3C64XX_UINTM); | ||
| 161 | __raw_writel(1 << bit, regs + S3C64XX_UINTP); | ||
| 162 | } | ||
| 163 | |||
| 164 | static void s3c_irq_uart_unmask(unsigned int irq) | ||
| 165 | { | ||
| 166 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
| 167 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
| 168 | u32 reg; | ||
| 169 | |||
| 170 | reg = __raw_readl(regs + S3C64XX_UINTM); | ||
| 171 | reg &= ~(1 << bit); | ||
| 172 | __raw_writel(reg, regs + S3C64XX_UINTM); | ||
| 173 | } | ||
| 174 | |||
| 175 | static void s3c_irq_uart_ack(unsigned int irq) | ||
| 176 | { | ||
| 177 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
| 178 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
| 179 | |||
| 180 | __raw_writel(1 << bit, regs + S3C64XX_UINTP); | ||
| 181 | } | ||
| 182 | |||
| 183 | static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) | ||
| 184 | { | ||
| 185 | struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0]; | ||
| 186 | u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); | ||
| 187 | int base = uirq->base_irq; | ||
| 188 | |||
| 189 | if (pend & (1 << 0)) | ||
| 190 | generic_handle_irq(base); | ||
| 191 | if (pend & (1 << 1)) | ||
| 192 | generic_handle_irq(base + 1); | ||
| 193 | if (pend & (1 << 2)) | ||
| 194 | generic_handle_irq(base + 2); | ||
| 195 | if (pend & (1 << 3)) | ||
| 196 | generic_handle_irq(base + 3); | ||
| 197 | } | ||
| 198 | |||
| 199 | static struct irq_chip s3c_irq_uart = { | ||
| 200 | .name = "s3c-uart", | ||
| 201 | .mask = s3c_irq_uart_mask, | ||
| 202 | .unmask = s3c_irq_uart_unmask, | ||
| 203 | .mask_ack = s3c_irq_uart_maskack, | ||
| 204 | .ack = s3c_irq_uart_ack, | ||
| 205 | }; | ||
| 206 | |||
| 207 | static void __init s3c64xx_uart_irq(struct uart_irq *uirq) | ||
| 208 | { | ||
| 209 | void __iomem *reg_base = uirq->regs; | ||
| 210 | unsigned int irq; | ||
| 211 | int offs; | ||
| 212 | |||
| 213 | /* mask all interrupts at the start. */ | ||
| 214 | __raw_writel(0xf, reg_base + S3C64XX_UINTM); | ||
| 215 | |||
| 216 | for (offs = 0; offs < 3; offs++) { | ||
| 217 | irq = uirq->base_irq + offs; | ||
| 218 | |||
| 219 | set_irq_chip(irq, &s3c_irq_uart); | ||
| 220 | set_irq_chip_data(irq, uirq); | ||
| 221 | set_irq_handler(irq, handle_level_irq); | ||
| 222 | set_irq_flags(irq, IRQF_VALID); | ||
| 223 | } | ||
| 224 | |||
| 225 | set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); | ||
| 226 | } | ||
| 227 | 51 | ||
| 228 | void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) | 52 | void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) |
| 229 | { | 53 | { |
| 230 | int uart, irq; | ||
| 231 | |||
| 232 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); | 54 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); |
| 233 | 55 | ||
| 234 | /* initialise the pair of VICs */ | 56 | /* initialise the pair of VICs */ |
| 235 | vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid, 0); | 57 | vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0); |
| 236 | vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid, 0); | 58 | vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0); |
| 237 | 59 | ||
| 238 | /* add the timer sub-irqs */ | 60 | /* add the timer sub-irqs */ |
| 239 | 61 | ||
| 240 | set_irq_chained_handler(IRQ_TIMER0_VIC, s3c_irq_demux_timer0); | 62 | s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); |
| 241 | set_irq_chained_handler(IRQ_TIMER1_VIC, s3c_irq_demux_timer1); | 63 | s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); |
| 242 | set_irq_chained_handler(IRQ_TIMER2_VIC, s3c_irq_demux_timer2); | 64 | s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); |
| 243 | set_irq_chained_handler(IRQ_TIMER3_VIC, s3c_irq_demux_timer3); | 65 | s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); |
| 244 | set_irq_chained_handler(IRQ_TIMER4_VIC, s3c_irq_demux_timer4); | 66 | s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); |
| 245 | |||
| 246 | for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) { | ||
| 247 | set_irq_chip(irq, &s3c_irq_timer); | ||
| 248 | set_irq_handler(irq, handle_level_irq); | ||
| 249 | set_irq_flags(irq, IRQF_VALID); | ||
| 250 | } | ||
| 251 | 67 | ||
| 252 | for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) | 68 | s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); |
| 253 | s3c64xx_uart_irq(&uart_irqs[uart]); | ||
| 254 | } | 69 | } |
| 255 | |||
| 256 | |||
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index ffd56deb9e81..cb2bf4bff051 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | 29 | ||
| 30 | #include <plat/regs-clock.h> | 30 | #include <plat/regs-clock.h> |
| 31 | #include <plat/clock.h> | 31 | #include <plat/clock.h> |
| 32 | #include <plat/clock-clksrc.h> | ||
| 32 | #include <plat/cpu.h> | 33 | #include <plat/cpu.h> |
| 33 | #include <plat/pll.h> | 34 | #include <plat/pll.h> |
| 34 | 35 | ||
| @@ -48,22 +49,6 @@ static struct clk clk_ext_xtal_mux = { | |||
| 48 | #define clk_fout_mpll clk_mpll | 49 | #define clk_fout_mpll clk_mpll |
| 49 | #define clk_fout_epll clk_epll | 50 | #define clk_fout_epll clk_epll |
| 50 | 51 | ||
| 51 | struct clk_sources { | ||
| 52 | unsigned int nr_sources; | ||
| 53 | struct clk **sources; | ||
| 54 | }; | ||
| 55 | |||
| 56 | struct clksrc_clk { | ||
| 57 | struct clk clk; | ||
| 58 | unsigned int mask; | ||
| 59 | unsigned int shift; | ||
| 60 | |||
| 61 | struct clk_sources *sources; | ||
| 62 | |||
| 63 | unsigned int divider_shift; | ||
| 64 | void __iomem *reg_divider; | ||
| 65 | }; | ||
| 66 | |||
| 67 | static struct clk clk_fout_apll = { | 52 | static struct clk clk_fout_apll = { |
| 68 | .name = "fout_apll", | 53 | .name = "fout_apll", |
| 69 | .id = -1, | 54 | .id = -1, |
| @@ -74,7 +59,7 @@ static struct clk *clk_src_apll_list[] = { | |||
| 74 | [1] = &clk_fout_apll, | 59 | [1] = &clk_fout_apll, |
| 75 | }; | 60 | }; |
| 76 | 61 | ||
| 77 | static struct clk_sources clk_src_apll = { | 62 | static struct clksrc_sources clk_src_apll = { |
| 78 | .sources = clk_src_apll_list, | 63 | .sources = clk_src_apll_list, |
| 79 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), | 64 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), |
| 80 | }; | 65 | }; |
| @@ -84,8 +69,7 @@ static struct clksrc_clk clk_mout_apll = { | |||
| 84 | .name = "mout_apll", | 69 | .name = "mout_apll", |
| 85 | .id = -1, | 70 | .id = -1, |
| 86 | }, | 71 | }, |
| 87 | .shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT, | 72 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, |
| 88 | .mask = S3C6400_CLKSRC_APLL_MOUT, | ||
| 89 | .sources = &clk_src_apll, | 73 | .sources = &clk_src_apll, |
| 90 | }; | 74 | }; |
| 91 | 75 | ||
| @@ -94,7 +78,7 @@ static struct clk *clk_src_epll_list[] = { | |||
| 94 | [1] = &clk_fout_epll, | 78 | [1] = &clk_fout_epll, |
| 95 | }; | 79 | }; |
| 96 | 80 | ||
| 97 | static struct clk_sources clk_src_epll = { | 81 | static struct clksrc_sources clk_src_epll = { |
| 98 | .sources = clk_src_epll_list, | 82 | .sources = clk_src_epll_list, |
| 99 | .nr_sources = ARRAY_SIZE(clk_src_epll_list), | 83 | .nr_sources = ARRAY_SIZE(clk_src_epll_list), |
| 100 | }; | 84 | }; |
| @@ -104,8 +88,7 @@ static struct clksrc_clk clk_mout_epll = { | |||
| 104 | .name = "mout_epll", | 88 | .name = "mout_epll", |
| 105 | .id = -1, | 89 | .id = -1, |
| 106 | }, | 90 | }, |
| 107 | .shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT, | 91 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, |
| 108 | .mask = S3C6400_CLKSRC_EPLL_MOUT, | ||
| 109 | .sources = &clk_src_epll, | 92 | .sources = &clk_src_epll, |
| 110 | }; | 93 | }; |
| 111 | 94 | ||
| @@ -114,7 +97,7 @@ static struct clk *clk_src_mpll_list[] = { | |||
| 114 | [1] = &clk_fout_mpll, | 97 | [1] = &clk_fout_mpll, |
| 115 | }; | 98 | }; |
| 116 | 99 | ||
| 117 | static struct clk_sources clk_src_mpll = { | 100 | static struct clksrc_sources clk_src_mpll = { |
| 118 | .sources = clk_src_mpll_list, | 101 | .sources = clk_src_mpll_list, |
| 119 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), | 102 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), |
| 120 | }; | 103 | }; |
| @@ -124,8 +107,7 @@ static struct clksrc_clk clk_mout_mpll = { | |||
| 124 | .name = "mout_mpll", | 107 | .name = "mout_mpll", |
| 125 | .id = -1, | 108 | .id = -1, |
| 126 | }, | 109 | }, |
| 127 | .shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT, | 110 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, |
| 128 | .mask = S3C6400_CLKSRC_MPLL_MOUT, | ||
| 129 | .sources = &clk_src_mpll, | 111 | .sources = &clk_src_mpll, |
| 130 | }; | 112 | }; |
| 131 | 113 | ||
| @@ -183,9 +165,11 @@ static struct clk clk_arm = { | |||
| 183 | .name = "armclk", | 165 | .name = "armclk", |
| 184 | .id = -1, | 166 | .id = -1, |
| 185 | .parent = &clk_mout_apll.clk, | 167 | .parent = &clk_mout_apll.clk, |
| 186 | .get_rate = s3c64xx_clk_arm_get_rate, | 168 | .ops = &(struct clk_ops) { |
| 187 | .set_rate = s3c64xx_clk_arm_set_rate, | 169 | .get_rate = s3c64xx_clk_arm_get_rate, |
| 188 | .round_rate = s3c64xx_clk_arm_round_rate, | 170 | .set_rate = s3c64xx_clk_arm_set_rate, |
| 171 | .round_rate = s3c64xx_clk_arm_round_rate, | ||
| 172 | }, | ||
| 189 | }; | 173 | }; |
| 190 | 174 | ||
| 191 | static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) | 175 | static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) |
| @@ -200,11 +184,15 @@ static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) | |||
| 200 | return rate; | 184 | return rate; |
| 201 | } | 185 | } |
| 202 | 186 | ||
| 187 | static struct clk_ops clk_dout_ops = { | ||
| 188 | .get_rate = s3c64xx_clk_doutmpll_get_rate, | ||
| 189 | }; | ||
| 190 | |||
| 203 | static struct clk clk_dout_mpll = { | 191 | static struct clk clk_dout_mpll = { |
| 204 | .name = "dout_mpll", | 192 | .name = "dout_mpll", |
| 205 | .id = -1, | 193 | .id = -1, |
| 206 | .parent = &clk_mout_mpll.clk, | 194 | .parent = &clk_mout_mpll.clk, |
| 207 | .get_rate = s3c64xx_clk_doutmpll_get_rate, | 195 | .ops = &clk_dout_ops, |
| 208 | }; | 196 | }; |
| 209 | 197 | ||
| 210 | static struct clk *clkset_spi_mmc_list[] = { | 198 | static struct clk *clkset_spi_mmc_list[] = { |
| @@ -214,7 +202,7 @@ static struct clk *clkset_spi_mmc_list[] = { | |||
| 214 | &clk_27m, | 202 | &clk_27m, |
| 215 | }; | 203 | }; |
| 216 | 204 | ||
| 217 | static struct clk_sources clkset_spi_mmc = { | 205 | static struct clksrc_sources clkset_spi_mmc = { |
| 218 | .sources = clkset_spi_mmc_list, | 206 | .sources = clkset_spi_mmc_list, |
| 219 | .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), | 207 | .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), |
| 220 | }; | 208 | }; |
| @@ -226,7 +214,7 @@ static struct clk *clkset_irda_list[] = { | |||
| 226 | &clk_27m, | 214 | &clk_27m, |
| 227 | }; | 215 | }; |
| 228 | 216 | ||
| 229 | static struct clk_sources clkset_irda = { | 217 | static struct clksrc_sources clkset_irda = { |
| 230 | .sources = clkset_irda_list, | 218 | .sources = clkset_irda_list, |
| 231 | .nr_sources = ARRAY_SIZE(clkset_irda_list), | 219 | .nr_sources = ARRAY_SIZE(clkset_irda_list), |
| 232 | }; | 220 | }; |
| @@ -238,7 +226,7 @@ static struct clk *clkset_uart_list[] = { | |||
| 238 | NULL | 226 | NULL |
| 239 | }; | 227 | }; |
| 240 | 228 | ||
| 241 | static struct clk_sources clkset_uart = { | 229 | static struct clksrc_sources clkset_uart = { |
| 242 | .sources = clkset_uart_list, | 230 | .sources = clkset_uart_list, |
| 243 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | 231 | .nr_sources = ARRAY_SIZE(clkset_uart_list), |
| 244 | }; | 232 | }; |
| @@ -250,12 +238,11 @@ static struct clk *clkset_uhost_list[] = { | |||
| 250 | &clk_fin_epll, | 238 | &clk_fin_epll, |
| 251 | }; | 239 | }; |
| 252 | 240 | ||
| 253 | static struct clk_sources clkset_uhost = { | 241 | static struct clksrc_sources clkset_uhost = { |
| 254 | .sources = clkset_uhost_list, | 242 | .sources = clkset_uhost_list, |
| 255 | .nr_sources = ARRAY_SIZE(clkset_uhost_list), | 243 | .nr_sources = ARRAY_SIZE(clkset_uhost_list), |
| 256 | }; | 244 | }; |
| 257 | 245 | ||
| 258 | |||
| 259 | /* The peripheral clocks are all controlled via clocksource followed | 246 | /* The peripheral clocks are all controlled via clocksource followed |
| 260 | * by an optional divider and gate stage. We currently roll this into | 247 | * by an optional divider and gate stage. We currently roll this into |
| 261 | * one clock which hides the intermediate clock from the mux. | 248 | * one clock which hides the intermediate clock from the mux. |
| @@ -266,221 +253,7 @@ static struct clk_sources clkset_uhost = { | |||
| 266 | * have a common parent divisor so are not included here. | 253 | * have a common parent divisor so are not included here. |
| 267 | */ | 254 | */ |
| 268 | 255 | ||
| 269 | static inline struct clksrc_clk *to_clksrc(struct clk *clk) | 256 | /* clocks that feed other parts of the clock source tree */ |
| 270 | { | ||
| 271 | return container_of(clk, struct clksrc_clk, clk); | ||
| 272 | } | ||
| 273 | |||
| 274 | static unsigned long s3c64xx_getrate_clksrc(struct clk *clk) | ||
| 275 | { | ||
| 276 | struct clksrc_clk *sclk = to_clksrc(clk); | ||
| 277 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 278 | u32 clkdiv = __raw_readl(sclk->reg_divider); | ||
| 279 | |||
| 280 | clkdiv >>= sclk->divider_shift; | ||
| 281 | clkdiv &= 0xf; | ||
| 282 | clkdiv++; | ||
| 283 | |||
| 284 | rate /= clkdiv; | ||
| 285 | return rate; | ||
| 286 | } | ||
| 287 | |||
| 288 | static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate) | ||
| 289 | { | ||
| 290 | struct clksrc_clk *sclk = to_clksrc(clk); | ||
| 291 | void __iomem *reg = sclk->reg_divider; | ||
| 292 | unsigned int div; | ||
| 293 | u32 val; | ||
| 294 | |||
| 295 | rate = clk_round_rate(clk, rate); | ||
| 296 | div = clk_get_rate(clk->parent) / rate; | ||
| 297 | if (div > 16) | ||
| 298 | return -EINVAL; | ||
| 299 | |||
| 300 | val = __raw_readl(reg); | ||
| 301 | val &= ~(0xf << sclk->divider_shift); | ||
| 302 | val |= (div - 1) << sclk->divider_shift; | ||
| 303 | __raw_writel(val, reg); | ||
| 304 | |||
| 305 | return 0; | ||
| 306 | } | ||
| 307 | |||
| 308 | static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent) | ||
| 309 | { | ||
| 310 | struct clksrc_clk *sclk = to_clksrc(clk); | ||
| 311 | struct clk_sources *srcs = sclk->sources; | ||
| 312 | u32 clksrc = __raw_readl(S3C_CLK_SRC); | ||
| 313 | int src_nr = -1; | ||
| 314 | int ptr; | ||
| 315 | |||
| 316 | for (ptr = 0; ptr < srcs->nr_sources; ptr++) | ||
| 317 | if (srcs->sources[ptr] == parent) { | ||
| 318 | src_nr = ptr; | ||
| 319 | break; | ||
| 320 | } | ||
| 321 | |||
| 322 | if (src_nr >= 0) { | ||
| 323 | clksrc &= ~sclk->mask; | ||
| 324 | clksrc |= src_nr << sclk->shift; | ||
| 325 | |||
| 326 | __raw_writel(clksrc, S3C_CLK_SRC); | ||
| 327 | |||
| 328 | clk->parent = parent; | ||
| 329 | return 0; | ||
| 330 | } | ||
| 331 | |||
| 332 | return -EINVAL; | ||
| 333 | } | ||
| 334 | |||
| 335 | static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk, | ||
| 336 | unsigned long rate) | ||
| 337 | { | ||
| 338 | unsigned long parent_rate = clk_get_rate(clk->parent); | ||
| 339 | int div; | ||
| 340 | |||
| 341 | if (rate > parent_rate) | ||
| 342 | rate = parent_rate; | ||
| 343 | else { | ||
| 344 | div = parent_rate / rate; | ||
| 345 | |||
| 346 | if (div == 0) | ||
| 347 | div = 1; | ||
| 348 | if (div > 16) | ||
| 349 | div = 16; | ||
| 350 | |||
| 351 | rate = parent_rate / div; | ||
| 352 | } | ||
| 353 | |||
| 354 | return rate; | ||
| 355 | } | ||
| 356 | |||
| 357 | static struct clksrc_clk clk_mmc0 = { | ||
| 358 | .clk = { | ||
| 359 | .name = "mmc_bus", | ||
| 360 | .id = 0, | ||
| 361 | .ctrlbit = S3C_CLKCON_SCLK_MMC0, | ||
| 362 | .enable = s3c64xx_sclk_ctrl, | ||
| 363 | .set_parent = s3c64xx_setparent_clksrc, | ||
| 364 | .get_rate = s3c64xx_getrate_clksrc, | ||
| 365 | .set_rate = s3c64xx_setrate_clksrc, | ||
| 366 | .round_rate = s3c64xx_roundrate_clksrc, | ||
| 367 | }, | ||
| 368 | .shift = S3C6400_CLKSRC_MMC0_SHIFT, | ||
| 369 | .mask = S3C6400_CLKSRC_MMC0_MASK, | ||
| 370 | .sources = &clkset_spi_mmc, | ||
| 371 | .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT, | ||
| 372 | .reg_divider = S3C_CLK_DIV1, | ||
| 373 | }; | ||
| 374 | |||
| 375 | static struct clksrc_clk clk_mmc1 = { | ||
| 376 | .clk = { | ||
| 377 | .name = "mmc_bus", | ||
| 378 | .id = 1, | ||
| 379 | .ctrlbit = S3C_CLKCON_SCLK_MMC1, | ||
| 380 | .enable = s3c64xx_sclk_ctrl, | ||
| 381 | .get_rate = s3c64xx_getrate_clksrc, | ||
| 382 | .set_rate = s3c64xx_setrate_clksrc, | ||
| 383 | .set_parent = s3c64xx_setparent_clksrc, | ||
| 384 | .round_rate = s3c64xx_roundrate_clksrc, | ||
| 385 | }, | ||
| 386 | .shift = S3C6400_CLKSRC_MMC1_SHIFT, | ||
| 387 | .mask = S3C6400_CLKSRC_MMC1_MASK, | ||
| 388 | .sources = &clkset_spi_mmc, | ||
| 389 | .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT, | ||
| 390 | .reg_divider = S3C_CLK_DIV1, | ||
| 391 | }; | ||
| 392 | |||
| 393 | static struct clksrc_clk clk_mmc2 = { | ||
| 394 | .clk = { | ||
| 395 | .name = "mmc_bus", | ||
| 396 | .id = 2, | ||
| 397 | .ctrlbit = S3C_CLKCON_SCLK_MMC2, | ||
| 398 | .enable = s3c64xx_sclk_ctrl, | ||
| 399 | .get_rate = s3c64xx_getrate_clksrc, | ||
| 400 | .set_rate = s3c64xx_setrate_clksrc, | ||
| 401 | .set_parent = s3c64xx_setparent_clksrc, | ||
| 402 | .round_rate = s3c64xx_roundrate_clksrc, | ||
| 403 | }, | ||
| 404 | .shift = S3C6400_CLKSRC_MMC2_SHIFT, | ||
| 405 | .mask = S3C6400_CLKSRC_MMC2_MASK, | ||
| 406 | .sources = &clkset_spi_mmc, | ||
| 407 | .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT, | ||
| 408 | .reg_divider = S3C_CLK_DIV1, | ||
| 409 | }; | ||
| 410 | |||
| 411 | static struct clksrc_clk clk_usbhost = { | ||
| 412 | .clk = { | ||
| 413 | .name = "usb-bus-host", | ||
| 414 | .id = -1, | ||
| 415 | .ctrlbit = S3C_CLKCON_SCLK_UHOST, | ||
| 416 | .enable = s3c64xx_sclk_ctrl, | ||
| 417 | .set_parent = s3c64xx_setparent_clksrc, | ||
| 418 | .get_rate = s3c64xx_getrate_clksrc, | ||
| 419 | .set_rate = s3c64xx_setrate_clksrc, | ||
| 420 | .round_rate = s3c64xx_roundrate_clksrc, | ||
| 421 | }, | ||
| 422 | .shift = S3C6400_CLKSRC_UHOST_SHIFT, | ||
| 423 | .mask = S3C6400_CLKSRC_UHOST_MASK, | ||
| 424 | .sources = &clkset_uhost, | ||
| 425 | .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT, | ||
| 426 | .reg_divider = S3C_CLK_DIV1, | ||
| 427 | }; | ||
| 428 | |||
| 429 | static struct clksrc_clk clk_uart_uclk1 = { | ||
| 430 | .clk = { | ||
| 431 | .name = "uclk1", | ||
| 432 | .id = -1, | ||
| 433 | .ctrlbit = S3C_CLKCON_SCLK_UART, | ||
| 434 | .enable = s3c64xx_sclk_ctrl, | ||
| 435 | .set_parent = s3c64xx_setparent_clksrc, | ||
| 436 | .get_rate = s3c64xx_getrate_clksrc, | ||
| 437 | .set_rate = s3c64xx_setrate_clksrc, | ||
| 438 | .round_rate = s3c64xx_roundrate_clksrc, | ||
| 439 | }, | ||
| 440 | .shift = S3C6400_CLKSRC_UART_SHIFT, | ||
| 441 | .mask = S3C6400_CLKSRC_UART_MASK, | ||
| 442 | .sources = &clkset_uart, | ||
| 443 | .divider_shift = S3C6400_CLKDIV2_UART_SHIFT, | ||
| 444 | .reg_divider = S3C_CLK_DIV2, | ||
| 445 | }; | ||
| 446 | |||
| 447 | /* Where does UCLK0 come from? */ | ||
| 448 | |||
| 449 | static struct clksrc_clk clk_spi0 = { | ||
| 450 | .clk = { | ||
| 451 | .name = "spi-bus", | ||
| 452 | .id = 0, | ||
| 453 | .ctrlbit = S3C_CLKCON_SCLK_SPI0, | ||
| 454 | .enable = s3c64xx_sclk_ctrl, | ||
| 455 | .set_parent = s3c64xx_setparent_clksrc, | ||
| 456 | .get_rate = s3c64xx_getrate_clksrc, | ||
| 457 | .set_rate = s3c64xx_setrate_clksrc, | ||
| 458 | .round_rate = s3c64xx_roundrate_clksrc, | ||
| 459 | }, | ||
| 460 | .shift = S3C6400_CLKSRC_SPI0_SHIFT, | ||
| 461 | .mask = S3C6400_CLKSRC_SPI0_MASK, | ||
| 462 | .sources = &clkset_spi_mmc, | ||
| 463 | .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT, | ||
| 464 | .reg_divider = S3C_CLK_DIV2, | ||
| 465 | }; | ||
| 466 | |||
| 467 | static struct clksrc_clk clk_spi1 = { | ||
| 468 | .clk = { | ||
| 469 | .name = "spi-bus", | ||
| 470 | .id = 1, | ||
| 471 | .ctrlbit = S3C_CLKCON_SCLK_SPI1, | ||
| 472 | .enable = s3c64xx_sclk_ctrl, | ||
| 473 | .set_parent = s3c64xx_setparent_clksrc, | ||
| 474 | .get_rate = s3c64xx_getrate_clksrc, | ||
| 475 | .set_rate = s3c64xx_setrate_clksrc, | ||
| 476 | .round_rate = s3c64xx_roundrate_clksrc, | ||
| 477 | }, | ||
| 478 | .shift = S3C6400_CLKSRC_SPI1_SHIFT, | ||
| 479 | .mask = S3C6400_CLKSRC_SPI1_MASK, | ||
| 480 | .sources = &clkset_spi_mmc, | ||
| 481 | .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT, | ||
| 482 | .reg_divider = S3C_CLK_DIV2, | ||
| 483 | }; | ||
| 484 | 257 | ||
| 485 | static struct clk clk_iis_cd0 = { | 258 | static struct clk clk_iis_cd0 = { |
| 486 | .name = "iis_cdclk0", | 259 | .name = "iis_cdclk0", |
| @@ -505,29 +278,11 @@ static struct clk *clkset_audio0_list[] = { | |||
| 505 | [4] = &clk_pcm_cd, | 278 | [4] = &clk_pcm_cd, |
| 506 | }; | 279 | }; |
| 507 | 280 | ||
| 508 | static struct clk_sources clkset_audio0 = { | 281 | static struct clksrc_sources clkset_audio0 = { |
| 509 | .sources = clkset_audio0_list, | 282 | .sources = clkset_audio0_list, |
| 510 | .nr_sources = ARRAY_SIZE(clkset_audio0_list), | 283 | .nr_sources = ARRAY_SIZE(clkset_audio0_list), |
| 511 | }; | 284 | }; |
| 512 | 285 | ||
| 513 | static struct clksrc_clk clk_audio0 = { | ||
| 514 | .clk = { | ||
| 515 | .name = "audio-bus", | ||
| 516 | .id = 0, | ||
| 517 | .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, | ||
| 518 | .enable = s3c64xx_sclk_ctrl, | ||
| 519 | .set_parent = s3c64xx_setparent_clksrc, | ||
| 520 | .get_rate = s3c64xx_getrate_clksrc, | ||
| 521 | .set_rate = s3c64xx_setrate_clksrc, | ||
| 522 | .round_rate = s3c64xx_roundrate_clksrc, | ||
| 523 | }, | ||
| 524 | .shift = S3C6400_CLKSRC_AUDIO0_SHIFT, | ||
| 525 | .mask = S3C6400_CLKSRC_AUDIO0_MASK, | ||
| 526 | .sources = &clkset_audio0, | ||
| 527 | .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT, | ||
| 528 | .reg_divider = S3C_CLK_DIV2, | ||
| 529 | }; | ||
| 530 | |||
| 531 | static struct clk *clkset_audio1_list[] = { | 286 | static struct clk *clkset_audio1_list[] = { |
| 532 | [0] = &clk_mout_epll.clk, | 287 | [0] = &clk_mout_epll.clk, |
| 533 | [1] = &clk_dout_mpll, | 288 | [1] = &clk_dout_mpll, |
| @@ -536,72 +291,133 @@ static struct clk *clkset_audio1_list[] = { | |||
| 536 | [4] = &clk_pcm_cd, | 291 | [4] = &clk_pcm_cd, |
| 537 | }; | 292 | }; |
| 538 | 293 | ||
| 539 | static struct clk_sources clkset_audio1 = { | 294 | static struct clksrc_sources clkset_audio1 = { |
| 540 | .sources = clkset_audio1_list, | 295 | .sources = clkset_audio1_list, |
| 541 | .nr_sources = ARRAY_SIZE(clkset_audio1_list), | 296 | .nr_sources = ARRAY_SIZE(clkset_audio1_list), |
| 542 | }; | 297 | }; |
| 543 | 298 | ||
| 544 | static struct clksrc_clk clk_audio1 = { | ||
| 545 | .clk = { | ||
| 546 | .name = "audio-bus", | ||
| 547 | .id = 1, | ||
| 548 | .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, | ||
| 549 | .enable = s3c64xx_sclk_ctrl, | ||
| 550 | .set_parent = s3c64xx_setparent_clksrc, | ||
| 551 | .get_rate = s3c64xx_getrate_clksrc, | ||
| 552 | .set_rate = s3c64xx_setrate_clksrc, | ||
| 553 | .round_rate = s3c64xx_roundrate_clksrc, | ||
| 554 | }, | ||
| 555 | .shift = S3C6400_CLKSRC_AUDIO1_SHIFT, | ||
| 556 | .mask = S3C6400_CLKSRC_AUDIO1_MASK, | ||
| 557 | .sources = &clkset_audio1, | ||
| 558 | .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT, | ||
| 559 | .reg_divider = S3C_CLK_DIV2, | ||
| 560 | }; | ||
| 561 | |||
| 562 | static struct clksrc_clk clk_irda = { | ||
| 563 | .clk = { | ||
| 564 | .name = "irda-bus", | ||
| 565 | .id = 0, | ||
| 566 | .ctrlbit = S3C_CLKCON_SCLK_IRDA, | ||
| 567 | .enable = s3c64xx_sclk_ctrl, | ||
| 568 | .set_parent = s3c64xx_setparent_clksrc, | ||
| 569 | .get_rate = s3c64xx_getrate_clksrc, | ||
| 570 | .set_rate = s3c64xx_setrate_clksrc, | ||
| 571 | .round_rate = s3c64xx_roundrate_clksrc, | ||
| 572 | }, | ||
| 573 | .shift = S3C6400_CLKSRC_IRDA_SHIFT, | ||
| 574 | .mask = S3C6400_CLKSRC_IRDA_MASK, | ||
| 575 | .sources = &clkset_irda, | ||
| 576 | .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT, | ||
| 577 | .reg_divider = S3C_CLK_DIV2, | ||
| 578 | }; | ||
| 579 | |||
| 580 | static struct clk *clkset_camif_list[] = { | 299 | static struct clk *clkset_camif_list[] = { |
| 581 | &clk_h2, | 300 | &clk_h2, |
| 582 | }; | 301 | }; |
| 583 | 302 | ||
| 584 | static struct clk_sources clkset_camif = { | 303 | static struct clksrc_sources clkset_camif = { |
| 585 | .sources = clkset_camif_list, | 304 | .sources = clkset_camif_list, |
| 586 | .nr_sources = ARRAY_SIZE(clkset_camif_list), | 305 | .nr_sources = ARRAY_SIZE(clkset_camif_list), |
| 587 | }; | 306 | }; |
| 588 | 307 | ||
| 589 | static struct clksrc_clk clk_camif = { | 308 | static struct clksrc_clk clksrcs[] = { |
| 590 | .clk = { | 309 | { |
| 591 | .name = "camera", | 310 | .clk = { |
| 592 | .id = -1, | 311 | .name = "mmc_bus", |
| 593 | .ctrlbit = S3C_CLKCON_SCLK_CAM, | 312 | .id = 0, |
| 594 | .enable = s3c64xx_sclk_ctrl, | 313 | .ctrlbit = S3C_CLKCON_SCLK_MMC0, |
| 595 | .set_parent = s3c64xx_setparent_clksrc, | 314 | .enable = s3c64xx_sclk_ctrl, |
| 596 | .get_rate = s3c64xx_getrate_clksrc, | 315 | }, |
| 597 | .set_rate = s3c64xx_setrate_clksrc, | 316 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 }, |
| 598 | .round_rate = s3c64xx_roundrate_clksrc, | 317 | .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 }, |
| 318 | .sources = &clkset_spi_mmc, | ||
| 319 | }, { | ||
| 320 | .clk = { | ||
| 321 | .name = "mmc_bus", | ||
| 322 | .id = 1, | ||
| 323 | .ctrlbit = S3C_CLKCON_SCLK_MMC1, | ||
| 324 | .enable = s3c64xx_sclk_ctrl, | ||
| 325 | }, | ||
| 326 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 }, | ||
| 327 | .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 }, | ||
| 328 | .sources = &clkset_spi_mmc, | ||
| 329 | }, { | ||
| 330 | .clk = { | ||
| 331 | .name = "mmc_bus", | ||
| 332 | .id = 2, | ||
| 333 | .ctrlbit = S3C_CLKCON_SCLK_MMC2, | ||
| 334 | .enable = s3c64xx_sclk_ctrl, | ||
| 335 | }, | ||
| 336 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 }, | ||
| 337 | .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 }, | ||
| 338 | .sources = &clkset_spi_mmc, | ||
| 339 | }, { | ||
| 340 | .clk = { | ||
| 341 | .name = "usb-bus-host", | ||
| 342 | .id = -1, | ||
| 343 | .ctrlbit = S3C_CLKCON_SCLK_UHOST, | ||
| 344 | .enable = s3c64xx_sclk_ctrl, | ||
| 345 | }, | ||
| 346 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 }, | ||
| 347 | .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 }, | ||
| 348 | .sources = &clkset_uhost, | ||
| 349 | }, { | ||
| 350 | .clk = { | ||
| 351 | .name = "uclk1", | ||
| 352 | .id = -1, | ||
| 353 | .ctrlbit = S3C_CLKCON_SCLK_UART, | ||
| 354 | .enable = s3c64xx_sclk_ctrl, | ||
| 355 | }, | ||
| 356 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 }, | ||
| 357 | .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 }, | ||
| 358 | .sources = &clkset_uart, | ||
| 359 | }, { | ||
| 360 | /* Where does UCLK0 come from? */ | ||
| 361 | .clk = { | ||
| 362 | .name = "spi-bus", | ||
| 363 | .id = 0, | ||
| 364 | .ctrlbit = S3C_CLKCON_SCLK_SPI0, | ||
| 365 | .enable = s3c64xx_sclk_ctrl, | ||
| 366 | }, | ||
| 367 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 }, | ||
| 368 | .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 }, | ||
| 369 | .sources = &clkset_spi_mmc, | ||
| 370 | }, { | ||
| 371 | .clk = { | ||
| 372 | .name = "spi-bus", | ||
| 373 | .id = 1, | ||
| 374 | .ctrlbit = S3C_CLKCON_SCLK_SPI1, | ||
| 375 | .enable = s3c64xx_sclk_ctrl, | ||
| 376 | }, | ||
| 377 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, | ||
| 378 | .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 }, | ||
| 379 | .sources = &clkset_spi_mmc, | ||
| 380 | }, { | ||
| 381 | .clk = { | ||
| 382 | .name = "audio-bus", | ||
| 383 | .id = 0, | ||
| 384 | .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, | ||
| 385 | .enable = s3c64xx_sclk_ctrl, | ||
| 386 | }, | ||
| 387 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 }, | ||
| 388 | .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 }, | ||
| 389 | .sources = &clkset_audio0, | ||
| 390 | }, { | ||
| 391 | .clk = { | ||
| 392 | .name = "audio-bus", | ||
| 393 | .id = 1, | ||
| 394 | .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, | ||
| 395 | .enable = s3c64xx_sclk_ctrl, | ||
| 396 | }, | ||
| 397 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 }, | ||
| 398 | .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 }, | ||
| 399 | .sources = &clkset_audio1, | ||
| 400 | }, { | ||
| 401 | .clk = { | ||
| 402 | .name = "irda-bus", | ||
| 403 | .id = 0, | ||
| 404 | .ctrlbit = S3C_CLKCON_SCLK_IRDA, | ||
| 405 | .enable = s3c64xx_sclk_ctrl, | ||
| 406 | }, | ||
| 407 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 }, | ||
| 408 | .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 }, | ||
| 409 | .sources = &clkset_irda, | ||
| 410 | }, { | ||
| 411 | .clk = { | ||
| 412 | .name = "camera", | ||
| 413 | .id = -1, | ||
| 414 | .ctrlbit = S3C_CLKCON_SCLK_CAM, | ||
| 415 | .enable = s3c64xx_sclk_ctrl, | ||
| 416 | }, | ||
| 417 | .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 }, | ||
| 418 | .reg_src = { .reg = NULL, .shift = 0, .size = 0 }, | ||
| 419 | .sources = &clkset_camif, | ||
| 599 | }, | 420 | }, |
| 600 | .shift = 0, | ||
| 601 | .mask = 0, | ||
| 602 | .sources = &clkset_camif, | ||
| 603 | .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT, | ||
| 604 | .reg_divider = S3C_CLK_DIV0, | ||
| 605 | }; | 421 | }; |
| 606 | 422 | ||
| 607 | /* Clock initialisation code */ | 423 | /* Clock initialisation code */ |
| @@ -610,39 +426,7 @@ static struct clksrc_clk *init_parents[] = { | |||
| 610 | &clk_mout_apll, | 426 | &clk_mout_apll, |
| 611 | &clk_mout_epll, | 427 | &clk_mout_epll, |
| 612 | &clk_mout_mpll, | 428 | &clk_mout_mpll, |
| 613 | &clk_mmc0, | 429 | }; |
| 614 | &clk_mmc1, | ||
| 615 | &clk_mmc2, | ||
| 616 | &clk_usbhost, | ||
| 617 | &clk_uart_uclk1, | ||
| 618 | &clk_spi0, | ||
| 619 | &clk_spi1, | ||
| 620 | &clk_audio0, | ||
| 621 | &clk_audio1, | ||
| 622 | &clk_irda, | ||
| 623 | &clk_camif, | ||
| 624 | }; | ||
| 625 | |||
| 626 | static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk) | ||
| 627 | { | ||
| 628 | struct clk_sources *srcs = clk->sources; | ||
| 629 | u32 clksrc = __raw_readl(S3C_CLK_SRC); | ||
| 630 | |||
| 631 | clksrc &= clk->mask; | ||
| 632 | clksrc >>= clk->shift; | ||
| 633 | |||
| 634 | if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { | ||
| 635 | printk(KERN_ERR "%s: bad source %d\n", | ||
| 636 | clk->clk.name, clksrc); | ||
| 637 | return; | ||
| 638 | } | ||
| 639 | |||
| 640 | clk->clk.parent = srcs->sources[clksrc]; | ||
| 641 | |||
| 642 | printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", | ||
| 643 | clk->clk.name, clk->clk.parent->name, clksrc, | ||
| 644 | clk_get_rate(&clk->clk)); | ||
| 645 | } | ||
| 646 | 430 | ||
| 647 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) | 431 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) |
| 648 | 432 | ||
| @@ -702,7 +486,10 @@ void __init_or_cpufreq s3c6400_setup_clocks(void) | |||
| 702 | clk_f.rate = fclk; | 486 | clk_f.rate = fclk; |
| 703 | 487 | ||
| 704 | for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) | 488 | for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) |
| 705 | s3c6400_set_clksrc(init_parents[ptr]); | 489 | s3c_set_clksrc(init_parents[ptr], true); |
| 490 | |||
| 491 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | ||
| 492 | s3c_set_clksrc(&clksrcs[ptr], true); | ||
| 706 | } | 493 | } |
| 707 | 494 | ||
| 708 | static struct clk *clks[] __initdata = { | 495 | static struct clk *clks[] __initdata = { |
| @@ -713,17 +500,6 @@ static struct clk *clks[] __initdata = { | |||
| 713 | &clk_mout_epll.clk, | 500 | &clk_mout_epll.clk, |
| 714 | &clk_mout_mpll.clk, | 501 | &clk_mout_mpll.clk, |
| 715 | &clk_dout_mpll, | 502 | &clk_dout_mpll, |
| 716 | &clk_mmc0.clk, | ||
| 717 | &clk_mmc1.clk, | ||
| 718 | &clk_mmc2.clk, | ||
| 719 | &clk_usbhost.clk, | ||
| 720 | &clk_uart_uclk1.clk, | ||
| 721 | &clk_spi0.clk, | ||
| 722 | &clk_spi1.clk, | ||
| 723 | &clk_audio0.clk, | ||
| 724 | &clk_audio1.clk, | ||
| 725 | &clk_irda.clk, | ||
| 726 | &clk_camif.clk, | ||
| 727 | &clk_arm, | 503 | &clk_arm, |
| 728 | }; | 504 | }; |
| 729 | 505 | ||
| @@ -755,4 +531,6 @@ void __init s3c6400_register_clocks(unsigned armclk_divlimit) | |||
| 755 | clkp->name, ret); | 531 | clkp->name, ret); |
| 756 | } | 532 | } |
| 757 | } | 533 | } |
| 534 | |||
| 535 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | ||
| 758 | } | 536 | } |
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig new file mode 100644 index 000000000000..e7c31e7060e5 --- /dev/null +++ b/arch/arm/plat-s5p/Kconfig | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | # arch/arm/plat-s5p/Kconfig | ||
| 2 | # | ||
| 3 | # Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | # http://www.samsung.com/ | ||
| 5 | # | ||
| 6 | # Licensed under GPLv2 | ||
| 7 | |||
| 8 | config PLAT_S5P | ||
| 9 | bool | ||
| 10 | depends on ARCH_S5P6440 | ||
| 11 | default y | ||
| 12 | select PLAT_S3C | ||
| 13 | select ARM_VIC | ||
| 14 | select NO_IOPORT | ||
| 15 | select ARCH_REQUIRE_GPIOLIB | ||
| 16 | select S3C_GPIO_TRACK | ||
| 17 | select SAMSUNG_GPIOLIB_4BIT | ||
| 18 | select S3C_GPIO_CFG_S3C64XX | ||
| 19 | select S3C_GPIO_PULL_UPDOWN | ||
| 20 | select S3C_GPIO_CFG_S3C24XX | ||
| 21 | select PLAT_SAMSUNG | ||
| 22 | select SAMSUNG_CLKSRC | ||
| 23 | select SAMSUNG_IRQ_VIC_TIMER | ||
| 24 | select SAMSUNG_IRQ_UART | ||
| 25 | help | ||
| 26 | Base platform code for Samsung's S5P series SoC. | ||
| 27 | |||
| 28 | if (PLAT_S5P && ARCH_S5P6440) | ||
| 29 | |||
| 30 | # Configuration options shared by all S5P64XX implementations | ||
| 31 | |||
| 32 | config CPU_S5P6440_INIT | ||
| 33 | bool | ||
| 34 | help | ||
| 35 | Initialisation code for the S5P6440. | ||
| 36 | |||
| 37 | config CPU_S5P6440_CLOCK | ||
| 38 | bool | ||
| 39 | help | ||
| 40 | Clock support code for the S5P6440. | ||
| 41 | |||
| 42 | endif | ||
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile new file mode 100644 index 000000000000..92b647450542 --- /dev/null +++ b/arch/arm/plat-s5p/Makefile | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | # arch/arm/plat-s5p/Makefile | ||
| 2 | # | ||
| 3 | # Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | # http://www.samsung.com/ | ||
| 5 | # | ||
| 6 | # Licensed under GPLv2 | ||
| 7 | |||
| 8 | obj-y := | ||
| 9 | obj-m := | ||
| 10 | obj-n := dummy.o | ||
| 11 | obj- := | ||
| 12 | |||
| 13 | # Core files | ||
| 14 | |||
| 15 | obj-y += dev-uart.o | ||
| 16 | obj-y += cpu.o | ||
| 17 | obj-y += clock.o | ||
| 18 | obj-y += irq.o | ||
| 19 | obj-y += setup-i2c0.o | ||
| 20 | |||
| 21 | # CPU support | ||
| 22 | |||
| 23 | obj-$(CONFIG_CPU_S5P6440_INIT) += s5p6440-init.o | ||
| 24 | obj-$(CONFIG_CPU_S5P6440_CLOCK) += s5p6440-clock.o | ||
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c new file mode 100644 index 000000000000..3d3c0f1934fc --- /dev/null +++ b/arch/arm/plat-s5p/clock.c | |||
| @@ -0,0 +1,136 @@ | |||
| 1 | /* linux/arch/arm/plat-s5p/clock.c | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P - Common clock support | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/module.h> | ||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/list.h> | ||
| 17 | #include <linux/errno.h> | ||
| 18 | #include <linux/err.h> | ||
| 19 | #include <linux/clk.h> | ||
| 20 | #include <linux/sysdev.h> | ||
| 21 | #include <linux/io.h> | ||
| 22 | #include <asm/div64.h> | ||
| 23 | |||
| 24 | #include <plat/clock.h> | ||
| 25 | #include <plat/clock-clksrc.h> | ||
| 26 | #include <plat/s5p-clock.h> | ||
| 27 | |||
| 28 | /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call | ||
| 29 | * clk_ext_xtal_mux. | ||
| 30 | */ | ||
| 31 | struct clk clk_ext_xtal_mux = { | ||
| 32 | .name = "ext_xtal", | ||
| 33 | .id = -1, | ||
| 34 | }; | ||
| 35 | |||
| 36 | /* 48MHz USB Phy clock output */ | ||
| 37 | struct clk clk_48m = { | ||
| 38 | .name = "clk_48m", | ||
| 39 | .id = -1, | ||
| 40 | .rate = 48000000, | ||
| 41 | }; | ||
| 42 | |||
| 43 | /* APLL clock output | ||
| 44 | * No need .ctrlbit, this is always on | ||
| 45 | */ | ||
| 46 | struct clk clk_fout_apll = { | ||
| 47 | .name = "fout_apll", | ||
| 48 | .id = -1, | ||
| 49 | }; | ||
| 50 | |||
| 51 | /* MPLL clock output | ||
| 52 | * No need .ctrlbit, this is always on | ||
| 53 | */ | ||
| 54 | struct clk clk_fout_mpll = { | ||
| 55 | .name = "fout_mpll", | ||
| 56 | .id = -1, | ||
| 57 | }; | ||
| 58 | |||
| 59 | /* EPLL clock output */ | ||
| 60 | struct clk clk_fout_epll = { | ||
| 61 | .name = "fout_epll", | ||
| 62 | .id = -1, | ||
| 63 | .ctrlbit = (1 << 31), | ||
| 64 | }; | ||
| 65 | |||
| 66 | /* ARM clock */ | ||
| 67 | struct clk clk_arm = { | ||
| 68 | .name = "armclk", | ||
| 69 | .id = -1, | ||
| 70 | .rate = 0, | ||
| 71 | .ctrlbit = 0, | ||
| 72 | }; | ||
| 73 | |||
| 74 | /* Possible clock sources for APLL Mux */ | ||
| 75 | static struct clk *clk_src_apll_list[] = { | ||
| 76 | [0] = &clk_fin_apll, | ||
| 77 | [1] = &clk_fout_apll, | ||
| 78 | }; | ||
| 79 | |||
| 80 | struct clksrc_sources clk_src_apll = { | ||
| 81 | .sources = clk_src_apll_list, | ||
| 82 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), | ||
| 83 | }; | ||
| 84 | |||
| 85 | /* Possible clock sources for MPLL Mux */ | ||
| 86 | static struct clk *clk_src_mpll_list[] = { | ||
| 87 | [0] = &clk_fin_mpll, | ||
| 88 | [1] = &clk_fout_mpll, | ||
| 89 | }; | ||
| 90 | |||
| 91 | struct clksrc_sources clk_src_mpll = { | ||
| 92 | .sources = clk_src_mpll_list, | ||
| 93 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), | ||
| 94 | }; | ||
| 95 | |||
| 96 | /* Possible clock sources for EPLL Mux */ | ||
| 97 | static struct clk *clk_src_epll_list[] = { | ||
| 98 | [0] = &clk_fin_epll, | ||
| 99 | [1] = &clk_fout_epll, | ||
| 100 | }; | ||
| 101 | |||
| 102 | struct clksrc_sources clk_src_epll = { | ||
| 103 | .sources = clk_src_epll_list, | ||
| 104 | .nr_sources = ARRAY_SIZE(clk_src_epll_list), | ||
| 105 | }; | ||
| 106 | |||
| 107 | int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable) | ||
| 108 | { | ||
| 109 | unsigned int ctrlbit = clk->ctrlbit; | ||
| 110 | u32 con; | ||
| 111 | |||
| 112 | con = __raw_readl(reg); | ||
| 113 | con = enable ? (con | ctrlbit) : (con & ~ctrlbit); | ||
| 114 | __raw_writel(con, reg); | ||
| 115 | return 0; | ||
| 116 | } | ||
| 117 | |||
| 118 | static struct clk *s5p_clks[] __initdata = { | ||
| 119 | &clk_ext_xtal_mux, | ||
| 120 | &clk_48m, | ||
| 121 | &clk_fout_apll, | ||
| 122 | &clk_fout_mpll, | ||
| 123 | &clk_fout_epll, | ||
| 124 | &clk_arm, | ||
| 125 | }; | ||
| 126 | |||
| 127 | void __init s5p_register_clocks(unsigned long xtal_freq) | ||
| 128 | { | ||
| 129 | int ret; | ||
| 130 | |||
| 131 | clk_ext_xtal_mux.rate = xtal_freq; | ||
| 132 | |||
| 133 | ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks)); | ||
| 134 | if (ret > 0) | ||
| 135 | printk(KERN_ERR "Failed to register s5p clocks\n"); | ||
| 136 | } | ||
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c new file mode 100644 index 000000000000..0895a77a2835 --- /dev/null +++ b/arch/arm/plat-s5p/cpu.c | |||
| @@ -0,0 +1,90 @@ | |||
| 1 | /* linux/arch/arm/plat-s5p/cpu.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P CPU Support | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/module.h> | ||
| 15 | #include <mach/map.h> | ||
| 16 | #include <asm/mach/arch.h> | ||
| 17 | #include <asm/mach/map.h> | ||
| 18 | #include <mach/regs-clock.h> | ||
| 19 | #include <plat/cpu.h> | ||
| 20 | #include <plat/s5p6440.h> | ||
| 21 | |||
| 22 | /* table of supported CPUs */ | ||
| 23 | |||
| 24 | static const char name_s5p6440[] = "S5P6440"; | ||
| 25 | |||
| 26 | static struct cpu_table cpu_ids[] __initdata = { | ||
| 27 | { | ||
| 28 | .idcode = 0x56440100, | ||
| 29 | .idmask = 0xffffff00, | ||
| 30 | .map_io = s5p6440_map_io, | ||
| 31 | .init_clocks = s5p6440_init_clocks, | ||
| 32 | .init_uarts = s5p6440_init_uarts, | ||
| 33 | .init = s5p6440_init, | ||
| 34 | .name = name_s5p6440, | ||
| 35 | }, | ||
| 36 | }; | ||
| 37 | |||
| 38 | /* minimal IO mapping */ | ||
| 39 | |||
| 40 | #define UART_OFFS (S5P_PA_UART & 0xfffff) | ||
| 41 | |||
| 42 | static struct map_desc s5p_iodesc[] __initdata = { | ||
| 43 | { | ||
| 44 | .virtual = (unsigned long)S5P_VA_SYSCON, | ||
| 45 | .pfn = __phys_to_pfn(S5P_PA_SYSCON), | ||
| 46 | .length = SZ_64K, | ||
| 47 | .type = MT_DEVICE, | ||
| 48 | }, { | ||
| 49 | .virtual = (unsigned long)(S5P_VA_UART + UART_OFFS), | ||
| 50 | .pfn = __phys_to_pfn(S5P_PA_UART), | ||
| 51 | .length = SZ_4K, | ||
| 52 | .type = MT_DEVICE, | ||
| 53 | }, { | ||
| 54 | .virtual = (unsigned long)S5P_VA_VIC0, | ||
| 55 | .pfn = __phys_to_pfn(S5P_PA_VIC0), | ||
| 56 | .length = SZ_16K, | ||
| 57 | .type = MT_DEVICE, | ||
| 58 | }, { | ||
| 59 | .virtual = (unsigned long)S5P_VA_VIC1, | ||
| 60 | .pfn = __phys_to_pfn(S5P_PA_VIC1), | ||
| 61 | .length = SZ_16K, | ||
| 62 | .type = MT_DEVICE, | ||
| 63 | }, { | ||
| 64 | .virtual = (unsigned long)S5P_VA_TIMER, | ||
| 65 | .pfn = __phys_to_pfn(S5P_PA_TIMER), | ||
| 66 | .length = SZ_16K, | ||
| 67 | .type = MT_DEVICE, | ||
| 68 | }, { | ||
| 69 | .virtual = (unsigned long)S5P_VA_GPIO, | ||
| 70 | .pfn = __phys_to_pfn(S5P_PA_GPIO), | ||
| 71 | .length = SZ_4K, | ||
| 72 | .type = MT_DEVICE, | ||
| 73 | }, | ||
| 74 | }; | ||
| 75 | |||
| 76 | /* read cpu identification code */ | ||
| 77 | |||
| 78 | void __init s5p_init_io(struct map_desc *mach_desc, | ||
| 79 | int size, void __iomem *cpuid_addr) | ||
| 80 | { | ||
| 81 | unsigned long idcode; | ||
| 82 | |||
| 83 | /* initialize the io descriptors we need for initialization */ | ||
| 84 | iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc)); | ||
| 85 | if (mach_desc) | ||
| 86 | iotable_init(mach_desc, size); | ||
| 87 | |||
| 88 | idcode = __raw_readl(cpuid_addr); | ||
| 89 | s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); | ||
| 90 | } | ||
diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c new file mode 100644 index 000000000000..23c75316d491 --- /dev/null +++ b/arch/arm/plat-s5p/dev-uart.c | |||
| @@ -0,0 +1,137 @@ | |||
| 1 | /* linux/arch/arm/plat-s5p/dev-uart.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * Base S5P UART resource and device definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/types.h> | ||
| 15 | #include <linux/interrupt.h> | ||
| 16 | #include <linux/list.h> | ||
| 17 | #include <linux/platform_device.h> | ||
| 18 | |||
| 19 | #include <asm/mach/arch.h> | ||
| 20 | #include <asm/mach/irq.h> | ||
| 21 | #include <mach/hardware.h> | ||
| 22 | #include <mach/map.h> | ||
| 23 | |||
| 24 | #include <plat/devs.h> | ||
| 25 | |||
| 26 | /* Serial port registrations */ | ||
| 27 | |||
| 28 | static struct resource s5p_uart0_resource[] = { | ||
| 29 | [0] = { | ||
| 30 | .start = S5P_PA_UART0, | ||
| 31 | .end = S5P_PA_UART0 + S5P_SZ_UART, | ||
| 32 | .flags = IORESOURCE_MEM, | ||
| 33 | }, | ||
| 34 | [1] = { | ||
| 35 | .start = IRQ_S5P_UART_RX0, | ||
| 36 | .end = IRQ_S5P_UART_RX0, | ||
| 37 | .flags = IORESOURCE_IRQ, | ||
| 38 | }, | ||
| 39 | [2] = { | ||
| 40 | .start = IRQ_S5P_UART_TX0, | ||
| 41 | .end = IRQ_S5P_UART_TX0, | ||
| 42 | .flags = IORESOURCE_IRQ, | ||
| 43 | }, | ||
| 44 | [3] = { | ||
| 45 | .start = IRQ_S5P_UART_ERR0, | ||
| 46 | .end = IRQ_S5P_UART_ERR0, | ||
| 47 | .flags = IORESOURCE_IRQ, | ||
| 48 | } | ||
| 49 | }; | ||
| 50 | |||
| 51 | static struct resource s5p_uart1_resource[] = { | ||
| 52 | [0] = { | ||
| 53 | .start = S5P_PA_UART1, | ||
| 54 | .end = S5P_PA_UART1 + S5P_SZ_UART, | ||
| 55 | .flags = IORESOURCE_MEM, | ||
| 56 | }, | ||
| 57 | [1] = { | ||
| 58 | .start = IRQ_S5P_UART_RX1, | ||
| 59 | .end = IRQ_S5P_UART_RX1, | ||
| 60 | .flags = IORESOURCE_IRQ, | ||
| 61 | }, | ||
| 62 | [2] = { | ||
| 63 | .start = IRQ_S5P_UART_TX1, | ||
| 64 | .end = IRQ_S5P_UART_TX1, | ||
| 65 | .flags = IORESOURCE_IRQ, | ||
| 66 | }, | ||
| 67 | [3] = { | ||
| 68 | .start = IRQ_S5P_UART_ERR1, | ||
| 69 | .end = IRQ_S5P_UART_ERR1, | ||
| 70 | .flags = IORESOURCE_IRQ, | ||
| 71 | }, | ||
| 72 | }; | ||
| 73 | |||
| 74 | static struct resource s5p_uart2_resource[] = { | ||
| 75 | [0] = { | ||
| 76 | .start = S5P_PA_UART2, | ||
| 77 | .end = S5P_PA_UART2 + S5P_SZ_UART, | ||
| 78 | .flags = IORESOURCE_MEM, | ||
| 79 | }, | ||
| 80 | [1] = { | ||
| 81 | .start = IRQ_S5P_UART_RX2, | ||
| 82 | .end = IRQ_S5P_UART_RX2, | ||
| 83 | .flags = IORESOURCE_IRQ, | ||
| 84 | }, | ||
| 85 | [2] = { | ||
| 86 | .start = IRQ_S5P_UART_TX2, | ||
| 87 | .end = IRQ_S5P_UART_TX2, | ||
| 88 | .flags = IORESOURCE_IRQ, | ||
| 89 | }, | ||
| 90 | [3] = { | ||
| 91 | .start = IRQ_S5P_UART_ERR2, | ||
| 92 | .end = IRQ_S5P_UART_ERR2, | ||
| 93 | .flags = IORESOURCE_IRQ, | ||
| 94 | }, | ||
| 95 | }; | ||
| 96 | |||
| 97 | static struct resource s5p_uart3_resource[] = { | ||
| 98 | [0] = { | ||
| 99 | .start = S5P_PA_UART3, | ||
| 100 | .end = S5P_PA_UART3 + S5P_SZ_UART, | ||
| 101 | .flags = IORESOURCE_MEM, | ||
| 102 | }, | ||
| 103 | [1] = { | ||
| 104 | .start = IRQ_S5P_UART_RX3, | ||
| 105 | .end = IRQ_S5P_UART_RX3, | ||
| 106 | .flags = IORESOURCE_IRQ, | ||
| 107 | }, | ||
| 108 | [2] = { | ||
| 109 | .start = IRQ_S5P_UART_TX3, | ||
| 110 | .end = IRQ_S5P_UART_TX3, | ||
| 111 | .flags = IORESOURCE_IRQ, | ||
| 112 | }, | ||
| 113 | [3] = { | ||
| 114 | .start = IRQ_S5P_UART_ERR3, | ||
| 115 | .end = IRQ_S5P_UART_ERR3, | ||
| 116 | .flags = IORESOURCE_IRQ, | ||
| 117 | }, | ||
| 118 | }; | ||
| 119 | |||
| 120 | struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = { | ||
| 121 | [0] = { | ||
| 122 | .resources = s5p_uart0_resource, | ||
| 123 | .nr_resources = ARRAY_SIZE(s5p_uart0_resource), | ||
| 124 | }, | ||
| 125 | [1] = { | ||
| 126 | .resources = s5p_uart1_resource, | ||
| 127 | .nr_resources = ARRAY_SIZE(s5p_uart1_resource), | ||
| 128 | }, | ||
| 129 | [2] = { | ||
| 130 | .resources = s5p_uart2_resource, | ||
| 131 | .nr_resources = ARRAY_SIZE(s5p_uart2_resource), | ||
| 132 | }, | ||
| 133 | [3] = { | ||
| 134 | .resources = s5p_uart3_resource, | ||
| 135 | .nr_resources = ARRAY_SIZE(s5p_uart3_resource), | ||
| 136 | }, | ||
| 137 | }; | ||
diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h new file mode 100644 index 000000000000..5d7937dddad2 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/irqs.h | |||
| @@ -0,0 +1,83 @@ | |||
| 1 | /* linux/arch/arm/plat-s5p/include/plat/irqs.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P Common IRQ support | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_PLAT_S5P_IRQS_H | ||
| 14 | #define __ASM_PLAT_S5P_IRQS_H __FILE__ | ||
| 15 | |||
| 16 | /* we keep the first set of CPU IRQs out of the range of | ||
| 17 | * the ISA space, so that the PC104 has them to itself | ||
| 18 | * and we don't end up having to do horrible things to the | ||
| 19 | * standard ISA drivers.... | ||
| 20 | * | ||
| 21 | * note, since we're using the VICs, our start must be a | ||
| 22 | * mulitple of 32 to allow the common code to work | ||
| 23 | */ | ||
| 24 | |||
| 25 | #define S5P_IRQ_OFFSET (32) | ||
| 26 | |||
| 27 | #define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET) | ||
| 28 | |||
| 29 | #define S5P_VIC0_BASE S5P_IRQ(0) | ||
| 30 | #define S5P_VIC1_BASE S5P_IRQ(32) | ||
| 31 | |||
| 32 | #define IRQ_VIC0_BASE S5P_VIC0_BASE | ||
| 33 | #define IRQ_VIC1_BASE S5P_VIC1_BASE | ||
| 34 | |||
| 35 | /* UART interrupts, each UART has 4 intterupts per channel so | ||
| 36 | * use the space between the ISA and S3C main interrupts. Note, these | ||
| 37 | * are not in the same order as the S3C24XX series! */ | ||
| 38 | |||
| 39 | #define IRQ_S5P_UART_BASE0 (16) | ||
| 40 | #define IRQ_S5P_UART_BASE1 (20) | ||
| 41 | #define IRQ_S5P_UART_BASE2 (24) | ||
| 42 | #define IRQ_S5P_UART_BASE3 (28) | ||
| 43 | |||
| 44 | #define UART_IRQ_RXD (0) | ||
| 45 | #define UART_IRQ_ERR (1) | ||
| 46 | #define UART_IRQ_TXD (2) | ||
| 47 | |||
| 48 | #define IRQ_S5P_UART_RX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_RXD) | ||
| 49 | #define IRQ_S5P_UART_TX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_TXD) | ||
| 50 | #define IRQ_S5P_UART_ERR0 (IRQ_S5P_UART_BASE0 + UART_IRQ_ERR) | ||
| 51 | |||
| 52 | #define IRQ_S5P_UART_RX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_RXD) | ||
| 53 | #define IRQ_S5P_UART_TX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_TXD) | ||
| 54 | #define IRQ_S5P_UART_ERR1 (IRQ_S5P_UART_BASE1 + UART_IRQ_ERR) | ||
| 55 | |||
| 56 | #define IRQ_S5P_UART_RX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_RXD) | ||
| 57 | #define IRQ_S5P_UART_TX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_TXD) | ||
| 58 | #define IRQ_S5P_UART_ERR2 (IRQ_S5P_UART_BASE2 + UART_IRQ_ERR) | ||
| 59 | |||
| 60 | #define IRQ_S5P_UART_RX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_RXD) | ||
| 61 | #define IRQ_S5P_UART_TX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_TXD) | ||
| 62 | #define IRQ_S5P_UART_ERR3 (IRQ_S5P_UART_BASE3 + UART_IRQ_ERR) | ||
| 63 | |||
| 64 | /* S3C compatibilty defines */ | ||
| 65 | #define IRQ_S3CUART_RX0 IRQ_S5P_UART_RX0 | ||
| 66 | #define IRQ_S3CUART_RX1 IRQ_S5P_UART_RX1 | ||
| 67 | #define IRQ_S3CUART_RX2 IRQ_S5P_UART_RX2 | ||
| 68 | #define IRQ_S3CUART_RX3 IRQ_S5P_UART_RX3 | ||
| 69 | |||
| 70 | /* VIC based IRQs */ | ||
| 71 | |||
| 72 | #define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x)) | ||
| 73 | #define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x)) | ||
| 74 | |||
| 75 | #define S5P_TIMER_IRQ(x) S5P_IRQ(64 + (x)) | ||
| 76 | |||
| 77 | #define IRQ_TIMER0 S5P_TIMER_IRQ(0) | ||
| 78 | #define IRQ_TIMER1 S5P_TIMER_IRQ(1) | ||
| 79 | #define IRQ_TIMER2 S5P_TIMER_IRQ(2) | ||
| 80 | #define IRQ_TIMER3 S5P_TIMER_IRQ(3) | ||
| 81 | #define IRQ_TIMER4 S5P_TIMER_IRQ(4) | ||
| 82 | |||
| 83 | #endif /* __ASM_PLAT_S5P_IRQS_H */ | ||
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h new file mode 100644 index 000000000000..d48325bb29e2 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/pll.h | |||
| @@ -0,0 +1,83 @@ | |||
| 1 | /* arch/arm/plat-s5p/include/plat/pll.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P PLL code | ||
| 7 | * | ||
| 8 | * Based on arch/arm/plat-s3c64xx/include/plat/pll.h | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #define PLL45XX_MDIV_MASK (0x3FF) | ||
| 16 | #define PLL45XX_PDIV_MASK (0x3F) | ||
| 17 | #define PLL45XX_SDIV_MASK (0x7) | ||
| 18 | #define PLL45XX_MDIV_SHIFT (16) | ||
| 19 | #define PLL45XX_PDIV_SHIFT (8) | ||
| 20 | #define PLL45XX_SDIV_SHIFT (0) | ||
| 21 | |||
| 22 | #include <asm/div64.h> | ||
| 23 | |||
| 24 | enum pll45xx_type_t { | ||
| 25 | pll_4500, | ||
| 26 | pll_4502, | ||
| 27 | pll_4508 | ||
| 28 | }; | ||
| 29 | |||
| 30 | static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con, | ||
| 31 | enum pll45xx_type_t pll_type) | ||
| 32 | { | ||
| 33 | u32 mdiv, pdiv, sdiv; | ||
| 34 | u64 fvco = baseclk; | ||
| 35 | |||
| 36 | mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; | ||
| 37 | pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; | ||
| 38 | sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK; | ||
| 39 | |||
| 40 | if (pll_type == pll_4508) | ||
| 41 | sdiv = sdiv - 1; | ||
| 42 | |||
| 43 | fvco *= mdiv; | ||
| 44 | do_div(fvco, (pdiv << sdiv)); | ||
| 45 | |||
| 46 | return (unsigned long)fvco; | ||
| 47 | } | ||
| 48 | |||
| 49 | #define PLL90XX_MDIV_MASK (0xFF) | ||
| 50 | #define PLL90XX_PDIV_MASK (0x3F) | ||
| 51 | #define PLL90XX_SDIV_MASK (0x7) | ||
| 52 | #define PLL90XX_KDIV_MASK (0xffff) | ||
| 53 | #define PLL90XX_MDIV_SHIFT (16) | ||
| 54 | #define PLL90XX_PDIV_SHIFT (8) | ||
| 55 | #define PLL90XX_SDIV_SHIFT (0) | ||
| 56 | #define PLL90XX_KDIV_SHIFT (0) | ||
| 57 | |||
| 58 | static inline unsigned long s5p_get_pll90xx(unsigned long baseclk, | ||
| 59 | u32 pll_con, u32 pll_conk) | ||
| 60 | { | ||
| 61 | unsigned long result; | ||
| 62 | u32 mdiv, pdiv, sdiv, kdiv; | ||
| 63 | u64 tmp; | ||
| 64 | |||
| 65 | mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK; | ||
| 66 | pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK; | ||
| 67 | sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK; | ||
| 68 | kdiv = pll_conk & PLL90XX_KDIV_MASK; | ||
| 69 | |||
| 70 | /* We need to multiple baseclk by mdiv (the integer part) and kdiv | ||
| 71 | * which is in 2^16ths, so shift mdiv up (does not overflow) and | ||
| 72 | * add kdiv before multiplying. The use of tmp is to avoid any | ||
| 73 | * overflows before shifting bac down into result when multipling | ||
| 74 | * by the mdiv and kdiv pair. | ||
| 75 | */ | ||
| 76 | |||
| 77 | tmp = baseclk; | ||
| 78 | tmp *= (mdiv << 16) + kdiv; | ||
| 79 | do_div(tmp, (pdiv << sdiv)); | ||
| 80 | result = tmp >> 16; | ||
| 81 | |||
| 82 | return result; | ||
| 83 | } | ||
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h new file mode 100644 index 000000000000..e1a7444b8829 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h | |||
| @@ -0,0 +1,38 @@ | |||
| 1 | /* linux/arch/arm/plat-s5p/include/plat/s5p-clock.h | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * Header file for s5p clock support | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_PLAT_S5P_CLOCK_H | ||
| 14 | #define __ASM_PLAT_S5P_CLOCK_H __FILE__ | ||
| 15 | |||
| 16 | #include <linux/clk.h> | ||
| 17 | |||
| 18 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) | ||
| 19 | |||
| 20 | #define clk_fin_apll clk_ext_xtal_mux | ||
| 21 | #define clk_fin_mpll clk_ext_xtal_mux | ||
| 22 | #define clk_fin_epll clk_ext_xtal_mux | ||
| 23 | |||
| 24 | extern struct clk clk_ext_xtal_mux; | ||
| 25 | extern struct clk clk_48m; | ||
| 26 | extern struct clk clk_fout_apll; | ||
| 27 | extern struct clk clk_fout_mpll; | ||
| 28 | extern struct clk clk_fout_epll; | ||
| 29 | extern struct clk clk_arm; | ||
| 30 | |||
| 31 | extern struct clksrc_sources clk_src_apll; | ||
| 32 | extern struct clksrc_sources clk_src_mpll; | ||
| 33 | extern struct clksrc_sources clk_src_epll; | ||
| 34 | |||
| 35 | extern int s5p6440_clk48m_ctrl(struct clk *clk, int enable); | ||
| 36 | extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable); | ||
| 37 | |||
| 38 | #endif /* __ASM_PLAT_S5P_CLOCK_H */ | ||
diff --git a/arch/arm/plat-s5p/include/plat/s5p6440.h b/arch/arm/plat-s5p/include/plat/s5p6440.h new file mode 100644 index 000000000000..a4cd75afeb3b --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5p6440.h | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | /* arch/arm/plat-s5p/include/plat/s5p6440.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * Header file for s5p6440 cpu support | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* Common init code for S5P6440 related SoCs */ | ||
| 14 | |||
| 15 | extern void s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
| 16 | extern void s5p6440_register_clocks(void); | ||
| 17 | extern void s5p6440_setup_clocks(void); | ||
| 18 | |||
| 19 | #ifdef CONFIG_CPU_S5P6440 | ||
| 20 | |||
| 21 | extern int s5p6440_init(void); | ||
| 22 | extern void s5p6440_init_irq(void); | ||
| 23 | extern void s5p6440_map_io(void); | ||
| 24 | extern void s5p6440_init_clocks(int xtal); | ||
| 25 | |||
| 26 | #define s5p6440_init_uarts s5p6440_common_init_uarts | ||
| 27 | |||
| 28 | #else | ||
| 29 | #define s5p6440_init_clocks NULL | ||
| 30 | #define s5p6440_init_uarts NULL | ||
| 31 | #define s5p6440_map_io NULL | ||
| 32 | #define s5p6440_init NULL | ||
| 33 | #endif | ||
| 34 | |||
| 35 | /* S5P6440 timer */ | ||
| 36 | |||
| 37 | extern struct sys_timer s5p6440_timer; | ||
diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c new file mode 100644 index 000000000000..eada40d0847d --- /dev/null +++ b/arch/arm/plat-s5p/irq.c | |||
| @@ -0,0 +1,73 @@ | |||
| 1 | /* arch/arm/plat-s5p/irq.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P - Interrupt handling | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/interrupt.h> | ||
| 15 | #include <linux/irq.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | |||
| 18 | #include <asm/hardware/vic.h> | ||
| 19 | |||
| 20 | #include <linux/serial_core.h> | ||
| 21 | #include <mach/map.h> | ||
| 22 | #include <plat/regs-timer.h> | ||
| 23 | #include <plat/regs-serial.h> | ||
| 24 | #include <plat/cpu.h> | ||
| 25 | #include <plat/irq-vic-timer.h> | ||
| 26 | #include <plat/irq-uart.h> | ||
| 27 | |||
| 28 | #define VIC_VAADDR(no) (S5P_VA_VIC0 + ((no)*0x10000)) | ||
| 29 | #define VIC_BASE(no) (S5P_VIC0_BASE + ((no)*32)) | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] | ||
| 33 | * are consecutive when looking up the interrupt in the demux routines. | ||
| 34 | */ | ||
| 35 | static struct s3c_uart_irq uart_irqs[] = { | ||
| 36 | [0] = { | ||
| 37 | .regs = S5P_VA_UART0, | ||
| 38 | .base_irq = IRQ_S5P_UART_BASE0, | ||
| 39 | .parent_irq = IRQ_UART0, | ||
| 40 | }, | ||
| 41 | [1] = { | ||
| 42 | .regs = S5P_VA_UART1, | ||
| 43 | .base_irq = IRQ_S5P_UART_BASE1, | ||
| 44 | .parent_irq = IRQ_UART1, | ||
| 45 | }, | ||
| 46 | [2] = { | ||
| 47 | .regs = S5P_VA_UART2, | ||
| 48 | .base_irq = IRQ_S5P_UART_BASE2, | ||
| 49 | .parent_irq = IRQ_UART2, | ||
| 50 | }, | ||
| 51 | [3] = { | ||
| 52 | .regs = S5P_VA_UART3, | ||
| 53 | .base_irq = IRQ_S5P_UART_BASE3, | ||
| 54 | .parent_irq = IRQ_UART3, | ||
| 55 | }, | ||
| 56 | }; | ||
| 57 | |||
| 58 | void __init s5p_init_irq(u32 *vic, u32 num_vic) | ||
| 59 | { | ||
| 60 | int irq; | ||
| 61 | |||
| 62 | /* initialize the VICs */ | ||
| 63 | for (irq = 0; irq < num_vic; irq++) | ||
| 64 | vic_init(VIC_VAADDR(irq), VIC_BASE(irq), vic[irq], 0); | ||
| 65 | |||
| 66 | s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); | ||
| 67 | s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); | ||
| 68 | s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); | ||
| 69 | s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); | ||
| 70 | s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); | ||
| 71 | |||
| 72 | s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); | ||
| 73 | } | ||
diff --git a/arch/arm/plat-s5p/s5p6440-clock.c b/arch/arm/plat-s5p/s5p6440-clock.c new file mode 100644 index 000000000000..2f412f8c1212 --- /dev/null +++ b/arch/arm/plat-s5p/s5p6440-clock.c | |||
| @@ -0,0 +1,698 @@ | |||
| 1 | /* linux/arch/arm/plat-s5p/s5p6440-clock.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5P6440 - Clock support | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/module.h> | ||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/list.h> | ||
| 17 | #include <linux/errno.h> | ||
| 18 | #include <linux/err.h> | ||
| 19 | #include <linux/clk.h> | ||
| 20 | #include <linux/sysdev.h> | ||
| 21 | #include <linux/io.h> | ||
| 22 | |||
| 23 | #include <mach/hardware.h> | ||
| 24 | #include <mach/map.h> | ||
| 25 | |||
| 26 | #include <plat/cpu-freq.h> | ||
| 27 | #include <mach/regs-clock.h> | ||
| 28 | #include <plat/clock.h> | ||
| 29 | #include <plat/cpu.h> | ||
| 30 | #include <plat/clock-clksrc.h> | ||
| 31 | #include <plat/s5p-clock.h> | ||
| 32 | #include <plat/pll.h> | ||
| 33 | #include <plat/s5p6440.h> | ||
| 34 | |||
| 35 | /* APLL Mux output clock */ | ||
| 36 | static struct clksrc_clk clk_mout_apll = { | ||
| 37 | .clk = { | ||
| 38 | .name = "mout_apll", | ||
| 39 | .id = -1, | ||
| 40 | }, | ||
| 41 | .sources = &clk_src_apll, | ||
| 42 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, | ||
| 43 | }; | ||
| 44 | |||
| 45 | static int s5p6440_epll_enable(struct clk *clk, int enable) | ||
| 46 | { | ||
| 47 | unsigned int ctrlbit = clk->ctrlbit; | ||
| 48 | unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit; | ||
| 49 | |||
| 50 | if (enable) | ||
| 51 | __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON); | ||
| 52 | else | ||
| 53 | __raw_writel(epll_con, S5P_EPLL_CON); | ||
| 54 | |||
| 55 | return 0; | ||
| 56 | } | ||
| 57 | |||
| 58 | static unsigned long s5p6440_epll_get_rate(struct clk *clk) | ||
| 59 | { | ||
| 60 | return clk->rate; | ||
| 61 | } | ||
| 62 | |||
| 63 | static u32 epll_div[][5] = { | ||
| 64 | { 36000000, 0, 48, 1, 4 }, | ||
| 65 | { 48000000, 0, 32, 1, 3 }, | ||
| 66 | { 60000000, 0, 40, 1, 3 }, | ||
| 67 | { 72000000, 0, 48, 1, 3 }, | ||
| 68 | { 84000000, 0, 28, 1, 2 }, | ||
| 69 | { 96000000, 0, 32, 1, 2 }, | ||
| 70 | { 32768000, 45264, 43, 1, 4 }, | ||
| 71 | { 45158000, 6903, 30, 1, 3 }, | ||
| 72 | { 49152000, 50332, 32, 1, 3 }, | ||
| 73 | { 67738000, 10398, 45, 1, 3 }, | ||
| 74 | { 73728000, 9961, 49, 1, 3 } | ||
| 75 | }; | ||
| 76 | |||
| 77 | static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate) | ||
| 78 | { | ||
| 79 | unsigned int epll_con, epll_con_k; | ||
| 80 | unsigned int i; | ||
| 81 | |||
| 82 | if (clk->rate == rate) /* Return if nothing changed */ | ||
| 83 | return 0; | ||
| 84 | |||
| 85 | epll_con = __raw_readl(S5P_EPLL_CON); | ||
| 86 | epll_con_k = __raw_readl(S5P_EPLL_CON_K); | ||
| 87 | |||
| 88 | epll_con_k &= ~(PLL90XX_KDIV_MASK); | ||
| 89 | epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK); | ||
| 90 | |||
| 91 | for (i = 0; i < ARRAY_SIZE(epll_div); i++) { | ||
| 92 | if (epll_div[i][0] == rate) { | ||
| 93 | epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT); | ||
| 94 | epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) | | ||
| 95 | (epll_div[i][3] << PLL90XX_PDIV_SHIFT) | | ||
| 96 | (epll_div[i][4] << PLL90XX_SDIV_SHIFT); | ||
| 97 | break; | ||
| 98 | } | ||
| 99 | } | ||
| 100 | |||
| 101 | if (i == ARRAY_SIZE(epll_div)) { | ||
| 102 | printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__); | ||
| 103 | return -EINVAL; | ||
| 104 | } | ||
| 105 | |||
| 106 | __raw_writel(epll_con, S5P_EPLL_CON); | ||
| 107 | __raw_writel(epll_con_k, S5P_EPLL_CON_K); | ||
| 108 | |||
| 109 | clk->rate = rate; | ||
| 110 | |||
| 111 | return 0; | ||
| 112 | } | ||
| 113 | |||
| 114 | static struct clk_ops s5p6440_epll_ops = { | ||
| 115 | .get_rate = s5p6440_epll_get_rate, | ||
| 116 | .set_rate = s5p6440_epll_set_rate, | ||
| 117 | }; | ||
| 118 | |||
| 119 | static struct clksrc_clk clk_mout_epll = { | ||
| 120 | .clk = { | ||
| 121 | .name = "mout_epll", | ||
| 122 | .id = -1, | ||
| 123 | }, | ||
| 124 | .sources = &clk_src_epll, | ||
| 125 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 2, .size = 1 }, | ||
| 126 | }; | ||
| 127 | |||
| 128 | static struct clksrc_clk clk_mout_mpll = { | ||
| 129 | .clk = { | ||
| 130 | .name = "mout_mpll", | ||
| 131 | .id = -1, | ||
| 132 | }, | ||
| 133 | .sources = &clk_src_mpll, | ||
| 134 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 }, | ||
| 135 | }; | ||
| 136 | |||
| 137 | static struct clk clk_h_low = { | ||
| 138 | .name = "hclk_low", | ||
| 139 | .id = -1, | ||
| 140 | .rate = 0, | ||
| 141 | .parent = NULL, | ||
| 142 | .ctrlbit = 0, | ||
| 143 | .ops = &clk_ops_def_setrate, | ||
| 144 | }; | ||
| 145 | |||
| 146 | static struct clk clk_p_low = { | ||
| 147 | .name = "pclk_low", | ||
| 148 | .id = -1, | ||
| 149 | .rate = 0, | ||
| 150 | .parent = NULL, | ||
| 151 | .ctrlbit = 0, | ||
| 152 | .ops = &clk_ops_def_setrate, | ||
| 153 | }; | ||
| 154 | |||
| 155 | enum perf_level { | ||
| 156 | L0 = 532*1000, | ||
| 157 | L1 = 266*1000, | ||
| 158 | L2 = 133*1000, | ||
| 159 | }; | ||
| 160 | |||
| 161 | static const u32 clock_table[][3] = { | ||
| 162 | /*{ARM_CLK, DIVarm, DIVhclk}*/ | ||
| 163 | {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P_CLKDIV0_HCLK_SHIFT)}, | ||
| 164 | {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P_CLKDIV0_HCLK_SHIFT)}, | ||
| 165 | {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P_CLKDIV0_HCLK_SHIFT)}, | ||
| 166 | }; | ||
| 167 | |||
| 168 | static unsigned long s5p6440_armclk_get_rate(struct clk *clk) | ||
| 169 | { | ||
| 170 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 171 | u32 clkdiv; | ||
| 172 | |||
| 173 | /* divisor mask starts at bit0, so no need to shift */ | ||
| 174 | clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK; | ||
| 175 | |||
| 176 | return rate / (clkdiv + 1); | ||
| 177 | } | ||
| 178 | |||
| 179 | static unsigned long s5p6440_armclk_round_rate(struct clk *clk, | ||
| 180 | unsigned long rate) | ||
| 181 | { | ||
| 182 | u32 iter; | ||
| 183 | |||
| 184 | for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) { | ||
| 185 | if (rate > clock_table[iter][0]) | ||
| 186 | return clock_table[iter-1][0]; | ||
| 187 | } | ||
| 188 | |||
| 189 | return clock_table[ARRAY_SIZE(clock_table) - 1][0]; | ||
| 190 | } | ||
| 191 | |||
| 192 | static int s5p6440_armclk_set_rate(struct clk *clk, unsigned long rate) | ||
| 193 | { | ||
| 194 | u32 round_tmp; | ||
| 195 | u32 iter; | ||
| 196 | u32 clk_div0_tmp; | ||
| 197 | u32 cur_rate = clk->ops->get_rate(clk); | ||
| 198 | unsigned long flags; | ||
| 199 | |||
| 200 | round_tmp = clk->ops->round_rate(clk, rate); | ||
| 201 | if (round_tmp == cur_rate) | ||
| 202 | return 0; | ||
| 203 | |||
| 204 | |||
| 205 | for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) { | ||
| 206 | if (round_tmp == clock_table[iter][0]) | ||
| 207 | break; | ||
| 208 | } | ||
| 209 | |||
| 210 | if (iter >= ARRAY_SIZE(clock_table)) | ||
| 211 | iter = ARRAY_SIZE(clock_table) - 1; | ||
| 212 | |||
| 213 | local_irq_save(flags); | ||
| 214 | if (cur_rate > round_tmp) { | ||
| 215 | /* Frequency Down */ | ||
| 216 | clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK); | ||
| 217 | clk_div0_tmp |= clock_table[iter][1]; | ||
| 218 | __raw_writel(clk_div0_tmp, ARM_CLK_DIV); | ||
| 219 | |||
| 220 | clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & | ||
| 221 | ~(S5P_CLKDIV0_HCLK_MASK); | ||
| 222 | clk_div0_tmp |= clock_table[iter][2]; | ||
| 223 | __raw_writel(clk_div0_tmp, ARM_CLK_DIV); | ||
| 224 | |||
| 225 | |||
| 226 | } else { | ||
| 227 | /* Frequency Up */ | ||
| 228 | clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & | ||
| 229 | ~(S5P_CLKDIV0_HCLK_MASK); | ||
| 230 | clk_div0_tmp |= clock_table[iter][2]; | ||
| 231 | __raw_writel(clk_div0_tmp, ARM_CLK_DIV); | ||
| 232 | |||
| 233 | clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK); | ||
| 234 | clk_div0_tmp |= clock_table[iter][1]; | ||
| 235 | __raw_writel(clk_div0_tmp, ARM_CLK_DIV); | ||
| 236 | } | ||
| 237 | local_irq_restore(flags); | ||
| 238 | |||
| 239 | clk->rate = clock_table[iter][0]; | ||
| 240 | |||
| 241 | return 0; | ||
| 242 | } | ||
| 243 | |||
| 244 | static struct clk_ops s5p6440_clkarm_ops = { | ||
| 245 | .get_rate = s5p6440_armclk_get_rate, | ||
| 246 | .set_rate = s5p6440_armclk_set_rate, | ||
| 247 | .round_rate = s5p6440_armclk_round_rate, | ||
| 248 | }; | ||
| 249 | |||
| 250 | static unsigned long s5p6440_clk_doutmpll_get_rate(struct clk *clk) | ||
| 251 | { | ||
| 252 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 253 | |||
| 254 | if (__raw_readl(S5P_CLK_DIV0) & S5P_CLKDIV0_MPLL_MASK) | ||
| 255 | rate /= 2; | ||
| 256 | |||
| 257 | return rate; | ||
| 258 | } | ||
| 259 | |||
| 260 | static struct clk clk_dout_mpll = { | ||
| 261 | .name = "dout_mpll", | ||
| 262 | .id = -1, | ||
| 263 | .parent = &clk_mout_mpll.clk, | ||
| 264 | .ops = &(struct clk_ops) { | ||
| 265 | .get_rate = s5p6440_clk_doutmpll_get_rate, | ||
| 266 | }, | ||
| 267 | }; | ||
| 268 | |||
| 269 | int s5p6440_clk48m_ctrl(struct clk *clk, int enable) | ||
| 270 | { | ||
| 271 | unsigned long flags; | ||
| 272 | u32 val; | ||
| 273 | |||
| 274 | /* can't rely on clock lock, this register has other usages */ | ||
| 275 | local_irq_save(flags); | ||
| 276 | |||
| 277 | val = __raw_readl(S5P_OTHERS); | ||
| 278 | if (enable) | ||
| 279 | val |= S5P_OTHERS_USB_SIG_MASK; | ||
| 280 | else | ||
| 281 | val &= ~S5P_OTHERS_USB_SIG_MASK; | ||
| 282 | |||
| 283 | __raw_writel(val, S5P_OTHERS); | ||
| 284 | |||
| 285 | local_irq_restore(flags); | ||
| 286 | |||
| 287 | return 0; | ||
| 288 | } | ||
| 289 | |||
| 290 | static int s5p6440_pclk_ctrl(struct clk *clk, int enable) | ||
| 291 | { | ||
| 292 | return s5p_gatectrl(S5P_CLK_GATE_PCLK, clk, enable); | ||
| 293 | } | ||
| 294 | |||
| 295 | static int s5p6440_hclk0_ctrl(struct clk *clk, int enable) | ||
| 296 | { | ||
| 297 | return s5p_gatectrl(S5P_CLK_GATE_HCLK0, clk, enable); | ||
| 298 | } | ||
| 299 | |||
| 300 | static int s5p6440_hclk1_ctrl(struct clk *clk, int enable) | ||
| 301 | { | ||
| 302 | return s5p_gatectrl(S5P_CLK_GATE_HCLK1, clk, enable); | ||
| 303 | } | ||
| 304 | |||
| 305 | static int s5p6440_sclk_ctrl(struct clk *clk, int enable) | ||
| 306 | { | ||
| 307 | return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable); | ||
| 308 | } | ||
| 309 | |||
| 310 | static int s5p6440_mem_ctrl(struct clk *clk, int enable) | ||
| 311 | { | ||
| 312 | return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable); | ||
| 313 | } | ||
| 314 | |||
| 315 | /* | ||
| 316 | * The following clocks will be disabled during clock initialization. It is | ||
| 317 | * recommended to keep the following clocks disabled until the driver requests | ||
| 318 | * for enabling the clock. | ||
| 319 | */ | ||
| 320 | static struct clk init_clocks_disable[] = { | ||
| 321 | { | ||
| 322 | .name = "nand", | ||
| 323 | .id = -1, | ||
| 324 | .parent = &clk_h, | ||
| 325 | .enable = s5p6440_mem_ctrl, | ||
| 326 | .ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON, | ||
| 327 | }, { | ||
| 328 | .name = "adc", | ||
| 329 | .id = -1, | ||
| 330 | .parent = &clk_p_low, | ||
| 331 | .enable = s5p6440_pclk_ctrl, | ||
| 332 | .ctrlbit = S5P_CLKCON_PCLK_TSADC, | ||
| 333 | }, { | ||
| 334 | .name = "i2c", | ||
| 335 | .id = -1, | ||
| 336 | .parent = &clk_p_low, | ||
| 337 | .enable = s5p6440_pclk_ctrl, | ||
| 338 | .ctrlbit = S5P_CLKCON_PCLK_IIC0, | ||
| 339 | }, { | ||
| 340 | .name = "i2s_v40", | ||
| 341 | .id = 0, | ||
| 342 | .parent = &clk_p_low, | ||
| 343 | .enable = s5p6440_pclk_ctrl, | ||
| 344 | .ctrlbit = S5P_CLKCON_PCLK_IIS2, | ||
| 345 | }, { | ||
| 346 | .name = "spi", | ||
| 347 | .id = 0, | ||
| 348 | .parent = &clk_p_low, | ||
| 349 | .enable = s5p6440_pclk_ctrl, | ||
| 350 | .ctrlbit = S5P_CLKCON_PCLK_SPI0, | ||
| 351 | }, { | ||
| 352 | .name = "spi", | ||
| 353 | .id = 1, | ||
| 354 | .parent = &clk_p_low, | ||
| 355 | .enable = s5p6440_pclk_ctrl, | ||
| 356 | .ctrlbit = S5P_CLKCON_PCLK_SPI1, | ||
| 357 | }, { | ||
| 358 | .name = "sclk_spi_48", | ||
| 359 | .id = 0, | ||
| 360 | .parent = &clk_48m, | ||
| 361 | .enable = s5p6440_sclk_ctrl, | ||
| 362 | .ctrlbit = S5P_CLKCON_SCLK0_SPI0_48, | ||
| 363 | }, { | ||
| 364 | .name = "sclk_spi_48", | ||
| 365 | .id = 1, | ||
| 366 | .parent = &clk_48m, | ||
| 367 | .enable = s5p6440_sclk_ctrl, | ||
| 368 | .ctrlbit = S5P_CLKCON_SCLK0_SPI1_48, | ||
| 369 | }, { | ||
| 370 | .name = "mmc_48m", | ||
| 371 | .id = 0, | ||
| 372 | .parent = &clk_48m, | ||
| 373 | .enable = s5p6440_sclk_ctrl, | ||
| 374 | .ctrlbit = S5P_CLKCON_SCLK0_MMC0_48, | ||
| 375 | }, { | ||
| 376 | .name = "mmc_48m", | ||
| 377 | .id = 1, | ||
| 378 | .parent = &clk_48m, | ||
| 379 | .enable = s5p6440_sclk_ctrl, | ||
| 380 | .ctrlbit = S5P_CLKCON_SCLK0_MMC1_48, | ||
| 381 | }, { | ||
| 382 | .name = "mmc_48m", | ||
| 383 | .id = 2, | ||
| 384 | .parent = &clk_48m, | ||
| 385 | .enable = s5p6440_sclk_ctrl, | ||
| 386 | .ctrlbit = S5P_CLKCON_SCLK0_MMC2_48, | ||
| 387 | }, { | ||
| 388 | .name = "otg", | ||
| 389 | .id = -1, | ||
| 390 | .parent = &clk_h_low, | ||
| 391 | .enable = s5p6440_hclk0_ctrl, | ||
| 392 | .ctrlbit = S5P_CLKCON_HCLK0_USB | ||
| 393 | }, { | ||
| 394 | .name = "post", | ||
| 395 | .id = -1, | ||
| 396 | .parent = &clk_h_low, | ||
| 397 | .enable = s5p6440_hclk0_ctrl, | ||
| 398 | .ctrlbit = S5P_CLKCON_HCLK0_POST0 | ||
| 399 | }, { | ||
| 400 | .name = "lcd", | ||
| 401 | .id = -1, | ||
| 402 | .parent = &clk_h_low, | ||
| 403 | .enable = s5p6440_hclk1_ctrl, | ||
| 404 | .ctrlbit = S5P_CLKCON_HCLK1_DISPCON, | ||
| 405 | }, { | ||
| 406 | .name = "hsmmc", | ||
| 407 | .id = 0, | ||
| 408 | .parent = &clk_h_low, | ||
| 409 | .enable = s5p6440_hclk0_ctrl, | ||
| 410 | .ctrlbit = S5P_CLKCON_HCLK0_HSMMC0, | ||
| 411 | }, { | ||
| 412 | .name = "hsmmc", | ||
| 413 | .id = 1, | ||
| 414 | .parent = &clk_h_low, | ||
| 415 | .enable = s5p6440_hclk0_ctrl, | ||
| 416 | .ctrlbit = S5P_CLKCON_HCLK0_HSMMC1, | ||
| 417 | }, { | ||
| 418 | .name = "hsmmc", | ||
| 419 | .id = 2, | ||
| 420 | .parent = &clk_h_low, | ||
| 421 | .enable = s5p6440_hclk0_ctrl, | ||
| 422 | .ctrlbit = S5P_CLKCON_HCLK0_HSMMC2, | ||
| 423 | }, { | ||
| 424 | .name = "rtc", | ||
| 425 | .id = -1, | ||
| 426 | .parent = &clk_p_low, | ||
| 427 | .enable = s5p6440_pclk_ctrl, | ||
| 428 | .ctrlbit = S5P_CLKCON_PCLK_RTC, | ||
| 429 | }, { | ||
| 430 | .name = "watchdog", | ||
| 431 | .id = -1, | ||
| 432 | .parent = &clk_p_low, | ||
| 433 | .enable = s5p6440_pclk_ctrl, | ||
| 434 | .ctrlbit = S5P_CLKCON_PCLK_WDT, | ||
| 435 | }, { | ||
| 436 | .name = "timers", | ||
| 437 | .id = -1, | ||
| 438 | .parent = &clk_p_low, | ||
| 439 | .enable = s5p6440_pclk_ctrl, | ||
| 440 | .ctrlbit = S5P_CLKCON_PCLK_PWM, | ||
| 441 | } | ||
| 442 | }; | ||
| 443 | |||
| 444 | /* | ||
| 445 | * The following clocks will be enabled during clock initialization. | ||
| 446 | */ | ||
| 447 | static struct clk init_clocks[] = { | ||
| 448 | { | ||
| 449 | .name = "gpio", | ||
| 450 | .id = -1, | ||
| 451 | .parent = &clk_p_low, | ||
| 452 | .enable = s5p6440_pclk_ctrl, | ||
| 453 | .ctrlbit = S5P_CLKCON_PCLK_GPIO, | ||
| 454 | }, { | ||
| 455 | .name = "uart", | ||
| 456 | .id = 0, | ||
| 457 | .parent = &clk_p_low, | ||
| 458 | .enable = s5p6440_pclk_ctrl, | ||
| 459 | .ctrlbit = S5P_CLKCON_PCLK_UART0, | ||
| 460 | }, { | ||
| 461 | .name = "uart", | ||
| 462 | .id = 1, | ||
| 463 | .parent = &clk_p_low, | ||
| 464 | .enable = s5p6440_pclk_ctrl, | ||
| 465 | .ctrlbit = S5P_CLKCON_PCLK_UART1, | ||
| 466 | }, { | ||
| 467 | .name = "uart", | ||
| 468 | .id = 2, | ||
| 469 | .parent = &clk_p_low, | ||
| 470 | .enable = s5p6440_pclk_ctrl, | ||
| 471 | .ctrlbit = S5P_CLKCON_PCLK_UART2, | ||
| 472 | }, { | ||
| 473 | .name = "uart", | ||
| 474 | .id = 3, | ||
| 475 | .parent = &clk_p_low, | ||
| 476 | .enable = s5p6440_pclk_ctrl, | ||
| 477 | .ctrlbit = S5P_CLKCON_PCLK_UART3, | ||
| 478 | } | ||
| 479 | }; | ||
| 480 | |||
| 481 | static struct clk clk_iis_cd_v40 = { | ||
| 482 | .name = "iis_cdclk_v40", | ||
| 483 | .id = -1, | ||
| 484 | }; | ||
| 485 | |||
| 486 | static struct clk clk_pcm_cd = { | ||
| 487 | .name = "pcm_cdclk", | ||
| 488 | .id = -1, | ||
| 489 | }; | ||
| 490 | |||
| 491 | static struct clk *clkset_spi_mmc_list[] = { | ||
| 492 | &clk_mout_epll.clk, | ||
| 493 | &clk_dout_mpll, | ||
| 494 | &clk_fin_epll, | ||
| 495 | }; | ||
| 496 | |||
| 497 | static struct clksrc_sources clkset_spi_mmc = { | ||
| 498 | .sources = clkset_spi_mmc_list, | ||
| 499 | .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), | ||
| 500 | }; | ||
| 501 | |||
| 502 | static struct clk *clkset_uart_list[] = { | ||
| 503 | &clk_mout_epll.clk, | ||
| 504 | &clk_dout_mpll | ||
| 505 | }; | ||
| 506 | |||
| 507 | static struct clksrc_sources clkset_uart = { | ||
| 508 | .sources = clkset_uart_list, | ||
| 509 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | ||
| 510 | }; | ||
| 511 | |||
| 512 | static struct clksrc_clk clksrcs[] = { | ||
| 513 | { | ||
| 514 | .clk = { | ||
| 515 | .name = "mmc_bus", | ||
| 516 | .id = 0, | ||
| 517 | .ctrlbit = S5P_CLKCON_SCLK0_MMC0, | ||
| 518 | .enable = s5p6440_sclk_ctrl, | ||
| 519 | }, | ||
| 520 | .sources = &clkset_spi_mmc, | ||
| 521 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 }, | ||
| 522 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 }, | ||
| 523 | }, { | ||
| 524 | .clk = { | ||
| 525 | .name = "mmc_bus", | ||
| 526 | .id = 1, | ||
| 527 | .ctrlbit = S5P_CLKCON_SCLK0_MMC1, | ||
| 528 | .enable = s5p6440_sclk_ctrl, | ||
| 529 | }, | ||
| 530 | .sources = &clkset_spi_mmc, | ||
| 531 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 }, | ||
| 532 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 }, | ||
| 533 | }, { | ||
| 534 | .clk = { | ||
| 535 | .name = "mmc_bus", | ||
| 536 | .id = 2, | ||
| 537 | .ctrlbit = S5P_CLKCON_SCLK0_MMC2, | ||
| 538 | .enable = s5p6440_sclk_ctrl, | ||
| 539 | }, | ||
| 540 | .sources = &clkset_spi_mmc, | ||
| 541 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 }, | ||
| 542 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 }, | ||
| 543 | }, { | ||
| 544 | .clk = { | ||
| 545 | .name = "uclk1", | ||
| 546 | .id = -1, | ||
| 547 | .ctrlbit = S5P_CLKCON_SCLK0_UART, | ||
| 548 | .enable = s5p6440_sclk_ctrl, | ||
| 549 | }, | ||
| 550 | .sources = &clkset_uart, | ||
| 551 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 13, .size = 1 }, | ||
| 552 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 }, | ||
| 553 | }, { | ||
| 554 | .clk = { | ||
| 555 | .name = "spi_epll", | ||
| 556 | .id = 0, | ||
| 557 | .ctrlbit = S5P_CLKCON_SCLK0_SPI0, | ||
| 558 | .enable = s5p6440_sclk_ctrl, | ||
| 559 | }, | ||
| 560 | .sources = &clkset_spi_mmc, | ||
| 561 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 }, | ||
| 562 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, | ||
| 563 | }, { | ||
| 564 | .clk = { | ||
| 565 | .name = "spi_epll", | ||
| 566 | .id = 1, | ||
| 567 | .ctrlbit = S5P_CLKCON_SCLK0_SPI1, | ||
| 568 | .enable = s5p6440_sclk_ctrl, | ||
| 569 | }, | ||
| 570 | .sources = &clkset_spi_mmc, | ||
| 571 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 }, | ||
| 572 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, | ||
| 573 | } | ||
| 574 | }; | ||
| 575 | |||
| 576 | /* Clock initialisation code */ | ||
| 577 | static struct clksrc_clk *init_parents[] = { | ||
| 578 | &clk_mout_apll, | ||
| 579 | &clk_mout_epll, | ||
| 580 | &clk_mout_mpll, | ||
| 581 | }; | ||
| 582 | |||
| 583 | void __init_or_cpufreq s5p6440_setup_clocks(void) | ||
| 584 | { | ||
| 585 | struct clk *xtal_clk; | ||
| 586 | unsigned long xtal; | ||
| 587 | unsigned long fclk; | ||
| 588 | unsigned long hclk; | ||
| 589 | unsigned long hclk_low; | ||
| 590 | unsigned long pclk; | ||
| 591 | unsigned long pclk_low; | ||
| 592 | unsigned long epll; | ||
| 593 | unsigned long apll; | ||
| 594 | unsigned long mpll; | ||
| 595 | unsigned int ptr; | ||
| 596 | u32 clkdiv0; | ||
| 597 | u32 clkdiv3; | ||
| 598 | |||
| 599 | /* Set S5P6440 functions for clk_fout_epll */ | ||
| 600 | clk_fout_epll.enable = s5p6440_epll_enable; | ||
| 601 | clk_fout_epll.ops = &s5p6440_epll_ops; | ||
| 602 | |||
| 603 | /* Set S5P6440 functions for arm clock */ | ||
| 604 | clk_arm.parent = &clk_mout_apll.clk; | ||
| 605 | clk_arm.ops = &s5p6440_clkarm_ops; | ||
| 606 | clk_48m.enable = s5p6440_clk48m_ctrl; | ||
| 607 | |||
| 608 | clkdiv0 = __raw_readl(S5P_CLK_DIV0); | ||
| 609 | clkdiv3 = __raw_readl(S5P_CLK_DIV3); | ||
| 610 | |||
| 611 | xtal_clk = clk_get(NULL, "ext_xtal"); | ||
| 612 | BUG_ON(IS_ERR(xtal_clk)); | ||
| 613 | |||
| 614 | xtal = clk_get_rate(xtal_clk); | ||
| 615 | clk_put(xtal_clk); | ||
| 616 | |||
| 617 | epll = s5p_get_pll90xx(xtal, __raw_readl(S5P_EPLL_CON), | ||
| 618 | __raw_readl(S5P_EPLL_CON_K)); | ||
| 619 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); | ||
| 620 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502); | ||
| 621 | |||
| 622 | printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \ | ||
| 623 | " E=%ld.%ldMHz\n", | ||
| 624 | print_mhz(apll), print_mhz(mpll), print_mhz(epll)); | ||
| 625 | |||
| 626 | fclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_ARM); | ||
| 627 | hclk = fclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK); | ||
| 628 | pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK); | ||
| 629 | |||
| 630 | if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) { | ||
| 631 | /* Asynchronous mode */ | ||
| 632 | hclk_low = mpll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW); | ||
| 633 | } else { | ||
| 634 | /* Synchronous mode */ | ||
| 635 | hclk_low = apll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW); | ||
| 636 | } | ||
| 637 | |||
| 638 | pclk_low = hclk_low / GET_DIV(clkdiv3, S5P_CLKDIV3_PCLK_LOW); | ||
| 639 | |||
| 640 | printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \ | ||
| 641 | " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n", | ||
| 642 | print_mhz(hclk), print_mhz(hclk_low), | ||
| 643 | print_mhz(pclk), print_mhz(pclk_low)); | ||
| 644 | |||
| 645 | clk_fout_mpll.rate = mpll; | ||
| 646 | clk_fout_epll.rate = epll; | ||
| 647 | clk_fout_apll.rate = apll; | ||
| 648 | |||
| 649 | clk_f.rate = fclk; | ||
| 650 | clk_h.rate = hclk; | ||
| 651 | clk_p.rate = pclk; | ||
| 652 | clk_h_low.rate = hclk_low; | ||
| 653 | clk_p_low.rate = pclk_low; | ||
| 654 | |||
| 655 | for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) | ||
| 656 | s3c_set_clksrc(init_parents[ptr], true); | ||
| 657 | |||
| 658 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | ||
| 659 | s3c_set_clksrc(&clksrcs[ptr], true); | ||
| 660 | } | ||
| 661 | |||
| 662 | static struct clk *clks[] __initdata = { | ||
| 663 | &clk_ext, | ||
| 664 | &clk_mout_epll.clk, | ||
| 665 | &clk_mout_mpll.clk, | ||
| 666 | &clk_dout_mpll, | ||
| 667 | &clk_iis_cd_v40, | ||
| 668 | &clk_pcm_cd, | ||
| 669 | &clk_p_low, | ||
| 670 | &clk_h_low, | ||
| 671 | }; | ||
| 672 | |||
| 673 | void __init s5p6440_register_clocks(void) | ||
| 674 | { | ||
| 675 | struct clk *clkp; | ||
| 676 | int ret; | ||
| 677 | int ptr; | ||
| 678 | |||
| 679 | ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | ||
| 680 | if (ret > 0) | ||
| 681 | printk(KERN_ERR "Failed to register %u clocks\n", ret); | ||
| 682 | |||
| 683 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | ||
| 684 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | ||
| 685 | |||
| 686 | clkp = init_clocks_disable; | ||
| 687 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { | ||
| 688 | |||
| 689 | ret = s3c24xx_register_clock(clkp); | ||
| 690 | if (ret < 0) { | ||
| 691 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
| 692 | clkp->name, ret); | ||
| 693 | } | ||
| 694 | (clkp->enable)(clkp, 0); | ||
| 695 | } | ||
| 696 | |||
| 697 | s3c_pwmclk_init(); | ||
| 698 | } | ||
diff --git a/arch/arm/plat-s5p/s5p6440-init.c b/arch/arm/plat-s5p/s5p6440-init.c new file mode 100644 index 000000000000..90178256cc28 --- /dev/null +++ b/arch/arm/plat-s5p/s5p6440-init.c | |||
| @@ -0,0 +1,50 @@ | |||
| 1 | /* linux/arch/arm/plat-s5p/s5p6440-init.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/types.h> | ||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/serial_core.h> | ||
| 15 | |||
| 16 | #include <plat/cpu.h> | ||
| 17 | #include <plat/devs.h> | ||
| 18 | #include <plat/s5p6440.h> | ||
| 19 | #include <plat/regs-serial.h> | ||
| 20 | |||
| 21 | static struct s3c24xx_uart_clksrc s5p6440_serial_clocks[] = { | ||
| 22 | [0] = { | ||
| 23 | .name = "pclk_low", | ||
| 24 | .divisor = 1, | ||
| 25 | .min_baud = 0, | ||
| 26 | .max_baud = 0, | ||
| 27 | }, | ||
| 28 | [1] = { | ||
| 29 | .name = "uclk1", | ||
| 30 | .divisor = 1, | ||
| 31 | .min_baud = 0, | ||
| 32 | .max_baud = 0, | ||
| 33 | }, | ||
| 34 | }; | ||
| 35 | |||
| 36 | /* uart registration process */ | ||
| 37 | void __init s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) | ||
| 38 | { | ||
| 39 | struct s3c2410_uartcfg *tcfg = cfg; | ||
| 40 | u32 ucnt; | ||
| 41 | |||
| 42 | for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { | ||
| 43 | if (!tcfg->clocks) { | ||
| 44 | tcfg->clocks = s5p6440_serial_clocks; | ||
| 45 | tcfg->clocks_size = ARRAY_SIZE(s5p6440_serial_clocks); | ||
| 46 | } | ||
| 47 | } | ||
| 48 | |||
| 49 | s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); | ||
| 50 | } | ||
diff --git a/arch/arm/plat-s5p/setup-i2c0.c b/arch/arm/plat-s5p/setup-i2c0.c new file mode 100644 index 000000000000..67a66e02a97a --- /dev/null +++ b/arch/arm/plat-s5p/setup-i2c0.c | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | /* linux/arch/arm/plat-s5p/setup-i2c0.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * I2C0 GPIO configuration. | ||
| 7 | * | ||
| 8 | * Based on plat-s3c64xx/setup-i2c0.c | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/types.h> | ||
| 17 | |||
| 18 | struct platform_device; /* don't need the contents */ | ||
| 19 | |||
| 20 | #include <plat/iic.h> | ||
| 21 | |||
| 22 | void s3c_i2c0_cfg_gpio(struct platform_device *dev) | ||
| 23 | { | ||
| 24 | /* Will be populated later */ | ||
| 25 | } | ||
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig index b7b9e91c0243..c7ccdf22eefa 100644 --- a/arch/arm/plat-s5pc1xx/Kconfig +++ b/arch/arm/plat-s5pc1xx/Kconfig | |||
| @@ -11,6 +11,9 @@ config PLAT_S5PC1XX | |||
| 11 | select ARM_VIC | 11 | select ARM_VIC |
| 12 | select NO_IOPORT | 12 | select NO_IOPORT |
| 13 | select ARCH_REQUIRE_GPIOLIB | 13 | select ARCH_REQUIRE_GPIOLIB |
| 14 | select SAMSUNG_CLKSRC | ||
| 15 | select SAMSUNG_IRQ_UART | ||
| 16 | select SAMSUNG_IRQ_VIC_TIMER | ||
| 14 | select S3C_GPIO_TRACK | 17 | select S3C_GPIO_TRACK |
| 15 | select S3C_GPIO_PULL_UPDOWN | 18 | select S3C_GPIO_PULL_UPDOWN |
| 16 | select S3C_GPIO_CFG_S3C24XX | 19 | select S3C_GPIO_CFG_S3C24XX |
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c index 26c21d849790..387f23190c3c 100644 --- a/arch/arm/plat-s5pc1xx/clock.c +++ b/arch/arm/plat-s5pc1xx/clock.c | |||
| @@ -64,25 +64,13 @@ struct clk clk_54m = { | |||
| 64 | .rate = 54000000, | 64 | .rate = 54000000, |
| 65 | }; | 65 | }; |
| 66 | 66 | ||
| 67 | static int clk_default_setrate(struct clk *clk, unsigned long rate) | ||
| 68 | { | ||
| 69 | clk->rate = rate; | ||
| 70 | return 0; | ||
| 71 | } | ||
| 72 | |||
| 73 | static int clk_dummy_enable(struct clk *clk, int enable) | ||
| 74 | { | ||
| 75 | return 0; | ||
| 76 | } | ||
| 77 | |||
| 78 | struct clk clk_hd0 = { | 67 | struct clk clk_hd0 = { |
| 79 | .name = "hclkd0", | 68 | .name = "hclkd0", |
| 80 | .id = -1, | 69 | .id = -1, |
| 81 | .rate = 0, | 70 | .rate = 0, |
| 82 | .parent = NULL, | 71 | .parent = NULL, |
| 83 | .ctrlbit = 0, | 72 | .ctrlbit = 0, |
| 84 | .set_rate = clk_default_setrate, | 73 | .ops = &clk_ops_def_setrate, |
| 85 | .enable = clk_dummy_enable, | ||
| 86 | }; | 74 | }; |
| 87 | 75 | ||
| 88 | struct clk clk_pd0 = { | 76 | struct clk clk_pd0 = { |
| @@ -91,8 +79,7 @@ struct clk clk_pd0 = { | |||
| 91 | .rate = 0, | 79 | .rate = 0, |
| 92 | .parent = NULL, | 80 | .parent = NULL, |
| 93 | .ctrlbit = 0, | 81 | .ctrlbit = 0, |
| 94 | .set_rate = clk_default_setrate, | 82 | .ops = &clk_ops_def_setrate, |
| 95 | .enable = clk_dummy_enable, | ||
| 96 | }; | 83 | }; |
| 97 | 84 | ||
| 98 | static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable) | 85 | static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable) |
| @@ -686,6 +673,8 @@ static struct clk s5pc100_init_clocks[] = { | |||
| 686 | static struct clk *clks[] __initdata = { | 673 | static struct clk *clks[] __initdata = { |
| 687 | &clk_ext, | 674 | &clk_ext, |
| 688 | &clk_epll, | 675 | &clk_epll, |
| 676 | &clk_pd0, | ||
| 677 | &clk_hd0, | ||
| 689 | &clk_27m, | 678 | &clk_27m, |
| 690 | &clk_48m, | 679 | &clk_48m, |
| 691 | &clk_54m, | 680 | &clk_54m, |
| @@ -700,16 +689,8 @@ void __init s5pc1xx_register_clocks(void) | |||
| 700 | 689 | ||
| 701 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | 690 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); |
| 702 | 691 | ||
| 703 | clkp = s5pc100_init_clocks; | 692 | s3c_register_clocks(s5pc100_init_clocks, |
| 704 | size = ARRAY_SIZE(s5pc100_init_clocks); | 693 | ARRAY_SIZE(s5pc100_init_clocks)); |
| 705 | |||
| 706 | for (ptr = 0; ptr < size; ptr++, clkp++) { | ||
| 707 | ret = s3c24xx_register_clock(clkp); | ||
| 708 | if (ret < 0) { | ||
| 709 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
| 710 | clkp->name, ret); | ||
| 711 | } | ||
| 712 | } | ||
| 713 | 694 | ||
| 714 | clkp = s5pc100_init_clocks_disable; | 695 | clkp = s5pc100_init_clocks_disable; |
| 715 | size = ARRAY_SIZE(s5pc100_init_clocks_disable); | 696 | size = ARRAY_SIZE(s5pc100_init_clocks_disable); |
diff --git a/arch/arm/plat-s5pc1xx/dev-uart.c b/arch/arm/plat-s5pc1xx/dev-uart.c index f749bc5407b5..586c95c60bfe 100644 --- a/arch/arm/plat-s5pc1xx/dev-uart.c +++ b/arch/arm/plat-s5pc1xx/dev-uart.c | |||
| @@ -143,32 +143,3 @@ struct s3c24xx_uart_resources s5pc1xx_uart_resources[] __initdata = { | |||
| 143 | .nr_resources = ARRAY_SIZE(s5pc1xx_uart3_resource), | 143 | .nr_resources = ARRAY_SIZE(s5pc1xx_uart3_resource), |
| 144 | }, | 144 | }, |
| 145 | }; | 145 | }; |
| 146 | |||
| 147 | /* uart devices */ | ||
| 148 | |||
| 149 | static struct platform_device s3c24xx_uart_device0 = { | ||
| 150 | .id = 0, | ||
| 151 | }; | ||
| 152 | |||
| 153 | static struct platform_device s3c24xx_uart_device1 = { | ||
| 154 | .id = 1, | ||
| 155 | }; | ||
| 156 | |||
| 157 | static struct platform_device s3c24xx_uart_device2 = { | ||
| 158 | .id = 2, | ||
| 159 | }; | ||
| 160 | |||
| 161 | static struct platform_device s3c24xx_uart_device3 = { | ||
| 162 | .id = 3, | ||
| 163 | }; | ||
| 164 | |||
| 165 | struct platform_device *s3c24xx_uart_src[4] = { | ||
| 166 | &s3c24xx_uart_device0, | ||
| 167 | &s3c24xx_uart_device1, | ||
| 168 | &s3c24xx_uart_device2, | ||
| 169 | &s3c24xx_uart_device3, | ||
| 170 | }; | ||
| 171 | |||
| 172 | struct platform_device *s3c24xx_uart_devs[4] = { | ||
| 173 | }; | ||
| 174 | |||
diff --git a/arch/arm/plat-s5pc1xx/gpio-config.c b/arch/arm/plat-s5pc1xx/gpio-config.c index bba675df9c75..a4f67e80a150 100644 --- a/arch/arm/plat-s5pc1xx/gpio-config.c +++ b/arch/arm/plat-s5pc1xx/gpio-config.c | |||
| @@ -16,7 +16,7 @@ | |||
| 16 | #include <linux/gpio.h> | 16 | #include <linux/gpio.h> |
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | 18 | ||
| 19 | #include <mach/gpio-core.h> | 19 | #include <plat/gpio-core.h> |
| 20 | #include <plat/gpio-cfg-s5pc1xx.h> | 20 | #include <plat/gpio-cfg-s5pc1xx.h> |
| 21 | 21 | ||
| 22 | s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off) | 22 | s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off) |
diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/plat-s5pc1xx/gpiolib.c index facb410e7a71..1ffc57ac293d 100644 --- a/arch/arm/plat-s5pc1xx/gpiolib.c +++ b/arch/arm/plat-s5pc1xx/gpiolib.c | |||
| @@ -17,8 +17,8 @@ | |||
| 17 | #include <linux/gpio.h> | 17 | #include <linux/gpio.h> |
| 18 | 18 | ||
| 19 | #include <mach/map.h> | 19 | #include <mach/map.h> |
| 20 | #include <mach/gpio-core.h> | ||
| 21 | 20 | ||
| 21 | #include <plat/gpio-core.h> | ||
| 22 | #include <plat/gpio-cfg.h> | 22 | #include <plat/gpio-cfg.h> |
| 23 | #include <plat/gpio-cfg-helpers.h> | 23 | #include <plat/gpio-cfg-helpers.h> |
| 24 | #include <plat/regs-gpio.h> | 24 | #include <plat/regs-gpio.h> |
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h index ef8736366f0d..409c804315e8 100644 --- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h +++ b/arch/arm/plat-s5pc1xx/include/plat/irqs.h | |||
| @@ -88,11 +88,11 @@ | |||
| 88 | #define IRQ_MDMA S5PC1XX_IRQ_VIC0(18) | 88 | #define IRQ_MDMA S5PC1XX_IRQ_VIC0(18) |
| 89 | #define IRQ_PDMA0 S5PC1XX_IRQ_VIC0(19) | 89 | #define IRQ_PDMA0 S5PC1XX_IRQ_VIC0(19) |
| 90 | #define IRQ_PDMA1 S5PC1XX_IRQ_VIC0(20) | 90 | #define IRQ_PDMA1 S5PC1XX_IRQ_VIC0(20) |
| 91 | #define IRQ_TIMER0 S5PC1XX_IRQ_VIC0(21) | 91 | #define IRQ_TIMER0_VIC S5PC1XX_IRQ_VIC0(21) |
| 92 | #define IRQ_TIMER1 S5PC1XX_IRQ_VIC0(22) | 92 | #define IRQ_TIMER1_VIC S5PC1XX_IRQ_VIC0(22) |
| 93 | #define IRQ_TIMER2 S5PC1XX_IRQ_VIC0(23) | 93 | #define IRQ_TIMER2_VIC S5PC1XX_IRQ_VIC0(23) |
| 94 | #define IRQ_TIMER3 S5PC1XX_IRQ_VIC0(24) | 94 | #define IRQ_TIMER3_VIC S5PC1XX_IRQ_VIC0(24) |
| 95 | #define IRQ_TIMER4 S5PC1XX_IRQ_VIC0(25) | 95 | #define IRQ_TIMER4_VIC S5PC1XX_IRQ_VIC0(25) |
| 96 | #define IRQ_SYSTIMER S5PC1XX_IRQ_VIC0(26) | 96 | #define IRQ_SYSTIMER S5PC1XX_IRQ_VIC0(26) |
| 97 | #define IRQ_WDT S5PC1XX_IRQ_VIC0(27) | 97 | #define IRQ_WDT S5PC1XX_IRQ_VIC0(27) |
| 98 | #define IRQ_RTC_ALARM S5PC1XX_IRQ_VIC0(28) | 98 | #define IRQ_RTC_ALARM S5PC1XX_IRQ_VIC0(28) |
| @@ -171,8 +171,15 @@ | |||
| 171 | #define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30) | 171 | #define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30) |
| 172 | #define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31) | 172 | #define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31) |
| 173 | 173 | ||
| 174 | #define IRQ_TIMER(x) (IRQ_SDMFIQ + 1 + (x)) | ||
| 175 | #define IRQ_TIMER0 IRQ_TIMER(0) | ||
| 176 | #define IRQ_TIMER1 IRQ_TIMER(1) | ||
| 177 | #define IRQ_TIMER2 IRQ_TIMER(2) | ||
| 178 | #define IRQ_TIMER3 IRQ_TIMER(3) | ||
| 179 | #define IRQ_TIMER4 IRQ_TIMER(4) | ||
| 180 | |||
| 174 | /* External interrupt */ | 181 | /* External interrupt */ |
| 175 | #define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 1) | 182 | #define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 6) |
| 176 | 183 | ||
| 177 | #define S3C_EINT(x) (S3C_IRQ_EINT_BASE + (x - 16)) | 184 | #define S3C_EINT(x) (S3C_IRQ_EINT_BASE + (x - 16)) |
| 178 | #define IRQ_EINT(x) (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x)) | 185 | #define IRQ_EINT(x) (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x)) |
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h index c5cc86e92d65..24dec4e52538 100644 --- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h | |||
| @@ -61,73 +61,10 @@ | |||
| 61 | #define S5PC100_EPLL_MASK 0xffffffff | 61 | #define S5PC100_EPLL_MASK 0xffffffff |
| 62 | #define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) | 62 | #define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) |
| 63 | 63 | ||
| 64 | /* CLKSRC0 */ | 64 | /* CLKSRC0..CLKSRC3 -> mostly removed due to clksrc updates */ |
| 65 | #define S5PC100_CLKSRC0_APLL_MASK (0x1<<0) | 65 | #define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24) |
| 66 | #define S5PC100_CLKSRC0_APLL_SHIFT (0) | ||
| 67 | #define S5PC100_CLKSRC0_MPLL_MASK (0x1<<4) | ||
| 68 | #define S5PC100_CLKSRC0_MPLL_SHIFT (4) | ||
| 69 | #define S5PC100_CLKSRC0_EPLL_MASK (0x1<<8) | ||
| 70 | #define S5PC100_CLKSRC0_EPLL_SHIFT (8) | ||
| 71 | #define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12) | ||
| 72 | #define S5PC100_CLKSRC0_HPLL_SHIFT (12) | ||
| 73 | #define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16) | ||
| 74 | #define S5PC100_CLKSRC0_AMMUX_SHIFT (16) | ||
| 75 | #define S5PC100_CLKSRC0_HREF_MASK (0x1<<20) | ||
| 76 | #define S5PC100_CLKSRC0_HREF_SHIFT (20) | ||
| 77 | #define S5PC100_CLKSRC0_ONENAND_MASK (0x1<<24) | ||
| 78 | #define S5PC100_CLKSRC0_ONENAND_SHIFT (24) | ||
| 79 | |||
| 80 | |||
| 81 | /* CLKSRC1 */ | ||
| 82 | #define S5PC100_CLKSRC1_UART_MASK (0x1<<0) | ||
| 83 | #define S5PC100_CLKSRC1_UART_SHIFT (0) | ||
| 84 | #define S5PC100_CLKSRC1_SPI0_MASK (0x3<<4) | ||
| 85 | #define S5PC100_CLKSRC1_SPI0_SHIFT (4) | ||
| 86 | #define S5PC100_CLKSRC1_SPI1_MASK (0x3<<8) | ||
| 87 | #define S5PC100_CLKSRC1_SPI1_SHIFT (8) | ||
| 88 | #define S5PC100_CLKSRC1_SPI2_MASK (0x3<<12) | ||
| 89 | #define S5PC100_CLKSRC1_SPI2_SHIFT (12) | ||
| 90 | #define S5PC100_CLKSRC1_IRDA_MASK (0x3<<16) | ||
| 91 | #define S5PC100_CLKSRC1_IRDA_SHIFT (16) | ||
| 92 | #define S5PC100_CLKSRC1_UHOST_MASK (0x3<<20) | ||
| 93 | #define S5PC100_CLKSRC1_UHOST_SHIFT (20) | ||
| 94 | #define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24) | ||
| 95 | #define S5PC100_CLKSRC1_CLK48M_SHIFT (24) | 66 | #define S5PC100_CLKSRC1_CLK48M_SHIFT (24) |
| 96 | 67 | ||
| 97 | /* CLKSRC2 */ | ||
| 98 | #define S5PC100_CLKSRC2_MMC0_MASK (0x3<<0) | ||
| 99 | #define S5PC100_CLKSRC2_MMC0_SHIFT (0) | ||
| 100 | #define S5PC100_CLKSRC2_MMC1_MASK (0x3<<4) | ||
| 101 | #define S5PC100_CLKSRC2_MMC1_SHIFT (4) | ||
| 102 | #define S5PC100_CLKSRC2_MMC2_MASK (0x3<<8) | ||
| 103 | #define S5PC100_CLKSRC2_MMC2_SHIFT (8) | ||
| 104 | #define S5PC100_CLKSRC2_LCD_MASK (0x3<<12) | ||
| 105 | #define S5PC100_CLKSRC2_LCD_SHIFT (12) | ||
| 106 | #define S5PC100_CLKSRC2_FIMC0_MASK (0x3<<16) | ||
| 107 | #define S5PC100_CLKSRC2_FIMC0_SHIFT (16) | ||
| 108 | #define S5PC100_CLKSRC2_FIMC1_MASK (0x3<<20) | ||
| 109 | #define S5PC100_CLKSRC2_FIMC1_SHIFT (20) | ||
| 110 | #define S5PC100_CLKSRC2_FIMC2_MASK (0x3<<24) | ||
| 111 | #define S5PC100_CLKSRC2_FIMC2_SHIFT (24) | ||
| 112 | #define S5PC100_CLKSRC2_MIXER_MASK (0x3<<28) | ||
| 113 | #define S5PC100_CLKSRC2_MIXER_SHIFT (28) | ||
| 114 | |||
| 115 | /* CLKSRC3 */ | ||
| 116 | #define S5PC100_CLKSRC3_PWI_MASK (0x3<<0) | ||
| 117 | #define S5PC100_CLKSRC3_PWI_SHIFT (0) | ||
| 118 | #define S5PC100_CLKSRC3_HCLKD2_MASK (0x1<<4) | ||
| 119 | #define S5PC100_CLKSRC3_HCLKD2_SHIFT (4) | ||
| 120 | #define S5PC100_CLKSRC3_I2SD2_MASK (0x3<<8) | ||
| 121 | #define S5PC100_CLKSRC3_I2SD2_SHIFT (8) | ||
| 122 | #define S5PC100_CLKSRC3_AUDIO0_MASK (0x7<<12) | ||
| 123 | #define S5PC100_CLKSRC3_AUDIO0_SHIFT (12) | ||
| 124 | #define S5PC100_CLKSRC3_AUDIO1_MASK (0x7<<16) | ||
| 125 | #define S5PC100_CLKSRC3_AUDIO1_SHIFT (16) | ||
| 126 | #define S5PC100_CLKSRC3_AUDIO2_MASK (0x7<<20) | ||
| 127 | #define S5PC100_CLKSRC3_AUDIO2_SHIFT (20) | ||
| 128 | #define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24) | ||
| 129 | #define S5PC100_CLKSRC3_SPDIF_SHIFT (24) | ||
| 130 | |||
| 131 | /* CLKDIV0 */ | 68 | /* CLKDIV0 */ |
| 132 | #define S5PC100_CLKDIV0_APLL_MASK (0x1<<0) | 69 | #define S5PC100_CLKDIV0_APLL_MASK (0x1<<0) |
| 133 | #define S5PC100_CLKDIV0_APLL_SHIFT (0) | 70 | #define S5PC100_CLKDIV0_APLL_SHIFT (0) |
| @@ -140,7 +77,7 @@ | |||
| 140 | #define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16) | 77 | #define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16) |
| 141 | #define S5PC100_CLKDIV0_SECSS_SHIFT (16) | 78 | #define S5PC100_CLKDIV0_SECSS_SHIFT (16) |
| 142 | 79 | ||
| 143 | /* CLKDIV1 */ | 80 | /* CLKDIV1 (OneNAND clock only used in one place, removed) */ |
| 144 | #define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0) | 81 | #define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0) |
| 145 | #define S5PC100_CLKDIV1_APLL2_SHIFT (0) | 82 | #define S5PC100_CLKDIV1_APLL2_SHIFT (0) |
| 146 | #define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4) | 83 | #define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4) |
| @@ -151,56 +88,12 @@ | |||
| 151 | #define S5PC100_CLKDIV1_D1_SHIFT (12) | 88 | #define S5PC100_CLKDIV1_D1_SHIFT (12) |
| 152 | #define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16) | 89 | #define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16) |
| 153 | #define S5PC100_CLKDIV1_PCLKD1_SHIFT (16) | 90 | #define S5PC100_CLKDIV1_PCLKD1_SHIFT (16) |
| 154 | #define S5PC100_CLKDIV1_ONENAND_MASK (0x3<<20) | ||
| 155 | #define S5PC100_CLKDIV1_ONENAND_SHIFT (20) | ||
| 156 | #define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24) | 91 | #define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24) |
| 157 | #define S5PC100_CLKDIV1_CAM_SHIFT (24) | 92 | #define S5PC100_CLKDIV1_CAM_SHIFT (24) |
| 158 | 93 | ||
| 159 | /* CLKDIV2 */ | 94 | /* CLKDIV2 => removed in clksrc update */ |
| 160 | #define S5PC100_CLKDIV2_UART_MASK (0x7<<0) | 95 | /* CLKDIV3 => removed in clksrc update, or not needed */ |
| 161 | #define S5PC100_CLKDIV2_UART_SHIFT (0) | 96 | /* CLKDIV4 => removed in clksrc update, or not needed */ |
| 162 | #define S5PC100_CLKDIV2_SPI0_MASK (0xf<<4) | ||
| 163 | #define S5PC100_CLKDIV2_SPI0_SHIFT (4) | ||
| 164 | #define S5PC100_CLKDIV2_SPI1_MASK (0xf<<8) | ||
| 165 | #define S5PC100_CLKDIV2_SPI1_SHIFT (8) | ||
| 166 | #define S5PC100_CLKDIV2_SPI2_MASK (0xf<<12) | ||
| 167 | #define S5PC100_CLKDIV2_SPI2_SHIFT (12) | ||
| 168 | #define S5PC100_CLKDIV2_IRDA_MASK (0xf<<16) | ||
| 169 | #define S5PC100_CLKDIV2_IRDA_SHIFT (16) | ||
| 170 | #define S5PC100_CLKDIV2_UHOST_MASK (0xf<<20) | ||
| 171 | #define S5PC100_CLKDIV2_UHOST_SHIFT (20) | ||
| 172 | |||
| 173 | /* CLKDIV3 */ | ||
| 174 | #define S5PC100_CLKDIV3_MMC0_MASK (0xf<<0) | ||
| 175 | #define S5PC100_CLKDIV3_MMC0_SHIFT (0) | ||
| 176 | #define S5PC100_CLKDIV3_MMC1_MASK (0xf<<4) | ||
| 177 | #define S5PC100_CLKDIV3_MMC1_SHIFT (4) | ||
| 178 | #define S5PC100_CLKDIV3_MMC2_MASK (0xf<<8) | ||
| 179 | #define S5PC100_CLKDIV3_MMC2_SHIFT (8) | ||
| 180 | #define S5PC100_CLKDIV3_LCD_MASK (0xf<<12) | ||
| 181 | #define S5PC100_CLKDIV3_LCD_SHIFT (12) | ||
| 182 | #define S5PC100_CLKDIV3_FIMC0_MASK (0xf<<16) | ||
| 183 | #define S5PC100_CLKDIV3_FIMC0_SHIFT (16) | ||
| 184 | #define S5PC100_CLKDIV3_FIMC1_MASK (0xf<<20) | ||
| 185 | #define S5PC100_CLKDIV3_FIMC1_SHIFT (20) | ||
| 186 | #define S5PC100_CLKDIV3_FIMC2_MASK (0xf<<24) | ||
| 187 | #define S5PC100_CLKDIV3_FIMC2_SHIFT (24) | ||
| 188 | #define S5PC100_CLKDIV3_HDMI_MASK (0xf<<28) | ||
| 189 | #define S5PC100_CLKDIV3_HDMI_SHIFT (28) | ||
| 190 | |||
| 191 | /* CLKDIV4 */ | ||
| 192 | #define S5PC100_CLKDIV4_PWI_MASK (0x7<<0) | ||
| 193 | #define S5PC100_CLKDIV4_PWI_SHIFT (0) | ||
| 194 | #define S5PC100_CLKDIV4_HCLKD2_MASK (0x7<<4) | ||
| 195 | #define S5PC100_CLKDIV4_HCLKD2_SHIFT (4) | ||
| 196 | #define S5PC100_CLKDIV4_I2SD2_MASK (0xf<<8) | ||
| 197 | #define S5PC100_CLKDIV4_I2SD2_SHIFT (8) | ||
| 198 | #define S5PC100_CLKDIV4_AUDIO0_MASK (0xf<<12) | ||
| 199 | #define S5PC100_CLKDIV4_AUDIO0_SHIFT (12) | ||
| 200 | #define S5PC100_CLKDIV4_AUDIO1_MASK (0xf<<16) | ||
| 201 | #define S5PC100_CLKDIV4_AUDIO1_SHIFT (16) | ||
| 202 | #define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20) | ||
| 203 | #define S5PC100_CLKDIV4_AUDIO2_SHIFT (20) | ||
| 204 | 97 | ||
| 205 | /* HCLKD0/PCLKD0 Clock Gate 0 Registers */ | 98 | /* HCLKD0/PCLKD0 Clock Gate 0 Registers */ |
| 206 | #define S5PC100_CLKGATE_D00_INTC (1<<0) | 99 | #define S5PC100_CLKGATE_D00_INTC (1<<0) |
diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c index e44fd04ef333..bfc524827819 100644 --- a/arch/arm/plat-s5pc1xx/irq.c +++ b/arch/arm/plat-s5pc1xx/irq.c | |||
| @@ -20,87 +20,14 @@ | |||
| 20 | #include <asm/hardware/vic.h> | 20 | #include <asm/hardware/vic.h> |
| 21 | 21 | ||
| 22 | #include <mach/map.h> | 22 | #include <mach/map.h> |
| 23 | #include <plat/regs-timer.h> | 23 | #include <plat/irq-vic-timer.h> |
| 24 | #include <plat/irq-uart.h> | ||
| 24 | #include <plat/cpu.h> | 25 | #include <plat/cpu.h> |
| 25 | 26 | ||
| 26 | /* Timer interrupt handling */ | ||
| 27 | |||
| 28 | static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq) | ||
| 29 | { | ||
| 30 | generic_handle_irq(sub_irq); | ||
| 31 | } | ||
| 32 | |||
| 33 | static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc) | ||
| 34 | { | ||
| 35 | s3c_irq_demux_timer(irq, IRQ_TIMER0); | ||
| 36 | } | ||
| 37 | |||
| 38 | static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc) | ||
| 39 | { | ||
| 40 | s3c_irq_demux_timer(irq, IRQ_TIMER1); | ||
| 41 | } | ||
| 42 | |||
| 43 | static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc) | ||
| 44 | { | ||
| 45 | s3c_irq_demux_timer(irq, IRQ_TIMER2); | ||
| 46 | } | ||
| 47 | |||
| 48 | static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc) | ||
| 49 | { | ||
| 50 | s3c_irq_demux_timer(irq, IRQ_TIMER3); | ||
| 51 | } | ||
| 52 | |||
| 53 | static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc) | ||
| 54 | { | ||
| 55 | s3c_irq_demux_timer(irq, IRQ_TIMER4); | ||
| 56 | } | ||
| 57 | |||
| 58 | /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ | ||
| 59 | |||
| 60 | static void s3c_irq_timer_mask(unsigned int irq) | ||
| 61 | { | ||
| 62 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
| 63 | |||
| 64 | reg &= 0x1f; /* mask out pending interrupts */ | ||
| 65 | reg &= ~(1 << (irq - IRQ_TIMER0)); | ||
| 66 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
| 67 | } | ||
| 68 | |||
| 69 | static void s3c_irq_timer_unmask(unsigned int irq) | ||
| 70 | { | ||
| 71 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
| 72 | |||
| 73 | reg &= 0x1f; /* mask out pending interrupts */ | ||
| 74 | reg |= 1 << (irq - IRQ_TIMER0); | ||
| 75 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
| 76 | } | ||
| 77 | |||
| 78 | static void s3c_irq_timer_ack(unsigned int irq) | ||
| 79 | { | ||
| 80 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
| 81 | |||
| 82 | reg &= 0x1f; /* mask out pending interrupts */ | ||
| 83 | reg |= (1 << 5) << (irq - IRQ_TIMER0); | ||
| 84 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
| 85 | } | ||
| 86 | |||
| 87 | static struct irq_chip s3c_irq_timer = { | ||
| 88 | .name = "s3c-timer", | ||
| 89 | .mask = s3c_irq_timer_mask, | ||
| 90 | .unmask = s3c_irq_timer_unmask, | ||
| 91 | .ack = s3c_irq_timer_ack, | ||
| 92 | }; | ||
| 93 | |||
| 94 | struct uart_irq { | ||
| 95 | void __iomem *regs; | ||
| 96 | unsigned int base_irq; | ||
| 97 | unsigned int parent_irq; | ||
| 98 | }; | ||
| 99 | |||
| 100 | /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] | 27 | /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] |
| 101 | * are consecutive when looking up the interrupt in the demux routines. | 28 | * are consecutive when looking up the interrupt in the demux routines. |
| 102 | */ | 29 | */ |
| 103 | static struct uart_irq uart_irqs[] = { | 30 | static struct s3c_uart_irq uart_irqs[] = { |
| 104 | [0] = { | 31 | [0] = { |
| 105 | .regs = (void *)S3C_VA_UART0, | 32 | .regs = (void *)S3C_VA_UART0, |
| 106 | .base_irq = IRQ_S3CUART_BASE0, | 33 | .base_irq = IRQ_S3CUART_BASE0, |
| @@ -123,113 +50,9 @@ static struct uart_irq uart_irqs[] = { | |||
| 123 | }, | 50 | }, |
| 124 | }; | 51 | }; |
| 125 | 52 | ||
| 126 | static inline void __iomem *s3c_irq_uart_base(unsigned int irq) | ||
| 127 | { | ||
| 128 | struct uart_irq *uirq = get_irq_chip_data(irq); | ||
| 129 | return uirq->regs; | ||
| 130 | } | ||
| 131 | |||
| 132 | static inline unsigned int s3c_irq_uart_bit(unsigned int irq) | ||
| 133 | { | ||
| 134 | return irq & 3; | ||
| 135 | } | ||
| 136 | |||
| 137 | /* UART interrupt registers, not worth adding to seperate include header */ | ||
| 138 | #define S3C64XX_UINTP 0x30 | ||
| 139 | #define S3C64XX_UINTSP 0x34 | ||
| 140 | #define S3C64XX_UINTM 0x38 | ||
| 141 | |||
| 142 | static void s3c_irq_uart_mask(unsigned int irq) | ||
| 143 | { | ||
| 144 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
| 145 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
| 146 | u32 reg; | ||
| 147 | |||
| 148 | reg = __raw_readl(regs + S3C64XX_UINTM); | ||
| 149 | reg |= (1 << bit); | ||
| 150 | __raw_writel(reg, regs + S3C64XX_UINTM); | ||
| 151 | } | ||
| 152 | |||
| 153 | static void s3c_irq_uart_maskack(unsigned int irq) | ||
| 154 | { | ||
| 155 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
| 156 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
| 157 | u32 reg; | ||
| 158 | |||
| 159 | reg = __raw_readl(regs + S3C64XX_UINTM); | ||
| 160 | reg |= (1 << bit); | ||
| 161 | __raw_writel(reg, regs + S3C64XX_UINTM); | ||
| 162 | __raw_writel(1 << bit, regs + S3C64XX_UINTP); | ||
| 163 | } | ||
| 164 | |||
| 165 | static void s3c_irq_uart_unmask(unsigned int irq) | ||
| 166 | { | ||
| 167 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
| 168 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
| 169 | u32 reg; | ||
| 170 | |||
| 171 | reg = __raw_readl(regs + S3C64XX_UINTM); | ||
| 172 | reg &= ~(1 << bit); | ||
| 173 | __raw_writel(reg, regs + S3C64XX_UINTM); | ||
| 174 | } | ||
| 175 | |||
| 176 | static void s3c_irq_uart_ack(unsigned int irq) | ||
| 177 | { | ||
| 178 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
| 179 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
| 180 | |||
| 181 | __raw_writel(1 << bit, regs + S3C64XX_UINTP); | ||
| 182 | } | ||
| 183 | |||
| 184 | static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) | ||
| 185 | { | ||
| 186 | struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0]; | ||
| 187 | u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); | ||
| 188 | int base = uirq->base_irq; | ||
| 189 | |||
| 190 | if (pend & (1 << 0)) | ||
| 191 | generic_handle_irq(base); | ||
| 192 | if (pend & (1 << 1)) | ||
| 193 | generic_handle_irq(base + 1); | ||
| 194 | if (pend & (1 << 2)) | ||
| 195 | generic_handle_irq(base + 2); | ||
| 196 | if (pend & (1 << 3)) | ||
| 197 | generic_handle_irq(base + 3); | ||
| 198 | } | ||
| 199 | |||
| 200 | static struct irq_chip s3c_irq_uart = { | ||
| 201 | .name = "s3c-uart", | ||
| 202 | .mask = s3c_irq_uart_mask, | ||
| 203 | .unmask = s3c_irq_uart_unmask, | ||
| 204 | .mask_ack = s3c_irq_uart_maskack, | ||
| 205 | .ack = s3c_irq_uart_ack, | ||
| 206 | }; | ||
| 207 | |||
| 208 | static void __init s5pc1xx_uart_irq(struct uart_irq *uirq) | ||
| 209 | { | ||
| 210 | void __iomem *reg_base = uirq->regs; | ||
| 211 | unsigned int irq; | ||
| 212 | int offs; | ||
| 213 | |||
| 214 | /* mask all interrupts at the start. */ | ||
| 215 | __raw_writel(0xf, reg_base + S3C64XX_UINTM); | ||
| 216 | |||
| 217 | for (offs = 0; offs < 3; offs++) { | ||
| 218 | irq = uirq->base_irq + offs; | ||
| 219 | |||
| 220 | set_irq_chip(irq, &s3c_irq_uart); | ||
| 221 | set_irq_chip_data(irq, uirq); | ||
| 222 | set_irq_handler(irq, handle_level_irq); | ||
| 223 | set_irq_flags(irq, IRQF_VALID); | ||
| 224 | } | ||
| 225 | |||
| 226 | set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); | ||
| 227 | } | ||
| 228 | |||
| 229 | void __init s5pc1xx_init_irq(u32 *vic_valid, int num) | 53 | void __init s5pc1xx_init_irq(u32 *vic_valid, int num) |
| 230 | { | 54 | { |
| 231 | int i; | 55 | int i; |
| 232 | int uart, irq; | ||
| 233 | 56 | ||
| 234 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); | 57 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); |
| 235 | 58 | ||
| @@ -240,20 +63,13 @@ void __init s5pc1xx_init_irq(u32 *vic_valid, int num) | |||
| 240 | 63 | ||
| 241 | /* add the timer sub-irqs */ | 64 | /* add the timer sub-irqs */ |
| 242 | 65 | ||
| 243 | set_irq_chained_handler(IRQ_TIMER0, s3c_irq_demux_timer0); | 66 | s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); |
| 244 | set_irq_chained_handler(IRQ_TIMER1, s3c_irq_demux_timer1); | 67 | s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); |
| 245 | set_irq_chained_handler(IRQ_TIMER2, s3c_irq_demux_timer2); | 68 | s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); |
| 246 | set_irq_chained_handler(IRQ_TIMER3, s3c_irq_demux_timer3); | 69 | s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); |
| 247 | set_irq_chained_handler(IRQ_TIMER4, s3c_irq_demux_timer4); | 70 | s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); |
| 248 | |||
| 249 | for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) { | ||
| 250 | set_irq_chip(irq, &s3c_irq_timer); | ||
| 251 | set_irq_handler(irq, handle_level_irq); | ||
| 252 | set_irq_flags(irq, IRQF_VALID); | ||
| 253 | } | ||
| 254 | 71 | ||
| 255 | for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) | 72 | s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); |
| 256 | s5pc1xx_uart_irq(&uart_irqs[uart]); | ||
| 257 | } | 73 | } |
| 258 | 74 | ||
| 259 | 75 | ||
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c index b436d44510c8..2bf6c57a96a2 100644 --- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c +++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | 29 | ||
| 30 | #include <plat/regs-clock.h> | 30 | #include <plat/regs-clock.h> |
| 31 | #include <plat/clock.h> | 31 | #include <plat/clock.h> |
| 32 | #include <plat/clock-clksrc.h> | ||
| 32 | #include <plat/cpu.h> | 33 | #include <plat/cpu.h> |
| 33 | #include <plat/pll.h> | 34 | #include <plat/pll.h> |
| 34 | #include <plat/devs.h> | 35 | #include <plat/devs.h> |
| @@ -51,23 +52,6 @@ static struct clk clk_ext_xtal_mux = { | |||
| 51 | #define clk_fout_mpll clk_mpll | 52 | #define clk_fout_mpll clk_mpll |
| 52 | #define clk_vclk_54m clk_54m | 53 | #define clk_vclk_54m clk_54m |
| 53 | 54 | ||
| 54 | struct clk_sources { | ||
| 55 | unsigned int nr_sources; | ||
| 56 | struct clk **sources; | ||
| 57 | }; | ||
| 58 | |||
| 59 | struct clksrc_clk { | ||
| 60 | struct clk clk; | ||
| 61 | unsigned int mask; | ||
| 62 | unsigned int shift; | ||
| 63 | |||
| 64 | struct clk_sources *sources; | ||
| 65 | |||
| 66 | unsigned int divider_shift; | ||
| 67 | void __iomem *reg_divider; | ||
| 68 | void __iomem *reg_source; | ||
| 69 | }; | ||
| 70 | |||
| 71 | /* APLL */ | 55 | /* APLL */ |
| 72 | static struct clk clk_fout_apll = { | 56 | static struct clk clk_fout_apll = { |
| 73 | .name = "fout_apll", | 57 | .name = "fout_apll", |
| @@ -80,7 +64,7 @@ static struct clk *clk_src_apll_list[] = { | |||
| 80 | [1] = &clk_fout_apll, | 64 | [1] = &clk_fout_apll, |
| 81 | }; | 65 | }; |
| 82 | 66 | ||
| 83 | static struct clk_sources clk_src_apll = { | 67 | static struct clksrc_sources clk_src_apll = { |
| 84 | .sources = clk_src_apll_list, | 68 | .sources = clk_src_apll_list, |
| 85 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), | 69 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), |
| 86 | }; | 70 | }; |
| @@ -90,10 +74,8 @@ static struct clksrc_clk clk_mout_apll = { | |||
| 90 | .name = "mout_apll", | 74 | .name = "mout_apll", |
| 91 | .id = -1, | 75 | .id = -1, |
| 92 | }, | 76 | }, |
| 93 | .shift = S5PC100_CLKSRC0_APLL_SHIFT, | ||
| 94 | .mask = S5PC100_CLKSRC0_APLL_MASK, | ||
| 95 | .sources = &clk_src_apll, | 77 | .sources = &clk_src_apll, |
| 96 | .reg_source = S5PC100_CLKSRC0, | 78 | .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 0, .size = 1, }, |
| 97 | }; | 79 | }; |
| 98 | 80 | ||
| 99 | static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk) | 81 | static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk) |
| @@ -111,7 +93,9 @@ static struct clk clk_dout_apll = { | |||
| 111 | .name = "dout_apll", | 93 | .name = "dout_apll", |
| 112 | .id = -1, | 94 | .id = -1, |
| 113 | .parent = &clk_mout_apll.clk, | 95 | .parent = &clk_mout_apll.clk, |
| 114 | .get_rate = s5pc100_clk_dout_apll_get_rate, | 96 | .ops = &(struct clk_ops) { |
| 97 | .get_rate = s5pc100_clk_dout_apll_get_rate, | ||
| 98 | }, | ||
| 115 | }; | 99 | }; |
| 116 | 100 | ||
| 117 | static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk) | 101 | static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk) |
| @@ -165,9 +149,11 @@ static struct clk clk_arm = { | |||
| 165 | .name = "armclk", | 149 | .name = "armclk", |
| 166 | .id = -1, | 150 | .id = -1, |
| 167 | .parent = &clk_dout_apll, | 151 | .parent = &clk_dout_apll, |
| 168 | .get_rate = s5pc100_clk_arm_get_rate, | 152 | .ops = &(struct clk_ops) { |
| 169 | .set_rate = s5pc100_clk_arm_set_rate, | 153 | .get_rate = s5pc100_clk_arm_get_rate, |
| 170 | .round_rate = s5pc100_clk_arm_round_rate, | 154 | .set_rate = s5pc100_clk_arm_set_rate, |
| 155 | .round_rate = s5pc100_clk_arm_round_rate, | ||
| 156 | }, | ||
| 171 | }; | 157 | }; |
| 172 | 158 | ||
| 173 | static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk) | 159 | static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk) |
| @@ -185,7 +171,9 @@ static struct clk clk_dout_d0_bus = { | |||
| 185 | .name = "dout_d0_bus", | 171 | .name = "dout_d0_bus", |
| 186 | .id = -1, | 172 | .id = -1, |
| 187 | .parent = &clk_arm, | 173 | .parent = &clk_arm, |
| 188 | .get_rate = s5pc100_clk_dout_d0_bus_get_rate, | 174 | .ops = &(struct clk_ops) { |
| 175 | .get_rate = s5pc100_clk_dout_d0_bus_get_rate, | ||
| 176 | }, | ||
| 189 | }; | 177 | }; |
| 190 | 178 | ||
| 191 | static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk) | 179 | static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk) |
| @@ -203,7 +191,9 @@ static struct clk clk_dout_pclkd0 = { | |||
| 203 | .name = "dout_pclkd0", | 191 | .name = "dout_pclkd0", |
| 204 | .id = -1, | 192 | .id = -1, |
| 205 | .parent = &clk_dout_d0_bus, | 193 | .parent = &clk_dout_d0_bus, |
| 206 | .get_rate = s5pc100_clk_dout_pclkd0_get_rate, | 194 | .ops = &(struct clk_ops) { |
| 195 | .get_rate = s5pc100_clk_dout_pclkd0_get_rate, | ||
| 196 | }, | ||
| 207 | }; | 197 | }; |
| 208 | 198 | ||
| 209 | static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk) | 199 | static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk) |
| @@ -221,7 +211,9 @@ static struct clk clk_dout_apll2 = { | |||
| 221 | .name = "dout_apll2", | 211 | .name = "dout_apll2", |
| 222 | .id = -1, | 212 | .id = -1, |
| 223 | .parent = &clk_mout_apll.clk, | 213 | .parent = &clk_mout_apll.clk, |
| 224 | .get_rate = s5pc100_clk_dout_apll2_get_rate, | 214 | .ops = &(struct clk_ops) { |
| 215 | .get_rate = s5pc100_clk_dout_apll2_get_rate, | ||
| 216 | }, | ||
| 225 | }; | 217 | }; |
| 226 | 218 | ||
| 227 | /* MPLL */ | 219 | /* MPLL */ |
| @@ -230,7 +222,7 @@ static struct clk *clk_src_mpll_list[] = { | |||
| 230 | [1] = &clk_fout_mpll, | 222 | [1] = &clk_fout_mpll, |
| 231 | }; | 223 | }; |
| 232 | 224 | ||
| 233 | static struct clk_sources clk_src_mpll = { | 225 | static struct clksrc_sources clk_src_mpll = { |
| 234 | .sources = clk_src_mpll_list, | 226 | .sources = clk_src_mpll_list, |
| 235 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), | 227 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), |
| 236 | }; | 228 | }; |
| @@ -240,10 +232,8 @@ static struct clksrc_clk clk_mout_mpll = { | |||
| 240 | .name = "mout_mpll", | 232 | .name = "mout_mpll", |
| 241 | .id = -1, | 233 | .id = -1, |
| 242 | }, | 234 | }, |
| 243 | .shift = S5PC100_CLKSRC0_MPLL_SHIFT, | ||
| 244 | .mask = S5PC100_CLKSRC0_MPLL_MASK, | ||
| 245 | .sources = &clk_src_mpll, | 235 | .sources = &clk_src_mpll, |
| 246 | .reg_source = S5PC100_CLKSRC0, | 236 | .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 4, .size = 1, }, |
| 247 | }; | 237 | }; |
| 248 | 238 | ||
| 249 | static struct clk *clkset_am_list[] = { | 239 | static struct clk *clkset_am_list[] = { |
| @@ -251,7 +241,7 @@ static struct clk *clkset_am_list[] = { | |||
| 251 | [1] = &clk_dout_apll2, | 241 | [1] = &clk_dout_apll2, |
| 252 | }; | 242 | }; |
| 253 | 243 | ||
| 254 | static struct clk_sources clk_src_am = { | 244 | static struct clksrc_sources clk_src_am = { |
| 255 | .sources = clkset_am_list, | 245 | .sources = clkset_am_list, |
| 256 | .nr_sources = ARRAY_SIZE(clkset_am_list), | 246 | .nr_sources = ARRAY_SIZE(clkset_am_list), |
| 257 | }; | 247 | }; |
| @@ -261,10 +251,8 @@ static struct clksrc_clk clk_mout_am = { | |||
| 261 | .name = "mout_am", | 251 | .name = "mout_am", |
| 262 | .id = -1, | 252 | .id = -1, |
| 263 | }, | 253 | }, |
| 264 | .shift = S5PC100_CLKSRC0_AMMUX_SHIFT, | ||
| 265 | .mask = S5PC100_CLKSRC0_AMMUX_MASK, | ||
| 266 | .sources = &clk_src_am, | 254 | .sources = &clk_src_am, |
| 267 | .reg_source = S5PC100_CLKSRC0, | 255 | .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 16, .size = 1, }, |
| 268 | }; | 256 | }; |
| 269 | 257 | ||
| 270 | static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk) | 258 | static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk) |
| @@ -284,7 +272,9 @@ static struct clk clk_dout_d1_bus = { | |||
| 284 | .name = "dout_d1_bus", | 272 | .name = "dout_d1_bus", |
| 285 | .id = -1, | 273 | .id = -1, |
| 286 | .parent = &clk_mout_am.clk, | 274 | .parent = &clk_mout_am.clk, |
| 287 | .get_rate = s5pc100_clk_dout_d1_bus_get_rate, | 275 | .ops = &(struct clk_ops) { |
| 276 | .get_rate = s5pc100_clk_dout_d1_bus_get_rate, | ||
| 277 | }, | ||
| 288 | }; | 278 | }; |
| 289 | 279 | ||
| 290 | static struct clk *clkset_onenand_list[] = { | 280 | static struct clk *clkset_onenand_list[] = { |
| @@ -292,7 +282,7 @@ static struct clk *clkset_onenand_list[] = { | |||
| 292 | [1] = &clk_dout_d1_bus, | 282 | [1] = &clk_dout_d1_bus, |
| 293 | }; | 283 | }; |
| 294 | 284 | ||
| 295 | static struct clk_sources clk_src_onenand = { | 285 | static struct clksrc_sources clk_src_onenand = { |
| 296 | .sources = clkset_onenand_list, | 286 | .sources = clkset_onenand_list, |
| 297 | .nr_sources = ARRAY_SIZE(clkset_onenand_list), | 287 | .nr_sources = ARRAY_SIZE(clkset_onenand_list), |
| 298 | }; | 288 | }; |
| @@ -302,10 +292,8 @@ static struct clksrc_clk clk_mout_onenand = { | |||
| 302 | .name = "mout_onenand", | 292 | .name = "mout_onenand", |
| 303 | .id = -1, | 293 | .id = -1, |
| 304 | }, | 294 | }, |
| 305 | .shift = S5PC100_CLKSRC0_ONENAND_SHIFT, | ||
| 306 | .mask = S5PC100_CLKSRC0_ONENAND_MASK, | ||
| 307 | .sources = &clk_src_onenand, | 295 | .sources = &clk_src_onenand, |
| 308 | .reg_source = S5PC100_CLKSRC0, | 296 | .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 24, .size = 1, }, |
| 309 | }; | 297 | }; |
| 310 | 298 | ||
| 311 | static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk) | 299 | static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk) |
| @@ -325,7 +313,9 @@ static struct clk clk_dout_pclkd1 = { | |||
| 325 | .name = "dout_pclkd1", | 313 | .name = "dout_pclkd1", |
| 326 | .id = -1, | 314 | .id = -1, |
| 327 | .parent = &clk_dout_d1_bus, | 315 | .parent = &clk_dout_d1_bus, |
| 328 | .get_rate = s5pc100_clk_dout_pclkd1_get_rate, | 316 | .ops = &(struct clk_ops) { |
| 317 | .get_rate = s5pc100_clk_dout_pclkd1_get_rate, | ||
| 318 | }, | ||
| 329 | }; | 319 | }; |
| 330 | 320 | ||
| 331 | static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk) | 321 | static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk) |
| @@ -345,7 +335,9 @@ static struct clk clk_dout_mpll2 = { | |||
| 345 | .name = "dout_mpll2", | 335 | .name = "dout_mpll2", |
| 346 | .id = -1, | 336 | .id = -1, |
| 347 | .parent = &clk_mout_am.clk, | 337 | .parent = &clk_mout_am.clk, |
| 348 | .get_rate = s5pc100_clk_dout_mpll2_get_rate, | 338 | .ops = &(struct clk_ops) { |
| 339 | .get_rate = s5pc100_clk_dout_mpll2_get_rate, | ||
| 340 | }, | ||
| 349 | }; | 341 | }; |
| 350 | 342 | ||
| 351 | static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk) | 343 | static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk) |
| @@ -365,7 +357,9 @@ static struct clk clk_dout_cam = { | |||
| 365 | .name = "dout_cam", | 357 | .name = "dout_cam", |
| 366 | .id = -1, | 358 | .id = -1, |
| 367 | .parent = &clk_dout_mpll2, | 359 | .parent = &clk_dout_mpll2, |
| 368 | .get_rate = s5pc100_clk_dout_cam_get_rate, | 360 | .ops = &(struct clk_ops) { |
| 361 | .get_rate = s5pc100_clk_dout_cam_get_rate, | ||
| 362 | }, | ||
| 369 | }; | 363 | }; |
| 370 | 364 | ||
| 371 | static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk) | 365 | static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk) |
| @@ -385,7 +379,9 @@ static struct clk clk_dout_mpll = { | |||
| 385 | .name = "dout_mpll", | 379 | .name = "dout_mpll", |
| 386 | .id = -1, | 380 | .id = -1, |
| 387 | .parent = &clk_mout_am.clk, | 381 | .parent = &clk_mout_am.clk, |
| 388 | .get_rate = s5pc100_clk_dout_mpll_get_rate, | 382 | .ops = &(struct clk_ops) { |
| 383 | .get_rate = s5pc100_clk_dout_mpll_get_rate, | ||
| 384 | }, | ||
| 389 | }; | 385 | }; |
| 390 | 386 | ||
| 391 | /* EPLL */ | 387 | /* EPLL */ |
| @@ -399,7 +395,7 @@ static struct clk *clk_src_epll_list[] = { | |||
| 399 | [1] = &clk_fout_epll, | 395 | [1] = &clk_fout_epll, |
| 400 | }; | 396 | }; |
| 401 | 397 | ||
| 402 | static struct clk_sources clk_src_epll = { | 398 | static struct clksrc_sources clk_src_epll = { |
| 403 | .sources = clk_src_epll_list, | 399 | .sources = clk_src_epll_list, |
| 404 | .nr_sources = ARRAY_SIZE(clk_src_epll_list), | 400 | .nr_sources = ARRAY_SIZE(clk_src_epll_list), |
| 405 | }; | 401 | }; |
| @@ -409,10 +405,8 @@ static struct clksrc_clk clk_mout_epll = { | |||
| 409 | .name = "mout_epll", | 405 | .name = "mout_epll", |
| 410 | .id = -1, | 406 | .id = -1, |
| 411 | }, | 407 | }, |
| 412 | .shift = S5PC100_CLKSRC0_EPLL_SHIFT, | 408 | .sources = &clk_src_epll, |
| 413 | .mask = S5PC100_CLKSRC0_EPLL_MASK, | 409 | .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 8, .size = 1, }, |
| 414 | .sources = &clk_src_epll, | ||
| 415 | .reg_source = S5PC100_CLKSRC0, | ||
| 416 | }; | 410 | }; |
| 417 | 411 | ||
| 418 | /* HPLL */ | 412 | /* HPLL */ |
| @@ -426,7 +420,7 @@ static struct clk *clk_src_hpll_list[] = { | |||
| 426 | [1] = &clk_fout_hpll, | 420 | [1] = &clk_fout_hpll, |
| 427 | }; | 421 | }; |
| 428 | 422 | ||
| 429 | static struct clk_sources clk_src_hpll = { | 423 | static struct clksrc_sources clk_src_hpll = { |
| 430 | .sources = clk_src_hpll_list, | 424 | .sources = clk_src_hpll_list, |
| 431 | .nr_sources = ARRAY_SIZE(clk_src_hpll_list), | 425 | .nr_sources = ARRAY_SIZE(clk_src_hpll_list), |
| 432 | }; | 426 | }; |
| @@ -436,10 +430,8 @@ static struct clksrc_clk clk_mout_hpll = { | |||
| 436 | .name = "mout_hpll", | 430 | .name = "mout_hpll", |
| 437 | .id = -1, | 431 | .id = -1, |
| 438 | }, | 432 | }, |
| 439 | .shift = S5PC100_CLKSRC0_HPLL_SHIFT, | 433 | .sources = &clk_src_hpll, |
| 440 | .mask = S5PC100_CLKSRC0_HPLL_MASK, | 434 | .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 12, .size = 1, }, |
| 441 | .sources = &clk_src_hpll, | ||
| 442 | .reg_source = S5PC100_CLKSRC0, | ||
| 443 | }; | 435 | }; |
| 444 | 436 | ||
| 445 | /* Peripherals */ | 437 | /* Peripherals */ |
| @@ -454,190 +446,6 @@ static struct clksrc_clk clk_mout_hpll = { | |||
| 454 | * have a common parent divisor so are not included here. | 446 | * have a common parent divisor so are not included here. |
| 455 | */ | 447 | */ |
| 456 | 448 | ||
| 457 | static inline struct clksrc_clk *to_clksrc(struct clk *clk) | ||
| 458 | { | ||
| 459 | return container_of(clk, struct clksrc_clk, clk); | ||
| 460 | } | ||
| 461 | |||
| 462 | static unsigned long s5pc100_getrate_clksrc(struct clk *clk) | ||
| 463 | { | ||
| 464 | struct clksrc_clk *sclk = to_clksrc(clk); | ||
| 465 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 466 | u32 clkdiv = __raw_readl(sclk->reg_divider); | ||
| 467 | |||
| 468 | clkdiv >>= sclk->divider_shift; | ||
| 469 | clkdiv &= 0xf; | ||
| 470 | clkdiv++; | ||
| 471 | |||
| 472 | rate /= clkdiv; | ||
| 473 | return rate; | ||
| 474 | } | ||
| 475 | |||
| 476 | static int s5pc100_setrate_clksrc(struct clk *clk, unsigned long rate) | ||
| 477 | { | ||
| 478 | struct clksrc_clk *sclk = to_clksrc(clk); | ||
| 479 | void __iomem *reg = sclk->reg_divider; | ||
| 480 | unsigned int div; | ||
| 481 | u32 val; | ||
| 482 | |||
| 483 | rate = clk_round_rate(clk, rate); | ||
| 484 | div = clk_get_rate(clk->parent) / rate; | ||
| 485 | if (div > 16) | ||
| 486 | return -EINVAL; | ||
| 487 | |||
| 488 | val = __raw_readl(reg); | ||
| 489 | val &= ~(0xf << sclk->divider_shift); | ||
| 490 | val |= (div - 1) << sclk->divider_shift; | ||
| 491 | __raw_writel(val, reg); | ||
| 492 | |||
| 493 | return 0; | ||
| 494 | } | ||
| 495 | |||
| 496 | static int s5pc100_setparent_clksrc(struct clk *clk, struct clk *parent) | ||
| 497 | { | ||
| 498 | struct clksrc_clk *sclk = to_clksrc(clk); | ||
| 499 | struct clk_sources *srcs = sclk->sources; | ||
| 500 | u32 clksrc = __raw_readl(sclk->reg_source); | ||
| 501 | int src_nr = -1; | ||
| 502 | int ptr; | ||
| 503 | |||
| 504 | for (ptr = 0; ptr < srcs->nr_sources; ptr++) | ||
| 505 | if (srcs->sources[ptr] == parent) { | ||
| 506 | src_nr = ptr; | ||
| 507 | break; | ||
| 508 | } | ||
| 509 | |||
| 510 | if (src_nr >= 0) { | ||
| 511 | clksrc &= ~sclk->mask; | ||
| 512 | clksrc |= src_nr << sclk->shift; | ||
| 513 | |||
| 514 | __raw_writel(clksrc, sclk->reg_source); | ||
| 515 | return 0; | ||
| 516 | } | ||
| 517 | |||
| 518 | return -EINVAL; | ||
| 519 | } | ||
| 520 | |||
| 521 | static unsigned long s5pc100_roundrate_clksrc(struct clk *clk, | ||
| 522 | unsigned long rate) | ||
| 523 | { | ||
| 524 | unsigned long parent_rate = clk_get_rate(clk->parent); | ||
| 525 | int div; | ||
| 526 | |||
| 527 | if (rate > parent_rate) | ||
| 528 | rate = parent_rate; | ||
| 529 | else { | ||
| 530 | div = rate / parent_rate; | ||
| 531 | |||
| 532 | if (div == 0) | ||
| 533 | div = 1; | ||
| 534 | if (div > 16) | ||
| 535 | div = 16; | ||
| 536 | |||
| 537 | rate = parent_rate / div; | ||
| 538 | } | ||
| 539 | |||
| 540 | return rate; | ||
| 541 | } | ||
| 542 | |||
| 543 | static struct clk *clkset_spi_list[] = { | ||
| 544 | &clk_mout_epll.clk, | ||
| 545 | &clk_dout_mpll2, | ||
| 546 | &clk_fin_epll, | ||
| 547 | &clk_mout_hpll.clk, | ||
| 548 | }; | ||
| 549 | |||
| 550 | static struct clk_sources clkset_spi = { | ||
| 551 | .sources = clkset_spi_list, | ||
| 552 | .nr_sources = ARRAY_SIZE(clkset_spi_list), | ||
| 553 | }; | ||
| 554 | |||
| 555 | static struct clksrc_clk clk_spi0 = { | ||
| 556 | .clk = { | ||
| 557 | .name = "spi_bus", | ||
| 558 | .id = 0, | ||
| 559 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0, | ||
| 560 | .enable = s5pc100_sclk0_ctrl, | ||
| 561 | .set_parent = s5pc100_setparent_clksrc, | ||
| 562 | .get_rate = s5pc100_getrate_clksrc, | ||
| 563 | .set_rate = s5pc100_setrate_clksrc, | ||
| 564 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 565 | }, | ||
| 566 | .shift = S5PC100_CLKSRC1_SPI0_SHIFT, | ||
| 567 | .mask = S5PC100_CLKSRC1_SPI0_MASK, | ||
| 568 | .sources = &clkset_spi, | ||
| 569 | .divider_shift = S5PC100_CLKDIV2_SPI0_SHIFT, | ||
| 570 | .reg_divider = S5PC100_CLKDIV2, | ||
| 571 | .reg_source = S5PC100_CLKSRC1, | ||
| 572 | }; | ||
| 573 | |||
| 574 | static struct clksrc_clk clk_spi1 = { | ||
| 575 | .clk = { | ||
| 576 | .name = "spi_bus", | ||
| 577 | .id = 1, | ||
| 578 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, | ||
| 579 | .enable = s5pc100_sclk0_ctrl, | ||
| 580 | .set_parent = s5pc100_setparent_clksrc, | ||
| 581 | .get_rate = s5pc100_getrate_clksrc, | ||
| 582 | .set_rate = s5pc100_setrate_clksrc, | ||
| 583 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 584 | }, | ||
| 585 | .shift = S5PC100_CLKSRC1_SPI1_SHIFT, | ||
| 586 | .mask = S5PC100_CLKSRC1_SPI1_MASK, | ||
| 587 | .sources = &clkset_spi, | ||
| 588 | .divider_shift = S5PC100_CLKDIV2_SPI1_SHIFT, | ||
| 589 | .reg_divider = S5PC100_CLKDIV2, | ||
| 590 | .reg_source = S5PC100_CLKSRC1, | ||
| 591 | }; | ||
| 592 | |||
| 593 | static struct clksrc_clk clk_spi2 = { | ||
| 594 | .clk = { | ||
| 595 | .name = "spi_bus", | ||
| 596 | .id = 2, | ||
| 597 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, | ||
| 598 | .enable = s5pc100_sclk0_ctrl, | ||
| 599 | .set_parent = s5pc100_setparent_clksrc, | ||
| 600 | .get_rate = s5pc100_getrate_clksrc, | ||
| 601 | .set_rate = s5pc100_setrate_clksrc, | ||
| 602 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 603 | }, | ||
| 604 | .shift = S5PC100_CLKSRC1_SPI2_SHIFT, | ||
| 605 | .mask = S5PC100_CLKSRC1_SPI2_MASK, | ||
| 606 | .sources = &clkset_spi, | ||
| 607 | .divider_shift = S5PC100_CLKDIV2_SPI2_SHIFT, | ||
| 608 | .reg_divider = S5PC100_CLKDIV2, | ||
| 609 | .reg_source = S5PC100_CLKSRC1, | ||
| 610 | }; | ||
| 611 | |||
| 612 | static struct clk *clkset_uart_list[] = { | ||
| 613 | &clk_mout_epll.clk, | ||
| 614 | &clk_dout_mpll, | ||
| 615 | }; | ||
| 616 | |||
| 617 | static struct clk_sources clkset_uart = { | ||
| 618 | .sources = clkset_uart_list, | ||
| 619 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | ||
| 620 | }; | ||
| 621 | |||
| 622 | static struct clksrc_clk clk_uart_uclk1 = { | ||
| 623 | .clk = { | ||
| 624 | .name = "uclk1", | ||
| 625 | .id = -1, | ||
| 626 | .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, | ||
| 627 | .enable = s5pc100_sclk0_ctrl, | ||
| 628 | .set_parent = s5pc100_setparent_clksrc, | ||
| 629 | .get_rate = s5pc100_getrate_clksrc, | ||
| 630 | .set_rate = s5pc100_setrate_clksrc, | ||
| 631 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 632 | }, | ||
| 633 | .shift = S5PC100_CLKSRC1_UART_SHIFT, | ||
| 634 | .mask = S5PC100_CLKSRC1_UART_MASK, | ||
| 635 | .sources = &clkset_uart, | ||
| 636 | .divider_shift = S5PC100_CLKDIV2_UART_SHIFT, | ||
| 637 | .reg_divider = S5PC100_CLKDIV2, | ||
| 638 | .reg_source = S5PC100_CLKSRC1, | ||
| 639 | }; | ||
| 640 | |||
| 641 | static struct clk clk_iis_cd0 = { | 449 | static struct clk clk_iis_cd0 = { |
| 642 | .name = "iis_cdclk0", | 450 | .name = "iis_cdclk0", |
| 643 | .id = -1, | 451 | .id = -1, |
| @@ -672,28 +480,31 @@ static struct clk *clkset_audio0_list[] = { | |||
| 672 | &clk_mout_hpll.clk, | 480 | &clk_mout_hpll.clk, |
| 673 | }; | 481 | }; |
| 674 | 482 | ||
| 675 | static struct clk_sources clkset_audio0 = { | 483 | static struct clksrc_sources clkset_audio0 = { |
| 676 | .sources = clkset_audio0_list, | 484 | .sources = clkset_audio0_list, |
| 677 | .nr_sources = ARRAY_SIZE(clkset_audio0_list), | 485 | .nr_sources = ARRAY_SIZE(clkset_audio0_list), |
| 678 | }; | 486 | }; |
| 679 | 487 | ||
| 680 | static struct clksrc_clk clk_audio0 = { | 488 | static struct clk *clkset_spi_list[] = { |
| 681 | .clk = { | 489 | &clk_mout_epll.clk, |
| 682 | .name = "audio-bus", | 490 | &clk_dout_mpll2, |
| 683 | .id = 0, | 491 | &clk_fin_epll, |
| 684 | .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, | 492 | &clk_mout_hpll.clk, |
| 685 | .enable = s5pc100_sclk1_ctrl, | 493 | }; |
| 686 | .set_parent = s5pc100_setparent_clksrc, | 494 | |
| 687 | .get_rate = s5pc100_getrate_clksrc, | 495 | static struct clksrc_sources clkset_spi = { |
| 688 | .set_rate = s5pc100_setrate_clksrc, | 496 | .sources = clkset_spi_list, |
| 689 | .round_rate = s5pc100_roundrate_clksrc, | 497 | .nr_sources = ARRAY_SIZE(clkset_spi_list), |
| 690 | }, | 498 | }; |
| 691 | .shift = S5PC100_CLKSRC3_AUDIO0_SHIFT, | 499 | |
| 692 | .mask = S5PC100_CLKSRC3_AUDIO0_MASK, | 500 | static struct clk *clkset_uart_list[] = { |
| 693 | .sources = &clkset_audio0, | 501 | &clk_mout_epll.clk, |
| 694 | .divider_shift = S5PC100_CLKDIV4_AUDIO0_SHIFT, | 502 | &clk_dout_mpll, |
| 695 | .reg_divider = S5PC100_CLKDIV4, | 503 | }; |
| 696 | .reg_source = S5PC100_CLKSRC3, | 504 | |
| 505 | static struct clksrc_sources clkset_uart = { | ||
| 506 | .sources = clkset_uart_list, | ||
| 507 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | ||
| 697 | }; | 508 | }; |
| 698 | 509 | ||
| 699 | static struct clk *clkset_audio1_list[] = { | 510 | static struct clk *clkset_audio1_list[] = { |
| @@ -705,30 +516,11 @@ static struct clk *clkset_audio1_list[] = { | |||
| 705 | &clk_mout_hpll.clk, | 516 | &clk_mout_hpll.clk, |
| 706 | }; | 517 | }; |
| 707 | 518 | ||
| 708 | static struct clk_sources clkset_audio1 = { | 519 | static struct clksrc_sources clkset_audio1 = { |
| 709 | .sources = clkset_audio1_list, | 520 | .sources = clkset_audio1_list, |
| 710 | .nr_sources = ARRAY_SIZE(clkset_audio1_list), | 521 | .nr_sources = ARRAY_SIZE(clkset_audio1_list), |
| 711 | }; | 522 | }; |
| 712 | 523 | ||
| 713 | static struct clksrc_clk clk_audio1 = { | ||
| 714 | .clk = { | ||
| 715 | .name = "audio-bus", | ||
| 716 | .id = 1, | ||
| 717 | .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, | ||
| 718 | .enable = s5pc100_sclk1_ctrl, | ||
| 719 | .set_parent = s5pc100_setparent_clksrc, | ||
| 720 | .get_rate = s5pc100_getrate_clksrc, | ||
| 721 | .set_rate = s5pc100_setrate_clksrc, | ||
| 722 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 723 | }, | ||
| 724 | .shift = S5PC100_CLKSRC3_AUDIO1_SHIFT, | ||
| 725 | .mask = S5PC100_CLKSRC3_AUDIO1_MASK, | ||
| 726 | .sources = &clkset_audio1, | ||
| 727 | .divider_shift = S5PC100_CLKDIV4_AUDIO1_SHIFT, | ||
| 728 | .reg_divider = S5PC100_CLKDIV4, | ||
| 729 | .reg_source = S5PC100_CLKSRC3, | ||
| 730 | }; | ||
| 731 | |||
| 732 | static struct clk *clkset_audio2_list[] = { | 524 | static struct clk *clkset_audio2_list[] = { |
| 733 | &clk_mout_epll.clk, | 525 | &clk_mout_epll.clk, |
| 734 | &clk_dout_mpll, | 526 | &clk_dout_mpll, |
| @@ -737,52 +529,56 @@ static struct clk *clkset_audio2_list[] = { | |||
| 737 | &clk_mout_hpll.clk, | 529 | &clk_mout_hpll.clk, |
| 738 | }; | 530 | }; |
| 739 | 531 | ||
| 740 | static struct clk_sources clkset_audio2 = { | 532 | static struct clksrc_sources clkset_audio2 = { |
| 741 | .sources = clkset_audio2_list, | 533 | .sources = clkset_audio2_list, |
| 742 | .nr_sources = ARRAY_SIZE(clkset_audio2_list), | 534 | .nr_sources = ARRAY_SIZE(clkset_audio2_list), |
| 743 | }; | 535 | }; |
| 744 | 536 | ||
| 745 | static struct clksrc_clk clk_audio2 = { | 537 | static struct clksrc_clk clksrc_audio[] = { |
| 746 | .clk = { | 538 | { |
| 747 | .name = "audio-bus", | 539 | .clk = { |
| 748 | .id = 2, | 540 | .name = "audio-bus", |
| 749 | .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, | 541 | .id = 0, |
| 750 | .enable = s5pc100_sclk1_ctrl, | 542 | .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, |
| 751 | .set_parent = s5pc100_setparent_clksrc, | 543 | .enable = s5pc100_sclk1_ctrl, |
| 752 | .get_rate = s5pc100_getrate_clksrc, | 544 | }, |
| 753 | .set_rate = s5pc100_setrate_clksrc, | 545 | .sources = &clkset_audio0, |
| 754 | .round_rate = s5pc100_roundrate_clksrc, | 546 | .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, }, |
| 547 | .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, }, | ||
| 548 | }, { | ||
| 549 | .clk = { | ||
| 550 | .name = "audio-bus", | ||
| 551 | .id = 1, | ||
| 552 | .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, | ||
| 553 | .enable = s5pc100_sclk1_ctrl, | ||
| 554 | }, | ||
| 555 | .sources = &clkset_audio1, | ||
| 556 | .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, }, | ||
| 557 | .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, }, | ||
| 558 | }, { | ||
| 559 | .clk = { | ||
| 560 | .name = "audio-bus", | ||
| 561 | .id = 2, | ||
| 562 | .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, | ||
| 563 | .enable = s5pc100_sclk1_ctrl, | ||
| 564 | }, | ||
| 565 | .sources = &clkset_audio2, | ||
| 566 | .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, }, | ||
| 567 | .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, }, | ||
| 755 | }, | 568 | }, |
| 756 | .shift = S5PC100_CLKSRC3_AUDIO2_SHIFT, | ||
| 757 | .mask = S5PC100_CLKSRC3_AUDIO2_MASK, | ||
| 758 | .sources = &clkset_audio2, | ||
| 759 | .divider_shift = S5PC100_CLKDIV4_AUDIO2_SHIFT, | ||
| 760 | .reg_divider = S5PC100_CLKDIV4, | ||
| 761 | .reg_source = S5PC100_CLKSRC3, | ||
| 762 | }; | 569 | }; |
| 763 | 570 | ||
| 764 | static struct clk *clkset_spdif_list[] = { | 571 | static struct clk *clkset_spdif_list[] = { |
| 765 | &clk_audio0.clk, | 572 | &clksrc_audio[0].clk, |
| 766 | &clk_audio1.clk, | 573 | &clksrc_audio[1].clk, |
| 767 | &clk_audio2.clk, | 574 | &clksrc_audio[2].clk, |
| 768 | }; | 575 | }; |
| 769 | 576 | ||
| 770 | static struct clk_sources clkset_spdif = { | 577 | static struct clksrc_sources clkset_spdif = { |
| 771 | .sources = clkset_spdif_list, | 578 | .sources = clkset_spdif_list, |
| 772 | .nr_sources = ARRAY_SIZE(clkset_spdif_list), | 579 | .nr_sources = ARRAY_SIZE(clkset_spdif_list), |
| 773 | }; | 580 | }; |
| 774 | 581 | ||
| 775 | static struct clksrc_clk clk_spdif = { | ||
| 776 | .clk = { | ||
| 777 | .name = "spdif", | ||
| 778 | .id = -1, | ||
| 779 | }, | ||
| 780 | .shift = S5PC100_CLKSRC3_SPDIF_SHIFT, | ||
| 781 | .mask = S5PC100_CLKSRC3_SPDIF_MASK, | ||
| 782 | .sources = &clkset_spdif, | ||
| 783 | .reg_source = S5PC100_CLKSRC3, | ||
| 784 | }; | ||
| 785 | |||
| 786 | static struct clk *clkset_lcd_fimc_list[] = { | 582 | static struct clk *clkset_lcd_fimc_list[] = { |
| 787 | &clk_mout_epll.clk, | 583 | &clk_mout_epll.clk, |
| 788 | &clk_dout_mpll, | 584 | &clk_dout_mpll, |
| @@ -790,87 +586,11 @@ static struct clk *clkset_lcd_fimc_list[] = { | |||
| 790 | &clk_vclk_54m, | 586 | &clk_vclk_54m, |
| 791 | }; | 587 | }; |
| 792 | 588 | ||
| 793 | static struct clk_sources clkset_lcd_fimc = { | 589 | static struct clksrc_sources clkset_lcd_fimc = { |
| 794 | .sources = clkset_lcd_fimc_list, | 590 | .sources = clkset_lcd_fimc_list, |
| 795 | .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list), | 591 | .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list), |
| 796 | }; | 592 | }; |
| 797 | 593 | ||
| 798 | static struct clksrc_clk clk_lcd = { | ||
| 799 | .clk = { | ||
| 800 | .name = "lcd", | ||
| 801 | .id = -1, | ||
| 802 | .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, | ||
| 803 | .enable = s5pc100_sclk1_ctrl, | ||
| 804 | .set_parent = s5pc100_setparent_clksrc, | ||
| 805 | .get_rate = s5pc100_getrate_clksrc, | ||
| 806 | .set_rate = s5pc100_setrate_clksrc, | ||
| 807 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 808 | }, | ||
| 809 | .shift = S5PC100_CLKSRC2_LCD_SHIFT, | ||
| 810 | .mask = S5PC100_CLKSRC2_LCD_MASK, | ||
| 811 | .sources = &clkset_lcd_fimc, | ||
| 812 | .divider_shift = S5PC100_CLKDIV3_LCD_SHIFT, | ||
| 813 | .reg_divider = S5PC100_CLKDIV3, | ||
| 814 | .reg_source = S5PC100_CLKSRC2, | ||
| 815 | }; | ||
| 816 | |||
| 817 | static struct clksrc_clk clk_fimc0 = { | ||
| 818 | .clk = { | ||
| 819 | .name = "fimc", | ||
| 820 | .id = 0, | ||
| 821 | .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, | ||
| 822 | .enable = s5pc100_sclk1_ctrl, | ||
| 823 | .set_parent = s5pc100_setparent_clksrc, | ||
| 824 | .get_rate = s5pc100_getrate_clksrc, | ||
| 825 | .set_rate = s5pc100_setrate_clksrc, | ||
| 826 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 827 | }, | ||
| 828 | .shift = S5PC100_CLKSRC2_FIMC0_SHIFT, | ||
| 829 | .mask = S5PC100_CLKSRC2_FIMC0_MASK, | ||
| 830 | .sources = &clkset_lcd_fimc, | ||
| 831 | .divider_shift = S5PC100_CLKDIV3_FIMC0_SHIFT, | ||
| 832 | .reg_divider = S5PC100_CLKDIV3, | ||
| 833 | .reg_source = S5PC100_CLKSRC2, | ||
| 834 | }; | ||
| 835 | |||
| 836 | static struct clksrc_clk clk_fimc1 = { | ||
| 837 | .clk = { | ||
| 838 | .name = "fimc", | ||
| 839 | .id = 1, | ||
| 840 | .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, | ||
| 841 | .enable = s5pc100_sclk1_ctrl, | ||
| 842 | .set_parent = s5pc100_setparent_clksrc, | ||
| 843 | .get_rate = s5pc100_getrate_clksrc, | ||
| 844 | .set_rate = s5pc100_setrate_clksrc, | ||
| 845 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 846 | }, | ||
| 847 | .shift = S5PC100_CLKSRC2_FIMC1_SHIFT, | ||
| 848 | .mask = S5PC100_CLKSRC2_FIMC1_MASK, | ||
| 849 | .sources = &clkset_lcd_fimc, | ||
| 850 | .divider_shift = S5PC100_CLKDIV3_FIMC1_SHIFT, | ||
| 851 | .reg_divider = S5PC100_CLKDIV3, | ||
| 852 | .reg_source = S5PC100_CLKSRC2, | ||
| 853 | }; | ||
| 854 | |||
| 855 | static struct clksrc_clk clk_fimc2 = { | ||
| 856 | .clk = { | ||
| 857 | .name = "fimc", | ||
| 858 | .id = 2, | ||
| 859 | .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2, | ||
| 860 | .enable = s5pc100_sclk1_ctrl, | ||
| 861 | .set_parent = s5pc100_setparent_clksrc, | ||
| 862 | .get_rate = s5pc100_getrate_clksrc, | ||
| 863 | .set_rate = s5pc100_setrate_clksrc, | ||
| 864 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 865 | }, | ||
| 866 | .shift = S5PC100_CLKSRC2_FIMC2_SHIFT, | ||
| 867 | .mask = S5PC100_CLKSRC2_FIMC2_MASK, | ||
| 868 | .sources = &clkset_lcd_fimc, | ||
| 869 | .divider_shift = S5PC100_CLKDIV3_FIMC2_SHIFT, | ||
| 870 | .reg_divider = S5PC100_CLKDIV3, | ||
| 871 | .reg_source = S5PC100_CLKSRC2, | ||
| 872 | }; | ||
| 873 | |||
| 874 | static struct clk *clkset_mmc_list[] = { | 594 | static struct clk *clkset_mmc_list[] = { |
| 875 | &clk_mout_epll.clk, | 595 | &clk_mout_epll.clk, |
| 876 | &clk_dout_mpll, | 596 | &clk_dout_mpll, |
| @@ -878,69 +598,11 @@ static struct clk *clkset_mmc_list[] = { | |||
| 878 | &clk_mout_hpll.clk , | 598 | &clk_mout_hpll.clk , |
| 879 | }; | 599 | }; |
| 880 | 600 | ||
| 881 | static struct clk_sources clkset_mmc = { | 601 | static struct clksrc_sources clkset_mmc = { |
| 882 | .sources = clkset_mmc_list, | 602 | .sources = clkset_mmc_list, |
| 883 | .nr_sources = ARRAY_SIZE(clkset_mmc_list), | 603 | .nr_sources = ARRAY_SIZE(clkset_mmc_list), |
| 884 | }; | 604 | }; |
| 885 | 605 | ||
| 886 | static struct clksrc_clk clk_mmc0 = { | ||
| 887 | .clk = { | ||
| 888 | .name = "mmc_bus", | ||
| 889 | .id = 0, | ||
| 890 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0, | ||
| 891 | .enable = s5pc100_sclk0_ctrl, | ||
| 892 | .set_parent = s5pc100_setparent_clksrc, | ||
| 893 | .get_rate = s5pc100_getrate_clksrc, | ||
| 894 | .set_rate = s5pc100_setrate_clksrc, | ||
| 895 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 896 | }, | ||
| 897 | .shift = S5PC100_CLKSRC2_MMC0_SHIFT, | ||
| 898 | .mask = S5PC100_CLKSRC2_MMC0_MASK, | ||
| 899 | .sources = &clkset_mmc, | ||
| 900 | .divider_shift = S5PC100_CLKDIV3_MMC0_SHIFT, | ||
| 901 | .reg_divider = S5PC100_CLKDIV3, | ||
| 902 | .reg_source = S5PC100_CLKSRC2, | ||
| 903 | }; | ||
| 904 | |||
| 905 | static struct clksrc_clk clk_mmc1 = { | ||
| 906 | .clk = { | ||
| 907 | .name = "mmc_bus", | ||
| 908 | .id = 1, | ||
| 909 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1, | ||
| 910 | .enable = s5pc100_sclk0_ctrl, | ||
| 911 | .set_parent = s5pc100_setparent_clksrc, | ||
| 912 | .get_rate = s5pc100_getrate_clksrc, | ||
| 913 | .set_rate = s5pc100_setrate_clksrc, | ||
| 914 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 915 | }, | ||
| 916 | .shift = S5PC100_CLKSRC2_MMC1_SHIFT, | ||
| 917 | .mask = S5PC100_CLKSRC2_MMC1_MASK, | ||
| 918 | .sources = &clkset_mmc, | ||
| 919 | .divider_shift = S5PC100_CLKDIV3_MMC1_SHIFT, | ||
| 920 | .reg_divider = S5PC100_CLKDIV3, | ||
| 921 | .reg_source = S5PC100_CLKSRC2, | ||
| 922 | }; | ||
| 923 | |||
| 924 | static struct clksrc_clk clk_mmc2 = { | ||
| 925 | .clk = { | ||
| 926 | .name = "mmc_bus", | ||
| 927 | .id = 2, | ||
| 928 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2, | ||
| 929 | .enable = s5pc100_sclk0_ctrl, | ||
| 930 | .set_parent = s5pc100_setparent_clksrc, | ||
| 931 | .get_rate = s5pc100_getrate_clksrc, | ||
| 932 | .set_rate = s5pc100_setrate_clksrc, | ||
| 933 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 934 | }, | ||
| 935 | .shift = S5PC100_CLKSRC2_MMC2_SHIFT, | ||
| 936 | .mask = S5PC100_CLKSRC2_MMC2_MASK, | ||
| 937 | .sources = &clkset_mmc, | ||
| 938 | .divider_shift = S5PC100_CLKDIV3_MMC2_SHIFT, | ||
| 939 | .reg_divider = S5PC100_CLKDIV3, | ||
| 940 | .reg_source = S5PC100_CLKSRC2, | ||
| 941 | }; | ||
| 942 | |||
| 943 | |||
| 944 | static struct clk *clkset_usbhost_list[] = { | 606 | static struct clk *clkset_usbhost_list[] = { |
| 945 | &clk_mout_epll.clk, | 607 | &clk_mout_epll.clk, |
| 946 | &clk_dout_mpll, | 608 | &clk_dout_mpll, |
| @@ -948,28 +610,141 @@ static struct clk *clkset_usbhost_list[] = { | |||
| 948 | &clk_48m, | 610 | &clk_48m, |
| 949 | }; | 611 | }; |
| 950 | 612 | ||
| 951 | static struct clk_sources clkset_usbhost = { | 613 | static struct clksrc_sources clkset_usbhost = { |
| 952 | .sources = clkset_usbhost_list, | 614 | .sources = clkset_usbhost_list, |
| 953 | .nr_sources = ARRAY_SIZE(clkset_usbhost_list), | 615 | .nr_sources = ARRAY_SIZE(clkset_usbhost_list), |
| 954 | }; | 616 | }; |
| 955 | 617 | ||
| 956 | static struct clksrc_clk clk_usbhost = { | 618 | static struct clksrc_clk clksrc_clks[] = { |
| 957 | .clk = { | 619 | { |
| 958 | .name = "usbhost", | 620 | .clk = { |
| 959 | .id = -1, | 621 | .name = "spi_bus", |
| 960 | .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST, | 622 | .id = 0, |
| 961 | .enable = s5pc100_sclk0_ctrl, | 623 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0, |
| 962 | .set_parent = s5pc100_setparent_clksrc, | 624 | .enable = s5pc100_sclk0_ctrl, |
| 963 | .get_rate = s5pc100_getrate_clksrc, | 625 | |
| 964 | .set_rate = s5pc100_setrate_clksrc, | 626 | }, |
| 965 | .round_rate = s5pc100_roundrate_clksrc, | 627 | .sources = &clkset_spi, |
| 966 | }, | 628 | .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, }, |
| 967 | .shift = S5PC100_CLKSRC1_UHOST_SHIFT, | 629 | .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, }, |
| 968 | .mask = S5PC100_CLKSRC1_UHOST_MASK, | 630 | }, { |
| 969 | .sources = &clkset_usbhost, | 631 | .clk = { |
| 970 | .divider_shift = S5PC100_CLKDIV2_UHOST_SHIFT, | 632 | .name = "spi_bus", |
| 971 | .reg_divider = S5PC100_CLKDIV2, | 633 | .id = 1, |
| 972 | .reg_source = S5PC100_CLKSRC1, | 634 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, |
| 635 | .enable = s5pc100_sclk0_ctrl, | ||
| 636 | }, | ||
| 637 | .sources = &clkset_spi, | ||
| 638 | .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, }, | ||
| 639 | .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, }, | ||
| 640 | }, { | ||
| 641 | .clk = { | ||
| 642 | .name = "spi_bus", | ||
| 643 | .id = 2, | ||
| 644 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, | ||
| 645 | .enable = s5pc100_sclk0_ctrl, | ||
| 646 | }, | ||
| 647 | .sources = &clkset_spi, | ||
| 648 | .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, }, | ||
| 649 | .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, }, | ||
| 650 | }, { | ||
| 651 | .clk = { | ||
| 652 | .name = "uclk1", | ||
| 653 | .id = -1, | ||
| 654 | .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, | ||
| 655 | .enable = s5pc100_sclk0_ctrl, | ||
| 656 | }, | ||
| 657 | .sources = &clkset_uart, | ||
| 658 | .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, }, | ||
| 659 | .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, }, | ||
| 660 | }, { | ||
| 661 | .clk = { | ||
| 662 | .name = "spdif", | ||
| 663 | .id = -1, | ||
| 664 | }, | ||
| 665 | .sources = &clkset_spdif, | ||
| 666 | .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, }, | ||
| 667 | }, { | ||
| 668 | .clk = { | ||
| 669 | .name = "lcd", | ||
| 670 | .id = -1, | ||
| 671 | .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, | ||
| 672 | .enable = s5pc100_sclk1_ctrl, | ||
| 673 | }, | ||
| 674 | .sources = &clkset_lcd_fimc, | ||
| 675 | .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, }, | ||
| 676 | .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, }, | ||
| 677 | }, { | ||
| 678 | .clk = { | ||
| 679 | .name = "fimc", | ||
| 680 | .id = 0, | ||
| 681 | .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, | ||
| 682 | .enable = s5pc100_sclk1_ctrl, | ||
| 683 | }, | ||
| 684 | .sources = &clkset_lcd_fimc, | ||
| 685 | .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, }, | ||
| 686 | .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, }, | ||
| 687 | }, { | ||
| 688 | .clk = { | ||
| 689 | .name = "fimc", | ||
| 690 | .id = 1, | ||
| 691 | .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, | ||
| 692 | .enable = s5pc100_sclk1_ctrl, | ||
| 693 | }, | ||
| 694 | .sources = &clkset_lcd_fimc, | ||
| 695 | .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, }, | ||
| 696 | .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, }, | ||
| 697 | }, { | ||
| 698 | .clk = { | ||
| 699 | .name = "fimc", | ||
| 700 | .id = 2, | ||
| 701 | .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2, | ||
| 702 | .enable = s5pc100_sclk1_ctrl, | ||
| 703 | }, | ||
| 704 | .sources = &clkset_lcd_fimc, | ||
| 705 | .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, }, | ||
| 706 | .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, }, | ||
| 707 | }, { | ||
| 708 | .clk = { | ||
| 709 | .name = "mmc_bus", | ||
| 710 | .id = 0, | ||
| 711 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0, | ||
| 712 | .enable = s5pc100_sclk0_ctrl, | ||
| 713 | }, | ||
| 714 | .sources = &clkset_mmc, | ||
| 715 | .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, }, | ||
| 716 | .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, }, | ||
| 717 | }, { | ||
| 718 | .clk = { | ||
| 719 | .name = "mmc_bus", | ||
| 720 | .id = 1, | ||
| 721 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1, | ||
| 722 | .enable = s5pc100_sclk0_ctrl, | ||
| 723 | }, | ||
| 724 | .sources = &clkset_mmc, | ||
| 725 | .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, }, | ||
| 726 | .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, }, | ||
| 727 | }, { | ||
| 728 | .clk = { | ||
| 729 | .name = "mmc_bus", | ||
| 730 | .id = 2, | ||
| 731 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2, | ||
| 732 | .enable = s5pc100_sclk0_ctrl, | ||
| 733 | }, | ||
| 734 | .sources = &clkset_mmc, | ||
| 735 | .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, }, | ||
| 736 | .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, }, | ||
| 737 | }, { | ||
| 738 | .clk = { | ||
| 739 | .name = "usbhost", | ||
| 740 | .id = -1, | ||
| 741 | .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST, | ||
| 742 | .enable = s5pc100_sclk0_ctrl, | ||
| 743 | }, | ||
| 744 | .sources = &clkset_usbhost, | ||
| 745 | .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, }, | ||
| 746 | .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, }, | ||
| 747 | } | ||
| 973 | }; | 748 | }; |
| 974 | 749 | ||
| 975 | /* Clock initialisation code */ | 750 | /* Clock initialisation code */ |
| @@ -981,45 +756,8 @@ static struct clksrc_clk *init_parents[] = { | |||
| 981 | &clk_mout_onenand, | 756 | &clk_mout_onenand, |
| 982 | &clk_mout_epll, | 757 | &clk_mout_epll, |
| 983 | &clk_mout_hpll, | 758 | &clk_mout_hpll, |
| 984 | &clk_spi0, | ||
| 985 | &clk_spi1, | ||
| 986 | &clk_spi2, | ||
| 987 | &clk_uart_uclk1, | ||
| 988 | &clk_audio0, | ||
| 989 | &clk_audio1, | ||
| 990 | &clk_audio2, | ||
| 991 | &clk_spdif, | ||
| 992 | &clk_lcd, | ||
| 993 | &clk_fimc0, | ||
| 994 | &clk_fimc1, | ||
| 995 | &clk_fimc2, | ||
| 996 | &clk_mmc0, | ||
| 997 | &clk_mmc1, | ||
| 998 | &clk_mmc2, | ||
| 999 | &clk_usbhost, | ||
| 1000 | }; | 759 | }; |
| 1001 | 760 | ||
| 1002 | static void __init_or_cpufreq s5pc100_set_clksrc(struct clksrc_clk *clk) | ||
| 1003 | { | ||
| 1004 | struct clk_sources *srcs = clk->sources; | ||
| 1005 | u32 clksrc = __raw_readl(clk->reg_source); | ||
| 1006 | |||
| 1007 | clksrc &= clk->mask; | ||
| 1008 | clksrc >>= clk->shift; | ||
| 1009 | |||
| 1010 | if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { | ||
| 1011 | printk(KERN_ERR "%s: bad source %d\n", | ||
| 1012 | clk->clk.name, clksrc); | ||
| 1013 | return; | ||
| 1014 | } | ||
| 1015 | |||
| 1016 | clk->clk.parent = srcs->sources[clksrc]; | ||
| 1017 | |||
| 1018 | printk(KERN_INFO "%s: source is %s (%d), rate is %ld.%03ld MHz\n", | ||
| 1019 | clk->clk.name, clk->clk.parent->name, clksrc, | ||
| 1020 | print_mhz(clk_get_rate(&clk->clk))); | ||
| 1021 | } | ||
| 1022 | |||
| 1023 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) | 761 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) |
| 1024 | 762 | ||
| 1025 | void __init_or_cpufreq s5pc100_setup_clocks(void) | 763 | void __init_or_cpufreq s5pc100_setup_clocks(void) |
| @@ -1083,17 +821,25 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) | |||
| 1083 | clk_f.rate = armclk; | 821 | clk_f.rate = armclk; |
| 1084 | 822 | ||
| 1085 | for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) | 823 | for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) |
| 1086 | s5pc100_set_clksrc(init_parents[ptr]); | 824 | s3c_set_clksrc(init_parents[ptr], true); |
| 825 | |||
| 826 | for (ptr = 0; ptr < ARRAY_SIZE(clksrc_audio); ptr++) | ||
| 827 | s3c_set_clksrc(clksrc_audio + ptr, true); | ||
| 828 | |||
| 829 | for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++) | ||
| 830 | s3c_set_clksrc(clksrc_clks + ptr, true); | ||
| 1087 | } | 831 | } |
| 1088 | 832 | ||
| 1089 | static struct clk *clks[] __initdata = { | 833 | static struct clk *clks[] __initdata = { |
| 1090 | &clk_ext_xtal_mux, | 834 | &clk_ext_xtal_mux, |
| 1091 | &clk_mout_apll.clk, | ||
| 1092 | &clk_dout_apll, | 835 | &clk_dout_apll, |
| 1093 | &clk_dout_d0_bus, | 836 | &clk_dout_d0_bus, |
| 1094 | &clk_dout_pclkd0, | 837 | &clk_dout_pclkd0, |
| 1095 | &clk_dout_apll2, | 838 | &clk_dout_apll2, |
| 839 | &clk_mout_apll.clk, | ||
| 1096 | &clk_mout_mpll.clk, | 840 | &clk_mout_mpll.clk, |
| 841 | &clk_mout_epll.clk, | ||
| 842 | &clk_mout_hpll.clk, | ||
| 1097 | &clk_mout_am.clk, | 843 | &clk_mout_am.clk, |
| 1098 | &clk_dout_d1_bus, | 844 | &clk_dout_d1_bus, |
| 1099 | &clk_mout_onenand.clk, | 845 | &clk_mout_onenand.clk, |
| @@ -1101,29 +847,12 @@ static struct clk *clks[] __initdata = { | |||
| 1101 | &clk_dout_mpll2, | 847 | &clk_dout_mpll2, |
| 1102 | &clk_dout_cam, | 848 | &clk_dout_cam, |
| 1103 | &clk_dout_mpll, | 849 | &clk_dout_mpll, |
| 1104 | &clk_mout_epll.clk, | ||
| 1105 | &clk_fout_epll, | 850 | &clk_fout_epll, |
| 1106 | &clk_iis_cd0, | 851 | &clk_iis_cd0, |
| 1107 | &clk_iis_cd1, | 852 | &clk_iis_cd1, |
| 1108 | &clk_iis_cd2, | 853 | &clk_iis_cd2, |
| 1109 | &clk_pcm_cd0, | 854 | &clk_pcm_cd0, |
| 1110 | &clk_pcm_cd1, | 855 | &clk_pcm_cd1, |
| 1111 | &clk_spi0.clk, | ||
| 1112 | &clk_spi1.clk, | ||
| 1113 | &clk_spi2.clk, | ||
| 1114 | &clk_uart_uclk1.clk, | ||
| 1115 | &clk_audio0.clk, | ||
| 1116 | &clk_audio1.clk, | ||
| 1117 | &clk_audio2.clk, | ||
| 1118 | &clk_spdif.clk, | ||
| 1119 | &clk_lcd.clk, | ||
| 1120 | &clk_fimc0.clk, | ||
| 1121 | &clk_fimc1.clk, | ||
| 1122 | &clk_fimc2.clk, | ||
| 1123 | &clk_mmc0.clk, | ||
| 1124 | &clk_mmc1.clk, | ||
| 1125 | &clk_mmc2.clk, | ||
| 1126 | &clk_usbhost.clk, | ||
| 1127 | &clk_arm, | 856 | &clk_arm, |
| 1128 | }; | 857 | }; |
| 1129 | 858 | ||
| @@ -1141,4 +870,7 @@ void __init s5pc100_register_clocks(void) | |||
| 1141 | clkp->name, ret); | 870 | clkp->name, ret); |
| 1142 | } | 871 | } |
| 1143 | } | 872 | } |
| 873 | |||
| 874 | s3c_register_clksrc(clksrc_audio, ARRAY_SIZE(clksrc_audio)); | ||
| 875 | s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks)); | ||
| 1144 | } | 876 | } |
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 486a0d6301e7..1c2fe91c23e9 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig | |||
| @@ -13,5 +13,168 @@ config PLAT_SAMSUNG | |||
| 13 | 13 | ||
| 14 | if PLAT_SAMSUNG | 14 | if PLAT_SAMSUNG |
| 15 | 15 | ||
| 16 | config SAMSUNG_CLKSRC | ||
| 17 | bool | ||
| 18 | help | ||
| 19 | Select the clock code for the clksrc implementation | ||
| 20 | used by newer systems such as the S3C64XX. | ||
| 21 | |||
| 22 | # options for IRQ support | ||
| 23 | |||
| 24 | config SAMSUNG_IRQ_VIC_TIMER | ||
| 25 | bool | ||
| 26 | help | ||
| 27 | Internal configuration to build the VIC timer interrupt code. | ||
| 28 | |||
| 29 | config SAMSUNG_IRQ_UART | ||
| 30 | bool | ||
| 31 | help | ||
| 32 | Internal configuration to build the IRQ UART demux code. | ||
| 33 | |||
| 34 | # options for gpio configuration support | ||
| 35 | |||
| 36 | config SAMSUNG_GPIOLIB_4BIT | ||
| 37 | bool | ||
| 38 | help | ||
| 39 | GPIOlib file contains the 4 bit modification functions for gpio | ||
| 40 | configuration. GPIOlib shall be compiled only for S3C64XX and S5P | ||
| 41 | series of processors. | ||
| 42 | |||
| 43 | config S3C_GPIO_CFG_S3C24XX | ||
| 44 | bool | ||
| 45 | help | ||
| 46 | Internal configuration to enable S3C24XX style GPIO configuration | ||
| 47 | functions. | ||
| 48 | |||
| 49 | config S3C_GPIO_CFG_S3C64XX | ||
| 50 | bool | ||
| 51 | help | ||
| 52 | Internal configuration to enable S3C64XX style GPIO configuration | ||
| 53 | functions. | ||
| 54 | |||
| 55 | config S5P_GPIO_CFG_S5PC1XX | ||
| 56 | bool | ||
| 57 | help | ||
| 58 | Internal configuration to enable S5PC1XX style GPIO configuration | ||
| 59 | functions. | ||
| 60 | |||
| 61 | config S3C_GPIO_PULL_UPDOWN | ||
| 62 | bool | ||
| 63 | help | ||
| 64 | Internal configuration to enable the correct GPIO pull helper | ||
| 65 | |||
| 66 | config S3C_GPIO_PULL_DOWN | ||
| 67 | bool | ||
| 68 | help | ||
| 69 | Internal configuration to enable the correct GPIO pull helper | ||
| 70 | |||
| 71 | config S3C_GPIO_PULL_UP | ||
| 72 | bool | ||
| 73 | help | ||
| 74 | Internal configuration to enable the correct GPIO pull helper | ||
| 75 | |||
| 76 | config SAMSUNG_GPIO_EXTRA | ||
| 77 | int "Number of additional GPIO pins" | ||
| 78 | default 0 | ||
| 79 | help | ||
| 80 | Use additional GPIO space in addition to the GPIO's the SOC | ||
| 81 | provides. This allows expanding the GPIO space for use with | ||
| 82 | GPIO expanders. | ||
| 83 | |||
| 84 | # ADC driver | ||
| 85 | |||
| 86 | config S3C_ADC | ||
| 87 | bool "ADC common driver support" | ||
| 88 | help | ||
| 89 | Core support for the ADC block found in the Samsung SoC systems | ||
| 90 | for drivers such as the touchscreen and hwmon to use to share | ||
| 91 | this resource. | ||
| 92 | |||
| 93 | # device definitions to compile in | ||
| 94 | |||
| 95 | config S3C_DEV_HSMMC | ||
| 96 | bool | ||
| 97 | help | ||
| 98 | Compile in platform device definitions for HSMMC code | ||
| 99 | |||
| 100 | config S3C_DEV_HSMMC1 | ||
| 101 | bool | ||
| 102 | help | ||
| 103 | Compile in platform device definitions for HSMMC channel 1 | ||
| 104 | |||
| 105 | config S3C_DEV_HSMMC2 | ||
| 106 | bool | ||
| 107 | help | ||
| 108 | Compile in platform device definitions for HSMMC channel 2 | ||
| 109 | |||
| 110 | config S3C_DEV_I2C1 | ||
| 111 | bool | ||
| 112 | help | ||
| 113 | Compile in platform device definitions for I2C channel 1 | ||
| 114 | |||
| 115 | config S3C_DEV_FB | ||
| 116 | bool | ||
| 117 | help | ||
| 118 | Compile in platform device definition for framebuffer | ||
| 119 | |||
| 120 | config S3C_DEV_USB_HOST | ||
| 121 | bool | ||
| 122 | help | ||
| 123 | Compile in platform device definition for USB host. | ||
| 124 | |||
| 125 | config S3C_DEV_USB_HSOTG | ||
| 126 | bool | ||
| 127 | help | ||
| 128 | Compile in platform device definition for USB high-speed OtG | ||
| 129 | |||
| 130 | config S3C_DEV_NAND | ||
| 131 | bool | ||
| 132 | help | ||
| 133 | Compile in platform device definition for NAND controller | ||
| 134 | |||
| 135 | comment "Power management" | ||
| 136 | |||
| 137 | config SAMSUNG_PM_DEBUG | ||
| 138 | bool "S3C2410 PM Suspend debug" | ||
| 139 | depends on PM | ||
| 140 | help | ||
| 141 | Say Y here if you want verbose debugging from the PM Suspend and | ||
| 142 | Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> | ||
| 143 | for more information. | ||
| 144 | |||
| 145 | config S3C_PM_DEBUG_LED_SMDK | ||
| 146 | bool "SMDK LED suspend/resume debugging" | ||
| 147 | depends on PM && (MACH_SMDK6410) | ||
| 148 | help | ||
| 149 | Say Y here to enable the use of the SMDK LEDs on the baseboard | ||
| 150 | for debugging of the state of the suspend and resume process. | ||
| 151 | |||
| 152 | Note, this currently only works for S3C64XX based SMDK boards. | ||
| 153 | |||
| 154 | config SAMSUNG_PM_CHECK | ||
| 155 | bool "S3C2410 PM Suspend Memory CRC" | ||
| 156 | depends on PM && CRC32 | ||
| 157 | help | ||
| 158 | Enable the PM code's memory area checksum over sleep. This option | ||
| 159 | will generate CRCs of all blocks of memory, and store them before | ||
| 160 | going to sleep. The blocks are then checked on resume for any | ||
| 161 | errors. | ||
| 162 | |||
| 163 | Note, this can take several seconds depending on memory size | ||
| 164 | and CPU speed. | ||
| 165 | |||
| 166 | See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> | ||
| 167 | |||
| 168 | config SAMSUNG_PM_CHECK_CHUNKSIZE | ||
| 169 | int "S3C2410 PM Suspend CRC Chunksize (KiB)" | ||
| 170 | depends on PM && SAMSUNG_PM_CHECK | ||
| 171 | default 64 | ||
| 172 | help | ||
| 173 | Set the chunksize in Kilobytes of the CRC for checking memory | ||
| 174 | corruption over suspend and resume. A smaller value will mean that | ||
| 175 | the CRC data block will take more memory, but wil identify any | ||
| 176 | faults with better precision. | ||
| 177 | |||
| 178 | See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> | ||
| 16 | 179 | ||
| 17 | endif | 180 | endif |
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 4478b9f7dc34..c8c8caec8cde 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile | |||
| @@ -9,3 +9,41 @@ obj-m := | |||
| 9 | obj-n := dummy.o | 9 | obj-n := dummy.o |
| 10 | obj- := | 10 | obj- := |
| 11 | 11 | ||
| 12 | # Objects we always build independent of SoC choice | ||
| 13 | |||
| 14 | obj-y += clock.o | ||
| 15 | obj-y += pwm-clock.o | ||
| 16 | obj-y += gpio.o | ||
| 17 | obj-y += gpio-config.o | ||
| 18 | |||
| 19 | obj-$(CONFIG_SAMSUNG_GPIOLIB_4BIT) += gpiolib.o | ||
| 20 | obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o | ||
| 21 | |||
| 22 | obj-$(CONFIG_SAMSUNG_IRQ_UART) += irq-uart.o | ||
| 23 | obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o | ||
| 24 | |||
| 25 | # ADC | ||
| 26 | |||
| 27 | obj-$(CONFIG_S3C_ADC) += adc.o | ||
| 28 | |||
| 29 | # devices | ||
| 30 | |||
| 31 | obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o | ||
| 32 | obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o | ||
| 33 | obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o | ||
| 34 | obj-y += dev-i2c0.o | ||
| 35 | obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o | ||
| 36 | obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o | ||
| 37 | obj-y += dev-uart.o | ||
| 38 | obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o | ||
| 39 | obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o | ||
| 40 | obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o | ||
| 41 | |||
| 42 | # PM support | ||
| 43 | |||
| 44 | obj-$(CONFIG_PM) += pm-gpio.o | ||
| 45 | obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o | ||
| 46 | |||
| 47 | # PWM support | ||
| 48 | |||
| 49 | obj-$(CONFIG_HAVE_PWM) += pwm.o | ||
diff --git a/arch/arm/plat-s3c24xx/adc.c b/arch/arm/plat-samsung/adc.c index ce47627f3368..c7659b7378b1 100644 --- a/arch/arm/plat-s3c24xx/adc.c +++ b/arch/arm/plat-samsung/adc.c | |||
| @@ -1,10 +1,10 @@ | |||
| 1 | /* arch/arm/plat-s3c24xx/adc.c | 1 | /* arch/arm/plat-samsung/adc.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2008 Simtec Electronics | 3 | * Copyright (c) 2008 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> | 5 | * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> |
| 6 | * | 6 | * |
| 7 | * S3C24XX ADC device core | 7 | * Samsung ADC device core |
| 8 | * | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify | 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by | 10 | * it under the terms of the GNU General Public License as published by |
| @@ -37,6 +37,11 @@ | |||
| 37 | * action is required. | 37 | * action is required. |
| 38 | */ | 38 | */ |
| 39 | 39 | ||
| 40 | enum s3c_cpu_type { | ||
| 41 | TYPE_S3C24XX, | ||
| 42 | TYPE_S3C64XX | ||
| 43 | }; | ||
| 44 | |||
| 40 | struct s3c_adc_client { | 45 | struct s3c_adc_client { |
| 41 | struct platform_device *pdev; | 46 | struct platform_device *pdev; |
| 42 | struct list_head pend; | 47 | struct list_head pend; |
| @@ -262,7 +267,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) | |||
| 262 | 267 | ||
| 263 | if (!client) { | 268 | if (!client) { |
| 264 | dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__); | 269 | dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__); |
| 265 | return IRQ_HANDLED; | 270 | goto exit; |
| 266 | } | 271 | } |
| 267 | 272 | ||
| 268 | data0 = readl(adc->regs + S3C2410_ADCDAT0); | 273 | data0 = readl(adc->regs + S3C2410_ADCDAT0); |
| @@ -289,6 +294,11 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) | |||
| 289 | local_irq_restore(flags); | 294 | local_irq_restore(flags); |
| 290 | } | 295 | } |
| 291 | 296 | ||
| 297 | exit: | ||
| 298 | if (platform_get_device_id(adc->pdev)->driver_data == TYPE_S3C64XX) { | ||
| 299 | /* Clear ADC interrupt */ | ||
| 300 | writel(0, adc->regs + S3C64XX_ADCCLRINT); | ||
| 301 | } | ||
| 292 | return IRQ_HANDLED; | 302 | return IRQ_HANDLED; |
| 293 | } | 303 | } |
| 294 | 304 | ||
| @@ -410,9 +420,22 @@ static int s3c_adc_resume(struct platform_device *pdev) | |||
| 410 | #define s3c_adc_resume NULL | 420 | #define s3c_adc_resume NULL |
| 411 | #endif | 421 | #endif |
| 412 | 422 | ||
| 423 | static struct platform_device_id s3c_adc_driver_ids[] = { | ||
| 424 | { | ||
| 425 | .name = "s3c24xx-adc", | ||
| 426 | .driver_data = TYPE_S3C24XX, | ||
| 427 | }, { | ||
| 428 | .name = "s3c64xx-adc", | ||
| 429 | .driver_data = TYPE_S3C64XX, | ||
| 430 | }, | ||
| 431 | { } | ||
| 432 | }; | ||
| 433 | MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids); | ||
| 434 | |||
| 413 | static struct platform_driver s3c_adc_driver = { | 435 | static struct platform_driver s3c_adc_driver = { |
| 436 | .id_table = s3c_adc_driver_ids, | ||
| 414 | .driver = { | 437 | .driver = { |
| 415 | .name = "s3c24xx-adc", | 438 | .name = "s3c-adc", |
| 416 | .owner = THIS_MODULE, | 439 | .owner = THIS_MODULE, |
| 417 | }, | 440 | }, |
| 418 | .probe = s3c_adc_probe, | 441 | .probe = s3c_adc_probe, |
diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c new file mode 100644 index 000000000000..ae8b8507663f --- /dev/null +++ b/arch/arm/plat-samsung/clock-clksrc.c | |||
| @@ -0,0 +1,212 @@ | |||
| 1 | /* linux/arch/arm/plat-samsung/clock-clksrc.c | ||
| 2 | * | ||
| 3 | * Copyright 2008 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * http://armlinux.simtec.co.uk/ | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/module.h> | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/list.h> | ||
| 16 | #include <linux/errno.h> | ||
| 17 | #include <linux/err.h> | ||
| 18 | #include <linux/clk.h> | ||
| 19 | #include <linux/sysdev.h> | ||
| 20 | #include <linux/io.h> | ||
| 21 | |||
| 22 | #include <plat/clock.h> | ||
| 23 | #include <plat/clock-clksrc.h> | ||
| 24 | #include <plat/cpu-freq.h> | ||
| 25 | |||
| 26 | static inline struct clksrc_clk *to_clksrc(struct clk *clk) | ||
| 27 | { | ||
| 28 | return container_of(clk, struct clksrc_clk, clk); | ||
| 29 | } | ||
| 30 | |||
| 31 | static inline u32 bit_mask(u32 shift, u32 nr_bits) | ||
| 32 | { | ||
| 33 | u32 mask = 0xffffffff >> (32 - nr_bits); | ||
| 34 | |||
| 35 | return mask << shift; | ||
| 36 | } | ||
| 37 | |||
| 38 | static unsigned long s3c_getrate_clksrc(struct clk *clk) | ||
| 39 | { | ||
| 40 | struct clksrc_clk *sclk = to_clksrc(clk); | ||
| 41 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 42 | u32 clkdiv = __raw_readl(sclk->reg_div.reg); | ||
| 43 | u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size); | ||
| 44 | |||
| 45 | clkdiv &= mask; | ||
| 46 | clkdiv >>= sclk->reg_div.shift; | ||
| 47 | clkdiv++; | ||
| 48 | |||
| 49 | rate /= clkdiv; | ||
| 50 | return rate; | ||
| 51 | } | ||
| 52 | |||
| 53 | static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate) | ||
| 54 | { | ||
| 55 | struct clksrc_clk *sclk = to_clksrc(clk); | ||
| 56 | void __iomem *reg = sclk->reg_div.reg; | ||
| 57 | unsigned int div; | ||
| 58 | u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size); | ||
| 59 | u32 val; | ||
| 60 | |||
| 61 | rate = clk_round_rate(clk, rate); | ||
| 62 | div = clk_get_rate(clk->parent) / rate; | ||
| 63 | if (div > (1 << sclk->reg_div.size)) | ||
| 64 | return -EINVAL; | ||
| 65 | |||
| 66 | val = __raw_readl(reg); | ||
| 67 | val &= ~mask; | ||
| 68 | val |= (div - 1) << sclk->reg_div.shift; | ||
| 69 | __raw_writel(val, reg); | ||
| 70 | |||
| 71 | return 0; | ||
| 72 | } | ||
| 73 | |||
| 74 | static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent) | ||
| 75 | { | ||
| 76 | struct clksrc_clk *sclk = to_clksrc(clk); | ||
| 77 | struct clksrc_sources *srcs = sclk->sources; | ||
| 78 | u32 clksrc = __raw_readl(sclk->reg_src.reg); | ||
| 79 | u32 mask = bit_mask(sclk->reg_src.shift, sclk->reg_src.size); | ||
| 80 | int src_nr = -1; | ||
| 81 | int ptr; | ||
| 82 | |||
| 83 | for (ptr = 0; ptr < srcs->nr_sources; ptr++) | ||
| 84 | if (srcs->sources[ptr] == parent) { | ||
| 85 | src_nr = ptr; | ||
| 86 | break; | ||
| 87 | } | ||
| 88 | |||
| 89 | if (src_nr >= 0) { | ||
| 90 | clk->parent = parent; | ||
| 91 | |||
| 92 | clksrc &= ~mask; | ||
| 93 | clksrc |= src_nr << sclk->reg_src.shift; | ||
| 94 | |||
| 95 | __raw_writel(clksrc, sclk->reg_src.reg); | ||
| 96 | return 0; | ||
| 97 | } | ||
| 98 | |||
| 99 | return -EINVAL; | ||
| 100 | } | ||
| 101 | |||
| 102 | static unsigned long s3c_roundrate_clksrc(struct clk *clk, | ||
| 103 | unsigned long rate) | ||
| 104 | { | ||
| 105 | struct clksrc_clk *sclk = to_clksrc(clk); | ||
| 106 | unsigned long parent_rate = clk_get_rate(clk->parent); | ||
| 107 | int max_div = 1 << sclk->reg_div.size; | ||
| 108 | int div; | ||
| 109 | |||
| 110 | if (rate >= parent_rate) | ||
| 111 | rate = parent_rate; | ||
| 112 | else { | ||
| 113 | div = parent_rate / rate; | ||
| 114 | if (parent_rate % rate) | ||
| 115 | div++; | ||
| 116 | |||
| 117 | if (div == 0) | ||
| 118 | div = 1; | ||
| 119 | if (div > max_div) | ||
| 120 | div = max_div; | ||
| 121 | |||
| 122 | rate = parent_rate / div; | ||
| 123 | } | ||
| 124 | |||
| 125 | return rate; | ||
| 126 | } | ||
| 127 | |||
| 128 | /* Clock initialisation code */ | ||
| 129 | |||
| 130 | void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk, bool announce) | ||
| 131 | { | ||
| 132 | struct clksrc_sources *srcs = clk->sources; | ||
| 133 | u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size); | ||
| 134 | u32 clksrc; | ||
| 135 | |||
| 136 | if (!clk->reg_src.reg) { | ||
| 137 | if (!clk->clk.parent) | ||
| 138 | printk(KERN_ERR "%s: no parent clock specified\n", | ||
| 139 | clk->clk.name); | ||
| 140 | return; | ||
| 141 | } | ||
| 142 | |||
| 143 | clksrc = __raw_readl(clk->reg_src.reg); | ||
| 144 | clksrc &= mask; | ||
| 145 | clksrc >>= clk->reg_src.shift; | ||
| 146 | |||
| 147 | if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { | ||
| 148 | printk(KERN_ERR "%s: bad source %d\n", | ||
| 149 | clk->clk.name, clksrc); | ||
| 150 | return; | ||
| 151 | } | ||
| 152 | |||
| 153 | clk->clk.parent = srcs->sources[clksrc]; | ||
| 154 | |||
| 155 | if (announce) | ||
| 156 | printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", | ||
| 157 | clk->clk.name, clk->clk.parent->name, clksrc, | ||
| 158 | clk_get_rate(&clk->clk)); | ||
| 159 | } | ||
| 160 | |||
| 161 | static struct clk_ops clksrc_ops = { | ||
| 162 | .set_parent = s3c_setparent_clksrc, | ||
| 163 | .get_rate = s3c_getrate_clksrc, | ||
| 164 | .set_rate = s3c_setrate_clksrc, | ||
| 165 | .round_rate = s3c_roundrate_clksrc, | ||
| 166 | }; | ||
| 167 | |||
| 168 | static struct clk_ops clksrc_ops_nodiv = { | ||
| 169 | .set_parent = s3c_setparent_clksrc, | ||
| 170 | }; | ||
| 171 | |||
| 172 | static struct clk_ops clksrc_ops_nosrc = { | ||
| 173 | .get_rate = s3c_getrate_clksrc, | ||
| 174 | .set_rate = s3c_setrate_clksrc, | ||
| 175 | .round_rate = s3c_roundrate_clksrc, | ||
| 176 | }; | ||
| 177 | |||
| 178 | void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size) | ||
| 179 | { | ||
| 180 | int ret; | ||
| 181 | |||
| 182 | for (; size > 0; size--, clksrc++) { | ||
| 183 | if (!clksrc->reg_div.reg && !clksrc->reg_src.reg) | ||
| 184 | printk(KERN_ERR "%s: clock %s has no registers set\n", | ||
| 185 | __func__, clksrc->clk.name); | ||
| 186 | |||
| 187 | /* fill in the default functions */ | ||
| 188 | |||
| 189 | if (!clksrc->clk.ops) { | ||
| 190 | if (!clksrc->reg_div.reg) | ||
| 191 | clksrc->clk.ops = &clksrc_ops_nodiv; | ||
| 192 | else if (!clksrc->reg_src.reg) | ||
| 193 | clksrc->clk.ops = &clksrc_ops_nosrc; | ||
| 194 | else | ||
| 195 | clksrc->clk.ops = &clksrc_ops; | ||
| 196 | } | ||
| 197 | |||
| 198 | /* setup the clocksource, but do not announce it | ||
| 199 | * as it may be re-set by the setup routines | ||
| 200 | * called after the rest of the clocks have been | ||
| 201 | * registered | ||
| 202 | */ | ||
| 203 | s3c_set_clksrc(clksrc, false); | ||
| 204 | |||
| 205 | ret = s3c24xx_register_clock(&clksrc->clk); | ||
| 206 | |||
| 207 | if (ret < 0) { | ||
| 208 | printk(KERN_ERR "%s: failed to register %s (%d)\n", | ||
| 209 | __func__, clksrc->clk.name, ret); | ||
| 210 | } | ||
| 211 | } | ||
| 212 | } | ||
diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-samsung/clock.c index 619cfa82dcab..e9cdbe47beb6 100644 --- a/arch/arm/plat-s3c/clock.c +++ b/arch/arm/plat-samsung/clock.c | |||
| @@ -150,8 +150,8 @@ unsigned long clk_get_rate(struct clk *clk) | |||
| 150 | if (clk->rate != 0) | 150 | if (clk->rate != 0) |
| 151 | return clk->rate; | 151 | return clk->rate; |
| 152 | 152 | ||
| 153 | if (clk->get_rate != NULL) | 153 | if (clk->ops != NULL && clk->ops->get_rate != NULL) |
| 154 | return (clk->get_rate)(clk); | 154 | return (clk->ops->get_rate)(clk); |
| 155 | 155 | ||
| 156 | if (clk->parent != NULL) | 156 | if (clk->parent != NULL) |
| 157 | return clk_get_rate(clk->parent); | 157 | return clk_get_rate(clk->parent); |
| @@ -161,8 +161,8 @@ unsigned long clk_get_rate(struct clk *clk) | |||
| 161 | 161 | ||
| 162 | long clk_round_rate(struct clk *clk, unsigned long rate) | 162 | long clk_round_rate(struct clk *clk, unsigned long rate) |
| 163 | { | 163 | { |
| 164 | if (!IS_ERR(clk) && clk->round_rate) | 164 | if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate) |
| 165 | return (clk->round_rate)(clk, rate); | 165 | return (clk->ops->round_rate)(clk, rate); |
| 166 | 166 | ||
| 167 | return rate; | 167 | return rate; |
| 168 | } | 168 | } |
| @@ -178,13 +178,14 @@ int clk_set_rate(struct clk *clk, unsigned long rate) | |||
| 178 | * the clock may have been made this way by choice. | 178 | * the clock may have been made this way by choice. |
| 179 | */ | 179 | */ |
| 180 | 180 | ||
| 181 | WARN_ON(clk->set_rate == NULL); | 181 | WARN_ON(clk->ops == NULL); |
| 182 | WARN_ON(clk->ops && clk->ops->set_rate == NULL); | ||
| 182 | 183 | ||
| 183 | if (clk->set_rate == NULL) | 184 | if (clk->ops == NULL || clk->ops->set_rate == NULL) |
| 184 | return -EINVAL; | 185 | return -EINVAL; |
| 185 | 186 | ||
| 186 | spin_lock(&clocks_lock); | 187 | spin_lock(&clocks_lock); |
| 187 | ret = (clk->set_rate)(clk, rate); | 188 | ret = (clk->ops->set_rate)(clk, rate); |
| 188 | spin_unlock(&clocks_lock); | 189 | spin_unlock(&clocks_lock); |
| 189 | 190 | ||
| 190 | return ret; | 191 | return ret; |
| @@ -204,8 +205,8 @@ int clk_set_parent(struct clk *clk, struct clk *parent) | |||
| 204 | 205 | ||
| 205 | spin_lock(&clocks_lock); | 206 | spin_lock(&clocks_lock); |
| 206 | 207 | ||
| 207 | if (clk->set_parent) | 208 | if (clk->ops && clk->ops->set_parent) |
| 208 | ret = (clk->set_parent)(clk, parent); | 209 | ret = (clk->ops->set_parent)(clk, parent); |
| 209 | 210 | ||
| 210 | spin_unlock(&clocks_lock); | 211 | spin_unlock(&clocks_lock); |
| 211 | 212 | ||
| @@ -224,12 +225,16 @@ EXPORT_SYMBOL(clk_set_parent); | |||
| 224 | 225 | ||
| 225 | /* base clocks */ | 226 | /* base clocks */ |
| 226 | 227 | ||
| 227 | static int clk_default_setrate(struct clk *clk, unsigned long rate) | 228 | int clk_default_setrate(struct clk *clk, unsigned long rate) |
| 228 | { | 229 | { |
| 229 | clk->rate = rate; | 230 | clk->rate = rate; |
| 230 | return 0; | 231 | return 0; |
| 231 | } | 232 | } |
| 232 | 233 | ||
| 234 | struct clk_ops clk_ops_def_setrate = { | ||
| 235 | .set_rate = clk_default_setrate, | ||
| 236 | }; | ||
| 237 | |||
| 233 | struct clk clk_xtal = { | 238 | struct clk clk_xtal = { |
| 234 | .name = "xtal", | 239 | .name = "xtal", |
| 235 | .id = -1, | 240 | .id = -1, |
| @@ -251,7 +256,7 @@ struct clk clk_epll = { | |||
| 251 | struct clk clk_mpll = { | 256 | struct clk clk_mpll = { |
| 252 | .name = "mpll", | 257 | .name = "mpll", |
| 253 | .id = -1, | 258 | .id = -1, |
| 254 | .set_rate = clk_default_setrate, | 259 | .ops = &clk_ops_def_setrate, |
| 255 | }; | 260 | }; |
| 256 | 261 | ||
| 257 | struct clk clk_upll = { | 262 | struct clk clk_upll = { |
| @@ -267,7 +272,6 @@ struct clk clk_f = { | |||
| 267 | .rate = 0, | 272 | .rate = 0, |
| 268 | .parent = &clk_mpll, | 273 | .parent = &clk_mpll, |
| 269 | .ctrlbit = 0, | 274 | .ctrlbit = 0, |
| 270 | .set_rate = clk_default_setrate, | ||
| 271 | }; | 275 | }; |
| 272 | 276 | ||
| 273 | struct clk clk_h = { | 277 | struct clk clk_h = { |
| @@ -276,7 +280,7 @@ struct clk clk_h = { | |||
| 276 | .rate = 0, | 280 | .rate = 0, |
| 277 | .parent = NULL, | 281 | .parent = NULL, |
| 278 | .ctrlbit = 0, | 282 | .ctrlbit = 0, |
| 279 | .set_rate = clk_default_setrate, | 283 | .ops = &clk_ops_def_setrate, |
| 280 | }; | 284 | }; |
| 281 | 285 | ||
| 282 | struct clk clk_p = { | 286 | struct clk clk_p = { |
| @@ -285,7 +289,7 @@ struct clk clk_p = { | |||
| 285 | .rate = 0, | 289 | .rate = 0, |
| 286 | .parent = NULL, | 290 | .parent = NULL, |
| 287 | .ctrlbit = 0, | 291 | .ctrlbit = 0, |
| 288 | .set_rate = clk_default_setrate, | 292 | .ops = &clk_ops_def_setrate, |
| 289 | }; | 293 | }; |
| 290 | 294 | ||
| 291 | struct clk clk_usb_bus = { | 295 | struct clk clk_usb_bus = { |
| @@ -296,7 +300,6 @@ struct clk clk_usb_bus = { | |||
| 296 | }; | 300 | }; |
| 297 | 301 | ||
| 298 | 302 | ||
| 299 | |||
| 300 | struct clk s3c24xx_uclk = { | 303 | struct clk s3c24xx_uclk = { |
| 301 | .name = "uclk", | 304 | .name = "uclk", |
| 302 | .id = -1, | 305 | .id = -1, |
| @@ -333,6 +336,28 @@ int s3c24xx_register_clocks(struct clk **clks, int nr_clks) | |||
| 333 | return fails; | 336 | return fails; |
| 334 | } | 337 | } |
| 335 | 338 | ||
| 339 | /** | ||
| 340 | * s3c_register_clocks() - register an array of clocks | ||
| 341 | * @clkp: Pointer to the first clock in the array. | ||
| 342 | * @nr_clks: Number of clocks to register. | ||
| 343 | * | ||
| 344 | * Call s3c24xx_register_clock() on the @clkp array given, printing an | ||
| 345 | * error if it fails to register the clock (unlikely). | ||
| 346 | */ | ||
| 347 | void __init s3c_register_clocks(struct clk *clkp, int nr_clks) | ||
| 348 | { | ||
| 349 | int ret; | ||
| 350 | |||
| 351 | for (; nr_clks > 0; nr_clks--, clkp++) { | ||
| 352 | ret = s3c24xx_register_clock(clkp); | ||
| 353 | |||
| 354 | if (ret < 0) { | ||
| 355 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
| 356 | clkp->name, ret); | ||
| 357 | } | ||
| 358 | } | ||
| 359 | } | ||
| 360 | |||
| 336 | /* initalise all the clocks */ | 361 | /* initalise all the clocks */ |
| 337 | 362 | ||
| 338 | int __init s3c24xx_register_baseclocks(unsigned long xtal) | 363 | int __init s3c24xx_register_baseclocks(unsigned long xtal) |
diff --git a/arch/arm/plat-s3c/dev-fb.c b/arch/arm/plat-samsung/dev-fb.c index a90198fc4b0f..a90198fc4b0f 100644 --- a/arch/arm/plat-s3c/dev-fb.c +++ b/arch/arm/plat-samsung/dev-fb.c | |||
diff --git a/arch/arm/plat-s3c/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c index 4c05b39810e2..4c05b39810e2 100644 --- a/arch/arm/plat-s3c/dev-hsmmc.c +++ b/arch/arm/plat-samsung/dev-hsmmc.c | |||
diff --git a/arch/arm/plat-s3c/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c index e49bc4cd0ee6..e49bc4cd0ee6 100644 --- a/arch/arm/plat-s3c/dev-hsmmc1.c +++ b/arch/arm/plat-samsung/dev-hsmmc1.c | |||
diff --git a/arch/arm/plat-s3c/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c index 824580bc0e06..824580bc0e06 100644 --- a/arch/arm/plat-s3c/dev-hsmmc2.c +++ b/arch/arm/plat-samsung/dev-hsmmc2.c | |||
diff --git a/arch/arm/plat-s3c/dev-i2c0.c b/arch/arm/plat-samsung/dev-i2c0.c index 4c761529b949..4c761529b949 100644 --- a/arch/arm/plat-s3c/dev-i2c0.c +++ b/arch/arm/plat-samsung/dev-i2c0.c | |||
diff --git a/arch/arm/plat-s3c/dev-i2c1.c b/arch/arm/plat-samsung/dev-i2c1.c index d44f79110506..d44f79110506 100644 --- a/arch/arm/plat-s3c/dev-i2c1.c +++ b/arch/arm/plat-samsung/dev-i2c1.c | |||
diff --git a/arch/arm/plat-s3c/dev-nand.c b/arch/arm/plat-samsung/dev-nand.c index a52fb6cf618f..a52fb6cf618f 100644 --- a/arch/arm/plat-s3c/dev-nand.c +++ b/arch/arm/plat-samsung/dev-nand.c | |||
diff --git a/arch/arm/plat-samsung/dev-uart.c b/arch/arm/plat-samsung/dev-uart.c new file mode 100644 index 000000000000..3776cd952450 --- /dev/null +++ b/arch/arm/plat-samsung/dev-uart.c | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* linux/arch/arm/plat-samsung/dev-uart.c | ||
| 2 | * originally from arch/arm/plat-s3c24xx/devs.c | ||
| 3 | *x | ||
| 4 | * Copyright (c) 2004 Simtec Electronics | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * Base S3C24XX platform device definitions | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | |||
| 18 | /* uart devices */ | ||
| 19 | |||
| 20 | static struct platform_device s3c24xx_uart_device0 = { | ||
| 21 | .id = 0, | ||
| 22 | }; | ||
| 23 | |||
| 24 | static struct platform_device s3c24xx_uart_device1 = { | ||
| 25 | .id = 1, | ||
| 26 | }; | ||
| 27 | |||
| 28 | static struct platform_device s3c24xx_uart_device2 = { | ||
| 29 | .id = 2, | ||
| 30 | }; | ||
| 31 | |||
| 32 | static struct platform_device s3c24xx_uart_device3 = { | ||
| 33 | .id = 3, | ||
| 34 | }; | ||
| 35 | |||
| 36 | struct platform_device *s3c24xx_uart_src[4] = { | ||
| 37 | &s3c24xx_uart_device0, | ||
| 38 | &s3c24xx_uart_device1, | ||
| 39 | &s3c24xx_uart_device2, | ||
| 40 | &s3c24xx_uart_device3, | ||
| 41 | }; | ||
| 42 | |||
| 43 | struct platform_device *s3c24xx_uart_devs[4] = { | ||
| 44 | }; | ||
diff --git a/arch/arm/plat-s3c/dev-usb-hsotg.c b/arch/arm/plat-samsung/dev-usb-hsotg.c index e2f604b51c86..e2f604b51c86 100644 --- a/arch/arm/plat-s3c/dev-usb-hsotg.c +++ b/arch/arm/plat-samsung/dev-usb-hsotg.c | |||
diff --git a/arch/arm/plat-s3c/dev-usb.c b/arch/arm/plat-samsung/dev-usb.c index 2ee85abed6d9..88165657fa53 100644 --- a/arch/arm/plat-s3c/dev-usb.c +++ b/arch/arm/plat-samsung/dev-usb.c | |||
| @@ -19,7 +19,7 @@ | |||
| 19 | #include <mach/map.h> | 19 | #include <mach/map.h> |
| 20 | 20 | ||
| 21 | #include <plat/devs.h> | 21 | #include <plat/devs.h> |
| 22 | 22 | #include <plat/usb-control.h> | |
| 23 | 23 | ||
| 24 | static struct resource s3c_usb_resource[] = { | 24 | static struct resource s3c_usb_resource[] = { |
| 25 | [0] = { | 25 | [0] = { |
| @@ -36,7 +36,7 @@ static struct resource s3c_usb_resource[] = { | |||
| 36 | 36 | ||
| 37 | static u64 s3c_device_usb_dmamask = 0xffffffffUL; | 37 | static u64 s3c_device_usb_dmamask = 0xffffffffUL; |
| 38 | 38 | ||
| 39 | struct platform_device s3c_device_usb = { | 39 | struct platform_device s3c_device_ohci = { |
| 40 | .name = "s3c2410-ohci", | 40 | .name = "s3c2410-ohci", |
| 41 | .id = -1, | 41 | .id = -1, |
| 42 | .num_resources = ARRAY_SIZE(s3c_usb_resource), | 42 | .num_resources = ARRAY_SIZE(s3c_usb_resource), |
| @@ -47,4 +47,23 @@ struct platform_device s3c_device_usb = { | |||
| 47 | } | 47 | } |
| 48 | }; | 48 | }; |
| 49 | 49 | ||
| 50 | EXPORT_SYMBOL(s3c_device_usb); | 50 | EXPORT_SYMBOL(s3c_device_ohci); |
| 51 | |||
| 52 | /** | ||
| 53 | * s3c_ohci_set_platdata - initialise OHCI device platform data | ||
| 54 | * @info: The platform data. | ||
| 55 | * | ||
| 56 | * This call copies the @info passed in and sets the device .platform_data | ||
| 57 | * field to that copy. The @info is copied so that the original can be marked | ||
| 58 | * __initdata. | ||
| 59 | */ | ||
| 60 | void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info) | ||
| 61 | { | ||
| 62 | struct s3c2410_hcd_info *npd; | ||
| 63 | |||
| 64 | npd = kmemdup(info, sizeof(struct s3c2410_hcd_info), GFP_KERNEL); | ||
| 65 | if (!npd) | ||
| 66 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
| 67 | |||
| 68 | s3c_device_ohci.dev.platform_data = npd; | ||
| 69 | } | ||
diff --git a/arch/arm/plat-s3c/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c index 456969b6fa0d..44a84e896546 100644 --- a/arch/arm/plat-s3c/gpio-config.c +++ b/arch/arm/plat-samsung/gpio-config.c | |||
| @@ -17,7 +17,7 @@ | |||
| 17 | #include <linux/gpio.h> | 17 | #include <linux/gpio.h> |
| 18 | #include <linux/io.h> | 18 | #include <linux/io.h> |
| 19 | 19 | ||
| 20 | #include <mach/gpio-core.h> | 20 | #include <plat/gpio-core.h> |
| 21 | #include <plat/gpio-cfg.h> | 21 | #include <plat/gpio-cfg.h> |
| 22 | #include <plat/gpio-cfg-helpers.h> | 22 | #include <plat/gpio-cfg-helpers.h> |
| 23 | 23 | ||
diff --git a/arch/arm/plat-s3c/gpio.c b/arch/arm/plat-samsung/gpio.c index 5ff24e0f9f89..28d2ab8a08db 100644 --- a/arch/arm/plat-s3c/gpio.c +++ b/arch/arm/plat-samsung/gpio.c | |||
| @@ -16,7 +16,7 @@ | |||
| 16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
| 17 | #include <linux/gpio.h> | 17 | #include <linux/gpio.h> |
| 18 | 18 | ||
| 19 | #include <mach/gpio-core.h> | 19 | #include <plat/gpio-core.h> |
| 20 | 20 | ||
| 21 | #ifdef CONFIG_S3C_GPIO_TRACK | 21 | #ifdef CONFIG_S3C_GPIO_TRACK |
| 22 | struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; | 22 | struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; |
diff --git a/arch/arm/plat-samsung/gpiolib.c b/arch/arm/plat-samsung/gpiolib.c new file mode 100644 index 000000000000..8a8ba8bc1d96 --- /dev/null +++ b/arch/arm/plat-samsung/gpiolib.c | |||
| @@ -0,0 +1,199 @@ | |||
| 1 | /* arch/arm/plat-samsung/gpiolib.c | ||
| 2 | * | ||
| 3 | * Copyright 2008 Openmoko, Inc. | ||
| 4 | * Copyright 2008 Simtec Electronics | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * http://armlinux.simtec.co.uk/ | ||
| 7 | * | ||
| 8 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
| 9 | * http://www.samsung.com/ | ||
| 10 | * | ||
| 11 | * SAMSUNG - GPIOlib support | ||
| 12 | * | ||
| 13 | * This program is free software; you can redistribute it and/or modify | ||
| 14 | * it under the terms of the GNU General Public License version 2 as | ||
| 15 | * published by the Free Software Foundation. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include <linux/kernel.h> | ||
| 19 | #include <linux/irq.h> | ||
| 20 | #include <linux/io.h> | ||
| 21 | #include <mach/gpio.h> | ||
| 22 | #include <plat/gpio-core.h> | ||
| 23 | #include <plat/gpio-cfg.h> | ||
| 24 | #include <plat/gpio-cfg-helpers.h> | ||
| 25 | |||
| 26 | #ifndef DEBUG_GPIO | ||
| 27 | #define gpio_dbg(x...) do { } while (0) | ||
| 28 | #else | ||
| 29 | #define gpio_dbg(x...) printk(KERN_DEBUG x) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | /* The samsung_gpiolib_4bit routines are to control the gpio banks where | ||
| 33 | * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the | ||
| 34 | * following example: | ||
| 35 | * | ||
| 36 | * base + 0x00: Control register, 4 bits per gpio | ||
| 37 | * gpio n: 4 bits starting at (4*n) | ||
| 38 | * 0000 = input, 0001 = output, others mean special-function | ||
| 39 | * base + 0x04: Data register, 1 bit per gpio | ||
| 40 | * bit n: data bit n | ||
| 41 | * | ||
| 42 | * Note, since the data register is one bit per gpio and is at base + 0x4 | ||
| 43 | * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of | ||
| 44 | * the output. | ||
| 45 | */ | ||
| 46 | |||
| 47 | static int samsung_gpiolib_4bit_input(struct gpio_chip *chip, | ||
| 48 | unsigned int offset) | ||
| 49 | { | ||
| 50 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
| 51 | void __iomem *base = ourchip->base; | ||
| 52 | unsigned long con; | ||
| 53 | |||
| 54 | con = __raw_readl(base + GPIOCON_OFF); | ||
| 55 | con &= ~(0xf << con_4bit_shift(offset)); | ||
| 56 | __raw_writel(con, base + GPIOCON_OFF); | ||
| 57 | |||
| 58 | gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); | ||
| 59 | |||
| 60 | return 0; | ||
| 61 | } | ||
| 62 | |||
| 63 | static int samsung_gpiolib_4bit_output(struct gpio_chip *chip, | ||
| 64 | unsigned int offset, int value) | ||
| 65 | { | ||
| 66 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
| 67 | void __iomem *base = ourchip->base; | ||
| 68 | unsigned long con; | ||
| 69 | unsigned long dat; | ||
| 70 | |||
| 71 | con = __raw_readl(base + GPIOCON_OFF); | ||
| 72 | con &= ~(0xf << con_4bit_shift(offset)); | ||
| 73 | con |= 0x1 << con_4bit_shift(offset); | ||
| 74 | |||
| 75 | dat = __raw_readl(base + GPIODAT_OFF); | ||
| 76 | |||
| 77 | if (value) | ||
| 78 | dat |= 1 << offset; | ||
| 79 | else | ||
| 80 | dat &= ~(1 << offset); | ||
| 81 | |||
| 82 | __raw_writel(dat, base + GPIODAT_OFF); | ||
| 83 | __raw_writel(con, base + GPIOCON_OFF); | ||
| 84 | __raw_writel(dat, base + GPIODAT_OFF); | ||
| 85 | |||
| 86 | gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); | ||
| 87 | |||
| 88 | return 0; | ||
| 89 | } | ||
| 90 | |||
| 91 | /* The next set of routines are for the case where the GPIO configuration | ||
| 92 | * registers are 4 bits per GPIO but there is more than one register (the | ||
| 93 | * bank has more than 8 GPIOs. | ||
| 94 | * | ||
| 95 | * This case is the similar to the 4 bit case, but the registers are as | ||
| 96 | * follows: | ||
| 97 | * | ||
| 98 | * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) | ||
| 99 | * gpio n: 4 bits starting at (4*n) | ||
| 100 | * 0000 = input, 0001 = output, others mean special-function | ||
| 101 | * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) | ||
| 102 | * gpio n: 4 bits starting at (4*n) | ||
| 103 | * 0000 = input, 0001 = output, others mean special-function | ||
| 104 | * base + 0x08: Data register, 1 bit per gpio | ||
| 105 | * bit n: data bit n | ||
| 106 | * | ||
| 107 | * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we | ||
| 108 | * store the 'base + 0x4' address so that these routines see the data | ||
| 109 | * register at ourchip->base + 0x04. | ||
| 110 | */ | ||
| 111 | |||
| 112 | static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip, | ||
| 113 | unsigned int offset) | ||
| 114 | { | ||
| 115 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
| 116 | void __iomem *base = ourchip->base; | ||
| 117 | void __iomem *regcon = base; | ||
| 118 | unsigned long con; | ||
| 119 | |||
| 120 | if (offset > 7) | ||
| 121 | offset -= 8; | ||
| 122 | else | ||
| 123 | regcon -= 4; | ||
| 124 | |||
| 125 | con = __raw_readl(regcon); | ||
| 126 | con &= ~(0xf << con_4bit_shift(offset)); | ||
| 127 | __raw_writel(con, regcon); | ||
| 128 | |||
| 129 | gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); | ||
| 130 | |||
| 131 | return 0; | ||
| 132 | } | ||
| 133 | |||
| 134 | static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip, | ||
| 135 | unsigned int offset, int value) | ||
| 136 | { | ||
| 137 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
| 138 | void __iomem *base = ourchip->base; | ||
| 139 | void __iomem *regcon = base; | ||
| 140 | unsigned long con; | ||
| 141 | unsigned long dat; | ||
| 142 | unsigned con_offset = offset; | ||
| 143 | |||
| 144 | if (con_offset > 7) | ||
| 145 | con_offset -= 8; | ||
| 146 | else | ||
| 147 | regcon -= 4; | ||
| 148 | |||
| 149 | con = __raw_readl(regcon); | ||
| 150 | con &= ~(0xf << con_4bit_shift(con_offset)); | ||
| 151 | con |= 0x1 << con_4bit_shift(con_offset); | ||
| 152 | |||
| 153 | dat = __raw_readl(base + GPIODAT_OFF); | ||
| 154 | |||
| 155 | if (value) | ||
| 156 | dat |= 1 << offset; | ||
| 157 | else | ||
| 158 | dat &= ~(1 << offset); | ||
| 159 | |||
| 160 | __raw_writel(dat, base + GPIODAT_OFF); | ||
| 161 | __raw_writel(con, regcon); | ||
| 162 | __raw_writel(dat, base + GPIODAT_OFF); | ||
| 163 | |||
| 164 | gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); | ||
| 165 | |||
| 166 | return 0; | ||
| 167 | } | ||
| 168 | |||
| 169 | void __init samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip) | ||
| 170 | { | ||
| 171 | chip->chip.direction_input = samsung_gpiolib_4bit_input; | ||
| 172 | chip->chip.direction_output = samsung_gpiolib_4bit_output; | ||
| 173 | chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); | ||
| 174 | } | ||
| 175 | |||
| 176 | void __init samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) | ||
| 177 | { | ||
| 178 | chip->chip.direction_input = samsung_gpiolib_4bit2_input; | ||
| 179 | chip->chip.direction_output = samsung_gpiolib_4bit2_output; | ||
| 180 | chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); | ||
| 181 | } | ||
| 182 | |||
| 183 | void __init samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, | ||
| 184 | int nr_chips) | ||
| 185 | { | ||
| 186 | for (; nr_chips > 0; nr_chips--, chip++) { | ||
| 187 | samsung_gpiolib_add_4bit(chip); | ||
| 188 | s3c_gpiolib_add(chip); | ||
| 189 | } | ||
| 190 | } | ||
| 191 | |||
| 192 | void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, | ||
| 193 | int nr_chips) | ||
| 194 | { | ||
| 195 | for (; nr_chips > 0; nr_chips--, chip++) { | ||
| 196 | samsung_gpiolib_add_4bit2(chip); | ||
| 197 | s3c_gpiolib_add(chip); | ||
| 198 | } | ||
| 199 | } | ||
diff --git a/arch/arm/plat-s3c/include/plat/adc.h b/arch/arm/plat-samsung/include/plat/adc.h index 5f3b1cd53b90..e8382c7be10b 100644 --- a/arch/arm/plat-s3c/include/plat/adc.h +++ b/arch/arm/plat-samsung/include/plat/adc.h | |||
| @@ -1,10 +1,10 @@ | |||
| 1 | /* arch/arm/plat-s3c/include/plat/adc.h | 1 | /* arch/arm/plat-samsung/include/plat/adc.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2008 Simtec Electronics | 3 | * Copyright (c) 2008 Simtec Electronics |
| 4 | * http://armlinux.simnte.co.uk/ | 4 | * http://armlinux.simnte.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * | 6 | * |
| 7 | * S3C24XX ADC driver information | 7 | * S3C ADC driver information |
| 8 | * | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify | 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as | 10 | * it under the terms of the GNU General Public License version 2 as |
diff --git a/arch/arm/plat-samsung/include/plat/clock-clksrc.h b/arch/arm/plat-samsung/include/plat/clock-clksrc.h new file mode 100644 index 000000000000..50a8ca7c3760 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/clock-clksrc.h | |||
| @@ -0,0 +1,83 @@ | |||
| 1 | /* linux/arch/arm/plat-samsung/include/plat/clock-clksrc.h | ||
| 2 | * | ||
| 3 | * Parts taken from arch/arm/plat-s3c64xx/clock.c | ||
| 4 | * Copyright 2008 Openmoko, Inc. | ||
| 5 | * Copyright 2008 Simtec Electronics | ||
| 6 | * Ben Dooks <ben@simtec.co.uk> | ||
| 7 | * http://armlinux.simtec.co.uk/ | ||
| 8 | * | ||
| 9 | * Copyright 2009 Ben Dooks <ben-linux@fluff.org> | ||
| 10 | * Copyright 2009 Harald Welte | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | /** | ||
| 18 | * struct clksrc_sources - list of sources for a given clock | ||
| 19 | * @sources: array of pointers to clocks | ||
| 20 | * @nr_sources: The size of @sources | ||
| 21 | */ | ||
| 22 | struct clksrc_sources { | ||
| 23 | unsigned int nr_sources; | ||
| 24 | struct clk **sources; | ||
| 25 | }; | ||
| 26 | |||
| 27 | /** | ||
| 28 | * struct clksrc_reg - register definition for clock control bits | ||
| 29 | * @reg: pointer to the register in virtual memory. | ||
| 30 | * @shift: the shift in bits to where the bitfield is. | ||
| 31 | * @size: the size in bits of the bitfield. | ||
| 32 | * | ||
| 33 | * This specifies the size and position of the bits we are interested | ||
| 34 | * in within the register specified by @reg. | ||
| 35 | */ | ||
| 36 | struct clksrc_reg { | ||
| 37 | void __iomem *reg; | ||
| 38 | unsigned short shift; | ||
| 39 | unsigned short size; | ||
| 40 | }; | ||
| 41 | |||
| 42 | /** | ||
| 43 | * struct clksrc_clk - class of clock for newer style samsung devices. | ||
| 44 | * @clk: the standard clock representation | ||
| 45 | * @sources: the sources for this clock | ||
| 46 | * @reg_src: the register definition for selecting the clock's source | ||
| 47 | * @reg_div: the register definition for the clock's output divisor | ||
| 48 | * | ||
| 49 | * This clock implements the features required by the newer SoCs where | ||
| 50 | * the standard clock block provides an input mux and a post-mux divisor | ||
| 51 | * to provide the periperhal's clock. | ||
| 52 | * | ||
| 53 | * The array of @sources provides the mapping of mux position to the | ||
| 54 | * clock, and @reg_src shows the code where to modify to change the mux | ||
| 55 | * position. The @reg_div defines how to change the divider settings on | ||
| 56 | * the output. | ||
| 57 | */ | ||
| 58 | struct clksrc_clk { | ||
| 59 | struct clk clk; | ||
| 60 | struct clksrc_sources *sources; | ||
| 61 | |||
| 62 | struct clksrc_reg reg_src; | ||
| 63 | struct clksrc_reg reg_div; | ||
| 64 | }; | ||
| 65 | |||
| 66 | /** | ||
| 67 | * s3c_set_clksrc() - setup the clock from the register settings | ||
| 68 | * @clk: The clock to setup. | ||
| 69 | * @announce: true to announce the setting to printk(). | ||
| 70 | * | ||
| 71 | * Setup the clock from the current register settings, for when the | ||
| 72 | * kernel boots or if it is resuming from a possibly unknown state. | ||
| 73 | */ | ||
| 74 | extern void s3c_set_clksrc(struct clksrc_clk *clk, bool announce); | ||
| 75 | |||
| 76 | /** | ||
| 77 | * s3c_register_clksrc() register clocks from an array of clksrc clocks | ||
| 78 | * @srcs: The array of clocks to register | ||
| 79 | * @size: The size of the @srcs array. | ||
| 80 | * | ||
| 81 | * Initialise and register the array of clocks described by @srcs. | ||
| 82 | */ | ||
| 83 | extern void s3c_register_clksrc(struct clksrc_clk *srcs, int size); | ||
diff --git a/arch/arm/plat-s3c/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index d86af84b5b8c..ba9a1cdd3a28 100644 --- a/arch/arm/plat-s3c/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h | |||
| @@ -11,6 +11,30 @@ | |||
| 11 | 11 | ||
| 12 | #include <linux/spinlock.h> | 12 | #include <linux/spinlock.h> |
| 13 | 13 | ||
| 14 | struct clk; | ||
| 15 | |||
| 16 | /** | ||
| 17 | * struct clk_ops - standard clock operations | ||
| 18 | * @set_rate: set the clock rate, see clk_set_rate(). | ||
| 19 | * @get_rate: get the clock rate, see clk_get_rate(). | ||
| 20 | * @round_rate: round a given clock rate, see clk_round_rate(). | ||
| 21 | * @set_parent: set the clock's parent, see clk_set_parent(). | ||
| 22 | * | ||
| 23 | * Group the common clock implementations together so that we | ||
| 24 | * don't have to keep setting the same fiels again. We leave | ||
| 25 | * enable in struct clk. | ||
| 26 | * | ||
| 27 | * Adding an extra layer of indirection into the process should | ||
| 28 | * not be a problem as it is unlikely these operations are going | ||
| 29 | * to need to be called quickly. | ||
| 30 | */ | ||
| 31 | struct clk_ops { | ||
| 32 | int (*set_rate)(struct clk *c, unsigned long rate); | ||
| 33 | unsigned long (*get_rate)(struct clk *c); | ||
| 34 | unsigned long (*round_rate)(struct clk *c, unsigned long rate); | ||
| 35 | int (*set_parent)(struct clk *c, struct clk *parent); | ||
| 36 | }; | ||
| 37 | |||
| 14 | struct clk { | 38 | struct clk { |
| 15 | struct list_head list; | 39 | struct list_head list; |
| 16 | struct module *owner; | 40 | struct module *owner; |
| @@ -21,11 +45,8 @@ struct clk { | |||
| 21 | unsigned long rate; | 45 | unsigned long rate; |
| 22 | unsigned long ctrlbit; | 46 | unsigned long ctrlbit; |
| 23 | 47 | ||
| 48 | struct clk_ops *ops; | ||
| 24 | int (*enable)(struct clk *, int enable); | 49 | int (*enable)(struct clk *, int enable); |
| 25 | int (*set_rate)(struct clk *c, unsigned long rate); | ||
| 26 | unsigned long (*get_rate)(struct clk *c); | ||
| 27 | unsigned long (*round_rate)(struct clk *c, unsigned long rate); | ||
| 28 | int (*set_parent)(struct clk *c, struct clk *parent); | ||
| 29 | }; | 50 | }; |
| 30 | 51 | ||
| 31 | /* other clocks which may be registered by board support */ | 52 | /* other clocks which may be registered by board support */ |
| @@ -54,6 +75,9 @@ extern struct clk clk_h2; | |||
| 54 | extern struct clk clk_27m; | 75 | extern struct clk clk_27m; |
| 55 | extern struct clk clk_48m; | 76 | extern struct clk clk_48m; |
| 56 | 77 | ||
| 78 | extern int clk_default_setrate(struct clk *clk, unsigned long rate); | ||
| 79 | extern struct clk_ops clk_ops_def_setrate; | ||
| 80 | |||
| 57 | /* exports for arch/arm/mach-s3c2410 | 81 | /* exports for arch/arm/mach-s3c2410 |
| 58 | * | 82 | * |
| 59 | * Please DO NOT use these outside of arch/arm/mach-s3c2410 | 83 | * Please DO NOT use these outside of arch/arm/mach-s3c2410 |
| @@ -66,9 +90,12 @@ extern int s3c2410_clkcon_enable(struct clk *clk, int enable); | |||
| 66 | extern int s3c24xx_register_clock(struct clk *clk); | 90 | extern int s3c24xx_register_clock(struct clk *clk); |
| 67 | extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); | 91 | extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); |
| 68 | 92 | ||
| 93 | extern void s3c_register_clocks(struct clk *clk, int nr_clks); | ||
| 94 | |||
| 69 | extern int s3c24xx_register_baseclocks(unsigned long xtal); | 95 | extern int s3c24xx_register_baseclocks(unsigned long xtal); |
| 70 | 96 | ||
| 71 | extern void s3c64xx_register_clocks(void); | 97 | extern void s3c64xx_register_clocks(void); |
| 98 | extern void s5p_register_clocks(unsigned long xtal_freq); | ||
| 72 | 99 | ||
| 73 | extern void s3c24xx_setup_clocks(unsigned long fclk, | 100 | extern void s3c24xx_setup_clocks(unsigned long fclk, |
| 74 | unsigned long hclk, | 101 | unsigned long hclk, |
diff --git a/arch/arm/plat-s3c/include/plat/dma-core.h b/arch/arm/plat-samsung/include/plat/dma-core.h index 32ff2a92cb3c..32ff2a92cb3c 100644 --- a/arch/arm/plat-s3c/include/plat/dma-core.h +++ b/arch/arm/plat-samsung/include/plat/dma-core.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h index 652e2bbdaa20..652e2bbdaa20 100644 --- a/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h index 29cd6a86cade..29cd6a86cade 100644 --- a/arch/arm/plat-s3c/include/plat/gpio-cfg.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index 32af612767aa..49ff406a7066 100644 --- a/arch/arm/plat-s3c/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h | |||
| @@ -11,6 +11,11 @@ | |||
| 11 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | #define GPIOCON_OFF (0x00) | ||
| 15 | #define GPIODAT_OFF (0x04) | ||
| 16 | |||
| 17 | #define con_4bit_shift(__off) ((__off) * 4) | ||
| 18 | |||
| 14 | /* Define the core gpiolib support functions that the s3c platforms may | 19 | /* Define the core gpiolib support functions that the s3c platforms may |
| 15 | * need to extend or change depending on the hardware and the s3c chip | 20 | * need to extend or change depending on the hardware and the s3c chip |
| 16 | * selected at build or found at run time. | 21 | * selected at build or found at run time. |
| @@ -80,6 +85,29 @@ extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip); | |||
| 80 | * and any other necessary functions. | 85 | * and any other necessary functions. |
| 81 | */ | 86 | */ |
| 82 | 87 | ||
| 88 | /** | ||
| 89 | * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config. | ||
| 90 | * @chip: The gpio chip that is being configured. | ||
| 91 | * @nr_chips: The no of chips (gpio ports) for the GPIO being configured. | ||
| 92 | * | ||
| 93 | * This helper deal with the GPIO cases where the control register has 4 bits | ||
| 94 | * of control per GPIO, generally in the form of: | ||
| 95 | * 0000 = Input | ||
| 96 | * 0001 = Output | ||
| 97 | * others = Special functions (dependant on bank) | ||
| 98 | * | ||
| 99 | * Note, since the code to deal with the case where there are two control | ||
| 100 | * registers instead of one, we do not have a seperate set of function | ||
| 101 | * (samsung_gpiolib_add_4bit2_chips)for each case. | ||
| 102 | */ | ||
| 103 | extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, | ||
| 104 | int nr_chips); | ||
| 105 | extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, | ||
| 106 | int nr_chips); | ||
| 107 | |||
| 108 | extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip); | ||
| 109 | extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip); | ||
| 110 | |||
| 83 | #ifdef CONFIG_S3C_GPIO_TRACK | 111 | #ifdef CONFIG_S3C_GPIO_TRACK |
| 84 | extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; | 112 | extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; |
| 85 | 113 | ||
| @@ -90,6 +118,8 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip) | |||
| 90 | #else | 118 | #else |
| 91 | /* machine specific code should provide s3c_gpiolib_getchip */ | 119 | /* machine specific code should provide s3c_gpiolib_getchip */ |
| 92 | 120 | ||
| 121 | #include <mach/gpio-track.h> | ||
| 122 | |||
| 93 | static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } | 123 | static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } |
| 94 | #endif | 124 | #endif |
| 95 | 125 | ||
diff --git a/arch/arm/plat-s3c/include/plat/hwmon.h b/arch/arm/plat-samsung/include/plat/hwmon.h index 1ba88ea0aa31..1ba88ea0aa31 100644 --- a/arch/arm/plat-s3c/include/plat/hwmon.h +++ b/arch/arm/plat-samsung/include/plat/hwmon.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/iic-core.h b/arch/arm/plat-samsung/include/plat/iic-core.h index 36397ca20962..36397ca20962 100644 --- a/arch/arm/plat-s3c/include/plat/iic-core.h +++ b/arch/arm/plat-samsung/include/plat/iic-core.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h index 3083df00dee6..3083df00dee6 100644 --- a/arch/arm/plat-s3c/include/plat/iic.h +++ b/arch/arm/plat-samsung/include/plat/iic.h | |||
diff --git a/arch/arm/plat-samsung/include/plat/irq-uart.h b/arch/arm/plat-samsung/include/plat/irq-uart.h new file mode 100644 index 000000000000..a9331e49bea3 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/irq-uart.h | |||
| @@ -0,0 +1,20 @@ | |||
| 1 | /* arch/arm/plat-samsung/include/plat/irq-uart.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2010 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * Header file for Samsung SoC UART IRQ demux for S3C64XX and later | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | struct s3c_uart_irq { | ||
| 14 | void __iomem *regs; | ||
| 15 | unsigned int base_irq; | ||
| 16 | unsigned int parent_irq; | ||
| 17 | }; | ||
| 18 | |||
| 19 | extern void s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs); | ||
| 20 | |||
diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h new file mode 100644 index 000000000000..a90b53431b5b --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | /* arch/arm/plat-samsung/include/plat/irq-vic-timer.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2010 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * Header file for Samsung SoC IRQ VIC timer | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | extern void s3c_init_vic_timer_irq(unsigned int vic, unsigned int timer); | ||
diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-samsung/include/plat/nand.h index 226147b7e026..226147b7e026 100644 --- a/arch/arm/plat-s3c/include/plat/nand.h +++ b/arch/arm/plat-samsung/include/plat/nand.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/regs-ac97.h b/arch/arm/plat-samsung/include/plat/regs-ac97.h index c3878f7acb83..c3878f7acb83 100644 --- a/arch/arm/plat-s3c/include/plat/regs-ac97.h +++ b/arch/arm/plat-samsung/include/plat/regs-ac97.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h index 4323cccc86cd..f43c8dab39e4 100644 --- a/arch/arm/plat-s3c/include/plat/regs-adc.h +++ b/arch/arm/plat-samsung/include/plat/regs-adc.h | |||
| @@ -19,6 +19,9 @@ | |||
| 19 | #define S3C2410_ADCDLY S3C2410_ADCREG(0x08) | 19 | #define S3C2410_ADCDLY S3C2410_ADCREG(0x08) |
| 20 | #define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) | 20 | #define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) |
| 21 | #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) | 21 | #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) |
| 22 | #define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14) | ||
| 23 | #define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18) | ||
| 24 | #define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20) | ||
| 22 | 25 | ||
| 23 | 26 | ||
| 24 | /* ADCCON Register Bits */ | 27 | /* ADCCON Register Bits */ |
diff --git a/arch/arm/plat-s3c/include/plat/regs-iic.h b/arch/arm/plat-samsung/include/plat/regs-iic.h index 2f7c17de8ac8..2f7c17de8ac8 100644 --- a/arch/arm/plat-s3c/include/plat/regs-iic.h +++ b/arch/arm/plat-samsung/include/plat/regs-iic.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/regs-irqtype.h b/arch/arm/plat-samsung/include/plat/regs-irqtype.h index c63cd3fc5ad3..c63cd3fc5ad3 100644 --- a/arch/arm/plat-s3c/include/plat/regs-irqtype.h +++ b/arch/arm/plat-samsung/include/plat/regs-irqtype.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/regs-nand.h b/arch/arm/plat-samsung/include/plat/regs-nand.h index 238efea7b9e4..238efea7b9e4 100644 --- a/arch/arm/plat-s3c/include/plat/regs-nand.h +++ b/arch/arm/plat-samsung/include/plat/regs-nand.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h index d5837cf8e402..d5837cf8e402 100644 --- a/arch/arm/plat-s3c/include/plat/regs-rtc.h +++ b/arch/arm/plat-samsung/include/plat/regs-rtc.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h b/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h index abf2fbc2eb2f..abf2fbc2eb2f 100644 --- a/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h +++ b/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/regs-sdhci.h b/arch/arm/plat-samsung/include/plat/regs-sdhci.h index e34049ad44cc..e34049ad44cc 100644 --- a/arch/arm/plat-s3c/include/plat/regs-sdhci.h +++ b/arch/arm/plat-samsung/include/plat/regs-sdhci.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/regs-timer.h b/arch/arm/plat-samsung/include/plat/regs-timer.h index d097d92f8cc7..d097d92f8cc7 100644 --- a/arch/arm/plat-s3c/include/plat/regs-timer.h +++ b/arch/arm/plat-samsung/include/plat/regs-timer.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h index 36a85f5000c8..36a85f5000c8 100644 --- a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h +++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h index 8d18d9d4d148..8d18d9d4d148 100644 --- a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h +++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/regs-watchdog.h b/arch/arm/plat-samsung/include/plat/regs-watchdog.h index 4938492470f7..4938492470f7 100644 --- a/arch/arm/plat-s3c/include/plat/regs-watchdog.h +++ b/arch/arm/plat-samsung/include/plat/regs-watchdog.h | |||
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h new file mode 100644 index 000000000000..d17724149315 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | |||
| @@ -0,0 +1,67 @@ | |||
| 1 | /* linux/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2009 Samsung Electronics Ltd. | ||
| 4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __S3C64XX_PLAT_SPI_H | ||
| 12 | #define __S3C64XX_PLAT_SPI_H | ||
| 13 | |||
| 14 | /** | ||
| 15 | * struct s3c64xx_spi_csinfo - ChipSelect description | ||
| 16 | * @fb_delay: Slave specific feedback delay. | ||
| 17 | * Refer to FB_CLK_SEL register definition in SPI chapter. | ||
| 18 | * @line: Custom 'identity' of the CS line. | ||
| 19 | * @set_level: CS line control. | ||
| 20 | * | ||
| 21 | * This is per SPI-Slave Chipselect information. | ||
| 22 | * Allocate and initialize one in machine init code and make the | ||
| 23 | * spi_board_info.controller_data point to it. | ||
| 24 | */ | ||
| 25 | struct s3c64xx_spi_csinfo { | ||
| 26 | u8 fb_delay; | ||
| 27 | unsigned line; | ||
| 28 | void (*set_level)(unsigned line_id, int lvl); | ||
| 29 | }; | ||
| 30 | |||
| 31 | /** | ||
| 32 | * struct s3c64xx_spi_info - SPI Controller defining structure | ||
| 33 | * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. | ||
| 34 | * @src_clk_name: Platform name of the corresponding clock. | ||
| 35 | * @num_cs: Number of CS this controller emulates. | ||
| 36 | * @cfg_gpio: Configure pins for this SPI controller. | ||
| 37 | * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6 | ||
| 38 | * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number | ||
| 39 | * @high_speed: If the controller supports HIGH_SPEED_EN bit | ||
| 40 | */ | ||
| 41 | struct s3c64xx_spi_info { | ||
| 42 | int src_clk_nr; | ||
| 43 | char *src_clk_name; | ||
| 44 | |||
| 45 | int num_cs; | ||
| 46 | |||
| 47 | int (*cfg_gpio)(struct platform_device *pdev); | ||
| 48 | |||
| 49 | /* Following two fields are for future compatibility */ | ||
| 50 | int fifo_lvl_mask; | ||
| 51 | int rx_lvl_offset; | ||
| 52 | int high_speed; | ||
| 53 | }; | ||
| 54 | |||
| 55 | /** | ||
| 56 | * s3c64xx_spi_set_info - SPI Controller configure callback by the board | ||
| 57 | * initialization code. | ||
| 58 | * @cntrlr: SPI controller number the configuration is for. | ||
| 59 | * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. | ||
| 60 | * @num_cs: Number of elements in the 'cs' array. | ||
| 61 | * | ||
| 62 | * Call this from machine init code for each SPI Controller that | ||
| 63 | * has some chips attached to it. | ||
| 64 | */ | ||
| 65 | extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); | ||
| 66 | |||
| 67 | #endif /* __S3C64XX_PLAT_SPI_H */ | ||
diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 53198673b6bd..53198673b6bd 100644 --- a/arch/arm/plat-s3c/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/udc-hs.h b/arch/arm/plat-samsung/include/plat/udc-hs.h index dd04db043109..a22a4f2eea94 100644 --- a/arch/arm/plat-s3c/include/plat/udc-hs.h +++ b/arch/arm/plat-samsung/include/plat/udc-hs.h | |||
| @@ -12,7 +12,7 @@ | |||
| 12 | * published by the Free Software Foundation. | 12 | * published by the Free Software Foundation. |
| 13 | */ | 13 | */ |
| 14 | 14 | ||
| 15 | enum s3c_hostg_dmamode { | 15 | enum s3c_hsotg_dmamode { |
| 16 | S3C_HSOTG_DMA_NONE, /* do not use DMA at-all */ | 16 | S3C_HSOTG_DMA_NONE, /* do not use DMA at-all */ |
| 17 | S3C_HSOTG_DMA_ONLY, /* always use DMA */ | 17 | S3C_HSOTG_DMA_ONLY, /* always use DMA */ |
| 18 | S3C_HSOTG_DMA_DRV, /* DMA is chosen by driver */ | 18 | S3C_HSOTG_DMA_DRV, /* DMA is chosen by driver */ |
| @@ -24,6 +24,6 @@ enum s3c_hostg_dmamode { | |||
| 24 | * @is_osc: The clock source is an oscillator, not a crystal | 24 | * @is_osc: The clock source is an oscillator, not a crystal |
| 25 | */ | 25 | */ |
| 26 | struct s3c_hsotg_plat { | 26 | struct s3c_hsotg_plat { |
| 27 | enum s3c_hostg_dmamode dma; | 27 | enum s3c_hsotg_dmamode dma; |
| 28 | unsigned int is_osc : 1; | 28 | unsigned int is_osc : 1; |
| 29 | }; | 29 | }; |
diff --git a/arch/arm/plat-s3c/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h index 54b762acb5a0..54b762acb5a0 100644 --- a/arch/arm/plat-s3c/include/plat/watchdog-reset.h +++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h | |||
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c new file mode 100644 index 000000000000..4f8c102674ae --- /dev/null +++ b/arch/arm/plat-samsung/irq-uart.c | |||
| @@ -0,0 +1,143 @@ | |||
| 1 | /* arch/arm/plat-samsung/irq-uart.c | ||
| 2 | * originally part of arch/arm/plat-s3c64xx/irq.c | ||
| 3 | * | ||
| 4 | * Copyright 2008 Openmoko, Inc. | ||
| 5 | * Copyright 2008 Simtec Electronics | ||
| 6 | * Ben Dooks <ben@simtec.co.uk> | ||
| 7 | * http://armlinux.simtec.co.uk/ | ||
| 8 | * | ||
| 9 | * Samsung- UART Interrupt handling | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/interrupt.h> | ||
| 18 | #include <linux/serial_core.h> | ||
| 19 | #include <linux/irq.h> | ||
| 20 | #include <linux/io.h> | ||
| 21 | |||
| 22 | #include <mach/map.h> | ||
| 23 | #include <plat/irq-uart.h> | ||
| 24 | #include <plat/regs-serial.h> | ||
| 25 | #include <plat/cpu.h> | ||
| 26 | |||
| 27 | /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] | ||
| 28 | * are consecutive when looking up the interrupt in the demux routines. | ||
| 29 | */ | ||
| 30 | |||
| 31 | static inline void __iomem *s3c_irq_uart_base(unsigned int irq) | ||
| 32 | { | ||
| 33 | struct s3c_uart_irq *uirq = get_irq_chip_data(irq); | ||
| 34 | return uirq->regs; | ||
| 35 | } | ||
| 36 | |||
| 37 | static inline unsigned int s3c_irq_uart_bit(unsigned int irq) | ||
| 38 | { | ||
| 39 | return irq & 3; | ||
| 40 | } | ||
| 41 | |||
| 42 | static void s3c_irq_uart_mask(unsigned int irq) | ||
| 43 | { | ||
| 44 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
| 45 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
| 46 | u32 reg; | ||
| 47 | |||
| 48 | reg = __raw_readl(regs + S3C64XX_UINTM); | ||
| 49 | reg |= (1 << bit); | ||
| 50 | __raw_writel(reg, regs + S3C64XX_UINTM); | ||
| 51 | } | ||
| 52 | |||
| 53 | static void s3c_irq_uart_maskack(unsigned int irq) | ||
| 54 | { | ||
| 55 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
| 56 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
| 57 | u32 reg; | ||
| 58 | |||
| 59 | reg = __raw_readl(regs + S3C64XX_UINTM); | ||
| 60 | reg |= (1 << bit); | ||
| 61 | __raw_writel(reg, regs + S3C64XX_UINTM); | ||
| 62 | __raw_writel(1 << bit, regs + S3C64XX_UINTP); | ||
| 63 | } | ||
| 64 | |||
| 65 | static void s3c_irq_uart_unmask(unsigned int irq) | ||
| 66 | { | ||
| 67 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
| 68 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
| 69 | u32 reg; | ||
| 70 | |||
| 71 | reg = __raw_readl(regs + S3C64XX_UINTM); | ||
| 72 | reg &= ~(1 << bit); | ||
| 73 | __raw_writel(reg, regs + S3C64XX_UINTM); | ||
| 74 | } | ||
| 75 | |||
| 76 | static void s3c_irq_uart_ack(unsigned int irq) | ||
| 77 | { | ||
| 78 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
| 79 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
| 80 | |||
| 81 | __raw_writel(1 << bit, regs + S3C64XX_UINTP); | ||
| 82 | } | ||
| 83 | |||
| 84 | static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) | ||
| 85 | { | ||
| 86 | struct s3c_uart_irq *uirq = desc->handler_data; | ||
| 87 | u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); | ||
| 88 | int base = uirq->base_irq; | ||
| 89 | |||
| 90 | if (pend & (1 << 0)) | ||
| 91 | generic_handle_irq(base); | ||
| 92 | if (pend & (1 << 1)) | ||
| 93 | generic_handle_irq(base + 1); | ||
| 94 | if (pend & (1 << 2)) | ||
| 95 | generic_handle_irq(base + 2); | ||
| 96 | if (pend & (1 << 3)) | ||
| 97 | generic_handle_irq(base + 3); | ||
| 98 | } | ||
| 99 | |||
| 100 | static struct irq_chip s3c_irq_uart = { | ||
| 101 | .name = "s3c-uart", | ||
| 102 | .mask = s3c_irq_uart_mask, | ||
| 103 | .unmask = s3c_irq_uart_unmask, | ||
| 104 | .mask_ack = s3c_irq_uart_maskack, | ||
| 105 | .ack = s3c_irq_uart_ack, | ||
| 106 | }; | ||
| 107 | |||
| 108 | static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) | ||
| 109 | { | ||
| 110 | struct irq_desc *desc = irq_to_desc(uirq->parent_irq); | ||
| 111 | void __iomem *reg_base = uirq->regs; | ||
| 112 | unsigned int irq; | ||
| 113 | int offs; | ||
| 114 | |||
| 115 | /* mask all interrupts at the start. */ | ||
| 116 | __raw_writel(0xf, reg_base + S3C64XX_UINTM); | ||
| 117 | |||
| 118 | for (offs = 0; offs < 3; offs++) { | ||
| 119 | irq = uirq->base_irq + offs; | ||
| 120 | |||
| 121 | set_irq_chip(irq, &s3c_irq_uart); | ||
| 122 | set_irq_chip_data(irq, uirq); | ||
| 123 | set_irq_handler(irq, handle_level_irq); | ||
| 124 | set_irq_flags(irq, IRQF_VALID); | ||
| 125 | } | ||
| 126 | |||
| 127 | desc->handler_data = uirq; | ||
| 128 | set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); | ||
| 129 | } | ||
| 130 | |||
| 131 | /** | ||
| 132 | * s3c_init_uart_irqs() - initialise UART IRQs and the necessary demuxing | ||
| 133 | * @irq: The interrupt data for registering | ||
| 134 | * @nr_irqs: The number of interrupt descriptions in @irq. | ||
| 135 | * | ||
| 136 | * Register the UART interrupts specified by @irq including the demuxing | ||
| 137 | * routines. This supports the S3C6400 and newer style of devices. | ||
| 138 | */ | ||
| 139 | void __init s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs) | ||
| 140 | { | ||
| 141 | for (; nr_irqs > 0; nr_irqs--, irq++) | ||
| 142 | s3c_init_uart_irq(irq); | ||
| 143 | } | ||
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c new file mode 100644 index 000000000000..0270519fcabc --- /dev/null +++ b/arch/arm/plat-samsung/irq-vic-timer.c | |||
| @@ -0,0 +1,86 @@ | |||
| 1 | /* arch/arm/plat-samsung/irq-vic-timer.c | ||
| 2 | * originally part of arch/arm/plat-s3c64xx/irq.c | ||
| 3 | * | ||
| 4 | * Copyright 2008 Openmoko, Inc. | ||
| 5 | * Copyright 2008 Simtec Electronics | ||
| 6 | * Ben Dooks <ben@simtec.co.uk> | ||
| 7 | * http://armlinux.simtec.co.uk/ | ||
| 8 | * | ||
| 9 | * S3C64XX - Interrupt handling | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/interrupt.h> | ||
| 18 | #include <linux/irq.h> | ||
| 19 | #include <linux/io.h> | ||
| 20 | |||
| 21 | #include <mach/map.h> | ||
| 22 | #include <plat/irq-vic-timer.h> | ||
| 23 | #include <plat/regs-timer.h> | ||
| 24 | |||
| 25 | static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) | ||
| 26 | { | ||
| 27 | generic_handle_irq((int)desc->handler_data); | ||
| 28 | } | ||
| 29 | |||
| 30 | /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ | ||
| 31 | |||
| 32 | static void s3c_irq_timer_mask(unsigned int irq) | ||
| 33 | { | ||
| 34 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
| 35 | |||
| 36 | reg &= 0x1f; /* mask out pending interrupts */ | ||
| 37 | reg &= ~(1 << (irq - IRQ_TIMER0)); | ||
| 38 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
| 39 | } | ||
| 40 | |||
| 41 | static void s3c_irq_timer_unmask(unsigned int irq) | ||
| 42 | { | ||
| 43 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
| 44 | |||
| 45 | reg &= 0x1f; /* mask out pending interrupts */ | ||
| 46 | reg |= 1 << (irq - IRQ_TIMER0); | ||
| 47 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
| 48 | } | ||
| 49 | |||
| 50 | static void s3c_irq_timer_ack(unsigned int irq) | ||
| 51 | { | ||
| 52 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
| 53 | |||
| 54 | reg &= 0x1f; | ||
| 55 | reg |= (1 << 5) << (irq - IRQ_TIMER0); | ||
| 56 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
| 57 | } | ||
| 58 | |||
| 59 | static struct irq_chip s3c_irq_timer = { | ||
| 60 | .name = "s3c-timer", | ||
| 61 | .mask = s3c_irq_timer_mask, | ||
| 62 | .unmask = s3c_irq_timer_unmask, | ||
| 63 | .ack = s3c_irq_timer_ack, | ||
| 64 | }; | ||
| 65 | |||
| 66 | /** | ||
| 67 | * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\ | ||
| 68 | * @parent_irq: The parent IRQ on the VIC for the timer. | ||
| 69 | * @timer_irq: The IRQ to be used for the timer. | ||
| 70 | * | ||
| 71 | * Register the necessary IRQ chaining and support for the timer IRQs | ||
| 72 | * chained of the VIC. | ||
| 73 | */ | ||
| 74 | void __init s3c_init_vic_timer_irq(unsigned int parent_irq, | ||
| 75 | unsigned int timer_irq) | ||
| 76 | { | ||
| 77 | struct irq_desc *desc = irq_to_desc(parent_irq); | ||
| 78 | |||
| 79 | set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer); | ||
| 80 | |||
| 81 | set_irq_chip(timer_irq, &s3c_irq_timer); | ||
| 82 | set_irq_handler(timer_irq, handle_level_irq); | ||
| 83 | set_irq_flags(timer_irq, IRQF_VALID); | ||
| 84 | |||
| 85 | desc->handler_data = (void *)timer_irq; | ||
| 86 | } | ||
diff --git a/arch/arm/plat-s3c/pm-check.c b/arch/arm/plat-samsung/pm-check.c index 8eb1f439861c..0b5bb774192a 100644 --- a/arch/arm/plat-s3c/pm-check.c +++ b/arch/arm/plat-samsung/pm-check.c | |||
| @@ -20,8 +20,8 @@ | |||
| 20 | 20 | ||
| 21 | #include <plat/pm.h> | 21 | #include <plat/pm.h> |
| 22 | 22 | ||
| 23 | #if CONFIG_S3C2410_PM_CHECK_CHUNKSIZE < 1 | 23 | #if CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE < 1 |
| 24 | #error CONFIG_S3C2410_PM_CHECK_CHUNKSIZE must be a positive non-zero value | 24 | #error CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE must be a positive non-zero value |
| 25 | #endif | 25 | #endif |
| 26 | 26 | ||
| 27 | /* suspend checking code... | 27 | /* suspend checking code... |
| @@ -29,12 +29,12 @@ | |||
| 29 | * this next area does a set of crc checks over all the installed | 29 | * this next area does a set of crc checks over all the installed |
| 30 | * memory, so the system can verify if the resume was ok. | 30 | * memory, so the system can verify if the resume was ok. |
| 31 | * | 31 | * |
| 32 | * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, | 32 | * CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, |
| 33 | * increasing it will mean that the area corrupted will be less easy to spot, | 33 | * increasing it will mean that the area corrupted will be less easy to spot, |
| 34 | * and reducing the size will cause the CRC save area to grow | 34 | * and reducing the size will cause the CRC save area to grow |
| 35 | */ | 35 | */ |
| 36 | 36 | ||
| 37 | #define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024) | 37 | #define CHECK_CHUNKSIZE (CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE * 1024) |
| 38 | 38 | ||
| 39 | static u32 crc_size; /* size needed for the crc block */ | 39 | static u32 crc_size; /* size needed for the crc block */ |
| 40 | static u32 *crcs; /* allocated over suspend/resume */ | 40 | static u32 *crcs; /* allocated over suspend/resume */ |
diff --git a/arch/arm/plat-s3c/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index cfd326a8b693..69a4c7f02e25 100644 --- a/arch/arm/plat-s3c/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c | |||
| @@ -19,7 +19,7 @@ | |||
| 19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
| 20 | #include <linux/gpio.h> | 20 | #include <linux/gpio.h> |
| 21 | 21 | ||
| 22 | #include <mach/gpio-core.h> | 22 | #include <plat/gpio-core.h> |
| 23 | #include <plat/pm.h> | 23 | #include <plat/pm.h> |
| 24 | 24 | ||
| 25 | /* PM GPIO helpers */ | 25 | /* PM GPIO helpers */ |
diff --git a/arch/arm/plat-s3c/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c index a318215ab535..46c9381e083b 100644 --- a/arch/arm/plat-s3c/pwm-clock.c +++ b/arch/arm/plat-samsung/pwm-clock.c | |||
| @@ -130,20 +130,22 @@ static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate) | |||
| 130 | return 0; | 130 | return 0; |
| 131 | } | 131 | } |
| 132 | 132 | ||
| 133 | static struct clk_ops clk_pwm_scaler_ops = { | ||
| 134 | .get_rate = clk_pwm_scaler_get_rate, | ||
| 135 | .set_rate = clk_pwm_scaler_set_rate, | ||
| 136 | .round_rate = clk_pwm_scaler_round_rate, | ||
| 137 | }; | ||
| 138 | |||
| 133 | static struct clk clk_timer_scaler[] = { | 139 | static struct clk clk_timer_scaler[] = { |
| 134 | [0] = { | 140 | [0] = { |
| 135 | .name = "pwm-scaler0", | 141 | .name = "pwm-scaler0", |
| 136 | .id = -1, | 142 | .id = -1, |
| 137 | .get_rate = clk_pwm_scaler_get_rate, | 143 | .ops = &clk_pwm_scaler_ops, |
| 138 | .set_rate = clk_pwm_scaler_set_rate, | ||
| 139 | .round_rate = clk_pwm_scaler_round_rate, | ||
| 140 | }, | 144 | }, |
| 141 | [1] = { | 145 | [1] = { |
| 142 | .name = "pwm-scaler1", | 146 | .name = "pwm-scaler1", |
| 143 | .id = -1, | 147 | .id = -1, |
| 144 | .get_rate = clk_pwm_scaler_get_rate, | 148 | .ops = &clk_pwm_scaler_ops, |
| 145 | .set_rate = clk_pwm_scaler_set_rate, | ||
| 146 | .round_rate = clk_pwm_scaler_round_rate, | ||
| 147 | }, | 149 | }, |
| 148 | }; | 150 | }; |
| 149 | 151 | ||
| @@ -256,50 +258,46 @@ static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate) | |||
| 256 | return 0; | 258 | return 0; |
| 257 | } | 259 | } |
| 258 | 260 | ||
| 261 | static struct clk_ops clk_tdiv_ops = { | ||
| 262 | .get_rate = clk_pwm_tdiv_get_rate, | ||
| 263 | .set_rate = clk_pwm_tdiv_set_rate, | ||
| 264 | .round_rate = clk_pwm_tdiv_round_rate, | ||
| 265 | }; | ||
| 266 | |||
| 259 | static struct pwm_tdiv_clk clk_timer_tdiv[] = { | 267 | static struct pwm_tdiv_clk clk_timer_tdiv[] = { |
| 260 | [0] = { | 268 | [0] = { |
| 261 | .clk = { | 269 | .clk = { |
| 262 | .name = "pwm-tdiv", | 270 | .name = "pwm-tdiv", |
| 263 | .parent = &clk_timer_scaler[0], | 271 | .ops = &clk_tdiv_ops, |
| 264 | .get_rate = clk_pwm_tdiv_get_rate, | 272 | .parent = &clk_timer_scaler[0], |
| 265 | .set_rate = clk_pwm_tdiv_set_rate, | ||
| 266 | .round_rate = clk_pwm_tdiv_round_rate, | ||
| 267 | }, | 273 | }, |
| 268 | }, | 274 | }, |
| 269 | [1] = { | 275 | [1] = { |
| 270 | .clk = { | 276 | .clk = { |
| 271 | .name = "pwm-tdiv", | 277 | .name = "pwm-tdiv", |
| 272 | .parent = &clk_timer_scaler[0], | 278 | .ops = &clk_tdiv_ops, |
| 273 | .get_rate = clk_pwm_tdiv_get_rate, | 279 | .parent = &clk_timer_scaler[0], |
| 274 | .set_rate = clk_pwm_tdiv_set_rate, | ||
| 275 | .round_rate = clk_pwm_tdiv_round_rate, | ||
| 276 | } | 280 | } |
| 277 | }, | 281 | }, |
| 278 | [2] = { | 282 | [2] = { |
| 279 | .clk = { | 283 | .clk = { |
| 280 | .name = "pwm-tdiv", | 284 | .name = "pwm-tdiv", |
| 281 | .parent = &clk_timer_scaler[1], | 285 | .ops = &clk_tdiv_ops, |
| 282 | .get_rate = clk_pwm_tdiv_get_rate, | 286 | .parent = &clk_timer_scaler[1], |
| 283 | .set_rate = clk_pwm_tdiv_set_rate, | ||
| 284 | .round_rate = clk_pwm_tdiv_round_rate, | ||
| 285 | }, | 287 | }, |
| 286 | }, | 288 | }, |
| 287 | [3] = { | 289 | [3] = { |
| 288 | .clk = { | 290 | .clk = { |
| 289 | .name = "pwm-tdiv", | 291 | .name = "pwm-tdiv", |
| 290 | .parent = &clk_timer_scaler[1], | 292 | .ops = &clk_tdiv_ops, |
| 291 | .get_rate = clk_pwm_tdiv_get_rate, | 293 | .parent = &clk_timer_scaler[1], |
| 292 | .set_rate = clk_pwm_tdiv_set_rate, | ||
| 293 | .round_rate = clk_pwm_tdiv_round_rate, | ||
| 294 | }, | 294 | }, |
| 295 | }, | 295 | }, |
| 296 | [4] = { | 296 | [4] = { |
| 297 | .clk = { | 297 | .clk = { |
| 298 | .name = "pwm-tdiv", | 298 | .name = "pwm-tdiv", |
| 299 | .parent = &clk_timer_scaler[1], | 299 | .ops = &clk_tdiv_ops, |
| 300 | .get_rate = clk_pwm_tdiv_get_rate, | 300 | .parent = &clk_timer_scaler[1], |
| 301 | .set_rate = clk_pwm_tdiv_set_rate, | ||
| 302 | .round_rate = clk_pwm_tdiv_round_rate, | ||
| 303 | }, | 301 | }, |
| 304 | }, | 302 | }, |
| 305 | }; | 303 | }; |
| @@ -356,31 +354,35 @@ static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent) | |||
| 356 | return 0; | 354 | return 0; |
| 357 | } | 355 | } |
| 358 | 356 | ||
| 357 | static struct clk_ops clk_tin_ops = { | ||
| 358 | .set_parent = clk_pwm_tin_set_parent, | ||
| 359 | }; | ||
| 360 | |||
| 359 | static struct clk clk_tin[] = { | 361 | static struct clk clk_tin[] = { |
| 360 | [0] = { | 362 | [0] = { |
| 361 | .name = "pwm-tin", | 363 | .name = "pwm-tin", |
| 362 | .id = 0, | 364 | .id = 0, |
| 363 | .set_parent = clk_pwm_tin_set_parent, | 365 | .ops = &clk_tin_ops, |
| 364 | }, | 366 | }, |
| 365 | [1] = { | 367 | [1] = { |
| 366 | .name = "pwm-tin", | 368 | .name = "pwm-tin", |
| 367 | .id = 1, | 369 | .id = 1, |
| 368 | .set_parent = clk_pwm_tin_set_parent, | 370 | .ops = &clk_tin_ops, |
| 369 | }, | 371 | }, |
| 370 | [2] = { | 372 | [2] = { |
| 371 | .name = "pwm-tin", | 373 | .name = "pwm-tin", |
| 372 | .id = 2, | 374 | .id = 2, |
| 373 | .set_parent = clk_pwm_tin_set_parent, | 375 | .ops = &clk_tin_ops, |
| 374 | }, | 376 | }, |
| 375 | [3] = { | 377 | [3] = { |
| 376 | .name = "pwm-tin", | 378 | .name = "pwm-tin", |
| 377 | .id = 3, | 379 | .id = 3, |
| 378 | .set_parent = clk_pwm_tin_set_parent, | 380 | .ops = &clk_tin_ops, |
| 379 | }, | 381 | }, |
| 380 | [4] = { | 382 | [4] = { |
| 381 | .name = "pwm-tin", | 383 | .name = "pwm-tin", |
| 382 | .id = 4, | 384 | .id = 4, |
| 383 | .set_parent = clk_pwm_tin_set_parent, | 385 | .ops = &clk_tin_ops, |
| 384 | }, | 386 | }, |
| 385 | }; | 387 | }; |
| 386 | 388 | ||
| @@ -428,25 +430,15 @@ __init void s3c_pwmclk_init(void) | |||
| 428 | return; | 430 | return; |
| 429 | } | 431 | } |
| 430 | 432 | ||
| 431 | for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) { | 433 | for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) |
| 432 | clk_timer_scaler[clk].parent = clk_timers; | 434 | clk_timer_scaler[clk].parent = clk_timers; |
| 433 | ret = s3c24xx_register_clock(&clk_timer_scaler[clk]); | ||
| 434 | if (ret < 0) { | ||
| 435 | printk(KERN_ERR "error adding pwm scaler%d clock\n", clk); | ||
| 436 | return; | ||
| 437 | } | ||
| 438 | } | ||
| 439 | 435 | ||
| 440 | for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) { | 436 | s3c_register_clocks(clk_timer_scaler, ARRAY_SIZE(clk_timer_scaler)); |
| 441 | ret = s3c24xx_register_clock(&clk_timer_tclk[clk]); | 437 | s3c_register_clocks(clk_timer_tclk, ARRAY_SIZE(clk_timer_tclk)); |
| 442 | if (ret < 0) { | ||
| 443 | printk(KERN_ERR "error adding pww tclk%d\n", clk); | ||
| 444 | return; | ||
| 445 | } | ||
| 446 | } | ||
| 447 | 438 | ||
| 448 | for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) { | 439 | for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) { |
| 449 | ret = clk_pwm_tdiv_register(clk); | 440 | ret = clk_pwm_tdiv_register(clk); |
| 441 | |||
| 450 | if (ret < 0) { | 442 | if (ret < 0) { |
| 451 | printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk); | 443 | printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk); |
| 452 | return; | 444 | return; |
diff --git a/arch/arm/plat-s3c/pwm.c b/arch/arm/plat-samsung/pwm.c index ef019f27b67d..ef019f27b67d 100644 --- a/arch/arm/plat-s3c/pwm.c +++ b/arch/arm/plat-samsung/pwm.c | |||